1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
37 /* Check assumptions made in this file. */
38 typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1];
39 typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1];
42 #define DBG(x) printf x
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug = -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr = FALSE;
86 int mips_flag_pdr = TRUE;
91 static char *mips_regmask_frag;
98 #define PIC_CALL_REG 25
106 #define ILLEGAL_REG (32)
108 #define AT mips_opts.at
110 extern int target_big_endian;
112 /* The name of the readonly data section. */
113 #define RDATA_SECTION_NAME ".rodata"
115 /* Ways in which an instruction can be "appended" to the output. */
117 /* Just add it normally. */
120 /* Add it normally and then add a nop. */
123 /* Turn an instruction with a delay slot into a "compact" version. */
126 /* Insert the instruction before the last one. */
130 /* Information about an instruction, including its format, operands
134 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
135 const struct mips_opcode *insn_mo;
137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
138 a copy of INSN_MO->match with the operands filled in. If we have
139 decided to use an extended MIPS16 instruction, this includes the
141 unsigned long insn_opcode;
143 /* The frag that contains the instruction. */
146 /* The offset into FRAG of the first instruction byte. */
149 /* The relocs associated with the instruction, if any. */
152 /* True if this entry cannot be moved from its current position. */
153 unsigned int fixed_p : 1;
155 /* True if this instruction occurred in a .set noreorder block. */
156 unsigned int noreorder_p : 1;
158 /* True for mips16 instructions that jump to an absolute address. */
159 unsigned int mips16_absolute_jump_p : 1;
161 /* True if this instruction is complete. */
162 unsigned int complete_p : 1;
164 /* True if this instruction is cleared from history by unconditional
166 unsigned int cleared_p : 1;
169 /* The ABI to use. */
180 /* MIPS ABI we are using for this output file. */
181 static enum mips_abi_level mips_abi = NO_ABI;
183 /* Whether or not we have code that can call pic code. */
184 int mips_abicalls = FALSE;
186 /* Whether or not we have code which can be put into a shared
188 static bfd_boolean mips_in_shared = TRUE;
190 /* This is the set of options which may be modified by the .set
191 pseudo-op. We use a struct so that .set push and .set pop are more
194 struct mips_set_options
196 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
197 if it has not been initialized. Changed by `.set mipsN', and the
198 -mipsN command line option, and the default CPU. */
200 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
201 <asename>', by command line options, and based on the default
204 /* Whether we are assembling for the mips16 processor. 0 if we are
205 not, 1 if we are, and -1 if the value has not been initialized.
206 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
207 -nomips16 command line options, and the default CPU. */
209 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
210 1 if we are, and -1 if the value has not been initialized. Changed
211 by `.set micromips' and `.set nomicromips', and the -mmicromips
212 and -mno-micromips command line options, and the default CPU. */
214 /* Non-zero if we should not reorder instructions. Changed by `.set
215 reorder' and `.set noreorder'. */
217 /* Non-zero if we should not permit the register designated "assembler
218 temporary" to be used in instructions. The value is the register
219 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
220 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
222 /* Non-zero if we should warn when a macro instruction expands into
223 more than one machine instruction. Changed by `.set nomacro' and
225 int warn_about_macros;
226 /* Non-zero if we should not move instructions. Changed by `.set
227 move', `.set volatile', `.set nomove', and `.set novolatile'. */
229 /* Non-zero if we should not optimize branches by moving the target
230 of the branch into the delay slot. Actually, we don't perform
231 this optimization anyhow. Changed by `.set bopt' and `.set
234 /* Non-zero if we should not autoextend mips16 instructions.
235 Changed by `.set autoextend' and `.set noautoextend'. */
237 /* True if we should only emit 32-bit microMIPS instructions.
238 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
239 and -mno-insn32 command line options. */
241 /* Restrict general purpose registers and floating point registers
242 to 32 bit. This is initially determined when -mgp32 or -mfp32
243 is passed but can changed if the assembler code uses .set mipsN. */
246 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
247 command line option, and the default CPU. */
249 /* True if ".set sym32" is in effect. */
251 /* True if floating-point operations are not allowed. Changed by .set
252 softfloat or .set hardfloat, by command line options -msoft-float or
253 -mhard-float. The default is false. */
254 bfd_boolean soft_float;
256 /* True if only single-precision floating-point operations are allowed.
257 Changed by .set singlefloat or .set doublefloat, command-line options
258 -msingle-float or -mdouble-float. The default is false. */
259 bfd_boolean single_float;
262 /* This is the struct we use to hold the current set of options. Note
263 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
264 -1 to indicate that they have not been initialized. */
266 /* True if -mgp32 was passed. */
267 static int file_mips_gp32 = -1;
269 /* True if -mfp32 was passed. */
270 static int file_mips_fp32 = -1;
272 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
273 static int file_mips_soft_float = 0;
275 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
276 static int file_mips_single_float = 0;
278 /* True if -mnan=2008, false if -mnan=legacy. */
279 static bfd_boolean mips_flag_nan2008 = FALSE;
281 static struct mips_set_options mips_opts =
283 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
284 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
285 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
286 /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
287 /* soft_float */ FALSE, /* single_float */ FALSE
290 /* The set of ASEs that were selected on the command line, either
291 explicitly via ASE options or implicitly through things like -march. */
292 static unsigned int file_ase;
294 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
295 static unsigned int file_ase_explicit;
297 /* These variables are filled in with the masks of registers used.
298 The object format code reads them and puts them in the appropriate
300 unsigned long mips_gprmask;
301 unsigned long mips_cprmask[4];
303 /* MIPS ISA we are using for this output file. */
304 static int file_mips_isa = ISA_UNKNOWN;
306 /* True if any MIPS16 code was produced. */
307 static int file_ase_mips16;
309 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
310 || mips_opts.isa == ISA_MIPS32R2 \
311 || mips_opts.isa == ISA_MIPS64 \
312 || mips_opts.isa == ISA_MIPS64R2)
314 /* True if any microMIPS code was produced. */
315 static int file_ase_micromips;
317 /* True if we want to create R_MIPS_JALR for jalr $25. */
319 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
321 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
322 because there's no place for any addend, the only acceptable
323 expression is a bare symbol. */
324 #define MIPS_JALR_HINT_P(EXPR) \
325 (!HAVE_IN_PLACE_ADDENDS \
326 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
329 /* The argument of the -march= flag. The architecture we are assembling. */
330 static int file_mips_arch = CPU_UNKNOWN;
331 static const char *mips_arch_string;
333 /* The argument of the -mtune= flag. The architecture for which we
335 static int mips_tune = CPU_UNKNOWN;
336 static const char *mips_tune_string;
338 /* True when generating 32-bit code for a 64-bit processor. */
339 static int mips_32bitmode = 0;
341 /* True if the given ABI requires 32-bit registers. */
342 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
344 /* Likewise 64-bit registers. */
345 #define ABI_NEEDS_64BIT_REGS(ABI) \
347 || (ABI) == N64_ABI \
350 /* Return true if ISA supports 64 bit wide gp registers. */
351 #define ISA_HAS_64BIT_REGS(ISA) \
352 ((ISA) == ISA_MIPS3 \
353 || (ISA) == ISA_MIPS4 \
354 || (ISA) == ISA_MIPS5 \
355 || (ISA) == ISA_MIPS64 \
356 || (ISA) == ISA_MIPS64R2)
358 /* Return true if ISA supports 64 bit wide float registers. */
359 #define ISA_HAS_64BIT_FPRS(ISA) \
360 ((ISA) == ISA_MIPS3 \
361 || (ISA) == ISA_MIPS4 \
362 || (ISA) == ISA_MIPS5 \
363 || (ISA) == ISA_MIPS32R2 \
364 || (ISA) == ISA_MIPS64 \
365 || (ISA) == ISA_MIPS64R2)
367 /* Return true if ISA supports 64-bit right rotate (dror et al.)
369 #define ISA_HAS_DROR(ISA) \
370 ((ISA) == ISA_MIPS64R2 \
371 || (mips_opts.micromips \
372 && ISA_HAS_64BIT_REGS (ISA)) \
375 /* Return true if ISA supports 32-bit right rotate (ror et al.)
377 #define ISA_HAS_ROR(ISA) \
378 ((ISA) == ISA_MIPS32R2 \
379 || (ISA) == ISA_MIPS64R2 \
380 || (mips_opts.ase & ASE_SMARTMIPS) \
381 || mips_opts.micromips \
384 /* Return true if ISA supports single-precision floats in odd registers. */
385 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
386 ((ISA) == ISA_MIPS32 \
387 || (ISA) == ISA_MIPS32R2 \
388 || (ISA) == ISA_MIPS64 \
389 || (ISA) == ISA_MIPS64R2)
391 /* Return true if ISA supports move to/from high part of a 64-bit
392 floating-point register. */
393 #define ISA_HAS_MXHC1(ISA) \
394 ((ISA) == ISA_MIPS32R2 \
395 || (ISA) == ISA_MIPS64R2)
397 #define HAVE_32BIT_GPRS \
398 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
400 #define HAVE_32BIT_FPRS \
401 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
403 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
404 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
406 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
408 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
410 /* True if relocations are stored in-place. */
411 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
413 /* The ABI-derived address size. */
414 #define HAVE_64BIT_ADDRESSES \
415 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
416 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
418 /* The size of symbolic constants (i.e., expressions of the form
419 "SYMBOL" or "SYMBOL + OFFSET"). */
420 #define HAVE_32BIT_SYMBOLS \
421 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
422 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
424 /* Addresses are loaded in different ways, depending on the address size
425 in use. The n32 ABI Documentation also mandates the use of additions
426 with overflow checking, but existing implementations don't follow it. */
427 #define ADDRESS_ADD_INSN \
428 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
430 #define ADDRESS_ADDI_INSN \
431 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
433 #define ADDRESS_LOAD_INSN \
434 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
436 #define ADDRESS_STORE_INSN \
437 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
439 /* Return true if the given CPU supports the MIPS16 ASE. */
440 #define CPU_HAS_MIPS16(cpu) \
441 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
442 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
444 /* Return true if the given CPU supports the microMIPS ASE. */
445 #define CPU_HAS_MICROMIPS(cpu) 0
447 /* True if CPU has a dror instruction. */
448 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
450 /* True if CPU has a ror instruction. */
451 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
453 /* True if CPU is in the Octeon family */
454 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
456 /* True if CPU has seq/sne and seqi/snei instructions. */
457 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
459 /* True, if CPU has support for ldc1 and sdc1. */
460 #define CPU_HAS_LDC1_SDC1(CPU) \
461 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
463 /* True if mflo and mfhi can be immediately followed by instructions
464 which write to the HI and LO registers.
466 According to MIPS specifications, MIPS ISAs I, II, and III need
467 (at least) two instructions between the reads of HI/LO and
468 instructions which write them, and later ISAs do not. Contradicting
469 the MIPS specifications, some MIPS IV processor user manuals (e.g.
470 the UM for the NEC Vr5000) document needing the instructions between
471 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
472 MIPS64 and later ISAs to have the interlocks, plus any specific
473 earlier-ISA CPUs for which CPU documentation declares that the
474 instructions are really interlocked. */
475 #define hilo_interlocks \
476 (mips_opts.isa == ISA_MIPS32 \
477 || mips_opts.isa == ISA_MIPS32R2 \
478 || mips_opts.isa == ISA_MIPS64 \
479 || mips_opts.isa == ISA_MIPS64R2 \
480 || mips_opts.arch == CPU_R4010 \
481 || mips_opts.arch == CPU_R5900 \
482 || mips_opts.arch == CPU_R10000 \
483 || mips_opts.arch == CPU_R12000 \
484 || mips_opts.arch == CPU_R14000 \
485 || mips_opts.arch == CPU_R16000 \
486 || mips_opts.arch == CPU_RM7000 \
487 || mips_opts.arch == CPU_VR5500 \
488 || mips_opts.micromips \
491 /* Whether the processor uses hardware interlocks to protect reads
492 from the GPRs after they are loaded from memory, and thus does not
493 require nops to be inserted. This applies to instructions marked
494 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
495 level I and microMIPS mode instructions are always interlocked. */
496 #define gpr_interlocks \
497 (mips_opts.isa != ISA_MIPS1 \
498 || mips_opts.arch == CPU_R3900 \
499 || mips_opts.arch == CPU_R5900 \
500 || mips_opts.micromips \
503 /* Whether the processor uses hardware interlocks to avoid delays
504 required by coprocessor instructions, and thus does not require
505 nops to be inserted. This applies to instructions marked
506 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
507 between instructions marked INSN_WRITE_COND_CODE and ones marked
508 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
509 levels I, II, and III and microMIPS mode instructions are always
511 /* Itbl support may require additional care here. */
512 #define cop_interlocks \
513 ((mips_opts.isa != ISA_MIPS1 \
514 && mips_opts.isa != ISA_MIPS2 \
515 && mips_opts.isa != ISA_MIPS3) \
516 || mips_opts.arch == CPU_R4300 \
517 || mips_opts.micromips \
520 /* Whether the processor uses hardware interlocks to protect reads
521 from coprocessor registers after they are loaded from memory, and
522 thus does not require nops to be inserted. This applies to
523 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
524 requires at MIPS ISA level I and microMIPS mode instructions are
525 always interlocked. */
526 #define cop_mem_interlocks \
527 (mips_opts.isa != ISA_MIPS1 \
528 || mips_opts.micromips \
531 /* Is this a mfhi or mflo instruction? */
532 #define MF_HILO_INSN(PINFO) \
533 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
535 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
536 has been selected. This implies, in particular, that addresses of text
537 labels have their LSB set. */
538 #define HAVE_CODE_COMPRESSION \
539 ((mips_opts.mips16 | mips_opts.micromips) != 0)
541 /* The minimum and maximum signed values that can be stored in a GPR. */
542 #define GPR_SMAX ((offsetT) (((valueT) 1 << (HAVE_64BIT_GPRS ? 63 : 31)) - 1))
543 #define GPR_SMIN (-GPR_SMAX - 1)
545 /* MIPS PIC level. */
547 enum mips_pic_level mips_pic;
549 /* 1 if we should generate 32 bit offsets from the $gp register in
550 SVR4_PIC mode. Currently has no meaning in other modes. */
551 static int mips_big_got = 0;
553 /* 1 if trap instructions should used for overflow rather than break
555 static int mips_trap = 0;
557 /* 1 if double width floating point constants should not be constructed
558 by assembling two single width halves into two single width floating
559 point registers which just happen to alias the double width destination
560 register. On some architectures this aliasing can be disabled by a bit
561 in the status register, and the setting of this bit cannot be determined
562 automatically at assemble time. */
563 static int mips_disable_float_construction;
565 /* Non-zero if any .set noreorder directives were used. */
567 static int mips_any_noreorder;
569 /* Non-zero if nops should be inserted when the register referenced in
570 an mfhi/mflo instruction is read in the next two instructions. */
571 static int mips_7000_hilo_fix;
573 /* The size of objects in the small data section. */
574 static unsigned int g_switch_value = 8;
575 /* Whether the -G option was used. */
576 static int g_switch_seen = 0;
581 /* If we can determine in advance that GP optimization won't be
582 possible, we can skip the relaxation stuff that tries to produce
583 GP-relative references. This makes delay slot optimization work
586 This function can only provide a guess, but it seems to work for
587 gcc output. It needs to guess right for gcc, otherwise gcc
588 will put what it thinks is a GP-relative instruction in a branch
591 I don't know if a fix is needed for the SVR4_PIC mode. I've only
592 fixed it for the non-PIC mode. KR 95/04/07 */
593 static int nopic_need_relax (symbolS *, int);
595 /* handle of the OPCODE hash table */
596 static struct hash_control *op_hash = NULL;
598 /* The opcode hash table we use for the mips16. */
599 static struct hash_control *mips16_op_hash = NULL;
601 /* The opcode hash table we use for the microMIPS ASE. */
602 static struct hash_control *micromips_op_hash = NULL;
604 /* This array holds the chars that always start a comment. If the
605 pre-processor is disabled, these aren't very useful */
606 const char comment_chars[] = "#";
608 /* This array holds the chars that only start a comment at the beginning of
609 a line. If the line seems to have the form '# 123 filename'
610 .line and .file directives will appear in the pre-processed output */
611 /* Note that input_file.c hand checks for '#' at the beginning of the
612 first line of the input file. This is because the compiler outputs
613 #NO_APP at the beginning of its output. */
614 /* Also note that C style comments are always supported. */
615 const char line_comment_chars[] = "#";
617 /* This array holds machine specific line separator characters. */
618 const char line_separator_chars[] = ";";
620 /* Chars that can be used to separate mant from exp in floating point nums */
621 const char EXP_CHARS[] = "eE";
623 /* Chars that mean this number is a floating point constant */
626 const char FLT_CHARS[] = "rRsSfFdDxXpP";
628 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
629 changed in read.c . Ideally it shouldn't have to know about it at all,
630 but nothing is ideal around here.
633 static char *insn_error;
635 static int auto_align = 1;
637 /* When outputting SVR4 PIC code, the assembler needs to know the
638 offset in the stack frame from which to restore the $gp register.
639 This is set by the .cprestore pseudo-op, and saved in this
641 static offsetT mips_cprestore_offset = -1;
643 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
644 more optimizations, it can use a register value instead of a memory-saved
645 offset and even an other register than $gp as global pointer. */
646 static offsetT mips_cpreturn_offset = -1;
647 static int mips_cpreturn_register = -1;
648 static int mips_gp_register = GP;
649 static int mips_gprel_offset = 0;
651 /* Whether mips_cprestore_offset has been set in the current function
652 (or whether it has already been warned about, if not). */
653 static int mips_cprestore_valid = 0;
655 /* This is the register which holds the stack frame, as set by the
656 .frame pseudo-op. This is needed to implement .cprestore. */
657 static int mips_frame_reg = SP;
659 /* Whether mips_frame_reg has been set in the current function
660 (or whether it has already been warned about, if not). */
661 static int mips_frame_reg_valid = 0;
663 /* To output NOP instructions correctly, we need to keep information
664 about the previous two instructions. */
666 /* Whether we are optimizing. The default value of 2 means to remove
667 unneeded NOPs and swap branch instructions when possible. A value
668 of 1 means to not swap branches. A value of 0 means to always
670 static int mips_optimize = 2;
672 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
673 equivalent to seeing no -g option at all. */
674 static int mips_debug = 0;
676 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
677 #define MAX_VR4130_NOPS 4
679 /* The maximum number of NOPs needed to fill delay slots. */
680 #define MAX_DELAY_NOPS 2
682 /* The maximum number of NOPs needed for any purpose. */
685 /* A list of previous instructions, with index 0 being the most recent.
686 We need to look back MAX_NOPS instructions when filling delay slots
687 or working around processor errata. We need to look back one
688 instruction further if we're thinking about using history[0] to
689 fill a branch delay slot. */
690 static struct mips_cl_insn history[1 + MAX_NOPS];
692 /* Arrays of operands for each instruction. */
693 #define MAX_OPERANDS 5
694 struct mips_operand_array {
695 const struct mips_operand *operand[MAX_OPERANDS];
697 static struct mips_operand_array *mips_operands;
698 static struct mips_operand_array *mips16_operands;
699 static struct mips_operand_array *micromips_operands;
701 /* Nop instructions used by emit_nop. */
702 static struct mips_cl_insn nop_insn;
703 static struct mips_cl_insn mips16_nop_insn;
704 static struct mips_cl_insn micromips_nop16_insn;
705 static struct mips_cl_insn micromips_nop32_insn;
707 /* The appropriate nop for the current mode. */
708 #define NOP_INSN (mips_opts.mips16 \
710 : (mips_opts.micromips \
711 ? (mips_opts.insn32 \
712 ? µmips_nop32_insn \
713 : µmips_nop16_insn) \
716 /* The size of NOP_INSN in bytes. */
717 #define NOP_INSN_SIZE ((mips_opts.mips16 \
718 || (mips_opts.micromips && !mips_opts.insn32)) \
721 /* If this is set, it points to a frag holding nop instructions which
722 were inserted before the start of a noreorder section. If those
723 nops turn out to be unnecessary, the size of the frag can be
725 static fragS *prev_nop_frag;
727 /* The number of nop instructions we created in prev_nop_frag. */
728 static int prev_nop_frag_holds;
730 /* The number of nop instructions that we know we need in
732 static int prev_nop_frag_required;
734 /* The number of instructions we've seen since prev_nop_frag. */
735 static int prev_nop_frag_since;
737 /* Relocations against symbols are sometimes done in two parts, with a HI
738 relocation and a LO relocation. Each relocation has only 16 bits of
739 space to store an addend. This means that in order for the linker to
740 handle carries correctly, it must be able to locate both the HI and
741 the LO relocation. This means that the relocations must appear in
742 order in the relocation table.
744 In order to implement this, we keep track of each unmatched HI
745 relocation. We then sort them so that they immediately precede the
746 corresponding LO relocation. */
751 struct mips_hi_fixup *next;
754 /* The section this fixup is in. */
758 /* The list of unmatched HI relocs. */
760 static struct mips_hi_fixup *mips_hi_fixup_list;
762 /* The frag containing the last explicit relocation operator.
763 Null if explicit relocations have not been used. */
765 static fragS *prev_reloc_op_frag;
767 /* Map mips16 register numbers to normal MIPS register numbers. */
769 static const unsigned int mips16_to_32_reg_map[] =
771 16, 17, 2, 3, 4, 5, 6, 7
774 /* Map microMIPS register numbers to normal MIPS register numbers. */
776 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
778 /* The microMIPS registers with type h. */
779 static const unsigned int micromips_to_32_reg_h_map1[] =
781 5, 5, 6, 4, 4, 4, 4, 4
783 static const unsigned int micromips_to_32_reg_h_map2[] =
785 6, 7, 7, 21, 22, 5, 6, 7
788 /* The microMIPS registers with type m. */
789 static const unsigned int micromips_to_32_reg_m_map[] =
791 0, 17, 2, 3, 16, 18, 19, 20
794 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
796 /* Classifies the kind of instructions we're interested in when
797 implementing -mfix-vr4120. */
798 enum fix_vr4120_class
806 NUM_FIX_VR4120_CLASSES
809 /* ...likewise -mfix-loongson2f-jump. */
810 static bfd_boolean mips_fix_loongson2f_jump;
812 /* ...likewise -mfix-loongson2f-nop. */
813 static bfd_boolean mips_fix_loongson2f_nop;
815 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
816 static bfd_boolean mips_fix_loongson2f;
818 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
819 there must be at least one other instruction between an instruction
820 of type X and an instruction of type Y. */
821 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
823 /* True if -mfix-vr4120 is in force. */
824 static int mips_fix_vr4120;
826 /* ...likewise -mfix-vr4130. */
827 static int mips_fix_vr4130;
829 /* ...likewise -mfix-24k. */
830 static int mips_fix_24k;
832 /* ...likewise -mfix-cn63xxp1 */
833 static bfd_boolean mips_fix_cn63xxp1;
835 /* We don't relax branches by default, since this causes us to expand
836 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
837 fail to compute the offset before expanding the macro to the most
838 efficient expansion. */
840 static int mips_relax_branch;
842 /* The expansion of many macros depends on the type of symbol that
843 they refer to. For example, when generating position-dependent code,
844 a macro that refers to a symbol may have two different expansions,
845 one which uses GP-relative addresses and one which uses absolute
846 addresses. When generating SVR4-style PIC, a macro may have
847 different expansions for local and global symbols.
849 We handle these situations by generating both sequences and putting
850 them in variant frags. In position-dependent code, the first sequence
851 will be the GP-relative one and the second sequence will be the
852 absolute one. In SVR4 PIC, the first sequence will be for global
853 symbols and the second will be for local symbols.
855 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
856 SECOND are the lengths of the two sequences in bytes. These fields
857 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
858 the subtype has the following flags:
861 Set if it has been decided that we should use the second
862 sequence instead of the first.
865 Set in the first variant frag if the macro's second implementation
866 is longer than its first. This refers to the macro as a whole,
867 not an individual relaxation.
870 Set in the first variant frag if the macro appeared in a .set nomacro
871 block and if one alternative requires a warning but the other does not.
874 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
877 RELAX_DELAY_SLOT_16BIT
878 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
881 RELAX_DELAY_SLOT_SIZE_FIRST
882 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
883 the macro is of the wrong size for the branch delay slot.
885 RELAX_DELAY_SLOT_SIZE_SECOND
886 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
887 the macro is of the wrong size for the branch delay slot.
889 The frag's "opcode" points to the first fixup for relaxable code.
891 Relaxable macros are generated using a sequence such as:
893 relax_start (SYMBOL);
894 ... generate first expansion ...
896 ... generate second expansion ...
899 The code and fixups for the unwanted alternative are discarded
900 by md_convert_frag. */
901 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
903 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
904 #define RELAX_SECOND(X) ((X) & 0xff)
905 #define RELAX_USE_SECOND 0x10000
906 #define RELAX_SECOND_LONGER 0x20000
907 #define RELAX_NOMACRO 0x40000
908 #define RELAX_DELAY_SLOT 0x80000
909 #define RELAX_DELAY_SLOT_16BIT 0x100000
910 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
911 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
913 /* Branch without likely bit. If label is out of range, we turn:
915 beq reg1, reg2, label
925 with the following opcode replacements:
932 bltzal <-> bgezal (with jal label instead of j label)
934 Even though keeping the delay slot instruction in the delay slot of
935 the branch would be more efficient, it would be very tricky to do
936 correctly, because we'd have to introduce a variable frag *after*
937 the delay slot instruction, and expand that instead. Let's do it
938 the easy way for now, even if the branch-not-taken case now costs
939 one additional instruction. Out-of-range branches are not supposed
940 to be common, anyway.
942 Branch likely. If label is out of range, we turn:
944 beql reg1, reg2, label
945 delay slot (annulled if branch not taken)
954 delay slot (executed only if branch taken)
957 It would be possible to generate a shorter sequence by losing the
958 likely bit, generating something like:
963 delay slot (executed only if branch taken)
975 bltzall -> bgezal (with jal label instead of j label)
976 bgezall -> bltzal (ditto)
979 but it's not clear that it would actually improve performance. */
980 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
984 | ((toofar) ? 0x20 : 0) \
985 | ((link) ? 0x40 : 0) \
986 | ((likely) ? 0x80 : 0) \
987 | ((uncond) ? 0x100 : 0)))
988 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
989 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
990 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
991 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
992 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
993 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
995 /* For mips16 code, we use an entirely different form of relaxation.
996 mips16 supports two versions of most instructions which take
997 immediate values: a small one which takes some small value, and a
998 larger one which takes a 16 bit value. Since branches also follow
999 this pattern, relaxing these values is required.
1001 We can assemble both mips16 and normal MIPS code in a single
1002 object. Therefore, we need to support this type of relaxation at
1003 the same time that we support the relaxation described above. We
1004 use the high bit of the subtype field to distinguish these cases.
1006 The information we store for this type of relaxation is the
1007 argument code found in the opcode file for this relocation, whether
1008 the user explicitly requested a small or extended form, and whether
1009 the relocation is in a jump or jal delay slot. That tells us the
1010 size of the value, and how it should be stored. We also store
1011 whether the fragment is considered to be extended or not. We also
1012 store whether this is known to be a branch to a different section,
1013 whether we have tried to relax this frag yet, and whether we have
1014 ever extended a PC relative fragment because of a shift count. */
1015 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1018 | ((small) ? 0x100 : 0) \
1019 | ((ext) ? 0x200 : 0) \
1020 | ((dslot) ? 0x400 : 0) \
1021 | ((jal_dslot) ? 0x800 : 0))
1022 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1023 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1024 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1025 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1026 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1027 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1028 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1029 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1030 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1031 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1032 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1033 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1035 /* For microMIPS code, we use relaxation similar to one we use for
1036 MIPS16 code. Some instructions that take immediate values support
1037 two encodings: a small one which takes some small value, and a
1038 larger one which takes a 16 bit value. As some branches also follow
1039 this pattern, relaxing these values is required.
1041 We can assemble both microMIPS and normal MIPS code in a single
1042 object. Therefore, we need to support this type of relaxation at
1043 the same time that we support the relaxation described above. We
1044 use one of the high bits of the subtype field to distinguish these
1047 The information we store for this type of relaxation is the argument
1048 code found in the opcode file for this relocation, the register
1049 selected as the assembler temporary, whether the branch is
1050 unconditional, whether it is compact, whether it stores the link
1051 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1052 branches to a sequence of instructions is enabled, and whether the
1053 displacement of a branch is too large to fit as an immediate argument
1054 of a 16-bit and a 32-bit branch, respectively. */
1055 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1056 relax32, toofar16, toofar32) \
1059 | (((at) & 0x1f) << 8) \
1060 | ((uncond) ? 0x2000 : 0) \
1061 | ((compact) ? 0x4000 : 0) \
1062 | ((link) ? 0x8000 : 0) \
1063 | ((relax32) ? 0x10000 : 0) \
1064 | ((toofar16) ? 0x20000 : 0) \
1065 | ((toofar32) ? 0x40000 : 0))
1066 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1067 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1068 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1069 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1070 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1071 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1072 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1074 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1075 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1076 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1077 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1078 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1079 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1081 /* Sign-extend 16-bit value X. */
1082 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1084 /* Is the given value a sign-extended 32-bit value? */
1085 #define IS_SEXT_32BIT_NUM(x) \
1086 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1087 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1089 /* Is the given value a sign-extended 16-bit value? */
1090 #define IS_SEXT_16BIT_NUM(x) \
1091 (((x) &~ (offsetT) 0x7fff) == 0 \
1092 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1094 /* Is the given value a sign-extended 12-bit value? */
1095 #define IS_SEXT_12BIT_NUM(x) \
1096 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1098 /* Is the given value a sign-extended 9-bit value? */
1099 #define IS_SEXT_9BIT_NUM(x) \
1100 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1102 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1103 #define IS_ZEXT_32BIT_NUM(x) \
1104 (((x) &~ (offsetT) 0xffffffff) == 0 \
1105 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1107 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1109 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1110 (((STRUCT) >> (SHIFT)) & (MASK))
1112 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1113 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1115 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1116 : EXTRACT_BITS ((INSN).insn_opcode, \
1117 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1118 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1119 EXTRACT_BITS ((INSN).insn_opcode, \
1120 MIPS16OP_MASK_##FIELD, \
1121 MIPS16OP_SH_##FIELD)
1123 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1124 #define MIPS16_EXTEND (0xf000U << 16)
1126 /* Whether or not we are emitting a branch-likely macro. */
1127 static bfd_boolean emit_branch_likely_macro = FALSE;
1129 /* Global variables used when generating relaxable macros. See the
1130 comment above RELAX_ENCODE for more details about how relaxation
1133 /* 0 if we're not emitting a relaxable macro.
1134 1 if we're emitting the first of the two relaxation alternatives.
1135 2 if we're emitting the second alternative. */
1138 /* The first relaxable fixup in the current frag. (In other words,
1139 the first fixup that refers to relaxable code.) */
1142 /* sizes[0] says how many bytes of the first alternative are stored in
1143 the current frag. Likewise sizes[1] for the second alternative. */
1144 unsigned int sizes[2];
1146 /* The symbol on which the choice of sequence depends. */
1150 /* Global variables used to decide whether a macro needs a warning. */
1152 /* True if the macro is in a branch delay slot. */
1153 bfd_boolean delay_slot_p;
1155 /* Set to the length in bytes required if the macro is in a delay slot
1156 that requires a specific length of instruction, otherwise zero. */
1157 unsigned int delay_slot_length;
1159 /* For relaxable macros, sizes[0] is the length of the first alternative
1160 in bytes and sizes[1] is the length of the second alternative.
1161 For non-relaxable macros, both elements give the length of the
1163 unsigned int sizes[2];
1165 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1166 instruction of the first alternative in bytes and first_insn_sizes[1]
1167 is the length of the first instruction of the second alternative.
1168 For non-relaxable macros, both elements give the length of the first
1169 instruction in bytes.
1171 Set to zero if we haven't yet seen the first instruction. */
1172 unsigned int first_insn_sizes[2];
1174 /* For relaxable macros, insns[0] is the number of instructions for the
1175 first alternative and insns[1] is the number of instructions for the
1178 For non-relaxable macros, both elements give the number of
1179 instructions for the macro. */
1180 unsigned int insns[2];
1182 /* The first variant frag for this macro. */
1184 } mips_macro_warning;
1186 /* Prototypes for static functions. */
1188 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1190 static void append_insn
1191 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1192 bfd_boolean expansionp);
1193 static void mips_no_prev_insn (void);
1194 static void macro_build (expressionS *, const char *, const char *, ...);
1195 static void mips16_macro_build
1196 (expressionS *, const char *, const char *, va_list *);
1197 static void load_register (int, expressionS *, int);
1198 static void macro_start (void);
1199 static void macro_end (void);
1200 static void macro (struct mips_cl_insn *ip, char *str);
1201 static void mips16_macro (struct mips_cl_insn * ip);
1202 static void mips_ip (char *str, struct mips_cl_insn * ip);
1203 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1204 static void mips16_immed
1205 (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT,
1206 unsigned int, unsigned long *);
1207 static size_t my_getSmallExpression
1208 (expressionS *, bfd_reloc_code_real_type *, char *);
1209 static void my_getExpression (expressionS *, char *);
1210 static void s_align (int);
1211 static void s_change_sec (int);
1212 static void s_change_section (int);
1213 static void s_cons (int);
1214 static void s_float_cons (int);
1215 static void s_mips_globl (int);
1216 static void s_option (int);
1217 static void s_mipsset (int);
1218 static void s_abicalls (int);
1219 static void s_cpload (int);
1220 static void s_cpsetup (int);
1221 static void s_cplocal (int);
1222 static void s_cprestore (int);
1223 static void s_cpreturn (int);
1224 static void s_dtprelword (int);
1225 static void s_dtpreldword (int);
1226 static void s_tprelword (int);
1227 static void s_tpreldword (int);
1228 static void s_gpvalue (int);
1229 static void s_gpword (int);
1230 static void s_gpdword (int);
1231 static void s_ehword (int);
1232 static void s_cpadd (int);
1233 static void s_insn (int);
1234 static void s_nan (int);
1235 static void md_obj_begin (void);
1236 static void md_obj_end (void);
1237 static void s_mips_ent (int);
1238 static void s_mips_end (int);
1239 static void s_mips_frame (int);
1240 static void s_mips_mask (int reg_type);
1241 static void s_mips_stab (int);
1242 static void s_mips_weakext (int);
1243 static void s_mips_file (int);
1244 static void s_mips_loc (int);
1245 static bfd_boolean pic_need_relax (symbolS *, asection *);
1246 static int relaxed_branch_length (fragS *, asection *, int);
1247 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1248 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1250 /* Table and functions used to map between CPU/ISA names, and
1251 ISA levels, and CPU numbers. */
1253 struct mips_cpu_info
1255 const char *name; /* CPU or ISA name. */
1256 int flags; /* MIPS_CPU_* flags. */
1257 int ase; /* Set of ASEs implemented by the CPU. */
1258 int isa; /* ISA level. */
1259 int cpu; /* CPU number (default CPU if ISA). */
1262 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1264 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1265 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1266 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1268 /* Command-line options. */
1269 const char *md_shortopts = "O::g::G:";
1273 OPTION_MARCH = OPTION_MD_BASE,
1297 OPTION_NO_SMARTMIPS,
1303 OPTION_NO_MICROMIPS,
1306 OPTION_COMPAT_ARCH_BASE,
1315 OPTION_M7000_HILO_FIX,
1316 OPTION_MNO_7000_HILO_FIX,
1319 OPTION_FIX_LOONGSON2F_JUMP,
1320 OPTION_NO_FIX_LOONGSON2F_JUMP,
1321 OPTION_FIX_LOONGSON2F_NOP,
1322 OPTION_NO_FIX_LOONGSON2F_NOP,
1324 OPTION_NO_FIX_VR4120,
1326 OPTION_NO_FIX_VR4130,
1327 OPTION_FIX_CN63XXP1,
1328 OPTION_NO_FIX_CN63XXP1,
1335 OPTION_CONSTRUCT_FLOATS,
1336 OPTION_NO_CONSTRUCT_FLOATS,
1339 OPTION_RELAX_BRANCH,
1340 OPTION_NO_RELAX_BRANCH,
1349 OPTION_SINGLE_FLOAT,
1350 OPTION_DOUBLE_FLOAT,
1363 OPTION_MVXWORKS_PIC,
1368 struct option md_longopts[] =
1370 /* Options which specify architecture. */
1371 {"march", required_argument, NULL, OPTION_MARCH},
1372 {"mtune", required_argument, NULL, OPTION_MTUNE},
1373 {"mips0", no_argument, NULL, OPTION_MIPS1},
1374 {"mips1", no_argument, NULL, OPTION_MIPS1},
1375 {"mips2", no_argument, NULL, OPTION_MIPS2},
1376 {"mips3", no_argument, NULL, OPTION_MIPS3},
1377 {"mips4", no_argument, NULL, OPTION_MIPS4},
1378 {"mips5", no_argument, NULL, OPTION_MIPS5},
1379 {"mips32", no_argument, NULL, OPTION_MIPS32},
1380 {"mips64", no_argument, NULL, OPTION_MIPS64},
1381 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
1382 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
1384 /* Options which specify Application Specific Extensions (ASEs). */
1385 {"mips16", no_argument, NULL, OPTION_MIPS16},
1386 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
1387 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
1388 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
1389 {"mdmx", no_argument, NULL, OPTION_MDMX},
1390 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
1391 {"mdsp", no_argument, NULL, OPTION_DSP},
1392 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
1393 {"mmt", no_argument, NULL, OPTION_MT},
1394 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
1395 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
1396 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
1397 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
1398 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
1399 {"meva", no_argument, NULL, OPTION_EVA},
1400 {"mno-eva", no_argument, NULL, OPTION_NO_EVA},
1401 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
1402 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
1403 {"mmcu", no_argument, NULL, OPTION_MCU},
1404 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
1405 {"mvirt", no_argument, NULL, OPTION_VIRT},
1406 {"mno-virt", no_argument, NULL, OPTION_NO_VIRT},
1408 /* Old-style architecture options. Don't add more of these. */
1409 {"m4650", no_argument, NULL, OPTION_M4650},
1410 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
1411 {"m4010", no_argument, NULL, OPTION_M4010},
1412 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
1413 {"m4100", no_argument, NULL, OPTION_M4100},
1414 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
1415 {"m3900", no_argument, NULL, OPTION_M3900},
1416 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
1418 /* Options which enable bug fixes. */
1419 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
1420 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1421 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1422 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
1423 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
1424 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
1425 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
1426 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
1427 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
1428 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
1429 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
1430 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
1431 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
1432 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
1433 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
1435 /* Miscellaneous options. */
1436 {"trap", no_argument, NULL, OPTION_TRAP},
1437 {"no-break", no_argument, NULL, OPTION_TRAP},
1438 {"break", no_argument, NULL, OPTION_BREAK},
1439 {"no-trap", no_argument, NULL, OPTION_BREAK},
1440 {"EB", no_argument, NULL, OPTION_EB},
1441 {"EL", no_argument, NULL, OPTION_EL},
1442 {"mfp32", no_argument, NULL, OPTION_FP32},
1443 {"mgp32", no_argument, NULL, OPTION_GP32},
1444 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
1445 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
1446 {"mfp64", no_argument, NULL, OPTION_FP64},
1447 {"mgp64", no_argument, NULL, OPTION_GP64},
1448 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
1449 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
1450 {"minsn32", no_argument, NULL, OPTION_INSN32},
1451 {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32},
1452 {"mshared", no_argument, NULL, OPTION_MSHARED},
1453 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
1454 {"msym32", no_argument, NULL, OPTION_MSYM32},
1455 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
1456 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
1457 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
1458 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
1459 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
1461 /* Strictly speaking this next option is ELF specific,
1462 but we allow it for other ports as well in order to
1463 make testing easier. */
1464 {"32", no_argument, NULL, OPTION_32},
1466 /* ELF-specific options. */
1467 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
1468 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
1469 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
1470 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
1471 {"xgot", no_argument, NULL, OPTION_XGOT},
1472 {"mabi", required_argument, NULL, OPTION_MABI},
1473 {"n32", no_argument, NULL, OPTION_N32},
1474 {"64", no_argument, NULL, OPTION_64},
1475 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
1476 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
1477 {"mpdr", no_argument, NULL, OPTION_PDR},
1478 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
1479 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
1480 {"mnan", required_argument, NULL, OPTION_NAN},
1482 {NULL, no_argument, NULL, 0}
1484 size_t md_longopts_size = sizeof (md_longopts);
1486 /* Information about either an Application Specific Extension or an
1487 optional architecture feature that, for simplicity, we treat in the
1488 same way as an ASE. */
1491 /* The name of the ASE, used in both the command-line and .set options. */
1494 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1495 and 64-bit architectures, the flags here refer to the subset that
1496 is available on both. */
1499 /* The ASE_* flag used for instructions that are available on 64-bit
1500 architectures but that are not included in FLAGS. */
1501 unsigned int flags64;
1503 /* The command-line options that turn the ASE on and off. */
1507 /* The minimum required architecture revisions for MIPS32, MIPS64,
1508 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1511 int micromips32_rev;
1512 int micromips64_rev;
1515 /* A table of all supported ASEs. */
1516 static const struct mips_ase mips_ases[] = {
1517 { "dsp", ASE_DSP, ASE_DSP64,
1518 OPTION_DSP, OPTION_NO_DSP,
1521 { "dspr2", ASE_DSP | ASE_DSPR2, 0,
1522 OPTION_DSPR2, OPTION_NO_DSPR2,
1525 { "eva", ASE_EVA, 0,
1526 OPTION_EVA, OPTION_NO_EVA,
1529 { "mcu", ASE_MCU, 0,
1530 OPTION_MCU, OPTION_NO_MCU,
1533 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1534 { "mdmx", ASE_MDMX, 0,
1535 OPTION_MDMX, OPTION_NO_MDMX,
1538 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1539 { "mips3d", ASE_MIPS3D, 0,
1540 OPTION_MIPS3D, OPTION_NO_MIPS3D,
1544 OPTION_MT, OPTION_NO_MT,
1547 { "smartmips", ASE_SMARTMIPS, 0,
1548 OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS,
1551 { "virt", ASE_VIRT, ASE_VIRT64,
1552 OPTION_VIRT, OPTION_NO_VIRT,
1556 /* The set of ASEs that require -mfp64. */
1557 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX)
1559 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1560 static const unsigned int mips_ase_groups[] = {
1566 The following pseudo-ops from the Kane and Heinrich MIPS book
1567 should be defined here, but are currently unsupported: .alias,
1568 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1570 The following pseudo-ops from the Kane and Heinrich MIPS book are
1571 specific to the type of debugging information being generated, and
1572 should be defined by the object format: .aent, .begin, .bend,
1573 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1576 The following pseudo-ops from the Kane and Heinrich MIPS book are
1577 not MIPS CPU specific, but are also not specific to the object file
1578 format. This file is probably the best place to define them, but
1579 they are not currently supported: .asm0, .endr, .lab, .struct. */
1581 static const pseudo_typeS mips_pseudo_table[] =
1583 /* MIPS specific pseudo-ops. */
1584 {"option", s_option, 0},
1585 {"set", s_mipsset, 0},
1586 {"rdata", s_change_sec, 'r'},
1587 {"sdata", s_change_sec, 's'},
1588 {"livereg", s_ignore, 0},
1589 {"abicalls", s_abicalls, 0},
1590 {"cpload", s_cpload, 0},
1591 {"cpsetup", s_cpsetup, 0},
1592 {"cplocal", s_cplocal, 0},
1593 {"cprestore", s_cprestore, 0},
1594 {"cpreturn", s_cpreturn, 0},
1595 {"dtprelword", s_dtprelword, 0},
1596 {"dtpreldword", s_dtpreldword, 0},
1597 {"tprelword", s_tprelword, 0},
1598 {"tpreldword", s_tpreldword, 0},
1599 {"gpvalue", s_gpvalue, 0},
1600 {"gpword", s_gpword, 0},
1601 {"gpdword", s_gpdword, 0},
1602 {"ehword", s_ehword, 0},
1603 {"cpadd", s_cpadd, 0},
1604 {"insn", s_insn, 0},
1607 /* Relatively generic pseudo-ops that happen to be used on MIPS
1609 {"asciiz", stringer, 8 + 1},
1610 {"bss", s_change_sec, 'b'},
1612 {"half", s_cons, 1},
1613 {"dword", s_cons, 3},
1614 {"weakext", s_mips_weakext, 0},
1615 {"origin", s_org, 0},
1616 {"repeat", s_rept, 0},
1618 /* For MIPS this is non-standard, but we define it for consistency. */
1619 {"sbss", s_change_sec, 'B'},
1621 /* These pseudo-ops are defined in read.c, but must be overridden
1622 here for one reason or another. */
1623 {"align", s_align, 0},
1624 {"byte", s_cons, 0},
1625 {"data", s_change_sec, 'd'},
1626 {"double", s_float_cons, 'd'},
1627 {"float", s_float_cons, 'f'},
1628 {"globl", s_mips_globl, 0},
1629 {"global", s_mips_globl, 0},
1630 {"hword", s_cons, 1},
1632 {"long", s_cons, 2},
1633 {"octa", s_cons, 4},
1634 {"quad", s_cons, 3},
1635 {"section", s_change_section, 0},
1636 {"short", s_cons, 1},
1637 {"single", s_float_cons, 'f'},
1638 {"stabd", s_mips_stab, 'd'},
1639 {"stabn", s_mips_stab, 'n'},
1640 {"stabs", s_mips_stab, 's'},
1641 {"text", s_change_sec, 't'},
1642 {"word", s_cons, 2},
1644 { "extern", ecoff_directive_extern, 0},
1649 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1651 /* These pseudo-ops should be defined by the object file format.
1652 However, a.out doesn't support them, so we have versions here. */
1653 {"aent", s_mips_ent, 1},
1654 {"bgnb", s_ignore, 0},
1655 {"end", s_mips_end, 0},
1656 {"endb", s_ignore, 0},
1657 {"ent", s_mips_ent, 0},
1658 {"file", s_mips_file, 0},
1659 {"fmask", s_mips_mask, 'F'},
1660 {"frame", s_mips_frame, 0},
1661 {"loc", s_mips_loc, 0},
1662 {"mask", s_mips_mask, 'R'},
1663 {"verstamp", s_ignore, 0},
1667 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1668 purpose of the `.dc.a' internal pseudo-op. */
1671 mips_address_bytes (void)
1673 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1676 extern void pop_insert (const pseudo_typeS *);
1679 mips_pop_insert (void)
1681 pop_insert (mips_pseudo_table);
1682 if (! ECOFF_DEBUGGING)
1683 pop_insert (mips_nonecoff_pseudo_table);
1686 /* Symbols labelling the current insn. */
1688 struct insn_label_list
1690 struct insn_label_list *next;
1694 static struct insn_label_list *free_insn_labels;
1695 #define label_list tc_segment_info_data.labels
1697 static void mips_clear_insn_labels (void);
1698 static void mips_mark_labels (void);
1699 static void mips_compressed_mark_labels (void);
1702 mips_clear_insn_labels (void)
1704 register struct insn_label_list **pl;
1705 segment_info_type *si;
1709 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1712 si = seg_info (now_seg);
1713 *pl = si->label_list;
1714 si->label_list = NULL;
1718 /* Mark instruction labels in MIPS16/microMIPS mode. */
1721 mips_mark_labels (void)
1723 if (HAVE_CODE_COMPRESSION)
1724 mips_compressed_mark_labels ();
1727 static char *expr_end;
1729 /* Expressions which appear in macro instructions. These are set by
1730 mips_ip and read by macro. */
1732 static expressionS imm_expr;
1733 static expressionS imm2_expr;
1735 /* The relocatable field in an instruction and the relocs associated
1736 with it. These variables are used for instructions like LUI and
1737 JAL as well as true offsets. They are also used for address
1738 operands in macros. */
1740 static expressionS offset_expr;
1741 static bfd_reloc_code_real_type offset_reloc[3]
1742 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1744 /* This is set to the resulting size of the instruction to be produced
1745 by mips16_ip if an explicit extension is used or by mips_ip if an
1746 explicit size is supplied. */
1748 static unsigned int forced_insn_length;
1750 /* True if we are assembling an instruction. All dot symbols defined during
1751 this time should be treated as code labels. */
1753 static bfd_boolean mips_assembling_insn;
1755 /* The pdr segment for per procedure frame/regmask info. Not used for
1758 static segT pdr_seg;
1760 /* The default target format to use. */
1762 #if defined (TE_FreeBSD)
1763 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1764 #elif defined (TE_TMIPS)
1765 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1767 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1771 mips_target_format (void)
1773 switch (OUTPUT_FLAVOR)
1775 case bfd_target_elf_flavour:
1777 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1778 return (target_big_endian
1779 ? "elf32-bigmips-vxworks"
1780 : "elf32-littlemips-vxworks");
1782 return (target_big_endian
1783 ? (HAVE_64BIT_OBJECTS
1784 ? ELF_TARGET ("elf64-", "big")
1786 ? ELF_TARGET ("elf32-n", "big")
1787 : ELF_TARGET ("elf32-", "big")))
1788 : (HAVE_64BIT_OBJECTS
1789 ? ELF_TARGET ("elf64-", "little")
1791 ? ELF_TARGET ("elf32-n", "little")
1792 : ELF_TARGET ("elf32-", "little"))));
1799 /* Return the ISA revision that is currently in use, or 0 if we are
1800 generating code for MIPS V or below. */
1805 if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2)
1808 /* microMIPS implies revision 2 or above. */
1809 if (mips_opts.micromips)
1812 if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64)
1818 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1821 mips_ase_mask (unsigned int flags)
1825 for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++)
1826 if (flags & mips_ase_groups[i])
1827 flags |= mips_ase_groups[i];
1831 /* Check whether the current ISA supports ASE. Issue a warning if
1835 mips_check_isa_supports_ase (const struct mips_ase *ase)
1839 static unsigned int warned_isa;
1840 static unsigned int warned_fp32;
1842 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
1843 min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev;
1845 min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev;
1846 if ((min_rev < 0 || mips_isa_rev () < min_rev)
1847 && (warned_isa & ase->flags) != ase->flags)
1849 warned_isa |= ase->flags;
1850 base = mips_opts.micromips ? "microMIPS" : "MIPS";
1851 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
1853 as_warn (_("The %d-bit %s architecture does not support the"
1854 " `%s' extension"), size, base, ase->name);
1856 as_warn (_("The `%s' extension requires %s%d revision %d or greater"),
1857 ase->name, base, size, min_rev);
1859 if ((ase->flags & FP64_ASES)
1861 && (warned_fp32 & ase->flags) != ase->flags)
1863 warned_fp32 |= ase->flags;
1864 as_warn (_("The `%s' extension requires 64-bit FPRs"), ase->name);
1868 /* Check all enabled ASEs to see whether they are supported by the
1869 chosen architecture. */
1872 mips_check_isa_supports_ases (void)
1874 unsigned int i, mask;
1876 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
1878 mask = mips_ase_mask (mips_ases[i].flags);
1879 if ((mips_opts.ase & mask) == mips_ases[i].flags)
1880 mips_check_isa_supports_ase (&mips_ases[i]);
1884 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
1885 that were affected. */
1888 mips_set_ase (const struct mips_ase *ase, bfd_boolean enabled_p)
1892 mask = mips_ase_mask (ase->flags);
1893 mips_opts.ase &= ~mask;
1895 mips_opts.ase |= ase->flags;
1899 /* Return the ASE called NAME, or null if none. */
1901 static const struct mips_ase *
1902 mips_lookup_ase (const char *name)
1906 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
1907 if (strcmp (name, mips_ases[i].name) == 0)
1908 return &mips_ases[i];
1912 /* Return the length of a microMIPS instruction in bytes. If bits of
1913 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1914 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1915 major opcode) will require further modifications to the opcode
1918 static inline unsigned int
1919 micromips_insn_length (const struct mips_opcode *mo)
1921 return (mo->mask >> 16) == 0 ? 2 : 4;
1924 /* Return the length of MIPS16 instruction OPCODE. */
1926 static inline unsigned int
1927 mips16_opcode_length (unsigned long opcode)
1929 return (opcode >> 16) == 0 ? 2 : 4;
1932 /* Return the length of instruction INSN. */
1934 static inline unsigned int
1935 insn_length (const struct mips_cl_insn *insn)
1937 if (mips_opts.micromips)
1938 return micromips_insn_length (insn->insn_mo);
1939 else if (mips_opts.mips16)
1940 return mips16_opcode_length (insn->insn_opcode);
1945 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1948 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1953 insn->insn_opcode = mo->match;
1956 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1957 insn->fixp[i] = NULL;
1958 insn->fixed_p = (mips_opts.noreorder > 0);
1959 insn->noreorder_p = (mips_opts.noreorder > 0);
1960 insn->mips16_absolute_jump_p = 0;
1961 insn->complete_p = 0;
1962 insn->cleared_p = 0;
1965 /* Get a list of all the operands in INSN. */
1967 static const struct mips_operand_array *
1968 insn_operands (const struct mips_cl_insn *insn)
1970 if (insn->insn_mo >= &mips_opcodes[0]
1971 && insn->insn_mo < &mips_opcodes[NUMOPCODES])
1972 return &mips_operands[insn->insn_mo - &mips_opcodes[0]];
1974 if (insn->insn_mo >= &mips16_opcodes[0]
1975 && insn->insn_mo < &mips16_opcodes[bfd_mips16_num_opcodes])
1976 return &mips16_operands[insn->insn_mo - &mips16_opcodes[0]];
1978 if (insn->insn_mo >= µmips_opcodes[0]
1979 && insn->insn_mo < µmips_opcodes[bfd_micromips_num_opcodes])
1980 return µmips_operands[insn->insn_mo - µmips_opcodes[0]];
1985 /* Get a description of operand OPNO of INSN. */
1987 static const struct mips_operand *
1988 insn_opno (const struct mips_cl_insn *insn, unsigned opno)
1990 const struct mips_operand_array *operands;
1992 operands = insn_operands (insn);
1993 if (opno >= MAX_OPERANDS || !operands->operand[opno])
1995 return operands->operand[opno];
1998 /* Install UVAL as the value of OPERAND in INSN. */
2001 insn_insert_operand (struct mips_cl_insn *insn,
2002 const struct mips_operand *operand, unsigned int uval)
2004 insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval);
2007 /* Extract the value of OPERAND from INSN. */
2009 static inline unsigned
2010 insn_extract_operand (const struct mips_cl_insn *insn,
2011 const struct mips_operand *operand)
2013 return mips_extract_operand (operand, insn->insn_opcode);
2016 /* Record the current MIPS16/microMIPS mode in now_seg. */
2019 mips_record_compressed_mode (void)
2021 segment_info_type *si;
2023 si = seg_info (now_seg);
2024 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
2025 si->tc_segment_info_data.mips16 = mips_opts.mips16;
2026 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
2027 si->tc_segment_info_data.micromips = mips_opts.micromips;
2030 /* Read a standard MIPS instruction from BUF. */
2032 static unsigned long
2033 read_insn (char *buf)
2035 if (target_big_endian)
2036 return bfd_getb32 ((bfd_byte *) buf);
2038 return bfd_getl32 ((bfd_byte *) buf);
2041 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2045 write_insn (char *buf, unsigned int insn)
2047 md_number_to_chars (buf, insn, 4);
2051 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2052 has length LENGTH. */
2054 static unsigned long
2055 read_compressed_insn (char *buf, unsigned int length)
2061 for (i = 0; i < length; i += 2)
2064 if (target_big_endian)
2065 insn |= bfd_getb16 ((char *) buf);
2067 insn |= bfd_getl16 ((char *) buf);
2073 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2074 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2077 write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
2081 for (i = 0; i < length; i += 2)
2082 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
2083 return buf + length;
2086 /* Install INSN at the location specified by its "frag" and "where" fields. */
2089 install_insn (const struct mips_cl_insn *insn)
2091 char *f = insn->frag->fr_literal + insn->where;
2092 if (HAVE_CODE_COMPRESSION)
2093 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
2095 write_insn (f, insn->insn_opcode);
2096 mips_record_compressed_mode ();
2099 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2100 and install the opcode in the new location. */
2103 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
2108 insn->where = where;
2109 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2110 if (insn->fixp[i] != NULL)
2112 insn->fixp[i]->fx_frag = frag;
2113 insn->fixp[i]->fx_where = where;
2115 install_insn (insn);
2118 /* Add INSN to the end of the output. */
2121 add_fixed_insn (struct mips_cl_insn *insn)
2123 char *f = frag_more (insn_length (insn));
2124 move_insn (insn, frag_now, f - frag_now->fr_literal);
2127 /* Start a variant frag and move INSN to the start of the variant part,
2128 marking it as fixed. The other arguments are as for frag_var. */
2131 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
2132 relax_substateT subtype, symbolS *symbol, offsetT offset)
2134 frag_grow (max_chars);
2135 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
2137 frag_var (rs_machine_dependent, max_chars, var,
2138 subtype, symbol, offset, NULL);
2141 /* Insert N copies of INSN into the history buffer, starting at
2142 position FIRST. Neither FIRST nor N need to be clipped. */
2145 insert_into_history (unsigned int first, unsigned int n,
2146 const struct mips_cl_insn *insn)
2148 if (mips_relax.sequence != 2)
2152 for (i = ARRAY_SIZE (history); i-- > first;)
2154 history[i] = history[i - n];
2160 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2161 the idea is to make it obvious at a glance that each errata is
2165 init_vr4120_conflicts (void)
2167 #define CONFLICT(FIRST, SECOND) \
2168 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2170 /* Errata 21 - [D]DIV[U] after [D]MACC */
2171 CONFLICT (MACC, DIV);
2172 CONFLICT (DMACC, DIV);
2174 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2175 CONFLICT (DMULT, DMULT);
2176 CONFLICT (DMULT, DMACC);
2177 CONFLICT (DMACC, DMULT);
2178 CONFLICT (DMACC, DMACC);
2180 /* Errata 24 - MT{LO,HI} after [D]MACC */
2181 CONFLICT (MACC, MTHILO);
2182 CONFLICT (DMACC, MTHILO);
2184 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2185 instruction is executed immediately after a MACC or DMACC
2186 instruction, the result of [either instruction] is incorrect." */
2187 CONFLICT (MACC, MULT);
2188 CONFLICT (MACC, DMULT);
2189 CONFLICT (DMACC, MULT);
2190 CONFLICT (DMACC, DMULT);
2192 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2193 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2194 DDIV or DDIVU instruction, the result of the MACC or
2195 DMACC instruction is incorrect.". */
2196 CONFLICT (DMULT, MACC);
2197 CONFLICT (DMULT, DMACC);
2198 CONFLICT (DIV, MACC);
2199 CONFLICT (DIV, DMACC);
2209 #define RTYPE_MASK 0x1ff00
2210 #define RTYPE_NUM 0x00100
2211 #define RTYPE_FPU 0x00200
2212 #define RTYPE_FCC 0x00400
2213 #define RTYPE_VEC 0x00800
2214 #define RTYPE_GP 0x01000
2215 #define RTYPE_CP0 0x02000
2216 #define RTYPE_PC 0x04000
2217 #define RTYPE_ACC 0x08000
2218 #define RTYPE_CCC 0x10000
2219 #define RNUM_MASK 0x000ff
2220 #define RWARN 0x80000
2222 #define GENERIC_REGISTER_NUMBERS \
2223 {"$0", RTYPE_NUM | 0}, \
2224 {"$1", RTYPE_NUM | 1}, \
2225 {"$2", RTYPE_NUM | 2}, \
2226 {"$3", RTYPE_NUM | 3}, \
2227 {"$4", RTYPE_NUM | 4}, \
2228 {"$5", RTYPE_NUM | 5}, \
2229 {"$6", RTYPE_NUM | 6}, \
2230 {"$7", RTYPE_NUM | 7}, \
2231 {"$8", RTYPE_NUM | 8}, \
2232 {"$9", RTYPE_NUM | 9}, \
2233 {"$10", RTYPE_NUM | 10}, \
2234 {"$11", RTYPE_NUM | 11}, \
2235 {"$12", RTYPE_NUM | 12}, \
2236 {"$13", RTYPE_NUM | 13}, \
2237 {"$14", RTYPE_NUM | 14}, \
2238 {"$15", RTYPE_NUM | 15}, \
2239 {"$16", RTYPE_NUM | 16}, \
2240 {"$17", RTYPE_NUM | 17}, \
2241 {"$18", RTYPE_NUM | 18}, \
2242 {"$19", RTYPE_NUM | 19}, \
2243 {"$20", RTYPE_NUM | 20}, \
2244 {"$21", RTYPE_NUM | 21}, \
2245 {"$22", RTYPE_NUM | 22}, \
2246 {"$23", RTYPE_NUM | 23}, \
2247 {"$24", RTYPE_NUM | 24}, \
2248 {"$25", RTYPE_NUM | 25}, \
2249 {"$26", RTYPE_NUM | 26}, \
2250 {"$27", RTYPE_NUM | 27}, \
2251 {"$28", RTYPE_NUM | 28}, \
2252 {"$29", RTYPE_NUM | 29}, \
2253 {"$30", RTYPE_NUM | 30}, \
2254 {"$31", RTYPE_NUM | 31}
2256 #define FPU_REGISTER_NAMES \
2257 {"$f0", RTYPE_FPU | 0}, \
2258 {"$f1", RTYPE_FPU | 1}, \
2259 {"$f2", RTYPE_FPU | 2}, \
2260 {"$f3", RTYPE_FPU | 3}, \
2261 {"$f4", RTYPE_FPU | 4}, \
2262 {"$f5", RTYPE_FPU | 5}, \
2263 {"$f6", RTYPE_FPU | 6}, \
2264 {"$f7", RTYPE_FPU | 7}, \
2265 {"$f8", RTYPE_FPU | 8}, \
2266 {"$f9", RTYPE_FPU | 9}, \
2267 {"$f10", RTYPE_FPU | 10}, \
2268 {"$f11", RTYPE_FPU | 11}, \
2269 {"$f12", RTYPE_FPU | 12}, \
2270 {"$f13", RTYPE_FPU | 13}, \
2271 {"$f14", RTYPE_FPU | 14}, \
2272 {"$f15", RTYPE_FPU | 15}, \
2273 {"$f16", RTYPE_FPU | 16}, \
2274 {"$f17", RTYPE_FPU | 17}, \
2275 {"$f18", RTYPE_FPU | 18}, \
2276 {"$f19", RTYPE_FPU | 19}, \
2277 {"$f20", RTYPE_FPU | 20}, \
2278 {"$f21", RTYPE_FPU | 21}, \
2279 {"$f22", RTYPE_FPU | 22}, \
2280 {"$f23", RTYPE_FPU | 23}, \
2281 {"$f24", RTYPE_FPU | 24}, \
2282 {"$f25", RTYPE_FPU | 25}, \
2283 {"$f26", RTYPE_FPU | 26}, \
2284 {"$f27", RTYPE_FPU | 27}, \
2285 {"$f28", RTYPE_FPU | 28}, \
2286 {"$f29", RTYPE_FPU | 29}, \
2287 {"$f30", RTYPE_FPU | 30}, \
2288 {"$f31", RTYPE_FPU | 31}
2290 #define FPU_CONDITION_CODE_NAMES \
2291 {"$fcc0", RTYPE_FCC | 0}, \
2292 {"$fcc1", RTYPE_FCC | 1}, \
2293 {"$fcc2", RTYPE_FCC | 2}, \
2294 {"$fcc3", RTYPE_FCC | 3}, \
2295 {"$fcc4", RTYPE_FCC | 4}, \
2296 {"$fcc5", RTYPE_FCC | 5}, \
2297 {"$fcc6", RTYPE_FCC | 6}, \
2298 {"$fcc7", RTYPE_FCC | 7}
2300 #define COPROC_CONDITION_CODE_NAMES \
2301 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2302 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2303 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2304 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2305 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2306 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2307 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2308 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2310 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2311 {"$a4", RTYPE_GP | 8}, \
2312 {"$a5", RTYPE_GP | 9}, \
2313 {"$a6", RTYPE_GP | 10}, \
2314 {"$a7", RTYPE_GP | 11}, \
2315 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2316 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2317 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2318 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2319 {"$t0", RTYPE_GP | 12}, \
2320 {"$t1", RTYPE_GP | 13}, \
2321 {"$t2", RTYPE_GP | 14}, \
2322 {"$t3", RTYPE_GP | 15}
2324 #define O32_SYMBOLIC_REGISTER_NAMES \
2325 {"$t0", RTYPE_GP | 8}, \
2326 {"$t1", RTYPE_GP | 9}, \
2327 {"$t2", RTYPE_GP | 10}, \
2328 {"$t3", RTYPE_GP | 11}, \
2329 {"$t4", RTYPE_GP | 12}, \
2330 {"$t5", RTYPE_GP | 13}, \
2331 {"$t6", RTYPE_GP | 14}, \
2332 {"$t7", RTYPE_GP | 15}, \
2333 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2334 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2335 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2336 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2338 /* Remaining symbolic register names */
2339 #define SYMBOLIC_REGISTER_NAMES \
2340 {"$zero", RTYPE_GP | 0}, \
2341 {"$at", RTYPE_GP | 1}, \
2342 {"$AT", RTYPE_GP | 1}, \
2343 {"$v0", RTYPE_GP | 2}, \
2344 {"$v1", RTYPE_GP | 3}, \
2345 {"$a0", RTYPE_GP | 4}, \
2346 {"$a1", RTYPE_GP | 5}, \
2347 {"$a2", RTYPE_GP | 6}, \
2348 {"$a3", RTYPE_GP | 7}, \
2349 {"$s0", RTYPE_GP | 16}, \
2350 {"$s1", RTYPE_GP | 17}, \
2351 {"$s2", RTYPE_GP | 18}, \
2352 {"$s3", RTYPE_GP | 19}, \
2353 {"$s4", RTYPE_GP | 20}, \
2354 {"$s5", RTYPE_GP | 21}, \
2355 {"$s6", RTYPE_GP | 22}, \
2356 {"$s7", RTYPE_GP | 23}, \
2357 {"$t8", RTYPE_GP | 24}, \
2358 {"$t9", RTYPE_GP | 25}, \
2359 {"$k0", RTYPE_GP | 26}, \
2360 {"$kt0", RTYPE_GP | 26}, \
2361 {"$k1", RTYPE_GP | 27}, \
2362 {"$kt1", RTYPE_GP | 27}, \
2363 {"$gp", RTYPE_GP | 28}, \
2364 {"$sp", RTYPE_GP | 29}, \
2365 {"$s8", RTYPE_GP | 30}, \
2366 {"$fp", RTYPE_GP | 30}, \
2367 {"$ra", RTYPE_GP | 31}
2369 #define MIPS16_SPECIAL_REGISTER_NAMES \
2370 {"$pc", RTYPE_PC | 0}
2372 #define MDMX_VECTOR_REGISTER_NAMES \
2373 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2374 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2375 {"$v2", RTYPE_VEC | 2}, \
2376 {"$v3", RTYPE_VEC | 3}, \
2377 {"$v4", RTYPE_VEC | 4}, \
2378 {"$v5", RTYPE_VEC | 5}, \
2379 {"$v6", RTYPE_VEC | 6}, \
2380 {"$v7", RTYPE_VEC | 7}, \
2381 {"$v8", RTYPE_VEC | 8}, \
2382 {"$v9", RTYPE_VEC | 9}, \
2383 {"$v10", RTYPE_VEC | 10}, \
2384 {"$v11", RTYPE_VEC | 11}, \
2385 {"$v12", RTYPE_VEC | 12}, \
2386 {"$v13", RTYPE_VEC | 13}, \
2387 {"$v14", RTYPE_VEC | 14}, \
2388 {"$v15", RTYPE_VEC | 15}, \
2389 {"$v16", RTYPE_VEC | 16}, \
2390 {"$v17", RTYPE_VEC | 17}, \
2391 {"$v18", RTYPE_VEC | 18}, \
2392 {"$v19", RTYPE_VEC | 19}, \
2393 {"$v20", RTYPE_VEC | 20}, \
2394 {"$v21", RTYPE_VEC | 21}, \
2395 {"$v22", RTYPE_VEC | 22}, \
2396 {"$v23", RTYPE_VEC | 23}, \
2397 {"$v24", RTYPE_VEC | 24}, \
2398 {"$v25", RTYPE_VEC | 25}, \
2399 {"$v26", RTYPE_VEC | 26}, \
2400 {"$v27", RTYPE_VEC | 27}, \
2401 {"$v28", RTYPE_VEC | 28}, \
2402 {"$v29", RTYPE_VEC | 29}, \
2403 {"$v30", RTYPE_VEC | 30}, \
2404 {"$v31", RTYPE_VEC | 31}
2406 #define MIPS_DSP_ACCUMULATOR_NAMES \
2407 {"$ac0", RTYPE_ACC | 0}, \
2408 {"$ac1", RTYPE_ACC | 1}, \
2409 {"$ac2", RTYPE_ACC | 2}, \
2410 {"$ac3", RTYPE_ACC | 3}
2412 static const struct regname reg_names[] = {
2413 GENERIC_REGISTER_NUMBERS,
2415 FPU_CONDITION_CODE_NAMES,
2416 COPROC_CONDITION_CODE_NAMES,
2418 /* The $txx registers depends on the abi,
2419 these will be added later into the symbol table from
2420 one of the tables below once mips_abi is set after
2421 parsing of arguments from the command line. */
2422 SYMBOLIC_REGISTER_NAMES,
2424 MIPS16_SPECIAL_REGISTER_NAMES,
2425 MDMX_VECTOR_REGISTER_NAMES,
2426 MIPS_DSP_ACCUMULATOR_NAMES,
2430 static const struct regname reg_names_o32[] = {
2431 O32_SYMBOLIC_REGISTER_NAMES,
2435 static const struct regname reg_names_n32n64[] = {
2436 N32N64_SYMBOLIC_REGISTER_NAMES,
2440 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2441 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2442 of these register symbols, return the associated vector register,
2443 otherwise return SYMVAL itself. */
2446 mips_prefer_vec_regno (unsigned int symval)
2448 if ((symval & -2) == (RTYPE_GP | 2))
2449 return RTYPE_VEC | (symval & 1);
2453 /* Return true if the string at *SPTR is a valid register name. If so,
2454 move *SPTR past the register and store the register's symbol value
2455 in *SYMVAL. This symbol value includes the register number
2456 (RNUM_MASK) and register type (RTYPE_MASK). */
2459 mips_parse_register (char **sptr, unsigned int *symval)
2465 /* Find end of name. */
2467 if (is_name_beginner (*e))
2469 while (is_part_of_name (*e))
2472 /* Terminate name. */
2476 /* Look up the name. */
2477 symbol = symbol_find (s);
2480 if (!symbol || S_GET_SEGMENT (symbol) != reg_section)
2484 *symval = S_GET_VALUE (symbol);
2488 /* Check if SPTR points at a valid register specifier according to TYPES.
2489 If so, then return 1, advance S to consume the specifier and store
2490 the register's number in REGNOP, otherwise return 0. */
2493 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2497 if (mips_parse_register (s, ®no))
2499 if (types & RTYPE_VEC)
2500 regno = mips_prefer_vec_regno (regno);
2509 as_warn (_("Unrecognized register name `%s'"), *s);
2514 return regno <= RNUM_MASK;
2517 /* Token types for parsed operand lists. */
2518 enum mips_operand_token_type {
2519 /* A plain register, e.g. $f2. */
2522 /* An element of a vector, e.g. $v0[1]. */
2525 /* A continuous range of registers, e.g. $s0-$s4. */
2528 /* A (possibly relocated) expression. */
2531 /* A floating-point value. */
2534 /* A single character. This can be '(', ')' or ',', but '(' only appears
2538 /* The end of the operand list. */
2542 /* A parsed operand token. */
2543 struct mips_operand_token
2545 /* The type of token. */
2546 enum mips_operand_token_type type;
2549 /* The register symbol value for an OT_REG. */
2552 /* The register symbol value and index for an OT_REG_ELEMENT. */
2558 /* The two register symbol values involved in an OT_REG_RANGE. */
2560 unsigned int regno1;
2561 unsigned int regno2;
2564 /* The value of an OT_INTEGER. The value is represented as an
2565 expression and the relocation operators that were applied to
2566 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2567 relocation operators were used. */
2570 bfd_reloc_code_real_type relocs[3];
2573 /* The binary data for an OT_FLOAT constant, and the number of bytes
2576 unsigned char data[8];
2580 /* The character represented by an OT_CHAR. */
2585 /* An obstack used to construct lists of mips_operand_tokens. */
2586 static struct obstack mips_operand_tokens;
2588 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
2591 mips_add_token (struct mips_operand_token *token,
2592 enum mips_operand_token_type type)
2595 obstack_grow (&mips_operand_tokens, token, sizeof (*token));
2598 /* Check whether S is '(' followed by a register name. Add OT_CHAR
2599 and OT_REG tokens for them if so, and return a pointer to the first
2600 unconsumed character. Return null otherwise. */
2603 mips_parse_base_start (char *s)
2605 struct mips_operand_token token;
2612 SKIP_SPACE_TABS (s);
2613 if (!mips_parse_register (&s, ®no))
2617 mips_add_token (&token, OT_CHAR);
2619 token.u.regno = regno;
2620 mips_add_token (&token, OT_REG);
2625 /* Parse one or more tokens from S. Return a pointer to the first
2626 unconsumed character on success. Return null if an error was found
2627 and store the error text in insn_error. FLOAT_FORMAT is as for
2628 mips_parse_arguments. */
2631 mips_parse_argument_token (char *s, char float_format)
2633 char *end, *save_in, *err;
2634 unsigned int regno1, regno2;
2635 struct mips_operand_token token;
2637 /* First look for "($reg", since we want to treat that as an
2638 OT_CHAR and OT_REG rather than an expression. */
2639 end = mips_parse_base_start (s);
2643 /* Handle other characters that end up as OT_CHARs. */
2644 if (*s == ')' || *s == ',')
2647 mips_add_token (&token, OT_CHAR);
2652 /* Handle tokens that start with a register. */
2653 if (mips_parse_register (&s, ®no1))
2655 SKIP_SPACE_TABS (s);
2658 /* A register range. */
2660 SKIP_SPACE_TABS (s);
2661 if (!mips_parse_register (&s, ®no2))
2663 insn_error = _("Invalid register range");
2667 token.u.reg_range.regno1 = regno1;
2668 token.u.reg_range.regno2 = regno2;
2669 mips_add_token (&token, OT_REG_RANGE);
2674 /* A vector element. */
2675 expressionS element;
2678 SKIP_SPACE_TABS (s);
2679 my_getExpression (&element, s);
2680 if (element.X_op != O_constant)
2682 insn_error = _("Vector element must be constant");
2686 SKIP_SPACE_TABS (s);
2689 insn_error = _("Missing `]'");
2694 token.u.reg_element.regno = regno1;
2695 token.u.reg_element.index = element.X_add_number;
2696 mips_add_token (&token, OT_REG_ELEMENT);
2700 /* Looks like just a plain register. */
2701 token.u.regno = regno1;
2702 mips_add_token (&token, OT_REG);
2708 /* First try to treat expressions as floats. */
2709 save_in = input_line_pointer;
2710 input_line_pointer = s;
2711 err = md_atof (float_format, (char *) token.u.flt.data,
2712 &token.u.flt.length);
2713 end = input_line_pointer;
2714 input_line_pointer = save_in;
2722 mips_add_token (&token, OT_FLOAT);
2727 /* Treat everything else as an integer expression. */
2728 token.u.integer.relocs[0] = BFD_RELOC_UNUSED;
2729 token.u.integer.relocs[1] = BFD_RELOC_UNUSED;
2730 token.u.integer.relocs[2] = BFD_RELOC_UNUSED;
2731 my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s);
2733 mips_add_token (&token, OT_INTEGER);
2737 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
2738 if expressions should be treated as 32-bit floating-point constants,
2739 'd' if they should be treated as 64-bit floating-point constants,
2740 or 0 if they should be treated as integer expressions (the usual case).
2742 Return a list of tokens on success, otherwise return 0. The caller
2743 must obstack_free the list after use. */
2745 static struct mips_operand_token *
2746 mips_parse_arguments (char *s, char float_format)
2748 struct mips_operand_token token;
2750 SKIP_SPACE_TABS (s);
2753 s = mips_parse_argument_token (s, float_format);
2756 obstack_free (&mips_operand_tokens,
2757 obstack_finish (&mips_operand_tokens));
2760 SKIP_SPACE_TABS (s);
2762 mips_add_token (&token, OT_END);
2763 return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens);
2766 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
2767 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2770 is_opcode_valid (const struct mips_opcode *mo)
2772 int isa = mips_opts.isa;
2773 int ase = mips_opts.ase;
2777 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
2778 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2779 if ((ase & mips_ases[i].flags) == mips_ases[i].flags)
2780 ase |= mips_ases[i].flags64;
2782 if (!opcode_is_member (mo, isa, ase, mips_opts.arch))
2785 /* Check whether the instruction or macro requires single-precision or
2786 double-precision floating-point support. Note that this information is
2787 stored differently in the opcode table for insns and macros. */
2788 if (mo->pinfo == INSN_MACRO)
2790 fp_s = mo->pinfo2 & INSN2_M_FP_S;
2791 fp_d = mo->pinfo2 & INSN2_M_FP_D;
2795 fp_s = mo->pinfo & FP_S;
2796 fp_d = mo->pinfo & FP_D;
2799 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
2802 if (fp_s && mips_opts.soft_float)
2808 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2809 selected ISA and architecture. */
2812 is_opcode_valid_16 (const struct mips_opcode *mo)
2814 return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch);
2817 /* Return TRUE if the size of the microMIPS opcode MO matches one
2818 explicitly requested. Always TRUE in the standard MIPS mode. */
2821 is_size_valid (const struct mips_opcode *mo)
2823 if (!mips_opts.micromips)
2826 if (mips_opts.insn32)
2828 if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4)
2830 if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0)
2833 if (!forced_insn_length)
2835 if (mo->pinfo == INSN_MACRO)
2837 return forced_insn_length == micromips_insn_length (mo);
2840 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2841 of the preceding instruction. Always TRUE in the standard MIPS mode.
2843 We don't accept macros in 16-bit delay slots to avoid a case where
2844 a macro expansion fails because it relies on a preceding 32-bit real
2845 instruction to have matched and does not handle the operands correctly.
2846 The only macros that may expand to 16-bit instructions are JAL that
2847 cannot be placed in a delay slot anyway, and corner cases of BALIGN
2848 and BGT (that likewise cannot be placed in a delay slot) that decay to
2849 a NOP. In all these cases the macros precede any corresponding real
2850 instruction definitions in the opcode table, so they will match in the
2851 second pass where the size of the delay slot is ignored and therefore
2852 produce correct code. */
2855 is_delay_slot_valid (const struct mips_opcode *mo)
2857 if (!mips_opts.micromips)
2860 if (mo->pinfo == INSN_MACRO)
2861 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0;
2862 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
2863 && micromips_insn_length (mo) != 4)
2865 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
2866 && micromips_insn_length (mo) != 2)
2872 /* For consistency checking, verify that all bits of OPCODE are specified
2873 either by the match/mask part of the instruction definition, or by the
2874 operand list. Also build up a list of operands in OPERANDS.
2876 INSN_BITS says which bits of the instruction are significant.
2877 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
2878 provides the mips_operand description of each operand. DECODE_OPERAND
2879 is null for MIPS16 instructions. */
2882 validate_mips_insn (const struct mips_opcode *opcode,
2883 unsigned long insn_bits,
2884 const struct mips_operand *(*decode_operand) (const char *),
2885 struct mips_operand_array *operands)
2888 unsigned long used_bits, doubled, undefined, opno, mask;
2889 const struct mips_operand *operand;
2891 mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask);
2892 if ((mask & opcode->match) != opcode->match)
2894 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
2895 opcode->name, opcode->args);
2900 for (s = opcode->args; *s; ++s)
2909 if (!decode_operand)
2910 operand = decode_mips16_operand (*s, FALSE);
2912 operand = decode_operand (s);
2913 if (!operand && opcode->pinfo != INSN_MACRO)
2915 as_bad (_("internal: unknown operand type: %s %s"),
2916 opcode->name, opcode->args);
2919 gas_assert (opno < MAX_OPERANDS);
2920 operands->operand[opno] = operand;
2923 used_bits |= ((1 << operand->size) - 1) << operand->lsb;
2924 if (operand->type == OP_MDMX_IMM_REG)
2925 /* Bit 5 is the format selector (OB vs QH). The opcode table
2926 has separate entries for each format. */
2927 used_bits &= ~(1 << (operand->lsb + 5));
2928 if (operand->type == OP_ENTRY_EXIT_LIST)
2929 used_bits &= ~(mask & 0x700);
2931 /* Skip prefix characters. */
2932 if (decode_operand && (*s == '+' || *s == 'm'))
2937 doubled = used_bits & mask & insn_bits;
2940 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
2941 " %s %s"), doubled, opcode->name, opcode->args);
2945 undefined = ~used_bits & insn_bits;
2946 if (opcode->pinfo != INSN_MACRO && undefined)
2948 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
2949 undefined, opcode->name, opcode->args);
2952 used_bits &= ~insn_bits;
2955 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
2956 used_bits, opcode->name, opcode->args);
2962 /* The MIPS16 version of validate_mips_insn. */
2965 validate_mips16_insn (const struct mips_opcode *opcode,
2966 struct mips_operand_array *operands)
2968 if (opcode->args[0] == 'a' || opcode->args[0] == 'i')
2970 /* In this case OPCODE defines the first 16 bits in a 32-bit jump
2971 instruction. Use TMP to describe the full instruction. */
2972 struct mips_opcode tmp;
2977 return validate_mips_insn (&tmp, 0xffffffff, 0, operands);
2979 return validate_mips_insn (opcode, 0xffff, 0, operands);
2982 /* The microMIPS version of validate_mips_insn. */
2985 validate_micromips_insn (const struct mips_opcode *opc,
2986 struct mips_operand_array *operands)
2988 unsigned long insn_bits;
2989 unsigned long major;
2990 unsigned int length;
2992 if (opc->pinfo == INSN_MACRO)
2993 return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand,
2996 length = micromips_insn_length (opc);
2997 if (length != 2 && length != 4)
2999 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
3000 "%s %s"), length, opc->name, opc->args);
3003 major = opc->match >> (10 + 8 * (length - 2));
3004 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
3005 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
3007 as_bad (_("Internal error: bad microMIPS opcode "
3008 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
3012 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3013 insn_bits = 1 << 4 * length;
3014 insn_bits <<= 4 * length;
3016 return validate_mips_insn (opc, insn_bits, decode_micromips_operand,
3020 /* This function is called once, at assembler startup time. It should set up
3021 all the tables, etc. that the MD part of the assembler will need. */
3026 const char *retval = NULL;
3030 if (mips_pic != NO_PIC)
3032 if (g_switch_seen && g_switch_value != 0)
3033 as_bad (_("-G may not be used in position-independent code"));
3037 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
3038 as_warn (_("Could not set architecture and machine"));
3040 op_hash = hash_new ();
3042 mips_operands = XCNEWVEC (struct mips_operand_array, NUMOPCODES);
3043 for (i = 0; i < NUMOPCODES;)
3045 const char *name = mips_opcodes[i].name;
3047 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
3050 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
3051 mips_opcodes[i].name, retval);
3052 /* Probably a memory allocation problem? Give up now. */
3053 as_fatal (_("Broken assembler. No assembly attempted."));
3057 if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff,
3058 decode_mips_operand, &mips_operands[i]))
3060 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3062 create_insn (&nop_insn, mips_opcodes + i);
3063 if (mips_fix_loongson2f_nop)
3064 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
3065 nop_insn.fixed_p = 1;
3069 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
3072 mips16_op_hash = hash_new ();
3073 mips16_operands = XCNEWVEC (struct mips_operand_array,
3074 bfd_mips16_num_opcodes);
3077 while (i < bfd_mips16_num_opcodes)
3079 const char *name = mips16_opcodes[i].name;
3081 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
3083 as_fatal (_("internal: can't hash `%s': %s"),
3084 mips16_opcodes[i].name, retval);
3087 if (!validate_mips16_insn (&mips16_opcodes[i], &mips16_operands[i]))
3089 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3091 create_insn (&mips16_nop_insn, mips16_opcodes + i);
3092 mips16_nop_insn.fixed_p = 1;
3096 while (i < bfd_mips16_num_opcodes
3097 && strcmp (mips16_opcodes[i].name, name) == 0);
3100 micromips_op_hash = hash_new ();
3101 micromips_operands = XCNEWVEC (struct mips_operand_array,
3102 bfd_micromips_num_opcodes);
3105 while (i < bfd_micromips_num_opcodes)
3107 const char *name = micromips_opcodes[i].name;
3109 retval = hash_insert (micromips_op_hash, name,
3110 (void *) µmips_opcodes[i]);
3112 as_fatal (_("internal: can't hash `%s': %s"),
3113 micromips_opcodes[i].name, retval);
3116 struct mips_cl_insn *micromips_nop_insn;
3118 if (!validate_micromips_insn (µmips_opcodes[i],
3119 µmips_operands[i]))
3122 if (micromips_opcodes[i].pinfo != INSN_MACRO)
3124 if (micromips_insn_length (micromips_opcodes + i) == 2)
3125 micromips_nop_insn = µmips_nop16_insn;
3126 else if (micromips_insn_length (micromips_opcodes + i) == 4)
3127 micromips_nop_insn = µmips_nop32_insn;
3131 if (micromips_nop_insn->insn_mo == NULL
3132 && strcmp (name, "nop") == 0)
3134 create_insn (micromips_nop_insn, micromips_opcodes + i);
3135 micromips_nop_insn->fixed_p = 1;
3139 while (++i < bfd_micromips_num_opcodes
3140 && strcmp (micromips_opcodes[i].name, name) == 0);
3144 as_fatal (_("Broken assembler. No assembly attempted."));
3146 /* We add all the general register names to the symbol table. This
3147 helps us detect invalid uses of them. */
3148 for (i = 0; reg_names[i].name; i++)
3149 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
3150 reg_names[i].num, /* & RNUM_MASK, */
3151 &zero_address_frag));
3153 for (i = 0; reg_names_n32n64[i].name; i++)
3154 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
3155 reg_names_n32n64[i].num, /* & RNUM_MASK, */
3156 &zero_address_frag));
3158 for (i = 0; reg_names_o32[i].name; i++)
3159 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
3160 reg_names_o32[i].num, /* & RNUM_MASK, */
3161 &zero_address_frag));
3163 obstack_init (&mips_operand_tokens);
3165 mips_no_prev_insn ();
3168 mips_cprmask[0] = 0;
3169 mips_cprmask[1] = 0;
3170 mips_cprmask[2] = 0;
3171 mips_cprmask[3] = 0;
3173 /* set the default alignment for the text section (2**2) */
3174 record_alignment (text_section, 2);
3176 bfd_set_gp_size (stdoutput, g_switch_value);
3178 /* On a native system other than VxWorks, sections must be aligned
3179 to 16 byte boundaries. When configured for an embedded ELF
3180 target, we don't bother. */
3181 if (strncmp (TARGET_OS, "elf", 3) != 0
3182 && strncmp (TARGET_OS, "vxworks", 7) != 0)
3184 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
3185 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
3186 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
3189 /* Create a .reginfo section for register masks and a .mdebug
3190 section for debugging information. */
3198 subseg = now_subseg;
3200 /* The ABI says this section should be loaded so that the
3201 running program can access it. However, we don't load it
3202 if we are configured for an embedded target */
3203 flags = SEC_READONLY | SEC_DATA;
3204 if (strncmp (TARGET_OS, "elf", 3) != 0)
3205 flags |= SEC_ALLOC | SEC_LOAD;
3207 if (mips_abi != N64_ABI)
3209 sec = subseg_new (".reginfo", (subsegT) 0);
3211 bfd_set_section_flags (stdoutput, sec, flags);
3212 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
3214 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
3218 /* The 64-bit ABI uses a .MIPS.options section rather than
3219 .reginfo section. */
3220 sec = subseg_new (".MIPS.options", (subsegT) 0);
3221 bfd_set_section_flags (stdoutput, sec, flags);
3222 bfd_set_section_alignment (stdoutput, sec, 3);
3224 /* Set up the option header. */
3226 Elf_Internal_Options opthdr;
3229 opthdr.kind = ODK_REGINFO;
3230 opthdr.size = (sizeof (Elf_External_Options)
3231 + sizeof (Elf64_External_RegInfo));
3234 f = frag_more (sizeof (Elf_External_Options));
3235 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
3236 (Elf_External_Options *) f);
3238 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
3242 if (ECOFF_DEBUGGING)
3244 sec = subseg_new (".mdebug", (subsegT) 0);
3245 (void) bfd_set_section_flags (stdoutput, sec,
3246 SEC_HAS_CONTENTS | SEC_READONLY);
3247 (void) bfd_set_section_alignment (stdoutput, sec, 2);
3249 else if (mips_flag_pdr)
3251 pdr_seg = subseg_new (".pdr", (subsegT) 0);
3252 (void) bfd_set_section_flags (stdoutput, pdr_seg,
3253 SEC_READONLY | SEC_RELOC
3255 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
3258 subseg_set (seg, subseg);
3261 if (! ECOFF_DEBUGGING)
3264 if (mips_fix_vr4120)
3265 init_vr4120_conflicts ();
3271 mips_emit_delays ();
3272 if (! ECOFF_DEBUGGING)
3277 md_assemble (char *str)
3279 struct mips_cl_insn insn;
3280 bfd_reloc_code_real_type unused_reloc[3]
3281 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3283 imm_expr.X_op = O_absent;
3284 imm2_expr.X_op = O_absent;
3285 offset_expr.X_op = O_absent;
3286 offset_reloc[0] = BFD_RELOC_UNUSED;
3287 offset_reloc[1] = BFD_RELOC_UNUSED;
3288 offset_reloc[2] = BFD_RELOC_UNUSED;
3290 mips_mark_labels ();
3291 mips_assembling_insn = TRUE;
3293 if (mips_opts.mips16)
3294 mips16_ip (str, &insn);
3297 mips_ip (str, &insn);
3298 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
3299 str, insn.insn_opcode));
3303 as_bad ("%s `%s'", insn_error, str);
3304 else if (insn.insn_mo->pinfo == INSN_MACRO)
3307 if (mips_opts.mips16)
3308 mips16_macro (&insn);
3315 if (offset_expr.X_op != O_absent)
3316 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
3318 append_insn (&insn, NULL, unused_reloc, FALSE);
3321 mips_assembling_insn = FALSE;
3324 /* Convenience functions for abstracting away the differences between
3325 MIPS16 and non-MIPS16 relocations. */
3327 static inline bfd_boolean
3328 mips16_reloc_p (bfd_reloc_code_real_type reloc)
3332 case BFD_RELOC_MIPS16_JMP:
3333 case BFD_RELOC_MIPS16_GPREL:
3334 case BFD_RELOC_MIPS16_GOT16:
3335 case BFD_RELOC_MIPS16_CALL16:
3336 case BFD_RELOC_MIPS16_HI16_S:
3337 case BFD_RELOC_MIPS16_HI16:
3338 case BFD_RELOC_MIPS16_LO16:
3346 static inline bfd_boolean
3347 micromips_reloc_p (bfd_reloc_code_real_type reloc)
3351 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
3352 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
3353 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
3354 case BFD_RELOC_MICROMIPS_GPREL16:
3355 case BFD_RELOC_MICROMIPS_JMP:
3356 case BFD_RELOC_MICROMIPS_HI16:
3357 case BFD_RELOC_MICROMIPS_HI16_S:
3358 case BFD_RELOC_MICROMIPS_LO16:
3359 case BFD_RELOC_MICROMIPS_LITERAL:
3360 case BFD_RELOC_MICROMIPS_GOT16:
3361 case BFD_RELOC_MICROMIPS_CALL16:
3362 case BFD_RELOC_MICROMIPS_GOT_HI16:
3363 case BFD_RELOC_MICROMIPS_GOT_LO16:
3364 case BFD_RELOC_MICROMIPS_CALL_HI16:
3365 case BFD_RELOC_MICROMIPS_CALL_LO16:
3366 case BFD_RELOC_MICROMIPS_SUB:
3367 case BFD_RELOC_MICROMIPS_GOT_PAGE:
3368 case BFD_RELOC_MICROMIPS_GOT_OFST:
3369 case BFD_RELOC_MICROMIPS_GOT_DISP:
3370 case BFD_RELOC_MICROMIPS_HIGHEST:
3371 case BFD_RELOC_MICROMIPS_HIGHER:
3372 case BFD_RELOC_MICROMIPS_SCN_DISP:
3373 case BFD_RELOC_MICROMIPS_JALR:
3381 static inline bfd_boolean
3382 jmp_reloc_p (bfd_reloc_code_real_type reloc)
3384 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
3387 static inline bfd_boolean
3388 got16_reloc_p (bfd_reloc_code_real_type reloc)
3390 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
3391 || reloc == BFD_RELOC_MICROMIPS_GOT16);
3394 static inline bfd_boolean
3395 hi16_reloc_p (bfd_reloc_code_real_type reloc)
3397 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
3398 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
3401 static inline bfd_boolean
3402 lo16_reloc_p (bfd_reloc_code_real_type reloc)
3404 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
3405 || reloc == BFD_RELOC_MICROMIPS_LO16);
3408 static inline bfd_boolean
3409 jalr_reloc_p (bfd_reloc_code_real_type reloc)
3411 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
3414 static inline bfd_boolean
3415 gprel16_reloc_p (bfd_reloc_code_real_type reloc)
3417 return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL
3418 || reloc == BFD_RELOC_MICROMIPS_GPREL16);
3421 /* Return true if RELOC is a PC-relative relocation that does not have
3422 full address range. */
3424 static inline bfd_boolean
3425 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc)
3429 case BFD_RELOC_16_PCREL_S2:
3430 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
3431 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
3432 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
3435 case BFD_RELOC_32_PCREL:
3436 return HAVE_64BIT_ADDRESSES;
3443 /* Return true if the given relocation might need a matching %lo().
3444 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
3445 need a matching %lo() when applied to local symbols. */
3447 static inline bfd_boolean
3448 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
3450 return (HAVE_IN_PLACE_ADDENDS
3451 && (hi16_reloc_p (reloc)
3452 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
3453 all GOT16 relocations evaluate to "G". */
3454 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
3457 /* Return the type of %lo() reloc needed by RELOC, given that
3458 reloc_needs_lo_p. */
3460 static inline bfd_reloc_code_real_type
3461 matching_lo_reloc (bfd_reloc_code_real_type reloc)
3463 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
3464 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
3468 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
3471 static inline bfd_boolean
3472 fixup_has_matching_lo_p (fixS *fixp)
3474 return (fixp->fx_next != NULL
3475 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
3476 && fixp->fx_addsy == fixp->fx_next->fx_addsy
3477 && fixp->fx_offset == fixp->fx_next->fx_offset);
3480 /* Move all labels in LABELS to the current insertion point. TEXT_P
3481 says whether the labels refer to text or data. */
3484 mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
3486 struct insn_label_list *l;
3489 for (l = labels; l != NULL; l = l->next)
3491 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
3492 symbol_set_frag (l->label, frag_now);
3493 val = (valueT) frag_now_fix ();
3494 /* MIPS16/microMIPS text labels are stored as odd. */
3495 if (text_p && HAVE_CODE_COMPRESSION)
3497 S_SET_VALUE (l->label, val);
3501 /* Move all labels in insn_labels to the current insertion point
3502 and treat them as text labels. */
3505 mips_move_text_labels (void)
3507 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
3511 s_is_linkonce (symbolS *sym, segT from_seg)
3513 bfd_boolean linkonce = FALSE;
3514 segT symseg = S_GET_SEGMENT (sym);
3516 if (symseg != from_seg && !S_IS_LOCAL (sym))
3518 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
3520 /* The GNU toolchain uses an extension for ELF: a section
3521 beginning with the magic string .gnu.linkonce is a
3522 linkonce section. */
3523 if (strncmp (segment_name (symseg), ".gnu.linkonce",
3524 sizeof ".gnu.linkonce" - 1) == 0)
3530 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
3531 linker to handle them specially, such as generating jalx instructions
3532 when needed. We also make them odd for the duration of the assembly,
3533 in order to generate the right sort of code. We will make them even
3534 in the adjust_symtab routine, while leaving them marked. This is
3535 convenient for the debugger and the disassembler. The linker knows
3536 to make them odd again. */
3539 mips_compressed_mark_label (symbolS *label)
3541 gas_assert (HAVE_CODE_COMPRESSION);
3543 if (mips_opts.mips16)
3544 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
3546 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
3547 if ((S_GET_VALUE (label) & 1) == 0
3548 /* Don't adjust the address if the label is global or weak, or
3549 in a link-once section, since we'll be emitting symbol reloc
3550 references to it which will be patched up by the linker, and
3551 the final value of the symbol may or may not be MIPS16/microMIPS. */
3552 && !S_IS_WEAK (label)
3553 && !S_IS_EXTERNAL (label)
3554 && !s_is_linkonce (label, now_seg))
3555 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
3558 /* Mark preceding MIPS16 or microMIPS instruction labels. */
3561 mips_compressed_mark_labels (void)
3563 struct insn_label_list *l;
3565 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next)
3566 mips_compressed_mark_label (l->label);
3569 /* End the current frag. Make it a variant frag and record the
3573 relax_close_frag (void)
3575 mips_macro_warning.first_frag = frag_now;
3576 frag_var (rs_machine_dependent, 0, 0,
3577 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
3578 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
3580 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
3581 mips_relax.first_fixup = 0;
3584 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
3585 See the comment above RELAX_ENCODE for more details. */
3588 relax_start (symbolS *symbol)
3590 gas_assert (mips_relax.sequence == 0);
3591 mips_relax.sequence = 1;
3592 mips_relax.symbol = symbol;
3595 /* Start generating the second version of a relaxable sequence.
3596 See the comment above RELAX_ENCODE for more details. */
3601 gas_assert (mips_relax.sequence == 1);
3602 mips_relax.sequence = 2;
3605 /* End the current relaxable sequence. */
3610 gas_assert (mips_relax.sequence == 2);
3611 relax_close_frag ();
3612 mips_relax.sequence = 0;
3615 /* Return true if IP is a delayed branch or jump. */
3617 static inline bfd_boolean
3618 delayed_branch_p (const struct mips_cl_insn *ip)
3620 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
3621 | INSN_COND_BRANCH_DELAY
3622 | INSN_COND_BRANCH_LIKELY)) != 0;
3625 /* Return true if IP is a compact branch or jump. */
3627 static inline bfd_boolean
3628 compact_branch_p (const struct mips_cl_insn *ip)
3630 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
3631 | INSN2_COND_BRANCH)) != 0;
3634 /* Return true if IP is an unconditional branch or jump. */
3636 static inline bfd_boolean
3637 uncond_branch_p (const struct mips_cl_insn *ip)
3639 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
3640 || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0);
3643 /* Return true if IP is a branch-likely instruction. */
3645 static inline bfd_boolean
3646 branch_likely_p (const struct mips_cl_insn *ip)
3648 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
3651 /* Return the type of nop that should be used to fill the delay slot
3652 of delayed branch IP. */
3654 static struct mips_cl_insn *
3655 get_delay_slot_nop (const struct mips_cl_insn *ip)
3657 if (mips_opts.micromips
3658 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
3659 return µmips_nop32_insn;
3663 /* Return a mask that has bit N set if OPCODE reads the register(s)
3667 insn_read_mask (const struct mips_opcode *opcode)
3669 return (opcode->pinfo & INSN_READ_ALL) >> INSN_READ_SHIFT;
3672 /* Return a mask that has bit N set if OPCODE writes to the register(s)
3676 insn_write_mask (const struct mips_opcode *opcode)
3678 return (opcode->pinfo & INSN_WRITE_ALL) >> INSN_WRITE_SHIFT;
3681 /* Return a mask of the registers specified by operand OPERAND of INSN.
3682 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
3686 operand_reg_mask (const struct mips_cl_insn *insn,
3687 const struct mips_operand *operand,
3688 unsigned int type_mask)
3690 unsigned int uval, vsel;
3692 switch (operand->type)
3699 case OP_ADDIUSP_INT:
3700 case OP_ENTRY_EXIT_LIST:
3701 case OP_REPEAT_DEST_REG:
3702 case OP_REPEAT_PREV_REG:
3708 const struct mips_reg_operand *reg_op;
3710 reg_op = (const struct mips_reg_operand *) operand;
3711 if (!(type_mask & (1 << reg_op->reg_type)))
3713 uval = insn_extract_operand (insn, operand);
3714 return 1 << mips_decode_reg_operand (reg_op, uval);
3719 const struct mips_reg_pair_operand *pair_op;
3721 pair_op = (const struct mips_reg_pair_operand *) operand;
3722 if (!(type_mask & (1 << pair_op->reg_type)))
3724 uval = insn_extract_operand (insn, operand);
3725 return (1 << pair_op->reg1_map[uval]) | (1 << pair_op->reg2_map[uval]);
3728 case OP_CLO_CLZ_DEST:
3729 if (!(type_mask & (1 << OP_REG_GP)))
3731 uval = insn_extract_operand (insn, operand);
3732 return (1 << (uval & 31)) | (1 << (uval >> 5));
3734 case OP_LWM_SWM_LIST:
3737 case OP_SAVE_RESTORE_LIST:
3740 case OP_MDMX_IMM_REG:
3741 if (!(type_mask & (1 << OP_REG_VEC)))
3743 uval = insn_extract_operand (insn, operand);
3745 if ((vsel & 0x18) == 0x18)
3747 return 1 << (uval & 31);
3752 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
3753 where bit N of OPNO_MASK is set if operand N should be included.
3754 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
3758 insn_reg_mask (const struct mips_cl_insn *insn,
3759 unsigned int type_mask, unsigned int opno_mask)
3761 unsigned int opno, reg_mask;
3765 while (opno_mask != 0)
3768 reg_mask |= operand_reg_mask (insn, insn_opno (insn, opno), type_mask);
3775 /* Return the mask of core registers that IP reads. */
3778 gpr_read_mask (const struct mips_cl_insn *ip)
3780 unsigned long pinfo, pinfo2;
3783 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_read_mask (ip->insn_mo));
3784 pinfo = ip->insn_mo->pinfo;
3785 pinfo2 = ip->insn_mo->pinfo2;
3786 if (pinfo & INSN_UDI)
3788 /* UDI instructions have traditionally been assumed to read RS
3790 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3791 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3793 if (pinfo & INSN_READ_GPR_24)
3795 if (pinfo2 & INSN2_READ_GPR_16)
3797 if (pinfo2 & INSN2_READ_SP)
3799 if (pinfo2 & INSN2_READ_GPR_31)
3801 /* Don't include register 0. */
3805 /* Return the mask of core registers that IP writes. */
3808 gpr_write_mask (const struct mips_cl_insn *ip)
3810 unsigned long pinfo, pinfo2;
3813 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_write_mask (ip->insn_mo));
3814 pinfo = ip->insn_mo->pinfo;
3815 pinfo2 = ip->insn_mo->pinfo2;
3816 if (pinfo & INSN_WRITE_GPR_24)
3818 if (pinfo & INSN_WRITE_GPR_31)
3820 if (pinfo & INSN_UDI)
3821 /* UDI instructions have traditionally been assumed to write to RD. */
3822 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3823 if (pinfo2 & INSN2_WRITE_SP)
3825 /* Don't include register 0. */
3829 /* Return the mask of floating-point registers that IP reads. */
3832 fpr_read_mask (const struct mips_cl_insn *ip)
3834 unsigned long pinfo;
3837 mask = insn_reg_mask (ip, (1 << OP_REG_FP) | (1 << OP_REG_VEC),
3838 insn_read_mask (ip->insn_mo));
3839 pinfo = ip->insn_mo->pinfo;
3840 /* Conservatively treat all operands to an FP_D instruction are doubles.
3841 (This is overly pessimistic for things like cvt.d.s.) */
3842 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3847 /* Return the mask of floating-point registers that IP writes. */
3850 fpr_write_mask (const struct mips_cl_insn *ip)
3852 unsigned long pinfo;
3855 mask = insn_reg_mask (ip, (1 << OP_REG_FP) | (1 << OP_REG_VEC),
3856 insn_write_mask (ip->insn_mo));
3857 pinfo = ip->insn_mo->pinfo;
3858 /* Conservatively treat all operands to an FP_D instruction are doubles.
3859 (This is overly pessimistic for things like cvt.s.d.) */
3860 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3865 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
3866 Check whether that is allowed. */
3869 mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum)
3871 const char *s = insn->name;
3873 if (insn->pinfo == INSN_MACRO)
3874 /* Let a macro pass, we'll catch it later when it is expanded. */
3877 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || mips_opts.arch == CPU_R5900)
3879 /* Allow odd registers for single-precision ops. */
3880 switch (insn->pinfo & (FP_S | FP_D))
3891 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
3892 s = strchr (insn->name, '.');
3893 if (s != NULL && opnum == 2)
3894 s = strchr (s + 1, '.');
3895 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
3898 /* Single-precision coprocessor loads and moves are OK too. */
3899 if ((insn->pinfo & FP_S)
3900 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
3901 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
3907 /* Report that user-supplied argument ARGNUM for INSN was VAL, but should
3908 have been in the range [MIN_VAL, MAX_VAL]. PRINT_HEX says whether
3909 this operand is normally printed in hex or decimal. */
3912 report_bad_range (struct mips_cl_insn *insn, int argnum,
3913 offsetT val, int min_val, int max_val,
3914 bfd_boolean print_hex)
3916 if (print_hex && val >= 0)
3917 as_bad (_("Operand %d of `%s' must be in the range [0x%x, 0x%x],"
3919 argnum, insn->insn_mo->name, min_val, max_val, (unsigned long) val);
3921 as_bad (_("Operand %d of `%s' must be in the range [0x%x, 0x%x],"
3923 argnum, insn->insn_mo->name, min_val, max_val, (unsigned long) val);
3925 as_bad (_("Operand %d of `%s' must be in the range [%d, %d],"
3927 argnum, insn->insn_mo->name, min_val, max_val, (unsigned long) val);
3930 /* Report an invalid combination of position and size operands for a bitfield
3931 operation. POS and SIZE are the values that were given. */
3934 report_bad_field (offsetT pos, offsetT size)
3936 as_bad (_("Invalid field specification (position %ld, size %ld)"),
3937 (unsigned long) pos, (unsigned long) size);
3940 /* Information about an instruction argument that we're trying to match. */
3941 struct mips_arg_info
3943 /* The instruction so far. */
3944 struct mips_cl_insn *insn;
3946 /* The first unconsumed operand token. */
3947 struct mips_operand_token *token;
3949 /* The 1-based operand number, in terms of insn->insn_mo->args. */
3952 /* The 1-based argument number, for error reporting. This does not
3953 count elided optional registers, etc.. */
3956 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
3957 unsigned int last_regno;
3959 /* If the first operand was an OP_REG, this is the register that it
3960 specified, otherwise it is ILLEGAL_REG. */
3961 unsigned int dest_regno;
3963 /* The value of the last OP_INT operand. Only used for OP_MSB,
3964 where it gives the lsb position. */
3965 unsigned int last_op_int;
3967 /* If true, match routines should silently reject invalid arguments.
3968 If false, match routines can accept invalid arguments as long as
3969 they report an appropriate error. They still have the option of
3970 silently rejecting arguments, in which case a generic "Invalid operands"
3971 style of error will be used instead. */
3972 bfd_boolean soft_match;
3974 /* If true, the OP_INT match routine should treat plain symbolic operands
3975 as if a relocation operator like %lo(...) had been used. This is only
3976 ever true if the operand can be relocated. */
3977 bfd_boolean allow_nonconst;
3979 /* When true, the OP_INT match routine should allow unsigned N-bit
3980 arguments to be used where a signed N-bit operand is expected. */
3981 bfd_boolean lax_max;
3983 /* True if a reference to the current AT register was seen. */
3984 bfd_boolean seen_at;
3987 /* Try to match an OT_CHAR token for character CH. Consume the token
3988 and return true on success, otherwise return false. */
3991 match_char (struct mips_arg_info *arg, char ch)
3993 if (arg->token->type == OT_CHAR && arg->token->u.ch == ch)
4003 /* Try to get an expression from the next tokens in ARG. Consume the
4004 tokens and return true on success, storing the expression value in
4005 VALUE and relocation types in R. */
4008 match_expression (struct mips_arg_info *arg, expressionS *value,
4009 bfd_reloc_code_real_type *r)
4011 if (arg->token->type == OT_INTEGER)
4013 *value = arg->token->u.integer.value;
4014 memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r));
4019 /* Error-reporting is more consistent if we treat registers as O_register
4020 rather than rejecting them outright. "$1", "($1)" and "(($1))" are
4021 then handled in the same way. */
4022 if (arg->token->type == OT_REG)
4024 value->X_add_number = arg->token->u.regno;
4027 else if (arg->token[0].type == OT_CHAR
4028 && arg->token[0].u.ch == '('
4029 && arg->token[1].type == OT_REG
4030 && arg->token[2].type == OT_CHAR
4031 && arg->token[2].u.ch == ')')
4033 value->X_add_number = arg->token[1].u.regno;
4039 value->X_op = O_register;
4040 r[0] = r[1] = r[2] = BFD_RELOC_UNUSED;
4044 /* Try to get a constant expression from the next tokens in ARG. Consume
4045 the tokens and return return true on success, storing the constant value
4046 in *VALUE. Use FALLBACK as the value if the match succeeded with an
4050 match_const_int (struct mips_arg_info *arg, offsetT *value, offsetT fallback)
4053 bfd_reloc_code_real_type r[3];
4055 if (!match_expression (arg, &ex, r))
4058 if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant)
4059 *value = ex.X_add_number;
4062 if (arg->soft_match)
4064 as_bad (_("Operand %d of `%s' must be constant"),
4065 arg->argnum, arg->insn->insn_mo->name);
4071 /* Return the RTYPE_* flags for a register operand of type TYPE that
4072 appears in instruction OPCODE. */
4075 convert_reg_type (const struct mips_opcode *opcode,
4076 enum mips_reg_operand_type type)
4081 return RTYPE_NUM | RTYPE_GP;
4084 /* Allow vector register names for MDMX if the instruction is a 64-bit
4085 FPR load, store or move (including moves to and from GPRs). */
4086 if ((mips_opts.ase & ASE_MDMX)
4087 && (opcode->pinfo & FP_D)
4088 && (opcode->pinfo & (INSN_COPROC_MOVE_DELAY
4089 | INSN_COPROC_MEMORY_DELAY
4090 | INSN_LOAD_COPROC_DELAY
4091 | INSN_LOAD_MEMORY_DELAY
4092 | INSN_STORE_MEMORY)))
4093 return RTYPE_FPU | RTYPE_VEC;
4097 if (opcode->pinfo & (FP_D | FP_S))
4098 return RTYPE_CCC | RTYPE_FCC;
4102 if (opcode->membership & INSN_5400)
4104 return RTYPE_FPU | RTYPE_VEC;
4110 if (opcode->name[strlen (opcode->name) - 1] == '0')
4111 return RTYPE_NUM | RTYPE_CP0;
4120 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4123 check_regno (struct mips_arg_info *arg,
4124 enum mips_reg_operand_type type, unsigned int regno)
4126 if (AT && type == OP_REG_GP && regno == AT)
4127 arg->seen_at = TRUE;
4129 if (type == OP_REG_FP
4132 && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum))
4133 as_warn (_("Float register should be even, was %d"), regno);
4135 if (type == OP_REG_CCC)
4140 name = arg->insn->insn_mo->name;
4141 length = strlen (name);
4142 if ((regno & 1) != 0
4143 && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0)
4144 || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0)))
4145 as_warn (_("Condition code register should be even for %s, was %d"),
4148 if ((regno & 3) != 0
4149 && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0))
4150 as_warn (_("Condition code register should be 0 or 4 for %s, was %d"),
4155 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
4156 a register of type TYPE. Return true on success, storing the register
4157 number in *REGNO and warning about any dubious uses. */
4160 match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4161 unsigned int symval, unsigned int *regno)
4163 if (type == OP_REG_VEC)
4164 symval = mips_prefer_vec_regno (symval);
4165 if (!(symval & convert_reg_type (arg->insn->insn_mo, type)))
4168 *regno = symval & RNUM_MASK;
4169 check_regno (arg, type, *regno);
4173 /* Try to interpret the next token in ARG as a register of type TYPE.
4174 Consume the token and return true on success, storing the register
4175 number in *REGNO. Return false on failure. */
4178 match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4179 unsigned int *regno)
4181 if (arg->token->type == OT_REG
4182 && match_regno (arg, type, arg->token->u.regno, regno))
4190 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
4191 Consume the token and return true on success, storing the register numbers
4192 in *REGNO1 and *REGNO2. Return false on failure. */
4195 match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4196 unsigned int *regno1, unsigned int *regno2)
4198 if (match_reg (arg, type, regno1))
4203 if (arg->token->type == OT_REG_RANGE
4204 && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1)
4205 && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2)
4206 && *regno1 <= *regno2)
4214 /* OP_INT matcher. */
4217 match_int_operand (struct mips_arg_info *arg,
4218 const struct mips_operand *operand_base)
4220 const struct mips_int_operand *operand;
4222 int min_val, max_val, factor;
4224 bfd_boolean print_hex;
4226 operand = (const struct mips_int_operand *) operand_base;
4227 factor = 1 << operand->shift;
4228 min_val = mips_int_operand_min (operand);
4229 max_val = mips_int_operand_max (operand);
4231 max_val = ((1 << operand_base->size) - 1) << operand->shift;
4233 if (arg->token->type == OT_CHAR && arg->token->u.ch == '(')
4234 /* Assume we have an elided offset. The later match will fail
4235 if this turns out to be wrong. */
4237 else if (operand_base->lsb == 0
4238 && operand_base->size == 16
4239 && operand->shift == 0
4240 && operand->bias == 0
4241 && (operand->max_val == 32767 || operand->max_val == 65535))
4243 /* The operand can be relocated. */
4244 if (!match_expression (arg, &offset_expr, offset_reloc))
4247 if (offset_reloc[0] != BFD_RELOC_UNUSED)
4248 /* Relocation operators were used. Accept the arguent and
4249 leave the relocation value in offset_expr and offset_relocs
4250 for the caller to process. */
4253 if (offset_expr.X_op != O_constant)
4255 /* If non-constant operands are allowed then leave them for
4256 the caller to process, otherwise fail the match. */
4257 if (!arg->allow_nonconst)
4259 offset_reloc[0] = BFD_RELOC_LO16;
4263 /* Clear the global state; we're going to install the operand
4265 sval = offset_expr.X_add_number;
4266 offset_expr.X_op = O_absent;
4270 if (!match_const_int (arg, &sval, min_val))
4274 arg->last_op_int = sval;
4276 /* Check the range. If there's a problem, record the lowest acceptable
4277 value in arg->last_op_int in order to prevent an unhelpful error
4280 Bit counts have traditionally been printed in hex by the disassembler
4281 but printed as decimal in error messages. Only resort to hex if
4282 the operand is bigger than 6 bits. */
4283 print_hex = operand->print_hex && operand_base->size > 6;
4284 if (sval < min_val || sval > max_val)
4286 if (arg->soft_match)
4288 report_bad_range (arg->insn, arg->argnum, sval, min_val, max_val,
4290 arg->last_op_int = min_val;
4292 else if (sval % factor)
4294 if (arg->soft_match)
4296 as_bad (print_hex && sval >= 0
4297 ? _("Operand %d of `%s' must be a factor of %d, was 0x%lx.")
4298 : _("Operand %d of `%s' must be a factor of %d, was %ld."),
4299 arg->argnum, arg->insn->insn_mo->name, factor,
4300 (unsigned long) sval);
4301 arg->last_op_int = min_val;
4304 uval = (unsigned int) sval >> operand->shift;
4305 uval -= operand->bias;
4307 /* Handle -mfix-cn63xxp1. */
4309 && mips_fix_cn63xxp1
4310 && !mips_opts.micromips
4311 && strcmp ("pref", arg->insn->insn_mo->name) == 0)
4326 /* The rest must be changed to 28. */
4331 insn_insert_operand (arg->insn, operand_base, uval);
4335 /* OP_MAPPED_INT matcher. */
4338 match_mapped_int_operand (struct mips_arg_info *arg,
4339 const struct mips_operand *operand_base)
4341 const struct mips_mapped_int_operand *operand;
4342 unsigned int uval, num_vals;
4345 operand = (const struct mips_mapped_int_operand *) operand_base;
4346 if (!match_const_int (arg, &sval, operand->int_map[0]))
4349 num_vals = 1 << operand_base->size;
4350 for (uval = 0; uval < num_vals; uval++)
4351 if (operand->int_map[uval] == sval)
4353 if (uval == num_vals)
4356 insn_insert_operand (arg->insn, operand_base, uval);
4360 /* OP_MSB matcher. */
4363 match_msb_operand (struct mips_arg_info *arg,
4364 const struct mips_operand *operand_base)
4366 const struct mips_msb_operand *operand;
4367 int min_val, max_val, max_high;
4368 offsetT size, sval, high;
4370 operand = (const struct mips_msb_operand *) operand_base;
4371 min_val = operand->bias;
4372 max_val = min_val + (1 << operand_base->size) - 1;
4373 max_high = operand->opsize;
4375 if (!match_const_int (arg, &size, 1))
4378 high = size + arg->last_op_int;
4379 sval = operand->add_lsb ? high : size;
4381 if (size < 0 || high > max_high || sval < min_val || sval > max_val)
4383 if (arg->soft_match)
4385 report_bad_field (arg->last_op_int, size);
4388 insn_insert_operand (arg->insn, operand_base, sval - min_val);
4392 /* OP_REG matcher. */
4395 match_reg_operand (struct mips_arg_info *arg,
4396 const struct mips_operand *operand_base)
4398 const struct mips_reg_operand *operand;
4399 unsigned int regno, uval, num_vals;
4401 operand = (const struct mips_reg_operand *) operand_base;
4402 if (!match_reg (arg, operand->reg_type, ®no))
4405 if (operand->reg_map)
4407 num_vals = 1 << operand->root.size;
4408 for (uval = 0; uval < num_vals; uval++)
4409 if (operand->reg_map[uval] == regno)
4411 if (num_vals == uval)
4417 arg->last_regno = regno;
4418 if (arg->opnum == 1)
4419 arg->dest_regno = regno;
4420 insn_insert_operand (arg->insn, operand_base, uval);
4424 /* OP_REG_PAIR matcher. */
4427 match_reg_pair_operand (struct mips_arg_info *arg,
4428 const struct mips_operand *operand_base)
4430 const struct mips_reg_pair_operand *operand;
4431 unsigned int regno1, regno2, uval, num_vals;
4433 operand = (const struct mips_reg_pair_operand *) operand_base;
4434 if (!match_reg (arg, operand->reg_type, ®no1)
4435 || !match_char (arg, ',')
4436 || !match_reg (arg, operand->reg_type, ®no2))
4439 num_vals = 1 << operand_base->size;
4440 for (uval = 0; uval < num_vals; uval++)
4441 if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2)
4443 if (uval == num_vals)
4446 insn_insert_operand (arg->insn, operand_base, uval);
4450 /* OP_PCREL matcher. The caller chooses the relocation type. */
4453 match_pcrel_operand (struct mips_arg_info *arg)
4455 bfd_reloc_code_real_type r[3];
4457 return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED;
4460 /* OP_PERF_REG matcher. */
4463 match_perf_reg_operand (struct mips_arg_info *arg,
4464 const struct mips_operand *operand)
4468 if (!match_const_int (arg, &sval, 0))
4473 || (mips_opts.arch == CPU_R5900
4474 && (strcmp (arg->insn->insn_mo->name, "mfps") == 0
4475 || strcmp (arg->insn->insn_mo->name, "mtps") == 0))))
4477 if (arg->soft_match)
4479 as_bad (_("Invalid performance register (%ld)"), (unsigned long) sval);
4482 insn_insert_operand (arg->insn, operand, sval);
4486 /* OP_ADDIUSP matcher. */
4489 match_addiusp_operand (struct mips_arg_info *arg,
4490 const struct mips_operand *operand)
4495 if (!match_const_int (arg, &sval, -256))
4502 if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1))
4505 uval = (unsigned int) sval;
4506 uval = ((uval >> 1) & ~0xff) | (uval & 0xff);
4507 insn_insert_operand (arg->insn, operand, uval);
4511 /* OP_CLO_CLZ_DEST matcher. */
4514 match_clo_clz_dest_operand (struct mips_arg_info *arg,
4515 const struct mips_operand *operand)
4519 if (!match_reg (arg, OP_REG_GP, ®no))
4522 insn_insert_operand (arg->insn, operand, regno | (regno << 5));
4526 /* OP_LWM_SWM_LIST matcher. */
4529 match_lwm_swm_list_operand (struct mips_arg_info *arg,
4530 const struct mips_operand *operand)
4532 unsigned int reglist, sregs, ra, regno1, regno2;
4533 struct mips_arg_info reset;
4536 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
4540 if (regno2 == FP && regno1 >= S0 && regno1 <= S7)
4545 reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1);
4548 while (match_char (arg, ',')
4549 && match_reg_range (arg, OP_REG_GP, ®no1, ®no2));
4552 if (operand->size == 2)
4554 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
4560 and any permutations of these. */
4561 if ((reglist & 0xfff1ffff) != 0x80010000)
4564 sregs = (reglist >> 17) & 7;
4569 /* The list must include at least one of ra and s0-sN,
4570 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
4571 which are $23 and $30 respectively.) E.g.:
4579 and any permutations of these. */
4580 if ((reglist & 0x3f00ffff) != 0)
4583 ra = (reglist >> 27) & 0x10;
4584 sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
4587 if ((sregs & -sregs) != sregs)
4590 insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra);
4594 /* OP_ENTRY_EXIT_LIST matcher. */
4597 match_entry_exit_operand (struct mips_arg_info *arg,
4598 const struct mips_operand *operand)
4601 bfd_boolean is_exit;
4603 /* The format is the same for both ENTRY and EXIT, but the constraints
4605 is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0;
4606 mask = (is_exit ? 7 << 3 : 0);
4609 unsigned int regno1, regno2;
4610 bfd_boolean is_freg;
4612 if (match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
4614 else if (match_reg_range (arg, OP_REG_FP, ®no1, ®no2))
4619 if (is_exit && is_freg && regno1 == 0 && regno2 < 2)
4622 mask |= (5 + regno2) << 3;
4624 else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7)
4625 mask |= (regno2 - 3) << 3;
4626 else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17)
4627 mask |= (regno2 - 15) << 1;
4628 else if (regno1 == RA && regno2 == RA)
4633 while (match_char (arg, ','));
4635 insn_insert_operand (arg->insn, operand, mask);
4639 /* OP_SAVE_RESTORE_LIST matcher. */
4642 match_save_restore_list_operand (struct mips_arg_info *arg)
4644 unsigned int opcode, args, statics, sregs;
4645 unsigned int num_frame_sizes, num_args, num_statics, num_sregs;
4650 opcode = arg->insn->insn_opcode;
4652 num_frame_sizes = 0;
4658 unsigned int regno1, regno2;
4660 if (arg->token->type == OT_INTEGER)
4662 /* Handle the frame size. */
4663 if (!match_const_int (arg, &frame_size, 0))
4665 num_frame_sizes += 1;
4669 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
4672 while (regno1 <= regno2)
4674 if (regno1 >= 4 && regno1 <= 7)
4676 if (num_frame_sizes == 0)
4678 args |= 1 << (regno1 - 4);
4680 /* statics $a0-$a3 */
4681 statics |= 1 << (regno1 - 4);
4683 else if (regno1 >= 16 && regno1 <= 23)
4685 sregs |= 1 << (regno1 - 16);
4686 else if (regno1 == 30)
4689 else if (regno1 == 31)
4690 /* Add $ra to insn. */
4700 while (match_char (arg, ','));
4702 /* Encode args/statics combination. */
4705 else if (args == 0xf)
4706 /* All $a0-$a3 are args. */
4707 opcode |= MIPS16_ALL_ARGS << 16;
4708 else if (statics == 0xf)
4709 /* All $a0-$a3 are statics. */
4710 opcode |= MIPS16_ALL_STATICS << 16;
4713 /* Count arg registers. */
4723 /* Count static registers. */
4725 while (statics & 0x8)
4727 statics = (statics << 1) & 0xf;
4733 /* Encode args/statics. */
4734 opcode |= ((num_args << 2) | num_statics) << 16;
4737 /* Encode $s0/$s1. */
4738 if (sregs & (1 << 0)) /* $s0 */
4740 if (sregs & (1 << 1)) /* $s1 */
4744 /* Encode $s2-$s8. */
4753 opcode |= num_sregs << 24;
4755 /* Encode frame size. */
4756 if (num_frame_sizes == 0)
4757 error = _("Missing frame size");
4758 else if (num_frame_sizes > 1)
4759 error = _("Frame size specified twice");
4760 else if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8)
4761 error = _("Invalid frame size");
4762 else if (frame_size != 128 || (opcode >> 16) != 0)
4765 opcode |= (((frame_size & 0xf0) << 16)
4766 | (frame_size & 0x0f));
4771 if (arg->soft_match)
4773 as_bad ("%s", error);
4776 /* Finally build the instruction. */
4777 if ((opcode >> 16) != 0 || frame_size == 0)
4778 opcode |= MIPS16_EXTEND;
4779 arg->insn->insn_opcode = opcode;
4783 /* OP_MDMX_IMM_REG matcher. */
4786 match_mdmx_imm_reg_operand (struct mips_arg_info *arg,
4787 const struct mips_operand *operand)
4789 unsigned int regno, uval;
4791 const struct mips_opcode *opcode;
4793 /* The mips_opcode records whether this is an octobyte or quadhalf
4794 instruction. Start out with that bit in place. */
4795 opcode = arg->insn->insn_mo;
4796 uval = mips_extract_operand (operand, opcode->match);
4797 is_qh = (uval != 0);
4799 if (arg->token->type == OT_REG || arg->token->type == OT_REG_ELEMENT)
4801 if ((opcode->membership & INSN_5400)
4802 && strcmp (opcode->name, "rzu.ob") == 0)
4804 if (arg->soft_match)
4806 as_bad (_("Operand %d of `%s' must be an immediate"),
4807 arg->argnum, opcode->name);
4810 /* Check whether this is a vector register or a broadcast of
4811 a single element. */
4812 if (arg->token->type == OT_REG_ELEMENT)
4814 if (!match_regno (arg, OP_REG_VEC, arg->token->u.reg_element.regno,
4817 if (arg->token->u.reg_element.index > (is_qh ? 3 : 7))
4819 if (arg->soft_match)
4821 as_bad (_("Invalid element selector"));
4824 uval |= arg->token->u.reg_element.index << (is_qh ? 2 : 1) << 5;
4828 /* A full vector. */
4829 if ((opcode->membership & INSN_5400)
4830 && (strcmp (opcode->name, "sll.ob") == 0
4831 || strcmp (opcode->name, "srl.ob") == 0))
4833 if (arg->soft_match)
4835 as_bad (_("Operand %d of `%s' must be scalar"),
4836 arg->argnum, opcode->name);
4839 if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no))
4842 uval |= MDMX_FMTSEL_VEC_QH << 5;
4844 uval |= MDMX_FMTSEL_VEC_OB << 5;
4853 if (!match_const_int (arg, &sval, 0))
4855 if (sval < 0 || sval > 31)
4857 if (arg->soft_match)
4859 report_bad_range (arg->insn, arg->argnum, sval, 0, 31, FALSE);
4861 uval |= (sval & 31);
4863 uval |= MDMX_FMTSEL_IMM_QH << 5;
4865 uval |= MDMX_FMTSEL_IMM_OB << 5;
4867 insn_insert_operand (arg->insn, operand, uval);
4871 /* OP_PC matcher. */
4874 match_pc_operand (struct mips_arg_info *arg)
4876 if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC))
4884 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
4885 register that we need to match. */
4888 match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno)
4892 return match_reg (arg, OP_REG_GP, ®no) && regno == other_regno;
4895 /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
4896 the length of the value in bytes (4 for float, 8 for double) and
4897 USING_GPRS says whether the destination is a GPR rather than an FPR.
4899 Return the constant in IMM and OFFSET as follows:
4901 - If the constant should be loaded via memory, set IMM to O_absent and
4902 OFFSET to the memory address.
4904 - Otherwise, if the constant should be loaded into two 32-bit registers,
4905 set IMM to the O_constant to load into the high register and OFFSET
4906 to the corresponding value for the low register.
4908 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
4910 These constants only appear as the last operand in an instruction,
4911 and every instruction that accepts them in any variant accepts them
4912 in all variants. This means we don't have to worry about backing out
4913 any changes if the instruction does not match. We just match
4914 unconditionally and report an error if the constant is invalid. */
4917 match_float_constant (struct mips_arg_info *arg, expressionS *imm,
4918 expressionS *offset, int length, bfd_boolean using_gprs)
4923 const char *newname;
4924 unsigned char *data;
4926 /* Where the constant is placed is based on how the MIPS assembler
4929 length == 4 && using_gprs -- immediate value only
4930 length == 8 && using_gprs -- .rdata or immediate value
4931 length == 4 && !using_gprs -- .lit4 or immediate value
4932 length == 8 && !using_gprs -- .lit8 or immediate value
4934 The .lit4 and .lit8 sections are only used if permitted by the
4936 if (arg->token->type != OT_FLOAT)
4939 gas_assert (arg->token->u.flt.length == length);
4940 data = arg->token->u.flt.data;
4943 /* Handle 32-bit constants for which an immediate value is best. */
4946 || g_switch_value < 4
4947 || (data[0] == 0 && data[1] == 0)
4948 || (data[2] == 0 && data[3] == 0)))
4950 imm->X_op = O_constant;
4951 if (!target_big_endian)
4952 imm->X_add_number = bfd_getl32 (data);
4954 imm->X_add_number = bfd_getb32 (data);
4955 offset->X_op = O_absent;
4959 /* Handle 64-bit constants for which an immediate value is best. */
4961 && !mips_disable_float_construction
4962 /* Constants can only be constructed in GPRs and copied
4963 to FPRs if the GPRs are at least as wide as the FPRs.
4964 Force the constant into memory if we are using 64-bit FPRs
4965 but the GPRs are only 32 bits wide. */
4966 /* ??? No longer true with the addition of MTHC1, but this
4967 is legacy code... */
4968 && (using_gprs || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
4969 && ((data[0] == 0 && data[1] == 0)
4970 || (data[2] == 0 && data[3] == 0))
4971 && ((data[4] == 0 && data[5] == 0)
4972 || (data[6] == 0 && data[7] == 0)))
4974 /* The value is simple enough to load with a couple of instructions.
4975 If using 32-bit registers, set IMM to the high order 32 bits and
4976 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
4978 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
4980 imm->X_op = O_constant;
4981 offset->X_op = O_constant;
4982 if (!target_big_endian)
4984 imm->X_add_number = bfd_getl32 (data + 4);
4985 offset->X_add_number = bfd_getl32 (data);
4989 imm->X_add_number = bfd_getb32 (data);
4990 offset->X_add_number = bfd_getb32 (data + 4);
4992 if (offset->X_add_number == 0)
4993 offset->X_op = O_absent;
4997 imm->X_op = O_constant;
4998 if (!target_big_endian)
4999 imm->X_add_number = bfd_getl64 (data);
5001 imm->X_add_number = bfd_getb64 (data);
5002 offset->X_op = O_absent;
5007 /* Switch to the right section. */
5009 subseg = now_subseg;
5012 gas_assert (!using_gprs && g_switch_value >= 4);
5017 if (using_gprs || g_switch_value < 8)
5018 newname = RDATA_SECTION_NAME;
5023 new_seg = subseg_new (newname, (subsegT) 0);
5024 bfd_set_section_flags (stdoutput, new_seg,
5025 SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA);
5026 frag_align (length == 4 ? 2 : 3, 0, 0);
5027 if (strncmp (TARGET_OS, "elf", 3) != 0)
5028 record_alignment (new_seg, 4);
5030 record_alignment (new_seg, length == 4 ? 2 : 3);
5032 as_bad (_("Can't use floating point insn in this section"));
5034 /* Set the argument to the current address in the section. */
5035 imm->X_op = O_absent;
5036 offset->X_op = O_symbol;
5037 offset->X_add_symbol = symbol_temp_new_now ();
5038 offset->X_add_number = 0;
5040 /* Put the floating point number into the section. */
5041 p = frag_more (length);
5042 memcpy (p, data, length);
5044 /* Switch back to the original section. */
5045 subseg_set (seg, subseg);
5049 /* S is the text seen for ARG. Match it against OPERAND. Return the end
5050 of the argument text if the match is successful, otherwise return null. */
5053 match_operand (struct mips_arg_info *arg,
5054 const struct mips_operand *operand)
5056 switch (operand->type)
5059 return match_int_operand (arg, operand);
5062 return match_mapped_int_operand (arg, operand);
5065 return match_msb_operand (arg, operand);
5068 return match_reg_operand (arg, operand);
5071 return match_reg_pair_operand (arg, operand);
5074 return match_pcrel_operand (arg);
5077 return match_perf_reg_operand (arg, operand);
5079 case OP_ADDIUSP_INT:
5080 return match_addiusp_operand (arg, operand);
5082 case OP_CLO_CLZ_DEST:
5083 return match_clo_clz_dest_operand (arg, operand);
5085 case OP_LWM_SWM_LIST:
5086 return match_lwm_swm_list_operand (arg, operand);
5088 case OP_ENTRY_EXIT_LIST:
5089 return match_entry_exit_operand (arg, operand);
5091 case OP_SAVE_RESTORE_LIST:
5092 return match_save_restore_list_operand (arg);
5094 case OP_MDMX_IMM_REG:
5095 return match_mdmx_imm_reg_operand (arg, operand);
5097 case OP_REPEAT_DEST_REG:
5098 return match_tied_reg_operand (arg, arg->dest_regno);
5100 case OP_REPEAT_PREV_REG:
5101 return match_tied_reg_operand (arg, arg->last_regno);
5104 return match_pc_operand (arg);
5109 /* ARG is the state after successfully matching an instruction.
5110 Issue any queued-up warnings. */
5113 check_completed_insn (struct mips_arg_info *arg)
5118 as_warn (_("Used $at without \".set noat\""));
5120 as_warn (_("Used $%u with \".set at=$%u\""), AT, AT);
5124 /* Return true if modifying general-purpose register REG needs a delay. */
5127 reg_needs_delay (unsigned int reg)
5129 unsigned long prev_pinfo;
5131 prev_pinfo = history[0].insn_mo->pinfo;
5132 if (!mips_opts.noreorder
5133 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) && !gpr_interlocks)
5134 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) && !cop_interlocks))
5135 && (gpr_write_mask (&history[0]) & (1 << reg)))
5141 /* Classify an instruction according to the FIX_VR4120_* enumeration.
5142 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
5143 by VR4120 errata. */
5146 classify_vr4120_insn (const char *name)
5148 if (strncmp (name, "macc", 4) == 0)
5149 return FIX_VR4120_MACC;
5150 if (strncmp (name, "dmacc", 5) == 0)
5151 return FIX_VR4120_DMACC;
5152 if (strncmp (name, "mult", 4) == 0)
5153 return FIX_VR4120_MULT;
5154 if (strncmp (name, "dmult", 5) == 0)
5155 return FIX_VR4120_DMULT;
5156 if (strstr (name, "div"))
5157 return FIX_VR4120_DIV;
5158 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
5159 return FIX_VR4120_MTHILO;
5160 return NUM_FIX_VR4120_CLASSES;
5163 #define INSN_ERET 0x42000018
5164 #define INSN_DERET 0x4200001f
5166 /* Return the number of instructions that must separate INSN1 and INSN2,
5167 where INSN1 is the earlier instruction. Return the worst-case value
5168 for any INSN2 if INSN2 is null. */
5171 insns_between (const struct mips_cl_insn *insn1,
5172 const struct mips_cl_insn *insn2)
5174 unsigned long pinfo1, pinfo2;
5177 /* If INFO2 is null, pessimistically assume that all flags are set for
5178 the second instruction. */
5179 pinfo1 = insn1->insn_mo->pinfo;
5180 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
5182 /* For most targets, write-after-read dependencies on the HI and LO
5183 registers must be separated by at least two instructions. */
5184 if (!hilo_interlocks)
5186 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
5188 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
5192 /* If we're working around r7000 errata, there must be two instructions
5193 between an mfhi or mflo and any instruction that uses the result. */
5194 if (mips_7000_hilo_fix
5195 && !mips_opts.micromips
5196 && MF_HILO_INSN (pinfo1)
5197 && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))))
5200 /* If we're working around 24K errata, one instruction is required
5201 if an ERET or DERET is followed by a branch instruction. */
5202 if (mips_fix_24k && !mips_opts.micromips)
5204 if (insn1->insn_opcode == INSN_ERET
5205 || insn1->insn_opcode == INSN_DERET)
5208 || insn2->insn_opcode == INSN_ERET
5209 || insn2->insn_opcode == INSN_DERET
5210 || delayed_branch_p (insn2))
5215 /* If working around VR4120 errata, check for combinations that need
5216 a single intervening instruction. */
5217 if (mips_fix_vr4120 && !mips_opts.micromips)
5219 unsigned int class1, class2;
5221 class1 = classify_vr4120_insn (insn1->insn_mo->name);
5222 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
5226 class2 = classify_vr4120_insn (insn2->insn_mo->name);
5227 if (vr4120_conflicts[class1] & (1 << class2))
5232 if (!HAVE_CODE_COMPRESSION)
5234 /* Check for GPR or coprocessor load delays. All such delays
5235 are on the RT register. */
5236 /* Itbl support may require additional care here. */
5237 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
5238 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
5240 if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))
5244 /* Check for generic coprocessor hazards.
5246 This case is not handled very well. There is no special
5247 knowledge of CP0 handling, and the coprocessors other than
5248 the floating point unit are not distinguished at all. */
5249 /* Itbl support may require additional care here. FIXME!
5250 Need to modify this to include knowledge about
5251 user specified delays! */
5252 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
5253 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
5255 /* Handle cases where INSN1 writes to a known general coprocessor
5256 register. There must be a one instruction delay before INSN2
5257 if INSN2 reads that register, otherwise no delay is needed. */
5258 mask = fpr_write_mask (insn1);
5261 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
5266 /* Read-after-write dependencies on the control registers
5267 require a two-instruction gap. */
5268 if ((pinfo1 & INSN_WRITE_COND_CODE)
5269 && (pinfo2 & INSN_READ_COND_CODE))
5272 /* We don't know exactly what INSN1 does. If INSN2 is
5273 also a coprocessor instruction, assume there must be
5274 a one instruction gap. */
5275 if (pinfo2 & INSN_COP)
5280 /* Check for read-after-write dependencies on the coprocessor
5281 control registers in cases where INSN1 does not need a general
5282 coprocessor delay. This means that INSN1 is a floating point
5283 comparison instruction. */
5284 /* Itbl support may require additional care here. */
5285 else if (!cop_interlocks
5286 && (pinfo1 & INSN_WRITE_COND_CODE)
5287 && (pinfo2 & INSN_READ_COND_CODE))
5294 /* Return the number of nops that would be needed to work around the
5295 VR4130 mflo/mfhi errata if instruction INSN immediately followed
5296 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
5297 that are contained within the first IGNORE instructions of HIST. */
5300 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
5301 const struct mips_cl_insn *insn)
5306 /* Check if the instruction writes to HI or LO. MTHI and MTLO
5307 are not affected by the errata. */
5309 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
5310 || strcmp (insn->insn_mo->name, "mtlo") == 0
5311 || strcmp (insn->insn_mo->name, "mthi") == 0))
5314 /* Search for the first MFLO or MFHI. */
5315 for (i = 0; i < MAX_VR4130_NOPS; i++)
5316 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
5318 /* Extract the destination register. */
5319 mask = gpr_write_mask (&hist[i]);
5321 /* No nops are needed if INSN reads that register. */
5322 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
5325 /* ...or if any of the intervening instructions do. */
5326 for (j = 0; j < i; j++)
5327 if (gpr_read_mask (&hist[j]) & mask)
5331 return MAX_VR4130_NOPS - i;
5336 #define BASE_REG_EQ(INSN1, INSN2) \
5337 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
5338 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
5340 /* Return the minimum alignment for this store instruction. */
5343 fix_24k_align_to (const struct mips_opcode *mo)
5345 if (strcmp (mo->name, "sh") == 0)
5348 if (strcmp (mo->name, "swc1") == 0
5349 || strcmp (mo->name, "swc2") == 0
5350 || strcmp (mo->name, "sw") == 0
5351 || strcmp (mo->name, "sc") == 0
5352 || strcmp (mo->name, "s.s") == 0)
5355 if (strcmp (mo->name, "sdc1") == 0
5356 || strcmp (mo->name, "sdc2") == 0
5357 || strcmp (mo->name, "s.d") == 0)
5364 struct fix_24k_store_info
5366 /* Immediate offset, if any, for this store instruction. */
5368 /* Alignment required by this store instruction. */
5370 /* True for register offsets. */
5371 int register_offset;
5374 /* Comparison function used by qsort. */
5377 fix_24k_sort (const void *a, const void *b)
5379 const struct fix_24k_store_info *pos1 = a;
5380 const struct fix_24k_store_info *pos2 = b;
5382 return (pos1->off - pos2->off);
5385 /* INSN is a store instruction. Try to record the store information
5386 in STINFO. Return false if the information isn't known. */
5389 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
5390 const struct mips_cl_insn *insn)
5392 /* The instruction must have a known offset. */
5393 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
5396 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
5397 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
5401 /* Return the number of nops that would be needed to work around the 24k
5402 "lost data on stores during refill" errata if instruction INSN
5403 immediately followed the 2 instructions described by HIST.
5404 Ignore hazards that are contained within the first IGNORE
5405 instructions of HIST.
5407 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
5408 for the data cache refills and store data. The following describes
5409 the scenario where the store data could be lost.
5411 * A data cache miss, due to either a load or a store, causing fill
5412 data to be supplied by the memory subsystem
5413 * The first three doublewords of fill data are returned and written
5415 * A sequence of four stores occurs in consecutive cycles around the
5416 final doubleword of the fill:
5420 * Zero, One or more instructions
5423 The four stores A-D must be to different doublewords of the line that
5424 is being filled. The fourth instruction in the sequence above permits
5425 the fill of the final doubleword to be transferred from the FSB into
5426 the cache. In the sequence above, the stores may be either integer
5427 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
5428 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
5429 different doublewords on the line. If the floating point unit is
5430 running in 1:2 mode, it is not possible to create the sequence above
5431 using only floating point store instructions.
5433 In this case, the cache line being filled is incorrectly marked
5434 invalid, thereby losing the data from any store to the line that
5435 occurs between the original miss and the completion of the five
5436 cycle sequence shown above.
5438 The workarounds are:
5440 * Run the data cache in write-through mode.
5441 * Insert a non-store instruction between
5442 Store A and Store B or Store B and Store C. */
5445 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
5446 const struct mips_cl_insn *insn)
5448 struct fix_24k_store_info pos[3];
5449 int align, i, base_offset;
5454 /* If the previous instruction wasn't a store, there's nothing to
5456 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
5459 /* If the instructions after the previous one are unknown, we have
5460 to assume the worst. */
5464 /* Check whether we are dealing with three consecutive stores. */
5465 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
5466 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
5469 /* If we don't know the relationship between the store addresses,
5470 assume the worst. */
5471 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
5472 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
5475 if (!fix_24k_record_store_info (&pos[0], insn)
5476 || !fix_24k_record_store_info (&pos[1], &hist[0])
5477 || !fix_24k_record_store_info (&pos[2], &hist[1]))
5480 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
5482 /* Pick a value of ALIGN and X such that all offsets are adjusted by
5483 X bytes and such that the base register + X is known to be aligned
5486 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
5490 align = pos[0].align_to;
5491 base_offset = pos[0].off;
5492 for (i = 1; i < 3; i++)
5493 if (align < pos[i].align_to)
5495 align = pos[i].align_to;
5496 base_offset = pos[i].off;
5498 for (i = 0; i < 3; i++)
5499 pos[i].off -= base_offset;
5502 pos[0].off &= ~align + 1;
5503 pos[1].off &= ~align + 1;
5504 pos[2].off &= ~align + 1;
5506 /* If any two stores write to the same chunk, they also write to the
5507 same doubleword. The offsets are still sorted at this point. */
5508 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
5511 /* A range of at least 9 bytes is needed for the stores to be in
5512 non-overlapping doublewords. */
5513 if (pos[2].off - pos[0].off <= 8)
5516 if (pos[2].off - pos[1].off >= 24
5517 || pos[1].off - pos[0].off >= 24
5518 || pos[2].off - pos[0].off >= 32)
5524 /* Return the number of nops that would be needed if instruction INSN
5525 immediately followed the MAX_NOPS instructions given by HIST,
5526 where HIST[0] is the most recent instruction. Ignore hazards
5527 between INSN and the first IGNORE instructions in HIST.
5529 If INSN is null, return the worse-case number of nops for any
5533 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
5534 const struct mips_cl_insn *insn)
5536 int i, nops, tmp_nops;
5539 for (i = ignore; i < MAX_DELAY_NOPS; i++)
5541 tmp_nops = insns_between (hist + i, insn) - i;
5542 if (tmp_nops > nops)
5546 if (mips_fix_vr4130 && !mips_opts.micromips)
5548 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
5549 if (tmp_nops > nops)
5553 if (mips_fix_24k && !mips_opts.micromips)
5555 tmp_nops = nops_for_24k (ignore, hist, insn);
5556 if (tmp_nops > nops)
5563 /* The variable arguments provide NUM_INSNS extra instructions that
5564 might be added to HIST. Return the largest number of nops that
5565 would be needed after the extended sequence, ignoring hazards
5566 in the first IGNORE instructions. */
5569 nops_for_sequence (int num_insns, int ignore,
5570 const struct mips_cl_insn *hist, ...)
5573 struct mips_cl_insn buffer[MAX_NOPS];
5574 struct mips_cl_insn *cursor;
5577 va_start (args, hist);
5578 cursor = buffer + num_insns;
5579 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
5580 while (cursor > buffer)
5581 *--cursor = *va_arg (args, const struct mips_cl_insn *);
5583 nops = nops_for_insn (ignore, buffer, NULL);
5588 /* Like nops_for_insn, but if INSN is a branch, take into account the
5589 worst-case delay for the branch target. */
5592 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
5593 const struct mips_cl_insn *insn)
5597 nops = nops_for_insn (ignore, hist, insn);
5598 if (delayed_branch_p (insn))
5600 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
5601 hist, insn, get_delay_slot_nop (insn));
5602 if (tmp_nops > nops)
5605 else if (compact_branch_p (insn))
5607 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
5608 if (tmp_nops > nops)
5614 /* Fix NOP issue: Replace nops by "or at,at,zero". */
5617 fix_loongson2f_nop (struct mips_cl_insn * ip)
5619 gas_assert (!HAVE_CODE_COMPRESSION);
5620 if (strcmp (ip->insn_mo->name, "nop") == 0)
5621 ip->insn_opcode = LOONGSON2F_NOP_INSN;
5624 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
5625 jr target pc &= 'hffff_ffff_cfff_ffff. */
5628 fix_loongson2f_jump (struct mips_cl_insn * ip)
5630 gas_assert (!HAVE_CODE_COMPRESSION);
5631 if (strcmp (ip->insn_mo->name, "j") == 0
5632 || strcmp (ip->insn_mo->name, "jr") == 0
5633 || strcmp (ip->insn_mo->name, "jalr") == 0)
5641 sreg = EXTRACT_OPERAND (0, RS, *ip);
5642 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
5645 ep.X_op = O_constant;
5646 ep.X_add_number = 0xcfff0000;
5647 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
5648 ep.X_add_number = 0xffff;
5649 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
5650 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
5655 fix_loongson2f (struct mips_cl_insn * ip)
5657 if (mips_fix_loongson2f_nop)
5658 fix_loongson2f_nop (ip);
5660 if (mips_fix_loongson2f_jump)
5661 fix_loongson2f_jump (ip);
5664 /* IP is a branch that has a delay slot, and we need to fill it
5665 automatically. Return true if we can do that by swapping IP
5666 with the previous instruction.
5667 ADDRESS_EXPR is an operand of the instruction to be used with
5671 can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
5672 bfd_reloc_code_real_type *reloc_type)
5674 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
5675 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
5677 /* -O2 and above is required for this optimization. */
5678 if (mips_optimize < 2)
5681 /* If we have seen .set volatile or .set nomove, don't optimize. */
5682 if (mips_opts.nomove)
5685 /* We can't swap if the previous instruction's position is fixed. */
5686 if (history[0].fixed_p)
5689 /* If the previous previous insn was in a .set noreorder, we can't
5690 swap. Actually, the MIPS assembler will swap in this situation.
5691 However, gcc configured -with-gnu-as will generate code like
5699 in which we can not swap the bne and INSN. If gcc is not configured
5700 -with-gnu-as, it does not output the .set pseudo-ops. */
5701 if (history[1].noreorder_p)
5704 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
5705 This means that the previous instruction was a 4-byte one anyhow. */
5706 if (mips_opts.mips16 && history[0].fixp[0])
5709 /* If the branch is itself the target of a branch, we can not swap.
5710 We cheat on this; all we check for is whether there is a label on
5711 this instruction. If there are any branches to anything other than
5712 a label, users must use .set noreorder. */
5713 if (seg_info (now_seg)->label_list)
5716 /* If the previous instruction is in a variant frag other than this
5717 branch's one, we cannot do the swap. This does not apply to
5718 MIPS16 code, which uses variant frags for different purposes. */
5719 if (!mips_opts.mips16
5721 && history[0].frag->fr_type == rs_machine_dependent)
5724 /* We do not swap with instructions that cannot architecturally
5725 be placed in a branch delay slot, such as SYNC or ERET. We
5726 also refrain from swapping with a trap instruction, since it
5727 complicates trap handlers to have the trap instruction be in
5729 prev_pinfo = history[0].insn_mo->pinfo;
5730 if (prev_pinfo & INSN_NO_DELAY_SLOT)
5733 /* Check for conflicts between the branch and the instructions
5734 before the candidate delay slot. */
5735 if (nops_for_insn (0, history + 1, ip) > 0)
5738 /* Check for conflicts between the swapped sequence and the
5739 target of the branch. */
5740 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
5743 /* If the branch reads a register that the previous
5744 instruction sets, we can not swap. */
5745 gpr_read = gpr_read_mask (ip);
5746 prev_gpr_write = gpr_write_mask (&history[0]);
5747 if (gpr_read & prev_gpr_write)
5750 /* If the branch writes a register that the previous
5751 instruction sets, we can not swap. */
5752 gpr_write = gpr_write_mask (ip);
5753 if (gpr_write & prev_gpr_write)
5756 /* If the branch writes a register that the previous
5757 instruction reads, we can not swap. */
5758 prev_gpr_read = gpr_read_mask (&history[0]);
5759 if (gpr_write & prev_gpr_read)
5762 /* If one instruction sets a condition code and the
5763 other one uses a condition code, we can not swap. */
5764 pinfo = ip->insn_mo->pinfo;
5765 if ((pinfo & INSN_READ_COND_CODE)
5766 && (prev_pinfo & INSN_WRITE_COND_CODE))
5768 if ((pinfo & INSN_WRITE_COND_CODE)
5769 && (prev_pinfo & INSN_READ_COND_CODE))
5772 /* If the previous instruction uses the PC, we can not swap. */
5773 prev_pinfo2 = history[0].insn_mo->pinfo2;
5774 if (prev_pinfo2 & INSN2_READ_PC)
5777 /* If the previous instruction has an incorrect size for a fixed
5778 branch delay slot in microMIPS mode, we cannot swap. */
5779 pinfo2 = ip->insn_mo->pinfo2;
5780 if (mips_opts.micromips
5781 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
5782 && insn_length (history) != 2)
5784 if (mips_opts.micromips
5785 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
5786 && insn_length (history) != 4)
5789 /* On R5900 short loops need to be fixed by inserting a nop in
5790 the branch delay slots.
5791 A short loop can be terminated too early. */
5792 if (mips_opts.arch == CPU_R5900
5793 /* Check if instruction has a parameter, ignore "j $31". */
5794 && (address_expr != NULL)
5795 /* Parameter must be 16 bit. */
5796 && (*reloc_type == BFD_RELOC_16_PCREL_S2)
5797 /* Branch to same segment. */
5798 && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg)
5799 /* Branch to same code fragment. */
5800 && (symbol_get_frag(address_expr->X_add_symbol) == frag_now)
5801 /* Can only calculate branch offset if value is known. */
5802 && symbol_constant_p(address_expr->X_add_symbol)
5803 /* Check if branch is really conditional. */
5804 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */
5805 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */
5806 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
5809 /* Check if loop is shorter than 6 instructions including
5810 branch and delay slot. */
5811 distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol);
5818 /* When the loop includes branches or jumps,
5819 it is not a short loop. */
5820 for (i = 0; i < (distance / 4); i++)
5822 if ((history[i].cleared_p)
5823 || delayed_branch_p(&history[i]))
5831 /* Insert nop after branch to fix short loop. */
5840 /* Decide how we should add IP to the instruction stream.
5841 ADDRESS_EXPR is an operand of the instruction to be used with
5844 static enum append_method
5845 get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
5846 bfd_reloc_code_real_type *reloc_type)
5848 /* The relaxed version of a macro sequence must be inherently
5850 if (mips_relax.sequence == 2)
5853 /* We must not dabble with instructions in a ".set norerorder" block. */
5854 if (mips_opts.noreorder)
5857 /* Otherwise, it's our responsibility to fill branch delay slots. */
5858 if (delayed_branch_p (ip))
5860 if (!branch_likely_p (ip)
5861 && can_swap_branch_p (ip, address_expr, reloc_type))
5864 if (mips_opts.mips16
5865 && ISA_SUPPORTS_MIPS16E
5866 && gpr_read_mask (ip) != 0)
5867 return APPEND_ADD_COMPACT;
5869 return APPEND_ADD_WITH_NOP;
5875 /* IP is a MIPS16 instruction whose opcode we have just changed.
5876 Point IP->insn_mo to the new opcode's definition. */
5879 find_altered_mips16_opcode (struct mips_cl_insn *ip)
5881 const struct mips_opcode *mo, *end;
5883 end = &mips16_opcodes[bfd_mips16_num_opcodes];
5884 for (mo = ip->insn_mo; mo < end; mo++)
5885 if ((ip->insn_opcode & mo->mask) == mo->match)
5893 /* For microMIPS macros, we need to generate a local number label
5894 as the target of branches. */
5895 #define MICROMIPS_LABEL_CHAR '\037'
5896 static unsigned long micromips_target_label;
5897 static char micromips_target_name[32];
5900 micromips_label_name (void)
5902 char *p = micromips_target_name;
5903 char symbol_name_temporary[24];
5911 l = micromips_target_label;
5912 #ifdef LOCAL_LABEL_PREFIX
5913 *p++ = LOCAL_LABEL_PREFIX;
5916 *p++ = MICROMIPS_LABEL_CHAR;
5919 symbol_name_temporary[i++] = l % 10 + '0';
5924 *p++ = symbol_name_temporary[--i];
5927 return micromips_target_name;
5931 micromips_label_expr (expressionS *label_expr)
5933 label_expr->X_op = O_symbol;
5934 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
5935 label_expr->X_add_number = 0;
5939 micromips_label_inc (void)
5941 micromips_target_label++;
5942 *micromips_target_name = '\0';
5946 micromips_add_label (void)
5950 s = colon (micromips_label_name ());
5951 micromips_label_inc ();
5952 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
5955 /* If assembling microMIPS code, then return the microMIPS reloc
5956 corresponding to the requested one if any. Otherwise return
5957 the reloc unchanged. */
5959 static bfd_reloc_code_real_type
5960 micromips_map_reloc (bfd_reloc_code_real_type reloc)
5962 static const bfd_reloc_code_real_type relocs[][2] =
5964 /* Keep sorted incrementally by the left-hand key. */
5965 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
5966 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
5967 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
5968 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
5969 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
5970 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
5971 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
5972 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
5973 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
5974 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
5975 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
5976 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
5977 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
5978 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
5979 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
5980 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
5981 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
5982 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
5983 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
5984 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
5985 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
5986 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
5987 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
5988 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
5989 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
5990 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
5991 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
5993 bfd_reloc_code_real_type r;
5996 if (!mips_opts.micromips)
5998 for (i = 0; i < ARRAY_SIZE (relocs); i++)
6004 return relocs[i][1];
6009 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
6010 Return true on success, storing the resolved value in RESULT. */
6013 calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
6018 case BFD_RELOC_MIPS_HIGHEST:
6019 case BFD_RELOC_MICROMIPS_HIGHEST:
6020 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff;
6023 case BFD_RELOC_MIPS_HIGHER:
6024 case BFD_RELOC_MICROMIPS_HIGHER:
6025 *result = ((operand + 0x80008000ull) >> 32) & 0xffff;
6028 case BFD_RELOC_HI16_S:
6029 case BFD_RELOC_MICROMIPS_HI16_S:
6030 case BFD_RELOC_MIPS16_HI16_S:
6031 *result = ((operand + 0x8000) >> 16) & 0xffff;
6034 case BFD_RELOC_HI16:
6035 case BFD_RELOC_MICROMIPS_HI16:
6036 case BFD_RELOC_MIPS16_HI16:
6037 *result = (operand >> 16) & 0xffff;
6040 case BFD_RELOC_LO16:
6041 case BFD_RELOC_MICROMIPS_LO16:
6042 case BFD_RELOC_MIPS16_LO16:
6043 *result = operand & 0xffff;
6046 case BFD_RELOC_UNUSED:
6055 /* Output an instruction. IP is the instruction information.
6056 ADDRESS_EXPR is an operand of the instruction to be used with
6057 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
6058 a macro expansion. */
6061 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
6062 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
6064 unsigned long prev_pinfo2, pinfo;
6065 bfd_boolean relaxed_branch = FALSE;
6066 enum append_method method;
6067 bfd_boolean relax32;
6070 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
6071 fix_loongson2f (ip);
6073 file_ase_mips16 |= mips_opts.mips16;
6074 file_ase_micromips |= mips_opts.micromips;
6076 prev_pinfo2 = history[0].insn_mo->pinfo2;
6077 pinfo = ip->insn_mo->pinfo;
6079 if (mips_opts.micromips
6081 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
6082 && micromips_insn_length (ip->insn_mo) != 2)
6083 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
6084 && micromips_insn_length (ip->insn_mo) != 4)))
6085 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
6086 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
6088 if (address_expr == NULL)
6090 else if (reloc_type[0] <= BFD_RELOC_UNUSED
6091 && reloc_type[1] == BFD_RELOC_UNUSED
6092 && reloc_type[2] == BFD_RELOC_UNUSED
6093 && address_expr->X_op == O_constant)
6095 switch (*reloc_type)
6097 case BFD_RELOC_MIPS_JMP:
6101 shift = mips_opts.micromips ? 1 : 2;
6102 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
6103 as_bad (_("jump to misaligned address (0x%lx)"),
6104 (unsigned long) address_expr->X_add_number);
6105 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
6111 case BFD_RELOC_MIPS16_JMP:
6112 if ((address_expr->X_add_number & 3) != 0)
6113 as_bad (_("jump to misaligned address (0x%lx)"),
6114 (unsigned long) address_expr->X_add_number);
6116 (((address_expr->X_add_number & 0x7c0000) << 3)
6117 | ((address_expr->X_add_number & 0xf800000) >> 7)
6118 | ((address_expr->X_add_number & 0x3fffc) >> 2));
6122 case BFD_RELOC_16_PCREL_S2:
6126 shift = mips_opts.micromips ? 1 : 2;
6127 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
6128 as_bad (_("branch to misaligned address (0x%lx)"),
6129 (unsigned long) address_expr->X_add_number);
6130 if (!mips_relax_branch)
6132 if ((address_expr->X_add_number + (1 << (shift + 15)))
6133 & ~((1 << (shift + 16)) - 1))
6134 as_bad (_("branch address range overflow (0x%lx)"),
6135 (unsigned long) address_expr->X_add_number);
6136 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
6146 if (calculate_reloc (*reloc_type, address_expr->X_add_number,
6149 ip->insn_opcode |= value & 0xffff;
6157 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
6159 /* There are a lot of optimizations we could do that we don't.
6160 In particular, we do not, in general, reorder instructions.
6161 If you use gcc with optimization, it will reorder
6162 instructions and generally do much more optimization then we
6163 do here; repeating all that work in the assembler would only
6164 benefit hand written assembly code, and does not seem worth
6166 int nops = (mips_optimize == 0
6167 ? nops_for_insn (0, history, NULL)
6168 : nops_for_insn_or_target (0, history, ip));
6172 unsigned long old_frag_offset;
6175 old_frag = frag_now;
6176 old_frag_offset = frag_now_fix ();
6178 for (i = 0; i < nops; i++)
6179 add_fixed_insn (NOP_INSN);
6180 insert_into_history (0, nops, NOP_INSN);
6184 listing_prev_line ();
6185 /* We may be at the start of a variant frag. In case we
6186 are, make sure there is enough space for the frag
6187 after the frags created by listing_prev_line. The
6188 argument to frag_grow here must be at least as large
6189 as the argument to all other calls to frag_grow in
6190 this file. We don't have to worry about being in the
6191 middle of a variant frag, because the variants insert
6192 all needed nop instructions themselves. */
6196 mips_move_text_labels ();
6198 #ifndef NO_ECOFF_DEBUGGING
6199 if (ECOFF_DEBUGGING)
6200 ecoff_fix_loc (old_frag, old_frag_offset);
6204 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
6208 /* Work out how many nops in prev_nop_frag are needed by IP,
6209 ignoring hazards generated by the first prev_nop_frag_since
6211 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
6212 gas_assert (nops <= prev_nop_frag_holds);
6214 /* Enforce NOPS as a minimum. */
6215 if (nops > prev_nop_frag_required)
6216 prev_nop_frag_required = nops;
6218 if (prev_nop_frag_holds == prev_nop_frag_required)
6220 /* Settle for the current number of nops. Update the history
6221 accordingly (for the benefit of any future .set reorder code). */
6222 prev_nop_frag = NULL;
6223 insert_into_history (prev_nop_frag_since,
6224 prev_nop_frag_holds, NOP_INSN);
6228 /* Allow this instruction to replace one of the nops that was
6229 tentatively added to prev_nop_frag. */
6230 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
6231 prev_nop_frag_holds--;
6232 prev_nop_frag_since++;
6236 method = get_append_method (ip, address_expr, reloc_type);
6237 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
6239 dwarf2_emit_insn (0);
6240 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
6241 so "move" the instruction address accordingly.
6243 Also, it doesn't seem appropriate for the assembler to reorder .loc
6244 entries. If this instruction is a branch that we are going to swap
6245 with the previous instruction, the two instructions should be
6246 treated as a unit, and the debug information for both instructions
6247 should refer to the start of the branch sequence. Using the
6248 current position is certainly wrong when swapping a 32-bit branch
6249 and a 16-bit delay slot, since the current position would then be
6250 in the middle of a branch. */
6251 dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp);
6253 relax32 = (mips_relax_branch
6254 /* Don't try branch relaxation within .set nomacro, or within
6255 .set noat if we use $at for PIC computations. If it turns
6256 out that the branch was out-of-range, we'll get an error. */
6257 && !mips_opts.warn_about_macros
6258 && (mips_opts.at || mips_pic == NO_PIC)
6259 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
6260 as they have no complementing branches. */
6261 && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP)));
6263 if (!HAVE_CODE_COMPRESSION
6266 && *reloc_type == BFD_RELOC_16_PCREL_S2
6267 && delayed_branch_p (ip))
6269 relaxed_branch = TRUE;
6270 add_relaxed_insn (ip, (relaxed_branch_length
6272 uncond_branch_p (ip) ? -1
6273 : branch_likely_p (ip) ? 1
6277 uncond_branch_p (ip),
6278 branch_likely_p (ip),
6279 pinfo & INSN_WRITE_GPR_31,
6281 address_expr->X_add_symbol,
6282 address_expr->X_add_number);
6283 *reloc_type = BFD_RELOC_UNUSED;
6285 else if (mips_opts.micromips
6287 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
6288 || *reloc_type > BFD_RELOC_UNUSED)
6289 && (delayed_branch_p (ip) || compact_branch_p (ip))
6290 /* Don't try branch relaxation when users specify
6291 16-bit/32-bit instructions. */
6292 && !forced_insn_length)
6294 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
6295 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
6296 int uncond = uncond_branch_p (ip) ? -1 : 0;
6297 int compact = compact_branch_p (ip);
6298 int al = pinfo & INSN_WRITE_GPR_31;
6301 gas_assert (address_expr != NULL);
6302 gas_assert (!mips_relax.sequence);
6304 relaxed_branch = TRUE;
6305 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
6306 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
6307 RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al,
6309 address_expr->X_add_symbol,
6310 address_expr->X_add_number);
6311 *reloc_type = BFD_RELOC_UNUSED;
6313 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
6315 /* We need to set up a variant frag. */
6316 gas_assert (address_expr != NULL);
6317 add_relaxed_insn (ip, 4, 0,
6319 (*reloc_type - BFD_RELOC_UNUSED,
6320 forced_insn_length == 2, forced_insn_length == 4,
6321 delayed_branch_p (&history[0]),
6322 history[0].mips16_absolute_jump_p),
6323 make_expr_symbol (address_expr), 0);
6325 else if (mips_opts.mips16 && insn_length (ip) == 2)
6327 if (!delayed_branch_p (ip))
6328 /* Make sure there is enough room to swap this instruction with
6329 a following jump instruction. */
6331 add_fixed_insn (ip);
6335 if (mips_opts.mips16
6336 && mips_opts.noreorder
6337 && delayed_branch_p (&history[0]))
6338 as_warn (_("extended instruction in delay slot"));
6340 if (mips_relax.sequence)
6342 /* If we've reached the end of this frag, turn it into a variant
6343 frag and record the information for the instructions we've
6345 if (frag_room () < 4)
6346 relax_close_frag ();
6347 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
6350 if (mips_relax.sequence != 2)
6352 if (mips_macro_warning.first_insn_sizes[0] == 0)
6353 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
6354 mips_macro_warning.sizes[0] += insn_length (ip);
6355 mips_macro_warning.insns[0]++;
6357 if (mips_relax.sequence != 1)
6359 if (mips_macro_warning.first_insn_sizes[1] == 0)
6360 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
6361 mips_macro_warning.sizes[1] += insn_length (ip);
6362 mips_macro_warning.insns[1]++;
6365 if (mips_opts.mips16)
6368 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
6370 add_fixed_insn (ip);
6373 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
6375 bfd_reloc_code_real_type final_type[3];
6376 reloc_howto_type *howto0;
6377 reloc_howto_type *howto;
6380 /* Perform any necessary conversion to microMIPS relocations
6381 and find out how many relocations there actually are. */
6382 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
6383 final_type[i] = micromips_map_reloc (reloc_type[i]);
6385 /* In a compound relocation, it is the final (outermost)
6386 operator that determines the relocated field. */
6387 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
6392 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
6393 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
6394 bfd_get_reloc_size (howto),
6396 howto0 && howto0->pc_relative,
6399 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
6400 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
6401 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
6403 /* These relocations can have an addend that won't fit in
6404 4 octets for 64bit assembly. */
6406 && ! howto->partial_inplace
6407 && (reloc_type[0] == BFD_RELOC_16
6408 || reloc_type[0] == BFD_RELOC_32
6409 || reloc_type[0] == BFD_RELOC_MIPS_JMP
6410 || reloc_type[0] == BFD_RELOC_GPREL16
6411 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
6412 || reloc_type[0] == BFD_RELOC_GPREL32
6413 || reloc_type[0] == BFD_RELOC_64
6414 || reloc_type[0] == BFD_RELOC_CTOR
6415 || reloc_type[0] == BFD_RELOC_MIPS_SUB
6416 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
6417 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
6418 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
6419 || reloc_type[0] == BFD_RELOC_MIPS_REL16
6420 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
6421 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
6422 || hi16_reloc_p (reloc_type[0])
6423 || lo16_reloc_p (reloc_type[0])))
6424 ip->fixp[0]->fx_no_overflow = 1;
6426 /* These relocations can have an addend that won't fit in 2 octets. */
6427 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
6428 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1)
6429 ip->fixp[0]->fx_no_overflow = 1;
6431 if (mips_relax.sequence)
6433 if (mips_relax.first_fixup == 0)
6434 mips_relax.first_fixup = ip->fixp[0];
6436 else if (reloc_needs_lo_p (*reloc_type))
6438 struct mips_hi_fixup *hi_fixup;
6440 /* Reuse the last entry if it already has a matching %lo. */
6441 hi_fixup = mips_hi_fixup_list;
6443 || !fixup_has_matching_lo_p (hi_fixup->fixp))
6445 hi_fixup = ((struct mips_hi_fixup *)
6446 xmalloc (sizeof (struct mips_hi_fixup)));
6447 hi_fixup->next = mips_hi_fixup_list;
6448 mips_hi_fixup_list = hi_fixup;
6450 hi_fixup->fixp = ip->fixp[0];
6451 hi_fixup->seg = now_seg;
6454 /* Add fixups for the second and third relocations, if given.
6455 Note that the ABI allows the second relocation to be
6456 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
6457 moment we only use RSS_UNDEF, but we could add support
6458 for the others if it ever becomes necessary. */
6459 for (i = 1; i < 3; i++)
6460 if (reloc_type[i] != BFD_RELOC_UNUSED)
6462 ip->fixp[i] = fix_new (ip->frag, ip->where,
6463 ip->fixp[0]->fx_size, NULL, 0,
6464 FALSE, final_type[i]);
6466 /* Use fx_tcbit to mark compound relocs. */
6467 ip->fixp[0]->fx_tcbit = 1;
6468 ip->fixp[i]->fx_tcbit = 1;
6473 /* Update the register mask information. */
6474 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
6475 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
6480 insert_into_history (0, 1, ip);
6483 case APPEND_ADD_WITH_NOP:
6485 struct mips_cl_insn *nop;
6487 insert_into_history (0, 1, ip);
6488 nop = get_delay_slot_nop (ip);
6489 add_fixed_insn (nop);
6490 insert_into_history (0, 1, nop);
6491 if (mips_relax.sequence)
6492 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
6496 case APPEND_ADD_COMPACT:
6497 /* Convert MIPS16 jr/jalr into a "compact" jump. */
6498 gas_assert (mips_opts.mips16);
6499 ip->insn_opcode |= 0x0080;
6500 find_altered_mips16_opcode (ip);
6502 insert_into_history (0, 1, ip);
6507 struct mips_cl_insn delay = history[0];
6508 if (mips_opts.mips16)
6510 know (delay.frag == ip->frag);
6511 move_insn (ip, delay.frag, delay.where);
6512 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
6514 else if (relaxed_branch || delay.frag != ip->frag)
6516 /* Add the delay slot instruction to the end of the
6517 current frag and shrink the fixed part of the
6518 original frag. If the branch occupies the tail of
6519 the latter, move it backwards to cover the gap. */
6520 delay.frag->fr_fix -= branch_disp;
6521 if (delay.frag == ip->frag)
6522 move_insn (ip, ip->frag, ip->where - branch_disp);
6523 add_fixed_insn (&delay);
6527 move_insn (&delay, ip->frag,
6528 ip->where - branch_disp + insn_length (ip));
6529 move_insn (ip, history[0].frag, history[0].where);
6533 insert_into_history (0, 1, &delay);
6538 /* If we have just completed an unconditional branch, clear the history. */
6539 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
6540 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
6544 mips_no_prev_insn ();
6546 for (i = 0; i < ARRAY_SIZE (history); i++)
6547 history[i].cleared_p = 1;
6550 /* We need to emit a label at the end of branch-likely macros. */
6551 if (emit_branch_likely_macro)
6553 emit_branch_likely_macro = FALSE;
6554 micromips_add_label ();
6557 /* We just output an insn, so the next one doesn't have a label. */
6558 mips_clear_insn_labels ();
6561 /* Forget that there was any previous instruction or label.
6562 When BRANCH is true, the branch history is also flushed. */
6565 mips_no_prev_insn (void)
6567 prev_nop_frag = NULL;
6568 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
6569 mips_clear_insn_labels ();
6572 /* This function must be called before we emit something other than
6573 instructions. It is like mips_no_prev_insn except that it inserts
6574 any NOPS that might be needed by previous instructions. */
6577 mips_emit_delays (void)
6579 if (! mips_opts.noreorder)
6581 int nops = nops_for_insn (0, history, NULL);
6585 add_fixed_insn (NOP_INSN);
6586 mips_move_text_labels ();
6589 mips_no_prev_insn ();
6592 /* Start a (possibly nested) noreorder block. */
6595 start_noreorder (void)
6597 if (mips_opts.noreorder == 0)
6602 /* None of the instructions before the .set noreorder can be moved. */
6603 for (i = 0; i < ARRAY_SIZE (history); i++)
6604 history[i].fixed_p = 1;
6606 /* Insert any nops that might be needed between the .set noreorder
6607 block and the previous instructions. We will later remove any
6608 nops that turn out not to be needed. */
6609 nops = nops_for_insn (0, history, NULL);
6612 if (mips_optimize != 0)
6614 /* Record the frag which holds the nop instructions, so
6615 that we can remove them if we don't need them. */
6616 frag_grow (nops * NOP_INSN_SIZE);
6617 prev_nop_frag = frag_now;
6618 prev_nop_frag_holds = nops;
6619 prev_nop_frag_required = 0;
6620 prev_nop_frag_since = 0;
6623 for (; nops > 0; --nops)
6624 add_fixed_insn (NOP_INSN);
6626 /* Move on to a new frag, so that it is safe to simply
6627 decrease the size of prev_nop_frag. */
6628 frag_wane (frag_now);
6630 mips_move_text_labels ();
6632 mips_mark_labels ();
6633 mips_clear_insn_labels ();
6635 mips_opts.noreorder++;
6636 mips_any_noreorder = 1;
6639 /* End a nested noreorder block. */
6642 end_noreorder (void)
6644 mips_opts.noreorder--;
6645 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
6647 /* Commit to inserting prev_nop_frag_required nops and go back to
6648 handling nop insertion the .set reorder way. */
6649 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
6651 insert_into_history (prev_nop_frag_since,
6652 prev_nop_frag_required, NOP_INSN);
6653 prev_nop_frag = NULL;
6657 /* Set up global variables for the start of a new macro. */
6662 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
6663 memset (&mips_macro_warning.first_insn_sizes, 0,
6664 sizeof (mips_macro_warning.first_insn_sizes));
6665 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
6666 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
6667 && delayed_branch_p (&history[0]));
6668 switch (history[0].insn_mo->pinfo2
6669 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
6671 case INSN2_BRANCH_DELAY_32BIT:
6672 mips_macro_warning.delay_slot_length = 4;
6674 case INSN2_BRANCH_DELAY_16BIT:
6675 mips_macro_warning.delay_slot_length = 2;
6678 mips_macro_warning.delay_slot_length = 0;
6681 mips_macro_warning.first_frag = NULL;
6684 /* Given that a macro is longer than one instruction or of the wrong size,
6685 return the appropriate warning for it. Return null if no warning is
6686 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
6687 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
6688 and RELAX_NOMACRO. */
6691 macro_warning (relax_substateT subtype)
6693 if (subtype & RELAX_DELAY_SLOT)
6694 return _("Macro instruction expanded into multiple instructions"
6695 " in a branch delay slot");
6696 else if (subtype & RELAX_NOMACRO)
6697 return _("Macro instruction expanded into multiple instructions");
6698 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
6699 | RELAX_DELAY_SLOT_SIZE_SECOND))
6700 return ((subtype & RELAX_DELAY_SLOT_16BIT)
6701 ? _("Macro instruction expanded into a wrong size instruction"
6702 " in a 16-bit branch delay slot")
6703 : _("Macro instruction expanded into a wrong size instruction"
6704 " in a 32-bit branch delay slot"));
6709 /* Finish up a macro. Emit warnings as appropriate. */
6714 /* Relaxation warning flags. */
6715 relax_substateT subtype = 0;
6717 /* Check delay slot size requirements. */
6718 if (mips_macro_warning.delay_slot_length == 2)
6719 subtype |= RELAX_DELAY_SLOT_16BIT;
6720 if (mips_macro_warning.delay_slot_length != 0)
6722 if (mips_macro_warning.delay_slot_length
6723 != mips_macro_warning.first_insn_sizes[0])
6724 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
6725 if (mips_macro_warning.delay_slot_length
6726 != mips_macro_warning.first_insn_sizes[1])
6727 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
6730 /* Check instruction count requirements. */
6731 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
6733 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
6734 subtype |= RELAX_SECOND_LONGER;
6735 if (mips_opts.warn_about_macros)
6736 subtype |= RELAX_NOMACRO;
6737 if (mips_macro_warning.delay_slot_p)
6738 subtype |= RELAX_DELAY_SLOT;
6741 /* If both alternatives fail to fill a delay slot correctly,
6742 emit the warning now. */
6743 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
6744 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
6749 s = subtype & (RELAX_DELAY_SLOT_16BIT
6750 | RELAX_DELAY_SLOT_SIZE_FIRST
6751 | RELAX_DELAY_SLOT_SIZE_SECOND);
6752 msg = macro_warning (s);
6754 as_warn ("%s", msg);
6758 /* If both implementations are longer than 1 instruction, then emit the
6760 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
6765 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
6766 msg = macro_warning (s);
6768 as_warn ("%s", msg);
6772 /* If any flags still set, then one implementation might need a warning
6773 and the other either will need one of a different kind or none at all.
6774 Pass any remaining flags over to relaxation. */
6775 if (mips_macro_warning.first_frag != NULL)
6776 mips_macro_warning.first_frag->fr_subtype |= subtype;
6779 /* Instruction operand formats used in macros that vary between
6780 standard MIPS and microMIPS code. */
6782 static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } };
6783 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
6784 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
6785 static const char * const lui_fmt[2] = { "t,u", "s,u" };
6786 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
6787 static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } };
6788 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
6789 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
6791 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
6792 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
6793 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
6794 #define LUI_FMT (lui_fmt[mips_opts.micromips])
6795 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
6796 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
6797 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
6798 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
6800 /* Read a macro's relocation codes from *ARGS and store them in *R.
6801 The first argument in *ARGS will be either the code for a single
6802 relocation or -1 followed by the three codes that make up a
6803 composite relocation. */
6806 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
6810 next = va_arg (*args, int);
6812 r[0] = (bfd_reloc_code_real_type) next;
6815 for (i = 0; i < 3; i++)
6816 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
6817 /* This function is only used for 16-bit relocation fields.
6818 To make the macro code simpler, treat an unrelocated value
6819 in the same way as BFD_RELOC_LO16. */
6820 if (r[0] == BFD_RELOC_UNUSED)
6821 r[0] = BFD_RELOC_LO16;
6825 /* Build an instruction created by a macro expansion. This is passed
6826 a pointer to the count of instructions created so far, an
6827 expression, the name of the instruction to build, an operand format
6828 string, and corresponding arguments. */
6831 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
6833 const struct mips_opcode *mo = NULL;
6834 bfd_reloc_code_real_type r[3];
6835 const struct mips_opcode *amo;
6836 const struct mips_operand *operand;
6837 struct hash_control *hash;
6838 struct mips_cl_insn insn;
6842 va_start (args, fmt);
6844 if (mips_opts.mips16)
6846 mips16_macro_build (ep, name, fmt, &args);
6851 r[0] = BFD_RELOC_UNUSED;
6852 r[1] = BFD_RELOC_UNUSED;
6853 r[2] = BFD_RELOC_UNUSED;
6854 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
6855 amo = (struct mips_opcode *) hash_find (hash, name);
6857 gas_assert (strcmp (name, amo->name) == 0);
6861 /* Search until we get a match for NAME. It is assumed here that
6862 macros will never generate MDMX, MIPS-3D, or MT instructions.
6863 We try to match an instruction that fulfils the branch delay
6864 slot instruction length requirement (if any) of the previous
6865 instruction. While doing this we record the first instruction
6866 seen that matches all the other conditions and use it anyway
6867 if the requirement cannot be met; we will issue an appropriate
6868 warning later on. */
6869 if (strcmp (fmt, amo->args) == 0
6870 && amo->pinfo != INSN_MACRO
6871 && is_opcode_valid (amo)
6872 && is_size_valid (amo))
6874 if (is_delay_slot_valid (amo))
6884 gas_assert (amo->name);
6886 while (strcmp (name, amo->name) == 0);
6889 create_insn (&insn, mo);
6902 macro_read_relocs (&args, r);
6903 gas_assert (*r == BFD_RELOC_GPREL16
6904 || *r == BFD_RELOC_MIPS_HIGHER
6905 || *r == BFD_RELOC_HI16_S
6906 || *r == BFD_RELOC_LO16
6907 || *r == BFD_RELOC_MIPS_GOT_OFST);
6911 macro_read_relocs (&args, r);
6915 macro_read_relocs (&args, r);
6916 gas_assert (ep != NULL
6917 && (ep->X_op == O_constant
6918 || (ep->X_op == O_symbol
6919 && (*r == BFD_RELOC_MIPS_HIGHEST
6920 || *r == BFD_RELOC_HI16_S
6921 || *r == BFD_RELOC_HI16
6922 || *r == BFD_RELOC_GPREL16
6923 || *r == BFD_RELOC_MIPS_GOT_HI16
6924 || *r == BFD_RELOC_MIPS_CALL_HI16))));
6928 gas_assert (ep != NULL);
6931 * This allows macro() to pass an immediate expression for
6932 * creating short branches without creating a symbol.
6934 * We don't allow branch relaxation for these branches, as
6935 * they should only appear in ".set nomacro" anyway.
6937 if (ep->X_op == O_constant)
6939 /* For microMIPS we always use relocations for branches.
6940 So we should not resolve immediate values. */
6941 gas_assert (!mips_opts.micromips);
6943 if ((ep->X_add_number & 3) != 0)
6944 as_bad (_("branch to misaligned address (0x%lx)"),
6945 (unsigned long) ep->X_add_number);
6946 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
6947 as_bad (_("branch address range overflow (0x%lx)"),
6948 (unsigned long) ep->X_add_number);
6949 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
6953 *r = BFD_RELOC_16_PCREL_S2;
6957 gas_assert (ep != NULL);
6958 *r = BFD_RELOC_MIPS_JMP;
6962 operand = (mips_opts.micromips
6963 ? decode_micromips_operand (fmt)
6964 : decode_mips_operand (fmt));
6968 uval = va_arg (args, int);
6969 if (operand->type == OP_CLO_CLZ_DEST)
6970 uval |= (uval << 5);
6971 insn_insert_operand (&insn, operand, uval);
6973 if (*fmt == '+' || *fmt == 'm')
6979 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
6981 append_insn (&insn, ep, r, TRUE);
6985 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
6988 struct mips_opcode *mo;
6989 struct mips_cl_insn insn;
6990 const struct mips_operand *operand;
6991 bfd_reloc_code_real_type r[3]
6992 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
6994 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
6996 gas_assert (strcmp (name, mo->name) == 0);
6998 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
7001 gas_assert (mo->name);
7002 gas_assert (strcmp (name, mo->name) == 0);
7005 create_insn (&insn, mo);
7043 gas_assert (ep != NULL);
7045 if (ep->X_op != O_constant)
7046 *r = (int) BFD_RELOC_UNUSED + c;
7047 else if (calculate_reloc (*r, ep->X_add_number, &value))
7049 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode);
7051 *r = BFD_RELOC_UNUSED;
7057 operand = decode_mips16_operand (c, FALSE);
7061 insn_insert_operand (&insn, operand, va_arg (*args, int));
7066 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
7068 append_insn (&insn, ep, r, TRUE);
7072 * Sign-extend 32-bit mode constants that have bit 31 set and all
7073 * higher bits unset.
7076 normalize_constant_expr (expressionS *ex)
7078 if (ex->X_op == O_constant
7079 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7080 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7085 * Sign-extend 32-bit mode address offsets that have bit 31 set and
7086 * all higher bits unset.
7089 normalize_address_expr (expressionS *ex)
7091 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
7092 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
7093 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7094 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7099 * Generate a "jalr" instruction with a relocation hint to the called
7100 * function. This occurs in NewABI PIC code.
7103 macro_build_jalr (expressionS *ep, int cprestore)
7105 static const bfd_reloc_code_real_type jalr_relocs[2]
7106 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
7107 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
7111 if (MIPS_JALR_HINT_P (ep))
7116 if (mips_opts.micromips)
7118 jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32
7119 ? "jalr" : "jalrs");
7120 if (MIPS_JALR_HINT_P (ep)
7122 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
7123 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
7125 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
7128 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
7129 if (MIPS_JALR_HINT_P (ep))
7130 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
7134 * Generate a "lui" instruction.
7137 macro_build_lui (expressionS *ep, int regnum)
7139 gas_assert (! mips_opts.mips16);
7141 if (ep->X_op != O_constant)
7143 gas_assert (ep->X_op == O_symbol);
7144 /* _gp_disp is a special case, used from s_cpload.
7145 __gnu_local_gp is used if mips_no_shared. */
7146 gas_assert (mips_pic == NO_PIC
7148 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
7149 || (! mips_in_shared
7150 && strcmp (S_GET_NAME (ep->X_add_symbol),
7151 "__gnu_local_gp") == 0));
7154 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
7157 /* Generate a sequence of instructions to do a load or store from a constant
7158 offset off of a base register (breg) into/from a target register (treg),
7159 using AT if necessary. */
7161 macro_build_ldst_constoffset (expressionS *ep, const char *op,
7162 int treg, int breg, int dbl)
7164 gas_assert (ep->X_op == O_constant);
7166 /* Sign-extending 32-bit constants makes their handling easier. */
7168 normalize_constant_expr (ep);
7170 /* Right now, this routine can only handle signed 32-bit constants. */
7171 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
7172 as_warn (_("operand overflow"));
7174 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
7176 /* Signed 16-bit offset will fit in the op. Easy! */
7177 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
7181 /* 32-bit offset, need multiple instructions and AT, like:
7182 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
7183 addu $tempreg,$tempreg,$breg
7184 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
7185 to handle the complete offset. */
7186 macro_build_lui (ep, AT);
7187 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7188 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7191 as_bad (_("Macro used $at after \".set noat\""));
7196 * Generates code to set the $at register to true (one)
7197 * if reg is less than the immediate expression.
7200 set_at (int reg, int unsignedp)
7202 if (imm_expr.X_op == O_constant
7203 && imm_expr.X_add_number >= -0x8000
7204 && imm_expr.X_add_number < 0x8000)
7205 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
7206 AT, reg, BFD_RELOC_LO16);
7209 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7210 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
7214 /* Count the leading zeroes by performing a binary chop. This is a
7215 bulky bit of source, but performance is a LOT better for the
7216 majority of values than a simple loop to count the bits:
7217 for (lcnt = 0; (lcnt < 32); lcnt++)
7218 if ((v) & (1 << (31 - lcnt)))
7220 However it is not code size friendly, and the gain will drop a bit
7221 on certain cached systems.
7223 #define COUNT_TOP_ZEROES(v) \
7224 (((v) & ~0xffff) == 0 \
7225 ? ((v) & ~0xff) == 0 \
7226 ? ((v) & ~0xf) == 0 \
7227 ? ((v) & ~0x3) == 0 \
7228 ? ((v) & ~0x1) == 0 \
7233 : ((v) & ~0x7) == 0 \
7236 : ((v) & ~0x3f) == 0 \
7237 ? ((v) & ~0x1f) == 0 \
7240 : ((v) & ~0x7f) == 0 \
7243 : ((v) & ~0xfff) == 0 \
7244 ? ((v) & ~0x3ff) == 0 \
7245 ? ((v) & ~0x1ff) == 0 \
7248 : ((v) & ~0x7ff) == 0 \
7251 : ((v) & ~0x3fff) == 0 \
7252 ? ((v) & ~0x1fff) == 0 \
7255 : ((v) & ~0x7fff) == 0 \
7258 : ((v) & ~0xffffff) == 0 \
7259 ? ((v) & ~0xfffff) == 0 \
7260 ? ((v) & ~0x3ffff) == 0 \
7261 ? ((v) & ~0x1ffff) == 0 \
7264 : ((v) & ~0x7ffff) == 0 \
7267 : ((v) & ~0x3fffff) == 0 \
7268 ? ((v) & ~0x1fffff) == 0 \
7271 : ((v) & ~0x7fffff) == 0 \
7274 : ((v) & ~0xfffffff) == 0 \
7275 ? ((v) & ~0x3ffffff) == 0 \
7276 ? ((v) & ~0x1ffffff) == 0 \
7279 : ((v) & ~0x7ffffff) == 0 \
7282 : ((v) & ~0x3fffffff) == 0 \
7283 ? ((v) & ~0x1fffffff) == 0 \
7286 : ((v) & ~0x7fffffff) == 0 \
7291 * This routine generates the least number of instructions necessary to load
7292 * an absolute expression value into a register.
7295 load_register (int reg, expressionS *ep, int dbl)
7298 expressionS hi32, lo32;
7300 if (ep->X_op != O_big)
7302 gas_assert (ep->X_op == O_constant);
7304 /* Sign-extending 32-bit constants makes their handling easier. */
7306 normalize_constant_expr (ep);
7308 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
7310 /* We can handle 16 bit signed values with an addiu to
7311 $zero. No need to ever use daddiu here, since $zero and
7312 the result are always correct in 32 bit mode. */
7313 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
7316 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
7318 /* We can handle 16 bit unsigned values with an ori to
7320 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
7323 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
7325 /* 32 bit values require an lui. */
7326 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
7327 if ((ep->X_add_number & 0xffff) != 0)
7328 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
7333 /* The value is larger than 32 bits. */
7335 if (!dbl || HAVE_32BIT_GPRS)
7339 sprintf_vma (value, ep->X_add_number);
7340 as_bad (_("Number (0x%s) larger than 32 bits"), value);
7341 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
7345 if (ep->X_op != O_big)
7348 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
7349 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
7350 hi32.X_add_number &= 0xffffffff;
7352 lo32.X_add_number &= 0xffffffff;
7356 gas_assert (ep->X_add_number > 2);
7357 if (ep->X_add_number == 3)
7358 generic_bignum[3] = 0;
7359 else if (ep->X_add_number > 4)
7360 as_bad (_("Number larger than 64 bits"));
7361 lo32.X_op = O_constant;
7362 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
7363 hi32.X_op = O_constant;
7364 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
7367 if (hi32.X_add_number == 0)
7372 unsigned long hi, lo;
7374 if (hi32.X_add_number == (offsetT) 0xffffffff)
7376 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
7378 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
7381 if (lo32.X_add_number & 0x80000000)
7383 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
7384 if (lo32.X_add_number & 0xffff)
7385 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
7390 /* Check for 16bit shifted constant. We know that hi32 is
7391 non-zero, so start the mask on the first bit of the hi32
7396 unsigned long himask, lomask;
7400 himask = 0xffff >> (32 - shift);
7401 lomask = (0xffff << shift) & 0xffffffff;
7405 himask = 0xffff << (shift - 32);
7408 if ((hi32.X_add_number & ~(offsetT) himask) == 0
7409 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
7413 tmp.X_op = O_constant;
7415 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
7416 | (lo32.X_add_number >> shift));
7418 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
7419 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
7420 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
7421 reg, reg, (shift >= 32) ? shift - 32 : shift);
7426 while (shift <= (64 - 16));
7428 /* Find the bit number of the lowest one bit, and store the
7429 shifted value in hi/lo. */
7430 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
7431 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
7435 while ((lo & 1) == 0)
7440 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
7446 while ((hi & 1) == 0)
7455 /* Optimize if the shifted value is a (power of 2) - 1. */
7456 if ((hi == 0 && ((lo + 1) & lo) == 0)
7457 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
7459 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
7464 /* This instruction will set the register to be all
7466 tmp.X_op = O_constant;
7467 tmp.X_add_number = (offsetT) -1;
7468 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
7472 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
7473 reg, reg, (bit >= 32) ? bit - 32 : bit);
7475 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
7476 reg, reg, (shift >= 32) ? shift - 32 : shift);
7481 /* Sign extend hi32 before calling load_register, because we can
7482 generally get better code when we load a sign extended value. */
7483 if ((hi32.X_add_number & 0x80000000) != 0)
7484 hi32.X_add_number |= ~(offsetT) 0xffffffff;
7485 load_register (reg, &hi32, 0);
7488 if ((lo32.X_add_number & 0xffff0000) == 0)
7492 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
7500 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
7502 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
7503 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
7509 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
7513 mid16.X_add_number >>= 16;
7514 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
7515 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
7518 if ((lo32.X_add_number & 0xffff) != 0)
7519 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
7523 load_delay_nop (void)
7525 if (!gpr_interlocks)
7526 macro_build (NULL, "nop", "");
7529 /* Load an address into a register. */
7532 load_address (int reg, expressionS *ep, int *used_at)
7534 if (ep->X_op != O_constant
7535 && ep->X_op != O_symbol)
7537 as_bad (_("expression too complex"));
7538 ep->X_op = O_constant;
7541 if (ep->X_op == O_constant)
7543 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
7547 if (mips_pic == NO_PIC)
7549 /* If this is a reference to a GP relative symbol, we want
7550 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
7552 lui $reg,<sym> (BFD_RELOC_HI16_S)
7553 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
7554 If we have an addend, we always use the latter form.
7556 With 64bit address space and a usable $at we want
7557 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7558 lui $at,<sym> (BFD_RELOC_HI16_S)
7559 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
7560 daddiu $at,<sym> (BFD_RELOC_LO16)
7564 If $at is already in use, we use a path which is suboptimal
7565 on superscalar processors.
7566 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7567 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
7569 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
7571 daddiu $reg,<sym> (BFD_RELOC_LO16)
7573 For GP relative symbols in 64bit address space we can use
7574 the same sequence as in 32bit address space. */
7575 if (HAVE_64BIT_SYMBOLS)
7577 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
7578 && !nopic_need_relax (ep->X_add_symbol, 1))
7580 relax_start (ep->X_add_symbol);
7581 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
7582 mips_gp_register, BFD_RELOC_GPREL16);
7586 if (*used_at == 0 && mips_opts.at)
7588 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
7589 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
7590 macro_build (ep, "daddiu", "t,r,j", reg, reg,
7591 BFD_RELOC_MIPS_HIGHER);
7592 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
7593 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
7594 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
7599 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
7600 macro_build (ep, "daddiu", "t,r,j", reg, reg,
7601 BFD_RELOC_MIPS_HIGHER);
7602 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
7603 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
7604 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
7605 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
7608 if (mips_relax.sequence)
7613 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
7614 && !nopic_need_relax (ep->X_add_symbol, 1))
7616 relax_start (ep->X_add_symbol);
7617 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
7618 mips_gp_register, BFD_RELOC_GPREL16);
7621 macro_build_lui (ep, reg);
7622 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
7623 reg, reg, BFD_RELOC_LO16);
7624 if (mips_relax.sequence)
7628 else if (!mips_big_got)
7632 /* If this is a reference to an external symbol, we want
7633 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7635 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7637 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
7638 If there is a constant, it must be added in after.
7640 If we have NewABI, we want
7641 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7642 unless we're referencing a global symbol with a non-zero
7643 offset, in which case cst must be added separately. */
7646 if (ep->X_add_number)
7648 ex.X_add_number = ep->X_add_number;
7649 ep->X_add_number = 0;
7650 relax_start (ep->X_add_symbol);
7651 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
7652 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7653 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
7654 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7655 ex.X_op = O_constant;
7656 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
7657 reg, reg, BFD_RELOC_LO16);
7658 ep->X_add_number = ex.X_add_number;
7661 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
7662 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7663 if (mips_relax.sequence)
7668 ex.X_add_number = ep->X_add_number;
7669 ep->X_add_number = 0;
7670 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
7671 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7673 relax_start (ep->X_add_symbol);
7675 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
7679 if (ex.X_add_number != 0)
7681 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
7682 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7683 ex.X_op = O_constant;
7684 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
7685 reg, reg, BFD_RELOC_LO16);
7689 else if (mips_big_got)
7693 /* This is the large GOT case. If this is a reference to an
7694 external symbol, we want
7695 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7697 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
7699 Otherwise, for a reference to a local symbol in old ABI, we want
7700 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7702 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
7703 If there is a constant, it must be added in after.
7705 In the NewABI, for local symbols, with or without offsets, we want:
7706 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7707 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
7711 ex.X_add_number = ep->X_add_number;
7712 ep->X_add_number = 0;
7713 relax_start (ep->X_add_symbol);
7714 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
7715 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7716 reg, reg, mips_gp_register);
7717 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
7718 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
7719 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
7720 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7721 else if (ex.X_add_number)
7723 ex.X_op = O_constant;
7724 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
7728 ep->X_add_number = ex.X_add_number;
7730 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
7731 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
7732 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
7733 BFD_RELOC_MIPS_GOT_OFST);
7738 ex.X_add_number = ep->X_add_number;
7739 ep->X_add_number = 0;
7740 relax_start (ep->X_add_symbol);
7741 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
7742 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7743 reg, reg, mips_gp_register);
7744 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
7745 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
7747 if (reg_needs_delay (mips_gp_register))
7749 /* We need a nop before loading from $gp. This special
7750 check is required because the lui which starts the main
7751 instruction stream does not refer to $gp, and so will not
7752 insert the nop which may be required. */
7753 macro_build (NULL, "nop", "");
7755 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
7756 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7758 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
7762 if (ex.X_add_number != 0)
7764 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
7765 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7766 ex.X_op = O_constant;
7767 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
7775 if (!mips_opts.at && *used_at == 1)
7776 as_bad (_("Macro used $at after \".set noat\""));
7779 /* Move the contents of register SOURCE into register DEST. */
7782 move_register (int dest, int source)
7784 /* Prefer to use a 16-bit microMIPS instruction unless the previous
7785 instruction specifically requires a 32-bit one. */
7786 if (mips_opts.micromips
7787 && !mips_opts.insn32
7788 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
7789 macro_build (NULL, "move", "mp,mj", dest, source);
7791 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
7795 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
7796 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
7797 The two alternatives are:
7799 Global symbol Local sybmol
7800 ------------- ------------
7801 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
7803 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
7805 load_got_offset emits the first instruction and add_got_offset
7806 emits the second for a 16-bit offset or add_got_offset_hilo emits
7807 a sequence to add a 32-bit offset using a scratch register. */
7810 load_got_offset (int dest, expressionS *local)
7815 global.X_add_number = 0;
7817 relax_start (local->X_add_symbol);
7818 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
7819 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7821 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
7822 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7827 add_got_offset (int dest, expressionS *local)
7831 global.X_op = O_constant;
7832 global.X_op_symbol = NULL;
7833 global.X_add_symbol = NULL;
7834 global.X_add_number = local->X_add_number;
7836 relax_start (local->X_add_symbol);
7837 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
7838 dest, dest, BFD_RELOC_LO16);
7840 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
7845 add_got_offset_hilo (int dest, expressionS *local, int tmp)
7848 int hold_mips_optimize;
7850 global.X_op = O_constant;
7851 global.X_op_symbol = NULL;
7852 global.X_add_symbol = NULL;
7853 global.X_add_number = local->X_add_number;
7855 relax_start (local->X_add_symbol);
7856 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
7858 /* Set mips_optimize around the lui instruction to avoid
7859 inserting an unnecessary nop after the lw. */
7860 hold_mips_optimize = mips_optimize;
7862 macro_build_lui (&global, tmp);
7863 mips_optimize = hold_mips_optimize;
7864 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
7867 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
7870 /* Emit a sequence of instructions to emulate a branch likely operation.
7871 BR is an ordinary branch corresponding to one to be emulated. BRNEG
7872 is its complementing branch with the original condition negated.
7873 CALL is set if the original branch specified the link operation.
7874 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
7876 Code like this is produced in the noreorder mode:
7881 delay slot (executed only if branch taken)
7889 delay slot (executed only if branch taken)
7892 In the reorder mode the delay slot would be filled with a nop anyway,
7893 so code produced is simply:
7898 This function is used when producing code for the microMIPS ASE that
7899 does not implement branch likely instructions in hardware. */
7902 macro_build_branch_likely (const char *br, const char *brneg,
7903 int call, expressionS *ep, const char *fmt,
7904 unsigned int sreg, unsigned int treg)
7906 int noreorder = mips_opts.noreorder;
7909 gas_assert (mips_opts.micromips);
7913 micromips_label_expr (&expr1);
7914 macro_build (&expr1, brneg, fmt, sreg, treg);
7915 macro_build (NULL, "nop", "");
7916 macro_build (ep, call ? "bal" : "b", "p");
7918 /* Set to true so that append_insn adds a label. */
7919 emit_branch_likely_macro = TRUE;
7923 macro_build (ep, br, fmt, sreg, treg);
7924 macro_build (NULL, "nop", "");
7929 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
7930 the condition code tested. EP specifies the branch target. */
7933 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
7960 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
7963 /* Emit a two-argument branch macro specified by TYPE, using SREG as
7964 the register tested. EP specifies the branch target. */
7967 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
7969 const char *brneg = NULL;
7979 br = mips_opts.micromips ? "bgez" : "bgezl";
7983 gas_assert (mips_opts.micromips);
7984 br = mips_opts.insn32 ? "bgezal" : "bgezals";
7992 br = mips_opts.micromips ? "bgtz" : "bgtzl";
7999 br = mips_opts.micromips ? "blez" : "blezl";
8006 br = mips_opts.micromips ? "bltz" : "bltzl";
8010 gas_assert (mips_opts.micromips);
8011 br = mips_opts.insn32 ? "bltzal" : "bltzals";
8018 if (mips_opts.micromips && brneg)
8019 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
8021 macro_build (ep, br, "s,p", sreg);
8024 /* Emit a three-argument branch macro specified by TYPE, using SREG and
8025 TREG as the registers tested. EP specifies the branch target. */
8028 macro_build_branch_rsrt (int type, expressionS *ep,
8029 unsigned int sreg, unsigned int treg)
8031 const char *brneg = NULL;
8043 br = mips_opts.micromips ? "beq" : "beql";
8052 br = mips_opts.micromips ? "bne" : "bnel";
8058 if (mips_opts.micromips && brneg)
8059 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
8061 macro_build (ep, br, "s,t,p", sreg, treg);
8064 /* Return the high part that should be loaded in order to make the low
8065 part of VALUE accessible using an offset of OFFBITS bits. */
8068 offset_high_part (offsetT value, unsigned int offbits)
8075 bias = 1 << (offbits - 1);
8076 low_mask = bias * 2 - 1;
8077 return (value + bias) & ~low_mask;
8080 /* Return true if the value stored in offset_expr and offset_reloc
8081 fits into a signed offset of OFFBITS bits. RANGE is the maximum
8082 amount that the caller wants to add without inducing overflow
8083 and ALIGN is the known alignment of the value in bytes. */
8086 small_offset_p (unsigned int range, unsigned int align, unsigned int offbits)
8090 /* Accept any relocation operator if overflow isn't a concern. */
8091 if (range < align && *offset_reloc != BFD_RELOC_UNUSED)
8094 /* These relocations are guaranteed not to overflow in correct links. */
8095 if (*offset_reloc == BFD_RELOC_MIPS_LITERAL
8096 || gprel16_reloc_p (*offset_reloc))
8099 if (offset_expr.X_op == O_constant
8100 && offset_high_part (offset_expr.X_add_number, offbits) == 0
8101 && offset_high_part (offset_expr.X_add_number + range, offbits) == 0)
8108 * This routine implements the seemingly endless macro or synthesized
8109 * instructions and addressing modes in the mips assembly language. Many
8110 * of these macros are simple and are similar to each other. These could
8111 * probably be handled by some kind of table or grammar approach instead of
8112 * this verbose method. Others are not simple macros but are more like
8113 * optimizing code generation.
8114 * One interesting optimization is when several store macros appear
8115 * consecutively that would load AT with the upper half of the same address.
8116 * The ensuing load upper instructions are ommited. This implies some kind
8117 * of global optimization. We currently only optimize within a single macro.
8118 * For many of the load and store macros if the address is specified as a
8119 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
8120 * first load register 'at' with zero and use it as the base register. The
8121 * mips assembler simply uses register $zero. Just one tiny optimization
8125 macro (struct mips_cl_insn *ip, char *str)
8127 const struct mips_operand_array *operands;
8128 unsigned int breg, i;
8129 unsigned int tempreg;
8132 expressionS label_expr;
8147 bfd_boolean large_offset;
8149 int hold_mips_optimize;
8151 unsigned int op[MAX_OPERANDS];
8153 gas_assert (! mips_opts.mips16);
8155 operands = insn_operands (ip);
8156 for (i = 0; i < MAX_OPERANDS; i++)
8157 if (operands->operand[i])
8158 op[i] = insn_extract_operand (ip, operands->operand[i]);
8162 mask = ip->insn_mo->mask;
8164 label_expr.X_op = O_constant;
8165 label_expr.X_op_symbol = NULL;
8166 label_expr.X_add_symbol = NULL;
8167 label_expr.X_add_number = 0;
8169 expr1.X_op = O_constant;
8170 expr1.X_op_symbol = NULL;
8171 expr1.X_add_symbol = NULL;
8172 expr1.X_add_number = 1;
8188 if (mips_opts.micromips)
8189 micromips_label_expr (&label_expr);
8191 label_expr.X_add_number = 8;
8192 macro_build (&label_expr, "bgez", "s,p", op[1]);
8194 macro_build (NULL, "nop", "");
8196 move_register (op[0], op[1]);
8197 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", op[0], 0, op[1]);
8198 if (mips_opts.micromips)
8199 micromips_add_label ();
8216 if (!mips_opts.micromips)
8218 if (imm_expr.X_op == O_constant
8219 && imm_expr.X_add_number >= -0x200
8220 && imm_expr.X_add_number < 0x200)
8222 macro_build (NULL, s, "t,r,.", op[0], op[1], imm_expr.X_add_number);
8231 if (imm_expr.X_op == O_constant
8232 && imm_expr.X_add_number >= -0x8000
8233 && imm_expr.X_add_number < 0x8000)
8235 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
8240 load_register (AT, &imm_expr, dbl);
8241 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
8260 if (imm_expr.X_op == O_constant
8261 && imm_expr.X_add_number >= 0
8262 && imm_expr.X_add_number < 0x10000)
8264 if (mask != M_NOR_I)
8265 macro_build (&imm_expr, s, "t,r,i", op[0], op[1], BFD_RELOC_LO16);
8268 macro_build (&imm_expr, "ori", "t,r,i",
8269 op[0], op[1], BFD_RELOC_LO16);
8270 macro_build (NULL, "nor", "d,v,t", op[0], op[0], 0);
8276 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8277 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
8281 switch (imm_expr.X_add_number)
8284 macro_build (NULL, "nop", "");
8287 macro_build (NULL, "packrl.ph", "d,s,t", op[0], op[0], op[1]);
8291 macro_build (NULL, "balign", "t,s,2", op[0], op[1],
8292 (int) imm_expr.X_add_number);
8295 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
8296 (unsigned long) imm_expr.X_add_number);
8305 gas_assert (mips_opts.micromips);
8306 macro_build_branch_ccl (mask, &offset_expr,
8307 EXTRACT_OPERAND (1, BCC, *ip));
8314 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
8320 load_register (op[1], &imm_expr, HAVE_64BIT_GPRS);
8325 macro_build_branch_rsrt (mask, &offset_expr, op[0], op[1]);
8332 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[0]);
8333 else if (op[0] == 0)
8334 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[1]);
8338 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
8339 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8340 &offset_expr, AT, ZERO);
8350 macro_build_branch_rs (mask, &offset_expr, op[0]);
8356 /* Check for > max integer. */
8357 if (imm_expr.X_op == O_constant && imm_expr.X_add_number >= GPR_SMAX)
8360 /* Result is always false. */
8362 macro_build (NULL, "nop", "");
8364 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
8367 if (imm_expr.X_op != O_constant)
8368 as_bad (_("Unsupported large constant"));
8369 ++imm_expr.X_add_number;
8373 if (mask == M_BGEL_I)
8375 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
8377 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
8378 &offset_expr, op[0]);
8381 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
8383 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
8384 &offset_expr, op[0]);
8387 if (imm_expr.X_op == O_constant && imm_expr.X_add_number <= GPR_SMIN)
8390 /* result is always true */
8391 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
8392 macro_build (&offset_expr, "b", "p");
8397 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8398 &offset_expr, AT, ZERO);
8406 else if (op[0] == 0)
8407 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8408 &offset_expr, ZERO, op[1]);
8412 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
8413 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8414 &offset_expr, AT, ZERO);
8423 && imm_expr.X_op == O_constant
8424 && imm_expr.X_add_number == -1))
8426 if (imm_expr.X_op != O_constant)
8427 as_bad (_("Unsupported large constant"));
8428 ++imm_expr.X_add_number;
8432 if (mask == M_BGEUL_I)
8434 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
8436 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
8437 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8438 &offset_expr, op[0], ZERO);
8443 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8444 &offset_expr, AT, ZERO);
8452 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[0]);
8453 else if (op[0] == 0)
8454 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[1]);
8458 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
8459 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8460 &offset_expr, AT, ZERO);
8468 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8469 &offset_expr, op[0], ZERO);
8470 else if (op[0] == 0)
8475 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
8476 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8477 &offset_expr, AT, ZERO);
8485 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
8486 else if (op[0] == 0)
8487 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[1]);
8491 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
8492 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8493 &offset_expr, AT, ZERO);
8500 if (imm_expr.X_op == O_constant && imm_expr.X_add_number >= GPR_SMAX)
8502 if (imm_expr.X_op != O_constant)
8503 as_bad (_("Unsupported large constant"));
8504 ++imm_expr.X_add_number;
8508 if (mask == M_BLTL_I)
8510 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
8511 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
8512 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
8513 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
8518 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8519 &offset_expr, AT, ZERO);
8527 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8528 &offset_expr, op[0], ZERO);
8529 else if (op[0] == 0)
8534 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
8535 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8536 &offset_expr, AT, ZERO);
8545 && imm_expr.X_op == O_constant
8546 && imm_expr.X_add_number == -1))
8548 if (imm_expr.X_op != O_constant)
8549 as_bad (_("Unsupported large constant"));
8550 ++imm_expr.X_add_number;
8554 if (mask == M_BLTUL_I)
8556 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
8558 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
8559 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8560 &offset_expr, op[0], ZERO);
8565 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8566 &offset_expr, AT, ZERO);
8574 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
8575 else if (op[0] == 0)
8576 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[1]);
8580 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
8581 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8582 &offset_expr, AT, ZERO);
8591 else if (op[0] == 0)
8592 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8593 &offset_expr, ZERO, op[1]);
8597 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
8598 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8599 &offset_expr, AT, ZERO);
8605 /* Use unsigned arithmetic. */
8609 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
8611 as_bad (_("Unsupported large constant"));
8616 pos = imm_expr.X_add_number;
8617 size = imm2_expr.X_add_number;
8622 report_bad_range (ip, 3, pos, 0, 63, FALSE);
8625 if (size == 0 || size > 64 || (pos + size - 1) > 63)
8627 report_bad_field (pos, size);
8631 if (size <= 32 && pos < 32)
8636 else if (size <= 32)
8646 macro_build ((expressionS *) NULL, s, fmt, op[0], op[1], (int) pos,
8653 /* Use unsigned arithmetic. */
8657 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
8659 as_bad (_("Unsupported large constant"));
8664 pos = imm_expr.X_add_number;
8665 size = imm2_expr.X_add_number;
8670 report_bad_range (ip, 3, pos, 0, 63, FALSE);
8673 if (size == 0 || size > 64 || (pos + size - 1) > 63)
8675 report_bad_field (pos, size);
8679 if (pos < 32 && (pos + size - 1) < 32)
8694 macro_build ((expressionS *) NULL, s, fmt, op[0], op[1], (int) pos,
8695 (int) (pos + size - 1));
8711 as_warn (_("Divide by zero."));
8713 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
8715 macro_build (NULL, "break", BRK_FMT, 7);
8722 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
8723 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
8727 if (mips_opts.micromips)
8728 micromips_label_expr (&label_expr);
8730 label_expr.X_add_number = 8;
8731 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
8732 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
8733 macro_build (NULL, "break", BRK_FMT, 7);
8734 if (mips_opts.micromips)
8735 micromips_add_label ();
8737 expr1.X_add_number = -1;
8739 load_register (AT, &expr1, dbl);
8740 if (mips_opts.micromips)
8741 micromips_label_expr (&label_expr);
8743 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
8744 macro_build (&label_expr, "bne", "s,t,p", op[2], AT);
8747 expr1.X_add_number = 1;
8748 load_register (AT, &expr1, dbl);
8749 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
8753 expr1.X_add_number = 0x80000000;
8754 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
8758 macro_build (NULL, "teq", TRAP_FMT, op[1], AT, 6);
8759 /* We want to close the noreorder block as soon as possible, so
8760 that later insns are available for delay slot filling. */
8765 if (mips_opts.micromips)
8766 micromips_label_expr (&label_expr);
8768 label_expr.X_add_number = 8;
8769 macro_build (&label_expr, "bne", "s,t,p", op[1], AT);
8770 macro_build (NULL, "nop", "");
8772 /* We want to close the noreorder block as soon as possible, so
8773 that later insns are available for delay slot filling. */
8776 macro_build (NULL, "break", BRK_FMT, 6);
8778 if (mips_opts.micromips)
8779 micromips_add_label ();
8780 macro_build (NULL, s, MFHL_FMT, op[0]);
8819 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
8821 as_warn (_("Divide by zero."));
8823 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
8825 macro_build (NULL, "break", BRK_FMT, 7);
8828 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
8830 if (strcmp (s2, "mflo") == 0)
8831 move_register (op[0], op[1]);
8833 move_register (op[0], ZERO);
8836 if (imm_expr.X_op == O_constant
8837 && imm_expr.X_add_number == -1
8838 && s[strlen (s) - 1] != 'u')
8840 if (strcmp (s2, "mflo") == 0)
8841 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", op[0], op[1]);
8843 move_register (op[0], ZERO);
8848 load_register (AT, &imm_expr, dbl);
8849 macro_build (NULL, s, "z,s,t", op[1], AT);
8850 macro_build (NULL, s2, MFHL_FMT, op[0]);
8872 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
8873 macro_build (NULL, s, "z,s,t", op[1], op[2]);
8874 /* We want to close the noreorder block as soon as possible, so
8875 that later insns are available for delay slot filling. */
8880 if (mips_opts.micromips)
8881 micromips_label_expr (&label_expr);
8883 label_expr.X_add_number = 8;
8884 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
8885 macro_build (NULL, s, "z,s,t", op[1], op[2]);
8887 /* We want to close the noreorder block as soon as possible, so
8888 that later insns are available for delay slot filling. */
8890 macro_build (NULL, "break", BRK_FMT, 7);
8891 if (mips_opts.micromips)
8892 micromips_add_label ();
8894 macro_build (NULL, s2, MFHL_FMT, op[0]);
8906 /* Load the address of a symbol into a register. If breg is not
8907 zero, we then add a base register to it. */
8910 if (dbl && HAVE_32BIT_GPRS)
8911 as_warn (_("dla used to load 32-bit register"));
8913 if (!dbl && HAVE_64BIT_OBJECTS)
8914 as_warn (_("la used to load 64-bit address"));
8916 if (small_offset_p (0, align, 16))
8918 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", op[0], breg,
8919 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
8923 if (mips_opts.at && (op[0] == breg))
8931 if (offset_expr.X_op != O_symbol
8932 && offset_expr.X_op != O_constant)
8934 as_bad (_("Expression too complex"));
8935 offset_expr.X_op = O_constant;
8938 if (offset_expr.X_op == O_constant)
8939 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
8940 else if (mips_pic == NO_PIC)
8942 /* If this is a reference to a GP relative symbol, we want
8943 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
8945 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8946 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8947 If we have a constant, we need two instructions anyhow,
8948 so we may as well always use the latter form.
8950 With 64bit address space and a usable $at we want
8951 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8952 lui $at,<sym> (BFD_RELOC_HI16_S)
8953 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8954 daddiu $at,<sym> (BFD_RELOC_LO16)
8956 daddu $tempreg,$tempreg,$at
8958 If $at is already in use, we use a path which is suboptimal
8959 on superscalar processors.
8960 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8961 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8963 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8965 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
8967 For GP relative symbols in 64bit address space we can use
8968 the same sequence as in 32bit address space. */
8969 if (HAVE_64BIT_SYMBOLS)
8971 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8972 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8974 relax_start (offset_expr.X_add_symbol);
8975 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8976 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
8980 if (used_at == 0 && mips_opts.at)
8982 macro_build (&offset_expr, "lui", LUI_FMT,
8983 tempreg, BFD_RELOC_MIPS_HIGHEST);
8984 macro_build (&offset_expr, "lui", LUI_FMT,
8985 AT, BFD_RELOC_HI16_S);
8986 macro_build (&offset_expr, "daddiu", "t,r,j",
8987 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
8988 macro_build (&offset_expr, "daddiu", "t,r,j",
8989 AT, AT, BFD_RELOC_LO16);
8990 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
8991 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
8996 macro_build (&offset_expr, "lui", LUI_FMT,
8997 tempreg, BFD_RELOC_MIPS_HIGHEST);
8998 macro_build (&offset_expr, "daddiu", "t,r,j",
8999 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
9000 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
9001 macro_build (&offset_expr, "daddiu", "t,r,j",
9002 tempreg, tempreg, BFD_RELOC_HI16_S);
9003 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
9004 macro_build (&offset_expr, "daddiu", "t,r,j",
9005 tempreg, tempreg, BFD_RELOC_LO16);
9008 if (mips_relax.sequence)
9013 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
9014 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
9016 relax_start (offset_expr.X_add_symbol);
9017 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9018 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
9021 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
9022 as_bad (_("Offset too large"));
9023 macro_build_lui (&offset_expr, tempreg);
9024 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9025 tempreg, tempreg, BFD_RELOC_LO16);
9026 if (mips_relax.sequence)
9030 else if (!mips_big_got && !HAVE_NEWABI)
9032 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
9034 /* If this is a reference to an external symbol, and there
9035 is no constant, we want
9036 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9037 or for lca or if tempreg is PIC_CALL_REG
9038 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9039 For a local symbol, we want
9040 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9042 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9044 If we have a small constant, and this is a reference to
9045 an external symbol, we want
9046 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9048 addiu $tempreg,$tempreg,<constant>
9049 For a local symbol, we want the same instruction
9050 sequence, but we output a BFD_RELOC_LO16 reloc on the
9053 If we have a large constant, and this is a reference to
9054 an external symbol, we want
9055 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9056 lui $at,<hiconstant>
9057 addiu $at,$at,<loconstant>
9058 addu $tempreg,$tempreg,$at
9059 For a local symbol, we want the same instruction
9060 sequence, but we output a BFD_RELOC_LO16 reloc on the
9064 if (offset_expr.X_add_number == 0)
9066 if (mips_pic == SVR4_PIC
9068 && (call || tempreg == PIC_CALL_REG))
9069 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
9071 relax_start (offset_expr.X_add_symbol);
9072 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9073 lw_reloc_type, mips_gp_register);
9076 /* We're going to put in an addu instruction using
9077 tempreg, so we may as well insert the nop right
9082 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9083 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
9085 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9086 tempreg, tempreg, BFD_RELOC_LO16);
9088 /* FIXME: If breg == 0, and the next instruction uses
9089 $tempreg, then if this variant case is used an extra
9090 nop will be generated. */
9092 else if (offset_expr.X_add_number >= -0x8000
9093 && offset_expr.X_add_number < 0x8000)
9095 load_got_offset (tempreg, &offset_expr);
9097 add_got_offset (tempreg, &offset_expr);
9101 expr1.X_add_number = offset_expr.X_add_number;
9102 offset_expr.X_add_number =
9103 SEXT_16BIT (offset_expr.X_add_number);
9104 load_got_offset (tempreg, &offset_expr);
9105 offset_expr.X_add_number = expr1.X_add_number;
9106 /* If we are going to add in a base register, and the
9107 target register and the base register are the same,
9108 then we are using AT as a temporary register. Since
9109 we want to load the constant into AT, we add our
9110 current AT (from the global offset table) and the
9111 register into the register now, and pretend we were
9112 not using a base register. */
9116 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9121 add_got_offset_hilo (tempreg, &offset_expr, AT);
9125 else if (!mips_big_got && HAVE_NEWABI)
9127 int add_breg_early = 0;
9129 /* If this is a reference to an external, and there is no
9130 constant, or local symbol (*), with or without a
9132 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9133 or for lca or if tempreg is PIC_CALL_REG
9134 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9136 If we have a small constant, and this is a reference to
9137 an external symbol, we want
9138 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9139 addiu $tempreg,$tempreg,<constant>
9141 If we have a large constant, and this is a reference to
9142 an external symbol, we want
9143 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9144 lui $at,<hiconstant>
9145 addiu $at,$at,<loconstant>
9146 addu $tempreg,$tempreg,$at
9148 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
9149 local symbols, even though it introduces an additional
9152 if (offset_expr.X_add_number)
9154 expr1.X_add_number = offset_expr.X_add_number;
9155 offset_expr.X_add_number = 0;
9157 relax_start (offset_expr.X_add_symbol);
9158 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9159 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9161 if (expr1.X_add_number >= -0x8000
9162 && expr1.X_add_number < 0x8000)
9164 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
9165 tempreg, tempreg, BFD_RELOC_LO16);
9167 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
9171 /* If we are going to add in a base register, and the
9172 target register and the base register are the same,
9173 then we are using AT as a temporary register. Since
9174 we want to load the constant into AT, we add our
9175 current AT (from the global offset table) and the
9176 register into the register now, and pretend we were
9177 not using a base register. */
9182 gas_assert (tempreg == AT);
9183 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9189 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
9190 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9196 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
9199 offset_expr.X_add_number = expr1.X_add_number;
9201 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9202 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9205 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9206 op[0], tempreg, breg);
9212 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
9214 relax_start (offset_expr.X_add_symbol);
9215 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9216 BFD_RELOC_MIPS_CALL16, mips_gp_register);
9218 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9219 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9224 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9225 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9228 else if (mips_big_got && !HAVE_NEWABI)
9231 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
9232 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
9233 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
9235 /* This is the large GOT case. If this is a reference to an
9236 external symbol, and there is no constant, we want
9237 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9238 addu $tempreg,$tempreg,$gp
9239 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9240 or for lca or if tempreg is PIC_CALL_REG
9241 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
9242 addu $tempreg,$tempreg,$gp
9243 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
9244 For a local symbol, we want
9245 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9247 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9249 If we have a small constant, and this is a reference to
9250 an external symbol, we want
9251 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9252 addu $tempreg,$tempreg,$gp
9253 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9255 addiu $tempreg,$tempreg,<constant>
9256 For a local symbol, we want
9257 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9259 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
9261 If we have a large constant, and this is a reference to
9262 an external symbol, we want
9263 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9264 addu $tempreg,$tempreg,$gp
9265 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9266 lui $at,<hiconstant>
9267 addiu $at,$at,<loconstant>
9268 addu $tempreg,$tempreg,$at
9269 For a local symbol, we want
9270 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9271 lui $at,<hiconstant>
9272 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
9273 addu $tempreg,$tempreg,$at
9276 expr1.X_add_number = offset_expr.X_add_number;
9277 offset_expr.X_add_number = 0;
9278 relax_start (offset_expr.X_add_symbol);
9279 gpdelay = reg_needs_delay (mips_gp_register);
9280 if (expr1.X_add_number == 0 && breg == 0
9281 && (call || tempreg == PIC_CALL_REG))
9283 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
9284 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
9286 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
9287 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9288 tempreg, tempreg, mips_gp_register);
9289 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9290 tempreg, lw_reloc_type, tempreg);
9291 if (expr1.X_add_number == 0)
9295 /* We're going to put in an addu instruction using
9296 tempreg, so we may as well insert the nop right
9301 else if (expr1.X_add_number >= -0x8000
9302 && expr1.X_add_number < 0x8000)
9305 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
9306 tempreg, tempreg, BFD_RELOC_LO16);
9312 /* If we are going to add in a base register, and the
9313 target register and the base register are the same,
9314 then we are using AT as a temporary register. Since
9315 we want to load the constant into AT, we add our
9316 current AT (from the global offset table) and the
9317 register into the register now, and pretend we were
9318 not using a base register. */
9323 gas_assert (tempreg == AT);
9325 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9330 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
9331 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
9335 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number);
9340 /* This is needed because this instruction uses $gp, but
9341 the first instruction on the main stream does not. */
9342 macro_build (NULL, "nop", "");
9345 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9346 local_reloc_type, mips_gp_register);
9347 if (expr1.X_add_number >= -0x8000
9348 && expr1.X_add_number < 0x8000)
9351 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9352 tempreg, tempreg, BFD_RELOC_LO16);
9353 /* FIXME: If add_number is 0, and there was no base
9354 register, the external symbol case ended with a load,
9355 so if the symbol turns out to not be external, and
9356 the next instruction uses tempreg, an unnecessary nop
9357 will be inserted. */
9363 /* We must add in the base register now, as in the
9364 external symbol case. */
9365 gas_assert (tempreg == AT);
9367 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9370 /* We set breg to 0 because we have arranged to add
9371 it in in both cases. */
9375 macro_build_lui (&expr1, AT);
9376 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9377 AT, AT, BFD_RELOC_LO16);
9378 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9379 tempreg, tempreg, AT);
9384 else if (mips_big_got && HAVE_NEWABI)
9386 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
9387 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
9388 int add_breg_early = 0;
9390 /* This is the large GOT case. If this is a reference to an
9391 external symbol, and there is no constant, we want
9392 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9393 add $tempreg,$tempreg,$gp
9394 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9395 or for lca or if tempreg is PIC_CALL_REG
9396 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
9397 add $tempreg,$tempreg,$gp
9398 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
9400 If we have a small constant, and this is a reference to
9401 an external symbol, we want
9402 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9403 add $tempreg,$tempreg,$gp
9404 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9405 addi $tempreg,$tempreg,<constant>
9407 If we have a large constant, and this is a reference to
9408 an external symbol, we want
9409 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9410 addu $tempreg,$tempreg,$gp
9411 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9412 lui $at,<hiconstant>
9413 addi $at,$at,<loconstant>
9414 add $tempreg,$tempreg,$at
9416 If we have NewABI, and we know it's a local symbol, we want
9417 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9418 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9419 otherwise we have to resort to GOT_HI16/GOT_LO16. */
9421 relax_start (offset_expr.X_add_symbol);
9423 expr1.X_add_number = offset_expr.X_add_number;
9424 offset_expr.X_add_number = 0;
9426 if (expr1.X_add_number == 0 && breg == 0
9427 && (call || tempreg == PIC_CALL_REG))
9429 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
9430 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
9432 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
9433 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9434 tempreg, tempreg, mips_gp_register);
9435 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9436 tempreg, lw_reloc_type, tempreg);
9438 if (expr1.X_add_number == 0)
9440 else if (expr1.X_add_number >= -0x8000
9441 && expr1.X_add_number < 0x8000)
9443 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
9444 tempreg, tempreg, BFD_RELOC_LO16);
9446 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
9450 /* If we are going to add in a base register, and the
9451 target register and the base register are the same,
9452 then we are using AT as a temporary register. Since
9453 we want to load the constant into AT, we add our
9454 current AT (from the global offset table) and the
9455 register into the register now, and pretend we were
9456 not using a base register. */
9461 gas_assert (tempreg == AT);
9462 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9468 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
9469 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
9474 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
9477 offset_expr.X_add_number = expr1.X_add_number;
9478 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9479 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
9480 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
9481 tempreg, BFD_RELOC_MIPS_GOT_OFST);
9484 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9485 op[0], tempreg, breg);
9495 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", op[0], tempreg, breg);
9499 gas_assert (!mips_opts.micromips);
9500 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x01);
9504 gas_assert (!mips_opts.micromips);
9505 macro_build (NULL, "c2", "C", 0x02);
9509 gas_assert (!mips_opts.micromips);
9510 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x02);
9514 gas_assert (!mips_opts.micromips);
9515 macro_build (NULL, "c2", "C", 3);
9519 gas_assert (!mips_opts.micromips);
9520 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x03);
9524 /* The j instruction may not be used in PIC code, since it
9525 requires an absolute address. We convert it to a b
9527 if (mips_pic == NO_PIC)
9528 macro_build (&offset_expr, "j", "a");
9530 macro_build (&offset_expr, "b", "p");
9533 /* The jal instructions must be handled as macros because when
9534 generating PIC code they expand to multi-instruction
9535 sequences. Normally they are simple instructions. */
9541 gas_assert (mips_opts.micromips);
9542 if (mips_opts.insn32)
9544 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str);
9555 if (mips_pic == NO_PIC)
9557 s = jals ? "jalrs" : "jalr";
9558 if (mips_opts.micromips
9559 && !mips_opts.insn32
9561 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
9562 macro_build (NULL, s, "mj", op[1]);
9564 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
9568 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
9569 && mips_cprestore_offset >= 0);
9571 if (op[1] != PIC_CALL_REG)
9572 as_warn (_("MIPS PIC call to register other than $25"));
9574 s = ((mips_opts.micromips
9575 && !mips_opts.insn32
9576 && (!mips_opts.noreorder || cprestore))
9577 ? "jalrs" : "jalr");
9578 if (mips_opts.micromips
9579 && !mips_opts.insn32
9581 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
9582 macro_build (NULL, s, "mj", op[1]);
9584 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
9585 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
9587 if (mips_cprestore_offset < 0)
9588 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9591 if (!mips_frame_reg_valid)
9593 as_warn (_("No .frame pseudo-op used in PIC code"));
9594 /* Quiet this warning. */
9595 mips_frame_reg_valid = 1;
9597 if (!mips_cprestore_valid)
9599 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9600 /* Quiet this warning. */
9601 mips_cprestore_valid = 1;
9603 if (mips_opts.noreorder)
9604 macro_build (NULL, "nop", "");
9605 expr1.X_add_number = mips_cprestore_offset;
9606 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
9609 HAVE_64BIT_ADDRESSES);
9617 gas_assert (mips_opts.micromips);
9618 if (mips_opts.insn32)
9620 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str);
9626 if (mips_pic == NO_PIC)
9627 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
9628 else if (mips_pic == SVR4_PIC)
9630 /* If this is a reference to an external symbol, and we are
9631 using a small GOT, we want
9632 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9636 lw $gp,cprestore($sp)
9637 The cprestore value is set using the .cprestore
9638 pseudo-op. If we are using a big GOT, we want
9639 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
9641 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
9645 lw $gp,cprestore($sp)
9646 If the symbol is not external, we want
9647 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9649 addiu $25,$25,<sym> (BFD_RELOC_LO16)
9652 lw $gp,cprestore($sp)
9654 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
9655 sequences above, minus nops, unless the symbol is local,
9656 which enables us to use GOT_PAGE/GOT_OFST (big got) or
9662 relax_start (offset_expr.X_add_symbol);
9663 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9664 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
9667 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9668 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
9674 relax_start (offset_expr.X_add_symbol);
9675 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
9676 BFD_RELOC_MIPS_CALL_HI16);
9677 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
9678 PIC_CALL_REG, mips_gp_register);
9679 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9680 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
9683 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9684 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
9686 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9687 PIC_CALL_REG, PIC_CALL_REG,
9688 BFD_RELOC_MIPS_GOT_OFST);
9692 macro_build_jalr (&offset_expr, 0);
9696 relax_start (offset_expr.X_add_symbol);
9699 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9700 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
9709 gpdelay = reg_needs_delay (mips_gp_register);
9710 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
9711 BFD_RELOC_MIPS_CALL_HI16);
9712 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
9713 PIC_CALL_REG, mips_gp_register);
9714 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9715 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
9720 macro_build (NULL, "nop", "");
9722 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9723 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
9726 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9727 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
9729 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
9731 if (mips_cprestore_offset < 0)
9732 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9735 if (!mips_frame_reg_valid)
9737 as_warn (_("No .frame pseudo-op used in PIC code"));
9738 /* Quiet this warning. */
9739 mips_frame_reg_valid = 1;
9741 if (!mips_cprestore_valid)
9743 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9744 /* Quiet this warning. */
9745 mips_cprestore_valid = 1;
9747 if (mips_opts.noreorder)
9748 macro_build (NULL, "nop", "");
9749 expr1.X_add_number = mips_cprestore_offset;
9750 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
9753 HAVE_64BIT_ADDRESSES);
9757 else if (mips_pic == VXWORKS_PIC)
9758 as_bad (_("Non-PIC jump used in PIC library"));
9865 gas_assert (!mips_opts.micromips);
9868 /* Itbl support may require additional care here. */
9874 /* Itbl support may require additional care here. */
9880 offbits = (mips_opts.micromips ? 12 : 16);
9881 /* Itbl support may require additional care here. */
9885 gas_assert (!mips_opts.micromips);
9888 /* Itbl support may require additional care here. */
9894 offbits = (mips_opts.micromips ? 12 : 16);
9899 offbits = (mips_opts.micromips ? 12 : 16);
9904 /* Itbl support may require additional care here. */
9910 offbits = (mips_opts.micromips ? 12 : 16);
9911 /* Itbl support may require additional care here. */
9917 /* Itbl support may require additional care here. */
9923 /* Itbl support may require additional care here. */
9929 offbits = (mips_opts.micromips ? 12 : 16);
9934 offbits = (mips_opts.micromips ? 12 : 16);
9939 offbits = (mips_opts.micromips ? 12 : 16);
9944 offbits = (mips_opts.micromips ? 12 : 16);
9949 offbits = (mips_opts.micromips ? 12 : 16);
9952 gas_assert (mips_opts.micromips);
9959 gas_assert (mips_opts.micromips);
9966 gas_assert (mips_opts.micromips);
9972 gas_assert (mips_opts.micromips);
9979 /* We don't want to use $0 as tempreg. */
9980 if (op[2] == op[0] + lp || op[0] + lp == ZERO)
9983 tempreg = op[0] + lp;
9999 gas_assert (!mips_opts.micromips);
10002 /* Itbl support may require additional care here. */
10008 /* Itbl support may require additional care here. */
10014 offbits = (mips_opts.micromips ? 12 : 16);
10015 /* Itbl support may require additional care here. */
10019 gas_assert (!mips_opts.micromips);
10022 /* Itbl support may require additional care here. */
10028 offbits = (mips_opts.micromips ? 12 : 16);
10033 offbits = (mips_opts.micromips ? 12 : 16);
10038 offbits = (mips_opts.micromips ? 12 : 16);
10043 offbits = (mips_opts.micromips ? 12 : 16);
10047 fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)";
10048 offbits = (mips_opts.micromips ? 12 : 16);
10057 fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)";
10058 offbits = (mips_opts.micromips ? 12 : 16);
10069 /* Itbl support may require additional care here. */
10074 offbits = (mips_opts.micromips ? 12 : 16);
10075 /* Itbl support may require additional care here. */
10081 /* Itbl support may require additional care here. */
10085 gas_assert (!mips_opts.micromips);
10088 /* Itbl support may require additional care here. */
10094 offbits = (mips_opts.micromips ? 12 : 16);
10099 offbits = (mips_opts.micromips ? 12 : 16);
10102 gas_assert (mips_opts.micromips);
10108 gas_assert (mips_opts.micromips);
10114 gas_assert (mips_opts.micromips);
10120 gas_assert (mips_opts.micromips);
10129 if (small_offset_p (0, align, 16))
10131 /* The first case exists for M_LD_AB and M_SD_AB, which are
10132 macros for o32 but which should act like normal instructions
10135 macro_build (&offset_expr, s, fmt, op[0], -1, offset_reloc[0],
10136 offset_reloc[1], offset_reloc[2], breg);
10137 else if (small_offset_p (0, align, offbits))
10140 macro_build (NULL, s, fmt, op[0], breg);
10142 macro_build (NULL, s, fmt, op[0],
10143 (int) offset_expr.X_add_number, breg);
10149 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10150 tempreg, breg, -1, offset_reloc[0],
10151 offset_reloc[1], offset_reloc[2]);
10153 macro_build (NULL, s, fmt, op[0], tempreg);
10155 macro_build (NULL, s, fmt, op[0], 0, tempreg);
10163 if (offset_expr.X_op != O_constant
10164 && offset_expr.X_op != O_symbol)
10166 as_bad (_("Expression too complex"));
10167 offset_expr.X_op = O_constant;
10170 if (HAVE_32BIT_ADDRESSES
10171 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
10175 sprintf_vma (value, offset_expr.X_add_number);
10176 as_bad (_("Number (0x%s) larger than 32 bits"), value);
10179 /* A constant expression in PIC code can be handled just as it
10180 is in non PIC code. */
10181 if (offset_expr.X_op == O_constant)
10183 expr1.X_add_number = offset_high_part (offset_expr.X_add_number,
10184 offbits == 0 ? 16 : offbits);
10185 offset_expr.X_add_number -= expr1.X_add_number;
10187 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
10189 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10190 tempreg, tempreg, breg);
10193 if (offset_expr.X_add_number != 0)
10194 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
10195 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
10196 macro_build (NULL, s, fmt, op[0], tempreg);
10198 else if (offbits == 16)
10199 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
10201 macro_build (NULL, s, fmt, op[0],
10202 (int) offset_expr.X_add_number, tempreg);
10204 else if (offbits != 16)
10206 /* The offset field is too narrow to be used for a low-part
10207 relocation, so load the whole address into the auxillary
10209 load_address (tempreg, &offset_expr, &used_at);
10211 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10212 tempreg, tempreg, breg);
10214 macro_build (NULL, s, fmt, op[0], tempreg);
10216 macro_build (NULL, s, fmt, op[0], 0, tempreg);
10218 else if (mips_pic == NO_PIC)
10220 /* If this is a reference to a GP relative symbol, and there
10221 is no base register, we want
10222 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
10223 Otherwise, if there is no base register, we want
10224 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10225 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
10226 If we have a constant, we need two instructions anyhow,
10227 so we always use the latter form.
10229 If we have a base register, and this is a reference to a
10230 GP relative symbol, we want
10231 addu $tempreg,$breg,$gp
10232 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
10234 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10235 addu $tempreg,$tempreg,$breg
10236 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
10237 With a constant we always use the latter case.
10239 With 64bit address space and no base register and $at usable,
10241 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10242 lui $at,<sym> (BFD_RELOC_HI16_S)
10243 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10246 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
10247 If we have a base register, we want
10248 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10249 lui $at,<sym> (BFD_RELOC_HI16_S)
10250 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10254 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
10256 Without $at we can't generate the optimal path for superscalar
10257 processors here since this would require two temporary registers.
10258 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10259 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10261 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10263 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
10264 If we have a base register, we want
10265 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10266 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10268 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10270 daddu $tempreg,$tempreg,$breg
10271 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
10273 For GP relative symbols in 64bit address space we can use
10274 the same sequence as in 32bit address space. */
10275 if (HAVE_64BIT_SYMBOLS)
10277 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10278 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10280 relax_start (offset_expr.X_add_symbol);
10283 macro_build (&offset_expr, s, fmt, op[0],
10284 BFD_RELOC_GPREL16, mips_gp_register);
10288 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10289 tempreg, breg, mips_gp_register);
10290 macro_build (&offset_expr, s, fmt, op[0],
10291 BFD_RELOC_GPREL16, tempreg);
10296 if (used_at == 0 && mips_opts.at)
10298 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
10299 BFD_RELOC_MIPS_HIGHEST);
10300 macro_build (&offset_expr, "lui", LUI_FMT, AT,
10302 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
10303 tempreg, BFD_RELOC_MIPS_HIGHER);
10305 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
10306 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
10307 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
10308 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16,
10314 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
10315 BFD_RELOC_MIPS_HIGHEST);
10316 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
10317 tempreg, BFD_RELOC_MIPS_HIGHER);
10318 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
10319 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
10320 tempreg, BFD_RELOC_HI16_S);
10321 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
10323 macro_build (NULL, "daddu", "d,v,t",
10324 tempreg, tempreg, breg);
10325 macro_build (&offset_expr, s, fmt, op[0],
10326 BFD_RELOC_LO16, tempreg);
10329 if (mips_relax.sequence)
10336 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10337 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10339 relax_start (offset_expr.X_add_symbol);
10340 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_GPREL16,
10344 macro_build_lui (&offset_expr, tempreg);
10345 macro_build (&offset_expr, s, fmt, op[0],
10346 BFD_RELOC_LO16, tempreg);
10347 if (mips_relax.sequence)
10352 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10353 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10355 relax_start (offset_expr.X_add_symbol);
10356 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10357 tempreg, breg, mips_gp_register);
10358 macro_build (&offset_expr, s, fmt, op[0],
10359 BFD_RELOC_GPREL16, tempreg);
10362 macro_build_lui (&offset_expr, tempreg);
10363 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10364 tempreg, tempreg, breg);
10365 macro_build (&offset_expr, s, fmt, op[0],
10366 BFD_RELOC_LO16, tempreg);
10367 if (mips_relax.sequence)
10371 else if (!mips_big_got)
10373 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
10375 /* If this is a reference to an external symbol, we want
10376 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10378 <op> op[0],0($tempreg)
10380 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10382 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10383 <op> op[0],0($tempreg)
10385 For NewABI, we want
10386 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10387 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
10389 If there is a base register, we add it to $tempreg before
10390 the <op>. If there is a constant, we stick it in the
10391 <op> instruction. We don't handle constants larger than
10392 16 bits, because we have no way to load the upper 16 bits
10393 (actually, we could handle them for the subset of cases
10394 in which we are not using $at). */
10395 gas_assert (offset_expr.X_op == O_symbol);
10398 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10399 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
10401 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10402 tempreg, tempreg, breg);
10403 macro_build (&offset_expr, s, fmt, op[0],
10404 BFD_RELOC_MIPS_GOT_OFST, tempreg);
10407 expr1.X_add_number = offset_expr.X_add_number;
10408 offset_expr.X_add_number = 0;
10409 if (expr1.X_add_number < -0x8000
10410 || expr1.X_add_number >= 0x8000)
10411 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10412 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10413 lw_reloc_type, mips_gp_register);
10415 relax_start (offset_expr.X_add_symbol);
10417 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
10418 tempreg, BFD_RELOC_LO16);
10421 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10422 tempreg, tempreg, breg);
10423 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
10425 else if (mips_big_got && !HAVE_NEWABI)
10429 /* If this is a reference to an external symbol, we want
10430 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10431 addu $tempreg,$tempreg,$gp
10432 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10433 <op> op[0],0($tempreg)
10435 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10437 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10438 <op> op[0],0($tempreg)
10439 If there is a base register, we add it to $tempreg before
10440 the <op>. If there is a constant, we stick it in the
10441 <op> instruction. We don't handle constants larger than
10442 16 bits, because we have no way to load the upper 16 bits
10443 (actually, we could handle them for the subset of cases
10444 in which we are not using $at). */
10445 gas_assert (offset_expr.X_op == O_symbol);
10446 expr1.X_add_number = offset_expr.X_add_number;
10447 offset_expr.X_add_number = 0;
10448 if (expr1.X_add_number < -0x8000
10449 || expr1.X_add_number >= 0x8000)
10450 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10451 gpdelay = reg_needs_delay (mips_gp_register);
10452 relax_start (offset_expr.X_add_symbol);
10453 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
10454 BFD_RELOC_MIPS_GOT_HI16);
10455 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
10457 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10458 BFD_RELOC_MIPS_GOT_LO16, tempreg);
10461 macro_build (NULL, "nop", "");
10462 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10463 BFD_RELOC_MIPS_GOT16, mips_gp_register);
10465 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
10466 tempreg, BFD_RELOC_LO16);
10470 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10471 tempreg, tempreg, breg);
10472 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
10474 else if (mips_big_got && HAVE_NEWABI)
10476 /* If this is a reference to an external symbol, we want
10477 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10478 add $tempreg,$tempreg,$gp
10479 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10480 <op> op[0],<ofst>($tempreg)
10481 Otherwise, for local symbols, we want:
10482 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10483 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
10484 gas_assert (offset_expr.X_op == O_symbol);
10485 expr1.X_add_number = offset_expr.X_add_number;
10486 offset_expr.X_add_number = 0;
10487 if (expr1.X_add_number < -0x8000
10488 || expr1.X_add_number >= 0x8000)
10489 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10490 relax_start (offset_expr.X_add_symbol);
10491 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
10492 BFD_RELOC_MIPS_GOT_HI16);
10493 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
10495 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10496 BFD_RELOC_MIPS_GOT_LO16, tempreg);
10498 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10499 tempreg, tempreg, breg);
10500 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
10503 offset_expr.X_add_number = expr1.X_add_number;
10504 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10505 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
10507 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10508 tempreg, tempreg, breg);
10509 macro_build (&offset_expr, s, fmt, op[0],
10510 BFD_RELOC_MIPS_GOT_OFST, tempreg);
10519 gas_assert (mips_opts.micromips);
10520 gas_assert (mips_opts.insn32);
10521 start_noreorder ();
10522 macro_build (NULL, "jr", "s", RA);
10523 expr1.X_add_number = op[0] << 2;
10524 macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16);
10529 gas_assert (mips_opts.micromips);
10530 gas_assert (mips_opts.insn32);
10531 macro_build (NULL, "jr", "s", op[0]);
10532 if (mips_opts.noreorder)
10533 macro_build (NULL, "nop", "");
10538 load_register (op[0], &imm_expr, 0);
10542 load_register (op[0], &imm_expr, 1);
10546 if (imm_expr.X_op == O_constant)
10549 load_register (AT, &imm_expr, 0);
10550 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
10555 gas_assert (offset_expr.X_op == O_symbol
10556 && strcmp (segment_name (S_GET_SEGMENT
10557 (offset_expr.X_add_symbol)),
10559 && offset_expr.X_add_number == 0);
10560 macro_build (&offset_expr, "lwc1", "T,o(b)", op[0],
10561 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
10566 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
10567 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
10568 order 32 bits of the value and the low order 32 bits are either
10569 zero or in OFFSET_EXPR. */
10570 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
10572 if (HAVE_64BIT_GPRS)
10573 load_register (op[0], &imm_expr, 1);
10578 if (target_big_endian)
10590 load_register (hreg, &imm_expr, 0);
10593 if (offset_expr.X_op == O_absent)
10594 move_register (lreg, 0);
10597 gas_assert (offset_expr.X_op == O_constant);
10598 load_register (lreg, &offset_expr, 0);
10605 /* We know that sym is in the .rdata section. First we get the
10606 upper 16 bits of the address. */
10607 if (mips_pic == NO_PIC)
10609 macro_build_lui (&offset_expr, AT);
10614 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
10615 BFD_RELOC_MIPS_GOT16, mips_gp_register);
10619 /* Now we load the register(s). */
10620 if (HAVE_64BIT_GPRS)
10623 macro_build (&offset_expr, "ld", "t,o(b)", op[0],
10624 BFD_RELOC_LO16, AT);
10629 macro_build (&offset_expr, "lw", "t,o(b)", op[0],
10630 BFD_RELOC_LO16, AT);
10633 /* FIXME: How in the world do we deal with the possible
10635 offset_expr.X_add_number += 4;
10636 macro_build (&offset_expr, "lw", "t,o(b)",
10637 op[0] + 1, BFD_RELOC_LO16, AT);
10643 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
10644 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
10645 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
10646 the value and the low order 32 bits are either zero or in
10648 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
10651 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
10652 if (HAVE_64BIT_FPRS)
10654 gas_assert (HAVE_64BIT_GPRS);
10655 macro_build (NULL, "dmtc1", "t,S", AT, op[0]);
10659 macro_build (NULL, "mtc1", "t,G", AT, op[0] + 1);
10660 if (offset_expr.X_op == O_absent)
10661 macro_build (NULL, "mtc1", "t,G", 0, op[0]);
10664 gas_assert (offset_expr.X_op == O_constant);
10665 load_register (AT, &offset_expr, 0);
10666 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
10672 gas_assert (offset_expr.X_op == O_symbol
10673 && offset_expr.X_add_number == 0);
10674 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
10675 if (strcmp (s, ".lit8") == 0)
10677 op[2] = mips_gp_register;
10678 offset_reloc[0] = BFD_RELOC_MIPS_LITERAL;
10679 offset_reloc[1] = BFD_RELOC_UNUSED;
10680 offset_reloc[2] = BFD_RELOC_UNUSED;
10684 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
10686 if (mips_pic != NO_PIC)
10687 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
10688 BFD_RELOC_MIPS_GOT16, mips_gp_register);
10691 /* FIXME: This won't work for a 64 bit address. */
10692 macro_build_lui (&offset_expr, AT);
10696 offset_reloc[0] = BFD_RELOC_LO16;
10697 offset_reloc[1] = BFD_RELOC_UNUSED;
10698 offset_reloc[2] = BFD_RELOC_UNUSED;
10705 * The MIPS assembler seems to check for X_add_number not
10706 * being double aligned and generating:
10707 * lui at,%hi(foo+1)
10709 * addiu at,at,%lo(foo+1)
10712 * But, the resulting address is the same after relocation so why
10713 * generate the extra instruction?
10715 /* Itbl support may require additional care here. */
10718 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
10727 gas_assert (!mips_opts.micromips);
10728 /* Itbl support may require additional care here. */
10731 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
10751 if (HAVE_64BIT_GPRS)
10761 if (HAVE_64BIT_GPRS)
10769 /* Even on a big endian machine $fn comes before $fn+1. We have
10770 to adjust when loading from memory. We set coproc if we must
10771 load $fn+1 first. */
10772 /* Itbl support may require additional care here. */
10773 if (!target_big_endian)
10777 if (small_offset_p (0, align, 16))
10780 if (!small_offset_p (4, align, 16))
10782 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg,
10783 -1, offset_reloc[0], offset_reloc[1],
10785 expr1.X_add_number = 0;
10789 offset_reloc[0] = BFD_RELOC_LO16;
10790 offset_reloc[1] = BFD_RELOC_UNUSED;
10791 offset_reloc[2] = BFD_RELOC_UNUSED;
10793 if (strcmp (s, "lw") == 0 && op[0] == breg)
10795 ep->X_add_number += 4;
10796 macro_build (ep, s, fmt, op[0] + 1, -1, offset_reloc[0],
10797 offset_reloc[1], offset_reloc[2], breg);
10798 ep->X_add_number -= 4;
10799 macro_build (ep, s, fmt, op[0], -1, offset_reloc[0],
10800 offset_reloc[1], offset_reloc[2], breg);
10804 macro_build (ep, s, fmt, coproc ? op[0] + 1 : op[0], -1,
10805 offset_reloc[0], offset_reloc[1], offset_reloc[2],
10807 ep->X_add_number += 4;
10808 macro_build (ep, s, fmt, coproc ? op[0] : op[0] + 1, -1,
10809 offset_reloc[0], offset_reloc[1], offset_reloc[2],
10815 if (offset_expr.X_op != O_symbol
10816 && offset_expr.X_op != O_constant)
10818 as_bad (_("Expression too complex"));
10819 offset_expr.X_op = O_constant;
10822 if (HAVE_32BIT_ADDRESSES
10823 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
10827 sprintf_vma (value, offset_expr.X_add_number);
10828 as_bad (_("Number (0x%s) larger than 32 bits"), value);
10831 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
10833 /* If this is a reference to a GP relative symbol, we want
10834 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
10835 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
10836 If we have a base register, we use this
10838 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
10839 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
10840 If this is not a GP relative symbol, we want
10841 lui $at,<sym> (BFD_RELOC_HI16_S)
10842 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
10843 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
10844 If there is a base register, we add it to $at after the
10845 lui instruction. If there is a constant, we always use
10847 if (offset_expr.X_op == O_symbol
10848 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10849 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10851 relax_start (offset_expr.X_add_symbol);
10854 tempreg = mips_gp_register;
10858 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10859 AT, breg, mips_gp_register);
10864 /* Itbl support may require additional care here. */
10865 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
10866 BFD_RELOC_GPREL16, tempreg);
10867 offset_expr.X_add_number += 4;
10869 /* Set mips_optimize to 2 to avoid inserting an
10871 hold_mips_optimize = mips_optimize;
10873 /* Itbl support may require additional care here. */
10874 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
10875 BFD_RELOC_GPREL16, tempreg);
10876 mips_optimize = hold_mips_optimize;
10880 offset_expr.X_add_number -= 4;
10883 if (offset_high_part (offset_expr.X_add_number, 16)
10884 != offset_high_part (offset_expr.X_add_number + 4, 16))
10886 load_address (AT, &offset_expr, &used_at);
10887 offset_expr.X_op = O_constant;
10888 offset_expr.X_add_number = 0;
10891 macro_build_lui (&offset_expr, AT);
10893 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
10894 /* Itbl support may require additional care here. */
10895 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
10896 BFD_RELOC_LO16, AT);
10897 /* FIXME: How do we handle overflow here? */
10898 offset_expr.X_add_number += 4;
10899 /* Itbl support may require additional care here. */
10900 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
10901 BFD_RELOC_LO16, AT);
10902 if (mips_relax.sequence)
10905 else if (!mips_big_got)
10907 /* If this is a reference to an external symbol, we want
10908 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10911 <op> op[0]+1,4($at)
10913 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10915 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
10916 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
10917 If there is a base register we add it to $at before the
10918 lwc1 instructions. If there is a constant we include it
10919 in the lwc1 instructions. */
10921 expr1.X_add_number = offset_expr.X_add_number;
10922 if (expr1.X_add_number < -0x8000
10923 || expr1.X_add_number >= 0x8000 - 4)
10924 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10925 load_got_offset (AT, &offset_expr);
10928 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
10930 /* Set mips_optimize to 2 to avoid inserting an undesired
10932 hold_mips_optimize = mips_optimize;
10935 /* Itbl support may require additional care here. */
10936 relax_start (offset_expr.X_add_symbol);
10937 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
10938 BFD_RELOC_LO16, AT);
10939 expr1.X_add_number += 4;
10940 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
10941 BFD_RELOC_LO16, AT);
10943 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
10944 BFD_RELOC_LO16, AT);
10945 offset_expr.X_add_number += 4;
10946 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
10947 BFD_RELOC_LO16, AT);
10950 mips_optimize = hold_mips_optimize;
10952 else if (mips_big_got)
10956 /* If this is a reference to an external symbol, we want
10957 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10959 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
10962 <op> op[0]+1,4($at)
10964 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10966 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
10967 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
10968 If there is a base register we add it to $at before the
10969 lwc1 instructions. If there is a constant we include it
10970 in the lwc1 instructions. */
10972 expr1.X_add_number = offset_expr.X_add_number;
10973 offset_expr.X_add_number = 0;
10974 if (expr1.X_add_number < -0x8000
10975 || expr1.X_add_number >= 0x8000 - 4)
10976 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10977 gpdelay = reg_needs_delay (mips_gp_register);
10978 relax_start (offset_expr.X_add_symbol);
10979 macro_build (&offset_expr, "lui", LUI_FMT,
10980 AT, BFD_RELOC_MIPS_GOT_HI16);
10981 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10982 AT, AT, mips_gp_register);
10983 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10984 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
10987 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
10988 /* Itbl support may require additional care here. */
10989 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
10990 BFD_RELOC_LO16, AT);
10991 expr1.X_add_number += 4;
10993 /* Set mips_optimize to 2 to avoid inserting an undesired
10995 hold_mips_optimize = mips_optimize;
10997 /* Itbl support may require additional care here. */
10998 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
10999 BFD_RELOC_LO16, AT);
11000 mips_optimize = hold_mips_optimize;
11001 expr1.X_add_number -= 4;
11004 offset_expr.X_add_number = expr1.X_add_number;
11006 macro_build (NULL, "nop", "");
11007 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
11008 BFD_RELOC_MIPS_GOT16, mips_gp_register);
11011 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
11012 /* Itbl support may require additional care here. */
11013 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
11014 BFD_RELOC_LO16, AT);
11015 offset_expr.X_add_number += 4;
11017 /* Set mips_optimize to 2 to avoid inserting an undesired
11019 hold_mips_optimize = mips_optimize;
11021 /* Itbl support may require additional care here. */
11022 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
11023 BFD_RELOC_LO16, AT);
11024 mips_optimize = hold_mips_optimize;
11043 /* New code added to support COPZ instructions.
11044 This code builds table entries out of the macros in mip_opcodes.
11045 R4000 uses interlocks to handle coproc delays.
11046 Other chips (like the R3000) require nops to be inserted for delays.
11048 FIXME: Currently, we require that the user handle delays.
11049 In order to fill delay slots for non-interlocked chips,
11050 we must have a way to specify delays based on the coprocessor.
11051 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
11052 What are the side-effects of the cop instruction?
11053 What cache support might we have and what are its effects?
11054 Both coprocessor & memory require delays. how long???
11055 What registers are read/set/modified?
11057 If an itbl is provided to interpret cop instructions,
11058 this knowledge can be encoded in the itbl spec. */
11072 gas_assert (!mips_opts.micromips);
11073 /* For now we just do C (same as Cz). The parameter will be
11074 stored in insn_opcode by mips_ip. */
11075 macro_build (NULL, s, "C", (int) ip->insn_opcode);
11079 move_register (op[0], op[1]);
11083 gas_assert (mips_opts.micromips);
11084 gas_assert (mips_opts.insn32);
11085 move_register (micromips_to_32_reg_h_map1[op[0]],
11086 micromips_to_32_reg_m_map[op[1]]);
11087 move_register (micromips_to_32_reg_h_map2[op[0]],
11088 micromips_to_32_reg_n_map[op[2]]);
11094 if (mips_opts.arch == CPU_R5900)
11095 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", op[0], op[1],
11099 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", op[1], op[2]);
11100 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
11107 /* The MIPS assembler some times generates shifts and adds. I'm
11108 not trying to be that fancy. GCC should do this for us
11111 load_register (AT, &imm_expr, dbl);
11112 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", op[1], AT);
11113 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
11126 start_noreorder ();
11129 load_register (AT, &imm_expr, dbl);
11130 macro_build (NULL, dbl ? "dmult" : "mult", "s,t",
11131 op[1], imm ? AT : op[2]);
11132 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
11133 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, op[0], op[0], 31);
11134 macro_build (NULL, "mfhi", MFHL_FMT, AT);
11136 macro_build (NULL, "tne", TRAP_FMT, op[0], AT, 6);
11139 if (mips_opts.micromips)
11140 micromips_label_expr (&label_expr);
11142 label_expr.X_add_number = 8;
11143 macro_build (&label_expr, "beq", "s,t,p", op[0], AT);
11144 macro_build (NULL, "nop", "");
11145 macro_build (NULL, "break", BRK_FMT, 6);
11146 if (mips_opts.micromips)
11147 micromips_add_label ();
11150 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
11163 start_noreorder ();
11166 load_register (AT, &imm_expr, dbl);
11167 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
11168 op[1], imm ? AT : op[2]);
11169 macro_build (NULL, "mfhi", MFHL_FMT, AT);
11170 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
11172 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
11175 if (mips_opts.micromips)
11176 micromips_label_expr (&label_expr);
11178 label_expr.X_add_number = 8;
11179 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
11180 macro_build (NULL, "nop", "");
11181 macro_build (NULL, "break", BRK_FMT, 6);
11182 if (mips_opts.micromips)
11183 micromips_add_label ();
11189 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
11191 if (op[0] == op[1])
11198 macro_build (NULL, "dnegu", "d,w", tempreg, op[2]);
11199 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], tempreg);
11203 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
11204 macro_build (NULL, "dsrlv", "d,t,s", AT, op[1], AT);
11205 macro_build (NULL, "dsllv", "d,t,s", op[0], op[1], op[2]);
11206 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
11210 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
11212 if (op[0] == op[1])
11219 macro_build (NULL, "negu", "d,w", tempreg, op[2]);
11220 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], tempreg);
11224 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
11225 macro_build (NULL, "srlv", "d,t,s", AT, op[1], AT);
11226 macro_build (NULL, "sllv", "d,t,s", op[0], op[1], op[2]);
11227 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
11236 if (imm_expr.X_op != O_constant)
11237 as_bad (_("Improper rotate count"));
11238 rot = imm_expr.X_add_number & 0x3f;
11239 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
11241 rot = (64 - rot) & 0x3f;
11243 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
11245 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
11250 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
11253 l = (rot < 0x20) ? "dsll" : "dsll32";
11254 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
11257 macro_build (NULL, l, SHFT_FMT, AT, op[1], rot);
11258 macro_build (NULL, rr, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
11259 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
11267 if (imm_expr.X_op != O_constant)
11268 as_bad (_("Improper rotate count"));
11269 rot = imm_expr.X_add_number & 0x1f;
11270 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
11272 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1],
11273 (32 - rot) & 0x1f);
11278 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
11282 macro_build (NULL, "sll", SHFT_FMT, AT, op[1], rot);
11283 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
11284 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
11289 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
11291 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], op[2]);
11295 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
11296 macro_build (NULL, "dsllv", "d,t,s", AT, op[1], AT);
11297 macro_build (NULL, "dsrlv", "d,t,s", op[0], op[1], op[2]);
11298 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
11302 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
11304 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], op[2]);
11308 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
11309 macro_build (NULL, "sllv", "d,t,s", AT, op[1], AT);
11310 macro_build (NULL, "srlv", "d,t,s", op[0], op[1], op[2]);
11311 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
11320 if (imm_expr.X_op != O_constant)
11321 as_bad (_("Improper rotate count"));
11322 rot = imm_expr.X_add_number & 0x3f;
11323 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
11326 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
11328 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
11333 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
11336 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
11337 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
11340 macro_build (NULL, rr, SHFT_FMT, AT, op[1], rot);
11341 macro_build (NULL, l, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
11342 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
11350 if (imm_expr.X_op != O_constant)
11351 as_bad (_("Improper rotate count"));
11352 rot = imm_expr.X_add_number & 0x1f;
11353 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
11355 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], rot);
11360 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
11364 macro_build (NULL, "srl", SHFT_FMT, AT, op[1], rot);
11365 macro_build (NULL, "sll", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
11366 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
11372 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[2], BFD_RELOC_LO16);
11373 else if (op[2] == 0)
11374 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
11377 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
11378 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
11383 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
11385 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
11390 as_warn (_("Instruction %s: result is always false"),
11391 ip->insn_mo->name);
11392 move_register (op[0], 0);
11395 if (CPU_HAS_SEQ (mips_opts.arch)
11396 && -512 <= imm_expr.X_add_number
11397 && imm_expr.X_add_number < 512)
11399 macro_build (NULL, "seqi", "t,r,+Q", op[0], op[1],
11400 (int) imm_expr.X_add_number);
11403 if (imm_expr.X_op == O_constant
11404 && imm_expr.X_add_number >= 0
11405 && imm_expr.X_add_number < 0x10000)
11406 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], BFD_RELOC_LO16);
11407 else if (imm_expr.X_op == O_constant
11408 && imm_expr.X_add_number > -0x8000
11409 && imm_expr.X_add_number < 0)
11411 imm_expr.X_add_number = -imm_expr.X_add_number;
11412 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
11413 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
11415 else if (CPU_HAS_SEQ (mips_opts.arch))
11418 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11419 macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT);
11424 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11425 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
11428 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
11431 case M_SGE: /* X >= Y <==> not (X < Y) */
11437 macro_build (NULL, s, "d,v,t", op[0], op[1], op[2]);
11438 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
11441 case M_SGE_I: /* X >= I <==> not (X < I) */
11443 if (imm_expr.X_op == O_constant
11444 && imm_expr.X_add_number >= -0x8000
11445 && imm_expr.X_add_number < 0x8000)
11446 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
11447 op[0], op[1], BFD_RELOC_LO16);
11450 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11451 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
11455 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
11458 case M_SGT: /* X > Y <==> Y < X */
11464 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
11467 case M_SGT_I: /* X > I <==> I < X */
11474 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11475 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
11478 case M_SLE: /* X <= Y <==> Y >= X <==> not (Y < X) */
11484 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
11485 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
11488 case M_SLE_I: /* X <= I <==> I >= X <==> not (I < X) */
11495 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11496 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
11497 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
11501 if (imm_expr.X_op == O_constant
11502 && imm_expr.X_add_number >= -0x8000
11503 && imm_expr.X_add_number < 0x8000)
11505 macro_build (&imm_expr, "slti", "t,r,j", op[0], op[1],
11510 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11511 macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT);
11515 if (imm_expr.X_op == O_constant
11516 && imm_expr.X_add_number >= -0x8000
11517 && imm_expr.X_add_number < 0x8000)
11519 macro_build (&imm_expr, "sltiu", "t,r,j", op[0], op[1],
11524 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11525 macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT);
11530 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[2]);
11531 else if (op[2] == 0)
11532 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
11535 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
11536 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
11541 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
11543 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
11548 as_warn (_("Instruction %s: result is always true"),
11549 ip->insn_mo->name);
11550 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
11551 op[0], 0, BFD_RELOC_LO16);
11554 if (CPU_HAS_SEQ (mips_opts.arch)
11555 && -512 <= imm_expr.X_add_number
11556 && imm_expr.X_add_number < 512)
11558 macro_build (NULL, "snei", "t,r,+Q", op[0], op[1],
11559 (int) imm_expr.X_add_number);
11562 if (imm_expr.X_op == O_constant
11563 && imm_expr.X_add_number >= 0
11564 && imm_expr.X_add_number < 0x10000)
11566 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1],
11569 else if (imm_expr.X_op == O_constant
11570 && imm_expr.X_add_number > -0x8000
11571 && imm_expr.X_add_number < 0)
11573 imm_expr.X_add_number = -imm_expr.X_add_number;
11574 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
11575 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
11577 else if (CPU_HAS_SEQ (mips_opts.arch))
11580 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11581 macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT);
11586 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11587 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
11590 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
11605 if (!mips_opts.micromips)
11607 if (imm_expr.X_op == O_constant
11608 && imm_expr.X_add_number > -0x200
11609 && imm_expr.X_add_number <= 0x200)
11611 macro_build (NULL, s, "t,r,.", op[0], op[1], -imm_expr.X_add_number);
11620 if (imm_expr.X_op == O_constant
11621 && imm_expr.X_add_number > -0x8000
11622 && imm_expr.X_add_number <= 0x8000)
11624 imm_expr.X_add_number = -imm_expr.X_add_number;
11625 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
11630 load_register (AT, &imm_expr, dbl);
11631 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
11653 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11654 macro_build (NULL, s, "s,t", op[0], AT);
11659 gas_assert (!mips_opts.micromips);
11660 gas_assert (mips_opts.isa == ISA_MIPS1);
11664 * Is the double cfc1 instruction a bug in the mips assembler;
11665 * or is there a reason for it?
11667 start_noreorder ();
11668 macro_build (NULL, "cfc1", "t,G", op[2], RA);
11669 macro_build (NULL, "cfc1", "t,G", op[2], RA);
11670 macro_build (NULL, "nop", "");
11671 expr1.X_add_number = 3;
11672 macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16);
11673 expr1.X_add_number = 2;
11674 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
11675 macro_build (NULL, "ctc1", "t,G", AT, RA);
11676 macro_build (NULL, "nop", "");
11677 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
11679 macro_build (NULL, "ctc1", "t,G", op[2], RA);
11680 macro_build (NULL, "nop", "");
11697 offbits = (mips_opts.micromips ? 12 : 16);
11703 offbits = (mips_opts.micromips ? 12 : 16);
11715 offbits = (mips_opts.micromips ? 12 : 16);
11722 offbits = (mips_opts.micromips ? 12 : 16);
11728 large_offset = !small_offset_p (off, align, offbits);
11730 expr1.X_add_number = 0;
11735 if (small_offset_p (0, align, 16))
11736 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1,
11737 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
11740 load_address (tempreg, ep, &used_at);
11742 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11743 tempreg, tempreg, breg);
11745 offset_reloc[0] = BFD_RELOC_LO16;
11746 offset_reloc[1] = BFD_RELOC_UNUSED;
11747 offset_reloc[2] = BFD_RELOC_UNUSED;
11752 else if (!ust && op[0] == breg)
11763 if (!target_big_endian)
11764 ep->X_add_number += off;
11766 macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg);
11768 macro_build (ep, s, "t,o(b)", tempreg, -1,
11769 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
11771 if (!target_big_endian)
11772 ep->X_add_number -= off;
11774 ep->X_add_number += off;
11776 macro_build (NULL, s2, "t,~(b)",
11777 tempreg, (int) ep->X_add_number, breg);
11779 macro_build (ep, s2, "t,o(b)", tempreg, -1,
11780 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
11782 /* If necessary, move the result in tempreg to the final destination. */
11783 if (!ust && op[0] != tempreg)
11785 /* Protect second load's delay slot. */
11787 move_register (op[0], tempreg);
11793 if (target_big_endian == ust)
11794 ep->X_add_number += off;
11795 tempreg = ust || large_offset ? op[0] : AT;
11796 macro_build (ep, s, "t,o(b)", tempreg, -1,
11797 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
11799 /* For halfword transfers we need a temporary register to shuffle
11800 bytes. Unfortunately for M_USH_A we have none available before
11801 the next store as AT holds the base address. We deal with this
11802 case by clobbering TREG and then restoring it as with ULH. */
11803 tempreg = ust == large_offset ? op[0] : AT;
11805 macro_build (NULL, "srl", SHFT_FMT, tempreg, op[0], 8);
11807 if (target_big_endian == ust)
11808 ep->X_add_number -= off;
11810 ep->X_add_number += off;
11811 macro_build (ep, s2, "t,o(b)", tempreg, -1,
11812 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
11814 /* For M_USH_A re-retrieve the LSB. */
11815 if (ust && large_offset)
11817 if (target_big_endian)
11818 ep->X_add_number += off;
11820 ep->X_add_number -= off;
11821 macro_build (&expr1, "lbu", "t,o(b)", AT, -1,
11822 offset_reloc[0], offset_reloc[1], offset_reloc[2], AT);
11824 /* For ULH and M_USH_A OR the LSB in. */
11825 if (!ust || large_offset)
11827 tempreg = !large_offset ? AT : op[0];
11828 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
11829 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
11834 /* FIXME: Check if this is one of the itbl macros, since they
11835 are added dynamically. */
11836 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
11839 if (!mips_opts.at && used_at)
11840 as_bad (_("Macro used $at after \".set noat\""));
11843 /* Implement macros in mips16 mode. */
11846 mips16_macro (struct mips_cl_insn *ip)
11848 const struct mips_operand_array *operands;
11853 const char *s, *s2, *s3;
11854 unsigned int op[MAX_OPERANDS];
11857 mask = ip->insn_mo->mask;
11859 operands = insn_operands (ip);
11860 for (i = 0; i < MAX_OPERANDS; i++)
11861 if (operands->operand[i])
11862 op[i] = insn_extract_operand (ip, operands->operand[i]);
11866 expr1.X_op = O_constant;
11867 expr1.X_op_symbol = NULL;
11868 expr1.X_add_symbol = NULL;
11869 expr1.X_add_number = 1;
11888 start_noreorder ();
11889 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", op[1], op[2]);
11890 expr1.X_add_number = 2;
11891 macro_build (&expr1, "bnez", "x,p", op[2]);
11892 macro_build (NULL, "break", "6", 7);
11894 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
11895 since that causes an overflow. We should do that as well,
11896 but I don't see how to do the comparisons without a temporary
11899 macro_build (NULL, s, "x", op[0]);
11918 start_noreorder ();
11919 macro_build (NULL, s, "0,x,y", op[1], op[2]);
11920 expr1.X_add_number = 2;
11921 macro_build (&expr1, "bnez", "x,p", op[2]);
11922 macro_build (NULL, "break", "6", 7);
11924 macro_build (NULL, s2, "x", op[0]);
11930 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", op[1], op[2]);
11931 macro_build (NULL, "mflo", "x", op[0]);
11939 if (imm_expr.X_op != O_constant)
11940 as_bad (_("Unsupported large constant"));
11941 imm_expr.X_add_number = -imm_expr.X_add_number;
11942 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", op[0], op[1]);
11946 if (imm_expr.X_op != O_constant)
11947 as_bad (_("Unsupported large constant"));
11948 imm_expr.X_add_number = -imm_expr.X_add_number;
11949 macro_build (&imm_expr, "addiu", "x,k", op[0]);
11953 if (imm_expr.X_op != O_constant)
11954 as_bad (_("Unsupported large constant"));
11955 imm_expr.X_add_number = -imm_expr.X_add_number;
11956 macro_build (&imm_expr, "daddiu", "y,j", op[0]);
11978 goto do_reverse_branch;
11982 goto do_reverse_branch;
11994 goto do_reverse_branch;
12005 macro_build (NULL, s, "x,y", op[0], op[1]);
12006 macro_build (&offset_expr, s2, "p");
12033 goto do_addone_branch_i;
12038 goto do_addone_branch_i;
12053 goto do_addone_branch_i;
12059 do_addone_branch_i:
12060 if (imm_expr.X_op != O_constant)
12061 as_bad (_("Unsupported large constant"));
12062 ++imm_expr.X_add_number;
12065 macro_build (&imm_expr, s, s3, op[0]);
12066 macro_build (&offset_expr, s2, "p");
12070 expr1.X_add_number = 0;
12071 macro_build (&expr1, "slti", "x,8", op[1]);
12072 if (op[0] != op[1])
12073 macro_build (NULL, "move", "y,X", op[0], mips16_to_32_reg_map[op[1]]);
12074 expr1.X_add_number = 2;
12075 macro_build (&expr1, "bteqz", "p");
12076 macro_build (NULL, "neg", "x,w", op[0], op[0]);
12081 /* Assemble an instruction into its binary format. If the instruction
12082 is a macro, set imm_expr, imm2_expr and offset_expr to the values
12083 associated with "I", "+I" and "A" operands respectively. Otherwise
12084 store the value of the relocatable field (if any) in offset_expr.
12085 In both cases set offset_reloc to the relocation operators applied
12089 mips_ip (char *str, struct mips_cl_insn *ip)
12091 bfd_boolean wrong_delay_slot_insns = FALSE;
12092 bfd_boolean need_delay_slot_ok = TRUE;
12093 struct mips_opcode *firstinsn = NULL;
12094 const struct mips_opcode *past;
12095 struct hash_control *hash;
12098 struct mips_opcode *insn;
12104 const struct mips_operand *operand;
12105 struct mips_arg_info arg;
12106 struct mips_operand_token *tokens;
12107 bfd_boolean optional_reg;
12111 if (mips_opts.micromips)
12113 hash = micromips_op_hash;
12114 past = µmips_opcodes[bfd_micromips_num_opcodes];
12119 past = &mips_opcodes[NUMOPCODES];
12121 forced_insn_length = 0;
12124 /* We first try to match an instruction up to a space or to the end. */
12125 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
12128 /* Make a copy of the instruction so that we can fiddle with it. */
12129 name = alloca (end + 1);
12130 memcpy (name, str, end);
12135 insn = (struct mips_opcode *) hash_find (hash, name);
12137 if (insn != NULL || !mips_opts.micromips)
12139 if (forced_insn_length)
12142 /* See if there's an instruction size override suffix,
12143 either `16' or `32', at the end of the mnemonic proper,
12144 that defines the operation, i.e. before the first `.'
12145 character if any. Strip it and retry. */
12146 dot = strchr (name, '.');
12147 opend = dot != NULL ? dot - name : end;
12150 if (name[opend - 2] == '1' && name[opend - 1] == '6')
12151 forced_insn_length = 2;
12152 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
12153 forced_insn_length = 4;
12156 memcpy (name + opend - 2, name + opend, end - opend + 1);
12160 insn_error = _("Unrecognized opcode");
12164 if (strcmp (name, "li.s") == 0)
12166 else if (strcmp (name, "li.d") == 0)
12170 tokens = mips_parse_arguments (str + end, format);
12174 /* For microMIPS instructions placed in a fixed-length branch delay slot
12175 we make up to two passes over the relevant fragment of the opcode
12176 table. First we try instructions that meet the delay slot's length
12177 requirement. If none matched, then we retry with the remaining ones
12178 and if one matches, then we use it and then issue an appropriate
12179 warning later on. */
12182 bfd_boolean delay_slot_ok;
12183 bfd_boolean size_ok;
12185 bfd_boolean more_alts;
12187 gas_assert (strcmp (insn->name, name) == 0);
12189 ok = is_opcode_valid (insn);
12190 size_ok = is_size_valid (insn);
12191 delay_slot_ok = is_delay_slot_valid (insn);
12192 if (!delay_slot_ok && !wrong_delay_slot_insns)
12195 wrong_delay_slot_insns = TRUE;
12197 more_alts = (insn + 1 < past
12198 && strcmp (insn[0].name, insn[1].name) == 0);
12199 if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok)
12201 static char buf[256];
12208 if (wrong_delay_slot_insns && need_delay_slot_ok)
12210 gas_assert (firstinsn);
12211 need_delay_slot_ok = FALSE;
12217 obstack_free (&mips_operand_tokens, tokens);
12222 sprintf (buf, _("Opcode not supported on this processor: %s (%s)"),
12223 mips_cpu_info_from_arch (mips_opts.arch)->name,
12224 mips_cpu_info_from_isa (mips_opts.isa)->name);
12225 else if (mips_opts.insn32)
12226 sprintf (buf, _("Opcode not supported in the `insn32' mode"));
12228 sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"),
12229 8 * forced_insn_length);
12235 imm_expr.X_op = O_absent;
12236 imm2_expr.X_op = O_absent;
12237 offset_expr.X_op = O_absent;
12238 offset_reloc[0] = BFD_RELOC_UNUSED;
12239 offset_reloc[1] = BFD_RELOC_UNUSED;
12240 offset_reloc[2] = BFD_RELOC_UNUSED;
12242 create_insn (ip, insn);
12244 memset (&arg, 0, sizeof (arg));
12246 arg.token = tokens;
12248 arg.last_regno = ILLEGAL_REG;
12249 arg.dest_regno = ILLEGAL_REG;
12250 arg.soft_match = (more_alts
12251 || (wrong_delay_slot_insns && need_delay_slot_ok));
12252 for (args = insn->args;; ++args)
12254 if (arg.token->type == OT_END)
12256 /* Handle unary instructions in which only one operand is given.
12257 The source is then the same as the destination. */
12258 if (arg.opnum == 1 && *args == ',')
12266 arg.token = tokens;
12271 /* Treat elided base registers as $0. */
12272 if (strcmp (args, "(b)") == 0)
12275 /* Fail the match if there were too few operands. */
12279 /* Successful match. */
12280 if (arg.dest_regno == arg.last_regno
12281 && strncmp (ip->insn_mo->name, "jalr", 4) == 0)
12283 if (arg.opnum == 2)
12284 as_bad (_("Source and destination must be different"));
12285 else if (arg.last_regno == 31)
12286 as_bad (_("A destination register must be supplied"));
12288 check_completed_insn (&arg);
12289 obstack_free (&mips_operand_tokens, tokens);
12293 /* Fail the match if the line has too many operands. */
12297 /* Handle characters that need to match exactly. */
12298 if (*args == '(' || *args == ')' || *args == ',')
12300 if (match_char (&arg, *args))
12305 /* Handle special macro operands. Work out the properties of
12308 arg.lax_max = FALSE;
12309 optional_reg = FALSE;
12328 /* If these integer forms come last, there is no other
12329 form of the instruction that could match. Prefer to
12330 give detailed error messages where possible. */
12332 arg.soft_match = FALSE;
12336 /* "+I" is like "I", except that imm2_expr is used. */
12337 if (match_const_int (&arg, &imm2_expr.X_add_number, 0))
12338 imm2_expr.X_op = O_constant;
12340 insn_error = _("absolute expression required");
12341 if (HAVE_32BIT_GPRS)
12342 normalize_constant_expr (&imm2_expr);
12347 *offset_reloc = BFD_RELOC_MIPS_JMP;
12377 /* If these integer forms come last, there is no other
12378 form of the instruction that could match. Prefer to
12379 give detailed error messages where possible. */
12381 arg.soft_match = FALSE;
12389 /* We have already matched a comma by this point, so the register
12390 is only optional if there is another operand to come. */
12391 gas_assert (arg.opnum == 2);
12392 optional_reg = (args[1] == ',');
12396 if (match_const_int (&arg, &imm_expr.X_add_number, 0))
12397 imm_expr.X_op = O_constant;
12399 insn_error = _("absolute expression required");
12400 if (HAVE_32BIT_GPRS)
12401 normalize_constant_expr (&imm_expr);
12405 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
12407 /* Assume that the offset has been elided and that what
12408 we saw was a base register. The match will fail later
12409 if that assumption turns out to be wrong. */
12410 offset_expr.X_op = O_constant;
12411 offset_expr.X_add_number = 0;
12413 else if (match_expression (&arg, &offset_expr, offset_reloc))
12414 normalize_address_expr (&offset_expr);
12416 insn_error = _("absolute expression required");
12420 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
12422 insn_error = _("floating-point expression required");
12426 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
12428 insn_error = _("floating-point expression required");
12432 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
12434 insn_error = _("floating-point expression required");
12438 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
12440 insn_error = _("floating-point expression required");
12443 /* ??? This is the traditional behavior, but is flaky if
12444 there are alternative versions of the same instruction
12445 for different subarchitectures. The next alternative
12446 might not be suitable. */
12448 /* For compatibility with older assemblers, we accept
12449 0x8000-0xffff as signed 16-bit numbers when only
12450 signed numbers are allowed. */
12451 arg.lax_max = !more_alts;
12453 /* Only accept non-constant operands if this is the
12454 final alternative. Later alternatives might include
12455 a macro implementation. */
12456 arg.allow_nonconst = !more_alts;
12460 /* There are no macro implementations for out-of-range values. */
12461 arg.allow_nonconst = TRUE;
12465 /* There should always be a macro implementation. */
12466 arg.allow_nonconst = FALSE;
12470 *offset_reloc = BFD_RELOC_16_PCREL_S2;
12474 *offset_reloc = BFD_RELOC_MIPS_JMP;
12478 gas_assert (mips_opts.micromips);
12485 /* We have already matched a comma by this point,
12486 so the register is only optional if there is another
12487 operand to come. */
12488 gas_assert (arg.opnum == 2);
12489 optional_reg = (args[2] == ',');
12494 if (!forced_insn_length)
12495 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
12497 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
12499 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
12505 operand = (mips_opts.micromips
12506 ? decode_micromips_operand (args)
12507 : decode_mips_operand (args));
12512 && (arg.token[0].type != OT_REG
12513 || arg.token[1].type == OT_END))
12515 /* Assume that the register has been elided and is the
12516 same as the first operand. */
12517 arg.token = tokens;
12521 if (!match_operand (&arg, operand))
12524 /* Skip prefixes. */
12525 if (*args == '+' || *args == 'm')
12530 /* Args don't match. */
12531 insn_error = _("Illegal operands");
12537 if (wrong_delay_slot_insns && need_delay_slot_ok)
12539 gas_assert (firstinsn);
12540 need_delay_slot_ok = FALSE;
12545 obstack_free (&mips_operand_tokens, tokens);
12550 /* As for mips_ip, but used when assembling MIPS16 code.
12551 Also set forced_insn_length to the resulting instruction size in
12552 bytes if the user explicitly requested a small or extended instruction. */
12555 mips16_ip (char *str, struct mips_cl_insn *ip)
12559 struct mips_opcode *insn;
12560 const struct mips_operand *operand;
12561 const struct mips_operand *ext_operand;
12562 struct mips_arg_info arg;
12563 struct mips_operand_token *tokens;
12564 bfd_boolean optional_reg;
12568 forced_insn_length = 0;
12570 for (s = str; ISLOWER (*s); ++s)
12582 if (s[1] == 't' && s[2] == ' ')
12585 forced_insn_length = 2;
12589 else if (s[1] == 'e' && s[2] == ' ')
12592 forced_insn_length = 4;
12596 /* Fall through. */
12598 insn_error = _("unknown opcode");
12602 if (mips_opts.noautoextend && !forced_insn_length)
12603 forced_insn_length = 2;
12605 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
12607 insn_error = _("unrecognized opcode");
12611 tokens = mips_parse_arguments (s, 0);
12618 bfd_boolean more_alts;
12621 gas_assert (strcmp (insn->name, str) == 0);
12623 ok = is_opcode_valid_16 (insn);
12624 more_alts = (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
12625 && strcmp (insn[0].name, insn[1].name) == 0);
12637 static char buf[100];
12639 _("Opcode not supported on this processor: %s (%s)"),
12640 mips_cpu_info_from_arch (mips_opts.arch)->name,
12641 mips_cpu_info_from_isa (mips_opts.isa)->name);
12644 obstack_free (&mips_operand_tokens, tokens);
12649 create_insn (ip, insn);
12650 imm_expr.X_op = O_absent;
12651 imm2_expr.X_op = O_absent;
12652 offset_expr.X_op = O_absent;
12653 offset_reloc[0] = BFD_RELOC_UNUSED;
12654 offset_reloc[1] = BFD_RELOC_UNUSED;
12655 offset_reloc[2] = BFD_RELOC_UNUSED;
12658 memset (&arg, 0, sizeof (arg));
12660 arg.token = tokens;
12662 arg.last_regno = ILLEGAL_REG;
12663 arg.dest_regno = ILLEGAL_REG;
12664 arg.soft_match = more_alts;
12666 for (args = insn->args; 1; ++args)
12670 if (arg.token->type == OT_END)
12674 /* Handle unary instructions in which only one operand is given.
12675 The source is then the same as the destination. */
12676 if (arg.opnum == 1 && *args == ',')
12681 arg.token = tokens;
12686 /* Fail the match if there were too few operands. */
12690 /* Successful match. Stuff the immediate value in now, if
12692 if (insn->pinfo == INSN_MACRO)
12694 gas_assert (relax_char == 0 || relax_char == 'p');
12695 gas_assert (*offset_reloc == BFD_RELOC_UNUSED);
12697 else if (relax_char
12698 && offset_expr.X_op == O_constant
12699 && calculate_reloc (*offset_reloc,
12700 offset_expr.X_add_number,
12703 mips16_immed (NULL, 0, relax_char, *offset_reloc, value,
12704 forced_insn_length, &ip->insn_opcode);
12705 offset_expr.X_op = O_absent;
12706 *offset_reloc = BFD_RELOC_UNUSED;
12708 else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED)
12710 if (forced_insn_length == 2)
12711 as_bad (_("invalid unextended operand value"));
12712 forced_insn_length = 4;
12713 ip->insn_opcode |= MIPS16_EXTEND;
12715 else if (relax_char)
12716 *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char;
12718 check_completed_insn (&arg);
12719 obstack_free (&mips_operand_tokens, tokens);
12723 /* Fail the match if the line has too many operands. */
12727 /* Handle characters that need to match exactly. */
12728 if (*args == '(' || *args == ')' || *args == ',')
12730 if (match_char (&arg, *args))
12736 optional_reg = FALSE;
12742 optional_reg = (args[1] == ',');
12754 if (match_const_int (&arg, &imm_expr.X_add_number, 0))
12755 imm_expr.X_op = O_constant;
12757 insn_error = _("absolute expression required");
12758 if (HAVE_32BIT_GPRS)
12759 normalize_constant_expr (&imm_expr);
12764 *offset_reloc = BFD_RELOC_MIPS16_JMP;
12765 ip->insn_opcode <<= 16;
12769 operand = decode_mips16_operand (c, FALSE);
12773 /* '6' is a special case. It is used for BREAK and SDBBP,
12774 whose operands are only meaningful to the software that decodes
12775 them. This means that there is no architectural reason why
12776 they cannot be prefixed by EXTEND, but in practice,
12777 exception handlers will only look at the instruction
12778 itself. We therefore allow '6' to be extended when
12779 disassembling but not when assembling. */
12780 if (operand->type != OP_PCREL && c != '6')
12782 ext_operand = decode_mips16_operand (c, TRUE);
12783 if (operand != ext_operand)
12785 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
12787 offset_expr.X_op = O_constant;
12788 offset_expr.X_add_number = 0;
12793 /* We need the OT_INTEGER check because some MIPS16
12794 immediate variants are listed before the register ones. */
12795 if (arg.token->type != OT_INTEGER
12796 || !match_expression (&arg, &offset_expr, offset_reloc))
12799 /* '8' is used for SLTI(U) and has traditionally not
12800 been allowed to take relocation operators. */
12801 if (offset_reloc[0] != BFD_RELOC_UNUSED
12802 && (ext_operand->size != 16 || c == '8'))
12811 && (arg.token[0].type != OT_REG
12812 || arg.token[1].type == OT_END))
12814 /* Assume that the register has been elided and is the
12815 same as the first operand. */
12816 arg.token = tokens;
12820 if (!match_operand (&arg, operand))
12825 /* Args don't match. */
12832 insn_error = _("illegal operands");
12834 obstack_free (&mips_operand_tokens, tokens);
12839 /* Marshal immediate value VAL for an extended MIPS16 instruction.
12840 NBITS is the number of significant bits in VAL. */
12842 static unsigned long
12843 mips16_immed_extend (offsetT val, unsigned int nbits)
12848 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
12851 else if (nbits == 15)
12853 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
12858 extval = ((val & 0x1f) << 6) | (val & 0x20);
12861 return (extval << 16) | val;
12864 /* Like decode_mips16_operand, but require the operand to be defined and
12865 require it to be an integer. */
12867 static const struct mips_int_operand *
12868 mips16_immed_operand (int type, bfd_boolean extended_p)
12870 const struct mips_operand *operand;
12872 operand = decode_mips16_operand (type, extended_p);
12873 if (!operand || (operand->type != OP_INT && operand->type != OP_PCREL))
12875 return (const struct mips_int_operand *) operand;
12878 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
12881 mips16_immed_in_range_p (const struct mips_int_operand *operand,
12882 bfd_reloc_code_real_type reloc, offsetT sval)
12884 int min_val, max_val;
12886 min_val = mips_int_operand_min (operand);
12887 max_val = mips_int_operand_max (operand);
12888 if (reloc != BFD_RELOC_UNUSED)
12891 sval = SEXT_16BIT (sval);
12896 return (sval >= min_val
12898 && (sval & ((1 << operand->shift) - 1)) == 0);
12901 /* Install immediate value VAL into MIPS16 instruction *INSN,
12902 extending it if necessary. The instruction in *INSN may
12903 already be extended.
12905 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
12906 if none. In the former case, VAL is a 16-bit number with no
12907 defined signedness.
12909 TYPE is the type of the immediate field. USER_INSN_LENGTH
12910 is the length that the user requested, or 0 if none. */
12913 mips16_immed (char *file, unsigned int line, int type,
12914 bfd_reloc_code_real_type reloc, offsetT val,
12915 unsigned int user_insn_length, unsigned long *insn)
12917 const struct mips_int_operand *operand;
12918 unsigned int uval, length;
12920 operand = mips16_immed_operand (type, FALSE);
12921 if (!mips16_immed_in_range_p (operand, reloc, val))
12923 /* We need an extended instruction. */
12924 if (user_insn_length == 2)
12925 as_bad_where (file, line, _("invalid unextended operand value"));
12927 *insn |= MIPS16_EXTEND;
12929 else if (user_insn_length == 4)
12931 /* The operand doesn't force an unextended instruction to be extended.
12932 Warn if the user wanted an extended instruction anyway. */
12933 *insn |= MIPS16_EXTEND;
12934 as_warn_where (file, line,
12935 _("extended operand requested but not required"));
12938 length = mips16_opcode_length (*insn);
12941 operand = mips16_immed_operand (type, TRUE);
12942 if (!mips16_immed_in_range_p (operand, reloc, val))
12943 as_bad_where (file, line,
12944 _("operand value out of range for instruction"));
12946 uval = ((unsigned int) val >> operand->shift) - operand->bias;
12948 *insn = mips_insert_operand (&operand->root, *insn, uval);
12950 *insn |= mips16_immed_extend (uval, operand->root.size);
12953 struct percent_op_match
12956 bfd_reloc_code_real_type reloc;
12959 static const struct percent_op_match mips_percent_op[] =
12961 {"%lo", BFD_RELOC_LO16},
12962 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
12963 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
12964 {"%call16", BFD_RELOC_MIPS_CALL16},
12965 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
12966 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
12967 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
12968 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
12969 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
12970 {"%got", BFD_RELOC_MIPS_GOT16},
12971 {"%gp_rel", BFD_RELOC_GPREL16},
12972 {"%half", BFD_RELOC_16},
12973 {"%highest", BFD_RELOC_MIPS_HIGHEST},
12974 {"%higher", BFD_RELOC_MIPS_HIGHER},
12975 {"%neg", BFD_RELOC_MIPS_SUB},
12976 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
12977 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
12978 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
12979 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
12980 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
12981 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
12982 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
12983 {"%hi", BFD_RELOC_HI16_S}
12986 static const struct percent_op_match mips16_percent_op[] =
12988 {"%lo", BFD_RELOC_MIPS16_LO16},
12989 {"%gprel", BFD_RELOC_MIPS16_GPREL},
12990 {"%got", BFD_RELOC_MIPS16_GOT16},
12991 {"%call16", BFD_RELOC_MIPS16_CALL16},
12992 {"%hi", BFD_RELOC_MIPS16_HI16_S},
12993 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
12994 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
12995 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
12996 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
12997 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
12998 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
12999 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
13003 /* Return true if *STR points to a relocation operator. When returning true,
13004 move *STR over the operator and store its relocation code in *RELOC.
13005 Leave both *STR and *RELOC alone when returning false. */
13008 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
13010 const struct percent_op_match *percent_op;
13013 if (mips_opts.mips16)
13015 percent_op = mips16_percent_op;
13016 limit = ARRAY_SIZE (mips16_percent_op);
13020 percent_op = mips_percent_op;
13021 limit = ARRAY_SIZE (mips_percent_op);
13024 for (i = 0; i < limit; i++)
13025 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
13027 int len = strlen (percent_op[i].str);
13029 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
13032 *str += strlen (percent_op[i].str);
13033 *reloc = percent_op[i].reloc;
13035 /* Check whether the output BFD supports this relocation.
13036 If not, issue an error and fall back on something safe. */
13037 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
13039 as_bad (_("relocation %s isn't supported by the current ABI"),
13040 percent_op[i].str);
13041 *reloc = BFD_RELOC_UNUSED;
13049 /* Parse string STR as a 16-bit relocatable operand. Store the
13050 expression in *EP and the relocations in the array starting
13051 at RELOC. Return the number of relocation operators used.
13053 On exit, EXPR_END points to the first character after the expression. */
13056 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
13059 bfd_reloc_code_real_type reversed_reloc[3];
13060 size_t reloc_index, i;
13061 int crux_depth, str_depth;
13064 /* Search for the start of the main expression, recoding relocations
13065 in REVERSED_RELOC. End the loop with CRUX pointing to the start
13066 of the main expression and with CRUX_DEPTH containing the number
13067 of open brackets at that point. */
13074 crux_depth = str_depth;
13076 /* Skip over whitespace and brackets, keeping count of the number
13078 while (*str == ' ' || *str == '\t' || *str == '(')
13083 && reloc_index < (HAVE_NEWABI ? 3 : 1)
13084 && parse_relocation (&str, &reversed_reloc[reloc_index]));
13086 my_getExpression (ep, crux);
13089 /* Match every open bracket. */
13090 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
13094 if (crux_depth > 0)
13095 as_bad (_("unclosed '('"));
13099 if (reloc_index != 0)
13101 prev_reloc_op_frag = frag_now;
13102 for (i = 0; i < reloc_index; i++)
13103 reloc[i] = reversed_reloc[reloc_index - 1 - i];
13106 return reloc_index;
13110 my_getExpression (expressionS *ep, char *str)
13114 save_in = input_line_pointer;
13115 input_line_pointer = str;
13117 expr_end = input_line_pointer;
13118 input_line_pointer = save_in;
13122 md_atof (int type, char *litP, int *sizeP)
13124 return ieee_md_atof (type, litP, sizeP, target_big_endian);
13128 md_number_to_chars (char *buf, valueT val, int n)
13130 if (target_big_endian)
13131 number_to_chars_bigendian (buf, val, n);
13133 number_to_chars_littleendian (buf, val, n);
13136 static int support_64bit_objects(void)
13138 const char **list, **l;
13141 list = bfd_target_list ();
13142 for (l = list; *l != NULL; l++)
13143 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
13144 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
13146 yes = (*l != NULL);
13151 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
13152 NEW_VALUE. Warn if another value was already specified. Note:
13153 we have to defer parsing the -march and -mtune arguments in order
13154 to handle 'from-abi' correctly, since the ABI might be specified
13155 in a later argument. */
13158 mips_set_option_string (const char **string_ptr, const char *new_value)
13160 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
13161 as_warn (_("A different %s was already specified, is now %s"),
13162 string_ptr == &mips_arch_string ? "-march" : "-mtune",
13165 *string_ptr = new_value;
13169 md_parse_option (int c, char *arg)
13173 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
13174 if (c == mips_ases[i].option_on || c == mips_ases[i].option_off)
13176 file_ase_explicit |= mips_set_ase (&mips_ases[i],
13177 c == mips_ases[i].option_on);
13183 case OPTION_CONSTRUCT_FLOATS:
13184 mips_disable_float_construction = 0;
13187 case OPTION_NO_CONSTRUCT_FLOATS:
13188 mips_disable_float_construction = 1;
13200 target_big_endian = 1;
13204 target_big_endian = 0;
13210 else if (arg[0] == '0')
13212 else if (arg[0] == '1')
13222 mips_debug = atoi (arg);
13226 file_mips_isa = ISA_MIPS1;
13230 file_mips_isa = ISA_MIPS2;
13234 file_mips_isa = ISA_MIPS3;
13238 file_mips_isa = ISA_MIPS4;
13242 file_mips_isa = ISA_MIPS5;
13245 case OPTION_MIPS32:
13246 file_mips_isa = ISA_MIPS32;
13249 case OPTION_MIPS32R2:
13250 file_mips_isa = ISA_MIPS32R2;
13253 case OPTION_MIPS64R2:
13254 file_mips_isa = ISA_MIPS64R2;
13257 case OPTION_MIPS64:
13258 file_mips_isa = ISA_MIPS64;
13262 mips_set_option_string (&mips_tune_string, arg);
13266 mips_set_option_string (&mips_arch_string, arg);
13270 mips_set_option_string (&mips_arch_string, "4650");
13271 mips_set_option_string (&mips_tune_string, "4650");
13274 case OPTION_NO_M4650:
13278 mips_set_option_string (&mips_arch_string, "4010");
13279 mips_set_option_string (&mips_tune_string, "4010");
13282 case OPTION_NO_M4010:
13286 mips_set_option_string (&mips_arch_string, "4100");
13287 mips_set_option_string (&mips_tune_string, "4100");
13290 case OPTION_NO_M4100:
13294 mips_set_option_string (&mips_arch_string, "3900");
13295 mips_set_option_string (&mips_tune_string, "3900");
13298 case OPTION_NO_M3900:
13301 case OPTION_MICROMIPS:
13302 if (mips_opts.mips16 == 1)
13304 as_bad (_("-mmicromips cannot be used with -mips16"));
13307 mips_opts.micromips = 1;
13308 mips_no_prev_insn ();
13311 case OPTION_NO_MICROMIPS:
13312 mips_opts.micromips = 0;
13313 mips_no_prev_insn ();
13316 case OPTION_MIPS16:
13317 if (mips_opts.micromips == 1)
13319 as_bad (_("-mips16 cannot be used with -micromips"));
13322 mips_opts.mips16 = 1;
13323 mips_no_prev_insn ();
13326 case OPTION_NO_MIPS16:
13327 mips_opts.mips16 = 0;
13328 mips_no_prev_insn ();
13331 case OPTION_FIX_24K:
13335 case OPTION_NO_FIX_24K:
13339 case OPTION_FIX_LOONGSON2F_JUMP:
13340 mips_fix_loongson2f_jump = TRUE;
13343 case OPTION_NO_FIX_LOONGSON2F_JUMP:
13344 mips_fix_loongson2f_jump = FALSE;
13347 case OPTION_FIX_LOONGSON2F_NOP:
13348 mips_fix_loongson2f_nop = TRUE;
13351 case OPTION_NO_FIX_LOONGSON2F_NOP:
13352 mips_fix_loongson2f_nop = FALSE;
13355 case OPTION_FIX_VR4120:
13356 mips_fix_vr4120 = 1;
13359 case OPTION_NO_FIX_VR4120:
13360 mips_fix_vr4120 = 0;
13363 case OPTION_FIX_VR4130:
13364 mips_fix_vr4130 = 1;
13367 case OPTION_NO_FIX_VR4130:
13368 mips_fix_vr4130 = 0;
13371 case OPTION_FIX_CN63XXP1:
13372 mips_fix_cn63xxp1 = TRUE;
13375 case OPTION_NO_FIX_CN63XXP1:
13376 mips_fix_cn63xxp1 = FALSE;
13379 case OPTION_RELAX_BRANCH:
13380 mips_relax_branch = 1;
13383 case OPTION_NO_RELAX_BRANCH:
13384 mips_relax_branch = 0;
13387 case OPTION_INSN32:
13388 mips_opts.insn32 = TRUE;
13391 case OPTION_NO_INSN32:
13392 mips_opts.insn32 = FALSE;
13395 case OPTION_MSHARED:
13396 mips_in_shared = TRUE;
13399 case OPTION_MNO_SHARED:
13400 mips_in_shared = FALSE;
13403 case OPTION_MSYM32:
13404 mips_opts.sym32 = TRUE;
13407 case OPTION_MNO_SYM32:
13408 mips_opts.sym32 = FALSE;
13411 /* When generating ELF code, we permit -KPIC and -call_shared to
13412 select SVR4_PIC, and -non_shared to select no PIC. This is
13413 intended to be compatible with Irix 5. */
13414 case OPTION_CALL_SHARED:
13415 mips_pic = SVR4_PIC;
13416 mips_abicalls = TRUE;
13419 case OPTION_CALL_NONPIC:
13421 mips_abicalls = TRUE;
13424 case OPTION_NON_SHARED:
13426 mips_abicalls = FALSE;
13429 /* The -xgot option tells the assembler to use 32 bit offsets
13430 when accessing the got in SVR4_PIC mode. It is for Irix
13437 g_switch_value = atoi (arg);
13441 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
13444 mips_abi = O32_ABI;
13448 mips_abi = N32_ABI;
13452 mips_abi = N64_ABI;
13453 if (!support_64bit_objects())
13454 as_fatal (_("No compiled in support for 64 bit object file format"));
13458 file_mips_gp32 = 1;
13462 file_mips_gp32 = 0;
13466 file_mips_fp32 = 1;
13470 file_mips_fp32 = 0;
13473 case OPTION_SINGLE_FLOAT:
13474 file_mips_single_float = 1;
13477 case OPTION_DOUBLE_FLOAT:
13478 file_mips_single_float = 0;
13481 case OPTION_SOFT_FLOAT:
13482 file_mips_soft_float = 1;
13485 case OPTION_HARD_FLOAT:
13486 file_mips_soft_float = 0;
13490 if (strcmp (arg, "32") == 0)
13491 mips_abi = O32_ABI;
13492 else if (strcmp (arg, "o64") == 0)
13493 mips_abi = O64_ABI;
13494 else if (strcmp (arg, "n32") == 0)
13495 mips_abi = N32_ABI;
13496 else if (strcmp (arg, "64") == 0)
13498 mips_abi = N64_ABI;
13499 if (! support_64bit_objects())
13500 as_fatal (_("No compiled in support for 64 bit object file "
13503 else if (strcmp (arg, "eabi") == 0)
13504 mips_abi = EABI_ABI;
13507 as_fatal (_("invalid abi -mabi=%s"), arg);
13512 case OPTION_M7000_HILO_FIX:
13513 mips_7000_hilo_fix = TRUE;
13516 case OPTION_MNO_7000_HILO_FIX:
13517 mips_7000_hilo_fix = FALSE;
13520 case OPTION_MDEBUG:
13521 mips_flag_mdebug = TRUE;
13524 case OPTION_NO_MDEBUG:
13525 mips_flag_mdebug = FALSE;
13529 mips_flag_pdr = TRUE;
13532 case OPTION_NO_PDR:
13533 mips_flag_pdr = FALSE;
13536 case OPTION_MVXWORKS_PIC:
13537 mips_pic = VXWORKS_PIC;
13541 if (strcmp (arg, "2008") == 0)
13542 mips_flag_nan2008 = TRUE;
13543 else if (strcmp (arg, "legacy") == 0)
13544 mips_flag_nan2008 = FALSE;
13547 as_fatal (_("Invalid NaN setting -mnan=%s"), arg);
13556 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
13561 /* Set up globals to generate code for the ISA or processor
13562 described by INFO. */
13565 mips_set_architecture (const struct mips_cpu_info *info)
13569 file_mips_arch = info->cpu;
13570 mips_opts.arch = info->cpu;
13571 mips_opts.isa = info->isa;
13576 /* Likewise for tuning. */
13579 mips_set_tune (const struct mips_cpu_info *info)
13582 mips_tune = info->cpu;
13587 mips_after_parse_args (void)
13589 const struct mips_cpu_info *arch_info = 0;
13590 const struct mips_cpu_info *tune_info = 0;
13592 /* GP relative stuff not working for PE */
13593 if (strncmp (TARGET_OS, "pe", 2) == 0)
13595 if (g_switch_seen && g_switch_value != 0)
13596 as_bad (_("-G not supported in this configuration."));
13597 g_switch_value = 0;
13600 if (mips_abi == NO_ABI)
13601 mips_abi = MIPS_DEFAULT_ABI;
13603 /* The following code determines the architecture and register size.
13604 Similar code was added to GCC 3.3 (see override_options() in
13605 config/mips/mips.c). The GAS and GCC code should be kept in sync
13606 as much as possible. */
13608 if (mips_arch_string != 0)
13609 arch_info = mips_parse_cpu ("-march", mips_arch_string);
13611 if (file_mips_isa != ISA_UNKNOWN)
13613 /* Handle -mipsN. At this point, file_mips_isa contains the
13614 ISA level specified by -mipsN, while arch_info->isa contains
13615 the -march selection (if any). */
13616 if (arch_info != 0)
13618 /* -march takes precedence over -mipsN, since it is more descriptive.
13619 There's no harm in specifying both as long as the ISA levels
13621 if (file_mips_isa != arch_info->isa)
13622 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
13623 mips_cpu_info_from_isa (file_mips_isa)->name,
13624 mips_cpu_info_from_isa (arch_info->isa)->name);
13627 arch_info = mips_cpu_info_from_isa (file_mips_isa);
13630 if (arch_info == 0)
13632 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
13633 gas_assert (arch_info);
13636 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
13637 as_bad (_("-march=%s is not compatible with the selected ABI"),
13640 mips_set_architecture (arch_info);
13642 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
13643 if (mips_tune_string != 0)
13644 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
13646 if (tune_info == 0)
13647 mips_set_tune (arch_info);
13649 mips_set_tune (tune_info);
13651 if (file_mips_gp32 >= 0)
13653 /* The user specified the size of the integer registers. Make sure
13654 it agrees with the ABI and ISA. */
13655 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
13656 as_bad (_("-mgp64 used with a 32-bit processor"));
13657 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
13658 as_bad (_("-mgp32 used with a 64-bit ABI"));
13659 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
13660 as_bad (_("-mgp64 used with a 32-bit ABI"));
13664 /* Infer the integer register size from the ABI and processor.
13665 Restrict ourselves to 32-bit registers if that's all the
13666 processor has, or if the ABI cannot handle 64-bit registers. */
13667 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
13668 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
13671 switch (file_mips_fp32)
13675 /* No user specified float register size.
13676 ??? GAS treats single-float processors as though they had 64-bit
13677 float registers (although it complains when double-precision
13678 instructions are used). As things stand, saying they have 32-bit
13679 registers would lead to spurious "register must be even" messages.
13680 So here we assume float registers are never smaller than the
13682 if (file_mips_gp32 == 0)
13683 /* 64-bit integer registers implies 64-bit float registers. */
13684 file_mips_fp32 = 0;
13685 else if ((mips_opts.ase & FP64_ASES)
13686 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
13687 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
13688 file_mips_fp32 = 0;
13690 /* 32-bit float registers. */
13691 file_mips_fp32 = 1;
13694 /* The user specified the size of the float registers. Check if it
13695 agrees with the ABI and ISA. */
13697 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
13698 as_bad (_("-mfp64 used with a 32-bit fpu"));
13699 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
13700 && !ISA_HAS_MXHC1 (mips_opts.isa))
13701 as_warn (_("-mfp64 used with a 32-bit ABI"));
13704 if (ABI_NEEDS_64BIT_REGS (mips_abi))
13705 as_warn (_("-mfp32 used with a 64-bit ABI"));
13709 /* End of GCC-shared inference code. */
13711 /* This flag is set when we have a 64-bit capable CPU but use only
13712 32-bit wide registers. Note that EABI does not use it. */
13713 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
13714 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
13715 || mips_abi == O32_ABI))
13716 mips_32bitmode = 1;
13718 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
13719 as_bad (_("trap exception not supported at ISA 1"));
13721 /* If the selected architecture includes support for ASEs, enable
13722 generation of code for them. */
13723 if (mips_opts.mips16 == -1)
13724 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
13725 if (mips_opts.micromips == -1)
13726 mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0;
13728 /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those
13729 ASEs from being selected implicitly. */
13730 if (file_mips_fp32 == 1)
13731 file_ase_explicit |= ASE_MIPS3D | ASE_MDMX;
13733 /* If the user didn't explicitly select or deselect a particular ASE,
13734 use the default setting for the CPU. */
13735 mips_opts.ase |= (arch_info->ase & ~file_ase_explicit);
13737 file_mips_isa = mips_opts.isa;
13738 file_ase = mips_opts.ase;
13739 mips_opts.gp32 = file_mips_gp32;
13740 mips_opts.fp32 = file_mips_fp32;
13741 mips_opts.soft_float = file_mips_soft_float;
13742 mips_opts.single_float = file_mips_single_float;
13744 mips_check_isa_supports_ases ();
13746 if (mips_flag_mdebug < 0)
13747 mips_flag_mdebug = 0;
13751 mips_init_after_args (void)
13753 /* initialize opcodes */
13754 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
13755 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
13759 md_pcrel_from (fixS *fixP)
13761 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
13762 switch (fixP->fx_r_type)
13764 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
13765 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
13766 /* Return the address of the delay slot. */
13769 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
13770 case BFD_RELOC_MICROMIPS_JMP:
13771 case BFD_RELOC_16_PCREL_S2:
13772 case BFD_RELOC_MIPS_JMP:
13773 /* Return the address of the delay slot. */
13776 case BFD_RELOC_32_PCREL:
13780 /* We have no relocation type for PC relative MIPS16 instructions. */
13781 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
13782 as_bad_where (fixP->fx_file, fixP->fx_line,
13783 _("PC relative MIPS16 instruction references a different section"));
13788 /* This is called before the symbol table is processed. In order to
13789 work with gcc when using mips-tfile, we must keep all local labels.
13790 However, in other cases, we want to discard them. If we were
13791 called with -g, but we didn't see any debugging information, it may
13792 mean that gcc is smuggling debugging information through to
13793 mips-tfile, in which case we must generate all local labels. */
13796 mips_frob_file_before_adjust (void)
13798 #ifndef NO_ECOFF_DEBUGGING
13799 if (ECOFF_DEBUGGING
13801 && ! ecoff_debugging_seen)
13802 flag_keep_locals = 1;
13806 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
13807 the corresponding LO16 reloc. This is called before md_apply_fix and
13808 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
13809 relocation operators.
13811 For our purposes, a %lo() expression matches a %got() or %hi()
13814 (a) it refers to the same symbol; and
13815 (b) the offset applied in the %lo() expression is no lower than
13816 the offset applied in the %got() or %hi().
13818 (b) allows us to cope with code like:
13821 lh $4,%lo(foo+2)($4)
13823 ...which is legal on RELA targets, and has a well-defined behaviour
13824 if the user knows that adding 2 to "foo" will not induce a carry to
13827 When several %lo()s match a particular %got() or %hi(), we use the
13828 following rules to distinguish them:
13830 (1) %lo()s with smaller offsets are a better match than %lo()s with
13833 (2) %lo()s with no matching %got() or %hi() are better than those
13834 that already have a matching %got() or %hi().
13836 (3) later %lo()s are better than earlier %lo()s.
13838 These rules are applied in order.
13840 (1) means, among other things, that %lo()s with identical offsets are
13841 chosen if they exist.
13843 (2) means that we won't associate several high-part relocations with
13844 the same low-part relocation unless there's no alternative. Having
13845 several high parts for the same low part is a GNU extension; this rule
13846 allows careful users to avoid it.
13848 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
13849 with the last high-part relocation being at the front of the list.
13850 It therefore makes sense to choose the last matching low-part
13851 relocation, all other things being equal. It's also easier
13852 to code that way. */
13855 mips_frob_file (void)
13857 struct mips_hi_fixup *l;
13858 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
13860 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
13862 segment_info_type *seginfo;
13863 bfd_boolean matched_lo_p;
13864 fixS **hi_pos, **lo_pos, **pos;
13866 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
13868 /* If a GOT16 relocation turns out to be against a global symbol,
13869 there isn't supposed to be a matching LO. Ignore %gots against
13870 constants; we'll report an error for those later. */
13871 if (got16_reloc_p (l->fixp->fx_r_type)
13872 && !(l->fixp->fx_addsy
13873 && pic_need_relax (l->fixp->fx_addsy, l->seg)))
13876 /* Check quickly whether the next fixup happens to be a matching %lo. */
13877 if (fixup_has_matching_lo_p (l->fixp))
13880 seginfo = seg_info (l->seg);
13882 /* Set HI_POS to the position of this relocation in the chain.
13883 Set LO_POS to the position of the chosen low-part relocation.
13884 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
13885 relocation that matches an immediately-preceding high-part
13889 matched_lo_p = FALSE;
13890 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
13892 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
13894 if (*pos == l->fixp)
13897 if ((*pos)->fx_r_type == looking_for_rtype
13898 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
13899 && (*pos)->fx_offset >= l->fixp->fx_offset
13901 || (*pos)->fx_offset < (*lo_pos)->fx_offset
13903 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
13906 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
13907 && fixup_has_matching_lo_p (*pos));
13910 /* If we found a match, remove the high-part relocation from its
13911 current position and insert it before the low-part relocation.
13912 Make the offsets match so that fixup_has_matching_lo_p()
13915 We don't warn about unmatched high-part relocations since some
13916 versions of gcc have been known to emit dead "lui ...%hi(...)"
13918 if (lo_pos != NULL)
13920 l->fixp->fx_offset = (*lo_pos)->fx_offset;
13921 if (l->fixp->fx_next != *lo_pos)
13923 *hi_pos = l->fixp->fx_next;
13924 l->fixp->fx_next = *lo_pos;
13932 mips_force_relocation (fixS *fixp)
13934 if (generic_force_reloc (fixp))
13937 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
13938 so that the linker relaxation can update targets. */
13939 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
13940 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
13941 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
13947 /* Read the instruction associated with RELOC from BUF. */
13949 static unsigned int
13950 read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc)
13952 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
13953 return read_compressed_insn (buf, 4);
13955 return read_insn (buf);
13958 /* Write instruction INSN to BUF, given that it has been relocated
13962 write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc,
13963 unsigned long insn)
13965 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
13966 write_compressed_insn (buf, insn, 4);
13968 write_insn (buf, insn);
13971 /* Apply a fixup to the object file. */
13974 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
13977 unsigned long insn;
13978 reloc_howto_type *howto;
13980 /* We ignore generic BFD relocations we don't know about. */
13981 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
13985 gas_assert (fixP->fx_size == 2
13986 || fixP->fx_size == 4
13987 || fixP->fx_r_type == BFD_RELOC_16
13988 || fixP->fx_r_type == BFD_RELOC_64
13989 || fixP->fx_r_type == BFD_RELOC_CTOR
13990 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
13991 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
13992 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
13993 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
13994 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
13996 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
13998 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
13999 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
14000 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
14001 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
14002 || fixP->fx_r_type == BFD_RELOC_32_PCREL);
14004 /* Don't treat parts of a composite relocation as done. There are two
14007 (1) The second and third parts will be against 0 (RSS_UNDEF) but
14008 should nevertheless be emitted if the first part is.
14010 (2) In normal usage, composite relocations are never assembly-time
14011 constants. The easiest way of dealing with the pathological
14012 exceptions is to generate a relocation against STN_UNDEF and
14013 leave everything up to the linker. */
14014 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
14017 switch (fixP->fx_r_type)
14019 case BFD_RELOC_MIPS_TLS_GD:
14020 case BFD_RELOC_MIPS_TLS_LDM:
14021 case BFD_RELOC_MIPS_TLS_DTPREL32:
14022 case BFD_RELOC_MIPS_TLS_DTPREL64:
14023 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
14024 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
14025 case BFD_RELOC_MIPS_TLS_GOTTPREL:
14026 case BFD_RELOC_MIPS_TLS_TPREL32:
14027 case BFD_RELOC_MIPS_TLS_TPREL64:
14028 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
14029 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
14030 case BFD_RELOC_MICROMIPS_TLS_GD:
14031 case BFD_RELOC_MICROMIPS_TLS_LDM:
14032 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
14033 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
14034 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
14035 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
14036 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
14037 case BFD_RELOC_MIPS16_TLS_GD:
14038 case BFD_RELOC_MIPS16_TLS_LDM:
14039 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
14040 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
14041 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
14042 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
14043 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
14044 if (!fixP->fx_addsy)
14046 as_bad_where (fixP->fx_file, fixP->fx_line,
14047 _("TLS relocation against a constant"));
14050 S_SET_THREAD_LOCAL (fixP->fx_addsy);
14053 case BFD_RELOC_MIPS_JMP:
14054 case BFD_RELOC_MIPS_SHIFT5:
14055 case BFD_RELOC_MIPS_SHIFT6:
14056 case BFD_RELOC_MIPS_GOT_DISP:
14057 case BFD_RELOC_MIPS_GOT_PAGE:
14058 case BFD_RELOC_MIPS_GOT_OFST:
14059 case BFD_RELOC_MIPS_SUB:
14060 case BFD_RELOC_MIPS_INSERT_A:
14061 case BFD_RELOC_MIPS_INSERT_B:
14062 case BFD_RELOC_MIPS_DELETE:
14063 case BFD_RELOC_MIPS_HIGHEST:
14064 case BFD_RELOC_MIPS_HIGHER:
14065 case BFD_RELOC_MIPS_SCN_DISP:
14066 case BFD_RELOC_MIPS_REL16:
14067 case BFD_RELOC_MIPS_RELGOT:
14068 case BFD_RELOC_MIPS_JALR:
14069 case BFD_RELOC_HI16:
14070 case BFD_RELOC_HI16_S:
14071 case BFD_RELOC_LO16:
14072 case BFD_RELOC_GPREL16:
14073 case BFD_RELOC_MIPS_LITERAL:
14074 case BFD_RELOC_MIPS_CALL16:
14075 case BFD_RELOC_MIPS_GOT16:
14076 case BFD_RELOC_GPREL32:
14077 case BFD_RELOC_MIPS_GOT_HI16:
14078 case BFD_RELOC_MIPS_GOT_LO16:
14079 case BFD_RELOC_MIPS_CALL_HI16:
14080 case BFD_RELOC_MIPS_CALL_LO16:
14081 case BFD_RELOC_MIPS16_GPREL:
14082 case BFD_RELOC_MIPS16_GOT16:
14083 case BFD_RELOC_MIPS16_CALL16:
14084 case BFD_RELOC_MIPS16_HI16:
14085 case BFD_RELOC_MIPS16_HI16_S:
14086 case BFD_RELOC_MIPS16_LO16:
14087 case BFD_RELOC_MIPS16_JMP:
14088 case BFD_RELOC_MICROMIPS_JMP:
14089 case BFD_RELOC_MICROMIPS_GOT_DISP:
14090 case BFD_RELOC_MICROMIPS_GOT_PAGE:
14091 case BFD_RELOC_MICROMIPS_GOT_OFST:
14092 case BFD_RELOC_MICROMIPS_SUB:
14093 case BFD_RELOC_MICROMIPS_HIGHEST:
14094 case BFD_RELOC_MICROMIPS_HIGHER:
14095 case BFD_RELOC_MICROMIPS_SCN_DISP:
14096 case BFD_RELOC_MICROMIPS_JALR:
14097 case BFD_RELOC_MICROMIPS_HI16:
14098 case BFD_RELOC_MICROMIPS_HI16_S:
14099 case BFD_RELOC_MICROMIPS_LO16:
14100 case BFD_RELOC_MICROMIPS_GPREL16:
14101 case BFD_RELOC_MICROMIPS_LITERAL:
14102 case BFD_RELOC_MICROMIPS_CALL16:
14103 case BFD_RELOC_MICROMIPS_GOT16:
14104 case BFD_RELOC_MICROMIPS_GOT_HI16:
14105 case BFD_RELOC_MICROMIPS_GOT_LO16:
14106 case BFD_RELOC_MICROMIPS_CALL_HI16:
14107 case BFD_RELOC_MICROMIPS_CALL_LO16:
14108 case BFD_RELOC_MIPS_EH:
14113 if (calculate_reloc (fixP->fx_r_type, *valP, &value))
14115 insn = read_reloc_insn (buf, fixP->fx_r_type);
14116 if (mips16_reloc_p (fixP->fx_r_type))
14117 insn |= mips16_immed_extend (value, 16);
14119 insn |= (value & 0xffff);
14120 write_reloc_insn (buf, fixP->fx_r_type, insn);
14123 as_bad_where (fixP->fx_file, fixP->fx_line,
14124 _("Unsupported constant in relocation"));
14129 /* This is handled like BFD_RELOC_32, but we output a sign
14130 extended value if we are only 32 bits. */
14133 if (8 <= sizeof (valueT))
14134 md_number_to_chars (buf, *valP, 8);
14139 if ((*valP & 0x80000000) != 0)
14143 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4);
14144 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4);
14149 case BFD_RELOC_RVA:
14151 case BFD_RELOC_32_PCREL:
14153 /* If we are deleting this reloc entry, we must fill in the
14154 value now. This can happen if we have a .word which is not
14155 resolved when it appears but is later defined. */
14157 md_number_to_chars (buf, *valP, fixP->fx_size);
14160 case BFD_RELOC_16_PCREL_S2:
14161 if ((*valP & 0x3) != 0)
14162 as_bad_where (fixP->fx_file, fixP->fx_line,
14163 _("Branch to misaligned address (%lx)"), (long) *valP);
14165 /* We need to save the bits in the instruction since fixup_segment()
14166 might be deleting the relocation entry (i.e., a branch within
14167 the current segment). */
14168 if (! fixP->fx_done)
14171 /* Update old instruction data. */
14172 insn = read_insn (buf);
14174 if (*valP + 0x20000 <= 0x3ffff)
14176 insn |= (*valP >> 2) & 0xffff;
14177 write_insn (buf, insn);
14179 else if (mips_pic == NO_PIC
14181 && fixP->fx_frag->fr_address >= text_section->vma
14182 && (fixP->fx_frag->fr_address
14183 < text_section->vma + bfd_get_section_size (text_section))
14184 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
14185 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
14186 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
14188 /* The branch offset is too large. If this is an
14189 unconditional branch, and we are not generating PIC code,
14190 we can convert it to an absolute jump instruction. */
14191 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
14192 insn = 0x0c000000; /* jal */
14194 insn = 0x08000000; /* j */
14195 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
14197 fixP->fx_addsy = section_symbol (text_section);
14198 *valP += md_pcrel_from (fixP);
14199 write_insn (buf, insn);
14203 /* If we got here, we have branch-relaxation disabled,
14204 and there's nothing we can do to fix this instruction
14205 without turning it into a longer sequence. */
14206 as_bad_where (fixP->fx_file, fixP->fx_line,
14207 _("Branch out of range"));
14211 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
14212 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
14213 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
14214 /* We adjust the offset back to even. */
14215 if ((*valP & 0x1) != 0)
14218 if (! fixP->fx_done)
14221 /* Should never visit here, because we keep the relocation. */
14225 case BFD_RELOC_VTABLE_INHERIT:
14228 && !S_IS_DEFINED (fixP->fx_addsy)
14229 && !S_IS_WEAK (fixP->fx_addsy))
14230 S_SET_WEAK (fixP->fx_addsy);
14233 case BFD_RELOC_VTABLE_ENTRY:
14241 /* Remember value for tc_gen_reloc. */
14242 fixP->fx_addnumber = *valP;
14252 name = input_line_pointer;
14253 c = get_symbol_end ();
14254 p = (symbolS *) symbol_find_or_make (name);
14255 *input_line_pointer = c;
14259 /* Align the current frag to a given power of two. If a particular
14260 fill byte should be used, FILL points to an integer that contains
14261 that byte, otherwise FILL is null.
14263 This function used to have the comment:
14265 The MIPS assembler also automatically adjusts any preceding label.
14267 The implementation therefore applied the adjustment to a maximum of
14268 one label. However, other label adjustments are applied to batches
14269 of labels, and adjusting just one caused problems when new labels
14270 were added for the sake of debugging or unwind information.
14271 We therefore adjust all preceding labels (given as LABELS) instead. */
14274 mips_align (int to, int *fill, struct insn_label_list *labels)
14276 mips_emit_delays ();
14277 mips_record_compressed_mode ();
14278 if (fill == NULL && subseg_text_p (now_seg))
14279 frag_align_code (to, 0);
14281 frag_align (to, fill ? *fill : 0, 0);
14282 record_alignment (now_seg, to);
14283 mips_move_labels (labels, FALSE);
14286 /* Align to a given power of two. .align 0 turns off the automatic
14287 alignment used by the data creating pseudo-ops. */
14290 s_align (int x ATTRIBUTE_UNUSED)
14292 int temp, fill_value, *fill_ptr;
14293 long max_alignment = 28;
14295 /* o Note that the assembler pulls down any immediately preceding label
14296 to the aligned address.
14297 o It's not documented but auto alignment is reinstated by
14298 a .align pseudo instruction.
14299 o Note also that after auto alignment is turned off the mips assembler
14300 issues an error on attempt to assemble an improperly aligned data item.
14303 temp = get_absolute_expression ();
14304 if (temp > max_alignment)
14305 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
14308 as_warn (_("Alignment negative: 0 assumed."));
14311 if (*input_line_pointer == ',')
14313 ++input_line_pointer;
14314 fill_value = get_absolute_expression ();
14315 fill_ptr = &fill_value;
14321 segment_info_type *si = seg_info (now_seg);
14322 struct insn_label_list *l = si->label_list;
14323 /* Auto alignment should be switched on by next section change. */
14325 mips_align (temp, fill_ptr, l);
14332 demand_empty_rest_of_line ();
14336 s_change_sec (int sec)
14340 /* The ELF backend needs to know that we are changing sections, so
14341 that .previous works correctly. We could do something like check
14342 for an obj_section_change_hook macro, but that might be confusing
14343 as it would not be appropriate to use it in the section changing
14344 functions in read.c, since obj-elf.c intercepts those. FIXME:
14345 This should be cleaner, somehow. */
14346 obj_elf_section_change_hook ();
14348 mips_emit_delays ();
14359 subseg_set (bss_section, (subsegT) get_absolute_expression ());
14360 demand_empty_rest_of_line ();
14364 seg = subseg_new (RDATA_SECTION_NAME,
14365 (subsegT) get_absolute_expression ());
14366 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
14367 | SEC_READONLY | SEC_RELOC
14369 if (strncmp (TARGET_OS, "elf", 3) != 0)
14370 record_alignment (seg, 4);
14371 demand_empty_rest_of_line ();
14375 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
14376 bfd_set_section_flags (stdoutput, seg,
14377 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
14378 if (strncmp (TARGET_OS, "elf", 3) != 0)
14379 record_alignment (seg, 4);
14380 demand_empty_rest_of_line ();
14384 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
14385 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
14386 if (strncmp (TARGET_OS, "elf", 3) != 0)
14387 record_alignment (seg, 4);
14388 demand_empty_rest_of_line ();
14396 s_change_section (int ignore ATTRIBUTE_UNUSED)
14398 char *section_name;
14403 int section_entry_size;
14404 int section_alignment;
14406 section_name = input_line_pointer;
14407 c = get_symbol_end ();
14409 next_c = *(input_line_pointer + 1);
14411 /* Do we have .section Name<,"flags">? */
14412 if (c != ',' || (c == ',' && next_c == '"'))
14414 /* just after name is now '\0'. */
14415 *input_line_pointer = c;
14416 input_line_pointer = section_name;
14417 obj_elf_section (ignore);
14420 input_line_pointer++;
14422 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
14424 section_type = get_absolute_expression ();
14427 if (*input_line_pointer++ == ',')
14428 section_flag = get_absolute_expression ();
14431 if (*input_line_pointer++ == ',')
14432 section_entry_size = get_absolute_expression ();
14434 section_entry_size = 0;
14435 if (*input_line_pointer++ == ',')
14436 section_alignment = get_absolute_expression ();
14438 section_alignment = 0;
14439 /* FIXME: really ignore? */
14440 (void) section_alignment;
14442 section_name = xstrdup (section_name);
14444 /* When using the generic form of .section (as implemented by obj-elf.c),
14445 there's no way to set the section type to SHT_MIPS_DWARF. Users have
14446 traditionally had to fall back on the more common @progbits instead.
14448 There's nothing really harmful in this, since bfd will correct
14449 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
14450 means that, for backwards compatibility, the special_section entries
14451 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
14453 Even so, we shouldn't force users of the MIPS .section syntax to
14454 incorrectly label the sections as SHT_PROGBITS. The best compromise
14455 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
14456 generic type-checking code. */
14457 if (section_type == SHT_MIPS_DWARF)
14458 section_type = SHT_PROGBITS;
14460 obj_elf_change_section (section_name, section_type, section_flag,
14461 section_entry_size, 0, 0, 0);
14463 if (now_seg->name != section_name)
14464 free (section_name);
14468 mips_enable_auto_align (void)
14474 s_cons (int log_size)
14476 segment_info_type *si = seg_info (now_seg);
14477 struct insn_label_list *l = si->label_list;
14479 mips_emit_delays ();
14480 if (log_size > 0 && auto_align)
14481 mips_align (log_size, 0, l);
14482 cons (1 << log_size);
14483 mips_clear_insn_labels ();
14487 s_float_cons (int type)
14489 segment_info_type *si = seg_info (now_seg);
14490 struct insn_label_list *l = si->label_list;
14492 mips_emit_delays ();
14497 mips_align (3, 0, l);
14499 mips_align (2, 0, l);
14503 mips_clear_insn_labels ();
14506 /* Handle .globl. We need to override it because on Irix 5 you are
14509 where foo is an undefined symbol, to mean that foo should be
14510 considered to be the address of a function. */
14513 s_mips_globl (int x ATTRIBUTE_UNUSED)
14522 name = input_line_pointer;
14523 c = get_symbol_end ();
14524 symbolP = symbol_find_or_make (name);
14525 S_SET_EXTERNAL (symbolP);
14527 *input_line_pointer = c;
14528 SKIP_WHITESPACE ();
14530 /* On Irix 5, every global symbol that is not explicitly labelled as
14531 being a function is apparently labelled as being an object. */
14534 if (!is_end_of_line[(unsigned char) *input_line_pointer]
14535 && (*input_line_pointer != ','))
14540 secname = input_line_pointer;
14541 c = get_symbol_end ();
14542 sec = bfd_get_section_by_name (stdoutput, secname);
14544 as_bad (_("%s: no such section"), secname);
14545 *input_line_pointer = c;
14547 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
14548 flag = BSF_FUNCTION;
14551 symbol_get_bfdsym (symbolP)->flags |= flag;
14553 c = *input_line_pointer;
14556 input_line_pointer++;
14557 SKIP_WHITESPACE ();
14558 if (is_end_of_line[(unsigned char) *input_line_pointer])
14564 demand_empty_rest_of_line ();
14568 s_option (int x ATTRIBUTE_UNUSED)
14573 opt = input_line_pointer;
14574 c = get_symbol_end ();
14578 /* FIXME: What does this mean? */
14580 else if (strncmp (opt, "pic", 3) == 0)
14584 i = atoi (opt + 3);
14589 mips_pic = SVR4_PIC;
14590 mips_abicalls = TRUE;
14593 as_bad (_(".option pic%d not supported"), i);
14595 if (mips_pic == SVR4_PIC)
14597 if (g_switch_seen && g_switch_value != 0)
14598 as_warn (_("-G may not be used with SVR4 PIC code"));
14599 g_switch_value = 0;
14600 bfd_set_gp_size (stdoutput, 0);
14604 as_warn (_("Unrecognized option \"%s\""), opt);
14606 *input_line_pointer = c;
14607 demand_empty_rest_of_line ();
14610 /* This structure is used to hold a stack of .set values. */
14612 struct mips_option_stack
14614 struct mips_option_stack *next;
14615 struct mips_set_options options;
14618 static struct mips_option_stack *mips_opts_stack;
14620 /* Handle the .set pseudo-op. */
14623 s_mipsset (int x ATTRIBUTE_UNUSED)
14625 char *name = input_line_pointer, ch;
14626 const struct mips_ase *ase;
14628 while (!is_end_of_line[(unsigned char) *input_line_pointer])
14629 ++input_line_pointer;
14630 ch = *input_line_pointer;
14631 *input_line_pointer = '\0';
14633 if (strcmp (name, "reorder") == 0)
14635 if (mips_opts.noreorder)
14638 else if (strcmp (name, "noreorder") == 0)
14640 if (!mips_opts.noreorder)
14641 start_noreorder ();
14643 else if (strncmp (name, "at=", 3) == 0)
14645 char *s = name + 3;
14647 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
14648 as_bad (_("Unrecognized register name `%s'"), s);
14650 else if (strcmp (name, "at") == 0)
14652 mips_opts.at = ATREG;
14654 else if (strcmp (name, "noat") == 0)
14656 mips_opts.at = ZERO;
14658 else if (strcmp (name, "macro") == 0)
14660 mips_opts.warn_about_macros = 0;
14662 else if (strcmp (name, "nomacro") == 0)
14664 if (mips_opts.noreorder == 0)
14665 as_bad (_("`noreorder' must be set before `nomacro'"));
14666 mips_opts.warn_about_macros = 1;
14668 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
14670 mips_opts.nomove = 0;
14672 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
14674 mips_opts.nomove = 1;
14676 else if (strcmp (name, "bopt") == 0)
14678 mips_opts.nobopt = 0;
14680 else if (strcmp (name, "nobopt") == 0)
14682 mips_opts.nobopt = 1;
14684 else if (strcmp (name, "gp=default") == 0)
14685 mips_opts.gp32 = file_mips_gp32;
14686 else if (strcmp (name, "gp=32") == 0)
14687 mips_opts.gp32 = 1;
14688 else if (strcmp (name, "gp=64") == 0)
14690 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
14691 as_warn (_("%s isa does not support 64-bit registers"),
14692 mips_cpu_info_from_isa (mips_opts.isa)->name);
14693 mips_opts.gp32 = 0;
14695 else if (strcmp (name, "fp=default") == 0)
14696 mips_opts.fp32 = file_mips_fp32;
14697 else if (strcmp (name, "fp=32") == 0)
14698 mips_opts.fp32 = 1;
14699 else if (strcmp (name, "fp=64") == 0)
14701 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
14702 as_warn (_("%s isa does not support 64-bit floating point registers"),
14703 mips_cpu_info_from_isa (mips_opts.isa)->name);
14704 mips_opts.fp32 = 0;
14706 else if (strcmp (name, "softfloat") == 0)
14707 mips_opts.soft_float = 1;
14708 else if (strcmp (name, "hardfloat") == 0)
14709 mips_opts.soft_float = 0;
14710 else if (strcmp (name, "singlefloat") == 0)
14711 mips_opts.single_float = 1;
14712 else if (strcmp (name, "doublefloat") == 0)
14713 mips_opts.single_float = 0;
14714 else if (strcmp (name, "mips16") == 0
14715 || strcmp (name, "MIPS-16") == 0)
14717 if (mips_opts.micromips == 1)
14718 as_fatal (_("`mips16' cannot be used with `micromips'"));
14719 mips_opts.mips16 = 1;
14721 else if (strcmp (name, "nomips16") == 0
14722 || strcmp (name, "noMIPS-16") == 0)
14723 mips_opts.mips16 = 0;
14724 else if (strcmp (name, "micromips") == 0)
14726 if (mips_opts.mips16 == 1)
14727 as_fatal (_("`micromips' cannot be used with `mips16'"));
14728 mips_opts.micromips = 1;
14730 else if (strcmp (name, "nomicromips") == 0)
14731 mips_opts.micromips = 0;
14732 else if (name[0] == 'n'
14734 && (ase = mips_lookup_ase (name + 2)))
14735 mips_set_ase (ase, FALSE);
14736 else if ((ase = mips_lookup_ase (name)))
14737 mips_set_ase (ase, TRUE);
14738 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
14742 /* Permit the user to change the ISA and architecture on the fly.
14743 Needless to say, misuse can cause serious problems. */
14744 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
14747 mips_opts.isa = file_mips_isa;
14748 mips_opts.arch = file_mips_arch;
14750 else if (strncmp (name, "arch=", 5) == 0)
14752 const struct mips_cpu_info *p;
14754 p = mips_parse_cpu("internal use", name + 5);
14756 as_bad (_("unknown architecture %s"), name + 5);
14759 mips_opts.arch = p->cpu;
14760 mips_opts.isa = p->isa;
14763 else if (strncmp (name, "mips", 4) == 0)
14765 const struct mips_cpu_info *p;
14767 p = mips_parse_cpu("internal use", name);
14769 as_bad (_("unknown ISA level %s"), name + 4);
14772 mips_opts.arch = p->cpu;
14773 mips_opts.isa = p->isa;
14777 as_bad (_("unknown ISA or architecture %s"), name);
14779 switch (mips_opts.isa)
14787 mips_opts.gp32 = 1;
14788 mips_opts.fp32 = 1;
14795 mips_opts.gp32 = 0;
14796 if (mips_opts.arch == CPU_R5900)
14798 mips_opts.fp32 = 1;
14802 mips_opts.fp32 = 0;
14806 as_bad (_("unknown ISA level %s"), name + 4);
14811 mips_opts.gp32 = file_mips_gp32;
14812 mips_opts.fp32 = file_mips_fp32;
14815 else if (strcmp (name, "autoextend") == 0)
14816 mips_opts.noautoextend = 0;
14817 else if (strcmp (name, "noautoextend") == 0)
14818 mips_opts.noautoextend = 1;
14819 else if (strcmp (name, "insn32") == 0)
14820 mips_opts.insn32 = TRUE;
14821 else if (strcmp (name, "noinsn32") == 0)
14822 mips_opts.insn32 = FALSE;
14823 else if (strcmp (name, "push") == 0)
14825 struct mips_option_stack *s;
14827 s = (struct mips_option_stack *) xmalloc (sizeof *s);
14828 s->next = mips_opts_stack;
14829 s->options = mips_opts;
14830 mips_opts_stack = s;
14832 else if (strcmp (name, "pop") == 0)
14834 struct mips_option_stack *s;
14836 s = mips_opts_stack;
14838 as_bad (_(".set pop with no .set push"));
14841 /* If we're changing the reorder mode we need to handle
14842 delay slots correctly. */
14843 if (s->options.noreorder && ! mips_opts.noreorder)
14844 start_noreorder ();
14845 else if (! s->options.noreorder && mips_opts.noreorder)
14848 mips_opts = s->options;
14849 mips_opts_stack = s->next;
14853 else if (strcmp (name, "sym32") == 0)
14854 mips_opts.sym32 = TRUE;
14855 else if (strcmp (name, "nosym32") == 0)
14856 mips_opts.sym32 = FALSE;
14857 else if (strchr (name, ','))
14859 /* Generic ".set" directive; use the generic handler. */
14860 *input_line_pointer = ch;
14861 input_line_pointer = name;
14867 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
14869 mips_check_isa_supports_ases ();
14870 *input_line_pointer = ch;
14871 demand_empty_rest_of_line ();
14874 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
14875 .option pic2. It means to generate SVR4 PIC calls. */
14878 s_abicalls (int ignore ATTRIBUTE_UNUSED)
14880 mips_pic = SVR4_PIC;
14881 mips_abicalls = TRUE;
14883 if (g_switch_seen && g_switch_value != 0)
14884 as_warn (_("-G may not be used with SVR4 PIC code"));
14885 g_switch_value = 0;
14887 bfd_set_gp_size (stdoutput, 0);
14888 demand_empty_rest_of_line ();
14891 /* Handle the .cpload pseudo-op. This is used when generating SVR4
14892 PIC code. It sets the $gp register for the function based on the
14893 function address, which is in the register named in the argument.
14894 This uses a relocation against _gp_disp, which is handled specially
14895 by the linker. The result is:
14896 lui $gp,%hi(_gp_disp)
14897 addiu $gp,$gp,%lo(_gp_disp)
14898 addu $gp,$gp,.cpload argument
14899 The .cpload argument is normally $25 == $t9.
14901 The -mno-shared option changes this to:
14902 lui $gp,%hi(__gnu_local_gp)
14903 addiu $gp,$gp,%lo(__gnu_local_gp)
14904 and the argument is ignored. This saves an instruction, but the
14905 resulting code is not position independent; it uses an absolute
14906 address for __gnu_local_gp. Thus code assembled with -mno-shared
14907 can go into an ordinary executable, but not into a shared library. */
14910 s_cpload (int ignore ATTRIBUTE_UNUSED)
14916 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
14917 .cpload is ignored. */
14918 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
14924 if (mips_opts.mips16)
14926 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
14927 ignore_rest_of_line ();
14931 /* .cpload should be in a .set noreorder section. */
14932 if (mips_opts.noreorder == 0)
14933 as_warn (_(".cpload not in noreorder section"));
14935 reg = tc_get_register (0);
14937 /* If we need to produce a 64-bit address, we are better off using
14938 the default instruction sequence. */
14939 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
14941 ex.X_op = O_symbol;
14942 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
14944 ex.X_op_symbol = NULL;
14945 ex.X_add_number = 0;
14947 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
14948 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
14950 mips_mark_labels ();
14951 mips_assembling_insn = TRUE;
14954 macro_build_lui (&ex, mips_gp_register);
14955 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
14956 mips_gp_register, BFD_RELOC_LO16);
14958 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
14959 mips_gp_register, reg);
14962 mips_assembling_insn = FALSE;
14963 demand_empty_rest_of_line ();
14966 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
14967 .cpsetup $reg1, offset|$reg2, label
14969 If offset is given, this results in:
14970 sd $gp, offset($sp)
14971 lui $gp, %hi(%neg(%gp_rel(label)))
14972 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
14973 daddu $gp, $gp, $reg1
14975 If $reg2 is given, this results in:
14976 daddu $reg2, $gp, $0
14977 lui $gp, %hi(%neg(%gp_rel(label)))
14978 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
14979 daddu $gp, $gp, $reg1
14980 $reg1 is normally $25 == $t9.
14982 The -mno-shared option replaces the last three instructions with
14984 addiu $gp,$gp,%lo(_gp) */
14987 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
14989 expressionS ex_off;
14990 expressionS ex_sym;
14993 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
14994 We also need NewABI support. */
14995 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15001 if (mips_opts.mips16)
15003 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
15004 ignore_rest_of_line ();
15008 reg1 = tc_get_register (0);
15009 SKIP_WHITESPACE ();
15010 if (*input_line_pointer != ',')
15012 as_bad (_("missing argument separator ',' for .cpsetup"));
15016 ++input_line_pointer;
15017 SKIP_WHITESPACE ();
15018 if (*input_line_pointer == '$')
15020 mips_cpreturn_register = tc_get_register (0);
15021 mips_cpreturn_offset = -1;
15025 mips_cpreturn_offset = get_absolute_expression ();
15026 mips_cpreturn_register = -1;
15028 SKIP_WHITESPACE ();
15029 if (*input_line_pointer != ',')
15031 as_bad (_("missing argument separator ',' for .cpsetup"));
15035 ++input_line_pointer;
15036 SKIP_WHITESPACE ();
15037 expression (&ex_sym);
15039 mips_mark_labels ();
15040 mips_assembling_insn = TRUE;
15043 if (mips_cpreturn_register == -1)
15045 ex_off.X_op = O_constant;
15046 ex_off.X_add_symbol = NULL;
15047 ex_off.X_op_symbol = NULL;
15048 ex_off.X_add_number = mips_cpreturn_offset;
15050 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
15051 BFD_RELOC_LO16, SP);
15054 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
15055 mips_gp_register, 0);
15057 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
15059 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
15060 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
15063 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
15064 mips_gp_register, -1, BFD_RELOC_GPREL16,
15065 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
15067 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
15068 mips_gp_register, reg1);
15074 ex.X_op = O_symbol;
15075 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
15076 ex.X_op_symbol = NULL;
15077 ex.X_add_number = 0;
15079 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15080 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
15082 macro_build_lui (&ex, mips_gp_register);
15083 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
15084 mips_gp_register, BFD_RELOC_LO16);
15089 mips_assembling_insn = FALSE;
15090 demand_empty_rest_of_line ();
15094 s_cplocal (int ignore ATTRIBUTE_UNUSED)
15096 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
15097 .cplocal is ignored. */
15098 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15104 if (mips_opts.mips16)
15106 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
15107 ignore_rest_of_line ();
15111 mips_gp_register = tc_get_register (0);
15112 demand_empty_rest_of_line ();
15115 /* Handle the .cprestore pseudo-op. This stores $gp into a given
15116 offset from $sp. The offset is remembered, and after making a PIC
15117 call $gp is restored from that location. */
15120 s_cprestore (int ignore ATTRIBUTE_UNUSED)
15124 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15125 .cprestore is ignored. */
15126 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
15132 if (mips_opts.mips16)
15134 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
15135 ignore_rest_of_line ();
15139 mips_cprestore_offset = get_absolute_expression ();
15140 mips_cprestore_valid = 1;
15142 ex.X_op = O_constant;
15143 ex.X_add_symbol = NULL;
15144 ex.X_op_symbol = NULL;
15145 ex.X_add_number = mips_cprestore_offset;
15147 mips_mark_labels ();
15148 mips_assembling_insn = TRUE;
15151 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
15152 SP, HAVE_64BIT_ADDRESSES);
15155 mips_assembling_insn = FALSE;
15156 demand_empty_rest_of_line ();
15159 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
15160 was given in the preceding .cpsetup, it results in:
15161 ld $gp, offset($sp)
15163 If a register $reg2 was given there, it results in:
15164 daddu $gp, $reg2, $0 */
15167 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
15171 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
15172 We also need NewABI support. */
15173 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15179 if (mips_opts.mips16)
15181 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
15182 ignore_rest_of_line ();
15186 mips_mark_labels ();
15187 mips_assembling_insn = TRUE;
15190 if (mips_cpreturn_register == -1)
15192 ex.X_op = O_constant;
15193 ex.X_add_symbol = NULL;
15194 ex.X_op_symbol = NULL;
15195 ex.X_add_number = mips_cpreturn_offset;
15197 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
15200 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
15201 mips_cpreturn_register, 0);
15204 mips_assembling_insn = FALSE;
15205 demand_empty_rest_of_line ();
15208 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
15209 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
15210 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
15211 debug information or MIPS16 TLS. */
15214 s_tls_rel_directive (const size_t bytes, const char *dirstr,
15215 bfd_reloc_code_real_type rtype)
15222 if (ex.X_op != O_symbol)
15224 as_bad (_("Unsupported use of %s"), dirstr);
15225 ignore_rest_of_line ();
15228 p = frag_more (bytes);
15229 md_number_to_chars (p, 0, bytes);
15230 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
15231 demand_empty_rest_of_line ();
15232 mips_clear_insn_labels ();
15235 /* Handle .dtprelword. */
15238 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
15240 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
15243 /* Handle .dtpreldword. */
15246 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
15248 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
15251 /* Handle .tprelword. */
15254 s_tprelword (int ignore ATTRIBUTE_UNUSED)
15256 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
15259 /* Handle .tpreldword. */
15262 s_tpreldword (int ignore ATTRIBUTE_UNUSED)
15264 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
15267 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
15268 code. It sets the offset to use in gp_rel relocations. */
15271 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
15273 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
15274 We also need NewABI support. */
15275 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15281 mips_gprel_offset = get_absolute_expression ();
15283 demand_empty_rest_of_line ();
15286 /* Handle the .gpword pseudo-op. This is used when generating PIC
15287 code. It generates a 32 bit GP relative reloc. */
15290 s_gpword (int ignore ATTRIBUTE_UNUSED)
15292 segment_info_type *si;
15293 struct insn_label_list *l;
15297 /* When not generating PIC code, this is treated as .word. */
15298 if (mips_pic != SVR4_PIC)
15304 si = seg_info (now_seg);
15305 l = si->label_list;
15306 mips_emit_delays ();
15308 mips_align (2, 0, l);
15311 mips_clear_insn_labels ();
15313 if (ex.X_op != O_symbol || ex.X_add_number != 0)
15315 as_bad (_("Unsupported use of .gpword"));
15316 ignore_rest_of_line ();
15320 md_number_to_chars (p, 0, 4);
15321 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
15322 BFD_RELOC_GPREL32);
15324 demand_empty_rest_of_line ();
15328 s_gpdword (int ignore ATTRIBUTE_UNUSED)
15330 segment_info_type *si;
15331 struct insn_label_list *l;
15335 /* When not generating PIC code, this is treated as .dword. */
15336 if (mips_pic != SVR4_PIC)
15342 si = seg_info (now_seg);
15343 l = si->label_list;
15344 mips_emit_delays ();
15346 mips_align (3, 0, l);
15349 mips_clear_insn_labels ();
15351 if (ex.X_op != O_symbol || ex.X_add_number != 0)
15353 as_bad (_("Unsupported use of .gpdword"));
15354 ignore_rest_of_line ();
15358 md_number_to_chars (p, 0, 8);
15359 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
15360 BFD_RELOC_GPREL32)->fx_tcbit = 1;
15362 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
15363 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
15364 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
15366 demand_empty_rest_of_line ();
15369 /* Handle the .ehword pseudo-op. This is used when generating unwinding
15370 tables. It generates a R_MIPS_EH reloc. */
15373 s_ehword (int ignore ATTRIBUTE_UNUSED)
15378 mips_emit_delays ();
15381 mips_clear_insn_labels ();
15383 if (ex.X_op != O_symbol || ex.X_add_number != 0)
15385 as_bad (_("Unsupported use of .ehword"));
15386 ignore_rest_of_line ();
15390 md_number_to_chars (p, 0, 4);
15391 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
15392 BFD_RELOC_MIPS_EH);
15394 demand_empty_rest_of_line ();
15397 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
15398 tables in SVR4 PIC code. */
15401 s_cpadd (int ignore ATTRIBUTE_UNUSED)
15405 /* This is ignored when not generating SVR4 PIC code. */
15406 if (mips_pic != SVR4_PIC)
15412 mips_mark_labels ();
15413 mips_assembling_insn = TRUE;
15415 /* Add $gp to the register named as an argument. */
15417 reg = tc_get_register (0);
15418 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
15421 mips_assembling_insn = FALSE;
15422 demand_empty_rest_of_line ();
15425 /* Handle the .insn pseudo-op. This marks instruction labels in
15426 mips16/micromips mode. This permits the linker to handle them specially,
15427 such as generating jalx instructions when needed. We also make
15428 them odd for the duration of the assembly, in order to generate the
15429 right sort of code. We will make them even in the adjust_symtab
15430 routine, while leaving them marked. This is convenient for the
15431 debugger and the disassembler. The linker knows to make them odd
15435 s_insn (int ignore ATTRIBUTE_UNUSED)
15437 mips_mark_labels ();
15439 demand_empty_rest_of_line ();
15442 /* Handle the .nan pseudo-op. */
15445 s_nan (int ignore ATTRIBUTE_UNUSED)
15447 static const char str_legacy[] = "legacy";
15448 static const char str_2008[] = "2008";
15451 for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++);
15453 if (i == sizeof (str_2008) - 1
15454 && memcmp (input_line_pointer, str_2008, i) == 0)
15455 mips_flag_nan2008 = TRUE;
15456 else if (i == sizeof (str_legacy) - 1
15457 && memcmp (input_line_pointer, str_legacy, i) == 0)
15458 mips_flag_nan2008 = FALSE;
15460 as_bad (_("Bad .nan directive"));
15462 input_line_pointer += i;
15463 demand_empty_rest_of_line ();
15466 /* Handle a .stab[snd] directive. Ideally these directives would be
15467 implemented in a transparent way, so that removing them would not
15468 have any effect on the generated instructions. However, s_stab
15469 internally changes the section, so in practice we need to decide
15470 now whether the preceding label marks compressed code. We do not
15471 support changing the compression mode of a label after a .stab*
15472 directive, such as in:
15478 so the current mode wins. */
15481 s_mips_stab (int type)
15483 mips_mark_labels ();
15487 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
15490 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
15497 name = input_line_pointer;
15498 c = get_symbol_end ();
15499 symbolP = symbol_find_or_make (name);
15500 S_SET_WEAK (symbolP);
15501 *input_line_pointer = c;
15503 SKIP_WHITESPACE ();
15505 if (! is_end_of_line[(unsigned char) *input_line_pointer])
15507 if (S_IS_DEFINED (symbolP))
15509 as_bad (_("ignoring attempt to redefine symbol %s"),
15510 S_GET_NAME (symbolP));
15511 ignore_rest_of_line ();
15515 if (*input_line_pointer == ',')
15517 ++input_line_pointer;
15518 SKIP_WHITESPACE ();
15522 if (exp.X_op != O_symbol)
15524 as_bad (_("bad .weakext directive"));
15525 ignore_rest_of_line ();
15528 symbol_set_value_expression (symbolP, &exp);
15531 demand_empty_rest_of_line ();
15534 /* Parse a register string into a number. Called from the ECOFF code
15535 to parse .frame. The argument is non-zero if this is the frame
15536 register, so that we can record it in mips_frame_reg. */
15539 tc_get_register (int frame)
15543 SKIP_WHITESPACE ();
15544 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
15548 mips_frame_reg = reg != 0 ? reg : SP;
15549 mips_frame_reg_valid = 1;
15550 mips_cprestore_valid = 0;
15556 md_section_align (asection *seg, valueT addr)
15558 int align = bfd_get_section_alignment (stdoutput, seg);
15560 /* We don't need to align ELF sections to the full alignment.
15561 However, Irix 5 may prefer that we align them at least to a 16
15562 byte boundary. We don't bother to align the sections if we
15563 are targeted for an embedded system. */
15564 if (strncmp (TARGET_OS, "elf", 3) == 0)
15569 return ((addr + (1 << align) - 1) & (-1 << align));
15572 /* Utility routine, called from above as well. If called while the
15573 input file is still being read, it's only an approximation. (For
15574 example, a symbol may later become defined which appeared to be
15575 undefined earlier.) */
15578 nopic_need_relax (symbolS *sym, int before_relaxing)
15583 if (g_switch_value > 0)
15585 const char *symname;
15588 /* Find out whether this symbol can be referenced off the $gp
15589 register. It can be if it is smaller than the -G size or if
15590 it is in the .sdata or .sbss section. Certain symbols can
15591 not be referenced off the $gp, although it appears as though
15593 symname = S_GET_NAME (sym);
15594 if (symname != (const char *) NULL
15595 && (strcmp (symname, "eprol") == 0
15596 || strcmp (symname, "etext") == 0
15597 || strcmp (symname, "_gp") == 0
15598 || strcmp (symname, "edata") == 0
15599 || strcmp (symname, "_fbss") == 0
15600 || strcmp (symname, "_fdata") == 0
15601 || strcmp (symname, "_ftext") == 0
15602 || strcmp (symname, "end") == 0
15603 || strcmp (symname, "_gp_disp") == 0))
15605 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
15607 #ifndef NO_ECOFF_DEBUGGING
15608 || (symbol_get_obj (sym)->ecoff_extern_size != 0
15609 && (symbol_get_obj (sym)->ecoff_extern_size
15610 <= g_switch_value))
15612 /* We must defer this decision until after the whole
15613 file has been read, since there might be a .extern
15614 after the first use of this symbol. */
15615 || (before_relaxing
15616 #ifndef NO_ECOFF_DEBUGGING
15617 && symbol_get_obj (sym)->ecoff_extern_size == 0
15619 && S_GET_VALUE (sym) == 0)
15620 || (S_GET_VALUE (sym) != 0
15621 && S_GET_VALUE (sym) <= g_switch_value)))
15625 const char *segname;
15627 segname = segment_name (S_GET_SEGMENT (sym));
15628 gas_assert (strcmp (segname, ".lit8") != 0
15629 && strcmp (segname, ".lit4") != 0);
15630 change = (strcmp (segname, ".sdata") != 0
15631 && strcmp (segname, ".sbss") != 0
15632 && strncmp (segname, ".sdata.", 7) != 0
15633 && strncmp (segname, ".sbss.", 6) != 0
15634 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
15635 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
15640 /* We are not optimizing for the $gp register. */
15645 /* Return true if the given symbol should be considered local for SVR4 PIC. */
15648 pic_need_relax (symbolS *sym, asection *segtype)
15652 /* Handle the case of a symbol equated to another symbol. */
15653 while (symbol_equated_reloc_p (sym))
15657 /* It's possible to get a loop here in a badly written program. */
15658 n = symbol_get_value_expression (sym)->X_add_symbol;
15664 if (symbol_section_p (sym))
15667 symsec = S_GET_SEGMENT (sym);
15669 /* This must duplicate the test in adjust_reloc_syms. */
15670 return (!bfd_is_und_section (symsec)
15671 && !bfd_is_abs_section (symsec)
15672 && !bfd_is_com_section (symsec)
15673 && !s_is_linkonce (sym, segtype)
15674 /* A global or weak symbol is treated as external. */
15675 && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym)));
15679 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
15680 extended opcode. SEC is the section the frag is in. */
15683 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
15686 const struct mips_int_operand *operand;
15691 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
15693 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
15696 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
15697 operand = mips16_immed_operand (type, FALSE);
15699 sym_frag = symbol_get_frag (fragp->fr_symbol);
15700 val = S_GET_VALUE (fragp->fr_symbol);
15701 symsec = S_GET_SEGMENT (fragp->fr_symbol);
15703 if (operand->root.type == OP_PCREL)
15705 const struct mips_pcrel_operand *pcrel_op;
15709 /* We won't have the section when we are called from
15710 mips_relax_frag. However, we will always have been called
15711 from md_estimate_size_before_relax first. If this is a
15712 branch to a different section, we mark it as such. If SEC is
15713 NULL, and the frag is not marked, then it must be a branch to
15714 the same section. */
15715 pcrel_op = (const struct mips_pcrel_operand *) operand;
15718 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
15723 /* Must have been called from md_estimate_size_before_relax. */
15726 fragp->fr_subtype =
15727 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
15729 /* FIXME: We should support this, and let the linker
15730 catch branches and loads that are out of range. */
15731 as_bad_where (fragp->fr_file, fragp->fr_line,
15732 _("unsupported PC relative reference to different section"));
15736 if (fragp != sym_frag && sym_frag->fr_address == 0)
15737 /* Assume non-extended on the first relaxation pass.
15738 The address we have calculated will be bogus if this is
15739 a forward branch to another frag, as the forward frag
15740 will have fr_address == 0. */
15744 /* In this case, we know for sure that the symbol fragment is in
15745 the same section. If the relax_marker of the symbol fragment
15746 differs from the relax_marker of this fragment, we have not
15747 yet adjusted the symbol fragment fr_address. We want to add
15748 in STRETCH in order to get a better estimate of the address.
15749 This particularly matters because of the shift bits. */
15751 && sym_frag->relax_marker != fragp->relax_marker)
15755 /* Adjust stretch for any alignment frag. Note that if have
15756 been expanding the earlier code, the symbol may be
15757 defined in what appears to be an earlier frag. FIXME:
15758 This doesn't handle the fr_subtype field, which specifies
15759 a maximum number of bytes to skip when doing an
15761 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
15763 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
15766 stretch = - ((- stretch)
15767 & ~ ((1 << (int) f->fr_offset) - 1));
15769 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
15778 addr = fragp->fr_address + fragp->fr_fix;
15780 /* The base address rules are complicated. The base address of
15781 a branch is the following instruction. The base address of a
15782 PC relative load or add is the instruction itself, but if it
15783 is in a delay slot (in which case it can not be extended) use
15784 the address of the instruction whose delay slot it is in. */
15785 if (pcrel_op->include_isa_bit)
15789 /* If we are currently assuming that this frag should be
15790 extended, then, the current address is two bytes
15792 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
15795 /* Ignore the low bit in the target, since it will be set
15796 for a text label. */
15799 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
15801 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
15804 val -= addr & -(1 << pcrel_op->align_log2);
15806 /* If any of the shifted bits are set, we must use an extended
15807 opcode. If the address depends on the size of this
15808 instruction, this can lead to a loop, so we arrange to always
15809 use an extended opcode. We only check this when we are in
15810 the main relaxation loop, when SEC is NULL. */
15811 if ((val & ((1 << operand->shift) - 1)) != 0 && sec == NULL)
15813 fragp->fr_subtype =
15814 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
15818 /* If we are about to mark a frag as extended because the value
15819 is precisely the next value above maxtiny, then there is a
15820 chance of an infinite loop as in the following code:
15825 In this case when the la is extended, foo is 0x3fc bytes
15826 away, so the la can be shrunk, but then foo is 0x400 away, so
15827 the la must be extended. To avoid this loop, we mark the
15828 frag as extended if it was small, and is about to become
15829 extended with the next value above maxtiny. */
15830 maxtiny = mips_int_operand_max (operand);
15831 if (val == maxtiny + (1 << operand->shift)
15832 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
15835 fragp->fr_subtype =
15836 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
15840 else if (symsec != absolute_section && sec != NULL)
15841 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
15843 return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val);
15846 /* Compute the length of a branch sequence, and adjust the
15847 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
15848 worst-case length is computed, with UPDATE being used to indicate
15849 whether an unconditional (-1), branch-likely (+1) or regular (0)
15850 branch is to be computed. */
15852 relaxed_branch_length (fragS *fragp, asection *sec, int update)
15854 bfd_boolean toofar;
15858 && S_IS_DEFINED (fragp->fr_symbol)
15859 && sec == S_GET_SEGMENT (fragp->fr_symbol))
15864 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
15866 addr = fragp->fr_address + fragp->fr_fix + 4;
15870 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
15873 /* If the symbol is not defined or it's in a different segment,
15874 assume the user knows what's going on and emit a short
15880 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
15882 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
15883 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
15884 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
15885 RELAX_BRANCH_LINK (fragp->fr_subtype),
15891 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
15894 if (mips_pic != NO_PIC)
15896 /* Additional space for PIC loading of target address. */
15898 if (mips_opts.isa == ISA_MIPS1)
15899 /* Additional space for $at-stabilizing nop. */
15903 /* If branch is conditional. */
15904 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
15911 /* Compute the length of a branch sequence, and adjust the
15912 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
15913 worst-case length is computed, with UPDATE being used to indicate
15914 whether an unconditional (-1), or regular (0) branch is to be
15918 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
15920 bfd_boolean toofar;
15924 && S_IS_DEFINED (fragp->fr_symbol)
15925 && sec == S_GET_SEGMENT (fragp->fr_symbol))
15930 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
15931 /* Ignore the low bit in the target, since it will be set
15932 for a text label. */
15933 if ((val & 1) != 0)
15936 addr = fragp->fr_address + fragp->fr_fix + 4;
15940 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
15943 /* If the symbol is not defined or it's in a different segment,
15944 assume the user knows what's going on and emit a short
15950 if (fragp && update
15951 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
15952 fragp->fr_subtype = (toofar
15953 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
15954 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
15959 bfd_boolean compact_known = fragp != NULL;
15960 bfd_boolean compact = FALSE;
15961 bfd_boolean uncond;
15964 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
15966 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
15968 uncond = update < 0;
15970 /* If label is out of range, we turn branch <br>:
15972 <br> label # 4 bytes
15978 nop # 2 bytes if compact && !PIC
15981 if (mips_pic == NO_PIC && (!compact_known || compact))
15984 /* If assembling PIC code, we further turn:
15990 lw/ld at, %got(label)(gp) # 4 bytes
15991 d/addiu at, %lo(label) # 4 bytes
15994 if (mips_pic != NO_PIC)
15997 /* If branch <br> is conditional, we prepend negated branch <brneg>:
15999 <brneg> 0f # 4 bytes
16000 nop # 2 bytes if !compact
16003 length += (compact_known && compact) ? 4 : 6;
16009 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
16010 bit accordingly. */
16013 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
16015 bfd_boolean toofar;
16018 && S_IS_DEFINED (fragp->fr_symbol)
16019 && sec == S_GET_SEGMENT (fragp->fr_symbol))
16025 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
16026 /* Ignore the low bit in the target, since it will be set
16027 for a text label. */
16028 if ((val & 1) != 0)
16031 /* Assume this is a 2-byte branch. */
16032 addr = fragp->fr_address + fragp->fr_fix + 2;
16034 /* We try to avoid the infinite loop by not adding 2 more bytes for
16039 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
16041 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
16042 else if (type == 'E')
16043 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
16048 /* If the symbol is not defined or it's in a different segment,
16049 we emit a normal 32-bit branch. */
16052 if (fragp && update
16053 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
16055 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
16056 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
16064 /* Estimate the size of a frag before relaxing. Unless this is the
16065 mips16, we are not really relaxing here, and the final size is
16066 encoded in the subtype information. For the mips16, we have to
16067 decide whether we are using an extended opcode or not. */
16070 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
16074 if (RELAX_BRANCH_P (fragp->fr_subtype))
16077 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
16079 return fragp->fr_var;
16082 if (RELAX_MIPS16_P (fragp->fr_subtype))
16083 /* We don't want to modify the EXTENDED bit here; it might get us
16084 into infinite loops. We change it only in mips_relax_frag(). */
16085 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
16087 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
16091 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
16092 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
16093 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
16094 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
16095 fragp->fr_var = length;
16100 if (mips_pic == NO_PIC)
16101 change = nopic_need_relax (fragp->fr_symbol, 0);
16102 else if (mips_pic == SVR4_PIC)
16103 change = pic_need_relax (fragp->fr_symbol, segtype);
16104 else if (mips_pic == VXWORKS_PIC)
16105 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
16112 fragp->fr_subtype |= RELAX_USE_SECOND;
16113 return -RELAX_FIRST (fragp->fr_subtype);
16116 return -RELAX_SECOND (fragp->fr_subtype);
16119 /* This is called to see whether a reloc against a defined symbol
16120 should be converted into a reloc against a section. */
16123 mips_fix_adjustable (fixS *fixp)
16125 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
16126 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
16129 if (fixp->fx_addsy == NULL)
16132 /* If symbol SYM is in a mergeable section, relocations of the form
16133 SYM + 0 can usually be made section-relative. The mergeable data
16134 is then identified by the section offset rather than by the symbol.
16136 However, if we're generating REL LO16 relocations, the offset is split
16137 between the LO16 and parterning high part relocation. The linker will
16138 need to recalculate the complete offset in order to correctly identify
16141 The linker has traditionally not looked for the parterning high part
16142 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
16143 placed anywhere. Rather than break backwards compatibility by changing
16144 this, it seems better not to force the issue, and instead keep the
16145 original symbol. This will work with either linker behavior. */
16146 if ((lo16_reloc_p (fixp->fx_r_type)
16147 || reloc_needs_lo_p (fixp->fx_r_type))
16148 && HAVE_IN_PLACE_ADDENDS
16149 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
16152 /* There is no place to store an in-place offset for JALR relocations.
16153 Likewise an in-range offset of limited PC-relative relocations may
16154 overflow the in-place relocatable field if recalculated against the
16155 start address of the symbol's containing section. */
16156 if (HAVE_IN_PLACE_ADDENDS
16157 && (limited_pcrel_reloc_p (fixp->fx_r_type)
16158 || jalr_reloc_p (fixp->fx_r_type)))
16161 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
16162 to a floating-point stub. The same is true for non-R_MIPS16_26
16163 relocations against MIPS16 functions; in this case, the stub becomes
16164 the function's canonical address.
16166 Floating-point stubs are stored in unique .mips16.call.* or
16167 .mips16.fn.* sections. If a stub T for function F is in section S,
16168 the first relocation in section S must be against F; this is how the
16169 linker determines the target function. All relocations that might
16170 resolve to T must also be against F. We therefore have the following
16171 restrictions, which are given in an intentionally-redundant way:
16173 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
16176 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
16177 if that stub might be used.
16179 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
16182 4. We cannot reduce a stub's relocations against MIPS16 symbols if
16183 that stub might be used.
16185 There is a further restriction:
16187 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
16188 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
16189 targets with in-place addends; the relocation field cannot
16190 encode the low bit.
16192 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
16193 against a MIPS16 symbol. We deal with (5) by by not reducing any
16194 such relocations on REL targets.
16196 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
16197 relocation against some symbol R, no relocation against R may be
16198 reduced. (Note that this deals with (2) as well as (1) because
16199 relocations against global symbols will never be reduced on ELF
16200 targets.) This approach is a little simpler than trying to detect
16201 stub sections, and gives the "all or nothing" per-symbol consistency
16202 that we have for MIPS16 symbols. */
16203 if (fixp->fx_subsy == NULL
16204 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
16205 || *symbol_get_tc (fixp->fx_addsy)
16206 || (HAVE_IN_PLACE_ADDENDS
16207 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
16208 && jmp_reloc_p (fixp->fx_r_type))))
16214 /* Translate internal representation of relocation info to BFD target
16218 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
16220 static arelent *retval[4];
16222 bfd_reloc_code_real_type code;
16224 memset (retval, 0, sizeof(retval));
16225 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
16226 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
16227 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
16228 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
16230 if (fixp->fx_pcrel)
16232 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
16233 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
16234 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
16235 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
16236 || fixp->fx_r_type == BFD_RELOC_32_PCREL);
16238 /* At this point, fx_addnumber is "symbol offset - pcrel address".
16239 Relocations want only the symbol offset. */
16240 reloc->addend = fixp->fx_addnumber + reloc->address;
16243 reloc->addend = fixp->fx_addnumber;
16245 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
16246 entry to be used in the relocation's section offset. */
16247 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
16249 reloc->address = reloc->addend;
16253 code = fixp->fx_r_type;
16255 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
16256 if (reloc->howto == NULL)
16258 as_bad_where (fixp->fx_file, fixp->fx_line,
16259 _("Can not represent %s relocation in this object file format"),
16260 bfd_get_reloc_code_name (code));
16267 /* Relax a machine dependent frag. This returns the amount by which
16268 the current size of the frag should change. */
16271 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
16273 if (RELAX_BRANCH_P (fragp->fr_subtype))
16275 offsetT old_var = fragp->fr_var;
16277 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
16279 return fragp->fr_var - old_var;
16282 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
16284 offsetT old_var = fragp->fr_var;
16285 offsetT new_var = 4;
16287 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
16288 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
16289 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
16290 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
16291 fragp->fr_var = new_var;
16293 return new_var - old_var;
16296 if (! RELAX_MIPS16_P (fragp->fr_subtype))
16299 if (mips16_extended_frag (fragp, NULL, stretch))
16301 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
16303 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
16308 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
16310 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
16317 /* Convert a machine dependent frag. */
16320 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
16322 if (RELAX_BRANCH_P (fragp->fr_subtype))
16325 unsigned long insn;
16329 buf = fragp->fr_literal + fragp->fr_fix;
16330 insn = read_insn (buf);
16332 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
16334 /* We generate a fixup instead of applying it right now
16335 because, if there are linker relaxations, we're going to
16336 need the relocations. */
16337 exp.X_op = O_symbol;
16338 exp.X_add_symbol = fragp->fr_symbol;
16339 exp.X_add_number = fragp->fr_offset;
16341 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
16342 BFD_RELOC_16_PCREL_S2);
16343 fixp->fx_file = fragp->fr_file;
16344 fixp->fx_line = fragp->fr_line;
16346 buf = write_insn (buf, insn);
16352 as_warn_where (fragp->fr_file, fragp->fr_line,
16353 _("Relaxed out-of-range branch into a jump"));
16355 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
16358 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
16360 /* Reverse the branch. */
16361 switch ((insn >> 28) & 0xf)
16364 /* bc[0-3][tf]l? instructions can have the condition
16365 reversed by tweaking a single TF bit, and their
16366 opcodes all have 0x4???????. */
16367 gas_assert ((insn & 0xf3e00000) == 0x41000000);
16368 insn ^= 0x00010000;
16372 /* bltz 0x04000000 bgez 0x04010000
16373 bltzal 0x04100000 bgezal 0x04110000 */
16374 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
16375 insn ^= 0x00010000;
16379 /* beq 0x10000000 bne 0x14000000
16380 blez 0x18000000 bgtz 0x1c000000 */
16381 insn ^= 0x04000000;
16389 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
16391 /* Clear the and-link bit. */
16392 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
16394 /* bltzal 0x04100000 bgezal 0x04110000
16395 bltzall 0x04120000 bgezall 0x04130000 */
16396 insn &= ~0x00100000;
16399 /* Branch over the branch (if the branch was likely) or the
16400 full jump (not likely case). Compute the offset from the
16401 current instruction to branch to. */
16402 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
16406 /* How many bytes in instructions we've already emitted? */
16407 i = buf - fragp->fr_literal - fragp->fr_fix;
16408 /* How many bytes in instructions from here to the end? */
16409 i = fragp->fr_var - i;
16411 /* Convert to instruction count. */
16413 /* Branch counts from the next instruction. */
16416 /* Branch over the jump. */
16417 buf = write_insn (buf, insn);
16420 buf = write_insn (buf, 0);
16422 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
16424 /* beql $0, $0, 2f */
16426 /* Compute the PC offset from the current instruction to
16427 the end of the variable frag. */
16428 /* How many bytes in instructions we've already emitted? */
16429 i = buf - fragp->fr_literal - fragp->fr_fix;
16430 /* How many bytes in instructions from here to the end? */
16431 i = fragp->fr_var - i;
16432 /* Convert to instruction count. */
16434 /* Don't decrement i, because we want to branch over the
16438 buf = write_insn (buf, insn);
16439 buf = write_insn (buf, 0);
16443 if (mips_pic == NO_PIC)
16446 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
16447 ? 0x0c000000 : 0x08000000);
16448 exp.X_op = O_symbol;
16449 exp.X_add_symbol = fragp->fr_symbol;
16450 exp.X_add_number = fragp->fr_offset;
16452 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
16453 FALSE, BFD_RELOC_MIPS_JMP);
16454 fixp->fx_file = fragp->fr_file;
16455 fixp->fx_line = fragp->fr_line;
16457 buf = write_insn (buf, insn);
16461 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
16463 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
16464 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
16465 insn |= at << OP_SH_RT;
16466 exp.X_op = O_symbol;
16467 exp.X_add_symbol = fragp->fr_symbol;
16468 exp.X_add_number = fragp->fr_offset;
16470 if (fragp->fr_offset)
16472 exp.X_add_symbol = make_expr_symbol (&exp);
16473 exp.X_add_number = 0;
16476 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
16477 FALSE, BFD_RELOC_MIPS_GOT16);
16478 fixp->fx_file = fragp->fr_file;
16479 fixp->fx_line = fragp->fr_line;
16481 buf = write_insn (buf, insn);
16483 if (mips_opts.isa == ISA_MIPS1)
16485 buf = write_insn (buf, 0);
16487 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
16488 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
16489 insn |= at << OP_SH_RS | at << OP_SH_RT;
16491 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
16492 FALSE, BFD_RELOC_LO16);
16493 fixp->fx_file = fragp->fr_file;
16494 fixp->fx_line = fragp->fr_line;
16496 buf = write_insn (buf, insn);
16499 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
16503 insn |= at << OP_SH_RS;
16505 buf = write_insn (buf, insn);
16509 fragp->fr_fix += fragp->fr_var;
16510 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
16514 /* Relax microMIPS branches. */
16515 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
16517 char *buf = fragp->fr_literal + fragp->fr_fix;
16518 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
16519 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
16520 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
16521 bfd_boolean short_ds;
16522 unsigned long insn;
16526 exp.X_op = O_symbol;
16527 exp.X_add_symbol = fragp->fr_symbol;
16528 exp.X_add_number = fragp->fr_offset;
16530 fragp->fr_fix += fragp->fr_var;
16532 /* Handle 16-bit branches that fit or are forced to fit. */
16533 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
16535 /* We generate a fixup instead of applying it right now,
16536 because if there is linker relaxation, we're going to
16537 need the relocations. */
16539 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
16540 BFD_RELOC_MICROMIPS_10_PCREL_S1);
16541 else if (type == 'E')
16542 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
16543 BFD_RELOC_MICROMIPS_7_PCREL_S1);
16547 fixp->fx_file = fragp->fr_file;
16548 fixp->fx_line = fragp->fr_line;
16550 /* These relocations can have an addend that won't fit in
16552 fixp->fx_no_overflow = 1;
16557 /* Handle 32-bit branches that fit or are forced to fit. */
16558 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
16559 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
16561 /* We generate a fixup instead of applying it right now,
16562 because if there is linker relaxation, we're going to
16563 need the relocations. */
16564 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
16565 BFD_RELOC_MICROMIPS_16_PCREL_S1);
16566 fixp->fx_file = fragp->fr_file;
16567 fixp->fx_line = fragp->fr_line;
16573 /* Relax 16-bit branches to 32-bit branches. */
16576 insn = read_compressed_insn (buf, 2);
16578 if ((insn & 0xfc00) == 0xcc00) /* b16 */
16579 insn = 0x94000000; /* beq */
16580 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
16582 unsigned long regno;
16584 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
16585 regno = micromips_to_32_reg_d_map [regno];
16586 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
16587 insn |= regno << MICROMIPSOP_SH_RS;
16592 /* Nothing else to do, just write it out. */
16593 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
16594 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
16596 buf = write_compressed_insn (buf, insn, 4);
16597 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
16602 insn = read_compressed_insn (buf, 4);
16604 /* Relax 32-bit branches to a sequence of instructions. */
16605 as_warn_where (fragp->fr_file, fragp->fr_line,
16606 _("Relaxed out-of-range branch into a jump"));
16608 /* Set the short-delay-slot bit. */
16609 short_ds = al && (insn & 0x02000000) != 0;
16611 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
16615 /* Reverse the branch. */
16616 if ((insn & 0xfc000000) == 0x94000000 /* beq */
16617 || (insn & 0xfc000000) == 0xb4000000) /* bne */
16618 insn ^= 0x20000000;
16619 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
16620 || (insn & 0xffe00000) == 0x40400000 /* bgez */
16621 || (insn & 0xffe00000) == 0x40800000 /* blez */
16622 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
16623 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
16624 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
16625 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
16626 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
16627 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
16628 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
16629 insn ^= 0x00400000;
16630 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
16631 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
16632 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
16633 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
16634 insn ^= 0x00200000;
16640 /* Clear the and-link and short-delay-slot bits. */
16641 gas_assert ((insn & 0xfda00000) == 0x40200000);
16643 /* bltzal 0x40200000 bgezal 0x40600000 */
16644 /* bltzals 0x42200000 bgezals 0x42600000 */
16645 insn &= ~0x02200000;
16648 /* Make a label at the end for use with the branch. */
16649 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
16650 micromips_label_inc ();
16651 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
16654 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE,
16655 BFD_RELOC_MICROMIPS_16_PCREL_S1);
16656 fixp->fx_file = fragp->fr_file;
16657 fixp->fx_line = fragp->fr_line;
16659 /* Branch over the jump. */
16660 buf = write_compressed_insn (buf, insn, 4);
16663 buf = write_compressed_insn (buf, 0x0c00, 2);
16666 if (mips_pic == NO_PIC)
16668 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
16670 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
16671 insn = al ? jal : 0xd4000000;
16673 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
16674 BFD_RELOC_MICROMIPS_JMP);
16675 fixp->fx_file = fragp->fr_file;
16676 fixp->fx_line = fragp->fr_line;
16678 buf = write_compressed_insn (buf, insn, 4);
16681 buf = write_compressed_insn (buf, 0x0c00, 2);
16685 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
16686 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
16687 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
16689 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
16690 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
16691 insn |= at << MICROMIPSOP_SH_RT;
16693 if (exp.X_add_number)
16695 exp.X_add_symbol = make_expr_symbol (&exp);
16696 exp.X_add_number = 0;
16699 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
16700 BFD_RELOC_MICROMIPS_GOT16);
16701 fixp->fx_file = fragp->fr_file;
16702 fixp->fx_line = fragp->fr_line;
16704 buf = write_compressed_insn (buf, insn, 4);
16706 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
16707 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
16708 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
16710 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
16711 BFD_RELOC_MICROMIPS_LO16);
16712 fixp->fx_file = fragp->fr_file;
16713 fixp->fx_line = fragp->fr_line;
16715 buf = write_compressed_insn (buf, insn, 4);
16717 /* jr/jrc/jalr/jalrs $at */
16718 insn = al ? jalr : jr;
16719 insn |= at << MICROMIPSOP_SH_MJ;
16721 buf = write_compressed_insn (buf, insn, 2);
16724 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
16728 if (RELAX_MIPS16_P (fragp->fr_subtype))
16731 const struct mips_int_operand *operand;
16734 unsigned int user_length, length;
16735 unsigned long insn;
16738 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
16739 operand = mips16_immed_operand (type, FALSE);
16741 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
16742 val = resolve_symbol_value (fragp->fr_symbol);
16743 if (operand->root.type == OP_PCREL)
16745 const struct mips_pcrel_operand *pcrel_op;
16748 pcrel_op = (const struct mips_pcrel_operand *) operand;
16749 addr = fragp->fr_address + fragp->fr_fix;
16751 /* The rules for the base address of a PC relative reloc are
16752 complicated; see mips16_extended_frag. */
16753 if (pcrel_op->include_isa_bit)
16758 /* Ignore the low bit in the target, since it will be
16759 set for a text label. */
16762 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
16764 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
16767 addr &= -(1 << pcrel_op->align_log2);
16770 /* Make sure the section winds up with the alignment we have
16772 if (operand->shift > 0)
16773 record_alignment (asec, operand->shift);
16777 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
16778 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
16779 as_warn_where (fragp->fr_file, fragp->fr_line,
16780 _("extended instruction in delay slot"));
16782 buf = fragp->fr_literal + fragp->fr_fix;
16784 insn = read_compressed_insn (buf, 2);
16786 insn |= MIPS16_EXTEND;
16788 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
16790 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
16795 mips16_immed (fragp->fr_file, fragp->fr_line, type,
16796 BFD_RELOC_UNUSED, val, user_length, &insn);
16798 length = (ext ? 4 : 2);
16799 gas_assert (mips16_opcode_length (insn) == length);
16800 write_compressed_insn (buf, insn, length);
16801 fragp->fr_fix += length;
16805 relax_substateT subtype = fragp->fr_subtype;
16806 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
16807 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
16811 first = RELAX_FIRST (subtype);
16812 second = RELAX_SECOND (subtype);
16813 fixp = (fixS *) fragp->fr_opcode;
16815 /* If the delay slot chosen does not match the size of the instruction,
16816 then emit a warning. */
16817 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
16818 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
16823 s = subtype & (RELAX_DELAY_SLOT_16BIT
16824 | RELAX_DELAY_SLOT_SIZE_FIRST
16825 | RELAX_DELAY_SLOT_SIZE_SECOND);
16826 msg = macro_warning (s);
16828 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
16832 /* Possibly emit a warning if we've chosen the longer option. */
16833 if (use_second == second_longer)
16839 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
16840 msg = macro_warning (s);
16842 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
16846 /* Go through all the fixups for the first sequence. Disable them
16847 (by marking them as done) if we're going to use the second
16848 sequence instead. */
16850 && fixp->fx_frag == fragp
16851 && fixp->fx_where < fragp->fr_fix - second)
16853 if (subtype & RELAX_USE_SECOND)
16855 fixp = fixp->fx_next;
16858 /* Go through the fixups for the second sequence. Disable them if
16859 we're going to use the first sequence, otherwise adjust their
16860 addresses to account for the relaxation. */
16861 while (fixp && fixp->fx_frag == fragp)
16863 if (subtype & RELAX_USE_SECOND)
16864 fixp->fx_where -= first;
16867 fixp = fixp->fx_next;
16870 /* Now modify the frag contents. */
16871 if (subtype & RELAX_USE_SECOND)
16875 start = fragp->fr_literal + fragp->fr_fix - first - second;
16876 memmove (start, start + first, second);
16877 fragp->fr_fix -= first;
16880 fragp->fr_fix -= second;
16884 /* This function is called after the relocs have been generated.
16885 We've been storing mips16 text labels as odd. Here we convert them
16886 back to even for the convenience of the debugger. */
16889 mips_frob_file_after_relocs (void)
16892 unsigned int count, i;
16894 syms = bfd_get_outsymbols (stdoutput);
16895 count = bfd_get_symcount (stdoutput);
16896 for (i = 0; i < count; i++, syms++)
16897 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
16898 && ((*syms)->value & 1) != 0)
16900 (*syms)->value &= ~1;
16901 /* If the symbol has an odd size, it was probably computed
16902 incorrectly, so adjust that as well. */
16903 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
16904 ++elf_symbol (*syms)->internal_elf_sym.st_size;
16908 /* This function is called whenever a label is defined, including fake
16909 labels instantiated off the dot special symbol. It is used when
16910 handling branch delays; if a branch has a label, we assume we cannot
16911 move it. This also bumps the value of the symbol by 1 in compressed
16915 mips_record_label (symbolS *sym)
16917 segment_info_type *si = seg_info (now_seg);
16918 struct insn_label_list *l;
16920 if (free_insn_labels == NULL)
16921 l = (struct insn_label_list *) xmalloc (sizeof *l);
16924 l = free_insn_labels;
16925 free_insn_labels = l->next;
16929 l->next = si->label_list;
16930 si->label_list = l;
16933 /* This function is called as tc_frob_label() whenever a label is defined
16934 and adds a DWARF-2 record we only want for true labels. */
16937 mips_define_label (symbolS *sym)
16939 mips_record_label (sym);
16940 dwarf2_emit_label (sym);
16943 /* This function is called by tc_new_dot_label whenever a new dot symbol
16947 mips_add_dot_label (symbolS *sym)
16949 mips_record_label (sym);
16950 if (mips_assembling_insn && HAVE_CODE_COMPRESSION)
16951 mips_compressed_mark_label (sym);
16954 /* Some special processing for a MIPS ELF file. */
16957 mips_elf_final_processing (void)
16959 /* Write out the register information. */
16960 if (mips_abi != N64_ABI)
16964 s.ri_gprmask = mips_gprmask;
16965 s.ri_cprmask[0] = mips_cprmask[0];
16966 s.ri_cprmask[1] = mips_cprmask[1];
16967 s.ri_cprmask[2] = mips_cprmask[2];
16968 s.ri_cprmask[3] = mips_cprmask[3];
16969 /* The gp_value field is set by the MIPS ELF backend. */
16971 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
16972 ((Elf32_External_RegInfo *)
16973 mips_regmask_frag));
16977 Elf64_Internal_RegInfo s;
16979 s.ri_gprmask = mips_gprmask;
16981 s.ri_cprmask[0] = mips_cprmask[0];
16982 s.ri_cprmask[1] = mips_cprmask[1];
16983 s.ri_cprmask[2] = mips_cprmask[2];
16984 s.ri_cprmask[3] = mips_cprmask[3];
16985 /* The gp_value field is set by the MIPS ELF backend. */
16987 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
16988 ((Elf64_External_RegInfo *)
16989 mips_regmask_frag));
16992 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
16993 sort of BFD interface for this. */
16994 if (mips_any_noreorder)
16995 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
16996 if (mips_pic != NO_PIC)
16998 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
16999 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
17002 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
17004 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
17005 defined at present; this might need to change in future. */
17006 if (file_ase_mips16)
17007 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
17008 if (file_ase_micromips)
17009 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
17010 if (file_ase & ASE_MDMX)
17011 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
17013 /* Set the MIPS ELF ABI flags. */
17014 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
17015 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
17016 else if (mips_abi == O64_ABI)
17017 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
17018 else if (mips_abi == EABI_ABI)
17020 if (!file_mips_gp32)
17021 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
17023 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
17025 else if (mips_abi == N32_ABI)
17026 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
17028 /* Nothing to do for N64_ABI. */
17030 if (mips_32bitmode)
17031 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
17033 if (mips_flag_nan2008)
17034 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008;
17036 #if 0 /* XXX FIXME */
17037 /* 32 bit code with 64 bit FP registers. */
17038 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
17039 elf_elfheader (stdoutput)->e_flags |= ???;
17043 typedef struct proc {
17045 symbolS *func_end_sym;
17046 unsigned long reg_mask;
17047 unsigned long reg_offset;
17048 unsigned long fpreg_mask;
17049 unsigned long fpreg_offset;
17050 unsigned long frame_offset;
17051 unsigned long frame_reg;
17052 unsigned long pc_reg;
17055 static procS cur_proc;
17056 static procS *cur_proc_ptr;
17057 static int numprocs;
17059 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
17060 as "2", and a normal nop as "0". */
17062 #define NOP_OPCODE_MIPS 0
17063 #define NOP_OPCODE_MIPS16 1
17064 #define NOP_OPCODE_MICROMIPS 2
17067 mips_nop_opcode (void)
17069 if (seg_info (now_seg)->tc_segment_info_data.micromips)
17070 return NOP_OPCODE_MICROMIPS;
17071 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
17072 return NOP_OPCODE_MIPS16;
17074 return NOP_OPCODE_MIPS;
17077 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
17078 32-bit microMIPS NOPs here (if applicable). */
17081 mips_handle_align (fragS *fragp)
17085 int bytes, size, excess;
17088 if (fragp->fr_type != rs_align_code)
17091 p = fragp->fr_literal + fragp->fr_fix;
17093 switch (nop_opcode)
17095 case NOP_OPCODE_MICROMIPS:
17096 opcode = micromips_nop32_insn.insn_opcode;
17099 case NOP_OPCODE_MIPS16:
17100 opcode = mips16_nop_insn.insn_opcode;
17103 case NOP_OPCODE_MIPS:
17105 opcode = nop_insn.insn_opcode;
17110 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
17111 excess = bytes % size;
17113 /* Handle the leading part if we're not inserting a whole number of
17114 instructions, and make it the end of the fixed part of the frag.
17115 Try to fit in a short microMIPS NOP if applicable and possible,
17116 and use zeroes otherwise. */
17117 gas_assert (excess < 4);
17118 fragp->fr_fix += excess;
17123 /* Fall through. */
17125 if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32)
17127 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2);
17131 /* Fall through. */
17134 /* Fall through. */
17139 md_number_to_chars (p, opcode, size);
17140 fragp->fr_var = size;
17144 md_obj_begin (void)
17151 /* Check for premature end, nesting errors, etc. */
17153 as_warn (_("missing .end at end of assembly"));
17162 if (*input_line_pointer == '-')
17164 ++input_line_pointer;
17167 if (!ISDIGIT (*input_line_pointer))
17168 as_bad (_("expected simple number"));
17169 if (input_line_pointer[0] == '0')
17171 if (input_line_pointer[1] == 'x')
17173 input_line_pointer += 2;
17174 while (ISXDIGIT (*input_line_pointer))
17177 val |= hex_value (*input_line_pointer++);
17179 return negative ? -val : val;
17183 ++input_line_pointer;
17184 while (ISDIGIT (*input_line_pointer))
17187 val |= *input_line_pointer++ - '0';
17189 return negative ? -val : val;
17192 if (!ISDIGIT (*input_line_pointer))
17194 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
17195 *input_line_pointer, *input_line_pointer);
17196 as_warn (_("invalid number"));
17199 while (ISDIGIT (*input_line_pointer))
17202 val += *input_line_pointer++ - '0';
17204 return negative ? -val : val;
17207 /* The .file directive; just like the usual .file directive, but there
17208 is an initial number which is the ECOFF file index. In the non-ECOFF
17209 case .file implies DWARF-2. */
17212 s_mips_file (int x ATTRIBUTE_UNUSED)
17214 static int first_file_directive = 0;
17216 if (ECOFF_DEBUGGING)
17225 filename = dwarf2_directive_file (0);
17227 /* Versions of GCC up to 3.1 start files with a ".file"
17228 directive even for stabs output. Make sure that this
17229 ".file" is handled. Note that you need a version of GCC
17230 after 3.1 in order to support DWARF-2 on MIPS. */
17231 if (filename != NULL && ! first_file_directive)
17233 (void) new_logical_line (filename, -1);
17234 s_app_file_string (filename, 0);
17236 first_file_directive = 1;
17240 /* The .loc directive, implying DWARF-2. */
17243 s_mips_loc (int x ATTRIBUTE_UNUSED)
17245 if (!ECOFF_DEBUGGING)
17246 dwarf2_directive_loc (0);
17249 /* The .end directive. */
17252 s_mips_end (int x ATTRIBUTE_UNUSED)
17256 /* Following functions need their own .frame and .cprestore directives. */
17257 mips_frame_reg_valid = 0;
17258 mips_cprestore_valid = 0;
17260 if (!is_end_of_line[(unsigned char) *input_line_pointer])
17263 demand_empty_rest_of_line ();
17268 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
17269 as_warn (_(".end not in text section"));
17273 as_warn (_(".end directive without a preceding .ent directive."));
17274 demand_empty_rest_of_line ();
17280 gas_assert (S_GET_NAME (p));
17281 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
17282 as_warn (_(".end symbol does not match .ent symbol."));
17284 if (debug_type == DEBUG_STABS)
17285 stabs_generate_asm_endfunc (S_GET_NAME (p),
17289 as_warn (_(".end directive missing or unknown symbol"));
17291 /* Create an expression to calculate the size of the function. */
17292 if (p && cur_proc_ptr)
17294 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
17295 expressionS *exp = xmalloc (sizeof (expressionS));
17298 exp->X_op = O_subtract;
17299 exp->X_add_symbol = symbol_temp_new_now ();
17300 exp->X_op_symbol = p;
17301 exp->X_add_number = 0;
17303 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
17306 /* Generate a .pdr section. */
17307 if (!ECOFF_DEBUGGING && mips_flag_pdr)
17309 segT saved_seg = now_seg;
17310 subsegT saved_subseg = now_subseg;
17314 #ifdef md_flush_pending_output
17315 md_flush_pending_output ();
17318 gas_assert (pdr_seg);
17319 subseg_set (pdr_seg, 0);
17321 /* Write the symbol. */
17322 exp.X_op = O_symbol;
17323 exp.X_add_symbol = p;
17324 exp.X_add_number = 0;
17325 emit_expr (&exp, 4);
17327 fragp = frag_more (7 * 4);
17329 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
17330 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
17331 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
17332 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
17333 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
17334 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
17335 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
17337 subseg_set (saved_seg, saved_subseg);
17340 cur_proc_ptr = NULL;
17343 /* The .aent and .ent directives. */
17346 s_mips_ent (int aent)
17350 symbolP = get_symbol ();
17351 if (*input_line_pointer == ',')
17352 ++input_line_pointer;
17353 SKIP_WHITESPACE ();
17354 if (ISDIGIT (*input_line_pointer)
17355 || *input_line_pointer == '-')
17358 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
17359 as_warn (_(".ent or .aent not in text section."));
17361 if (!aent && cur_proc_ptr)
17362 as_warn (_("missing .end"));
17366 /* This function needs its own .frame and .cprestore directives. */
17367 mips_frame_reg_valid = 0;
17368 mips_cprestore_valid = 0;
17370 cur_proc_ptr = &cur_proc;
17371 memset (cur_proc_ptr, '\0', sizeof (procS));
17373 cur_proc_ptr->func_sym = symbolP;
17377 if (debug_type == DEBUG_STABS)
17378 stabs_generate_asm_func (S_GET_NAME (symbolP),
17379 S_GET_NAME (symbolP));
17382 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
17384 demand_empty_rest_of_line ();
17387 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
17388 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
17389 s_mips_frame is used so that we can set the PDR information correctly.
17390 We can't use the ecoff routines because they make reference to the ecoff
17391 symbol table (in the mdebug section). */
17394 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
17396 if (ECOFF_DEBUGGING)
17402 if (cur_proc_ptr == (procS *) NULL)
17404 as_warn (_(".frame outside of .ent"));
17405 demand_empty_rest_of_line ();
17409 cur_proc_ptr->frame_reg = tc_get_register (1);
17411 SKIP_WHITESPACE ();
17412 if (*input_line_pointer++ != ','
17413 || get_absolute_expression_and_terminator (&val) != ',')
17415 as_warn (_("Bad .frame directive"));
17416 --input_line_pointer;
17417 demand_empty_rest_of_line ();
17421 cur_proc_ptr->frame_offset = val;
17422 cur_proc_ptr->pc_reg = tc_get_register (0);
17424 demand_empty_rest_of_line ();
17428 /* The .fmask and .mask directives. If the mdebug section is present
17429 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
17430 embedded targets, s_mips_mask is used so that we can set the PDR
17431 information correctly. We can't use the ecoff routines because they
17432 make reference to the ecoff symbol table (in the mdebug section). */
17435 s_mips_mask (int reg_type)
17437 if (ECOFF_DEBUGGING)
17438 s_ignore (reg_type);
17443 if (cur_proc_ptr == (procS *) NULL)
17445 as_warn (_(".mask/.fmask outside of .ent"));
17446 demand_empty_rest_of_line ();
17450 if (get_absolute_expression_and_terminator (&mask) != ',')
17452 as_warn (_("Bad .mask/.fmask directive"));
17453 --input_line_pointer;
17454 demand_empty_rest_of_line ();
17458 off = get_absolute_expression ();
17460 if (reg_type == 'F')
17462 cur_proc_ptr->fpreg_mask = mask;
17463 cur_proc_ptr->fpreg_offset = off;
17467 cur_proc_ptr->reg_mask = mask;
17468 cur_proc_ptr->reg_offset = off;
17471 demand_empty_rest_of_line ();
17475 /* A table describing all the processors gas knows about. Names are
17476 matched in the order listed.
17478 To ease comparison, please keep this table in the same order as
17479 gcc's mips_cpu_info_table[]. */
17480 static const struct mips_cpu_info mips_cpu_info_table[] =
17482 /* Entries for generic ISAs */
17483 { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 },
17484 { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 },
17485 { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 },
17486 { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 },
17487 { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 },
17488 { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 },
17489 { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17490 { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 },
17491 { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 },
17494 { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 },
17495 { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 },
17496 { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 },
17499 { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 },
17502 { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 },
17503 { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 },
17504 { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 },
17505 { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 },
17506 { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 },
17507 { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 },
17508 { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 },
17509 { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 },
17510 { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 },
17511 { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 },
17512 { "orion", 0, 0, ISA_MIPS3, CPU_R4600 },
17513 { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 },
17514 { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 },
17515 /* ST Microelectronics Loongson 2E and 2F cores */
17516 { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E },
17517 { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F },
17520 { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 },
17521 { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 },
17522 { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 },
17523 { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 },
17524 { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 },
17525 { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 },
17526 { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 },
17527 { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 },
17528 { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 },
17529 { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 },
17530 { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 },
17531 { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 },
17532 { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 },
17533 { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 },
17534 { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 },
17537 { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 },
17538 { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 },
17539 { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 },
17540 { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
17542 /* MIPS 32 Release 2 */
17543 { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17544 { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17545 { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17546 { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
17547 { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17548 { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17549 { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
17550 { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
17551 { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
17552 ISA_MIPS32R2, CPU_MIPS32R2 },
17553 { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
17554 ISA_MIPS32R2, CPU_MIPS32R2 },
17555 { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17556 { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17557 { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17558 { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17559 /* Deprecated forms of the above. */
17560 { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17561 { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17562 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
17563 { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17564 { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17565 { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17566 { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17567 /* Deprecated forms of the above. */
17568 { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17569 { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17570 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
17571 { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17572 { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17573 { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17574 { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17575 /* Deprecated forms of the above. */
17576 { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17577 { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17578 /* 34Kn is a 34kc without DSP. */
17579 { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17580 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
17581 { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17582 { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17583 { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17584 { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17585 { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17586 /* Deprecated forms of the above. */
17587 { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17588 { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17589 /* 1004K cores are multiprocessor versions of the 34K. */
17590 { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17591 { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17592 { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17593 { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17596 { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 },
17597 { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 },
17598 { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
17599 { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
17601 /* Broadcom SB-1 CPU core */
17602 { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
17603 /* Broadcom SB-1A CPU core */
17604 { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
17606 { "loongson3a", 0, 0, ISA_MIPS64, CPU_LOONGSON_3A },
17608 /* MIPS 64 Release 2 */
17610 /* Cavium Networks Octeon CPU core */
17611 { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
17612 { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP },
17613 { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 },
17616 { "xlr", 0, 0, ISA_MIPS64, CPU_XLR },
17619 XLP is mostly like XLR, with the prominent exception that it is
17620 MIPS64R2 rather than MIPS64. */
17621 { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
17624 { NULL, 0, 0, 0, 0 }
17628 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
17629 with a final "000" replaced by "k". Ignore case.
17631 Note: this function is shared between GCC and GAS. */
17634 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
17636 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
17637 given++, canonical++;
17639 return ((*given == 0 && *canonical == 0)
17640 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
17644 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
17645 CPU name. We've traditionally allowed a lot of variation here.
17647 Note: this function is shared between GCC and GAS. */
17650 mips_matching_cpu_name_p (const char *canonical, const char *given)
17652 /* First see if the name matches exactly, or with a final "000"
17653 turned into "k". */
17654 if (mips_strict_matching_cpu_name_p (canonical, given))
17657 /* If not, try comparing based on numerical designation alone.
17658 See if GIVEN is an unadorned number, or 'r' followed by a number. */
17659 if (TOLOWER (*given) == 'r')
17661 if (!ISDIGIT (*given))
17664 /* Skip over some well-known prefixes in the canonical name,
17665 hoping to find a number there too. */
17666 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
17668 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
17670 else if (TOLOWER (canonical[0]) == 'r')
17673 return mips_strict_matching_cpu_name_p (canonical, given);
17677 /* Parse an option that takes the name of a processor as its argument.
17678 OPTION is the name of the option and CPU_STRING is the argument.
17679 Return the corresponding processor enumeration if the CPU_STRING is
17680 recognized, otherwise report an error and return null.
17682 A similar function exists in GCC. */
17684 static const struct mips_cpu_info *
17685 mips_parse_cpu (const char *option, const char *cpu_string)
17687 const struct mips_cpu_info *p;
17689 /* 'from-abi' selects the most compatible architecture for the given
17690 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
17691 EABIs, we have to decide whether we're using the 32-bit or 64-bit
17692 version. Look first at the -mgp options, if given, otherwise base
17693 the choice on MIPS_DEFAULT_64BIT.
17695 Treat NO_ABI like the EABIs. One reason to do this is that the
17696 plain 'mips' and 'mips64' configs have 'from-abi' as their default
17697 architecture. This code picks MIPS I for 'mips' and MIPS III for
17698 'mips64', just as we did in the days before 'from-abi'. */
17699 if (strcasecmp (cpu_string, "from-abi") == 0)
17701 if (ABI_NEEDS_32BIT_REGS (mips_abi))
17702 return mips_cpu_info_from_isa (ISA_MIPS1);
17704 if (ABI_NEEDS_64BIT_REGS (mips_abi))
17705 return mips_cpu_info_from_isa (ISA_MIPS3);
17707 if (file_mips_gp32 >= 0)
17708 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
17710 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
17715 /* 'default' has traditionally been a no-op. Probably not very useful. */
17716 if (strcasecmp (cpu_string, "default") == 0)
17719 for (p = mips_cpu_info_table; p->name != 0; p++)
17720 if (mips_matching_cpu_name_p (p->name, cpu_string))
17723 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
17727 /* Return the canonical processor information for ISA (a member of the
17728 ISA_MIPS* enumeration). */
17730 static const struct mips_cpu_info *
17731 mips_cpu_info_from_isa (int isa)
17735 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
17736 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
17737 && isa == mips_cpu_info_table[i].isa)
17738 return (&mips_cpu_info_table[i]);
17743 static const struct mips_cpu_info *
17744 mips_cpu_info_from_arch (int arch)
17748 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
17749 if (arch == mips_cpu_info_table[i].cpu)
17750 return (&mips_cpu_info_table[i]);
17756 show (FILE *stream, const char *string, int *col_p, int *first_p)
17760 fprintf (stream, "%24s", "");
17765 fprintf (stream, ", ");
17769 if (*col_p + strlen (string) > 72)
17771 fprintf (stream, "\n%24s", "");
17775 fprintf (stream, "%s", string);
17776 *col_p += strlen (string);
17782 md_show_usage (FILE *stream)
17787 fprintf (stream, _("\
17789 -EB generate big endian output\n\
17790 -EL generate little endian output\n\
17791 -g, -g2 do not remove unneeded NOPs or swap branches\n\
17792 -G NUM allow referencing objects up to NUM bytes\n\
17793 implicitly with the gp register [default 8]\n"));
17794 fprintf (stream, _("\
17795 -mips1 generate MIPS ISA I instructions\n\
17796 -mips2 generate MIPS ISA II instructions\n\
17797 -mips3 generate MIPS ISA III instructions\n\
17798 -mips4 generate MIPS ISA IV instructions\n\
17799 -mips5 generate MIPS ISA V instructions\n\
17800 -mips32 generate MIPS32 ISA instructions\n\
17801 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
17802 -mips64 generate MIPS64 ISA instructions\n\
17803 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
17804 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
17808 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
17809 show (stream, mips_cpu_info_table[i].name, &column, &first);
17810 show (stream, "from-abi", &column, &first);
17811 fputc ('\n', stream);
17813 fprintf (stream, _("\
17814 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
17815 -no-mCPU don't generate code specific to CPU.\n\
17816 For -mCPU and -no-mCPU, CPU must be one of:\n"));
17820 show (stream, "3900", &column, &first);
17821 show (stream, "4010", &column, &first);
17822 show (stream, "4100", &column, &first);
17823 show (stream, "4650", &column, &first);
17824 fputc ('\n', stream);
17826 fprintf (stream, _("\
17827 -mips16 generate mips16 instructions\n\
17828 -no-mips16 do not generate mips16 instructions\n"));
17829 fprintf (stream, _("\
17830 -mmicromips generate microMIPS instructions\n\
17831 -mno-micromips do not generate microMIPS instructions\n"));
17832 fprintf (stream, _("\
17833 -msmartmips generate smartmips instructions\n\
17834 -mno-smartmips do not generate smartmips instructions\n"));
17835 fprintf (stream, _("\
17836 -mdsp generate DSP instructions\n\
17837 -mno-dsp do not generate DSP instructions\n"));
17838 fprintf (stream, _("\
17839 -mdspr2 generate DSP R2 instructions\n\
17840 -mno-dspr2 do not generate DSP R2 instructions\n"));
17841 fprintf (stream, _("\
17842 -mmt generate MT instructions\n\
17843 -mno-mt do not generate MT instructions\n"));
17844 fprintf (stream, _("\
17845 -mmcu generate MCU instructions\n\
17846 -mno-mcu do not generate MCU instructions\n"));
17847 fprintf (stream, _("\
17848 -mvirt generate Virtualization instructions\n\
17849 -mno-virt do not generate Virtualization instructions\n"));
17850 fprintf (stream, _("\
17851 -minsn32 only generate 32-bit microMIPS instructions\n\
17852 -mno-insn32 generate all microMIPS instructions\n"));
17853 fprintf (stream, _("\
17854 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
17855 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
17856 -mfix-vr4120 work around certain VR4120 errata\n\
17857 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
17858 -mfix-24k insert a nop after ERET and DERET instructions\n\
17859 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
17860 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
17861 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
17862 -msym32 assume all symbols have 32-bit values\n\
17863 -O0 remove unneeded NOPs, do not swap branches\n\
17864 -O remove unneeded NOPs and swap branches\n\
17865 --trap, --no-break trap exception on div by 0 and mult overflow\n\
17866 --break, --no-trap break exception on div by 0 and mult overflow\n"));
17867 fprintf (stream, _("\
17868 -mhard-float allow floating-point instructions\n\
17869 -msoft-float do not allow floating-point instructions\n\
17870 -msingle-float only allow 32-bit floating-point operations\n\
17871 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
17872 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
17873 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
17874 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
17878 show (stream, "legacy", &column, &first);
17879 show (stream, "2008", &column, &first);
17881 fputc ('\n', stream);
17883 fprintf (stream, _("\
17884 -KPIC, -call_shared generate SVR4 position independent code\n\
17885 -call_nonpic generate non-PIC code that can operate with DSOs\n\
17886 -mvxworks-pic generate VxWorks position independent code\n\
17887 -non_shared do not generate code that can operate with DSOs\n\
17888 -xgot assume a 32 bit GOT\n\
17889 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
17890 -mshared, -mno-shared disable/enable .cpload optimization for\n\
17891 position dependent (non shared) code\n\
17892 -mabi=ABI create ABI conformant object file for:\n"));
17896 show (stream, "32", &column, &first);
17897 show (stream, "o64", &column, &first);
17898 show (stream, "n32", &column, &first);
17899 show (stream, "64", &column, &first);
17900 show (stream, "eabi", &column, &first);
17902 fputc ('\n', stream);
17904 fprintf (stream, _("\
17905 -32 create o32 ABI object file (default)\n\
17906 -n32 create n32 ABI object file\n\
17907 -64 create 64 ABI object file\n"));
17912 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
17914 if (HAVE_64BIT_SYMBOLS)
17915 return dwarf2_format_64bit_irix;
17917 return dwarf2_format_32bit;
17922 mips_dwarf2_addr_size (void)
17924 if (HAVE_64BIT_OBJECTS)
17930 /* Standard calling conventions leave the CFA at SP on entry. */
17932 mips_cfi_frame_initial_instructions (void)
17934 cfi_add_CFA_def_cfa_register (SP);
17938 tc_mips_regname_to_dw2regnum (char *regname)
17940 unsigned int regnum = -1;
17943 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))