1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2016 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1];
37 typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define streq(a, b) (strcmp (a, b) == 0)
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug = -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr = FALSE;
86 int mips_flag_pdr = TRUE;
91 static char *mips_regmask_frag;
92 static char *mips_flags_frag;
99 #define PIC_CALL_REG 25
107 #define ILLEGAL_REG (32)
109 #define AT mips_opts.at
111 extern int target_big_endian;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME ".rodata"
116 /* Ways in which an instruction can be "appended" to the output. */
118 /* Just add it normally. */
121 /* Add it normally and then add a nop. */
124 /* Turn an instruction with a delay slot into a "compact" version. */
127 /* Insert the instruction before the last one. */
131 /* Information about an instruction, including its format, operands
135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
136 const struct mips_opcode *insn_mo;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. If we have
140 decided to use an extended MIPS16 instruction, this includes the
142 unsigned long insn_opcode;
144 /* The frag that contains the instruction. */
147 /* The offset into FRAG of the first instruction byte. */
150 /* The relocs associated with the instruction, if any. */
153 /* True if this entry cannot be moved from its current position. */
154 unsigned int fixed_p : 1;
156 /* True if this instruction occurred in a .set noreorder block. */
157 unsigned int noreorder_p : 1;
159 /* True for mips16 instructions that jump to an absolute address. */
160 unsigned int mips16_absolute_jump_p : 1;
162 /* True if this instruction is complete. */
163 unsigned int complete_p : 1;
165 /* True if this instruction is cleared from history by unconditional
167 unsigned int cleared_p : 1;
170 /* The ABI to use. */
181 /* MIPS ABI we are using for this output file. */
182 static enum mips_abi_level mips_abi = NO_ABI;
184 /* Whether or not we have code that can call pic code. */
185 int mips_abicalls = FALSE;
187 /* Whether or not we have code which can be put into a shared
189 static bfd_boolean mips_in_shared = TRUE;
191 /* This is the set of options which may be modified by the .set
192 pseudo-op. We use a struct so that .set push and .set pop are more
195 struct mips_set_options
197 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
198 if it has not been initialized. Changed by `.set mipsN', and the
199 -mipsN command line option, and the default CPU. */
201 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
202 <asename>', by command line options, and based on the default
205 /* Whether we are assembling for the mips16 processor. 0 if we are
206 not, 1 if we are, and -1 if the value has not been initialized.
207 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
208 -nomips16 command line options, and the default CPU. */
210 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
211 1 if we are, and -1 if the value has not been initialized. Changed
212 by `.set micromips' and `.set nomicromips', and the -mmicromips
213 and -mno-micromips command line options, and the default CPU. */
215 /* Non-zero if we should not reorder instructions. Changed by `.set
216 reorder' and `.set noreorder'. */
218 /* Non-zero if we should not permit the register designated "assembler
219 temporary" to be used in instructions. The value is the register
220 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
221 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
223 /* Non-zero if we should warn when a macro instruction expands into
224 more than one machine instruction. Changed by `.set nomacro' and
226 int warn_about_macros;
227 /* Non-zero if we should not move instructions. Changed by `.set
228 move', `.set volatile', `.set nomove', and `.set novolatile'. */
230 /* Non-zero if we should not optimize branches by moving the target
231 of the branch into the delay slot. Actually, we don't perform
232 this optimization anyhow. Changed by `.set bopt' and `.set
235 /* Non-zero if we should not autoextend mips16 instructions.
236 Changed by `.set autoextend' and `.set noautoextend'. */
238 /* True if we should only emit 32-bit microMIPS instructions.
239 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
240 and -mno-insn32 command line options. */
242 /* Restrict general purpose registers and floating point registers
243 to 32 bit. This is initially determined when -mgp32 or -mfp32
244 is passed but can changed if the assembler code uses .set mipsN. */
247 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
248 command line option, and the default CPU. */
250 /* True if ".set sym32" is in effect. */
252 /* True if floating-point operations are not allowed. Changed by .set
253 softfloat or .set hardfloat, by command line options -msoft-float or
254 -mhard-float. The default is false. */
255 bfd_boolean soft_float;
257 /* True if only single-precision floating-point operations are allowed.
258 Changed by .set singlefloat or .set doublefloat, command-line options
259 -msingle-float or -mdouble-float. The default is false. */
260 bfd_boolean single_float;
262 /* 1 if single-precision operations on odd-numbered registers are
267 /* Specifies whether module level options have been checked yet. */
268 static bfd_boolean file_mips_opts_checked = FALSE;
270 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
271 value has not been initialized. Changed by `.nan legacy' and
272 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
273 options, and the default CPU. */
274 static int mips_nan2008 = -1;
276 /* This is the struct we use to hold the module level set of options.
277 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
278 fp fields to -1 to indicate that they have not been initialized. */
280 static struct mips_set_options file_mips_opts =
282 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
283 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
284 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
285 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
286 /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1
289 /* This is similar to file_mips_opts, but for the current set of options. */
291 static struct mips_set_options mips_opts =
293 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
294 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
295 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
296 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
297 /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1
300 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
301 static unsigned int file_ase_explicit;
303 /* These variables are filled in with the masks of registers used.
304 The object format code reads them and puts them in the appropriate
306 unsigned long mips_gprmask;
307 unsigned long mips_cprmask[4];
309 /* True if any MIPS16 code was produced. */
310 static int file_ase_mips16;
312 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
313 || mips_opts.isa == ISA_MIPS32R2 \
314 || mips_opts.isa == ISA_MIPS32R3 \
315 || mips_opts.isa == ISA_MIPS32R5 \
316 || mips_opts.isa == ISA_MIPS64 \
317 || mips_opts.isa == ISA_MIPS64R2 \
318 || mips_opts.isa == ISA_MIPS64R3 \
319 || mips_opts.isa == ISA_MIPS64R5)
321 /* True if any microMIPS code was produced. */
322 static int file_ase_micromips;
324 /* True if we want to create R_MIPS_JALR for jalr $25. */
326 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
328 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
329 because there's no place for any addend, the only acceptable
330 expression is a bare symbol. */
331 #define MIPS_JALR_HINT_P(EXPR) \
332 (!HAVE_IN_PLACE_ADDENDS \
333 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
336 /* The argument of the -march= flag. The architecture we are assembling. */
337 static const char *mips_arch_string;
339 /* The argument of the -mtune= flag. The architecture for which we
341 static int mips_tune = CPU_UNKNOWN;
342 static const char *mips_tune_string;
344 /* True when generating 32-bit code for a 64-bit processor. */
345 static int mips_32bitmode = 0;
347 /* True if the given ABI requires 32-bit registers. */
348 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
350 /* Likewise 64-bit registers. */
351 #define ABI_NEEDS_64BIT_REGS(ABI) \
353 || (ABI) == N64_ABI \
356 #define ISA_IS_R6(ISA) \
357 ((ISA) == ISA_MIPS32R6 \
358 || (ISA) == ISA_MIPS64R6)
360 /* Return true if ISA supports 64 bit wide gp registers. */
361 #define ISA_HAS_64BIT_REGS(ISA) \
362 ((ISA) == ISA_MIPS3 \
363 || (ISA) == ISA_MIPS4 \
364 || (ISA) == ISA_MIPS5 \
365 || (ISA) == ISA_MIPS64 \
366 || (ISA) == ISA_MIPS64R2 \
367 || (ISA) == ISA_MIPS64R3 \
368 || (ISA) == ISA_MIPS64R5 \
369 || (ISA) == ISA_MIPS64R6)
371 /* Return true if ISA supports 64 bit wide float registers. */
372 #define ISA_HAS_64BIT_FPRS(ISA) \
373 ((ISA) == ISA_MIPS3 \
374 || (ISA) == ISA_MIPS4 \
375 || (ISA) == ISA_MIPS5 \
376 || (ISA) == ISA_MIPS32R2 \
377 || (ISA) == ISA_MIPS32R3 \
378 || (ISA) == ISA_MIPS32R5 \
379 || (ISA) == ISA_MIPS32R6 \
380 || (ISA) == ISA_MIPS64 \
381 || (ISA) == ISA_MIPS64R2 \
382 || (ISA) == ISA_MIPS64R3 \
383 || (ISA) == ISA_MIPS64R5 \
384 || (ISA) == ISA_MIPS64R6)
386 /* Return true if ISA supports 64-bit right rotate (dror et al.)
388 #define ISA_HAS_DROR(ISA) \
389 ((ISA) == ISA_MIPS64R2 \
390 || (ISA) == ISA_MIPS64R3 \
391 || (ISA) == ISA_MIPS64R5 \
392 || (ISA) == ISA_MIPS64R6 \
393 || (mips_opts.micromips \
394 && ISA_HAS_64BIT_REGS (ISA)) \
397 /* Return true if ISA supports 32-bit right rotate (ror et al.)
399 #define ISA_HAS_ROR(ISA) \
400 ((ISA) == ISA_MIPS32R2 \
401 || (ISA) == ISA_MIPS32R3 \
402 || (ISA) == ISA_MIPS32R5 \
403 || (ISA) == ISA_MIPS32R6 \
404 || (ISA) == ISA_MIPS64R2 \
405 || (ISA) == ISA_MIPS64R3 \
406 || (ISA) == ISA_MIPS64R5 \
407 || (ISA) == ISA_MIPS64R6 \
408 || (mips_opts.ase & ASE_SMARTMIPS) \
409 || mips_opts.micromips \
412 /* Return true if ISA supports single-precision floats in odd registers. */
413 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
414 (((ISA) == ISA_MIPS32 \
415 || (ISA) == ISA_MIPS32R2 \
416 || (ISA) == ISA_MIPS32R3 \
417 || (ISA) == ISA_MIPS32R5 \
418 || (ISA) == ISA_MIPS32R6 \
419 || (ISA) == ISA_MIPS64 \
420 || (ISA) == ISA_MIPS64R2 \
421 || (ISA) == ISA_MIPS64R3 \
422 || (ISA) == ISA_MIPS64R5 \
423 || (ISA) == ISA_MIPS64R6 \
424 || (CPU) == CPU_R5900) \
425 && (CPU) != CPU_LOONGSON_3A)
427 /* Return true if ISA supports move to/from high part of a 64-bit
428 floating-point register. */
429 #define ISA_HAS_MXHC1(ISA) \
430 ((ISA) == ISA_MIPS32R2 \
431 || (ISA) == ISA_MIPS32R3 \
432 || (ISA) == ISA_MIPS32R5 \
433 || (ISA) == ISA_MIPS32R6 \
434 || (ISA) == ISA_MIPS64R2 \
435 || (ISA) == ISA_MIPS64R3 \
436 || (ISA) == ISA_MIPS64R5 \
437 || (ISA) == ISA_MIPS64R6)
439 /* Return true if ISA supports legacy NAN. */
440 #define ISA_HAS_LEGACY_NAN(ISA) \
441 ((ISA) == ISA_MIPS1 \
442 || (ISA) == ISA_MIPS2 \
443 || (ISA) == ISA_MIPS3 \
444 || (ISA) == ISA_MIPS4 \
445 || (ISA) == ISA_MIPS5 \
446 || (ISA) == ISA_MIPS32 \
447 || (ISA) == ISA_MIPS32R2 \
448 || (ISA) == ISA_MIPS32R3 \
449 || (ISA) == ISA_MIPS32R5 \
450 || (ISA) == ISA_MIPS64 \
451 || (ISA) == ISA_MIPS64R2 \
452 || (ISA) == ISA_MIPS64R3 \
453 || (ISA) == ISA_MIPS64R5)
456 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
461 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
465 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
467 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
469 /* True if relocations are stored in-place. */
470 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
472 /* The ABI-derived address size. */
473 #define HAVE_64BIT_ADDRESSES \
474 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
475 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
477 /* The size of symbolic constants (i.e., expressions of the form
478 "SYMBOL" or "SYMBOL + OFFSET"). */
479 #define HAVE_32BIT_SYMBOLS \
480 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
481 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
483 /* Addresses are loaded in different ways, depending on the address size
484 in use. The n32 ABI Documentation also mandates the use of additions
485 with overflow checking, but existing implementations don't follow it. */
486 #define ADDRESS_ADD_INSN \
487 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
489 #define ADDRESS_ADDI_INSN \
490 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
492 #define ADDRESS_LOAD_INSN \
493 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
495 #define ADDRESS_STORE_INSN \
496 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
498 /* Return true if the given CPU supports the MIPS16 ASE. */
499 #define CPU_HAS_MIPS16(cpu) \
500 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
501 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
503 /* Return true if the given CPU supports the microMIPS ASE. */
504 #define CPU_HAS_MICROMIPS(cpu) 0
506 /* True if CPU has a dror instruction. */
507 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
509 /* True if CPU has a ror instruction. */
510 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
512 /* True if CPU is in the Octeon family */
513 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
514 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
516 /* True if CPU has seq/sne and seqi/snei instructions. */
517 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
519 /* True, if CPU has support for ldc1 and sdc1. */
520 #define CPU_HAS_LDC1_SDC1(CPU) \
521 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
523 /* True if mflo and mfhi can be immediately followed by instructions
524 which write to the HI and LO registers.
526 According to MIPS specifications, MIPS ISAs I, II, and III need
527 (at least) two instructions between the reads of HI/LO and
528 instructions which write them, and later ISAs do not. Contradicting
529 the MIPS specifications, some MIPS IV processor user manuals (e.g.
530 the UM for the NEC Vr5000) document needing the instructions between
531 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
532 MIPS64 and later ISAs to have the interlocks, plus any specific
533 earlier-ISA CPUs for which CPU documentation declares that the
534 instructions are really interlocked. */
535 #define hilo_interlocks \
536 (mips_opts.isa == ISA_MIPS32 \
537 || mips_opts.isa == ISA_MIPS32R2 \
538 || mips_opts.isa == ISA_MIPS32R3 \
539 || mips_opts.isa == ISA_MIPS32R5 \
540 || mips_opts.isa == ISA_MIPS32R6 \
541 || mips_opts.isa == ISA_MIPS64 \
542 || mips_opts.isa == ISA_MIPS64R2 \
543 || mips_opts.isa == ISA_MIPS64R3 \
544 || mips_opts.isa == ISA_MIPS64R5 \
545 || mips_opts.isa == ISA_MIPS64R6 \
546 || mips_opts.arch == CPU_R4010 \
547 || mips_opts.arch == CPU_R5900 \
548 || mips_opts.arch == CPU_R10000 \
549 || mips_opts.arch == CPU_R12000 \
550 || mips_opts.arch == CPU_R14000 \
551 || mips_opts.arch == CPU_R16000 \
552 || mips_opts.arch == CPU_RM7000 \
553 || mips_opts.arch == CPU_VR5500 \
554 || mips_opts.micromips \
557 /* Whether the processor uses hardware interlocks to protect reads
558 from the GPRs after they are loaded from memory, and thus does not
559 require nops to be inserted. This applies to instructions marked
560 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
561 level I and microMIPS mode instructions are always interlocked. */
562 #define gpr_interlocks \
563 (mips_opts.isa != ISA_MIPS1 \
564 || mips_opts.arch == CPU_R3900 \
565 || mips_opts.arch == CPU_R5900 \
566 || mips_opts.micromips \
569 /* Whether the processor uses hardware interlocks to avoid delays
570 required by coprocessor instructions, and thus does not require
571 nops to be inserted. This applies to instructions marked
572 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
573 instructions marked INSN_WRITE_COND_CODE and ones marked
574 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
575 levels I, II, and III and microMIPS mode instructions are always
577 /* Itbl support may require additional care here. */
578 #define cop_interlocks \
579 ((mips_opts.isa != ISA_MIPS1 \
580 && mips_opts.isa != ISA_MIPS2 \
581 && mips_opts.isa != ISA_MIPS3) \
582 || mips_opts.arch == CPU_R4300 \
583 || mips_opts.micromips \
586 /* Whether the processor uses hardware interlocks to protect reads
587 from coprocessor registers after they are loaded from memory, and
588 thus does not require nops to be inserted. This applies to
589 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
590 requires at MIPS ISA level I and microMIPS mode instructions are
591 always interlocked. */
592 #define cop_mem_interlocks \
593 (mips_opts.isa != ISA_MIPS1 \
594 || mips_opts.micromips \
597 /* Is this a mfhi or mflo instruction? */
598 #define MF_HILO_INSN(PINFO) \
599 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
601 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
602 has been selected. This implies, in particular, that addresses of text
603 labels have their LSB set. */
604 #define HAVE_CODE_COMPRESSION \
605 ((mips_opts.mips16 | mips_opts.micromips) != 0)
607 /* The minimum and maximum signed values that can be stored in a GPR. */
608 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
609 #define GPR_SMIN (-GPR_SMAX - 1)
611 /* MIPS PIC level. */
613 enum mips_pic_level mips_pic;
615 /* 1 if we should generate 32 bit offsets from the $gp register in
616 SVR4_PIC mode. Currently has no meaning in other modes. */
617 static int mips_big_got = 0;
619 /* 1 if trap instructions should used for overflow rather than break
621 static int mips_trap = 0;
623 /* 1 if double width floating point constants should not be constructed
624 by assembling two single width halves into two single width floating
625 point registers which just happen to alias the double width destination
626 register. On some architectures this aliasing can be disabled by a bit
627 in the status register, and the setting of this bit cannot be determined
628 automatically at assemble time. */
629 static int mips_disable_float_construction;
631 /* Non-zero if any .set noreorder directives were used. */
633 static int mips_any_noreorder;
635 /* Non-zero if nops should be inserted when the register referenced in
636 an mfhi/mflo instruction is read in the next two instructions. */
637 static int mips_7000_hilo_fix;
639 /* The size of objects in the small data section. */
640 static unsigned int g_switch_value = 8;
641 /* Whether the -G option was used. */
642 static int g_switch_seen = 0;
647 /* If we can determine in advance that GP optimization won't be
648 possible, we can skip the relaxation stuff that tries to produce
649 GP-relative references. This makes delay slot optimization work
652 This function can only provide a guess, but it seems to work for
653 gcc output. It needs to guess right for gcc, otherwise gcc
654 will put what it thinks is a GP-relative instruction in a branch
657 I don't know if a fix is needed for the SVR4_PIC mode. I've only
658 fixed it for the non-PIC mode. KR 95/04/07 */
659 static int nopic_need_relax (symbolS *, int);
661 /* handle of the OPCODE hash table */
662 static struct hash_control *op_hash = NULL;
664 /* The opcode hash table we use for the mips16. */
665 static struct hash_control *mips16_op_hash = NULL;
667 /* The opcode hash table we use for the microMIPS ASE. */
668 static struct hash_control *micromips_op_hash = NULL;
670 /* This array holds the chars that always start a comment. If the
671 pre-processor is disabled, these aren't very useful */
672 const char comment_chars[] = "#";
674 /* This array holds the chars that only start a comment at the beginning of
675 a line. If the line seems to have the form '# 123 filename'
676 .line and .file directives will appear in the pre-processed output */
677 /* Note that input_file.c hand checks for '#' at the beginning of the
678 first line of the input file. This is because the compiler outputs
679 #NO_APP at the beginning of its output. */
680 /* Also note that C style comments are always supported. */
681 const char line_comment_chars[] = "#";
683 /* This array holds machine specific line separator characters. */
684 const char line_separator_chars[] = ";";
686 /* Chars that can be used to separate mant from exp in floating point nums */
687 const char EXP_CHARS[] = "eE";
689 /* Chars that mean this number is a floating point constant */
692 const char FLT_CHARS[] = "rRsSfFdDxXpP";
694 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
695 changed in read.c . Ideally it shouldn't have to know about it at all,
696 but nothing is ideal around here.
699 /* Types of printf format used for instruction-related error messages.
700 "I" means int ("%d") and "S" means string ("%s"). */
701 enum mips_insn_error_format {
707 /* Information about an error that was found while assembling the current
709 struct mips_insn_error {
710 /* We sometimes need to match an instruction against more than one
711 opcode table entry. Errors found during this matching are reported
712 against a particular syntactic argument rather than against the
713 instruction as a whole. We grade these messages so that errors
714 against argument N have a greater priority than an error against
715 any argument < N, since the former implies that arguments up to N
716 were acceptable and that the opcode entry was therefore a closer match.
717 If several matches report an error against the same argument,
718 we only use that error if it is the same in all cases.
720 min_argnum is the minimum argument number for which an error message
721 should be accepted. It is 0 if MSG is against the instruction as
725 /* The printf()-style message, including its format and arguments. */
726 enum mips_insn_error_format format;
734 /* The error that should be reported for the current instruction. */
735 static struct mips_insn_error insn_error;
737 static int auto_align = 1;
739 /* When outputting SVR4 PIC code, the assembler needs to know the
740 offset in the stack frame from which to restore the $gp register.
741 This is set by the .cprestore pseudo-op, and saved in this
743 static offsetT mips_cprestore_offset = -1;
745 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
746 more optimizations, it can use a register value instead of a memory-saved
747 offset and even an other register than $gp as global pointer. */
748 static offsetT mips_cpreturn_offset = -1;
749 static int mips_cpreturn_register = -1;
750 static int mips_gp_register = GP;
751 static int mips_gprel_offset = 0;
753 /* Whether mips_cprestore_offset has been set in the current function
754 (or whether it has already been warned about, if not). */
755 static int mips_cprestore_valid = 0;
757 /* This is the register which holds the stack frame, as set by the
758 .frame pseudo-op. This is needed to implement .cprestore. */
759 static int mips_frame_reg = SP;
761 /* Whether mips_frame_reg has been set in the current function
762 (or whether it has already been warned about, if not). */
763 static int mips_frame_reg_valid = 0;
765 /* To output NOP instructions correctly, we need to keep information
766 about the previous two instructions. */
768 /* Whether we are optimizing. The default value of 2 means to remove
769 unneeded NOPs and swap branch instructions when possible. A value
770 of 1 means to not swap branches. A value of 0 means to always
772 static int mips_optimize = 2;
774 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
775 equivalent to seeing no -g option at all. */
776 static int mips_debug = 0;
778 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
779 #define MAX_VR4130_NOPS 4
781 /* The maximum number of NOPs needed to fill delay slots. */
782 #define MAX_DELAY_NOPS 2
784 /* The maximum number of NOPs needed for any purpose. */
787 /* A list of previous instructions, with index 0 being the most recent.
788 We need to look back MAX_NOPS instructions when filling delay slots
789 or working around processor errata. We need to look back one
790 instruction further if we're thinking about using history[0] to
791 fill a branch delay slot. */
792 static struct mips_cl_insn history[1 + MAX_NOPS];
794 /* Arrays of operands for each instruction. */
795 #define MAX_OPERANDS 6
796 struct mips_operand_array {
797 const struct mips_operand *operand[MAX_OPERANDS];
799 static struct mips_operand_array *mips_operands;
800 static struct mips_operand_array *mips16_operands;
801 static struct mips_operand_array *micromips_operands;
803 /* Nop instructions used by emit_nop. */
804 static struct mips_cl_insn nop_insn;
805 static struct mips_cl_insn mips16_nop_insn;
806 static struct mips_cl_insn micromips_nop16_insn;
807 static struct mips_cl_insn micromips_nop32_insn;
809 /* The appropriate nop for the current mode. */
810 #define NOP_INSN (mips_opts.mips16 \
812 : (mips_opts.micromips \
813 ? (mips_opts.insn32 \
814 ? µmips_nop32_insn \
815 : µmips_nop16_insn) \
818 /* The size of NOP_INSN in bytes. */
819 #define NOP_INSN_SIZE ((mips_opts.mips16 \
820 || (mips_opts.micromips && !mips_opts.insn32)) \
823 /* If this is set, it points to a frag holding nop instructions which
824 were inserted before the start of a noreorder section. If those
825 nops turn out to be unnecessary, the size of the frag can be
827 static fragS *prev_nop_frag;
829 /* The number of nop instructions we created in prev_nop_frag. */
830 static int prev_nop_frag_holds;
832 /* The number of nop instructions that we know we need in
834 static int prev_nop_frag_required;
836 /* The number of instructions we've seen since prev_nop_frag. */
837 static int prev_nop_frag_since;
839 /* Relocations against symbols are sometimes done in two parts, with a HI
840 relocation and a LO relocation. Each relocation has only 16 bits of
841 space to store an addend. This means that in order for the linker to
842 handle carries correctly, it must be able to locate both the HI and
843 the LO relocation. This means that the relocations must appear in
844 order in the relocation table.
846 In order to implement this, we keep track of each unmatched HI
847 relocation. We then sort them so that they immediately precede the
848 corresponding LO relocation. */
853 struct mips_hi_fixup *next;
856 /* The section this fixup is in. */
860 /* The list of unmatched HI relocs. */
862 static struct mips_hi_fixup *mips_hi_fixup_list;
864 /* The frag containing the last explicit relocation operator.
865 Null if explicit relocations have not been used. */
867 static fragS *prev_reloc_op_frag;
869 /* Map mips16 register numbers to normal MIPS register numbers. */
871 static const unsigned int mips16_to_32_reg_map[] =
873 16, 17, 2, 3, 4, 5, 6, 7
876 /* Map microMIPS register numbers to normal MIPS register numbers. */
878 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
880 /* The microMIPS registers with type h. */
881 static const unsigned int micromips_to_32_reg_h_map1[] =
883 5, 5, 6, 4, 4, 4, 4, 4
885 static const unsigned int micromips_to_32_reg_h_map2[] =
887 6, 7, 7, 21, 22, 5, 6, 7
890 /* The microMIPS registers with type m. */
891 static const unsigned int micromips_to_32_reg_m_map[] =
893 0, 17, 2, 3, 16, 18, 19, 20
896 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
898 /* Classifies the kind of instructions we're interested in when
899 implementing -mfix-vr4120. */
900 enum fix_vr4120_class
908 NUM_FIX_VR4120_CLASSES
911 /* ...likewise -mfix-loongson2f-jump. */
912 static bfd_boolean mips_fix_loongson2f_jump;
914 /* ...likewise -mfix-loongson2f-nop. */
915 static bfd_boolean mips_fix_loongson2f_nop;
917 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
918 static bfd_boolean mips_fix_loongson2f;
920 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
921 there must be at least one other instruction between an instruction
922 of type X and an instruction of type Y. */
923 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
925 /* True if -mfix-vr4120 is in force. */
926 static int mips_fix_vr4120;
928 /* ...likewise -mfix-vr4130. */
929 static int mips_fix_vr4130;
931 /* ...likewise -mfix-24k. */
932 static int mips_fix_24k;
934 /* ...likewise -mfix-rm7000 */
935 static int mips_fix_rm7000;
937 /* ...likewise -mfix-cn63xxp1 */
938 static bfd_boolean mips_fix_cn63xxp1;
940 /* We don't relax branches by default, since this causes us to expand
941 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
942 fail to compute the offset before expanding the macro to the most
943 efficient expansion. */
945 static int mips_relax_branch;
947 /* The expansion of many macros depends on the type of symbol that
948 they refer to. For example, when generating position-dependent code,
949 a macro that refers to a symbol may have two different expansions,
950 one which uses GP-relative addresses and one which uses absolute
951 addresses. When generating SVR4-style PIC, a macro may have
952 different expansions for local and global symbols.
954 We handle these situations by generating both sequences and putting
955 them in variant frags. In position-dependent code, the first sequence
956 will be the GP-relative one and the second sequence will be the
957 absolute one. In SVR4 PIC, the first sequence will be for global
958 symbols and the second will be for local symbols.
960 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
961 SECOND are the lengths of the two sequences in bytes. These fields
962 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
963 the subtype has the following flags:
966 Set if it has been decided that we should use the second
967 sequence instead of the first.
970 Set in the first variant frag if the macro's second implementation
971 is longer than its first. This refers to the macro as a whole,
972 not an individual relaxation.
975 Set in the first variant frag if the macro appeared in a .set nomacro
976 block and if one alternative requires a warning but the other does not.
979 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
982 RELAX_DELAY_SLOT_16BIT
983 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
986 RELAX_DELAY_SLOT_SIZE_FIRST
987 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
988 the macro is of the wrong size for the branch delay slot.
990 RELAX_DELAY_SLOT_SIZE_SECOND
991 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
992 the macro is of the wrong size for the branch delay slot.
994 The frag's "opcode" points to the first fixup for relaxable code.
996 Relaxable macros are generated using a sequence such as:
998 relax_start (SYMBOL);
999 ... generate first expansion ...
1001 ... generate second expansion ...
1004 The code and fixups for the unwanted alternative are discarded
1005 by md_convert_frag. */
1006 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
1008 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1009 #define RELAX_SECOND(X) ((X) & 0xff)
1010 #define RELAX_USE_SECOND 0x10000
1011 #define RELAX_SECOND_LONGER 0x20000
1012 #define RELAX_NOMACRO 0x40000
1013 #define RELAX_DELAY_SLOT 0x80000
1014 #define RELAX_DELAY_SLOT_16BIT 0x100000
1015 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1016 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
1018 /* Branch without likely bit. If label is out of range, we turn:
1020 beq reg1, reg2, label
1030 with the following opcode replacements:
1037 bltzal <-> bgezal (with jal label instead of j label)
1039 Even though keeping the delay slot instruction in the delay slot of
1040 the branch would be more efficient, it would be very tricky to do
1041 correctly, because we'd have to introduce a variable frag *after*
1042 the delay slot instruction, and expand that instead. Let's do it
1043 the easy way for now, even if the branch-not-taken case now costs
1044 one additional instruction. Out-of-range branches are not supposed
1045 to be common, anyway.
1047 Branch likely. If label is out of range, we turn:
1049 beql reg1, reg2, label
1050 delay slot (annulled if branch not taken)
1059 delay slot (executed only if branch taken)
1062 It would be possible to generate a shorter sequence by losing the
1063 likely bit, generating something like:
1068 delay slot (executed only if branch taken)
1080 bltzall -> bgezal (with jal label instead of j label)
1081 bgezall -> bltzal (ditto)
1084 but it's not clear that it would actually improve performance. */
1085 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1086 ((relax_substateT) \
1089 | ((toofar) ? 0x20 : 0) \
1090 | ((link) ? 0x40 : 0) \
1091 | ((likely) ? 0x80 : 0) \
1092 | ((uncond) ? 0x100 : 0)))
1093 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1094 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1095 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1096 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1097 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1098 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1100 /* For mips16 code, we use an entirely different form of relaxation.
1101 mips16 supports two versions of most instructions which take
1102 immediate values: a small one which takes some small value, and a
1103 larger one which takes a 16 bit value. Since branches also follow
1104 this pattern, relaxing these values is required.
1106 We can assemble both mips16 and normal MIPS code in a single
1107 object. Therefore, we need to support this type of relaxation at
1108 the same time that we support the relaxation described above. We
1109 use the high bit of the subtype field to distinguish these cases.
1111 The information we store for this type of relaxation is the
1112 argument code found in the opcode file for this relocation, whether
1113 the user explicitly requested a small or extended form, and whether
1114 the relocation is in a jump or jal delay slot. That tells us the
1115 size of the value, and how it should be stored. We also store
1116 whether the fragment is considered to be extended or not. We also
1117 store whether this is known to be a branch to a different section,
1118 whether we have tried to relax this frag yet, and whether we have
1119 ever extended a PC relative fragment because of a shift count. */
1120 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1123 | ((small) ? 0x100 : 0) \
1124 | ((ext) ? 0x200 : 0) \
1125 | ((dslot) ? 0x400 : 0) \
1126 | ((jal_dslot) ? 0x800 : 0))
1127 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1128 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1129 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1130 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1131 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1132 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1133 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1134 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1135 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1136 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1137 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1138 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1140 /* For microMIPS code, we use relaxation similar to one we use for
1141 MIPS16 code. Some instructions that take immediate values support
1142 two encodings: a small one which takes some small value, and a
1143 larger one which takes a 16 bit value. As some branches also follow
1144 this pattern, relaxing these values is required.
1146 We can assemble both microMIPS and normal MIPS code in a single
1147 object. Therefore, we need to support this type of relaxation at
1148 the same time that we support the relaxation described above. We
1149 use one of the high bits of the subtype field to distinguish these
1152 The information we store for this type of relaxation is the argument
1153 code found in the opcode file for this relocation, the register
1154 selected as the assembler temporary, whether in the 32-bit
1155 instruction mode, whether the branch is unconditional, whether it is
1156 compact, whether there is no delay-slot instruction available to fill
1157 in, whether it stores the link address implicitly in $ra, whether
1158 relaxation of out-of-range 32-bit branches to a sequence of
1159 instructions is enabled, and whether the displacement of a branch is
1160 too large to fit as an immediate argument of a 16-bit and a 32-bit
1161 branch, respectively. */
1162 #define RELAX_MICROMIPS_ENCODE(type, at, insn32, \
1163 uncond, compact, link, nods, \
1164 relax32, toofar16, toofar32) \
1167 | (((at) & 0x1f) << 8) \
1168 | ((insn32) ? 0x2000 : 0) \
1169 | ((uncond) ? 0x4000 : 0) \
1170 | ((compact) ? 0x8000 : 0) \
1171 | ((link) ? 0x10000 : 0) \
1172 | ((nods) ? 0x20000 : 0) \
1173 | ((relax32) ? 0x40000 : 0) \
1174 | ((toofar16) ? 0x80000 : 0) \
1175 | ((toofar32) ? 0x100000 : 0))
1176 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1177 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1178 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1179 #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0)
1180 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x4000) != 0)
1181 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x8000) != 0)
1182 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x10000) != 0)
1183 #define RELAX_MICROMIPS_NODS(i) (((i) & 0x20000) != 0)
1184 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x40000) != 0)
1186 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x80000) != 0)
1187 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x80000)
1188 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x80000)
1189 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x100000) != 0)
1190 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x100000)
1191 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x100000)
1193 /* Sign-extend 16-bit value X. */
1194 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1196 /* Is the given value a sign-extended 32-bit value? */
1197 #define IS_SEXT_32BIT_NUM(x) \
1198 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1199 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1201 /* Is the given value a sign-extended 16-bit value? */
1202 #define IS_SEXT_16BIT_NUM(x) \
1203 (((x) &~ (offsetT) 0x7fff) == 0 \
1204 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1206 /* Is the given value a sign-extended 12-bit value? */
1207 #define IS_SEXT_12BIT_NUM(x) \
1208 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1210 /* Is the given value a sign-extended 9-bit value? */
1211 #define IS_SEXT_9BIT_NUM(x) \
1212 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1214 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1215 #define IS_ZEXT_32BIT_NUM(x) \
1216 (((x) &~ (offsetT) 0xffffffff) == 0 \
1217 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1219 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1221 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1222 (((STRUCT) >> (SHIFT)) & (MASK))
1224 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1225 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1227 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1228 : EXTRACT_BITS ((INSN).insn_opcode, \
1229 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1230 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1231 EXTRACT_BITS ((INSN).insn_opcode, \
1232 MIPS16OP_MASK_##FIELD, \
1233 MIPS16OP_SH_##FIELD)
1235 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1236 #define MIPS16_EXTEND (0xf000U << 16)
1238 /* Whether or not we are emitting a branch-likely macro. */
1239 static bfd_boolean emit_branch_likely_macro = FALSE;
1241 /* Global variables used when generating relaxable macros. See the
1242 comment above RELAX_ENCODE for more details about how relaxation
1245 /* 0 if we're not emitting a relaxable macro.
1246 1 if we're emitting the first of the two relaxation alternatives.
1247 2 if we're emitting the second alternative. */
1250 /* The first relaxable fixup in the current frag. (In other words,
1251 the first fixup that refers to relaxable code.) */
1254 /* sizes[0] says how many bytes of the first alternative are stored in
1255 the current frag. Likewise sizes[1] for the second alternative. */
1256 unsigned int sizes[2];
1258 /* The symbol on which the choice of sequence depends. */
1262 /* Global variables used to decide whether a macro needs a warning. */
1264 /* True if the macro is in a branch delay slot. */
1265 bfd_boolean delay_slot_p;
1267 /* Set to the length in bytes required if the macro is in a delay slot
1268 that requires a specific length of instruction, otherwise zero. */
1269 unsigned int delay_slot_length;
1271 /* For relaxable macros, sizes[0] is the length of the first alternative
1272 in bytes and sizes[1] is the length of the second alternative.
1273 For non-relaxable macros, both elements give the length of the
1275 unsigned int sizes[2];
1277 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1278 instruction of the first alternative in bytes and first_insn_sizes[1]
1279 is the length of the first instruction of the second alternative.
1280 For non-relaxable macros, both elements give the length of the first
1281 instruction in bytes.
1283 Set to zero if we haven't yet seen the first instruction. */
1284 unsigned int first_insn_sizes[2];
1286 /* For relaxable macros, insns[0] is the number of instructions for the
1287 first alternative and insns[1] is the number of instructions for the
1290 For non-relaxable macros, both elements give the number of
1291 instructions for the macro. */
1292 unsigned int insns[2];
1294 /* The first variant frag for this macro. */
1296 } mips_macro_warning;
1298 /* Prototypes for static functions. */
1300 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1302 static void append_insn
1303 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1304 bfd_boolean expansionp);
1305 static void mips_no_prev_insn (void);
1306 static void macro_build (expressionS *, const char *, const char *, ...);
1307 static void mips16_macro_build
1308 (expressionS *, const char *, const char *, va_list *);
1309 static void load_register (int, expressionS *, int);
1310 static void macro_start (void);
1311 static void macro_end (void);
1312 static void macro (struct mips_cl_insn *ip, char *str);
1313 static void mips16_macro (struct mips_cl_insn * ip);
1314 static void mips_ip (char *str, struct mips_cl_insn * ip);
1315 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1316 static void mips16_immed
1317 (const char *, unsigned int, int, bfd_reloc_code_real_type, offsetT,
1318 unsigned int, unsigned long *);
1319 static size_t my_getSmallExpression
1320 (expressionS *, bfd_reloc_code_real_type *, char *);
1321 static void my_getExpression (expressionS *, char *);
1322 static void s_align (int);
1323 static void s_change_sec (int);
1324 static void s_change_section (int);
1325 static void s_cons (int);
1326 static void s_float_cons (int);
1327 static void s_mips_globl (int);
1328 static void s_option (int);
1329 static void s_mipsset (int);
1330 static void s_abicalls (int);
1331 static void s_cpload (int);
1332 static void s_cpsetup (int);
1333 static void s_cplocal (int);
1334 static void s_cprestore (int);
1335 static void s_cpreturn (int);
1336 static void s_dtprelword (int);
1337 static void s_dtpreldword (int);
1338 static void s_tprelword (int);
1339 static void s_tpreldword (int);
1340 static void s_gpvalue (int);
1341 static void s_gpword (int);
1342 static void s_gpdword (int);
1343 static void s_ehword (int);
1344 static void s_cpadd (int);
1345 static void s_insn (int);
1346 static void s_nan (int);
1347 static void s_module (int);
1348 static void s_mips_ent (int);
1349 static void s_mips_end (int);
1350 static void s_mips_frame (int);
1351 static void s_mips_mask (int reg_type);
1352 static void s_mips_stab (int);
1353 static void s_mips_weakext (int);
1354 static void s_mips_file (int);
1355 static void s_mips_loc (int);
1356 static bfd_boolean pic_need_relax (symbolS *, asection *);
1357 static int relaxed_branch_length (fragS *, asection *, int);
1358 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1359 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1360 static void file_mips_check_options (void);
1362 /* Table and functions used to map between CPU/ISA names, and
1363 ISA levels, and CPU numbers. */
1365 struct mips_cpu_info
1367 const char *name; /* CPU or ISA name. */
1368 int flags; /* MIPS_CPU_* flags. */
1369 int ase; /* Set of ASEs implemented by the CPU. */
1370 int isa; /* ISA level. */
1371 int cpu; /* CPU number (default CPU if ISA). */
1374 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1376 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1377 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1378 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1380 /* Command-line options. */
1381 const char *md_shortopts = "O::g::G:";
1385 OPTION_MARCH = OPTION_MD_BASE,
1417 OPTION_NO_SMARTMIPS,
1427 OPTION_NO_MICROMIPS,
1430 OPTION_COMPAT_ARCH_BASE,
1439 OPTION_M7000_HILO_FIX,
1440 OPTION_MNO_7000_HILO_FIX,
1444 OPTION_NO_FIX_RM7000,
1445 OPTION_FIX_LOONGSON2F_JUMP,
1446 OPTION_NO_FIX_LOONGSON2F_JUMP,
1447 OPTION_FIX_LOONGSON2F_NOP,
1448 OPTION_NO_FIX_LOONGSON2F_NOP,
1450 OPTION_NO_FIX_VR4120,
1452 OPTION_NO_FIX_VR4130,
1453 OPTION_FIX_CN63XXP1,
1454 OPTION_NO_FIX_CN63XXP1,
1461 OPTION_CONSTRUCT_FLOATS,
1462 OPTION_NO_CONSTRUCT_FLOATS,
1466 OPTION_RELAX_BRANCH,
1467 OPTION_NO_RELAX_BRANCH,
1476 OPTION_SINGLE_FLOAT,
1477 OPTION_DOUBLE_FLOAT,
1490 OPTION_MVXWORKS_PIC,
1493 OPTION_NO_ODD_SPREG,
1497 struct option md_longopts[] =
1499 /* Options which specify architecture. */
1500 {"march", required_argument, NULL, OPTION_MARCH},
1501 {"mtune", required_argument, NULL, OPTION_MTUNE},
1502 {"mips0", no_argument, NULL, OPTION_MIPS1},
1503 {"mips1", no_argument, NULL, OPTION_MIPS1},
1504 {"mips2", no_argument, NULL, OPTION_MIPS2},
1505 {"mips3", no_argument, NULL, OPTION_MIPS3},
1506 {"mips4", no_argument, NULL, OPTION_MIPS4},
1507 {"mips5", no_argument, NULL, OPTION_MIPS5},
1508 {"mips32", no_argument, NULL, OPTION_MIPS32},
1509 {"mips64", no_argument, NULL, OPTION_MIPS64},
1510 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
1511 {"mips32r3", no_argument, NULL, OPTION_MIPS32R3},
1512 {"mips32r5", no_argument, NULL, OPTION_MIPS32R5},
1513 {"mips32r6", no_argument, NULL, OPTION_MIPS32R6},
1514 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
1515 {"mips64r3", no_argument, NULL, OPTION_MIPS64R3},
1516 {"mips64r5", no_argument, NULL, OPTION_MIPS64R5},
1517 {"mips64r6", no_argument, NULL, OPTION_MIPS64R6},
1519 /* Options which specify Application Specific Extensions (ASEs). */
1520 {"mips16", no_argument, NULL, OPTION_MIPS16},
1521 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
1522 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
1523 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
1524 {"mdmx", no_argument, NULL, OPTION_MDMX},
1525 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
1526 {"mdsp", no_argument, NULL, OPTION_DSP},
1527 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
1528 {"mmt", no_argument, NULL, OPTION_MT},
1529 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
1530 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
1531 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
1532 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
1533 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
1534 {"mdspr3", no_argument, NULL, OPTION_DSPR3},
1535 {"mno-dspr3", no_argument, NULL, OPTION_NO_DSPR3},
1536 {"meva", no_argument, NULL, OPTION_EVA},
1537 {"mno-eva", no_argument, NULL, OPTION_NO_EVA},
1538 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
1539 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
1540 {"mmcu", no_argument, NULL, OPTION_MCU},
1541 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
1542 {"mvirt", no_argument, NULL, OPTION_VIRT},
1543 {"mno-virt", no_argument, NULL, OPTION_NO_VIRT},
1544 {"mmsa", no_argument, NULL, OPTION_MSA},
1545 {"mno-msa", no_argument, NULL, OPTION_NO_MSA},
1546 {"mxpa", no_argument, NULL, OPTION_XPA},
1547 {"mno-xpa", no_argument, NULL, OPTION_NO_XPA},
1549 /* Old-style architecture options. Don't add more of these. */
1550 {"m4650", no_argument, NULL, OPTION_M4650},
1551 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
1552 {"m4010", no_argument, NULL, OPTION_M4010},
1553 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
1554 {"m4100", no_argument, NULL, OPTION_M4100},
1555 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
1556 {"m3900", no_argument, NULL, OPTION_M3900},
1557 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
1559 /* Options which enable bug fixes. */
1560 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
1561 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1562 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1563 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
1564 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
1565 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
1566 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
1567 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
1568 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
1569 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
1570 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
1571 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
1572 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
1573 {"mfix-rm7000", no_argument, NULL, OPTION_FIX_RM7000},
1574 {"mno-fix-rm7000", no_argument, NULL, OPTION_NO_FIX_RM7000},
1575 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
1576 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
1578 /* Miscellaneous options. */
1579 {"trap", no_argument, NULL, OPTION_TRAP},
1580 {"no-break", no_argument, NULL, OPTION_TRAP},
1581 {"break", no_argument, NULL, OPTION_BREAK},
1582 {"no-trap", no_argument, NULL, OPTION_BREAK},
1583 {"EB", no_argument, NULL, OPTION_EB},
1584 {"EL", no_argument, NULL, OPTION_EL},
1585 {"mfp32", no_argument, NULL, OPTION_FP32},
1586 {"mgp32", no_argument, NULL, OPTION_GP32},
1587 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
1588 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
1589 {"mfp64", no_argument, NULL, OPTION_FP64},
1590 {"mfpxx", no_argument, NULL, OPTION_FPXX},
1591 {"mgp64", no_argument, NULL, OPTION_GP64},
1592 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
1593 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
1594 {"minsn32", no_argument, NULL, OPTION_INSN32},
1595 {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32},
1596 {"mshared", no_argument, NULL, OPTION_MSHARED},
1597 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
1598 {"msym32", no_argument, NULL, OPTION_MSYM32},
1599 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
1600 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
1601 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
1602 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
1603 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
1604 {"modd-spreg", no_argument, NULL, OPTION_ODD_SPREG},
1605 {"mno-odd-spreg", no_argument, NULL, OPTION_NO_ODD_SPREG},
1607 /* Strictly speaking this next option is ELF specific,
1608 but we allow it for other ports as well in order to
1609 make testing easier. */
1610 {"32", no_argument, NULL, OPTION_32},
1612 /* ELF-specific options. */
1613 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
1614 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
1615 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
1616 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
1617 {"xgot", no_argument, NULL, OPTION_XGOT},
1618 {"mabi", required_argument, NULL, OPTION_MABI},
1619 {"n32", no_argument, NULL, OPTION_N32},
1620 {"64", no_argument, NULL, OPTION_64},
1621 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
1622 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
1623 {"mpdr", no_argument, NULL, OPTION_PDR},
1624 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
1625 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
1626 {"mnan", required_argument, NULL, OPTION_NAN},
1628 {NULL, no_argument, NULL, 0}
1630 size_t md_longopts_size = sizeof (md_longopts);
1632 /* Information about either an Application Specific Extension or an
1633 optional architecture feature that, for simplicity, we treat in the
1634 same way as an ASE. */
1637 /* The name of the ASE, used in both the command-line and .set options. */
1640 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1641 and 64-bit architectures, the flags here refer to the subset that
1642 is available on both. */
1645 /* The ASE_* flag used for instructions that are available on 64-bit
1646 architectures but that are not included in FLAGS. */
1647 unsigned int flags64;
1649 /* The command-line options that turn the ASE on and off. */
1653 /* The minimum required architecture revisions for MIPS32, MIPS64,
1654 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1657 int micromips32_rev;
1658 int micromips64_rev;
1660 /* The architecture where the ASE was removed or -1 if the extension has not
1665 /* A table of all supported ASEs. */
1666 static const struct mips_ase mips_ases[] = {
1667 { "dsp", ASE_DSP, ASE_DSP64,
1668 OPTION_DSP, OPTION_NO_DSP,
1672 { "dspr2", ASE_DSP | ASE_DSPR2, 0,
1673 OPTION_DSPR2, OPTION_NO_DSPR2,
1677 { "dspr3", ASE_DSP | ASE_DSPR2 | ASE_DSPR3, 0,
1678 OPTION_DSPR3, OPTION_NO_DSPR3,
1682 { "eva", ASE_EVA, 0,
1683 OPTION_EVA, OPTION_NO_EVA,
1687 { "mcu", ASE_MCU, 0,
1688 OPTION_MCU, OPTION_NO_MCU,
1692 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1693 { "mdmx", ASE_MDMX, 0,
1694 OPTION_MDMX, OPTION_NO_MDMX,
1698 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1699 { "mips3d", ASE_MIPS3D, 0,
1700 OPTION_MIPS3D, OPTION_NO_MIPS3D,
1705 OPTION_MT, OPTION_NO_MT,
1709 { "smartmips", ASE_SMARTMIPS, 0,
1710 OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS,
1714 { "virt", ASE_VIRT, ASE_VIRT64,
1715 OPTION_VIRT, OPTION_NO_VIRT,
1719 { "msa", ASE_MSA, ASE_MSA64,
1720 OPTION_MSA, OPTION_NO_MSA,
1724 { "xpa", ASE_XPA, 0,
1725 OPTION_XPA, OPTION_NO_XPA,
1730 /* The set of ASEs that require -mfp64. */
1731 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
1733 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1734 static const unsigned int mips_ase_groups[] = {
1735 ASE_DSP | ASE_DSPR2 | ASE_DSPR3
1740 The following pseudo-ops from the Kane and Heinrich MIPS book
1741 should be defined here, but are currently unsupported: .alias,
1742 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1744 The following pseudo-ops from the Kane and Heinrich MIPS book are
1745 specific to the type of debugging information being generated, and
1746 should be defined by the object format: .aent, .begin, .bend,
1747 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1750 The following pseudo-ops from the Kane and Heinrich MIPS book are
1751 not MIPS CPU specific, but are also not specific to the object file
1752 format. This file is probably the best place to define them, but
1753 they are not currently supported: .asm0, .endr, .lab, .struct. */
1755 static const pseudo_typeS mips_pseudo_table[] =
1757 /* MIPS specific pseudo-ops. */
1758 {"option", s_option, 0},
1759 {"set", s_mipsset, 0},
1760 {"rdata", s_change_sec, 'r'},
1761 {"sdata", s_change_sec, 's'},
1762 {"livereg", s_ignore, 0},
1763 {"abicalls", s_abicalls, 0},
1764 {"cpload", s_cpload, 0},
1765 {"cpsetup", s_cpsetup, 0},
1766 {"cplocal", s_cplocal, 0},
1767 {"cprestore", s_cprestore, 0},
1768 {"cpreturn", s_cpreturn, 0},
1769 {"dtprelword", s_dtprelword, 0},
1770 {"dtpreldword", s_dtpreldword, 0},
1771 {"tprelword", s_tprelword, 0},
1772 {"tpreldword", s_tpreldword, 0},
1773 {"gpvalue", s_gpvalue, 0},
1774 {"gpword", s_gpword, 0},
1775 {"gpdword", s_gpdword, 0},
1776 {"ehword", s_ehword, 0},
1777 {"cpadd", s_cpadd, 0},
1778 {"insn", s_insn, 0},
1780 {"module", s_module, 0},
1782 /* Relatively generic pseudo-ops that happen to be used on MIPS
1784 {"asciiz", stringer, 8 + 1},
1785 {"bss", s_change_sec, 'b'},
1787 {"half", s_cons, 1},
1788 {"dword", s_cons, 3},
1789 {"weakext", s_mips_weakext, 0},
1790 {"origin", s_org, 0},
1791 {"repeat", s_rept, 0},
1793 /* For MIPS this is non-standard, but we define it for consistency. */
1794 {"sbss", s_change_sec, 'B'},
1796 /* These pseudo-ops are defined in read.c, but must be overridden
1797 here for one reason or another. */
1798 {"align", s_align, 0},
1799 {"byte", s_cons, 0},
1800 {"data", s_change_sec, 'd'},
1801 {"double", s_float_cons, 'd'},
1802 {"float", s_float_cons, 'f'},
1803 {"globl", s_mips_globl, 0},
1804 {"global", s_mips_globl, 0},
1805 {"hword", s_cons, 1},
1807 {"long", s_cons, 2},
1808 {"octa", s_cons, 4},
1809 {"quad", s_cons, 3},
1810 {"section", s_change_section, 0},
1811 {"short", s_cons, 1},
1812 {"single", s_float_cons, 'f'},
1813 {"stabd", s_mips_stab, 'd'},
1814 {"stabn", s_mips_stab, 'n'},
1815 {"stabs", s_mips_stab, 's'},
1816 {"text", s_change_sec, 't'},
1817 {"word", s_cons, 2},
1819 { "extern", ecoff_directive_extern, 0},
1824 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1826 /* These pseudo-ops should be defined by the object file format.
1827 However, a.out doesn't support them, so we have versions here. */
1828 {"aent", s_mips_ent, 1},
1829 {"bgnb", s_ignore, 0},
1830 {"end", s_mips_end, 0},
1831 {"endb", s_ignore, 0},
1832 {"ent", s_mips_ent, 0},
1833 {"file", s_mips_file, 0},
1834 {"fmask", s_mips_mask, 'F'},
1835 {"frame", s_mips_frame, 0},
1836 {"loc", s_mips_loc, 0},
1837 {"mask", s_mips_mask, 'R'},
1838 {"verstamp", s_ignore, 0},
1842 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1843 purpose of the `.dc.a' internal pseudo-op. */
1846 mips_address_bytes (void)
1848 file_mips_check_options ();
1849 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1852 extern void pop_insert (const pseudo_typeS *);
1855 mips_pop_insert (void)
1857 pop_insert (mips_pseudo_table);
1858 if (! ECOFF_DEBUGGING)
1859 pop_insert (mips_nonecoff_pseudo_table);
1862 /* Symbols labelling the current insn. */
1864 struct insn_label_list
1866 struct insn_label_list *next;
1870 static struct insn_label_list *free_insn_labels;
1871 #define label_list tc_segment_info_data.labels
1873 static void mips_clear_insn_labels (void);
1874 static void mips_mark_labels (void);
1875 static void mips_compressed_mark_labels (void);
1878 mips_clear_insn_labels (void)
1880 struct insn_label_list **pl;
1881 segment_info_type *si;
1885 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1888 si = seg_info (now_seg);
1889 *pl = si->label_list;
1890 si->label_list = NULL;
1894 /* Mark instruction labels in MIPS16/microMIPS mode. */
1897 mips_mark_labels (void)
1899 if (HAVE_CODE_COMPRESSION)
1900 mips_compressed_mark_labels ();
1903 static char *expr_end;
1905 /* An expression in a macro instruction. This is set by mips_ip and
1906 mips16_ip and when populated is always an O_constant. */
1908 static expressionS imm_expr;
1910 /* The relocatable field in an instruction and the relocs associated
1911 with it. These variables are used for instructions like LUI and
1912 JAL as well as true offsets. They are also used for address
1913 operands in macros. */
1915 static expressionS offset_expr;
1916 static bfd_reloc_code_real_type offset_reloc[3]
1917 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1919 /* This is set to the resulting size of the instruction to be produced
1920 by mips16_ip if an explicit extension is used or by mips_ip if an
1921 explicit size is supplied. */
1923 static unsigned int forced_insn_length;
1925 /* True if we are assembling an instruction. All dot symbols defined during
1926 this time should be treated as code labels. */
1928 static bfd_boolean mips_assembling_insn;
1930 /* The pdr segment for per procedure frame/regmask info. Not used for
1933 static segT pdr_seg;
1935 /* The default target format to use. */
1937 #if defined (TE_FreeBSD)
1938 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1939 #elif defined (TE_TMIPS)
1940 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1942 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1946 mips_target_format (void)
1948 switch (OUTPUT_FLAVOR)
1950 case bfd_target_elf_flavour:
1952 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1953 return (target_big_endian
1954 ? "elf32-bigmips-vxworks"
1955 : "elf32-littlemips-vxworks");
1957 return (target_big_endian
1958 ? (HAVE_64BIT_OBJECTS
1959 ? ELF_TARGET ("elf64-", "big")
1961 ? ELF_TARGET ("elf32-n", "big")
1962 : ELF_TARGET ("elf32-", "big")))
1963 : (HAVE_64BIT_OBJECTS
1964 ? ELF_TARGET ("elf64-", "little")
1966 ? ELF_TARGET ("elf32-n", "little")
1967 : ELF_TARGET ("elf32-", "little"))));
1974 /* Return the ISA revision that is currently in use, or 0 if we are
1975 generating code for MIPS V or below. */
1980 if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2)
1983 if (mips_opts.isa == ISA_MIPS32R3 || mips_opts.isa == ISA_MIPS64R3)
1986 if (mips_opts.isa == ISA_MIPS32R5 || mips_opts.isa == ISA_MIPS64R5)
1989 if (mips_opts.isa == ISA_MIPS32R6 || mips_opts.isa == ISA_MIPS64R6)
1992 /* microMIPS implies revision 2 or above. */
1993 if (mips_opts.micromips)
1996 if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64)
2002 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
2005 mips_ase_mask (unsigned int flags)
2009 for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++)
2010 if (flags & mips_ase_groups[i])
2011 flags |= mips_ase_groups[i];
2015 /* Check whether the current ISA supports ASE. Issue a warning if
2019 mips_check_isa_supports_ase (const struct mips_ase *ase)
2023 static unsigned int warned_isa;
2024 static unsigned int warned_fp32;
2026 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
2027 min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev;
2029 min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev;
2030 if ((min_rev < 0 || mips_isa_rev () < min_rev)
2031 && (warned_isa & ase->flags) != ase->flags)
2033 warned_isa |= ase->flags;
2034 base = mips_opts.micromips ? "microMIPS" : "MIPS";
2035 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
2037 as_warn (_("the %d-bit %s architecture does not support the"
2038 " `%s' extension"), size, base, ase->name);
2040 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
2041 ase->name, base, size, min_rev);
2043 else if ((ase->rem_rev > 0 && mips_isa_rev () >= ase->rem_rev)
2044 && (warned_isa & ase->flags) != ase->flags)
2046 warned_isa |= ase->flags;
2047 base = mips_opts.micromips ? "microMIPS" : "MIPS";
2048 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
2049 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2050 ase->name, base, size, ase->rem_rev);
2053 if ((ase->flags & FP64_ASES)
2054 && mips_opts.fp != 64
2055 && (warned_fp32 & ase->flags) != ase->flags)
2057 warned_fp32 |= ase->flags;
2058 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase->name);
2062 /* Check all enabled ASEs to see whether they are supported by the
2063 chosen architecture. */
2066 mips_check_isa_supports_ases (void)
2068 unsigned int i, mask;
2070 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2072 mask = mips_ase_mask (mips_ases[i].flags);
2073 if ((mips_opts.ase & mask) == mips_ases[i].flags)
2074 mips_check_isa_supports_ase (&mips_ases[i]);
2078 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2079 that were affected. */
2082 mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts,
2083 bfd_boolean enabled_p)
2087 mask = mips_ase_mask (ase->flags);
2090 opts->ase |= ase->flags;
2094 /* Return the ASE called NAME, or null if none. */
2096 static const struct mips_ase *
2097 mips_lookup_ase (const char *name)
2101 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2102 if (strcmp (name, mips_ases[i].name) == 0)
2103 return &mips_ases[i];
2107 /* Return the length of a microMIPS instruction in bytes. If bits of
2108 the mask beyond the low 16 are 0, then it is a 16-bit instruction,
2109 otherwise it is a 32-bit instruction. */
2111 static inline unsigned int
2112 micromips_insn_length (const struct mips_opcode *mo)
2114 return mips_opcode_32bit_p (mo) ? 4 : 2;
2117 /* Return the length of MIPS16 instruction OPCODE. */
2119 static inline unsigned int
2120 mips16_opcode_length (unsigned long opcode)
2122 return (opcode >> 16) == 0 ? 2 : 4;
2125 /* Return the length of instruction INSN. */
2127 static inline unsigned int
2128 insn_length (const struct mips_cl_insn *insn)
2130 if (mips_opts.micromips)
2131 return micromips_insn_length (insn->insn_mo);
2132 else if (mips_opts.mips16)
2133 return mips16_opcode_length (insn->insn_opcode);
2138 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2141 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
2146 insn->insn_opcode = mo->match;
2149 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2150 insn->fixp[i] = NULL;
2151 insn->fixed_p = (mips_opts.noreorder > 0);
2152 insn->noreorder_p = (mips_opts.noreorder > 0);
2153 insn->mips16_absolute_jump_p = 0;
2154 insn->complete_p = 0;
2155 insn->cleared_p = 0;
2158 /* Get a list of all the operands in INSN. */
2160 static const struct mips_operand_array *
2161 insn_operands (const struct mips_cl_insn *insn)
2163 if (insn->insn_mo >= &mips_opcodes[0]
2164 && insn->insn_mo < &mips_opcodes[NUMOPCODES])
2165 return &mips_operands[insn->insn_mo - &mips_opcodes[0]];
2167 if (insn->insn_mo >= &mips16_opcodes[0]
2168 && insn->insn_mo < &mips16_opcodes[bfd_mips16_num_opcodes])
2169 return &mips16_operands[insn->insn_mo - &mips16_opcodes[0]];
2171 if (insn->insn_mo >= µmips_opcodes[0]
2172 && insn->insn_mo < µmips_opcodes[bfd_micromips_num_opcodes])
2173 return µmips_operands[insn->insn_mo - µmips_opcodes[0]];
2178 /* Get a description of operand OPNO of INSN. */
2180 static const struct mips_operand *
2181 insn_opno (const struct mips_cl_insn *insn, unsigned opno)
2183 const struct mips_operand_array *operands;
2185 operands = insn_operands (insn);
2186 if (opno >= MAX_OPERANDS || !operands->operand[opno])
2188 return operands->operand[opno];
2191 /* Install UVAL as the value of OPERAND in INSN. */
2194 insn_insert_operand (struct mips_cl_insn *insn,
2195 const struct mips_operand *operand, unsigned int uval)
2197 insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval);
2200 /* Extract the value of OPERAND from INSN. */
2202 static inline unsigned
2203 insn_extract_operand (const struct mips_cl_insn *insn,
2204 const struct mips_operand *operand)
2206 return mips_extract_operand (operand, insn->insn_opcode);
2209 /* Record the current MIPS16/microMIPS mode in now_seg. */
2212 mips_record_compressed_mode (void)
2214 segment_info_type *si;
2216 si = seg_info (now_seg);
2217 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
2218 si->tc_segment_info_data.mips16 = mips_opts.mips16;
2219 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
2220 si->tc_segment_info_data.micromips = mips_opts.micromips;
2223 /* Read a standard MIPS instruction from BUF. */
2225 static unsigned long
2226 read_insn (char *buf)
2228 if (target_big_endian)
2229 return bfd_getb32 ((bfd_byte *) buf);
2231 return bfd_getl32 ((bfd_byte *) buf);
2234 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2238 write_insn (char *buf, unsigned int insn)
2240 md_number_to_chars (buf, insn, 4);
2244 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2245 has length LENGTH. */
2247 static unsigned long
2248 read_compressed_insn (char *buf, unsigned int length)
2254 for (i = 0; i < length; i += 2)
2257 if (target_big_endian)
2258 insn |= bfd_getb16 ((char *) buf);
2260 insn |= bfd_getl16 ((char *) buf);
2266 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2267 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2270 write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
2274 for (i = 0; i < length; i += 2)
2275 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
2276 return buf + length;
2279 /* Install INSN at the location specified by its "frag" and "where" fields. */
2282 install_insn (const struct mips_cl_insn *insn)
2284 char *f = insn->frag->fr_literal + insn->where;
2285 if (HAVE_CODE_COMPRESSION)
2286 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
2288 write_insn (f, insn->insn_opcode);
2289 mips_record_compressed_mode ();
2292 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2293 and install the opcode in the new location. */
2296 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
2301 insn->where = where;
2302 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2303 if (insn->fixp[i] != NULL)
2305 insn->fixp[i]->fx_frag = frag;
2306 insn->fixp[i]->fx_where = where;
2308 install_insn (insn);
2311 /* Add INSN to the end of the output. */
2314 add_fixed_insn (struct mips_cl_insn *insn)
2316 char *f = frag_more (insn_length (insn));
2317 move_insn (insn, frag_now, f - frag_now->fr_literal);
2320 /* Start a variant frag and move INSN to the start of the variant part,
2321 marking it as fixed. The other arguments are as for frag_var. */
2324 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
2325 relax_substateT subtype, symbolS *symbol, offsetT offset)
2327 frag_grow (max_chars);
2328 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
2330 frag_var (rs_machine_dependent, max_chars, var,
2331 subtype, symbol, offset, NULL);
2334 /* Insert N copies of INSN into the history buffer, starting at
2335 position FIRST. Neither FIRST nor N need to be clipped. */
2338 insert_into_history (unsigned int first, unsigned int n,
2339 const struct mips_cl_insn *insn)
2341 if (mips_relax.sequence != 2)
2345 for (i = ARRAY_SIZE (history); i-- > first;)
2347 history[i] = history[i - n];
2353 /* Clear the error in insn_error. */
2356 clear_insn_error (void)
2358 memset (&insn_error, 0, sizeof (insn_error));
2361 /* Possibly record error message MSG for the current instruction.
2362 If the error is about a particular argument, ARGNUM is the 1-based
2363 number of that argument, otherwise it is 0. FORMAT is the format
2364 of MSG. Return true if MSG was used, false if the current message
2368 set_insn_error_format (int argnum, enum mips_insn_error_format format,
2373 /* Give priority to errors against specific arguments, and to
2374 the first whole-instruction message. */
2380 /* Keep insn_error if it is against a later argument. */
2381 if (argnum < insn_error.min_argnum)
2384 /* If both errors are against the same argument but are different,
2385 give up on reporting a specific error for this argument.
2386 See the comment about mips_insn_error for details. */
2387 if (argnum == insn_error.min_argnum
2389 && strcmp (insn_error.msg, msg) != 0)
2392 insn_error.min_argnum += 1;
2396 insn_error.min_argnum = argnum;
2397 insn_error.format = format;
2398 insn_error.msg = msg;
2402 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2403 as for set_insn_error_format. */
2406 set_insn_error (int argnum, const char *msg)
2408 set_insn_error_format (argnum, ERR_FMT_PLAIN, msg);
2411 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2412 as for set_insn_error_format. */
2415 set_insn_error_i (int argnum, const char *msg, int i)
2417 if (set_insn_error_format (argnum, ERR_FMT_I, msg))
2421 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2422 are as for set_insn_error_format. */
2425 set_insn_error_ss (int argnum, const char *msg, const char *s1, const char *s2)
2427 if (set_insn_error_format (argnum, ERR_FMT_SS, msg))
2429 insn_error.u.ss[0] = s1;
2430 insn_error.u.ss[1] = s2;
2434 /* Report the error in insn_error, which is against assembly code STR. */
2437 report_insn_error (const char *str)
2439 const char *msg = concat (insn_error.msg, " `%s'", NULL);
2441 switch (insn_error.format)
2448 as_bad (msg, insn_error.u.i, str);
2452 as_bad (msg, insn_error.u.ss[0], insn_error.u.ss[1], str);
2456 free ((char *) msg);
2459 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2460 the idea is to make it obvious at a glance that each errata is
2464 init_vr4120_conflicts (void)
2466 #define CONFLICT(FIRST, SECOND) \
2467 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2469 /* Errata 21 - [D]DIV[U] after [D]MACC */
2470 CONFLICT (MACC, DIV);
2471 CONFLICT (DMACC, DIV);
2473 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2474 CONFLICT (DMULT, DMULT);
2475 CONFLICT (DMULT, DMACC);
2476 CONFLICT (DMACC, DMULT);
2477 CONFLICT (DMACC, DMACC);
2479 /* Errata 24 - MT{LO,HI} after [D]MACC */
2480 CONFLICT (MACC, MTHILO);
2481 CONFLICT (DMACC, MTHILO);
2483 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2484 instruction is executed immediately after a MACC or DMACC
2485 instruction, the result of [either instruction] is incorrect." */
2486 CONFLICT (MACC, MULT);
2487 CONFLICT (MACC, DMULT);
2488 CONFLICT (DMACC, MULT);
2489 CONFLICT (DMACC, DMULT);
2491 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2492 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2493 DDIV or DDIVU instruction, the result of the MACC or
2494 DMACC instruction is incorrect.". */
2495 CONFLICT (DMULT, MACC);
2496 CONFLICT (DMULT, DMACC);
2497 CONFLICT (DIV, MACC);
2498 CONFLICT (DIV, DMACC);
2508 #define RNUM_MASK 0x00000ff
2509 #define RTYPE_MASK 0x0ffff00
2510 #define RTYPE_NUM 0x0000100
2511 #define RTYPE_FPU 0x0000200
2512 #define RTYPE_FCC 0x0000400
2513 #define RTYPE_VEC 0x0000800
2514 #define RTYPE_GP 0x0001000
2515 #define RTYPE_CP0 0x0002000
2516 #define RTYPE_PC 0x0004000
2517 #define RTYPE_ACC 0x0008000
2518 #define RTYPE_CCC 0x0010000
2519 #define RTYPE_VI 0x0020000
2520 #define RTYPE_VF 0x0040000
2521 #define RTYPE_R5900_I 0x0080000
2522 #define RTYPE_R5900_Q 0x0100000
2523 #define RTYPE_R5900_R 0x0200000
2524 #define RTYPE_R5900_ACC 0x0400000
2525 #define RTYPE_MSA 0x0800000
2526 #define RWARN 0x8000000
2528 #define GENERIC_REGISTER_NUMBERS \
2529 {"$0", RTYPE_NUM | 0}, \
2530 {"$1", RTYPE_NUM | 1}, \
2531 {"$2", RTYPE_NUM | 2}, \
2532 {"$3", RTYPE_NUM | 3}, \
2533 {"$4", RTYPE_NUM | 4}, \
2534 {"$5", RTYPE_NUM | 5}, \
2535 {"$6", RTYPE_NUM | 6}, \
2536 {"$7", RTYPE_NUM | 7}, \
2537 {"$8", RTYPE_NUM | 8}, \
2538 {"$9", RTYPE_NUM | 9}, \
2539 {"$10", RTYPE_NUM | 10}, \
2540 {"$11", RTYPE_NUM | 11}, \
2541 {"$12", RTYPE_NUM | 12}, \
2542 {"$13", RTYPE_NUM | 13}, \
2543 {"$14", RTYPE_NUM | 14}, \
2544 {"$15", RTYPE_NUM | 15}, \
2545 {"$16", RTYPE_NUM | 16}, \
2546 {"$17", RTYPE_NUM | 17}, \
2547 {"$18", RTYPE_NUM | 18}, \
2548 {"$19", RTYPE_NUM | 19}, \
2549 {"$20", RTYPE_NUM | 20}, \
2550 {"$21", RTYPE_NUM | 21}, \
2551 {"$22", RTYPE_NUM | 22}, \
2552 {"$23", RTYPE_NUM | 23}, \
2553 {"$24", RTYPE_NUM | 24}, \
2554 {"$25", RTYPE_NUM | 25}, \
2555 {"$26", RTYPE_NUM | 26}, \
2556 {"$27", RTYPE_NUM | 27}, \
2557 {"$28", RTYPE_NUM | 28}, \
2558 {"$29", RTYPE_NUM | 29}, \
2559 {"$30", RTYPE_NUM | 30}, \
2560 {"$31", RTYPE_NUM | 31}
2562 #define FPU_REGISTER_NAMES \
2563 {"$f0", RTYPE_FPU | 0}, \
2564 {"$f1", RTYPE_FPU | 1}, \
2565 {"$f2", RTYPE_FPU | 2}, \
2566 {"$f3", RTYPE_FPU | 3}, \
2567 {"$f4", RTYPE_FPU | 4}, \
2568 {"$f5", RTYPE_FPU | 5}, \
2569 {"$f6", RTYPE_FPU | 6}, \
2570 {"$f7", RTYPE_FPU | 7}, \
2571 {"$f8", RTYPE_FPU | 8}, \
2572 {"$f9", RTYPE_FPU | 9}, \
2573 {"$f10", RTYPE_FPU | 10}, \
2574 {"$f11", RTYPE_FPU | 11}, \
2575 {"$f12", RTYPE_FPU | 12}, \
2576 {"$f13", RTYPE_FPU | 13}, \
2577 {"$f14", RTYPE_FPU | 14}, \
2578 {"$f15", RTYPE_FPU | 15}, \
2579 {"$f16", RTYPE_FPU | 16}, \
2580 {"$f17", RTYPE_FPU | 17}, \
2581 {"$f18", RTYPE_FPU | 18}, \
2582 {"$f19", RTYPE_FPU | 19}, \
2583 {"$f20", RTYPE_FPU | 20}, \
2584 {"$f21", RTYPE_FPU | 21}, \
2585 {"$f22", RTYPE_FPU | 22}, \
2586 {"$f23", RTYPE_FPU | 23}, \
2587 {"$f24", RTYPE_FPU | 24}, \
2588 {"$f25", RTYPE_FPU | 25}, \
2589 {"$f26", RTYPE_FPU | 26}, \
2590 {"$f27", RTYPE_FPU | 27}, \
2591 {"$f28", RTYPE_FPU | 28}, \
2592 {"$f29", RTYPE_FPU | 29}, \
2593 {"$f30", RTYPE_FPU | 30}, \
2594 {"$f31", RTYPE_FPU | 31}
2596 #define FPU_CONDITION_CODE_NAMES \
2597 {"$fcc0", RTYPE_FCC | 0}, \
2598 {"$fcc1", RTYPE_FCC | 1}, \
2599 {"$fcc2", RTYPE_FCC | 2}, \
2600 {"$fcc3", RTYPE_FCC | 3}, \
2601 {"$fcc4", RTYPE_FCC | 4}, \
2602 {"$fcc5", RTYPE_FCC | 5}, \
2603 {"$fcc6", RTYPE_FCC | 6}, \
2604 {"$fcc7", RTYPE_FCC | 7}
2606 #define COPROC_CONDITION_CODE_NAMES \
2607 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2608 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2609 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2610 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2611 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2612 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2613 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2614 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2616 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2617 {"$a4", RTYPE_GP | 8}, \
2618 {"$a5", RTYPE_GP | 9}, \
2619 {"$a6", RTYPE_GP | 10}, \
2620 {"$a7", RTYPE_GP | 11}, \
2621 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2622 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2623 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2624 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2625 {"$t0", RTYPE_GP | 12}, \
2626 {"$t1", RTYPE_GP | 13}, \
2627 {"$t2", RTYPE_GP | 14}, \
2628 {"$t3", RTYPE_GP | 15}
2630 #define O32_SYMBOLIC_REGISTER_NAMES \
2631 {"$t0", RTYPE_GP | 8}, \
2632 {"$t1", RTYPE_GP | 9}, \
2633 {"$t2", RTYPE_GP | 10}, \
2634 {"$t3", RTYPE_GP | 11}, \
2635 {"$t4", RTYPE_GP | 12}, \
2636 {"$t5", RTYPE_GP | 13}, \
2637 {"$t6", RTYPE_GP | 14}, \
2638 {"$t7", RTYPE_GP | 15}, \
2639 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2640 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2641 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2642 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2644 /* Remaining symbolic register names */
2645 #define SYMBOLIC_REGISTER_NAMES \
2646 {"$zero", RTYPE_GP | 0}, \
2647 {"$at", RTYPE_GP | 1}, \
2648 {"$AT", RTYPE_GP | 1}, \
2649 {"$v0", RTYPE_GP | 2}, \
2650 {"$v1", RTYPE_GP | 3}, \
2651 {"$a0", RTYPE_GP | 4}, \
2652 {"$a1", RTYPE_GP | 5}, \
2653 {"$a2", RTYPE_GP | 6}, \
2654 {"$a3", RTYPE_GP | 7}, \
2655 {"$s0", RTYPE_GP | 16}, \
2656 {"$s1", RTYPE_GP | 17}, \
2657 {"$s2", RTYPE_GP | 18}, \
2658 {"$s3", RTYPE_GP | 19}, \
2659 {"$s4", RTYPE_GP | 20}, \
2660 {"$s5", RTYPE_GP | 21}, \
2661 {"$s6", RTYPE_GP | 22}, \
2662 {"$s7", RTYPE_GP | 23}, \
2663 {"$t8", RTYPE_GP | 24}, \
2664 {"$t9", RTYPE_GP | 25}, \
2665 {"$k0", RTYPE_GP | 26}, \
2666 {"$kt0", RTYPE_GP | 26}, \
2667 {"$k1", RTYPE_GP | 27}, \
2668 {"$kt1", RTYPE_GP | 27}, \
2669 {"$gp", RTYPE_GP | 28}, \
2670 {"$sp", RTYPE_GP | 29}, \
2671 {"$s8", RTYPE_GP | 30}, \
2672 {"$fp", RTYPE_GP | 30}, \
2673 {"$ra", RTYPE_GP | 31}
2675 #define MIPS16_SPECIAL_REGISTER_NAMES \
2676 {"$pc", RTYPE_PC | 0}
2678 #define MDMX_VECTOR_REGISTER_NAMES \
2679 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2680 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2681 {"$v2", RTYPE_VEC | 2}, \
2682 {"$v3", RTYPE_VEC | 3}, \
2683 {"$v4", RTYPE_VEC | 4}, \
2684 {"$v5", RTYPE_VEC | 5}, \
2685 {"$v6", RTYPE_VEC | 6}, \
2686 {"$v7", RTYPE_VEC | 7}, \
2687 {"$v8", RTYPE_VEC | 8}, \
2688 {"$v9", RTYPE_VEC | 9}, \
2689 {"$v10", RTYPE_VEC | 10}, \
2690 {"$v11", RTYPE_VEC | 11}, \
2691 {"$v12", RTYPE_VEC | 12}, \
2692 {"$v13", RTYPE_VEC | 13}, \
2693 {"$v14", RTYPE_VEC | 14}, \
2694 {"$v15", RTYPE_VEC | 15}, \
2695 {"$v16", RTYPE_VEC | 16}, \
2696 {"$v17", RTYPE_VEC | 17}, \
2697 {"$v18", RTYPE_VEC | 18}, \
2698 {"$v19", RTYPE_VEC | 19}, \
2699 {"$v20", RTYPE_VEC | 20}, \
2700 {"$v21", RTYPE_VEC | 21}, \
2701 {"$v22", RTYPE_VEC | 22}, \
2702 {"$v23", RTYPE_VEC | 23}, \
2703 {"$v24", RTYPE_VEC | 24}, \
2704 {"$v25", RTYPE_VEC | 25}, \
2705 {"$v26", RTYPE_VEC | 26}, \
2706 {"$v27", RTYPE_VEC | 27}, \
2707 {"$v28", RTYPE_VEC | 28}, \
2708 {"$v29", RTYPE_VEC | 29}, \
2709 {"$v30", RTYPE_VEC | 30}, \
2710 {"$v31", RTYPE_VEC | 31}
2712 #define R5900_I_NAMES \
2713 {"$I", RTYPE_R5900_I | 0}
2715 #define R5900_Q_NAMES \
2716 {"$Q", RTYPE_R5900_Q | 0}
2718 #define R5900_R_NAMES \
2719 {"$R", RTYPE_R5900_R | 0}
2721 #define R5900_ACC_NAMES \
2722 {"$ACC", RTYPE_R5900_ACC | 0 }
2724 #define MIPS_DSP_ACCUMULATOR_NAMES \
2725 {"$ac0", RTYPE_ACC | 0}, \
2726 {"$ac1", RTYPE_ACC | 1}, \
2727 {"$ac2", RTYPE_ACC | 2}, \
2728 {"$ac3", RTYPE_ACC | 3}
2730 static const struct regname reg_names[] = {
2731 GENERIC_REGISTER_NUMBERS,
2733 FPU_CONDITION_CODE_NAMES,
2734 COPROC_CONDITION_CODE_NAMES,
2736 /* The $txx registers depends on the abi,
2737 these will be added later into the symbol table from
2738 one of the tables below once mips_abi is set after
2739 parsing of arguments from the command line. */
2740 SYMBOLIC_REGISTER_NAMES,
2742 MIPS16_SPECIAL_REGISTER_NAMES,
2743 MDMX_VECTOR_REGISTER_NAMES,
2748 MIPS_DSP_ACCUMULATOR_NAMES,
2752 static const struct regname reg_names_o32[] = {
2753 O32_SYMBOLIC_REGISTER_NAMES,
2757 static const struct regname reg_names_n32n64[] = {
2758 N32N64_SYMBOLIC_REGISTER_NAMES,
2762 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2763 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2764 of these register symbols, return the associated vector register,
2765 otherwise return SYMVAL itself. */
2768 mips_prefer_vec_regno (unsigned int symval)
2770 if ((symval & -2) == (RTYPE_GP | 2))
2771 return RTYPE_VEC | (symval & 1);
2775 /* Return true if string [S, E) is a valid register name, storing its
2776 symbol value in *SYMVAL_PTR if so. */
2779 mips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr)
2784 /* Terminate name. */
2788 /* Look up the name. */
2789 symbol = symbol_find (s);
2792 if (!symbol || S_GET_SEGMENT (symbol) != reg_section)
2795 *symval_ptr = S_GET_VALUE (symbol);
2799 /* Return true if the string at *SPTR is a valid register name. Allow it
2800 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2803 When returning true, move *SPTR past the register, store the
2804 register's symbol value in *SYMVAL_PTR and the channel mask in
2805 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2806 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2807 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2810 mips_parse_register (char **sptr, unsigned int *symval_ptr,
2811 unsigned int *channels_ptr)
2815 unsigned int channels, symval, bit;
2817 /* Find end of name. */
2819 if (is_name_beginner (*e))
2821 while (is_part_of_name (*e))
2825 if (!mips_parse_register_1 (s, e, &symval))
2830 /* Eat characters from the end of the string that are valid
2831 channel suffixes. The preceding register must be $ACC or
2832 end with a digit, so there is no ambiguity. */
2835 for (q = "wzyx"; *q; q++, bit <<= 1)
2836 if (m > s && m[-1] == *q)
2843 || !mips_parse_register_1 (s, m, &symval)
2844 || (symval & (RTYPE_VI | RTYPE_VF | RTYPE_R5900_ACC)) == 0)
2849 *symval_ptr = symval;
2851 *channels_ptr = channels;
2855 /* Check if SPTR points at a valid register specifier according to TYPES.
2856 If so, then return 1, advance S to consume the specifier and store
2857 the register's number in REGNOP, otherwise return 0. */
2860 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2864 if (mips_parse_register (s, ®no, NULL))
2866 if (types & RTYPE_VEC)
2867 regno = mips_prefer_vec_regno (regno);
2876 as_warn (_("unrecognized register name `%s'"), *s);
2881 return regno <= RNUM_MASK;
2884 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2885 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2888 mips_parse_vu0_channels (char *s, unsigned int *channels)
2893 for (i = 0; i < 4; i++)
2894 if (*s == "xyzw"[i])
2896 *channels |= 1 << (3 - i);
2902 /* Token types for parsed operand lists. */
2903 enum mips_operand_token_type {
2904 /* A plain register, e.g. $f2. */
2907 /* A 4-bit XYZW channel mask. */
2910 /* A constant vector index, e.g. [1]. */
2913 /* A register vector index, e.g. [$2]. */
2916 /* A continuous range of registers, e.g. $s0-$s4. */
2919 /* A (possibly relocated) expression. */
2922 /* A floating-point value. */
2925 /* A single character. This can be '(', ')' or ',', but '(' only appears
2929 /* A doubled character, either "--" or "++". */
2932 /* The end of the operand list. */
2936 /* A parsed operand token. */
2937 struct mips_operand_token
2939 /* The type of token. */
2940 enum mips_operand_token_type type;
2943 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
2946 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
2947 unsigned int channels;
2949 /* The integer value of an OT_INTEGER_INDEX. */
2952 /* The two register symbol values involved in an OT_REG_RANGE. */
2954 unsigned int regno1;
2955 unsigned int regno2;
2958 /* The value of an OT_INTEGER. The value is represented as an
2959 expression and the relocation operators that were applied to
2960 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2961 relocation operators were used. */
2964 bfd_reloc_code_real_type relocs[3];
2967 /* The binary data for an OT_FLOAT constant, and the number of bytes
2970 unsigned char data[8];
2974 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
2979 /* An obstack used to construct lists of mips_operand_tokens. */
2980 static struct obstack mips_operand_tokens;
2982 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
2985 mips_add_token (struct mips_operand_token *token,
2986 enum mips_operand_token_type type)
2989 obstack_grow (&mips_operand_tokens, token, sizeof (*token));
2992 /* Check whether S is '(' followed by a register name. Add OT_CHAR
2993 and OT_REG tokens for them if so, and return a pointer to the first
2994 unconsumed character. Return null otherwise. */
2997 mips_parse_base_start (char *s)
2999 struct mips_operand_token token;
3000 unsigned int regno, channels;
3001 bfd_boolean decrement_p;
3007 SKIP_SPACE_TABS (s);
3009 /* Only match "--" as part of a base expression. In other contexts "--X"
3010 is a double negative. */
3011 decrement_p = (s[0] == '-' && s[1] == '-');
3015 SKIP_SPACE_TABS (s);
3018 /* Allow a channel specifier because that leads to better error messages
3019 than treating something like "$vf0x++" as an expression. */
3020 if (!mips_parse_register (&s, ®no, &channels))
3024 mips_add_token (&token, OT_CHAR);
3029 mips_add_token (&token, OT_DOUBLE_CHAR);
3032 token.u.regno = regno;
3033 mips_add_token (&token, OT_REG);
3037 token.u.channels = channels;
3038 mips_add_token (&token, OT_CHANNELS);
3041 /* For consistency, only match "++" as part of base expressions too. */
3042 SKIP_SPACE_TABS (s);
3043 if (s[0] == '+' && s[1] == '+')
3047 mips_add_token (&token, OT_DOUBLE_CHAR);
3053 /* Parse one or more tokens from S. Return a pointer to the first
3054 unconsumed character on success. Return null if an error was found
3055 and store the error text in insn_error. FLOAT_FORMAT is as for
3056 mips_parse_arguments. */
3059 mips_parse_argument_token (char *s, char float_format)
3061 char *end, *save_in;
3063 unsigned int regno1, regno2, channels;
3064 struct mips_operand_token token;
3066 /* First look for "($reg", since we want to treat that as an
3067 OT_CHAR and OT_REG rather than an expression. */
3068 end = mips_parse_base_start (s);
3072 /* Handle other characters that end up as OT_CHARs. */
3073 if (*s == ')' || *s == ',')
3076 mips_add_token (&token, OT_CHAR);
3081 /* Handle tokens that start with a register. */
3082 if (mips_parse_register (&s, ®no1, &channels))
3086 /* A register and a VU0 channel suffix. */
3087 token.u.regno = regno1;
3088 mips_add_token (&token, OT_REG);
3090 token.u.channels = channels;
3091 mips_add_token (&token, OT_CHANNELS);
3095 SKIP_SPACE_TABS (s);
3098 /* A register range. */
3100 SKIP_SPACE_TABS (s);
3101 if (!mips_parse_register (&s, ®no2, NULL))
3103 set_insn_error (0, _("invalid register range"));
3107 token.u.reg_range.regno1 = regno1;
3108 token.u.reg_range.regno2 = regno2;
3109 mips_add_token (&token, OT_REG_RANGE);
3113 /* Add the register itself. */
3114 token.u.regno = regno1;
3115 mips_add_token (&token, OT_REG);
3117 /* Check for a vector index. */
3121 SKIP_SPACE_TABS (s);
3122 if (mips_parse_register (&s, &token.u.regno, NULL))
3123 mips_add_token (&token, OT_REG_INDEX);
3126 expressionS element;
3128 my_getExpression (&element, s);
3129 if (element.X_op != O_constant)
3131 set_insn_error (0, _("vector element must be constant"));
3135 token.u.index = element.X_add_number;
3136 mips_add_token (&token, OT_INTEGER_INDEX);
3138 SKIP_SPACE_TABS (s);
3141 set_insn_error (0, _("missing `]'"));
3151 /* First try to treat expressions as floats. */
3152 save_in = input_line_pointer;
3153 input_line_pointer = s;
3154 err = md_atof (float_format, (char *) token.u.flt.data,
3155 &token.u.flt.length);
3156 end = input_line_pointer;
3157 input_line_pointer = save_in;
3160 set_insn_error (0, err);
3165 mips_add_token (&token, OT_FLOAT);
3170 /* Treat everything else as an integer expression. */
3171 token.u.integer.relocs[0] = BFD_RELOC_UNUSED;
3172 token.u.integer.relocs[1] = BFD_RELOC_UNUSED;
3173 token.u.integer.relocs[2] = BFD_RELOC_UNUSED;
3174 my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s);
3176 mips_add_token (&token, OT_INTEGER);
3180 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3181 if expressions should be treated as 32-bit floating-point constants,
3182 'd' if they should be treated as 64-bit floating-point constants,
3183 or 0 if they should be treated as integer expressions (the usual case).
3185 Return a list of tokens on success, otherwise return 0. The caller
3186 must obstack_free the list after use. */
3188 static struct mips_operand_token *
3189 mips_parse_arguments (char *s, char float_format)
3191 struct mips_operand_token token;
3193 SKIP_SPACE_TABS (s);
3196 s = mips_parse_argument_token (s, float_format);
3199 obstack_free (&mips_operand_tokens,
3200 obstack_finish (&mips_operand_tokens));
3203 SKIP_SPACE_TABS (s);
3205 mips_add_token (&token, OT_END);
3206 return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens);
3209 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3210 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3213 is_opcode_valid (const struct mips_opcode *mo)
3215 int isa = mips_opts.isa;
3216 int ase = mips_opts.ase;
3220 if (ISA_HAS_64BIT_REGS (isa))
3221 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
3222 if ((ase & mips_ases[i].flags) == mips_ases[i].flags)
3223 ase |= mips_ases[i].flags64;
3225 if (!opcode_is_member (mo, isa, ase, mips_opts.arch))
3228 /* Check whether the instruction or macro requires single-precision or
3229 double-precision floating-point support. Note that this information is
3230 stored differently in the opcode table for insns and macros. */
3231 if (mo->pinfo == INSN_MACRO)
3233 fp_s = mo->pinfo2 & INSN2_M_FP_S;
3234 fp_d = mo->pinfo2 & INSN2_M_FP_D;
3238 fp_s = mo->pinfo & FP_S;
3239 fp_d = mo->pinfo & FP_D;
3242 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
3245 if (fp_s && mips_opts.soft_float)
3251 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3252 selected ISA and architecture. */
3255 is_opcode_valid_16 (const struct mips_opcode *mo)
3257 return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch);
3260 /* Return TRUE if the size of the microMIPS opcode MO matches one
3261 explicitly requested. Always TRUE in the standard MIPS mode.
3262 Use is_size_valid_16 for MIPS16 opcodes. */
3265 is_size_valid (const struct mips_opcode *mo)
3267 if (!mips_opts.micromips)
3270 if (mips_opts.insn32)
3272 if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4)
3274 if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0)
3277 if (!forced_insn_length)
3279 if (mo->pinfo == INSN_MACRO)
3281 return forced_insn_length == micromips_insn_length (mo);
3284 /* Return TRUE if the size of the MIPS16 opcode MO matches one
3285 explicitly requested. */
3288 is_size_valid_16 (const struct mips_opcode *mo)
3290 if (!forced_insn_length)
3292 if (mo->pinfo == INSN_MACRO)
3294 if (forced_insn_length == 2 && mips_opcode_32bit_p (mo))
3296 if (forced_insn_length == 4 && (mo->pinfo2 & INSN2_SHORT_ONLY))
3301 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3302 of the preceding instruction. Always TRUE in the standard MIPS mode.
3304 We don't accept macros in 16-bit delay slots to avoid a case where
3305 a macro expansion fails because it relies on a preceding 32-bit real
3306 instruction to have matched and does not handle the operands correctly.
3307 The only macros that may expand to 16-bit instructions are JAL that
3308 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3309 and BGT (that likewise cannot be placed in a delay slot) that decay to
3310 a NOP. In all these cases the macros precede any corresponding real
3311 instruction definitions in the opcode table, so they will match in the
3312 second pass where the size of the delay slot is ignored and therefore
3313 produce correct code. */
3316 is_delay_slot_valid (const struct mips_opcode *mo)
3318 if (!mips_opts.micromips)
3321 if (mo->pinfo == INSN_MACRO)
3322 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0;
3323 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
3324 && micromips_insn_length (mo) != 4)
3326 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
3327 && micromips_insn_length (mo) != 2)
3333 /* For consistency checking, verify that all bits of OPCODE are specified
3334 either by the match/mask part of the instruction definition, or by the
3335 operand list. Also build up a list of operands in OPERANDS.
3337 INSN_BITS says which bits of the instruction are significant.
3338 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3339 provides the mips_operand description of each operand. DECODE_OPERAND
3340 is null for MIPS16 instructions. */
3343 validate_mips_insn (const struct mips_opcode *opcode,
3344 unsigned long insn_bits,
3345 const struct mips_operand *(*decode_operand) (const char *),
3346 struct mips_operand_array *operands)
3349 unsigned long used_bits, doubled, undefined, opno, mask;
3350 const struct mips_operand *operand;
3352 mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask);
3353 if ((mask & opcode->match) != opcode->match)
3355 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3356 opcode->name, opcode->args);
3361 if (opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX)
3362 used_bits = mips_insert_operand (&mips_vu0_channel_mask, used_bits, -1);
3363 for (s = opcode->args; *s; ++s)
3376 if (!decode_operand)
3377 operand = decode_mips16_operand (*s, mips_opcode_32bit_p (opcode));
3379 operand = decode_operand (s);
3380 if (!operand && opcode->pinfo != INSN_MACRO)
3382 as_bad (_("internal: unknown operand type: %s %s"),
3383 opcode->name, opcode->args);
3386 gas_assert (opno < MAX_OPERANDS);
3387 operands->operand[opno] = operand;
3388 if (operand && operand->type != OP_VU0_MATCH_SUFFIX)
3390 used_bits = mips_insert_operand (operand, used_bits, -1);
3391 if (operand->type == OP_MDMX_IMM_REG)
3392 /* Bit 5 is the format selector (OB vs QH). The opcode table
3393 has separate entries for each format. */
3394 used_bits &= ~(1 << (operand->lsb + 5));
3395 if (operand->type == OP_ENTRY_EXIT_LIST)
3396 used_bits &= ~(mask & 0x700);
3398 /* Skip prefix characters. */
3399 if (decode_operand && (*s == '+' || *s == 'm' || *s == '-'))
3404 doubled = used_bits & mask & insn_bits;
3407 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3408 " %s %s"), doubled, opcode->name, opcode->args);
3412 undefined = ~used_bits & insn_bits;
3413 if (opcode->pinfo != INSN_MACRO && undefined)
3415 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3416 undefined, opcode->name, opcode->args);
3419 used_bits &= ~insn_bits;
3422 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3423 used_bits, opcode->name, opcode->args);
3429 /* The MIPS16 version of validate_mips_insn. */
3432 validate_mips16_insn (const struct mips_opcode *opcode,
3433 struct mips_operand_array *operands)
3435 unsigned long insn_bits = mips_opcode_32bit_p (opcode) ? 0xffffffff : 0xffff;
3437 return validate_mips_insn (opcode, insn_bits, 0, operands);
3440 /* The microMIPS version of validate_mips_insn. */
3443 validate_micromips_insn (const struct mips_opcode *opc,
3444 struct mips_operand_array *operands)
3446 unsigned long insn_bits;
3447 unsigned long major;
3448 unsigned int length;
3450 if (opc->pinfo == INSN_MACRO)
3451 return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand,
3454 length = micromips_insn_length (opc);
3455 if (length != 2 && length != 4)
3457 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3458 "%s %s"), length, opc->name, opc->args);
3461 major = opc->match >> (10 + 8 * (length - 2));
3462 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
3463 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
3465 as_bad (_("internal error: bad microMIPS opcode "
3466 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
3470 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3471 insn_bits = 1 << 4 * length;
3472 insn_bits <<= 4 * length;
3474 return validate_mips_insn (opc, insn_bits, decode_micromips_operand,
3478 /* This function is called once, at assembler startup time. It should set up
3479 all the tables, etc. that the MD part of the assembler will need. */
3484 const char *retval = NULL;
3488 if (mips_pic != NO_PIC)
3490 if (g_switch_seen && g_switch_value != 0)
3491 as_bad (_("-G may not be used in position-independent code"));
3494 else if (mips_abicalls)
3496 if (g_switch_seen && g_switch_value != 0)
3497 as_bad (_("-G may not be used with abicalls"));
3501 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch))
3502 as_warn (_("could not set architecture and machine"));
3504 op_hash = hash_new ();
3506 mips_operands = XCNEWVEC (struct mips_operand_array, NUMOPCODES);
3507 for (i = 0; i < NUMOPCODES;)
3509 const char *name = mips_opcodes[i].name;
3511 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
3514 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
3515 mips_opcodes[i].name, retval);
3516 /* Probably a memory allocation problem? Give up now. */
3517 as_fatal (_("broken assembler, no assembly attempted"));
3521 if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff,
3522 decode_mips_operand, &mips_operands[i]))
3524 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3526 create_insn (&nop_insn, mips_opcodes + i);
3527 if (mips_fix_loongson2f_nop)
3528 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
3529 nop_insn.fixed_p = 1;
3533 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
3536 mips16_op_hash = hash_new ();
3537 mips16_operands = XCNEWVEC (struct mips_operand_array,
3538 bfd_mips16_num_opcodes);
3541 while (i < bfd_mips16_num_opcodes)
3543 const char *name = mips16_opcodes[i].name;
3545 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
3547 as_fatal (_("internal: can't hash `%s': %s"),
3548 mips16_opcodes[i].name, retval);
3551 if (!validate_mips16_insn (&mips16_opcodes[i], &mips16_operands[i]))
3553 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3555 create_insn (&mips16_nop_insn, mips16_opcodes + i);
3556 mips16_nop_insn.fixed_p = 1;
3560 while (i < bfd_mips16_num_opcodes
3561 && strcmp (mips16_opcodes[i].name, name) == 0);
3564 micromips_op_hash = hash_new ();
3565 micromips_operands = XCNEWVEC (struct mips_operand_array,
3566 bfd_micromips_num_opcodes);
3569 while (i < bfd_micromips_num_opcodes)
3571 const char *name = micromips_opcodes[i].name;
3573 retval = hash_insert (micromips_op_hash, name,
3574 (void *) µmips_opcodes[i]);
3576 as_fatal (_("internal: can't hash `%s': %s"),
3577 micromips_opcodes[i].name, retval);
3580 struct mips_cl_insn *micromips_nop_insn;
3582 if (!validate_micromips_insn (µmips_opcodes[i],
3583 µmips_operands[i]))
3586 if (micromips_opcodes[i].pinfo != INSN_MACRO)
3588 if (micromips_insn_length (micromips_opcodes + i) == 2)
3589 micromips_nop_insn = µmips_nop16_insn;
3590 else if (micromips_insn_length (micromips_opcodes + i) == 4)
3591 micromips_nop_insn = µmips_nop32_insn;
3595 if (micromips_nop_insn->insn_mo == NULL
3596 && strcmp (name, "nop") == 0)
3598 create_insn (micromips_nop_insn, micromips_opcodes + i);
3599 micromips_nop_insn->fixed_p = 1;
3603 while (++i < bfd_micromips_num_opcodes
3604 && strcmp (micromips_opcodes[i].name, name) == 0);
3608 as_fatal (_("broken assembler, no assembly attempted"));
3610 /* We add all the general register names to the symbol table. This
3611 helps us detect invalid uses of them. */
3612 for (i = 0; reg_names[i].name; i++)
3613 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
3614 reg_names[i].num, /* & RNUM_MASK, */
3615 &zero_address_frag));
3617 for (i = 0; reg_names_n32n64[i].name; i++)
3618 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
3619 reg_names_n32n64[i].num, /* & RNUM_MASK, */
3620 &zero_address_frag));
3622 for (i = 0; reg_names_o32[i].name; i++)
3623 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
3624 reg_names_o32[i].num, /* & RNUM_MASK, */
3625 &zero_address_frag));
3627 for (i = 0; i < 32; i++)
3631 /* R5900 VU0 floating-point register. */
3632 sprintf (regname, "$vf%d", i);
3633 symbol_table_insert (symbol_new (regname, reg_section,
3634 RTYPE_VF | i, &zero_address_frag));
3636 /* R5900 VU0 integer register. */
3637 sprintf (regname, "$vi%d", i);
3638 symbol_table_insert (symbol_new (regname, reg_section,
3639 RTYPE_VI | i, &zero_address_frag));
3642 sprintf (regname, "$w%d", i);
3643 symbol_table_insert (symbol_new (regname, reg_section,
3644 RTYPE_MSA | i, &zero_address_frag));
3647 obstack_init (&mips_operand_tokens);
3649 mips_no_prev_insn ();
3652 mips_cprmask[0] = 0;
3653 mips_cprmask[1] = 0;
3654 mips_cprmask[2] = 0;
3655 mips_cprmask[3] = 0;
3657 /* set the default alignment for the text section (2**2) */
3658 record_alignment (text_section, 2);
3660 bfd_set_gp_size (stdoutput, g_switch_value);
3662 /* On a native system other than VxWorks, sections must be aligned
3663 to 16 byte boundaries. When configured for an embedded ELF
3664 target, we don't bother. */
3665 if (strncmp (TARGET_OS, "elf", 3) != 0
3666 && strncmp (TARGET_OS, "vxworks", 7) != 0)
3668 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
3669 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
3670 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
3673 /* Create a .reginfo section for register masks and a .mdebug
3674 section for debugging information. */
3682 subseg = now_subseg;
3684 /* The ABI says this section should be loaded so that the
3685 running program can access it. However, we don't load it
3686 if we are configured for an embedded target */
3687 flags = SEC_READONLY | SEC_DATA;
3688 if (strncmp (TARGET_OS, "elf", 3) != 0)
3689 flags |= SEC_ALLOC | SEC_LOAD;
3691 if (mips_abi != N64_ABI)
3693 sec = subseg_new (".reginfo", (subsegT) 0);
3695 bfd_set_section_flags (stdoutput, sec, flags);
3696 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
3698 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
3702 /* The 64-bit ABI uses a .MIPS.options section rather than
3703 .reginfo section. */
3704 sec = subseg_new (".MIPS.options", (subsegT) 0);
3705 bfd_set_section_flags (stdoutput, sec, flags);
3706 bfd_set_section_alignment (stdoutput, sec, 3);
3708 /* Set up the option header. */
3710 Elf_Internal_Options opthdr;
3713 opthdr.kind = ODK_REGINFO;
3714 opthdr.size = (sizeof (Elf_External_Options)
3715 + sizeof (Elf64_External_RegInfo));
3718 f = frag_more (sizeof (Elf_External_Options));
3719 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
3720 (Elf_External_Options *) f);
3722 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
3726 sec = subseg_new (".MIPS.abiflags", (subsegT) 0);
3727 bfd_set_section_flags (stdoutput, sec,
3728 SEC_READONLY | SEC_DATA | SEC_ALLOC | SEC_LOAD);
3729 bfd_set_section_alignment (stdoutput, sec, 3);
3730 mips_flags_frag = frag_more (sizeof (Elf_External_ABIFlags_v0));
3732 if (ECOFF_DEBUGGING)
3734 sec = subseg_new (".mdebug", (subsegT) 0);
3735 (void) bfd_set_section_flags (stdoutput, sec,
3736 SEC_HAS_CONTENTS | SEC_READONLY);
3737 (void) bfd_set_section_alignment (stdoutput, sec, 2);
3739 else if (mips_flag_pdr)
3741 pdr_seg = subseg_new (".pdr", (subsegT) 0);
3742 (void) bfd_set_section_flags (stdoutput, pdr_seg,
3743 SEC_READONLY | SEC_RELOC
3745 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
3748 subseg_set (seg, subseg);
3751 if (mips_fix_vr4120)
3752 init_vr4120_conflicts ();
3756 fpabi_incompatible_with (int fpabi, const char *what)
3758 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3759 Tag_GNU_MIPS_ABI_FP, fpabi, what);
3763 fpabi_requires (int fpabi, const char *what)
3765 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3766 Tag_GNU_MIPS_ABI_FP, fpabi, what);
3769 /* Check -mabi and register sizes against the specified FP ABI. */
3771 check_fpabi (int fpabi)
3775 case Val_GNU_MIPS_ABI_FP_DOUBLE:
3776 if (file_mips_opts.soft_float)
3777 fpabi_incompatible_with (fpabi, "softfloat");
3778 else if (file_mips_opts.single_float)
3779 fpabi_incompatible_with (fpabi, "singlefloat");
3780 if (file_mips_opts.gp == 64 && file_mips_opts.fp == 32)
3781 fpabi_incompatible_with (fpabi, "gp=64 fp=32");
3782 else if (file_mips_opts.gp == 32 && file_mips_opts.fp == 64)
3783 fpabi_incompatible_with (fpabi, "gp=32 fp=64");
3786 case Val_GNU_MIPS_ABI_FP_XX:
3787 if (mips_abi != O32_ABI)
3788 fpabi_requires (fpabi, "-mabi=32");
3789 else if (file_mips_opts.soft_float)
3790 fpabi_incompatible_with (fpabi, "softfloat");
3791 else if (file_mips_opts.single_float)
3792 fpabi_incompatible_with (fpabi, "singlefloat");
3793 else if (file_mips_opts.fp != 0)
3794 fpabi_requires (fpabi, "fp=xx");
3797 case Val_GNU_MIPS_ABI_FP_64A:
3798 case Val_GNU_MIPS_ABI_FP_64:
3799 if (mips_abi != O32_ABI)
3800 fpabi_requires (fpabi, "-mabi=32");
3801 else if (file_mips_opts.soft_float)
3802 fpabi_incompatible_with (fpabi, "softfloat");
3803 else if (file_mips_opts.single_float)
3804 fpabi_incompatible_with (fpabi, "singlefloat");
3805 else if (file_mips_opts.fp != 64)
3806 fpabi_requires (fpabi, "fp=64");
3807 else if (fpabi == Val_GNU_MIPS_ABI_FP_64 && !file_mips_opts.oddspreg)
3808 fpabi_incompatible_with (fpabi, "nooddspreg");
3809 else if (fpabi == Val_GNU_MIPS_ABI_FP_64A && file_mips_opts.oddspreg)
3810 fpabi_requires (fpabi, "nooddspreg");
3813 case Val_GNU_MIPS_ABI_FP_SINGLE:
3814 if (file_mips_opts.soft_float)
3815 fpabi_incompatible_with (fpabi, "softfloat");
3816 else if (!file_mips_opts.single_float)
3817 fpabi_requires (fpabi, "singlefloat");
3820 case Val_GNU_MIPS_ABI_FP_SOFT:
3821 if (!file_mips_opts.soft_float)
3822 fpabi_requires (fpabi, "softfloat");
3825 case Val_GNU_MIPS_ABI_FP_OLD_64:
3826 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
3827 Tag_GNU_MIPS_ABI_FP, fpabi);
3830 case Val_GNU_MIPS_ABI_FP_NAN2008:
3831 /* Silently ignore compatibility value. */
3835 as_warn (_(".gnu_attribute %d,%d is not a recognized"
3836 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP, fpabi);
3841 /* Perform consistency checks on the current options. */
3844 mips_check_options (struct mips_set_options *opts, bfd_boolean abi_checks)
3846 /* Check the size of integer registers agrees with the ABI and ISA. */
3847 if (opts->gp == 64 && !ISA_HAS_64BIT_REGS (opts->isa))
3848 as_bad (_("`gp=64' used with a 32-bit processor"));
3850 && opts->gp == 32 && ABI_NEEDS_64BIT_REGS (mips_abi))
3851 as_bad (_("`gp=32' used with a 64-bit ABI"));
3853 && opts->gp == 64 && ABI_NEEDS_32BIT_REGS (mips_abi))
3854 as_bad (_("`gp=64' used with a 32-bit ABI"));
3856 /* Check the size of the float registers agrees with the ABI and ISA. */
3860 if (!CPU_HAS_LDC1_SDC1 (opts->arch))
3861 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
3862 else if (opts->single_float == 1)
3863 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
3866 if (!ISA_HAS_64BIT_FPRS (opts->isa))
3867 as_bad (_("`fp=64' used with a 32-bit fpu"));
3869 && ABI_NEEDS_32BIT_REGS (mips_abi)
3870 && !ISA_HAS_MXHC1 (opts->isa))
3871 as_warn (_("`fp=64' used with a 32-bit ABI"));
3875 && ABI_NEEDS_64BIT_REGS (mips_abi))
3876 as_warn (_("`fp=32' used with a 64-bit ABI"));
3877 if (ISA_IS_R6 (opts->isa) && opts->single_float == 0)
3878 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
3881 as_bad (_("Unknown size of floating point registers"));
3885 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !opts->oddspreg)
3886 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
3888 if (opts->micromips == 1 && opts->mips16 == 1)
3889 as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips");
3890 else if (ISA_IS_R6 (opts->isa)
3891 && (opts->micromips == 1
3892 || opts->mips16 == 1))
3893 as_fatal (_("`%s' cannot be used with `%s'"),
3894 opts->micromips ? "micromips" : "mips16",
3895 mips_cpu_info_from_isa (opts->isa)->name);
3897 if (ISA_IS_R6 (opts->isa) && mips_relax_branch)
3898 as_fatal (_("branch relaxation is not supported in `%s'"),
3899 mips_cpu_info_from_isa (opts->isa)->name);
3902 /* Perform consistency checks on the module level options exactly once.
3903 This is a deferred check that happens:
3904 at the first .set directive
3905 or, at the first pseudo op that generates code (inc .dc.a)
3906 or, at the first instruction
3910 file_mips_check_options (void)
3912 const struct mips_cpu_info *arch_info = 0;
3914 if (file_mips_opts_checked)
3917 /* The following code determines the register size.
3918 Similar code was added to GCC 3.3 (see override_options() in
3919 config/mips/mips.c). The GAS and GCC code should be kept in sync
3920 as much as possible. */
3922 if (file_mips_opts.gp < 0)
3924 /* Infer the integer register size from the ABI and processor.
3925 Restrict ourselves to 32-bit registers if that's all the
3926 processor has, or if the ABI cannot handle 64-bit registers. */
3927 file_mips_opts.gp = (ABI_NEEDS_32BIT_REGS (mips_abi)
3928 || !ISA_HAS_64BIT_REGS (file_mips_opts.isa))
3932 if (file_mips_opts.fp < 0)
3934 /* No user specified float register size.
3935 ??? GAS treats single-float processors as though they had 64-bit
3936 float registers (although it complains when double-precision
3937 instructions are used). As things stand, saying they have 32-bit
3938 registers would lead to spurious "register must be even" messages.
3939 So here we assume float registers are never smaller than the
3941 if (file_mips_opts.gp == 64)
3942 /* 64-bit integer registers implies 64-bit float registers. */
3943 file_mips_opts.fp = 64;
3944 else if ((file_mips_opts.ase & FP64_ASES)
3945 && ISA_HAS_64BIT_FPRS (file_mips_opts.isa))
3946 /* Handle ASEs that require 64-bit float registers, if possible. */
3947 file_mips_opts.fp = 64;
3948 else if (ISA_IS_R6 (mips_opts.isa))
3949 /* R6 implies 64-bit float registers. */
3950 file_mips_opts.fp = 64;
3952 /* 32-bit float registers. */
3953 file_mips_opts.fp = 32;
3956 arch_info = mips_cpu_info_from_arch (file_mips_opts.arch);
3958 /* Disable operations on odd-numbered floating-point registers by default
3959 when using the FPXX ABI. */
3960 if (file_mips_opts.oddspreg < 0)
3962 if (file_mips_opts.fp == 0)
3963 file_mips_opts.oddspreg = 0;
3965 file_mips_opts.oddspreg = 1;
3968 /* End of GCC-shared inference code. */
3970 /* This flag is set when we have a 64-bit capable CPU but use only
3971 32-bit wide registers. Note that EABI does not use it. */
3972 if (ISA_HAS_64BIT_REGS (file_mips_opts.isa)
3973 && ((mips_abi == NO_ABI && file_mips_opts.gp == 32)
3974 || mips_abi == O32_ABI))
3977 if (file_mips_opts.isa == ISA_MIPS1 && mips_trap)
3978 as_bad (_("trap exception not supported at ISA 1"));
3980 /* If the selected architecture includes support for ASEs, enable
3981 generation of code for them. */
3982 if (file_mips_opts.mips16 == -1)
3983 file_mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_opts.arch)) ? 1 : 0;
3984 if (file_mips_opts.micromips == -1)
3985 file_mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_opts.arch))
3988 if (mips_nan2008 == -1)
3989 mips_nan2008 = (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) ? 0 : 1;
3990 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts.isa) && mips_nan2008 == 0)
3991 as_fatal (_("`%s' does not support legacy NaN"),
3992 mips_cpu_info_from_arch (file_mips_opts.arch)->name);
3994 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
3995 being selected implicitly. */
3996 if (file_mips_opts.fp != 64)
3997 file_ase_explicit |= ASE_MIPS3D | ASE_MDMX | ASE_MSA;
3999 /* If the user didn't explicitly select or deselect a particular ASE,
4000 use the default setting for the CPU. */
4001 file_mips_opts.ase |= (arch_info->ase & ~file_ase_explicit);
4003 /* Set up the current options. These may change throughout assembly. */
4004 mips_opts = file_mips_opts;
4006 mips_check_isa_supports_ases ();
4007 mips_check_options (&file_mips_opts, TRUE);
4008 file_mips_opts_checked = TRUE;
4010 if (!bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch))
4011 as_warn (_("could not set architecture and machine"));
4015 md_assemble (char *str)
4017 struct mips_cl_insn insn;
4018 bfd_reloc_code_real_type unused_reloc[3]
4019 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
4021 file_mips_check_options ();
4023 imm_expr.X_op = O_absent;
4024 offset_expr.X_op = O_absent;
4025 offset_reloc[0] = BFD_RELOC_UNUSED;
4026 offset_reloc[1] = BFD_RELOC_UNUSED;
4027 offset_reloc[2] = BFD_RELOC_UNUSED;
4029 mips_mark_labels ();
4030 mips_assembling_insn = TRUE;
4031 clear_insn_error ();
4033 if (mips_opts.mips16)
4034 mips16_ip (str, &insn);
4037 mips_ip (str, &insn);
4038 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4039 str, insn.insn_opcode));
4043 report_insn_error (str);
4044 else if (insn.insn_mo->pinfo == INSN_MACRO)
4047 if (mips_opts.mips16)
4048 mips16_macro (&insn);
4055 if (offset_expr.X_op != O_absent)
4056 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
4058 append_insn (&insn, NULL, unused_reloc, FALSE);
4061 mips_assembling_insn = FALSE;
4064 /* Convenience functions for abstracting away the differences between
4065 MIPS16 and non-MIPS16 relocations. */
4067 static inline bfd_boolean
4068 mips16_reloc_p (bfd_reloc_code_real_type reloc)
4072 case BFD_RELOC_MIPS16_JMP:
4073 case BFD_RELOC_MIPS16_GPREL:
4074 case BFD_RELOC_MIPS16_GOT16:
4075 case BFD_RELOC_MIPS16_CALL16:
4076 case BFD_RELOC_MIPS16_HI16_S:
4077 case BFD_RELOC_MIPS16_HI16:
4078 case BFD_RELOC_MIPS16_LO16:
4079 case BFD_RELOC_MIPS16_16_PCREL_S1:
4087 static inline bfd_boolean
4088 micromips_reloc_p (bfd_reloc_code_real_type reloc)
4092 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
4093 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
4094 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
4095 case BFD_RELOC_MICROMIPS_GPREL16:
4096 case BFD_RELOC_MICROMIPS_JMP:
4097 case BFD_RELOC_MICROMIPS_HI16:
4098 case BFD_RELOC_MICROMIPS_HI16_S:
4099 case BFD_RELOC_MICROMIPS_LO16:
4100 case BFD_RELOC_MICROMIPS_LITERAL:
4101 case BFD_RELOC_MICROMIPS_GOT16:
4102 case BFD_RELOC_MICROMIPS_CALL16:
4103 case BFD_RELOC_MICROMIPS_GOT_HI16:
4104 case BFD_RELOC_MICROMIPS_GOT_LO16:
4105 case BFD_RELOC_MICROMIPS_CALL_HI16:
4106 case BFD_RELOC_MICROMIPS_CALL_LO16:
4107 case BFD_RELOC_MICROMIPS_SUB:
4108 case BFD_RELOC_MICROMIPS_GOT_PAGE:
4109 case BFD_RELOC_MICROMIPS_GOT_OFST:
4110 case BFD_RELOC_MICROMIPS_GOT_DISP:
4111 case BFD_RELOC_MICROMIPS_HIGHEST:
4112 case BFD_RELOC_MICROMIPS_HIGHER:
4113 case BFD_RELOC_MICROMIPS_SCN_DISP:
4114 case BFD_RELOC_MICROMIPS_JALR:
4122 static inline bfd_boolean
4123 jmp_reloc_p (bfd_reloc_code_real_type reloc)
4125 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
4128 static inline bfd_boolean
4129 b_reloc_p (bfd_reloc_code_real_type reloc)
4131 return (reloc == BFD_RELOC_MIPS_26_PCREL_S2
4132 || reloc == BFD_RELOC_MIPS_21_PCREL_S2
4133 || reloc == BFD_RELOC_16_PCREL_S2
4134 || reloc == BFD_RELOC_MIPS16_16_PCREL_S1
4135 || reloc == BFD_RELOC_MICROMIPS_16_PCREL_S1
4136 || reloc == BFD_RELOC_MICROMIPS_10_PCREL_S1
4137 || reloc == BFD_RELOC_MICROMIPS_7_PCREL_S1);
4140 static inline bfd_boolean
4141 got16_reloc_p (bfd_reloc_code_real_type reloc)
4143 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
4144 || reloc == BFD_RELOC_MICROMIPS_GOT16);
4147 static inline bfd_boolean
4148 hi16_reloc_p (bfd_reloc_code_real_type reloc)
4150 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
4151 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
4154 static inline bfd_boolean
4155 lo16_reloc_p (bfd_reloc_code_real_type reloc)
4157 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
4158 || reloc == BFD_RELOC_MICROMIPS_LO16);
4161 static inline bfd_boolean
4162 jalr_reloc_p (bfd_reloc_code_real_type reloc)
4164 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
4167 static inline bfd_boolean
4168 gprel16_reloc_p (bfd_reloc_code_real_type reloc)
4170 return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL
4171 || reloc == BFD_RELOC_MICROMIPS_GPREL16);
4174 /* Return true if RELOC is a PC-relative relocation that does not have
4175 full address range. */
4177 static inline bfd_boolean
4178 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc)
4182 case BFD_RELOC_16_PCREL_S2:
4183 case BFD_RELOC_MIPS16_16_PCREL_S1:
4184 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
4185 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
4186 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
4187 case BFD_RELOC_MIPS_21_PCREL_S2:
4188 case BFD_RELOC_MIPS_26_PCREL_S2:
4189 case BFD_RELOC_MIPS_18_PCREL_S3:
4190 case BFD_RELOC_MIPS_19_PCREL_S2:
4193 case BFD_RELOC_32_PCREL:
4194 case BFD_RELOC_HI16_S_PCREL:
4195 case BFD_RELOC_LO16_PCREL:
4196 return HAVE_64BIT_ADDRESSES;
4203 /* Return true if the given relocation might need a matching %lo().
4204 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4205 need a matching %lo() when applied to local symbols. */
4207 static inline bfd_boolean
4208 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
4210 return (HAVE_IN_PLACE_ADDENDS
4211 && (hi16_reloc_p (reloc)
4212 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4213 all GOT16 relocations evaluate to "G". */
4214 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
4217 /* Return the type of %lo() reloc needed by RELOC, given that
4218 reloc_needs_lo_p. */
4220 static inline bfd_reloc_code_real_type
4221 matching_lo_reloc (bfd_reloc_code_real_type reloc)
4223 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
4224 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
4228 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
4231 static inline bfd_boolean
4232 fixup_has_matching_lo_p (fixS *fixp)
4234 return (fixp->fx_next != NULL
4235 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
4236 && fixp->fx_addsy == fixp->fx_next->fx_addsy
4237 && fixp->fx_offset == fixp->fx_next->fx_offset);
4240 /* Move all labels in LABELS to the current insertion point. TEXT_P
4241 says whether the labels refer to text or data. */
4244 mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
4246 struct insn_label_list *l;
4249 for (l = labels; l != NULL; l = l->next)
4251 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
4252 symbol_set_frag (l->label, frag_now);
4253 val = (valueT) frag_now_fix ();
4254 /* MIPS16/microMIPS text labels are stored as odd. */
4255 if (text_p && HAVE_CODE_COMPRESSION)
4257 S_SET_VALUE (l->label, val);
4261 /* Move all labels in insn_labels to the current insertion point
4262 and treat them as text labels. */
4265 mips_move_text_labels (void)
4267 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
4271 s_is_linkonce (symbolS *sym, segT from_seg)
4273 bfd_boolean linkonce = FALSE;
4274 segT symseg = S_GET_SEGMENT (sym);
4276 if (symseg != from_seg && !S_IS_LOCAL (sym))
4278 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
4280 /* The GNU toolchain uses an extension for ELF: a section
4281 beginning with the magic string .gnu.linkonce is a
4282 linkonce section. */
4283 if (strncmp (segment_name (symseg), ".gnu.linkonce",
4284 sizeof ".gnu.linkonce" - 1) == 0)
4290 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
4291 linker to handle them specially, such as generating jalx instructions
4292 when needed. We also make them odd for the duration of the assembly,
4293 in order to generate the right sort of code. We will make them even
4294 in the adjust_symtab routine, while leaving them marked. This is
4295 convenient for the debugger and the disassembler. The linker knows
4296 to make them odd again. */
4299 mips_compressed_mark_label (symbolS *label)
4301 gas_assert (HAVE_CODE_COMPRESSION);
4303 if (mips_opts.mips16)
4304 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
4306 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
4307 if ((S_GET_VALUE (label) & 1) == 0
4308 /* Don't adjust the address if the label is global or weak, or
4309 in a link-once section, since we'll be emitting symbol reloc
4310 references to it which will be patched up by the linker, and
4311 the final value of the symbol may or may not be MIPS16/microMIPS. */
4312 && !S_IS_WEAK (label)
4313 && !S_IS_EXTERNAL (label)
4314 && !s_is_linkonce (label, now_seg))
4315 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
4318 /* Mark preceding MIPS16 or microMIPS instruction labels. */
4321 mips_compressed_mark_labels (void)
4323 struct insn_label_list *l;
4325 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next)
4326 mips_compressed_mark_label (l->label);
4329 /* End the current frag. Make it a variant frag and record the
4333 relax_close_frag (void)
4335 mips_macro_warning.first_frag = frag_now;
4336 frag_var (rs_machine_dependent, 0, 0,
4337 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
4338 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
4340 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
4341 mips_relax.first_fixup = 0;
4344 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
4345 See the comment above RELAX_ENCODE for more details. */
4348 relax_start (symbolS *symbol)
4350 gas_assert (mips_relax.sequence == 0);
4351 mips_relax.sequence = 1;
4352 mips_relax.symbol = symbol;
4355 /* Start generating the second version of a relaxable sequence.
4356 See the comment above RELAX_ENCODE for more details. */
4361 gas_assert (mips_relax.sequence == 1);
4362 mips_relax.sequence = 2;
4365 /* End the current relaxable sequence. */
4370 gas_assert (mips_relax.sequence == 2);
4371 relax_close_frag ();
4372 mips_relax.sequence = 0;
4375 /* Return true if IP is a delayed branch or jump. */
4377 static inline bfd_boolean
4378 delayed_branch_p (const struct mips_cl_insn *ip)
4380 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
4381 | INSN_COND_BRANCH_DELAY
4382 | INSN_COND_BRANCH_LIKELY)) != 0;
4385 /* Return true if IP is a compact branch or jump. */
4387 static inline bfd_boolean
4388 compact_branch_p (const struct mips_cl_insn *ip)
4390 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
4391 | INSN2_COND_BRANCH)) != 0;
4394 /* Return true if IP is an unconditional branch or jump. */
4396 static inline bfd_boolean
4397 uncond_branch_p (const struct mips_cl_insn *ip)
4399 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
4400 || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0);
4403 /* Return true if IP is a branch-likely instruction. */
4405 static inline bfd_boolean
4406 branch_likely_p (const struct mips_cl_insn *ip)
4408 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
4411 /* Return the type of nop that should be used to fill the delay slot
4412 of delayed branch IP. */
4414 static struct mips_cl_insn *
4415 get_delay_slot_nop (const struct mips_cl_insn *ip)
4417 if (mips_opts.micromips
4418 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
4419 return µmips_nop32_insn;
4423 /* Return a mask that has bit N set if OPCODE reads the register(s)
4427 insn_read_mask (const struct mips_opcode *opcode)
4429 return (opcode->pinfo & INSN_READ_ALL) >> INSN_READ_SHIFT;
4432 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4436 insn_write_mask (const struct mips_opcode *opcode)
4438 return (opcode->pinfo & INSN_WRITE_ALL) >> INSN_WRITE_SHIFT;
4441 /* Return a mask of the registers specified by operand OPERAND of INSN.
4442 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4446 operand_reg_mask (const struct mips_cl_insn *insn,
4447 const struct mips_operand *operand,
4448 unsigned int type_mask)
4450 unsigned int uval, vsel;
4452 switch (operand->type)
4459 case OP_ADDIUSP_INT:
4460 case OP_ENTRY_EXIT_LIST:
4461 case OP_REPEAT_DEST_REG:
4462 case OP_REPEAT_PREV_REG:
4465 case OP_VU0_MATCH_SUFFIX:
4470 case OP_OPTIONAL_REG:
4472 const struct mips_reg_operand *reg_op;
4474 reg_op = (const struct mips_reg_operand *) operand;
4475 if (!(type_mask & (1 << reg_op->reg_type)))
4477 uval = insn_extract_operand (insn, operand);
4478 return 1 << mips_decode_reg_operand (reg_op, uval);
4483 const struct mips_reg_pair_operand *pair_op;
4485 pair_op = (const struct mips_reg_pair_operand *) operand;
4486 if (!(type_mask & (1 << pair_op->reg_type)))
4488 uval = insn_extract_operand (insn, operand);
4489 return (1 << pair_op->reg1_map[uval]) | (1 << pair_op->reg2_map[uval]);
4492 case OP_CLO_CLZ_DEST:
4493 if (!(type_mask & (1 << OP_REG_GP)))
4495 uval = insn_extract_operand (insn, operand);
4496 return (1 << (uval & 31)) | (1 << (uval >> 5));
4499 if (!(type_mask & (1 << OP_REG_GP)))
4501 uval = insn_extract_operand (insn, operand);
4502 gas_assert ((uval & 31) == (uval >> 5));
4503 return 1 << (uval & 31);
4506 case OP_NON_ZERO_REG:
4507 if (!(type_mask & (1 << OP_REG_GP)))
4509 uval = insn_extract_operand (insn, operand);
4510 return 1 << (uval & 31);
4512 case OP_LWM_SWM_LIST:
4515 case OP_SAVE_RESTORE_LIST:
4518 case OP_MDMX_IMM_REG:
4519 if (!(type_mask & (1 << OP_REG_VEC)))
4521 uval = insn_extract_operand (insn, operand);
4523 if ((vsel & 0x18) == 0x18)
4525 return 1 << (uval & 31);
4528 if (!(type_mask & (1 << OP_REG_GP)))
4530 return 1 << insn_extract_operand (insn, operand);
4535 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4536 where bit N of OPNO_MASK is set if operand N should be included.
4537 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4541 insn_reg_mask (const struct mips_cl_insn *insn,
4542 unsigned int type_mask, unsigned int opno_mask)
4544 unsigned int opno, reg_mask;
4548 while (opno_mask != 0)
4551 reg_mask |= operand_reg_mask (insn, insn_opno (insn, opno), type_mask);
4558 /* Return the mask of core registers that IP reads. */
4561 gpr_read_mask (const struct mips_cl_insn *ip)
4563 unsigned long pinfo, pinfo2;
4566 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_read_mask (ip->insn_mo));
4567 pinfo = ip->insn_mo->pinfo;
4568 pinfo2 = ip->insn_mo->pinfo2;
4569 if (pinfo & INSN_UDI)
4571 /* UDI instructions have traditionally been assumed to read RS
4573 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
4574 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
4576 if (pinfo & INSN_READ_GPR_24)
4578 if (pinfo2 & INSN2_READ_GPR_16)
4580 if (pinfo2 & INSN2_READ_SP)
4582 if (pinfo2 & INSN2_READ_GPR_31)
4584 /* Don't include register 0. */
4588 /* Return the mask of core registers that IP writes. */
4591 gpr_write_mask (const struct mips_cl_insn *ip)
4593 unsigned long pinfo, pinfo2;
4596 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_write_mask (ip->insn_mo));
4597 pinfo = ip->insn_mo->pinfo;
4598 pinfo2 = ip->insn_mo->pinfo2;
4599 if (pinfo & INSN_WRITE_GPR_24)
4601 if (pinfo & INSN_WRITE_GPR_31)
4603 if (pinfo & INSN_UDI)
4604 /* UDI instructions have traditionally been assumed to write to RD. */
4605 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
4606 if (pinfo2 & INSN2_WRITE_SP)
4608 /* Don't include register 0. */
4612 /* Return the mask of floating-point registers that IP reads. */
4615 fpr_read_mask (const struct mips_cl_insn *ip)
4617 unsigned long pinfo;
4620 mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC)
4621 | (1 << OP_REG_MSA)),
4622 insn_read_mask (ip->insn_mo));
4623 pinfo = ip->insn_mo->pinfo;
4624 /* Conservatively treat all operands to an FP_D instruction are doubles.
4625 (This is overly pessimistic for things like cvt.d.s.) */
4626 if (FPR_SIZE != 64 && (pinfo & FP_D))
4631 /* Return the mask of floating-point registers that IP writes. */
4634 fpr_write_mask (const struct mips_cl_insn *ip)
4636 unsigned long pinfo;
4639 mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC)
4640 | (1 << OP_REG_MSA)),
4641 insn_write_mask (ip->insn_mo));
4642 pinfo = ip->insn_mo->pinfo;
4643 /* Conservatively treat all operands to an FP_D instruction are doubles.
4644 (This is overly pessimistic for things like cvt.s.d.) */
4645 if (FPR_SIZE != 64 && (pinfo & FP_D))
4650 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4651 Check whether that is allowed. */
4654 mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum)
4656 const char *s = insn->name;
4657 bfd_boolean oddspreg = (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa, mips_opts.arch)
4659 && mips_opts.oddspreg;
4661 if (insn->pinfo == INSN_MACRO)
4662 /* Let a macro pass, we'll catch it later when it is expanded. */
4665 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4666 otherwise it depends on oddspreg. */
4667 if ((insn->pinfo & FP_S)
4668 && (insn->pinfo & (INSN_LOAD_MEMORY | INSN_STORE_MEMORY
4669 | INSN_LOAD_COPROC | INSN_COPROC_MOVE)))
4670 return FPR_SIZE == 32 || oddspreg;
4672 /* Allow odd registers for single-precision ops and double-precision if the
4673 floating-point registers are 64-bit wide. */
4674 switch (insn->pinfo & (FP_S | FP_D))
4680 return FPR_SIZE == 64;
4685 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4686 s = strchr (insn->name, '.');
4687 if (s != NULL && opnum == 2)
4688 s = strchr (s + 1, '.');
4689 if (s != NULL && (s[1] == 'w' || s[1] == 's'))
4692 return FPR_SIZE == 64;
4695 /* Information about an instruction argument that we're trying to match. */
4696 struct mips_arg_info
4698 /* The instruction so far. */
4699 struct mips_cl_insn *insn;
4701 /* The first unconsumed operand token. */
4702 struct mips_operand_token *token;
4704 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4707 /* The 1-based argument number, for error reporting. This does not
4708 count elided optional registers, etc.. */
4711 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4712 unsigned int last_regno;
4714 /* If the first operand was an OP_REG, this is the register that it
4715 specified, otherwise it is ILLEGAL_REG. */
4716 unsigned int dest_regno;
4718 /* The value of the last OP_INT operand. Only used for OP_MSB,
4719 where it gives the lsb position. */
4720 unsigned int last_op_int;
4722 /* If true, match routines should assume that no later instruction
4723 alternative matches and should therefore be as accommodating as
4724 possible. Match routines should not report errors if something
4725 is only invalid for !LAX_MATCH. */
4726 bfd_boolean lax_match;
4728 /* True if a reference to the current AT register was seen. */
4729 bfd_boolean seen_at;
4732 /* Record that the argument is out of range. */
4735 match_out_of_range (struct mips_arg_info *arg)
4737 set_insn_error_i (arg->argnum, _("operand %d out of range"), arg->argnum);
4740 /* Record that the argument isn't constant but needs to be. */
4743 match_not_constant (struct mips_arg_info *arg)
4745 set_insn_error_i (arg->argnum, _("operand %d must be constant"),
4749 /* Try to match an OT_CHAR token for character CH. Consume the token
4750 and return true on success, otherwise return false. */
4753 match_char (struct mips_arg_info *arg, char ch)
4755 if (arg->token->type == OT_CHAR && arg->token->u.ch == ch)
4765 /* Try to get an expression from the next tokens in ARG. Consume the
4766 tokens and return true on success, storing the expression value in
4767 VALUE and relocation types in R. */
4770 match_expression (struct mips_arg_info *arg, expressionS *value,
4771 bfd_reloc_code_real_type *r)
4773 /* If the next token is a '(' that was parsed as being part of a base
4774 expression, assume we have an elided offset. The later match will fail
4775 if this turns out to be wrong. */
4776 if (arg->token->type == OT_CHAR && arg->token->u.ch == '(')
4778 value->X_op = O_constant;
4779 value->X_add_number = 0;
4780 r[0] = r[1] = r[2] = BFD_RELOC_UNUSED;
4784 /* Reject register-based expressions such as "0+$2" and "(($2))".
4785 For plain registers the default error seems more appropriate. */
4786 if (arg->token->type == OT_INTEGER
4787 && arg->token->u.integer.value.X_op == O_register)
4789 set_insn_error (arg->argnum, _("register value used as expression"));
4793 if (arg->token->type == OT_INTEGER)
4795 *value = arg->token->u.integer.value;
4796 memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r));
4802 (arg->argnum, _("operand %d must be an immediate expression"),
4807 /* Try to get a constant expression from the next tokens in ARG. Consume
4808 the tokens and return return true on success, storing the constant value
4809 in *VALUE. Use FALLBACK as the value if the match succeeded with an
4813 match_const_int (struct mips_arg_info *arg, offsetT *value)
4816 bfd_reloc_code_real_type r[3];
4818 if (!match_expression (arg, &ex, r))
4821 if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant)
4822 *value = ex.X_add_number;
4825 match_not_constant (arg);
4831 /* Return the RTYPE_* flags for a register operand of type TYPE that
4832 appears in instruction OPCODE. */
4835 convert_reg_type (const struct mips_opcode *opcode,
4836 enum mips_reg_operand_type type)
4841 return RTYPE_NUM | RTYPE_GP;
4844 /* Allow vector register names for MDMX if the instruction is a 64-bit
4845 FPR load, store or move (including moves to and from GPRs). */
4846 if ((mips_opts.ase & ASE_MDMX)
4847 && (opcode->pinfo & FP_D)
4848 && (opcode->pinfo & (INSN_COPROC_MOVE
4849 | INSN_COPROC_MEMORY_DELAY
4852 | INSN_STORE_MEMORY)))
4853 return RTYPE_FPU | RTYPE_VEC;
4857 if (opcode->pinfo & (FP_D | FP_S))
4858 return RTYPE_CCC | RTYPE_FCC;
4862 if (opcode->membership & INSN_5400)
4864 return RTYPE_FPU | RTYPE_VEC;
4870 if (opcode->name[strlen (opcode->name) - 1] == '0')
4871 return RTYPE_NUM | RTYPE_CP0;
4878 return RTYPE_NUM | RTYPE_VI;
4881 return RTYPE_NUM | RTYPE_VF;
4883 case OP_REG_R5900_I:
4884 return RTYPE_R5900_I;
4886 case OP_REG_R5900_Q:
4887 return RTYPE_R5900_Q;
4889 case OP_REG_R5900_R:
4890 return RTYPE_R5900_R;
4892 case OP_REG_R5900_ACC:
4893 return RTYPE_R5900_ACC;
4898 case OP_REG_MSA_CTRL:
4904 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4907 check_regno (struct mips_arg_info *arg,
4908 enum mips_reg_operand_type type, unsigned int regno)
4910 if (AT && type == OP_REG_GP && regno == AT)
4911 arg->seen_at = TRUE;
4913 if (type == OP_REG_FP
4915 && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum))
4917 /* This was a warning prior to introducing O32 FPXX and FP64 support
4918 so maintain a warning for FP32 but raise an error for the new
4921 as_warn (_("float register should be even, was %d"), regno);
4923 as_bad (_("float register should be even, was %d"), regno);
4926 if (type == OP_REG_CCC)
4931 name = arg->insn->insn_mo->name;
4932 length = strlen (name);
4933 if ((regno & 1) != 0
4934 && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0)
4935 || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0)))
4936 as_warn (_("condition code register should be even for %s, was %d"),
4939 if ((regno & 3) != 0
4940 && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0))
4941 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
4946 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
4947 a register of type TYPE. Return true on success, storing the register
4948 number in *REGNO and warning about any dubious uses. */
4951 match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4952 unsigned int symval, unsigned int *regno)
4954 if (type == OP_REG_VEC)
4955 symval = mips_prefer_vec_regno (symval);
4956 if (!(symval & convert_reg_type (arg->insn->insn_mo, type)))
4959 *regno = symval & RNUM_MASK;
4960 check_regno (arg, type, *regno);
4964 /* Try to interpret the next token in ARG as a register of type TYPE.
4965 Consume the token and return true on success, storing the register
4966 number in *REGNO. Return false on failure. */
4969 match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4970 unsigned int *regno)
4972 if (arg->token->type == OT_REG
4973 && match_regno (arg, type, arg->token->u.regno, regno))
4981 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
4982 Consume the token and return true on success, storing the register numbers
4983 in *REGNO1 and *REGNO2. Return false on failure. */
4986 match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4987 unsigned int *regno1, unsigned int *regno2)
4989 if (match_reg (arg, type, regno1))
4994 if (arg->token->type == OT_REG_RANGE
4995 && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1)
4996 && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2)
4997 && *regno1 <= *regno2)
5005 /* OP_INT matcher. */
5008 match_int_operand (struct mips_arg_info *arg,
5009 const struct mips_operand *operand_base)
5011 const struct mips_int_operand *operand;
5013 int min_val, max_val, factor;
5016 operand = (const struct mips_int_operand *) operand_base;
5017 factor = 1 << operand->shift;
5018 min_val = mips_int_operand_min (operand);
5019 max_val = mips_int_operand_max (operand);
5021 if (operand_base->lsb == 0
5022 && operand_base->size == 16
5023 && operand->shift == 0
5024 && operand->bias == 0
5025 && (operand->max_val == 32767 || operand->max_val == 65535))
5027 /* The operand can be relocated. */
5028 if (!match_expression (arg, &offset_expr, offset_reloc))
5031 if (offset_reloc[0] != BFD_RELOC_UNUSED)
5032 /* Relocation operators were used. Accept the arguent and
5033 leave the relocation value in offset_expr and offset_relocs
5034 for the caller to process. */
5037 if (offset_expr.X_op != O_constant)
5039 /* Accept non-constant operands if no later alternative matches,
5040 leaving it for the caller to process. */
5041 if (!arg->lax_match)
5043 offset_reloc[0] = BFD_RELOC_LO16;
5047 /* Clear the global state; we're going to install the operand
5049 sval = offset_expr.X_add_number;
5050 offset_expr.X_op = O_absent;
5052 /* For compatibility with older assemblers, we accept
5053 0x8000-0xffff as signed 16-bit numbers when only
5054 signed numbers are allowed. */
5057 max_val = ((1 << operand_base->size) - 1) << operand->shift;
5058 if (!arg->lax_match && sval <= max_val)
5064 if (!match_const_int (arg, &sval))
5068 arg->last_op_int = sval;
5070 if (sval < min_val || sval > max_val || sval % factor)
5072 match_out_of_range (arg);
5076 uval = (unsigned int) sval >> operand->shift;
5077 uval -= operand->bias;
5079 /* Handle -mfix-cn63xxp1. */
5081 && mips_fix_cn63xxp1
5082 && !mips_opts.micromips
5083 && strcmp ("pref", arg->insn->insn_mo->name) == 0)
5098 /* The rest must be changed to 28. */
5103 insn_insert_operand (arg->insn, operand_base, uval);
5107 /* OP_MAPPED_INT matcher. */
5110 match_mapped_int_operand (struct mips_arg_info *arg,
5111 const struct mips_operand *operand_base)
5113 const struct mips_mapped_int_operand *operand;
5114 unsigned int uval, num_vals;
5117 operand = (const struct mips_mapped_int_operand *) operand_base;
5118 if (!match_const_int (arg, &sval))
5121 num_vals = 1 << operand_base->size;
5122 for (uval = 0; uval < num_vals; uval++)
5123 if (operand->int_map[uval] == sval)
5125 if (uval == num_vals)
5127 match_out_of_range (arg);
5131 insn_insert_operand (arg->insn, operand_base, uval);
5135 /* OP_MSB matcher. */
5138 match_msb_operand (struct mips_arg_info *arg,
5139 const struct mips_operand *operand_base)
5141 const struct mips_msb_operand *operand;
5142 int min_val, max_val, max_high;
5143 offsetT size, sval, high;
5145 operand = (const struct mips_msb_operand *) operand_base;
5146 min_val = operand->bias;
5147 max_val = min_val + (1 << operand_base->size) - 1;
5148 max_high = operand->opsize;
5150 if (!match_const_int (arg, &size))
5153 high = size + arg->last_op_int;
5154 sval = operand->add_lsb ? high : size;
5156 if (size < 0 || high > max_high || sval < min_val || sval > max_val)
5158 match_out_of_range (arg);
5161 insn_insert_operand (arg->insn, operand_base, sval - min_val);
5165 /* OP_REG matcher. */
5168 match_reg_operand (struct mips_arg_info *arg,
5169 const struct mips_operand *operand_base)
5171 const struct mips_reg_operand *operand;
5172 unsigned int regno, uval, num_vals;
5174 operand = (const struct mips_reg_operand *) operand_base;
5175 if (!match_reg (arg, operand->reg_type, ®no))
5178 if (operand->reg_map)
5180 num_vals = 1 << operand->root.size;
5181 for (uval = 0; uval < num_vals; uval++)
5182 if (operand->reg_map[uval] == regno)
5184 if (num_vals == uval)
5190 arg->last_regno = regno;
5191 if (arg->opnum == 1)
5192 arg->dest_regno = regno;
5193 insn_insert_operand (arg->insn, operand_base, uval);
5197 /* OP_REG_PAIR matcher. */
5200 match_reg_pair_operand (struct mips_arg_info *arg,
5201 const struct mips_operand *operand_base)
5203 const struct mips_reg_pair_operand *operand;
5204 unsigned int regno1, regno2, uval, num_vals;
5206 operand = (const struct mips_reg_pair_operand *) operand_base;
5207 if (!match_reg (arg, operand->reg_type, ®no1)
5208 || !match_char (arg, ',')
5209 || !match_reg (arg, operand->reg_type, ®no2))
5212 num_vals = 1 << operand_base->size;
5213 for (uval = 0; uval < num_vals; uval++)
5214 if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2)
5216 if (uval == num_vals)
5219 insn_insert_operand (arg->insn, operand_base, uval);
5223 /* OP_PCREL matcher. The caller chooses the relocation type. */
5226 match_pcrel_operand (struct mips_arg_info *arg)
5228 bfd_reloc_code_real_type r[3];
5230 return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED;
5233 /* OP_PERF_REG matcher. */
5236 match_perf_reg_operand (struct mips_arg_info *arg,
5237 const struct mips_operand *operand)
5241 if (!match_const_int (arg, &sval))
5246 || (mips_opts.arch == CPU_R5900
5247 && (strcmp (arg->insn->insn_mo->name, "mfps") == 0
5248 || strcmp (arg->insn->insn_mo->name, "mtps") == 0))))
5250 set_insn_error (arg->argnum, _("invalid performance register"));
5254 insn_insert_operand (arg->insn, operand, sval);
5258 /* OP_ADDIUSP matcher. */
5261 match_addiusp_operand (struct mips_arg_info *arg,
5262 const struct mips_operand *operand)
5267 if (!match_const_int (arg, &sval))
5272 match_out_of_range (arg);
5277 if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1))
5279 match_out_of_range (arg);
5283 uval = (unsigned int) sval;
5284 uval = ((uval >> 1) & ~0xff) | (uval & 0xff);
5285 insn_insert_operand (arg->insn, operand, uval);
5289 /* OP_CLO_CLZ_DEST matcher. */
5292 match_clo_clz_dest_operand (struct mips_arg_info *arg,
5293 const struct mips_operand *operand)
5297 if (!match_reg (arg, OP_REG_GP, ®no))
5300 insn_insert_operand (arg->insn, operand, regno | (regno << 5));
5304 /* OP_CHECK_PREV matcher. */
5307 match_check_prev_operand (struct mips_arg_info *arg,
5308 const struct mips_operand *operand_base)
5310 const struct mips_check_prev_operand *operand;
5313 operand = (const struct mips_check_prev_operand *) operand_base;
5315 if (!match_reg (arg, OP_REG_GP, ®no))
5318 if (!operand->zero_ok && regno == 0)
5321 if ((operand->less_than_ok && regno < arg->last_regno)
5322 || (operand->greater_than_ok && regno > arg->last_regno)
5323 || (operand->equal_ok && regno == arg->last_regno))
5325 arg->last_regno = regno;
5326 insn_insert_operand (arg->insn, operand_base, regno);
5333 /* OP_SAME_RS_RT matcher. */
5336 match_same_rs_rt_operand (struct mips_arg_info *arg,
5337 const struct mips_operand *operand)
5341 if (!match_reg (arg, OP_REG_GP, ®no))
5346 set_insn_error (arg->argnum, _("the source register must not be $0"));
5350 arg->last_regno = regno;
5352 insn_insert_operand (arg->insn, operand, regno | (regno << 5));
5356 /* OP_LWM_SWM_LIST matcher. */
5359 match_lwm_swm_list_operand (struct mips_arg_info *arg,
5360 const struct mips_operand *operand)
5362 unsigned int reglist, sregs, ra, regno1, regno2;
5363 struct mips_arg_info reset;
5366 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
5370 if (regno2 == FP && regno1 >= S0 && regno1 <= S7)
5375 reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1);
5378 while (match_char (arg, ',')
5379 && match_reg_range (arg, OP_REG_GP, ®no1, ®no2));
5382 if (operand->size == 2)
5384 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5390 and any permutations of these. */
5391 if ((reglist & 0xfff1ffff) != 0x80010000)
5394 sregs = (reglist >> 17) & 7;
5399 /* The list must include at least one of ra and s0-sN,
5400 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5401 which are $23 and $30 respectively.) E.g.:
5409 and any permutations of these. */
5410 if ((reglist & 0x3f00ffff) != 0)
5413 ra = (reglist >> 27) & 0x10;
5414 sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
5417 if ((sregs & -sregs) != sregs)
5420 insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra);
5424 /* OP_ENTRY_EXIT_LIST matcher. */
5427 match_entry_exit_operand (struct mips_arg_info *arg,
5428 const struct mips_operand *operand)
5431 bfd_boolean is_exit;
5433 /* The format is the same for both ENTRY and EXIT, but the constraints
5435 is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0;
5436 mask = (is_exit ? 7 << 3 : 0);
5439 unsigned int regno1, regno2;
5440 bfd_boolean is_freg;
5442 if (match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
5444 else if (match_reg_range (arg, OP_REG_FP, ®no1, ®no2))
5449 if (is_exit && is_freg && regno1 == 0 && regno2 < 2)
5452 mask |= (5 + regno2) << 3;
5454 else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7)
5455 mask |= (regno2 - 3) << 3;
5456 else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17)
5457 mask |= (regno2 - 15) << 1;
5458 else if (regno1 == RA && regno2 == RA)
5463 while (match_char (arg, ','));
5465 insn_insert_operand (arg->insn, operand, mask);
5469 /* OP_SAVE_RESTORE_LIST matcher. */
5472 match_save_restore_list_operand (struct mips_arg_info *arg)
5474 unsigned int opcode, args, statics, sregs;
5475 unsigned int num_frame_sizes, num_args, num_statics, num_sregs;
5478 opcode = arg->insn->insn_opcode;
5480 num_frame_sizes = 0;
5486 unsigned int regno1, regno2;
5488 if (arg->token->type == OT_INTEGER)
5490 /* Handle the frame size. */
5491 if (!match_const_int (arg, &frame_size))
5493 num_frame_sizes += 1;
5497 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
5500 while (regno1 <= regno2)
5502 if (regno1 >= 4 && regno1 <= 7)
5504 if (num_frame_sizes == 0)
5506 args |= 1 << (regno1 - 4);
5508 /* statics $a0-$a3 */
5509 statics |= 1 << (regno1 - 4);
5511 else if (regno1 >= 16 && regno1 <= 23)
5513 sregs |= 1 << (regno1 - 16);
5514 else if (regno1 == 30)
5517 else if (regno1 == 31)
5518 /* Add $ra to insn. */
5528 while (match_char (arg, ','));
5530 /* Encode args/statics combination. */
5533 else if (args == 0xf)
5534 /* All $a0-$a3 are args. */
5535 opcode |= MIPS16_ALL_ARGS << 16;
5536 else if (statics == 0xf)
5537 /* All $a0-$a3 are statics. */
5538 opcode |= MIPS16_ALL_STATICS << 16;
5541 /* Count arg registers. */
5551 /* Count static registers. */
5553 while (statics & 0x8)
5555 statics = (statics << 1) & 0xf;
5561 /* Encode args/statics. */
5562 opcode |= ((num_args << 2) | num_statics) << 16;
5565 /* Encode $s0/$s1. */
5566 if (sregs & (1 << 0)) /* $s0 */
5568 if (sregs & (1 << 1)) /* $s1 */
5572 /* Encode $s2-$s8. */
5581 opcode |= num_sregs << 24;
5583 /* Encode frame size. */
5584 if (num_frame_sizes == 0)
5586 set_insn_error (arg->argnum, _("missing frame size"));
5589 if (num_frame_sizes > 1)
5591 set_insn_error (arg->argnum, _("frame size specified twice"));
5594 if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8)
5596 set_insn_error (arg->argnum, _("invalid frame size"));
5599 if (frame_size != 128 || (opcode >> 16) != 0)
5602 opcode |= (((frame_size & 0xf0) << 16)
5603 | (frame_size & 0x0f));
5606 /* Finally build the instruction. */
5607 if ((opcode >> 16) != 0 || frame_size == 0)
5608 opcode |= MIPS16_EXTEND;
5609 arg->insn->insn_opcode = opcode;
5613 /* OP_MDMX_IMM_REG matcher. */
5616 match_mdmx_imm_reg_operand (struct mips_arg_info *arg,
5617 const struct mips_operand *operand)
5619 unsigned int regno, uval;
5621 const struct mips_opcode *opcode;
5623 /* The mips_opcode records whether this is an octobyte or quadhalf
5624 instruction. Start out with that bit in place. */
5625 opcode = arg->insn->insn_mo;
5626 uval = mips_extract_operand (operand, opcode->match);
5627 is_qh = (uval != 0);
5629 if (arg->token->type == OT_REG)
5631 if ((opcode->membership & INSN_5400)
5632 && strcmp (opcode->name, "rzu.ob") == 0)
5634 set_insn_error_i (arg->argnum, _("operand %d must be an immediate"),
5639 if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no))
5643 /* Check whether this is a vector register or a broadcast of
5644 a single element. */
5645 if (arg->token->type == OT_INTEGER_INDEX)
5647 if (arg->token->u.index > (is_qh ? 3 : 7))
5649 set_insn_error (arg->argnum, _("invalid element selector"));
5652 uval |= arg->token->u.index << (is_qh ? 2 : 1) << 5;
5657 /* A full vector. */
5658 if ((opcode->membership & INSN_5400)
5659 && (strcmp (opcode->name, "sll.ob") == 0
5660 || strcmp (opcode->name, "srl.ob") == 0))
5662 set_insn_error_i (arg->argnum, _("operand %d must be scalar"),
5668 uval |= MDMX_FMTSEL_VEC_QH << 5;
5670 uval |= MDMX_FMTSEL_VEC_OB << 5;
5678 if (!match_const_int (arg, &sval))
5680 if (sval < 0 || sval > 31)
5682 match_out_of_range (arg);
5685 uval |= (sval & 31);
5687 uval |= MDMX_FMTSEL_IMM_QH << 5;
5689 uval |= MDMX_FMTSEL_IMM_OB << 5;
5691 insn_insert_operand (arg->insn, operand, uval);
5695 /* OP_IMM_INDEX matcher. */
5698 match_imm_index_operand (struct mips_arg_info *arg,
5699 const struct mips_operand *operand)
5701 unsigned int max_val;
5703 if (arg->token->type != OT_INTEGER_INDEX)
5706 max_val = (1 << operand->size) - 1;
5707 if (arg->token->u.index > max_val)
5709 match_out_of_range (arg);
5712 insn_insert_operand (arg->insn, operand, arg->token->u.index);
5717 /* OP_REG_INDEX matcher. */
5720 match_reg_index_operand (struct mips_arg_info *arg,
5721 const struct mips_operand *operand)
5725 if (arg->token->type != OT_REG_INDEX)
5728 if (!match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no))
5731 insn_insert_operand (arg->insn, operand, regno);
5736 /* OP_PC matcher. */
5739 match_pc_operand (struct mips_arg_info *arg)
5741 if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC))
5749 /* OP_NON_ZERO_REG matcher. */
5752 match_non_zero_reg_operand (struct mips_arg_info *arg,
5753 const struct mips_operand *operand)
5757 if (!match_reg (arg, OP_REG_GP, ®no))
5763 arg->last_regno = regno;
5764 insn_insert_operand (arg->insn, operand, regno);
5768 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5769 register that we need to match. */
5772 match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno)
5776 return match_reg (arg, OP_REG_GP, ®no) && regno == other_regno;
5779 /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
5780 the length of the value in bytes (4 for float, 8 for double) and
5781 USING_GPRS says whether the destination is a GPR rather than an FPR.
5783 Return the constant in IMM and OFFSET as follows:
5785 - If the constant should be loaded via memory, set IMM to O_absent and
5786 OFFSET to the memory address.
5788 - Otherwise, if the constant should be loaded into two 32-bit registers,
5789 set IMM to the O_constant to load into the high register and OFFSET
5790 to the corresponding value for the low register.
5792 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5794 These constants only appear as the last operand in an instruction,
5795 and every instruction that accepts them in any variant accepts them
5796 in all variants. This means we don't have to worry about backing out
5797 any changes if the instruction does not match. We just match
5798 unconditionally and report an error if the constant is invalid. */
5801 match_float_constant (struct mips_arg_info *arg, expressionS *imm,
5802 expressionS *offset, int length, bfd_boolean using_gprs)
5807 const char *newname;
5808 unsigned char *data;
5810 /* Where the constant is placed is based on how the MIPS assembler
5813 length == 4 && using_gprs -- immediate value only
5814 length == 8 && using_gprs -- .rdata or immediate value
5815 length == 4 && !using_gprs -- .lit4 or immediate value
5816 length == 8 && !using_gprs -- .lit8 or immediate value
5818 The .lit4 and .lit8 sections are only used if permitted by the
5820 if (arg->token->type != OT_FLOAT)
5822 set_insn_error (arg->argnum, _("floating-point expression required"));
5826 gas_assert (arg->token->u.flt.length == length);
5827 data = arg->token->u.flt.data;
5830 /* Handle 32-bit constants for which an immediate value is best. */
5833 || g_switch_value < 4
5834 || (data[0] == 0 && data[1] == 0)
5835 || (data[2] == 0 && data[3] == 0)))
5837 imm->X_op = O_constant;
5838 if (!target_big_endian)
5839 imm->X_add_number = bfd_getl32 (data);
5841 imm->X_add_number = bfd_getb32 (data);
5842 offset->X_op = O_absent;
5846 /* Handle 64-bit constants for which an immediate value is best. */
5848 && !mips_disable_float_construction
5849 /* Constants can only be constructed in GPRs and copied to FPRs if the
5850 GPRs are at least as wide as the FPRs or MTHC1 is available.
5851 Unlike most tests for 32-bit floating-point registers this check
5852 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
5853 permit 64-bit moves without MXHC1.
5854 Force the constant into memory otherwise. */
5857 || ISA_HAS_MXHC1 (mips_opts.isa)
5859 && ((data[0] == 0 && data[1] == 0)
5860 || (data[2] == 0 && data[3] == 0))
5861 && ((data[4] == 0 && data[5] == 0)
5862 || (data[6] == 0 && data[7] == 0)))
5864 /* The value is simple enough to load with a couple of instructions.
5865 If using 32-bit registers, set IMM to the high order 32 bits and
5866 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
5868 if (GPR_SIZE == 32 || (!using_gprs && FPR_SIZE != 64))
5870 imm->X_op = O_constant;
5871 offset->X_op = O_constant;
5872 if (!target_big_endian)
5874 imm->X_add_number = bfd_getl32 (data + 4);
5875 offset->X_add_number = bfd_getl32 (data);
5879 imm->X_add_number = bfd_getb32 (data);
5880 offset->X_add_number = bfd_getb32 (data + 4);
5882 if (offset->X_add_number == 0)
5883 offset->X_op = O_absent;
5887 imm->X_op = O_constant;
5888 if (!target_big_endian)
5889 imm->X_add_number = bfd_getl64 (data);
5891 imm->X_add_number = bfd_getb64 (data);
5892 offset->X_op = O_absent;
5897 /* Switch to the right section. */
5899 subseg = now_subseg;
5902 gas_assert (!using_gprs && g_switch_value >= 4);
5907 if (using_gprs || g_switch_value < 8)
5908 newname = RDATA_SECTION_NAME;
5913 new_seg = subseg_new (newname, (subsegT) 0);
5914 bfd_set_section_flags (stdoutput, new_seg,
5915 SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA);
5916 frag_align (length == 4 ? 2 : 3, 0, 0);
5917 if (strncmp (TARGET_OS, "elf", 3) != 0)
5918 record_alignment (new_seg, 4);
5920 record_alignment (new_seg, length == 4 ? 2 : 3);
5922 as_bad (_("cannot use `%s' in this section"), arg->insn->insn_mo->name);
5924 /* Set the argument to the current address in the section. */
5925 imm->X_op = O_absent;
5926 offset->X_op = O_symbol;
5927 offset->X_add_symbol = symbol_temp_new_now ();
5928 offset->X_add_number = 0;
5930 /* Put the floating point number into the section. */
5931 p = frag_more (length);
5932 memcpy (p, data, length);
5934 /* Switch back to the original section. */
5935 subseg_set (seg, subseg);
5939 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
5943 match_vu0_suffix_operand (struct mips_arg_info *arg,
5944 const struct mips_operand *operand,
5945 bfd_boolean match_p)
5949 /* The operand can be an XYZW mask or a single 2-bit channel index
5950 (with X being 0). */
5951 gas_assert (operand->size == 2 || operand->size == 4);
5953 /* The suffix can be omitted when it is already part of the opcode. */
5954 if (arg->token->type != OT_CHANNELS)
5957 uval = arg->token->u.channels;
5958 if (operand->size == 2)
5960 /* Check that a single bit is set and convert it into a 2-bit index. */
5961 if ((uval & -uval) != uval)
5963 uval = 4 - ffs (uval);
5966 if (match_p && insn_extract_operand (arg->insn, operand) != uval)
5971 insn_insert_operand (arg->insn, operand, uval);
5975 /* S is the text seen for ARG. Match it against OPERAND. Return the end
5976 of the argument text if the match is successful, otherwise return null. */
5979 match_operand (struct mips_arg_info *arg,
5980 const struct mips_operand *operand)
5982 switch (operand->type)
5985 return match_int_operand (arg, operand);
5988 return match_mapped_int_operand (arg, operand);
5991 return match_msb_operand (arg, operand);
5994 case OP_OPTIONAL_REG:
5995 return match_reg_operand (arg, operand);
5998 return match_reg_pair_operand (arg, operand);
6001 return match_pcrel_operand (arg);
6004 return match_perf_reg_operand (arg, operand);
6006 case OP_ADDIUSP_INT:
6007 return match_addiusp_operand (arg, operand);
6009 case OP_CLO_CLZ_DEST:
6010 return match_clo_clz_dest_operand (arg, operand);
6012 case OP_LWM_SWM_LIST:
6013 return match_lwm_swm_list_operand (arg, operand);
6015 case OP_ENTRY_EXIT_LIST:
6016 return match_entry_exit_operand (arg, operand);
6018 case OP_SAVE_RESTORE_LIST:
6019 return match_save_restore_list_operand (arg);
6021 case OP_MDMX_IMM_REG:
6022 return match_mdmx_imm_reg_operand (arg, operand);
6024 case OP_REPEAT_DEST_REG:
6025 return match_tied_reg_operand (arg, arg->dest_regno);
6027 case OP_REPEAT_PREV_REG:
6028 return match_tied_reg_operand (arg, arg->last_regno);
6031 return match_pc_operand (arg);
6034 return match_vu0_suffix_operand (arg, operand, FALSE);
6036 case OP_VU0_MATCH_SUFFIX:
6037 return match_vu0_suffix_operand (arg, operand, TRUE);
6040 return match_imm_index_operand (arg, operand);
6043 return match_reg_index_operand (arg, operand);
6046 return match_same_rs_rt_operand (arg, operand);
6049 return match_check_prev_operand (arg, operand);
6051 case OP_NON_ZERO_REG:
6052 return match_non_zero_reg_operand (arg, operand);
6057 /* ARG is the state after successfully matching an instruction.
6058 Issue any queued-up warnings. */
6061 check_completed_insn (struct mips_arg_info *arg)
6066 as_warn (_("used $at without \".set noat\""));
6068 as_warn (_("used $%u with \".set at=$%u\""), AT, AT);
6072 /* Return true if modifying general-purpose register REG needs a delay. */
6075 reg_needs_delay (unsigned int reg)
6077 unsigned long prev_pinfo;
6079 prev_pinfo = history[0].insn_mo->pinfo;
6080 if (!mips_opts.noreorder
6081 && (((prev_pinfo & INSN_LOAD_MEMORY) && !gpr_interlocks)
6082 || ((prev_pinfo & INSN_LOAD_COPROC) && !cop_interlocks))
6083 && (gpr_write_mask (&history[0]) & (1 << reg)))
6089 /* Classify an instruction according to the FIX_VR4120_* enumeration.
6090 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6091 by VR4120 errata. */
6094 classify_vr4120_insn (const char *name)
6096 if (strncmp (name, "macc", 4) == 0)
6097 return FIX_VR4120_MACC;
6098 if (strncmp (name, "dmacc", 5) == 0)
6099 return FIX_VR4120_DMACC;
6100 if (strncmp (name, "mult", 4) == 0)
6101 return FIX_VR4120_MULT;
6102 if (strncmp (name, "dmult", 5) == 0)
6103 return FIX_VR4120_DMULT;
6104 if (strstr (name, "div"))
6105 return FIX_VR4120_DIV;
6106 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
6107 return FIX_VR4120_MTHILO;
6108 return NUM_FIX_VR4120_CLASSES;
6111 #define INSN_ERET 0x42000018
6112 #define INSN_DERET 0x4200001f
6113 #define INSN_DMULT 0x1c
6114 #define INSN_DMULTU 0x1d
6116 /* Return the number of instructions that must separate INSN1 and INSN2,
6117 where INSN1 is the earlier instruction. Return the worst-case value
6118 for any INSN2 if INSN2 is null. */
6121 insns_between (const struct mips_cl_insn *insn1,
6122 const struct mips_cl_insn *insn2)
6124 unsigned long pinfo1, pinfo2;
6127 /* If INFO2 is null, pessimistically assume that all flags are set for
6128 the second instruction. */
6129 pinfo1 = insn1->insn_mo->pinfo;
6130 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
6132 /* For most targets, write-after-read dependencies on the HI and LO
6133 registers must be separated by at least two instructions. */
6134 if (!hilo_interlocks)
6136 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
6138 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
6142 /* If we're working around r7000 errata, there must be two instructions
6143 between an mfhi or mflo and any instruction that uses the result. */
6144 if (mips_7000_hilo_fix
6145 && !mips_opts.micromips
6146 && MF_HILO_INSN (pinfo1)
6147 && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))))
6150 /* If we're working around 24K errata, one instruction is required
6151 if an ERET or DERET is followed by a branch instruction. */
6152 if (mips_fix_24k && !mips_opts.micromips)
6154 if (insn1->insn_opcode == INSN_ERET
6155 || insn1->insn_opcode == INSN_DERET)
6158 || insn2->insn_opcode == INSN_ERET
6159 || insn2->insn_opcode == INSN_DERET
6160 || delayed_branch_p (insn2))
6165 /* If we're working around PMC RM7000 errata, there must be three
6166 nops between a dmult and a load instruction. */
6167 if (mips_fix_rm7000 && !mips_opts.micromips)
6169 if ((insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULT
6170 || (insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULTU)
6172 if (pinfo2 & INSN_LOAD_MEMORY)
6177 /* If working around VR4120 errata, check for combinations that need
6178 a single intervening instruction. */
6179 if (mips_fix_vr4120 && !mips_opts.micromips)
6181 unsigned int class1, class2;
6183 class1 = classify_vr4120_insn (insn1->insn_mo->name);
6184 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
6188 class2 = classify_vr4120_insn (insn2->insn_mo->name);
6189 if (vr4120_conflicts[class1] & (1 << class2))
6194 if (!HAVE_CODE_COMPRESSION)
6196 /* Check for GPR or coprocessor load delays. All such delays
6197 are on the RT register. */
6198 /* Itbl support may require additional care here. */
6199 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY))
6200 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC)))
6202 if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))
6206 /* Check for generic coprocessor hazards.
6208 This case is not handled very well. There is no special
6209 knowledge of CP0 handling, and the coprocessors other than
6210 the floating point unit are not distinguished at all. */
6211 /* Itbl support may require additional care here. FIXME!
6212 Need to modify this to include knowledge about
6213 user specified delays! */
6214 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE))
6215 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
6217 /* Handle cases where INSN1 writes to a known general coprocessor
6218 register. There must be a one instruction delay before INSN2
6219 if INSN2 reads that register, otherwise no delay is needed. */
6220 mask = fpr_write_mask (insn1);
6223 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
6228 /* Read-after-write dependencies on the control registers
6229 require a two-instruction gap. */
6230 if ((pinfo1 & INSN_WRITE_COND_CODE)
6231 && (pinfo2 & INSN_READ_COND_CODE))
6234 /* We don't know exactly what INSN1 does. If INSN2 is
6235 also a coprocessor instruction, assume there must be
6236 a one instruction gap. */
6237 if (pinfo2 & INSN_COP)
6242 /* Check for read-after-write dependencies on the coprocessor
6243 control registers in cases where INSN1 does not need a general
6244 coprocessor delay. This means that INSN1 is a floating point
6245 comparison instruction. */
6246 /* Itbl support may require additional care here. */
6247 else if (!cop_interlocks
6248 && (pinfo1 & INSN_WRITE_COND_CODE)
6249 && (pinfo2 & INSN_READ_COND_CODE))
6253 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6254 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6256 if ((insn1->insn_mo->pinfo2 & INSN2_FORBIDDEN_SLOT)
6257 && ((pinfo2 & INSN_NO_DELAY_SLOT)
6258 || (insn2 && delayed_branch_p (insn2))))
6264 /* Return the number of nops that would be needed to work around the
6265 VR4130 mflo/mfhi errata if instruction INSN immediately followed
6266 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6267 that are contained within the first IGNORE instructions of HIST. */
6270 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
6271 const struct mips_cl_insn *insn)
6276 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6277 are not affected by the errata. */
6279 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
6280 || strcmp (insn->insn_mo->name, "mtlo") == 0
6281 || strcmp (insn->insn_mo->name, "mthi") == 0))
6284 /* Search for the first MFLO or MFHI. */
6285 for (i = 0; i < MAX_VR4130_NOPS; i++)
6286 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
6288 /* Extract the destination register. */
6289 mask = gpr_write_mask (&hist[i]);
6291 /* No nops are needed if INSN reads that register. */
6292 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
6295 /* ...or if any of the intervening instructions do. */
6296 for (j = 0; j < i; j++)
6297 if (gpr_read_mask (&hist[j]) & mask)
6301 return MAX_VR4130_NOPS - i;
6306 #define BASE_REG_EQ(INSN1, INSN2) \
6307 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
6308 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6310 /* Return the minimum alignment for this store instruction. */
6313 fix_24k_align_to (const struct mips_opcode *mo)
6315 if (strcmp (mo->name, "sh") == 0)
6318 if (strcmp (mo->name, "swc1") == 0
6319 || strcmp (mo->name, "swc2") == 0
6320 || strcmp (mo->name, "sw") == 0
6321 || strcmp (mo->name, "sc") == 0
6322 || strcmp (mo->name, "s.s") == 0)
6325 if (strcmp (mo->name, "sdc1") == 0
6326 || strcmp (mo->name, "sdc2") == 0
6327 || strcmp (mo->name, "s.d") == 0)
6334 struct fix_24k_store_info
6336 /* Immediate offset, if any, for this store instruction. */
6338 /* Alignment required by this store instruction. */
6340 /* True for register offsets. */
6341 int register_offset;
6344 /* Comparison function used by qsort. */
6347 fix_24k_sort (const void *a, const void *b)
6349 const struct fix_24k_store_info *pos1 = a;
6350 const struct fix_24k_store_info *pos2 = b;
6352 return (pos1->off - pos2->off);
6355 /* INSN is a store instruction. Try to record the store information
6356 in STINFO. Return false if the information isn't known. */
6359 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
6360 const struct mips_cl_insn *insn)
6362 /* The instruction must have a known offset. */
6363 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
6366 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
6367 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
6371 /* Return the number of nops that would be needed to work around the 24k
6372 "lost data on stores during refill" errata if instruction INSN
6373 immediately followed the 2 instructions described by HIST.
6374 Ignore hazards that are contained within the first IGNORE
6375 instructions of HIST.
6377 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6378 for the data cache refills and store data. The following describes
6379 the scenario where the store data could be lost.
6381 * A data cache miss, due to either a load or a store, causing fill
6382 data to be supplied by the memory subsystem
6383 * The first three doublewords of fill data are returned and written
6385 * A sequence of four stores occurs in consecutive cycles around the
6386 final doubleword of the fill:
6390 * Zero, One or more instructions
6393 The four stores A-D must be to different doublewords of the line that
6394 is being filled. The fourth instruction in the sequence above permits
6395 the fill of the final doubleword to be transferred from the FSB into
6396 the cache. In the sequence above, the stores may be either integer
6397 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6398 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6399 different doublewords on the line. If the floating point unit is
6400 running in 1:2 mode, it is not possible to create the sequence above
6401 using only floating point store instructions.
6403 In this case, the cache line being filled is incorrectly marked
6404 invalid, thereby losing the data from any store to the line that
6405 occurs between the original miss and the completion of the five
6406 cycle sequence shown above.
6408 The workarounds are:
6410 * Run the data cache in write-through mode.
6411 * Insert a non-store instruction between
6412 Store A and Store B or Store B and Store C. */
6415 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
6416 const struct mips_cl_insn *insn)
6418 struct fix_24k_store_info pos[3];
6419 int align, i, base_offset;
6424 /* If the previous instruction wasn't a store, there's nothing to
6426 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
6429 /* If the instructions after the previous one are unknown, we have
6430 to assume the worst. */
6434 /* Check whether we are dealing with three consecutive stores. */
6435 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
6436 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
6439 /* If we don't know the relationship between the store addresses,
6440 assume the worst. */
6441 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
6442 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
6445 if (!fix_24k_record_store_info (&pos[0], insn)
6446 || !fix_24k_record_store_info (&pos[1], &hist[0])
6447 || !fix_24k_record_store_info (&pos[2], &hist[1]))
6450 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
6452 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6453 X bytes and such that the base register + X is known to be aligned
6456 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
6460 align = pos[0].align_to;
6461 base_offset = pos[0].off;
6462 for (i = 1; i < 3; i++)
6463 if (align < pos[i].align_to)
6465 align = pos[i].align_to;
6466 base_offset = pos[i].off;
6468 for (i = 0; i < 3; i++)
6469 pos[i].off -= base_offset;
6472 pos[0].off &= ~align + 1;
6473 pos[1].off &= ~align + 1;
6474 pos[2].off &= ~align + 1;
6476 /* If any two stores write to the same chunk, they also write to the
6477 same doubleword. The offsets are still sorted at this point. */
6478 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
6481 /* A range of at least 9 bytes is needed for the stores to be in
6482 non-overlapping doublewords. */
6483 if (pos[2].off - pos[0].off <= 8)
6486 if (pos[2].off - pos[1].off >= 24
6487 || pos[1].off - pos[0].off >= 24
6488 || pos[2].off - pos[0].off >= 32)
6494 /* Return the number of nops that would be needed if instruction INSN
6495 immediately followed the MAX_NOPS instructions given by HIST,
6496 where HIST[0] is the most recent instruction. Ignore hazards
6497 between INSN and the first IGNORE instructions in HIST.
6499 If INSN is null, return the worse-case number of nops for any
6503 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
6504 const struct mips_cl_insn *insn)
6506 int i, nops, tmp_nops;
6509 for (i = ignore; i < MAX_DELAY_NOPS; i++)
6511 tmp_nops = insns_between (hist + i, insn) - i;
6512 if (tmp_nops > nops)
6516 if (mips_fix_vr4130 && !mips_opts.micromips)
6518 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
6519 if (tmp_nops > nops)
6523 if (mips_fix_24k && !mips_opts.micromips)
6525 tmp_nops = nops_for_24k (ignore, hist, insn);
6526 if (tmp_nops > nops)
6533 /* The variable arguments provide NUM_INSNS extra instructions that
6534 might be added to HIST. Return the largest number of nops that
6535 would be needed after the extended sequence, ignoring hazards
6536 in the first IGNORE instructions. */
6539 nops_for_sequence (int num_insns, int ignore,
6540 const struct mips_cl_insn *hist, ...)
6543 struct mips_cl_insn buffer[MAX_NOPS];
6544 struct mips_cl_insn *cursor;
6547 va_start (args, hist);
6548 cursor = buffer + num_insns;
6549 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
6550 while (cursor > buffer)
6551 *--cursor = *va_arg (args, const struct mips_cl_insn *);
6553 nops = nops_for_insn (ignore, buffer, NULL);
6558 /* Like nops_for_insn, but if INSN is a branch, take into account the
6559 worst-case delay for the branch target. */
6562 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
6563 const struct mips_cl_insn *insn)
6567 nops = nops_for_insn (ignore, hist, insn);
6568 if (delayed_branch_p (insn))
6570 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
6571 hist, insn, get_delay_slot_nop (insn));
6572 if (tmp_nops > nops)
6575 else if (compact_branch_p (insn))
6577 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
6578 if (tmp_nops > nops)
6584 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6587 fix_loongson2f_nop (struct mips_cl_insn * ip)
6589 gas_assert (!HAVE_CODE_COMPRESSION);
6590 if (strcmp (ip->insn_mo->name, "nop") == 0)
6591 ip->insn_opcode = LOONGSON2F_NOP_INSN;
6594 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6595 jr target pc &= 'hffff_ffff_cfff_ffff. */
6598 fix_loongson2f_jump (struct mips_cl_insn * ip)
6600 gas_assert (!HAVE_CODE_COMPRESSION);
6601 if (strcmp (ip->insn_mo->name, "j") == 0
6602 || strcmp (ip->insn_mo->name, "jr") == 0
6603 || strcmp (ip->insn_mo->name, "jalr") == 0)
6611 sreg = EXTRACT_OPERAND (0, RS, *ip);
6612 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
6615 ep.X_op = O_constant;
6616 ep.X_add_number = 0xcfff0000;
6617 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
6618 ep.X_add_number = 0xffff;
6619 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
6620 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
6625 fix_loongson2f (struct mips_cl_insn * ip)
6627 if (mips_fix_loongson2f_nop)
6628 fix_loongson2f_nop (ip);
6630 if (mips_fix_loongson2f_jump)
6631 fix_loongson2f_jump (ip);
6634 /* IP is a branch that has a delay slot, and we need to fill it
6635 automatically. Return true if we can do that by swapping IP
6636 with the previous instruction.
6637 ADDRESS_EXPR is an operand of the instruction to be used with
6641 can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
6642 bfd_reloc_code_real_type *reloc_type)
6644 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
6645 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
6646 unsigned int fpr_read, prev_fpr_write;
6648 /* -O2 and above is required for this optimization. */
6649 if (mips_optimize < 2)
6652 /* If we have seen .set volatile or .set nomove, don't optimize. */
6653 if (mips_opts.nomove)
6656 /* We can't swap if the previous instruction's position is fixed. */
6657 if (history[0].fixed_p)
6660 /* If the previous previous insn was in a .set noreorder, we can't
6661 swap. Actually, the MIPS assembler will swap in this situation.
6662 However, gcc configured -with-gnu-as will generate code like
6670 in which we can not swap the bne and INSN. If gcc is not configured
6671 -with-gnu-as, it does not output the .set pseudo-ops. */
6672 if (history[1].noreorder_p)
6675 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6676 This means that the previous instruction was a 4-byte one anyhow. */
6677 if (mips_opts.mips16 && history[0].fixp[0])
6680 /* If the branch is itself the target of a branch, we can not swap.
6681 We cheat on this; all we check for is whether there is a label on
6682 this instruction. If there are any branches to anything other than
6683 a label, users must use .set noreorder. */
6684 if (seg_info (now_seg)->label_list)
6687 /* If the previous instruction is in a variant frag other than this
6688 branch's one, we cannot do the swap. This does not apply to
6689 MIPS16 code, which uses variant frags for different purposes. */
6690 if (!mips_opts.mips16
6692 && history[0].frag->fr_type == rs_machine_dependent)
6695 /* We do not swap with instructions that cannot architecturally
6696 be placed in a branch delay slot, such as SYNC or ERET. We
6697 also refrain from swapping with a trap instruction, since it
6698 complicates trap handlers to have the trap instruction be in
6700 prev_pinfo = history[0].insn_mo->pinfo;
6701 if (prev_pinfo & INSN_NO_DELAY_SLOT)
6704 /* Check for conflicts between the branch and the instructions
6705 before the candidate delay slot. */
6706 if (nops_for_insn (0, history + 1, ip) > 0)
6709 /* Check for conflicts between the swapped sequence and the
6710 target of the branch. */
6711 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
6714 /* If the branch reads a register that the previous
6715 instruction sets, we can not swap. */
6716 gpr_read = gpr_read_mask (ip);
6717 prev_gpr_write = gpr_write_mask (&history[0]);
6718 if (gpr_read & prev_gpr_write)
6721 fpr_read = fpr_read_mask (ip);
6722 prev_fpr_write = fpr_write_mask (&history[0]);
6723 if (fpr_read & prev_fpr_write)
6726 /* If the branch writes a register that the previous
6727 instruction sets, we can not swap. */
6728 gpr_write = gpr_write_mask (ip);
6729 if (gpr_write & prev_gpr_write)
6732 /* If the branch writes a register that the previous
6733 instruction reads, we can not swap. */
6734 prev_gpr_read = gpr_read_mask (&history[0]);
6735 if (gpr_write & prev_gpr_read)
6738 /* If one instruction sets a condition code and the
6739 other one uses a condition code, we can not swap. */
6740 pinfo = ip->insn_mo->pinfo;
6741 if ((pinfo & INSN_READ_COND_CODE)
6742 && (prev_pinfo & INSN_WRITE_COND_CODE))
6744 if ((pinfo & INSN_WRITE_COND_CODE)
6745 && (prev_pinfo & INSN_READ_COND_CODE))
6748 /* If the previous instruction uses the PC, we can not swap. */
6749 prev_pinfo2 = history[0].insn_mo->pinfo2;
6750 if (prev_pinfo2 & INSN2_READ_PC)
6753 /* If the previous instruction has an incorrect size for a fixed
6754 branch delay slot in microMIPS mode, we cannot swap. */
6755 pinfo2 = ip->insn_mo->pinfo2;
6756 if (mips_opts.micromips
6757 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
6758 && insn_length (history) != 2)
6760 if (mips_opts.micromips
6761 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
6762 && insn_length (history) != 4)
6765 /* On R5900 short loops need to be fixed by inserting a nop in
6766 the branch delay slots.
6767 A short loop can be terminated too early. */
6768 if (mips_opts.arch == CPU_R5900
6769 /* Check if instruction has a parameter, ignore "j $31". */
6770 && (address_expr != NULL)
6771 /* Parameter must be 16 bit. */
6772 && (*reloc_type == BFD_RELOC_16_PCREL_S2)
6773 /* Branch to same segment. */
6774 && (S_GET_SEGMENT (address_expr->X_add_symbol) == now_seg)
6775 /* Branch to same code fragment. */
6776 && (symbol_get_frag (address_expr->X_add_symbol) == frag_now)
6777 /* Can only calculate branch offset if value is known. */
6778 && symbol_constant_p (address_expr->X_add_symbol)
6779 /* Check if branch is really conditional. */
6780 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */
6781 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */
6782 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
6785 /* Check if loop is shorter than 6 instructions including
6786 branch and delay slot. */
6787 distance = frag_now_fix () - S_GET_VALUE (address_expr->X_add_symbol);
6794 /* When the loop includes branches or jumps,
6795 it is not a short loop. */
6796 for (i = 0; i < (distance / 4); i++)
6798 if ((history[i].cleared_p)
6799 || delayed_branch_p (&history[i]))
6807 /* Insert nop after branch to fix short loop. */
6816 /* Decide how we should add IP to the instruction stream.
6817 ADDRESS_EXPR is an operand of the instruction to be used with
6820 static enum append_method
6821 get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
6822 bfd_reloc_code_real_type *reloc_type)
6824 /* The relaxed version of a macro sequence must be inherently
6826 if (mips_relax.sequence == 2)
6829 /* We must not dabble with instructions in a ".set noreorder" block. */
6830 if (mips_opts.noreorder)
6833 /* Otherwise, it's our responsibility to fill branch delay slots. */
6834 if (delayed_branch_p (ip))
6836 if (!branch_likely_p (ip)
6837 && can_swap_branch_p (ip, address_expr, reloc_type))
6840 if (mips_opts.mips16
6841 && ISA_SUPPORTS_MIPS16E
6842 && gpr_read_mask (ip) != 0)
6843 return APPEND_ADD_COMPACT;
6845 if (mips_opts.micromips
6846 && ((ip->insn_opcode & 0xffe0) == 0x4580
6847 || (!forced_insn_length
6848 && ((ip->insn_opcode & 0xfc00) == 0xcc00
6849 || (ip->insn_opcode & 0xdc00) == 0x8c00))
6850 || (ip->insn_opcode & 0xdfe00000) == 0x94000000
6851 || (ip->insn_opcode & 0xdc1f0000) == 0x94000000))
6852 return APPEND_ADD_COMPACT;
6854 return APPEND_ADD_WITH_NOP;
6860 /* IP is an instruction whose opcode we have just changed, END points
6861 to the end of the opcode table processed. Point IP->insn_mo to the
6862 new opcode's definition. */
6865 find_altered_opcode (struct mips_cl_insn *ip, const struct mips_opcode *end)
6867 const struct mips_opcode *mo;
6869 for (mo = ip->insn_mo; mo < end; mo++)
6870 if (mo->pinfo != INSN_MACRO
6871 && (ip->insn_opcode & mo->mask) == mo->match)
6879 /* IP is a MIPS16 instruction whose opcode we have just changed.
6880 Point IP->insn_mo to the new opcode's definition. */
6883 find_altered_mips16_opcode (struct mips_cl_insn *ip)
6885 find_altered_opcode (ip, &mips16_opcodes[bfd_mips16_num_opcodes]);
6888 /* IP is a microMIPS instruction whose opcode we have just changed.
6889 Point IP->insn_mo to the new opcode's definition. */
6892 find_altered_micromips_opcode (struct mips_cl_insn *ip)
6894 find_altered_opcode (ip, µmips_opcodes[bfd_micromips_num_opcodes]);
6897 /* For microMIPS macros, we need to generate a local number label
6898 as the target of branches. */
6899 #define MICROMIPS_LABEL_CHAR '\037'
6900 static unsigned long micromips_target_label;
6901 static char micromips_target_name[32];
6904 micromips_label_name (void)
6906 char *p = micromips_target_name;
6907 char symbol_name_temporary[24];
6915 l = micromips_target_label;
6916 #ifdef LOCAL_LABEL_PREFIX
6917 *p++ = LOCAL_LABEL_PREFIX;
6920 *p++ = MICROMIPS_LABEL_CHAR;
6923 symbol_name_temporary[i++] = l % 10 + '0';
6928 *p++ = symbol_name_temporary[--i];
6931 return micromips_target_name;
6935 micromips_label_expr (expressionS *label_expr)
6937 label_expr->X_op = O_symbol;
6938 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
6939 label_expr->X_add_number = 0;
6943 micromips_label_inc (void)
6945 micromips_target_label++;
6946 *micromips_target_name = '\0';
6950 micromips_add_label (void)
6954 s = colon (micromips_label_name ());
6955 micromips_label_inc ();
6956 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
6959 /* If assembling microMIPS code, then return the microMIPS reloc
6960 corresponding to the requested one if any. Otherwise return
6961 the reloc unchanged. */
6963 static bfd_reloc_code_real_type
6964 micromips_map_reloc (bfd_reloc_code_real_type reloc)
6966 static const bfd_reloc_code_real_type relocs[][2] =
6968 /* Keep sorted incrementally by the left-hand key. */
6969 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
6970 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
6971 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
6972 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
6973 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
6974 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
6975 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
6976 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
6977 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
6978 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
6979 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
6980 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
6981 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
6982 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
6983 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
6984 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
6985 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
6986 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
6987 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
6988 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
6989 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
6990 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
6991 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
6992 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
6993 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
6994 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
6995 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
6997 bfd_reloc_code_real_type r;
7000 if (!mips_opts.micromips)
7002 for (i = 0; i < ARRAY_SIZE (relocs); i++)
7008 return relocs[i][1];
7013 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
7014 Return true on success, storing the resolved value in RESULT. */
7017 calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
7022 case BFD_RELOC_MIPS_HIGHEST:
7023 case BFD_RELOC_MICROMIPS_HIGHEST:
7024 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff;
7027 case BFD_RELOC_MIPS_HIGHER:
7028 case BFD_RELOC_MICROMIPS_HIGHER:
7029 *result = ((operand + 0x80008000ull) >> 32) & 0xffff;
7032 case BFD_RELOC_HI16_S:
7033 case BFD_RELOC_HI16_S_PCREL:
7034 case BFD_RELOC_MICROMIPS_HI16_S:
7035 case BFD_RELOC_MIPS16_HI16_S:
7036 *result = ((operand + 0x8000) >> 16) & 0xffff;
7039 case BFD_RELOC_HI16:
7040 case BFD_RELOC_MICROMIPS_HI16:
7041 case BFD_RELOC_MIPS16_HI16:
7042 *result = (operand >> 16) & 0xffff;
7045 case BFD_RELOC_LO16:
7046 case BFD_RELOC_LO16_PCREL:
7047 case BFD_RELOC_MICROMIPS_LO16:
7048 case BFD_RELOC_MIPS16_LO16:
7049 *result = operand & 0xffff;
7052 case BFD_RELOC_UNUSED:
7061 /* Output an instruction. IP is the instruction information.
7062 ADDRESS_EXPR is an operand of the instruction to be used with
7063 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
7064 a macro expansion. */
7067 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
7068 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
7070 unsigned long prev_pinfo2, pinfo;
7071 bfd_boolean relaxed_branch = FALSE;
7072 enum append_method method;
7073 bfd_boolean relax32;
7076 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
7077 fix_loongson2f (ip);
7079 file_ase_mips16 |= mips_opts.mips16;
7080 file_ase_micromips |= mips_opts.micromips;
7082 prev_pinfo2 = history[0].insn_mo->pinfo2;
7083 pinfo = ip->insn_mo->pinfo;
7085 /* Don't raise alarm about `nods' frags as they'll fill in the right
7086 kind of nop in relaxation if required. */
7087 if (mips_opts.micromips
7089 && !(history[0].frag
7090 && history[0].frag->fr_type == rs_machine_dependent
7091 && RELAX_MICROMIPS_P (history[0].frag->fr_subtype)
7092 && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype))
7093 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
7094 && micromips_insn_length (ip->insn_mo) != 2)
7095 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
7096 && micromips_insn_length (ip->insn_mo) != 4)))
7097 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
7098 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
7100 if (address_expr == NULL)
7102 else if (reloc_type[0] <= BFD_RELOC_UNUSED
7103 && reloc_type[1] == BFD_RELOC_UNUSED
7104 && reloc_type[2] == BFD_RELOC_UNUSED
7105 && address_expr->X_op == O_constant)
7107 switch (*reloc_type)
7109 case BFD_RELOC_MIPS_JMP:
7113 /* Shift is 2, unusually, for microMIPS JALX. */
7114 shift = (mips_opts.micromips
7115 && strcmp (ip->insn_mo->name, "jalx") != 0) ? 1 : 2;
7116 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7117 as_bad (_("jump to misaligned address (0x%lx)"),
7118 (unsigned long) address_expr->X_add_number);
7119 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7125 case BFD_RELOC_MIPS16_JMP:
7126 if ((address_expr->X_add_number & 3) != 0)
7127 as_bad (_("jump to misaligned address (0x%lx)"),
7128 (unsigned long) address_expr->X_add_number);
7130 (((address_expr->X_add_number & 0x7c0000) << 3)
7131 | ((address_expr->X_add_number & 0xf800000) >> 7)
7132 | ((address_expr->X_add_number & 0x3fffc) >> 2));
7136 case BFD_RELOC_16_PCREL_S2:
7140 shift = mips_opts.micromips ? 1 : 2;
7141 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7142 as_bad (_("branch to misaligned address (0x%lx)"),
7143 (unsigned long) address_expr->X_add_number);
7144 if (!mips_relax_branch)
7146 if ((address_expr->X_add_number + (1 << (shift + 15)))
7147 & ~((1 << (shift + 16)) - 1))
7148 as_bad (_("branch address range overflow (0x%lx)"),
7149 (unsigned long) address_expr->X_add_number);
7150 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7156 case BFD_RELOC_MIPS_21_PCREL_S2:
7161 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7162 as_bad (_("branch to misaligned address (0x%lx)"),
7163 (unsigned long) address_expr->X_add_number);
7164 if ((address_expr->X_add_number + (1 << (shift + 20)))
7165 & ~((1 << (shift + 21)) - 1))
7166 as_bad (_("branch address range overflow (0x%lx)"),
7167 (unsigned long) address_expr->X_add_number);
7168 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7173 case BFD_RELOC_MIPS_26_PCREL_S2:
7178 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7179 as_bad (_("branch to misaligned address (0x%lx)"),
7180 (unsigned long) address_expr->X_add_number);
7181 if ((address_expr->X_add_number + (1 << (shift + 25)))
7182 & ~((1 << (shift + 26)) - 1))
7183 as_bad (_("branch address range overflow (0x%lx)"),
7184 (unsigned long) address_expr->X_add_number);
7185 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7194 if (calculate_reloc (*reloc_type, address_expr->X_add_number,
7197 ip->insn_opcode |= value & 0xffff;
7205 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
7207 /* There are a lot of optimizations we could do that we don't.
7208 In particular, we do not, in general, reorder instructions.
7209 If you use gcc with optimization, it will reorder
7210 instructions and generally do much more optimization then we
7211 do here; repeating all that work in the assembler would only
7212 benefit hand written assembly code, and does not seem worth
7214 int nops = (mips_optimize == 0
7215 ? nops_for_insn (0, history, NULL)
7216 : nops_for_insn_or_target (0, history, ip));
7220 unsigned long old_frag_offset;
7223 old_frag = frag_now;
7224 old_frag_offset = frag_now_fix ();
7226 for (i = 0; i < nops; i++)
7227 add_fixed_insn (NOP_INSN);
7228 insert_into_history (0, nops, NOP_INSN);
7232 listing_prev_line ();
7233 /* We may be at the start of a variant frag. In case we
7234 are, make sure there is enough space for the frag
7235 after the frags created by listing_prev_line. The
7236 argument to frag_grow here must be at least as large
7237 as the argument to all other calls to frag_grow in
7238 this file. We don't have to worry about being in the
7239 middle of a variant frag, because the variants insert
7240 all needed nop instructions themselves. */
7244 mips_move_text_labels ();
7246 #ifndef NO_ECOFF_DEBUGGING
7247 if (ECOFF_DEBUGGING)
7248 ecoff_fix_loc (old_frag, old_frag_offset);
7252 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
7256 /* Work out how many nops in prev_nop_frag are needed by IP,
7257 ignoring hazards generated by the first prev_nop_frag_since
7259 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
7260 gas_assert (nops <= prev_nop_frag_holds);
7262 /* Enforce NOPS as a minimum. */
7263 if (nops > prev_nop_frag_required)
7264 prev_nop_frag_required = nops;
7266 if (prev_nop_frag_holds == prev_nop_frag_required)
7268 /* Settle for the current number of nops. Update the history
7269 accordingly (for the benefit of any future .set reorder code). */
7270 prev_nop_frag = NULL;
7271 insert_into_history (prev_nop_frag_since,
7272 prev_nop_frag_holds, NOP_INSN);
7276 /* Allow this instruction to replace one of the nops that was
7277 tentatively added to prev_nop_frag. */
7278 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
7279 prev_nop_frag_holds--;
7280 prev_nop_frag_since++;
7284 method = get_append_method (ip, address_expr, reloc_type);
7285 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
7287 dwarf2_emit_insn (0);
7288 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7289 so "move" the instruction address accordingly.
7291 Also, it doesn't seem appropriate for the assembler to reorder .loc
7292 entries. If this instruction is a branch that we are going to swap
7293 with the previous instruction, the two instructions should be
7294 treated as a unit, and the debug information for both instructions
7295 should refer to the start of the branch sequence. Using the
7296 current position is certainly wrong when swapping a 32-bit branch
7297 and a 16-bit delay slot, since the current position would then be
7298 in the middle of a branch. */
7299 dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp);
7301 relax32 = (mips_relax_branch
7302 /* Don't try branch relaxation within .set nomacro, or within
7303 .set noat if we use $at for PIC computations. If it turns
7304 out that the branch was out-of-range, we'll get an error. */
7305 && !mips_opts.warn_about_macros
7306 && (mips_opts.at || mips_pic == NO_PIC)
7307 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7308 as they have no complementing branches. */
7309 && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP)));
7311 if (!HAVE_CODE_COMPRESSION
7314 && *reloc_type == BFD_RELOC_16_PCREL_S2
7315 && delayed_branch_p (ip))
7317 relaxed_branch = TRUE;
7318 add_relaxed_insn (ip, (relaxed_branch_length
7320 uncond_branch_p (ip) ? -1
7321 : branch_likely_p (ip) ? 1
7325 uncond_branch_p (ip),
7326 branch_likely_p (ip),
7327 pinfo & INSN_WRITE_GPR_31,
7329 address_expr->X_add_symbol,
7330 address_expr->X_add_number);
7331 *reloc_type = BFD_RELOC_UNUSED;
7333 else if (mips_opts.micromips
7335 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
7336 || *reloc_type > BFD_RELOC_UNUSED)
7337 && (delayed_branch_p (ip) || compact_branch_p (ip))
7338 /* Don't try branch relaxation when users specify
7339 16-bit/32-bit instructions. */
7340 && !forced_insn_length)
7342 bfd_boolean relax16 = (method != APPEND_ADD_COMPACT
7343 && *reloc_type > BFD_RELOC_UNUSED);
7344 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
7345 int uncond = uncond_branch_p (ip) ? -1 : 0;
7346 int compact = compact_branch_p (ip) || method == APPEND_ADD_COMPACT;
7347 int nods = method == APPEND_ADD_WITH_NOP;
7348 int al = pinfo & INSN_WRITE_GPR_31;
7349 int length32 = nods ? 8 : 4;
7351 gas_assert (address_expr != NULL);
7352 gas_assert (!mips_relax.sequence);
7354 relaxed_branch = TRUE;
7356 method = APPEND_ADD;
7358 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
7359 add_relaxed_insn (ip, length32, relax16 ? 2 : 4,
7360 RELAX_MICROMIPS_ENCODE (type, AT, mips_opts.insn32,
7361 uncond, compact, al, nods,
7363 address_expr->X_add_symbol,
7364 address_expr->X_add_number);
7365 *reloc_type = BFD_RELOC_UNUSED;
7367 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
7369 bfd_boolean require_unextended;
7370 bfd_boolean require_extended;
7374 if (forced_insn_length != 0)
7376 require_unextended = forced_insn_length == 2;
7377 require_extended = forced_insn_length == 4;
7381 require_unextended = (mips_opts.noautoextend
7382 && !mips_opcode_32bit_p (ip->insn_mo));
7383 require_extended = 0;
7386 /* We need to set up a variant frag. */
7387 gas_assert (address_expr != NULL);
7388 /* Pass any `O_symbol' expression unchanged as an `expr_section'
7389 symbol created by `make_expr_symbol' may not get a necessary
7390 external relocation produced. */
7391 if (address_expr->X_op == O_symbol)
7393 symbol = address_expr->X_add_symbol;
7394 offset = address_expr->X_add_number;
7398 symbol = make_expr_symbol (address_expr);
7401 add_relaxed_insn (ip, 4, 0,
7403 (*reloc_type - BFD_RELOC_UNUSED,
7404 require_unextended, require_extended,
7405 delayed_branch_p (&history[0]),
7406 history[0].mips16_absolute_jump_p),
7409 else if (mips_opts.mips16 && insn_length (ip) == 2)
7411 if (!delayed_branch_p (ip))
7412 /* Make sure there is enough room to swap this instruction with
7413 a following jump instruction. */
7415 add_fixed_insn (ip);
7419 if (mips_opts.mips16
7420 && mips_opts.noreorder
7421 && delayed_branch_p (&history[0]))
7422 as_warn (_("extended instruction in delay slot"));
7424 if (mips_relax.sequence)
7426 /* If we've reached the end of this frag, turn it into a variant
7427 frag and record the information for the instructions we've
7429 if (frag_room () < 4)
7430 relax_close_frag ();
7431 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
7434 if (mips_relax.sequence != 2)
7436 if (mips_macro_warning.first_insn_sizes[0] == 0)
7437 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
7438 mips_macro_warning.sizes[0] += insn_length (ip);
7439 mips_macro_warning.insns[0]++;
7441 if (mips_relax.sequence != 1)
7443 if (mips_macro_warning.first_insn_sizes[1] == 0)
7444 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
7445 mips_macro_warning.sizes[1] += insn_length (ip);
7446 mips_macro_warning.insns[1]++;
7449 if (mips_opts.mips16)
7452 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
7454 add_fixed_insn (ip);
7457 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
7459 bfd_reloc_code_real_type final_type[3];
7460 reloc_howto_type *howto0;
7461 reloc_howto_type *howto;
7464 /* Perform any necessary conversion to microMIPS relocations
7465 and find out how many relocations there actually are. */
7466 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
7467 final_type[i] = micromips_map_reloc (reloc_type[i]);
7469 /* In a compound relocation, it is the final (outermost)
7470 operator that determines the relocated field. */
7471 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
7476 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
7477 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
7478 bfd_get_reloc_size (howto),
7480 howto0 && howto0->pc_relative,
7483 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
7484 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
7485 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
7487 /* These relocations can have an addend that won't fit in
7488 4 octets for 64bit assembly. */
7490 && ! howto->partial_inplace
7491 && (reloc_type[0] == BFD_RELOC_16
7492 || reloc_type[0] == BFD_RELOC_32
7493 || reloc_type[0] == BFD_RELOC_MIPS_JMP
7494 || reloc_type[0] == BFD_RELOC_GPREL16
7495 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
7496 || reloc_type[0] == BFD_RELOC_GPREL32
7497 || reloc_type[0] == BFD_RELOC_64
7498 || reloc_type[0] == BFD_RELOC_CTOR
7499 || reloc_type[0] == BFD_RELOC_MIPS_SUB
7500 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
7501 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
7502 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
7503 || reloc_type[0] == BFD_RELOC_MIPS_REL16
7504 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
7505 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
7506 || hi16_reloc_p (reloc_type[0])
7507 || lo16_reloc_p (reloc_type[0])))
7508 ip->fixp[0]->fx_no_overflow = 1;
7510 /* These relocations can have an addend that won't fit in 2 octets. */
7511 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
7512 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1)
7513 ip->fixp[0]->fx_no_overflow = 1;
7515 if (mips_relax.sequence)
7517 if (mips_relax.first_fixup == 0)
7518 mips_relax.first_fixup = ip->fixp[0];
7520 else if (reloc_needs_lo_p (*reloc_type))
7522 struct mips_hi_fixup *hi_fixup;
7524 /* Reuse the last entry if it already has a matching %lo. */
7525 hi_fixup = mips_hi_fixup_list;
7527 || !fixup_has_matching_lo_p (hi_fixup->fixp))
7529 hi_fixup = XNEW (struct mips_hi_fixup);
7530 hi_fixup->next = mips_hi_fixup_list;
7531 mips_hi_fixup_list = hi_fixup;
7533 hi_fixup->fixp = ip->fixp[0];
7534 hi_fixup->seg = now_seg;
7537 /* Add fixups for the second and third relocations, if given.
7538 Note that the ABI allows the second relocation to be
7539 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
7540 moment we only use RSS_UNDEF, but we could add support
7541 for the others if it ever becomes necessary. */
7542 for (i = 1; i < 3; i++)
7543 if (reloc_type[i] != BFD_RELOC_UNUSED)
7545 ip->fixp[i] = fix_new (ip->frag, ip->where,
7546 ip->fixp[0]->fx_size, NULL, 0,
7547 FALSE, final_type[i]);
7549 /* Use fx_tcbit to mark compound relocs. */
7550 ip->fixp[0]->fx_tcbit = 1;
7551 ip->fixp[i]->fx_tcbit = 1;
7555 /* Update the register mask information. */
7556 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
7557 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
7562 insert_into_history (0, 1, ip);
7565 case APPEND_ADD_WITH_NOP:
7567 struct mips_cl_insn *nop;
7569 insert_into_history (0, 1, ip);
7570 nop = get_delay_slot_nop (ip);
7571 add_fixed_insn (nop);
7572 insert_into_history (0, 1, nop);
7573 if (mips_relax.sequence)
7574 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
7578 case APPEND_ADD_COMPACT:
7579 /* Convert MIPS16 jr/jalr into a "compact" jump. */
7580 if (mips_opts.mips16)
7582 ip->insn_opcode |= 0x0080;
7583 find_altered_mips16_opcode (ip);
7585 /* Convert microMIPS instructions. */
7586 else if (mips_opts.micromips)
7589 if ((ip->insn_opcode & 0xffe0) == 0x4580)
7590 ip->insn_opcode |= 0x0020;
7592 else if ((ip->insn_opcode & 0xfc00) == 0xcc00)
7593 ip->insn_opcode = 0x40e00000;
7594 /* beqz16->beqzc, bnez16->bnezc */
7595 else if ((ip->insn_opcode & 0xdc00) == 0x8c00)
7597 unsigned long regno;
7599 regno = ip->insn_opcode >> MICROMIPSOP_SH_MD;
7600 regno &= MICROMIPSOP_MASK_MD;
7601 regno = micromips_to_32_reg_d_map[regno];
7602 ip->insn_opcode = (((ip->insn_opcode << 9) & 0x00400000)
7603 | (regno << MICROMIPSOP_SH_RS)
7604 | 0x40a00000) ^ 0x00400000;
7606 /* beqz->beqzc, bnez->bnezc */
7607 else if ((ip->insn_opcode & 0xdfe00000) == 0x94000000)
7608 ip->insn_opcode = ((ip->insn_opcode & 0x001f0000)
7609 | ((ip->insn_opcode >> 7) & 0x00400000)
7610 | 0x40a00000) ^ 0x00400000;
7611 /* beq $0->beqzc, bne $0->bnezc */
7612 else if ((ip->insn_opcode & 0xdc1f0000) == 0x94000000)
7613 ip->insn_opcode = (((ip->insn_opcode >>
7614 (MICROMIPSOP_SH_RT - MICROMIPSOP_SH_RS))
7615 & (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS))
7616 | ((ip->insn_opcode >> 7) & 0x00400000)
7617 | 0x40a00000) ^ 0x00400000;
7620 find_altered_micromips_opcode (ip);
7625 insert_into_history (0, 1, ip);
7630 struct mips_cl_insn delay = history[0];
7632 if (relaxed_branch || delay.frag != ip->frag)
7634 /* Add the delay slot instruction to the end of the
7635 current frag and shrink the fixed part of the
7636 original frag. If the branch occupies the tail of
7637 the latter, move it backwards to cover the gap. */
7638 delay.frag->fr_fix -= branch_disp;
7639 if (delay.frag == ip->frag)
7640 move_insn (ip, ip->frag, ip->where - branch_disp);
7641 add_fixed_insn (&delay);
7645 /* If this is not a relaxed branch and we are in the
7646 same frag, then just swap the instructions. */
7647 move_insn (ip, delay.frag, delay.where);
7648 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
7652 insert_into_history (0, 1, &delay);
7657 /* If we have just completed an unconditional branch, clear the history. */
7658 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
7659 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
7663 mips_no_prev_insn ();
7665 for (i = 0; i < ARRAY_SIZE (history); i++)
7666 history[i].cleared_p = 1;
7669 /* We need to emit a label at the end of branch-likely macros. */
7670 if (emit_branch_likely_macro)
7672 emit_branch_likely_macro = FALSE;
7673 micromips_add_label ();
7676 /* We just output an insn, so the next one doesn't have a label. */
7677 mips_clear_insn_labels ();
7680 /* Forget that there was any previous instruction or label.
7681 When BRANCH is true, the branch history is also flushed. */
7684 mips_no_prev_insn (void)
7686 prev_nop_frag = NULL;
7687 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
7688 mips_clear_insn_labels ();
7691 /* This function must be called before we emit something other than
7692 instructions. It is like mips_no_prev_insn except that it inserts
7693 any NOPS that might be needed by previous instructions. */
7696 mips_emit_delays (void)
7698 if (! mips_opts.noreorder)
7700 int nops = nops_for_insn (0, history, NULL);
7704 add_fixed_insn (NOP_INSN);
7705 mips_move_text_labels ();
7708 mips_no_prev_insn ();
7711 /* Start a (possibly nested) noreorder block. */
7714 start_noreorder (void)
7716 if (mips_opts.noreorder == 0)
7721 /* None of the instructions before the .set noreorder can be moved. */
7722 for (i = 0; i < ARRAY_SIZE (history); i++)
7723 history[i].fixed_p = 1;
7725 /* Insert any nops that might be needed between the .set noreorder
7726 block and the previous instructions. We will later remove any
7727 nops that turn out not to be needed. */
7728 nops = nops_for_insn (0, history, NULL);
7731 if (mips_optimize != 0)
7733 /* Record the frag which holds the nop instructions, so
7734 that we can remove them if we don't need them. */
7735 frag_grow (nops * NOP_INSN_SIZE);
7736 prev_nop_frag = frag_now;
7737 prev_nop_frag_holds = nops;
7738 prev_nop_frag_required = 0;
7739 prev_nop_frag_since = 0;
7742 for (; nops > 0; --nops)
7743 add_fixed_insn (NOP_INSN);
7745 /* Move on to a new frag, so that it is safe to simply
7746 decrease the size of prev_nop_frag. */
7747 frag_wane (frag_now);
7749 mips_move_text_labels ();
7751 mips_mark_labels ();
7752 mips_clear_insn_labels ();
7754 mips_opts.noreorder++;
7755 mips_any_noreorder = 1;
7758 /* End a nested noreorder block. */
7761 end_noreorder (void)
7763 mips_opts.noreorder--;
7764 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
7766 /* Commit to inserting prev_nop_frag_required nops and go back to
7767 handling nop insertion the .set reorder way. */
7768 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
7770 insert_into_history (prev_nop_frag_since,
7771 prev_nop_frag_required, NOP_INSN);
7772 prev_nop_frag = NULL;
7776 /* Sign-extend 32-bit mode constants that have bit 31 set and all
7777 higher bits unset. */
7780 normalize_constant_expr (expressionS *ex)
7782 if (ex->X_op == O_constant
7783 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7784 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7788 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
7789 all higher bits unset. */
7792 normalize_address_expr (expressionS *ex)
7794 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
7795 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
7796 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7797 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7801 /* Try to match TOKENS against OPCODE, storing the result in INSN.
7802 Return true if the match was successful.
7804 OPCODE_EXTRA is a value that should be ORed into the opcode
7805 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
7806 there are more alternatives after OPCODE and SOFT_MATCH is
7807 as for mips_arg_info. */
7810 match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
7811 struct mips_operand_token *tokens, unsigned int opcode_extra,
7812 bfd_boolean lax_match, bfd_boolean complete_p)
7815 struct mips_arg_info arg;
7816 const struct mips_operand *operand;
7819 imm_expr.X_op = O_absent;
7820 offset_expr.X_op = O_absent;
7821 offset_reloc[0] = BFD_RELOC_UNUSED;
7822 offset_reloc[1] = BFD_RELOC_UNUSED;
7823 offset_reloc[2] = BFD_RELOC_UNUSED;
7825 create_insn (insn, opcode);
7826 /* When no opcode suffix is specified, assume ".xyzw". */
7827 if ((opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0 && opcode_extra == 0)
7828 insn->insn_opcode |= 0xf << mips_vu0_channel_mask.lsb;
7830 insn->insn_opcode |= opcode_extra;
7831 memset (&arg, 0, sizeof (arg));
7835 arg.last_regno = ILLEGAL_REG;
7836 arg.dest_regno = ILLEGAL_REG;
7837 arg.lax_match = lax_match;
7838 for (args = opcode->args;; ++args)
7840 if (arg.token->type == OT_END)
7842 /* Handle unary instructions in which only one operand is given.
7843 The source is then the same as the destination. */
7844 if (arg.opnum == 1 && *args == ',')
7846 operand = (mips_opts.micromips
7847 ? decode_micromips_operand (args + 1)
7848 : decode_mips_operand (args + 1));
7849 if (operand && mips_optional_operand_p (operand))
7857 /* Treat elided base registers as $0. */
7858 if (strcmp (args, "(b)") == 0)
7866 /* The register suffix is optional. */
7871 /* Fail the match if there were too few operands. */
7875 /* Successful match. */
7878 clear_insn_error ();
7879 if (arg.dest_regno == arg.last_regno
7880 && strncmp (insn->insn_mo->name, "jalr", 4) == 0)
7884 (0, _("source and destination must be different"));
7885 else if (arg.last_regno == 31)
7887 (0, _("a destination register must be supplied"));
7889 else if (arg.last_regno == 31
7890 && (strncmp (insn->insn_mo->name, "bltzal", 6) == 0
7891 || strncmp (insn->insn_mo->name, "bgezal", 6) == 0))
7892 set_insn_error (0, _("the source register must not be $31"));
7893 check_completed_insn (&arg);
7897 /* Fail the match if the line has too many operands. */
7901 /* Handle characters that need to match exactly. */
7902 if (*args == '(' || *args == ')' || *args == ',')
7904 if (match_char (&arg, *args))
7911 if (arg.token->type == OT_DOUBLE_CHAR
7912 && arg.token->u.ch == *args)
7920 /* Handle special macro operands. Work out the properties of
7929 *offset_reloc = BFD_RELOC_MIPS_19_PCREL_S2;
7933 *offset_reloc = BFD_RELOC_MIPS_18_PCREL_S3;
7942 *offset_reloc = BFD_RELOC_MIPS_JMP;
7946 *offset_reloc = BFD_RELOC_MIPS_26_PCREL_S2;
7950 *offset_reloc = BFD_RELOC_MIPS_21_PCREL_S2;
7956 if (!match_const_int (&arg, &imm_expr.X_add_number))
7958 imm_expr.X_op = O_constant;
7960 normalize_constant_expr (&imm_expr);
7964 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
7966 /* Assume that the offset has been elided and that what
7967 we saw was a base register. The match will fail later
7968 if that assumption turns out to be wrong. */
7969 offset_expr.X_op = O_constant;
7970 offset_expr.X_add_number = 0;
7974 if (!match_expression (&arg, &offset_expr, offset_reloc))
7976 normalize_address_expr (&offset_expr);
7981 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7987 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7993 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7999 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
8005 *offset_reloc = BFD_RELOC_16_PCREL_S2;
8009 *offset_reloc = BFD_RELOC_MIPS_JMP;
8013 gas_assert (mips_opts.micromips);
8019 if (!forced_insn_length)
8020 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
8022 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
8024 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
8030 operand = (mips_opts.micromips
8031 ? decode_micromips_operand (args)
8032 : decode_mips_operand (args));
8036 /* Skip prefixes. */
8037 if (*args == '+' || *args == 'm' || *args == '-')
8040 if (mips_optional_operand_p (operand)
8042 && (arg.token[0].type != OT_REG
8043 || arg.token[1].type == OT_END))
8045 /* Assume that the register has been elided and is the
8046 same as the first operand. */
8051 if (!match_operand (&arg, operand))
8056 /* Like match_insn, but for MIPS16. */
8059 match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
8060 struct mips_operand_token *tokens)
8063 const struct mips_operand *operand;
8064 const struct mips_operand *ext_operand;
8065 int required_insn_length;
8066 struct mips_arg_info arg;
8069 if (forced_insn_length)
8070 required_insn_length = forced_insn_length;
8071 else if (mips_opts.noautoextend && !mips_opcode_32bit_p (opcode))
8072 required_insn_length = 2;
8074 required_insn_length = 0;
8076 create_insn (insn, opcode);
8077 imm_expr.X_op = O_absent;
8078 offset_expr.X_op = O_absent;
8079 offset_reloc[0] = BFD_RELOC_UNUSED;
8080 offset_reloc[1] = BFD_RELOC_UNUSED;
8081 offset_reloc[2] = BFD_RELOC_UNUSED;
8084 memset (&arg, 0, sizeof (arg));
8088 arg.last_regno = ILLEGAL_REG;
8089 arg.dest_regno = ILLEGAL_REG;
8091 for (args = opcode->args;; ++args)
8095 if (arg.token->type == OT_END)
8099 /* Handle unary instructions in which only one operand is given.
8100 The source is then the same as the destination. */
8101 if (arg.opnum == 1 && *args == ',')
8103 operand = decode_mips16_operand (args[1], FALSE);
8104 if (operand && mips_optional_operand_p (operand))
8112 /* Fail the match if there were too few operands. */
8116 /* Successful match. Stuff the immediate value in now, if
8118 clear_insn_error ();
8119 if (opcode->pinfo == INSN_MACRO)
8121 gas_assert (relax_char == 0 || relax_char == 'p');
8122 gas_assert (*offset_reloc == BFD_RELOC_UNUSED);
8125 && offset_expr.X_op == O_constant
8126 && calculate_reloc (*offset_reloc,
8127 offset_expr.X_add_number,
8130 mips16_immed (NULL, 0, relax_char, *offset_reloc, value,
8131 required_insn_length, &insn->insn_opcode);
8132 offset_expr.X_op = O_absent;
8133 *offset_reloc = BFD_RELOC_UNUSED;
8135 else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED)
8137 if (required_insn_length == 2)
8138 set_insn_error (0, _("invalid unextended operand value"));
8141 forced_insn_length = 4;
8142 insn->insn_opcode |= MIPS16_EXTEND;
8145 else if (relax_char)
8146 *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char;
8148 check_completed_insn (&arg);
8152 /* Fail the match if the line has too many operands. */
8156 /* Handle characters that need to match exactly. */
8157 if (*args == '(' || *args == ')' || *args == ',')
8159 if (match_char (&arg, *args))
8177 if (!match_const_int (&arg, &imm_expr.X_add_number))
8179 imm_expr.X_op = O_constant;
8181 normalize_constant_expr (&imm_expr);
8186 *offset_reloc = BFD_RELOC_MIPS16_JMP;
8190 operand = decode_mips16_operand (c, mips_opcode_32bit_p (opcode));
8194 if (operand->type != OP_PCREL)
8196 ext_operand = decode_mips16_operand (c, TRUE);
8197 if (operand != ext_operand)
8199 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
8201 offset_expr.X_op = O_constant;
8202 offset_expr.X_add_number = 0;
8207 /* We need the OT_INTEGER check because some MIPS16
8208 immediate variants are listed before the register ones. */
8209 if (arg.token->type != OT_INTEGER
8210 || !match_expression (&arg, &offset_expr, offset_reloc))
8213 /* '8' is used for SLTI(U) and has traditionally not
8214 been allowed to take relocation operators. */
8215 if (offset_reloc[0] != BFD_RELOC_UNUSED
8216 && (ext_operand->size != 16 || c == '8'))
8224 if (mips_optional_operand_p (operand)
8226 && (arg.token[0].type != OT_REG
8227 || arg.token[1].type == OT_END))
8229 /* Assume that the register has been elided and is the
8230 same as the first operand. */
8235 if (!match_operand (&arg, operand))
8240 /* Record that the current instruction is invalid for the current ISA. */
8243 match_invalid_for_isa (void)
8246 (0, _("opcode not supported on this processor: %s (%s)"),
8247 mips_cpu_info_from_arch (mips_opts.arch)->name,
8248 mips_cpu_info_from_isa (mips_opts.isa)->name);
8251 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8252 Return true if a definite match or failure was found, storing any match
8253 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8254 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8255 tried and failed to match under normal conditions and now want to try a
8256 more relaxed match. */
8259 match_insns (struct mips_cl_insn *insn, const struct mips_opcode *first,
8260 const struct mips_opcode *past, struct mips_operand_token *tokens,
8261 int opcode_extra, bfd_boolean lax_match)
8263 const struct mips_opcode *opcode;
8264 const struct mips_opcode *invalid_delay_slot;
8265 bfd_boolean seen_valid_for_isa, seen_valid_for_size;
8267 /* Search for a match, ignoring alternatives that don't satisfy the
8268 current ISA or forced_length. */
8269 invalid_delay_slot = 0;
8270 seen_valid_for_isa = FALSE;
8271 seen_valid_for_size = FALSE;
8275 gas_assert (strcmp (opcode->name, first->name) == 0);
8276 if (is_opcode_valid (opcode))
8278 seen_valid_for_isa = TRUE;
8279 if (is_size_valid (opcode))
8281 bfd_boolean delay_slot_ok;
8283 seen_valid_for_size = TRUE;
8284 delay_slot_ok = is_delay_slot_valid (opcode);
8285 if (match_insn (insn, opcode, tokens, opcode_extra,
8286 lax_match, delay_slot_ok))
8290 if (!invalid_delay_slot)
8291 invalid_delay_slot = opcode;
8300 while (opcode < past && strcmp (opcode->name, first->name) == 0);
8302 /* If the only matches we found had the wrong length for the delay slot,
8303 pick the first such match. We'll issue an appropriate warning later. */
8304 if (invalid_delay_slot)
8306 if (match_insn (insn, invalid_delay_slot, tokens, opcode_extra,
8312 /* Handle the case where we didn't try to match an instruction because
8313 all the alternatives were incompatible with the current ISA. */
8314 if (!seen_valid_for_isa)
8316 match_invalid_for_isa ();
8320 /* Handle the case where we didn't try to match an instruction because
8321 all the alternatives were of the wrong size. */
8322 if (!seen_valid_for_size)
8324 if (mips_opts.insn32)
8325 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
8328 (0, _("unrecognized %d-bit version of microMIPS opcode"),
8329 8 * forced_insn_length);
8336 /* Like match_insns, but for MIPS16. */
8339 match_mips16_insns (struct mips_cl_insn *insn, const struct mips_opcode *first,
8340 struct mips_operand_token *tokens)
8342 const struct mips_opcode *opcode;
8343 bfd_boolean seen_valid_for_isa;
8344 bfd_boolean seen_valid_for_size;
8346 /* Search for a match, ignoring alternatives that don't satisfy the
8347 current ISA. There are no separate entries for extended forms so
8348 we deal with forced_length later. */
8349 seen_valid_for_isa = FALSE;
8350 seen_valid_for_size = FALSE;
8354 gas_assert (strcmp (opcode->name, first->name) == 0);
8355 if (is_opcode_valid_16 (opcode))
8357 seen_valid_for_isa = TRUE;
8358 if (is_size_valid_16 (opcode))
8360 seen_valid_for_size = TRUE;
8361 if (match_mips16_insn (insn, opcode, tokens))
8367 while (opcode < &mips16_opcodes[bfd_mips16_num_opcodes]
8368 && strcmp (opcode->name, first->name) == 0);
8370 /* Handle the case where we didn't try to match an instruction because
8371 all the alternatives were incompatible with the current ISA. */
8372 if (!seen_valid_for_isa)
8374 match_invalid_for_isa ();
8378 /* Handle the case where we didn't try to match an instruction because
8379 all the alternatives were of the wrong size. */
8380 if (!seen_valid_for_size)
8382 if (forced_insn_length == 2)
8384 (0, _("unrecognized unextended version of MIPS16 opcode"));
8387 (0, _("unrecognized extended version of MIPS16 opcode"));
8394 /* Set up global variables for the start of a new macro. */
8399 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
8400 memset (&mips_macro_warning.first_insn_sizes, 0,
8401 sizeof (mips_macro_warning.first_insn_sizes));
8402 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
8403 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
8404 && delayed_branch_p (&history[0]));
8406 && history[0].frag->fr_type == rs_machine_dependent
8407 && RELAX_MICROMIPS_P (history[0].frag->fr_subtype)
8408 && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype))
8409 mips_macro_warning.delay_slot_length = 0;
8411 switch (history[0].insn_mo->pinfo2
8412 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
8414 case INSN2_BRANCH_DELAY_32BIT:
8415 mips_macro_warning.delay_slot_length = 4;
8417 case INSN2_BRANCH_DELAY_16BIT:
8418 mips_macro_warning.delay_slot_length = 2;
8421 mips_macro_warning.delay_slot_length = 0;
8424 mips_macro_warning.first_frag = NULL;
8427 /* Given that a macro is longer than one instruction or of the wrong size,
8428 return the appropriate warning for it. Return null if no warning is
8429 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8430 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8431 and RELAX_NOMACRO. */
8434 macro_warning (relax_substateT subtype)
8436 if (subtype & RELAX_DELAY_SLOT)
8437 return _("macro instruction expanded into multiple instructions"
8438 " in a branch delay slot");
8439 else if (subtype & RELAX_NOMACRO)
8440 return _("macro instruction expanded into multiple instructions");
8441 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
8442 | RELAX_DELAY_SLOT_SIZE_SECOND))
8443 return ((subtype & RELAX_DELAY_SLOT_16BIT)
8444 ? _("macro instruction expanded into a wrong size instruction"
8445 " in a 16-bit branch delay slot")
8446 : _("macro instruction expanded into a wrong size instruction"
8447 " in a 32-bit branch delay slot"));
8452 /* Finish up a macro. Emit warnings as appropriate. */
8457 /* Relaxation warning flags. */
8458 relax_substateT subtype = 0;
8460 /* Check delay slot size requirements. */
8461 if (mips_macro_warning.delay_slot_length == 2)
8462 subtype |= RELAX_DELAY_SLOT_16BIT;
8463 if (mips_macro_warning.delay_slot_length != 0)
8465 if (mips_macro_warning.delay_slot_length
8466 != mips_macro_warning.first_insn_sizes[0])
8467 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
8468 if (mips_macro_warning.delay_slot_length
8469 != mips_macro_warning.first_insn_sizes[1])
8470 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
8473 /* Check instruction count requirements. */
8474 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
8476 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
8477 subtype |= RELAX_SECOND_LONGER;
8478 if (mips_opts.warn_about_macros)
8479 subtype |= RELAX_NOMACRO;
8480 if (mips_macro_warning.delay_slot_p)
8481 subtype |= RELAX_DELAY_SLOT;
8484 /* If both alternatives fail to fill a delay slot correctly,
8485 emit the warning now. */
8486 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
8487 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
8492 s = subtype & (RELAX_DELAY_SLOT_16BIT
8493 | RELAX_DELAY_SLOT_SIZE_FIRST
8494 | RELAX_DELAY_SLOT_SIZE_SECOND);
8495 msg = macro_warning (s);
8497 as_warn ("%s", msg);
8501 /* If both implementations are longer than 1 instruction, then emit the
8503 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
8508 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
8509 msg = macro_warning (s);
8511 as_warn ("%s", msg);
8515 /* If any flags still set, then one implementation might need a warning
8516 and the other either will need one of a different kind or none at all.
8517 Pass any remaining flags over to relaxation. */
8518 if (mips_macro_warning.first_frag != NULL)
8519 mips_macro_warning.first_frag->fr_subtype |= subtype;
8522 /* Instruction operand formats used in macros that vary between
8523 standard MIPS and microMIPS code. */
8525 static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } };
8526 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
8527 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
8528 static const char * const lui_fmt[2] = { "t,u", "s,u" };
8529 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
8530 static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } };
8531 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
8532 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
8534 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
8535 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8536 : cop12_fmt[mips_opts.micromips])
8537 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
8538 #define LUI_FMT (lui_fmt[mips_opts.micromips])
8539 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
8540 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
8541 : mem12_fmt[mips_opts.micromips])
8542 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
8543 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
8544 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
8546 /* Read a macro's relocation codes from *ARGS and store them in *R.
8547 The first argument in *ARGS will be either the code for a single
8548 relocation or -1 followed by the three codes that make up a
8549 composite relocation. */
8552 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
8556 next = va_arg (*args, int);
8558 r[0] = (bfd_reloc_code_real_type) next;
8561 for (i = 0; i < 3; i++)
8562 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
8563 /* This function is only used for 16-bit relocation fields.
8564 To make the macro code simpler, treat an unrelocated value
8565 in the same way as BFD_RELOC_LO16. */
8566 if (r[0] == BFD_RELOC_UNUSED)
8567 r[0] = BFD_RELOC_LO16;
8571 /* Build an instruction created by a macro expansion. This is passed
8572 a pointer to the count of instructions created so far, an
8573 expression, the name of the instruction to build, an operand format
8574 string, and corresponding arguments. */
8577 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
8579 const struct mips_opcode *mo = NULL;
8580 bfd_reloc_code_real_type r[3];
8581 const struct mips_opcode *amo;
8582 const struct mips_operand *operand;
8583 struct hash_control *hash;
8584 struct mips_cl_insn insn;
8588 va_start (args, fmt);
8590 if (mips_opts.mips16)
8592 mips16_macro_build (ep, name, fmt, &args);
8597 r[0] = BFD_RELOC_UNUSED;
8598 r[1] = BFD_RELOC_UNUSED;
8599 r[2] = BFD_RELOC_UNUSED;
8600 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
8601 amo = (struct mips_opcode *) hash_find (hash, name);
8603 gas_assert (strcmp (name, amo->name) == 0);
8607 /* Search until we get a match for NAME. It is assumed here that
8608 macros will never generate MDMX, MIPS-3D, or MT instructions.
8609 We try to match an instruction that fulfils the branch delay
8610 slot instruction length requirement (if any) of the previous
8611 instruction. While doing this we record the first instruction
8612 seen that matches all the other conditions and use it anyway
8613 if the requirement cannot be met; we will issue an appropriate
8614 warning later on. */
8615 if (strcmp (fmt, amo->args) == 0
8616 && amo->pinfo != INSN_MACRO
8617 && is_opcode_valid (amo)
8618 && is_size_valid (amo))
8620 if (is_delay_slot_valid (amo))
8630 gas_assert (amo->name);
8632 while (strcmp (name, amo->name) == 0);
8635 create_insn (&insn, mo);
8648 macro_read_relocs (&args, r);
8649 gas_assert (*r == BFD_RELOC_GPREL16
8650 || *r == BFD_RELOC_MIPS_HIGHER
8651 || *r == BFD_RELOC_HI16_S
8652 || *r == BFD_RELOC_LO16
8653 || *r == BFD_RELOC_MIPS_GOT_OFST);
8657 macro_read_relocs (&args, r);
8661 macro_read_relocs (&args, r);
8662 gas_assert (ep != NULL
8663 && (ep->X_op == O_constant
8664 || (ep->X_op == O_symbol
8665 && (*r == BFD_RELOC_MIPS_HIGHEST
8666 || *r == BFD_RELOC_HI16_S
8667 || *r == BFD_RELOC_HI16
8668 || *r == BFD_RELOC_GPREL16
8669 || *r == BFD_RELOC_MIPS_GOT_HI16
8670 || *r == BFD_RELOC_MIPS_CALL_HI16))));
8674 gas_assert (ep != NULL);
8677 * This allows macro() to pass an immediate expression for
8678 * creating short branches without creating a symbol.
8680 * We don't allow branch relaxation for these branches, as
8681 * they should only appear in ".set nomacro" anyway.
8683 if (ep->X_op == O_constant)
8685 /* For microMIPS we always use relocations for branches.
8686 So we should not resolve immediate values. */
8687 gas_assert (!mips_opts.micromips);
8689 if ((ep->X_add_number & 3) != 0)
8690 as_bad (_("branch to misaligned address (0x%lx)"),
8691 (unsigned long) ep->X_add_number);
8692 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
8693 as_bad (_("branch address range overflow (0x%lx)"),
8694 (unsigned long) ep->X_add_number);
8695 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
8699 *r = BFD_RELOC_16_PCREL_S2;
8703 gas_assert (ep != NULL);
8704 *r = BFD_RELOC_MIPS_JMP;
8708 operand = (mips_opts.micromips
8709 ? decode_micromips_operand (fmt)
8710 : decode_mips_operand (fmt));
8714 uval = va_arg (args, int);
8715 if (operand->type == OP_CLO_CLZ_DEST)
8716 uval |= (uval << 5);
8717 insn_insert_operand (&insn, operand, uval);
8719 if (*fmt == '+' || *fmt == 'm' || *fmt == '-')
8725 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
8727 append_insn (&insn, ep, r, TRUE);
8731 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
8734 struct mips_opcode *mo;
8735 struct mips_cl_insn insn;
8736 const struct mips_operand *operand;
8737 bfd_reloc_code_real_type r[3]
8738 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
8740 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
8742 gas_assert (strcmp (name, mo->name) == 0);
8744 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
8747 gas_assert (mo->name);
8748 gas_assert (strcmp (name, mo->name) == 0);
8751 create_insn (&insn, mo);
8788 gas_assert (ep != NULL);
8790 if (ep->X_op != O_constant)
8791 *r = (int) BFD_RELOC_UNUSED + c;
8792 else if (calculate_reloc (*r, ep->X_add_number, &value))
8794 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode);
8796 *r = BFD_RELOC_UNUSED;
8802 operand = decode_mips16_operand (c, FALSE);
8806 insn_insert_operand (&insn, operand, va_arg (*args, int));
8811 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
8813 append_insn (&insn, ep, r, TRUE);
8817 * Generate a "jalr" instruction with a relocation hint to the called
8818 * function. This occurs in NewABI PIC code.
8821 macro_build_jalr (expressionS *ep, int cprestore)
8823 static const bfd_reloc_code_real_type jalr_relocs[2]
8824 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
8825 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
8829 if (MIPS_JALR_HINT_P (ep))
8834 if (mips_opts.micromips)
8836 jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32
8837 ? "jalr" : "jalrs");
8838 if (MIPS_JALR_HINT_P (ep)
8840 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
8841 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
8843 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
8846 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
8847 if (MIPS_JALR_HINT_P (ep))
8848 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
8852 * Generate a "lui" instruction.
8855 macro_build_lui (expressionS *ep, int regnum)
8857 gas_assert (! mips_opts.mips16);
8859 if (ep->X_op != O_constant)
8861 gas_assert (ep->X_op == O_symbol);
8862 /* _gp_disp is a special case, used from s_cpload.
8863 __gnu_local_gp is used if mips_no_shared. */
8864 gas_assert (mips_pic == NO_PIC
8866 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
8867 || (! mips_in_shared
8868 && strcmp (S_GET_NAME (ep->X_add_symbol),
8869 "__gnu_local_gp") == 0));
8872 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
8875 /* Generate a sequence of instructions to do a load or store from a constant
8876 offset off of a base register (breg) into/from a target register (treg),
8877 using AT if necessary. */
8879 macro_build_ldst_constoffset (expressionS *ep, const char *op,
8880 int treg, int breg, int dbl)
8882 gas_assert (ep->X_op == O_constant);
8884 /* Sign-extending 32-bit constants makes their handling easier. */
8886 normalize_constant_expr (ep);
8888 /* Right now, this routine can only handle signed 32-bit constants. */
8889 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
8890 as_warn (_("operand overflow"));
8892 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
8894 /* Signed 16-bit offset will fit in the op. Easy! */
8895 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8899 /* 32-bit offset, need multiple instructions and AT, like:
8900 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
8901 addu $tempreg,$tempreg,$breg
8902 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
8903 to handle the complete offset. */
8904 macro_build_lui (ep, AT);
8905 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8906 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8909 as_bad (_("macro used $at after \".set noat\""));
8914 * Generates code to set the $at register to true (one)
8915 * if reg is less than the immediate expression.
8918 set_at (int reg, int unsignedp)
8920 if (imm_expr.X_add_number >= -0x8000
8921 && imm_expr.X_add_number < 0x8000)
8922 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
8923 AT, reg, BFD_RELOC_LO16);
8926 load_register (AT, &imm_expr, GPR_SIZE == 64);
8927 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
8931 /* Count the leading zeroes by performing a binary chop. This is a
8932 bulky bit of source, but performance is a LOT better for the
8933 majority of values than a simple loop to count the bits:
8934 for (lcnt = 0; (lcnt < 32); lcnt++)
8935 if ((v) & (1 << (31 - lcnt)))
8937 However it is not code size friendly, and the gain will drop a bit
8938 on certain cached systems.
8940 #define COUNT_TOP_ZEROES(v) \
8941 (((v) & ~0xffff) == 0 \
8942 ? ((v) & ~0xff) == 0 \
8943 ? ((v) & ~0xf) == 0 \
8944 ? ((v) & ~0x3) == 0 \
8945 ? ((v) & ~0x1) == 0 \
8950 : ((v) & ~0x7) == 0 \
8953 : ((v) & ~0x3f) == 0 \
8954 ? ((v) & ~0x1f) == 0 \
8957 : ((v) & ~0x7f) == 0 \
8960 : ((v) & ~0xfff) == 0 \
8961 ? ((v) & ~0x3ff) == 0 \
8962 ? ((v) & ~0x1ff) == 0 \
8965 : ((v) & ~0x7ff) == 0 \
8968 : ((v) & ~0x3fff) == 0 \
8969 ? ((v) & ~0x1fff) == 0 \
8972 : ((v) & ~0x7fff) == 0 \
8975 : ((v) & ~0xffffff) == 0 \
8976 ? ((v) & ~0xfffff) == 0 \
8977 ? ((v) & ~0x3ffff) == 0 \
8978 ? ((v) & ~0x1ffff) == 0 \
8981 : ((v) & ~0x7ffff) == 0 \
8984 : ((v) & ~0x3fffff) == 0 \
8985 ? ((v) & ~0x1fffff) == 0 \
8988 : ((v) & ~0x7fffff) == 0 \
8991 : ((v) & ~0xfffffff) == 0 \
8992 ? ((v) & ~0x3ffffff) == 0 \
8993 ? ((v) & ~0x1ffffff) == 0 \
8996 : ((v) & ~0x7ffffff) == 0 \
8999 : ((v) & ~0x3fffffff) == 0 \
9000 ? ((v) & ~0x1fffffff) == 0 \
9003 : ((v) & ~0x7fffffff) == 0 \
9008 * This routine generates the least number of instructions necessary to load
9009 * an absolute expression value into a register.
9012 load_register (int reg, expressionS *ep, int dbl)
9015 expressionS hi32, lo32;
9017 if (ep->X_op != O_big)
9019 gas_assert (ep->X_op == O_constant);
9021 /* Sign-extending 32-bit constants makes their handling easier. */
9023 normalize_constant_expr (ep);
9025 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
9027 /* We can handle 16 bit signed values with an addiu to
9028 $zero. No need to ever use daddiu here, since $zero and
9029 the result are always correct in 32 bit mode. */
9030 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
9033 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
9035 /* We can handle 16 bit unsigned values with an ori to
9037 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
9040 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
9042 /* 32 bit values require an lui. */
9043 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
9044 if ((ep->X_add_number & 0xffff) != 0)
9045 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
9050 /* The value is larger than 32 bits. */
9052 if (!dbl || GPR_SIZE == 32)
9056 sprintf_vma (value, ep->X_add_number);
9057 as_bad (_("number (0x%s) larger than 32 bits"), value);
9058 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
9062 if (ep->X_op != O_big)
9065 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
9066 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
9067 hi32.X_add_number &= 0xffffffff;
9069 lo32.X_add_number &= 0xffffffff;
9073 gas_assert (ep->X_add_number > 2);
9074 if (ep->X_add_number == 3)
9075 generic_bignum[3] = 0;
9076 else if (ep->X_add_number > 4)
9077 as_bad (_("number larger than 64 bits"));
9078 lo32.X_op = O_constant;
9079 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
9080 hi32.X_op = O_constant;
9081 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
9084 if (hi32.X_add_number == 0)
9089 unsigned long hi, lo;
9091 if (hi32.X_add_number == (offsetT) 0xffffffff)
9093 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
9095 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
9098 if (lo32.X_add_number & 0x80000000)
9100 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
9101 if (lo32.X_add_number & 0xffff)
9102 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
9107 /* Check for 16bit shifted constant. We know that hi32 is
9108 non-zero, so start the mask on the first bit of the hi32
9113 unsigned long himask, lomask;
9117 himask = 0xffff >> (32 - shift);
9118 lomask = (0xffff << shift) & 0xffffffff;
9122 himask = 0xffff << (shift - 32);
9125 if ((hi32.X_add_number & ~(offsetT) himask) == 0
9126 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
9130 tmp.X_op = O_constant;
9132 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
9133 | (lo32.X_add_number >> shift));
9135 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
9136 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
9137 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
9138 reg, reg, (shift >= 32) ? shift - 32 : shift);
9143 while (shift <= (64 - 16));
9145 /* Find the bit number of the lowest one bit, and store the
9146 shifted value in hi/lo. */
9147 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
9148 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
9152 while ((lo & 1) == 0)
9157 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
9163 while ((hi & 1) == 0)
9172 /* Optimize if the shifted value is a (power of 2) - 1. */
9173 if ((hi == 0 && ((lo + 1) & lo) == 0)
9174 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
9176 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
9181 /* This instruction will set the register to be all
9183 tmp.X_op = O_constant;
9184 tmp.X_add_number = (offsetT) -1;
9185 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
9189 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
9190 reg, reg, (bit >= 32) ? bit - 32 : bit);
9192 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
9193 reg, reg, (shift >= 32) ? shift - 32 : shift);
9198 /* Sign extend hi32 before calling load_register, because we can
9199 generally get better code when we load a sign extended value. */
9200 if ((hi32.X_add_number & 0x80000000) != 0)
9201 hi32.X_add_number |= ~(offsetT) 0xffffffff;
9202 load_register (reg, &hi32, 0);
9205 if ((lo32.X_add_number & 0xffff0000) == 0)
9209 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
9217 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
9219 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
9220 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
9226 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
9230 mid16.X_add_number >>= 16;
9231 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
9232 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
9235 if ((lo32.X_add_number & 0xffff) != 0)
9236 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
9240 load_delay_nop (void)
9242 if (!gpr_interlocks)
9243 macro_build (NULL, "nop", "");
9246 /* Load an address into a register. */
9249 load_address (int reg, expressionS *ep, int *used_at)
9251 if (ep->X_op != O_constant
9252 && ep->X_op != O_symbol)
9254 as_bad (_("expression too complex"));
9255 ep->X_op = O_constant;
9258 if (ep->X_op == O_constant)
9260 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
9264 if (mips_pic == NO_PIC)
9266 /* If this is a reference to a GP relative symbol, we want
9267 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
9269 lui $reg,<sym> (BFD_RELOC_HI16_S)
9270 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9271 If we have an addend, we always use the latter form.
9273 With 64bit address space and a usable $at we want
9274 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9275 lui $at,<sym> (BFD_RELOC_HI16_S)
9276 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9277 daddiu $at,<sym> (BFD_RELOC_LO16)
9281 If $at is already in use, we use a path which is suboptimal
9282 on superscalar processors.
9283 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9284 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9286 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9288 daddiu $reg,<sym> (BFD_RELOC_LO16)
9290 For GP relative symbols in 64bit address space we can use
9291 the same sequence as in 32bit address space. */
9292 if (HAVE_64BIT_SYMBOLS)
9294 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
9295 && !nopic_need_relax (ep->X_add_symbol, 1))
9297 relax_start (ep->X_add_symbol);
9298 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
9299 mips_gp_register, BFD_RELOC_GPREL16);
9303 if (*used_at == 0 && mips_opts.at)
9305 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
9306 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
9307 macro_build (ep, "daddiu", "t,r,j", reg, reg,
9308 BFD_RELOC_MIPS_HIGHER);
9309 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
9310 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
9311 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
9316 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
9317 macro_build (ep, "daddiu", "t,r,j", reg, reg,
9318 BFD_RELOC_MIPS_HIGHER);
9319 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
9320 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
9321 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
9322 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
9325 if (mips_relax.sequence)
9330 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
9331 && !nopic_need_relax (ep->X_add_symbol, 1))
9333 relax_start (ep->X_add_symbol);
9334 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
9335 mips_gp_register, BFD_RELOC_GPREL16);
9338 macro_build_lui (ep, reg);
9339 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
9340 reg, reg, BFD_RELOC_LO16);
9341 if (mips_relax.sequence)
9345 else if (!mips_big_got)
9349 /* If this is a reference to an external symbol, we want
9350 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9352 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9354 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9355 If there is a constant, it must be added in after.
9357 If we have NewABI, we want
9358 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9359 unless we're referencing a global symbol with a non-zero
9360 offset, in which case cst must be added separately. */
9363 if (ep->X_add_number)
9365 ex.X_add_number = ep->X_add_number;
9366 ep->X_add_number = 0;
9367 relax_start (ep->X_add_symbol);
9368 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9369 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9370 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9371 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9372 ex.X_op = O_constant;
9373 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
9374 reg, reg, BFD_RELOC_LO16);
9375 ep->X_add_number = ex.X_add_number;
9378 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9379 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9380 if (mips_relax.sequence)
9385 ex.X_add_number = ep->X_add_number;
9386 ep->X_add_number = 0;
9387 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9388 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9390 relax_start (ep->X_add_symbol);
9392 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9396 if (ex.X_add_number != 0)
9398 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9399 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9400 ex.X_op = O_constant;
9401 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
9402 reg, reg, BFD_RELOC_LO16);
9406 else if (mips_big_got)
9410 /* This is the large GOT case. If this is a reference to an
9411 external symbol, we want
9412 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9414 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
9416 Otherwise, for a reference to a local symbol in old ABI, we want
9417 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9419 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9420 If there is a constant, it must be added in after.
9422 In the NewABI, for local symbols, with or without offsets, we want:
9423 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9424 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9428 ex.X_add_number = ep->X_add_number;
9429 ep->X_add_number = 0;
9430 relax_start (ep->X_add_symbol);
9431 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
9432 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9433 reg, reg, mips_gp_register);
9434 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
9435 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
9436 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9437 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9438 else if (ex.X_add_number)
9440 ex.X_op = O_constant;
9441 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9445 ep->X_add_number = ex.X_add_number;
9447 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9448 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
9449 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9450 BFD_RELOC_MIPS_GOT_OFST);
9455 ex.X_add_number = ep->X_add_number;
9456 ep->X_add_number = 0;
9457 relax_start (ep->X_add_symbol);
9458 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
9459 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9460 reg, reg, mips_gp_register);
9461 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
9462 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
9464 if (reg_needs_delay (mips_gp_register))
9466 /* We need a nop before loading from $gp. This special
9467 check is required because the lui which starts the main
9468 instruction stream does not refer to $gp, and so will not
9469 insert the nop which may be required. */
9470 macro_build (NULL, "nop", "");
9472 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9473 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9475 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9479 if (ex.X_add_number != 0)
9481 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9482 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9483 ex.X_op = O_constant;
9484 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9492 if (!mips_opts.at && *used_at == 1)
9493 as_bad (_("macro used $at after \".set noat\""));
9496 /* Move the contents of register SOURCE into register DEST. */
9499 move_register (int dest, int source)
9501 /* Prefer to use a 16-bit microMIPS instruction unless the previous
9502 instruction specifically requires a 32-bit one. */
9503 if (mips_opts.micromips
9504 && !mips_opts.insn32
9505 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
9506 macro_build (NULL, "move", "mp,mj", dest, source);
9508 macro_build (NULL, "or", "d,v,t", dest, source, 0);
9511 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
9512 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
9513 The two alternatives are:
9515 Global symbol Local sybmol
9516 ------------- ------------
9517 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
9519 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
9521 load_got_offset emits the first instruction and add_got_offset
9522 emits the second for a 16-bit offset or add_got_offset_hilo emits
9523 a sequence to add a 32-bit offset using a scratch register. */
9526 load_got_offset (int dest, expressionS *local)
9531 global.X_add_number = 0;
9533 relax_start (local->X_add_symbol);
9534 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
9535 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9537 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
9538 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9543 add_got_offset (int dest, expressionS *local)
9547 global.X_op = O_constant;
9548 global.X_op_symbol = NULL;
9549 global.X_add_symbol = NULL;
9550 global.X_add_number = local->X_add_number;
9552 relax_start (local->X_add_symbol);
9553 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
9554 dest, dest, BFD_RELOC_LO16);
9556 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
9561 add_got_offset_hilo (int dest, expressionS *local, int tmp)
9564 int hold_mips_optimize;
9566 global.X_op = O_constant;
9567 global.X_op_symbol = NULL;
9568 global.X_add_symbol = NULL;
9569 global.X_add_number = local->X_add_number;
9571 relax_start (local->X_add_symbol);
9572 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
9574 /* Set mips_optimize around the lui instruction to avoid
9575 inserting an unnecessary nop after the lw. */
9576 hold_mips_optimize = mips_optimize;
9578 macro_build_lui (&global, tmp);
9579 mips_optimize = hold_mips_optimize;
9580 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
9583 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
9586 /* Emit a sequence of instructions to emulate a branch likely operation.
9587 BR is an ordinary branch corresponding to one to be emulated. BRNEG
9588 is its complementing branch with the original condition negated.
9589 CALL is set if the original branch specified the link operation.
9590 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
9592 Code like this is produced in the noreorder mode:
9597 delay slot (executed only if branch taken)
9605 delay slot (executed only if branch taken)
9608 In the reorder mode the delay slot would be filled with a nop anyway,
9609 so code produced is simply:
9614 This function is used when producing code for the microMIPS ASE that
9615 does not implement branch likely instructions in hardware. */
9618 macro_build_branch_likely (const char *br, const char *brneg,
9619 int call, expressionS *ep, const char *fmt,
9620 unsigned int sreg, unsigned int treg)
9622 int noreorder = mips_opts.noreorder;
9625 gas_assert (mips_opts.micromips);
9629 micromips_label_expr (&expr1);
9630 macro_build (&expr1, brneg, fmt, sreg, treg);
9631 macro_build (NULL, "nop", "");
9632 macro_build (ep, call ? "bal" : "b", "p");
9634 /* Set to true so that append_insn adds a label. */
9635 emit_branch_likely_macro = TRUE;
9639 macro_build (ep, br, fmt, sreg, treg);
9640 macro_build (NULL, "nop", "");
9645 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
9646 the condition code tested. EP specifies the branch target. */
9649 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
9676 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
9679 /* Emit a two-argument branch macro specified by TYPE, using SREG as
9680 the register tested. EP specifies the branch target. */
9683 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
9685 const char *brneg = NULL;
9695 br = mips_opts.micromips ? "bgez" : "bgezl";
9699 gas_assert (mips_opts.micromips);
9700 br = mips_opts.insn32 ? "bgezal" : "bgezals";
9708 br = mips_opts.micromips ? "bgtz" : "bgtzl";
9715 br = mips_opts.micromips ? "blez" : "blezl";
9722 br = mips_opts.micromips ? "bltz" : "bltzl";
9726 gas_assert (mips_opts.micromips);
9727 br = mips_opts.insn32 ? "bltzal" : "bltzals";
9734 if (mips_opts.micromips && brneg)
9735 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
9737 macro_build (ep, br, "s,p", sreg);
9740 /* Emit a three-argument branch macro specified by TYPE, using SREG and
9741 TREG as the registers tested. EP specifies the branch target. */
9744 macro_build_branch_rsrt (int type, expressionS *ep,
9745 unsigned int sreg, unsigned int treg)
9747 const char *brneg = NULL;
9759 br = mips_opts.micromips ? "beq" : "beql";
9768 br = mips_opts.micromips ? "bne" : "bnel";
9774 if (mips_opts.micromips && brneg)
9775 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
9777 macro_build (ep, br, "s,t,p", sreg, treg);
9780 /* Return the high part that should be loaded in order to make the low
9781 part of VALUE accessible using an offset of OFFBITS bits. */
9784 offset_high_part (offsetT value, unsigned int offbits)
9791 bias = 1 << (offbits - 1);
9792 low_mask = bias * 2 - 1;
9793 return (value + bias) & ~low_mask;
9796 /* Return true if the value stored in offset_expr and offset_reloc
9797 fits into a signed offset of OFFBITS bits. RANGE is the maximum
9798 amount that the caller wants to add without inducing overflow
9799 and ALIGN is the known alignment of the value in bytes. */
9802 small_offset_p (unsigned int range, unsigned int align, unsigned int offbits)
9806 /* Accept any relocation operator if overflow isn't a concern. */
9807 if (range < align && *offset_reloc != BFD_RELOC_UNUSED)
9810 /* These relocations are guaranteed not to overflow in correct links. */
9811 if (*offset_reloc == BFD_RELOC_MIPS_LITERAL
9812 || gprel16_reloc_p (*offset_reloc))
9815 if (offset_expr.X_op == O_constant
9816 && offset_high_part (offset_expr.X_add_number, offbits) == 0
9817 && offset_high_part (offset_expr.X_add_number + range, offbits) == 0)
9824 * This routine implements the seemingly endless macro or synthesized
9825 * instructions and addressing modes in the mips assembly language. Many
9826 * of these macros are simple and are similar to each other. These could
9827 * probably be handled by some kind of table or grammar approach instead of
9828 * this verbose method. Others are not simple macros but are more like
9829 * optimizing code generation.
9830 * One interesting optimization is when several store macros appear
9831 * consecutively that would load AT with the upper half of the same address.
9832 * The ensuing load upper instructions are omitted. This implies some kind
9833 * of global optimization. We currently only optimize within a single macro.
9834 * For many of the load and store macros if the address is specified as a
9835 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
9836 * first load register 'at' with zero and use it as the base register. The
9837 * mips assembler simply uses register $zero. Just one tiny optimization
9841 macro (struct mips_cl_insn *ip, char *str)
9843 const struct mips_operand_array *operands;
9844 unsigned int breg, i;
9845 unsigned int tempreg;
9848 expressionS label_expr;
9863 bfd_boolean large_offset;
9865 int hold_mips_optimize;
9867 unsigned int op[MAX_OPERANDS];
9869 gas_assert (! mips_opts.mips16);
9871 operands = insn_operands (ip);
9872 for (i = 0; i < MAX_OPERANDS; i++)
9873 if (operands->operand[i])
9874 op[i] = insn_extract_operand (ip, operands->operand[i]);
9878 mask = ip->insn_mo->mask;
9880 label_expr.X_op = O_constant;
9881 label_expr.X_op_symbol = NULL;
9882 label_expr.X_add_symbol = NULL;
9883 label_expr.X_add_number = 0;
9885 expr1.X_op = O_constant;
9886 expr1.X_op_symbol = NULL;
9887 expr1.X_add_symbol = NULL;
9888 expr1.X_add_number = 1;
9905 if (mips_opts.micromips)
9906 micromips_label_expr (&label_expr);
9908 label_expr.X_add_number = 8;
9909 macro_build (&label_expr, "bgez", "s,p", op[1]);
9911 macro_build (NULL, "nop", "");
9913 move_register (op[0], op[1]);
9914 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", op[0], 0, op[1]);
9915 if (mips_opts.micromips)
9916 micromips_add_label ();
9933 if (!mips_opts.micromips)
9935 if (imm_expr.X_add_number >= -0x200
9936 && imm_expr.X_add_number < 0x200)
9938 macro_build (NULL, s, "t,r,.", op[0], op[1],
9939 (int) imm_expr.X_add_number);
9948 if (imm_expr.X_add_number >= -0x8000
9949 && imm_expr.X_add_number < 0x8000)
9951 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
9956 load_register (AT, &imm_expr, dbl);
9957 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
9976 if (imm_expr.X_add_number >= 0
9977 && imm_expr.X_add_number < 0x10000)
9979 if (mask != M_NOR_I)
9980 macro_build (&imm_expr, s, "t,r,i", op[0], op[1], BFD_RELOC_LO16);
9983 macro_build (&imm_expr, "ori", "t,r,i",
9984 op[0], op[1], BFD_RELOC_LO16);
9985 macro_build (NULL, "nor", "d,v,t", op[0], op[0], 0);
9991 load_register (AT, &imm_expr, GPR_SIZE == 64);
9992 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
9996 switch (imm_expr.X_add_number)
9999 macro_build (NULL, "nop", "");
10002 macro_build (NULL, "packrl.ph", "d,s,t", op[0], op[0], op[1]);
10006 macro_build (NULL, "balign", "t,s,2", op[0], op[1],
10007 (int) imm_expr.X_add_number);
10010 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
10011 (unsigned long) imm_expr.X_add_number);
10020 gas_assert (mips_opts.micromips);
10021 macro_build_branch_ccl (mask, &offset_expr,
10022 EXTRACT_OPERAND (1, BCC, *ip));
10029 if (imm_expr.X_add_number == 0)
10035 load_register (op[1], &imm_expr, GPR_SIZE == 64);
10037 /* Fall through. */
10040 macro_build_branch_rsrt (mask, &offset_expr, op[0], op[1]);
10045 /* Fall through. */
10048 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[0]);
10049 else if (op[0] == 0)
10050 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[1]);
10054 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
10055 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10056 &offset_expr, AT, ZERO);
10066 macro_build_branch_rs (mask, &offset_expr, op[0]);
10071 /* Fall through. */
10073 /* Check for > max integer. */
10074 if (imm_expr.X_add_number >= GPR_SMAX)
10077 /* Result is always false. */
10079 macro_build (NULL, "nop", "");
10081 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
10084 ++imm_expr.X_add_number;
10088 if (mask == M_BGEL_I)
10090 if (imm_expr.X_add_number == 0)
10092 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
10093 &offset_expr, op[0]);
10096 if (imm_expr.X_add_number == 1)
10098 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
10099 &offset_expr, op[0]);
10102 if (imm_expr.X_add_number <= GPR_SMIN)
10105 /* result is always true */
10106 as_warn (_("branch %s is always true"), ip->insn_mo->name);
10107 macro_build (&offset_expr, "b", "p");
10112 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10113 &offset_expr, AT, ZERO);
10118 /* Fall through. */
10122 else if (op[0] == 0)
10123 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10124 &offset_expr, ZERO, op[1]);
10128 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
10129 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10130 &offset_expr, AT, ZERO);
10136 /* Fall through. */
10140 && imm_expr.X_add_number == -1))
10142 ++imm_expr.X_add_number;
10146 if (mask == M_BGEUL_I)
10148 if (imm_expr.X_add_number == 0)
10150 else if (imm_expr.X_add_number == 1)
10151 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10152 &offset_expr, op[0], ZERO);
10157 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10158 &offset_expr, AT, ZERO);
10164 /* Fall through. */
10167 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[0]);
10168 else if (op[0] == 0)
10169 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[1]);
10173 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
10174 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10175 &offset_expr, AT, ZERO);
10181 /* Fall through. */
10184 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10185 &offset_expr, op[0], ZERO);
10186 else if (op[0] == 0)
10191 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
10192 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10193 &offset_expr, AT, ZERO);
10199 /* Fall through. */
10202 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
10203 else if (op[0] == 0)
10204 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[1]);
10208 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
10209 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10210 &offset_expr, AT, ZERO);
10216 /* Fall through. */
10218 if (imm_expr.X_add_number >= GPR_SMAX)
10220 ++imm_expr.X_add_number;
10224 if (mask == M_BLTL_I)
10226 if (imm_expr.X_add_number == 0)
10227 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
10228 else if (imm_expr.X_add_number == 1)
10229 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
10234 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10235 &offset_expr, AT, ZERO);
10241 /* Fall through. */
10244 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10245 &offset_expr, op[0], ZERO);
10246 else if (op[0] == 0)
10251 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
10252 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10253 &offset_expr, AT, ZERO);
10259 /* Fall through. */
10263 && imm_expr.X_add_number == -1))
10265 ++imm_expr.X_add_number;
10269 if (mask == M_BLTUL_I)
10271 if (imm_expr.X_add_number == 0)
10273 else if (imm_expr.X_add_number == 1)
10274 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10275 &offset_expr, op[0], ZERO);
10280 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10281 &offset_expr, AT, ZERO);
10287 /* Fall through. */
10290 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
10291 else if (op[0] == 0)
10292 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[1]);
10296 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
10297 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10298 &offset_expr, AT, ZERO);
10304 /* Fall through. */
10308 else if (op[0] == 0)
10309 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10310 &offset_expr, ZERO, op[1]);
10314 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
10315 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10316 &offset_expr, AT, ZERO);
10322 /* Fall through. */
10328 /* Fall through. */
10334 as_warn (_("divide by zero"));
10336 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
10338 macro_build (NULL, "break", BRK_FMT, 7);
10342 start_noreorder ();
10345 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
10346 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
10350 if (mips_opts.micromips)
10351 micromips_label_expr (&label_expr);
10353 label_expr.X_add_number = 8;
10354 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
10355 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
10356 macro_build (NULL, "break", BRK_FMT, 7);
10357 if (mips_opts.micromips)
10358 micromips_add_label ();
10360 expr1.X_add_number = -1;
10362 load_register (AT, &expr1, dbl);
10363 if (mips_opts.micromips)
10364 micromips_label_expr (&label_expr);
10366 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
10367 macro_build (&label_expr, "bne", "s,t,p", op[2], AT);
10370 expr1.X_add_number = 1;
10371 load_register (AT, &expr1, dbl);
10372 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
10376 expr1.X_add_number = 0x80000000;
10377 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
10381 macro_build (NULL, "teq", TRAP_FMT, op[1], AT, 6);
10382 /* We want to close the noreorder block as soon as possible, so
10383 that later insns are available for delay slot filling. */
10388 if (mips_opts.micromips)
10389 micromips_label_expr (&label_expr);
10391 label_expr.X_add_number = 8;
10392 macro_build (&label_expr, "bne", "s,t,p", op[1], AT);
10393 macro_build (NULL, "nop", "");
10395 /* We want to close the noreorder block as soon as possible, so
10396 that later insns are available for delay slot filling. */
10399 macro_build (NULL, "break", BRK_FMT, 6);
10401 if (mips_opts.micromips)
10402 micromips_add_label ();
10403 macro_build (NULL, s, MFHL_FMT, op[0]);
10442 if (imm_expr.X_add_number == 0)
10444 as_warn (_("divide by zero"));
10446 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
10448 macro_build (NULL, "break", BRK_FMT, 7);
10451 if (imm_expr.X_add_number == 1)
10453 if (strcmp (s2, "mflo") == 0)
10454 move_register (op[0], op[1]);
10456 move_register (op[0], ZERO);
10459 if (imm_expr.X_add_number == -1 && s[strlen (s) - 1] != 'u')
10461 if (strcmp (s2, "mflo") == 0)
10462 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", op[0], op[1]);
10464 move_register (op[0], ZERO);
10469 load_register (AT, &imm_expr, dbl);
10470 macro_build (NULL, s, "z,s,t", op[1], AT);
10471 macro_build (NULL, s2, MFHL_FMT, op[0]);
10490 start_noreorder ();
10493 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
10494 macro_build (NULL, s, "z,s,t", op[1], op[2]);
10495 /* We want to close the noreorder block as soon as possible, so
10496 that later insns are available for delay slot filling. */
10501 if (mips_opts.micromips)
10502 micromips_label_expr (&label_expr);
10504 label_expr.X_add_number = 8;
10505 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
10506 macro_build (NULL, s, "z,s,t", op[1], op[2]);
10508 /* We want to close the noreorder block as soon as possible, so
10509 that later insns are available for delay slot filling. */
10511 macro_build (NULL, "break", BRK_FMT, 7);
10512 if (mips_opts.micromips)
10513 micromips_add_label ();
10515 macro_build (NULL, s2, MFHL_FMT, op[0]);
10520 /* Fall through. */
10526 /* Fall through. */
10529 /* Load the address of a symbol into a register. If breg is not
10530 zero, we then add a base register to it. */
10533 if (dbl && GPR_SIZE == 32)
10534 as_warn (_("dla used to load 32-bit register; recommend using la "
10537 if (!dbl && HAVE_64BIT_OBJECTS)
10538 as_warn (_("la used to load 64-bit address; recommend using dla "
10541 if (small_offset_p (0, align, 16))
10543 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", op[0], breg,
10544 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
10548 if (mips_opts.at && (op[0] == breg))
10556 if (offset_expr.X_op != O_symbol
10557 && offset_expr.X_op != O_constant)
10559 as_bad (_("expression too complex"));
10560 offset_expr.X_op = O_constant;
10563 if (offset_expr.X_op == O_constant)
10564 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
10565 else if (mips_pic == NO_PIC)
10567 /* If this is a reference to a GP relative symbol, we want
10568 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
10570 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10571 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10572 If we have a constant, we need two instructions anyhow,
10573 so we may as well always use the latter form.
10575 With 64bit address space and a usable $at we want
10576 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10577 lui $at,<sym> (BFD_RELOC_HI16_S)
10578 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10579 daddiu $at,<sym> (BFD_RELOC_LO16)
10581 daddu $tempreg,$tempreg,$at
10583 If $at is already in use, we use a path which is suboptimal
10584 on superscalar processors.
10585 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10586 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10588 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10590 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
10592 For GP relative symbols in 64bit address space we can use
10593 the same sequence as in 32bit address space. */
10594 if (HAVE_64BIT_SYMBOLS)
10596 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10597 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10599 relax_start (offset_expr.X_add_symbol);
10600 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10601 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
10605 if (used_at == 0 && mips_opts.at)
10607 macro_build (&offset_expr, "lui", LUI_FMT,
10608 tempreg, BFD_RELOC_MIPS_HIGHEST);
10609 macro_build (&offset_expr, "lui", LUI_FMT,
10610 AT, BFD_RELOC_HI16_S);
10611 macro_build (&offset_expr, "daddiu", "t,r,j",
10612 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
10613 macro_build (&offset_expr, "daddiu", "t,r,j",
10614 AT, AT, BFD_RELOC_LO16);
10615 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
10616 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
10621 macro_build (&offset_expr, "lui", LUI_FMT,
10622 tempreg, BFD_RELOC_MIPS_HIGHEST);
10623 macro_build (&offset_expr, "daddiu", "t,r,j",
10624 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
10625 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
10626 macro_build (&offset_expr, "daddiu", "t,r,j",
10627 tempreg, tempreg, BFD_RELOC_HI16_S);
10628 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
10629 macro_build (&offset_expr, "daddiu", "t,r,j",
10630 tempreg, tempreg, BFD_RELOC_LO16);
10633 if (mips_relax.sequence)
10638 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10639 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10641 relax_start (offset_expr.X_add_symbol);
10642 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10643 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
10646 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
10647 as_bad (_("offset too large"));
10648 macro_build_lui (&offset_expr, tempreg);
10649 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10650 tempreg, tempreg, BFD_RELOC_LO16);
10651 if (mips_relax.sequence)
10655 else if (!mips_big_got && !HAVE_NEWABI)
10657 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
10659 /* If this is a reference to an external symbol, and there
10660 is no constant, we want
10661 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10662 or for lca or if tempreg is PIC_CALL_REG
10663 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10664 For a local symbol, we want
10665 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10667 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10669 If we have a small constant, and this is a reference to
10670 an external symbol, we want
10671 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10673 addiu $tempreg,$tempreg,<constant>
10674 For a local symbol, we want the same instruction
10675 sequence, but we output a BFD_RELOC_LO16 reloc on the
10678 If we have a large constant, and this is a reference to
10679 an external symbol, we want
10680 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10681 lui $at,<hiconstant>
10682 addiu $at,$at,<loconstant>
10683 addu $tempreg,$tempreg,$at
10684 For a local symbol, we want the same instruction
10685 sequence, but we output a BFD_RELOC_LO16 reloc on the
10689 if (offset_expr.X_add_number == 0)
10691 if (mips_pic == SVR4_PIC
10693 && (call || tempreg == PIC_CALL_REG))
10694 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
10696 relax_start (offset_expr.X_add_symbol);
10697 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10698 lw_reloc_type, mips_gp_register);
10701 /* We're going to put in an addu instruction using
10702 tempreg, so we may as well insert the nop right
10707 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10708 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
10710 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10711 tempreg, tempreg, BFD_RELOC_LO16);
10713 /* FIXME: If breg == 0, and the next instruction uses
10714 $tempreg, then if this variant case is used an extra
10715 nop will be generated. */
10717 else if (offset_expr.X_add_number >= -0x8000
10718 && offset_expr.X_add_number < 0x8000)
10720 load_got_offset (tempreg, &offset_expr);
10722 add_got_offset (tempreg, &offset_expr);
10726 expr1.X_add_number = offset_expr.X_add_number;
10727 offset_expr.X_add_number =
10728 SEXT_16BIT (offset_expr.X_add_number);
10729 load_got_offset (tempreg, &offset_expr);
10730 offset_expr.X_add_number = expr1.X_add_number;
10731 /* If we are going to add in a base register, and the
10732 target register and the base register are the same,
10733 then we are using AT as a temporary register. Since
10734 we want to load the constant into AT, we add our
10735 current AT (from the global offset table) and the
10736 register into the register now, and pretend we were
10737 not using a base register. */
10741 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10746 add_got_offset_hilo (tempreg, &offset_expr, AT);
10750 else if (!mips_big_got && HAVE_NEWABI)
10752 int add_breg_early = 0;
10754 /* If this is a reference to an external, and there is no
10755 constant, or local symbol (*), with or without a
10757 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10758 or for lca or if tempreg is PIC_CALL_REG
10759 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10761 If we have a small constant, and this is a reference to
10762 an external symbol, we want
10763 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10764 addiu $tempreg,$tempreg,<constant>
10766 If we have a large constant, and this is a reference to
10767 an external symbol, we want
10768 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10769 lui $at,<hiconstant>
10770 addiu $at,$at,<loconstant>
10771 addu $tempreg,$tempreg,$at
10773 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
10774 local symbols, even though it introduces an additional
10777 if (offset_expr.X_add_number)
10779 expr1.X_add_number = offset_expr.X_add_number;
10780 offset_expr.X_add_number = 0;
10782 relax_start (offset_expr.X_add_symbol);
10783 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10784 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10786 if (expr1.X_add_number >= -0x8000
10787 && expr1.X_add_number < 0x8000)
10789 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
10790 tempreg, tempreg, BFD_RELOC_LO16);
10792 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
10796 /* If we are going to add in a base register, and the
10797 target register and the base register are the same,
10798 then we are using AT as a temporary register. Since
10799 we want to load the constant into AT, we add our
10800 current AT (from the global offset table) and the
10801 register into the register now, and pretend we were
10802 not using a base register. */
10807 gas_assert (tempreg == AT);
10808 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10811 add_breg_early = 1;
10814 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
10815 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10821 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10824 offset_expr.X_add_number = expr1.X_add_number;
10826 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10827 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10828 if (add_breg_early)
10830 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10831 op[0], tempreg, breg);
10837 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
10839 relax_start (offset_expr.X_add_symbol);
10840 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10841 BFD_RELOC_MIPS_CALL16, mips_gp_register);
10843 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10844 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10849 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10850 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10853 else if (mips_big_got && !HAVE_NEWABI)
10856 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
10857 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
10858 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
10860 /* This is the large GOT case. If this is a reference to an
10861 external symbol, and there is no constant, we want
10862 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10863 addu $tempreg,$tempreg,$gp
10864 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10865 or for lca or if tempreg is PIC_CALL_REG
10866 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10867 addu $tempreg,$tempreg,$gp
10868 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10869 For a local symbol, we want
10870 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10872 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10874 If we have a small constant, and this is a reference to
10875 an external symbol, we want
10876 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10877 addu $tempreg,$tempreg,$gp
10878 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10880 addiu $tempreg,$tempreg,<constant>
10881 For a local symbol, we want
10882 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10884 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
10886 If we have a large constant, and this is a reference to
10887 an external symbol, we want
10888 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10889 addu $tempreg,$tempreg,$gp
10890 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10891 lui $at,<hiconstant>
10892 addiu $at,$at,<loconstant>
10893 addu $tempreg,$tempreg,$at
10894 For a local symbol, we want
10895 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10896 lui $at,<hiconstant>
10897 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
10898 addu $tempreg,$tempreg,$at
10901 expr1.X_add_number = offset_expr.X_add_number;
10902 offset_expr.X_add_number = 0;
10903 relax_start (offset_expr.X_add_symbol);
10904 gpdelay = reg_needs_delay (mips_gp_register);
10905 if (expr1.X_add_number == 0 && breg == 0
10906 && (call || tempreg == PIC_CALL_REG))
10908 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
10909 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
10911 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
10912 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10913 tempreg, tempreg, mips_gp_register);
10914 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10915 tempreg, lw_reloc_type, tempreg);
10916 if (expr1.X_add_number == 0)
10920 /* We're going to put in an addu instruction using
10921 tempreg, so we may as well insert the nop right
10926 else if (expr1.X_add_number >= -0x8000
10927 && expr1.X_add_number < 0x8000)
10930 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
10931 tempreg, tempreg, BFD_RELOC_LO16);
10937 /* If we are going to add in a base register, and the
10938 target register and the base register are the same,
10939 then we are using AT as a temporary register. Since
10940 we want to load the constant into AT, we add our
10941 current AT (from the global offset table) and the
10942 register into the register now, and pretend we were
10943 not using a base register. */
10948 gas_assert (tempreg == AT);
10950 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10955 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
10956 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
10960 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number);
10965 /* This is needed because this instruction uses $gp, but
10966 the first instruction on the main stream does not. */
10967 macro_build (NULL, "nop", "");
10970 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10971 local_reloc_type, mips_gp_register);
10972 if (expr1.X_add_number >= -0x8000
10973 && expr1.X_add_number < 0x8000)
10976 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10977 tempreg, tempreg, BFD_RELOC_LO16);
10978 /* FIXME: If add_number is 0, and there was no base
10979 register, the external symbol case ended with a load,
10980 so if the symbol turns out to not be external, and
10981 the next instruction uses tempreg, an unnecessary nop
10982 will be inserted. */
10988 /* We must add in the base register now, as in the
10989 external symbol case. */
10990 gas_assert (tempreg == AT);
10992 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10995 /* We set breg to 0 because we have arranged to add
10996 it in in both cases. */
11000 macro_build_lui (&expr1, AT);
11001 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11002 AT, AT, BFD_RELOC_LO16);
11003 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11004 tempreg, tempreg, AT);
11009 else if (mips_big_got && HAVE_NEWABI)
11011 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
11012 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
11013 int add_breg_early = 0;
11015 /* This is the large GOT case. If this is a reference to an
11016 external symbol, and there is no constant, we want
11017 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11018 add $tempreg,$tempreg,$gp
11019 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11020 or for lca or if tempreg is PIC_CALL_REG
11021 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11022 add $tempreg,$tempreg,$gp
11023 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11025 If we have a small constant, and this is a reference to
11026 an external symbol, we want
11027 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11028 add $tempreg,$tempreg,$gp
11029 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11030 addi $tempreg,$tempreg,<constant>
11032 If we have a large constant, and this is a reference to
11033 an external symbol, we want
11034 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11035 addu $tempreg,$tempreg,$gp
11036 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11037 lui $at,<hiconstant>
11038 addi $at,$at,<loconstant>
11039 add $tempreg,$tempreg,$at
11041 If we have NewABI, and we know it's a local symbol, we want
11042 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11043 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
11044 otherwise we have to resort to GOT_HI16/GOT_LO16. */
11046 relax_start (offset_expr.X_add_symbol);
11048 expr1.X_add_number = offset_expr.X_add_number;
11049 offset_expr.X_add_number = 0;
11051 if (expr1.X_add_number == 0 && breg == 0
11052 && (call || tempreg == PIC_CALL_REG))
11054 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
11055 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
11057 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
11058 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11059 tempreg, tempreg, mips_gp_register);
11060 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11061 tempreg, lw_reloc_type, tempreg);
11063 if (expr1.X_add_number == 0)
11065 else if (expr1.X_add_number >= -0x8000
11066 && expr1.X_add_number < 0x8000)
11068 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
11069 tempreg, tempreg, BFD_RELOC_LO16);
11071 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
11075 /* If we are going to add in a base register, and the
11076 target register and the base register are the same,
11077 then we are using AT as a temporary register. Since
11078 we want to load the constant into AT, we add our
11079 current AT (from the global offset table) and the
11080 register into the register now, and pretend we were
11081 not using a base register. */
11086 gas_assert (tempreg == AT);
11087 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11090 add_breg_early = 1;
11093 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
11094 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
11099 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11102 offset_expr.X_add_number = expr1.X_add_number;
11103 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11104 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
11105 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
11106 tempreg, BFD_RELOC_MIPS_GOT_OFST);
11107 if (add_breg_early)
11109 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11110 op[0], tempreg, breg);
11120 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", op[0], tempreg, breg);
11124 gas_assert (!mips_opts.micromips);
11125 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x01);
11129 gas_assert (!mips_opts.micromips);
11130 macro_build (NULL, "c2", "C", 0x02);
11134 gas_assert (!mips_opts.micromips);
11135 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x02);
11139 gas_assert (!mips_opts.micromips);
11140 macro_build (NULL, "c2", "C", 3);
11144 gas_assert (!mips_opts.micromips);
11145 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x03);
11149 /* The j instruction may not be used in PIC code, since it
11150 requires an absolute address. We convert it to a b
11152 if (mips_pic == NO_PIC)
11153 macro_build (&offset_expr, "j", "a");
11155 macro_build (&offset_expr, "b", "p");
11158 /* The jal instructions must be handled as macros because when
11159 generating PIC code they expand to multi-instruction
11160 sequences. Normally they are simple instructions. */
11164 /* Fall through. */
11166 gas_assert (mips_opts.micromips);
11167 if (mips_opts.insn32)
11169 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str);
11177 /* Fall through. */
11180 if (mips_pic == NO_PIC)
11182 s = jals ? "jalrs" : "jalr";
11183 if (mips_opts.micromips
11184 && !mips_opts.insn32
11186 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
11187 macro_build (NULL, s, "mj", op[1]);
11189 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
11193 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
11194 && mips_cprestore_offset >= 0);
11196 if (op[1] != PIC_CALL_REG)
11197 as_warn (_("MIPS PIC call to register other than $25"));
11199 s = ((mips_opts.micromips
11200 && !mips_opts.insn32
11201 && (!mips_opts.noreorder || cprestore))
11202 ? "jalrs" : "jalr");
11203 if (mips_opts.micromips
11204 && !mips_opts.insn32
11206 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
11207 macro_build (NULL, s, "mj", op[1]);
11209 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
11210 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
11212 if (mips_cprestore_offset < 0)
11213 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11216 if (!mips_frame_reg_valid)
11218 as_warn (_("no .frame pseudo-op used in PIC code"));
11219 /* Quiet this warning. */
11220 mips_frame_reg_valid = 1;
11222 if (!mips_cprestore_valid)
11224 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11225 /* Quiet this warning. */
11226 mips_cprestore_valid = 1;
11228 if (mips_opts.noreorder)
11229 macro_build (NULL, "nop", "");
11230 expr1.X_add_number = mips_cprestore_offset;
11231 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
11234 HAVE_64BIT_ADDRESSES);
11242 gas_assert (mips_opts.micromips);
11243 if (mips_opts.insn32)
11245 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str);
11249 /* Fall through. */
11251 if (mips_pic == NO_PIC)
11252 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
11253 else if (mips_pic == SVR4_PIC)
11255 /* If this is a reference to an external symbol, and we are
11256 using a small GOT, we want
11257 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11261 lw $gp,cprestore($sp)
11262 The cprestore value is set using the .cprestore
11263 pseudo-op. If we are using a big GOT, we want
11264 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11266 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11270 lw $gp,cprestore($sp)
11271 If the symbol is not external, we want
11272 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11274 addiu $25,$25,<sym> (BFD_RELOC_LO16)
11277 lw $gp,cprestore($sp)
11279 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11280 sequences above, minus nops, unless the symbol is local,
11281 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11287 relax_start (offset_expr.X_add_symbol);
11288 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11289 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
11292 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11293 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
11299 relax_start (offset_expr.X_add_symbol);
11300 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
11301 BFD_RELOC_MIPS_CALL_HI16);
11302 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
11303 PIC_CALL_REG, mips_gp_register);
11304 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11305 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
11308 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11309 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
11311 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11312 PIC_CALL_REG, PIC_CALL_REG,
11313 BFD_RELOC_MIPS_GOT_OFST);
11317 macro_build_jalr (&offset_expr, 0);
11321 relax_start (offset_expr.X_add_symbol);
11324 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11325 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
11334 gpdelay = reg_needs_delay (mips_gp_register);
11335 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
11336 BFD_RELOC_MIPS_CALL_HI16);
11337 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
11338 PIC_CALL_REG, mips_gp_register);
11339 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11340 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
11345 macro_build (NULL, "nop", "");
11347 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11348 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
11351 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11352 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
11354 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
11356 if (mips_cprestore_offset < 0)
11357 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11360 if (!mips_frame_reg_valid)
11362 as_warn (_("no .frame pseudo-op used in PIC code"));
11363 /* Quiet this warning. */
11364 mips_frame_reg_valid = 1;
11366 if (!mips_cprestore_valid)
11368 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11369 /* Quiet this warning. */
11370 mips_cprestore_valid = 1;
11372 if (mips_opts.noreorder)
11373 macro_build (NULL, "nop", "");
11374 expr1.X_add_number = mips_cprestore_offset;
11375 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
11378 HAVE_64BIT_ADDRESSES);
11382 else if (mips_pic == VXWORKS_PIC)
11383 as_bad (_("non-PIC jump used in PIC library"));
11490 gas_assert (!mips_opts.micromips);
11493 /* Itbl support may require additional care here. */
11499 /* Itbl support may require additional care here. */
11505 offbits = (mips_opts.micromips ? 12
11506 : ISA_IS_R6 (mips_opts.isa) ? 11
11508 /* Itbl support may require additional care here. */
11512 gas_assert (!mips_opts.micromips);
11515 /* Itbl support may require additional care here. */
11521 offbits = (mips_opts.micromips ? 12 : 16);
11526 offbits = (mips_opts.micromips ? 12 : 16);
11531 /* Itbl support may require additional care here. */
11537 offbits = (mips_opts.micromips ? 12
11538 : ISA_IS_R6 (mips_opts.isa) ? 11
11540 /* Itbl support may require additional care here. */
11546 /* Itbl support may require additional care here. */
11552 /* Itbl support may require additional care here. */
11558 offbits = (mips_opts.micromips ? 12 : 16);
11563 offbits = (mips_opts.micromips ? 12 : 16);
11568 offbits = (mips_opts.micromips ? 12
11569 : ISA_IS_R6 (mips_opts.isa) ? 9
11575 offbits = (mips_opts.micromips ? 12
11576 : ISA_IS_R6 (mips_opts.isa) ? 9
11582 offbits = (mips_opts.micromips ? 12 : 16);
11585 gas_assert (mips_opts.micromips);
11592 gas_assert (mips_opts.micromips);
11599 gas_assert (mips_opts.micromips);
11605 gas_assert (mips_opts.micromips);
11612 /* We don't want to use $0 as tempreg. */
11613 if (op[2] == op[0] + lp || op[0] + lp == ZERO)
11616 tempreg = op[0] + lp;
11632 gas_assert (!mips_opts.micromips);
11635 /* Itbl support may require additional care here. */
11641 /* Itbl support may require additional care here. */
11647 offbits = (mips_opts.micromips ? 12
11648 : ISA_IS_R6 (mips_opts.isa) ? 11
11650 /* Itbl support may require additional care here. */
11654 gas_assert (!mips_opts.micromips);
11657 /* Itbl support may require additional care here. */
11663 offbits = (mips_opts.micromips ? 12 : 16);
11668 offbits = (mips_opts.micromips ? 12 : 16);
11673 offbits = (mips_opts.micromips ? 12
11674 : ISA_IS_R6 (mips_opts.isa) ? 9
11680 offbits = (mips_opts.micromips ? 12
11681 : ISA_IS_R6 (mips_opts.isa) ? 9
11686 fmt = (mips_opts.micromips ? "k,~(b)"
11687 : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)"
11689 offbits = (mips_opts.micromips ? 12
11690 : ISA_IS_R6 (mips_opts.isa) ? 9
11700 fmt = (mips_opts.micromips ? "k,~(b)"
11701 : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)"
11703 offbits = (mips_opts.micromips ? 12
11704 : ISA_IS_R6 (mips_opts.isa) ? 9
11716 /* Itbl support may require additional care here. */
11721 offbits = (mips_opts.micromips ? 12
11722 : ISA_IS_R6 (mips_opts.isa) ? 11
11724 /* Itbl support may require additional care here. */
11730 /* Itbl support may require additional care here. */
11734 gas_assert (!mips_opts.micromips);
11737 /* Itbl support may require additional care here. */
11743 offbits = (mips_opts.micromips ? 12 : 16);
11748 offbits = (mips_opts.micromips ? 12 : 16);
11751 gas_assert (mips_opts.micromips);
11757 gas_assert (mips_opts.micromips);
11763 gas_assert (mips_opts.micromips);
11769 gas_assert (mips_opts.micromips);
11778 if (small_offset_p (0, align, 16))
11780 /* The first case exists for M_LD_AB and M_SD_AB, which are
11781 macros for o32 but which should act like normal instructions
11784 macro_build (&offset_expr, s, fmt, op[0], -1, offset_reloc[0],
11785 offset_reloc[1], offset_reloc[2], breg);
11786 else if (small_offset_p (0, align, offbits))
11789 macro_build (NULL, s, fmt, op[0], breg);
11791 macro_build (NULL, s, fmt, op[0],
11792 (int) offset_expr.X_add_number, breg);
11798 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11799 tempreg, breg, -1, offset_reloc[0],
11800 offset_reloc[1], offset_reloc[2]);
11802 macro_build (NULL, s, fmt, op[0], tempreg);
11804 macro_build (NULL, s, fmt, op[0], 0, tempreg);
11812 if (offset_expr.X_op != O_constant
11813 && offset_expr.X_op != O_symbol)
11815 as_bad (_("expression too complex"));
11816 offset_expr.X_op = O_constant;
11819 if (HAVE_32BIT_ADDRESSES
11820 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
11824 sprintf_vma (value, offset_expr.X_add_number);
11825 as_bad (_("number (0x%s) larger than 32 bits"), value);
11828 /* A constant expression in PIC code can be handled just as it
11829 is in non PIC code. */
11830 if (offset_expr.X_op == O_constant)
11832 expr1.X_add_number = offset_high_part (offset_expr.X_add_number,
11833 offbits == 0 ? 16 : offbits);
11834 offset_expr.X_add_number -= expr1.X_add_number;
11836 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
11838 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11839 tempreg, tempreg, breg);
11842 if (offset_expr.X_add_number != 0)
11843 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
11844 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
11845 macro_build (NULL, s, fmt, op[0], tempreg);
11847 else if (offbits == 16)
11848 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
11850 macro_build (NULL, s, fmt, op[0],
11851 (int) offset_expr.X_add_number, tempreg);
11853 else if (offbits != 16)
11855 /* The offset field is too narrow to be used for a low-part
11856 relocation, so load the whole address into the auxiliary
11858 load_address (tempreg, &offset_expr, &used_at);
11860 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11861 tempreg, tempreg, breg);
11863 macro_build (NULL, s, fmt, op[0], tempreg);
11865 macro_build (NULL, s, fmt, op[0], 0, tempreg);
11867 else if (mips_pic == NO_PIC)
11869 /* If this is a reference to a GP relative symbol, and there
11870 is no base register, we want
11871 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11872 Otherwise, if there is no base register, we want
11873 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11874 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11875 If we have a constant, we need two instructions anyhow,
11876 so we always use the latter form.
11878 If we have a base register, and this is a reference to a
11879 GP relative symbol, we want
11880 addu $tempreg,$breg,$gp
11881 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
11883 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11884 addu $tempreg,$tempreg,$breg
11885 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11886 With a constant we always use the latter case.
11888 With 64bit address space and no base register and $at usable,
11890 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11891 lui $at,<sym> (BFD_RELOC_HI16_S)
11892 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11895 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11896 If we have a base register, we want
11897 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11898 lui $at,<sym> (BFD_RELOC_HI16_S)
11899 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11903 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11905 Without $at we can't generate the optimal path for superscalar
11906 processors here since this would require two temporary registers.
11907 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11908 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11910 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11912 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11913 If we have a base register, we want
11914 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11915 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11917 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11919 daddu $tempreg,$tempreg,$breg
11920 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11922 For GP relative symbols in 64bit address space we can use
11923 the same sequence as in 32bit address space. */
11924 if (HAVE_64BIT_SYMBOLS)
11926 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
11927 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11929 relax_start (offset_expr.X_add_symbol);
11932 macro_build (&offset_expr, s, fmt, op[0],
11933 BFD_RELOC_GPREL16, mips_gp_register);
11937 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11938 tempreg, breg, mips_gp_register);
11939 macro_build (&offset_expr, s, fmt, op[0],
11940 BFD_RELOC_GPREL16, tempreg);
11945 if (used_at == 0 && mips_opts.at)
11947 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11948 BFD_RELOC_MIPS_HIGHEST);
11949 macro_build (&offset_expr, "lui", LUI_FMT, AT,
11951 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11952 tempreg, BFD_RELOC_MIPS_HIGHER);
11954 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
11955 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
11956 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
11957 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16,
11963 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11964 BFD_RELOC_MIPS_HIGHEST);
11965 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11966 tempreg, BFD_RELOC_MIPS_HIGHER);
11967 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
11968 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11969 tempreg, BFD_RELOC_HI16_S);
11970 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
11972 macro_build (NULL, "daddu", "d,v,t",
11973 tempreg, tempreg, breg);
11974 macro_build (&offset_expr, s, fmt, op[0],
11975 BFD_RELOC_LO16, tempreg);
11978 if (mips_relax.sequence)
11985 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
11986 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11988 relax_start (offset_expr.X_add_symbol);
11989 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_GPREL16,
11993 macro_build_lui (&offset_expr, tempreg);
11994 macro_build (&offset_expr, s, fmt, op[0],
11995 BFD_RELOC_LO16, tempreg);
11996 if (mips_relax.sequence)
12001 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
12002 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
12004 relax_start (offset_expr.X_add_symbol);
12005 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12006 tempreg, breg, mips_gp_register);
12007 macro_build (&offset_expr, s, fmt, op[0],
12008 BFD_RELOC_GPREL16, tempreg);
12011 macro_build_lui (&offset_expr, tempreg);
12012 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12013 tempreg, tempreg, breg);
12014 macro_build (&offset_expr, s, fmt, op[0],
12015 BFD_RELOC_LO16, tempreg);
12016 if (mips_relax.sequence)
12020 else if (!mips_big_got)
12022 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
12024 /* If this is a reference to an external symbol, we want
12025 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12027 <op> op[0],0($tempreg)
12029 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12031 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12032 <op> op[0],0($tempreg)
12034 For NewABI, we want
12035 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12036 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
12038 If there is a base register, we add it to $tempreg before
12039 the <op>. If there is a constant, we stick it in the
12040 <op> instruction. We don't handle constants larger than
12041 16 bits, because we have no way to load the upper 16 bits
12042 (actually, we could handle them for the subset of cases
12043 in which we are not using $at). */
12044 gas_assert (offset_expr.X_op == O_symbol);
12047 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12048 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
12050 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12051 tempreg, tempreg, breg);
12052 macro_build (&offset_expr, s, fmt, op[0],
12053 BFD_RELOC_MIPS_GOT_OFST, tempreg);
12056 expr1.X_add_number = offset_expr.X_add_number;
12057 offset_expr.X_add_number = 0;
12058 if (expr1.X_add_number < -0x8000
12059 || expr1.X_add_number >= 0x8000)
12060 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12061 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12062 lw_reloc_type, mips_gp_register);
12064 relax_start (offset_expr.X_add_symbol);
12066 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
12067 tempreg, BFD_RELOC_LO16);
12070 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12071 tempreg, tempreg, breg);
12072 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
12074 else if (mips_big_got && !HAVE_NEWABI)
12078 /* If this is a reference to an external symbol, we want
12079 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12080 addu $tempreg,$tempreg,$gp
12081 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12082 <op> op[0],0($tempreg)
12084 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12086 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12087 <op> op[0],0($tempreg)
12088 If there is a base register, we add it to $tempreg before
12089 the <op>. If there is a constant, we stick it in the
12090 <op> instruction. We don't handle constants larger than
12091 16 bits, because we have no way to load the upper 16 bits
12092 (actually, we could handle them for the subset of cases
12093 in which we are not using $at). */
12094 gas_assert (offset_expr.X_op == O_symbol);
12095 expr1.X_add_number = offset_expr.X_add_number;
12096 offset_expr.X_add_number = 0;
12097 if (expr1.X_add_number < -0x8000
12098 || expr1.X_add_number >= 0x8000)
12099 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12100 gpdelay = reg_needs_delay (mips_gp_register);
12101 relax_start (offset_expr.X_add_symbol);
12102 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
12103 BFD_RELOC_MIPS_GOT_HI16);
12104 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
12106 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12107 BFD_RELOC_MIPS_GOT_LO16, tempreg);
12110 macro_build (NULL, "nop", "");
12111 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12112 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12114 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
12115 tempreg, BFD_RELOC_LO16);
12119 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12120 tempreg, tempreg, breg);
12121 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
12123 else if (mips_big_got && HAVE_NEWABI)
12125 /* If this is a reference to an external symbol, we want
12126 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12127 add $tempreg,$tempreg,$gp
12128 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12129 <op> op[0],<ofst>($tempreg)
12130 Otherwise, for local symbols, we want:
12131 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12132 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
12133 gas_assert (offset_expr.X_op == O_symbol);
12134 expr1.X_add_number = offset_expr.X_add_number;
12135 offset_expr.X_add_number = 0;
12136 if (expr1.X_add_number < -0x8000
12137 || expr1.X_add_number >= 0x8000)
12138 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12139 relax_start (offset_expr.X_add_symbol);
12140 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
12141 BFD_RELOC_MIPS_GOT_HI16);
12142 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
12144 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12145 BFD_RELOC_MIPS_GOT_LO16, tempreg);
12147 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12148 tempreg, tempreg, breg);
12149 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
12152 offset_expr.X_add_number = expr1.X_add_number;
12153 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12154 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
12156 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12157 tempreg, tempreg, breg);
12158 macro_build (&offset_expr, s, fmt, op[0],
12159 BFD_RELOC_MIPS_GOT_OFST, tempreg);
12168 gas_assert (mips_opts.micromips);
12169 gas_assert (mips_opts.insn32);
12170 start_noreorder ();
12171 macro_build (NULL, "jr", "s", RA);
12172 expr1.X_add_number = op[0] << 2;
12173 macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16);
12178 gas_assert (mips_opts.micromips);
12179 gas_assert (mips_opts.insn32);
12180 macro_build (NULL, "jr", "s", op[0]);
12181 if (mips_opts.noreorder)
12182 macro_build (NULL, "nop", "");
12187 load_register (op[0], &imm_expr, 0);
12191 load_register (op[0], &imm_expr, 1);
12195 if (imm_expr.X_op == O_constant)
12198 load_register (AT, &imm_expr, 0);
12199 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
12204 gas_assert (imm_expr.X_op == O_absent
12205 && offset_expr.X_op == O_symbol
12206 && strcmp (segment_name (S_GET_SEGMENT
12207 (offset_expr.X_add_symbol)),
12209 && offset_expr.X_add_number == 0);
12210 macro_build (&offset_expr, "lwc1", "T,o(b)", op[0],
12211 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
12216 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12217 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12218 order 32 bits of the value and the low order 32 bits are either
12219 zero or in OFFSET_EXPR. */
12220 if (imm_expr.X_op == O_constant)
12222 if (GPR_SIZE == 64)
12223 load_register (op[0], &imm_expr, 1);
12228 if (target_big_endian)
12240 load_register (hreg, &imm_expr, 0);
12243 if (offset_expr.X_op == O_absent)
12244 move_register (lreg, 0);
12247 gas_assert (offset_expr.X_op == O_constant);
12248 load_register (lreg, &offset_expr, 0);
12254 gas_assert (imm_expr.X_op == O_absent);
12256 /* We know that sym is in the .rdata section. First we get the
12257 upper 16 bits of the address. */
12258 if (mips_pic == NO_PIC)
12260 macro_build_lui (&offset_expr, AT);
12265 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12266 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12270 /* Now we load the register(s). */
12271 if (GPR_SIZE == 64)
12274 macro_build (&offset_expr, "ld", "t,o(b)", op[0],
12275 BFD_RELOC_LO16, AT);
12280 macro_build (&offset_expr, "lw", "t,o(b)", op[0],
12281 BFD_RELOC_LO16, AT);
12284 /* FIXME: How in the world do we deal with the possible
12286 offset_expr.X_add_number += 4;
12287 macro_build (&offset_expr, "lw", "t,o(b)",
12288 op[0] + 1, BFD_RELOC_LO16, AT);
12294 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12295 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12296 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12297 the value and the low order 32 bits are either zero or in
12299 if (imm_expr.X_op == O_constant)
12302 load_register (AT, &imm_expr, FPR_SIZE == 64);
12303 if (FPR_SIZE == 64 && GPR_SIZE == 64)
12304 macro_build (NULL, "dmtc1", "t,S", AT, op[0]);
12307 if (ISA_HAS_MXHC1 (mips_opts.isa))
12308 macro_build (NULL, "mthc1", "t,G", AT, op[0]);
12309 else if (FPR_SIZE != 32)
12310 as_bad (_("Unable to generate `%s' compliant code "
12312 (FPR_SIZE == 64) ? "fp64" : "fpxx");
12314 macro_build (NULL, "mtc1", "t,G", AT, op[0] + 1);
12315 if (offset_expr.X_op == O_absent)
12316 macro_build (NULL, "mtc1", "t,G", 0, op[0]);
12319 gas_assert (offset_expr.X_op == O_constant);
12320 load_register (AT, &offset_expr, 0);
12321 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
12327 gas_assert (imm_expr.X_op == O_absent
12328 && offset_expr.X_op == O_symbol
12329 && offset_expr.X_add_number == 0);
12330 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
12331 if (strcmp (s, ".lit8") == 0)
12333 op[2] = mips_gp_register;
12334 offset_reloc[0] = BFD_RELOC_MIPS_LITERAL;
12335 offset_reloc[1] = BFD_RELOC_UNUSED;
12336 offset_reloc[2] = BFD_RELOC_UNUSED;
12340 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
12342 if (mips_pic != NO_PIC)
12343 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12344 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12347 /* FIXME: This won't work for a 64 bit address. */
12348 macro_build_lui (&offset_expr, AT);
12352 offset_reloc[0] = BFD_RELOC_LO16;
12353 offset_reloc[1] = BFD_RELOC_UNUSED;
12354 offset_reloc[2] = BFD_RELOC_UNUSED;
12361 * The MIPS assembler seems to check for X_add_number not
12362 * being double aligned and generating:
12363 * lui at,%hi(foo+1)
12365 * addiu at,at,%lo(foo+1)
12368 * But, the resulting address is the same after relocation so why
12369 * generate the extra instruction?
12371 /* Itbl support may require additional care here. */
12374 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
12383 gas_assert (!mips_opts.micromips);
12384 /* Itbl support may require additional care here. */
12387 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
12407 if (GPR_SIZE == 64)
12417 if (GPR_SIZE == 64)
12425 /* Even on a big endian machine $fn comes before $fn+1. We have
12426 to adjust when loading from memory. We set coproc if we must
12427 load $fn+1 first. */
12428 /* Itbl support may require additional care here. */
12429 if (!target_big_endian)
12433 if (small_offset_p (0, align, 16))
12436 if (!small_offset_p (4, align, 16))
12438 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg,
12439 -1, offset_reloc[0], offset_reloc[1],
12441 expr1.X_add_number = 0;
12445 offset_reloc[0] = BFD_RELOC_LO16;
12446 offset_reloc[1] = BFD_RELOC_UNUSED;
12447 offset_reloc[2] = BFD_RELOC_UNUSED;
12449 if (strcmp (s, "lw") == 0 && op[0] == breg)
12451 ep->X_add_number += 4;
12452 macro_build (ep, s, fmt, op[0] + 1, -1, offset_reloc[0],
12453 offset_reloc[1], offset_reloc[2], breg);
12454 ep->X_add_number -= 4;
12455 macro_build (ep, s, fmt, op[0], -1, offset_reloc[0],
12456 offset_reloc[1], offset_reloc[2], breg);
12460 macro_build (ep, s, fmt, coproc ? op[0] + 1 : op[0], -1,
12461 offset_reloc[0], offset_reloc[1], offset_reloc[2],
12463 ep->X_add_number += 4;
12464 macro_build (ep, s, fmt, coproc ? op[0] : op[0] + 1, -1,
12465 offset_reloc[0], offset_reloc[1], offset_reloc[2],
12471 if (offset_expr.X_op != O_symbol
12472 && offset_expr.X_op != O_constant)
12474 as_bad (_("expression too complex"));
12475 offset_expr.X_op = O_constant;
12478 if (HAVE_32BIT_ADDRESSES
12479 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
12483 sprintf_vma (value, offset_expr.X_add_number);
12484 as_bad (_("number (0x%s) larger than 32 bits"), value);
12487 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
12489 /* If this is a reference to a GP relative symbol, we want
12490 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12491 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
12492 If we have a base register, we use this
12494 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
12495 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
12496 If this is not a GP relative symbol, we want
12497 lui $at,<sym> (BFD_RELOC_HI16_S)
12498 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12499 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12500 If there is a base register, we add it to $at after the
12501 lui instruction. If there is a constant, we always use
12503 if (offset_expr.X_op == O_symbol
12504 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
12505 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
12507 relax_start (offset_expr.X_add_symbol);
12510 tempreg = mips_gp_register;
12514 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12515 AT, breg, mips_gp_register);
12520 /* Itbl support may require additional care here. */
12521 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12522 BFD_RELOC_GPREL16, tempreg);
12523 offset_expr.X_add_number += 4;
12525 /* Set mips_optimize to 2 to avoid inserting an
12527 hold_mips_optimize = mips_optimize;
12529 /* Itbl support may require additional care here. */
12530 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12531 BFD_RELOC_GPREL16, tempreg);
12532 mips_optimize = hold_mips_optimize;
12536 offset_expr.X_add_number -= 4;
12539 if (offset_high_part (offset_expr.X_add_number, 16)
12540 != offset_high_part (offset_expr.X_add_number + 4, 16))
12542 load_address (AT, &offset_expr, &used_at);
12543 offset_expr.X_op = O_constant;
12544 offset_expr.X_add_number = 0;
12547 macro_build_lui (&offset_expr, AT);
12549 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12550 /* Itbl support may require additional care here. */
12551 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12552 BFD_RELOC_LO16, AT);
12553 /* FIXME: How do we handle overflow here? */
12554 offset_expr.X_add_number += 4;
12555 /* Itbl support may require additional care here. */
12556 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12557 BFD_RELOC_LO16, AT);
12558 if (mips_relax.sequence)
12561 else if (!mips_big_got)
12563 /* If this is a reference to an external symbol, we want
12564 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12567 <op> op[0]+1,4($at)
12569 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12571 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12572 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12573 If there is a base register we add it to $at before the
12574 lwc1 instructions. If there is a constant we include it
12575 in the lwc1 instructions. */
12577 expr1.X_add_number = offset_expr.X_add_number;
12578 if (expr1.X_add_number < -0x8000
12579 || expr1.X_add_number >= 0x8000 - 4)
12580 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12581 load_got_offset (AT, &offset_expr);
12584 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12586 /* Set mips_optimize to 2 to avoid inserting an undesired
12588 hold_mips_optimize = mips_optimize;
12591 /* Itbl support may require additional care here. */
12592 relax_start (offset_expr.X_add_symbol);
12593 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
12594 BFD_RELOC_LO16, AT);
12595 expr1.X_add_number += 4;
12596 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
12597 BFD_RELOC_LO16, AT);
12599 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12600 BFD_RELOC_LO16, AT);
12601 offset_expr.X_add_number += 4;
12602 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12603 BFD_RELOC_LO16, AT);
12606 mips_optimize = hold_mips_optimize;
12608 else if (mips_big_got)
12612 /* If this is a reference to an external symbol, we want
12613 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12615 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
12618 <op> op[0]+1,4($at)
12620 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12622 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12623 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12624 If there is a base register we add it to $at before the
12625 lwc1 instructions. If there is a constant we include it
12626 in the lwc1 instructions. */
12628 expr1.X_add_number = offset_expr.X_add_number;
12629 offset_expr.X_add_number = 0;
12630 if (expr1.X_add_number < -0x8000
12631 || expr1.X_add_number >= 0x8000 - 4)
12632 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12633 gpdelay = reg_needs_delay (mips_gp_register);
12634 relax_start (offset_expr.X_add_symbol);
12635 macro_build (&offset_expr, "lui", LUI_FMT,
12636 AT, BFD_RELOC_MIPS_GOT_HI16);
12637 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12638 AT, AT, mips_gp_register);
12639 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
12640 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
12643 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12644 /* Itbl support may require additional care here. */
12645 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
12646 BFD_RELOC_LO16, AT);
12647 expr1.X_add_number += 4;
12649 /* Set mips_optimize to 2 to avoid inserting an undesired
12651 hold_mips_optimize = mips_optimize;
12653 /* Itbl support may require additional care here. */
12654 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
12655 BFD_RELOC_LO16, AT);
12656 mips_optimize = hold_mips_optimize;
12657 expr1.X_add_number -= 4;
12660 offset_expr.X_add_number = expr1.X_add_number;
12662 macro_build (NULL, "nop", "");
12663 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12664 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12667 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12668 /* Itbl support may require additional care here. */
12669 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12670 BFD_RELOC_LO16, AT);
12671 offset_expr.X_add_number += 4;
12673 /* Set mips_optimize to 2 to avoid inserting an undesired
12675 hold_mips_optimize = mips_optimize;
12677 /* Itbl support may require additional care here. */
12678 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12679 BFD_RELOC_LO16, AT);
12680 mips_optimize = hold_mips_optimize;
12694 gas_assert (!mips_opts.micromips);
12699 /* New code added to support COPZ instructions.
12700 This code builds table entries out of the macros in mip_opcodes.
12701 R4000 uses interlocks to handle coproc delays.
12702 Other chips (like the R3000) require nops to be inserted for delays.
12704 FIXME: Currently, we require that the user handle delays.
12705 In order to fill delay slots for non-interlocked chips,
12706 we must have a way to specify delays based on the coprocessor.
12707 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
12708 What are the side-effects of the cop instruction?
12709 What cache support might we have and what are its effects?
12710 Both coprocessor & memory require delays. how long???
12711 What registers are read/set/modified?
12713 If an itbl is provided to interpret cop instructions,
12714 this knowledge can be encoded in the itbl spec. */
12728 gas_assert (!mips_opts.micromips);
12729 /* For now we just do C (same as Cz). The parameter will be
12730 stored in insn_opcode by mips_ip. */
12731 macro_build (NULL, s, "C", (int) ip->insn_opcode);
12735 move_register (op[0], op[1]);
12739 gas_assert (mips_opts.micromips);
12740 gas_assert (mips_opts.insn32);
12741 move_register (micromips_to_32_reg_h_map1[op[0]],
12742 micromips_to_32_reg_m_map[op[1]]);
12743 move_register (micromips_to_32_reg_h_map2[op[0]],
12744 micromips_to_32_reg_n_map[op[2]]);
12749 /* Fall through. */
12751 if (mips_opts.arch == CPU_R5900)
12752 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", op[0], op[1],
12756 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", op[1], op[2]);
12757 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12763 /* Fall through. */
12765 /* The MIPS assembler some times generates shifts and adds. I'm
12766 not trying to be that fancy. GCC should do this for us
12769 load_register (AT, &imm_expr, dbl);
12770 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", op[1], AT);
12771 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12776 /* Fall through. */
12783 /* Fall through. */
12786 start_noreorder ();
12789 load_register (AT, &imm_expr, dbl);
12790 macro_build (NULL, dbl ? "dmult" : "mult", "s,t",
12791 op[1], imm ? AT : op[2]);
12792 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12793 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, op[0], op[0], 31);
12794 macro_build (NULL, "mfhi", MFHL_FMT, AT);
12796 macro_build (NULL, "tne", TRAP_FMT, op[0], AT, 6);
12799 if (mips_opts.micromips)
12800 micromips_label_expr (&label_expr);
12802 label_expr.X_add_number = 8;
12803 macro_build (&label_expr, "beq", "s,t,p", op[0], AT);
12804 macro_build (NULL, "nop", "");
12805 macro_build (NULL, "break", BRK_FMT, 6);
12806 if (mips_opts.micromips)
12807 micromips_add_label ();
12810 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12815 /* Fall through. */
12822 /* Fall through. */
12825 start_noreorder ();
12828 load_register (AT, &imm_expr, dbl);
12829 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
12830 op[1], imm ? AT : op[2]);
12831 macro_build (NULL, "mfhi", MFHL_FMT, AT);
12832 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12834 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
12837 if (mips_opts.micromips)
12838 micromips_label_expr (&label_expr);
12840 label_expr.X_add_number = 8;
12841 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
12842 macro_build (NULL, "nop", "");
12843 macro_build (NULL, "break", BRK_FMT, 6);
12844 if (mips_opts.micromips)
12845 micromips_add_label ();
12851 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12853 if (op[0] == op[1])
12860 macro_build (NULL, "dnegu", "d,w", tempreg, op[2]);
12861 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], tempreg);
12865 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
12866 macro_build (NULL, "dsrlv", "d,t,s", AT, op[1], AT);
12867 macro_build (NULL, "dsllv", "d,t,s", op[0], op[1], op[2]);
12868 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12872 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12874 if (op[0] == op[1])
12881 macro_build (NULL, "negu", "d,w", tempreg, op[2]);
12882 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], tempreg);
12886 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
12887 macro_build (NULL, "srlv", "d,t,s", AT, op[1], AT);
12888 macro_build (NULL, "sllv", "d,t,s", op[0], op[1], op[2]);
12889 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12898 rot = imm_expr.X_add_number & 0x3f;
12899 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12901 rot = (64 - rot) & 0x3f;
12903 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
12905 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
12910 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
12913 l = (rot < 0x20) ? "dsll" : "dsll32";
12914 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
12917 macro_build (NULL, l, SHFT_FMT, AT, op[1], rot);
12918 macro_build (NULL, rr, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12919 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12927 rot = imm_expr.X_add_number & 0x1f;
12928 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12930 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1],
12931 (32 - rot) & 0x1f);
12936 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
12940 macro_build (NULL, "sll", SHFT_FMT, AT, op[1], rot);
12941 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12942 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12947 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12949 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], op[2]);
12953 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
12954 macro_build (NULL, "dsllv", "d,t,s", AT, op[1], AT);
12955 macro_build (NULL, "dsrlv", "d,t,s", op[0], op[1], op[2]);
12956 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12960 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12962 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], op[2]);
12966 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
12967 macro_build (NULL, "sllv", "d,t,s", AT, op[1], AT);
12968 macro_build (NULL, "srlv", "d,t,s", op[0], op[1], op[2]);
12969 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12978 rot = imm_expr.X_add_number & 0x3f;
12979 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12982 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
12984 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
12989 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
12992 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
12993 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
12996 macro_build (NULL, rr, SHFT_FMT, AT, op[1], rot);
12997 macro_build (NULL, l, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12998 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13006 rot = imm_expr.X_add_number & 0x1f;
13007 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
13009 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], rot);
13014 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
13018 macro_build (NULL, "srl", SHFT_FMT, AT, op[1], rot);
13019 macro_build (NULL, "sll", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
13020 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13026 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[2], BFD_RELOC_LO16);
13027 else if (op[2] == 0)
13028 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13031 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
13032 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
13037 if (imm_expr.X_add_number == 0)
13039 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13044 as_warn (_("instruction %s: result is always false"),
13045 ip->insn_mo->name);
13046 move_register (op[0], 0);
13049 if (CPU_HAS_SEQ (mips_opts.arch)
13050 && -512 <= imm_expr.X_add_number
13051 && imm_expr.X_add_number < 512)
13053 macro_build (NULL, "seqi", "t,r,+Q", op[0], op[1],
13054 (int) imm_expr.X_add_number);
13057 if (imm_expr.X_add_number >= 0
13058 && imm_expr.X_add_number < 0x10000)
13059 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], BFD_RELOC_LO16);
13060 else if (imm_expr.X_add_number > -0x8000
13061 && imm_expr.X_add_number < 0)
13063 imm_expr.X_add_number = -imm_expr.X_add_number;
13064 macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu",
13065 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13067 else if (CPU_HAS_SEQ (mips_opts.arch))
13070 load_register (AT, &imm_expr, GPR_SIZE == 64);
13071 macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT);
13076 load_register (AT, &imm_expr, GPR_SIZE == 64);
13077 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
13080 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
13083 case M_SGE: /* X >= Y <==> not (X < Y) */
13089 macro_build (NULL, s, "d,v,t", op[0], op[1], op[2]);
13090 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
13093 case M_SGE_I: /* X >= I <==> not (X < I) */
13095 if (imm_expr.X_add_number >= -0x8000
13096 && imm_expr.X_add_number < 0x8000)
13097 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
13098 op[0], op[1], BFD_RELOC_LO16);
13101 load_register (AT, &imm_expr, GPR_SIZE == 64);
13102 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
13106 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
13109 case M_SGT: /* X > Y <==> Y < X */
13115 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
13118 case M_SGT_I: /* X > I <==> I < X */
13125 load_register (AT, &imm_expr, GPR_SIZE == 64);
13126 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
13129 case M_SLE: /* X <= Y <==> Y >= X <==> not (Y < X) */
13135 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
13136 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
13139 case M_SLE_I: /* X <= I <==> I >= X <==> not (I < X) */
13146 load_register (AT, &imm_expr, GPR_SIZE == 64);
13147 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
13148 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
13152 if (imm_expr.X_add_number >= -0x8000
13153 && imm_expr.X_add_number < 0x8000)
13155 macro_build (&imm_expr, "slti", "t,r,j", op[0], op[1],
13160 load_register (AT, &imm_expr, GPR_SIZE == 64);
13161 macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT);
13165 if (imm_expr.X_add_number >= -0x8000
13166 && imm_expr.X_add_number < 0x8000)
13168 macro_build (&imm_expr, "sltiu", "t,r,j", op[0], op[1],
13173 load_register (AT, &imm_expr, GPR_SIZE == 64);
13174 macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT);
13179 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[2]);
13180 else if (op[2] == 0)
13181 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
13184 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
13185 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
13190 if (imm_expr.X_add_number == 0)
13192 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
13197 as_warn (_("instruction %s: result is always true"),
13198 ip->insn_mo->name);
13199 macro_build (&expr1, GPR_SIZE == 32 ? "addiu" : "daddiu", "t,r,j",
13200 op[0], 0, BFD_RELOC_LO16);
13203 if (CPU_HAS_SEQ (mips_opts.arch)
13204 && -512 <= imm_expr.X_add_number
13205 && imm_expr.X_add_number < 512)
13207 macro_build (NULL, "snei", "t,r,+Q", op[0], op[1],
13208 (int) imm_expr.X_add_number);
13211 if (imm_expr.X_add_number >= 0
13212 && imm_expr.X_add_number < 0x10000)
13214 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1],
13217 else if (imm_expr.X_add_number > -0x8000
13218 && imm_expr.X_add_number < 0)
13220 imm_expr.X_add_number = -imm_expr.X_add_number;
13221 macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu",
13222 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13224 else if (CPU_HAS_SEQ (mips_opts.arch))
13227 load_register (AT, &imm_expr, GPR_SIZE == 64);
13228 macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT);
13233 load_register (AT, &imm_expr, GPR_SIZE == 64);
13234 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
13237 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
13252 if (!mips_opts.micromips)
13254 if (imm_expr.X_add_number > -0x200
13255 && imm_expr.X_add_number <= 0x200)
13257 macro_build (NULL, s, "t,r,.", op[0], op[1],
13258 (int) -imm_expr.X_add_number);
13267 if (imm_expr.X_add_number > -0x8000
13268 && imm_expr.X_add_number <= 0x8000)
13270 imm_expr.X_add_number = -imm_expr.X_add_number;
13271 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13276 load_register (AT, &imm_expr, dbl);
13277 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
13299 load_register (AT, &imm_expr, GPR_SIZE == 64);
13300 macro_build (NULL, s, "s,t", op[0], AT);
13305 gas_assert (!mips_opts.micromips);
13306 gas_assert (mips_opts.isa == ISA_MIPS1);
13310 * Is the double cfc1 instruction a bug in the mips assembler;
13311 * or is there a reason for it?
13313 start_noreorder ();
13314 macro_build (NULL, "cfc1", "t,G", op[2], RA);
13315 macro_build (NULL, "cfc1", "t,G", op[2], RA);
13316 macro_build (NULL, "nop", "");
13317 expr1.X_add_number = 3;
13318 macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16);
13319 expr1.X_add_number = 2;
13320 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
13321 macro_build (NULL, "ctc1", "t,G", AT, RA);
13322 macro_build (NULL, "nop", "");
13323 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
13325 macro_build (NULL, "ctc1", "t,G", op[2], RA);
13326 macro_build (NULL, "nop", "");
13343 offbits = (mips_opts.micromips ? 12 : 16);
13349 offbits = (mips_opts.micromips ? 12 : 16);
13361 offbits = (mips_opts.micromips ? 12 : 16);
13368 offbits = (mips_opts.micromips ? 12 : 16);
13374 large_offset = !small_offset_p (off, align, offbits);
13376 expr1.X_add_number = 0;
13381 if (small_offset_p (0, align, 16))
13382 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1,
13383 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
13386 load_address (tempreg, ep, &used_at);
13388 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
13389 tempreg, tempreg, breg);
13391 offset_reloc[0] = BFD_RELOC_LO16;
13392 offset_reloc[1] = BFD_RELOC_UNUSED;
13393 offset_reloc[2] = BFD_RELOC_UNUSED;
13398 else if (!ust && op[0] == breg)
13409 if (!target_big_endian)
13410 ep->X_add_number += off;
13412 macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg);
13414 macro_build (ep, s, "t,o(b)", tempreg, -1,
13415 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13417 if (!target_big_endian)
13418 ep->X_add_number -= off;
13420 ep->X_add_number += off;
13422 macro_build (NULL, s2, "t,~(b)",
13423 tempreg, (int) ep->X_add_number, breg);
13425 macro_build (ep, s2, "t,o(b)", tempreg, -1,
13426 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13428 /* If necessary, move the result in tempreg to the final destination. */
13429 if (!ust && op[0] != tempreg)
13431 /* Protect second load's delay slot. */
13433 move_register (op[0], tempreg);
13439 if (target_big_endian == ust)
13440 ep->X_add_number += off;
13441 tempreg = ust || large_offset ? op[0] : AT;
13442 macro_build (ep, s, "t,o(b)", tempreg, -1,
13443 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13445 /* For halfword transfers we need a temporary register to shuffle
13446 bytes. Unfortunately for M_USH_A we have none available before
13447 the next store as AT holds the base address. We deal with this
13448 case by clobbering TREG and then restoring it as with ULH. */
13449 tempreg = ust == large_offset ? op[0] : AT;
13451 macro_build (NULL, "srl", SHFT_FMT, tempreg, op[0], 8);
13453 if (target_big_endian == ust)
13454 ep->X_add_number -= off;
13456 ep->X_add_number += off;
13457 macro_build (ep, s2, "t,o(b)", tempreg, -1,
13458 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13460 /* For M_USH_A re-retrieve the LSB. */
13461 if (ust && large_offset)
13463 if (target_big_endian)
13464 ep->X_add_number += off;
13466 ep->X_add_number -= off;
13467 macro_build (&expr1, "lbu", "t,o(b)", AT, -1,
13468 offset_reloc[0], offset_reloc[1], offset_reloc[2], AT);
13470 /* For ULH and M_USH_A OR the LSB in. */
13471 if (!ust || large_offset)
13473 tempreg = !large_offset ? AT : op[0];
13474 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
13475 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13480 /* FIXME: Check if this is one of the itbl macros, since they
13481 are added dynamically. */
13482 as_bad (_("macro %s not implemented yet"), ip->insn_mo->name);
13485 if (!mips_opts.at && used_at)
13486 as_bad (_("macro used $at after \".set noat\""));
13489 /* Implement macros in mips16 mode. */
13492 mips16_macro (struct mips_cl_insn *ip)
13494 const struct mips_operand_array *operands;
13499 const char *s, *s2, *s3;
13500 unsigned int op[MAX_OPERANDS];
13503 mask = ip->insn_mo->mask;
13505 operands = insn_operands (ip);
13506 for (i = 0; i < MAX_OPERANDS; i++)
13507 if (operands->operand[i])
13508 op[i] = insn_extract_operand (ip, operands->operand[i]);
13512 expr1.X_op = O_constant;
13513 expr1.X_op_symbol = NULL;
13514 expr1.X_add_symbol = NULL;
13515 expr1.X_add_number = 1;
13526 /* Fall through. */
13532 /* Fall through. */
13536 start_noreorder ();
13537 macro_build (NULL, dbl ? "ddiv" : "div", ".,x,y", op[1], op[2]);
13538 expr1.X_add_number = 2;
13539 macro_build (&expr1, "bnez", "x,p", op[2]);
13540 macro_build (NULL, "break", "6", 7);
13542 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
13543 since that causes an overflow. We should do that as well,
13544 but I don't see how to do the comparisons without a temporary
13547 macro_build (NULL, s, "x", op[0]);
13566 start_noreorder ();
13567 macro_build (NULL, s, ".,x,y", op[1], op[2]);
13568 expr1.X_add_number = 2;
13569 macro_build (&expr1, "bnez", "x,p", op[2]);
13570 macro_build (NULL, "break", "6", 7);
13572 macro_build (NULL, s2, "x", op[0]);
13577 /* Fall through. */
13579 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", op[1], op[2]);
13580 macro_build (NULL, "mflo", "x", op[0]);
13588 imm_expr.X_add_number = -imm_expr.X_add_number;
13589 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,F", op[0], op[1]);
13593 imm_expr.X_add_number = -imm_expr.X_add_number;
13594 macro_build (&imm_expr, "addiu", "x,k", op[0]);
13598 imm_expr.X_add_number = -imm_expr.X_add_number;
13599 macro_build (&imm_expr, "daddiu", "y,j", op[0]);
13621 goto do_reverse_branch;
13625 goto do_reverse_branch;
13637 goto do_reverse_branch;
13648 macro_build (NULL, s, "x,y", op[0], op[1]);
13649 macro_build (&offset_expr, s2, "p");
13676 goto do_addone_branch_i;
13681 goto do_addone_branch_i;
13696 goto do_addone_branch_i;
13702 do_addone_branch_i:
13703 ++imm_expr.X_add_number;
13706 macro_build (&imm_expr, s, s3, op[0]);
13707 macro_build (&offset_expr, s2, "p");
13711 expr1.X_add_number = 0;
13712 macro_build (&expr1, "slti", "x,8", op[1]);
13713 if (op[0] != op[1])
13714 macro_build (NULL, "move", "y,X", op[0], mips16_to_32_reg_map[op[1]]);
13715 expr1.X_add_number = 2;
13716 macro_build (&expr1, "bteqz", "p");
13717 macro_build (NULL, "neg", "x,w", op[0], op[0]);
13722 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
13723 opcode bits in *OPCODE_EXTRA. */
13725 static struct mips_opcode *
13726 mips_lookup_insn (struct hash_control *hash, const char *start,
13727 ssize_t length, unsigned int *opcode_extra)
13729 char *name, *dot, *p;
13730 unsigned int mask, suffix;
13732 struct mips_opcode *insn;
13734 /* Make a copy of the instruction so that we can fiddle with it. */
13735 name = xstrndup (start, length);
13737 /* Look up the instruction as-is. */
13738 insn = (struct mips_opcode *) hash_find (hash, name);
13742 dot = strchr (name, '.');
13745 /* Try to interpret the text after the dot as a VU0 channel suffix. */
13746 p = mips_parse_vu0_channels (dot + 1, &mask);
13747 if (*p == 0 && mask != 0)
13750 insn = (struct mips_opcode *) hash_find (hash, name);
13752 if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0)
13754 *opcode_extra |= mask << mips_vu0_channel_mask.lsb;
13760 if (mips_opts.micromips)
13762 /* See if there's an instruction size override suffix,
13763 either `16' or `32', at the end of the mnemonic proper,
13764 that defines the operation, i.e. before the first `.'
13765 character if any. Strip it and retry. */
13766 opend = dot != NULL ? dot - name : length;
13767 if (opend >= 3 && name[opend - 2] == '1' && name[opend - 1] == '6')
13769 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
13775 memcpy (name + opend - 2, name + opend, length - opend + 1);
13776 insn = (struct mips_opcode *) hash_find (hash, name);
13779 forced_insn_length = suffix;
13791 /* Assemble an instruction into its binary format. If the instruction
13792 is a macro, set imm_expr and offset_expr to the values associated
13793 with "I" and "A" operands respectively. Otherwise store the value
13794 of the relocatable field (if any) in offset_expr. In both cases
13795 set offset_reloc to the relocation operators applied to offset_expr. */
13798 mips_ip (char *str, struct mips_cl_insn *insn)
13800 const struct mips_opcode *first, *past;
13801 struct hash_control *hash;
13804 struct mips_operand_token *tokens;
13805 unsigned int opcode_extra;
13807 if (mips_opts.micromips)
13809 hash = micromips_op_hash;
13810 past = µmips_opcodes[bfd_micromips_num_opcodes];
13815 past = &mips_opcodes[NUMOPCODES];
13817 forced_insn_length = 0;
13820 /* We first try to match an instruction up to a space or to the end. */
13821 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
13824 first = mips_lookup_insn (hash, str, end, &opcode_extra);
13827 set_insn_error (0, _("unrecognized opcode"));
13831 if (strcmp (first->name, "li.s") == 0)
13833 else if (strcmp (first->name, "li.d") == 0)
13837 tokens = mips_parse_arguments (str + end, format);
13841 if (!match_insns (insn, first, past, tokens, opcode_extra, FALSE)
13842 && !match_insns (insn, first, past, tokens, opcode_extra, TRUE))
13843 set_insn_error (0, _("invalid operands"));
13845 obstack_free (&mips_operand_tokens, tokens);
13848 /* As for mips_ip, but used when assembling MIPS16 code.
13849 Also set forced_insn_length to the resulting instruction size in
13850 bytes if the user explicitly requested a small or extended instruction. */
13853 mips16_ip (char *str, struct mips_cl_insn *insn)
13856 struct mips_opcode *first;
13857 struct mips_operand_token *tokens;
13860 for (s = str; ISLOWER (*s); ++s)
13882 else if (*s == 'e')
13889 else if (*s++ == ' ')
13891 /* Fall through. */
13893 set_insn_error (0, _("unrecognized opcode"));
13896 forced_insn_length = l;
13899 first = (struct mips_opcode *) hash_find (mips16_op_hash, str);
13904 set_insn_error (0, _("unrecognized opcode"));
13908 tokens = mips_parse_arguments (s, 0);
13912 if (!match_mips16_insns (insn, first, tokens))
13913 set_insn_error (0, _("invalid operands"));
13915 obstack_free (&mips_operand_tokens, tokens);
13918 /* Marshal immediate value VAL for an extended MIPS16 instruction.
13919 NBITS is the number of significant bits in VAL. */
13921 static unsigned long
13922 mips16_immed_extend (offsetT val, unsigned int nbits)
13927 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
13930 else if (nbits == 15)
13932 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
13937 extval = ((val & 0x1f) << 6) | (val & 0x20);
13940 return (extval << 16) | val;
13943 /* Like decode_mips16_operand, but require the operand to be defined and
13944 require it to be an integer. */
13946 static const struct mips_int_operand *
13947 mips16_immed_operand (int type, bfd_boolean extended_p)
13949 const struct mips_operand *operand;
13951 operand = decode_mips16_operand (type, extended_p);
13952 if (!operand || (operand->type != OP_INT && operand->type != OP_PCREL))
13954 return (const struct mips_int_operand *) operand;
13957 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
13960 mips16_immed_in_range_p (const struct mips_int_operand *operand,
13961 bfd_reloc_code_real_type reloc, offsetT sval)
13963 int min_val, max_val;
13965 min_val = mips_int_operand_min (operand);
13966 max_val = mips_int_operand_max (operand);
13967 if (reloc != BFD_RELOC_UNUSED)
13970 sval = SEXT_16BIT (sval);
13975 return (sval >= min_val
13977 && (sval & ((1 << operand->shift) - 1)) == 0);
13980 /* Install immediate value VAL into MIPS16 instruction *INSN,
13981 extending it if necessary. The instruction in *INSN may
13982 already be extended.
13984 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
13985 if none. In the former case, VAL is a 16-bit number with no
13986 defined signedness.
13988 TYPE is the type of the immediate field. USER_INSN_LENGTH
13989 is the length that the user requested, or 0 if none. */
13992 mips16_immed (const char *file, unsigned int line, int type,
13993 bfd_reloc_code_real_type reloc, offsetT val,
13994 unsigned int user_insn_length, unsigned long *insn)
13996 const struct mips_int_operand *operand;
13997 unsigned int uval, length;
13999 operand = mips16_immed_operand (type, FALSE);
14000 if (!mips16_immed_in_range_p (operand, reloc, val))
14002 /* We need an extended instruction. */
14003 if (user_insn_length == 2)
14004 as_bad_where (file, line, _("invalid unextended operand value"));
14006 *insn |= MIPS16_EXTEND;
14008 else if (user_insn_length == 4)
14010 /* The operand doesn't force an unextended instruction to be extended.
14011 Warn if the user wanted an extended instruction anyway. */
14012 *insn |= MIPS16_EXTEND;
14013 as_warn_where (file, line,
14014 _("extended operand requested but not required"));
14017 length = mips16_opcode_length (*insn);
14020 operand = mips16_immed_operand (type, TRUE);
14021 if (!mips16_immed_in_range_p (operand, reloc, val))
14022 as_bad_where (file, line,
14023 _("operand value out of range for instruction"));
14025 uval = ((unsigned int) val >> operand->shift) - operand->bias;
14026 if (length == 2 || operand->root.lsb != 0)
14027 *insn = mips_insert_operand (&operand->root, *insn, uval);
14029 *insn |= mips16_immed_extend (uval, operand->root.size);
14032 struct percent_op_match
14035 bfd_reloc_code_real_type reloc;
14038 static const struct percent_op_match mips_percent_op[] =
14040 {"%lo", BFD_RELOC_LO16},
14041 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
14042 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
14043 {"%call16", BFD_RELOC_MIPS_CALL16},
14044 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
14045 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
14046 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
14047 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
14048 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
14049 {"%got", BFD_RELOC_MIPS_GOT16},
14050 {"%gp_rel", BFD_RELOC_GPREL16},
14051 {"%half", BFD_RELOC_16},
14052 {"%highest", BFD_RELOC_MIPS_HIGHEST},
14053 {"%higher", BFD_RELOC_MIPS_HIGHER},
14054 {"%neg", BFD_RELOC_MIPS_SUB},
14055 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
14056 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
14057 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
14058 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
14059 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
14060 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
14061 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
14062 {"%hi", BFD_RELOC_HI16_S},
14063 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL},
14064 {"%pcrel_lo", BFD_RELOC_LO16_PCREL}
14067 static const struct percent_op_match mips16_percent_op[] =
14069 {"%lo", BFD_RELOC_MIPS16_LO16},
14070 {"%gprel", BFD_RELOC_MIPS16_GPREL},
14071 {"%got", BFD_RELOC_MIPS16_GOT16},
14072 {"%call16", BFD_RELOC_MIPS16_CALL16},
14073 {"%hi", BFD_RELOC_MIPS16_HI16_S},
14074 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
14075 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
14076 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
14077 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
14078 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
14079 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
14080 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
14084 /* Return true if *STR points to a relocation operator. When returning true,
14085 move *STR over the operator and store its relocation code in *RELOC.
14086 Leave both *STR and *RELOC alone when returning false. */
14089 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
14091 const struct percent_op_match *percent_op;
14094 if (mips_opts.mips16)
14096 percent_op = mips16_percent_op;
14097 limit = ARRAY_SIZE (mips16_percent_op);
14101 percent_op = mips_percent_op;
14102 limit = ARRAY_SIZE (mips_percent_op);
14105 for (i = 0; i < limit; i++)
14106 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
14108 int len = strlen (percent_op[i].str);
14110 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
14113 *str += strlen (percent_op[i].str);
14114 *reloc = percent_op[i].reloc;
14116 /* Check whether the output BFD supports this relocation.
14117 If not, issue an error and fall back on something safe. */
14118 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
14120 as_bad (_("relocation %s isn't supported by the current ABI"),
14121 percent_op[i].str);
14122 *reloc = BFD_RELOC_UNUSED;
14130 /* Parse string STR as a 16-bit relocatable operand. Store the
14131 expression in *EP and the relocations in the array starting
14132 at RELOC. Return the number of relocation operators used.
14134 On exit, EXPR_END points to the first character after the expression. */
14137 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
14140 bfd_reloc_code_real_type reversed_reloc[3];
14141 size_t reloc_index, i;
14142 int crux_depth, str_depth;
14145 /* Search for the start of the main expression, recoding relocations
14146 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14147 of the main expression and with CRUX_DEPTH containing the number
14148 of open brackets at that point. */
14155 crux_depth = str_depth;
14157 /* Skip over whitespace and brackets, keeping count of the number
14159 while (*str == ' ' || *str == '\t' || *str == '(')
14164 && reloc_index < (HAVE_NEWABI ? 3 : 1)
14165 && parse_relocation (&str, &reversed_reloc[reloc_index]));
14167 my_getExpression (ep, crux);
14170 /* Match every open bracket. */
14171 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
14175 if (crux_depth > 0)
14176 as_bad (_("unclosed '('"));
14180 if (reloc_index != 0)
14182 prev_reloc_op_frag = frag_now;
14183 for (i = 0; i < reloc_index; i++)
14184 reloc[i] = reversed_reloc[reloc_index - 1 - i];
14187 return reloc_index;
14191 my_getExpression (expressionS *ep, char *str)
14195 save_in = input_line_pointer;
14196 input_line_pointer = str;
14198 expr_end = input_line_pointer;
14199 input_line_pointer = save_in;
14203 md_atof (int type, char *litP, int *sizeP)
14205 return ieee_md_atof (type, litP, sizeP, target_big_endian);
14209 md_number_to_chars (char *buf, valueT val, int n)
14211 if (target_big_endian)
14212 number_to_chars_bigendian (buf, val, n);
14214 number_to_chars_littleendian (buf, val, n);
14217 static int support_64bit_objects(void)
14219 const char **list, **l;
14222 list = bfd_target_list ();
14223 for (l = list; *l != NULL; l++)
14224 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
14225 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
14227 yes = (*l != NULL);
14232 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14233 NEW_VALUE. Warn if another value was already specified. Note:
14234 we have to defer parsing the -march and -mtune arguments in order
14235 to handle 'from-abi' correctly, since the ABI might be specified
14236 in a later argument. */
14239 mips_set_option_string (const char **string_ptr, const char *new_value)
14241 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
14242 as_warn (_("a different %s was already specified, is now %s"),
14243 string_ptr == &mips_arch_string ? "-march" : "-mtune",
14246 *string_ptr = new_value;
14250 md_parse_option (int c, const char *arg)
14254 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
14255 if (c == mips_ases[i].option_on || c == mips_ases[i].option_off)
14257 file_ase_explicit |= mips_set_ase (&mips_ases[i], &file_mips_opts,
14258 c == mips_ases[i].option_on);
14264 case OPTION_CONSTRUCT_FLOATS:
14265 mips_disable_float_construction = 0;
14268 case OPTION_NO_CONSTRUCT_FLOATS:
14269 mips_disable_float_construction = 1;
14281 target_big_endian = 1;
14285 target_big_endian = 0;
14291 else if (arg[0] == '0')
14293 else if (arg[0] == '1')
14303 mips_debug = atoi (arg);
14307 file_mips_opts.isa = ISA_MIPS1;
14311 file_mips_opts.isa = ISA_MIPS2;
14315 file_mips_opts.isa = ISA_MIPS3;
14319 file_mips_opts.isa = ISA_MIPS4;
14323 file_mips_opts.isa = ISA_MIPS5;
14326 case OPTION_MIPS32:
14327 file_mips_opts.isa = ISA_MIPS32;
14330 case OPTION_MIPS32R2:
14331 file_mips_opts.isa = ISA_MIPS32R2;
14334 case OPTION_MIPS32R3:
14335 file_mips_opts.isa = ISA_MIPS32R3;
14338 case OPTION_MIPS32R5:
14339 file_mips_opts.isa = ISA_MIPS32R5;
14342 case OPTION_MIPS32R6:
14343 file_mips_opts.isa = ISA_MIPS32R6;
14346 case OPTION_MIPS64R2:
14347 file_mips_opts.isa = ISA_MIPS64R2;
14350 case OPTION_MIPS64R3:
14351 file_mips_opts.isa = ISA_MIPS64R3;
14354 case OPTION_MIPS64R5:
14355 file_mips_opts.isa = ISA_MIPS64R5;
14358 case OPTION_MIPS64R6:
14359 file_mips_opts.isa = ISA_MIPS64R6;
14362 case OPTION_MIPS64:
14363 file_mips_opts.isa = ISA_MIPS64;
14367 mips_set_option_string (&mips_tune_string, arg);
14371 mips_set_option_string (&mips_arch_string, arg);
14375 mips_set_option_string (&mips_arch_string, "4650");
14376 mips_set_option_string (&mips_tune_string, "4650");
14379 case OPTION_NO_M4650:
14383 mips_set_option_string (&mips_arch_string, "4010");
14384 mips_set_option_string (&mips_tune_string, "4010");
14387 case OPTION_NO_M4010:
14391 mips_set_option_string (&mips_arch_string, "4100");
14392 mips_set_option_string (&mips_tune_string, "4100");
14395 case OPTION_NO_M4100:
14399 mips_set_option_string (&mips_arch_string, "3900");
14400 mips_set_option_string (&mips_tune_string, "3900");
14403 case OPTION_NO_M3900:
14406 case OPTION_MICROMIPS:
14407 if (file_mips_opts.mips16 == 1)
14409 as_bad (_("-mmicromips cannot be used with -mips16"));
14412 file_mips_opts.micromips = 1;
14413 mips_no_prev_insn ();
14416 case OPTION_NO_MICROMIPS:
14417 file_mips_opts.micromips = 0;
14418 mips_no_prev_insn ();
14421 case OPTION_MIPS16:
14422 if (file_mips_opts.micromips == 1)
14424 as_bad (_("-mips16 cannot be used with -micromips"));
14427 file_mips_opts.mips16 = 1;
14428 mips_no_prev_insn ();
14431 case OPTION_NO_MIPS16:
14432 file_mips_opts.mips16 = 0;
14433 mips_no_prev_insn ();
14436 case OPTION_FIX_24K:
14440 case OPTION_NO_FIX_24K:
14444 case OPTION_FIX_RM7000:
14445 mips_fix_rm7000 = 1;
14448 case OPTION_NO_FIX_RM7000:
14449 mips_fix_rm7000 = 0;
14452 case OPTION_FIX_LOONGSON2F_JUMP:
14453 mips_fix_loongson2f_jump = TRUE;
14456 case OPTION_NO_FIX_LOONGSON2F_JUMP:
14457 mips_fix_loongson2f_jump = FALSE;
14460 case OPTION_FIX_LOONGSON2F_NOP:
14461 mips_fix_loongson2f_nop = TRUE;
14464 case OPTION_NO_FIX_LOONGSON2F_NOP:
14465 mips_fix_loongson2f_nop = FALSE;
14468 case OPTION_FIX_VR4120:
14469 mips_fix_vr4120 = 1;
14472 case OPTION_NO_FIX_VR4120:
14473 mips_fix_vr4120 = 0;
14476 case OPTION_FIX_VR4130:
14477 mips_fix_vr4130 = 1;
14480 case OPTION_NO_FIX_VR4130:
14481 mips_fix_vr4130 = 0;
14484 case OPTION_FIX_CN63XXP1:
14485 mips_fix_cn63xxp1 = TRUE;
14488 case OPTION_NO_FIX_CN63XXP1:
14489 mips_fix_cn63xxp1 = FALSE;
14492 case OPTION_RELAX_BRANCH:
14493 mips_relax_branch = 1;
14496 case OPTION_NO_RELAX_BRANCH:
14497 mips_relax_branch = 0;
14500 case OPTION_INSN32:
14501 file_mips_opts.insn32 = TRUE;
14504 case OPTION_NO_INSN32:
14505 file_mips_opts.insn32 = FALSE;
14508 case OPTION_MSHARED:
14509 mips_in_shared = TRUE;
14512 case OPTION_MNO_SHARED:
14513 mips_in_shared = FALSE;
14516 case OPTION_MSYM32:
14517 file_mips_opts.sym32 = TRUE;
14520 case OPTION_MNO_SYM32:
14521 file_mips_opts.sym32 = FALSE;
14524 /* When generating ELF code, we permit -KPIC and -call_shared to
14525 select SVR4_PIC, and -non_shared to select no PIC. This is
14526 intended to be compatible with Irix 5. */
14527 case OPTION_CALL_SHARED:
14528 mips_pic = SVR4_PIC;
14529 mips_abicalls = TRUE;
14532 case OPTION_CALL_NONPIC:
14534 mips_abicalls = TRUE;
14537 case OPTION_NON_SHARED:
14539 mips_abicalls = FALSE;
14542 /* The -xgot option tells the assembler to use 32 bit offsets
14543 when accessing the got in SVR4_PIC mode. It is for Irix
14550 g_switch_value = atoi (arg);
14554 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14557 mips_abi = O32_ABI;
14561 mips_abi = N32_ABI;
14565 mips_abi = N64_ABI;
14566 if (!support_64bit_objects())
14567 as_fatal (_("no compiled in support for 64 bit object file format"));
14571 file_mips_opts.gp = 32;
14575 file_mips_opts.gp = 64;
14579 file_mips_opts.fp = 32;
14583 file_mips_opts.fp = 0;
14587 file_mips_opts.fp = 64;
14590 case OPTION_ODD_SPREG:
14591 file_mips_opts.oddspreg = 1;
14594 case OPTION_NO_ODD_SPREG:
14595 file_mips_opts.oddspreg = 0;
14598 case OPTION_SINGLE_FLOAT:
14599 file_mips_opts.single_float = 1;
14602 case OPTION_DOUBLE_FLOAT:
14603 file_mips_opts.single_float = 0;
14606 case OPTION_SOFT_FLOAT:
14607 file_mips_opts.soft_float = 1;
14610 case OPTION_HARD_FLOAT:
14611 file_mips_opts.soft_float = 0;
14615 if (strcmp (arg, "32") == 0)
14616 mips_abi = O32_ABI;
14617 else if (strcmp (arg, "o64") == 0)
14618 mips_abi = O64_ABI;
14619 else if (strcmp (arg, "n32") == 0)
14620 mips_abi = N32_ABI;
14621 else if (strcmp (arg, "64") == 0)
14623 mips_abi = N64_ABI;
14624 if (! support_64bit_objects())
14625 as_fatal (_("no compiled in support for 64 bit object file "
14628 else if (strcmp (arg, "eabi") == 0)
14629 mips_abi = EABI_ABI;
14632 as_fatal (_("invalid abi -mabi=%s"), arg);
14637 case OPTION_M7000_HILO_FIX:
14638 mips_7000_hilo_fix = TRUE;
14641 case OPTION_MNO_7000_HILO_FIX:
14642 mips_7000_hilo_fix = FALSE;
14645 case OPTION_MDEBUG:
14646 mips_flag_mdebug = TRUE;
14649 case OPTION_NO_MDEBUG:
14650 mips_flag_mdebug = FALSE;
14654 mips_flag_pdr = TRUE;
14657 case OPTION_NO_PDR:
14658 mips_flag_pdr = FALSE;
14661 case OPTION_MVXWORKS_PIC:
14662 mips_pic = VXWORKS_PIC;
14666 if (strcmp (arg, "2008") == 0)
14668 else if (strcmp (arg, "legacy") == 0)
14672 as_fatal (_("invalid NaN setting -mnan=%s"), arg);
14681 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
14686 /* Set up globals to tune for the ISA or processor described by INFO. */
14689 mips_set_tune (const struct mips_cpu_info *info)
14692 mips_tune = info->cpu;
14697 mips_after_parse_args (void)
14699 const struct mips_cpu_info *arch_info = 0;
14700 const struct mips_cpu_info *tune_info = 0;
14702 /* GP relative stuff not working for PE */
14703 if (strncmp (TARGET_OS, "pe", 2) == 0)
14705 if (g_switch_seen && g_switch_value != 0)
14706 as_bad (_("-G not supported in this configuration"));
14707 g_switch_value = 0;
14710 if (mips_abi == NO_ABI)
14711 mips_abi = MIPS_DEFAULT_ABI;
14713 /* The following code determines the architecture.
14714 Similar code was added to GCC 3.3 (see override_options() in
14715 config/mips/mips.c). The GAS and GCC code should be kept in sync
14716 as much as possible. */
14718 if (mips_arch_string != 0)
14719 arch_info = mips_parse_cpu ("-march", mips_arch_string);
14721 if (file_mips_opts.isa != ISA_UNKNOWN)
14723 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
14724 ISA level specified by -mipsN, while arch_info->isa contains
14725 the -march selection (if any). */
14726 if (arch_info != 0)
14728 /* -march takes precedence over -mipsN, since it is more descriptive.
14729 There's no harm in specifying both as long as the ISA levels
14731 if (file_mips_opts.isa != arch_info->isa)
14732 as_bad (_("-%s conflicts with the other architecture options,"
14733 " which imply -%s"),
14734 mips_cpu_info_from_isa (file_mips_opts.isa)->name,
14735 mips_cpu_info_from_isa (arch_info->isa)->name);
14738 arch_info = mips_cpu_info_from_isa (file_mips_opts.isa);
14741 if (arch_info == 0)
14743 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
14744 gas_assert (arch_info);
14747 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
14748 as_bad (_("-march=%s is not compatible with the selected ABI"),
14751 file_mips_opts.arch = arch_info->cpu;
14752 file_mips_opts.isa = arch_info->isa;
14754 /* Set up initial mips_opts state. */
14755 mips_opts = file_mips_opts;
14757 /* The register size inference code is now placed in
14758 file_mips_check_options. */
14760 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
14762 if (mips_tune_string != 0)
14763 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
14765 if (tune_info == 0)
14766 mips_set_tune (arch_info);
14768 mips_set_tune (tune_info);
14770 if (mips_flag_mdebug < 0)
14771 mips_flag_mdebug = 0;
14775 mips_init_after_args (void)
14777 /* initialize opcodes */
14778 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
14779 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
14783 md_pcrel_from (fixS *fixP)
14785 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
14786 switch (fixP->fx_r_type)
14788 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
14789 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
14790 /* Return the address of the delay slot. */
14793 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
14794 case BFD_RELOC_MICROMIPS_JMP:
14795 case BFD_RELOC_MIPS16_16_PCREL_S1:
14796 case BFD_RELOC_16_PCREL_S2:
14797 case BFD_RELOC_MIPS_21_PCREL_S2:
14798 case BFD_RELOC_MIPS_26_PCREL_S2:
14799 case BFD_RELOC_MIPS_JMP:
14800 /* Return the address of the delay slot. */
14803 case BFD_RELOC_MIPS_18_PCREL_S3:
14804 /* Return the aligned address of the doubleword containing
14805 the instruction. */
14813 /* This is called before the symbol table is processed. In order to
14814 work with gcc when using mips-tfile, we must keep all local labels.
14815 However, in other cases, we want to discard them. If we were
14816 called with -g, but we didn't see any debugging information, it may
14817 mean that gcc is smuggling debugging information through to
14818 mips-tfile, in which case we must generate all local labels. */
14821 mips_frob_file_before_adjust (void)
14823 #ifndef NO_ECOFF_DEBUGGING
14824 if (ECOFF_DEBUGGING
14826 && ! ecoff_debugging_seen)
14827 flag_keep_locals = 1;
14831 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
14832 the corresponding LO16 reloc. This is called before md_apply_fix and
14833 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
14834 relocation operators.
14836 For our purposes, a %lo() expression matches a %got() or %hi()
14839 (a) it refers to the same symbol; and
14840 (b) the offset applied in the %lo() expression is no lower than
14841 the offset applied in the %got() or %hi().
14843 (b) allows us to cope with code like:
14846 lh $4,%lo(foo+2)($4)
14848 ...which is legal on RELA targets, and has a well-defined behaviour
14849 if the user knows that adding 2 to "foo" will not induce a carry to
14852 When several %lo()s match a particular %got() or %hi(), we use the
14853 following rules to distinguish them:
14855 (1) %lo()s with smaller offsets are a better match than %lo()s with
14858 (2) %lo()s with no matching %got() or %hi() are better than those
14859 that already have a matching %got() or %hi().
14861 (3) later %lo()s are better than earlier %lo()s.
14863 These rules are applied in order.
14865 (1) means, among other things, that %lo()s with identical offsets are
14866 chosen if they exist.
14868 (2) means that we won't associate several high-part relocations with
14869 the same low-part relocation unless there's no alternative. Having
14870 several high parts for the same low part is a GNU extension; this rule
14871 allows careful users to avoid it.
14873 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
14874 with the last high-part relocation being at the front of the list.
14875 It therefore makes sense to choose the last matching low-part
14876 relocation, all other things being equal. It's also easier
14877 to code that way. */
14880 mips_frob_file (void)
14882 struct mips_hi_fixup *l;
14883 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
14885 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
14887 segment_info_type *seginfo;
14888 bfd_boolean matched_lo_p;
14889 fixS **hi_pos, **lo_pos, **pos;
14891 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
14893 /* If a GOT16 relocation turns out to be against a global symbol,
14894 there isn't supposed to be a matching LO. Ignore %gots against
14895 constants; we'll report an error for those later. */
14896 if (got16_reloc_p (l->fixp->fx_r_type)
14897 && !(l->fixp->fx_addsy
14898 && pic_need_relax (l->fixp->fx_addsy, l->seg)))
14901 /* Check quickly whether the next fixup happens to be a matching %lo. */
14902 if (fixup_has_matching_lo_p (l->fixp))
14905 seginfo = seg_info (l->seg);
14907 /* Set HI_POS to the position of this relocation in the chain.
14908 Set LO_POS to the position of the chosen low-part relocation.
14909 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
14910 relocation that matches an immediately-preceding high-part
14914 matched_lo_p = FALSE;
14915 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
14917 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
14919 if (*pos == l->fixp)
14922 if ((*pos)->fx_r_type == looking_for_rtype
14923 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
14924 && (*pos)->fx_offset >= l->fixp->fx_offset
14926 || (*pos)->fx_offset < (*lo_pos)->fx_offset
14928 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
14931 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
14932 && fixup_has_matching_lo_p (*pos));
14935 /* If we found a match, remove the high-part relocation from its
14936 current position and insert it before the low-part relocation.
14937 Make the offsets match so that fixup_has_matching_lo_p()
14940 We don't warn about unmatched high-part relocations since some
14941 versions of gcc have been known to emit dead "lui ...%hi(...)"
14943 if (lo_pos != NULL)
14945 l->fixp->fx_offset = (*lo_pos)->fx_offset;
14946 if (l->fixp->fx_next != *lo_pos)
14948 *hi_pos = l->fixp->fx_next;
14949 l->fixp->fx_next = *lo_pos;
14957 mips_force_relocation (fixS *fixp)
14959 if (generic_force_reloc (fixp))
14962 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
14963 so that the linker relaxation can update targets. */
14964 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
14965 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
14966 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
14969 /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2
14970 and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and
14971 microMIPS symbols so that we can do cross-mode branch diagnostics
14972 and BAL to JALX conversion by the linker. */
14973 if ((fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
14974 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
14975 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2)
14977 && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp->fx_addsy)))
14980 /* We want all PC-relative relocations to be kept for R6 relaxation. */
14981 if (ISA_IS_R6 (file_mips_opts.isa)
14982 && (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
14983 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
14984 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2
14985 || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3
14986 || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2
14987 || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL
14988 || fixp->fx_r_type == BFD_RELOC_LO16_PCREL))
14994 /* Implement TC_FORCE_RELOCATION_ABS. */
14997 mips_force_relocation_abs (fixS *fixp)
14999 if (generic_force_reloc (fixp))
15002 /* These relocations do not have enough bits in the in-place addend
15003 to hold an arbitrary absolute section's offset. */
15004 if (HAVE_IN_PLACE_ADDENDS && limited_pcrel_reloc_p (fixp->fx_r_type))
15010 /* Read the instruction associated with RELOC from BUF. */
15012 static unsigned int
15013 read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc)
15015 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
15016 return read_compressed_insn (buf, 4);
15018 return read_insn (buf);
15021 /* Write instruction INSN to BUF, given that it has been relocated
15025 write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc,
15026 unsigned long insn)
15028 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
15029 write_compressed_insn (buf, insn, 4);
15031 write_insn (buf, insn);
15034 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15035 to a symbol in another ISA mode, which cannot be converted to JALX. */
15038 fix_bad_cross_mode_jump_p (fixS *fixP)
15040 unsigned long opcode;
15044 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
15047 other = S_GET_OTHER (fixP->fx_addsy);
15048 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15049 opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26;
15050 switch (fixP->fx_r_type)
15052 case BFD_RELOC_MIPS_JMP:
15053 return opcode != 0x1d && opcode != 0x03 && ELF_ST_IS_COMPRESSED (other);
15054 case BFD_RELOC_MICROMIPS_JMP:
15055 return opcode != 0x3c && opcode != 0x3d && !ELF_ST_IS_MICROMIPS (other);
15061 /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX
15062 jump to a symbol in the same ISA mode. */
15065 fix_bad_same_mode_jalx_p (fixS *fixP)
15067 unsigned long opcode;
15071 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
15074 other = S_GET_OTHER (fixP->fx_addsy);
15075 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15076 opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26;
15077 switch (fixP->fx_r_type)
15079 case BFD_RELOC_MIPS_JMP:
15080 return opcode == 0x1d && !ELF_ST_IS_COMPRESSED (other);
15081 case BFD_RELOC_MIPS16_JMP:
15082 return opcode == 0x07 && ELF_ST_IS_COMPRESSED (other);
15083 case BFD_RELOC_MICROMIPS_JMP:
15084 return opcode == 0x3c && ELF_ST_IS_COMPRESSED (other);
15090 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15091 to a symbol whose value plus addend is not aligned according to the
15092 ultimate (after linker relaxation) jump instruction's immediate field
15093 requirement, either to (1 << SHIFT), or, for jumps from microMIPS to
15094 regular MIPS code, to (1 << 2). */
15097 fix_bad_misaligned_jump_p (fixS *fixP, int shift)
15099 bfd_boolean micro_to_mips_p;
15103 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
15106 other = S_GET_OTHER (fixP->fx_addsy);
15107 val = S_GET_VALUE (fixP->fx_addsy) | ELF_ST_IS_COMPRESSED (other);
15108 val += fixP->fx_offset;
15109 micro_to_mips_p = (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP
15110 && !ELF_ST_IS_MICROMIPS (other));
15111 return ((val & ((1 << (micro_to_mips_p ? 2 : shift)) - 1))
15112 != ELF_ST_IS_COMPRESSED (other));
15115 /* Return TRUE if the instruction pointed to by FIXP is an invalid branch
15116 to a symbol whose annotation indicates another ISA mode. For absolute
15117 symbols check the ISA bit instead.
15119 We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS
15120 symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular
15121 MIPS symbols and associated with BAL instructions as these instructions
15122 may be be converted to JALX by the linker. */
15125 fix_bad_cross_mode_branch_p (fixS *fixP)
15127 bfd_boolean absolute_p;
15128 unsigned long opcode;
15134 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
15137 symsec = S_GET_SEGMENT (fixP->fx_addsy);
15138 absolute_p = bfd_is_abs_section (symsec);
15140 val = S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset;
15141 other = S_GET_OTHER (fixP->fx_addsy);
15143 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15144 opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 16;
15145 switch (fixP->fx_r_type)
15147 case BFD_RELOC_16_PCREL_S2:
15148 return ((absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other))
15149 && opcode != 0x0411);
15150 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15151 return ((absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other))
15152 && opcode != 0x4060);
15153 case BFD_RELOC_MIPS_21_PCREL_S2:
15154 case BFD_RELOC_MIPS_26_PCREL_S2:
15155 return absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other);
15156 case BFD_RELOC_MIPS16_16_PCREL_S1:
15157 return absolute_p ? !(val & 1) : !ELF_ST_IS_MIPS16 (other);
15158 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15159 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15160 return absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other);
15166 /* Return TRUE if the symbol plus addend associated with a regular MIPS
15167 branch instruction pointed to by FIXP is not aligned according to the
15168 branch instruction's immediate field requirement. We need the addend
15169 to preserve the ISA bit and also the sum must not have bit 2 set. We
15170 must explicitly OR in the ISA bit from symbol annotation as the bit
15171 won't be set in the symbol's value then. */
15174 fix_bad_misaligned_branch_p (fixS *fixP)
15176 bfd_boolean absolute_p;
15183 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
15186 symsec = S_GET_SEGMENT (fixP->fx_addsy);
15187 absolute_p = bfd_is_abs_section (symsec);
15189 val = S_GET_VALUE (fixP->fx_addsy);
15190 other = S_GET_OTHER (fixP->fx_addsy);
15191 off = fixP->fx_offset;
15193 isa_bit = absolute_p ? (val + off) & 1 : ELF_ST_IS_COMPRESSED (other);
15194 val |= ELF_ST_IS_COMPRESSED (other);
15196 return (val & 0x3) != isa_bit;
15199 /* Make the necessary checks on a regular MIPS branch pointed to by FIXP
15200 and its calculated value VAL. */
15203 fix_validate_branch (fixS *fixP, valueT val)
15205 if (fixP->fx_done && (val & 0x3) != 0)
15206 as_bad_where (fixP->fx_file, fixP->fx_line,
15207 _("branch to misaligned address (0x%lx)"),
15208 (long) (val + md_pcrel_from (fixP)));
15209 else if (fix_bad_cross_mode_branch_p (fixP))
15210 as_bad_where (fixP->fx_file, fixP->fx_line,
15211 _("branch to a symbol in another ISA mode"));
15212 else if (fix_bad_misaligned_branch_p (fixP))
15213 as_bad_where (fixP->fx_file, fixP->fx_line,
15214 _("branch to misaligned address (0x%lx)"),
15215 (long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset));
15216 else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x3) != 0)
15217 as_bad_where (fixP->fx_file, fixP->fx_line,
15218 _("cannot encode misaligned addend "
15219 "in the relocatable field (0x%lx)"),
15220 (long) fixP->fx_offset);
15223 /* Apply a fixup to the object file. */
15226 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
15229 unsigned long insn;
15230 reloc_howto_type *howto;
15232 if (fixP->fx_pcrel)
15233 switch (fixP->fx_r_type)
15235 case BFD_RELOC_16_PCREL_S2:
15236 case BFD_RELOC_MIPS16_16_PCREL_S1:
15237 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15238 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15239 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15240 case BFD_RELOC_32_PCREL:
15241 case BFD_RELOC_MIPS_21_PCREL_S2:
15242 case BFD_RELOC_MIPS_26_PCREL_S2:
15243 case BFD_RELOC_MIPS_18_PCREL_S3:
15244 case BFD_RELOC_MIPS_19_PCREL_S2:
15245 case BFD_RELOC_HI16_S_PCREL:
15246 case BFD_RELOC_LO16_PCREL:
15250 fixP->fx_r_type = BFD_RELOC_32_PCREL;
15254 as_bad_where (fixP->fx_file, fixP->fx_line,
15255 _("PC-relative reference to a different section"));
15259 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
15260 that have no MIPS ELF equivalent. */
15261 if (fixP->fx_r_type != BFD_RELOC_8)
15263 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
15268 gas_assert (fixP->fx_size == 2
15269 || fixP->fx_size == 4
15270 || fixP->fx_r_type == BFD_RELOC_8
15271 || fixP->fx_r_type == BFD_RELOC_16
15272 || fixP->fx_r_type == BFD_RELOC_64
15273 || fixP->fx_r_type == BFD_RELOC_CTOR
15274 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
15275 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
15276 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
15277 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
15278 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64
15279 || fixP->fx_r_type == BFD_RELOC_NONE);
15281 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15283 /* Don't treat parts of a composite relocation as done. There are two
15286 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15287 should nevertheless be emitted if the first part is.
15289 (2) In normal usage, composite relocations are never assembly-time
15290 constants. The easiest way of dealing with the pathological
15291 exceptions is to generate a relocation against STN_UNDEF and
15292 leave everything up to the linker. */
15293 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
15296 switch (fixP->fx_r_type)
15298 case BFD_RELOC_MIPS_TLS_GD:
15299 case BFD_RELOC_MIPS_TLS_LDM:
15300 case BFD_RELOC_MIPS_TLS_DTPREL32:
15301 case BFD_RELOC_MIPS_TLS_DTPREL64:
15302 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
15303 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
15304 case BFD_RELOC_MIPS_TLS_GOTTPREL:
15305 case BFD_RELOC_MIPS_TLS_TPREL32:
15306 case BFD_RELOC_MIPS_TLS_TPREL64:
15307 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
15308 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
15309 case BFD_RELOC_MICROMIPS_TLS_GD:
15310 case BFD_RELOC_MICROMIPS_TLS_LDM:
15311 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
15312 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
15313 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
15314 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
15315 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
15316 case BFD_RELOC_MIPS16_TLS_GD:
15317 case BFD_RELOC_MIPS16_TLS_LDM:
15318 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
15319 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
15320 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
15321 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
15322 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
15323 if (fixP->fx_addsy)
15324 S_SET_THREAD_LOCAL (fixP->fx_addsy);
15326 as_bad_where (fixP->fx_file, fixP->fx_line,
15327 _("TLS relocation against a constant"));
15330 case BFD_RELOC_MIPS_JMP:
15331 case BFD_RELOC_MIPS16_JMP:
15332 case BFD_RELOC_MICROMIPS_JMP:
15336 gas_assert (!fixP->fx_done);
15338 /* Shift is 2, unusually, for microMIPS JALX. */
15339 if (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP
15340 && (read_compressed_insn (buf, 4) >> 26) != 0x3c)
15345 if (fix_bad_cross_mode_jump_p (fixP))
15346 as_bad_where (fixP->fx_file, fixP->fx_line,
15347 _("jump to a symbol in another ISA mode"));
15348 else if (fix_bad_same_mode_jalx_p (fixP))
15349 as_bad_where (fixP->fx_file, fixP->fx_line,
15350 _("JALX to a symbol in the same ISA mode"));
15351 else if (fix_bad_misaligned_jump_p (fixP, shift))
15352 as_bad_where (fixP->fx_file, fixP->fx_line,
15353 _("jump to misaligned address (0x%lx)"),
15354 (long) (S_GET_VALUE (fixP->fx_addsy)
15355 + fixP->fx_offset));
15356 else if (HAVE_IN_PLACE_ADDENDS
15357 && (fixP->fx_offset & ((1 << shift) - 1)) != 0)
15358 as_bad_where (fixP->fx_file, fixP->fx_line,
15359 _("cannot encode misaligned addend "
15360 "in the relocatable field (0x%lx)"),
15361 (long) fixP->fx_offset);
15363 /* Fall through. */
15365 case BFD_RELOC_MIPS_SHIFT5:
15366 case BFD_RELOC_MIPS_SHIFT6:
15367 case BFD_RELOC_MIPS_GOT_DISP:
15368 case BFD_RELOC_MIPS_GOT_PAGE:
15369 case BFD_RELOC_MIPS_GOT_OFST:
15370 case BFD_RELOC_MIPS_SUB:
15371 case BFD_RELOC_MIPS_INSERT_A:
15372 case BFD_RELOC_MIPS_INSERT_B:
15373 case BFD_RELOC_MIPS_DELETE:
15374 case BFD_RELOC_MIPS_HIGHEST:
15375 case BFD_RELOC_MIPS_HIGHER:
15376 case BFD_RELOC_MIPS_SCN_DISP:
15377 case BFD_RELOC_MIPS_REL16:
15378 case BFD_RELOC_MIPS_RELGOT:
15379 case BFD_RELOC_MIPS_JALR:
15380 case BFD_RELOC_HI16:
15381 case BFD_RELOC_HI16_S:
15382 case BFD_RELOC_LO16:
15383 case BFD_RELOC_GPREL16:
15384 case BFD_RELOC_MIPS_LITERAL:
15385 case BFD_RELOC_MIPS_CALL16:
15386 case BFD_RELOC_MIPS_GOT16:
15387 case BFD_RELOC_GPREL32:
15388 case BFD_RELOC_MIPS_GOT_HI16:
15389 case BFD_RELOC_MIPS_GOT_LO16:
15390 case BFD_RELOC_MIPS_CALL_HI16:
15391 case BFD_RELOC_MIPS_CALL_LO16:
15392 case BFD_RELOC_HI16_S_PCREL:
15393 case BFD_RELOC_LO16_PCREL:
15394 case BFD_RELOC_MIPS16_GPREL:
15395 case BFD_RELOC_MIPS16_GOT16:
15396 case BFD_RELOC_MIPS16_CALL16:
15397 case BFD_RELOC_MIPS16_HI16:
15398 case BFD_RELOC_MIPS16_HI16_S:
15399 case BFD_RELOC_MIPS16_LO16:
15400 case BFD_RELOC_MICROMIPS_GOT_DISP:
15401 case BFD_RELOC_MICROMIPS_GOT_PAGE:
15402 case BFD_RELOC_MICROMIPS_GOT_OFST:
15403 case BFD_RELOC_MICROMIPS_SUB:
15404 case BFD_RELOC_MICROMIPS_HIGHEST:
15405 case BFD_RELOC_MICROMIPS_HIGHER:
15406 case BFD_RELOC_MICROMIPS_SCN_DISP:
15407 case BFD_RELOC_MICROMIPS_JALR:
15408 case BFD_RELOC_MICROMIPS_HI16:
15409 case BFD_RELOC_MICROMIPS_HI16_S:
15410 case BFD_RELOC_MICROMIPS_LO16:
15411 case BFD_RELOC_MICROMIPS_GPREL16:
15412 case BFD_RELOC_MICROMIPS_LITERAL:
15413 case BFD_RELOC_MICROMIPS_CALL16:
15414 case BFD_RELOC_MICROMIPS_GOT16:
15415 case BFD_RELOC_MICROMIPS_GOT_HI16:
15416 case BFD_RELOC_MICROMIPS_GOT_LO16:
15417 case BFD_RELOC_MICROMIPS_CALL_HI16:
15418 case BFD_RELOC_MICROMIPS_CALL_LO16:
15419 case BFD_RELOC_MIPS_EH:
15424 if (calculate_reloc (fixP->fx_r_type, *valP, &value))
15426 insn = read_reloc_insn (buf, fixP->fx_r_type);
15427 if (mips16_reloc_p (fixP->fx_r_type))
15428 insn |= mips16_immed_extend (value, 16);
15430 insn |= (value & 0xffff);
15431 write_reloc_insn (buf, fixP->fx_r_type, insn);
15434 as_bad_where (fixP->fx_file, fixP->fx_line,
15435 _("unsupported constant in relocation"));
15440 /* This is handled like BFD_RELOC_32, but we output a sign
15441 extended value if we are only 32 bits. */
15444 if (8 <= sizeof (valueT))
15445 md_number_to_chars (buf, *valP, 8);
15450 if ((*valP & 0x80000000) != 0)
15454 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4);
15455 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4);
15460 case BFD_RELOC_RVA:
15462 case BFD_RELOC_32_PCREL:
15465 /* If we are deleting this reloc entry, we must fill in the
15466 value now. This can happen if we have a .word which is not
15467 resolved when it appears but is later defined. */
15469 md_number_to_chars (buf, *valP, fixP->fx_size);
15472 case BFD_RELOC_MIPS_21_PCREL_S2:
15473 fix_validate_branch (fixP, *valP);
15474 if (!fixP->fx_done)
15477 if (*valP + 0x400000 <= 0x7fffff)
15479 insn = read_insn (buf);
15480 insn |= (*valP >> 2) & 0x1fffff;
15481 write_insn (buf, insn);
15484 as_bad_where (fixP->fx_file, fixP->fx_line,
15485 _("branch out of range"));
15488 case BFD_RELOC_MIPS_26_PCREL_S2:
15489 fix_validate_branch (fixP, *valP);
15490 if (!fixP->fx_done)
15493 if (*valP + 0x8000000 <= 0xfffffff)
15495 insn = read_insn (buf);
15496 insn |= (*valP >> 2) & 0x3ffffff;
15497 write_insn (buf, insn);
15500 as_bad_where (fixP->fx_file, fixP->fx_line,
15501 _("branch out of range"));
15504 case BFD_RELOC_MIPS_18_PCREL_S3:
15505 if (fixP->fx_addsy && (S_GET_VALUE (fixP->fx_addsy) & 0x7) != 0)
15506 as_bad_where (fixP->fx_file, fixP->fx_line,
15507 _("PC-relative access using misaligned symbol (%lx)"),
15508 (long) S_GET_VALUE (fixP->fx_addsy));
15509 if ((fixP->fx_offset & 0x7) != 0)
15510 as_bad_where (fixP->fx_file, fixP->fx_line,
15511 _("PC-relative access using misaligned offset (%lx)"),
15512 (long) fixP->fx_offset);
15513 if (!fixP->fx_done)
15516 if (*valP + 0x100000 <= 0x1fffff)
15518 insn = read_insn (buf);
15519 insn |= (*valP >> 3) & 0x3ffff;
15520 write_insn (buf, insn);
15523 as_bad_where (fixP->fx_file, fixP->fx_line,
15524 _("PC-relative access out of range"));
15527 case BFD_RELOC_MIPS_19_PCREL_S2:
15528 if ((*valP & 0x3) != 0)
15529 as_bad_where (fixP->fx_file, fixP->fx_line,
15530 _("PC-relative access to misaligned address (%lx)"),
15532 if (!fixP->fx_done)
15535 if (*valP + 0x100000 <= 0x1fffff)
15537 insn = read_insn (buf);
15538 insn |= (*valP >> 2) & 0x7ffff;
15539 write_insn (buf, insn);
15542 as_bad_where (fixP->fx_file, fixP->fx_line,
15543 _("PC-relative access out of range"));
15546 case BFD_RELOC_16_PCREL_S2:
15547 fix_validate_branch (fixP, *valP);
15549 /* We need to save the bits in the instruction since fixup_segment()
15550 might be deleting the relocation entry (i.e., a branch within
15551 the current segment). */
15552 if (! fixP->fx_done)
15555 /* Update old instruction data. */
15556 insn = read_insn (buf);
15558 if (*valP + 0x20000 <= 0x3ffff)
15560 insn |= (*valP >> 2) & 0xffff;
15561 write_insn (buf, insn);
15563 else if (mips_pic == NO_PIC
15565 && fixP->fx_frag->fr_address >= text_section->vma
15566 && (fixP->fx_frag->fr_address
15567 < text_section->vma + bfd_get_section_size (text_section))
15568 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
15569 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
15570 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
15572 /* The branch offset is too large. If this is an
15573 unconditional branch, and we are not generating PIC code,
15574 we can convert it to an absolute jump instruction. */
15575 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
15576 insn = 0x0c000000; /* jal */
15578 insn = 0x08000000; /* j */
15579 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
15581 fixP->fx_addsy = section_symbol (text_section);
15582 *valP += md_pcrel_from (fixP);
15583 write_insn (buf, insn);
15587 /* If we got here, we have branch-relaxation disabled,
15588 and there's nothing we can do to fix this instruction
15589 without turning it into a longer sequence. */
15590 as_bad_where (fixP->fx_file, fixP->fx_line,
15591 _("branch out of range"));
15595 case BFD_RELOC_MIPS16_16_PCREL_S1:
15596 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15597 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15598 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15599 gas_assert (!fixP->fx_done);
15600 if (fix_bad_cross_mode_branch_p (fixP))
15601 as_bad_where (fixP->fx_file, fixP->fx_line,
15602 _("branch to a symbol in another ISA mode"));
15603 else if (fixP->fx_addsy
15604 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
15605 && !bfd_is_abs_section (S_GET_SEGMENT (fixP->fx_addsy))
15606 && (fixP->fx_offset & 0x1) != 0)
15607 as_bad_where (fixP->fx_file, fixP->fx_line,
15608 _("branch to misaligned address (0x%lx)"),
15609 (long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset));
15610 else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x1) != 0)
15611 as_bad_where (fixP->fx_file, fixP->fx_line,
15612 _("cannot encode misaligned addend "
15613 "in the relocatable field (0x%lx)"),
15614 (long) fixP->fx_offset);
15617 case BFD_RELOC_VTABLE_INHERIT:
15620 && !S_IS_DEFINED (fixP->fx_addsy)
15621 && !S_IS_WEAK (fixP->fx_addsy))
15622 S_SET_WEAK (fixP->fx_addsy);
15625 case BFD_RELOC_NONE:
15626 case BFD_RELOC_VTABLE_ENTRY:
15634 /* Remember value for tc_gen_reloc. */
15635 fixP->fx_addnumber = *valP;
15645 c = get_symbol_name (&name);
15646 p = (symbolS *) symbol_find_or_make (name);
15647 (void) restore_line_pointer (c);
15651 /* Align the current frag to a given power of two. If a particular
15652 fill byte should be used, FILL points to an integer that contains
15653 that byte, otherwise FILL is null.
15655 This function used to have the comment:
15657 The MIPS assembler also automatically adjusts any preceding label.
15659 The implementation therefore applied the adjustment to a maximum of
15660 one label. However, other label adjustments are applied to batches
15661 of labels, and adjusting just one caused problems when new labels
15662 were added for the sake of debugging or unwind information.
15663 We therefore adjust all preceding labels (given as LABELS) instead. */
15666 mips_align (int to, int *fill, struct insn_label_list *labels)
15668 mips_emit_delays ();
15669 mips_record_compressed_mode ();
15670 if (fill == NULL && subseg_text_p (now_seg))
15671 frag_align_code (to, 0);
15673 frag_align (to, fill ? *fill : 0, 0);
15674 record_alignment (now_seg, to);
15675 mips_move_labels (labels, FALSE);
15678 /* Align to a given power of two. .align 0 turns off the automatic
15679 alignment used by the data creating pseudo-ops. */
15682 s_align (int x ATTRIBUTE_UNUSED)
15684 int temp, fill_value, *fill_ptr;
15685 long max_alignment = 28;
15687 /* o Note that the assembler pulls down any immediately preceding label
15688 to the aligned address.
15689 o It's not documented but auto alignment is reinstated by
15690 a .align pseudo instruction.
15691 o Note also that after auto alignment is turned off the mips assembler
15692 issues an error on attempt to assemble an improperly aligned data item.
15695 temp = get_absolute_expression ();
15696 if (temp > max_alignment)
15697 as_bad (_("alignment too large, %d assumed"), temp = max_alignment);
15700 as_warn (_("alignment negative, 0 assumed"));
15703 if (*input_line_pointer == ',')
15705 ++input_line_pointer;
15706 fill_value = get_absolute_expression ();
15707 fill_ptr = &fill_value;
15713 segment_info_type *si = seg_info (now_seg);
15714 struct insn_label_list *l = si->label_list;
15715 /* Auto alignment should be switched on by next section change. */
15717 mips_align (temp, fill_ptr, l);
15724 demand_empty_rest_of_line ();
15728 s_change_sec (int sec)
15732 /* The ELF backend needs to know that we are changing sections, so
15733 that .previous works correctly. We could do something like check
15734 for an obj_section_change_hook macro, but that might be confusing
15735 as it would not be appropriate to use it in the section changing
15736 functions in read.c, since obj-elf.c intercepts those. FIXME:
15737 This should be cleaner, somehow. */
15738 obj_elf_section_change_hook ();
15740 mips_emit_delays ();
15751 subseg_set (bss_section, (subsegT) get_absolute_expression ());
15752 demand_empty_rest_of_line ();
15756 seg = subseg_new (RDATA_SECTION_NAME,
15757 (subsegT) get_absolute_expression ());
15758 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
15759 | SEC_READONLY | SEC_RELOC
15761 if (strncmp (TARGET_OS, "elf", 3) != 0)
15762 record_alignment (seg, 4);
15763 demand_empty_rest_of_line ();
15767 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
15768 bfd_set_section_flags (stdoutput, seg,
15769 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
15770 if (strncmp (TARGET_OS, "elf", 3) != 0)
15771 record_alignment (seg, 4);
15772 demand_empty_rest_of_line ();
15776 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
15777 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
15778 if (strncmp (TARGET_OS, "elf", 3) != 0)
15779 record_alignment (seg, 4);
15780 demand_empty_rest_of_line ();
15788 s_change_section (int ignore ATTRIBUTE_UNUSED)
15791 char *section_name;
15796 int section_entry_size;
15797 int section_alignment;
15799 saved_ilp = input_line_pointer;
15800 endc = get_symbol_name (§ion_name);
15801 c = (endc == '"' ? input_line_pointer[1] : endc);
15803 next_c = input_line_pointer [(endc == '"' ? 2 : 1)];
15805 /* Do we have .section Name<,"flags">? */
15806 if (c != ',' || (c == ',' && next_c == '"'))
15808 /* Just after name is now '\0'. */
15809 (void) restore_line_pointer (endc);
15810 input_line_pointer = saved_ilp;
15811 obj_elf_section (ignore);
15815 section_name = xstrdup (section_name);
15816 c = restore_line_pointer (endc);
15818 input_line_pointer++;
15820 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
15822 section_type = get_absolute_expression ();
15826 if (*input_line_pointer++ == ',')
15827 section_flag = get_absolute_expression ();
15831 if (*input_line_pointer++ == ',')
15832 section_entry_size = get_absolute_expression ();
15834 section_entry_size = 0;
15836 if (*input_line_pointer++ == ',')
15837 section_alignment = get_absolute_expression ();
15839 section_alignment = 0;
15841 /* FIXME: really ignore? */
15842 (void) section_alignment;
15844 /* When using the generic form of .section (as implemented by obj-elf.c),
15845 there's no way to set the section type to SHT_MIPS_DWARF. Users have
15846 traditionally had to fall back on the more common @progbits instead.
15848 There's nothing really harmful in this, since bfd will correct
15849 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
15850 means that, for backwards compatibility, the special_section entries
15851 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
15853 Even so, we shouldn't force users of the MIPS .section syntax to
15854 incorrectly label the sections as SHT_PROGBITS. The best compromise
15855 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
15856 generic type-checking code. */
15857 if (section_type == SHT_MIPS_DWARF)
15858 section_type = SHT_PROGBITS;
15860 obj_elf_change_section (section_name, section_type, section_flag,
15861 section_entry_size, 0, 0, 0);
15863 if (now_seg->name != section_name)
15864 free (section_name);
15868 mips_enable_auto_align (void)
15874 s_cons (int log_size)
15876 segment_info_type *si = seg_info (now_seg);
15877 struct insn_label_list *l = si->label_list;
15879 mips_emit_delays ();
15880 if (log_size > 0 && auto_align)
15881 mips_align (log_size, 0, l);
15882 cons (1 << log_size);
15883 mips_clear_insn_labels ();
15887 s_float_cons (int type)
15889 segment_info_type *si = seg_info (now_seg);
15890 struct insn_label_list *l = si->label_list;
15892 mips_emit_delays ();
15897 mips_align (3, 0, l);
15899 mips_align (2, 0, l);
15903 mips_clear_insn_labels ();
15906 /* Handle .globl. We need to override it because on Irix 5 you are
15909 where foo is an undefined symbol, to mean that foo should be
15910 considered to be the address of a function. */
15913 s_mips_globl (int x ATTRIBUTE_UNUSED)
15922 c = get_symbol_name (&name);
15923 symbolP = symbol_find_or_make (name);
15924 S_SET_EXTERNAL (symbolP);
15926 *input_line_pointer = c;
15927 SKIP_WHITESPACE_AFTER_NAME ();
15929 /* On Irix 5, every global symbol that is not explicitly labelled as
15930 being a function is apparently labelled as being an object. */
15933 if (!is_end_of_line[(unsigned char) *input_line_pointer]
15934 && (*input_line_pointer != ','))
15939 c = get_symbol_name (&secname);
15940 sec = bfd_get_section_by_name (stdoutput, secname);
15942 as_bad (_("%s: no such section"), secname);
15943 (void) restore_line_pointer (c);
15945 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
15946 flag = BSF_FUNCTION;
15949 symbol_get_bfdsym (symbolP)->flags |= flag;
15951 c = *input_line_pointer;
15954 input_line_pointer++;
15955 SKIP_WHITESPACE ();
15956 if (is_end_of_line[(unsigned char) *input_line_pointer])
15962 demand_empty_rest_of_line ();
15966 s_option (int x ATTRIBUTE_UNUSED)
15971 c = get_symbol_name (&opt);
15975 /* FIXME: What does this mean? */
15977 else if (strncmp (opt, "pic", 3) == 0 && ISDIGIT (opt[3]) && opt[4] == '\0')
15981 i = atoi (opt + 3);
15982 if (i != 0 && i != 2)
15983 as_bad (_(".option pic%d not supported"), i);
15984 else if (mips_pic == VXWORKS_PIC)
15985 as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i);
15990 mips_pic = SVR4_PIC;
15991 mips_abicalls = TRUE;
15994 if (mips_pic == SVR4_PIC)
15996 if (g_switch_seen && g_switch_value != 0)
15997 as_warn (_("-G may not be used with SVR4 PIC code"));
15998 g_switch_value = 0;
15999 bfd_set_gp_size (stdoutput, 0);
16003 as_warn (_("unrecognized option \"%s\""), opt);
16005 (void) restore_line_pointer (c);
16006 demand_empty_rest_of_line ();
16009 /* This structure is used to hold a stack of .set values. */
16011 struct mips_option_stack
16013 struct mips_option_stack *next;
16014 struct mips_set_options options;
16017 static struct mips_option_stack *mips_opts_stack;
16019 /* Return status for .set/.module option handling. */
16021 enum code_option_type
16023 /* Unrecognized option. */
16024 OPTION_TYPE_BAD = -1,
16026 /* Ordinary option. */
16027 OPTION_TYPE_NORMAL,
16029 /* ISA changing option. */
16033 /* Handle common .set/.module options. Return status indicating option
16036 static enum code_option_type
16037 parse_code_option (char * name)
16039 bfd_boolean isa_set = FALSE;
16040 const struct mips_ase *ase;
16042 if (strncmp (name, "at=", 3) == 0)
16044 char *s = name + 3;
16046 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
16047 as_bad (_("unrecognized register name `%s'"), s);
16049 else if (strcmp (name, "at") == 0)
16050 mips_opts.at = ATREG;
16051 else if (strcmp (name, "noat") == 0)
16052 mips_opts.at = ZERO;
16053 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
16054 mips_opts.nomove = 0;
16055 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
16056 mips_opts.nomove = 1;
16057 else if (strcmp (name, "bopt") == 0)
16058 mips_opts.nobopt = 0;
16059 else if (strcmp (name, "nobopt") == 0)
16060 mips_opts.nobopt = 1;
16061 else if (strcmp (name, "gp=32") == 0)
16063 else if (strcmp (name, "gp=64") == 0)
16065 else if (strcmp (name, "fp=32") == 0)
16067 else if (strcmp (name, "fp=xx") == 0)
16069 else if (strcmp (name, "fp=64") == 0)
16071 else if (strcmp (name, "softfloat") == 0)
16072 mips_opts.soft_float = 1;
16073 else if (strcmp (name, "hardfloat") == 0)
16074 mips_opts.soft_float = 0;
16075 else if (strcmp (name, "singlefloat") == 0)
16076 mips_opts.single_float = 1;
16077 else if (strcmp (name, "doublefloat") == 0)
16078 mips_opts.single_float = 0;
16079 else if (strcmp (name, "nooddspreg") == 0)
16080 mips_opts.oddspreg = 0;
16081 else if (strcmp (name, "oddspreg") == 0)
16082 mips_opts.oddspreg = 1;
16083 else if (strcmp (name, "mips16") == 0
16084 || strcmp (name, "MIPS-16") == 0)
16085 mips_opts.mips16 = 1;
16086 else if (strcmp (name, "nomips16") == 0
16087 || strcmp (name, "noMIPS-16") == 0)
16088 mips_opts.mips16 = 0;
16089 else if (strcmp (name, "micromips") == 0)
16090 mips_opts.micromips = 1;
16091 else if (strcmp (name, "nomicromips") == 0)
16092 mips_opts.micromips = 0;
16093 else if (name[0] == 'n'
16095 && (ase = mips_lookup_ase (name + 2)))
16096 mips_set_ase (ase, &mips_opts, FALSE);
16097 else if ((ase = mips_lookup_ase (name)))
16098 mips_set_ase (ase, &mips_opts, TRUE);
16099 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
16101 /* Permit the user to change the ISA and architecture on the fly.
16102 Needless to say, misuse can cause serious problems. */
16103 if (strncmp (name, "arch=", 5) == 0)
16105 const struct mips_cpu_info *p;
16107 p = mips_parse_cpu ("internal use", name + 5);
16109 as_bad (_("unknown architecture %s"), name + 5);
16112 mips_opts.arch = p->cpu;
16113 mips_opts.isa = p->isa;
16117 else if (strncmp (name, "mips", 4) == 0)
16119 const struct mips_cpu_info *p;
16121 p = mips_parse_cpu ("internal use", name);
16123 as_bad (_("unknown ISA level %s"), name + 4);
16126 mips_opts.arch = p->cpu;
16127 mips_opts.isa = p->isa;
16132 as_bad (_("unknown ISA or architecture %s"), name);
16134 else if (strcmp (name, "autoextend") == 0)
16135 mips_opts.noautoextend = 0;
16136 else if (strcmp (name, "noautoextend") == 0)
16137 mips_opts.noautoextend = 1;
16138 else if (strcmp (name, "insn32") == 0)
16139 mips_opts.insn32 = TRUE;
16140 else if (strcmp (name, "noinsn32") == 0)
16141 mips_opts.insn32 = FALSE;
16142 else if (strcmp (name, "sym32") == 0)
16143 mips_opts.sym32 = TRUE;
16144 else if (strcmp (name, "nosym32") == 0)
16145 mips_opts.sym32 = FALSE;
16147 return OPTION_TYPE_BAD;
16149 return isa_set ? OPTION_TYPE_ISA : OPTION_TYPE_NORMAL;
16152 /* Handle the .set pseudo-op. */
16155 s_mipsset (int x ATTRIBUTE_UNUSED)
16157 enum code_option_type type = OPTION_TYPE_NORMAL;
16158 char *name = input_line_pointer, ch;
16160 file_mips_check_options ();
16162 while (!is_end_of_line[(unsigned char) *input_line_pointer])
16163 ++input_line_pointer;
16164 ch = *input_line_pointer;
16165 *input_line_pointer = '\0';
16167 if (strchr (name, ','))
16169 /* Generic ".set" directive; use the generic handler. */
16170 *input_line_pointer = ch;
16171 input_line_pointer = name;
16176 if (strcmp (name, "reorder") == 0)
16178 if (mips_opts.noreorder)
16181 else if (strcmp (name, "noreorder") == 0)
16183 if (!mips_opts.noreorder)
16184 start_noreorder ();
16186 else if (strcmp (name, "macro") == 0)
16187 mips_opts.warn_about_macros = 0;
16188 else if (strcmp (name, "nomacro") == 0)
16190 if (mips_opts.noreorder == 0)
16191 as_bad (_("`noreorder' must be set before `nomacro'"));
16192 mips_opts.warn_about_macros = 1;
16194 else if (strcmp (name, "gp=default") == 0)
16195 mips_opts.gp = file_mips_opts.gp;
16196 else if (strcmp (name, "fp=default") == 0)
16197 mips_opts.fp = file_mips_opts.fp;
16198 else if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
16200 mips_opts.isa = file_mips_opts.isa;
16201 mips_opts.arch = file_mips_opts.arch;
16202 mips_opts.gp = file_mips_opts.gp;
16203 mips_opts.fp = file_mips_opts.fp;
16205 else if (strcmp (name, "push") == 0)
16207 struct mips_option_stack *s;
16209 s = XNEW (struct mips_option_stack);
16210 s->next = mips_opts_stack;
16211 s->options = mips_opts;
16212 mips_opts_stack = s;
16214 else if (strcmp (name, "pop") == 0)
16216 struct mips_option_stack *s;
16218 s = mips_opts_stack;
16220 as_bad (_(".set pop with no .set push"));
16223 /* If we're changing the reorder mode we need to handle
16224 delay slots correctly. */
16225 if (s->options.noreorder && ! mips_opts.noreorder)
16226 start_noreorder ();
16227 else if (! s->options.noreorder && mips_opts.noreorder)
16230 mips_opts = s->options;
16231 mips_opts_stack = s->next;
16237 type = parse_code_option (name);
16238 if (type == OPTION_TYPE_BAD)
16239 as_warn (_("tried to set unrecognized symbol: %s\n"), name);
16242 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
16243 registers based on what is supported by the arch/cpu. */
16244 if (type == OPTION_TYPE_ISA)
16246 switch (mips_opts.isa)
16251 /* MIPS I cannot support FPXX. */
16253 /* fall-through. */
16260 if (mips_opts.fp != 0)
16276 if (mips_opts.fp != 0)
16278 if (mips_opts.arch == CPU_R5900)
16285 as_bad (_("unknown ISA level %s"), name + 4);
16290 mips_check_options (&mips_opts, FALSE);
16292 mips_check_isa_supports_ases ();
16293 *input_line_pointer = ch;
16294 demand_empty_rest_of_line ();
16297 /* Handle the .module pseudo-op. */
16300 s_module (int ignore ATTRIBUTE_UNUSED)
16302 char *name = input_line_pointer, ch;
16304 while (!is_end_of_line[(unsigned char) *input_line_pointer])
16305 ++input_line_pointer;
16306 ch = *input_line_pointer;
16307 *input_line_pointer = '\0';
16309 if (!file_mips_opts_checked)
16311 if (parse_code_option (name) == OPTION_TYPE_BAD)
16312 as_bad (_(".module used with unrecognized symbol: %s\n"), name);
16314 /* Update module level settings from mips_opts. */
16315 file_mips_opts = mips_opts;
16318 as_bad (_(".module is not permitted after generating code"));
16320 *input_line_pointer = ch;
16321 demand_empty_rest_of_line ();
16324 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16325 .option pic2. It means to generate SVR4 PIC calls. */
16328 s_abicalls (int ignore ATTRIBUTE_UNUSED)
16330 mips_pic = SVR4_PIC;
16331 mips_abicalls = TRUE;
16333 if (g_switch_seen && g_switch_value != 0)
16334 as_warn (_("-G may not be used with SVR4 PIC code"));
16335 g_switch_value = 0;
16337 bfd_set_gp_size (stdoutput, 0);
16338 demand_empty_rest_of_line ();
16341 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16342 PIC code. It sets the $gp register for the function based on the
16343 function address, which is in the register named in the argument.
16344 This uses a relocation against _gp_disp, which is handled specially
16345 by the linker. The result is:
16346 lui $gp,%hi(_gp_disp)
16347 addiu $gp,$gp,%lo(_gp_disp)
16348 addu $gp,$gp,.cpload argument
16349 The .cpload argument is normally $25 == $t9.
16351 The -mno-shared option changes this to:
16352 lui $gp,%hi(__gnu_local_gp)
16353 addiu $gp,$gp,%lo(__gnu_local_gp)
16354 and the argument is ignored. This saves an instruction, but the
16355 resulting code is not position independent; it uses an absolute
16356 address for __gnu_local_gp. Thus code assembled with -mno-shared
16357 can go into an ordinary executable, but not into a shared library. */
16360 s_cpload (int ignore ATTRIBUTE_UNUSED)
16366 file_mips_check_options ();
16368 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16369 .cpload is ignored. */
16370 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16376 if (mips_opts.mips16)
16378 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16379 ignore_rest_of_line ();
16383 /* .cpload should be in a .set noreorder section. */
16384 if (mips_opts.noreorder == 0)
16385 as_warn (_(".cpload not in noreorder section"));
16387 reg = tc_get_register (0);
16389 /* If we need to produce a 64-bit address, we are better off using
16390 the default instruction sequence. */
16391 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
16393 ex.X_op = O_symbol;
16394 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
16396 ex.X_op_symbol = NULL;
16397 ex.X_add_number = 0;
16399 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16400 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16402 mips_mark_labels ();
16403 mips_assembling_insn = TRUE;
16406 macro_build_lui (&ex, mips_gp_register);
16407 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16408 mips_gp_register, BFD_RELOC_LO16);
16410 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
16411 mips_gp_register, reg);
16414 mips_assembling_insn = FALSE;
16415 demand_empty_rest_of_line ();
16418 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16419 .cpsetup $reg1, offset|$reg2, label
16421 If offset is given, this results in:
16422 sd $gp, offset($sp)
16423 lui $gp, %hi(%neg(%gp_rel(label)))
16424 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16425 daddu $gp, $gp, $reg1
16427 If $reg2 is given, this results in:
16429 lui $gp, %hi(%neg(%gp_rel(label)))
16430 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16431 daddu $gp, $gp, $reg1
16432 $reg1 is normally $25 == $t9.
16434 The -mno-shared option replaces the last three instructions with
16436 addiu $gp,$gp,%lo(_gp) */
16439 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
16441 expressionS ex_off;
16442 expressionS ex_sym;
16445 file_mips_check_options ();
16447 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16448 We also need NewABI support. */
16449 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16455 if (mips_opts.mips16)
16457 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16458 ignore_rest_of_line ();
16462 reg1 = tc_get_register (0);
16463 SKIP_WHITESPACE ();
16464 if (*input_line_pointer != ',')
16466 as_bad (_("missing argument separator ',' for .cpsetup"));
16470 ++input_line_pointer;
16471 SKIP_WHITESPACE ();
16472 if (*input_line_pointer == '$')
16474 mips_cpreturn_register = tc_get_register (0);
16475 mips_cpreturn_offset = -1;
16479 mips_cpreturn_offset = get_absolute_expression ();
16480 mips_cpreturn_register = -1;
16482 SKIP_WHITESPACE ();
16483 if (*input_line_pointer != ',')
16485 as_bad (_("missing argument separator ',' for .cpsetup"));
16489 ++input_line_pointer;
16490 SKIP_WHITESPACE ();
16491 expression (&ex_sym);
16493 mips_mark_labels ();
16494 mips_assembling_insn = TRUE;
16497 if (mips_cpreturn_register == -1)
16499 ex_off.X_op = O_constant;
16500 ex_off.X_add_symbol = NULL;
16501 ex_off.X_op_symbol = NULL;
16502 ex_off.X_add_number = mips_cpreturn_offset;
16504 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
16505 BFD_RELOC_LO16, SP);
16508 move_register (mips_cpreturn_register, mips_gp_register);
16510 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
16512 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
16513 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
16516 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
16517 mips_gp_register, -1, BFD_RELOC_GPREL16,
16518 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
16520 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
16521 mips_gp_register, reg1);
16527 ex.X_op = O_symbol;
16528 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
16529 ex.X_op_symbol = NULL;
16530 ex.X_add_number = 0;
16532 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16533 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16535 macro_build_lui (&ex, mips_gp_register);
16536 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16537 mips_gp_register, BFD_RELOC_LO16);
16542 mips_assembling_insn = FALSE;
16543 demand_empty_rest_of_line ();
16547 s_cplocal (int ignore ATTRIBUTE_UNUSED)
16549 file_mips_check_options ();
16551 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16552 .cplocal is ignored. */
16553 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16559 if (mips_opts.mips16)
16561 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16562 ignore_rest_of_line ();
16566 mips_gp_register = tc_get_register (0);
16567 demand_empty_rest_of_line ();
16570 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16571 offset from $sp. The offset is remembered, and after making a PIC
16572 call $gp is restored from that location. */
16575 s_cprestore (int ignore ATTRIBUTE_UNUSED)
16579 file_mips_check_options ();
16581 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16582 .cprestore is ignored. */
16583 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16589 if (mips_opts.mips16)
16591 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16592 ignore_rest_of_line ();
16596 mips_cprestore_offset = get_absolute_expression ();
16597 mips_cprestore_valid = 1;
16599 ex.X_op = O_constant;
16600 ex.X_add_symbol = NULL;
16601 ex.X_op_symbol = NULL;
16602 ex.X_add_number = mips_cprestore_offset;
16604 mips_mark_labels ();
16605 mips_assembling_insn = TRUE;
16608 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
16609 SP, HAVE_64BIT_ADDRESSES);
16612 mips_assembling_insn = FALSE;
16613 demand_empty_rest_of_line ();
16616 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16617 was given in the preceding .cpsetup, it results in:
16618 ld $gp, offset($sp)
16620 If a register $reg2 was given there, it results in:
16621 or $gp, $reg2, $0 */
16624 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
16628 file_mips_check_options ();
16630 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16631 We also need NewABI support. */
16632 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16638 if (mips_opts.mips16)
16640 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16641 ignore_rest_of_line ();
16645 mips_mark_labels ();
16646 mips_assembling_insn = TRUE;
16649 if (mips_cpreturn_register == -1)
16651 ex.X_op = O_constant;
16652 ex.X_add_symbol = NULL;
16653 ex.X_op_symbol = NULL;
16654 ex.X_add_number = mips_cpreturn_offset;
16656 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
16659 move_register (mips_gp_register, mips_cpreturn_register);
16663 mips_assembling_insn = FALSE;
16664 demand_empty_rest_of_line ();
16667 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16668 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16669 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16670 debug information or MIPS16 TLS. */
16673 s_tls_rel_directive (const size_t bytes, const char *dirstr,
16674 bfd_reloc_code_real_type rtype)
16681 if (ex.X_op != O_symbol)
16683 as_bad (_("unsupported use of %s"), dirstr);
16684 ignore_rest_of_line ();
16687 p = frag_more (bytes);
16688 md_number_to_chars (p, 0, bytes);
16689 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
16690 demand_empty_rest_of_line ();
16691 mips_clear_insn_labels ();
16694 /* Handle .dtprelword. */
16697 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
16699 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
16702 /* Handle .dtpreldword. */
16705 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
16707 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
16710 /* Handle .tprelword. */
16713 s_tprelword (int ignore ATTRIBUTE_UNUSED)
16715 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
16718 /* Handle .tpreldword. */
16721 s_tpreldword (int ignore ATTRIBUTE_UNUSED)
16723 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
16726 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16727 code. It sets the offset to use in gp_rel relocations. */
16730 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
16732 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16733 We also need NewABI support. */
16734 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16740 mips_gprel_offset = get_absolute_expression ();
16742 demand_empty_rest_of_line ();
16745 /* Handle the .gpword pseudo-op. This is used when generating PIC
16746 code. It generates a 32 bit GP relative reloc. */
16749 s_gpword (int ignore ATTRIBUTE_UNUSED)
16751 segment_info_type *si;
16752 struct insn_label_list *l;
16756 /* When not generating PIC code, this is treated as .word. */
16757 if (mips_pic != SVR4_PIC)
16763 si = seg_info (now_seg);
16764 l = si->label_list;
16765 mips_emit_delays ();
16767 mips_align (2, 0, l);
16770 mips_clear_insn_labels ();
16772 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16774 as_bad (_("unsupported use of .gpword"));
16775 ignore_rest_of_line ();
16779 md_number_to_chars (p, 0, 4);
16780 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16781 BFD_RELOC_GPREL32);
16783 demand_empty_rest_of_line ();
16787 s_gpdword (int ignore ATTRIBUTE_UNUSED)
16789 segment_info_type *si;
16790 struct insn_label_list *l;
16794 /* When not generating PIC code, this is treated as .dword. */
16795 if (mips_pic != SVR4_PIC)
16801 si = seg_info (now_seg);
16802 l = si->label_list;
16803 mips_emit_delays ();
16805 mips_align (3, 0, l);
16808 mips_clear_insn_labels ();
16810 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16812 as_bad (_("unsupported use of .gpdword"));
16813 ignore_rest_of_line ();
16817 md_number_to_chars (p, 0, 8);
16818 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16819 BFD_RELOC_GPREL32)->fx_tcbit = 1;
16821 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
16822 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
16823 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
16825 demand_empty_rest_of_line ();
16828 /* Handle the .ehword pseudo-op. This is used when generating unwinding
16829 tables. It generates a R_MIPS_EH reloc. */
16832 s_ehword (int ignore ATTRIBUTE_UNUSED)
16837 mips_emit_delays ();
16840 mips_clear_insn_labels ();
16842 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16844 as_bad (_("unsupported use of .ehword"));
16845 ignore_rest_of_line ();
16849 md_number_to_chars (p, 0, 4);
16850 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16851 BFD_RELOC_32_PCREL);
16853 demand_empty_rest_of_line ();
16856 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
16857 tables in SVR4 PIC code. */
16860 s_cpadd (int ignore ATTRIBUTE_UNUSED)
16864 file_mips_check_options ();
16866 /* This is ignored when not generating SVR4 PIC code. */
16867 if (mips_pic != SVR4_PIC)
16873 mips_mark_labels ();
16874 mips_assembling_insn = TRUE;
16876 /* Add $gp to the register named as an argument. */
16878 reg = tc_get_register (0);
16879 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
16882 mips_assembling_insn = FALSE;
16883 demand_empty_rest_of_line ();
16886 /* Handle the .insn pseudo-op. This marks instruction labels in
16887 mips16/micromips mode. This permits the linker to handle them specially,
16888 such as generating jalx instructions when needed. We also make
16889 them odd for the duration of the assembly, in order to generate the
16890 right sort of code. We will make them even in the adjust_symtab
16891 routine, while leaving them marked. This is convenient for the
16892 debugger and the disassembler. The linker knows to make them odd
16896 s_insn (int ignore ATTRIBUTE_UNUSED)
16898 file_mips_check_options ();
16899 file_ase_mips16 |= mips_opts.mips16;
16900 file_ase_micromips |= mips_opts.micromips;
16902 mips_mark_labels ();
16904 demand_empty_rest_of_line ();
16907 /* Handle the .nan pseudo-op. */
16910 s_nan (int ignore ATTRIBUTE_UNUSED)
16912 static const char str_legacy[] = "legacy";
16913 static const char str_2008[] = "2008";
16916 for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++);
16918 if (i == sizeof (str_2008) - 1
16919 && memcmp (input_line_pointer, str_2008, i) == 0)
16921 else if (i == sizeof (str_legacy) - 1
16922 && memcmp (input_line_pointer, str_legacy, i) == 0)
16924 if (ISA_HAS_LEGACY_NAN (file_mips_opts.isa))
16927 as_bad (_("`%s' does not support legacy NaN"),
16928 mips_cpu_info_from_isa (file_mips_opts.isa)->name);
16931 as_bad (_("bad .nan directive"));
16933 input_line_pointer += i;
16934 demand_empty_rest_of_line ();
16937 /* Handle a .stab[snd] directive. Ideally these directives would be
16938 implemented in a transparent way, so that removing them would not
16939 have any effect on the generated instructions. However, s_stab
16940 internally changes the section, so in practice we need to decide
16941 now whether the preceding label marks compressed code. We do not
16942 support changing the compression mode of a label after a .stab*
16943 directive, such as in:
16949 so the current mode wins. */
16952 s_mips_stab (int type)
16954 mips_mark_labels ();
16958 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
16961 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
16968 c = get_symbol_name (&name);
16969 symbolP = symbol_find_or_make (name);
16970 S_SET_WEAK (symbolP);
16971 *input_line_pointer = c;
16973 SKIP_WHITESPACE_AFTER_NAME ();
16975 if (! is_end_of_line[(unsigned char) *input_line_pointer])
16977 if (S_IS_DEFINED (symbolP))
16979 as_bad (_("ignoring attempt to redefine symbol %s"),
16980 S_GET_NAME (symbolP));
16981 ignore_rest_of_line ();
16985 if (*input_line_pointer == ',')
16987 ++input_line_pointer;
16988 SKIP_WHITESPACE ();
16992 if (exp.X_op != O_symbol)
16994 as_bad (_("bad .weakext directive"));
16995 ignore_rest_of_line ();
16998 symbol_set_value_expression (symbolP, &exp);
17001 demand_empty_rest_of_line ();
17004 /* Parse a register string into a number. Called from the ECOFF code
17005 to parse .frame. The argument is non-zero if this is the frame
17006 register, so that we can record it in mips_frame_reg. */
17009 tc_get_register (int frame)
17013 SKIP_WHITESPACE ();
17014 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
17018 mips_frame_reg = reg != 0 ? reg : SP;
17019 mips_frame_reg_valid = 1;
17020 mips_cprestore_valid = 0;
17026 md_section_align (asection *seg, valueT addr)
17028 int align = bfd_get_section_alignment (stdoutput, seg);
17030 /* We don't need to align ELF sections to the full alignment.
17031 However, Irix 5 may prefer that we align them at least to a 16
17032 byte boundary. We don't bother to align the sections if we
17033 are targeted for an embedded system. */
17034 if (strncmp (TARGET_OS, "elf", 3) == 0)
17039 return ((addr + (1 << align) - 1) & -(1 << align));
17042 /* Utility routine, called from above as well. If called while the
17043 input file is still being read, it's only an approximation. (For
17044 example, a symbol may later become defined which appeared to be
17045 undefined earlier.) */
17048 nopic_need_relax (symbolS *sym, int before_relaxing)
17053 if (g_switch_value > 0)
17055 const char *symname;
17058 /* Find out whether this symbol can be referenced off the $gp
17059 register. It can be if it is smaller than the -G size or if
17060 it is in the .sdata or .sbss section. Certain symbols can
17061 not be referenced off the $gp, although it appears as though
17063 symname = S_GET_NAME (sym);
17064 if (symname != (const char *) NULL
17065 && (strcmp (symname, "eprol") == 0
17066 || strcmp (symname, "etext") == 0
17067 || strcmp (symname, "_gp") == 0
17068 || strcmp (symname, "edata") == 0
17069 || strcmp (symname, "_fbss") == 0
17070 || strcmp (symname, "_fdata") == 0
17071 || strcmp (symname, "_ftext") == 0
17072 || strcmp (symname, "end") == 0
17073 || strcmp (symname, "_gp_disp") == 0))
17075 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
17077 #ifndef NO_ECOFF_DEBUGGING
17078 || (symbol_get_obj (sym)->ecoff_extern_size != 0
17079 && (symbol_get_obj (sym)->ecoff_extern_size
17080 <= g_switch_value))
17082 /* We must defer this decision until after the whole
17083 file has been read, since there might be a .extern
17084 after the first use of this symbol. */
17085 || (before_relaxing
17086 #ifndef NO_ECOFF_DEBUGGING
17087 && symbol_get_obj (sym)->ecoff_extern_size == 0
17089 && S_GET_VALUE (sym) == 0)
17090 || (S_GET_VALUE (sym) != 0
17091 && S_GET_VALUE (sym) <= g_switch_value)))
17095 const char *segname;
17097 segname = segment_name (S_GET_SEGMENT (sym));
17098 gas_assert (strcmp (segname, ".lit8") != 0
17099 && strcmp (segname, ".lit4") != 0);
17100 change = (strcmp (segname, ".sdata") != 0
17101 && strcmp (segname, ".sbss") != 0
17102 && strncmp (segname, ".sdata.", 7) != 0
17103 && strncmp (segname, ".sbss.", 6) != 0
17104 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
17105 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
17110 /* We are not optimizing for the $gp register. */
17115 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17118 pic_need_relax (symbolS *sym, asection *segtype)
17122 /* Handle the case of a symbol equated to another symbol. */
17123 while (symbol_equated_reloc_p (sym))
17127 /* It's possible to get a loop here in a badly written program. */
17128 n = symbol_get_value_expression (sym)->X_add_symbol;
17134 if (symbol_section_p (sym))
17137 symsec = S_GET_SEGMENT (sym);
17139 /* This must duplicate the test in adjust_reloc_syms. */
17140 return (!bfd_is_und_section (symsec)
17141 && !bfd_is_abs_section (symsec)
17142 && !bfd_is_com_section (symsec)
17143 && !s_is_linkonce (sym, segtype)
17144 /* A global or weak symbol is treated as external. */
17145 && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym)));
17149 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17150 extended opcode. SEC is the section the frag is in. */
17153 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
17156 const struct mips_int_operand *operand;
17161 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
17163 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17166 symsec = S_GET_SEGMENT (fragp->fr_symbol);
17167 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
17168 operand = mips16_immed_operand (type, FALSE);
17169 if (S_FORCE_RELOC (fragp->fr_symbol, TRUE)
17170 || (operand->root.type == OP_PCREL
17172 : !bfd_is_abs_section (symsec)))
17175 sym_frag = symbol_get_frag (fragp->fr_symbol);
17176 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17178 if (operand->root.type == OP_PCREL)
17180 const struct mips_pcrel_operand *pcrel_op;
17184 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
17187 pcrel_op = (const struct mips_pcrel_operand *) operand;
17189 /* If the relax_marker of the symbol fragment differs from the
17190 relax_marker of this fragment, we have not yet adjusted the
17191 symbol fragment fr_address. We want to add in STRETCH in
17192 order to get a better estimate of the address. This
17193 particularly matters because of the shift bits. */
17195 && sym_frag->relax_marker != fragp->relax_marker)
17199 /* Adjust stretch for any alignment frag. Note that if have
17200 been expanding the earlier code, the symbol may be
17201 defined in what appears to be an earlier frag. FIXME:
17202 This doesn't handle the fr_subtype field, which specifies
17203 a maximum number of bytes to skip when doing an
17205 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
17207 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
17210 stretch = - ((- stretch)
17211 & ~ ((1 << (int) f->fr_offset) - 1));
17213 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
17222 addr = fragp->fr_address + fragp->fr_fix;
17224 /* The base address rules are complicated. The base address of
17225 a branch is the following instruction. The base address of a
17226 PC relative load or add is the instruction itself, but if it
17227 is in a delay slot (in which case it can not be extended) use
17228 the address of the instruction whose delay slot it is in. */
17229 if (pcrel_op->include_isa_bit)
17233 /* If we are currently assuming that this frag should be
17234 extended, then, the current address is two bytes
17236 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17239 /* Ignore the low bit in the target, since it will be set
17240 for a text label. */
17243 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17245 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17248 val -= addr & -(1 << pcrel_op->align_log2);
17250 /* If any of the shifted bits are set, we must use an extended
17251 opcode. If the address depends on the size of this
17252 instruction, this can lead to a loop, so we arrange to always
17253 use an extended opcode. */
17254 if ((val & ((1 << operand->shift) - 1)) != 0)
17256 fragp->fr_subtype =
17257 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17261 /* If we are about to mark a frag as extended because the value
17262 is precisely the next value above maxtiny, then there is a
17263 chance of an infinite loop as in the following code:
17268 In this case when the la is extended, foo is 0x3fc bytes
17269 away, so the la can be shrunk, but then foo is 0x400 away, so
17270 the la must be extended. To avoid this loop, we mark the
17271 frag as extended if it was small, and is about to become
17272 extended with the next value above maxtiny. */
17273 maxtiny = mips_int_operand_max (operand);
17274 if (val == maxtiny + (1 << operand->shift)
17275 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17277 fragp->fr_subtype =
17278 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17283 return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val);
17286 /* Compute the length of a branch sequence, and adjust the
17287 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17288 worst-case length is computed, with UPDATE being used to indicate
17289 whether an unconditional (-1), branch-likely (+1) or regular (0)
17290 branch is to be computed. */
17292 relaxed_branch_length (fragS *fragp, asection *sec, int update)
17294 bfd_boolean toofar;
17298 && S_IS_DEFINED (fragp->fr_symbol)
17299 && !S_IS_WEAK (fragp->fr_symbol)
17300 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17305 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17307 addr = fragp->fr_address + fragp->fr_fix + 4;
17311 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
17314 /* If the symbol is not defined or it's in a different segment,
17315 we emit the long sequence. */
17318 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17320 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
17321 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
17322 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
17323 RELAX_BRANCH_LINK (fragp->fr_subtype),
17329 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
17332 if (mips_pic != NO_PIC)
17334 /* Additional space for PIC loading of target address. */
17336 if (mips_opts.isa == ISA_MIPS1)
17337 /* Additional space for $at-stabilizing nop. */
17341 /* If branch is conditional. */
17342 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
17349 /* Get a FRAG's branch instruction delay slot size, either from the
17350 short-delay-slot bit of a branch-and-link instruction if AL is TRUE,
17351 or SHORT_INSN_SIZE otherwise. */
17354 frag_branch_delay_slot_size (fragS *fragp, bfd_boolean al, int short_insn_size)
17356 char *buf = fragp->fr_literal + fragp->fr_fix;
17359 return (read_compressed_insn (buf, 4) & 0x02000000) ? 2 : 4;
17361 return short_insn_size;
17364 /* Compute the length of a branch sequence, and adjust the
17365 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17366 worst-case length is computed, with UPDATE being used to indicate
17367 whether an unconditional (-1), or regular (0) branch is to be
17371 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
17373 bfd_boolean insn32 = TRUE;
17374 bfd_boolean nods = TRUE;
17375 bfd_boolean al = TRUE;
17376 int short_insn_size;
17377 bfd_boolean toofar;
17382 insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype);
17383 nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype);
17384 al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
17386 short_insn_size = insn32 ? 4 : 2;
17389 && S_IS_DEFINED (fragp->fr_symbol)
17390 && !S_IS_WEAK (fragp->fr_symbol)
17391 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17396 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17397 /* Ignore the low bit in the target, since it will be set
17398 for a text label. */
17399 if ((val & 1) != 0)
17402 addr = fragp->fr_address + fragp->fr_fix + 4;
17406 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
17409 /* If the symbol is not defined or it's in a different segment,
17410 we emit the long sequence. */
17413 if (fragp && update
17414 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17415 fragp->fr_subtype = (toofar
17416 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
17417 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
17422 bfd_boolean compact_known = fragp != NULL;
17423 bfd_boolean compact = FALSE;
17424 bfd_boolean uncond;
17428 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17429 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
17432 uncond = update < 0;
17434 /* If label is out of range, we turn branch <br>:
17436 <br> label # 4 bytes
17443 # compact && (!PIC || insn32)
17446 if ((mips_pic == NO_PIC || insn32) && (!compact_known || compact))
17447 length += short_insn_size;
17449 /* If assembling PIC code, we further turn:
17455 lw/ld at, %got(label)(gp) # 4 bytes
17456 d/addiu at, %lo(label) # 4 bytes
17457 jr/c at # 2/4 bytes
17459 if (mips_pic != NO_PIC)
17460 length += 4 + short_insn_size;
17462 /* Add an extra nop if the jump has no compact form and we need
17463 to fill the delay slot. */
17464 if ((mips_pic == NO_PIC || al) && nods)
17466 ? frag_branch_delay_slot_size (fragp, al, short_insn_size)
17467 : short_insn_size);
17469 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17471 <brneg> 0f # 4 bytes
17472 nop # 2/4 bytes if !compact
17475 length += (compact_known && compact) ? 4 : 4 + short_insn_size;
17479 /* Add an extra nop to fill the delay slot. */
17480 gas_assert (fragp);
17481 length += frag_branch_delay_slot_size (fragp, al, short_insn_size);
17487 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17488 bit accordingly. */
17491 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
17493 bfd_boolean toofar;
17496 && S_IS_DEFINED (fragp->fr_symbol)
17497 && !S_IS_WEAK (fragp->fr_symbol)
17498 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17504 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17505 /* Ignore the low bit in the target, since it will be set
17506 for a text label. */
17507 if ((val & 1) != 0)
17510 /* Assume this is a 2-byte branch. */
17511 addr = fragp->fr_address + fragp->fr_fix + 2;
17513 /* We try to avoid the infinite loop by not adding 2 more bytes for
17518 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17520 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
17521 else if (type == 'E')
17522 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
17527 /* If the symbol is not defined or it's in a different segment,
17528 we emit a normal 32-bit branch. */
17531 if (fragp && update
17532 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17534 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
17535 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
17543 /* Estimate the size of a frag before relaxing. Unless this is the
17544 mips16, we are not really relaxing here, and the final size is
17545 encoded in the subtype information. For the mips16, we have to
17546 decide whether we are using an extended opcode or not. */
17549 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
17553 if (RELAX_BRANCH_P (fragp->fr_subtype))
17556 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
17558 return fragp->fr_var;
17561 if (RELAX_MIPS16_P (fragp->fr_subtype))
17562 /* We don't want to modify the EXTENDED bit here; it might get us
17563 into infinite loops. We change it only in mips_relax_frag(). */
17564 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
17566 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17570 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17571 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
17572 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17573 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
17574 fragp->fr_var = length;
17579 if (mips_pic == NO_PIC)
17580 change = nopic_need_relax (fragp->fr_symbol, 0);
17581 else if (mips_pic == SVR4_PIC)
17582 change = pic_need_relax (fragp->fr_symbol, segtype);
17583 else if (mips_pic == VXWORKS_PIC)
17584 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17591 fragp->fr_subtype |= RELAX_USE_SECOND;
17592 return -RELAX_FIRST (fragp->fr_subtype);
17595 return -RELAX_SECOND (fragp->fr_subtype);
17598 /* This is called to see whether a reloc against a defined symbol
17599 should be converted into a reloc against a section. */
17602 mips_fix_adjustable (fixS *fixp)
17604 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
17605 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17608 if (fixp->fx_addsy == NULL)
17611 /* Allow relocs used for EH tables. */
17612 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
17615 /* If symbol SYM is in a mergeable section, relocations of the form
17616 SYM + 0 can usually be made section-relative. The mergeable data
17617 is then identified by the section offset rather than by the symbol.
17619 However, if we're generating REL LO16 relocations, the offset is split
17620 between the LO16 and parterning high part relocation. The linker will
17621 need to recalculate the complete offset in order to correctly identify
17624 The linker has traditionally not looked for the parterning high part
17625 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17626 placed anywhere. Rather than break backwards compatibility by changing
17627 this, it seems better not to force the issue, and instead keep the
17628 original symbol. This will work with either linker behavior. */
17629 if ((lo16_reloc_p (fixp->fx_r_type)
17630 || reloc_needs_lo_p (fixp->fx_r_type))
17631 && HAVE_IN_PLACE_ADDENDS
17632 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
17635 /* There is no place to store an in-place offset for JALR relocations. */
17636 if (jalr_reloc_p (fixp->fx_r_type) && HAVE_IN_PLACE_ADDENDS)
17639 /* Likewise an in-range offset of limited PC-relative relocations may
17640 overflow the in-place relocatable field if recalculated against the
17641 start address of the symbol's containing section.
17643 Also, PC relative relocations for MIPS R6 need to be symbol rather than
17644 section relative to allow linker relaxations to be performed later on. */
17645 if (limited_pcrel_reloc_p (fixp->fx_r_type)
17646 && (HAVE_IN_PLACE_ADDENDS || ISA_IS_R6 (file_mips_opts.isa)))
17649 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17650 to a floating-point stub. The same is true for non-R_MIPS16_26
17651 relocations against MIPS16 functions; in this case, the stub becomes
17652 the function's canonical address.
17654 Floating-point stubs are stored in unique .mips16.call.* or
17655 .mips16.fn.* sections. If a stub T for function F is in section S,
17656 the first relocation in section S must be against F; this is how the
17657 linker determines the target function. All relocations that might
17658 resolve to T must also be against F. We therefore have the following
17659 restrictions, which are given in an intentionally-redundant way:
17661 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17664 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17665 if that stub might be used.
17667 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17670 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17671 that stub might be used.
17673 There is a further restriction:
17675 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17676 R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2,
17677 R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1,
17678 R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1)
17679 against MIPS16 or microMIPS symbols because we need to keep the
17680 MIPS16 or microMIPS symbol for the purpose of mode mismatch
17681 detection and JAL or BAL to JALX instruction conversion in the
17684 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17685 against a MIPS16 symbol. We deal with (5) by additionally leaving
17686 alone any jump and branch relocations against a microMIPS symbol.
17688 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17689 relocation against some symbol R, no relocation against R may be
17690 reduced. (Note that this deals with (2) as well as (1) because
17691 relocations against global symbols will never be reduced on ELF
17692 targets.) This approach is a little simpler than trying to detect
17693 stub sections, and gives the "all or nothing" per-symbol consistency
17694 that we have for MIPS16 symbols. */
17695 if (fixp->fx_subsy == NULL
17696 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
17697 || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
17698 && (jmp_reloc_p (fixp->fx_r_type)
17699 || b_reloc_p (fixp->fx_r_type)))
17700 || *symbol_get_tc (fixp->fx_addsy)))
17706 /* Translate internal representation of relocation info to BFD target
17710 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
17712 static arelent *retval[4];
17714 bfd_reloc_code_real_type code;
17716 memset (retval, 0, sizeof(retval));
17717 reloc = retval[0] = XCNEW (arelent);
17718 reloc->sym_ptr_ptr = XNEW (asymbol *);
17719 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
17720 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
17722 if (fixp->fx_pcrel)
17724 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
17725 || fixp->fx_r_type == BFD_RELOC_MIPS16_16_PCREL_S1
17726 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
17727 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
17728 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
17729 || fixp->fx_r_type == BFD_RELOC_32_PCREL
17730 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
17731 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2
17732 || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3
17733 || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2
17734 || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL
17735 || fixp->fx_r_type == BFD_RELOC_LO16_PCREL);
17737 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17738 Relocations want only the symbol offset. */
17739 switch (fixp->fx_r_type)
17741 case BFD_RELOC_MIPS_18_PCREL_S3:
17742 reloc->addend = fixp->fx_addnumber + (reloc->address & ~7);
17745 reloc->addend = fixp->fx_addnumber + reloc->address;
17749 else if (HAVE_IN_PLACE_ADDENDS
17750 && fixp->fx_r_type == BFD_RELOC_MICROMIPS_JMP
17751 && (read_compressed_insn (fixp->fx_frag->fr_literal
17752 + fixp->fx_where, 4) >> 26) == 0x3c)
17754 /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place
17755 addend accordingly. */
17756 reloc->addend = fixp->fx_addnumber >> 1;
17759 reloc->addend = fixp->fx_addnumber;
17761 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17762 entry to be used in the relocation's section offset. */
17763 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17765 reloc->address = reloc->addend;
17769 code = fixp->fx_r_type;
17771 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
17772 if (reloc->howto == NULL)
17774 as_bad_where (fixp->fx_file, fixp->fx_line,
17775 _("cannot represent %s relocation in this object file"
17777 bfd_get_reloc_code_name (code));
17784 /* Relax a machine dependent frag. This returns the amount by which
17785 the current size of the frag should change. */
17788 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
17790 if (RELAX_BRANCH_P (fragp->fr_subtype))
17792 offsetT old_var = fragp->fr_var;
17794 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
17796 return fragp->fr_var - old_var;
17799 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17801 offsetT old_var = fragp->fr_var;
17802 offsetT new_var = 4;
17804 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17805 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
17806 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17807 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
17808 fragp->fr_var = new_var;
17810 return new_var - old_var;
17813 if (! RELAX_MIPS16_P (fragp->fr_subtype))
17816 if (mips16_extended_frag (fragp, sec, stretch))
17818 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17820 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
17825 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17827 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
17834 /* Convert a machine dependent frag. */
17837 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
17839 if (RELAX_BRANCH_P (fragp->fr_subtype))
17842 unsigned long insn;
17846 buf = fragp->fr_literal + fragp->fr_fix;
17847 insn = read_insn (buf);
17849 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17851 /* We generate a fixup instead of applying it right now
17852 because, if there are linker relaxations, we're going to
17853 need the relocations. */
17854 exp.X_op = O_symbol;
17855 exp.X_add_symbol = fragp->fr_symbol;
17856 exp.X_add_number = fragp->fr_offset;
17858 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
17859 BFD_RELOC_16_PCREL_S2);
17860 fixp->fx_file = fragp->fr_file;
17861 fixp->fx_line = fragp->fr_line;
17863 buf = write_insn (buf, insn);
17869 as_warn_where (fragp->fr_file, fragp->fr_line,
17870 _("relaxed out-of-range branch into a jump"));
17872 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
17875 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17877 /* Reverse the branch. */
17878 switch ((insn >> 28) & 0xf)
17881 if ((insn & 0xff000000) == 0x47000000
17882 || (insn & 0xff600000) == 0x45600000)
17884 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
17885 reversed by tweaking bit 23. */
17886 insn ^= 0x00800000;
17890 /* bc[0-3][tf]l? instructions can have the condition
17891 reversed by tweaking a single TF bit, and their
17892 opcodes all have 0x4???????. */
17893 gas_assert ((insn & 0xf3e00000) == 0x41000000);
17894 insn ^= 0x00010000;
17899 /* bltz 0x04000000 bgez 0x04010000
17900 bltzal 0x04100000 bgezal 0x04110000 */
17901 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
17902 insn ^= 0x00010000;
17906 /* beq 0x10000000 bne 0x14000000
17907 blez 0x18000000 bgtz 0x1c000000 */
17908 insn ^= 0x04000000;
17916 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
17918 /* Clear the and-link bit. */
17919 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
17921 /* bltzal 0x04100000 bgezal 0x04110000
17922 bltzall 0x04120000 bgezall 0x04130000 */
17923 insn &= ~0x00100000;
17926 /* Branch over the branch (if the branch was likely) or the
17927 full jump (not likely case). Compute the offset from the
17928 current instruction to branch to. */
17929 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17933 /* How many bytes in instructions we've already emitted? */
17934 i = buf - fragp->fr_literal - fragp->fr_fix;
17935 /* How many bytes in instructions from here to the end? */
17936 i = fragp->fr_var - i;
17938 /* Convert to instruction count. */
17940 /* Branch counts from the next instruction. */
17943 /* Branch over the jump. */
17944 buf = write_insn (buf, insn);
17947 buf = write_insn (buf, 0);
17949 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17951 /* beql $0, $0, 2f */
17953 /* Compute the PC offset from the current instruction to
17954 the end of the variable frag. */
17955 /* How many bytes in instructions we've already emitted? */
17956 i = buf - fragp->fr_literal - fragp->fr_fix;
17957 /* How many bytes in instructions from here to the end? */
17958 i = fragp->fr_var - i;
17959 /* Convert to instruction count. */
17961 /* Don't decrement i, because we want to branch over the
17965 buf = write_insn (buf, insn);
17966 buf = write_insn (buf, 0);
17970 if (mips_pic == NO_PIC)
17973 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
17974 ? 0x0c000000 : 0x08000000);
17975 exp.X_op = O_symbol;
17976 exp.X_add_symbol = fragp->fr_symbol;
17977 exp.X_add_number = fragp->fr_offset;
17979 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
17980 FALSE, BFD_RELOC_MIPS_JMP);
17981 fixp->fx_file = fragp->fr_file;
17982 fixp->fx_line = fragp->fr_line;
17984 buf = write_insn (buf, insn);
17988 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
17990 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
17991 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
17992 insn |= at << OP_SH_RT;
17993 exp.X_op = O_symbol;
17994 exp.X_add_symbol = fragp->fr_symbol;
17995 exp.X_add_number = fragp->fr_offset;
17997 if (fragp->fr_offset)
17999 exp.X_add_symbol = make_expr_symbol (&exp);
18000 exp.X_add_number = 0;
18003 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18004 FALSE, BFD_RELOC_MIPS_GOT16);
18005 fixp->fx_file = fragp->fr_file;
18006 fixp->fx_line = fragp->fr_line;
18008 buf = write_insn (buf, insn);
18010 if (mips_opts.isa == ISA_MIPS1)
18012 buf = write_insn (buf, 0);
18014 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18015 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
18016 insn |= at << OP_SH_RS | at << OP_SH_RT;
18018 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18019 FALSE, BFD_RELOC_LO16);
18020 fixp->fx_file = fragp->fr_file;
18021 fixp->fx_line = fragp->fr_line;
18023 buf = write_insn (buf, insn);
18026 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
18030 insn |= at << OP_SH_RS;
18032 buf = write_insn (buf, insn);
18036 fragp->fr_fix += fragp->fr_var;
18037 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18041 /* Relax microMIPS branches. */
18042 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
18044 char *buf = fragp->fr_literal + fragp->fr_fix;
18045 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
18046 bfd_boolean insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype);
18047 bfd_boolean nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype);
18048 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
18049 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
18050 bfd_boolean short_ds;
18051 unsigned long insn;
18055 exp.X_op = O_symbol;
18056 exp.X_add_symbol = fragp->fr_symbol;
18057 exp.X_add_number = fragp->fr_offset;
18059 fragp->fr_fix += fragp->fr_var;
18061 /* Handle 16-bit branches that fit or are forced to fit. */
18062 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
18064 /* We generate a fixup instead of applying it right now,
18065 because if there is linker relaxation, we're going to
18066 need the relocations. */
18068 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
18069 BFD_RELOC_MICROMIPS_10_PCREL_S1);
18070 else if (type == 'E')
18071 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
18072 BFD_RELOC_MICROMIPS_7_PCREL_S1);
18076 fixp->fx_file = fragp->fr_file;
18077 fixp->fx_line = fragp->fr_line;
18079 /* These relocations can have an addend that won't fit in
18081 fixp->fx_no_overflow = 1;
18086 /* Handle 32-bit branches that fit or are forced to fit. */
18087 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18088 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18090 /* We generate a fixup instead of applying it right now,
18091 because if there is linker relaxation, we're going to
18092 need the relocations. */
18093 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
18094 BFD_RELOC_MICROMIPS_16_PCREL_S1);
18095 fixp->fx_file = fragp->fr_file;
18096 fixp->fx_line = fragp->fr_line;
18100 insn = read_compressed_insn (buf, 4);
18105 /* Check the short-delay-slot bit. */
18106 if (!al || (insn & 0x02000000) != 0)
18107 buf = write_compressed_insn (buf, 0x0c00, 2);
18109 buf = write_compressed_insn (buf, 0x00000000, 4);
18112 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18117 /* Relax 16-bit branches to 32-bit branches. */
18120 insn = read_compressed_insn (buf, 2);
18122 if ((insn & 0xfc00) == 0xcc00) /* b16 */
18123 insn = 0x94000000; /* beq */
18124 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18126 unsigned long regno;
18128 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
18129 regno = micromips_to_32_reg_d_map [regno];
18130 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
18131 insn |= regno << MICROMIPSOP_SH_RS;
18136 /* Nothing else to do, just write it out. */
18137 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18138 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18140 buf = write_compressed_insn (buf, insn, 4);
18142 buf = write_compressed_insn (buf, 0x0c00, 2);
18143 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18148 insn = read_compressed_insn (buf, 4);
18150 /* Relax 32-bit branches to a sequence of instructions. */
18151 as_warn_where (fragp->fr_file, fragp->fr_line,
18152 _("relaxed out-of-range branch into a jump"));
18154 /* Set the short-delay-slot bit. */
18155 short_ds = !al || (insn & 0x02000000) != 0;
18157 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
18161 /* Reverse the branch. */
18162 if ((insn & 0xfc000000) == 0x94000000 /* beq */
18163 || (insn & 0xfc000000) == 0xb4000000) /* bne */
18164 insn ^= 0x20000000;
18165 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
18166 || (insn & 0xffe00000) == 0x40400000 /* bgez */
18167 || (insn & 0xffe00000) == 0x40800000 /* blez */
18168 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
18169 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
18170 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
18171 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
18172 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
18173 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
18174 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
18175 insn ^= 0x00400000;
18176 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
18177 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
18178 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
18179 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
18180 insn ^= 0x00200000;
18181 else if ((insn & 0xff000000) == 0x83000000 /* BZ.df
18183 || (insn & 0xff600000) == 0x81600000) /* BZ.V
18185 insn ^= 0x00800000;
18191 /* Clear the and-link and short-delay-slot bits. */
18192 gas_assert ((insn & 0xfda00000) == 0x40200000);
18194 /* bltzal 0x40200000 bgezal 0x40600000 */
18195 /* bltzals 0x42200000 bgezals 0x42600000 */
18196 insn &= ~0x02200000;
18199 /* Make a label at the end for use with the branch. */
18200 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
18201 micromips_label_inc ();
18202 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
18205 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE,
18206 BFD_RELOC_MICROMIPS_16_PCREL_S1);
18207 fixp->fx_file = fragp->fr_file;
18208 fixp->fx_line = fragp->fr_line;
18210 /* Branch over the jump. */
18211 buf = write_compressed_insn (buf, insn, 4);
18217 buf = write_compressed_insn (buf, 0x00000000, 4);
18219 buf = write_compressed_insn (buf, 0x0c00, 2);
18223 if (mips_pic == NO_PIC)
18225 unsigned long jal = (short_ds || nods
18226 ? 0x74000000 : 0xf4000000); /* jal/s */
18228 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18229 insn = al ? jal : 0xd4000000;
18231 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18232 BFD_RELOC_MICROMIPS_JMP);
18233 fixp->fx_file = fragp->fr_file;
18234 fixp->fx_line = fragp->fr_line;
18236 buf = write_compressed_insn (buf, insn, 4);
18238 if (compact || nods)
18242 buf = write_compressed_insn (buf, 0x00000000, 4);
18244 buf = write_compressed_insn (buf, 0x0c00, 2);
18249 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
18251 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18252 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
18253 insn |= at << MICROMIPSOP_SH_RT;
18255 if (exp.X_add_number)
18257 exp.X_add_symbol = make_expr_symbol (&exp);
18258 exp.X_add_number = 0;
18261 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18262 BFD_RELOC_MICROMIPS_GOT16);
18263 fixp->fx_file = fragp->fr_file;
18264 fixp->fx_line = fragp->fr_line;
18266 buf = write_compressed_insn (buf, insn, 4);
18268 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18269 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
18270 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
18272 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18273 BFD_RELOC_MICROMIPS_LO16);
18274 fixp->fx_file = fragp->fr_file;
18275 fixp->fx_line = fragp->fr_line;
18277 buf = write_compressed_insn (buf, insn, 4);
18282 insn = 0x00000f3c | (al ? RA : ZERO) << MICROMIPSOP_SH_RT;
18283 insn |= at << MICROMIPSOP_SH_RS;
18285 buf = write_compressed_insn (buf, insn, 4);
18287 if (compact || nods)
18289 buf = write_compressed_insn (buf, 0x00000000, 4);
18293 /* jr/jrc/jalr/jalrs $at */
18294 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
18295 unsigned long jr = compact || nods ? 0x45a0 : 0x4580; /* jr/c */
18297 insn = al ? jalr : jr;
18298 insn |= at << MICROMIPSOP_SH_MJ;
18300 buf = write_compressed_insn (buf, insn, 2);
18305 buf = write_compressed_insn (buf, 0x0c00, 2);
18307 buf = write_compressed_insn (buf, 0x00000000, 4);
18312 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18316 if (RELAX_MIPS16_P (fragp->fr_subtype))
18319 const struct mips_int_operand *operand;
18322 unsigned int user_length, length;
18323 bfd_boolean need_reloc;
18324 unsigned long insn;
18328 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
18329 operand = mips16_immed_operand (type, FALSE);
18331 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
18332 val = resolve_symbol_value (fragp->fr_symbol) + fragp->fr_offset;
18334 symsec = S_GET_SEGMENT (fragp->fr_symbol);
18335 need_reloc = (S_FORCE_RELOC (fragp->fr_symbol, TRUE)
18336 || (operand->root.type == OP_PCREL
18338 : !bfd_is_abs_section (symsec)));
18340 if (operand->root.type == OP_PCREL)
18342 const struct mips_pcrel_operand *pcrel_op;
18345 pcrel_op = (const struct mips_pcrel_operand *) operand;
18346 addr = fragp->fr_address + fragp->fr_fix;
18348 /* The rules for the base address of a PC relative reloc are
18349 complicated; see mips16_extended_frag. */
18350 if (pcrel_op->include_isa_bit)
18354 if (!ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp->fr_symbol)))
18355 as_bad_where (fragp->fr_file, fragp->fr_line,
18356 _("branch to a symbol in another ISA mode"));
18357 else if ((fragp->fr_offset & 0x1) != 0)
18358 as_bad_where (fragp->fr_file, fragp->fr_line,
18359 _("branch to misaligned address (0x%lx)"),
18365 /* Ignore the low bit in the target, since it will be
18366 set for a text label. */
18369 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
18371 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
18374 addr &= -(1 << pcrel_op->align_log2);
18377 /* Make sure the section winds up with the alignment we have
18379 if (operand->shift > 0)
18380 record_alignment (asec, operand->shift);
18384 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
18385 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
18386 as_warn_where (fragp->fr_file, fragp->fr_line,
18387 _("extended instruction in delay slot"));
18389 buf = fragp->fr_literal + fragp->fr_fix;
18391 insn = read_compressed_insn (buf, 2);
18393 insn |= MIPS16_EXTEND;
18395 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
18397 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
18404 bfd_reloc_code_real_type reloc = BFD_RELOC_NONE;
18412 reloc = BFD_RELOC_MIPS16_16_PCREL_S1;
18415 as_bad_where (fragp->fr_file, fragp->fr_line,
18416 _("unsupported relocation"));
18419 if (reloc == BFD_RELOC_NONE)
18423 exp.X_op = O_symbol;
18424 exp.X_add_symbol = fragp->fr_symbol;
18425 exp.X_add_number = fragp->fr_offset;
18427 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp,
18430 fixp->fx_file = fragp->fr_file;
18431 fixp->fx_line = fragp->fr_line;
18433 /* These relocations can have an addend that won't fit
18435 fixp->fx_no_overflow = 1;
18438 as_bad_where (fragp->fr_file, fragp->fr_line,
18439 _("invalid unextended operand value"));
18442 mips16_immed (fragp->fr_file, fragp->fr_line, type,
18443 BFD_RELOC_UNUSED, val, user_length, &insn);
18445 length = (ext ? 4 : 2);
18446 gas_assert (mips16_opcode_length (insn) == length);
18447 write_compressed_insn (buf, insn, length);
18448 fragp->fr_fix += length;
18452 relax_substateT subtype = fragp->fr_subtype;
18453 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
18454 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
18458 first = RELAX_FIRST (subtype);
18459 second = RELAX_SECOND (subtype);
18460 fixp = (fixS *) fragp->fr_opcode;
18462 /* If the delay slot chosen does not match the size of the instruction,
18463 then emit a warning. */
18464 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
18465 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
18470 s = subtype & (RELAX_DELAY_SLOT_16BIT
18471 | RELAX_DELAY_SLOT_SIZE_FIRST
18472 | RELAX_DELAY_SLOT_SIZE_SECOND);
18473 msg = macro_warning (s);
18475 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18479 /* Possibly emit a warning if we've chosen the longer option. */
18480 if (use_second == second_longer)
18486 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
18487 msg = macro_warning (s);
18489 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18493 /* Go through all the fixups for the first sequence. Disable them
18494 (by marking them as done) if we're going to use the second
18495 sequence instead. */
18497 && fixp->fx_frag == fragp
18498 && fixp->fx_where < fragp->fr_fix - second)
18500 if (subtype & RELAX_USE_SECOND)
18502 fixp = fixp->fx_next;
18505 /* Go through the fixups for the second sequence. Disable them if
18506 we're going to use the first sequence, otherwise adjust their
18507 addresses to account for the relaxation. */
18508 while (fixp && fixp->fx_frag == fragp)
18510 if (subtype & RELAX_USE_SECOND)
18511 fixp->fx_where -= first;
18514 fixp = fixp->fx_next;
18517 /* Now modify the frag contents. */
18518 if (subtype & RELAX_USE_SECOND)
18522 start = fragp->fr_literal + fragp->fr_fix - first - second;
18523 memmove (start, start + first, second);
18524 fragp->fr_fix -= first;
18527 fragp->fr_fix -= second;
18531 /* This function is called after the relocs have been generated.
18532 We've been storing mips16 text labels as odd. Here we convert them
18533 back to even for the convenience of the debugger. */
18536 mips_frob_file_after_relocs (void)
18539 unsigned int count, i;
18541 syms = bfd_get_outsymbols (stdoutput);
18542 count = bfd_get_symcount (stdoutput);
18543 for (i = 0; i < count; i++, syms++)
18544 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
18545 && ((*syms)->value & 1) != 0)
18547 (*syms)->value &= ~1;
18548 /* If the symbol has an odd size, it was probably computed
18549 incorrectly, so adjust that as well. */
18550 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
18551 ++elf_symbol (*syms)->internal_elf_sym.st_size;
18555 /* This function is called whenever a label is defined, including fake
18556 labels instantiated off the dot special symbol. It is used when
18557 handling branch delays; if a branch has a label, we assume we cannot
18558 move it. This also bumps the value of the symbol by 1 in compressed
18562 mips_record_label (symbolS *sym)
18564 segment_info_type *si = seg_info (now_seg);
18565 struct insn_label_list *l;
18567 if (free_insn_labels == NULL)
18568 l = XNEW (struct insn_label_list);
18571 l = free_insn_labels;
18572 free_insn_labels = l->next;
18576 l->next = si->label_list;
18577 si->label_list = l;
18580 /* This function is called as tc_frob_label() whenever a label is defined
18581 and adds a DWARF-2 record we only want for true labels. */
18584 mips_define_label (symbolS *sym)
18586 mips_record_label (sym);
18587 dwarf2_emit_label (sym);
18590 /* This function is called by tc_new_dot_label whenever a new dot symbol
18594 mips_add_dot_label (symbolS *sym)
18596 mips_record_label (sym);
18597 if (mips_assembling_insn && HAVE_CODE_COMPRESSION)
18598 mips_compressed_mark_label (sym);
18601 /* Converting ASE flags from internal to .MIPS.abiflags values. */
18602 static unsigned int
18603 mips_convert_ase_flags (int ase)
18605 unsigned int ext_ases = 0;
18608 ext_ases |= AFL_ASE_DSP;
18609 if (ase & ASE_DSPR2)
18610 ext_ases |= AFL_ASE_DSPR2;
18611 if (ase & ASE_DSPR3)
18612 ext_ases |= AFL_ASE_DSPR3;
18614 ext_ases |= AFL_ASE_EVA;
18616 ext_ases |= AFL_ASE_MCU;
18617 if (ase & ASE_MDMX)
18618 ext_ases |= AFL_ASE_MDMX;
18619 if (ase & ASE_MIPS3D)
18620 ext_ases |= AFL_ASE_MIPS3D;
18622 ext_ases |= AFL_ASE_MT;
18623 if (ase & ASE_SMARTMIPS)
18624 ext_ases |= AFL_ASE_SMARTMIPS;
18625 if (ase & ASE_VIRT)
18626 ext_ases |= AFL_ASE_VIRT;
18628 ext_ases |= AFL_ASE_MSA;
18630 ext_ases |= AFL_ASE_XPA;
18634 /* Some special processing for a MIPS ELF file. */
18637 mips_elf_final_processing (void)
18640 Elf_Internal_ABIFlags_v0 flags;
18644 switch (file_mips_opts.isa)
18647 flags.isa_level = 1;
18650 flags.isa_level = 2;
18653 flags.isa_level = 3;
18656 flags.isa_level = 4;
18659 flags.isa_level = 5;
18662 flags.isa_level = 32;
18666 flags.isa_level = 32;
18670 flags.isa_level = 32;
18674 flags.isa_level = 32;
18678 flags.isa_level = 32;
18682 flags.isa_level = 64;
18686 flags.isa_level = 64;
18690 flags.isa_level = 64;
18694 flags.isa_level = 64;
18698 flags.isa_level = 64;
18703 flags.gpr_size = file_mips_opts.gp == 32 ? AFL_REG_32 : AFL_REG_64;
18704 flags.cpr1_size = file_mips_opts.soft_float ? AFL_REG_NONE
18705 : (file_mips_opts.ase & ASE_MSA) ? AFL_REG_128
18706 : (file_mips_opts.fp == 64) ? AFL_REG_64
18708 flags.cpr2_size = AFL_REG_NONE;
18709 flags.fp_abi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
18710 Tag_GNU_MIPS_ABI_FP);
18711 flags.isa_ext = bfd_mips_isa_ext (stdoutput);
18712 flags.ases = mips_convert_ase_flags (file_mips_opts.ase);
18713 if (file_ase_mips16)
18714 flags.ases |= AFL_ASE_MIPS16;
18715 if (file_ase_micromips)
18716 flags.ases |= AFL_ASE_MICROMIPS;
18718 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts.isa, file_mips_opts.arch)
18719 || file_mips_opts.fp == 64)
18720 && file_mips_opts.oddspreg)
18721 flags.flags1 |= AFL_FLAGS1_ODDSPREG;
18724 bfd_mips_elf_swap_abiflags_v0_out (stdoutput, &flags,
18725 ((Elf_External_ABIFlags_v0 *)
18728 /* Write out the register information. */
18729 if (mips_abi != N64_ABI)
18733 s.ri_gprmask = mips_gprmask;
18734 s.ri_cprmask[0] = mips_cprmask[0];
18735 s.ri_cprmask[1] = mips_cprmask[1];
18736 s.ri_cprmask[2] = mips_cprmask[2];
18737 s.ri_cprmask[3] = mips_cprmask[3];
18738 /* The gp_value field is set by the MIPS ELF backend. */
18740 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
18741 ((Elf32_External_RegInfo *)
18742 mips_regmask_frag));
18746 Elf64_Internal_RegInfo s;
18748 s.ri_gprmask = mips_gprmask;
18750 s.ri_cprmask[0] = mips_cprmask[0];
18751 s.ri_cprmask[1] = mips_cprmask[1];
18752 s.ri_cprmask[2] = mips_cprmask[2];
18753 s.ri_cprmask[3] = mips_cprmask[3];
18754 /* The gp_value field is set by the MIPS ELF backend. */
18756 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
18757 ((Elf64_External_RegInfo *)
18758 mips_regmask_frag));
18761 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18762 sort of BFD interface for this. */
18763 if (mips_any_noreorder)
18764 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
18765 if (mips_pic != NO_PIC)
18767 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
18768 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18771 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18773 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
18774 defined at present; this might need to change in future. */
18775 if (file_ase_mips16)
18776 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
18777 if (file_ase_micromips)
18778 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
18779 if (file_mips_opts.ase & ASE_MDMX)
18780 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
18782 /* Set the MIPS ELF ABI flags. */
18783 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
18784 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
18785 else if (mips_abi == O64_ABI)
18786 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
18787 else if (mips_abi == EABI_ABI)
18789 if (file_mips_opts.gp == 64)
18790 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
18792 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
18794 else if (mips_abi == N32_ABI)
18795 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
18797 /* Nothing to do for N64_ABI. */
18799 if (mips_32bitmode)
18800 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
18802 if (mips_nan2008 == 1)
18803 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008;
18805 /* 32 bit code with 64 bit FP registers. */
18806 fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
18807 Tag_GNU_MIPS_ABI_FP);
18808 if (fpabi == Val_GNU_MIPS_ABI_FP_OLD_64)
18809 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_FP64;
18812 typedef struct proc {
18814 symbolS *func_end_sym;
18815 unsigned long reg_mask;
18816 unsigned long reg_offset;
18817 unsigned long fpreg_mask;
18818 unsigned long fpreg_offset;
18819 unsigned long frame_offset;
18820 unsigned long frame_reg;
18821 unsigned long pc_reg;
18824 static procS cur_proc;
18825 static procS *cur_proc_ptr;
18826 static int numprocs;
18828 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18829 as "2", and a normal nop as "0". */
18831 #define NOP_OPCODE_MIPS 0
18832 #define NOP_OPCODE_MIPS16 1
18833 #define NOP_OPCODE_MICROMIPS 2
18836 mips_nop_opcode (void)
18838 if (seg_info (now_seg)->tc_segment_info_data.micromips)
18839 return NOP_OPCODE_MICROMIPS;
18840 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
18841 return NOP_OPCODE_MIPS16;
18843 return NOP_OPCODE_MIPS;
18846 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18847 32-bit microMIPS NOPs here (if applicable). */
18850 mips_handle_align (fragS *fragp)
18854 int bytes, size, excess;
18857 if (fragp->fr_type != rs_align_code)
18860 p = fragp->fr_literal + fragp->fr_fix;
18862 switch (nop_opcode)
18864 case NOP_OPCODE_MICROMIPS:
18865 opcode = micromips_nop32_insn.insn_opcode;
18868 case NOP_OPCODE_MIPS16:
18869 opcode = mips16_nop_insn.insn_opcode;
18872 case NOP_OPCODE_MIPS:
18874 opcode = nop_insn.insn_opcode;
18879 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
18880 excess = bytes % size;
18882 /* Handle the leading part if we're not inserting a whole number of
18883 instructions, and make it the end of the fixed part of the frag.
18884 Try to fit in a short microMIPS NOP if applicable and possible,
18885 and use zeroes otherwise. */
18886 gas_assert (excess < 4);
18887 fragp->fr_fix += excess;
18892 /* Fall through. */
18894 if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32)
18896 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2);
18900 /* Fall through. */
18903 /* Fall through. */
18908 md_number_to_chars (p, opcode, size);
18909 fragp->fr_var = size;
18918 if (*input_line_pointer == '-')
18920 ++input_line_pointer;
18923 if (!ISDIGIT (*input_line_pointer))
18924 as_bad (_("expected simple number"));
18925 if (input_line_pointer[0] == '0')
18927 if (input_line_pointer[1] == 'x')
18929 input_line_pointer += 2;
18930 while (ISXDIGIT (*input_line_pointer))
18933 val |= hex_value (*input_line_pointer++);
18935 return negative ? -val : val;
18939 ++input_line_pointer;
18940 while (ISDIGIT (*input_line_pointer))
18943 val |= *input_line_pointer++ - '0';
18945 return negative ? -val : val;
18948 if (!ISDIGIT (*input_line_pointer))
18950 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18951 *input_line_pointer, *input_line_pointer);
18952 as_warn (_("invalid number"));
18955 while (ISDIGIT (*input_line_pointer))
18958 val += *input_line_pointer++ - '0';
18960 return negative ? -val : val;
18963 /* The .file directive; just like the usual .file directive, but there
18964 is an initial number which is the ECOFF file index. In the non-ECOFF
18965 case .file implies DWARF-2. */
18968 s_mips_file (int x ATTRIBUTE_UNUSED)
18970 static int first_file_directive = 0;
18972 if (ECOFF_DEBUGGING)
18981 filename = dwarf2_directive_file (0);
18983 /* Versions of GCC up to 3.1 start files with a ".file"
18984 directive even for stabs output. Make sure that this
18985 ".file" is handled. Note that you need a version of GCC
18986 after 3.1 in order to support DWARF-2 on MIPS. */
18987 if (filename != NULL && ! first_file_directive)
18989 (void) new_logical_line (filename, -1);
18990 s_app_file_string (filename, 0);
18992 first_file_directive = 1;
18996 /* The .loc directive, implying DWARF-2. */
18999 s_mips_loc (int x ATTRIBUTE_UNUSED)
19001 if (!ECOFF_DEBUGGING)
19002 dwarf2_directive_loc (0);
19005 /* The .end directive. */
19008 s_mips_end (int x ATTRIBUTE_UNUSED)
19012 /* Following functions need their own .frame and .cprestore directives. */
19013 mips_frame_reg_valid = 0;
19014 mips_cprestore_valid = 0;
19016 if (!is_end_of_line[(unsigned char) *input_line_pointer])
19019 demand_empty_rest_of_line ();
19024 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
19025 as_warn (_(".end not in text section"));
19029 as_warn (_(".end directive without a preceding .ent directive"));
19030 demand_empty_rest_of_line ();
19036 gas_assert (S_GET_NAME (p));
19037 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
19038 as_warn (_(".end symbol does not match .ent symbol"));
19040 if (debug_type == DEBUG_STABS)
19041 stabs_generate_asm_endfunc (S_GET_NAME (p),
19045 as_warn (_(".end directive missing or unknown symbol"));
19047 /* Create an expression to calculate the size of the function. */
19048 if (p && cur_proc_ptr)
19050 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
19051 expressionS *exp = XNEW (expressionS);
19054 exp->X_op = O_subtract;
19055 exp->X_add_symbol = symbol_temp_new_now ();
19056 exp->X_op_symbol = p;
19057 exp->X_add_number = 0;
19059 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
19062 /* Generate a .pdr section. */
19063 if (!ECOFF_DEBUGGING && mips_flag_pdr)
19065 segT saved_seg = now_seg;
19066 subsegT saved_subseg = now_subseg;
19070 #ifdef md_flush_pending_output
19071 md_flush_pending_output ();
19074 gas_assert (pdr_seg);
19075 subseg_set (pdr_seg, 0);
19077 /* Write the symbol. */
19078 exp.X_op = O_symbol;
19079 exp.X_add_symbol = p;
19080 exp.X_add_number = 0;
19081 emit_expr (&exp, 4);
19083 fragp = frag_more (7 * 4);
19085 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
19086 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
19087 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
19088 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
19089 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
19090 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
19091 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
19093 subseg_set (saved_seg, saved_subseg);
19096 cur_proc_ptr = NULL;
19099 /* The .aent and .ent directives. */
19102 s_mips_ent (int aent)
19106 symbolP = get_symbol ();
19107 if (*input_line_pointer == ',')
19108 ++input_line_pointer;
19109 SKIP_WHITESPACE ();
19110 if (ISDIGIT (*input_line_pointer)
19111 || *input_line_pointer == '-')
19114 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
19115 as_warn (_(".ent or .aent not in text section"));
19117 if (!aent && cur_proc_ptr)
19118 as_warn (_("missing .end"));
19122 /* This function needs its own .frame and .cprestore directives. */
19123 mips_frame_reg_valid = 0;
19124 mips_cprestore_valid = 0;
19126 cur_proc_ptr = &cur_proc;
19127 memset (cur_proc_ptr, '\0', sizeof (procS));
19129 cur_proc_ptr->func_sym = symbolP;
19133 if (debug_type == DEBUG_STABS)
19134 stabs_generate_asm_func (S_GET_NAME (symbolP),
19135 S_GET_NAME (symbolP));
19138 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
19140 demand_empty_rest_of_line ();
19143 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19144 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19145 s_mips_frame is used so that we can set the PDR information correctly.
19146 We can't use the ecoff routines because they make reference to the ecoff
19147 symbol table (in the mdebug section). */
19150 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
19152 if (ECOFF_DEBUGGING)
19158 if (cur_proc_ptr == (procS *) NULL)
19160 as_warn (_(".frame outside of .ent"));
19161 demand_empty_rest_of_line ();
19165 cur_proc_ptr->frame_reg = tc_get_register (1);
19167 SKIP_WHITESPACE ();
19168 if (*input_line_pointer++ != ','
19169 || get_absolute_expression_and_terminator (&val) != ',')
19171 as_warn (_("bad .frame directive"));
19172 --input_line_pointer;
19173 demand_empty_rest_of_line ();
19177 cur_proc_ptr->frame_offset = val;
19178 cur_proc_ptr->pc_reg = tc_get_register (0);
19180 demand_empty_rest_of_line ();
19184 /* The .fmask and .mask directives. If the mdebug section is present
19185 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19186 embedded targets, s_mips_mask is used so that we can set the PDR
19187 information correctly. We can't use the ecoff routines because they
19188 make reference to the ecoff symbol table (in the mdebug section). */
19191 s_mips_mask (int reg_type)
19193 if (ECOFF_DEBUGGING)
19194 s_ignore (reg_type);
19199 if (cur_proc_ptr == (procS *) NULL)
19201 as_warn (_(".mask/.fmask outside of .ent"));
19202 demand_empty_rest_of_line ();
19206 if (get_absolute_expression_and_terminator (&mask) != ',')
19208 as_warn (_("bad .mask/.fmask directive"));
19209 --input_line_pointer;
19210 demand_empty_rest_of_line ();
19214 off = get_absolute_expression ();
19216 if (reg_type == 'F')
19218 cur_proc_ptr->fpreg_mask = mask;
19219 cur_proc_ptr->fpreg_offset = off;
19223 cur_proc_ptr->reg_mask = mask;
19224 cur_proc_ptr->reg_offset = off;
19227 demand_empty_rest_of_line ();
19231 /* A table describing all the processors gas knows about. Names are
19232 matched in the order listed.
19234 To ease comparison, please keep this table in the same order as
19235 gcc's mips_cpu_info_table[]. */
19236 static const struct mips_cpu_info mips_cpu_info_table[] =
19238 /* Entries for generic ISAs */
19239 { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 },
19240 { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 },
19241 { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 },
19242 { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 },
19243 { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 },
19244 { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 },
19245 { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19246 { "mips32r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R3, CPU_MIPS32R3 },
19247 { "mips32r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R5, CPU_MIPS32R5 },
19248 { "mips32r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R6, CPU_MIPS32R6 },
19249 { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 },
19250 { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 },
19251 { "mips64r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R3, CPU_MIPS64R3 },
19252 { "mips64r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R5, CPU_MIPS64R5 },
19253 { "mips64r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R6, CPU_MIPS64R6 },
19256 { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 },
19257 { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 },
19258 { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 },
19261 { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 },
19264 { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 },
19265 { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 },
19266 { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 },
19267 { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 },
19268 { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 },
19269 { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 },
19270 { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 },
19271 { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 },
19272 { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 },
19273 { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 },
19274 { "orion", 0, 0, ISA_MIPS3, CPU_R4600 },
19275 { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 },
19276 { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 },
19277 /* ST Microelectronics Loongson 2E and 2F cores */
19278 { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E },
19279 { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F },
19282 { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 },
19283 { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 },
19284 { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 },
19285 { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 },
19286 { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 },
19287 { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 },
19288 { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 },
19289 { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 },
19290 { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 },
19291 { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 },
19292 { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 },
19293 { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 },
19294 { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 },
19295 { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 },
19296 { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 },
19299 { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19300 { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19301 { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19302 { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
19304 /* MIPS 32 Release 2 */
19305 { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19306 { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19307 { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19308 { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
19309 { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19310 { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19311 { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19312 { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19313 { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
19314 ISA_MIPS32R2, CPU_MIPS32R2 },
19315 { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
19316 ISA_MIPS32R2, CPU_MIPS32R2 },
19317 { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19318 { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19319 { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19320 { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19321 /* Deprecated forms of the above. */
19322 { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19323 { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19324 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19325 { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19326 { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19327 { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19328 { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19329 /* Deprecated forms of the above. */
19330 { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19331 { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19332 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19333 { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19334 { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19335 { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19336 { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19337 /* Deprecated forms of the above. */
19338 { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19339 { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19340 /* 34Kn is a 34kc without DSP. */
19341 { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19342 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19343 { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19344 { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19345 { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19346 { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19347 { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19348 /* Deprecated forms of the above. */
19349 { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19350 { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19351 /* 1004K cores are multiprocessor versions of the 34K. */
19352 { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19353 { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19354 { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19355 { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19356 /* interaptiv is the new name for 1004kf */
19357 { "interaptiv", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19359 { "m5100", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 },
19360 { "m5101", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 },
19361 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
19362 { "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R5, CPU_MIPS32R5 },
19365 { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 },
19366 { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 },
19367 { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19368 { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19370 /* Broadcom SB-1 CPU core */
19371 { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
19372 /* Broadcom SB-1A CPU core */
19373 { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
19375 { "loongson3a", 0, 0, ISA_MIPS64R2, CPU_LOONGSON_3A },
19377 /* MIPS 64 Release 2 */
19379 /* Cavium Networks Octeon CPU core */
19380 { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
19381 { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP },
19382 { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 },
19383 { "octeon3", 0, ASE_VIRT | ASE_VIRT64, ISA_MIPS64R5, CPU_OCTEON3 },
19386 { "xlr", 0, 0, ISA_MIPS64, CPU_XLR },
19389 XLP is mostly like XLR, with the prominent exception that it is
19390 MIPS64R2 rather than MIPS64. */
19391 { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
19393 /* MIPS 64 Release 6 */
19394 { "i6400", 0, ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6},
19395 { "p6600", 0, ASE_VIRT | ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6},
19398 { NULL, 0, 0, 0, 0 }
19402 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19403 with a final "000" replaced by "k". Ignore case.
19405 Note: this function is shared between GCC and GAS. */
19408 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
19410 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
19411 given++, canonical++;
19413 return ((*given == 0 && *canonical == 0)
19414 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
19418 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19419 CPU name. We've traditionally allowed a lot of variation here.
19421 Note: this function is shared between GCC and GAS. */
19424 mips_matching_cpu_name_p (const char *canonical, const char *given)
19426 /* First see if the name matches exactly, or with a final "000"
19427 turned into "k". */
19428 if (mips_strict_matching_cpu_name_p (canonical, given))
19431 /* If not, try comparing based on numerical designation alone.
19432 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19433 if (TOLOWER (*given) == 'r')
19435 if (!ISDIGIT (*given))
19438 /* Skip over some well-known prefixes in the canonical name,
19439 hoping to find a number there too. */
19440 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
19442 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
19444 else if (TOLOWER (canonical[0]) == 'r')
19447 return mips_strict_matching_cpu_name_p (canonical, given);
19451 /* Parse an option that takes the name of a processor as its argument.
19452 OPTION is the name of the option and CPU_STRING is the argument.
19453 Return the corresponding processor enumeration if the CPU_STRING is
19454 recognized, otherwise report an error and return null.
19456 A similar function exists in GCC. */
19458 static const struct mips_cpu_info *
19459 mips_parse_cpu (const char *option, const char *cpu_string)
19461 const struct mips_cpu_info *p;
19463 /* 'from-abi' selects the most compatible architecture for the given
19464 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19465 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19466 version. Look first at the -mgp options, if given, otherwise base
19467 the choice on MIPS_DEFAULT_64BIT.
19469 Treat NO_ABI like the EABIs. One reason to do this is that the
19470 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19471 architecture. This code picks MIPS I for 'mips' and MIPS III for
19472 'mips64', just as we did in the days before 'from-abi'. */
19473 if (strcasecmp (cpu_string, "from-abi") == 0)
19475 if (ABI_NEEDS_32BIT_REGS (mips_abi))
19476 return mips_cpu_info_from_isa (ISA_MIPS1);
19478 if (ABI_NEEDS_64BIT_REGS (mips_abi))
19479 return mips_cpu_info_from_isa (ISA_MIPS3);
19481 if (file_mips_opts.gp >= 0)
19482 return mips_cpu_info_from_isa (file_mips_opts.gp == 32
19483 ? ISA_MIPS1 : ISA_MIPS3);
19485 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19490 /* 'default' has traditionally been a no-op. Probably not very useful. */
19491 if (strcasecmp (cpu_string, "default") == 0)
19494 for (p = mips_cpu_info_table; p->name != 0; p++)
19495 if (mips_matching_cpu_name_p (p->name, cpu_string))
19498 as_bad (_("bad value (%s) for %s"), cpu_string, option);
19502 /* Return the canonical processor information for ISA (a member of the
19503 ISA_MIPS* enumeration). */
19505 static const struct mips_cpu_info *
19506 mips_cpu_info_from_isa (int isa)
19510 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19511 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
19512 && isa == mips_cpu_info_table[i].isa)
19513 return (&mips_cpu_info_table[i]);
19518 static const struct mips_cpu_info *
19519 mips_cpu_info_from_arch (int arch)
19523 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19524 if (arch == mips_cpu_info_table[i].cpu)
19525 return (&mips_cpu_info_table[i]);
19531 show (FILE *stream, const char *string, int *col_p, int *first_p)
19535 fprintf (stream, "%24s", "");
19540 fprintf (stream, ", ");
19544 if (*col_p + strlen (string) > 72)
19546 fprintf (stream, "\n%24s", "");
19550 fprintf (stream, "%s", string);
19551 *col_p += strlen (string);
19557 md_show_usage (FILE *stream)
19562 fprintf (stream, _("\
19564 -EB generate big endian output\n\
19565 -EL generate little endian output\n\
19566 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19567 -G NUM allow referencing objects up to NUM bytes\n\
19568 implicitly with the gp register [default 8]\n"));
19569 fprintf (stream, _("\
19570 -mips1 generate MIPS ISA I instructions\n\
19571 -mips2 generate MIPS ISA II instructions\n\
19572 -mips3 generate MIPS ISA III instructions\n\
19573 -mips4 generate MIPS ISA IV instructions\n\
19574 -mips5 generate MIPS ISA V instructions\n\
19575 -mips32 generate MIPS32 ISA instructions\n\
19576 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19577 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
19578 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
19579 -mips32r6 generate MIPS32 release 6 ISA instructions\n\
19580 -mips64 generate MIPS64 ISA instructions\n\
19581 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19582 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
19583 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
19584 -mips64r6 generate MIPS64 release 6 ISA instructions\n\
19585 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19589 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19590 show (stream, mips_cpu_info_table[i].name, &column, &first);
19591 show (stream, "from-abi", &column, &first);
19592 fputc ('\n', stream);
19594 fprintf (stream, _("\
19595 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19596 -no-mCPU don't generate code specific to CPU.\n\
19597 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19601 show (stream, "3900", &column, &first);
19602 show (stream, "4010", &column, &first);
19603 show (stream, "4100", &column, &first);
19604 show (stream, "4650", &column, &first);
19605 fputc ('\n', stream);
19607 fprintf (stream, _("\
19608 -mips16 generate mips16 instructions\n\
19609 -no-mips16 do not generate mips16 instructions\n"));
19610 fprintf (stream, _("\
19611 -mmicromips generate microMIPS instructions\n\
19612 -mno-micromips do not generate microMIPS instructions\n"));
19613 fprintf (stream, _("\
19614 -msmartmips generate smartmips instructions\n\
19615 -mno-smartmips do not generate smartmips instructions\n"));
19616 fprintf (stream, _("\
19617 -mdsp generate DSP instructions\n\
19618 -mno-dsp do not generate DSP instructions\n"));
19619 fprintf (stream, _("\
19620 -mdspr2 generate DSP R2 instructions\n\
19621 -mno-dspr2 do not generate DSP R2 instructions\n"));
19622 fprintf (stream, _("\
19623 -mdspr3 generate DSP R3 instructions\n\
19624 -mno-dspr3 do not generate DSP R3 instructions\n"));
19625 fprintf (stream, _("\
19626 -mmt generate MT instructions\n\
19627 -mno-mt do not generate MT instructions\n"));
19628 fprintf (stream, _("\
19629 -mmcu generate MCU instructions\n\
19630 -mno-mcu do not generate MCU instructions\n"));
19631 fprintf (stream, _("\
19632 -mmsa generate MSA instructions\n\
19633 -mno-msa do not generate MSA instructions\n"));
19634 fprintf (stream, _("\
19635 -mxpa generate eXtended Physical Address (XPA) instructions\n\
19636 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
19637 fprintf (stream, _("\
19638 -mvirt generate Virtualization instructions\n\
19639 -mno-virt do not generate Virtualization instructions\n"));
19640 fprintf (stream, _("\
19641 -minsn32 only generate 32-bit microMIPS instructions\n\
19642 -mno-insn32 generate all microMIPS instructions\n"));
19643 fprintf (stream, _("\
19644 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19645 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19646 -mfix-vr4120 work around certain VR4120 errata\n\
19647 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19648 -mfix-24k insert a nop after ERET and DERET instructions\n\
19649 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19650 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19651 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19652 -msym32 assume all symbols have 32-bit values\n\
19653 -O0 remove unneeded NOPs, do not swap branches\n\
19654 -O remove unneeded NOPs and swap branches\n\
19655 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19656 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19657 fprintf (stream, _("\
19658 -mhard-float allow floating-point instructions\n\
19659 -msoft-float do not allow floating-point instructions\n\
19660 -msingle-float only allow 32-bit floating-point operations\n\
19661 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19662 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
19663 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
19664 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
19668 show (stream, "legacy", &column, &first);
19669 show (stream, "2008", &column, &first);
19671 fputc ('\n', stream);
19673 fprintf (stream, _("\
19674 -KPIC, -call_shared generate SVR4 position independent code\n\
19675 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19676 -mvxworks-pic generate VxWorks position independent code\n\
19677 -non_shared do not generate code that can operate with DSOs\n\
19678 -xgot assume a 32 bit GOT\n\
19679 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19680 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19681 position dependent (non shared) code\n\
19682 -mabi=ABI create ABI conformant object file for:\n"));
19686 show (stream, "32", &column, &first);
19687 show (stream, "o64", &column, &first);
19688 show (stream, "n32", &column, &first);
19689 show (stream, "64", &column, &first);
19690 show (stream, "eabi", &column, &first);
19692 fputc ('\n', stream);
19694 fprintf (stream, _("\
19695 -32 create o32 ABI object file (default)\n\
19696 -n32 create n32 ABI object file\n\
19697 -64 create 64 ABI object file\n"));
19702 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
19704 if (HAVE_64BIT_SYMBOLS)
19705 return dwarf2_format_64bit_irix;
19707 return dwarf2_format_32bit;
19712 mips_dwarf2_addr_size (void)
19714 if (HAVE_64BIT_OBJECTS)
19720 /* Standard calling conventions leave the CFA at SP on entry. */
19722 mips_cfi_frame_initial_instructions (void)
19724 cfi_add_CFA_def_cfa_register (SP);
19728 tc_mips_regname_to_dw2regnum (char *regname)
19730 unsigned int regnum = -1;
19733 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))
19739 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
19740 Given a symbolic attribute NAME, return the proper integer value.
19741 Returns -1 if the attribute is not known. */
19744 mips_convert_symbolic_attribute (const char *name)
19746 static const struct
19751 attribute_table[] =
19753 #define T(tag) {#tag, tag}
19754 T (Tag_GNU_MIPS_ABI_FP),
19755 T (Tag_GNU_MIPS_ABI_MSA),
19763 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
19764 if (streq (name, attribute_table[i].name))
19765 return attribute_table[i].tag;
19773 int fpabi = Val_GNU_MIPS_ABI_FP_ANY;
19775 mips_emit_delays ();
19777 as_warn (_("missing .end at end of assembly"));
19779 /* Just in case no code was emitted, do the consistency check. */
19780 file_mips_check_options ();
19782 /* Set a floating-point ABI if the user did not. */
19783 if (obj_elf_seen_attribute (OBJ_ATTR_GNU, Tag_GNU_MIPS_ABI_FP))
19785 /* Perform consistency checks on the floating-point ABI. */
19786 fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
19787 Tag_GNU_MIPS_ABI_FP);
19788 if (fpabi != Val_GNU_MIPS_ABI_FP_ANY)
19789 check_fpabi (fpabi);
19793 /* Soft-float gets precedence over single-float, the two options should
19794 not be used together so this should not matter. */
19795 if (file_mips_opts.soft_float == 1)
19796 fpabi = Val_GNU_MIPS_ABI_FP_SOFT;
19797 /* Single-float gets precedence over all double_float cases. */
19798 else if (file_mips_opts.single_float == 1)
19799 fpabi = Val_GNU_MIPS_ABI_FP_SINGLE;
19802 switch (file_mips_opts.fp)
19805 if (file_mips_opts.gp == 32)
19806 fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE;
19809 fpabi = Val_GNU_MIPS_ABI_FP_XX;
19812 if (file_mips_opts.gp == 32 && !file_mips_opts.oddspreg)
19813 fpabi = Val_GNU_MIPS_ABI_FP_64A;
19814 else if (file_mips_opts.gp == 32)
19815 fpabi = Val_GNU_MIPS_ABI_FP_64;
19817 fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE;
19822 bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
19823 Tag_GNU_MIPS_ABI_FP, fpabi);
19827 /* Returns the relocation type required for a particular CFI encoding. */
19829 bfd_reloc_code_real_type
19830 mips_cfi_reloc_for_encoding (int encoding)
19832 if (encoding == (DW_EH_PE_sdata4 | DW_EH_PE_pcrel))
19833 return BFD_RELOC_32_PCREL;
19834 else return BFD_RELOC_NONE;