1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2018 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1];
37 typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define streq(a, b) (strcmp (a, b) == 0)
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug = -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr = FALSE;
86 int mips_flag_pdr = TRUE;
91 static char *mips_regmask_frag;
92 static char *mips_flags_frag;
99 #define PIC_CALL_REG 25
107 #define ILLEGAL_REG (32)
109 #define AT mips_opts.at
111 extern int target_big_endian;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME ".rodata"
116 /* Ways in which an instruction can be "appended" to the output. */
118 /* Just add it normally. */
121 /* Add it normally and then add a nop. */
124 /* Turn an instruction with a delay slot into a "compact" version. */
127 /* Insert the instruction before the last one. */
131 /* Information about an instruction, including its format, operands
135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
136 const struct mips_opcode *insn_mo;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. If we have
140 decided to use an extended MIPS16 instruction, this includes the
142 unsigned long insn_opcode;
144 /* The frag that contains the instruction. */
147 /* The offset into FRAG of the first instruction byte. */
150 /* The relocs associated with the instruction, if any. */
153 /* True if this entry cannot be moved from its current position. */
154 unsigned int fixed_p : 1;
156 /* True if this instruction occurred in a .set noreorder block. */
157 unsigned int noreorder_p : 1;
159 /* True for mips16 instructions that jump to an absolute address. */
160 unsigned int mips16_absolute_jump_p : 1;
162 /* True if this instruction is complete. */
163 unsigned int complete_p : 1;
165 /* True if this instruction is cleared from history by unconditional
167 unsigned int cleared_p : 1;
170 /* The ABI to use. */
181 /* MIPS ABI we are using for this output file. */
182 static enum mips_abi_level mips_abi = NO_ABI;
184 /* Whether or not we have code that can call pic code. */
185 int mips_abicalls = FALSE;
187 /* Whether or not we have code which can be put into a shared
189 static bfd_boolean mips_in_shared = TRUE;
191 /* This is the set of options which may be modified by the .set
192 pseudo-op. We use a struct so that .set push and .set pop are more
195 struct mips_set_options
197 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
198 if it has not been initialized. Changed by `.set mipsN', and the
199 -mipsN command line option, and the default CPU. */
201 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
202 <asename>', by command line options, and based on the default
205 /* Whether we are assembling for the mips16 processor. 0 if we are
206 not, 1 if we are, and -1 if the value has not been initialized.
207 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
208 -nomips16 command line options, and the default CPU. */
210 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
211 1 if we are, and -1 if the value has not been initialized. Changed
212 by `.set micromips' and `.set nomicromips', and the -mmicromips
213 and -mno-micromips command line options, and the default CPU. */
215 /* Non-zero if we should not reorder instructions. Changed by `.set
216 reorder' and `.set noreorder'. */
218 /* Non-zero if we should not permit the register designated "assembler
219 temporary" to be used in instructions. The value is the register
220 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
221 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
223 /* Non-zero if we should warn when a macro instruction expands into
224 more than one machine instruction. Changed by `.set nomacro' and
226 int warn_about_macros;
227 /* Non-zero if we should not move instructions. Changed by `.set
228 move', `.set volatile', `.set nomove', and `.set novolatile'. */
230 /* Non-zero if we should not optimize branches by moving the target
231 of the branch into the delay slot. Actually, we don't perform
232 this optimization anyhow. Changed by `.set bopt' and `.set
235 /* Non-zero if we should not autoextend mips16 instructions.
236 Changed by `.set autoextend' and `.set noautoextend'. */
238 /* True if we should only emit 32-bit microMIPS instructions.
239 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
240 and -mno-insn32 command line options. */
242 /* Restrict general purpose registers and floating point registers
243 to 32 bit. This is initially determined when -mgp32 or -mfp32
244 is passed but can changed if the assembler code uses .set mipsN. */
247 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
248 command line option, and the default CPU. */
250 /* True if ".set sym32" is in effect. */
252 /* True if floating-point operations are not allowed. Changed by .set
253 softfloat or .set hardfloat, by command line options -msoft-float or
254 -mhard-float. The default is false. */
255 bfd_boolean soft_float;
257 /* True if only single-precision floating-point operations are allowed.
258 Changed by .set singlefloat or .set doublefloat, command-line options
259 -msingle-float or -mdouble-float. The default is false. */
260 bfd_boolean single_float;
262 /* 1 if single-precision operations on odd-numbered registers are
267 /* Specifies whether module level options have been checked yet. */
268 static bfd_boolean file_mips_opts_checked = FALSE;
270 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
271 value has not been initialized. Changed by `.nan legacy' and
272 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
273 options, and the default CPU. */
274 static int mips_nan2008 = -1;
276 /* This is the struct we use to hold the module level set of options.
277 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
278 fp fields to -1 to indicate that they have not been initialized. */
280 static struct mips_set_options file_mips_opts =
282 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
283 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
284 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
285 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
286 /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1
289 /* This is similar to file_mips_opts, but for the current set of options. */
291 static struct mips_set_options mips_opts =
293 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
294 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
295 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
296 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
297 /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1
300 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
301 static unsigned int file_ase_explicit;
303 /* These variables are filled in with the masks of registers used.
304 The object format code reads them and puts them in the appropriate
306 unsigned long mips_gprmask;
307 unsigned long mips_cprmask[4];
309 /* True if any MIPS16 code was produced. */
310 static int file_ase_mips16;
312 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
313 || mips_opts.isa == ISA_MIPS32R2 \
314 || mips_opts.isa == ISA_MIPS32R3 \
315 || mips_opts.isa == ISA_MIPS32R5 \
316 || mips_opts.isa == ISA_MIPS64 \
317 || mips_opts.isa == ISA_MIPS64R2 \
318 || mips_opts.isa == ISA_MIPS64R3 \
319 || mips_opts.isa == ISA_MIPS64R5)
321 /* True if any microMIPS code was produced. */
322 static int file_ase_micromips;
324 /* True if we want to create R_MIPS_JALR for jalr $25. */
326 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
328 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
329 because there's no place for any addend, the only acceptable
330 expression is a bare symbol. */
331 #define MIPS_JALR_HINT_P(EXPR) \
332 (!HAVE_IN_PLACE_ADDENDS \
333 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
336 /* The argument of the -march= flag. The architecture we are assembling. */
337 static const char *mips_arch_string;
339 /* The argument of the -mtune= flag. The architecture for which we
341 static int mips_tune = CPU_UNKNOWN;
342 static const char *mips_tune_string;
344 /* True when generating 32-bit code for a 64-bit processor. */
345 static int mips_32bitmode = 0;
347 /* True if the given ABI requires 32-bit registers. */
348 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
350 /* Likewise 64-bit registers. */
351 #define ABI_NEEDS_64BIT_REGS(ABI) \
353 || (ABI) == N64_ABI \
356 #define ISA_IS_R6(ISA) \
357 ((ISA) == ISA_MIPS32R6 \
358 || (ISA) == ISA_MIPS64R6)
360 /* Return true if ISA supports 64 bit wide gp registers. */
361 #define ISA_HAS_64BIT_REGS(ISA) \
362 ((ISA) == ISA_MIPS3 \
363 || (ISA) == ISA_MIPS4 \
364 || (ISA) == ISA_MIPS5 \
365 || (ISA) == ISA_MIPS64 \
366 || (ISA) == ISA_MIPS64R2 \
367 || (ISA) == ISA_MIPS64R3 \
368 || (ISA) == ISA_MIPS64R5 \
369 || (ISA) == ISA_MIPS64R6)
371 /* Return true if ISA supports 64 bit wide float registers. */
372 #define ISA_HAS_64BIT_FPRS(ISA) \
373 ((ISA) == ISA_MIPS3 \
374 || (ISA) == ISA_MIPS4 \
375 || (ISA) == ISA_MIPS5 \
376 || (ISA) == ISA_MIPS32R2 \
377 || (ISA) == ISA_MIPS32R3 \
378 || (ISA) == ISA_MIPS32R5 \
379 || (ISA) == ISA_MIPS32R6 \
380 || (ISA) == ISA_MIPS64 \
381 || (ISA) == ISA_MIPS64R2 \
382 || (ISA) == ISA_MIPS64R3 \
383 || (ISA) == ISA_MIPS64R5 \
384 || (ISA) == ISA_MIPS64R6)
386 /* Return true if ISA supports 64-bit right rotate (dror et al.)
388 #define ISA_HAS_DROR(ISA) \
389 ((ISA) == ISA_MIPS64R2 \
390 || (ISA) == ISA_MIPS64R3 \
391 || (ISA) == ISA_MIPS64R5 \
392 || (ISA) == ISA_MIPS64R6 \
393 || (mips_opts.micromips \
394 && ISA_HAS_64BIT_REGS (ISA)) \
397 /* Return true if ISA supports 32-bit right rotate (ror et al.)
399 #define ISA_HAS_ROR(ISA) \
400 ((ISA) == ISA_MIPS32R2 \
401 || (ISA) == ISA_MIPS32R3 \
402 || (ISA) == ISA_MIPS32R5 \
403 || (ISA) == ISA_MIPS32R6 \
404 || (ISA) == ISA_MIPS64R2 \
405 || (ISA) == ISA_MIPS64R3 \
406 || (ISA) == ISA_MIPS64R5 \
407 || (ISA) == ISA_MIPS64R6 \
408 || (mips_opts.ase & ASE_SMARTMIPS) \
409 || mips_opts.micromips \
412 /* Return true if ISA supports single-precision floats in odd registers. */
413 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
414 (((ISA) == ISA_MIPS32 \
415 || (ISA) == ISA_MIPS32R2 \
416 || (ISA) == ISA_MIPS32R3 \
417 || (ISA) == ISA_MIPS32R5 \
418 || (ISA) == ISA_MIPS32R6 \
419 || (ISA) == ISA_MIPS64 \
420 || (ISA) == ISA_MIPS64R2 \
421 || (ISA) == ISA_MIPS64R3 \
422 || (ISA) == ISA_MIPS64R5 \
423 || (ISA) == ISA_MIPS64R6 \
424 || (CPU) == CPU_R5900) \
425 && ((CPU) != CPU_GS464 \
426 || (CPU) != CPU_GS464E))
428 /* Return true if ISA supports move to/from high part of a 64-bit
429 floating-point register. */
430 #define ISA_HAS_MXHC1(ISA) \
431 ((ISA) == ISA_MIPS32R2 \
432 || (ISA) == ISA_MIPS32R3 \
433 || (ISA) == ISA_MIPS32R5 \
434 || (ISA) == ISA_MIPS32R6 \
435 || (ISA) == ISA_MIPS64R2 \
436 || (ISA) == ISA_MIPS64R3 \
437 || (ISA) == ISA_MIPS64R5 \
438 || (ISA) == ISA_MIPS64R6)
440 /* Return true if ISA supports legacy NAN. */
441 #define ISA_HAS_LEGACY_NAN(ISA) \
442 ((ISA) == ISA_MIPS1 \
443 || (ISA) == ISA_MIPS2 \
444 || (ISA) == ISA_MIPS3 \
445 || (ISA) == ISA_MIPS4 \
446 || (ISA) == ISA_MIPS5 \
447 || (ISA) == ISA_MIPS32 \
448 || (ISA) == ISA_MIPS32R2 \
449 || (ISA) == ISA_MIPS32R3 \
450 || (ISA) == ISA_MIPS32R5 \
451 || (ISA) == ISA_MIPS64 \
452 || (ISA) == ISA_MIPS64R2 \
453 || (ISA) == ISA_MIPS64R3 \
454 || (ISA) == ISA_MIPS64R5)
457 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
462 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
466 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
468 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
470 /* True if relocations are stored in-place. */
471 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
473 /* The ABI-derived address size. */
474 #define HAVE_64BIT_ADDRESSES \
475 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
476 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
478 /* The size of symbolic constants (i.e., expressions of the form
479 "SYMBOL" or "SYMBOL + OFFSET"). */
480 #define HAVE_32BIT_SYMBOLS \
481 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
482 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
484 /* Addresses are loaded in different ways, depending on the address size
485 in use. The n32 ABI Documentation also mandates the use of additions
486 with overflow checking, but existing implementations don't follow it. */
487 #define ADDRESS_ADD_INSN \
488 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
490 #define ADDRESS_ADDI_INSN \
491 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
493 #define ADDRESS_LOAD_INSN \
494 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
496 #define ADDRESS_STORE_INSN \
497 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
499 /* Return true if the given CPU supports the MIPS16 ASE. */
500 #define CPU_HAS_MIPS16(cpu) \
501 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
502 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
504 /* Return true if the given CPU supports the microMIPS ASE. */
505 #define CPU_HAS_MICROMIPS(cpu) 0
507 /* True if CPU has a dror instruction. */
508 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
510 /* True if CPU has a ror instruction. */
511 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
513 /* True if CPU is in the Octeon family */
514 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
515 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
517 /* True if CPU has seq/sne and seqi/snei instructions. */
518 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
520 /* True, if CPU has support for ldc1 and sdc1. */
521 #define CPU_HAS_LDC1_SDC1(CPU) \
522 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
524 /* True if mflo and mfhi can be immediately followed by instructions
525 which write to the HI and LO registers.
527 According to MIPS specifications, MIPS ISAs I, II, and III need
528 (at least) two instructions between the reads of HI/LO and
529 instructions which write them, and later ISAs do not. Contradicting
530 the MIPS specifications, some MIPS IV processor user manuals (e.g.
531 the UM for the NEC Vr5000) document needing the instructions between
532 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
533 MIPS64 and later ISAs to have the interlocks, plus any specific
534 earlier-ISA CPUs for which CPU documentation declares that the
535 instructions are really interlocked. */
536 #define hilo_interlocks \
537 (mips_opts.isa == ISA_MIPS32 \
538 || mips_opts.isa == ISA_MIPS32R2 \
539 || mips_opts.isa == ISA_MIPS32R3 \
540 || mips_opts.isa == ISA_MIPS32R5 \
541 || mips_opts.isa == ISA_MIPS32R6 \
542 || mips_opts.isa == ISA_MIPS64 \
543 || mips_opts.isa == ISA_MIPS64R2 \
544 || mips_opts.isa == ISA_MIPS64R3 \
545 || mips_opts.isa == ISA_MIPS64R5 \
546 || mips_opts.isa == ISA_MIPS64R6 \
547 || mips_opts.arch == CPU_R4010 \
548 || mips_opts.arch == CPU_R5900 \
549 || mips_opts.arch == CPU_R10000 \
550 || mips_opts.arch == CPU_R12000 \
551 || mips_opts.arch == CPU_R14000 \
552 || mips_opts.arch == CPU_R16000 \
553 || mips_opts.arch == CPU_RM7000 \
554 || mips_opts.arch == CPU_VR5500 \
555 || mips_opts.micromips \
558 /* Whether the processor uses hardware interlocks to protect reads
559 from the GPRs after they are loaded from memory, and thus does not
560 require nops to be inserted. This applies to instructions marked
561 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
562 level I and microMIPS mode instructions are always interlocked. */
563 #define gpr_interlocks \
564 (mips_opts.isa != ISA_MIPS1 \
565 || mips_opts.arch == CPU_R3900 \
566 || mips_opts.arch == CPU_R5900 \
567 || mips_opts.micromips \
570 /* Whether the processor uses hardware interlocks to avoid delays
571 required by coprocessor instructions, and thus does not require
572 nops to be inserted. This applies to instructions marked
573 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
574 instructions marked INSN_WRITE_COND_CODE and ones marked
575 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
576 levels I, II, and III and microMIPS mode instructions are always
578 /* Itbl support may require additional care here. */
579 #define cop_interlocks \
580 ((mips_opts.isa != ISA_MIPS1 \
581 && mips_opts.isa != ISA_MIPS2 \
582 && mips_opts.isa != ISA_MIPS3) \
583 || mips_opts.arch == CPU_R4300 \
584 || mips_opts.micromips \
587 /* Whether the processor uses hardware interlocks to protect reads
588 from coprocessor registers after they are loaded from memory, and
589 thus does not require nops to be inserted. This applies to
590 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
591 requires at MIPS ISA level I and microMIPS mode instructions are
592 always interlocked. */
593 #define cop_mem_interlocks \
594 (mips_opts.isa != ISA_MIPS1 \
595 || mips_opts.micromips \
598 /* Is this a mfhi or mflo instruction? */
599 #define MF_HILO_INSN(PINFO) \
600 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
602 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
603 has been selected. This implies, in particular, that addresses of text
604 labels have their LSB set. */
605 #define HAVE_CODE_COMPRESSION \
606 ((mips_opts.mips16 | mips_opts.micromips) != 0)
608 /* The minimum and maximum signed values that can be stored in a GPR. */
609 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
610 #define GPR_SMIN (-GPR_SMAX - 1)
612 /* MIPS PIC level. */
614 enum mips_pic_level mips_pic;
616 /* 1 if we should generate 32 bit offsets from the $gp register in
617 SVR4_PIC mode. Currently has no meaning in other modes. */
618 static int mips_big_got = 0;
620 /* 1 if trap instructions should used for overflow rather than break
622 static int mips_trap = 0;
624 /* 1 if double width floating point constants should not be constructed
625 by assembling two single width halves into two single width floating
626 point registers which just happen to alias the double width destination
627 register. On some architectures this aliasing can be disabled by a bit
628 in the status register, and the setting of this bit cannot be determined
629 automatically at assemble time. */
630 static int mips_disable_float_construction;
632 /* Non-zero if any .set noreorder directives were used. */
634 static int mips_any_noreorder;
636 /* Non-zero if nops should be inserted when the register referenced in
637 an mfhi/mflo instruction is read in the next two instructions. */
638 static int mips_7000_hilo_fix;
640 /* The size of objects in the small data section. */
641 static unsigned int g_switch_value = 8;
642 /* Whether the -G option was used. */
643 static int g_switch_seen = 0;
648 /* If we can determine in advance that GP optimization won't be
649 possible, we can skip the relaxation stuff that tries to produce
650 GP-relative references. This makes delay slot optimization work
653 This function can only provide a guess, but it seems to work for
654 gcc output. It needs to guess right for gcc, otherwise gcc
655 will put what it thinks is a GP-relative instruction in a branch
658 I don't know if a fix is needed for the SVR4_PIC mode. I've only
659 fixed it for the non-PIC mode. KR 95/04/07 */
660 static int nopic_need_relax (symbolS *, int);
662 /* handle of the OPCODE hash table */
663 static struct hash_control *op_hash = NULL;
665 /* The opcode hash table we use for the mips16. */
666 static struct hash_control *mips16_op_hash = NULL;
668 /* The opcode hash table we use for the microMIPS ASE. */
669 static struct hash_control *micromips_op_hash = NULL;
671 /* This array holds the chars that always start a comment. If the
672 pre-processor is disabled, these aren't very useful */
673 const char comment_chars[] = "#";
675 /* This array holds the chars that only start a comment at the beginning of
676 a line. If the line seems to have the form '# 123 filename'
677 .line and .file directives will appear in the pre-processed output */
678 /* Note that input_file.c hand checks for '#' at the beginning of the
679 first line of the input file. This is because the compiler outputs
680 #NO_APP at the beginning of its output. */
681 /* Also note that C style comments are always supported. */
682 const char line_comment_chars[] = "#";
684 /* This array holds machine specific line separator characters. */
685 const char line_separator_chars[] = ";";
687 /* Chars that can be used to separate mant from exp in floating point nums */
688 const char EXP_CHARS[] = "eE";
690 /* Chars that mean this number is a floating point constant */
693 const char FLT_CHARS[] = "rRsSfFdDxXpP";
695 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
696 changed in read.c . Ideally it shouldn't have to know about it at all,
697 but nothing is ideal around here.
700 /* Types of printf format used for instruction-related error messages.
701 "I" means int ("%d") and "S" means string ("%s"). */
702 enum mips_insn_error_format {
708 /* Information about an error that was found while assembling the current
710 struct mips_insn_error {
711 /* We sometimes need to match an instruction against more than one
712 opcode table entry. Errors found during this matching are reported
713 against a particular syntactic argument rather than against the
714 instruction as a whole. We grade these messages so that errors
715 against argument N have a greater priority than an error against
716 any argument < N, since the former implies that arguments up to N
717 were acceptable and that the opcode entry was therefore a closer match.
718 If several matches report an error against the same argument,
719 we only use that error if it is the same in all cases.
721 min_argnum is the minimum argument number for which an error message
722 should be accepted. It is 0 if MSG is against the instruction as
726 /* The printf()-style message, including its format and arguments. */
727 enum mips_insn_error_format format;
735 /* The error that should be reported for the current instruction. */
736 static struct mips_insn_error insn_error;
738 static int auto_align = 1;
740 /* When outputting SVR4 PIC code, the assembler needs to know the
741 offset in the stack frame from which to restore the $gp register.
742 This is set by the .cprestore pseudo-op, and saved in this
744 static offsetT mips_cprestore_offset = -1;
746 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
747 more optimizations, it can use a register value instead of a memory-saved
748 offset and even an other register than $gp as global pointer. */
749 static offsetT mips_cpreturn_offset = -1;
750 static int mips_cpreturn_register = -1;
751 static int mips_gp_register = GP;
752 static int mips_gprel_offset = 0;
754 /* Whether mips_cprestore_offset has been set in the current function
755 (or whether it has already been warned about, if not). */
756 static int mips_cprestore_valid = 0;
758 /* This is the register which holds the stack frame, as set by the
759 .frame pseudo-op. This is needed to implement .cprestore. */
760 static int mips_frame_reg = SP;
762 /* Whether mips_frame_reg has been set in the current function
763 (or whether it has already been warned about, if not). */
764 static int mips_frame_reg_valid = 0;
766 /* To output NOP instructions correctly, we need to keep information
767 about the previous two instructions. */
769 /* Whether we are optimizing. The default value of 2 means to remove
770 unneeded NOPs and swap branch instructions when possible. A value
771 of 1 means to not swap branches. A value of 0 means to always
773 static int mips_optimize = 2;
775 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
776 equivalent to seeing no -g option at all. */
777 static int mips_debug = 0;
779 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
780 #define MAX_VR4130_NOPS 4
782 /* The maximum number of NOPs needed to fill delay slots. */
783 #define MAX_DELAY_NOPS 2
785 /* The maximum number of NOPs needed for any purpose. */
788 /* A list of previous instructions, with index 0 being the most recent.
789 We need to look back MAX_NOPS instructions when filling delay slots
790 or working around processor errata. We need to look back one
791 instruction further if we're thinking about using history[0] to
792 fill a branch delay slot. */
793 static struct mips_cl_insn history[1 + MAX_NOPS];
795 /* Arrays of operands for each instruction. */
796 #define MAX_OPERANDS 6
797 struct mips_operand_array {
798 const struct mips_operand *operand[MAX_OPERANDS];
800 static struct mips_operand_array *mips_operands;
801 static struct mips_operand_array *mips16_operands;
802 static struct mips_operand_array *micromips_operands;
804 /* Nop instructions used by emit_nop. */
805 static struct mips_cl_insn nop_insn;
806 static struct mips_cl_insn mips16_nop_insn;
807 static struct mips_cl_insn micromips_nop16_insn;
808 static struct mips_cl_insn micromips_nop32_insn;
810 /* The appropriate nop for the current mode. */
811 #define NOP_INSN (mips_opts.mips16 \
813 : (mips_opts.micromips \
814 ? (mips_opts.insn32 \
815 ? µmips_nop32_insn \
816 : µmips_nop16_insn) \
819 /* The size of NOP_INSN in bytes. */
820 #define NOP_INSN_SIZE ((mips_opts.mips16 \
821 || (mips_opts.micromips && !mips_opts.insn32)) \
824 /* If this is set, it points to a frag holding nop instructions which
825 were inserted before the start of a noreorder section. If those
826 nops turn out to be unnecessary, the size of the frag can be
828 static fragS *prev_nop_frag;
830 /* The number of nop instructions we created in prev_nop_frag. */
831 static int prev_nop_frag_holds;
833 /* The number of nop instructions that we know we need in
835 static int prev_nop_frag_required;
837 /* The number of instructions we've seen since prev_nop_frag. */
838 static int prev_nop_frag_since;
840 /* Relocations against symbols are sometimes done in two parts, with a HI
841 relocation and a LO relocation. Each relocation has only 16 bits of
842 space to store an addend. This means that in order for the linker to
843 handle carries correctly, it must be able to locate both the HI and
844 the LO relocation. This means that the relocations must appear in
845 order in the relocation table.
847 In order to implement this, we keep track of each unmatched HI
848 relocation. We then sort them so that they immediately precede the
849 corresponding LO relocation. */
854 struct mips_hi_fixup *next;
857 /* The section this fixup is in. */
861 /* The list of unmatched HI relocs. */
863 static struct mips_hi_fixup *mips_hi_fixup_list;
865 /* The frag containing the last explicit relocation operator.
866 Null if explicit relocations have not been used. */
868 static fragS *prev_reloc_op_frag;
870 /* Map mips16 register numbers to normal MIPS register numbers. */
872 static const unsigned int mips16_to_32_reg_map[] =
874 16, 17, 2, 3, 4, 5, 6, 7
877 /* Map microMIPS register numbers to normal MIPS register numbers. */
879 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
881 /* The microMIPS registers with type h. */
882 static const unsigned int micromips_to_32_reg_h_map1[] =
884 5, 5, 6, 4, 4, 4, 4, 4
886 static const unsigned int micromips_to_32_reg_h_map2[] =
888 6, 7, 7, 21, 22, 5, 6, 7
891 /* The microMIPS registers with type m. */
892 static const unsigned int micromips_to_32_reg_m_map[] =
894 0, 17, 2, 3, 16, 18, 19, 20
897 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
899 /* Classifies the kind of instructions we're interested in when
900 implementing -mfix-vr4120. */
901 enum fix_vr4120_class
909 NUM_FIX_VR4120_CLASSES
912 /* ...likewise -mfix-loongson2f-jump. */
913 static bfd_boolean mips_fix_loongson2f_jump;
915 /* ...likewise -mfix-loongson2f-nop. */
916 static bfd_boolean mips_fix_loongson2f_nop;
918 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
919 static bfd_boolean mips_fix_loongson2f;
921 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
922 there must be at least one other instruction between an instruction
923 of type X and an instruction of type Y. */
924 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
926 /* True if -mfix-vr4120 is in force. */
927 static int mips_fix_vr4120;
929 /* ...likewise -mfix-vr4130. */
930 static int mips_fix_vr4130;
932 /* ...likewise -mfix-24k. */
933 static int mips_fix_24k;
935 /* ...likewise -mfix-rm7000 */
936 static int mips_fix_rm7000;
938 /* ...likewise -mfix-cn63xxp1 */
939 static bfd_boolean mips_fix_cn63xxp1;
941 /* We don't relax branches by default, since this causes us to expand
942 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
943 fail to compute the offset before expanding the macro to the most
944 efficient expansion. */
946 static int mips_relax_branch;
948 /* TRUE if checks are suppressed for invalid branches between ISA modes.
949 Needed for broken assembly produced by some GCC versions and some
950 sloppy code out there, where branches to data labels are present. */
951 static bfd_boolean mips_ignore_branch_isa;
953 /* The expansion of many macros depends on the type of symbol that
954 they refer to. For example, when generating position-dependent code,
955 a macro that refers to a symbol may have two different expansions,
956 one which uses GP-relative addresses and one which uses absolute
957 addresses. When generating SVR4-style PIC, a macro may have
958 different expansions for local and global symbols.
960 We handle these situations by generating both sequences and putting
961 them in variant frags. In position-dependent code, the first sequence
962 will be the GP-relative one and the second sequence will be the
963 absolute one. In SVR4 PIC, the first sequence will be for global
964 symbols and the second will be for local symbols.
966 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
967 SECOND are the lengths of the two sequences in bytes. These fields
968 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
969 the subtype has the following flags:
972 Set if generating PIC code.
975 Set if it has been decided that we should use the second
976 sequence instead of the first.
979 Set in the first variant frag if the macro's second implementation
980 is longer than its first. This refers to the macro as a whole,
981 not an individual relaxation.
984 Set in the first variant frag if the macro appeared in a .set nomacro
985 block and if one alternative requires a warning but the other does not.
988 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
991 RELAX_DELAY_SLOT_16BIT
992 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
995 RELAX_DELAY_SLOT_SIZE_FIRST
996 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
997 the macro is of the wrong size for the branch delay slot.
999 RELAX_DELAY_SLOT_SIZE_SECOND
1000 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
1001 the macro is of the wrong size for the branch delay slot.
1003 The frag's "opcode" points to the first fixup for relaxable code.
1005 Relaxable macros are generated using a sequence such as:
1007 relax_start (SYMBOL);
1008 ... generate first expansion ...
1010 ... generate second expansion ...
1013 The code and fixups for the unwanted alternative are discarded
1014 by md_convert_frag. */
1015 #define RELAX_ENCODE(FIRST, SECOND, PIC) \
1016 (((FIRST) << 8) | (SECOND) | ((PIC) ? 0x10000 : 0))
1018 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1019 #define RELAX_SECOND(X) ((X) & 0xff)
1020 #define RELAX_PIC(X) (((X) & 0x10000) != 0)
1021 #define RELAX_USE_SECOND 0x20000
1022 #define RELAX_SECOND_LONGER 0x40000
1023 #define RELAX_NOMACRO 0x80000
1024 #define RELAX_DELAY_SLOT 0x100000
1025 #define RELAX_DELAY_SLOT_16BIT 0x200000
1026 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x400000
1027 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x800000
1029 /* Branch without likely bit. If label is out of range, we turn:
1031 beq reg1, reg2, label
1041 with the following opcode replacements:
1048 bltzal <-> bgezal (with jal label instead of j label)
1050 Even though keeping the delay slot instruction in the delay slot of
1051 the branch would be more efficient, it would be very tricky to do
1052 correctly, because we'd have to introduce a variable frag *after*
1053 the delay slot instruction, and expand that instead. Let's do it
1054 the easy way for now, even if the branch-not-taken case now costs
1055 one additional instruction. Out-of-range branches are not supposed
1056 to be common, anyway.
1058 Branch likely. If label is out of range, we turn:
1060 beql reg1, reg2, label
1061 delay slot (annulled if branch not taken)
1070 delay slot (executed only if branch taken)
1073 It would be possible to generate a shorter sequence by losing the
1074 likely bit, generating something like:
1079 delay slot (executed only if branch taken)
1091 bltzall -> bgezal (with jal label instead of j label)
1092 bgezall -> bltzal (ditto)
1095 but it's not clear that it would actually improve performance. */
1096 #define RELAX_BRANCH_ENCODE(at, pic, \
1097 uncond, likely, link, toofar) \
1098 ((relax_substateT) \
1101 | ((pic) ? 0x20 : 0) \
1102 | ((toofar) ? 0x40 : 0) \
1103 | ((link) ? 0x80 : 0) \
1104 | ((likely) ? 0x100 : 0) \
1105 | ((uncond) ? 0x200 : 0)))
1106 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1107 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x200) != 0)
1108 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x100) != 0)
1109 #define RELAX_BRANCH_LINK(i) (((i) & 0x80) != 0)
1110 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x40) != 0)
1111 #define RELAX_BRANCH_PIC(i) (((i) & 0x20) != 0)
1112 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1114 /* For mips16 code, we use an entirely different form of relaxation.
1115 mips16 supports two versions of most instructions which take
1116 immediate values: a small one which takes some small value, and a
1117 larger one which takes a 16 bit value. Since branches also follow
1118 this pattern, relaxing these values is required.
1120 We can assemble both mips16 and normal MIPS code in a single
1121 object. Therefore, we need to support this type of relaxation at
1122 the same time that we support the relaxation described above. We
1123 use the high bit of the subtype field to distinguish these cases.
1125 The information we store for this type of relaxation is the
1126 argument code found in the opcode file for this relocation, whether
1127 the user explicitly requested a small or extended form, and whether
1128 the relocation is in a jump or jal delay slot. That tells us the
1129 size of the value, and how it should be stored. We also store
1130 whether the fragment is considered to be extended or not. We also
1131 store whether this is known to be a branch to a different section,
1132 whether we have tried to relax this frag yet, and whether we have
1133 ever extended a PC relative fragment because of a shift count. */
1134 #define RELAX_MIPS16_ENCODE(type, e2, pic, sym32, nomacro, \
1139 | ((e2) ? 0x100 : 0) \
1140 | ((pic) ? 0x200 : 0) \
1141 | ((sym32) ? 0x400 : 0) \
1142 | ((nomacro) ? 0x800 : 0) \
1143 | ((small) ? 0x1000 : 0) \
1144 | ((ext) ? 0x2000 : 0) \
1145 | ((dslot) ? 0x4000 : 0) \
1146 | ((jal_dslot) ? 0x8000 : 0))
1148 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1149 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1150 #define RELAX_MIPS16_E2(i) (((i) & 0x100) != 0)
1151 #define RELAX_MIPS16_PIC(i) (((i) & 0x200) != 0)
1152 #define RELAX_MIPS16_SYM32(i) (((i) & 0x400) != 0)
1153 #define RELAX_MIPS16_NOMACRO(i) (((i) & 0x800) != 0)
1154 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x1000) != 0)
1155 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x2000) != 0)
1156 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x4000) != 0)
1157 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x8000) != 0)
1159 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x10000) != 0)
1160 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x10000)
1161 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) & ~0x10000)
1162 #define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x20000) != 0)
1163 #define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x20000)
1164 #define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x20000)
1165 #define RELAX_MIPS16_MACRO(i) (((i) & 0x40000) != 0)
1166 #define RELAX_MIPS16_MARK_MACRO(i) ((i) | 0x40000)
1167 #define RELAX_MIPS16_CLEAR_MACRO(i) ((i) & ~0x40000)
1169 /* For microMIPS code, we use relaxation similar to one we use for
1170 MIPS16 code. Some instructions that take immediate values support
1171 two encodings: a small one which takes some small value, and a
1172 larger one which takes a 16 bit value. As some branches also follow
1173 this pattern, relaxing these values is required.
1175 We can assemble both microMIPS and normal MIPS code in a single
1176 object. Therefore, we need to support this type of relaxation at
1177 the same time that we support the relaxation described above. We
1178 use one of the high bits of the subtype field to distinguish these
1181 The information we store for this type of relaxation is the argument
1182 code found in the opcode file for this relocation, the register
1183 selected as the assembler temporary, whether in the 32-bit
1184 instruction mode, whether the branch is unconditional, whether it is
1185 compact, whether there is no delay-slot instruction available to fill
1186 in, whether it stores the link address implicitly in $ra, whether
1187 relaxation of out-of-range 32-bit branches to a sequence of
1188 instructions is enabled, and whether the displacement of a branch is
1189 too large to fit as an immediate argument of a 16-bit and a 32-bit
1190 branch, respectively. */
1191 #define RELAX_MICROMIPS_ENCODE(type, at, insn32, pic, \
1192 uncond, compact, link, nods, \
1193 relax32, toofar16, toofar32) \
1196 | (((at) & 0x1f) << 8) \
1197 | ((insn32) ? 0x2000 : 0) \
1198 | ((pic) ? 0x4000 : 0) \
1199 | ((uncond) ? 0x8000 : 0) \
1200 | ((compact) ? 0x10000 : 0) \
1201 | ((link) ? 0x20000 : 0) \
1202 | ((nods) ? 0x40000 : 0) \
1203 | ((relax32) ? 0x80000 : 0) \
1204 | ((toofar16) ? 0x100000 : 0) \
1205 | ((toofar32) ? 0x200000 : 0))
1206 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1207 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1208 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1209 #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0)
1210 #define RELAX_MICROMIPS_PIC(i) (((i) & 0x4000) != 0)
1211 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x8000) != 0)
1212 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x10000) != 0)
1213 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x20000) != 0)
1214 #define RELAX_MICROMIPS_NODS(i) (((i) & 0x40000) != 0)
1215 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x80000) != 0)
1217 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x100000) != 0)
1218 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x100000)
1219 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x100000)
1220 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x200000) != 0)
1221 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x200000)
1222 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x200000)
1224 /* Sign-extend 16-bit value X. */
1225 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1227 /* Is the given value a sign-extended 32-bit value? */
1228 #define IS_SEXT_32BIT_NUM(x) \
1229 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1230 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1232 /* Is the given value a sign-extended 16-bit value? */
1233 #define IS_SEXT_16BIT_NUM(x) \
1234 (((x) &~ (offsetT) 0x7fff) == 0 \
1235 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1237 /* Is the given value a sign-extended 12-bit value? */
1238 #define IS_SEXT_12BIT_NUM(x) \
1239 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1241 /* Is the given value a sign-extended 9-bit value? */
1242 #define IS_SEXT_9BIT_NUM(x) \
1243 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1245 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1246 #define IS_ZEXT_32BIT_NUM(x) \
1247 (((x) &~ (offsetT) 0xffffffff) == 0 \
1248 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1250 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1252 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1253 (((STRUCT) >> (SHIFT)) & (MASK))
1255 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1256 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1258 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1259 : EXTRACT_BITS ((INSN).insn_opcode, \
1260 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1261 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1262 EXTRACT_BITS ((INSN).insn_opcode, \
1263 MIPS16OP_MASK_##FIELD, \
1264 MIPS16OP_SH_##FIELD)
1266 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1267 #define MIPS16_EXTEND (0xf000U << 16)
1269 /* Whether or not we are emitting a branch-likely macro. */
1270 static bfd_boolean emit_branch_likely_macro = FALSE;
1272 /* Global variables used when generating relaxable macros. See the
1273 comment above RELAX_ENCODE for more details about how relaxation
1276 /* 0 if we're not emitting a relaxable macro.
1277 1 if we're emitting the first of the two relaxation alternatives.
1278 2 if we're emitting the second alternative. */
1281 /* The first relaxable fixup in the current frag. (In other words,
1282 the first fixup that refers to relaxable code.) */
1285 /* sizes[0] says how many bytes of the first alternative are stored in
1286 the current frag. Likewise sizes[1] for the second alternative. */
1287 unsigned int sizes[2];
1289 /* The symbol on which the choice of sequence depends. */
1293 /* Global variables used to decide whether a macro needs a warning. */
1295 /* True if the macro is in a branch delay slot. */
1296 bfd_boolean delay_slot_p;
1298 /* Set to the length in bytes required if the macro is in a delay slot
1299 that requires a specific length of instruction, otherwise zero. */
1300 unsigned int delay_slot_length;
1302 /* For relaxable macros, sizes[0] is the length of the first alternative
1303 in bytes and sizes[1] is the length of the second alternative.
1304 For non-relaxable macros, both elements give the length of the
1306 unsigned int sizes[2];
1308 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1309 instruction of the first alternative in bytes and first_insn_sizes[1]
1310 is the length of the first instruction of the second alternative.
1311 For non-relaxable macros, both elements give the length of the first
1312 instruction in bytes.
1314 Set to zero if we haven't yet seen the first instruction. */
1315 unsigned int first_insn_sizes[2];
1317 /* For relaxable macros, insns[0] is the number of instructions for the
1318 first alternative and insns[1] is the number of instructions for the
1321 For non-relaxable macros, both elements give the number of
1322 instructions for the macro. */
1323 unsigned int insns[2];
1325 /* The first variant frag for this macro. */
1327 } mips_macro_warning;
1329 /* Prototypes for static functions. */
1331 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1333 static void append_insn
1334 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1335 bfd_boolean expansionp);
1336 static void mips_no_prev_insn (void);
1337 static void macro_build (expressionS *, const char *, const char *, ...);
1338 static void mips16_macro_build
1339 (expressionS *, const char *, const char *, va_list *);
1340 static void load_register (int, expressionS *, int);
1341 static void macro_start (void);
1342 static void macro_end (void);
1343 static void macro (struct mips_cl_insn *ip, char *str);
1344 static void mips16_macro (struct mips_cl_insn * ip);
1345 static void mips_ip (char *str, struct mips_cl_insn * ip);
1346 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1347 static unsigned long mips16_immed_extend (offsetT, unsigned int);
1348 static void mips16_immed
1349 (const char *, unsigned int, int, bfd_reloc_code_real_type, offsetT,
1350 unsigned int, unsigned long *);
1351 static size_t my_getSmallExpression
1352 (expressionS *, bfd_reloc_code_real_type *, char *);
1353 static void my_getExpression (expressionS *, char *);
1354 static void s_align (int);
1355 static void s_change_sec (int);
1356 static void s_change_section (int);
1357 static void s_cons (int);
1358 static void s_float_cons (int);
1359 static void s_mips_globl (int);
1360 static void s_option (int);
1361 static void s_mipsset (int);
1362 static void s_abicalls (int);
1363 static void s_cpload (int);
1364 static void s_cpsetup (int);
1365 static void s_cplocal (int);
1366 static void s_cprestore (int);
1367 static void s_cpreturn (int);
1368 static void s_dtprelword (int);
1369 static void s_dtpreldword (int);
1370 static void s_tprelword (int);
1371 static void s_tpreldword (int);
1372 static void s_gpvalue (int);
1373 static void s_gpword (int);
1374 static void s_gpdword (int);
1375 static void s_ehword (int);
1376 static void s_cpadd (int);
1377 static void s_insn (int);
1378 static void s_nan (int);
1379 static void s_module (int);
1380 static void s_mips_ent (int);
1381 static void s_mips_end (int);
1382 static void s_mips_frame (int);
1383 static void s_mips_mask (int reg_type);
1384 static void s_mips_stab (int);
1385 static void s_mips_weakext (int);
1386 static void s_mips_file (int);
1387 static void s_mips_loc (int);
1388 static bfd_boolean pic_need_relax (symbolS *);
1389 static int relaxed_branch_length (fragS *, asection *, int);
1390 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1391 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1392 static void file_mips_check_options (void);
1394 /* Table and functions used to map between CPU/ISA names, and
1395 ISA levels, and CPU numbers. */
1397 struct mips_cpu_info
1399 const char *name; /* CPU or ISA name. */
1400 int flags; /* MIPS_CPU_* flags. */
1401 int ase; /* Set of ASEs implemented by the CPU. */
1402 int isa; /* ISA level. */
1403 int cpu; /* CPU number (default CPU if ISA). */
1406 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1408 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1409 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1410 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1412 /* Command-line options. */
1413 const char *md_shortopts = "O::g::G:";
1417 OPTION_MARCH = OPTION_MD_BASE,
1449 OPTION_NO_SMARTMIPS,
1459 OPTION_NO_MICROMIPS,
1474 OPTION_M7000_HILO_FIX,
1475 OPTION_MNO_7000_HILO_FIX,
1479 OPTION_NO_FIX_RM7000,
1480 OPTION_FIX_LOONGSON2F_JUMP,
1481 OPTION_NO_FIX_LOONGSON2F_JUMP,
1482 OPTION_FIX_LOONGSON2F_NOP,
1483 OPTION_NO_FIX_LOONGSON2F_NOP,
1485 OPTION_NO_FIX_VR4120,
1487 OPTION_NO_FIX_VR4130,
1488 OPTION_FIX_CN63XXP1,
1489 OPTION_NO_FIX_CN63XXP1,
1496 OPTION_CONSTRUCT_FLOATS,
1497 OPTION_NO_CONSTRUCT_FLOATS,
1501 OPTION_RELAX_BRANCH,
1502 OPTION_NO_RELAX_BRANCH,
1503 OPTION_IGNORE_BRANCH_ISA,
1504 OPTION_NO_IGNORE_BRANCH_ISA,
1513 OPTION_SINGLE_FLOAT,
1514 OPTION_DOUBLE_FLOAT,
1527 OPTION_MVXWORKS_PIC,
1530 OPTION_NO_ODD_SPREG,
1533 OPTION_LOONGSON_MMI,
1534 OPTION_NO_LOONGSON_MMI,
1535 OPTION_LOONGSON_CAM,
1536 OPTION_NO_LOONGSON_CAM,
1537 OPTION_LOONGSON_EXT,
1538 OPTION_NO_LOONGSON_EXT,
1539 OPTION_LOONGSON_EXT2,
1540 OPTION_NO_LOONGSON_EXT2,
1544 struct option md_longopts[] =
1546 /* Options which specify architecture. */
1547 {"march", required_argument, NULL, OPTION_MARCH},
1548 {"mtune", required_argument, NULL, OPTION_MTUNE},
1549 {"mips0", no_argument, NULL, OPTION_MIPS1},
1550 {"mips1", no_argument, NULL, OPTION_MIPS1},
1551 {"mips2", no_argument, NULL, OPTION_MIPS2},
1552 {"mips3", no_argument, NULL, OPTION_MIPS3},
1553 {"mips4", no_argument, NULL, OPTION_MIPS4},
1554 {"mips5", no_argument, NULL, OPTION_MIPS5},
1555 {"mips32", no_argument, NULL, OPTION_MIPS32},
1556 {"mips64", no_argument, NULL, OPTION_MIPS64},
1557 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
1558 {"mips32r3", no_argument, NULL, OPTION_MIPS32R3},
1559 {"mips32r5", no_argument, NULL, OPTION_MIPS32R5},
1560 {"mips32r6", no_argument, NULL, OPTION_MIPS32R6},
1561 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
1562 {"mips64r3", no_argument, NULL, OPTION_MIPS64R3},
1563 {"mips64r5", no_argument, NULL, OPTION_MIPS64R5},
1564 {"mips64r6", no_argument, NULL, OPTION_MIPS64R6},
1566 /* Options which specify Application Specific Extensions (ASEs). */
1567 {"mips16", no_argument, NULL, OPTION_MIPS16},
1568 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
1569 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
1570 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
1571 {"mdmx", no_argument, NULL, OPTION_MDMX},
1572 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
1573 {"mdsp", no_argument, NULL, OPTION_DSP},
1574 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
1575 {"mmt", no_argument, NULL, OPTION_MT},
1576 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
1577 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
1578 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
1579 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
1580 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
1581 {"mdspr3", no_argument, NULL, OPTION_DSPR3},
1582 {"mno-dspr3", no_argument, NULL, OPTION_NO_DSPR3},
1583 {"meva", no_argument, NULL, OPTION_EVA},
1584 {"mno-eva", no_argument, NULL, OPTION_NO_EVA},
1585 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
1586 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
1587 {"mmcu", no_argument, NULL, OPTION_MCU},
1588 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
1589 {"mvirt", no_argument, NULL, OPTION_VIRT},
1590 {"mno-virt", no_argument, NULL, OPTION_NO_VIRT},
1591 {"mmsa", no_argument, NULL, OPTION_MSA},
1592 {"mno-msa", no_argument, NULL, OPTION_NO_MSA},
1593 {"mxpa", no_argument, NULL, OPTION_XPA},
1594 {"mno-xpa", no_argument, NULL, OPTION_NO_XPA},
1595 {"mmips16e2", no_argument, NULL, OPTION_MIPS16E2},
1596 {"mno-mips16e2", no_argument, NULL, OPTION_NO_MIPS16E2},
1597 {"mcrc", no_argument, NULL, OPTION_CRC},
1598 {"mno-crc", no_argument, NULL, OPTION_NO_CRC},
1599 {"mginv", no_argument, NULL, OPTION_GINV},
1600 {"mno-ginv", no_argument, NULL, OPTION_NO_GINV},
1601 {"mloongson-mmi", no_argument, NULL, OPTION_LOONGSON_MMI},
1602 {"mno-loongson-mmi", no_argument, NULL, OPTION_NO_LOONGSON_MMI},
1603 {"mloongson-cam", no_argument, NULL, OPTION_LOONGSON_CAM},
1604 {"mno-loongson-cam", no_argument, NULL, OPTION_NO_LOONGSON_CAM},
1605 {"mloongson-ext", no_argument, NULL, OPTION_LOONGSON_EXT},
1606 {"mno-loongson-ext", no_argument, NULL, OPTION_NO_LOONGSON_EXT},
1607 {"mloongson-ext2", no_argument, NULL, OPTION_LOONGSON_EXT2},
1608 {"mno-loongson-ext2", no_argument, NULL, OPTION_NO_LOONGSON_EXT2},
1610 /* Old-style architecture options. Don't add more of these. */
1611 {"m4650", no_argument, NULL, OPTION_M4650},
1612 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
1613 {"m4010", no_argument, NULL, OPTION_M4010},
1614 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
1615 {"m4100", no_argument, NULL, OPTION_M4100},
1616 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
1617 {"m3900", no_argument, NULL, OPTION_M3900},
1618 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
1620 /* Options which enable bug fixes. */
1621 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
1622 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1623 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1624 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
1625 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
1626 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
1627 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
1628 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
1629 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
1630 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
1631 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
1632 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
1633 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
1634 {"mfix-rm7000", no_argument, NULL, OPTION_FIX_RM7000},
1635 {"mno-fix-rm7000", no_argument, NULL, OPTION_NO_FIX_RM7000},
1636 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
1637 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
1639 /* Miscellaneous options. */
1640 {"trap", no_argument, NULL, OPTION_TRAP},
1641 {"no-break", no_argument, NULL, OPTION_TRAP},
1642 {"break", no_argument, NULL, OPTION_BREAK},
1643 {"no-trap", no_argument, NULL, OPTION_BREAK},
1644 {"EB", no_argument, NULL, OPTION_EB},
1645 {"EL", no_argument, NULL, OPTION_EL},
1646 {"mfp32", no_argument, NULL, OPTION_FP32},
1647 {"mgp32", no_argument, NULL, OPTION_GP32},
1648 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
1649 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
1650 {"mfp64", no_argument, NULL, OPTION_FP64},
1651 {"mfpxx", no_argument, NULL, OPTION_FPXX},
1652 {"mgp64", no_argument, NULL, OPTION_GP64},
1653 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
1654 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
1655 {"mignore-branch-isa", no_argument, NULL, OPTION_IGNORE_BRANCH_ISA},
1656 {"mno-ignore-branch-isa", no_argument, NULL, OPTION_NO_IGNORE_BRANCH_ISA},
1657 {"minsn32", no_argument, NULL, OPTION_INSN32},
1658 {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32},
1659 {"mshared", no_argument, NULL, OPTION_MSHARED},
1660 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
1661 {"msym32", no_argument, NULL, OPTION_MSYM32},
1662 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
1663 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
1664 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
1665 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
1666 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
1667 {"modd-spreg", no_argument, NULL, OPTION_ODD_SPREG},
1668 {"mno-odd-spreg", no_argument, NULL, OPTION_NO_ODD_SPREG},
1670 /* Strictly speaking this next option is ELF specific,
1671 but we allow it for other ports as well in order to
1672 make testing easier. */
1673 {"32", no_argument, NULL, OPTION_32},
1675 /* ELF-specific options. */
1676 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
1677 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
1678 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
1679 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
1680 {"xgot", no_argument, NULL, OPTION_XGOT},
1681 {"mabi", required_argument, NULL, OPTION_MABI},
1682 {"n32", no_argument, NULL, OPTION_N32},
1683 {"64", no_argument, NULL, OPTION_64},
1684 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
1685 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
1686 {"mpdr", no_argument, NULL, OPTION_PDR},
1687 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
1688 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
1689 {"mnan", required_argument, NULL, OPTION_NAN},
1691 {NULL, no_argument, NULL, 0}
1693 size_t md_longopts_size = sizeof (md_longopts);
1695 /* Information about either an Application Specific Extension or an
1696 optional architecture feature that, for simplicity, we treat in the
1697 same way as an ASE. */
1700 /* The name of the ASE, used in both the command-line and .set options. */
1703 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1704 and 64-bit architectures, the flags here refer to the subset that
1705 is available on both. */
1708 /* The ASE_* flag used for instructions that are available on 64-bit
1709 architectures but that are not included in FLAGS. */
1710 unsigned int flags64;
1712 /* The command-line options that turn the ASE on and off. */
1716 /* The minimum required architecture revisions for MIPS32, MIPS64,
1717 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1720 int micromips32_rev;
1721 int micromips64_rev;
1723 /* The architecture where the ASE was removed or -1 if the extension has not
1728 /* A table of all supported ASEs. */
1729 static const struct mips_ase mips_ases[] = {
1730 { "dsp", ASE_DSP, ASE_DSP64,
1731 OPTION_DSP, OPTION_NO_DSP,
1735 { "dspr2", ASE_DSP | ASE_DSPR2, 0,
1736 OPTION_DSPR2, OPTION_NO_DSPR2,
1740 { "dspr3", ASE_DSP | ASE_DSPR2 | ASE_DSPR3, 0,
1741 OPTION_DSPR3, OPTION_NO_DSPR3,
1745 { "eva", ASE_EVA, 0,
1746 OPTION_EVA, OPTION_NO_EVA,
1750 { "mcu", ASE_MCU, 0,
1751 OPTION_MCU, OPTION_NO_MCU,
1755 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1756 { "mdmx", ASE_MDMX, 0,
1757 OPTION_MDMX, OPTION_NO_MDMX,
1761 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1762 { "mips3d", ASE_MIPS3D, 0,
1763 OPTION_MIPS3D, OPTION_NO_MIPS3D,
1768 OPTION_MT, OPTION_NO_MT,
1772 { "smartmips", ASE_SMARTMIPS, 0,
1773 OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS,
1777 { "virt", ASE_VIRT, ASE_VIRT64,
1778 OPTION_VIRT, OPTION_NO_VIRT,
1782 { "msa", ASE_MSA, ASE_MSA64,
1783 OPTION_MSA, OPTION_NO_MSA,
1787 { "xpa", ASE_XPA, 0,
1788 OPTION_XPA, OPTION_NO_XPA,
1792 { "mips16e2", ASE_MIPS16E2, 0,
1793 OPTION_MIPS16E2, OPTION_NO_MIPS16E2,
1797 { "crc", ASE_CRC, ASE_CRC64,
1798 OPTION_CRC, OPTION_NO_CRC,
1802 { "ginv", ASE_GINV, 0,
1803 OPTION_GINV, OPTION_NO_GINV,
1807 { "loongson-mmi", ASE_LOONGSON_MMI, 0,
1808 OPTION_LOONGSON_MMI, OPTION_NO_LOONGSON_MMI,
1812 { "loongson-cam", ASE_LOONGSON_CAM, 0,
1813 OPTION_LOONGSON_CAM, OPTION_NO_LOONGSON_CAM,
1817 { "loongson-ext", ASE_LOONGSON_EXT, 0,
1818 OPTION_LOONGSON_EXT, OPTION_NO_LOONGSON_EXT,
1822 { "loongson-ext2", ASE_LOONGSON_EXT | ASE_LOONGSON_EXT2, 0,
1823 OPTION_LOONGSON_EXT2, OPTION_NO_LOONGSON_EXT2,
1828 /* The set of ASEs that require -mfp64. */
1829 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
1831 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1832 static const unsigned int mips_ase_groups[] = {
1833 ASE_DSP | ASE_DSPR2 | ASE_DSPR3,
1834 ASE_LOONGSON_EXT | ASE_LOONGSON_EXT2
1839 The following pseudo-ops from the Kane and Heinrich MIPS book
1840 should be defined here, but are currently unsupported: .alias,
1841 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1843 The following pseudo-ops from the Kane and Heinrich MIPS book are
1844 specific to the type of debugging information being generated, and
1845 should be defined by the object format: .aent, .begin, .bend,
1846 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1849 The following pseudo-ops from the Kane and Heinrich MIPS book are
1850 not MIPS CPU specific, but are also not specific to the object file
1851 format. This file is probably the best place to define them, but
1852 they are not currently supported: .asm0, .endr, .lab, .struct. */
1854 static const pseudo_typeS mips_pseudo_table[] =
1856 /* MIPS specific pseudo-ops. */
1857 {"option", s_option, 0},
1858 {"set", s_mipsset, 0},
1859 {"rdata", s_change_sec, 'r'},
1860 {"sdata", s_change_sec, 's'},
1861 {"livereg", s_ignore, 0},
1862 {"abicalls", s_abicalls, 0},
1863 {"cpload", s_cpload, 0},
1864 {"cpsetup", s_cpsetup, 0},
1865 {"cplocal", s_cplocal, 0},
1866 {"cprestore", s_cprestore, 0},
1867 {"cpreturn", s_cpreturn, 0},
1868 {"dtprelword", s_dtprelword, 0},
1869 {"dtpreldword", s_dtpreldword, 0},
1870 {"tprelword", s_tprelword, 0},
1871 {"tpreldword", s_tpreldword, 0},
1872 {"gpvalue", s_gpvalue, 0},
1873 {"gpword", s_gpword, 0},
1874 {"gpdword", s_gpdword, 0},
1875 {"ehword", s_ehword, 0},
1876 {"cpadd", s_cpadd, 0},
1877 {"insn", s_insn, 0},
1879 {"module", s_module, 0},
1881 /* Relatively generic pseudo-ops that happen to be used on MIPS
1883 {"asciiz", stringer, 8 + 1},
1884 {"bss", s_change_sec, 'b'},
1886 {"half", s_cons, 1},
1887 {"dword", s_cons, 3},
1888 {"weakext", s_mips_weakext, 0},
1889 {"origin", s_org, 0},
1890 {"repeat", s_rept, 0},
1892 /* For MIPS this is non-standard, but we define it for consistency. */
1893 {"sbss", s_change_sec, 'B'},
1895 /* These pseudo-ops are defined in read.c, but must be overridden
1896 here for one reason or another. */
1897 {"align", s_align, 0},
1898 {"byte", s_cons, 0},
1899 {"data", s_change_sec, 'd'},
1900 {"double", s_float_cons, 'd'},
1901 {"float", s_float_cons, 'f'},
1902 {"globl", s_mips_globl, 0},
1903 {"global", s_mips_globl, 0},
1904 {"hword", s_cons, 1},
1906 {"long", s_cons, 2},
1907 {"octa", s_cons, 4},
1908 {"quad", s_cons, 3},
1909 {"section", s_change_section, 0},
1910 {"short", s_cons, 1},
1911 {"single", s_float_cons, 'f'},
1912 {"stabd", s_mips_stab, 'd'},
1913 {"stabn", s_mips_stab, 'n'},
1914 {"stabs", s_mips_stab, 's'},
1915 {"text", s_change_sec, 't'},
1916 {"word", s_cons, 2},
1918 { "extern", ecoff_directive_extern, 0},
1923 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1925 /* These pseudo-ops should be defined by the object file format.
1926 However, a.out doesn't support them, so we have versions here. */
1927 {"aent", s_mips_ent, 1},
1928 {"bgnb", s_ignore, 0},
1929 {"end", s_mips_end, 0},
1930 {"endb", s_ignore, 0},
1931 {"ent", s_mips_ent, 0},
1932 {"file", s_mips_file, 0},
1933 {"fmask", s_mips_mask, 'F'},
1934 {"frame", s_mips_frame, 0},
1935 {"loc", s_mips_loc, 0},
1936 {"mask", s_mips_mask, 'R'},
1937 {"verstamp", s_ignore, 0},
1941 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1942 purpose of the `.dc.a' internal pseudo-op. */
1945 mips_address_bytes (void)
1947 file_mips_check_options ();
1948 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1951 extern void pop_insert (const pseudo_typeS *);
1954 mips_pop_insert (void)
1956 pop_insert (mips_pseudo_table);
1957 if (! ECOFF_DEBUGGING)
1958 pop_insert (mips_nonecoff_pseudo_table);
1961 /* Symbols labelling the current insn. */
1963 struct insn_label_list
1965 struct insn_label_list *next;
1969 static struct insn_label_list *free_insn_labels;
1970 #define label_list tc_segment_info_data.labels
1972 static void mips_clear_insn_labels (void);
1973 static void mips_mark_labels (void);
1974 static void mips_compressed_mark_labels (void);
1977 mips_clear_insn_labels (void)
1979 struct insn_label_list **pl;
1980 segment_info_type *si;
1984 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1987 si = seg_info (now_seg);
1988 *pl = si->label_list;
1989 si->label_list = NULL;
1993 /* Mark instruction labels in MIPS16/microMIPS mode. */
1996 mips_mark_labels (void)
1998 if (HAVE_CODE_COMPRESSION)
1999 mips_compressed_mark_labels ();
2002 static char *expr_end;
2004 /* An expression in a macro instruction. This is set by mips_ip and
2005 mips16_ip and when populated is always an O_constant. */
2007 static expressionS imm_expr;
2009 /* The relocatable field in an instruction and the relocs associated
2010 with it. These variables are used for instructions like LUI and
2011 JAL as well as true offsets. They are also used for address
2012 operands in macros. */
2014 static expressionS offset_expr;
2015 static bfd_reloc_code_real_type offset_reloc[3]
2016 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2018 /* This is set to the resulting size of the instruction to be produced
2019 by mips16_ip if an explicit extension is used or by mips_ip if an
2020 explicit size is supplied. */
2022 static unsigned int forced_insn_length;
2024 /* True if we are assembling an instruction. All dot symbols defined during
2025 this time should be treated as code labels. */
2027 static bfd_boolean mips_assembling_insn;
2029 /* The pdr segment for per procedure frame/regmask info. Not used for
2032 static segT pdr_seg;
2034 /* The default target format to use. */
2036 #if defined (TE_FreeBSD)
2037 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
2038 #elif defined (TE_TMIPS)
2039 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
2041 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
2045 mips_target_format (void)
2047 switch (OUTPUT_FLAVOR)
2049 case bfd_target_elf_flavour:
2051 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
2052 return (target_big_endian
2053 ? "elf32-bigmips-vxworks"
2054 : "elf32-littlemips-vxworks");
2056 return (target_big_endian
2057 ? (HAVE_64BIT_OBJECTS
2058 ? ELF_TARGET ("elf64-", "big")
2060 ? ELF_TARGET ("elf32-n", "big")
2061 : ELF_TARGET ("elf32-", "big")))
2062 : (HAVE_64BIT_OBJECTS
2063 ? ELF_TARGET ("elf64-", "little")
2065 ? ELF_TARGET ("elf32-n", "little")
2066 : ELF_TARGET ("elf32-", "little"))));
2073 /* Return the ISA revision that is currently in use, or 0 if we are
2074 generating code for MIPS V or below. */
2079 if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2)
2082 if (mips_opts.isa == ISA_MIPS32R3 || mips_opts.isa == ISA_MIPS64R3)
2085 if (mips_opts.isa == ISA_MIPS32R5 || mips_opts.isa == ISA_MIPS64R5)
2088 if (mips_opts.isa == ISA_MIPS32R6 || mips_opts.isa == ISA_MIPS64R6)
2091 /* microMIPS implies revision 2 or above. */
2092 if (mips_opts.micromips)
2095 if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64)
2101 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
2104 mips_ase_mask (unsigned int flags)
2108 for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++)
2109 if (flags & mips_ase_groups[i])
2110 flags |= mips_ase_groups[i];
2114 /* Check whether the current ISA supports ASE. Issue a warning if
2118 mips_check_isa_supports_ase (const struct mips_ase *ase)
2122 static unsigned int warned_isa;
2123 static unsigned int warned_fp32;
2125 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
2126 min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev;
2128 min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev;
2129 if ((min_rev < 0 || mips_isa_rev () < min_rev)
2130 && (warned_isa & ase->flags) != ase->flags)
2132 warned_isa |= ase->flags;
2133 base = mips_opts.micromips ? "microMIPS" : "MIPS";
2134 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
2136 as_warn (_("the %d-bit %s architecture does not support the"
2137 " `%s' extension"), size, base, ase->name);
2139 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
2140 ase->name, base, size, min_rev);
2142 else if ((ase->rem_rev > 0 && mips_isa_rev () >= ase->rem_rev)
2143 && (warned_isa & ase->flags) != ase->flags)
2145 warned_isa |= ase->flags;
2146 base = mips_opts.micromips ? "microMIPS" : "MIPS";
2147 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
2148 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2149 ase->name, base, size, ase->rem_rev);
2152 if ((ase->flags & FP64_ASES)
2153 && mips_opts.fp != 64
2154 && (warned_fp32 & ase->flags) != ase->flags)
2156 warned_fp32 |= ase->flags;
2157 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase->name);
2161 /* Check all enabled ASEs to see whether they are supported by the
2162 chosen architecture. */
2165 mips_check_isa_supports_ases (void)
2167 unsigned int i, mask;
2169 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2171 mask = mips_ase_mask (mips_ases[i].flags);
2172 if ((mips_opts.ase & mask) == mips_ases[i].flags)
2173 mips_check_isa_supports_ase (&mips_ases[i]);
2177 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2178 that were affected. */
2181 mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts,
2182 bfd_boolean enabled_p)
2186 mask = mips_ase_mask (ase->flags);
2189 /* Clear combination ASE flags, which need to be recalculated based on
2190 updated regular ASE settings. */
2191 opts->ase &= ~(ASE_MIPS16E2_MT | ASE_XPA_VIRT);
2194 opts->ase |= ase->flags;
2196 /* The Virtualization ASE has eXtended Physical Addressing (XPA)
2197 instructions which are only valid when both ASEs are enabled.
2198 This sets the ASE_XPA_VIRT flag when both ASEs are present. */
2199 if ((opts->ase & (ASE_XPA | ASE_VIRT)) == (ASE_XPA | ASE_VIRT))
2201 opts->ase |= ASE_XPA_VIRT;
2202 mask |= ASE_XPA_VIRT;
2204 if ((opts->ase & (ASE_MIPS16E2 | ASE_MT)) == (ASE_MIPS16E2 | ASE_MT))
2206 opts->ase |= ASE_MIPS16E2_MT;
2207 mask |= ASE_MIPS16E2_MT;
2213 /* Return the ASE called NAME, or null if none. */
2215 static const struct mips_ase *
2216 mips_lookup_ase (const char *name)
2220 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2221 if (strcmp (name, mips_ases[i].name) == 0)
2222 return &mips_ases[i];
2226 /* Return the length of a microMIPS instruction in bytes. If bits of
2227 the mask beyond the low 16 are 0, then it is a 16-bit instruction,
2228 otherwise it is a 32-bit instruction. */
2230 static inline unsigned int
2231 micromips_insn_length (const struct mips_opcode *mo)
2233 return mips_opcode_32bit_p (mo) ? 4 : 2;
2236 /* Return the length of MIPS16 instruction OPCODE. */
2238 static inline unsigned int
2239 mips16_opcode_length (unsigned long opcode)
2241 return (opcode >> 16) == 0 ? 2 : 4;
2244 /* Return the length of instruction INSN. */
2246 static inline unsigned int
2247 insn_length (const struct mips_cl_insn *insn)
2249 if (mips_opts.micromips)
2250 return micromips_insn_length (insn->insn_mo);
2251 else if (mips_opts.mips16)
2252 return mips16_opcode_length (insn->insn_opcode);
2257 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2260 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
2265 insn->insn_opcode = mo->match;
2268 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2269 insn->fixp[i] = NULL;
2270 insn->fixed_p = (mips_opts.noreorder > 0);
2271 insn->noreorder_p = (mips_opts.noreorder > 0);
2272 insn->mips16_absolute_jump_p = 0;
2273 insn->complete_p = 0;
2274 insn->cleared_p = 0;
2277 /* Get a list of all the operands in INSN. */
2279 static const struct mips_operand_array *
2280 insn_operands (const struct mips_cl_insn *insn)
2282 if (insn->insn_mo >= &mips_opcodes[0]
2283 && insn->insn_mo < &mips_opcodes[NUMOPCODES])
2284 return &mips_operands[insn->insn_mo - &mips_opcodes[0]];
2286 if (insn->insn_mo >= &mips16_opcodes[0]
2287 && insn->insn_mo < &mips16_opcodes[bfd_mips16_num_opcodes])
2288 return &mips16_operands[insn->insn_mo - &mips16_opcodes[0]];
2290 if (insn->insn_mo >= µmips_opcodes[0]
2291 && insn->insn_mo < µmips_opcodes[bfd_micromips_num_opcodes])
2292 return µmips_operands[insn->insn_mo - µmips_opcodes[0]];
2297 /* Get a description of operand OPNO of INSN. */
2299 static const struct mips_operand *
2300 insn_opno (const struct mips_cl_insn *insn, unsigned opno)
2302 const struct mips_operand_array *operands;
2304 operands = insn_operands (insn);
2305 if (opno >= MAX_OPERANDS || !operands->operand[opno])
2307 return operands->operand[opno];
2310 /* Install UVAL as the value of OPERAND in INSN. */
2313 insn_insert_operand (struct mips_cl_insn *insn,
2314 const struct mips_operand *operand, unsigned int uval)
2316 if (mips_opts.mips16
2317 && operand->type == OP_INT && operand->lsb == 0
2318 && mips_opcode_32bit_p (insn->insn_mo))
2319 insn->insn_opcode |= mips16_immed_extend (uval, operand->size);
2321 insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval);
2324 /* Extract the value of OPERAND from INSN. */
2326 static inline unsigned
2327 insn_extract_operand (const struct mips_cl_insn *insn,
2328 const struct mips_operand *operand)
2330 return mips_extract_operand (operand, insn->insn_opcode);
2333 /* Record the current MIPS16/microMIPS mode in now_seg. */
2336 mips_record_compressed_mode (void)
2338 segment_info_type *si;
2340 si = seg_info (now_seg);
2341 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
2342 si->tc_segment_info_data.mips16 = mips_opts.mips16;
2343 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
2344 si->tc_segment_info_data.micromips = mips_opts.micromips;
2347 /* Read a standard MIPS instruction from BUF. */
2349 static unsigned long
2350 read_insn (char *buf)
2352 if (target_big_endian)
2353 return bfd_getb32 ((bfd_byte *) buf);
2355 return bfd_getl32 ((bfd_byte *) buf);
2358 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2362 write_insn (char *buf, unsigned int insn)
2364 md_number_to_chars (buf, insn, 4);
2368 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2369 has length LENGTH. */
2371 static unsigned long
2372 read_compressed_insn (char *buf, unsigned int length)
2378 for (i = 0; i < length; i += 2)
2381 if (target_big_endian)
2382 insn |= bfd_getb16 ((char *) buf);
2384 insn |= bfd_getl16 ((char *) buf);
2390 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2391 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2394 write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
2398 for (i = 0; i < length; i += 2)
2399 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
2400 return buf + length;
2403 /* Install INSN at the location specified by its "frag" and "where" fields. */
2406 install_insn (const struct mips_cl_insn *insn)
2408 char *f = insn->frag->fr_literal + insn->where;
2409 if (HAVE_CODE_COMPRESSION)
2410 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
2412 write_insn (f, insn->insn_opcode);
2413 mips_record_compressed_mode ();
2416 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2417 and install the opcode in the new location. */
2420 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
2425 insn->where = where;
2426 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2427 if (insn->fixp[i] != NULL)
2429 insn->fixp[i]->fx_frag = frag;
2430 insn->fixp[i]->fx_where = where;
2432 install_insn (insn);
2435 /* Add INSN to the end of the output. */
2438 add_fixed_insn (struct mips_cl_insn *insn)
2440 char *f = frag_more (insn_length (insn));
2441 move_insn (insn, frag_now, f - frag_now->fr_literal);
2444 /* Start a variant frag and move INSN to the start of the variant part,
2445 marking it as fixed. The other arguments are as for frag_var. */
2448 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
2449 relax_substateT subtype, symbolS *symbol, offsetT offset)
2451 frag_grow (max_chars);
2452 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
2454 frag_var (rs_machine_dependent, max_chars, var,
2455 subtype, symbol, offset, NULL);
2458 /* Insert N copies of INSN into the history buffer, starting at
2459 position FIRST. Neither FIRST nor N need to be clipped. */
2462 insert_into_history (unsigned int first, unsigned int n,
2463 const struct mips_cl_insn *insn)
2465 if (mips_relax.sequence != 2)
2469 for (i = ARRAY_SIZE (history); i-- > first;)
2471 history[i] = history[i - n];
2477 /* Clear the error in insn_error. */
2480 clear_insn_error (void)
2482 memset (&insn_error, 0, sizeof (insn_error));
2485 /* Possibly record error message MSG for the current instruction.
2486 If the error is about a particular argument, ARGNUM is the 1-based
2487 number of that argument, otherwise it is 0. FORMAT is the format
2488 of MSG. Return true if MSG was used, false if the current message
2492 set_insn_error_format (int argnum, enum mips_insn_error_format format,
2497 /* Give priority to errors against specific arguments, and to
2498 the first whole-instruction message. */
2504 /* Keep insn_error if it is against a later argument. */
2505 if (argnum < insn_error.min_argnum)
2508 /* If both errors are against the same argument but are different,
2509 give up on reporting a specific error for this argument.
2510 See the comment about mips_insn_error for details. */
2511 if (argnum == insn_error.min_argnum
2513 && strcmp (insn_error.msg, msg) != 0)
2516 insn_error.min_argnum += 1;
2520 insn_error.min_argnum = argnum;
2521 insn_error.format = format;
2522 insn_error.msg = msg;
2526 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2527 as for set_insn_error_format. */
2530 set_insn_error (int argnum, const char *msg)
2532 set_insn_error_format (argnum, ERR_FMT_PLAIN, msg);
2535 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2536 as for set_insn_error_format. */
2539 set_insn_error_i (int argnum, const char *msg, int i)
2541 if (set_insn_error_format (argnum, ERR_FMT_I, msg))
2545 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2546 are as for set_insn_error_format. */
2549 set_insn_error_ss (int argnum, const char *msg, const char *s1, const char *s2)
2551 if (set_insn_error_format (argnum, ERR_FMT_SS, msg))
2553 insn_error.u.ss[0] = s1;
2554 insn_error.u.ss[1] = s2;
2558 /* Report the error in insn_error, which is against assembly code STR. */
2561 report_insn_error (const char *str)
2563 const char *msg = concat (insn_error.msg, " `%s'", NULL);
2565 switch (insn_error.format)
2572 as_bad (msg, insn_error.u.i, str);
2576 as_bad (msg, insn_error.u.ss[0], insn_error.u.ss[1], str);
2580 free ((char *) msg);
2583 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2584 the idea is to make it obvious at a glance that each errata is
2588 init_vr4120_conflicts (void)
2590 #define CONFLICT(FIRST, SECOND) \
2591 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2593 /* Errata 21 - [D]DIV[U] after [D]MACC */
2594 CONFLICT (MACC, DIV);
2595 CONFLICT (DMACC, DIV);
2597 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2598 CONFLICT (DMULT, DMULT);
2599 CONFLICT (DMULT, DMACC);
2600 CONFLICT (DMACC, DMULT);
2601 CONFLICT (DMACC, DMACC);
2603 /* Errata 24 - MT{LO,HI} after [D]MACC */
2604 CONFLICT (MACC, MTHILO);
2605 CONFLICT (DMACC, MTHILO);
2607 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2608 instruction is executed immediately after a MACC or DMACC
2609 instruction, the result of [either instruction] is incorrect." */
2610 CONFLICT (MACC, MULT);
2611 CONFLICT (MACC, DMULT);
2612 CONFLICT (DMACC, MULT);
2613 CONFLICT (DMACC, DMULT);
2615 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2616 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2617 DDIV or DDIVU instruction, the result of the MACC or
2618 DMACC instruction is incorrect.". */
2619 CONFLICT (DMULT, MACC);
2620 CONFLICT (DMULT, DMACC);
2621 CONFLICT (DIV, MACC);
2622 CONFLICT (DIV, DMACC);
2632 #define RNUM_MASK 0x00000ff
2633 #define RTYPE_MASK 0x0ffff00
2634 #define RTYPE_NUM 0x0000100
2635 #define RTYPE_FPU 0x0000200
2636 #define RTYPE_FCC 0x0000400
2637 #define RTYPE_VEC 0x0000800
2638 #define RTYPE_GP 0x0001000
2639 #define RTYPE_CP0 0x0002000
2640 #define RTYPE_PC 0x0004000
2641 #define RTYPE_ACC 0x0008000
2642 #define RTYPE_CCC 0x0010000
2643 #define RTYPE_VI 0x0020000
2644 #define RTYPE_VF 0x0040000
2645 #define RTYPE_R5900_I 0x0080000
2646 #define RTYPE_R5900_Q 0x0100000
2647 #define RTYPE_R5900_R 0x0200000
2648 #define RTYPE_R5900_ACC 0x0400000
2649 #define RTYPE_MSA 0x0800000
2650 #define RWARN 0x8000000
2652 #define GENERIC_REGISTER_NUMBERS \
2653 {"$0", RTYPE_NUM | 0}, \
2654 {"$1", RTYPE_NUM | 1}, \
2655 {"$2", RTYPE_NUM | 2}, \
2656 {"$3", RTYPE_NUM | 3}, \
2657 {"$4", RTYPE_NUM | 4}, \
2658 {"$5", RTYPE_NUM | 5}, \
2659 {"$6", RTYPE_NUM | 6}, \
2660 {"$7", RTYPE_NUM | 7}, \
2661 {"$8", RTYPE_NUM | 8}, \
2662 {"$9", RTYPE_NUM | 9}, \
2663 {"$10", RTYPE_NUM | 10}, \
2664 {"$11", RTYPE_NUM | 11}, \
2665 {"$12", RTYPE_NUM | 12}, \
2666 {"$13", RTYPE_NUM | 13}, \
2667 {"$14", RTYPE_NUM | 14}, \
2668 {"$15", RTYPE_NUM | 15}, \
2669 {"$16", RTYPE_NUM | 16}, \
2670 {"$17", RTYPE_NUM | 17}, \
2671 {"$18", RTYPE_NUM | 18}, \
2672 {"$19", RTYPE_NUM | 19}, \
2673 {"$20", RTYPE_NUM | 20}, \
2674 {"$21", RTYPE_NUM | 21}, \
2675 {"$22", RTYPE_NUM | 22}, \
2676 {"$23", RTYPE_NUM | 23}, \
2677 {"$24", RTYPE_NUM | 24}, \
2678 {"$25", RTYPE_NUM | 25}, \
2679 {"$26", RTYPE_NUM | 26}, \
2680 {"$27", RTYPE_NUM | 27}, \
2681 {"$28", RTYPE_NUM | 28}, \
2682 {"$29", RTYPE_NUM | 29}, \
2683 {"$30", RTYPE_NUM | 30}, \
2684 {"$31", RTYPE_NUM | 31}
2686 #define FPU_REGISTER_NAMES \
2687 {"$f0", RTYPE_FPU | 0}, \
2688 {"$f1", RTYPE_FPU | 1}, \
2689 {"$f2", RTYPE_FPU | 2}, \
2690 {"$f3", RTYPE_FPU | 3}, \
2691 {"$f4", RTYPE_FPU | 4}, \
2692 {"$f5", RTYPE_FPU | 5}, \
2693 {"$f6", RTYPE_FPU | 6}, \
2694 {"$f7", RTYPE_FPU | 7}, \
2695 {"$f8", RTYPE_FPU | 8}, \
2696 {"$f9", RTYPE_FPU | 9}, \
2697 {"$f10", RTYPE_FPU | 10}, \
2698 {"$f11", RTYPE_FPU | 11}, \
2699 {"$f12", RTYPE_FPU | 12}, \
2700 {"$f13", RTYPE_FPU | 13}, \
2701 {"$f14", RTYPE_FPU | 14}, \
2702 {"$f15", RTYPE_FPU | 15}, \
2703 {"$f16", RTYPE_FPU | 16}, \
2704 {"$f17", RTYPE_FPU | 17}, \
2705 {"$f18", RTYPE_FPU | 18}, \
2706 {"$f19", RTYPE_FPU | 19}, \
2707 {"$f20", RTYPE_FPU | 20}, \
2708 {"$f21", RTYPE_FPU | 21}, \
2709 {"$f22", RTYPE_FPU | 22}, \
2710 {"$f23", RTYPE_FPU | 23}, \
2711 {"$f24", RTYPE_FPU | 24}, \
2712 {"$f25", RTYPE_FPU | 25}, \
2713 {"$f26", RTYPE_FPU | 26}, \
2714 {"$f27", RTYPE_FPU | 27}, \
2715 {"$f28", RTYPE_FPU | 28}, \
2716 {"$f29", RTYPE_FPU | 29}, \
2717 {"$f30", RTYPE_FPU | 30}, \
2718 {"$f31", RTYPE_FPU | 31}
2720 #define FPU_CONDITION_CODE_NAMES \
2721 {"$fcc0", RTYPE_FCC | 0}, \
2722 {"$fcc1", RTYPE_FCC | 1}, \
2723 {"$fcc2", RTYPE_FCC | 2}, \
2724 {"$fcc3", RTYPE_FCC | 3}, \
2725 {"$fcc4", RTYPE_FCC | 4}, \
2726 {"$fcc5", RTYPE_FCC | 5}, \
2727 {"$fcc6", RTYPE_FCC | 6}, \
2728 {"$fcc7", RTYPE_FCC | 7}
2730 #define COPROC_CONDITION_CODE_NAMES \
2731 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2732 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2733 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2734 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2735 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2736 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2737 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2738 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2740 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2741 {"$a4", RTYPE_GP | 8}, \
2742 {"$a5", RTYPE_GP | 9}, \
2743 {"$a6", RTYPE_GP | 10}, \
2744 {"$a7", RTYPE_GP | 11}, \
2745 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2746 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2747 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2748 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2749 {"$t0", RTYPE_GP | 12}, \
2750 {"$t1", RTYPE_GP | 13}, \
2751 {"$t2", RTYPE_GP | 14}, \
2752 {"$t3", RTYPE_GP | 15}
2754 #define O32_SYMBOLIC_REGISTER_NAMES \
2755 {"$t0", RTYPE_GP | 8}, \
2756 {"$t1", RTYPE_GP | 9}, \
2757 {"$t2", RTYPE_GP | 10}, \
2758 {"$t3", RTYPE_GP | 11}, \
2759 {"$t4", RTYPE_GP | 12}, \
2760 {"$t5", RTYPE_GP | 13}, \
2761 {"$t6", RTYPE_GP | 14}, \
2762 {"$t7", RTYPE_GP | 15}, \
2763 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2764 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2765 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2766 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2768 /* Remaining symbolic register names */
2769 #define SYMBOLIC_REGISTER_NAMES \
2770 {"$zero", RTYPE_GP | 0}, \
2771 {"$at", RTYPE_GP | 1}, \
2772 {"$AT", RTYPE_GP | 1}, \
2773 {"$v0", RTYPE_GP | 2}, \
2774 {"$v1", RTYPE_GP | 3}, \
2775 {"$a0", RTYPE_GP | 4}, \
2776 {"$a1", RTYPE_GP | 5}, \
2777 {"$a2", RTYPE_GP | 6}, \
2778 {"$a3", RTYPE_GP | 7}, \
2779 {"$s0", RTYPE_GP | 16}, \
2780 {"$s1", RTYPE_GP | 17}, \
2781 {"$s2", RTYPE_GP | 18}, \
2782 {"$s3", RTYPE_GP | 19}, \
2783 {"$s4", RTYPE_GP | 20}, \
2784 {"$s5", RTYPE_GP | 21}, \
2785 {"$s6", RTYPE_GP | 22}, \
2786 {"$s7", RTYPE_GP | 23}, \
2787 {"$t8", RTYPE_GP | 24}, \
2788 {"$t9", RTYPE_GP | 25}, \
2789 {"$k0", RTYPE_GP | 26}, \
2790 {"$kt0", RTYPE_GP | 26}, \
2791 {"$k1", RTYPE_GP | 27}, \
2792 {"$kt1", RTYPE_GP | 27}, \
2793 {"$gp", RTYPE_GP | 28}, \
2794 {"$sp", RTYPE_GP | 29}, \
2795 {"$s8", RTYPE_GP | 30}, \
2796 {"$fp", RTYPE_GP | 30}, \
2797 {"$ra", RTYPE_GP | 31}
2799 #define MIPS16_SPECIAL_REGISTER_NAMES \
2800 {"$pc", RTYPE_PC | 0}
2802 #define MDMX_VECTOR_REGISTER_NAMES \
2803 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2804 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2805 {"$v2", RTYPE_VEC | 2}, \
2806 {"$v3", RTYPE_VEC | 3}, \
2807 {"$v4", RTYPE_VEC | 4}, \
2808 {"$v5", RTYPE_VEC | 5}, \
2809 {"$v6", RTYPE_VEC | 6}, \
2810 {"$v7", RTYPE_VEC | 7}, \
2811 {"$v8", RTYPE_VEC | 8}, \
2812 {"$v9", RTYPE_VEC | 9}, \
2813 {"$v10", RTYPE_VEC | 10}, \
2814 {"$v11", RTYPE_VEC | 11}, \
2815 {"$v12", RTYPE_VEC | 12}, \
2816 {"$v13", RTYPE_VEC | 13}, \
2817 {"$v14", RTYPE_VEC | 14}, \
2818 {"$v15", RTYPE_VEC | 15}, \
2819 {"$v16", RTYPE_VEC | 16}, \
2820 {"$v17", RTYPE_VEC | 17}, \
2821 {"$v18", RTYPE_VEC | 18}, \
2822 {"$v19", RTYPE_VEC | 19}, \
2823 {"$v20", RTYPE_VEC | 20}, \
2824 {"$v21", RTYPE_VEC | 21}, \
2825 {"$v22", RTYPE_VEC | 22}, \
2826 {"$v23", RTYPE_VEC | 23}, \
2827 {"$v24", RTYPE_VEC | 24}, \
2828 {"$v25", RTYPE_VEC | 25}, \
2829 {"$v26", RTYPE_VEC | 26}, \
2830 {"$v27", RTYPE_VEC | 27}, \
2831 {"$v28", RTYPE_VEC | 28}, \
2832 {"$v29", RTYPE_VEC | 29}, \
2833 {"$v30", RTYPE_VEC | 30}, \
2834 {"$v31", RTYPE_VEC | 31}
2836 #define R5900_I_NAMES \
2837 {"$I", RTYPE_R5900_I | 0}
2839 #define R5900_Q_NAMES \
2840 {"$Q", RTYPE_R5900_Q | 0}
2842 #define R5900_R_NAMES \
2843 {"$R", RTYPE_R5900_R | 0}
2845 #define R5900_ACC_NAMES \
2846 {"$ACC", RTYPE_R5900_ACC | 0 }
2848 #define MIPS_DSP_ACCUMULATOR_NAMES \
2849 {"$ac0", RTYPE_ACC | 0}, \
2850 {"$ac1", RTYPE_ACC | 1}, \
2851 {"$ac2", RTYPE_ACC | 2}, \
2852 {"$ac3", RTYPE_ACC | 3}
2854 static const struct regname reg_names[] = {
2855 GENERIC_REGISTER_NUMBERS,
2857 FPU_CONDITION_CODE_NAMES,
2858 COPROC_CONDITION_CODE_NAMES,
2860 /* The $txx registers depends on the abi,
2861 these will be added later into the symbol table from
2862 one of the tables below once mips_abi is set after
2863 parsing of arguments from the command line. */
2864 SYMBOLIC_REGISTER_NAMES,
2866 MIPS16_SPECIAL_REGISTER_NAMES,
2867 MDMX_VECTOR_REGISTER_NAMES,
2872 MIPS_DSP_ACCUMULATOR_NAMES,
2876 static const struct regname reg_names_o32[] = {
2877 O32_SYMBOLIC_REGISTER_NAMES,
2881 static const struct regname reg_names_n32n64[] = {
2882 N32N64_SYMBOLIC_REGISTER_NAMES,
2886 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2887 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2888 of these register symbols, return the associated vector register,
2889 otherwise return SYMVAL itself. */
2892 mips_prefer_vec_regno (unsigned int symval)
2894 if ((symval & -2) == (RTYPE_GP | 2))
2895 return RTYPE_VEC | (symval & 1);
2899 /* Return true if string [S, E) is a valid register name, storing its
2900 symbol value in *SYMVAL_PTR if so. */
2903 mips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr)
2908 /* Terminate name. */
2912 /* Look up the name. */
2913 symbol = symbol_find (s);
2916 if (!symbol || S_GET_SEGMENT (symbol) != reg_section)
2919 *symval_ptr = S_GET_VALUE (symbol);
2923 /* Return true if the string at *SPTR is a valid register name. Allow it
2924 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2927 When returning true, move *SPTR past the register, store the
2928 register's symbol value in *SYMVAL_PTR and the channel mask in
2929 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2930 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2931 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2934 mips_parse_register (char **sptr, unsigned int *symval_ptr,
2935 unsigned int *channels_ptr)
2939 unsigned int channels, symval, bit;
2941 /* Find end of name. */
2943 if (is_name_beginner (*e))
2945 while (is_part_of_name (*e))
2949 if (!mips_parse_register_1 (s, e, &symval))
2954 /* Eat characters from the end of the string that are valid
2955 channel suffixes. The preceding register must be $ACC or
2956 end with a digit, so there is no ambiguity. */
2959 for (q = "wzyx"; *q; q++, bit <<= 1)
2960 if (m > s && m[-1] == *q)
2967 || !mips_parse_register_1 (s, m, &symval)
2968 || (symval & (RTYPE_VI | RTYPE_VF | RTYPE_R5900_ACC)) == 0)
2973 *symval_ptr = symval;
2975 *channels_ptr = channels;
2979 /* Check if SPTR points at a valid register specifier according to TYPES.
2980 If so, then return 1, advance S to consume the specifier and store
2981 the register's number in REGNOP, otherwise return 0. */
2984 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2988 if (mips_parse_register (s, ®no, NULL))
2990 if (types & RTYPE_VEC)
2991 regno = mips_prefer_vec_regno (regno);
3000 as_warn (_("unrecognized register name `%s'"), *s);
3005 return regno <= RNUM_MASK;
3008 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
3009 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
3012 mips_parse_vu0_channels (char *s, unsigned int *channels)
3017 for (i = 0; i < 4; i++)
3018 if (*s == "xyzw"[i])
3020 *channels |= 1 << (3 - i);
3026 /* Token types for parsed operand lists. */
3027 enum mips_operand_token_type {
3028 /* A plain register, e.g. $f2. */
3031 /* A 4-bit XYZW channel mask. */
3034 /* A constant vector index, e.g. [1]. */
3037 /* A register vector index, e.g. [$2]. */
3040 /* A continuous range of registers, e.g. $s0-$s4. */
3043 /* A (possibly relocated) expression. */
3046 /* A floating-point value. */
3049 /* A single character. This can be '(', ')' or ',', but '(' only appears
3053 /* A doubled character, either "--" or "++". */
3056 /* The end of the operand list. */
3060 /* A parsed operand token. */
3061 struct mips_operand_token
3063 /* The type of token. */
3064 enum mips_operand_token_type type;
3067 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
3070 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
3071 unsigned int channels;
3073 /* The integer value of an OT_INTEGER_INDEX. */
3076 /* The two register symbol values involved in an OT_REG_RANGE. */
3078 unsigned int regno1;
3079 unsigned int regno2;
3082 /* The value of an OT_INTEGER. The value is represented as an
3083 expression and the relocation operators that were applied to
3084 that expression. The reloc entries are BFD_RELOC_UNUSED if no
3085 relocation operators were used. */
3088 bfd_reloc_code_real_type relocs[3];
3091 /* The binary data for an OT_FLOAT constant, and the number of bytes
3094 unsigned char data[8];
3098 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
3103 /* An obstack used to construct lists of mips_operand_tokens. */
3104 static struct obstack mips_operand_tokens;
3106 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
3109 mips_add_token (struct mips_operand_token *token,
3110 enum mips_operand_token_type type)
3113 obstack_grow (&mips_operand_tokens, token, sizeof (*token));
3116 /* Check whether S is '(' followed by a register name. Add OT_CHAR
3117 and OT_REG tokens for them if so, and return a pointer to the first
3118 unconsumed character. Return null otherwise. */
3121 mips_parse_base_start (char *s)
3123 struct mips_operand_token token;
3124 unsigned int regno, channels;
3125 bfd_boolean decrement_p;
3131 SKIP_SPACE_TABS (s);
3133 /* Only match "--" as part of a base expression. In other contexts "--X"
3134 is a double negative. */
3135 decrement_p = (s[0] == '-' && s[1] == '-');
3139 SKIP_SPACE_TABS (s);
3142 /* Allow a channel specifier because that leads to better error messages
3143 than treating something like "$vf0x++" as an expression. */
3144 if (!mips_parse_register (&s, ®no, &channels))
3148 mips_add_token (&token, OT_CHAR);
3153 mips_add_token (&token, OT_DOUBLE_CHAR);
3156 token.u.regno = regno;
3157 mips_add_token (&token, OT_REG);
3161 token.u.channels = channels;
3162 mips_add_token (&token, OT_CHANNELS);
3165 /* For consistency, only match "++" as part of base expressions too. */
3166 SKIP_SPACE_TABS (s);
3167 if (s[0] == '+' && s[1] == '+')
3171 mips_add_token (&token, OT_DOUBLE_CHAR);
3177 /* Parse one or more tokens from S. Return a pointer to the first
3178 unconsumed character on success. Return null if an error was found
3179 and store the error text in insn_error. FLOAT_FORMAT is as for
3180 mips_parse_arguments. */
3183 mips_parse_argument_token (char *s, char float_format)
3185 char *end, *save_in;
3187 unsigned int regno1, regno2, channels;
3188 struct mips_operand_token token;
3190 /* First look for "($reg", since we want to treat that as an
3191 OT_CHAR and OT_REG rather than an expression. */
3192 end = mips_parse_base_start (s);
3196 /* Handle other characters that end up as OT_CHARs. */
3197 if (*s == ')' || *s == ',')
3200 mips_add_token (&token, OT_CHAR);
3205 /* Handle tokens that start with a register. */
3206 if (mips_parse_register (&s, ®no1, &channels))
3210 /* A register and a VU0 channel suffix. */
3211 token.u.regno = regno1;
3212 mips_add_token (&token, OT_REG);
3214 token.u.channels = channels;
3215 mips_add_token (&token, OT_CHANNELS);
3219 SKIP_SPACE_TABS (s);
3222 /* A register range. */
3224 SKIP_SPACE_TABS (s);
3225 if (!mips_parse_register (&s, ®no2, NULL))
3227 set_insn_error (0, _("invalid register range"));
3231 token.u.reg_range.regno1 = regno1;
3232 token.u.reg_range.regno2 = regno2;
3233 mips_add_token (&token, OT_REG_RANGE);
3237 /* Add the register itself. */
3238 token.u.regno = regno1;
3239 mips_add_token (&token, OT_REG);
3241 /* Check for a vector index. */
3245 SKIP_SPACE_TABS (s);
3246 if (mips_parse_register (&s, &token.u.regno, NULL))
3247 mips_add_token (&token, OT_REG_INDEX);
3250 expressionS element;
3252 my_getExpression (&element, s);
3253 if (element.X_op != O_constant)
3255 set_insn_error (0, _("vector element must be constant"));
3259 token.u.index = element.X_add_number;
3260 mips_add_token (&token, OT_INTEGER_INDEX);
3262 SKIP_SPACE_TABS (s);
3265 set_insn_error (0, _("missing `]'"));
3275 /* First try to treat expressions as floats. */
3276 save_in = input_line_pointer;
3277 input_line_pointer = s;
3278 err = md_atof (float_format, (char *) token.u.flt.data,
3279 &token.u.flt.length);
3280 end = input_line_pointer;
3281 input_line_pointer = save_in;
3284 set_insn_error (0, err);
3289 mips_add_token (&token, OT_FLOAT);
3294 /* Treat everything else as an integer expression. */
3295 token.u.integer.relocs[0] = BFD_RELOC_UNUSED;
3296 token.u.integer.relocs[1] = BFD_RELOC_UNUSED;
3297 token.u.integer.relocs[2] = BFD_RELOC_UNUSED;
3298 my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s);
3300 mips_add_token (&token, OT_INTEGER);
3304 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3305 if expressions should be treated as 32-bit floating-point constants,
3306 'd' if they should be treated as 64-bit floating-point constants,
3307 or 0 if they should be treated as integer expressions (the usual case).
3309 Return a list of tokens on success, otherwise return 0. The caller
3310 must obstack_free the list after use. */
3312 static struct mips_operand_token *
3313 mips_parse_arguments (char *s, char float_format)
3315 struct mips_operand_token token;
3317 SKIP_SPACE_TABS (s);
3320 s = mips_parse_argument_token (s, float_format);
3323 obstack_free (&mips_operand_tokens,
3324 obstack_finish (&mips_operand_tokens));
3327 SKIP_SPACE_TABS (s);
3329 mips_add_token (&token, OT_END);
3330 return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens);
3333 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3334 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3337 is_opcode_valid (const struct mips_opcode *mo)
3339 int isa = mips_opts.isa;
3340 int ase = mips_opts.ase;
3344 if (ISA_HAS_64BIT_REGS (isa))
3345 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
3346 if ((ase & mips_ases[i].flags) == mips_ases[i].flags)
3347 ase |= mips_ases[i].flags64;
3349 if (!opcode_is_member (mo, isa, ase, mips_opts.arch))
3352 /* Check whether the instruction or macro requires single-precision or
3353 double-precision floating-point support. Note that this information is
3354 stored differently in the opcode table for insns and macros. */
3355 if (mo->pinfo == INSN_MACRO)
3357 fp_s = mo->pinfo2 & INSN2_M_FP_S;
3358 fp_d = mo->pinfo2 & INSN2_M_FP_D;
3362 fp_s = mo->pinfo & FP_S;
3363 fp_d = mo->pinfo & FP_D;
3366 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
3369 if (fp_s && mips_opts.soft_float)
3375 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3376 selected ISA and architecture. */
3379 is_opcode_valid_16 (const struct mips_opcode *mo)
3381 int isa = mips_opts.isa;
3382 int ase = mips_opts.ase;
3385 if (ISA_HAS_64BIT_REGS (isa))
3386 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
3387 if ((ase & mips_ases[i].flags) == mips_ases[i].flags)
3388 ase |= mips_ases[i].flags64;
3390 return opcode_is_member (mo, isa, ase, mips_opts.arch);
3393 /* Return TRUE if the size of the microMIPS opcode MO matches one
3394 explicitly requested. Always TRUE in the standard MIPS mode.
3395 Use is_size_valid_16 for MIPS16 opcodes. */
3398 is_size_valid (const struct mips_opcode *mo)
3400 if (!mips_opts.micromips)
3403 if (mips_opts.insn32)
3405 if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4)
3407 if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0)
3410 if (!forced_insn_length)
3412 if (mo->pinfo == INSN_MACRO)
3414 return forced_insn_length == micromips_insn_length (mo);
3417 /* Return TRUE if the size of the MIPS16 opcode MO matches one
3418 explicitly requested. */
3421 is_size_valid_16 (const struct mips_opcode *mo)
3423 if (!forced_insn_length)
3425 if (mo->pinfo == INSN_MACRO)
3427 if (forced_insn_length == 2 && mips_opcode_32bit_p (mo))
3429 if (forced_insn_length == 4 && (mo->pinfo2 & INSN2_SHORT_ONLY))
3434 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3435 of the preceding instruction. Always TRUE in the standard MIPS mode.
3437 We don't accept macros in 16-bit delay slots to avoid a case where
3438 a macro expansion fails because it relies on a preceding 32-bit real
3439 instruction to have matched and does not handle the operands correctly.
3440 The only macros that may expand to 16-bit instructions are JAL that
3441 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3442 and BGT (that likewise cannot be placed in a delay slot) that decay to
3443 a NOP. In all these cases the macros precede any corresponding real
3444 instruction definitions in the opcode table, so they will match in the
3445 second pass where the size of the delay slot is ignored and therefore
3446 produce correct code. */
3449 is_delay_slot_valid (const struct mips_opcode *mo)
3451 if (!mips_opts.micromips)
3454 if (mo->pinfo == INSN_MACRO)
3455 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0;
3456 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
3457 && micromips_insn_length (mo) != 4)
3459 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
3460 && micromips_insn_length (mo) != 2)
3466 /* For consistency checking, verify that all bits of OPCODE are specified
3467 either by the match/mask part of the instruction definition, or by the
3468 operand list. Also build up a list of operands in OPERANDS.
3470 INSN_BITS says which bits of the instruction are significant.
3471 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3472 provides the mips_operand description of each operand. DECODE_OPERAND
3473 is null for MIPS16 instructions. */
3476 validate_mips_insn (const struct mips_opcode *opcode,
3477 unsigned long insn_bits,
3478 const struct mips_operand *(*decode_operand) (const char *),
3479 struct mips_operand_array *operands)
3482 unsigned long used_bits, doubled, undefined, opno, mask;
3483 const struct mips_operand *operand;
3485 mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask);
3486 if ((mask & opcode->match) != opcode->match)
3488 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3489 opcode->name, opcode->args);
3494 if (opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX)
3495 used_bits = mips_insert_operand (&mips_vu0_channel_mask, used_bits, -1);
3496 for (s = opcode->args; *s; ++s)
3509 if (!decode_operand)
3510 operand = decode_mips16_operand (*s, mips_opcode_32bit_p (opcode));
3512 operand = decode_operand (s);
3513 if (!operand && opcode->pinfo != INSN_MACRO)
3515 as_bad (_("internal: unknown operand type: %s %s"),
3516 opcode->name, opcode->args);
3519 gas_assert (opno < MAX_OPERANDS);
3520 operands->operand[opno] = operand;
3521 if (!decode_operand && operand
3522 && operand->type == OP_INT && operand->lsb == 0
3523 && mips_opcode_32bit_p (opcode))
3524 used_bits |= mips16_immed_extend (-1, operand->size);
3525 else if (operand && operand->type != OP_VU0_MATCH_SUFFIX)
3527 used_bits = mips_insert_operand (operand, used_bits, -1);
3528 if (operand->type == OP_MDMX_IMM_REG)
3529 /* Bit 5 is the format selector (OB vs QH). The opcode table
3530 has separate entries for each format. */
3531 used_bits &= ~(1 << (operand->lsb + 5));
3532 if (operand->type == OP_ENTRY_EXIT_LIST)
3533 used_bits &= ~(mask & 0x700);
3534 /* interAptiv MR2 SAVE/RESTORE instructions have a discontiguous
3535 operand field that cannot be fully described with LSB/SIZE. */
3536 if (operand->type == OP_SAVE_RESTORE_LIST && operand->lsb == 6)
3537 used_bits &= ~0x6000;
3539 /* Skip prefix characters. */
3540 if (decode_operand && (*s == '+' || *s == 'm' || *s == '-'))
3545 doubled = used_bits & mask & insn_bits;
3548 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3549 " %s %s"), doubled, opcode->name, opcode->args);
3553 undefined = ~used_bits & insn_bits;
3554 if (opcode->pinfo != INSN_MACRO && undefined)
3556 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3557 undefined, opcode->name, opcode->args);
3560 used_bits &= ~insn_bits;
3563 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3564 used_bits, opcode->name, opcode->args);
3570 /* The MIPS16 version of validate_mips_insn. */
3573 validate_mips16_insn (const struct mips_opcode *opcode,
3574 struct mips_operand_array *operands)
3576 unsigned long insn_bits = mips_opcode_32bit_p (opcode) ? 0xffffffff : 0xffff;
3578 return validate_mips_insn (opcode, insn_bits, 0, operands);
3581 /* The microMIPS version of validate_mips_insn. */
3584 validate_micromips_insn (const struct mips_opcode *opc,
3585 struct mips_operand_array *operands)
3587 unsigned long insn_bits;
3588 unsigned long major;
3589 unsigned int length;
3591 if (opc->pinfo == INSN_MACRO)
3592 return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand,
3595 length = micromips_insn_length (opc);
3596 if (length != 2 && length != 4)
3598 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3599 "%s %s"), length, opc->name, opc->args);
3602 major = opc->match >> (10 + 8 * (length - 2));
3603 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
3604 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
3606 as_bad (_("internal error: bad microMIPS opcode "
3607 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
3611 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3612 insn_bits = 1 << 4 * length;
3613 insn_bits <<= 4 * length;
3615 return validate_mips_insn (opc, insn_bits, decode_micromips_operand,
3619 /* This function is called once, at assembler startup time. It should set up
3620 all the tables, etc. that the MD part of the assembler will need. */
3625 const char *retval = NULL;
3629 if (mips_pic != NO_PIC)
3631 if (g_switch_seen && g_switch_value != 0)
3632 as_bad (_("-G may not be used in position-independent code"));
3635 else if (mips_abicalls)
3637 if (g_switch_seen && g_switch_value != 0)
3638 as_bad (_("-G may not be used with abicalls"));
3642 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch))
3643 as_warn (_("could not set architecture and machine"));
3645 op_hash = hash_new ();
3647 mips_operands = XCNEWVEC (struct mips_operand_array, NUMOPCODES);
3648 for (i = 0; i < NUMOPCODES;)
3650 const char *name = mips_opcodes[i].name;
3652 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
3655 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
3656 mips_opcodes[i].name, retval);
3657 /* Probably a memory allocation problem? Give up now. */
3658 as_fatal (_("broken assembler, no assembly attempted"));
3662 if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff,
3663 decode_mips_operand, &mips_operands[i]))
3665 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3667 create_insn (&nop_insn, mips_opcodes + i);
3668 if (mips_fix_loongson2f_nop)
3669 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
3670 nop_insn.fixed_p = 1;
3674 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
3677 mips16_op_hash = hash_new ();
3678 mips16_operands = XCNEWVEC (struct mips_operand_array,
3679 bfd_mips16_num_opcodes);
3682 while (i < bfd_mips16_num_opcodes)
3684 const char *name = mips16_opcodes[i].name;
3686 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
3688 as_fatal (_("internal: can't hash `%s': %s"),
3689 mips16_opcodes[i].name, retval);
3692 if (!validate_mips16_insn (&mips16_opcodes[i], &mips16_operands[i]))
3694 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3696 create_insn (&mips16_nop_insn, mips16_opcodes + i);
3697 mips16_nop_insn.fixed_p = 1;
3701 while (i < bfd_mips16_num_opcodes
3702 && strcmp (mips16_opcodes[i].name, name) == 0);
3705 micromips_op_hash = hash_new ();
3706 micromips_operands = XCNEWVEC (struct mips_operand_array,
3707 bfd_micromips_num_opcodes);
3710 while (i < bfd_micromips_num_opcodes)
3712 const char *name = micromips_opcodes[i].name;
3714 retval = hash_insert (micromips_op_hash, name,
3715 (void *) µmips_opcodes[i]);
3717 as_fatal (_("internal: can't hash `%s': %s"),
3718 micromips_opcodes[i].name, retval);
3721 struct mips_cl_insn *micromips_nop_insn;
3723 if (!validate_micromips_insn (µmips_opcodes[i],
3724 µmips_operands[i]))
3727 if (micromips_opcodes[i].pinfo != INSN_MACRO)
3729 if (micromips_insn_length (micromips_opcodes + i) == 2)
3730 micromips_nop_insn = µmips_nop16_insn;
3731 else if (micromips_insn_length (micromips_opcodes + i) == 4)
3732 micromips_nop_insn = µmips_nop32_insn;
3736 if (micromips_nop_insn->insn_mo == NULL
3737 && strcmp (name, "nop") == 0)
3739 create_insn (micromips_nop_insn, micromips_opcodes + i);
3740 micromips_nop_insn->fixed_p = 1;
3744 while (++i < bfd_micromips_num_opcodes
3745 && strcmp (micromips_opcodes[i].name, name) == 0);
3749 as_fatal (_("broken assembler, no assembly attempted"));
3751 /* We add all the general register names to the symbol table. This
3752 helps us detect invalid uses of them. */
3753 for (i = 0; reg_names[i].name; i++)
3754 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
3755 reg_names[i].num, /* & RNUM_MASK, */
3756 &zero_address_frag));
3758 for (i = 0; reg_names_n32n64[i].name; i++)
3759 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
3760 reg_names_n32n64[i].num, /* & RNUM_MASK, */
3761 &zero_address_frag));
3763 for (i = 0; reg_names_o32[i].name; i++)
3764 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
3765 reg_names_o32[i].num, /* & RNUM_MASK, */
3766 &zero_address_frag));
3768 for (i = 0; i < 32; i++)
3772 /* R5900 VU0 floating-point register. */
3773 sprintf (regname, "$vf%d", i);
3774 symbol_table_insert (symbol_new (regname, reg_section,
3775 RTYPE_VF | i, &zero_address_frag));
3777 /* R5900 VU0 integer register. */
3778 sprintf (regname, "$vi%d", i);
3779 symbol_table_insert (symbol_new (regname, reg_section,
3780 RTYPE_VI | i, &zero_address_frag));
3783 sprintf (regname, "$w%d", i);
3784 symbol_table_insert (symbol_new (regname, reg_section,
3785 RTYPE_MSA | i, &zero_address_frag));
3788 obstack_init (&mips_operand_tokens);
3790 mips_no_prev_insn ();
3793 mips_cprmask[0] = 0;
3794 mips_cprmask[1] = 0;
3795 mips_cprmask[2] = 0;
3796 mips_cprmask[3] = 0;
3798 /* set the default alignment for the text section (2**2) */
3799 record_alignment (text_section, 2);
3801 bfd_set_gp_size (stdoutput, g_switch_value);
3803 /* On a native system other than VxWorks, sections must be aligned
3804 to 16 byte boundaries. When configured for an embedded ELF
3805 target, we don't bother. */
3806 if (strncmp (TARGET_OS, "elf", 3) != 0
3807 && strncmp (TARGET_OS, "vxworks", 7) != 0)
3809 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
3810 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
3811 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
3814 /* Create a .reginfo section for register masks and a .mdebug
3815 section for debugging information. */
3823 subseg = now_subseg;
3825 /* The ABI says this section should be loaded so that the
3826 running program can access it. However, we don't load it
3827 if we are configured for an embedded target */
3828 flags = SEC_READONLY | SEC_DATA;
3829 if (strncmp (TARGET_OS, "elf", 3) != 0)
3830 flags |= SEC_ALLOC | SEC_LOAD;
3832 if (mips_abi != N64_ABI)
3834 sec = subseg_new (".reginfo", (subsegT) 0);
3836 bfd_set_section_flags (stdoutput, sec, flags);
3837 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
3839 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
3843 /* The 64-bit ABI uses a .MIPS.options section rather than
3844 .reginfo section. */
3845 sec = subseg_new (".MIPS.options", (subsegT) 0);
3846 bfd_set_section_flags (stdoutput, sec, flags);
3847 bfd_set_section_alignment (stdoutput, sec, 3);
3849 /* Set up the option header. */
3851 Elf_Internal_Options opthdr;
3854 opthdr.kind = ODK_REGINFO;
3855 opthdr.size = (sizeof (Elf_External_Options)
3856 + sizeof (Elf64_External_RegInfo));
3859 f = frag_more (sizeof (Elf_External_Options));
3860 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
3861 (Elf_External_Options *) f);
3863 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
3867 sec = subseg_new (".MIPS.abiflags", (subsegT) 0);
3868 bfd_set_section_flags (stdoutput, sec,
3869 SEC_READONLY | SEC_DATA | SEC_ALLOC | SEC_LOAD);
3870 bfd_set_section_alignment (stdoutput, sec, 3);
3871 mips_flags_frag = frag_more (sizeof (Elf_External_ABIFlags_v0));
3873 if (ECOFF_DEBUGGING)
3875 sec = subseg_new (".mdebug", (subsegT) 0);
3876 (void) bfd_set_section_flags (stdoutput, sec,
3877 SEC_HAS_CONTENTS | SEC_READONLY);
3878 (void) bfd_set_section_alignment (stdoutput, sec, 2);
3880 else if (mips_flag_pdr)
3882 pdr_seg = subseg_new (".pdr", (subsegT) 0);
3883 (void) bfd_set_section_flags (stdoutput, pdr_seg,
3884 SEC_READONLY | SEC_RELOC
3886 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
3889 subseg_set (seg, subseg);
3892 if (mips_fix_vr4120)
3893 init_vr4120_conflicts ();
3897 fpabi_incompatible_with (int fpabi, const char *what)
3899 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3900 Tag_GNU_MIPS_ABI_FP, fpabi, what);
3904 fpabi_requires (int fpabi, const char *what)
3906 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3907 Tag_GNU_MIPS_ABI_FP, fpabi, what);
3910 /* Check -mabi and register sizes against the specified FP ABI. */
3912 check_fpabi (int fpabi)
3916 case Val_GNU_MIPS_ABI_FP_DOUBLE:
3917 if (file_mips_opts.soft_float)
3918 fpabi_incompatible_with (fpabi, "softfloat");
3919 else if (file_mips_opts.single_float)
3920 fpabi_incompatible_with (fpabi, "singlefloat");
3921 if (file_mips_opts.gp == 64 && file_mips_opts.fp == 32)
3922 fpabi_incompatible_with (fpabi, "gp=64 fp=32");
3923 else if (file_mips_opts.gp == 32 && file_mips_opts.fp == 64)
3924 fpabi_incompatible_with (fpabi, "gp=32 fp=64");
3927 case Val_GNU_MIPS_ABI_FP_XX:
3928 if (mips_abi != O32_ABI)
3929 fpabi_requires (fpabi, "-mabi=32");
3930 else if (file_mips_opts.soft_float)
3931 fpabi_incompatible_with (fpabi, "softfloat");
3932 else if (file_mips_opts.single_float)
3933 fpabi_incompatible_with (fpabi, "singlefloat");
3934 else if (file_mips_opts.fp != 0)
3935 fpabi_requires (fpabi, "fp=xx");
3938 case Val_GNU_MIPS_ABI_FP_64A:
3939 case Val_GNU_MIPS_ABI_FP_64:
3940 if (mips_abi != O32_ABI)
3941 fpabi_requires (fpabi, "-mabi=32");
3942 else if (file_mips_opts.soft_float)
3943 fpabi_incompatible_with (fpabi, "softfloat");
3944 else if (file_mips_opts.single_float)
3945 fpabi_incompatible_with (fpabi, "singlefloat");
3946 else if (file_mips_opts.fp != 64)
3947 fpabi_requires (fpabi, "fp=64");
3948 else if (fpabi == Val_GNU_MIPS_ABI_FP_64 && !file_mips_opts.oddspreg)
3949 fpabi_incompatible_with (fpabi, "nooddspreg");
3950 else if (fpabi == Val_GNU_MIPS_ABI_FP_64A && file_mips_opts.oddspreg)
3951 fpabi_requires (fpabi, "nooddspreg");
3954 case Val_GNU_MIPS_ABI_FP_SINGLE:
3955 if (file_mips_opts.soft_float)
3956 fpabi_incompatible_with (fpabi, "softfloat");
3957 else if (!file_mips_opts.single_float)
3958 fpabi_requires (fpabi, "singlefloat");
3961 case Val_GNU_MIPS_ABI_FP_SOFT:
3962 if (!file_mips_opts.soft_float)
3963 fpabi_requires (fpabi, "softfloat");
3966 case Val_GNU_MIPS_ABI_FP_OLD_64:
3967 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
3968 Tag_GNU_MIPS_ABI_FP, fpabi);
3971 case Val_GNU_MIPS_ABI_FP_NAN2008:
3972 /* Silently ignore compatibility value. */
3976 as_warn (_(".gnu_attribute %d,%d is not a recognized"
3977 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP, fpabi);
3982 /* Perform consistency checks on the current options. */
3985 mips_check_options (struct mips_set_options *opts, bfd_boolean abi_checks)
3987 /* Check the size of integer registers agrees with the ABI and ISA. */
3988 if (opts->gp == 64 && !ISA_HAS_64BIT_REGS (opts->isa))
3989 as_bad (_("`gp=64' used with a 32-bit processor"));
3991 && opts->gp == 32 && ABI_NEEDS_64BIT_REGS (mips_abi))
3992 as_bad (_("`gp=32' used with a 64-bit ABI"));
3994 && opts->gp == 64 && ABI_NEEDS_32BIT_REGS (mips_abi))
3995 as_bad (_("`gp=64' used with a 32-bit ABI"));
3997 /* Check the size of the float registers agrees with the ABI and ISA. */
4001 if (!CPU_HAS_LDC1_SDC1 (opts->arch))
4002 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
4003 else if (opts->single_float == 1)
4004 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
4007 if (!ISA_HAS_64BIT_FPRS (opts->isa))
4008 as_bad (_("`fp=64' used with a 32-bit fpu"));
4010 && ABI_NEEDS_32BIT_REGS (mips_abi)
4011 && !ISA_HAS_MXHC1 (opts->isa))
4012 as_warn (_("`fp=64' used with a 32-bit ABI"));
4016 && ABI_NEEDS_64BIT_REGS (mips_abi))
4017 as_warn (_("`fp=32' used with a 64-bit ABI"));
4018 if (ISA_IS_R6 (opts->isa) && opts->single_float == 0)
4019 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
4022 as_bad (_("Unknown size of floating point registers"));
4026 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !opts->oddspreg)
4027 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
4029 if (opts->micromips == 1 && opts->mips16 == 1)
4030 as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips");
4031 else if (ISA_IS_R6 (opts->isa)
4032 && (opts->micromips == 1
4033 || opts->mips16 == 1))
4034 as_fatal (_("`%s' cannot be used with `%s'"),
4035 opts->micromips ? "micromips" : "mips16",
4036 mips_cpu_info_from_isa (opts->isa)->name);
4038 if (ISA_IS_R6 (opts->isa) && mips_relax_branch)
4039 as_fatal (_("branch relaxation is not supported in `%s'"),
4040 mips_cpu_info_from_isa (opts->isa)->name);
4043 /* Perform consistency checks on the module level options exactly once.
4044 This is a deferred check that happens:
4045 at the first .set directive
4046 or, at the first pseudo op that generates code (inc .dc.a)
4047 or, at the first instruction
4051 file_mips_check_options (void)
4053 const struct mips_cpu_info *arch_info = 0;
4055 if (file_mips_opts_checked)
4058 /* The following code determines the register size.
4059 Similar code was added to GCC 3.3 (see override_options() in
4060 config/mips/mips.c). The GAS and GCC code should be kept in sync
4061 as much as possible. */
4063 if (file_mips_opts.gp < 0)
4065 /* Infer the integer register size from the ABI and processor.
4066 Restrict ourselves to 32-bit registers if that's all the
4067 processor has, or if the ABI cannot handle 64-bit registers. */
4068 file_mips_opts.gp = (ABI_NEEDS_32BIT_REGS (mips_abi)
4069 || !ISA_HAS_64BIT_REGS (file_mips_opts.isa))
4073 if (file_mips_opts.fp < 0)
4075 /* No user specified float register size.
4076 ??? GAS treats single-float processors as though they had 64-bit
4077 float registers (although it complains when double-precision
4078 instructions are used). As things stand, saying they have 32-bit
4079 registers would lead to spurious "register must be even" messages.
4080 So here we assume float registers are never smaller than the
4082 if (file_mips_opts.gp == 64)
4083 /* 64-bit integer registers implies 64-bit float registers. */
4084 file_mips_opts.fp = 64;
4085 else if ((file_mips_opts.ase & FP64_ASES)
4086 && ISA_HAS_64BIT_FPRS (file_mips_opts.isa))
4087 /* Handle ASEs that require 64-bit float registers, if possible. */
4088 file_mips_opts.fp = 64;
4089 else if (ISA_IS_R6 (mips_opts.isa))
4090 /* R6 implies 64-bit float registers. */
4091 file_mips_opts.fp = 64;
4093 /* 32-bit float registers. */
4094 file_mips_opts.fp = 32;
4097 arch_info = mips_cpu_info_from_arch (file_mips_opts.arch);
4099 /* Disable operations on odd-numbered floating-point registers by default
4100 when using the FPXX ABI. */
4101 if (file_mips_opts.oddspreg < 0)
4103 if (file_mips_opts.fp == 0)
4104 file_mips_opts.oddspreg = 0;
4106 file_mips_opts.oddspreg = 1;
4109 /* End of GCC-shared inference code. */
4111 /* This flag is set when we have a 64-bit capable CPU but use only
4112 32-bit wide registers. Note that EABI does not use it. */
4113 if (ISA_HAS_64BIT_REGS (file_mips_opts.isa)
4114 && ((mips_abi == NO_ABI && file_mips_opts.gp == 32)
4115 || mips_abi == O32_ABI))
4118 if (file_mips_opts.isa == ISA_MIPS1 && mips_trap)
4119 as_bad (_("trap exception not supported at ISA 1"));
4121 /* If the selected architecture includes support for ASEs, enable
4122 generation of code for them. */
4123 if (file_mips_opts.mips16 == -1)
4124 file_mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_opts.arch)) ? 1 : 0;
4125 if (file_mips_opts.micromips == -1)
4126 file_mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_opts.arch))
4129 if (mips_nan2008 == -1)
4130 mips_nan2008 = (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) ? 0 : 1;
4131 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts.isa) && mips_nan2008 == 0)
4132 as_fatal (_("`%s' does not support legacy NaN"),
4133 mips_cpu_info_from_arch (file_mips_opts.arch)->name);
4135 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
4136 being selected implicitly. */
4137 if (file_mips_opts.fp != 64)
4138 file_ase_explicit |= ASE_MIPS3D | ASE_MDMX | ASE_MSA;
4140 /* If the user didn't explicitly select or deselect a particular ASE,
4141 use the default setting for the CPU. */
4142 file_mips_opts.ase |= (arch_info->ase & ~file_ase_explicit);
4144 /* Set up the current options. These may change throughout assembly. */
4145 mips_opts = file_mips_opts;
4147 mips_check_isa_supports_ases ();
4148 mips_check_options (&file_mips_opts, TRUE);
4149 file_mips_opts_checked = TRUE;
4151 if (!bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch))
4152 as_warn (_("could not set architecture and machine"));
4156 md_assemble (char *str)
4158 struct mips_cl_insn insn;
4159 bfd_reloc_code_real_type unused_reloc[3]
4160 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
4162 file_mips_check_options ();
4164 imm_expr.X_op = O_absent;
4165 offset_expr.X_op = O_absent;
4166 offset_reloc[0] = BFD_RELOC_UNUSED;
4167 offset_reloc[1] = BFD_RELOC_UNUSED;
4168 offset_reloc[2] = BFD_RELOC_UNUSED;
4170 mips_mark_labels ();
4171 mips_assembling_insn = TRUE;
4172 clear_insn_error ();
4174 if (mips_opts.mips16)
4175 mips16_ip (str, &insn);
4178 mips_ip (str, &insn);
4179 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4180 str, insn.insn_opcode));
4184 report_insn_error (str);
4185 else if (insn.insn_mo->pinfo == INSN_MACRO)
4188 if (mips_opts.mips16)
4189 mips16_macro (&insn);
4196 if (offset_expr.X_op != O_absent)
4197 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
4199 append_insn (&insn, NULL, unused_reloc, FALSE);
4202 mips_assembling_insn = FALSE;
4205 /* Convenience functions for abstracting away the differences between
4206 MIPS16 and non-MIPS16 relocations. */
4208 static inline bfd_boolean
4209 mips16_reloc_p (bfd_reloc_code_real_type reloc)
4213 case BFD_RELOC_MIPS16_JMP:
4214 case BFD_RELOC_MIPS16_GPREL:
4215 case BFD_RELOC_MIPS16_GOT16:
4216 case BFD_RELOC_MIPS16_CALL16:
4217 case BFD_RELOC_MIPS16_HI16_S:
4218 case BFD_RELOC_MIPS16_HI16:
4219 case BFD_RELOC_MIPS16_LO16:
4220 case BFD_RELOC_MIPS16_16_PCREL_S1:
4228 static inline bfd_boolean
4229 micromips_reloc_p (bfd_reloc_code_real_type reloc)
4233 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
4234 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
4235 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
4236 case BFD_RELOC_MICROMIPS_GPREL16:
4237 case BFD_RELOC_MICROMIPS_JMP:
4238 case BFD_RELOC_MICROMIPS_HI16:
4239 case BFD_RELOC_MICROMIPS_HI16_S:
4240 case BFD_RELOC_MICROMIPS_LO16:
4241 case BFD_RELOC_MICROMIPS_LITERAL:
4242 case BFD_RELOC_MICROMIPS_GOT16:
4243 case BFD_RELOC_MICROMIPS_CALL16:
4244 case BFD_RELOC_MICROMIPS_GOT_HI16:
4245 case BFD_RELOC_MICROMIPS_GOT_LO16:
4246 case BFD_RELOC_MICROMIPS_CALL_HI16:
4247 case BFD_RELOC_MICROMIPS_CALL_LO16:
4248 case BFD_RELOC_MICROMIPS_SUB:
4249 case BFD_RELOC_MICROMIPS_GOT_PAGE:
4250 case BFD_RELOC_MICROMIPS_GOT_OFST:
4251 case BFD_RELOC_MICROMIPS_GOT_DISP:
4252 case BFD_RELOC_MICROMIPS_HIGHEST:
4253 case BFD_RELOC_MICROMIPS_HIGHER:
4254 case BFD_RELOC_MICROMIPS_SCN_DISP:
4255 case BFD_RELOC_MICROMIPS_JALR:
4263 static inline bfd_boolean
4264 jmp_reloc_p (bfd_reloc_code_real_type reloc)
4266 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
4269 static inline bfd_boolean
4270 b_reloc_p (bfd_reloc_code_real_type reloc)
4272 return (reloc == BFD_RELOC_MIPS_26_PCREL_S2
4273 || reloc == BFD_RELOC_MIPS_21_PCREL_S2
4274 || reloc == BFD_RELOC_16_PCREL_S2
4275 || reloc == BFD_RELOC_MIPS16_16_PCREL_S1
4276 || reloc == BFD_RELOC_MICROMIPS_16_PCREL_S1
4277 || reloc == BFD_RELOC_MICROMIPS_10_PCREL_S1
4278 || reloc == BFD_RELOC_MICROMIPS_7_PCREL_S1);
4281 static inline bfd_boolean
4282 got16_reloc_p (bfd_reloc_code_real_type reloc)
4284 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
4285 || reloc == BFD_RELOC_MICROMIPS_GOT16);
4288 static inline bfd_boolean
4289 hi16_reloc_p (bfd_reloc_code_real_type reloc)
4291 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
4292 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
4295 static inline bfd_boolean
4296 lo16_reloc_p (bfd_reloc_code_real_type reloc)
4298 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
4299 || reloc == BFD_RELOC_MICROMIPS_LO16);
4302 static inline bfd_boolean
4303 jalr_reloc_p (bfd_reloc_code_real_type reloc)
4305 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
4308 static inline bfd_boolean
4309 gprel16_reloc_p (bfd_reloc_code_real_type reloc)
4311 return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL
4312 || reloc == BFD_RELOC_MICROMIPS_GPREL16);
4315 /* Return true if RELOC is a PC-relative relocation that does not have
4316 full address range. */
4318 static inline bfd_boolean
4319 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc)
4323 case BFD_RELOC_16_PCREL_S2:
4324 case BFD_RELOC_MIPS16_16_PCREL_S1:
4325 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
4326 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
4327 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
4328 case BFD_RELOC_MIPS_21_PCREL_S2:
4329 case BFD_RELOC_MIPS_26_PCREL_S2:
4330 case BFD_RELOC_MIPS_18_PCREL_S3:
4331 case BFD_RELOC_MIPS_19_PCREL_S2:
4334 case BFD_RELOC_32_PCREL:
4335 case BFD_RELOC_HI16_S_PCREL:
4336 case BFD_RELOC_LO16_PCREL:
4337 return HAVE_64BIT_ADDRESSES;
4344 /* Return true if the given relocation might need a matching %lo().
4345 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4346 need a matching %lo() when applied to local symbols. */
4348 static inline bfd_boolean
4349 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
4351 return (HAVE_IN_PLACE_ADDENDS
4352 && (hi16_reloc_p (reloc)
4353 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4354 all GOT16 relocations evaluate to "G". */
4355 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
4358 /* Return the type of %lo() reloc needed by RELOC, given that
4359 reloc_needs_lo_p. */
4361 static inline bfd_reloc_code_real_type
4362 matching_lo_reloc (bfd_reloc_code_real_type reloc)
4364 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
4365 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
4369 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
4372 static inline bfd_boolean
4373 fixup_has_matching_lo_p (fixS *fixp)
4375 return (fixp->fx_next != NULL
4376 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
4377 && fixp->fx_addsy == fixp->fx_next->fx_addsy
4378 && fixp->fx_offset == fixp->fx_next->fx_offset);
4381 /* Move all labels in LABELS to the current insertion point. TEXT_P
4382 says whether the labels refer to text or data. */
4385 mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
4387 struct insn_label_list *l;
4390 for (l = labels; l != NULL; l = l->next)
4392 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
4393 symbol_set_frag (l->label, frag_now);
4394 val = (valueT) frag_now_fix ();
4395 /* MIPS16/microMIPS text labels are stored as odd. */
4396 if (text_p && HAVE_CODE_COMPRESSION)
4398 S_SET_VALUE (l->label, val);
4402 /* Move all labels in insn_labels to the current insertion point
4403 and treat them as text labels. */
4406 mips_move_text_labels (void)
4408 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
4411 /* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */
4414 s_is_linkonce (symbolS *sym, segT from_seg)
4416 bfd_boolean linkonce = FALSE;
4417 segT symseg = S_GET_SEGMENT (sym);
4419 if (symseg != from_seg && !S_IS_LOCAL (sym))
4421 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
4423 /* The GNU toolchain uses an extension for ELF: a section
4424 beginning with the magic string .gnu.linkonce is a
4425 linkonce section. */
4426 if (strncmp (segment_name (symseg), ".gnu.linkonce",
4427 sizeof ".gnu.linkonce" - 1) == 0)
4433 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
4434 linker to handle them specially, such as generating jalx instructions
4435 when needed. We also make them odd for the duration of the assembly,
4436 in order to generate the right sort of code. We will make them even
4437 in the adjust_symtab routine, while leaving them marked. This is
4438 convenient for the debugger and the disassembler. The linker knows
4439 to make them odd again. */
4442 mips_compressed_mark_label (symbolS *label)
4444 gas_assert (HAVE_CODE_COMPRESSION);
4446 if (mips_opts.mips16)
4447 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
4449 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
4450 if ((S_GET_VALUE (label) & 1) == 0
4451 /* Don't adjust the address if the label is global or weak, or
4452 in a link-once section, since we'll be emitting symbol reloc
4453 references to it which will be patched up by the linker, and
4454 the final value of the symbol may or may not be MIPS16/microMIPS. */
4455 && !S_IS_WEAK (label)
4456 && !S_IS_EXTERNAL (label)
4457 && !s_is_linkonce (label, now_seg))
4458 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
4461 /* Mark preceding MIPS16 or microMIPS instruction labels. */
4464 mips_compressed_mark_labels (void)
4466 struct insn_label_list *l;
4468 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next)
4469 mips_compressed_mark_label (l->label);
4472 /* End the current frag. Make it a variant frag and record the
4476 relax_close_frag (void)
4478 mips_macro_warning.first_frag = frag_now;
4479 frag_var (rs_machine_dependent, 0, 0,
4480 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1],
4481 mips_pic != NO_PIC),
4482 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
4484 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
4485 mips_relax.first_fixup = 0;
4488 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
4489 See the comment above RELAX_ENCODE for more details. */
4492 relax_start (symbolS *symbol)
4494 gas_assert (mips_relax.sequence == 0);
4495 mips_relax.sequence = 1;
4496 mips_relax.symbol = symbol;
4499 /* Start generating the second version of a relaxable sequence.
4500 See the comment above RELAX_ENCODE for more details. */
4505 gas_assert (mips_relax.sequence == 1);
4506 mips_relax.sequence = 2;
4509 /* End the current relaxable sequence. */
4514 gas_assert (mips_relax.sequence == 2);
4515 relax_close_frag ();
4516 mips_relax.sequence = 0;
4519 /* Return true if IP is a delayed branch or jump. */
4521 static inline bfd_boolean
4522 delayed_branch_p (const struct mips_cl_insn *ip)
4524 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
4525 | INSN_COND_BRANCH_DELAY
4526 | INSN_COND_BRANCH_LIKELY)) != 0;
4529 /* Return true if IP is a compact branch or jump. */
4531 static inline bfd_boolean
4532 compact_branch_p (const struct mips_cl_insn *ip)
4534 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
4535 | INSN2_COND_BRANCH)) != 0;
4538 /* Return true if IP is an unconditional branch or jump. */
4540 static inline bfd_boolean
4541 uncond_branch_p (const struct mips_cl_insn *ip)
4543 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
4544 || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0);
4547 /* Return true if IP is a branch-likely instruction. */
4549 static inline bfd_boolean
4550 branch_likely_p (const struct mips_cl_insn *ip)
4552 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
4555 /* Return the type of nop that should be used to fill the delay slot
4556 of delayed branch IP. */
4558 static struct mips_cl_insn *
4559 get_delay_slot_nop (const struct mips_cl_insn *ip)
4561 if (mips_opts.micromips
4562 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
4563 return µmips_nop32_insn;
4567 /* Return a mask that has bit N set if OPCODE reads the register(s)
4571 insn_read_mask (const struct mips_opcode *opcode)
4573 return (opcode->pinfo & INSN_READ_ALL) >> INSN_READ_SHIFT;
4576 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4580 insn_write_mask (const struct mips_opcode *opcode)
4582 return (opcode->pinfo & INSN_WRITE_ALL) >> INSN_WRITE_SHIFT;
4585 /* Return a mask of the registers specified by operand OPERAND of INSN.
4586 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4590 operand_reg_mask (const struct mips_cl_insn *insn,
4591 const struct mips_operand *operand,
4592 unsigned int type_mask)
4594 unsigned int uval, vsel;
4596 switch (operand->type)
4603 case OP_ADDIUSP_INT:
4604 case OP_ENTRY_EXIT_LIST:
4605 case OP_REPEAT_DEST_REG:
4606 case OP_REPEAT_PREV_REG:
4609 case OP_VU0_MATCH_SUFFIX:
4617 case OP_OPTIONAL_REG:
4619 const struct mips_reg_operand *reg_op;
4621 reg_op = (const struct mips_reg_operand *) operand;
4622 if (!(type_mask & (1 << reg_op->reg_type)))
4624 uval = insn_extract_operand (insn, operand);
4625 return 1 << mips_decode_reg_operand (reg_op, uval);
4630 const struct mips_reg_pair_operand *pair_op;
4632 pair_op = (const struct mips_reg_pair_operand *) operand;
4633 if (!(type_mask & (1 << pair_op->reg_type)))
4635 uval = insn_extract_operand (insn, operand);
4636 return (1 << pair_op->reg1_map[uval]) | (1 << pair_op->reg2_map[uval]);
4639 case OP_CLO_CLZ_DEST:
4640 if (!(type_mask & (1 << OP_REG_GP)))
4642 uval = insn_extract_operand (insn, operand);
4643 return (1 << (uval & 31)) | (1 << (uval >> 5));
4646 if (!(type_mask & (1 << OP_REG_GP)))
4648 uval = insn_extract_operand (insn, operand);
4649 gas_assert ((uval & 31) == (uval >> 5));
4650 return 1 << (uval & 31);
4653 case OP_NON_ZERO_REG:
4654 if (!(type_mask & (1 << OP_REG_GP)))
4656 uval = insn_extract_operand (insn, operand);
4657 return 1 << (uval & 31);
4659 case OP_LWM_SWM_LIST:
4662 case OP_SAVE_RESTORE_LIST:
4665 case OP_MDMX_IMM_REG:
4666 if (!(type_mask & (1 << OP_REG_VEC)))
4668 uval = insn_extract_operand (insn, operand);
4670 if ((vsel & 0x18) == 0x18)
4672 return 1 << (uval & 31);
4675 if (!(type_mask & (1 << OP_REG_GP)))
4677 return 1 << insn_extract_operand (insn, operand);
4682 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4683 where bit N of OPNO_MASK is set if operand N should be included.
4684 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4688 insn_reg_mask (const struct mips_cl_insn *insn,
4689 unsigned int type_mask, unsigned int opno_mask)
4691 unsigned int opno, reg_mask;
4695 while (opno_mask != 0)
4698 reg_mask |= operand_reg_mask (insn, insn_opno (insn, opno), type_mask);
4705 /* Return the mask of core registers that IP reads. */
4708 gpr_read_mask (const struct mips_cl_insn *ip)
4710 unsigned long pinfo, pinfo2;
4713 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_read_mask (ip->insn_mo));
4714 pinfo = ip->insn_mo->pinfo;
4715 pinfo2 = ip->insn_mo->pinfo2;
4716 if (pinfo & INSN_UDI)
4718 /* UDI instructions have traditionally been assumed to read RS
4720 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
4721 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
4723 if (pinfo & INSN_READ_GPR_24)
4725 if (pinfo2 & INSN2_READ_GPR_16)
4727 if (pinfo2 & INSN2_READ_SP)
4729 if (pinfo2 & INSN2_READ_GPR_31)
4731 /* Don't include register 0. */
4735 /* Return the mask of core registers that IP writes. */
4738 gpr_write_mask (const struct mips_cl_insn *ip)
4740 unsigned long pinfo, pinfo2;
4743 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_write_mask (ip->insn_mo));
4744 pinfo = ip->insn_mo->pinfo;
4745 pinfo2 = ip->insn_mo->pinfo2;
4746 if (pinfo & INSN_WRITE_GPR_24)
4748 if (pinfo & INSN_WRITE_GPR_31)
4750 if (pinfo & INSN_UDI)
4751 /* UDI instructions have traditionally been assumed to write to RD. */
4752 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
4753 if (pinfo2 & INSN2_WRITE_SP)
4755 /* Don't include register 0. */
4759 /* Return the mask of floating-point registers that IP reads. */
4762 fpr_read_mask (const struct mips_cl_insn *ip)
4764 unsigned long pinfo;
4767 mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC)
4768 | (1 << OP_REG_MSA)),
4769 insn_read_mask (ip->insn_mo));
4770 pinfo = ip->insn_mo->pinfo;
4771 /* Conservatively treat all operands to an FP_D instruction are doubles.
4772 (This is overly pessimistic for things like cvt.d.s.) */
4773 if (FPR_SIZE != 64 && (pinfo & FP_D))
4778 /* Return the mask of floating-point registers that IP writes. */
4781 fpr_write_mask (const struct mips_cl_insn *ip)
4783 unsigned long pinfo;
4786 mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC)
4787 | (1 << OP_REG_MSA)),
4788 insn_write_mask (ip->insn_mo));
4789 pinfo = ip->insn_mo->pinfo;
4790 /* Conservatively treat all operands to an FP_D instruction are doubles.
4791 (This is overly pessimistic for things like cvt.s.d.) */
4792 if (FPR_SIZE != 64 && (pinfo & FP_D))
4797 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4798 Check whether that is allowed. */
4801 mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum)
4803 const char *s = insn->name;
4804 bfd_boolean oddspreg = (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa, mips_opts.arch)
4806 && mips_opts.oddspreg;
4808 if (insn->pinfo == INSN_MACRO)
4809 /* Let a macro pass, we'll catch it later when it is expanded. */
4812 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4813 otherwise it depends on oddspreg. */
4814 if ((insn->pinfo & FP_S)
4815 && (insn->pinfo & (INSN_LOAD_MEMORY | INSN_STORE_MEMORY
4816 | INSN_LOAD_COPROC | INSN_COPROC_MOVE)))
4817 return FPR_SIZE == 32 || oddspreg;
4819 /* Allow odd registers for single-precision ops and double-precision if the
4820 floating-point registers are 64-bit wide. */
4821 switch (insn->pinfo & (FP_S | FP_D))
4827 return FPR_SIZE == 64;
4832 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4833 s = strchr (insn->name, '.');
4834 if (s != NULL && opnum == 2)
4835 s = strchr (s + 1, '.');
4836 if (s != NULL && (s[1] == 'w' || s[1] == 's'))
4839 return FPR_SIZE == 64;
4842 /* Information about an instruction argument that we're trying to match. */
4843 struct mips_arg_info
4845 /* The instruction so far. */
4846 struct mips_cl_insn *insn;
4848 /* The first unconsumed operand token. */
4849 struct mips_operand_token *token;
4851 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4854 /* The 1-based argument number, for error reporting. This does not
4855 count elided optional registers, etc.. */
4858 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4859 unsigned int last_regno;
4861 /* If the first operand was an OP_REG, this is the register that it
4862 specified, otherwise it is ILLEGAL_REG. */
4863 unsigned int dest_regno;
4865 /* The value of the last OP_INT operand. Only used for OP_MSB,
4866 where it gives the lsb position. */
4867 unsigned int last_op_int;
4869 /* If true, match routines should assume that no later instruction
4870 alternative matches and should therefore be as accommodating as
4871 possible. Match routines should not report errors if something
4872 is only invalid for !LAX_MATCH. */
4873 bfd_boolean lax_match;
4875 /* True if a reference to the current AT register was seen. */
4876 bfd_boolean seen_at;
4879 /* Record that the argument is out of range. */
4882 match_out_of_range (struct mips_arg_info *arg)
4884 set_insn_error_i (arg->argnum, _("operand %d out of range"), arg->argnum);
4887 /* Record that the argument isn't constant but needs to be. */
4890 match_not_constant (struct mips_arg_info *arg)
4892 set_insn_error_i (arg->argnum, _("operand %d must be constant"),
4896 /* Try to match an OT_CHAR token for character CH. Consume the token
4897 and return true on success, otherwise return false. */
4900 match_char (struct mips_arg_info *arg, char ch)
4902 if (arg->token->type == OT_CHAR && arg->token->u.ch == ch)
4912 /* Try to get an expression from the next tokens in ARG. Consume the
4913 tokens and return true on success, storing the expression value in
4914 VALUE and relocation types in R. */
4917 match_expression (struct mips_arg_info *arg, expressionS *value,
4918 bfd_reloc_code_real_type *r)
4920 /* If the next token is a '(' that was parsed as being part of a base
4921 expression, assume we have an elided offset. The later match will fail
4922 if this turns out to be wrong. */
4923 if (arg->token->type == OT_CHAR && arg->token->u.ch == '(')
4925 value->X_op = O_constant;
4926 value->X_add_number = 0;
4927 r[0] = r[1] = r[2] = BFD_RELOC_UNUSED;
4931 /* Reject register-based expressions such as "0+$2" and "(($2))".
4932 For plain registers the default error seems more appropriate. */
4933 if (arg->token->type == OT_INTEGER
4934 && arg->token->u.integer.value.X_op == O_register)
4936 set_insn_error (arg->argnum, _("register value used as expression"));
4940 if (arg->token->type == OT_INTEGER)
4942 *value = arg->token->u.integer.value;
4943 memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r));
4949 (arg->argnum, _("operand %d must be an immediate expression"),
4954 /* Try to get a constant expression from the next tokens in ARG. Consume
4955 the tokens and return true on success, storing the constant value
4959 match_const_int (struct mips_arg_info *arg, offsetT *value)
4962 bfd_reloc_code_real_type r[3];
4964 if (!match_expression (arg, &ex, r))
4967 if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant)
4968 *value = ex.X_add_number;
4971 if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_big)
4972 match_out_of_range (arg);
4974 match_not_constant (arg);
4980 /* Return the RTYPE_* flags for a register operand of type TYPE that
4981 appears in instruction OPCODE. */
4984 convert_reg_type (const struct mips_opcode *opcode,
4985 enum mips_reg_operand_type type)
4990 return RTYPE_NUM | RTYPE_GP;
4993 /* Allow vector register names for MDMX if the instruction is a 64-bit
4994 FPR load, store or move (including moves to and from GPRs). */
4995 if ((mips_opts.ase & ASE_MDMX)
4996 && (opcode->pinfo & FP_D)
4997 && (opcode->pinfo & (INSN_COPROC_MOVE
4998 | INSN_COPROC_MEMORY_DELAY
5001 | INSN_STORE_MEMORY)))
5002 return RTYPE_FPU | RTYPE_VEC;
5006 if (opcode->pinfo & (FP_D | FP_S))
5007 return RTYPE_CCC | RTYPE_FCC;
5011 if (opcode->membership & INSN_5400)
5013 return RTYPE_FPU | RTYPE_VEC;
5019 if (opcode->name[strlen (opcode->name) - 1] == '0')
5020 return RTYPE_NUM | RTYPE_CP0;
5027 return RTYPE_NUM | RTYPE_VI;
5030 return RTYPE_NUM | RTYPE_VF;
5032 case OP_REG_R5900_I:
5033 return RTYPE_R5900_I;
5035 case OP_REG_R5900_Q:
5036 return RTYPE_R5900_Q;
5038 case OP_REG_R5900_R:
5039 return RTYPE_R5900_R;
5041 case OP_REG_R5900_ACC:
5042 return RTYPE_R5900_ACC;
5047 case OP_REG_MSA_CTRL:
5053 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
5056 check_regno (struct mips_arg_info *arg,
5057 enum mips_reg_operand_type type, unsigned int regno)
5059 if (AT && type == OP_REG_GP && regno == AT)
5060 arg->seen_at = TRUE;
5062 if (type == OP_REG_FP
5064 && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum))
5066 /* This was a warning prior to introducing O32 FPXX and FP64 support
5067 so maintain a warning for FP32 but raise an error for the new
5070 as_warn (_("float register should be even, was %d"), regno);
5072 as_bad (_("float register should be even, was %d"), regno);
5075 if (type == OP_REG_CCC)
5080 name = arg->insn->insn_mo->name;
5081 length = strlen (name);
5082 if ((regno & 1) != 0
5083 && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0)
5084 || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0)))
5085 as_warn (_("condition code register should be even for %s, was %d"),
5088 if ((regno & 3) != 0
5089 && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0))
5090 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
5095 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
5096 a register of type TYPE. Return true on success, storing the register
5097 number in *REGNO and warning about any dubious uses. */
5100 match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type,
5101 unsigned int symval, unsigned int *regno)
5103 if (type == OP_REG_VEC)
5104 symval = mips_prefer_vec_regno (symval);
5105 if (!(symval & convert_reg_type (arg->insn->insn_mo, type)))
5108 *regno = symval & RNUM_MASK;
5109 check_regno (arg, type, *regno);
5113 /* Try to interpret the next token in ARG as a register of type TYPE.
5114 Consume the token and return true on success, storing the register
5115 number in *REGNO. Return false on failure. */
5118 match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type,
5119 unsigned int *regno)
5121 if (arg->token->type == OT_REG
5122 && match_regno (arg, type, arg->token->u.regno, regno))
5130 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
5131 Consume the token and return true on success, storing the register numbers
5132 in *REGNO1 and *REGNO2. Return false on failure. */
5135 match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type,
5136 unsigned int *regno1, unsigned int *regno2)
5138 if (match_reg (arg, type, regno1))
5143 if (arg->token->type == OT_REG_RANGE
5144 && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1)
5145 && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2)
5146 && *regno1 <= *regno2)
5154 /* OP_INT matcher. */
5157 match_int_operand (struct mips_arg_info *arg,
5158 const struct mips_operand *operand_base)
5160 const struct mips_int_operand *operand;
5162 int min_val, max_val, factor;
5165 operand = (const struct mips_int_operand *) operand_base;
5166 factor = 1 << operand->shift;
5167 min_val = mips_int_operand_min (operand);
5168 max_val = mips_int_operand_max (operand);
5170 if (operand_base->lsb == 0
5171 && operand_base->size == 16
5172 && operand->shift == 0
5173 && operand->bias == 0
5174 && (operand->max_val == 32767 || operand->max_val == 65535))
5176 /* The operand can be relocated. */
5177 if (!match_expression (arg, &offset_expr, offset_reloc))
5180 if (offset_expr.X_op == O_big)
5182 match_out_of_range (arg);
5186 if (offset_reloc[0] != BFD_RELOC_UNUSED)
5187 /* Relocation operators were used. Accept the argument and
5188 leave the relocation value in offset_expr and offset_relocs
5189 for the caller to process. */
5192 if (offset_expr.X_op != O_constant)
5194 /* Accept non-constant operands if no later alternative matches,
5195 leaving it for the caller to process. */
5196 if (!arg->lax_match)
5198 match_not_constant (arg);
5201 offset_reloc[0] = BFD_RELOC_LO16;
5205 /* Clear the global state; we're going to install the operand
5207 sval = offset_expr.X_add_number;
5208 offset_expr.X_op = O_absent;
5210 /* For compatibility with older assemblers, we accept
5211 0x8000-0xffff as signed 16-bit numbers when only
5212 signed numbers are allowed. */
5215 max_val = ((1 << operand_base->size) - 1) << operand->shift;
5216 if (!arg->lax_match && sval <= max_val)
5218 match_out_of_range (arg);
5225 if (!match_const_int (arg, &sval))
5229 arg->last_op_int = sval;
5231 if (sval < min_val || sval > max_val || sval % factor)
5233 match_out_of_range (arg);
5237 uval = (unsigned int) sval >> operand->shift;
5238 uval -= operand->bias;
5240 /* Handle -mfix-cn63xxp1. */
5242 && mips_fix_cn63xxp1
5243 && !mips_opts.micromips
5244 && strcmp ("pref", arg->insn->insn_mo->name) == 0)
5259 /* The rest must be changed to 28. */
5264 insn_insert_operand (arg->insn, operand_base, uval);
5268 /* OP_MAPPED_INT matcher. */
5271 match_mapped_int_operand (struct mips_arg_info *arg,
5272 const struct mips_operand *operand_base)
5274 const struct mips_mapped_int_operand *operand;
5275 unsigned int uval, num_vals;
5278 operand = (const struct mips_mapped_int_operand *) operand_base;
5279 if (!match_const_int (arg, &sval))
5282 num_vals = 1 << operand_base->size;
5283 for (uval = 0; uval < num_vals; uval++)
5284 if (operand->int_map[uval] == sval)
5286 if (uval == num_vals)
5288 match_out_of_range (arg);
5292 insn_insert_operand (arg->insn, operand_base, uval);
5296 /* OP_MSB matcher. */
5299 match_msb_operand (struct mips_arg_info *arg,
5300 const struct mips_operand *operand_base)
5302 const struct mips_msb_operand *operand;
5303 int min_val, max_val, max_high;
5304 offsetT size, sval, high;
5306 operand = (const struct mips_msb_operand *) operand_base;
5307 min_val = operand->bias;
5308 max_val = min_val + (1 << operand_base->size) - 1;
5309 max_high = operand->opsize;
5311 if (!match_const_int (arg, &size))
5314 high = size + arg->last_op_int;
5315 sval = operand->add_lsb ? high : size;
5317 if (size < 0 || high > max_high || sval < min_val || sval > max_val)
5319 match_out_of_range (arg);
5322 insn_insert_operand (arg->insn, operand_base, sval - min_val);
5326 /* OP_REG matcher. */
5329 match_reg_operand (struct mips_arg_info *arg,
5330 const struct mips_operand *operand_base)
5332 const struct mips_reg_operand *operand;
5333 unsigned int regno, uval, num_vals;
5335 operand = (const struct mips_reg_operand *) operand_base;
5336 if (!match_reg (arg, operand->reg_type, ®no))
5339 if (operand->reg_map)
5341 num_vals = 1 << operand->root.size;
5342 for (uval = 0; uval < num_vals; uval++)
5343 if (operand->reg_map[uval] == regno)
5345 if (num_vals == uval)
5351 arg->last_regno = regno;
5352 if (arg->opnum == 1)
5353 arg->dest_regno = regno;
5354 insn_insert_operand (arg->insn, operand_base, uval);
5358 /* OP_REG_PAIR matcher. */
5361 match_reg_pair_operand (struct mips_arg_info *arg,
5362 const struct mips_operand *operand_base)
5364 const struct mips_reg_pair_operand *operand;
5365 unsigned int regno1, regno2, uval, num_vals;
5367 operand = (const struct mips_reg_pair_operand *) operand_base;
5368 if (!match_reg (arg, operand->reg_type, ®no1)
5369 || !match_char (arg, ',')
5370 || !match_reg (arg, operand->reg_type, ®no2))
5373 num_vals = 1 << operand_base->size;
5374 for (uval = 0; uval < num_vals; uval++)
5375 if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2)
5377 if (uval == num_vals)
5380 insn_insert_operand (arg->insn, operand_base, uval);
5384 /* OP_PCREL matcher. The caller chooses the relocation type. */
5387 match_pcrel_operand (struct mips_arg_info *arg)
5389 bfd_reloc_code_real_type r[3];
5391 return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED;
5394 /* OP_PERF_REG matcher. */
5397 match_perf_reg_operand (struct mips_arg_info *arg,
5398 const struct mips_operand *operand)
5402 if (!match_const_int (arg, &sval))
5407 || (mips_opts.arch == CPU_R5900
5408 && (strcmp (arg->insn->insn_mo->name, "mfps") == 0
5409 || strcmp (arg->insn->insn_mo->name, "mtps") == 0))))
5411 set_insn_error (arg->argnum, _("invalid performance register"));
5415 insn_insert_operand (arg->insn, operand, sval);
5419 /* OP_ADDIUSP matcher. */
5422 match_addiusp_operand (struct mips_arg_info *arg,
5423 const struct mips_operand *operand)
5428 if (!match_const_int (arg, &sval))
5433 match_out_of_range (arg);
5438 if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1))
5440 match_out_of_range (arg);
5444 uval = (unsigned int) sval;
5445 uval = ((uval >> 1) & ~0xff) | (uval & 0xff);
5446 insn_insert_operand (arg->insn, operand, uval);
5450 /* OP_CLO_CLZ_DEST matcher. */
5453 match_clo_clz_dest_operand (struct mips_arg_info *arg,
5454 const struct mips_operand *operand)
5458 if (!match_reg (arg, OP_REG_GP, ®no))
5461 insn_insert_operand (arg->insn, operand, regno | (regno << 5));
5465 /* OP_CHECK_PREV matcher. */
5468 match_check_prev_operand (struct mips_arg_info *arg,
5469 const struct mips_operand *operand_base)
5471 const struct mips_check_prev_operand *operand;
5474 operand = (const struct mips_check_prev_operand *) operand_base;
5476 if (!match_reg (arg, OP_REG_GP, ®no))
5479 if (!operand->zero_ok && regno == 0)
5482 if ((operand->less_than_ok && regno < arg->last_regno)
5483 || (operand->greater_than_ok && regno > arg->last_regno)
5484 || (operand->equal_ok && regno == arg->last_regno))
5486 arg->last_regno = regno;
5487 insn_insert_operand (arg->insn, operand_base, regno);
5494 /* OP_SAME_RS_RT matcher. */
5497 match_same_rs_rt_operand (struct mips_arg_info *arg,
5498 const struct mips_operand *operand)
5502 if (!match_reg (arg, OP_REG_GP, ®no))
5507 set_insn_error (arg->argnum, _("the source register must not be $0"));
5511 arg->last_regno = regno;
5513 insn_insert_operand (arg->insn, operand, regno | (regno << 5));
5517 /* OP_LWM_SWM_LIST matcher. */
5520 match_lwm_swm_list_operand (struct mips_arg_info *arg,
5521 const struct mips_operand *operand)
5523 unsigned int reglist, sregs, ra, regno1, regno2;
5524 struct mips_arg_info reset;
5527 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
5531 if (regno2 == FP && regno1 >= S0 && regno1 <= S7)
5536 reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1);
5539 while (match_char (arg, ',')
5540 && match_reg_range (arg, OP_REG_GP, ®no1, ®no2));
5543 if (operand->size == 2)
5545 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5551 and any permutations of these. */
5552 if ((reglist & 0xfff1ffff) != 0x80010000)
5555 sregs = (reglist >> 17) & 7;
5560 /* The list must include at least one of ra and s0-sN,
5561 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5562 which are $23 and $30 respectively.) E.g.:
5570 and any permutations of these. */
5571 if ((reglist & 0x3f00ffff) != 0)
5574 ra = (reglist >> 27) & 0x10;
5575 sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
5578 if ((sregs & -sregs) != sregs)
5581 insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra);
5585 /* OP_ENTRY_EXIT_LIST matcher. */
5588 match_entry_exit_operand (struct mips_arg_info *arg,
5589 const struct mips_operand *operand)
5592 bfd_boolean is_exit;
5594 /* The format is the same for both ENTRY and EXIT, but the constraints
5596 is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0;
5597 mask = (is_exit ? 7 << 3 : 0);
5600 unsigned int regno1, regno2;
5601 bfd_boolean is_freg;
5603 if (match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
5605 else if (match_reg_range (arg, OP_REG_FP, ®no1, ®no2))
5610 if (is_exit && is_freg && regno1 == 0 && regno2 < 2)
5613 mask |= (5 + regno2) << 3;
5615 else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7)
5616 mask |= (regno2 - 3) << 3;
5617 else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17)
5618 mask |= (regno2 - 15) << 1;
5619 else if (regno1 == RA && regno2 == RA)
5624 while (match_char (arg, ','));
5626 insn_insert_operand (arg->insn, operand, mask);
5630 /* Encode regular MIPS SAVE/RESTORE instruction operands according to
5631 the argument register mask AMASK, the number of static registers
5632 saved NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5633 respectively, and the frame size FRAME_SIZE. */
5636 mips_encode_save_restore (unsigned int amask, unsigned int nsreg,
5637 unsigned int ra, unsigned int s0, unsigned int s1,
5638 unsigned int frame_size)
5640 return ((nsreg << 23) | ((frame_size & 0xf0) << 15) | (amask << 15)
5641 | (ra << 12) | (s0 << 11) | (s1 << 10) | ((frame_size & 0xf) << 6));
5644 /* Encode MIPS16 SAVE/RESTORE instruction operands according to the
5645 argument register mask AMASK, the number of static registers saved
5646 NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5647 respectively, and the frame size FRAME_SIZE. */
5650 mips16_encode_save_restore (unsigned int amask, unsigned int nsreg,
5651 unsigned int ra, unsigned int s0, unsigned int s1,
5652 unsigned int frame_size)
5656 args = (ra << 6) | (s0 << 5) | (s1 << 4) | (frame_size & 0xf);
5657 if (nsreg || amask || frame_size == 0 || frame_size > 16)
5658 args |= (MIPS16_EXTEND | (nsreg << 24) | (amask << 16)
5659 | ((frame_size & 0xf0) << 16));
5663 /* OP_SAVE_RESTORE_LIST matcher. */
5666 match_save_restore_list_operand (struct mips_arg_info *arg)
5668 unsigned int opcode, args, statics, sregs;
5669 unsigned int num_frame_sizes, num_args, num_statics, num_sregs;
5670 unsigned int arg_mask, ra, s0, s1;
5673 opcode = arg->insn->insn_opcode;
5675 num_frame_sizes = 0;
5684 unsigned int regno1, regno2;
5686 if (arg->token->type == OT_INTEGER)
5688 /* Handle the frame size. */
5689 if (!match_const_int (arg, &frame_size))
5691 num_frame_sizes += 1;
5695 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
5698 while (regno1 <= regno2)
5700 if (regno1 >= 4 && regno1 <= 7)
5702 if (num_frame_sizes == 0)
5704 args |= 1 << (regno1 - 4);
5706 /* statics $a0-$a3 */
5707 statics |= 1 << (regno1 - 4);
5709 else if (regno1 >= 16 && regno1 <= 23)
5711 sregs |= 1 << (regno1 - 16);
5712 else if (regno1 == 30)
5715 else if (regno1 == 31)
5716 /* Add $ra to insn. */
5726 while (match_char (arg, ','));
5728 /* Encode args/statics combination. */
5731 else if (args == 0xf)
5732 /* All $a0-$a3 are args. */
5733 arg_mask = MIPS_SVRS_ALL_ARGS;
5734 else if (statics == 0xf)
5735 /* All $a0-$a3 are statics. */
5736 arg_mask = MIPS_SVRS_ALL_STATICS;
5739 /* Count arg registers. */
5749 /* Count static registers. */
5751 while (statics & 0x8)
5753 statics = (statics << 1) & 0xf;
5759 /* Encode args/statics. */
5760 arg_mask = (num_args << 2) | num_statics;
5763 /* Encode $s0/$s1. */
5764 if (sregs & (1 << 0)) /* $s0 */
5766 if (sregs & (1 << 1)) /* $s1 */
5770 /* Encode $s2-$s8. */
5780 /* Encode frame size. */
5781 if (num_frame_sizes == 0)
5783 set_insn_error (arg->argnum, _("missing frame size"));
5786 if (num_frame_sizes > 1)
5788 set_insn_error (arg->argnum, _("frame size specified twice"));
5791 if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8)
5793 set_insn_error (arg->argnum, _("invalid frame size"));
5798 /* Finally build the instruction. */
5799 if (mips_opts.mips16)
5800 opcode |= mips16_encode_save_restore (arg_mask, num_sregs, ra, s0, s1,
5802 else if (!mips_opts.micromips)
5803 opcode |= mips_encode_save_restore (arg_mask, num_sregs, ra, s0, s1,
5808 arg->insn->insn_opcode = opcode;
5812 /* OP_MDMX_IMM_REG matcher. */
5815 match_mdmx_imm_reg_operand (struct mips_arg_info *arg,
5816 const struct mips_operand *operand)
5818 unsigned int regno, uval;
5820 const struct mips_opcode *opcode;
5822 /* The mips_opcode records whether this is an octobyte or quadhalf
5823 instruction. Start out with that bit in place. */
5824 opcode = arg->insn->insn_mo;
5825 uval = mips_extract_operand (operand, opcode->match);
5826 is_qh = (uval != 0);
5828 if (arg->token->type == OT_REG)
5830 if ((opcode->membership & INSN_5400)
5831 && strcmp (opcode->name, "rzu.ob") == 0)
5833 set_insn_error_i (arg->argnum, _("operand %d must be an immediate"),
5838 if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no))
5842 /* Check whether this is a vector register or a broadcast of
5843 a single element. */
5844 if (arg->token->type == OT_INTEGER_INDEX)
5846 if (arg->token->u.index > (is_qh ? 3 : 7))
5848 set_insn_error (arg->argnum, _("invalid element selector"));
5851 uval |= arg->token->u.index << (is_qh ? 2 : 1) << 5;
5856 /* A full vector. */
5857 if ((opcode->membership & INSN_5400)
5858 && (strcmp (opcode->name, "sll.ob") == 0
5859 || strcmp (opcode->name, "srl.ob") == 0))
5861 set_insn_error_i (arg->argnum, _("operand %d must be scalar"),
5867 uval |= MDMX_FMTSEL_VEC_QH << 5;
5869 uval |= MDMX_FMTSEL_VEC_OB << 5;
5877 if (!match_const_int (arg, &sval))
5879 if (sval < 0 || sval > 31)
5881 match_out_of_range (arg);
5884 uval |= (sval & 31);
5886 uval |= MDMX_FMTSEL_IMM_QH << 5;
5888 uval |= MDMX_FMTSEL_IMM_OB << 5;
5890 insn_insert_operand (arg->insn, operand, uval);
5894 /* OP_IMM_INDEX matcher. */
5897 match_imm_index_operand (struct mips_arg_info *arg,
5898 const struct mips_operand *operand)
5900 unsigned int max_val;
5902 if (arg->token->type != OT_INTEGER_INDEX)
5905 max_val = (1 << operand->size) - 1;
5906 if (arg->token->u.index > max_val)
5908 match_out_of_range (arg);
5911 insn_insert_operand (arg->insn, operand, arg->token->u.index);
5916 /* OP_REG_INDEX matcher. */
5919 match_reg_index_operand (struct mips_arg_info *arg,
5920 const struct mips_operand *operand)
5924 if (arg->token->type != OT_REG_INDEX)
5927 if (!match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no))
5930 insn_insert_operand (arg->insn, operand, regno);
5935 /* OP_PC matcher. */
5938 match_pc_operand (struct mips_arg_info *arg)
5940 if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC))
5948 /* OP_REG28 matcher. */
5951 match_reg28_operand (struct mips_arg_info *arg)
5955 if (arg->token->type == OT_REG
5956 && match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no)
5965 /* OP_NON_ZERO_REG matcher. */
5968 match_non_zero_reg_operand (struct mips_arg_info *arg,
5969 const struct mips_operand *operand)
5973 if (!match_reg (arg, OP_REG_GP, ®no))
5979 arg->last_regno = regno;
5980 insn_insert_operand (arg->insn, operand, regno);
5984 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5985 register that we need to match. */
5988 match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno)
5992 return match_reg (arg, OP_REG_GP, ®no) && regno == other_regno;
5995 /* Try to match a floating-point constant from ARG for LI.S or LI.D.
5996 LENGTH is the length of the value in bytes (4 for float, 8 for double)
5997 and USING_GPRS says whether the destination is a GPR rather than an FPR.
5999 Return the constant in IMM and OFFSET as follows:
6001 - If the constant should be loaded via memory, set IMM to O_absent and
6002 OFFSET to the memory address.
6004 - Otherwise, if the constant should be loaded into two 32-bit registers,
6005 set IMM to the O_constant to load into the high register and OFFSET
6006 to the corresponding value for the low register.
6008 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
6010 These constants only appear as the last operand in an instruction,
6011 and every instruction that accepts them in any variant accepts them
6012 in all variants. This means we don't have to worry about backing out
6013 any changes if the instruction does not match. We just match
6014 unconditionally and report an error if the constant is invalid. */
6017 match_float_constant (struct mips_arg_info *arg, expressionS *imm,
6018 expressionS *offset, int length, bfd_boolean using_gprs)
6023 const char *newname;
6024 unsigned char *data;
6026 /* Where the constant is placed is based on how the MIPS assembler
6029 length == 4 && using_gprs -- immediate value only
6030 length == 8 && using_gprs -- .rdata or immediate value
6031 length == 4 && !using_gprs -- .lit4 or immediate value
6032 length == 8 && !using_gprs -- .lit8 or immediate value
6034 The .lit4 and .lit8 sections are only used if permitted by the
6036 if (arg->token->type != OT_FLOAT)
6038 set_insn_error (arg->argnum, _("floating-point expression required"));
6042 gas_assert (arg->token->u.flt.length == length);
6043 data = arg->token->u.flt.data;
6046 /* Handle 32-bit constants for which an immediate value is best. */
6049 || g_switch_value < 4
6050 || (data[0] == 0 && data[1] == 0)
6051 || (data[2] == 0 && data[3] == 0)))
6053 imm->X_op = O_constant;
6054 if (!target_big_endian)
6055 imm->X_add_number = bfd_getl32 (data);
6057 imm->X_add_number = bfd_getb32 (data);
6058 offset->X_op = O_absent;
6062 /* Handle 64-bit constants for which an immediate value is best. */
6064 && !mips_disable_float_construction
6065 /* Constants can only be constructed in GPRs and copied to FPRs if the
6066 GPRs are at least as wide as the FPRs or MTHC1 is available.
6067 Unlike most tests for 32-bit floating-point registers this check
6068 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
6069 permit 64-bit moves without MXHC1.
6070 Force the constant into memory otherwise. */
6073 || ISA_HAS_MXHC1 (mips_opts.isa)
6075 && ((data[0] == 0 && data[1] == 0)
6076 || (data[2] == 0 && data[3] == 0))
6077 && ((data[4] == 0 && data[5] == 0)
6078 || (data[6] == 0 && data[7] == 0)))
6080 /* The value is simple enough to load with a couple of instructions.
6081 If using 32-bit registers, set IMM to the high order 32 bits and
6082 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
6084 if (GPR_SIZE == 32 || (!using_gprs && FPR_SIZE != 64))
6086 imm->X_op = O_constant;
6087 offset->X_op = O_constant;
6088 if (!target_big_endian)
6090 imm->X_add_number = bfd_getl32 (data + 4);
6091 offset->X_add_number = bfd_getl32 (data);
6095 imm->X_add_number = bfd_getb32 (data);
6096 offset->X_add_number = bfd_getb32 (data + 4);
6098 if (offset->X_add_number == 0)
6099 offset->X_op = O_absent;
6103 imm->X_op = O_constant;
6104 if (!target_big_endian)
6105 imm->X_add_number = bfd_getl64 (data);
6107 imm->X_add_number = bfd_getb64 (data);
6108 offset->X_op = O_absent;
6113 /* Switch to the right section. */
6115 subseg = now_subseg;
6118 gas_assert (!using_gprs && g_switch_value >= 4);
6123 if (using_gprs || g_switch_value < 8)
6124 newname = RDATA_SECTION_NAME;
6129 new_seg = subseg_new (newname, (subsegT) 0);
6130 bfd_set_section_flags (stdoutput, new_seg,
6131 SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA);
6132 frag_align (length == 4 ? 2 : 3, 0, 0);
6133 if (strncmp (TARGET_OS, "elf", 3) != 0)
6134 record_alignment (new_seg, 4);
6136 record_alignment (new_seg, length == 4 ? 2 : 3);
6138 as_bad (_("cannot use `%s' in this section"), arg->insn->insn_mo->name);
6140 /* Set the argument to the current address in the section. */
6141 imm->X_op = O_absent;
6142 offset->X_op = O_symbol;
6143 offset->X_add_symbol = symbol_temp_new_now ();
6144 offset->X_add_number = 0;
6146 /* Put the floating point number into the section. */
6147 p = frag_more (length);
6148 memcpy (p, data, length);
6150 /* Switch back to the original section. */
6151 subseg_set (seg, subseg);
6155 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
6159 match_vu0_suffix_operand (struct mips_arg_info *arg,
6160 const struct mips_operand *operand,
6161 bfd_boolean match_p)
6165 /* The operand can be an XYZW mask or a single 2-bit channel index
6166 (with X being 0). */
6167 gas_assert (operand->size == 2 || operand->size == 4);
6169 /* The suffix can be omitted when it is already part of the opcode. */
6170 if (arg->token->type != OT_CHANNELS)
6173 uval = arg->token->u.channels;
6174 if (operand->size == 2)
6176 /* Check that a single bit is set and convert it into a 2-bit index. */
6177 if ((uval & -uval) != uval)
6179 uval = 4 - ffs (uval);
6182 if (match_p && insn_extract_operand (arg->insn, operand) != uval)
6187 insn_insert_operand (arg->insn, operand, uval);
6191 /* Try to match a token from ARG against OPERAND. Consume the token
6192 and return true on success, otherwise return false. */
6195 match_operand (struct mips_arg_info *arg,
6196 const struct mips_operand *operand)
6198 switch (operand->type)
6201 return match_int_operand (arg, operand);
6204 return match_mapped_int_operand (arg, operand);
6207 return match_msb_operand (arg, operand);
6210 case OP_OPTIONAL_REG:
6211 return match_reg_operand (arg, operand);
6214 return match_reg_pair_operand (arg, operand);
6217 return match_pcrel_operand (arg);
6220 return match_perf_reg_operand (arg, operand);
6222 case OP_ADDIUSP_INT:
6223 return match_addiusp_operand (arg, operand);
6225 case OP_CLO_CLZ_DEST:
6226 return match_clo_clz_dest_operand (arg, operand);
6228 case OP_LWM_SWM_LIST:
6229 return match_lwm_swm_list_operand (arg, operand);
6231 case OP_ENTRY_EXIT_LIST:
6232 return match_entry_exit_operand (arg, operand);
6234 case OP_SAVE_RESTORE_LIST:
6235 return match_save_restore_list_operand (arg);
6237 case OP_MDMX_IMM_REG:
6238 return match_mdmx_imm_reg_operand (arg, operand);
6240 case OP_REPEAT_DEST_REG:
6241 return match_tied_reg_operand (arg, arg->dest_regno);
6243 case OP_REPEAT_PREV_REG:
6244 return match_tied_reg_operand (arg, arg->last_regno);
6247 return match_pc_operand (arg);
6250 return match_reg28_operand (arg);
6253 return match_vu0_suffix_operand (arg, operand, FALSE);
6255 case OP_VU0_MATCH_SUFFIX:
6256 return match_vu0_suffix_operand (arg, operand, TRUE);
6259 return match_imm_index_operand (arg, operand);
6262 return match_reg_index_operand (arg, operand);
6265 return match_same_rs_rt_operand (arg, operand);
6268 return match_check_prev_operand (arg, operand);
6270 case OP_NON_ZERO_REG:
6271 return match_non_zero_reg_operand (arg, operand);
6276 /* ARG is the state after successfully matching an instruction.
6277 Issue any queued-up warnings. */
6280 check_completed_insn (struct mips_arg_info *arg)
6285 as_warn (_("used $at without \".set noat\""));
6287 as_warn (_("used $%u with \".set at=$%u\""), AT, AT);
6291 /* Return true if modifying general-purpose register REG needs a delay. */
6294 reg_needs_delay (unsigned int reg)
6296 unsigned long prev_pinfo;
6298 prev_pinfo = history[0].insn_mo->pinfo;
6299 if (!mips_opts.noreorder
6300 && (((prev_pinfo & INSN_LOAD_MEMORY) && !gpr_interlocks)
6301 || ((prev_pinfo & INSN_LOAD_COPROC) && !cop_interlocks))
6302 && (gpr_write_mask (&history[0]) & (1 << reg)))
6308 /* Classify an instruction according to the FIX_VR4120_* enumeration.
6309 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6310 by VR4120 errata. */
6313 classify_vr4120_insn (const char *name)
6315 if (strncmp (name, "macc", 4) == 0)
6316 return FIX_VR4120_MACC;
6317 if (strncmp (name, "dmacc", 5) == 0)
6318 return FIX_VR4120_DMACC;
6319 if (strncmp (name, "mult", 4) == 0)
6320 return FIX_VR4120_MULT;
6321 if (strncmp (name, "dmult", 5) == 0)
6322 return FIX_VR4120_DMULT;
6323 if (strstr (name, "div"))
6324 return FIX_VR4120_DIV;
6325 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
6326 return FIX_VR4120_MTHILO;
6327 return NUM_FIX_VR4120_CLASSES;
6330 #define INSN_ERET 0x42000018
6331 #define INSN_DERET 0x4200001f
6332 #define INSN_DMULT 0x1c
6333 #define INSN_DMULTU 0x1d
6335 /* Return the number of instructions that must separate INSN1 and INSN2,
6336 where INSN1 is the earlier instruction. Return the worst-case value
6337 for any INSN2 if INSN2 is null. */
6340 insns_between (const struct mips_cl_insn *insn1,
6341 const struct mips_cl_insn *insn2)
6343 unsigned long pinfo1, pinfo2;
6346 /* If INFO2 is null, pessimistically assume that all flags are set for
6347 the second instruction. */
6348 pinfo1 = insn1->insn_mo->pinfo;
6349 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
6351 /* For most targets, write-after-read dependencies on the HI and LO
6352 registers must be separated by at least two instructions. */
6353 if (!hilo_interlocks)
6355 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
6357 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
6361 /* If we're working around r7000 errata, there must be two instructions
6362 between an mfhi or mflo and any instruction that uses the result. */
6363 if (mips_7000_hilo_fix
6364 && !mips_opts.micromips
6365 && MF_HILO_INSN (pinfo1)
6366 && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))))
6369 /* If we're working around 24K errata, one instruction is required
6370 if an ERET or DERET is followed by a branch instruction. */
6371 if (mips_fix_24k && !mips_opts.micromips)
6373 if (insn1->insn_opcode == INSN_ERET
6374 || insn1->insn_opcode == INSN_DERET)
6377 || insn2->insn_opcode == INSN_ERET
6378 || insn2->insn_opcode == INSN_DERET
6379 || delayed_branch_p (insn2))
6384 /* If we're working around PMC RM7000 errata, there must be three
6385 nops between a dmult and a load instruction. */
6386 if (mips_fix_rm7000 && !mips_opts.micromips)
6388 if ((insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULT
6389 || (insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULTU)
6391 if (pinfo2 & INSN_LOAD_MEMORY)
6396 /* If working around VR4120 errata, check for combinations that need
6397 a single intervening instruction. */
6398 if (mips_fix_vr4120 && !mips_opts.micromips)
6400 unsigned int class1, class2;
6402 class1 = classify_vr4120_insn (insn1->insn_mo->name);
6403 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
6407 class2 = classify_vr4120_insn (insn2->insn_mo->name);
6408 if (vr4120_conflicts[class1] & (1 << class2))
6413 if (!HAVE_CODE_COMPRESSION)
6415 /* Check for GPR or coprocessor load delays. All such delays
6416 are on the RT register. */
6417 /* Itbl support may require additional care here. */
6418 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY))
6419 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC)))
6421 if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))
6425 /* Check for generic coprocessor hazards.
6427 This case is not handled very well. There is no special
6428 knowledge of CP0 handling, and the coprocessors other than
6429 the floating point unit are not distinguished at all. */
6430 /* Itbl support may require additional care here. FIXME!
6431 Need to modify this to include knowledge about
6432 user specified delays! */
6433 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE))
6434 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
6436 /* Handle cases where INSN1 writes to a known general coprocessor
6437 register. There must be a one instruction delay before INSN2
6438 if INSN2 reads that register, otherwise no delay is needed. */
6439 mask = fpr_write_mask (insn1);
6442 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
6447 /* Read-after-write dependencies on the control registers
6448 require a two-instruction gap. */
6449 if ((pinfo1 & INSN_WRITE_COND_CODE)
6450 && (pinfo2 & INSN_READ_COND_CODE))
6453 /* We don't know exactly what INSN1 does. If INSN2 is
6454 also a coprocessor instruction, assume there must be
6455 a one instruction gap. */
6456 if (pinfo2 & INSN_COP)
6461 /* Check for read-after-write dependencies on the coprocessor
6462 control registers in cases where INSN1 does not need a general
6463 coprocessor delay. This means that INSN1 is a floating point
6464 comparison instruction. */
6465 /* Itbl support may require additional care here. */
6466 else if (!cop_interlocks
6467 && (pinfo1 & INSN_WRITE_COND_CODE)
6468 && (pinfo2 & INSN_READ_COND_CODE))
6472 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6473 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6475 if ((insn1->insn_mo->pinfo2 & INSN2_FORBIDDEN_SLOT)
6476 && ((pinfo2 & INSN_NO_DELAY_SLOT)
6477 || (insn2 && delayed_branch_p (insn2))))
6483 /* Return the number of nops that would be needed to work around the
6484 VR4130 mflo/mfhi errata if instruction INSN immediately followed
6485 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6486 that are contained within the first IGNORE instructions of HIST. */
6489 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
6490 const struct mips_cl_insn *insn)
6495 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6496 are not affected by the errata. */
6498 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
6499 || strcmp (insn->insn_mo->name, "mtlo") == 0
6500 || strcmp (insn->insn_mo->name, "mthi") == 0))
6503 /* Search for the first MFLO or MFHI. */
6504 for (i = 0; i < MAX_VR4130_NOPS; i++)
6505 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
6507 /* Extract the destination register. */
6508 mask = gpr_write_mask (&hist[i]);
6510 /* No nops are needed if INSN reads that register. */
6511 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
6514 /* ...or if any of the intervening instructions do. */
6515 for (j = 0; j < i; j++)
6516 if (gpr_read_mask (&hist[j]) & mask)
6520 return MAX_VR4130_NOPS - i;
6525 #define BASE_REG_EQ(INSN1, INSN2) \
6526 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
6527 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6529 /* Return the minimum alignment for this store instruction. */
6532 fix_24k_align_to (const struct mips_opcode *mo)
6534 if (strcmp (mo->name, "sh") == 0)
6537 if (strcmp (mo->name, "swc1") == 0
6538 || strcmp (mo->name, "swc2") == 0
6539 || strcmp (mo->name, "sw") == 0
6540 || strcmp (mo->name, "sc") == 0
6541 || strcmp (mo->name, "s.s") == 0)
6544 if (strcmp (mo->name, "sdc1") == 0
6545 || strcmp (mo->name, "sdc2") == 0
6546 || strcmp (mo->name, "s.d") == 0)
6553 struct fix_24k_store_info
6555 /* Immediate offset, if any, for this store instruction. */
6557 /* Alignment required by this store instruction. */
6559 /* True for register offsets. */
6560 int register_offset;
6563 /* Comparison function used by qsort. */
6566 fix_24k_sort (const void *a, const void *b)
6568 const struct fix_24k_store_info *pos1 = a;
6569 const struct fix_24k_store_info *pos2 = b;
6571 return (pos1->off - pos2->off);
6574 /* INSN is a store instruction. Try to record the store information
6575 in STINFO. Return false if the information isn't known. */
6578 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
6579 const struct mips_cl_insn *insn)
6581 /* The instruction must have a known offset. */
6582 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
6585 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
6586 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
6590 /* Return the number of nops that would be needed to work around the 24k
6591 "lost data on stores during refill" errata if instruction INSN
6592 immediately followed the 2 instructions described by HIST.
6593 Ignore hazards that are contained within the first IGNORE
6594 instructions of HIST.
6596 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6597 for the data cache refills and store data. The following describes
6598 the scenario where the store data could be lost.
6600 * A data cache miss, due to either a load or a store, causing fill
6601 data to be supplied by the memory subsystem
6602 * The first three doublewords of fill data are returned and written
6604 * A sequence of four stores occurs in consecutive cycles around the
6605 final doubleword of the fill:
6609 * Zero, One or more instructions
6612 The four stores A-D must be to different doublewords of the line that
6613 is being filled. The fourth instruction in the sequence above permits
6614 the fill of the final doubleword to be transferred from the FSB into
6615 the cache. In the sequence above, the stores may be either integer
6616 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6617 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6618 different doublewords on the line. If the floating point unit is
6619 running in 1:2 mode, it is not possible to create the sequence above
6620 using only floating point store instructions.
6622 In this case, the cache line being filled is incorrectly marked
6623 invalid, thereby losing the data from any store to the line that
6624 occurs between the original miss and the completion of the five
6625 cycle sequence shown above.
6627 The workarounds are:
6629 * Run the data cache in write-through mode.
6630 * Insert a non-store instruction between
6631 Store A and Store B or Store B and Store C. */
6634 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
6635 const struct mips_cl_insn *insn)
6637 struct fix_24k_store_info pos[3];
6638 int align, i, base_offset;
6643 /* If the previous instruction wasn't a store, there's nothing to
6645 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
6648 /* If the instructions after the previous one are unknown, we have
6649 to assume the worst. */
6653 /* Check whether we are dealing with three consecutive stores. */
6654 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
6655 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
6658 /* If we don't know the relationship between the store addresses,
6659 assume the worst. */
6660 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
6661 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
6664 if (!fix_24k_record_store_info (&pos[0], insn)
6665 || !fix_24k_record_store_info (&pos[1], &hist[0])
6666 || !fix_24k_record_store_info (&pos[2], &hist[1]))
6669 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
6671 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6672 X bytes and such that the base register + X is known to be aligned
6675 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
6679 align = pos[0].align_to;
6680 base_offset = pos[0].off;
6681 for (i = 1; i < 3; i++)
6682 if (align < pos[i].align_to)
6684 align = pos[i].align_to;
6685 base_offset = pos[i].off;
6687 for (i = 0; i < 3; i++)
6688 pos[i].off -= base_offset;
6691 pos[0].off &= ~align + 1;
6692 pos[1].off &= ~align + 1;
6693 pos[2].off &= ~align + 1;
6695 /* If any two stores write to the same chunk, they also write to the
6696 same doubleword. The offsets are still sorted at this point. */
6697 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
6700 /* A range of at least 9 bytes is needed for the stores to be in
6701 non-overlapping doublewords. */
6702 if (pos[2].off - pos[0].off <= 8)
6705 if (pos[2].off - pos[1].off >= 24
6706 || pos[1].off - pos[0].off >= 24
6707 || pos[2].off - pos[0].off >= 32)
6713 /* Return the number of nops that would be needed if instruction INSN
6714 immediately followed the MAX_NOPS instructions given by HIST,
6715 where HIST[0] is the most recent instruction. Ignore hazards
6716 between INSN and the first IGNORE instructions in HIST.
6718 If INSN is null, return the worse-case number of nops for any
6722 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
6723 const struct mips_cl_insn *insn)
6725 int i, nops, tmp_nops;
6728 for (i = ignore; i < MAX_DELAY_NOPS; i++)
6730 tmp_nops = insns_between (hist + i, insn) - i;
6731 if (tmp_nops > nops)
6735 if (mips_fix_vr4130 && !mips_opts.micromips)
6737 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
6738 if (tmp_nops > nops)
6742 if (mips_fix_24k && !mips_opts.micromips)
6744 tmp_nops = nops_for_24k (ignore, hist, insn);
6745 if (tmp_nops > nops)
6752 /* The variable arguments provide NUM_INSNS extra instructions that
6753 might be added to HIST. Return the largest number of nops that
6754 would be needed after the extended sequence, ignoring hazards
6755 in the first IGNORE instructions. */
6758 nops_for_sequence (int num_insns, int ignore,
6759 const struct mips_cl_insn *hist, ...)
6762 struct mips_cl_insn buffer[MAX_NOPS];
6763 struct mips_cl_insn *cursor;
6766 va_start (args, hist);
6767 cursor = buffer + num_insns;
6768 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
6769 while (cursor > buffer)
6770 *--cursor = *va_arg (args, const struct mips_cl_insn *);
6772 nops = nops_for_insn (ignore, buffer, NULL);
6777 /* Like nops_for_insn, but if INSN is a branch, take into account the
6778 worst-case delay for the branch target. */
6781 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
6782 const struct mips_cl_insn *insn)
6786 nops = nops_for_insn (ignore, hist, insn);
6787 if (delayed_branch_p (insn))
6789 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
6790 hist, insn, get_delay_slot_nop (insn));
6791 if (tmp_nops > nops)
6794 else if (compact_branch_p (insn))
6796 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
6797 if (tmp_nops > nops)
6803 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6806 fix_loongson2f_nop (struct mips_cl_insn * ip)
6808 gas_assert (!HAVE_CODE_COMPRESSION);
6809 if (strcmp (ip->insn_mo->name, "nop") == 0)
6810 ip->insn_opcode = LOONGSON2F_NOP_INSN;
6813 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6814 jr target pc &= 'hffff_ffff_cfff_ffff. */
6817 fix_loongson2f_jump (struct mips_cl_insn * ip)
6819 gas_assert (!HAVE_CODE_COMPRESSION);
6820 if (strcmp (ip->insn_mo->name, "j") == 0
6821 || strcmp (ip->insn_mo->name, "jr") == 0
6822 || strcmp (ip->insn_mo->name, "jalr") == 0)
6830 sreg = EXTRACT_OPERAND (0, RS, *ip);
6831 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
6834 ep.X_op = O_constant;
6835 ep.X_add_number = 0xcfff0000;
6836 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
6837 ep.X_add_number = 0xffff;
6838 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
6839 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
6844 fix_loongson2f (struct mips_cl_insn * ip)
6846 if (mips_fix_loongson2f_nop)
6847 fix_loongson2f_nop (ip);
6849 if (mips_fix_loongson2f_jump)
6850 fix_loongson2f_jump (ip);
6853 /* IP is a branch that has a delay slot, and we need to fill it
6854 automatically. Return true if we can do that by swapping IP
6855 with the previous instruction.
6856 ADDRESS_EXPR is an operand of the instruction to be used with
6860 can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
6861 bfd_reloc_code_real_type *reloc_type)
6863 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
6864 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
6865 unsigned int fpr_read, prev_fpr_write;
6867 /* -O2 and above is required for this optimization. */
6868 if (mips_optimize < 2)
6871 /* If we have seen .set volatile or .set nomove, don't optimize. */
6872 if (mips_opts.nomove)
6875 /* We can't swap if the previous instruction's position is fixed. */
6876 if (history[0].fixed_p)
6879 /* If the previous previous insn was in a .set noreorder, we can't
6880 swap. Actually, the MIPS assembler will swap in this situation.
6881 However, gcc configured -with-gnu-as will generate code like
6889 in which we can not swap the bne and INSN. If gcc is not configured
6890 -with-gnu-as, it does not output the .set pseudo-ops. */
6891 if (history[1].noreorder_p)
6894 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6895 This means that the previous instruction was a 4-byte one anyhow. */
6896 if (mips_opts.mips16 && history[0].fixp[0])
6899 /* If the branch is itself the target of a branch, we can not swap.
6900 We cheat on this; all we check for is whether there is a label on
6901 this instruction. If there are any branches to anything other than
6902 a label, users must use .set noreorder. */
6903 if (seg_info (now_seg)->label_list)
6906 /* If the previous instruction is in a variant frag other than this
6907 branch's one, we cannot do the swap. This does not apply to
6908 MIPS16 code, which uses variant frags for different purposes. */
6909 if (!mips_opts.mips16
6911 && history[0].frag->fr_type == rs_machine_dependent)
6914 /* We do not swap with instructions that cannot architecturally
6915 be placed in a branch delay slot, such as SYNC or ERET. We
6916 also refrain from swapping with a trap instruction, since it
6917 complicates trap handlers to have the trap instruction be in
6919 prev_pinfo = history[0].insn_mo->pinfo;
6920 if (prev_pinfo & INSN_NO_DELAY_SLOT)
6923 /* Check for conflicts between the branch and the instructions
6924 before the candidate delay slot. */
6925 if (nops_for_insn (0, history + 1, ip) > 0)
6928 /* Check for conflicts between the swapped sequence and the
6929 target of the branch. */
6930 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
6933 /* If the branch reads a register that the previous
6934 instruction sets, we can not swap. */
6935 gpr_read = gpr_read_mask (ip);
6936 prev_gpr_write = gpr_write_mask (&history[0]);
6937 if (gpr_read & prev_gpr_write)
6940 fpr_read = fpr_read_mask (ip);
6941 prev_fpr_write = fpr_write_mask (&history[0]);
6942 if (fpr_read & prev_fpr_write)
6945 /* If the branch writes a register that the previous
6946 instruction sets, we can not swap. */
6947 gpr_write = gpr_write_mask (ip);
6948 if (gpr_write & prev_gpr_write)
6951 /* If the branch writes a register that the previous
6952 instruction reads, we can not swap. */
6953 prev_gpr_read = gpr_read_mask (&history[0]);
6954 if (gpr_write & prev_gpr_read)
6957 /* If one instruction sets a condition code and the
6958 other one uses a condition code, we can not swap. */
6959 pinfo = ip->insn_mo->pinfo;
6960 if ((pinfo & INSN_READ_COND_CODE)
6961 && (prev_pinfo & INSN_WRITE_COND_CODE))
6963 if ((pinfo & INSN_WRITE_COND_CODE)
6964 && (prev_pinfo & INSN_READ_COND_CODE))
6967 /* If the previous instruction uses the PC, we can not swap. */
6968 prev_pinfo2 = history[0].insn_mo->pinfo2;
6969 if (prev_pinfo2 & INSN2_READ_PC)
6972 /* If the previous instruction has an incorrect size for a fixed
6973 branch delay slot in microMIPS mode, we cannot swap. */
6974 pinfo2 = ip->insn_mo->pinfo2;
6975 if (mips_opts.micromips
6976 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
6977 && insn_length (history) != 2)
6979 if (mips_opts.micromips
6980 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
6981 && insn_length (history) != 4)
6984 /* On R5900 short loops need to be fixed by inserting a nop in
6985 the branch delay slots.
6986 A short loop can be terminated too early. */
6987 if (mips_opts.arch == CPU_R5900
6988 /* Check if instruction has a parameter, ignore "j $31". */
6989 && (address_expr != NULL)
6990 /* Parameter must be 16 bit. */
6991 && (*reloc_type == BFD_RELOC_16_PCREL_S2)
6992 /* Branch to same segment. */
6993 && (S_GET_SEGMENT (address_expr->X_add_symbol) == now_seg)
6994 /* Branch to same code fragment. */
6995 && (symbol_get_frag (address_expr->X_add_symbol) == frag_now)
6996 /* Can only calculate branch offset if value is known. */
6997 && symbol_constant_p (address_expr->X_add_symbol)
6998 /* Check if branch is really conditional. */
6999 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */
7000 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */
7001 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
7004 /* Check if loop is shorter than 6 instructions including
7005 branch and delay slot. */
7006 distance = frag_now_fix () - S_GET_VALUE (address_expr->X_add_symbol);
7013 /* When the loop includes branches or jumps,
7014 it is not a short loop. */
7015 for (i = 0; i < (distance / 4); i++)
7017 if ((history[i].cleared_p)
7018 || delayed_branch_p (&history[i]))
7026 /* Insert nop after branch to fix short loop. */
7035 /* Decide how we should add IP to the instruction stream.
7036 ADDRESS_EXPR is an operand of the instruction to be used with
7039 static enum append_method
7040 get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
7041 bfd_reloc_code_real_type *reloc_type)
7043 /* The relaxed version of a macro sequence must be inherently
7045 if (mips_relax.sequence == 2)
7048 /* We must not dabble with instructions in a ".set noreorder" block. */
7049 if (mips_opts.noreorder)
7052 /* Otherwise, it's our responsibility to fill branch delay slots. */
7053 if (delayed_branch_p (ip))
7055 if (!branch_likely_p (ip)
7056 && can_swap_branch_p (ip, address_expr, reloc_type))
7059 if (mips_opts.mips16
7060 && ISA_SUPPORTS_MIPS16E
7061 && gpr_read_mask (ip) != 0)
7062 return APPEND_ADD_COMPACT;
7064 if (mips_opts.micromips
7065 && ((ip->insn_opcode & 0xffe0) == 0x4580
7066 || (!forced_insn_length
7067 && ((ip->insn_opcode & 0xfc00) == 0xcc00
7068 || (ip->insn_opcode & 0xdc00) == 0x8c00))
7069 || (ip->insn_opcode & 0xdfe00000) == 0x94000000
7070 || (ip->insn_opcode & 0xdc1f0000) == 0x94000000))
7071 return APPEND_ADD_COMPACT;
7073 return APPEND_ADD_WITH_NOP;
7079 /* IP is an instruction whose opcode we have just changed, END points
7080 to the end of the opcode table processed. Point IP->insn_mo to the
7081 new opcode's definition. */
7084 find_altered_opcode (struct mips_cl_insn *ip, const struct mips_opcode *end)
7086 const struct mips_opcode *mo;
7088 for (mo = ip->insn_mo; mo < end; mo++)
7089 if (mo->pinfo != INSN_MACRO
7090 && (ip->insn_opcode & mo->mask) == mo->match)
7098 /* IP is a MIPS16 instruction whose opcode we have just changed.
7099 Point IP->insn_mo to the new opcode's definition. */
7102 find_altered_mips16_opcode (struct mips_cl_insn *ip)
7104 find_altered_opcode (ip, &mips16_opcodes[bfd_mips16_num_opcodes]);
7107 /* IP is a microMIPS instruction whose opcode we have just changed.
7108 Point IP->insn_mo to the new opcode's definition. */
7111 find_altered_micromips_opcode (struct mips_cl_insn *ip)
7113 find_altered_opcode (ip, µmips_opcodes[bfd_micromips_num_opcodes]);
7116 /* For microMIPS macros, we need to generate a local number label
7117 as the target of branches. */
7118 #define MICROMIPS_LABEL_CHAR '\037'
7119 static unsigned long micromips_target_label;
7120 static char micromips_target_name[32];
7123 micromips_label_name (void)
7125 char *p = micromips_target_name;
7126 char symbol_name_temporary[24];
7134 l = micromips_target_label;
7135 #ifdef LOCAL_LABEL_PREFIX
7136 *p++ = LOCAL_LABEL_PREFIX;
7139 *p++ = MICROMIPS_LABEL_CHAR;
7142 symbol_name_temporary[i++] = l % 10 + '0';
7147 *p++ = symbol_name_temporary[--i];
7150 return micromips_target_name;
7154 micromips_label_expr (expressionS *label_expr)
7156 label_expr->X_op = O_symbol;
7157 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
7158 label_expr->X_add_number = 0;
7162 micromips_label_inc (void)
7164 micromips_target_label++;
7165 *micromips_target_name = '\0';
7169 micromips_add_label (void)
7173 s = colon (micromips_label_name ());
7174 micromips_label_inc ();
7175 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
7178 /* If assembling microMIPS code, then return the microMIPS reloc
7179 corresponding to the requested one if any. Otherwise return
7180 the reloc unchanged. */
7182 static bfd_reloc_code_real_type
7183 micromips_map_reloc (bfd_reloc_code_real_type reloc)
7185 static const bfd_reloc_code_real_type relocs[][2] =
7187 /* Keep sorted incrementally by the left-hand key. */
7188 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
7189 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
7190 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
7191 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
7192 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
7193 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
7194 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
7195 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
7196 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
7197 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
7198 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
7199 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
7200 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
7201 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
7202 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
7203 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
7204 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
7205 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
7206 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
7207 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
7208 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
7209 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
7210 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
7211 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
7212 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
7213 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
7214 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
7216 bfd_reloc_code_real_type r;
7219 if (!mips_opts.micromips)
7221 for (i = 0; i < ARRAY_SIZE (relocs); i++)
7227 return relocs[i][1];
7232 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
7233 Return true on success, storing the resolved value in RESULT. */
7236 calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
7241 case BFD_RELOC_MIPS_HIGHEST:
7242 case BFD_RELOC_MICROMIPS_HIGHEST:
7243 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff;
7246 case BFD_RELOC_MIPS_HIGHER:
7247 case BFD_RELOC_MICROMIPS_HIGHER:
7248 *result = ((operand + 0x80008000ull) >> 32) & 0xffff;
7251 case BFD_RELOC_HI16_S:
7252 case BFD_RELOC_HI16_S_PCREL:
7253 case BFD_RELOC_MICROMIPS_HI16_S:
7254 case BFD_RELOC_MIPS16_HI16_S:
7255 *result = ((operand + 0x8000) >> 16) & 0xffff;
7258 case BFD_RELOC_HI16:
7259 case BFD_RELOC_MICROMIPS_HI16:
7260 case BFD_RELOC_MIPS16_HI16:
7261 *result = (operand >> 16) & 0xffff;
7264 case BFD_RELOC_LO16:
7265 case BFD_RELOC_LO16_PCREL:
7266 case BFD_RELOC_MICROMIPS_LO16:
7267 case BFD_RELOC_MIPS16_LO16:
7268 *result = operand & 0xffff;
7271 case BFD_RELOC_UNUSED:
7280 /* Output an instruction. IP is the instruction information.
7281 ADDRESS_EXPR is an operand of the instruction to be used with
7282 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
7283 a macro expansion. */
7286 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
7287 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
7289 unsigned long prev_pinfo2, pinfo;
7290 bfd_boolean relaxed_branch = FALSE;
7291 enum append_method method;
7292 bfd_boolean relax32;
7295 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
7296 fix_loongson2f (ip);
7298 file_ase_mips16 |= mips_opts.mips16;
7299 file_ase_micromips |= mips_opts.micromips;
7301 prev_pinfo2 = history[0].insn_mo->pinfo2;
7302 pinfo = ip->insn_mo->pinfo;
7304 /* Don't raise alarm about `nods' frags as they'll fill in the right
7305 kind of nop in relaxation if required. */
7306 if (mips_opts.micromips
7308 && !(history[0].frag
7309 && history[0].frag->fr_type == rs_machine_dependent
7310 && RELAX_MICROMIPS_P (history[0].frag->fr_subtype)
7311 && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype))
7312 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
7313 && micromips_insn_length (ip->insn_mo) != 2)
7314 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
7315 && micromips_insn_length (ip->insn_mo) != 4)))
7316 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
7317 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
7319 if (address_expr == NULL)
7321 else if (reloc_type[0] <= BFD_RELOC_UNUSED
7322 && reloc_type[1] == BFD_RELOC_UNUSED
7323 && reloc_type[2] == BFD_RELOC_UNUSED
7324 && address_expr->X_op == O_constant)
7326 switch (*reloc_type)
7328 case BFD_RELOC_MIPS_JMP:
7332 /* Shift is 2, unusually, for microMIPS JALX. */
7333 shift = (mips_opts.micromips
7334 && strcmp (ip->insn_mo->name, "jalx") != 0) ? 1 : 2;
7335 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7336 as_bad (_("jump to misaligned address (0x%lx)"),
7337 (unsigned long) address_expr->X_add_number);
7338 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7344 case BFD_RELOC_MIPS16_JMP:
7345 if ((address_expr->X_add_number & 3) != 0)
7346 as_bad (_("jump to misaligned address (0x%lx)"),
7347 (unsigned long) address_expr->X_add_number);
7349 (((address_expr->X_add_number & 0x7c0000) << 3)
7350 | ((address_expr->X_add_number & 0xf800000) >> 7)
7351 | ((address_expr->X_add_number & 0x3fffc) >> 2));
7355 case BFD_RELOC_16_PCREL_S2:
7359 shift = mips_opts.micromips ? 1 : 2;
7360 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7361 as_bad (_("branch to misaligned address (0x%lx)"),
7362 (unsigned long) address_expr->X_add_number);
7363 if (!mips_relax_branch)
7365 if ((address_expr->X_add_number + (1 << (shift + 15)))
7366 & ~((1 << (shift + 16)) - 1))
7367 as_bad (_("branch address range overflow (0x%lx)"),
7368 (unsigned long) address_expr->X_add_number);
7369 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7375 case BFD_RELOC_MIPS_21_PCREL_S2:
7380 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7381 as_bad (_("branch to misaligned address (0x%lx)"),
7382 (unsigned long) address_expr->X_add_number);
7383 if ((address_expr->X_add_number + (1 << (shift + 20)))
7384 & ~((1 << (shift + 21)) - 1))
7385 as_bad (_("branch address range overflow (0x%lx)"),
7386 (unsigned long) address_expr->X_add_number);
7387 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7392 case BFD_RELOC_MIPS_26_PCREL_S2:
7397 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7398 as_bad (_("branch to misaligned address (0x%lx)"),
7399 (unsigned long) address_expr->X_add_number);
7400 if ((address_expr->X_add_number + (1 << (shift + 25)))
7401 & ~((1 << (shift + 26)) - 1))
7402 as_bad (_("branch address range overflow (0x%lx)"),
7403 (unsigned long) address_expr->X_add_number);
7404 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7413 if (calculate_reloc (*reloc_type, address_expr->X_add_number,
7416 ip->insn_opcode |= value & 0xffff;
7424 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
7426 /* There are a lot of optimizations we could do that we don't.
7427 In particular, we do not, in general, reorder instructions.
7428 If you use gcc with optimization, it will reorder
7429 instructions and generally do much more optimization then we
7430 do here; repeating all that work in the assembler would only
7431 benefit hand written assembly code, and does not seem worth
7433 int nops = (mips_optimize == 0
7434 ? nops_for_insn (0, history, NULL)
7435 : nops_for_insn_or_target (0, history, ip));
7439 unsigned long old_frag_offset;
7442 old_frag = frag_now;
7443 old_frag_offset = frag_now_fix ();
7445 for (i = 0; i < nops; i++)
7446 add_fixed_insn (NOP_INSN);
7447 insert_into_history (0, nops, NOP_INSN);
7451 listing_prev_line ();
7452 /* We may be at the start of a variant frag. In case we
7453 are, make sure there is enough space for the frag
7454 after the frags created by listing_prev_line. The
7455 argument to frag_grow here must be at least as large
7456 as the argument to all other calls to frag_grow in
7457 this file. We don't have to worry about being in the
7458 middle of a variant frag, because the variants insert
7459 all needed nop instructions themselves. */
7463 mips_move_text_labels ();
7465 #ifndef NO_ECOFF_DEBUGGING
7466 if (ECOFF_DEBUGGING)
7467 ecoff_fix_loc (old_frag, old_frag_offset);
7471 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
7475 /* Work out how many nops in prev_nop_frag are needed by IP,
7476 ignoring hazards generated by the first prev_nop_frag_since
7478 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
7479 gas_assert (nops <= prev_nop_frag_holds);
7481 /* Enforce NOPS as a minimum. */
7482 if (nops > prev_nop_frag_required)
7483 prev_nop_frag_required = nops;
7485 if (prev_nop_frag_holds == prev_nop_frag_required)
7487 /* Settle for the current number of nops. Update the history
7488 accordingly (for the benefit of any future .set reorder code). */
7489 prev_nop_frag = NULL;
7490 insert_into_history (prev_nop_frag_since,
7491 prev_nop_frag_holds, NOP_INSN);
7495 /* Allow this instruction to replace one of the nops that was
7496 tentatively added to prev_nop_frag. */
7497 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
7498 prev_nop_frag_holds--;
7499 prev_nop_frag_since++;
7503 method = get_append_method (ip, address_expr, reloc_type);
7504 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
7506 dwarf2_emit_insn (0);
7507 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7508 so "move" the instruction address accordingly.
7510 Also, it doesn't seem appropriate for the assembler to reorder .loc
7511 entries. If this instruction is a branch that we are going to swap
7512 with the previous instruction, the two instructions should be
7513 treated as a unit, and the debug information for both instructions
7514 should refer to the start of the branch sequence. Using the
7515 current position is certainly wrong when swapping a 32-bit branch
7516 and a 16-bit delay slot, since the current position would then be
7517 in the middle of a branch. */
7518 dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp);
7520 relax32 = (mips_relax_branch
7521 /* Don't try branch relaxation within .set nomacro, or within
7522 .set noat if we use $at for PIC computations. If it turns
7523 out that the branch was out-of-range, we'll get an error. */
7524 && !mips_opts.warn_about_macros
7525 && (mips_opts.at || mips_pic == NO_PIC)
7526 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7527 as they have no complementing branches. */
7528 && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP)));
7530 if (!HAVE_CODE_COMPRESSION
7533 && *reloc_type == BFD_RELOC_16_PCREL_S2
7534 && delayed_branch_p (ip))
7536 relaxed_branch = TRUE;
7537 add_relaxed_insn (ip, (relaxed_branch_length
7539 uncond_branch_p (ip) ? -1
7540 : branch_likely_p (ip) ? 1
7543 (AT, mips_pic != NO_PIC,
7544 uncond_branch_p (ip),
7545 branch_likely_p (ip),
7546 pinfo & INSN_WRITE_GPR_31,
7548 address_expr->X_add_symbol,
7549 address_expr->X_add_number);
7550 *reloc_type = BFD_RELOC_UNUSED;
7552 else if (mips_opts.micromips
7554 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
7555 || *reloc_type > BFD_RELOC_UNUSED)
7556 && (delayed_branch_p (ip) || compact_branch_p (ip))
7557 /* Don't try branch relaxation when users specify
7558 16-bit/32-bit instructions. */
7559 && !forced_insn_length)
7561 bfd_boolean relax16 = (method != APPEND_ADD_COMPACT
7562 && *reloc_type > BFD_RELOC_UNUSED);
7563 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
7564 int uncond = uncond_branch_p (ip) ? -1 : 0;
7565 int compact = compact_branch_p (ip) || method == APPEND_ADD_COMPACT;
7566 int nods = method == APPEND_ADD_WITH_NOP;
7567 int al = pinfo & INSN_WRITE_GPR_31;
7568 int length32 = nods ? 8 : 4;
7570 gas_assert (address_expr != NULL);
7571 gas_assert (!mips_relax.sequence);
7573 relaxed_branch = TRUE;
7575 method = APPEND_ADD;
7577 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
7578 add_relaxed_insn (ip, length32, relax16 ? 2 : 4,
7579 RELAX_MICROMIPS_ENCODE (type, AT, mips_opts.insn32,
7581 uncond, compact, al, nods,
7583 address_expr->X_add_symbol,
7584 address_expr->X_add_number);
7585 *reloc_type = BFD_RELOC_UNUSED;
7587 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
7589 bfd_boolean require_unextended;
7590 bfd_boolean require_extended;
7594 if (forced_insn_length != 0)
7596 require_unextended = forced_insn_length == 2;
7597 require_extended = forced_insn_length == 4;
7601 require_unextended = (mips_opts.noautoextend
7602 && !mips_opcode_32bit_p (ip->insn_mo));
7603 require_extended = 0;
7606 /* We need to set up a variant frag. */
7607 gas_assert (address_expr != NULL);
7608 /* Pass any `O_symbol' expression unchanged as an `expr_section'
7609 symbol created by `make_expr_symbol' may not get a necessary
7610 external relocation produced. */
7611 if (address_expr->X_op == O_symbol)
7613 symbol = address_expr->X_add_symbol;
7614 offset = address_expr->X_add_number;
7618 symbol = make_expr_symbol (address_expr);
7619 symbol_append (symbol, symbol_lastP, &symbol_rootP, &symbol_lastP);
7622 add_relaxed_insn (ip, 12, 0,
7624 (*reloc_type - BFD_RELOC_UNUSED,
7625 mips_opts.ase & ASE_MIPS16E2,
7628 mips_opts.warn_about_macros,
7629 require_unextended, require_extended,
7630 delayed_branch_p (&history[0]),
7631 history[0].mips16_absolute_jump_p),
7634 else if (mips_opts.mips16 && insn_length (ip) == 2)
7636 if (!delayed_branch_p (ip))
7637 /* Make sure there is enough room to swap this instruction with
7638 a following jump instruction. */
7640 add_fixed_insn (ip);
7644 if (mips_opts.mips16
7645 && mips_opts.noreorder
7646 && delayed_branch_p (&history[0]))
7647 as_warn (_("extended instruction in delay slot"));
7649 if (mips_relax.sequence)
7651 /* If we've reached the end of this frag, turn it into a variant
7652 frag and record the information for the instructions we've
7654 if (frag_room () < 4)
7655 relax_close_frag ();
7656 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
7659 if (mips_relax.sequence != 2)
7661 if (mips_macro_warning.first_insn_sizes[0] == 0)
7662 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
7663 mips_macro_warning.sizes[0] += insn_length (ip);
7664 mips_macro_warning.insns[0]++;
7666 if (mips_relax.sequence != 1)
7668 if (mips_macro_warning.first_insn_sizes[1] == 0)
7669 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
7670 mips_macro_warning.sizes[1] += insn_length (ip);
7671 mips_macro_warning.insns[1]++;
7674 if (mips_opts.mips16)
7677 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
7679 add_fixed_insn (ip);
7682 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
7684 bfd_reloc_code_real_type final_type[3];
7685 reloc_howto_type *howto0;
7686 reloc_howto_type *howto;
7689 /* Perform any necessary conversion to microMIPS relocations
7690 and find out how many relocations there actually are. */
7691 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
7692 final_type[i] = micromips_map_reloc (reloc_type[i]);
7694 /* In a compound relocation, it is the final (outermost)
7695 operator that determines the relocated field. */
7696 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
7701 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
7702 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
7703 bfd_get_reloc_size (howto),
7705 howto0 && howto0->pc_relative,
7707 /* Record non-PIC mode in `fx_tcbit2' for `md_apply_fix'. */
7708 ip->fixp[0]->fx_tcbit2 = mips_pic == NO_PIC;
7710 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
7711 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
7712 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
7714 /* These relocations can have an addend that won't fit in
7715 4 octets for 64bit assembly. */
7717 && ! howto->partial_inplace
7718 && (reloc_type[0] == BFD_RELOC_16
7719 || reloc_type[0] == BFD_RELOC_32
7720 || reloc_type[0] == BFD_RELOC_MIPS_JMP
7721 || reloc_type[0] == BFD_RELOC_GPREL16
7722 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
7723 || reloc_type[0] == BFD_RELOC_GPREL32
7724 || reloc_type[0] == BFD_RELOC_64
7725 || reloc_type[0] == BFD_RELOC_CTOR
7726 || reloc_type[0] == BFD_RELOC_MIPS_SUB
7727 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
7728 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
7729 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
7730 || reloc_type[0] == BFD_RELOC_MIPS_REL16
7731 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
7732 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
7733 || hi16_reloc_p (reloc_type[0])
7734 || lo16_reloc_p (reloc_type[0])))
7735 ip->fixp[0]->fx_no_overflow = 1;
7737 /* These relocations can have an addend that won't fit in 2 octets. */
7738 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
7739 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1)
7740 ip->fixp[0]->fx_no_overflow = 1;
7742 if (mips_relax.sequence)
7744 if (mips_relax.first_fixup == 0)
7745 mips_relax.first_fixup = ip->fixp[0];
7747 else if (reloc_needs_lo_p (*reloc_type))
7749 struct mips_hi_fixup *hi_fixup;
7751 /* Reuse the last entry if it already has a matching %lo. */
7752 hi_fixup = mips_hi_fixup_list;
7754 || !fixup_has_matching_lo_p (hi_fixup->fixp))
7756 hi_fixup = XNEW (struct mips_hi_fixup);
7757 hi_fixup->next = mips_hi_fixup_list;
7758 mips_hi_fixup_list = hi_fixup;
7760 hi_fixup->fixp = ip->fixp[0];
7761 hi_fixup->seg = now_seg;
7764 /* Add fixups for the second and third relocations, if given.
7765 Note that the ABI allows the second relocation to be
7766 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
7767 moment we only use RSS_UNDEF, but we could add support
7768 for the others if it ever becomes necessary. */
7769 for (i = 1; i < 3; i++)
7770 if (reloc_type[i] != BFD_RELOC_UNUSED)
7772 ip->fixp[i] = fix_new (ip->frag, ip->where,
7773 ip->fixp[0]->fx_size, NULL, 0,
7774 FALSE, final_type[i]);
7776 /* Use fx_tcbit to mark compound relocs. */
7777 ip->fixp[0]->fx_tcbit = 1;
7778 ip->fixp[i]->fx_tcbit = 1;
7782 /* Update the register mask information. */
7783 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
7784 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
7789 insert_into_history (0, 1, ip);
7792 case APPEND_ADD_WITH_NOP:
7794 struct mips_cl_insn *nop;
7796 insert_into_history (0, 1, ip);
7797 nop = get_delay_slot_nop (ip);
7798 add_fixed_insn (nop);
7799 insert_into_history (0, 1, nop);
7800 if (mips_relax.sequence)
7801 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
7805 case APPEND_ADD_COMPACT:
7806 /* Convert MIPS16 jr/jalr into a "compact" jump. */
7807 if (mips_opts.mips16)
7809 ip->insn_opcode |= 0x0080;
7810 find_altered_mips16_opcode (ip);
7812 /* Convert microMIPS instructions. */
7813 else if (mips_opts.micromips)
7816 if ((ip->insn_opcode & 0xffe0) == 0x4580)
7817 ip->insn_opcode |= 0x0020;
7819 else if ((ip->insn_opcode & 0xfc00) == 0xcc00)
7820 ip->insn_opcode = 0x40e00000;
7821 /* beqz16->beqzc, bnez16->bnezc */
7822 else if ((ip->insn_opcode & 0xdc00) == 0x8c00)
7824 unsigned long regno;
7826 regno = ip->insn_opcode >> MICROMIPSOP_SH_MD;
7827 regno &= MICROMIPSOP_MASK_MD;
7828 regno = micromips_to_32_reg_d_map[regno];
7829 ip->insn_opcode = (((ip->insn_opcode << 9) & 0x00400000)
7830 | (regno << MICROMIPSOP_SH_RS)
7831 | 0x40a00000) ^ 0x00400000;
7833 /* beqz->beqzc, bnez->bnezc */
7834 else if ((ip->insn_opcode & 0xdfe00000) == 0x94000000)
7835 ip->insn_opcode = ((ip->insn_opcode & 0x001f0000)
7836 | ((ip->insn_opcode >> 7) & 0x00400000)
7837 | 0x40a00000) ^ 0x00400000;
7838 /* beq $0->beqzc, bne $0->bnezc */
7839 else if ((ip->insn_opcode & 0xdc1f0000) == 0x94000000)
7840 ip->insn_opcode = (((ip->insn_opcode >>
7841 (MICROMIPSOP_SH_RT - MICROMIPSOP_SH_RS))
7842 & (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS))
7843 | ((ip->insn_opcode >> 7) & 0x00400000)
7844 | 0x40a00000) ^ 0x00400000;
7847 find_altered_micromips_opcode (ip);
7852 insert_into_history (0, 1, ip);
7857 struct mips_cl_insn delay = history[0];
7859 if (relaxed_branch || delay.frag != ip->frag)
7861 /* Add the delay slot instruction to the end of the
7862 current frag and shrink the fixed part of the
7863 original frag. If the branch occupies the tail of
7864 the latter, move it backwards to cover the gap. */
7865 delay.frag->fr_fix -= branch_disp;
7866 if (delay.frag == ip->frag)
7867 move_insn (ip, ip->frag, ip->where - branch_disp);
7868 add_fixed_insn (&delay);
7872 /* If this is not a relaxed branch and we are in the
7873 same frag, then just swap the instructions. */
7874 move_insn (ip, delay.frag, delay.where);
7875 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
7879 insert_into_history (0, 1, &delay);
7884 /* If we have just completed an unconditional branch, clear the history. */
7885 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
7886 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
7890 mips_no_prev_insn ();
7892 for (i = 0; i < ARRAY_SIZE (history); i++)
7893 history[i].cleared_p = 1;
7896 /* We need to emit a label at the end of branch-likely macros. */
7897 if (emit_branch_likely_macro)
7899 emit_branch_likely_macro = FALSE;
7900 micromips_add_label ();
7903 /* We just output an insn, so the next one doesn't have a label. */
7904 mips_clear_insn_labels ();
7907 /* Forget that there was any previous instruction or label.
7908 When BRANCH is true, the branch history is also flushed. */
7911 mips_no_prev_insn (void)
7913 prev_nop_frag = NULL;
7914 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
7915 mips_clear_insn_labels ();
7918 /* This function must be called before we emit something other than
7919 instructions. It is like mips_no_prev_insn except that it inserts
7920 any NOPS that might be needed by previous instructions. */
7923 mips_emit_delays (void)
7925 if (! mips_opts.noreorder)
7927 int nops = nops_for_insn (0, history, NULL);
7931 add_fixed_insn (NOP_INSN);
7932 mips_move_text_labels ();
7935 mips_no_prev_insn ();
7938 /* Start a (possibly nested) noreorder block. */
7941 start_noreorder (void)
7943 if (mips_opts.noreorder == 0)
7948 /* None of the instructions before the .set noreorder can be moved. */
7949 for (i = 0; i < ARRAY_SIZE (history); i++)
7950 history[i].fixed_p = 1;
7952 /* Insert any nops that might be needed between the .set noreorder
7953 block and the previous instructions. We will later remove any
7954 nops that turn out not to be needed. */
7955 nops = nops_for_insn (0, history, NULL);
7958 if (mips_optimize != 0)
7960 /* Record the frag which holds the nop instructions, so
7961 that we can remove them if we don't need them. */
7962 frag_grow (nops * NOP_INSN_SIZE);
7963 prev_nop_frag = frag_now;
7964 prev_nop_frag_holds = nops;
7965 prev_nop_frag_required = 0;
7966 prev_nop_frag_since = 0;
7969 for (; nops > 0; --nops)
7970 add_fixed_insn (NOP_INSN);
7972 /* Move on to a new frag, so that it is safe to simply
7973 decrease the size of prev_nop_frag. */
7974 frag_wane (frag_now);
7976 mips_move_text_labels ();
7978 mips_mark_labels ();
7979 mips_clear_insn_labels ();
7981 mips_opts.noreorder++;
7982 mips_any_noreorder = 1;
7985 /* End a nested noreorder block. */
7988 end_noreorder (void)
7990 mips_opts.noreorder--;
7991 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
7993 /* Commit to inserting prev_nop_frag_required nops and go back to
7994 handling nop insertion the .set reorder way. */
7995 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
7997 insert_into_history (prev_nop_frag_since,
7998 prev_nop_frag_required, NOP_INSN);
7999 prev_nop_frag = NULL;
8003 /* Sign-extend 32-bit mode constants that have bit 31 set and all
8004 higher bits unset. */
8007 normalize_constant_expr (expressionS *ex)
8009 if (ex->X_op == O_constant
8010 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
8011 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
8015 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
8016 all higher bits unset. */
8019 normalize_address_expr (expressionS *ex)
8021 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
8022 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
8023 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
8024 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
8028 /* Try to match TOKENS against OPCODE, storing the result in INSN.
8029 Return true if the match was successful.
8031 OPCODE_EXTRA is a value that should be ORed into the opcode
8032 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
8033 there are more alternatives after OPCODE and SOFT_MATCH is
8034 as for mips_arg_info. */
8037 match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
8038 struct mips_operand_token *tokens, unsigned int opcode_extra,
8039 bfd_boolean lax_match, bfd_boolean complete_p)
8042 struct mips_arg_info arg;
8043 const struct mips_operand *operand;
8046 imm_expr.X_op = O_absent;
8047 offset_expr.X_op = O_absent;
8048 offset_reloc[0] = BFD_RELOC_UNUSED;
8049 offset_reloc[1] = BFD_RELOC_UNUSED;
8050 offset_reloc[2] = BFD_RELOC_UNUSED;
8052 create_insn (insn, opcode);
8053 /* When no opcode suffix is specified, assume ".xyzw". */
8054 if ((opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0 && opcode_extra == 0)
8055 insn->insn_opcode |= 0xf << mips_vu0_channel_mask.lsb;
8057 insn->insn_opcode |= opcode_extra;
8058 memset (&arg, 0, sizeof (arg));
8062 arg.last_regno = ILLEGAL_REG;
8063 arg.dest_regno = ILLEGAL_REG;
8064 arg.lax_match = lax_match;
8065 for (args = opcode->args;; ++args)
8067 if (arg.token->type == OT_END)
8069 /* Handle unary instructions in which only one operand is given.
8070 The source is then the same as the destination. */
8071 if (arg.opnum == 1 && *args == ',')
8073 operand = (mips_opts.micromips
8074 ? decode_micromips_operand (args + 1)
8075 : decode_mips_operand (args + 1));
8076 if (operand && mips_optional_operand_p (operand))
8084 /* Treat elided base registers as $0. */
8085 if (strcmp (args, "(b)") == 0)
8093 /* The register suffix is optional. */
8098 /* Fail the match if there were too few operands. */
8102 /* Successful match. */
8105 clear_insn_error ();
8106 if (arg.dest_regno == arg.last_regno
8107 && strncmp (insn->insn_mo->name, "jalr", 4) == 0)
8111 (0, _("source and destination must be different"));
8112 else if (arg.last_regno == 31)
8114 (0, _("a destination register must be supplied"));
8116 else if (arg.last_regno == 31
8117 && (strncmp (insn->insn_mo->name, "bltzal", 6) == 0
8118 || strncmp (insn->insn_mo->name, "bgezal", 6) == 0))
8119 set_insn_error (0, _("the source register must not be $31"));
8120 check_completed_insn (&arg);
8124 /* Fail the match if the line has too many operands. */
8128 /* Handle characters that need to match exactly. */
8129 if (*args == '(' || *args == ')' || *args == ',')
8131 if (match_char (&arg, *args))
8138 if (arg.token->type == OT_DOUBLE_CHAR
8139 && arg.token->u.ch == *args)
8147 /* Handle special macro operands. Work out the properties of
8156 *offset_reloc = BFD_RELOC_MIPS_19_PCREL_S2;
8160 *offset_reloc = BFD_RELOC_MIPS_18_PCREL_S3;
8169 *offset_reloc = BFD_RELOC_MIPS_JMP;
8173 *offset_reloc = BFD_RELOC_MIPS_26_PCREL_S2;
8177 *offset_reloc = BFD_RELOC_MIPS_21_PCREL_S2;
8183 if (!match_const_int (&arg, &imm_expr.X_add_number))
8185 imm_expr.X_op = O_constant;
8187 normalize_constant_expr (&imm_expr);
8191 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
8193 /* Assume that the offset has been elided and that what
8194 we saw was a base register. The match will fail later
8195 if that assumption turns out to be wrong. */
8196 offset_expr.X_op = O_constant;
8197 offset_expr.X_add_number = 0;
8201 if (!match_expression (&arg, &offset_expr, offset_reloc))
8203 normalize_address_expr (&offset_expr);
8208 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
8214 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
8220 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
8226 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
8232 *offset_reloc = BFD_RELOC_16_PCREL_S2;
8236 *offset_reloc = BFD_RELOC_MIPS_JMP;
8240 gas_assert (mips_opts.micromips);
8246 if (!forced_insn_length)
8247 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
8249 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
8251 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
8257 operand = (mips_opts.micromips
8258 ? decode_micromips_operand (args)
8259 : decode_mips_operand (args));
8263 /* Skip prefixes. */
8264 if (*args == '+' || *args == 'm' || *args == '-')
8267 if (mips_optional_operand_p (operand)
8269 && (arg.token[0].type != OT_REG
8270 || arg.token[1].type == OT_END))
8272 /* Assume that the register has been elided and is the
8273 same as the first operand. */
8278 if (!match_operand (&arg, operand))
8283 /* Like match_insn, but for MIPS16. */
8286 match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
8287 struct mips_operand_token *tokens)
8290 const struct mips_operand *operand;
8291 const struct mips_operand *ext_operand;
8292 bfd_boolean pcrel = FALSE;
8293 int required_insn_length;
8294 struct mips_arg_info arg;
8297 if (forced_insn_length)
8298 required_insn_length = forced_insn_length;
8299 else if (mips_opts.noautoextend && !mips_opcode_32bit_p (opcode))
8300 required_insn_length = 2;
8302 required_insn_length = 0;
8304 create_insn (insn, opcode);
8305 imm_expr.X_op = O_absent;
8306 offset_expr.X_op = O_absent;
8307 offset_reloc[0] = BFD_RELOC_UNUSED;
8308 offset_reloc[1] = BFD_RELOC_UNUSED;
8309 offset_reloc[2] = BFD_RELOC_UNUSED;
8312 memset (&arg, 0, sizeof (arg));
8316 arg.last_regno = ILLEGAL_REG;
8317 arg.dest_regno = ILLEGAL_REG;
8319 for (args = opcode->args;; ++args)
8323 if (arg.token->type == OT_END)
8327 /* Handle unary instructions in which only one operand is given.
8328 The source is then the same as the destination. */
8329 if (arg.opnum == 1 && *args == ',')
8331 operand = decode_mips16_operand (args[1], FALSE);
8332 if (operand && mips_optional_operand_p (operand))
8340 /* Fail the match if there were too few operands. */
8344 /* Successful match. Stuff the immediate value in now, if
8346 clear_insn_error ();
8347 if (opcode->pinfo == INSN_MACRO)
8349 gas_assert (relax_char == 0 || relax_char == 'p');
8350 gas_assert (*offset_reloc == BFD_RELOC_UNUSED);
8353 && offset_expr.X_op == O_constant
8355 && calculate_reloc (*offset_reloc,
8356 offset_expr.X_add_number,
8359 mips16_immed (NULL, 0, relax_char, *offset_reloc, value,
8360 required_insn_length, &insn->insn_opcode);
8361 offset_expr.X_op = O_absent;
8362 *offset_reloc = BFD_RELOC_UNUSED;
8364 else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED)
8366 if (required_insn_length == 2)
8367 set_insn_error (0, _("invalid unextended operand value"));
8368 else if (!mips_opcode_32bit_p (opcode))
8370 forced_insn_length = 4;
8371 insn->insn_opcode |= MIPS16_EXTEND;
8374 else if (relax_char)
8375 *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char;
8377 check_completed_insn (&arg);
8381 /* Fail the match if the line has too many operands. */
8385 /* Handle characters that need to match exactly. */
8386 if (*args == '(' || *args == ')' || *args == ',')
8388 if (match_char (&arg, *args))
8408 if (!match_const_int (&arg, &imm_expr.X_add_number))
8410 imm_expr.X_op = O_constant;
8412 normalize_constant_expr (&imm_expr);
8417 *offset_reloc = BFD_RELOC_MIPS16_JMP;
8421 operand = decode_mips16_operand (c, mips_opcode_32bit_p (opcode));
8425 if (operand->type == OP_PCREL)
8429 ext_operand = decode_mips16_operand (c, TRUE);
8430 if (operand != ext_operand)
8432 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
8434 offset_expr.X_op = O_constant;
8435 offset_expr.X_add_number = 0;
8440 if (!match_expression (&arg, &offset_expr, offset_reloc))
8443 /* '8' is used for SLTI(U) and has traditionally not
8444 been allowed to take relocation operators. */
8445 if (offset_reloc[0] != BFD_RELOC_UNUSED
8446 && (ext_operand->size != 16 || c == '8'))
8448 match_not_constant (&arg);
8452 if (offset_expr.X_op == O_big)
8454 match_out_of_range (&arg);
8463 if (mips_optional_operand_p (operand)
8465 && (arg.token[0].type != OT_REG
8466 || arg.token[1].type == OT_END))
8468 /* Assume that the register has been elided and is the
8469 same as the first operand. */
8474 if (!match_operand (&arg, operand))
8479 /* Record that the current instruction is invalid for the current ISA. */
8482 match_invalid_for_isa (void)
8485 (0, _("opcode not supported on this processor: %s (%s)"),
8486 mips_cpu_info_from_arch (mips_opts.arch)->name,
8487 mips_cpu_info_from_isa (mips_opts.isa)->name);
8490 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8491 Return true if a definite match or failure was found, storing any match
8492 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8493 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8494 tried and failed to match under normal conditions and now want to try a
8495 more relaxed match. */
8498 match_insns (struct mips_cl_insn *insn, const struct mips_opcode *first,
8499 const struct mips_opcode *past, struct mips_operand_token *tokens,
8500 int opcode_extra, bfd_boolean lax_match)
8502 const struct mips_opcode *opcode;
8503 const struct mips_opcode *invalid_delay_slot;
8504 bfd_boolean seen_valid_for_isa, seen_valid_for_size;
8506 /* Search for a match, ignoring alternatives that don't satisfy the
8507 current ISA or forced_length. */
8508 invalid_delay_slot = 0;
8509 seen_valid_for_isa = FALSE;
8510 seen_valid_for_size = FALSE;
8514 gas_assert (strcmp (opcode->name, first->name) == 0);
8515 if (is_opcode_valid (opcode))
8517 seen_valid_for_isa = TRUE;
8518 if (is_size_valid (opcode))
8520 bfd_boolean delay_slot_ok;
8522 seen_valid_for_size = TRUE;
8523 delay_slot_ok = is_delay_slot_valid (opcode);
8524 if (match_insn (insn, opcode, tokens, opcode_extra,
8525 lax_match, delay_slot_ok))
8529 if (!invalid_delay_slot)
8530 invalid_delay_slot = opcode;
8539 while (opcode < past && strcmp (opcode->name, first->name) == 0);
8541 /* If the only matches we found had the wrong length for the delay slot,
8542 pick the first such match. We'll issue an appropriate warning later. */
8543 if (invalid_delay_slot)
8545 if (match_insn (insn, invalid_delay_slot, tokens, opcode_extra,
8551 /* Handle the case where we didn't try to match an instruction because
8552 all the alternatives were incompatible with the current ISA. */
8553 if (!seen_valid_for_isa)
8555 match_invalid_for_isa ();
8559 /* Handle the case where we didn't try to match an instruction because
8560 all the alternatives were of the wrong size. */
8561 if (!seen_valid_for_size)
8563 if (mips_opts.insn32)
8564 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
8567 (0, _("unrecognized %d-bit version of microMIPS opcode"),
8568 8 * forced_insn_length);
8575 /* Like match_insns, but for MIPS16. */
8578 match_mips16_insns (struct mips_cl_insn *insn, const struct mips_opcode *first,
8579 struct mips_operand_token *tokens)
8581 const struct mips_opcode *opcode;
8582 bfd_boolean seen_valid_for_isa;
8583 bfd_boolean seen_valid_for_size;
8585 /* Search for a match, ignoring alternatives that don't satisfy the
8586 current ISA. There are no separate entries for extended forms so
8587 we deal with forced_length later. */
8588 seen_valid_for_isa = FALSE;
8589 seen_valid_for_size = FALSE;
8593 gas_assert (strcmp (opcode->name, first->name) == 0);
8594 if (is_opcode_valid_16 (opcode))
8596 seen_valid_for_isa = TRUE;
8597 if (is_size_valid_16 (opcode))
8599 seen_valid_for_size = TRUE;
8600 if (match_mips16_insn (insn, opcode, tokens))
8606 while (opcode < &mips16_opcodes[bfd_mips16_num_opcodes]
8607 && strcmp (opcode->name, first->name) == 0);
8609 /* Handle the case where we didn't try to match an instruction because
8610 all the alternatives were incompatible with the current ISA. */
8611 if (!seen_valid_for_isa)
8613 match_invalid_for_isa ();
8617 /* Handle the case where we didn't try to match an instruction because
8618 all the alternatives were of the wrong size. */
8619 if (!seen_valid_for_size)
8621 if (forced_insn_length == 2)
8623 (0, _("unrecognized unextended version of MIPS16 opcode"));
8626 (0, _("unrecognized extended version of MIPS16 opcode"));
8633 /* Set up global variables for the start of a new macro. */
8638 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
8639 memset (&mips_macro_warning.first_insn_sizes, 0,
8640 sizeof (mips_macro_warning.first_insn_sizes));
8641 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
8642 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
8643 && delayed_branch_p (&history[0]));
8645 && history[0].frag->fr_type == rs_machine_dependent
8646 && RELAX_MICROMIPS_P (history[0].frag->fr_subtype)
8647 && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype))
8648 mips_macro_warning.delay_slot_length = 0;
8650 switch (history[0].insn_mo->pinfo2
8651 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
8653 case INSN2_BRANCH_DELAY_32BIT:
8654 mips_macro_warning.delay_slot_length = 4;
8656 case INSN2_BRANCH_DELAY_16BIT:
8657 mips_macro_warning.delay_slot_length = 2;
8660 mips_macro_warning.delay_slot_length = 0;
8663 mips_macro_warning.first_frag = NULL;
8666 /* Given that a macro is longer than one instruction or of the wrong size,
8667 return the appropriate warning for it. Return null if no warning is
8668 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8669 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8670 and RELAX_NOMACRO. */
8673 macro_warning (relax_substateT subtype)
8675 if (subtype & RELAX_DELAY_SLOT)
8676 return _("macro instruction expanded into multiple instructions"
8677 " in a branch delay slot");
8678 else if (subtype & RELAX_NOMACRO)
8679 return _("macro instruction expanded into multiple instructions");
8680 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
8681 | RELAX_DELAY_SLOT_SIZE_SECOND))
8682 return ((subtype & RELAX_DELAY_SLOT_16BIT)
8683 ? _("macro instruction expanded into a wrong size instruction"
8684 " in a 16-bit branch delay slot")
8685 : _("macro instruction expanded into a wrong size instruction"
8686 " in a 32-bit branch delay slot"));
8691 /* Finish up a macro. Emit warnings as appropriate. */
8696 /* Relaxation warning flags. */
8697 relax_substateT subtype = 0;
8699 /* Check delay slot size requirements. */
8700 if (mips_macro_warning.delay_slot_length == 2)
8701 subtype |= RELAX_DELAY_SLOT_16BIT;
8702 if (mips_macro_warning.delay_slot_length != 0)
8704 if (mips_macro_warning.delay_slot_length
8705 != mips_macro_warning.first_insn_sizes[0])
8706 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
8707 if (mips_macro_warning.delay_slot_length
8708 != mips_macro_warning.first_insn_sizes[1])
8709 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
8712 /* Check instruction count requirements. */
8713 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
8715 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
8716 subtype |= RELAX_SECOND_LONGER;
8717 if (mips_opts.warn_about_macros)
8718 subtype |= RELAX_NOMACRO;
8719 if (mips_macro_warning.delay_slot_p)
8720 subtype |= RELAX_DELAY_SLOT;
8723 /* If both alternatives fail to fill a delay slot correctly,
8724 emit the warning now. */
8725 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
8726 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
8731 s = subtype & (RELAX_DELAY_SLOT_16BIT
8732 | RELAX_DELAY_SLOT_SIZE_FIRST
8733 | RELAX_DELAY_SLOT_SIZE_SECOND);
8734 msg = macro_warning (s);
8736 as_warn ("%s", msg);
8740 /* If both implementations are longer than 1 instruction, then emit the
8742 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
8747 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
8748 msg = macro_warning (s);
8750 as_warn ("%s", msg);
8754 /* If any flags still set, then one implementation might need a warning
8755 and the other either will need one of a different kind or none at all.
8756 Pass any remaining flags over to relaxation. */
8757 if (mips_macro_warning.first_frag != NULL)
8758 mips_macro_warning.first_frag->fr_subtype |= subtype;
8761 /* Instruction operand formats used in macros that vary between
8762 standard MIPS and microMIPS code. */
8764 static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } };
8765 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
8766 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
8767 static const char * const lui_fmt[2] = { "t,u", "s,u" };
8768 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
8769 static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } };
8770 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
8771 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
8773 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
8774 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8775 : cop12_fmt[mips_opts.micromips])
8776 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
8777 #define LUI_FMT (lui_fmt[mips_opts.micromips])
8778 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
8779 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
8780 : mem12_fmt[mips_opts.micromips])
8781 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
8782 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
8783 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
8785 /* Read a macro's relocation codes from *ARGS and store them in *R.
8786 The first argument in *ARGS will be either the code for a single
8787 relocation or -1 followed by the three codes that make up a
8788 composite relocation. */
8791 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
8795 next = va_arg (*args, int);
8797 r[0] = (bfd_reloc_code_real_type) next;
8800 for (i = 0; i < 3; i++)
8801 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
8802 /* This function is only used for 16-bit relocation fields.
8803 To make the macro code simpler, treat an unrelocated value
8804 in the same way as BFD_RELOC_LO16. */
8805 if (r[0] == BFD_RELOC_UNUSED)
8806 r[0] = BFD_RELOC_LO16;
8810 /* Build an instruction created by a macro expansion. This is passed
8811 a pointer to the count of instructions created so far, an
8812 expression, the name of the instruction to build, an operand format
8813 string, and corresponding arguments. */
8816 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
8818 const struct mips_opcode *mo = NULL;
8819 bfd_reloc_code_real_type r[3];
8820 const struct mips_opcode *amo;
8821 const struct mips_operand *operand;
8822 struct hash_control *hash;
8823 struct mips_cl_insn insn;
8827 va_start (args, fmt);
8829 if (mips_opts.mips16)
8831 mips16_macro_build (ep, name, fmt, &args);
8836 r[0] = BFD_RELOC_UNUSED;
8837 r[1] = BFD_RELOC_UNUSED;
8838 r[2] = BFD_RELOC_UNUSED;
8839 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
8840 amo = (struct mips_opcode *) hash_find (hash, name);
8842 gas_assert (strcmp (name, amo->name) == 0);
8846 /* Search until we get a match for NAME. It is assumed here that
8847 macros will never generate MDMX, MIPS-3D, or MT instructions.
8848 We try to match an instruction that fulfills the branch delay
8849 slot instruction length requirement (if any) of the previous
8850 instruction. While doing this we record the first instruction
8851 seen that matches all the other conditions and use it anyway
8852 if the requirement cannot be met; we will issue an appropriate
8853 warning later on. */
8854 if (strcmp (fmt, amo->args) == 0
8855 && amo->pinfo != INSN_MACRO
8856 && is_opcode_valid (amo)
8857 && is_size_valid (amo))
8859 if (is_delay_slot_valid (amo))
8869 gas_assert (amo->name);
8871 while (strcmp (name, amo->name) == 0);
8874 create_insn (&insn, mo);
8887 macro_read_relocs (&args, r);
8888 gas_assert (*r == BFD_RELOC_GPREL16
8889 || *r == BFD_RELOC_MIPS_HIGHER
8890 || *r == BFD_RELOC_HI16_S
8891 || *r == BFD_RELOC_LO16
8892 || *r == BFD_RELOC_MIPS_GOT_OFST
8893 || (mips_opts.micromips
8894 && (*r == BFD_RELOC_16
8895 || *r == BFD_RELOC_MIPS_GOT16
8896 || *r == BFD_RELOC_MIPS_CALL16
8897 || *r == BFD_RELOC_MIPS_GOT_HI16
8898 || *r == BFD_RELOC_MIPS_GOT_LO16
8899 || *r == BFD_RELOC_MIPS_CALL_HI16
8900 || *r == BFD_RELOC_MIPS_CALL_LO16
8901 || *r == BFD_RELOC_MIPS_SUB
8902 || *r == BFD_RELOC_MIPS_GOT_PAGE
8903 || *r == BFD_RELOC_MIPS_HIGHEST
8904 || *r == BFD_RELOC_MIPS_GOT_DISP
8905 || *r == BFD_RELOC_MIPS_TLS_GD
8906 || *r == BFD_RELOC_MIPS_TLS_LDM
8907 || *r == BFD_RELOC_MIPS_TLS_DTPREL_HI16
8908 || *r == BFD_RELOC_MIPS_TLS_DTPREL_LO16
8909 || *r == BFD_RELOC_MIPS_TLS_GOTTPREL
8910 || *r == BFD_RELOC_MIPS_TLS_TPREL_HI16
8911 || *r == BFD_RELOC_MIPS_TLS_TPREL_LO16)));
8915 macro_read_relocs (&args, r);
8919 macro_read_relocs (&args, r);
8920 gas_assert (ep != NULL
8921 && (ep->X_op == O_constant
8922 || (ep->X_op == O_symbol
8923 && (*r == BFD_RELOC_MIPS_HIGHEST
8924 || *r == BFD_RELOC_HI16_S
8925 || *r == BFD_RELOC_HI16
8926 || *r == BFD_RELOC_GPREL16
8927 || *r == BFD_RELOC_MIPS_GOT_HI16
8928 || *r == BFD_RELOC_MIPS_CALL_HI16))));
8932 gas_assert (ep != NULL);
8935 * This allows macro() to pass an immediate expression for
8936 * creating short branches without creating a symbol.
8938 * We don't allow branch relaxation for these branches, as
8939 * they should only appear in ".set nomacro" anyway.
8941 if (ep->X_op == O_constant)
8943 /* For microMIPS we always use relocations for branches.
8944 So we should not resolve immediate values. */
8945 gas_assert (!mips_opts.micromips);
8947 if ((ep->X_add_number & 3) != 0)
8948 as_bad (_("branch to misaligned address (0x%lx)"),
8949 (unsigned long) ep->X_add_number);
8950 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
8951 as_bad (_("branch address range overflow (0x%lx)"),
8952 (unsigned long) ep->X_add_number);
8953 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
8957 *r = BFD_RELOC_16_PCREL_S2;
8961 gas_assert (ep != NULL);
8962 *r = BFD_RELOC_MIPS_JMP;
8966 operand = (mips_opts.micromips
8967 ? decode_micromips_operand (fmt)
8968 : decode_mips_operand (fmt));
8972 uval = va_arg (args, int);
8973 if (operand->type == OP_CLO_CLZ_DEST)
8974 uval |= (uval << 5);
8975 insn_insert_operand (&insn, operand, uval);
8977 if (*fmt == '+' || *fmt == 'm' || *fmt == '-')
8983 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
8985 append_insn (&insn, ep, r, TRUE);
8989 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
8992 struct mips_opcode *mo;
8993 struct mips_cl_insn insn;
8994 const struct mips_operand *operand;
8995 bfd_reloc_code_real_type r[3]
8996 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
8998 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
9000 gas_assert (strcmp (name, mo->name) == 0);
9002 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
9005 gas_assert (mo->name);
9006 gas_assert (strcmp (name, mo->name) == 0);
9009 create_insn (&insn, mo);
9046 gas_assert (ep != NULL);
9048 if (ep->X_op != O_constant)
9049 *r = (int) BFD_RELOC_UNUSED + c;
9050 else if (calculate_reloc (*r, ep->X_add_number, &value))
9052 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode);
9054 *r = BFD_RELOC_UNUSED;
9060 operand = decode_mips16_operand (c, FALSE);
9064 insn_insert_operand (&insn, operand, va_arg (*args, int));
9069 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
9071 append_insn (&insn, ep, r, TRUE);
9075 * Generate a "jalr" instruction with a relocation hint to the called
9076 * function. This occurs in NewABI PIC code.
9079 macro_build_jalr (expressionS *ep, int cprestore)
9081 static const bfd_reloc_code_real_type jalr_relocs[2]
9082 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
9083 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
9087 if (MIPS_JALR_HINT_P (ep))
9092 if (mips_opts.micromips)
9094 jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32
9095 ? "jalr" : "jalrs");
9096 if (MIPS_JALR_HINT_P (ep)
9098 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
9099 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
9101 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
9104 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
9105 if (MIPS_JALR_HINT_P (ep))
9106 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
9110 * Generate a "lui" instruction.
9113 macro_build_lui (expressionS *ep, int regnum)
9115 gas_assert (! mips_opts.mips16);
9117 if (ep->X_op != O_constant)
9119 gas_assert (ep->X_op == O_symbol);
9120 /* _gp_disp is a special case, used from s_cpload.
9121 __gnu_local_gp is used if mips_no_shared. */
9122 gas_assert (mips_pic == NO_PIC
9124 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
9125 || (! mips_in_shared
9126 && strcmp (S_GET_NAME (ep->X_add_symbol),
9127 "__gnu_local_gp") == 0));
9130 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
9133 /* Generate a sequence of instructions to do a load or store from a constant
9134 offset off of a base register (breg) into/from a target register (treg),
9135 using AT if necessary. */
9137 macro_build_ldst_constoffset (expressionS *ep, const char *op,
9138 int treg, int breg, int dbl)
9140 gas_assert (ep->X_op == O_constant);
9142 /* Sign-extending 32-bit constants makes their handling easier. */
9144 normalize_constant_expr (ep);
9146 /* Right now, this routine can only handle signed 32-bit constants. */
9147 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
9148 as_warn (_("operand overflow"));
9150 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
9152 /* Signed 16-bit offset will fit in the op. Easy! */
9153 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
9157 /* 32-bit offset, need multiple instructions and AT, like:
9158 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
9159 addu $tempreg,$tempreg,$breg
9160 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
9161 to handle the complete offset. */
9162 macro_build_lui (ep, AT);
9163 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
9164 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
9167 as_bad (_("macro used $at after \".set noat\""));
9172 * Generates code to set the $at register to true (one)
9173 * if reg is less than the immediate expression.
9176 set_at (int reg, int unsignedp)
9178 if (imm_expr.X_add_number >= -0x8000
9179 && imm_expr.X_add_number < 0x8000)
9180 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
9181 AT, reg, BFD_RELOC_LO16);
9184 load_register (AT, &imm_expr, GPR_SIZE == 64);
9185 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
9189 /* Count the leading zeroes by performing a binary chop. This is a
9190 bulky bit of source, but performance is a LOT better for the
9191 majority of values than a simple loop to count the bits:
9192 for (lcnt = 0; (lcnt < 32); lcnt++)
9193 if ((v) & (1 << (31 - lcnt)))
9195 However it is not code size friendly, and the gain will drop a bit
9196 on certain cached systems.
9198 #define COUNT_TOP_ZEROES(v) \
9199 (((v) & ~0xffff) == 0 \
9200 ? ((v) & ~0xff) == 0 \
9201 ? ((v) & ~0xf) == 0 \
9202 ? ((v) & ~0x3) == 0 \
9203 ? ((v) & ~0x1) == 0 \
9208 : ((v) & ~0x7) == 0 \
9211 : ((v) & ~0x3f) == 0 \
9212 ? ((v) & ~0x1f) == 0 \
9215 : ((v) & ~0x7f) == 0 \
9218 : ((v) & ~0xfff) == 0 \
9219 ? ((v) & ~0x3ff) == 0 \
9220 ? ((v) & ~0x1ff) == 0 \
9223 : ((v) & ~0x7ff) == 0 \
9226 : ((v) & ~0x3fff) == 0 \
9227 ? ((v) & ~0x1fff) == 0 \
9230 : ((v) & ~0x7fff) == 0 \
9233 : ((v) & ~0xffffff) == 0 \
9234 ? ((v) & ~0xfffff) == 0 \
9235 ? ((v) & ~0x3ffff) == 0 \
9236 ? ((v) & ~0x1ffff) == 0 \
9239 : ((v) & ~0x7ffff) == 0 \
9242 : ((v) & ~0x3fffff) == 0 \
9243 ? ((v) & ~0x1fffff) == 0 \
9246 : ((v) & ~0x7fffff) == 0 \
9249 : ((v) & ~0xfffffff) == 0 \
9250 ? ((v) & ~0x3ffffff) == 0 \
9251 ? ((v) & ~0x1ffffff) == 0 \
9254 : ((v) & ~0x7ffffff) == 0 \
9257 : ((v) & ~0x3fffffff) == 0 \
9258 ? ((v) & ~0x1fffffff) == 0 \
9261 : ((v) & ~0x7fffffff) == 0 \
9266 * This routine generates the least number of instructions necessary to load
9267 * an absolute expression value into a register.
9270 load_register (int reg, expressionS *ep, int dbl)
9273 expressionS hi32, lo32;
9275 if (ep->X_op != O_big)
9277 gas_assert (ep->X_op == O_constant);
9279 /* Sign-extending 32-bit constants makes their handling easier. */
9281 normalize_constant_expr (ep);
9283 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
9285 /* We can handle 16 bit signed values with an addiu to
9286 $zero. No need to ever use daddiu here, since $zero and
9287 the result are always correct in 32 bit mode. */
9288 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
9291 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
9293 /* We can handle 16 bit unsigned values with an ori to
9295 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
9298 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
9300 /* 32 bit values require an lui. */
9301 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
9302 if ((ep->X_add_number & 0xffff) != 0)
9303 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
9308 /* The value is larger than 32 bits. */
9310 if (!dbl || GPR_SIZE == 32)
9314 sprintf_vma (value, ep->X_add_number);
9315 as_bad (_("number (0x%s) larger than 32 bits"), value);
9316 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
9320 if (ep->X_op != O_big)
9323 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
9324 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
9325 hi32.X_add_number &= 0xffffffff;
9327 lo32.X_add_number &= 0xffffffff;
9331 gas_assert (ep->X_add_number > 2);
9332 if (ep->X_add_number == 3)
9333 generic_bignum[3] = 0;
9334 else if (ep->X_add_number > 4)
9335 as_bad (_("number larger than 64 bits"));
9336 lo32.X_op = O_constant;
9337 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
9338 hi32.X_op = O_constant;
9339 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
9342 if (hi32.X_add_number == 0)
9347 unsigned long hi, lo;
9349 if (hi32.X_add_number == (offsetT) 0xffffffff)
9351 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
9353 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
9356 if (lo32.X_add_number & 0x80000000)
9358 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
9359 if (lo32.X_add_number & 0xffff)
9360 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
9365 /* Check for 16bit shifted constant. We know that hi32 is
9366 non-zero, so start the mask on the first bit of the hi32
9371 unsigned long himask, lomask;
9375 himask = 0xffff >> (32 - shift);
9376 lomask = (0xffff << shift) & 0xffffffff;
9380 himask = 0xffff << (shift - 32);
9383 if ((hi32.X_add_number & ~(offsetT) himask) == 0
9384 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
9388 tmp.X_op = O_constant;
9390 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
9391 | (lo32.X_add_number >> shift));
9393 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
9394 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
9395 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
9396 reg, reg, (shift >= 32) ? shift - 32 : shift);
9401 while (shift <= (64 - 16));
9403 /* Find the bit number of the lowest one bit, and store the
9404 shifted value in hi/lo. */
9405 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
9406 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
9410 while ((lo & 1) == 0)
9415 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
9421 while ((hi & 1) == 0)
9430 /* Optimize if the shifted value is a (power of 2) - 1. */
9431 if ((hi == 0 && ((lo + 1) & lo) == 0)
9432 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
9434 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
9439 /* This instruction will set the register to be all
9441 tmp.X_op = O_constant;
9442 tmp.X_add_number = (offsetT) -1;
9443 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
9447 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
9448 reg, reg, (bit >= 32) ? bit - 32 : bit);
9450 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
9451 reg, reg, (shift >= 32) ? shift - 32 : shift);
9456 /* Sign extend hi32 before calling load_register, because we can
9457 generally get better code when we load a sign extended value. */
9458 if ((hi32.X_add_number & 0x80000000) != 0)
9459 hi32.X_add_number |= ~(offsetT) 0xffffffff;
9460 load_register (reg, &hi32, 0);
9463 if ((lo32.X_add_number & 0xffff0000) == 0)
9467 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
9475 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
9477 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
9478 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
9484 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
9488 mid16.X_add_number >>= 16;
9489 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
9490 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
9493 if ((lo32.X_add_number & 0xffff) != 0)
9494 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
9498 load_delay_nop (void)
9500 if (!gpr_interlocks)
9501 macro_build (NULL, "nop", "");
9504 /* Load an address into a register. */
9507 load_address (int reg, expressionS *ep, int *used_at)
9509 if (ep->X_op != O_constant
9510 && ep->X_op != O_symbol)
9512 as_bad (_("expression too complex"));
9513 ep->X_op = O_constant;
9516 if (ep->X_op == O_constant)
9518 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
9522 if (mips_pic == NO_PIC)
9524 /* If this is a reference to a GP relative symbol, we want
9525 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
9527 lui $reg,<sym> (BFD_RELOC_HI16_S)
9528 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9529 If we have an addend, we always use the latter form.
9531 With 64bit address space and a usable $at we want
9532 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9533 lui $at,<sym> (BFD_RELOC_HI16_S)
9534 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9535 daddiu $at,<sym> (BFD_RELOC_LO16)
9539 If $at is already in use, we use a path which is suboptimal
9540 on superscalar processors.
9541 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9542 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9544 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9546 daddiu $reg,<sym> (BFD_RELOC_LO16)
9548 For GP relative symbols in 64bit address space we can use
9549 the same sequence as in 32bit address space. */
9550 if (HAVE_64BIT_SYMBOLS)
9552 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
9553 && !nopic_need_relax (ep->X_add_symbol, 1))
9555 relax_start (ep->X_add_symbol);
9556 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
9557 mips_gp_register, BFD_RELOC_GPREL16);
9561 if (*used_at == 0 && mips_opts.at)
9563 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
9564 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
9565 macro_build (ep, "daddiu", "t,r,j", reg, reg,
9566 BFD_RELOC_MIPS_HIGHER);
9567 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
9568 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
9569 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
9574 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
9575 macro_build (ep, "daddiu", "t,r,j", reg, reg,
9576 BFD_RELOC_MIPS_HIGHER);
9577 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
9578 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
9579 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
9580 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
9583 if (mips_relax.sequence)
9588 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
9589 && !nopic_need_relax (ep->X_add_symbol, 1))
9591 relax_start (ep->X_add_symbol);
9592 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
9593 mips_gp_register, BFD_RELOC_GPREL16);
9596 macro_build_lui (ep, reg);
9597 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
9598 reg, reg, BFD_RELOC_LO16);
9599 if (mips_relax.sequence)
9603 else if (!mips_big_got)
9607 /* If this is a reference to an external symbol, we want
9608 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9610 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9612 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9613 If there is a constant, it must be added in after.
9615 If we have NewABI, we want
9616 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9617 unless we're referencing a global symbol with a non-zero
9618 offset, in which case cst must be added separately. */
9621 if (ep->X_add_number)
9623 ex.X_add_number = ep->X_add_number;
9624 ep->X_add_number = 0;
9625 relax_start (ep->X_add_symbol);
9626 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9627 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9628 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9629 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9630 ex.X_op = O_constant;
9631 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
9632 reg, reg, BFD_RELOC_LO16);
9633 ep->X_add_number = ex.X_add_number;
9636 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9637 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9638 if (mips_relax.sequence)
9643 ex.X_add_number = ep->X_add_number;
9644 ep->X_add_number = 0;
9645 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9646 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9648 relax_start (ep->X_add_symbol);
9650 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9654 if (ex.X_add_number != 0)
9656 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9657 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9658 ex.X_op = O_constant;
9659 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
9660 reg, reg, BFD_RELOC_LO16);
9664 else if (mips_big_got)
9668 /* This is the large GOT case. If this is a reference to an
9669 external symbol, we want
9670 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9672 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
9674 Otherwise, for a reference to a local symbol in old ABI, we want
9675 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9677 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9678 If there is a constant, it must be added in after.
9680 In the NewABI, for local symbols, with or without offsets, we want:
9681 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9682 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9686 ex.X_add_number = ep->X_add_number;
9687 ep->X_add_number = 0;
9688 relax_start (ep->X_add_symbol);
9689 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
9690 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9691 reg, reg, mips_gp_register);
9692 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
9693 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
9694 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9695 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9696 else if (ex.X_add_number)
9698 ex.X_op = O_constant;
9699 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9703 ep->X_add_number = ex.X_add_number;
9705 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9706 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
9707 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9708 BFD_RELOC_MIPS_GOT_OFST);
9713 ex.X_add_number = ep->X_add_number;
9714 ep->X_add_number = 0;
9715 relax_start (ep->X_add_symbol);
9716 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
9717 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9718 reg, reg, mips_gp_register);
9719 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
9720 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
9722 if (reg_needs_delay (mips_gp_register))
9724 /* We need a nop before loading from $gp. This special
9725 check is required because the lui which starts the main
9726 instruction stream does not refer to $gp, and so will not
9727 insert the nop which may be required. */
9728 macro_build (NULL, "nop", "");
9730 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9731 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9733 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9737 if (ex.X_add_number != 0)
9739 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9740 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9741 ex.X_op = O_constant;
9742 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9750 if (!mips_opts.at && *used_at == 1)
9751 as_bad (_("macro used $at after \".set noat\""));
9754 /* Move the contents of register SOURCE into register DEST. */
9757 move_register (int dest, int source)
9759 /* Prefer to use a 16-bit microMIPS instruction unless the previous
9760 instruction specifically requires a 32-bit one. */
9761 if (mips_opts.micromips
9762 && !mips_opts.insn32
9763 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
9764 macro_build (NULL, "move", "mp,mj", dest, source);
9766 macro_build (NULL, "or", "d,v,t", dest, source, 0);
9769 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
9770 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
9771 The two alternatives are:
9773 Global symbol Local symbol
9774 ------------- ------------
9775 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
9777 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
9779 load_got_offset emits the first instruction and add_got_offset
9780 emits the second for a 16-bit offset or add_got_offset_hilo emits
9781 a sequence to add a 32-bit offset using a scratch register. */
9784 load_got_offset (int dest, expressionS *local)
9789 global.X_add_number = 0;
9791 relax_start (local->X_add_symbol);
9792 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
9793 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9795 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
9796 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9801 add_got_offset (int dest, expressionS *local)
9805 global.X_op = O_constant;
9806 global.X_op_symbol = NULL;
9807 global.X_add_symbol = NULL;
9808 global.X_add_number = local->X_add_number;
9810 relax_start (local->X_add_symbol);
9811 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
9812 dest, dest, BFD_RELOC_LO16);
9814 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
9819 add_got_offset_hilo (int dest, expressionS *local, int tmp)
9822 int hold_mips_optimize;
9824 global.X_op = O_constant;
9825 global.X_op_symbol = NULL;
9826 global.X_add_symbol = NULL;
9827 global.X_add_number = local->X_add_number;
9829 relax_start (local->X_add_symbol);
9830 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
9832 /* Set mips_optimize around the lui instruction to avoid
9833 inserting an unnecessary nop after the lw. */
9834 hold_mips_optimize = mips_optimize;
9836 macro_build_lui (&global, tmp);
9837 mips_optimize = hold_mips_optimize;
9838 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
9841 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
9844 /* Emit a sequence of instructions to emulate a branch likely operation.
9845 BR is an ordinary branch corresponding to one to be emulated. BRNEG
9846 is its complementing branch with the original condition negated.
9847 CALL is set if the original branch specified the link operation.
9848 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
9850 Code like this is produced in the noreorder mode:
9855 delay slot (executed only if branch taken)
9863 delay slot (executed only if branch taken)
9866 In the reorder mode the delay slot would be filled with a nop anyway,
9867 so code produced is simply:
9872 This function is used when producing code for the microMIPS ASE that
9873 does not implement branch likely instructions in hardware. */
9876 macro_build_branch_likely (const char *br, const char *brneg,
9877 int call, expressionS *ep, const char *fmt,
9878 unsigned int sreg, unsigned int treg)
9880 int noreorder = mips_opts.noreorder;
9883 gas_assert (mips_opts.micromips);
9887 micromips_label_expr (&expr1);
9888 macro_build (&expr1, brneg, fmt, sreg, treg);
9889 macro_build (NULL, "nop", "");
9890 macro_build (ep, call ? "bal" : "b", "p");
9892 /* Set to true so that append_insn adds a label. */
9893 emit_branch_likely_macro = TRUE;
9897 macro_build (ep, br, fmt, sreg, treg);
9898 macro_build (NULL, "nop", "");
9903 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
9904 the condition code tested. EP specifies the branch target. */
9907 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
9934 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
9937 /* Emit a two-argument branch macro specified by TYPE, using SREG as
9938 the register tested. EP specifies the branch target. */
9941 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
9943 const char *brneg = NULL;
9953 br = mips_opts.micromips ? "bgez" : "bgezl";
9957 gas_assert (mips_opts.micromips);
9958 br = mips_opts.insn32 ? "bgezal" : "bgezals";
9966 br = mips_opts.micromips ? "bgtz" : "bgtzl";
9973 br = mips_opts.micromips ? "blez" : "blezl";
9980 br = mips_opts.micromips ? "bltz" : "bltzl";
9984 gas_assert (mips_opts.micromips);
9985 br = mips_opts.insn32 ? "bltzal" : "bltzals";
9992 if (mips_opts.micromips && brneg)
9993 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
9995 macro_build (ep, br, "s,p", sreg);
9998 /* Emit a three-argument branch macro specified by TYPE, using SREG and
9999 TREG as the registers tested. EP specifies the branch target. */
10002 macro_build_branch_rsrt (int type, expressionS *ep,
10003 unsigned int sreg, unsigned int treg)
10005 const char *brneg = NULL;
10006 const int call = 0;
10017 br = mips_opts.micromips ? "beq" : "beql";
10026 br = mips_opts.micromips ? "bne" : "bnel";
10032 if (mips_opts.micromips && brneg)
10033 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
10035 macro_build (ep, br, "s,t,p", sreg, treg);
10038 /* Return the high part that should be loaded in order to make the low
10039 part of VALUE accessible using an offset of OFFBITS bits. */
10042 offset_high_part (offsetT value, unsigned int offbits)
10049 bias = 1 << (offbits - 1);
10050 low_mask = bias * 2 - 1;
10051 return (value + bias) & ~low_mask;
10054 /* Return true if the value stored in offset_expr and offset_reloc
10055 fits into a signed offset of OFFBITS bits. RANGE is the maximum
10056 amount that the caller wants to add without inducing overflow
10057 and ALIGN is the known alignment of the value in bytes. */
10060 small_offset_p (unsigned int range, unsigned int align, unsigned int offbits)
10064 /* Accept any relocation operator if overflow isn't a concern. */
10065 if (range < align && *offset_reloc != BFD_RELOC_UNUSED)
10068 /* These relocations are guaranteed not to overflow in correct links. */
10069 if (*offset_reloc == BFD_RELOC_MIPS_LITERAL
10070 || gprel16_reloc_p (*offset_reloc))
10073 if (offset_expr.X_op == O_constant
10074 && offset_high_part (offset_expr.X_add_number, offbits) == 0
10075 && offset_high_part (offset_expr.X_add_number + range, offbits) == 0)
10082 * This routine implements the seemingly endless macro or synthesized
10083 * instructions and addressing modes in the mips assembly language. Many
10084 * of these macros are simple and are similar to each other. These could
10085 * probably be handled by some kind of table or grammar approach instead of
10086 * this verbose method. Others are not simple macros but are more like
10087 * optimizing code generation.
10088 * One interesting optimization is when several store macros appear
10089 * consecutively that would load AT with the upper half of the same address.
10090 * The ensuing load upper instructions are omitted. This implies some kind
10091 * of global optimization. We currently only optimize within a single macro.
10092 * For many of the load and store macros if the address is specified as a
10093 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
10094 * first load register 'at' with zero and use it as the base register. The
10095 * mips assembler simply uses register $zero. Just one tiny optimization
10099 macro (struct mips_cl_insn *ip, char *str)
10101 const struct mips_operand_array *operands;
10102 unsigned int breg, i;
10103 unsigned int tempreg;
10106 expressionS label_expr;
10121 bfd_boolean large_offset;
10123 int hold_mips_optimize;
10124 unsigned int align;
10125 unsigned int op[MAX_OPERANDS];
10127 gas_assert (! mips_opts.mips16);
10129 operands = insn_operands (ip);
10130 for (i = 0; i < MAX_OPERANDS; i++)
10131 if (operands->operand[i])
10132 op[i] = insn_extract_operand (ip, operands->operand[i]);
10136 mask = ip->insn_mo->mask;
10138 label_expr.X_op = O_constant;
10139 label_expr.X_op_symbol = NULL;
10140 label_expr.X_add_symbol = NULL;
10141 label_expr.X_add_number = 0;
10143 expr1.X_op = O_constant;
10144 expr1.X_op_symbol = NULL;
10145 expr1.X_add_symbol = NULL;
10146 expr1.X_add_number = 1;
10153 /* Fall through. */
10161 start_noreorder ();
10163 if (mips_opts.micromips)
10164 micromips_label_expr (&label_expr);
10166 label_expr.X_add_number = 8;
10167 macro_build (&label_expr, "bgez", "s,p", op[1]);
10168 if (op[0] == op[1])
10169 macro_build (NULL, "nop", "");
10171 move_register (op[0], op[1]);
10172 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", op[0], 0, op[1]);
10173 if (mips_opts.micromips)
10174 micromips_add_label ();
10191 if (!mips_opts.micromips)
10193 if (imm_expr.X_add_number >= -0x200
10194 && imm_expr.X_add_number < 0x200)
10196 macro_build (NULL, s, "t,r,.", op[0], op[1],
10197 (int) imm_expr.X_add_number);
10206 if (imm_expr.X_add_number >= -0x8000
10207 && imm_expr.X_add_number < 0x8000)
10209 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
10214 load_register (AT, &imm_expr, dbl);
10215 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
10234 if (imm_expr.X_add_number >= 0
10235 && imm_expr.X_add_number < 0x10000)
10237 if (mask != M_NOR_I)
10238 macro_build (&imm_expr, s, "t,r,i", op[0], op[1], BFD_RELOC_LO16);
10241 macro_build (&imm_expr, "ori", "t,r,i",
10242 op[0], op[1], BFD_RELOC_LO16);
10243 macro_build (NULL, "nor", "d,v,t", op[0], op[0], 0);
10249 load_register (AT, &imm_expr, GPR_SIZE == 64);
10250 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
10254 switch (imm_expr.X_add_number)
10257 macro_build (NULL, "nop", "");
10260 macro_build (NULL, "packrl.ph", "d,s,t", op[0], op[0], op[1]);
10264 macro_build (NULL, "balign", "t,s,2", op[0], op[1],
10265 (int) imm_expr.X_add_number);
10268 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
10269 (unsigned long) imm_expr.X_add_number);
10278 gas_assert (mips_opts.micromips);
10279 macro_build_branch_ccl (mask, &offset_expr,
10280 EXTRACT_OPERAND (1, BCC, *ip));
10287 if (imm_expr.X_add_number == 0)
10293 load_register (op[1], &imm_expr, GPR_SIZE == 64);
10295 /* Fall through. */
10298 macro_build_branch_rsrt (mask, &offset_expr, op[0], op[1]);
10303 /* Fall through. */
10306 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[0]);
10307 else if (op[0] == 0)
10308 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[1]);
10312 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
10313 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10314 &offset_expr, AT, ZERO);
10324 macro_build_branch_rs (mask, &offset_expr, op[0]);
10329 /* Fall through. */
10331 /* Check for > max integer. */
10332 if (imm_expr.X_add_number >= GPR_SMAX)
10335 /* Result is always false. */
10337 macro_build (NULL, "nop", "");
10339 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
10342 ++imm_expr.X_add_number;
10346 if (mask == M_BGEL_I)
10348 if (imm_expr.X_add_number == 0)
10350 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
10351 &offset_expr, op[0]);
10354 if (imm_expr.X_add_number == 1)
10356 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
10357 &offset_expr, op[0]);
10360 if (imm_expr.X_add_number <= GPR_SMIN)
10363 /* result is always true */
10364 as_warn (_("branch %s is always true"), ip->insn_mo->name);
10365 macro_build (&offset_expr, "b", "p");
10370 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10371 &offset_expr, AT, ZERO);
10376 /* Fall through. */
10380 else if (op[0] == 0)
10381 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10382 &offset_expr, ZERO, op[1]);
10386 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
10387 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10388 &offset_expr, AT, ZERO);
10394 /* Fall through. */
10398 && imm_expr.X_add_number == -1))
10400 ++imm_expr.X_add_number;
10404 if (mask == M_BGEUL_I)
10406 if (imm_expr.X_add_number == 0)
10408 else if (imm_expr.X_add_number == 1)
10409 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10410 &offset_expr, op[0], ZERO);
10415 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10416 &offset_expr, AT, ZERO);
10422 /* Fall through. */
10425 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[0]);
10426 else if (op[0] == 0)
10427 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[1]);
10431 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
10432 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10433 &offset_expr, AT, ZERO);
10439 /* Fall through. */
10442 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10443 &offset_expr, op[0], ZERO);
10444 else if (op[0] == 0)
10449 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
10450 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10451 &offset_expr, AT, ZERO);
10457 /* Fall through. */
10460 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
10461 else if (op[0] == 0)
10462 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[1]);
10466 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
10467 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10468 &offset_expr, AT, ZERO);
10474 /* Fall through. */
10476 if (imm_expr.X_add_number >= GPR_SMAX)
10478 ++imm_expr.X_add_number;
10482 if (mask == M_BLTL_I)
10484 if (imm_expr.X_add_number == 0)
10485 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
10486 else if (imm_expr.X_add_number == 1)
10487 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
10492 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10493 &offset_expr, AT, ZERO);
10499 /* Fall through. */
10502 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10503 &offset_expr, op[0], ZERO);
10504 else if (op[0] == 0)
10509 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
10510 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10511 &offset_expr, AT, ZERO);
10517 /* Fall through. */
10521 && imm_expr.X_add_number == -1))
10523 ++imm_expr.X_add_number;
10527 if (mask == M_BLTUL_I)
10529 if (imm_expr.X_add_number == 0)
10531 else if (imm_expr.X_add_number == 1)
10532 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10533 &offset_expr, op[0], ZERO);
10538 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10539 &offset_expr, AT, ZERO);
10545 /* Fall through. */
10548 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
10549 else if (op[0] == 0)
10550 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[1]);
10554 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
10555 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10556 &offset_expr, AT, ZERO);
10562 /* Fall through. */
10566 else if (op[0] == 0)
10567 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10568 &offset_expr, ZERO, op[1]);
10572 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
10573 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10574 &offset_expr, AT, ZERO);
10580 /* Fall through. */
10586 /* Fall through. */
10592 as_warn (_("divide by zero"));
10594 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
10596 macro_build (NULL, "break", BRK_FMT, 7);
10600 start_noreorder ();
10603 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
10604 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
10608 if (mips_opts.micromips)
10609 micromips_label_expr (&label_expr);
10611 label_expr.X_add_number = 8;
10612 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
10613 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
10614 macro_build (NULL, "break", BRK_FMT, 7);
10615 if (mips_opts.micromips)
10616 micromips_add_label ();
10618 expr1.X_add_number = -1;
10620 load_register (AT, &expr1, dbl);
10621 if (mips_opts.micromips)
10622 micromips_label_expr (&label_expr);
10624 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
10625 macro_build (&label_expr, "bne", "s,t,p", op[2], AT);
10628 expr1.X_add_number = 1;
10629 load_register (AT, &expr1, dbl);
10630 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
10634 expr1.X_add_number = 0x80000000;
10635 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
10639 macro_build (NULL, "teq", TRAP_FMT, op[1], AT, 6);
10640 /* We want to close the noreorder block as soon as possible, so
10641 that later insns are available for delay slot filling. */
10646 if (mips_opts.micromips)
10647 micromips_label_expr (&label_expr);
10649 label_expr.X_add_number = 8;
10650 macro_build (&label_expr, "bne", "s,t,p", op[1], AT);
10651 macro_build (NULL, "nop", "");
10653 /* We want to close the noreorder block as soon as possible, so
10654 that later insns are available for delay slot filling. */
10657 macro_build (NULL, "break", BRK_FMT, 6);
10659 if (mips_opts.micromips)
10660 micromips_add_label ();
10661 macro_build (NULL, s, MFHL_FMT, op[0]);
10700 if (imm_expr.X_add_number == 0)
10702 as_warn (_("divide by zero"));
10704 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
10706 macro_build (NULL, "break", BRK_FMT, 7);
10709 if (imm_expr.X_add_number == 1)
10711 if (strcmp (s2, "mflo") == 0)
10712 move_register (op[0], op[1]);
10714 move_register (op[0], ZERO);
10717 if (imm_expr.X_add_number == -1 && s[strlen (s) - 1] != 'u')
10719 if (strcmp (s2, "mflo") == 0)
10720 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", op[0], op[1]);
10722 move_register (op[0], ZERO);
10727 load_register (AT, &imm_expr, dbl);
10728 macro_build (NULL, s, "z,s,t", op[1], AT);
10729 macro_build (NULL, s2, MFHL_FMT, op[0]);
10748 start_noreorder ();
10751 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
10752 macro_build (NULL, s, "z,s,t", op[1], op[2]);
10753 /* We want to close the noreorder block as soon as possible, so
10754 that later insns are available for delay slot filling. */
10759 if (mips_opts.micromips)
10760 micromips_label_expr (&label_expr);
10762 label_expr.X_add_number = 8;
10763 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
10764 macro_build (NULL, s, "z,s,t", op[1], op[2]);
10766 /* We want to close the noreorder block as soon as possible, so
10767 that later insns are available for delay slot filling. */
10769 macro_build (NULL, "break", BRK_FMT, 7);
10770 if (mips_opts.micromips)
10771 micromips_add_label ();
10773 macro_build (NULL, s2, MFHL_FMT, op[0]);
10778 /* Fall through. */
10784 /* Fall through. */
10787 /* Load the address of a symbol into a register. If breg is not
10788 zero, we then add a base register to it. */
10791 if (dbl && GPR_SIZE == 32)
10792 as_warn (_("dla used to load 32-bit register; recommend using la "
10795 if (!dbl && HAVE_64BIT_OBJECTS)
10796 as_warn (_("la used to load 64-bit address; recommend using dla "
10799 if (small_offset_p (0, align, 16))
10801 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", op[0], breg,
10802 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
10806 if (mips_opts.at && (op[0] == breg))
10814 if (offset_expr.X_op != O_symbol
10815 && offset_expr.X_op != O_constant)
10817 as_bad (_("expression too complex"));
10818 offset_expr.X_op = O_constant;
10821 if (offset_expr.X_op == O_constant)
10822 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
10823 else if (mips_pic == NO_PIC)
10825 /* If this is a reference to a GP relative symbol, we want
10826 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
10828 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10829 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10830 If we have a constant, we need two instructions anyhow,
10831 so we may as well always use the latter form.
10833 With 64bit address space and a usable $at we want
10834 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10835 lui $at,<sym> (BFD_RELOC_HI16_S)
10836 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10837 daddiu $at,<sym> (BFD_RELOC_LO16)
10839 daddu $tempreg,$tempreg,$at
10841 If $at is already in use, we use a path which is suboptimal
10842 on superscalar processors.
10843 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10844 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10846 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10848 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
10850 For GP relative symbols in 64bit address space we can use
10851 the same sequence as in 32bit address space. */
10852 if (HAVE_64BIT_SYMBOLS)
10854 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10855 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10857 relax_start (offset_expr.X_add_symbol);
10858 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10859 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
10863 if (used_at == 0 && mips_opts.at)
10865 macro_build (&offset_expr, "lui", LUI_FMT,
10866 tempreg, BFD_RELOC_MIPS_HIGHEST);
10867 macro_build (&offset_expr, "lui", LUI_FMT,
10868 AT, BFD_RELOC_HI16_S);
10869 macro_build (&offset_expr, "daddiu", "t,r,j",
10870 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
10871 macro_build (&offset_expr, "daddiu", "t,r,j",
10872 AT, AT, BFD_RELOC_LO16);
10873 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
10874 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
10879 macro_build (&offset_expr, "lui", LUI_FMT,
10880 tempreg, BFD_RELOC_MIPS_HIGHEST);
10881 macro_build (&offset_expr, "daddiu", "t,r,j",
10882 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
10883 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
10884 macro_build (&offset_expr, "daddiu", "t,r,j",
10885 tempreg, tempreg, BFD_RELOC_HI16_S);
10886 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
10887 macro_build (&offset_expr, "daddiu", "t,r,j",
10888 tempreg, tempreg, BFD_RELOC_LO16);
10891 if (mips_relax.sequence)
10896 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10897 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10899 relax_start (offset_expr.X_add_symbol);
10900 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10901 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
10904 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
10905 as_bad (_("offset too large"));
10906 macro_build_lui (&offset_expr, tempreg);
10907 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10908 tempreg, tempreg, BFD_RELOC_LO16);
10909 if (mips_relax.sequence)
10913 else if (!mips_big_got && !HAVE_NEWABI)
10915 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
10917 /* If this is a reference to an external symbol, and there
10918 is no constant, we want
10919 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10920 or for lca or if tempreg is PIC_CALL_REG
10921 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10922 For a local symbol, we want
10923 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10925 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10927 If we have a small constant, and this is a reference to
10928 an external symbol, we want
10929 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10931 addiu $tempreg,$tempreg,<constant>
10932 For a local symbol, we want the same instruction
10933 sequence, but we output a BFD_RELOC_LO16 reloc on the
10936 If we have a large constant, and this is a reference to
10937 an external symbol, we want
10938 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10939 lui $at,<hiconstant>
10940 addiu $at,$at,<loconstant>
10941 addu $tempreg,$tempreg,$at
10942 For a local symbol, we want the same instruction
10943 sequence, but we output a BFD_RELOC_LO16 reloc on the
10947 if (offset_expr.X_add_number == 0)
10949 if (mips_pic == SVR4_PIC
10951 && (call || tempreg == PIC_CALL_REG))
10952 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
10954 relax_start (offset_expr.X_add_symbol);
10955 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10956 lw_reloc_type, mips_gp_register);
10959 /* We're going to put in an addu instruction using
10960 tempreg, so we may as well insert the nop right
10965 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10966 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
10968 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10969 tempreg, tempreg, BFD_RELOC_LO16);
10971 /* FIXME: If breg == 0, and the next instruction uses
10972 $tempreg, then if this variant case is used an extra
10973 nop will be generated. */
10975 else if (offset_expr.X_add_number >= -0x8000
10976 && offset_expr.X_add_number < 0x8000)
10978 load_got_offset (tempreg, &offset_expr);
10980 add_got_offset (tempreg, &offset_expr);
10984 expr1.X_add_number = offset_expr.X_add_number;
10985 offset_expr.X_add_number =
10986 SEXT_16BIT (offset_expr.X_add_number);
10987 load_got_offset (tempreg, &offset_expr);
10988 offset_expr.X_add_number = expr1.X_add_number;
10989 /* If we are going to add in a base register, and the
10990 target register and the base register are the same,
10991 then we are using AT as a temporary register. Since
10992 we want to load the constant into AT, we add our
10993 current AT (from the global offset table) and the
10994 register into the register now, and pretend we were
10995 not using a base register. */
10999 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11004 add_got_offset_hilo (tempreg, &offset_expr, AT);
11008 else if (!mips_big_got && HAVE_NEWABI)
11010 int add_breg_early = 0;
11012 /* If this is a reference to an external, and there is no
11013 constant, or local symbol (*), with or without a
11015 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11016 or for lca or if tempreg is PIC_CALL_REG
11017 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11019 If we have a small constant, and this is a reference to
11020 an external symbol, we want
11021 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11022 addiu $tempreg,$tempreg,<constant>
11024 If we have a large constant, and this is a reference to
11025 an external symbol, we want
11026 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11027 lui $at,<hiconstant>
11028 addiu $at,$at,<loconstant>
11029 addu $tempreg,$tempreg,$at
11031 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
11032 local symbols, even though it introduces an additional
11035 if (offset_expr.X_add_number)
11037 expr1.X_add_number = offset_expr.X_add_number;
11038 offset_expr.X_add_number = 0;
11040 relax_start (offset_expr.X_add_symbol);
11041 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11042 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
11044 if (expr1.X_add_number >= -0x8000
11045 && expr1.X_add_number < 0x8000)
11047 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
11048 tempreg, tempreg, BFD_RELOC_LO16);
11050 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
11054 /* If we are going to add in a base register, and the
11055 target register and the base register are the same,
11056 then we are using AT as a temporary register. Since
11057 we want to load the constant into AT, we add our
11058 current AT (from the global offset table) and the
11059 register into the register now, and pretend we were
11060 not using a base register. */
11065 gas_assert (tempreg == AT);
11066 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11069 add_breg_early = 1;
11072 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
11073 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11079 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11082 offset_expr.X_add_number = expr1.X_add_number;
11084 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11085 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
11086 if (add_breg_early)
11088 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11089 op[0], tempreg, breg);
11095 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
11097 relax_start (offset_expr.X_add_symbol);
11098 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11099 BFD_RELOC_MIPS_CALL16, mips_gp_register);
11101 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11102 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
11107 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11108 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
11111 else if (mips_big_got && !HAVE_NEWABI)
11114 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
11115 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
11116 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
11118 /* This is the large GOT case. If this is a reference to an
11119 external symbol, and there is no constant, we want
11120 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11121 addu $tempreg,$tempreg,$gp
11122 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11123 or for lca or if tempreg is PIC_CALL_REG
11124 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11125 addu $tempreg,$tempreg,$gp
11126 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11127 For a local symbol, we want
11128 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11130 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11132 If we have a small constant, and this is a reference to
11133 an external symbol, we want
11134 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11135 addu $tempreg,$tempreg,$gp
11136 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11138 addiu $tempreg,$tempreg,<constant>
11139 For a local symbol, we want
11140 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11142 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
11144 If we have a large constant, and this is a reference to
11145 an external symbol, we want
11146 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11147 addu $tempreg,$tempreg,$gp
11148 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11149 lui $at,<hiconstant>
11150 addiu $at,$at,<loconstant>
11151 addu $tempreg,$tempreg,$at
11152 For a local symbol, we want
11153 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11154 lui $at,<hiconstant>
11155 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
11156 addu $tempreg,$tempreg,$at
11159 expr1.X_add_number = offset_expr.X_add_number;
11160 offset_expr.X_add_number = 0;
11161 relax_start (offset_expr.X_add_symbol);
11162 gpdelay = reg_needs_delay (mips_gp_register);
11163 if (expr1.X_add_number == 0 && breg == 0
11164 && (call || tempreg == PIC_CALL_REG))
11166 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
11167 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
11169 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
11170 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11171 tempreg, tempreg, mips_gp_register);
11172 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11173 tempreg, lw_reloc_type, tempreg);
11174 if (expr1.X_add_number == 0)
11178 /* We're going to put in an addu instruction using
11179 tempreg, so we may as well insert the nop right
11184 else if (expr1.X_add_number >= -0x8000
11185 && expr1.X_add_number < 0x8000)
11188 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
11189 tempreg, tempreg, BFD_RELOC_LO16);
11195 /* If we are going to add in a base register, and the
11196 target register and the base register are the same,
11197 then we are using AT as a temporary register. Since
11198 we want to load the constant into AT, we add our
11199 current AT (from the global offset table) and the
11200 register into the register now, and pretend we were
11201 not using a base register. */
11206 gas_assert (tempreg == AT);
11208 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11213 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
11214 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
11218 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number);
11223 /* This is needed because this instruction uses $gp, but
11224 the first instruction on the main stream does not. */
11225 macro_build (NULL, "nop", "");
11228 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11229 local_reloc_type, mips_gp_register);
11230 if (expr1.X_add_number >= -0x8000
11231 && expr1.X_add_number < 0x8000)
11234 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11235 tempreg, tempreg, BFD_RELOC_LO16);
11236 /* FIXME: If add_number is 0, and there was no base
11237 register, the external symbol case ended with a load,
11238 so if the symbol turns out to not be external, and
11239 the next instruction uses tempreg, an unnecessary nop
11240 will be inserted. */
11246 /* We must add in the base register now, as in the
11247 external symbol case. */
11248 gas_assert (tempreg == AT);
11250 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11253 /* We set breg to 0 because we have arranged to add
11254 it in in both cases. */
11258 macro_build_lui (&expr1, AT);
11259 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11260 AT, AT, BFD_RELOC_LO16);
11261 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11262 tempreg, tempreg, AT);
11267 else if (mips_big_got && HAVE_NEWABI)
11269 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
11270 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
11271 int add_breg_early = 0;
11273 /* This is the large GOT case. If this is a reference to an
11274 external symbol, and there is no constant, we want
11275 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11276 add $tempreg,$tempreg,$gp
11277 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11278 or for lca or if tempreg is PIC_CALL_REG
11279 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11280 add $tempreg,$tempreg,$gp
11281 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11283 If we have a small constant, and this is a reference to
11284 an external symbol, we want
11285 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11286 add $tempreg,$tempreg,$gp
11287 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11288 addi $tempreg,$tempreg,<constant>
11290 If we have a large constant, and this is a reference to
11291 an external symbol, we want
11292 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11293 addu $tempreg,$tempreg,$gp
11294 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11295 lui $at,<hiconstant>
11296 addi $at,$at,<loconstant>
11297 add $tempreg,$tempreg,$at
11299 If we have NewABI, and we know it's a local symbol, we want
11300 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11301 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
11302 otherwise we have to resort to GOT_HI16/GOT_LO16. */
11304 relax_start (offset_expr.X_add_symbol);
11306 expr1.X_add_number = offset_expr.X_add_number;
11307 offset_expr.X_add_number = 0;
11309 if (expr1.X_add_number == 0 && breg == 0
11310 && (call || tempreg == PIC_CALL_REG))
11312 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
11313 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
11315 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
11316 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11317 tempreg, tempreg, mips_gp_register);
11318 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11319 tempreg, lw_reloc_type, tempreg);
11321 if (expr1.X_add_number == 0)
11323 else if (expr1.X_add_number >= -0x8000
11324 && expr1.X_add_number < 0x8000)
11326 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
11327 tempreg, tempreg, BFD_RELOC_LO16);
11329 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
11333 /* If we are going to add in a base register, and the
11334 target register and the base register are the same,
11335 then we are using AT as a temporary register. Since
11336 we want to load the constant into AT, we add our
11337 current AT (from the global offset table) and the
11338 register into the register now, and pretend we were
11339 not using a base register. */
11344 gas_assert (tempreg == AT);
11345 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11348 add_breg_early = 1;
11351 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
11352 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
11357 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11360 offset_expr.X_add_number = expr1.X_add_number;
11361 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11362 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
11363 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
11364 tempreg, BFD_RELOC_MIPS_GOT_OFST);
11365 if (add_breg_early)
11367 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11368 op[0], tempreg, breg);
11378 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", op[0], tempreg, breg);
11382 gas_assert (!mips_opts.micromips);
11383 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x01);
11387 gas_assert (!mips_opts.micromips);
11388 macro_build (NULL, "c2", "C", 0x02);
11392 gas_assert (!mips_opts.micromips);
11393 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x02);
11397 gas_assert (!mips_opts.micromips);
11398 macro_build (NULL, "c2", "C", 3);
11402 gas_assert (!mips_opts.micromips);
11403 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x03);
11407 /* The j instruction may not be used in PIC code, since it
11408 requires an absolute address. We convert it to a b
11410 if (mips_pic == NO_PIC)
11411 macro_build (&offset_expr, "j", "a");
11413 macro_build (&offset_expr, "b", "p");
11416 /* The jal instructions must be handled as macros because when
11417 generating PIC code they expand to multi-instruction
11418 sequences. Normally they are simple instructions. */
11422 /* Fall through. */
11424 gas_assert (mips_opts.micromips);
11425 if (mips_opts.insn32)
11427 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str);
11435 /* Fall through. */
11438 if (mips_pic == NO_PIC)
11440 s = jals ? "jalrs" : "jalr";
11441 if (mips_opts.micromips
11442 && !mips_opts.insn32
11444 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
11445 macro_build (NULL, s, "mj", op[1]);
11447 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
11451 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
11452 && mips_cprestore_offset >= 0);
11454 if (op[1] != PIC_CALL_REG)
11455 as_warn (_("MIPS PIC call to register other than $25"));
11457 s = ((mips_opts.micromips
11458 && !mips_opts.insn32
11459 && (!mips_opts.noreorder || cprestore))
11460 ? "jalrs" : "jalr");
11461 if (mips_opts.micromips
11462 && !mips_opts.insn32
11464 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
11465 macro_build (NULL, s, "mj", op[1]);
11467 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
11468 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
11470 if (mips_cprestore_offset < 0)
11471 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11474 if (!mips_frame_reg_valid)
11476 as_warn (_("no .frame pseudo-op used in PIC code"));
11477 /* Quiet this warning. */
11478 mips_frame_reg_valid = 1;
11480 if (!mips_cprestore_valid)
11482 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11483 /* Quiet this warning. */
11484 mips_cprestore_valid = 1;
11486 if (mips_opts.noreorder)
11487 macro_build (NULL, "nop", "");
11488 expr1.X_add_number = mips_cprestore_offset;
11489 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
11492 HAVE_64BIT_ADDRESSES);
11500 gas_assert (mips_opts.micromips);
11501 if (mips_opts.insn32)
11503 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str);
11507 /* Fall through. */
11509 if (mips_pic == NO_PIC)
11510 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
11511 else if (mips_pic == SVR4_PIC)
11513 /* If this is a reference to an external symbol, and we are
11514 using a small GOT, we want
11515 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11519 lw $gp,cprestore($sp)
11520 The cprestore value is set using the .cprestore
11521 pseudo-op. If we are using a big GOT, we want
11522 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11524 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11528 lw $gp,cprestore($sp)
11529 If the symbol is not external, we want
11530 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11532 addiu $25,$25,<sym> (BFD_RELOC_LO16)
11535 lw $gp,cprestore($sp)
11537 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11538 sequences above, minus nops, unless the symbol is local,
11539 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11545 relax_start (offset_expr.X_add_symbol);
11546 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11547 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
11550 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11551 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
11557 relax_start (offset_expr.X_add_symbol);
11558 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
11559 BFD_RELOC_MIPS_CALL_HI16);
11560 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
11561 PIC_CALL_REG, mips_gp_register);
11562 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11563 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
11566 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11567 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
11569 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11570 PIC_CALL_REG, PIC_CALL_REG,
11571 BFD_RELOC_MIPS_GOT_OFST);
11575 macro_build_jalr (&offset_expr, 0);
11579 relax_start (offset_expr.X_add_symbol);
11582 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11583 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
11592 gpdelay = reg_needs_delay (mips_gp_register);
11593 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
11594 BFD_RELOC_MIPS_CALL_HI16);
11595 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
11596 PIC_CALL_REG, mips_gp_register);
11597 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11598 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
11603 macro_build (NULL, "nop", "");
11605 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11606 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
11609 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11610 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
11612 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
11614 if (mips_cprestore_offset < 0)
11615 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11618 if (!mips_frame_reg_valid)
11620 as_warn (_("no .frame pseudo-op used in PIC code"));
11621 /* Quiet this warning. */
11622 mips_frame_reg_valid = 1;
11624 if (!mips_cprestore_valid)
11626 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11627 /* Quiet this warning. */
11628 mips_cprestore_valid = 1;
11630 if (mips_opts.noreorder)
11631 macro_build (NULL, "nop", "");
11632 expr1.X_add_number = mips_cprestore_offset;
11633 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
11636 HAVE_64BIT_ADDRESSES);
11640 else if (mips_pic == VXWORKS_PIC)
11641 as_bad (_("non-PIC jump used in PIC library"));
11748 gas_assert (!mips_opts.micromips);
11751 /* Itbl support may require additional care here. */
11757 /* Itbl support may require additional care here. */
11763 offbits = (mips_opts.micromips ? 12
11764 : ISA_IS_R6 (mips_opts.isa) ? 11
11766 /* Itbl support may require additional care here. */
11770 gas_assert (!mips_opts.micromips);
11773 /* Itbl support may require additional care here. */
11779 offbits = (mips_opts.micromips ? 12 : 16);
11784 offbits = (mips_opts.micromips ? 12 : 16);
11789 /* Itbl support may require additional care here. */
11795 offbits = (mips_opts.micromips ? 12
11796 : ISA_IS_R6 (mips_opts.isa) ? 11
11798 /* Itbl support may require additional care here. */
11804 /* Itbl support may require additional care here. */
11810 /* Itbl support may require additional care here. */
11816 offbits = (mips_opts.micromips ? 12 : 16);
11821 offbits = (mips_opts.micromips ? 12 : 16);
11826 offbits = (mips_opts.micromips ? 12
11827 : ISA_IS_R6 (mips_opts.isa) ? 9
11833 offbits = (mips_opts.micromips ? 12
11834 : ISA_IS_R6 (mips_opts.isa) ? 9
11840 offbits = (mips_opts.micromips ? 12 : 16);
11843 gas_assert (mips_opts.micromips);
11850 gas_assert (mips_opts.micromips);
11857 gas_assert (mips_opts.micromips);
11863 gas_assert (mips_opts.micromips);
11870 /* We don't want to use $0 as tempreg. */
11871 if (op[2] == op[0] + lp || op[0] + lp == ZERO)
11874 tempreg = op[0] + lp;
11890 gas_assert (!mips_opts.micromips);
11893 /* Itbl support may require additional care here. */
11899 /* Itbl support may require additional care here. */
11905 offbits = (mips_opts.micromips ? 12
11906 : ISA_IS_R6 (mips_opts.isa) ? 11
11908 /* Itbl support may require additional care here. */
11912 gas_assert (!mips_opts.micromips);
11915 /* Itbl support may require additional care here. */
11921 offbits = (mips_opts.micromips ? 12 : 16);
11926 offbits = (mips_opts.micromips ? 12 : 16);
11931 offbits = (mips_opts.micromips ? 12
11932 : ISA_IS_R6 (mips_opts.isa) ? 9
11938 offbits = (mips_opts.micromips ? 12
11939 : ISA_IS_R6 (mips_opts.isa) ? 9
11944 fmt = (mips_opts.micromips ? "k,~(b)"
11945 : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)"
11947 offbits = (mips_opts.micromips ? 12
11948 : ISA_IS_R6 (mips_opts.isa) ? 9
11958 fmt = (mips_opts.micromips ? "k,~(b)"
11959 : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)"
11961 offbits = (mips_opts.micromips ? 12
11962 : ISA_IS_R6 (mips_opts.isa) ? 9
11974 /* Itbl support may require additional care here. */
11979 offbits = (mips_opts.micromips ? 12
11980 : ISA_IS_R6 (mips_opts.isa) ? 11
11982 /* Itbl support may require additional care here. */
11988 /* Itbl support may require additional care here. */
11992 gas_assert (!mips_opts.micromips);
11995 /* Itbl support may require additional care here. */
12001 offbits = (mips_opts.micromips ? 12 : 16);
12006 offbits = (mips_opts.micromips ? 12 : 16);
12009 gas_assert (mips_opts.micromips);
12015 gas_assert (mips_opts.micromips);
12021 gas_assert (mips_opts.micromips);
12027 gas_assert (mips_opts.micromips);
12036 if (small_offset_p (0, align, 16))
12038 /* The first case exists for M_LD_AB and M_SD_AB, which are
12039 macros for o32 but which should act like normal instructions
12042 macro_build (&offset_expr, s, fmt, op[0], -1, offset_reloc[0],
12043 offset_reloc[1], offset_reloc[2], breg);
12044 else if (small_offset_p (0, align, offbits))
12047 macro_build (NULL, s, fmt, op[0], breg);
12049 macro_build (NULL, s, fmt, op[0],
12050 (int) offset_expr.X_add_number, breg);
12056 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
12057 tempreg, breg, -1, offset_reloc[0],
12058 offset_reloc[1], offset_reloc[2]);
12060 macro_build (NULL, s, fmt, op[0], tempreg);
12062 macro_build (NULL, s, fmt, op[0], 0, tempreg);
12070 if (offset_expr.X_op != O_constant
12071 && offset_expr.X_op != O_symbol)
12073 as_bad (_("expression too complex"));
12074 offset_expr.X_op = O_constant;
12077 if (HAVE_32BIT_ADDRESSES
12078 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
12082 sprintf_vma (value, offset_expr.X_add_number);
12083 as_bad (_("number (0x%s) larger than 32 bits"), value);
12086 /* A constant expression in PIC code can be handled just as it
12087 is in non PIC code. */
12088 if (offset_expr.X_op == O_constant)
12090 expr1.X_add_number = offset_high_part (offset_expr.X_add_number,
12091 offbits == 0 ? 16 : offbits);
12092 offset_expr.X_add_number -= expr1.X_add_number;
12094 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
12096 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12097 tempreg, tempreg, breg);
12100 if (offset_expr.X_add_number != 0)
12101 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
12102 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
12103 macro_build (NULL, s, fmt, op[0], tempreg);
12105 else if (offbits == 16)
12106 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
12108 macro_build (NULL, s, fmt, op[0],
12109 (int) offset_expr.X_add_number, tempreg);
12111 else if (offbits != 16)
12113 /* The offset field is too narrow to be used for a low-part
12114 relocation, so load the whole address into the auxiliary
12116 load_address (tempreg, &offset_expr, &used_at);
12118 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12119 tempreg, tempreg, breg);
12121 macro_build (NULL, s, fmt, op[0], tempreg);
12123 macro_build (NULL, s, fmt, op[0], 0, tempreg);
12125 else if (mips_pic == NO_PIC)
12127 /* If this is a reference to a GP relative symbol, and there
12128 is no base register, we want
12129 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12130 Otherwise, if there is no base register, we want
12131 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12132 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12133 If we have a constant, we need two instructions anyhow,
12134 so we always use the latter form.
12136 If we have a base register, and this is a reference to a
12137 GP relative symbol, we want
12138 addu $tempreg,$breg,$gp
12139 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
12141 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12142 addu $tempreg,$tempreg,$breg
12143 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12144 With a constant we always use the latter case.
12146 With 64bit address space and no base register and $at usable,
12148 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12149 lui $at,<sym> (BFD_RELOC_HI16_S)
12150 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12153 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12154 If we have a base register, we want
12155 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12156 lui $at,<sym> (BFD_RELOC_HI16_S)
12157 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12161 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12163 Without $at we can't generate the optimal path for superscalar
12164 processors here since this would require two temporary registers.
12165 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12166 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12168 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12170 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12171 If we have a base register, we want
12172 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12173 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12175 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12177 daddu $tempreg,$tempreg,$breg
12178 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12180 For GP relative symbols in 64bit address space we can use
12181 the same sequence as in 32bit address space. */
12182 if (HAVE_64BIT_SYMBOLS)
12184 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
12185 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
12187 relax_start (offset_expr.X_add_symbol);
12190 macro_build (&offset_expr, s, fmt, op[0],
12191 BFD_RELOC_GPREL16, mips_gp_register);
12195 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12196 tempreg, breg, mips_gp_register);
12197 macro_build (&offset_expr, s, fmt, op[0],
12198 BFD_RELOC_GPREL16, tempreg);
12203 if (used_at == 0 && mips_opts.at)
12205 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
12206 BFD_RELOC_MIPS_HIGHEST);
12207 macro_build (&offset_expr, "lui", LUI_FMT, AT,
12209 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
12210 tempreg, BFD_RELOC_MIPS_HIGHER);
12212 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
12213 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
12214 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
12215 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16,
12221 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
12222 BFD_RELOC_MIPS_HIGHEST);
12223 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
12224 tempreg, BFD_RELOC_MIPS_HIGHER);
12225 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
12226 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
12227 tempreg, BFD_RELOC_HI16_S);
12228 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
12230 macro_build (NULL, "daddu", "d,v,t",
12231 tempreg, tempreg, breg);
12232 macro_build (&offset_expr, s, fmt, op[0],
12233 BFD_RELOC_LO16, tempreg);
12236 if (mips_relax.sequence)
12243 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
12244 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
12246 relax_start (offset_expr.X_add_symbol);
12247 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_GPREL16,
12251 macro_build_lui (&offset_expr, tempreg);
12252 macro_build (&offset_expr, s, fmt, op[0],
12253 BFD_RELOC_LO16, tempreg);
12254 if (mips_relax.sequence)
12259 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
12260 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
12262 relax_start (offset_expr.X_add_symbol);
12263 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12264 tempreg, breg, mips_gp_register);
12265 macro_build (&offset_expr, s, fmt, op[0],
12266 BFD_RELOC_GPREL16, tempreg);
12269 macro_build_lui (&offset_expr, tempreg);
12270 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12271 tempreg, tempreg, breg);
12272 macro_build (&offset_expr, s, fmt, op[0],
12273 BFD_RELOC_LO16, tempreg);
12274 if (mips_relax.sequence)
12278 else if (!mips_big_got)
12280 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
12282 /* If this is a reference to an external symbol, we want
12283 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12285 <op> op[0],0($tempreg)
12287 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12289 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12290 <op> op[0],0($tempreg)
12292 For NewABI, we want
12293 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12294 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
12296 If there is a base register, we add it to $tempreg before
12297 the <op>. If there is a constant, we stick it in the
12298 <op> instruction. We don't handle constants larger than
12299 16 bits, because we have no way to load the upper 16 bits
12300 (actually, we could handle them for the subset of cases
12301 in which we are not using $at). */
12302 gas_assert (offset_expr.X_op == O_symbol);
12305 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12306 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
12308 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12309 tempreg, tempreg, breg);
12310 macro_build (&offset_expr, s, fmt, op[0],
12311 BFD_RELOC_MIPS_GOT_OFST, tempreg);
12314 expr1.X_add_number = offset_expr.X_add_number;
12315 offset_expr.X_add_number = 0;
12316 if (expr1.X_add_number < -0x8000
12317 || expr1.X_add_number >= 0x8000)
12318 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12319 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12320 lw_reloc_type, mips_gp_register);
12322 relax_start (offset_expr.X_add_symbol);
12324 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
12325 tempreg, BFD_RELOC_LO16);
12328 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12329 tempreg, tempreg, breg);
12330 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
12332 else if (mips_big_got && !HAVE_NEWABI)
12336 /* If this is a reference to an external symbol, we want
12337 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12338 addu $tempreg,$tempreg,$gp
12339 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12340 <op> op[0],0($tempreg)
12342 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12344 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12345 <op> op[0],0($tempreg)
12346 If there is a base register, we add it to $tempreg before
12347 the <op>. If there is a constant, we stick it in the
12348 <op> instruction. We don't handle constants larger than
12349 16 bits, because we have no way to load the upper 16 bits
12350 (actually, we could handle them for the subset of cases
12351 in which we are not using $at). */
12352 gas_assert (offset_expr.X_op == O_symbol);
12353 expr1.X_add_number = offset_expr.X_add_number;
12354 offset_expr.X_add_number = 0;
12355 if (expr1.X_add_number < -0x8000
12356 || expr1.X_add_number >= 0x8000)
12357 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12358 gpdelay = reg_needs_delay (mips_gp_register);
12359 relax_start (offset_expr.X_add_symbol);
12360 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
12361 BFD_RELOC_MIPS_GOT_HI16);
12362 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
12364 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12365 BFD_RELOC_MIPS_GOT_LO16, tempreg);
12368 macro_build (NULL, "nop", "");
12369 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12370 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12372 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
12373 tempreg, BFD_RELOC_LO16);
12377 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12378 tempreg, tempreg, breg);
12379 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
12381 else if (mips_big_got && HAVE_NEWABI)
12383 /* If this is a reference to an external symbol, we want
12384 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12385 add $tempreg,$tempreg,$gp
12386 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12387 <op> op[0],<ofst>($tempreg)
12388 Otherwise, for local symbols, we want:
12389 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12390 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
12391 gas_assert (offset_expr.X_op == O_symbol);
12392 expr1.X_add_number = offset_expr.X_add_number;
12393 offset_expr.X_add_number = 0;
12394 if (expr1.X_add_number < -0x8000
12395 || expr1.X_add_number >= 0x8000)
12396 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12397 relax_start (offset_expr.X_add_symbol);
12398 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
12399 BFD_RELOC_MIPS_GOT_HI16);
12400 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
12402 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12403 BFD_RELOC_MIPS_GOT_LO16, tempreg);
12405 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12406 tempreg, tempreg, breg);
12407 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
12410 offset_expr.X_add_number = expr1.X_add_number;
12411 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12412 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
12414 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12415 tempreg, tempreg, breg);
12416 macro_build (&offset_expr, s, fmt, op[0],
12417 BFD_RELOC_MIPS_GOT_OFST, tempreg);
12426 gas_assert (mips_opts.micromips);
12427 gas_assert (mips_opts.insn32);
12428 start_noreorder ();
12429 macro_build (NULL, "jr", "s", RA);
12430 expr1.X_add_number = op[0] << 2;
12431 macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16);
12436 gas_assert (mips_opts.micromips);
12437 gas_assert (mips_opts.insn32);
12438 macro_build (NULL, "jr", "s", op[0]);
12439 if (mips_opts.noreorder)
12440 macro_build (NULL, "nop", "");
12445 load_register (op[0], &imm_expr, 0);
12449 load_register (op[0], &imm_expr, 1);
12453 if (imm_expr.X_op == O_constant)
12456 load_register (AT, &imm_expr, 0);
12457 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
12462 gas_assert (imm_expr.X_op == O_absent
12463 && offset_expr.X_op == O_symbol
12464 && strcmp (segment_name (S_GET_SEGMENT
12465 (offset_expr.X_add_symbol)),
12467 && offset_expr.X_add_number == 0);
12468 macro_build (&offset_expr, "lwc1", "T,o(b)", op[0],
12469 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
12474 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12475 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12476 order 32 bits of the value and the low order 32 bits are either
12477 zero or in OFFSET_EXPR. */
12478 if (imm_expr.X_op == O_constant)
12480 if (GPR_SIZE == 64)
12481 load_register (op[0], &imm_expr, 1);
12486 if (target_big_endian)
12498 load_register (hreg, &imm_expr, 0);
12501 if (offset_expr.X_op == O_absent)
12502 move_register (lreg, 0);
12505 gas_assert (offset_expr.X_op == O_constant);
12506 load_register (lreg, &offset_expr, 0);
12512 gas_assert (imm_expr.X_op == O_absent);
12514 /* We know that sym is in the .rdata section. First we get the
12515 upper 16 bits of the address. */
12516 if (mips_pic == NO_PIC)
12518 macro_build_lui (&offset_expr, AT);
12523 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12524 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12528 /* Now we load the register(s). */
12529 if (GPR_SIZE == 64)
12532 macro_build (&offset_expr, "ld", "t,o(b)", op[0],
12533 BFD_RELOC_LO16, AT);
12538 macro_build (&offset_expr, "lw", "t,o(b)", op[0],
12539 BFD_RELOC_LO16, AT);
12542 /* FIXME: How in the world do we deal with the possible
12544 offset_expr.X_add_number += 4;
12545 macro_build (&offset_expr, "lw", "t,o(b)",
12546 op[0] + 1, BFD_RELOC_LO16, AT);
12552 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12553 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12554 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12555 the value and the low order 32 bits are either zero or in
12557 if (imm_expr.X_op == O_constant)
12560 load_register (AT, &imm_expr, FPR_SIZE == 64);
12561 if (FPR_SIZE == 64 && GPR_SIZE == 64)
12562 macro_build (NULL, "dmtc1", "t,S", AT, op[0]);
12565 if (ISA_HAS_MXHC1 (mips_opts.isa))
12566 macro_build (NULL, "mthc1", "t,G", AT, op[0]);
12567 else if (FPR_SIZE != 32)
12568 as_bad (_("Unable to generate `%s' compliant code "
12570 (FPR_SIZE == 64) ? "fp64" : "fpxx");
12572 macro_build (NULL, "mtc1", "t,G", AT, op[0] + 1);
12573 if (offset_expr.X_op == O_absent)
12574 macro_build (NULL, "mtc1", "t,G", 0, op[0]);
12577 gas_assert (offset_expr.X_op == O_constant);
12578 load_register (AT, &offset_expr, 0);
12579 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
12585 gas_assert (imm_expr.X_op == O_absent
12586 && offset_expr.X_op == O_symbol
12587 && offset_expr.X_add_number == 0);
12588 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
12589 if (strcmp (s, ".lit8") == 0)
12591 op[2] = mips_gp_register;
12592 offset_reloc[0] = BFD_RELOC_MIPS_LITERAL;
12593 offset_reloc[1] = BFD_RELOC_UNUSED;
12594 offset_reloc[2] = BFD_RELOC_UNUSED;
12598 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
12600 if (mips_pic != NO_PIC)
12601 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12602 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12605 /* FIXME: This won't work for a 64 bit address. */
12606 macro_build_lui (&offset_expr, AT);
12610 offset_reloc[0] = BFD_RELOC_LO16;
12611 offset_reloc[1] = BFD_RELOC_UNUSED;
12612 offset_reloc[2] = BFD_RELOC_UNUSED;
12619 * The MIPS assembler seems to check for X_add_number not
12620 * being double aligned and generating:
12621 * lui at,%hi(foo+1)
12623 * addiu at,at,%lo(foo+1)
12626 * But, the resulting address is the same after relocation so why
12627 * generate the extra instruction?
12629 /* Itbl support may require additional care here. */
12632 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
12641 gas_assert (!mips_opts.micromips);
12642 /* Itbl support may require additional care here. */
12645 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
12665 if (GPR_SIZE == 64)
12675 if (GPR_SIZE == 64)
12683 /* Even on a big endian machine $fn comes before $fn+1. We have
12684 to adjust when loading from memory. We set coproc if we must
12685 load $fn+1 first. */
12686 /* Itbl support may require additional care here. */
12687 if (!target_big_endian)
12691 if (small_offset_p (0, align, 16))
12694 if (!small_offset_p (4, align, 16))
12696 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg,
12697 -1, offset_reloc[0], offset_reloc[1],
12699 expr1.X_add_number = 0;
12703 offset_reloc[0] = BFD_RELOC_LO16;
12704 offset_reloc[1] = BFD_RELOC_UNUSED;
12705 offset_reloc[2] = BFD_RELOC_UNUSED;
12707 if (strcmp (s, "lw") == 0 && op[0] == breg)
12709 ep->X_add_number += 4;
12710 macro_build (ep, s, fmt, op[0] + 1, -1, offset_reloc[0],
12711 offset_reloc[1], offset_reloc[2], breg);
12712 ep->X_add_number -= 4;
12713 macro_build (ep, s, fmt, op[0], -1, offset_reloc[0],
12714 offset_reloc[1], offset_reloc[2], breg);
12718 macro_build (ep, s, fmt, coproc ? op[0] + 1 : op[0], -1,
12719 offset_reloc[0], offset_reloc[1], offset_reloc[2],
12721 ep->X_add_number += 4;
12722 macro_build (ep, s, fmt, coproc ? op[0] : op[0] + 1, -1,
12723 offset_reloc[0], offset_reloc[1], offset_reloc[2],
12729 if (offset_expr.X_op != O_symbol
12730 && offset_expr.X_op != O_constant)
12732 as_bad (_("expression too complex"));
12733 offset_expr.X_op = O_constant;
12736 if (HAVE_32BIT_ADDRESSES
12737 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
12741 sprintf_vma (value, offset_expr.X_add_number);
12742 as_bad (_("number (0x%s) larger than 32 bits"), value);
12745 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
12747 /* If this is a reference to a GP relative symbol, we want
12748 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12749 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
12750 If we have a base register, we use this
12752 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
12753 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
12754 If this is not a GP relative symbol, we want
12755 lui $at,<sym> (BFD_RELOC_HI16_S)
12756 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12757 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12758 If there is a base register, we add it to $at after the
12759 lui instruction. If there is a constant, we always use
12761 if (offset_expr.X_op == O_symbol
12762 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
12763 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
12765 relax_start (offset_expr.X_add_symbol);
12768 tempreg = mips_gp_register;
12772 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12773 AT, breg, mips_gp_register);
12778 /* Itbl support may require additional care here. */
12779 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12780 BFD_RELOC_GPREL16, tempreg);
12781 offset_expr.X_add_number += 4;
12783 /* Set mips_optimize to 2 to avoid inserting an
12785 hold_mips_optimize = mips_optimize;
12787 /* Itbl support may require additional care here. */
12788 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12789 BFD_RELOC_GPREL16, tempreg);
12790 mips_optimize = hold_mips_optimize;
12794 offset_expr.X_add_number -= 4;
12797 if (offset_high_part (offset_expr.X_add_number, 16)
12798 != offset_high_part (offset_expr.X_add_number + 4, 16))
12800 load_address (AT, &offset_expr, &used_at);
12801 offset_expr.X_op = O_constant;
12802 offset_expr.X_add_number = 0;
12805 macro_build_lui (&offset_expr, AT);
12807 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12808 /* Itbl support may require additional care here. */
12809 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12810 BFD_RELOC_LO16, AT);
12811 /* FIXME: How do we handle overflow here? */
12812 offset_expr.X_add_number += 4;
12813 /* Itbl support may require additional care here. */
12814 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12815 BFD_RELOC_LO16, AT);
12816 if (mips_relax.sequence)
12819 else if (!mips_big_got)
12821 /* If this is a reference to an external symbol, we want
12822 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12825 <op> op[0]+1,4($at)
12827 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12829 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12830 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12831 If there is a base register we add it to $at before the
12832 lwc1 instructions. If there is a constant we include it
12833 in the lwc1 instructions. */
12835 expr1.X_add_number = offset_expr.X_add_number;
12836 if (expr1.X_add_number < -0x8000
12837 || expr1.X_add_number >= 0x8000 - 4)
12838 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12839 load_got_offset (AT, &offset_expr);
12842 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12844 /* Set mips_optimize to 2 to avoid inserting an undesired
12846 hold_mips_optimize = mips_optimize;
12849 /* Itbl support may require additional care here. */
12850 relax_start (offset_expr.X_add_symbol);
12851 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
12852 BFD_RELOC_LO16, AT);
12853 expr1.X_add_number += 4;
12854 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
12855 BFD_RELOC_LO16, AT);
12857 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12858 BFD_RELOC_LO16, AT);
12859 offset_expr.X_add_number += 4;
12860 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12861 BFD_RELOC_LO16, AT);
12864 mips_optimize = hold_mips_optimize;
12866 else if (mips_big_got)
12870 /* If this is a reference to an external symbol, we want
12871 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12873 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
12876 <op> op[0]+1,4($at)
12878 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12880 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12881 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12882 If there is a base register we add it to $at before the
12883 lwc1 instructions. If there is a constant we include it
12884 in the lwc1 instructions. */
12886 expr1.X_add_number = offset_expr.X_add_number;
12887 offset_expr.X_add_number = 0;
12888 if (expr1.X_add_number < -0x8000
12889 || expr1.X_add_number >= 0x8000 - 4)
12890 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12891 gpdelay = reg_needs_delay (mips_gp_register);
12892 relax_start (offset_expr.X_add_symbol);
12893 macro_build (&offset_expr, "lui", LUI_FMT,
12894 AT, BFD_RELOC_MIPS_GOT_HI16);
12895 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12896 AT, AT, mips_gp_register);
12897 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
12898 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
12901 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12902 /* Itbl support may require additional care here. */
12903 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
12904 BFD_RELOC_LO16, AT);
12905 expr1.X_add_number += 4;
12907 /* Set mips_optimize to 2 to avoid inserting an undesired
12909 hold_mips_optimize = mips_optimize;
12911 /* Itbl support may require additional care here. */
12912 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
12913 BFD_RELOC_LO16, AT);
12914 mips_optimize = hold_mips_optimize;
12915 expr1.X_add_number -= 4;
12918 offset_expr.X_add_number = expr1.X_add_number;
12920 macro_build (NULL, "nop", "");
12921 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12922 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12925 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12926 /* Itbl support may require additional care here. */
12927 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12928 BFD_RELOC_LO16, AT);
12929 offset_expr.X_add_number += 4;
12931 /* Set mips_optimize to 2 to avoid inserting an undesired
12933 hold_mips_optimize = mips_optimize;
12935 /* Itbl support may require additional care here. */
12936 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12937 BFD_RELOC_LO16, AT);
12938 mips_optimize = hold_mips_optimize;
12952 gas_assert (!mips_opts.micromips);
12957 /* New code added to support COPZ instructions.
12958 This code builds table entries out of the macros in mip_opcodes.
12959 R4000 uses interlocks to handle coproc delays.
12960 Other chips (like the R3000) require nops to be inserted for delays.
12962 FIXME: Currently, we require that the user handle delays.
12963 In order to fill delay slots for non-interlocked chips,
12964 we must have a way to specify delays based on the coprocessor.
12965 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
12966 What are the side-effects of the cop instruction?
12967 What cache support might we have and what are its effects?
12968 Both coprocessor & memory require delays. how long???
12969 What registers are read/set/modified?
12971 If an itbl is provided to interpret cop instructions,
12972 this knowledge can be encoded in the itbl spec. */
12986 gas_assert (!mips_opts.micromips);
12987 /* For now we just do C (same as Cz). The parameter will be
12988 stored in insn_opcode by mips_ip. */
12989 macro_build (NULL, s, "C", (int) ip->insn_opcode);
12993 move_register (op[0], op[1]);
12997 gas_assert (mips_opts.micromips);
12998 gas_assert (mips_opts.insn32);
12999 move_register (micromips_to_32_reg_h_map1[op[0]],
13000 micromips_to_32_reg_m_map[op[1]]);
13001 move_register (micromips_to_32_reg_h_map2[op[0]],
13002 micromips_to_32_reg_n_map[op[2]]);
13007 /* Fall through. */
13009 if (mips_opts.arch == CPU_R5900)
13010 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", op[0], op[1],
13014 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", op[1], op[2]);
13015 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
13021 /* Fall through. */
13023 /* The MIPS assembler some times generates shifts and adds. I'm
13024 not trying to be that fancy. GCC should do this for us
13027 load_register (AT, &imm_expr, dbl);
13028 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", op[1], AT);
13029 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
13034 /* Fall through. */
13041 /* Fall through. */
13044 start_noreorder ();
13047 load_register (AT, &imm_expr, dbl);
13048 macro_build (NULL, dbl ? "dmult" : "mult", "s,t",
13049 op[1], imm ? AT : op[2]);
13050 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
13051 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, op[0], op[0], 31);
13052 macro_build (NULL, "mfhi", MFHL_FMT, AT);
13054 macro_build (NULL, "tne", TRAP_FMT, op[0], AT, 6);
13057 if (mips_opts.micromips)
13058 micromips_label_expr (&label_expr);
13060 label_expr.X_add_number = 8;
13061 macro_build (&label_expr, "beq", "s,t,p", op[0], AT);
13062 macro_build (NULL, "nop", "");
13063 macro_build (NULL, "break", BRK_FMT, 6);
13064 if (mips_opts.micromips)
13065 micromips_add_label ();
13068 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
13073 /* Fall through. */
13080 /* Fall through. */
13083 start_noreorder ();
13086 load_register (AT, &imm_expr, dbl);
13087 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
13088 op[1], imm ? AT : op[2]);
13089 macro_build (NULL, "mfhi", MFHL_FMT, AT);
13090 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
13092 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
13095 if (mips_opts.micromips)
13096 micromips_label_expr (&label_expr);
13098 label_expr.X_add_number = 8;
13099 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
13100 macro_build (NULL, "nop", "");
13101 macro_build (NULL, "break", BRK_FMT, 6);
13102 if (mips_opts.micromips)
13103 micromips_add_label ();
13109 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
13111 if (op[0] == op[1])
13118 macro_build (NULL, "dnegu", "d,w", tempreg, op[2]);
13119 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], tempreg);
13123 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
13124 macro_build (NULL, "dsrlv", "d,t,s", AT, op[1], AT);
13125 macro_build (NULL, "dsllv", "d,t,s", op[0], op[1], op[2]);
13126 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13130 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
13132 if (op[0] == op[1])
13139 macro_build (NULL, "negu", "d,w", tempreg, op[2]);
13140 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], tempreg);
13144 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
13145 macro_build (NULL, "srlv", "d,t,s", AT, op[1], AT);
13146 macro_build (NULL, "sllv", "d,t,s", op[0], op[1], op[2]);
13147 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13156 rot = imm_expr.X_add_number & 0x3f;
13157 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
13159 rot = (64 - rot) & 0x3f;
13161 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
13163 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
13168 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
13171 l = (rot < 0x20) ? "dsll" : "dsll32";
13172 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
13175 macro_build (NULL, l, SHFT_FMT, AT, op[1], rot);
13176 macro_build (NULL, rr, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
13177 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13185 rot = imm_expr.X_add_number & 0x1f;
13186 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
13188 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1],
13189 (32 - rot) & 0x1f);
13194 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
13198 macro_build (NULL, "sll", SHFT_FMT, AT, op[1], rot);
13199 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
13200 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13205 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
13207 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], op[2]);
13211 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
13212 macro_build (NULL, "dsllv", "d,t,s", AT, op[1], AT);
13213 macro_build (NULL, "dsrlv", "d,t,s", op[0], op[1], op[2]);
13214 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13218 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
13220 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], op[2]);
13224 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
13225 macro_build (NULL, "sllv", "d,t,s", AT, op[1], AT);
13226 macro_build (NULL, "srlv", "d,t,s", op[0], op[1], op[2]);
13227 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13236 rot = imm_expr.X_add_number & 0x3f;
13237 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
13240 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
13242 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
13247 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
13250 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
13251 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
13254 macro_build (NULL, rr, SHFT_FMT, AT, op[1], rot);
13255 macro_build (NULL, l, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
13256 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13264 rot = imm_expr.X_add_number & 0x1f;
13265 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
13267 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], rot);
13272 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
13276 macro_build (NULL, "srl", SHFT_FMT, AT, op[1], rot);
13277 macro_build (NULL, "sll", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
13278 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13284 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[2], BFD_RELOC_LO16);
13285 else if (op[2] == 0)
13286 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13289 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
13290 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
13295 if (imm_expr.X_add_number == 0)
13297 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13302 as_warn (_("instruction %s: result is always false"),
13303 ip->insn_mo->name);
13304 move_register (op[0], 0);
13307 if (CPU_HAS_SEQ (mips_opts.arch)
13308 && -512 <= imm_expr.X_add_number
13309 && imm_expr.X_add_number < 512)
13311 macro_build (NULL, "seqi", "t,r,+Q", op[0], op[1],
13312 (int) imm_expr.X_add_number);
13315 if (imm_expr.X_add_number >= 0
13316 && imm_expr.X_add_number < 0x10000)
13317 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], BFD_RELOC_LO16);
13318 else if (imm_expr.X_add_number > -0x8000
13319 && imm_expr.X_add_number < 0)
13321 imm_expr.X_add_number = -imm_expr.X_add_number;
13322 macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu",
13323 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13325 else if (CPU_HAS_SEQ (mips_opts.arch))
13328 load_register (AT, &imm_expr, GPR_SIZE == 64);
13329 macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT);
13334 load_register (AT, &imm_expr, GPR_SIZE == 64);
13335 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
13338 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
13341 case M_SGE: /* X >= Y <==> not (X < Y) */
13347 macro_build (NULL, s, "d,v,t", op[0], op[1], op[2]);
13348 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
13351 case M_SGE_I: /* X >= I <==> not (X < I) */
13353 if (imm_expr.X_add_number >= -0x8000
13354 && imm_expr.X_add_number < 0x8000)
13355 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
13356 op[0], op[1], BFD_RELOC_LO16);
13359 load_register (AT, &imm_expr, GPR_SIZE == 64);
13360 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
13364 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
13367 case M_SGT: /* X > Y <==> Y < X */
13373 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
13376 case M_SGT_I: /* X > I <==> I < X */
13383 load_register (AT, &imm_expr, GPR_SIZE == 64);
13384 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
13387 case M_SLE: /* X <= Y <==> Y >= X <==> not (Y < X) */
13393 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
13394 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
13397 case M_SLE_I: /* X <= I <==> I >= X <==> not (I < X) */
13404 load_register (AT, &imm_expr, GPR_SIZE == 64);
13405 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
13406 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
13410 if (imm_expr.X_add_number >= -0x8000
13411 && imm_expr.X_add_number < 0x8000)
13413 macro_build (&imm_expr, "slti", "t,r,j", op[0], op[1],
13418 load_register (AT, &imm_expr, GPR_SIZE == 64);
13419 macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT);
13423 if (imm_expr.X_add_number >= -0x8000
13424 && imm_expr.X_add_number < 0x8000)
13426 macro_build (&imm_expr, "sltiu", "t,r,j", op[0], op[1],
13431 load_register (AT, &imm_expr, GPR_SIZE == 64);
13432 macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT);
13437 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[2]);
13438 else if (op[2] == 0)
13439 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
13442 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
13443 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
13448 if (imm_expr.X_add_number == 0)
13450 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
13455 as_warn (_("instruction %s: result is always true"),
13456 ip->insn_mo->name);
13457 macro_build (&expr1, GPR_SIZE == 32 ? "addiu" : "daddiu", "t,r,j",
13458 op[0], 0, BFD_RELOC_LO16);
13461 if (CPU_HAS_SEQ (mips_opts.arch)
13462 && -512 <= imm_expr.X_add_number
13463 && imm_expr.X_add_number < 512)
13465 macro_build (NULL, "snei", "t,r,+Q", op[0], op[1],
13466 (int) imm_expr.X_add_number);
13469 if (imm_expr.X_add_number >= 0
13470 && imm_expr.X_add_number < 0x10000)
13472 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1],
13475 else if (imm_expr.X_add_number > -0x8000
13476 && imm_expr.X_add_number < 0)
13478 imm_expr.X_add_number = -imm_expr.X_add_number;
13479 macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu",
13480 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13482 else if (CPU_HAS_SEQ (mips_opts.arch))
13485 load_register (AT, &imm_expr, GPR_SIZE == 64);
13486 macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT);
13491 load_register (AT, &imm_expr, GPR_SIZE == 64);
13492 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
13495 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
13510 if (!mips_opts.micromips)
13512 if (imm_expr.X_add_number > -0x200
13513 && imm_expr.X_add_number <= 0x200)
13515 macro_build (NULL, s, "t,r,.", op[0], op[1],
13516 (int) -imm_expr.X_add_number);
13525 if (imm_expr.X_add_number > -0x8000
13526 && imm_expr.X_add_number <= 0x8000)
13528 imm_expr.X_add_number = -imm_expr.X_add_number;
13529 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13534 load_register (AT, &imm_expr, dbl);
13535 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
13557 load_register (AT, &imm_expr, GPR_SIZE == 64);
13558 macro_build (NULL, s, "s,t", op[0], AT);
13563 gas_assert (!mips_opts.micromips);
13564 gas_assert (mips_opts.isa == ISA_MIPS1);
13568 * Is the double cfc1 instruction a bug in the mips assembler;
13569 * or is there a reason for it?
13571 start_noreorder ();
13572 macro_build (NULL, "cfc1", "t,G", op[2], RA);
13573 macro_build (NULL, "cfc1", "t,G", op[2], RA);
13574 macro_build (NULL, "nop", "");
13575 expr1.X_add_number = 3;
13576 macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16);
13577 expr1.X_add_number = 2;
13578 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
13579 macro_build (NULL, "ctc1", "t,G", AT, RA);
13580 macro_build (NULL, "nop", "");
13581 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
13583 macro_build (NULL, "ctc1", "t,G", op[2], RA);
13584 macro_build (NULL, "nop", "");
13601 offbits = (mips_opts.micromips ? 12 : 16);
13607 offbits = (mips_opts.micromips ? 12 : 16);
13619 offbits = (mips_opts.micromips ? 12 : 16);
13626 offbits = (mips_opts.micromips ? 12 : 16);
13632 large_offset = !small_offset_p (off, align, offbits);
13634 expr1.X_add_number = 0;
13639 if (small_offset_p (0, align, 16))
13640 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1,
13641 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
13644 load_address (tempreg, ep, &used_at);
13646 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
13647 tempreg, tempreg, breg);
13649 offset_reloc[0] = BFD_RELOC_LO16;
13650 offset_reloc[1] = BFD_RELOC_UNUSED;
13651 offset_reloc[2] = BFD_RELOC_UNUSED;
13656 else if (!ust && op[0] == breg)
13667 if (!target_big_endian)
13668 ep->X_add_number += off;
13670 macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg);
13672 macro_build (ep, s, "t,o(b)", tempreg, -1,
13673 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13675 if (!target_big_endian)
13676 ep->X_add_number -= off;
13678 ep->X_add_number += off;
13680 macro_build (NULL, s2, "t,~(b)",
13681 tempreg, (int) ep->X_add_number, breg);
13683 macro_build (ep, s2, "t,o(b)", tempreg, -1,
13684 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13686 /* If necessary, move the result in tempreg to the final destination. */
13687 if (!ust && op[0] != tempreg)
13689 /* Protect second load's delay slot. */
13691 move_register (op[0], tempreg);
13697 if (target_big_endian == ust)
13698 ep->X_add_number += off;
13699 tempreg = ust || large_offset ? op[0] : AT;
13700 macro_build (ep, s, "t,o(b)", tempreg, -1,
13701 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13703 /* For halfword transfers we need a temporary register to shuffle
13704 bytes. Unfortunately for M_USH_A we have none available before
13705 the next store as AT holds the base address. We deal with this
13706 case by clobbering TREG and then restoring it as with ULH. */
13707 tempreg = ust == large_offset ? op[0] : AT;
13709 macro_build (NULL, "srl", SHFT_FMT, tempreg, op[0], 8);
13711 if (target_big_endian == ust)
13712 ep->X_add_number -= off;
13714 ep->X_add_number += off;
13715 macro_build (ep, s2, "t,o(b)", tempreg, -1,
13716 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13718 /* For M_USH_A re-retrieve the LSB. */
13719 if (ust && large_offset)
13721 if (target_big_endian)
13722 ep->X_add_number += off;
13724 ep->X_add_number -= off;
13725 macro_build (&expr1, "lbu", "t,o(b)", AT, -1,
13726 offset_reloc[0], offset_reloc[1], offset_reloc[2], AT);
13728 /* For ULH and M_USH_A OR the LSB in. */
13729 if (!ust || large_offset)
13731 tempreg = !large_offset ? AT : op[0];
13732 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
13733 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13738 /* FIXME: Check if this is one of the itbl macros, since they
13739 are added dynamically. */
13740 as_bad (_("macro %s not implemented yet"), ip->insn_mo->name);
13743 if (!mips_opts.at && used_at)
13744 as_bad (_("macro used $at after \".set noat\""));
13747 /* Implement macros in mips16 mode. */
13750 mips16_macro (struct mips_cl_insn *ip)
13752 const struct mips_operand_array *operands;
13757 const char *s, *s2, *s3;
13758 unsigned int op[MAX_OPERANDS];
13761 mask = ip->insn_mo->mask;
13763 operands = insn_operands (ip);
13764 for (i = 0; i < MAX_OPERANDS; i++)
13765 if (operands->operand[i])
13766 op[i] = insn_extract_operand (ip, operands->operand[i]);
13770 expr1.X_op = O_constant;
13771 expr1.X_op_symbol = NULL;
13772 expr1.X_add_symbol = NULL;
13773 expr1.X_add_number = 1;
13784 /* Fall through. */
13790 /* Fall through. */
13794 start_noreorder ();
13795 macro_build (NULL, dbl ? "ddiv" : "div", ".,x,y", op[1], op[2]);
13796 expr1.X_add_number = 2;
13797 macro_build (&expr1, "bnez", "x,p", op[2]);
13798 macro_build (NULL, "break", "6", 7);
13800 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
13801 since that causes an overflow. We should do that as well,
13802 but I don't see how to do the comparisons without a temporary
13805 macro_build (NULL, s, "x", op[0]);
13824 start_noreorder ();
13825 macro_build (NULL, s, ".,x,y", op[1], op[2]);
13826 expr1.X_add_number = 2;
13827 macro_build (&expr1, "bnez", "x,p", op[2]);
13828 macro_build (NULL, "break", "6", 7);
13830 macro_build (NULL, s2, "x", op[0]);
13835 /* Fall through. */
13837 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", op[1], op[2]);
13838 macro_build (NULL, "mflo", "x", op[0]);
13846 imm_expr.X_add_number = -imm_expr.X_add_number;
13847 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,F", op[0], op[1]);
13851 imm_expr.X_add_number = -imm_expr.X_add_number;
13852 macro_build (&imm_expr, "addiu", "x,k", op[0]);
13856 imm_expr.X_add_number = -imm_expr.X_add_number;
13857 macro_build (&imm_expr, "daddiu", "y,j", op[0]);
13879 goto do_reverse_branch;
13883 goto do_reverse_branch;
13895 goto do_reverse_branch;
13906 macro_build (NULL, s, "x,y", op[0], op[1]);
13907 macro_build (&offset_expr, s2, "p");
13934 goto do_addone_branch_i;
13939 goto do_addone_branch_i;
13954 goto do_addone_branch_i;
13960 do_addone_branch_i:
13961 ++imm_expr.X_add_number;
13964 macro_build (&imm_expr, s, s3, op[0]);
13965 macro_build (&offset_expr, s2, "p");
13969 expr1.X_add_number = 0;
13970 macro_build (&expr1, "slti", "x,8", op[1]);
13971 if (op[0] != op[1])
13972 macro_build (NULL, "move", "y,X", op[0], mips16_to_32_reg_map[op[1]]);
13973 expr1.X_add_number = 2;
13974 macro_build (&expr1, "bteqz", "p");
13975 macro_build (NULL, "neg", "x,w", op[0], op[0]);
13980 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
13981 opcode bits in *OPCODE_EXTRA. */
13983 static struct mips_opcode *
13984 mips_lookup_insn (struct hash_control *hash, const char *start,
13985 ssize_t length, unsigned int *opcode_extra)
13987 char *name, *dot, *p;
13988 unsigned int mask, suffix;
13990 struct mips_opcode *insn;
13992 /* Make a copy of the instruction so that we can fiddle with it. */
13993 name = xstrndup (start, length);
13995 /* Look up the instruction as-is. */
13996 insn = (struct mips_opcode *) hash_find (hash, name);
14000 dot = strchr (name, '.');
14003 /* Try to interpret the text after the dot as a VU0 channel suffix. */
14004 p = mips_parse_vu0_channels (dot + 1, &mask);
14005 if (*p == 0 && mask != 0)
14008 insn = (struct mips_opcode *) hash_find (hash, name);
14010 if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0)
14012 *opcode_extra |= mask << mips_vu0_channel_mask.lsb;
14018 if (mips_opts.micromips)
14020 /* See if there's an instruction size override suffix,
14021 either `16' or `32', at the end of the mnemonic proper,
14022 that defines the operation, i.e. before the first `.'
14023 character if any. Strip it and retry. */
14024 opend = dot != NULL ? dot - name : length;
14025 if (opend >= 3 && name[opend - 2] == '1' && name[opend - 1] == '6')
14027 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
14033 memmove (name + opend - 2, name + opend, length - opend + 1);
14034 insn = (struct mips_opcode *) hash_find (hash, name);
14037 forced_insn_length = suffix;
14049 /* Assemble an instruction into its binary format. If the instruction
14050 is a macro, set imm_expr and offset_expr to the values associated
14051 with "I" and "A" operands respectively. Otherwise store the value
14052 of the relocatable field (if any) in offset_expr. In both cases
14053 set offset_reloc to the relocation operators applied to offset_expr. */
14056 mips_ip (char *str, struct mips_cl_insn *insn)
14058 const struct mips_opcode *first, *past;
14059 struct hash_control *hash;
14062 struct mips_operand_token *tokens;
14063 unsigned int opcode_extra;
14065 if (mips_opts.micromips)
14067 hash = micromips_op_hash;
14068 past = µmips_opcodes[bfd_micromips_num_opcodes];
14073 past = &mips_opcodes[NUMOPCODES];
14075 forced_insn_length = 0;
14078 /* We first try to match an instruction up to a space or to the end. */
14079 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
14082 first = mips_lookup_insn (hash, str, end, &opcode_extra);
14085 set_insn_error (0, _("unrecognized opcode"));
14089 if (strcmp (first->name, "li.s") == 0)
14091 else if (strcmp (first->name, "li.d") == 0)
14095 tokens = mips_parse_arguments (str + end, format);
14099 if (!match_insns (insn, first, past, tokens, opcode_extra, FALSE)
14100 && !match_insns (insn, first, past, tokens, opcode_extra, TRUE))
14101 set_insn_error (0, _("invalid operands"));
14103 obstack_free (&mips_operand_tokens, tokens);
14106 /* As for mips_ip, but used when assembling MIPS16 code.
14107 Also set forced_insn_length to the resulting instruction size in
14108 bytes if the user explicitly requested a small or extended instruction. */
14111 mips16_ip (char *str, struct mips_cl_insn *insn)
14114 struct mips_opcode *first;
14115 struct mips_operand_token *tokens;
14118 for (s = str; *s != '\0' && *s != '.' && *s != ' '; ++s)
14140 else if (*s == 'e')
14147 else if (*s++ == ' ')
14149 set_insn_error (0, _("unrecognized opcode"));
14152 forced_insn_length = l;
14155 first = (struct mips_opcode *) hash_find (mips16_op_hash, str);
14160 set_insn_error (0, _("unrecognized opcode"));
14164 tokens = mips_parse_arguments (s, 0);
14168 if (!match_mips16_insns (insn, first, tokens))
14169 set_insn_error (0, _("invalid operands"));
14171 obstack_free (&mips_operand_tokens, tokens);
14174 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14175 NBITS is the number of significant bits in VAL. */
14177 static unsigned long
14178 mips16_immed_extend (offsetT val, unsigned int nbits)
14183 val &= (1U << nbits) - 1;
14184 if (nbits == 16 || nbits == 9)
14186 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
14189 else if (nbits == 15)
14191 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
14194 else if (nbits == 6)
14196 extval = ((val & 0x1f) << 6) | (val & 0x20);
14199 return (extval << 16) | val;
14202 /* Like decode_mips16_operand, but require the operand to be defined and
14203 require it to be an integer. */
14205 static const struct mips_int_operand *
14206 mips16_immed_operand (int type, bfd_boolean extended_p)
14208 const struct mips_operand *operand;
14210 operand = decode_mips16_operand (type, extended_p);
14211 if (!operand || (operand->type != OP_INT && operand->type != OP_PCREL))
14213 return (const struct mips_int_operand *) operand;
14216 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
14219 mips16_immed_in_range_p (const struct mips_int_operand *operand,
14220 bfd_reloc_code_real_type reloc, offsetT sval)
14222 int min_val, max_val;
14224 min_val = mips_int_operand_min (operand);
14225 max_val = mips_int_operand_max (operand);
14226 if (reloc != BFD_RELOC_UNUSED)
14229 sval = SEXT_16BIT (sval);
14234 return (sval >= min_val
14236 && (sval & ((1 << operand->shift) - 1)) == 0);
14239 /* Install immediate value VAL into MIPS16 instruction *INSN,
14240 extending it if necessary. The instruction in *INSN may
14241 already be extended.
14243 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14244 if none. In the former case, VAL is a 16-bit number with no
14245 defined signedness.
14247 TYPE is the type of the immediate field. USER_INSN_LENGTH
14248 is the length that the user requested, or 0 if none. */
14251 mips16_immed (const char *file, unsigned int line, int type,
14252 bfd_reloc_code_real_type reloc, offsetT val,
14253 unsigned int user_insn_length, unsigned long *insn)
14255 const struct mips_int_operand *operand;
14256 unsigned int uval, length;
14258 operand = mips16_immed_operand (type, FALSE);
14259 if (!mips16_immed_in_range_p (operand, reloc, val))
14261 /* We need an extended instruction. */
14262 if (user_insn_length == 2)
14263 as_bad_where (file, line, _("invalid unextended operand value"));
14265 *insn |= MIPS16_EXTEND;
14267 else if (user_insn_length == 4)
14269 /* The operand doesn't force an unextended instruction to be extended.
14270 Warn if the user wanted an extended instruction anyway. */
14271 *insn |= MIPS16_EXTEND;
14272 as_warn_where (file, line,
14273 _("extended operand requested but not required"));
14276 length = mips16_opcode_length (*insn);
14279 operand = mips16_immed_operand (type, TRUE);
14280 if (!mips16_immed_in_range_p (operand, reloc, val))
14281 as_bad_where (file, line,
14282 _("operand value out of range for instruction"));
14284 uval = ((unsigned int) val >> operand->shift) - operand->bias;
14285 if (length == 2 || operand->root.lsb != 0)
14286 *insn = mips_insert_operand (&operand->root, *insn, uval);
14288 *insn |= mips16_immed_extend (uval, operand->root.size);
14291 struct percent_op_match
14294 bfd_reloc_code_real_type reloc;
14297 static const struct percent_op_match mips_percent_op[] =
14299 {"%lo", BFD_RELOC_LO16},
14300 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
14301 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
14302 {"%call16", BFD_RELOC_MIPS_CALL16},
14303 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
14304 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
14305 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
14306 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
14307 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
14308 {"%got", BFD_RELOC_MIPS_GOT16},
14309 {"%gp_rel", BFD_RELOC_GPREL16},
14310 {"%gprel", BFD_RELOC_GPREL16},
14311 {"%half", BFD_RELOC_16},
14312 {"%highest", BFD_RELOC_MIPS_HIGHEST},
14313 {"%higher", BFD_RELOC_MIPS_HIGHER},
14314 {"%neg", BFD_RELOC_MIPS_SUB},
14315 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
14316 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
14317 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
14318 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
14319 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
14320 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
14321 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
14322 {"%hi", BFD_RELOC_HI16_S},
14323 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL},
14324 {"%pcrel_lo", BFD_RELOC_LO16_PCREL}
14327 static const struct percent_op_match mips16_percent_op[] =
14329 {"%lo", BFD_RELOC_MIPS16_LO16},
14330 {"%gp_rel", BFD_RELOC_MIPS16_GPREL},
14331 {"%gprel", BFD_RELOC_MIPS16_GPREL},
14332 {"%got", BFD_RELOC_MIPS16_GOT16},
14333 {"%call16", BFD_RELOC_MIPS16_CALL16},
14334 {"%hi", BFD_RELOC_MIPS16_HI16_S},
14335 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
14336 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
14337 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
14338 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
14339 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
14340 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
14341 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
14345 /* Return true if *STR points to a relocation operator. When returning true,
14346 move *STR over the operator and store its relocation code in *RELOC.
14347 Leave both *STR and *RELOC alone when returning false. */
14350 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
14352 const struct percent_op_match *percent_op;
14355 if (mips_opts.mips16)
14357 percent_op = mips16_percent_op;
14358 limit = ARRAY_SIZE (mips16_percent_op);
14362 percent_op = mips_percent_op;
14363 limit = ARRAY_SIZE (mips_percent_op);
14366 for (i = 0; i < limit; i++)
14367 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
14369 int len = strlen (percent_op[i].str);
14371 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
14374 *str += strlen (percent_op[i].str);
14375 *reloc = percent_op[i].reloc;
14377 /* Check whether the output BFD supports this relocation.
14378 If not, issue an error and fall back on something safe. */
14379 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
14381 as_bad (_("relocation %s isn't supported by the current ABI"),
14382 percent_op[i].str);
14383 *reloc = BFD_RELOC_UNUSED;
14391 /* Parse string STR as a 16-bit relocatable operand. Store the
14392 expression in *EP and the relocations in the array starting
14393 at RELOC. Return the number of relocation operators used.
14395 On exit, EXPR_END points to the first character after the expression. */
14398 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
14401 bfd_reloc_code_real_type reversed_reloc[3];
14402 size_t reloc_index, i;
14403 int crux_depth, str_depth;
14406 /* Search for the start of the main expression, recoding relocations
14407 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14408 of the main expression and with CRUX_DEPTH containing the number
14409 of open brackets at that point. */
14416 crux_depth = str_depth;
14418 /* Skip over whitespace and brackets, keeping count of the number
14420 while (*str == ' ' || *str == '\t' || *str == '(')
14425 && reloc_index < (HAVE_NEWABI ? 3 : 1)
14426 && parse_relocation (&str, &reversed_reloc[reloc_index]));
14428 my_getExpression (ep, crux);
14431 /* Match every open bracket. */
14432 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
14436 if (crux_depth > 0)
14437 as_bad (_("unclosed '('"));
14441 if (reloc_index != 0)
14443 prev_reloc_op_frag = frag_now;
14444 for (i = 0; i < reloc_index; i++)
14445 reloc[i] = reversed_reloc[reloc_index - 1 - i];
14448 return reloc_index;
14452 my_getExpression (expressionS *ep, char *str)
14456 save_in = input_line_pointer;
14457 input_line_pointer = str;
14459 expr_end = input_line_pointer;
14460 input_line_pointer = save_in;
14464 md_atof (int type, char *litP, int *sizeP)
14466 return ieee_md_atof (type, litP, sizeP, target_big_endian);
14470 md_number_to_chars (char *buf, valueT val, int n)
14472 if (target_big_endian)
14473 number_to_chars_bigendian (buf, val, n);
14475 number_to_chars_littleendian (buf, val, n);
14478 static int support_64bit_objects(void)
14480 const char **list, **l;
14483 list = bfd_target_list ();
14484 for (l = list; *l != NULL; l++)
14485 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
14486 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
14488 yes = (*l != NULL);
14493 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14494 NEW_VALUE. Warn if another value was already specified. Note:
14495 we have to defer parsing the -march and -mtune arguments in order
14496 to handle 'from-abi' correctly, since the ABI might be specified
14497 in a later argument. */
14500 mips_set_option_string (const char **string_ptr, const char *new_value)
14502 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
14503 as_warn (_("a different %s was already specified, is now %s"),
14504 string_ptr == &mips_arch_string ? "-march" : "-mtune",
14507 *string_ptr = new_value;
14511 md_parse_option (int c, const char *arg)
14515 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
14516 if (c == mips_ases[i].option_on || c == mips_ases[i].option_off)
14518 file_ase_explicit |= mips_set_ase (&mips_ases[i], &file_mips_opts,
14519 c == mips_ases[i].option_on);
14525 case OPTION_CONSTRUCT_FLOATS:
14526 mips_disable_float_construction = 0;
14529 case OPTION_NO_CONSTRUCT_FLOATS:
14530 mips_disable_float_construction = 1;
14542 target_big_endian = 1;
14546 target_big_endian = 0;
14552 else if (arg[0] == '0')
14554 else if (arg[0] == '1')
14564 mips_debug = atoi (arg);
14568 file_mips_opts.isa = ISA_MIPS1;
14572 file_mips_opts.isa = ISA_MIPS2;
14576 file_mips_opts.isa = ISA_MIPS3;
14580 file_mips_opts.isa = ISA_MIPS4;
14584 file_mips_opts.isa = ISA_MIPS5;
14587 case OPTION_MIPS32:
14588 file_mips_opts.isa = ISA_MIPS32;
14591 case OPTION_MIPS32R2:
14592 file_mips_opts.isa = ISA_MIPS32R2;
14595 case OPTION_MIPS32R3:
14596 file_mips_opts.isa = ISA_MIPS32R3;
14599 case OPTION_MIPS32R5:
14600 file_mips_opts.isa = ISA_MIPS32R5;
14603 case OPTION_MIPS32R6:
14604 file_mips_opts.isa = ISA_MIPS32R6;
14607 case OPTION_MIPS64R2:
14608 file_mips_opts.isa = ISA_MIPS64R2;
14611 case OPTION_MIPS64R3:
14612 file_mips_opts.isa = ISA_MIPS64R3;
14615 case OPTION_MIPS64R5:
14616 file_mips_opts.isa = ISA_MIPS64R5;
14619 case OPTION_MIPS64R6:
14620 file_mips_opts.isa = ISA_MIPS64R6;
14623 case OPTION_MIPS64:
14624 file_mips_opts.isa = ISA_MIPS64;
14628 mips_set_option_string (&mips_tune_string, arg);
14632 mips_set_option_string (&mips_arch_string, arg);
14636 mips_set_option_string (&mips_arch_string, "4650");
14637 mips_set_option_string (&mips_tune_string, "4650");
14640 case OPTION_NO_M4650:
14644 mips_set_option_string (&mips_arch_string, "4010");
14645 mips_set_option_string (&mips_tune_string, "4010");
14648 case OPTION_NO_M4010:
14652 mips_set_option_string (&mips_arch_string, "4100");
14653 mips_set_option_string (&mips_tune_string, "4100");
14656 case OPTION_NO_M4100:
14660 mips_set_option_string (&mips_arch_string, "3900");
14661 mips_set_option_string (&mips_tune_string, "3900");
14664 case OPTION_NO_M3900:
14667 case OPTION_MICROMIPS:
14668 if (file_mips_opts.mips16 == 1)
14670 as_bad (_("-mmicromips cannot be used with -mips16"));
14673 file_mips_opts.micromips = 1;
14674 mips_no_prev_insn ();
14677 case OPTION_NO_MICROMIPS:
14678 file_mips_opts.micromips = 0;
14679 mips_no_prev_insn ();
14682 case OPTION_MIPS16:
14683 if (file_mips_opts.micromips == 1)
14685 as_bad (_("-mips16 cannot be used with -micromips"));
14688 file_mips_opts.mips16 = 1;
14689 mips_no_prev_insn ();
14692 case OPTION_NO_MIPS16:
14693 file_mips_opts.mips16 = 0;
14694 mips_no_prev_insn ();
14697 case OPTION_FIX_24K:
14701 case OPTION_NO_FIX_24K:
14705 case OPTION_FIX_RM7000:
14706 mips_fix_rm7000 = 1;
14709 case OPTION_NO_FIX_RM7000:
14710 mips_fix_rm7000 = 0;
14713 case OPTION_FIX_LOONGSON2F_JUMP:
14714 mips_fix_loongson2f_jump = TRUE;
14717 case OPTION_NO_FIX_LOONGSON2F_JUMP:
14718 mips_fix_loongson2f_jump = FALSE;
14721 case OPTION_FIX_LOONGSON2F_NOP:
14722 mips_fix_loongson2f_nop = TRUE;
14725 case OPTION_NO_FIX_LOONGSON2F_NOP:
14726 mips_fix_loongson2f_nop = FALSE;
14729 case OPTION_FIX_VR4120:
14730 mips_fix_vr4120 = 1;
14733 case OPTION_NO_FIX_VR4120:
14734 mips_fix_vr4120 = 0;
14737 case OPTION_FIX_VR4130:
14738 mips_fix_vr4130 = 1;
14741 case OPTION_NO_FIX_VR4130:
14742 mips_fix_vr4130 = 0;
14745 case OPTION_FIX_CN63XXP1:
14746 mips_fix_cn63xxp1 = TRUE;
14749 case OPTION_NO_FIX_CN63XXP1:
14750 mips_fix_cn63xxp1 = FALSE;
14753 case OPTION_RELAX_BRANCH:
14754 mips_relax_branch = 1;
14757 case OPTION_NO_RELAX_BRANCH:
14758 mips_relax_branch = 0;
14761 case OPTION_IGNORE_BRANCH_ISA:
14762 mips_ignore_branch_isa = TRUE;
14765 case OPTION_NO_IGNORE_BRANCH_ISA:
14766 mips_ignore_branch_isa = FALSE;
14769 case OPTION_INSN32:
14770 file_mips_opts.insn32 = TRUE;
14773 case OPTION_NO_INSN32:
14774 file_mips_opts.insn32 = FALSE;
14777 case OPTION_MSHARED:
14778 mips_in_shared = TRUE;
14781 case OPTION_MNO_SHARED:
14782 mips_in_shared = FALSE;
14785 case OPTION_MSYM32:
14786 file_mips_opts.sym32 = TRUE;
14789 case OPTION_MNO_SYM32:
14790 file_mips_opts.sym32 = FALSE;
14793 /* When generating ELF code, we permit -KPIC and -call_shared to
14794 select SVR4_PIC, and -non_shared to select no PIC. This is
14795 intended to be compatible with Irix 5. */
14796 case OPTION_CALL_SHARED:
14797 mips_pic = SVR4_PIC;
14798 mips_abicalls = TRUE;
14801 case OPTION_CALL_NONPIC:
14803 mips_abicalls = TRUE;
14806 case OPTION_NON_SHARED:
14808 mips_abicalls = FALSE;
14811 /* The -xgot option tells the assembler to use 32 bit offsets
14812 when accessing the got in SVR4_PIC mode. It is for Irix
14819 g_switch_value = atoi (arg);
14823 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14826 mips_abi = O32_ABI;
14830 mips_abi = N32_ABI;
14834 mips_abi = N64_ABI;
14835 if (!support_64bit_objects())
14836 as_fatal (_("no compiled in support for 64 bit object file format"));
14840 file_mips_opts.gp = 32;
14844 file_mips_opts.gp = 64;
14848 file_mips_opts.fp = 32;
14852 file_mips_opts.fp = 0;
14856 file_mips_opts.fp = 64;
14859 case OPTION_ODD_SPREG:
14860 file_mips_opts.oddspreg = 1;
14863 case OPTION_NO_ODD_SPREG:
14864 file_mips_opts.oddspreg = 0;
14867 case OPTION_SINGLE_FLOAT:
14868 file_mips_opts.single_float = 1;
14871 case OPTION_DOUBLE_FLOAT:
14872 file_mips_opts.single_float = 0;
14875 case OPTION_SOFT_FLOAT:
14876 file_mips_opts.soft_float = 1;
14879 case OPTION_HARD_FLOAT:
14880 file_mips_opts.soft_float = 0;
14884 if (strcmp (arg, "32") == 0)
14885 mips_abi = O32_ABI;
14886 else if (strcmp (arg, "o64") == 0)
14887 mips_abi = O64_ABI;
14888 else if (strcmp (arg, "n32") == 0)
14889 mips_abi = N32_ABI;
14890 else if (strcmp (arg, "64") == 0)
14892 mips_abi = N64_ABI;
14893 if (! support_64bit_objects())
14894 as_fatal (_("no compiled in support for 64 bit object file "
14897 else if (strcmp (arg, "eabi") == 0)
14898 mips_abi = EABI_ABI;
14901 as_fatal (_("invalid abi -mabi=%s"), arg);
14906 case OPTION_M7000_HILO_FIX:
14907 mips_7000_hilo_fix = TRUE;
14910 case OPTION_MNO_7000_HILO_FIX:
14911 mips_7000_hilo_fix = FALSE;
14914 case OPTION_MDEBUG:
14915 mips_flag_mdebug = TRUE;
14918 case OPTION_NO_MDEBUG:
14919 mips_flag_mdebug = FALSE;
14923 mips_flag_pdr = TRUE;
14926 case OPTION_NO_PDR:
14927 mips_flag_pdr = FALSE;
14930 case OPTION_MVXWORKS_PIC:
14931 mips_pic = VXWORKS_PIC;
14935 if (strcmp (arg, "2008") == 0)
14937 else if (strcmp (arg, "legacy") == 0)
14941 as_fatal (_("invalid NaN setting -mnan=%s"), arg);
14950 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
14955 /* Set up globals to tune for the ISA or processor described by INFO. */
14958 mips_set_tune (const struct mips_cpu_info *info)
14961 mips_tune = info->cpu;
14966 mips_after_parse_args (void)
14968 const struct mips_cpu_info *arch_info = 0;
14969 const struct mips_cpu_info *tune_info = 0;
14971 /* GP relative stuff not working for PE */
14972 if (strncmp (TARGET_OS, "pe", 2) == 0)
14974 if (g_switch_seen && g_switch_value != 0)
14975 as_bad (_("-G not supported in this configuration"));
14976 g_switch_value = 0;
14979 if (mips_abi == NO_ABI)
14980 mips_abi = MIPS_DEFAULT_ABI;
14982 /* The following code determines the architecture.
14983 Similar code was added to GCC 3.3 (see override_options() in
14984 config/mips/mips.c). The GAS and GCC code should be kept in sync
14985 as much as possible. */
14987 if (mips_arch_string != 0)
14988 arch_info = mips_parse_cpu ("-march", mips_arch_string);
14990 if (file_mips_opts.isa != ISA_UNKNOWN)
14992 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
14993 ISA level specified by -mipsN, while arch_info->isa contains
14994 the -march selection (if any). */
14995 if (arch_info != 0)
14997 /* -march takes precedence over -mipsN, since it is more descriptive.
14998 There's no harm in specifying both as long as the ISA levels
15000 if (file_mips_opts.isa != arch_info->isa)
15001 as_bad (_("-%s conflicts with the other architecture options,"
15002 " which imply -%s"),
15003 mips_cpu_info_from_isa (file_mips_opts.isa)->name,
15004 mips_cpu_info_from_isa (arch_info->isa)->name);
15007 arch_info = mips_cpu_info_from_isa (file_mips_opts.isa);
15010 if (arch_info == 0)
15012 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
15013 gas_assert (arch_info);
15016 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
15017 as_bad (_("-march=%s is not compatible with the selected ABI"),
15020 file_mips_opts.arch = arch_info->cpu;
15021 file_mips_opts.isa = arch_info->isa;
15023 /* Set up initial mips_opts state. */
15024 mips_opts = file_mips_opts;
15026 /* The register size inference code is now placed in
15027 file_mips_check_options. */
15029 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
15031 if (mips_tune_string != 0)
15032 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
15034 if (tune_info == 0)
15035 mips_set_tune (arch_info);
15037 mips_set_tune (tune_info);
15039 if (mips_flag_mdebug < 0)
15040 mips_flag_mdebug = 0;
15044 mips_init_after_args (void)
15046 /* initialize opcodes */
15047 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
15048 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
15052 md_pcrel_from (fixS *fixP)
15054 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
15055 switch (fixP->fx_r_type)
15057 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15058 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15059 /* Return the address of the delay slot. */
15062 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15063 case BFD_RELOC_MICROMIPS_JMP:
15064 case BFD_RELOC_MIPS16_16_PCREL_S1:
15065 case BFD_RELOC_16_PCREL_S2:
15066 case BFD_RELOC_MIPS_21_PCREL_S2:
15067 case BFD_RELOC_MIPS_26_PCREL_S2:
15068 case BFD_RELOC_MIPS_JMP:
15069 /* Return the address of the delay slot. */
15072 case BFD_RELOC_MIPS_18_PCREL_S3:
15073 /* Return the aligned address of the doubleword containing
15074 the instruction. */
15082 /* This is called before the symbol table is processed. In order to
15083 work with gcc when using mips-tfile, we must keep all local labels.
15084 However, in other cases, we want to discard them. If we were
15085 called with -g, but we didn't see any debugging information, it may
15086 mean that gcc is smuggling debugging information through to
15087 mips-tfile, in which case we must generate all local labels. */
15090 mips_frob_file_before_adjust (void)
15092 #ifndef NO_ECOFF_DEBUGGING
15093 if (ECOFF_DEBUGGING
15095 && ! ecoff_debugging_seen)
15096 flag_keep_locals = 1;
15100 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15101 the corresponding LO16 reloc. This is called before md_apply_fix and
15102 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15103 relocation operators.
15105 For our purposes, a %lo() expression matches a %got() or %hi()
15108 (a) it refers to the same symbol; and
15109 (b) the offset applied in the %lo() expression is no lower than
15110 the offset applied in the %got() or %hi().
15112 (b) allows us to cope with code like:
15115 lh $4,%lo(foo+2)($4)
15117 ...which is legal on RELA targets, and has a well-defined behaviour
15118 if the user knows that adding 2 to "foo" will not induce a carry to
15121 When several %lo()s match a particular %got() or %hi(), we use the
15122 following rules to distinguish them:
15124 (1) %lo()s with smaller offsets are a better match than %lo()s with
15127 (2) %lo()s with no matching %got() or %hi() are better than those
15128 that already have a matching %got() or %hi().
15130 (3) later %lo()s are better than earlier %lo()s.
15132 These rules are applied in order.
15134 (1) means, among other things, that %lo()s with identical offsets are
15135 chosen if they exist.
15137 (2) means that we won't associate several high-part relocations with
15138 the same low-part relocation unless there's no alternative. Having
15139 several high parts for the same low part is a GNU extension; this rule
15140 allows careful users to avoid it.
15142 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15143 with the last high-part relocation being at the front of the list.
15144 It therefore makes sense to choose the last matching low-part
15145 relocation, all other things being equal. It's also easier
15146 to code that way. */
15149 mips_frob_file (void)
15151 struct mips_hi_fixup *l;
15152 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
15154 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
15156 segment_info_type *seginfo;
15157 bfd_boolean matched_lo_p;
15158 fixS **hi_pos, **lo_pos, **pos;
15160 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
15162 /* If a GOT16 relocation turns out to be against a global symbol,
15163 there isn't supposed to be a matching LO. Ignore %gots against
15164 constants; we'll report an error for those later. */
15165 if (got16_reloc_p (l->fixp->fx_r_type)
15166 && !(l->fixp->fx_addsy
15167 && pic_need_relax (l->fixp->fx_addsy)))
15170 /* Check quickly whether the next fixup happens to be a matching %lo. */
15171 if (fixup_has_matching_lo_p (l->fixp))
15174 seginfo = seg_info (l->seg);
15176 /* Set HI_POS to the position of this relocation in the chain.
15177 Set LO_POS to the position of the chosen low-part relocation.
15178 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15179 relocation that matches an immediately-preceding high-part
15183 matched_lo_p = FALSE;
15184 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
15186 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
15188 if (*pos == l->fixp)
15191 if ((*pos)->fx_r_type == looking_for_rtype
15192 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
15193 && (*pos)->fx_offset >= l->fixp->fx_offset
15195 || (*pos)->fx_offset < (*lo_pos)->fx_offset
15197 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
15200 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
15201 && fixup_has_matching_lo_p (*pos));
15204 /* If we found a match, remove the high-part relocation from its
15205 current position and insert it before the low-part relocation.
15206 Make the offsets match so that fixup_has_matching_lo_p()
15209 We don't warn about unmatched high-part relocations since some
15210 versions of gcc have been known to emit dead "lui ...%hi(...)"
15212 if (lo_pos != NULL)
15214 l->fixp->fx_offset = (*lo_pos)->fx_offset;
15215 if (l->fixp->fx_next != *lo_pos)
15217 *hi_pos = l->fixp->fx_next;
15218 l->fixp->fx_next = *lo_pos;
15226 mips_force_relocation (fixS *fixp)
15228 if (generic_force_reloc (fixp))
15231 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15232 so that the linker relaxation can update targets. */
15233 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15234 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15235 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
15238 /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2
15239 and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and
15240 microMIPS symbols so that we can do cross-mode branch diagnostics
15241 and BAL to JALX conversion by the linker. */
15242 if ((fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
15243 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
15244 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2)
15246 && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp->fx_addsy)))
15249 /* We want all PC-relative relocations to be kept for R6 relaxation. */
15250 if (ISA_IS_R6 (file_mips_opts.isa)
15251 && (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
15252 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
15253 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2
15254 || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3
15255 || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2
15256 || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL
15257 || fixp->fx_r_type == BFD_RELOC_LO16_PCREL))
15263 /* Implement TC_FORCE_RELOCATION_ABS. */
15266 mips_force_relocation_abs (fixS *fixp)
15268 if (generic_force_reloc (fixp))
15271 /* These relocations do not have enough bits in the in-place addend
15272 to hold an arbitrary absolute section's offset. */
15273 if (HAVE_IN_PLACE_ADDENDS && limited_pcrel_reloc_p (fixp->fx_r_type))
15279 /* Read the instruction associated with RELOC from BUF. */
15281 static unsigned int
15282 read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc)
15284 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
15285 return read_compressed_insn (buf, 4);
15287 return read_insn (buf);
15290 /* Write instruction INSN to BUF, given that it has been relocated
15294 write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc,
15295 unsigned long insn)
15297 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
15298 write_compressed_insn (buf, insn, 4);
15300 write_insn (buf, insn);
15303 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15304 to a symbol in another ISA mode, which cannot be converted to JALX. */
15307 fix_bad_cross_mode_jump_p (fixS *fixP)
15309 unsigned long opcode;
15313 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
15316 other = S_GET_OTHER (fixP->fx_addsy);
15317 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15318 opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26;
15319 switch (fixP->fx_r_type)
15321 case BFD_RELOC_MIPS_JMP:
15322 return opcode != 0x1d && opcode != 0x03 && ELF_ST_IS_COMPRESSED (other);
15323 case BFD_RELOC_MICROMIPS_JMP:
15324 return opcode != 0x3c && opcode != 0x3d && !ELF_ST_IS_MICROMIPS (other);
15330 /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX
15331 jump to a symbol in the same ISA mode. */
15334 fix_bad_same_mode_jalx_p (fixS *fixP)
15336 unsigned long opcode;
15340 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
15343 other = S_GET_OTHER (fixP->fx_addsy);
15344 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15345 opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26;
15346 switch (fixP->fx_r_type)
15348 case BFD_RELOC_MIPS_JMP:
15349 return opcode == 0x1d && !ELF_ST_IS_COMPRESSED (other);
15350 case BFD_RELOC_MIPS16_JMP:
15351 return opcode == 0x07 && ELF_ST_IS_COMPRESSED (other);
15352 case BFD_RELOC_MICROMIPS_JMP:
15353 return opcode == 0x3c && ELF_ST_IS_COMPRESSED (other);
15359 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15360 to a symbol whose value plus addend is not aligned according to the
15361 ultimate (after linker relaxation) jump instruction's immediate field
15362 requirement, either to (1 << SHIFT), or, for jumps from microMIPS to
15363 regular MIPS code, to (1 << 2). */
15366 fix_bad_misaligned_jump_p (fixS *fixP, int shift)
15368 bfd_boolean micro_to_mips_p;
15372 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
15375 other = S_GET_OTHER (fixP->fx_addsy);
15376 val = S_GET_VALUE (fixP->fx_addsy) | ELF_ST_IS_COMPRESSED (other);
15377 val += fixP->fx_offset;
15378 micro_to_mips_p = (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP
15379 && !ELF_ST_IS_MICROMIPS (other));
15380 return ((val & ((1 << (micro_to_mips_p ? 2 : shift)) - 1))
15381 != ELF_ST_IS_COMPRESSED (other));
15384 /* Return TRUE if the instruction pointed to by FIXP is an invalid branch
15385 to a symbol whose annotation indicates another ISA mode. For absolute
15386 symbols check the ISA bit instead.
15388 We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS
15389 symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular
15390 MIPS symbols and associated with BAL instructions as these instructions
15391 may be converted to JALX by the linker. */
15394 fix_bad_cross_mode_branch_p (fixS *fixP)
15396 bfd_boolean absolute_p;
15397 unsigned long opcode;
15403 if (mips_ignore_branch_isa)
15406 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
15409 symsec = S_GET_SEGMENT (fixP->fx_addsy);
15410 absolute_p = bfd_is_abs_section (symsec);
15412 val = S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset;
15413 other = S_GET_OTHER (fixP->fx_addsy);
15415 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15416 opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 16;
15417 switch (fixP->fx_r_type)
15419 case BFD_RELOC_16_PCREL_S2:
15420 return ((absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other))
15421 && opcode != 0x0411);
15422 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15423 return ((absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other))
15424 && opcode != 0x4060);
15425 case BFD_RELOC_MIPS_21_PCREL_S2:
15426 case BFD_RELOC_MIPS_26_PCREL_S2:
15427 return absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other);
15428 case BFD_RELOC_MIPS16_16_PCREL_S1:
15429 return absolute_p ? !(val & 1) : !ELF_ST_IS_MIPS16 (other);
15430 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15431 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15432 return absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other);
15438 /* Return TRUE if the symbol plus addend associated with a regular MIPS
15439 branch instruction pointed to by FIXP is not aligned according to the
15440 branch instruction's immediate field requirement. We need the addend
15441 to preserve the ISA bit and also the sum must not have bit 2 set. We
15442 must explicitly OR in the ISA bit from symbol annotation as the bit
15443 won't be set in the symbol's value then. */
15446 fix_bad_misaligned_branch_p (fixS *fixP)
15448 bfd_boolean absolute_p;
15455 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
15458 symsec = S_GET_SEGMENT (fixP->fx_addsy);
15459 absolute_p = bfd_is_abs_section (symsec);
15461 val = S_GET_VALUE (fixP->fx_addsy);
15462 other = S_GET_OTHER (fixP->fx_addsy);
15463 off = fixP->fx_offset;
15465 isa_bit = absolute_p ? (val + off) & 1 : ELF_ST_IS_COMPRESSED (other);
15466 val |= ELF_ST_IS_COMPRESSED (other);
15468 return (val & 0x3) != isa_bit;
15471 /* Make the necessary checks on a regular MIPS branch pointed to by FIXP
15472 and its calculated value VAL. */
15475 fix_validate_branch (fixS *fixP, valueT val)
15477 if (fixP->fx_done && (val & 0x3) != 0)
15478 as_bad_where (fixP->fx_file, fixP->fx_line,
15479 _("branch to misaligned address (0x%lx)"),
15480 (long) (val + md_pcrel_from (fixP)));
15481 else if (fix_bad_cross_mode_branch_p (fixP))
15482 as_bad_where (fixP->fx_file, fixP->fx_line,
15483 _("branch to a symbol in another ISA mode"));
15484 else if (fix_bad_misaligned_branch_p (fixP))
15485 as_bad_where (fixP->fx_file, fixP->fx_line,
15486 _("branch to misaligned address (0x%lx)"),
15487 (long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset));
15488 else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x3) != 0)
15489 as_bad_where (fixP->fx_file, fixP->fx_line,
15490 _("cannot encode misaligned addend "
15491 "in the relocatable field (0x%lx)"),
15492 (long) fixP->fx_offset);
15495 /* Apply a fixup to the object file. */
15498 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
15501 unsigned long insn;
15502 reloc_howto_type *howto;
15504 if (fixP->fx_pcrel)
15505 switch (fixP->fx_r_type)
15507 case BFD_RELOC_16_PCREL_S2:
15508 case BFD_RELOC_MIPS16_16_PCREL_S1:
15509 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15510 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15511 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15512 case BFD_RELOC_32_PCREL:
15513 case BFD_RELOC_MIPS_21_PCREL_S2:
15514 case BFD_RELOC_MIPS_26_PCREL_S2:
15515 case BFD_RELOC_MIPS_18_PCREL_S3:
15516 case BFD_RELOC_MIPS_19_PCREL_S2:
15517 case BFD_RELOC_HI16_S_PCREL:
15518 case BFD_RELOC_LO16_PCREL:
15522 fixP->fx_r_type = BFD_RELOC_32_PCREL;
15526 as_bad_where (fixP->fx_file, fixP->fx_line,
15527 _("PC-relative reference to a different section"));
15531 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
15532 that have no MIPS ELF equivalent. */
15533 if (fixP->fx_r_type != BFD_RELOC_8)
15535 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
15540 gas_assert (fixP->fx_size == 2
15541 || fixP->fx_size == 4
15542 || fixP->fx_r_type == BFD_RELOC_8
15543 || fixP->fx_r_type == BFD_RELOC_16
15544 || fixP->fx_r_type == BFD_RELOC_64
15545 || fixP->fx_r_type == BFD_RELOC_CTOR
15546 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
15547 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
15548 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
15549 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
15550 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64
15551 || fixP->fx_r_type == BFD_RELOC_NONE);
15553 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15555 /* Don't treat parts of a composite relocation as done. There are two
15558 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15559 should nevertheless be emitted if the first part is.
15561 (2) In normal usage, composite relocations are never assembly-time
15562 constants. The easiest way of dealing with the pathological
15563 exceptions is to generate a relocation against STN_UNDEF and
15564 leave everything up to the linker. */
15565 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
15568 switch (fixP->fx_r_type)
15570 case BFD_RELOC_MIPS_TLS_GD:
15571 case BFD_RELOC_MIPS_TLS_LDM:
15572 case BFD_RELOC_MIPS_TLS_DTPREL32:
15573 case BFD_RELOC_MIPS_TLS_DTPREL64:
15574 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
15575 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
15576 case BFD_RELOC_MIPS_TLS_GOTTPREL:
15577 case BFD_RELOC_MIPS_TLS_TPREL32:
15578 case BFD_RELOC_MIPS_TLS_TPREL64:
15579 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
15580 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
15581 case BFD_RELOC_MICROMIPS_TLS_GD:
15582 case BFD_RELOC_MICROMIPS_TLS_LDM:
15583 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
15584 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
15585 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
15586 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
15587 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
15588 case BFD_RELOC_MIPS16_TLS_GD:
15589 case BFD_RELOC_MIPS16_TLS_LDM:
15590 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
15591 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
15592 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
15593 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
15594 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
15595 if (fixP->fx_addsy)
15596 S_SET_THREAD_LOCAL (fixP->fx_addsy);
15598 as_bad_where (fixP->fx_file, fixP->fx_line,
15599 _("TLS relocation against a constant"));
15602 case BFD_RELOC_MIPS_JMP:
15603 case BFD_RELOC_MIPS16_JMP:
15604 case BFD_RELOC_MICROMIPS_JMP:
15608 gas_assert (!fixP->fx_done);
15610 /* Shift is 2, unusually, for microMIPS JALX. */
15611 if (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP
15612 && (read_compressed_insn (buf, 4) >> 26) != 0x3c)
15617 if (fix_bad_cross_mode_jump_p (fixP))
15618 as_bad_where (fixP->fx_file, fixP->fx_line,
15619 _("jump to a symbol in another ISA mode"));
15620 else if (fix_bad_same_mode_jalx_p (fixP))
15621 as_bad_where (fixP->fx_file, fixP->fx_line,
15622 _("JALX to a symbol in the same ISA mode"));
15623 else if (fix_bad_misaligned_jump_p (fixP, shift))
15624 as_bad_where (fixP->fx_file, fixP->fx_line,
15625 _("jump to misaligned address (0x%lx)"),
15626 (long) (S_GET_VALUE (fixP->fx_addsy)
15627 + fixP->fx_offset));
15628 else if (HAVE_IN_PLACE_ADDENDS
15629 && (fixP->fx_offset & ((1 << shift) - 1)) != 0)
15630 as_bad_where (fixP->fx_file, fixP->fx_line,
15631 _("cannot encode misaligned addend "
15632 "in the relocatable field (0x%lx)"),
15633 (long) fixP->fx_offset);
15635 /* Fall through. */
15637 case BFD_RELOC_MIPS_SHIFT5:
15638 case BFD_RELOC_MIPS_SHIFT6:
15639 case BFD_RELOC_MIPS_GOT_DISP:
15640 case BFD_RELOC_MIPS_GOT_PAGE:
15641 case BFD_RELOC_MIPS_GOT_OFST:
15642 case BFD_RELOC_MIPS_SUB:
15643 case BFD_RELOC_MIPS_INSERT_A:
15644 case BFD_RELOC_MIPS_INSERT_B:
15645 case BFD_RELOC_MIPS_DELETE:
15646 case BFD_RELOC_MIPS_HIGHEST:
15647 case BFD_RELOC_MIPS_HIGHER:
15648 case BFD_RELOC_MIPS_SCN_DISP:
15649 case BFD_RELOC_MIPS_REL16:
15650 case BFD_RELOC_MIPS_RELGOT:
15651 case BFD_RELOC_MIPS_JALR:
15652 case BFD_RELOC_HI16:
15653 case BFD_RELOC_HI16_S:
15654 case BFD_RELOC_LO16:
15655 case BFD_RELOC_GPREL16:
15656 case BFD_RELOC_MIPS_LITERAL:
15657 case BFD_RELOC_MIPS_CALL16:
15658 case BFD_RELOC_MIPS_GOT16:
15659 case BFD_RELOC_GPREL32:
15660 case BFD_RELOC_MIPS_GOT_HI16:
15661 case BFD_RELOC_MIPS_GOT_LO16:
15662 case BFD_RELOC_MIPS_CALL_HI16:
15663 case BFD_RELOC_MIPS_CALL_LO16:
15664 case BFD_RELOC_HI16_S_PCREL:
15665 case BFD_RELOC_LO16_PCREL:
15666 case BFD_RELOC_MIPS16_GPREL:
15667 case BFD_RELOC_MIPS16_GOT16:
15668 case BFD_RELOC_MIPS16_CALL16:
15669 case BFD_RELOC_MIPS16_HI16:
15670 case BFD_RELOC_MIPS16_HI16_S:
15671 case BFD_RELOC_MIPS16_LO16:
15672 case BFD_RELOC_MICROMIPS_GOT_DISP:
15673 case BFD_RELOC_MICROMIPS_GOT_PAGE:
15674 case BFD_RELOC_MICROMIPS_GOT_OFST:
15675 case BFD_RELOC_MICROMIPS_SUB:
15676 case BFD_RELOC_MICROMIPS_HIGHEST:
15677 case BFD_RELOC_MICROMIPS_HIGHER:
15678 case BFD_RELOC_MICROMIPS_SCN_DISP:
15679 case BFD_RELOC_MICROMIPS_JALR:
15680 case BFD_RELOC_MICROMIPS_HI16:
15681 case BFD_RELOC_MICROMIPS_HI16_S:
15682 case BFD_RELOC_MICROMIPS_LO16:
15683 case BFD_RELOC_MICROMIPS_GPREL16:
15684 case BFD_RELOC_MICROMIPS_LITERAL:
15685 case BFD_RELOC_MICROMIPS_CALL16:
15686 case BFD_RELOC_MICROMIPS_GOT16:
15687 case BFD_RELOC_MICROMIPS_GOT_HI16:
15688 case BFD_RELOC_MICROMIPS_GOT_LO16:
15689 case BFD_RELOC_MICROMIPS_CALL_HI16:
15690 case BFD_RELOC_MICROMIPS_CALL_LO16:
15691 case BFD_RELOC_MIPS_EH:
15696 if (calculate_reloc (fixP->fx_r_type, *valP, &value))
15698 insn = read_reloc_insn (buf, fixP->fx_r_type);
15699 if (mips16_reloc_p (fixP->fx_r_type))
15700 insn |= mips16_immed_extend (value, 16);
15702 insn |= (value & 0xffff);
15703 write_reloc_insn (buf, fixP->fx_r_type, insn);
15706 as_bad_where (fixP->fx_file, fixP->fx_line,
15707 _("unsupported constant in relocation"));
15712 /* This is handled like BFD_RELOC_32, but we output a sign
15713 extended value if we are only 32 bits. */
15716 if (8 <= sizeof (valueT))
15717 md_number_to_chars (buf, *valP, 8);
15722 if ((*valP & 0x80000000) != 0)
15726 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4);
15727 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4);
15732 case BFD_RELOC_RVA:
15734 case BFD_RELOC_32_PCREL:
15737 /* If we are deleting this reloc entry, we must fill in the
15738 value now. This can happen if we have a .word which is not
15739 resolved when it appears but is later defined. */
15741 md_number_to_chars (buf, *valP, fixP->fx_size);
15744 case BFD_RELOC_MIPS_21_PCREL_S2:
15745 fix_validate_branch (fixP, *valP);
15746 if (!fixP->fx_done)
15749 if (*valP + 0x400000 <= 0x7fffff)
15751 insn = read_insn (buf);
15752 insn |= (*valP >> 2) & 0x1fffff;
15753 write_insn (buf, insn);
15756 as_bad_where (fixP->fx_file, fixP->fx_line,
15757 _("branch out of range"));
15760 case BFD_RELOC_MIPS_26_PCREL_S2:
15761 fix_validate_branch (fixP, *valP);
15762 if (!fixP->fx_done)
15765 if (*valP + 0x8000000 <= 0xfffffff)
15767 insn = read_insn (buf);
15768 insn |= (*valP >> 2) & 0x3ffffff;
15769 write_insn (buf, insn);
15772 as_bad_where (fixP->fx_file, fixP->fx_line,
15773 _("branch out of range"));
15776 case BFD_RELOC_MIPS_18_PCREL_S3:
15777 if (fixP->fx_addsy && (S_GET_VALUE (fixP->fx_addsy) & 0x7) != 0)
15778 as_bad_where (fixP->fx_file, fixP->fx_line,
15779 _("PC-relative access using misaligned symbol (%lx)"),
15780 (long) S_GET_VALUE (fixP->fx_addsy));
15781 if ((fixP->fx_offset & 0x7) != 0)
15782 as_bad_where (fixP->fx_file, fixP->fx_line,
15783 _("PC-relative access using misaligned offset (%lx)"),
15784 (long) fixP->fx_offset);
15785 if (!fixP->fx_done)
15788 if (*valP + 0x100000 <= 0x1fffff)
15790 insn = read_insn (buf);
15791 insn |= (*valP >> 3) & 0x3ffff;
15792 write_insn (buf, insn);
15795 as_bad_where (fixP->fx_file, fixP->fx_line,
15796 _("PC-relative access out of range"));
15799 case BFD_RELOC_MIPS_19_PCREL_S2:
15800 if ((*valP & 0x3) != 0)
15801 as_bad_where (fixP->fx_file, fixP->fx_line,
15802 _("PC-relative access to misaligned address (%lx)"),
15804 if (!fixP->fx_done)
15807 if (*valP + 0x100000 <= 0x1fffff)
15809 insn = read_insn (buf);
15810 insn |= (*valP >> 2) & 0x7ffff;
15811 write_insn (buf, insn);
15814 as_bad_where (fixP->fx_file, fixP->fx_line,
15815 _("PC-relative access out of range"));
15818 case BFD_RELOC_16_PCREL_S2:
15819 fix_validate_branch (fixP, *valP);
15821 /* We need to save the bits in the instruction since fixup_segment()
15822 might be deleting the relocation entry (i.e., a branch within
15823 the current segment). */
15824 if (! fixP->fx_done)
15827 /* Update old instruction data. */
15828 insn = read_insn (buf);
15830 if (*valP + 0x20000 <= 0x3ffff)
15832 insn |= (*valP >> 2) & 0xffff;
15833 write_insn (buf, insn);
15835 else if (fixP->fx_tcbit2
15837 && fixP->fx_frag->fr_address >= text_section->vma
15838 && (fixP->fx_frag->fr_address
15839 < text_section->vma + bfd_get_section_size (text_section))
15840 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
15841 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
15842 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
15844 /* The branch offset is too large. If this is an
15845 unconditional branch, and we are not generating PIC code,
15846 we can convert it to an absolute jump instruction. */
15847 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
15848 insn = 0x0c000000; /* jal */
15850 insn = 0x08000000; /* j */
15851 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
15853 fixP->fx_addsy = section_symbol (text_section);
15854 *valP += md_pcrel_from (fixP);
15855 write_insn (buf, insn);
15859 /* If we got here, we have branch-relaxation disabled,
15860 and there's nothing we can do to fix this instruction
15861 without turning it into a longer sequence. */
15862 as_bad_where (fixP->fx_file, fixP->fx_line,
15863 _("branch out of range"));
15867 case BFD_RELOC_MIPS16_16_PCREL_S1:
15868 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15869 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15870 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15871 gas_assert (!fixP->fx_done);
15872 if (fix_bad_cross_mode_branch_p (fixP))
15873 as_bad_where (fixP->fx_file, fixP->fx_line,
15874 _("branch to a symbol in another ISA mode"));
15875 else if (fixP->fx_addsy
15876 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
15877 && !bfd_is_abs_section (S_GET_SEGMENT (fixP->fx_addsy))
15878 && (fixP->fx_offset & 0x1) != 0)
15879 as_bad_where (fixP->fx_file, fixP->fx_line,
15880 _("branch to misaligned address (0x%lx)"),
15881 (long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset));
15882 else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x1) != 0)
15883 as_bad_where (fixP->fx_file, fixP->fx_line,
15884 _("cannot encode misaligned addend "
15885 "in the relocatable field (0x%lx)"),
15886 (long) fixP->fx_offset);
15889 case BFD_RELOC_VTABLE_INHERIT:
15892 && !S_IS_DEFINED (fixP->fx_addsy)
15893 && !S_IS_WEAK (fixP->fx_addsy))
15894 S_SET_WEAK (fixP->fx_addsy);
15897 case BFD_RELOC_NONE:
15898 case BFD_RELOC_VTABLE_ENTRY:
15906 /* Remember value for tc_gen_reloc. */
15907 fixP->fx_addnumber = *valP;
15917 c = get_symbol_name (&name);
15918 p = (symbolS *) symbol_find_or_make (name);
15919 (void) restore_line_pointer (c);
15923 /* Align the current frag to a given power of two. If a particular
15924 fill byte should be used, FILL points to an integer that contains
15925 that byte, otherwise FILL is null.
15927 This function used to have the comment:
15929 The MIPS assembler also automatically adjusts any preceding label.
15931 The implementation therefore applied the adjustment to a maximum of
15932 one label. However, other label adjustments are applied to batches
15933 of labels, and adjusting just one caused problems when new labels
15934 were added for the sake of debugging or unwind information.
15935 We therefore adjust all preceding labels (given as LABELS) instead. */
15938 mips_align (int to, int *fill, struct insn_label_list *labels)
15940 mips_emit_delays ();
15941 mips_record_compressed_mode ();
15942 if (fill == NULL && subseg_text_p (now_seg))
15943 frag_align_code (to, 0);
15945 frag_align (to, fill ? *fill : 0, 0);
15946 record_alignment (now_seg, to);
15947 mips_move_labels (labels, FALSE);
15950 /* Align to a given power of two. .align 0 turns off the automatic
15951 alignment used by the data creating pseudo-ops. */
15954 s_align (int x ATTRIBUTE_UNUSED)
15956 int temp, fill_value, *fill_ptr;
15957 long max_alignment = 28;
15959 /* o Note that the assembler pulls down any immediately preceding label
15960 to the aligned address.
15961 o It's not documented but auto alignment is reinstated by
15962 a .align pseudo instruction.
15963 o Note also that after auto alignment is turned off the mips assembler
15964 issues an error on attempt to assemble an improperly aligned data item.
15967 temp = get_absolute_expression ();
15968 if (temp > max_alignment)
15969 as_bad (_("alignment too large, %d assumed"), temp = max_alignment);
15972 as_warn (_("alignment negative, 0 assumed"));
15975 if (*input_line_pointer == ',')
15977 ++input_line_pointer;
15978 fill_value = get_absolute_expression ();
15979 fill_ptr = &fill_value;
15985 segment_info_type *si = seg_info (now_seg);
15986 struct insn_label_list *l = si->label_list;
15987 /* Auto alignment should be switched on by next section change. */
15989 mips_align (temp, fill_ptr, l);
15996 demand_empty_rest_of_line ();
16000 s_change_sec (int sec)
16004 /* The ELF backend needs to know that we are changing sections, so
16005 that .previous works correctly. We could do something like check
16006 for an obj_section_change_hook macro, but that might be confusing
16007 as it would not be appropriate to use it in the section changing
16008 functions in read.c, since obj-elf.c intercepts those. FIXME:
16009 This should be cleaner, somehow. */
16010 obj_elf_section_change_hook ();
16012 mips_emit_delays ();
16023 subseg_set (bss_section, (subsegT) get_absolute_expression ());
16024 demand_empty_rest_of_line ();
16028 seg = subseg_new (RDATA_SECTION_NAME,
16029 (subsegT) get_absolute_expression ());
16030 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
16031 | SEC_READONLY | SEC_RELOC
16033 if (strncmp (TARGET_OS, "elf", 3) != 0)
16034 record_alignment (seg, 4);
16035 demand_empty_rest_of_line ();
16039 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
16040 bfd_set_section_flags (stdoutput, seg,
16041 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
16042 if (strncmp (TARGET_OS, "elf", 3) != 0)
16043 record_alignment (seg, 4);
16044 demand_empty_rest_of_line ();
16048 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
16049 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
16050 if (strncmp (TARGET_OS, "elf", 3) != 0)
16051 record_alignment (seg, 4);
16052 demand_empty_rest_of_line ();
16060 s_change_section (int ignore ATTRIBUTE_UNUSED)
16063 char *section_name;
16068 int section_entry_size;
16069 int section_alignment;
16071 saved_ilp = input_line_pointer;
16072 endc = get_symbol_name (§ion_name);
16073 c = (endc == '"' ? input_line_pointer[1] : endc);
16075 next_c = input_line_pointer [(endc == '"' ? 2 : 1)];
16077 /* Do we have .section Name<,"flags">? */
16078 if (c != ',' || (c == ',' && next_c == '"'))
16080 /* Just after name is now '\0'. */
16081 (void) restore_line_pointer (endc);
16082 input_line_pointer = saved_ilp;
16083 obj_elf_section (ignore);
16087 section_name = xstrdup (section_name);
16088 c = restore_line_pointer (endc);
16090 input_line_pointer++;
16092 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16094 section_type = get_absolute_expression ();
16098 if (*input_line_pointer++ == ',')
16099 section_flag = get_absolute_expression ();
16103 if (*input_line_pointer++ == ',')
16104 section_entry_size = get_absolute_expression ();
16106 section_entry_size = 0;
16108 if (*input_line_pointer++ == ',')
16109 section_alignment = get_absolute_expression ();
16111 section_alignment = 0;
16113 /* FIXME: really ignore? */
16114 (void) section_alignment;
16116 /* When using the generic form of .section (as implemented by obj-elf.c),
16117 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16118 traditionally had to fall back on the more common @progbits instead.
16120 There's nothing really harmful in this, since bfd will correct
16121 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16122 means that, for backwards compatibility, the special_section entries
16123 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16125 Even so, we shouldn't force users of the MIPS .section syntax to
16126 incorrectly label the sections as SHT_PROGBITS. The best compromise
16127 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16128 generic type-checking code. */
16129 if (section_type == SHT_MIPS_DWARF)
16130 section_type = SHT_PROGBITS;
16132 obj_elf_change_section (section_name, section_type, 0, section_flag,
16133 section_entry_size, 0, 0, 0);
16135 if (now_seg->name != section_name)
16136 free (section_name);
16140 mips_enable_auto_align (void)
16146 s_cons (int log_size)
16148 segment_info_type *si = seg_info (now_seg);
16149 struct insn_label_list *l = si->label_list;
16151 mips_emit_delays ();
16152 if (log_size > 0 && auto_align)
16153 mips_align (log_size, 0, l);
16154 cons (1 << log_size);
16155 mips_clear_insn_labels ();
16159 s_float_cons (int type)
16161 segment_info_type *si = seg_info (now_seg);
16162 struct insn_label_list *l = si->label_list;
16164 mips_emit_delays ();
16169 mips_align (3, 0, l);
16171 mips_align (2, 0, l);
16175 mips_clear_insn_labels ();
16178 /* Handle .globl. We need to override it because on Irix 5 you are
16181 where foo is an undefined symbol, to mean that foo should be
16182 considered to be the address of a function. */
16185 s_mips_globl (int x ATTRIBUTE_UNUSED)
16194 c = get_symbol_name (&name);
16195 symbolP = symbol_find_or_make (name);
16196 S_SET_EXTERNAL (symbolP);
16198 *input_line_pointer = c;
16199 SKIP_WHITESPACE_AFTER_NAME ();
16201 /* On Irix 5, every global symbol that is not explicitly labelled as
16202 being a function is apparently labelled as being an object. */
16205 if (!is_end_of_line[(unsigned char) *input_line_pointer]
16206 && (*input_line_pointer != ','))
16211 c = get_symbol_name (&secname);
16212 sec = bfd_get_section_by_name (stdoutput, secname);
16214 as_bad (_("%s: no such section"), secname);
16215 (void) restore_line_pointer (c);
16217 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
16218 flag = BSF_FUNCTION;
16221 symbol_get_bfdsym (symbolP)->flags |= flag;
16223 c = *input_line_pointer;
16226 input_line_pointer++;
16227 SKIP_WHITESPACE ();
16228 if (is_end_of_line[(unsigned char) *input_line_pointer])
16234 demand_empty_rest_of_line ();
16238 s_option (int x ATTRIBUTE_UNUSED)
16243 c = get_symbol_name (&opt);
16247 /* FIXME: What does this mean? */
16249 else if (strncmp (opt, "pic", 3) == 0 && ISDIGIT (opt[3]) && opt[4] == '\0')
16253 i = atoi (opt + 3);
16254 if (i != 0 && i != 2)
16255 as_bad (_(".option pic%d not supported"), i);
16256 else if (mips_pic == VXWORKS_PIC)
16257 as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i);
16262 mips_pic = SVR4_PIC;
16263 mips_abicalls = TRUE;
16266 if (mips_pic == SVR4_PIC)
16268 if (g_switch_seen && g_switch_value != 0)
16269 as_warn (_("-G may not be used with SVR4 PIC code"));
16270 g_switch_value = 0;
16271 bfd_set_gp_size (stdoutput, 0);
16275 as_warn (_("unrecognized option \"%s\""), opt);
16277 (void) restore_line_pointer (c);
16278 demand_empty_rest_of_line ();
16281 /* This structure is used to hold a stack of .set values. */
16283 struct mips_option_stack
16285 struct mips_option_stack *next;
16286 struct mips_set_options options;
16289 static struct mips_option_stack *mips_opts_stack;
16291 /* Return status for .set/.module option handling. */
16293 enum code_option_type
16295 /* Unrecognized option. */
16296 OPTION_TYPE_BAD = -1,
16298 /* Ordinary option. */
16299 OPTION_TYPE_NORMAL,
16301 /* ISA changing option. */
16305 /* Handle common .set/.module options. Return status indicating option
16308 static enum code_option_type
16309 parse_code_option (char * name)
16311 bfd_boolean isa_set = FALSE;
16312 const struct mips_ase *ase;
16314 if (strncmp (name, "at=", 3) == 0)
16316 char *s = name + 3;
16318 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
16319 as_bad (_("unrecognized register name `%s'"), s);
16321 else if (strcmp (name, "at") == 0)
16322 mips_opts.at = ATREG;
16323 else if (strcmp (name, "noat") == 0)
16324 mips_opts.at = ZERO;
16325 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
16326 mips_opts.nomove = 0;
16327 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
16328 mips_opts.nomove = 1;
16329 else if (strcmp (name, "bopt") == 0)
16330 mips_opts.nobopt = 0;
16331 else if (strcmp (name, "nobopt") == 0)
16332 mips_opts.nobopt = 1;
16333 else if (strcmp (name, "gp=32") == 0)
16335 else if (strcmp (name, "gp=64") == 0)
16337 else if (strcmp (name, "fp=32") == 0)
16339 else if (strcmp (name, "fp=xx") == 0)
16341 else if (strcmp (name, "fp=64") == 0)
16343 else if (strcmp (name, "softfloat") == 0)
16344 mips_opts.soft_float = 1;
16345 else if (strcmp (name, "hardfloat") == 0)
16346 mips_opts.soft_float = 0;
16347 else if (strcmp (name, "singlefloat") == 0)
16348 mips_opts.single_float = 1;
16349 else if (strcmp (name, "doublefloat") == 0)
16350 mips_opts.single_float = 0;
16351 else if (strcmp (name, "nooddspreg") == 0)
16352 mips_opts.oddspreg = 0;
16353 else if (strcmp (name, "oddspreg") == 0)
16354 mips_opts.oddspreg = 1;
16355 else if (strcmp (name, "mips16") == 0
16356 || strcmp (name, "MIPS-16") == 0)
16357 mips_opts.mips16 = 1;
16358 else if (strcmp (name, "nomips16") == 0
16359 || strcmp (name, "noMIPS-16") == 0)
16360 mips_opts.mips16 = 0;
16361 else if (strcmp (name, "micromips") == 0)
16362 mips_opts.micromips = 1;
16363 else if (strcmp (name, "nomicromips") == 0)
16364 mips_opts.micromips = 0;
16365 else if (name[0] == 'n'
16367 && (ase = mips_lookup_ase (name + 2)))
16368 mips_set_ase (ase, &mips_opts, FALSE);
16369 else if ((ase = mips_lookup_ase (name)))
16370 mips_set_ase (ase, &mips_opts, TRUE);
16371 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
16373 /* Permit the user to change the ISA and architecture on the fly.
16374 Needless to say, misuse can cause serious problems. */
16375 if (strncmp (name, "arch=", 5) == 0)
16377 const struct mips_cpu_info *p;
16379 p = mips_parse_cpu ("internal use", name + 5);
16381 as_bad (_("unknown architecture %s"), name + 5);
16384 mips_opts.arch = p->cpu;
16385 mips_opts.isa = p->isa;
16389 else if (strncmp (name, "mips", 4) == 0)
16391 const struct mips_cpu_info *p;
16393 p = mips_parse_cpu ("internal use", name);
16395 as_bad (_("unknown ISA level %s"), name + 4);
16398 mips_opts.arch = p->cpu;
16399 mips_opts.isa = p->isa;
16404 as_bad (_("unknown ISA or architecture %s"), name);
16406 else if (strcmp (name, "autoextend") == 0)
16407 mips_opts.noautoextend = 0;
16408 else if (strcmp (name, "noautoextend") == 0)
16409 mips_opts.noautoextend = 1;
16410 else if (strcmp (name, "insn32") == 0)
16411 mips_opts.insn32 = TRUE;
16412 else if (strcmp (name, "noinsn32") == 0)
16413 mips_opts.insn32 = FALSE;
16414 else if (strcmp (name, "sym32") == 0)
16415 mips_opts.sym32 = TRUE;
16416 else if (strcmp (name, "nosym32") == 0)
16417 mips_opts.sym32 = FALSE;
16419 return OPTION_TYPE_BAD;
16421 return isa_set ? OPTION_TYPE_ISA : OPTION_TYPE_NORMAL;
16424 /* Handle the .set pseudo-op. */
16427 s_mipsset (int x ATTRIBUTE_UNUSED)
16429 enum code_option_type type = OPTION_TYPE_NORMAL;
16430 char *name = input_line_pointer, ch;
16432 file_mips_check_options ();
16434 while (!is_end_of_line[(unsigned char) *input_line_pointer])
16435 ++input_line_pointer;
16436 ch = *input_line_pointer;
16437 *input_line_pointer = '\0';
16439 if (strchr (name, ','))
16441 /* Generic ".set" directive; use the generic handler. */
16442 *input_line_pointer = ch;
16443 input_line_pointer = name;
16448 if (strcmp (name, "reorder") == 0)
16450 if (mips_opts.noreorder)
16453 else if (strcmp (name, "noreorder") == 0)
16455 if (!mips_opts.noreorder)
16456 start_noreorder ();
16458 else if (strcmp (name, "macro") == 0)
16459 mips_opts.warn_about_macros = 0;
16460 else if (strcmp (name, "nomacro") == 0)
16462 if (mips_opts.noreorder == 0)
16463 as_bad (_("`noreorder' must be set before `nomacro'"));
16464 mips_opts.warn_about_macros = 1;
16466 else if (strcmp (name, "gp=default") == 0)
16467 mips_opts.gp = file_mips_opts.gp;
16468 else if (strcmp (name, "fp=default") == 0)
16469 mips_opts.fp = file_mips_opts.fp;
16470 else if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
16472 mips_opts.isa = file_mips_opts.isa;
16473 mips_opts.arch = file_mips_opts.arch;
16474 mips_opts.gp = file_mips_opts.gp;
16475 mips_opts.fp = file_mips_opts.fp;
16477 else if (strcmp (name, "push") == 0)
16479 struct mips_option_stack *s;
16481 s = XNEW (struct mips_option_stack);
16482 s->next = mips_opts_stack;
16483 s->options = mips_opts;
16484 mips_opts_stack = s;
16486 else if (strcmp (name, "pop") == 0)
16488 struct mips_option_stack *s;
16490 s = mips_opts_stack;
16492 as_bad (_(".set pop with no .set push"));
16495 /* If we're changing the reorder mode we need to handle
16496 delay slots correctly. */
16497 if (s->options.noreorder && ! mips_opts.noreorder)
16498 start_noreorder ();
16499 else if (! s->options.noreorder && mips_opts.noreorder)
16502 mips_opts = s->options;
16503 mips_opts_stack = s->next;
16509 type = parse_code_option (name);
16510 if (type == OPTION_TYPE_BAD)
16511 as_warn (_("tried to set unrecognized symbol: %s\n"), name);
16514 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
16515 registers based on what is supported by the arch/cpu. */
16516 if (type == OPTION_TYPE_ISA)
16518 switch (mips_opts.isa)
16523 /* MIPS I cannot support FPXX. */
16525 /* fall-through. */
16532 if (mips_opts.fp != 0)
16548 if (mips_opts.fp != 0)
16550 if (mips_opts.arch == CPU_R5900)
16557 as_bad (_("unknown ISA level %s"), name + 4);
16562 mips_check_options (&mips_opts, FALSE);
16564 mips_check_isa_supports_ases ();
16565 *input_line_pointer = ch;
16566 demand_empty_rest_of_line ();
16569 /* Handle the .module pseudo-op. */
16572 s_module (int ignore ATTRIBUTE_UNUSED)
16574 char *name = input_line_pointer, ch;
16576 while (!is_end_of_line[(unsigned char) *input_line_pointer])
16577 ++input_line_pointer;
16578 ch = *input_line_pointer;
16579 *input_line_pointer = '\0';
16581 if (!file_mips_opts_checked)
16583 if (parse_code_option (name) == OPTION_TYPE_BAD)
16584 as_bad (_(".module used with unrecognized symbol: %s\n"), name);
16586 /* Update module level settings from mips_opts. */
16587 file_mips_opts = mips_opts;
16590 as_bad (_(".module is not permitted after generating code"));
16592 *input_line_pointer = ch;
16593 demand_empty_rest_of_line ();
16596 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16597 .option pic2. It means to generate SVR4 PIC calls. */
16600 s_abicalls (int ignore ATTRIBUTE_UNUSED)
16602 mips_pic = SVR4_PIC;
16603 mips_abicalls = TRUE;
16605 if (g_switch_seen && g_switch_value != 0)
16606 as_warn (_("-G may not be used with SVR4 PIC code"));
16607 g_switch_value = 0;
16609 bfd_set_gp_size (stdoutput, 0);
16610 demand_empty_rest_of_line ();
16613 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16614 PIC code. It sets the $gp register for the function based on the
16615 function address, which is in the register named in the argument.
16616 This uses a relocation against _gp_disp, which is handled specially
16617 by the linker. The result is:
16618 lui $gp,%hi(_gp_disp)
16619 addiu $gp,$gp,%lo(_gp_disp)
16620 addu $gp,$gp,.cpload argument
16621 The .cpload argument is normally $25 == $t9.
16623 The -mno-shared option changes this to:
16624 lui $gp,%hi(__gnu_local_gp)
16625 addiu $gp,$gp,%lo(__gnu_local_gp)
16626 and the argument is ignored. This saves an instruction, but the
16627 resulting code is not position independent; it uses an absolute
16628 address for __gnu_local_gp. Thus code assembled with -mno-shared
16629 can go into an ordinary executable, but not into a shared library. */
16632 s_cpload (int ignore ATTRIBUTE_UNUSED)
16638 file_mips_check_options ();
16640 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16641 .cpload is ignored. */
16642 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16648 if (mips_opts.mips16)
16650 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16651 ignore_rest_of_line ();
16655 /* .cpload should be in a .set noreorder section. */
16656 if (mips_opts.noreorder == 0)
16657 as_warn (_(".cpload not in noreorder section"));
16659 reg = tc_get_register (0);
16661 /* If we need to produce a 64-bit address, we are better off using
16662 the default instruction sequence. */
16663 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
16665 ex.X_op = O_symbol;
16666 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
16668 ex.X_op_symbol = NULL;
16669 ex.X_add_number = 0;
16671 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16672 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16674 mips_mark_labels ();
16675 mips_assembling_insn = TRUE;
16678 macro_build_lui (&ex, mips_gp_register);
16679 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16680 mips_gp_register, BFD_RELOC_LO16);
16682 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
16683 mips_gp_register, reg);
16686 mips_assembling_insn = FALSE;
16687 demand_empty_rest_of_line ();
16690 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16691 .cpsetup $reg1, offset|$reg2, label
16693 If offset is given, this results in:
16694 sd $gp, offset($sp)
16695 lui $gp, %hi(%neg(%gp_rel(label)))
16696 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16697 daddu $gp, $gp, $reg1
16699 If $reg2 is given, this results in:
16701 lui $gp, %hi(%neg(%gp_rel(label)))
16702 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16703 daddu $gp, $gp, $reg1
16704 $reg1 is normally $25 == $t9.
16706 The -mno-shared option replaces the last three instructions with
16708 addiu $gp,$gp,%lo(_gp) */
16711 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
16713 expressionS ex_off;
16714 expressionS ex_sym;
16717 file_mips_check_options ();
16719 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16720 We also need NewABI support. */
16721 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16727 if (mips_opts.mips16)
16729 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16730 ignore_rest_of_line ();
16734 reg1 = tc_get_register (0);
16735 SKIP_WHITESPACE ();
16736 if (*input_line_pointer != ',')
16738 as_bad (_("missing argument separator ',' for .cpsetup"));
16742 ++input_line_pointer;
16743 SKIP_WHITESPACE ();
16744 if (*input_line_pointer == '$')
16746 mips_cpreturn_register = tc_get_register (0);
16747 mips_cpreturn_offset = -1;
16751 mips_cpreturn_offset = get_absolute_expression ();
16752 mips_cpreturn_register = -1;
16754 SKIP_WHITESPACE ();
16755 if (*input_line_pointer != ',')
16757 as_bad (_("missing argument separator ',' for .cpsetup"));
16761 ++input_line_pointer;
16762 SKIP_WHITESPACE ();
16763 expression (&ex_sym);
16765 mips_mark_labels ();
16766 mips_assembling_insn = TRUE;
16769 if (mips_cpreturn_register == -1)
16771 ex_off.X_op = O_constant;
16772 ex_off.X_add_symbol = NULL;
16773 ex_off.X_op_symbol = NULL;
16774 ex_off.X_add_number = mips_cpreturn_offset;
16776 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
16777 BFD_RELOC_LO16, SP);
16780 move_register (mips_cpreturn_register, mips_gp_register);
16782 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
16784 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
16785 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
16788 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
16789 mips_gp_register, -1, BFD_RELOC_GPREL16,
16790 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
16792 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
16793 mips_gp_register, reg1);
16799 ex.X_op = O_symbol;
16800 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
16801 ex.X_op_symbol = NULL;
16802 ex.X_add_number = 0;
16804 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16805 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16807 macro_build_lui (&ex, mips_gp_register);
16808 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16809 mips_gp_register, BFD_RELOC_LO16);
16814 mips_assembling_insn = FALSE;
16815 demand_empty_rest_of_line ();
16819 s_cplocal (int ignore ATTRIBUTE_UNUSED)
16821 file_mips_check_options ();
16823 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16824 .cplocal is ignored. */
16825 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16831 if (mips_opts.mips16)
16833 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16834 ignore_rest_of_line ();
16838 mips_gp_register = tc_get_register (0);
16839 demand_empty_rest_of_line ();
16842 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16843 offset from $sp. The offset is remembered, and after making a PIC
16844 call $gp is restored from that location. */
16847 s_cprestore (int ignore ATTRIBUTE_UNUSED)
16851 file_mips_check_options ();
16853 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16854 .cprestore is ignored. */
16855 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16861 if (mips_opts.mips16)
16863 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16864 ignore_rest_of_line ();
16868 mips_cprestore_offset = get_absolute_expression ();
16869 mips_cprestore_valid = 1;
16871 ex.X_op = O_constant;
16872 ex.X_add_symbol = NULL;
16873 ex.X_op_symbol = NULL;
16874 ex.X_add_number = mips_cprestore_offset;
16876 mips_mark_labels ();
16877 mips_assembling_insn = TRUE;
16880 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
16881 SP, HAVE_64BIT_ADDRESSES);
16884 mips_assembling_insn = FALSE;
16885 demand_empty_rest_of_line ();
16888 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16889 was given in the preceding .cpsetup, it results in:
16890 ld $gp, offset($sp)
16892 If a register $reg2 was given there, it results in:
16893 or $gp, $reg2, $0 */
16896 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
16900 file_mips_check_options ();
16902 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16903 We also need NewABI support. */
16904 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16910 if (mips_opts.mips16)
16912 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16913 ignore_rest_of_line ();
16917 mips_mark_labels ();
16918 mips_assembling_insn = TRUE;
16921 if (mips_cpreturn_register == -1)
16923 ex.X_op = O_constant;
16924 ex.X_add_symbol = NULL;
16925 ex.X_op_symbol = NULL;
16926 ex.X_add_number = mips_cpreturn_offset;
16928 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
16931 move_register (mips_gp_register, mips_cpreturn_register);
16935 mips_assembling_insn = FALSE;
16936 demand_empty_rest_of_line ();
16939 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16940 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16941 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16942 debug information or MIPS16 TLS. */
16945 s_tls_rel_directive (const size_t bytes, const char *dirstr,
16946 bfd_reloc_code_real_type rtype)
16953 if (ex.X_op != O_symbol)
16955 as_bad (_("unsupported use of %s"), dirstr);
16956 ignore_rest_of_line ();
16959 p = frag_more (bytes);
16960 md_number_to_chars (p, 0, bytes);
16961 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
16962 demand_empty_rest_of_line ();
16963 mips_clear_insn_labels ();
16966 /* Handle .dtprelword. */
16969 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
16971 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
16974 /* Handle .dtpreldword. */
16977 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
16979 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
16982 /* Handle .tprelword. */
16985 s_tprelword (int ignore ATTRIBUTE_UNUSED)
16987 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
16990 /* Handle .tpreldword. */
16993 s_tpreldword (int ignore ATTRIBUTE_UNUSED)
16995 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
16998 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16999 code. It sets the offset to use in gp_rel relocations. */
17002 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
17004 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
17005 We also need NewABI support. */
17006 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
17012 mips_gprel_offset = get_absolute_expression ();
17014 demand_empty_rest_of_line ();
17017 /* Handle the .gpword pseudo-op. This is used when generating PIC
17018 code. It generates a 32 bit GP relative reloc. */
17021 s_gpword (int ignore ATTRIBUTE_UNUSED)
17023 segment_info_type *si;
17024 struct insn_label_list *l;
17028 /* When not generating PIC code, this is treated as .word. */
17029 if (mips_pic != SVR4_PIC)
17035 si = seg_info (now_seg);
17036 l = si->label_list;
17037 mips_emit_delays ();
17039 mips_align (2, 0, l);
17042 mips_clear_insn_labels ();
17044 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17046 as_bad (_("unsupported use of .gpword"));
17047 ignore_rest_of_line ();
17051 md_number_to_chars (p, 0, 4);
17052 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17053 BFD_RELOC_GPREL32);
17055 demand_empty_rest_of_line ();
17059 s_gpdword (int ignore ATTRIBUTE_UNUSED)
17061 segment_info_type *si;
17062 struct insn_label_list *l;
17066 /* When not generating PIC code, this is treated as .dword. */
17067 if (mips_pic != SVR4_PIC)
17073 si = seg_info (now_seg);
17074 l = si->label_list;
17075 mips_emit_delays ();
17077 mips_align (3, 0, l);
17080 mips_clear_insn_labels ();
17082 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17084 as_bad (_("unsupported use of .gpdword"));
17085 ignore_rest_of_line ();
17089 md_number_to_chars (p, 0, 8);
17090 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17091 BFD_RELOC_GPREL32)->fx_tcbit = 1;
17093 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17094 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
17095 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
17097 demand_empty_rest_of_line ();
17100 /* Handle the .ehword pseudo-op. This is used when generating unwinding
17101 tables. It generates a R_MIPS_EH reloc. */
17104 s_ehword (int ignore ATTRIBUTE_UNUSED)
17109 mips_emit_delays ();
17112 mips_clear_insn_labels ();
17114 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17116 as_bad (_("unsupported use of .ehword"));
17117 ignore_rest_of_line ();
17121 md_number_to_chars (p, 0, 4);
17122 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17123 BFD_RELOC_32_PCREL);
17125 demand_empty_rest_of_line ();
17128 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17129 tables in SVR4 PIC code. */
17132 s_cpadd (int ignore ATTRIBUTE_UNUSED)
17136 file_mips_check_options ();
17138 /* This is ignored when not generating SVR4 PIC code. */
17139 if (mips_pic != SVR4_PIC)
17145 mips_mark_labels ();
17146 mips_assembling_insn = TRUE;
17148 /* Add $gp to the register named as an argument. */
17150 reg = tc_get_register (0);
17151 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
17154 mips_assembling_insn = FALSE;
17155 demand_empty_rest_of_line ();
17158 /* Handle the .insn pseudo-op. This marks instruction labels in
17159 mips16/micromips mode. This permits the linker to handle them specially,
17160 such as generating jalx instructions when needed. We also make
17161 them odd for the duration of the assembly, in order to generate the
17162 right sort of code. We will make them even in the adjust_symtab
17163 routine, while leaving them marked. This is convenient for the
17164 debugger and the disassembler. The linker knows to make them odd
17168 s_insn (int ignore ATTRIBUTE_UNUSED)
17170 file_mips_check_options ();
17171 file_ase_mips16 |= mips_opts.mips16;
17172 file_ase_micromips |= mips_opts.micromips;
17174 mips_mark_labels ();
17176 demand_empty_rest_of_line ();
17179 /* Handle the .nan pseudo-op. */
17182 s_nan (int ignore ATTRIBUTE_UNUSED)
17184 static const char str_legacy[] = "legacy";
17185 static const char str_2008[] = "2008";
17188 for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++);
17190 if (i == sizeof (str_2008) - 1
17191 && memcmp (input_line_pointer, str_2008, i) == 0)
17193 else if (i == sizeof (str_legacy) - 1
17194 && memcmp (input_line_pointer, str_legacy, i) == 0)
17196 if (ISA_HAS_LEGACY_NAN (file_mips_opts.isa))
17199 as_bad (_("`%s' does not support legacy NaN"),
17200 mips_cpu_info_from_isa (file_mips_opts.isa)->name);
17203 as_bad (_("bad .nan directive"));
17205 input_line_pointer += i;
17206 demand_empty_rest_of_line ();
17209 /* Handle a .stab[snd] directive. Ideally these directives would be
17210 implemented in a transparent way, so that removing them would not
17211 have any effect on the generated instructions. However, s_stab
17212 internally changes the section, so in practice we need to decide
17213 now whether the preceding label marks compressed code. We do not
17214 support changing the compression mode of a label after a .stab*
17215 directive, such as in:
17221 so the current mode wins. */
17224 s_mips_stab (int type)
17226 file_mips_check_options ();
17227 mips_mark_labels ();
17231 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17234 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
17241 c = get_symbol_name (&name);
17242 symbolP = symbol_find_or_make (name);
17243 S_SET_WEAK (symbolP);
17244 *input_line_pointer = c;
17246 SKIP_WHITESPACE_AFTER_NAME ();
17248 if (! is_end_of_line[(unsigned char) *input_line_pointer])
17250 if (S_IS_DEFINED (symbolP))
17252 as_bad (_("ignoring attempt to redefine symbol %s"),
17253 S_GET_NAME (symbolP));
17254 ignore_rest_of_line ();
17258 if (*input_line_pointer == ',')
17260 ++input_line_pointer;
17261 SKIP_WHITESPACE ();
17265 if (exp.X_op != O_symbol)
17267 as_bad (_("bad .weakext directive"));
17268 ignore_rest_of_line ();
17271 symbol_set_value_expression (symbolP, &exp);
17274 demand_empty_rest_of_line ();
17277 /* Parse a register string into a number. Called from the ECOFF code
17278 to parse .frame. The argument is non-zero if this is the frame
17279 register, so that we can record it in mips_frame_reg. */
17282 tc_get_register (int frame)
17286 SKIP_WHITESPACE ();
17287 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
17291 mips_frame_reg = reg != 0 ? reg : SP;
17292 mips_frame_reg_valid = 1;
17293 mips_cprestore_valid = 0;
17299 md_section_align (asection *seg, valueT addr)
17301 int align = bfd_get_section_alignment (stdoutput, seg);
17303 /* We don't need to align ELF sections to the full alignment.
17304 However, Irix 5 may prefer that we align them at least to a 16
17305 byte boundary. We don't bother to align the sections if we
17306 are targeted for an embedded system. */
17307 if (strncmp (TARGET_OS, "elf", 3) == 0)
17312 return ((addr + (1 << align) - 1) & -(1 << align));
17315 /* Utility routine, called from above as well. If called while the
17316 input file is still being read, it's only an approximation. (For
17317 example, a symbol may later become defined which appeared to be
17318 undefined earlier.) */
17321 nopic_need_relax (symbolS *sym, int before_relaxing)
17326 if (g_switch_value > 0)
17328 const char *symname;
17331 /* Find out whether this symbol can be referenced off the $gp
17332 register. It can be if it is smaller than the -G size or if
17333 it is in the .sdata or .sbss section. Certain symbols can
17334 not be referenced off the $gp, although it appears as though
17336 symname = S_GET_NAME (sym);
17337 if (symname != (const char *) NULL
17338 && (strcmp (symname, "eprol") == 0
17339 || strcmp (symname, "etext") == 0
17340 || strcmp (symname, "_gp") == 0
17341 || strcmp (symname, "edata") == 0
17342 || strcmp (symname, "_fbss") == 0
17343 || strcmp (symname, "_fdata") == 0
17344 || strcmp (symname, "_ftext") == 0
17345 || strcmp (symname, "end") == 0
17346 || strcmp (symname, "_gp_disp") == 0))
17348 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
17350 #ifndef NO_ECOFF_DEBUGGING
17351 || (symbol_get_obj (sym)->ecoff_extern_size != 0
17352 && (symbol_get_obj (sym)->ecoff_extern_size
17353 <= g_switch_value))
17355 /* We must defer this decision until after the whole
17356 file has been read, since there might be a .extern
17357 after the first use of this symbol. */
17358 || (before_relaxing
17359 #ifndef NO_ECOFF_DEBUGGING
17360 && symbol_get_obj (sym)->ecoff_extern_size == 0
17362 && S_GET_VALUE (sym) == 0)
17363 || (S_GET_VALUE (sym) != 0
17364 && S_GET_VALUE (sym) <= g_switch_value)))
17368 const char *segname;
17370 segname = segment_name (S_GET_SEGMENT (sym));
17371 gas_assert (strcmp (segname, ".lit8") != 0
17372 && strcmp (segname, ".lit4") != 0);
17373 change = (strcmp (segname, ".sdata") != 0
17374 && strcmp (segname, ".sbss") != 0
17375 && strncmp (segname, ".sdata.", 7) != 0
17376 && strncmp (segname, ".sbss.", 6) != 0
17377 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
17378 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
17383 /* We are not optimizing for the $gp register. */
17388 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17391 pic_need_relax (symbolS *sym)
17395 /* Handle the case of a symbol equated to another symbol. */
17396 while (symbol_equated_reloc_p (sym))
17400 /* It's possible to get a loop here in a badly written program. */
17401 n = symbol_get_value_expression (sym)->X_add_symbol;
17407 if (symbol_section_p (sym))
17410 symsec = S_GET_SEGMENT (sym);
17412 /* This must duplicate the test in adjust_reloc_syms. */
17413 return (!bfd_is_und_section (symsec)
17414 && !bfd_is_abs_section (symsec)
17415 && !bfd_is_com_section (symsec)
17416 /* A global or weak symbol is treated as external. */
17417 && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym)));
17420 /* Given a MIPS16 variant frag FRAGP and PC-relative operand PCREL_OP
17421 convert a section-relative value VAL to the equivalent PC-relative
17425 mips16_pcrel_val (fragS *fragp, const struct mips_pcrel_operand *pcrel_op,
17426 offsetT val, long stretch)
17431 gas_assert (pcrel_op->root.root.type == OP_PCREL);
17433 sym_frag = symbol_get_frag (fragp->fr_symbol);
17435 /* If the relax_marker of the symbol fragment differs from the
17436 relax_marker of this fragment, we have not yet adjusted the
17437 symbol fragment fr_address. We want to add in STRETCH in
17438 order to get a better estimate of the address. This
17439 particularly matters because of the shift bits. */
17440 if (stretch != 0 && sym_frag->relax_marker != fragp->relax_marker)
17444 /* Adjust stretch for any alignment frag. Note that if have
17445 been expanding the earlier code, the symbol may be
17446 defined in what appears to be an earlier frag. FIXME:
17447 This doesn't handle the fr_subtype field, which specifies
17448 a maximum number of bytes to skip when doing an
17450 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
17452 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
17455 stretch = -(-stretch & ~((1 << (int) f->fr_offset) - 1));
17457 stretch &= ~((1 << (int) f->fr_offset) - 1);
17466 addr = fragp->fr_address + fragp->fr_fix;
17468 /* The base address rules are complicated. The base address of
17469 a branch is the following instruction. The base address of a
17470 PC relative load or add is the instruction itself, but if it
17471 is in a delay slot (in which case it can not be extended) use
17472 the address of the instruction whose delay slot it is in. */
17473 if (pcrel_op->include_isa_bit)
17477 /* If we are currently assuming that this frag should be
17478 extended, then the current address is two bytes higher. */
17479 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17482 /* Ignore the low bit in the target, since it will be set
17483 for a text label. */
17486 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17488 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17491 val -= addr & -(1 << pcrel_op->align_log2);
17496 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17497 extended opcode. SEC is the section the frag is in. */
17500 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
17502 const struct mips_int_operand *operand;
17507 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
17509 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17512 symsec = S_GET_SEGMENT (fragp->fr_symbol);
17513 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
17514 operand = mips16_immed_operand (type, FALSE);
17515 if (S_FORCE_RELOC (fragp->fr_symbol, TRUE)
17516 || (operand->root.type == OP_PCREL
17518 : !bfd_is_abs_section (symsec)))
17521 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17523 if (operand->root.type == OP_PCREL)
17525 const struct mips_pcrel_operand *pcrel_op;
17528 if (RELAX_MIPS16_ALWAYS_EXTENDED (fragp->fr_subtype))
17531 pcrel_op = (const struct mips_pcrel_operand *) operand;
17532 val = mips16_pcrel_val (fragp, pcrel_op, val, stretch);
17534 /* If any of the shifted bits are set, we must use an extended
17535 opcode. If the address depends on the size of this
17536 instruction, this can lead to a loop, so we arrange to always
17537 use an extended opcode. */
17538 if ((val & ((1 << operand->shift) - 1)) != 0)
17540 fragp->fr_subtype =
17541 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp->fr_subtype);
17545 /* If we are about to mark a frag as extended because the value
17546 is precisely the next value above maxtiny, then there is a
17547 chance of an infinite loop as in the following code:
17552 In this case when the la is extended, foo is 0x3fc bytes
17553 away, so the la can be shrunk, but then foo is 0x400 away, so
17554 the la must be extended. To avoid this loop, we mark the
17555 frag as extended if it was small, and is about to become
17556 extended with the next value above maxtiny. */
17557 maxtiny = mips_int_operand_max (operand);
17558 if (val == maxtiny + (1 << operand->shift)
17559 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17561 fragp->fr_subtype =
17562 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp->fr_subtype);
17567 return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val);
17570 /* Given a MIPS16 variant frag FRAGP, return non-zero if it needs
17571 macro expansion. SEC is the section the frag is in. We only
17572 support PC-relative instructions (LA, DLA, LW, LD) here, in
17573 non-PIC code using 32-bit addressing. */
17576 mips16_macro_frag (fragS *fragp, asection *sec, long stretch)
17578 const struct mips_pcrel_operand *pcrel_op;
17579 const struct mips_int_operand *operand;
17584 gas_assert (!RELAX_MIPS16_USER_SMALL (fragp->fr_subtype));
17586 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17588 if (!RELAX_MIPS16_SYM32 (fragp->fr_subtype))
17591 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
17597 symsec = S_GET_SEGMENT (fragp->fr_symbol);
17598 if (bfd_is_abs_section (symsec))
17600 if (RELAX_MIPS16_PIC (fragp->fr_subtype))
17602 if (S_FORCE_RELOC (fragp->fr_symbol, TRUE) || sec != symsec)
17605 operand = mips16_immed_operand (type, TRUE);
17606 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17607 pcrel_op = (const struct mips_pcrel_operand *) operand;
17608 val = mips16_pcrel_val (fragp, pcrel_op, val, stretch);
17610 return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val);
17617 /* Compute the length of a branch sequence, and adjust the
17618 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17619 worst-case length is computed, with UPDATE being used to indicate
17620 whether an unconditional (-1), branch-likely (+1) or regular (0)
17621 branch is to be computed. */
17623 relaxed_branch_length (fragS *fragp, asection *sec, int update)
17625 bfd_boolean toofar;
17629 && S_IS_DEFINED (fragp->fr_symbol)
17630 && !S_IS_WEAK (fragp->fr_symbol)
17631 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17636 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17638 addr = fragp->fr_address + fragp->fr_fix + 4;
17642 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
17645 /* If the symbol is not defined or it's in a different segment,
17646 we emit the long sequence. */
17649 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17651 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
17652 RELAX_BRANCH_PIC (fragp->fr_subtype),
17653 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
17654 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
17655 RELAX_BRANCH_LINK (fragp->fr_subtype),
17661 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
17664 if (!fragp || RELAX_BRANCH_PIC (fragp->fr_subtype))
17666 /* Additional space for PIC loading of target address. */
17668 if (mips_opts.isa == ISA_MIPS1)
17669 /* Additional space for $at-stabilizing nop. */
17673 /* If branch is conditional. */
17674 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
17681 /* Get a FRAG's branch instruction delay slot size, either from the
17682 short-delay-slot bit of a branch-and-link instruction if AL is TRUE,
17683 or SHORT_INSN_SIZE otherwise. */
17686 frag_branch_delay_slot_size (fragS *fragp, bfd_boolean al, int short_insn_size)
17688 char *buf = fragp->fr_literal + fragp->fr_fix;
17691 return (read_compressed_insn (buf, 4) & 0x02000000) ? 2 : 4;
17693 return short_insn_size;
17696 /* Compute the length of a branch sequence, and adjust the
17697 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17698 worst-case length is computed, with UPDATE being used to indicate
17699 whether an unconditional (-1), or regular (0) branch is to be
17703 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
17705 bfd_boolean insn32 = TRUE;
17706 bfd_boolean nods = TRUE;
17707 bfd_boolean pic = TRUE;
17708 bfd_boolean al = TRUE;
17709 int short_insn_size;
17710 bfd_boolean toofar;
17715 insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype);
17716 nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype);
17717 pic = RELAX_MICROMIPS_PIC (fragp->fr_subtype);
17718 al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
17720 short_insn_size = insn32 ? 4 : 2;
17723 && S_IS_DEFINED (fragp->fr_symbol)
17724 && !S_IS_WEAK (fragp->fr_symbol)
17725 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17730 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17731 /* Ignore the low bit in the target, since it will be set
17732 for a text label. */
17733 if ((val & 1) != 0)
17736 addr = fragp->fr_address + fragp->fr_fix + 4;
17740 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
17743 /* If the symbol is not defined or it's in a different segment,
17744 we emit the long sequence. */
17747 if (fragp && update
17748 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17749 fragp->fr_subtype = (toofar
17750 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
17751 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
17756 bfd_boolean compact_known = fragp != NULL;
17757 bfd_boolean compact = FALSE;
17758 bfd_boolean uncond;
17762 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17763 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
17766 uncond = update < 0;
17768 /* If label is out of range, we turn branch <br>:
17770 <br> label # 4 bytes
17777 # compact && (!PIC || insn32)
17780 if ((!pic || insn32) && (!compact_known || compact))
17781 length += short_insn_size;
17783 /* If assembling PIC code, we further turn:
17789 lw/ld at, %got(label)(gp) # 4 bytes
17790 d/addiu at, %lo(label) # 4 bytes
17791 jr/c at # 2/4 bytes
17794 length += 4 + short_insn_size;
17796 /* Add an extra nop if the jump has no compact form and we need
17797 to fill the delay slot. */
17798 if ((!pic || al) && nods)
17800 ? frag_branch_delay_slot_size (fragp, al, short_insn_size)
17801 : short_insn_size);
17803 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17805 <brneg> 0f # 4 bytes
17806 nop # 2/4 bytes if !compact
17809 length += (compact_known && compact) ? 4 : 4 + short_insn_size;
17813 /* Add an extra nop to fill the delay slot. */
17814 gas_assert (fragp);
17815 length += frag_branch_delay_slot_size (fragp, al, short_insn_size);
17821 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17822 bit accordingly. */
17825 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
17827 bfd_boolean toofar;
17830 && S_IS_DEFINED (fragp->fr_symbol)
17831 && !S_IS_WEAK (fragp->fr_symbol)
17832 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17838 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17839 /* Ignore the low bit in the target, since it will be set
17840 for a text label. */
17841 if ((val & 1) != 0)
17844 /* Assume this is a 2-byte branch. */
17845 addr = fragp->fr_address + fragp->fr_fix + 2;
17847 /* We try to avoid the infinite loop by not adding 2 more bytes for
17852 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17854 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
17855 else if (type == 'E')
17856 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
17861 /* If the symbol is not defined or it's in a different segment,
17862 we emit a normal 32-bit branch. */
17865 if (fragp && update
17866 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17868 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
17869 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
17877 /* Estimate the size of a frag before relaxing. Unless this is the
17878 mips16, we are not really relaxing here, and the final size is
17879 encoded in the subtype information. For the mips16, we have to
17880 decide whether we are using an extended opcode or not. */
17883 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
17887 if (RELAX_BRANCH_P (fragp->fr_subtype))
17890 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
17892 return fragp->fr_var;
17895 if (RELAX_MIPS16_P (fragp->fr_subtype))
17897 /* We don't want to modify the EXTENDED bit here; it might get us
17898 into infinite loops. We change it only in mips_relax_frag(). */
17899 if (RELAX_MIPS16_MACRO (fragp->fr_subtype))
17900 return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 8 : 12;
17902 return RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2;
17905 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17909 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17910 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
17911 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17912 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
17913 fragp->fr_var = length;
17918 if (mips_pic == VXWORKS_PIC)
17919 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17921 else if (RELAX_PIC (fragp->fr_subtype))
17922 change = pic_need_relax (fragp->fr_symbol);
17924 change = nopic_need_relax (fragp->fr_symbol, 0);
17928 fragp->fr_subtype |= RELAX_USE_SECOND;
17929 return -RELAX_FIRST (fragp->fr_subtype);
17932 return -RELAX_SECOND (fragp->fr_subtype);
17935 /* This is called to see whether a reloc against a defined symbol
17936 should be converted into a reloc against a section. */
17939 mips_fix_adjustable (fixS *fixp)
17941 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
17942 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17945 if (fixp->fx_addsy == NULL)
17948 /* Allow relocs used for EH tables. */
17949 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
17952 /* If symbol SYM is in a mergeable section, relocations of the form
17953 SYM + 0 can usually be made section-relative. The mergeable data
17954 is then identified by the section offset rather than by the symbol.
17956 However, if we're generating REL LO16 relocations, the offset is split
17957 between the LO16 and partnering high part relocation. The linker will
17958 need to recalculate the complete offset in order to correctly identify
17961 The linker has traditionally not looked for the partnering high part
17962 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17963 placed anywhere. Rather than break backwards compatibility by changing
17964 this, it seems better not to force the issue, and instead keep the
17965 original symbol. This will work with either linker behavior. */
17966 if ((lo16_reloc_p (fixp->fx_r_type)
17967 || reloc_needs_lo_p (fixp->fx_r_type))
17968 && HAVE_IN_PLACE_ADDENDS
17969 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
17972 /* There is no place to store an in-place offset for JALR relocations. */
17973 if (jalr_reloc_p (fixp->fx_r_type) && HAVE_IN_PLACE_ADDENDS)
17976 /* Likewise an in-range offset of limited PC-relative relocations may
17977 overflow the in-place relocatable field if recalculated against the
17978 start address of the symbol's containing section.
17980 Also, PC relative relocations for MIPS R6 need to be symbol rather than
17981 section relative to allow linker relaxations to be performed later on. */
17982 if (limited_pcrel_reloc_p (fixp->fx_r_type)
17983 && (HAVE_IN_PLACE_ADDENDS || ISA_IS_R6 (file_mips_opts.isa)))
17986 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17987 to a floating-point stub. The same is true for non-R_MIPS16_26
17988 relocations against MIPS16 functions; in this case, the stub becomes
17989 the function's canonical address.
17991 Floating-point stubs are stored in unique .mips16.call.* or
17992 .mips16.fn.* sections. If a stub T for function F is in section S,
17993 the first relocation in section S must be against F; this is how the
17994 linker determines the target function. All relocations that might
17995 resolve to T must also be against F. We therefore have the following
17996 restrictions, which are given in an intentionally-redundant way:
17998 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
18001 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
18002 if that stub might be used.
18004 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
18007 4. We cannot reduce a stub's relocations against MIPS16 symbols if
18008 that stub might be used.
18010 There is a further restriction:
18012 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
18013 R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2,
18014 R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1,
18015 R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1)
18016 against MIPS16 or microMIPS symbols because we need to keep the
18017 MIPS16 or microMIPS symbol for the purpose of mode mismatch
18018 detection and JAL or BAL to JALX instruction conversion in the
18021 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
18022 against a MIPS16 symbol. We deal with (5) by additionally leaving
18023 alone any jump and branch relocations against a microMIPS symbol.
18025 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
18026 relocation against some symbol R, no relocation against R may be
18027 reduced. (Note that this deals with (2) as well as (1) because
18028 relocations against global symbols will never be reduced on ELF
18029 targets.) This approach is a little simpler than trying to detect
18030 stub sections, and gives the "all or nothing" per-symbol consistency
18031 that we have for MIPS16 symbols. */
18032 if (fixp->fx_subsy == NULL
18033 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
18034 || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
18035 && (jmp_reloc_p (fixp->fx_r_type)
18036 || b_reloc_p (fixp->fx_r_type)))
18037 || *symbol_get_tc (fixp->fx_addsy)))
18043 /* Translate internal representation of relocation info to BFD target
18047 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
18049 static arelent *retval[4];
18051 bfd_reloc_code_real_type code;
18053 memset (retval, 0, sizeof(retval));
18054 reloc = retval[0] = XCNEW (arelent);
18055 reloc->sym_ptr_ptr = XNEW (asymbol *);
18056 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
18057 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
18059 if (fixp->fx_pcrel)
18061 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
18062 || fixp->fx_r_type == BFD_RELOC_MIPS16_16_PCREL_S1
18063 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
18064 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
18065 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
18066 || fixp->fx_r_type == BFD_RELOC_32_PCREL
18067 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
18068 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2
18069 || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3
18070 || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2
18071 || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL
18072 || fixp->fx_r_type == BFD_RELOC_LO16_PCREL);
18074 /* At this point, fx_addnumber is "symbol offset - pcrel address".
18075 Relocations want only the symbol offset. */
18076 switch (fixp->fx_r_type)
18078 case BFD_RELOC_MIPS_18_PCREL_S3:
18079 reloc->addend = fixp->fx_addnumber + (reloc->address & ~7);
18082 reloc->addend = fixp->fx_addnumber + reloc->address;
18086 else if (HAVE_IN_PLACE_ADDENDS
18087 && fixp->fx_r_type == BFD_RELOC_MICROMIPS_JMP
18088 && (read_compressed_insn (fixp->fx_frag->fr_literal
18089 + fixp->fx_where, 4) >> 26) == 0x3c)
18091 /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place
18092 addend accordingly. */
18093 reloc->addend = fixp->fx_addnumber >> 1;
18096 reloc->addend = fixp->fx_addnumber;
18098 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
18099 entry to be used in the relocation's section offset. */
18100 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
18102 reloc->address = reloc->addend;
18106 code = fixp->fx_r_type;
18108 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
18109 if (reloc->howto == NULL)
18111 as_bad_where (fixp->fx_file, fixp->fx_line,
18112 _("cannot represent %s relocation in this object file"
18114 bfd_get_reloc_code_name (code));
18121 /* Relax a machine dependent frag. This returns the amount by which
18122 the current size of the frag should change. */
18125 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
18127 if (RELAX_BRANCH_P (fragp->fr_subtype))
18129 offsetT old_var = fragp->fr_var;
18131 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
18133 return fragp->fr_var - old_var;
18136 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
18138 offsetT old_var = fragp->fr_var;
18139 offsetT new_var = 4;
18141 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
18142 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
18143 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
18144 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
18145 fragp->fr_var = new_var;
18147 return new_var - old_var;
18150 if (! RELAX_MIPS16_P (fragp->fr_subtype))
18153 if (!mips16_extended_frag (fragp, sec, stretch))
18155 if (RELAX_MIPS16_MACRO (fragp->fr_subtype))
18157 fragp->fr_subtype = RELAX_MIPS16_CLEAR_MACRO (fragp->fr_subtype);
18158 return RELAX_MIPS16_E2 (fragp->fr_subtype) ? -6 : -10;
18160 else if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18162 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
18168 else if (!mips16_macro_frag (fragp, sec, stretch))
18170 if (RELAX_MIPS16_MACRO (fragp->fr_subtype))
18172 fragp->fr_subtype = RELAX_MIPS16_CLEAR_MACRO (fragp->fr_subtype);
18173 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
18174 return RELAX_MIPS16_E2 (fragp->fr_subtype) ? -4 : -8;
18176 else if (!RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18178 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
18186 if (RELAX_MIPS16_MACRO (fragp->fr_subtype))
18188 else if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18190 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
18191 fragp->fr_subtype = RELAX_MIPS16_MARK_MACRO (fragp->fr_subtype);
18192 return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 4 : 8;
18196 fragp->fr_subtype = RELAX_MIPS16_MARK_MACRO (fragp->fr_subtype);
18197 return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 6 : 10;
18204 /* Convert a machine dependent frag. */
18207 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
18209 if (RELAX_BRANCH_P (fragp->fr_subtype))
18212 unsigned long insn;
18215 buf = fragp->fr_literal + fragp->fr_fix;
18216 insn = read_insn (buf);
18218 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
18220 /* We generate a fixup instead of applying it right now
18221 because, if there are linker relaxations, we're going to
18222 need the relocations. */
18223 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18224 fragp->fr_symbol, fragp->fr_offset,
18225 TRUE, BFD_RELOC_16_PCREL_S2);
18226 fixp->fx_file = fragp->fr_file;
18227 fixp->fx_line = fragp->fr_line;
18229 buf = write_insn (buf, insn);
18235 as_warn_where (fragp->fr_file, fragp->fr_line,
18236 _("relaxed out-of-range branch into a jump"));
18238 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
18241 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18243 /* Reverse the branch. */
18244 switch ((insn >> 28) & 0xf)
18247 if ((insn & 0xff000000) == 0x47000000
18248 || (insn & 0xff600000) == 0x45600000)
18250 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
18251 reversed by tweaking bit 23. */
18252 insn ^= 0x00800000;
18256 /* bc[0-3][tf]l? instructions can have the condition
18257 reversed by tweaking a single TF bit, and their
18258 opcodes all have 0x4???????. */
18259 gas_assert ((insn & 0xf3e00000) == 0x41000000);
18260 insn ^= 0x00010000;
18265 /* bltz 0x04000000 bgez 0x04010000
18266 bltzal 0x04100000 bgezal 0x04110000 */
18267 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
18268 insn ^= 0x00010000;
18272 /* beq 0x10000000 bne 0x14000000
18273 blez 0x18000000 bgtz 0x1c000000 */
18274 insn ^= 0x04000000;
18282 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
18284 /* Clear the and-link bit. */
18285 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
18287 /* bltzal 0x04100000 bgezal 0x04110000
18288 bltzall 0x04120000 bgezall 0x04130000 */
18289 insn &= ~0x00100000;
18292 /* Branch over the branch (if the branch was likely) or the
18293 full jump (not likely case). Compute the offset from the
18294 current instruction to branch to. */
18295 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18299 /* How many bytes in instructions we've already emitted? */
18300 i = buf - fragp->fr_literal - fragp->fr_fix;
18301 /* How many bytes in instructions from here to the end? */
18302 i = fragp->fr_var - i;
18304 /* Convert to instruction count. */
18306 /* Branch counts from the next instruction. */
18309 /* Branch over the jump. */
18310 buf = write_insn (buf, insn);
18313 buf = write_insn (buf, 0);
18315 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18317 /* beql $0, $0, 2f */
18319 /* Compute the PC offset from the current instruction to
18320 the end of the variable frag. */
18321 /* How many bytes in instructions we've already emitted? */
18322 i = buf - fragp->fr_literal - fragp->fr_fix;
18323 /* How many bytes in instructions from here to the end? */
18324 i = fragp->fr_var - i;
18325 /* Convert to instruction count. */
18327 /* Don't decrement i, because we want to branch over the
18331 buf = write_insn (buf, insn);
18332 buf = write_insn (buf, 0);
18336 if (!RELAX_BRANCH_PIC (fragp->fr_subtype))
18339 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
18340 ? 0x0c000000 : 0x08000000);
18342 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18343 fragp->fr_symbol, fragp->fr_offset,
18344 FALSE, BFD_RELOC_MIPS_JMP);
18345 fixp->fx_file = fragp->fr_file;
18346 fixp->fx_line = fragp->fr_line;
18348 buf = write_insn (buf, insn);
18352 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
18354 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18355 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
18356 insn |= at << OP_SH_RT;
18358 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18359 fragp->fr_symbol, fragp->fr_offset,
18360 FALSE, BFD_RELOC_MIPS_GOT16);
18361 fixp->fx_file = fragp->fr_file;
18362 fixp->fx_line = fragp->fr_line;
18364 buf = write_insn (buf, insn);
18366 if (mips_opts.isa == ISA_MIPS1)
18368 buf = write_insn (buf, 0);
18370 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18371 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
18372 insn |= at << OP_SH_RS | at << OP_SH_RT;
18374 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18375 fragp->fr_symbol, fragp->fr_offset,
18376 FALSE, BFD_RELOC_LO16);
18377 fixp->fx_file = fragp->fr_file;
18378 fixp->fx_line = fragp->fr_line;
18380 buf = write_insn (buf, insn);
18383 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
18387 insn |= at << OP_SH_RS;
18389 buf = write_insn (buf, insn);
18393 fragp->fr_fix += fragp->fr_var;
18394 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18398 /* Relax microMIPS branches. */
18399 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
18401 char *buf = fragp->fr_literal + fragp->fr_fix;
18402 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
18403 bfd_boolean insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype);
18404 bfd_boolean nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype);
18405 bfd_boolean pic = RELAX_MICROMIPS_PIC (fragp->fr_subtype);
18406 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
18407 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
18408 bfd_boolean short_ds;
18409 unsigned long insn;
18412 fragp->fr_fix += fragp->fr_var;
18414 /* Handle 16-bit branches that fit or are forced to fit. */
18415 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
18417 /* We generate a fixup instead of applying it right now,
18418 because if there is linker relaxation, we're going to
18419 need the relocations. */
18423 fixp = fix_new (fragp, buf - fragp->fr_literal, 2,
18424 fragp->fr_symbol, fragp->fr_offset,
18425 TRUE, BFD_RELOC_MICROMIPS_10_PCREL_S1);
18428 fixp = fix_new (fragp, buf - fragp->fr_literal, 2,
18429 fragp->fr_symbol, fragp->fr_offset,
18430 TRUE, BFD_RELOC_MICROMIPS_7_PCREL_S1);
18436 fixp->fx_file = fragp->fr_file;
18437 fixp->fx_line = fragp->fr_line;
18439 /* These relocations can have an addend that won't fit in
18441 fixp->fx_no_overflow = 1;
18446 /* Handle 32-bit branches that fit or are forced to fit. */
18447 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18448 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18450 /* We generate a fixup instead of applying it right now,
18451 because if there is linker relaxation, we're going to
18452 need the relocations. */
18453 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18454 fragp->fr_symbol, fragp->fr_offset,
18455 TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1);
18456 fixp->fx_file = fragp->fr_file;
18457 fixp->fx_line = fragp->fr_line;
18461 insn = read_compressed_insn (buf, 4);
18466 /* Check the short-delay-slot bit. */
18467 if (!al || (insn & 0x02000000) != 0)
18468 buf = write_compressed_insn (buf, 0x0c00, 2);
18470 buf = write_compressed_insn (buf, 0x00000000, 4);
18473 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18478 /* Relax 16-bit branches to 32-bit branches. */
18481 insn = read_compressed_insn (buf, 2);
18483 if ((insn & 0xfc00) == 0xcc00) /* b16 */
18484 insn = 0x94000000; /* beq */
18485 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18487 unsigned long regno;
18489 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
18490 regno = micromips_to_32_reg_d_map [regno];
18491 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
18492 insn |= regno << MICROMIPSOP_SH_RS;
18497 /* Nothing else to do, just write it out. */
18498 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18499 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18501 buf = write_compressed_insn (buf, insn, 4);
18503 buf = write_compressed_insn (buf, 0x0c00, 2);
18504 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18509 insn = read_compressed_insn (buf, 4);
18511 /* Relax 32-bit branches to a sequence of instructions. */
18512 as_warn_where (fragp->fr_file, fragp->fr_line,
18513 _("relaxed out-of-range branch into a jump"));
18515 /* Set the short-delay-slot bit. */
18516 short_ds = !al || (insn & 0x02000000) != 0;
18518 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
18522 /* Reverse the branch. */
18523 if ((insn & 0xfc000000) == 0x94000000 /* beq */
18524 || (insn & 0xfc000000) == 0xb4000000) /* bne */
18525 insn ^= 0x20000000;
18526 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
18527 || (insn & 0xffe00000) == 0x40400000 /* bgez */
18528 || (insn & 0xffe00000) == 0x40800000 /* blez */
18529 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
18530 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
18531 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
18532 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
18533 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
18534 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
18535 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
18536 insn ^= 0x00400000;
18537 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
18538 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
18539 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
18540 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
18541 insn ^= 0x00200000;
18542 else if ((insn & 0xff000000) == 0x83000000 /* BZ.df
18544 || (insn & 0xff600000) == 0x81600000) /* BZ.V
18546 insn ^= 0x00800000;
18552 /* Clear the and-link and short-delay-slot bits. */
18553 gas_assert ((insn & 0xfda00000) == 0x40200000);
18555 /* bltzal 0x40200000 bgezal 0x40600000 */
18556 /* bltzals 0x42200000 bgezals 0x42600000 */
18557 insn &= ~0x02200000;
18560 /* Make a label at the end for use with the branch. */
18561 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
18562 micromips_label_inc ();
18563 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
18566 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE,
18567 BFD_RELOC_MICROMIPS_16_PCREL_S1);
18568 fixp->fx_file = fragp->fr_file;
18569 fixp->fx_line = fragp->fr_line;
18571 /* Branch over the jump. */
18572 buf = write_compressed_insn (buf, insn, 4);
18578 buf = write_compressed_insn (buf, 0x00000000, 4);
18580 buf = write_compressed_insn (buf, 0x0c00, 2);
18586 unsigned long jal = (short_ds || nods
18587 ? 0x74000000 : 0xf4000000); /* jal/s */
18589 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18590 insn = al ? jal : 0xd4000000;
18592 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18593 fragp->fr_symbol, fragp->fr_offset,
18594 FALSE, BFD_RELOC_MICROMIPS_JMP);
18595 fixp->fx_file = fragp->fr_file;
18596 fixp->fx_line = fragp->fr_line;
18598 buf = write_compressed_insn (buf, insn, 4);
18600 if (compact || nods)
18604 buf = write_compressed_insn (buf, 0x00000000, 4);
18606 buf = write_compressed_insn (buf, 0x0c00, 2);
18611 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
18613 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18614 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
18615 insn |= at << MICROMIPSOP_SH_RT;
18617 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18618 fragp->fr_symbol, fragp->fr_offset,
18619 FALSE, BFD_RELOC_MICROMIPS_GOT16);
18620 fixp->fx_file = fragp->fr_file;
18621 fixp->fx_line = fragp->fr_line;
18623 buf = write_compressed_insn (buf, insn, 4);
18625 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18626 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
18627 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
18629 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18630 fragp->fr_symbol, fragp->fr_offset,
18631 FALSE, BFD_RELOC_MICROMIPS_LO16);
18632 fixp->fx_file = fragp->fr_file;
18633 fixp->fx_line = fragp->fr_line;
18635 buf = write_compressed_insn (buf, insn, 4);
18640 insn = 0x00000f3c | (al ? RA : ZERO) << MICROMIPSOP_SH_RT;
18641 insn |= at << MICROMIPSOP_SH_RS;
18643 buf = write_compressed_insn (buf, insn, 4);
18645 if (compact || nods)
18647 buf = write_compressed_insn (buf, 0x00000000, 4);
18651 /* jr/jrc/jalr/jalrs $at */
18652 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
18653 unsigned long jr = compact || nods ? 0x45a0 : 0x4580; /* jr/c */
18655 insn = al ? jalr : jr;
18656 insn |= at << MICROMIPSOP_SH_MJ;
18658 buf = write_compressed_insn (buf, insn, 2);
18663 buf = write_compressed_insn (buf, 0x0c00, 2);
18665 buf = write_compressed_insn (buf, 0x00000000, 4);
18670 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18674 if (RELAX_MIPS16_P (fragp->fr_subtype))
18677 const struct mips_int_operand *operand;
18680 unsigned int user_length;
18681 bfd_boolean need_reloc;
18682 unsigned long insn;
18687 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
18688 operand = mips16_immed_operand (type, FALSE);
18690 mac = RELAX_MIPS16_MACRO (fragp->fr_subtype);
18691 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
18692 val = resolve_symbol_value (fragp->fr_symbol) + fragp->fr_offset;
18694 symsec = S_GET_SEGMENT (fragp->fr_symbol);
18695 need_reloc = (S_FORCE_RELOC (fragp->fr_symbol, TRUE)
18696 || (operand->root.type == OP_PCREL && !mac
18698 : !bfd_is_abs_section (symsec)));
18700 if (operand->root.type == OP_PCREL && !mac)
18702 const struct mips_pcrel_operand *pcrel_op;
18704 pcrel_op = (const struct mips_pcrel_operand *) operand;
18706 if (pcrel_op->include_isa_bit && !need_reloc)
18708 if (!mips_ignore_branch_isa
18709 && !ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp->fr_symbol)))
18710 as_bad_where (fragp->fr_file, fragp->fr_line,
18711 _("branch to a symbol in another ISA mode"));
18712 else if ((fragp->fr_offset & 0x1) != 0)
18713 as_bad_where (fragp->fr_file, fragp->fr_line,
18714 _("branch to misaligned address (0x%lx)"),
18718 val = mips16_pcrel_val (fragp, pcrel_op, val, 0);
18720 /* Make sure the section winds up with the alignment we have
18722 if (operand->shift > 0)
18723 record_alignment (asec, operand->shift);
18726 if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
18727 || RELAX_MIPS16_DSLOT (fragp->fr_subtype))
18730 as_warn_where (fragp->fr_file, fragp->fr_line,
18731 _("macro instruction expanded into multiple "
18732 "instructions in a branch delay slot"));
18734 as_warn_where (fragp->fr_file, fragp->fr_line,
18735 _("extended instruction in a branch delay slot"));
18737 else if (RELAX_MIPS16_NOMACRO (fragp->fr_subtype) && mac)
18738 as_warn_where (fragp->fr_file, fragp->fr_line,
18739 _("macro instruction expanded into multiple "
18742 buf = fragp->fr_literal + fragp->fr_fix;
18744 insn = read_compressed_insn (buf, 2);
18746 insn |= MIPS16_EXTEND;
18748 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
18750 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
18762 gas_assert (type == 'A' || type == 'B' || type == 'E');
18763 gas_assert (RELAX_MIPS16_SYM32 (fragp->fr_subtype));
18765 e2 = RELAX_MIPS16_E2 (fragp->fr_subtype);
18771 gas_assert (!RELAX_MIPS16_PIC (fragp->fr_subtype));
18773 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18774 fragp->fr_symbol, fragp->fr_offset,
18775 FALSE, BFD_RELOC_MIPS16_HI16_S);
18776 fixp->fx_file = fragp->fr_file;
18777 fixp->fx_line = fragp->fr_line;
18779 fixp = fix_new (fragp, buf - fragp->fr_literal + (e2 ? 4 : 8), 4,
18780 fragp->fr_symbol, fragp->fr_offset,
18781 FALSE, BFD_RELOC_MIPS16_LO16);
18782 fixp->fx_file = fragp->fr_file;
18783 fixp->fx_line = fragp->fr_line;
18788 switch (insn & 0xf800)
18790 case 0x0800: /* ADDIU */
18791 reg = (insn >> 8) & 0x7;
18792 op = 0xf0004800 | (reg << 8);
18794 case 0xb000: /* LW */
18795 reg = (insn >> 8) & 0x7;
18796 op = 0xf0009800 | (reg << 8) | (reg << 5);
18798 case 0xf800: /* I64 */
18799 reg = (insn >> 5) & 0x7;
18800 switch (insn & 0x0700)
18802 case 0x0400: /* LD */
18803 op = 0xf0003800 | (reg << 8) | (reg << 5);
18805 case 0x0600: /* DADDIU */
18806 op = 0xf000fd00 | (reg << 5);
18816 new = (e2 ? 0xf0006820 : 0xf0006800) | (reg << 8); /* LUI/LI */
18817 new |= mips16_immed_extend ((val + 0x8000) >> 16, 16);
18818 buf = write_compressed_insn (buf, new, 4);
18821 new = 0xf4003000 | (reg << 8) | (reg << 5); /* SLL */
18822 buf = write_compressed_insn (buf, new, 4);
18824 op |= mips16_immed_extend (val, 16);
18825 buf = write_compressed_insn (buf, op, 4);
18827 fragp->fr_fix += e2 ? 8 : 12;
18831 unsigned int length = ext ? 4 : 2;
18835 bfd_reloc_code_real_type reloc = BFD_RELOC_NONE;
18842 reloc = BFD_RELOC_MIPS16_16_PCREL_S1;
18847 if (mac || reloc == BFD_RELOC_NONE)
18848 as_bad_where (fragp->fr_file, fragp->fr_line,
18849 _("unsupported relocation"));
18852 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18853 fragp->fr_symbol, fragp->fr_offset,
18855 fixp->fx_file = fragp->fr_file;
18856 fixp->fx_line = fragp->fr_line;
18859 as_bad_where (fragp->fr_file, fragp->fr_line,
18860 _("invalid unextended operand value"));
18863 mips16_immed (fragp->fr_file, fragp->fr_line, type,
18864 BFD_RELOC_UNUSED, val, user_length, &insn);
18866 gas_assert (mips16_opcode_length (insn) == length);
18867 write_compressed_insn (buf, insn, length);
18868 fragp->fr_fix += length;
18873 relax_substateT subtype = fragp->fr_subtype;
18874 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
18875 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
18879 first = RELAX_FIRST (subtype);
18880 second = RELAX_SECOND (subtype);
18881 fixp = (fixS *) fragp->fr_opcode;
18883 /* If the delay slot chosen does not match the size of the instruction,
18884 then emit a warning. */
18885 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
18886 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
18891 s = subtype & (RELAX_DELAY_SLOT_16BIT
18892 | RELAX_DELAY_SLOT_SIZE_FIRST
18893 | RELAX_DELAY_SLOT_SIZE_SECOND);
18894 msg = macro_warning (s);
18896 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18900 /* Possibly emit a warning if we've chosen the longer option. */
18901 if (use_second == second_longer)
18907 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
18908 msg = macro_warning (s);
18910 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18914 /* Go through all the fixups for the first sequence. Disable them
18915 (by marking them as done) if we're going to use the second
18916 sequence instead. */
18918 && fixp->fx_frag == fragp
18919 && fixp->fx_where < fragp->fr_fix - second)
18921 if (subtype & RELAX_USE_SECOND)
18923 fixp = fixp->fx_next;
18926 /* Go through the fixups for the second sequence. Disable them if
18927 we're going to use the first sequence, otherwise adjust their
18928 addresses to account for the relaxation. */
18929 while (fixp && fixp->fx_frag == fragp)
18931 if (subtype & RELAX_USE_SECOND)
18932 fixp->fx_where -= first;
18935 fixp = fixp->fx_next;
18938 /* Now modify the frag contents. */
18939 if (subtype & RELAX_USE_SECOND)
18943 start = fragp->fr_literal + fragp->fr_fix - first - second;
18944 memmove (start, start + first, second);
18945 fragp->fr_fix -= first;
18948 fragp->fr_fix -= second;
18952 /* This function is called after the relocs have been generated.
18953 We've been storing mips16 text labels as odd. Here we convert them
18954 back to even for the convenience of the debugger. */
18957 mips_frob_file_after_relocs (void)
18960 unsigned int count, i;
18962 syms = bfd_get_outsymbols (stdoutput);
18963 count = bfd_get_symcount (stdoutput);
18964 for (i = 0; i < count; i++, syms++)
18965 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
18966 && ((*syms)->value & 1) != 0)
18968 (*syms)->value &= ~1;
18969 /* If the symbol has an odd size, it was probably computed
18970 incorrectly, so adjust that as well. */
18971 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
18972 ++elf_symbol (*syms)->internal_elf_sym.st_size;
18976 /* This function is called whenever a label is defined, including fake
18977 labels instantiated off the dot special symbol. It is used when
18978 handling branch delays; if a branch has a label, we assume we cannot
18979 move it. This also bumps the value of the symbol by 1 in compressed
18983 mips_record_label (symbolS *sym)
18985 segment_info_type *si = seg_info (now_seg);
18986 struct insn_label_list *l;
18988 if (free_insn_labels == NULL)
18989 l = XNEW (struct insn_label_list);
18992 l = free_insn_labels;
18993 free_insn_labels = l->next;
18997 l->next = si->label_list;
18998 si->label_list = l;
19001 /* This function is called as tc_frob_label() whenever a label is defined
19002 and adds a DWARF-2 record we only want for true labels. */
19005 mips_define_label (symbolS *sym)
19007 mips_record_label (sym);
19008 dwarf2_emit_label (sym);
19011 /* This function is called by tc_new_dot_label whenever a new dot symbol
19015 mips_add_dot_label (symbolS *sym)
19017 mips_record_label (sym);
19018 if (mips_assembling_insn && HAVE_CODE_COMPRESSION)
19019 mips_compressed_mark_label (sym);
19022 /* Converting ASE flags from internal to .MIPS.abiflags values. */
19023 static unsigned int
19024 mips_convert_ase_flags (int ase)
19026 unsigned int ext_ases = 0;
19029 ext_ases |= AFL_ASE_DSP;
19030 if (ase & ASE_DSPR2)
19031 ext_ases |= AFL_ASE_DSPR2;
19032 if (ase & ASE_DSPR3)
19033 ext_ases |= AFL_ASE_DSPR3;
19035 ext_ases |= AFL_ASE_EVA;
19037 ext_ases |= AFL_ASE_MCU;
19038 if (ase & ASE_MDMX)
19039 ext_ases |= AFL_ASE_MDMX;
19040 if (ase & ASE_MIPS3D)
19041 ext_ases |= AFL_ASE_MIPS3D;
19043 ext_ases |= AFL_ASE_MT;
19044 if (ase & ASE_SMARTMIPS)
19045 ext_ases |= AFL_ASE_SMARTMIPS;
19046 if (ase & ASE_VIRT)
19047 ext_ases |= AFL_ASE_VIRT;
19049 ext_ases |= AFL_ASE_MSA;
19051 ext_ases |= AFL_ASE_XPA;
19052 if (ase & ASE_MIPS16E2)
19053 ext_ases |= file_ase_mips16 ? AFL_ASE_MIPS16E2 : 0;
19055 ext_ases |= AFL_ASE_CRC;
19056 if (ase & ASE_GINV)
19057 ext_ases |= AFL_ASE_GINV;
19058 if (ase & ASE_LOONGSON_MMI)
19059 ext_ases |= AFL_ASE_LOONGSON_MMI;
19060 if (ase & ASE_LOONGSON_CAM)
19061 ext_ases |= AFL_ASE_LOONGSON_CAM;
19062 if (ase & ASE_LOONGSON_EXT)
19063 ext_ases |= AFL_ASE_LOONGSON_EXT;
19064 if (ase & ASE_LOONGSON_EXT2)
19065 ext_ases |= AFL_ASE_LOONGSON_EXT2;
19069 /* Some special processing for a MIPS ELF file. */
19072 mips_elf_final_processing (void)
19075 Elf_Internal_ABIFlags_v0 flags;
19079 switch (file_mips_opts.isa)
19082 flags.isa_level = 1;
19085 flags.isa_level = 2;
19088 flags.isa_level = 3;
19091 flags.isa_level = 4;
19094 flags.isa_level = 5;
19097 flags.isa_level = 32;
19101 flags.isa_level = 32;
19105 flags.isa_level = 32;
19109 flags.isa_level = 32;
19113 flags.isa_level = 32;
19117 flags.isa_level = 64;
19121 flags.isa_level = 64;
19125 flags.isa_level = 64;
19129 flags.isa_level = 64;
19133 flags.isa_level = 64;
19138 flags.gpr_size = file_mips_opts.gp == 32 ? AFL_REG_32 : AFL_REG_64;
19139 flags.cpr1_size = file_mips_opts.soft_float ? AFL_REG_NONE
19140 : (file_mips_opts.ase & ASE_MSA) ? AFL_REG_128
19141 : (file_mips_opts.fp == 64) ? AFL_REG_64
19143 flags.cpr2_size = AFL_REG_NONE;
19144 flags.fp_abi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
19145 Tag_GNU_MIPS_ABI_FP);
19146 flags.isa_ext = bfd_mips_isa_ext (stdoutput);
19147 flags.ases = mips_convert_ase_flags (file_mips_opts.ase);
19148 if (file_ase_mips16)
19149 flags.ases |= AFL_ASE_MIPS16;
19150 if (file_ase_micromips)
19151 flags.ases |= AFL_ASE_MICROMIPS;
19153 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts.isa, file_mips_opts.arch)
19154 || file_mips_opts.fp == 64)
19155 && file_mips_opts.oddspreg)
19156 flags.flags1 |= AFL_FLAGS1_ODDSPREG;
19159 bfd_mips_elf_swap_abiflags_v0_out (stdoutput, &flags,
19160 ((Elf_External_ABIFlags_v0 *)
19163 /* Write out the register information. */
19164 if (mips_abi != N64_ABI)
19168 s.ri_gprmask = mips_gprmask;
19169 s.ri_cprmask[0] = mips_cprmask[0];
19170 s.ri_cprmask[1] = mips_cprmask[1];
19171 s.ri_cprmask[2] = mips_cprmask[2];
19172 s.ri_cprmask[3] = mips_cprmask[3];
19173 /* The gp_value field is set by the MIPS ELF backend. */
19175 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
19176 ((Elf32_External_RegInfo *)
19177 mips_regmask_frag));
19181 Elf64_Internal_RegInfo s;
19183 s.ri_gprmask = mips_gprmask;
19185 s.ri_cprmask[0] = mips_cprmask[0];
19186 s.ri_cprmask[1] = mips_cprmask[1];
19187 s.ri_cprmask[2] = mips_cprmask[2];
19188 s.ri_cprmask[3] = mips_cprmask[3];
19189 /* The gp_value field is set by the MIPS ELF backend. */
19191 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
19192 ((Elf64_External_RegInfo *)
19193 mips_regmask_frag));
19196 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
19197 sort of BFD interface for this. */
19198 if (mips_any_noreorder)
19199 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
19200 if (mips_pic != NO_PIC)
19202 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
19203 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
19206 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
19208 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
19209 defined at present; this might need to change in future. */
19210 if (file_ase_mips16)
19211 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
19212 if (file_ase_micromips)
19213 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
19214 if (file_mips_opts.ase & ASE_MDMX)
19215 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
19217 /* Set the MIPS ELF ABI flags. */
19218 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
19219 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
19220 else if (mips_abi == O64_ABI)
19221 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
19222 else if (mips_abi == EABI_ABI)
19224 if (file_mips_opts.gp == 64)
19225 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
19227 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
19230 /* Nothing to do for N32_ABI or N64_ABI. */
19232 if (mips_32bitmode)
19233 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
19235 if (mips_nan2008 == 1)
19236 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008;
19238 /* 32 bit code with 64 bit FP registers. */
19239 fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
19240 Tag_GNU_MIPS_ABI_FP);
19241 if (fpabi == Val_GNU_MIPS_ABI_FP_OLD_64)
19242 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_FP64;
19245 typedef struct proc {
19247 symbolS *func_end_sym;
19248 unsigned long reg_mask;
19249 unsigned long reg_offset;
19250 unsigned long fpreg_mask;
19251 unsigned long fpreg_offset;
19252 unsigned long frame_offset;
19253 unsigned long frame_reg;
19254 unsigned long pc_reg;
19257 static procS cur_proc;
19258 static procS *cur_proc_ptr;
19259 static int numprocs;
19261 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
19262 as "2", and a normal nop as "0". */
19264 #define NOP_OPCODE_MIPS 0
19265 #define NOP_OPCODE_MIPS16 1
19266 #define NOP_OPCODE_MICROMIPS 2
19269 mips_nop_opcode (void)
19271 if (seg_info (now_seg)->tc_segment_info_data.micromips)
19272 return NOP_OPCODE_MICROMIPS;
19273 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
19274 return NOP_OPCODE_MIPS16;
19276 return NOP_OPCODE_MIPS;
19279 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
19280 32-bit microMIPS NOPs here (if applicable). */
19283 mips_handle_align (fragS *fragp)
19287 int bytes, size, excess;
19290 if (fragp->fr_type != rs_align_code)
19293 p = fragp->fr_literal + fragp->fr_fix;
19295 switch (nop_opcode)
19297 case NOP_OPCODE_MICROMIPS:
19298 opcode = micromips_nop32_insn.insn_opcode;
19301 case NOP_OPCODE_MIPS16:
19302 opcode = mips16_nop_insn.insn_opcode;
19305 case NOP_OPCODE_MIPS:
19307 opcode = nop_insn.insn_opcode;
19312 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
19313 excess = bytes % size;
19315 /* Handle the leading part if we're not inserting a whole number of
19316 instructions, and make it the end of the fixed part of the frag.
19317 Try to fit in a short microMIPS NOP if applicable and possible,
19318 and use zeroes otherwise. */
19319 gas_assert (excess < 4);
19320 fragp->fr_fix += excess;
19325 /* Fall through. */
19327 if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32)
19329 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2);
19333 /* Fall through. */
19336 /* Fall through. */
19341 md_number_to_chars (p, opcode, size);
19342 fragp->fr_var = size;
19351 if (*input_line_pointer == '-')
19353 ++input_line_pointer;
19356 if (!ISDIGIT (*input_line_pointer))
19357 as_bad (_("expected simple number"));
19358 if (input_line_pointer[0] == '0')
19360 if (input_line_pointer[1] == 'x')
19362 input_line_pointer += 2;
19363 while (ISXDIGIT (*input_line_pointer))
19366 val |= hex_value (*input_line_pointer++);
19368 return negative ? -val : val;
19372 ++input_line_pointer;
19373 while (ISDIGIT (*input_line_pointer))
19376 val |= *input_line_pointer++ - '0';
19378 return negative ? -val : val;
19381 if (!ISDIGIT (*input_line_pointer))
19383 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
19384 *input_line_pointer, *input_line_pointer);
19385 as_warn (_("invalid number"));
19388 while (ISDIGIT (*input_line_pointer))
19391 val += *input_line_pointer++ - '0';
19393 return negative ? -val : val;
19396 /* The .file directive; just like the usual .file directive, but there
19397 is an initial number which is the ECOFF file index. In the non-ECOFF
19398 case .file implies DWARF-2. */
19401 s_mips_file (int x ATTRIBUTE_UNUSED)
19403 static int first_file_directive = 0;
19405 if (ECOFF_DEBUGGING)
19414 filename = dwarf2_directive_filename ();
19416 /* Versions of GCC up to 3.1 start files with a ".file"
19417 directive even for stabs output. Make sure that this
19418 ".file" is handled. Note that you need a version of GCC
19419 after 3.1 in order to support DWARF-2 on MIPS. */
19420 if (filename != NULL && ! first_file_directive)
19422 (void) new_logical_line (filename, -1);
19423 s_app_file_string (filename, 0);
19425 first_file_directive = 1;
19429 /* The .loc directive, implying DWARF-2. */
19432 s_mips_loc (int x ATTRIBUTE_UNUSED)
19434 if (!ECOFF_DEBUGGING)
19435 dwarf2_directive_loc (0);
19438 /* The .end directive. */
19441 s_mips_end (int x ATTRIBUTE_UNUSED)
19445 /* Following functions need their own .frame and .cprestore directives. */
19446 mips_frame_reg_valid = 0;
19447 mips_cprestore_valid = 0;
19449 if (!is_end_of_line[(unsigned char) *input_line_pointer])
19452 demand_empty_rest_of_line ();
19457 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
19458 as_warn (_(".end not in text section"));
19462 as_warn (_(".end directive without a preceding .ent directive"));
19463 demand_empty_rest_of_line ();
19469 gas_assert (S_GET_NAME (p));
19470 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
19471 as_warn (_(".end symbol does not match .ent symbol"));
19473 if (debug_type == DEBUG_STABS)
19474 stabs_generate_asm_endfunc (S_GET_NAME (p),
19478 as_warn (_(".end directive missing or unknown symbol"));
19480 /* Create an expression to calculate the size of the function. */
19481 if (p && cur_proc_ptr)
19483 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
19484 expressionS *exp = XNEW (expressionS);
19487 exp->X_op = O_subtract;
19488 exp->X_add_symbol = symbol_temp_new_now ();
19489 exp->X_op_symbol = p;
19490 exp->X_add_number = 0;
19492 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
19495 #ifdef md_flush_pending_output
19496 md_flush_pending_output ();
19499 /* Generate a .pdr section. */
19500 if (!ECOFF_DEBUGGING && mips_flag_pdr)
19502 segT saved_seg = now_seg;
19503 subsegT saved_subseg = now_subseg;
19507 gas_assert (pdr_seg);
19508 subseg_set (pdr_seg, 0);
19510 /* Write the symbol. */
19511 exp.X_op = O_symbol;
19512 exp.X_add_symbol = p;
19513 exp.X_add_number = 0;
19514 emit_expr (&exp, 4);
19516 fragp = frag_more (7 * 4);
19518 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
19519 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
19520 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
19521 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
19522 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
19523 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
19524 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
19526 subseg_set (saved_seg, saved_subseg);
19529 cur_proc_ptr = NULL;
19532 /* The .aent and .ent directives. */
19535 s_mips_ent (int aent)
19539 symbolP = get_symbol ();
19540 if (*input_line_pointer == ',')
19541 ++input_line_pointer;
19542 SKIP_WHITESPACE ();
19543 if (ISDIGIT (*input_line_pointer)
19544 || *input_line_pointer == '-')
19547 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
19548 as_warn (_(".ent or .aent not in text section"));
19550 if (!aent && cur_proc_ptr)
19551 as_warn (_("missing .end"));
19555 /* This function needs its own .frame and .cprestore directives. */
19556 mips_frame_reg_valid = 0;
19557 mips_cprestore_valid = 0;
19559 cur_proc_ptr = &cur_proc;
19560 memset (cur_proc_ptr, '\0', sizeof (procS));
19562 cur_proc_ptr->func_sym = symbolP;
19566 if (debug_type == DEBUG_STABS)
19567 stabs_generate_asm_func (S_GET_NAME (symbolP),
19568 S_GET_NAME (symbolP));
19571 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
19573 demand_empty_rest_of_line ();
19576 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19577 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19578 s_mips_frame is used so that we can set the PDR information correctly.
19579 We can't use the ecoff routines because they make reference to the ecoff
19580 symbol table (in the mdebug section). */
19583 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
19585 if (ECOFF_DEBUGGING)
19591 if (cur_proc_ptr == (procS *) NULL)
19593 as_warn (_(".frame outside of .ent"));
19594 demand_empty_rest_of_line ();
19598 cur_proc_ptr->frame_reg = tc_get_register (1);
19600 SKIP_WHITESPACE ();
19601 if (*input_line_pointer++ != ','
19602 || get_absolute_expression_and_terminator (&val) != ',')
19604 as_warn (_("bad .frame directive"));
19605 --input_line_pointer;
19606 demand_empty_rest_of_line ();
19610 cur_proc_ptr->frame_offset = val;
19611 cur_proc_ptr->pc_reg = tc_get_register (0);
19613 demand_empty_rest_of_line ();
19617 /* The .fmask and .mask directives. If the mdebug section is present
19618 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19619 embedded targets, s_mips_mask is used so that we can set the PDR
19620 information correctly. We can't use the ecoff routines because they
19621 make reference to the ecoff symbol table (in the mdebug section). */
19624 s_mips_mask (int reg_type)
19626 if (ECOFF_DEBUGGING)
19627 s_ignore (reg_type);
19632 if (cur_proc_ptr == (procS *) NULL)
19634 as_warn (_(".mask/.fmask outside of .ent"));
19635 demand_empty_rest_of_line ();
19639 if (get_absolute_expression_and_terminator (&mask) != ',')
19641 as_warn (_("bad .mask/.fmask directive"));
19642 --input_line_pointer;
19643 demand_empty_rest_of_line ();
19647 off = get_absolute_expression ();
19649 if (reg_type == 'F')
19651 cur_proc_ptr->fpreg_mask = mask;
19652 cur_proc_ptr->fpreg_offset = off;
19656 cur_proc_ptr->reg_mask = mask;
19657 cur_proc_ptr->reg_offset = off;
19660 demand_empty_rest_of_line ();
19664 /* A table describing all the processors gas knows about. Names are
19665 matched in the order listed.
19667 To ease comparison, please keep this table in the same order as
19668 gcc's mips_cpu_info_table[]. */
19669 static const struct mips_cpu_info mips_cpu_info_table[] =
19671 /* Entries for generic ISAs */
19672 { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 },
19673 { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 },
19674 { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 },
19675 { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 },
19676 { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 },
19677 { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 },
19678 { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19679 { "mips32r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R3, CPU_MIPS32R3 },
19680 { "mips32r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R5, CPU_MIPS32R5 },
19681 { "mips32r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R6, CPU_MIPS32R6 },
19682 { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 },
19683 { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 },
19684 { "mips64r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R3, CPU_MIPS64R3 },
19685 { "mips64r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R5, CPU_MIPS64R5 },
19686 { "mips64r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R6, CPU_MIPS64R6 },
19689 { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 },
19690 { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 },
19691 { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 },
19694 { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 },
19697 { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 },
19698 { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 },
19699 { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 },
19700 { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 },
19701 { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 },
19702 { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 },
19703 { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 },
19704 { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 },
19705 { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 },
19706 { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 },
19707 { "orion", 0, 0, ISA_MIPS3, CPU_R4600 },
19708 { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 },
19709 { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 },
19710 /* ST Microelectronics Loongson 2E and 2F cores */
19711 { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E },
19712 { "loongson2f", 0, ASE_LOONGSON_MMI, ISA_MIPS3, CPU_LOONGSON_2F },
19715 { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 },
19716 { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 },
19717 { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 },
19718 { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 },
19719 { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 },
19720 { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 },
19721 { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 },
19722 { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 },
19723 { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 },
19724 { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 },
19725 { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 },
19726 { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 },
19727 { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 },
19728 { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 },
19729 { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 },
19732 { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19733 { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19734 { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19735 { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
19737 /* MIPS 32 Release 2 */
19738 { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19739 { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19740 { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19741 { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
19742 { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19743 { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19744 { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19745 { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19746 { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
19747 ISA_MIPS32R2, CPU_MIPS32R2 },
19748 { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
19749 ISA_MIPS32R2, CPU_MIPS32R2 },
19750 { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19751 { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19752 { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19753 { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19754 /* Deprecated forms of the above. */
19755 { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19756 { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19757 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19758 { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19759 { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19760 { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19761 { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19762 /* Deprecated forms of the above. */
19763 { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19764 { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19765 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19766 { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19767 { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19768 { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19769 { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19770 /* Deprecated forms of the above. */
19771 { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19772 { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19773 /* 34Kn is a 34kc without DSP. */
19774 { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19775 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19776 { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19777 { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19778 { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19779 { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19780 { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19781 /* Deprecated forms of the above. */
19782 { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19783 { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19784 /* 1004K cores are multiprocessor versions of the 34K. */
19785 { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19786 { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19787 { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19788 { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19789 /* interaptiv is the new name for 1004kf */
19790 { "interaptiv", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19791 { "interaptiv-mr2", 0,
19792 ASE_DSP | ASE_EVA | ASE_MT | ASE_MIPS16E2 | ASE_MIPS16E2_MT,
19793 ISA_MIPS32R3, CPU_INTERAPTIV_MR2 },
19795 { "m5100", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 },
19796 { "m5101", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 },
19797 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
19798 { "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R5, CPU_MIPS32R5 },
19801 { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 },
19802 { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 },
19803 { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19804 { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19806 /* Broadcom SB-1 CPU core */
19807 { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
19808 /* Broadcom SB-1A CPU core */
19809 { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
19811 /* MIPS 64 Release 2 */
19812 /* Loongson CPU core */
19813 /* -march=loongson3a is an alias of -march=gs464 for compatibility */
19814 { "loongson3a", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT,
19815 ISA_MIPS64R2, CPU_GS464 },
19816 { "gs464", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT,
19817 ISA_MIPS64R2, CPU_GS464 },
19818 { "gs464e", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT
19819 | ASE_LOONGSON_EXT2, ISA_MIPS64R2, CPU_GS464E },
19821 /* Cavium Networks Octeon CPU core */
19822 { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
19823 { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP },
19824 { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 },
19825 { "octeon3", 0, ASE_VIRT | ASE_VIRT64, ISA_MIPS64R5, CPU_OCTEON3 },
19828 { "xlr", 0, 0, ISA_MIPS64, CPU_XLR },
19831 XLP is mostly like XLR, with the prominent exception that it is
19832 MIPS64R2 rather than MIPS64. */
19833 { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
19835 /* MIPS 64 Release 6 */
19836 { "i6400", 0, ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6},
19837 { "p6600", 0, ASE_VIRT | ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6},
19840 { NULL, 0, 0, 0, 0 }
19844 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19845 with a final "000" replaced by "k". Ignore case.
19847 Note: this function is shared between GCC and GAS. */
19850 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
19852 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
19853 given++, canonical++;
19855 return ((*given == 0 && *canonical == 0)
19856 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
19860 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19861 CPU name. We've traditionally allowed a lot of variation here.
19863 Note: this function is shared between GCC and GAS. */
19866 mips_matching_cpu_name_p (const char *canonical, const char *given)
19868 /* First see if the name matches exactly, or with a final "000"
19869 turned into "k". */
19870 if (mips_strict_matching_cpu_name_p (canonical, given))
19873 /* If not, try comparing based on numerical designation alone.
19874 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19875 if (TOLOWER (*given) == 'r')
19877 if (!ISDIGIT (*given))
19880 /* Skip over some well-known prefixes in the canonical name,
19881 hoping to find a number there too. */
19882 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
19884 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
19886 else if (TOLOWER (canonical[0]) == 'r')
19889 return mips_strict_matching_cpu_name_p (canonical, given);
19893 /* Parse an option that takes the name of a processor as its argument.
19894 OPTION is the name of the option and CPU_STRING is the argument.
19895 Return the corresponding processor enumeration if the CPU_STRING is
19896 recognized, otherwise report an error and return null.
19898 A similar function exists in GCC. */
19900 static const struct mips_cpu_info *
19901 mips_parse_cpu (const char *option, const char *cpu_string)
19903 const struct mips_cpu_info *p;
19905 /* 'from-abi' selects the most compatible architecture for the given
19906 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19907 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19908 version. Look first at the -mgp options, if given, otherwise base
19909 the choice on MIPS_DEFAULT_64BIT.
19911 Treat NO_ABI like the EABIs. One reason to do this is that the
19912 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19913 architecture. This code picks MIPS I for 'mips' and MIPS III for
19914 'mips64', just as we did in the days before 'from-abi'. */
19915 if (strcasecmp (cpu_string, "from-abi") == 0)
19917 if (ABI_NEEDS_32BIT_REGS (mips_abi))
19918 return mips_cpu_info_from_isa (ISA_MIPS1);
19920 if (ABI_NEEDS_64BIT_REGS (mips_abi))
19921 return mips_cpu_info_from_isa (ISA_MIPS3);
19923 if (file_mips_opts.gp >= 0)
19924 return mips_cpu_info_from_isa (file_mips_opts.gp == 32
19925 ? ISA_MIPS1 : ISA_MIPS3);
19927 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19932 /* 'default' has traditionally been a no-op. Probably not very useful. */
19933 if (strcasecmp (cpu_string, "default") == 0)
19936 for (p = mips_cpu_info_table; p->name != 0; p++)
19937 if (mips_matching_cpu_name_p (p->name, cpu_string))
19940 as_bad (_("bad value (%s) for %s"), cpu_string, option);
19944 /* Return the canonical processor information for ISA (a member of the
19945 ISA_MIPS* enumeration). */
19947 static const struct mips_cpu_info *
19948 mips_cpu_info_from_isa (int isa)
19952 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19953 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
19954 && isa == mips_cpu_info_table[i].isa)
19955 return (&mips_cpu_info_table[i]);
19960 static const struct mips_cpu_info *
19961 mips_cpu_info_from_arch (int arch)
19965 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19966 if (arch == mips_cpu_info_table[i].cpu)
19967 return (&mips_cpu_info_table[i]);
19973 show (FILE *stream, const char *string, int *col_p, int *first_p)
19977 fprintf (stream, "%24s", "");
19982 fprintf (stream, ", ");
19986 if (*col_p + strlen (string) > 72)
19988 fprintf (stream, "\n%24s", "");
19992 fprintf (stream, "%s", string);
19993 *col_p += strlen (string);
19999 md_show_usage (FILE *stream)
20004 fprintf (stream, _("\
20006 -EB generate big endian output\n\
20007 -EL generate little endian output\n\
20008 -g, -g2 do not remove unneeded NOPs or swap branches\n\
20009 -G NUM allow referencing objects up to NUM bytes\n\
20010 implicitly with the gp register [default 8]\n"));
20011 fprintf (stream, _("\
20012 -mips1 generate MIPS ISA I instructions\n\
20013 -mips2 generate MIPS ISA II instructions\n\
20014 -mips3 generate MIPS ISA III instructions\n\
20015 -mips4 generate MIPS ISA IV instructions\n\
20016 -mips5 generate MIPS ISA V instructions\n\
20017 -mips32 generate MIPS32 ISA instructions\n\
20018 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
20019 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
20020 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
20021 -mips32r6 generate MIPS32 release 6 ISA instructions\n\
20022 -mips64 generate MIPS64 ISA instructions\n\
20023 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
20024 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
20025 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
20026 -mips64r6 generate MIPS64 release 6 ISA instructions\n\
20027 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
20031 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
20032 show (stream, mips_cpu_info_table[i].name, &column, &first);
20033 show (stream, "from-abi", &column, &first);
20034 fputc ('\n', stream);
20036 fprintf (stream, _("\
20037 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
20038 -no-mCPU don't generate code specific to CPU.\n\
20039 For -mCPU and -no-mCPU, CPU must be one of:\n"));
20043 show (stream, "3900", &column, &first);
20044 show (stream, "4010", &column, &first);
20045 show (stream, "4100", &column, &first);
20046 show (stream, "4650", &column, &first);
20047 fputc ('\n', stream);
20049 fprintf (stream, _("\
20050 -mips16 generate mips16 instructions\n\
20051 -no-mips16 do not generate mips16 instructions\n"));
20052 fprintf (stream, _("\
20053 -mmips16e2 generate MIPS16e2 instructions\n\
20054 -mno-mips16e2 do not generate MIPS16e2 instructions\n"));
20055 fprintf (stream, _("\
20056 -mmicromips generate microMIPS instructions\n\
20057 -mno-micromips do not generate microMIPS instructions\n"));
20058 fprintf (stream, _("\
20059 -msmartmips generate smartmips instructions\n\
20060 -mno-smartmips do not generate smartmips instructions\n"));
20061 fprintf (stream, _("\
20062 -mdsp generate DSP instructions\n\
20063 -mno-dsp do not generate DSP instructions\n"));
20064 fprintf (stream, _("\
20065 -mdspr2 generate DSP R2 instructions\n\
20066 -mno-dspr2 do not generate DSP R2 instructions\n"));
20067 fprintf (stream, _("\
20068 -mdspr3 generate DSP R3 instructions\n\
20069 -mno-dspr3 do not generate DSP R3 instructions\n"));
20070 fprintf (stream, _("\
20071 -mmt generate MT instructions\n\
20072 -mno-mt do not generate MT instructions\n"));
20073 fprintf (stream, _("\
20074 -mmcu generate MCU instructions\n\
20075 -mno-mcu do not generate MCU instructions\n"));
20076 fprintf (stream, _("\
20077 -mmsa generate MSA instructions\n\
20078 -mno-msa do not generate MSA instructions\n"));
20079 fprintf (stream, _("\
20080 -mxpa generate eXtended Physical Address (XPA) instructions\n\
20081 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
20082 fprintf (stream, _("\
20083 -mvirt generate Virtualization instructions\n\
20084 -mno-virt do not generate Virtualization instructions\n"));
20085 fprintf (stream, _("\
20086 -mcrc generate CRC instructions\n\
20087 -mno-crc do not generate CRC instructions\n"));
20088 fprintf (stream, _("\
20089 -mginv generate Global INValidate (GINV) instructions\n\
20090 -mno-ginv do not generate Global INValidate instructions\n"));
20091 fprintf (stream, _("\
20092 -mloongson-mmi generate Loongson MultiMedia extensions Instructions (MMI) instructions\n\
20093 -mno-loongson-mmi do not generate Loongson MultiMedia extensions Instructions\n"));
20094 fprintf (stream, _("\
20095 -mloongson-cam generate Loongson Content Address Memory (CAM) instructions\n\
20096 -mno-loongson-cam do not generate Loongson Content Address Memory Instructions\n"));
20097 fprintf (stream, _("\
20098 -mloongson-ext generate Loongson EXTensions (EXT) instructions\n\
20099 -mno-loongson-ext do not generate Loongson EXTensions Instructions\n"));
20100 fprintf (stream, _("\
20101 -mloongson-ext2 generate Loongson EXTensions R2 (EXT2) instructions\n\
20102 -mno-loongson-ext2 do not generate Loongson EXTensions R2 Instructions\n"));
20103 fprintf (stream, _("\
20104 -minsn32 only generate 32-bit microMIPS instructions\n\
20105 -mno-insn32 generate all microMIPS instructions\n"));
20106 fprintf (stream, _("\
20107 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
20108 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
20109 -mfix-vr4120 work around certain VR4120 errata\n\
20110 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
20111 -mfix-24k insert a nop after ERET and DERET instructions\n\
20112 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
20113 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
20114 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
20115 -msym32 assume all symbols have 32-bit values\n\
20116 -O0 do not remove unneeded NOPs, do not swap branches\n\
20117 -O, -O1 remove unneeded NOPs, do not swap branches\n\
20118 -O2 remove unneeded NOPs and swap branches\n\
20119 --trap, --no-break trap exception on div by 0 and mult overflow\n\
20120 --break, --no-trap break exception on div by 0 and mult overflow\n"));
20121 fprintf (stream, _("\
20122 -mhard-float allow floating-point instructions\n\
20123 -msoft-float do not allow floating-point instructions\n\
20124 -msingle-float only allow 32-bit floating-point operations\n\
20125 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
20126 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
20127 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
20128 -mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\
20129 -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\
20130 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
20134 show (stream, "legacy", &column, &first);
20135 show (stream, "2008", &column, &first);
20137 fputc ('\n', stream);
20139 fprintf (stream, _("\
20140 -KPIC, -call_shared generate SVR4 position independent code\n\
20141 -call_nonpic generate non-PIC code that can operate with DSOs\n\
20142 -mvxworks-pic generate VxWorks position independent code\n\
20143 -non_shared do not generate code that can operate with DSOs\n\
20144 -xgot assume a 32 bit GOT\n\
20145 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
20146 -mshared, -mno-shared disable/enable .cpload optimization for\n\
20147 position dependent (non shared) code\n\
20148 -mabi=ABI create ABI conformant object file for:\n"));
20152 show (stream, "32", &column, &first);
20153 show (stream, "o64", &column, &first);
20154 show (stream, "n32", &column, &first);
20155 show (stream, "64", &column, &first);
20156 show (stream, "eabi", &column, &first);
20158 fputc ('\n', stream);
20160 fprintf (stream, _("\
20161 -32 create o32 ABI object file%s\n"),
20162 MIPS_DEFAULT_ABI == O32_ABI ? _(" (default)") : "");
20163 fprintf (stream, _("\
20164 -n32 create n32 ABI object file%s\n"),
20165 MIPS_DEFAULT_ABI == N32_ABI ? _(" (default)") : "");
20166 fprintf (stream, _("\
20167 -64 create 64 ABI object file%s\n"),
20168 MIPS_DEFAULT_ABI == N64_ABI ? _(" (default)") : "");
20173 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
20175 if (HAVE_64BIT_SYMBOLS)
20176 return dwarf2_format_64bit_irix;
20178 return dwarf2_format_32bit;
20183 mips_dwarf2_addr_size (void)
20185 if (HAVE_64BIT_OBJECTS)
20191 /* Standard calling conventions leave the CFA at SP on entry. */
20193 mips_cfi_frame_initial_instructions (void)
20195 cfi_add_CFA_def_cfa_register (SP);
20199 tc_mips_regname_to_dw2regnum (char *regname)
20201 unsigned int regnum = -1;
20204 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))
20210 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
20211 Given a symbolic attribute NAME, return the proper integer value.
20212 Returns -1 if the attribute is not known. */
20215 mips_convert_symbolic_attribute (const char *name)
20217 static const struct
20222 attribute_table[] =
20224 #define T(tag) {#tag, tag}
20225 T (Tag_GNU_MIPS_ABI_FP),
20226 T (Tag_GNU_MIPS_ABI_MSA),
20234 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
20235 if (streq (name, attribute_table[i].name))
20236 return attribute_table[i].tag;
20244 int fpabi = Val_GNU_MIPS_ABI_FP_ANY;
20246 mips_emit_delays ();
20248 as_warn (_("missing .end at end of assembly"));
20250 /* Just in case no code was emitted, do the consistency check. */
20251 file_mips_check_options ();
20253 /* Set a floating-point ABI if the user did not. */
20254 if (obj_elf_seen_attribute (OBJ_ATTR_GNU, Tag_GNU_MIPS_ABI_FP))
20256 /* Perform consistency checks on the floating-point ABI. */
20257 fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
20258 Tag_GNU_MIPS_ABI_FP);
20259 if (fpabi != Val_GNU_MIPS_ABI_FP_ANY)
20260 check_fpabi (fpabi);
20264 /* Soft-float gets precedence over single-float, the two options should
20265 not be used together so this should not matter. */
20266 if (file_mips_opts.soft_float == 1)
20267 fpabi = Val_GNU_MIPS_ABI_FP_SOFT;
20268 /* Single-float gets precedence over all double_float cases. */
20269 else if (file_mips_opts.single_float == 1)
20270 fpabi = Val_GNU_MIPS_ABI_FP_SINGLE;
20273 switch (file_mips_opts.fp)
20276 if (file_mips_opts.gp == 32)
20277 fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE;
20280 fpabi = Val_GNU_MIPS_ABI_FP_XX;
20283 if (file_mips_opts.gp == 32 && !file_mips_opts.oddspreg)
20284 fpabi = Val_GNU_MIPS_ABI_FP_64A;
20285 else if (file_mips_opts.gp == 32)
20286 fpabi = Val_GNU_MIPS_ABI_FP_64;
20288 fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE;
20293 bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
20294 Tag_GNU_MIPS_ABI_FP, fpabi);
20298 /* Returns the relocation type required for a particular CFI encoding. */
20300 bfd_reloc_code_real_type
20301 mips_cfi_reloc_for_encoding (int encoding)
20303 if (encoding == (DW_EH_PE_sdata4 | DW_EH_PE_pcrel))
20304 return BFD_RELOC_32_PCREL;
20305 else return BFD_RELOC_NONE;