1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 #define AT mips_opts.at
107 /* Allow override of standard little-endian ECOFF format. */
109 #ifndef ECOFF_LITTLE_FORMAT
110 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
113 extern int target_big_endian;
115 /* The name of the readonly data section. */
116 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
124 /* Ways in which an instruction can be "appended" to the output. */
126 /* Just add it normally. */
129 /* Add it normally and then add a nop. */
132 /* Turn an instruction with a delay slot into a "compact" version. */
135 /* Insert the instruction before the last one. */
139 /* Information about an instruction, including its format, operands
143 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
144 const struct mips_opcode *insn_mo;
146 /* True if this is a mips16 instruction and if we want the extended
148 bfd_boolean use_extend;
150 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
151 unsigned short extend;
153 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
154 a copy of INSN_MO->match with the operands filled in. */
155 unsigned long insn_opcode;
157 /* The frag that contains the instruction. */
160 /* The offset into FRAG of the first instruction byte. */
163 /* The relocs associated with the instruction, if any. */
166 /* True if this entry cannot be moved from its current position. */
167 unsigned int fixed_p : 1;
169 /* True if this instruction occurred in a .set noreorder block. */
170 unsigned int noreorder_p : 1;
172 /* True for mips16 instructions that jump to an absolute address. */
173 unsigned int mips16_absolute_jump_p : 1;
175 /* True if this instruction is complete. */
176 unsigned int complete_p : 1;
179 /* The ABI to use. */
190 /* MIPS ABI we are using for this output file. */
191 static enum mips_abi_level mips_abi = NO_ABI;
193 /* Whether or not we have code that can call pic code. */
194 int mips_abicalls = FALSE;
196 /* Whether or not we have code which can be put into a shared
198 static bfd_boolean mips_in_shared = TRUE;
200 /* This is the set of options which may be modified by the .set
201 pseudo-op. We use a struct so that .set push and .set pop are more
204 struct mips_set_options
206 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
207 if it has not been initialized. Changed by `.set mipsN', and the
208 -mipsN command line option, and the default CPU. */
210 /* Enabled Application Specific Extensions (ASEs). These are set to -1
211 if they have not been initialized. Changed by `.set <asename>', by
212 command line options, and based on the default architecture. */
219 /* Whether we are assembling for the mips16 processor. 0 if we are
220 not, 1 if we are, and -1 if the value has not been initialized.
221 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
222 -nomips16 command line options, and the default CPU. */
224 /* Non-zero if we should not reorder instructions. Changed by `.set
225 reorder' and `.set noreorder'. */
227 /* Non-zero if we should not permit the register designated "assembler
228 temporary" to be used in instructions. The value is the register
229 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
230 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
232 /* Non-zero if we should warn when a macro instruction expands into
233 more than one machine instruction. Changed by `.set nomacro' and
235 int warn_about_macros;
236 /* Non-zero if we should not move instructions. Changed by `.set
237 move', `.set volatile', `.set nomove', and `.set novolatile'. */
239 /* Non-zero if we should not optimize branches by moving the target
240 of the branch into the delay slot. Actually, we don't perform
241 this optimization anyhow. Changed by `.set bopt' and `.set
244 /* Non-zero if we should not autoextend mips16 instructions.
245 Changed by `.set autoextend' and `.set noautoextend'. */
247 /* Restrict general purpose registers and floating point registers
248 to 32 bit. This is initially determined when -mgp32 or -mfp32
249 is passed but can changed if the assembler code uses .set mipsN. */
252 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
253 command line option, and the default CPU. */
255 /* True if ".set sym32" is in effect. */
257 /* True if floating-point operations are not allowed. Changed by .set
258 softfloat or .set hardfloat, by command line options -msoft-float or
259 -mhard-float. The default is false. */
260 bfd_boolean soft_float;
262 /* True if only single-precision floating-point operations are allowed.
263 Changed by .set singlefloat or .set doublefloat, command-line options
264 -msingle-float or -mdouble-float. The default is false. */
265 bfd_boolean single_float;
268 /* This is the struct we use to hold the current set of options. Note
269 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
270 -1 to indicate that they have not been initialized. */
272 /* True if -mgp32 was passed. */
273 static int file_mips_gp32 = -1;
275 /* True if -mfp32 was passed. */
276 static int file_mips_fp32 = -1;
278 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
279 static int file_mips_soft_float = 0;
281 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
282 static int file_mips_single_float = 0;
284 static struct mips_set_options mips_opts =
286 /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
287 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
288 /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG,
289 /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
290 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN,
291 /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE
294 /* These variables are filled in with the masks of registers used.
295 The object format code reads them and puts them in the appropriate
297 unsigned long mips_gprmask;
298 unsigned long mips_cprmask[4];
300 /* MIPS ISA we are using for this output file. */
301 static int file_mips_isa = ISA_UNKNOWN;
303 /* True if any MIPS16 code was produced. */
304 static int file_ase_mips16;
306 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
307 || mips_opts.isa == ISA_MIPS32R2 \
308 || mips_opts.isa == ISA_MIPS64 \
309 || mips_opts.isa == ISA_MIPS64R2)
311 /* True if we want to create R_MIPS_JALR for jalr $25. */
313 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
315 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
316 because there's no place for any addend, the only acceptable
317 expression is a bare symbol. */
318 #define MIPS_JALR_HINT_P(EXPR) \
319 (!HAVE_IN_PLACE_ADDENDS \
320 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
323 /* True if -mips3d was passed or implied by arguments passed on the
324 command line (e.g., by -march). */
325 static int file_ase_mips3d;
327 /* True if -mdmx was passed or implied by arguments passed on the
328 command line (e.g., by -march). */
329 static int file_ase_mdmx;
331 /* True if -msmartmips was passed or implied by arguments passed on the
332 command line (e.g., by -march). */
333 static int file_ase_smartmips;
335 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
336 || mips_opts.isa == ISA_MIPS32R2)
338 /* True if -mdsp was passed or implied by arguments passed on the
339 command line (e.g., by -march). */
340 static int file_ase_dsp;
342 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
343 || mips_opts.isa == ISA_MIPS64R2)
345 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
347 /* True if -mdspr2 was passed or implied by arguments passed on the
348 command line (e.g., by -march). */
349 static int file_ase_dspr2;
351 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
352 || mips_opts.isa == ISA_MIPS64R2)
354 /* True if -mmt was passed or implied by arguments passed on the
355 command line (e.g., by -march). */
356 static int file_ase_mt;
358 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
359 || mips_opts.isa == ISA_MIPS64R2)
361 /* The argument of the -march= flag. The architecture we are assembling. */
362 static int file_mips_arch = CPU_UNKNOWN;
363 static const char *mips_arch_string;
365 /* The argument of the -mtune= flag. The architecture for which we
367 static int mips_tune = CPU_UNKNOWN;
368 static const char *mips_tune_string;
370 /* True when generating 32-bit code for a 64-bit processor. */
371 static int mips_32bitmode = 0;
373 /* True if the given ABI requires 32-bit registers. */
374 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
376 /* Likewise 64-bit registers. */
377 #define ABI_NEEDS_64BIT_REGS(ABI) \
379 || (ABI) == N64_ABI \
382 /* Return true if ISA supports 64 bit wide gp registers. */
383 #define ISA_HAS_64BIT_REGS(ISA) \
384 ((ISA) == ISA_MIPS3 \
385 || (ISA) == ISA_MIPS4 \
386 || (ISA) == ISA_MIPS5 \
387 || (ISA) == ISA_MIPS64 \
388 || (ISA) == ISA_MIPS64R2)
390 /* Return true if ISA supports 64 bit wide float registers. */
391 #define ISA_HAS_64BIT_FPRS(ISA) \
392 ((ISA) == ISA_MIPS3 \
393 || (ISA) == ISA_MIPS4 \
394 || (ISA) == ISA_MIPS5 \
395 || (ISA) == ISA_MIPS32R2 \
396 || (ISA) == ISA_MIPS64 \
397 || (ISA) == ISA_MIPS64R2)
399 /* Return true if ISA supports 64-bit right rotate (dror et al.)
401 #define ISA_HAS_DROR(ISA) \
402 ((ISA) == ISA_MIPS64R2)
404 /* Return true if ISA supports 32-bit right rotate (ror et al.)
406 #define ISA_HAS_ROR(ISA) \
407 ((ISA) == ISA_MIPS32R2 \
408 || (ISA) == ISA_MIPS64R2 \
409 || mips_opts.ase_smartmips)
411 /* Return true if ISA supports single-precision floats in odd registers. */
412 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
413 ((ISA) == ISA_MIPS32 \
414 || (ISA) == ISA_MIPS32R2 \
415 || (ISA) == ISA_MIPS64 \
416 || (ISA) == ISA_MIPS64R2)
418 /* Return true if ISA supports move to/from high part of a 64-bit
419 floating-point register. */
420 #define ISA_HAS_MXHC1(ISA) \
421 ((ISA) == ISA_MIPS32R2 \
422 || (ISA) == ISA_MIPS64R2)
424 #define HAVE_32BIT_GPRS \
425 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
427 #define HAVE_32BIT_FPRS \
428 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
430 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
431 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
433 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
435 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
437 /* True if relocations are stored in-place. */
438 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
440 /* The ABI-derived address size. */
441 #define HAVE_64BIT_ADDRESSES \
442 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
443 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
445 /* The size of symbolic constants (i.e., expressions of the form
446 "SYMBOL" or "SYMBOL + OFFSET"). */
447 #define HAVE_32BIT_SYMBOLS \
448 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
449 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
451 /* Addresses are loaded in different ways, depending on the address size
452 in use. The n32 ABI Documentation also mandates the use of additions
453 with overflow checking, but existing implementations don't follow it. */
454 #define ADDRESS_ADD_INSN \
455 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
457 #define ADDRESS_ADDI_INSN \
458 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
460 #define ADDRESS_LOAD_INSN \
461 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
463 #define ADDRESS_STORE_INSN \
464 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
466 /* Return true if the given CPU supports the MIPS16 ASE. */
467 #define CPU_HAS_MIPS16(cpu) \
468 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
469 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
471 /* True if CPU has a dror instruction. */
472 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
474 /* True if CPU has a ror instruction. */
475 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
477 /* True if CPU has seq/sne and seqi/snei instructions. */
478 #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON)
480 /* True if CPU does not implement the all the coprocessor insns. For these
481 CPUs only those COP insns are accepted that are explicitly marked to be
482 available on the CPU. ISA membership for COP insns is ignored. */
483 #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON)
485 /* True if mflo and mfhi can be immediately followed by instructions
486 which write to the HI and LO registers.
488 According to MIPS specifications, MIPS ISAs I, II, and III need
489 (at least) two instructions between the reads of HI/LO and
490 instructions which write them, and later ISAs do not. Contradicting
491 the MIPS specifications, some MIPS IV processor user manuals (e.g.
492 the UM for the NEC Vr5000) document needing the instructions between
493 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
494 MIPS64 and later ISAs to have the interlocks, plus any specific
495 earlier-ISA CPUs for which CPU documentation declares that the
496 instructions are really interlocked. */
497 #define hilo_interlocks \
498 (mips_opts.isa == ISA_MIPS32 \
499 || mips_opts.isa == ISA_MIPS32R2 \
500 || mips_opts.isa == ISA_MIPS64 \
501 || mips_opts.isa == ISA_MIPS64R2 \
502 || mips_opts.arch == CPU_R4010 \
503 || mips_opts.arch == CPU_R10000 \
504 || mips_opts.arch == CPU_R12000 \
505 || mips_opts.arch == CPU_R14000 \
506 || mips_opts.arch == CPU_R16000 \
507 || mips_opts.arch == CPU_RM7000 \
508 || mips_opts.arch == CPU_VR5500 \
511 /* Whether the processor uses hardware interlocks to protect reads
512 from the GPRs after they are loaded from memory, and thus does not
513 require nops to be inserted. This applies to instructions marked
514 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
516 #define gpr_interlocks \
517 (mips_opts.isa != ISA_MIPS1 \
518 || mips_opts.arch == CPU_R3900)
520 /* Whether the processor uses hardware interlocks to avoid delays
521 required by coprocessor instructions, and thus does not require
522 nops to be inserted. This applies to instructions marked
523 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
524 between instructions marked INSN_WRITE_COND_CODE and ones marked
525 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
526 levels I, II, and III. */
527 /* Itbl support may require additional care here. */
528 #define cop_interlocks \
529 ((mips_opts.isa != ISA_MIPS1 \
530 && mips_opts.isa != ISA_MIPS2 \
531 && mips_opts.isa != ISA_MIPS3) \
532 || mips_opts.arch == CPU_R4300 \
535 /* Whether the processor uses hardware interlocks to protect reads
536 from coprocessor registers after they are loaded from memory, and
537 thus does not require nops to be inserted. This applies to
538 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
539 requires at MIPS ISA level I. */
540 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
542 /* Is this a mfhi or mflo instruction? */
543 #define MF_HILO_INSN(PINFO) \
544 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
546 /* Returns true for a (non floating-point) coprocessor instruction. Reading
547 or writing the condition code is only possible on the coprocessors and
548 these insns are not marked with INSN_COP. Thus for these insns use the
549 condition-code flags. */
550 #define COP_INSN(PINFO) \
551 (PINFO != INSN_MACRO \
552 && ((PINFO) & (FP_S | FP_D)) == 0 \
553 && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
555 /* MIPS PIC level. */
557 enum mips_pic_level mips_pic;
559 /* 1 if we should generate 32 bit offsets from the $gp register in
560 SVR4_PIC mode. Currently has no meaning in other modes. */
561 static int mips_big_got = 0;
563 /* 1 if trap instructions should used for overflow rather than break
565 static int mips_trap = 0;
567 /* 1 if double width floating point constants should not be constructed
568 by assembling two single width halves into two single width floating
569 point registers which just happen to alias the double width destination
570 register. On some architectures this aliasing can be disabled by a bit
571 in the status register, and the setting of this bit cannot be determined
572 automatically at assemble time. */
573 static int mips_disable_float_construction;
575 /* Non-zero if any .set noreorder directives were used. */
577 static int mips_any_noreorder;
579 /* Non-zero if nops should be inserted when the register referenced in
580 an mfhi/mflo instruction is read in the next two instructions. */
581 static int mips_7000_hilo_fix;
583 /* The size of objects in the small data section. */
584 static unsigned int g_switch_value = 8;
585 /* Whether the -G option was used. */
586 static int g_switch_seen = 0;
591 /* If we can determine in advance that GP optimization won't be
592 possible, we can skip the relaxation stuff that tries to produce
593 GP-relative references. This makes delay slot optimization work
596 This function can only provide a guess, but it seems to work for
597 gcc output. It needs to guess right for gcc, otherwise gcc
598 will put what it thinks is a GP-relative instruction in a branch
601 I don't know if a fix is needed for the SVR4_PIC mode. I've only
602 fixed it for the non-PIC mode. KR 95/04/07 */
603 static int nopic_need_relax (symbolS *, int);
605 /* handle of the OPCODE hash table */
606 static struct hash_control *op_hash = NULL;
608 /* The opcode hash table we use for the mips16. */
609 static struct hash_control *mips16_op_hash = NULL;
611 /* This array holds the chars that always start a comment. If the
612 pre-processor is disabled, these aren't very useful */
613 const char comment_chars[] = "#";
615 /* This array holds the chars that only start a comment at the beginning of
616 a line. If the line seems to have the form '# 123 filename'
617 .line and .file directives will appear in the pre-processed output */
618 /* Note that input_file.c hand checks for '#' at the beginning of the
619 first line of the input file. This is because the compiler outputs
620 #NO_APP at the beginning of its output. */
621 /* Also note that C style comments are always supported. */
622 const char line_comment_chars[] = "#";
624 /* This array holds machine specific line separator characters. */
625 const char line_separator_chars[] = ";";
627 /* Chars that can be used to separate mant from exp in floating point nums */
628 const char EXP_CHARS[] = "eE";
630 /* Chars that mean this number is a floating point constant */
633 const char FLT_CHARS[] = "rRsSfFdDxXpP";
635 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
636 changed in read.c . Ideally it shouldn't have to know about it at all,
637 but nothing is ideal around here.
640 static char *insn_error;
642 static int auto_align = 1;
644 /* When outputting SVR4 PIC code, the assembler needs to know the
645 offset in the stack frame from which to restore the $gp register.
646 This is set by the .cprestore pseudo-op, and saved in this
648 static offsetT mips_cprestore_offset = -1;
650 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
651 more optimizations, it can use a register value instead of a memory-saved
652 offset and even an other register than $gp as global pointer. */
653 static offsetT mips_cpreturn_offset = -1;
654 static int mips_cpreturn_register = -1;
655 static int mips_gp_register = GP;
656 static int mips_gprel_offset = 0;
658 /* Whether mips_cprestore_offset has been set in the current function
659 (or whether it has already been warned about, if not). */
660 static int mips_cprestore_valid = 0;
662 /* This is the register which holds the stack frame, as set by the
663 .frame pseudo-op. This is needed to implement .cprestore. */
664 static int mips_frame_reg = SP;
666 /* Whether mips_frame_reg has been set in the current function
667 (or whether it has already been warned about, if not). */
668 static int mips_frame_reg_valid = 0;
670 /* To output NOP instructions correctly, we need to keep information
671 about the previous two instructions. */
673 /* Whether we are optimizing. The default value of 2 means to remove
674 unneeded NOPs and swap branch instructions when possible. A value
675 of 1 means to not swap branches. A value of 0 means to always
677 static int mips_optimize = 2;
679 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
680 equivalent to seeing no -g option at all. */
681 static int mips_debug = 0;
683 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
684 #define MAX_VR4130_NOPS 4
686 /* The maximum number of NOPs needed to fill delay slots. */
687 #define MAX_DELAY_NOPS 2
689 /* The maximum number of NOPs needed for any purpose. */
692 /* A list of previous instructions, with index 0 being the most recent.
693 We need to look back MAX_NOPS instructions when filling delay slots
694 or working around processor errata. We need to look back one
695 instruction further if we're thinking about using history[0] to
696 fill a branch delay slot. */
697 static struct mips_cl_insn history[1 + MAX_NOPS];
699 /* Nop instructions used by emit_nop. */
700 static struct mips_cl_insn nop_insn, mips16_nop_insn;
702 /* The appropriate nop for the current mode. */
703 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
705 /* If this is set, it points to a frag holding nop instructions which
706 were inserted before the start of a noreorder section. If those
707 nops turn out to be unnecessary, the size of the frag can be
709 static fragS *prev_nop_frag;
711 /* The number of nop instructions we created in prev_nop_frag. */
712 static int prev_nop_frag_holds;
714 /* The number of nop instructions that we know we need in
716 static int prev_nop_frag_required;
718 /* The number of instructions we've seen since prev_nop_frag. */
719 static int prev_nop_frag_since;
721 /* For ECOFF and ELF, relocations against symbols are done in two
722 parts, with a HI relocation and a LO relocation. Each relocation
723 has only 16 bits of space to store an addend. This means that in
724 order for the linker to handle carries correctly, it must be able
725 to locate both the HI and the LO relocation. This means that the
726 relocations must appear in order in the relocation table.
728 In order to implement this, we keep track of each unmatched HI
729 relocation. We then sort them so that they immediately precede the
730 corresponding LO relocation. */
735 struct mips_hi_fixup *next;
738 /* The section this fixup is in. */
742 /* The list of unmatched HI relocs. */
744 static struct mips_hi_fixup *mips_hi_fixup_list;
746 /* The frag containing the last explicit relocation operator.
747 Null if explicit relocations have not been used. */
749 static fragS *prev_reloc_op_frag;
751 /* Map normal MIPS register numbers to mips16 register numbers. */
753 #define X ILLEGAL_REG
754 static const int mips32_to_16_reg_map[] =
756 X, X, 2, 3, 4, 5, 6, 7,
757 X, X, X, X, X, X, X, X,
758 0, 1, X, X, X, X, X, X,
759 X, X, X, X, X, X, X, X
763 /* Map mips16 register numbers to normal MIPS register numbers. */
765 static const unsigned int mips16_to_32_reg_map[] =
767 16, 17, 2, 3, 4, 5, 6, 7
770 /* Classifies the kind of instructions we're interested in when
771 implementing -mfix-vr4120. */
772 enum fix_vr4120_class
780 NUM_FIX_VR4120_CLASSES
783 /* ...likewise -mfix-loongson2f-jump. */
784 static bfd_boolean mips_fix_loongson2f_jump;
786 /* ...likewise -mfix-loongson2f-nop. */
787 static bfd_boolean mips_fix_loongson2f_nop;
789 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
790 static bfd_boolean mips_fix_loongson2f;
792 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
793 there must be at least one other instruction between an instruction
794 of type X and an instruction of type Y. */
795 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
797 /* True if -mfix-vr4120 is in force. */
798 static int mips_fix_vr4120;
800 /* ...likewise -mfix-vr4130. */
801 static int mips_fix_vr4130;
803 /* ...likewise -mfix-24k. */
804 static int mips_fix_24k;
806 /* ...likewise -mfix-cn63xxp1 */
807 static bfd_boolean mips_fix_cn63xxp1;
809 /* We don't relax branches by default, since this causes us to expand
810 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
811 fail to compute the offset before expanding the macro to the most
812 efficient expansion. */
814 static int mips_relax_branch;
816 /* The expansion of many macros depends on the type of symbol that
817 they refer to. For example, when generating position-dependent code,
818 a macro that refers to a symbol may have two different expansions,
819 one which uses GP-relative addresses and one which uses absolute
820 addresses. When generating SVR4-style PIC, a macro may have
821 different expansions for local and global symbols.
823 We handle these situations by generating both sequences and putting
824 them in variant frags. In position-dependent code, the first sequence
825 will be the GP-relative one and the second sequence will be the
826 absolute one. In SVR4 PIC, the first sequence will be for global
827 symbols and the second will be for local symbols.
829 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
830 SECOND are the lengths of the two sequences in bytes. These fields
831 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
832 the subtype has the following flags:
835 Set if it has been decided that we should use the second
836 sequence instead of the first.
839 Set in the first variant frag if the macro's second implementation
840 is longer than its first. This refers to the macro as a whole,
841 not an individual relaxation.
844 Set in the first variant frag if the macro appeared in a .set nomacro
845 block and if one alternative requires a warning but the other does not.
848 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
851 The frag's "opcode" points to the first fixup for relaxable code.
853 Relaxable macros are generated using a sequence such as:
855 relax_start (SYMBOL);
856 ... generate first expansion ...
858 ... generate second expansion ...
861 The code and fixups for the unwanted alternative are discarded
862 by md_convert_frag. */
863 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
865 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
866 #define RELAX_SECOND(X) ((X) & 0xff)
867 #define RELAX_USE_SECOND 0x10000
868 #define RELAX_SECOND_LONGER 0x20000
869 #define RELAX_NOMACRO 0x40000
870 #define RELAX_DELAY_SLOT 0x80000
872 /* Branch without likely bit. If label is out of range, we turn:
874 beq reg1, reg2, label
884 with the following opcode replacements:
891 bltzal <-> bgezal (with jal label instead of j label)
893 Even though keeping the delay slot instruction in the delay slot of
894 the branch would be more efficient, it would be very tricky to do
895 correctly, because we'd have to introduce a variable frag *after*
896 the delay slot instruction, and expand that instead. Let's do it
897 the easy way for now, even if the branch-not-taken case now costs
898 one additional instruction. Out-of-range branches are not supposed
899 to be common, anyway.
901 Branch likely. If label is out of range, we turn:
903 beql reg1, reg2, label
904 delay slot (annulled if branch not taken)
913 delay slot (executed only if branch taken)
916 It would be possible to generate a shorter sequence by losing the
917 likely bit, generating something like:
922 delay slot (executed only if branch taken)
934 bltzall -> bgezal (with jal label instead of j label)
935 bgezall -> bltzal (ditto)
938 but it's not clear that it would actually improve performance. */
939 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
943 | ((toofar) ? 0x20 : 0) \
944 | ((link) ? 0x40 : 0) \
945 | ((likely) ? 0x80 : 0) \
946 | ((uncond) ? 0x100 : 0)))
947 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
948 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
949 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
950 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
951 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
952 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
954 /* For mips16 code, we use an entirely different form of relaxation.
955 mips16 supports two versions of most instructions which take
956 immediate values: a small one which takes some small value, and a
957 larger one which takes a 16 bit value. Since branches also follow
958 this pattern, relaxing these values is required.
960 We can assemble both mips16 and normal MIPS code in a single
961 object. Therefore, we need to support this type of relaxation at
962 the same time that we support the relaxation described above. We
963 use the high bit of the subtype field to distinguish these cases.
965 The information we store for this type of relaxation is the
966 argument code found in the opcode file for this relocation, whether
967 the user explicitly requested a small or extended form, and whether
968 the relocation is in a jump or jal delay slot. That tells us the
969 size of the value, and how it should be stored. We also store
970 whether the fragment is considered to be extended or not. We also
971 store whether this is known to be a branch to a different section,
972 whether we have tried to relax this frag yet, and whether we have
973 ever extended a PC relative fragment because of a shift count. */
974 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
977 | ((small) ? 0x100 : 0) \
978 | ((ext) ? 0x200 : 0) \
979 | ((dslot) ? 0x400 : 0) \
980 | ((jal_dslot) ? 0x800 : 0))
981 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
982 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
983 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
984 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
985 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
986 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
987 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
988 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
989 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
990 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
991 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
992 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
994 /* Is the given value a sign-extended 32-bit value? */
995 #define IS_SEXT_32BIT_NUM(x) \
996 (((x) &~ (offsetT) 0x7fffffff) == 0 \
997 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
999 /* Is the given value a sign-extended 16-bit value? */
1000 #define IS_SEXT_16BIT_NUM(x) \
1001 (((x) &~ (offsetT) 0x7fff) == 0 \
1002 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1004 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1005 #define IS_ZEXT_32BIT_NUM(x) \
1006 (((x) &~ (offsetT) 0xffffffff) == 0 \
1007 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1009 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1010 VALUE << SHIFT. VALUE is evaluated exactly once. */
1011 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1012 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1013 | (((VALUE) & (MASK)) << (SHIFT)))
1015 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1017 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1018 (((STRUCT) >> (SHIFT)) & (MASK))
1020 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1021 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1023 include/opcode/mips.h specifies operand fields using the macros
1024 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1025 with "MIPS16OP" instead of "OP". */
1026 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
1027 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
1028 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1029 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1030 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1032 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1033 #define EXTRACT_OPERAND(FIELD, INSN) \
1034 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
1035 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1036 EXTRACT_BITS ((INSN).insn_opcode, \
1037 MIPS16OP_MASK_##FIELD, \
1038 MIPS16OP_SH_##FIELD)
1040 /* Global variables used when generating relaxable macros. See the
1041 comment above RELAX_ENCODE for more details about how relaxation
1044 /* 0 if we're not emitting a relaxable macro.
1045 1 if we're emitting the first of the two relaxation alternatives.
1046 2 if we're emitting the second alternative. */
1049 /* The first relaxable fixup in the current frag. (In other words,
1050 the first fixup that refers to relaxable code.) */
1053 /* sizes[0] says how many bytes of the first alternative are stored in
1054 the current frag. Likewise sizes[1] for the second alternative. */
1055 unsigned int sizes[2];
1057 /* The symbol on which the choice of sequence depends. */
1061 /* Global variables used to decide whether a macro needs a warning. */
1063 /* True if the macro is in a branch delay slot. */
1064 bfd_boolean delay_slot_p;
1066 /* For relaxable macros, sizes[0] is the length of the first alternative
1067 in bytes and sizes[1] is the length of the second alternative.
1068 For non-relaxable macros, both elements give the length of the
1070 unsigned int sizes[2];
1072 /* The first variant frag for this macro. */
1074 } mips_macro_warning;
1076 /* Prototypes for static functions. */
1078 #define internalError() \
1079 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1081 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1083 static void append_insn
1084 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *);
1085 static void mips_no_prev_insn (void);
1086 static void macro_build (expressionS *, const char *, const char *, ...);
1087 static void mips16_macro_build
1088 (expressionS *, const char *, const char *, va_list *);
1089 static void load_register (int, expressionS *, int);
1090 static void macro_start (void);
1091 static void macro_end (void);
1092 static void macro (struct mips_cl_insn * ip);
1093 static void mips16_macro (struct mips_cl_insn * ip);
1094 static void mips_ip (char *str, struct mips_cl_insn * ip);
1095 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1096 static void mips16_immed
1097 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
1098 unsigned long *, bfd_boolean *, unsigned short *);
1099 static size_t my_getSmallExpression
1100 (expressionS *, bfd_reloc_code_real_type *, char *);
1101 static void my_getExpression (expressionS *, char *);
1102 static void s_align (int);
1103 static void s_change_sec (int);
1104 static void s_change_section (int);
1105 static void s_cons (int);
1106 static void s_float_cons (int);
1107 static void s_mips_globl (int);
1108 static void s_option (int);
1109 static void s_mipsset (int);
1110 static void s_abicalls (int);
1111 static void s_cpload (int);
1112 static void s_cpsetup (int);
1113 static void s_cplocal (int);
1114 static void s_cprestore (int);
1115 static void s_cpreturn (int);
1116 static void s_dtprelword (int);
1117 static void s_dtpreldword (int);
1118 static void s_gpvalue (int);
1119 static void s_gpword (int);
1120 static void s_gpdword (int);
1121 static void s_cpadd (int);
1122 static void s_insn (int);
1123 static void md_obj_begin (void);
1124 static void md_obj_end (void);
1125 static void s_mips_ent (int);
1126 static void s_mips_end (int);
1127 static void s_mips_frame (int);
1128 static void s_mips_mask (int reg_type);
1129 static void s_mips_stab (int);
1130 static void s_mips_weakext (int);
1131 static void s_mips_file (int);
1132 static void s_mips_loc (int);
1133 static bfd_boolean pic_need_relax (symbolS *, asection *);
1134 static int relaxed_branch_length (fragS *, asection *, int);
1135 static int validate_mips_insn (const struct mips_opcode *);
1137 /* Table and functions used to map between CPU/ISA names, and
1138 ISA levels, and CPU numbers. */
1140 struct mips_cpu_info
1142 const char *name; /* CPU or ISA name. */
1143 int flags; /* ASEs available, or ISA flag. */
1144 int isa; /* ISA level. */
1145 int cpu; /* CPU number (default CPU if ISA). */
1148 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1149 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1150 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1151 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1152 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1153 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1154 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1156 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1157 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1158 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1162 The following pseudo-ops from the Kane and Heinrich MIPS book
1163 should be defined here, but are currently unsupported: .alias,
1164 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1166 The following pseudo-ops from the Kane and Heinrich MIPS book are
1167 specific to the type of debugging information being generated, and
1168 should be defined by the object format: .aent, .begin, .bend,
1169 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1172 The following pseudo-ops from the Kane and Heinrich MIPS book are
1173 not MIPS CPU specific, but are also not specific to the object file
1174 format. This file is probably the best place to define them, but
1175 they are not currently supported: .asm0, .endr, .lab, .struct. */
1177 static const pseudo_typeS mips_pseudo_table[] =
1179 /* MIPS specific pseudo-ops. */
1180 {"option", s_option, 0},
1181 {"set", s_mipsset, 0},
1182 {"rdata", s_change_sec, 'r'},
1183 {"sdata", s_change_sec, 's'},
1184 {"livereg", s_ignore, 0},
1185 {"abicalls", s_abicalls, 0},
1186 {"cpload", s_cpload, 0},
1187 {"cpsetup", s_cpsetup, 0},
1188 {"cplocal", s_cplocal, 0},
1189 {"cprestore", s_cprestore, 0},
1190 {"cpreturn", s_cpreturn, 0},
1191 {"dtprelword", s_dtprelword, 0},
1192 {"dtpreldword", s_dtpreldword, 0},
1193 {"gpvalue", s_gpvalue, 0},
1194 {"gpword", s_gpword, 0},
1195 {"gpdword", s_gpdword, 0},
1196 {"cpadd", s_cpadd, 0},
1197 {"insn", s_insn, 0},
1199 /* Relatively generic pseudo-ops that happen to be used on MIPS
1201 {"asciiz", stringer, 8 + 1},
1202 {"bss", s_change_sec, 'b'},
1204 {"half", s_cons, 1},
1205 {"dword", s_cons, 3},
1206 {"weakext", s_mips_weakext, 0},
1207 {"origin", s_org, 0},
1208 {"repeat", s_rept, 0},
1210 /* For MIPS this is non-standard, but we define it for consistency. */
1211 {"sbss", s_change_sec, 'B'},
1213 /* These pseudo-ops are defined in read.c, but must be overridden
1214 here for one reason or another. */
1215 {"align", s_align, 0},
1216 {"byte", s_cons, 0},
1217 {"data", s_change_sec, 'd'},
1218 {"double", s_float_cons, 'd'},
1219 {"float", s_float_cons, 'f'},
1220 {"globl", s_mips_globl, 0},
1221 {"global", s_mips_globl, 0},
1222 {"hword", s_cons, 1},
1224 {"long", s_cons, 2},
1225 {"octa", s_cons, 4},
1226 {"quad", s_cons, 3},
1227 {"section", s_change_section, 0},
1228 {"short", s_cons, 1},
1229 {"single", s_float_cons, 'f'},
1230 {"stabn", s_mips_stab, 'n'},
1231 {"text", s_change_sec, 't'},
1232 {"word", s_cons, 2},
1234 { "extern", ecoff_directive_extern, 0},
1239 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1241 /* These pseudo-ops should be defined by the object file format.
1242 However, a.out doesn't support them, so we have versions here. */
1243 {"aent", s_mips_ent, 1},
1244 {"bgnb", s_ignore, 0},
1245 {"end", s_mips_end, 0},
1246 {"endb", s_ignore, 0},
1247 {"ent", s_mips_ent, 0},
1248 {"file", s_mips_file, 0},
1249 {"fmask", s_mips_mask, 'F'},
1250 {"frame", s_mips_frame, 0},
1251 {"loc", s_mips_loc, 0},
1252 {"mask", s_mips_mask, 'R'},
1253 {"verstamp", s_ignore, 0},
1257 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1258 purpose of the `.dc.a' internal pseudo-op. */
1261 mips_address_bytes (void)
1263 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1266 extern void pop_insert (const pseudo_typeS *);
1269 mips_pop_insert (void)
1271 pop_insert (mips_pseudo_table);
1272 if (! ECOFF_DEBUGGING)
1273 pop_insert (mips_nonecoff_pseudo_table);
1276 /* Symbols labelling the current insn. */
1278 struct insn_label_list
1280 struct insn_label_list *next;
1284 static struct insn_label_list *free_insn_labels;
1285 #define label_list tc_segment_info_data.labels
1287 static void mips_clear_insn_labels (void);
1290 mips_clear_insn_labels (void)
1292 register struct insn_label_list **pl;
1293 segment_info_type *si;
1297 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1300 si = seg_info (now_seg);
1301 *pl = si->label_list;
1302 si->label_list = NULL;
1307 static char *expr_end;
1309 /* Expressions which appear in instructions. These are set by
1312 static expressionS imm_expr;
1313 static expressionS imm2_expr;
1314 static expressionS offset_expr;
1316 /* Relocs associated with imm_expr and offset_expr. */
1318 static bfd_reloc_code_real_type imm_reloc[3]
1319 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1320 static bfd_reloc_code_real_type offset_reloc[3]
1321 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1323 /* These are set by mips16_ip if an explicit extension is used. */
1325 static bfd_boolean mips16_small, mips16_ext;
1328 /* The pdr segment for per procedure frame/regmask info. Not used for
1331 static segT pdr_seg;
1334 /* The default target format to use. */
1336 #if defined (TE_FreeBSD)
1337 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1338 #elif defined (TE_TMIPS)
1339 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1341 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1345 mips_target_format (void)
1347 switch (OUTPUT_FLAVOR)
1349 case bfd_target_ecoff_flavour:
1350 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1351 case bfd_target_coff_flavour:
1353 case bfd_target_elf_flavour:
1355 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1356 return (target_big_endian
1357 ? "elf32-bigmips-vxworks"
1358 : "elf32-littlemips-vxworks");
1360 return (target_big_endian
1361 ? (HAVE_64BIT_OBJECTS
1362 ? ELF_TARGET ("elf64-", "big")
1364 ? ELF_TARGET ("elf32-n", "big")
1365 : ELF_TARGET ("elf32-", "big")))
1366 : (HAVE_64BIT_OBJECTS
1367 ? ELF_TARGET ("elf64-", "little")
1369 ? ELF_TARGET ("elf32-n", "little")
1370 : ELF_TARGET ("elf32-", "little"))));
1377 /* Return the length of instruction INSN. */
1379 static inline unsigned int
1380 insn_length (const struct mips_cl_insn *insn)
1382 if (!mips_opts.mips16)
1384 return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2;
1387 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1390 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1395 insn->use_extend = FALSE;
1397 insn->insn_opcode = mo->match;
1400 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1401 insn->fixp[i] = NULL;
1402 insn->fixed_p = (mips_opts.noreorder > 0);
1403 insn->noreorder_p = (mips_opts.noreorder > 0);
1404 insn->mips16_absolute_jump_p = 0;
1405 insn->complete_p = 0;
1408 /* Record the current MIPS16 mode in now_seg. */
1411 mips_record_mips16_mode (void)
1413 segment_info_type *si;
1415 si = seg_info (now_seg);
1416 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
1417 si->tc_segment_info_data.mips16 = mips_opts.mips16;
1420 /* Install INSN at the location specified by its "frag" and "where" fields. */
1423 install_insn (const struct mips_cl_insn *insn)
1425 char *f = insn->frag->fr_literal + insn->where;
1426 if (!mips_opts.mips16)
1427 md_number_to_chars (f, insn->insn_opcode, 4);
1428 else if (insn->mips16_absolute_jump_p)
1430 md_number_to_chars (f, insn->insn_opcode >> 16, 2);
1431 md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2);
1435 if (insn->use_extend)
1437 md_number_to_chars (f, 0xf000 | insn->extend, 2);
1440 md_number_to_chars (f, insn->insn_opcode, 2);
1442 mips_record_mips16_mode ();
1445 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1446 and install the opcode in the new location. */
1449 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
1454 insn->where = where;
1455 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1456 if (insn->fixp[i] != NULL)
1458 insn->fixp[i]->fx_frag = frag;
1459 insn->fixp[i]->fx_where = where;
1461 install_insn (insn);
1464 /* Add INSN to the end of the output. */
1467 add_fixed_insn (struct mips_cl_insn *insn)
1469 char *f = frag_more (insn_length (insn));
1470 move_insn (insn, frag_now, f - frag_now->fr_literal);
1473 /* Start a variant frag and move INSN to the start of the variant part,
1474 marking it as fixed. The other arguments are as for frag_var. */
1477 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
1478 relax_substateT subtype, symbolS *symbol, offsetT offset)
1480 frag_grow (max_chars);
1481 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
1483 frag_var (rs_machine_dependent, max_chars, var,
1484 subtype, symbol, offset, NULL);
1487 /* Insert N copies of INSN into the history buffer, starting at
1488 position FIRST. Neither FIRST nor N need to be clipped. */
1491 insert_into_history (unsigned int first, unsigned int n,
1492 const struct mips_cl_insn *insn)
1494 if (mips_relax.sequence != 2)
1498 for (i = ARRAY_SIZE (history); i-- > first;)
1500 history[i] = history[i - n];
1506 /* Emit a nop instruction, recording it in the history buffer. */
1511 add_fixed_insn (NOP_INSN);
1512 insert_into_history (0, 1, NOP_INSN);
1515 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1516 the idea is to make it obvious at a glance that each errata is
1520 init_vr4120_conflicts (void)
1522 #define CONFLICT(FIRST, SECOND) \
1523 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1525 /* Errata 21 - [D]DIV[U] after [D]MACC */
1526 CONFLICT (MACC, DIV);
1527 CONFLICT (DMACC, DIV);
1529 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1530 CONFLICT (DMULT, DMULT);
1531 CONFLICT (DMULT, DMACC);
1532 CONFLICT (DMACC, DMULT);
1533 CONFLICT (DMACC, DMACC);
1535 /* Errata 24 - MT{LO,HI} after [D]MACC */
1536 CONFLICT (MACC, MTHILO);
1537 CONFLICT (DMACC, MTHILO);
1539 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1540 instruction is executed immediately after a MACC or DMACC
1541 instruction, the result of [either instruction] is incorrect." */
1542 CONFLICT (MACC, MULT);
1543 CONFLICT (MACC, DMULT);
1544 CONFLICT (DMACC, MULT);
1545 CONFLICT (DMACC, DMULT);
1547 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1548 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1549 DDIV or DDIVU instruction, the result of the MACC or
1550 DMACC instruction is incorrect.". */
1551 CONFLICT (DMULT, MACC);
1552 CONFLICT (DMULT, DMACC);
1553 CONFLICT (DIV, MACC);
1554 CONFLICT (DIV, DMACC);
1564 #define RTYPE_MASK 0x1ff00
1565 #define RTYPE_NUM 0x00100
1566 #define RTYPE_FPU 0x00200
1567 #define RTYPE_FCC 0x00400
1568 #define RTYPE_VEC 0x00800
1569 #define RTYPE_GP 0x01000
1570 #define RTYPE_CP0 0x02000
1571 #define RTYPE_PC 0x04000
1572 #define RTYPE_ACC 0x08000
1573 #define RTYPE_CCC 0x10000
1574 #define RNUM_MASK 0x000ff
1575 #define RWARN 0x80000
1577 #define GENERIC_REGISTER_NUMBERS \
1578 {"$0", RTYPE_NUM | 0}, \
1579 {"$1", RTYPE_NUM | 1}, \
1580 {"$2", RTYPE_NUM | 2}, \
1581 {"$3", RTYPE_NUM | 3}, \
1582 {"$4", RTYPE_NUM | 4}, \
1583 {"$5", RTYPE_NUM | 5}, \
1584 {"$6", RTYPE_NUM | 6}, \
1585 {"$7", RTYPE_NUM | 7}, \
1586 {"$8", RTYPE_NUM | 8}, \
1587 {"$9", RTYPE_NUM | 9}, \
1588 {"$10", RTYPE_NUM | 10}, \
1589 {"$11", RTYPE_NUM | 11}, \
1590 {"$12", RTYPE_NUM | 12}, \
1591 {"$13", RTYPE_NUM | 13}, \
1592 {"$14", RTYPE_NUM | 14}, \
1593 {"$15", RTYPE_NUM | 15}, \
1594 {"$16", RTYPE_NUM | 16}, \
1595 {"$17", RTYPE_NUM | 17}, \
1596 {"$18", RTYPE_NUM | 18}, \
1597 {"$19", RTYPE_NUM | 19}, \
1598 {"$20", RTYPE_NUM | 20}, \
1599 {"$21", RTYPE_NUM | 21}, \
1600 {"$22", RTYPE_NUM | 22}, \
1601 {"$23", RTYPE_NUM | 23}, \
1602 {"$24", RTYPE_NUM | 24}, \
1603 {"$25", RTYPE_NUM | 25}, \
1604 {"$26", RTYPE_NUM | 26}, \
1605 {"$27", RTYPE_NUM | 27}, \
1606 {"$28", RTYPE_NUM | 28}, \
1607 {"$29", RTYPE_NUM | 29}, \
1608 {"$30", RTYPE_NUM | 30}, \
1609 {"$31", RTYPE_NUM | 31}
1611 #define FPU_REGISTER_NAMES \
1612 {"$f0", RTYPE_FPU | 0}, \
1613 {"$f1", RTYPE_FPU | 1}, \
1614 {"$f2", RTYPE_FPU | 2}, \
1615 {"$f3", RTYPE_FPU | 3}, \
1616 {"$f4", RTYPE_FPU | 4}, \
1617 {"$f5", RTYPE_FPU | 5}, \
1618 {"$f6", RTYPE_FPU | 6}, \
1619 {"$f7", RTYPE_FPU | 7}, \
1620 {"$f8", RTYPE_FPU | 8}, \
1621 {"$f9", RTYPE_FPU | 9}, \
1622 {"$f10", RTYPE_FPU | 10}, \
1623 {"$f11", RTYPE_FPU | 11}, \
1624 {"$f12", RTYPE_FPU | 12}, \
1625 {"$f13", RTYPE_FPU | 13}, \
1626 {"$f14", RTYPE_FPU | 14}, \
1627 {"$f15", RTYPE_FPU | 15}, \
1628 {"$f16", RTYPE_FPU | 16}, \
1629 {"$f17", RTYPE_FPU | 17}, \
1630 {"$f18", RTYPE_FPU | 18}, \
1631 {"$f19", RTYPE_FPU | 19}, \
1632 {"$f20", RTYPE_FPU | 20}, \
1633 {"$f21", RTYPE_FPU | 21}, \
1634 {"$f22", RTYPE_FPU | 22}, \
1635 {"$f23", RTYPE_FPU | 23}, \
1636 {"$f24", RTYPE_FPU | 24}, \
1637 {"$f25", RTYPE_FPU | 25}, \
1638 {"$f26", RTYPE_FPU | 26}, \
1639 {"$f27", RTYPE_FPU | 27}, \
1640 {"$f28", RTYPE_FPU | 28}, \
1641 {"$f29", RTYPE_FPU | 29}, \
1642 {"$f30", RTYPE_FPU | 30}, \
1643 {"$f31", RTYPE_FPU | 31}
1645 #define FPU_CONDITION_CODE_NAMES \
1646 {"$fcc0", RTYPE_FCC | 0}, \
1647 {"$fcc1", RTYPE_FCC | 1}, \
1648 {"$fcc2", RTYPE_FCC | 2}, \
1649 {"$fcc3", RTYPE_FCC | 3}, \
1650 {"$fcc4", RTYPE_FCC | 4}, \
1651 {"$fcc5", RTYPE_FCC | 5}, \
1652 {"$fcc6", RTYPE_FCC | 6}, \
1653 {"$fcc7", RTYPE_FCC | 7}
1655 #define COPROC_CONDITION_CODE_NAMES \
1656 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1657 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1658 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1659 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1660 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1661 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1662 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1663 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1665 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1666 {"$a4", RTYPE_GP | 8}, \
1667 {"$a5", RTYPE_GP | 9}, \
1668 {"$a6", RTYPE_GP | 10}, \
1669 {"$a7", RTYPE_GP | 11}, \
1670 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1671 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1672 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1673 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1674 {"$t0", RTYPE_GP | 12}, \
1675 {"$t1", RTYPE_GP | 13}, \
1676 {"$t2", RTYPE_GP | 14}, \
1677 {"$t3", RTYPE_GP | 15}
1679 #define O32_SYMBOLIC_REGISTER_NAMES \
1680 {"$t0", RTYPE_GP | 8}, \
1681 {"$t1", RTYPE_GP | 9}, \
1682 {"$t2", RTYPE_GP | 10}, \
1683 {"$t3", RTYPE_GP | 11}, \
1684 {"$t4", RTYPE_GP | 12}, \
1685 {"$t5", RTYPE_GP | 13}, \
1686 {"$t6", RTYPE_GP | 14}, \
1687 {"$t7", RTYPE_GP | 15}, \
1688 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1689 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1690 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1691 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1693 /* Remaining symbolic register names */
1694 #define SYMBOLIC_REGISTER_NAMES \
1695 {"$zero", RTYPE_GP | 0}, \
1696 {"$at", RTYPE_GP | 1}, \
1697 {"$AT", RTYPE_GP | 1}, \
1698 {"$v0", RTYPE_GP | 2}, \
1699 {"$v1", RTYPE_GP | 3}, \
1700 {"$a0", RTYPE_GP | 4}, \
1701 {"$a1", RTYPE_GP | 5}, \
1702 {"$a2", RTYPE_GP | 6}, \
1703 {"$a3", RTYPE_GP | 7}, \
1704 {"$s0", RTYPE_GP | 16}, \
1705 {"$s1", RTYPE_GP | 17}, \
1706 {"$s2", RTYPE_GP | 18}, \
1707 {"$s3", RTYPE_GP | 19}, \
1708 {"$s4", RTYPE_GP | 20}, \
1709 {"$s5", RTYPE_GP | 21}, \
1710 {"$s6", RTYPE_GP | 22}, \
1711 {"$s7", RTYPE_GP | 23}, \
1712 {"$t8", RTYPE_GP | 24}, \
1713 {"$t9", RTYPE_GP | 25}, \
1714 {"$k0", RTYPE_GP | 26}, \
1715 {"$kt0", RTYPE_GP | 26}, \
1716 {"$k1", RTYPE_GP | 27}, \
1717 {"$kt1", RTYPE_GP | 27}, \
1718 {"$gp", RTYPE_GP | 28}, \
1719 {"$sp", RTYPE_GP | 29}, \
1720 {"$s8", RTYPE_GP | 30}, \
1721 {"$fp", RTYPE_GP | 30}, \
1722 {"$ra", RTYPE_GP | 31}
1724 #define MIPS16_SPECIAL_REGISTER_NAMES \
1725 {"$pc", RTYPE_PC | 0}
1727 #define MDMX_VECTOR_REGISTER_NAMES \
1728 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
1729 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
1730 {"$v2", RTYPE_VEC | 2}, \
1731 {"$v3", RTYPE_VEC | 3}, \
1732 {"$v4", RTYPE_VEC | 4}, \
1733 {"$v5", RTYPE_VEC | 5}, \
1734 {"$v6", RTYPE_VEC | 6}, \
1735 {"$v7", RTYPE_VEC | 7}, \
1736 {"$v8", RTYPE_VEC | 8}, \
1737 {"$v9", RTYPE_VEC | 9}, \
1738 {"$v10", RTYPE_VEC | 10}, \
1739 {"$v11", RTYPE_VEC | 11}, \
1740 {"$v12", RTYPE_VEC | 12}, \
1741 {"$v13", RTYPE_VEC | 13}, \
1742 {"$v14", RTYPE_VEC | 14}, \
1743 {"$v15", RTYPE_VEC | 15}, \
1744 {"$v16", RTYPE_VEC | 16}, \
1745 {"$v17", RTYPE_VEC | 17}, \
1746 {"$v18", RTYPE_VEC | 18}, \
1747 {"$v19", RTYPE_VEC | 19}, \
1748 {"$v20", RTYPE_VEC | 20}, \
1749 {"$v21", RTYPE_VEC | 21}, \
1750 {"$v22", RTYPE_VEC | 22}, \
1751 {"$v23", RTYPE_VEC | 23}, \
1752 {"$v24", RTYPE_VEC | 24}, \
1753 {"$v25", RTYPE_VEC | 25}, \
1754 {"$v26", RTYPE_VEC | 26}, \
1755 {"$v27", RTYPE_VEC | 27}, \
1756 {"$v28", RTYPE_VEC | 28}, \
1757 {"$v29", RTYPE_VEC | 29}, \
1758 {"$v30", RTYPE_VEC | 30}, \
1759 {"$v31", RTYPE_VEC | 31}
1761 #define MIPS_DSP_ACCUMULATOR_NAMES \
1762 {"$ac0", RTYPE_ACC | 0}, \
1763 {"$ac1", RTYPE_ACC | 1}, \
1764 {"$ac2", RTYPE_ACC | 2}, \
1765 {"$ac3", RTYPE_ACC | 3}
1767 static const struct regname reg_names[] = {
1768 GENERIC_REGISTER_NUMBERS,
1770 FPU_CONDITION_CODE_NAMES,
1771 COPROC_CONDITION_CODE_NAMES,
1773 /* The $txx registers depends on the abi,
1774 these will be added later into the symbol table from
1775 one of the tables below once mips_abi is set after
1776 parsing of arguments from the command line. */
1777 SYMBOLIC_REGISTER_NAMES,
1779 MIPS16_SPECIAL_REGISTER_NAMES,
1780 MDMX_VECTOR_REGISTER_NAMES,
1781 MIPS_DSP_ACCUMULATOR_NAMES,
1785 static const struct regname reg_names_o32[] = {
1786 O32_SYMBOLIC_REGISTER_NAMES,
1790 static const struct regname reg_names_n32n64[] = {
1791 N32N64_SYMBOLIC_REGISTER_NAMES,
1796 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
1803 /* Find end of name. */
1805 if (is_name_beginner (*e))
1807 while (is_part_of_name (*e))
1810 /* Terminate name. */
1814 /* Look for a register symbol. */
1815 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
1817 int r = S_GET_VALUE (symbolP);
1819 reg = r & RNUM_MASK;
1820 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
1821 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
1822 reg = (r & RNUM_MASK) - 2;
1824 /* Else see if this is a register defined in an itbl entry. */
1825 else if ((types & RTYPE_GP) && itbl_have_entries)
1832 if (itbl_get_reg_val (n, &r))
1833 reg = r & RNUM_MASK;
1836 /* Advance to next token if a register was recognised. */
1839 else if (types & RWARN)
1840 as_warn (_("Unrecognized register name `%s'"), *s);
1848 /* Return TRUE if opcode MO is valid on the currently selected ISA and
1849 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
1852 is_opcode_valid (const struct mips_opcode *mo)
1854 int isa = mips_opts.isa;
1857 if (mips_opts.ase_mdmx)
1859 if (mips_opts.ase_dsp)
1861 if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
1863 if (mips_opts.ase_dspr2)
1865 if (mips_opts.ase_mt)
1867 if (mips_opts.ase_mips3d)
1869 if (mips_opts.ase_smartmips)
1870 isa |= INSN_SMARTMIPS;
1872 /* Don't accept instructions based on the ISA if the CPU does not implement
1873 all the coprocessor insns. */
1874 if (NO_ISA_COP (mips_opts.arch)
1875 && COP_INSN (mo->pinfo))
1878 if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch))
1881 /* Check whether the instruction or macro requires single-precision or
1882 double-precision floating-point support. Note that this information is
1883 stored differently in the opcode table for insns and macros. */
1884 if (mo->pinfo == INSN_MACRO)
1886 fp_s = mo->pinfo2 & INSN2_M_FP_S;
1887 fp_d = mo->pinfo2 & INSN2_M_FP_D;
1891 fp_s = mo->pinfo & FP_S;
1892 fp_d = mo->pinfo & FP_D;
1895 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
1898 if (fp_s && mips_opts.soft_float)
1904 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
1905 selected ISA and architecture. */
1908 is_opcode_valid_16 (const struct mips_opcode *mo)
1910 return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE;
1913 /* This function is called once, at assembler startup time. It should set up
1914 all the tables, etc. that the MD part of the assembler will need. */
1919 const char *retval = NULL;
1923 if (mips_pic != NO_PIC)
1925 if (g_switch_seen && g_switch_value != 0)
1926 as_bad (_("-G may not be used in position-independent code"));
1930 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
1931 as_warn (_("Could not set architecture and machine"));
1933 op_hash = hash_new ();
1935 for (i = 0; i < NUMOPCODES;)
1937 const char *name = mips_opcodes[i].name;
1939 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
1942 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1943 mips_opcodes[i].name, retval);
1944 /* Probably a memory allocation problem? Give up now. */
1945 as_fatal (_("Broken assembler. No assembly attempted."));
1949 if (mips_opcodes[i].pinfo != INSN_MACRO)
1951 if (!validate_mips_insn (&mips_opcodes[i]))
1953 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
1955 create_insn (&nop_insn, mips_opcodes + i);
1956 if (mips_fix_loongson2f_nop)
1957 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
1958 nop_insn.fixed_p = 1;
1963 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1966 mips16_op_hash = hash_new ();
1969 while (i < bfd_mips16_num_opcodes)
1971 const char *name = mips16_opcodes[i].name;
1973 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
1975 as_fatal (_("internal: can't hash `%s': %s"),
1976 mips16_opcodes[i].name, retval);
1979 if (mips16_opcodes[i].pinfo != INSN_MACRO
1980 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1981 != mips16_opcodes[i].match))
1983 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1984 mips16_opcodes[i].name, mips16_opcodes[i].args);
1987 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
1989 create_insn (&mips16_nop_insn, mips16_opcodes + i);
1990 mips16_nop_insn.fixed_p = 1;
1994 while (i < bfd_mips16_num_opcodes
1995 && strcmp (mips16_opcodes[i].name, name) == 0);
1999 as_fatal (_("Broken assembler. No assembly attempted."));
2001 /* We add all the general register names to the symbol table. This
2002 helps us detect invalid uses of them. */
2003 for (i = 0; reg_names[i].name; i++)
2004 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
2005 reg_names[i].num, /* & RNUM_MASK, */
2006 &zero_address_frag));
2008 for (i = 0; reg_names_n32n64[i].name; i++)
2009 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
2010 reg_names_n32n64[i].num, /* & RNUM_MASK, */
2011 &zero_address_frag));
2013 for (i = 0; reg_names_o32[i].name; i++)
2014 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
2015 reg_names_o32[i].num, /* & RNUM_MASK, */
2016 &zero_address_frag));
2018 mips_no_prev_insn ();
2021 mips_cprmask[0] = 0;
2022 mips_cprmask[1] = 0;
2023 mips_cprmask[2] = 0;
2024 mips_cprmask[3] = 0;
2026 /* set the default alignment for the text section (2**2) */
2027 record_alignment (text_section, 2);
2029 bfd_set_gp_size (stdoutput, g_switch_value);
2034 /* On a native system other than VxWorks, sections must be aligned
2035 to 16 byte boundaries. When configured for an embedded ELF
2036 target, we don't bother. */
2037 if (strncmp (TARGET_OS, "elf", 3) != 0
2038 && strncmp (TARGET_OS, "vxworks", 7) != 0)
2040 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
2041 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
2042 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
2045 /* Create a .reginfo section for register masks and a .mdebug
2046 section for debugging information. */
2054 subseg = now_subseg;
2056 /* The ABI says this section should be loaded so that the
2057 running program can access it. However, we don't load it
2058 if we are configured for an embedded target */
2059 flags = SEC_READONLY | SEC_DATA;
2060 if (strncmp (TARGET_OS, "elf", 3) != 0)
2061 flags |= SEC_ALLOC | SEC_LOAD;
2063 if (mips_abi != N64_ABI)
2065 sec = subseg_new (".reginfo", (subsegT) 0);
2067 bfd_set_section_flags (stdoutput, sec, flags);
2068 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
2070 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
2074 /* The 64-bit ABI uses a .MIPS.options section rather than
2075 .reginfo section. */
2076 sec = subseg_new (".MIPS.options", (subsegT) 0);
2077 bfd_set_section_flags (stdoutput, sec, flags);
2078 bfd_set_section_alignment (stdoutput, sec, 3);
2080 /* Set up the option header. */
2082 Elf_Internal_Options opthdr;
2085 opthdr.kind = ODK_REGINFO;
2086 opthdr.size = (sizeof (Elf_External_Options)
2087 + sizeof (Elf64_External_RegInfo));
2090 f = frag_more (sizeof (Elf_External_Options));
2091 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2092 (Elf_External_Options *) f);
2094 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2098 if (ECOFF_DEBUGGING)
2100 sec = subseg_new (".mdebug", (subsegT) 0);
2101 (void) bfd_set_section_flags (stdoutput, sec,
2102 SEC_HAS_CONTENTS | SEC_READONLY);
2103 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2105 else if (mips_flag_pdr)
2107 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2108 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2109 SEC_READONLY | SEC_RELOC
2111 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2114 subseg_set (seg, subseg);
2117 #endif /* OBJ_ELF */
2119 if (! ECOFF_DEBUGGING)
2122 if (mips_fix_vr4120)
2123 init_vr4120_conflicts ();
2129 mips_emit_delays ();
2130 if (! ECOFF_DEBUGGING)
2135 md_assemble (char *str)
2137 struct mips_cl_insn insn;
2138 bfd_reloc_code_real_type unused_reloc[3]
2139 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2141 imm_expr.X_op = O_absent;
2142 imm2_expr.X_op = O_absent;
2143 offset_expr.X_op = O_absent;
2144 imm_reloc[0] = BFD_RELOC_UNUSED;
2145 imm_reloc[1] = BFD_RELOC_UNUSED;
2146 imm_reloc[2] = BFD_RELOC_UNUSED;
2147 offset_reloc[0] = BFD_RELOC_UNUSED;
2148 offset_reloc[1] = BFD_RELOC_UNUSED;
2149 offset_reloc[2] = BFD_RELOC_UNUSED;
2151 if (mips_opts.mips16)
2152 mips16_ip (str, &insn);
2155 mips_ip (str, &insn);
2156 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2157 str, insn.insn_opcode));
2162 as_bad ("%s `%s'", insn_error, str);
2166 if (insn.insn_mo->pinfo == INSN_MACRO)
2169 if (mips_opts.mips16)
2170 mips16_macro (&insn);
2177 if (imm_expr.X_op != O_absent)
2178 append_insn (&insn, &imm_expr, imm_reloc);
2179 else if (offset_expr.X_op != O_absent)
2180 append_insn (&insn, &offset_expr, offset_reloc);
2182 append_insn (&insn, NULL, unused_reloc);
2186 /* Convenience functions for abstracting away the differences between
2187 MIPS16 and non-MIPS16 relocations. */
2189 static inline bfd_boolean
2190 mips16_reloc_p (bfd_reloc_code_real_type reloc)
2194 case BFD_RELOC_MIPS16_JMP:
2195 case BFD_RELOC_MIPS16_GPREL:
2196 case BFD_RELOC_MIPS16_GOT16:
2197 case BFD_RELOC_MIPS16_CALL16:
2198 case BFD_RELOC_MIPS16_HI16_S:
2199 case BFD_RELOC_MIPS16_HI16:
2200 case BFD_RELOC_MIPS16_LO16:
2208 static inline bfd_boolean
2209 got16_reloc_p (bfd_reloc_code_real_type reloc)
2211 return reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16;
2214 static inline bfd_boolean
2215 hi16_reloc_p (bfd_reloc_code_real_type reloc)
2217 return reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S;
2220 static inline bfd_boolean
2221 lo16_reloc_p (bfd_reloc_code_real_type reloc)
2223 return reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16;
2226 /* Return true if the given relocation might need a matching %lo().
2227 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2228 need a matching %lo() when applied to local symbols. */
2230 static inline bfd_boolean
2231 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
2233 return (HAVE_IN_PLACE_ADDENDS
2234 && (hi16_reloc_p (reloc)
2235 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2236 all GOT16 relocations evaluate to "G". */
2237 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
2240 /* Return the type of %lo() reloc needed by RELOC, given that
2241 reloc_needs_lo_p. */
2243 static inline bfd_reloc_code_real_type
2244 matching_lo_reloc (bfd_reloc_code_real_type reloc)
2246 return mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 : BFD_RELOC_LO16;
2249 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2252 static inline bfd_boolean
2253 fixup_has_matching_lo_p (fixS *fixp)
2255 return (fixp->fx_next != NULL
2256 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
2257 && fixp->fx_addsy == fixp->fx_next->fx_addsy
2258 && fixp->fx_offset == fixp->fx_next->fx_offset);
2261 /* This function returns true if modifying a register requires a
2265 reg_needs_delay (unsigned int reg)
2267 unsigned long prev_pinfo;
2269 prev_pinfo = history[0].insn_mo->pinfo;
2270 if (! mips_opts.noreorder
2271 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2272 && ! gpr_interlocks)
2273 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
2274 && ! cop_interlocks)))
2276 /* A load from a coprocessor or from memory. All load delays
2277 delay the use of general register rt for one instruction. */
2278 /* Itbl support may require additional care here. */
2279 know (prev_pinfo & INSN_WRITE_GPR_T);
2280 if (reg == EXTRACT_OPERAND (RT, history[0]))
2287 /* Move all labels in insn_labels to the current insertion point. */
2290 mips_move_labels (void)
2292 segment_info_type *si = seg_info (now_seg);
2293 struct insn_label_list *l;
2296 for (l = si->label_list; l != NULL; l = l->next)
2298 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
2299 symbol_set_frag (l->label, frag_now);
2300 val = (valueT) frag_now_fix ();
2301 /* mips16 text labels are stored as odd. */
2302 if (mips_opts.mips16)
2304 S_SET_VALUE (l->label, val);
2309 s_is_linkonce (symbolS *sym, segT from_seg)
2311 bfd_boolean linkonce = FALSE;
2312 segT symseg = S_GET_SEGMENT (sym);
2314 if (symseg != from_seg && !S_IS_LOCAL (sym))
2316 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
2319 /* The GNU toolchain uses an extension for ELF: a section
2320 beginning with the magic string .gnu.linkonce is a
2321 linkonce section. */
2322 if (strncmp (segment_name (symseg), ".gnu.linkonce",
2323 sizeof ".gnu.linkonce" - 1) == 0)
2330 /* Mark instruction labels in mips16 mode. This permits the linker to
2331 handle them specially, such as generating jalx instructions when
2332 needed. We also make them odd for the duration of the assembly, in
2333 order to generate the right sort of code. We will make them even
2334 in the adjust_symtab routine, while leaving them marked. This is
2335 convenient for the debugger and the disassembler. The linker knows
2336 to make them odd again. */
2339 mips16_mark_labels (void)
2341 segment_info_type *si = seg_info (now_seg);
2342 struct insn_label_list *l;
2344 if (!mips_opts.mips16)
2347 for (l = si->label_list; l != NULL; l = l->next)
2349 symbolS *label = l->label;
2351 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2353 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
2355 if ((S_GET_VALUE (label) & 1) == 0
2356 /* Don't adjust the address if the label is global or weak, or
2357 in a link-once section, since we'll be emitting symbol reloc
2358 references to it which will be patched up by the linker, and
2359 the final value of the symbol may or may not be MIPS16. */
2360 && ! S_IS_WEAK (label)
2361 && ! S_IS_EXTERNAL (label)
2362 && ! s_is_linkonce (label, now_seg))
2363 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
2367 /* End the current frag. Make it a variant frag and record the
2371 relax_close_frag (void)
2373 mips_macro_warning.first_frag = frag_now;
2374 frag_var (rs_machine_dependent, 0, 0,
2375 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
2376 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
2378 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
2379 mips_relax.first_fixup = 0;
2382 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2383 See the comment above RELAX_ENCODE for more details. */
2386 relax_start (symbolS *symbol)
2388 gas_assert (mips_relax.sequence == 0);
2389 mips_relax.sequence = 1;
2390 mips_relax.symbol = symbol;
2393 /* Start generating the second version of a relaxable sequence.
2394 See the comment above RELAX_ENCODE for more details. */
2399 gas_assert (mips_relax.sequence == 1);
2400 mips_relax.sequence = 2;
2403 /* End the current relaxable sequence. */
2408 gas_assert (mips_relax.sequence == 2);
2409 relax_close_frag ();
2410 mips_relax.sequence = 0;
2413 /* Return the mask of core registers that IP reads. */
2416 gpr_read_mask (const struct mips_cl_insn *ip)
2418 unsigned long pinfo, pinfo2;
2422 pinfo = ip->insn_mo->pinfo;
2423 pinfo2 = ip->insn_mo->pinfo2;
2424 if (mips_opts.mips16)
2426 if (pinfo & MIPS16_INSN_READ_X)
2427 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
2428 if (pinfo & MIPS16_INSN_READ_Y)
2429 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
2430 if (pinfo & MIPS16_INSN_READ_T)
2432 if (pinfo & MIPS16_INSN_READ_SP)
2434 if (pinfo & MIPS16_INSN_READ_31)
2436 if (pinfo & MIPS16_INSN_READ_Z)
2437 mask |= 1 << (mips16_to_32_reg_map
2438 [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]);
2439 if (pinfo & MIPS16_INSN_READ_GPR_X)
2440 mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
2444 if (pinfo2 & INSN2_READ_GPR_D)
2445 mask |= 1 << EXTRACT_OPERAND (RD, *ip);
2446 if (pinfo & INSN_READ_GPR_T)
2447 mask |= 1 << EXTRACT_OPERAND (RT, *ip);
2448 if (pinfo & INSN_READ_GPR_S)
2449 mask |= 1 << EXTRACT_OPERAND (RS, *ip);
2450 if (pinfo2 & INSN2_READ_GPR_Z)
2451 mask |= 1 << EXTRACT_OPERAND (RZ, *ip);
2453 /* Don't include register 0. */
2457 /* Return the mask of core registers that IP writes. */
2460 gpr_write_mask (const struct mips_cl_insn *ip)
2462 unsigned long pinfo, pinfo2;
2466 pinfo = ip->insn_mo->pinfo;
2467 pinfo2 = ip->insn_mo->pinfo2;
2468 if (mips_opts.mips16)
2470 if (pinfo & MIPS16_INSN_WRITE_X)
2471 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
2472 if (pinfo & MIPS16_INSN_WRITE_Y)
2473 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
2474 if (pinfo & MIPS16_INSN_WRITE_Z)
2475 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)];
2476 if (pinfo & MIPS16_INSN_WRITE_T)
2478 if (pinfo & MIPS16_INSN_WRITE_SP)
2480 if (pinfo & MIPS16_INSN_WRITE_31)
2482 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2483 mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2487 if (pinfo & INSN_WRITE_GPR_D)
2488 mask |= 1 << EXTRACT_OPERAND (RD, *ip);
2489 if (pinfo & INSN_WRITE_GPR_T)
2490 mask |= 1 << EXTRACT_OPERAND (RT, *ip);
2491 if (pinfo & INSN_WRITE_GPR_31)
2493 if (pinfo2 & INSN2_WRITE_GPR_Z)
2494 mask |= 1 << EXTRACT_OPERAND (RZ, *ip);
2496 /* Don't include register 0. */
2500 /* Return the mask of floating-point registers that IP reads. */
2503 fpr_read_mask (const struct mips_cl_insn *ip)
2505 unsigned long pinfo, pinfo2;
2509 pinfo = ip->insn_mo->pinfo;
2510 pinfo2 = ip->insn_mo->pinfo2;
2511 if (!mips_opts.mips16)
2513 if (pinfo & INSN_READ_FPR_S)
2514 mask |= 1 << EXTRACT_OPERAND (FS, *ip);
2515 if (pinfo & INSN_READ_FPR_T)
2516 mask |= 1 << EXTRACT_OPERAND (FT, *ip);
2517 if (pinfo & INSN_READ_FPR_R)
2518 mask |= 1 << EXTRACT_OPERAND (FR, *ip);
2519 if (pinfo2 & INSN2_READ_FPR_Z)
2520 mask |= 1 << EXTRACT_OPERAND (FZ, *ip);
2522 /* Conservatively treat all operands to an FP_D instruction are doubles.
2523 (This is overly pessimistic for things like cvt.d.s.) */
2524 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
2529 /* Return the mask of floating-point registers that IP writes. */
2532 fpr_write_mask (const struct mips_cl_insn *ip)
2534 unsigned long pinfo, pinfo2;
2538 pinfo = ip->insn_mo->pinfo;
2539 pinfo2 = ip->insn_mo->pinfo2;
2540 if (!mips_opts.mips16)
2542 if (pinfo & INSN_WRITE_FPR_D)
2543 mask |= 1 << EXTRACT_OPERAND (FD, *ip);
2544 if (pinfo & INSN_WRITE_FPR_S)
2545 mask |= 1 << EXTRACT_OPERAND (FS, *ip);
2546 if (pinfo & INSN_WRITE_FPR_T)
2547 mask |= 1 << EXTRACT_OPERAND (FT, *ip);
2548 if (pinfo2 & INSN2_WRITE_FPR_Z)
2549 mask |= 1 << EXTRACT_OPERAND (FZ, *ip);
2551 /* Conservatively treat all operands to an FP_D instruction are doubles.
2552 (This is overly pessimistic for things like cvt.s.d.) */
2553 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
2558 /* Classify an instruction according to the FIX_VR4120_* enumeration.
2559 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
2560 by VR4120 errata. */
2563 classify_vr4120_insn (const char *name)
2565 if (strncmp (name, "macc", 4) == 0)
2566 return FIX_VR4120_MACC;
2567 if (strncmp (name, "dmacc", 5) == 0)
2568 return FIX_VR4120_DMACC;
2569 if (strncmp (name, "mult", 4) == 0)
2570 return FIX_VR4120_MULT;
2571 if (strncmp (name, "dmult", 5) == 0)
2572 return FIX_VR4120_DMULT;
2573 if (strstr (name, "div"))
2574 return FIX_VR4120_DIV;
2575 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
2576 return FIX_VR4120_MTHILO;
2577 return NUM_FIX_VR4120_CLASSES;
2580 #define INSN_ERET 0x42000018
2581 #define INSN_DERET 0x4200001f
2583 /* Return the number of instructions that must separate INSN1 and INSN2,
2584 where INSN1 is the earlier instruction. Return the worst-case value
2585 for any INSN2 if INSN2 is null. */
2588 insns_between (const struct mips_cl_insn *insn1,
2589 const struct mips_cl_insn *insn2)
2591 unsigned long pinfo1, pinfo2;
2594 /* This function needs to know which pinfo flags are set for INSN2
2595 and which registers INSN2 uses. The former is stored in PINFO2 and
2596 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
2597 will have every flag set and INSN2_USES_GPR will always return true. */
2598 pinfo1 = insn1->insn_mo->pinfo;
2599 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
2601 #define INSN2_USES_GPR(REG) \
2602 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
2604 /* For most targets, write-after-read dependencies on the HI and LO
2605 registers must be separated by at least two instructions. */
2606 if (!hilo_interlocks)
2608 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
2610 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
2614 /* If we're working around r7000 errata, there must be two instructions
2615 between an mfhi or mflo and any instruction that uses the result. */
2616 if (mips_7000_hilo_fix
2617 && MF_HILO_INSN (pinfo1)
2618 && INSN2_USES_GPR (EXTRACT_OPERAND (RD, *insn1)))
2621 /* If we're working around 24K errata, one instruction is required
2622 if an ERET or DERET is followed by a branch instruction. */
2625 if (insn1->insn_opcode == INSN_ERET
2626 || insn1->insn_opcode == INSN_DERET)
2629 || insn2->insn_opcode == INSN_ERET
2630 || insn2->insn_opcode == INSN_DERET
2631 || (insn2->insn_mo->pinfo
2632 & (INSN_UNCOND_BRANCH_DELAY
2633 | INSN_COND_BRANCH_DELAY
2634 | INSN_COND_BRANCH_LIKELY)) != 0)
2639 /* If working around VR4120 errata, check for combinations that need
2640 a single intervening instruction. */
2641 if (mips_fix_vr4120)
2643 unsigned int class1, class2;
2645 class1 = classify_vr4120_insn (insn1->insn_mo->name);
2646 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
2650 class2 = classify_vr4120_insn (insn2->insn_mo->name);
2651 if (vr4120_conflicts[class1] & (1 << class2))
2656 if (!mips_opts.mips16)
2658 /* Check for GPR or coprocessor load delays. All such delays
2659 are on the RT register. */
2660 /* Itbl support may require additional care here. */
2661 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
2662 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
2664 know (pinfo1 & INSN_WRITE_GPR_T);
2665 if (INSN2_USES_GPR (EXTRACT_OPERAND (RT, *insn1)))
2669 /* Check for generic coprocessor hazards.
2671 This case is not handled very well. There is no special
2672 knowledge of CP0 handling, and the coprocessors other than
2673 the floating point unit are not distinguished at all. */
2674 /* Itbl support may require additional care here. FIXME!
2675 Need to modify this to include knowledge about
2676 user specified delays! */
2677 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
2678 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
2680 /* Handle cases where INSN1 writes to a known general coprocessor
2681 register. There must be a one instruction delay before INSN2
2682 if INSN2 reads that register, otherwise no delay is needed. */
2683 mask = fpr_write_mask (insn1);
2686 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
2691 /* Read-after-write dependencies on the control registers
2692 require a two-instruction gap. */
2693 if ((pinfo1 & INSN_WRITE_COND_CODE)
2694 && (pinfo2 & INSN_READ_COND_CODE))
2697 /* We don't know exactly what INSN1 does. If INSN2 is
2698 also a coprocessor instruction, assume there must be
2699 a one instruction gap. */
2700 if (pinfo2 & INSN_COP)
2705 /* Check for read-after-write dependencies on the coprocessor
2706 control registers in cases where INSN1 does not need a general
2707 coprocessor delay. This means that INSN1 is a floating point
2708 comparison instruction. */
2709 /* Itbl support may require additional care here. */
2710 else if (!cop_interlocks
2711 && (pinfo1 & INSN_WRITE_COND_CODE)
2712 && (pinfo2 & INSN_READ_COND_CODE))
2716 #undef INSN2_USES_GPR
2721 /* Return the number of nops that would be needed to work around the
2722 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2723 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
2724 that are contained within the first IGNORE instructions of HIST. */
2727 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
2728 const struct mips_cl_insn *insn)
2733 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2734 are not affected by the errata. */
2736 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
2737 || strcmp (insn->insn_mo->name, "mtlo") == 0
2738 || strcmp (insn->insn_mo->name, "mthi") == 0))
2741 /* Search for the first MFLO or MFHI. */
2742 for (i = 0; i < MAX_VR4130_NOPS; i++)
2743 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
2745 /* Extract the destination register. */
2746 mask = gpr_write_mask (&hist[i]);
2748 /* No nops are needed if INSN reads that register. */
2749 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
2752 /* ...or if any of the intervening instructions do. */
2753 for (j = 0; j < i; j++)
2754 if (gpr_read_mask (&hist[j]) & mask)
2758 return MAX_VR4130_NOPS - i;
2763 #define BASE_REG_EQ(INSN1, INSN2) \
2764 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
2765 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
2767 /* Return the minimum alignment for this store instruction. */
2770 fix_24k_align_to (const struct mips_opcode *mo)
2772 if (strcmp (mo->name, "sh") == 0)
2775 if (strcmp (mo->name, "swc1") == 0
2776 || strcmp (mo->name, "swc2") == 0
2777 || strcmp (mo->name, "sw") == 0
2778 || strcmp (mo->name, "sc") == 0
2779 || strcmp (mo->name, "s.s") == 0)
2782 if (strcmp (mo->name, "sdc1") == 0
2783 || strcmp (mo->name, "sdc2") == 0
2784 || strcmp (mo->name, "s.d") == 0)
2791 struct fix_24k_store_info
2793 /* Immediate offset, if any, for this store instruction. */
2795 /* Alignment required by this store instruction. */
2797 /* True for register offsets. */
2798 int register_offset;
2801 /* Comparison function used by qsort. */
2804 fix_24k_sort (const void *a, const void *b)
2806 const struct fix_24k_store_info *pos1 = a;
2807 const struct fix_24k_store_info *pos2 = b;
2809 return (pos1->off - pos2->off);
2812 /* INSN is a store instruction. Try to record the store information
2813 in STINFO. Return false if the information isn't known. */
2816 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
2817 const struct mips_cl_insn *insn)
2819 /* The instruction must have a known offset. */
2820 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
2823 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
2824 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
2828 /* Return the number of nops that would be needed to work around the 24k
2829 "lost data on stores during refill" errata if instruction INSN
2830 immediately followed the 2 instructions described by HIST.
2831 Ignore hazards that are contained within the first IGNORE
2832 instructions of HIST.
2834 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
2835 for the data cache refills and store data. The following describes
2836 the scenario where the store data could be lost.
2838 * A data cache miss, due to either a load or a store, causing fill
2839 data to be supplied by the memory subsystem
2840 * The first three doublewords of fill data are returned and written
2842 * A sequence of four stores occurs in consecutive cycles around the
2843 final doubleword of the fill:
2847 * Zero, One or more instructions
2850 The four stores A-D must be to different doublewords of the line that
2851 is being filled. The fourth instruction in the sequence above permits
2852 the fill of the final doubleword to be transferred from the FSB into
2853 the cache. In the sequence above, the stores may be either integer
2854 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
2855 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
2856 different doublewords on the line. If the floating point unit is
2857 running in 1:2 mode, it is not possible to create the sequence above
2858 using only floating point store instructions.
2860 In this case, the cache line being filled is incorrectly marked
2861 invalid, thereby losing the data from any store to the line that
2862 occurs between the original miss and the completion of the five
2863 cycle sequence shown above.
2865 The workarounds are:
2867 * Run the data cache in write-through mode.
2868 * Insert a non-store instruction between
2869 Store A and Store B or Store B and Store C. */
2872 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
2873 const struct mips_cl_insn *insn)
2875 struct fix_24k_store_info pos[3];
2876 int align, i, base_offset;
2881 /* If the previous instruction wasn't a store, there's nothing to
2883 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
2886 /* If the instructions after the previous one are unknown, we have
2887 to assume the worst. */
2891 /* Check whether we are dealing with three consecutive stores. */
2892 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
2893 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
2896 /* If we don't know the relationship between the store addresses,
2897 assume the worst. */
2898 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
2899 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
2902 if (!fix_24k_record_store_info (&pos[0], insn)
2903 || !fix_24k_record_store_info (&pos[1], &hist[0])
2904 || !fix_24k_record_store_info (&pos[2], &hist[1]))
2907 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
2909 /* Pick a value of ALIGN and X such that all offsets are adjusted by
2910 X bytes and such that the base register + X is known to be aligned
2913 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
2917 align = pos[0].align_to;
2918 base_offset = pos[0].off;
2919 for (i = 1; i < 3; i++)
2920 if (align < pos[i].align_to)
2922 align = pos[i].align_to;
2923 base_offset = pos[i].off;
2925 for (i = 0; i < 3; i++)
2926 pos[i].off -= base_offset;
2929 pos[0].off &= ~align + 1;
2930 pos[1].off &= ~align + 1;
2931 pos[2].off &= ~align + 1;
2933 /* If any two stores write to the same chunk, they also write to the
2934 same doubleword. The offsets are still sorted at this point. */
2935 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
2938 /* A range of at least 9 bytes is needed for the stores to be in
2939 non-overlapping doublewords. */
2940 if (pos[2].off - pos[0].off <= 8)
2943 if (pos[2].off - pos[1].off >= 24
2944 || pos[1].off - pos[0].off >= 24
2945 || pos[2].off - pos[0].off >= 32)
2951 /* Return the number of nops that would be needed if instruction INSN
2952 immediately followed the MAX_NOPS instructions given by HIST,
2953 where HIST[0] is the most recent instruction. Ignore hazards
2954 between INSN and the first IGNORE instructions in HIST.
2956 If INSN is null, return the worse-case number of nops for any
2960 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
2961 const struct mips_cl_insn *insn)
2963 int i, nops, tmp_nops;
2966 for (i = ignore; i < MAX_DELAY_NOPS; i++)
2968 tmp_nops = insns_between (hist + i, insn) - i;
2969 if (tmp_nops > nops)
2973 if (mips_fix_vr4130)
2975 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
2976 if (tmp_nops > nops)
2982 tmp_nops = nops_for_24k (ignore, hist, insn);
2983 if (tmp_nops > nops)
2990 /* The variable arguments provide NUM_INSNS extra instructions that
2991 might be added to HIST. Return the largest number of nops that
2992 would be needed after the extended sequence, ignoring hazards
2993 in the first IGNORE instructions. */
2996 nops_for_sequence (int num_insns, int ignore,
2997 const struct mips_cl_insn *hist, ...)
3000 struct mips_cl_insn buffer[MAX_NOPS];
3001 struct mips_cl_insn *cursor;
3004 va_start (args, hist);
3005 cursor = buffer + num_insns;
3006 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
3007 while (cursor > buffer)
3008 *--cursor = *va_arg (args, const struct mips_cl_insn *);
3010 nops = nops_for_insn (ignore, buffer, NULL);
3015 /* Like nops_for_insn, but if INSN is a branch, take into account the
3016 worst-case delay for the branch target. */
3019 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
3020 const struct mips_cl_insn *insn)
3024 nops = nops_for_insn (ignore, hist, insn);
3025 if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
3026 | INSN_COND_BRANCH_DELAY
3027 | INSN_COND_BRANCH_LIKELY))
3029 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
3030 hist, insn, NOP_INSN);
3031 if (tmp_nops > nops)
3034 else if (mips_opts.mips16
3035 && (insn->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
3036 | MIPS16_INSN_COND_BRANCH)))
3038 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
3039 if (tmp_nops > nops)
3045 /* Fix NOP issue: Replace nops by "or at,at,zero". */
3048 fix_loongson2f_nop (struct mips_cl_insn * ip)
3050 if (strcmp (ip->insn_mo->name, "nop") == 0)
3051 ip->insn_opcode = LOONGSON2F_NOP_INSN;
3054 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
3055 jr target pc &= 'hffff_ffff_cfff_ffff. */
3058 fix_loongson2f_jump (struct mips_cl_insn * ip)
3060 if (strcmp (ip->insn_mo->name, "j") == 0
3061 || strcmp (ip->insn_mo->name, "jr") == 0
3062 || strcmp (ip->insn_mo->name, "jalr") == 0)
3070 sreg = EXTRACT_OPERAND (RS, *ip);
3071 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
3074 ep.X_op = O_constant;
3075 ep.X_add_number = 0xcfff0000;
3076 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
3077 ep.X_add_number = 0xffff;
3078 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
3079 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
3084 fix_loongson2f (struct mips_cl_insn * ip)
3086 if (mips_fix_loongson2f_nop)
3087 fix_loongson2f_nop (ip);
3089 if (mips_fix_loongson2f_jump)
3090 fix_loongson2f_jump (ip);
3093 /* IP is a branch that has a delay slot, and we need to fill it
3094 automatically. Return true if we can do that by swapping IP
3095 with the previous instruction. */
3098 can_swap_branch_p (struct mips_cl_insn *ip)
3100 unsigned long pinfo, prev_pinfo;
3101 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
3103 /* -O2 and above is required for this optimization. */
3104 if (mips_optimize < 2)
3107 /* If we have seen .set volatile or .set nomove, don't optimize. */
3108 if (mips_opts.nomove)
3111 /* We can't swap if the previous instruction's position is fixed. */
3112 if (history[0].fixed_p)
3115 /* If the previous previous insn was in a .set noreorder, we can't
3116 swap. Actually, the MIPS assembler will swap in this situation.
3117 However, gcc configured -with-gnu-as will generate code like
3125 in which we can not swap the bne and INSN. If gcc is not configured
3126 -with-gnu-as, it does not output the .set pseudo-ops. */
3127 if (history[1].noreorder_p)
3130 /* If the previous instruction had a fixup in mips16 mode, we can not
3131 swap. This normally means that the previous instruction was a 4
3132 byte branch anyhow. */
3133 if (mips_opts.mips16 && history[0].fixp[0])
3136 /* If the branch is itself the target of a branch, we can not swap.
3137 We cheat on this; all we check for is whether there is a label on
3138 this instruction. If there are any branches to anything other than
3139 a label, users must use .set noreorder. */
3140 if (seg_info (now_seg)->label_list)
3143 /* If the previous instruction is in a variant frag other than this
3144 branch's one, we cannot do the swap. This does not apply to the
3145 mips16, which uses variant frags for different purposes. */
3146 if (!mips_opts.mips16
3148 && history[0].frag->fr_type == rs_machine_dependent)
3151 /* We do not swap with instructions that cannot architecturally
3152 be placed in a branch delay slot, such as SYNC or ERET. We
3153 also refrain from swapping with a trap instruction, since it
3154 complicates trap handlers to have the trap instruction be in
3156 prev_pinfo = history[0].insn_mo->pinfo;
3157 if (prev_pinfo & INSN_NO_DELAY_SLOT)
3160 /* Check for conflicts between the branch and the instructions
3161 before the candidate delay slot. */
3162 if (nops_for_insn (0, history + 1, ip) > 0)
3165 /* Check for conflicts between the swapped sequence and the
3166 target of the branch. */
3167 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
3170 /* If the branch reads a register that the previous
3171 instruction sets, we can not swap. */
3172 gpr_read = gpr_read_mask (ip);
3173 prev_gpr_write = gpr_write_mask (&history[0]);
3174 if (gpr_read & prev_gpr_write)
3177 /* If the branch writes a register that the previous
3178 instruction sets, we can not swap. */
3179 gpr_write = gpr_write_mask (ip);
3180 if (gpr_write & prev_gpr_write)
3183 /* If the branch writes a register that the previous
3184 instruction reads, we can not swap. */
3185 prev_gpr_read = gpr_read_mask (&history[0]);
3186 if (gpr_write & prev_gpr_read)
3189 /* If one instruction sets a condition code and the
3190 other one uses a condition code, we can not swap. */
3191 pinfo = ip->insn_mo->pinfo;
3192 if ((pinfo & INSN_READ_COND_CODE)
3193 && (prev_pinfo & INSN_WRITE_COND_CODE))
3195 if ((pinfo & INSN_WRITE_COND_CODE)
3196 && (prev_pinfo & INSN_READ_COND_CODE))
3199 /* If the previous instruction uses the PC, we can not swap. */
3200 if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC))
3206 /* Decide how we should add IP to the instruction stream. */
3208 static enum append_method
3209 get_append_method (struct mips_cl_insn *ip)
3211 unsigned long pinfo;
3213 /* The relaxed version of a macro sequence must be inherently
3215 if (mips_relax.sequence == 2)
3218 /* We must not dabble with instructions in a ".set norerorder" block. */
3219 if (mips_opts.noreorder)
3222 /* Otherwise, it's our responsibility to fill branch delay slots. */
3223 pinfo = ip->insn_mo->pinfo;
3224 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
3225 || (pinfo & INSN_COND_BRANCH_DELAY))
3227 if (can_swap_branch_p (ip))
3230 if (mips_opts.mips16
3231 && ISA_SUPPORTS_MIPS16E
3232 && (pinfo & INSN_UNCOND_BRANCH_DELAY)
3233 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)))
3234 return APPEND_ADD_COMPACT;
3236 return APPEND_ADD_WITH_NOP;
3239 /* We don't bother trying to track the target of branches, so there's
3240 nothing we can use to fill a branch-likely slot. */
3241 if (pinfo & INSN_COND_BRANCH_LIKELY)
3242 return APPEND_ADD_WITH_NOP;
3247 /* IP is a MIPS16 instruction whose opcode we have just changed.
3248 Point IP->insn_mo to the new opcode's definition. */
3251 find_altered_mips16_opcode (struct mips_cl_insn *ip)
3253 const struct mips_opcode *mo, *end;
3255 end = &mips16_opcodes[bfd_mips16_num_opcodes];
3256 for (mo = ip->insn_mo; mo < end; mo++)
3257 if ((ip->insn_opcode & mo->mask) == mo->match)
3265 /* Output an instruction. IP is the instruction information.
3266 ADDRESS_EXPR is an operand of the instruction to be used with
3270 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
3271 bfd_reloc_code_real_type *reloc_type)
3273 unsigned long prev_pinfo, pinfo;
3274 bfd_boolean relaxed_branch = FALSE;
3275 enum append_method method;
3277 if (mips_fix_loongson2f)
3278 fix_loongson2f (ip);
3280 /* Mark instruction labels in mips16 mode. */
3281 mips16_mark_labels ();
3283 file_ase_mips16 |= mips_opts.mips16;
3285 prev_pinfo = history[0].insn_mo->pinfo;
3286 pinfo = ip->insn_mo->pinfo;
3288 if (address_expr == NULL)
3290 else if (*reloc_type <= BFD_RELOC_UNUSED
3291 && address_expr->X_op == O_constant)
3296 switch (*reloc_type)
3299 ip->insn_opcode |= address_expr->X_add_number;
3302 case BFD_RELOC_MIPS_HIGHEST:
3303 tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48;
3304 ip->insn_opcode |= tmp & 0xffff;
3307 case BFD_RELOC_MIPS_HIGHER:
3308 tmp = (address_expr->X_add_number + 0x80008000ull) >> 32;
3309 ip->insn_opcode |= tmp & 0xffff;
3312 case BFD_RELOC_HI16_S:
3313 tmp = (address_expr->X_add_number + 0x8000) >> 16;
3314 ip->insn_opcode |= tmp & 0xffff;
3317 case BFD_RELOC_HI16:
3318 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
3321 case BFD_RELOC_UNUSED:
3322 case BFD_RELOC_LO16:
3323 case BFD_RELOC_MIPS_GOT_DISP:
3324 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
3327 case BFD_RELOC_MIPS_JMP:
3328 if ((address_expr->X_add_number & 3) != 0)
3329 as_bad (_("jump to misaligned address (0x%lx)"),
3330 (unsigned long) address_expr->X_add_number);
3331 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
3335 case BFD_RELOC_MIPS16_JMP:
3336 if ((address_expr->X_add_number & 3) != 0)
3337 as_bad (_("jump to misaligned address (0x%lx)"),
3338 (unsigned long) address_expr->X_add_number);
3340 (((address_expr->X_add_number & 0x7c0000) << 3)
3341 | ((address_expr->X_add_number & 0xf800000) >> 7)
3342 | ((address_expr->X_add_number & 0x3fffc) >> 2));
3346 case BFD_RELOC_16_PCREL_S2:
3347 if ((address_expr->X_add_number & 3) != 0)
3348 as_bad (_("branch to misaligned address (0x%lx)"),
3349 (unsigned long) address_expr->X_add_number);
3350 if (!mips_relax_branch)
3352 if ((address_expr->X_add_number + 0x20000) & ~0x3ffff)
3353 as_bad (_("branch address range overflow (0x%lx)"),
3354 (unsigned long) address_expr->X_add_number);
3355 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff;
3365 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
3367 /* There are a lot of optimizations we could do that we don't.
3368 In particular, we do not, in general, reorder instructions.
3369 If you use gcc with optimization, it will reorder
3370 instructions and generally do much more optimization then we
3371 do here; repeating all that work in the assembler would only
3372 benefit hand written assembly code, and does not seem worth
3374 int nops = (mips_optimize == 0
3375 ? nops_for_insn (0, history, NULL)
3376 : nops_for_insn_or_target (0, history, ip));
3380 unsigned long old_frag_offset;
3383 old_frag = frag_now;
3384 old_frag_offset = frag_now_fix ();
3386 for (i = 0; i < nops; i++)
3391 listing_prev_line ();
3392 /* We may be at the start of a variant frag. In case we
3393 are, make sure there is enough space for the frag
3394 after the frags created by listing_prev_line. The
3395 argument to frag_grow here must be at least as large
3396 as the argument to all other calls to frag_grow in
3397 this file. We don't have to worry about being in the
3398 middle of a variant frag, because the variants insert
3399 all needed nop instructions themselves. */
3403 mips_move_labels ();
3405 #ifndef NO_ECOFF_DEBUGGING
3406 if (ECOFF_DEBUGGING)
3407 ecoff_fix_loc (old_frag, old_frag_offset);
3411 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
3415 /* Work out how many nops in prev_nop_frag are needed by IP,
3416 ignoring hazards generated by the first prev_nop_frag_since
3418 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
3419 gas_assert (nops <= prev_nop_frag_holds);
3421 /* Enforce NOPS as a minimum. */
3422 if (nops > prev_nop_frag_required)
3423 prev_nop_frag_required = nops;
3425 if (prev_nop_frag_holds == prev_nop_frag_required)
3427 /* Settle for the current number of nops. Update the history
3428 accordingly (for the benefit of any future .set reorder code). */
3429 prev_nop_frag = NULL;
3430 insert_into_history (prev_nop_frag_since,
3431 prev_nop_frag_holds, NOP_INSN);
3435 /* Allow this instruction to replace one of the nops that was
3436 tentatively added to prev_nop_frag. */
3437 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
3438 prev_nop_frag_holds--;
3439 prev_nop_frag_since++;
3443 method = get_append_method (ip);
3446 /* The value passed to dwarf2_emit_insn is the distance between
3447 the beginning of the current instruction and the address that
3448 should be recorded in the debug tables. This is normally the
3451 For MIPS16 debug info we want to use ISA-encoded addresses,
3452 so we use -1 for an address higher by one than the current one.
3454 If the instruction produced is a branch that we will swap with
3455 the preceding instruction, then we add the displacement by which
3456 the branch will be moved backwards. This is more appropriate
3457 and for MIPS16 code also prevents a debugger from placing a
3458 breakpoint in the middle of the branch (and corrupting code if
3459 software breakpoints are used). */
3460 dwarf2_emit_insn ((mips_opts.mips16 ? -1 : 0)
3461 + (method == APPEND_SWAP ? insn_length (history) : 0));
3465 && *reloc_type == BFD_RELOC_16_PCREL_S2
3466 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
3467 || pinfo & INSN_COND_BRANCH_LIKELY)
3468 && mips_relax_branch
3469 /* Don't try branch relaxation within .set nomacro, or within
3470 .set noat if we use $at for PIC computations. If it turns
3471 out that the branch was out-of-range, we'll get an error. */
3472 && !mips_opts.warn_about_macros
3473 && (mips_opts.at || mips_pic == NO_PIC)
3474 /* Don't relax BPOSGE32/64 as they have no complementing branches. */
3475 && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP))
3476 && !mips_opts.mips16)
3478 relaxed_branch = TRUE;
3479 add_relaxed_insn (ip, (relaxed_branch_length
3481 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
3482 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1
3486 pinfo & INSN_UNCOND_BRANCH_DELAY,
3487 pinfo & INSN_COND_BRANCH_LIKELY,
3488 pinfo & INSN_WRITE_GPR_31,
3490 address_expr->X_add_symbol,
3491 address_expr->X_add_number);
3492 *reloc_type = BFD_RELOC_UNUSED;
3494 else if (*reloc_type > BFD_RELOC_UNUSED)
3496 /* We need to set up a variant frag. */
3497 gas_assert (mips_opts.mips16 && address_expr != NULL);
3498 add_relaxed_insn (ip, 4, 0,
3500 (*reloc_type - BFD_RELOC_UNUSED,
3501 mips16_small, mips16_ext,
3502 prev_pinfo & INSN_UNCOND_BRANCH_DELAY,
3503 history[0].mips16_absolute_jump_p),
3504 make_expr_symbol (address_expr), 0);
3506 else if (mips_opts.mips16
3508 && *reloc_type != BFD_RELOC_MIPS16_JMP)
3510 if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0)
3511 /* Make sure there is enough room to swap this instruction with
3512 a following jump instruction. */
3514 add_fixed_insn (ip);
3518 if (mips_opts.mips16
3519 && mips_opts.noreorder
3520 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
3521 as_warn (_("extended instruction in delay slot"));
3523 if (mips_relax.sequence)
3525 /* If we've reached the end of this frag, turn it into a variant
3526 frag and record the information for the instructions we've
3528 if (frag_room () < 4)
3529 relax_close_frag ();
3530 mips_relax.sizes[mips_relax.sequence - 1] += 4;
3533 if (mips_relax.sequence != 2)
3534 mips_macro_warning.sizes[0] += 4;
3535 if (mips_relax.sequence != 1)
3536 mips_macro_warning.sizes[1] += 4;
3538 if (mips_opts.mips16)
3541 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
3543 add_fixed_insn (ip);
3546 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
3548 reloc_howto_type *howto;
3551 /* In a compound relocation, it is the final (outermost)
3552 operator that determines the relocated field. */
3553 for (i = 1; i < 3; i++)
3554 if (reloc_type[i] == BFD_RELOC_UNUSED)
3557 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
3560 /* To reproduce this failure try assembling gas/testsuites/
3561 gas/mips/mips16-intermix.s with a mips-ecoff targeted
3563 as_bad (_("Unsupported MIPS relocation number %d"), reloc_type[i - 1]);
3564 howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16);
3567 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
3568 bfd_get_reloc_size (howto),
3570 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
3573 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
3574 if (reloc_type[0] == BFD_RELOC_MIPS16_JMP
3575 && ip->fixp[0]->fx_addsy)
3576 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
3578 /* These relocations can have an addend that won't fit in
3579 4 octets for 64bit assembly. */
3581 && ! howto->partial_inplace
3582 && (reloc_type[0] == BFD_RELOC_16
3583 || reloc_type[0] == BFD_RELOC_32
3584 || reloc_type[0] == BFD_RELOC_MIPS_JMP
3585 || reloc_type[0] == BFD_RELOC_GPREL16
3586 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
3587 || reloc_type[0] == BFD_RELOC_GPREL32
3588 || reloc_type[0] == BFD_RELOC_64
3589 || reloc_type[0] == BFD_RELOC_CTOR
3590 || reloc_type[0] == BFD_RELOC_MIPS_SUB
3591 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
3592 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
3593 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
3594 || reloc_type[0] == BFD_RELOC_MIPS_REL16
3595 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
3596 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
3597 || hi16_reloc_p (reloc_type[0])
3598 || lo16_reloc_p (reloc_type[0])))
3599 ip->fixp[0]->fx_no_overflow = 1;
3601 if (mips_relax.sequence)
3603 if (mips_relax.first_fixup == 0)
3604 mips_relax.first_fixup = ip->fixp[0];
3606 else if (reloc_needs_lo_p (*reloc_type))
3608 struct mips_hi_fixup *hi_fixup;
3610 /* Reuse the last entry if it already has a matching %lo. */
3611 hi_fixup = mips_hi_fixup_list;
3613 || !fixup_has_matching_lo_p (hi_fixup->fixp))
3615 hi_fixup = ((struct mips_hi_fixup *)
3616 xmalloc (sizeof (struct mips_hi_fixup)));
3617 hi_fixup->next = mips_hi_fixup_list;
3618 mips_hi_fixup_list = hi_fixup;
3620 hi_fixup->fixp = ip->fixp[0];
3621 hi_fixup->seg = now_seg;
3624 /* Add fixups for the second and third relocations, if given.
3625 Note that the ABI allows the second relocation to be
3626 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
3627 moment we only use RSS_UNDEF, but we could add support
3628 for the others if it ever becomes necessary. */
3629 for (i = 1; i < 3; i++)
3630 if (reloc_type[i] != BFD_RELOC_UNUSED)
3632 ip->fixp[i] = fix_new (ip->frag, ip->where,
3633 ip->fixp[0]->fx_size, NULL, 0,
3634 FALSE, reloc_type[i]);
3636 /* Use fx_tcbit to mark compound relocs. */
3637 ip->fixp[0]->fx_tcbit = 1;
3638 ip->fixp[i]->fx_tcbit = 1;
3643 /* Update the register mask information. */
3644 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
3645 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
3650 insert_into_history (0, 1, ip);
3653 case APPEND_ADD_WITH_NOP:
3654 insert_into_history (0, 1, ip);
3656 if (mips_relax.sequence)
3657 mips_relax.sizes[mips_relax.sequence - 1] += 4;
3660 case APPEND_ADD_COMPACT:
3661 /* Convert MIPS16 jr/jalr into a "compact" jump. */
3662 gas_assert (mips_opts.mips16);
3663 ip->insn_opcode |= 0x0080;
3664 find_altered_mips16_opcode (ip);
3666 insert_into_history (0, 1, ip);
3671 struct mips_cl_insn delay = history[0];
3672 if (mips_opts.mips16)
3674 know (delay.frag == ip->frag);
3675 move_insn (ip, delay.frag, delay.where);
3676 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
3678 else if (relaxed_branch)
3680 /* Add the delay slot instruction to the end of the
3681 current frag and shrink the fixed part of the
3682 original frag. If the branch occupies the tail of
3683 the latter, move it backwards to cover the gap. */
3684 delay.frag->fr_fix -= 4;
3685 if (delay.frag == ip->frag)
3686 move_insn (ip, ip->frag, ip->where - 4);
3687 add_fixed_insn (&delay);
3691 move_insn (&delay, ip->frag, ip->where);
3692 move_insn (ip, history[0].frag, history[0].where);
3696 insert_into_history (0, 1, &delay);
3701 /* If we have just completed an unconditional branch, clear the history. */
3702 if ((history[1].insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY)
3703 || (mips_opts.mips16
3704 && (history[0].insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH)))
3705 mips_no_prev_insn ();
3707 /* We just output an insn, so the next one doesn't have a label. */
3708 mips_clear_insn_labels ();
3711 /* Forget that there was any previous instruction or label. */
3714 mips_no_prev_insn (void)
3716 prev_nop_frag = NULL;
3717 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
3718 mips_clear_insn_labels ();
3721 /* This function must be called before we emit something other than
3722 instructions. It is like mips_no_prev_insn except that it inserts
3723 any NOPS that might be needed by previous instructions. */
3726 mips_emit_delays (void)
3728 if (! mips_opts.noreorder)
3730 int nops = nops_for_insn (0, history, NULL);
3734 add_fixed_insn (NOP_INSN);
3735 mips_move_labels ();
3738 mips_no_prev_insn ();
3741 /* Start a (possibly nested) noreorder block. */
3744 start_noreorder (void)
3746 if (mips_opts.noreorder == 0)
3751 /* None of the instructions before the .set noreorder can be moved. */
3752 for (i = 0; i < ARRAY_SIZE (history); i++)
3753 history[i].fixed_p = 1;
3755 /* Insert any nops that might be needed between the .set noreorder
3756 block and the previous instructions. We will later remove any
3757 nops that turn out not to be needed. */
3758 nops = nops_for_insn (0, history, NULL);
3761 if (mips_optimize != 0)
3763 /* Record the frag which holds the nop instructions, so
3764 that we can remove them if we don't need them. */
3765 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
3766 prev_nop_frag = frag_now;
3767 prev_nop_frag_holds = nops;
3768 prev_nop_frag_required = 0;
3769 prev_nop_frag_since = 0;
3772 for (; nops > 0; --nops)
3773 add_fixed_insn (NOP_INSN);
3775 /* Move on to a new frag, so that it is safe to simply
3776 decrease the size of prev_nop_frag. */
3777 frag_wane (frag_now);
3779 mips_move_labels ();
3781 mips16_mark_labels ();
3782 mips_clear_insn_labels ();
3784 mips_opts.noreorder++;
3785 mips_any_noreorder = 1;
3788 /* End a nested noreorder block. */
3791 end_noreorder (void)
3794 mips_opts.noreorder--;
3795 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
3797 /* Commit to inserting prev_nop_frag_required nops and go back to
3798 handling nop insertion the .set reorder way. */
3799 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
3800 * (mips_opts.mips16 ? 2 : 4));
3801 insert_into_history (prev_nop_frag_since,
3802 prev_nop_frag_required, NOP_INSN);
3803 prev_nop_frag = NULL;
3807 /* Set up global variables for the start of a new macro. */
3812 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
3813 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
3814 && (history[0].insn_mo->pinfo
3815 & (INSN_UNCOND_BRANCH_DELAY
3816 | INSN_COND_BRANCH_DELAY
3817 | INSN_COND_BRANCH_LIKELY)) != 0);
3820 /* Given that a macro is longer than 4 bytes, return the appropriate warning
3821 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
3822 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
3825 macro_warning (relax_substateT subtype)
3827 if (subtype & RELAX_DELAY_SLOT)
3828 return _("Macro instruction expanded into multiple instructions"
3829 " in a branch delay slot");
3830 else if (subtype & RELAX_NOMACRO)
3831 return _("Macro instruction expanded into multiple instructions");
3836 /* Finish up a macro. Emit warnings as appropriate. */
3841 if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4)
3843 relax_substateT subtype;
3845 /* Set up the relaxation warning flags. */
3847 if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0])
3848 subtype |= RELAX_SECOND_LONGER;
3849 if (mips_opts.warn_about_macros)
3850 subtype |= RELAX_NOMACRO;
3851 if (mips_macro_warning.delay_slot_p)
3852 subtype |= RELAX_DELAY_SLOT;
3854 if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4)
3856 /* Either the macro has a single implementation or both
3857 implementations are longer than 4 bytes. Emit the
3859 const char *msg = macro_warning (subtype);
3861 as_warn ("%s", msg);
3865 /* One implementation might need a warning but the other
3866 definitely doesn't. */
3867 mips_macro_warning.first_frag->fr_subtype |= subtype;
3872 /* Read a macro's relocation codes from *ARGS and store them in *R.
3873 The first argument in *ARGS will be either the code for a single
3874 relocation or -1 followed by the three codes that make up a
3875 composite relocation. */
3878 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
3882 next = va_arg (*args, int);
3884 r[0] = (bfd_reloc_code_real_type) next;
3886 for (i = 0; i < 3; i++)
3887 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
3890 /* Build an instruction created by a macro expansion. This is passed
3891 a pointer to the count of instructions created so far, an
3892 expression, the name of the instruction to build, an operand format
3893 string, and corresponding arguments. */
3896 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
3898 const struct mips_opcode *mo;
3899 struct mips_cl_insn insn;
3900 bfd_reloc_code_real_type r[3];
3903 va_start (args, fmt);
3905 if (mips_opts.mips16)
3907 mips16_macro_build (ep, name, fmt, &args);
3912 r[0] = BFD_RELOC_UNUSED;
3913 r[1] = BFD_RELOC_UNUSED;
3914 r[2] = BFD_RELOC_UNUSED;
3915 mo = (struct mips_opcode *) hash_find (op_hash, name);
3917 gas_assert (strcmp (name, mo->name) == 0);
3921 /* Search until we get a match for NAME. It is assumed here that
3922 macros will never generate MDMX, MIPS-3D, or MT instructions. */
3923 if (strcmp (fmt, mo->args) == 0
3924 && mo->pinfo != INSN_MACRO
3925 && is_opcode_valid (mo))
3929 gas_assert (mo->name);
3930 gas_assert (strcmp (name, mo->name) == 0);
3933 create_insn (&insn, mo);
3951 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
3956 /* Note that in the macro case, these arguments are already
3957 in MSB form. (When handling the instruction in the
3958 non-macro case, these arguments are sizes from which
3959 MSB values must be calculated.) */
3960 INSERT_OPERAND (INSMSB, insn, va_arg (args, int));
3966 /* Note that in the macro case, these arguments are already
3967 in MSBD form. (When handling the instruction in the
3968 non-macro case, these arguments are sizes from which
3969 MSBD values must be calculated.) */
3970 INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int));
3974 INSERT_OPERAND (SEQI, insn, va_arg (args, int));
3983 INSERT_OPERAND (BP, insn, va_arg (args, int));
3989 INSERT_OPERAND (RT, insn, va_arg (args, int));
3993 INSERT_OPERAND (CODE, insn, va_arg (args, int));
3998 INSERT_OPERAND (FT, insn, va_arg (args, int));
4004 INSERT_OPERAND (RD, insn, va_arg (args, int));
4009 int tmp = va_arg (args, int);
4011 INSERT_OPERAND (RT, insn, tmp);
4012 INSERT_OPERAND (RD, insn, tmp);
4018 INSERT_OPERAND (FS, insn, va_arg (args, int));
4025 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
4029 INSERT_OPERAND (FD, insn, va_arg (args, int));
4033 INSERT_OPERAND (CODE20, insn, va_arg (args, int));
4037 INSERT_OPERAND (CODE19, insn, va_arg (args, int));
4041 INSERT_OPERAND (CODE2, insn, va_arg (args, int));
4048 INSERT_OPERAND (RS, insn, va_arg (args, int));
4053 macro_read_relocs (&args, r);
4054 gas_assert (*r == BFD_RELOC_GPREL16
4055 || *r == BFD_RELOC_MIPS_HIGHER
4056 || *r == BFD_RELOC_HI16_S
4057 || *r == BFD_RELOC_LO16
4058 || *r == BFD_RELOC_MIPS_GOT_OFST);
4062 macro_read_relocs (&args, r);
4066 macro_read_relocs (&args, r);
4067 gas_assert (ep != NULL
4068 && (ep->X_op == O_constant
4069 || (ep->X_op == O_symbol
4070 && (*r == BFD_RELOC_MIPS_HIGHEST
4071 || *r == BFD_RELOC_HI16_S
4072 || *r == BFD_RELOC_HI16
4073 || *r == BFD_RELOC_GPREL16
4074 || *r == BFD_RELOC_MIPS_GOT_HI16
4075 || *r == BFD_RELOC_MIPS_CALL_HI16))));
4079 gas_assert (ep != NULL);
4082 * This allows macro() to pass an immediate expression for
4083 * creating short branches without creating a symbol.
4085 * We don't allow branch relaxation for these branches, as
4086 * they should only appear in ".set nomacro" anyway.
4088 if (ep->X_op == O_constant)
4090 if ((ep->X_add_number & 3) != 0)
4091 as_bad (_("branch to misaligned address (0x%lx)"),
4092 (unsigned long) ep->X_add_number);
4093 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
4094 as_bad (_("branch address range overflow (0x%lx)"),
4095 (unsigned long) ep->X_add_number);
4096 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
4100 *r = BFD_RELOC_16_PCREL_S2;
4104 gas_assert (ep != NULL);
4105 *r = BFD_RELOC_MIPS_JMP;
4109 INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long));
4113 INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long));
4122 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
4124 append_insn (&insn, ep, r);
4128 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
4131 struct mips_opcode *mo;
4132 struct mips_cl_insn insn;
4133 bfd_reloc_code_real_type r[3]
4134 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
4136 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
4138 gas_assert (strcmp (name, mo->name) == 0);
4140 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
4143 gas_assert (mo->name);
4144 gas_assert (strcmp (name, mo->name) == 0);
4147 create_insn (&insn, mo);
4165 MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int));
4170 MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int));
4174 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int));
4178 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int));
4188 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int));
4195 regno = va_arg (*args, int);
4196 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
4197 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
4218 gas_assert (ep != NULL);
4220 if (ep->X_op != O_constant)
4221 *r = (int) BFD_RELOC_UNUSED + c;
4224 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
4225 FALSE, &insn.insn_opcode, &insn.use_extend,
4228 *r = BFD_RELOC_UNUSED;
4234 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int));
4241 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
4243 append_insn (&insn, ep, r);
4247 * Sign-extend 32-bit mode constants that have bit 31 set and all
4248 * higher bits unset.
4251 normalize_constant_expr (expressionS *ex)
4253 if (ex->X_op == O_constant
4254 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
4255 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
4260 * Sign-extend 32-bit mode address offsets that have bit 31 set and
4261 * all higher bits unset.
4264 normalize_address_expr (expressionS *ex)
4266 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
4267 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
4268 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
4269 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
4274 * Generate a "jalr" instruction with a relocation hint to the called
4275 * function. This occurs in NewABI PIC code.
4278 macro_build_jalr (expressionS *ep)
4282 if (MIPS_JALR_HINT_P (ep))
4287 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
4288 if (MIPS_JALR_HINT_P (ep))
4289 fix_new_exp (frag_now, f - frag_now->fr_literal,
4290 4, ep, FALSE, BFD_RELOC_MIPS_JALR);
4294 * Generate a "lui" instruction.
4297 macro_build_lui (expressionS *ep, int regnum)
4299 expressionS high_expr;
4300 const struct mips_opcode *mo;
4301 struct mips_cl_insn insn;
4302 bfd_reloc_code_real_type r[3]
4303 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
4304 const char *name = "lui";
4305 const char *fmt = "t,u";
4307 gas_assert (! mips_opts.mips16);
4311 if (high_expr.X_op == O_constant)
4313 /* We can compute the instruction now without a relocation entry. */
4314 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
4316 *r = BFD_RELOC_UNUSED;
4320 gas_assert (ep->X_op == O_symbol);
4321 /* _gp_disp is a special case, used from s_cpload.
4322 __gnu_local_gp is used if mips_no_shared. */
4323 gas_assert (mips_pic == NO_PIC
4325 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
4326 || (! mips_in_shared
4327 && strcmp (S_GET_NAME (ep->X_add_symbol),
4328 "__gnu_local_gp") == 0));
4329 *r = BFD_RELOC_HI16_S;
4332 mo = hash_find (op_hash, name);
4333 gas_assert (strcmp (name, mo->name) == 0);
4334 gas_assert (strcmp (fmt, mo->args) == 0);
4335 create_insn (&insn, mo);
4337 insn.insn_opcode = insn.insn_mo->match;
4338 INSERT_OPERAND (RT, insn, regnum);
4339 if (*r == BFD_RELOC_UNUSED)
4341 insn.insn_opcode |= high_expr.X_add_number;
4342 append_insn (&insn, NULL, r);
4345 append_insn (&insn, &high_expr, r);
4348 /* Generate a sequence of instructions to do a load or store from a constant
4349 offset off of a base register (breg) into/from a target register (treg),
4350 using AT if necessary. */
4352 macro_build_ldst_constoffset (expressionS *ep, const char *op,
4353 int treg, int breg, int dbl)
4355 gas_assert (ep->X_op == O_constant);
4357 /* Sign-extending 32-bit constants makes their handling easier. */
4359 normalize_constant_expr (ep);
4361 /* Right now, this routine can only handle signed 32-bit constants. */
4362 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
4363 as_warn (_("operand overflow"));
4365 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
4367 /* Signed 16-bit offset will fit in the op. Easy! */
4368 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
4372 /* 32-bit offset, need multiple instructions and AT, like:
4373 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
4374 addu $tempreg,$tempreg,$breg
4375 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
4376 to handle the complete offset. */
4377 macro_build_lui (ep, AT);
4378 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
4379 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
4382 as_bad (_("Macro used $at after \".set noat\""));
4387 * Generates code to set the $at register to true (one)
4388 * if reg is less than the immediate expression.
4391 set_at (int reg, int unsignedp)
4393 if (imm_expr.X_op == O_constant
4394 && imm_expr.X_add_number >= -0x8000
4395 && imm_expr.X_add_number < 0x8000)
4396 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
4397 AT, reg, BFD_RELOC_LO16);
4400 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4401 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
4405 /* Warn if an expression is not a constant. */
4408 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
4410 if (ex->X_op == O_big)
4411 as_bad (_("unsupported large constant"));
4412 else if (ex->X_op != O_constant)
4413 as_bad (_("Instruction %s requires absolute expression"),
4416 if (HAVE_32BIT_GPRS)
4417 normalize_constant_expr (ex);
4420 /* Count the leading zeroes by performing a binary chop. This is a
4421 bulky bit of source, but performance is a LOT better for the
4422 majority of values than a simple loop to count the bits:
4423 for (lcnt = 0; (lcnt < 32); lcnt++)
4424 if ((v) & (1 << (31 - lcnt)))
4426 However it is not code size friendly, and the gain will drop a bit
4427 on certain cached systems.
4429 #define COUNT_TOP_ZEROES(v) \
4430 (((v) & ~0xffff) == 0 \
4431 ? ((v) & ~0xff) == 0 \
4432 ? ((v) & ~0xf) == 0 \
4433 ? ((v) & ~0x3) == 0 \
4434 ? ((v) & ~0x1) == 0 \
4439 : ((v) & ~0x7) == 0 \
4442 : ((v) & ~0x3f) == 0 \
4443 ? ((v) & ~0x1f) == 0 \
4446 : ((v) & ~0x7f) == 0 \
4449 : ((v) & ~0xfff) == 0 \
4450 ? ((v) & ~0x3ff) == 0 \
4451 ? ((v) & ~0x1ff) == 0 \
4454 : ((v) & ~0x7ff) == 0 \
4457 : ((v) & ~0x3fff) == 0 \
4458 ? ((v) & ~0x1fff) == 0 \
4461 : ((v) & ~0x7fff) == 0 \
4464 : ((v) & ~0xffffff) == 0 \
4465 ? ((v) & ~0xfffff) == 0 \
4466 ? ((v) & ~0x3ffff) == 0 \
4467 ? ((v) & ~0x1ffff) == 0 \
4470 : ((v) & ~0x7ffff) == 0 \
4473 : ((v) & ~0x3fffff) == 0 \
4474 ? ((v) & ~0x1fffff) == 0 \
4477 : ((v) & ~0x7fffff) == 0 \
4480 : ((v) & ~0xfffffff) == 0 \
4481 ? ((v) & ~0x3ffffff) == 0 \
4482 ? ((v) & ~0x1ffffff) == 0 \
4485 : ((v) & ~0x7ffffff) == 0 \
4488 : ((v) & ~0x3fffffff) == 0 \
4489 ? ((v) & ~0x1fffffff) == 0 \
4492 : ((v) & ~0x7fffffff) == 0 \
4497 * This routine generates the least number of instructions necessary to load
4498 * an absolute expression value into a register.
4501 load_register (int reg, expressionS *ep, int dbl)
4504 expressionS hi32, lo32;
4506 if (ep->X_op != O_big)
4508 gas_assert (ep->X_op == O_constant);
4510 /* Sign-extending 32-bit constants makes their handling easier. */
4512 normalize_constant_expr (ep);
4514 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
4516 /* We can handle 16 bit signed values with an addiu to
4517 $zero. No need to ever use daddiu here, since $zero and
4518 the result are always correct in 32 bit mode. */
4519 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4522 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
4524 /* We can handle 16 bit unsigned values with an ori to
4526 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
4529 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
4531 /* 32 bit values require an lui. */
4532 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16);
4533 if ((ep->X_add_number & 0xffff) != 0)
4534 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
4539 /* The value is larger than 32 bits. */
4541 if (!dbl || HAVE_32BIT_GPRS)
4545 sprintf_vma (value, ep->X_add_number);
4546 as_bad (_("Number (0x%s) larger than 32 bits"), value);
4547 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4551 if (ep->X_op != O_big)
4554 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
4555 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
4556 hi32.X_add_number &= 0xffffffff;
4558 lo32.X_add_number &= 0xffffffff;
4562 gas_assert (ep->X_add_number > 2);
4563 if (ep->X_add_number == 3)
4564 generic_bignum[3] = 0;
4565 else if (ep->X_add_number > 4)
4566 as_bad (_("Number larger than 64 bits"));
4567 lo32.X_op = O_constant;
4568 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
4569 hi32.X_op = O_constant;
4570 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
4573 if (hi32.X_add_number == 0)
4578 unsigned long hi, lo;
4580 if (hi32.X_add_number == (offsetT) 0xffffffff)
4582 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
4584 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4587 if (lo32.X_add_number & 0x80000000)
4589 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
4590 if (lo32.X_add_number & 0xffff)
4591 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
4596 /* Check for 16bit shifted constant. We know that hi32 is
4597 non-zero, so start the mask on the first bit of the hi32
4602 unsigned long himask, lomask;
4606 himask = 0xffff >> (32 - shift);
4607 lomask = (0xffff << shift) & 0xffffffff;
4611 himask = 0xffff << (shift - 32);
4614 if ((hi32.X_add_number & ~(offsetT) himask) == 0
4615 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
4619 tmp.X_op = O_constant;
4621 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
4622 | (lo32.X_add_number >> shift));
4624 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
4625 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
4626 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<",
4627 reg, reg, (shift >= 32) ? shift - 32 : shift);
4632 while (shift <= (64 - 16));
4634 /* Find the bit number of the lowest one bit, and store the
4635 shifted value in hi/lo. */
4636 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
4637 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
4641 while ((lo & 1) == 0)
4646 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
4652 while ((hi & 1) == 0)
4661 /* Optimize if the shifted value is a (power of 2) - 1. */
4662 if ((hi == 0 && ((lo + 1) & lo) == 0)
4663 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
4665 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
4670 /* This instruction will set the register to be all
4672 tmp.X_op = O_constant;
4673 tmp.X_add_number = (offsetT) -1;
4674 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4678 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<",
4679 reg, reg, (bit >= 32) ? bit - 32 : bit);
4681 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<",
4682 reg, reg, (shift >= 32) ? shift - 32 : shift);
4687 /* Sign extend hi32 before calling load_register, because we can
4688 generally get better code when we load a sign extended value. */
4689 if ((hi32.X_add_number & 0x80000000) != 0)
4690 hi32.X_add_number |= ~(offsetT) 0xffffffff;
4691 load_register (reg, &hi32, 0);
4694 if ((lo32.X_add_number & 0xffff0000) == 0)
4698 macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0);
4706 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
4708 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
4709 macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0);
4715 macro_build (NULL, "dsll", "d,w,<", reg, freg, 16);
4719 mid16.X_add_number >>= 16;
4720 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
4721 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4724 if ((lo32.X_add_number & 0xffff) != 0)
4725 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
4729 load_delay_nop (void)
4731 if (!gpr_interlocks)
4732 macro_build (NULL, "nop", "");
4735 /* Load an address into a register. */
4738 load_address (int reg, expressionS *ep, int *used_at)
4740 if (ep->X_op != O_constant
4741 && ep->X_op != O_symbol)
4743 as_bad (_("expression too complex"));
4744 ep->X_op = O_constant;
4747 if (ep->X_op == O_constant)
4749 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
4753 if (mips_pic == NO_PIC)
4755 /* If this is a reference to a GP relative symbol, we want
4756 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4758 lui $reg,<sym> (BFD_RELOC_HI16_S)
4759 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4760 If we have an addend, we always use the latter form.
4762 With 64bit address space and a usable $at we want
4763 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4764 lui $at,<sym> (BFD_RELOC_HI16_S)
4765 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4766 daddiu $at,<sym> (BFD_RELOC_LO16)
4770 If $at is already in use, we use a path which is suboptimal
4771 on superscalar processors.
4772 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4773 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4775 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
4777 daddiu $reg,<sym> (BFD_RELOC_LO16)
4779 For GP relative symbols in 64bit address space we can use
4780 the same sequence as in 32bit address space. */
4781 if (HAVE_64BIT_SYMBOLS)
4783 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
4784 && !nopic_need_relax (ep->X_add_symbol, 1))
4786 relax_start (ep->X_add_symbol);
4787 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4788 mips_gp_register, BFD_RELOC_GPREL16);
4792 if (*used_at == 0 && mips_opts.at)
4794 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
4795 macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S);
4796 macro_build (ep, "daddiu", "t,r,j", reg, reg,
4797 BFD_RELOC_MIPS_HIGHER);
4798 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
4799 macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0);
4800 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
4805 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
4806 macro_build (ep, "daddiu", "t,r,j", reg, reg,
4807 BFD_RELOC_MIPS_HIGHER);
4808 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4809 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
4810 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4811 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
4814 if (mips_relax.sequence)
4819 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
4820 && !nopic_need_relax (ep->X_add_symbol, 1))
4822 relax_start (ep->X_add_symbol);
4823 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4824 mips_gp_register, BFD_RELOC_GPREL16);
4827 macro_build_lui (ep, reg);
4828 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
4829 reg, reg, BFD_RELOC_LO16);
4830 if (mips_relax.sequence)
4834 else if (!mips_big_got)
4838 /* If this is a reference to an external symbol, we want
4839 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4841 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4843 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4844 If there is a constant, it must be added in after.
4846 If we have NewABI, we want
4847 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4848 unless we're referencing a global symbol with a non-zero
4849 offset, in which case cst must be added separately. */
4852 if (ep->X_add_number)
4854 ex.X_add_number = ep->X_add_number;
4855 ep->X_add_number = 0;
4856 relax_start (ep->X_add_symbol);
4857 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4858 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4859 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4860 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4861 ex.X_op = O_constant;
4862 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
4863 reg, reg, BFD_RELOC_LO16);
4864 ep->X_add_number = ex.X_add_number;
4867 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4868 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4869 if (mips_relax.sequence)
4874 ex.X_add_number = ep->X_add_number;
4875 ep->X_add_number = 0;
4876 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4877 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4879 relax_start (ep->X_add_symbol);
4881 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4885 if (ex.X_add_number != 0)
4887 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4888 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4889 ex.X_op = O_constant;
4890 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
4891 reg, reg, BFD_RELOC_LO16);
4895 else if (mips_big_got)
4899 /* This is the large GOT case. If this is a reference to an
4900 external symbol, we want
4901 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4903 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
4905 Otherwise, for a reference to a local symbol in old ABI, we want
4906 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4908 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4909 If there is a constant, it must be added in after.
4911 In the NewABI, for local symbols, with or without offsets, we want:
4912 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4913 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4917 ex.X_add_number = ep->X_add_number;
4918 ep->X_add_number = 0;
4919 relax_start (ep->X_add_symbol);
4920 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4921 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4922 reg, reg, mips_gp_register);
4923 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4924 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4925 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4926 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4927 else if (ex.X_add_number)
4929 ex.X_op = O_constant;
4930 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4934 ep->X_add_number = ex.X_add_number;
4936 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4937 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
4938 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4939 BFD_RELOC_MIPS_GOT_OFST);
4944 ex.X_add_number = ep->X_add_number;
4945 ep->X_add_number = 0;
4946 relax_start (ep->X_add_symbol);
4947 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4948 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4949 reg, reg, mips_gp_register);
4950 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4951 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4953 if (reg_needs_delay (mips_gp_register))
4955 /* We need a nop before loading from $gp. This special
4956 check is required because the lui which starts the main
4957 instruction stream does not refer to $gp, and so will not
4958 insert the nop which may be required. */
4959 macro_build (NULL, "nop", "");
4961 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4962 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4964 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4968 if (ex.X_add_number != 0)
4970 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4971 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4972 ex.X_op = O_constant;
4973 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4981 if (!mips_opts.at && *used_at == 1)
4982 as_bad (_("Macro used $at after \".set noat\""));
4985 /* Move the contents of register SOURCE into register DEST. */
4988 move_register (int dest, int source)
4990 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
4994 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4995 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4996 The two alternatives are:
4998 Global symbol Local sybmol
4999 ------------- ------------
5000 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
5002 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
5004 load_got_offset emits the first instruction and add_got_offset
5005 emits the second for a 16-bit offset or add_got_offset_hilo emits
5006 a sequence to add a 32-bit offset using a scratch register. */
5009 load_got_offset (int dest, expressionS *local)
5014 global.X_add_number = 0;
5016 relax_start (local->X_add_symbol);
5017 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
5018 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5020 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
5021 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5026 add_got_offset (int dest, expressionS *local)
5030 global.X_op = O_constant;
5031 global.X_op_symbol = NULL;
5032 global.X_add_symbol = NULL;
5033 global.X_add_number = local->X_add_number;
5035 relax_start (local->X_add_symbol);
5036 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
5037 dest, dest, BFD_RELOC_LO16);
5039 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
5044 add_got_offset_hilo (int dest, expressionS *local, int tmp)
5047 int hold_mips_optimize;
5049 global.X_op = O_constant;
5050 global.X_op_symbol = NULL;
5051 global.X_add_symbol = NULL;
5052 global.X_add_number = local->X_add_number;
5054 relax_start (local->X_add_symbol);
5055 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
5057 /* Set mips_optimize around the lui instruction to avoid
5058 inserting an unnecessary nop after the lw. */
5059 hold_mips_optimize = mips_optimize;
5061 macro_build_lui (&global, tmp);
5062 mips_optimize = hold_mips_optimize;
5063 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
5066 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
5071 * This routine implements the seemingly endless macro or synthesized
5072 * instructions and addressing modes in the mips assembly language. Many
5073 * of these macros are simple and are similar to each other. These could
5074 * probably be handled by some kind of table or grammar approach instead of
5075 * this verbose method. Others are not simple macros but are more like
5076 * optimizing code generation.
5077 * One interesting optimization is when several store macros appear
5078 * consecutively that would load AT with the upper half of the same address.
5079 * The ensuing load upper instructions are ommited. This implies some kind
5080 * of global optimization. We currently only optimize within a single macro.
5081 * For many of the load and store macros if the address is specified as a
5082 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
5083 * first load register 'at' with zero and use it as the base register. The
5084 * mips assembler simply uses register $zero. Just one tiny optimization
5088 macro (struct mips_cl_insn *ip)
5090 unsigned int treg, sreg, dreg, breg;
5091 unsigned int tempreg;
5106 bfd_reloc_code_real_type r;
5107 int hold_mips_optimize;
5109 gas_assert (! mips_opts.mips16);
5111 treg = EXTRACT_OPERAND (RT, *ip);
5112 dreg = EXTRACT_OPERAND (RD, *ip);
5113 sreg = breg = EXTRACT_OPERAND (RS, *ip);
5114 mask = ip->insn_mo->mask;
5116 expr1.X_op = O_constant;
5117 expr1.X_op_symbol = NULL;
5118 expr1.X_add_symbol = NULL;
5119 expr1.X_add_number = 1;
5133 expr1.X_add_number = 8;
5134 macro_build (&expr1, "bgez", "s,p", sreg);
5136 macro_build (NULL, "nop", "");
5138 move_register (dreg, sreg);
5139 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
5162 if (imm_expr.X_op == O_constant
5163 && imm_expr.X_add_number >= -0x8000
5164 && imm_expr.X_add_number < 0x8000)
5166 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
5170 load_register (AT, &imm_expr, dbl);
5171 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
5190 if (imm_expr.X_op == O_constant
5191 && imm_expr.X_add_number >= 0
5192 && imm_expr.X_add_number < 0x10000)
5194 if (mask != M_NOR_I)
5195 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
5198 macro_build (&imm_expr, "ori", "t,r,i",
5199 treg, sreg, BFD_RELOC_LO16);
5200 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
5206 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5207 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
5211 switch (imm_expr.X_add_number)
5214 macro_build (NULL, "nop", "");
5217 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
5220 macro_build (NULL, "balign", "t,s,2", treg, sreg,
5221 (int) imm_expr.X_add_number);
5240 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5242 macro_build (&offset_expr, s, "s,t,p", sreg, ZERO);
5246 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5247 macro_build (&offset_expr, s, "s,t,p", sreg, AT);
5255 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
5260 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg);
5264 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
5265 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5271 /* Check for > max integer. */
5272 maxnum = 0x7fffffff;
5273 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5280 if (imm_expr.X_op == O_constant
5281 && imm_expr.X_add_number >= maxnum
5282 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5285 /* Result is always false. */
5287 macro_build (NULL, "nop", "");
5289 macro_build (&offset_expr, "bnel", "s,t,p", ZERO, ZERO);
5292 if (imm_expr.X_op != O_constant)
5293 as_bad (_("Unsupported large constant"));
5294 ++imm_expr.X_add_number;
5298 if (mask == M_BGEL_I)
5300 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5302 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
5305 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5307 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
5310 maxnum = 0x7fffffff;
5311 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5318 maxnum = - maxnum - 1;
5319 if (imm_expr.X_op == O_constant
5320 && imm_expr.X_add_number <= maxnum
5321 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5324 /* result is always true */
5325 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
5326 macro_build (&offset_expr, "b", "p");
5331 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5341 macro_build (&offset_expr, likely ? "beql" : "beq",
5342 "s,t,p", ZERO, treg);
5346 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
5347 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5355 && imm_expr.X_op == O_constant
5356 && imm_expr.X_add_number == -1))
5358 if (imm_expr.X_op != O_constant)
5359 as_bad (_("Unsupported large constant"));
5360 ++imm_expr.X_add_number;
5364 if (mask == M_BGEUL_I)
5366 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5368 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5370 macro_build (&offset_expr, likely ? "bnel" : "bne",
5371 "s,t,p", sreg, ZERO);
5376 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5384 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
5389 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg);
5393 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
5394 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5402 macro_build (&offset_expr, likely ? "bnel" : "bne",
5403 "s,t,p", sreg, ZERO);
5409 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
5410 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5418 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
5423 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg);
5427 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
5428 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5434 maxnum = 0x7fffffff;
5435 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5442 if (imm_expr.X_op == O_constant
5443 && imm_expr.X_add_number >= maxnum
5444 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5446 if (imm_expr.X_op != O_constant)
5447 as_bad (_("Unsupported large constant"));
5448 ++imm_expr.X_add_number;
5452 if (mask == M_BLTL_I)
5454 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5456 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
5459 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5461 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
5466 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5474 macro_build (&offset_expr, likely ? "beql" : "beq",
5475 "s,t,p", sreg, ZERO);
5481 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
5482 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5490 && imm_expr.X_op == O_constant
5491 && imm_expr.X_add_number == -1))
5493 if (imm_expr.X_op != O_constant)
5494 as_bad (_("Unsupported large constant"));
5495 ++imm_expr.X_add_number;
5499 if (mask == M_BLTUL_I)
5501 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5503 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5505 macro_build (&offset_expr, likely ? "beql" : "beq",
5506 "s,t,p", sreg, ZERO);
5511 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5519 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
5524 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg);
5528 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
5529 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5539 macro_build (&offset_expr, likely ? "bnel" : "bne",
5540 "s,t,p", ZERO, treg);
5544 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
5545 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5550 /* Use unsigned arithmetic. */
5554 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5556 as_bad (_("Unsupported large constant"));
5561 pos = imm_expr.X_add_number;
5562 size = imm2_expr.X_add_number;
5567 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
5570 if (size == 0 || size > 64 || (pos + size - 1) > 63)
5572 as_bad (_("Improper extract size (%lu, position %lu)"),
5573 (unsigned long) size, (unsigned long) pos);
5577 if (size <= 32 && pos < 32)
5582 else if (size <= 32)
5592 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
5599 /* Use unsigned arithmetic. */
5603 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5605 as_bad (_("Unsupported large constant"));
5610 pos = imm_expr.X_add_number;
5611 size = imm2_expr.X_add_number;
5616 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
5619 if (size == 0 || size > 64 || (pos + size - 1) > 63)
5621 as_bad (_("Improper insert size (%lu, position %lu)"),
5622 (unsigned long) size, (unsigned long) pos);
5626 if (pos < 32 && (pos + size - 1) < 32)
5641 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
5642 (int) (pos + size - 1));
5658 as_warn (_("Divide by zero."));
5660 macro_build (NULL, "teq", "s,t,q", ZERO, ZERO, 7);
5662 macro_build (NULL, "break", "c", 7);
5669 macro_build (NULL, "teq", "s,t,q", treg, ZERO, 7);
5670 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
5674 expr1.X_add_number = 8;
5675 macro_build (&expr1, "bne", "s,t,p", treg, ZERO);
5676 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
5677 macro_build (NULL, "break", "c", 7);
5679 expr1.X_add_number = -1;
5681 load_register (AT, &expr1, dbl);
5682 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
5683 macro_build (&expr1, "bne", "s,t,p", treg, AT);
5686 expr1.X_add_number = 1;
5687 load_register (AT, &expr1, dbl);
5688 macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31);
5692 expr1.X_add_number = 0x80000000;
5693 macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16);
5697 macro_build (NULL, "teq", "s,t,q", sreg, AT, 6);
5698 /* We want to close the noreorder block as soon as possible, so
5699 that later insns are available for delay slot filling. */
5704 expr1.X_add_number = 8;
5705 macro_build (&expr1, "bne", "s,t,p", sreg, AT);
5706 macro_build (NULL, "nop", "");
5708 /* We want to close the noreorder block as soon as possible, so
5709 that later insns are available for delay slot filling. */
5712 macro_build (NULL, "break", "c", 6);
5714 macro_build (NULL, s, "d", dreg);
5753 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5755 as_warn (_("Divide by zero."));
5757 macro_build (NULL, "teq", "s,t,q", ZERO, ZERO, 7);
5759 macro_build (NULL, "break", "c", 7);
5762 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5764 if (strcmp (s2, "mflo") == 0)
5765 move_register (dreg, sreg);
5767 move_register (dreg, ZERO);
5770 if (imm_expr.X_op == O_constant
5771 && imm_expr.X_add_number == -1
5772 && s[strlen (s) - 1] != 'u')
5774 if (strcmp (s2, "mflo") == 0)
5776 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
5779 move_register (dreg, ZERO);
5784 load_register (AT, &imm_expr, dbl);
5785 macro_build (NULL, s, "z,s,t", sreg, AT);
5786 macro_build (NULL, s2, "d", dreg);
5808 macro_build (NULL, "teq", "s,t,q", treg, ZERO, 7);
5809 macro_build (NULL, s, "z,s,t", sreg, treg);
5810 /* We want to close the noreorder block as soon as possible, so
5811 that later insns are available for delay slot filling. */
5816 expr1.X_add_number = 8;
5817 macro_build (&expr1, "bne", "s,t,p", treg, ZERO);
5818 macro_build (NULL, s, "z,s,t", sreg, treg);
5820 /* We want to close the noreorder block as soon as possible, so
5821 that later insns are available for delay slot filling. */
5823 macro_build (NULL, "break", "c", 7);
5825 macro_build (NULL, s2, "d", dreg);
5837 /* Load the address of a symbol into a register. If breg is not
5838 zero, we then add a base register to it. */
5840 if (dbl && HAVE_32BIT_GPRS)
5841 as_warn (_("dla used to load 32-bit register"));
5843 if (!dbl && HAVE_64BIT_OBJECTS)
5844 as_warn (_("la used to load 64-bit address"));
5846 if (offset_expr.X_op == O_constant
5847 && offset_expr.X_add_number >= -0x8000
5848 && offset_expr.X_add_number < 0x8000)
5850 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
5851 "t,r,j", treg, sreg, BFD_RELOC_LO16);
5855 if (mips_opts.at && (treg == breg))
5865 if (offset_expr.X_op != O_symbol
5866 && offset_expr.X_op != O_constant)
5868 as_bad (_("Expression too complex"));
5869 offset_expr.X_op = O_constant;
5872 if (offset_expr.X_op == O_constant)
5873 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
5874 else if (mips_pic == NO_PIC)
5876 /* If this is a reference to a GP relative symbol, we want
5877 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5879 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5880 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5881 If we have a constant, we need two instructions anyhow,
5882 so we may as well always use the latter form.
5884 With 64bit address space and a usable $at we want
5885 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5886 lui $at,<sym> (BFD_RELOC_HI16_S)
5887 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5888 daddiu $at,<sym> (BFD_RELOC_LO16)
5890 daddu $tempreg,$tempreg,$at
5892 If $at is already in use, we use a path which is suboptimal
5893 on superscalar processors.
5894 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5895 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5897 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5899 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
5901 For GP relative symbols in 64bit address space we can use
5902 the same sequence as in 32bit address space. */
5903 if (HAVE_64BIT_SYMBOLS)
5905 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5906 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5908 relax_start (offset_expr.X_add_symbol);
5909 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5910 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5914 if (used_at == 0 && mips_opts.at)
5916 macro_build (&offset_expr, "lui", "t,u",
5917 tempreg, BFD_RELOC_MIPS_HIGHEST);
5918 macro_build (&offset_expr, "lui", "t,u",
5919 AT, BFD_RELOC_HI16_S);
5920 macro_build (&offset_expr, "daddiu", "t,r,j",
5921 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5922 macro_build (&offset_expr, "daddiu", "t,r,j",
5923 AT, AT, BFD_RELOC_LO16);
5924 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
5925 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
5930 macro_build (&offset_expr, "lui", "t,u",
5931 tempreg, BFD_RELOC_MIPS_HIGHEST);
5932 macro_build (&offset_expr, "daddiu", "t,r,j",
5933 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5934 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5935 macro_build (&offset_expr, "daddiu", "t,r,j",
5936 tempreg, tempreg, BFD_RELOC_HI16_S);
5937 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5938 macro_build (&offset_expr, "daddiu", "t,r,j",
5939 tempreg, tempreg, BFD_RELOC_LO16);
5942 if (mips_relax.sequence)
5947 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5948 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5950 relax_start (offset_expr.X_add_symbol);
5951 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5952 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5955 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
5956 as_bad (_("Offset too large"));
5957 macro_build_lui (&offset_expr, tempreg);
5958 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5959 tempreg, tempreg, BFD_RELOC_LO16);
5960 if (mips_relax.sequence)
5964 else if (!mips_big_got && !HAVE_NEWABI)
5966 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5968 /* If this is a reference to an external symbol, and there
5969 is no constant, we want
5970 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5971 or for lca or if tempreg is PIC_CALL_REG
5972 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5973 For a local symbol, we want
5974 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5976 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5978 If we have a small constant, and this is a reference to
5979 an external symbol, we want
5980 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5982 addiu $tempreg,$tempreg,<constant>
5983 For a local symbol, we want the same instruction
5984 sequence, but we output a BFD_RELOC_LO16 reloc on the
5987 If we have a large constant, and this is a reference to
5988 an external symbol, we want
5989 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5990 lui $at,<hiconstant>
5991 addiu $at,$at,<loconstant>
5992 addu $tempreg,$tempreg,$at
5993 For a local symbol, we want the same instruction
5994 sequence, but we output a BFD_RELOC_LO16 reloc on the
5998 if (offset_expr.X_add_number == 0)
6000 if (mips_pic == SVR4_PIC
6002 && (call || tempreg == PIC_CALL_REG))
6003 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
6005 relax_start (offset_expr.X_add_symbol);
6006 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6007 lw_reloc_type, mips_gp_register);
6010 /* We're going to put in an addu instruction using
6011 tempreg, so we may as well insert the nop right
6016 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6017 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
6019 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6020 tempreg, tempreg, BFD_RELOC_LO16);
6022 /* FIXME: If breg == 0, and the next instruction uses
6023 $tempreg, then if this variant case is used an extra
6024 nop will be generated. */
6026 else if (offset_expr.X_add_number >= -0x8000
6027 && offset_expr.X_add_number < 0x8000)
6029 load_got_offset (tempreg, &offset_expr);
6031 add_got_offset (tempreg, &offset_expr);
6035 expr1.X_add_number = offset_expr.X_add_number;
6036 offset_expr.X_add_number =
6037 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
6038 load_got_offset (tempreg, &offset_expr);
6039 offset_expr.X_add_number = expr1.X_add_number;
6040 /* If we are going to add in a base register, and the
6041 target register and the base register are the same,
6042 then we are using AT as a temporary register. Since
6043 we want to load the constant into AT, we add our
6044 current AT (from the global offset table) and the
6045 register into the register now, and pretend we were
6046 not using a base register. */
6050 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6055 add_got_offset_hilo (tempreg, &offset_expr, AT);
6059 else if (!mips_big_got && HAVE_NEWABI)
6061 int add_breg_early = 0;
6063 /* If this is a reference to an external, and there is no
6064 constant, or local symbol (*), with or without a
6066 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6067 or for lca or if tempreg is PIC_CALL_REG
6068 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
6070 If we have a small constant, and this is a reference to
6071 an external symbol, we want
6072 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6073 addiu $tempreg,$tempreg,<constant>
6075 If we have a large constant, and this is a reference to
6076 an external symbol, we want
6077 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6078 lui $at,<hiconstant>
6079 addiu $at,$at,<loconstant>
6080 addu $tempreg,$tempreg,$at
6082 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
6083 local symbols, even though it introduces an additional
6086 if (offset_expr.X_add_number)
6088 expr1.X_add_number = offset_expr.X_add_number;
6089 offset_expr.X_add_number = 0;
6091 relax_start (offset_expr.X_add_symbol);
6092 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6093 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6095 if (expr1.X_add_number >= -0x8000
6096 && expr1.X_add_number < 0x8000)
6098 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
6099 tempreg, tempreg, BFD_RELOC_LO16);
6101 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
6103 /* If we are going to add in a base register, and the
6104 target register and the base register are the same,
6105 then we are using AT as a temporary register. Since
6106 we want to load the constant into AT, we add our
6107 current AT (from the global offset table) and the
6108 register into the register now, and pretend we were
6109 not using a base register. */
6114 gas_assert (tempreg == AT);
6115 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6121 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
6122 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6128 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
6131 offset_expr.X_add_number = expr1.X_add_number;
6133 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6134 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6137 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6138 treg, tempreg, breg);
6144 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
6146 relax_start (offset_expr.X_add_symbol);
6147 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6148 BFD_RELOC_MIPS_CALL16, mips_gp_register);
6150 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6151 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6156 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6157 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6160 else if (mips_big_got && !HAVE_NEWABI)
6163 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
6164 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
6165 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6167 /* This is the large GOT case. If this is a reference to an
6168 external symbol, and there is no constant, we want
6169 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6170 addu $tempreg,$tempreg,$gp
6171 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6172 or for lca or if tempreg is PIC_CALL_REG
6173 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6174 addu $tempreg,$tempreg,$gp
6175 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
6176 For a local symbol, we want
6177 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6179 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6181 If we have a small constant, and this is a reference to
6182 an external symbol, we want
6183 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6184 addu $tempreg,$tempreg,$gp
6185 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6187 addiu $tempreg,$tempreg,<constant>
6188 For a local symbol, we want
6189 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6191 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
6193 If we have a large constant, and this is a reference to
6194 an external symbol, we want
6195 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6196 addu $tempreg,$tempreg,$gp
6197 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6198 lui $at,<hiconstant>
6199 addiu $at,$at,<loconstant>
6200 addu $tempreg,$tempreg,$at
6201 For a local symbol, we want
6202 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6203 lui $at,<hiconstant>
6204 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
6205 addu $tempreg,$tempreg,$at
6208 expr1.X_add_number = offset_expr.X_add_number;
6209 offset_expr.X_add_number = 0;
6210 relax_start (offset_expr.X_add_symbol);
6211 gpdelay = reg_needs_delay (mips_gp_register);
6212 if (expr1.X_add_number == 0 && breg == 0
6213 && (call || tempreg == PIC_CALL_REG))
6215 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
6216 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
6218 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
6219 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6220 tempreg, tempreg, mips_gp_register);
6221 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6222 tempreg, lw_reloc_type, tempreg);
6223 if (expr1.X_add_number == 0)
6227 /* We're going to put in an addu instruction using
6228 tempreg, so we may as well insert the nop right
6233 else if (expr1.X_add_number >= -0x8000
6234 && expr1.X_add_number < 0x8000)
6237 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
6238 tempreg, tempreg, BFD_RELOC_LO16);
6242 /* If we are going to add in a base register, and the
6243 target register and the base register are the same,
6244 then we are using AT as a temporary register. Since
6245 we want to load the constant into AT, we add our
6246 current AT (from the global offset table) and the
6247 register into the register now, and pretend we were
6248 not using a base register. */
6253 gas_assert (tempreg == AT);
6255 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6260 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
6261 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
6265 offset_expr.X_add_number =
6266 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000;
6271 /* This is needed because this instruction uses $gp, but
6272 the first instruction on the main stream does not. */
6273 macro_build (NULL, "nop", "");
6276 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6277 local_reloc_type, mips_gp_register);
6278 if (expr1.X_add_number >= -0x8000
6279 && expr1.X_add_number < 0x8000)
6282 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6283 tempreg, tempreg, BFD_RELOC_LO16);
6284 /* FIXME: If add_number is 0, and there was no base
6285 register, the external symbol case ended with a load,
6286 so if the symbol turns out to not be external, and
6287 the next instruction uses tempreg, an unnecessary nop
6288 will be inserted. */
6294 /* We must add in the base register now, as in the
6295 external symbol case. */
6296 gas_assert (tempreg == AT);
6298 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6301 /* We set breg to 0 because we have arranged to add
6302 it in in both cases. */
6306 macro_build_lui (&expr1, AT);
6307 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6308 AT, AT, BFD_RELOC_LO16);
6309 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6310 tempreg, tempreg, AT);
6315 else if (mips_big_got && HAVE_NEWABI)
6317 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
6318 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
6319 int add_breg_early = 0;
6321 /* This is the large GOT case. If this is a reference to an
6322 external symbol, and there is no constant, we want
6323 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6324 add $tempreg,$tempreg,$gp
6325 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6326 or for lca or if tempreg is PIC_CALL_REG
6327 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6328 add $tempreg,$tempreg,$gp
6329 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
6331 If we have a small constant, and this is a reference to
6332 an external symbol, we want
6333 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6334 add $tempreg,$tempreg,$gp
6335 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6336 addi $tempreg,$tempreg,<constant>
6338 If we have a large constant, and this is a reference to
6339 an external symbol, we want
6340 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6341 addu $tempreg,$tempreg,$gp
6342 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6343 lui $at,<hiconstant>
6344 addi $at,$at,<loconstant>
6345 add $tempreg,$tempreg,$at
6347 If we have NewABI, and we know it's a local symbol, we want
6348 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6349 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6350 otherwise we have to resort to GOT_HI16/GOT_LO16. */
6352 relax_start (offset_expr.X_add_symbol);
6354 expr1.X_add_number = offset_expr.X_add_number;
6355 offset_expr.X_add_number = 0;
6357 if (expr1.X_add_number == 0 && breg == 0
6358 && (call || tempreg == PIC_CALL_REG))
6360 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
6361 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
6363 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
6364 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6365 tempreg, tempreg, mips_gp_register);
6366 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6367 tempreg, lw_reloc_type, tempreg);
6369 if (expr1.X_add_number == 0)
6371 else if (expr1.X_add_number >= -0x8000
6372 && expr1.X_add_number < 0x8000)
6374 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
6375 tempreg, tempreg, BFD_RELOC_LO16);
6377 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
6379 /* If we are going to add in a base register, and the
6380 target register and the base register are the same,
6381 then we are using AT as a temporary register. Since
6382 we want to load the constant into AT, we add our
6383 current AT (from the global offset table) and the
6384 register into the register now, and pretend we were
6385 not using a base register. */
6390 gas_assert (tempreg == AT);
6391 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6397 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
6398 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
6403 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
6406 offset_expr.X_add_number = expr1.X_add_number;
6407 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6408 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6409 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6410 tempreg, BFD_RELOC_MIPS_GOT_OFST);
6413 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6414 treg, tempreg, breg);
6424 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
6429 unsigned long temp = (treg << 16) | (0x01);
6430 macro_build (NULL, "c2", "C", temp);
6436 unsigned long temp = (0x02);
6437 macro_build (NULL, "c2", "C", temp);
6443 unsigned long temp = (treg << 16) | (0x02);
6444 macro_build (NULL, "c2", "C", temp);
6449 macro_build (NULL, "c2", "C", 3);
6454 unsigned long temp = (treg << 16) | 0x03;
6455 macro_build (NULL, "c2", "C", temp);
6460 /* The j instruction may not be used in PIC code, since it
6461 requires an absolute address. We convert it to a b
6463 if (mips_pic == NO_PIC)
6464 macro_build (&offset_expr, "j", "a");
6466 macro_build (&offset_expr, "b", "p");
6469 /* The jal instructions must be handled as macros because when
6470 generating PIC code they expand to multi-instruction
6471 sequences. Normally they are simple instructions. */
6476 if (mips_pic == NO_PIC)
6477 macro_build (NULL, "jalr", "d,s", dreg, sreg);
6480 if (sreg != PIC_CALL_REG)
6481 as_warn (_("MIPS PIC call to register other than $25"));
6483 macro_build (NULL, "jalr", "d,s", dreg, sreg);
6484 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
6486 if (mips_cprestore_offset < 0)
6487 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6490 if (!mips_frame_reg_valid)
6492 as_warn (_("No .frame pseudo-op used in PIC code"));
6493 /* Quiet this warning. */
6494 mips_frame_reg_valid = 1;
6496 if (!mips_cprestore_valid)
6498 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6499 /* Quiet this warning. */
6500 mips_cprestore_valid = 1;
6502 if (mips_opts.noreorder)
6503 macro_build (NULL, "nop", "");
6504 expr1.X_add_number = mips_cprestore_offset;
6505 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
6508 HAVE_64BIT_ADDRESSES);
6516 if (mips_pic == NO_PIC)
6517 macro_build (&offset_expr, "jal", "a");
6518 else if (mips_pic == SVR4_PIC)
6520 /* If this is a reference to an external symbol, and we are
6521 using a small GOT, we want
6522 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
6526 lw $gp,cprestore($sp)
6527 The cprestore value is set using the .cprestore
6528 pseudo-op. If we are using a big GOT, we want
6529 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6531 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
6535 lw $gp,cprestore($sp)
6536 If the symbol is not external, we want
6537 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6539 addiu $25,$25,<sym> (BFD_RELOC_LO16)
6542 lw $gp,cprestore($sp)
6544 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
6545 sequences above, minus nops, unless the symbol is local,
6546 which enables us to use GOT_PAGE/GOT_OFST (big got) or
6552 relax_start (offset_expr.X_add_symbol);
6553 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6554 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
6557 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6558 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
6564 relax_start (offset_expr.X_add_symbol);
6565 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
6566 BFD_RELOC_MIPS_CALL_HI16);
6567 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
6568 PIC_CALL_REG, mips_gp_register);
6569 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6570 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
6573 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6574 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
6576 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6577 PIC_CALL_REG, PIC_CALL_REG,
6578 BFD_RELOC_MIPS_GOT_OFST);
6582 macro_build_jalr (&offset_expr);
6586 relax_start (offset_expr.X_add_symbol);
6589 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6590 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
6599 gpdelay = reg_needs_delay (mips_gp_register);
6600 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
6601 BFD_RELOC_MIPS_CALL_HI16);
6602 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
6603 PIC_CALL_REG, mips_gp_register);
6604 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6605 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
6610 macro_build (NULL, "nop", "");
6612 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6613 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
6616 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6617 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
6619 macro_build_jalr (&offset_expr);
6621 if (mips_cprestore_offset < 0)
6622 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6625 if (!mips_frame_reg_valid)
6627 as_warn (_("No .frame pseudo-op used in PIC code"));
6628 /* Quiet this warning. */
6629 mips_frame_reg_valid = 1;
6631 if (!mips_cprestore_valid)
6633 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6634 /* Quiet this warning. */
6635 mips_cprestore_valid = 1;
6637 if (mips_opts.noreorder)
6638 macro_build (NULL, "nop", "");
6639 expr1.X_add_number = mips_cprestore_offset;
6640 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
6643 HAVE_64BIT_ADDRESSES);
6647 else if (mips_pic == VXWORKS_PIC)
6648 as_bad (_("Non-PIC jump used in PIC library"));
6671 /* Itbl support may require additional care here. */
6676 /* Itbl support may require additional care here. */
6681 /* Itbl support may require additional care here. */
6686 /* Itbl support may require additional care here. */
6699 /* Itbl support may require additional care here. */
6704 /* Itbl support may require additional care here. */
6709 /* Itbl support may require additional care here. */
6729 if (breg == treg || coproc || lr)
6750 /* Itbl support may require additional care here. */
6755 /* Itbl support may require additional care here. */
6760 /* Itbl support may require additional care here. */
6765 /* Itbl support may require additional care here. */
6789 /* Itbl support may require additional care here. */
6793 /* Itbl support may require additional care here. */
6798 /* Itbl support may require additional care here. */
6811 && NO_ISA_COP (mips_opts.arch)
6812 && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0)
6814 as_bad (_("Opcode not supported on this processor: %s"),
6815 mips_cpu_info_from_arch (mips_opts.arch)->name);
6819 /* Itbl support may require additional care here. */
6820 if (mask == M_LWC1_AB
6821 || mask == M_SWC1_AB
6822 || mask == M_LDC1_AB
6823 || mask == M_SDC1_AB
6827 else if (mask == M_CACHE_AB || mask == M_PREF_AB)
6834 if (offset_expr.X_op != O_constant
6835 && offset_expr.X_op != O_symbol)
6837 as_bad (_("Expression too complex"));
6838 offset_expr.X_op = O_constant;
6841 if (HAVE_32BIT_ADDRESSES
6842 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
6846 sprintf_vma (value, offset_expr.X_add_number);
6847 as_bad (_("Number (0x%s) larger than 32 bits"), value);
6850 /* A constant expression in PIC code can be handled just as it
6851 is in non PIC code. */
6852 if (offset_expr.X_op == O_constant)
6854 expr1.X_add_number = offset_expr.X_add_number;
6855 normalize_address_expr (&expr1);
6856 if (!IS_SEXT_16BIT_NUM (expr1.X_add_number))
6858 expr1.X_add_number = ((expr1.X_add_number + 0x8000)
6859 & ~(bfd_vma) 0xffff);
6860 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
6862 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6863 tempreg, tempreg, breg);
6866 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg);
6868 else if (mips_pic == NO_PIC)
6870 /* If this is a reference to a GP relative symbol, and there
6871 is no base register, we want
6872 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6873 Otherwise, if there is no base register, we want
6874 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6875 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6876 If we have a constant, we need two instructions anyhow,
6877 so we always use the latter form.
6879 If we have a base register, and this is a reference to a
6880 GP relative symbol, we want
6881 addu $tempreg,$breg,$gp
6882 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6884 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6885 addu $tempreg,$tempreg,$breg
6886 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6887 With a constant we always use the latter case.
6889 With 64bit address space and no base register and $at usable,
6891 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6892 lui $at,<sym> (BFD_RELOC_HI16_S)
6893 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6896 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6897 If we have a base register, we want
6898 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6899 lui $at,<sym> (BFD_RELOC_HI16_S)
6900 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6904 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6906 Without $at we can't generate the optimal path for superscalar
6907 processors here since this would require two temporary registers.
6908 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6909 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6911 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6913 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6914 If we have a base register, we want
6915 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6916 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6918 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6920 daddu $tempreg,$tempreg,$breg
6921 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6923 For GP relative symbols in 64bit address space we can use
6924 the same sequence as in 32bit address space. */
6925 if (HAVE_64BIT_SYMBOLS)
6927 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6928 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6930 relax_start (offset_expr.X_add_symbol);
6933 macro_build (&offset_expr, s, fmt, treg,
6934 BFD_RELOC_GPREL16, mips_gp_register);
6938 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6939 tempreg, breg, mips_gp_register);
6940 macro_build (&offset_expr, s, fmt, treg,
6941 BFD_RELOC_GPREL16, tempreg);
6946 if (used_at == 0 && mips_opts.at)
6948 macro_build (&offset_expr, "lui", "t,u", tempreg,
6949 BFD_RELOC_MIPS_HIGHEST);
6950 macro_build (&offset_expr, "lui", "t,u", AT,
6952 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6953 tempreg, BFD_RELOC_MIPS_HIGHER);
6955 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
6956 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
6957 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
6958 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
6964 macro_build (&offset_expr, "lui", "t,u", tempreg,
6965 BFD_RELOC_MIPS_HIGHEST);
6966 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6967 tempreg, BFD_RELOC_MIPS_HIGHER);
6968 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6969 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6970 tempreg, BFD_RELOC_HI16_S);
6971 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6973 macro_build (NULL, "daddu", "d,v,t",
6974 tempreg, tempreg, breg);
6975 macro_build (&offset_expr, s, fmt, treg,
6976 BFD_RELOC_LO16, tempreg);
6979 if (mips_relax.sequence)
6986 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6987 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6989 relax_start (offset_expr.X_add_symbol);
6990 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
6994 macro_build_lui (&offset_expr, tempreg);
6995 macro_build (&offset_expr, s, fmt, treg,
6996 BFD_RELOC_LO16, tempreg);
6997 if (mips_relax.sequence)
7002 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7003 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7005 relax_start (offset_expr.X_add_symbol);
7006 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7007 tempreg, breg, mips_gp_register);
7008 macro_build (&offset_expr, s, fmt, treg,
7009 BFD_RELOC_GPREL16, tempreg);
7012 macro_build_lui (&offset_expr, tempreg);
7013 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7014 tempreg, tempreg, breg);
7015 macro_build (&offset_expr, s, fmt, treg,
7016 BFD_RELOC_LO16, tempreg);
7017 if (mips_relax.sequence)
7021 else if (!mips_big_got)
7023 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7025 /* If this is a reference to an external symbol, we want
7026 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7028 <op> $treg,0($tempreg)
7030 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7032 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7033 <op> $treg,0($tempreg)
7036 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7037 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
7039 If there is a base register, we add it to $tempreg before
7040 the <op>. If there is a constant, we stick it in the
7041 <op> instruction. We don't handle constants larger than
7042 16 bits, because we have no way to load the upper 16 bits
7043 (actually, we could handle them for the subset of cases
7044 in which we are not using $at). */
7045 gas_assert (offset_expr.X_op == O_symbol);
7048 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7049 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
7051 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7052 tempreg, tempreg, breg);
7053 macro_build (&offset_expr, s, fmt, treg,
7054 BFD_RELOC_MIPS_GOT_OFST, tempreg);
7057 expr1.X_add_number = offset_expr.X_add_number;
7058 offset_expr.X_add_number = 0;
7059 if (expr1.X_add_number < -0x8000
7060 || expr1.X_add_number >= 0x8000)
7061 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7062 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7063 lw_reloc_type, mips_gp_register);
7065 relax_start (offset_expr.X_add_symbol);
7067 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
7068 tempreg, BFD_RELOC_LO16);
7071 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7072 tempreg, tempreg, breg);
7073 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
7075 else if (mips_big_got && !HAVE_NEWABI)
7079 /* If this is a reference to an external symbol, we want
7080 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7081 addu $tempreg,$tempreg,$gp
7082 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7083 <op> $treg,0($tempreg)
7085 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7087 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7088 <op> $treg,0($tempreg)
7089 If there is a base register, we add it to $tempreg before
7090 the <op>. If there is a constant, we stick it in the
7091 <op> instruction. We don't handle constants larger than
7092 16 bits, because we have no way to load the upper 16 bits
7093 (actually, we could handle them for the subset of cases
7094 in which we are not using $at). */
7095 gas_assert (offset_expr.X_op == O_symbol);
7096 expr1.X_add_number = offset_expr.X_add_number;
7097 offset_expr.X_add_number = 0;
7098 if (expr1.X_add_number < -0x8000
7099 || expr1.X_add_number >= 0x8000)
7100 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7101 gpdelay = reg_needs_delay (mips_gp_register);
7102 relax_start (offset_expr.X_add_symbol);
7103 macro_build (&offset_expr, "lui", "t,u", tempreg,
7104 BFD_RELOC_MIPS_GOT_HI16);
7105 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
7107 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7108 BFD_RELOC_MIPS_GOT_LO16, tempreg);
7111 macro_build (NULL, "nop", "");
7112 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7113 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7115 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
7116 tempreg, BFD_RELOC_LO16);
7120 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7121 tempreg, tempreg, breg);
7122 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
7124 else if (mips_big_got && HAVE_NEWABI)
7126 /* If this is a reference to an external symbol, we want
7127 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7128 add $tempreg,$tempreg,$gp
7129 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7130 <op> $treg,<ofst>($tempreg)
7131 Otherwise, for local symbols, we want:
7132 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7133 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
7134 gas_assert (offset_expr.X_op == O_symbol);
7135 expr1.X_add_number = offset_expr.X_add_number;
7136 offset_expr.X_add_number = 0;
7137 if (expr1.X_add_number < -0x8000
7138 || expr1.X_add_number >= 0x8000)
7139 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7140 relax_start (offset_expr.X_add_symbol);
7141 macro_build (&offset_expr, "lui", "t,u", tempreg,
7142 BFD_RELOC_MIPS_GOT_HI16);
7143 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
7145 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7146 BFD_RELOC_MIPS_GOT_LO16, tempreg);
7148 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7149 tempreg, tempreg, breg);
7150 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
7153 offset_expr.X_add_number = expr1.X_add_number;
7154 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7155 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
7157 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7158 tempreg, tempreg, breg);
7159 macro_build (&offset_expr, s, fmt, treg,
7160 BFD_RELOC_MIPS_GOT_OFST, tempreg);
7170 load_register (treg, &imm_expr, 0);
7174 load_register (treg, &imm_expr, 1);
7178 if (imm_expr.X_op == O_constant)
7181 load_register (AT, &imm_expr, 0);
7182 macro_build (NULL, "mtc1", "t,G", AT, treg);
7187 gas_assert (offset_expr.X_op == O_symbol
7188 && strcmp (segment_name (S_GET_SEGMENT
7189 (offset_expr.X_add_symbol)),
7191 && offset_expr.X_add_number == 0);
7192 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
7193 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
7198 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
7199 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
7200 order 32 bits of the value and the low order 32 bits are either
7201 zero or in OFFSET_EXPR. */
7202 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
7204 if (HAVE_64BIT_GPRS)
7205 load_register (treg, &imm_expr, 1);
7210 if (target_big_endian)
7222 load_register (hreg, &imm_expr, 0);
7225 if (offset_expr.X_op == O_absent)
7226 move_register (lreg, 0);
7229 gas_assert (offset_expr.X_op == O_constant);
7230 load_register (lreg, &offset_expr, 0);
7237 /* We know that sym is in the .rdata section. First we get the
7238 upper 16 bits of the address. */
7239 if (mips_pic == NO_PIC)
7241 macro_build_lui (&offset_expr, AT);
7246 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7247 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7251 /* Now we load the register(s). */
7252 if (HAVE_64BIT_GPRS)
7255 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7260 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7263 /* FIXME: How in the world do we deal with the possible
7265 offset_expr.X_add_number += 4;
7266 macro_build (&offset_expr, "lw", "t,o(b)",
7267 treg + 1, BFD_RELOC_LO16, AT);
7273 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
7274 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
7275 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
7276 the value and the low order 32 bits are either zero or in
7278 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
7281 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
7282 if (HAVE_64BIT_FPRS)
7284 gas_assert (HAVE_64BIT_GPRS);
7285 macro_build (NULL, "dmtc1", "t,S", AT, treg);
7289 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
7290 if (offset_expr.X_op == O_absent)
7291 macro_build (NULL, "mtc1", "t,G", 0, treg);
7294 gas_assert (offset_expr.X_op == O_constant);
7295 load_register (AT, &offset_expr, 0);
7296 macro_build (NULL, "mtc1", "t,G", AT, treg);
7302 gas_assert (offset_expr.X_op == O_symbol
7303 && offset_expr.X_add_number == 0);
7304 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
7305 if (strcmp (s, ".lit8") == 0)
7307 if (mips_opts.isa != ISA_MIPS1)
7309 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
7310 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
7313 breg = mips_gp_register;
7314 r = BFD_RELOC_MIPS_LITERAL;
7319 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
7321 if (mips_pic != NO_PIC)
7322 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7323 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7326 /* FIXME: This won't work for a 64 bit address. */
7327 macro_build_lui (&offset_expr, AT);
7330 if (mips_opts.isa != ISA_MIPS1)
7332 macro_build (&offset_expr, "ldc1", "T,o(b)",
7333 treg, BFD_RELOC_LO16, AT);
7342 /* Even on a big endian machine $fn comes before $fn+1. We have
7343 to adjust when loading from memory. */
7346 gas_assert (mips_opts.isa == ISA_MIPS1);
7347 macro_build (&offset_expr, "lwc1", "T,o(b)",
7348 target_big_endian ? treg + 1 : treg, r, breg);
7349 /* FIXME: A possible overflow which I don't know how to deal
7351 offset_expr.X_add_number += 4;
7352 macro_build (&offset_expr, "lwc1", "T,o(b)",
7353 target_big_endian ? treg : treg + 1, r, breg);
7357 gas_assert (mips_opts.isa == ISA_MIPS1);
7358 /* Even on a big endian machine $fn comes before $fn+1. We have
7359 to adjust when storing to memory. */
7360 macro_build (&offset_expr, "swc1", "T,o(b)",
7361 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
7362 offset_expr.X_add_number += 4;
7363 macro_build (&offset_expr, "swc1", "T,o(b)",
7364 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
7369 * The MIPS assembler seems to check for X_add_number not
7370 * being double aligned and generating:
7373 * addiu at,at,%lo(foo+1)
7376 * But, the resulting address is the same after relocation so why
7377 * generate the extra instruction?
7379 /* Itbl support may require additional care here. */
7381 if (mips_opts.isa != ISA_MIPS1)
7392 if (mips_opts.isa != ISA_MIPS1)
7400 /* Itbl support may require additional care here. */
7405 if (HAVE_64BIT_GPRS)
7416 if (HAVE_64BIT_GPRS)
7426 if (offset_expr.X_op != O_symbol
7427 && offset_expr.X_op != O_constant)
7429 as_bad (_("Expression too complex"));
7430 offset_expr.X_op = O_constant;
7433 if (HAVE_32BIT_ADDRESSES
7434 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
7438 sprintf_vma (value, offset_expr.X_add_number);
7439 as_bad (_("Number (0x%s) larger than 32 bits"), value);
7442 /* Even on a big endian machine $fn comes before $fn+1. We have
7443 to adjust when loading from memory. We set coproc if we must
7444 load $fn+1 first. */
7445 /* Itbl support may require additional care here. */
7446 if (!target_big_endian)
7449 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
7451 /* If this is a reference to a GP relative symbol, we want
7452 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
7453 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
7454 If we have a base register, we use this
7456 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
7457 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
7458 If this is not a GP relative symbol, we want
7459 lui $at,<sym> (BFD_RELOC_HI16_S)
7460 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7461 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7462 If there is a base register, we add it to $at after the
7463 lui instruction. If there is a constant, we always use
7465 if (offset_expr.X_op == O_symbol
7466 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7467 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7469 relax_start (offset_expr.X_add_symbol);
7472 tempreg = mips_gp_register;
7476 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7477 AT, breg, mips_gp_register);
7482 /* Itbl support may require additional care here. */
7483 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7484 BFD_RELOC_GPREL16, tempreg);
7485 offset_expr.X_add_number += 4;
7487 /* Set mips_optimize to 2 to avoid inserting an
7489 hold_mips_optimize = mips_optimize;
7491 /* Itbl support may require additional care here. */
7492 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7493 BFD_RELOC_GPREL16, tempreg);
7494 mips_optimize = hold_mips_optimize;
7498 offset_expr.X_add_number -= 4;
7501 macro_build_lui (&offset_expr, AT);
7503 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7504 /* Itbl support may require additional care here. */
7505 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7506 BFD_RELOC_LO16, AT);
7507 /* FIXME: How do we handle overflow here? */
7508 offset_expr.X_add_number += 4;
7509 /* Itbl support may require additional care here. */
7510 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7511 BFD_RELOC_LO16, AT);
7512 if (mips_relax.sequence)
7515 else if (!mips_big_got)
7517 /* If this is a reference to an external symbol, we want
7518 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7523 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7525 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7526 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7527 If there is a base register we add it to $at before the
7528 lwc1 instructions. If there is a constant we include it
7529 in the lwc1 instructions. */
7531 expr1.X_add_number = offset_expr.X_add_number;
7532 if (expr1.X_add_number < -0x8000
7533 || expr1.X_add_number >= 0x8000 - 4)
7534 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7535 load_got_offset (AT, &offset_expr);
7538 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7540 /* Set mips_optimize to 2 to avoid inserting an undesired
7542 hold_mips_optimize = mips_optimize;
7545 /* Itbl support may require additional care here. */
7546 relax_start (offset_expr.X_add_symbol);
7547 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
7548 BFD_RELOC_LO16, AT);
7549 expr1.X_add_number += 4;
7550 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
7551 BFD_RELOC_LO16, AT);
7553 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7554 BFD_RELOC_LO16, AT);
7555 offset_expr.X_add_number += 4;
7556 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7557 BFD_RELOC_LO16, AT);
7560 mips_optimize = hold_mips_optimize;
7562 else if (mips_big_got)
7566 /* If this is a reference to an external symbol, we want
7567 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7569 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
7574 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7576 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7577 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7578 If there is a base register we add it to $at before the
7579 lwc1 instructions. If there is a constant we include it
7580 in the lwc1 instructions. */
7582 expr1.X_add_number = offset_expr.X_add_number;
7583 offset_expr.X_add_number = 0;
7584 if (expr1.X_add_number < -0x8000
7585 || expr1.X_add_number >= 0x8000 - 4)
7586 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7587 gpdelay = reg_needs_delay (mips_gp_register);
7588 relax_start (offset_expr.X_add_symbol);
7589 macro_build (&offset_expr, "lui", "t,u",
7590 AT, BFD_RELOC_MIPS_GOT_HI16);
7591 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7592 AT, AT, mips_gp_register);
7593 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7594 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
7597 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7598 /* Itbl support may require additional care here. */
7599 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
7600 BFD_RELOC_LO16, AT);
7601 expr1.X_add_number += 4;
7603 /* Set mips_optimize to 2 to avoid inserting an undesired
7605 hold_mips_optimize = mips_optimize;
7607 /* Itbl support may require additional care here. */
7608 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
7609 BFD_RELOC_LO16, AT);
7610 mips_optimize = hold_mips_optimize;
7611 expr1.X_add_number -= 4;
7614 offset_expr.X_add_number = expr1.X_add_number;
7616 macro_build (NULL, "nop", "");
7617 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7618 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7621 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7622 /* Itbl support may require additional care here. */
7623 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7624 BFD_RELOC_LO16, AT);
7625 offset_expr.X_add_number += 4;
7627 /* Set mips_optimize to 2 to avoid inserting an undesired
7629 hold_mips_optimize = mips_optimize;
7631 /* Itbl support may require additional care here. */
7632 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7633 BFD_RELOC_LO16, AT);
7634 mips_optimize = hold_mips_optimize;
7643 s = HAVE_64BIT_GPRS ? "ld" : "lw";
7646 s = HAVE_64BIT_GPRS ? "sd" : "sw";
7648 macro_build (&offset_expr, s, "t,o(b)", treg,
7649 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
7651 if (!HAVE_64BIT_GPRS)
7653 offset_expr.X_add_number += 4;
7654 macro_build (&offset_expr, s, "t,o(b)", treg + 1,
7655 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
7660 /* New code added to support COPZ instructions.
7661 This code builds table entries out of the macros in mip_opcodes.
7662 R4000 uses interlocks to handle coproc delays.
7663 Other chips (like the R3000) require nops to be inserted for delays.
7665 FIXME: Currently, we require that the user handle delays.
7666 In order to fill delay slots for non-interlocked chips,
7667 we must have a way to specify delays based on the coprocessor.
7668 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7669 What are the side-effects of the cop instruction?
7670 What cache support might we have and what are its effects?
7671 Both coprocessor & memory require delays. how long???
7672 What registers are read/set/modified?
7674 If an itbl is provided to interpret cop instructions,
7675 this knowledge can be encoded in the itbl spec. */
7689 if (NO_ISA_COP (mips_opts.arch)
7690 && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0)
7692 as_bad (_("opcode not supported on this processor: %s"),
7693 mips_cpu_info_from_arch (mips_opts.arch)->name);
7697 /* For now we just do C (same as Cz). The parameter will be
7698 stored in insn_opcode by mips_ip. */
7699 macro_build (NULL, s, "C", ip->insn_opcode);
7703 move_register (dreg, sreg);
7709 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
7710 macro_build (NULL, "mflo", "d", dreg);
7716 /* The MIPS assembler some times generates shifts and adds. I'm
7717 not trying to be that fancy. GCC should do this for us
7720 load_register (AT, &imm_expr, dbl);
7721 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
7722 macro_build (NULL, "mflo", "d", dreg);
7738 load_register (AT, &imm_expr, dbl);
7739 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
7740 macro_build (NULL, "mflo", "d", dreg);
7741 macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
7742 macro_build (NULL, "mfhi", "d", AT);
7744 macro_build (NULL, "tne", "s,t,q", dreg, AT, 6);
7747 expr1.X_add_number = 8;
7748 macro_build (&expr1, "beq", "s,t,p", dreg, AT);
7749 macro_build (NULL, "nop", "");
7750 macro_build (NULL, "break", "c", 6);
7753 macro_build (NULL, "mflo", "d", dreg);
7769 load_register (AT, &imm_expr, dbl);
7770 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
7771 sreg, imm ? AT : treg);
7772 macro_build (NULL, "mfhi", "d", AT);
7773 macro_build (NULL, "mflo", "d", dreg);
7775 macro_build (NULL, "tne", "s,t,q", AT, ZERO, 6);
7778 expr1.X_add_number = 8;
7779 macro_build (&expr1, "beq", "s,t,p", AT, ZERO);
7780 macro_build (NULL, "nop", "");
7781 macro_build (NULL, "break", "c", 6);
7787 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7798 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
7799 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
7803 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
7804 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
7805 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
7806 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7810 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7821 macro_build (NULL, "negu", "d,w", tempreg, treg);
7822 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
7826 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
7827 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
7828 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
7829 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7838 if (imm_expr.X_op != O_constant)
7839 as_bad (_("Improper rotate count"));
7840 rot = imm_expr.X_add_number & 0x3f;
7841 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7843 rot = (64 - rot) & 0x3f;
7845 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7847 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7852 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7855 l = (rot < 0x20) ? "dsll" : "dsll32";
7856 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
7859 macro_build (NULL, l, "d,w,<", AT, sreg, rot);
7860 macro_build (NULL, rr, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7861 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7869 if (imm_expr.X_op != O_constant)
7870 as_bad (_("Improper rotate count"));
7871 rot = imm_expr.X_add_number & 0x1f;
7872 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7874 macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f);
7879 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7883 macro_build (NULL, "sll", "d,w,<", AT, sreg, rot);
7884 macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7885 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7890 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7892 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
7896 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
7897 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
7898 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
7899 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7903 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7905 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
7909 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
7910 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
7911 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
7912 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7921 if (imm_expr.X_op != O_constant)
7922 as_bad (_("Improper rotate count"));
7923 rot = imm_expr.X_add_number & 0x3f;
7924 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7927 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7929 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7934 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7937 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
7938 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7941 macro_build (NULL, rr, "d,w,<", AT, sreg, rot);
7942 macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7943 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7951 if (imm_expr.X_op != O_constant)
7952 as_bad (_("Improper rotate count"));
7953 rot = imm_expr.X_add_number & 0x1f;
7954 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7956 macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot);
7961 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7965 macro_build (NULL, "srl", "d,w,<", AT, sreg, rot);
7966 macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7967 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7973 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
7975 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7978 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7979 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7984 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7986 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7991 as_warn (_("Instruction %s: result is always false"),
7993 move_register (dreg, 0);
7996 if (CPU_HAS_SEQ (mips_opts.arch)
7997 && -512 <= imm_expr.X_add_number
7998 && imm_expr.X_add_number < 512)
8000 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
8001 (int) imm_expr.X_add_number);
8004 if (imm_expr.X_op == O_constant
8005 && imm_expr.X_add_number >= 0
8006 && imm_expr.X_add_number < 0x10000)
8008 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
8010 else if (imm_expr.X_op == O_constant
8011 && imm_expr.X_add_number > -0x8000
8012 && imm_expr.X_add_number < 0)
8014 imm_expr.X_add_number = -imm_expr.X_add_number;
8015 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
8016 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
8018 else if (CPU_HAS_SEQ (mips_opts.arch))
8021 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8022 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
8027 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8028 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
8031 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
8034 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
8040 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
8041 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
8044 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
8046 if (imm_expr.X_op == O_constant
8047 && imm_expr.X_add_number >= -0x8000
8048 && imm_expr.X_add_number < 0x8000)
8050 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
8051 dreg, sreg, BFD_RELOC_LO16);
8055 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8056 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
8060 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
8063 case M_SGT: /* sreg > treg <==> treg < sreg */
8069 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
8072 case M_SGT_I: /* sreg > I <==> I < sreg */
8079 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8080 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
8083 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
8089 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
8090 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
8093 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
8100 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8101 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
8102 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
8106 if (imm_expr.X_op == O_constant
8107 && imm_expr.X_add_number >= -0x8000
8108 && imm_expr.X_add_number < 0x8000)
8110 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
8114 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8115 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
8119 if (imm_expr.X_op == O_constant
8120 && imm_expr.X_add_number >= -0x8000
8121 && imm_expr.X_add_number < 0x8000)
8123 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
8128 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8129 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
8134 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
8136 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
8139 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
8140 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
8145 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
8147 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
8152 as_warn (_("Instruction %s: result is always true"),
8154 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
8155 dreg, 0, BFD_RELOC_LO16);
8158 if (CPU_HAS_SEQ (mips_opts.arch)
8159 && -512 <= imm_expr.X_add_number
8160 && imm_expr.X_add_number < 512)
8162 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
8163 (int) imm_expr.X_add_number);
8166 if (imm_expr.X_op == O_constant
8167 && imm_expr.X_add_number >= 0
8168 && imm_expr.X_add_number < 0x10000)
8170 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
8172 else if (imm_expr.X_op == O_constant
8173 && imm_expr.X_add_number > -0x8000
8174 && imm_expr.X_add_number < 0)
8176 imm_expr.X_add_number = -imm_expr.X_add_number;
8177 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
8178 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
8180 else if (CPU_HAS_SEQ (mips_opts.arch))
8183 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8184 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
8189 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8190 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
8193 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
8199 if (imm_expr.X_op == O_constant
8200 && imm_expr.X_add_number > -0x8000
8201 && imm_expr.X_add_number <= 0x8000)
8203 imm_expr.X_add_number = -imm_expr.X_add_number;
8204 macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j",
8205 dreg, sreg, BFD_RELOC_LO16);
8209 load_register (AT, &imm_expr, dbl);
8210 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
8216 if (imm_expr.X_op == O_constant
8217 && imm_expr.X_add_number > -0x8000
8218 && imm_expr.X_add_number <= 0x8000)
8220 imm_expr.X_add_number = -imm_expr.X_add_number;
8221 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j",
8222 dreg, sreg, BFD_RELOC_LO16);
8226 load_register (AT, &imm_expr, dbl);
8227 macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
8249 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8250 macro_build (NULL, s, "s,t", sreg, AT);
8255 gas_assert (mips_opts.isa == ISA_MIPS1);
8257 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
8258 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
8261 * Is the double cfc1 instruction a bug in the mips assembler;
8262 * or is there a reason for it?
8265 macro_build (NULL, "cfc1", "t,G", treg, RA);
8266 macro_build (NULL, "cfc1", "t,G", treg, RA);
8267 macro_build (NULL, "nop", "");
8268 expr1.X_add_number = 3;
8269 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
8270 expr1.X_add_number = 2;
8271 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
8272 macro_build (NULL, "ctc1", "t,G", AT, RA);
8273 macro_build (NULL, "nop", "");
8274 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
8276 macro_build (NULL, "ctc1", "t,G", treg, RA);
8277 macro_build (NULL, "nop", "");
8288 if (offset_expr.X_add_number >= 0x7fff)
8289 as_bad (_("Operand overflow"));
8290 if (!target_big_endian)
8291 ++offset_expr.X_add_number;
8292 macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg);
8293 if (!target_big_endian)
8294 --offset_expr.X_add_number;
8296 ++offset_expr.X_add_number;
8297 macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg);
8298 macro_build (NULL, "sll", "d,w,<", AT, AT, 8);
8299 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8312 if (offset_expr.X_add_number >= 0x8000 - off)
8313 as_bad (_("Operand overflow"));
8321 if (!target_big_endian)
8322 offset_expr.X_add_number += off;
8323 macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
8324 if (!target_big_endian)
8325 offset_expr.X_add_number -= off;
8327 offset_expr.X_add_number += off;
8328 macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
8330 /* If necessary, move the result in tempreg to the final destination. */
8331 if (treg == tempreg)
8333 /* Protect second load's delay slot. */
8335 move_register (treg, tempreg);
8349 load_address (AT, &offset_expr, &used_at);
8351 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8352 if (!target_big_endian)
8353 expr1.X_add_number = off;
8355 expr1.X_add_number = 0;
8356 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8357 if (!target_big_endian)
8358 expr1.X_add_number = 0;
8360 expr1.X_add_number = off;
8361 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8367 load_address (AT, &offset_expr, &used_at);
8369 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8370 if (target_big_endian)
8371 expr1.X_add_number = 0;
8372 macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
8373 treg, BFD_RELOC_LO16, AT);
8374 if (target_big_endian)
8375 expr1.X_add_number = 1;
8377 expr1.X_add_number = 0;
8378 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
8379 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
8380 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8385 if (offset_expr.X_add_number >= 0x7fff)
8386 as_bad (_("Operand overflow"));
8387 if (target_big_endian)
8388 ++offset_expr.X_add_number;
8389 macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg);
8390 macro_build (NULL, "srl", "d,w,<", AT, treg, 8);
8391 if (target_big_endian)
8392 --offset_expr.X_add_number;
8394 ++offset_expr.X_add_number;
8395 macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg);
8408 if (offset_expr.X_add_number >= 0x8000 - off)
8409 as_bad (_("Operand overflow"));
8410 if (!target_big_endian)
8411 offset_expr.X_add_number += off;
8412 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8413 if (!target_big_endian)
8414 offset_expr.X_add_number -= off;
8416 offset_expr.X_add_number += off;
8417 macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8431 load_address (AT, &offset_expr, &used_at);
8433 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8434 if (!target_big_endian)
8435 expr1.X_add_number = off;
8437 expr1.X_add_number = 0;
8438 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8439 if (!target_big_endian)
8440 expr1.X_add_number = 0;
8442 expr1.X_add_number = off;
8443 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8448 load_address (AT, &offset_expr, &used_at);
8450 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8451 if (!target_big_endian)
8452 expr1.X_add_number = 0;
8453 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8454 macro_build (NULL, "srl", "d,w,<", treg, treg, 8);
8455 if (!target_big_endian)
8456 expr1.X_add_number = 1;
8458 expr1.X_add_number = 0;
8459 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8460 if (!target_big_endian)
8461 expr1.X_add_number = 0;
8463 expr1.X_add_number = 1;
8464 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
8465 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
8466 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8470 /* FIXME: Check if this is one of the itbl macros, since they
8471 are added dynamically. */
8472 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
8475 if (!mips_opts.at && used_at)
8476 as_bad (_("Macro used $at after \".set noat\""));
8479 /* Implement macros in mips16 mode. */
8482 mips16_macro (struct mips_cl_insn *ip)
8485 int xreg, yreg, zreg, tmp;
8488 const char *s, *s2, *s3;
8490 mask = ip->insn_mo->mask;
8492 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
8493 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
8494 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
8496 expr1.X_op = O_constant;
8497 expr1.X_op_symbol = NULL;
8498 expr1.X_add_symbol = NULL;
8499 expr1.X_add_number = 1;
8519 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
8520 expr1.X_add_number = 2;
8521 macro_build (&expr1, "bnez", "x,p", yreg);
8522 macro_build (NULL, "break", "6", 7);
8524 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
8525 since that causes an overflow. We should do that as well,
8526 but I don't see how to do the comparisons without a temporary
8529 macro_build (NULL, s, "x", zreg);
8549 macro_build (NULL, s, "0,x,y", xreg, yreg);
8550 expr1.X_add_number = 2;
8551 macro_build (&expr1, "bnez", "x,p", yreg);
8552 macro_build (NULL, "break", "6", 7);
8554 macro_build (NULL, s2, "x", zreg);
8560 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
8561 macro_build (NULL, "mflo", "x", zreg);
8569 if (imm_expr.X_op != O_constant)
8570 as_bad (_("Unsupported large constant"));
8571 imm_expr.X_add_number = -imm_expr.X_add_number;
8572 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
8576 if (imm_expr.X_op != O_constant)
8577 as_bad (_("Unsupported large constant"));
8578 imm_expr.X_add_number = -imm_expr.X_add_number;
8579 macro_build (&imm_expr, "addiu", "x,k", xreg);
8583 if (imm_expr.X_op != O_constant)
8584 as_bad (_("Unsupported large constant"));
8585 imm_expr.X_add_number = -imm_expr.X_add_number;
8586 macro_build (&imm_expr, "daddiu", "y,j", yreg);
8608 goto do_reverse_branch;
8612 goto do_reverse_branch;
8624 goto do_reverse_branch;
8635 macro_build (NULL, s, "x,y", xreg, yreg);
8636 macro_build (&offset_expr, s2, "p");
8663 goto do_addone_branch_i;
8668 goto do_addone_branch_i;
8683 goto do_addone_branch_i;
8690 if (imm_expr.X_op != O_constant)
8691 as_bad (_("Unsupported large constant"));
8692 ++imm_expr.X_add_number;
8695 macro_build (&imm_expr, s, s3, xreg);
8696 macro_build (&offset_expr, s2, "p");
8700 expr1.X_add_number = 0;
8701 macro_build (&expr1, "slti", "x,8", yreg);
8703 move_register (xreg, yreg);
8704 expr1.X_add_number = 2;
8705 macro_build (&expr1, "bteqz", "p");
8706 macro_build (NULL, "neg", "x,w", xreg, xreg);
8710 /* For consistency checking, verify that all bits are specified either
8711 by the match/mask part of the instruction definition, or by the
8714 validate_mips_insn (const struct mips_opcode *opc)
8716 const char *p = opc->args;
8718 unsigned long used_bits = opc->mask;
8720 if ((used_bits & opc->match) != opc->match)
8722 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8723 opc->name, opc->args);
8726 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8736 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
8737 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
8738 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
8739 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
8740 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8741 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8742 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8743 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
8744 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8745 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8746 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8747 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8748 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8750 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8751 case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
8752 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8753 case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
8754 case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
8755 case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
8756 case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
8757 case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
8758 case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
8759 case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
8760 case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break;
8761 case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break;
8762 case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break;
8763 case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break;
8764 case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break;
8767 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8768 c, opc->name, opc->args);
8772 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8773 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8775 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
8776 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
8777 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8778 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8780 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8781 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8783 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
8784 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8786 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
8787 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
8788 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
8789 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
8790 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8791 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
8792 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8793 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8794 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8795 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8796 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8797 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8798 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8799 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
8800 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8801 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
8802 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8804 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
8805 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8806 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8807 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
8809 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8810 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8811 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
8812 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8813 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8814 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8815 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8816 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8817 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8820 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
8821 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
8822 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8823 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
8824 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
8827 case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8828 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
8829 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
8830 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
8831 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
8832 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8833 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
8834 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
8835 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
8836 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
8837 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
8838 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
8839 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
8840 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
8841 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
8842 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
8843 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
8844 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8846 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8847 c, opc->name, opc->args);
8851 if (used_bits != 0xffffffff)
8853 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8854 ~used_bits & 0xffffffff, opc->name, opc->args);
8860 /* UDI immediates. */
8868 static const struct mips_immed mips_immed[] = {
8869 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
8870 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
8871 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
8872 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
8876 /* Check whether an odd floating-point register is allowed. */
8878 mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
8880 const char *s = insn->name;
8882 if (insn->pinfo == INSN_MACRO)
8883 /* Let a macro pass, we'll catch it later when it is expanded. */
8886 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa))
8888 /* Allow odd registers for single-precision ops. */
8889 switch (insn->pinfo & (FP_S | FP_D))
8893 return 1; /* both single precision - ok */
8895 return 0; /* both double precision - fail */
8900 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
8901 s = strchr (insn->name, '.');
8903 s = s != NULL ? strchr (s + 1, '.') : NULL;
8904 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
8907 /* Single-precision coprocessor loads and moves are OK too. */
8908 if ((insn->pinfo & FP_S)
8909 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
8910 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
8916 /* This routine assembles an instruction into its binary format. As a
8917 side effect, it sets one of the global variables imm_reloc or
8918 offset_reloc to the type of relocation to do if one of the operands
8919 is an address expression. */
8922 mips_ip (char *str, struct mips_cl_insn *ip)
8927 struct mips_opcode *insn;
8930 unsigned int lastregno;
8931 unsigned int lastpos = 0;
8932 unsigned int limlo, limhi;
8935 offsetT min_range, max_range;
8941 /* If the instruction contains a '.', we first try to match an instruction
8942 including the '.'. Then we try again without the '.'. */
8944 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
8947 /* If we stopped on whitespace, then replace the whitespace with null for
8948 the call to hash_find. Save the character we replaced just in case we
8949 have to re-parse the instruction. */
8956 insn = (struct mips_opcode *) hash_find (op_hash, str);
8958 /* If we didn't find the instruction in the opcode table, try again, but
8959 this time with just the instruction up to, but not including the
8963 /* Restore the character we overwrite above (if any). */
8967 /* Scan up to the first '.' or whitespace. */
8969 *s != '\0' && *s != '.' && !ISSPACE (*s);
8973 /* If we did not find a '.', then we can quit now. */
8976 insn_error = _("Unrecognized opcode");
8980 /* Lookup the instruction in the hash table. */
8982 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
8984 insn_error = _("Unrecognized opcode");
8994 gas_assert (strcmp (insn->name, str) == 0);
8996 ok = is_opcode_valid (insn);
8999 if (insn + 1 < &mips_opcodes[NUMOPCODES]
9000 && strcmp (insn->name, insn[1].name) == 0)
9009 static char buf[100];
9011 _("opcode not supported on this processor: %s (%s)"),
9012 mips_cpu_info_from_arch (mips_opts.arch)->name,
9013 mips_cpu_info_from_isa (mips_opts.isa)->name);
9022 create_insn (ip, insn);
9025 lastregno = 0xffffffff;
9026 for (args = insn->args;; ++args)
9030 s += strspn (s, " \t");
9034 case '\0': /* end of args */
9039 case '2': /* DSP 2-bit unsigned immediate in bit 11. */
9040 my_getExpression (&imm_expr, s);
9041 check_absolute_expr (ip, &imm_expr);
9042 if ((unsigned long) imm_expr.X_add_number != 1
9043 && (unsigned long) imm_expr.X_add_number != 3)
9045 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
9046 (unsigned long) imm_expr.X_add_number);
9048 INSERT_OPERAND (BP, *ip, imm_expr.X_add_number);
9049 imm_expr.X_op = O_absent;
9053 case '3': /* DSP 3-bit unsigned immediate in bit 21. */
9054 my_getExpression (&imm_expr, s);
9055 check_absolute_expr (ip, &imm_expr);
9056 if (imm_expr.X_add_number & ~OP_MASK_SA3)
9058 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9059 OP_MASK_SA3, (unsigned long) imm_expr.X_add_number);
9061 INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number);
9062 imm_expr.X_op = O_absent;
9066 case '4': /* DSP 4-bit unsigned immediate in bit 21. */
9067 my_getExpression (&imm_expr, s);
9068 check_absolute_expr (ip, &imm_expr);
9069 if (imm_expr.X_add_number & ~OP_MASK_SA4)
9071 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9072 OP_MASK_SA4, (unsigned long) imm_expr.X_add_number);
9074 INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number);
9075 imm_expr.X_op = O_absent;
9079 case '5': /* DSP 8-bit unsigned immediate in bit 16. */
9080 my_getExpression (&imm_expr, s);
9081 check_absolute_expr (ip, &imm_expr);
9082 if (imm_expr.X_add_number & ~OP_MASK_IMM8)
9084 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9085 OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number);
9087 INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number);
9088 imm_expr.X_op = O_absent;
9092 case '6': /* DSP 5-bit unsigned immediate in bit 21. */
9093 my_getExpression (&imm_expr, s);
9094 check_absolute_expr (ip, &imm_expr);
9095 if (imm_expr.X_add_number & ~OP_MASK_RS)
9097 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9098 OP_MASK_RS, (unsigned long) imm_expr.X_add_number);
9100 INSERT_OPERAND (RS, *ip, imm_expr.X_add_number);
9101 imm_expr.X_op = O_absent;
9105 case '7': /* Four DSP accumulators in bits 11,12. */
9106 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9107 s[3] >= '0' && s[3] <= '3')
9111 INSERT_OPERAND (DSPACC, *ip, regno);
9115 as_bad (_("Invalid dsp acc register"));
9118 case '8': /* DSP 6-bit unsigned immediate in bit 11. */
9119 my_getExpression (&imm_expr, s);
9120 check_absolute_expr (ip, &imm_expr);
9121 if (imm_expr.X_add_number & ~OP_MASK_WRDSP)
9123 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9125 (unsigned long) imm_expr.X_add_number);
9127 INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number);
9128 imm_expr.X_op = O_absent;
9132 case '9': /* Four DSP accumulators in bits 21,22. */
9133 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9134 s[3] >= '0' && s[3] <= '3')
9138 INSERT_OPERAND (DSPACC_S, *ip, regno);
9142 as_bad (_("Invalid dsp acc register"));
9145 case '0': /* DSP 6-bit signed immediate in bit 20. */
9146 my_getExpression (&imm_expr, s);
9147 check_absolute_expr (ip, &imm_expr);
9148 min_range = -((OP_MASK_DSPSFT + 1) >> 1);
9149 max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1;
9150 if (imm_expr.X_add_number < min_range ||
9151 imm_expr.X_add_number > max_range)
9153 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
9154 (long) min_range, (long) max_range,
9155 (long) imm_expr.X_add_number);
9157 INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number);
9158 imm_expr.X_op = O_absent;
9162 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
9163 my_getExpression (&imm_expr, s);
9164 check_absolute_expr (ip, &imm_expr);
9165 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
9167 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9169 (unsigned long) imm_expr.X_add_number);
9171 INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number);
9172 imm_expr.X_op = O_absent;
9176 case ':': /* DSP 7-bit signed immediate in bit 19. */
9177 my_getExpression (&imm_expr, s);
9178 check_absolute_expr (ip, &imm_expr);
9179 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
9180 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
9181 if (imm_expr.X_add_number < min_range ||
9182 imm_expr.X_add_number > max_range)
9184 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
9185 (long) min_range, (long) max_range,
9186 (long) imm_expr.X_add_number);
9188 INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number);
9189 imm_expr.X_op = O_absent;
9193 case '@': /* DSP 10-bit signed immediate in bit 16. */
9194 my_getExpression (&imm_expr, s);
9195 check_absolute_expr (ip, &imm_expr);
9196 min_range = -((OP_MASK_IMM10 + 1) >> 1);
9197 max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1;
9198 if (imm_expr.X_add_number < min_range ||
9199 imm_expr.X_add_number > max_range)
9201 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
9202 (long) min_range, (long) max_range,
9203 (long) imm_expr.X_add_number);
9205 INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number);
9206 imm_expr.X_op = O_absent;
9210 case '!': /* MT usermode flag bit. */
9211 my_getExpression (&imm_expr, s);
9212 check_absolute_expr (ip, &imm_expr);
9213 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
9214 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
9215 (unsigned long) imm_expr.X_add_number);
9216 INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number);
9217 imm_expr.X_op = O_absent;
9221 case '$': /* MT load high flag bit. */
9222 my_getExpression (&imm_expr, s);
9223 check_absolute_expr (ip, &imm_expr);
9224 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
9225 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
9226 (unsigned long) imm_expr.X_add_number);
9227 INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number);
9228 imm_expr.X_op = O_absent;
9232 case '*': /* Four DSP accumulators in bits 18,19. */
9233 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9234 s[3] >= '0' && s[3] <= '3')
9238 INSERT_OPERAND (MTACC_T, *ip, regno);
9242 as_bad (_("Invalid dsp/smartmips acc register"));
9245 case '&': /* Four DSP accumulators in bits 13,14. */
9246 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9247 s[3] >= '0' && s[3] <= '3')
9251 INSERT_OPERAND (MTACC_D, *ip, regno);
9255 as_bad (_("Invalid dsp/smartmips acc register"));
9267 INSERT_OPERAND (RS, *ip, lastregno);
9271 INSERT_OPERAND (RT, *ip, lastregno);
9275 INSERT_OPERAND (FT, *ip, lastregno);
9279 INSERT_OPERAND (FS, *ip, lastregno);
9285 /* Handle optional base register.
9286 Either the base register is omitted or
9287 we must have a left paren. */
9288 /* This is dependent on the next operand specifier
9289 is a base register specification. */
9290 gas_assert (args[1] == 'b');
9294 case ')': /* These must match exactly. */
9301 case '+': /* Opcode extension character. */
9304 case '1': /* UDI immediates. */
9309 const struct mips_immed *imm = mips_immed;
9311 while (imm->type && imm->type != *args)
9315 my_getExpression (&imm_expr, s);
9316 check_absolute_expr (ip, &imm_expr);
9317 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
9319 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
9320 imm->desc ? imm->desc : ip->insn_mo->name,
9321 (unsigned long) imm_expr.X_add_number,
9322 (unsigned long) imm_expr.X_add_number);
9323 imm_expr.X_add_number &= imm->mask;
9325 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
9327 imm_expr.X_op = O_absent;
9332 case 'A': /* ins/ext position, becomes LSB. */
9341 my_getExpression (&imm_expr, s);
9342 check_absolute_expr (ip, &imm_expr);
9343 if ((unsigned long) imm_expr.X_add_number < limlo
9344 || (unsigned long) imm_expr.X_add_number > limhi)
9346 as_bad (_("Improper position (%lu)"),
9347 (unsigned long) imm_expr.X_add_number);
9348 imm_expr.X_add_number = limlo;
9350 lastpos = imm_expr.X_add_number;
9351 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9352 imm_expr.X_op = O_absent;
9356 case 'B': /* ins size, becomes MSB. */
9365 my_getExpression (&imm_expr, s);
9366 check_absolute_expr (ip, &imm_expr);
9367 /* Check for negative input so that small negative numbers
9368 will not succeed incorrectly. The checks against
9369 (pos+size) transitively check "size" itself,
9370 assuming that "pos" is reasonable. */
9371 if ((long) imm_expr.X_add_number < 0
9372 || ((unsigned long) imm_expr.X_add_number
9374 || ((unsigned long) imm_expr.X_add_number
9377 as_bad (_("Improper insert size (%lu, position %lu)"),
9378 (unsigned long) imm_expr.X_add_number,
9379 (unsigned long) lastpos);
9380 imm_expr.X_add_number = limlo - lastpos;
9382 INSERT_OPERAND (INSMSB, *ip,
9383 lastpos + imm_expr.X_add_number - 1);
9384 imm_expr.X_op = O_absent;
9388 case 'C': /* ext size, becomes MSBD. */
9401 my_getExpression (&imm_expr, s);
9402 check_absolute_expr (ip, &imm_expr);
9403 /* Check for negative input so that small negative numbers
9404 will not succeed incorrectly. The checks against
9405 (pos+size) transitively check "size" itself,
9406 assuming that "pos" is reasonable. */
9407 if ((long) imm_expr.X_add_number < 0
9408 || ((unsigned long) imm_expr.X_add_number
9410 || ((unsigned long) imm_expr.X_add_number
9413 as_bad (_("Improper extract size (%lu, position %lu)"),
9414 (unsigned long) imm_expr.X_add_number,
9415 (unsigned long) lastpos);
9416 imm_expr.X_add_number = limlo - lastpos;
9418 INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1);
9419 imm_expr.X_op = O_absent;
9424 /* +D is for disassembly only; never match. */
9428 /* "+I" is like "I", except that imm2_expr is used. */
9429 my_getExpression (&imm2_expr, s);
9430 if (imm2_expr.X_op != O_big
9431 && imm2_expr.X_op != O_constant)
9432 insn_error = _("absolute expression required");
9433 if (HAVE_32BIT_GPRS)
9434 normalize_constant_expr (&imm2_expr);
9438 case 'T': /* Coprocessor register. */
9439 /* +T is for disassembly only; never match. */
9442 case 't': /* Coprocessor register number. */
9443 if (s[0] == '$' && ISDIGIT (s[1]))
9453 while (ISDIGIT (*s));
9455 as_bad (_("Invalid register number (%d)"), regno);
9458 INSERT_OPERAND (RT, *ip, regno);
9463 as_bad (_("Invalid coprocessor 0 register number"));
9467 /* bbit[01] and bbit[01]32 bit index. Give error if index
9468 is not in the valid range. */
9469 my_getExpression (&imm_expr, s);
9470 check_absolute_expr (ip, &imm_expr);
9471 if ((unsigned) imm_expr.X_add_number > 31)
9473 as_bad (_("Improper bit index (%lu)"),
9474 (unsigned long) imm_expr.X_add_number);
9475 imm_expr.X_add_number = 0;
9477 INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number);
9478 imm_expr.X_op = O_absent;
9483 /* bbit[01] bit index when bbit is used but we generate
9484 bbit[01]32 because the index is over 32. Move to the
9485 next candidate if index is not in the valid range. */
9486 my_getExpression (&imm_expr, s);
9487 check_absolute_expr (ip, &imm_expr);
9488 if ((unsigned) imm_expr.X_add_number < 32
9489 || (unsigned) imm_expr.X_add_number > 63)
9491 INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number - 32);
9492 imm_expr.X_op = O_absent;
9497 /* cins, cins32, exts and exts32 position field. Give error
9498 if it's not in the valid range. */
9499 my_getExpression (&imm_expr, s);
9500 check_absolute_expr (ip, &imm_expr);
9501 if ((unsigned) imm_expr.X_add_number > 31)
9503 as_bad (_("Improper position (%lu)"),
9504 (unsigned long) imm_expr.X_add_number);
9505 imm_expr.X_add_number = 0;
9507 /* Make the pos explicit to simplify +S. */
9508 lastpos = imm_expr.X_add_number + 32;
9509 INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number);
9510 imm_expr.X_op = O_absent;
9515 /* cins, cins32, exts and exts32 position field. Move to
9516 the next candidate if it's not in the valid range. */
9517 my_getExpression (&imm_expr, s);
9518 check_absolute_expr (ip, &imm_expr);
9519 if ((unsigned) imm_expr.X_add_number < 32
9520 || (unsigned) imm_expr.X_add_number > 63)
9522 lastpos = imm_expr.X_add_number;
9523 INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number - 32);
9524 imm_expr.X_op = O_absent;
9529 /* cins and exts length-minus-one field. */
9530 my_getExpression (&imm_expr, s);
9531 check_absolute_expr (ip, &imm_expr);
9532 if ((unsigned long) imm_expr.X_add_number > 31)
9534 as_bad (_("Improper size (%lu)"),
9535 (unsigned long) imm_expr.X_add_number);
9536 imm_expr.X_add_number = 0;
9538 INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number);
9539 imm_expr.X_op = O_absent;
9544 /* cins32/exts32 and cins/exts aliasing cint32/exts32
9545 length-minus-one field. */
9546 my_getExpression (&imm_expr, s);
9547 check_absolute_expr (ip, &imm_expr);
9548 if ((long) imm_expr.X_add_number < 0
9549 || (unsigned long) imm_expr.X_add_number + lastpos > 63)
9551 as_bad (_("Improper size (%lu)"),
9552 (unsigned long) imm_expr.X_add_number);
9553 imm_expr.X_add_number = 0;
9555 INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number);
9556 imm_expr.X_op = O_absent;
9561 /* seqi/snei immediate field. */
9562 my_getExpression (&imm_expr, s);
9563 check_absolute_expr (ip, &imm_expr);
9564 if ((long) imm_expr.X_add_number < -512
9565 || (long) imm_expr.X_add_number >= 512)
9567 as_bad (_("Improper immediate (%ld)"),
9568 (long) imm_expr.X_add_number);
9569 imm_expr.X_add_number = 0;
9571 INSERT_OPERAND (SEQI, *ip, imm_expr.X_add_number);
9572 imm_expr.X_op = O_absent;
9576 case 'a': /* 8-bit signed offset in bit 6 */
9577 my_getExpression (&imm_expr, s);
9578 check_absolute_expr (ip, &imm_expr);
9579 min_range = -((OP_MASK_OFFSET_A + 1) >> 1);
9580 max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1;
9581 if (imm_expr.X_add_number < min_range
9582 || imm_expr.X_add_number > max_range)
9584 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9585 (long) min_range, (long) max_range,
9586 (long) imm_expr.X_add_number);
9588 INSERT_OPERAND (OFFSET_A, *ip, imm_expr.X_add_number);
9589 imm_expr.X_op = O_absent;
9593 case 'b': /* 8-bit signed offset in bit 3 */
9594 my_getExpression (&imm_expr, s);
9595 check_absolute_expr (ip, &imm_expr);
9596 min_range = -((OP_MASK_OFFSET_B + 1) >> 1);
9597 max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1;
9598 if (imm_expr.X_add_number < min_range
9599 || imm_expr.X_add_number > max_range)
9601 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9602 (long) min_range, (long) max_range,
9603 (long) imm_expr.X_add_number);
9605 INSERT_OPERAND (OFFSET_B, *ip, imm_expr.X_add_number);
9606 imm_expr.X_op = O_absent;
9610 case 'c': /* 9-bit signed offset in bit 6 */
9611 my_getExpression (&imm_expr, s);
9612 check_absolute_expr (ip, &imm_expr);
9613 min_range = -((OP_MASK_OFFSET_C + 1) >> 1);
9614 max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1;
9615 /* We check the offset range before adjusted. */
9618 if (imm_expr.X_add_number < min_range
9619 || imm_expr.X_add_number > max_range)
9621 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9622 (long) min_range, (long) max_range,
9623 (long) imm_expr.X_add_number);
9625 if (imm_expr.X_add_number & 0xf)
9627 as_bad (_("Offset not 16 bytes alignment (%ld)"),
9628 (long) imm_expr.X_add_number);
9630 /* Right shift 4 bits to adjust the offset operand. */
9631 INSERT_OPERAND (OFFSET_C, *ip, imm_expr.X_add_number >> 4);
9632 imm_expr.X_op = O_absent;
9637 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
9639 if (regno == AT && mips_opts.at)
9641 if (mips_opts.at == ATREG)
9642 as_warn (_("used $at without \".set noat\""));
9644 as_warn (_("used $%u with \".set at=$%u\""),
9645 regno, mips_opts.at);
9647 INSERT_OPERAND (RZ, *ip, regno);
9651 if (!reg_lookup (&s, RTYPE_FPU, ®no))
9653 INSERT_OPERAND (FZ, *ip, regno);
9657 as_bad (_("Internal error: bad mips opcode "
9658 "(unknown extension operand type `+%c'): %s %s"),
9659 *args, insn->name, insn->args);
9660 /* Further processing is fruitless. */
9665 case '<': /* must be at least one digit */
9667 * According to the manual, if the shift amount is greater
9668 * than 31 or less than 0, then the shift amount should be
9669 * mod 32. In reality the mips assembler issues an error.
9670 * We issue a warning and mask out all but the low 5 bits.
9672 my_getExpression (&imm_expr, s);
9673 check_absolute_expr (ip, &imm_expr);
9674 if ((unsigned long) imm_expr.X_add_number > 31)
9675 as_warn (_("Improper shift amount (%lu)"),
9676 (unsigned long) imm_expr.X_add_number);
9677 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9678 imm_expr.X_op = O_absent;
9682 case '>': /* shift amount minus 32 */
9683 my_getExpression (&imm_expr, s);
9684 check_absolute_expr (ip, &imm_expr);
9685 if ((unsigned long) imm_expr.X_add_number < 32
9686 || (unsigned long) imm_expr.X_add_number > 63)
9688 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32);
9689 imm_expr.X_op = O_absent;
9693 case 'k': /* CACHE code. */
9694 case 'h': /* PREFX code. */
9695 case '1': /* SYNC type. */
9696 my_getExpression (&imm_expr, s);
9697 check_absolute_expr (ip, &imm_expr);
9698 if ((unsigned long) imm_expr.X_add_number > 31)
9699 as_warn (_("Invalid value for `%s' (%lu)"),
9701 (unsigned long) imm_expr.X_add_number);
9704 if (mips_fix_cn63xxp1 && strcmp ("pref", insn->name) == 0)
9705 switch (imm_expr.X_add_number)
9714 case 31: /* These are ok. */
9717 default: /* The rest must be changed to 28. */
9718 imm_expr.X_add_number = 28;
9721 INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number);
9723 else if (*args == 'h')
9724 INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number);
9726 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9727 imm_expr.X_op = O_absent;
9731 case 'c': /* BREAK code. */
9732 my_getExpression (&imm_expr, s);
9733 check_absolute_expr (ip, &imm_expr);
9734 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE)
9735 as_warn (_("Code for %s not in range 0..1023 (%lu)"),
9737 (unsigned long) imm_expr.X_add_number);
9738 INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number);
9739 imm_expr.X_op = O_absent;
9743 case 'q': /* Lower BREAK code. */
9744 my_getExpression (&imm_expr, s);
9745 check_absolute_expr (ip, &imm_expr);
9746 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2)
9747 as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
9749 (unsigned long) imm_expr.X_add_number);
9750 INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number);
9751 imm_expr.X_op = O_absent;
9755 case 'B': /* 20-bit SYSCALL/BREAK code. */
9756 my_getExpression (&imm_expr, s);
9757 check_absolute_expr (ip, &imm_expr);
9758 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
9759 as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
9761 (unsigned long) imm_expr.X_add_number);
9762 INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number);
9763 imm_expr.X_op = O_absent;
9767 case 'C': /* Coprocessor code. */
9768 my_getExpression (&imm_expr, s);
9769 check_absolute_expr (ip, &imm_expr);
9770 if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ)
9772 as_warn (_("Coproccesor code > 25 bits (%lu)"),
9773 (unsigned long) imm_expr.X_add_number);
9774 imm_expr.X_add_number &= OP_MASK_COPZ;
9776 INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number);
9777 imm_expr.X_op = O_absent;
9781 case 'J': /* 19-bit WAIT code. */
9782 my_getExpression (&imm_expr, s);
9783 check_absolute_expr (ip, &imm_expr);
9784 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
9786 as_warn (_("Illegal 19-bit code (%lu)"),
9787 (unsigned long) imm_expr.X_add_number);
9788 imm_expr.X_add_number &= OP_MASK_CODE19;
9790 INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number);
9791 imm_expr.X_op = O_absent;
9795 case 'P': /* Performance register. */
9796 my_getExpression (&imm_expr, s);
9797 check_absolute_expr (ip, &imm_expr);
9798 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
9799 as_warn (_("Invalid performance register (%lu)"),
9800 (unsigned long) imm_expr.X_add_number);
9801 INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number);
9802 imm_expr.X_op = O_absent;
9806 case 'G': /* Coprocessor destination register. */
9807 if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0)
9808 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, ®no);
9810 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
9811 INSERT_OPERAND (RD, *ip, regno);
9820 case 'b': /* Base register. */
9821 case 'd': /* Destination register. */
9822 case 's': /* Source register. */
9823 case 't': /* Target register. */
9824 case 'r': /* Both target and source. */
9825 case 'v': /* Both dest and source. */
9826 case 'w': /* Both dest and target. */
9827 case 'E': /* Coprocessor target register. */
9828 case 'K': /* RDHWR destination register. */
9829 case 'x': /* Ignore register name. */
9830 case 'z': /* Must be zero register. */
9831 case 'U': /* Destination register (CLO/CLZ). */
9832 case 'g': /* Coprocessor destination register. */
9834 if (*args == 'E' || *args == 'K')
9835 ok = reg_lookup (&s, RTYPE_NUM, ®no);
9838 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
9839 if (regno == AT && mips_opts.at)
9841 if (mips_opts.at == ATREG)
9842 as_warn (_("Used $at without \".set noat\""));
9844 as_warn (_("Used $%u with \".set at=$%u\""),
9845 regno, mips_opts.at);
9855 if (c == 'r' || c == 'v' || c == 'w')
9862 /* 'z' only matches $0. */
9863 if (c == 'z' && regno != 0)
9866 if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
9868 if (regno == lastregno)
9871 = _("Source and destination must be different");
9874 if (regno == 31 && lastregno == 0xffffffff)
9877 = _("A destination register must be supplied");
9881 /* Now that we have assembled one operand, we use the args
9882 string to figure out where it goes in the instruction. */
9889 INSERT_OPERAND (RS, *ip, regno);
9894 INSERT_OPERAND (RD, *ip, regno);
9897 INSERT_OPERAND (RD, *ip, regno);
9898 INSERT_OPERAND (RT, *ip, regno);
9903 INSERT_OPERAND (RT, *ip, regno);
9906 /* This case exists because on the r3000 trunc
9907 expands into a macro which requires a gp
9908 register. On the r6000 or r4000 it is
9909 assembled into a single instruction which
9910 ignores the register. Thus the insn version
9911 is MIPS_ISA2 and uses 'x', and the macro
9912 version is MIPS_ISA1 and uses 't'. */
9915 /* This case is for the div instruction, which
9916 acts differently if the destination argument
9917 is $0. This only matches $0, and is checked
9918 outside the switch. */
9928 INSERT_OPERAND (RS, *ip, lastregno);
9931 INSERT_OPERAND (RT, *ip, lastregno);
9936 case 'O': /* MDMX alignment immediate constant. */
9937 my_getExpression (&imm_expr, s);
9938 check_absolute_expr (ip, &imm_expr);
9939 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
9940 as_warn (_("Improper align amount (%ld), using low bits"),
9941 (long) imm_expr.X_add_number);
9942 INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number);
9943 imm_expr.X_op = O_absent;
9947 case 'Q': /* MDMX vector, element sel, or const. */
9950 /* MDMX Immediate. */
9951 my_getExpression (&imm_expr, s);
9952 check_absolute_expr (ip, &imm_expr);
9953 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
9954 as_warn (_("Invalid MDMX Immediate (%ld)"),
9955 (long) imm_expr.X_add_number);
9956 INSERT_OPERAND (FT, *ip, imm_expr.X_add_number);
9957 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
9958 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
9960 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
9961 imm_expr.X_op = O_absent;
9965 /* Not MDMX Immediate. Fall through. */
9966 case 'X': /* MDMX destination register. */
9967 case 'Y': /* MDMX source register. */
9968 case 'Z': /* MDMX target register. */
9970 case 'D': /* Floating point destination register. */
9971 case 'S': /* Floating point source register. */
9972 case 'T': /* Floating point target register. */
9973 case 'R': /* Floating point source register. */
9978 || (mips_opts.ase_mdmx
9979 && (ip->insn_mo->pinfo & FP_D)
9980 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
9981 | INSN_COPROC_MEMORY_DELAY
9982 | INSN_LOAD_COPROC_DELAY
9983 | INSN_LOAD_MEMORY_DELAY
9984 | INSN_STORE_MEMORY))))
9987 if (reg_lookup (&s, rtype, ®no))
9989 if ((regno & 1) != 0
9991 && !mips_oddfpreg_ok (ip->insn_mo, argnum))
9992 as_warn (_("Float register should be even, was %d"),
10000 if (c == 'V' || c == 'W')
10011 INSERT_OPERAND (FD, *ip, regno);
10016 INSERT_OPERAND (FS, *ip, regno);
10019 /* This is like 'Z', but also needs to fix the MDMX
10020 vector/scalar select bits. Note that the
10021 scalar immediate case is handled above. */
10024 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
10025 int max_el = (is_qh ? 3 : 7);
10027 my_getExpression(&imm_expr, s);
10028 check_absolute_expr (ip, &imm_expr);
10030 if (imm_expr.X_add_number > max_el)
10031 as_bad (_("Bad element selector %ld"),
10032 (long) imm_expr.X_add_number);
10033 imm_expr.X_add_number &= max_el;
10034 ip->insn_opcode |= (imm_expr.X_add_number
10037 imm_expr.X_op = O_absent;
10039 as_warn (_("Expecting ']' found '%s'"), s);
10045 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
10046 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
10049 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
10052 /* Fall through. */
10056 INSERT_OPERAND (FT, *ip, regno);
10059 INSERT_OPERAND (FR, *ip, regno);
10069 INSERT_OPERAND (FS, *ip, lastregno);
10072 INSERT_OPERAND (FT, *ip, lastregno);
10078 my_getExpression (&imm_expr, s);
10079 if (imm_expr.X_op != O_big
10080 && imm_expr.X_op != O_constant)
10081 insn_error = _("absolute expression required");
10082 if (HAVE_32BIT_GPRS)
10083 normalize_constant_expr (&imm_expr);
10088 my_getExpression (&offset_expr, s);
10089 normalize_address_expr (&offset_expr);
10090 *imm_reloc = BFD_RELOC_32;
10103 unsigned char temp[8];
10105 unsigned int length;
10110 /* These only appear as the last operand in an
10111 instruction, and every instruction that accepts
10112 them in any variant accepts them in all variants.
10113 This means we don't have to worry about backing out
10114 any changes if the instruction does not match.
10116 The difference between them is the size of the
10117 floating point constant and where it goes. For 'F'
10118 and 'L' the constant is 64 bits; for 'f' and 'l' it
10119 is 32 bits. Where the constant is placed is based
10120 on how the MIPS assembler does things:
10123 f -- immediate value
10126 The .lit4 and .lit8 sections are only used if
10127 permitted by the -G argument.
10129 The code below needs to know whether the target register
10130 is 32 or 64 bits wide. It relies on the fact 'f' and
10131 'F' are used with GPR-based instructions and 'l' and
10132 'L' are used with FPR-based instructions. */
10134 f64 = *args == 'F' || *args == 'L';
10135 using_gprs = *args == 'F' || *args == 'f';
10137 save_in = input_line_pointer;
10138 input_line_pointer = s;
10139 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
10141 s = input_line_pointer;
10142 input_line_pointer = save_in;
10143 if (err != NULL && *err != '\0')
10145 as_bad (_("Bad floating point constant: %s"), err);
10146 memset (temp, '\0', sizeof temp);
10147 length = f64 ? 8 : 4;
10150 gas_assert (length == (unsigned) (f64 ? 8 : 4));
10154 && (g_switch_value < 4
10155 || (temp[0] == 0 && temp[1] == 0)
10156 || (temp[2] == 0 && temp[3] == 0))))
10158 imm_expr.X_op = O_constant;
10159 if (!target_big_endian)
10160 imm_expr.X_add_number = bfd_getl32 (temp);
10162 imm_expr.X_add_number = bfd_getb32 (temp);
10164 else if (length > 4
10165 && !mips_disable_float_construction
10166 /* Constants can only be constructed in GPRs and
10167 copied to FPRs if the GPRs are at least as wide
10168 as the FPRs. Force the constant into memory if
10169 we are using 64-bit FPRs but the GPRs are only
10172 || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
10173 && ((temp[0] == 0 && temp[1] == 0)
10174 || (temp[2] == 0 && temp[3] == 0))
10175 && ((temp[4] == 0 && temp[5] == 0)
10176 || (temp[6] == 0 && temp[7] == 0)))
10178 /* The value is simple enough to load with a couple of
10179 instructions. If using 32-bit registers, set
10180 imm_expr to the high order 32 bits and offset_expr to
10181 the low order 32 bits. Otherwise, set imm_expr to
10182 the entire 64 bit constant. */
10183 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
10185 imm_expr.X_op = O_constant;
10186 offset_expr.X_op = O_constant;
10187 if (!target_big_endian)
10189 imm_expr.X_add_number = bfd_getl32 (temp + 4);
10190 offset_expr.X_add_number = bfd_getl32 (temp);
10194 imm_expr.X_add_number = bfd_getb32 (temp);
10195 offset_expr.X_add_number = bfd_getb32 (temp + 4);
10197 if (offset_expr.X_add_number == 0)
10198 offset_expr.X_op = O_absent;
10200 else if (sizeof (imm_expr.X_add_number) > 4)
10202 imm_expr.X_op = O_constant;
10203 if (!target_big_endian)
10204 imm_expr.X_add_number = bfd_getl64 (temp);
10206 imm_expr.X_add_number = bfd_getb64 (temp);
10210 imm_expr.X_op = O_big;
10211 imm_expr.X_add_number = 4;
10212 if (!target_big_endian)
10214 generic_bignum[0] = bfd_getl16 (temp);
10215 generic_bignum[1] = bfd_getl16 (temp + 2);
10216 generic_bignum[2] = bfd_getl16 (temp + 4);
10217 generic_bignum[3] = bfd_getl16 (temp + 6);
10221 generic_bignum[0] = bfd_getb16 (temp + 6);
10222 generic_bignum[1] = bfd_getb16 (temp + 4);
10223 generic_bignum[2] = bfd_getb16 (temp + 2);
10224 generic_bignum[3] = bfd_getb16 (temp);
10230 const char *newname;
10233 /* Switch to the right section. */
10235 subseg = now_subseg;
10238 default: /* unused default case avoids warnings. */
10240 newname = RDATA_SECTION_NAME;
10241 if (g_switch_value >= 8)
10245 newname = RDATA_SECTION_NAME;
10248 gas_assert (g_switch_value >= 4);
10252 new_seg = subseg_new (newname, (subsegT) 0);
10254 bfd_set_section_flags (stdoutput, new_seg,
10259 frag_align (*args == 'l' ? 2 : 3, 0, 0);
10260 if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0)
10261 record_alignment (new_seg, 4);
10263 record_alignment (new_seg, *args == 'l' ? 2 : 3);
10264 if (seg == now_seg)
10265 as_bad (_("Can't use floating point insn in this section"));
10267 /* Set the argument to the current address in the
10269 offset_expr.X_op = O_symbol;
10270 offset_expr.X_add_symbol = symbol_temp_new_now ();
10271 offset_expr.X_add_number = 0;
10273 /* Put the floating point number into the section. */
10274 p = frag_more ((int) length);
10275 memcpy (p, temp, length);
10277 /* Switch back to the original section. */
10278 subseg_set (seg, subseg);
10283 case 'i': /* 16-bit unsigned immediate. */
10284 case 'j': /* 16-bit signed immediate. */
10285 *imm_reloc = BFD_RELOC_LO16;
10286 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
10289 offsetT minval, maxval;
10291 more = (insn + 1 < &mips_opcodes[NUMOPCODES]
10292 && strcmp (insn->name, insn[1].name) == 0);
10294 /* If the expression was written as an unsigned number,
10295 only treat it as signed if there are no more
10299 && sizeof (imm_expr.X_add_number) <= 4
10300 && imm_expr.X_op == O_constant
10301 && imm_expr.X_add_number < 0
10302 && imm_expr.X_unsigned
10303 && HAVE_64BIT_GPRS)
10306 /* For compatibility with older assemblers, we accept
10307 0x8000-0xffff as signed 16-bit numbers when only
10308 signed numbers are allowed. */
10310 minval = 0, maxval = 0xffff;
10312 minval = -0x8000, maxval = 0x7fff;
10314 minval = -0x8000, maxval = 0xffff;
10316 if (imm_expr.X_op != O_constant
10317 || imm_expr.X_add_number < minval
10318 || imm_expr.X_add_number > maxval)
10322 if (imm_expr.X_op == O_constant
10323 || imm_expr.X_op == O_big)
10324 as_bad (_("Expression out of range"));
10330 case 'o': /* 16-bit offset. */
10331 offset_reloc[0] = BFD_RELOC_LO16;
10332 offset_reloc[1] = BFD_RELOC_UNUSED;
10333 offset_reloc[2] = BFD_RELOC_UNUSED;
10335 /* Check whether there is only a single bracketed expression
10336 left. If so, it must be the base register and the
10337 constant must be zero. */
10338 if (*s == '(' && strchr (s + 1, '(') == 0)
10340 offset_expr.X_op = O_constant;
10341 offset_expr.X_add_number = 0;
10345 /* If this value won't fit into a 16 bit offset, then go
10346 find a macro that will generate the 32 bit offset
10348 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
10349 && (offset_expr.X_op != O_constant
10350 || offset_expr.X_add_number >= 0x8000
10351 || offset_expr.X_add_number < -0x8000))
10357 case 'p': /* PC-relative offset. */
10358 *offset_reloc = BFD_RELOC_16_PCREL_S2;
10359 my_getExpression (&offset_expr, s);
10363 case 'u': /* Upper 16 bits. */
10364 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
10365 && imm_expr.X_op == O_constant
10366 && (imm_expr.X_add_number < 0
10367 || imm_expr.X_add_number >= 0x10000))
10368 as_bad (_("lui expression (%lu) not in range 0..65535"),
10369 (unsigned long) imm_expr.X_add_number);
10373 case 'a': /* 26-bit address. */
10374 my_getExpression (&offset_expr, s);
10376 *offset_reloc = BFD_RELOC_MIPS_JMP;
10379 case 'N': /* 3-bit branch condition code. */
10380 case 'M': /* 3-bit compare condition code. */
10382 if (ip->insn_mo->pinfo & (FP_D | FP_S))
10383 rtype |= RTYPE_FCC;
10384 if (!reg_lookup (&s, rtype, ®no))
10386 if ((strcmp (str + strlen (str) - 3, ".ps") == 0
10387 || strcmp (str + strlen (str) - 5, "any2f") == 0
10388 || strcmp (str + strlen (str) - 5, "any2t") == 0)
10389 && (regno & 1) != 0)
10390 as_warn (_("Condition code register should be even for %s, "
10393 if ((strcmp (str + strlen (str) - 5, "any4f") == 0
10394 || strcmp (str + strlen (str) - 5, "any4t") == 0)
10395 && (regno & 3) != 0)
10396 as_warn (_("Condition code register should be 0 or 4 for %s, "
10400 INSERT_OPERAND (BCC, *ip, regno);
10402 INSERT_OPERAND (CCC, *ip, regno);
10406 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
10417 while (ISDIGIT (*s));
10420 c = 8; /* Invalid sel value. */
10423 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
10424 ip->insn_opcode |= c;
10428 /* Must be at least one digit. */
10429 my_getExpression (&imm_expr, s);
10430 check_absolute_expr (ip, &imm_expr);
10432 if ((unsigned long) imm_expr.X_add_number
10433 > (unsigned long) OP_MASK_VECBYTE)
10435 as_bad (_("bad byte vector index (%ld)"),
10436 (long) imm_expr.X_add_number);
10437 imm_expr.X_add_number = 0;
10440 INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number);
10441 imm_expr.X_op = O_absent;
10446 my_getExpression (&imm_expr, s);
10447 check_absolute_expr (ip, &imm_expr);
10449 if ((unsigned long) imm_expr.X_add_number
10450 > (unsigned long) OP_MASK_VECALIGN)
10452 as_bad (_("bad byte vector index (%ld)"),
10453 (long) imm_expr.X_add_number);
10454 imm_expr.X_add_number = 0;
10457 INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number);
10458 imm_expr.X_op = O_absent;
10463 as_bad (_("Bad char = '%c'\n"), *args);
10468 /* Args don't match. */
10469 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
10470 !strcmp (insn->name, insn[1].name))
10474 insn_error = _("Illegal operands");
10478 *(--argsStart) = save_c;
10479 insn_error = _("Illegal operands");
10484 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
10486 /* This routine assembles an instruction into its binary format when
10487 assembling for the mips16. As a side effect, it sets one of the
10488 global variables imm_reloc or offset_reloc to the type of
10489 relocation to do if one of the operands is an address expression.
10490 It also sets mips16_small and mips16_ext if the user explicitly
10491 requested a small or extended instruction. */
10494 mips16_ip (char *str, struct mips_cl_insn *ip)
10498 struct mips_opcode *insn;
10500 unsigned int regno;
10501 unsigned int lastregno = 0;
10507 mips16_small = FALSE;
10508 mips16_ext = FALSE;
10510 for (s = str; ISLOWER (*s); ++s)
10522 if (s[1] == 't' && s[2] == ' ')
10525 mips16_small = TRUE;
10529 else if (s[1] == 'e' && s[2] == ' ')
10536 /* Fall through. */
10538 insn_error = _("unknown opcode");
10542 if (mips_opts.noautoextend && ! mips16_ext)
10543 mips16_small = TRUE;
10545 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
10547 insn_error = _("unrecognized opcode");
10556 gas_assert (strcmp (insn->name, str) == 0);
10558 ok = is_opcode_valid_16 (insn);
10561 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
10562 && strcmp (insn->name, insn[1].name) == 0)
10571 static char buf[100];
10573 _("opcode not supported on this processor: %s (%s)"),
10574 mips_cpu_info_from_arch (mips_opts.arch)->name,
10575 mips_cpu_info_from_isa (mips_opts.isa)->name);
10582 create_insn (ip, insn);
10583 imm_expr.X_op = O_absent;
10584 imm_reloc[0] = BFD_RELOC_UNUSED;
10585 imm_reloc[1] = BFD_RELOC_UNUSED;
10586 imm_reloc[2] = BFD_RELOC_UNUSED;
10587 imm2_expr.X_op = O_absent;
10588 offset_expr.X_op = O_absent;
10589 offset_reloc[0] = BFD_RELOC_UNUSED;
10590 offset_reloc[1] = BFD_RELOC_UNUSED;
10591 offset_reloc[2] = BFD_RELOC_UNUSED;
10592 for (args = insn->args; 1; ++args)
10599 /* In this switch statement we call break if we did not find
10600 a match, continue if we did find a match, or return if we
10609 /* Stuff the immediate value in now, if we can. */
10610 if (imm_expr.X_op == O_constant
10611 && *imm_reloc > BFD_RELOC_UNUSED
10612 && *imm_reloc != BFD_RELOC_MIPS16_GOT16
10613 && *imm_reloc != BFD_RELOC_MIPS16_CALL16
10614 && insn->pinfo != INSN_MACRO)
10618 switch (*offset_reloc)
10620 case BFD_RELOC_MIPS16_HI16_S:
10621 tmp = (imm_expr.X_add_number + 0x8000) >> 16;
10624 case BFD_RELOC_MIPS16_HI16:
10625 tmp = imm_expr.X_add_number >> 16;
10628 case BFD_RELOC_MIPS16_LO16:
10629 tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff)
10633 case BFD_RELOC_UNUSED:
10634 tmp = imm_expr.X_add_number;
10640 *offset_reloc = BFD_RELOC_UNUSED;
10642 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
10643 tmp, TRUE, mips16_small,
10644 mips16_ext, &ip->insn_opcode,
10645 &ip->use_extend, &ip->extend);
10646 imm_expr.X_op = O_absent;
10647 *imm_reloc = BFD_RELOC_UNUSED;
10661 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10664 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10680 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10682 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10686 /* Fall through. */
10697 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
10699 if (c == 'v' || c == 'w')
10702 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10704 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10715 if (c == 'v' || c == 'w')
10717 regno = mips16_to_32_reg_map[lastregno];
10731 regno = mips32_to_16_reg_map[regno];
10736 regno = ILLEGAL_REG;
10741 regno = ILLEGAL_REG;
10746 regno = ILLEGAL_REG;
10751 if (regno == AT && mips_opts.at)
10753 if (mips_opts.at == ATREG)
10754 as_warn (_("used $at without \".set noat\""));
10756 as_warn (_("used $%u with \".set at=$%u\""),
10757 regno, mips_opts.at);
10765 if (regno == ILLEGAL_REG)
10772 MIPS16_INSERT_OPERAND (RX, *ip, regno);
10776 MIPS16_INSERT_OPERAND (RY, *ip, regno);
10779 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
10782 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
10788 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
10791 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
10792 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
10802 if (strncmp (s, "$pc", 3) == 0)
10819 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
10822 if (imm_expr.X_op != O_constant)
10825 ip->use_extend = TRUE;
10830 /* We need to relax this instruction. */
10831 *offset_reloc = *imm_reloc;
10832 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10837 *imm_reloc = BFD_RELOC_UNUSED;
10838 /* Fall through. */
10845 my_getExpression (&imm_expr, s);
10846 if (imm_expr.X_op == O_register)
10848 /* What we thought was an expression turned out to
10851 if (s[0] == '(' && args[1] == '(')
10853 /* It looks like the expression was omitted
10854 before a register indirection, which means
10855 that the expression is implicitly zero. We
10856 still set up imm_expr, so that we handle
10857 explicit extensions correctly. */
10858 imm_expr.X_op = O_constant;
10859 imm_expr.X_add_number = 0;
10860 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10867 /* We need to relax this instruction. */
10868 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10877 /* We use offset_reloc rather than imm_reloc for the PC
10878 relative operands. This lets macros with both
10879 immediate and address operands work correctly. */
10880 my_getExpression (&offset_expr, s);
10882 if (offset_expr.X_op == O_register)
10885 /* We need to relax this instruction. */
10886 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
10890 case '6': /* break code */
10891 my_getExpression (&imm_expr, s);
10892 check_absolute_expr (ip, &imm_expr);
10893 if ((unsigned long) imm_expr.X_add_number > 63)
10894 as_warn (_("Invalid value for `%s' (%lu)"),
10896 (unsigned long) imm_expr.X_add_number);
10897 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
10898 imm_expr.X_op = O_absent;
10902 case 'a': /* 26 bit address */
10903 my_getExpression (&offset_expr, s);
10905 *offset_reloc = BFD_RELOC_MIPS16_JMP;
10906 ip->insn_opcode <<= 16;
10909 case 'l': /* register list for entry macro */
10910 case 'L': /* register list for exit macro */
10920 unsigned int freg, reg1, reg2;
10922 while (*s == ' ' || *s == ',')
10924 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
10926 else if (reg_lookup (&s, RTYPE_FPU, ®1))
10930 as_bad (_("can't parse register list"));
10940 if (!reg_lookup (&s, freg ? RTYPE_FPU
10941 : (RTYPE_GP | RTYPE_NUM), ®2))
10943 as_bad (_("invalid register list"));
10947 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
10949 mask &= ~ (7 << 3);
10952 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
10954 mask &= ~ (7 << 3);
10957 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
10958 mask |= (reg2 - 3) << 3;
10959 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
10960 mask |= (reg2 - 15) << 1;
10961 else if (reg1 == RA && reg2 == RA)
10965 as_bad (_("invalid register list"));
10969 /* The mask is filled in in the opcode table for the
10970 benefit of the disassembler. We remove it before
10971 applying the actual mask. */
10972 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
10973 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
10977 case 'm': /* Register list for save insn. */
10978 case 'M': /* Register list for restore insn. */
10981 int framesz = 0, seen_framesz = 0;
10982 int nargs = 0, statics = 0, sregs = 0;
10986 unsigned int reg1, reg2;
10988 SKIP_SPACE_TABS (s);
10991 SKIP_SPACE_TABS (s);
10993 my_getExpression (&imm_expr, s);
10994 if (imm_expr.X_op == O_constant)
10996 /* Handle the frame size. */
10999 as_bad (_("more than one frame size in list"));
11003 framesz = imm_expr.X_add_number;
11004 imm_expr.X_op = O_absent;
11009 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
11011 as_bad (_("can't parse register list"));
11023 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2)
11026 as_bad (_("can't parse register list"));
11031 while (reg1 <= reg2)
11033 if (reg1 >= 4 && reg1 <= 7)
11037 nargs |= 1 << (reg1 - 4);
11039 /* statics $a0-$a3 */
11040 statics |= 1 << (reg1 - 4);
11042 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
11045 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
11047 else if (reg1 == 31)
11049 /* Add $ra to insn. */
11054 as_bad (_("unexpected register in list"));
11062 /* Encode args/statics combination. */
11063 if (nargs & statics)
11064 as_bad (_("arg/static registers overlap"));
11065 else if (nargs == 0xf)
11066 /* All $a0-$a3 are args. */
11067 opcode |= MIPS16_ALL_ARGS << 16;
11068 else if (statics == 0xf)
11069 /* All $a0-$a3 are statics. */
11070 opcode |= MIPS16_ALL_STATICS << 16;
11073 int narg = 0, nstat = 0;
11075 /* Count arg registers. */
11076 while (nargs & 0x1)
11082 as_bad (_("invalid arg register list"));
11084 /* Count static registers. */
11085 while (statics & 0x8)
11087 statics = (statics << 1) & 0xf;
11091 as_bad (_("invalid static register list"));
11093 /* Encode args/statics. */
11094 opcode |= ((narg << 2) | nstat) << 16;
11097 /* Encode $s0/$s1. */
11098 if (sregs & (1 << 0)) /* $s0 */
11100 if (sregs & (1 << 1)) /* $s1 */
11106 /* Count regs $s2-$s8. */
11114 as_bad (_("invalid static register list"));
11115 /* Encode $s2-$s8. */
11116 opcode |= nsreg << 24;
11119 /* Encode frame size. */
11121 as_bad (_("missing frame size"));
11122 else if ((framesz & 7) != 0 || framesz < 0
11123 || framesz > 0xff * 8)
11124 as_bad (_("invalid frame size"));
11125 else if (framesz != 128 || (opcode >> 16) != 0)
11128 opcode |= (((framesz & 0xf0) << 16)
11129 | (framesz & 0x0f));
11132 /* Finally build the instruction. */
11133 if ((opcode >> 16) != 0 || framesz == 0)
11135 ip->use_extend = TRUE;
11136 ip->extend = opcode >> 16;
11138 ip->insn_opcode |= opcode & 0x7f;
11142 case 'e': /* extend code */
11143 my_getExpression (&imm_expr, s);
11144 check_absolute_expr (ip, &imm_expr);
11145 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
11147 as_warn (_("Invalid value for `%s' (%lu)"),
11149 (unsigned long) imm_expr.X_add_number);
11150 imm_expr.X_add_number &= 0x7ff;
11152 ip->insn_opcode |= imm_expr.X_add_number;
11153 imm_expr.X_op = O_absent;
11163 /* Args don't match. */
11164 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
11165 strcmp (insn->name, insn[1].name) == 0)
11172 insn_error = _("illegal operands");
11178 /* This structure holds information we know about a mips16 immediate
11181 struct mips16_immed_operand
11183 /* The type code used in the argument string in the opcode table. */
11185 /* The number of bits in the short form of the opcode. */
11187 /* The number of bits in the extended form of the opcode. */
11189 /* The amount by which the short form is shifted when it is used;
11190 for example, the sw instruction has a shift count of 2. */
11192 /* The amount by which the short form is shifted when it is stored
11193 into the instruction code. */
11195 /* Non-zero if the short form is unsigned. */
11197 /* Non-zero if the extended form is unsigned. */
11199 /* Non-zero if the value is PC relative. */
11203 /* The mips16 immediate operand types. */
11205 static const struct mips16_immed_operand mips16_immed_operands[] =
11207 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
11208 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
11209 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
11210 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
11211 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
11212 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
11213 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
11214 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
11215 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
11216 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
11217 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
11218 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
11219 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
11220 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
11221 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
11222 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
11223 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
11224 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
11225 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
11226 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
11227 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
11230 #define MIPS16_NUM_IMMED \
11231 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
11233 /* Handle a mips16 instruction with an immediate value. This or's the
11234 small immediate value into *INSN. It sets *USE_EXTEND to indicate
11235 whether an extended value is needed; if one is needed, it sets
11236 *EXTEND to the value. The argument type is TYPE. The value is VAL.
11237 If SMALL is true, an unextended opcode was explicitly requested.
11238 If EXT is true, an extended opcode was explicitly requested. If
11239 WARN is true, warn if EXT does not match reality. */
11242 mips16_immed (char *file, unsigned int line, int type, offsetT val,
11243 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
11244 unsigned long *insn, bfd_boolean *use_extend,
11245 unsigned short *extend)
11247 const struct mips16_immed_operand *op;
11248 int mintiny, maxtiny;
11249 bfd_boolean needext;
11251 op = mips16_immed_operands;
11252 while (op->type != type)
11255 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
11260 if (type == '<' || type == '>' || type == '[' || type == ']')
11263 maxtiny = 1 << op->nbits;
11268 maxtiny = (1 << op->nbits) - 1;
11273 mintiny = - (1 << (op->nbits - 1));
11274 maxtiny = (1 << (op->nbits - 1)) - 1;
11277 /* Branch offsets have an implicit 0 in the lowest bit. */
11278 if (type == 'p' || type == 'q')
11281 if ((val & ((1 << op->shift) - 1)) != 0
11282 || val < (mintiny << op->shift)
11283 || val > (maxtiny << op->shift))
11288 if (warn && ext && ! needext)
11289 as_warn_where (file, line,
11290 _("extended operand requested but not required"));
11291 if (small && needext)
11292 as_bad_where (file, line, _("invalid unextended operand value"));
11294 if (small || (! ext && ! needext))
11298 *use_extend = FALSE;
11299 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
11300 insnval <<= op->op_shift;
11305 long minext, maxext;
11311 maxext = (1 << op->extbits) - 1;
11315 minext = - (1 << (op->extbits - 1));
11316 maxext = (1 << (op->extbits - 1)) - 1;
11318 if (val < minext || val > maxext)
11319 as_bad_where (file, line,
11320 _("operand value out of range for instruction"));
11322 *use_extend = TRUE;
11323 if (op->extbits == 16)
11325 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
11328 else if (op->extbits == 15)
11330 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
11335 extval = ((val & 0x1f) << 6) | (val & 0x20);
11339 *extend = (unsigned short) extval;
11344 struct percent_op_match
11347 bfd_reloc_code_real_type reloc;
11350 static const struct percent_op_match mips_percent_op[] =
11352 {"%lo", BFD_RELOC_LO16},
11354 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
11355 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
11356 {"%call16", BFD_RELOC_MIPS_CALL16},
11357 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
11358 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
11359 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
11360 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
11361 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
11362 {"%got", BFD_RELOC_MIPS_GOT16},
11363 {"%gp_rel", BFD_RELOC_GPREL16},
11364 {"%half", BFD_RELOC_16},
11365 {"%highest", BFD_RELOC_MIPS_HIGHEST},
11366 {"%higher", BFD_RELOC_MIPS_HIGHER},
11367 {"%neg", BFD_RELOC_MIPS_SUB},
11368 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
11369 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
11370 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
11371 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
11372 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
11373 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
11374 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
11376 {"%hi", BFD_RELOC_HI16_S}
11379 static const struct percent_op_match mips16_percent_op[] =
11381 {"%lo", BFD_RELOC_MIPS16_LO16},
11382 {"%gprel", BFD_RELOC_MIPS16_GPREL},
11383 {"%got", BFD_RELOC_MIPS16_GOT16},
11384 {"%call16", BFD_RELOC_MIPS16_CALL16},
11385 {"%hi", BFD_RELOC_MIPS16_HI16_S}
11389 /* Return true if *STR points to a relocation operator. When returning true,
11390 move *STR over the operator and store its relocation code in *RELOC.
11391 Leave both *STR and *RELOC alone when returning false. */
11394 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
11396 const struct percent_op_match *percent_op;
11399 if (mips_opts.mips16)
11401 percent_op = mips16_percent_op;
11402 limit = ARRAY_SIZE (mips16_percent_op);
11406 percent_op = mips_percent_op;
11407 limit = ARRAY_SIZE (mips_percent_op);
11410 for (i = 0; i < limit; i++)
11411 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
11413 int len = strlen (percent_op[i].str);
11415 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
11418 *str += strlen (percent_op[i].str);
11419 *reloc = percent_op[i].reloc;
11421 /* Check whether the output BFD supports this relocation.
11422 If not, issue an error and fall back on something safe. */
11423 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
11425 as_bad (_("relocation %s isn't supported by the current ABI"),
11426 percent_op[i].str);
11427 *reloc = BFD_RELOC_UNUSED;
11435 /* Parse string STR as a 16-bit relocatable operand. Store the
11436 expression in *EP and the relocations in the array starting
11437 at RELOC. Return the number of relocation operators used.
11439 On exit, EXPR_END points to the first character after the expression. */
11442 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
11445 bfd_reloc_code_real_type reversed_reloc[3];
11446 size_t reloc_index, i;
11447 int crux_depth, str_depth;
11450 /* Search for the start of the main expression, recoding relocations
11451 in REVERSED_RELOC. End the loop with CRUX pointing to the start
11452 of the main expression and with CRUX_DEPTH containing the number
11453 of open brackets at that point. */
11460 crux_depth = str_depth;
11462 /* Skip over whitespace and brackets, keeping count of the number
11464 while (*str == ' ' || *str == '\t' || *str == '(')
11469 && reloc_index < (HAVE_NEWABI ? 3 : 1)
11470 && parse_relocation (&str, &reversed_reloc[reloc_index]));
11472 my_getExpression (ep, crux);
11475 /* Match every open bracket. */
11476 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
11480 if (crux_depth > 0)
11481 as_bad (_("unclosed '('"));
11485 if (reloc_index != 0)
11487 prev_reloc_op_frag = frag_now;
11488 for (i = 0; i < reloc_index; i++)
11489 reloc[i] = reversed_reloc[reloc_index - 1 - i];
11492 return reloc_index;
11496 my_getExpression (expressionS *ep, char *str)
11500 save_in = input_line_pointer;
11501 input_line_pointer = str;
11503 expr_end = input_line_pointer;
11504 input_line_pointer = save_in;
11508 md_atof (int type, char *litP, int *sizeP)
11510 return ieee_md_atof (type, litP, sizeP, target_big_endian);
11514 md_number_to_chars (char *buf, valueT val, int n)
11516 if (target_big_endian)
11517 number_to_chars_bigendian (buf, val, n);
11519 number_to_chars_littleendian (buf, val, n);
11523 static int support_64bit_objects(void)
11525 const char **list, **l;
11528 list = bfd_target_list ();
11529 for (l = list; *l != NULL; l++)
11530 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
11531 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
11533 yes = (*l != NULL);
11537 #endif /* OBJ_ELF */
11539 const char *md_shortopts = "O::g::G:";
11543 OPTION_MARCH = OPTION_MD_BASE,
11565 OPTION_NO_SMARTMIPS,
11568 OPTION_COMPAT_ARCH_BASE,
11577 OPTION_M7000_HILO_FIX,
11578 OPTION_MNO_7000_HILO_FIX,
11581 OPTION_FIX_LOONGSON2F_JUMP,
11582 OPTION_NO_FIX_LOONGSON2F_JUMP,
11583 OPTION_FIX_LOONGSON2F_NOP,
11584 OPTION_NO_FIX_LOONGSON2F_NOP,
11586 OPTION_NO_FIX_VR4120,
11588 OPTION_NO_FIX_VR4130,
11589 OPTION_FIX_CN63XXP1,
11590 OPTION_NO_FIX_CN63XXP1,
11597 OPTION_CONSTRUCT_FLOATS,
11598 OPTION_NO_CONSTRUCT_FLOATS,
11601 OPTION_RELAX_BRANCH,
11602 OPTION_NO_RELAX_BRANCH,
11609 OPTION_SINGLE_FLOAT,
11610 OPTION_DOUBLE_FLOAT,
11613 OPTION_CALL_SHARED,
11614 OPTION_CALL_NONPIC,
11624 OPTION_MVXWORKS_PIC,
11625 #endif /* OBJ_ELF */
11629 struct option md_longopts[] =
11631 /* Options which specify architecture. */
11632 {"march", required_argument, NULL, OPTION_MARCH},
11633 {"mtune", required_argument, NULL, OPTION_MTUNE},
11634 {"mips0", no_argument, NULL, OPTION_MIPS1},
11635 {"mips1", no_argument, NULL, OPTION_MIPS1},
11636 {"mips2", no_argument, NULL, OPTION_MIPS2},
11637 {"mips3", no_argument, NULL, OPTION_MIPS3},
11638 {"mips4", no_argument, NULL, OPTION_MIPS4},
11639 {"mips5", no_argument, NULL, OPTION_MIPS5},
11640 {"mips32", no_argument, NULL, OPTION_MIPS32},
11641 {"mips64", no_argument, NULL, OPTION_MIPS64},
11642 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
11643 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
11645 /* Options which specify Application Specific Extensions (ASEs). */
11646 {"mips16", no_argument, NULL, OPTION_MIPS16},
11647 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
11648 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
11649 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
11650 {"mdmx", no_argument, NULL, OPTION_MDMX},
11651 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
11652 {"mdsp", no_argument, NULL, OPTION_DSP},
11653 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
11654 {"mmt", no_argument, NULL, OPTION_MT},
11655 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
11656 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
11657 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
11658 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
11659 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
11661 /* Old-style architecture options. Don't add more of these. */
11662 {"m4650", no_argument, NULL, OPTION_M4650},
11663 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
11664 {"m4010", no_argument, NULL, OPTION_M4010},
11665 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
11666 {"m4100", no_argument, NULL, OPTION_M4100},
11667 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
11668 {"m3900", no_argument, NULL, OPTION_M3900},
11669 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
11671 /* Options which enable bug fixes. */
11672 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
11673 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
11674 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
11675 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
11676 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
11677 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
11678 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
11679 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
11680 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
11681 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
11682 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
11683 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
11684 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
11685 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
11686 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
11688 /* Miscellaneous options. */
11689 {"trap", no_argument, NULL, OPTION_TRAP},
11690 {"no-break", no_argument, NULL, OPTION_TRAP},
11691 {"break", no_argument, NULL, OPTION_BREAK},
11692 {"no-trap", no_argument, NULL, OPTION_BREAK},
11693 {"EB", no_argument, NULL, OPTION_EB},
11694 {"EL", no_argument, NULL, OPTION_EL},
11695 {"mfp32", no_argument, NULL, OPTION_FP32},
11696 {"mgp32", no_argument, NULL, OPTION_GP32},
11697 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
11698 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
11699 {"mfp64", no_argument, NULL, OPTION_FP64},
11700 {"mgp64", no_argument, NULL, OPTION_GP64},
11701 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
11702 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
11703 {"mshared", no_argument, NULL, OPTION_MSHARED},
11704 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
11705 {"msym32", no_argument, NULL, OPTION_MSYM32},
11706 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
11707 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
11708 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
11709 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
11710 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
11712 /* Strictly speaking this next option is ELF specific,
11713 but we allow it for other ports as well in order to
11714 make testing easier. */
11715 {"32", no_argument, NULL, OPTION_32},
11717 /* ELF-specific options. */
11719 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
11720 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
11721 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
11722 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
11723 {"xgot", no_argument, NULL, OPTION_XGOT},
11724 {"mabi", required_argument, NULL, OPTION_MABI},
11725 {"n32", no_argument, NULL, OPTION_N32},
11726 {"64", no_argument, NULL, OPTION_64},
11727 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
11728 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
11729 {"mpdr", no_argument, NULL, OPTION_PDR},
11730 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
11731 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
11732 #endif /* OBJ_ELF */
11734 {NULL, no_argument, NULL, 0}
11736 size_t md_longopts_size = sizeof (md_longopts);
11738 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
11739 NEW_VALUE. Warn if another value was already specified. Note:
11740 we have to defer parsing the -march and -mtune arguments in order
11741 to handle 'from-abi' correctly, since the ABI might be specified
11742 in a later argument. */
11745 mips_set_option_string (const char **string_ptr, const char *new_value)
11747 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
11748 as_warn (_("A different %s was already specified, is now %s"),
11749 string_ptr == &mips_arch_string ? "-march" : "-mtune",
11752 *string_ptr = new_value;
11756 md_parse_option (int c, char *arg)
11760 case OPTION_CONSTRUCT_FLOATS:
11761 mips_disable_float_construction = 0;
11764 case OPTION_NO_CONSTRUCT_FLOATS:
11765 mips_disable_float_construction = 1;
11777 target_big_endian = 1;
11781 target_big_endian = 0;
11787 else if (arg[0] == '0')
11789 else if (arg[0] == '1')
11799 mips_debug = atoi (arg);
11803 file_mips_isa = ISA_MIPS1;
11807 file_mips_isa = ISA_MIPS2;
11811 file_mips_isa = ISA_MIPS3;
11815 file_mips_isa = ISA_MIPS4;
11819 file_mips_isa = ISA_MIPS5;
11822 case OPTION_MIPS32:
11823 file_mips_isa = ISA_MIPS32;
11826 case OPTION_MIPS32R2:
11827 file_mips_isa = ISA_MIPS32R2;
11830 case OPTION_MIPS64R2:
11831 file_mips_isa = ISA_MIPS64R2;
11834 case OPTION_MIPS64:
11835 file_mips_isa = ISA_MIPS64;
11839 mips_set_option_string (&mips_tune_string, arg);
11843 mips_set_option_string (&mips_arch_string, arg);
11847 mips_set_option_string (&mips_arch_string, "4650");
11848 mips_set_option_string (&mips_tune_string, "4650");
11851 case OPTION_NO_M4650:
11855 mips_set_option_string (&mips_arch_string, "4010");
11856 mips_set_option_string (&mips_tune_string, "4010");
11859 case OPTION_NO_M4010:
11863 mips_set_option_string (&mips_arch_string, "4100");
11864 mips_set_option_string (&mips_tune_string, "4100");
11867 case OPTION_NO_M4100:
11871 mips_set_option_string (&mips_arch_string, "3900");
11872 mips_set_option_string (&mips_tune_string, "3900");
11875 case OPTION_NO_M3900:
11879 mips_opts.ase_mdmx = 1;
11882 case OPTION_NO_MDMX:
11883 mips_opts.ase_mdmx = 0;
11887 mips_opts.ase_dsp = 1;
11888 mips_opts.ase_dspr2 = 0;
11891 case OPTION_NO_DSP:
11892 mips_opts.ase_dsp = 0;
11893 mips_opts.ase_dspr2 = 0;
11897 mips_opts.ase_dspr2 = 1;
11898 mips_opts.ase_dsp = 1;
11901 case OPTION_NO_DSPR2:
11902 mips_opts.ase_dspr2 = 0;
11903 mips_opts.ase_dsp = 0;
11907 mips_opts.ase_mt = 1;
11911 mips_opts.ase_mt = 0;
11914 case OPTION_MIPS16:
11915 mips_opts.mips16 = 1;
11916 mips_no_prev_insn ();
11919 case OPTION_NO_MIPS16:
11920 mips_opts.mips16 = 0;
11921 mips_no_prev_insn ();
11924 case OPTION_MIPS3D:
11925 mips_opts.ase_mips3d = 1;
11928 case OPTION_NO_MIPS3D:
11929 mips_opts.ase_mips3d = 0;
11932 case OPTION_SMARTMIPS:
11933 mips_opts.ase_smartmips = 1;
11936 case OPTION_NO_SMARTMIPS:
11937 mips_opts.ase_smartmips = 0;
11940 case OPTION_FIX_24K:
11944 case OPTION_NO_FIX_24K:
11948 case OPTION_FIX_LOONGSON2F_JUMP:
11949 mips_fix_loongson2f_jump = TRUE;
11952 case OPTION_NO_FIX_LOONGSON2F_JUMP:
11953 mips_fix_loongson2f_jump = FALSE;
11956 case OPTION_FIX_LOONGSON2F_NOP:
11957 mips_fix_loongson2f_nop = TRUE;
11960 case OPTION_NO_FIX_LOONGSON2F_NOP:
11961 mips_fix_loongson2f_nop = FALSE;
11964 case OPTION_FIX_VR4120:
11965 mips_fix_vr4120 = 1;
11968 case OPTION_NO_FIX_VR4120:
11969 mips_fix_vr4120 = 0;
11972 case OPTION_FIX_VR4130:
11973 mips_fix_vr4130 = 1;
11976 case OPTION_NO_FIX_VR4130:
11977 mips_fix_vr4130 = 0;
11980 case OPTION_FIX_CN63XXP1:
11981 mips_fix_cn63xxp1 = TRUE;
11984 case OPTION_NO_FIX_CN63XXP1:
11985 mips_fix_cn63xxp1 = FALSE;
11988 case OPTION_RELAX_BRANCH:
11989 mips_relax_branch = 1;
11992 case OPTION_NO_RELAX_BRANCH:
11993 mips_relax_branch = 0;
11996 case OPTION_MSHARED:
11997 mips_in_shared = TRUE;
12000 case OPTION_MNO_SHARED:
12001 mips_in_shared = FALSE;
12004 case OPTION_MSYM32:
12005 mips_opts.sym32 = TRUE;
12008 case OPTION_MNO_SYM32:
12009 mips_opts.sym32 = FALSE;
12013 /* When generating ELF code, we permit -KPIC and -call_shared to
12014 select SVR4_PIC, and -non_shared to select no PIC. This is
12015 intended to be compatible with Irix 5. */
12016 case OPTION_CALL_SHARED:
12019 as_bad (_("-call_shared is supported only for ELF format"));
12022 mips_pic = SVR4_PIC;
12023 mips_abicalls = TRUE;
12026 case OPTION_CALL_NONPIC:
12029 as_bad (_("-call_nonpic is supported only for ELF format"));
12033 mips_abicalls = TRUE;
12036 case OPTION_NON_SHARED:
12039 as_bad (_("-non_shared is supported only for ELF format"));
12043 mips_abicalls = FALSE;
12046 /* The -xgot option tells the assembler to use 32 bit offsets
12047 when accessing the got in SVR4_PIC mode. It is for Irix
12052 #endif /* OBJ_ELF */
12055 g_switch_value = atoi (arg);
12059 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
12063 mips_abi = O32_ABI;
12064 /* We silently ignore -32 for non-ELF targets. This greatly
12065 simplifies the construction of the MIPS GAS test cases. */
12072 as_bad (_("-n32 is supported for ELF format only"));
12075 mips_abi = N32_ABI;
12081 as_bad (_("-64 is supported for ELF format only"));
12084 mips_abi = N64_ABI;
12085 if (!support_64bit_objects())
12086 as_fatal (_("No compiled in support for 64 bit object file format"));
12088 #endif /* OBJ_ELF */
12091 file_mips_gp32 = 1;
12095 file_mips_gp32 = 0;
12099 file_mips_fp32 = 1;
12103 file_mips_fp32 = 0;
12106 case OPTION_SINGLE_FLOAT:
12107 file_mips_single_float = 1;
12110 case OPTION_DOUBLE_FLOAT:
12111 file_mips_single_float = 0;
12114 case OPTION_SOFT_FLOAT:
12115 file_mips_soft_float = 1;
12118 case OPTION_HARD_FLOAT:
12119 file_mips_soft_float = 0;
12126 as_bad (_("-mabi is supported for ELF format only"));
12129 if (strcmp (arg, "32") == 0)
12130 mips_abi = O32_ABI;
12131 else if (strcmp (arg, "o64") == 0)
12132 mips_abi = O64_ABI;
12133 else if (strcmp (arg, "n32") == 0)
12134 mips_abi = N32_ABI;
12135 else if (strcmp (arg, "64") == 0)
12137 mips_abi = N64_ABI;
12138 if (! support_64bit_objects())
12139 as_fatal (_("No compiled in support for 64 bit object file "
12142 else if (strcmp (arg, "eabi") == 0)
12143 mips_abi = EABI_ABI;
12146 as_fatal (_("invalid abi -mabi=%s"), arg);
12150 #endif /* OBJ_ELF */
12152 case OPTION_M7000_HILO_FIX:
12153 mips_7000_hilo_fix = TRUE;
12156 case OPTION_MNO_7000_HILO_FIX:
12157 mips_7000_hilo_fix = FALSE;
12161 case OPTION_MDEBUG:
12162 mips_flag_mdebug = TRUE;
12165 case OPTION_NO_MDEBUG:
12166 mips_flag_mdebug = FALSE;
12170 mips_flag_pdr = TRUE;
12173 case OPTION_NO_PDR:
12174 mips_flag_pdr = FALSE;
12177 case OPTION_MVXWORKS_PIC:
12178 mips_pic = VXWORKS_PIC;
12180 #endif /* OBJ_ELF */
12186 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
12191 /* Set up globals to generate code for the ISA or processor
12192 described by INFO. */
12195 mips_set_architecture (const struct mips_cpu_info *info)
12199 file_mips_arch = info->cpu;
12200 mips_opts.arch = info->cpu;
12201 mips_opts.isa = info->isa;
12206 /* Likewise for tuning. */
12209 mips_set_tune (const struct mips_cpu_info *info)
12212 mips_tune = info->cpu;
12217 mips_after_parse_args (void)
12219 const struct mips_cpu_info *arch_info = 0;
12220 const struct mips_cpu_info *tune_info = 0;
12222 /* GP relative stuff not working for PE */
12223 if (strncmp (TARGET_OS, "pe", 2) == 0)
12225 if (g_switch_seen && g_switch_value != 0)
12226 as_bad (_("-G not supported in this configuration."));
12227 g_switch_value = 0;
12230 if (mips_abi == NO_ABI)
12231 mips_abi = MIPS_DEFAULT_ABI;
12233 /* The following code determines the architecture and register size.
12234 Similar code was added to GCC 3.3 (see override_options() in
12235 config/mips/mips.c). The GAS and GCC code should be kept in sync
12236 as much as possible. */
12238 if (mips_arch_string != 0)
12239 arch_info = mips_parse_cpu ("-march", mips_arch_string);
12241 if (file_mips_isa != ISA_UNKNOWN)
12243 /* Handle -mipsN. At this point, file_mips_isa contains the
12244 ISA level specified by -mipsN, while arch_info->isa contains
12245 the -march selection (if any). */
12246 if (arch_info != 0)
12248 /* -march takes precedence over -mipsN, since it is more descriptive.
12249 There's no harm in specifying both as long as the ISA levels
12251 if (file_mips_isa != arch_info->isa)
12252 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
12253 mips_cpu_info_from_isa (file_mips_isa)->name,
12254 mips_cpu_info_from_isa (arch_info->isa)->name);
12257 arch_info = mips_cpu_info_from_isa (file_mips_isa);
12260 if (arch_info == 0)
12261 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
12263 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
12264 as_bad (_("-march=%s is not compatible with the selected ABI"),
12267 mips_set_architecture (arch_info);
12269 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
12270 if (mips_tune_string != 0)
12271 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
12273 if (tune_info == 0)
12274 mips_set_tune (arch_info);
12276 mips_set_tune (tune_info);
12278 if (file_mips_gp32 >= 0)
12280 /* The user specified the size of the integer registers. Make sure
12281 it agrees with the ABI and ISA. */
12282 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
12283 as_bad (_("-mgp64 used with a 32-bit processor"));
12284 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
12285 as_bad (_("-mgp32 used with a 64-bit ABI"));
12286 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
12287 as_bad (_("-mgp64 used with a 32-bit ABI"));
12291 /* Infer the integer register size from the ABI and processor.
12292 Restrict ourselves to 32-bit registers if that's all the
12293 processor has, or if the ABI cannot handle 64-bit registers. */
12294 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
12295 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
12298 switch (file_mips_fp32)
12302 /* No user specified float register size.
12303 ??? GAS treats single-float processors as though they had 64-bit
12304 float registers (although it complains when double-precision
12305 instructions are used). As things stand, saying they have 32-bit
12306 registers would lead to spurious "register must be even" messages.
12307 So here we assume float registers are never smaller than the
12309 if (file_mips_gp32 == 0)
12310 /* 64-bit integer registers implies 64-bit float registers. */
12311 file_mips_fp32 = 0;
12312 else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
12313 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
12314 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
12315 file_mips_fp32 = 0;
12317 /* 32-bit float registers. */
12318 file_mips_fp32 = 1;
12321 /* The user specified the size of the float registers. Check if it
12322 agrees with the ABI and ISA. */
12324 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
12325 as_bad (_("-mfp64 used with a 32-bit fpu"));
12326 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
12327 && !ISA_HAS_MXHC1 (mips_opts.isa))
12328 as_warn (_("-mfp64 used with a 32-bit ABI"));
12331 if (ABI_NEEDS_64BIT_REGS (mips_abi))
12332 as_warn (_("-mfp32 used with a 64-bit ABI"));
12336 /* End of GCC-shared inference code. */
12338 /* This flag is set when we have a 64-bit capable CPU but use only
12339 32-bit wide registers. Note that EABI does not use it. */
12340 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
12341 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
12342 || mips_abi == O32_ABI))
12343 mips_32bitmode = 1;
12345 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
12346 as_bad (_("trap exception not supported at ISA 1"));
12348 /* If the selected architecture includes support for ASEs, enable
12349 generation of code for them. */
12350 if (mips_opts.mips16 == -1)
12351 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
12352 if (mips_opts.ase_mips3d == -1)
12353 mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
12354 && file_mips_fp32 == 0) ? 1 : 0;
12355 if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
12356 as_bad (_("-mfp32 used with -mips3d"));
12358 if (mips_opts.ase_mdmx == -1)
12359 mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
12360 && file_mips_fp32 == 0) ? 1 : 0;
12361 if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
12362 as_bad (_("-mfp32 used with -mdmx"));
12364 if (mips_opts.ase_smartmips == -1)
12365 mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
12366 if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
12367 as_warn (_("%s ISA does not support SmartMIPS"),
12368 mips_cpu_info_from_isa (mips_opts.isa)->name);
12370 if (mips_opts.ase_dsp == -1)
12371 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
12372 if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
12373 as_warn (_("%s ISA does not support DSP ASE"),
12374 mips_cpu_info_from_isa (mips_opts.isa)->name);
12376 if (mips_opts.ase_dspr2 == -1)
12378 mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
12379 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
12381 if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
12382 as_warn (_("%s ISA does not support DSP R2 ASE"),
12383 mips_cpu_info_from_isa (mips_opts.isa)->name);
12385 if (mips_opts.ase_mt == -1)
12386 mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
12387 if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
12388 as_warn (_("%s ISA does not support MT ASE"),
12389 mips_cpu_info_from_isa (mips_opts.isa)->name);
12391 file_mips_isa = mips_opts.isa;
12392 file_ase_mips3d = mips_opts.ase_mips3d;
12393 file_ase_mdmx = mips_opts.ase_mdmx;
12394 file_ase_smartmips = mips_opts.ase_smartmips;
12395 file_ase_dsp = mips_opts.ase_dsp;
12396 file_ase_dspr2 = mips_opts.ase_dspr2;
12397 file_ase_mt = mips_opts.ase_mt;
12398 mips_opts.gp32 = file_mips_gp32;
12399 mips_opts.fp32 = file_mips_fp32;
12400 mips_opts.soft_float = file_mips_soft_float;
12401 mips_opts.single_float = file_mips_single_float;
12403 if (mips_flag_mdebug < 0)
12405 #ifdef OBJ_MAYBE_ECOFF
12406 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
12407 mips_flag_mdebug = 1;
12409 #endif /* OBJ_MAYBE_ECOFF */
12410 mips_flag_mdebug = 0;
12415 mips_init_after_args (void)
12417 /* initialize opcodes */
12418 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
12419 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
12423 md_pcrel_from (fixS *fixP)
12425 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
12426 switch (fixP->fx_r_type)
12428 case BFD_RELOC_16_PCREL_S2:
12429 case BFD_RELOC_MIPS_JMP:
12430 /* Return the address of the delay slot. */
12433 /* We have no relocation type for PC relative MIPS16 instructions. */
12434 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
12435 as_bad_where (fixP->fx_file, fixP->fx_line,
12436 _("PC relative MIPS16 instruction references a different section"));
12441 /* This is called before the symbol table is processed. In order to
12442 work with gcc when using mips-tfile, we must keep all local labels.
12443 However, in other cases, we want to discard them. If we were
12444 called with -g, but we didn't see any debugging information, it may
12445 mean that gcc is smuggling debugging information through to
12446 mips-tfile, in which case we must generate all local labels. */
12449 mips_frob_file_before_adjust (void)
12451 #ifndef NO_ECOFF_DEBUGGING
12452 if (ECOFF_DEBUGGING
12454 && ! ecoff_debugging_seen)
12455 flag_keep_locals = 1;
12459 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
12460 the corresponding LO16 reloc. This is called before md_apply_fix and
12461 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
12462 relocation operators.
12464 For our purposes, a %lo() expression matches a %got() or %hi()
12467 (a) it refers to the same symbol; and
12468 (b) the offset applied in the %lo() expression is no lower than
12469 the offset applied in the %got() or %hi().
12471 (b) allows us to cope with code like:
12474 lh $4,%lo(foo+2)($4)
12476 ...which is legal on RELA targets, and has a well-defined behaviour
12477 if the user knows that adding 2 to "foo" will not induce a carry to
12480 When several %lo()s match a particular %got() or %hi(), we use the
12481 following rules to distinguish them:
12483 (1) %lo()s with smaller offsets are a better match than %lo()s with
12486 (2) %lo()s with no matching %got() or %hi() are better than those
12487 that already have a matching %got() or %hi().
12489 (3) later %lo()s are better than earlier %lo()s.
12491 These rules are applied in order.
12493 (1) means, among other things, that %lo()s with identical offsets are
12494 chosen if they exist.
12496 (2) means that we won't associate several high-part relocations with
12497 the same low-part relocation unless there's no alternative. Having
12498 several high parts for the same low part is a GNU extension; this rule
12499 allows careful users to avoid it.
12501 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
12502 with the last high-part relocation being at the front of the list.
12503 It therefore makes sense to choose the last matching low-part
12504 relocation, all other things being equal. It's also easier
12505 to code that way. */
12508 mips_frob_file (void)
12510 struct mips_hi_fixup *l;
12511 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
12513 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
12515 segment_info_type *seginfo;
12516 bfd_boolean matched_lo_p;
12517 fixS **hi_pos, **lo_pos, **pos;
12519 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
12521 /* If a GOT16 relocation turns out to be against a global symbol,
12522 there isn't supposed to be a matching LO. */
12523 if (got16_reloc_p (l->fixp->fx_r_type)
12524 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
12527 /* Check quickly whether the next fixup happens to be a matching %lo. */
12528 if (fixup_has_matching_lo_p (l->fixp))
12531 seginfo = seg_info (l->seg);
12533 /* Set HI_POS to the position of this relocation in the chain.
12534 Set LO_POS to the position of the chosen low-part relocation.
12535 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
12536 relocation that matches an immediately-preceding high-part
12540 matched_lo_p = FALSE;
12541 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
12543 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
12545 if (*pos == l->fixp)
12548 if ((*pos)->fx_r_type == looking_for_rtype
12549 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
12550 && (*pos)->fx_offset >= l->fixp->fx_offset
12552 || (*pos)->fx_offset < (*lo_pos)->fx_offset
12554 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
12557 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
12558 && fixup_has_matching_lo_p (*pos));
12561 /* If we found a match, remove the high-part relocation from its
12562 current position and insert it before the low-part relocation.
12563 Make the offsets match so that fixup_has_matching_lo_p()
12566 We don't warn about unmatched high-part relocations since some
12567 versions of gcc have been known to emit dead "lui ...%hi(...)"
12569 if (lo_pos != NULL)
12571 l->fixp->fx_offset = (*lo_pos)->fx_offset;
12572 if (l->fixp->fx_next != *lo_pos)
12574 *hi_pos = l->fixp->fx_next;
12575 l->fixp->fx_next = *lo_pos;
12582 /* We may have combined relocations without symbols in the N32/N64 ABI.
12583 We have to prevent gas from dropping them. */
12586 mips_force_relocation (fixS *fixp)
12588 if (generic_force_reloc (fixp))
12592 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
12593 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
12594 || hi16_reloc_p (fixp->fx_r_type)
12595 || lo16_reloc_p (fixp->fx_r_type)))
12601 /* Apply a fixup to the object file. */
12604 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
12608 reloc_howto_type *howto;
12610 /* We ignore generic BFD relocations we don't know about. */
12611 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
12615 gas_assert (fixP->fx_size == 4
12616 || fixP->fx_r_type == BFD_RELOC_16
12617 || fixP->fx_r_type == BFD_RELOC_64
12618 || fixP->fx_r_type == BFD_RELOC_CTOR
12619 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
12620 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12621 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
12622 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
12624 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
12626 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2);
12628 /* Don't treat parts of a composite relocation as done. There are two
12631 (1) The second and third parts will be against 0 (RSS_UNDEF) but
12632 should nevertheless be emitted if the first part is.
12634 (2) In normal usage, composite relocations are never assembly-time
12635 constants. The easiest way of dealing with the pathological
12636 exceptions is to generate a relocation against STN_UNDEF and
12637 leave everything up to the linker. */
12638 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
12641 switch (fixP->fx_r_type)
12643 case BFD_RELOC_MIPS_TLS_GD:
12644 case BFD_RELOC_MIPS_TLS_LDM:
12645 case BFD_RELOC_MIPS_TLS_DTPREL32:
12646 case BFD_RELOC_MIPS_TLS_DTPREL64:
12647 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
12648 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
12649 case BFD_RELOC_MIPS_TLS_GOTTPREL:
12650 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
12651 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
12652 S_SET_THREAD_LOCAL (fixP->fx_addsy);
12655 case BFD_RELOC_MIPS_JMP:
12656 case BFD_RELOC_MIPS_SHIFT5:
12657 case BFD_RELOC_MIPS_SHIFT6:
12658 case BFD_RELOC_MIPS_GOT_DISP:
12659 case BFD_RELOC_MIPS_GOT_PAGE:
12660 case BFD_RELOC_MIPS_GOT_OFST:
12661 case BFD_RELOC_MIPS_SUB:
12662 case BFD_RELOC_MIPS_INSERT_A:
12663 case BFD_RELOC_MIPS_INSERT_B:
12664 case BFD_RELOC_MIPS_DELETE:
12665 case BFD_RELOC_MIPS_HIGHEST:
12666 case BFD_RELOC_MIPS_HIGHER:
12667 case BFD_RELOC_MIPS_SCN_DISP:
12668 case BFD_RELOC_MIPS_REL16:
12669 case BFD_RELOC_MIPS_RELGOT:
12670 case BFD_RELOC_MIPS_JALR:
12671 case BFD_RELOC_HI16:
12672 case BFD_RELOC_HI16_S:
12673 case BFD_RELOC_GPREL16:
12674 case BFD_RELOC_MIPS_LITERAL:
12675 case BFD_RELOC_MIPS_CALL16:
12676 case BFD_RELOC_MIPS_GOT16:
12677 case BFD_RELOC_GPREL32:
12678 case BFD_RELOC_MIPS_GOT_HI16:
12679 case BFD_RELOC_MIPS_GOT_LO16:
12680 case BFD_RELOC_MIPS_CALL_HI16:
12681 case BFD_RELOC_MIPS_CALL_LO16:
12682 case BFD_RELOC_MIPS16_GPREL:
12683 case BFD_RELOC_MIPS16_GOT16:
12684 case BFD_RELOC_MIPS16_CALL16:
12685 case BFD_RELOC_MIPS16_HI16:
12686 case BFD_RELOC_MIPS16_HI16_S:
12687 case BFD_RELOC_MIPS16_JMP:
12688 /* Nothing needed to do. The value comes from the reloc entry. */
12692 /* This is handled like BFD_RELOC_32, but we output a sign
12693 extended value if we are only 32 bits. */
12696 if (8 <= sizeof (valueT))
12697 md_number_to_chars ((char *) buf, *valP, 8);
12702 if ((*valP & 0x80000000) != 0)
12706 md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)),
12708 md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)),
12714 case BFD_RELOC_RVA:
12717 /* If we are deleting this reloc entry, we must fill in the
12718 value now. This can happen if we have a .word which is not
12719 resolved when it appears but is later defined. */
12721 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
12724 case BFD_RELOC_LO16:
12725 case BFD_RELOC_MIPS16_LO16:
12726 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
12727 may be safe to remove, but if so it's not obvious. */
12728 /* When handling an embedded PIC switch statement, we can wind
12729 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
12732 if (*valP + 0x8000 > 0xffff)
12733 as_bad_where (fixP->fx_file, fixP->fx_line,
12734 _("relocation overflow"));
12735 if (target_big_endian)
12737 md_number_to_chars ((char *) buf, *valP, 2);
12741 case BFD_RELOC_16_PCREL_S2:
12742 if ((*valP & 0x3) != 0)
12743 as_bad_where (fixP->fx_file, fixP->fx_line,
12744 _("Branch to misaligned address (%lx)"), (long) *valP);
12746 /* We need to save the bits in the instruction since fixup_segment()
12747 might be deleting the relocation entry (i.e., a branch within
12748 the current segment). */
12749 if (! fixP->fx_done)
12752 /* Update old instruction data. */
12753 if (target_big_endian)
12754 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
12756 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
12758 if (*valP + 0x20000 <= 0x3ffff)
12760 insn |= (*valP >> 2) & 0xffff;
12761 md_number_to_chars ((char *) buf, insn, 4);
12763 else if (mips_pic == NO_PIC
12765 && fixP->fx_frag->fr_address >= text_section->vma
12766 && (fixP->fx_frag->fr_address
12767 < text_section->vma + bfd_get_section_size (text_section))
12768 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
12769 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
12770 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
12772 /* The branch offset is too large. If this is an
12773 unconditional branch, and we are not generating PIC code,
12774 we can convert it to an absolute jump instruction. */
12775 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
12776 insn = 0x0c000000; /* jal */
12778 insn = 0x08000000; /* j */
12779 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
12781 fixP->fx_addsy = section_symbol (text_section);
12782 *valP += md_pcrel_from (fixP);
12783 md_number_to_chars ((char *) buf, insn, 4);
12787 /* If we got here, we have branch-relaxation disabled,
12788 and there's nothing we can do to fix this instruction
12789 without turning it into a longer sequence. */
12790 as_bad_where (fixP->fx_file, fixP->fx_line,
12791 _("Branch out of range"));
12795 case BFD_RELOC_VTABLE_INHERIT:
12798 && !S_IS_DEFINED (fixP->fx_addsy)
12799 && !S_IS_WEAK (fixP->fx_addsy))
12800 S_SET_WEAK (fixP->fx_addsy);
12803 case BFD_RELOC_VTABLE_ENTRY:
12811 /* Remember value for tc_gen_reloc. */
12812 fixP->fx_addnumber = *valP;
12822 name = input_line_pointer;
12823 c = get_symbol_end ();
12824 p = (symbolS *) symbol_find_or_make (name);
12825 *input_line_pointer = c;
12829 /* Align the current frag to a given power of two. If a particular
12830 fill byte should be used, FILL points to an integer that contains
12831 that byte, otherwise FILL is null.
12833 The MIPS assembler also automatically adjusts any preceding
12837 mips_align (int to, int *fill, symbolS *label)
12839 mips_emit_delays ();
12840 mips_record_mips16_mode ();
12841 if (fill == NULL && subseg_text_p (now_seg))
12842 frag_align_code (to, 0);
12844 frag_align (to, fill ? *fill : 0, 0);
12845 record_alignment (now_seg, to);
12848 gas_assert (S_GET_SEGMENT (label) == now_seg);
12849 symbol_set_frag (label, frag_now);
12850 S_SET_VALUE (label, (valueT) frag_now_fix ());
12854 /* Align to a given power of two. .align 0 turns off the automatic
12855 alignment used by the data creating pseudo-ops. */
12858 s_align (int x ATTRIBUTE_UNUSED)
12860 int temp, fill_value, *fill_ptr;
12861 long max_alignment = 28;
12863 /* o Note that the assembler pulls down any immediately preceding label
12864 to the aligned address.
12865 o It's not documented but auto alignment is reinstated by
12866 a .align pseudo instruction.
12867 o Note also that after auto alignment is turned off the mips assembler
12868 issues an error on attempt to assemble an improperly aligned data item.
12871 temp = get_absolute_expression ();
12872 if (temp > max_alignment)
12873 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
12876 as_warn (_("Alignment negative: 0 assumed."));
12879 if (*input_line_pointer == ',')
12881 ++input_line_pointer;
12882 fill_value = get_absolute_expression ();
12883 fill_ptr = &fill_value;
12889 segment_info_type *si = seg_info (now_seg);
12890 struct insn_label_list *l = si->label_list;
12891 /* Auto alignment should be switched on by next section change. */
12893 mips_align (temp, fill_ptr, l != NULL ? l->label : NULL);
12900 demand_empty_rest_of_line ();
12904 s_change_sec (int sec)
12909 /* The ELF backend needs to know that we are changing sections, so
12910 that .previous works correctly. We could do something like check
12911 for an obj_section_change_hook macro, but that might be confusing
12912 as it would not be appropriate to use it in the section changing
12913 functions in read.c, since obj-elf.c intercepts those. FIXME:
12914 This should be cleaner, somehow. */
12916 obj_elf_section_change_hook ();
12919 mips_emit_delays ();
12930 subseg_set (bss_section, (subsegT) get_absolute_expression ());
12931 demand_empty_rest_of_line ();
12935 seg = subseg_new (RDATA_SECTION_NAME,
12936 (subsegT) get_absolute_expression ());
12939 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
12940 | SEC_READONLY | SEC_RELOC
12942 if (strncmp (TARGET_OS, "elf", 3) != 0)
12943 record_alignment (seg, 4);
12945 demand_empty_rest_of_line ();
12949 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
12952 bfd_set_section_flags (stdoutput, seg,
12953 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
12954 if (strncmp (TARGET_OS, "elf", 3) != 0)
12955 record_alignment (seg, 4);
12957 demand_empty_rest_of_line ();
12961 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
12964 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
12965 if (strncmp (TARGET_OS, "elf", 3) != 0)
12966 record_alignment (seg, 4);
12968 demand_empty_rest_of_line ();
12976 s_change_section (int ignore ATTRIBUTE_UNUSED)
12979 char *section_name;
12984 int section_entry_size;
12985 int section_alignment;
12990 section_name = input_line_pointer;
12991 c = get_symbol_end ();
12993 next_c = *(input_line_pointer + 1);
12995 /* Do we have .section Name<,"flags">? */
12996 if (c != ',' || (c == ',' && next_c == '"'))
12998 /* just after name is now '\0'. */
12999 *input_line_pointer = c;
13000 input_line_pointer = section_name;
13001 obj_elf_section (ignore);
13004 input_line_pointer++;
13006 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
13008 section_type = get_absolute_expression ();
13011 if (*input_line_pointer++ == ',')
13012 section_flag = get_absolute_expression ();
13015 if (*input_line_pointer++ == ',')
13016 section_entry_size = get_absolute_expression ();
13018 section_entry_size = 0;
13019 if (*input_line_pointer++ == ',')
13020 section_alignment = get_absolute_expression ();
13022 section_alignment = 0;
13023 /* FIXME: really ignore? */
13024 (void) section_alignment;
13026 section_name = xstrdup (section_name);
13028 /* When using the generic form of .section (as implemented by obj-elf.c),
13029 there's no way to set the section type to SHT_MIPS_DWARF. Users have
13030 traditionally had to fall back on the more common @progbits instead.
13032 There's nothing really harmful in this, since bfd will correct
13033 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
13034 means that, for backwards compatibility, the special_section entries
13035 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
13037 Even so, we shouldn't force users of the MIPS .section syntax to
13038 incorrectly label the sections as SHT_PROGBITS. The best compromise
13039 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
13040 generic type-checking code. */
13041 if (section_type == SHT_MIPS_DWARF)
13042 section_type = SHT_PROGBITS;
13044 obj_elf_change_section (section_name, section_type, section_flag,
13045 section_entry_size, 0, 0, 0);
13047 if (now_seg->name != section_name)
13048 free (section_name);
13049 #endif /* OBJ_ELF */
13053 mips_enable_auto_align (void)
13059 s_cons (int log_size)
13061 segment_info_type *si = seg_info (now_seg);
13062 struct insn_label_list *l = si->label_list;
13065 label = l != NULL ? l->label : NULL;
13066 mips_emit_delays ();
13067 if (log_size > 0 && auto_align)
13068 mips_align (log_size, 0, label);
13069 cons (1 << log_size);
13070 mips_clear_insn_labels ();
13074 s_float_cons (int type)
13076 segment_info_type *si = seg_info (now_seg);
13077 struct insn_label_list *l = si->label_list;
13080 label = l != NULL ? l->label : NULL;
13082 mips_emit_delays ();
13087 mips_align (3, 0, label);
13089 mips_align (2, 0, label);
13093 mips_clear_insn_labels ();
13096 /* Handle .globl. We need to override it because on Irix 5 you are
13099 where foo is an undefined symbol, to mean that foo should be
13100 considered to be the address of a function. */
13103 s_mips_globl (int x ATTRIBUTE_UNUSED)
13112 name = input_line_pointer;
13113 c = get_symbol_end ();
13114 symbolP = symbol_find_or_make (name);
13115 S_SET_EXTERNAL (symbolP);
13117 *input_line_pointer = c;
13118 SKIP_WHITESPACE ();
13120 /* On Irix 5, every global symbol that is not explicitly labelled as
13121 being a function is apparently labelled as being an object. */
13124 if (!is_end_of_line[(unsigned char) *input_line_pointer]
13125 && (*input_line_pointer != ','))
13130 secname = input_line_pointer;
13131 c = get_symbol_end ();
13132 sec = bfd_get_section_by_name (stdoutput, secname);
13134 as_bad (_("%s: no such section"), secname);
13135 *input_line_pointer = c;
13137 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
13138 flag = BSF_FUNCTION;
13141 symbol_get_bfdsym (symbolP)->flags |= flag;
13143 c = *input_line_pointer;
13146 input_line_pointer++;
13147 SKIP_WHITESPACE ();
13148 if (is_end_of_line[(unsigned char) *input_line_pointer])
13154 demand_empty_rest_of_line ();
13158 s_option (int x ATTRIBUTE_UNUSED)
13163 opt = input_line_pointer;
13164 c = get_symbol_end ();
13168 /* FIXME: What does this mean? */
13170 else if (strncmp (opt, "pic", 3) == 0)
13174 i = atoi (opt + 3);
13179 mips_pic = SVR4_PIC;
13180 mips_abicalls = TRUE;
13183 as_bad (_(".option pic%d not supported"), i);
13185 if (mips_pic == SVR4_PIC)
13187 if (g_switch_seen && g_switch_value != 0)
13188 as_warn (_("-G may not be used with SVR4 PIC code"));
13189 g_switch_value = 0;
13190 bfd_set_gp_size (stdoutput, 0);
13194 as_warn (_("Unrecognized option \"%s\""), opt);
13196 *input_line_pointer = c;
13197 demand_empty_rest_of_line ();
13200 /* This structure is used to hold a stack of .set values. */
13202 struct mips_option_stack
13204 struct mips_option_stack *next;
13205 struct mips_set_options options;
13208 static struct mips_option_stack *mips_opts_stack;
13210 /* Handle the .set pseudo-op. */
13213 s_mipsset (int x ATTRIBUTE_UNUSED)
13215 char *name = input_line_pointer, ch;
13217 while (!is_end_of_line[(unsigned char) *input_line_pointer])
13218 ++input_line_pointer;
13219 ch = *input_line_pointer;
13220 *input_line_pointer = '\0';
13222 if (strcmp (name, "reorder") == 0)
13224 if (mips_opts.noreorder)
13227 else if (strcmp (name, "noreorder") == 0)
13229 if (!mips_opts.noreorder)
13230 start_noreorder ();
13232 else if (strncmp (name, "at=", 3) == 0)
13234 char *s = name + 3;
13236 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
13237 as_bad (_("Unrecognized register name `%s'"), s);
13239 else if (strcmp (name, "at") == 0)
13241 mips_opts.at = ATREG;
13243 else if (strcmp (name, "noat") == 0)
13245 mips_opts.at = ZERO;
13247 else if (strcmp (name, "macro") == 0)
13249 mips_opts.warn_about_macros = 0;
13251 else if (strcmp (name, "nomacro") == 0)
13253 if (mips_opts.noreorder == 0)
13254 as_bad (_("`noreorder' must be set before `nomacro'"));
13255 mips_opts.warn_about_macros = 1;
13257 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
13259 mips_opts.nomove = 0;
13261 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
13263 mips_opts.nomove = 1;
13265 else if (strcmp (name, "bopt") == 0)
13267 mips_opts.nobopt = 0;
13269 else if (strcmp (name, "nobopt") == 0)
13271 mips_opts.nobopt = 1;
13273 else if (strcmp (name, "gp=default") == 0)
13274 mips_opts.gp32 = file_mips_gp32;
13275 else if (strcmp (name, "gp=32") == 0)
13276 mips_opts.gp32 = 1;
13277 else if (strcmp (name, "gp=64") == 0)
13279 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
13280 as_warn (_("%s isa does not support 64-bit registers"),
13281 mips_cpu_info_from_isa (mips_opts.isa)->name);
13282 mips_opts.gp32 = 0;
13284 else if (strcmp (name, "fp=default") == 0)
13285 mips_opts.fp32 = file_mips_fp32;
13286 else if (strcmp (name, "fp=32") == 0)
13287 mips_opts.fp32 = 1;
13288 else if (strcmp (name, "fp=64") == 0)
13290 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
13291 as_warn (_("%s isa does not support 64-bit floating point registers"),
13292 mips_cpu_info_from_isa (mips_opts.isa)->name);
13293 mips_opts.fp32 = 0;
13295 else if (strcmp (name, "softfloat") == 0)
13296 mips_opts.soft_float = 1;
13297 else if (strcmp (name, "hardfloat") == 0)
13298 mips_opts.soft_float = 0;
13299 else if (strcmp (name, "singlefloat") == 0)
13300 mips_opts.single_float = 1;
13301 else if (strcmp (name, "doublefloat") == 0)
13302 mips_opts.single_float = 0;
13303 else if (strcmp (name, "mips16") == 0
13304 || strcmp (name, "MIPS-16") == 0)
13305 mips_opts.mips16 = 1;
13306 else if (strcmp (name, "nomips16") == 0
13307 || strcmp (name, "noMIPS-16") == 0)
13308 mips_opts.mips16 = 0;
13309 else if (strcmp (name, "smartmips") == 0)
13311 if (!ISA_SUPPORTS_SMARTMIPS)
13312 as_warn (_("%s ISA does not support SmartMIPS ASE"),
13313 mips_cpu_info_from_isa (mips_opts.isa)->name);
13314 mips_opts.ase_smartmips = 1;
13316 else if (strcmp (name, "nosmartmips") == 0)
13317 mips_opts.ase_smartmips = 0;
13318 else if (strcmp (name, "mips3d") == 0)
13319 mips_opts.ase_mips3d = 1;
13320 else if (strcmp (name, "nomips3d") == 0)
13321 mips_opts.ase_mips3d = 0;
13322 else if (strcmp (name, "mdmx") == 0)
13323 mips_opts.ase_mdmx = 1;
13324 else if (strcmp (name, "nomdmx") == 0)
13325 mips_opts.ase_mdmx = 0;
13326 else if (strcmp (name, "dsp") == 0)
13328 if (!ISA_SUPPORTS_DSP_ASE)
13329 as_warn (_("%s ISA does not support DSP ASE"),
13330 mips_cpu_info_from_isa (mips_opts.isa)->name);
13331 mips_opts.ase_dsp = 1;
13332 mips_opts.ase_dspr2 = 0;
13334 else if (strcmp (name, "nodsp") == 0)
13336 mips_opts.ase_dsp = 0;
13337 mips_opts.ase_dspr2 = 0;
13339 else if (strcmp (name, "dspr2") == 0)
13341 if (!ISA_SUPPORTS_DSPR2_ASE)
13342 as_warn (_("%s ISA does not support DSP R2 ASE"),
13343 mips_cpu_info_from_isa (mips_opts.isa)->name);
13344 mips_opts.ase_dspr2 = 1;
13345 mips_opts.ase_dsp = 1;
13347 else if (strcmp (name, "nodspr2") == 0)
13349 mips_opts.ase_dspr2 = 0;
13350 mips_opts.ase_dsp = 0;
13352 else if (strcmp (name, "mt") == 0)
13354 if (!ISA_SUPPORTS_MT_ASE)
13355 as_warn (_("%s ISA does not support MT ASE"),
13356 mips_cpu_info_from_isa (mips_opts.isa)->name);
13357 mips_opts.ase_mt = 1;
13359 else if (strcmp (name, "nomt") == 0)
13360 mips_opts.ase_mt = 0;
13361 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
13365 /* Permit the user to change the ISA and architecture on the fly.
13366 Needless to say, misuse can cause serious problems. */
13367 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
13370 mips_opts.isa = file_mips_isa;
13371 mips_opts.arch = file_mips_arch;
13373 else if (strncmp (name, "arch=", 5) == 0)
13375 const struct mips_cpu_info *p;
13377 p = mips_parse_cpu("internal use", name + 5);
13379 as_bad (_("unknown architecture %s"), name + 5);
13382 mips_opts.arch = p->cpu;
13383 mips_opts.isa = p->isa;
13386 else if (strncmp (name, "mips", 4) == 0)
13388 const struct mips_cpu_info *p;
13390 p = mips_parse_cpu("internal use", name);
13392 as_bad (_("unknown ISA level %s"), name + 4);
13395 mips_opts.arch = p->cpu;
13396 mips_opts.isa = p->isa;
13400 as_bad (_("unknown ISA or architecture %s"), name);
13402 switch (mips_opts.isa)
13410 mips_opts.gp32 = 1;
13411 mips_opts.fp32 = 1;
13418 mips_opts.gp32 = 0;
13419 mips_opts.fp32 = 0;
13422 as_bad (_("unknown ISA level %s"), name + 4);
13427 mips_opts.gp32 = file_mips_gp32;
13428 mips_opts.fp32 = file_mips_fp32;
13431 else if (strcmp (name, "autoextend") == 0)
13432 mips_opts.noautoextend = 0;
13433 else if (strcmp (name, "noautoextend") == 0)
13434 mips_opts.noautoextend = 1;
13435 else if (strcmp (name, "push") == 0)
13437 struct mips_option_stack *s;
13439 s = (struct mips_option_stack *) xmalloc (sizeof *s);
13440 s->next = mips_opts_stack;
13441 s->options = mips_opts;
13442 mips_opts_stack = s;
13444 else if (strcmp (name, "pop") == 0)
13446 struct mips_option_stack *s;
13448 s = mips_opts_stack;
13450 as_bad (_(".set pop with no .set push"));
13453 /* If we're changing the reorder mode we need to handle
13454 delay slots correctly. */
13455 if (s->options.noreorder && ! mips_opts.noreorder)
13456 start_noreorder ();
13457 else if (! s->options.noreorder && mips_opts.noreorder)
13460 mips_opts = s->options;
13461 mips_opts_stack = s->next;
13465 else if (strcmp (name, "sym32") == 0)
13466 mips_opts.sym32 = TRUE;
13467 else if (strcmp (name, "nosym32") == 0)
13468 mips_opts.sym32 = FALSE;
13469 else if (strchr (name, ','))
13471 /* Generic ".set" directive; use the generic handler. */
13472 *input_line_pointer = ch;
13473 input_line_pointer = name;
13479 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
13481 *input_line_pointer = ch;
13482 demand_empty_rest_of_line ();
13485 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
13486 .option pic2. It means to generate SVR4 PIC calls. */
13489 s_abicalls (int ignore ATTRIBUTE_UNUSED)
13491 mips_pic = SVR4_PIC;
13492 mips_abicalls = TRUE;
13494 if (g_switch_seen && g_switch_value != 0)
13495 as_warn (_("-G may not be used with SVR4 PIC code"));
13496 g_switch_value = 0;
13498 bfd_set_gp_size (stdoutput, 0);
13499 demand_empty_rest_of_line ();
13502 /* Handle the .cpload pseudo-op. This is used when generating SVR4
13503 PIC code. It sets the $gp register for the function based on the
13504 function address, which is in the register named in the argument.
13505 This uses a relocation against _gp_disp, which is handled specially
13506 by the linker. The result is:
13507 lui $gp,%hi(_gp_disp)
13508 addiu $gp,$gp,%lo(_gp_disp)
13509 addu $gp,$gp,.cpload argument
13510 The .cpload argument is normally $25 == $t9.
13512 The -mno-shared option changes this to:
13513 lui $gp,%hi(__gnu_local_gp)
13514 addiu $gp,$gp,%lo(__gnu_local_gp)
13515 and the argument is ignored. This saves an instruction, but the
13516 resulting code is not position independent; it uses an absolute
13517 address for __gnu_local_gp. Thus code assembled with -mno-shared
13518 can go into an ordinary executable, but not into a shared library. */
13521 s_cpload (int ignore ATTRIBUTE_UNUSED)
13527 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13528 .cpload is ignored. */
13529 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
13535 /* .cpload should be in a .set noreorder section. */
13536 if (mips_opts.noreorder == 0)
13537 as_warn (_(".cpload not in noreorder section"));
13539 reg = tc_get_register (0);
13541 /* If we need to produce a 64-bit address, we are better off using
13542 the default instruction sequence. */
13543 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
13545 ex.X_op = O_symbol;
13546 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
13548 ex.X_op_symbol = NULL;
13549 ex.X_add_number = 0;
13551 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13552 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
13555 macro_build_lui (&ex, mips_gp_register);
13556 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
13557 mips_gp_register, BFD_RELOC_LO16);
13559 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
13560 mips_gp_register, reg);
13563 demand_empty_rest_of_line ();
13566 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
13567 .cpsetup $reg1, offset|$reg2, label
13569 If offset is given, this results in:
13570 sd $gp, offset($sp)
13571 lui $gp, %hi(%neg(%gp_rel(label)))
13572 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13573 daddu $gp, $gp, $reg1
13575 If $reg2 is given, this results in:
13576 daddu $reg2, $gp, $0
13577 lui $gp, %hi(%neg(%gp_rel(label)))
13578 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13579 daddu $gp, $gp, $reg1
13580 $reg1 is normally $25 == $t9.
13582 The -mno-shared option replaces the last three instructions with
13584 addiu $gp,$gp,%lo(_gp) */
13587 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
13589 expressionS ex_off;
13590 expressionS ex_sym;
13593 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
13594 We also need NewABI support. */
13595 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13601 reg1 = tc_get_register (0);
13602 SKIP_WHITESPACE ();
13603 if (*input_line_pointer != ',')
13605 as_bad (_("missing argument separator ',' for .cpsetup"));
13609 ++input_line_pointer;
13610 SKIP_WHITESPACE ();
13611 if (*input_line_pointer == '$')
13613 mips_cpreturn_register = tc_get_register (0);
13614 mips_cpreturn_offset = -1;
13618 mips_cpreturn_offset = get_absolute_expression ();
13619 mips_cpreturn_register = -1;
13621 SKIP_WHITESPACE ();
13622 if (*input_line_pointer != ',')
13624 as_bad (_("missing argument separator ',' for .cpsetup"));
13628 ++input_line_pointer;
13629 SKIP_WHITESPACE ();
13630 expression (&ex_sym);
13633 if (mips_cpreturn_register == -1)
13635 ex_off.X_op = O_constant;
13636 ex_off.X_add_symbol = NULL;
13637 ex_off.X_op_symbol = NULL;
13638 ex_off.X_add_number = mips_cpreturn_offset;
13640 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
13641 BFD_RELOC_LO16, SP);
13644 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
13645 mips_gp_register, 0);
13647 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
13649 macro_build (&ex_sym, "lui", "t,u", mips_gp_register,
13650 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
13653 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
13654 mips_gp_register, -1, BFD_RELOC_GPREL16,
13655 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
13657 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
13658 mips_gp_register, reg1);
13664 ex.X_op = O_symbol;
13665 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
13666 ex.X_op_symbol = NULL;
13667 ex.X_add_number = 0;
13669 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13670 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
13672 macro_build_lui (&ex, mips_gp_register);
13673 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
13674 mips_gp_register, BFD_RELOC_LO16);
13679 demand_empty_rest_of_line ();
13683 s_cplocal (int ignore ATTRIBUTE_UNUSED)
13685 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
13686 .cplocal is ignored. */
13687 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13693 mips_gp_register = tc_get_register (0);
13694 demand_empty_rest_of_line ();
13697 /* Handle the .cprestore pseudo-op. This stores $gp into a given
13698 offset from $sp. The offset is remembered, and after making a PIC
13699 call $gp is restored from that location. */
13702 s_cprestore (int ignore ATTRIBUTE_UNUSED)
13706 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13707 .cprestore is ignored. */
13708 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
13714 mips_cprestore_offset = get_absolute_expression ();
13715 mips_cprestore_valid = 1;
13717 ex.X_op = O_constant;
13718 ex.X_add_symbol = NULL;
13719 ex.X_op_symbol = NULL;
13720 ex.X_add_number = mips_cprestore_offset;
13723 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
13724 SP, HAVE_64BIT_ADDRESSES);
13727 demand_empty_rest_of_line ();
13730 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
13731 was given in the preceding .cpsetup, it results in:
13732 ld $gp, offset($sp)
13734 If a register $reg2 was given there, it results in:
13735 daddu $gp, $reg2, $0 */
13738 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
13742 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
13743 We also need NewABI support. */
13744 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13751 if (mips_cpreturn_register == -1)
13753 ex.X_op = O_constant;
13754 ex.X_add_symbol = NULL;
13755 ex.X_op_symbol = NULL;
13756 ex.X_add_number = mips_cpreturn_offset;
13758 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
13761 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
13762 mips_cpreturn_register, 0);
13765 demand_empty_rest_of_line ();
13768 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
13769 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
13770 use in DWARF debug information. */
13773 s_dtprel_internal (size_t bytes)
13780 if (ex.X_op != O_symbol)
13782 as_bad (_("Unsupported use of %s"), (bytes == 8
13785 ignore_rest_of_line ();
13788 p = frag_more (bytes);
13789 md_number_to_chars (p, 0, bytes);
13790 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
13792 ? BFD_RELOC_MIPS_TLS_DTPREL64
13793 : BFD_RELOC_MIPS_TLS_DTPREL32));
13795 demand_empty_rest_of_line ();
13798 /* Handle .dtprelword. */
13801 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
13803 s_dtprel_internal (4);
13806 /* Handle .dtpreldword. */
13809 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
13811 s_dtprel_internal (8);
13814 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
13815 code. It sets the offset to use in gp_rel relocations. */
13818 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
13820 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
13821 We also need NewABI support. */
13822 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13828 mips_gprel_offset = get_absolute_expression ();
13830 demand_empty_rest_of_line ();
13833 /* Handle the .gpword pseudo-op. This is used when generating PIC
13834 code. It generates a 32 bit GP relative reloc. */
13837 s_gpword (int ignore ATTRIBUTE_UNUSED)
13839 segment_info_type *si;
13840 struct insn_label_list *l;
13845 /* When not generating PIC code, this is treated as .word. */
13846 if (mips_pic != SVR4_PIC)
13852 si = seg_info (now_seg);
13853 l = si->label_list;
13854 label = l != NULL ? l->label : NULL;
13855 mips_emit_delays ();
13857 mips_align (2, 0, label);
13860 mips_clear_insn_labels ();
13862 if (ex.X_op != O_symbol || ex.X_add_number != 0)
13864 as_bad (_("Unsupported use of .gpword"));
13865 ignore_rest_of_line ();
13869 md_number_to_chars (p, 0, 4);
13870 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
13871 BFD_RELOC_GPREL32);
13873 demand_empty_rest_of_line ();
13877 s_gpdword (int ignore ATTRIBUTE_UNUSED)
13879 segment_info_type *si;
13880 struct insn_label_list *l;
13885 /* When not generating PIC code, this is treated as .dword. */
13886 if (mips_pic != SVR4_PIC)
13892 si = seg_info (now_seg);
13893 l = si->label_list;
13894 label = l != NULL ? l->label : NULL;
13895 mips_emit_delays ();
13897 mips_align (3, 0, label);
13900 mips_clear_insn_labels ();
13902 if (ex.X_op != O_symbol || ex.X_add_number != 0)
13904 as_bad (_("Unsupported use of .gpdword"));
13905 ignore_rest_of_line ();
13909 md_number_to_chars (p, 0, 8);
13910 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
13911 BFD_RELOC_GPREL32)->fx_tcbit = 1;
13913 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
13914 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
13915 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
13917 demand_empty_rest_of_line ();
13920 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
13921 tables in SVR4 PIC code. */
13924 s_cpadd (int ignore ATTRIBUTE_UNUSED)
13928 /* This is ignored when not generating SVR4 PIC code. */
13929 if (mips_pic != SVR4_PIC)
13935 /* Add $gp to the register named as an argument. */
13937 reg = tc_get_register (0);
13938 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
13941 demand_empty_rest_of_line ();
13944 /* Handle the .insn pseudo-op. This marks instruction labels in
13945 mips16 mode. This permits the linker to handle them specially,
13946 such as generating jalx instructions when needed. We also make
13947 them odd for the duration of the assembly, in order to generate the
13948 right sort of code. We will make them even in the adjust_symtab
13949 routine, while leaving them marked. This is convenient for the
13950 debugger and the disassembler. The linker knows to make them odd
13954 s_insn (int ignore ATTRIBUTE_UNUSED)
13956 mips16_mark_labels ();
13958 demand_empty_rest_of_line ();
13961 /* Handle a .stabn directive. We need these in order to mark a label
13962 as being a mips16 text label correctly. Sometimes the compiler
13963 will emit a label, followed by a .stabn, and then switch sections.
13964 If the label and .stabn are in mips16 mode, then the label is
13965 really a mips16 text label. */
13968 s_mips_stab (int type)
13971 mips16_mark_labels ();
13976 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
13979 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
13986 name = input_line_pointer;
13987 c = get_symbol_end ();
13988 symbolP = symbol_find_or_make (name);
13989 S_SET_WEAK (symbolP);
13990 *input_line_pointer = c;
13992 SKIP_WHITESPACE ();
13994 if (! is_end_of_line[(unsigned char) *input_line_pointer])
13996 if (S_IS_DEFINED (symbolP))
13998 as_bad (_("ignoring attempt to redefine symbol %s"),
13999 S_GET_NAME (symbolP));
14000 ignore_rest_of_line ();
14004 if (*input_line_pointer == ',')
14006 ++input_line_pointer;
14007 SKIP_WHITESPACE ();
14011 if (exp.X_op != O_symbol)
14013 as_bad (_("bad .weakext directive"));
14014 ignore_rest_of_line ();
14017 symbol_set_value_expression (symbolP, &exp);
14020 demand_empty_rest_of_line ();
14023 /* Parse a register string into a number. Called from the ECOFF code
14024 to parse .frame. The argument is non-zero if this is the frame
14025 register, so that we can record it in mips_frame_reg. */
14028 tc_get_register (int frame)
14032 SKIP_WHITESPACE ();
14033 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
14037 mips_frame_reg = reg != 0 ? reg : SP;
14038 mips_frame_reg_valid = 1;
14039 mips_cprestore_valid = 0;
14045 md_section_align (asection *seg, valueT addr)
14047 int align = bfd_get_section_alignment (stdoutput, seg);
14051 /* We don't need to align ELF sections to the full alignment.
14052 However, Irix 5 may prefer that we align them at least to a 16
14053 byte boundary. We don't bother to align the sections if we
14054 are targeted for an embedded system. */
14055 if (strncmp (TARGET_OS, "elf", 3) == 0)
14061 return ((addr + (1 << align) - 1) & (-1 << align));
14064 /* Utility routine, called from above as well. If called while the
14065 input file is still being read, it's only an approximation. (For
14066 example, a symbol may later become defined which appeared to be
14067 undefined earlier.) */
14070 nopic_need_relax (symbolS *sym, int before_relaxing)
14075 if (g_switch_value > 0)
14077 const char *symname;
14080 /* Find out whether this symbol can be referenced off the $gp
14081 register. It can be if it is smaller than the -G size or if
14082 it is in the .sdata or .sbss section. Certain symbols can
14083 not be referenced off the $gp, although it appears as though
14085 symname = S_GET_NAME (sym);
14086 if (symname != (const char *) NULL
14087 && (strcmp (symname, "eprol") == 0
14088 || strcmp (symname, "etext") == 0
14089 || strcmp (symname, "_gp") == 0
14090 || strcmp (symname, "edata") == 0
14091 || strcmp (symname, "_fbss") == 0
14092 || strcmp (symname, "_fdata") == 0
14093 || strcmp (symname, "_ftext") == 0
14094 || strcmp (symname, "end") == 0
14095 || strcmp (symname, "_gp_disp") == 0))
14097 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
14099 #ifndef NO_ECOFF_DEBUGGING
14100 || (symbol_get_obj (sym)->ecoff_extern_size != 0
14101 && (symbol_get_obj (sym)->ecoff_extern_size
14102 <= g_switch_value))
14104 /* We must defer this decision until after the whole
14105 file has been read, since there might be a .extern
14106 after the first use of this symbol. */
14107 || (before_relaxing
14108 #ifndef NO_ECOFF_DEBUGGING
14109 && symbol_get_obj (sym)->ecoff_extern_size == 0
14111 && S_GET_VALUE (sym) == 0)
14112 || (S_GET_VALUE (sym) != 0
14113 && S_GET_VALUE (sym) <= g_switch_value)))
14117 const char *segname;
14119 segname = segment_name (S_GET_SEGMENT (sym));
14120 gas_assert (strcmp (segname, ".lit8") != 0
14121 && strcmp (segname, ".lit4") != 0);
14122 change = (strcmp (segname, ".sdata") != 0
14123 && strcmp (segname, ".sbss") != 0
14124 && strncmp (segname, ".sdata.", 7) != 0
14125 && strncmp (segname, ".sbss.", 6) != 0
14126 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
14127 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
14132 /* We are not optimizing for the $gp register. */
14137 /* Return true if the given symbol should be considered local for SVR4 PIC. */
14140 pic_need_relax (symbolS *sym, asection *segtype)
14144 /* Handle the case of a symbol equated to another symbol. */
14145 while (symbol_equated_reloc_p (sym))
14149 /* It's possible to get a loop here in a badly written program. */
14150 n = symbol_get_value_expression (sym)->X_add_symbol;
14156 if (symbol_section_p (sym))
14159 symsec = S_GET_SEGMENT (sym);
14161 /* This must duplicate the test in adjust_reloc_syms. */
14162 return (symsec != &bfd_und_section
14163 && symsec != &bfd_abs_section
14164 && !bfd_is_com_section (symsec)
14165 && !s_is_linkonce (sym, segtype)
14167 /* A global or weak symbol is treated as external. */
14168 && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
14174 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
14175 extended opcode. SEC is the section the frag is in. */
14178 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
14181 const struct mips16_immed_operand *op;
14183 int mintiny, maxtiny;
14187 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
14189 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
14192 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
14193 op = mips16_immed_operands;
14194 while (op->type != type)
14197 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
14202 if (type == '<' || type == '>' || type == '[' || type == ']')
14205 maxtiny = 1 << op->nbits;
14210 maxtiny = (1 << op->nbits) - 1;
14215 mintiny = - (1 << (op->nbits - 1));
14216 maxtiny = (1 << (op->nbits - 1)) - 1;
14219 sym_frag = symbol_get_frag (fragp->fr_symbol);
14220 val = S_GET_VALUE (fragp->fr_symbol);
14221 symsec = S_GET_SEGMENT (fragp->fr_symbol);
14227 /* We won't have the section when we are called from
14228 mips_relax_frag. However, we will always have been called
14229 from md_estimate_size_before_relax first. If this is a
14230 branch to a different section, we mark it as such. If SEC is
14231 NULL, and the frag is not marked, then it must be a branch to
14232 the same section. */
14235 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
14240 /* Must have been called from md_estimate_size_before_relax. */
14243 fragp->fr_subtype =
14244 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14246 /* FIXME: We should support this, and let the linker
14247 catch branches and loads that are out of range. */
14248 as_bad_where (fragp->fr_file, fragp->fr_line,
14249 _("unsupported PC relative reference to different section"));
14253 if (fragp != sym_frag && sym_frag->fr_address == 0)
14254 /* Assume non-extended on the first relaxation pass.
14255 The address we have calculated will be bogus if this is
14256 a forward branch to another frag, as the forward frag
14257 will have fr_address == 0. */
14261 /* In this case, we know for sure that the symbol fragment is in
14262 the same section. If the relax_marker of the symbol fragment
14263 differs from the relax_marker of this fragment, we have not
14264 yet adjusted the symbol fragment fr_address. We want to add
14265 in STRETCH in order to get a better estimate of the address.
14266 This particularly matters because of the shift bits. */
14268 && sym_frag->relax_marker != fragp->relax_marker)
14272 /* Adjust stretch for any alignment frag. Note that if have
14273 been expanding the earlier code, the symbol may be
14274 defined in what appears to be an earlier frag. FIXME:
14275 This doesn't handle the fr_subtype field, which specifies
14276 a maximum number of bytes to skip when doing an
14278 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
14280 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
14283 stretch = - ((- stretch)
14284 & ~ ((1 << (int) f->fr_offset) - 1));
14286 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
14295 addr = fragp->fr_address + fragp->fr_fix;
14297 /* The base address rules are complicated. The base address of
14298 a branch is the following instruction. The base address of a
14299 PC relative load or add is the instruction itself, but if it
14300 is in a delay slot (in which case it can not be extended) use
14301 the address of the instruction whose delay slot it is in. */
14302 if (type == 'p' || type == 'q')
14306 /* If we are currently assuming that this frag should be
14307 extended, then, the current address is two bytes
14309 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14312 /* Ignore the low bit in the target, since it will be set
14313 for a text label. */
14314 if ((val & 1) != 0)
14317 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
14319 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
14322 val -= addr & ~ ((1 << op->shift) - 1);
14324 /* Branch offsets have an implicit 0 in the lowest bit. */
14325 if (type == 'p' || type == 'q')
14328 /* If any of the shifted bits are set, we must use an extended
14329 opcode. If the address depends on the size of this
14330 instruction, this can lead to a loop, so we arrange to always
14331 use an extended opcode. We only check this when we are in
14332 the main relaxation loop, when SEC is NULL. */
14333 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
14335 fragp->fr_subtype =
14336 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14340 /* If we are about to mark a frag as extended because the value
14341 is precisely maxtiny + 1, then there is a chance of an
14342 infinite loop as in the following code:
14347 In this case when the la is extended, foo is 0x3fc bytes
14348 away, so the la can be shrunk, but then foo is 0x400 away, so
14349 the la must be extended. To avoid this loop, we mark the
14350 frag as extended if it was small, and is about to become
14351 extended with a value of maxtiny + 1. */
14352 if (val == ((maxtiny + 1) << op->shift)
14353 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
14356 fragp->fr_subtype =
14357 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14361 else if (symsec != absolute_section && sec != NULL)
14362 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
14364 if ((val & ((1 << op->shift) - 1)) != 0
14365 || val < (mintiny << op->shift)
14366 || val > (maxtiny << op->shift))
14372 /* Compute the length of a branch sequence, and adjust the
14373 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
14374 worst-case length is computed, with UPDATE being used to indicate
14375 whether an unconditional (-1), branch-likely (+1) or regular (0)
14376 branch is to be computed. */
14378 relaxed_branch_length (fragS *fragp, asection *sec, int update)
14380 bfd_boolean toofar;
14384 && S_IS_DEFINED (fragp->fr_symbol)
14385 && sec == S_GET_SEGMENT (fragp->fr_symbol))
14390 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
14392 addr = fragp->fr_address + fragp->fr_fix + 4;
14396 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
14399 /* If the symbol is not defined or it's in a different segment,
14400 assume the user knows what's going on and emit a short
14406 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
14408 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
14409 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
14410 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
14411 RELAX_BRANCH_LINK (fragp->fr_subtype),
14417 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
14420 if (mips_pic != NO_PIC)
14422 /* Additional space for PIC loading of target address. */
14424 if (mips_opts.isa == ISA_MIPS1)
14425 /* Additional space for $at-stabilizing nop. */
14429 /* If branch is conditional. */
14430 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
14437 /* Estimate the size of a frag before relaxing. Unless this is the
14438 mips16, we are not really relaxing here, and the final size is
14439 encoded in the subtype information. For the mips16, we have to
14440 decide whether we are using an extended opcode or not. */
14443 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
14447 if (RELAX_BRANCH_P (fragp->fr_subtype))
14450 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
14452 return fragp->fr_var;
14455 if (RELAX_MIPS16_P (fragp->fr_subtype))
14456 /* We don't want to modify the EXTENDED bit here; it might get us
14457 into infinite loops. We change it only in mips_relax_frag(). */
14458 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
14460 if (mips_pic == NO_PIC)
14461 change = nopic_need_relax (fragp->fr_symbol, 0);
14462 else if (mips_pic == SVR4_PIC)
14463 change = pic_need_relax (fragp->fr_symbol, segtype);
14464 else if (mips_pic == VXWORKS_PIC)
14465 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
14472 fragp->fr_subtype |= RELAX_USE_SECOND;
14473 return -RELAX_FIRST (fragp->fr_subtype);
14476 return -RELAX_SECOND (fragp->fr_subtype);
14479 /* This is called to see whether a reloc against a defined symbol
14480 should be converted into a reloc against a section. */
14483 mips_fix_adjustable (fixS *fixp)
14485 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
14486 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
14489 if (fixp->fx_addsy == NULL)
14492 /* If symbol SYM is in a mergeable section, relocations of the form
14493 SYM + 0 can usually be made section-relative. The mergeable data
14494 is then identified by the section offset rather than by the symbol.
14496 However, if we're generating REL LO16 relocations, the offset is split
14497 between the LO16 and parterning high part relocation. The linker will
14498 need to recalculate the complete offset in order to correctly identify
14501 The linker has traditionally not looked for the parterning high part
14502 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
14503 placed anywhere. Rather than break backwards compatibility by changing
14504 this, it seems better not to force the issue, and instead keep the
14505 original symbol. This will work with either linker behavior. */
14506 if ((lo16_reloc_p (fixp->fx_r_type)
14507 || reloc_needs_lo_p (fixp->fx_r_type))
14508 && HAVE_IN_PLACE_ADDENDS
14509 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
14512 /* There is no place to store an in-place offset for JALR relocations.
14513 Likewise an in-range offset of PC-relative relocations may overflow
14514 the in-place relocatable field if recalculated against the start
14515 address of the symbol's containing section. */
14516 if (HAVE_IN_PLACE_ADDENDS
14517 && (fixp->fx_pcrel || fixp->fx_r_type == BFD_RELOC_MIPS_JALR))
14521 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
14522 to a floating-point stub. The same is true for non-R_MIPS16_26
14523 relocations against MIPS16 functions; in this case, the stub becomes
14524 the function's canonical address.
14526 Floating-point stubs are stored in unique .mips16.call.* or
14527 .mips16.fn.* sections. If a stub T for function F is in section S,
14528 the first relocation in section S must be against F; this is how the
14529 linker determines the target function. All relocations that might
14530 resolve to T must also be against F. We therefore have the following
14531 restrictions, which are given in an intentionally-redundant way:
14533 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
14536 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
14537 if that stub might be used.
14539 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
14542 4. We cannot reduce a stub's relocations against MIPS16 symbols if
14543 that stub might be used.
14545 There is a further restriction:
14547 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols
14548 on targets with in-place addends; the relocation field cannot
14549 encode the low bit.
14551 For simplicity, we deal with (3)-(5) by not reducing _any_ relocation
14552 against a MIPS16 symbol.
14554 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
14555 relocation against some symbol R, no relocation against R may be
14556 reduced. (Note that this deals with (2) as well as (1) because
14557 relocations against global symbols will never be reduced on ELF
14558 targets.) This approach is a little simpler than trying to detect
14559 stub sections, and gives the "all or nothing" per-symbol consistency
14560 that we have for MIPS16 symbols. */
14562 && fixp->fx_subsy == NULL
14563 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
14564 || *symbol_get_tc (fixp->fx_addsy)))
14571 /* Translate internal representation of relocation info to BFD target
14575 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
14577 static arelent *retval[4];
14579 bfd_reloc_code_real_type code;
14581 memset (retval, 0, sizeof(retval));
14582 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
14583 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
14584 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
14585 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
14587 if (fixp->fx_pcrel)
14589 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2);
14591 /* At this point, fx_addnumber is "symbol offset - pcrel address".
14592 Relocations want only the symbol offset. */
14593 reloc->addend = fixp->fx_addnumber + reloc->address;
14596 /* A gruesome hack which is a result of the gruesome gas
14597 reloc handling. What's worse, for COFF (as opposed to
14598 ECOFF), we might need yet another copy of reloc->address.
14599 See bfd_install_relocation. */
14600 reloc->addend += reloc->address;
14604 reloc->addend = fixp->fx_addnumber;
14606 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
14607 entry to be used in the relocation's section offset. */
14608 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
14610 reloc->address = reloc->addend;
14614 code = fixp->fx_r_type;
14616 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
14617 if (reloc->howto == NULL)
14619 as_bad_where (fixp->fx_file, fixp->fx_line,
14620 _("Can not represent %s relocation in this object file format"),
14621 bfd_get_reloc_code_name (code));
14628 /* Relax a machine dependent frag. This returns the amount by which
14629 the current size of the frag should change. */
14632 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
14634 if (RELAX_BRANCH_P (fragp->fr_subtype))
14636 offsetT old_var = fragp->fr_var;
14638 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
14640 return fragp->fr_var - old_var;
14643 if (! RELAX_MIPS16_P (fragp->fr_subtype))
14646 if (mips16_extended_frag (fragp, NULL, stretch))
14648 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14650 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
14655 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14657 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
14664 /* Convert a machine dependent frag. */
14667 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
14669 if (RELAX_BRANCH_P (fragp->fr_subtype))
14672 unsigned long insn;
14676 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
14678 if (target_big_endian)
14679 insn = bfd_getb32 (buf);
14681 insn = bfd_getl32 (buf);
14683 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
14685 /* We generate a fixup instead of applying it right now
14686 because, if there are linker relaxations, we're going to
14687 need the relocations. */
14688 exp.X_op = O_symbol;
14689 exp.X_add_symbol = fragp->fr_symbol;
14690 exp.X_add_number = fragp->fr_offset;
14692 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14693 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2);
14694 fixp->fx_file = fragp->fr_file;
14695 fixp->fx_line = fragp->fr_line;
14697 md_number_to_chars ((char *) buf, insn, 4);
14704 as_warn_where (fragp->fr_file, fragp->fr_line,
14705 _("Relaxed out-of-range branch into a jump"));
14707 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
14710 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14712 /* Reverse the branch. */
14713 switch ((insn >> 28) & 0xf)
14716 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
14717 have the condition reversed by tweaking a single
14718 bit, and their opcodes all have 0x4???????. */
14719 gas_assert ((insn & 0xf1000000) == 0x41000000);
14720 insn ^= 0x00010000;
14724 /* bltz 0x04000000 bgez 0x04010000
14725 bltzal 0x04100000 bgezal 0x04110000 */
14726 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
14727 insn ^= 0x00010000;
14731 /* beq 0x10000000 bne 0x14000000
14732 blez 0x18000000 bgtz 0x1c000000 */
14733 insn ^= 0x04000000;
14741 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
14743 /* Clear the and-link bit. */
14744 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
14746 /* bltzal 0x04100000 bgezal 0x04110000
14747 bltzall 0x04120000 bgezall 0x04130000 */
14748 insn &= ~0x00100000;
14751 /* Branch over the branch (if the branch was likely) or the
14752 full jump (not likely case). Compute the offset from the
14753 current instruction to branch to. */
14754 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14758 /* How many bytes in instructions we've already emitted? */
14759 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
14760 /* How many bytes in instructions from here to the end? */
14761 i = fragp->fr_var - i;
14763 /* Convert to instruction count. */
14765 /* Branch counts from the next instruction. */
14768 /* Branch over the jump. */
14769 md_number_to_chars ((char *) buf, insn, 4);
14773 md_number_to_chars ((char *) buf, 0, 4);
14776 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14778 /* beql $0, $0, 2f */
14780 /* Compute the PC offset from the current instruction to
14781 the end of the variable frag. */
14782 /* How many bytes in instructions we've already emitted? */
14783 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
14784 /* How many bytes in instructions from here to the end? */
14785 i = fragp->fr_var - i;
14786 /* Convert to instruction count. */
14788 /* Don't decrement i, because we want to branch over the
14792 md_number_to_chars ((char *) buf, insn, 4);
14795 md_number_to_chars ((char *) buf, 0, 4);
14800 if (mips_pic == NO_PIC)
14803 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
14804 ? 0x0c000000 : 0x08000000);
14805 exp.X_op = O_symbol;
14806 exp.X_add_symbol = fragp->fr_symbol;
14807 exp.X_add_number = fragp->fr_offset;
14809 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14810 4, &exp, FALSE, BFD_RELOC_MIPS_JMP);
14811 fixp->fx_file = fragp->fr_file;
14812 fixp->fx_line = fragp->fr_line;
14814 md_number_to_chars ((char *) buf, insn, 4);
14819 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
14821 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
14822 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
14823 insn |= at << OP_SH_RT;
14824 exp.X_op = O_symbol;
14825 exp.X_add_symbol = fragp->fr_symbol;
14826 exp.X_add_number = fragp->fr_offset;
14828 if (fragp->fr_offset)
14830 exp.X_add_symbol = make_expr_symbol (&exp);
14831 exp.X_add_number = 0;
14834 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14835 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16);
14836 fixp->fx_file = fragp->fr_file;
14837 fixp->fx_line = fragp->fr_line;
14839 md_number_to_chars ((char *) buf, insn, 4);
14842 if (mips_opts.isa == ISA_MIPS1)
14845 md_number_to_chars ((char *) buf, 0, 4);
14849 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
14850 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
14851 insn |= at << OP_SH_RS | at << OP_SH_RT;
14853 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14854 4, &exp, FALSE, BFD_RELOC_LO16);
14855 fixp->fx_file = fragp->fr_file;
14856 fixp->fx_line = fragp->fr_line;
14858 md_number_to_chars ((char *) buf, insn, 4);
14862 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
14866 insn |= at << OP_SH_RS;
14868 md_number_to_chars ((char *) buf, insn, 4);
14873 gas_assert (buf == (bfd_byte *)fragp->fr_literal
14874 + fragp->fr_fix + fragp->fr_var);
14876 fragp->fr_fix += fragp->fr_var;
14881 if (RELAX_MIPS16_P (fragp->fr_subtype))
14884 const struct mips16_immed_operand *op;
14885 bfd_boolean small, ext;
14888 unsigned long insn;
14889 bfd_boolean use_extend;
14890 unsigned short extend;
14892 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
14893 op = mips16_immed_operands;
14894 while (op->type != type)
14897 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14908 val = resolve_symbol_value (fragp->fr_symbol);
14913 addr = fragp->fr_address + fragp->fr_fix;
14915 /* The rules for the base address of a PC relative reloc are
14916 complicated; see mips16_extended_frag. */
14917 if (type == 'p' || type == 'q')
14922 /* Ignore the low bit in the target, since it will be
14923 set for a text label. */
14924 if ((val & 1) != 0)
14927 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
14929 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
14932 addr &= ~ (addressT) ((1 << op->shift) - 1);
14935 /* Make sure the section winds up with the alignment we have
14938 record_alignment (asec, op->shift);
14942 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
14943 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
14944 as_warn_where (fragp->fr_file, fragp->fr_line,
14945 _("extended instruction in delay slot"));
14947 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
14949 if (target_big_endian)
14950 insn = bfd_getb16 (buf);
14952 insn = bfd_getl16 (buf);
14954 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
14955 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
14956 small, ext, &insn, &use_extend, &extend);
14960 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
14961 fragp->fr_fix += 2;
14965 md_number_to_chars ((char *) buf, insn, 2);
14966 fragp->fr_fix += 2;
14974 first = RELAX_FIRST (fragp->fr_subtype);
14975 second = RELAX_SECOND (fragp->fr_subtype);
14976 fixp = (fixS *) fragp->fr_opcode;
14978 /* Possibly emit a warning if we've chosen the longer option. */
14979 if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0)
14980 == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0))
14982 const char *msg = macro_warning (fragp->fr_subtype);
14984 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
14987 /* Go through all the fixups for the first sequence. Disable them
14988 (by marking them as done) if we're going to use the second
14989 sequence instead. */
14991 && fixp->fx_frag == fragp
14992 && fixp->fx_where < fragp->fr_fix - second)
14994 if (fragp->fr_subtype & RELAX_USE_SECOND)
14996 fixp = fixp->fx_next;
14999 /* Go through the fixups for the second sequence. Disable them if
15000 we're going to use the first sequence, otherwise adjust their
15001 addresses to account for the relaxation. */
15002 while (fixp && fixp->fx_frag == fragp)
15004 if (fragp->fr_subtype & RELAX_USE_SECOND)
15005 fixp->fx_where -= first;
15008 fixp = fixp->fx_next;
15011 /* Now modify the frag contents. */
15012 if (fragp->fr_subtype & RELAX_USE_SECOND)
15016 start = fragp->fr_literal + fragp->fr_fix - first - second;
15017 memmove (start, start + first, second);
15018 fragp->fr_fix -= first;
15021 fragp->fr_fix -= second;
15027 /* This function is called after the relocs have been generated.
15028 We've been storing mips16 text labels as odd. Here we convert them
15029 back to even for the convenience of the debugger. */
15032 mips_frob_file_after_relocs (void)
15035 unsigned int count, i;
15040 syms = bfd_get_outsymbols (stdoutput);
15041 count = bfd_get_symcount (stdoutput);
15042 for (i = 0; i < count; i++, syms++)
15044 if (ELF_ST_IS_MIPS16 (elf_symbol (*syms)->internal_elf_sym.st_other)
15045 && ((*syms)->value & 1) != 0)
15047 (*syms)->value &= ~1;
15048 /* If the symbol has an odd size, it was probably computed
15049 incorrectly, so adjust that as well. */
15050 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
15051 ++elf_symbol (*syms)->internal_elf_sym.st_size;
15058 /* This function is called whenever a label is defined, including fake
15059 labels instantiated off the dot special symbol. It is used when
15060 handling branch delays; if a branch has a label, we assume we cannot
15061 move it. This also bumps the value of the symbol by 1 in compressed
15065 mips_record_label (symbolS *sym)
15067 segment_info_type *si = seg_info (now_seg);
15068 struct insn_label_list *l;
15070 if (free_insn_labels == NULL)
15071 l = (struct insn_label_list *) xmalloc (sizeof *l);
15074 l = free_insn_labels;
15075 free_insn_labels = l->next;
15079 l->next = si->label_list;
15080 si->label_list = l;
15083 /* This function is called as tc_frob_label() whenever a label is defined
15084 and adds a DWARF-2 record we only want for true labels. */
15087 mips_define_label (symbolS *sym)
15089 mips_record_label (sym);
15091 dwarf2_emit_label (sym);
15095 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15097 /* Some special processing for a MIPS ELF file. */
15100 mips_elf_final_processing (void)
15102 /* Write out the register information. */
15103 if (mips_abi != N64_ABI)
15107 s.ri_gprmask = mips_gprmask;
15108 s.ri_cprmask[0] = mips_cprmask[0];
15109 s.ri_cprmask[1] = mips_cprmask[1];
15110 s.ri_cprmask[2] = mips_cprmask[2];
15111 s.ri_cprmask[3] = mips_cprmask[3];
15112 /* The gp_value field is set by the MIPS ELF backend. */
15114 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
15115 ((Elf32_External_RegInfo *)
15116 mips_regmask_frag));
15120 Elf64_Internal_RegInfo s;
15122 s.ri_gprmask = mips_gprmask;
15124 s.ri_cprmask[0] = mips_cprmask[0];
15125 s.ri_cprmask[1] = mips_cprmask[1];
15126 s.ri_cprmask[2] = mips_cprmask[2];
15127 s.ri_cprmask[3] = mips_cprmask[3];
15128 /* The gp_value field is set by the MIPS ELF backend. */
15130 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
15131 ((Elf64_External_RegInfo *)
15132 mips_regmask_frag));
15135 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
15136 sort of BFD interface for this. */
15137 if (mips_any_noreorder)
15138 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
15139 if (mips_pic != NO_PIC)
15141 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
15142 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
15145 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
15147 /* Set MIPS ELF flags for ASEs. */
15148 /* We may need to define a new flag for DSP ASE, and set this flag when
15149 file_ase_dsp is true. */
15150 /* Same for DSP R2. */
15151 /* We may need to define a new flag for MT ASE, and set this flag when
15152 file_ase_mt is true. */
15153 if (file_ase_mips16)
15154 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
15155 #if 0 /* XXX FIXME */
15156 if (file_ase_mips3d)
15157 elf_elfheader (stdoutput)->e_flags |= ???;
15160 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
15162 /* Set the MIPS ELF ABI flags. */
15163 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
15164 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
15165 else if (mips_abi == O64_ABI)
15166 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
15167 else if (mips_abi == EABI_ABI)
15169 if (!file_mips_gp32)
15170 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
15172 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
15174 else if (mips_abi == N32_ABI)
15175 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
15177 /* Nothing to do for N64_ABI. */
15179 if (mips_32bitmode)
15180 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
15182 #if 0 /* XXX FIXME */
15183 /* 32 bit code with 64 bit FP registers. */
15184 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
15185 elf_elfheader (stdoutput)->e_flags |= ???;
15189 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
15191 typedef struct proc {
15193 symbolS *func_end_sym;
15194 unsigned long reg_mask;
15195 unsigned long reg_offset;
15196 unsigned long fpreg_mask;
15197 unsigned long fpreg_offset;
15198 unsigned long frame_offset;
15199 unsigned long frame_reg;
15200 unsigned long pc_reg;
15203 static procS cur_proc;
15204 static procS *cur_proc_ptr;
15205 static int numprocs;
15207 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal
15211 mips_nop_opcode (void)
15213 return seg_info (now_seg)->tc_segment_info_data.mips16;
15216 /* Fill in an rs_align_code fragment. This only needs to do something
15217 for MIPS16 code, where 0 is not a nop. */
15220 mips_handle_align (fragS *fragp)
15223 int bytes, size, excess;
15226 if (fragp->fr_type != rs_align_code)
15229 p = fragp->fr_literal + fragp->fr_fix;
15232 opcode = mips16_nop_insn.insn_opcode;
15237 opcode = nop_insn.insn_opcode;
15241 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
15242 excess = bytes % size;
15245 /* If we're not inserting a whole number of instructions,
15246 pad the end of the fixed part of the frag with zeros. */
15247 memset (p, 0, excess);
15249 fragp->fr_fix += excess;
15252 md_number_to_chars (p, opcode, size);
15253 fragp->fr_var = size;
15257 md_obj_begin (void)
15264 /* Check for premature end, nesting errors, etc. */
15266 as_warn (_("missing .end at end of assembly"));
15275 if (*input_line_pointer == '-')
15277 ++input_line_pointer;
15280 if (!ISDIGIT (*input_line_pointer))
15281 as_bad (_("expected simple number"));
15282 if (input_line_pointer[0] == '0')
15284 if (input_line_pointer[1] == 'x')
15286 input_line_pointer += 2;
15287 while (ISXDIGIT (*input_line_pointer))
15290 val |= hex_value (*input_line_pointer++);
15292 return negative ? -val : val;
15296 ++input_line_pointer;
15297 while (ISDIGIT (*input_line_pointer))
15300 val |= *input_line_pointer++ - '0';
15302 return negative ? -val : val;
15305 if (!ISDIGIT (*input_line_pointer))
15307 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
15308 *input_line_pointer, *input_line_pointer);
15309 as_warn (_("invalid number"));
15312 while (ISDIGIT (*input_line_pointer))
15315 val += *input_line_pointer++ - '0';
15317 return negative ? -val : val;
15320 /* The .file directive; just like the usual .file directive, but there
15321 is an initial number which is the ECOFF file index. In the non-ECOFF
15322 case .file implies DWARF-2. */
15325 s_mips_file (int x ATTRIBUTE_UNUSED)
15327 static int first_file_directive = 0;
15329 if (ECOFF_DEBUGGING)
15338 filename = dwarf2_directive_file (0);
15340 /* Versions of GCC up to 3.1 start files with a ".file"
15341 directive even for stabs output. Make sure that this
15342 ".file" is handled. Note that you need a version of GCC
15343 after 3.1 in order to support DWARF-2 on MIPS. */
15344 if (filename != NULL && ! first_file_directive)
15346 (void) new_logical_line (filename, -1);
15347 s_app_file_string (filename, 0);
15349 first_file_directive = 1;
15353 /* The .loc directive, implying DWARF-2. */
15356 s_mips_loc (int x ATTRIBUTE_UNUSED)
15358 if (!ECOFF_DEBUGGING)
15359 dwarf2_directive_loc (0);
15362 /* The .end directive. */
15365 s_mips_end (int x ATTRIBUTE_UNUSED)
15369 /* Following functions need their own .frame and .cprestore directives. */
15370 mips_frame_reg_valid = 0;
15371 mips_cprestore_valid = 0;
15373 if (!is_end_of_line[(unsigned char) *input_line_pointer])
15376 demand_empty_rest_of_line ();
15381 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
15382 as_warn (_(".end not in text section"));
15386 as_warn (_(".end directive without a preceding .ent directive."));
15387 demand_empty_rest_of_line ();
15393 gas_assert (S_GET_NAME (p));
15394 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
15395 as_warn (_(".end symbol does not match .ent symbol."));
15397 if (debug_type == DEBUG_STABS)
15398 stabs_generate_asm_endfunc (S_GET_NAME (p),
15402 as_warn (_(".end directive missing or unknown symbol"));
15405 /* Create an expression to calculate the size of the function. */
15406 if (p && cur_proc_ptr)
15408 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
15409 expressionS *exp = xmalloc (sizeof (expressionS));
15412 exp->X_op = O_subtract;
15413 exp->X_add_symbol = symbol_temp_new_now ();
15414 exp->X_op_symbol = p;
15415 exp->X_add_number = 0;
15417 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
15420 /* Generate a .pdr section. */
15421 if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr)
15423 segT saved_seg = now_seg;
15424 subsegT saved_subseg = now_subseg;
15428 #ifdef md_flush_pending_output
15429 md_flush_pending_output ();
15432 gas_assert (pdr_seg);
15433 subseg_set (pdr_seg, 0);
15435 /* Write the symbol. */
15436 exp.X_op = O_symbol;
15437 exp.X_add_symbol = p;
15438 exp.X_add_number = 0;
15439 emit_expr (&exp, 4);
15441 fragp = frag_more (7 * 4);
15443 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
15444 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
15445 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
15446 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
15447 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
15448 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
15449 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
15451 subseg_set (saved_seg, saved_subseg);
15453 #endif /* OBJ_ELF */
15455 cur_proc_ptr = NULL;
15458 /* The .aent and .ent directives. */
15461 s_mips_ent (int aent)
15465 symbolP = get_symbol ();
15466 if (*input_line_pointer == ',')
15467 ++input_line_pointer;
15468 SKIP_WHITESPACE ();
15469 if (ISDIGIT (*input_line_pointer)
15470 || *input_line_pointer == '-')
15473 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
15474 as_warn (_(".ent or .aent not in text section."));
15476 if (!aent && cur_proc_ptr)
15477 as_warn (_("missing .end"));
15481 /* This function needs its own .frame and .cprestore directives. */
15482 mips_frame_reg_valid = 0;
15483 mips_cprestore_valid = 0;
15485 cur_proc_ptr = &cur_proc;
15486 memset (cur_proc_ptr, '\0', sizeof (procS));
15488 cur_proc_ptr->func_sym = symbolP;
15492 if (debug_type == DEBUG_STABS)
15493 stabs_generate_asm_func (S_GET_NAME (symbolP),
15494 S_GET_NAME (symbolP));
15497 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
15499 demand_empty_rest_of_line ();
15502 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
15503 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
15504 s_mips_frame is used so that we can set the PDR information correctly.
15505 We can't use the ecoff routines because they make reference to the ecoff
15506 symbol table (in the mdebug section). */
15509 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
15512 if (IS_ELF && !ECOFF_DEBUGGING)
15516 if (cur_proc_ptr == (procS *) NULL)
15518 as_warn (_(".frame outside of .ent"));
15519 demand_empty_rest_of_line ();
15523 cur_proc_ptr->frame_reg = tc_get_register (1);
15525 SKIP_WHITESPACE ();
15526 if (*input_line_pointer++ != ','
15527 || get_absolute_expression_and_terminator (&val) != ',')
15529 as_warn (_("Bad .frame directive"));
15530 --input_line_pointer;
15531 demand_empty_rest_of_line ();
15535 cur_proc_ptr->frame_offset = val;
15536 cur_proc_ptr->pc_reg = tc_get_register (0);
15538 demand_empty_rest_of_line ();
15541 #endif /* OBJ_ELF */
15545 /* The .fmask and .mask directives. If the mdebug section is present
15546 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
15547 embedded targets, s_mips_mask is used so that we can set the PDR
15548 information correctly. We can't use the ecoff routines because they
15549 make reference to the ecoff symbol table (in the mdebug section). */
15552 s_mips_mask (int reg_type)
15555 if (IS_ELF && !ECOFF_DEBUGGING)
15559 if (cur_proc_ptr == (procS *) NULL)
15561 as_warn (_(".mask/.fmask outside of .ent"));
15562 demand_empty_rest_of_line ();
15566 if (get_absolute_expression_and_terminator (&mask) != ',')
15568 as_warn (_("Bad .mask/.fmask directive"));
15569 --input_line_pointer;
15570 demand_empty_rest_of_line ();
15574 off = get_absolute_expression ();
15576 if (reg_type == 'F')
15578 cur_proc_ptr->fpreg_mask = mask;
15579 cur_proc_ptr->fpreg_offset = off;
15583 cur_proc_ptr->reg_mask = mask;
15584 cur_proc_ptr->reg_offset = off;
15587 demand_empty_rest_of_line ();
15590 #endif /* OBJ_ELF */
15591 s_ignore (reg_type);
15594 /* A table describing all the processors gas knows about. Names are
15595 matched in the order listed.
15597 To ease comparison, please keep this table in the same order as
15598 gcc's mips_cpu_info_table[]. */
15599 static const struct mips_cpu_info mips_cpu_info_table[] =
15601 /* Entries for generic ISAs */
15602 { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 },
15603 { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 },
15604 { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 },
15605 { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 },
15606 { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 },
15607 { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 },
15608 { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 },
15609 { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
15610 { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
15613 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
15614 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
15615 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
15618 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
15621 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
15622 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
15623 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
15624 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
15625 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
15626 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
15627 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
15628 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
15629 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
15630 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
15631 { "orion", 0, ISA_MIPS3, CPU_R4600 },
15632 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
15633 /* ST Microelectronics Loongson 2E and 2F cores */
15634 { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E },
15635 { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F },
15638 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
15639 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
15640 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
15641 { "r14000", 0, ISA_MIPS4, CPU_R14000 },
15642 { "r16000", 0, ISA_MIPS4, CPU_R16000 },
15643 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
15644 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
15645 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
15646 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
15647 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
15648 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
15649 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
15650 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
15651 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
15652 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
15655 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
15656 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
15657 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
15658 { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
15660 /* MIPS 32 Release 2 */
15661 { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15662 { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15663 { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15664 { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
15665 { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15666 { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15667 { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15668 { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15669 { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15670 { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15671 /* Deprecated forms of the above. */
15672 { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15673 { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15674 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
15675 { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15676 { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15677 { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15678 { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15679 /* Deprecated forms of the above. */
15680 { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15681 { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15682 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
15683 { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15684 ISA_MIPS32R2, CPU_MIPS32R2 },
15685 { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15686 ISA_MIPS32R2, CPU_MIPS32R2 },
15687 { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15688 ISA_MIPS32R2, CPU_MIPS32R2 },
15689 { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15690 ISA_MIPS32R2, CPU_MIPS32R2 },
15691 /* Deprecated forms of the above. */
15692 { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15693 ISA_MIPS32R2, CPU_MIPS32R2 },
15694 { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15695 ISA_MIPS32R2, CPU_MIPS32R2 },
15696 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
15697 { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15698 ISA_MIPS32R2, CPU_MIPS32R2 },
15699 { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15700 ISA_MIPS32R2, CPU_MIPS32R2 },
15701 { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15702 ISA_MIPS32R2, CPU_MIPS32R2 },
15703 { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15704 ISA_MIPS32R2, CPU_MIPS32R2 },
15705 { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15706 ISA_MIPS32R2, CPU_MIPS32R2 },
15707 /* Deprecated forms of the above. */
15708 { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15709 ISA_MIPS32R2, CPU_MIPS32R2 },
15710 { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15711 ISA_MIPS32R2, CPU_MIPS32R2 },
15712 /* 1004K cores are multiprocessor versions of the 34K. */
15713 { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15714 ISA_MIPS32R2, CPU_MIPS32R2 },
15715 { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15716 ISA_MIPS32R2, CPU_MIPS32R2 },
15717 { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15718 ISA_MIPS32R2, CPU_MIPS32R2 },
15719 { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15720 ISA_MIPS32R2, CPU_MIPS32R2 },
15723 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
15724 { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
15725 { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
15726 { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
15728 /* Broadcom SB-1 CPU core */
15729 { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
15730 ISA_MIPS64, CPU_SB1 },
15731 /* Broadcom SB-1A CPU core */
15732 { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
15733 ISA_MIPS64, CPU_SB1 },
15735 { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A },
15737 /* MIPS 64 Release 2 */
15739 /* Cavium Networks Octeon CPU core */
15740 { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
15743 { "xlr", 0, ISA_MIPS64, CPU_XLR },
15750 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
15751 with a final "000" replaced by "k". Ignore case.
15753 Note: this function is shared between GCC and GAS. */
15756 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
15758 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
15759 given++, canonical++;
15761 return ((*given == 0 && *canonical == 0)
15762 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
15766 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
15767 CPU name. We've traditionally allowed a lot of variation here.
15769 Note: this function is shared between GCC and GAS. */
15772 mips_matching_cpu_name_p (const char *canonical, const char *given)
15774 /* First see if the name matches exactly, or with a final "000"
15775 turned into "k". */
15776 if (mips_strict_matching_cpu_name_p (canonical, given))
15779 /* If not, try comparing based on numerical designation alone.
15780 See if GIVEN is an unadorned number, or 'r' followed by a number. */
15781 if (TOLOWER (*given) == 'r')
15783 if (!ISDIGIT (*given))
15786 /* Skip over some well-known prefixes in the canonical name,
15787 hoping to find a number there too. */
15788 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
15790 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
15792 else if (TOLOWER (canonical[0]) == 'r')
15795 return mips_strict_matching_cpu_name_p (canonical, given);
15799 /* Parse an option that takes the name of a processor as its argument.
15800 OPTION is the name of the option and CPU_STRING is the argument.
15801 Return the corresponding processor enumeration if the CPU_STRING is
15802 recognized, otherwise report an error and return null.
15804 A similar function exists in GCC. */
15806 static const struct mips_cpu_info *
15807 mips_parse_cpu (const char *option, const char *cpu_string)
15809 const struct mips_cpu_info *p;
15811 /* 'from-abi' selects the most compatible architecture for the given
15812 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
15813 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15814 version. Look first at the -mgp options, if given, otherwise base
15815 the choice on MIPS_DEFAULT_64BIT.
15817 Treat NO_ABI like the EABIs. One reason to do this is that the
15818 plain 'mips' and 'mips64' configs have 'from-abi' as their default
15819 architecture. This code picks MIPS I for 'mips' and MIPS III for
15820 'mips64', just as we did in the days before 'from-abi'. */
15821 if (strcasecmp (cpu_string, "from-abi") == 0)
15823 if (ABI_NEEDS_32BIT_REGS (mips_abi))
15824 return mips_cpu_info_from_isa (ISA_MIPS1);
15826 if (ABI_NEEDS_64BIT_REGS (mips_abi))
15827 return mips_cpu_info_from_isa (ISA_MIPS3);
15829 if (file_mips_gp32 >= 0)
15830 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
15832 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
15837 /* 'default' has traditionally been a no-op. Probably not very useful. */
15838 if (strcasecmp (cpu_string, "default") == 0)
15841 for (p = mips_cpu_info_table; p->name != 0; p++)
15842 if (mips_matching_cpu_name_p (p->name, cpu_string))
15845 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
15849 /* Return the canonical processor information for ISA (a member of the
15850 ISA_MIPS* enumeration). */
15852 static const struct mips_cpu_info *
15853 mips_cpu_info_from_isa (int isa)
15857 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15858 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
15859 && isa == mips_cpu_info_table[i].isa)
15860 return (&mips_cpu_info_table[i]);
15865 static const struct mips_cpu_info *
15866 mips_cpu_info_from_arch (int arch)
15870 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15871 if (arch == mips_cpu_info_table[i].cpu)
15872 return (&mips_cpu_info_table[i]);
15878 show (FILE *stream, const char *string, int *col_p, int *first_p)
15882 fprintf (stream, "%24s", "");
15887 fprintf (stream, ", ");
15891 if (*col_p + strlen (string) > 72)
15893 fprintf (stream, "\n%24s", "");
15897 fprintf (stream, "%s", string);
15898 *col_p += strlen (string);
15904 md_show_usage (FILE *stream)
15909 fprintf (stream, _("\
15911 -EB generate big endian output\n\
15912 -EL generate little endian output\n\
15913 -g, -g2 do not remove unneeded NOPs or swap branches\n\
15914 -G NUM allow referencing objects up to NUM bytes\n\
15915 implicitly with the gp register [default 8]\n"));
15916 fprintf (stream, _("\
15917 -mips1 generate MIPS ISA I instructions\n\
15918 -mips2 generate MIPS ISA II instructions\n\
15919 -mips3 generate MIPS ISA III instructions\n\
15920 -mips4 generate MIPS ISA IV instructions\n\
15921 -mips5 generate MIPS ISA V instructions\n\
15922 -mips32 generate MIPS32 ISA instructions\n\
15923 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
15924 -mips64 generate MIPS64 ISA instructions\n\
15925 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
15926 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
15930 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15931 show (stream, mips_cpu_info_table[i].name, &column, &first);
15932 show (stream, "from-abi", &column, &first);
15933 fputc ('\n', stream);
15935 fprintf (stream, _("\
15936 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
15937 -no-mCPU don't generate code specific to CPU.\n\
15938 For -mCPU and -no-mCPU, CPU must be one of:\n"));
15942 show (stream, "3900", &column, &first);
15943 show (stream, "4010", &column, &first);
15944 show (stream, "4100", &column, &first);
15945 show (stream, "4650", &column, &first);
15946 fputc ('\n', stream);
15948 fprintf (stream, _("\
15949 -mips16 generate mips16 instructions\n\
15950 -no-mips16 do not generate mips16 instructions\n"));
15951 fprintf (stream, _("\
15952 -msmartmips generate smartmips instructions\n\
15953 -mno-smartmips do not generate smartmips instructions\n"));
15954 fprintf (stream, _("\
15955 -mdsp generate DSP instructions\n\
15956 -mno-dsp do not generate DSP instructions\n"));
15957 fprintf (stream, _("\
15958 -mdspr2 generate DSP R2 instructions\n\
15959 -mno-dspr2 do not generate DSP R2 instructions\n"));
15960 fprintf (stream, _("\
15961 -mmt generate MT instructions\n\
15962 -mno-mt do not generate MT instructions\n"));
15963 fprintf (stream, _("\
15964 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
15965 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
15966 -mfix-vr4120 work around certain VR4120 errata\n\
15967 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
15968 -mfix-24k insert a nop after ERET and DERET instructions\n\
15969 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
15970 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
15971 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
15972 -msym32 assume all symbols have 32-bit values\n\
15973 -O0 remove unneeded NOPs, do not swap branches\n\
15974 -O remove unneeded NOPs and swap branches\n\
15975 --trap, --no-break trap exception on div by 0 and mult overflow\n\
15976 --break, --no-trap break exception on div by 0 and mult overflow\n"));
15977 fprintf (stream, _("\
15978 -mhard-float allow floating-point instructions\n\
15979 -msoft-float do not allow floating-point instructions\n\
15980 -msingle-float only allow 32-bit floating-point operations\n\
15981 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
15982 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
15985 fprintf (stream, _("\
15986 -KPIC, -call_shared generate SVR4 position independent code\n\
15987 -call_nonpic generate non-PIC code that can operate with DSOs\n\
15988 -mvxworks-pic generate VxWorks position independent code\n\
15989 -non_shared do not generate code that can operate with DSOs\n\
15990 -xgot assume a 32 bit GOT\n\
15991 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
15992 -mshared, -mno-shared disable/enable .cpload optimization for\n\
15993 position dependent (non shared) code\n\
15994 -mabi=ABI create ABI conformant object file for:\n"));
15998 show (stream, "32", &column, &first);
15999 show (stream, "o64", &column, &first);
16000 show (stream, "n32", &column, &first);
16001 show (stream, "64", &column, &first);
16002 show (stream, "eabi", &column, &first);
16004 fputc ('\n', stream);
16006 fprintf (stream, _("\
16007 -32 create o32 ABI object file (default)\n\
16008 -n32 create n32 ABI object file\n\
16009 -64 create 64 ABI object file\n"));
16015 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
16017 if (HAVE_64BIT_SYMBOLS)
16018 return dwarf2_format_64bit_irix;
16020 return dwarf2_format_32bit;
16025 mips_dwarf2_addr_size (void)
16027 if (HAVE_64BIT_OBJECTS)
16033 /* Standard calling conventions leave the CFA at SP on entry. */
16035 mips_cfi_frame_initial_instructions (void)
16037 cfi_add_CFA_def_cfa_register (SP);
16041 tc_mips_regname_to_dw2regnum (char *regname)
16043 unsigned int regnum = -1;
16046 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))