1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
37 /* Check assumptions made in this file. */
38 typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1];
39 typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1];
42 #define DBG(x) printf x
47 /* Clean up namespace so we can include obj-elf.h too. */
48 static int mips_output_flavor (void);
49 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
50 #undef OBJ_PROCESS_STAB
57 #undef obj_frob_file_after_relocs
58 #undef obj_frob_symbol
60 #undef obj_sec_sym_ok_for_reloc
61 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
64 /* Fix any of them that we actually care about. */
66 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 static char *mips_regmask_frag;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 #define AT mips_opts.at
107 extern int target_big_endian;
109 /* The name of the readonly data section. */
110 #define RDATA_SECTION_NAME ".rodata"
112 /* Ways in which an instruction can be "appended" to the output. */
114 /* Just add it normally. */
117 /* Add it normally and then add a nop. */
120 /* Turn an instruction with a delay slot into a "compact" version. */
123 /* Insert the instruction before the last one. */
127 /* Information about an instruction, including its format, operands
131 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
132 const struct mips_opcode *insn_mo;
134 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
135 a copy of INSN_MO->match with the operands filled in. If we have
136 decided to use an extended MIPS16 instruction, this includes the
138 unsigned long insn_opcode;
140 /* The frag that contains the instruction. */
143 /* The offset into FRAG of the first instruction byte. */
146 /* The relocs associated with the instruction, if any. */
149 /* True if this entry cannot be moved from its current position. */
150 unsigned int fixed_p : 1;
152 /* True if this instruction occurred in a .set noreorder block. */
153 unsigned int noreorder_p : 1;
155 /* True for mips16 instructions that jump to an absolute address. */
156 unsigned int mips16_absolute_jump_p : 1;
158 /* True if this instruction is complete. */
159 unsigned int complete_p : 1;
161 /* True if this instruction is cleared from history by unconditional
163 unsigned int cleared_p : 1;
166 /* The ABI to use. */
177 /* MIPS ABI we are using for this output file. */
178 static enum mips_abi_level mips_abi = NO_ABI;
180 /* Whether or not we have code that can call pic code. */
181 int mips_abicalls = FALSE;
183 /* Whether or not we have code which can be put into a shared
185 static bfd_boolean mips_in_shared = TRUE;
187 /* This is the set of options which may be modified by the .set
188 pseudo-op. We use a struct so that .set push and .set pop are more
191 struct mips_set_options
193 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
194 if it has not been initialized. Changed by `.set mipsN', and the
195 -mipsN command line option, and the default CPU. */
197 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
198 <asename>', by command line options, and based on the default
201 /* Whether we are assembling for the mips16 processor. 0 if we are
202 not, 1 if we are, and -1 if the value has not been initialized.
203 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
204 -nomips16 command line options, and the default CPU. */
206 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
207 1 if we are, and -1 if the value has not been initialized. Changed
208 by `.set micromips' and `.set nomicromips', and the -mmicromips
209 and -mno-micromips command line options, and the default CPU. */
211 /* Non-zero if we should not reorder instructions. Changed by `.set
212 reorder' and `.set noreorder'. */
214 /* Non-zero if we should not permit the register designated "assembler
215 temporary" to be used in instructions. The value is the register
216 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
217 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
219 /* Non-zero if we should warn when a macro instruction expands into
220 more than one machine instruction. Changed by `.set nomacro' and
222 int warn_about_macros;
223 /* Non-zero if we should not move instructions. Changed by `.set
224 move', `.set volatile', `.set nomove', and `.set novolatile'. */
226 /* Non-zero if we should not optimize branches by moving the target
227 of the branch into the delay slot. Actually, we don't perform
228 this optimization anyhow. Changed by `.set bopt' and `.set
231 /* Non-zero if we should not autoextend mips16 instructions.
232 Changed by `.set autoextend' and `.set noautoextend'. */
234 /* True if we should only emit 32-bit microMIPS instructions.
235 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
236 and -mno-insn32 command line options. */
238 /* Restrict general purpose registers and floating point registers
239 to 32 bit. This is initially determined when -mgp32 or -mfp32
240 is passed but can changed if the assembler code uses .set mipsN. */
243 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
244 command line option, and the default CPU. */
246 /* True if ".set sym32" is in effect. */
248 /* True if floating-point operations are not allowed. Changed by .set
249 softfloat or .set hardfloat, by command line options -msoft-float or
250 -mhard-float. The default is false. */
251 bfd_boolean soft_float;
253 /* True if only single-precision floating-point operations are allowed.
254 Changed by .set singlefloat or .set doublefloat, command-line options
255 -msingle-float or -mdouble-float. The default is false. */
256 bfd_boolean single_float;
259 /* This is the struct we use to hold the current set of options. Note
260 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
261 -1 to indicate that they have not been initialized. */
263 /* True if -mgp32 was passed. */
264 static int file_mips_gp32 = -1;
266 /* True if -mfp32 was passed. */
267 static int file_mips_fp32 = -1;
269 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
270 static int file_mips_soft_float = 0;
272 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
273 static int file_mips_single_float = 0;
275 /* True if -mnan=2008, false if -mnan=legacy. */
276 static bfd_boolean mips_flag_nan2008 = FALSE;
278 static struct mips_set_options mips_opts =
280 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
281 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
282 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
283 /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
284 /* soft_float */ FALSE, /* single_float */ FALSE
287 /* The set of ASEs that were selected on the command line, either
288 explicitly via ASE options or implicitly through things like -march. */
289 static unsigned int file_ase;
291 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
292 static unsigned int file_ase_explicit;
294 /* These variables are filled in with the masks of registers used.
295 The object format code reads them and puts them in the appropriate
297 unsigned long mips_gprmask;
298 unsigned long mips_cprmask[4];
300 /* MIPS ISA we are using for this output file. */
301 static int file_mips_isa = ISA_UNKNOWN;
303 /* True if any MIPS16 code was produced. */
304 static int file_ase_mips16;
306 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
307 || mips_opts.isa == ISA_MIPS32R2 \
308 || mips_opts.isa == ISA_MIPS64 \
309 || mips_opts.isa == ISA_MIPS64R2)
311 /* True if any microMIPS code was produced. */
312 static int file_ase_micromips;
314 /* True if we want to create R_MIPS_JALR for jalr $25. */
316 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
318 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
319 because there's no place for any addend, the only acceptable
320 expression is a bare symbol. */
321 #define MIPS_JALR_HINT_P(EXPR) \
322 (!HAVE_IN_PLACE_ADDENDS \
323 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
326 /* The argument of the -march= flag. The architecture we are assembling. */
327 static int file_mips_arch = CPU_UNKNOWN;
328 static const char *mips_arch_string;
330 /* The argument of the -mtune= flag. The architecture for which we
332 static int mips_tune = CPU_UNKNOWN;
333 static const char *mips_tune_string;
335 /* True when generating 32-bit code for a 64-bit processor. */
336 static int mips_32bitmode = 0;
338 /* True if the given ABI requires 32-bit registers. */
339 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
341 /* Likewise 64-bit registers. */
342 #define ABI_NEEDS_64BIT_REGS(ABI) \
344 || (ABI) == N64_ABI \
347 /* Return true if ISA supports 64 bit wide gp registers. */
348 #define ISA_HAS_64BIT_REGS(ISA) \
349 ((ISA) == ISA_MIPS3 \
350 || (ISA) == ISA_MIPS4 \
351 || (ISA) == ISA_MIPS5 \
352 || (ISA) == ISA_MIPS64 \
353 || (ISA) == ISA_MIPS64R2)
355 /* Return true if ISA supports 64 bit wide float registers. */
356 #define ISA_HAS_64BIT_FPRS(ISA) \
357 ((ISA) == ISA_MIPS3 \
358 || (ISA) == ISA_MIPS4 \
359 || (ISA) == ISA_MIPS5 \
360 || (ISA) == ISA_MIPS32R2 \
361 || (ISA) == ISA_MIPS64 \
362 || (ISA) == ISA_MIPS64R2)
364 /* Return true if ISA supports 64-bit right rotate (dror et al.)
366 #define ISA_HAS_DROR(ISA) \
367 ((ISA) == ISA_MIPS64R2 \
368 || (mips_opts.micromips \
369 && ISA_HAS_64BIT_REGS (ISA)) \
372 /* Return true if ISA supports 32-bit right rotate (ror et al.)
374 #define ISA_HAS_ROR(ISA) \
375 ((ISA) == ISA_MIPS32R2 \
376 || (ISA) == ISA_MIPS64R2 \
377 || (mips_opts.ase & ASE_SMARTMIPS) \
378 || mips_opts.micromips \
381 /* Return true if ISA supports single-precision floats in odd registers. */
382 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
383 ((ISA) == ISA_MIPS32 \
384 || (ISA) == ISA_MIPS32R2 \
385 || (ISA) == ISA_MIPS64 \
386 || (ISA) == ISA_MIPS64R2)
388 /* Return true if ISA supports move to/from high part of a 64-bit
389 floating-point register. */
390 #define ISA_HAS_MXHC1(ISA) \
391 ((ISA) == ISA_MIPS32R2 \
392 || (ISA) == ISA_MIPS64R2)
394 #define HAVE_32BIT_GPRS \
395 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
397 #define HAVE_32BIT_FPRS \
398 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
400 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
401 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
403 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
405 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
407 /* True if relocations are stored in-place. */
408 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
410 /* The ABI-derived address size. */
411 #define HAVE_64BIT_ADDRESSES \
412 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
413 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
415 /* The size of symbolic constants (i.e., expressions of the form
416 "SYMBOL" or "SYMBOL + OFFSET"). */
417 #define HAVE_32BIT_SYMBOLS \
418 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
419 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
421 /* Addresses are loaded in different ways, depending on the address size
422 in use. The n32 ABI Documentation also mandates the use of additions
423 with overflow checking, but existing implementations don't follow it. */
424 #define ADDRESS_ADD_INSN \
425 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
427 #define ADDRESS_ADDI_INSN \
428 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
430 #define ADDRESS_LOAD_INSN \
431 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
433 #define ADDRESS_STORE_INSN \
434 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
436 /* Return true if the given CPU supports the MIPS16 ASE. */
437 #define CPU_HAS_MIPS16(cpu) \
438 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
439 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
441 /* Return true if the given CPU supports the microMIPS ASE. */
442 #define CPU_HAS_MICROMIPS(cpu) 0
444 /* True if CPU has a dror instruction. */
445 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
447 /* True if CPU has a ror instruction. */
448 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
450 /* True if CPU is in the Octeon family */
451 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
453 /* True if CPU has seq/sne and seqi/snei instructions. */
454 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
456 /* True, if CPU has support for ldc1 and sdc1. */
457 #define CPU_HAS_LDC1_SDC1(CPU) \
458 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
460 /* True if mflo and mfhi can be immediately followed by instructions
461 which write to the HI and LO registers.
463 According to MIPS specifications, MIPS ISAs I, II, and III need
464 (at least) two instructions between the reads of HI/LO and
465 instructions which write them, and later ISAs do not. Contradicting
466 the MIPS specifications, some MIPS IV processor user manuals (e.g.
467 the UM for the NEC Vr5000) document needing the instructions between
468 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
469 MIPS64 and later ISAs to have the interlocks, plus any specific
470 earlier-ISA CPUs for which CPU documentation declares that the
471 instructions are really interlocked. */
472 #define hilo_interlocks \
473 (mips_opts.isa == ISA_MIPS32 \
474 || mips_opts.isa == ISA_MIPS32R2 \
475 || mips_opts.isa == ISA_MIPS64 \
476 || mips_opts.isa == ISA_MIPS64R2 \
477 || mips_opts.arch == CPU_R4010 \
478 || mips_opts.arch == CPU_R5900 \
479 || mips_opts.arch == CPU_R10000 \
480 || mips_opts.arch == CPU_R12000 \
481 || mips_opts.arch == CPU_R14000 \
482 || mips_opts.arch == CPU_R16000 \
483 || mips_opts.arch == CPU_RM7000 \
484 || mips_opts.arch == CPU_VR5500 \
485 || mips_opts.micromips \
488 /* Whether the processor uses hardware interlocks to protect reads
489 from the GPRs after they are loaded from memory, and thus does not
490 require nops to be inserted. This applies to instructions marked
491 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
492 level I and microMIPS mode instructions are always interlocked. */
493 #define gpr_interlocks \
494 (mips_opts.isa != ISA_MIPS1 \
495 || mips_opts.arch == CPU_R3900 \
496 || mips_opts.arch == CPU_R5900 \
497 || mips_opts.micromips \
500 /* Whether the processor uses hardware interlocks to avoid delays
501 required by coprocessor instructions, and thus does not require
502 nops to be inserted. This applies to instructions marked
503 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
504 between instructions marked INSN_WRITE_COND_CODE and ones marked
505 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
506 levels I, II, and III and microMIPS mode instructions are always
508 /* Itbl support may require additional care here. */
509 #define cop_interlocks \
510 ((mips_opts.isa != ISA_MIPS1 \
511 && mips_opts.isa != ISA_MIPS2 \
512 && mips_opts.isa != ISA_MIPS3) \
513 || mips_opts.arch == CPU_R4300 \
514 || mips_opts.micromips \
517 /* Whether the processor uses hardware interlocks to protect reads
518 from coprocessor registers after they are loaded from memory, and
519 thus does not require nops to be inserted. This applies to
520 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
521 requires at MIPS ISA level I and microMIPS mode instructions are
522 always interlocked. */
523 #define cop_mem_interlocks \
524 (mips_opts.isa != ISA_MIPS1 \
525 || mips_opts.micromips \
528 /* Is this a mfhi or mflo instruction? */
529 #define MF_HILO_INSN(PINFO) \
530 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
532 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
533 has been selected. This implies, in particular, that addresses of text
534 labels have their LSB set. */
535 #define HAVE_CODE_COMPRESSION \
536 ((mips_opts.mips16 | mips_opts.micromips) != 0)
538 /* The minimum and maximum signed values that can be stored in a GPR. */
539 #define GPR_SMAX ((offsetT) (((valueT) 1 << (HAVE_64BIT_GPRS ? 63 : 31)) - 1))
540 #define GPR_SMIN (-GPR_SMAX - 1)
542 /* MIPS PIC level. */
544 enum mips_pic_level mips_pic;
546 /* 1 if we should generate 32 bit offsets from the $gp register in
547 SVR4_PIC mode. Currently has no meaning in other modes. */
548 static int mips_big_got = 0;
550 /* 1 if trap instructions should used for overflow rather than break
552 static int mips_trap = 0;
554 /* 1 if double width floating point constants should not be constructed
555 by assembling two single width halves into two single width floating
556 point registers which just happen to alias the double width destination
557 register. On some architectures this aliasing can be disabled by a bit
558 in the status register, and the setting of this bit cannot be determined
559 automatically at assemble time. */
560 static int mips_disable_float_construction;
562 /* Non-zero if any .set noreorder directives were used. */
564 static int mips_any_noreorder;
566 /* Non-zero if nops should be inserted when the register referenced in
567 an mfhi/mflo instruction is read in the next two instructions. */
568 static int mips_7000_hilo_fix;
570 /* The size of objects in the small data section. */
571 static unsigned int g_switch_value = 8;
572 /* Whether the -G option was used. */
573 static int g_switch_seen = 0;
578 /* If we can determine in advance that GP optimization won't be
579 possible, we can skip the relaxation stuff that tries to produce
580 GP-relative references. This makes delay slot optimization work
583 This function can only provide a guess, but it seems to work for
584 gcc output. It needs to guess right for gcc, otherwise gcc
585 will put what it thinks is a GP-relative instruction in a branch
588 I don't know if a fix is needed for the SVR4_PIC mode. I've only
589 fixed it for the non-PIC mode. KR 95/04/07 */
590 static int nopic_need_relax (symbolS *, int);
592 /* handle of the OPCODE hash table */
593 static struct hash_control *op_hash = NULL;
595 /* The opcode hash table we use for the mips16. */
596 static struct hash_control *mips16_op_hash = NULL;
598 /* The opcode hash table we use for the microMIPS ASE. */
599 static struct hash_control *micromips_op_hash = NULL;
601 /* This array holds the chars that always start a comment. If the
602 pre-processor is disabled, these aren't very useful */
603 const char comment_chars[] = "#";
605 /* This array holds the chars that only start a comment at the beginning of
606 a line. If the line seems to have the form '# 123 filename'
607 .line and .file directives will appear in the pre-processed output */
608 /* Note that input_file.c hand checks for '#' at the beginning of the
609 first line of the input file. This is because the compiler outputs
610 #NO_APP at the beginning of its output. */
611 /* Also note that C style comments are always supported. */
612 const char line_comment_chars[] = "#";
614 /* This array holds machine specific line separator characters. */
615 const char line_separator_chars[] = ";";
617 /* Chars that can be used to separate mant from exp in floating point nums */
618 const char EXP_CHARS[] = "eE";
620 /* Chars that mean this number is a floating point constant */
623 const char FLT_CHARS[] = "rRsSfFdDxXpP";
625 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
626 changed in read.c . Ideally it shouldn't have to know about it at all,
627 but nothing is ideal around here.
630 static char *insn_error;
632 static int auto_align = 1;
634 /* When outputting SVR4 PIC code, the assembler needs to know the
635 offset in the stack frame from which to restore the $gp register.
636 This is set by the .cprestore pseudo-op, and saved in this
638 static offsetT mips_cprestore_offset = -1;
640 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
641 more optimizations, it can use a register value instead of a memory-saved
642 offset and even an other register than $gp as global pointer. */
643 static offsetT mips_cpreturn_offset = -1;
644 static int mips_cpreturn_register = -1;
645 static int mips_gp_register = GP;
646 static int mips_gprel_offset = 0;
648 /* Whether mips_cprestore_offset has been set in the current function
649 (or whether it has already been warned about, if not). */
650 static int mips_cprestore_valid = 0;
652 /* This is the register which holds the stack frame, as set by the
653 .frame pseudo-op. This is needed to implement .cprestore. */
654 static int mips_frame_reg = SP;
656 /* Whether mips_frame_reg has been set in the current function
657 (or whether it has already been warned about, if not). */
658 static int mips_frame_reg_valid = 0;
660 /* To output NOP instructions correctly, we need to keep information
661 about the previous two instructions. */
663 /* Whether we are optimizing. The default value of 2 means to remove
664 unneeded NOPs and swap branch instructions when possible. A value
665 of 1 means to not swap branches. A value of 0 means to always
667 static int mips_optimize = 2;
669 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
670 equivalent to seeing no -g option at all. */
671 static int mips_debug = 0;
673 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
674 #define MAX_VR4130_NOPS 4
676 /* The maximum number of NOPs needed to fill delay slots. */
677 #define MAX_DELAY_NOPS 2
679 /* The maximum number of NOPs needed for any purpose. */
682 /* A list of previous instructions, with index 0 being the most recent.
683 We need to look back MAX_NOPS instructions when filling delay slots
684 or working around processor errata. We need to look back one
685 instruction further if we're thinking about using history[0] to
686 fill a branch delay slot. */
687 static struct mips_cl_insn history[1 + MAX_NOPS];
689 /* Nop instructions used by emit_nop. */
690 static struct mips_cl_insn nop_insn;
691 static struct mips_cl_insn mips16_nop_insn;
692 static struct mips_cl_insn micromips_nop16_insn;
693 static struct mips_cl_insn micromips_nop32_insn;
695 /* The appropriate nop for the current mode. */
696 #define NOP_INSN (mips_opts.mips16 \
698 : (mips_opts.micromips \
699 ? (mips_opts.insn32 \
700 ? µmips_nop32_insn \
701 : µmips_nop16_insn) \
704 /* The size of NOP_INSN in bytes. */
705 #define NOP_INSN_SIZE ((mips_opts.mips16 \
706 || (mips_opts.micromips && !mips_opts.insn32)) \
709 /* If this is set, it points to a frag holding nop instructions which
710 were inserted before the start of a noreorder section. If those
711 nops turn out to be unnecessary, the size of the frag can be
713 static fragS *prev_nop_frag;
715 /* The number of nop instructions we created in prev_nop_frag. */
716 static int prev_nop_frag_holds;
718 /* The number of nop instructions that we know we need in
720 static int prev_nop_frag_required;
722 /* The number of instructions we've seen since prev_nop_frag. */
723 static int prev_nop_frag_since;
725 /* Relocations against symbols are sometimes done in two parts, with a HI
726 relocation and a LO relocation. Each relocation has only 16 bits of
727 space to store an addend. This means that in order for the linker to
728 handle carries correctly, it must be able to locate both the HI and
729 the LO relocation. This means that the relocations must appear in
730 order in the relocation table.
732 In order to implement this, we keep track of each unmatched HI
733 relocation. We then sort them so that they immediately precede the
734 corresponding LO relocation. */
739 struct mips_hi_fixup *next;
742 /* The section this fixup is in. */
746 /* The list of unmatched HI relocs. */
748 static struct mips_hi_fixup *mips_hi_fixup_list;
750 /* The frag containing the last explicit relocation operator.
751 Null if explicit relocations have not been used. */
753 static fragS *prev_reloc_op_frag;
755 /* Map normal MIPS register numbers to mips16 register numbers. */
757 #define X ILLEGAL_REG
758 static const int mips32_to_16_reg_map[] =
760 X, X, 2, 3, 4, 5, 6, 7,
761 X, X, X, X, X, X, X, X,
762 0, 1, X, X, X, X, X, X,
763 X, X, X, X, X, X, X, X
767 /* Map mips16 register numbers to normal MIPS register numbers. */
769 static const unsigned int mips16_to_32_reg_map[] =
771 16, 17, 2, 3, 4, 5, 6, 7
774 /* Map normal MIPS register numbers to microMIPS register numbers. */
776 #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map
777 #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map
778 #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map
779 #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map
780 #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map
781 #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map
782 #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
784 #define X ILLEGAL_REG
785 /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
786 static const int mips32_to_micromips_reg_m_map[] =
788 0, X, 2, 3, X, X, X, X,
789 X, X, X, X, X, X, X, X,
790 4, 1, 5, 6, 7, X, X, X,
791 X, X, X, X, X, X, X, X
794 /* reg type q: 0, 2-7. 17. */
795 static const int mips32_to_micromips_reg_q_map[] =
797 0, X, 2, 3, 4, 5, 6, 7,
798 X, X, X, X, X, X, X, X,
799 X, 1, X, X, X, X, X, X,
800 X, X, X, X, X, X, X, X
803 #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map
806 /* Map microMIPS register numbers to normal MIPS register numbers. */
808 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
809 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
810 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
811 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
812 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
813 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
815 /* The microMIPS registers with type h. */
816 static const unsigned int micromips_to_32_reg_h_map1[] =
818 5, 5, 6, 4, 4, 4, 4, 4
820 static const unsigned int micromips_to_32_reg_h_map2[] =
822 6, 7, 7, 21, 22, 5, 6, 7
825 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
827 /* The microMIPS registers with type m. */
828 static const unsigned int micromips_to_32_reg_m_map[] =
830 0, 17, 2, 3, 16, 18, 19, 20
833 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
835 /* The microMIPS registers with type q. */
836 static const unsigned int micromips_to_32_reg_q_map[] =
838 0, 17, 2, 3, 4, 5, 6, 7
841 /* microMIPS imm type B. */
842 static const int micromips_imm_b_map[] =
844 1, 4, 8, 12, 16, 20, 24, -1
847 /* microMIPS imm type C. */
848 static const int micromips_imm_c_map[] =
850 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
853 /* Classifies the kind of instructions we're interested in when
854 implementing -mfix-vr4120. */
855 enum fix_vr4120_class
863 NUM_FIX_VR4120_CLASSES
866 /* ...likewise -mfix-loongson2f-jump. */
867 static bfd_boolean mips_fix_loongson2f_jump;
869 /* ...likewise -mfix-loongson2f-nop. */
870 static bfd_boolean mips_fix_loongson2f_nop;
872 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
873 static bfd_boolean mips_fix_loongson2f;
875 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
876 there must be at least one other instruction between an instruction
877 of type X and an instruction of type Y. */
878 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
880 /* True if -mfix-vr4120 is in force. */
881 static int mips_fix_vr4120;
883 /* ...likewise -mfix-vr4130. */
884 static int mips_fix_vr4130;
886 /* ...likewise -mfix-24k. */
887 static int mips_fix_24k;
889 /* ...likewise -mfix-cn63xxp1 */
890 static bfd_boolean mips_fix_cn63xxp1;
892 /* We don't relax branches by default, since this causes us to expand
893 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
894 fail to compute the offset before expanding the macro to the most
895 efficient expansion. */
897 static int mips_relax_branch;
899 /* The expansion of many macros depends on the type of symbol that
900 they refer to. For example, when generating position-dependent code,
901 a macro that refers to a symbol may have two different expansions,
902 one which uses GP-relative addresses and one which uses absolute
903 addresses. When generating SVR4-style PIC, a macro may have
904 different expansions for local and global symbols.
906 We handle these situations by generating both sequences and putting
907 them in variant frags. In position-dependent code, the first sequence
908 will be the GP-relative one and the second sequence will be the
909 absolute one. In SVR4 PIC, the first sequence will be for global
910 symbols and the second will be for local symbols.
912 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
913 SECOND are the lengths of the two sequences in bytes. These fields
914 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
915 the subtype has the following flags:
918 Set if it has been decided that we should use the second
919 sequence instead of the first.
922 Set in the first variant frag if the macro's second implementation
923 is longer than its first. This refers to the macro as a whole,
924 not an individual relaxation.
927 Set in the first variant frag if the macro appeared in a .set nomacro
928 block and if one alternative requires a warning but the other does not.
931 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
934 RELAX_DELAY_SLOT_16BIT
935 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
938 RELAX_DELAY_SLOT_SIZE_FIRST
939 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
940 the macro is of the wrong size for the branch delay slot.
942 RELAX_DELAY_SLOT_SIZE_SECOND
943 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
944 the macro is of the wrong size for the branch delay slot.
946 The frag's "opcode" points to the first fixup for relaxable code.
948 Relaxable macros are generated using a sequence such as:
950 relax_start (SYMBOL);
951 ... generate first expansion ...
953 ... generate second expansion ...
956 The code and fixups for the unwanted alternative are discarded
957 by md_convert_frag. */
958 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
960 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
961 #define RELAX_SECOND(X) ((X) & 0xff)
962 #define RELAX_USE_SECOND 0x10000
963 #define RELAX_SECOND_LONGER 0x20000
964 #define RELAX_NOMACRO 0x40000
965 #define RELAX_DELAY_SLOT 0x80000
966 #define RELAX_DELAY_SLOT_16BIT 0x100000
967 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
968 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
970 /* Branch without likely bit. If label is out of range, we turn:
972 beq reg1, reg2, label
982 with the following opcode replacements:
989 bltzal <-> bgezal (with jal label instead of j label)
991 Even though keeping the delay slot instruction in the delay slot of
992 the branch would be more efficient, it would be very tricky to do
993 correctly, because we'd have to introduce a variable frag *after*
994 the delay slot instruction, and expand that instead. Let's do it
995 the easy way for now, even if the branch-not-taken case now costs
996 one additional instruction. Out-of-range branches are not supposed
997 to be common, anyway.
999 Branch likely. If label is out of range, we turn:
1001 beql reg1, reg2, label
1002 delay slot (annulled if branch not taken)
1011 delay slot (executed only if branch taken)
1014 It would be possible to generate a shorter sequence by losing the
1015 likely bit, generating something like:
1020 delay slot (executed only if branch taken)
1032 bltzall -> bgezal (with jal label instead of j label)
1033 bgezall -> bltzal (ditto)
1036 but it's not clear that it would actually improve performance. */
1037 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1038 ((relax_substateT) \
1041 | ((toofar) ? 0x20 : 0) \
1042 | ((link) ? 0x40 : 0) \
1043 | ((likely) ? 0x80 : 0) \
1044 | ((uncond) ? 0x100 : 0)))
1045 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1046 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1047 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1048 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1049 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1050 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1052 /* For mips16 code, we use an entirely different form of relaxation.
1053 mips16 supports two versions of most instructions which take
1054 immediate values: a small one which takes some small value, and a
1055 larger one which takes a 16 bit value. Since branches also follow
1056 this pattern, relaxing these values is required.
1058 We can assemble both mips16 and normal MIPS code in a single
1059 object. Therefore, we need to support this type of relaxation at
1060 the same time that we support the relaxation described above. We
1061 use the high bit of the subtype field to distinguish these cases.
1063 The information we store for this type of relaxation is the
1064 argument code found in the opcode file for this relocation, whether
1065 the user explicitly requested a small or extended form, and whether
1066 the relocation is in a jump or jal delay slot. That tells us the
1067 size of the value, and how it should be stored. We also store
1068 whether the fragment is considered to be extended or not. We also
1069 store whether this is known to be a branch to a different section,
1070 whether we have tried to relax this frag yet, and whether we have
1071 ever extended a PC relative fragment because of a shift count. */
1072 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1075 | ((small) ? 0x100 : 0) \
1076 | ((ext) ? 0x200 : 0) \
1077 | ((dslot) ? 0x400 : 0) \
1078 | ((jal_dslot) ? 0x800 : 0))
1079 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1080 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1081 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1082 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1083 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1084 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1085 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1086 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1087 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1088 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1089 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1090 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1092 /* For microMIPS code, we use relaxation similar to one we use for
1093 MIPS16 code. Some instructions that take immediate values support
1094 two encodings: a small one which takes some small value, and a
1095 larger one which takes a 16 bit value. As some branches also follow
1096 this pattern, relaxing these values is required.
1098 We can assemble both microMIPS and normal MIPS code in a single
1099 object. Therefore, we need to support this type of relaxation at
1100 the same time that we support the relaxation described above. We
1101 use one of the high bits of the subtype field to distinguish these
1104 The information we store for this type of relaxation is the argument
1105 code found in the opcode file for this relocation, the register
1106 selected as the assembler temporary, whether the branch is
1107 unconditional, whether it is compact, whether it stores the link
1108 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1109 branches to a sequence of instructions is enabled, and whether the
1110 displacement of a branch is too large to fit as an immediate argument
1111 of a 16-bit and a 32-bit branch, respectively. */
1112 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1113 relax32, toofar16, toofar32) \
1116 | (((at) & 0x1f) << 8) \
1117 | ((uncond) ? 0x2000 : 0) \
1118 | ((compact) ? 0x4000 : 0) \
1119 | ((link) ? 0x8000 : 0) \
1120 | ((relax32) ? 0x10000 : 0) \
1121 | ((toofar16) ? 0x20000 : 0) \
1122 | ((toofar32) ? 0x40000 : 0))
1123 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1124 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1125 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1126 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1127 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1128 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1129 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1131 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1132 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1133 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1134 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1135 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1136 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1138 /* Sign-extend 16-bit value X. */
1139 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1141 /* Is the given value a sign-extended 32-bit value? */
1142 #define IS_SEXT_32BIT_NUM(x) \
1143 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1144 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1146 /* Is the given value a sign-extended 16-bit value? */
1147 #define IS_SEXT_16BIT_NUM(x) \
1148 (((x) &~ (offsetT) 0x7fff) == 0 \
1149 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1151 /* Is the given value a sign-extended 12-bit value? */
1152 #define IS_SEXT_12BIT_NUM(x) \
1153 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1155 /* Is the given value a sign-extended 9-bit value? */
1156 #define IS_SEXT_9BIT_NUM(x) \
1157 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1159 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1160 #define IS_ZEXT_32BIT_NUM(x) \
1161 (((x) &~ (offsetT) 0xffffffff) == 0 \
1162 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1164 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1165 VALUE << SHIFT. VALUE is evaluated exactly once. */
1166 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1167 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1168 | (((VALUE) & (MASK)) << (SHIFT)))
1170 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1172 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1173 (((STRUCT) >> (SHIFT)) & (MASK))
1175 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1176 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1178 include/opcode/mips.h specifies operand fields using the macros
1179 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1180 with "MIPS16OP" instead of "OP". */
1181 #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \
1184 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1185 OP_MASK_##FIELD, OP_SH_##FIELD); \
1187 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1188 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \
1190 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1191 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1192 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1194 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1195 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1197 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1198 : EXTRACT_BITS ((INSN).insn_opcode, \
1199 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1200 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1201 EXTRACT_BITS ((INSN).insn_opcode, \
1202 MIPS16OP_MASK_##FIELD, \
1203 MIPS16OP_SH_##FIELD)
1205 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1206 #define MIPS16_EXTEND (0xf000U << 16)
1208 /* Whether or not we are emitting a branch-likely macro. */
1209 static bfd_boolean emit_branch_likely_macro = FALSE;
1211 /* Global variables used when generating relaxable macros. See the
1212 comment above RELAX_ENCODE for more details about how relaxation
1215 /* 0 if we're not emitting a relaxable macro.
1216 1 if we're emitting the first of the two relaxation alternatives.
1217 2 if we're emitting the second alternative. */
1220 /* The first relaxable fixup in the current frag. (In other words,
1221 the first fixup that refers to relaxable code.) */
1224 /* sizes[0] says how many bytes of the first alternative are stored in
1225 the current frag. Likewise sizes[1] for the second alternative. */
1226 unsigned int sizes[2];
1228 /* The symbol on which the choice of sequence depends. */
1232 /* Global variables used to decide whether a macro needs a warning. */
1234 /* True if the macro is in a branch delay slot. */
1235 bfd_boolean delay_slot_p;
1237 /* Set to the length in bytes required if the macro is in a delay slot
1238 that requires a specific length of instruction, otherwise zero. */
1239 unsigned int delay_slot_length;
1241 /* For relaxable macros, sizes[0] is the length of the first alternative
1242 in bytes and sizes[1] is the length of the second alternative.
1243 For non-relaxable macros, both elements give the length of the
1245 unsigned int sizes[2];
1247 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1248 instruction of the first alternative in bytes and first_insn_sizes[1]
1249 is the length of the first instruction of the second alternative.
1250 For non-relaxable macros, both elements give the length of the first
1251 instruction in bytes.
1253 Set to zero if we haven't yet seen the first instruction. */
1254 unsigned int first_insn_sizes[2];
1256 /* For relaxable macros, insns[0] is the number of instructions for the
1257 first alternative and insns[1] is the number of instructions for the
1260 For non-relaxable macros, both elements give the number of
1261 instructions for the macro. */
1262 unsigned int insns[2];
1264 /* The first variant frag for this macro. */
1266 } mips_macro_warning;
1268 /* Prototypes for static functions. */
1270 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1272 static void append_insn
1273 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1274 bfd_boolean expansionp);
1275 static void mips_no_prev_insn (void);
1276 static void macro_build (expressionS *, const char *, const char *, ...);
1277 static void mips16_macro_build
1278 (expressionS *, const char *, const char *, va_list *);
1279 static void load_register (int, expressionS *, int);
1280 static void macro_start (void);
1281 static void macro_end (void);
1282 static void macro (struct mips_cl_insn *ip, char *str);
1283 static void mips16_macro (struct mips_cl_insn * ip);
1284 static void mips_ip (char *str, struct mips_cl_insn * ip);
1285 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1286 static void mips16_immed
1287 (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT,
1288 unsigned int, unsigned long *);
1289 static size_t my_getSmallExpression
1290 (expressionS *, bfd_reloc_code_real_type *, char *);
1291 static void my_getExpression (expressionS *, char *);
1292 static void s_align (int);
1293 static void s_change_sec (int);
1294 static void s_change_section (int);
1295 static void s_cons (int);
1296 static void s_float_cons (int);
1297 static void s_mips_globl (int);
1298 static void s_option (int);
1299 static void s_mipsset (int);
1300 static void s_abicalls (int);
1301 static void s_cpload (int);
1302 static void s_cpsetup (int);
1303 static void s_cplocal (int);
1304 static void s_cprestore (int);
1305 static void s_cpreturn (int);
1306 static void s_dtprelword (int);
1307 static void s_dtpreldword (int);
1308 static void s_tprelword (int);
1309 static void s_tpreldword (int);
1310 static void s_gpvalue (int);
1311 static void s_gpword (int);
1312 static void s_gpdword (int);
1313 static void s_ehword (int);
1314 static void s_cpadd (int);
1315 static void s_insn (int);
1316 static void s_nan (int);
1317 static void md_obj_begin (void);
1318 static void md_obj_end (void);
1319 static void s_mips_ent (int);
1320 static void s_mips_end (int);
1321 static void s_mips_frame (int);
1322 static void s_mips_mask (int reg_type);
1323 static void s_mips_stab (int);
1324 static void s_mips_weakext (int);
1325 static void s_mips_file (int);
1326 static void s_mips_loc (int);
1327 static bfd_boolean pic_need_relax (symbolS *, asection *);
1328 static int relaxed_branch_length (fragS *, asection *, int);
1329 static int validate_mips_insn (const struct mips_opcode *);
1330 static int validate_micromips_insn (const struct mips_opcode *);
1331 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1332 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1334 /* Table and functions used to map between CPU/ISA names, and
1335 ISA levels, and CPU numbers. */
1337 struct mips_cpu_info
1339 const char *name; /* CPU or ISA name. */
1340 int flags; /* MIPS_CPU_* flags. */
1341 int ase; /* Set of ASEs implemented by the CPU. */
1342 int isa; /* ISA level. */
1343 int cpu; /* CPU number (default CPU if ISA). */
1346 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1348 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1349 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1350 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1352 /* Command-line options. */
1353 const char *md_shortopts = "O::g::G:";
1357 OPTION_MARCH = OPTION_MD_BASE,
1381 OPTION_NO_SMARTMIPS,
1387 OPTION_NO_MICROMIPS,
1390 OPTION_COMPAT_ARCH_BASE,
1399 OPTION_M7000_HILO_FIX,
1400 OPTION_MNO_7000_HILO_FIX,
1403 OPTION_FIX_LOONGSON2F_JUMP,
1404 OPTION_NO_FIX_LOONGSON2F_JUMP,
1405 OPTION_FIX_LOONGSON2F_NOP,
1406 OPTION_NO_FIX_LOONGSON2F_NOP,
1408 OPTION_NO_FIX_VR4120,
1410 OPTION_NO_FIX_VR4130,
1411 OPTION_FIX_CN63XXP1,
1412 OPTION_NO_FIX_CN63XXP1,
1419 OPTION_CONSTRUCT_FLOATS,
1420 OPTION_NO_CONSTRUCT_FLOATS,
1423 OPTION_RELAX_BRANCH,
1424 OPTION_NO_RELAX_BRANCH,
1433 OPTION_SINGLE_FLOAT,
1434 OPTION_DOUBLE_FLOAT,
1447 OPTION_MVXWORKS_PIC,
1452 struct option md_longopts[] =
1454 /* Options which specify architecture. */
1455 {"march", required_argument, NULL, OPTION_MARCH},
1456 {"mtune", required_argument, NULL, OPTION_MTUNE},
1457 {"mips0", no_argument, NULL, OPTION_MIPS1},
1458 {"mips1", no_argument, NULL, OPTION_MIPS1},
1459 {"mips2", no_argument, NULL, OPTION_MIPS2},
1460 {"mips3", no_argument, NULL, OPTION_MIPS3},
1461 {"mips4", no_argument, NULL, OPTION_MIPS4},
1462 {"mips5", no_argument, NULL, OPTION_MIPS5},
1463 {"mips32", no_argument, NULL, OPTION_MIPS32},
1464 {"mips64", no_argument, NULL, OPTION_MIPS64},
1465 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
1466 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
1468 /* Options which specify Application Specific Extensions (ASEs). */
1469 {"mips16", no_argument, NULL, OPTION_MIPS16},
1470 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
1471 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
1472 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
1473 {"mdmx", no_argument, NULL, OPTION_MDMX},
1474 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
1475 {"mdsp", no_argument, NULL, OPTION_DSP},
1476 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
1477 {"mmt", no_argument, NULL, OPTION_MT},
1478 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
1479 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
1480 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
1481 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
1482 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
1483 {"meva", no_argument, NULL, OPTION_EVA},
1484 {"mno-eva", no_argument, NULL, OPTION_NO_EVA},
1485 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
1486 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
1487 {"mmcu", no_argument, NULL, OPTION_MCU},
1488 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
1489 {"mvirt", no_argument, NULL, OPTION_VIRT},
1490 {"mno-virt", no_argument, NULL, OPTION_NO_VIRT},
1492 /* Old-style architecture options. Don't add more of these. */
1493 {"m4650", no_argument, NULL, OPTION_M4650},
1494 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
1495 {"m4010", no_argument, NULL, OPTION_M4010},
1496 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
1497 {"m4100", no_argument, NULL, OPTION_M4100},
1498 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
1499 {"m3900", no_argument, NULL, OPTION_M3900},
1500 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
1502 /* Options which enable bug fixes. */
1503 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
1504 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1505 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1506 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
1507 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
1508 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
1509 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
1510 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
1511 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
1512 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
1513 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
1514 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
1515 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
1516 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
1517 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
1519 /* Miscellaneous options. */
1520 {"trap", no_argument, NULL, OPTION_TRAP},
1521 {"no-break", no_argument, NULL, OPTION_TRAP},
1522 {"break", no_argument, NULL, OPTION_BREAK},
1523 {"no-trap", no_argument, NULL, OPTION_BREAK},
1524 {"EB", no_argument, NULL, OPTION_EB},
1525 {"EL", no_argument, NULL, OPTION_EL},
1526 {"mfp32", no_argument, NULL, OPTION_FP32},
1527 {"mgp32", no_argument, NULL, OPTION_GP32},
1528 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
1529 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
1530 {"mfp64", no_argument, NULL, OPTION_FP64},
1531 {"mgp64", no_argument, NULL, OPTION_GP64},
1532 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
1533 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
1534 {"minsn32", no_argument, NULL, OPTION_INSN32},
1535 {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32},
1536 {"mshared", no_argument, NULL, OPTION_MSHARED},
1537 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
1538 {"msym32", no_argument, NULL, OPTION_MSYM32},
1539 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
1540 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
1541 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
1542 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
1543 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
1545 /* Strictly speaking this next option is ELF specific,
1546 but we allow it for other ports as well in order to
1547 make testing easier. */
1548 {"32", no_argument, NULL, OPTION_32},
1550 /* ELF-specific options. */
1551 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
1552 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
1553 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
1554 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
1555 {"xgot", no_argument, NULL, OPTION_XGOT},
1556 {"mabi", required_argument, NULL, OPTION_MABI},
1557 {"n32", no_argument, NULL, OPTION_N32},
1558 {"64", no_argument, NULL, OPTION_64},
1559 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
1560 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
1561 {"mpdr", no_argument, NULL, OPTION_PDR},
1562 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
1563 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
1564 {"mnan", required_argument, NULL, OPTION_NAN},
1566 {NULL, no_argument, NULL, 0}
1568 size_t md_longopts_size = sizeof (md_longopts);
1570 /* Information about either an Application Specific Extension or an
1571 optional architecture feature that, for simplicity, we treat in the
1572 same way as an ASE. */
1575 /* The name of the ASE, used in both the command-line and .set options. */
1578 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1579 and 64-bit architectures, the flags here refer to the subset that
1580 is available on both. */
1583 /* The ASE_* flag used for instructions that are available on 64-bit
1584 architectures but that are not included in FLAGS. */
1585 unsigned int flags64;
1587 /* The command-line options that turn the ASE on and off. */
1591 /* The minimum required architecture revisions for MIPS32, MIPS64,
1592 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1595 int micromips32_rev;
1596 int micromips64_rev;
1599 /* A table of all supported ASEs. */
1600 static const struct mips_ase mips_ases[] = {
1601 { "dsp", ASE_DSP, ASE_DSP64,
1602 OPTION_DSP, OPTION_NO_DSP,
1605 { "dspr2", ASE_DSP | ASE_DSPR2, 0,
1606 OPTION_DSPR2, OPTION_NO_DSPR2,
1609 { "eva", ASE_EVA, 0,
1610 OPTION_EVA, OPTION_NO_EVA,
1613 { "mcu", ASE_MCU, 0,
1614 OPTION_MCU, OPTION_NO_MCU,
1617 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1618 { "mdmx", ASE_MDMX, 0,
1619 OPTION_MDMX, OPTION_NO_MDMX,
1622 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1623 { "mips3d", ASE_MIPS3D, 0,
1624 OPTION_MIPS3D, OPTION_NO_MIPS3D,
1628 OPTION_MT, OPTION_NO_MT,
1631 { "smartmips", ASE_SMARTMIPS, 0,
1632 OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS,
1635 { "virt", ASE_VIRT, ASE_VIRT64,
1636 OPTION_VIRT, OPTION_NO_VIRT,
1640 /* The set of ASEs that require -mfp64. */
1641 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX)
1643 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1644 static const unsigned int mips_ase_groups[] = {
1650 The following pseudo-ops from the Kane and Heinrich MIPS book
1651 should be defined here, but are currently unsupported: .alias,
1652 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1654 The following pseudo-ops from the Kane and Heinrich MIPS book are
1655 specific to the type of debugging information being generated, and
1656 should be defined by the object format: .aent, .begin, .bend,
1657 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1660 The following pseudo-ops from the Kane and Heinrich MIPS book are
1661 not MIPS CPU specific, but are also not specific to the object file
1662 format. This file is probably the best place to define them, but
1663 they are not currently supported: .asm0, .endr, .lab, .struct. */
1665 static const pseudo_typeS mips_pseudo_table[] =
1667 /* MIPS specific pseudo-ops. */
1668 {"option", s_option, 0},
1669 {"set", s_mipsset, 0},
1670 {"rdata", s_change_sec, 'r'},
1671 {"sdata", s_change_sec, 's'},
1672 {"livereg", s_ignore, 0},
1673 {"abicalls", s_abicalls, 0},
1674 {"cpload", s_cpload, 0},
1675 {"cpsetup", s_cpsetup, 0},
1676 {"cplocal", s_cplocal, 0},
1677 {"cprestore", s_cprestore, 0},
1678 {"cpreturn", s_cpreturn, 0},
1679 {"dtprelword", s_dtprelword, 0},
1680 {"dtpreldword", s_dtpreldword, 0},
1681 {"tprelword", s_tprelword, 0},
1682 {"tpreldword", s_tpreldword, 0},
1683 {"gpvalue", s_gpvalue, 0},
1684 {"gpword", s_gpword, 0},
1685 {"gpdword", s_gpdword, 0},
1686 {"ehword", s_ehword, 0},
1687 {"cpadd", s_cpadd, 0},
1688 {"insn", s_insn, 0},
1691 /* Relatively generic pseudo-ops that happen to be used on MIPS
1693 {"asciiz", stringer, 8 + 1},
1694 {"bss", s_change_sec, 'b'},
1696 {"half", s_cons, 1},
1697 {"dword", s_cons, 3},
1698 {"weakext", s_mips_weakext, 0},
1699 {"origin", s_org, 0},
1700 {"repeat", s_rept, 0},
1702 /* For MIPS this is non-standard, but we define it for consistency. */
1703 {"sbss", s_change_sec, 'B'},
1705 /* These pseudo-ops are defined in read.c, but must be overridden
1706 here for one reason or another. */
1707 {"align", s_align, 0},
1708 {"byte", s_cons, 0},
1709 {"data", s_change_sec, 'd'},
1710 {"double", s_float_cons, 'd'},
1711 {"float", s_float_cons, 'f'},
1712 {"globl", s_mips_globl, 0},
1713 {"global", s_mips_globl, 0},
1714 {"hword", s_cons, 1},
1716 {"long", s_cons, 2},
1717 {"octa", s_cons, 4},
1718 {"quad", s_cons, 3},
1719 {"section", s_change_section, 0},
1720 {"short", s_cons, 1},
1721 {"single", s_float_cons, 'f'},
1722 {"stabd", s_mips_stab, 'd'},
1723 {"stabn", s_mips_stab, 'n'},
1724 {"stabs", s_mips_stab, 's'},
1725 {"text", s_change_sec, 't'},
1726 {"word", s_cons, 2},
1728 { "extern", ecoff_directive_extern, 0},
1733 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1735 /* These pseudo-ops should be defined by the object file format.
1736 However, a.out doesn't support them, so we have versions here. */
1737 {"aent", s_mips_ent, 1},
1738 {"bgnb", s_ignore, 0},
1739 {"end", s_mips_end, 0},
1740 {"endb", s_ignore, 0},
1741 {"ent", s_mips_ent, 0},
1742 {"file", s_mips_file, 0},
1743 {"fmask", s_mips_mask, 'F'},
1744 {"frame", s_mips_frame, 0},
1745 {"loc", s_mips_loc, 0},
1746 {"mask", s_mips_mask, 'R'},
1747 {"verstamp", s_ignore, 0},
1751 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1752 purpose of the `.dc.a' internal pseudo-op. */
1755 mips_address_bytes (void)
1757 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1760 extern void pop_insert (const pseudo_typeS *);
1763 mips_pop_insert (void)
1765 pop_insert (mips_pseudo_table);
1766 if (! ECOFF_DEBUGGING)
1767 pop_insert (mips_nonecoff_pseudo_table);
1770 /* Symbols labelling the current insn. */
1772 struct insn_label_list
1774 struct insn_label_list *next;
1778 static struct insn_label_list *free_insn_labels;
1779 #define label_list tc_segment_info_data.labels
1781 static void mips_clear_insn_labels (void);
1782 static void mips_mark_labels (void);
1783 static void mips_compressed_mark_labels (void);
1786 mips_clear_insn_labels (void)
1788 register struct insn_label_list **pl;
1789 segment_info_type *si;
1793 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1796 si = seg_info (now_seg);
1797 *pl = si->label_list;
1798 si->label_list = NULL;
1802 /* Mark instruction labels in MIPS16/microMIPS mode. */
1805 mips_mark_labels (void)
1807 if (HAVE_CODE_COMPRESSION)
1808 mips_compressed_mark_labels ();
1811 static char *expr_end;
1813 /* Expressions which appear in instructions. These are set by
1816 static expressionS imm_expr;
1817 static expressionS imm2_expr;
1818 static expressionS offset_expr;
1820 /* Relocs associated with imm_expr and offset_expr. */
1822 static bfd_reloc_code_real_type imm_reloc[3]
1823 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1824 static bfd_reloc_code_real_type offset_reloc[3]
1825 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1827 /* This is set to the resulting size of the instruction to be produced
1828 by mips16_ip if an explicit extension is used or by mips_ip if an
1829 explicit size is supplied. */
1831 static unsigned int forced_insn_length;
1833 /* True if we are assembling an instruction. All dot symbols defined during
1834 this time should be treated as code labels. */
1836 static bfd_boolean mips_assembling_insn;
1838 /* The pdr segment for per procedure frame/regmask info. Not used for
1841 static segT pdr_seg;
1843 /* The default target format to use. */
1845 #if defined (TE_FreeBSD)
1846 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1847 #elif defined (TE_TMIPS)
1848 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1850 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1854 mips_target_format (void)
1856 switch (OUTPUT_FLAVOR)
1858 case bfd_target_elf_flavour:
1860 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1861 return (target_big_endian
1862 ? "elf32-bigmips-vxworks"
1863 : "elf32-littlemips-vxworks");
1865 return (target_big_endian
1866 ? (HAVE_64BIT_OBJECTS
1867 ? ELF_TARGET ("elf64-", "big")
1869 ? ELF_TARGET ("elf32-n", "big")
1870 : ELF_TARGET ("elf32-", "big")))
1871 : (HAVE_64BIT_OBJECTS
1872 ? ELF_TARGET ("elf64-", "little")
1874 ? ELF_TARGET ("elf32-n", "little")
1875 : ELF_TARGET ("elf32-", "little"))));
1882 /* Return the ISA revision that is currently in use, or 0 if we are
1883 generating code for MIPS V or below. */
1888 if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2)
1891 /* microMIPS implies revision 2 or above. */
1892 if (mips_opts.micromips)
1895 if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64)
1901 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1904 mips_ase_mask (unsigned int flags)
1908 for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++)
1909 if (flags & mips_ase_groups[i])
1910 flags |= mips_ase_groups[i];
1914 /* Check whether the current ISA supports ASE. Issue a warning if
1918 mips_check_isa_supports_ase (const struct mips_ase *ase)
1922 static unsigned int warned_isa;
1923 static unsigned int warned_fp32;
1925 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
1926 min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev;
1928 min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev;
1929 if ((min_rev < 0 || mips_isa_rev () < min_rev)
1930 && (warned_isa & ase->flags) != ase->flags)
1932 warned_isa |= ase->flags;
1933 base = mips_opts.micromips ? "microMIPS" : "MIPS";
1934 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
1936 as_warn (_("The %d-bit %s architecture does not support the"
1937 " `%s' extension"), size, base, ase->name);
1939 as_warn (_("The `%s' extension requires %s%d revision %d or greater"),
1940 ase->name, base, size, min_rev);
1942 if ((ase->flags & FP64_ASES)
1944 && (warned_fp32 & ase->flags) != ase->flags)
1946 warned_fp32 |= ase->flags;
1947 as_warn (_("The `%s' extension requires 64-bit FPRs"), ase->name);
1951 /* Check all enabled ASEs to see whether they are supported by the
1952 chosen architecture. */
1955 mips_check_isa_supports_ases (void)
1957 unsigned int i, mask;
1959 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
1961 mask = mips_ase_mask (mips_ases[i].flags);
1962 if ((mips_opts.ase & mask) == mips_ases[i].flags)
1963 mips_check_isa_supports_ase (&mips_ases[i]);
1967 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
1968 that were affected. */
1971 mips_set_ase (const struct mips_ase *ase, bfd_boolean enabled_p)
1975 mask = mips_ase_mask (ase->flags);
1976 mips_opts.ase &= ~mask;
1978 mips_opts.ase |= ase->flags;
1982 /* Return the ASE called NAME, or null if none. */
1984 static const struct mips_ase *
1985 mips_lookup_ase (const char *name)
1989 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
1990 if (strcmp (name, mips_ases[i].name) == 0)
1991 return &mips_ases[i];
1995 /* Return the length of a microMIPS instruction in bytes. If bits of
1996 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1997 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1998 major opcode) will require further modifications to the opcode
2001 static inline unsigned int
2002 micromips_insn_length (const struct mips_opcode *mo)
2004 return (mo->mask >> 16) == 0 ? 2 : 4;
2007 /* Return the length of MIPS16 instruction OPCODE. */
2009 static inline unsigned int
2010 mips16_opcode_length (unsigned long opcode)
2012 return (opcode >> 16) == 0 ? 2 : 4;
2015 /* Return the length of instruction INSN. */
2017 static inline unsigned int
2018 insn_length (const struct mips_cl_insn *insn)
2020 if (mips_opts.micromips)
2021 return micromips_insn_length (insn->insn_mo);
2022 else if (mips_opts.mips16)
2023 return mips16_opcode_length (insn->insn_opcode);
2028 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2031 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
2036 insn->insn_opcode = mo->match;
2039 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2040 insn->fixp[i] = NULL;
2041 insn->fixed_p = (mips_opts.noreorder > 0);
2042 insn->noreorder_p = (mips_opts.noreorder > 0);
2043 insn->mips16_absolute_jump_p = 0;
2044 insn->complete_p = 0;
2045 insn->cleared_p = 0;
2048 /* Record the current MIPS16/microMIPS mode in now_seg. */
2051 mips_record_compressed_mode (void)
2053 segment_info_type *si;
2055 si = seg_info (now_seg);
2056 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
2057 si->tc_segment_info_data.mips16 = mips_opts.mips16;
2058 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
2059 si->tc_segment_info_data.micromips = mips_opts.micromips;
2062 /* Read a standard MIPS instruction from BUF. */
2064 static unsigned long
2065 read_insn (char *buf)
2067 if (target_big_endian)
2068 return bfd_getb32 ((bfd_byte *) buf);
2070 return bfd_getl32 ((bfd_byte *) buf);
2073 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2077 write_insn (char *buf, unsigned int insn)
2079 md_number_to_chars (buf, insn, 4);
2083 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2084 has length LENGTH. */
2086 static unsigned long
2087 read_compressed_insn (char *buf, unsigned int length)
2093 for (i = 0; i < length; i += 2)
2096 if (target_big_endian)
2097 insn |= bfd_getb16 ((char *) buf);
2099 insn |= bfd_getl16 ((char *) buf);
2105 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2106 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2109 write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
2113 for (i = 0; i < length; i += 2)
2114 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
2115 return buf + length;
2118 /* Install INSN at the location specified by its "frag" and "where" fields. */
2121 install_insn (const struct mips_cl_insn *insn)
2123 char *f = insn->frag->fr_literal + insn->where;
2124 if (HAVE_CODE_COMPRESSION)
2125 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
2127 write_insn (f, insn->insn_opcode);
2128 mips_record_compressed_mode ();
2131 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2132 and install the opcode in the new location. */
2135 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
2140 insn->where = where;
2141 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2142 if (insn->fixp[i] != NULL)
2144 insn->fixp[i]->fx_frag = frag;
2145 insn->fixp[i]->fx_where = where;
2147 install_insn (insn);
2150 /* Add INSN to the end of the output. */
2153 add_fixed_insn (struct mips_cl_insn *insn)
2155 char *f = frag_more (insn_length (insn));
2156 move_insn (insn, frag_now, f - frag_now->fr_literal);
2159 /* Start a variant frag and move INSN to the start of the variant part,
2160 marking it as fixed. The other arguments are as for frag_var. */
2163 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
2164 relax_substateT subtype, symbolS *symbol, offsetT offset)
2166 frag_grow (max_chars);
2167 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
2169 frag_var (rs_machine_dependent, max_chars, var,
2170 subtype, symbol, offset, NULL);
2173 /* Insert N copies of INSN into the history buffer, starting at
2174 position FIRST. Neither FIRST nor N need to be clipped. */
2177 insert_into_history (unsigned int first, unsigned int n,
2178 const struct mips_cl_insn *insn)
2180 if (mips_relax.sequence != 2)
2184 for (i = ARRAY_SIZE (history); i-- > first;)
2186 history[i] = history[i - n];
2192 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2193 the idea is to make it obvious at a glance that each errata is
2197 init_vr4120_conflicts (void)
2199 #define CONFLICT(FIRST, SECOND) \
2200 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2202 /* Errata 21 - [D]DIV[U] after [D]MACC */
2203 CONFLICT (MACC, DIV);
2204 CONFLICT (DMACC, DIV);
2206 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2207 CONFLICT (DMULT, DMULT);
2208 CONFLICT (DMULT, DMACC);
2209 CONFLICT (DMACC, DMULT);
2210 CONFLICT (DMACC, DMACC);
2212 /* Errata 24 - MT{LO,HI} after [D]MACC */
2213 CONFLICT (MACC, MTHILO);
2214 CONFLICT (DMACC, MTHILO);
2216 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2217 instruction is executed immediately after a MACC or DMACC
2218 instruction, the result of [either instruction] is incorrect." */
2219 CONFLICT (MACC, MULT);
2220 CONFLICT (MACC, DMULT);
2221 CONFLICT (DMACC, MULT);
2222 CONFLICT (DMACC, DMULT);
2224 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2225 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2226 DDIV or DDIVU instruction, the result of the MACC or
2227 DMACC instruction is incorrect.". */
2228 CONFLICT (DMULT, MACC);
2229 CONFLICT (DMULT, DMACC);
2230 CONFLICT (DIV, MACC);
2231 CONFLICT (DIV, DMACC);
2241 #define RTYPE_MASK 0x1ff00
2242 #define RTYPE_NUM 0x00100
2243 #define RTYPE_FPU 0x00200
2244 #define RTYPE_FCC 0x00400
2245 #define RTYPE_VEC 0x00800
2246 #define RTYPE_GP 0x01000
2247 #define RTYPE_CP0 0x02000
2248 #define RTYPE_PC 0x04000
2249 #define RTYPE_ACC 0x08000
2250 #define RTYPE_CCC 0x10000
2251 #define RNUM_MASK 0x000ff
2252 #define RWARN 0x80000
2254 #define GENERIC_REGISTER_NUMBERS \
2255 {"$0", RTYPE_NUM | 0}, \
2256 {"$1", RTYPE_NUM | 1}, \
2257 {"$2", RTYPE_NUM | 2}, \
2258 {"$3", RTYPE_NUM | 3}, \
2259 {"$4", RTYPE_NUM | 4}, \
2260 {"$5", RTYPE_NUM | 5}, \
2261 {"$6", RTYPE_NUM | 6}, \
2262 {"$7", RTYPE_NUM | 7}, \
2263 {"$8", RTYPE_NUM | 8}, \
2264 {"$9", RTYPE_NUM | 9}, \
2265 {"$10", RTYPE_NUM | 10}, \
2266 {"$11", RTYPE_NUM | 11}, \
2267 {"$12", RTYPE_NUM | 12}, \
2268 {"$13", RTYPE_NUM | 13}, \
2269 {"$14", RTYPE_NUM | 14}, \
2270 {"$15", RTYPE_NUM | 15}, \
2271 {"$16", RTYPE_NUM | 16}, \
2272 {"$17", RTYPE_NUM | 17}, \
2273 {"$18", RTYPE_NUM | 18}, \
2274 {"$19", RTYPE_NUM | 19}, \
2275 {"$20", RTYPE_NUM | 20}, \
2276 {"$21", RTYPE_NUM | 21}, \
2277 {"$22", RTYPE_NUM | 22}, \
2278 {"$23", RTYPE_NUM | 23}, \
2279 {"$24", RTYPE_NUM | 24}, \
2280 {"$25", RTYPE_NUM | 25}, \
2281 {"$26", RTYPE_NUM | 26}, \
2282 {"$27", RTYPE_NUM | 27}, \
2283 {"$28", RTYPE_NUM | 28}, \
2284 {"$29", RTYPE_NUM | 29}, \
2285 {"$30", RTYPE_NUM | 30}, \
2286 {"$31", RTYPE_NUM | 31}
2288 #define FPU_REGISTER_NAMES \
2289 {"$f0", RTYPE_FPU | 0}, \
2290 {"$f1", RTYPE_FPU | 1}, \
2291 {"$f2", RTYPE_FPU | 2}, \
2292 {"$f3", RTYPE_FPU | 3}, \
2293 {"$f4", RTYPE_FPU | 4}, \
2294 {"$f5", RTYPE_FPU | 5}, \
2295 {"$f6", RTYPE_FPU | 6}, \
2296 {"$f7", RTYPE_FPU | 7}, \
2297 {"$f8", RTYPE_FPU | 8}, \
2298 {"$f9", RTYPE_FPU | 9}, \
2299 {"$f10", RTYPE_FPU | 10}, \
2300 {"$f11", RTYPE_FPU | 11}, \
2301 {"$f12", RTYPE_FPU | 12}, \
2302 {"$f13", RTYPE_FPU | 13}, \
2303 {"$f14", RTYPE_FPU | 14}, \
2304 {"$f15", RTYPE_FPU | 15}, \
2305 {"$f16", RTYPE_FPU | 16}, \
2306 {"$f17", RTYPE_FPU | 17}, \
2307 {"$f18", RTYPE_FPU | 18}, \
2308 {"$f19", RTYPE_FPU | 19}, \
2309 {"$f20", RTYPE_FPU | 20}, \
2310 {"$f21", RTYPE_FPU | 21}, \
2311 {"$f22", RTYPE_FPU | 22}, \
2312 {"$f23", RTYPE_FPU | 23}, \
2313 {"$f24", RTYPE_FPU | 24}, \
2314 {"$f25", RTYPE_FPU | 25}, \
2315 {"$f26", RTYPE_FPU | 26}, \
2316 {"$f27", RTYPE_FPU | 27}, \
2317 {"$f28", RTYPE_FPU | 28}, \
2318 {"$f29", RTYPE_FPU | 29}, \
2319 {"$f30", RTYPE_FPU | 30}, \
2320 {"$f31", RTYPE_FPU | 31}
2322 #define FPU_CONDITION_CODE_NAMES \
2323 {"$fcc0", RTYPE_FCC | 0}, \
2324 {"$fcc1", RTYPE_FCC | 1}, \
2325 {"$fcc2", RTYPE_FCC | 2}, \
2326 {"$fcc3", RTYPE_FCC | 3}, \
2327 {"$fcc4", RTYPE_FCC | 4}, \
2328 {"$fcc5", RTYPE_FCC | 5}, \
2329 {"$fcc6", RTYPE_FCC | 6}, \
2330 {"$fcc7", RTYPE_FCC | 7}
2332 #define COPROC_CONDITION_CODE_NAMES \
2333 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2334 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2335 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2336 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2337 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2338 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2339 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2340 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2342 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2343 {"$a4", RTYPE_GP | 8}, \
2344 {"$a5", RTYPE_GP | 9}, \
2345 {"$a6", RTYPE_GP | 10}, \
2346 {"$a7", RTYPE_GP | 11}, \
2347 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2348 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2349 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2350 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2351 {"$t0", RTYPE_GP | 12}, \
2352 {"$t1", RTYPE_GP | 13}, \
2353 {"$t2", RTYPE_GP | 14}, \
2354 {"$t3", RTYPE_GP | 15}
2356 #define O32_SYMBOLIC_REGISTER_NAMES \
2357 {"$t0", RTYPE_GP | 8}, \
2358 {"$t1", RTYPE_GP | 9}, \
2359 {"$t2", RTYPE_GP | 10}, \
2360 {"$t3", RTYPE_GP | 11}, \
2361 {"$t4", RTYPE_GP | 12}, \
2362 {"$t5", RTYPE_GP | 13}, \
2363 {"$t6", RTYPE_GP | 14}, \
2364 {"$t7", RTYPE_GP | 15}, \
2365 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2366 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2367 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2368 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2370 /* Remaining symbolic register names */
2371 #define SYMBOLIC_REGISTER_NAMES \
2372 {"$zero", RTYPE_GP | 0}, \
2373 {"$at", RTYPE_GP | 1}, \
2374 {"$AT", RTYPE_GP | 1}, \
2375 {"$v0", RTYPE_GP | 2}, \
2376 {"$v1", RTYPE_GP | 3}, \
2377 {"$a0", RTYPE_GP | 4}, \
2378 {"$a1", RTYPE_GP | 5}, \
2379 {"$a2", RTYPE_GP | 6}, \
2380 {"$a3", RTYPE_GP | 7}, \
2381 {"$s0", RTYPE_GP | 16}, \
2382 {"$s1", RTYPE_GP | 17}, \
2383 {"$s2", RTYPE_GP | 18}, \
2384 {"$s3", RTYPE_GP | 19}, \
2385 {"$s4", RTYPE_GP | 20}, \
2386 {"$s5", RTYPE_GP | 21}, \
2387 {"$s6", RTYPE_GP | 22}, \
2388 {"$s7", RTYPE_GP | 23}, \
2389 {"$t8", RTYPE_GP | 24}, \
2390 {"$t9", RTYPE_GP | 25}, \
2391 {"$k0", RTYPE_GP | 26}, \
2392 {"$kt0", RTYPE_GP | 26}, \
2393 {"$k1", RTYPE_GP | 27}, \
2394 {"$kt1", RTYPE_GP | 27}, \
2395 {"$gp", RTYPE_GP | 28}, \
2396 {"$sp", RTYPE_GP | 29}, \
2397 {"$s8", RTYPE_GP | 30}, \
2398 {"$fp", RTYPE_GP | 30}, \
2399 {"$ra", RTYPE_GP | 31}
2401 #define MIPS16_SPECIAL_REGISTER_NAMES \
2402 {"$pc", RTYPE_PC | 0}
2404 #define MDMX_VECTOR_REGISTER_NAMES \
2405 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2406 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2407 {"$v2", RTYPE_VEC | 2}, \
2408 {"$v3", RTYPE_VEC | 3}, \
2409 {"$v4", RTYPE_VEC | 4}, \
2410 {"$v5", RTYPE_VEC | 5}, \
2411 {"$v6", RTYPE_VEC | 6}, \
2412 {"$v7", RTYPE_VEC | 7}, \
2413 {"$v8", RTYPE_VEC | 8}, \
2414 {"$v9", RTYPE_VEC | 9}, \
2415 {"$v10", RTYPE_VEC | 10}, \
2416 {"$v11", RTYPE_VEC | 11}, \
2417 {"$v12", RTYPE_VEC | 12}, \
2418 {"$v13", RTYPE_VEC | 13}, \
2419 {"$v14", RTYPE_VEC | 14}, \
2420 {"$v15", RTYPE_VEC | 15}, \
2421 {"$v16", RTYPE_VEC | 16}, \
2422 {"$v17", RTYPE_VEC | 17}, \
2423 {"$v18", RTYPE_VEC | 18}, \
2424 {"$v19", RTYPE_VEC | 19}, \
2425 {"$v20", RTYPE_VEC | 20}, \
2426 {"$v21", RTYPE_VEC | 21}, \
2427 {"$v22", RTYPE_VEC | 22}, \
2428 {"$v23", RTYPE_VEC | 23}, \
2429 {"$v24", RTYPE_VEC | 24}, \
2430 {"$v25", RTYPE_VEC | 25}, \
2431 {"$v26", RTYPE_VEC | 26}, \
2432 {"$v27", RTYPE_VEC | 27}, \
2433 {"$v28", RTYPE_VEC | 28}, \
2434 {"$v29", RTYPE_VEC | 29}, \
2435 {"$v30", RTYPE_VEC | 30}, \
2436 {"$v31", RTYPE_VEC | 31}
2438 #define MIPS_DSP_ACCUMULATOR_NAMES \
2439 {"$ac0", RTYPE_ACC | 0}, \
2440 {"$ac1", RTYPE_ACC | 1}, \
2441 {"$ac2", RTYPE_ACC | 2}, \
2442 {"$ac3", RTYPE_ACC | 3}
2444 static const struct regname reg_names[] = {
2445 GENERIC_REGISTER_NUMBERS,
2447 FPU_CONDITION_CODE_NAMES,
2448 COPROC_CONDITION_CODE_NAMES,
2450 /* The $txx registers depends on the abi,
2451 these will be added later into the symbol table from
2452 one of the tables below once mips_abi is set after
2453 parsing of arguments from the command line. */
2454 SYMBOLIC_REGISTER_NAMES,
2456 MIPS16_SPECIAL_REGISTER_NAMES,
2457 MDMX_VECTOR_REGISTER_NAMES,
2458 MIPS_DSP_ACCUMULATOR_NAMES,
2462 static const struct regname reg_names_o32[] = {
2463 O32_SYMBOLIC_REGISTER_NAMES,
2467 static const struct regname reg_names_n32n64[] = {
2468 N32N64_SYMBOLIC_REGISTER_NAMES,
2472 /* Check if S points at a valid register specifier according to TYPES.
2473 If so, then return 1, advance S to consume the specifier and store
2474 the register's number in REGNOP, otherwise return 0. */
2477 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2484 /* Find end of name. */
2486 if (is_name_beginner (*e))
2488 while (is_part_of_name (*e))
2491 /* Terminate name. */
2495 /* Look for a register symbol. */
2496 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
2498 int r = S_GET_VALUE (symbolP);
2500 reg = r & RNUM_MASK;
2501 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
2502 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2503 reg = (r & RNUM_MASK) - 2;
2505 /* Else see if this is a register defined in an itbl entry. */
2506 else if ((types & RTYPE_GP) && itbl_have_entries)
2513 if (itbl_get_reg_val (n, &r))
2514 reg = r & RNUM_MASK;
2517 /* Advance to next token if a register was recognised. */
2520 else if (types & RWARN)
2521 as_warn (_("Unrecognized register name `%s'"), *s);
2529 /* Check if S points at a valid register list according to TYPES.
2530 If so, then return 1, advance S to consume the list and store
2531 the registers present on the list as a bitmask of ones in REGLISTP,
2532 otherwise return 0. A valid list comprises a comma-separated
2533 enumeration of valid single registers and/or dash-separated
2534 contiguous register ranges as determined by their numbers.
2536 As a special exception if one of s0-s7 registers is specified as
2537 the range's lower delimiter and s8 (fp) is its upper one, then no
2538 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2539 are selected; they have to be listed separately if needed. */
2542 reglist_lookup (char **s, unsigned int types, unsigned int *reglistp)
2544 unsigned int reglist = 0;
2545 unsigned int lastregno;
2546 bfd_boolean ok = TRUE;
2547 unsigned int regmask;
2548 char *s_endlist = *s;
2552 while (reg_lookup (s, types, ®no))
2558 ok = reg_lookup (s, types, &lastregno);
2559 if (ok && lastregno < regno)
2565 if (lastregno == FP && regno >= S0 && regno <= S7)
2570 regmask = 1 << lastregno;
2571 regmask = (regmask << 1) - 1;
2572 regmask ^= (1 << regno) - 1;
2586 *reglistp = reglist;
2587 return ok && reglist != 0;
2591 mips_lookup_reg_pair (unsigned int regno1, unsigned int regno2,
2592 const unsigned int *map1, const unsigned int *map2,
2597 for (i = 0; i < count; i++)
2598 if (map1[i] == regno1 && map2[i] == regno2)
2603 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
2604 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2607 is_opcode_valid (const struct mips_opcode *mo)
2609 int isa = mips_opts.isa;
2610 int ase = mips_opts.ase;
2614 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
2615 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2616 if ((ase & mips_ases[i].flags) == mips_ases[i].flags)
2617 ase |= mips_ases[i].flags64;
2619 if (!opcode_is_member (mo, isa, ase, mips_opts.arch))
2622 /* Check whether the instruction or macro requires single-precision or
2623 double-precision floating-point support. Note that this information is
2624 stored differently in the opcode table for insns and macros. */
2625 if (mo->pinfo == INSN_MACRO)
2627 fp_s = mo->pinfo2 & INSN2_M_FP_S;
2628 fp_d = mo->pinfo2 & INSN2_M_FP_D;
2632 fp_s = mo->pinfo & FP_S;
2633 fp_d = mo->pinfo & FP_D;
2636 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
2639 if (fp_s && mips_opts.soft_float)
2645 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2646 selected ISA and architecture. */
2649 is_opcode_valid_16 (const struct mips_opcode *mo)
2651 return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch);
2654 /* Return TRUE if the size of the microMIPS opcode MO matches one
2655 explicitly requested. Always TRUE in the standard MIPS mode. */
2658 is_size_valid (const struct mips_opcode *mo)
2660 if (!mips_opts.micromips)
2663 if (mips_opts.insn32)
2665 if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4)
2667 if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0)
2670 if (!forced_insn_length)
2672 if (mo->pinfo == INSN_MACRO)
2674 return forced_insn_length == micromips_insn_length (mo);
2677 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2678 of the preceding instruction. Always TRUE in the standard MIPS mode.
2680 We don't accept macros in 16-bit delay slots to avoid a case where
2681 a macro expansion fails because it relies on a preceding 32-bit real
2682 instruction to have matched and does not handle the operands correctly.
2683 The only macros that may expand to 16-bit instructions are JAL that
2684 cannot be placed in a delay slot anyway, and corner cases of BALIGN
2685 and BGT (that likewise cannot be placed in a delay slot) that decay to
2686 a NOP. In all these cases the macros precede any corresponding real
2687 instruction definitions in the opcode table, so they will match in the
2688 second pass where the size of the delay slot is ignored and therefore
2689 produce correct code. */
2692 is_delay_slot_valid (const struct mips_opcode *mo)
2694 if (!mips_opts.micromips)
2697 if (mo->pinfo == INSN_MACRO)
2698 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0;
2699 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
2700 && micromips_insn_length (mo) != 4)
2702 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
2703 && micromips_insn_length (mo) != 2)
2709 /* This function is called once, at assembler startup time. It should set up
2710 all the tables, etc. that the MD part of the assembler will need. */
2715 const char *retval = NULL;
2719 if (mips_pic != NO_PIC)
2721 if (g_switch_seen && g_switch_value != 0)
2722 as_bad (_("-G may not be used in position-independent code"));
2726 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
2727 as_warn (_("Could not set architecture and machine"));
2729 op_hash = hash_new ();
2731 for (i = 0; i < NUMOPCODES;)
2733 const char *name = mips_opcodes[i].name;
2735 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
2738 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
2739 mips_opcodes[i].name, retval);
2740 /* Probably a memory allocation problem? Give up now. */
2741 as_fatal (_("Broken assembler. No assembly attempted."));
2745 if (mips_opcodes[i].pinfo != INSN_MACRO)
2747 if (!validate_mips_insn (&mips_opcodes[i]))
2749 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2751 create_insn (&nop_insn, mips_opcodes + i);
2752 if (mips_fix_loongson2f_nop)
2753 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
2754 nop_insn.fixed_p = 1;
2759 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
2762 mips16_op_hash = hash_new ();
2765 while (i < bfd_mips16_num_opcodes)
2767 const char *name = mips16_opcodes[i].name;
2769 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
2771 as_fatal (_("internal: can't hash `%s': %s"),
2772 mips16_opcodes[i].name, retval);
2775 if (mips16_opcodes[i].pinfo != INSN_MACRO
2776 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
2777 != mips16_opcodes[i].match))
2779 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
2780 mips16_opcodes[i].name, mips16_opcodes[i].args);
2783 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2785 create_insn (&mips16_nop_insn, mips16_opcodes + i);
2786 mips16_nop_insn.fixed_p = 1;
2790 while (i < bfd_mips16_num_opcodes
2791 && strcmp (mips16_opcodes[i].name, name) == 0);
2794 micromips_op_hash = hash_new ();
2797 while (i < bfd_micromips_num_opcodes)
2799 const char *name = micromips_opcodes[i].name;
2801 retval = hash_insert (micromips_op_hash, name,
2802 (void *) µmips_opcodes[i]);
2804 as_fatal (_("internal: can't hash `%s': %s"),
2805 micromips_opcodes[i].name, retval);
2807 if (micromips_opcodes[i].pinfo != INSN_MACRO)
2809 struct mips_cl_insn *micromips_nop_insn;
2811 if (!validate_micromips_insn (µmips_opcodes[i]))
2814 if (micromips_insn_length (micromips_opcodes + i) == 2)
2815 micromips_nop_insn = µmips_nop16_insn;
2816 else if (micromips_insn_length (micromips_opcodes + i) == 4)
2817 micromips_nop_insn = µmips_nop32_insn;
2821 if (micromips_nop_insn->insn_mo == NULL
2822 && strcmp (name, "nop") == 0)
2824 create_insn (micromips_nop_insn, micromips_opcodes + i);
2825 micromips_nop_insn->fixed_p = 1;
2828 while (++i < bfd_micromips_num_opcodes
2829 && strcmp (micromips_opcodes[i].name, name) == 0);
2833 as_fatal (_("Broken assembler. No assembly attempted."));
2835 /* We add all the general register names to the symbol table. This
2836 helps us detect invalid uses of them. */
2837 for (i = 0; reg_names[i].name; i++)
2838 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
2839 reg_names[i].num, /* & RNUM_MASK, */
2840 &zero_address_frag));
2842 for (i = 0; reg_names_n32n64[i].name; i++)
2843 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
2844 reg_names_n32n64[i].num, /* & RNUM_MASK, */
2845 &zero_address_frag));
2847 for (i = 0; reg_names_o32[i].name; i++)
2848 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
2849 reg_names_o32[i].num, /* & RNUM_MASK, */
2850 &zero_address_frag));
2852 mips_no_prev_insn ();
2855 mips_cprmask[0] = 0;
2856 mips_cprmask[1] = 0;
2857 mips_cprmask[2] = 0;
2858 mips_cprmask[3] = 0;
2860 /* set the default alignment for the text section (2**2) */
2861 record_alignment (text_section, 2);
2863 bfd_set_gp_size (stdoutput, g_switch_value);
2865 /* On a native system other than VxWorks, sections must be aligned
2866 to 16 byte boundaries. When configured for an embedded ELF
2867 target, we don't bother. */
2868 if (strncmp (TARGET_OS, "elf", 3) != 0
2869 && strncmp (TARGET_OS, "vxworks", 7) != 0)
2871 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
2872 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
2873 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
2876 /* Create a .reginfo section for register masks and a .mdebug
2877 section for debugging information. */
2885 subseg = now_subseg;
2887 /* The ABI says this section should be loaded so that the
2888 running program can access it. However, we don't load it
2889 if we are configured for an embedded target */
2890 flags = SEC_READONLY | SEC_DATA;
2891 if (strncmp (TARGET_OS, "elf", 3) != 0)
2892 flags |= SEC_ALLOC | SEC_LOAD;
2894 if (mips_abi != N64_ABI)
2896 sec = subseg_new (".reginfo", (subsegT) 0);
2898 bfd_set_section_flags (stdoutput, sec, flags);
2899 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
2901 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
2905 /* The 64-bit ABI uses a .MIPS.options section rather than
2906 .reginfo section. */
2907 sec = subseg_new (".MIPS.options", (subsegT) 0);
2908 bfd_set_section_flags (stdoutput, sec, flags);
2909 bfd_set_section_alignment (stdoutput, sec, 3);
2911 /* Set up the option header. */
2913 Elf_Internal_Options opthdr;
2916 opthdr.kind = ODK_REGINFO;
2917 opthdr.size = (sizeof (Elf_External_Options)
2918 + sizeof (Elf64_External_RegInfo));
2921 f = frag_more (sizeof (Elf_External_Options));
2922 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2923 (Elf_External_Options *) f);
2925 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2929 if (ECOFF_DEBUGGING)
2931 sec = subseg_new (".mdebug", (subsegT) 0);
2932 (void) bfd_set_section_flags (stdoutput, sec,
2933 SEC_HAS_CONTENTS | SEC_READONLY);
2934 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2936 else if (mips_flag_pdr)
2938 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2939 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2940 SEC_READONLY | SEC_RELOC
2942 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2945 subseg_set (seg, subseg);
2948 if (! ECOFF_DEBUGGING)
2951 if (mips_fix_vr4120)
2952 init_vr4120_conflicts ();
2958 mips_emit_delays ();
2959 if (! ECOFF_DEBUGGING)
2964 md_assemble (char *str)
2966 struct mips_cl_insn insn;
2967 bfd_reloc_code_real_type unused_reloc[3]
2968 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2970 imm_expr.X_op = O_absent;
2971 imm2_expr.X_op = O_absent;
2972 offset_expr.X_op = O_absent;
2973 imm_reloc[0] = BFD_RELOC_UNUSED;
2974 imm_reloc[1] = BFD_RELOC_UNUSED;
2975 imm_reloc[2] = BFD_RELOC_UNUSED;
2976 offset_reloc[0] = BFD_RELOC_UNUSED;
2977 offset_reloc[1] = BFD_RELOC_UNUSED;
2978 offset_reloc[2] = BFD_RELOC_UNUSED;
2980 mips_mark_labels ();
2981 mips_assembling_insn = TRUE;
2983 if (mips_opts.mips16)
2984 mips16_ip (str, &insn);
2987 mips_ip (str, &insn);
2988 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2989 str, insn.insn_opcode));
2993 as_bad ("%s `%s'", insn_error, str);
2994 else if (insn.insn_mo->pinfo == INSN_MACRO)
2997 if (mips_opts.mips16)
2998 mips16_macro (&insn);
3005 if (imm_expr.X_op != O_absent)
3006 append_insn (&insn, &imm_expr, imm_reloc, FALSE);
3007 else if (offset_expr.X_op != O_absent)
3008 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
3010 append_insn (&insn, NULL, unused_reloc, FALSE);
3013 mips_assembling_insn = FALSE;
3016 /* Convenience functions for abstracting away the differences between
3017 MIPS16 and non-MIPS16 relocations. */
3019 static inline bfd_boolean
3020 mips16_reloc_p (bfd_reloc_code_real_type reloc)
3024 case BFD_RELOC_MIPS16_JMP:
3025 case BFD_RELOC_MIPS16_GPREL:
3026 case BFD_RELOC_MIPS16_GOT16:
3027 case BFD_RELOC_MIPS16_CALL16:
3028 case BFD_RELOC_MIPS16_HI16_S:
3029 case BFD_RELOC_MIPS16_HI16:
3030 case BFD_RELOC_MIPS16_LO16:
3038 static inline bfd_boolean
3039 micromips_reloc_p (bfd_reloc_code_real_type reloc)
3043 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
3044 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
3045 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
3046 case BFD_RELOC_MICROMIPS_GPREL16:
3047 case BFD_RELOC_MICROMIPS_JMP:
3048 case BFD_RELOC_MICROMIPS_HI16:
3049 case BFD_RELOC_MICROMIPS_HI16_S:
3050 case BFD_RELOC_MICROMIPS_LO16:
3051 case BFD_RELOC_MICROMIPS_LITERAL:
3052 case BFD_RELOC_MICROMIPS_GOT16:
3053 case BFD_RELOC_MICROMIPS_CALL16:
3054 case BFD_RELOC_MICROMIPS_GOT_HI16:
3055 case BFD_RELOC_MICROMIPS_GOT_LO16:
3056 case BFD_RELOC_MICROMIPS_CALL_HI16:
3057 case BFD_RELOC_MICROMIPS_CALL_LO16:
3058 case BFD_RELOC_MICROMIPS_SUB:
3059 case BFD_RELOC_MICROMIPS_GOT_PAGE:
3060 case BFD_RELOC_MICROMIPS_GOT_OFST:
3061 case BFD_RELOC_MICROMIPS_GOT_DISP:
3062 case BFD_RELOC_MICROMIPS_HIGHEST:
3063 case BFD_RELOC_MICROMIPS_HIGHER:
3064 case BFD_RELOC_MICROMIPS_SCN_DISP:
3065 case BFD_RELOC_MICROMIPS_JALR:
3073 static inline bfd_boolean
3074 jmp_reloc_p (bfd_reloc_code_real_type reloc)
3076 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
3079 static inline bfd_boolean
3080 got16_reloc_p (bfd_reloc_code_real_type reloc)
3082 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
3083 || reloc == BFD_RELOC_MICROMIPS_GOT16);
3086 static inline bfd_boolean
3087 hi16_reloc_p (bfd_reloc_code_real_type reloc)
3089 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
3090 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
3093 static inline bfd_boolean
3094 lo16_reloc_p (bfd_reloc_code_real_type reloc)
3096 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
3097 || reloc == BFD_RELOC_MICROMIPS_LO16);
3100 static inline bfd_boolean
3101 jalr_reloc_p (bfd_reloc_code_real_type reloc)
3103 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
3106 static inline bfd_boolean
3107 gprel16_reloc_p (bfd_reloc_code_real_type reloc)
3109 return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL
3110 || reloc == BFD_RELOC_MICROMIPS_GPREL16);
3113 /* Return true if RELOC is a PC-relative relocation that does not have
3114 full address range. */
3116 static inline bfd_boolean
3117 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc)
3121 case BFD_RELOC_16_PCREL_S2:
3122 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
3123 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
3124 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
3127 case BFD_RELOC_32_PCREL:
3128 return HAVE_64BIT_ADDRESSES;
3135 /* Return true if the given relocation might need a matching %lo().
3136 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
3137 need a matching %lo() when applied to local symbols. */
3139 static inline bfd_boolean
3140 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
3142 return (HAVE_IN_PLACE_ADDENDS
3143 && (hi16_reloc_p (reloc)
3144 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
3145 all GOT16 relocations evaluate to "G". */
3146 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
3149 /* Return the type of %lo() reloc needed by RELOC, given that
3150 reloc_needs_lo_p. */
3152 static inline bfd_reloc_code_real_type
3153 matching_lo_reloc (bfd_reloc_code_real_type reloc)
3155 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
3156 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
3160 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
3163 static inline bfd_boolean
3164 fixup_has_matching_lo_p (fixS *fixp)
3166 return (fixp->fx_next != NULL
3167 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
3168 && fixp->fx_addsy == fixp->fx_next->fx_addsy
3169 && fixp->fx_offset == fixp->fx_next->fx_offset);
3172 /* This function returns true if modifying a register requires a
3176 reg_needs_delay (unsigned int reg)
3178 unsigned long prev_pinfo;
3180 prev_pinfo = history[0].insn_mo->pinfo;
3181 if (! mips_opts.noreorder
3182 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
3183 && ! gpr_interlocks)
3184 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
3185 && ! cop_interlocks)))
3187 /* A load from a coprocessor or from memory. All load delays
3188 delay the use of general register rt for one instruction. */
3189 /* Itbl support may require additional care here. */
3190 know (prev_pinfo & INSN_WRITE_GPR_T);
3191 if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0]))
3198 /* Move all labels in LABELS to the current insertion point. TEXT_P
3199 says whether the labels refer to text or data. */
3202 mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
3204 struct insn_label_list *l;
3207 for (l = labels; l != NULL; l = l->next)
3209 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
3210 symbol_set_frag (l->label, frag_now);
3211 val = (valueT) frag_now_fix ();
3212 /* MIPS16/microMIPS text labels are stored as odd. */
3213 if (text_p && HAVE_CODE_COMPRESSION)
3215 S_SET_VALUE (l->label, val);
3219 /* Move all labels in insn_labels to the current insertion point
3220 and treat them as text labels. */
3223 mips_move_text_labels (void)
3225 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
3229 s_is_linkonce (symbolS *sym, segT from_seg)
3231 bfd_boolean linkonce = FALSE;
3232 segT symseg = S_GET_SEGMENT (sym);
3234 if (symseg != from_seg && !S_IS_LOCAL (sym))
3236 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
3238 /* The GNU toolchain uses an extension for ELF: a section
3239 beginning with the magic string .gnu.linkonce is a
3240 linkonce section. */
3241 if (strncmp (segment_name (symseg), ".gnu.linkonce",
3242 sizeof ".gnu.linkonce" - 1) == 0)
3248 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
3249 linker to handle them specially, such as generating jalx instructions
3250 when needed. We also make them odd for the duration of the assembly,
3251 in order to generate the right sort of code. We will make them even
3252 in the adjust_symtab routine, while leaving them marked. This is
3253 convenient for the debugger and the disassembler. The linker knows
3254 to make them odd again. */
3257 mips_compressed_mark_label (symbolS *label)
3259 gas_assert (HAVE_CODE_COMPRESSION);
3261 if (mips_opts.mips16)
3262 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
3264 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
3265 if ((S_GET_VALUE (label) & 1) == 0
3266 /* Don't adjust the address if the label is global or weak, or
3267 in a link-once section, since we'll be emitting symbol reloc
3268 references to it which will be patched up by the linker, and
3269 the final value of the symbol may or may not be MIPS16/microMIPS. */
3270 && !S_IS_WEAK (label)
3271 && !S_IS_EXTERNAL (label)
3272 && !s_is_linkonce (label, now_seg))
3273 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
3276 /* Mark preceding MIPS16 or microMIPS instruction labels. */
3279 mips_compressed_mark_labels (void)
3281 struct insn_label_list *l;
3283 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next)
3284 mips_compressed_mark_label (l->label);
3287 /* End the current frag. Make it a variant frag and record the
3291 relax_close_frag (void)
3293 mips_macro_warning.first_frag = frag_now;
3294 frag_var (rs_machine_dependent, 0, 0,
3295 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
3296 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
3298 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
3299 mips_relax.first_fixup = 0;
3302 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
3303 See the comment above RELAX_ENCODE for more details. */
3306 relax_start (symbolS *symbol)
3308 gas_assert (mips_relax.sequence == 0);
3309 mips_relax.sequence = 1;
3310 mips_relax.symbol = symbol;
3313 /* Start generating the second version of a relaxable sequence.
3314 See the comment above RELAX_ENCODE for more details. */
3319 gas_assert (mips_relax.sequence == 1);
3320 mips_relax.sequence = 2;
3323 /* End the current relaxable sequence. */
3328 gas_assert (mips_relax.sequence == 2);
3329 relax_close_frag ();
3330 mips_relax.sequence = 0;
3333 /* Return true if IP is a delayed branch or jump. */
3335 static inline bfd_boolean
3336 delayed_branch_p (const struct mips_cl_insn *ip)
3338 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
3339 | INSN_COND_BRANCH_DELAY
3340 | INSN_COND_BRANCH_LIKELY)) != 0;
3343 /* Return true if IP is a compact branch or jump. */
3345 static inline bfd_boolean
3346 compact_branch_p (const struct mips_cl_insn *ip)
3348 if (mips_opts.mips16)
3349 return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
3350 | MIPS16_INSN_COND_BRANCH)) != 0;
3352 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
3353 | INSN2_COND_BRANCH)) != 0;
3356 /* Return true if IP is an unconditional branch or jump. */
3358 static inline bfd_boolean
3359 uncond_branch_p (const struct mips_cl_insn *ip)
3361 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
3362 || (mips_opts.mips16
3363 ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0
3364 : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0));
3367 /* Return true if IP is a branch-likely instruction. */
3369 static inline bfd_boolean
3370 branch_likely_p (const struct mips_cl_insn *ip)
3372 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
3375 /* Return the type of nop that should be used to fill the delay slot
3376 of delayed branch IP. */
3378 static struct mips_cl_insn *
3379 get_delay_slot_nop (const struct mips_cl_insn *ip)
3381 if (mips_opts.micromips
3382 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
3383 return µmips_nop32_insn;
3387 /* Return the mask of core registers that IP reads or writes. */
3390 gpr_mod_mask (const struct mips_cl_insn *ip)
3392 unsigned long pinfo2;
3396 pinfo2 = ip->insn_mo->pinfo2;
3397 if (mips_opts.micromips)
3399 if (pinfo2 & INSN2_MOD_GPR_MD)
3400 mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)];
3401 if (pinfo2 & INSN2_MOD_GPR_MF)
3402 mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)];
3403 if (pinfo2 & INSN2_MOD_SP)
3409 /* Return the mask of core registers that IP reads. */
3412 gpr_read_mask (const struct mips_cl_insn *ip)
3414 unsigned long pinfo, pinfo2;
3417 mask = gpr_mod_mask (ip);
3418 pinfo = ip->insn_mo->pinfo;
3419 pinfo2 = ip->insn_mo->pinfo2;
3420 if (mips_opts.mips16)
3422 if (pinfo & MIPS16_INSN_READ_X)
3423 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3424 if (pinfo & MIPS16_INSN_READ_Y)
3425 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3426 if (pinfo & MIPS16_INSN_READ_T)
3428 if (pinfo & MIPS16_INSN_READ_SP)
3430 if (pinfo & MIPS16_INSN_READ_31)
3432 if (pinfo & MIPS16_INSN_READ_Z)
3433 mask |= 1 << (mips16_to_32_reg_map
3434 [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]);
3435 if (pinfo & MIPS16_INSN_READ_GPR_X)
3436 mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
3440 if (pinfo2 & INSN2_READ_GPR_D)
3441 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3442 if (pinfo & INSN_READ_GPR_T)
3443 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3444 if (pinfo & INSN_READ_GPR_S)
3445 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3446 if (pinfo2 & INSN2_READ_GP)
3448 if (pinfo2 & INSN2_READ_GPR_31)
3450 if (pinfo2 & INSN2_READ_GPR_Z)
3451 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3453 if (mips_opts.micromips)
3455 if (pinfo2 & INSN2_READ_GPR_MC)
3456 mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)];
3457 if (pinfo2 & INSN2_READ_GPR_ME)
3458 mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)];
3459 if (pinfo2 & INSN2_READ_GPR_MG)
3460 mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)];
3461 if (pinfo2 & INSN2_READ_GPR_MJ)
3462 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3463 if (pinfo2 & INSN2_READ_GPR_MMN)
3465 mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)];
3466 mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)];
3468 if (pinfo2 & INSN2_READ_GPR_MP)
3469 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3470 if (pinfo2 & INSN2_READ_GPR_MQ)
3471 mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)];
3473 /* Don't include register 0. */
3477 /* Return the mask of core registers that IP writes. */
3480 gpr_write_mask (const struct mips_cl_insn *ip)
3482 unsigned long pinfo, pinfo2;
3485 mask = gpr_mod_mask (ip);
3486 pinfo = ip->insn_mo->pinfo;
3487 pinfo2 = ip->insn_mo->pinfo2;
3488 if (mips_opts.mips16)
3490 if (pinfo & MIPS16_INSN_WRITE_X)
3491 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3492 if (pinfo & MIPS16_INSN_WRITE_Y)
3493 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3494 if (pinfo & MIPS16_INSN_WRITE_Z)
3495 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)];
3496 if (pinfo & MIPS16_INSN_WRITE_T)
3498 if (pinfo & MIPS16_INSN_WRITE_SP)
3500 if (pinfo & MIPS16_INSN_WRITE_31)
3502 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
3503 mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
3507 if (pinfo & INSN_WRITE_GPR_D)
3508 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3509 if (pinfo & INSN_WRITE_GPR_T)
3510 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3511 if (pinfo & INSN_WRITE_GPR_S)
3512 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3513 if (pinfo & INSN_WRITE_GPR_31)
3515 if (pinfo2 & INSN2_WRITE_GPR_Z)
3516 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3518 if (mips_opts.micromips)
3520 if (pinfo2 & INSN2_WRITE_GPR_MB)
3521 mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)];
3522 if (pinfo2 & INSN2_WRITE_GPR_MH)
3524 mask |= 1 << micromips_to_32_reg_h_map1[EXTRACT_OPERAND (1, MH, *ip)];
3525 mask |= 1 << micromips_to_32_reg_h_map2[EXTRACT_OPERAND (1, MH, *ip)];
3527 if (pinfo2 & INSN2_WRITE_GPR_MJ)
3528 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3529 if (pinfo2 & INSN2_WRITE_GPR_MP)
3530 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3532 /* Don't include register 0. */
3536 /* Return the mask of floating-point registers that IP reads. */
3539 fpr_read_mask (const struct mips_cl_insn *ip)
3541 unsigned long pinfo, pinfo2;
3545 pinfo = ip->insn_mo->pinfo;
3546 pinfo2 = ip->insn_mo->pinfo2;
3547 if (!mips_opts.mips16)
3549 if (pinfo2 & INSN2_READ_FPR_D)
3550 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3551 if (pinfo & INSN_READ_FPR_S)
3552 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3553 if (pinfo & INSN_READ_FPR_T)
3554 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3555 if (pinfo & INSN_READ_FPR_R)
3556 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip);
3557 if (pinfo2 & INSN2_READ_FPR_Z)
3558 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3560 /* Conservatively treat all operands to an FP_D instruction are doubles.
3561 (This is overly pessimistic for things like cvt.d.s.) */
3562 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3567 /* Return the mask of floating-point registers that IP writes. */
3570 fpr_write_mask (const struct mips_cl_insn *ip)
3572 unsigned long pinfo, pinfo2;
3576 pinfo = ip->insn_mo->pinfo;
3577 pinfo2 = ip->insn_mo->pinfo2;
3578 if (!mips_opts.mips16)
3580 if (pinfo & INSN_WRITE_FPR_D)
3581 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3582 if (pinfo & INSN_WRITE_FPR_S)
3583 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3584 if (pinfo & INSN_WRITE_FPR_T)
3585 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3586 if (pinfo2 & INSN2_WRITE_FPR_Z)
3587 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3589 /* Conservatively treat all operands to an FP_D instruction are doubles.
3590 (This is overly pessimistic for things like cvt.s.d.) */
3591 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3596 /* Classify an instruction according to the FIX_VR4120_* enumeration.
3597 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
3598 by VR4120 errata. */
3601 classify_vr4120_insn (const char *name)
3603 if (strncmp (name, "macc", 4) == 0)
3604 return FIX_VR4120_MACC;
3605 if (strncmp (name, "dmacc", 5) == 0)
3606 return FIX_VR4120_DMACC;
3607 if (strncmp (name, "mult", 4) == 0)
3608 return FIX_VR4120_MULT;
3609 if (strncmp (name, "dmult", 5) == 0)
3610 return FIX_VR4120_DMULT;
3611 if (strstr (name, "div"))
3612 return FIX_VR4120_DIV;
3613 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
3614 return FIX_VR4120_MTHILO;
3615 return NUM_FIX_VR4120_CLASSES;
3618 #define INSN_ERET 0x42000018
3619 #define INSN_DERET 0x4200001f
3621 /* Return the number of instructions that must separate INSN1 and INSN2,
3622 where INSN1 is the earlier instruction. Return the worst-case value
3623 for any INSN2 if INSN2 is null. */
3626 insns_between (const struct mips_cl_insn *insn1,
3627 const struct mips_cl_insn *insn2)
3629 unsigned long pinfo1, pinfo2;
3632 /* This function needs to know which pinfo flags are set for INSN2
3633 and which registers INSN2 uses. The former is stored in PINFO2 and
3634 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
3635 will have every flag set and INSN2_USES_GPR will always return true. */
3636 pinfo1 = insn1->insn_mo->pinfo;
3637 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
3639 #define INSN2_USES_GPR(REG) \
3640 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
3642 /* For most targets, write-after-read dependencies on the HI and LO
3643 registers must be separated by at least two instructions. */
3644 if (!hilo_interlocks)
3646 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
3648 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
3652 /* If we're working around r7000 errata, there must be two instructions
3653 between an mfhi or mflo and any instruction that uses the result. */
3654 if (mips_7000_hilo_fix
3655 && !mips_opts.micromips
3656 && MF_HILO_INSN (pinfo1)
3657 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1)))
3660 /* If we're working around 24K errata, one instruction is required
3661 if an ERET or DERET is followed by a branch instruction. */
3662 if (mips_fix_24k && !mips_opts.micromips)
3664 if (insn1->insn_opcode == INSN_ERET
3665 || insn1->insn_opcode == INSN_DERET)
3668 || insn2->insn_opcode == INSN_ERET
3669 || insn2->insn_opcode == INSN_DERET
3670 || delayed_branch_p (insn2))
3675 /* If working around VR4120 errata, check for combinations that need
3676 a single intervening instruction. */
3677 if (mips_fix_vr4120 && !mips_opts.micromips)
3679 unsigned int class1, class2;
3681 class1 = classify_vr4120_insn (insn1->insn_mo->name);
3682 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
3686 class2 = classify_vr4120_insn (insn2->insn_mo->name);
3687 if (vr4120_conflicts[class1] & (1 << class2))
3692 if (!HAVE_CODE_COMPRESSION)
3694 /* Check for GPR or coprocessor load delays. All such delays
3695 are on the RT register. */
3696 /* Itbl support may require additional care here. */
3697 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
3698 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
3700 know (pinfo1 & INSN_WRITE_GPR_T);
3701 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1)))
3705 /* Check for generic coprocessor hazards.
3707 This case is not handled very well. There is no special
3708 knowledge of CP0 handling, and the coprocessors other than
3709 the floating point unit are not distinguished at all. */
3710 /* Itbl support may require additional care here. FIXME!
3711 Need to modify this to include knowledge about
3712 user specified delays! */
3713 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
3714 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
3716 /* Handle cases where INSN1 writes to a known general coprocessor
3717 register. There must be a one instruction delay before INSN2
3718 if INSN2 reads that register, otherwise no delay is needed. */
3719 mask = fpr_write_mask (insn1);
3722 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
3727 /* Read-after-write dependencies on the control registers
3728 require a two-instruction gap. */
3729 if ((pinfo1 & INSN_WRITE_COND_CODE)
3730 && (pinfo2 & INSN_READ_COND_CODE))
3733 /* We don't know exactly what INSN1 does. If INSN2 is
3734 also a coprocessor instruction, assume there must be
3735 a one instruction gap. */
3736 if (pinfo2 & INSN_COP)
3741 /* Check for read-after-write dependencies on the coprocessor
3742 control registers in cases where INSN1 does not need a general
3743 coprocessor delay. This means that INSN1 is a floating point
3744 comparison instruction. */
3745 /* Itbl support may require additional care here. */
3746 else if (!cop_interlocks
3747 && (pinfo1 & INSN_WRITE_COND_CODE)
3748 && (pinfo2 & INSN_READ_COND_CODE))
3752 #undef INSN2_USES_GPR
3757 /* Return the number of nops that would be needed to work around the
3758 VR4130 mflo/mfhi errata if instruction INSN immediately followed
3759 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
3760 that are contained within the first IGNORE instructions of HIST. */
3763 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
3764 const struct mips_cl_insn *insn)
3769 /* Check if the instruction writes to HI or LO. MTHI and MTLO
3770 are not affected by the errata. */
3772 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
3773 || strcmp (insn->insn_mo->name, "mtlo") == 0
3774 || strcmp (insn->insn_mo->name, "mthi") == 0))
3777 /* Search for the first MFLO or MFHI. */
3778 for (i = 0; i < MAX_VR4130_NOPS; i++)
3779 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
3781 /* Extract the destination register. */
3782 mask = gpr_write_mask (&hist[i]);
3784 /* No nops are needed if INSN reads that register. */
3785 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
3788 /* ...or if any of the intervening instructions do. */
3789 for (j = 0; j < i; j++)
3790 if (gpr_read_mask (&hist[j]) & mask)
3794 return MAX_VR4130_NOPS - i;
3799 #define BASE_REG_EQ(INSN1, INSN2) \
3800 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
3801 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
3803 /* Return the minimum alignment for this store instruction. */
3806 fix_24k_align_to (const struct mips_opcode *mo)
3808 if (strcmp (mo->name, "sh") == 0)
3811 if (strcmp (mo->name, "swc1") == 0
3812 || strcmp (mo->name, "swc2") == 0
3813 || strcmp (mo->name, "sw") == 0
3814 || strcmp (mo->name, "sc") == 0
3815 || strcmp (mo->name, "s.s") == 0)
3818 if (strcmp (mo->name, "sdc1") == 0
3819 || strcmp (mo->name, "sdc2") == 0
3820 || strcmp (mo->name, "s.d") == 0)
3827 struct fix_24k_store_info
3829 /* Immediate offset, if any, for this store instruction. */
3831 /* Alignment required by this store instruction. */
3833 /* True for register offsets. */
3834 int register_offset;
3837 /* Comparison function used by qsort. */
3840 fix_24k_sort (const void *a, const void *b)
3842 const struct fix_24k_store_info *pos1 = a;
3843 const struct fix_24k_store_info *pos2 = b;
3845 return (pos1->off - pos2->off);
3848 /* INSN is a store instruction. Try to record the store information
3849 in STINFO. Return false if the information isn't known. */
3852 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
3853 const struct mips_cl_insn *insn)
3855 /* The instruction must have a known offset. */
3856 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
3859 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
3860 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
3864 /* Return the number of nops that would be needed to work around the 24k
3865 "lost data on stores during refill" errata if instruction INSN
3866 immediately followed the 2 instructions described by HIST.
3867 Ignore hazards that are contained within the first IGNORE
3868 instructions of HIST.
3870 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
3871 for the data cache refills and store data. The following describes
3872 the scenario where the store data could be lost.
3874 * A data cache miss, due to either a load or a store, causing fill
3875 data to be supplied by the memory subsystem
3876 * The first three doublewords of fill data are returned and written
3878 * A sequence of four stores occurs in consecutive cycles around the
3879 final doubleword of the fill:
3883 * Zero, One or more instructions
3886 The four stores A-D must be to different doublewords of the line that
3887 is being filled. The fourth instruction in the sequence above permits
3888 the fill of the final doubleword to be transferred from the FSB into
3889 the cache. In the sequence above, the stores may be either integer
3890 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
3891 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
3892 different doublewords on the line. If the floating point unit is
3893 running in 1:2 mode, it is not possible to create the sequence above
3894 using only floating point store instructions.
3896 In this case, the cache line being filled is incorrectly marked
3897 invalid, thereby losing the data from any store to the line that
3898 occurs between the original miss and the completion of the five
3899 cycle sequence shown above.
3901 The workarounds are:
3903 * Run the data cache in write-through mode.
3904 * Insert a non-store instruction between
3905 Store A and Store B or Store B and Store C. */
3908 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
3909 const struct mips_cl_insn *insn)
3911 struct fix_24k_store_info pos[3];
3912 int align, i, base_offset;
3917 /* If the previous instruction wasn't a store, there's nothing to
3919 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3922 /* If the instructions after the previous one are unknown, we have
3923 to assume the worst. */
3927 /* Check whether we are dealing with three consecutive stores. */
3928 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
3929 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3932 /* If we don't know the relationship between the store addresses,
3933 assume the worst. */
3934 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
3935 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
3938 if (!fix_24k_record_store_info (&pos[0], insn)
3939 || !fix_24k_record_store_info (&pos[1], &hist[0])
3940 || !fix_24k_record_store_info (&pos[2], &hist[1]))
3943 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
3945 /* Pick a value of ALIGN and X such that all offsets are adjusted by
3946 X bytes and such that the base register + X is known to be aligned
3949 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
3953 align = pos[0].align_to;
3954 base_offset = pos[0].off;
3955 for (i = 1; i < 3; i++)
3956 if (align < pos[i].align_to)
3958 align = pos[i].align_to;
3959 base_offset = pos[i].off;
3961 for (i = 0; i < 3; i++)
3962 pos[i].off -= base_offset;
3965 pos[0].off &= ~align + 1;
3966 pos[1].off &= ~align + 1;
3967 pos[2].off &= ~align + 1;
3969 /* If any two stores write to the same chunk, they also write to the
3970 same doubleword. The offsets are still sorted at this point. */
3971 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
3974 /* A range of at least 9 bytes is needed for the stores to be in
3975 non-overlapping doublewords. */
3976 if (pos[2].off - pos[0].off <= 8)
3979 if (pos[2].off - pos[1].off >= 24
3980 || pos[1].off - pos[0].off >= 24
3981 || pos[2].off - pos[0].off >= 32)
3987 /* Return the number of nops that would be needed if instruction INSN
3988 immediately followed the MAX_NOPS instructions given by HIST,
3989 where HIST[0] is the most recent instruction. Ignore hazards
3990 between INSN and the first IGNORE instructions in HIST.
3992 If INSN is null, return the worse-case number of nops for any
3996 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
3997 const struct mips_cl_insn *insn)
3999 int i, nops, tmp_nops;
4002 for (i = ignore; i < MAX_DELAY_NOPS; i++)
4004 tmp_nops = insns_between (hist + i, insn) - i;
4005 if (tmp_nops > nops)
4009 if (mips_fix_vr4130 && !mips_opts.micromips)
4011 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
4012 if (tmp_nops > nops)
4016 if (mips_fix_24k && !mips_opts.micromips)
4018 tmp_nops = nops_for_24k (ignore, hist, insn);
4019 if (tmp_nops > nops)
4026 /* The variable arguments provide NUM_INSNS extra instructions that
4027 might be added to HIST. Return the largest number of nops that
4028 would be needed after the extended sequence, ignoring hazards
4029 in the first IGNORE instructions. */
4032 nops_for_sequence (int num_insns, int ignore,
4033 const struct mips_cl_insn *hist, ...)
4036 struct mips_cl_insn buffer[MAX_NOPS];
4037 struct mips_cl_insn *cursor;
4040 va_start (args, hist);
4041 cursor = buffer + num_insns;
4042 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
4043 while (cursor > buffer)
4044 *--cursor = *va_arg (args, const struct mips_cl_insn *);
4046 nops = nops_for_insn (ignore, buffer, NULL);
4051 /* Like nops_for_insn, but if INSN is a branch, take into account the
4052 worst-case delay for the branch target. */
4055 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
4056 const struct mips_cl_insn *insn)
4060 nops = nops_for_insn (ignore, hist, insn);
4061 if (delayed_branch_p (insn))
4063 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
4064 hist, insn, get_delay_slot_nop (insn));
4065 if (tmp_nops > nops)
4068 else if (compact_branch_p (insn))
4070 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
4071 if (tmp_nops > nops)
4077 /* Fix NOP issue: Replace nops by "or at,at,zero". */
4080 fix_loongson2f_nop (struct mips_cl_insn * ip)
4082 gas_assert (!HAVE_CODE_COMPRESSION);
4083 if (strcmp (ip->insn_mo->name, "nop") == 0)
4084 ip->insn_opcode = LOONGSON2F_NOP_INSN;
4087 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
4088 jr target pc &= 'hffff_ffff_cfff_ffff. */
4091 fix_loongson2f_jump (struct mips_cl_insn * ip)
4093 gas_assert (!HAVE_CODE_COMPRESSION);
4094 if (strcmp (ip->insn_mo->name, "j") == 0
4095 || strcmp (ip->insn_mo->name, "jr") == 0
4096 || strcmp (ip->insn_mo->name, "jalr") == 0)
4104 sreg = EXTRACT_OPERAND (0, RS, *ip);
4105 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
4108 ep.X_op = O_constant;
4109 ep.X_add_number = 0xcfff0000;
4110 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
4111 ep.X_add_number = 0xffff;
4112 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
4113 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
4118 fix_loongson2f (struct mips_cl_insn * ip)
4120 if (mips_fix_loongson2f_nop)
4121 fix_loongson2f_nop (ip);
4123 if (mips_fix_loongson2f_jump)
4124 fix_loongson2f_jump (ip);
4127 /* IP is a branch that has a delay slot, and we need to fill it
4128 automatically. Return true if we can do that by swapping IP
4129 with the previous instruction.
4130 ADDRESS_EXPR is an operand of the instruction to be used with
4134 can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
4135 bfd_reloc_code_real_type *reloc_type)
4137 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
4138 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
4140 /* -O2 and above is required for this optimization. */
4141 if (mips_optimize < 2)
4144 /* If we have seen .set volatile or .set nomove, don't optimize. */
4145 if (mips_opts.nomove)
4148 /* We can't swap if the previous instruction's position is fixed. */
4149 if (history[0].fixed_p)
4152 /* If the previous previous insn was in a .set noreorder, we can't
4153 swap. Actually, the MIPS assembler will swap in this situation.
4154 However, gcc configured -with-gnu-as will generate code like
4162 in which we can not swap the bne and INSN. If gcc is not configured
4163 -with-gnu-as, it does not output the .set pseudo-ops. */
4164 if (history[1].noreorder_p)
4167 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
4168 This means that the previous instruction was a 4-byte one anyhow. */
4169 if (mips_opts.mips16 && history[0].fixp[0])
4172 /* If the branch is itself the target of a branch, we can not swap.
4173 We cheat on this; all we check for is whether there is a label on
4174 this instruction. If there are any branches to anything other than
4175 a label, users must use .set noreorder. */
4176 if (seg_info (now_seg)->label_list)
4179 /* If the previous instruction is in a variant frag other than this
4180 branch's one, we cannot do the swap. This does not apply to
4181 MIPS16 code, which uses variant frags for different purposes. */
4182 if (!mips_opts.mips16
4184 && history[0].frag->fr_type == rs_machine_dependent)
4187 /* We do not swap with instructions that cannot architecturally
4188 be placed in a branch delay slot, such as SYNC or ERET. We
4189 also refrain from swapping with a trap instruction, since it
4190 complicates trap handlers to have the trap instruction be in
4192 prev_pinfo = history[0].insn_mo->pinfo;
4193 if (prev_pinfo & INSN_NO_DELAY_SLOT)
4196 /* Check for conflicts between the branch and the instructions
4197 before the candidate delay slot. */
4198 if (nops_for_insn (0, history + 1, ip) > 0)
4201 /* Check for conflicts between the swapped sequence and the
4202 target of the branch. */
4203 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
4206 /* If the branch reads a register that the previous
4207 instruction sets, we can not swap. */
4208 gpr_read = gpr_read_mask (ip);
4209 prev_gpr_write = gpr_write_mask (&history[0]);
4210 if (gpr_read & prev_gpr_write)
4213 /* If the branch writes a register that the previous
4214 instruction sets, we can not swap. */
4215 gpr_write = gpr_write_mask (ip);
4216 if (gpr_write & prev_gpr_write)
4219 /* If the branch writes a register that the previous
4220 instruction reads, we can not swap. */
4221 prev_gpr_read = gpr_read_mask (&history[0]);
4222 if (gpr_write & prev_gpr_read)
4225 /* If one instruction sets a condition code and the
4226 other one uses a condition code, we can not swap. */
4227 pinfo = ip->insn_mo->pinfo;
4228 if ((pinfo & INSN_READ_COND_CODE)
4229 && (prev_pinfo & INSN_WRITE_COND_CODE))
4231 if ((pinfo & INSN_WRITE_COND_CODE)
4232 && (prev_pinfo & INSN_READ_COND_CODE))
4235 /* If the previous instruction uses the PC, we can not swap. */
4236 prev_pinfo2 = history[0].insn_mo->pinfo2;
4237 if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC))
4239 if (mips_opts.micromips && (prev_pinfo2 & INSN2_READ_PC))
4242 /* If the previous instruction has an incorrect size for a fixed
4243 branch delay slot in microMIPS mode, we cannot swap. */
4244 pinfo2 = ip->insn_mo->pinfo2;
4245 if (mips_opts.micromips
4246 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
4247 && insn_length (history) != 2)
4249 if (mips_opts.micromips
4250 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
4251 && insn_length (history) != 4)
4254 /* On R5900 short loops need to be fixed by inserting a nop in
4255 the branch delay slots.
4256 A short loop can be terminated too early. */
4257 if (mips_opts.arch == CPU_R5900
4258 /* Check if instruction has a parameter, ignore "j $31". */
4259 && (address_expr != NULL)
4260 /* Parameter must be 16 bit. */
4261 && (*reloc_type == BFD_RELOC_16_PCREL_S2)
4262 /* Branch to same segment. */
4263 && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg)
4264 /* Branch to same code fragment. */
4265 && (symbol_get_frag(address_expr->X_add_symbol) == frag_now)
4266 /* Can only calculate branch offset if value is known. */
4267 && symbol_constant_p(address_expr->X_add_symbol)
4268 /* Check if branch is really conditional. */
4269 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */
4270 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */
4271 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
4274 /* Check if loop is shorter than 6 instructions including
4275 branch and delay slot. */
4276 distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol);
4283 /* When the loop includes branches or jumps,
4284 it is not a short loop. */
4285 for (i = 0; i < (distance / 4); i++)
4287 if ((history[i].cleared_p)
4288 || delayed_branch_p(&history[i]))
4296 /* Insert nop after branch to fix short loop. */
4305 /* Decide how we should add IP to the instruction stream.
4306 ADDRESS_EXPR is an operand of the instruction to be used with
4309 static enum append_method
4310 get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
4311 bfd_reloc_code_real_type *reloc_type)
4313 unsigned long pinfo;
4315 /* The relaxed version of a macro sequence must be inherently
4317 if (mips_relax.sequence == 2)
4320 /* We must not dabble with instructions in a ".set norerorder" block. */
4321 if (mips_opts.noreorder)
4324 /* Otherwise, it's our responsibility to fill branch delay slots. */
4325 if (delayed_branch_p (ip))
4327 if (!branch_likely_p (ip)
4328 && can_swap_branch_p (ip, address_expr, reloc_type))
4331 pinfo = ip->insn_mo->pinfo;
4332 if (mips_opts.mips16
4333 && ISA_SUPPORTS_MIPS16E
4334 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)))
4335 return APPEND_ADD_COMPACT;
4337 return APPEND_ADD_WITH_NOP;
4343 /* IP is a MIPS16 instruction whose opcode we have just changed.
4344 Point IP->insn_mo to the new opcode's definition. */
4347 find_altered_mips16_opcode (struct mips_cl_insn *ip)
4349 const struct mips_opcode *mo, *end;
4351 end = &mips16_opcodes[bfd_mips16_num_opcodes];
4352 for (mo = ip->insn_mo; mo < end; mo++)
4353 if ((ip->insn_opcode & mo->mask) == mo->match)
4361 /* For microMIPS macros, we need to generate a local number label
4362 as the target of branches. */
4363 #define MICROMIPS_LABEL_CHAR '\037'
4364 static unsigned long micromips_target_label;
4365 static char micromips_target_name[32];
4368 micromips_label_name (void)
4370 char *p = micromips_target_name;
4371 char symbol_name_temporary[24];
4379 l = micromips_target_label;
4380 #ifdef LOCAL_LABEL_PREFIX
4381 *p++ = LOCAL_LABEL_PREFIX;
4384 *p++ = MICROMIPS_LABEL_CHAR;
4387 symbol_name_temporary[i++] = l % 10 + '0';
4392 *p++ = symbol_name_temporary[--i];
4395 return micromips_target_name;
4399 micromips_label_expr (expressionS *label_expr)
4401 label_expr->X_op = O_symbol;
4402 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
4403 label_expr->X_add_number = 0;
4407 micromips_label_inc (void)
4409 micromips_target_label++;
4410 *micromips_target_name = '\0';
4414 micromips_add_label (void)
4418 s = colon (micromips_label_name ());
4419 micromips_label_inc ();
4420 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
4423 /* If assembling microMIPS code, then return the microMIPS reloc
4424 corresponding to the requested one if any. Otherwise return
4425 the reloc unchanged. */
4427 static bfd_reloc_code_real_type
4428 micromips_map_reloc (bfd_reloc_code_real_type reloc)
4430 static const bfd_reloc_code_real_type relocs[][2] =
4432 /* Keep sorted incrementally by the left-hand key. */
4433 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
4434 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
4435 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
4436 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
4437 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
4438 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
4439 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
4440 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
4441 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
4442 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
4443 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
4444 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
4445 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
4446 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
4447 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
4448 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
4449 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
4450 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
4451 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
4452 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
4453 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
4454 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
4455 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
4456 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
4457 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
4458 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
4459 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
4461 bfd_reloc_code_real_type r;
4464 if (!mips_opts.micromips)
4466 for (i = 0; i < ARRAY_SIZE (relocs); i++)
4472 return relocs[i][1];
4477 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
4478 Return true on success, storing the resolved value in RESULT. */
4481 calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
4486 case BFD_RELOC_MIPS_HIGHEST:
4487 case BFD_RELOC_MICROMIPS_HIGHEST:
4488 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff;
4491 case BFD_RELOC_MIPS_HIGHER:
4492 case BFD_RELOC_MICROMIPS_HIGHER:
4493 *result = ((operand + 0x80008000ull) >> 32) & 0xffff;
4496 case BFD_RELOC_HI16_S:
4497 case BFD_RELOC_MICROMIPS_HI16_S:
4498 case BFD_RELOC_MIPS16_HI16_S:
4499 *result = ((operand + 0x8000) >> 16) & 0xffff;
4502 case BFD_RELOC_HI16:
4503 case BFD_RELOC_MICROMIPS_HI16:
4504 case BFD_RELOC_MIPS16_HI16:
4505 *result = (operand >> 16) & 0xffff;
4508 case BFD_RELOC_LO16:
4509 case BFD_RELOC_MICROMIPS_LO16:
4510 case BFD_RELOC_MIPS16_LO16:
4511 *result = operand & 0xffff;
4514 case BFD_RELOC_UNUSED:
4523 /* Output an instruction. IP is the instruction information.
4524 ADDRESS_EXPR is an operand of the instruction to be used with
4525 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
4526 a macro expansion. */
4529 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
4530 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
4532 unsigned long prev_pinfo2, pinfo;
4533 bfd_boolean relaxed_branch = FALSE;
4534 enum append_method method;
4535 bfd_boolean relax32;
4538 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
4539 fix_loongson2f (ip);
4541 file_ase_mips16 |= mips_opts.mips16;
4542 file_ase_micromips |= mips_opts.micromips;
4544 prev_pinfo2 = history[0].insn_mo->pinfo2;
4545 pinfo = ip->insn_mo->pinfo;
4547 if (mips_opts.micromips
4549 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
4550 && micromips_insn_length (ip->insn_mo) != 2)
4551 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
4552 && micromips_insn_length (ip->insn_mo) != 4)))
4553 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
4554 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
4556 if (address_expr == NULL)
4558 else if (reloc_type[0] <= BFD_RELOC_UNUSED
4559 && reloc_type[1] == BFD_RELOC_UNUSED
4560 && reloc_type[2] == BFD_RELOC_UNUSED
4561 && address_expr->X_op == O_constant)
4563 switch (*reloc_type)
4565 case BFD_RELOC_MIPS_JMP:
4569 shift = mips_opts.micromips ? 1 : 2;
4570 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4571 as_bad (_("jump to misaligned address (0x%lx)"),
4572 (unsigned long) address_expr->X_add_number);
4573 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4579 case BFD_RELOC_MIPS16_JMP:
4580 if ((address_expr->X_add_number & 3) != 0)
4581 as_bad (_("jump to misaligned address (0x%lx)"),
4582 (unsigned long) address_expr->X_add_number);
4584 (((address_expr->X_add_number & 0x7c0000) << 3)
4585 | ((address_expr->X_add_number & 0xf800000) >> 7)
4586 | ((address_expr->X_add_number & 0x3fffc) >> 2));
4590 case BFD_RELOC_16_PCREL_S2:
4594 shift = mips_opts.micromips ? 1 : 2;
4595 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4596 as_bad (_("branch to misaligned address (0x%lx)"),
4597 (unsigned long) address_expr->X_add_number);
4598 if (!mips_relax_branch)
4600 if ((address_expr->X_add_number + (1 << (shift + 15)))
4601 & ~((1 << (shift + 16)) - 1))
4602 as_bad (_("branch address range overflow (0x%lx)"),
4603 (unsigned long) address_expr->X_add_number);
4604 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4614 if (calculate_reloc (*reloc_type, address_expr->X_add_number,
4617 ip->insn_opcode |= value & 0xffff;
4625 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
4627 /* There are a lot of optimizations we could do that we don't.
4628 In particular, we do not, in general, reorder instructions.
4629 If you use gcc with optimization, it will reorder
4630 instructions and generally do much more optimization then we
4631 do here; repeating all that work in the assembler would only
4632 benefit hand written assembly code, and does not seem worth
4634 int nops = (mips_optimize == 0
4635 ? nops_for_insn (0, history, NULL)
4636 : nops_for_insn_or_target (0, history, ip));
4640 unsigned long old_frag_offset;
4643 old_frag = frag_now;
4644 old_frag_offset = frag_now_fix ();
4646 for (i = 0; i < nops; i++)
4647 add_fixed_insn (NOP_INSN);
4648 insert_into_history (0, nops, NOP_INSN);
4652 listing_prev_line ();
4653 /* We may be at the start of a variant frag. In case we
4654 are, make sure there is enough space for the frag
4655 after the frags created by listing_prev_line. The
4656 argument to frag_grow here must be at least as large
4657 as the argument to all other calls to frag_grow in
4658 this file. We don't have to worry about being in the
4659 middle of a variant frag, because the variants insert
4660 all needed nop instructions themselves. */
4664 mips_move_text_labels ();
4666 #ifndef NO_ECOFF_DEBUGGING
4667 if (ECOFF_DEBUGGING)
4668 ecoff_fix_loc (old_frag, old_frag_offset);
4672 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
4676 /* Work out how many nops in prev_nop_frag are needed by IP,
4677 ignoring hazards generated by the first prev_nop_frag_since
4679 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
4680 gas_assert (nops <= prev_nop_frag_holds);
4682 /* Enforce NOPS as a minimum. */
4683 if (nops > prev_nop_frag_required)
4684 prev_nop_frag_required = nops;
4686 if (prev_nop_frag_holds == prev_nop_frag_required)
4688 /* Settle for the current number of nops. Update the history
4689 accordingly (for the benefit of any future .set reorder code). */
4690 prev_nop_frag = NULL;
4691 insert_into_history (prev_nop_frag_since,
4692 prev_nop_frag_holds, NOP_INSN);
4696 /* Allow this instruction to replace one of the nops that was
4697 tentatively added to prev_nop_frag. */
4698 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
4699 prev_nop_frag_holds--;
4700 prev_nop_frag_since++;
4704 method = get_append_method (ip, address_expr, reloc_type);
4705 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
4707 dwarf2_emit_insn (0);
4708 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
4709 so "move" the instruction address accordingly.
4711 Also, it doesn't seem appropriate for the assembler to reorder .loc
4712 entries. If this instruction is a branch that we are going to swap
4713 with the previous instruction, the two instructions should be
4714 treated as a unit, and the debug information for both instructions
4715 should refer to the start of the branch sequence. Using the
4716 current position is certainly wrong when swapping a 32-bit branch
4717 and a 16-bit delay slot, since the current position would then be
4718 in the middle of a branch. */
4719 dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp);
4721 relax32 = (mips_relax_branch
4722 /* Don't try branch relaxation within .set nomacro, or within
4723 .set noat if we use $at for PIC computations. If it turns
4724 out that the branch was out-of-range, we'll get an error. */
4725 && !mips_opts.warn_about_macros
4726 && (mips_opts.at || mips_pic == NO_PIC)
4727 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
4728 as they have no complementing branches. */
4729 && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP)));
4731 if (!HAVE_CODE_COMPRESSION
4734 && *reloc_type == BFD_RELOC_16_PCREL_S2
4735 && delayed_branch_p (ip))
4737 relaxed_branch = TRUE;
4738 add_relaxed_insn (ip, (relaxed_branch_length
4740 uncond_branch_p (ip) ? -1
4741 : branch_likely_p (ip) ? 1
4745 uncond_branch_p (ip),
4746 branch_likely_p (ip),
4747 pinfo & INSN_WRITE_GPR_31,
4749 address_expr->X_add_symbol,
4750 address_expr->X_add_number);
4751 *reloc_type = BFD_RELOC_UNUSED;
4753 else if (mips_opts.micromips
4755 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
4756 || *reloc_type > BFD_RELOC_UNUSED)
4757 && (delayed_branch_p (ip) || compact_branch_p (ip))
4758 /* Don't try branch relaxation when users specify
4759 16-bit/32-bit instructions. */
4760 && !forced_insn_length)
4762 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
4763 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
4764 int uncond = uncond_branch_p (ip) ? -1 : 0;
4765 int compact = compact_branch_p (ip);
4766 int al = pinfo & INSN_WRITE_GPR_31;
4769 gas_assert (address_expr != NULL);
4770 gas_assert (!mips_relax.sequence);
4772 relaxed_branch = TRUE;
4773 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
4774 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
4775 RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al,
4777 address_expr->X_add_symbol,
4778 address_expr->X_add_number);
4779 *reloc_type = BFD_RELOC_UNUSED;
4781 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
4783 /* We need to set up a variant frag. */
4784 gas_assert (address_expr != NULL);
4785 add_relaxed_insn (ip, 4, 0,
4787 (*reloc_type - BFD_RELOC_UNUSED,
4788 forced_insn_length == 2, forced_insn_length == 4,
4789 delayed_branch_p (&history[0]),
4790 history[0].mips16_absolute_jump_p),
4791 make_expr_symbol (address_expr), 0);
4793 else if (mips_opts.mips16 && insn_length (ip) == 2)
4795 if (!delayed_branch_p (ip))
4796 /* Make sure there is enough room to swap this instruction with
4797 a following jump instruction. */
4799 add_fixed_insn (ip);
4803 if (mips_opts.mips16
4804 && mips_opts.noreorder
4805 && delayed_branch_p (&history[0]))
4806 as_warn (_("extended instruction in delay slot"));
4808 if (mips_relax.sequence)
4810 /* If we've reached the end of this frag, turn it into a variant
4811 frag and record the information for the instructions we've
4813 if (frag_room () < 4)
4814 relax_close_frag ();
4815 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
4818 if (mips_relax.sequence != 2)
4820 if (mips_macro_warning.first_insn_sizes[0] == 0)
4821 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
4822 mips_macro_warning.sizes[0] += insn_length (ip);
4823 mips_macro_warning.insns[0]++;
4825 if (mips_relax.sequence != 1)
4827 if (mips_macro_warning.first_insn_sizes[1] == 0)
4828 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
4829 mips_macro_warning.sizes[1] += insn_length (ip);
4830 mips_macro_warning.insns[1]++;
4833 if (mips_opts.mips16)
4836 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
4838 add_fixed_insn (ip);
4841 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
4843 bfd_reloc_code_real_type final_type[3];
4844 reloc_howto_type *howto0;
4845 reloc_howto_type *howto;
4848 /* Perform any necessary conversion to microMIPS relocations
4849 and find out how many relocations there actually are. */
4850 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
4851 final_type[i] = micromips_map_reloc (reloc_type[i]);
4853 /* In a compound relocation, it is the final (outermost)
4854 operator that determines the relocated field. */
4855 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
4860 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
4861 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
4862 bfd_get_reloc_size (howto),
4864 howto0 && howto0->pc_relative,
4867 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
4868 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
4869 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
4871 /* These relocations can have an addend that won't fit in
4872 4 octets for 64bit assembly. */
4874 && ! howto->partial_inplace
4875 && (reloc_type[0] == BFD_RELOC_16
4876 || reloc_type[0] == BFD_RELOC_32
4877 || reloc_type[0] == BFD_RELOC_MIPS_JMP
4878 || reloc_type[0] == BFD_RELOC_GPREL16
4879 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
4880 || reloc_type[0] == BFD_RELOC_GPREL32
4881 || reloc_type[0] == BFD_RELOC_64
4882 || reloc_type[0] == BFD_RELOC_CTOR
4883 || reloc_type[0] == BFD_RELOC_MIPS_SUB
4884 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
4885 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
4886 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
4887 || reloc_type[0] == BFD_RELOC_MIPS_REL16
4888 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
4889 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
4890 || hi16_reloc_p (reloc_type[0])
4891 || lo16_reloc_p (reloc_type[0])))
4892 ip->fixp[0]->fx_no_overflow = 1;
4894 /* These relocations can have an addend that won't fit in 2 octets. */
4895 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
4896 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1)
4897 ip->fixp[0]->fx_no_overflow = 1;
4899 if (mips_relax.sequence)
4901 if (mips_relax.first_fixup == 0)
4902 mips_relax.first_fixup = ip->fixp[0];
4904 else if (reloc_needs_lo_p (*reloc_type))
4906 struct mips_hi_fixup *hi_fixup;
4908 /* Reuse the last entry if it already has a matching %lo. */
4909 hi_fixup = mips_hi_fixup_list;
4911 || !fixup_has_matching_lo_p (hi_fixup->fixp))
4913 hi_fixup = ((struct mips_hi_fixup *)
4914 xmalloc (sizeof (struct mips_hi_fixup)));
4915 hi_fixup->next = mips_hi_fixup_list;
4916 mips_hi_fixup_list = hi_fixup;
4918 hi_fixup->fixp = ip->fixp[0];
4919 hi_fixup->seg = now_seg;
4922 /* Add fixups for the second and third relocations, if given.
4923 Note that the ABI allows the second relocation to be
4924 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
4925 moment we only use RSS_UNDEF, but we could add support
4926 for the others if it ever becomes necessary. */
4927 for (i = 1; i < 3; i++)
4928 if (reloc_type[i] != BFD_RELOC_UNUSED)
4930 ip->fixp[i] = fix_new (ip->frag, ip->where,
4931 ip->fixp[0]->fx_size, NULL, 0,
4932 FALSE, final_type[i]);
4934 /* Use fx_tcbit to mark compound relocs. */
4935 ip->fixp[0]->fx_tcbit = 1;
4936 ip->fixp[i]->fx_tcbit = 1;
4941 /* Update the register mask information. */
4942 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
4943 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
4948 insert_into_history (0, 1, ip);
4951 case APPEND_ADD_WITH_NOP:
4953 struct mips_cl_insn *nop;
4955 insert_into_history (0, 1, ip);
4956 nop = get_delay_slot_nop (ip);
4957 add_fixed_insn (nop);
4958 insert_into_history (0, 1, nop);
4959 if (mips_relax.sequence)
4960 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
4964 case APPEND_ADD_COMPACT:
4965 /* Convert MIPS16 jr/jalr into a "compact" jump. */
4966 gas_assert (mips_opts.mips16);
4967 ip->insn_opcode |= 0x0080;
4968 find_altered_mips16_opcode (ip);
4970 insert_into_history (0, 1, ip);
4975 struct mips_cl_insn delay = history[0];
4976 if (mips_opts.mips16)
4978 know (delay.frag == ip->frag);
4979 move_insn (ip, delay.frag, delay.where);
4980 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
4982 else if (relaxed_branch || delay.frag != ip->frag)
4984 /* Add the delay slot instruction to the end of the
4985 current frag and shrink the fixed part of the
4986 original frag. If the branch occupies the tail of
4987 the latter, move it backwards to cover the gap. */
4988 delay.frag->fr_fix -= branch_disp;
4989 if (delay.frag == ip->frag)
4990 move_insn (ip, ip->frag, ip->where - branch_disp);
4991 add_fixed_insn (&delay);
4995 move_insn (&delay, ip->frag,
4996 ip->where - branch_disp + insn_length (ip));
4997 move_insn (ip, history[0].frag, history[0].where);
5001 insert_into_history (0, 1, &delay);
5006 /* If we have just completed an unconditional branch, clear the history. */
5007 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
5008 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
5012 mips_no_prev_insn ();
5014 for (i = 0; i < ARRAY_SIZE (history); i++)
5015 history[i].cleared_p = 1;
5018 /* We need to emit a label at the end of branch-likely macros. */
5019 if (emit_branch_likely_macro)
5021 emit_branch_likely_macro = FALSE;
5022 micromips_add_label ();
5025 /* We just output an insn, so the next one doesn't have a label. */
5026 mips_clear_insn_labels ();
5029 /* Forget that there was any previous instruction or label.
5030 When BRANCH is true, the branch history is also flushed. */
5033 mips_no_prev_insn (void)
5035 prev_nop_frag = NULL;
5036 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
5037 mips_clear_insn_labels ();
5040 /* This function must be called before we emit something other than
5041 instructions. It is like mips_no_prev_insn except that it inserts
5042 any NOPS that might be needed by previous instructions. */
5045 mips_emit_delays (void)
5047 if (! mips_opts.noreorder)
5049 int nops = nops_for_insn (0, history, NULL);
5053 add_fixed_insn (NOP_INSN);
5054 mips_move_text_labels ();
5057 mips_no_prev_insn ();
5060 /* Start a (possibly nested) noreorder block. */
5063 start_noreorder (void)
5065 if (mips_opts.noreorder == 0)
5070 /* None of the instructions before the .set noreorder can be moved. */
5071 for (i = 0; i < ARRAY_SIZE (history); i++)
5072 history[i].fixed_p = 1;
5074 /* Insert any nops that might be needed between the .set noreorder
5075 block and the previous instructions. We will later remove any
5076 nops that turn out not to be needed. */
5077 nops = nops_for_insn (0, history, NULL);
5080 if (mips_optimize != 0)
5082 /* Record the frag which holds the nop instructions, so
5083 that we can remove them if we don't need them. */
5084 frag_grow (nops * NOP_INSN_SIZE);
5085 prev_nop_frag = frag_now;
5086 prev_nop_frag_holds = nops;
5087 prev_nop_frag_required = 0;
5088 prev_nop_frag_since = 0;
5091 for (; nops > 0; --nops)
5092 add_fixed_insn (NOP_INSN);
5094 /* Move on to a new frag, so that it is safe to simply
5095 decrease the size of prev_nop_frag. */
5096 frag_wane (frag_now);
5098 mips_move_text_labels ();
5100 mips_mark_labels ();
5101 mips_clear_insn_labels ();
5103 mips_opts.noreorder++;
5104 mips_any_noreorder = 1;
5107 /* End a nested noreorder block. */
5110 end_noreorder (void)
5112 mips_opts.noreorder--;
5113 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
5115 /* Commit to inserting prev_nop_frag_required nops and go back to
5116 handling nop insertion the .set reorder way. */
5117 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
5119 insert_into_history (prev_nop_frag_since,
5120 prev_nop_frag_required, NOP_INSN);
5121 prev_nop_frag = NULL;
5125 /* Set up global variables for the start of a new macro. */
5130 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
5131 memset (&mips_macro_warning.first_insn_sizes, 0,
5132 sizeof (mips_macro_warning.first_insn_sizes));
5133 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
5134 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
5135 && delayed_branch_p (&history[0]));
5136 switch (history[0].insn_mo->pinfo2
5137 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
5139 case INSN2_BRANCH_DELAY_32BIT:
5140 mips_macro_warning.delay_slot_length = 4;
5142 case INSN2_BRANCH_DELAY_16BIT:
5143 mips_macro_warning.delay_slot_length = 2;
5146 mips_macro_warning.delay_slot_length = 0;
5149 mips_macro_warning.first_frag = NULL;
5152 /* Given that a macro is longer than one instruction or of the wrong size,
5153 return the appropriate warning for it. Return null if no warning is
5154 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
5155 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
5156 and RELAX_NOMACRO. */
5159 macro_warning (relax_substateT subtype)
5161 if (subtype & RELAX_DELAY_SLOT)
5162 return _("Macro instruction expanded into multiple instructions"
5163 " in a branch delay slot");
5164 else if (subtype & RELAX_NOMACRO)
5165 return _("Macro instruction expanded into multiple instructions");
5166 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
5167 | RELAX_DELAY_SLOT_SIZE_SECOND))
5168 return ((subtype & RELAX_DELAY_SLOT_16BIT)
5169 ? _("Macro instruction expanded into a wrong size instruction"
5170 " in a 16-bit branch delay slot")
5171 : _("Macro instruction expanded into a wrong size instruction"
5172 " in a 32-bit branch delay slot"));
5177 /* Finish up a macro. Emit warnings as appropriate. */
5182 /* Relaxation warning flags. */
5183 relax_substateT subtype = 0;
5185 /* Check delay slot size requirements. */
5186 if (mips_macro_warning.delay_slot_length == 2)
5187 subtype |= RELAX_DELAY_SLOT_16BIT;
5188 if (mips_macro_warning.delay_slot_length != 0)
5190 if (mips_macro_warning.delay_slot_length
5191 != mips_macro_warning.first_insn_sizes[0])
5192 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
5193 if (mips_macro_warning.delay_slot_length
5194 != mips_macro_warning.first_insn_sizes[1])
5195 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
5198 /* Check instruction count requirements. */
5199 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
5201 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
5202 subtype |= RELAX_SECOND_LONGER;
5203 if (mips_opts.warn_about_macros)
5204 subtype |= RELAX_NOMACRO;
5205 if (mips_macro_warning.delay_slot_p)
5206 subtype |= RELAX_DELAY_SLOT;
5209 /* If both alternatives fail to fill a delay slot correctly,
5210 emit the warning now. */
5211 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
5212 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
5217 s = subtype & (RELAX_DELAY_SLOT_16BIT
5218 | RELAX_DELAY_SLOT_SIZE_FIRST
5219 | RELAX_DELAY_SLOT_SIZE_SECOND);
5220 msg = macro_warning (s);
5222 as_warn ("%s", msg);
5226 /* If both implementations are longer than 1 instruction, then emit the
5228 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
5233 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
5234 msg = macro_warning (s);
5236 as_warn ("%s", msg);
5240 /* If any flags still set, then one implementation might need a warning
5241 and the other either will need one of a different kind or none at all.
5242 Pass any remaining flags over to relaxation. */
5243 if (mips_macro_warning.first_frag != NULL)
5244 mips_macro_warning.first_frag->fr_subtype |= subtype;
5247 /* Instruction operand formats used in macros that vary between
5248 standard MIPS and microMIPS code. */
5250 static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } };
5251 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
5252 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
5253 static const char * const lui_fmt[2] = { "t,u", "s,u" };
5254 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
5255 static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } };
5256 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
5257 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
5259 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
5260 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
5261 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
5262 #define LUI_FMT (lui_fmt[mips_opts.micromips])
5263 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
5264 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
5265 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
5266 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
5268 /* Read a macro's relocation codes from *ARGS and store them in *R.
5269 The first argument in *ARGS will be either the code for a single
5270 relocation or -1 followed by the three codes that make up a
5271 composite relocation. */
5274 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
5278 next = va_arg (*args, int);
5280 r[0] = (bfd_reloc_code_real_type) next;
5283 for (i = 0; i < 3; i++)
5284 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
5285 /* This function is only used for 16-bit relocation fields.
5286 To make the macro code simpler, treat an unrelocated value
5287 in the same way as BFD_RELOC_LO16. */
5288 if (r[0] == BFD_RELOC_UNUSED)
5289 r[0] = BFD_RELOC_LO16;
5293 /* Build an instruction created by a macro expansion. This is passed
5294 a pointer to the count of instructions created so far, an
5295 expression, the name of the instruction to build, an operand format
5296 string, and corresponding arguments. */
5299 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
5301 const struct mips_opcode *mo = NULL;
5302 bfd_reloc_code_real_type r[3];
5303 const struct mips_opcode *amo;
5304 struct hash_control *hash;
5305 struct mips_cl_insn insn;
5308 va_start (args, fmt);
5310 if (mips_opts.mips16)
5312 mips16_macro_build (ep, name, fmt, &args);
5317 r[0] = BFD_RELOC_UNUSED;
5318 r[1] = BFD_RELOC_UNUSED;
5319 r[2] = BFD_RELOC_UNUSED;
5320 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
5321 amo = (struct mips_opcode *) hash_find (hash, name);
5323 gas_assert (strcmp (name, amo->name) == 0);
5327 /* Search until we get a match for NAME. It is assumed here that
5328 macros will never generate MDMX, MIPS-3D, or MT instructions.
5329 We try to match an instruction that fulfils the branch delay
5330 slot instruction length requirement (if any) of the previous
5331 instruction. While doing this we record the first instruction
5332 seen that matches all the other conditions and use it anyway
5333 if the requirement cannot be met; we will issue an appropriate
5334 warning later on. */
5335 if (strcmp (fmt, amo->args) == 0
5336 && amo->pinfo != INSN_MACRO
5337 && is_opcode_valid (amo)
5338 && is_size_valid (amo))
5340 if (is_delay_slot_valid (amo))
5350 gas_assert (amo->name);
5352 while (strcmp (name, amo->name) == 0);
5355 create_insn (&insn, mo);
5373 INSERT_OPERAND (mips_opts.micromips,
5374 EXTLSB, insn, va_arg (args, int));
5379 /* Note that in the macro case, these arguments are already
5380 in MSB form. (When handling the instruction in the
5381 non-macro case, these arguments are sizes from which
5382 MSB values must be calculated.) */
5383 INSERT_OPERAND (mips_opts.micromips,
5384 INSMSB, insn, va_arg (args, int));
5388 gas_assert (!mips_opts.micromips);
5389 INSERT_OPERAND (0, CODE10, insn, va_arg (args, int));
5395 /* Note that in the macro case, these arguments are already
5396 in MSBD form. (When handling the instruction in the
5397 non-macro case, these arguments are sizes from which
5398 MSBD values must be calculated.) */
5399 INSERT_OPERAND (mips_opts.micromips,
5400 EXTMSBD, insn, va_arg (args, int));
5404 gas_assert (!mips_opts.micromips);
5405 INSERT_OPERAND (0, SEQI, insn, va_arg (args, int));
5409 INSERT_OPERAND (mips_opts.micromips, EVAOFFSET, insn, va_arg (args, int));
5418 INSERT_OPERAND (mips_opts.micromips, BP, insn, va_arg (args, int));
5422 gas_assert (mips_opts.micromips);
5426 INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int));
5430 INSERT_OPERAND (mips_opts.micromips, CODE, insn, va_arg (args, int));
5434 gas_assert (!mips_opts.micromips);
5436 INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int));
5440 if (mips_opts.micromips)
5441 INSERT_OPERAND (1, RS, insn, va_arg (args, int));
5443 INSERT_OPERAND (0, RD, insn, va_arg (args, int));
5447 gas_assert (!mips_opts.micromips);
5449 INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int));
5453 gas_assert (!mips_opts.micromips);
5455 int tmp = va_arg (args, int);
5457 INSERT_OPERAND (0, RT, insn, tmp);
5458 INSERT_OPERAND (0, RD, insn, tmp);
5464 gas_assert (!mips_opts.micromips);
5465 INSERT_OPERAND (0, FS, insn, va_arg (args, int));
5472 INSERT_OPERAND (mips_opts.micromips,
5473 SHAMT, insn, va_arg (args, int));
5477 gas_assert (!mips_opts.micromips);
5478 INSERT_OPERAND (0, FD, insn, va_arg (args, int));
5482 gas_assert (!mips_opts.micromips);
5483 INSERT_OPERAND (0, CODE20, insn, va_arg (args, int));
5487 gas_assert (!mips_opts.micromips);
5488 INSERT_OPERAND (0, CODE19, insn, va_arg (args, int));
5492 gas_assert (!mips_opts.micromips);
5493 INSERT_OPERAND (0, CODE2, insn, va_arg (args, int));
5500 INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int));
5505 macro_read_relocs (&args, r);
5506 gas_assert (*r == BFD_RELOC_GPREL16
5507 || *r == BFD_RELOC_MIPS_HIGHER
5508 || *r == BFD_RELOC_HI16_S
5509 || *r == BFD_RELOC_LO16
5510 || *r == BFD_RELOC_MIPS_GOT_OFST);
5514 macro_read_relocs (&args, r);
5518 macro_read_relocs (&args, r);
5519 gas_assert (ep != NULL
5520 && (ep->X_op == O_constant
5521 || (ep->X_op == O_symbol
5522 && (*r == BFD_RELOC_MIPS_HIGHEST
5523 || *r == BFD_RELOC_HI16_S
5524 || *r == BFD_RELOC_HI16
5525 || *r == BFD_RELOC_GPREL16
5526 || *r == BFD_RELOC_MIPS_GOT_HI16
5527 || *r == BFD_RELOC_MIPS_CALL_HI16))));
5531 gas_assert (ep != NULL);
5534 * This allows macro() to pass an immediate expression for
5535 * creating short branches without creating a symbol.
5537 * We don't allow branch relaxation for these branches, as
5538 * they should only appear in ".set nomacro" anyway.
5540 if (ep->X_op == O_constant)
5542 /* For microMIPS we always use relocations for branches.
5543 So we should not resolve immediate values. */
5544 gas_assert (!mips_opts.micromips);
5546 if ((ep->X_add_number & 3) != 0)
5547 as_bad (_("branch to misaligned address (0x%lx)"),
5548 (unsigned long) ep->X_add_number);
5549 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
5550 as_bad (_("branch address range overflow (0x%lx)"),
5551 (unsigned long) ep->X_add_number);
5552 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
5556 *r = BFD_RELOC_16_PCREL_S2;
5560 gas_assert (ep != NULL);
5561 *r = BFD_RELOC_MIPS_JMP;
5565 gas_assert (!mips_opts.micromips);
5566 INSERT_OPERAND (0, COPZ, insn, va_arg (args, unsigned long));
5570 INSERT_OPERAND (mips_opts.micromips,
5571 CACHE, insn, va_arg (args, unsigned long));
5575 gas_assert (mips_opts.micromips);
5576 INSERT_OPERAND (1, TRAP, insn, va_arg (args, int));
5580 gas_assert (mips_opts.micromips);
5581 INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int));
5585 INSERT_OPERAND (mips_opts.micromips,
5586 3BITPOS, insn, va_arg (args, unsigned int));
5590 INSERT_OPERAND (mips_opts.micromips,
5591 OFFSET12, insn, va_arg (args, unsigned long));
5595 gas_assert (mips_opts.micromips);
5596 INSERT_OPERAND (1, BCC, insn, va_arg (args, int));
5599 case 'm': /* Opcode extension character. */
5600 gas_assert (mips_opts.micromips);
5604 INSERT_OPERAND (1, MJ, insn, va_arg (args, int));
5608 INSERT_OPERAND (1, MP, insn, va_arg (args, int));
5612 INSERT_OPERAND (1, IMMF, insn, va_arg (args, int));
5626 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5628 append_insn (&insn, ep, r, TRUE);
5632 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
5635 struct mips_opcode *mo;
5636 struct mips_cl_insn insn;
5637 bfd_reloc_code_real_type r[3]
5638 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
5640 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
5642 gas_assert (strcmp (name, mo->name) == 0);
5644 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
5647 gas_assert (mo->name);
5648 gas_assert (strcmp (name, mo->name) == 0);
5651 create_insn (&insn, mo);
5669 MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int));
5674 MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int));
5678 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int));
5682 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int));
5692 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int));
5699 regno = va_arg (*args, int);
5700 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
5701 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
5724 gas_assert (ep != NULL);
5726 if (ep->X_op != O_constant)
5727 *r = (int) BFD_RELOC_UNUSED + c;
5728 else if (calculate_reloc (*r, ep->X_add_number, &value))
5730 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode);
5732 *r = BFD_RELOC_UNUSED;
5738 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int));
5745 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5747 append_insn (&insn, ep, r, TRUE);
5751 * Sign-extend 32-bit mode constants that have bit 31 set and all
5752 * higher bits unset.
5755 normalize_constant_expr (expressionS *ex)
5757 if (ex->X_op == O_constant
5758 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5759 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5764 * Sign-extend 32-bit mode address offsets that have bit 31 set and
5765 * all higher bits unset.
5768 normalize_address_expr (expressionS *ex)
5770 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
5771 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
5772 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5773 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5778 * Generate a "jalr" instruction with a relocation hint to the called
5779 * function. This occurs in NewABI PIC code.
5782 macro_build_jalr (expressionS *ep, int cprestore)
5784 static const bfd_reloc_code_real_type jalr_relocs[2]
5785 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
5786 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
5790 if (MIPS_JALR_HINT_P (ep))
5795 if (mips_opts.micromips)
5797 jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32
5798 ? "jalr" : "jalrs");
5799 if (MIPS_JALR_HINT_P (ep)
5801 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
5802 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
5804 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
5807 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
5808 if (MIPS_JALR_HINT_P (ep))
5809 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
5813 * Generate a "lui" instruction.
5816 macro_build_lui (expressionS *ep, int regnum)
5818 gas_assert (! mips_opts.mips16);
5820 if (ep->X_op != O_constant)
5822 gas_assert (ep->X_op == O_symbol);
5823 /* _gp_disp is a special case, used from s_cpload.
5824 __gnu_local_gp is used if mips_no_shared. */
5825 gas_assert (mips_pic == NO_PIC
5827 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
5828 || (! mips_in_shared
5829 && strcmp (S_GET_NAME (ep->X_add_symbol),
5830 "__gnu_local_gp") == 0));
5833 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
5836 /* Generate a sequence of instructions to do a load or store from a constant
5837 offset off of a base register (breg) into/from a target register (treg),
5838 using AT if necessary. */
5840 macro_build_ldst_constoffset (expressionS *ep, const char *op,
5841 int treg, int breg, int dbl)
5843 gas_assert (ep->X_op == O_constant);
5845 /* Sign-extending 32-bit constants makes their handling easier. */
5847 normalize_constant_expr (ep);
5849 /* Right now, this routine can only handle signed 32-bit constants. */
5850 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
5851 as_warn (_("operand overflow"));
5853 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
5855 /* Signed 16-bit offset will fit in the op. Easy! */
5856 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
5860 /* 32-bit offset, need multiple instructions and AT, like:
5861 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
5862 addu $tempreg,$tempreg,$breg
5863 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
5864 to handle the complete offset. */
5865 macro_build_lui (ep, AT);
5866 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
5867 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
5870 as_bad (_("Macro used $at after \".set noat\""));
5875 * Generates code to set the $at register to true (one)
5876 * if reg is less than the immediate expression.
5879 set_at (int reg, int unsignedp)
5881 if (imm_expr.X_op == O_constant
5882 && imm_expr.X_add_number >= -0x8000
5883 && imm_expr.X_add_number < 0x8000)
5884 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
5885 AT, reg, BFD_RELOC_LO16);
5888 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5889 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
5893 /* Warn if an expression is not a constant. */
5896 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
5898 if (ex->X_op == O_big)
5899 as_bad (_("unsupported large constant"));
5900 else if (ex->X_op != O_constant)
5901 as_bad (_("Instruction %s requires absolute expression"),
5904 if (HAVE_32BIT_GPRS)
5905 normalize_constant_expr (ex);
5908 /* Count the leading zeroes by performing a binary chop. This is a
5909 bulky bit of source, but performance is a LOT better for the
5910 majority of values than a simple loop to count the bits:
5911 for (lcnt = 0; (lcnt < 32); lcnt++)
5912 if ((v) & (1 << (31 - lcnt)))
5914 However it is not code size friendly, and the gain will drop a bit
5915 on certain cached systems.
5917 #define COUNT_TOP_ZEROES(v) \
5918 (((v) & ~0xffff) == 0 \
5919 ? ((v) & ~0xff) == 0 \
5920 ? ((v) & ~0xf) == 0 \
5921 ? ((v) & ~0x3) == 0 \
5922 ? ((v) & ~0x1) == 0 \
5927 : ((v) & ~0x7) == 0 \
5930 : ((v) & ~0x3f) == 0 \
5931 ? ((v) & ~0x1f) == 0 \
5934 : ((v) & ~0x7f) == 0 \
5937 : ((v) & ~0xfff) == 0 \
5938 ? ((v) & ~0x3ff) == 0 \
5939 ? ((v) & ~0x1ff) == 0 \
5942 : ((v) & ~0x7ff) == 0 \
5945 : ((v) & ~0x3fff) == 0 \
5946 ? ((v) & ~0x1fff) == 0 \
5949 : ((v) & ~0x7fff) == 0 \
5952 : ((v) & ~0xffffff) == 0 \
5953 ? ((v) & ~0xfffff) == 0 \
5954 ? ((v) & ~0x3ffff) == 0 \
5955 ? ((v) & ~0x1ffff) == 0 \
5958 : ((v) & ~0x7ffff) == 0 \
5961 : ((v) & ~0x3fffff) == 0 \
5962 ? ((v) & ~0x1fffff) == 0 \
5965 : ((v) & ~0x7fffff) == 0 \
5968 : ((v) & ~0xfffffff) == 0 \
5969 ? ((v) & ~0x3ffffff) == 0 \
5970 ? ((v) & ~0x1ffffff) == 0 \
5973 : ((v) & ~0x7ffffff) == 0 \
5976 : ((v) & ~0x3fffffff) == 0 \
5977 ? ((v) & ~0x1fffffff) == 0 \
5980 : ((v) & ~0x7fffffff) == 0 \
5985 * This routine generates the least number of instructions necessary to load
5986 * an absolute expression value into a register.
5989 load_register (int reg, expressionS *ep, int dbl)
5992 expressionS hi32, lo32;
5994 if (ep->X_op != O_big)
5996 gas_assert (ep->X_op == O_constant);
5998 /* Sign-extending 32-bit constants makes their handling easier. */
6000 normalize_constant_expr (ep);
6002 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
6004 /* We can handle 16 bit signed values with an addiu to
6005 $zero. No need to ever use daddiu here, since $zero and
6006 the result are always correct in 32 bit mode. */
6007 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
6010 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
6012 /* We can handle 16 bit unsigned values with an ori to
6014 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
6017 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
6019 /* 32 bit values require an lui. */
6020 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
6021 if ((ep->X_add_number & 0xffff) != 0)
6022 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
6027 /* The value is larger than 32 bits. */
6029 if (!dbl || HAVE_32BIT_GPRS)
6033 sprintf_vma (value, ep->X_add_number);
6034 as_bad (_("Number (0x%s) larger than 32 bits"), value);
6035 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
6039 if (ep->X_op != O_big)
6042 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
6043 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
6044 hi32.X_add_number &= 0xffffffff;
6046 lo32.X_add_number &= 0xffffffff;
6050 gas_assert (ep->X_add_number > 2);
6051 if (ep->X_add_number == 3)
6052 generic_bignum[3] = 0;
6053 else if (ep->X_add_number > 4)
6054 as_bad (_("Number larger than 64 bits"));
6055 lo32.X_op = O_constant;
6056 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
6057 hi32.X_op = O_constant;
6058 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
6061 if (hi32.X_add_number == 0)
6066 unsigned long hi, lo;
6068 if (hi32.X_add_number == (offsetT) 0xffffffff)
6070 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
6072 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
6075 if (lo32.X_add_number & 0x80000000)
6077 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
6078 if (lo32.X_add_number & 0xffff)
6079 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
6084 /* Check for 16bit shifted constant. We know that hi32 is
6085 non-zero, so start the mask on the first bit of the hi32
6090 unsigned long himask, lomask;
6094 himask = 0xffff >> (32 - shift);
6095 lomask = (0xffff << shift) & 0xffffffff;
6099 himask = 0xffff << (shift - 32);
6102 if ((hi32.X_add_number & ~(offsetT) himask) == 0
6103 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
6107 tmp.X_op = O_constant;
6109 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
6110 | (lo32.X_add_number >> shift));
6112 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
6113 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
6114 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
6115 reg, reg, (shift >= 32) ? shift - 32 : shift);
6120 while (shift <= (64 - 16));
6122 /* Find the bit number of the lowest one bit, and store the
6123 shifted value in hi/lo. */
6124 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
6125 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
6129 while ((lo & 1) == 0)
6134 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
6140 while ((hi & 1) == 0)
6149 /* Optimize if the shifted value is a (power of 2) - 1. */
6150 if ((hi == 0 && ((lo + 1) & lo) == 0)
6151 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
6153 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
6158 /* This instruction will set the register to be all
6160 tmp.X_op = O_constant;
6161 tmp.X_add_number = (offsetT) -1;
6162 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
6166 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
6167 reg, reg, (bit >= 32) ? bit - 32 : bit);
6169 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
6170 reg, reg, (shift >= 32) ? shift - 32 : shift);
6175 /* Sign extend hi32 before calling load_register, because we can
6176 generally get better code when we load a sign extended value. */
6177 if ((hi32.X_add_number & 0x80000000) != 0)
6178 hi32.X_add_number |= ~(offsetT) 0xffffffff;
6179 load_register (reg, &hi32, 0);
6182 if ((lo32.X_add_number & 0xffff0000) == 0)
6186 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
6194 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
6196 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
6197 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
6203 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
6207 mid16.X_add_number >>= 16;
6208 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
6209 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
6212 if ((lo32.X_add_number & 0xffff) != 0)
6213 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
6217 load_delay_nop (void)
6219 if (!gpr_interlocks)
6220 macro_build (NULL, "nop", "");
6223 /* Load an address into a register. */
6226 load_address (int reg, expressionS *ep, int *used_at)
6228 if (ep->X_op != O_constant
6229 && ep->X_op != O_symbol)
6231 as_bad (_("expression too complex"));
6232 ep->X_op = O_constant;
6235 if (ep->X_op == O_constant)
6237 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
6241 if (mips_pic == NO_PIC)
6243 /* If this is a reference to a GP relative symbol, we want
6244 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
6246 lui $reg,<sym> (BFD_RELOC_HI16_S)
6247 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6248 If we have an addend, we always use the latter form.
6250 With 64bit address space and a usable $at we want
6251 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6252 lui $at,<sym> (BFD_RELOC_HI16_S)
6253 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
6254 daddiu $at,<sym> (BFD_RELOC_LO16)
6258 If $at is already in use, we use a path which is suboptimal
6259 on superscalar processors.
6260 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6261 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
6263 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
6265 daddiu $reg,<sym> (BFD_RELOC_LO16)
6267 For GP relative symbols in 64bit address space we can use
6268 the same sequence as in 32bit address space. */
6269 if (HAVE_64BIT_SYMBOLS)
6271 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
6272 && !nopic_need_relax (ep->X_add_symbol, 1))
6274 relax_start (ep->X_add_symbol);
6275 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
6276 mips_gp_register, BFD_RELOC_GPREL16);
6280 if (*used_at == 0 && mips_opts.at)
6282 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
6283 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
6284 macro_build (ep, "daddiu", "t,r,j", reg, reg,
6285 BFD_RELOC_MIPS_HIGHER);
6286 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
6287 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
6288 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
6293 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
6294 macro_build (ep, "daddiu", "t,r,j", reg, reg,
6295 BFD_RELOC_MIPS_HIGHER);
6296 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
6297 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
6298 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
6299 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
6302 if (mips_relax.sequence)
6307 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
6308 && !nopic_need_relax (ep->X_add_symbol, 1))
6310 relax_start (ep->X_add_symbol);
6311 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
6312 mips_gp_register, BFD_RELOC_GPREL16);
6315 macro_build_lui (ep, reg);
6316 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
6317 reg, reg, BFD_RELOC_LO16);
6318 if (mips_relax.sequence)
6322 else if (!mips_big_got)
6326 /* If this is a reference to an external symbol, we want
6327 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6329 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6331 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6332 If there is a constant, it must be added in after.
6334 If we have NewABI, we want
6335 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6336 unless we're referencing a global symbol with a non-zero
6337 offset, in which case cst must be added separately. */
6340 if (ep->X_add_number)
6342 ex.X_add_number = ep->X_add_number;
6343 ep->X_add_number = 0;
6344 relax_start (ep->X_add_symbol);
6345 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6346 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6347 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6348 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6349 ex.X_op = O_constant;
6350 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
6351 reg, reg, BFD_RELOC_LO16);
6352 ep->X_add_number = ex.X_add_number;
6355 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6356 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6357 if (mips_relax.sequence)
6362 ex.X_add_number = ep->X_add_number;
6363 ep->X_add_number = 0;
6364 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6365 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6367 relax_start (ep->X_add_symbol);
6369 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6373 if (ex.X_add_number != 0)
6375 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6376 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6377 ex.X_op = O_constant;
6378 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
6379 reg, reg, BFD_RELOC_LO16);
6383 else if (mips_big_got)
6387 /* This is the large GOT case. If this is a reference to an
6388 external symbol, we want
6389 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6391 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
6393 Otherwise, for a reference to a local symbol in old ABI, we want
6394 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6396 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6397 If there is a constant, it must be added in after.
6399 In the NewABI, for local symbols, with or without offsets, we want:
6400 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6401 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6405 ex.X_add_number = ep->X_add_number;
6406 ep->X_add_number = 0;
6407 relax_start (ep->X_add_symbol);
6408 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
6409 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6410 reg, reg, mips_gp_register);
6411 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
6412 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
6413 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6414 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6415 else if (ex.X_add_number)
6417 ex.X_op = O_constant;
6418 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6422 ep->X_add_number = ex.X_add_number;
6424 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6425 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6426 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6427 BFD_RELOC_MIPS_GOT_OFST);
6432 ex.X_add_number = ep->X_add_number;
6433 ep->X_add_number = 0;
6434 relax_start (ep->X_add_symbol);
6435 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
6436 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6437 reg, reg, mips_gp_register);
6438 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
6439 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
6441 if (reg_needs_delay (mips_gp_register))
6443 /* We need a nop before loading from $gp. This special
6444 check is required because the lui which starts the main
6445 instruction stream does not refer to $gp, and so will not
6446 insert the nop which may be required. */
6447 macro_build (NULL, "nop", "");
6449 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6450 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6452 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6456 if (ex.X_add_number != 0)
6458 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6459 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6460 ex.X_op = O_constant;
6461 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6469 if (!mips_opts.at && *used_at == 1)
6470 as_bad (_("Macro used $at after \".set noat\""));
6473 /* Move the contents of register SOURCE into register DEST. */
6476 move_register (int dest, int source)
6478 /* Prefer to use a 16-bit microMIPS instruction unless the previous
6479 instruction specifically requires a 32-bit one. */
6480 if (mips_opts.micromips
6481 && !mips_opts.insn32
6482 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
6483 macro_build (NULL, "move", "mp,mj", dest, source);
6485 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
6489 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
6490 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
6491 The two alternatives are:
6493 Global symbol Local sybmol
6494 ------------- ------------
6495 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
6497 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
6499 load_got_offset emits the first instruction and add_got_offset
6500 emits the second for a 16-bit offset or add_got_offset_hilo emits
6501 a sequence to add a 32-bit offset using a scratch register. */
6504 load_got_offset (int dest, expressionS *local)
6509 global.X_add_number = 0;
6511 relax_start (local->X_add_symbol);
6512 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
6513 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6515 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
6516 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6521 add_got_offset (int dest, expressionS *local)
6525 global.X_op = O_constant;
6526 global.X_op_symbol = NULL;
6527 global.X_add_symbol = NULL;
6528 global.X_add_number = local->X_add_number;
6530 relax_start (local->X_add_symbol);
6531 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
6532 dest, dest, BFD_RELOC_LO16);
6534 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
6539 add_got_offset_hilo (int dest, expressionS *local, int tmp)
6542 int hold_mips_optimize;
6544 global.X_op = O_constant;
6545 global.X_op_symbol = NULL;
6546 global.X_add_symbol = NULL;
6547 global.X_add_number = local->X_add_number;
6549 relax_start (local->X_add_symbol);
6550 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
6552 /* Set mips_optimize around the lui instruction to avoid
6553 inserting an unnecessary nop after the lw. */
6554 hold_mips_optimize = mips_optimize;
6556 macro_build_lui (&global, tmp);
6557 mips_optimize = hold_mips_optimize;
6558 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
6561 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
6564 /* Emit a sequence of instructions to emulate a branch likely operation.
6565 BR is an ordinary branch corresponding to one to be emulated. BRNEG
6566 is its complementing branch with the original condition negated.
6567 CALL is set if the original branch specified the link operation.
6568 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
6570 Code like this is produced in the noreorder mode:
6575 delay slot (executed only if branch taken)
6583 delay slot (executed only if branch taken)
6586 In the reorder mode the delay slot would be filled with a nop anyway,
6587 so code produced is simply:
6592 This function is used when producing code for the microMIPS ASE that
6593 does not implement branch likely instructions in hardware. */
6596 macro_build_branch_likely (const char *br, const char *brneg,
6597 int call, expressionS *ep, const char *fmt,
6598 unsigned int sreg, unsigned int treg)
6600 int noreorder = mips_opts.noreorder;
6603 gas_assert (mips_opts.micromips);
6607 micromips_label_expr (&expr1);
6608 macro_build (&expr1, brneg, fmt, sreg, treg);
6609 macro_build (NULL, "nop", "");
6610 macro_build (ep, call ? "bal" : "b", "p");
6612 /* Set to true so that append_insn adds a label. */
6613 emit_branch_likely_macro = TRUE;
6617 macro_build (ep, br, fmt, sreg, treg);
6618 macro_build (NULL, "nop", "");
6623 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
6624 the condition code tested. EP specifies the branch target. */
6627 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
6654 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
6657 /* Emit a two-argument branch macro specified by TYPE, using SREG as
6658 the register tested. EP specifies the branch target. */
6661 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
6663 const char *brneg = NULL;
6673 br = mips_opts.micromips ? "bgez" : "bgezl";
6677 gas_assert (mips_opts.micromips);
6678 br = mips_opts.insn32 ? "bgezal" : "bgezals";
6686 br = mips_opts.micromips ? "bgtz" : "bgtzl";
6693 br = mips_opts.micromips ? "blez" : "blezl";
6700 br = mips_opts.micromips ? "bltz" : "bltzl";
6704 gas_assert (mips_opts.micromips);
6705 br = mips_opts.insn32 ? "bltzal" : "bltzals";
6712 if (mips_opts.micromips && brneg)
6713 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
6715 macro_build (ep, br, "s,p", sreg);
6718 /* Emit a three-argument branch macro specified by TYPE, using SREG and
6719 TREG as the registers tested. EP specifies the branch target. */
6722 macro_build_branch_rsrt (int type, expressionS *ep,
6723 unsigned int sreg, unsigned int treg)
6725 const char *brneg = NULL;
6737 br = mips_opts.micromips ? "beq" : "beql";
6746 br = mips_opts.micromips ? "bne" : "bnel";
6752 if (mips_opts.micromips && brneg)
6753 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
6755 macro_build (ep, br, "s,t,p", sreg, treg);
6758 /* Return the high part that should be loaded in order to make the low
6759 part of VALUE accessible using an offset of OFFBITS bits. */
6762 offset_high_part (offsetT value, unsigned int offbits)
6769 bias = 1 << (offbits - 1);
6770 low_mask = bias * 2 - 1;
6771 return (value + bias) & ~low_mask;
6774 /* Return true if the value stored in offset_expr and offset_reloc
6775 fits into a signed offset of OFFBITS bits. RANGE is the maximum
6776 amount that the caller wants to add without inducing overflow
6777 and ALIGN is the known alignment of the value in bytes. */
6780 small_offset_p (unsigned int range, unsigned int align, unsigned int offbits)
6784 /* Accept any relocation operator if overflow isn't a concern. */
6785 if (range < align && *offset_reloc != BFD_RELOC_UNUSED)
6788 /* These relocations are guaranteed not to overflow in correct links. */
6789 if (*offset_reloc == BFD_RELOC_MIPS_LITERAL
6790 || gprel16_reloc_p (*offset_reloc))
6793 if (offset_expr.X_op == O_constant
6794 && offset_high_part (offset_expr.X_add_number, offbits) == 0
6795 && offset_high_part (offset_expr.X_add_number + range, offbits) == 0)
6802 * This routine implements the seemingly endless macro or synthesized
6803 * instructions and addressing modes in the mips assembly language. Many
6804 * of these macros are simple and are similar to each other. These could
6805 * probably be handled by some kind of table or grammar approach instead of
6806 * this verbose method. Others are not simple macros but are more like
6807 * optimizing code generation.
6808 * One interesting optimization is when several store macros appear
6809 * consecutively that would load AT with the upper half of the same address.
6810 * The ensuing load upper instructions are ommited. This implies some kind
6811 * of global optimization. We currently only optimize within a single macro.
6812 * For many of the load and store macros if the address is specified as a
6813 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
6814 * first load register 'at' with zero and use it as the base register. The
6815 * mips assembler simply uses register $zero. Just one tiny optimization
6819 macro (struct mips_cl_insn *ip, char *str)
6821 unsigned int treg, sreg, dreg, breg;
6822 unsigned int tempreg;
6825 expressionS label_expr;
6840 bfd_boolean large_offset;
6842 int hold_mips_optimize;
6845 gas_assert (! mips_opts.mips16);
6847 treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
6848 dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
6849 sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
6850 mask = ip->insn_mo->mask;
6852 label_expr.X_op = O_constant;
6853 label_expr.X_op_symbol = NULL;
6854 label_expr.X_add_symbol = NULL;
6855 label_expr.X_add_number = 0;
6857 expr1.X_op = O_constant;
6858 expr1.X_op_symbol = NULL;
6859 expr1.X_add_symbol = NULL;
6860 expr1.X_add_number = 1;
6876 if (mips_opts.micromips)
6877 micromips_label_expr (&label_expr);
6879 label_expr.X_add_number = 8;
6880 macro_build (&label_expr, "bgez", "s,p", sreg);
6882 macro_build (NULL, "nop", "");
6884 move_register (dreg, sreg);
6885 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
6886 if (mips_opts.micromips)
6887 micromips_add_label ();
6904 if (!mips_opts.micromips)
6906 if (imm_expr.X_op == O_constant
6907 && imm_expr.X_add_number >= -0x200
6908 && imm_expr.X_add_number < 0x200)
6910 macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number);
6919 if (imm_expr.X_op == O_constant
6920 && imm_expr.X_add_number >= -0x8000
6921 && imm_expr.X_add_number < 0x8000)
6923 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
6928 load_register (AT, &imm_expr, dbl);
6929 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6948 if (imm_expr.X_op == O_constant
6949 && imm_expr.X_add_number >= 0
6950 && imm_expr.X_add_number < 0x10000)
6952 if (mask != M_NOR_I)
6953 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
6956 macro_build (&imm_expr, "ori", "t,r,i",
6957 treg, sreg, BFD_RELOC_LO16);
6958 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
6964 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
6965 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6969 switch (imm_expr.X_add_number)
6972 macro_build (NULL, "nop", "");
6975 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
6979 macro_build (NULL, "balign", "t,s,2", treg, sreg,
6980 (int) imm_expr.X_add_number);
6983 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
6984 (unsigned long) imm_expr.X_add_number);
6993 gas_assert (mips_opts.micromips);
6994 macro_build_branch_ccl (mask, &offset_expr,
6995 EXTRACT_OPERAND (1, BCC, *ip));
7002 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7008 load_register (treg, &imm_expr, HAVE_64BIT_GPRS);
7013 macro_build_branch_rsrt (mask, &offset_expr, sreg, treg);
7020 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg);
7022 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg);
7026 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
7027 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7028 &offset_expr, AT, ZERO);
7038 macro_build_branch_rs (mask, &offset_expr, sreg);
7044 /* Check for > max integer. */
7045 if (imm_expr.X_op == O_constant && imm_expr.X_add_number >= GPR_SMAX)
7048 /* Result is always false. */
7050 macro_build (NULL, "nop", "");
7052 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
7055 if (imm_expr.X_op != O_constant)
7056 as_bad (_("Unsupported large constant"));
7057 ++imm_expr.X_add_number;
7061 if (mask == M_BGEL_I)
7063 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7065 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
7066 &offset_expr, sreg);
7069 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
7071 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
7072 &offset_expr, sreg);
7075 if (imm_expr.X_op == O_constant && imm_expr.X_add_number <= GPR_SMIN)
7078 /* result is always true */
7079 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
7080 macro_build (&offset_expr, "b", "p");
7085 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7086 &offset_expr, AT, ZERO);
7095 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7096 &offset_expr, ZERO, treg);
7100 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
7101 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7102 &offset_expr, AT, ZERO);
7111 && imm_expr.X_op == O_constant
7112 && imm_expr.X_add_number == -1))
7114 if (imm_expr.X_op != O_constant)
7115 as_bad (_("Unsupported large constant"));
7116 ++imm_expr.X_add_number;
7120 if (mask == M_BGEUL_I)
7122 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7124 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
7125 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7126 &offset_expr, sreg, ZERO);
7131 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7132 &offset_expr, AT, ZERO);
7140 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg);
7142 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg);
7146 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
7147 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7148 &offset_expr, AT, ZERO);
7156 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7157 &offset_expr, sreg, ZERO);
7163 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
7164 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7165 &offset_expr, AT, ZERO);
7173 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
7175 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg);
7179 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
7180 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7181 &offset_expr, AT, ZERO);
7188 if (imm_expr.X_op == O_constant && imm_expr.X_add_number >= GPR_SMAX)
7190 if (imm_expr.X_op != O_constant)
7191 as_bad (_("Unsupported large constant"));
7192 ++imm_expr.X_add_number;
7196 if (mask == M_BLTL_I)
7198 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7199 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
7200 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
7201 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
7206 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7207 &offset_expr, AT, ZERO);
7215 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7216 &offset_expr, sreg, ZERO);
7222 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
7223 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7224 &offset_expr, AT, ZERO);
7233 && imm_expr.X_op == O_constant
7234 && imm_expr.X_add_number == -1))
7236 if (imm_expr.X_op != O_constant)
7237 as_bad (_("Unsupported large constant"));
7238 ++imm_expr.X_add_number;
7242 if (mask == M_BLTUL_I)
7244 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7246 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
7247 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7248 &offset_expr, sreg, ZERO);
7253 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7254 &offset_expr, AT, ZERO);
7262 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
7264 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg);
7268 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
7269 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7270 &offset_expr, AT, ZERO);
7280 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7281 &offset_expr, ZERO, treg);
7285 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
7286 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7287 &offset_expr, AT, ZERO);
7293 /* Use unsigned arithmetic. */
7297 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
7299 as_bad (_("Unsupported large constant"));
7304 pos = imm_expr.X_add_number;
7305 size = imm2_expr.X_add_number;
7310 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
7313 if (size == 0 || size > 64 || (pos + size - 1) > 63)
7315 as_bad (_("Improper extract size (%lu, position %lu)"),
7316 (unsigned long) size, (unsigned long) pos);
7320 if (size <= 32 && pos < 32)
7325 else if (size <= 32)
7335 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
7342 /* Use unsigned arithmetic. */
7346 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
7348 as_bad (_("Unsupported large constant"));
7353 pos = imm_expr.X_add_number;
7354 size = imm2_expr.X_add_number;
7359 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
7362 if (size == 0 || size > 64 || (pos + size - 1) > 63)
7364 as_bad (_("Improper insert size (%lu, position %lu)"),
7365 (unsigned long) size, (unsigned long) pos);
7369 if (pos < 32 && (pos + size - 1) < 32)
7384 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
7385 (int) (pos + size - 1));
7401 as_warn (_("Divide by zero."));
7403 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
7405 macro_build (NULL, "break", BRK_FMT, 7);
7412 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
7413 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
7417 if (mips_opts.micromips)
7418 micromips_label_expr (&label_expr);
7420 label_expr.X_add_number = 8;
7421 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
7422 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
7423 macro_build (NULL, "break", BRK_FMT, 7);
7424 if (mips_opts.micromips)
7425 micromips_add_label ();
7427 expr1.X_add_number = -1;
7429 load_register (AT, &expr1, dbl);
7430 if (mips_opts.micromips)
7431 micromips_label_expr (&label_expr);
7433 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
7434 macro_build (&label_expr, "bne", "s,t,p", treg, AT);
7437 expr1.X_add_number = 1;
7438 load_register (AT, &expr1, dbl);
7439 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
7443 expr1.X_add_number = 0x80000000;
7444 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
7448 macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6);
7449 /* We want to close the noreorder block as soon as possible, so
7450 that later insns are available for delay slot filling. */
7455 if (mips_opts.micromips)
7456 micromips_label_expr (&label_expr);
7458 label_expr.X_add_number = 8;
7459 macro_build (&label_expr, "bne", "s,t,p", sreg, AT);
7460 macro_build (NULL, "nop", "");
7462 /* We want to close the noreorder block as soon as possible, so
7463 that later insns are available for delay slot filling. */
7466 macro_build (NULL, "break", BRK_FMT, 6);
7468 if (mips_opts.micromips)
7469 micromips_add_label ();
7470 macro_build (NULL, s, MFHL_FMT, dreg);
7509 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7511 as_warn (_("Divide by zero."));
7513 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
7515 macro_build (NULL, "break", BRK_FMT, 7);
7518 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
7520 if (strcmp (s2, "mflo") == 0)
7521 move_register (dreg, sreg);
7523 move_register (dreg, ZERO);
7526 if (imm_expr.X_op == O_constant
7527 && imm_expr.X_add_number == -1
7528 && s[strlen (s) - 1] != 'u')
7530 if (strcmp (s2, "mflo") == 0)
7532 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
7535 move_register (dreg, ZERO);
7540 load_register (AT, &imm_expr, dbl);
7541 macro_build (NULL, s, "z,s,t", sreg, AT);
7542 macro_build (NULL, s2, MFHL_FMT, dreg);
7564 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
7565 macro_build (NULL, s, "z,s,t", sreg, treg);
7566 /* We want to close the noreorder block as soon as possible, so
7567 that later insns are available for delay slot filling. */
7572 if (mips_opts.micromips)
7573 micromips_label_expr (&label_expr);
7575 label_expr.X_add_number = 8;
7576 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
7577 macro_build (NULL, s, "z,s,t", sreg, treg);
7579 /* We want to close the noreorder block as soon as possible, so
7580 that later insns are available for delay slot filling. */
7582 macro_build (NULL, "break", BRK_FMT, 7);
7583 if (mips_opts.micromips)
7584 micromips_add_label ();
7586 macro_build (NULL, s2, MFHL_FMT, dreg);
7598 /* Load the address of a symbol into a register. If breg is not
7599 zero, we then add a base register to it. */
7601 if (dbl && HAVE_32BIT_GPRS)
7602 as_warn (_("dla used to load 32-bit register"));
7604 if (!dbl && HAVE_64BIT_OBJECTS)
7605 as_warn (_("la used to load 64-bit address"));
7607 if (small_offset_p (0, align, 16))
7609 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", treg, breg,
7610 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
7614 if (mips_opts.at && (treg == breg))
7624 if (offset_expr.X_op != O_symbol
7625 && offset_expr.X_op != O_constant)
7627 as_bad (_("Expression too complex"));
7628 offset_expr.X_op = O_constant;
7631 if (offset_expr.X_op == O_constant)
7632 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
7633 else if (mips_pic == NO_PIC)
7635 /* If this is a reference to a GP relative symbol, we want
7636 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
7638 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
7639 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7640 If we have a constant, we need two instructions anyhow,
7641 so we may as well always use the latter form.
7643 With 64bit address space and a usable $at we want
7644 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7645 lui $at,<sym> (BFD_RELOC_HI16_S)
7646 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7647 daddiu $at,<sym> (BFD_RELOC_LO16)
7649 daddu $tempreg,$tempreg,$at
7651 If $at is already in use, we use a path which is suboptimal
7652 on superscalar processors.
7653 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7654 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7656 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
7658 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
7660 For GP relative symbols in 64bit address space we can use
7661 the same sequence as in 32bit address space. */
7662 if (HAVE_64BIT_SYMBOLS)
7664 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7665 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7667 relax_start (offset_expr.X_add_symbol);
7668 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7669 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7673 if (used_at == 0 && mips_opts.at)
7675 macro_build (&offset_expr, "lui", LUI_FMT,
7676 tempreg, BFD_RELOC_MIPS_HIGHEST);
7677 macro_build (&offset_expr, "lui", LUI_FMT,
7678 AT, BFD_RELOC_HI16_S);
7679 macro_build (&offset_expr, "daddiu", "t,r,j",
7680 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7681 macro_build (&offset_expr, "daddiu", "t,r,j",
7682 AT, AT, BFD_RELOC_LO16);
7683 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
7684 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
7689 macro_build (&offset_expr, "lui", LUI_FMT,
7690 tempreg, BFD_RELOC_MIPS_HIGHEST);
7691 macro_build (&offset_expr, "daddiu", "t,r,j",
7692 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7693 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7694 macro_build (&offset_expr, "daddiu", "t,r,j",
7695 tempreg, tempreg, BFD_RELOC_HI16_S);
7696 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7697 macro_build (&offset_expr, "daddiu", "t,r,j",
7698 tempreg, tempreg, BFD_RELOC_LO16);
7701 if (mips_relax.sequence)
7706 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7707 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7709 relax_start (offset_expr.X_add_symbol);
7710 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7711 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7714 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
7715 as_bad (_("Offset too large"));
7716 macro_build_lui (&offset_expr, tempreg);
7717 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7718 tempreg, tempreg, BFD_RELOC_LO16);
7719 if (mips_relax.sequence)
7723 else if (!mips_big_got && !HAVE_NEWABI)
7725 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7727 /* If this is a reference to an external symbol, and there
7728 is no constant, we want
7729 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7730 or for lca or if tempreg is PIC_CALL_REG
7731 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7732 For a local symbol, we want
7733 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7735 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7737 If we have a small constant, and this is a reference to
7738 an external symbol, we want
7739 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7741 addiu $tempreg,$tempreg,<constant>
7742 For a local symbol, we want the same instruction
7743 sequence, but we output a BFD_RELOC_LO16 reloc on the
7746 If we have a large constant, and this is a reference to
7747 an external symbol, we want
7748 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7749 lui $at,<hiconstant>
7750 addiu $at,$at,<loconstant>
7751 addu $tempreg,$tempreg,$at
7752 For a local symbol, we want the same instruction
7753 sequence, but we output a BFD_RELOC_LO16 reloc on the
7757 if (offset_expr.X_add_number == 0)
7759 if (mips_pic == SVR4_PIC
7761 && (call || tempreg == PIC_CALL_REG))
7762 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
7764 relax_start (offset_expr.X_add_symbol);
7765 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7766 lw_reloc_type, mips_gp_register);
7769 /* We're going to put in an addu instruction using
7770 tempreg, so we may as well insert the nop right
7775 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7776 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
7778 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7779 tempreg, tempreg, BFD_RELOC_LO16);
7781 /* FIXME: If breg == 0, and the next instruction uses
7782 $tempreg, then if this variant case is used an extra
7783 nop will be generated. */
7785 else if (offset_expr.X_add_number >= -0x8000
7786 && offset_expr.X_add_number < 0x8000)
7788 load_got_offset (tempreg, &offset_expr);
7790 add_got_offset (tempreg, &offset_expr);
7794 expr1.X_add_number = offset_expr.X_add_number;
7795 offset_expr.X_add_number =
7796 SEXT_16BIT (offset_expr.X_add_number);
7797 load_got_offset (tempreg, &offset_expr);
7798 offset_expr.X_add_number = expr1.X_add_number;
7799 /* If we are going to add in a base register, and the
7800 target register and the base register are the same,
7801 then we are using AT as a temporary register. Since
7802 we want to load the constant into AT, we add our
7803 current AT (from the global offset table) and the
7804 register into the register now, and pretend we were
7805 not using a base register. */
7809 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7814 add_got_offset_hilo (tempreg, &offset_expr, AT);
7818 else if (!mips_big_got && HAVE_NEWABI)
7820 int add_breg_early = 0;
7822 /* If this is a reference to an external, and there is no
7823 constant, or local symbol (*), with or without a
7825 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7826 or for lca or if tempreg is PIC_CALL_REG
7827 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7829 If we have a small constant, and this is a reference to
7830 an external symbol, we want
7831 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7832 addiu $tempreg,$tempreg,<constant>
7834 If we have a large constant, and this is a reference to
7835 an external symbol, we want
7836 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7837 lui $at,<hiconstant>
7838 addiu $at,$at,<loconstant>
7839 addu $tempreg,$tempreg,$at
7841 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
7842 local symbols, even though it introduces an additional
7845 if (offset_expr.X_add_number)
7847 expr1.X_add_number = offset_expr.X_add_number;
7848 offset_expr.X_add_number = 0;
7850 relax_start (offset_expr.X_add_symbol);
7851 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7852 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7854 if (expr1.X_add_number >= -0x8000
7855 && expr1.X_add_number < 0x8000)
7857 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7858 tempreg, tempreg, BFD_RELOC_LO16);
7860 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
7862 /* If we are going to add in a base register, and the
7863 target register and the base register are the same,
7864 then we are using AT as a temporary register. Since
7865 we want to load the constant into AT, we add our
7866 current AT (from the global offset table) and the
7867 register into the register now, and pretend we were
7868 not using a base register. */
7873 gas_assert (tempreg == AT);
7874 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7880 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7881 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7887 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7890 offset_expr.X_add_number = expr1.X_add_number;
7892 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7893 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7896 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7897 treg, tempreg, breg);
7903 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
7905 relax_start (offset_expr.X_add_symbol);
7906 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7907 BFD_RELOC_MIPS_CALL16, mips_gp_register);
7909 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7910 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7915 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7916 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7919 else if (mips_big_got && !HAVE_NEWABI)
7922 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
7923 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
7924 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7926 /* This is the large GOT case. If this is a reference to an
7927 external symbol, and there is no constant, we want
7928 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7929 addu $tempreg,$tempreg,$gp
7930 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7931 or for lca or if tempreg is PIC_CALL_REG
7932 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7933 addu $tempreg,$tempreg,$gp
7934 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7935 For a local symbol, we want
7936 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7938 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7940 If we have a small constant, and this is a reference to
7941 an external symbol, we want
7942 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7943 addu $tempreg,$tempreg,$gp
7944 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7946 addiu $tempreg,$tempreg,<constant>
7947 For a local symbol, we want
7948 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7950 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
7952 If we have a large constant, and this is a reference to
7953 an external symbol, we want
7954 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7955 addu $tempreg,$tempreg,$gp
7956 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7957 lui $at,<hiconstant>
7958 addiu $at,$at,<loconstant>
7959 addu $tempreg,$tempreg,$at
7960 For a local symbol, we want
7961 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7962 lui $at,<hiconstant>
7963 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
7964 addu $tempreg,$tempreg,$at
7967 expr1.X_add_number = offset_expr.X_add_number;
7968 offset_expr.X_add_number = 0;
7969 relax_start (offset_expr.X_add_symbol);
7970 gpdelay = reg_needs_delay (mips_gp_register);
7971 if (expr1.X_add_number == 0 && breg == 0
7972 && (call || tempreg == PIC_CALL_REG))
7974 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
7975 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
7977 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
7978 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7979 tempreg, tempreg, mips_gp_register);
7980 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7981 tempreg, lw_reloc_type, tempreg);
7982 if (expr1.X_add_number == 0)
7986 /* We're going to put in an addu instruction using
7987 tempreg, so we may as well insert the nop right
7992 else if (expr1.X_add_number >= -0x8000
7993 && expr1.X_add_number < 0x8000)
7996 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7997 tempreg, tempreg, BFD_RELOC_LO16);
8001 /* If we are going to add in a base register, and the
8002 target register and the base register are the same,
8003 then we are using AT as a temporary register. Since
8004 we want to load the constant into AT, we add our
8005 current AT (from the global offset table) and the
8006 register into the register now, and pretend we were
8007 not using a base register. */
8012 gas_assert (tempreg == AT);
8014 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8019 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
8020 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
8024 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number);
8029 /* This is needed because this instruction uses $gp, but
8030 the first instruction on the main stream does not. */
8031 macro_build (NULL, "nop", "");
8034 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8035 local_reloc_type, mips_gp_register);
8036 if (expr1.X_add_number >= -0x8000
8037 && expr1.X_add_number < 0x8000)
8040 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8041 tempreg, tempreg, BFD_RELOC_LO16);
8042 /* FIXME: If add_number is 0, and there was no base
8043 register, the external symbol case ended with a load,
8044 so if the symbol turns out to not be external, and
8045 the next instruction uses tempreg, an unnecessary nop
8046 will be inserted. */
8052 /* We must add in the base register now, as in the
8053 external symbol case. */
8054 gas_assert (tempreg == AT);
8056 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8059 /* We set breg to 0 because we have arranged to add
8060 it in in both cases. */
8064 macro_build_lui (&expr1, AT);
8065 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8066 AT, AT, BFD_RELOC_LO16);
8067 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8068 tempreg, tempreg, AT);
8073 else if (mips_big_got && HAVE_NEWABI)
8075 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
8076 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
8077 int add_breg_early = 0;
8079 /* This is the large GOT case. If this is a reference to an
8080 external symbol, and there is no constant, we want
8081 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8082 add $tempreg,$tempreg,$gp
8083 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8084 or for lca or if tempreg is PIC_CALL_REG
8085 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
8086 add $tempreg,$tempreg,$gp
8087 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
8089 If we have a small constant, and this is a reference to
8090 an external symbol, we want
8091 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8092 add $tempreg,$tempreg,$gp
8093 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8094 addi $tempreg,$tempreg,<constant>
8096 If we have a large constant, and this is a reference to
8097 an external symbol, we want
8098 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8099 addu $tempreg,$tempreg,$gp
8100 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8101 lui $at,<hiconstant>
8102 addi $at,$at,<loconstant>
8103 add $tempreg,$tempreg,$at
8105 If we have NewABI, and we know it's a local symbol, we want
8106 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8107 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
8108 otherwise we have to resort to GOT_HI16/GOT_LO16. */
8110 relax_start (offset_expr.X_add_symbol);
8112 expr1.X_add_number = offset_expr.X_add_number;
8113 offset_expr.X_add_number = 0;
8115 if (expr1.X_add_number == 0 && breg == 0
8116 && (call || tempreg == PIC_CALL_REG))
8118 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
8119 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
8121 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
8122 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8123 tempreg, tempreg, mips_gp_register);
8124 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8125 tempreg, lw_reloc_type, tempreg);
8127 if (expr1.X_add_number == 0)
8129 else if (expr1.X_add_number >= -0x8000
8130 && expr1.X_add_number < 0x8000)
8132 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
8133 tempreg, tempreg, BFD_RELOC_LO16);
8135 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
8137 /* If we are going to add in a base register, and the
8138 target register and the base register are the same,
8139 then we are using AT as a temporary register. Since
8140 we want to load the constant into AT, we add our
8141 current AT (from the global offset table) and the
8142 register into the register now, and pretend we were
8143 not using a base register. */
8148 gas_assert (tempreg == AT);
8149 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8155 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
8156 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
8161 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
8164 offset_expr.X_add_number = expr1.X_add_number;
8165 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8166 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8167 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
8168 tempreg, BFD_RELOC_MIPS_GOT_OFST);
8171 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8172 treg, tempreg, breg);
8182 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
8186 gas_assert (!mips_opts.micromips);
8188 unsigned long temp = (treg << 16) | (0x01);
8189 macro_build (NULL, "c2", "C", temp);
8194 gas_assert (!mips_opts.micromips);
8196 unsigned long temp = (0x02);
8197 macro_build (NULL, "c2", "C", temp);
8202 gas_assert (!mips_opts.micromips);
8204 unsigned long temp = (treg << 16) | (0x02);
8205 macro_build (NULL, "c2", "C", temp);
8210 gas_assert (!mips_opts.micromips);
8211 macro_build (NULL, "c2", "C", 3);
8215 gas_assert (!mips_opts.micromips);
8217 unsigned long temp = (treg << 16) | 0x03;
8218 macro_build (NULL, "c2", "C", temp);
8223 /* The j instruction may not be used in PIC code, since it
8224 requires an absolute address. We convert it to a b
8226 if (mips_pic == NO_PIC)
8227 macro_build (&offset_expr, "j", "a");
8229 macro_build (&offset_expr, "b", "p");
8232 /* The jal instructions must be handled as macros because when
8233 generating PIC code they expand to multi-instruction
8234 sequences. Normally they are simple instructions. */
8239 gas_assert (mips_opts.micromips);
8240 if (mips_opts.insn32)
8242 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str);
8252 if (mips_pic == NO_PIC)
8254 s = jals ? "jalrs" : "jalr";
8255 if (mips_opts.micromips
8256 && !mips_opts.insn32
8258 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
8259 macro_build (NULL, s, "mj", sreg);
8261 macro_build (NULL, s, JALR_FMT, dreg, sreg);
8265 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
8266 && mips_cprestore_offset >= 0);
8268 if (sreg != PIC_CALL_REG)
8269 as_warn (_("MIPS PIC call to register other than $25"));
8271 s = ((mips_opts.micromips
8272 && !mips_opts.insn32
8273 && (!mips_opts.noreorder || cprestore))
8274 ? "jalrs" : "jalr");
8275 if (mips_opts.micromips
8276 && !mips_opts.insn32
8278 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
8279 macro_build (NULL, s, "mj", sreg);
8281 macro_build (NULL, s, JALR_FMT, dreg, sreg);
8282 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
8284 if (mips_cprestore_offset < 0)
8285 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8288 if (!mips_frame_reg_valid)
8290 as_warn (_("No .frame pseudo-op used in PIC code"));
8291 /* Quiet this warning. */
8292 mips_frame_reg_valid = 1;
8294 if (!mips_cprestore_valid)
8296 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8297 /* Quiet this warning. */
8298 mips_cprestore_valid = 1;
8300 if (mips_opts.noreorder)
8301 macro_build (NULL, "nop", "");
8302 expr1.X_add_number = mips_cprestore_offset;
8303 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
8306 HAVE_64BIT_ADDRESSES);
8314 gas_assert (mips_opts.micromips);
8315 if (mips_opts.insn32)
8317 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str);
8323 if (mips_pic == NO_PIC)
8324 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
8325 else if (mips_pic == SVR4_PIC)
8327 /* If this is a reference to an external symbol, and we are
8328 using a small GOT, we want
8329 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
8333 lw $gp,cprestore($sp)
8334 The cprestore value is set using the .cprestore
8335 pseudo-op. If we are using a big GOT, we want
8336 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
8338 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
8342 lw $gp,cprestore($sp)
8343 If the symbol is not external, we want
8344 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8346 addiu $25,$25,<sym> (BFD_RELOC_LO16)
8349 lw $gp,cprestore($sp)
8351 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
8352 sequences above, minus nops, unless the symbol is local,
8353 which enables us to use GOT_PAGE/GOT_OFST (big got) or
8359 relax_start (offset_expr.X_add_symbol);
8360 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8361 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
8364 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8365 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
8371 relax_start (offset_expr.X_add_symbol);
8372 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
8373 BFD_RELOC_MIPS_CALL_HI16);
8374 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
8375 PIC_CALL_REG, mips_gp_register);
8376 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8377 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
8380 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8381 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
8383 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8384 PIC_CALL_REG, PIC_CALL_REG,
8385 BFD_RELOC_MIPS_GOT_OFST);
8389 macro_build_jalr (&offset_expr, 0);
8393 relax_start (offset_expr.X_add_symbol);
8396 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8397 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
8406 gpdelay = reg_needs_delay (mips_gp_register);
8407 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
8408 BFD_RELOC_MIPS_CALL_HI16);
8409 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
8410 PIC_CALL_REG, mips_gp_register);
8411 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8412 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
8417 macro_build (NULL, "nop", "");
8419 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8420 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
8423 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8424 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
8426 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
8428 if (mips_cprestore_offset < 0)
8429 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8432 if (!mips_frame_reg_valid)
8434 as_warn (_("No .frame pseudo-op used in PIC code"));
8435 /* Quiet this warning. */
8436 mips_frame_reg_valid = 1;
8438 if (!mips_cprestore_valid)
8440 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8441 /* Quiet this warning. */
8442 mips_cprestore_valid = 1;
8444 if (mips_opts.noreorder)
8445 macro_build (NULL, "nop", "");
8446 expr1.X_add_number = mips_cprestore_offset;
8447 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
8450 HAVE_64BIT_ADDRESSES);
8454 else if (mips_pic == VXWORKS_PIC)
8455 as_bad (_("Non-PIC jump used in PIC library"));
8533 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
8539 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
8564 gas_assert (!mips_opts.micromips);
8567 /* Itbl support may require additional care here. */
8573 /* Itbl support may require additional care here. */
8579 offbits = (mips_opts.micromips ? 12 : 16);
8580 /* Itbl support may require additional care here. */
8584 gas_assert (!mips_opts.micromips);
8587 /* Itbl support may require additional care here. */
8593 offbits = (mips_opts.micromips ? 12 : 16);
8598 offbits = (mips_opts.micromips ? 12 : 16);
8603 /* Itbl support may require additional care here. */
8609 offbits = (mips_opts.micromips ? 12 : 16);
8610 /* Itbl support may require additional care here. */
8616 /* Itbl support may require additional care here. */
8622 /* Itbl support may require additional care here. */
8628 offbits = (mips_opts.micromips ? 12 : 16);
8633 offbits = (mips_opts.micromips ? 12 : 16);
8638 offbits = (mips_opts.micromips ? 12 : 16);
8643 offbits = (mips_opts.micromips ? 12 : 16);
8648 offbits = (mips_opts.micromips ? 12 : 16);
8651 gas_assert (mips_opts.micromips);
8658 gas_assert (mips_opts.micromips);
8665 gas_assert (mips_opts.micromips);
8671 gas_assert (mips_opts.micromips);
8678 /* We don't want to use $0 as tempreg. */
8679 if (breg == treg + lp || treg + lp == ZERO)
8682 tempreg = treg + lp;
8698 gas_assert (!mips_opts.micromips);
8701 /* Itbl support may require additional care here. */
8707 /* Itbl support may require additional care here. */
8713 offbits = (mips_opts.micromips ? 12 : 16);
8714 /* Itbl support may require additional care here. */
8718 gas_assert (!mips_opts.micromips);
8721 /* Itbl support may require additional care here. */
8727 offbits = (mips_opts.micromips ? 12 : 16);
8732 offbits = (mips_opts.micromips ? 12 : 16);
8737 offbits = (mips_opts.micromips ? 12 : 16);
8742 offbits = (mips_opts.micromips ? 12 : 16);
8746 fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)";
8747 offbits = (mips_opts.micromips ? 12 : 16);
8756 fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)";
8757 offbits = (mips_opts.micromips ? 12 : 16);
8768 /* Itbl support may require additional care here. */
8773 offbits = (mips_opts.micromips ? 12 : 16);
8774 /* Itbl support may require additional care here. */
8780 /* Itbl support may require additional care here. */
8784 gas_assert (!mips_opts.micromips);
8787 /* Itbl support may require additional care here. */
8793 offbits = (mips_opts.micromips ? 12 : 16);
8798 offbits = (mips_opts.micromips ? 12 : 16);
8801 gas_assert (mips_opts.micromips);
8807 gas_assert (mips_opts.micromips);
8813 gas_assert (mips_opts.micromips);
8819 gas_assert (mips_opts.micromips);
8827 if (small_offset_p (0, align, 16))
8829 /* The first case exists for M_LD_AB and M_SD_AB, which are
8830 macros for o32 but which should act like normal instructions
8833 macro_build (&offset_expr, s, fmt, treg, -1, offset_reloc[0],
8834 offset_reloc[1], offset_reloc[2], breg);
8835 else if (small_offset_p (0, align, offbits))
8838 macro_build (NULL, s, fmt, treg, breg);
8840 macro_build (NULL, s, fmt, treg,
8841 (unsigned long) offset_expr.X_add_number, breg);
8847 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8848 tempreg, breg, -1, offset_reloc[0],
8849 offset_reloc[1], offset_reloc[2]);
8851 macro_build (NULL, s, fmt, treg, tempreg);
8853 macro_build (NULL, s, fmt, treg, 0L, tempreg);
8861 if (offset_expr.X_op != O_constant
8862 && offset_expr.X_op != O_symbol)
8864 as_bad (_("Expression too complex"));
8865 offset_expr.X_op = O_constant;
8868 if (HAVE_32BIT_ADDRESSES
8869 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
8873 sprintf_vma (value, offset_expr.X_add_number);
8874 as_bad (_("Number (0x%s) larger than 32 bits"), value);
8877 /* A constant expression in PIC code can be handled just as it
8878 is in non PIC code. */
8879 if (offset_expr.X_op == O_constant)
8881 expr1.X_add_number = offset_high_part (offset_expr.X_add_number,
8882 offbits == 0 ? 16 : offbits);
8883 offset_expr.X_add_number -= expr1.X_add_number;
8885 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
8887 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8888 tempreg, tempreg, breg);
8891 if (offset_expr.X_add_number != 0)
8892 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
8893 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
8894 macro_build (NULL, s, fmt, treg, tempreg);
8896 else if (offbits == 16)
8897 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8899 macro_build (NULL, s, fmt, treg,
8900 (unsigned long) offset_expr.X_add_number, tempreg);
8902 else if (offbits != 16)
8904 /* The offset field is too narrow to be used for a low-part
8905 relocation, so load the whole address into the auxillary
8907 load_address (tempreg, &offset_expr, &used_at);
8909 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8910 tempreg, tempreg, breg);
8912 macro_build (NULL, s, fmt, treg, tempreg);
8914 macro_build (NULL, s, fmt, treg, 0L, tempreg);
8916 else if (mips_pic == NO_PIC)
8918 /* If this is a reference to a GP relative symbol, and there
8919 is no base register, we want
8920 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8921 Otherwise, if there is no base register, we want
8922 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8923 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8924 If we have a constant, we need two instructions anyhow,
8925 so we always use the latter form.
8927 If we have a base register, and this is a reference to a
8928 GP relative symbol, we want
8929 addu $tempreg,$breg,$gp
8930 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
8932 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8933 addu $tempreg,$tempreg,$breg
8934 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8935 With a constant we always use the latter case.
8937 With 64bit address space and no base register and $at usable,
8939 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8940 lui $at,<sym> (BFD_RELOC_HI16_S)
8941 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8944 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8945 If we have a base register, we want
8946 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8947 lui $at,<sym> (BFD_RELOC_HI16_S)
8948 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8952 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8954 Without $at we can't generate the optimal path for superscalar
8955 processors here since this would require two temporary registers.
8956 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8957 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8959 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8961 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8962 If we have a base register, we want
8963 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8964 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8966 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8968 daddu $tempreg,$tempreg,$breg
8969 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8971 For GP relative symbols in 64bit address space we can use
8972 the same sequence as in 32bit address space. */
8973 if (HAVE_64BIT_SYMBOLS)
8975 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8976 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8978 relax_start (offset_expr.X_add_symbol);
8981 macro_build (&offset_expr, s, fmt, treg,
8982 BFD_RELOC_GPREL16, mips_gp_register);
8986 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8987 tempreg, breg, mips_gp_register);
8988 macro_build (&offset_expr, s, fmt, treg,
8989 BFD_RELOC_GPREL16, tempreg);
8994 if (used_at == 0 && mips_opts.at)
8996 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8997 BFD_RELOC_MIPS_HIGHEST);
8998 macro_build (&offset_expr, "lui", LUI_FMT, AT,
9000 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
9001 tempreg, BFD_RELOC_MIPS_HIGHER);
9003 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
9004 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
9005 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
9006 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
9012 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
9013 BFD_RELOC_MIPS_HIGHEST);
9014 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
9015 tempreg, BFD_RELOC_MIPS_HIGHER);
9016 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
9017 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
9018 tempreg, BFD_RELOC_HI16_S);
9019 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
9021 macro_build (NULL, "daddu", "d,v,t",
9022 tempreg, tempreg, breg);
9023 macro_build (&offset_expr, s, fmt, treg,
9024 BFD_RELOC_LO16, tempreg);
9027 if (mips_relax.sequence)
9034 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
9035 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
9037 relax_start (offset_expr.X_add_symbol);
9038 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
9042 macro_build_lui (&offset_expr, tempreg);
9043 macro_build (&offset_expr, s, fmt, treg,
9044 BFD_RELOC_LO16, tempreg);
9045 if (mips_relax.sequence)
9050 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
9051 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
9053 relax_start (offset_expr.X_add_symbol);
9054 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9055 tempreg, breg, mips_gp_register);
9056 macro_build (&offset_expr, s, fmt, treg,
9057 BFD_RELOC_GPREL16, tempreg);
9060 macro_build_lui (&offset_expr, tempreg);
9061 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9062 tempreg, tempreg, breg);
9063 macro_build (&offset_expr, s, fmt, treg,
9064 BFD_RELOC_LO16, tempreg);
9065 if (mips_relax.sequence)
9069 else if (!mips_big_got)
9071 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
9073 /* If this is a reference to an external symbol, we want
9074 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9076 <op> $treg,0($tempreg)
9078 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9080 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9081 <op> $treg,0($tempreg)
9084 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9085 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
9087 If there is a base register, we add it to $tempreg before
9088 the <op>. If there is a constant, we stick it in the
9089 <op> instruction. We don't handle constants larger than
9090 16 bits, because we have no way to load the upper 16 bits
9091 (actually, we could handle them for the subset of cases
9092 in which we are not using $at). */
9093 gas_assert (offset_expr.X_op == O_symbol);
9096 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9097 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
9099 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9100 tempreg, tempreg, breg);
9101 macro_build (&offset_expr, s, fmt, treg,
9102 BFD_RELOC_MIPS_GOT_OFST, tempreg);
9105 expr1.X_add_number = offset_expr.X_add_number;
9106 offset_expr.X_add_number = 0;
9107 if (expr1.X_add_number < -0x8000
9108 || expr1.X_add_number >= 0x8000)
9109 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9110 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9111 lw_reloc_type, mips_gp_register);
9113 relax_start (offset_expr.X_add_symbol);
9115 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
9116 tempreg, BFD_RELOC_LO16);
9119 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9120 tempreg, tempreg, breg);
9121 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
9123 else if (mips_big_got && !HAVE_NEWABI)
9127 /* If this is a reference to an external symbol, we want
9128 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9129 addu $tempreg,$tempreg,$gp
9130 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9131 <op> $treg,0($tempreg)
9133 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9135 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9136 <op> $treg,0($tempreg)
9137 If there is a base register, we add it to $tempreg before
9138 the <op>. If there is a constant, we stick it in the
9139 <op> instruction. We don't handle constants larger than
9140 16 bits, because we have no way to load the upper 16 bits
9141 (actually, we could handle them for the subset of cases
9142 in which we are not using $at). */
9143 gas_assert (offset_expr.X_op == O_symbol);
9144 expr1.X_add_number = offset_expr.X_add_number;
9145 offset_expr.X_add_number = 0;
9146 if (expr1.X_add_number < -0x8000
9147 || expr1.X_add_number >= 0x8000)
9148 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9149 gpdelay = reg_needs_delay (mips_gp_register);
9150 relax_start (offset_expr.X_add_symbol);
9151 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
9152 BFD_RELOC_MIPS_GOT_HI16);
9153 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
9155 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9156 BFD_RELOC_MIPS_GOT_LO16, tempreg);
9159 macro_build (NULL, "nop", "");
9160 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9161 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9163 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
9164 tempreg, BFD_RELOC_LO16);
9168 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9169 tempreg, tempreg, breg);
9170 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
9172 else if (mips_big_got && HAVE_NEWABI)
9174 /* If this is a reference to an external symbol, we want
9175 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9176 add $tempreg,$tempreg,$gp
9177 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9178 <op> $treg,<ofst>($tempreg)
9179 Otherwise, for local symbols, we want:
9180 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9181 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
9182 gas_assert (offset_expr.X_op == O_symbol);
9183 expr1.X_add_number = offset_expr.X_add_number;
9184 offset_expr.X_add_number = 0;
9185 if (expr1.X_add_number < -0x8000
9186 || expr1.X_add_number >= 0x8000)
9187 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9188 relax_start (offset_expr.X_add_symbol);
9189 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
9190 BFD_RELOC_MIPS_GOT_HI16);
9191 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
9193 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9194 BFD_RELOC_MIPS_GOT_LO16, tempreg);
9196 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9197 tempreg, tempreg, breg);
9198 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
9201 offset_expr.X_add_number = expr1.X_add_number;
9202 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9203 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
9205 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9206 tempreg, tempreg, breg);
9207 macro_build (&offset_expr, s, fmt, treg,
9208 BFD_RELOC_MIPS_GOT_OFST, tempreg);
9217 gas_assert (mips_opts.micromips);
9218 gas_assert (mips_opts.insn32);
9220 macro_build (NULL, "jr", "s", RA);
9221 expr1.X_add_number = EXTRACT_OPERAND (1, IMMP, *ip) << 2;
9222 macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16);
9227 gas_assert (mips_opts.micromips);
9228 gas_assert (mips_opts.insn32);
9229 macro_build (NULL, "jr", "s", sreg);
9230 if (mips_opts.noreorder)
9231 macro_build (NULL, "nop", "");
9236 load_register (treg, &imm_expr, 0);
9240 load_register (treg, &imm_expr, 1);
9244 if (imm_expr.X_op == O_constant)
9247 load_register (AT, &imm_expr, 0);
9248 macro_build (NULL, "mtc1", "t,G", AT, treg);
9253 gas_assert (offset_expr.X_op == O_symbol
9254 && strcmp (segment_name (S_GET_SEGMENT
9255 (offset_expr.X_add_symbol)),
9257 && offset_expr.X_add_number == 0);
9258 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
9259 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
9264 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
9265 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
9266 order 32 bits of the value and the low order 32 bits are either
9267 zero or in OFFSET_EXPR. */
9268 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
9270 if (HAVE_64BIT_GPRS)
9271 load_register (treg, &imm_expr, 1);
9276 if (target_big_endian)
9288 load_register (hreg, &imm_expr, 0);
9291 if (offset_expr.X_op == O_absent)
9292 move_register (lreg, 0);
9295 gas_assert (offset_expr.X_op == O_constant);
9296 load_register (lreg, &offset_expr, 0);
9303 /* We know that sym is in the .rdata section. First we get the
9304 upper 16 bits of the address. */
9305 if (mips_pic == NO_PIC)
9307 macro_build_lui (&offset_expr, AT);
9312 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
9313 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9317 /* Now we load the register(s). */
9318 if (HAVE_64BIT_GPRS)
9321 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
9326 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
9329 /* FIXME: How in the world do we deal with the possible
9331 offset_expr.X_add_number += 4;
9332 macro_build (&offset_expr, "lw", "t,o(b)",
9333 treg + 1, BFD_RELOC_LO16, AT);
9339 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
9340 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
9341 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
9342 the value and the low order 32 bits are either zero or in
9344 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
9347 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
9348 if (HAVE_64BIT_FPRS)
9350 gas_assert (HAVE_64BIT_GPRS);
9351 macro_build (NULL, "dmtc1", "t,S", AT, treg);
9355 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
9356 if (offset_expr.X_op == O_absent)
9357 macro_build (NULL, "mtc1", "t,G", 0, treg);
9360 gas_assert (offset_expr.X_op == O_constant);
9361 load_register (AT, &offset_expr, 0);
9362 macro_build (NULL, "mtc1", "t,G", AT, treg);
9368 gas_assert (offset_expr.X_op == O_symbol
9369 && offset_expr.X_add_number == 0);
9370 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
9371 if (strcmp (s, ".lit8") == 0)
9373 breg = mips_gp_register;
9374 offset_reloc[0] = BFD_RELOC_MIPS_LITERAL;
9375 offset_reloc[1] = BFD_RELOC_UNUSED;
9376 offset_reloc[2] = BFD_RELOC_UNUSED;
9380 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
9382 if (mips_pic != NO_PIC)
9383 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
9384 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9387 /* FIXME: This won't work for a 64 bit address. */
9388 macro_build_lui (&offset_expr, AT);
9392 offset_reloc[0] = BFD_RELOC_LO16;
9393 offset_reloc[1] = BFD_RELOC_UNUSED;
9394 offset_reloc[2] = BFD_RELOC_UNUSED;
9401 * The MIPS assembler seems to check for X_add_number not
9402 * being double aligned and generating:
9405 * addiu at,at,%lo(foo+1)
9408 * But, the resulting address is the same after relocation so why
9409 * generate the extra instruction?
9411 /* Itbl support may require additional care here. */
9414 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
9423 gas_assert (!mips_opts.micromips);
9424 /* Itbl support may require additional care here. */
9427 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
9447 if (HAVE_64BIT_GPRS)
9457 if (HAVE_64BIT_GPRS)
9465 /* Even on a big endian machine $fn comes before $fn+1. We have
9466 to adjust when loading from memory. We set coproc if we must
9467 load $fn+1 first. */
9468 /* Itbl support may require additional care here. */
9469 if (!target_big_endian)
9472 if (small_offset_p (0, align, 16))
9475 if (!small_offset_p (4, align, 16))
9477 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg,
9478 -1, offset_reloc[0], offset_reloc[1],
9480 expr1.X_add_number = 0;
9484 offset_reloc[0] = BFD_RELOC_LO16;
9485 offset_reloc[1] = BFD_RELOC_UNUSED;
9486 offset_reloc[2] = BFD_RELOC_UNUSED;
9488 if (strcmp (s, "lw") == 0 && treg == breg)
9490 ep->X_add_number += 4;
9491 macro_build (ep, s, fmt, treg + 1, -1, offset_reloc[0],
9492 offset_reloc[1], offset_reloc[2], breg);
9493 ep->X_add_number -= 4;
9494 macro_build (ep, s, fmt, treg, -1, offset_reloc[0],
9495 offset_reloc[1], offset_reloc[2], breg);
9499 macro_build (ep, s, fmt, coproc ? treg + 1 : treg, -1,
9500 offset_reloc[0], offset_reloc[1], offset_reloc[2],
9502 ep->X_add_number += 4;
9503 macro_build (ep, s, fmt, coproc ? treg : treg + 1, -1,
9504 offset_reloc[0], offset_reloc[1], offset_reloc[2],
9510 if (offset_expr.X_op != O_symbol
9511 && offset_expr.X_op != O_constant)
9513 as_bad (_("Expression too complex"));
9514 offset_expr.X_op = O_constant;
9517 if (HAVE_32BIT_ADDRESSES
9518 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
9522 sprintf_vma (value, offset_expr.X_add_number);
9523 as_bad (_("Number (0x%s) larger than 32 bits"), value);
9526 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
9528 /* If this is a reference to a GP relative symbol, we want
9529 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
9530 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
9531 If we have a base register, we use this
9533 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
9534 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
9535 If this is not a GP relative symbol, we want
9536 lui $at,<sym> (BFD_RELOC_HI16_S)
9537 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9538 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9539 If there is a base register, we add it to $at after the
9540 lui instruction. If there is a constant, we always use
9542 if (offset_expr.X_op == O_symbol
9543 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
9544 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
9546 relax_start (offset_expr.X_add_symbol);
9549 tempreg = mips_gp_register;
9553 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9554 AT, breg, mips_gp_register);
9559 /* Itbl support may require additional care here. */
9560 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9561 BFD_RELOC_GPREL16, tempreg);
9562 offset_expr.X_add_number += 4;
9564 /* Set mips_optimize to 2 to avoid inserting an
9566 hold_mips_optimize = mips_optimize;
9568 /* Itbl support may require additional care here. */
9569 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9570 BFD_RELOC_GPREL16, tempreg);
9571 mips_optimize = hold_mips_optimize;
9575 offset_expr.X_add_number -= 4;
9578 if (offset_high_part (offset_expr.X_add_number, 16)
9579 != offset_high_part (offset_expr.X_add_number + 4, 16))
9581 load_address (AT, &offset_expr, &used_at);
9582 offset_expr.X_op = O_constant;
9583 offset_expr.X_add_number = 0;
9586 macro_build_lui (&offset_expr, AT);
9588 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9589 /* Itbl support may require additional care here. */
9590 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9591 BFD_RELOC_LO16, AT);
9592 /* FIXME: How do we handle overflow here? */
9593 offset_expr.X_add_number += 4;
9594 /* Itbl support may require additional care here. */
9595 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9596 BFD_RELOC_LO16, AT);
9597 if (mips_relax.sequence)
9600 else if (!mips_big_got)
9602 /* If this is a reference to an external symbol, we want
9603 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9608 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9610 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9611 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9612 If there is a base register we add it to $at before the
9613 lwc1 instructions. If there is a constant we include it
9614 in the lwc1 instructions. */
9616 expr1.X_add_number = offset_expr.X_add_number;
9617 if (expr1.X_add_number < -0x8000
9618 || expr1.X_add_number >= 0x8000 - 4)
9619 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9620 load_got_offset (AT, &offset_expr);
9623 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9625 /* Set mips_optimize to 2 to avoid inserting an undesired
9627 hold_mips_optimize = mips_optimize;
9630 /* Itbl support may require additional care here. */
9631 relax_start (offset_expr.X_add_symbol);
9632 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9633 BFD_RELOC_LO16, AT);
9634 expr1.X_add_number += 4;
9635 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9636 BFD_RELOC_LO16, AT);
9638 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9639 BFD_RELOC_LO16, AT);
9640 offset_expr.X_add_number += 4;
9641 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9642 BFD_RELOC_LO16, AT);
9645 mips_optimize = hold_mips_optimize;
9647 else if (mips_big_got)
9651 /* If this is a reference to an external symbol, we want
9652 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9654 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
9659 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9661 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9662 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9663 If there is a base register we add it to $at before the
9664 lwc1 instructions. If there is a constant we include it
9665 in the lwc1 instructions. */
9667 expr1.X_add_number = offset_expr.X_add_number;
9668 offset_expr.X_add_number = 0;
9669 if (expr1.X_add_number < -0x8000
9670 || expr1.X_add_number >= 0x8000 - 4)
9671 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9672 gpdelay = reg_needs_delay (mips_gp_register);
9673 relax_start (offset_expr.X_add_symbol);
9674 macro_build (&offset_expr, "lui", LUI_FMT,
9675 AT, BFD_RELOC_MIPS_GOT_HI16);
9676 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9677 AT, AT, mips_gp_register);
9678 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9679 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
9682 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9683 /* Itbl support may require additional care here. */
9684 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9685 BFD_RELOC_LO16, AT);
9686 expr1.X_add_number += 4;
9688 /* Set mips_optimize to 2 to avoid inserting an undesired
9690 hold_mips_optimize = mips_optimize;
9692 /* Itbl support may require additional care here. */
9693 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9694 BFD_RELOC_LO16, AT);
9695 mips_optimize = hold_mips_optimize;
9696 expr1.X_add_number -= 4;
9699 offset_expr.X_add_number = expr1.X_add_number;
9701 macro_build (NULL, "nop", "");
9702 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
9703 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9706 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9707 /* Itbl support may require additional care here. */
9708 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9709 BFD_RELOC_LO16, AT);
9710 offset_expr.X_add_number += 4;
9712 /* Set mips_optimize to 2 to avoid inserting an undesired
9714 hold_mips_optimize = mips_optimize;
9716 /* Itbl support may require additional care here. */
9717 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9718 BFD_RELOC_LO16, AT);
9719 mips_optimize = hold_mips_optimize;
9738 /* New code added to support COPZ instructions.
9739 This code builds table entries out of the macros in mip_opcodes.
9740 R4000 uses interlocks to handle coproc delays.
9741 Other chips (like the R3000) require nops to be inserted for delays.
9743 FIXME: Currently, we require that the user handle delays.
9744 In order to fill delay slots for non-interlocked chips,
9745 we must have a way to specify delays based on the coprocessor.
9746 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
9747 What are the side-effects of the cop instruction?
9748 What cache support might we have and what are its effects?
9749 Both coprocessor & memory require delays. how long???
9750 What registers are read/set/modified?
9752 If an itbl is provided to interpret cop instructions,
9753 this knowledge can be encoded in the itbl spec. */
9767 gas_assert (!mips_opts.micromips);
9768 /* For now we just do C (same as Cz). The parameter will be
9769 stored in insn_opcode by mips_ip. */
9770 macro_build (NULL, s, "C", ip->insn_opcode);
9774 move_register (dreg, sreg);
9778 gas_assert (mips_opts.micromips);
9779 gas_assert (mips_opts.insn32);
9780 dreg = micromips_to_32_reg_h_map1[EXTRACT_OPERAND (1, MH, *ip)];
9781 breg = micromips_to_32_reg_h_map2[EXTRACT_OPERAND (1, MH, *ip)];
9782 sreg = micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)];
9783 treg = micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)];
9784 move_register (dreg, sreg);
9785 move_register (breg, treg);
9791 if (mips_opts.arch == CPU_R5900)
9793 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", dreg, sreg, treg);
9797 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
9798 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9805 /* The MIPS assembler some times generates shifts and adds. I'm
9806 not trying to be that fancy. GCC should do this for us
9809 load_register (AT, &imm_expr, dbl);
9810 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
9811 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9827 load_register (AT, &imm_expr, dbl);
9828 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
9829 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9830 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA);
9831 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9833 macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6);
9836 if (mips_opts.micromips)
9837 micromips_label_expr (&label_expr);
9839 label_expr.X_add_number = 8;
9840 macro_build (&label_expr, "beq", "s,t,p", dreg, AT);
9841 macro_build (NULL, "nop", "");
9842 macro_build (NULL, "break", BRK_FMT, 6);
9843 if (mips_opts.micromips)
9844 micromips_add_label ();
9847 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9863 load_register (AT, &imm_expr, dbl);
9864 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
9865 sreg, imm ? AT : treg);
9866 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9867 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9869 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
9872 if (mips_opts.micromips)
9873 micromips_label_expr (&label_expr);
9875 label_expr.X_add_number = 8;
9876 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
9877 macro_build (NULL, "nop", "");
9878 macro_build (NULL, "break", BRK_FMT, 6);
9879 if (mips_opts.micromips)
9880 micromips_add_label ();
9886 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9897 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
9898 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
9902 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9903 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
9904 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
9905 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9909 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9920 macro_build (NULL, "negu", "d,w", tempreg, treg);
9921 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
9925 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
9926 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
9927 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
9928 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9937 if (imm_expr.X_op != O_constant)
9938 as_bad (_("Improper rotate count"));
9939 rot = imm_expr.X_add_number & 0x3f;
9940 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9942 rot = (64 - rot) & 0x3f;
9944 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
9946 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
9951 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
9954 l = (rot < 0x20) ? "dsll" : "dsll32";
9955 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
9958 macro_build (NULL, l, SHFT_FMT, AT, sreg, rot);
9959 macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9960 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9968 if (imm_expr.X_op != O_constant)
9969 as_bad (_("Improper rotate count"));
9970 rot = imm_expr.X_add_number & 0x1f;
9971 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9973 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f);
9978 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
9982 macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot);
9983 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9984 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9989 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9991 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
9995 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9996 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
9997 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
9998 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
10002 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
10004 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
10008 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
10009 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
10010 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
10011 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
10020 if (imm_expr.X_op != O_constant)
10021 as_bad (_("Improper rotate count"));
10022 rot = imm_expr.X_add_number & 0x3f;
10023 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
10026 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
10028 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
10033 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
10036 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
10037 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
10040 macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot);
10041 macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
10042 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
10050 if (imm_expr.X_op != O_constant)
10051 as_bad (_("Improper rotate count"));
10052 rot = imm_expr.X_add_number & 0x1f;
10053 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
10055 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot);
10060 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
10064 macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot);
10065 macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
10066 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
10072 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
10073 else if (treg == 0)
10074 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
10077 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
10078 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
10083 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
10085 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
10090 as_warn (_("Instruction %s: result is always false"),
10091 ip->insn_mo->name);
10092 move_register (dreg, 0);
10095 if (CPU_HAS_SEQ (mips_opts.arch)
10096 && -512 <= imm_expr.X_add_number
10097 && imm_expr.X_add_number < 512)
10099 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
10100 (int) imm_expr.X_add_number);
10103 if (imm_expr.X_op == O_constant
10104 && imm_expr.X_add_number >= 0
10105 && imm_expr.X_add_number < 0x10000)
10107 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
10109 else if (imm_expr.X_op == O_constant
10110 && imm_expr.X_add_number > -0x8000
10111 && imm_expr.X_add_number < 0)
10113 imm_expr.X_add_number = -imm_expr.X_add_number;
10114 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
10115 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
10117 else if (CPU_HAS_SEQ (mips_opts.arch))
10120 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10121 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
10126 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10127 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
10130 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
10133 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
10139 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
10140 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
10143 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
10145 if (imm_expr.X_op == O_constant
10146 && imm_expr.X_add_number >= -0x8000
10147 && imm_expr.X_add_number < 0x8000)
10149 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
10150 dreg, sreg, BFD_RELOC_LO16);
10154 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10155 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
10159 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
10162 case M_SGT: /* sreg > treg <==> treg < sreg */
10168 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
10171 case M_SGT_I: /* sreg > I <==> I < sreg */
10178 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10179 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
10182 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
10188 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
10189 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
10192 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
10199 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10200 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
10201 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
10205 if (imm_expr.X_op == O_constant
10206 && imm_expr.X_add_number >= -0x8000
10207 && imm_expr.X_add_number < 0x8000)
10209 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
10213 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10214 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
10218 if (imm_expr.X_op == O_constant
10219 && imm_expr.X_add_number >= -0x8000
10220 && imm_expr.X_add_number < 0x8000)
10222 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
10227 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10228 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
10233 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
10234 else if (treg == 0)
10235 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
10238 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
10239 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
10244 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
10246 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
10251 as_warn (_("Instruction %s: result is always true"),
10252 ip->insn_mo->name);
10253 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
10254 dreg, 0, BFD_RELOC_LO16);
10257 if (CPU_HAS_SEQ (mips_opts.arch)
10258 && -512 <= imm_expr.X_add_number
10259 && imm_expr.X_add_number < 512)
10261 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
10262 (int) imm_expr.X_add_number);
10265 if (imm_expr.X_op == O_constant
10266 && imm_expr.X_add_number >= 0
10267 && imm_expr.X_add_number < 0x10000)
10269 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
10271 else if (imm_expr.X_op == O_constant
10272 && imm_expr.X_add_number > -0x8000
10273 && imm_expr.X_add_number < 0)
10275 imm_expr.X_add_number = -imm_expr.X_add_number;
10276 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
10277 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
10279 else if (CPU_HAS_SEQ (mips_opts.arch))
10282 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10283 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
10288 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10289 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
10292 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
10307 if (!mips_opts.micromips)
10309 if (imm_expr.X_op == O_constant
10310 && imm_expr.X_add_number > -0x200
10311 && imm_expr.X_add_number <= 0x200)
10313 macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number);
10322 if (imm_expr.X_op == O_constant
10323 && imm_expr.X_add_number > -0x8000
10324 && imm_expr.X_add_number <= 0x8000)
10326 imm_expr.X_add_number = -imm_expr.X_add_number;
10327 macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16);
10332 load_register (AT, &imm_expr, dbl);
10333 macro_build (NULL, s2, "d,v,t", dreg, sreg, AT);
10355 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10356 macro_build (NULL, s, "s,t", sreg, AT);
10361 gas_assert (!mips_opts.micromips);
10362 gas_assert (mips_opts.isa == ISA_MIPS1);
10364 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
10365 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
10368 * Is the double cfc1 instruction a bug in the mips assembler;
10369 * or is there a reason for it?
10371 start_noreorder ();
10372 macro_build (NULL, "cfc1", "t,G", treg, RA);
10373 macro_build (NULL, "cfc1", "t,G", treg, RA);
10374 macro_build (NULL, "nop", "");
10375 expr1.X_add_number = 3;
10376 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
10377 expr1.X_add_number = 2;
10378 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
10379 macro_build (NULL, "ctc1", "t,G", AT, RA);
10380 macro_build (NULL, "nop", "");
10381 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
10383 macro_build (NULL, "ctc1", "t,G", treg, RA);
10384 macro_build (NULL, "nop", "");
10401 offbits = (mips_opts.micromips ? 12 : 16);
10407 offbits = (mips_opts.micromips ? 12 : 16);
10419 offbits = (mips_opts.micromips ? 12 : 16);
10426 offbits = (mips_opts.micromips ? 12 : 16);
10431 large_offset = !small_offset_p (off, align, offbits);
10433 expr1.X_add_number = 0;
10438 if (small_offset_p (0, align, 16))
10439 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1,
10440 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
10443 load_address (tempreg, ep, &used_at);
10445 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10446 tempreg, tempreg, breg);
10448 offset_reloc[0] = BFD_RELOC_LO16;
10449 offset_reloc[1] = BFD_RELOC_UNUSED;
10450 offset_reloc[2] = BFD_RELOC_UNUSED;
10455 else if (!ust && treg == breg)
10466 if (!target_big_endian)
10467 ep->X_add_number += off;
10469 macro_build (NULL, s, "t,~(b)",
10470 tempreg, (unsigned long) ep->X_add_number, breg);
10472 macro_build (ep, s, "t,o(b)", tempreg, -1,
10473 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
10475 if (!target_big_endian)
10476 ep->X_add_number -= off;
10478 ep->X_add_number += off;
10480 macro_build (NULL, s2, "t,~(b)",
10481 tempreg, (unsigned long) ep->X_add_number, breg);
10483 macro_build (ep, s2, "t,o(b)", tempreg, -1,
10484 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
10486 /* If necessary, move the result in tempreg to the final destination. */
10487 if (!ust && treg != tempreg)
10489 /* Protect second load's delay slot. */
10491 move_register (treg, tempreg);
10497 if (target_big_endian == ust)
10498 ep->X_add_number += off;
10499 tempreg = ust || large_offset ? treg : AT;
10500 macro_build (ep, s, "t,o(b)", tempreg, -1,
10501 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
10503 /* For halfword transfers we need a temporary register to shuffle
10504 bytes. Unfortunately for M_USH_A we have none available before
10505 the next store as AT holds the base address. We deal with this
10506 case by clobbering TREG and then restoring it as with ULH. */
10507 tempreg = ust == large_offset ? treg : AT;
10509 macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8);
10511 if (target_big_endian == ust)
10512 ep->X_add_number -= off;
10514 ep->X_add_number += off;
10515 macro_build (ep, s2, "t,o(b)", tempreg, -1,
10516 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
10518 /* For M_USH_A re-retrieve the LSB. */
10519 if (ust && large_offset)
10521 if (target_big_endian)
10522 ep->X_add_number += off;
10524 ep->X_add_number -= off;
10525 macro_build (&expr1, "lbu", "t,o(b)", AT, -1,
10526 offset_reloc[0], offset_reloc[1], offset_reloc[2], AT);
10528 /* For ULH and M_USH_A OR the LSB in. */
10529 if (!ust || large_offset)
10531 tempreg = !large_offset ? AT : treg;
10532 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
10533 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
10538 /* FIXME: Check if this is one of the itbl macros, since they
10539 are added dynamically. */
10540 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
10543 if (!mips_opts.at && used_at)
10544 as_bad (_("Macro used $at after \".set noat\""));
10547 /* Implement macros in mips16 mode. */
10550 mips16_macro (struct mips_cl_insn *ip)
10553 int xreg, yreg, zreg, tmp;
10556 const char *s, *s2, *s3;
10558 mask = ip->insn_mo->mask;
10560 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
10561 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
10562 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
10564 expr1.X_op = O_constant;
10565 expr1.X_op_symbol = NULL;
10566 expr1.X_add_symbol = NULL;
10567 expr1.X_add_number = 1;
10586 start_noreorder ();
10587 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
10588 expr1.X_add_number = 2;
10589 macro_build (&expr1, "bnez", "x,p", yreg);
10590 macro_build (NULL, "break", "6", 7);
10592 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
10593 since that causes an overflow. We should do that as well,
10594 but I don't see how to do the comparisons without a temporary
10597 macro_build (NULL, s, "x", zreg);
10616 start_noreorder ();
10617 macro_build (NULL, s, "0,x,y", xreg, yreg);
10618 expr1.X_add_number = 2;
10619 macro_build (&expr1, "bnez", "x,p", yreg);
10620 macro_build (NULL, "break", "6", 7);
10622 macro_build (NULL, s2, "x", zreg);
10628 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
10629 macro_build (NULL, "mflo", "x", zreg);
10637 if (imm_expr.X_op != O_constant)
10638 as_bad (_("Unsupported large constant"));
10639 imm_expr.X_add_number = -imm_expr.X_add_number;
10640 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
10644 if (imm_expr.X_op != O_constant)
10645 as_bad (_("Unsupported large constant"));
10646 imm_expr.X_add_number = -imm_expr.X_add_number;
10647 macro_build (&imm_expr, "addiu", "x,k", xreg);
10651 if (imm_expr.X_op != O_constant)
10652 as_bad (_("Unsupported large constant"));
10653 imm_expr.X_add_number = -imm_expr.X_add_number;
10654 macro_build (&imm_expr, "daddiu", "y,j", yreg);
10676 goto do_reverse_branch;
10680 goto do_reverse_branch;
10692 goto do_reverse_branch;
10703 macro_build (NULL, s, "x,y", xreg, yreg);
10704 macro_build (&offset_expr, s2, "p");
10731 goto do_addone_branch_i;
10736 goto do_addone_branch_i;
10751 goto do_addone_branch_i;
10757 do_addone_branch_i:
10758 if (imm_expr.X_op != O_constant)
10759 as_bad (_("Unsupported large constant"));
10760 ++imm_expr.X_add_number;
10763 macro_build (&imm_expr, s, s3, xreg);
10764 macro_build (&offset_expr, s2, "p");
10768 expr1.X_add_number = 0;
10769 macro_build (&expr1, "slti", "x,8", yreg);
10771 move_register (xreg, yreg);
10772 expr1.X_add_number = 2;
10773 macro_build (&expr1, "bteqz", "p");
10774 macro_build (NULL, "neg", "x,w", xreg, xreg);
10778 /* For consistency checking, verify that all bits are specified either
10779 by the match/mask part of the instruction definition, or by the
10782 validate_mips_insn (const struct mips_opcode *opc)
10784 const char *p = opc->args;
10786 unsigned long used_bits = opc->mask;
10788 if ((used_bits & opc->match) != opc->match)
10790 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
10791 opc->name, opc->args);
10794 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
10804 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
10805 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
10806 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
10807 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
10808 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10809 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10810 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10811 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10812 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10813 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10814 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10816 case 'J': USE_BITS (OP_MASK_CODE10, OP_SH_CODE10); break;
10817 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10818 case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10819 case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10820 case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10821 case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10822 case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
10823 case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10824 case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10825 case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break;
10826 case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break;
10827 case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break;
10828 case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break;
10829 case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break;
10830 case 'i': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
10831 case 'j': USE_BITS (OP_MASK_EVAOFFSET, OP_SH_EVAOFFSET); break;
10834 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
10835 c, opc->name, opc->args);
10839 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10840 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10842 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
10843 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
10844 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10845 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10847 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10848 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10850 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
10851 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10853 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
10854 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
10855 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
10856 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
10857 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10858 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
10859 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10860 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10861 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10862 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10863 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10864 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10865 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10866 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
10867 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10868 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
10869 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10871 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
10872 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10873 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10874 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
10876 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10877 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10878 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
10879 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10880 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10881 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10882 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10883 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10884 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10887 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
10888 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
10889 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10890 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
10891 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
10892 case '1': USE_BITS (OP_MASK_STYPE, OP_SH_STYPE); break;
10893 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
10894 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
10895 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
10896 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
10897 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10898 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
10899 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
10900 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
10901 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
10902 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
10903 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
10904 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
10905 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
10906 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
10907 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
10908 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
10909 case '\\': USE_BITS (OP_MASK_3BITPOS, OP_SH_3BITPOS); break;
10910 case '~': USE_BITS (OP_MASK_OFFSET12, OP_SH_OFFSET12); break;
10911 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10913 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
10914 c, opc->name, opc->args);
10918 if (used_bits != 0xffffffff)
10920 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
10921 ~used_bits & 0xffffffff, opc->name, opc->args);
10927 /* For consistency checking, verify that the length implied matches the
10928 major opcode and that all bits are specified either by the match/mask
10929 part of the instruction definition, or by the operand list. */
10932 validate_micromips_insn (const struct mips_opcode *opc)
10934 unsigned long match = opc->match;
10935 unsigned long mask = opc->mask;
10936 const char *p = opc->args;
10937 unsigned long insn_bits;
10938 unsigned long used_bits;
10939 unsigned long major;
10940 unsigned int length;
10944 if ((mask & match) != match)
10946 as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"),
10947 opc->name, opc->args);
10950 length = micromips_insn_length (opc);
10951 if (length != 2 && length != 4)
10953 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
10954 "%s %s"), length, opc->name, opc->args);
10957 major = match >> (10 + 8 * (length - 2));
10958 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
10959 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
10961 as_bad (_("Internal error: bad microMIPS opcode "
10962 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
10966 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
10967 insn_bits = 1 << 4 * length;
10968 insn_bits <<= 4 * length;
10971 #define USE_BITS(field) \
10972 (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field)
10983 case 'A': USE_BITS (EXTLSB); break;
10984 case 'B': USE_BITS (INSMSB); break;
10985 case 'C': USE_BITS (EXTMSBD); break;
10986 case 'E': USE_BITS (EXTLSB); break;
10987 case 'F': USE_BITS (INSMSB); break;
10988 case 'G': USE_BITS (EXTMSBD); break;
10989 case 'H': USE_BITS (EXTMSBD); break;
10990 case 'i': USE_BITS (TARGET); break;
10991 case 'j': USE_BITS (EVAOFFSET); break;
10993 as_bad (_("Internal error: bad mips opcode "
10994 "(unknown extension operand type `%c%c'): %s %s"),
10995 e, c, opc->name, opc->args);
11003 case 'A': USE_BITS (IMMA); break;
11004 case 'B': USE_BITS (IMMB); break;
11005 case 'C': USE_BITS (IMMC); break;
11006 case 'D': USE_BITS (IMMD); break;
11007 case 'E': USE_BITS (IMME); break;
11008 case 'F': USE_BITS (IMMF); break;
11009 case 'G': USE_BITS (IMMG); break;
11010 case 'H': USE_BITS (IMMH); break;
11011 case 'I': USE_BITS (IMMI); break;
11012 case 'J': USE_BITS (IMMJ); break;
11013 case 'L': USE_BITS (IMML); break;
11014 case 'M': USE_BITS (IMMM); break;
11015 case 'N': USE_BITS (IMMN); break;
11016 case 'O': USE_BITS (IMMO); break;
11017 case 'P': USE_BITS (IMMP); break;
11018 case 'Q': USE_BITS (IMMQ); break;
11019 case 'U': USE_BITS (IMMU); break;
11020 case 'W': USE_BITS (IMMW); break;
11021 case 'X': USE_BITS (IMMX); break;
11022 case 'Y': USE_BITS (IMMY); break;
11025 case 'b': USE_BITS (MB); break;
11026 case 'c': USE_BITS (MC); break;
11027 case 'd': USE_BITS (MD); break;
11028 case 'e': USE_BITS (ME); break;
11029 case 'f': USE_BITS (MF); break;
11030 case 'g': USE_BITS (MG); break;
11031 case 'h': USE_BITS (MH); break;
11032 case 'j': USE_BITS (MJ); break;
11033 case 'l': USE_BITS (ML); break;
11034 case 'm': USE_BITS (MM); break;
11035 case 'n': USE_BITS (MN); break;
11036 case 'p': USE_BITS (MP); break;
11037 case 'q': USE_BITS (MQ); break;
11045 as_bad (_("Internal error: bad mips opcode "
11046 "(unknown extension operand type `%c%c'): %s %s"),
11047 e, c, opc->name, opc->args);
11051 case '.': USE_BITS (OFFSET10); break;
11052 case '1': USE_BITS (STYPE); break;
11053 case '2': USE_BITS (BP); break;
11054 case '3': USE_BITS (SA3); break;
11055 case '4': USE_BITS (SA4); break;
11056 case '5': USE_BITS (IMM8); break;
11057 case '6': USE_BITS (RS); break;
11058 case '7': USE_BITS (DSPACC); break;
11059 case '8': USE_BITS (WRDSP); break;
11060 case '0': USE_BITS (DSPSFT); break;
11061 case '<': USE_BITS (SHAMT); break;
11062 case '>': USE_BITS (SHAMT); break;
11063 case '@': USE_BITS (IMM10); break;
11064 case 'B': USE_BITS (CODE10); break;
11065 case 'C': USE_BITS (COPZ); break;
11066 case 'D': USE_BITS (FD); break;
11067 case 'E': USE_BITS (RT); break;
11068 case 'G': USE_BITS (RS); break;
11069 case 'H': USE_BITS (SEL); break;
11070 case 'K': USE_BITS (RS); break;
11071 case 'M': USE_BITS (CCC); break;
11072 case 'N': USE_BITS (BCC); break;
11073 case 'R': USE_BITS (FR); break;
11074 case 'S': USE_BITS (FS); break;
11075 case 'T': USE_BITS (FT); break;
11076 case 'V': USE_BITS (FS); break;
11077 case '\\': USE_BITS (3BITPOS); break;
11078 case '^': USE_BITS (RD); break;
11079 case 'a': USE_BITS (TARGET); break;
11080 case 'b': USE_BITS (RS); break;
11081 case 'c': USE_BITS (CODE); break;
11082 case 'd': USE_BITS (RD); break;
11083 case 'h': USE_BITS (PREFX); break;
11084 case 'i': USE_BITS (IMMEDIATE); break;
11085 case 'j': USE_BITS (DELTA); break;
11086 case 'k': USE_BITS (CACHE); break;
11087 case 'n': USE_BITS (RT); break;
11088 case 'o': USE_BITS (DELTA); break;
11089 case 'p': USE_BITS (DELTA); break;
11090 case 'q': USE_BITS (CODE2); break;
11091 case 'r': USE_BITS (RS); break;
11092 case 's': USE_BITS (RS); break;
11093 case 't': USE_BITS (RT); break;
11094 case 'u': USE_BITS (IMMEDIATE); break;
11095 case 'v': USE_BITS (RS); break;
11096 case 'w': USE_BITS (RT); break;
11097 case 'y': USE_BITS (RS3); break;
11099 case '|': USE_BITS (TRAP); break;
11100 case '~': USE_BITS (OFFSET12); break;
11102 as_bad (_("Internal error: bad microMIPS opcode "
11103 "(unknown operand type `%c'): %s %s"),
11104 c, opc->name, opc->args);
11108 if (used_bits != insn_bits)
11110 if (~used_bits & insn_bits)
11111 as_bad (_("Internal error: bad microMIPS opcode "
11112 "(bits 0x%lx undefined): %s %s"),
11113 ~used_bits & insn_bits, opc->name, opc->args);
11114 if (used_bits & ~insn_bits)
11115 as_bad (_("Internal error: bad microMIPS opcode "
11116 "(bits 0x%lx defined): %s %s"),
11117 used_bits & ~insn_bits, opc->name, opc->args);
11123 /* UDI immediates. */
11124 struct mips_immed {
11126 unsigned int shift;
11127 unsigned long mask;
11131 static const struct mips_immed mips_immed[] = {
11132 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
11133 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
11134 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
11135 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
11139 /* Check whether an odd floating-point register is allowed. */
11141 mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
11143 const char *s = insn->name;
11145 if (insn->pinfo == INSN_MACRO)
11146 /* Let a macro pass, we'll catch it later when it is expanded. */
11149 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || (mips_opts.arch == CPU_R5900))
11151 /* Allow odd registers for single-precision ops. */
11152 switch (insn->pinfo & (FP_S | FP_D))
11156 return 1; /* both single precision - ok */
11158 return 0; /* both double precision - fail */
11163 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
11164 s = strchr (insn->name, '.');
11166 s = s != NULL ? strchr (s + 1, '.') : NULL;
11167 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
11170 /* Single-precision coprocessor loads and moves are OK too. */
11171 if ((insn->pinfo & FP_S)
11172 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
11173 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
11179 /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
11180 taking bits from BIT up. */
11182 expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit)
11184 return (ep->X_op == O_constant
11185 && (ep->X_add_number & ((1 << bit) - 1)) == 0
11186 && ep->X_add_number >= min << bit
11187 && ep->X_add_number < max << bit);
11190 /* This routine assembles an instruction into its binary format. As a
11191 side effect, it sets one of the global variables imm_reloc or
11192 offset_reloc to the type of relocation to do if one of the operands
11193 is an address expression. */
11196 mips_ip (char *str, struct mips_cl_insn *ip)
11198 bfd_boolean wrong_delay_slot_insns = FALSE;
11199 bfd_boolean need_delay_slot_ok = TRUE;
11200 struct mips_opcode *firstinsn = NULL;
11201 const struct mips_opcode *past;
11202 struct hash_control *hash;
11206 struct mips_opcode *insn;
11208 unsigned int regno, regno2;
11209 unsigned int lastregno;
11210 unsigned int destregno = 0;
11211 unsigned int lastpos = 0;
11212 unsigned int limlo, limhi;
11215 offsetT min_range, max_range;
11219 unsigned int rtype;
11225 if (mips_opts.micromips)
11227 hash = micromips_op_hash;
11228 past = µmips_opcodes[bfd_micromips_num_opcodes];
11233 past = &mips_opcodes[NUMOPCODES];
11235 forced_insn_length = 0;
11238 /* We first try to match an instruction up to a space or to the end. */
11239 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
11242 /* Make a copy of the instruction so that we can fiddle with it. */
11243 name = alloca (end + 1);
11244 memcpy (name, str, end);
11249 insn = (struct mips_opcode *) hash_find (hash, name);
11251 if (insn != NULL || !mips_opts.micromips)
11253 if (forced_insn_length)
11256 /* See if there's an instruction size override suffix,
11257 either `16' or `32', at the end of the mnemonic proper,
11258 that defines the operation, i.e. before the first `.'
11259 character if any. Strip it and retry. */
11260 dot = strchr (name, '.');
11261 opend = dot != NULL ? dot - name : end;
11264 if (name[opend - 2] == '1' && name[opend - 1] == '6')
11265 forced_insn_length = 2;
11266 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
11267 forced_insn_length = 4;
11270 memcpy (name + opend - 2, name + opend, end - opend + 1);
11274 insn_error = _("Unrecognized opcode");
11278 /* For microMIPS instructions placed in a fixed-length branch delay slot
11279 we make up to two passes over the relevant fragment of the opcode
11280 table. First we try instructions that meet the delay slot's length
11281 requirement. If none matched, then we retry with the remaining ones
11282 and if one matches, then we use it and then issue an appropriate
11283 warning later on. */
11284 argsStart = s = str + end;
11287 bfd_boolean delay_slot_ok;
11288 bfd_boolean size_ok;
11291 gas_assert (strcmp (insn->name, name) == 0);
11293 ok = is_opcode_valid (insn);
11294 size_ok = is_size_valid (insn);
11295 delay_slot_ok = is_delay_slot_valid (insn);
11296 if (!delay_slot_ok && !wrong_delay_slot_insns)
11299 wrong_delay_slot_insns = TRUE;
11301 if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok)
11303 static char buf[256];
11305 if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0)
11310 if (wrong_delay_slot_insns && need_delay_slot_ok)
11312 gas_assert (firstinsn);
11313 need_delay_slot_ok = FALSE;
11323 sprintf (buf, _("Opcode not supported on this processor: %s (%s)"),
11324 mips_cpu_info_from_arch (mips_opts.arch)->name,
11325 mips_cpu_info_from_isa (mips_opts.isa)->name);
11326 else if (mips_opts.insn32)
11327 sprintf (buf, _("Opcode not supported in the `insn32' mode"));
11329 sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"),
11330 8 * forced_insn_length);
11336 imm_expr.X_op = O_absent;
11337 imm2_expr.X_op = O_absent;
11338 offset_expr.X_op = O_absent;
11339 imm_reloc[0] = BFD_RELOC_UNUSED;
11340 imm_reloc[1] = BFD_RELOC_UNUSED;
11341 imm_reloc[2] = BFD_RELOC_UNUSED;
11342 offset_reloc[0] = BFD_RELOC_UNUSED;
11343 offset_reloc[1] = BFD_RELOC_UNUSED;
11344 offset_reloc[2] = BFD_RELOC_UNUSED;
11346 create_insn (ip, insn);
11349 lastregno = 0xffffffff;
11350 for (args = insn->args;; ++args)
11354 s += strspn (s, " \t");
11358 case '\0': /* end of args */
11364 /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS
11365 code) or 14 (for microMIPS code). */
11366 my_getExpression (&imm_expr, s);
11367 check_absolute_expr (ip, &imm_expr);
11368 if ((unsigned long) imm_expr.X_add_number != 1
11369 && (unsigned long) imm_expr.X_add_number != 3)
11371 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
11372 (unsigned long) imm_expr.X_add_number);
11374 INSERT_OPERAND (mips_opts.micromips,
11375 BP, *ip, imm_expr.X_add_number);
11376 imm_expr.X_op = O_absent;
11381 /* DSP 3-bit unsigned immediate in bit 21 (for standard MIPS
11382 code) or 13 (for microMIPS code). */
11384 unsigned long mask = (mips_opts.micromips
11385 ? MICROMIPSOP_MASK_SA3 : OP_MASK_SA3);
11387 my_getExpression (&imm_expr, s);
11388 check_absolute_expr (ip, &imm_expr);
11389 if ((unsigned long) imm_expr.X_add_number > mask)
11390 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11391 mask, (unsigned long) imm_expr.X_add_number);
11392 INSERT_OPERAND (mips_opts.micromips,
11393 SA3, *ip, imm_expr.X_add_number);
11394 imm_expr.X_op = O_absent;
11400 /* DSP 4-bit unsigned immediate in bit 21 (for standard MIPS
11401 code) or 12 (for microMIPS code). */
11403 unsigned long mask = (mips_opts.micromips
11404 ? MICROMIPSOP_MASK_SA4 : OP_MASK_SA4);
11406 my_getExpression (&imm_expr, s);
11407 check_absolute_expr (ip, &imm_expr);
11408 if ((unsigned long) imm_expr.X_add_number > mask)
11409 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11410 mask, (unsigned long) imm_expr.X_add_number);
11411 INSERT_OPERAND (mips_opts.micromips,
11412 SA4, *ip, imm_expr.X_add_number);
11413 imm_expr.X_op = O_absent;
11419 /* DSP 8-bit unsigned immediate in bit 16 (for standard MIPS
11420 code) or 13 (for microMIPS code). */
11422 unsigned long mask = (mips_opts.micromips
11423 ? MICROMIPSOP_MASK_IMM8 : OP_MASK_IMM8);
11425 my_getExpression (&imm_expr, s);
11426 check_absolute_expr (ip, &imm_expr);
11427 if ((unsigned long) imm_expr.X_add_number > mask)
11428 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11429 mask, (unsigned long) imm_expr.X_add_number);
11430 INSERT_OPERAND (mips_opts.micromips,
11431 IMM8, *ip, imm_expr.X_add_number);
11432 imm_expr.X_op = O_absent;
11438 /* DSP 5-bit unsigned immediate in bit 21 (for standard MIPS
11439 code) or 16 (for microMIPS code). */
11441 unsigned long mask = (mips_opts.micromips
11442 ? MICROMIPSOP_MASK_RS : OP_MASK_RS);
11444 my_getExpression (&imm_expr, s);
11445 check_absolute_expr (ip, &imm_expr);
11446 if ((unsigned long) imm_expr.X_add_number > mask)
11447 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11448 mask, (unsigned long) imm_expr.X_add_number);
11449 INSERT_OPERAND (mips_opts.micromips,
11450 RS, *ip, imm_expr.X_add_number);
11451 imm_expr.X_op = O_absent;
11457 /* Four DSP accumulators in bit 11 (for standard MIPS code)
11458 or 14 (for microMIPS code). */
11459 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c'
11460 && s[3] >= '0' && s[3] <= '3')
11462 regno = s[3] - '0';
11464 INSERT_OPERAND (mips_opts.micromips, DSPACC, *ip, regno);
11468 as_bad (_("Invalid dsp acc register"));
11472 /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS
11473 code) or 14 (for microMIPS code). */
11475 unsigned long mask = (mips_opts.micromips
11476 ? MICROMIPSOP_MASK_WRDSP
11479 my_getExpression (&imm_expr, s);
11480 check_absolute_expr (ip, &imm_expr);
11481 if ((unsigned long) imm_expr.X_add_number > mask)
11482 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11483 mask, (unsigned long) imm_expr.X_add_number);
11484 INSERT_OPERAND (mips_opts.micromips,
11485 WRDSP, *ip, imm_expr.X_add_number);
11486 imm_expr.X_op = O_absent;
11491 case '9': /* Four DSP accumulators in bits 21,22. */
11492 gas_assert (!mips_opts.micromips);
11493 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c'
11494 && s[3] >= '0' && s[3] <= '3')
11496 regno = s[3] - '0';
11498 INSERT_OPERAND (0, DSPACC_S, *ip, regno);
11502 as_bad (_("Invalid dsp acc register"));
11506 /* DSP 6-bit signed immediate in bit 20 (for standard MIPS
11507 code) or 16 (for microMIPS code). */
11509 long mask = (mips_opts.micromips
11510 ? MICROMIPSOP_MASK_DSPSFT : OP_MASK_DSPSFT);
11512 my_getExpression (&imm_expr, s);
11513 check_absolute_expr (ip, &imm_expr);
11514 min_range = -((mask + 1) >> 1);
11515 max_range = ((mask + 1) >> 1) - 1;
11516 if (imm_expr.X_add_number < min_range
11517 || imm_expr.X_add_number > max_range)
11518 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11519 (long) min_range, (long) max_range,
11520 (long) imm_expr.X_add_number);
11521 INSERT_OPERAND (mips_opts.micromips,
11522 DSPSFT, *ip, imm_expr.X_add_number);
11523 imm_expr.X_op = O_absent;
11528 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
11529 gas_assert (!mips_opts.micromips);
11530 my_getExpression (&imm_expr, s);
11531 check_absolute_expr (ip, &imm_expr);
11532 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
11534 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11536 (unsigned long) imm_expr.X_add_number);
11538 INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number);
11539 imm_expr.X_op = O_absent;
11543 case ':': /* DSP 7-bit signed immediate in bit 19. */
11544 gas_assert (!mips_opts.micromips);
11545 my_getExpression (&imm_expr, s);
11546 check_absolute_expr (ip, &imm_expr);
11547 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
11548 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
11549 if (imm_expr.X_add_number < min_range ||
11550 imm_expr.X_add_number > max_range)
11552 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11553 (long) min_range, (long) max_range,
11554 (long) imm_expr.X_add_number);
11556 INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number);
11557 imm_expr.X_op = O_absent;
11561 case '@': /* DSP 10-bit signed immediate in bit 16. */
11563 long mask = (mips_opts.micromips
11564 ? MICROMIPSOP_MASK_IMM10 : OP_MASK_IMM10);
11566 my_getExpression (&imm_expr, s);
11567 check_absolute_expr (ip, &imm_expr);
11568 min_range = -((mask + 1) >> 1);
11569 max_range = ((mask + 1) >> 1) - 1;
11570 if (imm_expr.X_add_number < min_range
11571 || imm_expr.X_add_number > max_range)
11572 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11573 (long) min_range, (long) max_range,
11574 (long) imm_expr.X_add_number);
11575 INSERT_OPERAND (mips_opts.micromips,
11576 IMM10, *ip, imm_expr.X_add_number);
11577 imm_expr.X_op = O_absent;
11582 case '^': /* DSP 5-bit unsigned immediate in bit 11. */
11583 gas_assert (mips_opts.micromips);
11584 my_getExpression (&imm_expr, s);
11585 check_absolute_expr (ip, &imm_expr);
11586 if (imm_expr.X_add_number & ~MICROMIPSOP_MASK_RD)
11587 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11588 MICROMIPSOP_MASK_RD,
11589 (unsigned long) imm_expr.X_add_number);
11590 INSERT_OPERAND (1, RD, *ip, imm_expr.X_add_number);
11591 imm_expr.X_op = O_absent;
11595 case '!': /* MT usermode flag bit. */
11596 gas_assert (!mips_opts.micromips);
11597 my_getExpression (&imm_expr, s);
11598 check_absolute_expr (ip, &imm_expr);
11599 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
11600 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
11601 (unsigned long) imm_expr.X_add_number);
11602 INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number);
11603 imm_expr.X_op = O_absent;
11607 case '$': /* MT load high flag bit. */
11608 gas_assert (!mips_opts.micromips);
11609 my_getExpression (&imm_expr, s);
11610 check_absolute_expr (ip, &imm_expr);
11611 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
11612 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
11613 (unsigned long) imm_expr.X_add_number);
11614 INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number);
11615 imm_expr.X_op = O_absent;
11619 case '*': /* Four DSP accumulators in bits 18,19. */
11620 gas_assert (!mips_opts.micromips);
11621 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
11622 s[3] >= '0' && s[3] <= '3')
11624 regno = s[3] - '0';
11626 INSERT_OPERAND (0, MTACC_T, *ip, regno);
11630 as_bad (_("Invalid dsp/smartmips acc register"));
11633 case '&': /* Four DSP accumulators in bits 13,14. */
11634 gas_assert (!mips_opts.micromips);
11635 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
11636 s[3] >= '0' && s[3] <= '3')
11638 regno = s[3] - '0';
11640 INSERT_OPERAND (0, MTACC_D, *ip, regno);
11644 as_bad (_("Invalid dsp/smartmips acc register"));
11647 case '\\': /* 3-bit bit position. */
11649 unsigned long mask = (mips_opts.micromips
11650 ? MICROMIPSOP_MASK_3BITPOS
11651 : OP_MASK_3BITPOS);
11653 my_getExpression (&imm_expr, s);
11654 check_absolute_expr (ip, &imm_expr);
11655 if ((unsigned long) imm_expr.X_add_number > mask)
11656 as_warn (_("Bit position for %s not in range 0..%lu (%lu)"),
11658 mask, (unsigned long) imm_expr.X_add_number);
11659 INSERT_OPERAND (mips_opts.micromips,
11660 3BITPOS, *ip, imm_expr.X_add_number);
11661 imm_expr.X_op = O_absent;
11675 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
11679 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
11683 gas_assert (!mips_opts.micromips);
11684 INSERT_OPERAND (0, FT, *ip, lastregno);
11688 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
11694 /* Handle optional base register.
11695 Either the base register is omitted or
11696 we must have a left paren. */
11697 /* This is dependent on the next operand specifier
11698 is a base register specification. */
11699 gas_assert (args[1] == 'b'
11700 || (mips_opts.micromips
11702 && (args[2] == 'l' || args[2] == 'n'
11703 || args[2] == 's' || args[2] == 'a')));
11704 if (*s == '\0' && args[1] == 'b')
11706 /* Fall through. */
11708 case ')': /* These must match exactly. */
11713 case '+': /* Opcode extension character. */
11716 case '1': /* UDI immediates. */
11720 gas_assert (!mips_opts.micromips);
11722 const struct mips_immed *imm = mips_immed;
11724 while (imm->type && imm->type != *args)
11728 my_getExpression (&imm_expr, s);
11729 check_absolute_expr (ip, &imm_expr);
11730 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
11732 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
11733 imm->desc ? imm->desc : ip->insn_mo->name,
11734 (unsigned long) imm_expr.X_add_number,
11735 (unsigned long) imm_expr.X_add_number);
11736 imm_expr.X_add_number &= imm->mask;
11738 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
11740 imm_expr.X_op = O_absent;
11745 case 'J': /* 10-bit hypcall code. */
11746 gas_assert (!mips_opts.micromips);
11748 unsigned long mask = OP_MASK_CODE10;
11750 my_getExpression (&imm_expr, s);
11751 check_absolute_expr (ip, &imm_expr);
11752 if ((unsigned long) imm_expr.X_add_number > mask)
11753 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11755 mask, (unsigned long) imm_expr.X_add_number);
11756 INSERT_OPERAND (0, CODE10, *ip, imm_expr.X_add_number);
11757 imm_expr.X_op = O_absent;
11762 case 'A': /* ins/ext position, becomes LSB. */
11771 my_getExpression (&imm_expr, s);
11772 check_absolute_expr (ip, &imm_expr);
11773 if ((unsigned long) imm_expr.X_add_number < limlo
11774 || (unsigned long) imm_expr.X_add_number > limhi)
11776 as_bad (_("Improper position (%lu)"),
11777 (unsigned long) imm_expr.X_add_number);
11778 imm_expr.X_add_number = limlo;
11780 lastpos = imm_expr.X_add_number;
11781 INSERT_OPERAND (mips_opts.micromips,
11782 EXTLSB, *ip, imm_expr.X_add_number);
11783 imm_expr.X_op = O_absent;
11787 case 'B': /* ins size, becomes MSB. */
11796 my_getExpression (&imm_expr, s);
11797 check_absolute_expr (ip, &imm_expr);
11798 /* Check for negative input so that small negative numbers
11799 will not succeed incorrectly. The checks against
11800 (pos+size) transitively check "size" itself,
11801 assuming that "pos" is reasonable. */
11802 if ((long) imm_expr.X_add_number < 0
11803 || ((unsigned long) imm_expr.X_add_number
11805 || ((unsigned long) imm_expr.X_add_number
11806 + lastpos) > limhi)
11808 as_bad (_("Improper insert size (%lu, position %lu)"),
11809 (unsigned long) imm_expr.X_add_number,
11810 (unsigned long) lastpos);
11811 imm_expr.X_add_number = limlo - lastpos;
11813 INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip,
11814 lastpos + imm_expr.X_add_number - 1);
11815 imm_expr.X_op = O_absent;
11819 case 'C': /* ext size, becomes MSBD. */
11835 my_getExpression (&imm_expr, s);
11836 check_absolute_expr (ip, &imm_expr);
11837 /* The checks against (pos+size) don't transitively check
11838 "size" itself, assuming that "pos" is reasonable.
11839 We also need to check the lower bound of "size". */
11840 if ((long) imm_expr.X_add_number < sizelo
11841 || ((unsigned long) imm_expr.X_add_number
11843 || ((unsigned long) imm_expr.X_add_number
11844 + lastpos) > limhi)
11846 as_bad (_("Improper extract size (%lu, position %lu)"),
11847 (unsigned long) imm_expr.X_add_number,
11848 (unsigned long) lastpos);
11849 imm_expr.X_add_number = limlo - lastpos;
11851 INSERT_OPERAND (mips_opts.micromips,
11852 EXTMSBD, *ip, imm_expr.X_add_number - 1);
11853 imm_expr.X_op = O_absent;
11858 /* "+I" is like "I", except that imm2_expr is used. */
11859 my_getExpression (&imm2_expr, s);
11860 if (imm2_expr.X_op != O_big
11861 && imm2_expr.X_op != O_constant)
11862 insn_error = _("absolute expression required");
11863 if (HAVE_32BIT_GPRS)
11864 normalize_constant_expr (&imm2_expr);
11868 case 't': /* Coprocessor register number. */
11869 gas_assert (!mips_opts.micromips);
11870 if (s[0] == '$' && ISDIGIT (s[1]))
11880 while (ISDIGIT (*s));
11882 as_bad (_("Invalid register number (%d)"), regno);
11885 INSERT_OPERAND (0, RT, *ip, regno);
11890 as_bad (_("Invalid coprocessor 0 register number"));
11894 /* bbit[01] and bbit[01]32 bit index. Give error if index
11895 is not in the valid range. */
11896 gas_assert (!mips_opts.micromips);
11897 my_getExpression (&imm_expr, s);
11898 check_absolute_expr (ip, &imm_expr);
11899 if ((unsigned) imm_expr.X_add_number > 31)
11901 as_bad (_("Improper bit index (%lu)"),
11902 (unsigned long) imm_expr.X_add_number);
11903 imm_expr.X_add_number = 0;
11905 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number);
11906 imm_expr.X_op = O_absent;
11911 /* bbit[01] bit index when bbit is used but we generate
11912 bbit[01]32 because the index is over 32. Move to the
11913 next candidate if index is not in the valid range. */
11914 gas_assert (!mips_opts.micromips);
11915 my_getExpression (&imm_expr, s);
11916 check_absolute_expr (ip, &imm_expr);
11917 if ((unsigned) imm_expr.X_add_number < 32
11918 || (unsigned) imm_expr.X_add_number > 63)
11920 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32);
11921 imm_expr.X_op = O_absent;
11926 /* cins, cins32, exts and exts32 position field. Give error
11927 if it's not in the valid range. */
11928 gas_assert (!mips_opts.micromips);
11929 my_getExpression (&imm_expr, s);
11930 check_absolute_expr (ip, &imm_expr);
11931 if ((unsigned) imm_expr.X_add_number > 31)
11933 as_bad (_("Improper position (%lu)"),
11934 (unsigned long) imm_expr.X_add_number);
11935 imm_expr.X_add_number = 0;
11937 lastpos = imm_expr.X_add_number;
11938 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number);
11939 imm_expr.X_op = O_absent;
11944 /* cins, cins32, exts and exts32 position field. Move to
11945 the next candidate if it's not in the valid range. */
11946 gas_assert (!mips_opts.micromips);
11947 my_getExpression (&imm_expr, s);
11948 check_absolute_expr (ip, &imm_expr);
11949 if ((unsigned) imm_expr.X_add_number < 32
11950 || (unsigned) imm_expr.X_add_number > 63)
11952 lastpos = imm_expr.X_add_number;
11953 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32);
11954 imm_expr.X_op = O_absent;
11959 /* cins32 and exts32 length-minus-one field. */
11960 gas_assert (!mips_opts.micromips);
11961 my_getExpression (&imm_expr, s);
11962 check_absolute_expr (ip, &imm_expr);
11963 if ((unsigned long) imm_expr.X_add_number > 31
11964 || (unsigned long) imm_expr.X_add_number + lastpos > 31)
11966 as_bad (_("Improper size (%lu)"),
11967 (unsigned long) imm_expr.X_add_number);
11968 imm_expr.X_add_number = 0;
11970 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11971 imm_expr.X_op = O_absent;
11976 /* cins/exts length-minus-one field. */
11977 gas_assert (!mips_opts.micromips);
11978 my_getExpression (&imm_expr, s);
11979 check_absolute_expr (ip, &imm_expr);
11980 if ((unsigned long) imm_expr.X_add_number > 31
11981 || (unsigned long) imm_expr.X_add_number + lastpos > 63)
11983 as_bad (_("Improper size (%lu)"),
11984 (unsigned long) imm_expr.X_add_number);
11985 imm_expr.X_add_number = 0;
11987 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11988 imm_expr.X_op = O_absent;
11993 /* seqi/snei immediate field. */
11994 gas_assert (!mips_opts.micromips);
11995 my_getExpression (&imm_expr, s);
11996 check_absolute_expr (ip, &imm_expr);
11997 if ((long) imm_expr.X_add_number < -512
11998 || (long) imm_expr.X_add_number >= 512)
12000 as_bad (_("Improper immediate (%ld)"),
12001 (long) imm_expr.X_add_number);
12002 imm_expr.X_add_number = 0;
12004 INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number);
12005 imm_expr.X_op = O_absent;
12009 case 'a': /* 8-bit signed offset in bit 6 */
12010 gas_assert (!mips_opts.micromips);
12011 my_getExpression (&imm_expr, s);
12012 check_absolute_expr (ip, &imm_expr);
12013 min_range = -((OP_MASK_OFFSET_A + 1) >> 1);
12014 max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1;
12015 if (imm_expr.X_add_number < min_range
12016 || imm_expr.X_add_number > max_range)
12018 as_bad (_("Offset not in range %ld..%ld (%ld)"),
12019 (long) min_range, (long) max_range,
12020 (long) imm_expr.X_add_number);
12022 INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number);
12023 imm_expr.X_op = O_absent;
12027 case 'b': /* 8-bit signed offset in bit 3 */
12028 gas_assert (!mips_opts.micromips);
12029 my_getExpression (&imm_expr, s);
12030 check_absolute_expr (ip, &imm_expr);
12031 min_range = -((OP_MASK_OFFSET_B + 1) >> 1);
12032 max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1;
12033 if (imm_expr.X_add_number < min_range
12034 || imm_expr.X_add_number > max_range)
12036 as_bad (_("Offset not in range %ld..%ld (%ld)"),
12037 (long) min_range, (long) max_range,
12038 (long) imm_expr.X_add_number);
12040 INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number);
12041 imm_expr.X_op = O_absent;
12045 case 'c': /* 9-bit signed offset in bit 6 */
12046 gas_assert (!mips_opts.micromips);
12047 my_getExpression (&imm_expr, s);
12048 check_absolute_expr (ip, &imm_expr);
12049 min_range = -((OP_MASK_OFFSET_C + 1) >> 1);
12050 max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1;
12051 /* We check the offset range before adjusted. */
12054 if (imm_expr.X_add_number < min_range
12055 || imm_expr.X_add_number > max_range)
12057 as_bad (_("Offset not in range %ld..%ld (%ld)"),
12058 (long) min_range, (long) max_range,
12059 (long) imm_expr.X_add_number);
12061 if (imm_expr.X_add_number & 0xf)
12063 as_bad (_("Offset not 16 bytes alignment (%ld)"),
12064 (long) imm_expr.X_add_number);
12066 /* Right shift 4 bits to adjust the offset operand. */
12067 INSERT_OPERAND (0, OFFSET_C, *ip,
12068 imm_expr.X_add_number >> 4);
12069 imm_expr.X_op = O_absent;
12074 gas_assert (!mips_opts.micromips);
12075 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
12077 if (regno == AT && mips_opts.at)
12079 if (mips_opts.at == ATREG)
12080 as_warn (_("used $at without \".set noat\""));
12082 as_warn (_("used $%u with \".set at=$%u\""),
12083 regno, mips_opts.at);
12085 INSERT_OPERAND (0, RZ, *ip, regno);
12089 gas_assert (!mips_opts.micromips);
12090 if (!reg_lookup (&s, RTYPE_FPU, ®no))
12092 INSERT_OPERAND (0, FZ, *ip, regno);
12102 /* Check whether there is only a single bracketed expression
12103 left. If so, it must be the base register and the
12104 constant must be zero. */
12105 if (*s == '(' && strchr (s + 1, '(') == 0)
12108 /* If this value won't fit into the offset, then go find
12109 a macro that will generate a 16- or 32-bit offset code
12111 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
12112 if ((i == 0 && (imm_expr.X_op != O_constant
12113 || imm_expr.X_add_number >= 1 << shift
12114 || imm_expr.X_add_number < -1 << shift))
12117 imm_expr.X_op = O_absent;
12120 INSERT_OPERAND (mips_opts.micromips, EVAOFFSET, *ip,
12121 imm_expr.X_add_number);
12122 imm_expr.X_op = O_absent;
12128 as_bad (_("Internal error: bad %s opcode "
12129 "(unknown extension operand type `+%c'): %s %s"),
12130 mips_opts.micromips ? "microMIPS" : "MIPS",
12131 *args, insn->name, insn->args);
12132 /* Further processing is fruitless. */
12137 case '.': /* 10-bit offset. */
12138 gas_assert (mips_opts.micromips);
12139 case '~': /* 12-bit offset. */
12141 int shift = *args == '.' ? 9 : 11;
12144 /* Check whether there is only a single bracketed expression
12145 left. If so, it must be the base register and the
12146 constant must be zero. */
12147 if (*s == '(' && strchr (s + 1, '(') == 0)
12150 /* If this value won't fit into the offset, then go find
12151 a macro that will generate a 16- or 32-bit offset code
12153 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
12154 if ((i == 0 && (imm_expr.X_op != O_constant
12155 || imm_expr.X_add_number >= 1 << shift
12156 || imm_expr.X_add_number < -1 << shift))
12159 imm_expr.X_op = O_absent;
12163 INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number);
12165 INSERT_OPERAND (mips_opts.micromips,
12166 OFFSET12, *ip, imm_expr.X_add_number);
12167 imm_expr.X_op = O_absent;
12172 case '<': /* must be at least one digit */
12174 * According to the manual, if the shift amount is greater
12175 * than 31 or less than 0, then the shift amount should be
12176 * mod 32. In reality the mips assembler issues an error.
12177 * We issue a warning and mask out all but the low 5 bits.
12179 my_getExpression (&imm_expr, s);
12180 check_absolute_expr (ip, &imm_expr);
12181 if ((unsigned long) imm_expr.X_add_number > 31)
12182 as_warn (_("Improper shift amount (%lu)"),
12183 (unsigned long) imm_expr.X_add_number);
12184 INSERT_OPERAND (mips_opts.micromips,
12185 SHAMT, *ip, imm_expr.X_add_number);
12186 imm_expr.X_op = O_absent;
12190 case '>': /* shift amount minus 32 */
12191 my_getExpression (&imm_expr, s);
12192 check_absolute_expr (ip, &imm_expr);
12193 if ((unsigned long) imm_expr.X_add_number < 32
12194 || (unsigned long) imm_expr.X_add_number > 63)
12196 INSERT_OPERAND (mips_opts.micromips,
12197 SHAMT, *ip, imm_expr.X_add_number - 32);
12198 imm_expr.X_op = O_absent;
12202 case 'k': /* CACHE code. */
12203 case 'h': /* PREFX code. */
12204 case '1': /* SYNC type. */
12205 my_getExpression (&imm_expr, s);
12206 check_absolute_expr (ip, &imm_expr);
12207 if ((unsigned long) imm_expr.X_add_number > 31)
12208 as_warn (_("Invalid value for `%s' (%lu)"),
12210 (unsigned long) imm_expr.X_add_number);
12214 if (mips_fix_cn63xxp1
12215 && !mips_opts.micromips
12216 && strcmp ("pref", insn->name) == 0)
12217 switch (imm_expr.X_add_number)
12226 case 31: /* These are ok. */
12229 default: /* The rest must be changed to 28. */
12230 imm_expr.X_add_number = 28;
12233 INSERT_OPERAND (mips_opts.micromips,
12234 CACHE, *ip, imm_expr.X_add_number);
12237 INSERT_OPERAND (mips_opts.micromips,
12238 PREFX, *ip, imm_expr.X_add_number);
12241 INSERT_OPERAND (mips_opts.micromips,
12242 STYPE, *ip, imm_expr.X_add_number);
12245 imm_expr.X_op = O_absent;
12249 case 'c': /* BREAK code. */
12251 unsigned long mask = (mips_opts.micromips
12252 ? MICROMIPSOP_MASK_CODE
12255 my_getExpression (&imm_expr, s);
12256 check_absolute_expr (ip, &imm_expr);
12257 if ((unsigned long) imm_expr.X_add_number > mask)
12258 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
12260 mask, (unsigned long) imm_expr.X_add_number);
12261 INSERT_OPERAND (mips_opts.micromips,
12262 CODE, *ip, imm_expr.X_add_number);
12263 imm_expr.X_op = O_absent;
12268 case 'q': /* Lower BREAK code. */
12270 unsigned long mask = (mips_opts.micromips
12271 ? MICROMIPSOP_MASK_CODE2
12274 my_getExpression (&imm_expr, s);
12275 check_absolute_expr (ip, &imm_expr);
12276 if ((unsigned long) imm_expr.X_add_number > mask)
12277 as_warn (_("Lower code for %s not in range 0..%lu (%lu)"),
12279 mask, (unsigned long) imm_expr.X_add_number);
12280 INSERT_OPERAND (mips_opts.micromips,
12281 CODE2, *ip, imm_expr.X_add_number);
12282 imm_expr.X_op = O_absent;
12287 case 'B': /* 20- or 10-bit syscall/break/wait code. */
12289 unsigned long mask = (mips_opts.micromips
12290 ? MICROMIPSOP_MASK_CODE10
12293 my_getExpression (&imm_expr, s);
12294 check_absolute_expr (ip, &imm_expr);
12295 if ((unsigned long) imm_expr.X_add_number > mask)
12296 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
12298 mask, (unsigned long) imm_expr.X_add_number);
12299 if (mips_opts.micromips)
12300 INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number);
12302 INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number);
12303 imm_expr.X_op = O_absent;
12308 case 'C': /* 25- or 23-bit coprocessor code. */
12310 unsigned long mask = (mips_opts.micromips
12311 ? MICROMIPSOP_MASK_COPZ
12314 my_getExpression (&imm_expr, s);
12315 check_absolute_expr (ip, &imm_expr);
12316 if ((unsigned long) imm_expr.X_add_number > mask)
12317 as_warn (_("Coproccesor code > %u bits (%lu)"),
12318 mips_opts.micromips ? 23U : 25U,
12319 (unsigned long) imm_expr.X_add_number);
12320 INSERT_OPERAND (mips_opts.micromips,
12321 COPZ, *ip, imm_expr.X_add_number);
12322 imm_expr.X_op = O_absent;
12327 case 'J': /* 19-bit WAIT code. */
12328 gas_assert (!mips_opts.micromips);
12329 my_getExpression (&imm_expr, s);
12330 check_absolute_expr (ip, &imm_expr);
12331 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
12333 as_warn (_("Illegal 19-bit code (%lu)"),
12334 (unsigned long) imm_expr.X_add_number);
12335 imm_expr.X_add_number &= OP_MASK_CODE19;
12337 INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number);
12338 imm_expr.X_op = O_absent;
12342 case 'P': /* Performance register. */
12343 gas_assert (!mips_opts.micromips);
12344 my_getExpression (&imm_expr, s);
12345 check_absolute_expr (ip, &imm_expr);
12346 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
12347 as_warn (_("Invalid performance register (%lu)"),
12348 (unsigned long) imm_expr.X_add_number);
12349 if (imm_expr.X_add_number != 0 && mips_opts.arch == CPU_R5900
12350 && (!strcmp(insn->name,"mfps") || !strcmp(insn->name,"mtps")))
12351 as_warn (_("Invalid performance register (%lu)"),
12352 (unsigned long) imm_expr.X_add_number);
12353 INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number);
12354 imm_expr.X_op = O_absent;
12358 case 'G': /* Coprocessor destination register. */
12360 unsigned long opcode = ip->insn_opcode;
12361 unsigned long mask;
12362 unsigned int types;
12365 if (mips_opts.micromips)
12367 mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT)
12368 | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)
12369 | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL));
12373 case 0x000000fc: /* mfc0 */
12374 case 0x000002fc: /* mtc0 */
12375 case 0x580000fc: /* dmfc0 */
12376 case 0x580002fc: /* dmtc0 */
12386 opcode = (opcode >> OP_SH_OP) & OP_MASK_OP;
12387 cop0 = opcode == OP_OP_COP0;
12389 types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP);
12390 ok = reg_lookup (&s, types, ®no);
12391 if (mips_opts.micromips)
12392 INSERT_OPERAND (1, RS, *ip, regno);
12394 INSERT_OPERAND (0, RD, *ip, regno);
12403 case 'y': /* ALNV.PS source register. */
12404 gas_assert (mips_opts.micromips);
12406 case 'x': /* Ignore register name. */
12407 case 'U': /* Destination register (CLO/CLZ). */
12408 case 'g': /* Coprocessor destination register. */
12409 gas_assert (!mips_opts.micromips);
12410 case 'b': /* Base register. */
12411 case 'd': /* Destination register. */
12412 case 's': /* Source register. */
12413 case 't': /* Target register. */
12414 case 'r': /* Both target and source. */
12415 case 'v': /* Both dest and source. */
12416 case 'w': /* Both dest and target. */
12417 case 'E': /* Coprocessor target register. */
12418 case 'K': /* RDHWR destination register. */
12419 case 'z': /* Must be zero register. */
12422 if (*args == 'E' || *args == 'K')
12423 ok = reg_lookup (&s, RTYPE_NUM, ®no);
12426 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
12427 if (regno == AT && mips_opts.at)
12429 if (mips_opts.at == ATREG)
12430 as_warn (_("Used $at without \".set noat\""));
12432 as_warn (_("Used $%u with \".set at=$%u\""),
12433 regno, mips_opts.at);
12443 if (c == 'r' || c == 'v' || c == 'w')
12450 /* 'z' only matches $0. */
12451 if (c == 'z' && regno != 0)
12454 if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
12456 if (regno == lastregno)
12459 = _("Source and destination must be different");
12462 if (regno == 31 && lastregno == 0xffffffff)
12465 = _("A destination register must be supplied");
12469 /* Now that we have assembled one operand, we use the args
12470 string to figure out where it goes in the instruction. */
12477 INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno);
12481 if (mips_opts.micromips)
12482 INSERT_OPERAND (1, RS, *ip, regno);
12484 INSERT_OPERAND (0, RD, *ip, regno);
12489 INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno);
12493 gas_assert (!mips_opts.micromips);
12494 INSERT_OPERAND (0, RD, *ip, regno);
12495 INSERT_OPERAND (0, RT, *ip, regno);
12501 INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno);
12505 gas_assert (mips_opts.micromips);
12506 INSERT_OPERAND (1, RS3, *ip, regno);
12510 /* This case exists because on the r3000 trunc
12511 expands into a macro which requires a gp
12512 register. On the r6000 or r4000 it is
12513 assembled into a single instruction which
12514 ignores the register. Thus the insn version
12515 is MIPS_ISA2 and uses 'x', and the macro
12516 version is MIPS_ISA1 and uses 't'. */
12520 /* This case is for the div instruction, which
12521 acts differently if the destination argument
12522 is $0. This only matches $0, and is checked
12523 outside the switch. */
12533 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
12537 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
12542 case 'O': /* MDMX alignment immediate constant. */
12543 gas_assert (!mips_opts.micromips);
12544 my_getExpression (&imm_expr, s);
12545 check_absolute_expr (ip, &imm_expr);
12546 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
12547 as_warn (_("Improper align amount (%ld), using low bits"),
12548 (long) imm_expr.X_add_number);
12549 INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number);
12550 imm_expr.X_op = O_absent;
12554 case 'Q': /* MDMX vector, element sel, or const. */
12557 /* MDMX Immediate. */
12558 gas_assert (!mips_opts.micromips);
12559 my_getExpression (&imm_expr, s);
12560 check_absolute_expr (ip, &imm_expr);
12561 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
12562 as_warn (_("Invalid MDMX Immediate (%ld)"),
12563 (long) imm_expr.X_add_number);
12564 INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number);
12565 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
12566 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
12568 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
12569 imm_expr.X_op = O_absent;
12573 /* Not MDMX Immediate. Fall through. */
12574 case 'X': /* MDMX destination register. */
12575 case 'Y': /* MDMX source register. */
12576 case 'Z': /* MDMX target register. */
12577 is_mdmx = !(insn->membership & INSN_5400);
12579 gas_assert (!mips_opts.micromips);
12580 case 'D': /* Floating point destination register. */
12581 case 'S': /* Floating point source register. */
12582 case 'T': /* Floating point target register. */
12583 case 'R': /* Floating point source register. */
12587 || ((mips_opts.ase & ASE_MDMX)
12588 && (ip->insn_mo->pinfo & FP_D)
12589 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
12590 | INSN_COPROC_MEMORY_DELAY
12591 | INSN_LOAD_COPROC_DELAY
12592 | INSN_LOAD_MEMORY_DELAY
12593 | INSN_STORE_MEMORY))))
12594 rtype |= RTYPE_VEC;
12596 if (reg_lookup (&s, rtype, ®no))
12598 if ((regno & 1) != 0
12600 && !mips_oddfpreg_ok (ip->insn_mo, argnum))
12601 as_warn (_("Float register should be even, was %d"),
12609 if (c == 'V' || c == 'W')
12620 INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno);
12626 INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno);
12630 /* This is like 'Z', but also needs to fix the MDMX
12631 vector/scalar select bits. Note that the
12632 scalar immediate case is handled above. */
12633 if ((ip->insn_mo->membership & INSN_5400)
12634 && strcmp (insn->name, "rzu.ob") == 0)
12635 as_bad (_("Operand %d of `%s' must be an immediate"),
12636 argnum, ip->insn_mo->name);
12640 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
12641 int max_el = (is_qh ? 3 : 7);
12643 my_getExpression(&imm_expr, s);
12644 check_absolute_expr (ip, &imm_expr);
12646 if (imm_expr.X_add_number > max_el)
12647 as_bad (_("Bad element selector %ld"),
12648 (long) imm_expr.X_add_number);
12649 imm_expr.X_add_number &= max_el;
12650 ip->insn_opcode |= (imm_expr.X_add_number
12653 imm_expr.X_op = O_absent;
12655 as_warn (_("Expecting ']' found '%s'"), s);
12661 if ((ip->insn_mo->membership & INSN_5400)
12662 && (strcmp (insn->name, "sll.ob") == 0
12663 || strcmp (insn->name, "srl.ob") == 0))
12664 as_bad (_("Operand %d of `%s' must be scalar"),
12665 argnum, ip->insn_mo->name);
12667 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
12668 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
12671 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
12674 /* Fall through. */
12678 INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno);
12682 INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno);
12692 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
12696 INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno);
12702 my_getExpression (&imm_expr, s);
12703 if (imm_expr.X_op != O_big
12704 && imm_expr.X_op != O_constant)
12705 insn_error = _("absolute expression required");
12706 if (HAVE_32BIT_GPRS)
12707 normalize_constant_expr (&imm_expr);
12712 my_getSmallExpression (&offset_expr, offset_reloc, s);
12713 if (offset_expr.X_op == O_register)
12715 /* Assume that the offset has been elided and that what
12716 we saw was a base register. The match will fail later
12717 if that assumption turns out to be wrong. */
12718 offset_expr.X_op = O_constant;
12719 offset_expr.X_add_number = 0;
12723 normalize_address_expr (&offset_expr);
12737 unsigned char temp[8];
12739 unsigned int length;
12744 /* These only appear as the last operand in an
12745 instruction, and every instruction that accepts
12746 them in any variant accepts them in all variants.
12747 This means we don't have to worry about backing out
12748 any changes if the instruction does not match.
12750 The difference between them is the size of the
12751 floating point constant and where it goes. For 'F'
12752 and 'L' the constant is 64 bits; for 'f' and 'l' it
12753 is 32 bits. Where the constant is placed is based
12754 on how the MIPS assembler does things:
12757 f -- immediate value
12760 The .lit4 and .lit8 sections are only used if
12761 permitted by the -G argument.
12763 The code below needs to know whether the target register
12764 is 32 or 64 bits wide. It relies on the fact 'f' and
12765 'F' are used with GPR-based instructions and 'l' and
12766 'L' are used with FPR-based instructions. */
12768 f64 = *args == 'F' || *args == 'L';
12769 using_gprs = *args == 'F' || *args == 'f';
12771 save_in = input_line_pointer;
12772 input_line_pointer = s;
12773 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
12775 s = input_line_pointer;
12776 input_line_pointer = save_in;
12777 if (err != NULL && *err != '\0')
12779 as_bad (_("Bad floating point constant: %s"), err);
12780 memset (temp, '\0', sizeof temp);
12781 length = f64 ? 8 : 4;
12784 gas_assert (length == (unsigned) (f64 ? 8 : 4));
12788 && (g_switch_value < 4
12789 || (temp[0] == 0 && temp[1] == 0)
12790 || (temp[2] == 0 && temp[3] == 0))))
12792 imm_expr.X_op = O_constant;
12793 if (!target_big_endian)
12794 imm_expr.X_add_number = bfd_getl32 (temp);
12796 imm_expr.X_add_number = bfd_getb32 (temp);
12798 else if (length > 4
12799 && !mips_disable_float_construction
12800 /* Constants can only be constructed in GPRs and
12801 copied to FPRs if the GPRs are at least as wide
12802 as the FPRs. Force the constant into memory if
12803 we are using 64-bit FPRs but the GPRs are only
12806 || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
12807 && ((temp[0] == 0 && temp[1] == 0)
12808 || (temp[2] == 0 && temp[3] == 0))
12809 && ((temp[4] == 0 && temp[5] == 0)
12810 || (temp[6] == 0 && temp[7] == 0)))
12812 /* The value is simple enough to load with a couple of
12813 instructions. If using 32-bit registers, set
12814 imm_expr to the high order 32 bits and offset_expr to
12815 the low order 32 bits. Otherwise, set imm_expr to
12816 the entire 64 bit constant. */
12817 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
12819 imm_expr.X_op = O_constant;
12820 offset_expr.X_op = O_constant;
12821 if (!target_big_endian)
12823 imm_expr.X_add_number = bfd_getl32 (temp + 4);
12824 offset_expr.X_add_number = bfd_getl32 (temp);
12828 imm_expr.X_add_number = bfd_getb32 (temp);
12829 offset_expr.X_add_number = bfd_getb32 (temp + 4);
12831 if (offset_expr.X_add_number == 0)
12832 offset_expr.X_op = O_absent;
12836 imm_expr.X_op = O_constant;
12837 if (!target_big_endian)
12838 imm_expr.X_add_number = bfd_getl64 (temp);
12840 imm_expr.X_add_number = bfd_getb64 (temp);
12845 const char *newname;
12848 /* Switch to the right section. */
12850 subseg = now_subseg;
12853 default: /* unused default case avoids warnings. */
12855 newname = RDATA_SECTION_NAME;
12856 if (g_switch_value >= 8)
12860 newname = RDATA_SECTION_NAME;
12863 gas_assert (g_switch_value >= 4);
12867 new_seg = subseg_new (newname, (subsegT) 0);
12868 bfd_set_section_flags (stdoutput, new_seg,
12873 frag_align (*args == 'l' ? 2 : 3, 0, 0);
12874 if (strncmp (TARGET_OS, "elf", 3) != 0)
12875 record_alignment (new_seg, 4);
12877 record_alignment (new_seg, *args == 'l' ? 2 : 3);
12878 if (seg == now_seg)
12879 as_bad (_("Can't use floating point insn in this section"));
12881 /* Set the argument to the current address in the
12883 offset_expr.X_op = O_symbol;
12884 offset_expr.X_add_symbol = symbol_temp_new_now ();
12885 offset_expr.X_add_number = 0;
12887 /* Put the floating point number into the section. */
12888 p = frag_more ((int) length);
12889 memcpy (p, temp, length);
12891 /* Switch back to the original section. */
12892 subseg_set (seg, subseg);
12897 case 'i': /* 16-bit unsigned immediate. */
12898 case 'j': /* 16-bit signed immediate. */
12899 *imm_reloc = BFD_RELOC_LO16;
12900 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
12903 offsetT minval, maxval;
12905 more = (insn + 1 < past
12906 && strcmp (insn->name, insn[1].name) == 0);
12908 /* For compatibility with older assemblers, we accept
12909 0x8000-0xffff as signed 16-bit numbers when only
12910 signed numbers are allowed. */
12912 minval = 0, maxval = 0xffff;
12914 minval = -0x8000, maxval = 0x7fff;
12916 minval = -0x8000, maxval = 0xffff;
12918 if (imm_expr.X_op != O_constant
12919 || imm_expr.X_add_number < minval
12920 || imm_expr.X_add_number > maxval)
12924 if (imm_expr.X_op == O_constant
12925 || imm_expr.X_op == O_big)
12926 as_bad (_("Expression out of range"));
12932 case 'o': /* 16-bit offset. */
12933 offset_reloc[0] = BFD_RELOC_LO16;
12934 offset_reloc[1] = BFD_RELOC_UNUSED;
12935 offset_reloc[2] = BFD_RELOC_UNUSED;
12937 /* Check whether there is only a single bracketed expression
12938 left. If so, it must be the base register and the
12939 constant must be zero. */
12940 if (*s == '(' && strchr (s + 1, '(') == 0)
12942 offset_expr.X_op = O_constant;
12943 offset_expr.X_add_number = 0;
12947 /* If this value won't fit into a 16 bit offset, then go
12948 find a macro that will generate the 32 bit offset
12950 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
12951 && (offset_expr.X_op != O_constant
12952 || offset_expr.X_add_number >= 0x8000
12953 || offset_expr.X_add_number < -0x8000))
12959 case 'p': /* PC-relative offset. */
12960 *offset_reloc = BFD_RELOC_16_PCREL_S2;
12961 my_getExpression (&offset_expr, s);
12965 case 'u': /* Upper 16 bits. */
12966 *imm_reloc = BFD_RELOC_LO16;
12967 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
12968 && imm_expr.X_op == O_constant
12969 && (imm_expr.X_add_number < 0
12970 || imm_expr.X_add_number >= 0x10000))
12971 as_bad (_("lui expression (%lu) not in range 0..65535"),
12972 (unsigned long) imm_expr.X_add_number);
12976 case 'a': /* 26-bit address. */
12978 *offset_reloc = BFD_RELOC_MIPS_JMP;
12979 my_getExpression (&offset_expr, s);
12983 case 'N': /* 3-bit branch condition code. */
12984 case 'M': /* 3-bit compare condition code. */
12986 if (ip->insn_mo->pinfo & (FP_D | FP_S))
12987 rtype |= RTYPE_FCC;
12988 if (!reg_lookup (&s, rtype, ®no))
12990 if ((strcmp (str + strlen (str) - 3, ".ps") == 0
12991 || strcmp (str + strlen (str) - 5, "any2f") == 0
12992 || strcmp (str + strlen (str) - 5, "any2t") == 0)
12993 && (regno & 1) != 0)
12994 as_warn (_("Condition code register should be even for %s, "
12997 if ((strcmp (str + strlen (str) - 5, "any4f") == 0
12998 || strcmp (str + strlen (str) - 5, "any4t") == 0)
12999 && (regno & 3) != 0)
13000 as_warn (_("Condition code register should be 0 or 4 for %s, "
13004 INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno);
13006 INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno);
13010 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
13021 while (ISDIGIT (*s));
13024 c = 8; /* Invalid sel value. */
13027 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
13028 INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c);
13032 gas_assert (!mips_opts.micromips);
13033 /* Must be at least one digit. */
13034 my_getExpression (&imm_expr, s);
13035 check_absolute_expr (ip, &imm_expr);
13037 if ((unsigned long) imm_expr.X_add_number
13038 > (unsigned long) OP_MASK_VECBYTE)
13040 as_bad (_("bad byte vector index (%ld)"),
13041 (long) imm_expr.X_add_number);
13042 imm_expr.X_add_number = 0;
13045 INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number);
13046 imm_expr.X_op = O_absent;
13051 gas_assert (!mips_opts.micromips);
13052 my_getExpression (&imm_expr, s);
13053 check_absolute_expr (ip, &imm_expr);
13055 if ((unsigned long) imm_expr.X_add_number
13056 > (unsigned long) OP_MASK_VECALIGN)
13058 as_bad (_("bad byte vector index (%ld)"),
13059 (long) imm_expr.X_add_number);
13060 imm_expr.X_add_number = 0;
13063 INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number);
13064 imm_expr.X_op = O_absent;
13068 case 'm': /* Opcode extension character. */
13069 gas_assert (mips_opts.micromips);
13074 if (strncmp (s, "$pc", 3) == 0)
13101 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
13102 if (regno == AT && mips_opts.at)
13104 if (mips_opts.at == ATREG)
13105 as_warn (_("Used $at without \".set noat\""));
13107 as_warn (_("Used $%u with \".set at=$%u\""),
13108 regno, mips_opts.at);
13114 gas_assert (args[1] == ',');
13120 gas_assert (args[1] == ',');
13122 continue; /* Nothing to do. */
13128 if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4))
13130 if (regno == lastregno)
13133 = _("Source and destination must be different");
13136 if (regno == 31 && lastregno == 0xffffffff)
13139 = _("A destination register must be supplied");
13150 gas_assert (args[1] == ',');
13157 gas_assert (args[1] == ',');
13160 continue; /* Nothing to do. */
13164 /* Make sure regno is the same as lastregno. */
13165 if (c == 't' && regno != lastregno)
13168 /* Make sure regno is the same as destregno. */
13169 if (c == 'x' && regno != destregno)
13172 /* We need to save regno, before regno maps to the
13173 microMIPS register encoding. */
13183 regno = ILLEGAL_REG;
13187 regno = mips32_to_micromips_reg_b_map[regno];
13191 regno = mips32_to_micromips_reg_c_map[regno];
13195 regno = mips32_to_micromips_reg_d_map[regno];
13199 regno = mips32_to_micromips_reg_e_map[regno];
13203 regno = mips32_to_micromips_reg_f_map[regno];
13207 regno = mips32_to_micromips_reg_g_map[regno];
13211 s += strspn (s, " \t");
13214 regno = ILLEGAL_REG;
13218 s += strspn (s, " \t");
13219 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no2);
13222 regno = ILLEGAL_REG;
13225 if (regno2 == AT && mips_opts.at)
13227 if (mips_opts.at == ATREG)
13228 as_warn (_("Used $at without \".set noat\""));
13230 as_warn (_("Used $%u with \".set at=$%u\""),
13231 regno2, mips_opts.at);
13233 regno = (mips_lookup_reg_pair
13235 micromips_to_32_reg_h_map1,
13236 micromips_to_32_reg_h_map2, 8));
13240 regno = mips32_to_micromips_reg_l_map[regno];
13244 regno = mips32_to_micromips_reg_m_map[regno];
13248 regno = mips32_to_micromips_reg_n_map[regno];
13252 regno = mips32_to_micromips_reg_q_map[regno];
13257 regno = ILLEGAL_REG;
13262 regno = ILLEGAL_REG;
13267 regno = ILLEGAL_REG;
13270 case 'j': /* Do nothing. */
13280 if (regno == ILLEGAL_REG)
13286 INSERT_OPERAND (1, MB, *ip, regno);
13290 INSERT_OPERAND (1, MC, *ip, regno);
13294 INSERT_OPERAND (1, MD, *ip, regno);
13298 INSERT_OPERAND (1, ME, *ip, regno);
13302 INSERT_OPERAND (1, MF, *ip, regno);
13306 INSERT_OPERAND (1, MG, *ip, regno);
13310 INSERT_OPERAND (1, MH, *ip, regno);
13314 INSERT_OPERAND (1, MJ, *ip, regno);
13318 INSERT_OPERAND (1, ML, *ip, regno);
13322 INSERT_OPERAND (1, MM, *ip, regno);
13326 INSERT_OPERAND (1, MN, *ip, regno);
13330 INSERT_OPERAND (1, MP, *ip, regno);
13334 INSERT_OPERAND (1, MQ, *ip, regno);
13337 case 'a': /* Do nothing. */
13338 case 's': /* Do nothing. */
13339 case 't': /* Do nothing. */
13340 case 'x': /* Do nothing. */
13341 case 'y': /* Do nothing. */
13342 case 'z': /* Do nothing. */
13352 bfd_reloc_code_real_type r[3];
13356 /* Check whether there is only a single bracketed
13357 expression left. If so, it must be the base register
13358 and the constant must be zero. */
13359 if (*s == '(' && strchr (s + 1, '(') == 0)
13361 INSERT_OPERAND (1, IMMA, *ip, 0);
13365 if (my_getSmallExpression (&ep, r, s) > 0
13366 || !expr_const_in_range (&ep, -64, 64, 2))
13369 imm = ep.X_add_number >> 2;
13370 INSERT_OPERAND (1, IMMA, *ip, imm);
13377 bfd_reloc_code_real_type r[3];
13381 if (my_getSmallExpression (&ep, r, s) > 0
13382 || ep.X_op != O_constant)
13385 for (imm = 0; imm < 8; imm++)
13386 if (micromips_imm_b_map[imm] == ep.X_add_number)
13391 INSERT_OPERAND (1, IMMB, *ip, imm);
13398 bfd_reloc_code_real_type r[3];
13402 if (my_getSmallExpression (&ep, r, s) > 0
13403 || ep.X_op != O_constant)
13406 for (imm = 0; imm < 16; imm++)
13407 if (micromips_imm_c_map[imm] == ep.X_add_number)
13412 INSERT_OPERAND (1, IMMC, *ip, imm);
13417 case 'D': /* pc relative offset */
13418 case 'E': /* pc relative offset */
13419 my_getExpression (&offset_expr, s);
13420 if (offset_expr.X_op == O_register)
13423 if (!forced_insn_length)
13424 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
13426 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
13428 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
13434 bfd_reloc_code_real_type r[3];
13438 if (my_getSmallExpression (&ep, r, s) > 0
13439 || !expr_const_in_range (&ep, 0, 16, 0))
13442 imm = ep.X_add_number;
13443 INSERT_OPERAND (1, IMMF, *ip, imm);
13450 bfd_reloc_code_real_type r[3];
13454 /* Check whether there is only a single bracketed
13455 expression left. If so, it must be the base register
13456 and the constant must be zero. */
13457 if (*s == '(' && strchr (s + 1, '(') == 0)
13459 INSERT_OPERAND (1, IMMG, *ip, 0);
13463 if (my_getSmallExpression (&ep, r, s) > 0
13464 || !expr_const_in_range (&ep, -1, 15, 0))
13467 imm = ep.X_add_number & 15;
13468 INSERT_OPERAND (1, IMMG, *ip, imm);
13475 bfd_reloc_code_real_type r[3];
13479 /* Check whether there is only a single bracketed
13480 expression left. If so, it must be the base register
13481 and the constant must be zero. */
13482 if (*s == '(' && strchr (s + 1, '(') == 0)
13484 INSERT_OPERAND (1, IMMH, *ip, 0);
13488 if (my_getSmallExpression (&ep, r, s) > 0
13489 || !expr_const_in_range (&ep, 0, 16, 1))
13492 imm = ep.X_add_number >> 1;
13493 INSERT_OPERAND (1, IMMH, *ip, imm);
13500 bfd_reloc_code_real_type r[3];
13504 if (my_getSmallExpression (&ep, r, s) > 0
13505 || !expr_const_in_range (&ep, -1, 127, 0))
13508 imm = ep.X_add_number & 127;
13509 INSERT_OPERAND (1, IMMI, *ip, imm);
13516 bfd_reloc_code_real_type r[3];
13520 /* Check whether there is only a single bracketed
13521 expression left. If so, it must be the base register
13522 and the constant must be zero. */
13523 if (*s == '(' && strchr (s + 1, '(') == 0)
13525 INSERT_OPERAND (1, IMMJ, *ip, 0);
13529 if (my_getSmallExpression (&ep, r, s) > 0
13530 || !expr_const_in_range (&ep, 0, 16, 2))
13533 imm = ep.X_add_number >> 2;
13534 INSERT_OPERAND (1, IMMJ, *ip, imm);
13541 bfd_reloc_code_real_type r[3];
13545 /* Check whether there is only a single bracketed
13546 expression left. If so, it must be the base register
13547 and the constant must be zero. */
13548 if (*s == '(' && strchr (s + 1, '(') == 0)
13550 INSERT_OPERAND (1, IMML, *ip, 0);
13554 if (my_getSmallExpression (&ep, r, s) > 0
13555 || !expr_const_in_range (&ep, 0, 16, 0))
13558 imm = ep.X_add_number;
13559 INSERT_OPERAND (1, IMML, *ip, imm);
13566 bfd_reloc_code_real_type r[3];
13570 if (my_getSmallExpression (&ep, r, s) > 0
13571 || !expr_const_in_range (&ep, 1, 9, 0))
13574 imm = ep.X_add_number & 7;
13575 INSERT_OPERAND (1, IMMM, *ip, imm);
13580 case 'N': /* Register list for lwm and swm. */
13582 /* A comma-separated list of registers and/or
13583 dash-separated contiguous ranges including
13584 both ra and a set of one or more registers
13585 starting at s0 up to s3 which have to be
13592 and any permutations of these. */
13593 unsigned int reglist;
13596 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
13599 if ((reglist & 0xfff1ffff) != 0x80010000)
13602 reglist = (reglist >> 17) & 7;
13604 if ((reglist & -reglist) != reglist)
13607 imm = ffs (reglist) - 1;
13608 INSERT_OPERAND (1, IMMN, *ip, imm);
13612 case 'O': /* sdbbp 4-bit code. */
13614 bfd_reloc_code_real_type r[3];
13618 if (my_getSmallExpression (&ep, r, s) > 0
13619 || !expr_const_in_range (&ep, 0, 16, 0))
13622 imm = ep.X_add_number;
13623 INSERT_OPERAND (1, IMMO, *ip, imm);
13630 bfd_reloc_code_real_type r[3];
13634 if (my_getSmallExpression (&ep, r, s) > 0
13635 || !expr_const_in_range (&ep, 0, 32, 2))
13638 imm = ep.X_add_number >> 2;
13639 INSERT_OPERAND (1, IMMP, *ip, imm);
13646 bfd_reloc_code_real_type r[3];
13650 if (my_getSmallExpression (&ep, r, s) > 0
13651 || !expr_const_in_range (&ep, -0x400000, 0x400000, 2))
13654 imm = ep.X_add_number >> 2;
13655 INSERT_OPERAND (1, IMMQ, *ip, imm);
13662 bfd_reloc_code_real_type r[3];
13666 /* Check whether there is only a single bracketed
13667 expression left. If so, it must be the base register
13668 and the constant must be zero. */
13669 if (*s == '(' && strchr (s + 1, '(') == 0)
13671 INSERT_OPERAND (1, IMMU, *ip, 0);
13675 if (my_getSmallExpression (&ep, r, s) > 0
13676 || !expr_const_in_range (&ep, 0, 32, 2))
13679 imm = ep.X_add_number >> 2;
13680 INSERT_OPERAND (1, IMMU, *ip, imm);
13687 bfd_reloc_code_real_type r[3];
13691 if (my_getSmallExpression (&ep, r, s) > 0
13692 || !expr_const_in_range (&ep, 0, 64, 2))
13695 imm = ep.X_add_number >> 2;
13696 INSERT_OPERAND (1, IMMW, *ip, imm);
13703 bfd_reloc_code_real_type r[3];
13707 if (my_getSmallExpression (&ep, r, s) > 0
13708 || !expr_const_in_range (&ep, -8, 8, 0))
13711 imm = ep.X_add_number;
13712 INSERT_OPERAND (1, IMMX, *ip, imm);
13719 bfd_reloc_code_real_type r[3];
13723 if (my_getSmallExpression (&ep, r, s) > 0
13724 || expr_const_in_range (&ep, -2, 2, 2)
13725 || !expr_const_in_range (&ep, -258, 258, 2))
13728 imm = ep.X_add_number >> 2;
13729 imm = ((imm >> 1) & ~0xff) | (imm & 0xff);
13730 INSERT_OPERAND (1, IMMY, *ip, imm);
13737 bfd_reloc_code_real_type r[3];
13740 if (my_getSmallExpression (&ep, r, s) > 0
13741 || !expr_const_in_range (&ep, 0, 1, 0))
13748 as_bad (_("Internal error: bad microMIPS opcode "
13749 "(unknown extension operand type `m%c'): %s %s"),
13750 *args, insn->name, insn->args);
13751 /* Further processing is fruitless. */
13756 case 'n': /* Register list for 32-bit lwm and swm. */
13757 gas_assert (mips_opts.micromips);
13759 /* A comma-separated list of registers and/or
13760 dash-separated contiguous ranges including
13761 at least one of ra and a set of one or more
13762 registers starting at s0 up to s7 and then
13763 s8 which have to be consecutive, e.g.:
13771 and any permutations of these. */
13772 unsigned int reglist;
13776 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
13779 if ((reglist & 0x3f00ffff) != 0)
13782 ra = (reglist >> 27) & 0x10;
13783 reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
13785 if ((reglist & -reglist) != reglist)
13788 imm = (ffs (reglist) - 1) | ra;
13789 INSERT_OPERAND (1, RT, *ip, imm);
13790 imm_expr.X_op = O_absent;
13794 case '|': /* 4-bit trap code. */
13795 gas_assert (mips_opts.micromips);
13796 my_getExpression (&imm_expr, s);
13797 check_absolute_expr (ip, &imm_expr);
13798 if ((unsigned long) imm_expr.X_add_number
13799 > MICROMIPSOP_MASK_TRAP)
13800 as_bad (_("Trap code (%lu) for %s not in 0..15 range"),
13801 (unsigned long) imm_expr.X_add_number,
13802 ip->insn_mo->name);
13803 INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number);
13804 imm_expr.X_op = O_absent;
13809 as_bad (_("Bad char = '%c'\n"), *args);
13814 /* Args don't match. */
13816 insn_error = _("Illegal operands");
13817 if (insn + 1 < past && !strcmp (insn->name, insn[1].name))
13822 else if (wrong_delay_slot_insns && need_delay_slot_ok)
13824 gas_assert (firstinsn);
13825 need_delay_slot_ok = FALSE;
13834 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
13836 /* This routine assembles an instruction into its binary format when
13837 assembling for the mips16. As a side effect, it sets one of the
13838 global variables imm_reloc or offset_reloc to the type of relocation
13839 to do if one of the operands is an address expression. It also sets
13840 forced_insn_length to the resulting instruction size in bytes if the
13841 user explicitly requested a small or extended instruction. */
13844 mips16_ip (char *str, struct mips_cl_insn *ip)
13848 struct mips_opcode *insn;
13850 unsigned int regno;
13851 unsigned int lastregno = 0;
13857 forced_insn_length = 0;
13859 for (s = str; ISLOWER (*s); ++s)
13871 if (s[1] == 't' && s[2] == ' ')
13874 forced_insn_length = 2;
13878 else if (s[1] == 'e' && s[2] == ' ')
13881 forced_insn_length = 4;
13885 /* Fall through. */
13887 insn_error = _("unknown opcode");
13891 if (mips_opts.noautoextend && !forced_insn_length)
13892 forced_insn_length = 2;
13894 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
13896 insn_error = _("unrecognized opcode");
13905 gas_assert (strcmp (insn->name, str) == 0);
13907 ok = is_opcode_valid_16 (insn);
13910 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
13911 && strcmp (insn->name, insn[1].name) == 0)
13920 static char buf[100];
13922 _("Opcode not supported on this processor: %s (%s)"),
13923 mips_cpu_info_from_arch (mips_opts.arch)->name,
13924 mips_cpu_info_from_isa (mips_opts.isa)->name);
13931 create_insn (ip, insn);
13932 imm_expr.X_op = O_absent;
13933 imm_reloc[0] = BFD_RELOC_UNUSED;
13934 imm_reloc[1] = BFD_RELOC_UNUSED;
13935 imm_reloc[2] = BFD_RELOC_UNUSED;
13936 imm2_expr.X_op = O_absent;
13937 offset_expr.X_op = O_absent;
13938 offset_reloc[0] = BFD_RELOC_UNUSED;
13939 offset_reloc[1] = BFD_RELOC_UNUSED;
13940 offset_reloc[2] = BFD_RELOC_UNUSED;
13941 for (args = insn->args; 1; ++args)
13948 /* In this switch statement we call break if we did not find
13949 a match, continue if we did find a match, or return if we
13960 /* Stuff the immediate value in now, if we can. */
13961 if (imm_expr.X_op == O_constant
13962 && *imm_reloc > BFD_RELOC_UNUSED
13963 && insn->pinfo != INSN_MACRO
13964 && calculate_reloc (*offset_reloc,
13965 imm_expr.X_add_number, &value))
13967 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
13968 *offset_reloc, value, forced_insn_length,
13970 imm_expr.X_op = O_absent;
13971 *imm_reloc = BFD_RELOC_UNUSED;
13972 *offset_reloc = BFD_RELOC_UNUSED;
13986 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13989 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
14005 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
14007 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
14011 /* Fall through. */
14022 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
14024 if (c == 'v' || c == 'w')
14027 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
14029 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
14040 if (c == 'v' || c == 'w')
14042 regno = mips16_to_32_reg_map[lastregno];
14056 regno = mips32_to_16_reg_map[regno];
14061 regno = ILLEGAL_REG;
14066 regno = ILLEGAL_REG;
14071 regno = ILLEGAL_REG;
14076 if (regno == AT && mips_opts.at)
14078 if (mips_opts.at == ATREG)
14079 as_warn (_("used $at without \".set noat\""));
14081 as_warn (_("used $%u with \".set at=$%u\""),
14082 regno, mips_opts.at);
14090 if (regno == ILLEGAL_REG)
14097 MIPS16_INSERT_OPERAND (RX, *ip, regno);
14101 MIPS16_INSERT_OPERAND (RY, *ip, regno);
14104 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
14107 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
14113 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
14116 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
14117 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
14127 if (strncmp (s, "$pc", 3) == 0)
14144 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
14147 if (imm_expr.X_op != O_constant)
14149 forced_insn_length = 4;
14150 ip->insn_opcode |= MIPS16_EXTEND;
14154 /* We need to relax this instruction. */
14155 *offset_reloc = *imm_reloc;
14156 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
14161 *imm_reloc = BFD_RELOC_UNUSED;
14162 /* Fall through. */
14169 my_getExpression (&imm_expr, s);
14170 if (imm_expr.X_op == O_register)
14172 /* What we thought was an expression turned out to
14175 if (s[0] == '(' && args[1] == '(')
14177 /* It looks like the expression was omitted
14178 before a register indirection, which means
14179 that the expression is implicitly zero. We
14180 still set up imm_expr, so that we handle
14181 explicit extensions correctly. */
14182 imm_expr.X_op = O_constant;
14183 imm_expr.X_add_number = 0;
14184 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
14191 /* We need to relax this instruction. */
14192 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
14201 /* We use offset_reloc rather than imm_reloc for the PC
14202 relative operands. This lets macros with both
14203 immediate and address operands work correctly. */
14204 my_getExpression (&offset_expr, s);
14206 if (offset_expr.X_op == O_register)
14209 /* We need to relax this instruction. */
14210 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
14214 case '6': /* break code */
14215 my_getExpression (&imm_expr, s);
14216 check_absolute_expr (ip, &imm_expr);
14217 if ((unsigned long) imm_expr.X_add_number > 63)
14218 as_warn (_("Invalid value for `%s' (%lu)"),
14220 (unsigned long) imm_expr.X_add_number);
14221 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
14222 imm_expr.X_op = O_absent;
14226 case 'a': /* 26 bit address */
14228 my_getExpression (&offset_expr, s);
14230 *offset_reloc = BFD_RELOC_MIPS16_JMP;
14231 ip->insn_opcode <<= 16;
14234 case 'l': /* register list for entry macro */
14235 case 'L': /* register list for exit macro */
14245 unsigned int freg, reg1, reg2;
14247 while (*s == ' ' || *s == ',')
14249 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
14251 else if (reg_lookup (&s, RTYPE_FPU, ®1))
14255 as_bad (_("can't parse register list"));
14265 if (!reg_lookup (&s, freg ? RTYPE_FPU
14266 : (RTYPE_GP | RTYPE_NUM), ®2))
14268 as_bad (_("invalid register list"));
14272 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
14274 mask &= ~ (7 << 3);
14277 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
14279 mask &= ~ (7 << 3);
14282 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
14283 mask |= (reg2 - 3) << 3;
14284 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
14285 mask |= (reg2 - 15) << 1;
14286 else if (reg1 == RA && reg2 == RA)
14290 as_bad (_("invalid register list"));
14294 /* The mask is filled in in the opcode table for the
14295 benefit of the disassembler. We remove it before
14296 applying the actual mask. */
14297 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
14298 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
14302 case 'm': /* Register list for save insn. */
14303 case 'M': /* Register list for restore insn. */
14305 int opcode = ip->insn_opcode;
14306 int framesz = 0, seen_framesz = 0;
14307 int nargs = 0, statics = 0, sregs = 0;
14311 unsigned int reg1, reg2;
14313 SKIP_SPACE_TABS (s);
14316 SKIP_SPACE_TABS (s);
14318 my_getExpression (&imm_expr, s);
14319 if (imm_expr.X_op == O_constant)
14321 /* Handle the frame size. */
14324 as_bad (_("more than one frame size in list"));
14328 framesz = imm_expr.X_add_number;
14329 imm_expr.X_op = O_absent;
14334 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
14336 as_bad (_("can't parse register list"));
14348 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2)
14351 as_bad (_("can't parse register list"));
14356 while (reg1 <= reg2)
14358 if (reg1 >= 4 && reg1 <= 7)
14362 nargs |= 1 << (reg1 - 4);
14364 /* statics $a0-$a3 */
14365 statics |= 1 << (reg1 - 4);
14367 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
14370 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
14372 else if (reg1 == 31)
14374 /* Add $ra to insn. */
14379 as_bad (_("unexpected register in list"));
14387 /* Encode args/statics combination. */
14388 if (nargs & statics)
14389 as_bad (_("arg/static registers overlap"));
14390 else if (nargs == 0xf)
14391 /* All $a0-$a3 are args. */
14392 opcode |= MIPS16_ALL_ARGS << 16;
14393 else if (statics == 0xf)
14394 /* All $a0-$a3 are statics. */
14395 opcode |= MIPS16_ALL_STATICS << 16;
14398 int narg = 0, nstat = 0;
14400 /* Count arg registers. */
14401 while (nargs & 0x1)
14407 as_bad (_("invalid arg register list"));
14409 /* Count static registers. */
14410 while (statics & 0x8)
14412 statics = (statics << 1) & 0xf;
14416 as_bad (_("invalid static register list"));
14418 /* Encode args/statics. */
14419 opcode |= ((narg << 2) | nstat) << 16;
14422 /* Encode $s0/$s1. */
14423 if (sregs & (1 << 0)) /* $s0 */
14425 if (sregs & (1 << 1)) /* $s1 */
14431 /* Count regs $s2-$s8. */
14439 as_bad (_("invalid static register list"));
14440 /* Encode $s2-$s8. */
14441 opcode |= nsreg << 24;
14444 /* Encode frame size. */
14446 as_bad (_("missing frame size"));
14447 else if ((framesz & 7) != 0 || framesz < 0
14448 || framesz > 0xff * 8)
14449 as_bad (_("invalid frame size"));
14450 else if (framesz != 128 || (opcode >> 16) != 0)
14453 opcode |= (((framesz & 0xf0) << 16)
14454 | (framesz & 0x0f));
14457 /* Finally build the instruction. */
14458 if ((opcode >> 16) != 0 || framesz == 0)
14459 opcode |= MIPS16_EXTEND;
14460 ip->insn_opcode = opcode;
14464 case 'e': /* extend code */
14465 my_getExpression (&imm_expr, s);
14466 check_absolute_expr (ip, &imm_expr);
14467 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
14469 as_warn (_("Invalid value for `%s' (%lu)"),
14471 (unsigned long) imm_expr.X_add_number);
14472 imm_expr.X_add_number &= 0x7ff;
14474 ip->insn_opcode |= imm_expr.X_add_number;
14475 imm_expr.X_op = O_absent;
14485 /* Args don't match. */
14486 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
14487 strcmp (insn->name, insn[1].name) == 0)
14494 insn_error = _("illegal operands");
14500 /* This structure holds information we know about a mips16 immediate
14503 struct mips16_immed_operand
14505 /* The type code used in the argument string in the opcode table. */
14507 /* The number of bits in the short form of the opcode. */
14509 /* The number of bits in the extended form of the opcode. */
14511 /* The amount by which the short form is shifted when it is used;
14512 for example, the sw instruction has a shift count of 2. */
14514 /* The amount by which the short form is shifted when it is stored
14515 into the instruction code. */
14517 /* Non-zero if the short form is unsigned. */
14519 /* Non-zero if the extended form is unsigned. */
14521 /* Non-zero if the value is PC relative. */
14525 /* The mips16 immediate operand types. */
14527 static const struct mips16_immed_operand mips16_immed_operands[] =
14529 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
14530 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
14531 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
14532 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
14533 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
14534 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
14535 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
14536 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
14537 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
14538 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
14539 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
14540 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
14541 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
14542 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
14543 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
14544 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
14545 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
14546 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
14547 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
14548 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
14549 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
14552 #define MIPS16_NUM_IMMED \
14553 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
14555 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14556 NBITS is the number of significant bits in VAL. */
14558 static unsigned long
14559 mips16_immed_extend (offsetT val, unsigned int nbits)
14564 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
14567 else if (nbits == 15)
14569 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
14574 extval = ((val & 0x1f) << 6) | (val & 0x20);
14577 return (extval << 16) | val;
14580 /* Install immediate value VAL into MIPS16 instruction *INSN,
14581 extending it if necessary. The instruction in *INSN may
14582 already be extended.
14584 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14585 if none. In the former case, VAL is a 16-bit number with no
14586 defined signedness.
14588 TYPE is the type of the immediate field. USER_INSN_LENGTH
14589 is the length that the user requested, or 0 if none. */
14592 mips16_immed (char *file, unsigned int line, int type,
14593 bfd_reloc_code_real_type reloc, offsetT val,
14594 unsigned int user_insn_length, unsigned long *insn)
14596 const struct mips16_immed_operand *op;
14597 int mintiny, maxtiny;
14599 op = mips16_immed_operands;
14600 while (op->type != type)
14603 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
14608 if (type == '<' || type == '>' || type == '[' || type == ']')
14611 maxtiny = 1 << op->nbits;
14616 maxtiny = (1 << op->nbits) - 1;
14618 if (reloc != BFD_RELOC_UNUSED)
14623 mintiny = - (1 << (op->nbits - 1));
14624 maxtiny = (1 << (op->nbits - 1)) - 1;
14625 if (reloc != BFD_RELOC_UNUSED)
14626 val = SEXT_16BIT (val);
14629 /* Branch offsets have an implicit 0 in the lowest bit. */
14630 if (type == 'p' || type == 'q')
14633 if ((val & ((1 << op->shift) - 1)) != 0
14634 || val < (mintiny << op->shift)
14635 || val > (maxtiny << op->shift))
14637 /* We need an extended instruction. */
14638 if (user_insn_length == 2)
14639 as_bad_where (file, line, _("invalid unextended operand value"));
14641 *insn |= MIPS16_EXTEND;
14643 else if (user_insn_length == 4)
14645 /* The operand doesn't force an unextended instruction to be extended.
14646 Warn if the user wanted an extended instruction anyway. */
14647 *insn |= MIPS16_EXTEND;
14648 as_warn_where (file, line,
14649 _("extended operand requested but not required"));
14652 if (mips16_opcode_length (*insn) == 2)
14656 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
14657 insnval <<= op->op_shift;
14662 long minext, maxext;
14664 if (reloc == BFD_RELOC_UNUSED)
14669 maxext = (1 << op->extbits) - 1;
14673 minext = - (1 << (op->extbits - 1));
14674 maxext = (1 << (op->extbits - 1)) - 1;
14676 if (val < minext || val > maxext)
14677 as_bad_where (file, line,
14678 _("operand value out of range for instruction"));
14681 *insn |= mips16_immed_extend (val, op->extbits);
14685 struct percent_op_match
14688 bfd_reloc_code_real_type reloc;
14691 static const struct percent_op_match mips_percent_op[] =
14693 {"%lo", BFD_RELOC_LO16},
14694 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
14695 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
14696 {"%call16", BFD_RELOC_MIPS_CALL16},
14697 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
14698 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
14699 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
14700 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
14701 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
14702 {"%got", BFD_RELOC_MIPS_GOT16},
14703 {"%gp_rel", BFD_RELOC_GPREL16},
14704 {"%half", BFD_RELOC_16},
14705 {"%highest", BFD_RELOC_MIPS_HIGHEST},
14706 {"%higher", BFD_RELOC_MIPS_HIGHER},
14707 {"%neg", BFD_RELOC_MIPS_SUB},
14708 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
14709 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
14710 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
14711 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
14712 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
14713 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
14714 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
14715 {"%hi", BFD_RELOC_HI16_S}
14718 static const struct percent_op_match mips16_percent_op[] =
14720 {"%lo", BFD_RELOC_MIPS16_LO16},
14721 {"%gprel", BFD_RELOC_MIPS16_GPREL},
14722 {"%got", BFD_RELOC_MIPS16_GOT16},
14723 {"%call16", BFD_RELOC_MIPS16_CALL16},
14724 {"%hi", BFD_RELOC_MIPS16_HI16_S},
14725 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
14726 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
14727 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
14728 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
14729 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
14730 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
14731 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
14735 /* Return true if *STR points to a relocation operator. When returning true,
14736 move *STR over the operator and store its relocation code in *RELOC.
14737 Leave both *STR and *RELOC alone when returning false. */
14740 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
14742 const struct percent_op_match *percent_op;
14745 if (mips_opts.mips16)
14747 percent_op = mips16_percent_op;
14748 limit = ARRAY_SIZE (mips16_percent_op);
14752 percent_op = mips_percent_op;
14753 limit = ARRAY_SIZE (mips_percent_op);
14756 for (i = 0; i < limit; i++)
14757 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
14759 int len = strlen (percent_op[i].str);
14761 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
14764 *str += strlen (percent_op[i].str);
14765 *reloc = percent_op[i].reloc;
14767 /* Check whether the output BFD supports this relocation.
14768 If not, issue an error and fall back on something safe. */
14769 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
14771 as_bad (_("relocation %s isn't supported by the current ABI"),
14772 percent_op[i].str);
14773 *reloc = BFD_RELOC_UNUSED;
14781 /* Parse string STR as a 16-bit relocatable operand. Store the
14782 expression in *EP and the relocations in the array starting
14783 at RELOC. Return the number of relocation operators used.
14785 On exit, EXPR_END points to the first character after the expression. */
14788 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
14791 bfd_reloc_code_real_type reversed_reloc[3];
14792 size_t reloc_index, i;
14793 int crux_depth, str_depth;
14796 /* Search for the start of the main expression, recoding relocations
14797 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14798 of the main expression and with CRUX_DEPTH containing the number
14799 of open brackets at that point. */
14806 crux_depth = str_depth;
14808 /* Skip over whitespace and brackets, keeping count of the number
14810 while (*str == ' ' || *str == '\t' || *str == '(')
14815 && reloc_index < (HAVE_NEWABI ? 3 : 1)
14816 && parse_relocation (&str, &reversed_reloc[reloc_index]));
14818 my_getExpression (ep, crux);
14821 /* Match every open bracket. */
14822 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
14826 if (crux_depth > 0)
14827 as_bad (_("unclosed '('"));
14831 if (reloc_index != 0)
14833 prev_reloc_op_frag = frag_now;
14834 for (i = 0; i < reloc_index; i++)
14835 reloc[i] = reversed_reloc[reloc_index - 1 - i];
14838 return reloc_index;
14842 my_getExpression (expressionS *ep, char *str)
14846 save_in = input_line_pointer;
14847 input_line_pointer = str;
14849 expr_end = input_line_pointer;
14850 input_line_pointer = save_in;
14854 md_atof (int type, char *litP, int *sizeP)
14856 return ieee_md_atof (type, litP, sizeP, target_big_endian);
14860 md_number_to_chars (char *buf, valueT val, int n)
14862 if (target_big_endian)
14863 number_to_chars_bigendian (buf, val, n);
14865 number_to_chars_littleendian (buf, val, n);
14868 static int support_64bit_objects(void)
14870 const char **list, **l;
14873 list = bfd_target_list ();
14874 for (l = list; *l != NULL; l++)
14875 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
14876 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
14878 yes = (*l != NULL);
14883 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14884 NEW_VALUE. Warn if another value was already specified. Note:
14885 we have to defer parsing the -march and -mtune arguments in order
14886 to handle 'from-abi' correctly, since the ABI might be specified
14887 in a later argument. */
14890 mips_set_option_string (const char **string_ptr, const char *new_value)
14892 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
14893 as_warn (_("A different %s was already specified, is now %s"),
14894 string_ptr == &mips_arch_string ? "-march" : "-mtune",
14897 *string_ptr = new_value;
14901 md_parse_option (int c, char *arg)
14905 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
14906 if (c == mips_ases[i].option_on || c == mips_ases[i].option_off)
14908 file_ase_explicit |= mips_set_ase (&mips_ases[i],
14909 c == mips_ases[i].option_on);
14915 case OPTION_CONSTRUCT_FLOATS:
14916 mips_disable_float_construction = 0;
14919 case OPTION_NO_CONSTRUCT_FLOATS:
14920 mips_disable_float_construction = 1;
14932 target_big_endian = 1;
14936 target_big_endian = 0;
14942 else if (arg[0] == '0')
14944 else if (arg[0] == '1')
14954 mips_debug = atoi (arg);
14958 file_mips_isa = ISA_MIPS1;
14962 file_mips_isa = ISA_MIPS2;
14966 file_mips_isa = ISA_MIPS3;
14970 file_mips_isa = ISA_MIPS4;
14974 file_mips_isa = ISA_MIPS5;
14977 case OPTION_MIPS32:
14978 file_mips_isa = ISA_MIPS32;
14981 case OPTION_MIPS32R2:
14982 file_mips_isa = ISA_MIPS32R2;
14985 case OPTION_MIPS64R2:
14986 file_mips_isa = ISA_MIPS64R2;
14989 case OPTION_MIPS64:
14990 file_mips_isa = ISA_MIPS64;
14994 mips_set_option_string (&mips_tune_string, arg);
14998 mips_set_option_string (&mips_arch_string, arg);
15002 mips_set_option_string (&mips_arch_string, "4650");
15003 mips_set_option_string (&mips_tune_string, "4650");
15006 case OPTION_NO_M4650:
15010 mips_set_option_string (&mips_arch_string, "4010");
15011 mips_set_option_string (&mips_tune_string, "4010");
15014 case OPTION_NO_M4010:
15018 mips_set_option_string (&mips_arch_string, "4100");
15019 mips_set_option_string (&mips_tune_string, "4100");
15022 case OPTION_NO_M4100:
15026 mips_set_option_string (&mips_arch_string, "3900");
15027 mips_set_option_string (&mips_tune_string, "3900");
15030 case OPTION_NO_M3900:
15033 case OPTION_MICROMIPS:
15034 if (mips_opts.mips16 == 1)
15036 as_bad (_("-mmicromips cannot be used with -mips16"));
15039 mips_opts.micromips = 1;
15040 mips_no_prev_insn ();
15043 case OPTION_NO_MICROMIPS:
15044 mips_opts.micromips = 0;
15045 mips_no_prev_insn ();
15048 case OPTION_MIPS16:
15049 if (mips_opts.micromips == 1)
15051 as_bad (_("-mips16 cannot be used with -micromips"));
15054 mips_opts.mips16 = 1;
15055 mips_no_prev_insn ();
15058 case OPTION_NO_MIPS16:
15059 mips_opts.mips16 = 0;
15060 mips_no_prev_insn ();
15063 case OPTION_FIX_24K:
15067 case OPTION_NO_FIX_24K:
15071 case OPTION_FIX_LOONGSON2F_JUMP:
15072 mips_fix_loongson2f_jump = TRUE;
15075 case OPTION_NO_FIX_LOONGSON2F_JUMP:
15076 mips_fix_loongson2f_jump = FALSE;
15079 case OPTION_FIX_LOONGSON2F_NOP:
15080 mips_fix_loongson2f_nop = TRUE;
15083 case OPTION_NO_FIX_LOONGSON2F_NOP:
15084 mips_fix_loongson2f_nop = FALSE;
15087 case OPTION_FIX_VR4120:
15088 mips_fix_vr4120 = 1;
15091 case OPTION_NO_FIX_VR4120:
15092 mips_fix_vr4120 = 0;
15095 case OPTION_FIX_VR4130:
15096 mips_fix_vr4130 = 1;
15099 case OPTION_NO_FIX_VR4130:
15100 mips_fix_vr4130 = 0;
15103 case OPTION_FIX_CN63XXP1:
15104 mips_fix_cn63xxp1 = TRUE;
15107 case OPTION_NO_FIX_CN63XXP1:
15108 mips_fix_cn63xxp1 = FALSE;
15111 case OPTION_RELAX_BRANCH:
15112 mips_relax_branch = 1;
15115 case OPTION_NO_RELAX_BRANCH:
15116 mips_relax_branch = 0;
15119 case OPTION_INSN32:
15120 mips_opts.insn32 = TRUE;
15123 case OPTION_NO_INSN32:
15124 mips_opts.insn32 = FALSE;
15127 case OPTION_MSHARED:
15128 mips_in_shared = TRUE;
15131 case OPTION_MNO_SHARED:
15132 mips_in_shared = FALSE;
15135 case OPTION_MSYM32:
15136 mips_opts.sym32 = TRUE;
15139 case OPTION_MNO_SYM32:
15140 mips_opts.sym32 = FALSE;
15143 /* When generating ELF code, we permit -KPIC and -call_shared to
15144 select SVR4_PIC, and -non_shared to select no PIC. This is
15145 intended to be compatible with Irix 5. */
15146 case OPTION_CALL_SHARED:
15147 mips_pic = SVR4_PIC;
15148 mips_abicalls = TRUE;
15151 case OPTION_CALL_NONPIC:
15153 mips_abicalls = TRUE;
15156 case OPTION_NON_SHARED:
15158 mips_abicalls = FALSE;
15161 /* The -xgot option tells the assembler to use 32 bit offsets
15162 when accessing the got in SVR4_PIC mode. It is for Irix
15169 g_switch_value = atoi (arg);
15173 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
15176 mips_abi = O32_ABI;
15180 mips_abi = N32_ABI;
15184 mips_abi = N64_ABI;
15185 if (!support_64bit_objects())
15186 as_fatal (_("No compiled in support for 64 bit object file format"));
15190 file_mips_gp32 = 1;
15194 file_mips_gp32 = 0;
15198 file_mips_fp32 = 1;
15202 file_mips_fp32 = 0;
15205 case OPTION_SINGLE_FLOAT:
15206 file_mips_single_float = 1;
15209 case OPTION_DOUBLE_FLOAT:
15210 file_mips_single_float = 0;
15213 case OPTION_SOFT_FLOAT:
15214 file_mips_soft_float = 1;
15217 case OPTION_HARD_FLOAT:
15218 file_mips_soft_float = 0;
15222 if (strcmp (arg, "32") == 0)
15223 mips_abi = O32_ABI;
15224 else if (strcmp (arg, "o64") == 0)
15225 mips_abi = O64_ABI;
15226 else if (strcmp (arg, "n32") == 0)
15227 mips_abi = N32_ABI;
15228 else if (strcmp (arg, "64") == 0)
15230 mips_abi = N64_ABI;
15231 if (! support_64bit_objects())
15232 as_fatal (_("No compiled in support for 64 bit object file "
15235 else if (strcmp (arg, "eabi") == 0)
15236 mips_abi = EABI_ABI;
15239 as_fatal (_("invalid abi -mabi=%s"), arg);
15244 case OPTION_M7000_HILO_FIX:
15245 mips_7000_hilo_fix = TRUE;
15248 case OPTION_MNO_7000_HILO_FIX:
15249 mips_7000_hilo_fix = FALSE;
15252 case OPTION_MDEBUG:
15253 mips_flag_mdebug = TRUE;
15256 case OPTION_NO_MDEBUG:
15257 mips_flag_mdebug = FALSE;
15261 mips_flag_pdr = TRUE;
15264 case OPTION_NO_PDR:
15265 mips_flag_pdr = FALSE;
15268 case OPTION_MVXWORKS_PIC:
15269 mips_pic = VXWORKS_PIC;
15273 if (strcmp (arg, "2008") == 0)
15274 mips_flag_nan2008 = TRUE;
15275 else if (strcmp (arg, "legacy") == 0)
15276 mips_flag_nan2008 = FALSE;
15279 as_fatal (_("Invalid NaN setting -mnan=%s"), arg);
15288 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
15293 /* Set up globals to generate code for the ISA or processor
15294 described by INFO. */
15297 mips_set_architecture (const struct mips_cpu_info *info)
15301 file_mips_arch = info->cpu;
15302 mips_opts.arch = info->cpu;
15303 mips_opts.isa = info->isa;
15308 /* Likewise for tuning. */
15311 mips_set_tune (const struct mips_cpu_info *info)
15314 mips_tune = info->cpu;
15319 mips_after_parse_args (void)
15321 const struct mips_cpu_info *arch_info = 0;
15322 const struct mips_cpu_info *tune_info = 0;
15324 /* GP relative stuff not working for PE */
15325 if (strncmp (TARGET_OS, "pe", 2) == 0)
15327 if (g_switch_seen && g_switch_value != 0)
15328 as_bad (_("-G not supported in this configuration."));
15329 g_switch_value = 0;
15332 if (mips_abi == NO_ABI)
15333 mips_abi = MIPS_DEFAULT_ABI;
15335 /* The following code determines the architecture and register size.
15336 Similar code was added to GCC 3.3 (see override_options() in
15337 config/mips/mips.c). The GAS and GCC code should be kept in sync
15338 as much as possible. */
15340 if (mips_arch_string != 0)
15341 arch_info = mips_parse_cpu ("-march", mips_arch_string);
15343 if (file_mips_isa != ISA_UNKNOWN)
15345 /* Handle -mipsN. At this point, file_mips_isa contains the
15346 ISA level specified by -mipsN, while arch_info->isa contains
15347 the -march selection (if any). */
15348 if (arch_info != 0)
15350 /* -march takes precedence over -mipsN, since it is more descriptive.
15351 There's no harm in specifying both as long as the ISA levels
15353 if (file_mips_isa != arch_info->isa)
15354 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
15355 mips_cpu_info_from_isa (file_mips_isa)->name,
15356 mips_cpu_info_from_isa (arch_info->isa)->name);
15359 arch_info = mips_cpu_info_from_isa (file_mips_isa);
15362 if (arch_info == 0)
15364 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
15365 gas_assert (arch_info);
15368 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
15369 as_bad (_("-march=%s is not compatible with the selected ABI"),
15372 mips_set_architecture (arch_info);
15374 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
15375 if (mips_tune_string != 0)
15376 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
15378 if (tune_info == 0)
15379 mips_set_tune (arch_info);
15381 mips_set_tune (tune_info);
15383 if (file_mips_gp32 >= 0)
15385 /* The user specified the size of the integer registers. Make sure
15386 it agrees with the ABI and ISA. */
15387 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
15388 as_bad (_("-mgp64 used with a 32-bit processor"));
15389 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
15390 as_bad (_("-mgp32 used with a 64-bit ABI"));
15391 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
15392 as_bad (_("-mgp64 used with a 32-bit ABI"));
15396 /* Infer the integer register size from the ABI and processor.
15397 Restrict ourselves to 32-bit registers if that's all the
15398 processor has, or if the ABI cannot handle 64-bit registers. */
15399 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
15400 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
15403 switch (file_mips_fp32)
15407 /* No user specified float register size.
15408 ??? GAS treats single-float processors as though they had 64-bit
15409 float registers (although it complains when double-precision
15410 instructions are used). As things stand, saying they have 32-bit
15411 registers would lead to spurious "register must be even" messages.
15412 So here we assume float registers are never smaller than the
15414 if (file_mips_gp32 == 0)
15415 /* 64-bit integer registers implies 64-bit float registers. */
15416 file_mips_fp32 = 0;
15417 else if ((mips_opts.ase & FP64_ASES)
15418 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
15419 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
15420 file_mips_fp32 = 0;
15422 /* 32-bit float registers. */
15423 file_mips_fp32 = 1;
15426 /* The user specified the size of the float registers. Check if it
15427 agrees with the ABI and ISA. */
15429 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
15430 as_bad (_("-mfp64 used with a 32-bit fpu"));
15431 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
15432 && !ISA_HAS_MXHC1 (mips_opts.isa))
15433 as_warn (_("-mfp64 used with a 32-bit ABI"));
15436 if (ABI_NEEDS_64BIT_REGS (mips_abi))
15437 as_warn (_("-mfp32 used with a 64-bit ABI"));
15441 /* End of GCC-shared inference code. */
15443 /* This flag is set when we have a 64-bit capable CPU but use only
15444 32-bit wide registers. Note that EABI does not use it. */
15445 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
15446 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
15447 || mips_abi == O32_ABI))
15448 mips_32bitmode = 1;
15450 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
15451 as_bad (_("trap exception not supported at ISA 1"));
15453 /* If the selected architecture includes support for ASEs, enable
15454 generation of code for them. */
15455 if (mips_opts.mips16 == -1)
15456 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
15457 if (mips_opts.micromips == -1)
15458 mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0;
15460 /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those
15461 ASEs from being selected implicitly. */
15462 if (file_mips_fp32 == 1)
15463 file_ase_explicit |= ASE_MIPS3D | ASE_MDMX;
15465 /* If the user didn't explicitly select or deselect a particular ASE,
15466 use the default setting for the CPU. */
15467 mips_opts.ase |= (arch_info->ase & ~file_ase_explicit);
15469 file_mips_isa = mips_opts.isa;
15470 file_ase = mips_opts.ase;
15471 mips_opts.gp32 = file_mips_gp32;
15472 mips_opts.fp32 = file_mips_fp32;
15473 mips_opts.soft_float = file_mips_soft_float;
15474 mips_opts.single_float = file_mips_single_float;
15476 mips_check_isa_supports_ases ();
15478 if (mips_flag_mdebug < 0)
15479 mips_flag_mdebug = 0;
15483 mips_init_after_args (void)
15485 /* initialize opcodes */
15486 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
15487 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
15491 md_pcrel_from (fixS *fixP)
15493 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
15494 switch (fixP->fx_r_type)
15496 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15497 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15498 /* Return the address of the delay slot. */
15501 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15502 case BFD_RELOC_MICROMIPS_JMP:
15503 case BFD_RELOC_16_PCREL_S2:
15504 case BFD_RELOC_MIPS_JMP:
15505 /* Return the address of the delay slot. */
15508 case BFD_RELOC_32_PCREL:
15512 /* We have no relocation type for PC relative MIPS16 instructions. */
15513 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
15514 as_bad_where (fixP->fx_file, fixP->fx_line,
15515 _("PC relative MIPS16 instruction references a different section"));
15520 /* This is called before the symbol table is processed. In order to
15521 work with gcc when using mips-tfile, we must keep all local labels.
15522 However, in other cases, we want to discard them. If we were
15523 called with -g, but we didn't see any debugging information, it may
15524 mean that gcc is smuggling debugging information through to
15525 mips-tfile, in which case we must generate all local labels. */
15528 mips_frob_file_before_adjust (void)
15530 #ifndef NO_ECOFF_DEBUGGING
15531 if (ECOFF_DEBUGGING
15533 && ! ecoff_debugging_seen)
15534 flag_keep_locals = 1;
15538 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15539 the corresponding LO16 reloc. This is called before md_apply_fix and
15540 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15541 relocation operators.
15543 For our purposes, a %lo() expression matches a %got() or %hi()
15546 (a) it refers to the same symbol; and
15547 (b) the offset applied in the %lo() expression is no lower than
15548 the offset applied in the %got() or %hi().
15550 (b) allows us to cope with code like:
15553 lh $4,%lo(foo+2)($4)
15555 ...which is legal on RELA targets, and has a well-defined behaviour
15556 if the user knows that adding 2 to "foo" will not induce a carry to
15559 When several %lo()s match a particular %got() or %hi(), we use the
15560 following rules to distinguish them:
15562 (1) %lo()s with smaller offsets are a better match than %lo()s with
15565 (2) %lo()s with no matching %got() or %hi() are better than those
15566 that already have a matching %got() or %hi().
15568 (3) later %lo()s are better than earlier %lo()s.
15570 These rules are applied in order.
15572 (1) means, among other things, that %lo()s with identical offsets are
15573 chosen if they exist.
15575 (2) means that we won't associate several high-part relocations with
15576 the same low-part relocation unless there's no alternative. Having
15577 several high parts for the same low part is a GNU extension; this rule
15578 allows careful users to avoid it.
15580 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15581 with the last high-part relocation being at the front of the list.
15582 It therefore makes sense to choose the last matching low-part
15583 relocation, all other things being equal. It's also easier
15584 to code that way. */
15587 mips_frob_file (void)
15589 struct mips_hi_fixup *l;
15590 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
15592 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
15594 segment_info_type *seginfo;
15595 bfd_boolean matched_lo_p;
15596 fixS **hi_pos, **lo_pos, **pos;
15598 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
15600 /* If a GOT16 relocation turns out to be against a global symbol,
15601 there isn't supposed to be a matching LO. Ignore %gots against
15602 constants; we'll report an error for those later. */
15603 if (got16_reloc_p (l->fixp->fx_r_type)
15604 && !(l->fixp->fx_addsy
15605 && pic_need_relax (l->fixp->fx_addsy, l->seg)))
15608 /* Check quickly whether the next fixup happens to be a matching %lo. */
15609 if (fixup_has_matching_lo_p (l->fixp))
15612 seginfo = seg_info (l->seg);
15614 /* Set HI_POS to the position of this relocation in the chain.
15615 Set LO_POS to the position of the chosen low-part relocation.
15616 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15617 relocation that matches an immediately-preceding high-part
15621 matched_lo_p = FALSE;
15622 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
15624 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
15626 if (*pos == l->fixp)
15629 if ((*pos)->fx_r_type == looking_for_rtype
15630 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
15631 && (*pos)->fx_offset >= l->fixp->fx_offset
15633 || (*pos)->fx_offset < (*lo_pos)->fx_offset
15635 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
15638 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
15639 && fixup_has_matching_lo_p (*pos));
15642 /* If we found a match, remove the high-part relocation from its
15643 current position and insert it before the low-part relocation.
15644 Make the offsets match so that fixup_has_matching_lo_p()
15647 We don't warn about unmatched high-part relocations since some
15648 versions of gcc have been known to emit dead "lui ...%hi(...)"
15650 if (lo_pos != NULL)
15652 l->fixp->fx_offset = (*lo_pos)->fx_offset;
15653 if (l->fixp->fx_next != *lo_pos)
15655 *hi_pos = l->fixp->fx_next;
15656 l->fixp->fx_next = *lo_pos;
15664 mips_force_relocation (fixS *fixp)
15666 if (generic_force_reloc (fixp))
15669 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15670 so that the linker relaxation can update targets. */
15671 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15672 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15673 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
15679 /* Read the instruction associated with RELOC from BUF. */
15681 static unsigned int
15682 read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc)
15684 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
15685 return read_compressed_insn (buf, 4);
15687 return read_insn (buf);
15690 /* Write instruction INSN to BUF, given that it has been relocated
15694 write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc,
15695 unsigned long insn)
15697 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
15698 write_compressed_insn (buf, insn, 4);
15700 write_insn (buf, insn);
15703 /* Apply a fixup to the object file. */
15706 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
15709 unsigned long insn;
15710 reloc_howto_type *howto;
15712 /* We ignore generic BFD relocations we don't know about. */
15713 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
15717 gas_assert (fixP->fx_size == 2
15718 || fixP->fx_size == 4
15719 || fixP->fx_r_type == BFD_RELOC_16
15720 || fixP->fx_r_type == BFD_RELOC_64
15721 || fixP->fx_r_type == BFD_RELOC_CTOR
15722 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
15723 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
15724 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
15725 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
15726 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
15728 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15730 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
15731 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15732 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15733 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
15734 || fixP->fx_r_type == BFD_RELOC_32_PCREL);
15736 /* Don't treat parts of a composite relocation as done. There are two
15739 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15740 should nevertheless be emitted if the first part is.
15742 (2) In normal usage, composite relocations are never assembly-time
15743 constants. The easiest way of dealing with the pathological
15744 exceptions is to generate a relocation against STN_UNDEF and
15745 leave everything up to the linker. */
15746 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
15749 switch (fixP->fx_r_type)
15751 case BFD_RELOC_MIPS_TLS_GD:
15752 case BFD_RELOC_MIPS_TLS_LDM:
15753 case BFD_RELOC_MIPS_TLS_DTPREL32:
15754 case BFD_RELOC_MIPS_TLS_DTPREL64:
15755 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
15756 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
15757 case BFD_RELOC_MIPS_TLS_GOTTPREL:
15758 case BFD_RELOC_MIPS_TLS_TPREL32:
15759 case BFD_RELOC_MIPS_TLS_TPREL64:
15760 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
15761 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
15762 case BFD_RELOC_MICROMIPS_TLS_GD:
15763 case BFD_RELOC_MICROMIPS_TLS_LDM:
15764 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
15765 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
15766 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
15767 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
15768 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
15769 case BFD_RELOC_MIPS16_TLS_GD:
15770 case BFD_RELOC_MIPS16_TLS_LDM:
15771 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
15772 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
15773 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
15774 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
15775 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
15776 if (!fixP->fx_addsy)
15778 as_bad_where (fixP->fx_file, fixP->fx_line,
15779 _("TLS relocation against a constant"));
15782 S_SET_THREAD_LOCAL (fixP->fx_addsy);
15785 case BFD_RELOC_MIPS_JMP:
15786 case BFD_RELOC_MIPS_SHIFT5:
15787 case BFD_RELOC_MIPS_SHIFT6:
15788 case BFD_RELOC_MIPS_GOT_DISP:
15789 case BFD_RELOC_MIPS_GOT_PAGE:
15790 case BFD_RELOC_MIPS_GOT_OFST:
15791 case BFD_RELOC_MIPS_SUB:
15792 case BFD_RELOC_MIPS_INSERT_A:
15793 case BFD_RELOC_MIPS_INSERT_B:
15794 case BFD_RELOC_MIPS_DELETE:
15795 case BFD_RELOC_MIPS_HIGHEST:
15796 case BFD_RELOC_MIPS_HIGHER:
15797 case BFD_RELOC_MIPS_SCN_DISP:
15798 case BFD_RELOC_MIPS_REL16:
15799 case BFD_RELOC_MIPS_RELGOT:
15800 case BFD_RELOC_MIPS_JALR:
15801 case BFD_RELOC_HI16:
15802 case BFD_RELOC_HI16_S:
15803 case BFD_RELOC_LO16:
15804 case BFD_RELOC_GPREL16:
15805 case BFD_RELOC_MIPS_LITERAL:
15806 case BFD_RELOC_MIPS_CALL16:
15807 case BFD_RELOC_MIPS_GOT16:
15808 case BFD_RELOC_GPREL32:
15809 case BFD_RELOC_MIPS_GOT_HI16:
15810 case BFD_RELOC_MIPS_GOT_LO16:
15811 case BFD_RELOC_MIPS_CALL_HI16:
15812 case BFD_RELOC_MIPS_CALL_LO16:
15813 case BFD_RELOC_MIPS16_GPREL:
15814 case BFD_RELOC_MIPS16_GOT16:
15815 case BFD_RELOC_MIPS16_CALL16:
15816 case BFD_RELOC_MIPS16_HI16:
15817 case BFD_RELOC_MIPS16_HI16_S:
15818 case BFD_RELOC_MIPS16_LO16:
15819 case BFD_RELOC_MIPS16_JMP:
15820 case BFD_RELOC_MICROMIPS_JMP:
15821 case BFD_RELOC_MICROMIPS_GOT_DISP:
15822 case BFD_RELOC_MICROMIPS_GOT_PAGE:
15823 case BFD_RELOC_MICROMIPS_GOT_OFST:
15824 case BFD_RELOC_MICROMIPS_SUB:
15825 case BFD_RELOC_MICROMIPS_HIGHEST:
15826 case BFD_RELOC_MICROMIPS_HIGHER:
15827 case BFD_RELOC_MICROMIPS_SCN_DISP:
15828 case BFD_RELOC_MICROMIPS_JALR:
15829 case BFD_RELOC_MICROMIPS_HI16:
15830 case BFD_RELOC_MICROMIPS_HI16_S:
15831 case BFD_RELOC_MICROMIPS_LO16:
15832 case BFD_RELOC_MICROMIPS_GPREL16:
15833 case BFD_RELOC_MICROMIPS_LITERAL:
15834 case BFD_RELOC_MICROMIPS_CALL16:
15835 case BFD_RELOC_MICROMIPS_GOT16:
15836 case BFD_RELOC_MICROMIPS_GOT_HI16:
15837 case BFD_RELOC_MICROMIPS_GOT_LO16:
15838 case BFD_RELOC_MICROMIPS_CALL_HI16:
15839 case BFD_RELOC_MICROMIPS_CALL_LO16:
15840 case BFD_RELOC_MIPS_EH:
15845 if (calculate_reloc (fixP->fx_r_type, *valP, &value))
15847 insn = read_reloc_insn (buf, fixP->fx_r_type);
15848 if (mips16_reloc_p (fixP->fx_r_type))
15849 insn |= mips16_immed_extend (value, 16);
15851 insn |= (value & 0xffff);
15852 write_reloc_insn (buf, fixP->fx_r_type, insn);
15855 as_bad_where (fixP->fx_file, fixP->fx_line,
15856 _("Unsupported constant in relocation"));
15861 /* This is handled like BFD_RELOC_32, but we output a sign
15862 extended value if we are only 32 bits. */
15865 if (8 <= sizeof (valueT))
15866 md_number_to_chars (buf, *valP, 8);
15871 if ((*valP & 0x80000000) != 0)
15875 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4);
15876 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4);
15881 case BFD_RELOC_RVA:
15883 case BFD_RELOC_32_PCREL:
15885 /* If we are deleting this reloc entry, we must fill in the
15886 value now. This can happen if we have a .word which is not
15887 resolved when it appears but is later defined. */
15889 md_number_to_chars (buf, *valP, fixP->fx_size);
15892 case BFD_RELOC_16_PCREL_S2:
15893 if ((*valP & 0x3) != 0)
15894 as_bad_where (fixP->fx_file, fixP->fx_line,
15895 _("Branch to misaligned address (%lx)"), (long) *valP);
15897 /* We need to save the bits in the instruction since fixup_segment()
15898 might be deleting the relocation entry (i.e., a branch within
15899 the current segment). */
15900 if (! fixP->fx_done)
15903 /* Update old instruction data. */
15904 insn = read_insn (buf);
15906 if (*valP + 0x20000 <= 0x3ffff)
15908 insn |= (*valP >> 2) & 0xffff;
15909 write_insn (buf, insn);
15911 else if (mips_pic == NO_PIC
15913 && fixP->fx_frag->fr_address >= text_section->vma
15914 && (fixP->fx_frag->fr_address
15915 < text_section->vma + bfd_get_section_size (text_section))
15916 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
15917 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
15918 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
15920 /* The branch offset is too large. If this is an
15921 unconditional branch, and we are not generating PIC code,
15922 we can convert it to an absolute jump instruction. */
15923 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
15924 insn = 0x0c000000; /* jal */
15926 insn = 0x08000000; /* j */
15927 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
15929 fixP->fx_addsy = section_symbol (text_section);
15930 *valP += md_pcrel_from (fixP);
15931 write_insn (buf, insn);
15935 /* If we got here, we have branch-relaxation disabled,
15936 and there's nothing we can do to fix this instruction
15937 without turning it into a longer sequence. */
15938 as_bad_where (fixP->fx_file, fixP->fx_line,
15939 _("Branch out of range"));
15943 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15944 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15945 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15946 /* We adjust the offset back to even. */
15947 if ((*valP & 0x1) != 0)
15950 if (! fixP->fx_done)
15953 /* Should never visit here, because we keep the relocation. */
15957 case BFD_RELOC_VTABLE_INHERIT:
15960 && !S_IS_DEFINED (fixP->fx_addsy)
15961 && !S_IS_WEAK (fixP->fx_addsy))
15962 S_SET_WEAK (fixP->fx_addsy);
15965 case BFD_RELOC_VTABLE_ENTRY:
15973 /* Remember value for tc_gen_reloc. */
15974 fixP->fx_addnumber = *valP;
15984 name = input_line_pointer;
15985 c = get_symbol_end ();
15986 p = (symbolS *) symbol_find_or_make (name);
15987 *input_line_pointer = c;
15991 /* Align the current frag to a given power of two. If a particular
15992 fill byte should be used, FILL points to an integer that contains
15993 that byte, otherwise FILL is null.
15995 This function used to have the comment:
15997 The MIPS assembler also automatically adjusts any preceding label.
15999 The implementation therefore applied the adjustment to a maximum of
16000 one label. However, other label adjustments are applied to batches
16001 of labels, and adjusting just one caused problems when new labels
16002 were added for the sake of debugging or unwind information.
16003 We therefore adjust all preceding labels (given as LABELS) instead. */
16006 mips_align (int to, int *fill, struct insn_label_list *labels)
16008 mips_emit_delays ();
16009 mips_record_compressed_mode ();
16010 if (fill == NULL && subseg_text_p (now_seg))
16011 frag_align_code (to, 0);
16013 frag_align (to, fill ? *fill : 0, 0);
16014 record_alignment (now_seg, to);
16015 mips_move_labels (labels, FALSE);
16018 /* Align to a given power of two. .align 0 turns off the automatic
16019 alignment used by the data creating pseudo-ops. */
16022 s_align (int x ATTRIBUTE_UNUSED)
16024 int temp, fill_value, *fill_ptr;
16025 long max_alignment = 28;
16027 /* o Note that the assembler pulls down any immediately preceding label
16028 to the aligned address.
16029 o It's not documented but auto alignment is reinstated by
16030 a .align pseudo instruction.
16031 o Note also that after auto alignment is turned off the mips assembler
16032 issues an error on attempt to assemble an improperly aligned data item.
16035 temp = get_absolute_expression ();
16036 if (temp > max_alignment)
16037 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
16040 as_warn (_("Alignment negative: 0 assumed."));
16043 if (*input_line_pointer == ',')
16045 ++input_line_pointer;
16046 fill_value = get_absolute_expression ();
16047 fill_ptr = &fill_value;
16053 segment_info_type *si = seg_info (now_seg);
16054 struct insn_label_list *l = si->label_list;
16055 /* Auto alignment should be switched on by next section change. */
16057 mips_align (temp, fill_ptr, l);
16064 demand_empty_rest_of_line ();
16068 s_change_sec (int sec)
16072 /* The ELF backend needs to know that we are changing sections, so
16073 that .previous works correctly. We could do something like check
16074 for an obj_section_change_hook macro, but that might be confusing
16075 as it would not be appropriate to use it in the section changing
16076 functions in read.c, since obj-elf.c intercepts those. FIXME:
16077 This should be cleaner, somehow. */
16078 obj_elf_section_change_hook ();
16080 mips_emit_delays ();
16091 subseg_set (bss_section, (subsegT) get_absolute_expression ());
16092 demand_empty_rest_of_line ();
16096 seg = subseg_new (RDATA_SECTION_NAME,
16097 (subsegT) get_absolute_expression ());
16098 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
16099 | SEC_READONLY | SEC_RELOC
16101 if (strncmp (TARGET_OS, "elf", 3) != 0)
16102 record_alignment (seg, 4);
16103 demand_empty_rest_of_line ();
16107 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
16108 bfd_set_section_flags (stdoutput, seg,
16109 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
16110 if (strncmp (TARGET_OS, "elf", 3) != 0)
16111 record_alignment (seg, 4);
16112 demand_empty_rest_of_line ();
16116 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
16117 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
16118 if (strncmp (TARGET_OS, "elf", 3) != 0)
16119 record_alignment (seg, 4);
16120 demand_empty_rest_of_line ();
16128 s_change_section (int ignore ATTRIBUTE_UNUSED)
16130 char *section_name;
16135 int section_entry_size;
16136 int section_alignment;
16138 section_name = input_line_pointer;
16139 c = get_symbol_end ();
16141 next_c = *(input_line_pointer + 1);
16143 /* Do we have .section Name<,"flags">? */
16144 if (c != ',' || (c == ',' && next_c == '"'))
16146 /* just after name is now '\0'. */
16147 *input_line_pointer = c;
16148 input_line_pointer = section_name;
16149 obj_elf_section (ignore);
16152 input_line_pointer++;
16154 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16156 section_type = get_absolute_expression ();
16159 if (*input_line_pointer++ == ',')
16160 section_flag = get_absolute_expression ();
16163 if (*input_line_pointer++ == ',')
16164 section_entry_size = get_absolute_expression ();
16166 section_entry_size = 0;
16167 if (*input_line_pointer++ == ',')
16168 section_alignment = get_absolute_expression ();
16170 section_alignment = 0;
16171 /* FIXME: really ignore? */
16172 (void) section_alignment;
16174 section_name = xstrdup (section_name);
16176 /* When using the generic form of .section (as implemented by obj-elf.c),
16177 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16178 traditionally had to fall back on the more common @progbits instead.
16180 There's nothing really harmful in this, since bfd will correct
16181 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16182 means that, for backwards compatibility, the special_section entries
16183 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16185 Even so, we shouldn't force users of the MIPS .section syntax to
16186 incorrectly label the sections as SHT_PROGBITS. The best compromise
16187 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16188 generic type-checking code. */
16189 if (section_type == SHT_MIPS_DWARF)
16190 section_type = SHT_PROGBITS;
16192 obj_elf_change_section (section_name, section_type, section_flag,
16193 section_entry_size, 0, 0, 0);
16195 if (now_seg->name != section_name)
16196 free (section_name);
16200 mips_enable_auto_align (void)
16206 s_cons (int log_size)
16208 segment_info_type *si = seg_info (now_seg);
16209 struct insn_label_list *l = si->label_list;
16211 mips_emit_delays ();
16212 if (log_size > 0 && auto_align)
16213 mips_align (log_size, 0, l);
16214 cons (1 << log_size);
16215 mips_clear_insn_labels ();
16219 s_float_cons (int type)
16221 segment_info_type *si = seg_info (now_seg);
16222 struct insn_label_list *l = si->label_list;
16224 mips_emit_delays ();
16229 mips_align (3, 0, l);
16231 mips_align (2, 0, l);
16235 mips_clear_insn_labels ();
16238 /* Handle .globl. We need to override it because on Irix 5 you are
16241 where foo is an undefined symbol, to mean that foo should be
16242 considered to be the address of a function. */
16245 s_mips_globl (int x ATTRIBUTE_UNUSED)
16254 name = input_line_pointer;
16255 c = get_symbol_end ();
16256 symbolP = symbol_find_or_make (name);
16257 S_SET_EXTERNAL (symbolP);
16259 *input_line_pointer = c;
16260 SKIP_WHITESPACE ();
16262 /* On Irix 5, every global symbol that is not explicitly labelled as
16263 being a function is apparently labelled as being an object. */
16266 if (!is_end_of_line[(unsigned char) *input_line_pointer]
16267 && (*input_line_pointer != ','))
16272 secname = input_line_pointer;
16273 c = get_symbol_end ();
16274 sec = bfd_get_section_by_name (stdoutput, secname);
16276 as_bad (_("%s: no such section"), secname);
16277 *input_line_pointer = c;
16279 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
16280 flag = BSF_FUNCTION;
16283 symbol_get_bfdsym (symbolP)->flags |= flag;
16285 c = *input_line_pointer;
16288 input_line_pointer++;
16289 SKIP_WHITESPACE ();
16290 if (is_end_of_line[(unsigned char) *input_line_pointer])
16296 demand_empty_rest_of_line ();
16300 s_option (int x ATTRIBUTE_UNUSED)
16305 opt = input_line_pointer;
16306 c = get_symbol_end ();
16310 /* FIXME: What does this mean? */
16312 else if (strncmp (opt, "pic", 3) == 0)
16316 i = atoi (opt + 3);
16321 mips_pic = SVR4_PIC;
16322 mips_abicalls = TRUE;
16325 as_bad (_(".option pic%d not supported"), i);
16327 if (mips_pic == SVR4_PIC)
16329 if (g_switch_seen && g_switch_value != 0)
16330 as_warn (_("-G may not be used with SVR4 PIC code"));
16331 g_switch_value = 0;
16332 bfd_set_gp_size (stdoutput, 0);
16336 as_warn (_("Unrecognized option \"%s\""), opt);
16338 *input_line_pointer = c;
16339 demand_empty_rest_of_line ();
16342 /* This structure is used to hold a stack of .set values. */
16344 struct mips_option_stack
16346 struct mips_option_stack *next;
16347 struct mips_set_options options;
16350 static struct mips_option_stack *mips_opts_stack;
16352 /* Handle the .set pseudo-op. */
16355 s_mipsset (int x ATTRIBUTE_UNUSED)
16357 char *name = input_line_pointer, ch;
16358 const struct mips_ase *ase;
16360 while (!is_end_of_line[(unsigned char) *input_line_pointer])
16361 ++input_line_pointer;
16362 ch = *input_line_pointer;
16363 *input_line_pointer = '\0';
16365 if (strcmp (name, "reorder") == 0)
16367 if (mips_opts.noreorder)
16370 else if (strcmp (name, "noreorder") == 0)
16372 if (!mips_opts.noreorder)
16373 start_noreorder ();
16375 else if (strncmp (name, "at=", 3) == 0)
16377 char *s = name + 3;
16379 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
16380 as_bad (_("Unrecognized register name `%s'"), s);
16382 else if (strcmp (name, "at") == 0)
16384 mips_opts.at = ATREG;
16386 else if (strcmp (name, "noat") == 0)
16388 mips_opts.at = ZERO;
16390 else if (strcmp (name, "macro") == 0)
16392 mips_opts.warn_about_macros = 0;
16394 else if (strcmp (name, "nomacro") == 0)
16396 if (mips_opts.noreorder == 0)
16397 as_bad (_("`noreorder' must be set before `nomacro'"));
16398 mips_opts.warn_about_macros = 1;
16400 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
16402 mips_opts.nomove = 0;
16404 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
16406 mips_opts.nomove = 1;
16408 else if (strcmp (name, "bopt") == 0)
16410 mips_opts.nobopt = 0;
16412 else if (strcmp (name, "nobopt") == 0)
16414 mips_opts.nobopt = 1;
16416 else if (strcmp (name, "gp=default") == 0)
16417 mips_opts.gp32 = file_mips_gp32;
16418 else if (strcmp (name, "gp=32") == 0)
16419 mips_opts.gp32 = 1;
16420 else if (strcmp (name, "gp=64") == 0)
16422 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
16423 as_warn (_("%s isa does not support 64-bit registers"),
16424 mips_cpu_info_from_isa (mips_opts.isa)->name);
16425 mips_opts.gp32 = 0;
16427 else if (strcmp (name, "fp=default") == 0)
16428 mips_opts.fp32 = file_mips_fp32;
16429 else if (strcmp (name, "fp=32") == 0)
16430 mips_opts.fp32 = 1;
16431 else if (strcmp (name, "fp=64") == 0)
16433 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
16434 as_warn (_("%s isa does not support 64-bit floating point registers"),
16435 mips_cpu_info_from_isa (mips_opts.isa)->name);
16436 mips_opts.fp32 = 0;
16438 else if (strcmp (name, "softfloat") == 0)
16439 mips_opts.soft_float = 1;
16440 else if (strcmp (name, "hardfloat") == 0)
16441 mips_opts.soft_float = 0;
16442 else if (strcmp (name, "singlefloat") == 0)
16443 mips_opts.single_float = 1;
16444 else if (strcmp (name, "doublefloat") == 0)
16445 mips_opts.single_float = 0;
16446 else if (strcmp (name, "mips16") == 0
16447 || strcmp (name, "MIPS-16") == 0)
16449 if (mips_opts.micromips == 1)
16450 as_fatal (_("`mips16' cannot be used with `micromips'"));
16451 mips_opts.mips16 = 1;
16453 else if (strcmp (name, "nomips16") == 0
16454 || strcmp (name, "noMIPS-16") == 0)
16455 mips_opts.mips16 = 0;
16456 else if (strcmp (name, "micromips") == 0)
16458 if (mips_opts.mips16 == 1)
16459 as_fatal (_("`micromips' cannot be used with `mips16'"));
16460 mips_opts.micromips = 1;
16462 else if (strcmp (name, "nomicromips") == 0)
16463 mips_opts.micromips = 0;
16464 else if (name[0] == 'n'
16466 && (ase = mips_lookup_ase (name + 2)))
16467 mips_set_ase (ase, FALSE);
16468 else if ((ase = mips_lookup_ase (name)))
16469 mips_set_ase (ase, TRUE);
16470 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
16474 /* Permit the user to change the ISA and architecture on the fly.
16475 Needless to say, misuse can cause serious problems. */
16476 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
16479 mips_opts.isa = file_mips_isa;
16480 mips_opts.arch = file_mips_arch;
16482 else if (strncmp (name, "arch=", 5) == 0)
16484 const struct mips_cpu_info *p;
16486 p = mips_parse_cpu("internal use", name + 5);
16488 as_bad (_("unknown architecture %s"), name + 5);
16491 mips_opts.arch = p->cpu;
16492 mips_opts.isa = p->isa;
16495 else if (strncmp (name, "mips", 4) == 0)
16497 const struct mips_cpu_info *p;
16499 p = mips_parse_cpu("internal use", name);
16501 as_bad (_("unknown ISA level %s"), name + 4);
16504 mips_opts.arch = p->cpu;
16505 mips_opts.isa = p->isa;
16509 as_bad (_("unknown ISA or architecture %s"), name);
16511 switch (mips_opts.isa)
16519 mips_opts.gp32 = 1;
16520 mips_opts.fp32 = 1;
16527 mips_opts.gp32 = 0;
16528 if (mips_opts.arch == CPU_R5900)
16530 mips_opts.fp32 = 1;
16534 mips_opts.fp32 = 0;
16538 as_bad (_("unknown ISA level %s"), name + 4);
16543 mips_opts.gp32 = file_mips_gp32;
16544 mips_opts.fp32 = file_mips_fp32;
16547 else if (strcmp (name, "autoextend") == 0)
16548 mips_opts.noautoextend = 0;
16549 else if (strcmp (name, "noautoextend") == 0)
16550 mips_opts.noautoextend = 1;
16551 else if (strcmp (name, "insn32") == 0)
16552 mips_opts.insn32 = TRUE;
16553 else if (strcmp (name, "noinsn32") == 0)
16554 mips_opts.insn32 = FALSE;
16555 else if (strcmp (name, "push") == 0)
16557 struct mips_option_stack *s;
16559 s = (struct mips_option_stack *) xmalloc (sizeof *s);
16560 s->next = mips_opts_stack;
16561 s->options = mips_opts;
16562 mips_opts_stack = s;
16564 else if (strcmp (name, "pop") == 0)
16566 struct mips_option_stack *s;
16568 s = mips_opts_stack;
16570 as_bad (_(".set pop with no .set push"));
16573 /* If we're changing the reorder mode we need to handle
16574 delay slots correctly. */
16575 if (s->options.noreorder && ! mips_opts.noreorder)
16576 start_noreorder ();
16577 else if (! s->options.noreorder && mips_opts.noreorder)
16580 mips_opts = s->options;
16581 mips_opts_stack = s->next;
16585 else if (strcmp (name, "sym32") == 0)
16586 mips_opts.sym32 = TRUE;
16587 else if (strcmp (name, "nosym32") == 0)
16588 mips_opts.sym32 = FALSE;
16589 else if (strchr (name, ','))
16591 /* Generic ".set" directive; use the generic handler. */
16592 *input_line_pointer = ch;
16593 input_line_pointer = name;
16599 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
16601 mips_check_isa_supports_ases ();
16602 *input_line_pointer = ch;
16603 demand_empty_rest_of_line ();
16606 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16607 .option pic2. It means to generate SVR4 PIC calls. */
16610 s_abicalls (int ignore ATTRIBUTE_UNUSED)
16612 mips_pic = SVR4_PIC;
16613 mips_abicalls = TRUE;
16615 if (g_switch_seen && g_switch_value != 0)
16616 as_warn (_("-G may not be used with SVR4 PIC code"));
16617 g_switch_value = 0;
16619 bfd_set_gp_size (stdoutput, 0);
16620 demand_empty_rest_of_line ();
16623 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16624 PIC code. It sets the $gp register for the function based on the
16625 function address, which is in the register named in the argument.
16626 This uses a relocation against _gp_disp, which is handled specially
16627 by the linker. The result is:
16628 lui $gp,%hi(_gp_disp)
16629 addiu $gp,$gp,%lo(_gp_disp)
16630 addu $gp,$gp,.cpload argument
16631 The .cpload argument is normally $25 == $t9.
16633 The -mno-shared option changes this to:
16634 lui $gp,%hi(__gnu_local_gp)
16635 addiu $gp,$gp,%lo(__gnu_local_gp)
16636 and the argument is ignored. This saves an instruction, but the
16637 resulting code is not position independent; it uses an absolute
16638 address for __gnu_local_gp. Thus code assembled with -mno-shared
16639 can go into an ordinary executable, but not into a shared library. */
16642 s_cpload (int ignore ATTRIBUTE_UNUSED)
16648 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16649 .cpload is ignored. */
16650 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16656 if (mips_opts.mips16)
16658 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16659 ignore_rest_of_line ();
16663 /* .cpload should be in a .set noreorder section. */
16664 if (mips_opts.noreorder == 0)
16665 as_warn (_(".cpload not in noreorder section"));
16667 reg = tc_get_register (0);
16669 /* If we need to produce a 64-bit address, we are better off using
16670 the default instruction sequence. */
16671 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
16673 ex.X_op = O_symbol;
16674 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
16676 ex.X_op_symbol = NULL;
16677 ex.X_add_number = 0;
16679 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16680 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16682 mips_mark_labels ();
16683 mips_assembling_insn = TRUE;
16686 macro_build_lui (&ex, mips_gp_register);
16687 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16688 mips_gp_register, BFD_RELOC_LO16);
16690 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
16691 mips_gp_register, reg);
16694 mips_assembling_insn = FALSE;
16695 demand_empty_rest_of_line ();
16698 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16699 .cpsetup $reg1, offset|$reg2, label
16701 If offset is given, this results in:
16702 sd $gp, offset($sp)
16703 lui $gp, %hi(%neg(%gp_rel(label)))
16704 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16705 daddu $gp, $gp, $reg1
16707 If $reg2 is given, this results in:
16708 daddu $reg2, $gp, $0
16709 lui $gp, %hi(%neg(%gp_rel(label)))
16710 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16711 daddu $gp, $gp, $reg1
16712 $reg1 is normally $25 == $t9.
16714 The -mno-shared option replaces the last three instructions with
16716 addiu $gp,$gp,%lo(_gp) */
16719 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
16721 expressionS ex_off;
16722 expressionS ex_sym;
16725 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16726 We also need NewABI support. */
16727 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16733 if (mips_opts.mips16)
16735 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16736 ignore_rest_of_line ();
16740 reg1 = tc_get_register (0);
16741 SKIP_WHITESPACE ();
16742 if (*input_line_pointer != ',')
16744 as_bad (_("missing argument separator ',' for .cpsetup"));
16748 ++input_line_pointer;
16749 SKIP_WHITESPACE ();
16750 if (*input_line_pointer == '$')
16752 mips_cpreturn_register = tc_get_register (0);
16753 mips_cpreturn_offset = -1;
16757 mips_cpreturn_offset = get_absolute_expression ();
16758 mips_cpreturn_register = -1;
16760 SKIP_WHITESPACE ();
16761 if (*input_line_pointer != ',')
16763 as_bad (_("missing argument separator ',' for .cpsetup"));
16767 ++input_line_pointer;
16768 SKIP_WHITESPACE ();
16769 expression (&ex_sym);
16771 mips_mark_labels ();
16772 mips_assembling_insn = TRUE;
16775 if (mips_cpreturn_register == -1)
16777 ex_off.X_op = O_constant;
16778 ex_off.X_add_symbol = NULL;
16779 ex_off.X_op_symbol = NULL;
16780 ex_off.X_add_number = mips_cpreturn_offset;
16782 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
16783 BFD_RELOC_LO16, SP);
16786 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
16787 mips_gp_register, 0);
16789 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
16791 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
16792 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
16795 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
16796 mips_gp_register, -1, BFD_RELOC_GPREL16,
16797 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
16799 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
16800 mips_gp_register, reg1);
16806 ex.X_op = O_symbol;
16807 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
16808 ex.X_op_symbol = NULL;
16809 ex.X_add_number = 0;
16811 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16812 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16814 macro_build_lui (&ex, mips_gp_register);
16815 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16816 mips_gp_register, BFD_RELOC_LO16);
16821 mips_assembling_insn = FALSE;
16822 demand_empty_rest_of_line ();
16826 s_cplocal (int ignore ATTRIBUTE_UNUSED)
16828 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16829 .cplocal is ignored. */
16830 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16836 if (mips_opts.mips16)
16838 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16839 ignore_rest_of_line ();
16843 mips_gp_register = tc_get_register (0);
16844 demand_empty_rest_of_line ();
16847 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16848 offset from $sp. The offset is remembered, and after making a PIC
16849 call $gp is restored from that location. */
16852 s_cprestore (int ignore ATTRIBUTE_UNUSED)
16856 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16857 .cprestore is ignored. */
16858 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16864 if (mips_opts.mips16)
16866 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16867 ignore_rest_of_line ();
16871 mips_cprestore_offset = get_absolute_expression ();
16872 mips_cprestore_valid = 1;
16874 ex.X_op = O_constant;
16875 ex.X_add_symbol = NULL;
16876 ex.X_op_symbol = NULL;
16877 ex.X_add_number = mips_cprestore_offset;
16879 mips_mark_labels ();
16880 mips_assembling_insn = TRUE;
16883 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
16884 SP, HAVE_64BIT_ADDRESSES);
16887 mips_assembling_insn = FALSE;
16888 demand_empty_rest_of_line ();
16891 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16892 was given in the preceding .cpsetup, it results in:
16893 ld $gp, offset($sp)
16895 If a register $reg2 was given there, it results in:
16896 daddu $gp, $reg2, $0 */
16899 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
16903 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16904 We also need NewABI support. */
16905 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16911 if (mips_opts.mips16)
16913 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16914 ignore_rest_of_line ();
16918 mips_mark_labels ();
16919 mips_assembling_insn = TRUE;
16922 if (mips_cpreturn_register == -1)
16924 ex.X_op = O_constant;
16925 ex.X_add_symbol = NULL;
16926 ex.X_op_symbol = NULL;
16927 ex.X_add_number = mips_cpreturn_offset;
16929 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
16932 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
16933 mips_cpreturn_register, 0);
16936 mips_assembling_insn = FALSE;
16937 demand_empty_rest_of_line ();
16940 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16941 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16942 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16943 debug information or MIPS16 TLS. */
16946 s_tls_rel_directive (const size_t bytes, const char *dirstr,
16947 bfd_reloc_code_real_type rtype)
16954 if (ex.X_op != O_symbol)
16956 as_bad (_("Unsupported use of %s"), dirstr);
16957 ignore_rest_of_line ();
16960 p = frag_more (bytes);
16961 md_number_to_chars (p, 0, bytes);
16962 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
16963 demand_empty_rest_of_line ();
16964 mips_clear_insn_labels ();
16967 /* Handle .dtprelword. */
16970 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
16972 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
16975 /* Handle .dtpreldword. */
16978 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
16980 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
16983 /* Handle .tprelword. */
16986 s_tprelword (int ignore ATTRIBUTE_UNUSED)
16988 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
16991 /* Handle .tpreldword. */
16994 s_tpreldword (int ignore ATTRIBUTE_UNUSED)
16996 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
16999 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
17000 code. It sets the offset to use in gp_rel relocations. */
17003 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
17005 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
17006 We also need NewABI support. */
17007 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
17013 mips_gprel_offset = get_absolute_expression ();
17015 demand_empty_rest_of_line ();
17018 /* Handle the .gpword pseudo-op. This is used when generating PIC
17019 code. It generates a 32 bit GP relative reloc. */
17022 s_gpword (int ignore ATTRIBUTE_UNUSED)
17024 segment_info_type *si;
17025 struct insn_label_list *l;
17029 /* When not generating PIC code, this is treated as .word. */
17030 if (mips_pic != SVR4_PIC)
17036 si = seg_info (now_seg);
17037 l = si->label_list;
17038 mips_emit_delays ();
17040 mips_align (2, 0, l);
17043 mips_clear_insn_labels ();
17045 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17047 as_bad (_("Unsupported use of .gpword"));
17048 ignore_rest_of_line ();
17052 md_number_to_chars (p, 0, 4);
17053 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17054 BFD_RELOC_GPREL32);
17056 demand_empty_rest_of_line ();
17060 s_gpdword (int ignore ATTRIBUTE_UNUSED)
17062 segment_info_type *si;
17063 struct insn_label_list *l;
17067 /* When not generating PIC code, this is treated as .dword. */
17068 if (mips_pic != SVR4_PIC)
17074 si = seg_info (now_seg);
17075 l = si->label_list;
17076 mips_emit_delays ();
17078 mips_align (3, 0, l);
17081 mips_clear_insn_labels ();
17083 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17085 as_bad (_("Unsupported use of .gpdword"));
17086 ignore_rest_of_line ();
17090 md_number_to_chars (p, 0, 8);
17091 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17092 BFD_RELOC_GPREL32)->fx_tcbit = 1;
17094 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17095 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
17096 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
17098 demand_empty_rest_of_line ();
17101 /* Handle the .ehword pseudo-op. This is used when generating unwinding
17102 tables. It generates a R_MIPS_EH reloc. */
17105 s_ehword (int ignore ATTRIBUTE_UNUSED)
17110 mips_emit_delays ();
17113 mips_clear_insn_labels ();
17115 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17117 as_bad (_("Unsupported use of .ehword"));
17118 ignore_rest_of_line ();
17122 md_number_to_chars (p, 0, 4);
17123 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17124 BFD_RELOC_MIPS_EH);
17126 demand_empty_rest_of_line ();
17129 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17130 tables in SVR4 PIC code. */
17133 s_cpadd (int ignore ATTRIBUTE_UNUSED)
17137 /* This is ignored when not generating SVR4 PIC code. */
17138 if (mips_pic != SVR4_PIC)
17144 mips_mark_labels ();
17145 mips_assembling_insn = TRUE;
17147 /* Add $gp to the register named as an argument. */
17149 reg = tc_get_register (0);
17150 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
17153 mips_assembling_insn = FALSE;
17154 demand_empty_rest_of_line ();
17157 /* Handle the .insn pseudo-op. This marks instruction labels in
17158 mips16/micromips mode. This permits the linker to handle them specially,
17159 such as generating jalx instructions when needed. We also make
17160 them odd for the duration of the assembly, in order to generate the
17161 right sort of code. We will make them even in the adjust_symtab
17162 routine, while leaving them marked. This is convenient for the
17163 debugger and the disassembler. The linker knows to make them odd
17167 s_insn (int ignore ATTRIBUTE_UNUSED)
17169 mips_mark_labels ();
17171 demand_empty_rest_of_line ();
17174 /* Handle the .nan pseudo-op. */
17177 s_nan (int ignore ATTRIBUTE_UNUSED)
17179 static const char str_legacy[] = "legacy";
17180 static const char str_2008[] = "2008";
17183 for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++);
17185 if (i == sizeof (str_2008) - 1
17186 && memcmp (input_line_pointer, str_2008, i) == 0)
17187 mips_flag_nan2008 = TRUE;
17188 else if (i == sizeof (str_legacy) - 1
17189 && memcmp (input_line_pointer, str_legacy, i) == 0)
17190 mips_flag_nan2008 = FALSE;
17192 as_bad (_("Bad .nan directive"));
17194 input_line_pointer += i;
17195 demand_empty_rest_of_line ();
17198 /* Handle a .stab[snd] directive. Ideally these directives would be
17199 implemented in a transparent way, so that removing them would not
17200 have any effect on the generated instructions. However, s_stab
17201 internally changes the section, so in practice we need to decide
17202 now whether the preceding label marks compressed code. We do not
17203 support changing the compression mode of a label after a .stab*
17204 directive, such as in:
17210 so the current mode wins. */
17213 s_mips_stab (int type)
17215 mips_mark_labels ();
17219 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17222 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
17229 name = input_line_pointer;
17230 c = get_symbol_end ();
17231 symbolP = symbol_find_or_make (name);
17232 S_SET_WEAK (symbolP);
17233 *input_line_pointer = c;
17235 SKIP_WHITESPACE ();
17237 if (! is_end_of_line[(unsigned char) *input_line_pointer])
17239 if (S_IS_DEFINED (symbolP))
17241 as_bad (_("ignoring attempt to redefine symbol %s"),
17242 S_GET_NAME (symbolP));
17243 ignore_rest_of_line ();
17247 if (*input_line_pointer == ',')
17249 ++input_line_pointer;
17250 SKIP_WHITESPACE ();
17254 if (exp.X_op != O_symbol)
17256 as_bad (_("bad .weakext directive"));
17257 ignore_rest_of_line ();
17260 symbol_set_value_expression (symbolP, &exp);
17263 demand_empty_rest_of_line ();
17266 /* Parse a register string into a number. Called from the ECOFF code
17267 to parse .frame. The argument is non-zero if this is the frame
17268 register, so that we can record it in mips_frame_reg. */
17271 tc_get_register (int frame)
17275 SKIP_WHITESPACE ();
17276 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
17280 mips_frame_reg = reg != 0 ? reg : SP;
17281 mips_frame_reg_valid = 1;
17282 mips_cprestore_valid = 0;
17288 md_section_align (asection *seg, valueT addr)
17290 int align = bfd_get_section_alignment (stdoutput, seg);
17292 /* We don't need to align ELF sections to the full alignment.
17293 However, Irix 5 may prefer that we align them at least to a 16
17294 byte boundary. We don't bother to align the sections if we
17295 are targeted for an embedded system. */
17296 if (strncmp (TARGET_OS, "elf", 3) == 0)
17301 return ((addr + (1 << align) - 1) & (-1 << align));
17304 /* Utility routine, called from above as well. If called while the
17305 input file is still being read, it's only an approximation. (For
17306 example, a symbol may later become defined which appeared to be
17307 undefined earlier.) */
17310 nopic_need_relax (symbolS *sym, int before_relaxing)
17315 if (g_switch_value > 0)
17317 const char *symname;
17320 /* Find out whether this symbol can be referenced off the $gp
17321 register. It can be if it is smaller than the -G size or if
17322 it is in the .sdata or .sbss section. Certain symbols can
17323 not be referenced off the $gp, although it appears as though
17325 symname = S_GET_NAME (sym);
17326 if (symname != (const char *) NULL
17327 && (strcmp (symname, "eprol") == 0
17328 || strcmp (symname, "etext") == 0
17329 || strcmp (symname, "_gp") == 0
17330 || strcmp (symname, "edata") == 0
17331 || strcmp (symname, "_fbss") == 0
17332 || strcmp (symname, "_fdata") == 0
17333 || strcmp (symname, "_ftext") == 0
17334 || strcmp (symname, "end") == 0
17335 || strcmp (symname, "_gp_disp") == 0))
17337 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
17339 #ifndef NO_ECOFF_DEBUGGING
17340 || (symbol_get_obj (sym)->ecoff_extern_size != 0
17341 && (symbol_get_obj (sym)->ecoff_extern_size
17342 <= g_switch_value))
17344 /* We must defer this decision until after the whole
17345 file has been read, since there might be a .extern
17346 after the first use of this symbol. */
17347 || (before_relaxing
17348 #ifndef NO_ECOFF_DEBUGGING
17349 && symbol_get_obj (sym)->ecoff_extern_size == 0
17351 && S_GET_VALUE (sym) == 0)
17352 || (S_GET_VALUE (sym) != 0
17353 && S_GET_VALUE (sym) <= g_switch_value)))
17357 const char *segname;
17359 segname = segment_name (S_GET_SEGMENT (sym));
17360 gas_assert (strcmp (segname, ".lit8") != 0
17361 && strcmp (segname, ".lit4") != 0);
17362 change = (strcmp (segname, ".sdata") != 0
17363 && strcmp (segname, ".sbss") != 0
17364 && strncmp (segname, ".sdata.", 7) != 0
17365 && strncmp (segname, ".sbss.", 6) != 0
17366 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
17367 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
17372 /* We are not optimizing for the $gp register. */
17377 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17380 pic_need_relax (symbolS *sym, asection *segtype)
17384 /* Handle the case of a symbol equated to another symbol. */
17385 while (symbol_equated_reloc_p (sym))
17389 /* It's possible to get a loop here in a badly written program. */
17390 n = symbol_get_value_expression (sym)->X_add_symbol;
17396 if (symbol_section_p (sym))
17399 symsec = S_GET_SEGMENT (sym);
17401 /* This must duplicate the test in adjust_reloc_syms. */
17402 return (!bfd_is_und_section (symsec)
17403 && !bfd_is_abs_section (symsec)
17404 && !bfd_is_com_section (symsec)
17405 && !s_is_linkonce (sym, segtype)
17406 /* A global or weak symbol is treated as external. */
17407 && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym)));
17411 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17412 extended opcode. SEC is the section the frag is in. */
17415 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
17418 const struct mips16_immed_operand *op;
17420 int mintiny, maxtiny;
17424 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
17426 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17429 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
17430 op = mips16_immed_operands;
17431 while (op->type != type)
17434 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
17439 if (type == '<' || type == '>' || type == '[' || type == ']')
17442 maxtiny = 1 << op->nbits;
17447 maxtiny = (1 << op->nbits) - 1;
17452 mintiny = - (1 << (op->nbits - 1));
17453 maxtiny = (1 << (op->nbits - 1)) - 1;
17456 sym_frag = symbol_get_frag (fragp->fr_symbol);
17457 val = S_GET_VALUE (fragp->fr_symbol);
17458 symsec = S_GET_SEGMENT (fragp->fr_symbol);
17464 /* We won't have the section when we are called from
17465 mips_relax_frag. However, we will always have been called
17466 from md_estimate_size_before_relax first. If this is a
17467 branch to a different section, we mark it as such. If SEC is
17468 NULL, and the frag is not marked, then it must be a branch to
17469 the same section. */
17472 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
17477 /* Must have been called from md_estimate_size_before_relax. */
17480 fragp->fr_subtype =
17481 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17483 /* FIXME: We should support this, and let the linker
17484 catch branches and loads that are out of range. */
17485 as_bad_where (fragp->fr_file, fragp->fr_line,
17486 _("unsupported PC relative reference to different section"));
17490 if (fragp != sym_frag && sym_frag->fr_address == 0)
17491 /* Assume non-extended on the first relaxation pass.
17492 The address we have calculated will be bogus if this is
17493 a forward branch to another frag, as the forward frag
17494 will have fr_address == 0. */
17498 /* In this case, we know for sure that the symbol fragment is in
17499 the same section. If the relax_marker of the symbol fragment
17500 differs from the relax_marker of this fragment, we have not
17501 yet adjusted the symbol fragment fr_address. We want to add
17502 in STRETCH in order to get a better estimate of the address.
17503 This particularly matters because of the shift bits. */
17505 && sym_frag->relax_marker != fragp->relax_marker)
17509 /* Adjust stretch for any alignment frag. Note that if have
17510 been expanding the earlier code, the symbol may be
17511 defined in what appears to be an earlier frag. FIXME:
17512 This doesn't handle the fr_subtype field, which specifies
17513 a maximum number of bytes to skip when doing an
17515 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
17517 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
17520 stretch = - ((- stretch)
17521 & ~ ((1 << (int) f->fr_offset) - 1));
17523 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
17532 addr = fragp->fr_address + fragp->fr_fix;
17534 /* The base address rules are complicated. The base address of
17535 a branch is the following instruction. The base address of a
17536 PC relative load or add is the instruction itself, but if it
17537 is in a delay slot (in which case it can not be extended) use
17538 the address of the instruction whose delay slot it is in. */
17539 if (type == 'p' || type == 'q')
17543 /* If we are currently assuming that this frag should be
17544 extended, then, the current address is two bytes
17546 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17549 /* Ignore the low bit in the target, since it will be set
17550 for a text label. */
17551 if ((val & 1) != 0)
17554 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17556 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17559 val -= addr & ~ ((1 << op->shift) - 1);
17561 /* Branch offsets have an implicit 0 in the lowest bit. */
17562 if (type == 'p' || type == 'q')
17565 /* If any of the shifted bits are set, we must use an extended
17566 opcode. If the address depends on the size of this
17567 instruction, this can lead to a loop, so we arrange to always
17568 use an extended opcode. We only check this when we are in
17569 the main relaxation loop, when SEC is NULL. */
17570 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
17572 fragp->fr_subtype =
17573 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17577 /* If we are about to mark a frag as extended because the value
17578 is precisely maxtiny + 1, then there is a chance of an
17579 infinite loop as in the following code:
17584 In this case when the la is extended, foo is 0x3fc bytes
17585 away, so the la can be shrunk, but then foo is 0x400 away, so
17586 the la must be extended. To avoid this loop, we mark the
17587 frag as extended if it was small, and is about to become
17588 extended with a value of maxtiny + 1. */
17589 if (val == ((maxtiny + 1) << op->shift)
17590 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
17593 fragp->fr_subtype =
17594 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17598 else if (symsec != absolute_section && sec != NULL)
17599 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
17601 if ((val & ((1 << op->shift) - 1)) != 0
17602 || val < (mintiny << op->shift)
17603 || val > (maxtiny << op->shift))
17609 /* Compute the length of a branch sequence, and adjust the
17610 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17611 worst-case length is computed, with UPDATE being used to indicate
17612 whether an unconditional (-1), branch-likely (+1) or regular (0)
17613 branch is to be computed. */
17615 relaxed_branch_length (fragS *fragp, asection *sec, int update)
17617 bfd_boolean toofar;
17621 && S_IS_DEFINED (fragp->fr_symbol)
17622 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17627 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17629 addr = fragp->fr_address + fragp->fr_fix + 4;
17633 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
17636 /* If the symbol is not defined or it's in a different segment,
17637 assume the user knows what's going on and emit a short
17643 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17645 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
17646 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
17647 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
17648 RELAX_BRANCH_LINK (fragp->fr_subtype),
17654 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
17657 if (mips_pic != NO_PIC)
17659 /* Additional space for PIC loading of target address. */
17661 if (mips_opts.isa == ISA_MIPS1)
17662 /* Additional space for $at-stabilizing nop. */
17666 /* If branch is conditional. */
17667 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
17674 /* Compute the length of a branch sequence, and adjust the
17675 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17676 worst-case length is computed, with UPDATE being used to indicate
17677 whether an unconditional (-1), or regular (0) branch is to be
17681 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
17683 bfd_boolean toofar;
17687 && S_IS_DEFINED (fragp->fr_symbol)
17688 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17693 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17694 /* Ignore the low bit in the target, since it will be set
17695 for a text label. */
17696 if ((val & 1) != 0)
17699 addr = fragp->fr_address + fragp->fr_fix + 4;
17703 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
17706 /* If the symbol is not defined or it's in a different segment,
17707 assume the user knows what's going on and emit a short
17713 if (fragp && update
17714 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17715 fragp->fr_subtype = (toofar
17716 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
17717 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
17722 bfd_boolean compact_known = fragp != NULL;
17723 bfd_boolean compact = FALSE;
17724 bfd_boolean uncond;
17727 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17729 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
17731 uncond = update < 0;
17733 /* If label is out of range, we turn branch <br>:
17735 <br> label # 4 bytes
17741 nop # 2 bytes if compact && !PIC
17744 if (mips_pic == NO_PIC && (!compact_known || compact))
17747 /* If assembling PIC code, we further turn:
17753 lw/ld at, %got(label)(gp) # 4 bytes
17754 d/addiu at, %lo(label) # 4 bytes
17757 if (mips_pic != NO_PIC)
17760 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17762 <brneg> 0f # 4 bytes
17763 nop # 2 bytes if !compact
17766 length += (compact_known && compact) ? 4 : 6;
17772 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17773 bit accordingly. */
17776 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
17778 bfd_boolean toofar;
17781 && S_IS_DEFINED (fragp->fr_symbol)
17782 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17788 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17789 /* Ignore the low bit in the target, since it will be set
17790 for a text label. */
17791 if ((val & 1) != 0)
17794 /* Assume this is a 2-byte branch. */
17795 addr = fragp->fr_address + fragp->fr_fix + 2;
17797 /* We try to avoid the infinite loop by not adding 2 more bytes for
17802 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17804 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
17805 else if (type == 'E')
17806 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
17811 /* If the symbol is not defined or it's in a different segment,
17812 we emit a normal 32-bit branch. */
17815 if (fragp && update
17816 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17818 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
17819 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
17827 /* Estimate the size of a frag before relaxing. Unless this is the
17828 mips16, we are not really relaxing here, and the final size is
17829 encoded in the subtype information. For the mips16, we have to
17830 decide whether we are using an extended opcode or not. */
17833 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
17837 if (RELAX_BRANCH_P (fragp->fr_subtype))
17840 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
17842 return fragp->fr_var;
17845 if (RELAX_MIPS16_P (fragp->fr_subtype))
17846 /* We don't want to modify the EXTENDED bit here; it might get us
17847 into infinite loops. We change it only in mips_relax_frag(). */
17848 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
17850 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17854 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17855 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
17856 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17857 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
17858 fragp->fr_var = length;
17863 if (mips_pic == NO_PIC)
17864 change = nopic_need_relax (fragp->fr_symbol, 0);
17865 else if (mips_pic == SVR4_PIC)
17866 change = pic_need_relax (fragp->fr_symbol, segtype);
17867 else if (mips_pic == VXWORKS_PIC)
17868 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17875 fragp->fr_subtype |= RELAX_USE_SECOND;
17876 return -RELAX_FIRST (fragp->fr_subtype);
17879 return -RELAX_SECOND (fragp->fr_subtype);
17882 /* This is called to see whether a reloc against a defined symbol
17883 should be converted into a reloc against a section. */
17886 mips_fix_adjustable (fixS *fixp)
17888 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
17889 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17892 if (fixp->fx_addsy == NULL)
17895 /* If symbol SYM is in a mergeable section, relocations of the form
17896 SYM + 0 can usually be made section-relative. The mergeable data
17897 is then identified by the section offset rather than by the symbol.
17899 However, if we're generating REL LO16 relocations, the offset is split
17900 between the LO16 and parterning high part relocation. The linker will
17901 need to recalculate the complete offset in order to correctly identify
17904 The linker has traditionally not looked for the parterning high part
17905 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17906 placed anywhere. Rather than break backwards compatibility by changing
17907 this, it seems better not to force the issue, and instead keep the
17908 original symbol. This will work with either linker behavior. */
17909 if ((lo16_reloc_p (fixp->fx_r_type)
17910 || reloc_needs_lo_p (fixp->fx_r_type))
17911 && HAVE_IN_PLACE_ADDENDS
17912 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
17915 /* There is no place to store an in-place offset for JALR relocations.
17916 Likewise an in-range offset of limited PC-relative relocations may
17917 overflow the in-place relocatable field if recalculated against the
17918 start address of the symbol's containing section. */
17919 if (HAVE_IN_PLACE_ADDENDS
17920 && (limited_pcrel_reloc_p (fixp->fx_r_type)
17921 || jalr_reloc_p (fixp->fx_r_type)))
17924 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17925 to a floating-point stub. The same is true for non-R_MIPS16_26
17926 relocations against MIPS16 functions; in this case, the stub becomes
17927 the function's canonical address.
17929 Floating-point stubs are stored in unique .mips16.call.* or
17930 .mips16.fn.* sections. If a stub T for function F is in section S,
17931 the first relocation in section S must be against F; this is how the
17932 linker determines the target function. All relocations that might
17933 resolve to T must also be against F. We therefore have the following
17934 restrictions, which are given in an intentionally-redundant way:
17936 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17939 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17940 if that stub might be used.
17942 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17945 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17946 that stub might be used.
17948 There is a further restriction:
17950 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17951 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17952 targets with in-place addends; the relocation field cannot
17953 encode the low bit.
17955 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17956 against a MIPS16 symbol. We deal with (5) by by not reducing any
17957 such relocations on REL targets.
17959 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17960 relocation against some symbol R, no relocation against R may be
17961 reduced. (Note that this deals with (2) as well as (1) because
17962 relocations against global symbols will never be reduced on ELF
17963 targets.) This approach is a little simpler than trying to detect
17964 stub sections, and gives the "all or nothing" per-symbol consistency
17965 that we have for MIPS16 symbols. */
17966 if (fixp->fx_subsy == NULL
17967 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
17968 || *symbol_get_tc (fixp->fx_addsy)
17969 || (HAVE_IN_PLACE_ADDENDS
17970 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
17971 && jmp_reloc_p (fixp->fx_r_type))))
17977 /* Translate internal representation of relocation info to BFD target
17981 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
17983 static arelent *retval[4];
17985 bfd_reloc_code_real_type code;
17987 memset (retval, 0, sizeof(retval));
17988 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
17989 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
17990 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
17991 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
17993 if (fixp->fx_pcrel)
17995 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
17996 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
17997 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
17998 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
17999 || fixp->fx_r_type == BFD_RELOC_32_PCREL);
18001 /* At this point, fx_addnumber is "symbol offset - pcrel address".
18002 Relocations want only the symbol offset. */
18003 reloc->addend = fixp->fx_addnumber + reloc->address;
18006 reloc->addend = fixp->fx_addnumber;
18008 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
18009 entry to be used in the relocation's section offset. */
18010 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
18012 reloc->address = reloc->addend;
18016 code = fixp->fx_r_type;
18018 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
18019 if (reloc->howto == NULL)
18021 as_bad_where (fixp->fx_file, fixp->fx_line,
18022 _("Can not represent %s relocation in this object file format"),
18023 bfd_get_reloc_code_name (code));
18030 /* Relax a machine dependent frag. This returns the amount by which
18031 the current size of the frag should change. */
18034 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
18036 if (RELAX_BRANCH_P (fragp->fr_subtype))
18038 offsetT old_var = fragp->fr_var;
18040 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
18042 return fragp->fr_var - old_var;
18045 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
18047 offsetT old_var = fragp->fr_var;
18048 offsetT new_var = 4;
18050 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
18051 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
18052 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
18053 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
18054 fragp->fr_var = new_var;
18056 return new_var - old_var;
18059 if (! RELAX_MIPS16_P (fragp->fr_subtype))
18062 if (mips16_extended_frag (fragp, NULL, stretch))
18064 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18066 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
18071 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18073 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
18080 /* Convert a machine dependent frag. */
18083 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
18085 if (RELAX_BRANCH_P (fragp->fr_subtype))
18088 unsigned long insn;
18092 buf = fragp->fr_literal + fragp->fr_fix;
18093 insn = read_insn (buf);
18095 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
18097 /* We generate a fixup instead of applying it right now
18098 because, if there are linker relaxations, we're going to
18099 need the relocations. */
18100 exp.X_op = O_symbol;
18101 exp.X_add_symbol = fragp->fr_symbol;
18102 exp.X_add_number = fragp->fr_offset;
18104 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
18105 BFD_RELOC_16_PCREL_S2);
18106 fixp->fx_file = fragp->fr_file;
18107 fixp->fx_line = fragp->fr_line;
18109 buf = write_insn (buf, insn);
18115 as_warn_where (fragp->fr_file, fragp->fr_line,
18116 _("Relaxed out-of-range branch into a jump"));
18118 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
18121 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18123 /* Reverse the branch. */
18124 switch ((insn >> 28) & 0xf)
18127 /* bc[0-3][tf]l? instructions can have the condition
18128 reversed by tweaking a single TF bit, and their
18129 opcodes all have 0x4???????. */
18130 gas_assert ((insn & 0xf3e00000) == 0x41000000);
18131 insn ^= 0x00010000;
18135 /* bltz 0x04000000 bgez 0x04010000
18136 bltzal 0x04100000 bgezal 0x04110000 */
18137 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
18138 insn ^= 0x00010000;
18142 /* beq 0x10000000 bne 0x14000000
18143 blez 0x18000000 bgtz 0x1c000000 */
18144 insn ^= 0x04000000;
18152 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
18154 /* Clear the and-link bit. */
18155 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
18157 /* bltzal 0x04100000 bgezal 0x04110000
18158 bltzall 0x04120000 bgezall 0x04130000 */
18159 insn &= ~0x00100000;
18162 /* Branch over the branch (if the branch was likely) or the
18163 full jump (not likely case). Compute the offset from the
18164 current instruction to branch to. */
18165 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18169 /* How many bytes in instructions we've already emitted? */
18170 i = buf - fragp->fr_literal - fragp->fr_fix;
18171 /* How many bytes in instructions from here to the end? */
18172 i = fragp->fr_var - i;
18174 /* Convert to instruction count. */
18176 /* Branch counts from the next instruction. */
18179 /* Branch over the jump. */
18180 buf = write_insn (buf, insn);
18183 buf = write_insn (buf, 0);
18185 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18187 /* beql $0, $0, 2f */
18189 /* Compute the PC offset from the current instruction to
18190 the end of the variable frag. */
18191 /* How many bytes in instructions we've already emitted? */
18192 i = buf - fragp->fr_literal - fragp->fr_fix;
18193 /* How many bytes in instructions from here to the end? */
18194 i = fragp->fr_var - i;
18195 /* Convert to instruction count. */
18197 /* Don't decrement i, because we want to branch over the
18201 buf = write_insn (buf, insn);
18202 buf = write_insn (buf, 0);
18206 if (mips_pic == NO_PIC)
18209 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
18210 ? 0x0c000000 : 0x08000000);
18211 exp.X_op = O_symbol;
18212 exp.X_add_symbol = fragp->fr_symbol;
18213 exp.X_add_number = fragp->fr_offset;
18215 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18216 FALSE, BFD_RELOC_MIPS_JMP);
18217 fixp->fx_file = fragp->fr_file;
18218 fixp->fx_line = fragp->fr_line;
18220 buf = write_insn (buf, insn);
18224 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
18226 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18227 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
18228 insn |= at << OP_SH_RT;
18229 exp.X_op = O_symbol;
18230 exp.X_add_symbol = fragp->fr_symbol;
18231 exp.X_add_number = fragp->fr_offset;
18233 if (fragp->fr_offset)
18235 exp.X_add_symbol = make_expr_symbol (&exp);
18236 exp.X_add_number = 0;
18239 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18240 FALSE, BFD_RELOC_MIPS_GOT16);
18241 fixp->fx_file = fragp->fr_file;
18242 fixp->fx_line = fragp->fr_line;
18244 buf = write_insn (buf, insn);
18246 if (mips_opts.isa == ISA_MIPS1)
18248 buf = write_insn (buf, 0);
18250 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18251 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
18252 insn |= at << OP_SH_RS | at << OP_SH_RT;
18254 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18255 FALSE, BFD_RELOC_LO16);
18256 fixp->fx_file = fragp->fr_file;
18257 fixp->fx_line = fragp->fr_line;
18259 buf = write_insn (buf, insn);
18262 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
18266 insn |= at << OP_SH_RS;
18268 buf = write_insn (buf, insn);
18272 fragp->fr_fix += fragp->fr_var;
18273 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18277 /* Relax microMIPS branches. */
18278 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
18280 char *buf = fragp->fr_literal + fragp->fr_fix;
18281 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
18282 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
18283 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
18284 bfd_boolean short_ds;
18285 unsigned long insn;
18289 exp.X_op = O_symbol;
18290 exp.X_add_symbol = fragp->fr_symbol;
18291 exp.X_add_number = fragp->fr_offset;
18293 fragp->fr_fix += fragp->fr_var;
18295 /* Handle 16-bit branches that fit or are forced to fit. */
18296 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
18298 /* We generate a fixup instead of applying it right now,
18299 because if there is linker relaxation, we're going to
18300 need the relocations. */
18302 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
18303 BFD_RELOC_MICROMIPS_10_PCREL_S1);
18304 else if (type == 'E')
18305 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
18306 BFD_RELOC_MICROMIPS_7_PCREL_S1);
18310 fixp->fx_file = fragp->fr_file;
18311 fixp->fx_line = fragp->fr_line;
18313 /* These relocations can have an addend that won't fit in
18315 fixp->fx_no_overflow = 1;
18320 /* Handle 32-bit branches that fit or are forced to fit. */
18321 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18322 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18324 /* We generate a fixup instead of applying it right now,
18325 because if there is linker relaxation, we're going to
18326 need the relocations. */
18327 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
18328 BFD_RELOC_MICROMIPS_16_PCREL_S1);
18329 fixp->fx_file = fragp->fr_file;
18330 fixp->fx_line = fragp->fr_line;
18336 /* Relax 16-bit branches to 32-bit branches. */
18339 insn = read_compressed_insn (buf, 2);
18341 if ((insn & 0xfc00) == 0xcc00) /* b16 */
18342 insn = 0x94000000; /* beq */
18343 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18345 unsigned long regno;
18347 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
18348 regno = micromips_to_32_reg_d_map [regno];
18349 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
18350 insn |= regno << MICROMIPSOP_SH_RS;
18355 /* Nothing else to do, just write it out. */
18356 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18357 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18359 buf = write_compressed_insn (buf, insn, 4);
18360 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18365 insn = read_compressed_insn (buf, 4);
18367 /* Relax 32-bit branches to a sequence of instructions. */
18368 as_warn_where (fragp->fr_file, fragp->fr_line,
18369 _("Relaxed out-of-range branch into a jump"));
18371 /* Set the short-delay-slot bit. */
18372 short_ds = al && (insn & 0x02000000) != 0;
18374 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
18378 /* Reverse the branch. */
18379 if ((insn & 0xfc000000) == 0x94000000 /* beq */
18380 || (insn & 0xfc000000) == 0xb4000000) /* bne */
18381 insn ^= 0x20000000;
18382 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
18383 || (insn & 0xffe00000) == 0x40400000 /* bgez */
18384 || (insn & 0xffe00000) == 0x40800000 /* blez */
18385 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
18386 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
18387 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
18388 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
18389 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
18390 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
18391 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
18392 insn ^= 0x00400000;
18393 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
18394 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
18395 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
18396 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
18397 insn ^= 0x00200000;
18403 /* Clear the and-link and short-delay-slot bits. */
18404 gas_assert ((insn & 0xfda00000) == 0x40200000);
18406 /* bltzal 0x40200000 bgezal 0x40600000 */
18407 /* bltzals 0x42200000 bgezals 0x42600000 */
18408 insn &= ~0x02200000;
18411 /* Make a label at the end for use with the branch. */
18412 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
18413 micromips_label_inc ();
18414 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
18417 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE,
18418 BFD_RELOC_MICROMIPS_16_PCREL_S1);
18419 fixp->fx_file = fragp->fr_file;
18420 fixp->fx_line = fragp->fr_line;
18422 /* Branch over the jump. */
18423 buf = write_compressed_insn (buf, insn, 4);
18426 buf = write_compressed_insn (buf, 0x0c00, 2);
18429 if (mips_pic == NO_PIC)
18431 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
18433 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18434 insn = al ? jal : 0xd4000000;
18436 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18437 BFD_RELOC_MICROMIPS_JMP);
18438 fixp->fx_file = fragp->fr_file;
18439 fixp->fx_line = fragp->fr_line;
18441 buf = write_compressed_insn (buf, insn, 4);
18444 buf = write_compressed_insn (buf, 0x0c00, 2);
18448 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
18449 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
18450 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
18452 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18453 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
18454 insn |= at << MICROMIPSOP_SH_RT;
18456 if (exp.X_add_number)
18458 exp.X_add_symbol = make_expr_symbol (&exp);
18459 exp.X_add_number = 0;
18462 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18463 BFD_RELOC_MICROMIPS_GOT16);
18464 fixp->fx_file = fragp->fr_file;
18465 fixp->fx_line = fragp->fr_line;
18467 buf = write_compressed_insn (buf, insn, 4);
18469 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18470 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
18471 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
18473 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18474 BFD_RELOC_MICROMIPS_LO16);
18475 fixp->fx_file = fragp->fr_file;
18476 fixp->fx_line = fragp->fr_line;
18478 buf = write_compressed_insn (buf, insn, 4);
18480 /* jr/jrc/jalr/jalrs $at */
18481 insn = al ? jalr : jr;
18482 insn |= at << MICROMIPSOP_SH_MJ;
18484 buf = write_compressed_insn (buf, insn, 2);
18487 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18491 if (RELAX_MIPS16_P (fragp->fr_subtype))
18494 const struct mips16_immed_operand *op;
18497 unsigned int user_length, length;
18498 unsigned long insn;
18501 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
18502 op = mips16_immed_operands;
18503 while (op->type != type)
18506 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
18507 val = resolve_symbol_value (fragp->fr_symbol);
18512 addr = fragp->fr_address + fragp->fr_fix;
18514 /* The rules for the base address of a PC relative reloc are
18515 complicated; see mips16_extended_frag. */
18516 if (type == 'p' || type == 'q')
18521 /* Ignore the low bit in the target, since it will be
18522 set for a text label. */
18523 if ((val & 1) != 0)
18526 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
18528 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
18531 addr &= ~ (addressT) ((1 << op->shift) - 1);
18534 /* Make sure the section winds up with the alignment we have
18537 record_alignment (asec, op->shift);
18541 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
18542 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
18543 as_warn_where (fragp->fr_file, fragp->fr_line,
18544 _("extended instruction in delay slot"));
18546 buf = fragp->fr_literal + fragp->fr_fix;
18548 insn = read_compressed_insn (buf, 2);
18550 insn |= MIPS16_EXTEND;
18552 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
18554 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
18559 mips16_immed (fragp->fr_file, fragp->fr_line, type,
18560 BFD_RELOC_UNUSED, val, user_length, &insn);
18562 length = (ext ? 4 : 2);
18563 gas_assert (mips16_opcode_length (insn) == length);
18564 write_compressed_insn (buf, insn, length);
18565 fragp->fr_fix += length;
18569 relax_substateT subtype = fragp->fr_subtype;
18570 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
18571 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
18575 first = RELAX_FIRST (subtype);
18576 second = RELAX_SECOND (subtype);
18577 fixp = (fixS *) fragp->fr_opcode;
18579 /* If the delay slot chosen does not match the size of the instruction,
18580 then emit a warning. */
18581 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
18582 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
18587 s = subtype & (RELAX_DELAY_SLOT_16BIT
18588 | RELAX_DELAY_SLOT_SIZE_FIRST
18589 | RELAX_DELAY_SLOT_SIZE_SECOND);
18590 msg = macro_warning (s);
18592 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18596 /* Possibly emit a warning if we've chosen the longer option. */
18597 if (use_second == second_longer)
18603 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
18604 msg = macro_warning (s);
18606 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18610 /* Go through all the fixups for the first sequence. Disable them
18611 (by marking them as done) if we're going to use the second
18612 sequence instead. */
18614 && fixp->fx_frag == fragp
18615 && fixp->fx_where < fragp->fr_fix - second)
18617 if (subtype & RELAX_USE_SECOND)
18619 fixp = fixp->fx_next;
18622 /* Go through the fixups for the second sequence. Disable them if
18623 we're going to use the first sequence, otherwise adjust their
18624 addresses to account for the relaxation. */
18625 while (fixp && fixp->fx_frag == fragp)
18627 if (subtype & RELAX_USE_SECOND)
18628 fixp->fx_where -= first;
18631 fixp = fixp->fx_next;
18634 /* Now modify the frag contents. */
18635 if (subtype & RELAX_USE_SECOND)
18639 start = fragp->fr_literal + fragp->fr_fix - first - second;
18640 memmove (start, start + first, second);
18641 fragp->fr_fix -= first;
18644 fragp->fr_fix -= second;
18648 /* This function is called after the relocs have been generated.
18649 We've been storing mips16 text labels as odd. Here we convert them
18650 back to even for the convenience of the debugger. */
18653 mips_frob_file_after_relocs (void)
18656 unsigned int count, i;
18658 syms = bfd_get_outsymbols (stdoutput);
18659 count = bfd_get_symcount (stdoutput);
18660 for (i = 0; i < count; i++, syms++)
18661 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
18662 && ((*syms)->value & 1) != 0)
18664 (*syms)->value &= ~1;
18665 /* If the symbol has an odd size, it was probably computed
18666 incorrectly, so adjust that as well. */
18667 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
18668 ++elf_symbol (*syms)->internal_elf_sym.st_size;
18672 /* This function is called whenever a label is defined, including fake
18673 labels instantiated off the dot special symbol. It is used when
18674 handling branch delays; if a branch has a label, we assume we cannot
18675 move it. This also bumps the value of the symbol by 1 in compressed
18679 mips_record_label (symbolS *sym)
18681 segment_info_type *si = seg_info (now_seg);
18682 struct insn_label_list *l;
18684 if (free_insn_labels == NULL)
18685 l = (struct insn_label_list *) xmalloc (sizeof *l);
18688 l = free_insn_labels;
18689 free_insn_labels = l->next;
18693 l->next = si->label_list;
18694 si->label_list = l;
18697 /* This function is called as tc_frob_label() whenever a label is defined
18698 and adds a DWARF-2 record we only want for true labels. */
18701 mips_define_label (symbolS *sym)
18703 mips_record_label (sym);
18704 dwarf2_emit_label (sym);
18707 /* This function is called by tc_new_dot_label whenever a new dot symbol
18711 mips_add_dot_label (symbolS *sym)
18713 mips_record_label (sym);
18714 if (mips_assembling_insn && HAVE_CODE_COMPRESSION)
18715 mips_compressed_mark_label (sym);
18718 /* Some special processing for a MIPS ELF file. */
18721 mips_elf_final_processing (void)
18723 /* Write out the register information. */
18724 if (mips_abi != N64_ABI)
18728 s.ri_gprmask = mips_gprmask;
18729 s.ri_cprmask[0] = mips_cprmask[0];
18730 s.ri_cprmask[1] = mips_cprmask[1];
18731 s.ri_cprmask[2] = mips_cprmask[2];
18732 s.ri_cprmask[3] = mips_cprmask[3];
18733 /* The gp_value field is set by the MIPS ELF backend. */
18735 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
18736 ((Elf32_External_RegInfo *)
18737 mips_regmask_frag));
18741 Elf64_Internal_RegInfo s;
18743 s.ri_gprmask = mips_gprmask;
18745 s.ri_cprmask[0] = mips_cprmask[0];
18746 s.ri_cprmask[1] = mips_cprmask[1];
18747 s.ri_cprmask[2] = mips_cprmask[2];
18748 s.ri_cprmask[3] = mips_cprmask[3];
18749 /* The gp_value field is set by the MIPS ELF backend. */
18751 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
18752 ((Elf64_External_RegInfo *)
18753 mips_regmask_frag));
18756 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18757 sort of BFD interface for this. */
18758 if (mips_any_noreorder)
18759 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
18760 if (mips_pic != NO_PIC)
18762 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
18763 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18766 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18768 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
18769 defined at present; this might need to change in future. */
18770 if (file_ase_mips16)
18771 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
18772 if (file_ase_micromips)
18773 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
18774 if (file_ase & ASE_MDMX)
18775 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
18777 /* Set the MIPS ELF ABI flags. */
18778 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
18779 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
18780 else if (mips_abi == O64_ABI)
18781 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
18782 else if (mips_abi == EABI_ABI)
18784 if (!file_mips_gp32)
18785 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
18787 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
18789 else if (mips_abi == N32_ABI)
18790 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
18792 /* Nothing to do for N64_ABI. */
18794 if (mips_32bitmode)
18795 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
18797 if (mips_flag_nan2008)
18798 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008;
18800 #if 0 /* XXX FIXME */
18801 /* 32 bit code with 64 bit FP registers. */
18802 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
18803 elf_elfheader (stdoutput)->e_flags |= ???;
18807 typedef struct proc {
18809 symbolS *func_end_sym;
18810 unsigned long reg_mask;
18811 unsigned long reg_offset;
18812 unsigned long fpreg_mask;
18813 unsigned long fpreg_offset;
18814 unsigned long frame_offset;
18815 unsigned long frame_reg;
18816 unsigned long pc_reg;
18819 static procS cur_proc;
18820 static procS *cur_proc_ptr;
18821 static int numprocs;
18823 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18824 as "2", and a normal nop as "0". */
18826 #define NOP_OPCODE_MIPS 0
18827 #define NOP_OPCODE_MIPS16 1
18828 #define NOP_OPCODE_MICROMIPS 2
18831 mips_nop_opcode (void)
18833 if (seg_info (now_seg)->tc_segment_info_data.micromips)
18834 return NOP_OPCODE_MICROMIPS;
18835 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
18836 return NOP_OPCODE_MIPS16;
18838 return NOP_OPCODE_MIPS;
18841 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18842 32-bit microMIPS NOPs here (if applicable). */
18845 mips_handle_align (fragS *fragp)
18849 int bytes, size, excess;
18852 if (fragp->fr_type != rs_align_code)
18855 p = fragp->fr_literal + fragp->fr_fix;
18857 switch (nop_opcode)
18859 case NOP_OPCODE_MICROMIPS:
18860 opcode = micromips_nop32_insn.insn_opcode;
18863 case NOP_OPCODE_MIPS16:
18864 opcode = mips16_nop_insn.insn_opcode;
18867 case NOP_OPCODE_MIPS:
18869 opcode = nop_insn.insn_opcode;
18874 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
18875 excess = bytes % size;
18877 /* Handle the leading part if we're not inserting a whole number of
18878 instructions, and make it the end of the fixed part of the frag.
18879 Try to fit in a short microMIPS NOP if applicable and possible,
18880 and use zeroes otherwise. */
18881 gas_assert (excess < 4);
18882 fragp->fr_fix += excess;
18887 /* Fall through. */
18889 if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32)
18891 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2);
18895 /* Fall through. */
18898 /* Fall through. */
18903 md_number_to_chars (p, opcode, size);
18904 fragp->fr_var = size;
18908 md_obj_begin (void)
18915 /* Check for premature end, nesting errors, etc. */
18917 as_warn (_("missing .end at end of assembly"));
18926 if (*input_line_pointer == '-')
18928 ++input_line_pointer;
18931 if (!ISDIGIT (*input_line_pointer))
18932 as_bad (_("expected simple number"));
18933 if (input_line_pointer[0] == '0')
18935 if (input_line_pointer[1] == 'x')
18937 input_line_pointer += 2;
18938 while (ISXDIGIT (*input_line_pointer))
18941 val |= hex_value (*input_line_pointer++);
18943 return negative ? -val : val;
18947 ++input_line_pointer;
18948 while (ISDIGIT (*input_line_pointer))
18951 val |= *input_line_pointer++ - '0';
18953 return negative ? -val : val;
18956 if (!ISDIGIT (*input_line_pointer))
18958 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18959 *input_line_pointer, *input_line_pointer);
18960 as_warn (_("invalid number"));
18963 while (ISDIGIT (*input_line_pointer))
18966 val += *input_line_pointer++ - '0';
18968 return negative ? -val : val;
18971 /* The .file directive; just like the usual .file directive, but there
18972 is an initial number which is the ECOFF file index. In the non-ECOFF
18973 case .file implies DWARF-2. */
18976 s_mips_file (int x ATTRIBUTE_UNUSED)
18978 static int first_file_directive = 0;
18980 if (ECOFF_DEBUGGING)
18989 filename = dwarf2_directive_file (0);
18991 /* Versions of GCC up to 3.1 start files with a ".file"
18992 directive even for stabs output. Make sure that this
18993 ".file" is handled. Note that you need a version of GCC
18994 after 3.1 in order to support DWARF-2 on MIPS. */
18995 if (filename != NULL && ! first_file_directive)
18997 (void) new_logical_line (filename, -1);
18998 s_app_file_string (filename, 0);
19000 first_file_directive = 1;
19004 /* The .loc directive, implying DWARF-2. */
19007 s_mips_loc (int x ATTRIBUTE_UNUSED)
19009 if (!ECOFF_DEBUGGING)
19010 dwarf2_directive_loc (0);
19013 /* The .end directive. */
19016 s_mips_end (int x ATTRIBUTE_UNUSED)
19020 /* Following functions need their own .frame and .cprestore directives. */
19021 mips_frame_reg_valid = 0;
19022 mips_cprestore_valid = 0;
19024 if (!is_end_of_line[(unsigned char) *input_line_pointer])
19027 demand_empty_rest_of_line ();
19032 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
19033 as_warn (_(".end not in text section"));
19037 as_warn (_(".end directive without a preceding .ent directive."));
19038 demand_empty_rest_of_line ();
19044 gas_assert (S_GET_NAME (p));
19045 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
19046 as_warn (_(".end symbol does not match .ent symbol."));
19048 if (debug_type == DEBUG_STABS)
19049 stabs_generate_asm_endfunc (S_GET_NAME (p),
19053 as_warn (_(".end directive missing or unknown symbol"));
19055 /* Create an expression to calculate the size of the function. */
19056 if (p && cur_proc_ptr)
19058 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
19059 expressionS *exp = xmalloc (sizeof (expressionS));
19062 exp->X_op = O_subtract;
19063 exp->X_add_symbol = symbol_temp_new_now ();
19064 exp->X_op_symbol = p;
19065 exp->X_add_number = 0;
19067 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
19070 /* Generate a .pdr section. */
19071 if (!ECOFF_DEBUGGING && mips_flag_pdr)
19073 segT saved_seg = now_seg;
19074 subsegT saved_subseg = now_subseg;
19078 #ifdef md_flush_pending_output
19079 md_flush_pending_output ();
19082 gas_assert (pdr_seg);
19083 subseg_set (pdr_seg, 0);
19085 /* Write the symbol. */
19086 exp.X_op = O_symbol;
19087 exp.X_add_symbol = p;
19088 exp.X_add_number = 0;
19089 emit_expr (&exp, 4);
19091 fragp = frag_more (7 * 4);
19093 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
19094 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
19095 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
19096 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
19097 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
19098 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
19099 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
19101 subseg_set (saved_seg, saved_subseg);
19104 cur_proc_ptr = NULL;
19107 /* The .aent and .ent directives. */
19110 s_mips_ent (int aent)
19114 symbolP = get_symbol ();
19115 if (*input_line_pointer == ',')
19116 ++input_line_pointer;
19117 SKIP_WHITESPACE ();
19118 if (ISDIGIT (*input_line_pointer)
19119 || *input_line_pointer == '-')
19122 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
19123 as_warn (_(".ent or .aent not in text section."));
19125 if (!aent && cur_proc_ptr)
19126 as_warn (_("missing .end"));
19130 /* This function needs its own .frame and .cprestore directives. */
19131 mips_frame_reg_valid = 0;
19132 mips_cprestore_valid = 0;
19134 cur_proc_ptr = &cur_proc;
19135 memset (cur_proc_ptr, '\0', sizeof (procS));
19137 cur_proc_ptr->func_sym = symbolP;
19141 if (debug_type == DEBUG_STABS)
19142 stabs_generate_asm_func (S_GET_NAME (symbolP),
19143 S_GET_NAME (symbolP));
19146 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
19148 demand_empty_rest_of_line ();
19151 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19152 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19153 s_mips_frame is used so that we can set the PDR information correctly.
19154 We can't use the ecoff routines because they make reference to the ecoff
19155 symbol table (in the mdebug section). */
19158 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
19160 if (ECOFF_DEBUGGING)
19166 if (cur_proc_ptr == (procS *) NULL)
19168 as_warn (_(".frame outside of .ent"));
19169 demand_empty_rest_of_line ();
19173 cur_proc_ptr->frame_reg = tc_get_register (1);
19175 SKIP_WHITESPACE ();
19176 if (*input_line_pointer++ != ','
19177 || get_absolute_expression_and_terminator (&val) != ',')
19179 as_warn (_("Bad .frame directive"));
19180 --input_line_pointer;
19181 demand_empty_rest_of_line ();
19185 cur_proc_ptr->frame_offset = val;
19186 cur_proc_ptr->pc_reg = tc_get_register (0);
19188 demand_empty_rest_of_line ();
19192 /* The .fmask and .mask directives. If the mdebug section is present
19193 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19194 embedded targets, s_mips_mask is used so that we can set the PDR
19195 information correctly. We can't use the ecoff routines because they
19196 make reference to the ecoff symbol table (in the mdebug section). */
19199 s_mips_mask (int reg_type)
19201 if (ECOFF_DEBUGGING)
19202 s_ignore (reg_type);
19207 if (cur_proc_ptr == (procS *) NULL)
19209 as_warn (_(".mask/.fmask outside of .ent"));
19210 demand_empty_rest_of_line ();
19214 if (get_absolute_expression_and_terminator (&mask) != ',')
19216 as_warn (_("Bad .mask/.fmask directive"));
19217 --input_line_pointer;
19218 demand_empty_rest_of_line ();
19222 off = get_absolute_expression ();
19224 if (reg_type == 'F')
19226 cur_proc_ptr->fpreg_mask = mask;
19227 cur_proc_ptr->fpreg_offset = off;
19231 cur_proc_ptr->reg_mask = mask;
19232 cur_proc_ptr->reg_offset = off;
19235 demand_empty_rest_of_line ();
19239 /* A table describing all the processors gas knows about. Names are
19240 matched in the order listed.
19242 To ease comparison, please keep this table in the same order as
19243 gcc's mips_cpu_info_table[]. */
19244 static const struct mips_cpu_info mips_cpu_info_table[] =
19246 /* Entries for generic ISAs */
19247 { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 },
19248 { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 },
19249 { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 },
19250 { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 },
19251 { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 },
19252 { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 },
19253 { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19254 { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 },
19255 { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 },
19258 { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 },
19259 { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 },
19260 { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 },
19263 { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 },
19266 { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 },
19267 { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 },
19268 { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 },
19269 { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 },
19270 { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 },
19271 { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 },
19272 { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 },
19273 { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 },
19274 { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 },
19275 { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 },
19276 { "orion", 0, 0, ISA_MIPS3, CPU_R4600 },
19277 { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 },
19278 { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 },
19279 /* ST Microelectronics Loongson 2E and 2F cores */
19280 { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E },
19281 { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F },
19284 { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 },
19285 { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 },
19286 { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 },
19287 { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 },
19288 { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 },
19289 { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 },
19290 { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 },
19291 { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 },
19292 { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 },
19293 { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 },
19294 { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 },
19295 { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 },
19296 { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 },
19297 { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 },
19298 { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 },
19301 { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19302 { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19303 { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19304 { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
19306 /* MIPS 32 Release 2 */
19307 { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19308 { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19309 { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19310 { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
19311 { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19312 { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19313 { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19314 { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19315 { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
19316 ISA_MIPS32R2, CPU_MIPS32R2 },
19317 { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
19318 ISA_MIPS32R2, CPU_MIPS32R2 },
19319 { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19320 { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19321 { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19322 { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19323 /* Deprecated forms of the above. */
19324 { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19325 { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19326 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19327 { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19328 { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19329 { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19330 { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19331 /* Deprecated forms of the above. */
19332 { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19333 { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19334 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19335 { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19336 { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19337 { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19338 { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19339 /* Deprecated forms of the above. */
19340 { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19341 { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19342 /* 34Kn is a 34kc without DSP. */
19343 { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19344 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19345 { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19346 { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19347 { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19348 { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19349 { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19350 /* Deprecated forms of the above. */
19351 { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19352 { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19353 /* 1004K cores are multiprocessor versions of the 34K. */
19354 { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19355 { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19356 { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19357 { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19360 { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 },
19361 { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 },
19362 { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19363 { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19365 /* Broadcom SB-1 CPU core */
19366 { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
19367 /* Broadcom SB-1A CPU core */
19368 { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
19370 { "loongson3a", 0, 0, ISA_MIPS64, CPU_LOONGSON_3A },
19372 /* MIPS 64 Release 2 */
19374 /* Cavium Networks Octeon CPU core */
19375 { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
19376 { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP },
19377 { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 },
19380 { "xlr", 0, 0, ISA_MIPS64, CPU_XLR },
19383 XLP is mostly like XLR, with the prominent exception that it is
19384 MIPS64R2 rather than MIPS64. */
19385 { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
19388 { NULL, 0, 0, 0, 0 }
19392 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19393 with a final "000" replaced by "k". Ignore case.
19395 Note: this function is shared between GCC and GAS. */
19398 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
19400 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
19401 given++, canonical++;
19403 return ((*given == 0 && *canonical == 0)
19404 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
19408 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19409 CPU name. We've traditionally allowed a lot of variation here.
19411 Note: this function is shared between GCC and GAS. */
19414 mips_matching_cpu_name_p (const char *canonical, const char *given)
19416 /* First see if the name matches exactly, or with a final "000"
19417 turned into "k". */
19418 if (mips_strict_matching_cpu_name_p (canonical, given))
19421 /* If not, try comparing based on numerical designation alone.
19422 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19423 if (TOLOWER (*given) == 'r')
19425 if (!ISDIGIT (*given))
19428 /* Skip over some well-known prefixes in the canonical name,
19429 hoping to find a number there too. */
19430 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
19432 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
19434 else if (TOLOWER (canonical[0]) == 'r')
19437 return mips_strict_matching_cpu_name_p (canonical, given);
19441 /* Parse an option that takes the name of a processor as its argument.
19442 OPTION is the name of the option and CPU_STRING is the argument.
19443 Return the corresponding processor enumeration if the CPU_STRING is
19444 recognized, otherwise report an error and return null.
19446 A similar function exists in GCC. */
19448 static const struct mips_cpu_info *
19449 mips_parse_cpu (const char *option, const char *cpu_string)
19451 const struct mips_cpu_info *p;
19453 /* 'from-abi' selects the most compatible architecture for the given
19454 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19455 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19456 version. Look first at the -mgp options, if given, otherwise base
19457 the choice on MIPS_DEFAULT_64BIT.
19459 Treat NO_ABI like the EABIs. One reason to do this is that the
19460 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19461 architecture. This code picks MIPS I for 'mips' and MIPS III for
19462 'mips64', just as we did in the days before 'from-abi'. */
19463 if (strcasecmp (cpu_string, "from-abi") == 0)
19465 if (ABI_NEEDS_32BIT_REGS (mips_abi))
19466 return mips_cpu_info_from_isa (ISA_MIPS1);
19468 if (ABI_NEEDS_64BIT_REGS (mips_abi))
19469 return mips_cpu_info_from_isa (ISA_MIPS3);
19471 if (file_mips_gp32 >= 0)
19472 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
19474 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19479 /* 'default' has traditionally been a no-op. Probably not very useful. */
19480 if (strcasecmp (cpu_string, "default") == 0)
19483 for (p = mips_cpu_info_table; p->name != 0; p++)
19484 if (mips_matching_cpu_name_p (p->name, cpu_string))
19487 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
19491 /* Return the canonical processor information for ISA (a member of the
19492 ISA_MIPS* enumeration). */
19494 static const struct mips_cpu_info *
19495 mips_cpu_info_from_isa (int isa)
19499 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19500 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
19501 && isa == mips_cpu_info_table[i].isa)
19502 return (&mips_cpu_info_table[i]);
19507 static const struct mips_cpu_info *
19508 mips_cpu_info_from_arch (int arch)
19512 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19513 if (arch == mips_cpu_info_table[i].cpu)
19514 return (&mips_cpu_info_table[i]);
19520 show (FILE *stream, const char *string, int *col_p, int *first_p)
19524 fprintf (stream, "%24s", "");
19529 fprintf (stream, ", ");
19533 if (*col_p + strlen (string) > 72)
19535 fprintf (stream, "\n%24s", "");
19539 fprintf (stream, "%s", string);
19540 *col_p += strlen (string);
19546 md_show_usage (FILE *stream)
19551 fprintf (stream, _("\
19553 -EB generate big endian output\n\
19554 -EL generate little endian output\n\
19555 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19556 -G NUM allow referencing objects up to NUM bytes\n\
19557 implicitly with the gp register [default 8]\n"));
19558 fprintf (stream, _("\
19559 -mips1 generate MIPS ISA I instructions\n\
19560 -mips2 generate MIPS ISA II instructions\n\
19561 -mips3 generate MIPS ISA III instructions\n\
19562 -mips4 generate MIPS ISA IV instructions\n\
19563 -mips5 generate MIPS ISA V instructions\n\
19564 -mips32 generate MIPS32 ISA instructions\n\
19565 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19566 -mips64 generate MIPS64 ISA instructions\n\
19567 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19568 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19572 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19573 show (stream, mips_cpu_info_table[i].name, &column, &first);
19574 show (stream, "from-abi", &column, &first);
19575 fputc ('\n', stream);
19577 fprintf (stream, _("\
19578 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19579 -no-mCPU don't generate code specific to CPU.\n\
19580 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19584 show (stream, "3900", &column, &first);
19585 show (stream, "4010", &column, &first);
19586 show (stream, "4100", &column, &first);
19587 show (stream, "4650", &column, &first);
19588 fputc ('\n', stream);
19590 fprintf (stream, _("\
19591 -mips16 generate mips16 instructions\n\
19592 -no-mips16 do not generate mips16 instructions\n"));
19593 fprintf (stream, _("\
19594 -mmicromips generate microMIPS instructions\n\
19595 -mno-micromips do not generate microMIPS instructions\n"));
19596 fprintf (stream, _("\
19597 -msmartmips generate smartmips instructions\n\
19598 -mno-smartmips do not generate smartmips instructions\n"));
19599 fprintf (stream, _("\
19600 -mdsp generate DSP instructions\n\
19601 -mno-dsp do not generate DSP instructions\n"));
19602 fprintf (stream, _("\
19603 -mdspr2 generate DSP R2 instructions\n\
19604 -mno-dspr2 do not generate DSP R2 instructions\n"));
19605 fprintf (stream, _("\
19606 -mmt generate MT instructions\n\
19607 -mno-mt do not generate MT instructions\n"));
19608 fprintf (stream, _("\
19609 -mmcu generate MCU instructions\n\
19610 -mno-mcu do not generate MCU instructions\n"));
19611 fprintf (stream, _("\
19612 -mvirt generate Virtualization instructions\n\
19613 -mno-virt do not generate Virtualization instructions\n"));
19614 fprintf (stream, _("\
19615 -minsn32 only generate 32-bit microMIPS instructions\n\
19616 -mno-insn32 generate all microMIPS instructions\n"));
19617 fprintf (stream, _("\
19618 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19619 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19620 -mfix-vr4120 work around certain VR4120 errata\n\
19621 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19622 -mfix-24k insert a nop after ERET and DERET instructions\n\
19623 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19624 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19625 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19626 -msym32 assume all symbols have 32-bit values\n\
19627 -O0 remove unneeded NOPs, do not swap branches\n\
19628 -O remove unneeded NOPs and swap branches\n\
19629 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19630 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19631 fprintf (stream, _("\
19632 -mhard-float allow floating-point instructions\n\
19633 -msoft-float do not allow floating-point instructions\n\
19634 -msingle-float only allow 32-bit floating-point operations\n\
19635 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19636 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
19637 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
19638 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
19642 show (stream, "legacy", &column, &first);
19643 show (stream, "2008", &column, &first);
19645 fputc ('\n', stream);
19647 fprintf (stream, _("\
19648 -KPIC, -call_shared generate SVR4 position independent code\n\
19649 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19650 -mvxworks-pic generate VxWorks position independent code\n\
19651 -non_shared do not generate code that can operate with DSOs\n\
19652 -xgot assume a 32 bit GOT\n\
19653 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19654 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19655 position dependent (non shared) code\n\
19656 -mabi=ABI create ABI conformant object file for:\n"));
19660 show (stream, "32", &column, &first);
19661 show (stream, "o64", &column, &first);
19662 show (stream, "n32", &column, &first);
19663 show (stream, "64", &column, &first);
19664 show (stream, "eabi", &column, &first);
19666 fputc ('\n', stream);
19668 fprintf (stream, _("\
19669 -32 create o32 ABI object file (default)\n\
19670 -n32 create n32 ABI object file\n\
19671 -64 create 64 ABI object file\n"));
19676 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
19678 if (HAVE_64BIT_SYMBOLS)
19679 return dwarf2_format_64bit_irix;
19681 return dwarf2_format_32bit;
19686 mips_dwarf2_addr_size (void)
19688 if (HAVE_64BIT_OBJECTS)
19694 /* Standard calling conventions leave the CFA at SP on entry. */
19696 mips_cfi_frame_initial_instructions (void)
19698 cfi_add_CFA_def_cfa_register (SP);
19702 tc_mips_regname_to_dw2regnum (char *regname)
19704 unsigned int regnum = -1;
19707 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))