1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
38 #include "opcode/mips.h"
40 #include "dwarf2dbg.h"
43 #define DBG(x) printf x
49 /* Clean up namespace so we can include obj-elf.h too. */
50 static int mips_output_flavor PARAMS ((void));
51 static int mips_output_flavor () { return OUTPUT_FLAVOR; }
52 #undef OBJ_PROCESS_STAB
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
80 int mips_flag_mdebug = -1;
84 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
85 static char *mips_regmask_frag;
91 #define PIC_CALL_REG 25
99 #define ILLEGAL_REG (32)
101 /* Allow override of standard little-endian ECOFF format. */
103 #ifndef ECOFF_LITTLE_FORMAT
104 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
107 extern int target_big_endian;
109 /* The name of the readonly data section. */
110 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
112 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
114 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
120 /* The ABI to use. */
131 /* MIPS ABI we are using for this output file. */
132 static enum mips_abi_level mips_abi = NO_ABI;
134 /* This is the set of options which may be modified by the .set
135 pseudo-op. We use a struct so that .set push and .set pop are more
138 struct mips_set_options
140 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
141 if it has not been initialized. Changed by `.set mipsN', and the
142 -mipsN command line option, and the default CPU. */
144 /* Enabled Application Specific Extensions (ASEs). These are set to -1
145 if they have not been initialized. Changed by `.set <asename>', by
146 command line options, and based on the default architecture. */
149 /* Whether we are assembling for the mips16 processor. 0 if we are
150 not, 1 if we are, and -1 if the value has not been initialized.
151 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
152 -nomips16 command line options, and the default CPU. */
154 /* Non-zero if we should not reorder instructions. Changed by `.set
155 reorder' and `.set noreorder'. */
157 /* Non-zero if we should not permit the $at ($1) register to be used
158 in instructions. Changed by `.set at' and `.set noat'. */
160 /* Non-zero if we should warn when a macro instruction expands into
161 more than one machine instruction. Changed by `.set nomacro' and
163 int warn_about_macros;
164 /* Non-zero if we should not move instructions. Changed by `.set
165 move', `.set volatile', `.set nomove', and `.set novolatile'. */
167 /* Non-zero if we should not optimize branches by moving the target
168 of the branch into the delay slot. Actually, we don't perform
169 this optimization anyhow. Changed by `.set bopt' and `.set
172 /* Non-zero if we should not autoextend mips16 instructions.
173 Changed by `.set autoextend' and `.set noautoextend'. */
175 /* Restrict general purpose registers and floating point registers
176 to 32 bit. This is initially determined when -mgp32 or -mfp32
177 is passed but can changed if the assembler code uses .set mipsN. */
182 /* True if -mgp32 was passed. */
183 static int file_mips_gp32 = -1;
185 /* True if -mfp32 was passed. */
186 static int file_mips_fp32 = -1;
188 /* This is the struct we use to hold the current set of options. Note
189 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
190 -1 to indicate that they have not been initialized. */
192 static struct mips_set_options mips_opts =
194 ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0
197 /* These variables are filled in with the masks of registers used.
198 The object format code reads them and puts them in the appropriate
200 unsigned long mips_gprmask;
201 unsigned long mips_cprmask[4];
203 /* MIPS ISA we are using for this output file. */
204 static int file_mips_isa = ISA_UNKNOWN;
206 /* True if -mips16 was passed or implied by arguments passed on the
207 command line (e.g., by -march). */
208 static int file_ase_mips16;
210 /* True if -mips3d was passed or implied by arguments passed on the
211 command line (e.g., by -march). */
212 static int file_ase_mips3d;
214 /* True if -mdmx was passed or implied by arguments passed on the
215 command line (e.g., by -march). */
216 static int file_ase_mdmx;
218 /* The argument of the -march= flag. The architecture we are assembling. */
219 static int mips_arch = CPU_UNKNOWN;
220 static const char *mips_arch_string;
221 static const struct mips_cpu_info *mips_arch_info;
223 /* The argument of the -mtune= flag. The architecture for which we
225 static int mips_tune = CPU_UNKNOWN;
226 static const char *mips_tune_string;
227 static const struct mips_cpu_info *mips_tune_info;
229 /* True when generating 32-bit code for a 64-bit processor. */
230 static int mips_32bitmode = 0;
232 /* Some ISA's have delay slots for instructions which read or write
233 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
234 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
235 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
236 delay slot in this ISA. The uses of this macro assume that any
237 ISA that has delay slots for one of these, has them for all. They
238 also assume that ISAs which don't have delays for these insns, don't
239 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
240 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
242 || (ISA) == ISA_MIPS2 \
243 || (ISA) == ISA_MIPS3 \
246 /* True if the given ABI requires 32-bit registers. */
247 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
249 /* Likewise 64-bit registers. */
250 #define ABI_NEEDS_64BIT_REGS(ABI) \
252 || (ABI) == N64_ABI \
255 /* Return true if ISA supports 64 bit gp register instructions. */
256 #define ISA_HAS_64BIT_REGS(ISA) ( \
258 || (ISA) == ISA_MIPS4 \
259 || (ISA) == ISA_MIPS5 \
260 || (ISA) == ISA_MIPS64 \
263 /* Return true if ISA supports 64-bit right rotate (dror et al.)
265 #define ISA_HAS_DROR(ISA) ( \
269 /* Return true if ISA supports 32-bit right rotate (ror et al.)
271 #define ISA_HAS_ROR(ISA) ( \
272 (ISA) == ISA_MIPS32R2 \
275 #define HAVE_32BIT_GPRS \
276 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
278 #define HAVE_32BIT_FPRS \
279 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
281 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
282 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
284 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
286 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
288 /* We can only have 64bit addresses if the object file format
290 #define HAVE_32BIT_ADDRESSES \
292 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
293 || ! HAVE_64BIT_OBJECTS) \
294 && mips_pic != EMBEDDED_PIC))
296 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
298 /* Return true if the given CPU supports the MIPS16 ASE. */
299 #define CPU_HAS_MIPS16(cpu) \
300 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
301 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
303 /* Return true if the given CPU supports the MIPS3D ASE. */
304 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
307 /* Return true if the given CPU supports the MDMX ASE. */
308 #define CPU_HAS_MDMX(cpu) (FALSE \
311 /* True if CPU has a dror instruction. */
312 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
314 /* True if CPU has a ror instruction. */
315 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
317 /* Whether the processor uses hardware interlocks to protect
318 reads from the HI and LO registers, and thus does not
319 require nops to be inserted. */
321 #define hilo_interlocks (mips_arch == CPU_R4010 \
322 || mips_arch == CPU_VR5500 \
323 || mips_arch == CPU_SB1 \
326 /* Whether the processor uses hardware interlocks to protect reads
327 from the GPRs, and thus does not require nops to be inserted. */
328 #define gpr_interlocks \
329 (mips_opts.isa != ISA_MIPS1 \
330 || mips_arch == CPU_VR5400 \
331 || mips_arch == CPU_VR5500 \
332 || mips_arch == CPU_R3900)
334 /* As with other "interlocks" this is used by hardware that has FP
335 (co-processor) interlocks. */
336 /* Itbl support may require additional care here. */
337 #define cop_interlocks (mips_arch == CPU_R4300 \
338 || mips_arch == CPU_VR5400 \
339 || mips_arch == CPU_VR5500 \
340 || mips_arch == CPU_SB1 \
343 /* Is this a mfhi or mflo instruction? */
344 #define MF_HILO_INSN(PINFO) \
345 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
347 /* MIPS PIC level. */
349 enum mips_pic_level mips_pic;
351 /* Warn about all NOPS that the assembler generates. */
352 static int warn_nops = 0;
354 /* 1 if we should generate 32 bit offsets from the $gp register in
355 SVR4_PIC mode. Currently has no meaning in other modes. */
356 static int mips_big_got = 0;
358 /* 1 if trap instructions should used for overflow rather than break
360 static int mips_trap = 0;
362 /* 1 if double width floating point constants should not be constructed
363 by assembling two single width halves into two single width floating
364 point registers which just happen to alias the double width destination
365 register. On some architectures this aliasing can be disabled by a bit
366 in the status register, and the setting of this bit cannot be determined
367 automatically at assemble time. */
368 static int mips_disable_float_construction;
370 /* Non-zero if any .set noreorder directives were used. */
372 static int mips_any_noreorder;
374 /* Non-zero if nops should be inserted when the register referenced in
375 an mfhi/mflo instruction is read in the next two instructions. */
376 static int mips_7000_hilo_fix;
378 /* The size of the small data section. */
379 static unsigned int g_switch_value = 8;
380 /* Whether the -G option was used. */
381 static int g_switch_seen = 0;
386 /* If we can determine in advance that GP optimization won't be
387 possible, we can skip the relaxation stuff that tries to produce
388 GP-relative references. This makes delay slot optimization work
391 This function can only provide a guess, but it seems to work for
392 gcc output. It needs to guess right for gcc, otherwise gcc
393 will put what it thinks is a GP-relative instruction in a branch
396 I don't know if a fix is needed for the SVR4_PIC mode. I've only
397 fixed it for the non-PIC mode. KR 95/04/07 */
398 static int nopic_need_relax PARAMS ((symbolS *, int));
400 /* handle of the OPCODE hash table */
401 static struct hash_control *op_hash = NULL;
403 /* The opcode hash table we use for the mips16. */
404 static struct hash_control *mips16_op_hash = NULL;
406 /* This array holds the chars that always start a comment. If the
407 pre-processor is disabled, these aren't very useful */
408 const char comment_chars[] = "#";
410 /* This array holds the chars that only start a comment at the beginning of
411 a line. If the line seems to have the form '# 123 filename'
412 .line and .file directives will appear in the pre-processed output */
413 /* Note that input_file.c hand checks for '#' at the beginning of the
414 first line of the input file. This is because the compiler outputs
415 #NO_APP at the beginning of its output. */
416 /* Also note that C style comments are always supported. */
417 const char line_comment_chars[] = "#";
419 /* This array holds machine specific line separator characters. */
420 const char line_separator_chars[] = ";";
422 /* Chars that can be used to separate mant from exp in floating point nums */
423 const char EXP_CHARS[] = "eE";
425 /* Chars that mean this number is a floating point constant */
428 const char FLT_CHARS[] = "rRsSfFdDxXpP";
430 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
431 changed in read.c . Ideally it shouldn't have to know about it at all,
432 but nothing is ideal around here.
435 static char *insn_error;
437 static int auto_align = 1;
439 /* When outputting SVR4 PIC code, the assembler needs to know the
440 offset in the stack frame from which to restore the $gp register.
441 This is set by the .cprestore pseudo-op, and saved in this
443 static offsetT mips_cprestore_offset = -1;
445 /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some
446 more optimizations, it can use a register value instead of a memory-saved
447 offset and even an other register than $gp as global pointer. */
448 static offsetT mips_cpreturn_offset = -1;
449 static int mips_cpreturn_register = -1;
450 static int mips_gp_register = GP;
451 static int mips_gprel_offset = 0;
453 /* Whether mips_cprestore_offset has been set in the current function
454 (or whether it has already been warned about, if not). */
455 static int mips_cprestore_valid = 0;
457 /* This is the register which holds the stack frame, as set by the
458 .frame pseudo-op. This is needed to implement .cprestore. */
459 static int mips_frame_reg = SP;
461 /* Whether mips_frame_reg has been set in the current function
462 (or whether it has already been warned about, if not). */
463 static int mips_frame_reg_valid = 0;
465 /* To output NOP instructions correctly, we need to keep information
466 about the previous two instructions. */
468 /* Whether we are optimizing. The default value of 2 means to remove
469 unneeded NOPs and swap branch instructions when possible. A value
470 of 1 means to not swap branches. A value of 0 means to always
472 static int mips_optimize = 2;
474 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
475 equivalent to seeing no -g option at all. */
476 static int mips_debug = 0;
478 /* The previous instruction. */
479 static struct mips_cl_insn prev_insn;
481 /* The instruction before prev_insn. */
482 static struct mips_cl_insn prev_prev_insn;
484 /* If we don't want information for prev_insn or prev_prev_insn, we
485 point the insn_mo field at this dummy integer. */
486 static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 };
488 /* Non-zero if prev_insn is valid. */
489 static int prev_insn_valid;
491 /* The frag for the previous instruction. */
492 static struct frag *prev_insn_frag;
494 /* The offset into prev_insn_frag for the previous instruction. */
495 static long prev_insn_where;
497 /* The reloc type for the previous instruction, if any. */
498 static bfd_reloc_code_real_type prev_insn_reloc_type[3];
500 /* The reloc for the previous instruction, if any. */
501 static fixS *prev_insn_fixp[3];
503 /* Non-zero if the previous instruction was in a delay slot. */
504 static int prev_insn_is_delay_slot;
506 /* Non-zero if the previous instruction was in a .set noreorder. */
507 static int prev_insn_unreordered;
509 /* Non-zero if the previous instruction uses an extend opcode (if
511 static int prev_insn_extended;
513 /* Non-zero if the previous previous instruction was in a .set
515 static int prev_prev_insn_unreordered;
517 /* If this is set, it points to a frag holding nop instructions which
518 were inserted before the start of a noreorder section. If those
519 nops turn out to be unnecessary, the size of the frag can be
521 static fragS *prev_nop_frag;
523 /* The number of nop instructions we created in prev_nop_frag. */
524 static int prev_nop_frag_holds;
526 /* The number of nop instructions that we know we need in
528 static int prev_nop_frag_required;
530 /* The number of instructions we've seen since prev_nop_frag. */
531 static int prev_nop_frag_since;
533 /* For ECOFF and ELF, relocations against symbols are done in two
534 parts, with a HI relocation and a LO relocation. Each relocation
535 has only 16 bits of space to store an addend. This means that in
536 order for the linker to handle carries correctly, it must be able
537 to locate both the HI and the LO relocation. This means that the
538 relocations must appear in order in the relocation table.
540 In order to implement this, we keep track of each unmatched HI
541 relocation. We then sort them so that they immediately precede the
542 corresponding LO relocation. */
547 struct mips_hi_fixup *next;
550 /* The section this fixup is in. */
554 /* The list of unmatched HI relocs. */
556 static struct mips_hi_fixup *mips_hi_fixup_list;
558 /* The frag containing the last explicit relocation operator.
559 Null if explicit relocations have not been used. */
561 static fragS *prev_reloc_op_frag;
563 /* Map normal MIPS register numbers to mips16 register numbers. */
565 #define X ILLEGAL_REG
566 static const int mips32_to_16_reg_map[] =
568 X, X, 2, 3, 4, 5, 6, 7,
569 X, X, X, X, X, X, X, X,
570 0, 1, X, X, X, X, X, X,
571 X, X, X, X, X, X, X, X
575 /* Map mips16 register numbers to normal MIPS register numbers. */
577 static const unsigned int mips16_to_32_reg_map[] =
579 16, 17, 2, 3, 4, 5, 6, 7
582 static int mips_fix_4122_bugs;
584 /* We don't relax branches by default, since this causes us to expand
585 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
586 fail to compute the offset before expanding the macro to the most
587 efficient expansion. */
589 static int mips_relax_branch;
591 /* Since the MIPS does not have multiple forms of PC relative
592 instructions, we do not have to do relaxing as is done on other
593 platforms. However, we do have to handle GP relative addressing
594 correctly, which turns out to be a similar problem.
596 Every macro that refers to a symbol can occur in (at least) two
597 forms, one with GP relative addressing and one without. For
598 example, loading a global variable into a register generally uses
599 a macro instruction like this:
601 If i can be addressed off the GP register (this is true if it is in
602 the .sbss or .sdata section, or if it is known to be smaller than
603 the -G argument) this will generate the following instruction:
605 This instruction will use a GPREL reloc. If i can not be addressed
606 off the GP register, the following instruction sequence will be used:
609 In this case the first instruction will have a HI16 reloc, and the
610 second reloc will have a LO16 reloc. Both relocs will be against
613 The issue here is that we may not know whether i is GP addressable
614 until after we see the instruction that uses it. Therefore, we
615 want to be able to choose the final instruction sequence only at
616 the end of the assembly. This is similar to the way other
617 platforms choose the size of a PC relative instruction only at the
620 When generating position independent code we do not use GP
621 addressing in quite the same way, but the issue still arises as
622 external symbols and local symbols must be handled differently.
624 We handle these issues by actually generating both possible
625 instruction sequences. The longer one is put in a frag_var with
626 type rs_machine_dependent. We encode what to do with the frag in
627 the subtype field. We encode (1) the number of existing bytes to
628 replace, (2) the number of new bytes to use, (3) the offset from
629 the start of the existing bytes to the first reloc we must generate
630 (that is, the offset is applied from the start of the existing
631 bytes after they are replaced by the new bytes, if any), (4) the
632 offset from the start of the existing bytes to the second reloc,
633 (5) whether a third reloc is needed (the third reloc is always four
634 bytes after the second reloc), and (6) whether to warn if this
635 variant is used (this is sometimes needed if .set nomacro or .set
636 noat is in effect). All these numbers are reasonably small.
638 Generating two instruction sequences must be handled carefully to
639 ensure that delay slots are handled correctly. Fortunately, there
640 are a limited number of cases. When the second instruction
641 sequence is generated, append_insn is directed to maintain the
642 existing delay slot information, so it continues to apply to any
643 code after the second instruction sequence. This means that the
644 second instruction sequence must not impose any requirements not
645 required by the first instruction sequence.
647 These variant frags are then handled in functions called by the
648 machine independent code. md_estimate_size_before_relax returns
649 the final size of the frag. md_convert_frag sets up the final form
650 of the frag. tc_gen_reloc adjust the first reloc and adds a second
652 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
656 | (((reloc1) + 64) << 9) \
657 | (((reloc2) + 64) << 2) \
658 | ((reloc3) ? (1 << 1) : 0) \
660 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
661 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
662 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
663 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
664 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
665 #define RELAX_WARN(i) ((i) & 1)
667 /* Branch without likely bit. If label is out of range, we turn:
669 beq reg1, reg2, label
679 with the following opcode replacements:
686 bltzal <-> bgezal (with jal label instead of j label)
688 Even though keeping the delay slot instruction in the delay slot of
689 the branch would be more efficient, it would be very tricky to do
690 correctly, because we'd have to introduce a variable frag *after*
691 the delay slot instruction, and expand that instead. Let's do it
692 the easy way for now, even if the branch-not-taken case now costs
693 one additional instruction. Out-of-range branches are not supposed
694 to be common, anyway.
696 Branch likely. If label is out of range, we turn:
698 beql reg1, reg2, label
699 delay slot (annulled if branch not taken)
708 delay slot (executed only if branch taken)
711 It would be possible to generate a shorter sequence by losing the
712 likely bit, generating something like:
717 delay slot (executed only if branch taken)
729 bltzall -> bgezal (with jal label instead of j label)
730 bgezall -> bltzal (ditto)
733 but it's not clear that it would actually improve performance. */
734 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
737 | ((toofar) ? 1 : 0) \
739 | ((likely) ? 4 : 0) \
740 | ((uncond) ? 8 : 0)))
741 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
742 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
743 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
744 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
745 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
747 /* For mips16 code, we use an entirely different form of relaxation.
748 mips16 supports two versions of most instructions which take
749 immediate values: a small one which takes some small value, and a
750 larger one which takes a 16 bit value. Since branches also follow
751 this pattern, relaxing these values is required.
753 We can assemble both mips16 and normal MIPS code in a single
754 object. Therefore, we need to support this type of relaxation at
755 the same time that we support the relaxation described above. We
756 use the high bit of the subtype field to distinguish these cases.
758 The information we store for this type of relaxation is the
759 argument code found in the opcode file for this relocation, whether
760 the user explicitly requested a small or extended form, and whether
761 the relocation is in a jump or jal delay slot. That tells us the
762 size of the value, and how it should be stored. We also store
763 whether the fragment is considered to be extended or not. We also
764 store whether this is known to be a branch to a different section,
765 whether we have tried to relax this frag yet, and whether we have
766 ever extended a PC relative fragment because of a shift count. */
767 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
770 | ((small) ? 0x100 : 0) \
771 | ((ext) ? 0x200 : 0) \
772 | ((dslot) ? 0x400 : 0) \
773 | ((jal_dslot) ? 0x800 : 0))
774 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
775 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
776 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
777 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
778 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
779 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
780 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
781 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
782 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
783 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
784 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
785 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
787 /* Is the given value a sign-extended 32-bit value? */
788 #define IS_SEXT_32BIT_NUM(x) \
789 (((x) &~ (offsetT) 0x7fffffff) == 0 \
790 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
792 /* Is the given value a sign-extended 16-bit value? */
793 #define IS_SEXT_16BIT_NUM(x) \
794 (((x) &~ (offsetT) 0x7fff) == 0 \
795 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
798 /* Prototypes for static functions. */
801 #define internalError() \
802 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
804 #define internalError() as_fatal (_("MIPS internal Error"));
807 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
809 static inline bfd_boolean reloc_needs_lo_p
810 PARAMS ((bfd_reloc_code_real_type));
811 static inline bfd_boolean fixup_has_matching_lo_p
813 static int insn_uses_reg
814 PARAMS ((struct mips_cl_insn *ip, unsigned int reg,
815 enum mips_regclass class));
816 static int reg_needs_delay
817 PARAMS ((unsigned int));
818 static void mips16_mark_labels
820 static void append_insn
821 PARAMS ((char *place, struct mips_cl_insn * ip, expressionS * p,
822 bfd_reloc_code_real_type *r));
823 static void mips_no_prev_insn
825 static void mips_emit_delays
826 PARAMS ((bfd_boolean));
828 static void macro_build
829 PARAMS ((char *place, int *counter, expressionS * ep, const char *name,
830 const char *fmt, ...));
832 static void macro_build ();
834 static void mips16_macro_build
835 PARAMS ((char *, int *, expressionS *, const char *, const char *, va_list));
836 static void macro_build_jalr
837 PARAMS ((int, expressionS *));
838 static void macro_build_lui
839 PARAMS ((char *place, int *counter, expressionS * ep, int regnum));
840 static void macro_build_ldst_constoffset
841 PARAMS ((char *place, int *counter, expressionS * ep, const char *op,
842 int valreg, int breg));
844 PARAMS ((int *counter, int reg, int unsignedp));
845 static void check_absolute_expr
846 PARAMS ((struct mips_cl_insn * ip, expressionS *));
847 static void load_register
848 PARAMS ((int *, int, expressionS *, int));
849 static void load_address
850 PARAMS ((int *, int, expressionS *, int *));
851 static void move_register
852 PARAMS ((int *, int, int));
854 PARAMS ((struct mips_cl_insn * ip));
855 static void mips16_macro
856 PARAMS ((struct mips_cl_insn * ip));
857 #ifdef LOSING_COMPILER
859 PARAMS ((struct mips_cl_insn * ip));
862 PARAMS ((char *str, struct mips_cl_insn * ip));
863 static void mips16_ip
864 PARAMS ((char *str, struct mips_cl_insn * ip));
865 static void mips16_immed
866 PARAMS ((char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean,
867 bfd_boolean, unsigned long *, bfd_boolean *, unsigned short *));
868 static bfd_boolean parse_relocation
869 PARAMS ((char **, bfd_reloc_code_real_type *));
870 static size_t my_getSmallExpression
871 PARAMS ((expressionS *, bfd_reloc_code_real_type *, char *));
872 static void my_getExpression
873 PARAMS ((expressionS *, char *));
875 static int support_64bit_objects
878 static void mips_set_option_string
879 PARAMS ((const char **, const char *));
880 static symbolS *get_symbol
882 static void mips_align
883 PARAMS ((int to, int fill, symbolS *label));
886 static void s_change_sec
888 static void s_change_section
892 static void s_float_cons
894 static void s_mips_globl
898 static void s_mipsset
900 static void s_abicalls
904 static void s_cpsetup
906 static void s_cplocal
908 static void s_cprestore
910 static void s_cpreturn
912 static void s_gpvalue
916 static void s_gpdword
922 static void md_obj_begin
924 static void md_obj_end
926 static long get_number
928 static void s_mips_ent
930 static void s_mips_end
932 static void s_mips_frame
934 static void s_mips_mask
936 static void s_mips_stab
938 static void s_mips_weakext
940 static void s_mips_file
942 static void s_mips_loc
944 static bfd_boolean pic_need_relax
945 PARAMS ((symbolS *, asection *));
946 static int mips16_extended_frag
947 PARAMS ((fragS *, asection *, long));
948 static int relaxed_branch_length (fragS *, asection *, int);
949 static int validate_mips_insn
950 PARAMS ((const struct mips_opcode *));
952 PARAMS ((FILE *, const char *, int *, int *));
954 static int mips_need_elf_addend_fixup
958 /* Table and functions used to map between CPU/ISA names, and
959 ISA levels, and CPU numbers. */
963 const char *name; /* CPU or ISA name. */
964 int is_isa; /* Is this an ISA? (If 0, a CPU.) */
965 int isa; /* ISA level. */
966 int cpu; /* CPU number (default CPU if ISA). */
969 static void mips_set_architecture
970 PARAMS ((const struct mips_cpu_info *));
971 static void mips_set_tune
972 PARAMS ((const struct mips_cpu_info *));
973 static bfd_boolean mips_strict_matching_cpu_name_p
974 PARAMS ((const char *, const char *));
975 static bfd_boolean mips_matching_cpu_name_p
976 PARAMS ((const char *, const char *));
977 static const struct mips_cpu_info *mips_parse_cpu
978 PARAMS ((const char *, const char *));
979 static const struct mips_cpu_info *mips_cpu_info_from_isa
984 The following pseudo-ops from the Kane and Heinrich MIPS book
985 should be defined here, but are currently unsupported: .alias,
986 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
988 The following pseudo-ops from the Kane and Heinrich MIPS book are
989 specific to the type of debugging information being generated, and
990 should be defined by the object format: .aent, .begin, .bend,
991 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
994 The following pseudo-ops from the Kane and Heinrich MIPS book are
995 not MIPS CPU specific, but are also not specific to the object file
996 format. This file is probably the best place to define them, but
997 they are not currently supported: .asm0, .endr, .lab, .repeat,
1000 static const pseudo_typeS mips_pseudo_table[] =
1002 /* MIPS specific pseudo-ops. */
1003 {"option", s_option, 0},
1004 {"set", s_mipsset, 0},
1005 {"rdata", s_change_sec, 'r'},
1006 {"sdata", s_change_sec, 's'},
1007 {"livereg", s_ignore, 0},
1008 {"abicalls", s_abicalls, 0},
1009 {"cpload", s_cpload, 0},
1010 {"cpsetup", s_cpsetup, 0},
1011 {"cplocal", s_cplocal, 0},
1012 {"cprestore", s_cprestore, 0},
1013 {"cpreturn", s_cpreturn, 0},
1014 {"gpvalue", s_gpvalue, 0},
1015 {"gpword", s_gpword, 0},
1016 {"gpdword", s_gpdword, 0},
1017 {"cpadd", s_cpadd, 0},
1018 {"insn", s_insn, 0},
1020 /* Relatively generic pseudo-ops that happen to be used on MIPS
1022 {"asciiz", stringer, 1},
1023 {"bss", s_change_sec, 'b'},
1025 {"half", s_cons, 1},
1026 {"dword", s_cons, 3},
1027 {"weakext", s_mips_weakext, 0},
1029 /* These pseudo-ops are defined in read.c, but must be overridden
1030 here for one reason or another. */
1031 {"align", s_align, 0},
1032 {"byte", s_cons, 0},
1033 {"data", s_change_sec, 'd'},
1034 {"double", s_float_cons, 'd'},
1035 {"float", s_float_cons, 'f'},
1036 {"globl", s_mips_globl, 0},
1037 {"global", s_mips_globl, 0},
1038 {"hword", s_cons, 1},
1040 {"long", s_cons, 2},
1041 {"octa", s_cons, 4},
1042 {"quad", s_cons, 3},
1043 {"section", s_change_section, 0},
1044 {"short", s_cons, 1},
1045 {"single", s_float_cons, 'f'},
1046 {"stabn", s_mips_stab, 'n'},
1047 {"text", s_change_sec, 't'},
1048 {"word", s_cons, 2},
1050 { "extern", ecoff_directive_extern, 0},
1055 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1057 /* These pseudo-ops should be defined by the object file format.
1058 However, a.out doesn't support them, so we have versions here. */
1059 {"aent", s_mips_ent, 1},
1060 {"bgnb", s_ignore, 0},
1061 {"end", s_mips_end, 0},
1062 {"endb", s_ignore, 0},
1063 {"ent", s_mips_ent, 0},
1064 {"file", s_mips_file, 0},
1065 {"fmask", s_mips_mask, 'F'},
1066 {"frame", s_mips_frame, 0},
1067 {"loc", s_mips_loc, 0},
1068 {"mask", s_mips_mask, 'R'},
1069 {"verstamp", s_ignore, 0},
1073 extern void pop_insert PARAMS ((const pseudo_typeS *));
1078 pop_insert (mips_pseudo_table);
1079 if (! ECOFF_DEBUGGING)
1080 pop_insert (mips_nonecoff_pseudo_table);
1083 /* Symbols labelling the current insn. */
1085 struct insn_label_list
1087 struct insn_label_list *next;
1091 static struct insn_label_list *insn_labels;
1092 static struct insn_label_list *free_insn_labels;
1094 static void mips_clear_insn_labels PARAMS ((void));
1097 mips_clear_insn_labels ()
1099 register struct insn_label_list **pl;
1101 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1107 static char *expr_end;
1109 /* Expressions which appear in instructions. These are set by
1112 static expressionS imm_expr;
1113 static expressionS offset_expr;
1115 /* Relocs associated with imm_expr and offset_expr. */
1117 static bfd_reloc_code_real_type imm_reloc[3]
1118 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1119 static bfd_reloc_code_real_type offset_reloc[3]
1120 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1122 /* These are set by mips16_ip if an explicit extension is used. */
1124 static bfd_boolean mips16_small, mips16_ext;
1127 /* The pdr segment for per procedure frame/regmask info. Not used for
1130 static segT pdr_seg;
1133 /* The default target format to use. */
1136 mips_target_format ()
1138 switch (OUTPUT_FLAVOR)
1140 case bfd_target_aout_flavour:
1141 return target_big_endian ? "a.out-mips-big" : "a.out-mips-little";
1142 case bfd_target_ecoff_flavour:
1143 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1144 case bfd_target_coff_flavour:
1146 case bfd_target_elf_flavour:
1148 /* This is traditional mips. */
1149 return (target_big_endian
1150 ? (HAVE_64BIT_OBJECTS
1151 ? "elf64-tradbigmips"
1153 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1154 : (HAVE_64BIT_OBJECTS
1155 ? "elf64-tradlittlemips"
1157 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1159 return (target_big_endian
1160 ? (HAVE_64BIT_OBJECTS
1163 ? "elf32-nbigmips" : "elf32-bigmips"))
1164 : (HAVE_64BIT_OBJECTS
1165 ? "elf64-littlemips"
1167 ? "elf32-nlittlemips" : "elf32-littlemips")));
1175 /* This function is called once, at assembler startup time. It should
1176 set up all the tables, etc. that the MD part of the assembler will need. */
1181 register const char *retval = NULL;
1185 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_arch))
1186 as_warn (_("Could not set architecture and machine"));
1188 op_hash = hash_new ();
1190 for (i = 0; i < NUMOPCODES;)
1192 const char *name = mips_opcodes[i].name;
1194 retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]);
1197 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1198 mips_opcodes[i].name, retval);
1199 /* Probably a memory allocation problem? Give up now. */
1200 as_fatal (_("Broken assembler. No assembly attempted."));
1204 if (mips_opcodes[i].pinfo != INSN_MACRO)
1206 if (!validate_mips_insn (&mips_opcodes[i]))
1211 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1214 mips16_op_hash = hash_new ();
1217 while (i < bfd_mips16_num_opcodes)
1219 const char *name = mips16_opcodes[i].name;
1221 retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]);
1223 as_fatal (_("internal: can't hash `%s': %s"),
1224 mips16_opcodes[i].name, retval);
1227 if (mips16_opcodes[i].pinfo != INSN_MACRO
1228 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1229 != mips16_opcodes[i].match))
1231 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1232 mips16_opcodes[i].name, mips16_opcodes[i].args);
1237 while (i < bfd_mips16_num_opcodes
1238 && strcmp (mips16_opcodes[i].name, name) == 0);
1242 as_fatal (_("Broken assembler. No assembly attempted."));
1244 /* We add all the general register names to the symbol table. This
1245 helps us detect invalid uses of them. */
1246 for (i = 0; i < 32; i++)
1250 sprintf (buf, "$%d", i);
1251 symbol_table_insert (symbol_new (buf, reg_section, i,
1252 &zero_address_frag));
1254 symbol_table_insert (symbol_new ("$ra", reg_section, RA,
1255 &zero_address_frag));
1256 symbol_table_insert (symbol_new ("$fp", reg_section, FP,
1257 &zero_address_frag));
1258 symbol_table_insert (symbol_new ("$sp", reg_section, SP,
1259 &zero_address_frag));
1260 symbol_table_insert (symbol_new ("$gp", reg_section, GP,
1261 &zero_address_frag));
1262 symbol_table_insert (symbol_new ("$at", reg_section, AT,
1263 &zero_address_frag));
1264 symbol_table_insert (symbol_new ("$kt0", reg_section, KT0,
1265 &zero_address_frag));
1266 symbol_table_insert (symbol_new ("$kt1", reg_section, KT1,
1267 &zero_address_frag));
1268 symbol_table_insert (symbol_new ("$zero", reg_section, ZERO,
1269 &zero_address_frag));
1270 symbol_table_insert (symbol_new ("$pc", reg_section, -1,
1271 &zero_address_frag));
1273 /* If we don't add these register names to the symbol table, they
1274 may end up being added as regular symbols by operand(), and then
1275 make it to the object file as undefined in case they're not
1276 regarded as local symbols. They're local in o32, since `$' is a
1277 local symbol prefix, but not in n32 or n64. */
1278 for (i = 0; i < 8; i++)
1282 sprintf (buf, "$fcc%i", i);
1283 symbol_table_insert (symbol_new (buf, reg_section, -1,
1284 &zero_address_frag));
1287 mips_no_prev_insn (FALSE);
1290 mips_cprmask[0] = 0;
1291 mips_cprmask[1] = 0;
1292 mips_cprmask[2] = 0;
1293 mips_cprmask[3] = 0;
1295 /* set the default alignment for the text section (2**2) */
1296 record_alignment (text_section, 2);
1298 if (USE_GLOBAL_POINTER_OPT)
1299 bfd_set_gp_size (stdoutput, g_switch_value);
1301 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1303 /* On a native system, sections must be aligned to 16 byte
1304 boundaries. When configured for an embedded ELF target, we
1306 if (strcmp (TARGET_OS, "elf") != 0)
1308 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
1309 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
1310 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
1313 /* Create a .reginfo section for register masks and a .mdebug
1314 section for debugging information. */
1322 subseg = now_subseg;
1324 /* The ABI says this section should be loaded so that the
1325 running program can access it. However, we don't load it
1326 if we are configured for an embedded target */
1327 flags = SEC_READONLY | SEC_DATA;
1328 if (strcmp (TARGET_OS, "elf") != 0)
1329 flags |= SEC_ALLOC | SEC_LOAD;
1331 if (mips_abi != N64_ABI)
1333 sec = subseg_new (".reginfo", (subsegT) 0);
1335 bfd_set_section_flags (stdoutput, sec, flags);
1336 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
1339 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
1344 /* The 64-bit ABI uses a .MIPS.options section rather than
1345 .reginfo section. */
1346 sec = subseg_new (".MIPS.options", (subsegT) 0);
1347 bfd_set_section_flags (stdoutput, sec, flags);
1348 bfd_set_section_alignment (stdoutput, sec, 3);
1351 /* Set up the option header. */
1353 Elf_Internal_Options opthdr;
1356 opthdr.kind = ODK_REGINFO;
1357 opthdr.size = (sizeof (Elf_External_Options)
1358 + sizeof (Elf64_External_RegInfo));
1361 f = frag_more (sizeof (Elf_External_Options));
1362 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
1363 (Elf_External_Options *) f);
1365 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
1370 if (ECOFF_DEBUGGING)
1372 sec = subseg_new (".mdebug", (subsegT) 0);
1373 (void) bfd_set_section_flags (stdoutput, sec,
1374 SEC_HAS_CONTENTS | SEC_READONLY);
1375 (void) bfd_set_section_alignment (stdoutput, sec, 2);
1378 else if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1380 pdr_seg = subseg_new (".pdr", (subsegT) 0);
1381 (void) bfd_set_section_flags (stdoutput, pdr_seg,
1382 SEC_READONLY | SEC_RELOC
1384 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
1388 subseg_set (seg, subseg);
1392 if (! ECOFF_DEBUGGING)
1399 if (! ECOFF_DEBUGGING)
1407 struct mips_cl_insn insn;
1408 bfd_reloc_code_real_type unused_reloc[3]
1409 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1411 imm_expr.X_op = O_absent;
1412 offset_expr.X_op = O_absent;
1413 imm_reloc[0] = BFD_RELOC_UNUSED;
1414 imm_reloc[1] = BFD_RELOC_UNUSED;
1415 imm_reloc[2] = BFD_RELOC_UNUSED;
1416 offset_reloc[0] = BFD_RELOC_UNUSED;
1417 offset_reloc[1] = BFD_RELOC_UNUSED;
1418 offset_reloc[2] = BFD_RELOC_UNUSED;
1420 if (mips_opts.mips16)
1421 mips16_ip (str, &insn);
1424 mips_ip (str, &insn);
1425 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1426 str, insn.insn_opcode));
1431 as_bad ("%s `%s'", insn_error, str);
1435 if (insn.insn_mo->pinfo == INSN_MACRO)
1437 if (mips_opts.mips16)
1438 mips16_macro (&insn);
1444 if (imm_expr.X_op != O_absent)
1445 append_insn (NULL, &insn, &imm_expr, imm_reloc);
1446 else if (offset_expr.X_op != O_absent)
1447 append_insn (NULL, &insn, &offset_expr, offset_reloc);
1449 append_insn (NULL, &insn, NULL, unused_reloc);
1453 /* Return true if the given relocation might need a matching %lo().
1454 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1455 applied to local symbols. */
1457 static inline bfd_boolean
1458 reloc_needs_lo_p (reloc)
1459 bfd_reloc_code_real_type reloc;
1461 return (reloc == BFD_RELOC_HI16_S
1462 || reloc == BFD_RELOC_MIPS_GOT16);
1465 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1468 static inline bfd_boolean
1469 fixup_has_matching_lo_p (fixp)
1472 return (fixp->fx_next != NULL
1473 && fixp->fx_next->fx_r_type == BFD_RELOC_LO16
1474 && fixp->fx_addsy == fixp->fx_next->fx_addsy
1475 && fixp->fx_offset == fixp->fx_next->fx_offset);
1478 /* See whether instruction IP reads register REG. CLASS is the type
1482 insn_uses_reg (ip, reg, class)
1483 struct mips_cl_insn *ip;
1485 enum mips_regclass class;
1487 if (class == MIPS16_REG)
1489 assert (mips_opts.mips16);
1490 reg = mips16_to_32_reg_map[reg];
1491 class = MIPS_GR_REG;
1494 /* Don't report on general register ZERO, since it never changes. */
1495 if (class == MIPS_GR_REG && reg == ZERO)
1498 if (class == MIPS_FP_REG)
1500 assert (! mips_opts.mips16);
1501 /* If we are called with either $f0 or $f1, we must check $f0.
1502 This is not optimal, because it will introduce an unnecessary
1503 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1504 need to distinguish reading both $f0 and $f1 or just one of
1505 them. Note that we don't have to check the other way,
1506 because there is no instruction that sets both $f0 and $f1
1507 and requires a delay. */
1508 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
1509 && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1)
1510 == (reg &~ (unsigned) 1)))
1512 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
1513 && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1)
1514 == (reg &~ (unsigned) 1)))
1517 else if (! mips_opts.mips16)
1519 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
1520 && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg)
1522 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
1523 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg)
1528 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
1529 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX)
1530 & MIPS16OP_MASK_RX)]
1533 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
1534 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY)
1535 & MIPS16OP_MASK_RY)]
1538 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
1539 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
1540 & MIPS16OP_MASK_MOVE32Z)]
1543 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
1545 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
1547 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
1549 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
1550 && ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
1551 & MIPS16OP_MASK_REGR32) == reg)
1558 /* This function returns true if modifying a register requires a
1562 reg_needs_delay (reg)
1565 unsigned long prev_pinfo;
1567 prev_pinfo = prev_insn.insn_mo->pinfo;
1568 if (! mips_opts.noreorder
1569 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1570 && ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1571 || (! gpr_interlocks
1572 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
1574 /* A load from a coprocessor or from memory. All load
1575 delays delay the use of general register rt for one
1576 instruction on the r3000. The r6000 and r4000 use
1578 /* Itbl support may require additional care here. */
1579 know (prev_pinfo & INSN_WRITE_GPR_T);
1580 if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT))
1587 /* Mark instruction labels in mips16 mode. This permits the linker to
1588 handle them specially, such as generating jalx instructions when
1589 needed. We also make them odd for the duration of the assembly, in
1590 order to generate the right sort of code. We will make them even
1591 in the adjust_symtab routine, while leaving them marked. This is
1592 convenient for the debugger and the disassembler. The linker knows
1593 to make them odd again. */
1596 mips16_mark_labels ()
1598 if (mips_opts.mips16)
1600 struct insn_label_list *l;
1603 for (l = insn_labels; l != NULL; l = l->next)
1606 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1607 S_SET_OTHER (l->label, STO_MIPS16);
1609 val = S_GET_VALUE (l->label);
1611 S_SET_VALUE (l->label, val + 1);
1616 /* Output an instruction. PLACE is where to put the instruction; if
1617 it is NULL, this uses frag_more to get room. IP is the instruction
1618 information. ADDRESS_EXPR is an operand of the instruction to be
1619 used with RELOC_TYPE. */
1622 append_insn (place, ip, address_expr, reloc_type)
1624 struct mips_cl_insn *ip;
1625 expressionS *address_expr;
1626 bfd_reloc_code_real_type *reloc_type;
1628 register unsigned long prev_pinfo, pinfo;
1633 /* Mark instruction labels in mips16 mode. */
1634 mips16_mark_labels ();
1636 prev_pinfo = prev_insn.insn_mo->pinfo;
1637 pinfo = ip->insn_mo->pinfo;
1639 if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL))
1643 /* If the previous insn required any delay slots, see if we need
1644 to insert a NOP or two. There are eight kinds of possible
1645 hazards, of which an instruction can have at most one type.
1646 (1) a load from memory delay
1647 (2) a load from a coprocessor delay
1648 (3) an unconditional branch delay
1649 (4) a conditional branch delay
1650 (5) a move to coprocessor register delay
1651 (6) a load coprocessor register from memory delay
1652 (7) a coprocessor condition code delay
1653 (8) a HI/LO special register delay
1655 There are a lot of optimizations we could do that we don't.
1656 In particular, we do not, in general, reorder instructions.
1657 If you use gcc with optimization, it will reorder
1658 instructions and generally do much more optimization then we
1659 do here; repeating all that work in the assembler would only
1660 benefit hand written assembly code, and does not seem worth
1663 /* This is how a NOP is emitted. */
1664 #define emit_nop() \
1666 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1667 : md_number_to_chars (frag_more (4), 0, 4))
1669 /* The previous insn might require a delay slot, depending upon
1670 the contents of the current insn. */
1671 if (! mips_opts.mips16
1672 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1673 && (((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1674 && ! cop_interlocks)
1675 || (! gpr_interlocks
1676 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
1678 /* A load from a coprocessor or from memory. All load
1679 delays delay the use of general register rt for one
1680 instruction on the r3000. The r6000 and r4000 use
1682 /* Itbl support may require additional care here. */
1683 know (prev_pinfo & INSN_WRITE_GPR_T);
1684 if (mips_optimize == 0
1685 || insn_uses_reg (ip,
1686 ((prev_insn.insn_opcode >> OP_SH_RT)
1691 else if (! mips_opts.mips16
1692 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1693 && (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
1694 && ! cop_interlocks)
1695 || (mips_opts.isa == ISA_MIPS1
1696 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))))
1698 /* A generic coprocessor delay. The previous instruction
1699 modified a coprocessor general or control register. If
1700 it modified a control register, we need to avoid any
1701 coprocessor instruction (this is probably not always
1702 required, but it sometimes is). If it modified a general
1703 register, we avoid using that register.
1705 On the r6000 and r4000 loading a coprocessor register
1706 from memory is interlocked, and does not require a delay.
1708 This case is not handled very well. There is no special
1709 knowledge of CP0 handling, and the coprocessors other
1710 than the floating point unit are not distinguished at
1712 /* Itbl support may require additional care here. FIXME!
1713 Need to modify this to include knowledge about
1714 user specified delays! */
1715 if (prev_pinfo & INSN_WRITE_FPR_T)
1717 if (mips_optimize == 0
1718 || insn_uses_reg (ip,
1719 ((prev_insn.insn_opcode >> OP_SH_FT)
1724 else if (prev_pinfo & INSN_WRITE_FPR_S)
1726 if (mips_optimize == 0
1727 || insn_uses_reg (ip,
1728 ((prev_insn.insn_opcode >> OP_SH_FS)
1735 /* We don't know exactly what the previous instruction
1736 does. If the current instruction uses a coprocessor
1737 register, we must insert a NOP. If previous
1738 instruction may set the condition codes, and the
1739 current instruction uses them, we must insert two
1741 /* Itbl support may require additional care here. */
1742 if (mips_optimize == 0
1743 || ((prev_pinfo & INSN_WRITE_COND_CODE)
1744 && (pinfo & INSN_READ_COND_CODE)))
1746 else if (pinfo & INSN_COP)
1750 else if (! mips_opts.mips16
1751 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1752 && (prev_pinfo & INSN_WRITE_COND_CODE)
1753 && ! cop_interlocks)
1755 /* The previous instruction sets the coprocessor condition
1756 codes, but does not require a general coprocessor delay
1757 (this means it is a floating point comparison
1758 instruction). If this instruction uses the condition
1759 codes, we need to insert a single NOP. */
1760 /* Itbl support may require additional care here. */
1761 if (mips_optimize == 0
1762 || (pinfo & INSN_READ_COND_CODE))
1766 /* If we're fixing up mfhi/mflo for the r7000 and the
1767 previous insn was an mfhi/mflo and the current insn
1768 reads the register that the mfhi/mflo wrote to, then
1771 else if (mips_7000_hilo_fix
1772 && MF_HILO_INSN (prev_pinfo)
1773 && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD)
1780 /* If we're fixing up mfhi/mflo for the r7000 and the
1781 2nd previous insn was an mfhi/mflo and the current insn
1782 reads the register that the mfhi/mflo wrote to, then
1785 else if (mips_7000_hilo_fix
1786 && MF_HILO_INSN (prev_prev_insn.insn_opcode)
1787 && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD)
1795 else if (prev_pinfo & INSN_READ_LO)
1797 /* The previous instruction reads the LO register; if the
1798 current instruction writes to the LO register, we must
1799 insert two NOPS. Some newer processors have interlocks.
1800 Also the tx39's multiply instructions can be exectuted
1801 immediatly after a read from HI/LO (without the delay),
1802 though the tx39's divide insns still do require the
1804 if (! (hilo_interlocks
1805 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
1806 && (mips_optimize == 0
1807 || (pinfo & INSN_WRITE_LO)))
1809 /* Most mips16 branch insns don't have a delay slot.
1810 If a read from LO is immediately followed by a branch
1811 to a write to LO we have a read followed by a write
1812 less than 2 insns away. We assume the target of
1813 a branch might be a write to LO, and insert a nop
1814 between a read and an immediately following branch. */
1815 else if (mips_opts.mips16
1816 && (mips_optimize == 0
1817 || (pinfo & MIPS16_INSN_BRANCH)))
1820 else if (prev_insn.insn_mo->pinfo & INSN_READ_HI)
1822 /* The previous instruction reads the HI register; if the
1823 current instruction writes to the HI register, we must
1824 insert a NOP. Some newer processors have interlocks.
1825 Also the note tx39's multiply above. */
1826 if (! (hilo_interlocks
1827 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
1828 && (mips_optimize == 0
1829 || (pinfo & INSN_WRITE_HI)))
1831 /* Most mips16 branch insns don't have a delay slot.
1832 If a read from HI is immediately followed by a branch
1833 to a write to HI we have a read followed by a write
1834 less than 2 insns away. We assume the target of
1835 a branch might be a write to HI, and insert a nop
1836 between a read and an immediately following branch. */
1837 else if (mips_opts.mips16
1838 && (mips_optimize == 0
1839 || (pinfo & MIPS16_INSN_BRANCH)))
1843 /* If the previous instruction was in a noreorder section, then
1844 we don't want to insert the nop after all. */
1845 /* Itbl support may require additional care here. */
1846 if (prev_insn_unreordered)
1849 /* There are two cases which require two intervening
1850 instructions: 1) setting the condition codes using a move to
1851 coprocessor instruction which requires a general coprocessor
1852 delay and then reading the condition codes 2) reading the HI
1853 or LO register and then writing to it (except on processors
1854 which have interlocks). If we are not already emitting a NOP
1855 instruction, we must check for these cases compared to the
1856 instruction previous to the previous instruction. */
1857 if ((! mips_opts.mips16
1858 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1859 && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
1860 && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
1861 && (pinfo & INSN_READ_COND_CODE)
1862 && ! cop_interlocks)
1863 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
1864 && (pinfo & INSN_WRITE_LO)
1865 && ! (hilo_interlocks
1866 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))))
1867 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
1868 && (pinfo & INSN_WRITE_HI)
1869 && ! (hilo_interlocks
1870 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))))
1875 if (prev_prev_insn_unreordered)
1878 if (prev_prev_nop && nops == 0)
1881 if (mips_fix_4122_bugs && prev_insn.insn_mo->name)
1883 /* We're out of bits in pinfo, so we must resort to string
1884 ops here. Shortcuts are selected based on opcodes being
1885 limited to the VR4122 instruction set. */
1887 const char *pn = prev_insn.insn_mo->name;
1888 const char *tn = ip->insn_mo->name;
1889 if (strncmp(pn, "macc", 4) == 0
1890 || strncmp(pn, "dmacc", 5) == 0)
1892 /* Errata 21 - [D]DIV[U] after [D]MACC */
1893 if (strstr (tn, "div"))
1898 /* Errata 23 - Continuous DMULT[U]/DMACC instructions */
1899 if (pn[0] == 'd' /* dmacc */
1900 && (strncmp(tn, "dmult", 5) == 0
1901 || strncmp(tn, "dmacc", 5) == 0))
1906 /* Errata 24 - MT{LO,HI} after [D]MACC */
1907 if (strcmp (tn, "mtlo") == 0
1908 || strcmp (tn, "mthi") == 0)
1914 else if (strncmp(pn, "dmult", 5) == 0
1915 && (strncmp(tn, "dmult", 5) == 0
1916 || strncmp(tn, "dmacc", 5) == 0))
1918 /* Here is the rest of errata 23. */
1921 if (nops < min_nops)
1925 /* If we are being given a nop instruction, don't bother with
1926 one of the nops we would otherwise output. This will only
1927 happen when a nop instruction is used with mips_optimize set
1930 && ! mips_opts.noreorder
1931 && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0))
1934 /* Now emit the right number of NOP instructions. */
1935 if (nops > 0 && ! mips_opts.noreorder)
1938 unsigned long old_frag_offset;
1940 struct insn_label_list *l;
1942 old_frag = frag_now;
1943 old_frag_offset = frag_now_fix ();
1945 for (i = 0; i < nops; i++)
1950 listing_prev_line ();
1951 /* We may be at the start of a variant frag. In case we
1952 are, make sure there is enough space for the frag
1953 after the frags created by listing_prev_line. The
1954 argument to frag_grow here must be at least as large
1955 as the argument to all other calls to frag_grow in
1956 this file. We don't have to worry about being in the
1957 middle of a variant frag, because the variants insert
1958 all needed nop instructions themselves. */
1962 for (l = insn_labels; l != NULL; l = l->next)
1966 assert (S_GET_SEGMENT (l->label) == now_seg);
1967 symbol_set_frag (l->label, frag_now);
1968 val = (valueT) frag_now_fix ();
1969 /* mips16 text labels are stored as odd. */
1970 if (mips_opts.mips16)
1972 S_SET_VALUE (l->label, val);
1975 #ifndef NO_ECOFF_DEBUGGING
1976 if (ECOFF_DEBUGGING)
1977 ecoff_fix_loc (old_frag, old_frag_offset);
1980 else if (prev_nop_frag != NULL)
1982 /* We have a frag holding nops we may be able to remove. If
1983 we don't need any nops, we can decrease the size of
1984 prev_nop_frag by the size of one instruction. If we do
1985 need some nops, we count them in prev_nops_required. */
1986 if (prev_nop_frag_since == 0)
1990 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1991 --prev_nop_frag_holds;
1994 prev_nop_frag_required += nops;
1998 if (prev_prev_nop == 0)
2000 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
2001 --prev_nop_frag_holds;
2004 ++prev_nop_frag_required;
2007 if (prev_nop_frag_holds <= prev_nop_frag_required)
2008 prev_nop_frag = NULL;
2010 ++prev_nop_frag_since;
2012 /* Sanity check: by the time we reach the second instruction
2013 after prev_nop_frag, we should have used up all the nops
2014 one way or another. */
2015 assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL);
2021 && *reloc_type == BFD_RELOC_16_PCREL_S2
2022 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
2023 || pinfo & INSN_COND_BRANCH_LIKELY)
2024 && mips_relax_branch
2025 /* Don't try branch relaxation within .set nomacro, or within
2026 .set noat if we use $at for PIC computations. If it turns
2027 out that the branch was out-of-range, we'll get an error. */
2028 && !mips_opts.warn_about_macros
2029 && !(mips_opts.noat && mips_pic != NO_PIC)
2030 && !mips_opts.mips16)
2032 f = frag_var (rs_machine_dependent,
2033 relaxed_branch_length
2035 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
2036 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4,
2038 (pinfo & INSN_UNCOND_BRANCH_DELAY,
2039 pinfo & INSN_COND_BRANCH_LIKELY,
2040 pinfo & INSN_WRITE_GPR_31,
2042 address_expr->X_add_symbol,
2043 address_expr->X_add_number,
2045 *reloc_type = BFD_RELOC_UNUSED;
2047 else if (*reloc_type > BFD_RELOC_UNUSED)
2049 /* We need to set up a variant frag. */
2050 assert (mips_opts.mips16 && address_expr != NULL);
2051 f = frag_var (rs_machine_dependent, 4, 0,
2052 RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED,
2053 mips16_small, mips16_ext,
2055 & INSN_UNCOND_BRANCH_DELAY),
2056 (*prev_insn_reloc_type
2057 == BFD_RELOC_MIPS16_JMP)),
2058 make_expr_symbol (address_expr), 0, NULL);
2060 else if (place != NULL)
2062 else if (mips_opts.mips16
2064 && *reloc_type != BFD_RELOC_MIPS16_JMP)
2066 /* Make sure there is enough room to swap this instruction with
2067 a following jump instruction. */
2073 if (mips_opts.mips16
2074 && mips_opts.noreorder
2075 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2076 as_warn (_("extended instruction in delay slot"));
2081 fixp[0] = fixp[1] = fixp[2] = NULL;
2082 if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED)
2084 if (address_expr->X_op == O_constant)
2088 switch (*reloc_type)
2091 ip->insn_opcode |= address_expr->X_add_number;
2094 case BFD_RELOC_MIPS_HIGHEST:
2095 tmp = (address_expr->X_add_number + 0x800080008000) >> 16;
2097 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2100 case BFD_RELOC_MIPS_HIGHER:
2101 tmp = (address_expr->X_add_number + 0x80008000) >> 16;
2102 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2105 case BFD_RELOC_HI16_S:
2106 ip->insn_opcode |= ((address_expr->X_add_number + 0x8000)
2110 case BFD_RELOC_HI16:
2111 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
2114 case BFD_RELOC_LO16:
2115 case BFD_RELOC_MIPS_GOT_DISP:
2116 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
2119 case BFD_RELOC_MIPS_JMP:
2120 if ((address_expr->X_add_number & 3) != 0)
2121 as_bad (_("jump to misaligned address (0x%lx)"),
2122 (unsigned long) address_expr->X_add_number);
2123 if (address_expr->X_add_number & ~0xfffffff)
2124 as_bad (_("jump address range overflow (0x%lx)"),
2125 (unsigned long) address_expr->X_add_number);
2126 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
2129 case BFD_RELOC_MIPS16_JMP:
2130 if ((address_expr->X_add_number & 3) != 0)
2131 as_bad (_("jump to misaligned address (0x%lx)"),
2132 (unsigned long) address_expr->X_add_number);
2133 if (address_expr->X_add_number & ~0xfffffff)
2134 as_bad (_("jump address range overflow (0x%lx)"),
2135 (unsigned long) address_expr->X_add_number);
2137 (((address_expr->X_add_number & 0x7c0000) << 3)
2138 | ((address_expr->X_add_number & 0xf800000) >> 7)
2139 | ((address_expr->X_add_number & 0x3fffc) >> 2));
2142 case BFD_RELOC_16_PCREL_S2:
2152 /* Don't generate a reloc if we are writing into a variant frag. */
2155 fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal, 4,
2157 *reloc_type == BFD_RELOC_16_PCREL_S2,
2160 /* These relocations can have an addend that won't fit in
2161 4 octets for 64bit assembly. */
2162 if (HAVE_64BIT_GPRS &&
2163 (*reloc_type == BFD_RELOC_16
2164 || *reloc_type == BFD_RELOC_32
2165 || *reloc_type == BFD_RELOC_MIPS_JMP
2166 || *reloc_type == BFD_RELOC_HI16_S
2167 || *reloc_type == BFD_RELOC_LO16
2168 || *reloc_type == BFD_RELOC_GPREL16
2169 || *reloc_type == BFD_RELOC_MIPS_LITERAL
2170 || *reloc_type == BFD_RELOC_GPREL32
2171 || *reloc_type == BFD_RELOC_64
2172 || *reloc_type == BFD_RELOC_CTOR
2173 || *reloc_type == BFD_RELOC_MIPS_SUB
2174 || *reloc_type == BFD_RELOC_MIPS_HIGHEST
2175 || *reloc_type == BFD_RELOC_MIPS_HIGHER
2176 || *reloc_type == BFD_RELOC_MIPS_SCN_DISP
2177 || *reloc_type == BFD_RELOC_MIPS_REL16
2178 || *reloc_type == BFD_RELOC_MIPS_RELGOT))
2179 fixp[0]->fx_no_overflow = 1;
2181 if (reloc_needs_lo_p (*reloc_type))
2183 struct mips_hi_fixup *hi_fixup;
2185 /* Reuse the last entry if it already has a matching %lo. */
2186 hi_fixup = mips_hi_fixup_list;
2188 || !fixup_has_matching_lo_p (hi_fixup->fixp))
2190 hi_fixup = ((struct mips_hi_fixup *)
2191 xmalloc (sizeof (struct mips_hi_fixup)));
2192 hi_fixup->next = mips_hi_fixup_list;
2193 mips_hi_fixup_list = hi_fixup;
2195 hi_fixup->fixp = fixp[0];
2196 hi_fixup->seg = now_seg;
2199 if (reloc_type[1] != BFD_RELOC_UNUSED)
2201 /* FIXME: This symbol can be one of
2202 RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */
2203 address_expr->X_op = O_absent;
2204 address_expr->X_add_symbol = 0;
2205 address_expr->X_add_number = 0;
2207 fixp[1] = fix_new_exp (frag_now, f - frag_now->fr_literal,
2208 4, address_expr, FALSE,
2211 /* These relocations can have an addend that won't fit in
2212 4 octets for 64bit assembly. */
2213 if (HAVE_64BIT_GPRS &&
2214 (*reloc_type == BFD_RELOC_16
2215 || *reloc_type == BFD_RELOC_32
2216 || *reloc_type == BFD_RELOC_MIPS_JMP
2217 || *reloc_type == BFD_RELOC_HI16_S
2218 || *reloc_type == BFD_RELOC_LO16
2219 || *reloc_type == BFD_RELOC_GPREL16
2220 || *reloc_type == BFD_RELOC_MIPS_LITERAL
2221 || *reloc_type == BFD_RELOC_GPREL32
2222 || *reloc_type == BFD_RELOC_64
2223 || *reloc_type == BFD_RELOC_CTOR
2224 || *reloc_type == BFD_RELOC_MIPS_SUB
2225 || *reloc_type == BFD_RELOC_MIPS_HIGHEST
2226 || *reloc_type == BFD_RELOC_MIPS_HIGHER
2227 || *reloc_type == BFD_RELOC_MIPS_SCN_DISP
2228 || *reloc_type == BFD_RELOC_MIPS_REL16
2229 || *reloc_type == BFD_RELOC_MIPS_RELGOT))
2230 fixp[1]->fx_no_overflow = 1;
2232 if (reloc_type[2] != BFD_RELOC_UNUSED)
2234 address_expr->X_op = O_absent;
2235 address_expr->X_add_symbol = 0;
2236 address_expr->X_add_number = 0;
2238 fixp[2] = fix_new_exp (frag_now,
2239 f - frag_now->fr_literal, 4,
2240 address_expr, FALSE,
2243 /* These relocations can have an addend that won't fit in
2244 4 octets for 64bit assembly. */
2245 if (HAVE_64BIT_GPRS &&
2246 (*reloc_type == BFD_RELOC_16
2247 || *reloc_type == BFD_RELOC_32
2248 || *reloc_type == BFD_RELOC_MIPS_JMP
2249 || *reloc_type == BFD_RELOC_HI16_S
2250 || *reloc_type == BFD_RELOC_LO16
2251 || *reloc_type == BFD_RELOC_GPREL16
2252 || *reloc_type == BFD_RELOC_MIPS_LITERAL
2253 || *reloc_type == BFD_RELOC_GPREL32
2254 || *reloc_type == BFD_RELOC_64
2255 || *reloc_type == BFD_RELOC_CTOR
2256 || *reloc_type == BFD_RELOC_MIPS_SUB
2257 || *reloc_type == BFD_RELOC_MIPS_HIGHEST
2258 || *reloc_type == BFD_RELOC_MIPS_HIGHER
2259 || *reloc_type == BFD_RELOC_MIPS_SCN_DISP
2260 || *reloc_type == BFD_RELOC_MIPS_REL16
2261 || *reloc_type == BFD_RELOC_MIPS_RELGOT))
2262 fixp[2]->fx_no_overflow = 1;
2269 if (! mips_opts.mips16)
2271 md_number_to_chars (f, ip->insn_opcode, 4);
2273 dwarf2_emit_insn (4);
2276 else if (*reloc_type == BFD_RELOC_MIPS16_JMP)
2278 md_number_to_chars (f, ip->insn_opcode >> 16, 2);
2279 md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2);
2281 dwarf2_emit_insn (4);
2288 md_number_to_chars (f, 0xf000 | ip->extend, 2);
2291 md_number_to_chars (f, ip->insn_opcode, 2);
2293 dwarf2_emit_insn (ip->use_extend ? 4 : 2);
2297 /* Update the register mask information. */
2298 if (! mips_opts.mips16)
2300 if (pinfo & INSN_WRITE_GPR_D)
2301 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD);
2302 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
2303 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT);
2304 if (pinfo & INSN_READ_GPR_S)
2305 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS);
2306 if (pinfo & INSN_WRITE_GPR_31)
2307 mips_gprmask |= 1 << RA;
2308 if (pinfo & INSN_WRITE_FPR_D)
2309 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD);
2310 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
2311 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS);
2312 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
2313 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT);
2314 if ((pinfo & INSN_READ_FPR_R) != 0)
2315 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR);
2316 if (pinfo & INSN_COP)
2318 /* We don't keep enough information to sort these cases out.
2319 The itbl support does keep this information however, although
2320 we currently don't support itbl fprmats as part of the cop
2321 instruction. May want to add this support in the future. */
2323 /* Never set the bit for $0, which is always zero. */
2324 mips_gprmask &= ~1 << 0;
2328 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
2329 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX)
2330 & MIPS16OP_MASK_RX);
2331 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
2332 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY)
2333 & MIPS16OP_MASK_RY);
2334 if (pinfo & MIPS16_INSN_WRITE_Z)
2335 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ)
2336 & MIPS16OP_MASK_RZ);
2337 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
2338 mips_gprmask |= 1 << TREG;
2339 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
2340 mips_gprmask |= 1 << SP;
2341 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
2342 mips_gprmask |= 1 << RA;
2343 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2344 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2345 if (pinfo & MIPS16_INSN_READ_Z)
2346 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
2347 & MIPS16OP_MASK_MOVE32Z);
2348 if (pinfo & MIPS16_INSN_READ_GPR_X)
2349 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
2350 & MIPS16OP_MASK_REGR32);
2353 if (place == NULL && ! mips_opts.noreorder)
2355 /* Filling the branch delay slot is more complex. We try to
2356 switch the branch with the previous instruction, which we can
2357 do if the previous instruction does not set up a condition
2358 that the branch tests and if the branch is not itself the
2359 target of any branch. */
2360 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
2361 || (pinfo & INSN_COND_BRANCH_DELAY))
2363 if (mips_optimize < 2
2364 /* If we have seen .set volatile or .set nomove, don't
2366 || mips_opts.nomove != 0
2367 /* If we had to emit any NOP instructions, then we
2368 already know we can not swap. */
2370 /* If we don't even know the previous insn, we can not
2372 || ! prev_insn_valid
2373 /* If the previous insn is already in a branch delay
2374 slot, then we can not swap. */
2375 || prev_insn_is_delay_slot
2376 /* If the previous previous insn was in a .set
2377 noreorder, we can't swap. Actually, the MIPS
2378 assembler will swap in this situation. However, gcc
2379 configured -with-gnu-as will generate code like
2385 in which we can not swap the bne and INSN. If gcc is
2386 not configured -with-gnu-as, it does not output the
2387 .set pseudo-ops. We don't have to check
2388 prev_insn_unreordered, because prev_insn_valid will
2389 be 0 in that case. We don't want to use
2390 prev_prev_insn_valid, because we do want to be able
2391 to swap at the start of a function. */
2392 || prev_prev_insn_unreordered
2393 /* If the branch is itself the target of a branch, we
2394 can not swap. We cheat on this; all we check for is
2395 whether there is a label on this instruction. If
2396 there are any branches to anything other than a
2397 label, users must use .set noreorder. */
2398 || insn_labels != NULL
2399 /* If the previous instruction is in a variant frag, we
2400 can not do the swap. This does not apply to the
2401 mips16, which uses variant frags for different
2403 || (! mips_opts.mips16
2404 && prev_insn_frag->fr_type == rs_machine_dependent)
2405 /* If the branch reads the condition codes, we don't
2406 even try to swap, because in the sequence
2411 we can not swap, and I don't feel like handling that
2413 || (! mips_opts.mips16
2414 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2415 && (pinfo & INSN_READ_COND_CODE))
2416 /* We can not swap with an instruction that requires a
2417 delay slot, becase the target of the branch might
2418 interfere with that instruction. */
2419 || (! mips_opts.mips16
2420 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2422 /* Itbl support may require additional care here. */
2423 & (INSN_LOAD_COPROC_DELAY
2424 | INSN_COPROC_MOVE_DELAY
2425 | INSN_WRITE_COND_CODE)))
2426 || (! (hilo_interlocks
2427 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
2431 || (! mips_opts.mips16
2433 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))
2434 || (! mips_opts.mips16
2435 && mips_opts.isa == ISA_MIPS1
2436 /* Itbl support may require additional care here. */
2437 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))
2438 /* We can not swap with a branch instruction. */
2440 & (INSN_UNCOND_BRANCH_DELAY
2441 | INSN_COND_BRANCH_DELAY
2442 | INSN_COND_BRANCH_LIKELY))
2443 /* We do not swap with a trap instruction, since it
2444 complicates trap handlers to have the trap
2445 instruction be in a delay slot. */
2446 || (prev_pinfo & INSN_TRAP)
2447 /* If the branch reads a register that the previous
2448 instruction sets, we can not swap. */
2449 || (! mips_opts.mips16
2450 && (prev_pinfo & INSN_WRITE_GPR_T)
2451 && insn_uses_reg (ip,
2452 ((prev_insn.insn_opcode >> OP_SH_RT)
2455 || (! mips_opts.mips16
2456 && (prev_pinfo & INSN_WRITE_GPR_D)
2457 && insn_uses_reg (ip,
2458 ((prev_insn.insn_opcode >> OP_SH_RD)
2461 || (mips_opts.mips16
2462 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
2463 && insn_uses_reg (ip,
2464 ((prev_insn.insn_opcode
2466 & MIPS16OP_MASK_RX),
2468 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
2469 && insn_uses_reg (ip,
2470 ((prev_insn.insn_opcode
2472 & MIPS16OP_MASK_RY),
2474 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
2475 && insn_uses_reg (ip,
2476 ((prev_insn.insn_opcode
2478 & MIPS16OP_MASK_RZ),
2480 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
2481 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
2482 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
2483 && insn_uses_reg (ip, RA, MIPS_GR_REG))
2484 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2485 && insn_uses_reg (ip,
2486 MIPS16OP_EXTRACT_REG32R (prev_insn.
2489 /* If the branch writes a register that the previous
2490 instruction sets, we can not swap (we know that
2491 branches write only to RD or to $31). */
2492 || (! mips_opts.mips16
2493 && (prev_pinfo & INSN_WRITE_GPR_T)
2494 && (((pinfo & INSN_WRITE_GPR_D)
2495 && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)
2496 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2497 || ((pinfo & INSN_WRITE_GPR_31)
2498 && (((prev_insn.insn_opcode >> OP_SH_RT)
2501 || (! mips_opts.mips16
2502 && (prev_pinfo & INSN_WRITE_GPR_D)
2503 && (((pinfo & INSN_WRITE_GPR_D)
2504 && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD)
2505 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2506 || ((pinfo & INSN_WRITE_GPR_31)
2507 && (((prev_insn.insn_opcode >> OP_SH_RD)
2510 || (mips_opts.mips16
2511 && (pinfo & MIPS16_INSN_WRITE_31)
2512 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
2513 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2514 && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode)
2516 /* If the branch writes a register that the previous
2517 instruction reads, we can not swap (we know that
2518 branches only write to RD or to $31). */
2519 || (! mips_opts.mips16
2520 && (pinfo & INSN_WRITE_GPR_D)
2521 && insn_uses_reg (&prev_insn,
2522 ((ip->insn_opcode >> OP_SH_RD)
2525 || (! mips_opts.mips16
2526 && (pinfo & INSN_WRITE_GPR_31)
2527 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2528 || (mips_opts.mips16
2529 && (pinfo & MIPS16_INSN_WRITE_31)
2530 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2531 /* If we are generating embedded PIC code, the branch
2532 might be expanded into a sequence which uses $at, so
2533 we can't swap with an instruction which reads it. */
2534 || (mips_pic == EMBEDDED_PIC
2535 && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG))
2536 /* If the previous previous instruction has a load
2537 delay, and sets a register that the branch reads, we
2539 || (! mips_opts.mips16
2540 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2541 /* Itbl support may require additional care here. */
2542 && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
2543 || (! gpr_interlocks
2544 && (prev_prev_insn.insn_mo->pinfo
2545 & INSN_LOAD_MEMORY_DELAY)))
2546 && insn_uses_reg (ip,
2547 ((prev_prev_insn.insn_opcode >> OP_SH_RT)
2550 /* If one instruction sets a condition code and the
2551 other one uses a condition code, we can not swap. */
2552 || ((pinfo & INSN_READ_COND_CODE)
2553 && (prev_pinfo & INSN_WRITE_COND_CODE))
2554 || ((pinfo & INSN_WRITE_COND_CODE)
2555 && (prev_pinfo & INSN_READ_COND_CODE))
2556 /* If the previous instruction uses the PC, we can not
2558 || (mips_opts.mips16
2559 && (prev_pinfo & MIPS16_INSN_READ_PC))
2560 /* If the previous instruction was extended, we can not
2562 || (mips_opts.mips16 && prev_insn_extended)
2563 /* If the previous instruction had a fixup in mips16
2564 mode, we can not swap. This normally means that the
2565 previous instruction was a 4 byte branch anyhow. */
2566 || (mips_opts.mips16 && prev_insn_fixp[0])
2567 /* If the previous instruction is a sync, sync.l, or
2568 sync.p, we can not swap. */
2569 || (prev_pinfo & INSN_SYNC))
2571 /* We could do even better for unconditional branches to
2572 portions of this object file; we could pick up the
2573 instruction at the destination, put it in the delay
2574 slot, and bump the destination address. */
2576 /* Update the previous insn information. */
2577 prev_prev_insn = *ip;
2578 prev_insn.insn_mo = &dummy_opcode;
2582 /* It looks like we can actually do the swap. */
2583 if (! mips_opts.mips16)
2588 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2589 memcpy (temp, prev_f, 4);
2590 memcpy (prev_f, f, 4);
2591 memcpy (f, temp, 4);
2592 if (prev_insn_fixp[0])
2594 prev_insn_fixp[0]->fx_frag = frag_now;
2595 prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal;
2597 if (prev_insn_fixp[1])
2599 prev_insn_fixp[1]->fx_frag = frag_now;
2600 prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal;
2602 if (prev_insn_fixp[2])
2604 prev_insn_fixp[2]->fx_frag = frag_now;
2605 prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal;
2609 fixp[0]->fx_frag = prev_insn_frag;
2610 fixp[0]->fx_where = prev_insn_where;
2614 fixp[1]->fx_frag = prev_insn_frag;
2615 fixp[1]->fx_where = prev_insn_where;
2619 fixp[2]->fx_frag = prev_insn_frag;
2620 fixp[2]->fx_where = prev_insn_where;
2628 assert (prev_insn_fixp[0] == NULL);
2629 assert (prev_insn_fixp[1] == NULL);
2630 assert (prev_insn_fixp[2] == NULL);
2631 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2632 memcpy (temp, prev_f, 2);
2633 memcpy (prev_f, f, 2);
2634 if (*reloc_type != BFD_RELOC_MIPS16_JMP)
2636 assert (*reloc_type == BFD_RELOC_UNUSED);
2637 memcpy (f, temp, 2);
2641 memcpy (f, f + 2, 2);
2642 memcpy (f + 2, temp, 2);
2646 fixp[0]->fx_frag = prev_insn_frag;
2647 fixp[0]->fx_where = prev_insn_where;
2651 fixp[1]->fx_frag = prev_insn_frag;
2652 fixp[1]->fx_where = prev_insn_where;
2656 fixp[2]->fx_frag = prev_insn_frag;
2657 fixp[2]->fx_where = prev_insn_where;
2661 /* Update the previous insn information; leave prev_insn
2663 prev_prev_insn = *ip;
2665 prev_insn_is_delay_slot = 1;
2667 /* If that was an unconditional branch, forget the previous
2668 insn information. */
2669 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
2671 prev_prev_insn.insn_mo = &dummy_opcode;
2672 prev_insn.insn_mo = &dummy_opcode;
2675 prev_insn_fixp[0] = NULL;
2676 prev_insn_fixp[1] = NULL;
2677 prev_insn_fixp[2] = NULL;
2678 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2679 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2680 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2681 prev_insn_extended = 0;
2683 else if (pinfo & INSN_COND_BRANCH_LIKELY)
2685 /* We don't yet optimize a branch likely. What we should do
2686 is look at the target, copy the instruction found there
2687 into the delay slot, and increment the branch to jump to
2688 the next instruction. */
2690 /* Update the previous insn information. */
2691 prev_prev_insn = *ip;
2692 prev_insn.insn_mo = &dummy_opcode;
2693 prev_insn_fixp[0] = NULL;
2694 prev_insn_fixp[1] = NULL;
2695 prev_insn_fixp[2] = NULL;
2696 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2697 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2698 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2699 prev_insn_extended = 0;
2703 /* Update the previous insn information. */
2705 prev_prev_insn.insn_mo = &dummy_opcode;
2707 prev_prev_insn = prev_insn;
2710 /* Any time we see a branch, we always fill the delay slot
2711 immediately; since this insn is not a branch, we know it
2712 is not in a delay slot. */
2713 prev_insn_is_delay_slot = 0;
2715 prev_insn_fixp[0] = fixp[0];
2716 prev_insn_fixp[1] = fixp[1];
2717 prev_insn_fixp[2] = fixp[2];
2718 prev_insn_reloc_type[0] = reloc_type[0];
2719 prev_insn_reloc_type[1] = reloc_type[1];
2720 prev_insn_reloc_type[2] = reloc_type[2];
2721 if (mips_opts.mips16)
2722 prev_insn_extended = (ip->use_extend
2723 || *reloc_type > BFD_RELOC_UNUSED);
2726 prev_prev_insn_unreordered = prev_insn_unreordered;
2727 prev_insn_unreordered = 0;
2728 prev_insn_frag = frag_now;
2729 prev_insn_where = f - frag_now->fr_literal;
2730 prev_insn_valid = 1;
2732 else if (place == NULL)
2734 /* We need to record a bit of information even when we are not
2735 reordering, in order to determine the base address for mips16
2736 PC relative relocs. */
2737 prev_prev_insn = prev_insn;
2739 prev_insn_reloc_type[0] = reloc_type[0];
2740 prev_insn_reloc_type[1] = reloc_type[1];
2741 prev_insn_reloc_type[2] = reloc_type[2];
2742 prev_prev_insn_unreordered = prev_insn_unreordered;
2743 prev_insn_unreordered = 1;
2746 /* We just output an insn, so the next one doesn't have a label. */
2747 mips_clear_insn_labels ();
2750 /* This function forgets that there was any previous instruction or
2751 label. If PRESERVE is non-zero, it remembers enough information to
2752 know whether nops are needed before a noreorder section. */
2755 mips_no_prev_insn (preserve)
2760 prev_insn.insn_mo = &dummy_opcode;
2761 prev_prev_insn.insn_mo = &dummy_opcode;
2762 prev_nop_frag = NULL;
2763 prev_nop_frag_holds = 0;
2764 prev_nop_frag_required = 0;
2765 prev_nop_frag_since = 0;
2767 prev_insn_valid = 0;
2768 prev_insn_is_delay_slot = 0;
2769 prev_insn_unreordered = 0;
2770 prev_insn_extended = 0;
2771 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2772 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2773 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2774 prev_prev_insn_unreordered = 0;
2775 mips_clear_insn_labels ();
2778 /* This function must be called whenever we turn on noreorder or emit
2779 something other than instructions. It inserts any NOPS which might
2780 be needed by the previous instruction, and clears the information
2781 kept for the previous instructions. The INSNS parameter is true if
2782 instructions are to follow. */
2785 mips_emit_delays (insns)
2788 if (! mips_opts.noreorder)
2793 if ((! mips_opts.mips16
2794 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2795 && (! cop_interlocks
2796 && (prev_insn.insn_mo->pinfo
2797 & (INSN_LOAD_COPROC_DELAY
2798 | INSN_COPROC_MOVE_DELAY
2799 | INSN_WRITE_COND_CODE))))
2800 || (! hilo_interlocks
2801 && (prev_insn.insn_mo->pinfo
2804 || (! mips_opts.mips16
2806 && (prev_insn.insn_mo->pinfo
2807 & INSN_LOAD_MEMORY_DELAY))
2808 || (! mips_opts.mips16
2809 && mips_opts.isa == ISA_MIPS1
2810 && (prev_insn.insn_mo->pinfo
2811 & INSN_COPROC_MEMORY_DELAY)))
2813 /* Itbl support may require additional care here. */
2815 if ((! mips_opts.mips16
2816 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2817 && (! cop_interlocks
2818 && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
2819 || (! hilo_interlocks
2820 && ((prev_insn.insn_mo->pinfo & INSN_READ_HI)
2821 || (prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2824 if (prev_insn_unreordered)
2827 else if ((! mips_opts.mips16
2828 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2829 && (! cop_interlocks
2830 && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
2831 || (! hilo_interlocks
2832 && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
2833 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2835 /* Itbl support may require additional care here. */
2836 if (! prev_prev_insn_unreordered)
2840 if (mips_fix_4122_bugs && prev_insn.insn_mo->name)
2843 const char *pn = prev_insn.insn_mo->name;
2844 if (strncmp(pn, "macc", 4) == 0
2845 || strncmp(pn, "dmacc", 5) == 0
2846 || strncmp(pn, "dmult", 5) == 0)
2850 if (nops < min_nops)
2856 struct insn_label_list *l;
2860 /* Record the frag which holds the nop instructions, so
2861 that we can remove them if we don't need them. */
2862 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
2863 prev_nop_frag = frag_now;
2864 prev_nop_frag_holds = nops;
2865 prev_nop_frag_required = 0;
2866 prev_nop_frag_since = 0;
2869 for (; nops > 0; --nops)
2874 /* Move on to a new frag, so that it is safe to simply
2875 decrease the size of prev_nop_frag. */
2876 frag_wane (frag_now);
2880 for (l = insn_labels; l != NULL; l = l->next)
2884 assert (S_GET_SEGMENT (l->label) == now_seg);
2885 symbol_set_frag (l->label, frag_now);
2886 val = (valueT) frag_now_fix ();
2887 /* mips16 text labels are stored as odd. */
2888 if (mips_opts.mips16)
2890 S_SET_VALUE (l->label, val);
2895 /* Mark instruction labels in mips16 mode. */
2897 mips16_mark_labels ();
2899 mips_no_prev_insn (insns);
2902 /* Build an instruction created by a macro expansion. This is passed
2903 a pointer to the count of instructions created so far, an
2904 expression, the name of the instruction to build, an operand format
2905 string, and corresponding arguments. */
2909 macro_build (char *place,
2917 macro_build (place, counter, ep, name, fmt, va_alist)
2926 struct mips_cl_insn insn;
2927 bfd_reloc_code_real_type r[3];
2931 va_start (args, fmt);
2937 * If the macro is about to expand into a second instruction,
2938 * print a warning if needed. We need to pass ip as a parameter
2939 * to generate a better warning message here...
2941 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
2942 as_warn (_("Macro instruction expanded into multiple instructions"));
2945 * If the macro is about to expand into a second instruction,
2946 * and it is in a delay slot, print a warning.
2950 && mips_opts.noreorder
2951 && (prev_prev_insn.insn_mo->pinfo
2952 & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY
2953 | INSN_COND_BRANCH_LIKELY)) != 0)
2954 as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot"));
2957 ++*counter; /* bump instruction counter */
2959 if (mips_opts.mips16)
2961 mips16_macro_build (place, counter, ep, name, fmt, args);
2966 r[0] = BFD_RELOC_UNUSED;
2967 r[1] = BFD_RELOC_UNUSED;
2968 r[2] = BFD_RELOC_UNUSED;
2969 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
2970 assert (insn.insn_mo);
2971 assert (strcmp (name, insn.insn_mo->name) == 0);
2973 /* Search until we get a match for NAME. */
2976 /* It is assumed here that macros will never generate
2977 MDMX or MIPS-3D instructions. */
2978 if (strcmp (fmt, insn.insn_mo->args) == 0
2979 && insn.insn_mo->pinfo != INSN_MACRO
2980 && OPCODE_IS_MEMBER (insn.insn_mo,
2982 | (file_ase_mips16 ? INSN_MIPS16 : 0)),
2984 && (mips_arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
2988 assert (insn.insn_mo->name);
2989 assert (strcmp (name, insn.insn_mo->name) == 0);
2992 insn.insn_opcode = insn.insn_mo->match;
3008 insn.insn_opcode |= va_arg (args, int) << OP_SH_RT;
3012 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE;
3017 insn.insn_opcode |= va_arg (args, int) << OP_SH_FT;
3023 insn.insn_opcode |= va_arg (args, int) << OP_SH_RD;
3028 int tmp = va_arg (args, int);
3030 insn.insn_opcode |= tmp << OP_SH_RT;
3031 insn.insn_opcode |= tmp << OP_SH_RD;
3037 insn.insn_opcode |= va_arg (args, int) << OP_SH_FS;
3044 insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT;
3048 insn.insn_opcode |= va_arg (args, int) << OP_SH_FD;
3052 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20;
3056 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19;
3060 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2;
3067 insn.insn_opcode |= va_arg (args, int) << OP_SH_RS;
3073 *r = (bfd_reloc_code_real_type) va_arg (args, int);
3074 assert (*r == BFD_RELOC_GPREL16
3075 || *r == BFD_RELOC_MIPS_LITERAL
3076 || *r == BFD_RELOC_MIPS_HIGHER
3077 || *r == BFD_RELOC_HI16_S
3078 || *r == BFD_RELOC_LO16
3079 || *r == BFD_RELOC_MIPS_GOT16
3080 || *r == BFD_RELOC_MIPS_CALL16
3081 || *r == BFD_RELOC_MIPS_GOT_DISP
3082 || *r == BFD_RELOC_MIPS_GOT_PAGE
3083 || *r == BFD_RELOC_MIPS_GOT_OFST
3084 || *r == BFD_RELOC_MIPS_GOT_LO16
3085 || *r == BFD_RELOC_MIPS_CALL_LO16
3086 || (ep->X_op == O_subtract
3087 && *r == BFD_RELOC_PCREL_LO16));
3091 *r = (bfd_reloc_code_real_type) va_arg (args, int);
3093 && (ep->X_op == O_constant
3094 || (ep->X_op == O_symbol
3095 && (*r == BFD_RELOC_MIPS_HIGHEST
3096 || *r == BFD_RELOC_HI16_S
3097 || *r == BFD_RELOC_HI16
3098 || *r == BFD_RELOC_GPREL16
3099 || *r == BFD_RELOC_MIPS_GOT_HI16
3100 || *r == BFD_RELOC_MIPS_CALL_HI16))
3101 || (ep->X_op == O_subtract
3102 && *r == BFD_RELOC_PCREL_HI16_S)));
3106 assert (ep != NULL);
3108 * This allows macro() to pass an immediate expression for
3109 * creating short branches without creating a symbol.
3110 * Note that the expression still might come from the assembly
3111 * input, in which case the value is not checked for range nor
3112 * is a relocation entry generated (yuck).
3114 if (ep->X_op == O_constant)
3116 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
3120 *r = BFD_RELOC_16_PCREL_S2;
3124 assert (ep != NULL);
3125 *r = BFD_RELOC_MIPS_JMP;
3129 insn.insn_opcode |= va_arg (args, unsigned long);
3138 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3140 append_insn (place, &insn, ep, r);
3144 mips16_macro_build (place, counter, ep, name, fmt, args)
3146 int *counter ATTRIBUTE_UNUSED;
3152 struct mips_cl_insn insn;
3153 bfd_reloc_code_real_type r[3]
3154 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3156 insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
3157 assert (insn.insn_mo);
3158 assert (strcmp (name, insn.insn_mo->name) == 0);
3160 while (strcmp (fmt, insn.insn_mo->args) != 0
3161 || insn.insn_mo->pinfo == INSN_MACRO)
3164 assert (insn.insn_mo->name);
3165 assert (strcmp (name, insn.insn_mo->name) == 0);
3168 insn.insn_opcode = insn.insn_mo->match;
3169 insn.use_extend = FALSE;
3188 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY;
3193 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX;
3197 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ;
3201 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z;
3211 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32;
3218 regno = va_arg (args, int);
3219 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
3220 insn.insn_opcode |= regno << MIPS16OP_SH_REG32R;
3241 assert (ep != NULL);
3243 if (ep->X_op != O_constant)
3244 *r = (int) BFD_RELOC_UNUSED + c;
3247 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
3248 FALSE, &insn.insn_opcode, &insn.use_extend,
3251 *r = BFD_RELOC_UNUSED;
3257 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6;
3264 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3266 append_insn (place, &insn, ep, r);
3270 * Generate a "jalr" instruction with a relocation hint to the called
3271 * function. This occurs in NewABI PIC code.
3274 macro_build_jalr (icnt, ep)
3285 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", "d,s",
3288 fix_new_exp (frag_now, f - frag_now->fr_literal,
3289 0, ep, FALSE, BFD_RELOC_MIPS_JALR);
3293 * Generate a "lui" instruction.
3296 macro_build_lui (place, counter, ep, regnum)
3302 expressionS high_expr;
3303 struct mips_cl_insn insn;
3304 bfd_reloc_code_real_type r[3]
3305 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3306 const char *name = "lui";
3307 const char *fmt = "t,u";
3309 assert (! mips_opts.mips16);
3315 high_expr.X_op = O_constant;
3316 high_expr.X_add_number = ep->X_add_number;
3319 if (high_expr.X_op == O_constant)
3321 /* we can compute the instruction now without a relocation entry */
3322 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
3324 *r = BFD_RELOC_UNUSED;
3328 assert (ep->X_op == O_symbol);
3329 /* _gp_disp is a special case, used from s_cpload. */
3330 assert (mips_pic == NO_PIC
3332 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0));
3333 *r = BFD_RELOC_HI16_S;
3337 * If the macro is about to expand into a second instruction,
3338 * print a warning if needed. We need to pass ip as a parameter
3339 * to generate a better warning message here...
3341 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
3342 as_warn (_("Macro instruction expanded into multiple instructions"));
3345 ++*counter; /* bump instruction counter */
3347 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
3348 assert (insn.insn_mo);
3349 assert (strcmp (name, insn.insn_mo->name) == 0);
3350 assert (strcmp (fmt, insn.insn_mo->args) == 0);
3352 insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT);
3353 if (*r == BFD_RELOC_UNUSED)
3355 insn.insn_opcode |= high_expr.X_add_number;
3356 append_insn (place, &insn, NULL, r);
3359 append_insn (place, &insn, &high_expr, r);
3362 /* Generate a sequence of instructions to do a load or store from a constant
3363 offset off of a base register (breg) into/from a target register (treg),
3364 using AT if necessary. */
3366 macro_build_ldst_constoffset (place, counter, ep, op, treg, breg)
3373 assert (ep->X_op == O_constant);
3375 /* Right now, this routine can only handle signed 32-bit contants. */
3376 if (! IS_SEXT_32BIT_NUM(ep->X_add_number))
3377 as_warn (_("operand overflow"));
3379 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
3381 /* Signed 16-bit offset will fit in the op. Easy! */
3382 macro_build (place, counter, ep, op, "t,o(b)", treg,
3383 (int) BFD_RELOC_LO16, breg);
3387 /* 32-bit offset, need multiple instructions and AT, like:
3388 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3389 addu $tempreg,$tempreg,$breg
3390 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3391 to handle the complete offset. */
3392 macro_build_lui (place, counter, ep, AT);
3395 macro_build (place, counter, (expressionS *) NULL,
3396 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
3397 "d,v,t", AT, AT, breg);
3400 macro_build (place, counter, ep, op, "t,o(b)", treg,
3401 (int) BFD_RELOC_LO16, AT);
3404 as_warn (_("Macro used $at after \".set noat\""));
3409 * Generates code to set the $at register to true (one)
3410 * if reg is less than the immediate expression.
3413 set_at (counter, reg, unsignedp)
3418 if (imm_expr.X_op == O_constant
3419 && imm_expr.X_add_number >= -0x8000
3420 && imm_expr.X_add_number < 0x8000)
3421 macro_build ((char *) NULL, counter, &imm_expr,
3422 unsignedp ? "sltiu" : "slti",
3423 "t,r,j", AT, reg, (int) BFD_RELOC_LO16);
3426 load_register (counter, AT, &imm_expr, HAVE_64BIT_GPRS);
3427 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3428 unsignedp ? "sltu" : "slt",
3429 "d,v,t", AT, reg, AT);
3433 /* Warn if an expression is not a constant. */
3436 check_absolute_expr (ip, ex)
3437 struct mips_cl_insn *ip;
3440 if (ex->X_op == O_big)
3441 as_bad (_("unsupported large constant"));
3442 else if (ex->X_op != O_constant)
3443 as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name);
3446 /* Count the leading zeroes by performing a binary chop. This is a
3447 bulky bit of source, but performance is a LOT better for the
3448 majority of values than a simple loop to count the bits:
3449 for (lcnt = 0; (lcnt < 32); lcnt++)
3450 if ((v) & (1 << (31 - lcnt)))
3452 However it is not code size friendly, and the gain will drop a bit
3453 on certain cached systems.
3455 #define COUNT_TOP_ZEROES(v) \
3456 (((v) & ~0xffff) == 0 \
3457 ? ((v) & ~0xff) == 0 \
3458 ? ((v) & ~0xf) == 0 \
3459 ? ((v) & ~0x3) == 0 \
3460 ? ((v) & ~0x1) == 0 \
3465 : ((v) & ~0x7) == 0 \
3468 : ((v) & ~0x3f) == 0 \
3469 ? ((v) & ~0x1f) == 0 \
3472 : ((v) & ~0x7f) == 0 \
3475 : ((v) & ~0xfff) == 0 \
3476 ? ((v) & ~0x3ff) == 0 \
3477 ? ((v) & ~0x1ff) == 0 \
3480 : ((v) & ~0x7ff) == 0 \
3483 : ((v) & ~0x3fff) == 0 \
3484 ? ((v) & ~0x1fff) == 0 \
3487 : ((v) & ~0x7fff) == 0 \
3490 : ((v) & ~0xffffff) == 0 \
3491 ? ((v) & ~0xfffff) == 0 \
3492 ? ((v) & ~0x3ffff) == 0 \
3493 ? ((v) & ~0x1ffff) == 0 \
3496 : ((v) & ~0x7ffff) == 0 \
3499 : ((v) & ~0x3fffff) == 0 \
3500 ? ((v) & ~0x1fffff) == 0 \
3503 : ((v) & ~0x7fffff) == 0 \
3506 : ((v) & ~0xfffffff) == 0 \
3507 ? ((v) & ~0x3ffffff) == 0 \
3508 ? ((v) & ~0x1ffffff) == 0 \
3511 : ((v) & ~0x7ffffff) == 0 \
3514 : ((v) & ~0x3fffffff) == 0 \
3515 ? ((v) & ~0x1fffffff) == 0 \
3518 : ((v) & ~0x7fffffff) == 0 \
3523 * This routine generates the least number of instructions neccessary to load
3524 * an absolute expression value into a register.
3527 load_register (counter, reg, ep, dbl)
3534 expressionS hi32, lo32;
3536 if (ep->X_op != O_big)
3538 assert (ep->X_op == O_constant);
3539 if (ep->X_add_number < 0x8000
3540 && (ep->X_add_number >= 0
3541 || (ep->X_add_number >= -0x8000
3544 || sizeof (ep->X_add_number) > 4))))
3546 /* We can handle 16 bit signed values with an addiu to
3547 $zero. No need to ever use daddiu here, since $zero and
3548 the result are always correct in 32 bit mode. */
3549 macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3550 (int) BFD_RELOC_LO16);
3553 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
3555 /* We can handle 16 bit unsigned values with an ori to
3557 macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0,
3558 (int) BFD_RELOC_LO16);
3561 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)
3564 || sizeof (ep->X_add_number) > 4
3565 || (ep->X_add_number & 0x80000000) == 0))
3566 || ((HAVE_32BIT_GPRS || ! dbl)
3567 && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0)
3570 && ((ep->X_add_number &~ (offsetT) 0xffffffff)
3571 == ~ (offsetT) 0xffffffff)))
3573 /* 32 bit values require an lui. */
3574 macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg,
3575 (int) BFD_RELOC_HI16);
3576 if ((ep->X_add_number & 0xffff) != 0)
3577 macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg,
3578 (int) BFD_RELOC_LO16);
3583 /* The value is larger than 32 bits. */
3585 if (HAVE_32BIT_GPRS)
3587 as_bad (_("Number (0x%lx) larger than 32 bits"),
3588 (unsigned long) ep->X_add_number);
3589 macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3590 (int) BFD_RELOC_LO16);
3594 if (ep->X_op != O_big)
3597 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3598 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3599 hi32.X_add_number &= 0xffffffff;
3601 lo32.X_add_number &= 0xffffffff;
3605 assert (ep->X_add_number > 2);
3606 if (ep->X_add_number == 3)
3607 generic_bignum[3] = 0;
3608 else if (ep->X_add_number > 4)
3609 as_bad (_("Number larger than 64 bits"));
3610 lo32.X_op = O_constant;
3611 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
3612 hi32.X_op = O_constant;
3613 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
3616 if (hi32.X_add_number == 0)
3621 unsigned long hi, lo;
3623 if (hi32.X_add_number == (offsetT) 0xffffffff)
3625 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
3627 macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j",
3628 reg, 0, (int) BFD_RELOC_LO16);
3631 if (lo32.X_add_number & 0x80000000)
3633 macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg,
3634 (int) BFD_RELOC_HI16);
3635 if (lo32.X_add_number & 0xffff)
3636 macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i",
3637 reg, reg, (int) BFD_RELOC_LO16);
3642 /* Check for 16bit shifted constant. We know that hi32 is
3643 non-zero, so start the mask on the first bit of the hi32
3648 unsigned long himask, lomask;
3652 himask = 0xffff >> (32 - shift);
3653 lomask = (0xffff << shift) & 0xffffffff;
3657 himask = 0xffff << (shift - 32);
3660 if ((hi32.X_add_number & ~(offsetT) himask) == 0
3661 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
3665 tmp.X_op = O_constant;
3667 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
3668 | (lo32.X_add_number >> shift));
3670 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
3671 macro_build ((char *) NULL, counter, &tmp,
3672 "ori", "t,r,i", reg, 0,
3673 (int) BFD_RELOC_LO16);
3674 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3675 (shift >= 32) ? "dsll32" : "dsll",
3677 (shift >= 32) ? shift - 32 : shift);
3682 while (shift <= (64 - 16));
3684 /* Find the bit number of the lowest one bit, and store the
3685 shifted value in hi/lo. */
3686 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
3687 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
3691 while ((lo & 1) == 0)
3696 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
3702 while ((hi & 1) == 0)
3711 /* Optimize if the shifted value is a (power of 2) - 1. */
3712 if ((hi == 0 && ((lo + 1) & lo) == 0)
3713 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
3715 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
3720 /* This instruction will set the register to be all
3722 tmp.X_op = O_constant;
3723 tmp.X_add_number = (offsetT) -1;
3724 macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j",
3725 reg, 0, (int) BFD_RELOC_LO16);
3729 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3730 (bit >= 32) ? "dsll32" : "dsll",
3732 (bit >= 32) ? bit - 32 : bit);
3734 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3735 (shift >= 32) ? "dsrl32" : "dsrl",
3737 (shift >= 32) ? shift - 32 : shift);
3742 /* Sign extend hi32 before calling load_register, because we can
3743 generally get better code when we load a sign extended value. */
3744 if ((hi32.X_add_number & 0x80000000) != 0)
3745 hi32.X_add_number |= ~(offsetT) 0xffffffff;
3746 load_register (counter, reg, &hi32, 0);
3749 if ((lo32.X_add_number & 0xffff0000) == 0)
3753 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3754 "dsll32", "d,w,<", reg, freg, 0);
3762 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
3764 macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg,
3765 (int) BFD_RELOC_HI16);
3766 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3767 "dsrl32", "d,w,<", reg, reg, 0);
3773 macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll",
3774 "d,w,<", reg, freg, 16);
3778 mid16.X_add_number >>= 16;
3779 macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg,
3780 freg, (int) BFD_RELOC_LO16);
3781 macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll",
3782 "d,w,<", reg, reg, 16);
3785 if ((lo32.X_add_number & 0xffff) != 0)
3786 macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg,
3787 (int) BFD_RELOC_LO16);
3790 /* Load an address into a register. */
3793 load_address (counter, reg, ep, used_at)
3801 if (ep->X_op != O_constant
3802 && ep->X_op != O_symbol)
3804 as_bad (_("expression too complex"));
3805 ep->X_op = O_constant;
3808 if (ep->X_op == O_constant)
3810 load_register (counter, reg, ep, HAVE_64BIT_ADDRESSES);
3814 if (mips_pic == NO_PIC)
3816 /* If this is a reference to a GP relative symbol, we want
3817 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3819 lui $reg,<sym> (BFD_RELOC_HI16_S)
3820 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3821 If we have an addend, we always use the latter form.
3823 With 64bit address space and a usable $at we want
3824 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3825 lui $at,<sym> (BFD_RELOC_HI16_S)
3826 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3827 daddiu $at,<sym> (BFD_RELOC_LO16)
3831 If $at is already in use, we use a path which is suboptimal
3832 on superscalar processors.
3833 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3834 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3836 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3838 daddiu $reg,<sym> (BFD_RELOC_LO16)
3840 if (HAVE_64BIT_ADDRESSES)
3842 /* We don't do GP optimization for now because RELAX_ENCODE can't
3843 hold the data for such large chunks. */
3845 if (*used_at == 0 && ! mips_opts.noat)
3847 macro_build (p, counter, ep, "lui", "t,u",
3848 reg, (int) BFD_RELOC_MIPS_HIGHEST);
3849 macro_build (p, counter, ep, "lui", "t,u",
3850 AT, (int) BFD_RELOC_HI16_S);
3851 macro_build (p, counter, ep, "daddiu", "t,r,j",
3852 reg, reg, (int) BFD_RELOC_MIPS_HIGHER);
3853 macro_build (p, counter, ep, "daddiu", "t,r,j",
3854 AT, AT, (int) BFD_RELOC_LO16);
3855 macro_build (p, counter, (expressionS *) NULL, "dsll32",
3856 "d,w,<", reg, reg, 0);
3857 macro_build (p, counter, (expressionS *) NULL, "daddu",
3858 "d,v,t", reg, reg, AT);
3863 macro_build (p, counter, ep, "lui", "t,u",
3864 reg, (int) BFD_RELOC_MIPS_HIGHEST);
3865 macro_build (p, counter, ep, "daddiu", "t,r,j",
3866 reg, reg, (int) BFD_RELOC_MIPS_HIGHER);
3867 macro_build (p, counter, (expressionS *) NULL, "dsll",
3868 "d,w,<", reg, reg, 16);
3869 macro_build (p, counter, ep, "daddiu", "t,r,j",
3870 reg, reg, (int) BFD_RELOC_HI16_S);
3871 macro_build (p, counter, (expressionS *) NULL, "dsll",
3872 "d,w,<", reg, reg, 16);
3873 macro_build (p, counter, ep, "daddiu", "t,r,j",
3874 reg, reg, (int) BFD_RELOC_LO16);
3879 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
3880 && ! nopic_need_relax (ep->X_add_symbol, 1))
3883 macro_build ((char *) NULL, counter, ep,
3884 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j",
3885 reg, mips_gp_register, (int) BFD_RELOC_GPREL16);
3886 p = frag_var (rs_machine_dependent, 8, 0,
3887 RELAX_ENCODE (4, 8, 0, 4, 0,
3888 mips_opts.warn_about_macros),
3889 ep->X_add_symbol, 0, NULL);
3891 macro_build_lui (p, counter, ep, reg);
3894 macro_build (p, counter, ep,
3895 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3896 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3899 else if (mips_pic == SVR4_PIC && ! mips_big_got)
3903 /* If this is a reference to an external symbol, we want
3904 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3906 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3908 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3909 If we have NewABI, we want
3910 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3911 If there is a constant, it must be added in after. */
3912 ex.X_add_number = ep->X_add_number;
3913 ep->X_add_number = 0;
3917 macro_build ((char *) NULL, counter, ep,
3918 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg,
3919 (int) BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
3923 macro_build ((char *) NULL, counter, ep,
3924 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)",
3925 reg, (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
3926 macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", "");
3927 p = frag_var (rs_machine_dependent, 4, 0,
3928 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros),
3929 ep->X_add_symbol, (offsetT) 0, (char *) NULL);
3930 macro_build (p, counter, ep,
3931 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3932 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3935 if (ex.X_add_number != 0)
3937 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3938 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3939 ex.X_op = O_constant;
3940 macro_build ((char *) NULL, counter, &ex,
3941 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3942 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3945 else if (mips_pic == SVR4_PIC)
3950 /* This is the large GOT case. If this is a reference to an
3951 external symbol, we want
3952 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3954 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3955 Otherwise, for a reference to a local symbol, we want
3956 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3958 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3959 If we have NewABI, we want
3960 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3961 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3962 If there is a constant, it must be added in after. */
3963 ex.X_add_number = ep->X_add_number;
3964 ep->X_add_number = 0;
3967 macro_build ((char *) NULL, counter, ep,
3968 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg,
3969 (int) BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
3970 macro_build (p, counter, ep,
3971 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j",
3972 reg, reg, (int) BFD_RELOC_MIPS_GOT_OFST);
3976 if (reg_needs_delay (mips_gp_register))
3981 macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg,
3982 (int) BFD_RELOC_MIPS_GOT_HI16);
3983 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3984 HAVE_32BIT_ADDRESSES ? "addu" : "daddu", "d,v,t", reg,
3985 reg, mips_gp_register);
3986 macro_build ((char *) NULL, counter, ep,
3987 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
3988 "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg);
3989 p = frag_var (rs_machine_dependent, 12 + off, 0,
3990 RELAX_ENCODE (12, 12 + off, off, 8 + off, 0,
3991 mips_opts.warn_about_macros),
3992 ep->X_add_symbol, 0, NULL);
3995 /* We need a nop before loading from $gp. This special
3996 check is required because the lui which starts the main
3997 instruction stream does not refer to $gp, and so will not
3998 insert the nop which may be required. */
3999 macro_build (p, counter, (expressionS *) NULL, "nop", "");
4002 macro_build (p, counter, ep,
4003 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg,
4004 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
4006 macro_build (p, counter, (expressionS *) NULL, "nop", "");
4008 macro_build (p, counter, ep,
4009 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4010 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
4013 if (ex.X_add_number != 0)
4015 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4016 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4017 ex.X_op = O_constant;
4018 macro_build ((char *) NULL, counter, &ex,
4019 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4020 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
4023 else if (mips_pic == EMBEDDED_PIC)
4026 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4028 macro_build ((char *) NULL, counter, ep,
4029 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4030 "t,r,j", reg, mips_gp_register, (int) BFD_RELOC_GPREL16);
4036 /* Move the contents of register SOURCE into register DEST. */
4039 move_register (counter, dest, source)
4044 macro_build ((char *) NULL, counter, (expressionS *) NULL,
4045 HAVE_32BIT_GPRS ? "addu" : "daddu",
4046 "d,v,t", dest, source, 0);
4051 * This routine implements the seemingly endless macro or synthesized
4052 * instructions and addressing modes in the mips assembly language. Many
4053 * of these macros are simple and are similar to each other. These could
4054 * probably be handled by some kind of table or grammer aproach instead of
4055 * this verbose method. Others are not simple macros but are more like
4056 * optimizing code generation.
4057 * One interesting optimization is when several store macros appear
4058 * consecutivly that would load AT with the upper half of the same address.
4059 * The ensuing load upper instructions are ommited. This implies some kind
4060 * of global optimization. We currently only optimize within a single macro.
4061 * For many of the load and store macros if the address is specified as a
4062 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4063 * first load register 'at' with zero and use it as the base register. The
4064 * mips assembler simply uses register $zero. Just one tiny optimization
4069 struct mips_cl_insn *ip;
4071 register int treg, sreg, dreg, breg;
4087 bfd_reloc_code_real_type r;
4088 int hold_mips_optimize;
4090 assert (! mips_opts.mips16);
4092 treg = (ip->insn_opcode >> 16) & 0x1f;
4093 dreg = (ip->insn_opcode >> 11) & 0x1f;
4094 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
4095 mask = ip->insn_mo->mask;
4097 expr1.X_op = O_constant;
4098 expr1.X_op_symbol = NULL;
4099 expr1.X_add_symbol = NULL;
4100 expr1.X_add_number = 1;
4102 /* Umatched fixups should not be put in the same frag as a relaxable
4103 macro. For example, suppose we have:
4107 addiu $4,$4,%lo(l1) # 3
4109 If instructions 1 and 2 were put in the same frag, md_frob_file would
4110 move the fixup for #1 after the fixups for the "unrelaxed" version of
4111 #2. This would confuse tc_gen_reloc, which expects the relocations
4112 for #2 to be the last for that frag.
4114 Also, if tc_gen_reloc sees certain relocations in a variant frag,
4115 it assumes that they belong to a relaxable macro. We mustn't put
4116 other uses of such relocations into a variant frag.
4118 To avoid both problems, finish the current frag it contains a
4119 %reloc() operator. The macro then goes into a new frag. */
4120 if (prev_reloc_op_frag == frag_now)
4122 frag_wane (frag_now);
4136 mips_emit_delays (TRUE);
4137 ++mips_opts.noreorder;
4138 mips_any_noreorder = 1;
4140 expr1.X_add_number = 8;
4141 macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg);
4143 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
4146 move_register (&icnt, dreg, sreg);
4147 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4148 dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
4150 --mips_opts.noreorder;
4171 if (imm_expr.X_op == O_constant
4172 && imm_expr.X_add_number >= -0x8000
4173 && imm_expr.X_add_number < 0x8000)
4175 macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg,
4176 (int) BFD_RELOC_LO16);
4179 load_register (&icnt, AT, &imm_expr, dbl);
4180 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t",
4200 if (imm_expr.X_op == O_constant
4201 && imm_expr.X_add_number >= 0
4202 && imm_expr.X_add_number < 0x10000)
4204 if (mask != M_NOR_I)
4205 macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg,
4206 sreg, (int) BFD_RELOC_LO16);
4209 macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i",
4210 treg, sreg, (int) BFD_RELOC_LO16);
4211 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nor",
4212 "d,v,t", treg, treg, 0);
4217 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
4218 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t",
4236 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4238 macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg,
4242 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
4243 macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT);
4251 macro_build ((char *) NULL, &icnt, &offset_expr,
4252 likely ? "bgezl" : "bgez", "s,p", sreg);
4257 macro_build ((char *) NULL, &icnt, &offset_expr,
4258 likely ? "blezl" : "blez", "s,p", treg);
4261 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4263 macro_build ((char *) NULL, &icnt, &offset_expr,
4264 likely ? "beql" : "beq", "s,t,p", AT, 0);
4270 /* check for > max integer */
4271 maxnum = 0x7fffffff;
4272 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4279 if (imm_expr.X_op == O_constant
4280 && imm_expr.X_add_number >= maxnum
4281 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4284 /* result is always false */
4288 as_warn (_("Branch %s is always false (nop)"),
4290 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop",
4296 as_warn (_("Branch likely %s is always false"),
4298 macro_build ((char *) NULL, &icnt, &offset_expr, "bnel",
4303 if (imm_expr.X_op != O_constant)
4304 as_bad (_("Unsupported large constant"));
4305 ++imm_expr.X_add_number;
4309 if (mask == M_BGEL_I)
4311 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4313 macro_build ((char *) NULL, &icnt, &offset_expr,
4314 likely ? "bgezl" : "bgez", "s,p", sreg);
4317 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4319 macro_build ((char *) NULL, &icnt, &offset_expr,
4320 likely ? "bgtzl" : "bgtz", "s,p", sreg);
4323 maxnum = 0x7fffffff;
4324 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4331 maxnum = - maxnum - 1;
4332 if (imm_expr.X_op == O_constant
4333 && imm_expr.X_add_number <= maxnum
4334 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4337 /* result is always true */
4338 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
4339 macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p");
4342 set_at (&icnt, sreg, 0);
4343 macro_build ((char *) NULL, &icnt, &offset_expr,
4344 likely ? "beql" : "beq", "s,t,p", AT, 0);
4354 macro_build ((char *) NULL, &icnt, &offset_expr,
4355 likely ? "beql" : "beq", "s,t,p", 0, treg);
4358 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4359 "d,v,t", AT, sreg, treg);
4360 macro_build ((char *) NULL, &icnt, &offset_expr,
4361 likely ? "beql" : "beq", "s,t,p", AT, 0);
4369 && imm_expr.X_op == O_constant
4370 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4372 if (imm_expr.X_op != O_constant)
4373 as_bad (_("Unsupported large constant"));
4374 ++imm_expr.X_add_number;
4378 if (mask == M_BGEUL_I)
4380 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4382 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4384 macro_build ((char *) NULL, &icnt, &offset_expr,
4385 likely ? "bnel" : "bne", "s,t,p", sreg, 0);
4388 set_at (&icnt, sreg, 1);
4389 macro_build ((char *) NULL, &icnt, &offset_expr,
4390 likely ? "beql" : "beq", "s,t,p", AT, 0);
4398 macro_build ((char *) NULL, &icnt, &offset_expr,
4399 likely ? "bgtzl" : "bgtz", "s,p", sreg);
4404 macro_build ((char *) NULL, &icnt, &offset_expr,
4405 likely ? "bltzl" : "bltz", "s,p", treg);
4408 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4410 macro_build ((char *) NULL, &icnt, &offset_expr,
4411 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4419 macro_build ((char *) NULL, &icnt, &offset_expr,
4420 likely ? "bnel" : "bne", "s,t,p", sreg, 0);
4425 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4426 "d,v,t", AT, treg, sreg);
4427 macro_build ((char *) NULL, &icnt, &offset_expr,
4428 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4436 macro_build ((char *) NULL, &icnt, &offset_expr,
4437 likely ? "blezl" : "blez", "s,p", sreg);
4442 macro_build ((char *) NULL, &icnt, &offset_expr,
4443 likely ? "bgezl" : "bgez", "s,p", treg);
4446 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4448 macro_build ((char *) NULL, &icnt, &offset_expr,
4449 likely ? "beql" : "beq", "s,t,p", AT, 0);
4455 maxnum = 0x7fffffff;
4456 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4463 if (imm_expr.X_op == O_constant
4464 && imm_expr.X_add_number >= maxnum
4465 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4467 if (imm_expr.X_op != O_constant)
4468 as_bad (_("Unsupported large constant"));
4469 ++imm_expr.X_add_number;
4473 if (mask == M_BLTL_I)
4475 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4477 macro_build ((char *) NULL, &icnt, &offset_expr,
4478 likely ? "bltzl" : "bltz", "s,p", sreg);
4481 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4483 macro_build ((char *) NULL, &icnt, &offset_expr,
4484 likely ? "blezl" : "blez", "s,p", sreg);
4487 set_at (&icnt, sreg, 0);
4488 macro_build ((char *) NULL, &icnt, &offset_expr,
4489 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4497 macro_build ((char *) NULL, &icnt, &offset_expr,
4498 likely ? "beql" : "beq", "s,t,p", sreg, 0);
4503 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4504 "d,v,t", AT, treg, sreg);
4505 macro_build ((char *) NULL, &icnt, &offset_expr,
4506 likely ? "beql" : "beq", "s,t,p", AT, 0);
4514 && imm_expr.X_op == O_constant
4515 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4517 if (imm_expr.X_op != O_constant)
4518 as_bad (_("Unsupported large constant"));
4519 ++imm_expr.X_add_number;
4523 if (mask == M_BLTUL_I)
4525 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4527 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4529 macro_build ((char *) NULL, &icnt, &offset_expr,
4530 likely ? "beql" : "beq",
4534 set_at (&icnt, sreg, 1);
4535 macro_build ((char *) NULL, &icnt, &offset_expr,
4536 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4544 macro_build ((char *) NULL, &icnt, &offset_expr,
4545 likely ? "bltzl" : "bltz", "s,p", sreg);
4550 macro_build ((char *) NULL, &icnt, &offset_expr,
4551 likely ? "bgtzl" : "bgtz", "s,p", treg);
4554 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4556 macro_build ((char *) NULL, &icnt, &offset_expr,
4557 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4567 macro_build ((char *) NULL, &icnt, &offset_expr,
4568 likely ? "bnel" : "bne", "s,t,p", 0, treg);
4571 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4574 macro_build ((char *) NULL, &icnt, &offset_expr,
4575 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4590 as_warn (_("Divide by zero."));
4592 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4595 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4600 mips_emit_delays (TRUE);
4601 ++mips_opts.noreorder;
4602 mips_any_noreorder = 1;
4605 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4606 "s,t,q", treg, 0, 7);
4607 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4608 dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4612 expr1.X_add_number = 8;
4613 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4614 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4615 dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4616 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4619 expr1.X_add_number = -1;
4620 macro_build ((char *) NULL, &icnt, &expr1,
4621 dbl ? "daddiu" : "addiu",
4622 "t,r,j", AT, 0, (int) BFD_RELOC_LO16);
4623 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
4624 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT);
4627 expr1.X_add_number = 1;
4628 macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0,
4629 (int) BFD_RELOC_LO16);
4630 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsll32",
4631 "d,w,<", AT, AT, 31);
4635 expr1.X_add_number = 0x80000000;
4636 macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT,
4637 (int) BFD_RELOC_HI16);
4641 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4642 "s,t,q", sreg, AT, 6);
4643 /* We want to close the noreorder block as soon as possible, so
4644 that later insns are available for delay slot filling. */
4645 --mips_opts.noreorder;
4649 expr1.X_add_number = 8;
4650 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT);
4651 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
4654 /* We want to close the noreorder block as soon as possible, so
4655 that later insns are available for delay slot filling. */
4656 --mips_opts.noreorder;
4658 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4661 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d", dreg);
4700 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4702 as_warn (_("Divide by zero."));
4704 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4707 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4711 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4713 if (strcmp (s2, "mflo") == 0)
4714 move_register (&icnt, dreg, sreg);
4716 move_register (&icnt, dreg, 0);
4719 if (imm_expr.X_op == O_constant
4720 && imm_expr.X_add_number == -1
4721 && s[strlen (s) - 1] != 'u')
4723 if (strcmp (s2, "mflo") == 0)
4725 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4726 dbl ? "dneg" : "neg", "d,w", dreg, sreg);
4729 move_register (&icnt, dreg, 0);
4733 load_register (&icnt, AT, &imm_expr, dbl);
4734 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4736 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg);
4755 mips_emit_delays (TRUE);
4756 ++mips_opts.noreorder;
4757 mips_any_noreorder = 1;
4760 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4761 "s,t,q", treg, 0, 7);
4762 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4764 /* We want to close the noreorder block as soon as possible, so
4765 that later insns are available for delay slot filling. */
4766 --mips_opts.noreorder;
4770 expr1.X_add_number = 8;
4771 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4772 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4775 /* We want to close the noreorder block as soon as possible, so
4776 that later insns are available for delay slot filling. */
4777 --mips_opts.noreorder;
4778 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4781 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg);
4787 /* Load the address of a symbol into a register. If breg is not
4788 zero, we then add a base register to it. */
4790 if (dbl && HAVE_32BIT_GPRS)
4791 as_warn (_("dla used to load 32-bit register"));
4793 if (! dbl && HAVE_64BIT_OBJECTS)
4794 as_warn (_("la used to load 64-bit address"));
4796 if (offset_expr.X_op == O_constant
4797 && offset_expr.X_add_number >= -0x8000
4798 && offset_expr.X_add_number < 0x8000)
4800 macro_build ((char *) NULL, &icnt, &offset_expr,
4801 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4802 "t,r,j", treg, sreg, (int) BFD_RELOC_LO16);
4817 /* When generating embedded PIC code, we permit expressions of
4820 la $treg,foo-bar($breg)
4821 where bar is an address in the current section. These are used
4822 when getting the addresses of functions. We don't permit
4823 X_add_number to be non-zero, because if the symbol is
4824 external the relaxing code needs to know that any addend is
4825 purely the offset to X_op_symbol. */
4826 if (mips_pic == EMBEDDED_PIC
4827 && offset_expr.X_op == O_subtract
4828 && (symbol_constant_p (offset_expr.X_op_symbol)
4829 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
4830 : (symbol_equated_p (offset_expr.X_op_symbol)
4832 (symbol_get_value_expression (offset_expr.X_op_symbol)
4835 && (offset_expr.X_add_number == 0
4836 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
4842 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4843 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
4847 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4848 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
4849 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4850 (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu",
4851 "d,v,t", tempreg, tempreg, breg);
4853 macro_build ((char *) NULL, &icnt, &offset_expr,
4854 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4855 "t,r,j", treg, tempreg, (int) BFD_RELOC_PCREL_LO16);
4861 if (offset_expr.X_op != O_symbol
4862 && offset_expr.X_op != O_constant)
4864 as_bad (_("expression too complex"));
4865 offset_expr.X_op = O_constant;
4868 if (offset_expr.X_op == O_constant)
4869 load_register (&icnt, tempreg, &offset_expr,
4870 ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
4871 ? (dbl || HAVE_64BIT_ADDRESSES)
4872 : HAVE_64BIT_ADDRESSES));
4873 else if (mips_pic == NO_PIC)
4875 /* If this is a reference to a GP relative symbol, we want
4876 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4878 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4879 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4880 If we have a constant, we need two instructions anyhow,
4881 so we may as well always use the latter form.
4883 With 64bit address space and a usable $at we want
4884 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4885 lui $at,<sym> (BFD_RELOC_HI16_S)
4886 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4887 daddiu $at,<sym> (BFD_RELOC_LO16)
4889 daddu $tempreg,$tempreg,$at
4891 If $at is already in use, we use a path which is suboptimal
4892 on superscalar processors.
4893 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4894 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4896 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4898 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4901 if (HAVE_64BIT_ADDRESSES)
4903 /* We don't do GP optimization for now because RELAX_ENCODE can't
4904 hold the data for such large chunks. */
4906 if (used_at == 0 && ! mips_opts.noat)
4908 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4909 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
4910 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4911 AT, (int) BFD_RELOC_HI16_S);
4912 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4913 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
4914 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4915 AT, AT, (int) BFD_RELOC_LO16);
4916 macro_build (p, &icnt, (expressionS *) NULL, "dsll32",
4917 "d,w,<", tempreg, tempreg, 0);
4918 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
4919 "d,v,t", tempreg, tempreg, AT);
4924 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4925 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
4926 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4927 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
4928 macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<",
4929 tempreg, tempreg, 16);
4930 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4931 tempreg, tempreg, (int) BFD_RELOC_HI16_S);
4932 macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<",
4933 tempreg, tempreg, 16);
4934 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4935 tempreg, tempreg, (int) BFD_RELOC_LO16);
4940 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
4941 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
4944 macro_build ((char *) NULL, &icnt, &offset_expr, "addiu",
4945 "t,r,j", tempreg, mips_gp_register,
4946 (int) BFD_RELOC_GPREL16);
4947 p = frag_var (rs_machine_dependent, 8, 0,
4948 RELAX_ENCODE (4, 8, 0, 4, 0,
4949 mips_opts.warn_about_macros),
4950 offset_expr.X_add_symbol, 0, NULL);
4952 macro_build_lui (p, &icnt, &offset_expr, tempreg);
4955 macro_build (p, &icnt, &offset_expr, "addiu",
4956 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4959 else if (mips_pic == SVR4_PIC && ! mips_big_got)
4961 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
4963 /* If this is a reference to an external symbol, and there
4964 is no constant, we want
4965 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4966 or if tempreg is PIC_CALL_REG
4967 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4968 For a local symbol, we want
4969 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4971 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4973 If we have a small constant, and this is a reference to
4974 an external symbol, we want
4975 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4977 addiu $tempreg,$tempreg,<constant>
4978 For a local symbol, we want the same instruction
4979 sequence, but we output a BFD_RELOC_LO16 reloc on the
4982 If we have a large constant, and this is a reference to
4983 an external symbol, we want
4984 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4985 lui $at,<hiconstant>
4986 addiu $at,$at,<loconstant>
4987 addu $tempreg,$tempreg,$at
4988 For a local symbol, we want the same instruction
4989 sequence, but we output a BFD_RELOC_LO16 reloc on the
4992 For NewABI, we want for local or external data addresses
4993 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4994 For a local function symbol, we want
4995 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4997 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5000 expr1.X_add_number = offset_expr.X_add_number;
5001 offset_expr.X_add_number = 0;
5003 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
5004 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
5005 else if (HAVE_NEWABI)
5006 lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_DISP;
5007 macro_build ((char *) NULL, &icnt, &offset_expr,
5008 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5009 "t,o(b)", tempreg, lw_reloc_type, mips_gp_register);
5010 if (expr1.X_add_number == 0)
5019 /* We're going to put in an addu instruction using
5020 tempreg, so we may as well insert the nop right
5022 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5026 p = frag_var (rs_machine_dependent, 8 - off, 0,
5027 RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0,
5029 ? mips_opts.warn_about_macros
5031 offset_expr.X_add_symbol, 0, NULL);
5034 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5037 macro_build (p, &icnt, &expr1,
5038 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5039 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5040 /* FIXME: If breg == 0, and the next instruction uses
5041 $tempreg, then if this variant case is used an extra
5042 nop will be generated. */
5044 else if (expr1.X_add_number >= -0x8000
5045 && expr1.X_add_number < 0x8000)
5047 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5049 macro_build ((char *) NULL, &icnt, &expr1,
5050 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5051 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5052 frag_var (rs_machine_dependent, 0, 0,
5053 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
5054 offset_expr.X_add_symbol, 0, NULL);
5060 /* If we are going to add in a base register, and the
5061 target register and the base register are the same,
5062 then we are using AT as a temporary register. Since
5063 we want to load the constant into AT, we add our
5064 current AT (from the global offset table) and the
5065 register into the register now, and pretend we were
5066 not using a base register. */
5071 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5073 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5074 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5075 "d,v,t", treg, AT, breg);
5081 /* Set mips_optimize around the lui instruction to avoid
5082 inserting an unnecessary nop after the lw. */
5083 hold_mips_optimize = mips_optimize;
5085 macro_build_lui (NULL, &icnt, &expr1, AT);
5086 mips_optimize = hold_mips_optimize;
5088 macro_build ((char *) NULL, &icnt, &expr1,
5089 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5090 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
5091 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5092 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5093 "d,v,t", tempreg, tempreg, AT);
5094 frag_var (rs_machine_dependent, 0, 0,
5095 RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0),
5096 offset_expr.X_add_symbol, 0, NULL);
5100 else if (mips_pic == SVR4_PIC)
5104 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5105 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5106 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5108 /* This is the large GOT case. If this is a reference to an
5109 external symbol, and there is no constant, we want
5110 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5111 addu $tempreg,$tempreg,$gp
5112 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5113 or if tempreg is PIC_CALL_REG
5114 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5115 addu $tempreg,$tempreg,$gp
5116 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5117 For a local symbol, we want
5118 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5120 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5122 If we have a small constant, and this is a reference to
5123 an external symbol, we want
5124 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5125 addu $tempreg,$tempreg,$gp
5126 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5128 addiu $tempreg,$tempreg,<constant>
5129 For a local symbol, we want
5130 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5132 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5134 If we have a large constant, and this is a reference to
5135 an external symbol, we want
5136 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5137 addu $tempreg,$tempreg,$gp
5138 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5139 lui $at,<hiconstant>
5140 addiu $at,$at,<loconstant>
5141 addu $tempreg,$tempreg,$at
5142 For a local symbol, we want
5143 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5144 lui $at,<hiconstant>
5145 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5146 addu $tempreg,$tempreg,$at
5148 For NewABI, we want for local data addresses
5149 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5152 expr1.X_add_number = offset_expr.X_add_number;
5153 offset_expr.X_add_number = 0;
5155 if (reg_needs_delay (mips_gp_register))
5159 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
5161 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5162 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5164 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
5165 tempreg, lui_reloc_type);
5166 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5167 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5168 "d,v,t", tempreg, tempreg, mips_gp_register);
5169 macro_build ((char *) NULL, &icnt, &offset_expr,
5170 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5171 "t,o(b)", tempreg, lw_reloc_type, tempreg);
5172 if (expr1.X_add_number == 0)
5180 /* We're going to put in an addu instruction using
5181 tempreg, so we may as well insert the nop right
5183 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5188 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5189 RELAX_ENCODE (12 + off, 12 + gpdel, gpdel,
5192 ? mips_opts.warn_about_macros
5194 offset_expr.X_add_symbol, 0, NULL);
5196 else if (expr1.X_add_number >= -0x8000
5197 && expr1.X_add_number < 0x8000)
5199 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5201 macro_build ((char *) NULL, &icnt, &expr1,
5202 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5203 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5205 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5206 RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0,
5208 ? mips_opts.warn_about_macros
5210 offset_expr.X_add_symbol, 0, NULL);
5216 /* If we are going to add in a base register, and the
5217 target register and the base register are the same,
5218 then we are using AT as a temporary register. Since
5219 we want to load the constant into AT, we add our
5220 current AT (from the global offset table) and the
5221 register into the register now, and pretend we were
5222 not using a base register. */
5230 assert (tempreg == AT);
5231 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5233 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5234 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5235 "d,v,t", treg, AT, breg);
5240 /* Set mips_optimize around the lui instruction to avoid
5241 inserting an unnecessary nop after the lw. */
5242 hold_mips_optimize = mips_optimize;
5244 macro_build_lui (NULL, &icnt, &expr1, AT);
5245 mips_optimize = hold_mips_optimize;
5247 macro_build ((char *) NULL, &icnt, &expr1,
5248 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5249 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
5250 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5251 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5252 "d,v,t", dreg, dreg, AT);
5254 p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0,
5255 RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel,
5258 ? mips_opts.warn_about_macros
5260 offset_expr.X_add_symbol, 0, NULL);
5267 /* This is needed because this instruction uses $gp, but
5268 the first instruction on the main stream does not. */
5269 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5274 local_reloc_type = (int) BFD_RELOC_MIPS_GOT_DISP;
5275 macro_build (p, &icnt, &offset_expr,
5276 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5281 if (expr1.X_add_number == 0 && HAVE_NEWABI)
5283 /* BFD_RELOC_MIPS_GOT_DISP is sufficient for newabi */
5286 if (expr1.X_add_number >= -0x8000
5287 && expr1.X_add_number < 0x8000)
5289 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5291 macro_build (p, &icnt, &expr1,
5292 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5293 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5294 /* FIXME: If add_number is 0, and there was no base
5295 register, the external symbol case ended with a load,
5296 so if the symbol turns out to not be external, and
5297 the next instruction uses tempreg, an unnecessary nop
5298 will be inserted. */
5304 /* We must add in the base register now, as in the
5305 external symbol case. */
5306 assert (tempreg == AT);
5307 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5309 macro_build (p, &icnt, (expressionS *) NULL,
5310 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5311 "d,v,t", treg, AT, breg);
5314 /* We set breg to 0 because we have arranged to add
5315 it in in both cases. */
5319 macro_build_lui (p, &icnt, &expr1, AT);
5321 macro_build (p, &icnt, &expr1,
5322 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5323 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
5325 macro_build (p, &icnt, (expressionS *) NULL,
5326 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5327 "d,v,t", tempreg, tempreg, AT);
5331 else if (mips_pic == EMBEDDED_PIC)
5334 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5336 macro_build ((char *) NULL, &icnt, &offset_expr,
5337 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j",
5338 tempreg, mips_gp_register, (int) BFD_RELOC_GPREL16);
5347 if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
5348 s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu";
5350 s = HAVE_64BIT_ADDRESSES ? "daddu" : "addu";
5352 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s,
5353 "d,v,t", treg, tempreg, breg);
5362 /* The j instruction may not be used in PIC code, since it
5363 requires an absolute address. We convert it to a b
5365 if (mips_pic == NO_PIC)
5366 macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a");
5368 macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p");
5371 /* The jal instructions must be handled as macros because when
5372 generating PIC code they expand to multi-instruction
5373 sequences. Normally they are simple instructions. */
5378 if (mips_pic == NO_PIC
5379 || mips_pic == EMBEDDED_PIC)
5380 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr",
5382 else if (mips_pic == SVR4_PIC)
5384 if (sreg != PIC_CALL_REG)
5385 as_warn (_("MIPS PIC call to register other than $25"));
5387 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr",
5391 if (mips_cprestore_offset < 0)
5392 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5395 if (! mips_frame_reg_valid)
5397 as_warn (_("No .frame pseudo-op used in PIC code"));
5398 /* Quiet this warning. */
5399 mips_frame_reg_valid = 1;
5401 if (! mips_cprestore_valid)
5403 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5404 /* Quiet this warning. */
5405 mips_cprestore_valid = 1;
5407 expr1.X_add_number = mips_cprestore_offset;
5408 macro_build_ldst_constoffset ((char *) NULL, &icnt, &expr1,
5409 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5410 mips_gp_register, mips_frame_reg);
5420 if (mips_pic == NO_PIC)
5421 macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a");
5422 else if (mips_pic == SVR4_PIC)
5426 /* If this is a reference to an external symbol, and we are
5427 using a small GOT, we want
5428 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5432 lw $gp,cprestore($sp)
5433 The cprestore value is set using the .cprestore
5434 pseudo-op. If we are using a big GOT, we want
5435 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5437 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5441 lw $gp,cprestore($sp)
5442 If the symbol is not external, we want
5443 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5445 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5448 lw $gp,cprestore($sp)
5450 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5451 jalr $ra,$25 (BFD_RELOC_MIPS_JALR)
5455 macro_build ((char *) NULL, &icnt, &offset_expr,
5456 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5457 "t,o(b)", PIC_CALL_REG,
5458 (int) BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5459 macro_build_jalr (icnt, &offset_expr);
5466 macro_build ((char *) NULL, &icnt, &offset_expr,
5467 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5468 "t,o(b)", PIC_CALL_REG,
5469 (int) BFD_RELOC_MIPS_CALL16, mips_gp_register);
5470 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5472 p = frag_var (rs_machine_dependent, 4, 0,
5473 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5474 offset_expr.X_add_symbol, 0, NULL);
5480 if (reg_needs_delay (mips_gp_register))
5484 macro_build ((char *) NULL, &icnt, &offset_expr, "lui",
5485 "t,u", PIC_CALL_REG,
5486 (int) BFD_RELOC_MIPS_CALL_HI16);
5487 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5488 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5489 "d,v,t", PIC_CALL_REG, PIC_CALL_REG,
5491 macro_build ((char *) NULL, &icnt, &offset_expr,
5492 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5493 "t,o(b)", PIC_CALL_REG,
5494 (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
5495 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5497 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5498 RELAX_ENCODE (16, 12 + gpdel, gpdel,
5500 offset_expr.X_add_symbol, 0, NULL);
5503 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5506 macro_build (p, &icnt, &offset_expr,
5507 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5508 "t,o(b)", PIC_CALL_REG,
5509 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
5511 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5514 macro_build (p, &icnt, &offset_expr,
5515 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5516 "t,r,j", PIC_CALL_REG, PIC_CALL_REG,
5517 (int) BFD_RELOC_LO16);
5518 macro_build_jalr (icnt, &offset_expr);
5520 if (mips_cprestore_offset < 0)
5521 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5524 if (! mips_frame_reg_valid)
5526 as_warn (_("No .frame pseudo-op used in PIC code"));
5527 /* Quiet this warning. */
5528 mips_frame_reg_valid = 1;
5530 if (! mips_cprestore_valid)
5532 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5533 /* Quiet this warning. */
5534 mips_cprestore_valid = 1;
5536 if (mips_opts.noreorder)
5537 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5539 expr1.X_add_number = mips_cprestore_offset;
5540 macro_build_ldst_constoffset ((char *) NULL, &icnt, &expr1,
5541 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5542 mips_gp_register, mips_frame_reg);
5546 else if (mips_pic == EMBEDDED_PIC)
5548 macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p");
5549 /* The linker may expand the call to a longer sequence which
5550 uses $at, so we must break rather than return. */
5575 /* Itbl support may require additional care here. */
5580 /* Itbl support may require additional care here. */
5585 /* Itbl support may require additional care here. */
5590 /* Itbl support may require additional care here. */
5602 if (mips_arch == CPU_R4650)
5604 as_bad (_("opcode not supported on this processor"));
5608 /* Itbl support may require additional care here. */
5613 /* Itbl support may require additional care here. */
5618 /* Itbl support may require additional care here. */
5638 if (breg == treg || coproc || lr)
5660 /* Itbl support may require additional care here. */
5665 /* Itbl support may require additional care here. */
5670 /* Itbl support may require additional care here. */
5675 /* Itbl support may require additional care here. */
5691 if (mips_arch == CPU_R4650)
5693 as_bad (_("opcode not supported on this processor"));
5698 /* Itbl support may require additional care here. */
5702 /* Itbl support may require additional care here. */
5707 /* Itbl support may require additional care here. */
5719 /* Itbl support may require additional care here. */
5720 if (mask == M_LWC1_AB
5721 || mask == M_SWC1_AB
5722 || mask == M_LDC1_AB
5723 || mask == M_SDC1_AB
5732 /* For embedded PIC, we allow loads where the offset is calculated
5733 by subtracting a symbol in the current segment from an unknown
5734 symbol, relative to a base register, e.g.:
5735 <op> $treg, <sym>-<localsym>($breg)
5736 This is used by the compiler for switch statements. */
5737 if (mips_pic == EMBEDDED_PIC
5738 && offset_expr.X_op == O_subtract
5739 && (symbol_constant_p (offset_expr.X_op_symbol)
5740 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
5741 : (symbol_equated_p (offset_expr.X_op_symbol)
5743 (symbol_get_value_expression (offset_expr.X_op_symbol)
5747 && (offset_expr.X_add_number == 0
5748 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
5750 /* For this case, we output the instructions:
5751 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5752 addiu $tempreg,$tempreg,$breg
5753 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5754 If the relocation would fit entirely in 16 bits, it would be
5756 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5757 instead, but that seems quite difficult. */
5758 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
5759 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
5760 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5761 ((bfd_arch_bits_per_address (stdoutput) == 32
5762 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
5763 ? "addu" : "daddu"),
5764 "d,v,t", tempreg, tempreg, breg);
5765 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, treg,
5766 (int) BFD_RELOC_PCREL_LO16, tempreg);
5772 if (offset_expr.X_op != O_constant
5773 && offset_expr.X_op != O_symbol)
5775 as_bad (_("expression too complex"));
5776 offset_expr.X_op = O_constant;
5779 /* A constant expression in PIC code can be handled just as it
5780 is in non PIC code. */
5781 if (mips_pic == NO_PIC
5782 || offset_expr.X_op == O_constant)
5786 /* If this is a reference to a GP relative symbol, and there
5787 is no base register, we want
5788 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5789 Otherwise, if there is no base register, we want
5790 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5791 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5792 If we have a constant, we need two instructions anyhow,
5793 so we always use the latter form.
5795 If we have a base register, and this is a reference to a
5796 GP relative symbol, we want
5797 addu $tempreg,$breg,$gp
5798 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5800 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5801 addu $tempreg,$tempreg,$breg
5802 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5803 With a constant we always use the latter case.
5805 With 64bit address space and no base register and $at usable,
5807 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5808 lui $at,<sym> (BFD_RELOC_HI16_S)
5809 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5812 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5813 If we have a base register, we want
5814 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5815 lui $at,<sym> (BFD_RELOC_HI16_S)
5816 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5820 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5822 Without $at we can't generate the optimal path for superscalar
5823 processors here since this would require two temporary registers.
5824 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5825 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5827 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5829 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5830 If we have a base register, we want
5831 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5832 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5834 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5836 daddu $tempreg,$tempreg,$breg
5837 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5839 If we have 64-bit addresses, as an optimization, for
5840 addresses which are 32-bit constants (e.g. kseg0/kseg1
5841 addresses) we fall back to the 32-bit address generation
5842 mechanism since it is more efficient. Note that due to
5843 the signed offset used by memory operations, the 32-bit
5844 range is shifted down by 32768 here. This code should
5845 probably attempt to generate 64-bit constants more
5846 efficiently in general.
5848 if (HAVE_64BIT_ADDRESSES
5849 && !(offset_expr.X_op == O_constant
5850 && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
5854 /* We don't do GP optimization for now because RELAX_ENCODE can't
5855 hold the data for such large chunks. */
5857 if (used_at == 0 && ! mips_opts.noat)
5859 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5860 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
5861 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5862 AT, (int) BFD_RELOC_HI16_S);
5863 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5864 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
5866 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
5867 "d,v,t", AT, AT, breg);
5868 macro_build (p, &icnt, (expressionS *) NULL, "dsll32",
5869 "d,w,<", tempreg, tempreg, 0);
5870 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
5871 "d,v,t", tempreg, tempreg, AT);
5872 macro_build (p, &icnt, &offset_expr, s,
5873 fmt, treg, (int) BFD_RELOC_LO16, tempreg);
5878 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5879 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
5880 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5881 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
5882 macro_build (p, &icnt, (expressionS *) NULL, "dsll",
5883 "d,w,<", tempreg, tempreg, 16);
5884 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5885 tempreg, tempreg, (int) BFD_RELOC_HI16_S);
5886 macro_build (p, &icnt, (expressionS *) NULL, "dsll",
5887 "d,w,<", tempreg, tempreg, 16);
5889 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
5890 "d,v,t", tempreg, tempreg, breg);
5891 macro_build (p, &icnt, &offset_expr, s,
5892 fmt, treg, (int) BFD_RELOC_LO16, tempreg);
5900 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
5901 || nopic_need_relax (offset_expr.X_add_symbol, 1))
5906 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5907 treg, (int) BFD_RELOC_GPREL16,
5909 p = frag_var (rs_machine_dependent, 8, 0,
5910 RELAX_ENCODE (4, 8, 0, 4, 0,
5911 (mips_opts.warn_about_macros
5913 && mips_opts.noat))),
5914 offset_expr.X_add_symbol, 0, NULL);
5917 macro_build_lui (p, &icnt, &offset_expr, tempreg);
5920 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
5921 (int) BFD_RELOC_LO16, tempreg);
5925 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
5926 || nopic_need_relax (offset_expr.X_add_symbol, 1))
5931 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5932 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5933 "d,v,t", tempreg, breg, mips_gp_register);
5934 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5935 treg, (int) BFD_RELOC_GPREL16, tempreg);
5936 p = frag_var (rs_machine_dependent, 12, 0,
5937 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5938 offset_expr.X_add_symbol, 0, NULL);
5940 macro_build_lui (p, &icnt, &offset_expr, tempreg);
5943 macro_build (p, &icnt, (expressionS *) NULL,
5944 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5945 "d,v,t", tempreg, tempreg, breg);
5948 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
5949 (int) BFD_RELOC_LO16, tempreg);
5952 else if (mips_pic == SVR4_PIC && ! mips_big_got)
5955 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5957 /* If this is a reference to an external symbol, we want
5958 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5960 <op> $treg,0($tempreg)
5962 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5964 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5965 <op> $treg,0($tempreg)
5966 If we have NewABI, we want
5967 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5968 If there is a base register, we add it to $tempreg before
5969 the <op>. If there is a constant, we stick it in the
5970 <op> instruction. We don't handle constants larger than
5971 16 bits, because we have no way to load the upper 16 bits
5972 (actually, we could handle them for the subset of cases
5973 in which we are not using $at). */
5974 assert (offset_expr.X_op == O_symbol);
5975 expr1.X_add_number = offset_expr.X_add_number;
5976 offset_expr.X_add_number = 0;
5978 lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_DISP;
5979 if (expr1.X_add_number < -0x8000
5980 || expr1.X_add_number >= 0x8000)
5981 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5983 macro_build ((char *) NULL, &icnt, &offset_expr,
5984 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", tempreg,
5985 (int) lw_reloc_type, mips_gp_register);
5986 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
5987 p = frag_var (rs_machine_dependent, 4, 0,
5988 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5989 offset_expr.X_add_symbol, 0, NULL);
5990 macro_build (p, &icnt, &offset_expr,
5991 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5992 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5994 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5995 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5996 "d,v,t", tempreg, tempreg, breg);
5997 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
5998 (int) BFD_RELOC_LO16, tempreg);
6000 else if (mips_pic == SVR4_PIC)
6005 /* If this is a reference to an external symbol, we want
6006 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6007 addu $tempreg,$tempreg,$gp
6008 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6009 <op> $treg,0($tempreg)
6011 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6013 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6014 <op> $treg,0($tempreg)
6015 If there is a base register, we add it to $tempreg before
6016 the <op>. If there is a constant, we stick it in the
6017 <op> instruction. We don't handle constants larger than
6018 16 bits, because we have no way to load the upper 16 bits
6019 (actually, we could handle them for the subset of cases
6020 in which we are not using $at).
6023 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6024 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6025 <op> $treg,0($tempreg)
6027 assert (offset_expr.X_op == O_symbol);
6028 expr1.X_add_number = offset_expr.X_add_number;
6029 offset_expr.X_add_number = 0;
6030 if (expr1.X_add_number < -0x8000
6031 || expr1.X_add_number >= 0x8000)
6032 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6035 macro_build ((char *) NULL, &icnt, &offset_expr,
6036 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6037 "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_PAGE,
6039 macro_build ((char *) NULL, &icnt, &offset_expr,
6040 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
6041 "t,r,j", tempreg, tempreg,
6042 BFD_RELOC_MIPS_GOT_OFST);
6044 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6045 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6046 "d,v,t", tempreg, tempreg, breg);
6047 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
6048 (int) BFD_RELOC_LO16, tempreg);
6055 if (reg_needs_delay (mips_gp_register))
6060 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
6061 tempreg, (int) BFD_RELOC_MIPS_GOT_HI16);
6062 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6063 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6064 "d,v,t", tempreg, tempreg, mips_gp_register);
6065 macro_build ((char *) NULL, &icnt, &offset_expr,
6066 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6067 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16,
6069 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
6070 RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0),
6071 offset_expr.X_add_symbol, 0, NULL);
6074 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
6077 macro_build (p, &icnt, &offset_expr,
6078 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6079 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16,
6082 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
6084 macro_build (p, &icnt, &offset_expr,
6085 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
6086 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
6088 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6089 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6090 "d,v,t", tempreg, tempreg, breg);
6091 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
6092 (int) BFD_RELOC_LO16, tempreg);
6094 else if (mips_pic == EMBEDDED_PIC)
6096 /* If there is no base register, we want
6097 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6098 If there is a base register, we want
6099 addu $tempreg,$breg,$gp
6100 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6102 assert (offset_expr.X_op == O_symbol);
6105 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6106 treg, (int) BFD_RELOC_GPREL16, mips_gp_register);
6111 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6112 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6113 "d,v,t", tempreg, breg, mips_gp_register);
6114 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6115 treg, (int) BFD_RELOC_GPREL16, tempreg);
6128 load_register (&icnt, treg, &imm_expr, 0);
6132 load_register (&icnt, treg, &imm_expr, 1);
6136 if (imm_expr.X_op == O_constant)
6138 load_register (&icnt, AT, &imm_expr, 0);
6139 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6140 "mtc1", "t,G", AT, treg);
6145 assert (offset_expr.X_op == O_symbol
6146 && strcmp (segment_name (S_GET_SEGMENT
6147 (offset_expr.X_add_symbol)),
6149 && offset_expr.X_add_number == 0);
6150 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
6151 treg, (int) BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6156 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6157 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6158 order 32 bits of the value and the low order 32 bits are either
6159 zero or in OFFSET_EXPR. */
6160 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6162 if (HAVE_64BIT_GPRS)
6163 load_register (&icnt, treg, &imm_expr, 1);
6168 if (target_big_endian)
6180 load_register (&icnt, hreg, &imm_expr, 0);
6183 if (offset_expr.X_op == O_absent)
6184 move_register (&icnt, lreg, 0);
6187 assert (offset_expr.X_op == O_constant);
6188 load_register (&icnt, lreg, &offset_expr, 0);
6195 /* We know that sym is in the .rdata section. First we get the
6196 upper 16 bits of the address. */
6197 if (mips_pic == NO_PIC)
6199 macro_build_lui (NULL, &icnt, &offset_expr, AT);
6201 else if (mips_pic == SVR4_PIC)
6203 macro_build ((char *) NULL, &icnt, &offset_expr,
6204 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6205 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
6208 else if (mips_pic == EMBEDDED_PIC)
6210 /* For embedded PIC we pick up the entire address off $gp in
6211 a single instruction. */
6212 macro_build ((char *) NULL, &icnt, &offset_expr,
6213 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j", AT,
6214 mips_gp_register, (int) BFD_RELOC_GPREL16);
6215 offset_expr.X_op = O_constant;
6216 offset_expr.X_add_number = 0;
6221 /* Now we load the register(s). */
6222 if (HAVE_64BIT_GPRS)
6223 macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)",
6224 treg, (int) BFD_RELOC_LO16, AT);
6227 macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)",
6228 treg, (int) BFD_RELOC_LO16, AT);
6231 /* FIXME: How in the world do we deal with the possible
6233 offset_expr.X_add_number += 4;
6234 macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)",
6235 treg + 1, (int) BFD_RELOC_LO16, AT);
6239 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6240 does not become a variant frag. */
6241 frag_wane (frag_now);
6247 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6248 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6249 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6250 the value and the low order 32 bits are either zero or in
6252 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6254 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS);
6255 if (HAVE_64BIT_FPRS)
6257 assert (HAVE_64BIT_GPRS);
6258 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6259 "dmtc1", "t,S", AT, treg);
6263 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6264 "mtc1", "t,G", AT, treg + 1);
6265 if (offset_expr.X_op == O_absent)
6266 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6267 "mtc1", "t,G", 0, treg);
6270 assert (offset_expr.X_op == O_constant);
6271 load_register (&icnt, AT, &offset_expr, 0);
6272 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6273 "mtc1", "t,G", AT, treg);
6279 assert (offset_expr.X_op == O_symbol
6280 && offset_expr.X_add_number == 0);
6281 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
6282 if (strcmp (s, ".lit8") == 0)
6284 if (mips_opts.isa != ISA_MIPS1)
6286 macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
6287 "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL,
6291 breg = mips_gp_register;
6292 r = BFD_RELOC_MIPS_LITERAL;
6297 assert (strcmp (s, RDATA_SECTION_NAME) == 0);
6298 if (mips_pic == SVR4_PIC)
6299 macro_build ((char *) NULL, &icnt, &offset_expr,
6300 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6301 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
6305 /* FIXME: This won't work for a 64 bit address. */
6306 macro_build_lui (NULL, &icnt, &offset_expr, AT);
6309 if (mips_opts.isa != ISA_MIPS1)
6311 macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
6312 "T,o(b)", treg, (int) BFD_RELOC_LO16, AT);
6314 /* To avoid confusion in tc_gen_reloc, we must ensure
6315 that this does not become a variant frag. */
6316 frag_wane (frag_now);
6327 if (mips_arch == CPU_R4650)
6329 as_bad (_("opcode not supported on this processor"));
6332 /* Even on a big endian machine $fn comes before $fn+1. We have
6333 to adjust when loading from memory. */
6336 assert (mips_opts.isa == ISA_MIPS1);
6337 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
6338 target_big_endian ? treg + 1 : treg,
6340 /* FIXME: A possible overflow which I don't know how to deal
6342 offset_expr.X_add_number += 4;
6343 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
6344 target_big_endian ? treg : treg + 1,
6347 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6348 does not become a variant frag. */
6349 frag_wane (frag_now);
6358 * The MIPS assembler seems to check for X_add_number not
6359 * being double aligned and generating:
6362 * addiu at,at,%lo(foo+1)
6365 * But, the resulting address is the same after relocation so why
6366 * generate the extra instruction?
6368 if (mips_arch == CPU_R4650)
6370 as_bad (_("opcode not supported on this processor"));
6373 /* Itbl support may require additional care here. */
6375 if (mips_opts.isa != ISA_MIPS1)
6386 if (mips_arch == CPU_R4650)
6388 as_bad (_("opcode not supported on this processor"));
6392 if (mips_opts.isa != ISA_MIPS1)
6400 /* Itbl support may require additional care here. */
6405 if (HAVE_64BIT_GPRS)
6416 if (HAVE_64BIT_GPRS)
6426 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6427 loads for the case of doing a pair of loads to simulate an 'ld'.
6428 This is not currently done by the compiler, and assembly coders
6429 writing embedded-pic code can cope. */
6431 if (offset_expr.X_op != O_symbol
6432 && offset_expr.X_op != O_constant)
6434 as_bad (_("expression too complex"));
6435 offset_expr.X_op = O_constant;
6438 /* Even on a big endian machine $fn comes before $fn+1. We have
6439 to adjust when loading from memory. We set coproc if we must
6440 load $fn+1 first. */
6441 /* Itbl support may require additional care here. */
6442 if (! target_big_endian)
6445 if (mips_pic == NO_PIC
6446 || offset_expr.X_op == O_constant)
6450 /* If this is a reference to a GP relative symbol, we want
6451 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6452 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6453 If we have a base register, we use this
6455 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6456 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6457 If this is not a GP relative symbol, we want
6458 lui $at,<sym> (BFD_RELOC_HI16_S)
6459 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6460 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6461 If there is a base register, we add it to $at after the
6462 lui instruction. If there is a constant, we always use
6464 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6465 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6477 tempreg = mips_gp_register;
6484 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6485 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6486 "d,v,t", AT, breg, mips_gp_register);
6492 /* Itbl support may require additional care here. */
6493 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6494 coproc ? treg + 1 : treg,
6495 (int) BFD_RELOC_GPREL16, tempreg);
6496 offset_expr.X_add_number += 4;
6498 /* Set mips_optimize to 2 to avoid inserting an
6500 hold_mips_optimize = mips_optimize;
6502 /* Itbl support may require additional care here. */
6503 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6504 coproc ? treg : treg + 1,
6505 (int) BFD_RELOC_GPREL16, tempreg);
6506 mips_optimize = hold_mips_optimize;
6508 p = frag_var (rs_machine_dependent, 12 + off, 0,
6509 RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1,
6510 used_at && mips_opts.noat),
6511 offset_expr.X_add_symbol, 0, NULL);
6513 /* We just generated two relocs. When tc_gen_reloc
6514 handles this case, it will skip the first reloc and
6515 handle the second. The second reloc already has an
6516 extra addend of 4, which we added above. We must
6517 subtract it out, and then subtract another 4 to make
6518 the first reloc come out right. The second reloc
6519 will come out right because we are going to add 4 to
6520 offset_expr when we build its instruction below.
6522 If we have a symbol, then we don't want to include
6523 the offset, because it will wind up being included
6524 when we generate the reloc. */
6526 if (offset_expr.X_op == O_constant)
6527 offset_expr.X_add_number -= 8;
6530 offset_expr.X_add_number = -4;
6531 offset_expr.X_op = O_constant;
6534 macro_build_lui (p, &icnt, &offset_expr, AT);
6539 macro_build (p, &icnt, (expressionS *) NULL,
6540 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6541 "d,v,t", AT, breg, AT);
6545 /* Itbl support may require additional care here. */
6546 macro_build (p, &icnt, &offset_expr, s, fmt,
6547 coproc ? treg + 1 : treg,
6548 (int) BFD_RELOC_LO16, AT);
6551 /* FIXME: How do we handle overflow here? */
6552 offset_expr.X_add_number += 4;
6553 /* Itbl support may require additional care here. */
6554 macro_build (p, &icnt, &offset_expr, s, fmt,
6555 coproc ? treg : treg + 1,
6556 (int) BFD_RELOC_LO16, AT);
6558 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6562 /* If this is a reference to an external symbol, we want
6563 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6568 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6570 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6571 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6572 If there is a base register we add it to $at before the
6573 lwc1 instructions. If there is a constant we include it
6574 in the lwc1 instructions. */
6576 expr1.X_add_number = offset_expr.X_add_number;
6577 offset_expr.X_add_number = 0;
6578 if (expr1.X_add_number < -0x8000
6579 || expr1.X_add_number >= 0x8000 - 4)
6580 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6585 frag_grow (24 + off);
6586 macro_build ((char *) NULL, &icnt, &offset_expr,
6587 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", AT,
6588 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
6589 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
6591 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6592 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6593 "d,v,t", AT, breg, AT);
6594 /* Itbl support may require additional care here. */
6595 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6596 coproc ? treg + 1 : treg,
6597 (int) BFD_RELOC_LO16, AT);
6598 expr1.X_add_number += 4;
6600 /* Set mips_optimize to 2 to avoid inserting an undesired
6602 hold_mips_optimize = mips_optimize;
6604 /* Itbl support may require additional care here. */
6605 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6606 coproc ? treg : treg + 1,
6607 (int) BFD_RELOC_LO16, AT);
6608 mips_optimize = hold_mips_optimize;
6610 (void) frag_var (rs_machine_dependent, 0, 0,
6611 RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0),
6612 offset_expr.X_add_symbol, 0, NULL);
6614 else if (mips_pic == SVR4_PIC)
6619 /* If this is a reference to an external symbol, we want
6620 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6622 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6627 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6629 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6630 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6631 If there is a base register we add it to $at before the
6632 lwc1 instructions. If there is a constant we include it
6633 in the lwc1 instructions. */
6635 expr1.X_add_number = offset_expr.X_add_number;
6636 offset_expr.X_add_number = 0;
6637 if (expr1.X_add_number < -0x8000
6638 || expr1.X_add_number >= 0x8000 - 4)
6639 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6640 if (reg_needs_delay (mips_gp_register))
6649 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
6650 AT, (int) BFD_RELOC_MIPS_GOT_HI16);
6651 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6652 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6653 "d,v,t", AT, AT, mips_gp_register);
6654 macro_build ((char *) NULL, &icnt, &offset_expr,
6655 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6656 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT);
6657 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
6659 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6660 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6661 "d,v,t", AT, breg, AT);
6662 /* Itbl support may require additional care here. */
6663 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6664 coproc ? treg + 1 : treg,
6665 (int) BFD_RELOC_LO16, AT);
6666 expr1.X_add_number += 4;
6668 /* Set mips_optimize to 2 to avoid inserting an undesired
6670 hold_mips_optimize = mips_optimize;
6672 /* Itbl support may require additional care here. */
6673 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6674 coproc ? treg : treg + 1,
6675 (int) BFD_RELOC_LO16, AT);
6676 mips_optimize = hold_mips_optimize;
6677 expr1.X_add_number -= 4;
6679 p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0,
6680 RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel,
6681 8 + gpdel + off, 1, 0),
6682 offset_expr.X_add_symbol, 0, NULL);
6685 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
6688 macro_build (p, &icnt, &offset_expr,
6689 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6690 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
6693 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
6697 macro_build (p, &icnt, (expressionS *) NULL,
6698 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6699 "d,v,t", AT, breg, AT);
6702 /* Itbl support may require additional care here. */
6703 macro_build (p, &icnt, &expr1, s, fmt,
6704 coproc ? treg + 1 : treg,
6705 (int) BFD_RELOC_LO16, AT);
6707 expr1.X_add_number += 4;
6709 /* Set mips_optimize to 2 to avoid inserting an undesired
6711 hold_mips_optimize = mips_optimize;
6713 /* Itbl support may require additional care here. */
6714 macro_build (p, &icnt, &expr1, s, fmt,
6715 coproc ? treg : treg + 1,
6716 (int) BFD_RELOC_LO16, AT);
6717 mips_optimize = hold_mips_optimize;
6719 else if (mips_pic == EMBEDDED_PIC)
6721 /* If there is no base register, we use
6722 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6723 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6724 If we have a base register, we use
6726 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6727 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6731 tempreg = mips_gp_register;
6736 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6737 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6738 "d,v,t", AT, breg, mips_gp_register);
6743 /* Itbl support may require additional care here. */
6744 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6745 coproc ? treg + 1 : treg,
6746 (int) BFD_RELOC_GPREL16, tempreg);
6747 offset_expr.X_add_number += 4;
6748 /* Itbl support may require additional care here. */
6749 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6750 coproc ? treg : treg + 1,
6751 (int) BFD_RELOC_GPREL16, tempreg);
6767 assert (HAVE_32BIT_ADDRESSES);
6768 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
6769 (int) BFD_RELOC_LO16, breg);
6770 offset_expr.X_add_number += 4;
6771 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1,
6772 (int) BFD_RELOC_LO16, breg);
6775 /* New code added to support COPZ instructions.
6776 This code builds table entries out of the macros in mip_opcodes.
6777 R4000 uses interlocks to handle coproc delays.
6778 Other chips (like the R3000) require nops to be inserted for delays.
6780 FIXME: Currently, we require that the user handle delays.
6781 In order to fill delay slots for non-interlocked chips,
6782 we must have a way to specify delays based on the coprocessor.
6783 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6784 What are the side-effects of the cop instruction?
6785 What cache support might we have and what are its effects?
6786 Both coprocessor & memory require delays. how long???
6787 What registers are read/set/modified?
6789 If an itbl is provided to interpret cop instructions,
6790 this knowledge can be encoded in the itbl spec. */
6804 /* For now we just do C (same as Cz). The parameter will be
6805 stored in insn_opcode by mips_ip. */
6806 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "C",
6811 move_register (&icnt, dreg, sreg);
6814 #ifdef LOSING_COMPILER
6816 /* Try and see if this is a new itbl instruction.
6817 This code builds table entries out of the macros in mip_opcodes.
6818 FIXME: For now we just assemble the expression and pass it's
6819 value along as a 32-bit immediate.
6820 We may want to have the assembler assemble this value,
6821 so that we gain the assembler's knowledge of delay slots,
6823 Would it be more efficient to use mask (id) here? */
6824 if (itbl_have_entries
6825 && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
6827 s = ip->insn_mo->name;
6829 coproc = ITBL_DECODE_PNUM (immed_expr);;
6830 macro_build ((char *) NULL, &icnt, &immed_expr, s, "C");
6837 as_warn (_("Macro used $at after \".set noat\""));
6842 struct mips_cl_insn *ip;
6844 register int treg, sreg, dreg, breg;
6860 bfd_reloc_code_real_type r;
6863 treg = (ip->insn_opcode >> 16) & 0x1f;
6864 dreg = (ip->insn_opcode >> 11) & 0x1f;
6865 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
6866 mask = ip->insn_mo->mask;
6868 expr1.X_op = O_constant;
6869 expr1.X_op_symbol = NULL;
6870 expr1.X_add_symbol = NULL;
6871 expr1.X_add_number = 1;
6875 #endif /* LOSING_COMPILER */
6880 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6881 dbl ? "dmultu" : "multu", "s,t", sreg, treg);
6882 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6889 /* The MIPS assembler some times generates shifts and adds. I'm
6890 not trying to be that fancy. GCC should do this for us
6892 load_register (&icnt, AT, &imm_expr, dbl);
6893 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6894 dbl ? "dmult" : "mult", "s,t", sreg, AT);
6895 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6909 mips_emit_delays (TRUE);
6910 ++mips_opts.noreorder;
6911 mips_any_noreorder = 1;
6913 load_register (&icnt, AT, &imm_expr, dbl);
6914 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6915 dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
6916 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6918 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6919 dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
6920 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d",
6923 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne",
6924 "s,t,q", dreg, AT, 6);
6927 expr1.X_add_number = 8;
6928 macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg,
6930 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
6932 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
6935 --mips_opts.noreorder;
6936 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", dreg);
6949 mips_emit_delays (TRUE);
6950 ++mips_opts.noreorder;
6951 mips_any_noreorder = 1;
6953 load_register (&icnt, AT, &imm_expr, dbl);
6954 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6955 dbl ? "dmultu" : "multu",
6956 "s,t", sreg, imm ? AT : treg);
6957 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d",
6959 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6962 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne",
6966 expr1.X_add_number = 8;
6967 macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0);
6968 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
6970 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
6973 --mips_opts.noreorder;
6977 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_arch))
6989 macro_build ((char *) NULL, &icnt, NULL, "dnegu",
6990 "d,w", tempreg, treg);
6991 macro_build ((char *) NULL, &icnt, NULL, "drorv",
6992 "d,t,s", dreg, sreg, tempreg);
6997 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
6998 "d,v,t", AT, 0, treg);
6999 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
7000 "d,t,s", AT, sreg, AT);
7001 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
7002 "d,t,s", dreg, sreg, treg);
7003 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
7004 "d,v,t", dreg, dreg, AT);
7008 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_arch))
7020 macro_build ((char *) NULL, &icnt, NULL, "negu",
7021 "d,w", tempreg, treg);
7022 macro_build ((char *) NULL, &icnt, NULL, "rorv",
7023 "d,t,s", dreg, sreg, tempreg);
7028 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
7029 "d,v,t", AT, 0, treg);
7030 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv",
7031 "d,t,s", AT, sreg, AT);
7032 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv",
7033 "d,t,s", dreg, sreg, treg);
7034 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
7035 "d,v,t", dreg, dreg, AT);
7043 if (imm_expr.X_op != O_constant)
7044 as_bad (_("Improper rotate count"));
7045 rot = imm_expr.X_add_number & 0x3f;
7046 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_arch))
7048 rot = (64 - rot) & 0x3f;
7050 macro_build ((char *) NULL, &icnt, NULL, "dror32",
7051 "d,w,<", dreg, sreg, rot - 32);
7053 macro_build ((char *) NULL, &icnt, NULL, "dror",
7054 "d,w,<", dreg, sreg, rot);
7059 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrl",
7060 "d,w,<", dreg, sreg, 0);
7063 l = (rot < 0x20) ? "dsll" : "dsll32";
7064 r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
7066 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
7067 "d,w,<", AT, sreg, rot);
7068 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
7069 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7070 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
7071 "d,v,t", dreg, dreg, AT);
7079 if (imm_expr.X_op != O_constant)
7080 as_bad (_("Improper rotate count"));
7081 rot = imm_expr.X_add_number & 0x1f;
7082 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_arch))
7084 macro_build ((char *) NULL, &icnt, NULL, "ror",
7085 "d,w,<", dreg, sreg, (32 - rot) & 0x1f);
7090 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
7091 "d,w,<", dreg, sreg, 0);
7094 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
7095 "d,w,<", AT, sreg, rot);
7096 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
7097 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7098 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
7099 "d,v,t", dreg, dreg, AT);
7104 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_arch))
7106 macro_build ((char *) NULL, &icnt, NULL, "drorv",
7107 "d,t,s", dreg, sreg, treg);
7110 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
7111 "d,v,t", AT, 0, treg);
7112 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
7113 "d,t,s", AT, sreg, AT);
7114 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
7115 "d,t,s", dreg, sreg, treg);
7116 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
7117 "d,v,t", dreg, dreg, AT);
7121 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_arch))
7123 macro_build ((char *) NULL, &icnt, NULL, "rorv",
7124 "d,t,s", dreg, sreg, treg);
7127 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
7128 "d,v,t", AT, 0, treg);
7129 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv",
7130 "d,t,s", AT, sreg, AT);
7131 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv",
7132 "d,t,s", dreg, sreg, treg);
7133 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
7134 "d,v,t", dreg, dreg, AT);
7142 if (imm_expr.X_op != O_constant)
7143 as_bad (_("Improper rotate count"));
7144 rot = imm_expr.X_add_number & 0x3f;
7145 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_arch))
7148 macro_build ((char *) NULL, &icnt, NULL, "dror32",
7149 "d,w,<", dreg, sreg, rot - 32);
7151 macro_build ((char *) NULL, &icnt, NULL, "dror",
7152 "d,w,<", dreg, sreg, rot);
7157 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrl",
7158 "d,w,<", dreg, sreg, 0);
7161 r = (rot < 0x20) ? "dsrl" : "dsrl32";
7162 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7164 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
7165 "d,w,<", AT, sreg, rot);
7166 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
7167 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7168 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
7169 "d,v,t", dreg, dreg, AT);
7177 if (imm_expr.X_op != O_constant)
7178 as_bad (_("Improper rotate count"));
7179 rot = imm_expr.X_add_number & 0x1f;
7180 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_arch))
7182 macro_build ((char *) NULL, &icnt, NULL, "ror",
7183 "d,w,<", dreg, sreg, rot);
7188 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
7189 "d,w,<", dreg, sreg, 0);
7192 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
7193 "d,w,<", AT, sreg, rot);
7194 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
7195 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7196 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
7197 "d,v,t", dreg, dreg, AT);
7202 if (mips_arch == CPU_R4650)
7204 as_bad (_("opcode not supported on this processor"));
7207 assert (mips_opts.isa == ISA_MIPS1);
7208 /* Even on a big endian machine $fn comes before $fn+1. We have
7209 to adjust when storing to memory. */
7210 macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
7211 target_big_endian ? treg + 1 : treg,
7212 (int) BFD_RELOC_LO16, breg);
7213 offset_expr.X_add_number += 4;
7214 macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
7215 target_big_endian ? treg : treg + 1,
7216 (int) BFD_RELOC_LO16, breg);
7221 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
7222 treg, (int) BFD_RELOC_LO16);
7224 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
7225 sreg, (int) BFD_RELOC_LO16);
7228 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
7229 "d,v,t", dreg, sreg, treg);
7230 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
7231 dreg, (int) BFD_RELOC_LO16);
7236 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7238 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
7239 sreg, (int) BFD_RELOC_LO16);
7244 as_warn (_("Instruction %s: result is always false"),
7246 move_register (&icnt, dreg, 0);
7249 if (imm_expr.X_op == O_constant
7250 && imm_expr.X_add_number >= 0
7251 && imm_expr.X_add_number < 0x10000)
7253 macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg,
7254 sreg, (int) BFD_RELOC_LO16);
7257 else if (imm_expr.X_op == O_constant
7258 && imm_expr.X_add_number > -0x8000
7259 && imm_expr.X_add_number < 0)
7261 imm_expr.X_add_number = -imm_expr.X_add_number;
7262 macro_build ((char *) NULL, &icnt, &imm_expr,
7263 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7264 "t,r,j", dreg, sreg,
7265 (int) BFD_RELOC_LO16);
7270 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7271 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
7272 "d,v,t", dreg, sreg, AT);
7275 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg,
7276 (int) BFD_RELOC_LO16);
7281 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
7287 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
7289 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7290 (int) BFD_RELOC_LO16);
7293 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
7295 if (imm_expr.X_op == O_constant
7296 && imm_expr.X_add_number >= -0x8000
7297 && imm_expr.X_add_number < 0x8000)
7299 macro_build ((char *) NULL, &icnt, &imm_expr,
7300 mask == M_SGE_I ? "slti" : "sltiu",
7301 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
7306 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7307 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7308 mask == M_SGE_I ? "slt" : "sltu", "d,v,t", dreg, sreg,
7312 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7313 (int) BFD_RELOC_LO16);
7318 case M_SGT: /* sreg > treg <==> treg < sreg */
7324 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
7328 case M_SGT_I: /* sreg > I <==> I < sreg */
7334 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7335 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
7339 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7345 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
7347 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7348 (int) BFD_RELOC_LO16);
7351 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7357 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7358 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
7360 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7361 (int) BFD_RELOC_LO16);
7365 if (imm_expr.X_op == O_constant
7366 && imm_expr.X_add_number >= -0x8000
7367 && imm_expr.X_add_number < 0x8000)
7369 macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j",
7370 dreg, sreg, (int) BFD_RELOC_LO16);
7373 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7374 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
7379 if (imm_expr.X_op == O_constant
7380 && imm_expr.X_add_number >= -0x8000
7381 && imm_expr.X_add_number < 0x8000)
7383 macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j",
7384 dreg, sreg, (int) BFD_RELOC_LO16);
7387 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7388 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
7389 "d,v,t", dreg, sreg, AT);
7394 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
7395 "d,v,t", dreg, 0, treg);
7397 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
7398 "d,v,t", dreg, 0, sreg);
7401 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
7402 "d,v,t", dreg, sreg, treg);
7403 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
7404 "d,v,t", dreg, 0, dreg);
7409 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7411 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
7412 "d,v,t", dreg, 0, sreg);
7417 as_warn (_("Instruction %s: result is always true"),
7419 macro_build ((char *) NULL, &icnt, &expr1,
7420 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7421 "t,r,j", dreg, 0, (int) BFD_RELOC_LO16);
7424 if (imm_expr.X_op == O_constant
7425 && imm_expr.X_add_number >= 0
7426 && imm_expr.X_add_number < 0x10000)
7428 macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i",
7429 dreg, sreg, (int) BFD_RELOC_LO16);
7432 else if (imm_expr.X_op == O_constant
7433 && imm_expr.X_add_number > -0x8000
7434 && imm_expr.X_add_number < 0)
7436 imm_expr.X_add_number = -imm_expr.X_add_number;
7437 macro_build ((char *) NULL, &icnt, &imm_expr,
7438 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7439 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
7444 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7445 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
7446 "d,v,t", dreg, sreg, AT);
7449 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
7450 "d,v,t", dreg, 0, dreg);
7458 if (imm_expr.X_op == O_constant
7459 && imm_expr.X_add_number > -0x8000
7460 && imm_expr.X_add_number <= 0x8000)
7462 imm_expr.X_add_number = -imm_expr.X_add_number;
7463 macro_build ((char *) NULL, &icnt, &imm_expr,
7464 dbl ? "daddi" : "addi",
7465 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
7468 load_register (&icnt, AT, &imm_expr, dbl);
7469 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7470 dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
7476 if (imm_expr.X_op == O_constant
7477 && imm_expr.X_add_number > -0x8000
7478 && imm_expr.X_add_number <= 0x8000)
7480 imm_expr.X_add_number = -imm_expr.X_add_number;
7481 macro_build ((char *) NULL, &icnt, &imm_expr,
7482 dbl ? "daddiu" : "addiu",
7483 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
7486 load_register (&icnt, AT, &imm_expr, dbl);
7487 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7488 dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
7509 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7510 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "s,t", sreg,
7516 assert (mips_opts.isa == ISA_MIPS1);
7517 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
7518 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
7521 * Is the double cfc1 instruction a bug in the mips assembler;
7522 * or is there a reason for it?
7524 mips_emit_delays (TRUE);
7525 ++mips_opts.noreorder;
7526 mips_any_noreorder = 1;
7527 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G",
7529 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G",
7531 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7532 expr1.X_add_number = 3;
7533 macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg,
7534 (int) BFD_RELOC_LO16);
7535 expr1.X_add_number = 2;
7536 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT,
7537 (int) BFD_RELOC_LO16);
7538 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G",
7540 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7541 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7542 mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg);
7543 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G",
7545 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7546 --mips_opts.noreorder;
7555 if (offset_expr.X_add_number >= 0x7fff)
7556 as_bad (_("operand overflow"));
7557 if (! target_big_endian)
7558 ++offset_expr.X_add_number;
7559 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", AT,
7560 (int) BFD_RELOC_LO16, breg);
7561 if (! target_big_endian)
7562 --offset_expr.X_add_number;
7564 ++offset_expr.X_add_number;
7565 macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", treg,
7566 (int) BFD_RELOC_LO16, breg);
7567 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7569 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7583 if (offset_expr.X_add_number >= 0x8000 - off)
7584 as_bad (_("operand overflow"));
7589 if (! target_big_endian)
7590 offset_expr.X_add_number += off;
7591 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", tempreg,
7592 (int) BFD_RELOC_LO16, breg);
7593 if (! target_big_endian)
7594 offset_expr.X_add_number -= off;
7596 offset_expr.X_add_number += off;
7597 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", tempreg,
7598 (int) BFD_RELOC_LO16, breg);
7600 /* If necessary, move the result in tempreg the final destination. */
7601 if (treg == tempreg)
7603 /* Protect second load's delay slot. */
7604 if (!gpr_interlocks)
7605 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7606 move_register (&icnt, treg, tempreg);
7620 load_address (&icnt, AT, &offset_expr, &used_at);
7622 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7623 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7624 "d,v,t", AT, AT, breg);
7625 if (! target_big_endian)
7626 expr1.X_add_number = off;
7628 expr1.X_add_number = 0;
7629 macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg,
7630 (int) BFD_RELOC_LO16, AT);
7631 if (! target_big_endian)
7632 expr1.X_add_number = 0;
7634 expr1.X_add_number = off;
7635 macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7636 (int) BFD_RELOC_LO16, AT);
7642 load_address (&icnt, AT, &offset_expr, &used_at);
7644 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7645 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7646 "d,v,t", AT, AT, breg);
7647 if (target_big_endian)
7648 expr1.X_add_number = 0;
7649 macro_build ((char *) NULL, &icnt, &expr1,
7650 mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg,
7651 (int) BFD_RELOC_LO16, AT);
7652 if (target_big_endian)
7653 expr1.X_add_number = 1;
7655 expr1.X_add_number = 0;
7656 macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
7657 (int) BFD_RELOC_LO16, AT);
7658 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7660 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7665 if (offset_expr.X_add_number >= 0x7fff)
7666 as_bad (_("operand overflow"));
7667 if (target_big_endian)
7668 ++offset_expr.X_add_number;
7669 macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg,
7670 (int) BFD_RELOC_LO16, breg);
7671 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
7673 if (target_big_endian)
7674 --offset_expr.X_add_number;
7676 ++offset_expr.X_add_number;
7677 macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT,
7678 (int) BFD_RELOC_LO16, breg);
7691 if (offset_expr.X_add_number >= 0x8000 - off)
7692 as_bad (_("operand overflow"));
7693 if (! target_big_endian)
7694 offset_expr.X_add_number += off;
7695 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7696 (int) BFD_RELOC_LO16, breg);
7697 if (! target_big_endian)
7698 offset_expr.X_add_number -= off;
7700 offset_expr.X_add_number += off;
7701 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
7702 (int) BFD_RELOC_LO16, breg);
7716 load_address (&icnt, AT, &offset_expr, &used_at);
7718 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7719 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7720 "d,v,t", AT, AT, breg);
7721 if (! target_big_endian)
7722 expr1.X_add_number = off;
7724 expr1.X_add_number = 0;
7725 macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg,
7726 (int) BFD_RELOC_LO16, AT);
7727 if (! target_big_endian)
7728 expr1.X_add_number = 0;
7730 expr1.X_add_number = off;
7731 macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7732 (int) BFD_RELOC_LO16, AT);
7737 load_address (&icnt, AT, &offset_expr, &used_at);
7739 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7740 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7741 "d,v,t", AT, AT, breg);
7742 if (! target_big_endian)
7743 expr1.X_add_number = 0;
7744 macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7745 (int) BFD_RELOC_LO16, AT);
7746 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
7748 if (! target_big_endian)
7749 expr1.X_add_number = 1;
7751 expr1.X_add_number = 0;
7752 macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7753 (int) BFD_RELOC_LO16, AT);
7754 if (! target_big_endian)
7755 expr1.X_add_number = 0;
7757 expr1.X_add_number = 1;
7758 macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
7759 (int) BFD_RELOC_LO16, AT);
7760 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7762 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7767 /* FIXME: Check if this is one of the itbl macros, since they
7768 are added dynamically. */
7769 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
7773 as_warn (_("Macro used $at after \".set noat\""));
7776 /* Implement macros in mips16 mode. */
7780 struct mips_cl_insn *ip;
7783 int xreg, yreg, zreg, tmp;
7787 const char *s, *s2, *s3;
7789 mask = ip->insn_mo->mask;
7791 xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
7792 yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY;
7793 zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
7797 expr1.X_op = O_constant;
7798 expr1.X_op_symbol = NULL;
7799 expr1.X_add_symbol = NULL;
7800 expr1.X_add_number = 1;
7819 mips_emit_delays (TRUE);
7820 ++mips_opts.noreorder;
7821 mips_any_noreorder = 1;
7822 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7823 dbl ? "ddiv" : "div",
7824 "0,x,y", xreg, yreg);
7825 expr1.X_add_number = 2;
7826 macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg);
7827 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", "6",
7830 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7831 since that causes an overflow. We should do that as well,
7832 but I don't see how to do the comparisons without a temporary
7834 --mips_opts.noreorder;
7835 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x", zreg);
7854 mips_emit_delays (TRUE);
7855 ++mips_opts.noreorder;
7856 mips_any_noreorder = 1;
7857 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "0,x,y",
7859 expr1.X_add_number = 2;
7860 macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg);
7861 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
7863 --mips_opts.noreorder;
7864 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "x", zreg);
7870 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7871 dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
7872 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "x",
7881 if (imm_expr.X_op != O_constant)
7882 as_bad (_("Unsupported large constant"));
7883 imm_expr.X_add_number = -imm_expr.X_add_number;
7884 macro_build ((char *) NULL, &icnt, &imm_expr,
7885 dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
7889 if (imm_expr.X_op != O_constant)
7890 as_bad (_("Unsupported large constant"));
7891 imm_expr.X_add_number = -imm_expr.X_add_number;
7892 macro_build ((char *) NULL, &icnt, &imm_expr, "addiu",
7897 if (imm_expr.X_op != O_constant)
7898 as_bad (_("Unsupported large constant"));
7899 imm_expr.X_add_number = -imm_expr.X_add_number;
7900 macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu",
7923 goto do_reverse_branch;
7927 goto do_reverse_branch;
7939 goto do_reverse_branch;
7950 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y",
7952 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p");
7979 goto do_addone_branch_i;
7984 goto do_addone_branch_i;
7999 goto do_addone_branch_i;
8006 if (imm_expr.X_op != O_constant)
8007 as_bad (_("Unsupported large constant"));
8008 ++imm_expr.X_add_number;
8011 macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg);
8012 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p");
8016 expr1.X_add_number = 0;
8017 macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg);
8019 move_register (&icnt, xreg, yreg);
8020 expr1.X_add_number = 2;
8021 macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p");
8022 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
8023 "neg", "x,w", xreg, xreg);
8027 /* For consistency checking, verify that all bits are specified either
8028 by the match/mask part of the instruction definition, or by the
8031 validate_mips_insn (opc)
8032 const struct mips_opcode *opc;
8034 const char *p = opc->args;
8036 unsigned long used_bits = opc->mask;
8038 if ((used_bits & opc->match) != opc->match)
8040 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8041 opc->name, opc->args);
8044 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8054 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8055 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8056 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8057 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
8058 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8060 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8061 c, opc->name, opc->args);
8065 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8066 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8068 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
8069 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
8070 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8071 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8073 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8074 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8076 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
8077 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8079 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
8080 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
8081 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
8082 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
8083 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8084 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
8085 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8086 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8087 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8088 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8089 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8090 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8091 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8092 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
8093 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8094 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
8095 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8097 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
8098 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8099 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8100 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
8102 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8103 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8104 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
8105 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8106 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8107 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8108 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8109 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8110 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8113 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
8114 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
8115 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8116 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
8117 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
8121 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8122 c, opc->name, opc->args);
8126 if (used_bits != 0xffffffff)
8128 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8129 ~used_bits & 0xffffffff, opc->name, opc->args);
8135 /* This routine assembles an instruction into its binary format. As a
8136 side effect, it sets one of the global variables imm_reloc or
8137 offset_reloc to the type of relocation to do if one of the operands
8138 is an address expression. */
8143 struct mips_cl_insn *ip;
8148 struct mips_opcode *insn;
8151 unsigned int lastregno = 0;
8152 unsigned int lastpos = 0;
8153 unsigned int limlo, limhi;
8159 /* If the instruction contains a '.', we first try to match an instruction
8160 including the '.'. Then we try again without the '.'. */
8162 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
8165 /* If we stopped on whitespace, then replace the whitespace with null for
8166 the call to hash_find. Save the character we replaced just in case we
8167 have to re-parse the instruction. */
8174 insn = (struct mips_opcode *) hash_find (op_hash, str);
8176 /* If we didn't find the instruction in the opcode table, try again, but
8177 this time with just the instruction up to, but not including the
8181 /* Restore the character we overwrite above (if any). */
8185 /* Scan up to the first '.' or whitespace. */
8187 *s != '\0' && *s != '.' && !ISSPACE (*s);
8191 /* If we did not find a '.', then we can quit now. */
8194 insn_error = "unrecognized opcode";
8198 /* Lookup the instruction in the hash table. */
8200 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
8202 insn_error = "unrecognized opcode";
8212 assert (strcmp (insn->name, str) == 0);
8214 if (OPCODE_IS_MEMBER (insn,
8216 | (file_ase_mips16 ? INSN_MIPS16 : 0)
8217 | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
8218 | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
8224 if (insn->pinfo != INSN_MACRO)
8226 if (mips_arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)
8232 if (insn + 1 < &mips_opcodes[NUMOPCODES]
8233 && strcmp (insn->name, insn[1].name) == 0)
8242 static char buf[100];
8243 if (mips_arch_info->is_isa)
8245 _("opcode not supported at this ISA level (%s)"),
8246 mips_cpu_info_from_isa (mips_opts.isa)->name);
8249 _("opcode not supported on this processor: %s (%s)"),
8250 mips_arch_info->name,
8251 mips_cpu_info_from_isa (mips_opts.isa)->name);
8261 ip->insn_opcode = insn->match;
8263 for (args = insn->args;; ++args)
8267 s += strspn (s, " \t");
8271 case '\0': /* end of args */
8284 ip->insn_opcode |= lastregno << OP_SH_RS;
8288 ip->insn_opcode |= lastregno << OP_SH_RT;
8292 ip->insn_opcode |= lastregno << OP_SH_FT;
8296 ip->insn_opcode |= lastregno << OP_SH_FS;
8302 /* Handle optional base register.
8303 Either the base register is omitted or
8304 we must have a left paren. */
8305 /* This is dependent on the next operand specifier
8306 is a base register specification. */
8307 assert (args[1] == 'b' || args[1] == '5'
8308 || args[1] == '-' || args[1] == '4');
8312 case ')': /* these must match exactly */
8319 case '+': /* Opcode extension character. */
8322 case 'A': /* ins/ext position, becomes LSB. */
8325 my_getExpression (&imm_expr, s);
8326 check_absolute_expr (ip, &imm_expr);
8327 if ((unsigned long) imm_expr.X_add_number < limlo
8328 || (unsigned long) imm_expr.X_add_number > limhi)
8330 as_bad (_("Improper position (%lu)"),
8331 (unsigned long) imm_expr.X_add_number);
8332 imm_expr.X_add_number = limlo;
8334 lastpos = imm_expr.X_add_number;
8335 ip->insn_opcode |= (imm_expr.X_add_number
8336 & OP_MASK_SHAMT) << OP_SH_SHAMT;
8337 imm_expr.X_op = O_absent;
8341 case 'B': /* ins size, becomes MSB. */
8344 my_getExpression (&imm_expr, s);
8345 check_absolute_expr (ip, &imm_expr);
8346 /* Check for negative input so that small negative numbers
8347 will not succeed incorrectly. The checks against
8348 (pos+size) transitively check "size" itself,
8349 assuming that "pos" is reasonable. */
8350 if ((long) imm_expr.X_add_number < 0
8351 || ((unsigned long) imm_expr.X_add_number
8353 || ((unsigned long) imm_expr.X_add_number
8356 as_bad (_("Improper insert size (%lu, position %lu)"),
8357 (unsigned long) imm_expr.X_add_number,
8358 (unsigned long) lastpos);
8359 imm_expr.X_add_number = limlo - lastpos;
8361 ip->insn_opcode |= ((lastpos + imm_expr.X_add_number - 1)
8362 & OP_MASK_INSMSB) << OP_SH_INSMSB;
8363 imm_expr.X_op = O_absent;
8367 case 'C': /* ext size, becomes MSBD. */
8370 my_getExpression (&imm_expr, s);
8371 check_absolute_expr (ip, &imm_expr);
8372 /* Check for negative input so that small negative numbers
8373 will not succeed incorrectly. The checks against
8374 (pos+size) transitively check "size" itself,
8375 assuming that "pos" is reasonable. */
8376 if ((long) imm_expr.X_add_number < 0
8377 || ((unsigned long) imm_expr.X_add_number
8379 || ((unsigned long) imm_expr.X_add_number
8382 as_bad (_("Improper extract size (%lu, position %lu)"),
8383 (unsigned long) imm_expr.X_add_number,
8384 (unsigned long) lastpos);
8385 imm_expr.X_add_number = limlo - lastpos;
8387 ip->insn_opcode |= ((imm_expr.X_add_number - 1)
8388 & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD;
8389 imm_expr.X_op = O_absent;
8394 /* +D is for disassembly only; never match. */
8398 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8399 *args, insn->name, insn->args);
8400 /* Further processing is fruitless. */
8405 case '<': /* must be at least one digit */
8407 * According to the manual, if the shift amount is greater
8408 * than 31 or less than 0, then the shift amount should be
8409 * mod 32. In reality the mips assembler issues an error.
8410 * We issue a warning and mask out all but the low 5 bits.
8412 my_getExpression (&imm_expr, s);
8413 check_absolute_expr (ip, &imm_expr);
8414 if ((unsigned long) imm_expr.X_add_number > 31)
8416 as_warn (_("Improper shift amount (%lu)"),
8417 (unsigned long) imm_expr.X_add_number);
8418 imm_expr.X_add_number &= OP_MASK_SHAMT;
8420 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT;
8421 imm_expr.X_op = O_absent;
8425 case '>': /* shift amount minus 32 */
8426 my_getExpression (&imm_expr, s);
8427 check_absolute_expr (ip, &imm_expr);
8428 if ((unsigned long) imm_expr.X_add_number < 32
8429 || (unsigned long) imm_expr.X_add_number > 63)
8431 ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT;
8432 imm_expr.X_op = O_absent;
8436 case 'k': /* cache code */
8437 case 'h': /* prefx code */
8438 my_getExpression (&imm_expr, s);
8439 check_absolute_expr (ip, &imm_expr);
8440 if ((unsigned long) imm_expr.X_add_number > 31)
8442 as_warn (_("Invalid value for `%s' (%lu)"),
8444 (unsigned long) imm_expr.X_add_number);
8445 imm_expr.X_add_number &= 0x1f;
8448 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE;
8450 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX;
8451 imm_expr.X_op = O_absent;
8455 case 'c': /* break code */
8456 my_getExpression (&imm_expr, s);
8457 check_absolute_expr (ip, &imm_expr);
8458 if ((unsigned long) imm_expr.X_add_number > 1023)
8460 as_warn (_("Illegal break code (%lu)"),
8461 (unsigned long) imm_expr.X_add_number);
8462 imm_expr.X_add_number &= OP_MASK_CODE;
8464 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE;
8465 imm_expr.X_op = O_absent;
8469 case 'q': /* lower break code */
8470 my_getExpression (&imm_expr, s);
8471 check_absolute_expr (ip, &imm_expr);
8472 if ((unsigned long) imm_expr.X_add_number > 1023)
8474 as_warn (_("Illegal lower break code (%lu)"),
8475 (unsigned long) imm_expr.X_add_number);
8476 imm_expr.X_add_number &= OP_MASK_CODE2;
8478 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2;
8479 imm_expr.X_op = O_absent;
8483 case 'B': /* 20-bit syscall/break code. */
8484 my_getExpression (&imm_expr, s);
8485 check_absolute_expr (ip, &imm_expr);
8486 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
8487 as_warn (_("Illegal 20-bit code (%lu)"),
8488 (unsigned long) imm_expr.X_add_number);
8489 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20;
8490 imm_expr.X_op = O_absent;
8494 case 'C': /* Coprocessor code */
8495 my_getExpression (&imm_expr, s);
8496 check_absolute_expr (ip, &imm_expr);
8497 if ((unsigned long) imm_expr.X_add_number >= (1 << 25))
8499 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8500 (unsigned long) imm_expr.X_add_number);
8501 imm_expr.X_add_number &= ((1 << 25) - 1);
8503 ip->insn_opcode |= imm_expr.X_add_number;
8504 imm_expr.X_op = O_absent;
8508 case 'J': /* 19-bit wait code. */
8509 my_getExpression (&imm_expr, s);
8510 check_absolute_expr (ip, &imm_expr);
8511 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
8512 as_warn (_("Illegal 19-bit code (%lu)"),
8513 (unsigned long) imm_expr.X_add_number);
8514 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19;
8515 imm_expr.X_op = O_absent;
8519 case 'P': /* Performance register */
8520 my_getExpression (&imm_expr, s);
8521 check_absolute_expr (ip, &imm_expr);
8522 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
8524 as_warn (_("Invalid performance register (%lu)"),
8525 (unsigned long) imm_expr.X_add_number);
8526 imm_expr.X_add_number &= OP_MASK_PERFREG;
8528 ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG);
8529 imm_expr.X_op = O_absent;
8533 case 'b': /* base register */
8534 case 'd': /* destination register */
8535 case 's': /* source register */
8536 case 't': /* target register */
8537 case 'r': /* both target and source */
8538 case 'v': /* both dest and source */
8539 case 'w': /* both dest and target */
8540 case 'E': /* coprocessor target register */
8541 case 'G': /* coprocessor destination register */
8542 case 'K': /* 'rdhwr' destination register */
8543 case 'x': /* ignore register name */
8544 case 'z': /* must be zero register */
8545 case 'U': /* destination register (clo/clz). */
8560 while (ISDIGIT (*s));
8562 as_bad (_("Invalid register number (%d)"), regno);
8564 else if (*args == 'E' || *args == 'G' || *args == 'K')
8568 if (s[1] == 'r' && s[2] == 'a')
8573 else if (s[1] == 'f' && s[2] == 'p')
8578 else if (s[1] == 's' && s[2] == 'p')
8583 else if (s[1] == 'g' && s[2] == 'p')
8588 else if (s[1] == 'a' && s[2] == 't')
8593 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
8598 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
8603 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
8608 else if (itbl_have_entries)
8613 p = s + 1; /* advance past '$' */
8614 n = itbl_get_field (&p); /* n is name */
8616 /* See if this is a register defined in an
8618 if (itbl_get_reg_val (n, &r))
8620 /* Get_field advances to the start of
8621 the next field, so we need to back
8622 rack to the end of the last field. */
8626 s = strchr (s, '\0');
8640 as_warn (_("Used $at without \".set noat\""));
8646 if (c == 'r' || c == 'v' || c == 'w')
8653 /* 'z' only matches $0. */
8654 if (c == 'z' && regno != 0)
8657 /* Now that we have assembled one operand, we use the args string
8658 * to figure out where it goes in the instruction. */
8665 ip->insn_opcode |= regno << OP_SH_RS;
8670 ip->insn_opcode |= regno << OP_SH_RD;
8673 ip->insn_opcode |= regno << OP_SH_RD;
8674 ip->insn_opcode |= regno << OP_SH_RT;
8679 ip->insn_opcode |= regno << OP_SH_RT;
8682 /* This case exists because on the r3000 trunc
8683 expands into a macro which requires a gp
8684 register. On the r6000 or r4000 it is
8685 assembled into a single instruction which
8686 ignores the register. Thus the insn version
8687 is MIPS_ISA2 and uses 'x', and the macro
8688 version is MIPS_ISA1 and uses 't'. */
8691 /* This case is for the div instruction, which
8692 acts differently if the destination argument
8693 is $0. This only matches $0, and is checked
8694 outside the switch. */
8697 /* Itbl operand; not yet implemented. FIXME ?? */
8699 /* What about all other operands like 'i', which
8700 can be specified in the opcode table? */
8710 ip->insn_opcode |= lastregno << OP_SH_RS;
8713 ip->insn_opcode |= lastregno << OP_SH_RT;
8718 case 'O': /* MDMX alignment immediate constant. */
8719 my_getExpression (&imm_expr, s);
8720 check_absolute_expr (ip, &imm_expr);
8721 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
8723 as_warn ("Improper align amount (%ld), using low bits",
8724 (long) imm_expr.X_add_number);
8725 imm_expr.X_add_number &= OP_MASK_ALN;
8727 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN;
8728 imm_expr.X_op = O_absent;
8732 case 'Q': /* MDMX vector, element sel, or const. */
8735 /* MDMX Immediate. */
8736 my_getExpression (&imm_expr, s);
8737 check_absolute_expr (ip, &imm_expr);
8738 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
8740 as_warn (_("Invalid MDMX Immediate (%ld)"),
8741 (long) imm_expr.X_add_number);
8742 imm_expr.X_add_number &= OP_MASK_FT;
8744 imm_expr.X_add_number &= OP_MASK_FT;
8745 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8746 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
8748 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
8749 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT;
8750 imm_expr.X_op = O_absent;
8754 /* Not MDMX Immediate. Fall through. */
8755 case 'X': /* MDMX destination register. */
8756 case 'Y': /* MDMX source register. */
8757 case 'Z': /* MDMX target register. */
8759 case 'D': /* floating point destination register */
8760 case 'S': /* floating point source register */
8761 case 'T': /* floating point target register */
8762 case 'R': /* floating point source register */
8766 /* Accept $fN for FP and MDMX register numbers, and in
8767 addition accept $vN for MDMX register numbers. */
8768 if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2]))
8769 || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v'
8780 while (ISDIGIT (*s));
8783 as_bad (_("Invalid float register number (%d)"), regno);
8785 if ((regno & 1) != 0
8787 && ! (strcmp (str, "mtc1") == 0
8788 || strcmp (str, "mfc1") == 0
8789 || strcmp (str, "lwc1") == 0
8790 || strcmp (str, "swc1") == 0
8791 || strcmp (str, "l.s") == 0
8792 || strcmp (str, "s.s") == 0))
8793 as_warn (_("Float register should be even, was %d"),
8801 if (c == 'V' || c == 'W')
8812 ip->insn_opcode |= regno << OP_SH_FD;
8817 ip->insn_opcode |= regno << OP_SH_FS;
8820 /* This is like 'Z', but also needs to fix the MDMX
8821 vector/scalar select bits. Note that the
8822 scalar immediate case is handled above. */
8825 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
8826 int max_el = (is_qh ? 3 : 7);
8828 my_getExpression(&imm_expr, s);
8829 check_absolute_expr (ip, &imm_expr);
8831 if (imm_expr.X_add_number > max_el)
8832 as_bad(_("Bad element selector %ld"),
8833 (long) imm_expr.X_add_number);
8834 imm_expr.X_add_number &= max_el;
8835 ip->insn_opcode |= (imm_expr.X_add_number
8839 as_warn(_("Expecting ']' found '%s'"), s);
8845 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8846 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
8849 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
8856 ip->insn_opcode |= regno << OP_SH_FT;
8859 ip->insn_opcode |= regno << OP_SH_FR;
8869 ip->insn_opcode |= lastregno << OP_SH_FS;
8872 ip->insn_opcode |= lastregno << OP_SH_FT;
8878 my_getExpression (&imm_expr, s);
8879 if (imm_expr.X_op != O_big
8880 && imm_expr.X_op != O_constant)
8881 insn_error = _("absolute expression required");
8886 my_getExpression (&offset_expr, s);
8887 *imm_reloc = BFD_RELOC_32;
8900 unsigned char temp[8];
8902 unsigned int length;
8907 /* These only appear as the last operand in an
8908 instruction, and every instruction that accepts
8909 them in any variant accepts them in all variants.
8910 This means we don't have to worry about backing out
8911 any changes if the instruction does not match.
8913 The difference between them is the size of the
8914 floating point constant and where it goes. For 'F'
8915 and 'L' the constant is 64 bits; for 'f' and 'l' it
8916 is 32 bits. Where the constant is placed is based
8917 on how the MIPS assembler does things:
8920 f -- immediate value
8923 The .lit4 and .lit8 sections are only used if
8924 permitted by the -G argument.
8926 When generating embedded PIC code, we use the
8927 .lit8 section but not the .lit4 section (we can do
8928 .lit4 inline easily; we need to put .lit8
8929 somewhere in the data segment, and using .lit8
8930 permits the linker to eventually combine identical
8933 The code below needs to know whether the target register
8934 is 32 or 64 bits wide. It relies on the fact 'f' and
8935 'F' are used with GPR-based instructions and 'l' and
8936 'L' are used with FPR-based instructions. */
8938 f64 = *args == 'F' || *args == 'L';
8939 using_gprs = *args == 'F' || *args == 'f';
8941 save_in = input_line_pointer;
8942 input_line_pointer = s;
8943 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
8945 s = input_line_pointer;
8946 input_line_pointer = save_in;
8947 if (err != NULL && *err != '\0')
8949 as_bad (_("Bad floating point constant: %s"), err);
8950 memset (temp, '\0', sizeof temp);
8951 length = f64 ? 8 : 4;
8954 assert (length == (unsigned) (f64 ? 8 : 4));
8958 && (! USE_GLOBAL_POINTER_OPT
8959 || mips_pic == EMBEDDED_PIC
8960 || g_switch_value < 4
8961 || (temp[0] == 0 && temp[1] == 0)
8962 || (temp[2] == 0 && temp[3] == 0))))
8964 imm_expr.X_op = O_constant;
8965 if (! target_big_endian)
8966 imm_expr.X_add_number = bfd_getl32 (temp);
8968 imm_expr.X_add_number = bfd_getb32 (temp);
8971 && ! mips_disable_float_construction
8972 /* Constants can only be constructed in GPRs and
8973 copied to FPRs if the GPRs are at least as wide
8974 as the FPRs. Force the constant into memory if
8975 we are using 64-bit FPRs but the GPRs are only
8978 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
8979 && ((temp[0] == 0 && temp[1] == 0)
8980 || (temp[2] == 0 && temp[3] == 0))
8981 && ((temp[4] == 0 && temp[5] == 0)
8982 || (temp[6] == 0 && temp[7] == 0)))
8984 /* The value is simple enough to load with a couple of
8985 instructions. If using 32-bit registers, set
8986 imm_expr to the high order 32 bits and offset_expr to
8987 the low order 32 bits. Otherwise, set imm_expr to
8988 the entire 64 bit constant. */
8989 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
8991 imm_expr.X_op = O_constant;
8992 offset_expr.X_op = O_constant;
8993 if (! target_big_endian)
8995 imm_expr.X_add_number = bfd_getl32 (temp + 4);
8996 offset_expr.X_add_number = bfd_getl32 (temp);
9000 imm_expr.X_add_number = bfd_getb32 (temp);
9001 offset_expr.X_add_number = bfd_getb32 (temp + 4);
9003 if (offset_expr.X_add_number == 0)
9004 offset_expr.X_op = O_absent;
9006 else if (sizeof (imm_expr.X_add_number) > 4)
9008 imm_expr.X_op = O_constant;
9009 if (! target_big_endian)
9010 imm_expr.X_add_number = bfd_getl64 (temp);
9012 imm_expr.X_add_number = bfd_getb64 (temp);
9016 imm_expr.X_op = O_big;
9017 imm_expr.X_add_number = 4;
9018 if (! target_big_endian)
9020 generic_bignum[0] = bfd_getl16 (temp);
9021 generic_bignum[1] = bfd_getl16 (temp + 2);
9022 generic_bignum[2] = bfd_getl16 (temp + 4);
9023 generic_bignum[3] = bfd_getl16 (temp + 6);
9027 generic_bignum[0] = bfd_getb16 (temp + 6);
9028 generic_bignum[1] = bfd_getb16 (temp + 4);
9029 generic_bignum[2] = bfd_getb16 (temp + 2);
9030 generic_bignum[3] = bfd_getb16 (temp);
9036 const char *newname;
9039 /* Switch to the right section. */
9041 subseg = now_subseg;
9044 default: /* unused default case avoids warnings. */
9046 newname = RDATA_SECTION_NAME;
9047 if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8)
9048 || mips_pic == EMBEDDED_PIC)
9052 if (mips_pic == EMBEDDED_PIC)
9055 newname = RDATA_SECTION_NAME;
9058 assert (!USE_GLOBAL_POINTER_OPT
9059 || g_switch_value >= 4);
9063 new_seg = subseg_new (newname, (subsegT) 0);
9064 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
9065 bfd_set_section_flags (stdoutput, new_seg,
9070 frag_align (*args == 'l' ? 2 : 3, 0, 0);
9071 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
9072 && strcmp (TARGET_OS, "elf") != 0)
9073 record_alignment (new_seg, 4);
9075 record_alignment (new_seg, *args == 'l' ? 2 : 3);
9077 as_bad (_("Can't use floating point insn in this section"));
9079 /* Set the argument to the current address in the
9081 offset_expr.X_op = O_symbol;
9082 offset_expr.X_add_symbol =
9083 symbol_new ("L0\001", now_seg,
9084 (valueT) frag_now_fix (), frag_now);
9085 offset_expr.X_add_number = 0;
9087 /* Put the floating point number into the section. */
9088 p = frag_more ((int) length);
9089 memcpy (p, temp, length);
9091 /* Switch back to the original section. */
9092 subseg_set (seg, subseg);
9097 case 'i': /* 16 bit unsigned immediate */
9098 case 'j': /* 16 bit signed immediate */
9099 *imm_reloc = BFD_RELOC_LO16;
9100 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
9103 offsetT minval, maxval;
9105 more = (insn + 1 < &mips_opcodes[NUMOPCODES]
9106 && strcmp (insn->name, insn[1].name) == 0);
9108 /* If the expression was written as an unsigned number,
9109 only treat it as signed if there are no more
9113 && sizeof (imm_expr.X_add_number) <= 4
9114 && imm_expr.X_op == O_constant
9115 && imm_expr.X_add_number < 0
9116 && imm_expr.X_unsigned
9120 /* For compatibility with older assemblers, we accept
9121 0x8000-0xffff as signed 16-bit numbers when only
9122 signed numbers are allowed. */
9124 minval = 0, maxval = 0xffff;
9126 minval = -0x8000, maxval = 0x7fff;
9128 minval = -0x8000, maxval = 0xffff;
9130 if (imm_expr.X_op != O_constant
9131 || imm_expr.X_add_number < minval
9132 || imm_expr.X_add_number > maxval)
9136 if (imm_expr.X_op == O_constant
9137 || imm_expr.X_op == O_big)
9138 as_bad (_("expression out of range"));
9144 case 'o': /* 16 bit offset */
9145 /* Check whether there is only a single bracketed expression
9146 left. If so, it must be the base register and the
9147 constant must be zero. */
9148 if (*s == '(' && strchr (s + 1, '(') == 0)
9150 offset_expr.X_op = O_constant;
9151 offset_expr.X_add_number = 0;
9155 /* If this value won't fit into a 16 bit offset, then go
9156 find a macro that will generate the 32 bit offset
9158 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
9159 && (offset_expr.X_op != O_constant
9160 || offset_expr.X_add_number >= 0x8000
9161 || offset_expr.X_add_number < -0x8000))
9167 case 'p': /* pc relative offset */
9168 *offset_reloc = BFD_RELOC_16_PCREL_S2;
9169 my_getExpression (&offset_expr, s);
9173 case 'u': /* upper 16 bits */
9174 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
9175 && imm_expr.X_op == O_constant
9176 && (imm_expr.X_add_number < 0
9177 || imm_expr.X_add_number >= 0x10000))
9178 as_bad (_("lui expression not in range 0..65535"));
9182 case 'a': /* 26 bit address */
9183 my_getExpression (&offset_expr, s);
9185 *offset_reloc = BFD_RELOC_MIPS_JMP;
9188 case 'N': /* 3 bit branch condition code */
9189 case 'M': /* 3 bit compare condition code */
9190 if (strncmp (s, "$fcc", 4) != 0)
9200 while (ISDIGIT (*s));
9202 as_bad (_("invalid condition code register $fcc%d"), regno);
9204 ip->insn_opcode |= regno << OP_SH_BCC;
9206 ip->insn_opcode |= regno << OP_SH_CCC;
9210 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
9221 while (ISDIGIT (*s));
9224 c = 8; /* Invalid sel value. */
9227 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9228 ip->insn_opcode |= c;
9232 /* Must be at least one digit. */
9233 my_getExpression (&imm_expr, s);
9234 check_absolute_expr (ip, &imm_expr);
9236 if ((unsigned long) imm_expr.X_add_number
9237 > (unsigned long) OP_MASK_VECBYTE)
9239 as_bad (_("bad byte vector index (%ld)"),
9240 (long) imm_expr.X_add_number);
9241 imm_expr.X_add_number = 0;
9244 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE;
9245 imm_expr.X_op = O_absent;
9250 my_getExpression (&imm_expr, s);
9251 check_absolute_expr (ip, &imm_expr);
9253 if ((unsigned long) imm_expr.X_add_number
9254 > (unsigned long) OP_MASK_VECALIGN)
9256 as_bad (_("bad byte vector index (%ld)"),
9257 (long) imm_expr.X_add_number);
9258 imm_expr.X_add_number = 0;
9261 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN;
9262 imm_expr.X_op = O_absent;
9267 as_bad (_("bad char = '%c'\n"), *args);
9272 /* Args don't match. */
9273 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
9274 !strcmp (insn->name, insn[1].name))
9278 insn_error = _("illegal operands");
9283 insn_error = _("illegal operands");
9288 /* This routine assembles an instruction into its binary format when
9289 assembling for the mips16. As a side effect, it sets one of the
9290 global variables imm_reloc or offset_reloc to the type of
9291 relocation to do if one of the operands is an address expression.
9292 It also sets mips16_small and mips16_ext if the user explicitly
9293 requested a small or extended instruction. */
9298 struct mips_cl_insn *ip;
9302 struct mips_opcode *insn;
9305 unsigned int lastregno = 0;
9310 mips16_small = FALSE;
9313 for (s = str; ISLOWER (*s); ++s)
9325 if (s[1] == 't' && s[2] == ' ')
9328 mips16_small = TRUE;
9332 else if (s[1] == 'e' && s[2] == ' ')
9341 insn_error = _("unknown opcode");
9345 if (mips_opts.noautoextend && ! mips16_ext)
9346 mips16_small = TRUE;
9348 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
9350 insn_error = _("unrecognized opcode");
9357 assert (strcmp (insn->name, str) == 0);
9360 ip->insn_opcode = insn->match;
9361 ip->use_extend = FALSE;
9362 imm_expr.X_op = O_absent;
9363 imm_reloc[0] = BFD_RELOC_UNUSED;
9364 imm_reloc[1] = BFD_RELOC_UNUSED;
9365 imm_reloc[2] = BFD_RELOC_UNUSED;
9366 offset_expr.X_op = O_absent;
9367 offset_reloc[0] = BFD_RELOC_UNUSED;
9368 offset_reloc[1] = BFD_RELOC_UNUSED;
9369 offset_reloc[2] = BFD_RELOC_UNUSED;
9370 for (args = insn->args; 1; ++args)
9377 /* In this switch statement we call break if we did not find
9378 a match, continue if we did find a match, or return if we
9387 /* Stuff the immediate value in now, if we can. */
9388 if (imm_expr.X_op == O_constant
9389 && *imm_reloc > BFD_RELOC_UNUSED
9390 && insn->pinfo != INSN_MACRO)
9392 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
9393 imm_expr.X_add_number, TRUE, mips16_small,
9394 mips16_ext, &ip->insn_opcode,
9395 &ip->use_extend, &ip->extend);
9396 imm_expr.X_op = O_absent;
9397 *imm_reloc = BFD_RELOC_UNUSED;
9411 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9414 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9430 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9432 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9459 while (ISDIGIT (*s));
9462 as_bad (_("invalid register number (%d)"), regno);
9468 if (s[1] == 'r' && s[2] == 'a')
9473 else if (s[1] == 'f' && s[2] == 'p')
9478 else if (s[1] == 's' && s[2] == 'p')
9483 else if (s[1] == 'g' && s[2] == 'p')
9488 else if (s[1] == 'a' && s[2] == 't')
9493 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
9498 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
9503 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
9516 if (c == 'v' || c == 'w')
9518 regno = mips16_to_32_reg_map[lastregno];
9532 regno = mips32_to_16_reg_map[regno];
9537 regno = ILLEGAL_REG;
9542 regno = ILLEGAL_REG;
9547 regno = ILLEGAL_REG;
9552 if (regno == AT && ! mips_opts.noat)
9553 as_warn (_("used $at without \".set noat\""));
9560 if (regno == ILLEGAL_REG)
9567 ip->insn_opcode |= regno << MIPS16OP_SH_RX;
9571 ip->insn_opcode |= regno << MIPS16OP_SH_RY;
9574 ip->insn_opcode |= regno << MIPS16OP_SH_RZ;
9577 ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z;
9583 ip->insn_opcode |= regno << MIPS16OP_SH_REGR32;
9586 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
9587 ip->insn_opcode |= regno << MIPS16OP_SH_REG32R;
9597 if (strncmp (s, "$pc", 3) == 0)
9621 && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0)
9623 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9624 and generate the appropriate reloc. If the text
9625 inside %gprel is not a symbol name with an
9626 optional offset, then we generate a normal reloc
9627 and will probably fail later. */
9628 my_getExpression (&imm_expr, s + sizeof "%gprel" - 1);
9629 if (imm_expr.X_op == O_symbol)
9632 *imm_reloc = BFD_RELOC_MIPS16_GPREL;
9634 ip->use_extend = TRUE;
9641 /* Just pick up a normal expression. */
9642 my_getExpression (&imm_expr, s);
9645 if (imm_expr.X_op == O_register)
9647 /* What we thought was an expression turned out to
9650 if (s[0] == '(' && args[1] == '(')
9652 /* It looks like the expression was omitted
9653 before a register indirection, which means
9654 that the expression is implicitly zero. We
9655 still set up imm_expr, so that we handle
9656 explicit extensions correctly. */
9657 imm_expr.X_op = O_constant;
9658 imm_expr.X_add_number = 0;
9659 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9666 /* We need to relax this instruction. */
9667 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9676 /* We use offset_reloc rather than imm_reloc for the PC
9677 relative operands. This lets macros with both
9678 immediate and address operands work correctly. */
9679 my_getExpression (&offset_expr, s);
9681 if (offset_expr.X_op == O_register)
9684 /* We need to relax this instruction. */
9685 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
9689 case '6': /* break code */
9690 my_getExpression (&imm_expr, s);
9691 check_absolute_expr (ip, &imm_expr);
9692 if ((unsigned long) imm_expr.X_add_number > 63)
9694 as_warn (_("Invalid value for `%s' (%lu)"),
9696 (unsigned long) imm_expr.X_add_number);
9697 imm_expr.X_add_number &= 0x3f;
9699 ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6;
9700 imm_expr.X_op = O_absent;
9704 case 'a': /* 26 bit address */
9705 my_getExpression (&offset_expr, s);
9707 *offset_reloc = BFD_RELOC_MIPS16_JMP;
9708 ip->insn_opcode <<= 16;
9711 case 'l': /* register list for entry macro */
9712 case 'L': /* register list for exit macro */
9722 int freg, reg1, reg2;
9724 while (*s == ' ' || *s == ',')
9728 as_bad (_("can't parse register list"));
9740 while (ISDIGIT (*s))
9762 as_bad (_("invalid register list"));
9767 while (ISDIGIT (*s))
9774 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
9779 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
9784 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
9785 mask |= (reg2 - 3) << 3;
9786 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
9787 mask |= (reg2 - 15) << 1;
9788 else if (reg1 == RA && reg2 == RA)
9792 as_bad (_("invalid register list"));
9796 /* The mask is filled in in the opcode table for the
9797 benefit of the disassembler. We remove it before
9798 applying the actual mask. */
9799 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
9800 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
9804 case 'e': /* extend code */
9805 my_getExpression (&imm_expr, s);
9806 check_absolute_expr (ip, &imm_expr);
9807 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
9809 as_warn (_("Invalid value for `%s' (%lu)"),
9811 (unsigned long) imm_expr.X_add_number);
9812 imm_expr.X_add_number &= 0x7ff;
9814 ip->insn_opcode |= imm_expr.X_add_number;
9815 imm_expr.X_op = O_absent;
9825 /* Args don't match. */
9826 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
9827 strcmp (insn->name, insn[1].name) == 0)
9834 insn_error = _("illegal operands");
9840 /* This structure holds information we know about a mips16 immediate
9843 struct mips16_immed_operand
9845 /* The type code used in the argument string in the opcode table. */
9847 /* The number of bits in the short form of the opcode. */
9849 /* The number of bits in the extended form of the opcode. */
9851 /* The amount by which the short form is shifted when it is used;
9852 for example, the sw instruction has a shift count of 2. */
9854 /* The amount by which the short form is shifted when it is stored
9855 into the instruction code. */
9857 /* Non-zero if the short form is unsigned. */
9859 /* Non-zero if the extended form is unsigned. */
9861 /* Non-zero if the value is PC relative. */
9865 /* The mips16 immediate operand types. */
9867 static const struct mips16_immed_operand mips16_immed_operands[] =
9869 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9870 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9871 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9872 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9873 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
9874 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
9875 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
9876 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
9877 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
9878 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
9879 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
9880 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
9881 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
9882 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
9883 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
9884 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
9885 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9886 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9887 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
9888 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
9889 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
9892 #define MIPS16_NUM_IMMED \
9893 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9895 /* Handle a mips16 instruction with an immediate value. This or's the
9896 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9897 whether an extended value is needed; if one is needed, it sets
9898 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9899 If SMALL is true, an unextended opcode was explicitly requested.
9900 If EXT is true, an extended opcode was explicitly requested. If
9901 WARN is true, warn if EXT does not match reality. */
9904 mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend,
9913 unsigned long *insn;
9914 bfd_boolean *use_extend;
9915 unsigned short *extend;
9917 register const struct mips16_immed_operand *op;
9918 int mintiny, maxtiny;
9919 bfd_boolean needext;
9921 op = mips16_immed_operands;
9922 while (op->type != type)
9925 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
9930 if (type == '<' || type == '>' || type == '[' || type == ']')
9933 maxtiny = 1 << op->nbits;
9938 maxtiny = (1 << op->nbits) - 1;
9943 mintiny = - (1 << (op->nbits - 1));
9944 maxtiny = (1 << (op->nbits - 1)) - 1;
9947 /* Branch offsets have an implicit 0 in the lowest bit. */
9948 if (type == 'p' || type == 'q')
9951 if ((val & ((1 << op->shift) - 1)) != 0
9952 || val < (mintiny << op->shift)
9953 || val > (maxtiny << op->shift))
9958 if (warn && ext && ! needext)
9959 as_warn_where (file, line,
9960 _("extended operand requested but not required"));
9961 if (small && needext)
9962 as_bad_where (file, line, _("invalid unextended operand value"));
9964 if (small || (! ext && ! needext))
9968 *use_extend = FALSE;
9969 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
9970 insnval <<= op->op_shift;
9975 long minext, maxext;
9981 maxext = (1 << op->extbits) - 1;
9985 minext = - (1 << (op->extbits - 1));
9986 maxext = (1 << (op->extbits - 1)) - 1;
9988 if (val < minext || val > maxext)
9989 as_bad_where (file, line,
9990 _("operand value out of range for instruction"));
9993 if (op->extbits == 16)
9995 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
9998 else if (op->extbits == 15)
10000 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
10005 extval = ((val & 0x1f) << 6) | (val & 0x20);
10009 *extend = (unsigned short) extval;
10014 static const struct percent_op_match
10017 bfd_reloc_code_real_type reloc;
10020 {"%lo", BFD_RELOC_LO16},
10022 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
10023 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
10024 {"%call16", BFD_RELOC_MIPS_CALL16},
10025 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
10026 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
10027 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
10028 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
10029 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
10030 {"%got", BFD_RELOC_MIPS_GOT16},
10031 {"%gp_rel", BFD_RELOC_GPREL16},
10032 {"%half", BFD_RELOC_16},
10033 {"%highest", BFD_RELOC_MIPS_HIGHEST},
10034 {"%higher", BFD_RELOC_MIPS_HIGHER},
10035 {"%neg", BFD_RELOC_MIPS_SUB},
10037 {"%hi", BFD_RELOC_HI16_S}
10041 /* Return true if *STR points to a relocation operator. When returning true,
10042 move *STR over the operator and store its relocation code in *RELOC.
10043 Leave both *STR and *RELOC alone when returning false. */
10046 parse_relocation (str, reloc)
10048 bfd_reloc_code_real_type *reloc;
10052 for (i = 0; i < ARRAY_SIZE (percent_op); i++)
10053 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
10055 *str += strlen (percent_op[i].str);
10056 *reloc = percent_op[i].reloc;
10058 /* Check whether the output BFD supports this relocation.
10059 If not, issue an error and fall back on something safe. */
10060 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
10062 as_bad ("relocation %s isn't supported by the current ABI",
10063 percent_op[i].str);
10064 *reloc = BFD_RELOC_LO16;
10072 /* Parse string STR as a 16-bit relocatable operand. Store the
10073 expression in *EP and the relocations in the array starting
10074 at RELOC. Return the number of relocation operators used.
10076 On exit, EXPR_END points to the first character after the expression.
10077 If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16. */
10080 my_getSmallExpression (ep, reloc, str)
10082 bfd_reloc_code_real_type *reloc;
10085 bfd_reloc_code_real_type reversed_reloc[3];
10086 size_t reloc_index, i;
10087 int crux_depth, str_depth;
10090 /* Search for the start of the main expression, recoding relocations
10091 in REVERSED_RELOC. End the loop with CRUX pointing to the start
10092 of the main expression and with CRUX_DEPTH containing the number
10093 of open brackets at that point. */
10100 crux_depth = str_depth;
10102 /* Skip over whitespace and brackets, keeping count of the number
10104 while (*str == ' ' || *str == '\t' || *str == '(')
10109 && reloc_index < (HAVE_NEWABI ? 3 : 1)
10110 && parse_relocation (&str, &reversed_reloc[reloc_index]));
10112 my_getExpression (ep, crux);
10115 /* Match every open bracket. */
10116 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
10120 if (crux_depth > 0)
10121 as_bad ("unclosed '('");
10125 if (reloc_index == 0)
10126 reloc[0] = BFD_RELOC_LO16;
10129 prev_reloc_op_frag = frag_now;
10130 for (i = 0; i < reloc_index; i++)
10131 reloc[i] = reversed_reloc[reloc_index - 1 - i];
10134 return reloc_index;
10138 my_getExpression (ep, str)
10145 save_in = input_line_pointer;
10146 input_line_pointer = str;
10148 expr_end = input_line_pointer;
10149 input_line_pointer = save_in;
10151 /* If we are in mips16 mode, and this is an expression based on `.',
10152 then we bump the value of the symbol by 1 since that is how other
10153 text symbols are handled. We don't bother to handle complex
10154 expressions, just `.' plus or minus a constant. */
10155 if (mips_opts.mips16
10156 && ep->X_op == O_symbol
10157 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
10158 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg
10159 && symbol_get_frag (ep->X_add_symbol) == frag_now
10160 && symbol_constant_p (ep->X_add_symbol)
10161 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
10162 S_SET_VALUE (ep->X_add_symbol, val + 1);
10165 /* Turn a string in input_line_pointer into a floating point constant
10166 of type TYPE, and store the appropriate bytes in *LITP. The number
10167 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10168 returned, or NULL on OK. */
10171 md_atof (type, litP, sizeP)
10177 LITTLENUM_TYPE words[4];
10193 return _("bad call to md_atof");
10196 t = atof_ieee (input_line_pointer, type, words);
10198 input_line_pointer = t;
10202 if (! target_big_endian)
10204 for (i = prec - 1; i >= 0; i--)
10206 md_number_to_chars (litP, (valueT) words[i], 2);
10212 for (i = 0; i < prec; i++)
10214 md_number_to_chars (litP, (valueT) words[i], 2);
10223 md_number_to_chars (buf, val, n)
10228 if (target_big_endian)
10229 number_to_chars_bigendian (buf, val, n);
10231 number_to_chars_littleendian (buf, val, n);
10235 static int support_64bit_objects(void)
10237 const char **list, **l;
10240 list = bfd_target_list ();
10241 for (l = list; *l != NULL; l++)
10243 /* This is traditional mips */
10244 if (strcmp (*l, "elf64-tradbigmips") == 0
10245 || strcmp (*l, "elf64-tradlittlemips") == 0)
10247 if (strcmp (*l, "elf64-bigmips") == 0
10248 || strcmp (*l, "elf64-littlemips") == 0)
10251 yes = (*l != NULL);
10255 #endif /* OBJ_ELF */
10257 const char *md_shortopts = "nO::g::G:";
10259 struct option md_longopts[] =
10261 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
10262 {"mips0", no_argument, NULL, OPTION_MIPS1},
10263 {"mips1", no_argument, NULL, OPTION_MIPS1},
10264 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
10265 {"mips2", no_argument, NULL, OPTION_MIPS2},
10266 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
10267 {"mips3", no_argument, NULL, OPTION_MIPS3},
10268 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
10269 {"mips4", no_argument, NULL, OPTION_MIPS4},
10270 #define OPTION_MIPS5 (OPTION_MD_BASE + 5)
10271 {"mips5", no_argument, NULL, OPTION_MIPS5},
10272 #define OPTION_MIPS32 (OPTION_MD_BASE + 6)
10273 {"mips32", no_argument, NULL, OPTION_MIPS32},
10274 #define OPTION_MIPS64 (OPTION_MD_BASE + 7)
10275 {"mips64", no_argument, NULL, OPTION_MIPS64},
10276 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 8)
10277 {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC},
10278 #define OPTION_TRAP (OPTION_MD_BASE + 9)
10279 {"trap", no_argument, NULL, OPTION_TRAP},
10280 {"no-break", no_argument, NULL, OPTION_TRAP},
10281 #define OPTION_BREAK (OPTION_MD_BASE + 10)
10282 {"break", no_argument, NULL, OPTION_BREAK},
10283 {"no-trap", no_argument, NULL, OPTION_BREAK},
10284 #define OPTION_EB (OPTION_MD_BASE + 11)
10285 {"EB", no_argument, NULL, OPTION_EB},
10286 #define OPTION_EL (OPTION_MD_BASE + 12)
10287 {"EL", no_argument, NULL, OPTION_EL},
10288 #define OPTION_MIPS16 (OPTION_MD_BASE + 13)
10289 {"mips16", no_argument, NULL, OPTION_MIPS16},
10290 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 14)
10291 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
10292 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 15)
10293 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
10294 #define OPTION_MNO_7000_HILO_FIX (OPTION_MD_BASE + 16)
10295 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10296 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10297 #define OPTION_FP32 (OPTION_MD_BASE + 17)
10298 {"mfp32", no_argument, NULL, OPTION_FP32},
10299 #define OPTION_GP32 (OPTION_MD_BASE + 18)
10300 {"mgp32", no_argument, NULL, OPTION_GP32},
10301 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 19)
10302 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
10303 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 20)
10304 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
10305 #define OPTION_MARCH (OPTION_MD_BASE + 21)
10306 {"march", required_argument, NULL, OPTION_MARCH},
10307 #define OPTION_MTUNE (OPTION_MD_BASE + 22)
10308 {"mtune", required_argument, NULL, OPTION_MTUNE},
10309 #define OPTION_FP64 (OPTION_MD_BASE + 23)
10310 {"mfp64", no_argument, NULL, OPTION_FP64},
10311 #define OPTION_M4650 (OPTION_MD_BASE + 24)
10312 {"m4650", no_argument, NULL, OPTION_M4650},
10313 #define OPTION_NO_M4650 (OPTION_MD_BASE + 25)
10314 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
10315 #define OPTION_M4010 (OPTION_MD_BASE + 26)
10316 {"m4010", no_argument, NULL, OPTION_M4010},
10317 #define OPTION_NO_M4010 (OPTION_MD_BASE + 27)
10318 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
10319 #define OPTION_M4100 (OPTION_MD_BASE + 28)
10320 {"m4100", no_argument, NULL, OPTION_M4100},
10321 #define OPTION_NO_M4100 (OPTION_MD_BASE + 29)
10322 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
10323 #define OPTION_M3900 (OPTION_MD_BASE + 30)
10324 {"m3900", no_argument, NULL, OPTION_M3900},
10325 #define OPTION_NO_M3900 (OPTION_MD_BASE + 31)
10326 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
10327 #define OPTION_GP64 (OPTION_MD_BASE + 32)
10328 {"mgp64", no_argument, NULL, OPTION_GP64},
10329 #define OPTION_MIPS3D (OPTION_MD_BASE + 33)
10330 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
10331 #define OPTION_NO_MIPS3D (OPTION_MD_BASE + 34)
10332 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
10333 #define OPTION_MDMX (OPTION_MD_BASE + 35)
10334 {"mdmx", no_argument, NULL, OPTION_MDMX},
10335 #define OPTION_NO_MDMX (OPTION_MD_BASE + 36)
10336 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
10337 #define OPTION_FIX_VR4122 (OPTION_MD_BASE + 37)
10338 #define OPTION_NO_FIX_VR4122 (OPTION_MD_BASE + 38)
10339 {"mfix-vr4122-bugs", no_argument, NULL, OPTION_FIX_VR4122},
10340 {"no-mfix-vr4122-bugs", no_argument, NULL, OPTION_NO_FIX_VR4122},
10341 #define OPTION_RELAX_BRANCH (OPTION_MD_BASE + 39)
10342 #define OPTION_NO_RELAX_BRANCH (OPTION_MD_BASE + 40)
10343 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
10344 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
10345 #define OPTION_MIPS32R2 (OPTION_MD_BASE + 41)
10346 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
10348 #define OPTION_ELF_BASE (OPTION_MD_BASE + 42)
10349 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10350 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
10351 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
10352 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10353 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
10354 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10355 {"xgot", no_argument, NULL, OPTION_XGOT},
10356 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10357 {"mabi", required_argument, NULL, OPTION_MABI},
10358 #define OPTION_32 (OPTION_ELF_BASE + 4)
10359 {"32", no_argument, NULL, OPTION_32},
10360 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10361 {"n32", no_argument, NULL, OPTION_N32},
10362 #define OPTION_64 (OPTION_ELF_BASE + 6)
10363 {"64", no_argument, NULL, OPTION_64},
10364 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10365 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
10366 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10367 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
10368 #endif /* OBJ_ELF */
10369 {NULL, no_argument, NULL, 0}
10371 size_t md_longopts_size = sizeof (md_longopts);
10373 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10374 NEW_VALUE. Warn if another value was already specified. Note:
10375 we have to defer parsing the -march and -mtune arguments in order
10376 to handle 'from-abi' correctly, since the ABI might be specified
10377 in a later argument. */
10380 mips_set_option_string (string_ptr, new_value)
10381 const char **string_ptr, *new_value;
10383 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
10384 as_warn (_("A different %s was already specified, is now %s"),
10385 string_ptr == &mips_arch_string ? "-march" : "-mtune",
10388 *string_ptr = new_value;
10392 md_parse_option (c, arg)
10398 case OPTION_CONSTRUCT_FLOATS:
10399 mips_disable_float_construction = 0;
10402 case OPTION_NO_CONSTRUCT_FLOATS:
10403 mips_disable_float_construction = 1;
10415 target_big_endian = 1;
10419 target_big_endian = 0;
10427 if (arg && arg[1] == '0')
10437 mips_debug = atoi (arg);
10438 /* When the MIPS assembler sees -g or -g2, it does not do
10439 optimizations which limit full symbolic debugging. We take
10440 that to be equivalent to -O0. */
10441 if (mips_debug == 2)
10446 file_mips_isa = ISA_MIPS1;
10450 file_mips_isa = ISA_MIPS2;
10454 file_mips_isa = ISA_MIPS3;
10458 file_mips_isa = ISA_MIPS4;
10462 file_mips_isa = ISA_MIPS5;
10465 case OPTION_MIPS32:
10466 file_mips_isa = ISA_MIPS32;
10469 case OPTION_MIPS32R2:
10470 file_mips_isa = ISA_MIPS32R2;
10473 case OPTION_MIPS64:
10474 file_mips_isa = ISA_MIPS64;
10478 mips_set_option_string (&mips_tune_string, arg);
10482 mips_set_option_string (&mips_arch_string, arg);
10486 mips_set_option_string (&mips_arch_string, "4650");
10487 mips_set_option_string (&mips_tune_string, "4650");
10490 case OPTION_NO_M4650:
10494 mips_set_option_string (&mips_arch_string, "4010");
10495 mips_set_option_string (&mips_tune_string, "4010");
10498 case OPTION_NO_M4010:
10502 mips_set_option_string (&mips_arch_string, "4100");
10503 mips_set_option_string (&mips_tune_string, "4100");
10506 case OPTION_NO_M4100:
10510 mips_set_option_string (&mips_arch_string, "3900");
10511 mips_set_option_string (&mips_tune_string, "3900");
10514 case OPTION_NO_M3900:
10518 mips_opts.ase_mdmx = 1;
10521 case OPTION_NO_MDMX:
10522 mips_opts.ase_mdmx = 0;
10525 case OPTION_MIPS16:
10526 mips_opts.mips16 = 1;
10527 mips_no_prev_insn (FALSE);
10530 case OPTION_NO_MIPS16:
10531 mips_opts.mips16 = 0;
10532 mips_no_prev_insn (FALSE);
10535 case OPTION_MIPS3D:
10536 mips_opts.ase_mips3d = 1;
10539 case OPTION_NO_MIPS3D:
10540 mips_opts.ase_mips3d = 0;
10543 case OPTION_MEMBEDDED_PIC:
10544 mips_pic = EMBEDDED_PIC;
10545 if (USE_GLOBAL_POINTER_OPT && g_switch_seen)
10547 as_bad (_("-G may not be used with embedded PIC code"));
10550 g_switch_value = 0x7fffffff;
10553 case OPTION_FIX_VR4122:
10554 mips_fix_4122_bugs = 1;
10557 case OPTION_NO_FIX_VR4122:
10558 mips_fix_4122_bugs = 0;
10561 case OPTION_RELAX_BRANCH:
10562 mips_relax_branch = 1;
10565 case OPTION_NO_RELAX_BRANCH:
10566 mips_relax_branch = 0;
10570 /* When generating ELF code, we permit -KPIC and -call_shared to
10571 select SVR4_PIC, and -non_shared to select no PIC. This is
10572 intended to be compatible with Irix 5. */
10573 case OPTION_CALL_SHARED:
10574 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10576 as_bad (_("-call_shared is supported only for ELF format"));
10579 mips_pic = SVR4_PIC;
10580 if (g_switch_seen && g_switch_value != 0)
10582 as_bad (_("-G may not be used with SVR4 PIC code"));
10585 g_switch_value = 0;
10588 case OPTION_NON_SHARED:
10589 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10591 as_bad (_("-non_shared is supported only for ELF format"));
10597 /* The -xgot option tells the assembler to use 32 offsets when
10598 accessing the got in SVR4_PIC mode. It is for Irix
10603 #endif /* OBJ_ELF */
10606 if (! USE_GLOBAL_POINTER_OPT)
10608 as_bad (_("-G is not supported for this configuration"));
10611 else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC)
10613 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
10617 g_switch_value = atoi (arg);
10622 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10625 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10627 as_bad (_("-32 is supported for ELF format only"));
10630 mips_abi = O32_ABI;
10634 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10636 as_bad (_("-n32 is supported for ELF format only"));
10639 mips_abi = N32_ABI;
10643 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10645 as_bad (_("-64 is supported for ELF format only"));
10648 mips_abi = N64_ABI;
10649 if (! support_64bit_objects())
10650 as_fatal (_("No compiled in support for 64 bit object file format"));
10652 #endif /* OBJ_ELF */
10655 file_mips_gp32 = 1;
10659 file_mips_gp32 = 0;
10663 file_mips_fp32 = 1;
10667 file_mips_fp32 = 0;
10672 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10674 as_bad (_("-mabi is supported for ELF format only"));
10677 if (strcmp (arg, "32") == 0)
10678 mips_abi = O32_ABI;
10679 else if (strcmp (arg, "o64") == 0)
10680 mips_abi = O64_ABI;
10681 else if (strcmp (arg, "n32") == 0)
10682 mips_abi = N32_ABI;
10683 else if (strcmp (arg, "64") == 0)
10685 mips_abi = N64_ABI;
10686 if (! support_64bit_objects())
10687 as_fatal (_("No compiled in support for 64 bit object file "
10690 else if (strcmp (arg, "eabi") == 0)
10691 mips_abi = EABI_ABI;
10694 as_fatal (_("invalid abi -mabi=%s"), arg);
10698 #endif /* OBJ_ELF */
10700 case OPTION_M7000_HILO_FIX:
10701 mips_7000_hilo_fix = TRUE;
10704 case OPTION_MNO_7000_HILO_FIX:
10705 mips_7000_hilo_fix = FALSE;
10709 case OPTION_MDEBUG:
10710 mips_flag_mdebug = TRUE;
10713 case OPTION_NO_MDEBUG:
10714 mips_flag_mdebug = FALSE;
10716 #endif /* OBJ_ELF */
10725 /* Set up globals to generate code for the ISA or processor
10726 described by INFO. */
10729 mips_set_architecture (info)
10730 const struct mips_cpu_info *info;
10734 mips_arch_info = info;
10735 mips_arch = info->cpu;
10736 mips_opts.isa = info->isa;
10741 /* Likewise for tuning. */
10744 mips_set_tune (info)
10745 const struct mips_cpu_info *info;
10749 mips_tune_info = info;
10750 mips_tune = info->cpu;
10756 mips_after_parse_args ()
10758 /* GP relative stuff not working for PE */
10759 if (strncmp (TARGET_OS, "pe", 2) == 0
10760 && g_switch_value != 0)
10763 as_bad (_("-G not supported in this configuration."));
10764 g_switch_value = 0;
10767 /* The following code determines the architecture and register size.
10768 Similar code was added to GCC 3.3 (see override_options() in
10769 config/mips/mips.c). The GAS and GCC code should be kept in sync
10770 as much as possible. */
10772 if (mips_arch_string != 0)
10773 mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string));
10775 if (mips_tune_string != 0)
10776 mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string));
10778 if (file_mips_isa != ISA_UNKNOWN)
10780 /* Handle -mipsN. At this point, file_mips_isa contains the
10781 ISA level specified by -mipsN, while mips_opts.isa contains
10782 the -march selection (if any). */
10783 if (mips_arch_info != 0)
10785 /* -march takes precedence over -mipsN, since it is more descriptive.
10786 There's no harm in specifying both as long as the ISA levels
10788 if (file_mips_isa != mips_opts.isa)
10789 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10790 mips_cpu_info_from_isa (file_mips_isa)->name,
10791 mips_cpu_info_from_isa (mips_opts.isa)->name);
10794 mips_set_architecture (mips_cpu_info_from_isa (file_mips_isa));
10797 if (mips_arch_info == 0)
10798 mips_set_architecture (mips_parse_cpu ("default CPU",
10799 MIPS_CPU_STRING_DEFAULT));
10801 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (mips_opts.isa))
10802 as_bad ("-march=%s is not compatible with the selected ABI",
10803 mips_arch_info->name);
10805 /* Optimize for mips_arch, unless -mtune selects a different processor. */
10806 if (mips_tune_info == 0)
10807 mips_set_tune (mips_arch_info);
10809 if (file_mips_gp32 >= 0)
10811 /* The user specified the size of the integer registers. Make sure
10812 it agrees with the ABI and ISA. */
10813 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
10814 as_bad (_("-mgp64 used with a 32-bit processor"));
10815 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
10816 as_bad (_("-mgp32 used with a 64-bit ABI"));
10817 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
10818 as_bad (_("-mgp64 used with a 32-bit ABI"));
10822 /* Infer the integer register size from the ABI and processor.
10823 Restrict ourselves to 32-bit registers if that's all the
10824 processor has, or if the ABI cannot handle 64-bit registers. */
10825 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
10826 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
10829 /* ??? GAS treats single-float processors as though they had 64-bit
10830 float registers (although it complains when double-precision
10831 instructions are used). As things stand, saying they have 32-bit
10832 registers would lead to spurious "register must be even" messages.
10833 So here we assume float registers are always the same size as
10834 integer ones, unless the user says otherwise. */
10835 if (file_mips_fp32 < 0)
10836 file_mips_fp32 = file_mips_gp32;
10838 /* End of GCC-shared inference code. */
10840 /* ??? When do we want this flag to be set? Who uses it? */
10841 if (file_mips_gp32 == 1
10842 && mips_abi == NO_ABI
10843 && ISA_HAS_64BIT_REGS (mips_opts.isa))
10844 mips_32bitmode = 1;
10846 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
10847 as_bad (_("trap exception not supported at ISA 1"));
10849 /* If the selected architecture includes support for ASEs, enable
10850 generation of code for them. */
10851 if (mips_opts.mips16 == -1)
10852 mips_opts.mips16 = (CPU_HAS_MIPS16 (mips_arch)) ? 1 : 0;
10853 if (mips_opts.ase_mips3d == -1)
10854 mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (mips_arch)) ? 1 : 0;
10855 if (mips_opts.ase_mdmx == -1)
10856 mips_opts.ase_mdmx = (CPU_HAS_MDMX (mips_arch)) ? 1 : 0;
10858 file_mips_isa = mips_opts.isa;
10859 file_ase_mips16 = mips_opts.mips16;
10860 file_ase_mips3d = mips_opts.ase_mips3d;
10861 file_ase_mdmx = mips_opts.ase_mdmx;
10862 mips_opts.gp32 = file_mips_gp32;
10863 mips_opts.fp32 = file_mips_fp32;
10865 if (mips_flag_mdebug < 0)
10867 #ifdef OBJ_MAYBE_ECOFF
10868 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
10869 mips_flag_mdebug = 1;
10871 #endif /* OBJ_MAYBE_ECOFF */
10872 mips_flag_mdebug = 0;
10877 mips_init_after_args ()
10879 /* initialize opcodes */
10880 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
10881 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
10885 md_pcrel_from (fixP)
10888 if (OUTPUT_FLAVOR != bfd_target_aout_flavour
10889 && fixP->fx_addsy != (symbolS *) NULL
10890 && ! S_IS_DEFINED (fixP->fx_addsy))
10893 /* Return the address of the delay slot. */
10894 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10897 /* This is called before the symbol table is processed. In order to
10898 work with gcc when using mips-tfile, we must keep all local labels.
10899 However, in other cases, we want to discard them. If we were
10900 called with -g, but we didn't see any debugging information, it may
10901 mean that gcc is smuggling debugging information through to
10902 mips-tfile, in which case we must generate all local labels. */
10905 mips_frob_file_before_adjust ()
10907 #ifndef NO_ECOFF_DEBUGGING
10908 if (ECOFF_DEBUGGING
10910 && ! ecoff_debugging_seen)
10911 flag_keep_locals = 1;
10915 /* Sort any unmatched HI16_S relocs so that they immediately precede
10916 the corresponding LO reloc. This is called before md_apply_fix3 and
10917 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10918 explicit use of the %hi modifier. */
10923 struct mips_hi_fixup *l;
10925 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
10927 segment_info_type *seginfo;
10930 assert (reloc_needs_lo_p (l->fixp->fx_r_type));
10932 /* If a GOT16 relocation turns out to be against a global symbol,
10933 there isn't supposed to be a matching LO. */
10934 if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
10935 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
10938 /* Check quickly whether the next fixup happens to be a matching %lo. */
10939 if (fixup_has_matching_lo_p (l->fixp))
10942 /* Look through the fixups for this segment for a matching %lo.
10943 When we find one, move the %hi just in front of it. We do
10944 this in two passes. In the first pass, we try to find a
10945 unique %lo. In the second pass, we permit multiple %hi
10946 relocs for a single %lo (this is a GNU extension). */
10947 seginfo = seg_info (l->seg);
10948 for (pass = 0; pass < 2; pass++)
10953 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
10955 /* Check whether this is a %lo fixup which matches l->fixp. */
10956 if (f->fx_r_type == BFD_RELOC_LO16
10957 && f->fx_addsy == l->fixp->fx_addsy
10958 && f->fx_offset == l->fixp->fx_offset
10961 || !reloc_needs_lo_p (prev->fx_r_type)
10962 || !fixup_has_matching_lo_p (prev)))
10966 /* Move l->fixp before f. */
10967 for (pf = &seginfo->fix_root;
10969 pf = &(*pf)->fx_next)
10970 assert (*pf != NULL);
10972 *pf = l->fixp->fx_next;
10974 l->fixp->fx_next = f;
10976 seginfo->fix_root = l->fixp;
10978 prev->fx_next = l->fixp;
10989 #if 0 /* GCC code motion plus incomplete dead code elimination
10990 can leave a %hi without a %lo. */
10992 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
10993 _("Unmatched %%hi reloc"));
10999 /* When generating embedded PIC code we need to use a special
11000 relocation to represent the difference of two symbols in the .text
11001 section (switch tables use a difference of this sort). See
11002 include/coff/mips.h for details. This macro checks whether this
11003 fixup requires the special reloc. */
11004 #define SWITCH_TABLE(fixp) \
11005 ((fixp)->fx_r_type == BFD_RELOC_32 \
11006 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
11007 && (fixp)->fx_addsy != NULL \
11008 && (fixp)->fx_subsy != NULL \
11009 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
11010 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
11012 /* When generating embedded PIC code we must keep all PC relative
11013 relocations, in case the linker has to relax a call. We also need
11014 to keep relocations for switch table entries.
11016 We may have combined relocations without symbols in the N32/N64 ABI.
11017 We have to prevent gas from dropping them. */
11020 mips_force_relocation (fixp)
11023 if (generic_force_reloc (fixp))
11027 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
11028 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
11029 || fixp->fx_r_type == BFD_RELOC_HI16_S
11030 || fixp->fx_r_type == BFD_RELOC_LO16))
11033 return (mips_pic == EMBEDDED_PIC
11035 || SWITCH_TABLE (fixp)
11036 || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S
11037 || fixp->fx_r_type == BFD_RELOC_PCREL_LO16));
11040 /* This hook is called before a fix is simplified. We don't really
11041 decide whether to skip a fix here. Rather, we turn global symbols
11042 used as branch targets into local symbols, such that they undergo
11043 simplification. We can only do this if the symbol is defined and
11044 it is in the same section as the branch. If this doesn't hold, we
11045 emit a better error message than just saying the relocation is not
11046 valid for the selected object format.
11048 FIXP is the fix-up we're going to try to simplify, SEG is the
11049 segment in which the fix up occurs. The return value should be
11050 non-zero to indicate the fix-up is valid for further
11051 simplifications. */
11054 mips_validate_fix (fixP, seg)
11058 /* There's a lot of discussion on whether it should be possible to
11059 use R_MIPS_PC16 to represent branch relocations. The outcome
11060 seems to be that it can, but gas/bfd are very broken in creating
11061 RELA relocations for this, so for now we only accept branches to
11062 symbols in the same section. Anything else is of dubious value,
11063 since there's no guarantee that at link time the symbol would be
11064 in range. Even for branches to local symbols this is arguably
11065 wrong, since it we assume the symbol is not going to be
11066 overridden, which should be possible per ELF library semantics,
11067 but then, there isn't a dynamic relocation that could be used to
11068 this effect, and the target would likely be out of range as well.
11070 Unfortunately, it seems that there is too much code out there
11071 that relies on branches to symbols that are global to be resolved
11072 as if they were local, like the IRIX tools do, so we do it as
11073 well, but with a warning so that people are reminded to fix their
11074 code. If we ever get back to using R_MIPS_PC16 for branch
11075 targets, this entire block should go away (and probably the
11076 whole function). */
11078 if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
11079 && (((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
11080 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
11081 && mips_pic != EMBEDDED_PIC)
11082 || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL)
11085 if (! S_IS_DEFINED (fixP->fx_addsy))
11087 as_bad_where (fixP->fx_file, fixP->fx_line,
11088 _("Cannot branch to undefined symbol."));
11089 /* Avoid any further errors about this fixup. */
11092 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
11094 as_bad_where (fixP->fx_file, fixP->fx_line,
11095 _("Cannot branch to symbol in another section."));
11098 else if (S_IS_EXTERNAL (fixP->fx_addsy))
11100 symbolS *sym = fixP->fx_addsy;
11102 as_warn_where (fixP->fx_file, fixP->fx_line,
11103 _("Pretending global symbol used as branch target is local."));
11105 fixP->fx_addsy = symbol_create (S_GET_NAME (sym),
11106 S_GET_SEGMENT (sym),
11108 symbol_get_frag (sym));
11109 copy_symbol_attributes (fixP->fx_addsy, sym);
11110 S_CLEAR_EXTERNAL (fixP->fx_addsy);
11111 assert (symbol_resolved_p (sym));
11112 symbol_mark_resolved (fixP->fx_addsy);
11121 mips_need_elf_addend_fixup (fixP)
11124 if (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16)
11126 if (mips_pic == EMBEDDED_PIC
11127 && S_IS_WEAK (fixP->fx_addsy))
11129 if (mips_pic != EMBEDDED_PIC
11130 && (S_IS_WEAK (fixP->fx_addsy)
11131 || S_IS_EXTERNAL (fixP->fx_addsy))
11132 && !S_IS_COMMON (fixP->fx_addsy))
11134 if (symbol_used_in_reloc_p (fixP->fx_addsy)
11135 && (((bfd_get_section_flags (stdoutput,
11136 S_GET_SEGMENT (fixP->fx_addsy))
11137 & (SEC_LINK_ONCE | SEC_MERGE)) != 0)
11138 || !strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)),
11140 sizeof (".gnu.linkonce") - 1)))
11146 /* Apply a fixup to the object file. */
11149 md_apply_fix3 (fixP, valP, seg)
11152 segT seg ATTRIBUTE_UNUSED;
11157 static int previous_fx_r_type = 0;
11159 /* FIXME: Maybe just return for all reloc types not listed below?
11160 Eric Christopher says: "This is stupid, please rewrite md_apply_fix3. */
11161 if (fixP->fx_r_type == BFD_RELOC_8)
11164 assert (fixP->fx_size == 4
11165 || fixP->fx_r_type == BFD_RELOC_16
11166 || fixP->fx_r_type == BFD_RELOC_32
11167 || fixP->fx_r_type == BFD_RELOC_MIPS_JMP
11168 || fixP->fx_r_type == BFD_RELOC_HI16_S
11169 || fixP->fx_r_type == BFD_RELOC_LO16
11170 || fixP->fx_r_type == BFD_RELOC_GPREL16
11171 || fixP->fx_r_type == BFD_RELOC_MIPS_LITERAL
11172 || fixP->fx_r_type == BFD_RELOC_GPREL32
11173 || fixP->fx_r_type == BFD_RELOC_64
11174 || fixP->fx_r_type == BFD_RELOC_CTOR
11175 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
11176 || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHEST
11177 || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHER
11178 || fixP->fx_r_type == BFD_RELOC_MIPS_SCN_DISP
11179 || fixP->fx_r_type == BFD_RELOC_MIPS_REL16
11180 || fixP->fx_r_type == BFD_RELOC_MIPS_RELGOT
11181 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
11182 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
11183 || fixP->fx_r_type == BFD_RELOC_MIPS_JALR);
11187 /* If we aren't adjusting this fixup to be against the section
11188 symbol, we need to adjust the value. */
11190 if (fixP->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour)
11192 if (mips_need_elf_addend_fixup (fixP))
11194 reloc_howto_type *howto;
11195 valueT symval = S_GET_VALUE (fixP->fx_addsy);
11199 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
11200 if (value != 0 && howto && howto->partial_inplace
11201 && (! fixP->fx_pcrel || howto->pcrel_offset))
11203 /* In this case, the bfd_install_relocation routine will
11204 incorrectly add the symbol value back in. We just want
11205 the addend to appear in the object file.
11207 howto->pcrel_offset is added for R_MIPS_PC16, which is
11208 generated for code like
11219 /* Make sure the addend is still non-zero. If it became zero
11220 after the last operation, set it to a spurious value and
11221 subtract the same value from the object file's contents. */
11226 /* The in-place addends for LO16 relocations are signed;
11227 leave the matching HI16 in-place addends as zero. */
11228 if (fixP->fx_r_type != BFD_RELOC_HI16_S)
11230 bfd_vma contents, mask, field;
11232 contents = bfd_get_bits (fixP->fx_frag->fr_literal
11235 target_big_endian);
11237 /* MASK has bits set where the relocation should go.
11238 FIELD is -value, shifted into the appropriate place
11239 for this relocation. */
11240 mask = 1 << (howto->bitsize - 1);
11241 mask = (((mask - 1) << 1) | 1) << howto->bitpos;
11242 field = (-value >> howto->rightshift) << howto->bitpos;
11244 bfd_put_bits ((field & mask) | (contents & ~mask),
11245 fixP->fx_frag->fr_literal + fixP->fx_where,
11247 target_big_endian);
11253 /* This code was generated using trial and error and so is
11254 fragile and not trustworthy. If you change it, you should
11255 rerun the elf-rel, elf-rel2, and empic testcases and ensure
11256 they still pass. */
11257 if (fixP->fx_pcrel || fixP->fx_subsy != NULL)
11259 value += fixP->fx_frag->fr_address + fixP->fx_where;
11261 /* BFD's REL handling, for MIPS, is _very_ weird.
11262 This gives the right results, but it can't possibly
11263 be the way things are supposed to work. */
11264 if (fixP->fx_r_type != BFD_RELOC_16_PCREL_S2
11265 || S_GET_SEGMENT (fixP->fx_addsy) != undefined_section)
11266 value += fixP->fx_frag->fr_address + fixP->fx_where;
11271 fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc. */
11273 /* We are not done if this is a composite relocation to set up gp. */
11274 if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel
11275 && !(fixP->fx_r_type == BFD_RELOC_MIPS_SUB
11276 || (fixP->fx_r_type == BFD_RELOC_64
11277 && (previous_fx_r_type == BFD_RELOC_GPREL32
11278 || previous_fx_r_type == BFD_RELOC_GPREL16))
11279 || (previous_fx_r_type == BFD_RELOC_MIPS_SUB
11280 && (fixP->fx_r_type == BFD_RELOC_HI16_S
11281 || fixP->fx_r_type == BFD_RELOC_LO16))))
11283 previous_fx_r_type = fixP->fx_r_type;
11285 switch (fixP->fx_r_type)
11287 case BFD_RELOC_MIPS_JMP:
11288 case BFD_RELOC_MIPS_SHIFT5:
11289 case BFD_RELOC_MIPS_SHIFT6:
11290 case BFD_RELOC_MIPS_GOT_DISP:
11291 case BFD_RELOC_MIPS_GOT_PAGE:
11292 case BFD_RELOC_MIPS_GOT_OFST:
11293 case BFD_RELOC_MIPS_SUB:
11294 case BFD_RELOC_MIPS_INSERT_A:
11295 case BFD_RELOC_MIPS_INSERT_B:
11296 case BFD_RELOC_MIPS_DELETE:
11297 case BFD_RELOC_MIPS_HIGHEST:
11298 case BFD_RELOC_MIPS_HIGHER:
11299 case BFD_RELOC_MIPS_SCN_DISP:
11300 case BFD_RELOC_MIPS_REL16:
11301 case BFD_RELOC_MIPS_RELGOT:
11302 case BFD_RELOC_MIPS_JALR:
11303 case BFD_RELOC_HI16:
11304 case BFD_RELOC_HI16_S:
11305 case BFD_RELOC_GPREL16:
11306 case BFD_RELOC_MIPS_LITERAL:
11307 case BFD_RELOC_MIPS_CALL16:
11308 case BFD_RELOC_MIPS_GOT16:
11309 case BFD_RELOC_GPREL32:
11310 case BFD_RELOC_MIPS_GOT_HI16:
11311 case BFD_RELOC_MIPS_GOT_LO16:
11312 case BFD_RELOC_MIPS_CALL_HI16:
11313 case BFD_RELOC_MIPS_CALL_LO16:
11314 case BFD_RELOC_MIPS16_GPREL:
11315 if (fixP->fx_pcrel)
11316 as_bad_where (fixP->fx_file, fixP->fx_line,
11317 _("Invalid PC relative reloc"));
11318 /* Nothing needed to do. The value comes from the reloc entry */
11321 case BFD_RELOC_MIPS16_JMP:
11322 /* We currently always generate a reloc against a symbol, which
11323 means that we don't want an addend even if the symbol is
11325 fixP->fx_addnumber = 0;
11328 case BFD_RELOC_PCREL_HI16_S:
11329 /* The addend for this is tricky if it is internal, so we just
11330 do everything here rather than in bfd_install_relocation. */
11331 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
11336 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
11338 /* For an external symbol adjust by the address to make it
11339 pcrel_offset. We use the address of the RELLO reloc
11340 which follows this one. */
11341 value += (fixP->fx_next->fx_frag->fr_address
11342 + fixP->fx_next->fx_where);
11344 value = ((value + 0x8000) >> 16) & 0xffff;
11345 buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where;
11346 if (target_big_endian)
11348 md_number_to_chars ((char *) buf, value, 2);
11351 case BFD_RELOC_PCREL_LO16:
11352 /* The addend for this is tricky if it is internal, so we just
11353 do everything here rather than in bfd_install_relocation. */
11354 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
11359 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
11360 value += fixP->fx_frag->fr_address + fixP->fx_where;
11361 buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where;
11362 if (target_big_endian)
11364 md_number_to_chars ((char *) buf, value, 2);
11368 /* This is handled like BFD_RELOC_32, but we output a sign
11369 extended value if we are only 32 bits. */
11371 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
11373 if (8 <= sizeof (valueT))
11374 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
11381 w1 = w2 = fixP->fx_where;
11382 if (target_big_endian)
11386 md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4);
11387 if ((value & 0x80000000) != 0)
11391 md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4);
11396 case BFD_RELOC_RVA:
11398 /* If we are deleting this reloc entry, we must fill in the
11399 value now. This can happen if we have a .word which is not
11400 resolved when it appears but is later defined. We also need
11401 to fill in the value if this is an embedded PIC switch table
11404 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
11405 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
11410 /* If we are deleting this reloc entry, we must fill in the
11412 assert (fixP->fx_size == 2);
11414 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
11418 case BFD_RELOC_LO16:
11419 /* When handling an embedded PIC switch statement, we can wind
11420 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11423 if (value + 0x8000 > 0xffff)
11424 as_bad_where (fixP->fx_file, fixP->fx_line,
11425 _("relocation overflow"));
11426 buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where;
11427 if (target_big_endian)
11429 md_number_to_chars ((char *) buf, value, 2);
11433 case BFD_RELOC_16_PCREL_S2:
11434 if ((value & 0x3) != 0)
11435 as_bad_where (fixP->fx_file, fixP->fx_line,
11436 _("Branch to odd address (%lx)"), (long) value);
11439 * We need to save the bits in the instruction since fixup_segment()
11440 * might be deleting the relocation entry (i.e., a branch within
11441 * the current segment).
11443 if (!fixP->fx_done && (value != 0 || HAVE_NEWABI))
11445 /* If 'value' is zero, the remaining reloc code won't actually
11446 do the store, so it must be done here. This is probably
11447 a bug somewhere. */
11449 && (fixP->fx_r_type != BFD_RELOC_16_PCREL_S2
11450 || fixP->fx_addsy == NULL /* ??? */
11451 || ! S_IS_DEFINED (fixP->fx_addsy)))
11452 value -= fixP->fx_frag->fr_address + fixP->fx_where;
11454 value = (offsetT) value >> 2;
11456 /* update old instruction data */
11457 buf = (bfd_byte *) (fixP->fx_where + fixP->fx_frag->fr_literal);
11458 if (target_big_endian)
11459 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
11461 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
11463 if (value + 0x8000 <= 0xffff)
11464 insn |= value & 0xffff;
11467 /* The branch offset is too large. If this is an
11468 unconditional branch, and we are not generating PIC code,
11469 we can convert it to an absolute jump instruction. */
11470 if (mips_pic == NO_PIC
11472 && fixP->fx_frag->fr_address >= text_section->vma
11473 && (fixP->fx_frag->fr_address
11474 < text_section->vma + text_section->_raw_size)
11475 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
11476 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
11477 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
11479 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
11480 insn = 0x0c000000; /* jal */
11482 insn = 0x08000000; /* j */
11483 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
11485 fixP->fx_addsy = section_symbol (text_section);
11486 fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP);
11490 /* If we got here, we have branch-relaxation disabled,
11491 and there's nothing we can do to fix this instruction
11492 without turning it into a longer sequence. */
11493 as_bad_where (fixP->fx_file, fixP->fx_line,
11494 _("Branch out of range"));
11498 md_number_to_chars ((char *) buf, (valueT) insn, 4);
11501 case BFD_RELOC_VTABLE_INHERIT:
11504 && !S_IS_DEFINED (fixP->fx_addsy)
11505 && !S_IS_WEAK (fixP->fx_addsy))
11506 S_SET_WEAK (fixP->fx_addsy);
11509 case BFD_RELOC_VTABLE_ENTRY:
11523 const struct mips_opcode *p;
11524 int treg, sreg, dreg, shamt;
11529 for (i = 0; i < NUMOPCODES; ++i)
11531 p = &mips_opcodes[i];
11532 if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO))
11534 printf ("%08lx %s\t", oc, p->name);
11535 treg = (oc >> 16) & 0x1f;
11536 sreg = (oc >> 21) & 0x1f;
11537 dreg = (oc >> 11) & 0x1f;
11538 shamt = (oc >> 6) & 0x1f;
11540 for (args = p->args;; ++args)
11551 printf ("%c", *args);
11555 assert (treg == sreg);
11556 printf ("$%d,$%d", treg, sreg);
11561 printf ("$%d", dreg);
11566 printf ("$%d", treg);
11570 printf ("0x%x", treg);
11575 printf ("$%d", sreg);
11579 printf ("0x%08lx", oc & 0x1ffffff);
11586 printf ("%d", imm);
11591 printf ("$%d", shamt);
11602 printf (_("%08lx UNDEFINED\n"), oc);
11613 name = input_line_pointer;
11614 c = get_symbol_end ();
11615 p = (symbolS *) symbol_find_or_make (name);
11616 *input_line_pointer = c;
11620 /* Align the current frag to a given power of two. The MIPS assembler
11621 also automatically adjusts any preceding label. */
11624 mips_align (to, fill, label)
11629 mips_emit_delays (FALSE);
11630 frag_align (to, fill, 0);
11631 record_alignment (now_seg, to);
11634 assert (S_GET_SEGMENT (label) == now_seg);
11635 symbol_set_frag (label, frag_now);
11636 S_SET_VALUE (label, (valueT) frag_now_fix ());
11640 /* Align to a given power of two. .align 0 turns off the automatic
11641 alignment used by the data creating pseudo-ops. */
11645 int x ATTRIBUTE_UNUSED;
11648 register long temp_fill;
11649 long max_alignment = 15;
11653 o Note that the assembler pulls down any immediately preceeding label
11654 to the aligned address.
11655 o It's not documented but auto alignment is reinstated by
11656 a .align pseudo instruction.
11657 o Note also that after auto alignment is turned off the mips assembler
11658 issues an error on attempt to assemble an improperly aligned data item.
11663 temp = get_absolute_expression ();
11664 if (temp > max_alignment)
11665 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
11668 as_warn (_("Alignment negative: 0 assumed."));
11671 if (*input_line_pointer == ',')
11673 ++input_line_pointer;
11674 temp_fill = get_absolute_expression ();
11681 mips_align (temp, (int) temp_fill,
11682 insn_labels != NULL ? insn_labels->label : NULL);
11689 demand_empty_rest_of_line ();
11693 mips_flush_pending_output ()
11695 mips_emit_delays (FALSE);
11696 mips_clear_insn_labels ();
11705 /* When generating embedded PIC code, we only use the .text, .lit8,
11706 .sdata and .sbss sections. We change the .data and .rdata
11707 pseudo-ops to use .sdata. */
11708 if (mips_pic == EMBEDDED_PIC
11709 && (sec == 'd' || sec == 'r'))
11713 /* The ELF backend needs to know that we are changing sections, so
11714 that .previous works correctly. We could do something like check
11715 for an obj_section_change_hook macro, but that might be confusing
11716 as it would not be appropriate to use it in the section changing
11717 functions in read.c, since obj-elf.c intercepts those. FIXME:
11718 This should be cleaner, somehow. */
11719 obj_elf_section_change_hook ();
11722 mips_emit_delays (FALSE);
11732 subseg_set (bss_section, (subsegT) get_absolute_expression ());
11733 demand_empty_rest_of_line ();
11737 if (USE_GLOBAL_POINTER_OPT)
11739 seg = subseg_new (RDATA_SECTION_NAME,
11740 (subsegT) get_absolute_expression ());
11741 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11743 bfd_set_section_flags (stdoutput, seg,
11749 if (strcmp (TARGET_OS, "elf") != 0)
11750 record_alignment (seg, 4);
11752 demand_empty_rest_of_line ();
11756 as_bad (_("No read only data section in this object file format"));
11757 demand_empty_rest_of_line ();
11763 if (USE_GLOBAL_POINTER_OPT)
11765 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
11766 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11768 bfd_set_section_flags (stdoutput, seg,
11769 SEC_ALLOC | SEC_LOAD | SEC_RELOC
11771 if (strcmp (TARGET_OS, "elf") != 0)
11772 record_alignment (seg, 4);
11774 demand_empty_rest_of_line ();
11779 as_bad (_("Global pointers not supported; recompile -G 0"));
11780 demand_empty_rest_of_line ();
11789 s_change_section (ignore)
11790 int ignore ATTRIBUTE_UNUSED;
11793 char *section_name;
11798 int section_entry_size;
11799 int section_alignment;
11801 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
11804 section_name = input_line_pointer;
11805 c = get_symbol_end ();
11807 next_c = *(input_line_pointer + 1);
11809 /* Do we have .section Name<,"flags">? */
11810 if (c != ',' || (c == ',' && next_c == '"'))
11812 /* just after name is now '\0'. */
11813 *input_line_pointer = c;
11814 input_line_pointer = section_name;
11815 obj_elf_section (ignore);
11818 input_line_pointer++;
11820 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11822 section_type = get_absolute_expression ();
11825 if (*input_line_pointer++ == ',')
11826 section_flag = get_absolute_expression ();
11829 if (*input_line_pointer++ == ',')
11830 section_entry_size = get_absolute_expression ();
11832 section_entry_size = 0;
11833 if (*input_line_pointer++ == ',')
11834 section_alignment = get_absolute_expression ();
11836 section_alignment = 0;
11838 section_name = xstrdup (section_name);
11840 obj_elf_change_section (section_name, section_type, section_flag,
11841 section_entry_size, 0, 0, 0);
11843 if (now_seg->name != section_name)
11844 free (section_name);
11845 #endif /* OBJ_ELF */
11849 mips_enable_auto_align ()
11860 label = insn_labels != NULL ? insn_labels->label : NULL;
11861 mips_emit_delays (FALSE);
11862 if (log_size > 0 && auto_align)
11863 mips_align (log_size, 0, label);
11864 mips_clear_insn_labels ();
11865 cons (1 << log_size);
11869 s_float_cons (type)
11874 label = insn_labels != NULL ? insn_labels->label : NULL;
11876 mips_emit_delays (FALSE);
11881 mips_align (3, 0, label);
11883 mips_align (2, 0, label);
11886 mips_clear_insn_labels ();
11891 /* Handle .globl. We need to override it because on Irix 5 you are
11894 where foo is an undefined symbol, to mean that foo should be
11895 considered to be the address of a function. */
11899 int x ATTRIBUTE_UNUSED;
11906 name = input_line_pointer;
11907 c = get_symbol_end ();
11908 symbolP = symbol_find_or_make (name);
11909 *input_line_pointer = c;
11910 SKIP_WHITESPACE ();
11912 /* On Irix 5, every global symbol that is not explicitly labelled as
11913 being a function is apparently labelled as being an object. */
11916 if (! is_end_of_line[(unsigned char) *input_line_pointer])
11921 secname = input_line_pointer;
11922 c = get_symbol_end ();
11923 sec = bfd_get_section_by_name (stdoutput, secname);
11925 as_bad (_("%s: no such section"), secname);
11926 *input_line_pointer = c;
11928 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
11929 flag = BSF_FUNCTION;
11932 symbol_get_bfdsym (symbolP)->flags |= flag;
11934 S_SET_EXTERNAL (symbolP);
11935 demand_empty_rest_of_line ();
11940 int x ATTRIBUTE_UNUSED;
11945 opt = input_line_pointer;
11946 c = get_symbol_end ();
11950 /* FIXME: What does this mean? */
11952 else if (strncmp (opt, "pic", 3) == 0)
11956 i = atoi (opt + 3);
11960 mips_pic = SVR4_PIC;
11962 as_bad (_(".option pic%d not supported"), i);
11964 if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC)
11966 if (g_switch_seen && g_switch_value != 0)
11967 as_warn (_("-G may not be used with SVR4 PIC code"));
11968 g_switch_value = 0;
11969 bfd_set_gp_size (stdoutput, 0);
11973 as_warn (_("Unrecognized option \"%s\""), opt);
11975 *input_line_pointer = c;
11976 demand_empty_rest_of_line ();
11979 /* This structure is used to hold a stack of .set values. */
11981 struct mips_option_stack
11983 struct mips_option_stack *next;
11984 struct mips_set_options options;
11987 static struct mips_option_stack *mips_opts_stack;
11989 /* Handle the .set pseudo-op. */
11993 int x ATTRIBUTE_UNUSED;
11995 char *name = input_line_pointer, ch;
11997 while (!is_end_of_line[(unsigned char) *input_line_pointer])
11998 ++input_line_pointer;
11999 ch = *input_line_pointer;
12000 *input_line_pointer = '\0';
12002 if (strcmp (name, "reorder") == 0)
12004 if (mips_opts.noreorder && prev_nop_frag != NULL)
12006 /* If we still have pending nops, we can discard them. The
12007 usual nop handling will insert any that are still
12009 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
12010 * (mips_opts.mips16 ? 2 : 4));
12011 prev_nop_frag = NULL;
12013 mips_opts.noreorder = 0;
12015 else if (strcmp (name, "noreorder") == 0)
12017 mips_emit_delays (TRUE);
12018 mips_opts.noreorder = 1;
12019 mips_any_noreorder = 1;
12021 else if (strcmp (name, "at") == 0)
12023 mips_opts.noat = 0;
12025 else if (strcmp (name, "noat") == 0)
12027 mips_opts.noat = 1;
12029 else if (strcmp (name, "macro") == 0)
12031 mips_opts.warn_about_macros = 0;
12033 else if (strcmp (name, "nomacro") == 0)
12035 if (mips_opts.noreorder == 0)
12036 as_bad (_("`noreorder' must be set before `nomacro'"));
12037 mips_opts.warn_about_macros = 1;
12039 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
12041 mips_opts.nomove = 0;
12043 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
12045 mips_opts.nomove = 1;
12047 else if (strcmp (name, "bopt") == 0)
12049 mips_opts.nobopt = 0;
12051 else if (strcmp (name, "nobopt") == 0)
12053 mips_opts.nobopt = 1;
12055 else if (strcmp (name, "mips16") == 0
12056 || strcmp (name, "MIPS-16") == 0)
12057 mips_opts.mips16 = 1;
12058 else if (strcmp (name, "nomips16") == 0
12059 || strcmp (name, "noMIPS-16") == 0)
12060 mips_opts.mips16 = 0;
12061 else if (strcmp (name, "mips3d") == 0)
12062 mips_opts.ase_mips3d = 1;
12063 else if (strcmp (name, "nomips3d") == 0)
12064 mips_opts.ase_mips3d = 0;
12065 else if (strcmp (name, "mdmx") == 0)
12066 mips_opts.ase_mdmx = 1;
12067 else if (strcmp (name, "nomdmx") == 0)
12068 mips_opts.ase_mdmx = 0;
12069 else if (strncmp (name, "mips", 4) == 0)
12073 /* Permit the user to change the ISA on the fly. Needless to
12074 say, misuse can cause serious problems. */
12075 if (strcmp (name, "mips0") == 0)
12078 mips_opts.isa = file_mips_isa;
12080 else if (strcmp (name, "mips1") == 0)
12081 mips_opts.isa = ISA_MIPS1;
12082 else if (strcmp (name, "mips2") == 0)
12083 mips_opts.isa = ISA_MIPS2;
12084 else if (strcmp (name, "mips3") == 0)
12085 mips_opts.isa = ISA_MIPS3;
12086 else if (strcmp (name, "mips4") == 0)
12087 mips_opts.isa = ISA_MIPS4;
12088 else if (strcmp (name, "mips5") == 0)
12089 mips_opts.isa = ISA_MIPS5;
12090 else if (strcmp (name, "mips32") == 0)
12091 mips_opts.isa = ISA_MIPS32;
12092 else if (strcmp (name, "mips32r2") == 0)
12093 mips_opts.isa = ISA_MIPS32R2;
12094 else if (strcmp (name, "mips64") == 0)
12095 mips_opts.isa = ISA_MIPS64;
12097 as_bad (_("unknown ISA level %s"), name + 4);
12099 switch (mips_opts.isa)
12107 mips_opts.gp32 = 1;
12108 mips_opts.fp32 = 1;
12114 mips_opts.gp32 = 0;
12115 mips_opts.fp32 = 0;
12118 as_bad (_("unknown ISA level %s"), name + 4);
12123 mips_opts.gp32 = file_mips_gp32;
12124 mips_opts.fp32 = file_mips_fp32;
12127 else if (strcmp (name, "autoextend") == 0)
12128 mips_opts.noautoextend = 0;
12129 else if (strcmp (name, "noautoextend") == 0)
12130 mips_opts.noautoextend = 1;
12131 else if (strcmp (name, "push") == 0)
12133 struct mips_option_stack *s;
12135 s = (struct mips_option_stack *) xmalloc (sizeof *s);
12136 s->next = mips_opts_stack;
12137 s->options = mips_opts;
12138 mips_opts_stack = s;
12140 else if (strcmp (name, "pop") == 0)
12142 struct mips_option_stack *s;
12144 s = mips_opts_stack;
12146 as_bad (_(".set pop with no .set push"));
12149 /* If we're changing the reorder mode we need to handle
12150 delay slots correctly. */
12151 if (s->options.noreorder && ! mips_opts.noreorder)
12152 mips_emit_delays (TRUE);
12153 else if (! s->options.noreorder && mips_opts.noreorder)
12155 if (prev_nop_frag != NULL)
12157 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
12158 * (mips_opts.mips16 ? 2 : 4));
12159 prev_nop_frag = NULL;
12163 mips_opts = s->options;
12164 mips_opts_stack = s->next;
12170 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
12172 *input_line_pointer = ch;
12173 demand_empty_rest_of_line ();
12176 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
12177 .option pic2. It means to generate SVR4 PIC calls. */
12180 s_abicalls (ignore)
12181 int ignore ATTRIBUTE_UNUSED;
12183 mips_pic = SVR4_PIC;
12184 if (USE_GLOBAL_POINTER_OPT)
12186 if (g_switch_seen && g_switch_value != 0)
12187 as_warn (_("-G may not be used with SVR4 PIC code"));
12188 g_switch_value = 0;
12190 bfd_set_gp_size (stdoutput, 0);
12191 demand_empty_rest_of_line ();
12194 /* Handle the .cpload pseudo-op. This is used when generating SVR4
12195 PIC code. It sets the $gp register for the function based on the
12196 function address, which is in the register named in the argument.
12197 This uses a relocation against _gp_disp, which is handled specially
12198 by the linker. The result is:
12199 lui $gp,%hi(_gp_disp)
12200 addiu $gp,$gp,%lo(_gp_disp)
12201 addu $gp,$gp,.cpload argument
12202 The .cpload argument is normally $25 == $t9. */
12206 int ignore ATTRIBUTE_UNUSED;
12211 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12212 .cpload is ignored. */
12213 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12219 /* .cpload should be in a .set noreorder section. */
12220 if (mips_opts.noreorder == 0)
12221 as_warn (_(".cpload not in noreorder section"));
12223 ex.X_op = O_symbol;
12224 ex.X_add_symbol = symbol_find_or_make ("_gp_disp");
12225 ex.X_op_symbol = NULL;
12226 ex.X_add_number = 0;
12228 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12229 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
12231 macro_build_lui (NULL, &icnt, &ex, mips_gp_register);
12232 macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j",
12233 mips_gp_register, mips_gp_register, (int) BFD_RELOC_LO16);
12235 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t",
12236 mips_gp_register, mips_gp_register, tc_get_register (0));
12238 demand_empty_rest_of_line ();
12241 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12242 .cpsetup $reg1, offset|$reg2, label
12244 If offset is given, this results in:
12245 sd $gp, offset($sp)
12246 lui $gp, %hi(%neg(%gp_rel(label)))
12247 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12248 daddu $gp, $gp, $reg1
12250 If $reg2 is given, this results in:
12251 daddu $reg2, $gp, $0
12252 lui $gp, %hi(%neg(%gp_rel(label)))
12253 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12254 daddu $gp, $gp, $reg1
12255 $reg1 is normally $25 == $t9. */
12258 int ignore ATTRIBUTE_UNUSED;
12260 expressionS ex_off;
12261 expressionS ex_sym;
12266 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12267 We also need NewABI support. */
12268 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12274 reg1 = tc_get_register (0);
12275 SKIP_WHITESPACE ();
12276 if (*input_line_pointer != ',')
12278 as_bad (_("missing argument separator ',' for .cpsetup"));
12282 ++input_line_pointer;
12283 SKIP_WHITESPACE ();
12284 if (*input_line_pointer == '$')
12286 mips_cpreturn_register = tc_get_register (0);
12287 mips_cpreturn_offset = -1;
12291 mips_cpreturn_offset = get_absolute_expression ();
12292 mips_cpreturn_register = -1;
12294 SKIP_WHITESPACE ();
12295 if (*input_line_pointer != ',')
12297 as_bad (_("missing argument separator ',' for .cpsetup"));
12301 ++input_line_pointer;
12302 SKIP_WHITESPACE ();
12303 expression (&ex_sym);
12305 if (mips_cpreturn_register == -1)
12307 ex_off.X_op = O_constant;
12308 ex_off.X_add_symbol = NULL;
12309 ex_off.X_op_symbol = NULL;
12310 ex_off.X_add_number = mips_cpreturn_offset;
12312 macro_build ((char *) NULL, &icnt, &ex_off, "sd", "t,o(b)",
12313 mips_gp_register, (int) BFD_RELOC_LO16, SP);
12316 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu",
12317 "d,v,t", mips_cpreturn_register, mips_gp_register, 0);
12319 /* Ensure there's room for the next two instructions, so that `f'
12320 doesn't end up with an address in the wrong frag. */
12323 macro_build ((char *) NULL, &icnt, &ex_sym, "lui", "t,u", mips_gp_register,
12324 (int) BFD_RELOC_GPREL16);
12325 fix_new (frag_now, f - frag_now->fr_literal,
12326 0, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
12327 fix_new (frag_now, f - frag_now->fr_literal,
12328 0, NULL, 0, 0, BFD_RELOC_HI16_S);
12331 macro_build ((char *) NULL, &icnt, &ex_sym, "addiu", "t,r,j",
12332 mips_gp_register, mips_gp_register, (int) BFD_RELOC_GPREL16);
12333 fix_new (frag_now, f - frag_now->fr_literal,
12334 0, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
12335 fix_new (frag_now, f - frag_now->fr_literal,
12336 0, NULL, 0, 0, BFD_RELOC_LO16);
12338 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
12339 HAVE_64BIT_ADDRESSES ? "daddu" : "addu", "d,v,t",
12340 mips_gp_register, mips_gp_register, reg1);
12342 demand_empty_rest_of_line ();
12347 int ignore ATTRIBUTE_UNUSED;
12349 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12350 .cplocal is ignored. */
12351 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12357 mips_gp_register = tc_get_register (0);
12358 demand_empty_rest_of_line ();
12361 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12362 offset from $sp. The offset is remembered, and after making a PIC
12363 call $gp is restored from that location. */
12366 s_cprestore (ignore)
12367 int ignore ATTRIBUTE_UNUSED;
12372 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12373 .cprestore is ignored. */
12374 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12380 mips_cprestore_offset = get_absolute_expression ();
12381 mips_cprestore_valid = 1;
12383 ex.X_op = O_constant;
12384 ex.X_add_symbol = NULL;
12385 ex.X_op_symbol = NULL;
12386 ex.X_add_number = mips_cprestore_offset;
12388 macro_build_ldst_constoffset ((char *) NULL, &icnt, &ex,
12389 HAVE_32BIT_ADDRESSES ? "sw" : "sd",
12390 mips_gp_register, SP);
12392 demand_empty_rest_of_line ();
12395 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12396 was given in the preceeding .gpsetup, it results in:
12397 ld $gp, offset($sp)
12399 If a register $reg2 was given there, it results in:
12400 daddiu $gp, $gp, $reg2
12403 s_cpreturn (ignore)
12404 int ignore ATTRIBUTE_UNUSED;
12409 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12410 We also need NewABI support. */
12411 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12417 if (mips_cpreturn_register == -1)
12419 ex.X_op = O_constant;
12420 ex.X_add_symbol = NULL;
12421 ex.X_op_symbol = NULL;
12422 ex.X_add_number = mips_cpreturn_offset;
12424 macro_build ((char *) NULL, &icnt, &ex, "ld", "t,o(b)",
12425 mips_gp_register, (int) BFD_RELOC_LO16, SP);
12428 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu",
12429 "d,v,t", mips_gp_register, mips_cpreturn_register, 0);
12431 demand_empty_rest_of_line ();
12434 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12435 code. It sets the offset to use in gp_rel relocations. */
12439 int ignore ATTRIBUTE_UNUSED;
12441 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12442 We also need NewABI support. */
12443 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12449 mips_gprel_offset = get_absolute_expression ();
12451 demand_empty_rest_of_line ();
12454 /* Handle the .gpword pseudo-op. This is used when generating PIC
12455 code. It generates a 32 bit GP relative reloc. */
12459 int ignore ATTRIBUTE_UNUSED;
12465 /* When not generating PIC code, this is treated as .word. */
12466 if (mips_pic != SVR4_PIC)
12472 label = insn_labels != NULL ? insn_labels->label : NULL;
12473 mips_emit_delays (TRUE);
12475 mips_align (2, 0, label);
12476 mips_clear_insn_labels ();
12480 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12482 as_bad (_("Unsupported use of .gpword"));
12483 ignore_rest_of_line ();
12487 md_number_to_chars (p, (valueT) 0, 4);
12488 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
12489 BFD_RELOC_GPREL32);
12491 demand_empty_rest_of_line ();
12496 int ignore ATTRIBUTE_UNUSED;
12502 /* When not generating PIC code, this is treated as .dword. */
12503 if (mips_pic != SVR4_PIC)
12509 label = insn_labels != NULL ? insn_labels->label : NULL;
12510 mips_emit_delays (TRUE);
12512 mips_align (3, 0, label);
12513 mips_clear_insn_labels ();
12517 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12519 as_bad (_("Unsupported use of .gpdword"));
12520 ignore_rest_of_line ();
12524 md_number_to_chars (p, (valueT) 0, 8);
12525 fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &ex, FALSE,
12526 BFD_RELOC_GPREL32);
12528 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12529 ex.X_op = O_absent;
12530 ex.X_add_symbol = 0;
12531 ex.X_add_number = 0;
12532 fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &ex, FALSE,
12535 demand_empty_rest_of_line ();
12538 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12539 tables in SVR4 PIC code. */
12543 int ignore ATTRIBUTE_UNUSED;
12548 /* This is ignored when not generating SVR4 PIC code. */
12549 if (mips_pic != SVR4_PIC)
12555 /* Add $gp to the register named as an argument. */
12556 reg = tc_get_register (0);
12557 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
12558 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
12559 "d,v,t", reg, reg, mips_gp_register);
12561 demand_empty_rest_of_line ();
12564 /* Handle the .insn pseudo-op. This marks instruction labels in
12565 mips16 mode. This permits the linker to handle them specially,
12566 such as generating jalx instructions when needed. We also make
12567 them odd for the duration of the assembly, in order to generate the
12568 right sort of code. We will make them even in the adjust_symtab
12569 routine, while leaving them marked. This is convenient for the
12570 debugger and the disassembler. The linker knows to make them odd
12575 int ignore ATTRIBUTE_UNUSED;
12577 mips16_mark_labels ();
12579 demand_empty_rest_of_line ();
12582 /* Handle a .stabn directive. We need these in order to mark a label
12583 as being a mips16 text label correctly. Sometimes the compiler
12584 will emit a label, followed by a .stabn, and then switch sections.
12585 If the label and .stabn are in mips16 mode, then the label is
12586 really a mips16 text label. */
12593 mips16_mark_labels ();
12598 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12602 s_mips_weakext (ignore)
12603 int ignore ATTRIBUTE_UNUSED;
12610 name = input_line_pointer;
12611 c = get_symbol_end ();
12612 symbolP = symbol_find_or_make (name);
12613 S_SET_WEAK (symbolP);
12614 *input_line_pointer = c;
12616 SKIP_WHITESPACE ();
12618 if (! is_end_of_line[(unsigned char) *input_line_pointer])
12620 if (S_IS_DEFINED (symbolP))
12622 as_bad ("ignoring attempt to redefine symbol %s",
12623 S_GET_NAME (symbolP));
12624 ignore_rest_of_line ();
12628 if (*input_line_pointer == ',')
12630 ++input_line_pointer;
12631 SKIP_WHITESPACE ();
12635 if (exp.X_op != O_symbol)
12637 as_bad ("bad .weakext directive");
12638 ignore_rest_of_line ();
12641 symbol_set_value_expression (symbolP, &exp);
12644 demand_empty_rest_of_line ();
12647 /* Parse a register string into a number. Called from the ECOFF code
12648 to parse .frame. The argument is non-zero if this is the frame
12649 register, so that we can record it in mips_frame_reg. */
12652 tc_get_register (frame)
12657 SKIP_WHITESPACE ();
12658 if (*input_line_pointer++ != '$')
12660 as_warn (_("expected `$'"));
12663 else if (ISDIGIT (*input_line_pointer))
12665 reg = get_absolute_expression ();
12666 if (reg < 0 || reg >= 32)
12668 as_warn (_("Bad register number"));
12674 if (strncmp (input_line_pointer, "ra", 2) == 0)
12677 input_line_pointer += 2;
12679 else if (strncmp (input_line_pointer, "fp", 2) == 0)
12682 input_line_pointer += 2;
12684 else if (strncmp (input_line_pointer, "sp", 2) == 0)
12687 input_line_pointer += 2;
12689 else if (strncmp (input_line_pointer, "gp", 2) == 0)
12692 input_line_pointer += 2;
12694 else if (strncmp (input_line_pointer, "at", 2) == 0)
12697 input_line_pointer += 2;
12699 else if (strncmp (input_line_pointer, "kt0", 3) == 0)
12702 input_line_pointer += 3;
12704 else if (strncmp (input_line_pointer, "kt1", 3) == 0)
12707 input_line_pointer += 3;
12709 else if (strncmp (input_line_pointer, "zero", 4) == 0)
12712 input_line_pointer += 4;
12716 as_warn (_("Unrecognized register name"));
12718 while (ISALNUM(*input_line_pointer))
12719 input_line_pointer++;
12724 mips_frame_reg = reg != 0 ? reg : SP;
12725 mips_frame_reg_valid = 1;
12726 mips_cprestore_valid = 0;
12732 md_section_align (seg, addr)
12736 int align = bfd_get_section_alignment (stdoutput, seg);
12739 /* We don't need to align ELF sections to the full alignment.
12740 However, Irix 5 may prefer that we align them at least to a 16
12741 byte boundary. We don't bother to align the sections if we are
12742 targeted for an embedded system. */
12743 if (strcmp (TARGET_OS, "elf") == 0)
12749 return ((addr + (1 << align) - 1) & (-1 << align));
12752 /* Utility routine, called from above as well. If called while the
12753 input file is still being read, it's only an approximation. (For
12754 example, a symbol may later become defined which appeared to be
12755 undefined earlier.) */
12758 nopic_need_relax (sym, before_relaxing)
12760 int before_relaxing;
12765 if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0)
12767 const char *symname;
12770 /* Find out whether this symbol can be referenced off the $gp
12771 register. It can be if it is smaller than the -G size or if
12772 it is in the .sdata or .sbss section. Certain symbols can
12773 not be referenced off the $gp, although it appears as though
12775 symname = S_GET_NAME (sym);
12776 if (symname != (const char *) NULL
12777 && (strcmp (symname, "eprol") == 0
12778 || strcmp (symname, "etext") == 0
12779 || strcmp (symname, "_gp") == 0
12780 || strcmp (symname, "edata") == 0
12781 || strcmp (symname, "_fbss") == 0
12782 || strcmp (symname, "_fdata") == 0
12783 || strcmp (symname, "_ftext") == 0
12784 || strcmp (symname, "end") == 0
12785 || strcmp (symname, "_gp_disp") == 0))
12787 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
12788 && !S_IS_EXTERN (sym)
12790 #ifndef NO_ECOFF_DEBUGGING
12791 || (symbol_get_obj (sym)->ecoff_extern_size != 0
12792 && (symbol_get_obj (sym)->ecoff_extern_size
12793 <= g_switch_value))
12795 /* We must defer this decision until after the whole
12796 file has been read, since there might be a .extern
12797 after the first use of this symbol. */
12798 || (before_relaxing
12799 #ifndef NO_ECOFF_DEBUGGING
12800 && symbol_get_obj (sym)->ecoff_extern_size == 0
12802 && S_GET_VALUE (sym) == 0)
12803 || (S_GET_VALUE (sym) != 0
12804 && S_GET_VALUE (sym) <= g_switch_value)))
12808 const char *segname;
12810 segname = segment_name (S_GET_SEGMENT (sym));
12811 assert (strcmp (segname, ".lit8") != 0
12812 && strcmp (segname, ".lit4") != 0);
12813 change = (strcmp (segname, ".sdata") != 0
12814 && strcmp (segname, ".sbss") != 0
12815 && strncmp (segname, ".sdata.", 7) != 0
12816 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
12821 /* We are not optimizing for the $gp register. */
12826 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12829 pic_need_relax (sym, segtype)
12834 bfd_boolean linkonce;
12836 /* Handle the case of a symbol equated to another symbol. */
12837 while (symbol_equated_reloc_p (sym))
12841 /* It's possible to get a loop here in a badly written
12843 n = symbol_get_value_expression (sym)->X_add_symbol;
12849 symsec = S_GET_SEGMENT (sym);
12851 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12853 if (symsec != segtype && ! S_IS_LOCAL (sym))
12855 if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE)
12859 /* The GNU toolchain uses an extension for ELF: a section
12860 beginning with the magic string .gnu.linkonce is a linkonce
12862 if (strncmp (segment_name (symsec), ".gnu.linkonce",
12863 sizeof ".gnu.linkonce" - 1) == 0)
12867 /* This must duplicate the test in adjust_reloc_syms. */
12868 return (symsec != &bfd_und_section
12869 && symsec != &bfd_abs_section
12870 && ! bfd_is_com_section (symsec)
12873 /* A global or weak symbol is treated as external. */
12874 && (OUTPUT_FLAVOR != bfd_target_elf_flavour
12875 || (! S_IS_WEAK (sym)
12876 && (! S_IS_EXTERNAL (sym)
12877 || mips_pic == EMBEDDED_PIC)))
12883 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12884 extended opcode. SEC is the section the frag is in. */
12887 mips16_extended_frag (fragp, sec, stretch)
12893 register const struct mips16_immed_operand *op;
12895 int mintiny, maxtiny;
12899 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
12901 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
12904 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
12905 op = mips16_immed_operands;
12906 while (op->type != type)
12909 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
12914 if (type == '<' || type == '>' || type == '[' || type == ']')
12917 maxtiny = 1 << op->nbits;
12922 maxtiny = (1 << op->nbits) - 1;
12927 mintiny = - (1 << (op->nbits - 1));
12928 maxtiny = (1 << (op->nbits - 1)) - 1;
12931 sym_frag = symbol_get_frag (fragp->fr_symbol);
12932 val = S_GET_VALUE (fragp->fr_symbol);
12933 symsec = S_GET_SEGMENT (fragp->fr_symbol);
12939 /* We won't have the section when we are called from
12940 mips_relax_frag. However, we will always have been called
12941 from md_estimate_size_before_relax first. If this is a
12942 branch to a different section, we mark it as such. If SEC is
12943 NULL, and the frag is not marked, then it must be a branch to
12944 the same section. */
12947 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
12952 /* Must have been called from md_estimate_size_before_relax. */
12955 fragp->fr_subtype =
12956 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12958 /* FIXME: We should support this, and let the linker
12959 catch branches and loads that are out of range. */
12960 as_bad_where (fragp->fr_file, fragp->fr_line,
12961 _("unsupported PC relative reference to different section"));
12965 if (fragp != sym_frag && sym_frag->fr_address == 0)
12966 /* Assume non-extended on the first relaxation pass.
12967 The address we have calculated will be bogus if this is
12968 a forward branch to another frag, as the forward frag
12969 will have fr_address == 0. */
12973 /* In this case, we know for sure that the symbol fragment is in
12974 the same section. If the relax_marker of the symbol fragment
12975 differs from the relax_marker of this fragment, we have not
12976 yet adjusted the symbol fragment fr_address. We want to add
12977 in STRETCH in order to get a better estimate of the address.
12978 This particularly matters because of the shift bits. */
12980 && sym_frag->relax_marker != fragp->relax_marker)
12984 /* Adjust stretch for any alignment frag. Note that if have
12985 been expanding the earlier code, the symbol may be
12986 defined in what appears to be an earlier frag. FIXME:
12987 This doesn't handle the fr_subtype field, which specifies
12988 a maximum number of bytes to skip when doing an
12990 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
12992 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
12995 stretch = - ((- stretch)
12996 & ~ ((1 << (int) f->fr_offset) - 1));
12998 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
13007 addr = fragp->fr_address + fragp->fr_fix;
13009 /* The base address rules are complicated. The base address of
13010 a branch is the following instruction. The base address of a
13011 PC relative load or add is the instruction itself, but if it
13012 is in a delay slot (in which case it can not be extended) use
13013 the address of the instruction whose delay slot it is in. */
13014 if (type == 'p' || type == 'q')
13018 /* If we are currently assuming that this frag should be
13019 extended, then, the current address is two bytes
13021 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13024 /* Ignore the low bit in the target, since it will be set
13025 for a text label. */
13026 if ((val & 1) != 0)
13029 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
13031 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
13034 val -= addr & ~ ((1 << op->shift) - 1);
13036 /* Branch offsets have an implicit 0 in the lowest bit. */
13037 if (type == 'p' || type == 'q')
13040 /* If any of the shifted bits are set, we must use an extended
13041 opcode. If the address depends on the size of this
13042 instruction, this can lead to a loop, so we arrange to always
13043 use an extended opcode. We only check this when we are in
13044 the main relaxation loop, when SEC is NULL. */
13045 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
13047 fragp->fr_subtype =
13048 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
13052 /* If we are about to mark a frag as extended because the value
13053 is precisely maxtiny + 1, then there is a chance of an
13054 infinite loop as in the following code:
13059 In this case when the la is extended, foo is 0x3fc bytes
13060 away, so the la can be shrunk, but then foo is 0x400 away, so
13061 the la must be extended. To avoid this loop, we mark the
13062 frag as extended if it was small, and is about to become
13063 extended with a value of maxtiny + 1. */
13064 if (val == ((maxtiny + 1) << op->shift)
13065 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
13068 fragp->fr_subtype =
13069 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
13073 else if (symsec != absolute_section && sec != NULL)
13074 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
13076 if ((val & ((1 << op->shift) - 1)) != 0
13077 || val < (mintiny << op->shift)
13078 || val > (maxtiny << op->shift))
13084 /* Compute the length of a branch sequence, and adjust the
13085 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
13086 worst-case length is computed, with UPDATE being used to indicate
13087 whether an unconditional (-1), branch-likely (+1) or regular (0)
13088 branch is to be computed. */
13090 relaxed_branch_length (fragp, sec, update)
13095 bfd_boolean toofar;
13099 && S_IS_DEFINED (fragp->fr_symbol)
13100 && sec == S_GET_SEGMENT (fragp->fr_symbol))
13105 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
13107 addr = fragp->fr_address + fragp->fr_fix + 4;
13111 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
13114 /* If the symbol is not defined or it's in a different segment,
13115 assume the user knows what's going on and emit a short
13121 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
13123 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype),
13124 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
13125 RELAX_BRANCH_LINK (fragp->fr_subtype),
13131 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
13134 if (mips_pic != NO_PIC)
13136 /* Additional space for PIC loading of target address. */
13138 if (mips_opts.isa == ISA_MIPS1)
13139 /* Additional space for $at-stabilizing nop. */
13143 /* If branch is conditional. */
13144 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
13151 /* Estimate the size of a frag before relaxing. Unless this is the
13152 mips16, we are not really relaxing here, and the final size is
13153 encoded in the subtype information. For the mips16, we have to
13154 decide whether we are using an extended opcode or not. */
13157 md_estimate_size_before_relax (fragp, segtype)
13163 if (RELAX_BRANCH_P (fragp->fr_subtype))
13166 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
13168 return fragp->fr_var;
13171 if (RELAX_MIPS16_P (fragp->fr_subtype))
13172 /* We don't want to modify the EXTENDED bit here; it might get us
13173 into infinite loops. We change it only in mips_relax_frag(). */
13174 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
13176 if (mips_pic == NO_PIC)
13177 change = nopic_need_relax (fragp->fr_symbol, 0);
13178 else if (mips_pic == SVR4_PIC)
13179 change = pic_need_relax (fragp->fr_symbol, segtype);
13185 /* Record the offset to the first reloc in the fr_opcode field.
13186 This lets md_convert_frag and tc_gen_reloc know that the code
13187 must be expanded. */
13188 fragp->fr_opcode = (fragp->fr_literal
13190 - RELAX_OLD (fragp->fr_subtype)
13191 + RELAX_RELOC1 (fragp->fr_subtype));
13192 /* FIXME: This really needs as_warn_where. */
13193 if (RELAX_WARN (fragp->fr_subtype))
13194 as_warn (_("AT used after \".set noat\" or macro used after "
13195 "\".set nomacro\""));
13197 return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype);
13203 /* This is called to see whether a reloc against a defined symbol
13204 should be converted into a reloc against a section. Don't adjust
13205 MIPS16 jump relocations, so we don't have to worry about the format
13206 of the offset in the .o file. Don't adjust relocations against
13207 mips16 symbols, so that the linker can find them if it needs to set
13211 mips_fix_adjustable (fixp)
13214 if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
13217 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
13218 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
13221 if (fixp->fx_addsy == NULL)
13225 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
13226 && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
13227 && fixp->fx_subsy == NULL)
13234 /* Translate internal representation of relocation info to BFD target
13238 tc_gen_reloc (section, fixp)
13239 asection *section ATTRIBUTE_UNUSED;
13242 static arelent *retval[4];
13244 bfd_reloc_code_real_type code;
13246 reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent));
13249 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
13250 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
13251 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
13253 if (mips_pic == EMBEDDED_PIC
13254 && SWITCH_TABLE (fixp))
13256 /* For a switch table entry we use a special reloc. The addend
13257 is actually the difference between the reloc address and the
13259 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
13260 if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour)
13261 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
13262 fixp->fx_r_type = BFD_RELOC_GPREL32;
13264 else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16)
13266 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
13267 reloc->addend = fixp->fx_addnumber;
13270 /* We use a special addend for an internal RELLO reloc. */
13271 if (symbol_section_p (fixp->fx_addsy))
13272 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
13274 reloc->addend = fixp->fx_addnumber + reloc->address;
13277 else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
13279 assert (fixp->fx_next != NULL
13280 && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16);
13282 /* The reloc is relative to the RELLO; adjust the addend
13284 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
13285 reloc->addend = fixp->fx_next->fx_addnumber;
13288 /* We use a special addend for an internal RELHI reloc. */
13289 if (symbol_section_p (fixp->fx_addsy))
13290 reloc->addend = (fixp->fx_next->fx_frag->fr_address
13291 + fixp->fx_next->fx_where
13292 - S_GET_VALUE (fixp->fx_subsy));
13294 reloc->addend = (fixp->fx_addnumber
13295 + fixp->fx_next->fx_frag->fr_address
13296 + fixp->fx_next->fx_where);
13299 else if (fixp->fx_pcrel == 0 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
13300 reloc->addend = fixp->fx_addnumber;
13303 if (OUTPUT_FLAVOR != bfd_target_aout_flavour)
13304 /* A gruesome hack which is a result of the gruesome gas reloc
13306 reloc->addend = reloc->address;
13308 reloc->addend = -reloc->address;
13311 /* If this is a variant frag, we may need to adjust the existing
13312 reloc and generate a new one. */
13313 if (fixp->fx_frag->fr_opcode != NULL
13314 && ((fixp->fx_r_type == BFD_RELOC_GPREL16
13316 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
13317 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16
13318 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
13319 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16
13320 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
13321 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)
13326 assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype));
13328 /* If this is not the last reloc in this frag, then we have two
13329 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
13330 CALL_HI16/CALL_LO16, both of which are being replaced. Let
13331 the second one handle all of them. */
13332 if (fixp->fx_next != NULL
13333 && fixp->fx_frag == fixp->fx_next->fx_frag)
13335 assert ((fixp->fx_r_type == BFD_RELOC_GPREL16
13336 && fixp->fx_next->fx_r_type == BFD_RELOC_GPREL16)
13337 || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
13338 && (fixp->fx_next->fx_r_type
13339 == BFD_RELOC_MIPS_GOT_LO16))
13340 || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
13341 && (fixp->fx_next->fx_r_type
13342 == BFD_RELOC_MIPS_CALL_LO16)));
13347 fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal;
13348 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
13349 reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent));
13351 reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
13352 *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
13353 reloc2->address = (reloc->address
13354 + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype)
13355 - RELAX_RELOC1 (fixp->fx_frag->fr_subtype)));
13356 reloc2->addend = fixp->fx_addnumber;
13357 reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16);
13358 assert (reloc2->howto != NULL);
13360 if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype))
13364 reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent));
13367 reloc3->address += 4;
13370 if (mips_pic == NO_PIC)
13372 assert (fixp->fx_r_type == BFD_RELOC_GPREL16);
13373 fixp->fx_r_type = BFD_RELOC_HI16_S;
13375 else if (mips_pic == SVR4_PIC)
13377 switch (fixp->fx_r_type)
13381 case BFD_RELOC_MIPS_GOT16:
13383 case BFD_RELOC_MIPS_GOT_LO16:
13384 case BFD_RELOC_MIPS_CALL_LO16:
13385 fixp->fx_r_type = BFD_RELOC_MIPS_GOT16;
13387 case BFD_RELOC_MIPS_CALL16:
13390 /* BFD_RELOC_MIPS_GOT16;*/
13391 fixp->fx_r_type = BFD_RELOC_MIPS_GOT_PAGE;
13392 reloc2->howto = bfd_reloc_type_lookup
13393 (stdoutput, BFD_RELOC_MIPS_GOT_OFST);
13396 fixp->fx_r_type = BFD_RELOC_MIPS_GOT16;
13403 /* newabi uses R_MIPS_GOT_DISP for local symbols */
13404 if (HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16)
13406 fixp->fx_r_type = BFD_RELOC_MIPS_GOT_DISP;
13411 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
13412 entry to be used in the relocation's section offset. */
13413 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
13415 reloc->address = reloc->addend;
13419 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
13420 fixup_segment converted a non-PC relative reloc into a PC
13421 relative reloc. In such a case, we need to convert the reloc
13423 code = fixp->fx_r_type;
13424 if (fixp->fx_pcrel)
13429 code = BFD_RELOC_8_PCREL;
13432 code = BFD_RELOC_16_PCREL;
13435 code = BFD_RELOC_32_PCREL;
13438 code = BFD_RELOC_64_PCREL;
13440 case BFD_RELOC_8_PCREL:
13441 case BFD_RELOC_16_PCREL:
13442 case BFD_RELOC_32_PCREL:
13443 case BFD_RELOC_64_PCREL:
13444 case BFD_RELOC_16_PCREL_S2:
13445 case BFD_RELOC_PCREL_HI16_S:
13446 case BFD_RELOC_PCREL_LO16:
13449 as_bad_where (fixp->fx_file, fixp->fx_line,
13450 _("Cannot make %s relocation PC relative"),
13451 bfd_get_reloc_code_name (code));
13456 /* md_apply_fix3 has a double-subtraction hack to get
13457 bfd_install_relocation to behave nicely. GPREL relocations are
13458 handled correctly without this hack, so undo it here. We can't
13459 stop md_apply_fix3 from subtracting twice in the first place since
13460 the fake addend is required for variant frags above. */
13461 if (fixp->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour
13462 && (code == BFD_RELOC_GPREL16 || code == BFD_RELOC_MIPS16_GPREL)
13463 && reloc->addend != 0
13464 && mips_need_elf_addend_fixup (fixp))
13465 reloc->addend += S_GET_VALUE (fixp->fx_addsy);
13468 /* To support a PC relative reloc when generating embedded PIC code
13469 for ECOFF, we use a Cygnus extension. We check for that here to
13470 make sure that we don't let such a reloc escape normally. */
13471 if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
13472 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
13473 && code == BFD_RELOC_16_PCREL_S2
13474 && mips_pic != EMBEDDED_PIC)
13475 reloc->howto = NULL;
13477 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
13479 if (reloc->howto == NULL)
13481 as_bad_where (fixp->fx_file, fixp->fx_line,
13482 _("Can not represent %s relocation in this object file format"),
13483 bfd_get_reloc_code_name (code));
13490 /* Relax a machine dependent frag. This returns the amount by which
13491 the current size of the frag should change. */
13494 mips_relax_frag (sec, fragp, stretch)
13499 if (RELAX_BRANCH_P (fragp->fr_subtype))
13501 offsetT old_var = fragp->fr_var;
13503 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
13505 return fragp->fr_var - old_var;
13508 if (! RELAX_MIPS16_P (fragp->fr_subtype))
13511 if (mips16_extended_frag (fragp, NULL, stretch))
13513 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13515 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
13520 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13522 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
13529 /* Convert a machine dependent frag. */
13532 md_convert_frag (abfd, asec, fragp)
13533 bfd *abfd ATTRIBUTE_UNUSED;
13540 if (RELAX_BRANCH_P (fragp->fr_subtype))
13543 unsigned long insn;
13547 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
13549 if (target_big_endian)
13550 insn = bfd_getb32 (buf);
13552 insn = bfd_getl32 (buf);
13554 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
13556 /* We generate a fixup instead of applying it right now
13557 because, if there are linker relaxations, we're going to
13558 need the relocations. */
13559 exp.X_op = O_symbol;
13560 exp.X_add_symbol = fragp->fr_symbol;
13561 exp.X_add_number = fragp->fr_offset;
13563 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13565 BFD_RELOC_16_PCREL_S2);
13566 fixp->fx_file = fragp->fr_file;
13567 fixp->fx_line = fragp->fr_line;
13569 md_number_to_chars ((char *)buf, insn, 4);
13576 as_warn_where (fragp->fr_file, fragp->fr_line,
13577 _("relaxed out-of-range branch into a jump"));
13579 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
13582 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13584 /* Reverse the branch. */
13585 switch ((insn >> 28) & 0xf)
13588 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
13589 have the condition reversed by tweaking a single
13590 bit, and their opcodes all have 0x4???????. */
13591 assert ((insn & 0xf1000000) == 0x41000000);
13592 insn ^= 0x00010000;
13596 /* bltz 0x04000000 bgez 0x04010000
13597 bltzal 0x04100000 bgezal 0x04110000 */
13598 assert ((insn & 0xfc0e0000) == 0x04000000);
13599 insn ^= 0x00010000;
13603 /* beq 0x10000000 bne 0x14000000
13604 blez 0x18000000 bgtz 0x1c000000 */
13605 insn ^= 0x04000000;
13613 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13615 /* Clear the and-link bit. */
13616 assert ((insn & 0xfc1c0000) == 0x04100000);
13618 /* bltzal 0x04100000 bgezal 0x04110000
13619 bltzall 0x04120000 bgezall 0x04130000 */
13620 insn &= ~0x00100000;
13623 /* Branch over the branch (if the branch was likely) or the
13624 full jump (not likely case). Compute the offset from the
13625 current instruction to branch to. */
13626 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13630 /* How many bytes in instructions we've already emitted? */
13631 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
13632 /* How many bytes in instructions from here to the end? */
13633 i = fragp->fr_var - i;
13635 /* Convert to instruction count. */
13637 /* Branch counts from the next instruction. */
13640 /* Branch over the jump. */
13641 md_number_to_chars ((char *)buf, insn, 4);
13645 md_number_to_chars ((char*)buf, 0, 4);
13648 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13650 /* beql $0, $0, 2f */
13652 /* Compute the PC offset from the current instruction to
13653 the end of the variable frag. */
13654 /* How many bytes in instructions we've already emitted? */
13655 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
13656 /* How many bytes in instructions from here to the end? */
13657 i = fragp->fr_var - i;
13658 /* Convert to instruction count. */
13660 /* Don't decrement i, because we want to branch over the
13664 md_number_to_chars ((char *)buf, insn, 4);
13667 md_number_to_chars ((char *)buf, 0, 4);
13672 if (mips_pic == NO_PIC)
13675 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
13676 ? 0x0c000000 : 0x08000000);
13677 exp.X_op = O_symbol;
13678 exp.X_add_symbol = fragp->fr_symbol;
13679 exp.X_add_number = fragp->fr_offset;
13681 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13682 4, &exp, 0, BFD_RELOC_MIPS_JMP);
13683 fixp->fx_file = fragp->fr_file;
13684 fixp->fx_line = fragp->fr_line;
13686 md_number_to_chars ((char*)buf, insn, 4);
13691 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13692 insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000;
13693 exp.X_op = O_symbol;
13694 exp.X_add_symbol = fragp->fr_symbol;
13695 exp.X_add_number = fragp->fr_offset;
13697 if (fragp->fr_offset)
13699 exp.X_add_symbol = make_expr_symbol (&exp);
13700 exp.X_add_number = 0;
13703 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13704 4, &exp, 0, BFD_RELOC_MIPS_GOT16);
13705 fixp->fx_file = fragp->fr_file;
13706 fixp->fx_line = fragp->fr_line;
13708 md_number_to_chars ((char*)buf, insn, 4);
13711 if (mips_opts.isa == ISA_MIPS1)
13714 md_number_to_chars ((char*)buf, 0, 4);
13718 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13719 insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000;
13721 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13722 4, &exp, 0, BFD_RELOC_LO16);
13723 fixp->fx_file = fragp->fr_file;
13724 fixp->fx_line = fragp->fr_line;
13726 md_number_to_chars ((char*)buf, insn, 4);
13730 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13735 md_number_to_chars ((char*)buf, insn, 4);
13740 assert (buf == (bfd_byte *)fragp->fr_literal
13741 + fragp->fr_fix + fragp->fr_var);
13743 fragp->fr_fix += fragp->fr_var;
13748 if (RELAX_MIPS16_P (fragp->fr_subtype))
13751 register const struct mips16_immed_operand *op;
13752 bfd_boolean small, ext;
13755 unsigned long insn;
13756 bfd_boolean use_extend;
13757 unsigned short extend;
13759 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
13760 op = mips16_immed_operands;
13761 while (op->type != type)
13764 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13775 resolve_symbol_value (fragp->fr_symbol);
13776 val = S_GET_VALUE (fragp->fr_symbol);
13781 addr = fragp->fr_address + fragp->fr_fix;
13783 /* The rules for the base address of a PC relative reloc are
13784 complicated; see mips16_extended_frag. */
13785 if (type == 'p' || type == 'q')
13790 /* Ignore the low bit in the target, since it will be
13791 set for a text label. */
13792 if ((val & 1) != 0)
13795 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
13797 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
13800 addr &= ~ (addressT) ((1 << op->shift) - 1);
13803 /* Make sure the section winds up with the alignment we have
13806 record_alignment (asec, op->shift);
13810 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
13811 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
13812 as_warn_where (fragp->fr_file, fragp->fr_line,
13813 _("extended instruction in delay slot"));
13815 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
13817 if (target_big_endian)
13818 insn = bfd_getb16 (buf);
13820 insn = bfd_getl16 (buf);
13822 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
13823 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
13824 small, ext, &insn, &use_extend, &extend);
13828 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
13829 fragp->fr_fix += 2;
13833 md_number_to_chars ((char *) buf, insn, 2);
13834 fragp->fr_fix += 2;
13839 if (fragp->fr_opcode == NULL)
13842 old = RELAX_OLD (fragp->fr_subtype);
13843 new = RELAX_NEW (fragp->fr_subtype);
13844 fixptr = fragp->fr_literal + fragp->fr_fix;
13847 memcpy (fixptr - old, fixptr, new);
13849 fragp->fr_fix += new - old;
13855 /* This function is called after the relocs have been generated.
13856 We've been storing mips16 text labels as odd. Here we convert them
13857 back to even for the convenience of the debugger. */
13860 mips_frob_file_after_relocs ()
13863 unsigned int count, i;
13865 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
13868 syms = bfd_get_outsymbols (stdoutput);
13869 count = bfd_get_symcount (stdoutput);
13870 for (i = 0; i < count; i++, syms++)
13872 if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16
13873 && ((*syms)->value & 1) != 0)
13875 (*syms)->value &= ~1;
13876 /* If the symbol has an odd size, it was probably computed
13877 incorrectly, so adjust that as well. */
13878 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
13879 ++elf_symbol (*syms)->internal_elf_sym.st_size;
13886 /* This function is called whenever a label is defined. It is used
13887 when handling branch delays; if a branch has a label, we assume we
13888 can not move it. */
13891 mips_define_label (sym)
13894 struct insn_label_list *l;
13896 if (free_insn_labels == NULL)
13897 l = (struct insn_label_list *) xmalloc (sizeof *l);
13900 l = free_insn_labels;
13901 free_insn_labels = l->next;
13905 l->next = insn_labels;
13909 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13911 /* Some special processing for a MIPS ELF file. */
13914 mips_elf_final_processing ()
13916 /* Write out the register information. */
13917 if (mips_abi != N64_ABI)
13921 s.ri_gprmask = mips_gprmask;
13922 s.ri_cprmask[0] = mips_cprmask[0];
13923 s.ri_cprmask[1] = mips_cprmask[1];
13924 s.ri_cprmask[2] = mips_cprmask[2];
13925 s.ri_cprmask[3] = mips_cprmask[3];
13926 /* The gp_value field is set by the MIPS ELF backend. */
13928 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
13929 ((Elf32_External_RegInfo *)
13930 mips_regmask_frag));
13934 Elf64_Internal_RegInfo s;
13936 s.ri_gprmask = mips_gprmask;
13938 s.ri_cprmask[0] = mips_cprmask[0];
13939 s.ri_cprmask[1] = mips_cprmask[1];
13940 s.ri_cprmask[2] = mips_cprmask[2];
13941 s.ri_cprmask[3] = mips_cprmask[3];
13942 /* The gp_value field is set by the MIPS ELF backend. */
13944 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
13945 ((Elf64_External_RegInfo *)
13946 mips_regmask_frag));
13949 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13950 sort of BFD interface for this. */
13951 if (mips_any_noreorder)
13952 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
13953 if (mips_pic != NO_PIC)
13954 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
13956 /* Set MIPS ELF flags for ASEs. */
13957 if (file_ase_mips16)
13958 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
13959 #if 0 /* XXX FIXME */
13960 if (file_ase_mips3d)
13961 elf_elfheader (stdoutput)->e_flags |= ???;
13964 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
13966 /* Set the MIPS ELF ABI flags. */
13967 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
13968 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
13969 else if (mips_abi == O64_ABI)
13970 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
13971 else if (mips_abi == EABI_ABI)
13973 if (!file_mips_gp32)
13974 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
13976 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
13978 else if (mips_abi == N32_ABI)
13979 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
13981 /* Nothing to do for N64_ABI. */
13983 if (mips_32bitmode)
13984 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
13987 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13989 typedef struct proc {
13991 unsigned long reg_mask;
13992 unsigned long reg_offset;
13993 unsigned long fpreg_mask;
13994 unsigned long fpreg_offset;
13995 unsigned long frame_offset;
13996 unsigned long frame_reg;
13997 unsigned long pc_reg;
14000 static procS cur_proc;
14001 static procS *cur_proc_ptr;
14002 static int numprocs;
14004 /* Fill in an rs_align_code fragment. */
14007 mips_handle_align (fragp)
14010 if (fragp->fr_type != rs_align_code)
14013 if (mips_opts.mips16)
14015 static const unsigned char be_nop[] = { 0x65, 0x00 };
14016 static const unsigned char le_nop[] = { 0x00, 0x65 };
14021 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
14022 p = fragp->fr_literal + fragp->fr_fix;
14030 memcpy (p, (target_big_endian ? be_nop : le_nop), 2);
14034 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
14045 /* check for premature end, nesting errors, etc */
14047 as_warn (_("missing .end at end of assembly"));
14056 if (*input_line_pointer == '-')
14058 ++input_line_pointer;
14061 if (!ISDIGIT (*input_line_pointer))
14062 as_bad (_("expected simple number"));
14063 if (input_line_pointer[0] == '0')
14065 if (input_line_pointer[1] == 'x')
14067 input_line_pointer += 2;
14068 while (ISXDIGIT (*input_line_pointer))
14071 val |= hex_value (*input_line_pointer++);
14073 return negative ? -val : val;
14077 ++input_line_pointer;
14078 while (ISDIGIT (*input_line_pointer))
14081 val |= *input_line_pointer++ - '0';
14083 return negative ? -val : val;
14086 if (!ISDIGIT (*input_line_pointer))
14088 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
14089 *input_line_pointer, *input_line_pointer);
14090 as_warn (_("invalid number"));
14093 while (ISDIGIT (*input_line_pointer))
14096 val += *input_line_pointer++ - '0';
14098 return negative ? -val : val;
14101 /* The .file directive; just like the usual .file directive, but there
14102 is an initial number which is the ECOFF file index. In the non-ECOFF
14103 case .file implies DWARF-2. */
14107 int x ATTRIBUTE_UNUSED;
14109 static int first_file_directive = 0;
14111 if (ECOFF_DEBUGGING)
14120 filename = dwarf2_directive_file (0);
14122 /* Versions of GCC up to 3.1 start files with a ".file"
14123 directive even for stabs output. Make sure that this
14124 ".file" is handled. Note that you need a version of GCC
14125 after 3.1 in order to support DWARF-2 on MIPS. */
14126 if (filename != NULL && ! first_file_directive)
14128 (void) new_logical_line (filename, -1);
14129 s_app_file_string (filename);
14131 first_file_directive = 1;
14135 /* The .loc directive, implying DWARF-2. */
14139 int x ATTRIBUTE_UNUSED;
14141 if (!ECOFF_DEBUGGING)
14142 dwarf2_directive_loc (0);
14145 /* The .end directive. */
14149 int x ATTRIBUTE_UNUSED;
14153 /* Following functions need their own .frame and .cprestore directives. */
14154 mips_frame_reg_valid = 0;
14155 mips_cprestore_valid = 0;
14157 if (!is_end_of_line[(unsigned char) *input_line_pointer])
14160 demand_empty_rest_of_line ();
14165 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
14166 as_warn (_(".end not in text section"));
14170 as_warn (_(".end directive without a preceding .ent directive."));
14171 demand_empty_rest_of_line ();
14177 assert (S_GET_NAME (p));
14178 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym)))
14179 as_warn (_(".end symbol does not match .ent symbol."));
14181 if (debug_type == DEBUG_STABS)
14182 stabs_generate_asm_endfunc (S_GET_NAME (p),
14186 as_warn (_(".end directive missing or unknown symbol"));
14189 /* Generate a .pdr section. */
14190 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
14192 segT saved_seg = now_seg;
14193 subsegT saved_subseg = now_subseg;
14198 dot = frag_now_fix ();
14200 #ifdef md_flush_pending_output
14201 md_flush_pending_output ();
14205 subseg_set (pdr_seg, 0);
14207 /* Write the symbol. */
14208 exp.X_op = O_symbol;
14209 exp.X_add_symbol = p;
14210 exp.X_add_number = 0;
14211 emit_expr (&exp, 4);
14213 fragp = frag_more (7 * 4);
14215 md_number_to_chars (fragp, (valueT) cur_proc_ptr->reg_mask, 4);
14216 md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4);
14217 md_number_to_chars (fragp + 8, (valueT) cur_proc_ptr->fpreg_mask, 4);
14218 md_number_to_chars (fragp + 12, (valueT) cur_proc_ptr->fpreg_offset, 4);
14219 md_number_to_chars (fragp + 16, (valueT) cur_proc_ptr->frame_offset, 4);
14220 md_number_to_chars (fragp + 20, (valueT) cur_proc_ptr->frame_reg, 4);
14221 md_number_to_chars (fragp + 24, (valueT) cur_proc_ptr->pc_reg, 4);
14223 subseg_set (saved_seg, saved_subseg);
14225 #endif /* OBJ_ELF */
14227 cur_proc_ptr = NULL;
14230 /* The .aent and .ent directives. */
14238 symbolP = get_symbol ();
14239 if (*input_line_pointer == ',')
14240 ++input_line_pointer;
14241 SKIP_WHITESPACE ();
14242 if (ISDIGIT (*input_line_pointer)
14243 || *input_line_pointer == '-')
14246 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
14247 as_warn (_(".ent or .aent not in text section."));
14249 if (!aent && cur_proc_ptr)
14250 as_warn (_("missing .end"));
14254 /* This function needs its own .frame and .cprestore directives. */
14255 mips_frame_reg_valid = 0;
14256 mips_cprestore_valid = 0;
14258 cur_proc_ptr = &cur_proc;
14259 memset (cur_proc_ptr, '\0', sizeof (procS));
14261 cur_proc_ptr->isym = symbolP;
14263 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
14267 if (debug_type == DEBUG_STABS)
14268 stabs_generate_asm_func (S_GET_NAME (symbolP),
14269 S_GET_NAME (symbolP));
14272 demand_empty_rest_of_line ();
14275 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
14276 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
14277 s_mips_frame is used so that we can set the PDR information correctly.
14278 We can't use the ecoff routines because they make reference to the ecoff
14279 symbol table (in the mdebug section). */
14282 s_mips_frame (ignore)
14283 int ignore ATTRIBUTE_UNUSED;
14286 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
14290 if (cur_proc_ptr == (procS *) NULL)
14292 as_warn (_(".frame outside of .ent"));
14293 demand_empty_rest_of_line ();
14297 cur_proc_ptr->frame_reg = tc_get_register (1);
14299 SKIP_WHITESPACE ();
14300 if (*input_line_pointer++ != ','
14301 || get_absolute_expression_and_terminator (&val) != ',')
14303 as_warn (_("Bad .frame directive"));
14304 --input_line_pointer;
14305 demand_empty_rest_of_line ();
14309 cur_proc_ptr->frame_offset = val;
14310 cur_proc_ptr->pc_reg = tc_get_register (0);
14312 demand_empty_rest_of_line ();
14315 #endif /* OBJ_ELF */
14319 /* The .fmask and .mask directives. If the mdebug section is present
14320 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
14321 embedded targets, s_mips_mask is used so that we can set the PDR
14322 information correctly. We can't use the ecoff routines because they
14323 make reference to the ecoff symbol table (in the mdebug section). */
14326 s_mips_mask (reg_type)
14330 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
14334 if (cur_proc_ptr == (procS *) NULL)
14336 as_warn (_(".mask/.fmask outside of .ent"));
14337 demand_empty_rest_of_line ();
14341 if (get_absolute_expression_and_terminator (&mask) != ',')
14343 as_warn (_("Bad .mask/.fmask directive"));
14344 --input_line_pointer;
14345 demand_empty_rest_of_line ();
14349 off = get_absolute_expression ();
14351 if (reg_type == 'F')
14353 cur_proc_ptr->fpreg_mask = mask;
14354 cur_proc_ptr->fpreg_offset = off;
14358 cur_proc_ptr->reg_mask = mask;
14359 cur_proc_ptr->reg_offset = off;
14362 demand_empty_rest_of_line ();
14365 #endif /* OBJ_ELF */
14366 s_ignore (reg_type);
14369 /* The .loc directive. */
14380 assert (now_seg == text_section);
14382 lineno = get_number ();
14383 addroff = frag_now_fix ();
14385 symbolP = symbol_new ("", N_SLINE, addroff, frag_now);
14386 S_SET_TYPE (symbolP, N_SLINE);
14387 S_SET_OTHER (symbolP, 0);
14388 S_SET_DESC (symbolP, lineno);
14389 symbolP->sy_segment = now_seg;
14393 /* A table describing all the processors gas knows about. Names are
14394 matched in the order listed.
14396 To ease comparison, please keep this table in the same order as
14397 gcc's mips_cpu_info_table[]. */
14398 static const struct mips_cpu_info mips_cpu_info_table[] =
14400 /* Entries for generic ISAs */
14401 { "mips1", 1, ISA_MIPS1, CPU_R3000 },
14402 { "mips2", 1, ISA_MIPS2, CPU_R6000 },
14403 { "mips3", 1, ISA_MIPS3, CPU_R4000 },
14404 { "mips4", 1, ISA_MIPS4, CPU_R8000 },
14405 { "mips5", 1, ISA_MIPS5, CPU_MIPS5 },
14406 { "mips32", 1, ISA_MIPS32, CPU_MIPS32 },
14407 { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 },
14408 { "mips64", 1, ISA_MIPS64, CPU_MIPS64 },
14411 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
14412 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
14413 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
14416 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
14419 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
14420 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
14421 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
14422 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
14423 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
14424 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
14425 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
14426 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
14427 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
14428 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
14429 { "orion", 0, ISA_MIPS3, CPU_R4600 },
14430 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
14433 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
14434 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
14435 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
14436 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
14437 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
14438 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
14439 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
14440 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
14441 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
14442 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
14443 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
14444 { "r7000", 0, ISA_MIPS4, CPU_R5000 },
14447 { "4kc", 0, ISA_MIPS32, CPU_MIPS32, },
14448 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
14449 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
14452 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
14453 { "20kc", 0, ISA_MIPS64, CPU_MIPS64 },
14455 /* Broadcom SB-1 CPU core */
14456 { "sb1", 0, ISA_MIPS64, CPU_SB1 },
14463 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14464 with a final "000" replaced by "k". Ignore case.
14466 Note: this function is shared between GCC and GAS. */
14469 mips_strict_matching_cpu_name_p (canonical, given)
14470 const char *canonical, *given;
14472 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
14473 given++, canonical++;
14475 return ((*given == 0 && *canonical == 0)
14476 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
14480 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14481 CPU name. We've traditionally allowed a lot of variation here.
14483 Note: this function is shared between GCC and GAS. */
14486 mips_matching_cpu_name_p (canonical, given)
14487 const char *canonical, *given;
14489 /* First see if the name matches exactly, or with a final "000"
14490 turned into "k". */
14491 if (mips_strict_matching_cpu_name_p (canonical, given))
14494 /* If not, try comparing based on numerical designation alone.
14495 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14496 if (TOLOWER (*given) == 'r')
14498 if (!ISDIGIT (*given))
14501 /* Skip over some well-known prefixes in the canonical name,
14502 hoping to find a number there too. */
14503 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
14505 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
14507 else if (TOLOWER (canonical[0]) == 'r')
14510 return mips_strict_matching_cpu_name_p (canonical, given);
14514 /* Parse an option that takes the name of a processor as its argument.
14515 OPTION is the name of the option and CPU_STRING is the argument.
14516 Return the corresponding processor enumeration if the CPU_STRING is
14517 recognized, otherwise report an error and return null.
14519 A similar function exists in GCC. */
14521 static const struct mips_cpu_info *
14522 mips_parse_cpu (option, cpu_string)
14523 const char *option, *cpu_string;
14525 const struct mips_cpu_info *p;
14527 /* 'from-abi' selects the most compatible architecture for the given
14528 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14529 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14530 version. Look first at the -mgp options, if given, otherwise base
14531 the choice on MIPS_DEFAULT_64BIT.
14533 Treat NO_ABI like the EABIs. One reason to do this is that the
14534 plain 'mips' and 'mips64' configs have 'from-abi' as their default
14535 architecture. This code picks MIPS I for 'mips' and MIPS III for
14536 'mips64', just as we did in the days before 'from-abi'. */
14537 if (strcasecmp (cpu_string, "from-abi") == 0)
14539 if (ABI_NEEDS_32BIT_REGS (mips_abi))
14540 return mips_cpu_info_from_isa (ISA_MIPS1);
14542 if (ABI_NEEDS_64BIT_REGS (mips_abi))
14543 return mips_cpu_info_from_isa (ISA_MIPS3);
14545 if (file_mips_gp32 >= 0)
14546 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
14548 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
14553 /* 'default' has traditionally been a no-op. Probably not very useful. */
14554 if (strcasecmp (cpu_string, "default") == 0)
14557 for (p = mips_cpu_info_table; p->name != 0; p++)
14558 if (mips_matching_cpu_name_p (p->name, cpu_string))
14561 as_bad ("Bad value (%s) for %s", cpu_string, option);
14565 /* Return the canonical processor information for ISA (a member of the
14566 ISA_MIPS* enumeration). */
14568 static const struct mips_cpu_info *
14569 mips_cpu_info_from_isa (isa)
14574 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14575 if (mips_cpu_info_table[i].is_isa
14576 && isa == mips_cpu_info_table[i].isa)
14577 return (&mips_cpu_info_table[i]);
14583 show (stream, string, col_p, first_p)
14585 const char *string;
14591 fprintf (stream, "%24s", "");
14596 fprintf (stream, ", ");
14600 if (*col_p + strlen (string) > 72)
14602 fprintf (stream, "\n%24s", "");
14606 fprintf (stream, "%s", string);
14607 *col_p += strlen (string);
14613 md_show_usage (stream)
14619 fprintf (stream, _("\
14621 -membedded-pic generate embedded position independent code\n\
14622 -EB generate big endian output\n\
14623 -EL generate little endian output\n\
14624 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14625 -G NUM allow referencing objects up to NUM bytes\n\
14626 implicitly with the gp register [default 8]\n"));
14627 fprintf (stream, _("\
14628 -mips1 generate MIPS ISA I instructions\n\
14629 -mips2 generate MIPS ISA II instructions\n\
14630 -mips3 generate MIPS ISA III instructions\n\
14631 -mips4 generate MIPS ISA IV instructions\n\
14632 -mips5 generate MIPS ISA V instructions\n\
14633 -mips32 generate MIPS32 ISA instructions\n\
14634 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14635 -mips64 generate MIPS64 ISA instructions\n\
14636 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14640 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14641 show (stream, mips_cpu_info_table[i].name, &column, &first);
14642 show (stream, "from-abi", &column, &first);
14643 fputc ('\n', stream);
14645 fprintf (stream, _("\
14646 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14647 -no-mCPU don't generate code specific to CPU.\n\
14648 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14652 show (stream, "3900", &column, &first);
14653 show (stream, "4010", &column, &first);
14654 show (stream, "4100", &column, &first);
14655 show (stream, "4650", &column, &first);
14656 fputc ('\n', stream);
14658 fprintf (stream, _("\
14659 -mips16 generate mips16 instructions\n\
14660 -no-mips16 do not generate mips16 instructions\n"));
14661 fprintf (stream, _("\
14662 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14663 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14664 -O0 remove unneeded NOPs, do not swap branches\n\
14665 -O remove unneeded NOPs and swap branches\n\
14666 -n warn about NOPs generated from macros\n\
14667 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14668 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14669 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14671 fprintf (stream, _("\
14672 -KPIC, -call_shared generate SVR4 position independent code\n\
14673 -non_shared do not generate position independent code\n\
14674 -xgot assume a 32 bit GOT\n\
14675 -mabi=ABI create ABI conformant object file for:\n"));
14679 show (stream, "32", &column, &first);
14680 show (stream, "o64", &column, &first);
14681 show (stream, "n32", &column, &first);
14682 show (stream, "64", &column, &first);
14683 show (stream, "eabi", &column, &first);
14685 fputc ('\n', stream);
14687 fprintf (stream, _("\
14688 -32 create o32 ABI object file (default)\n\
14689 -n32 create n32 ABI object file\n\
14690 -64 create 64 ABI object file\n"));
14695 mips_dwarf2_format ()
14697 if (mips_abi == N64_ABI)
14700 return dwarf2_format_64bit_irix;
14702 return dwarf2_format_64bit;
14706 return dwarf2_format_32bit;