1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 /* Allow override of standard little-endian ECOFF format. */
107 #ifndef ECOFF_LITTLE_FORMAT
108 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
111 extern int target_big_endian;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
116 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
124 /* The ABI to use. */
135 /* MIPS ABI we are using for this output file. */
136 static enum mips_abi_level mips_abi = NO_ABI;
138 /* Whether or not we have code that can call pic code. */
139 int mips_abicalls = FALSE;
141 /* This is the set of options which may be modified by the .set
142 pseudo-op. We use a struct so that .set push and .set pop are more
145 struct mips_set_options
147 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
148 if it has not been initialized. Changed by `.set mipsN', and the
149 -mipsN command line option, and the default CPU. */
151 /* Enabled Application Specific Extensions (ASEs). These are set to -1
152 if they have not been initialized. Changed by `.set <asename>', by
153 command line options, and based on the default architecture. */
156 /* Whether we are assembling for the mips16 processor. 0 if we are
157 not, 1 if we are, and -1 if the value has not been initialized.
158 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
159 -nomips16 command line options, and the default CPU. */
161 /* Non-zero if we should not reorder instructions. Changed by `.set
162 reorder' and `.set noreorder'. */
164 /* Non-zero if we should not permit the $at ($1) register to be used
165 in instructions. Changed by `.set at' and `.set noat'. */
167 /* Non-zero if we should warn when a macro instruction expands into
168 more than one machine instruction. Changed by `.set nomacro' and
170 int warn_about_macros;
171 /* Non-zero if we should not move instructions. Changed by `.set
172 move', `.set volatile', `.set nomove', and `.set novolatile'. */
174 /* Non-zero if we should not optimize branches by moving the target
175 of the branch into the delay slot. Actually, we don't perform
176 this optimization anyhow. Changed by `.set bopt' and `.set
179 /* Non-zero if we should not autoextend mips16 instructions.
180 Changed by `.set autoextend' and `.set noautoextend'. */
182 /* Restrict general purpose registers and floating point registers
183 to 32 bit. This is initially determined when -mgp32 or -mfp32
184 is passed but can changed if the assembler code uses .set mipsN. */
187 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
188 command line option, and the default CPU. */
192 /* True if -mgp32 was passed. */
193 static int file_mips_gp32 = -1;
195 /* True if -mfp32 was passed. */
196 static int file_mips_fp32 = -1;
198 /* This is the struct we use to hold the current set of options. Note
199 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
200 -1 to indicate that they have not been initialized. */
202 static struct mips_set_options mips_opts =
204 ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
207 /* These variables are filled in with the masks of registers used.
208 The object format code reads them and puts them in the appropriate
210 unsigned long mips_gprmask;
211 unsigned long mips_cprmask[4];
213 /* MIPS ISA we are using for this output file. */
214 static int file_mips_isa = ISA_UNKNOWN;
216 /* True if -mips16 was passed or implied by arguments passed on the
217 command line (e.g., by -march). */
218 static int file_ase_mips16;
220 /* True if -mips3d was passed or implied by arguments passed on the
221 command line (e.g., by -march). */
222 static int file_ase_mips3d;
224 /* True if -mdmx was passed or implied by arguments passed on the
225 command line (e.g., by -march). */
226 static int file_ase_mdmx;
228 /* The argument of the -march= flag. The architecture we are assembling. */
229 static int file_mips_arch = CPU_UNKNOWN;
230 static const char *mips_arch_string;
232 /* The argument of the -mtune= flag. The architecture for which we
234 static int mips_tune = CPU_UNKNOWN;
235 static const char *mips_tune_string;
237 /* True when generating 32-bit code for a 64-bit processor. */
238 static int mips_32bitmode = 0;
240 /* Some ISA's have delay slots for instructions which read or write
241 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
242 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
243 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
244 delay slot in this ISA. The uses of this macro assume that any
245 ISA that has delay slots for one of these, has them for all. They
246 also assume that ISAs which don't have delays for these insns, don't
247 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
248 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
250 || (ISA) == ISA_MIPS2 \
251 || (ISA) == ISA_MIPS3 \
254 /* True if the given ABI requires 32-bit registers. */
255 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
257 /* Likewise 64-bit registers. */
258 #define ABI_NEEDS_64BIT_REGS(ABI) \
260 || (ABI) == N64_ABI \
263 /* Return true if ISA supports 64 bit gp register instructions. */
264 #define ISA_HAS_64BIT_REGS(ISA) ( \
266 || (ISA) == ISA_MIPS4 \
267 || (ISA) == ISA_MIPS5 \
268 || (ISA) == ISA_MIPS64 \
271 /* Return true if ISA supports 64-bit right rotate (dror et al.)
273 #define ISA_HAS_DROR(ISA) ( \
277 /* Return true if ISA supports 32-bit right rotate (ror et al.)
279 #define ISA_HAS_ROR(ISA) ( \
280 (ISA) == ISA_MIPS32R2 \
283 #define HAVE_32BIT_GPRS \
284 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
286 #define HAVE_32BIT_FPRS \
287 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
289 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
290 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
292 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
294 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
296 /* We can only have 64bit addresses if the object file format
298 #define HAVE_32BIT_ADDRESSES \
300 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
301 || ! HAVE_64BIT_OBJECTS) \
302 && mips_pic != EMBEDDED_PIC))
304 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
306 /* Addresses are loaded in different ways, depending on the address size
307 in use. The n32 ABI Documentation also mandates the use of additions
308 with overflow checking, but existing implementations don't follow it. */
309 #define ADDRESS_ADD_INSN \
310 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
312 #define ADDRESS_ADDI_INSN \
313 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
315 #define ADDRESS_LOAD_INSN \
316 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
318 #define ADDRESS_STORE_INSN \
319 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
321 /* Return true if the given CPU supports the MIPS16 ASE. */
322 #define CPU_HAS_MIPS16(cpu) \
323 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
324 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
326 /* Return true if the given CPU supports the MIPS3D ASE. */
327 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
330 /* Return true if the given CPU supports the MDMX ASE. */
331 #define CPU_HAS_MDMX(cpu) (FALSE \
334 /* True if CPU has a dror instruction. */
335 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
337 /* True if CPU has a ror instruction. */
338 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
340 /* Whether the processor uses hardware interlocks to protect
341 reads from the HI and LO registers, and thus does not
342 require nops to be inserted. */
344 #define hilo_interlocks (mips_opts.arch == CPU_R4010 \
345 || mips_opts.arch == CPU_VR5500 \
346 || mips_opts.arch == CPU_RM7000 \
347 || mips_opts.arch == CPU_SB1 \
350 /* Whether the processor uses hardware interlocks to protect reads
351 from the GPRs, and thus does not require nops to be inserted. */
352 #define gpr_interlocks \
353 (mips_opts.isa != ISA_MIPS1 \
354 || mips_opts.arch == CPU_VR5400 \
355 || mips_opts.arch == CPU_VR5500 \
356 || mips_opts.arch == CPU_R3900)
358 /* As with other "interlocks" this is used by hardware that has FP
359 (co-processor) interlocks. */
360 /* Itbl support may require additional care here. */
361 #define cop_interlocks (mips_opts.arch == CPU_R4300 \
362 || mips_opts.arch == CPU_VR5400 \
363 || mips_opts.arch == CPU_VR5500 \
364 || mips_opts.arch == CPU_SB1 \
367 /* Is this a mfhi or mflo instruction? */
368 #define MF_HILO_INSN(PINFO) \
369 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
371 /* MIPS PIC level. */
373 enum mips_pic_level mips_pic;
375 /* Warn about all NOPS that the assembler generates. */
376 static int warn_nops = 0;
378 /* 1 if we should generate 32 bit offsets from the $gp register in
379 SVR4_PIC mode. Currently has no meaning in other modes. */
380 static int mips_big_got = 0;
382 /* 1 if trap instructions should used for overflow rather than break
384 static int mips_trap = 0;
386 /* 1 if double width floating point constants should not be constructed
387 by assembling two single width halves into two single width floating
388 point registers which just happen to alias the double width destination
389 register. On some architectures this aliasing can be disabled by a bit
390 in the status register, and the setting of this bit cannot be determined
391 automatically at assemble time. */
392 static int mips_disable_float_construction;
394 /* Non-zero if any .set noreorder directives were used. */
396 static int mips_any_noreorder;
398 /* Non-zero if nops should be inserted when the register referenced in
399 an mfhi/mflo instruction is read in the next two instructions. */
400 static int mips_7000_hilo_fix;
402 /* The size of the small data section. */
403 static unsigned int g_switch_value = 8;
404 /* Whether the -G option was used. */
405 static int g_switch_seen = 0;
410 /* If we can determine in advance that GP optimization won't be
411 possible, we can skip the relaxation stuff that tries to produce
412 GP-relative references. This makes delay slot optimization work
415 This function can only provide a guess, but it seems to work for
416 gcc output. It needs to guess right for gcc, otherwise gcc
417 will put what it thinks is a GP-relative instruction in a branch
420 I don't know if a fix is needed for the SVR4_PIC mode. I've only
421 fixed it for the non-PIC mode. KR 95/04/07 */
422 static int nopic_need_relax (symbolS *, int);
424 /* handle of the OPCODE hash table */
425 static struct hash_control *op_hash = NULL;
427 /* The opcode hash table we use for the mips16. */
428 static struct hash_control *mips16_op_hash = NULL;
430 /* This array holds the chars that always start a comment. If the
431 pre-processor is disabled, these aren't very useful */
432 const char comment_chars[] = "#";
434 /* This array holds the chars that only start a comment at the beginning of
435 a line. If the line seems to have the form '# 123 filename'
436 .line and .file directives will appear in the pre-processed output */
437 /* Note that input_file.c hand checks for '#' at the beginning of the
438 first line of the input file. This is because the compiler outputs
439 #NO_APP at the beginning of its output. */
440 /* Also note that C style comments are always supported. */
441 const char line_comment_chars[] = "#";
443 /* This array holds machine specific line separator characters. */
444 const char line_separator_chars[] = ";";
446 /* Chars that can be used to separate mant from exp in floating point nums */
447 const char EXP_CHARS[] = "eE";
449 /* Chars that mean this number is a floating point constant */
452 const char FLT_CHARS[] = "rRsSfFdDxXpP";
454 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
455 changed in read.c . Ideally it shouldn't have to know about it at all,
456 but nothing is ideal around here.
459 static char *insn_error;
461 static int auto_align = 1;
463 /* When outputting SVR4 PIC code, the assembler needs to know the
464 offset in the stack frame from which to restore the $gp register.
465 This is set by the .cprestore pseudo-op, and saved in this
467 static offsetT mips_cprestore_offset = -1;
469 /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some
470 more optimizations, it can use a register value instead of a memory-saved
471 offset and even an other register than $gp as global pointer. */
472 static offsetT mips_cpreturn_offset = -1;
473 static int mips_cpreturn_register = -1;
474 static int mips_gp_register = GP;
475 static int mips_gprel_offset = 0;
477 /* Whether mips_cprestore_offset has been set in the current function
478 (or whether it has already been warned about, if not). */
479 static int mips_cprestore_valid = 0;
481 /* This is the register which holds the stack frame, as set by the
482 .frame pseudo-op. This is needed to implement .cprestore. */
483 static int mips_frame_reg = SP;
485 /* Whether mips_frame_reg has been set in the current function
486 (or whether it has already been warned about, if not). */
487 static int mips_frame_reg_valid = 0;
489 /* To output NOP instructions correctly, we need to keep information
490 about the previous two instructions. */
492 /* Whether we are optimizing. The default value of 2 means to remove
493 unneeded NOPs and swap branch instructions when possible. A value
494 of 1 means to not swap branches. A value of 0 means to always
496 static int mips_optimize = 2;
498 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
499 equivalent to seeing no -g option at all. */
500 static int mips_debug = 0;
502 /* The previous instruction. */
503 static struct mips_cl_insn prev_insn;
505 /* The instruction before prev_insn. */
506 static struct mips_cl_insn prev_prev_insn;
508 /* If we don't want information for prev_insn or prev_prev_insn, we
509 point the insn_mo field at this dummy integer. */
510 static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 };
512 /* Non-zero if prev_insn is valid. */
513 static int prev_insn_valid;
515 /* The frag for the previous instruction. */
516 static struct frag *prev_insn_frag;
518 /* The offset into prev_insn_frag for the previous instruction. */
519 static long prev_insn_where;
521 /* The reloc type for the previous instruction, if any. */
522 static bfd_reloc_code_real_type prev_insn_reloc_type[3];
524 /* The reloc for the previous instruction, if any. */
525 static fixS *prev_insn_fixp[3];
527 /* Non-zero if the previous instruction was in a delay slot. */
528 static int prev_insn_is_delay_slot;
530 /* Non-zero if the previous instruction was in a .set noreorder. */
531 static int prev_insn_unreordered;
533 /* Non-zero if the previous instruction uses an extend opcode (if
535 static int prev_insn_extended;
537 /* Non-zero if the previous previous instruction was in a .set
539 static int prev_prev_insn_unreordered;
541 /* If this is set, it points to a frag holding nop instructions which
542 were inserted before the start of a noreorder section. If those
543 nops turn out to be unnecessary, the size of the frag can be
545 static fragS *prev_nop_frag;
547 /* The number of nop instructions we created in prev_nop_frag. */
548 static int prev_nop_frag_holds;
550 /* The number of nop instructions that we know we need in
552 static int prev_nop_frag_required;
554 /* The number of instructions we've seen since prev_nop_frag. */
555 static int prev_nop_frag_since;
557 /* For ECOFF and ELF, relocations against symbols are done in two
558 parts, with a HI relocation and a LO relocation. Each relocation
559 has only 16 bits of space to store an addend. This means that in
560 order for the linker to handle carries correctly, it must be able
561 to locate both the HI and the LO relocation. This means that the
562 relocations must appear in order in the relocation table.
564 In order to implement this, we keep track of each unmatched HI
565 relocation. We then sort them so that they immediately precede the
566 corresponding LO relocation. */
571 struct mips_hi_fixup *next;
574 /* The section this fixup is in. */
578 /* The list of unmatched HI relocs. */
580 static struct mips_hi_fixup *mips_hi_fixup_list;
582 /* The frag containing the last explicit relocation operator.
583 Null if explicit relocations have not been used. */
585 static fragS *prev_reloc_op_frag;
587 /* Map normal MIPS register numbers to mips16 register numbers. */
589 #define X ILLEGAL_REG
590 static const int mips32_to_16_reg_map[] =
592 X, X, 2, 3, 4, 5, 6, 7,
593 X, X, X, X, X, X, X, X,
594 0, 1, X, X, X, X, X, X,
595 X, X, X, X, X, X, X, X
599 /* Map mips16 register numbers to normal MIPS register numbers. */
601 static const unsigned int mips16_to_32_reg_map[] =
603 16, 17, 2, 3, 4, 5, 6, 7
606 static int mips_fix_4122_bugs;
608 /* We don't relax branches by default, since this causes us to expand
609 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
610 fail to compute the offset before expanding the macro to the most
611 efficient expansion. */
613 static int mips_relax_branch;
615 /* Since the MIPS does not have multiple forms of PC relative
616 instructions, we do not have to do relaxing as is done on other
617 platforms. However, we do have to handle GP relative addressing
618 correctly, which turns out to be a similar problem.
620 Every macro that refers to a symbol can occur in (at least) two
621 forms, one with GP relative addressing and one without. For
622 example, loading a global variable into a register generally uses
623 a macro instruction like this:
625 If i can be addressed off the GP register (this is true if it is in
626 the .sbss or .sdata section, or if it is known to be smaller than
627 the -G argument) this will generate the following instruction:
629 This instruction will use a GPREL reloc. If i can not be addressed
630 off the GP register, the following instruction sequence will be used:
633 In this case the first instruction will have a HI16 reloc, and the
634 second reloc will have a LO16 reloc. Both relocs will be against
637 The issue here is that we may not know whether i is GP addressable
638 until after we see the instruction that uses it. Therefore, we
639 want to be able to choose the final instruction sequence only at
640 the end of the assembly. This is similar to the way other
641 platforms choose the size of a PC relative instruction only at the
644 When generating position independent code we do not use GP
645 addressing in quite the same way, but the issue still arises as
646 external symbols and local symbols must be handled differently.
648 We handle these issues by actually generating both possible
649 instruction sequences. The longer one is put in a frag_var with
650 type rs_machine_dependent. We encode what to do with the frag in
651 the subtype field. We encode (1) the number of existing bytes to
652 replace, (2) the number of new bytes to use, (3) the offset from
653 the start of the existing bytes to the first reloc we must generate
654 (that is, the offset is applied from the start of the existing
655 bytes after they are replaced by the new bytes, if any), (4) the
656 offset from the start of the existing bytes to the second reloc,
657 (5) whether a third reloc is needed (the third reloc is always four
658 bytes after the second reloc), and (6) whether to warn if this
659 variant is used (this is sometimes needed if .set nomacro or .set
660 noat is in effect). All these numbers are reasonably small.
662 Generating two instruction sequences must be handled carefully to
663 ensure that delay slots are handled correctly. Fortunately, there
664 are a limited number of cases. When the second instruction
665 sequence is generated, append_insn is directed to maintain the
666 existing delay slot information, so it continues to apply to any
667 code after the second instruction sequence. This means that the
668 second instruction sequence must not impose any requirements not
669 required by the first instruction sequence.
671 These variant frags are then handled in functions called by the
672 machine independent code. md_estimate_size_before_relax returns
673 the final size of the frag. md_convert_frag sets up the final form
674 of the frag. tc_gen_reloc adjust the first reloc and adds a second
676 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
680 | (((reloc1) + 64) << 9) \
681 | (((reloc2) + 64) << 2) \
682 | ((reloc3) ? (1 << 1) : 0) \
684 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
685 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
686 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
687 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
688 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
689 #define RELAX_WARN(i) ((i) & 1)
691 /* Branch without likely bit. If label is out of range, we turn:
693 beq reg1, reg2, label
703 with the following opcode replacements:
710 bltzal <-> bgezal (with jal label instead of j label)
712 Even though keeping the delay slot instruction in the delay slot of
713 the branch would be more efficient, it would be very tricky to do
714 correctly, because we'd have to introduce a variable frag *after*
715 the delay slot instruction, and expand that instead. Let's do it
716 the easy way for now, even if the branch-not-taken case now costs
717 one additional instruction. Out-of-range branches are not supposed
718 to be common, anyway.
720 Branch likely. If label is out of range, we turn:
722 beql reg1, reg2, label
723 delay slot (annulled if branch not taken)
732 delay slot (executed only if branch taken)
735 It would be possible to generate a shorter sequence by losing the
736 likely bit, generating something like:
741 delay slot (executed only if branch taken)
753 bltzall -> bgezal (with jal label instead of j label)
754 bgezall -> bltzal (ditto)
757 but it's not clear that it would actually improve performance. */
758 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
761 | ((toofar) ? 1 : 0) \
763 | ((likely) ? 4 : 0) \
764 | ((uncond) ? 8 : 0)))
765 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
766 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
767 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
768 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
769 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
771 /* For mips16 code, we use an entirely different form of relaxation.
772 mips16 supports two versions of most instructions which take
773 immediate values: a small one which takes some small value, and a
774 larger one which takes a 16 bit value. Since branches also follow
775 this pattern, relaxing these values is required.
777 We can assemble both mips16 and normal MIPS code in a single
778 object. Therefore, we need to support this type of relaxation at
779 the same time that we support the relaxation described above. We
780 use the high bit of the subtype field to distinguish these cases.
782 The information we store for this type of relaxation is the
783 argument code found in the opcode file for this relocation, whether
784 the user explicitly requested a small or extended form, and whether
785 the relocation is in a jump or jal delay slot. That tells us the
786 size of the value, and how it should be stored. We also store
787 whether the fragment is considered to be extended or not. We also
788 store whether this is known to be a branch to a different section,
789 whether we have tried to relax this frag yet, and whether we have
790 ever extended a PC relative fragment because of a shift count. */
791 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
794 | ((small) ? 0x100 : 0) \
795 | ((ext) ? 0x200 : 0) \
796 | ((dslot) ? 0x400 : 0) \
797 | ((jal_dslot) ? 0x800 : 0))
798 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
799 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
800 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
801 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
802 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
803 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
804 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
805 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
806 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
807 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
808 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
809 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
811 /* Is the given value a sign-extended 32-bit value? */
812 #define IS_SEXT_32BIT_NUM(x) \
813 (((x) &~ (offsetT) 0x7fffffff) == 0 \
814 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
816 /* Is the given value a sign-extended 16-bit value? */
817 #define IS_SEXT_16BIT_NUM(x) \
818 (((x) &~ (offsetT) 0x7fff) == 0 \
819 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
822 /* Prototypes for static functions. */
824 #define internalError() \
825 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
827 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
829 static void append_insn
830 (char *place, struct mips_cl_insn *ip, expressionS *p,
831 bfd_reloc_code_real_type *r);
832 static void mips_no_prev_insn (int);
833 static void mips16_macro_build
834 (char *, int *, expressionS *, const char *, const char *, va_list);
835 static void load_register (int *, int, expressionS *, int);
836 static void macro (struct mips_cl_insn * ip);
837 static void mips16_macro (struct mips_cl_insn * ip);
838 #ifdef LOSING_COMPILER
839 static void macro2 (struct mips_cl_insn * ip);
841 static void mips_ip (char *str, struct mips_cl_insn * ip);
842 static void mips16_ip (char *str, struct mips_cl_insn * ip);
843 static void mips16_immed
844 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
845 unsigned long *, bfd_boolean *, unsigned short *);
846 static size_t my_getSmallExpression
847 (expressionS *, bfd_reloc_code_real_type *, char *);
848 static void my_getExpression (expressionS *, char *);
849 static void s_align (int);
850 static void s_change_sec (int);
851 static void s_change_section (int);
852 static void s_cons (int);
853 static void s_float_cons (int);
854 static void s_mips_globl (int);
855 static void s_option (int);
856 static void s_mipsset (int);
857 static void s_abicalls (int);
858 static void s_cpload (int);
859 static void s_cpsetup (int);
860 static void s_cplocal (int);
861 static void s_cprestore (int);
862 static void s_cpreturn (int);
863 static void s_gpvalue (int);
864 static void s_gpword (int);
865 static void s_gpdword (int);
866 static void s_cpadd (int);
867 static void s_insn (int);
868 static void md_obj_begin (void);
869 static void md_obj_end (void);
870 static void s_mips_ent (int);
871 static void s_mips_end (int);
872 static void s_mips_frame (int);
873 static void s_mips_mask (int reg_type);
874 static void s_mips_stab (int);
875 static void s_mips_weakext (int);
876 static void s_mips_file (int);
877 static void s_mips_loc (int);
878 static bfd_boolean pic_need_relax (symbolS *, asection *);
879 static int relaxed_branch_length (fragS *, asection *, int);
880 static int validate_mips_insn (const struct mips_opcode *);
882 /* Table and functions used to map between CPU/ISA names, and
883 ISA levels, and CPU numbers. */
887 const char *name; /* CPU or ISA name. */
888 int is_isa; /* Is this an ISA? (If 0, a CPU.) */
889 int isa; /* ISA level. */
890 int cpu; /* CPU number (default CPU if ISA). */
893 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
894 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
895 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
899 The following pseudo-ops from the Kane and Heinrich MIPS book
900 should be defined here, but are currently unsupported: .alias,
901 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
903 The following pseudo-ops from the Kane and Heinrich MIPS book are
904 specific to the type of debugging information being generated, and
905 should be defined by the object format: .aent, .begin, .bend,
906 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
909 The following pseudo-ops from the Kane and Heinrich MIPS book are
910 not MIPS CPU specific, but are also not specific to the object file
911 format. This file is probably the best place to define them, but
912 they are not currently supported: .asm0, .endr, .lab, .repeat,
915 static const pseudo_typeS mips_pseudo_table[] =
917 /* MIPS specific pseudo-ops. */
918 {"option", s_option, 0},
919 {"set", s_mipsset, 0},
920 {"rdata", s_change_sec, 'r'},
921 {"sdata", s_change_sec, 's'},
922 {"livereg", s_ignore, 0},
923 {"abicalls", s_abicalls, 0},
924 {"cpload", s_cpload, 0},
925 {"cpsetup", s_cpsetup, 0},
926 {"cplocal", s_cplocal, 0},
927 {"cprestore", s_cprestore, 0},
928 {"cpreturn", s_cpreturn, 0},
929 {"gpvalue", s_gpvalue, 0},
930 {"gpword", s_gpword, 0},
931 {"gpdword", s_gpdword, 0},
932 {"cpadd", s_cpadd, 0},
935 /* Relatively generic pseudo-ops that happen to be used on MIPS
937 {"asciiz", stringer, 1},
938 {"bss", s_change_sec, 'b'},
941 {"dword", s_cons, 3},
942 {"weakext", s_mips_weakext, 0},
944 /* These pseudo-ops are defined in read.c, but must be overridden
945 here for one reason or another. */
946 {"align", s_align, 0},
948 {"data", s_change_sec, 'd'},
949 {"double", s_float_cons, 'd'},
950 {"float", s_float_cons, 'f'},
951 {"globl", s_mips_globl, 0},
952 {"global", s_mips_globl, 0},
953 {"hword", s_cons, 1},
958 {"section", s_change_section, 0},
959 {"short", s_cons, 1},
960 {"single", s_float_cons, 'f'},
961 {"stabn", s_mips_stab, 'n'},
962 {"text", s_change_sec, 't'},
965 { "extern", ecoff_directive_extern, 0},
970 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
972 /* These pseudo-ops should be defined by the object file format.
973 However, a.out doesn't support them, so we have versions here. */
974 {"aent", s_mips_ent, 1},
975 {"bgnb", s_ignore, 0},
976 {"end", s_mips_end, 0},
977 {"endb", s_ignore, 0},
978 {"ent", s_mips_ent, 0},
979 {"file", s_mips_file, 0},
980 {"fmask", s_mips_mask, 'F'},
981 {"frame", s_mips_frame, 0},
982 {"loc", s_mips_loc, 0},
983 {"mask", s_mips_mask, 'R'},
984 {"verstamp", s_ignore, 0},
988 extern void pop_insert (const pseudo_typeS *);
991 mips_pop_insert (void)
993 pop_insert (mips_pseudo_table);
994 if (! ECOFF_DEBUGGING)
995 pop_insert (mips_nonecoff_pseudo_table);
998 /* Symbols labelling the current insn. */
1000 struct insn_label_list
1002 struct insn_label_list *next;
1006 static struct insn_label_list *insn_labels;
1007 static struct insn_label_list *free_insn_labels;
1009 static void mips_clear_insn_labels (void);
1012 mips_clear_insn_labels (void)
1014 register struct insn_label_list **pl;
1016 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1022 static char *expr_end;
1024 /* Expressions which appear in instructions. These are set by
1027 static expressionS imm_expr;
1028 static expressionS offset_expr;
1030 /* Relocs associated with imm_expr and offset_expr. */
1032 static bfd_reloc_code_real_type imm_reloc[3]
1033 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1034 static bfd_reloc_code_real_type offset_reloc[3]
1035 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1037 /* These are set by mips16_ip if an explicit extension is used. */
1039 static bfd_boolean mips16_small, mips16_ext;
1042 /* The pdr segment for per procedure frame/regmask info. Not used for
1045 static segT pdr_seg;
1048 /* The default target format to use. */
1051 mips_target_format (void)
1053 switch (OUTPUT_FLAVOR)
1055 case bfd_target_aout_flavour:
1056 return target_big_endian ? "a.out-mips-big" : "a.out-mips-little";
1057 case bfd_target_ecoff_flavour:
1058 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1059 case bfd_target_coff_flavour:
1061 case bfd_target_elf_flavour:
1063 /* This is traditional mips. */
1064 return (target_big_endian
1065 ? (HAVE_64BIT_OBJECTS
1066 ? "elf64-tradbigmips"
1068 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1069 : (HAVE_64BIT_OBJECTS
1070 ? "elf64-tradlittlemips"
1072 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1074 return (target_big_endian
1075 ? (HAVE_64BIT_OBJECTS
1078 ? "elf32-nbigmips" : "elf32-bigmips"))
1079 : (HAVE_64BIT_OBJECTS
1080 ? "elf64-littlemips"
1082 ? "elf32-nlittlemips" : "elf32-littlemips")));
1090 /* This function is called once, at assembler startup time. It should
1091 set up all the tables, etc. that the MD part of the assembler will need. */
1096 register const char *retval = NULL;
1100 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
1101 as_warn (_("Could not set architecture and machine"));
1103 op_hash = hash_new ();
1105 for (i = 0; i < NUMOPCODES;)
1107 const char *name = mips_opcodes[i].name;
1109 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
1112 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1113 mips_opcodes[i].name, retval);
1114 /* Probably a memory allocation problem? Give up now. */
1115 as_fatal (_("Broken assembler. No assembly attempted."));
1119 if (mips_opcodes[i].pinfo != INSN_MACRO)
1121 if (!validate_mips_insn (&mips_opcodes[i]))
1126 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1129 mips16_op_hash = hash_new ();
1132 while (i < bfd_mips16_num_opcodes)
1134 const char *name = mips16_opcodes[i].name;
1136 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
1138 as_fatal (_("internal: can't hash `%s': %s"),
1139 mips16_opcodes[i].name, retval);
1142 if (mips16_opcodes[i].pinfo != INSN_MACRO
1143 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1144 != mips16_opcodes[i].match))
1146 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1147 mips16_opcodes[i].name, mips16_opcodes[i].args);
1152 while (i < bfd_mips16_num_opcodes
1153 && strcmp (mips16_opcodes[i].name, name) == 0);
1157 as_fatal (_("Broken assembler. No assembly attempted."));
1159 /* We add all the general register names to the symbol table. This
1160 helps us detect invalid uses of them. */
1161 for (i = 0; i < 32; i++)
1165 sprintf (buf, "$%d", i);
1166 symbol_table_insert (symbol_new (buf, reg_section, i,
1167 &zero_address_frag));
1169 symbol_table_insert (symbol_new ("$ra", reg_section, RA,
1170 &zero_address_frag));
1171 symbol_table_insert (symbol_new ("$fp", reg_section, FP,
1172 &zero_address_frag));
1173 symbol_table_insert (symbol_new ("$sp", reg_section, SP,
1174 &zero_address_frag));
1175 symbol_table_insert (symbol_new ("$gp", reg_section, GP,
1176 &zero_address_frag));
1177 symbol_table_insert (symbol_new ("$at", reg_section, AT,
1178 &zero_address_frag));
1179 symbol_table_insert (symbol_new ("$kt0", reg_section, KT0,
1180 &zero_address_frag));
1181 symbol_table_insert (symbol_new ("$kt1", reg_section, KT1,
1182 &zero_address_frag));
1183 symbol_table_insert (symbol_new ("$zero", reg_section, ZERO,
1184 &zero_address_frag));
1185 symbol_table_insert (symbol_new ("$pc", reg_section, -1,
1186 &zero_address_frag));
1188 /* If we don't add these register names to the symbol table, they
1189 may end up being added as regular symbols by operand(), and then
1190 make it to the object file as undefined in case they're not
1191 regarded as local symbols. They're local in o32, since `$' is a
1192 local symbol prefix, but not in n32 or n64. */
1193 for (i = 0; i < 8; i++)
1197 sprintf (buf, "$fcc%i", i);
1198 symbol_table_insert (symbol_new (buf, reg_section, -1,
1199 &zero_address_frag));
1202 mips_no_prev_insn (FALSE);
1205 mips_cprmask[0] = 0;
1206 mips_cprmask[1] = 0;
1207 mips_cprmask[2] = 0;
1208 mips_cprmask[3] = 0;
1210 /* set the default alignment for the text section (2**2) */
1211 record_alignment (text_section, 2);
1213 if (USE_GLOBAL_POINTER_OPT)
1214 bfd_set_gp_size (stdoutput, g_switch_value);
1216 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1218 /* On a native system, sections must be aligned to 16 byte
1219 boundaries. When configured for an embedded ELF target, we
1221 if (strcmp (TARGET_OS, "elf") != 0)
1223 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
1224 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
1225 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
1228 /* Create a .reginfo section for register masks and a .mdebug
1229 section for debugging information. */
1237 subseg = now_subseg;
1239 /* The ABI says this section should be loaded so that the
1240 running program can access it. However, we don't load it
1241 if we are configured for an embedded target */
1242 flags = SEC_READONLY | SEC_DATA;
1243 if (strcmp (TARGET_OS, "elf") != 0)
1244 flags |= SEC_ALLOC | SEC_LOAD;
1246 if (mips_abi != N64_ABI)
1248 sec = subseg_new (".reginfo", (subsegT) 0);
1250 bfd_set_section_flags (stdoutput, sec, flags);
1251 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
1254 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
1259 /* The 64-bit ABI uses a .MIPS.options section rather than
1260 .reginfo section. */
1261 sec = subseg_new (".MIPS.options", (subsegT) 0);
1262 bfd_set_section_flags (stdoutput, sec, flags);
1263 bfd_set_section_alignment (stdoutput, sec, 3);
1266 /* Set up the option header. */
1268 Elf_Internal_Options opthdr;
1271 opthdr.kind = ODK_REGINFO;
1272 opthdr.size = (sizeof (Elf_External_Options)
1273 + sizeof (Elf64_External_RegInfo));
1276 f = frag_more (sizeof (Elf_External_Options));
1277 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
1278 (Elf_External_Options *) f);
1280 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
1285 if (ECOFF_DEBUGGING)
1287 sec = subseg_new (".mdebug", (subsegT) 0);
1288 (void) bfd_set_section_flags (stdoutput, sec,
1289 SEC_HAS_CONTENTS | SEC_READONLY);
1290 (void) bfd_set_section_alignment (stdoutput, sec, 2);
1293 else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr)
1295 pdr_seg = subseg_new (".pdr", (subsegT) 0);
1296 (void) bfd_set_section_flags (stdoutput, pdr_seg,
1297 SEC_READONLY | SEC_RELOC
1299 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
1303 subseg_set (seg, subseg);
1307 if (! ECOFF_DEBUGGING)
1314 if (! ECOFF_DEBUGGING)
1319 md_assemble (char *str)
1321 struct mips_cl_insn insn;
1322 bfd_reloc_code_real_type unused_reloc[3]
1323 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1325 imm_expr.X_op = O_absent;
1326 offset_expr.X_op = O_absent;
1327 imm_reloc[0] = BFD_RELOC_UNUSED;
1328 imm_reloc[1] = BFD_RELOC_UNUSED;
1329 imm_reloc[2] = BFD_RELOC_UNUSED;
1330 offset_reloc[0] = BFD_RELOC_UNUSED;
1331 offset_reloc[1] = BFD_RELOC_UNUSED;
1332 offset_reloc[2] = BFD_RELOC_UNUSED;
1334 if (mips_opts.mips16)
1335 mips16_ip (str, &insn);
1338 mips_ip (str, &insn);
1339 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1340 str, insn.insn_opcode));
1345 as_bad ("%s `%s'", insn_error, str);
1349 if (insn.insn_mo->pinfo == INSN_MACRO)
1351 if (mips_opts.mips16)
1352 mips16_macro (&insn);
1358 if (imm_expr.X_op != O_absent)
1359 append_insn (NULL, &insn, &imm_expr, imm_reloc);
1360 else if (offset_expr.X_op != O_absent)
1361 append_insn (NULL, &insn, &offset_expr, offset_reloc);
1363 append_insn (NULL, &insn, NULL, unused_reloc);
1367 /* Return true if the given relocation might need a matching %lo().
1368 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1369 applied to local symbols. */
1371 static inline bfd_boolean
1372 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
1374 return (reloc == BFD_RELOC_HI16_S
1375 || reloc == BFD_RELOC_MIPS_GOT16);
1378 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1381 static inline bfd_boolean
1382 fixup_has_matching_lo_p (fixS *fixp)
1384 return (fixp->fx_next != NULL
1385 && fixp->fx_next->fx_r_type == BFD_RELOC_LO16
1386 && fixp->fx_addsy == fixp->fx_next->fx_addsy
1387 && fixp->fx_offset == fixp->fx_next->fx_offset);
1390 /* See whether instruction IP reads register REG. CLASS is the type
1394 insn_uses_reg (struct mips_cl_insn *ip, unsigned int reg,
1395 enum mips_regclass class)
1397 if (class == MIPS16_REG)
1399 assert (mips_opts.mips16);
1400 reg = mips16_to_32_reg_map[reg];
1401 class = MIPS_GR_REG;
1404 /* Don't report on general register ZERO, since it never changes. */
1405 if (class == MIPS_GR_REG && reg == ZERO)
1408 if (class == MIPS_FP_REG)
1410 assert (! mips_opts.mips16);
1411 /* If we are called with either $f0 or $f1, we must check $f0.
1412 This is not optimal, because it will introduce an unnecessary
1413 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1414 need to distinguish reading both $f0 and $f1 or just one of
1415 them. Note that we don't have to check the other way,
1416 because there is no instruction that sets both $f0 and $f1
1417 and requires a delay. */
1418 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
1419 && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1)
1420 == (reg &~ (unsigned) 1)))
1422 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
1423 && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1)
1424 == (reg &~ (unsigned) 1)))
1427 else if (! mips_opts.mips16)
1429 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
1430 && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg)
1432 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
1433 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg)
1438 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
1439 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX)
1440 & MIPS16OP_MASK_RX)]
1443 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
1444 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY)
1445 & MIPS16OP_MASK_RY)]
1448 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
1449 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
1450 & MIPS16OP_MASK_MOVE32Z)]
1453 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
1455 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
1457 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
1459 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
1460 && ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
1461 & MIPS16OP_MASK_REGR32) == reg)
1468 /* This function returns true if modifying a register requires a
1472 reg_needs_delay (unsigned int reg)
1474 unsigned long prev_pinfo;
1476 prev_pinfo = prev_insn.insn_mo->pinfo;
1477 if (! mips_opts.noreorder
1478 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1479 && ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1480 || (! gpr_interlocks
1481 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
1483 /* A load from a coprocessor or from memory. All load
1484 delays delay the use of general register rt for one
1485 instruction on the r3000. The r6000 and r4000 use
1487 /* Itbl support may require additional care here. */
1488 know (prev_pinfo & INSN_WRITE_GPR_T);
1489 if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT))
1496 /* Mark instruction labels in mips16 mode. This permits the linker to
1497 handle them specially, such as generating jalx instructions when
1498 needed. We also make them odd for the duration of the assembly, in
1499 order to generate the right sort of code. We will make them even
1500 in the adjust_symtab routine, while leaving them marked. This is
1501 convenient for the debugger and the disassembler. The linker knows
1502 to make them odd again. */
1505 mips16_mark_labels (void)
1507 if (mips_opts.mips16)
1509 struct insn_label_list *l;
1512 for (l = insn_labels; l != NULL; l = l->next)
1515 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1516 S_SET_OTHER (l->label, STO_MIPS16);
1518 val = S_GET_VALUE (l->label);
1520 S_SET_VALUE (l->label, val + 1);
1525 /* Output an instruction. PLACE is where to put the instruction; if
1526 it is NULL, this uses frag_more to get room. IP is the instruction
1527 information. ADDRESS_EXPR is an operand of the instruction to be
1528 used with RELOC_TYPE. */
1531 append_insn (char *place, struct mips_cl_insn *ip, expressionS *address_expr,
1532 bfd_reloc_code_real_type *reloc_type)
1534 register unsigned long prev_pinfo, pinfo;
1538 bfd_boolean force_new_frag = FALSE;
1540 /* Mark instruction labels in mips16 mode. */
1541 mips16_mark_labels ();
1543 prev_pinfo = prev_insn.insn_mo->pinfo;
1544 pinfo = ip->insn_mo->pinfo;
1546 if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL))
1550 /* If the previous insn required any delay slots, see if we need
1551 to insert a NOP or two. There are eight kinds of possible
1552 hazards, of which an instruction can have at most one type.
1553 (1) a load from memory delay
1554 (2) a load from a coprocessor delay
1555 (3) an unconditional branch delay
1556 (4) a conditional branch delay
1557 (5) a move to coprocessor register delay
1558 (6) a load coprocessor register from memory delay
1559 (7) a coprocessor condition code delay
1560 (8) a HI/LO special register delay
1562 There are a lot of optimizations we could do that we don't.
1563 In particular, we do not, in general, reorder instructions.
1564 If you use gcc with optimization, it will reorder
1565 instructions and generally do much more optimization then we
1566 do here; repeating all that work in the assembler would only
1567 benefit hand written assembly code, and does not seem worth
1570 /* This is how a NOP is emitted. */
1571 #define emit_nop() \
1573 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1574 : md_number_to_chars (frag_more (4), 0, 4))
1576 /* The previous insn might require a delay slot, depending upon
1577 the contents of the current insn. */
1578 if (! mips_opts.mips16
1579 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1580 && (((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1581 && ! cop_interlocks)
1582 || (! gpr_interlocks
1583 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
1585 /* A load from a coprocessor or from memory. All load
1586 delays delay the use of general register rt for one
1587 instruction on the r3000. The r6000 and r4000 use
1589 /* Itbl support may require additional care here. */
1590 know (prev_pinfo & INSN_WRITE_GPR_T);
1591 if (mips_optimize == 0
1592 || insn_uses_reg (ip,
1593 ((prev_insn.insn_opcode >> OP_SH_RT)
1598 else if (! mips_opts.mips16
1599 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1600 && (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
1601 && ! cop_interlocks)
1602 || (mips_opts.isa == ISA_MIPS1
1603 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))))
1605 /* A generic coprocessor delay. The previous instruction
1606 modified a coprocessor general or control register. If
1607 it modified a control register, we need to avoid any
1608 coprocessor instruction (this is probably not always
1609 required, but it sometimes is). If it modified a general
1610 register, we avoid using that register.
1612 On the r6000 and r4000 loading a coprocessor register
1613 from memory is interlocked, and does not require a delay.
1615 This case is not handled very well. There is no special
1616 knowledge of CP0 handling, and the coprocessors other
1617 than the floating point unit are not distinguished at
1619 /* Itbl support may require additional care here. FIXME!
1620 Need to modify this to include knowledge about
1621 user specified delays! */
1622 if (prev_pinfo & INSN_WRITE_FPR_T)
1624 if (mips_optimize == 0
1625 || insn_uses_reg (ip,
1626 ((prev_insn.insn_opcode >> OP_SH_FT)
1631 else if (prev_pinfo & INSN_WRITE_FPR_S)
1633 if (mips_optimize == 0
1634 || insn_uses_reg (ip,
1635 ((prev_insn.insn_opcode >> OP_SH_FS)
1642 /* We don't know exactly what the previous instruction
1643 does. If the current instruction uses a coprocessor
1644 register, we must insert a NOP. If previous
1645 instruction may set the condition codes, and the
1646 current instruction uses them, we must insert two
1648 /* Itbl support may require additional care here. */
1649 if (mips_optimize == 0
1650 || ((prev_pinfo & INSN_WRITE_COND_CODE)
1651 && (pinfo & INSN_READ_COND_CODE)))
1653 else if (pinfo & INSN_COP)
1657 else if (! mips_opts.mips16
1658 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1659 && (prev_pinfo & INSN_WRITE_COND_CODE)
1660 && ! cop_interlocks)
1662 /* The previous instruction sets the coprocessor condition
1663 codes, but does not require a general coprocessor delay
1664 (this means it is a floating point comparison
1665 instruction). If this instruction uses the condition
1666 codes, we need to insert a single NOP. */
1667 /* Itbl support may require additional care here. */
1668 if (mips_optimize == 0
1669 || (pinfo & INSN_READ_COND_CODE))
1673 /* If we're fixing up mfhi/mflo for the r7000 and the
1674 previous insn was an mfhi/mflo and the current insn
1675 reads the register that the mfhi/mflo wrote to, then
1678 else if (mips_7000_hilo_fix
1679 && MF_HILO_INSN (prev_pinfo)
1680 && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD)
1687 /* If we're fixing up mfhi/mflo for the r7000 and the
1688 2nd previous insn was an mfhi/mflo and the current insn
1689 reads the register that the mfhi/mflo wrote to, then
1692 else if (mips_7000_hilo_fix
1693 && MF_HILO_INSN (prev_prev_insn.insn_opcode)
1694 && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD)
1702 else if (prev_pinfo & INSN_READ_LO)
1704 /* The previous instruction reads the LO register; if the
1705 current instruction writes to the LO register, we must
1706 insert two NOPS. Some newer processors have interlocks.
1707 Also the tx39's multiply instructions can be exectuted
1708 immediatly after a read from HI/LO (without the delay),
1709 though the tx39's divide insns still do require the
1711 if (! (hilo_interlocks
1712 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
1713 && (mips_optimize == 0
1714 || (pinfo & INSN_WRITE_LO)))
1716 /* Most mips16 branch insns don't have a delay slot.
1717 If a read from LO is immediately followed by a branch
1718 to a write to LO we have a read followed by a write
1719 less than 2 insns away. We assume the target of
1720 a branch might be a write to LO, and insert a nop
1721 between a read and an immediately following branch. */
1722 else if (mips_opts.mips16
1723 && (mips_optimize == 0
1724 || (pinfo & MIPS16_INSN_BRANCH)))
1727 else if (prev_insn.insn_mo->pinfo & INSN_READ_HI)
1729 /* The previous instruction reads the HI register; if the
1730 current instruction writes to the HI register, we must
1731 insert a NOP. Some newer processors have interlocks.
1732 Also the note tx39's multiply above. */
1733 if (! (hilo_interlocks
1734 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
1735 && (mips_optimize == 0
1736 || (pinfo & INSN_WRITE_HI)))
1738 /* Most mips16 branch insns don't have a delay slot.
1739 If a read from HI is immediately followed by a branch
1740 to a write to HI we have a read followed by a write
1741 less than 2 insns away. We assume the target of
1742 a branch might be a write to HI, and insert a nop
1743 between a read and an immediately following branch. */
1744 else if (mips_opts.mips16
1745 && (mips_optimize == 0
1746 || (pinfo & MIPS16_INSN_BRANCH)))
1750 /* If the previous instruction was in a noreorder section, then
1751 we don't want to insert the nop after all. */
1752 /* Itbl support may require additional care here. */
1753 if (prev_insn_unreordered)
1756 /* There are two cases which require two intervening
1757 instructions: 1) setting the condition codes using a move to
1758 coprocessor instruction which requires a general coprocessor
1759 delay and then reading the condition codes 2) reading the HI
1760 or LO register and then writing to it (except on processors
1761 which have interlocks). If we are not already emitting a NOP
1762 instruction, we must check for these cases compared to the
1763 instruction previous to the previous instruction. */
1764 if ((! mips_opts.mips16
1765 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1766 && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
1767 && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
1768 && (pinfo & INSN_READ_COND_CODE)
1769 && ! cop_interlocks)
1770 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
1771 && (pinfo & INSN_WRITE_LO)
1772 && ! (hilo_interlocks
1773 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))))
1774 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
1775 && (pinfo & INSN_WRITE_HI)
1776 && ! (hilo_interlocks
1777 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))))
1782 if (prev_prev_insn_unreordered)
1785 if (prev_prev_nop && nops == 0)
1788 if (mips_fix_4122_bugs && prev_insn.insn_mo->name)
1790 /* We're out of bits in pinfo, so we must resort to string
1791 ops here. Shortcuts are selected based on opcodes being
1792 limited to the VR4122 instruction set. */
1794 const char *pn = prev_insn.insn_mo->name;
1795 const char *tn = ip->insn_mo->name;
1796 if (strncmp(pn, "macc", 4) == 0
1797 || strncmp(pn, "dmacc", 5) == 0)
1799 /* Errata 21 - [D]DIV[U] after [D]MACC */
1800 if (strstr (tn, "div"))
1805 /* Errata 23 - Continuous DMULT[U]/DMACC instructions */
1806 if (pn[0] == 'd' /* dmacc */
1807 && (strncmp(tn, "dmult", 5) == 0
1808 || strncmp(tn, "dmacc", 5) == 0))
1813 /* Errata 24 - MT{LO,HI} after [D]MACC */
1814 if (strcmp (tn, "mtlo") == 0
1815 || strcmp (tn, "mthi") == 0)
1821 else if (strncmp(pn, "dmult", 5) == 0
1822 && (strncmp(tn, "dmult", 5) == 0
1823 || strncmp(tn, "dmacc", 5) == 0))
1825 /* Here is the rest of errata 23. */
1828 if (nops < min_nops)
1832 /* If we are being given a nop instruction, don't bother with
1833 one of the nops we would otherwise output. This will only
1834 happen when a nop instruction is used with mips_optimize set
1837 && ! mips_opts.noreorder
1838 && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0))
1841 /* Now emit the right number of NOP instructions. */
1842 if (nops > 0 && ! mips_opts.noreorder)
1845 unsigned long old_frag_offset;
1847 struct insn_label_list *l;
1849 old_frag = frag_now;
1850 old_frag_offset = frag_now_fix ();
1852 for (i = 0; i < nops; i++)
1857 listing_prev_line ();
1858 /* We may be at the start of a variant frag. In case we
1859 are, make sure there is enough space for the frag
1860 after the frags created by listing_prev_line. The
1861 argument to frag_grow here must be at least as large
1862 as the argument to all other calls to frag_grow in
1863 this file. We don't have to worry about being in the
1864 middle of a variant frag, because the variants insert
1865 all needed nop instructions themselves. */
1869 for (l = insn_labels; l != NULL; l = l->next)
1873 assert (S_GET_SEGMENT (l->label) == now_seg);
1874 symbol_set_frag (l->label, frag_now);
1875 val = (valueT) frag_now_fix ();
1876 /* mips16 text labels are stored as odd. */
1877 if (mips_opts.mips16)
1879 S_SET_VALUE (l->label, val);
1882 #ifndef NO_ECOFF_DEBUGGING
1883 if (ECOFF_DEBUGGING)
1884 ecoff_fix_loc (old_frag, old_frag_offset);
1887 else if (prev_nop_frag != NULL)
1889 /* We have a frag holding nops we may be able to remove. If
1890 we don't need any nops, we can decrease the size of
1891 prev_nop_frag by the size of one instruction. If we do
1892 need some nops, we count them in prev_nops_required. */
1893 if (prev_nop_frag_since == 0)
1897 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1898 --prev_nop_frag_holds;
1901 prev_nop_frag_required += nops;
1905 if (prev_prev_nop == 0)
1907 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1908 --prev_nop_frag_holds;
1911 ++prev_nop_frag_required;
1914 if (prev_nop_frag_holds <= prev_nop_frag_required)
1915 prev_nop_frag = NULL;
1917 ++prev_nop_frag_since;
1919 /* Sanity check: by the time we reach the second instruction
1920 after prev_nop_frag, we should have used up all the nops
1921 one way or another. */
1922 assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL);
1928 && *reloc_type == BFD_RELOC_16_PCREL_S2
1929 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
1930 || pinfo & INSN_COND_BRANCH_LIKELY)
1931 && mips_relax_branch
1932 /* Don't try branch relaxation within .set nomacro, or within
1933 .set noat if we use $at for PIC computations. If it turns
1934 out that the branch was out-of-range, we'll get an error. */
1935 && !mips_opts.warn_about_macros
1936 && !(mips_opts.noat && mips_pic != NO_PIC)
1937 && !mips_opts.mips16)
1939 f = frag_var (rs_machine_dependent,
1940 relaxed_branch_length
1942 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
1943 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4,
1945 (pinfo & INSN_UNCOND_BRANCH_DELAY,
1946 pinfo & INSN_COND_BRANCH_LIKELY,
1947 pinfo & INSN_WRITE_GPR_31,
1949 address_expr->X_add_symbol,
1950 address_expr->X_add_number,
1952 *reloc_type = BFD_RELOC_UNUSED;
1954 else if (*reloc_type > BFD_RELOC_UNUSED)
1956 /* We need to set up a variant frag. */
1957 assert (mips_opts.mips16 && address_expr != NULL);
1958 f = frag_var (rs_machine_dependent, 4, 0,
1959 RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED,
1960 mips16_small, mips16_ext,
1962 & INSN_UNCOND_BRANCH_DELAY),
1963 (*prev_insn_reloc_type
1964 == BFD_RELOC_MIPS16_JMP)),
1965 make_expr_symbol (address_expr), 0, NULL);
1967 else if (place != NULL)
1969 else if (mips_opts.mips16
1971 && *reloc_type != BFD_RELOC_MIPS16_JMP)
1973 /* Make sure there is enough room to swap this instruction with
1974 a following jump instruction. */
1980 if (mips_opts.mips16
1981 && mips_opts.noreorder
1982 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1983 as_warn (_("extended instruction in delay slot"));
1988 fixp[0] = fixp[1] = fixp[2] = NULL;
1989 if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED)
1991 if (address_expr->X_op == O_constant)
1995 switch (*reloc_type)
1998 ip->insn_opcode |= address_expr->X_add_number;
2001 case BFD_RELOC_MIPS_HIGHEST:
2002 tmp = (address_expr->X_add_number
2003 + ((valueT) 0x8000 << 32) + 0x80008000) >> 16;
2005 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2008 case BFD_RELOC_MIPS_HIGHER:
2009 tmp = (address_expr->X_add_number + 0x80008000) >> 16;
2010 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2013 case BFD_RELOC_HI16_S:
2014 ip->insn_opcode |= ((address_expr->X_add_number + 0x8000)
2018 case BFD_RELOC_HI16:
2019 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
2022 case BFD_RELOC_LO16:
2023 case BFD_RELOC_MIPS_GOT_DISP:
2024 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
2027 case BFD_RELOC_MIPS_JMP:
2028 if ((address_expr->X_add_number & 3) != 0)
2029 as_bad (_("jump to misaligned address (0x%lx)"),
2030 (unsigned long) address_expr->X_add_number);
2031 if (address_expr->X_add_number & ~0xfffffff)
2032 as_bad (_("jump address range overflow (0x%lx)"),
2033 (unsigned long) address_expr->X_add_number);
2034 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
2037 case BFD_RELOC_MIPS16_JMP:
2038 if ((address_expr->X_add_number & 3) != 0)
2039 as_bad (_("jump to misaligned address (0x%lx)"),
2040 (unsigned long) address_expr->X_add_number);
2041 if (address_expr->X_add_number & ~0xfffffff)
2042 as_bad (_("jump address range overflow (0x%lx)"),
2043 (unsigned long) address_expr->X_add_number);
2045 (((address_expr->X_add_number & 0x7c0000) << 3)
2046 | ((address_expr->X_add_number & 0xf800000) >> 7)
2047 | ((address_expr->X_add_number & 0x3fffc) >> 2));
2050 case BFD_RELOC_16_PCREL_S2:
2060 /* Don't generate a reloc if we are writing into a variant frag. */
2063 reloc_howto_type *howto;
2066 /* In a compound relocation, it is the final (outermost)
2067 operator that determines the relocated field. */
2068 for (i = 1; i < 3; i++)
2069 if (reloc_type[i] == BFD_RELOC_UNUSED)
2072 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
2073 fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal,
2074 bfd_get_reloc_size(howto),
2076 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
2079 /* These relocations can have an addend that won't fit in
2080 4 octets for 64bit assembly. */
2082 && ! howto->partial_inplace
2083 && (reloc_type[0] == BFD_RELOC_16
2084 || reloc_type[0] == BFD_RELOC_32
2085 || reloc_type[0] == BFD_RELOC_MIPS_JMP
2086 || reloc_type[0] == BFD_RELOC_HI16_S
2087 || reloc_type[0] == BFD_RELOC_LO16
2088 || reloc_type[0] == BFD_RELOC_GPREL16
2089 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
2090 || reloc_type[0] == BFD_RELOC_GPREL32
2091 || reloc_type[0] == BFD_RELOC_64
2092 || reloc_type[0] == BFD_RELOC_CTOR
2093 || reloc_type[0] == BFD_RELOC_MIPS_SUB
2094 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
2095 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
2096 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
2097 || reloc_type[0] == BFD_RELOC_MIPS_REL16
2098 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT))
2099 fixp[0]->fx_no_overflow = 1;
2101 if (reloc_needs_lo_p (*reloc_type))
2103 struct mips_hi_fixup *hi_fixup;
2105 /* Reuse the last entry if it already has a matching %lo. */
2106 hi_fixup = mips_hi_fixup_list;
2108 || !fixup_has_matching_lo_p (hi_fixup->fixp))
2110 hi_fixup = ((struct mips_hi_fixup *)
2111 xmalloc (sizeof (struct mips_hi_fixup)));
2112 hi_fixup->next = mips_hi_fixup_list;
2113 mips_hi_fixup_list = hi_fixup;
2115 hi_fixup->fixp = fixp[0];
2116 hi_fixup->seg = now_seg;
2119 /* Add fixups for the second and third relocations, if given.
2120 Note that the ABI allows the second relocation to be
2121 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2122 moment we only use RSS_UNDEF, but we could add support
2123 for the others if it ever becomes necessary. */
2124 for (i = 1; i < 3; i++)
2125 if (reloc_type[i] != BFD_RELOC_UNUSED)
2127 address_expr->X_op = O_absent;
2128 address_expr->X_add_symbol = 0;
2129 address_expr->X_add_number = 0;
2131 fixp[i] = fix_new_exp (frag_now, fixp[0]->fx_where,
2132 fixp[0]->fx_size, address_expr,
2133 FALSE, reloc_type[i]);
2139 if (! mips_opts.mips16)
2141 md_number_to_chars (f, ip->insn_opcode, 4);
2143 dwarf2_emit_insn (4);
2146 else if (*reloc_type == BFD_RELOC_MIPS16_JMP)
2148 md_number_to_chars (f, ip->insn_opcode >> 16, 2);
2149 md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2);
2151 dwarf2_emit_insn (4);
2158 md_number_to_chars (f, 0xf000 | ip->extend, 2);
2161 md_number_to_chars (f, ip->insn_opcode, 2);
2163 dwarf2_emit_insn (ip->use_extend ? 4 : 2);
2167 /* Update the register mask information. */
2168 if (! mips_opts.mips16)
2170 if (pinfo & INSN_WRITE_GPR_D)
2171 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD);
2172 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
2173 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT);
2174 if (pinfo & INSN_READ_GPR_S)
2175 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS);
2176 if (pinfo & INSN_WRITE_GPR_31)
2177 mips_gprmask |= 1 << RA;
2178 if (pinfo & INSN_WRITE_FPR_D)
2179 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD);
2180 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
2181 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS);
2182 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
2183 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT);
2184 if ((pinfo & INSN_READ_FPR_R) != 0)
2185 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR);
2186 if (pinfo & INSN_COP)
2188 /* We don't keep enough information to sort these cases out.
2189 The itbl support does keep this information however, although
2190 we currently don't support itbl fprmats as part of the cop
2191 instruction. May want to add this support in the future. */
2193 /* Never set the bit for $0, which is always zero. */
2194 mips_gprmask &= ~1 << 0;
2198 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
2199 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX)
2200 & MIPS16OP_MASK_RX);
2201 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
2202 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY)
2203 & MIPS16OP_MASK_RY);
2204 if (pinfo & MIPS16_INSN_WRITE_Z)
2205 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ)
2206 & MIPS16OP_MASK_RZ);
2207 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
2208 mips_gprmask |= 1 << TREG;
2209 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
2210 mips_gprmask |= 1 << SP;
2211 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
2212 mips_gprmask |= 1 << RA;
2213 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2214 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2215 if (pinfo & MIPS16_INSN_READ_Z)
2216 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
2217 & MIPS16OP_MASK_MOVE32Z);
2218 if (pinfo & MIPS16_INSN_READ_GPR_X)
2219 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
2220 & MIPS16OP_MASK_REGR32);
2223 if (place == NULL && ! mips_opts.noreorder)
2225 /* Filling the branch delay slot is more complex. We try to
2226 switch the branch with the previous instruction, which we can
2227 do if the previous instruction does not set up a condition
2228 that the branch tests and if the branch is not itself the
2229 target of any branch. */
2230 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
2231 || (pinfo & INSN_COND_BRANCH_DELAY))
2233 if (mips_optimize < 2
2234 /* If we have seen .set volatile or .set nomove, don't
2236 || mips_opts.nomove != 0
2237 /* If we had to emit any NOP instructions, then we
2238 already know we can not swap. */
2240 /* If we don't even know the previous insn, we can not
2242 || ! prev_insn_valid
2243 /* If the previous insn is already in a branch delay
2244 slot, then we can not swap. */
2245 || prev_insn_is_delay_slot
2246 /* If the previous previous insn was in a .set
2247 noreorder, we can't swap. Actually, the MIPS
2248 assembler will swap in this situation. However, gcc
2249 configured -with-gnu-as will generate code like
2255 in which we can not swap the bne and INSN. If gcc is
2256 not configured -with-gnu-as, it does not output the
2257 .set pseudo-ops. We don't have to check
2258 prev_insn_unreordered, because prev_insn_valid will
2259 be 0 in that case. We don't want to use
2260 prev_prev_insn_valid, because we do want to be able
2261 to swap at the start of a function. */
2262 || prev_prev_insn_unreordered
2263 /* If the branch is itself the target of a branch, we
2264 can not swap. We cheat on this; all we check for is
2265 whether there is a label on this instruction. If
2266 there are any branches to anything other than a
2267 label, users must use .set noreorder. */
2268 || insn_labels != NULL
2269 /* If the previous instruction is in a variant frag, we
2270 can not do the swap. This does not apply to the
2271 mips16, which uses variant frags for different
2273 || (! mips_opts.mips16
2274 && prev_insn_frag->fr_type == rs_machine_dependent)
2275 /* If the branch reads the condition codes, we don't
2276 even try to swap, because in the sequence
2281 we can not swap, and I don't feel like handling that
2283 || (! mips_opts.mips16
2284 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2285 && (pinfo & INSN_READ_COND_CODE))
2286 /* We can not swap with an instruction that requires a
2287 delay slot, becase the target of the branch might
2288 interfere with that instruction. */
2289 || (! mips_opts.mips16
2290 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2292 /* Itbl support may require additional care here. */
2293 & (INSN_LOAD_COPROC_DELAY
2294 | INSN_COPROC_MOVE_DELAY
2295 | INSN_WRITE_COND_CODE)))
2296 || (! (hilo_interlocks
2297 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
2301 || (! mips_opts.mips16
2303 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))
2304 || (! mips_opts.mips16
2305 && mips_opts.isa == ISA_MIPS1
2306 /* Itbl support may require additional care here. */
2307 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))
2308 /* We can not swap with a branch instruction. */
2310 & (INSN_UNCOND_BRANCH_DELAY
2311 | INSN_COND_BRANCH_DELAY
2312 | INSN_COND_BRANCH_LIKELY))
2313 /* We do not swap with a trap instruction, since it
2314 complicates trap handlers to have the trap
2315 instruction be in a delay slot. */
2316 || (prev_pinfo & INSN_TRAP)
2317 /* If the branch reads a register that the previous
2318 instruction sets, we can not swap. */
2319 || (! mips_opts.mips16
2320 && (prev_pinfo & INSN_WRITE_GPR_T)
2321 && insn_uses_reg (ip,
2322 ((prev_insn.insn_opcode >> OP_SH_RT)
2325 || (! mips_opts.mips16
2326 && (prev_pinfo & INSN_WRITE_GPR_D)
2327 && insn_uses_reg (ip,
2328 ((prev_insn.insn_opcode >> OP_SH_RD)
2331 || (mips_opts.mips16
2332 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
2333 && insn_uses_reg (ip,
2334 ((prev_insn.insn_opcode
2336 & MIPS16OP_MASK_RX),
2338 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
2339 && insn_uses_reg (ip,
2340 ((prev_insn.insn_opcode
2342 & MIPS16OP_MASK_RY),
2344 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
2345 && insn_uses_reg (ip,
2346 ((prev_insn.insn_opcode
2348 & MIPS16OP_MASK_RZ),
2350 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
2351 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
2352 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
2353 && insn_uses_reg (ip, RA, MIPS_GR_REG))
2354 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2355 && insn_uses_reg (ip,
2356 MIPS16OP_EXTRACT_REG32R (prev_insn.
2359 /* If the branch writes a register that the previous
2360 instruction sets, we can not swap (we know that
2361 branches write only to RD or to $31). */
2362 || (! mips_opts.mips16
2363 && (prev_pinfo & INSN_WRITE_GPR_T)
2364 && (((pinfo & INSN_WRITE_GPR_D)
2365 && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)
2366 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2367 || ((pinfo & INSN_WRITE_GPR_31)
2368 && (((prev_insn.insn_opcode >> OP_SH_RT)
2371 || (! mips_opts.mips16
2372 && (prev_pinfo & INSN_WRITE_GPR_D)
2373 && (((pinfo & INSN_WRITE_GPR_D)
2374 && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD)
2375 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2376 || ((pinfo & INSN_WRITE_GPR_31)
2377 && (((prev_insn.insn_opcode >> OP_SH_RD)
2380 || (mips_opts.mips16
2381 && (pinfo & MIPS16_INSN_WRITE_31)
2382 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
2383 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2384 && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode)
2386 /* If the branch writes a register that the previous
2387 instruction reads, we can not swap (we know that
2388 branches only write to RD or to $31). */
2389 || (! mips_opts.mips16
2390 && (pinfo & INSN_WRITE_GPR_D)
2391 && insn_uses_reg (&prev_insn,
2392 ((ip->insn_opcode >> OP_SH_RD)
2395 || (! mips_opts.mips16
2396 && (pinfo & INSN_WRITE_GPR_31)
2397 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2398 || (mips_opts.mips16
2399 && (pinfo & MIPS16_INSN_WRITE_31)
2400 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2401 /* If we are generating embedded PIC code, the branch
2402 might be expanded into a sequence which uses $at, so
2403 we can't swap with an instruction which reads it. */
2404 || (mips_pic == EMBEDDED_PIC
2405 && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG))
2406 /* If the previous previous instruction has a load
2407 delay, and sets a register that the branch reads, we
2409 || (! mips_opts.mips16
2410 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2411 /* Itbl support may require additional care here. */
2412 && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
2413 || (! gpr_interlocks
2414 && (prev_prev_insn.insn_mo->pinfo
2415 & INSN_LOAD_MEMORY_DELAY)))
2416 && insn_uses_reg (ip,
2417 ((prev_prev_insn.insn_opcode >> OP_SH_RT)
2420 /* If one instruction sets a condition code and the
2421 other one uses a condition code, we can not swap. */
2422 || ((pinfo & INSN_READ_COND_CODE)
2423 && (prev_pinfo & INSN_WRITE_COND_CODE))
2424 || ((pinfo & INSN_WRITE_COND_CODE)
2425 && (prev_pinfo & INSN_READ_COND_CODE))
2426 /* If the previous instruction uses the PC, we can not
2428 || (mips_opts.mips16
2429 && (prev_pinfo & MIPS16_INSN_READ_PC))
2430 /* If the previous instruction was extended, we can not
2432 || (mips_opts.mips16 && prev_insn_extended)
2433 /* If the previous instruction had a fixup in mips16
2434 mode, we can not swap. This normally means that the
2435 previous instruction was a 4 byte branch anyhow. */
2436 || (mips_opts.mips16 && prev_insn_fixp[0])
2437 /* If the previous instruction is a sync, sync.l, or
2438 sync.p, we can not swap. */
2439 || (prev_pinfo & INSN_SYNC))
2441 /* We could do even better for unconditional branches to
2442 portions of this object file; we could pick up the
2443 instruction at the destination, put it in the delay
2444 slot, and bump the destination address. */
2446 /* Update the previous insn information. */
2447 prev_prev_insn = *ip;
2448 prev_insn.insn_mo = &dummy_opcode;
2452 /* It looks like we can actually do the swap. */
2453 if (! mips_opts.mips16)
2458 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2459 memcpy (temp, prev_f, 4);
2460 memcpy (prev_f, f, 4);
2461 memcpy (f, temp, 4);
2462 if (prev_insn_fixp[0])
2464 prev_insn_fixp[0]->fx_frag = frag_now;
2465 prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal;
2467 if (prev_insn_fixp[1])
2469 prev_insn_fixp[1]->fx_frag = frag_now;
2470 prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal;
2472 if (prev_insn_fixp[2])
2474 prev_insn_fixp[2]->fx_frag = frag_now;
2475 prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal;
2477 if (prev_insn_fixp[0] && HAVE_NEWABI
2478 && prev_insn_frag != frag_now
2479 && (prev_insn_fixp[0]->fx_r_type
2480 == BFD_RELOC_MIPS_GOT_DISP
2481 || (prev_insn_fixp[0]->fx_r_type
2482 == BFD_RELOC_MIPS_CALL16)))
2484 /* To avoid confusion in tc_gen_reloc, we must
2485 ensure that this does not become a variant
2487 force_new_frag = TRUE;
2491 fixp[0]->fx_frag = prev_insn_frag;
2492 fixp[0]->fx_where = prev_insn_where;
2496 fixp[1]->fx_frag = prev_insn_frag;
2497 fixp[1]->fx_where = prev_insn_where;
2501 fixp[2]->fx_frag = prev_insn_frag;
2502 fixp[2]->fx_where = prev_insn_where;
2510 assert (prev_insn_fixp[0] == NULL);
2511 assert (prev_insn_fixp[1] == NULL);
2512 assert (prev_insn_fixp[2] == NULL);
2513 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2514 memcpy (temp, prev_f, 2);
2515 memcpy (prev_f, f, 2);
2516 if (*reloc_type != BFD_RELOC_MIPS16_JMP)
2518 assert (*reloc_type == BFD_RELOC_UNUSED);
2519 memcpy (f, temp, 2);
2523 memcpy (f, f + 2, 2);
2524 memcpy (f + 2, temp, 2);
2528 fixp[0]->fx_frag = prev_insn_frag;
2529 fixp[0]->fx_where = prev_insn_where;
2533 fixp[1]->fx_frag = prev_insn_frag;
2534 fixp[1]->fx_where = prev_insn_where;
2538 fixp[2]->fx_frag = prev_insn_frag;
2539 fixp[2]->fx_where = prev_insn_where;
2543 /* Update the previous insn information; leave prev_insn
2545 prev_prev_insn = *ip;
2547 prev_insn_is_delay_slot = 1;
2549 /* If that was an unconditional branch, forget the previous
2550 insn information. */
2551 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
2553 prev_prev_insn.insn_mo = &dummy_opcode;
2554 prev_insn.insn_mo = &dummy_opcode;
2557 prev_insn_fixp[0] = NULL;
2558 prev_insn_fixp[1] = NULL;
2559 prev_insn_fixp[2] = NULL;
2560 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2561 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2562 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2563 prev_insn_extended = 0;
2565 else if (pinfo & INSN_COND_BRANCH_LIKELY)
2567 /* We don't yet optimize a branch likely. What we should do
2568 is look at the target, copy the instruction found there
2569 into the delay slot, and increment the branch to jump to
2570 the next instruction. */
2572 /* Update the previous insn information. */
2573 prev_prev_insn = *ip;
2574 prev_insn.insn_mo = &dummy_opcode;
2575 prev_insn_fixp[0] = NULL;
2576 prev_insn_fixp[1] = NULL;
2577 prev_insn_fixp[2] = NULL;
2578 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2579 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2580 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2581 prev_insn_extended = 0;
2585 /* Update the previous insn information. */
2587 prev_prev_insn.insn_mo = &dummy_opcode;
2589 prev_prev_insn = prev_insn;
2592 /* Any time we see a branch, we always fill the delay slot
2593 immediately; since this insn is not a branch, we know it
2594 is not in a delay slot. */
2595 prev_insn_is_delay_slot = 0;
2597 prev_insn_fixp[0] = fixp[0];
2598 prev_insn_fixp[1] = fixp[1];
2599 prev_insn_fixp[2] = fixp[2];
2600 prev_insn_reloc_type[0] = reloc_type[0];
2601 prev_insn_reloc_type[1] = reloc_type[1];
2602 prev_insn_reloc_type[2] = reloc_type[2];
2603 if (mips_opts.mips16)
2604 prev_insn_extended = (ip->use_extend
2605 || *reloc_type > BFD_RELOC_UNUSED);
2608 prev_prev_insn_unreordered = prev_insn_unreordered;
2609 prev_insn_unreordered = 0;
2610 prev_insn_frag = frag_now;
2611 prev_insn_where = f - frag_now->fr_literal;
2612 prev_insn_valid = 1;
2614 else if (place == NULL)
2616 /* We need to record a bit of information even when we are not
2617 reordering, in order to determine the base address for mips16
2618 PC relative relocs. */
2619 prev_prev_insn = prev_insn;
2621 prev_insn_reloc_type[0] = reloc_type[0];
2622 prev_insn_reloc_type[1] = reloc_type[1];
2623 prev_insn_reloc_type[2] = reloc_type[2];
2624 prev_prev_insn_unreordered = prev_insn_unreordered;
2625 prev_insn_unreordered = 1;
2628 /* We just output an insn, so the next one doesn't have a label. */
2629 mips_clear_insn_labels ();
2631 /* We must ensure that the frag to which an instruction that was
2632 moved from a non-variant frag doesn't become a variant frag,
2633 otherwise tc_gen_reloc may get confused. */
2636 frag_wane (frag_now);
2641 /* This function forgets that there was any previous instruction or
2642 label. If PRESERVE is non-zero, it remembers enough information to
2643 know whether nops are needed before a noreorder section. */
2646 mips_no_prev_insn (int preserve)
2650 prev_insn.insn_mo = &dummy_opcode;
2651 prev_prev_insn.insn_mo = &dummy_opcode;
2652 prev_nop_frag = NULL;
2653 prev_nop_frag_holds = 0;
2654 prev_nop_frag_required = 0;
2655 prev_nop_frag_since = 0;
2657 prev_insn_valid = 0;
2658 prev_insn_is_delay_slot = 0;
2659 prev_insn_unreordered = 0;
2660 prev_insn_extended = 0;
2661 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2662 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2663 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2664 prev_prev_insn_unreordered = 0;
2665 mips_clear_insn_labels ();
2668 /* This function must be called whenever we turn on noreorder or emit
2669 something other than instructions. It inserts any NOPS which might
2670 be needed by the previous instruction, and clears the information
2671 kept for the previous instructions. The INSNS parameter is true if
2672 instructions are to follow. */
2675 mips_emit_delays (bfd_boolean insns)
2677 if (! mips_opts.noreorder)
2682 if ((! mips_opts.mips16
2683 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2684 && (! cop_interlocks
2685 && (prev_insn.insn_mo->pinfo
2686 & (INSN_LOAD_COPROC_DELAY
2687 | INSN_COPROC_MOVE_DELAY
2688 | INSN_WRITE_COND_CODE))))
2689 || (! hilo_interlocks
2690 && (prev_insn.insn_mo->pinfo
2693 || (! mips_opts.mips16
2695 && (prev_insn.insn_mo->pinfo
2696 & INSN_LOAD_MEMORY_DELAY))
2697 || (! mips_opts.mips16
2698 && mips_opts.isa == ISA_MIPS1
2699 && (prev_insn.insn_mo->pinfo
2700 & INSN_COPROC_MEMORY_DELAY)))
2702 /* Itbl support may require additional care here. */
2704 if ((! mips_opts.mips16
2705 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2706 && (! cop_interlocks
2707 && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
2708 || (! hilo_interlocks
2709 && ((prev_insn.insn_mo->pinfo & INSN_READ_HI)
2710 || (prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2713 if (prev_insn_unreordered)
2716 else if ((! mips_opts.mips16
2717 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2718 && (! cop_interlocks
2719 && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
2720 || (! hilo_interlocks
2721 && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
2722 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2724 /* Itbl support may require additional care here. */
2725 if (! prev_prev_insn_unreordered)
2729 if (mips_fix_4122_bugs && prev_insn.insn_mo->name)
2732 const char *pn = prev_insn.insn_mo->name;
2733 if (strncmp(pn, "macc", 4) == 0
2734 || strncmp(pn, "dmacc", 5) == 0
2735 || strncmp(pn, "dmult", 5) == 0)
2739 if (nops < min_nops)
2745 struct insn_label_list *l;
2749 /* Record the frag which holds the nop instructions, so
2750 that we can remove them if we don't need them. */
2751 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
2752 prev_nop_frag = frag_now;
2753 prev_nop_frag_holds = nops;
2754 prev_nop_frag_required = 0;
2755 prev_nop_frag_since = 0;
2758 for (; nops > 0; --nops)
2763 /* Move on to a new frag, so that it is safe to simply
2764 decrease the size of prev_nop_frag. */
2765 frag_wane (frag_now);
2769 for (l = insn_labels; l != NULL; l = l->next)
2773 assert (S_GET_SEGMENT (l->label) == now_seg);
2774 symbol_set_frag (l->label, frag_now);
2775 val = (valueT) frag_now_fix ();
2776 /* mips16 text labels are stored as odd. */
2777 if (mips_opts.mips16)
2779 S_SET_VALUE (l->label, val);
2784 /* Mark instruction labels in mips16 mode. */
2786 mips16_mark_labels ();
2788 mips_no_prev_insn (insns);
2791 /* Build an instruction created by a macro expansion. This is passed
2792 a pointer to the count of instructions created so far, an
2793 expression, the name of the instruction to build, an operand format
2794 string, and corresponding arguments. */
2797 macro_build (char *place, int *counter, expressionS *ep, const char *name,
2798 const char *fmt, ...)
2800 struct mips_cl_insn insn;
2801 bfd_reloc_code_real_type r[3];
2804 va_start (args, fmt);
2807 * If the macro is about to expand into a second instruction,
2808 * print a warning if needed. We need to pass ip as a parameter
2809 * to generate a better warning message here...
2811 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
2812 as_warn (_("Macro instruction expanded into multiple instructions"));
2815 * If the macro is about to expand into a second instruction,
2816 * and it is in a delay slot, print a warning.
2820 && mips_opts.noreorder
2821 && (prev_prev_insn.insn_mo->pinfo
2822 & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY
2823 | INSN_COND_BRANCH_LIKELY)) != 0)
2824 as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot"));
2827 ++*counter; /* bump instruction counter */
2829 if (mips_opts.mips16)
2831 mips16_macro_build (place, counter, ep, name, fmt, args);
2836 r[0] = BFD_RELOC_UNUSED;
2837 r[1] = BFD_RELOC_UNUSED;
2838 r[2] = BFD_RELOC_UNUSED;
2839 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
2840 assert (insn.insn_mo);
2841 assert (strcmp (name, insn.insn_mo->name) == 0);
2843 /* Search until we get a match for NAME. */
2846 /* It is assumed here that macros will never generate
2847 MDMX or MIPS-3D instructions. */
2848 if (strcmp (fmt, insn.insn_mo->args) == 0
2849 && insn.insn_mo->pinfo != INSN_MACRO
2850 && OPCODE_IS_MEMBER (insn.insn_mo,
2852 | (file_ase_mips16 ? INSN_MIPS16 : 0)),
2854 && (mips_opts.arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
2858 assert (insn.insn_mo->name);
2859 assert (strcmp (name, insn.insn_mo->name) == 0);
2862 insn.insn_opcode = insn.insn_mo->match;
2878 insn.insn_opcode |= va_arg (args, int) << OP_SH_RT;
2882 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE;
2887 insn.insn_opcode |= va_arg (args, int) << OP_SH_FT;
2893 insn.insn_opcode |= va_arg (args, int) << OP_SH_RD;
2898 int tmp = va_arg (args, int);
2900 insn.insn_opcode |= tmp << OP_SH_RT;
2901 insn.insn_opcode |= tmp << OP_SH_RD;
2907 insn.insn_opcode |= va_arg (args, int) << OP_SH_FS;
2914 insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT;
2918 insn.insn_opcode |= va_arg (args, int) << OP_SH_FD;
2922 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20;
2926 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19;
2930 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2;
2937 insn.insn_opcode |= va_arg (args, int) << OP_SH_RS;
2943 *r = (bfd_reloc_code_real_type) va_arg (args, int);
2944 assert (*r == BFD_RELOC_GPREL16
2945 || *r == BFD_RELOC_MIPS_LITERAL
2946 || *r == BFD_RELOC_MIPS_HIGHER
2947 || *r == BFD_RELOC_HI16_S
2948 || *r == BFD_RELOC_LO16
2949 || *r == BFD_RELOC_MIPS_GOT16
2950 || *r == BFD_RELOC_MIPS_CALL16
2951 || *r == BFD_RELOC_MIPS_GOT_DISP
2952 || *r == BFD_RELOC_MIPS_GOT_PAGE
2953 || *r == BFD_RELOC_MIPS_GOT_OFST
2954 || *r == BFD_RELOC_MIPS_GOT_LO16
2955 || *r == BFD_RELOC_MIPS_CALL_LO16
2956 || (ep->X_op == O_subtract
2957 && *r == BFD_RELOC_PCREL_LO16));
2961 *r = (bfd_reloc_code_real_type) va_arg (args, int);
2963 && (ep->X_op == O_constant
2964 || (ep->X_op == O_symbol
2965 && (*r == BFD_RELOC_MIPS_HIGHEST
2966 || *r == BFD_RELOC_HI16_S
2967 || *r == BFD_RELOC_HI16
2968 || *r == BFD_RELOC_GPREL16
2969 || *r == BFD_RELOC_MIPS_GOT_HI16
2970 || *r == BFD_RELOC_MIPS_CALL_HI16))
2971 || (ep->X_op == O_subtract
2972 && *r == BFD_RELOC_PCREL_HI16_S)));
2976 assert (ep != NULL);
2978 * This allows macro() to pass an immediate expression for
2979 * creating short branches without creating a symbol.
2980 * Note that the expression still might come from the assembly
2981 * input, in which case the value is not checked for range nor
2982 * is a relocation entry generated (yuck).
2984 if (ep->X_op == O_constant)
2986 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
2990 *r = BFD_RELOC_16_PCREL_S2;
2994 assert (ep != NULL);
2995 *r = BFD_RELOC_MIPS_JMP;
2999 insn.insn_opcode |= va_arg (args, unsigned long);
3008 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3010 append_insn (place, &insn, ep, r);
3014 mips16_macro_build (char *place, int *counter ATTRIBUTE_UNUSED,
3015 expressionS *ep, const char *name, const char *fmt,
3018 struct mips_cl_insn insn;
3019 bfd_reloc_code_real_type r[3]
3020 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3022 insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
3023 assert (insn.insn_mo);
3024 assert (strcmp (name, insn.insn_mo->name) == 0);
3026 while (strcmp (fmt, insn.insn_mo->args) != 0
3027 || insn.insn_mo->pinfo == INSN_MACRO)
3030 assert (insn.insn_mo->name);
3031 assert (strcmp (name, insn.insn_mo->name) == 0);
3034 insn.insn_opcode = insn.insn_mo->match;
3035 insn.use_extend = FALSE;
3054 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY;
3059 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX;
3063 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ;
3067 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z;
3077 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32;
3084 regno = va_arg (args, int);
3085 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
3086 insn.insn_opcode |= regno << MIPS16OP_SH_REG32R;
3107 assert (ep != NULL);
3109 if (ep->X_op != O_constant)
3110 *r = (int) BFD_RELOC_UNUSED + c;
3113 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
3114 FALSE, &insn.insn_opcode, &insn.use_extend,
3117 *r = BFD_RELOC_UNUSED;
3123 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6;
3130 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3132 append_insn (place, &insn, ep, r);
3136 * Generate a "jalr" instruction with a relocation hint to the called
3137 * function. This occurs in NewABI PIC code.
3140 macro_build_jalr (int icnt, expressionS *ep)
3149 macro_build (NULL, &icnt, NULL, "jalr", "d,s", RA, PIC_CALL_REG);
3151 fix_new_exp (frag_now, f - frag_now->fr_literal,
3152 4, ep, FALSE, BFD_RELOC_MIPS_JALR);
3156 * Generate a "lui" instruction.
3159 macro_build_lui (char *place, int *counter, expressionS *ep, int regnum)
3161 expressionS high_expr;
3162 struct mips_cl_insn insn;
3163 bfd_reloc_code_real_type r[3]
3164 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3165 const char *name = "lui";
3166 const char *fmt = "t,u";
3168 assert (! mips_opts.mips16);
3174 high_expr.X_op = O_constant;
3175 high_expr.X_add_number = ep->X_add_number;
3178 if (high_expr.X_op == O_constant)
3180 /* we can compute the instruction now without a relocation entry */
3181 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
3183 *r = BFD_RELOC_UNUSED;
3187 assert (ep->X_op == O_symbol);
3188 /* _gp_disp is a special case, used from s_cpload. */
3189 assert (mips_pic == NO_PIC
3191 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0));
3192 *r = BFD_RELOC_HI16_S;
3196 * If the macro is about to expand into a second instruction,
3197 * print a warning if needed. We need to pass ip as a parameter
3198 * to generate a better warning message here...
3200 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
3201 as_warn (_("Macro instruction expanded into multiple instructions"));
3204 ++*counter; /* bump instruction counter */
3206 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
3207 assert (insn.insn_mo);
3208 assert (strcmp (name, insn.insn_mo->name) == 0);
3209 assert (strcmp (fmt, insn.insn_mo->args) == 0);
3211 insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT);
3212 if (*r == BFD_RELOC_UNUSED)
3214 insn.insn_opcode |= high_expr.X_add_number;
3215 append_insn (place, &insn, NULL, r);
3218 append_insn (place, &insn, &high_expr, r);
3221 /* Generate a sequence of instructions to do a load or store from a constant
3222 offset off of a base register (breg) into/from a target register (treg),
3223 using AT if necessary. */
3225 macro_build_ldst_constoffset (char *place, int *counter, expressionS *ep,
3226 const char *op, int treg, int breg, int dbl)
3228 assert (ep->X_op == O_constant);
3230 /* Sign-extending 32-bit constants makes their handling easier. */
3233 if (ep->X_add_number & ~((bfd_vma) 0xffffffff)
3234 && ~(ep->X_add_number | 0xffffffff))
3235 as_bad (_("too large constant specified"));
3237 ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000)
3241 /* Right now, this routine can only handle signed 32-bit contants. */
3242 if (! IS_SEXT_32BIT_NUM(ep->X_add_number))
3243 as_warn (_("operand overflow"));
3245 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
3247 /* Signed 16-bit offset will fit in the op. Easy! */
3248 macro_build (place, counter, ep, op, "t,o(b)", treg, BFD_RELOC_LO16,
3253 /* 32-bit offset, need multiple instructions and AT, like:
3254 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3255 addu $tempreg,$tempreg,$breg
3256 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3257 to handle the complete offset. */
3258 macro_build_lui (place, counter, ep, AT);
3261 macro_build (place, counter, NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT,
3265 macro_build (place, counter, ep, op, "t,o(b)", treg, BFD_RELOC_LO16,
3269 as_warn (_("Macro used $at after \".set noat\""));
3274 * Generates code to set the $at register to true (one)
3275 * if reg is less than the immediate expression.
3278 set_at (int *counter, int reg, int unsignedp)
3280 if (imm_expr.X_op == O_constant
3281 && imm_expr.X_add_number >= -0x8000
3282 && imm_expr.X_add_number < 0x8000)
3283 macro_build (NULL, counter, &imm_expr, unsignedp ? "sltiu" : "slti",
3284 "t,r,j", AT, reg, BFD_RELOC_LO16);
3287 load_register (counter, AT, &imm_expr, HAVE_64BIT_GPRS);
3288 macro_build (NULL, counter, NULL, unsignedp ? "sltu" : "slt",
3289 "d,v,t", AT, reg, AT);
3293 /* Warn if an expression is not a constant. */
3296 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
3298 if (ex->X_op == O_big)
3299 as_bad (_("unsupported large constant"));
3300 else if (ex->X_op != O_constant)
3301 as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name);
3304 /* Count the leading zeroes by performing a binary chop. This is a
3305 bulky bit of source, but performance is a LOT better for the
3306 majority of values than a simple loop to count the bits:
3307 for (lcnt = 0; (lcnt < 32); lcnt++)
3308 if ((v) & (1 << (31 - lcnt)))
3310 However it is not code size friendly, and the gain will drop a bit
3311 on certain cached systems.
3313 #define COUNT_TOP_ZEROES(v) \
3314 (((v) & ~0xffff) == 0 \
3315 ? ((v) & ~0xff) == 0 \
3316 ? ((v) & ~0xf) == 0 \
3317 ? ((v) & ~0x3) == 0 \
3318 ? ((v) & ~0x1) == 0 \
3323 : ((v) & ~0x7) == 0 \
3326 : ((v) & ~0x3f) == 0 \
3327 ? ((v) & ~0x1f) == 0 \
3330 : ((v) & ~0x7f) == 0 \
3333 : ((v) & ~0xfff) == 0 \
3334 ? ((v) & ~0x3ff) == 0 \
3335 ? ((v) & ~0x1ff) == 0 \
3338 : ((v) & ~0x7ff) == 0 \
3341 : ((v) & ~0x3fff) == 0 \
3342 ? ((v) & ~0x1fff) == 0 \
3345 : ((v) & ~0x7fff) == 0 \
3348 : ((v) & ~0xffffff) == 0 \
3349 ? ((v) & ~0xfffff) == 0 \
3350 ? ((v) & ~0x3ffff) == 0 \
3351 ? ((v) & ~0x1ffff) == 0 \
3354 : ((v) & ~0x7ffff) == 0 \
3357 : ((v) & ~0x3fffff) == 0 \
3358 ? ((v) & ~0x1fffff) == 0 \
3361 : ((v) & ~0x7fffff) == 0 \
3364 : ((v) & ~0xfffffff) == 0 \
3365 ? ((v) & ~0x3ffffff) == 0 \
3366 ? ((v) & ~0x1ffffff) == 0 \
3369 : ((v) & ~0x7ffffff) == 0 \
3372 : ((v) & ~0x3fffffff) == 0 \
3373 ? ((v) & ~0x1fffffff) == 0 \
3376 : ((v) & ~0x7fffffff) == 0 \
3381 * This routine generates the least number of instructions neccessary to load
3382 * an absolute expression value into a register.
3385 load_register (int *counter, int reg, expressionS *ep, int dbl)
3388 expressionS hi32, lo32;
3390 if (ep->X_op != O_big)
3392 assert (ep->X_op == O_constant);
3394 /* Sign-extending 32-bit constants makes their handling easier. */
3397 if (ep->X_add_number & ~((bfd_vma) 0xffffffff)
3398 && ~(ep->X_add_number | 0xffffffff))
3399 as_bad (_("too large constant specified"));
3401 ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000)
3405 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
3407 /* We can handle 16 bit signed values with an addiu to
3408 $zero. No need to ever use daddiu here, since $zero and
3409 the result are always correct in 32 bit mode. */
3410 macro_build (NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3414 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
3416 /* We can handle 16 bit unsigned values with an ori to
3418 macro_build (NULL, counter, ep, "ori", "t,r,i", reg, 0,
3422 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
3424 /* 32 bit values require an lui. */
3425 macro_build (NULL, counter, ep, "lui", "t,u", reg, BFD_RELOC_HI16);
3426 if ((ep->X_add_number & 0xffff) != 0)
3427 macro_build (NULL, counter, ep, "ori", "t,r,i", reg, reg,
3433 /* The value is larger than 32 bits. */
3435 if (HAVE_32BIT_GPRS)
3437 as_bad (_("Number (0x%lx) larger than 32 bits"),
3438 (unsigned long) ep->X_add_number);
3439 macro_build (NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3444 if (ep->X_op != O_big)
3447 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3448 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3449 hi32.X_add_number &= 0xffffffff;
3451 lo32.X_add_number &= 0xffffffff;
3455 assert (ep->X_add_number > 2);
3456 if (ep->X_add_number == 3)
3457 generic_bignum[3] = 0;
3458 else if (ep->X_add_number > 4)
3459 as_bad (_("Number larger than 64 bits"));
3460 lo32.X_op = O_constant;
3461 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
3462 hi32.X_op = O_constant;
3463 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
3466 if (hi32.X_add_number == 0)
3471 unsigned long hi, lo;
3473 if (hi32.X_add_number == (offsetT) 0xffffffff)
3475 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
3477 macro_build (NULL, counter, &lo32, "addiu", "t,r,j", reg, 0,
3481 if (lo32.X_add_number & 0x80000000)
3483 macro_build (NULL, counter, &lo32, "lui", "t,u", reg,
3485 if (lo32.X_add_number & 0xffff)
3486 macro_build (NULL, counter, &lo32, "ori", "t,r,i", reg, reg,
3492 /* Check for 16bit shifted constant. We know that hi32 is
3493 non-zero, so start the mask on the first bit of the hi32
3498 unsigned long himask, lomask;
3502 himask = 0xffff >> (32 - shift);
3503 lomask = (0xffff << shift) & 0xffffffff;
3507 himask = 0xffff << (shift - 32);
3510 if ((hi32.X_add_number & ~(offsetT) himask) == 0
3511 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
3515 tmp.X_op = O_constant;
3517 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
3518 | (lo32.X_add_number >> shift));
3520 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
3521 macro_build (NULL, counter, &tmp, "ori", "t,r,i", reg, 0,
3523 macro_build (NULL, counter, NULL,
3524 (shift >= 32) ? "dsll32" : "dsll",
3526 (shift >= 32) ? shift - 32 : shift);
3531 while (shift <= (64 - 16));
3533 /* Find the bit number of the lowest one bit, and store the
3534 shifted value in hi/lo. */
3535 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
3536 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
3540 while ((lo & 1) == 0)
3545 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
3551 while ((hi & 1) == 0)
3560 /* Optimize if the shifted value is a (power of 2) - 1. */
3561 if ((hi == 0 && ((lo + 1) & lo) == 0)
3562 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
3564 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
3569 /* This instruction will set the register to be all
3571 tmp.X_op = O_constant;
3572 tmp.X_add_number = (offsetT) -1;
3573 macro_build (NULL, counter, &tmp, "addiu", "t,r,j", reg, 0,
3578 macro_build (NULL, counter, NULL,
3579 (bit >= 32) ? "dsll32" : "dsll",
3581 (bit >= 32) ? bit - 32 : bit);
3583 macro_build (NULL, counter, NULL,
3584 (shift >= 32) ? "dsrl32" : "dsrl",
3586 (shift >= 32) ? shift - 32 : shift);
3591 /* Sign extend hi32 before calling load_register, because we can
3592 generally get better code when we load a sign extended value. */
3593 if ((hi32.X_add_number & 0x80000000) != 0)
3594 hi32.X_add_number |= ~(offsetT) 0xffffffff;
3595 load_register (counter, reg, &hi32, 0);
3598 if ((lo32.X_add_number & 0xffff0000) == 0)
3602 macro_build (NULL, counter, NULL, "dsll32", "d,w,<", reg, freg, 0);
3610 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
3612 macro_build (NULL, counter, &lo32, "lui", "t,u", reg,
3614 macro_build (NULL, counter, NULL, "dsrl32", "d,w,<", reg, reg, 0);
3620 macro_build (NULL, counter, NULL, "dsll", "d,w,<", reg, freg, 16);
3624 mid16.X_add_number >>= 16;
3625 macro_build (NULL, counter, &mid16, "ori", "t,r,i", reg, freg,
3627 macro_build (NULL, counter, NULL, "dsll", "d,w,<", reg, reg, 16);
3630 if ((lo32.X_add_number & 0xffff) != 0)
3631 macro_build (NULL, counter, &lo32, "ori", "t,r,i", reg, freg,
3635 /* Load an address into a register. */
3638 load_address (int *counter, int reg, expressionS *ep, int *used_at)
3642 if (ep->X_op != O_constant
3643 && ep->X_op != O_symbol)
3645 as_bad (_("expression too complex"));
3646 ep->X_op = O_constant;
3649 if (ep->X_op == O_constant)
3651 load_register (counter, reg, ep, HAVE_64BIT_ADDRESSES);
3655 if (mips_pic == NO_PIC)
3657 /* If this is a reference to a GP relative symbol, we want
3658 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3660 lui $reg,<sym> (BFD_RELOC_HI16_S)
3661 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3662 If we have an addend, we always use the latter form.
3664 With 64bit address space and a usable $at we want
3665 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3666 lui $at,<sym> (BFD_RELOC_HI16_S)
3667 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3668 daddiu $at,<sym> (BFD_RELOC_LO16)
3672 If $at is already in use, we use a path which is suboptimal
3673 on superscalar processors.
3674 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3675 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3677 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3679 daddiu $reg,<sym> (BFD_RELOC_LO16)
3681 if (HAVE_64BIT_ADDRESSES)
3683 /* We don't do GP optimization for now because RELAX_ENCODE can't
3684 hold the data for such large chunks. */
3686 if (*used_at == 0 && ! mips_opts.noat)
3688 macro_build (p, counter, ep, "lui", "t,u",
3689 reg, BFD_RELOC_MIPS_HIGHEST);
3690 macro_build (p, counter, ep, "lui", "t,u",
3691 AT, BFD_RELOC_HI16_S);
3692 macro_build (p, counter, ep, "daddiu", "t,r,j",
3693 reg, reg, BFD_RELOC_MIPS_HIGHER);
3694 macro_build (p, counter, ep, "daddiu", "t,r,j",
3695 AT, AT, BFD_RELOC_LO16);
3696 macro_build (p, counter, NULL, "dsll32", "d,w,<", reg, reg, 0);
3697 macro_build (p, counter, NULL, "daddu", "d,v,t", reg, reg, AT);
3702 macro_build (p, counter, ep, "lui", "t,u",
3703 reg, BFD_RELOC_MIPS_HIGHEST);
3704 macro_build (p, counter, ep, "daddiu", "t,r,j",
3705 reg, reg, BFD_RELOC_MIPS_HIGHER);
3706 macro_build (p, counter, NULL, "dsll", "d,w,<", reg, reg, 16);
3707 macro_build (p, counter, ep, "daddiu", "t,r,j",
3708 reg, reg, BFD_RELOC_HI16_S);
3709 macro_build (p, counter, NULL, "dsll", "d,w,<", reg, reg, 16);
3710 macro_build (p, counter, ep, "daddiu", "t,r,j",
3711 reg, reg, BFD_RELOC_LO16);
3716 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
3717 && ! nopic_need_relax (ep->X_add_symbol, 1))
3720 macro_build (NULL, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
3721 mips_gp_register, BFD_RELOC_GPREL16);
3722 p = frag_var (rs_machine_dependent, 8, 0,
3723 RELAX_ENCODE (4, 8, 0, 4, 0,
3724 mips_opts.warn_about_macros),
3725 ep->X_add_symbol, 0, NULL);
3727 macro_build_lui (p, counter, ep, reg);
3730 macro_build (p, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3734 else if (mips_pic == SVR4_PIC && ! mips_big_got)
3738 /* If this is a reference to an external symbol, we want
3739 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3741 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3743 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3744 If there is a constant, it must be added in after.
3746 If we have NewABI, we want
3747 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3748 unless we're referencing a global symbol with a non-zero
3749 offset, in which case cst must be added separately. */
3754 if (ep->X_add_number)
3756 frag_now->tc_frag_data.tc_fr_offset =
3757 ex.X_add_number = ep->X_add_number;
3758 ep->X_add_number = 0;
3759 macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)",
3760 reg, BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
3761 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3762 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3763 ex.X_op = O_constant;
3764 macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j",
3765 reg, reg, BFD_RELOC_LO16);
3766 p = frag_var (rs_machine_dependent, 8, 0,
3767 RELAX_ENCODE (8, 4, 0, 0, 0,
3768 mips_opts.warn_about_macros),
3769 ep->X_add_symbol, 0, NULL);
3770 ep->X_add_number = ex.X_add_number;
3773 macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3774 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
3778 /* To avoid confusion in tc_gen_reloc, we must ensure
3779 that this does not become a variant frag. */
3780 frag_wane (frag_now);
3786 ex.X_add_number = ep->X_add_number;
3787 ep->X_add_number = 0;
3789 macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3790 BFD_RELOC_MIPS_GOT16,
3792 macro_build (NULL, counter, NULL, "nop", "");
3793 p = frag_var (rs_machine_dependent, 4, 0,
3794 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros),
3795 ep->X_add_symbol, 0, NULL);
3796 macro_build (p, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3799 if (ex.X_add_number != 0)
3801 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3802 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3803 ex.X_op = O_constant;
3804 macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j",
3805 reg, reg, BFD_RELOC_LO16);
3809 else if (mips_pic == SVR4_PIC)
3814 /* This is the large GOT case. If this is a reference to an
3815 external symbol, we want
3816 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3818 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3820 Otherwise, for a reference to a local symbol in old ABI, we want
3821 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3823 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3824 If there is a constant, it must be added in after.
3826 In the NewABI, for local symbols, with or without offsets, we want:
3827 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3828 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3834 frag_now->tc_frag_data.tc_fr_offset =
3835 ex.X_add_number = ep->X_add_number;
3836 ep->X_add_number = 0;
3837 macro_build (NULL, counter, ep, "lui", "t,u", reg,
3838 BFD_RELOC_MIPS_GOT_HI16);
3839 macro_build (NULL, counter, NULL, ADDRESS_ADD_INSN, "d,v,t", reg,
3840 reg, mips_gp_register);
3841 macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3842 BFD_RELOC_MIPS_GOT_LO16, reg);
3843 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3844 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3845 else if (ex.X_add_number)
3847 ex.X_op = O_constant;
3848 macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j",
3849 reg, reg, BFD_RELOC_LO16);
3852 ep->X_add_number = ex.X_add_number;
3853 p = frag_var (rs_machine_dependent, 8, 0,
3854 RELAX_ENCODE (ex.X_add_number ? 16 : 12, 8, 0, 4, 0,
3855 mips_opts.warn_about_macros),
3856 ep->X_add_symbol, 0, NULL);
3857 macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3858 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
3859 macro_build (p + 4, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
3860 reg, BFD_RELOC_MIPS_GOT_OFST);
3864 ex.X_add_number = ep->X_add_number;
3865 ep->X_add_number = 0;
3866 if (reg_needs_delay (mips_gp_register))
3871 macro_build (NULL, counter, ep, "lui", "t,u", reg,
3872 BFD_RELOC_MIPS_GOT_HI16);
3873 macro_build (NULL, counter, NULL, ADDRESS_ADD_INSN, "d,v,t", reg,
3874 reg, mips_gp_register);
3875 macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3876 BFD_RELOC_MIPS_GOT_LO16, reg);
3877 p = frag_var (rs_machine_dependent, 12 + off, 0,
3878 RELAX_ENCODE (12, 12 + off, off, 8 + off, 0,
3879 mips_opts.warn_about_macros),
3880 ep->X_add_symbol, 0, NULL);
3883 /* We need a nop before loading from $gp. This special
3884 check is required because the lui which starts the main
3885 instruction stream does not refer to $gp, and so will not
3886 insert the nop which may be required. */
3887 macro_build (p, counter, NULL, "nop", "");
3890 macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3891 BFD_RELOC_MIPS_GOT16, mips_gp_register);
3893 macro_build (p, counter, NULL, "nop", "");
3895 macro_build (p, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3898 if (ex.X_add_number != 0)
3900 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3901 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3902 ex.X_op = O_constant;
3903 macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j",
3904 reg, reg, BFD_RELOC_LO16);
3908 else if (mips_pic == EMBEDDED_PIC)
3911 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3913 macro_build (NULL, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
3914 mips_gp_register, BFD_RELOC_GPREL16);
3920 /* Move the contents of register SOURCE into register DEST. */
3923 move_register (int *counter, int dest, int source)
3925 macro_build (NULL, counter, NULL, HAVE_32BIT_GPRS ? "addu" : "daddu",
3926 "d,v,t", dest, source, 0);
3931 * This routine implements the seemingly endless macro or synthesized
3932 * instructions and addressing modes in the mips assembly language. Many
3933 * of these macros are simple and are similar to each other. These could
3934 * probably be handled by some kind of table or grammer aproach instead of
3935 * this verbose method. Others are not simple macros but are more like
3936 * optimizing code generation.
3937 * One interesting optimization is when several store macros appear
3938 * consecutivly that would load AT with the upper half of the same address.
3939 * The ensuing load upper instructions are ommited. This implies some kind
3940 * of global optimization. We currently only optimize within a single macro.
3941 * For many of the load and store macros if the address is specified as a
3942 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3943 * first load register 'at' with zero and use it as the base register. The
3944 * mips assembler simply uses register $zero. Just one tiny optimization
3948 macro (struct mips_cl_insn *ip)
3950 register int treg, sreg, dreg, breg;
3966 bfd_reloc_code_real_type r;
3967 int hold_mips_optimize;
3969 assert (! mips_opts.mips16);
3971 treg = (ip->insn_opcode >> 16) & 0x1f;
3972 dreg = (ip->insn_opcode >> 11) & 0x1f;
3973 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
3974 mask = ip->insn_mo->mask;
3976 expr1.X_op = O_constant;
3977 expr1.X_op_symbol = NULL;
3978 expr1.X_add_symbol = NULL;
3979 expr1.X_add_number = 1;
3981 /* Umatched fixups should not be put in the same frag as a relaxable
3982 macro. For example, suppose we have:
3986 addiu $4,$4,%lo(l1) # 3
3988 If instructions 1 and 2 were put in the same frag, md_frob_file would
3989 move the fixup for #1 after the fixups for the "unrelaxed" version of
3990 #2. This would confuse tc_gen_reloc, which expects the relocations
3991 for #2 to be the last for that frag.
3993 Also, if tc_gen_reloc sees certain relocations in a variant frag,
3994 it assumes that they belong to a relaxable macro. We mustn't put
3995 other uses of such relocations into a variant frag.
3997 To avoid both problems, finish the current frag it contains a
3998 %reloc() operator. The macro then goes into a new frag. */
3999 if (prev_reloc_op_frag == frag_now)
4001 frag_wane (frag_now);
4015 mips_emit_delays (TRUE);
4016 ++mips_opts.noreorder;
4017 mips_any_noreorder = 1;
4019 expr1.X_add_number = 8;
4020 macro_build (NULL, &icnt, &expr1, "bgez", "s,p", sreg);
4022 macro_build (NULL, &icnt, NULL, "nop", "", 0);
4024 move_register (&icnt, dreg, sreg);
4025 macro_build (NULL, &icnt, NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0,
4028 --mips_opts.noreorder;
4049 if (imm_expr.X_op == O_constant
4050 && imm_expr.X_add_number >= -0x8000
4051 && imm_expr.X_add_number < 0x8000)
4053 macro_build (NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg,
4057 load_register (&icnt, AT, &imm_expr, dbl);
4058 macro_build (NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT);
4077 if (imm_expr.X_op == O_constant
4078 && imm_expr.X_add_number >= 0
4079 && imm_expr.X_add_number < 0x10000)
4081 if (mask != M_NOR_I)
4082 macro_build (NULL, &icnt, &imm_expr, s, "t,r,i", treg, sreg,
4086 macro_build (NULL, &icnt, &imm_expr, "ori", "t,r,i", treg, sreg,
4088 macro_build (NULL, &icnt, NULL, "nor", "d,v,t", treg, treg, 0);
4093 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
4094 macro_build (NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT);
4111 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4113 macro_build (NULL, &icnt, &offset_expr, s, "s,t,p", sreg, 0);
4116 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
4117 macro_build (NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT);
4125 macro_build (NULL, &icnt, &offset_expr, likely ? "bgezl" : "bgez",
4131 macro_build (NULL, &icnt, &offset_expr, likely ? "blezl" : "blez",
4135 macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg);
4136 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4143 /* check for > max integer */
4144 maxnum = 0x7fffffff;
4145 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4152 if (imm_expr.X_op == O_constant
4153 && imm_expr.X_add_number >= maxnum
4154 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4157 /* result is always false */
4161 as_warn (_("Branch %s is always false (nop)"),
4163 macro_build (NULL, &icnt, NULL, "nop", "", 0);
4168 as_warn (_("Branch likely %s is always false"),
4170 macro_build (NULL, &icnt, &offset_expr, "bnel", "s,t,p", 0, 0);
4174 if (imm_expr.X_op != O_constant)
4175 as_bad (_("Unsupported large constant"));
4176 ++imm_expr.X_add_number;
4180 if (mask == M_BGEL_I)
4182 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4184 macro_build (NULL, &icnt, &offset_expr, likely ? "bgezl" : "bgez",
4188 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4190 macro_build (NULL, &icnt, &offset_expr, likely ? "bgtzl" : "bgtz",
4194 maxnum = 0x7fffffff;
4195 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4202 maxnum = - maxnum - 1;
4203 if (imm_expr.X_op == O_constant
4204 && imm_expr.X_add_number <= maxnum
4205 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4208 /* result is always true */
4209 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
4210 macro_build (NULL, &icnt, &offset_expr, "b", "p");
4213 set_at (&icnt, sreg, 0);
4214 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4225 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4229 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, treg);
4230 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4239 && imm_expr.X_op == O_constant
4240 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4242 if (imm_expr.X_op != O_constant)
4243 as_bad (_("Unsupported large constant"));
4244 ++imm_expr.X_add_number;
4248 if (mask == M_BGEUL_I)
4250 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4252 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4254 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4258 set_at (&icnt, sreg, 1);
4259 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4268 macro_build (NULL, &icnt, &offset_expr, likely ? "bgtzl" : "bgtz",
4274 macro_build (NULL, &icnt, &offset_expr, likely ? "bltzl" : "bltz",
4278 macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg);
4279 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4288 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4294 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, sreg);
4295 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4304 macro_build (NULL, &icnt, &offset_expr, likely ? "blezl" : "blez",
4310 macro_build (NULL, &icnt, &offset_expr, likely ? "bgezl" : "bgez",
4314 macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg);
4315 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4322 maxnum = 0x7fffffff;
4323 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4330 if (imm_expr.X_op == O_constant
4331 && imm_expr.X_add_number >= maxnum
4332 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4334 if (imm_expr.X_op != O_constant)
4335 as_bad (_("Unsupported large constant"));
4336 ++imm_expr.X_add_number;
4340 if (mask == M_BLTL_I)
4342 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4344 macro_build (NULL, &icnt, &offset_expr, likely ? "bltzl" : "bltz",
4348 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4350 macro_build (NULL, &icnt, &offset_expr, likely ? "blezl" : "blez",
4354 set_at (&icnt, sreg, 0);
4355 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4364 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4370 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, sreg);
4371 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4380 && imm_expr.X_op == O_constant
4381 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4383 if (imm_expr.X_op != O_constant)
4384 as_bad (_("Unsupported large constant"));
4385 ++imm_expr.X_add_number;
4389 if (mask == M_BLTUL_I)
4391 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4393 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4395 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4399 set_at (&icnt, sreg, 1);
4400 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4409 macro_build (NULL, &icnt, &offset_expr, likely ? "bltzl" : "bltz",
4415 macro_build (NULL, &icnt, &offset_expr, likely ? "bgtzl" : "bgtz",
4419 macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg);
4420 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4431 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4435 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, treg);
4436 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4452 as_warn (_("Divide by zero."));
4454 macro_build (NULL, &icnt, NULL, "teq", "s,t,q", 0, 0, 7);
4456 macro_build (NULL, &icnt, NULL, "break", "c", 7);
4460 mips_emit_delays (TRUE);
4461 ++mips_opts.noreorder;
4462 mips_any_noreorder = 1;
4465 macro_build (NULL, &icnt, NULL, "teq", "s,t,q", treg, 0, 7);
4466 macro_build (NULL, &icnt, NULL, dbl ? "ddiv" : "div", "z,s,t",
4471 expr1.X_add_number = 8;
4472 macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4473 macro_build (NULL, &icnt, NULL, dbl ? "ddiv" : "div", "z,s,t",
4475 macro_build (NULL, &icnt,NULL, "break", "c", 7);
4477 expr1.X_add_number = -1;
4478 macro_build (NULL, &icnt, &expr1, dbl ? "daddiu" : "addiu", "t,r,j",
4479 AT, 0, BFD_RELOC_LO16);
4480 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
4481 macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT);
4484 expr1.X_add_number = 1;
4485 macro_build (NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0,
4487 macro_build (NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, 31);
4491 expr1.X_add_number = 0x80000000;
4492 macro_build (NULL, &icnt, &expr1, "lui", "t,u", AT,
4497 macro_build (NULL, &icnt, NULL, "teq", "s,t,q", sreg, AT, 6);
4498 /* We want to close the noreorder block as soon as possible, so
4499 that later insns are available for delay slot filling. */
4500 --mips_opts.noreorder;
4504 expr1.X_add_number = 8;
4505 macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT);
4506 macro_build (NULL, &icnt, NULL, "nop", "", 0);
4508 /* We want to close the noreorder block as soon as possible, so
4509 that later insns are available for delay slot filling. */
4510 --mips_opts.noreorder;
4512 macro_build (NULL, &icnt, NULL, "break", "c", 6);
4514 macro_build (NULL, &icnt, NULL, s, "d", dreg);
4553 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4555 as_warn (_("Divide by zero."));
4557 macro_build (NULL, &icnt, NULL, "teq", "s,t,q", 0, 0, 7);
4559 macro_build (NULL, &icnt, NULL, "break", "c", 7);
4562 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4564 if (strcmp (s2, "mflo") == 0)
4565 move_register (&icnt, dreg, sreg);
4567 move_register (&icnt, dreg, 0);
4570 if (imm_expr.X_op == O_constant
4571 && imm_expr.X_add_number == -1
4572 && s[strlen (s) - 1] != 'u')
4574 if (strcmp (s2, "mflo") == 0)
4576 macro_build (NULL, &icnt, NULL, dbl ? "dneg" : "neg", "d,w",
4580 move_register (&icnt, dreg, 0);
4584 load_register (&icnt, AT, &imm_expr, dbl);
4585 macro_build (NULL, &icnt, NULL, s, "z,s,t", sreg, AT);
4586 macro_build (NULL, &icnt, NULL, s2, "d", dreg);
4605 mips_emit_delays (TRUE);
4606 ++mips_opts.noreorder;
4607 mips_any_noreorder = 1;
4610 macro_build (NULL, &icnt, NULL, "teq", "s,t,q", treg, 0, 7);
4611 macro_build (NULL, &icnt, NULL, s, "z,s,t", sreg, treg);
4612 /* We want to close the noreorder block as soon as possible, so
4613 that later insns are available for delay slot filling. */
4614 --mips_opts.noreorder;
4618 expr1.X_add_number = 8;
4619 macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4620 macro_build (NULL, &icnt, NULL, s, "z,s,t", sreg, treg);
4622 /* We want to close the noreorder block as soon as possible, so
4623 that later insns are available for delay slot filling. */
4624 --mips_opts.noreorder;
4625 macro_build (NULL, &icnt, NULL, "break", "c", 7);
4627 macro_build (NULL, &icnt, NULL, s2, "d", dreg);
4633 /* Load the address of a symbol into a register. If breg is not
4634 zero, we then add a base register to it. */
4636 if (dbl && HAVE_32BIT_GPRS)
4637 as_warn (_("dla used to load 32-bit register"));
4639 if (! dbl && HAVE_64BIT_OBJECTS)
4640 as_warn (_("la used to load 64-bit address"));
4642 if (offset_expr.X_op == O_constant
4643 && offset_expr.X_add_number >= -0x8000
4644 && offset_expr.X_add_number < 0x8000)
4646 macro_build (NULL, &icnt, &offset_expr,
4647 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4648 "t,r,j", treg, sreg, BFD_RELOC_LO16);
4663 /* When generating embedded PIC code, we permit expressions of
4666 la $treg,foo-bar($breg)
4667 where bar is an address in the current section. These are used
4668 when getting the addresses of functions. We don't permit
4669 X_add_number to be non-zero, because if the symbol is
4670 external the relaxing code needs to know that any addend is
4671 purely the offset to X_op_symbol. */
4672 if (mips_pic == EMBEDDED_PIC
4673 && offset_expr.X_op == O_subtract
4674 && (symbol_constant_p (offset_expr.X_op_symbol)
4675 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
4676 : (symbol_equated_p (offset_expr.X_op_symbol)
4678 (symbol_get_value_expression (offset_expr.X_op_symbol)
4681 && (offset_expr.X_add_number == 0
4682 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
4688 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
4689 BFD_RELOC_PCREL_HI16_S);
4693 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
4694 BFD_RELOC_PCREL_HI16_S);
4695 macro_build (NULL, &icnt, NULL,
4696 (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu",
4697 "d,v,t", tempreg, tempreg, breg);
4699 macro_build (NULL, &icnt, &offset_expr,
4700 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4701 "t,r,j", treg, tempreg, BFD_RELOC_PCREL_LO16);
4707 if (offset_expr.X_op != O_symbol
4708 && offset_expr.X_op != O_constant)
4710 as_bad (_("expression too complex"));
4711 offset_expr.X_op = O_constant;
4714 if (offset_expr.X_op == O_constant)
4715 load_register (&icnt, tempreg, &offset_expr,
4716 ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
4717 ? (dbl || HAVE_64BIT_ADDRESSES)
4718 : HAVE_64BIT_ADDRESSES));
4719 else if (mips_pic == NO_PIC)
4721 /* If this is a reference to a GP relative symbol, we want
4722 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4724 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4725 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4726 If we have a constant, we need two instructions anyhow,
4727 so we may as well always use the latter form.
4729 With 64bit address space and a usable $at we want
4730 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4731 lui $at,<sym> (BFD_RELOC_HI16_S)
4732 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4733 daddiu $at,<sym> (BFD_RELOC_LO16)
4735 daddu $tempreg,$tempreg,$at
4737 If $at is already in use, we use a path which is suboptimal
4738 on superscalar processors.
4739 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4740 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4742 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4744 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4747 if (HAVE_64BIT_ADDRESSES)
4749 /* We don't do GP optimization for now because RELAX_ENCODE can't
4750 hold the data for such large chunks. */
4752 if (used_at == 0 && ! mips_opts.noat)
4754 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4755 tempreg, BFD_RELOC_MIPS_HIGHEST);
4756 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4757 AT, BFD_RELOC_HI16_S);
4758 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4759 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
4760 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4761 AT, AT, BFD_RELOC_LO16);
4762 macro_build (p, &icnt, NULL, "dsll32", "d,w,<",
4763 tempreg, tempreg, 0);
4764 macro_build (p, &icnt, NULL, "daddu", "d,v,t",
4765 tempreg, tempreg, AT);
4770 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4771 tempreg, BFD_RELOC_MIPS_HIGHEST);
4772 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4773 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
4774 macro_build (p, &icnt, NULL, "dsll", "d,w,<",
4775 tempreg, tempreg, 16);
4776 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4777 tempreg, tempreg, BFD_RELOC_HI16_S);
4778 macro_build (p, &icnt, NULL, "dsll", "d,w,<",
4779 tempreg, tempreg, 16);
4780 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4781 tempreg, tempreg, BFD_RELOC_LO16);
4786 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
4787 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
4790 macro_build (NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
4791 "t,r,j", tempreg, mips_gp_register,
4793 p = frag_var (rs_machine_dependent, 8, 0,
4794 RELAX_ENCODE (4, 8, 0, 4, 0,
4795 mips_opts.warn_about_macros),
4796 offset_expr.X_add_symbol, 0, NULL);
4798 macro_build_lui (p, &icnt, &offset_expr, tempreg);
4801 macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
4802 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
4805 else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI)
4807 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
4809 /* If this is a reference to an external symbol, and there
4810 is no constant, we want
4811 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4812 or if tempreg is PIC_CALL_REG
4813 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4814 For a local symbol, we want
4815 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4817 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4819 If we have a small constant, and this is a reference to
4820 an external symbol, we want
4821 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4823 addiu $tempreg,$tempreg,<constant>
4824 For a local symbol, we want the same instruction
4825 sequence, but we output a BFD_RELOC_LO16 reloc on the
4828 If we have a large constant, and this is a reference to
4829 an external symbol, we want
4830 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4831 lui $at,<hiconstant>
4832 addiu $at,$at,<loconstant>
4833 addu $tempreg,$tempreg,$at
4834 For a local symbol, we want the same instruction
4835 sequence, but we output a BFD_RELOC_LO16 reloc on the
4839 expr1.X_add_number = offset_expr.X_add_number;
4840 offset_expr.X_add_number = 0;
4842 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
4843 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
4844 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
4845 tempreg, lw_reloc_type, mips_gp_register);
4846 if (expr1.X_add_number == 0)
4855 /* We're going to put in an addu instruction using
4856 tempreg, so we may as well insert the nop right
4858 macro_build (NULL, &icnt, NULL, "nop", "");
4861 p = frag_var (rs_machine_dependent, 8 - off, 0,
4862 RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0,
4864 ? mips_opts.warn_about_macros
4866 offset_expr.X_add_symbol, 0, NULL);
4869 macro_build (p, &icnt, NULL, "nop", "");
4872 macro_build (p, &icnt, &expr1, ADDRESS_ADDI_INSN,
4873 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
4874 /* FIXME: If breg == 0, and the next instruction uses
4875 $tempreg, then if this variant case is used an extra
4876 nop will be generated. */
4878 else if (expr1.X_add_number >= -0x8000
4879 && expr1.X_add_number < 0x8000)
4881 macro_build (NULL, &icnt, NULL, "nop", "");
4882 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
4883 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
4884 frag_var (rs_machine_dependent, 0, 0,
4885 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4886 offset_expr.X_add_symbol, 0, NULL);
4892 /* If we are going to add in a base register, and the
4893 target register and the base register are the same,
4894 then we are using AT as a temporary register. Since
4895 we want to load the constant into AT, we add our
4896 current AT (from the global offset table) and the
4897 register into the register now, and pretend we were
4898 not using a base register. */
4903 macro_build (NULL, &icnt, NULL, "nop", "");
4904 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
4911 /* Set mips_optimize around the lui instruction to avoid
4912 inserting an unnecessary nop after the lw. */
4913 hold_mips_optimize = mips_optimize;
4915 macro_build_lui (NULL, &icnt, &expr1, AT);
4916 mips_optimize = hold_mips_optimize;
4918 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j",
4919 AT, AT, BFD_RELOC_LO16);
4920 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
4921 tempreg, tempreg, AT);
4922 frag_var (rs_machine_dependent, 0, 0,
4923 RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0),
4924 offset_expr.X_add_symbol, 0, NULL);
4928 else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI)
4931 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_DISP;
4934 /* If this is a reference to an external, and there is no
4935 constant, or local symbol (*), with or without a
4937 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4938 or if tempreg is PIC_CALL_REG
4939 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4941 If we have a small constant, and this is a reference to
4942 an external symbol, we want
4943 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4944 addiu $tempreg,$tempreg,<constant>
4946 If we have a large constant, and this is a reference to
4947 an external symbol, we want
4948 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4949 lui $at,<hiconstant>
4950 addiu $at,$at,<loconstant>
4951 addu $tempreg,$tempreg,$at
4953 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
4954 local symbols, even though it introduces an additional
4958 if (offset_expr.X_add_number == 0 && tempreg == PIC_CALL_REG)
4959 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
4960 if (offset_expr.X_add_number)
4962 frag_now->tc_frag_data.tc_fr_offset =
4963 expr1.X_add_number = offset_expr.X_add_number;
4964 offset_expr.X_add_number = 0;
4966 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
4967 "t,o(b)", tempreg, lw_reloc_type,
4970 if (expr1.X_add_number >= -0x8000
4971 && expr1.X_add_number < 0x8000)
4973 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
4974 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
4975 p = frag_var (rs_machine_dependent, 4, 0,
4976 RELAX_ENCODE (8, 4, 0, 0, 0, 0),
4977 offset_expr.X_add_symbol, 0, NULL);
4979 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number))
4983 /* If we are going to add in a base register, and the
4984 target register and the base register are the same,
4985 then we are using AT as a temporary register. Since
4986 we want to load the constant into AT, we add our
4987 current AT (from the global offset table) and the
4988 register into the register now, and pretend we were
4989 not using a base register. */
4994 assert (tempreg == AT);
4995 macro_build (NULL, &icnt,NULL, ADDRESS_ADD_INSN,
4996 "d,v,t", treg, AT, breg);
5001 macro_build_lui (NULL, &icnt, &expr1, AT);
5002 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
5003 "t,r,j", AT, AT, BFD_RELOC_LO16);
5004 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5007 p = frag_var (rs_machine_dependent, 4 + adj, 0,
5008 RELAX_ENCODE (16 + adj, 4 + adj,
5010 offset_expr.X_add_symbol, 0, NULL);
5015 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5017 offset_expr.X_add_number = expr1.X_add_number;
5019 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5020 "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_DISP,
5024 macro_build (p + 4, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5025 treg, tempreg, breg);
5032 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5033 "t,o(b)", tempreg, lw_reloc_type,
5035 if (lw_reloc_type != BFD_RELOC_MIPS_GOT_DISP)
5036 p = frag_var (rs_machine_dependent, 0, 0,
5037 RELAX_ENCODE (0, 0, -4, 0, 0, 0),
5038 offset_expr.X_add_symbol, 0, NULL);
5043 /* To avoid confusion in tc_gen_reloc, we must ensure
5044 that this does not become a variant frag. */
5045 frag_wane (frag_now);
5049 else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
5053 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5054 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5055 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5057 /* This is the large GOT case. If this is a reference to an
5058 external symbol, and there is no constant, we want
5059 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5060 addu $tempreg,$tempreg,$gp
5061 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5062 or if tempreg is PIC_CALL_REG
5063 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5064 addu $tempreg,$tempreg,$gp
5065 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5066 For a local symbol, we want
5067 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5069 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5071 If we have a small constant, and this is a reference to
5072 an external symbol, we want
5073 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5074 addu $tempreg,$tempreg,$gp
5075 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5077 addiu $tempreg,$tempreg,<constant>
5078 For a local symbol, we want
5079 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5081 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5083 If we have a large constant, and this is a reference to
5084 an external symbol, we want
5085 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5086 addu $tempreg,$tempreg,$gp
5087 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5088 lui $at,<hiconstant>
5089 addiu $at,$at,<loconstant>
5090 addu $tempreg,$tempreg,$at
5091 For a local symbol, we want
5092 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5093 lui $at,<hiconstant>
5094 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5095 addu $tempreg,$tempreg,$at
5098 expr1.X_add_number = offset_expr.X_add_number;
5099 offset_expr.X_add_number = 0;
5101 if (reg_needs_delay (mips_gp_register))
5105 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
5107 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5108 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5110 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u",
5111 tempreg, lui_reloc_type);
5112 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5113 tempreg, tempreg, mips_gp_register);
5114 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5115 tempreg, lw_reloc_type, tempreg);
5116 if (expr1.X_add_number == 0)
5124 /* We're going to put in an addu instruction using
5125 tempreg, so we may as well insert the nop right
5127 macro_build (NULL, &icnt, NULL, "nop", "");
5131 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5132 RELAX_ENCODE (12 + off, 12 + gpdel, gpdel,
5135 ? mips_opts.warn_about_macros
5137 offset_expr.X_add_symbol, 0, NULL);
5139 else if (expr1.X_add_number >= -0x8000
5140 && expr1.X_add_number < 0x8000)
5142 macro_build (NULL, &icnt, NULL, "nop", "");
5143 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j",
5144 tempreg, tempreg, BFD_RELOC_LO16);
5146 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5147 RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0,
5149 ? mips_opts.warn_about_macros
5151 offset_expr.X_add_symbol, 0, NULL);
5157 /* If we are going to add in a base register, and the
5158 target register and the base register are the same,
5159 then we are using AT as a temporary register. Since
5160 we want to load the constant into AT, we add our
5161 current AT (from the global offset table) and the
5162 register into the register now, and pretend we were
5163 not using a base register. */
5171 assert (tempreg == AT);
5172 macro_build (NULL, &icnt, NULL, "nop", "");
5173 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5179 /* Set mips_optimize around the lui instruction to avoid
5180 inserting an unnecessary nop after the lw. */
5181 hold_mips_optimize = mips_optimize;
5183 macro_build_lui (NULL, &icnt, &expr1, AT);
5184 mips_optimize = hold_mips_optimize;
5186 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j",
5187 AT, AT, BFD_RELOC_LO16);
5188 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5191 p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0,
5192 RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel,
5195 ? mips_opts.warn_about_macros
5197 offset_expr.X_add_symbol, 0, NULL);
5204 /* This is needed because this instruction uses $gp, but
5205 the first instruction on the main stream does not. */
5206 macro_build (p, &icnt, NULL, "nop", "");
5210 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5211 tempreg, local_reloc_type, mips_gp_register);
5213 if (expr1.X_add_number >= -0x8000
5214 && expr1.X_add_number < 0x8000)
5216 macro_build (p, &icnt, NULL, "nop", "");
5218 macro_build (p, &icnt, &expr1, ADDRESS_ADDI_INSN,
5219 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
5220 /* FIXME: If add_number is 0, and there was no base
5221 register, the external symbol case ended with a load,
5222 so if the symbol turns out to not be external, and
5223 the next instruction uses tempreg, an unnecessary nop
5224 will be inserted. */
5230 /* We must add in the base register now, as in the
5231 external symbol case. */
5232 assert (tempreg == AT);
5233 macro_build (p, &icnt, NULL, "nop", "");
5235 macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5239 /* We set breg to 0 because we have arranged to add
5240 it in in both cases. */
5244 macro_build_lui (p, &icnt, &expr1, AT);
5246 macro_build (p, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j",
5247 AT, AT, BFD_RELOC_LO16);
5249 macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5250 tempreg, tempreg, AT);
5254 else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
5257 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5258 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5261 /* This is the large GOT case. If this is a reference to an
5262 external symbol, and there is no constant, we want
5263 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5264 add $tempreg,$tempreg,$gp
5265 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5266 or if tempreg is PIC_CALL_REG
5267 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5268 add $tempreg,$tempreg,$gp
5269 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5271 If we have a small constant, and this is a reference to
5272 an external symbol, we want
5273 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5274 add $tempreg,$tempreg,$gp
5275 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5276 addi $tempreg,$tempreg,<constant>
5278 If we have a large constant, and this is a reference to
5279 an external symbol, we want
5280 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5281 addu $tempreg,$tempreg,$gp
5282 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5283 lui $at,<hiconstant>
5284 addi $at,$at,<loconstant>
5285 add $tempreg,$tempreg,$at
5287 If we have NewABI, and we know it's a local symbol, we want
5288 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5289 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5290 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5294 frag_now->tc_frag_data.tc_fr_offset =
5295 expr1.X_add_number = offset_expr.X_add_number;
5296 offset_expr.X_add_number = 0;
5298 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
5300 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5301 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5303 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u",
5304 tempreg, lui_reloc_type);
5305 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5306 tempreg, tempreg, mips_gp_register);
5307 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5308 "t,o(b)", tempreg, lw_reloc_type, tempreg);
5310 if (expr1.X_add_number == 0)
5312 p = frag_var (rs_machine_dependent, 8, 0,
5313 RELAX_ENCODE (12, 8, 0, 4, 0,
5314 mips_opts.warn_about_macros),
5315 offset_expr.X_add_symbol, 0, NULL);
5317 else if (expr1.X_add_number >= -0x8000
5318 && expr1.X_add_number < 0x8000)
5320 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j",
5321 tempreg, tempreg, BFD_RELOC_LO16);
5322 p = frag_var (rs_machine_dependent, 8, 0,
5323 RELAX_ENCODE (16, 8, 0, 4, 0,
5324 mips_opts.warn_about_macros),
5325 offset_expr.X_add_symbol, 0, NULL);
5327 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number))
5331 /* If we are going to add in a base register, and the
5332 target register and the base register are the same,
5333 then we are using AT as a temporary register. Since
5334 we want to load the constant into AT, we add our
5335 current AT (from the global offset table) and the
5336 register into the register now, and pretend we were
5337 not using a base register. */
5342 assert (tempreg == AT);
5343 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5349 /* Set mips_optimize around the lui instruction to avoid
5350 inserting an unnecessary nop after the lw. */
5351 macro_build_lui (NULL, &icnt, &expr1, AT);
5352 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
5353 "t,r,j", AT, AT, BFD_RELOC_LO16);
5354 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5357 p = frag_var (rs_machine_dependent, 8 + adj, 0,
5358 RELAX_ENCODE (24 + adj, 8 + adj,
5361 ? mips_opts.warn_about_macros
5363 offset_expr.X_add_symbol, 0, NULL);
5368 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5370 offset_expr.X_add_number = expr1.X_add_number;
5371 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5372 tempreg, BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
5373 macro_build (p + 4, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5374 tempreg, tempreg, BFD_RELOC_MIPS_GOT_OFST);
5377 macro_build (p + 8, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5378 treg, tempreg, breg);
5383 else if (mips_pic == EMBEDDED_PIC)
5386 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5388 macro_build (NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5389 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5398 if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
5399 s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu";
5401 s = ADDRESS_ADD_INSN;
5403 macro_build (NULL, &icnt, NULL, s, "d,v,t", treg, tempreg, breg);
5412 /* The j instruction may not be used in PIC code, since it
5413 requires an absolute address. We convert it to a b
5415 if (mips_pic == NO_PIC)
5416 macro_build (NULL, &icnt, &offset_expr, "j", "a");
5418 macro_build (NULL, &icnt, &offset_expr, "b", "p");
5421 /* The jal instructions must be handled as macros because when
5422 generating PIC code they expand to multi-instruction
5423 sequences. Normally they are simple instructions. */
5428 if (mips_pic == NO_PIC
5429 || mips_pic == EMBEDDED_PIC)
5430 macro_build (NULL, &icnt, NULL, "jalr", "d,s", dreg, sreg);
5431 else if (mips_pic == SVR4_PIC)
5433 if (sreg != PIC_CALL_REG)
5434 as_warn (_("MIPS PIC call to register other than $25"));
5436 macro_build (NULL, &icnt, NULL, "jalr", "d,s", dreg, sreg);
5439 if (mips_cprestore_offset < 0)
5440 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5443 if (! mips_frame_reg_valid)
5445 as_warn (_("No .frame pseudo-op used in PIC code"));
5446 /* Quiet this warning. */
5447 mips_frame_reg_valid = 1;
5449 if (! mips_cprestore_valid)
5451 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5452 /* Quiet this warning. */
5453 mips_cprestore_valid = 1;
5455 expr1.X_add_number = mips_cprestore_offset;
5456 macro_build_ldst_constoffset (NULL, &icnt, &expr1,
5460 HAVE_64BIT_ADDRESSES);
5470 if (mips_pic == NO_PIC)
5471 macro_build (NULL, &icnt, &offset_expr, "jal", "a");
5472 else if (mips_pic == SVR4_PIC)
5476 /* If this is a reference to an external symbol, and we are
5477 using a small GOT, we want
5478 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5482 lw $gp,cprestore($sp)
5483 The cprestore value is set using the .cprestore
5484 pseudo-op. If we are using a big GOT, we want
5485 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5487 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5491 lw $gp,cprestore($sp)
5492 If the symbol is not external, we want
5493 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5495 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5498 lw $gp,cprestore($sp)
5500 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5501 sequences above, minus nops, unless the symbol is local,
5502 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5509 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5510 "t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
5512 frag_var (rs_machine_dependent, 0, 0,
5513 RELAX_ENCODE (0, 0, -4, 0, 0, 0),
5514 offset_expr.X_add_symbol, 0, NULL);
5519 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u",
5520 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_HI16);
5521 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5522 PIC_CALL_REG, PIC_CALL_REG, mips_gp_register);
5523 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5524 "t,o(b)", PIC_CALL_REG,
5525 BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
5526 p = frag_var (rs_machine_dependent, 8, 0,
5527 RELAX_ENCODE (12, 8, 0, 4, 0, 0),
5528 offset_expr.X_add_symbol, 0, NULL);
5529 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5530 "t,o(b)", PIC_CALL_REG,
5531 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
5532 macro_build (p + 4, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
5533 "t,r,j", PIC_CALL_REG, PIC_CALL_REG,
5534 BFD_RELOC_MIPS_GOT_OFST);
5537 macro_build_jalr (icnt, &offset_expr);
5544 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5545 "t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
5547 macro_build (NULL, &icnt, NULL, "nop", "");
5548 p = frag_var (rs_machine_dependent, 4, 0,
5549 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5550 offset_expr.X_add_symbol, 0, NULL);
5556 if (reg_needs_delay (mips_gp_register))
5560 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u",
5561 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_HI16);
5562 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5563 PIC_CALL_REG, PIC_CALL_REG, mips_gp_register);
5564 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5565 "t,o(b)", PIC_CALL_REG,
5566 BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
5567 macro_build (NULL, &icnt, NULL, "nop", "");
5568 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5569 RELAX_ENCODE (16, 12 + gpdel, gpdel,
5571 offset_expr.X_add_symbol, 0, NULL);
5574 macro_build (p, &icnt, NULL, "nop", "");
5577 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5578 "t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
5581 macro_build (p, &icnt, NULL, "nop", "");
5584 macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
5585 "t,r,j", PIC_CALL_REG, PIC_CALL_REG,
5587 macro_build_jalr (icnt, &offset_expr);
5589 if (mips_cprestore_offset < 0)
5590 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5593 if (! mips_frame_reg_valid)
5595 as_warn (_("No .frame pseudo-op used in PIC code"));
5596 /* Quiet this warning. */
5597 mips_frame_reg_valid = 1;
5599 if (! mips_cprestore_valid)
5601 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5602 /* Quiet this warning. */
5603 mips_cprestore_valid = 1;
5605 if (mips_opts.noreorder)
5606 macro_build (NULL, &icnt, NULL, "nop", "");
5607 expr1.X_add_number = mips_cprestore_offset;
5608 macro_build_ldst_constoffset (NULL, &icnt, &expr1,
5612 HAVE_64BIT_ADDRESSES);
5616 else if (mips_pic == EMBEDDED_PIC)
5618 macro_build (NULL, &icnt, &offset_expr, "bal", "p");
5619 /* The linker may expand the call to a longer sequence which
5620 uses $at, so we must break rather than return. */
5645 /* Itbl support may require additional care here. */
5650 /* Itbl support may require additional care here. */
5655 /* Itbl support may require additional care here. */
5660 /* Itbl support may require additional care here. */
5672 if (mips_opts.arch == CPU_R4650)
5674 as_bad (_("opcode not supported on this processor"));
5678 /* Itbl support may require additional care here. */
5683 /* Itbl support may require additional care here. */
5688 /* Itbl support may require additional care here. */
5708 if (breg == treg || coproc || lr)
5730 /* Itbl support may require additional care here. */
5735 /* Itbl support may require additional care here. */
5740 /* Itbl support may require additional care here. */
5745 /* Itbl support may require additional care here. */
5761 if (mips_opts.arch == CPU_R4650)
5763 as_bad (_("opcode not supported on this processor"));
5768 /* Itbl support may require additional care here. */
5772 /* Itbl support may require additional care here. */
5777 /* Itbl support may require additional care here. */
5789 /* Itbl support may require additional care here. */
5790 if (mask == M_LWC1_AB
5791 || mask == M_SWC1_AB
5792 || mask == M_LDC1_AB
5793 || mask == M_SDC1_AB
5802 /* Sign-extending 32-bit constants makes their handling easier.
5803 The HAVE_64BIT_GPRS... part is due to the linux kernel hack
5805 if ((! HAVE_64BIT_ADDRESSES
5806 && (! HAVE_64BIT_GPRS && offset_expr.X_op == O_constant))
5807 && (offset_expr.X_op == O_constant))
5809 if (offset_expr.X_add_number & ~((bfd_vma) 0xffffffff)
5810 && ~(offset_expr.X_add_number | 0xffffffff))
5811 as_bad (_("too large constant specified"));
5813 offset_expr.X_add_number = (((offset_expr.X_add_number & 0xffffffff)
5814 ^ 0x80000000) - 0x80000000);
5817 /* For embedded PIC, we allow loads where the offset is calculated
5818 by subtracting a symbol in the current segment from an unknown
5819 symbol, relative to a base register, e.g.:
5820 <op> $treg, <sym>-<localsym>($breg)
5821 This is used by the compiler for switch statements. */
5822 if (mips_pic == EMBEDDED_PIC
5823 && offset_expr.X_op == O_subtract
5824 && (symbol_constant_p (offset_expr.X_op_symbol)
5825 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
5826 : (symbol_equated_p (offset_expr.X_op_symbol)
5828 (symbol_get_value_expression (offset_expr.X_op_symbol)
5832 && (offset_expr.X_add_number == 0
5833 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
5835 /* For this case, we output the instructions:
5836 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5837 addiu $tempreg,$tempreg,$breg
5838 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5839 If the relocation would fit entirely in 16 bits, it would be
5841 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5842 instead, but that seems quite difficult. */
5843 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
5844 BFD_RELOC_PCREL_HI16_S);
5845 macro_build (NULL, &icnt, NULL,
5846 ((bfd_arch_bits_per_address (stdoutput) == 32
5847 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
5848 ? "addu" : "daddu"),
5849 "d,v,t", tempreg, tempreg, breg);
5850 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
5851 BFD_RELOC_PCREL_LO16, tempreg);
5857 if (offset_expr.X_op != O_constant
5858 && offset_expr.X_op != O_symbol)
5860 as_bad (_("expression too complex"));
5861 offset_expr.X_op = O_constant;
5864 /* A constant expression in PIC code can be handled just as it
5865 is in non PIC code. */
5866 if (mips_pic == NO_PIC
5867 || offset_expr.X_op == O_constant)
5871 /* If this is a reference to a GP relative symbol, and there
5872 is no base register, we want
5873 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5874 Otherwise, if there is no base register, we want
5875 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5876 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5877 If we have a constant, we need two instructions anyhow,
5878 so we always use the latter form.
5880 If we have a base register, and this is a reference to a
5881 GP relative symbol, we want
5882 addu $tempreg,$breg,$gp
5883 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5885 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5886 addu $tempreg,$tempreg,$breg
5887 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5888 With a constant we always use the latter case.
5890 With 64bit address space and no base register and $at usable,
5892 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5893 lui $at,<sym> (BFD_RELOC_HI16_S)
5894 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5897 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5898 If we have a base register, we want
5899 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5900 lui $at,<sym> (BFD_RELOC_HI16_S)
5901 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5905 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5907 Without $at we can't generate the optimal path for superscalar
5908 processors here since this would require two temporary registers.
5909 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5910 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5912 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5914 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5915 If we have a base register, we want
5916 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5917 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5919 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5921 daddu $tempreg,$tempreg,$breg
5922 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5924 If we have 64-bit addresses, as an optimization, for
5925 addresses which are 32-bit constants (e.g. kseg0/kseg1
5926 addresses) we fall back to the 32-bit address generation
5927 mechanism since it is more efficient. Note that due to
5928 the signed offset used by memory operations, the 32-bit
5929 range is shifted down by 32768 here. This code should
5930 probably attempt to generate 64-bit constants more
5931 efficiently in general.
5933 As an extension for architectures with 64-bit registers,
5934 we don't truncate 64-bit addresses given as literal
5935 constants down to 32 bits, to support existing practice
5936 in the mips64 Linux (the kernel), that compiles source
5937 files with -mabi=64, assembling them as o32 or n32 (with
5938 -Wa,-32 or -Wa,-n32). This is not beautiful, but since
5939 the whole kernel is loaded into a memory region that is
5940 addressible with sign-extended 32-bit addresses, it is
5941 wasteful to compute the upper 32 bits of every
5942 non-literal address, that takes more space and time.
5943 Some day this should probably be implemented as an
5944 assembler option, such that the kernel doesn't have to
5945 use such ugly hacks, even though it will still have to
5946 end up converting the binary to ELF32 for a number of
5947 platforms whose boot loaders don't support ELF64
5949 if ((HAVE_64BIT_ADDRESSES
5950 && ! (offset_expr.X_op == O_constant
5951 && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
5953 && offset_expr.X_op == O_constant
5954 && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
5958 /* We don't do GP optimization for now because RELAX_ENCODE can't
5959 hold the data for such large chunks. */
5961 if (used_at == 0 && ! mips_opts.noat)
5963 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5964 tempreg, BFD_RELOC_MIPS_HIGHEST);
5965 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5966 AT, BFD_RELOC_HI16_S);
5967 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5968 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5970 macro_build (p, &icnt, NULL, "daddu", "d,v,t",
5972 macro_build (p, &icnt, NULL, "dsll32", "d,w,<",
5973 tempreg, tempreg, 0);
5974 macro_build (p, &icnt, NULL, "daddu", "d,v,t",
5975 tempreg, tempreg, AT);
5976 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
5977 BFD_RELOC_LO16, tempreg);
5982 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5983 tempreg, BFD_RELOC_MIPS_HIGHEST);
5984 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5985 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5986 macro_build (p, &icnt, NULL, "dsll", "d,w,<",
5987 tempreg, tempreg, 16);
5988 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5989 tempreg, tempreg, BFD_RELOC_HI16_S);
5990 macro_build (p, &icnt, NULL, "dsll", "d,w,<",
5991 tempreg, tempreg, 16);
5993 macro_build (p, &icnt, NULL, "daddu", "d,v,t",
5994 tempreg, tempreg, breg);
5995 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
5996 BFD_RELOC_LO16, tempreg);
6002 if (offset_expr.X_op == O_constant
6003 && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
6004 as_bad (_("load/store address overflow (max 32 bits)"));
6008 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6009 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6014 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
6015 BFD_RELOC_GPREL16, mips_gp_register);
6016 p = frag_var (rs_machine_dependent, 8, 0,
6017 RELAX_ENCODE (4, 8, 0, 4, 0,
6018 (mips_opts.warn_about_macros
6020 && mips_opts.noat))),
6021 offset_expr.X_add_symbol, 0, NULL);
6024 macro_build_lui (p, &icnt, &offset_expr, tempreg);
6027 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
6028 BFD_RELOC_LO16, tempreg);
6032 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6033 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6038 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6039 tempreg, breg, mips_gp_register);
6040 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
6041 BFD_RELOC_GPREL16, tempreg);
6042 p = frag_var (rs_machine_dependent, 12, 0,
6043 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
6044 offset_expr.X_add_symbol, 0, NULL);
6046 macro_build_lui (p, &icnt, &offset_expr, tempreg);
6049 macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6050 tempreg, tempreg, breg);
6053 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
6054 BFD_RELOC_LO16, tempreg);
6057 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6060 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6062 /* If this is a reference to an external symbol, we want
6063 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6065 <op> $treg,0($tempreg)
6067 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6069 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6070 <op> $treg,0($tempreg)
6073 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6074 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6076 If there is a base register, we add it to $tempreg before
6077 the <op>. If there is a constant, we stick it in the
6078 <op> instruction. We don't handle constants larger than
6079 16 bits, because we have no way to load the upper 16 bits
6080 (actually, we could handle them for the subset of cases
6081 in which we are not using $at). */
6082 assert (offset_expr.X_op == O_symbol);
6085 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
6086 "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_PAGE,
6089 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6090 tempreg, tempreg, breg);
6091 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
6092 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6099 expr1.X_add_number = offset_expr.X_add_number;
6100 offset_expr.X_add_number = 0;
6101 if (expr1.X_add_number < -0x8000
6102 || expr1.X_add_number >= 0x8000)
6103 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6105 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6106 tempreg, lw_reloc_type, mips_gp_register);
6107 macro_build (NULL, &icnt, NULL, "nop", "");
6108 p = frag_var (rs_machine_dependent, 4, 0,
6109 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
6110 offset_expr.X_add_symbol, 0, NULL);
6111 macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
6112 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
6114 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6115 tempreg, tempreg, breg);
6116 macro_build (NULL, &icnt, &expr1, s, fmt, treg, BFD_RELOC_LO16,
6119 else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
6124 /* If this is a reference to an external symbol, we want
6125 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6126 addu $tempreg,$tempreg,$gp
6127 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6128 <op> $treg,0($tempreg)
6130 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6132 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6133 <op> $treg,0($tempreg)
6134 If there is a base register, we add it to $tempreg before
6135 the <op>. If there is a constant, we stick it in the
6136 <op> instruction. We don't handle constants larger than
6137 16 bits, because we have no way to load the upper 16 bits
6138 (actually, we could handle them for the subset of cases
6139 in which we are not using $at). */
6140 assert (offset_expr.X_op == O_symbol);
6141 expr1.X_add_number = offset_expr.X_add_number;
6142 offset_expr.X_add_number = 0;
6143 if (expr1.X_add_number < -0x8000
6144 || expr1.X_add_number >= 0x8000)
6145 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6146 if (reg_needs_delay (mips_gp_register))
6151 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
6152 BFD_RELOC_MIPS_GOT_HI16);
6153 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6154 tempreg, tempreg, mips_gp_register);
6155 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6156 tempreg, BFD_RELOC_MIPS_GOT_LO16, tempreg);
6157 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
6158 RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0),
6159 offset_expr.X_add_symbol, 0, NULL);
6162 macro_build (p, &icnt, NULL, "nop", "");
6165 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6166 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
6168 macro_build (p, &icnt, NULL, "nop", "");
6170 macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6171 tempreg, tempreg, BFD_RELOC_LO16);
6173 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6174 tempreg, tempreg, breg);
6175 macro_build (NULL, &icnt, &expr1, s, fmt, treg, BFD_RELOC_LO16,
6178 else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
6181 int bregsz = breg != 0 ? 4 : 0;
6183 /* If this is a reference to an external symbol, we want
6184 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6185 add $tempreg,$tempreg,$gp
6186 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6187 <op> $treg,<ofst>($tempreg)
6188 Otherwise, for local symbols, we want:
6189 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6190 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6191 assert (offset_expr.X_op == O_symbol);
6192 frag_now->tc_frag_data.tc_fr_offset =
6193 expr1.X_add_number = offset_expr.X_add_number;
6194 offset_expr.X_add_number = 0;
6195 if (expr1.X_add_number < -0x8000
6196 || expr1.X_add_number >= 0x8000)
6197 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6199 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
6200 BFD_RELOC_MIPS_GOT_HI16);
6201 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6202 tempreg, tempreg, mips_gp_register);
6203 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6204 tempreg, BFD_RELOC_MIPS_GOT_LO16, tempreg);
6206 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6207 tempreg, tempreg, breg);
6208 macro_build (NULL, &icnt, &expr1, s, fmt, treg, BFD_RELOC_LO16,
6211 offset_expr.X_add_number = expr1.X_add_number;
6212 p = frag_var (rs_machine_dependent, 12 + bregsz, 0,
6213 RELAX_ENCODE (16 + bregsz, 8 + bregsz,
6214 0, 4 + bregsz, 0, 0),
6215 offset_expr.X_add_symbol, 0, NULL);
6216 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6217 tempreg, BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6219 macro_build (p + 4, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6220 tempreg, tempreg, breg);
6221 macro_build (p + 4 + bregsz, &icnt, &offset_expr, s, fmt, treg,
6222 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6224 else if (mips_pic == EMBEDDED_PIC)
6226 /* If there is no base register, we want
6227 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6228 If there is a base register, we want
6229 addu $tempreg,$breg,$gp
6230 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6232 assert (offset_expr.X_op == O_symbol);
6235 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
6236 BFD_RELOC_GPREL16, mips_gp_register);
6241 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6242 tempreg, breg, mips_gp_register);
6243 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
6244 BFD_RELOC_GPREL16, tempreg);
6257 load_register (&icnt, treg, &imm_expr, 0);
6261 load_register (&icnt, treg, &imm_expr, 1);
6265 if (imm_expr.X_op == O_constant)
6267 load_register (&icnt, AT, &imm_expr, 0);
6268 macro_build (NULL, &icnt, NULL, "mtc1", "t,G", AT, treg);
6273 assert (offset_expr.X_op == O_symbol
6274 && strcmp (segment_name (S_GET_SEGMENT
6275 (offset_expr.X_add_symbol)),
6277 && offset_expr.X_add_number == 0);
6278 macro_build (NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", treg,
6279 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6284 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6285 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6286 order 32 bits of the value and the low order 32 bits are either
6287 zero or in OFFSET_EXPR. */
6288 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6290 if (HAVE_64BIT_GPRS)
6291 load_register (&icnt, treg, &imm_expr, 1);
6296 if (target_big_endian)
6308 load_register (&icnt, hreg, &imm_expr, 0);
6311 if (offset_expr.X_op == O_absent)
6312 move_register (&icnt, lreg, 0);
6315 assert (offset_expr.X_op == O_constant);
6316 load_register (&icnt, lreg, &offset_expr, 0);
6323 /* We know that sym is in the .rdata section. First we get the
6324 upper 16 bits of the address. */
6325 if (mips_pic == NO_PIC)
6327 macro_build_lui (NULL, &icnt, &offset_expr, AT);
6329 else if (mips_pic == SVR4_PIC)
6331 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6332 AT, BFD_RELOC_MIPS_GOT16, mips_gp_register);
6334 else if (mips_pic == EMBEDDED_PIC)
6336 /* For embedded PIC we pick up the entire address off $gp in
6337 a single instruction. */
6338 macro_build (NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6339 AT, mips_gp_register, BFD_RELOC_GPREL16);
6340 offset_expr.X_op = O_constant;
6341 offset_expr.X_add_number = 0;
6346 /* Now we load the register(s). */
6347 if (HAVE_64BIT_GPRS)
6348 macro_build (NULL, &icnt, &offset_expr, "ld", "t,o(b)", treg,
6349 BFD_RELOC_LO16, AT);
6352 macro_build (NULL, &icnt, &offset_expr, "lw", "t,o(b)", treg,
6353 BFD_RELOC_LO16, AT);
6356 /* FIXME: How in the world do we deal with the possible
6358 offset_expr.X_add_number += 4;
6359 macro_build (NULL, &icnt, &offset_expr, "lw", "t,o(b)",
6360 treg + 1, BFD_RELOC_LO16, AT);
6364 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6365 does not become a variant frag. */
6366 frag_wane (frag_now);
6372 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6373 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6374 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6375 the value and the low order 32 bits are either zero or in
6377 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6379 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS);
6380 if (HAVE_64BIT_FPRS)
6382 assert (HAVE_64BIT_GPRS);
6383 macro_build (NULL, &icnt, NULL, "dmtc1", "t,S", AT, treg);
6387 macro_build (NULL, &icnt, NULL, "mtc1", "t,G", AT, treg + 1);
6388 if (offset_expr.X_op == O_absent)
6389 macro_build (NULL, &icnt, NULL, "mtc1", "t,G", 0, treg);
6392 assert (offset_expr.X_op == O_constant);
6393 load_register (&icnt, AT, &offset_expr, 0);
6394 macro_build (NULL, &icnt, NULL, "mtc1", "t,G", AT, treg);
6400 assert (offset_expr.X_op == O_symbol
6401 && offset_expr.X_add_number == 0);
6402 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
6403 if (strcmp (s, ".lit8") == 0)
6405 if (mips_opts.isa != ISA_MIPS1)
6407 macro_build (NULL, &icnt, &offset_expr, "ldc1", "T,o(b)", treg,
6408 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6411 breg = mips_gp_register;
6412 r = BFD_RELOC_MIPS_LITERAL;
6417 assert (strcmp (s, RDATA_SECTION_NAME) == 0);
6418 if (mips_pic == SVR4_PIC)
6419 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
6420 "t,o(b)", AT, BFD_RELOC_MIPS_GOT16,
6424 /* FIXME: This won't work for a 64 bit address. */
6425 macro_build_lui (NULL, &icnt, &offset_expr, AT);
6428 if (mips_opts.isa != ISA_MIPS1)
6430 macro_build (NULL, &icnt, &offset_expr, "ldc1", "T,o(b)", treg,
6431 BFD_RELOC_LO16, AT);
6433 /* To avoid confusion in tc_gen_reloc, we must ensure
6434 that this does not become a variant frag. */
6435 frag_wane (frag_now);
6446 if (mips_opts.arch == CPU_R4650)
6448 as_bad (_("opcode not supported on this processor"));
6451 /* Even on a big endian machine $fn comes before $fn+1. We have
6452 to adjust when loading from memory. */
6455 assert (mips_opts.isa == ISA_MIPS1);
6456 macro_build (NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
6457 target_big_endian ? treg + 1 : treg, r, breg);
6458 /* FIXME: A possible overflow which I don't know how to deal
6460 offset_expr.X_add_number += 4;
6461 macro_build (NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
6462 target_big_endian ? treg : treg + 1, r, breg);
6464 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6465 does not become a variant frag. */
6466 frag_wane (frag_now);
6475 * The MIPS assembler seems to check for X_add_number not
6476 * being double aligned and generating:
6479 * addiu at,at,%lo(foo+1)
6482 * But, the resulting address is the same after relocation so why
6483 * generate the extra instruction?
6485 if (mips_opts.arch == CPU_R4650)
6487 as_bad (_("opcode not supported on this processor"));
6490 /* Itbl support may require additional care here. */
6492 if (mips_opts.isa != ISA_MIPS1)
6503 if (mips_opts.arch == CPU_R4650)
6505 as_bad (_("opcode not supported on this processor"));
6509 if (mips_opts.isa != ISA_MIPS1)
6517 /* Itbl support may require additional care here. */
6522 if (HAVE_64BIT_GPRS)
6533 if (HAVE_64BIT_GPRS)
6543 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6544 loads for the case of doing a pair of loads to simulate an 'ld'.
6545 This is not currently done by the compiler, and assembly coders
6546 writing embedded-pic code can cope. */
6548 if (offset_expr.X_op != O_symbol
6549 && offset_expr.X_op != O_constant)
6551 as_bad (_("expression too complex"));
6552 offset_expr.X_op = O_constant;
6555 /* Even on a big endian machine $fn comes before $fn+1. We have
6556 to adjust when loading from memory. We set coproc if we must
6557 load $fn+1 first. */
6558 /* Itbl support may require additional care here. */
6559 if (! target_big_endian)
6562 if (mips_pic == NO_PIC
6563 || offset_expr.X_op == O_constant)
6567 /* If this is a reference to a GP relative symbol, we want
6568 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6569 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6570 If we have a base register, we use this
6572 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6573 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6574 If this is not a GP relative symbol, we want
6575 lui $at,<sym> (BFD_RELOC_HI16_S)
6576 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6577 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6578 If there is a base register, we add it to $at after the
6579 lui instruction. If there is a constant, we always use
6581 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6582 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6594 tempreg = mips_gp_register;
6601 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6602 AT, breg, mips_gp_register);
6608 /* Itbl support may require additional care here. */
6609 macro_build (NULL, &icnt, &offset_expr, s, fmt,
6610 coproc ? treg + 1 : treg,
6611 BFD_RELOC_GPREL16, tempreg);
6612 offset_expr.X_add_number += 4;
6614 /* Set mips_optimize to 2 to avoid inserting an
6616 hold_mips_optimize = mips_optimize;
6618 /* Itbl support may require additional care here. */
6619 macro_build (NULL, &icnt, &offset_expr, s, fmt,
6620 coproc ? treg : treg + 1,
6621 BFD_RELOC_GPREL16, tempreg);
6622 mips_optimize = hold_mips_optimize;
6624 p = frag_var (rs_machine_dependent, 12 + off, 0,
6625 RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1,
6626 used_at && mips_opts.noat),
6627 offset_expr.X_add_symbol, 0, NULL);
6629 /* We just generated two relocs. When tc_gen_reloc
6630 handles this case, it will skip the first reloc and
6631 handle the second. The second reloc already has an
6632 extra addend of 4, which we added above. We must
6633 subtract it out, and then subtract another 4 to make
6634 the first reloc come out right. The second reloc
6635 will come out right because we are going to add 4 to
6636 offset_expr when we build its instruction below.
6638 If we have a symbol, then we don't want to include
6639 the offset, because it will wind up being included
6640 when we generate the reloc. */
6642 if (offset_expr.X_op == O_constant)
6643 offset_expr.X_add_number -= 8;
6646 offset_expr.X_add_number = -4;
6647 offset_expr.X_op = O_constant;
6650 macro_build_lui (p, &icnt, &offset_expr, AT);
6655 macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6660 /* Itbl support may require additional care here. */
6661 macro_build (p, &icnt, &offset_expr, s, fmt,
6662 coproc ? treg + 1 : treg,
6663 BFD_RELOC_LO16, AT);
6666 /* FIXME: How do we handle overflow here? */
6667 offset_expr.X_add_number += 4;
6668 /* Itbl support may require additional care here. */
6669 macro_build (p, &icnt, &offset_expr, s, fmt,
6670 coproc ? treg : treg + 1,
6671 BFD_RELOC_LO16, AT);
6673 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6677 /* If this is a reference to an external symbol, we want
6678 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6683 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6685 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6686 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6687 If there is a base register we add it to $at before the
6688 lwc1 instructions. If there is a constant we include it
6689 in the lwc1 instructions. */
6691 expr1.X_add_number = offset_expr.X_add_number;
6692 offset_expr.X_add_number = 0;
6693 if (expr1.X_add_number < -0x8000
6694 || expr1.X_add_number >= 0x8000 - 4)
6695 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6700 frag_grow (24 + off);
6701 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6702 AT, BFD_RELOC_MIPS_GOT16, mips_gp_register);
6703 macro_build (NULL, &icnt, NULL, "nop", "");
6705 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6707 /* Itbl support may require additional care here. */
6708 macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg + 1 : treg,
6709 BFD_RELOC_LO16, AT);
6710 expr1.X_add_number += 4;
6712 /* Set mips_optimize to 2 to avoid inserting an undesired
6714 hold_mips_optimize = mips_optimize;
6716 /* Itbl support may require additional care here. */
6717 macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg : treg + 1,
6718 BFD_RELOC_LO16, AT);
6719 mips_optimize = hold_mips_optimize;
6721 (void) frag_var (rs_machine_dependent, 0, 0,
6722 RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0),
6723 offset_expr.X_add_symbol, 0, NULL);
6725 else if (mips_pic == SVR4_PIC)
6730 /* If this is a reference to an external symbol, we want
6731 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6733 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6738 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6740 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6741 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6742 If there is a base register we add it to $at before the
6743 lwc1 instructions. If there is a constant we include it
6744 in the lwc1 instructions. */
6746 expr1.X_add_number = offset_expr.X_add_number;
6747 offset_expr.X_add_number = 0;
6748 if (expr1.X_add_number < -0x8000
6749 || expr1.X_add_number >= 0x8000 - 4)
6750 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6751 if (reg_needs_delay (mips_gp_register))
6760 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", AT,
6761 BFD_RELOC_MIPS_GOT_HI16);
6762 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6763 AT, AT, mips_gp_register);
6764 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6765 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
6766 macro_build (NULL, &icnt, NULL, "nop", "");
6768 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6770 /* Itbl support may require additional care here. */
6771 macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg + 1 : treg,
6772 BFD_RELOC_LO16, AT);
6773 expr1.X_add_number += 4;
6775 /* Set mips_optimize to 2 to avoid inserting an undesired
6777 hold_mips_optimize = mips_optimize;
6779 /* Itbl support may require additional care here. */
6780 macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg : treg + 1,
6781 BFD_RELOC_LO16, AT);
6782 mips_optimize = hold_mips_optimize;
6783 expr1.X_add_number -= 4;
6785 p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0,
6786 RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel,
6787 8 + gpdel + off, 1, 0),
6788 offset_expr.X_add_symbol, 0, NULL);
6791 macro_build (p, &icnt, NULL, "nop", "");
6794 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6795 AT, BFD_RELOC_MIPS_GOT16, mips_gp_register);
6797 macro_build (p, &icnt, NULL, "nop", "");
6801 macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6805 /* Itbl support may require additional care here. */
6806 macro_build (p, &icnt, &expr1, s, fmt, coproc ? treg + 1 : treg,
6807 BFD_RELOC_LO16, AT);
6809 expr1.X_add_number += 4;
6811 /* Set mips_optimize to 2 to avoid inserting an undesired
6813 hold_mips_optimize = mips_optimize;
6815 /* Itbl support may require additional care here. */
6816 macro_build (p, &icnt, &expr1, s, fmt, coproc ? treg : treg + 1,
6817 BFD_RELOC_LO16, AT);
6818 mips_optimize = hold_mips_optimize;
6820 else if (mips_pic == EMBEDDED_PIC)
6822 /* If there is no base register, we use
6823 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6824 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6825 If we have a base register, we use
6827 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6828 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6832 tempreg = mips_gp_register;
6837 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6838 AT, breg, mips_gp_register);
6843 /* Itbl support may require additional care here. */
6844 macro_build (NULL, &icnt, &offset_expr, s, fmt,
6845 coproc ? treg + 1 : treg,
6846 BFD_RELOC_GPREL16, tempreg);
6847 offset_expr.X_add_number += 4;
6848 /* Itbl support may require additional care here. */
6849 macro_build (NULL, &icnt, &offset_expr, s, fmt,
6850 coproc ? treg : treg + 1,
6851 BFD_RELOC_GPREL16, tempreg);
6867 assert (HAVE_32BIT_ADDRESSES);
6868 macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
6869 BFD_RELOC_LO16, breg);
6870 offset_expr.X_add_number += 4;
6871 macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1,
6872 BFD_RELOC_LO16, breg);
6875 /* New code added to support COPZ instructions.
6876 This code builds table entries out of the macros in mip_opcodes.
6877 R4000 uses interlocks to handle coproc delays.
6878 Other chips (like the R3000) require nops to be inserted for delays.
6880 FIXME: Currently, we require that the user handle delays.
6881 In order to fill delay slots for non-interlocked chips,
6882 we must have a way to specify delays based on the coprocessor.
6883 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6884 What are the side-effects of the cop instruction?
6885 What cache support might we have and what are its effects?
6886 Both coprocessor & memory require delays. how long???
6887 What registers are read/set/modified?
6889 If an itbl is provided to interpret cop instructions,
6890 this knowledge can be encoded in the itbl spec. */
6904 /* For now we just do C (same as Cz). The parameter will be
6905 stored in insn_opcode by mips_ip. */
6906 macro_build (NULL, &icnt, NULL, s, "C", ip->insn_opcode);
6910 move_register (&icnt, dreg, sreg);
6913 #ifdef LOSING_COMPILER
6915 /* Try and see if this is a new itbl instruction.
6916 This code builds table entries out of the macros in mip_opcodes.
6917 FIXME: For now we just assemble the expression and pass it's
6918 value along as a 32-bit immediate.
6919 We may want to have the assembler assemble this value,
6920 so that we gain the assembler's knowledge of delay slots,
6922 Would it be more efficient to use mask (id) here? */
6923 if (itbl_have_entries
6924 && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
6926 s = ip->insn_mo->name;
6928 coproc = ITBL_DECODE_PNUM (immed_expr);;
6929 macro_build (NULL, &icnt, &immed_expr, s, "C");
6936 as_warn (_("Macro used $at after \".set noat\""));
6940 macro2 (struct mips_cl_insn *ip)
6942 register int treg, sreg, dreg, breg;
6958 bfd_reloc_code_real_type r;
6961 treg = (ip->insn_opcode >> 16) & 0x1f;
6962 dreg = (ip->insn_opcode >> 11) & 0x1f;
6963 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
6964 mask = ip->insn_mo->mask;
6966 expr1.X_op = O_constant;
6967 expr1.X_op_symbol = NULL;
6968 expr1.X_add_symbol = NULL;
6969 expr1.X_add_number = 1;
6973 #endif /* LOSING_COMPILER */
6978 macro_build (NULL, &icnt, NULL, dbl ? "dmultu" : "multu", "s,t",
6980 macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
6986 /* The MIPS assembler some times generates shifts and adds. I'm
6987 not trying to be that fancy. GCC should do this for us
6989 load_register (&icnt, AT, &imm_expr, dbl);
6990 macro_build (NULL, &icnt, NULL, dbl ? "dmult" : "mult", "s,t",
6992 macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
7005 mips_emit_delays (TRUE);
7006 ++mips_opts.noreorder;
7007 mips_any_noreorder = 1;
7009 load_register (&icnt, AT, &imm_expr, dbl);
7010 macro_build (NULL, &icnt, NULL, dbl ? "dmult" : "mult", "s,t",
7011 sreg, imm ? AT : treg);
7012 macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
7013 macro_build (NULL, &icnt, NULL, dbl ? "dsra32" : "sra", "d,w,<",
7015 macro_build (NULL, &icnt, NULL, "mfhi", "d", AT);
7017 macro_build (NULL, &icnt, NULL, "tne", "s,t,q", dreg, AT, 6);
7020 expr1.X_add_number = 8;
7021 macro_build (NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT);
7022 macro_build (NULL, &icnt, NULL, "nop", "", 0);
7023 macro_build (NULL, &icnt, NULL, "break", "c", 6);
7025 --mips_opts.noreorder;
7026 macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
7039 mips_emit_delays (TRUE);
7040 ++mips_opts.noreorder;
7041 mips_any_noreorder = 1;
7043 load_register (&icnt, AT, &imm_expr, dbl);
7044 macro_build (NULL, &icnt, NULL, dbl ? "dmultu" : "multu", "s,t",
7045 sreg, imm ? AT : treg);
7046 macro_build (NULL, &icnt, NULL, "mfhi", "d", AT);
7047 macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
7049 macro_build (NULL, &icnt, NULL, "tne", "s,t,q", AT, 0, 6);
7052 expr1.X_add_number = 8;
7053 macro_build (NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0);
7054 macro_build (NULL, &icnt, NULL, "nop", "", 0);
7055 macro_build (NULL, &icnt, NULL, "break", "c", 6);
7057 --mips_opts.noreorder;
7061 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7073 macro_build (NULL, &icnt, NULL, "dnegu", "d,w", tempreg, treg);
7074 macro_build (NULL, &icnt, NULL, "drorv", "d,t,s", dreg, sreg,
7080 macro_build (NULL, &icnt, NULL, "dsubu", "d,v,t", AT, 0, treg);
7081 macro_build (NULL, &icnt, NULL, "dsrlv", "d,t,s", AT, sreg, AT);
7082 macro_build (NULL, &icnt, NULL, "dsllv", "d,t,s", dreg, sreg, treg);
7083 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7087 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7099 macro_build (NULL, &icnt, NULL, "negu", "d,w", tempreg, treg);
7100 macro_build (NULL, &icnt, NULL, "rorv", "d,t,s", dreg, sreg,
7106 macro_build (NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg);
7107 macro_build (NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT);
7108 macro_build (NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, treg);
7109 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7117 if (imm_expr.X_op != O_constant)
7118 as_bad (_("Improper rotate count"));
7119 rot = imm_expr.X_add_number & 0x3f;
7120 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7122 rot = (64 - rot) & 0x3f;
7124 macro_build (NULL, &icnt, NULL, "dror32", "d,w,<",
7125 dreg, sreg, rot - 32);
7127 macro_build (NULL, &icnt, NULL, "dror", "d,w,<",
7133 macro_build (NULL, &icnt, NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7136 l = (rot < 0x20) ? "dsll" : "dsll32";
7137 r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
7139 macro_build (NULL, &icnt, NULL, l, "d,w,<", AT, sreg, rot);
7140 macro_build (NULL, &icnt, NULL, r, "d,w,<", dreg, sreg,
7141 (0x20 - rot) & 0x1f);
7142 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7150 if (imm_expr.X_op != O_constant)
7151 as_bad (_("Improper rotate count"));
7152 rot = imm_expr.X_add_number & 0x1f;
7153 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7155 macro_build (NULL, &icnt, NULL, "ror", "d,w,<", dreg, sreg,
7161 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, 0);
7164 macro_build (NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, rot);
7165 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg,
7166 (0x20 - rot) & 0x1f);
7167 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7172 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7174 macro_build (NULL, &icnt, NULL, "drorv", "d,t,s", dreg, sreg, treg);
7177 macro_build (NULL, &icnt,NULL, "dsubu", "d,v,t", AT, 0, treg);
7178 macro_build (NULL, &icnt, NULL, "dsllv", "d,t,s", AT, sreg, AT);
7179 macro_build (NULL, &icnt, NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
7180 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7184 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7186 macro_build (NULL, &icnt, NULL, "rorv", "d,t,s", dreg, sreg, treg);
7189 macro_build (NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg);
7190 macro_build (NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT);
7191 macro_build (NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, treg);
7192 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7200 if (imm_expr.X_op != O_constant)
7201 as_bad (_("Improper rotate count"));
7202 rot = imm_expr.X_add_number & 0x3f;
7203 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7206 macro_build (NULL, &icnt, NULL, "dror32", "d,w,<",
7207 dreg, sreg, rot - 32);
7209 macro_build (NULL, &icnt, NULL, "dror", "d,w,<",
7215 macro_build (NULL, &icnt, NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7218 r = (rot < 0x20) ? "dsrl" : "dsrl32";
7219 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7221 macro_build ( NULL, &icnt,NULL, r, "d,w,<", AT, sreg, rot);
7222 macro_build (NULL, &icnt, NULL, l, "d,w,<", dreg, sreg,
7223 (0x20 - rot) & 0x1f);
7224 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7232 if (imm_expr.X_op != O_constant)
7233 as_bad (_("Improper rotate count"));
7234 rot = imm_expr.X_add_number & 0x1f;
7235 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7237 macro_build (NULL, &icnt, NULL, "ror", "d,w,<", dreg, sreg, rot);
7242 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, 0);
7245 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, rot);
7246 macro_build (NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg,
7247 (0x20 - rot) & 0x1f);
7248 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7253 if (mips_opts.arch == CPU_R4650)
7255 as_bad (_("opcode not supported on this processor"));
7258 assert (mips_opts.isa == ISA_MIPS1);
7259 /* Even on a big endian machine $fn comes before $fn+1. We have
7260 to adjust when storing to memory. */
7261 macro_build (NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
7262 target_big_endian ? treg + 1 : treg,
7263 BFD_RELOC_LO16, breg);
7264 offset_expr.X_add_number += 4;
7265 macro_build (NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
7266 target_big_endian ? treg : treg + 1,
7267 BFD_RELOC_LO16, breg);
7272 macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, treg,
7275 macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, sreg,
7279 macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, treg);
7280 macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg,
7286 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7288 macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, sreg,
7294 as_warn (_("Instruction %s: result is always false"),
7296 move_register (&icnt, dreg, 0);
7299 if (imm_expr.X_op == O_constant
7300 && imm_expr.X_add_number >= 0
7301 && imm_expr.X_add_number < 0x10000)
7303 macro_build (NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, sreg,
7307 else if (imm_expr.X_op == O_constant
7308 && imm_expr.X_add_number > -0x8000
7309 && imm_expr.X_add_number < 0)
7311 imm_expr.X_add_number = -imm_expr.X_add_number;
7312 macro_build (NULL, &icnt, &imm_expr,
7313 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7314 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7319 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7320 macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, AT);
7323 macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg,
7329 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
7335 macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg);
7336 macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7340 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
7342 if (imm_expr.X_op == O_constant
7343 && imm_expr.X_add_number >= -0x8000
7344 && imm_expr.X_add_number < 0x8000)
7346 macro_build (NULL, &icnt, &imm_expr,
7347 mask == M_SGE_I ? "slti" : "sltiu",
7348 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7353 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7354 macro_build (NULL, &icnt, NULL, mask == M_SGE_I ? "slt" : "sltu",
7355 "d,v,t", dreg, sreg, AT);
7358 macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7364 case M_SGT: /* sreg > treg <==> treg < sreg */
7370 macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg);
7373 case M_SGT_I: /* sreg > I <==> I < sreg */
7379 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7380 macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg);
7383 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7389 macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg);
7390 macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7394 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7400 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7401 macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg);
7402 macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7407 if (imm_expr.X_op == O_constant
7408 && imm_expr.X_add_number >= -0x8000
7409 && imm_expr.X_add_number < 0x8000)
7411 macro_build (NULL, &icnt, &imm_expr, "slti", "t,r,j", dreg, sreg,
7415 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7416 macro_build (NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT);
7420 if (imm_expr.X_op == O_constant
7421 && imm_expr.X_add_number >= -0x8000
7422 && imm_expr.X_add_number < 0x8000)
7424 macro_build (NULL, &icnt, &imm_expr, "sltiu", "t,r,j", dreg, sreg,
7428 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7429 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, AT);
7434 macro_build (NULL, &icnt,NULL, "sltu","d,v,t", dreg, 0, treg);
7436 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, sreg);
7439 macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, treg);
7440 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg);
7445 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7447 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, sreg);
7452 as_warn (_("Instruction %s: result is always true"),
7454 macro_build (NULL, &icnt, &expr1,
7455 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7456 "t,r,j", dreg, 0, BFD_RELOC_LO16);
7459 if (imm_expr.X_op == O_constant
7460 && imm_expr.X_add_number >= 0
7461 && imm_expr.X_add_number < 0x10000)
7463 macro_build (NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, sreg,
7467 else if (imm_expr.X_op == O_constant
7468 && imm_expr.X_add_number > -0x8000
7469 && imm_expr.X_add_number < 0)
7471 imm_expr.X_add_number = -imm_expr.X_add_number;
7472 macro_build (NULL, &icnt, &imm_expr,
7473 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7474 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7479 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7480 macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, AT);
7483 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg);
7491 if (imm_expr.X_op == O_constant
7492 && imm_expr.X_add_number > -0x8000
7493 && imm_expr.X_add_number <= 0x8000)
7495 imm_expr.X_add_number = -imm_expr.X_add_number;
7496 macro_build (NULL, &icnt, &imm_expr, dbl ? "daddi" : "addi",
7497 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7500 load_register (&icnt, AT, &imm_expr, dbl);
7501 macro_build (NULL, &icnt, NULL, dbl ? "dsub" : "sub", "d,v,t",
7508 if (imm_expr.X_op == O_constant
7509 && imm_expr.X_add_number > -0x8000
7510 && imm_expr.X_add_number <= 0x8000)
7512 imm_expr.X_add_number = -imm_expr.X_add_number;
7513 macro_build (NULL, &icnt, &imm_expr, dbl ? "daddiu" : "addiu",
7514 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7517 load_register (&icnt, AT, &imm_expr, dbl);
7518 macro_build (NULL, &icnt, NULL, dbl ? "dsubu" : "subu", "d,v,t",
7540 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7541 macro_build (NULL, &icnt, NULL, s, "s,t", sreg, AT);
7546 assert (mips_opts.isa == ISA_MIPS1);
7547 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
7548 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
7551 * Is the double cfc1 instruction a bug in the mips assembler;
7552 * or is there a reason for it?
7554 mips_emit_delays (TRUE);
7555 ++mips_opts.noreorder;
7556 mips_any_noreorder = 1;
7557 macro_build (NULL, &icnt, NULL, "cfc1", "t,G", treg, RA);
7558 macro_build (NULL, &icnt, NULL, "cfc1", "t,G", treg, RA);
7559 macro_build (NULL, &icnt, NULL, "nop", "");
7560 expr1.X_add_number = 3;
7561 macro_build (NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg,
7563 expr1.X_add_number = 2;
7564 macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT,
7566 macro_build (NULL, &icnt, NULL, "ctc1", "t,G", AT, RA);
7567 macro_build (NULL, &icnt, NULL, "nop", "");
7568 macro_build (NULL, &icnt, NULL,
7569 mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s",
7571 macro_build (NULL, &icnt, NULL, "ctc1", "t,G", treg, RA);
7572 macro_build (NULL, &icnt, NULL, "nop", "");
7573 --mips_opts.noreorder;
7582 if (offset_expr.X_add_number >= 0x7fff)
7583 as_bad (_("operand overflow"));
7584 if (! target_big_endian)
7585 ++offset_expr.X_add_number;
7586 macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", AT,
7587 BFD_RELOC_LO16, breg);
7588 if (! target_big_endian)
7589 --offset_expr.X_add_number;
7591 ++offset_expr.X_add_number;
7592 macro_build (NULL, &icnt, &offset_expr, "lbu", "t,o(b)", treg,
7593 BFD_RELOC_LO16, breg);
7594 macro_build (NULL, &icnt, NULL, "sll", "d,w,<", AT, AT, 8);
7595 macro_build (NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT);
7608 if (offset_expr.X_add_number >= 0x8000 - off)
7609 as_bad (_("operand overflow"));
7614 if (! target_big_endian)
7615 offset_expr.X_add_number += off;
7616 macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", tempreg,
7617 BFD_RELOC_LO16, breg);
7618 if (! target_big_endian)
7619 offset_expr.X_add_number -= off;
7621 offset_expr.X_add_number += off;
7622 macro_build (NULL, &icnt, &offset_expr, s2, "t,o(b)", tempreg,
7623 BFD_RELOC_LO16, breg);
7625 /* If necessary, move the result in tempreg the final destination. */
7626 if (treg == tempreg)
7628 /* Protect second load's delay slot. */
7629 if (!gpr_interlocks)
7630 macro_build (NULL, &icnt, NULL, "nop", "");
7631 move_register (&icnt, treg, tempreg);
7645 load_address (&icnt, AT, &offset_expr, &used_at);
7647 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
7649 if (! target_big_endian)
7650 expr1.X_add_number = off;
7652 expr1.X_add_number = 0;
7653 macro_build (NULL, &icnt, &expr1, s, "t,o(b)", treg,
7654 BFD_RELOC_LO16, AT);
7655 if (! target_big_endian)
7656 expr1.X_add_number = 0;
7658 expr1.X_add_number = off;
7659 macro_build (NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7660 BFD_RELOC_LO16, AT);
7666 load_address (&icnt, AT, &offset_expr, &used_at);
7668 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
7670 if (target_big_endian)
7671 expr1.X_add_number = 0;
7672 macro_build (NULL, &icnt, &expr1,
7673 mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
7674 treg, BFD_RELOC_LO16, AT);
7675 if (target_big_endian)
7676 expr1.X_add_number = 1;
7678 expr1.X_add_number = 0;
7679 macro_build (NULL, &icnt, &expr1, "lbu", "t,o(b)",
7680 AT, BFD_RELOC_LO16, AT);
7681 macro_build (NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8);
7682 macro_build (NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT);
7686 if (offset_expr.X_add_number >= 0x7fff)
7687 as_bad (_("operand overflow"));
7688 if (target_big_endian)
7689 ++offset_expr.X_add_number;
7690 macro_build (NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg,
7691 BFD_RELOC_LO16, breg);
7692 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8);
7693 if (target_big_endian)
7694 --offset_expr.X_add_number;
7696 ++offset_expr.X_add_number;
7697 macro_build (NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT,
7698 BFD_RELOC_LO16, breg);
7711 if (offset_expr.X_add_number >= 0x8000 - off)
7712 as_bad (_("operand overflow"));
7713 if (! target_big_endian)
7714 offset_expr.X_add_number += off;
7715 macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7716 BFD_RELOC_LO16, breg);
7717 if (! target_big_endian)
7718 offset_expr.X_add_number -= off;
7720 offset_expr.X_add_number += off;
7721 macro_build (NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
7722 BFD_RELOC_LO16, breg);
7736 load_address (&icnt, AT, &offset_expr, &used_at);
7738 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
7740 if (! target_big_endian)
7741 expr1.X_add_number = off;
7743 expr1.X_add_number = 0;
7744 macro_build (NULL, &icnt, &expr1, s, "t,o(b)", treg,
7745 BFD_RELOC_LO16, AT);
7746 if (! target_big_endian)
7747 expr1.X_add_number = 0;
7749 expr1.X_add_number = off;
7750 macro_build (NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7751 BFD_RELOC_LO16, AT);
7756 load_address (&icnt, AT, &offset_expr, &used_at);
7758 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
7760 if (! target_big_endian)
7761 expr1.X_add_number = 0;
7762 macro_build (NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7763 BFD_RELOC_LO16, AT);
7764 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", treg, treg, 8);
7765 if (! target_big_endian)
7766 expr1.X_add_number = 1;
7768 expr1.X_add_number = 0;
7769 macro_build (NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7770 BFD_RELOC_LO16, AT);
7771 if (! target_big_endian)
7772 expr1.X_add_number = 0;
7774 expr1.X_add_number = 1;
7775 macro_build (NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
7776 BFD_RELOC_LO16, AT);
7777 macro_build (NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8);
7778 macro_build (NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT);
7782 /* FIXME: Check if this is one of the itbl macros, since they
7783 are added dynamically. */
7784 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
7788 as_warn (_("Macro used $at after \".set noat\""));
7791 /* Implement macros in mips16 mode. */
7794 mips16_macro (struct mips_cl_insn *ip)
7797 int xreg, yreg, zreg, tmp;
7801 const char *s, *s2, *s3;
7803 mask = ip->insn_mo->mask;
7805 xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
7806 yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY;
7807 zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
7811 expr1.X_op = O_constant;
7812 expr1.X_op_symbol = NULL;
7813 expr1.X_add_symbol = NULL;
7814 expr1.X_add_number = 1;
7833 mips_emit_delays (TRUE);
7834 ++mips_opts.noreorder;
7835 mips_any_noreorder = 1;
7836 macro_build (NULL, &icnt, NULL, dbl ? "ddiv" : "div", "0,x,y",
7838 expr1.X_add_number = 2;
7839 macro_build (NULL, &icnt, &expr1, "bnez", "x,p", yreg);
7840 macro_build (NULL, &icnt, NULL, "break", "6", 7);
7842 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7843 since that causes an overflow. We should do that as well,
7844 but I don't see how to do the comparisons without a temporary
7846 --mips_opts.noreorder;
7847 macro_build (NULL, &icnt, NULL, s, "x", zreg);
7866 mips_emit_delays (TRUE);
7867 ++mips_opts.noreorder;
7868 mips_any_noreorder = 1;
7869 macro_build (NULL, &icnt, NULL, s, "0,x,y", xreg, yreg);
7870 expr1.X_add_number = 2;
7871 macro_build (NULL, &icnt, &expr1, "bnez", "x,p", yreg);
7872 macro_build (NULL, &icnt, NULL, "break", "6", 7);
7873 --mips_opts.noreorder;
7874 macro_build (NULL, &icnt, NULL, s2, "x", zreg);
7880 macro_build (NULL, &icnt, NULL, dbl ? "dmultu" : "multu", "x,y",
7882 macro_build (NULL, &icnt, NULL, "mflo", "x", zreg);
7890 if (imm_expr.X_op != O_constant)
7891 as_bad (_("Unsupported large constant"));
7892 imm_expr.X_add_number = -imm_expr.X_add_number;
7893 macro_build (NULL, &icnt, &imm_expr, dbl ? "daddiu" : "addiu", "y,x,4",
7898 if (imm_expr.X_op != O_constant)
7899 as_bad (_("Unsupported large constant"));
7900 imm_expr.X_add_number = -imm_expr.X_add_number;
7901 macro_build (NULL, &icnt, &imm_expr, "addiu", "x,k", xreg);
7905 if (imm_expr.X_op != O_constant)
7906 as_bad (_("Unsupported large constant"));
7907 imm_expr.X_add_number = -imm_expr.X_add_number;
7908 macro_build (NULL, &icnt, &imm_expr, "daddiu", "y,j", yreg);
7930 goto do_reverse_branch;
7934 goto do_reverse_branch;
7946 goto do_reverse_branch;
7957 macro_build (NULL, &icnt, NULL, s, "x,y", xreg, yreg);
7958 macro_build (NULL, &icnt, &offset_expr, s2, "p");
7985 goto do_addone_branch_i;
7990 goto do_addone_branch_i;
8005 goto do_addone_branch_i;
8012 if (imm_expr.X_op != O_constant)
8013 as_bad (_("Unsupported large constant"));
8014 ++imm_expr.X_add_number;
8017 macro_build (NULL, &icnt, &imm_expr, s, s3, xreg);
8018 macro_build (NULL, &icnt, &offset_expr, s2, "p");
8022 expr1.X_add_number = 0;
8023 macro_build (NULL, &icnt, &expr1, "slti", "x,8", yreg);
8025 move_register (&icnt, xreg, yreg);
8026 expr1.X_add_number = 2;
8027 macro_build (NULL, &icnt, &expr1, "bteqz", "p");
8028 macro_build (NULL, &icnt, NULL, "neg", "x,w", xreg, xreg);
8032 /* For consistency checking, verify that all bits are specified either
8033 by the match/mask part of the instruction definition, or by the
8036 validate_mips_insn (const struct mips_opcode *opc)
8038 const char *p = opc->args;
8040 unsigned long used_bits = opc->mask;
8042 if ((used_bits & opc->match) != opc->match)
8044 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8045 opc->name, opc->args);
8048 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8058 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8059 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8060 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8061 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
8062 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8064 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8065 c, opc->name, opc->args);
8069 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8070 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8072 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
8073 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
8074 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8075 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8077 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8078 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8080 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
8081 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8083 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
8084 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
8085 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
8086 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
8087 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8088 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
8089 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8090 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8091 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8092 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8093 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8094 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8095 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8096 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
8097 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8098 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
8099 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8101 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
8102 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8103 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8104 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
8106 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8107 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8108 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
8109 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8110 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8111 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8112 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8113 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8114 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8117 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
8118 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
8119 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8120 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
8121 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
8125 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8126 c, opc->name, opc->args);
8130 if (used_bits != 0xffffffff)
8132 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8133 ~used_bits & 0xffffffff, opc->name, opc->args);
8139 /* This routine assembles an instruction into its binary format. As a
8140 side effect, it sets one of the global variables imm_reloc or
8141 offset_reloc to the type of relocation to do if one of the operands
8142 is an address expression. */
8145 mips_ip (char *str, struct mips_cl_insn *ip)
8150 struct mips_opcode *insn;
8153 unsigned int lastregno = 0;
8154 unsigned int lastpos = 0;
8155 unsigned int limlo, limhi;
8161 /* If the instruction contains a '.', we first try to match an instruction
8162 including the '.'. Then we try again without the '.'. */
8164 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
8167 /* If we stopped on whitespace, then replace the whitespace with null for
8168 the call to hash_find. Save the character we replaced just in case we
8169 have to re-parse the instruction. */
8176 insn = (struct mips_opcode *) hash_find (op_hash, str);
8178 /* If we didn't find the instruction in the opcode table, try again, but
8179 this time with just the instruction up to, but not including the
8183 /* Restore the character we overwrite above (if any). */
8187 /* Scan up to the first '.' or whitespace. */
8189 *s != '\0' && *s != '.' && !ISSPACE (*s);
8193 /* If we did not find a '.', then we can quit now. */
8196 insn_error = "unrecognized opcode";
8200 /* Lookup the instruction in the hash table. */
8202 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
8204 insn_error = "unrecognized opcode";
8214 assert (strcmp (insn->name, str) == 0);
8216 if (OPCODE_IS_MEMBER (insn,
8218 | (file_ase_mips16 ? INSN_MIPS16 : 0)
8219 | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
8220 | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
8226 if (insn->pinfo != INSN_MACRO)
8228 if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)
8234 if (insn + 1 < &mips_opcodes[NUMOPCODES]
8235 && strcmp (insn->name, insn[1].name) == 0)
8244 static char buf[100];
8246 _("opcode not supported on this processor: %s (%s)"),
8247 mips_cpu_info_from_arch (mips_opts.arch)->name,
8248 mips_cpu_info_from_isa (mips_opts.isa)->name);
8258 ip->insn_opcode = insn->match;
8260 for (args = insn->args;; ++args)
8264 s += strspn (s, " \t");
8268 case '\0': /* end of args */
8281 ip->insn_opcode |= lastregno << OP_SH_RS;
8285 ip->insn_opcode |= lastregno << OP_SH_RT;
8289 ip->insn_opcode |= lastregno << OP_SH_FT;
8293 ip->insn_opcode |= lastregno << OP_SH_FS;
8299 /* Handle optional base register.
8300 Either the base register is omitted or
8301 we must have a left paren. */
8302 /* This is dependent on the next operand specifier
8303 is a base register specification. */
8304 assert (args[1] == 'b' || args[1] == '5'
8305 || args[1] == '-' || args[1] == '4');
8309 case ')': /* these must match exactly */
8316 case '+': /* Opcode extension character. */
8319 case 'A': /* ins/ext position, becomes LSB. */
8322 my_getExpression (&imm_expr, s);
8323 check_absolute_expr (ip, &imm_expr);
8324 if ((unsigned long) imm_expr.X_add_number < limlo
8325 || (unsigned long) imm_expr.X_add_number > limhi)
8327 as_bad (_("Improper position (%lu)"),
8328 (unsigned long) imm_expr.X_add_number);
8329 imm_expr.X_add_number = limlo;
8331 lastpos = imm_expr.X_add_number;
8332 ip->insn_opcode |= (imm_expr.X_add_number
8333 & OP_MASK_SHAMT) << OP_SH_SHAMT;
8334 imm_expr.X_op = O_absent;
8338 case 'B': /* ins size, becomes MSB. */
8341 my_getExpression (&imm_expr, s);
8342 check_absolute_expr (ip, &imm_expr);
8343 /* Check for negative input so that small negative numbers
8344 will not succeed incorrectly. The checks against
8345 (pos+size) transitively check "size" itself,
8346 assuming that "pos" is reasonable. */
8347 if ((long) imm_expr.X_add_number < 0
8348 || ((unsigned long) imm_expr.X_add_number
8350 || ((unsigned long) imm_expr.X_add_number
8353 as_bad (_("Improper insert size (%lu, position %lu)"),
8354 (unsigned long) imm_expr.X_add_number,
8355 (unsigned long) lastpos);
8356 imm_expr.X_add_number = limlo - lastpos;
8358 ip->insn_opcode |= ((lastpos + imm_expr.X_add_number - 1)
8359 & OP_MASK_INSMSB) << OP_SH_INSMSB;
8360 imm_expr.X_op = O_absent;
8364 case 'C': /* ext size, becomes MSBD. */
8367 my_getExpression (&imm_expr, s);
8368 check_absolute_expr (ip, &imm_expr);
8369 /* Check for negative input so that small negative numbers
8370 will not succeed incorrectly. The checks against
8371 (pos+size) transitively check "size" itself,
8372 assuming that "pos" is reasonable. */
8373 if ((long) imm_expr.X_add_number < 0
8374 || ((unsigned long) imm_expr.X_add_number
8376 || ((unsigned long) imm_expr.X_add_number
8379 as_bad (_("Improper extract size (%lu, position %lu)"),
8380 (unsigned long) imm_expr.X_add_number,
8381 (unsigned long) lastpos);
8382 imm_expr.X_add_number = limlo - lastpos;
8384 ip->insn_opcode |= ((imm_expr.X_add_number - 1)
8385 & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD;
8386 imm_expr.X_op = O_absent;
8391 /* +D is for disassembly only; never match. */
8395 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8396 *args, insn->name, insn->args);
8397 /* Further processing is fruitless. */
8402 case '<': /* must be at least one digit */
8404 * According to the manual, if the shift amount is greater
8405 * than 31 or less than 0, then the shift amount should be
8406 * mod 32. In reality the mips assembler issues an error.
8407 * We issue a warning and mask out all but the low 5 bits.
8409 my_getExpression (&imm_expr, s);
8410 check_absolute_expr (ip, &imm_expr);
8411 if ((unsigned long) imm_expr.X_add_number > 31)
8413 as_warn (_("Improper shift amount (%lu)"),
8414 (unsigned long) imm_expr.X_add_number);
8415 imm_expr.X_add_number &= OP_MASK_SHAMT;
8417 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT;
8418 imm_expr.X_op = O_absent;
8422 case '>': /* shift amount minus 32 */
8423 my_getExpression (&imm_expr, s);
8424 check_absolute_expr (ip, &imm_expr);
8425 if ((unsigned long) imm_expr.X_add_number < 32
8426 || (unsigned long) imm_expr.X_add_number > 63)
8428 ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT;
8429 imm_expr.X_op = O_absent;
8433 case 'k': /* cache code */
8434 case 'h': /* prefx code */
8435 my_getExpression (&imm_expr, s);
8436 check_absolute_expr (ip, &imm_expr);
8437 if ((unsigned long) imm_expr.X_add_number > 31)
8439 as_warn (_("Invalid value for `%s' (%lu)"),
8441 (unsigned long) imm_expr.X_add_number);
8442 imm_expr.X_add_number &= 0x1f;
8445 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE;
8447 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX;
8448 imm_expr.X_op = O_absent;
8452 case 'c': /* break code */
8453 my_getExpression (&imm_expr, s);
8454 check_absolute_expr (ip, &imm_expr);
8455 if ((unsigned long) imm_expr.X_add_number > 1023)
8457 as_warn (_("Illegal break code (%lu)"),
8458 (unsigned long) imm_expr.X_add_number);
8459 imm_expr.X_add_number &= OP_MASK_CODE;
8461 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE;
8462 imm_expr.X_op = O_absent;
8466 case 'q': /* lower break code */
8467 my_getExpression (&imm_expr, s);
8468 check_absolute_expr (ip, &imm_expr);
8469 if ((unsigned long) imm_expr.X_add_number > 1023)
8471 as_warn (_("Illegal lower break code (%lu)"),
8472 (unsigned long) imm_expr.X_add_number);
8473 imm_expr.X_add_number &= OP_MASK_CODE2;
8475 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2;
8476 imm_expr.X_op = O_absent;
8480 case 'B': /* 20-bit syscall/break code. */
8481 my_getExpression (&imm_expr, s);
8482 check_absolute_expr (ip, &imm_expr);
8483 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
8484 as_warn (_("Illegal 20-bit code (%lu)"),
8485 (unsigned long) imm_expr.X_add_number);
8486 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20;
8487 imm_expr.X_op = O_absent;
8491 case 'C': /* Coprocessor code */
8492 my_getExpression (&imm_expr, s);
8493 check_absolute_expr (ip, &imm_expr);
8494 if ((unsigned long) imm_expr.X_add_number >= (1 << 25))
8496 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8497 (unsigned long) imm_expr.X_add_number);
8498 imm_expr.X_add_number &= ((1 << 25) - 1);
8500 ip->insn_opcode |= imm_expr.X_add_number;
8501 imm_expr.X_op = O_absent;
8505 case 'J': /* 19-bit wait code. */
8506 my_getExpression (&imm_expr, s);
8507 check_absolute_expr (ip, &imm_expr);
8508 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
8509 as_warn (_("Illegal 19-bit code (%lu)"),
8510 (unsigned long) imm_expr.X_add_number);
8511 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19;
8512 imm_expr.X_op = O_absent;
8516 case 'P': /* Performance register */
8517 my_getExpression (&imm_expr, s);
8518 check_absolute_expr (ip, &imm_expr);
8519 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
8521 as_warn (_("Invalid performance register (%lu)"),
8522 (unsigned long) imm_expr.X_add_number);
8523 imm_expr.X_add_number &= OP_MASK_PERFREG;
8525 ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG);
8526 imm_expr.X_op = O_absent;
8530 case 'b': /* base register */
8531 case 'd': /* destination register */
8532 case 's': /* source register */
8533 case 't': /* target register */
8534 case 'r': /* both target and source */
8535 case 'v': /* both dest and source */
8536 case 'w': /* both dest and target */
8537 case 'E': /* coprocessor target register */
8538 case 'G': /* coprocessor destination register */
8539 case 'K': /* 'rdhwr' destination register */
8540 case 'x': /* ignore register name */
8541 case 'z': /* must be zero register */
8542 case 'U': /* destination register (clo/clz). */
8557 while (ISDIGIT (*s));
8559 as_bad (_("Invalid register number (%d)"), regno);
8561 else if (*args == 'E' || *args == 'G' || *args == 'K')
8565 if (s[1] == 'r' && s[2] == 'a')
8570 else if (s[1] == 'f' && s[2] == 'p')
8575 else if (s[1] == 's' && s[2] == 'p')
8580 else if (s[1] == 'g' && s[2] == 'p')
8585 else if (s[1] == 'a' && s[2] == 't')
8590 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
8595 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
8600 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
8605 else if (itbl_have_entries)
8610 p = s + 1; /* advance past '$' */
8611 n = itbl_get_field (&p); /* n is name */
8613 /* See if this is a register defined in an
8615 if (itbl_get_reg_val (n, &r))
8617 /* Get_field advances to the start of
8618 the next field, so we need to back
8619 rack to the end of the last field. */
8623 s = strchr (s, '\0');
8637 as_warn (_("Used $at without \".set noat\""));
8643 if (c == 'r' || c == 'v' || c == 'w')
8650 /* 'z' only matches $0. */
8651 if (c == 'z' && regno != 0)
8654 /* Now that we have assembled one operand, we use the args string
8655 * to figure out where it goes in the instruction. */
8662 ip->insn_opcode |= regno << OP_SH_RS;
8667 ip->insn_opcode |= regno << OP_SH_RD;
8670 ip->insn_opcode |= regno << OP_SH_RD;
8671 ip->insn_opcode |= regno << OP_SH_RT;
8676 ip->insn_opcode |= regno << OP_SH_RT;
8679 /* This case exists because on the r3000 trunc
8680 expands into a macro which requires a gp
8681 register. On the r6000 or r4000 it is
8682 assembled into a single instruction which
8683 ignores the register. Thus the insn version
8684 is MIPS_ISA2 and uses 'x', and the macro
8685 version is MIPS_ISA1 and uses 't'. */
8688 /* This case is for the div instruction, which
8689 acts differently if the destination argument
8690 is $0. This only matches $0, and is checked
8691 outside the switch. */
8694 /* Itbl operand; not yet implemented. FIXME ?? */
8696 /* What about all other operands like 'i', which
8697 can be specified in the opcode table? */
8707 ip->insn_opcode |= lastregno << OP_SH_RS;
8710 ip->insn_opcode |= lastregno << OP_SH_RT;
8715 case 'O': /* MDMX alignment immediate constant. */
8716 my_getExpression (&imm_expr, s);
8717 check_absolute_expr (ip, &imm_expr);
8718 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
8720 as_warn ("Improper align amount (%ld), using low bits",
8721 (long) imm_expr.X_add_number);
8722 imm_expr.X_add_number &= OP_MASK_ALN;
8724 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN;
8725 imm_expr.X_op = O_absent;
8729 case 'Q': /* MDMX vector, element sel, or const. */
8732 /* MDMX Immediate. */
8733 my_getExpression (&imm_expr, s);
8734 check_absolute_expr (ip, &imm_expr);
8735 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
8737 as_warn (_("Invalid MDMX Immediate (%ld)"),
8738 (long) imm_expr.X_add_number);
8739 imm_expr.X_add_number &= OP_MASK_FT;
8741 imm_expr.X_add_number &= OP_MASK_FT;
8742 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8743 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
8745 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
8746 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT;
8747 imm_expr.X_op = O_absent;
8751 /* Not MDMX Immediate. Fall through. */
8752 case 'X': /* MDMX destination register. */
8753 case 'Y': /* MDMX source register. */
8754 case 'Z': /* MDMX target register. */
8756 case 'D': /* floating point destination register */
8757 case 'S': /* floating point source register */
8758 case 'T': /* floating point target register */
8759 case 'R': /* floating point source register */
8763 /* Accept $fN for FP and MDMX register numbers, and in
8764 addition accept $vN for MDMX register numbers. */
8765 if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2]))
8766 || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v'
8777 while (ISDIGIT (*s));
8780 as_bad (_("Invalid float register number (%d)"), regno);
8782 if ((regno & 1) != 0
8784 && ! (strcmp (str, "mtc1") == 0
8785 || strcmp (str, "mfc1") == 0
8786 || strcmp (str, "lwc1") == 0
8787 || strcmp (str, "swc1") == 0
8788 || strcmp (str, "l.s") == 0
8789 || strcmp (str, "s.s") == 0))
8790 as_warn (_("Float register should be even, was %d"),
8798 if (c == 'V' || c == 'W')
8809 ip->insn_opcode |= regno << OP_SH_FD;
8814 ip->insn_opcode |= regno << OP_SH_FS;
8817 /* This is like 'Z', but also needs to fix the MDMX
8818 vector/scalar select bits. Note that the
8819 scalar immediate case is handled above. */
8822 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
8823 int max_el = (is_qh ? 3 : 7);
8825 my_getExpression(&imm_expr, s);
8826 check_absolute_expr (ip, &imm_expr);
8828 if (imm_expr.X_add_number > max_el)
8829 as_bad(_("Bad element selector %ld"),
8830 (long) imm_expr.X_add_number);
8831 imm_expr.X_add_number &= max_el;
8832 ip->insn_opcode |= (imm_expr.X_add_number
8836 as_warn(_("Expecting ']' found '%s'"), s);
8842 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8843 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
8846 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
8853 ip->insn_opcode |= regno << OP_SH_FT;
8856 ip->insn_opcode |= regno << OP_SH_FR;
8866 ip->insn_opcode |= lastregno << OP_SH_FS;
8869 ip->insn_opcode |= lastregno << OP_SH_FT;
8875 my_getExpression (&imm_expr, s);
8876 if (imm_expr.X_op != O_big
8877 && imm_expr.X_op != O_constant)
8878 insn_error = _("absolute expression required");
8883 my_getExpression (&offset_expr, s);
8884 *imm_reloc = BFD_RELOC_32;
8897 unsigned char temp[8];
8899 unsigned int length;
8904 /* These only appear as the last operand in an
8905 instruction, and every instruction that accepts
8906 them in any variant accepts them in all variants.
8907 This means we don't have to worry about backing out
8908 any changes if the instruction does not match.
8910 The difference between them is the size of the
8911 floating point constant and where it goes. For 'F'
8912 and 'L' the constant is 64 bits; for 'f' and 'l' it
8913 is 32 bits. Where the constant is placed is based
8914 on how the MIPS assembler does things:
8917 f -- immediate value
8920 The .lit4 and .lit8 sections are only used if
8921 permitted by the -G argument.
8923 When generating embedded PIC code, we use the
8924 .lit8 section but not the .lit4 section (we can do
8925 .lit4 inline easily; we need to put .lit8
8926 somewhere in the data segment, and using .lit8
8927 permits the linker to eventually combine identical
8930 The code below needs to know whether the target register
8931 is 32 or 64 bits wide. It relies on the fact 'f' and
8932 'F' are used with GPR-based instructions and 'l' and
8933 'L' are used with FPR-based instructions. */
8935 f64 = *args == 'F' || *args == 'L';
8936 using_gprs = *args == 'F' || *args == 'f';
8938 save_in = input_line_pointer;
8939 input_line_pointer = s;
8940 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
8942 s = input_line_pointer;
8943 input_line_pointer = save_in;
8944 if (err != NULL && *err != '\0')
8946 as_bad (_("Bad floating point constant: %s"), err);
8947 memset (temp, '\0', sizeof temp);
8948 length = f64 ? 8 : 4;
8951 assert (length == (unsigned) (f64 ? 8 : 4));
8955 && (! USE_GLOBAL_POINTER_OPT
8956 || mips_pic == EMBEDDED_PIC
8957 || g_switch_value < 4
8958 || (temp[0] == 0 && temp[1] == 0)
8959 || (temp[2] == 0 && temp[3] == 0))))
8961 imm_expr.X_op = O_constant;
8962 if (! target_big_endian)
8963 imm_expr.X_add_number = bfd_getl32 (temp);
8965 imm_expr.X_add_number = bfd_getb32 (temp);
8968 && ! mips_disable_float_construction
8969 /* Constants can only be constructed in GPRs and
8970 copied to FPRs if the GPRs are at least as wide
8971 as the FPRs. Force the constant into memory if
8972 we are using 64-bit FPRs but the GPRs are only
8975 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
8976 && ((temp[0] == 0 && temp[1] == 0)
8977 || (temp[2] == 0 && temp[3] == 0))
8978 && ((temp[4] == 0 && temp[5] == 0)
8979 || (temp[6] == 0 && temp[7] == 0)))
8981 /* The value is simple enough to load with a couple of
8982 instructions. If using 32-bit registers, set
8983 imm_expr to the high order 32 bits and offset_expr to
8984 the low order 32 bits. Otherwise, set imm_expr to
8985 the entire 64 bit constant. */
8986 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
8988 imm_expr.X_op = O_constant;
8989 offset_expr.X_op = O_constant;
8990 if (! target_big_endian)
8992 imm_expr.X_add_number = bfd_getl32 (temp + 4);
8993 offset_expr.X_add_number = bfd_getl32 (temp);
8997 imm_expr.X_add_number = bfd_getb32 (temp);
8998 offset_expr.X_add_number = bfd_getb32 (temp + 4);
9000 if (offset_expr.X_add_number == 0)
9001 offset_expr.X_op = O_absent;
9003 else if (sizeof (imm_expr.X_add_number) > 4)
9005 imm_expr.X_op = O_constant;
9006 if (! target_big_endian)
9007 imm_expr.X_add_number = bfd_getl64 (temp);
9009 imm_expr.X_add_number = bfd_getb64 (temp);
9013 imm_expr.X_op = O_big;
9014 imm_expr.X_add_number = 4;
9015 if (! target_big_endian)
9017 generic_bignum[0] = bfd_getl16 (temp);
9018 generic_bignum[1] = bfd_getl16 (temp + 2);
9019 generic_bignum[2] = bfd_getl16 (temp + 4);
9020 generic_bignum[3] = bfd_getl16 (temp + 6);
9024 generic_bignum[0] = bfd_getb16 (temp + 6);
9025 generic_bignum[1] = bfd_getb16 (temp + 4);
9026 generic_bignum[2] = bfd_getb16 (temp + 2);
9027 generic_bignum[3] = bfd_getb16 (temp);
9033 const char *newname;
9036 /* Switch to the right section. */
9038 subseg = now_subseg;
9041 default: /* unused default case avoids warnings. */
9043 newname = RDATA_SECTION_NAME;
9044 if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8)
9045 || mips_pic == EMBEDDED_PIC)
9049 if (mips_pic == EMBEDDED_PIC)
9052 newname = RDATA_SECTION_NAME;
9055 assert (!USE_GLOBAL_POINTER_OPT
9056 || g_switch_value >= 4);
9060 new_seg = subseg_new (newname, (subsegT) 0);
9061 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
9062 bfd_set_section_flags (stdoutput, new_seg,
9067 frag_align (*args == 'l' ? 2 : 3, 0, 0);
9068 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
9069 && strcmp (TARGET_OS, "elf") != 0)
9070 record_alignment (new_seg, 4);
9072 record_alignment (new_seg, *args == 'l' ? 2 : 3);
9074 as_bad (_("Can't use floating point insn in this section"));
9076 /* Set the argument to the current address in the
9078 offset_expr.X_op = O_symbol;
9079 offset_expr.X_add_symbol =
9080 symbol_new ("L0\001", now_seg,
9081 (valueT) frag_now_fix (), frag_now);
9082 offset_expr.X_add_number = 0;
9084 /* Put the floating point number into the section. */
9085 p = frag_more ((int) length);
9086 memcpy (p, temp, length);
9088 /* Switch back to the original section. */
9089 subseg_set (seg, subseg);
9094 case 'i': /* 16 bit unsigned immediate */
9095 case 'j': /* 16 bit signed immediate */
9096 *imm_reloc = BFD_RELOC_LO16;
9097 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
9100 offsetT minval, maxval;
9102 more = (insn + 1 < &mips_opcodes[NUMOPCODES]
9103 && strcmp (insn->name, insn[1].name) == 0);
9105 /* If the expression was written as an unsigned number,
9106 only treat it as signed if there are no more
9110 && sizeof (imm_expr.X_add_number) <= 4
9111 && imm_expr.X_op == O_constant
9112 && imm_expr.X_add_number < 0
9113 && imm_expr.X_unsigned
9117 /* For compatibility with older assemblers, we accept
9118 0x8000-0xffff as signed 16-bit numbers when only
9119 signed numbers are allowed. */
9121 minval = 0, maxval = 0xffff;
9123 minval = -0x8000, maxval = 0x7fff;
9125 minval = -0x8000, maxval = 0xffff;
9127 if (imm_expr.X_op != O_constant
9128 || imm_expr.X_add_number < minval
9129 || imm_expr.X_add_number > maxval)
9133 if (imm_expr.X_op == O_constant
9134 || imm_expr.X_op == O_big)
9135 as_bad (_("expression out of range"));
9141 case 'o': /* 16 bit offset */
9142 /* Check whether there is only a single bracketed expression
9143 left. If so, it must be the base register and the
9144 constant must be zero. */
9145 if (*s == '(' && strchr (s + 1, '(') == 0)
9147 offset_expr.X_op = O_constant;
9148 offset_expr.X_add_number = 0;
9152 /* If this value won't fit into a 16 bit offset, then go
9153 find a macro that will generate the 32 bit offset
9155 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
9156 && (offset_expr.X_op != O_constant
9157 || offset_expr.X_add_number >= 0x8000
9158 || offset_expr.X_add_number < -0x8000))
9164 case 'p': /* pc relative offset */
9165 *offset_reloc = BFD_RELOC_16_PCREL_S2;
9166 my_getExpression (&offset_expr, s);
9170 case 'u': /* upper 16 bits */
9171 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
9172 && imm_expr.X_op == O_constant
9173 && (imm_expr.X_add_number < 0
9174 || imm_expr.X_add_number >= 0x10000))
9175 as_bad (_("lui expression not in range 0..65535"));
9179 case 'a': /* 26 bit address */
9180 my_getExpression (&offset_expr, s);
9182 *offset_reloc = BFD_RELOC_MIPS_JMP;
9185 case 'N': /* 3 bit branch condition code */
9186 case 'M': /* 3 bit compare condition code */
9187 if (strncmp (s, "$fcc", 4) != 0)
9197 while (ISDIGIT (*s));
9199 as_bad (_("invalid condition code register $fcc%d"), regno);
9201 ip->insn_opcode |= regno << OP_SH_BCC;
9203 ip->insn_opcode |= regno << OP_SH_CCC;
9207 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
9218 while (ISDIGIT (*s));
9221 c = 8; /* Invalid sel value. */
9224 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9225 ip->insn_opcode |= c;
9229 /* Must be at least one digit. */
9230 my_getExpression (&imm_expr, s);
9231 check_absolute_expr (ip, &imm_expr);
9233 if ((unsigned long) imm_expr.X_add_number
9234 > (unsigned long) OP_MASK_VECBYTE)
9236 as_bad (_("bad byte vector index (%ld)"),
9237 (long) imm_expr.X_add_number);
9238 imm_expr.X_add_number = 0;
9241 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE;
9242 imm_expr.X_op = O_absent;
9247 my_getExpression (&imm_expr, s);
9248 check_absolute_expr (ip, &imm_expr);
9250 if ((unsigned long) imm_expr.X_add_number
9251 > (unsigned long) OP_MASK_VECALIGN)
9253 as_bad (_("bad byte vector index (%ld)"),
9254 (long) imm_expr.X_add_number);
9255 imm_expr.X_add_number = 0;
9258 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN;
9259 imm_expr.X_op = O_absent;
9264 as_bad (_("bad char = '%c'\n"), *args);
9269 /* Args don't match. */
9270 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
9271 !strcmp (insn->name, insn[1].name))
9275 insn_error = _("illegal operands");
9280 insn_error = _("illegal operands");
9285 /* This routine assembles an instruction into its binary format when
9286 assembling for the mips16. As a side effect, it sets one of the
9287 global variables imm_reloc or offset_reloc to the type of
9288 relocation to do if one of the operands is an address expression.
9289 It also sets mips16_small and mips16_ext if the user explicitly
9290 requested a small or extended instruction. */
9293 mips16_ip (char *str, struct mips_cl_insn *ip)
9297 struct mips_opcode *insn;
9300 unsigned int lastregno = 0;
9305 mips16_small = FALSE;
9308 for (s = str; ISLOWER (*s); ++s)
9320 if (s[1] == 't' && s[2] == ' ')
9323 mips16_small = TRUE;
9327 else if (s[1] == 'e' && s[2] == ' ')
9336 insn_error = _("unknown opcode");
9340 if (mips_opts.noautoextend && ! mips16_ext)
9341 mips16_small = TRUE;
9343 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
9345 insn_error = _("unrecognized opcode");
9352 assert (strcmp (insn->name, str) == 0);
9355 ip->insn_opcode = insn->match;
9356 ip->use_extend = FALSE;
9357 imm_expr.X_op = O_absent;
9358 imm_reloc[0] = BFD_RELOC_UNUSED;
9359 imm_reloc[1] = BFD_RELOC_UNUSED;
9360 imm_reloc[2] = BFD_RELOC_UNUSED;
9361 offset_expr.X_op = O_absent;
9362 offset_reloc[0] = BFD_RELOC_UNUSED;
9363 offset_reloc[1] = BFD_RELOC_UNUSED;
9364 offset_reloc[2] = BFD_RELOC_UNUSED;
9365 for (args = insn->args; 1; ++args)
9372 /* In this switch statement we call break if we did not find
9373 a match, continue if we did find a match, or return if we
9382 /* Stuff the immediate value in now, if we can. */
9383 if (imm_expr.X_op == O_constant
9384 && *imm_reloc > BFD_RELOC_UNUSED
9385 && insn->pinfo != INSN_MACRO)
9387 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
9388 imm_expr.X_add_number, TRUE, mips16_small,
9389 mips16_ext, &ip->insn_opcode,
9390 &ip->use_extend, &ip->extend);
9391 imm_expr.X_op = O_absent;
9392 *imm_reloc = BFD_RELOC_UNUSED;
9406 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9409 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9425 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9427 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9454 while (ISDIGIT (*s));
9457 as_bad (_("invalid register number (%d)"), regno);
9463 if (s[1] == 'r' && s[2] == 'a')
9468 else if (s[1] == 'f' && s[2] == 'p')
9473 else if (s[1] == 's' && s[2] == 'p')
9478 else if (s[1] == 'g' && s[2] == 'p')
9483 else if (s[1] == 'a' && s[2] == 't')
9488 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
9493 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
9498 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
9511 if (c == 'v' || c == 'w')
9513 regno = mips16_to_32_reg_map[lastregno];
9527 regno = mips32_to_16_reg_map[regno];
9532 regno = ILLEGAL_REG;
9537 regno = ILLEGAL_REG;
9542 regno = ILLEGAL_REG;
9547 if (regno == AT && ! mips_opts.noat)
9548 as_warn (_("used $at without \".set noat\""));
9555 if (regno == ILLEGAL_REG)
9562 ip->insn_opcode |= regno << MIPS16OP_SH_RX;
9566 ip->insn_opcode |= regno << MIPS16OP_SH_RY;
9569 ip->insn_opcode |= regno << MIPS16OP_SH_RZ;
9572 ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z;
9578 ip->insn_opcode |= regno << MIPS16OP_SH_REGR32;
9581 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
9582 ip->insn_opcode |= regno << MIPS16OP_SH_REG32R;
9592 if (strncmp (s, "$pc", 3) == 0)
9616 && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0)
9618 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9619 and generate the appropriate reloc. If the text
9620 inside %gprel is not a symbol name with an
9621 optional offset, then we generate a normal reloc
9622 and will probably fail later. */
9623 my_getExpression (&imm_expr, s + sizeof "%gprel" - 1);
9624 if (imm_expr.X_op == O_symbol)
9627 *imm_reloc = BFD_RELOC_MIPS16_GPREL;
9629 ip->use_extend = TRUE;
9636 /* Just pick up a normal expression. */
9637 my_getExpression (&imm_expr, s);
9640 if (imm_expr.X_op == O_register)
9642 /* What we thought was an expression turned out to
9645 if (s[0] == '(' && args[1] == '(')
9647 /* It looks like the expression was omitted
9648 before a register indirection, which means
9649 that the expression is implicitly zero. We
9650 still set up imm_expr, so that we handle
9651 explicit extensions correctly. */
9652 imm_expr.X_op = O_constant;
9653 imm_expr.X_add_number = 0;
9654 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9661 /* We need to relax this instruction. */
9662 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9671 /* We use offset_reloc rather than imm_reloc for the PC
9672 relative operands. This lets macros with both
9673 immediate and address operands work correctly. */
9674 my_getExpression (&offset_expr, s);
9676 if (offset_expr.X_op == O_register)
9679 /* We need to relax this instruction. */
9680 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
9684 case '6': /* break code */
9685 my_getExpression (&imm_expr, s);
9686 check_absolute_expr (ip, &imm_expr);
9687 if ((unsigned long) imm_expr.X_add_number > 63)
9689 as_warn (_("Invalid value for `%s' (%lu)"),
9691 (unsigned long) imm_expr.X_add_number);
9692 imm_expr.X_add_number &= 0x3f;
9694 ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6;
9695 imm_expr.X_op = O_absent;
9699 case 'a': /* 26 bit address */
9700 my_getExpression (&offset_expr, s);
9702 *offset_reloc = BFD_RELOC_MIPS16_JMP;
9703 ip->insn_opcode <<= 16;
9706 case 'l': /* register list for entry macro */
9707 case 'L': /* register list for exit macro */
9717 int freg, reg1, reg2;
9719 while (*s == ' ' || *s == ',')
9723 as_bad (_("can't parse register list"));
9735 while (ISDIGIT (*s))
9757 as_bad (_("invalid register list"));
9762 while (ISDIGIT (*s))
9769 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
9774 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
9779 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
9780 mask |= (reg2 - 3) << 3;
9781 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
9782 mask |= (reg2 - 15) << 1;
9783 else if (reg1 == RA && reg2 == RA)
9787 as_bad (_("invalid register list"));
9791 /* The mask is filled in in the opcode table for the
9792 benefit of the disassembler. We remove it before
9793 applying the actual mask. */
9794 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
9795 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
9799 case 'e': /* extend code */
9800 my_getExpression (&imm_expr, s);
9801 check_absolute_expr (ip, &imm_expr);
9802 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
9804 as_warn (_("Invalid value for `%s' (%lu)"),
9806 (unsigned long) imm_expr.X_add_number);
9807 imm_expr.X_add_number &= 0x7ff;
9809 ip->insn_opcode |= imm_expr.X_add_number;
9810 imm_expr.X_op = O_absent;
9820 /* Args don't match. */
9821 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
9822 strcmp (insn->name, insn[1].name) == 0)
9829 insn_error = _("illegal operands");
9835 /* This structure holds information we know about a mips16 immediate
9838 struct mips16_immed_operand
9840 /* The type code used in the argument string in the opcode table. */
9842 /* The number of bits in the short form of the opcode. */
9844 /* The number of bits in the extended form of the opcode. */
9846 /* The amount by which the short form is shifted when it is used;
9847 for example, the sw instruction has a shift count of 2. */
9849 /* The amount by which the short form is shifted when it is stored
9850 into the instruction code. */
9852 /* Non-zero if the short form is unsigned. */
9854 /* Non-zero if the extended form is unsigned. */
9856 /* Non-zero if the value is PC relative. */
9860 /* The mips16 immediate operand types. */
9862 static const struct mips16_immed_operand mips16_immed_operands[] =
9864 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9865 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9866 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9867 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9868 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
9869 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
9870 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
9871 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
9872 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
9873 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
9874 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
9875 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
9876 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
9877 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
9878 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
9879 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
9880 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9881 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9882 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
9883 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
9884 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
9887 #define MIPS16_NUM_IMMED \
9888 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9890 /* Handle a mips16 instruction with an immediate value. This or's the
9891 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9892 whether an extended value is needed; if one is needed, it sets
9893 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9894 If SMALL is true, an unextended opcode was explicitly requested.
9895 If EXT is true, an extended opcode was explicitly requested. If
9896 WARN is true, warn if EXT does not match reality. */
9899 mips16_immed (char *file, unsigned int line, int type, offsetT val,
9900 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
9901 unsigned long *insn, bfd_boolean *use_extend,
9902 unsigned short *extend)
9904 register const struct mips16_immed_operand *op;
9905 int mintiny, maxtiny;
9906 bfd_boolean needext;
9908 op = mips16_immed_operands;
9909 while (op->type != type)
9912 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
9917 if (type == '<' || type == '>' || type == '[' || type == ']')
9920 maxtiny = 1 << op->nbits;
9925 maxtiny = (1 << op->nbits) - 1;
9930 mintiny = - (1 << (op->nbits - 1));
9931 maxtiny = (1 << (op->nbits - 1)) - 1;
9934 /* Branch offsets have an implicit 0 in the lowest bit. */
9935 if (type == 'p' || type == 'q')
9938 if ((val & ((1 << op->shift) - 1)) != 0
9939 || val < (mintiny << op->shift)
9940 || val > (maxtiny << op->shift))
9945 if (warn && ext && ! needext)
9946 as_warn_where (file, line,
9947 _("extended operand requested but not required"));
9948 if (small && needext)
9949 as_bad_where (file, line, _("invalid unextended operand value"));
9951 if (small || (! ext && ! needext))
9955 *use_extend = FALSE;
9956 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
9957 insnval <<= op->op_shift;
9962 long minext, maxext;
9968 maxext = (1 << op->extbits) - 1;
9972 minext = - (1 << (op->extbits - 1));
9973 maxext = (1 << (op->extbits - 1)) - 1;
9975 if (val < minext || val > maxext)
9976 as_bad_where (file, line,
9977 _("operand value out of range for instruction"));
9980 if (op->extbits == 16)
9982 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
9985 else if (op->extbits == 15)
9987 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
9992 extval = ((val & 0x1f) << 6) | (val & 0x20);
9996 *extend = (unsigned short) extval;
10001 static const struct percent_op_match
10004 bfd_reloc_code_real_type reloc;
10007 {"%lo", BFD_RELOC_LO16},
10009 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
10010 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
10011 {"%call16", BFD_RELOC_MIPS_CALL16},
10012 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
10013 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
10014 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
10015 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
10016 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
10017 {"%got", BFD_RELOC_MIPS_GOT16},
10018 {"%gp_rel", BFD_RELOC_GPREL16},
10019 {"%half", BFD_RELOC_16},
10020 {"%highest", BFD_RELOC_MIPS_HIGHEST},
10021 {"%higher", BFD_RELOC_MIPS_HIGHER},
10022 {"%neg", BFD_RELOC_MIPS_SUB},
10024 {"%hi", BFD_RELOC_HI16_S}
10028 /* Return true if *STR points to a relocation operator. When returning true,
10029 move *STR over the operator and store its relocation code in *RELOC.
10030 Leave both *STR and *RELOC alone when returning false. */
10033 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
10037 for (i = 0; i < ARRAY_SIZE (percent_op); i++)
10038 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
10040 *str += strlen (percent_op[i].str);
10041 *reloc = percent_op[i].reloc;
10043 /* Check whether the output BFD supports this relocation.
10044 If not, issue an error and fall back on something safe. */
10045 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
10047 as_bad ("relocation %s isn't supported by the current ABI",
10048 percent_op[i].str);
10049 *reloc = BFD_RELOC_LO16;
10057 /* Parse string STR as a 16-bit relocatable operand. Store the
10058 expression in *EP and the relocations in the array starting
10059 at RELOC. Return the number of relocation operators used.
10061 On exit, EXPR_END points to the first character after the expression.
10062 If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16. */
10065 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
10068 bfd_reloc_code_real_type reversed_reloc[3];
10069 size_t reloc_index, i;
10070 int crux_depth, str_depth;
10073 /* Search for the start of the main expression, recoding relocations
10074 in REVERSED_RELOC. End the loop with CRUX pointing to the start
10075 of the main expression and with CRUX_DEPTH containing the number
10076 of open brackets at that point. */
10083 crux_depth = str_depth;
10085 /* Skip over whitespace and brackets, keeping count of the number
10087 while (*str == ' ' || *str == '\t' || *str == '(')
10092 && reloc_index < (HAVE_NEWABI ? 3 : 1)
10093 && parse_relocation (&str, &reversed_reloc[reloc_index]));
10095 my_getExpression (ep, crux);
10098 /* Match every open bracket. */
10099 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
10103 if (crux_depth > 0)
10104 as_bad ("unclosed '('");
10108 if (reloc_index == 0)
10109 reloc[0] = BFD_RELOC_LO16;
10112 prev_reloc_op_frag = frag_now;
10113 for (i = 0; i < reloc_index; i++)
10114 reloc[i] = reversed_reloc[reloc_index - 1 - i];
10117 return reloc_index;
10121 my_getExpression (expressionS *ep, char *str)
10126 save_in = input_line_pointer;
10127 input_line_pointer = str;
10129 expr_end = input_line_pointer;
10130 input_line_pointer = save_in;
10132 /* If we are in mips16 mode, and this is an expression based on `.',
10133 then we bump the value of the symbol by 1 since that is how other
10134 text symbols are handled. We don't bother to handle complex
10135 expressions, just `.' plus or minus a constant. */
10136 if (mips_opts.mips16
10137 && ep->X_op == O_symbol
10138 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
10139 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg
10140 && symbol_get_frag (ep->X_add_symbol) == frag_now
10141 && symbol_constant_p (ep->X_add_symbol)
10142 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
10143 S_SET_VALUE (ep->X_add_symbol, val + 1);
10146 /* Turn a string in input_line_pointer into a floating point constant
10147 of type TYPE, and store the appropriate bytes in *LITP. The number
10148 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10149 returned, or NULL on OK. */
10152 md_atof (int type, char *litP, int *sizeP)
10155 LITTLENUM_TYPE words[4];
10171 return _("bad call to md_atof");
10174 t = atof_ieee (input_line_pointer, type, words);
10176 input_line_pointer = t;
10180 if (! target_big_endian)
10182 for (i = prec - 1; i >= 0; i--)
10184 md_number_to_chars (litP, words[i], 2);
10190 for (i = 0; i < prec; i++)
10192 md_number_to_chars (litP, words[i], 2);
10201 md_number_to_chars (char *buf, valueT val, int n)
10203 if (target_big_endian)
10204 number_to_chars_bigendian (buf, val, n);
10206 number_to_chars_littleendian (buf, val, n);
10210 static int support_64bit_objects(void)
10212 const char **list, **l;
10215 list = bfd_target_list ();
10216 for (l = list; *l != NULL; l++)
10218 /* This is traditional mips */
10219 if (strcmp (*l, "elf64-tradbigmips") == 0
10220 || strcmp (*l, "elf64-tradlittlemips") == 0)
10222 if (strcmp (*l, "elf64-bigmips") == 0
10223 || strcmp (*l, "elf64-littlemips") == 0)
10226 yes = (*l != NULL);
10230 #endif /* OBJ_ELF */
10232 const char *md_shortopts = "nO::g::G:";
10234 struct option md_longopts[] =
10236 /* Options which specify architecture. */
10237 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10238 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10239 {"march", required_argument, NULL, OPTION_MARCH},
10240 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10241 {"mtune", required_argument, NULL, OPTION_MTUNE},
10242 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10243 {"mips0", no_argument, NULL, OPTION_MIPS1},
10244 {"mips1", no_argument, NULL, OPTION_MIPS1},
10245 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10246 {"mips2", no_argument, NULL, OPTION_MIPS2},
10247 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10248 {"mips3", no_argument, NULL, OPTION_MIPS3},
10249 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10250 {"mips4", no_argument, NULL, OPTION_MIPS4},
10251 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10252 {"mips5", no_argument, NULL, OPTION_MIPS5},
10253 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10254 {"mips32", no_argument, NULL, OPTION_MIPS32},
10255 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10256 {"mips64", no_argument, NULL, OPTION_MIPS64},
10257 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10258 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
10260 /* Options which specify Application Specific Extensions (ASEs). */
10261 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 10)
10262 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10263 {"mips16", no_argument, NULL, OPTION_MIPS16},
10264 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10265 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
10266 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10267 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
10268 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10269 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
10270 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10271 {"mdmx", no_argument, NULL, OPTION_MDMX},
10272 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10273 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
10275 /* Old-style architecture options. Don't add more of these. */
10276 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
10277 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10278 {"m4650", no_argument, NULL, OPTION_M4650},
10279 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10280 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
10281 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10282 {"m4010", no_argument, NULL, OPTION_M4010},
10283 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10284 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
10285 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10286 {"m4100", no_argument, NULL, OPTION_M4100},
10287 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10288 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
10289 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10290 {"m3900", no_argument, NULL, OPTION_M3900},
10291 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10292 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
10294 /* Options which enable bug fixes. */
10295 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10296 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10297 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
10298 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10299 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10300 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10301 #define OPTION_FIX_VR4122 (OPTION_FIX_BASE + 2)
10302 #define OPTION_NO_FIX_VR4122 (OPTION_FIX_BASE + 3)
10303 {"mfix-vr4122-bugs", no_argument, NULL, OPTION_FIX_VR4122},
10304 {"no-mfix-vr4122-bugs", no_argument, NULL, OPTION_NO_FIX_VR4122},
10306 /* Miscellaneous options. */
10307 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
10308 #define OPTION_MEMBEDDED_PIC (OPTION_MISC_BASE + 0)
10309 {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC},
10310 #define OPTION_TRAP (OPTION_MISC_BASE + 1)
10311 {"trap", no_argument, NULL, OPTION_TRAP},
10312 {"no-break", no_argument, NULL, OPTION_TRAP},
10313 #define OPTION_BREAK (OPTION_MISC_BASE + 2)
10314 {"break", no_argument, NULL, OPTION_BREAK},
10315 {"no-trap", no_argument, NULL, OPTION_BREAK},
10316 #define OPTION_EB (OPTION_MISC_BASE + 3)
10317 {"EB", no_argument, NULL, OPTION_EB},
10318 #define OPTION_EL (OPTION_MISC_BASE + 4)
10319 {"EL", no_argument, NULL, OPTION_EL},
10320 #define OPTION_FP32 (OPTION_MISC_BASE + 5)
10321 {"mfp32", no_argument, NULL, OPTION_FP32},
10322 #define OPTION_GP32 (OPTION_MISC_BASE + 6)
10323 {"mgp32", no_argument, NULL, OPTION_GP32},
10324 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10325 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
10326 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 8)
10327 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
10328 #define OPTION_FP64 (OPTION_MISC_BASE + 9)
10329 {"mfp64", no_argument, NULL, OPTION_FP64},
10330 #define OPTION_GP64 (OPTION_MISC_BASE + 10)
10331 {"mgp64", no_argument, NULL, OPTION_GP64},
10332 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10333 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 12)
10334 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
10335 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
10337 /* ELF-specific options. */
10339 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 13)
10340 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10341 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
10342 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
10343 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10344 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
10345 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10346 {"xgot", no_argument, NULL, OPTION_XGOT},
10347 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10348 {"mabi", required_argument, NULL, OPTION_MABI},
10349 #define OPTION_32 (OPTION_ELF_BASE + 4)
10350 {"32", no_argument, NULL, OPTION_32},
10351 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10352 {"n32", no_argument, NULL, OPTION_N32},
10353 #define OPTION_64 (OPTION_ELF_BASE + 6)
10354 {"64", no_argument, NULL, OPTION_64},
10355 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10356 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
10357 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10358 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
10359 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10360 {"mpdr", no_argument, NULL, OPTION_PDR},
10361 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10362 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
10363 #endif /* OBJ_ELF */
10365 {NULL, no_argument, NULL, 0}
10367 size_t md_longopts_size = sizeof (md_longopts);
10369 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10370 NEW_VALUE. Warn if another value was already specified. Note:
10371 we have to defer parsing the -march and -mtune arguments in order
10372 to handle 'from-abi' correctly, since the ABI might be specified
10373 in a later argument. */
10376 mips_set_option_string (const char **string_ptr, const char *new_value)
10378 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
10379 as_warn (_("A different %s was already specified, is now %s"),
10380 string_ptr == &mips_arch_string ? "-march" : "-mtune",
10383 *string_ptr = new_value;
10387 md_parse_option (int c, char *arg)
10391 case OPTION_CONSTRUCT_FLOATS:
10392 mips_disable_float_construction = 0;
10395 case OPTION_NO_CONSTRUCT_FLOATS:
10396 mips_disable_float_construction = 1;
10408 target_big_endian = 1;
10412 target_big_endian = 0;
10420 if (arg && arg[1] == '0')
10430 mips_debug = atoi (arg);
10431 /* When the MIPS assembler sees -g or -g2, it does not do
10432 optimizations which limit full symbolic debugging. We take
10433 that to be equivalent to -O0. */
10434 if (mips_debug == 2)
10439 file_mips_isa = ISA_MIPS1;
10443 file_mips_isa = ISA_MIPS2;
10447 file_mips_isa = ISA_MIPS3;
10451 file_mips_isa = ISA_MIPS4;
10455 file_mips_isa = ISA_MIPS5;
10458 case OPTION_MIPS32:
10459 file_mips_isa = ISA_MIPS32;
10462 case OPTION_MIPS32R2:
10463 file_mips_isa = ISA_MIPS32R2;
10466 case OPTION_MIPS64:
10467 file_mips_isa = ISA_MIPS64;
10471 mips_set_option_string (&mips_tune_string, arg);
10475 mips_set_option_string (&mips_arch_string, arg);
10479 mips_set_option_string (&mips_arch_string, "4650");
10480 mips_set_option_string (&mips_tune_string, "4650");
10483 case OPTION_NO_M4650:
10487 mips_set_option_string (&mips_arch_string, "4010");
10488 mips_set_option_string (&mips_tune_string, "4010");
10491 case OPTION_NO_M4010:
10495 mips_set_option_string (&mips_arch_string, "4100");
10496 mips_set_option_string (&mips_tune_string, "4100");
10499 case OPTION_NO_M4100:
10503 mips_set_option_string (&mips_arch_string, "3900");
10504 mips_set_option_string (&mips_tune_string, "3900");
10507 case OPTION_NO_M3900:
10511 mips_opts.ase_mdmx = 1;
10514 case OPTION_NO_MDMX:
10515 mips_opts.ase_mdmx = 0;
10518 case OPTION_MIPS16:
10519 mips_opts.mips16 = 1;
10520 mips_no_prev_insn (FALSE);
10523 case OPTION_NO_MIPS16:
10524 mips_opts.mips16 = 0;
10525 mips_no_prev_insn (FALSE);
10528 case OPTION_MIPS3D:
10529 mips_opts.ase_mips3d = 1;
10532 case OPTION_NO_MIPS3D:
10533 mips_opts.ase_mips3d = 0;
10536 case OPTION_MEMBEDDED_PIC:
10537 mips_pic = EMBEDDED_PIC;
10538 if (USE_GLOBAL_POINTER_OPT && g_switch_seen)
10540 as_bad (_("-G may not be used with embedded PIC code"));
10543 g_switch_value = 0x7fffffff;
10546 case OPTION_FIX_VR4122:
10547 mips_fix_4122_bugs = 1;
10550 case OPTION_NO_FIX_VR4122:
10551 mips_fix_4122_bugs = 0;
10554 case OPTION_RELAX_BRANCH:
10555 mips_relax_branch = 1;
10558 case OPTION_NO_RELAX_BRANCH:
10559 mips_relax_branch = 0;
10563 /* When generating ELF code, we permit -KPIC and -call_shared to
10564 select SVR4_PIC, and -non_shared to select no PIC. This is
10565 intended to be compatible with Irix 5. */
10566 case OPTION_CALL_SHARED:
10567 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10569 as_bad (_("-call_shared is supported only for ELF format"));
10572 mips_pic = SVR4_PIC;
10573 mips_abicalls = TRUE;
10574 if (g_switch_seen && g_switch_value != 0)
10576 as_bad (_("-G may not be used with SVR4 PIC code"));
10579 g_switch_value = 0;
10582 case OPTION_NON_SHARED:
10583 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10585 as_bad (_("-non_shared is supported only for ELF format"));
10589 mips_abicalls = FALSE;
10592 /* The -xgot option tells the assembler to use 32 offsets when
10593 accessing the got in SVR4_PIC mode. It is for Irix
10598 #endif /* OBJ_ELF */
10601 if (! USE_GLOBAL_POINTER_OPT)
10603 as_bad (_("-G is not supported for this configuration"));
10606 else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC)
10608 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
10612 g_switch_value = atoi (arg);
10617 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10620 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10622 as_bad (_("-32 is supported for ELF format only"));
10625 mips_abi = O32_ABI;
10629 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10631 as_bad (_("-n32 is supported for ELF format only"));
10634 mips_abi = N32_ABI;
10638 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10640 as_bad (_("-64 is supported for ELF format only"));
10643 mips_abi = N64_ABI;
10644 if (! support_64bit_objects())
10645 as_fatal (_("No compiled in support for 64 bit object file format"));
10647 #endif /* OBJ_ELF */
10650 file_mips_gp32 = 1;
10654 file_mips_gp32 = 0;
10658 file_mips_fp32 = 1;
10662 file_mips_fp32 = 0;
10667 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10669 as_bad (_("-mabi is supported for ELF format only"));
10672 if (strcmp (arg, "32") == 0)
10673 mips_abi = O32_ABI;
10674 else if (strcmp (arg, "o64") == 0)
10675 mips_abi = O64_ABI;
10676 else if (strcmp (arg, "n32") == 0)
10677 mips_abi = N32_ABI;
10678 else if (strcmp (arg, "64") == 0)
10680 mips_abi = N64_ABI;
10681 if (! support_64bit_objects())
10682 as_fatal (_("No compiled in support for 64 bit object file "
10685 else if (strcmp (arg, "eabi") == 0)
10686 mips_abi = EABI_ABI;
10689 as_fatal (_("invalid abi -mabi=%s"), arg);
10693 #endif /* OBJ_ELF */
10695 case OPTION_M7000_HILO_FIX:
10696 mips_7000_hilo_fix = TRUE;
10699 case OPTION_MNO_7000_HILO_FIX:
10700 mips_7000_hilo_fix = FALSE;
10704 case OPTION_MDEBUG:
10705 mips_flag_mdebug = TRUE;
10708 case OPTION_NO_MDEBUG:
10709 mips_flag_mdebug = FALSE;
10713 mips_flag_pdr = TRUE;
10716 case OPTION_NO_PDR:
10717 mips_flag_pdr = FALSE;
10719 #endif /* OBJ_ELF */
10728 /* Set up globals to generate code for the ISA or processor
10729 described by INFO. */
10732 mips_set_architecture (const struct mips_cpu_info *info)
10736 file_mips_arch = info->cpu;
10737 mips_opts.arch = info->cpu;
10738 mips_opts.isa = info->isa;
10743 /* Likewise for tuning. */
10746 mips_set_tune (const struct mips_cpu_info *info)
10749 mips_tune = info->cpu;
10754 mips_after_parse_args (void)
10756 const struct mips_cpu_info *arch_info = 0;
10757 const struct mips_cpu_info *tune_info = 0;
10759 /* GP relative stuff not working for PE */
10760 if (strncmp (TARGET_OS, "pe", 2) == 0
10761 && g_switch_value != 0)
10764 as_bad (_("-G not supported in this configuration."));
10765 g_switch_value = 0;
10768 if (mips_abi == NO_ABI)
10769 mips_abi = MIPS_DEFAULT_ABI;
10771 /* The following code determines the architecture and register size.
10772 Similar code was added to GCC 3.3 (see override_options() in
10773 config/mips/mips.c). The GAS and GCC code should be kept in sync
10774 as much as possible. */
10776 if (mips_arch_string != 0)
10777 arch_info = mips_parse_cpu ("-march", mips_arch_string);
10779 if (file_mips_isa != ISA_UNKNOWN)
10781 /* Handle -mipsN. At this point, file_mips_isa contains the
10782 ISA level specified by -mipsN, while arch_info->isa contains
10783 the -march selection (if any). */
10784 if (arch_info != 0)
10786 /* -march takes precedence over -mipsN, since it is more descriptive.
10787 There's no harm in specifying both as long as the ISA levels
10789 if (file_mips_isa != arch_info->isa)
10790 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10791 mips_cpu_info_from_isa (file_mips_isa)->name,
10792 mips_cpu_info_from_isa (arch_info->isa)->name);
10795 arch_info = mips_cpu_info_from_isa (file_mips_isa);
10798 if (arch_info == 0)
10799 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
10801 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
10802 as_bad ("-march=%s is not compatible with the selected ABI",
10805 mips_set_architecture (arch_info);
10807 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
10808 if (mips_tune_string != 0)
10809 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
10811 if (tune_info == 0)
10812 mips_set_tune (arch_info);
10814 mips_set_tune (tune_info);
10816 if (file_mips_gp32 >= 0)
10818 /* The user specified the size of the integer registers. Make sure
10819 it agrees with the ABI and ISA. */
10820 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
10821 as_bad (_("-mgp64 used with a 32-bit processor"));
10822 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
10823 as_bad (_("-mgp32 used with a 64-bit ABI"));
10824 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
10825 as_bad (_("-mgp64 used with a 32-bit ABI"));
10829 /* Infer the integer register size from the ABI and processor.
10830 Restrict ourselves to 32-bit registers if that's all the
10831 processor has, or if the ABI cannot handle 64-bit registers. */
10832 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
10833 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
10836 /* ??? GAS treats single-float processors as though they had 64-bit
10837 float registers (although it complains when double-precision
10838 instructions are used). As things stand, saying they have 32-bit
10839 registers would lead to spurious "register must be even" messages.
10840 So here we assume float registers are always the same size as
10841 integer ones, unless the user says otherwise. */
10842 if (file_mips_fp32 < 0)
10843 file_mips_fp32 = file_mips_gp32;
10845 /* End of GCC-shared inference code. */
10847 /* This flag is set when we have a 64-bit capable CPU but use only
10848 32-bit wide registers. Note that EABI does not use it. */
10849 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
10850 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
10851 || mips_abi == O32_ABI))
10852 mips_32bitmode = 1;
10854 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
10855 as_bad (_("trap exception not supported at ISA 1"));
10857 /* If the selected architecture includes support for ASEs, enable
10858 generation of code for them. */
10859 if (mips_opts.mips16 == -1)
10860 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
10861 if (mips_opts.ase_mips3d == -1)
10862 mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0;
10863 if (mips_opts.ase_mdmx == -1)
10864 mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0;
10866 file_mips_isa = mips_opts.isa;
10867 file_ase_mips16 = mips_opts.mips16;
10868 file_ase_mips3d = mips_opts.ase_mips3d;
10869 file_ase_mdmx = mips_opts.ase_mdmx;
10870 mips_opts.gp32 = file_mips_gp32;
10871 mips_opts.fp32 = file_mips_fp32;
10873 if (mips_flag_mdebug < 0)
10875 #ifdef OBJ_MAYBE_ECOFF
10876 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
10877 mips_flag_mdebug = 1;
10879 #endif /* OBJ_MAYBE_ECOFF */
10880 mips_flag_mdebug = 0;
10885 mips_init_after_args (void)
10887 /* initialize opcodes */
10888 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
10889 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
10893 md_pcrel_from (fixS *fixP)
10895 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
10896 switch (fixP->fx_r_type)
10898 case BFD_RELOC_16_PCREL_S2:
10899 case BFD_RELOC_MIPS_JMP:
10900 /* Return the address of the delay slot. */
10907 /* This is called before the symbol table is processed. In order to
10908 work with gcc when using mips-tfile, we must keep all local labels.
10909 However, in other cases, we want to discard them. If we were
10910 called with -g, but we didn't see any debugging information, it may
10911 mean that gcc is smuggling debugging information through to
10912 mips-tfile, in which case we must generate all local labels. */
10915 mips_frob_file_before_adjust (void)
10917 #ifndef NO_ECOFF_DEBUGGING
10918 if (ECOFF_DEBUGGING
10920 && ! ecoff_debugging_seen)
10921 flag_keep_locals = 1;
10925 /* Sort any unmatched HI16_S relocs so that they immediately precede
10926 the corresponding LO reloc. This is called before md_apply_fix3 and
10927 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10928 explicit use of the %hi modifier. */
10931 mips_frob_file (void)
10933 struct mips_hi_fixup *l;
10935 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
10937 segment_info_type *seginfo;
10940 assert (reloc_needs_lo_p (l->fixp->fx_r_type));
10942 /* If a GOT16 relocation turns out to be against a global symbol,
10943 there isn't supposed to be a matching LO. */
10944 if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
10945 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
10948 /* Check quickly whether the next fixup happens to be a matching %lo. */
10949 if (fixup_has_matching_lo_p (l->fixp))
10952 /* Look through the fixups for this segment for a matching %lo.
10953 When we find one, move the %hi just in front of it. We do
10954 this in two passes. In the first pass, we try to find a
10955 unique %lo. In the second pass, we permit multiple %hi
10956 relocs for a single %lo (this is a GNU extension). */
10957 seginfo = seg_info (l->seg);
10958 for (pass = 0; pass < 2; pass++)
10963 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
10965 /* Check whether this is a %lo fixup which matches l->fixp. */
10966 if (f->fx_r_type == BFD_RELOC_LO16
10967 && f->fx_addsy == l->fixp->fx_addsy
10968 && f->fx_offset == l->fixp->fx_offset
10971 || !reloc_needs_lo_p (prev->fx_r_type)
10972 || !fixup_has_matching_lo_p (prev)))
10976 /* Move l->fixp before f. */
10977 for (pf = &seginfo->fix_root;
10979 pf = &(*pf)->fx_next)
10980 assert (*pf != NULL);
10982 *pf = l->fixp->fx_next;
10984 l->fixp->fx_next = f;
10986 seginfo->fix_root = l->fixp;
10988 prev->fx_next = l->fixp;
10999 #if 0 /* GCC code motion plus incomplete dead code elimination
11000 can leave a %hi without a %lo. */
11002 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
11003 _("Unmatched %%hi reloc"));
11009 /* When generating embedded PIC code we need to use a special
11010 relocation to represent the difference of two symbols in the .text
11011 section (switch tables use a difference of this sort). See
11012 include/coff/mips.h for details. This macro checks whether this
11013 fixup requires the special reloc. */
11014 #define SWITCH_TABLE(fixp) \
11015 ((fixp)->fx_r_type == BFD_RELOC_32 \
11016 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
11017 && (fixp)->fx_addsy != NULL \
11018 && (fixp)->fx_subsy != NULL \
11019 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
11020 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
11022 /* When generating embedded PIC code we must keep all PC relative
11023 relocations, in case the linker has to relax a call. We also need
11024 to keep relocations for switch table entries.
11026 We may have combined relocations without symbols in the N32/N64 ABI.
11027 We have to prevent gas from dropping them. */
11030 mips_force_relocation (fixS *fixp)
11032 if (generic_force_reloc (fixp))
11036 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
11037 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
11038 || fixp->fx_r_type == BFD_RELOC_HI16_S
11039 || fixp->fx_r_type == BFD_RELOC_LO16))
11042 return (mips_pic == EMBEDDED_PIC
11044 || SWITCH_TABLE (fixp)
11045 || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S
11046 || fixp->fx_r_type == BFD_RELOC_PCREL_LO16));
11049 /* This hook is called before a fix is simplified. We don't really
11050 decide whether to skip a fix here. Rather, we turn global symbols
11051 used as branch targets into local symbols, such that they undergo
11052 simplification. We can only do this if the symbol is defined and
11053 it is in the same section as the branch. If this doesn't hold, we
11054 emit a better error message than just saying the relocation is not
11055 valid for the selected object format.
11057 FIXP is the fix-up we're going to try to simplify, SEG is the
11058 segment in which the fix up occurs. The return value should be
11059 non-zero to indicate the fix-up is valid for further
11060 simplifications. */
11063 mips_validate_fix (struct fix *fixP, asection *seg)
11065 /* There's a lot of discussion on whether it should be possible to
11066 use R_MIPS_PC16 to represent branch relocations. The outcome
11067 seems to be that it can, but gas/bfd are very broken in creating
11068 RELA relocations for this, so for now we only accept branches to
11069 symbols in the same section. Anything else is of dubious value,
11070 since there's no guarantee that at link time the symbol would be
11071 in range. Even for branches to local symbols this is arguably
11072 wrong, since it we assume the symbol is not going to be
11073 overridden, which should be possible per ELF library semantics,
11074 but then, there isn't a dynamic relocation that could be used to
11075 this effect, and the target would likely be out of range as well.
11077 Unfortunately, it seems that there is too much code out there
11078 that relies on branches to symbols that are global to be resolved
11079 as if they were local, like the IRIX tools do, so we do it as
11080 well, but with a warning so that people are reminded to fix their
11081 code. If we ever get back to using R_MIPS_PC16 for branch
11082 targets, this entire block should go away (and probably the
11083 whole function). */
11085 if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
11086 && (((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
11087 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
11088 && mips_pic != EMBEDDED_PIC)
11089 || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL)
11092 if (! S_IS_DEFINED (fixP->fx_addsy))
11094 as_bad_where (fixP->fx_file, fixP->fx_line,
11095 _("Cannot branch to undefined symbol."));
11096 /* Avoid any further errors about this fixup. */
11099 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
11101 as_bad_where (fixP->fx_file, fixP->fx_line,
11102 _("Cannot branch to symbol in another section."));
11105 else if (S_IS_EXTERNAL (fixP->fx_addsy))
11107 symbolS *sym = fixP->fx_addsy;
11109 if (mips_pic == SVR4_PIC)
11110 as_warn_where (fixP->fx_file, fixP->fx_line,
11111 _("Pretending global symbol used as branch target is local."));
11113 fixP->fx_addsy = symbol_create (S_GET_NAME (sym),
11114 S_GET_SEGMENT (sym),
11116 symbol_get_frag (sym));
11117 copy_symbol_attributes (fixP->fx_addsy, sym);
11118 S_CLEAR_EXTERNAL (fixP->fx_addsy);
11119 assert (symbol_resolved_p (sym));
11120 symbol_mark_resolved (fixP->fx_addsy);
11129 mips_need_elf_addend_fixup (fixS *fixP)
11131 if (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16)
11133 if (mips_pic == EMBEDDED_PIC
11134 && S_IS_WEAK (fixP->fx_addsy))
11136 if (mips_pic != EMBEDDED_PIC
11137 && (S_IS_WEAK (fixP->fx_addsy)
11138 || S_IS_EXTERNAL (fixP->fx_addsy))
11139 && !S_IS_COMMON (fixP->fx_addsy))
11141 if (((bfd_get_section_flags (stdoutput,
11142 S_GET_SEGMENT (fixP->fx_addsy))
11143 & (SEC_LINK_ONCE | SEC_MERGE)) != 0)
11144 || !strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)),
11146 sizeof (".gnu.linkonce") - 1))
11152 /* Apply a fixup to the object file. */
11155 md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
11159 static int previous_fx_r_type = 0;
11160 reloc_howto_type *howto;
11162 /* We ignore generic BFD relocations we don't know about. */
11163 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
11167 assert (fixP->fx_size == 4
11168 || fixP->fx_r_type == BFD_RELOC_16
11169 || fixP->fx_r_type == BFD_RELOC_64
11170 || fixP->fx_r_type == BFD_RELOC_CTOR
11171 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
11172 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
11173 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY);
11175 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
11177 /* If we aren't adjusting this fixup to be against the section
11178 symbol, we need to adjust the value. */
11180 if (fixP->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour)
11182 if (mips_need_elf_addend_fixup (fixP)
11183 && howto->partial_inplace
11184 && fixP->fx_r_type != BFD_RELOC_GPREL16
11185 && fixP->fx_r_type != BFD_RELOC_GPREL32
11186 && fixP->fx_r_type != BFD_RELOC_MIPS16_GPREL)
11188 /* In this case, the bfd_install_relocation routine will
11189 incorrectly add the symbol value back in. We just want
11190 the addend to appear in the object file.
11192 The condition above used to include
11193 "&& (! fixP->fx_pcrel || howto->pcrel_offset)".
11195 However, howto can't be trusted here, because we
11196 might change the reloc type in tc_gen_reloc. We can
11197 check howto->partial_inplace because that conversion
11198 happens to preserve howto->partial_inplace; but it
11199 does not preserve howto->pcrel_offset. I've just
11200 eliminated the check, because all MIPS PC-relative
11201 relocations are marked howto->pcrel_offset.
11203 howto->pcrel_offset was originally added for
11204 R_MIPS_PC16, which is generated for code like
11213 *valP -= S_GET_VALUE (fixP->fx_addsy);
11216 /* This code was generated using trial and error and so is
11217 fragile and not trustworthy. If you change it, you should
11218 rerun the elf-rel, elf-rel2, and empic testcases and ensure
11219 they still pass. */
11220 if (fixP->fx_pcrel)
11222 *valP += fixP->fx_frag->fr_address + fixP->fx_where;
11224 /* BFD's REL handling, for MIPS, is _very_ weird.
11225 This gives the right results, but it can't possibly
11226 be the way things are supposed to work. */
11227 *valP += fixP->fx_frag->fr_address + fixP->fx_where;
11232 /* We are not done if this is a composite relocation to set up gp. */
11233 if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel
11234 && !(fixP->fx_r_type == BFD_RELOC_MIPS_SUB
11235 || (fixP->fx_r_type == BFD_RELOC_64
11236 && (previous_fx_r_type == BFD_RELOC_GPREL32
11237 || previous_fx_r_type == BFD_RELOC_GPREL16))
11238 || (previous_fx_r_type == BFD_RELOC_MIPS_SUB
11239 && (fixP->fx_r_type == BFD_RELOC_HI16_S
11240 || fixP->fx_r_type == BFD_RELOC_LO16))))
11242 previous_fx_r_type = fixP->fx_r_type;
11244 switch (fixP->fx_r_type)
11246 case BFD_RELOC_MIPS_JMP:
11247 case BFD_RELOC_MIPS_SHIFT5:
11248 case BFD_RELOC_MIPS_SHIFT6:
11249 case BFD_RELOC_MIPS_GOT_DISP:
11250 case BFD_RELOC_MIPS_GOT_PAGE:
11251 case BFD_RELOC_MIPS_GOT_OFST:
11252 case BFD_RELOC_MIPS_SUB:
11253 case BFD_RELOC_MIPS_INSERT_A:
11254 case BFD_RELOC_MIPS_INSERT_B:
11255 case BFD_RELOC_MIPS_DELETE:
11256 case BFD_RELOC_MIPS_HIGHEST:
11257 case BFD_RELOC_MIPS_HIGHER:
11258 case BFD_RELOC_MIPS_SCN_DISP:
11259 case BFD_RELOC_MIPS_REL16:
11260 case BFD_RELOC_MIPS_RELGOT:
11261 case BFD_RELOC_MIPS_JALR:
11262 case BFD_RELOC_HI16:
11263 case BFD_RELOC_HI16_S:
11264 case BFD_RELOC_GPREL16:
11265 case BFD_RELOC_MIPS_LITERAL:
11266 case BFD_RELOC_MIPS_CALL16:
11267 case BFD_RELOC_MIPS_GOT16:
11268 case BFD_RELOC_GPREL32:
11269 case BFD_RELOC_MIPS_GOT_HI16:
11270 case BFD_RELOC_MIPS_GOT_LO16:
11271 case BFD_RELOC_MIPS_CALL_HI16:
11272 case BFD_RELOC_MIPS_CALL_LO16:
11273 case BFD_RELOC_MIPS16_GPREL:
11274 if (fixP->fx_pcrel)
11275 as_bad_where (fixP->fx_file, fixP->fx_line,
11276 _("Invalid PC relative reloc"));
11277 /* Nothing needed to do. The value comes from the reloc entry */
11280 case BFD_RELOC_MIPS16_JMP:
11281 /* We currently always generate a reloc against a symbol, which
11282 means that we don't want an addend even if the symbol is
11287 case BFD_RELOC_PCREL_HI16_S:
11288 /* The addend for this is tricky if it is internal, so we just
11289 do everything here rather than in bfd_install_relocation. */
11290 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done)
11293 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
11295 /* For an external symbol adjust by the address to make it
11296 pcrel_offset. We use the address of the RELLO reloc
11297 which follows this one. */
11298 *valP += (fixP->fx_next->fx_frag->fr_address
11299 + fixP->fx_next->fx_where);
11301 *valP = ((*valP + 0x8000) >> 16) & 0xffff;
11302 if (target_big_endian)
11304 md_number_to_chars (buf, *valP, 2);
11307 case BFD_RELOC_PCREL_LO16:
11308 /* The addend for this is tricky if it is internal, so we just
11309 do everything here rather than in bfd_install_relocation. */
11310 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done)
11313 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
11314 *valP += fixP->fx_frag->fr_address + fixP->fx_where;
11315 if (target_big_endian)
11317 md_number_to_chars (buf, *valP, 2);
11321 /* This is handled like BFD_RELOC_32, but we output a sign
11322 extended value if we are only 32 bits. */
11324 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
11326 if (8 <= sizeof (valueT))
11327 md_number_to_chars (buf, *valP, 8);
11332 if ((*valP & 0x80000000) != 0)
11336 md_number_to_chars ((char *)(buf + target_big_endian ? 4 : 0),
11338 md_number_to_chars ((char *)(buf + target_big_endian ? 0 : 4),
11344 case BFD_RELOC_RVA:
11346 /* If we are deleting this reloc entry, we must fill in the
11347 value now. This can happen if we have a .word which is not
11348 resolved when it appears but is later defined. We also need
11349 to fill in the value if this is an embedded PIC switch table
11352 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
11353 md_number_to_chars (buf, *valP, 4);
11357 /* If we are deleting this reloc entry, we must fill in the
11359 assert (fixP->fx_size == 2);
11361 md_number_to_chars (buf, *valP, 2);
11364 case BFD_RELOC_LO16:
11365 /* When handling an embedded PIC switch statement, we can wind
11366 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11369 if (*valP + 0x8000 > 0xffff)
11370 as_bad_where (fixP->fx_file, fixP->fx_line,
11371 _("relocation overflow"));
11372 if (target_big_endian)
11374 md_number_to_chars (buf, *valP, 2);
11378 case BFD_RELOC_16_PCREL_S2:
11379 if ((*valP & 0x3) != 0)
11380 as_bad_where (fixP->fx_file, fixP->fx_line,
11381 _("Branch to odd address (%lx)"), (long) *valP);
11384 * We need to save the bits in the instruction since fixup_segment()
11385 * might be deleting the relocation entry (i.e., a branch within
11386 * the current segment).
11388 if (! fixP->fx_done)
11391 /* update old instruction data */
11392 if (target_big_endian)
11393 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
11395 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
11397 if (*valP + 0x20000 <= 0x3ffff)
11399 insn |= (*valP >> 2) & 0xffff;
11400 md_number_to_chars (buf, insn, 4);
11402 else if (mips_pic == NO_PIC
11404 && fixP->fx_frag->fr_address >= text_section->vma
11405 && (fixP->fx_frag->fr_address
11406 < text_section->vma + text_section->_raw_size)
11407 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
11408 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
11409 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
11411 /* The branch offset is too large. If this is an
11412 unconditional branch, and we are not generating PIC code,
11413 we can convert it to an absolute jump instruction. */
11414 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
11415 insn = 0x0c000000; /* jal */
11417 insn = 0x08000000; /* j */
11418 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
11420 fixP->fx_addsy = section_symbol (text_section);
11421 *valP += md_pcrel_from (fixP);
11422 md_number_to_chars (buf, insn, 4);
11426 /* If we got here, we have branch-relaxation disabled,
11427 and there's nothing we can do to fix this instruction
11428 without turning it into a longer sequence. */
11429 as_bad_where (fixP->fx_file, fixP->fx_line,
11430 _("Branch out of range"));
11434 case BFD_RELOC_VTABLE_INHERIT:
11437 && !S_IS_DEFINED (fixP->fx_addsy)
11438 && !S_IS_WEAK (fixP->fx_addsy))
11439 S_SET_WEAK (fixP->fx_addsy);
11442 case BFD_RELOC_VTABLE_ENTRY:
11450 /* Remember value for tc_gen_reloc. */
11451 fixP->fx_addnumber = *valP;
11456 printInsn (unsigned long oc)
11458 const struct mips_opcode *p;
11459 int treg, sreg, dreg, shamt;
11464 for (i = 0; i < NUMOPCODES; ++i)
11466 p = &mips_opcodes[i];
11467 if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO))
11469 printf ("%08lx %s\t", oc, p->name);
11470 treg = (oc >> 16) & 0x1f;
11471 sreg = (oc >> 21) & 0x1f;
11472 dreg = (oc >> 11) & 0x1f;
11473 shamt = (oc >> 6) & 0x1f;
11475 for (args = p->args;; ++args)
11486 printf ("%c", *args);
11490 assert (treg == sreg);
11491 printf ("$%d,$%d", treg, sreg);
11496 printf ("$%d", dreg);
11501 printf ("$%d", treg);
11505 printf ("0x%x", treg);
11510 printf ("$%d", sreg);
11514 printf ("0x%08lx", oc & 0x1ffffff);
11521 printf ("%d", imm);
11526 printf ("$%d", shamt);
11537 printf (_("%08lx UNDEFINED\n"), oc);
11548 name = input_line_pointer;
11549 c = get_symbol_end ();
11550 p = (symbolS *) symbol_find_or_make (name);
11551 *input_line_pointer = c;
11555 /* Align the current frag to a given power of two. The MIPS assembler
11556 also automatically adjusts any preceding label. */
11559 mips_align (int to, int fill, symbolS *label)
11561 mips_emit_delays (FALSE);
11562 frag_align (to, fill, 0);
11563 record_alignment (now_seg, to);
11566 assert (S_GET_SEGMENT (label) == now_seg);
11567 symbol_set_frag (label, frag_now);
11568 S_SET_VALUE (label, (valueT) frag_now_fix ());
11572 /* Align to a given power of two. .align 0 turns off the automatic
11573 alignment used by the data creating pseudo-ops. */
11576 s_align (int x ATTRIBUTE_UNUSED)
11579 register long temp_fill;
11580 long max_alignment = 15;
11584 o Note that the assembler pulls down any immediately preceeding label
11585 to the aligned address.
11586 o It's not documented but auto alignment is reinstated by
11587 a .align pseudo instruction.
11588 o Note also that after auto alignment is turned off the mips assembler
11589 issues an error on attempt to assemble an improperly aligned data item.
11594 temp = get_absolute_expression ();
11595 if (temp > max_alignment)
11596 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
11599 as_warn (_("Alignment negative: 0 assumed."));
11602 if (*input_line_pointer == ',')
11604 ++input_line_pointer;
11605 temp_fill = get_absolute_expression ();
11612 mips_align (temp, (int) temp_fill,
11613 insn_labels != NULL ? insn_labels->label : NULL);
11620 demand_empty_rest_of_line ();
11624 mips_flush_pending_output (void)
11626 mips_emit_delays (FALSE);
11627 mips_clear_insn_labels ();
11631 s_change_sec (int sec)
11635 /* When generating embedded PIC code, we only use the .text, .lit8,
11636 .sdata and .sbss sections. We change the .data and .rdata
11637 pseudo-ops to use .sdata. */
11638 if (mips_pic == EMBEDDED_PIC
11639 && (sec == 'd' || sec == 'r'))
11643 /* The ELF backend needs to know that we are changing sections, so
11644 that .previous works correctly. We could do something like check
11645 for an obj_section_change_hook macro, but that might be confusing
11646 as it would not be appropriate to use it in the section changing
11647 functions in read.c, since obj-elf.c intercepts those. FIXME:
11648 This should be cleaner, somehow. */
11649 obj_elf_section_change_hook ();
11652 mips_emit_delays (FALSE);
11662 subseg_set (bss_section, (subsegT) get_absolute_expression ());
11663 demand_empty_rest_of_line ();
11667 if (USE_GLOBAL_POINTER_OPT)
11669 seg = subseg_new (RDATA_SECTION_NAME,
11670 (subsegT) get_absolute_expression ());
11671 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11673 bfd_set_section_flags (stdoutput, seg,
11679 if (strcmp (TARGET_OS, "elf") != 0)
11680 record_alignment (seg, 4);
11682 demand_empty_rest_of_line ();
11686 as_bad (_("No read only data section in this object file format"));
11687 demand_empty_rest_of_line ();
11693 if (USE_GLOBAL_POINTER_OPT)
11695 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
11696 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11698 bfd_set_section_flags (stdoutput, seg,
11699 SEC_ALLOC | SEC_LOAD | SEC_RELOC
11701 if (strcmp (TARGET_OS, "elf") != 0)
11702 record_alignment (seg, 4);
11704 demand_empty_rest_of_line ();
11709 as_bad (_("Global pointers not supported; recompile -G 0"));
11710 demand_empty_rest_of_line ();
11719 s_change_section (int ignore ATTRIBUTE_UNUSED)
11722 char *section_name;
11727 int section_entry_size;
11728 int section_alignment;
11730 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
11733 section_name = input_line_pointer;
11734 c = get_symbol_end ();
11736 next_c = *(input_line_pointer + 1);
11738 /* Do we have .section Name<,"flags">? */
11739 if (c != ',' || (c == ',' && next_c == '"'))
11741 /* just after name is now '\0'. */
11742 *input_line_pointer = c;
11743 input_line_pointer = section_name;
11744 obj_elf_section (ignore);
11747 input_line_pointer++;
11749 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11751 section_type = get_absolute_expression ();
11754 if (*input_line_pointer++ == ',')
11755 section_flag = get_absolute_expression ();
11758 if (*input_line_pointer++ == ',')
11759 section_entry_size = get_absolute_expression ();
11761 section_entry_size = 0;
11762 if (*input_line_pointer++ == ',')
11763 section_alignment = get_absolute_expression ();
11765 section_alignment = 0;
11767 section_name = xstrdup (section_name);
11769 obj_elf_change_section (section_name, section_type, section_flag,
11770 section_entry_size, 0, 0, 0);
11772 if (now_seg->name != section_name)
11773 free (section_name);
11774 #endif /* OBJ_ELF */
11778 mips_enable_auto_align (void)
11784 s_cons (int log_size)
11788 label = insn_labels != NULL ? insn_labels->label : NULL;
11789 mips_emit_delays (FALSE);
11790 if (log_size > 0 && auto_align)
11791 mips_align (log_size, 0, label);
11792 mips_clear_insn_labels ();
11793 cons (1 << log_size);
11797 s_float_cons (int type)
11801 label = insn_labels != NULL ? insn_labels->label : NULL;
11803 mips_emit_delays (FALSE);
11808 mips_align (3, 0, label);
11810 mips_align (2, 0, label);
11813 mips_clear_insn_labels ();
11818 /* Handle .globl. We need to override it because on Irix 5 you are
11821 where foo is an undefined symbol, to mean that foo should be
11822 considered to be the address of a function. */
11825 s_mips_globl (int x ATTRIBUTE_UNUSED)
11832 name = input_line_pointer;
11833 c = get_symbol_end ();
11834 symbolP = symbol_find_or_make (name);
11835 *input_line_pointer = c;
11836 SKIP_WHITESPACE ();
11838 /* On Irix 5, every global symbol that is not explicitly labelled as
11839 being a function is apparently labelled as being an object. */
11842 if (! is_end_of_line[(unsigned char) *input_line_pointer])
11847 secname = input_line_pointer;
11848 c = get_symbol_end ();
11849 sec = bfd_get_section_by_name (stdoutput, secname);
11851 as_bad (_("%s: no such section"), secname);
11852 *input_line_pointer = c;
11854 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
11855 flag = BSF_FUNCTION;
11858 symbol_get_bfdsym (symbolP)->flags |= flag;
11860 S_SET_EXTERNAL (symbolP);
11861 demand_empty_rest_of_line ();
11865 s_option (int x ATTRIBUTE_UNUSED)
11870 opt = input_line_pointer;
11871 c = get_symbol_end ();
11875 /* FIXME: What does this mean? */
11877 else if (strncmp (opt, "pic", 3) == 0)
11881 i = atoi (opt + 3);
11886 mips_pic = SVR4_PIC;
11887 mips_abicalls = TRUE;
11890 as_bad (_(".option pic%d not supported"), i);
11892 if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC)
11894 if (g_switch_seen && g_switch_value != 0)
11895 as_warn (_("-G may not be used with SVR4 PIC code"));
11896 g_switch_value = 0;
11897 bfd_set_gp_size (stdoutput, 0);
11901 as_warn (_("Unrecognized option \"%s\""), opt);
11903 *input_line_pointer = c;
11904 demand_empty_rest_of_line ();
11907 /* This structure is used to hold a stack of .set values. */
11909 struct mips_option_stack
11911 struct mips_option_stack *next;
11912 struct mips_set_options options;
11915 static struct mips_option_stack *mips_opts_stack;
11917 /* Handle the .set pseudo-op. */
11920 s_mipsset (int x ATTRIBUTE_UNUSED)
11922 char *name = input_line_pointer, ch;
11924 while (!is_end_of_line[(unsigned char) *input_line_pointer])
11925 ++input_line_pointer;
11926 ch = *input_line_pointer;
11927 *input_line_pointer = '\0';
11929 if (strcmp (name, "reorder") == 0)
11931 if (mips_opts.noreorder && prev_nop_frag != NULL)
11933 /* If we still have pending nops, we can discard them. The
11934 usual nop handling will insert any that are still
11936 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11937 * (mips_opts.mips16 ? 2 : 4));
11938 prev_nop_frag = NULL;
11940 mips_opts.noreorder = 0;
11942 else if (strcmp (name, "noreorder") == 0)
11944 mips_emit_delays (TRUE);
11945 mips_opts.noreorder = 1;
11946 mips_any_noreorder = 1;
11948 else if (strcmp (name, "at") == 0)
11950 mips_opts.noat = 0;
11952 else if (strcmp (name, "noat") == 0)
11954 mips_opts.noat = 1;
11956 else if (strcmp (name, "macro") == 0)
11958 mips_opts.warn_about_macros = 0;
11960 else if (strcmp (name, "nomacro") == 0)
11962 if (mips_opts.noreorder == 0)
11963 as_bad (_("`noreorder' must be set before `nomacro'"));
11964 mips_opts.warn_about_macros = 1;
11966 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
11968 mips_opts.nomove = 0;
11970 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
11972 mips_opts.nomove = 1;
11974 else if (strcmp (name, "bopt") == 0)
11976 mips_opts.nobopt = 0;
11978 else if (strcmp (name, "nobopt") == 0)
11980 mips_opts.nobopt = 1;
11982 else if (strcmp (name, "mips16") == 0
11983 || strcmp (name, "MIPS-16") == 0)
11984 mips_opts.mips16 = 1;
11985 else if (strcmp (name, "nomips16") == 0
11986 || strcmp (name, "noMIPS-16") == 0)
11987 mips_opts.mips16 = 0;
11988 else if (strcmp (name, "mips3d") == 0)
11989 mips_opts.ase_mips3d = 1;
11990 else if (strcmp (name, "nomips3d") == 0)
11991 mips_opts.ase_mips3d = 0;
11992 else if (strcmp (name, "mdmx") == 0)
11993 mips_opts.ase_mdmx = 1;
11994 else if (strcmp (name, "nomdmx") == 0)
11995 mips_opts.ase_mdmx = 0;
11996 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
12000 /* Permit the user to change the ISA and architecture on the fly.
12001 Needless to say, misuse can cause serious problems. */
12002 if (strcmp (name, "mips0") == 0)
12005 mips_opts.isa = file_mips_isa;
12007 else if (strcmp (name, "mips1") == 0)
12008 mips_opts.isa = ISA_MIPS1;
12009 else if (strcmp (name, "mips2") == 0)
12010 mips_opts.isa = ISA_MIPS2;
12011 else if (strcmp (name, "mips3") == 0)
12012 mips_opts.isa = ISA_MIPS3;
12013 else if (strcmp (name, "mips4") == 0)
12014 mips_opts.isa = ISA_MIPS4;
12015 else if (strcmp (name, "mips5") == 0)
12016 mips_opts.isa = ISA_MIPS5;
12017 else if (strcmp (name, "mips32") == 0)
12018 mips_opts.isa = ISA_MIPS32;
12019 else if (strcmp (name, "mips32r2") == 0)
12020 mips_opts.isa = ISA_MIPS32R2;
12021 else if (strcmp (name, "mips64") == 0)
12022 mips_opts.isa = ISA_MIPS64;
12023 else if (strcmp (name, "arch=default") == 0)
12026 mips_opts.arch = file_mips_arch;
12027 mips_opts.isa = file_mips_isa;
12029 else if (strncmp (name, "arch=", 5) == 0)
12031 const struct mips_cpu_info *p;
12033 p = mips_parse_cpu("internal use", name + 5);
12035 as_bad (_("unknown architecture %s"), name + 5);
12038 mips_opts.arch = p->cpu;
12039 mips_opts.isa = p->isa;
12043 as_bad (_("unknown ISA level %s"), name + 4);
12045 switch (mips_opts.isa)
12053 mips_opts.gp32 = 1;
12054 mips_opts.fp32 = 1;
12060 mips_opts.gp32 = 0;
12061 mips_opts.fp32 = 0;
12064 as_bad (_("unknown ISA level %s"), name + 4);
12069 mips_opts.gp32 = file_mips_gp32;
12070 mips_opts.fp32 = file_mips_fp32;
12073 else if (strcmp (name, "autoextend") == 0)
12074 mips_opts.noautoextend = 0;
12075 else if (strcmp (name, "noautoextend") == 0)
12076 mips_opts.noautoextend = 1;
12077 else if (strcmp (name, "push") == 0)
12079 struct mips_option_stack *s;
12081 s = (struct mips_option_stack *) xmalloc (sizeof *s);
12082 s->next = mips_opts_stack;
12083 s->options = mips_opts;
12084 mips_opts_stack = s;
12086 else if (strcmp (name, "pop") == 0)
12088 struct mips_option_stack *s;
12090 s = mips_opts_stack;
12092 as_bad (_(".set pop with no .set push"));
12095 /* If we're changing the reorder mode we need to handle
12096 delay slots correctly. */
12097 if (s->options.noreorder && ! mips_opts.noreorder)
12098 mips_emit_delays (TRUE);
12099 else if (! s->options.noreorder && mips_opts.noreorder)
12101 if (prev_nop_frag != NULL)
12103 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
12104 * (mips_opts.mips16 ? 2 : 4));
12105 prev_nop_frag = NULL;
12109 mips_opts = s->options;
12110 mips_opts_stack = s->next;
12116 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
12118 *input_line_pointer = ch;
12119 demand_empty_rest_of_line ();
12122 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
12123 .option pic2. It means to generate SVR4 PIC calls. */
12126 s_abicalls (int ignore ATTRIBUTE_UNUSED)
12128 mips_pic = SVR4_PIC;
12129 mips_abicalls = TRUE;
12130 if (USE_GLOBAL_POINTER_OPT)
12132 if (g_switch_seen && g_switch_value != 0)
12133 as_warn (_("-G may not be used with SVR4 PIC code"));
12134 g_switch_value = 0;
12136 bfd_set_gp_size (stdoutput, 0);
12137 demand_empty_rest_of_line ();
12140 /* Handle the .cpload pseudo-op. This is used when generating SVR4
12141 PIC code. It sets the $gp register for the function based on the
12142 function address, which is in the register named in the argument.
12143 This uses a relocation against _gp_disp, which is handled specially
12144 by the linker. The result is:
12145 lui $gp,%hi(_gp_disp)
12146 addiu $gp,$gp,%lo(_gp_disp)
12147 addu $gp,$gp,.cpload argument
12148 The .cpload argument is normally $25 == $t9. */
12151 s_cpload (int ignore ATTRIBUTE_UNUSED)
12156 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12157 .cpload is ignored. */
12158 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12164 /* .cpload should be in a .set noreorder section. */
12165 if (mips_opts.noreorder == 0)
12166 as_warn (_(".cpload not in noreorder section"));
12168 ex.X_op = O_symbol;
12169 ex.X_add_symbol = symbol_find_or_make ("_gp_disp");
12170 ex.X_op_symbol = NULL;
12171 ex.X_add_number = 0;
12173 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12174 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
12176 macro_build_lui (NULL, &icnt, &ex, mips_gp_register);
12177 macro_build (NULL, &icnt, &ex, "addiu", "t,r,j", mips_gp_register,
12178 mips_gp_register, BFD_RELOC_LO16);
12180 macro_build (NULL, &icnt, NULL, "addu", "d,v,t", mips_gp_register,
12181 mips_gp_register, tc_get_register (0));
12183 demand_empty_rest_of_line ();
12186 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12187 .cpsetup $reg1, offset|$reg2, label
12189 If offset is given, this results in:
12190 sd $gp, offset($sp)
12191 lui $gp, %hi(%neg(%gp_rel(label)))
12192 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12193 daddu $gp, $gp, $reg1
12195 If $reg2 is given, this results in:
12196 daddu $reg2, $gp, $0
12197 lui $gp, %hi(%neg(%gp_rel(label)))
12198 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12199 daddu $gp, $gp, $reg1
12200 $reg1 is normally $25 == $t9. */
12202 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
12204 expressionS ex_off;
12205 expressionS ex_sym;
12210 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12211 We also need NewABI support. */
12212 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12218 reg1 = tc_get_register (0);
12219 SKIP_WHITESPACE ();
12220 if (*input_line_pointer != ',')
12222 as_bad (_("missing argument separator ',' for .cpsetup"));
12226 ++input_line_pointer;
12227 SKIP_WHITESPACE ();
12228 if (*input_line_pointer == '$')
12230 mips_cpreturn_register = tc_get_register (0);
12231 mips_cpreturn_offset = -1;
12235 mips_cpreturn_offset = get_absolute_expression ();
12236 mips_cpreturn_register = -1;
12238 SKIP_WHITESPACE ();
12239 if (*input_line_pointer != ',')
12241 as_bad (_("missing argument separator ',' for .cpsetup"));
12245 ++input_line_pointer;
12246 SKIP_WHITESPACE ();
12247 expression (&ex_sym);
12249 if (mips_cpreturn_register == -1)
12251 ex_off.X_op = O_constant;
12252 ex_off.X_add_symbol = NULL;
12253 ex_off.X_op_symbol = NULL;
12254 ex_off.X_add_number = mips_cpreturn_offset;
12256 macro_build (NULL, &icnt, &ex_off, "sd", "t,o(b)", mips_gp_register,
12257 BFD_RELOC_LO16, SP);
12260 macro_build (NULL, &icnt, NULL, "daddu", "d,v,t", mips_cpreturn_register,
12261 mips_gp_register, 0);
12263 /* Ensure there's room for the next two instructions, so that `f'
12264 doesn't end up with an address in the wrong frag. */
12267 macro_build (NULL, &icnt, &ex_sym, "lui", "t,u", mips_gp_register,
12268 BFD_RELOC_GPREL16);
12269 fix_new (frag_now, f - frag_now->fr_literal,
12270 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
12271 fix_new (frag_now, f - frag_now->fr_literal,
12272 4, NULL, 0, 0, BFD_RELOC_HI16_S);
12275 macro_build (NULL, &icnt, &ex_sym, "addiu", "t,r,j", mips_gp_register,
12276 mips_gp_register, BFD_RELOC_GPREL16);
12277 fix_new (frag_now, f - frag_now->fr_literal,
12278 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
12279 fix_new (frag_now, f - frag_now->fr_literal,
12280 4, NULL, 0, 0, BFD_RELOC_LO16);
12282 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
12283 mips_gp_register, reg1);
12285 demand_empty_rest_of_line ();
12289 s_cplocal (int ignore ATTRIBUTE_UNUSED)
12291 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12292 .cplocal is ignored. */
12293 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12299 mips_gp_register = tc_get_register (0);
12300 demand_empty_rest_of_line ();
12303 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12304 offset from $sp. The offset is remembered, and after making a PIC
12305 call $gp is restored from that location. */
12308 s_cprestore (int ignore ATTRIBUTE_UNUSED)
12313 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12314 .cprestore is ignored. */
12315 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12321 mips_cprestore_offset = get_absolute_expression ();
12322 mips_cprestore_valid = 1;
12324 ex.X_op = O_constant;
12325 ex.X_add_symbol = NULL;
12326 ex.X_op_symbol = NULL;
12327 ex.X_add_number = mips_cprestore_offset;
12329 macro_build_ldst_constoffset (NULL, &icnt, &ex, ADDRESS_STORE_INSN,
12330 mips_gp_register, SP, HAVE_64BIT_ADDRESSES);
12332 demand_empty_rest_of_line ();
12335 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12336 was given in the preceeding .gpsetup, it results in:
12337 ld $gp, offset($sp)
12339 If a register $reg2 was given there, it results in:
12340 daddiu $gp, $gp, $reg2
12343 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
12348 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12349 We also need NewABI support. */
12350 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12356 if (mips_cpreturn_register == -1)
12358 ex.X_op = O_constant;
12359 ex.X_add_symbol = NULL;
12360 ex.X_op_symbol = NULL;
12361 ex.X_add_number = mips_cpreturn_offset;
12363 macro_build (NULL, &icnt, &ex, "ld", "t,o(b)", mips_gp_register,
12364 BFD_RELOC_LO16, SP);
12367 macro_build (NULL, &icnt, NULL, "daddu", "d,v,t", mips_gp_register,
12368 mips_cpreturn_register, 0);
12370 demand_empty_rest_of_line ();
12373 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12374 code. It sets the offset to use in gp_rel relocations. */
12377 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
12379 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12380 We also need NewABI support. */
12381 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12387 mips_gprel_offset = get_absolute_expression ();
12389 demand_empty_rest_of_line ();
12392 /* Handle the .gpword pseudo-op. This is used when generating PIC
12393 code. It generates a 32 bit GP relative reloc. */
12396 s_gpword (int ignore ATTRIBUTE_UNUSED)
12402 /* When not generating PIC code, this is treated as .word. */
12403 if (mips_pic != SVR4_PIC)
12409 label = insn_labels != NULL ? insn_labels->label : NULL;
12410 mips_emit_delays (TRUE);
12412 mips_align (2, 0, label);
12413 mips_clear_insn_labels ();
12417 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12419 as_bad (_("Unsupported use of .gpword"));
12420 ignore_rest_of_line ();
12424 md_number_to_chars (p, 0, 4);
12425 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
12426 BFD_RELOC_GPREL32);
12428 demand_empty_rest_of_line ();
12432 s_gpdword (int ignore ATTRIBUTE_UNUSED)
12438 /* When not generating PIC code, this is treated as .dword. */
12439 if (mips_pic != SVR4_PIC)
12445 label = insn_labels != NULL ? insn_labels->label : NULL;
12446 mips_emit_delays (TRUE);
12448 mips_align (3, 0, label);
12449 mips_clear_insn_labels ();
12453 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12455 as_bad (_("Unsupported use of .gpdword"));
12456 ignore_rest_of_line ();
12460 md_number_to_chars (p, 0, 8);
12461 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
12462 BFD_RELOC_GPREL32);
12464 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12465 ex.X_op = O_absent;
12466 ex.X_add_symbol = 0;
12467 ex.X_add_number = 0;
12468 fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &ex, FALSE,
12471 demand_empty_rest_of_line ();
12474 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12475 tables in SVR4 PIC code. */
12478 s_cpadd (int ignore ATTRIBUTE_UNUSED)
12483 /* This is ignored when not generating SVR4 PIC code. */
12484 if (mips_pic != SVR4_PIC)
12490 /* Add $gp to the register named as an argument. */
12491 reg = tc_get_register (0);
12492 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
12493 reg, reg, mips_gp_register);
12495 demand_empty_rest_of_line ();
12498 /* Handle the .insn pseudo-op. This marks instruction labels in
12499 mips16 mode. This permits the linker to handle them specially,
12500 such as generating jalx instructions when needed. We also make
12501 them odd for the duration of the assembly, in order to generate the
12502 right sort of code. We will make them even in the adjust_symtab
12503 routine, while leaving them marked. This is convenient for the
12504 debugger and the disassembler. The linker knows to make them odd
12508 s_insn (int ignore ATTRIBUTE_UNUSED)
12510 mips16_mark_labels ();
12512 demand_empty_rest_of_line ();
12515 /* Handle a .stabn directive. We need these in order to mark a label
12516 as being a mips16 text label correctly. Sometimes the compiler
12517 will emit a label, followed by a .stabn, and then switch sections.
12518 If the label and .stabn are in mips16 mode, then the label is
12519 really a mips16 text label. */
12522 s_mips_stab (int type)
12525 mips16_mark_labels ();
12530 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12534 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
12541 name = input_line_pointer;
12542 c = get_symbol_end ();
12543 symbolP = symbol_find_or_make (name);
12544 S_SET_WEAK (symbolP);
12545 *input_line_pointer = c;
12547 SKIP_WHITESPACE ();
12549 if (! is_end_of_line[(unsigned char) *input_line_pointer])
12551 if (S_IS_DEFINED (symbolP))
12553 as_bad ("ignoring attempt to redefine symbol %s",
12554 S_GET_NAME (symbolP));
12555 ignore_rest_of_line ();
12559 if (*input_line_pointer == ',')
12561 ++input_line_pointer;
12562 SKIP_WHITESPACE ();
12566 if (exp.X_op != O_symbol)
12568 as_bad ("bad .weakext directive");
12569 ignore_rest_of_line ();
12572 symbol_set_value_expression (symbolP, &exp);
12575 demand_empty_rest_of_line ();
12578 /* Parse a register string into a number. Called from the ECOFF code
12579 to parse .frame. The argument is non-zero if this is the frame
12580 register, so that we can record it in mips_frame_reg. */
12583 tc_get_register (int frame)
12587 SKIP_WHITESPACE ();
12588 if (*input_line_pointer++ != '$')
12590 as_warn (_("expected `$'"));
12593 else if (ISDIGIT (*input_line_pointer))
12595 reg = get_absolute_expression ();
12596 if (reg < 0 || reg >= 32)
12598 as_warn (_("Bad register number"));
12604 if (strncmp (input_line_pointer, "ra", 2) == 0)
12607 input_line_pointer += 2;
12609 else if (strncmp (input_line_pointer, "fp", 2) == 0)
12612 input_line_pointer += 2;
12614 else if (strncmp (input_line_pointer, "sp", 2) == 0)
12617 input_line_pointer += 2;
12619 else if (strncmp (input_line_pointer, "gp", 2) == 0)
12622 input_line_pointer += 2;
12624 else if (strncmp (input_line_pointer, "at", 2) == 0)
12627 input_line_pointer += 2;
12629 else if (strncmp (input_line_pointer, "kt0", 3) == 0)
12632 input_line_pointer += 3;
12634 else if (strncmp (input_line_pointer, "kt1", 3) == 0)
12637 input_line_pointer += 3;
12639 else if (strncmp (input_line_pointer, "zero", 4) == 0)
12642 input_line_pointer += 4;
12646 as_warn (_("Unrecognized register name"));
12648 while (ISALNUM(*input_line_pointer))
12649 input_line_pointer++;
12654 mips_frame_reg = reg != 0 ? reg : SP;
12655 mips_frame_reg_valid = 1;
12656 mips_cprestore_valid = 0;
12662 md_section_align (asection *seg, valueT addr)
12664 int align = bfd_get_section_alignment (stdoutput, seg);
12667 /* We don't need to align ELF sections to the full alignment.
12668 However, Irix 5 may prefer that we align them at least to a 16
12669 byte boundary. We don't bother to align the sections if we are
12670 targeted for an embedded system. */
12671 if (strcmp (TARGET_OS, "elf") == 0)
12677 return ((addr + (1 << align) - 1) & (-1 << align));
12680 /* Utility routine, called from above as well. If called while the
12681 input file is still being read, it's only an approximation. (For
12682 example, a symbol may later become defined which appeared to be
12683 undefined earlier.) */
12686 nopic_need_relax (symbolS *sym, int before_relaxing)
12691 if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0)
12693 const char *symname;
12696 /* Find out whether this symbol can be referenced off the $gp
12697 register. It can be if it is smaller than the -G size or if
12698 it is in the .sdata or .sbss section. Certain symbols can
12699 not be referenced off the $gp, although it appears as though
12701 symname = S_GET_NAME (sym);
12702 if (symname != (const char *) NULL
12703 && (strcmp (symname, "eprol") == 0
12704 || strcmp (symname, "etext") == 0
12705 || strcmp (symname, "_gp") == 0
12706 || strcmp (symname, "edata") == 0
12707 || strcmp (symname, "_fbss") == 0
12708 || strcmp (symname, "_fdata") == 0
12709 || strcmp (symname, "_ftext") == 0
12710 || strcmp (symname, "end") == 0
12711 || strcmp (symname, "_gp_disp") == 0))
12713 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
12715 #ifndef NO_ECOFF_DEBUGGING
12716 || (symbol_get_obj (sym)->ecoff_extern_size != 0
12717 && (symbol_get_obj (sym)->ecoff_extern_size
12718 <= g_switch_value))
12720 /* We must defer this decision until after the whole
12721 file has been read, since there might be a .extern
12722 after the first use of this symbol. */
12723 || (before_relaxing
12724 #ifndef NO_ECOFF_DEBUGGING
12725 && symbol_get_obj (sym)->ecoff_extern_size == 0
12727 && S_GET_VALUE (sym) == 0)
12728 || (S_GET_VALUE (sym) != 0
12729 && S_GET_VALUE (sym) <= g_switch_value)))
12733 const char *segname;
12735 segname = segment_name (S_GET_SEGMENT (sym));
12736 assert (strcmp (segname, ".lit8") != 0
12737 && strcmp (segname, ".lit4") != 0);
12738 change = (strcmp (segname, ".sdata") != 0
12739 && strcmp (segname, ".sbss") != 0
12740 && strncmp (segname, ".sdata.", 7) != 0
12741 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
12746 /* We are not optimizing for the $gp register. */
12751 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12754 pic_need_relax (symbolS *sym, asection *segtype)
12757 bfd_boolean linkonce;
12759 /* Handle the case of a symbol equated to another symbol. */
12760 while (symbol_equated_reloc_p (sym))
12764 /* It's possible to get a loop here in a badly written
12766 n = symbol_get_value_expression (sym)->X_add_symbol;
12772 symsec = S_GET_SEGMENT (sym);
12774 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12776 if (symsec != segtype && ! S_IS_LOCAL (sym))
12778 if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE)
12782 /* The GNU toolchain uses an extension for ELF: a section
12783 beginning with the magic string .gnu.linkonce is a linkonce
12785 if (strncmp (segment_name (symsec), ".gnu.linkonce",
12786 sizeof ".gnu.linkonce" - 1) == 0)
12790 /* This must duplicate the test in adjust_reloc_syms. */
12791 return (symsec != &bfd_und_section
12792 && symsec != &bfd_abs_section
12793 && ! bfd_is_com_section (symsec)
12796 /* A global or weak symbol is treated as external. */
12797 && (OUTPUT_FLAVOR != bfd_target_elf_flavour
12798 || (! S_IS_WEAK (sym)
12799 && (! S_IS_EXTERNAL (sym)
12800 || mips_pic == EMBEDDED_PIC)))
12806 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12807 extended opcode. SEC is the section the frag is in. */
12810 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
12813 register const struct mips16_immed_operand *op;
12815 int mintiny, maxtiny;
12819 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
12821 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
12824 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
12825 op = mips16_immed_operands;
12826 while (op->type != type)
12829 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
12834 if (type == '<' || type == '>' || type == '[' || type == ']')
12837 maxtiny = 1 << op->nbits;
12842 maxtiny = (1 << op->nbits) - 1;
12847 mintiny = - (1 << (op->nbits - 1));
12848 maxtiny = (1 << (op->nbits - 1)) - 1;
12851 sym_frag = symbol_get_frag (fragp->fr_symbol);
12852 val = S_GET_VALUE (fragp->fr_symbol);
12853 symsec = S_GET_SEGMENT (fragp->fr_symbol);
12859 /* We won't have the section when we are called from
12860 mips_relax_frag. However, we will always have been called
12861 from md_estimate_size_before_relax first. If this is a
12862 branch to a different section, we mark it as such. If SEC is
12863 NULL, and the frag is not marked, then it must be a branch to
12864 the same section. */
12867 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
12872 /* Must have been called from md_estimate_size_before_relax. */
12875 fragp->fr_subtype =
12876 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12878 /* FIXME: We should support this, and let the linker
12879 catch branches and loads that are out of range. */
12880 as_bad_where (fragp->fr_file, fragp->fr_line,
12881 _("unsupported PC relative reference to different section"));
12885 if (fragp != sym_frag && sym_frag->fr_address == 0)
12886 /* Assume non-extended on the first relaxation pass.
12887 The address we have calculated will be bogus if this is
12888 a forward branch to another frag, as the forward frag
12889 will have fr_address == 0. */
12893 /* In this case, we know for sure that the symbol fragment is in
12894 the same section. If the relax_marker of the symbol fragment
12895 differs from the relax_marker of this fragment, we have not
12896 yet adjusted the symbol fragment fr_address. We want to add
12897 in STRETCH in order to get a better estimate of the address.
12898 This particularly matters because of the shift bits. */
12900 && sym_frag->relax_marker != fragp->relax_marker)
12904 /* Adjust stretch for any alignment frag. Note that if have
12905 been expanding the earlier code, the symbol may be
12906 defined in what appears to be an earlier frag. FIXME:
12907 This doesn't handle the fr_subtype field, which specifies
12908 a maximum number of bytes to skip when doing an
12910 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
12912 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
12915 stretch = - ((- stretch)
12916 & ~ ((1 << (int) f->fr_offset) - 1));
12918 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
12927 addr = fragp->fr_address + fragp->fr_fix;
12929 /* The base address rules are complicated. The base address of
12930 a branch is the following instruction. The base address of a
12931 PC relative load or add is the instruction itself, but if it
12932 is in a delay slot (in which case it can not be extended) use
12933 the address of the instruction whose delay slot it is in. */
12934 if (type == 'p' || type == 'q')
12938 /* If we are currently assuming that this frag should be
12939 extended, then, the current address is two bytes
12941 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12944 /* Ignore the low bit in the target, since it will be set
12945 for a text label. */
12946 if ((val & 1) != 0)
12949 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
12951 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
12954 val -= addr & ~ ((1 << op->shift) - 1);
12956 /* Branch offsets have an implicit 0 in the lowest bit. */
12957 if (type == 'p' || type == 'q')
12960 /* If any of the shifted bits are set, we must use an extended
12961 opcode. If the address depends on the size of this
12962 instruction, this can lead to a loop, so we arrange to always
12963 use an extended opcode. We only check this when we are in
12964 the main relaxation loop, when SEC is NULL. */
12965 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
12967 fragp->fr_subtype =
12968 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12972 /* If we are about to mark a frag as extended because the value
12973 is precisely maxtiny + 1, then there is a chance of an
12974 infinite loop as in the following code:
12979 In this case when the la is extended, foo is 0x3fc bytes
12980 away, so the la can be shrunk, but then foo is 0x400 away, so
12981 the la must be extended. To avoid this loop, we mark the
12982 frag as extended if it was small, and is about to become
12983 extended with a value of maxtiny + 1. */
12984 if (val == ((maxtiny + 1) << op->shift)
12985 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
12988 fragp->fr_subtype =
12989 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12993 else if (symsec != absolute_section && sec != NULL)
12994 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
12996 if ((val & ((1 << op->shift) - 1)) != 0
12997 || val < (mintiny << op->shift)
12998 || val > (maxtiny << op->shift))
13004 /* Compute the length of a branch sequence, and adjust the
13005 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
13006 worst-case length is computed, with UPDATE being used to indicate
13007 whether an unconditional (-1), branch-likely (+1) or regular (0)
13008 branch is to be computed. */
13010 relaxed_branch_length (fragS *fragp, asection *sec, int update)
13012 bfd_boolean toofar;
13016 && S_IS_DEFINED (fragp->fr_symbol)
13017 && sec == S_GET_SEGMENT (fragp->fr_symbol))
13022 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
13024 addr = fragp->fr_address + fragp->fr_fix + 4;
13028 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
13031 /* If the symbol is not defined or it's in a different segment,
13032 assume the user knows what's going on and emit a short
13038 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
13040 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype),
13041 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
13042 RELAX_BRANCH_LINK (fragp->fr_subtype),
13048 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
13051 if (mips_pic != NO_PIC)
13053 /* Additional space for PIC loading of target address. */
13055 if (mips_opts.isa == ISA_MIPS1)
13056 /* Additional space for $at-stabilizing nop. */
13060 /* If branch is conditional. */
13061 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
13068 /* Estimate the size of a frag before relaxing. Unless this is the
13069 mips16, we are not really relaxing here, and the final size is
13070 encoded in the subtype information. For the mips16, we have to
13071 decide whether we are using an extended opcode or not. */
13074 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
13078 if (RELAX_BRANCH_P (fragp->fr_subtype))
13081 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
13083 return fragp->fr_var;
13086 if (RELAX_MIPS16_P (fragp->fr_subtype))
13087 /* We don't want to modify the EXTENDED bit here; it might get us
13088 into infinite loops. We change it only in mips_relax_frag(). */
13089 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
13091 if (mips_pic == NO_PIC)
13092 change = nopic_need_relax (fragp->fr_symbol, 0);
13093 else if (mips_pic == SVR4_PIC)
13094 change = pic_need_relax (fragp->fr_symbol, segtype);
13100 /* Record the offset to the first reloc in the fr_opcode field.
13101 This lets md_convert_frag and tc_gen_reloc know that the code
13102 must be expanded. */
13103 fragp->fr_opcode = (fragp->fr_literal
13105 - RELAX_OLD (fragp->fr_subtype)
13106 + RELAX_RELOC1 (fragp->fr_subtype));
13107 /* FIXME: This really needs as_warn_where. */
13108 if (RELAX_WARN (fragp->fr_subtype))
13109 as_warn (_("AT used after \".set noat\" or macro used after "
13110 "\".set nomacro\""));
13112 return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype);
13118 /* This is called to see whether a reloc against a defined symbol
13119 should be converted into a reloc against a section. Don't adjust
13120 MIPS16 jump relocations, so we don't have to worry about the format
13121 of the offset in the .o file. Don't adjust relocations against
13122 mips16 symbols, so that the linker can find them if it needs to set
13126 mips_fix_adjustable (fixS *fixp)
13128 if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
13131 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
13132 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
13135 if (fixp->fx_addsy == NULL)
13139 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
13140 && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
13141 && fixp->fx_subsy == NULL)
13148 /* Translate internal representation of relocation info to BFD target
13152 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
13154 static arelent *retval[4];
13156 bfd_reloc_code_real_type code;
13158 memset (retval, 0, sizeof(retval));
13159 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
13160 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
13161 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
13162 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
13164 if (mips_pic == EMBEDDED_PIC
13165 && SWITCH_TABLE (fixp))
13167 /* For a switch table entry we use a special reloc. The addend
13168 is actually the difference between the reloc address and the
13170 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
13171 if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour)
13172 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
13173 fixp->fx_r_type = BFD_RELOC_GPREL32;
13175 else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16)
13177 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
13178 reloc->addend = fixp->fx_addnumber;
13181 /* We use a special addend for an internal RELLO reloc. */
13182 if (symbol_section_p (fixp->fx_addsy))
13183 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
13185 reloc->addend = fixp->fx_addnumber + reloc->address;
13188 else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
13190 assert (fixp->fx_next != NULL
13191 && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16);
13193 /* The reloc is relative to the RELLO; adjust the addend
13195 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
13196 reloc->addend = fixp->fx_next->fx_addnumber;
13199 /* We use a special addend for an internal RELHI reloc. */
13200 if (symbol_section_p (fixp->fx_addsy))
13201 reloc->addend = (fixp->fx_next->fx_frag->fr_address
13202 + fixp->fx_next->fx_where
13203 - S_GET_VALUE (fixp->fx_subsy));
13205 reloc->addend = (fixp->fx_addnumber
13206 + fixp->fx_next->fx_frag->fr_address
13207 + fixp->fx_next->fx_where);
13210 else if (fixp->fx_pcrel == 0 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
13211 reloc->addend = fixp->fx_addnumber;
13214 if (OUTPUT_FLAVOR != bfd_target_aout_flavour)
13215 /* A gruesome hack which is a result of the gruesome gas reloc
13217 reloc->addend = reloc->address;
13219 reloc->addend = -reloc->address;
13222 /* If this is a variant frag, we may need to adjust the existing
13223 reloc and generate a new one. */
13224 if (fixp->fx_frag->fr_opcode != NULL
13225 && ((fixp->fx_r_type == BFD_RELOC_GPREL16
13227 || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_DISP
13229 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
13230 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16
13231 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
13232 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16
13233 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
13234 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)
13239 assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype));
13241 /* If this is not the last reloc in this frag, then we have two
13242 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
13243 CALL_HI16/CALL_LO16, both of which are being replaced. Let
13244 the second one handle all of them. */
13245 if (fixp->fx_next != NULL
13246 && fixp->fx_frag == fixp->fx_next->fx_frag)
13248 assert ((fixp->fx_r_type == BFD_RELOC_GPREL16
13249 && fixp->fx_next->fx_r_type == BFD_RELOC_GPREL16)
13250 || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
13251 && (fixp->fx_next->fx_r_type
13252 == BFD_RELOC_MIPS_GOT_LO16))
13253 || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
13254 && (fixp->fx_next->fx_r_type
13255 == BFD_RELOC_MIPS_CALL_LO16)));
13260 fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal;
13261 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
13262 reloc->addend += fixp->fx_frag->tc_frag_data.tc_fr_offset;
13263 reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent));
13264 reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
13265 *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
13266 reloc2->address = (reloc->address
13267 + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype)
13268 - RELAX_RELOC1 (fixp->fx_frag->fr_subtype)));
13269 reloc2->addend = fixp->fx_addnumber - S_GET_VALUE (fixp->fx_addsy)
13270 + fixp->fx_frag->tc_frag_data.tc_fr_offset;
13271 reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16);
13272 assert (reloc2->howto != NULL);
13274 if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype))
13278 reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent));
13280 reloc3->address += 4;
13283 if (mips_pic == NO_PIC)
13285 assert (fixp->fx_r_type == BFD_RELOC_GPREL16);
13286 fixp->fx_r_type = BFD_RELOC_HI16_S;
13288 else if (mips_pic == SVR4_PIC)
13290 switch (fixp->fx_r_type)
13294 case BFD_RELOC_MIPS_GOT16:
13296 case BFD_RELOC_MIPS_GOT_LO16:
13297 case BFD_RELOC_MIPS_CALL_LO16:
13300 fixp->fx_r_type = BFD_RELOC_MIPS_GOT_PAGE;
13301 reloc2->howto = bfd_reloc_type_lookup
13302 (stdoutput, BFD_RELOC_MIPS_GOT_OFST);
13305 fixp->fx_r_type = BFD_RELOC_MIPS_GOT16;
13307 case BFD_RELOC_MIPS_CALL16:
13308 case BFD_RELOC_MIPS_GOT_OFST:
13309 case BFD_RELOC_MIPS_GOT_DISP:
13312 /* It may seem nonsensical to relax GOT_DISP to
13313 GOT_DISP, but we're actually turning a GOT_DISP
13314 without offset into a GOT_DISP with an offset,
13315 getting rid of the separate addition, which we can
13316 do when the symbol is found to be local. */
13317 fixp->fx_r_type = BFD_RELOC_MIPS_GOT_DISP;
13321 fixp->fx_r_type = BFD_RELOC_MIPS_GOT16;
13329 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
13330 entry to be used in the relocation's section offset. */
13331 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
13333 reloc->address = reloc->addend;
13337 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
13338 fixup_segment converted a non-PC relative reloc into a PC
13339 relative reloc. In such a case, we need to convert the reloc
13341 code = fixp->fx_r_type;
13342 if (fixp->fx_pcrel)
13347 code = BFD_RELOC_8_PCREL;
13350 code = BFD_RELOC_16_PCREL;
13353 code = BFD_RELOC_32_PCREL;
13356 code = BFD_RELOC_64_PCREL;
13358 case BFD_RELOC_8_PCREL:
13359 case BFD_RELOC_16_PCREL:
13360 case BFD_RELOC_32_PCREL:
13361 case BFD_RELOC_64_PCREL:
13362 case BFD_RELOC_16_PCREL_S2:
13363 case BFD_RELOC_PCREL_HI16_S:
13364 case BFD_RELOC_PCREL_LO16:
13367 as_bad_where (fixp->fx_file, fixp->fx_line,
13368 _("Cannot make %s relocation PC relative"),
13369 bfd_get_reloc_code_name (code));
13373 /* To support a PC relative reloc when generating embedded PIC code
13374 for ECOFF, we use a Cygnus extension. We check for that here to
13375 make sure that we don't let such a reloc escape normally. */
13376 if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
13377 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
13378 && code == BFD_RELOC_16_PCREL_S2
13379 && mips_pic != EMBEDDED_PIC)
13380 reloc->howto = NULL;
13382 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
13384 if (reloc->howto == NULL)
13386 as_bad_where (fixp->fx_file, fixp->fx_line,
13387 _("Can not represent %s relocation in this object file format"),
13388 bfd_get_reloc_code_name (code));
13395 /* Relax a machine dependent frag. This returns the amount by which
13396 the current size of the frag should change. */
13399 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
13401 if (RELAX_BRANCH_P (fragp->fr_subtype))
13403 offsetT old_var = fragp->fr_var;
13405 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
13407 return fragp->fr_var - old_var;
13410 if (! RELAX_MIPS16_P (fragp->fr_subtype))
13413 if (mips16_extended_frag (fragp, NULL, stretch))
13415 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13417 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
13422 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13424 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
13431 /* Convert a machine dependent frag. */
13434 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
13439 if (RELAX_BRANCH_P (fragp->fr_subtype))
13442 unsigned long insn;
13446 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
13448 if (target_big_endian)
13449 insn = bfd_getb32 (buf);
13451 insn = bfd_getl32 (buf);
13453 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
13455 /* We generate a fixup instead of applying it right now
13456 because, if there are linker relaxations, we're going to
13457 need the relocations. */
13458 exp.X_op = O_symbol;
13459 exp.X_add_symbol = fragp->fr_symbol;
13460 exp.X_add_number = fragp->fr_offset;
13462 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13464 BFD_RELOC_16_PCREL_S2);
13465 fixp->fx_file = fragp->fr_file;
13466 fixp->fx_line = fragp->fr_line;
13468 md_number_to_chars (buf, insn, 4);
13475 as_warn_where (fragp->fr_file, fragp->fr_line,
13476 _("relaxed out-of-range branch into a jump"));
13478 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
13481 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13483 /* Reverse the branch. */
13484 switch ((insn >> 28) & 0xf)
13487 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
13488 have the condition reversed by tweaking a single
13489 bit, and their opcodes all have 0x4???????. */
13490 assert ((insn & 0xf1000000) == 0x41000000);
13491 insn ^= 0x00010000;
13495 /* bltz 0x04000000 bgez 0x04010000
13496 bltzal 0x04100000 bgezal 0x04110000 */
13497 assert ((insn & 0xfc0e0000) == 0x04000000);
13498 insn ^= 0x00010000;
13502 /* beq 0x10000000 bne 0x14000000
13503 blez 0x18000000 bgtz 0x1c000000 */
13504 insn ^= 0x04000000;
13512 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13514 /* Clear the and-link bit. */
13515 assert ((insn & 0xfc1c0000) == 0x04100000);
13517 /* bltzal 0x04100000 bgezal 0x04110000
13518 bltzall 0x04120000 bgezall 0x04130000 */
13519 insn &= ~0x00100000;
13522 /* Branch over the branch (if the branch was likely) or the
13523 full jump (not likely case). Compute the offset from the
13524 current instruction to branch to. */
13525 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13529 /* How many bytes in instructions we've already emitted? */
13530 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
13531 /* How many bytes in instructions from here to the end? */
13532 i = fragp->fr_var - i;
13534 /* Convert to instruction count. */
13536 /* Branch counts from the next instruction. */
13539 /* Branch over the jump. */
13540 md_number_to_chars (buf, insn, 4);
13544 md_number_to_chars (buf, 0, 4);
13547 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13549 /* beql $0, $0, 2f */
13551 /* Compute the PC offset from the current instruction to
13552 the end of the variable frag. */
13553 /* How many bytes in instructions we've already emitted? */
13554 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
13555 /* How many bytes in instructions from here to the end? */
13556 i = fragp->fr_var - i;
13557 /* Convert to instruction count. */
13559 /* Don't decrement i, because we want to branch over the
13563 md_number_to_chars (buf, insn, 4);
13566 md_number_to_chars (buf, 0, 4);
13571 if (mips_pic == NO_PIC)
13574 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
13575 ? 0x0c000000 : 0x08000000);
13576 exp.X_op = O_symbol;
13577 exp.X_add_symbol = fragp->fr_symbol;
13578 exp.X_add_number = fragp->fr_offset;
13580 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13581 4, &exp, 0, BFD_RELOC_MIPS_JMP);
13582 fixp->fx_file = fragp->fr_file;
13583 fixp->fx_line = fragp->fr_line;
13585 md_number_to_chars (buf, insn, 4);
13590 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13591 insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000;
13592 exp.X_op = O_symbol;
13593 exp.X_add_symbol = fragp->fr_symbol;
13594 exp.X_add_number = fragp->fr_offset;
13596 if (fragp->fr_offset)
13598 exp.X_add_symbol = make_expr_symbol (&exp);
13599 exp.X_add_number = 0;
13602 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13603 4, &exp, 0, BFD_RELOC_MIPS_GOT16);
13604 fixp->fx_file = fragp->fr_file;
13605 fixp->fx_line = fragp->fr_line;
13607 md_number_to_chars (buf, insn, 4);
13610 if (mips_opts.isa == ISA_MIPS1)
13613 md_number_to_chars (buf, 0, 4);
13617 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13618 insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000;
13620 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13621 4, &exp, 0, BFD_RELOC_LO16);
13622 fixp->fx_file = fragp->fr_file;
13623 fixp->fx_line = fragp->fr_line;
13625 md_number_to_chars (buf, insn, 4);
13629 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13634 md_number_to_chars (buf, insn, 4);
13639 assert (buf == (bfd_byte *)fragp->fr_literal
13640 + fragp->fr_fix + fragp->fr_var);
13642 fragp->fr_fix += fragp->fr_var;
13647 if (RELAX_MIPS16_P (fragp->fr_subtype))
13650 register const struct mips16_immed_operand *op;
13651 bfd_boolean small, ext;
13654 unsigned long insn;
13655 bfd_boolean use_extend;
13656 unsigned short extend;
13658 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
13659 op = mips16_immed_operands;
13660 while (op->type != type)
13663 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13674 resolve_symbol_value (fragp->fr_symbol);
13675 val = S_GET_VALUE (fragp->fr_symbol);
13680 addr = fragp->fr_address + fragp->fr_fix;
13682 /* The rules for the base address of a PC relative reloc are
13683 complicated; see mips16_extended_frag. */
13684 if (type == 'p' || type == 'q')
13689 /* Ignore the low bit in the target, since it will be
13690 set for a text label. */
13691 if ((val & 1) != 0)
13694 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
13696 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
13699 addr &= ~ (addressT) ((1 << op->shift) - 1);
13702 /* Make sure the section winds up with the alignment we have
13705 record_alignment (asec, op->shift);
13709 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
13710 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
13711 as_warn_where (fragp->fr_file, fragp->fr_line,
13712 _("extended instruction in delay slot"));
13714 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
13716 if (target_big_endian)
13717 insn = bfd_getb16 (buf);
13719 insn = bfd_getl16 (buf);
13721 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
13722 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
13723 small, ext, &insn, &use_extend, &extend);
13727 md_number_to_chars (buf, 0xf000 | extend, 2);
13728 fragp->fr_fix += 2;
13732 md_number_to_chars (buf, insn, 2);
13733 fragp->fr_fix += 2;
13738 if (fragp->fr_opcode == NULL)
13741 old = RELAX_OLD (fragp->fr_subtype);
13742 new = RELAX_NEW (fragp->fr_subtype);
13743 fixptr = fragp->fr_literal + fragp->fr_fix;
13746 memmove (fixptr - old, fixptr, new);
13748 fragp->fr_fix += new - old;
13754 /* This function is called after the relocs have been generated.
13755 We've been storing mips16 text labels as odd. Here we convert them
13756 back to even for the convenience of the debugger. */
13759 mips_frob_file_after_relocs (void)
13762 unsigned int count, i;
13764 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
13767 syms = bfd_get_outsymbols (stdoutput);
13768 count = bfd_get_symcount (stdoutput);
13769 for (i = 0; i < count; i++, syms++)
13771 if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16
13772 && ((*syms)->value & 1) != 0)
13774 (*syms)->value &= ~1;
13775 /* If the symbol has an odd size, it was probably computed
13776 incorrectly, so adjust that as well. */
13777 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
13778 ++elf_symbol (*syms)->internal_elf_sym.st_size;
13785 /* This function is called whenever a label is defined. It is used
13786 when handling branch delays; if a branch has a label, we assume we
13787 can not move it. */
13790 mips_define_label (symbolS *sym)
13792 struct insn_label_list *l;
13794 if (free_insn_labels == NULL)
13795 l = (struct insn_label_list *) xmalloc (sizeof *l);
13798 l = free_insn_labels;
13799 free_insn_labels = l->next;
13803 l->next = insn_labels;
13807 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13809 /* Some special processing for a MIPS ELF file. */
13812 mips_elf_final_processing (void)
13814 /* Write out the register information. */
13815 if (mips_abi != N64_ABI)
13819 s.ri_gprmask = mips_gprmask;
13820 s.ri_cprmask[0] = mips_cprmask[0];
13821 s.ri_cprmask[1] = mips_cprmask[1];
13822 s.ri_cprmask[2] = mips_cprmask[2];
13823 s.ri_cprmask[3] = mips_cprmask[3];
13824 /* The gp_value field is set by the MIPS ELF backend. */
13826 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
13827 ((Elf32_External_RegInfo *)
13828 mips_regmask_frag));
13832 Elf64_Internal_RegInfo s;
13834 s.ri_gprmask = mips_gprmask;
13836 s.ri_cprmask[0] = mips_cprmask[0];
13837 s.ri_cprmask[1] = mips_cprmask[1];
13838 s.ri_cprmask[2] = mips_cprmask[2];
13839 s.ri_cprmask[3] = mips_cprmask[3];
13840 /* The gp_value field is set by the MIPS ELF backend. */
13842 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
13843 ((Elf64_External_RegInfo *)
13844 mips_regmask_frag));
13847 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13848 sort of BFD interface for this. */
13849 if (mips_any_noreorder)
13850 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
13851 if (mips_pic != NO_PIC)
13853 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
13854 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
13857 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
13859 /* Set MIPS ELF flags for ASEs. */
13860 if (file_ase_mips16)
13861 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
13862 #if 0 /* XXX FIXME */
13863 if (file_ase_mips3d)
13864 elf_elfheader (stdoutput)->e_flags |= ???;
13867 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
13869 /* Set the MIPS ELF ABI flags. */
13870 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
13871 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
13872 else if (mips_abi == O64_ABI)
13873 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
13874 else if (mips_abi == EABI_ABI)
13876 if (!file_mips_gp32)
13877 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
13879 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
13881 else if (mips_abi == N32_ABI)
13882 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
13884 /* Nothing to do for N64_ABI. */
13886 if (mips_32bitmode)
13887 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
13890 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13892 typedef struct proc {
13894 unsigned long reg_mask;
13895 unsigned long reg_offset;
13896 unsigned long fpreg_mask;
13897 unsigned long fpreg_offset;
13898 unsigned long frame_offset;
13899 unsigned long frame_reg;
13900 unsigned long pc_reg;
13903 static procS cur_proc;
13904 static procS *cur_proc_ptr;
13905 static int numprocs;
13907 /* Fill in an rs_align_code fragment. */
13910 mips_handle_align (fragS *fragp)
13912 if (fragp->fr_type != rs_align_code)
13915 if (mips_opts.mips16)
13917 static const unsigned char be_nop[] = { 0x65, 0x00 };
13918 static const unsigned char le_nop[] = { 0x00, 0x65 };
13923 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
13924 p = fragp->fr_literal + fragp->fr_fix;
13932 memcpy (p, (target_big_endian ? be_nop : le_nop), 2);
13936 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13940 md_obj_begin (void)
13947 /* check for premature end, nesting errors, etc */
13949 as_warn (_("missing .end at end of assembly"));
13958 if (*input_line_pointer == '-')
13960 ++input_line_pointer;
13963 if (!ISDIGIT (*input_line_pointer))
13964 as_bad (_("expected simple number"));
13965 if (input_line_pointer[0] == '0')
13967 if (input_line_pointer[1] == 'x')
13969 input_line_pointer += 2;
13970 while (ISXDIGIT (*input_line_pointer))
13973 val |= hex_value (*input_line_pointer++);
13975 return negative ? -val : val;
13979 ++input_line_pointer;
13980 while (ISDIGIT (*input_line_pointer))
13983 val |= *input_line_pointer++ - '0';
13985 return negative ? -val : val;
13988 if (!ISDIGIT (*input_line_pointer))
13990 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13991 *input_line_pointer, *input_line_pointer);
13992 as_warn (_("invalid number"));
13995 while (ISDIGIT (*input_line_pointer))
13998 val += *input_line_pointer++ - '0';
14000 return negative ? -val : val;
14003 /* The .file directive; just like the usual .file directive, but there
14004 is an initial number which is the ECOFF file index. In the non-ECOFF
14005 case .file implies DWARF-2. */
14008 s_mips_file (int x ATTRIBUTE_UNUSED)
14010 static int first_file_directive = 0;
14012 if (ECOFF_DEBUGGING)
14021 filename = dwarf2_directive_file (0);
14023 /* Versions of GCC up to 3.1 start files with a ".file"
14024 directive even for stabs output. Make sure that this
14025 ".file" is handled. Note that you need a version of GCC
14026 after 3.1 in order to support DWARF-2 on MIPS. */
14027 if (filename != NULL && ! first_file_directive)
14029 (void) new_logical_line (filename, -1);
14030 s_app_file_string (filename);
14032 first_file_directive = 1;
14036 /* The .loc directive, implying DWARF-2. */
14039 s_mips_loc (int x ATTRIBUTE_UNUSED)
14041 if (!ECOFF_DEBUGGING)
14042 dwarf2_directive_loc (0);
14045 /* The .end directive. */
14048 s_mips_end (int x ATTRIBUTE_UNUSED)
14052 /* Following functions need their own .frame and .cprestore directives. */
14053 mips_frame_reg_valid = 0;
14054 mips_cprestore_valid = 0;
14056 if (!is_end_of_line[(unsigned char) *input_line_pointer])
14059 demand_empty_rest_of_line ();
14064 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
14065 as_warn (_(".end not in text section"));
14069 as_warn (_(".end directive without a preceding .ent directive."));
14070 demand_empty_rest_of_line ();
14076 assert (S_GET_NAME (p));
14077 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym)))
14078 as_warn (_(".end symbol does not match .ent symbol."));
14080 if (debug_type == DEBUG_STABS)
14081 stabs_generate_asm_endfunc (S_GET_NAME (p),
14085 as_warn (_(".end directive missing or unknown symbol"));
14088 /* Generate a .pdr section. */
14089 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING
14092 segT saved_seg = now_seg;
14093 subsegT saved_subseg = now_subseg;
14098 dot = frag_now_fix ();
14100 #ifdef md_flush_pending_output
14101 md_flush_pending_output ();
14105 subseg_set (pdr_seg, 0);
14107 /* Write the symbol. */
14108 exp.X_op = O_symbol;
14109 exp.X_add_symbol = p;
14110 exp.X_add_number = 0;
14111 emit_expr (&exp, 4);
14113 fragp = frag_more (7 * 4);
14115 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
14116 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
14117 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
14118 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
14119 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
14120 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
14121 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
14123 subseg_set (saved_seg, saved_subseg);
14125 #endif /* OBJ_ELF */
14127 cur_proc_ptr = NULL;
14130 /* The .aent and .ent directives. */
14133 s_mips_ent (int aent)
14137 symbolP = get_symbol ();
14138 if (*input_line_pointer == ',')
14139 ++input_line_pointer;
14140 SKIP_WHITESPACE ();
14141 if (ISDIGIT (*input_line_pointer)
14142 || *input_line_pointer == '-')
14145 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
14146 as_warn (_(".ent or .aent not in text section."));
14148 if (!aent && cur_proc_ptr)
14149 as_warn (_("missing .end"));
14153 /* This function needs its own .frame and .cprestore directives. */
14154 mips_frame_reg_valid = 0;
14155 mips_cprestore_valid = 0;
14157 cur_proc_ptr = &cur_proc;
14158 memset (cur_proc_ptr, '\0', sizeof (procS));
14160 cur_proc_ptr->isym = symbolP;
14162 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
14166 if (debug_type == DEBUG_STABS)
14167 stabs_generate_asm_func (S_GET_NAME (symbolP),
14168 S_GET_NAME (symbolP));
14171 demand_empty_rest_of_line ();
14174 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
14175 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
14176 s_mips_frame is used so that we can set the PDR information correctly.
14177 We can't use the ecoff routines because they make reference to the ecoff
14178 symbol table (in the mdebug section). */
14181 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
14184 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
14188 if (cur_proc_ptr == (procS *) NULL)
14190 as_warn (_(".frame outside of .ent"));
14191 demand_empty_rest_of_line ();
14195 cur_proc_ptr->frame_reg = tc_get_register (1);
14197 SKIP_WHITESPACE ();
14198 if (*input_line_pointer++ != ','
14199 || get_absolute_expression_and_terminator (&val) != ',')
14201 as_warn (_("Bad .frame directive"));
14202 --input_line_pointer;
14203 demand_empty_rest_of_line ();
14207 cur_proc_ptr->frame_offset = val;
14208 cur_proc_ptr->pc_reg = tc_get_register (0);
14210 demand_empty_rest_of_line ();
14213 #endif /* OBJ_ELF */
14217 /* The .fmask and .mask directives. If the mdebug section is present
14218 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
14219 embedded targets, s_mips_mask is used so that we can set the PDR
14220 information correctly. We can't use the ecoff routines because they
14221 make reference to the ecoff symbol table (in the mdebug section). */
14224 s_mips_mask (int reg_type)
14227 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
14231 if (cur_proc_ptr == (procS *) NULL)
14233 as_warn (_(".mask/.fmask outside of .ent"));
14234 demand_empty_rest_of_line ();
14238 if (get_absolute_expression_and_terminator (&mask) != ',')
14240 as_warn (_("Bad .mask/.fmask directive"));
14241 --input_line_pointer;
14242 demand_empty_rest_of_line ();
14246 off = get_absolute_expression ();
14248 if (reg_type == 'F')
14250 cur_proc_ptr->fpreg_mask = mask;
14251 cur_proc_ptr->fpreg_offset = off;
14255 cur_proc_ptr->reg_mask = mask;
14256 cur_proc_ptr->reg_offset = off;
14259 demand_empty_rest_of_line ();
14262 #endif /* OBJ_ELF */
14263 s_ignore (reg_type);
14266 /* The .loc directive. */
14276 assert (now_seg == text_section);
14278 lineno = get_number ();
14279 addroff = frag_now_fix ();
14281 symbolP = symbol_new ("", N_SLINE, addroff, frag_now);
14282 S_SET_TYPE (symbolP, N_SLINE);
14283 S_SET_OTHER (symbolP, 0);
14284 S_SET_DESC (symbolP, lineno);
14285 symbolP->sy_segment = now_seg;
14289 /* A table describing all the processors gas knows about. Names are
14290 matched in the order listed.
14292 To ease comparison, please keep this table in the same order as
14293 gcc's mips_cpu_info_table[]. */
14294 static const struct mips_cpu_info mips_cpu_info_table[] =
14296 /* Entries for generic ISAs */
14297 { "mips1", 1, ISA_MIPS1, CPU_R3000 },
14298 { "mips2", 1, ISA_MIPS2, CPU_R6000 },
14299 { "mips3", 1, ISA_MIPS3, CPU_R4000 },
14300 { "mips4", 1, ISA_MIPS4, CPU_R8000 },
14301 { "mips5", 1, ISA_MIPS5, CPU_MIPS5 },
14302 { "mips32", 1, ISA_MIPS32, CPU_MIPS32 },
14303 { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 },
14304 { "mips64", 1, ISA_MIPS64, CPU_MIPS64 },
14307 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
14308 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
14309 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
14312 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
14315 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
14316 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
14317 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
14318 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
14319 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
14320 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
14321 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
14322 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
14323 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
14324 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
14325 { "orion", 0, ISA_MIPS3, CPU_R4600 },
14326 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
14329 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
14330 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
14331 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
14332 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
14333 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
14334 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
14335 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
14336 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
14337 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
14338 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
14339 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
14340 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
14341 { "rm9000", 0, ISA_MIPS4, CPU_RM7000 },
14344 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
14345 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
14346 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
14349 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
14350 { "20kc", 0, ISA_MIPS64, CPU_MIPS64 },
14352 /* Broadcom SB-1 CPU core */
14353 { "sb1", 0, ISA_MIPS64, CPU_SB1 },
14360 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14361 with a final "000" replaced by "k". Ignore case.
14363 Note: this function is shared between GCC and GAS. */
14366 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
14368 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
14369 given++, canonical++;
14371 return ((*given == 0 && *canonical == 0)
14372 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
14376 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14377 CPU name. We've traditionally allowed a lot of variation here.
14379 Note: this function is shared between GCC and GAS. */
14382 mips_matching_cpu_name_p (const char *canonical, const char *given)
14384 /* First see if the name matches exactly, or with a final "000"
14385 turned into "k". */
14386 if (mips_strict_matching_cpu_name_p (canonical, given))
14389 /* If not, try comparing based on numerical designation alone.
14390 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14391 if (TOLOWER (*given) == 'r')
14393 if (!ISDIGIT (*given))
14396 /* Skip over some well-known prefixes in the canonical name,
14397 hoping to find a number there too. */
14398 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
14400 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
14402 else if (TOLOWER (canonical[0]) == 'r')
14405 return mips_strict_matching_cpu_name_p (canonical, given);
14409 /* Parse an option that takes the name of a processor as its argument.
14410 OPTION is the name of the option and CPU_STRING is the argument.
14411 Return the corresponding processor enumeration if the CPU_STRING is
14412 recognized, otherwise report an error and return null.
14414 A similar function exists in GCC. */
14416 static const struct mips_cpu_info *
14417 mips_parse_cpu (const char *option, const char *cpu_string)
14419 const struct mips_cpu_info *p;
14421 /* 'from-abi' selects the most compatible architecture for the given
14422 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14423 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14424 version. Look first at the -mgp options, if given, otherwise base
14425 the choice on MIPS_DEFAULT_64BIT.
14427 Treat NO_ABI like the EABIs. One reason to do this is that the
14428 plain 'mips' and 'mips64' configs have 'from-abi' as their default
14429 architecture. This code picks MIPS I for 'mips' and MIPS III for
14430 'mips64', just as we did in the days before 'from-abi'. */
14431 if (strcasecmp (cpu_string, "from-abi") == 0)
14433 if (ABI_NEEDS_32BIT_REGS (mips_abi))
14434 return mips_cpu_info_from_isa (ISA_MIPS1);
14436 if (ABI_NEEDS_64BIT_REGS (mips_abi))
14437 return mips_cpu_info_from_isa (ISA_MIPS3);
14439 if (file_mips_gp32 >= 0)
14440 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
14442 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
14447 /* 'default' has traditionally been a no-op. Probably not very useful. */
14448 if (strcasecmp (cpu_string, "default") == 0)
14451 for (p = mips_cpu_info_table; p->name != 0; p++)
14452 if (mips_matching_cpu_name_p (p->name, cpu_string))
14455 as_bad ("Bad value (%s) for %s", cpu_string, option);
14459 /* Return the canonical processor information for ISA (a member of the
14460 ISA_MIPS* enumeration). */
14462 static const struct mips_cpu_info *
14463 mips_cpu_info_from_isa (int isa)
14467 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14468 if (mips_cpu_info_table[i].is_isa
14469 && isa == mips_cpu_info_table[i].isa)
14470 return (&mips_cpu_info_table[i]);
14475 static const struct mips_cpu_info *
14476 mips_cpu_info_from_arch (int arch)
14480 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14481 if (arch == mips_cpu_info_table[i].cpu)
14482 return (&mips_cpu_info_table[i]);
14488 show (FILE *stream, const char *string, int *col_p, int *first_p)
14492 fprintf (stream, "%24s", "");
14497 fprintf (stream, ", ");
14501 if (*col_p + strlen (string) > 72)
14503 fprintf (stream, "\n%24s", "");
14507 fprintf (stream, "%s", string);
14508 *col_p += strlen (string);
14514 md_show_usage (FILE *stream)
14519 fprintf (stream, _("\
14521 -membedded-pic generate embedded position independent code\n\
14522 -EB generate big endian output\n\
14523 -EL generate little endian output\n\
14524 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14525 -G NUM allow referencing objects up to NUM bytes\n\
14526 implicitly with the gp register [default 8]\n"));
14527 fprintf (stream, _("\
14528 -mips1 generate MIPS ISA I instructions\n\
14529 -mips2 generate MIPS ISA II instructions\n\
14530 -mips3 generate MIPS ISA III instructions\n\
14531 -mips4 generate MIPS ISA IV instructions\n\
14532 -mips5 generate MIPS ISA V instructions\n\
14533 -mips32 generate MIPS32 ISA instructions\n\
14534 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14535 -mips64 generate MIPS64 ISA instructions\n\
14536 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14540 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14541 show (stream, mips_cpu_info_table[i].name, &column, &first);
14542 show (stream, "from-abi", &column, &first);
14543 fputc ('\n', stream);
14545 fprintf (stream, _("\
14546 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14547 -no-mCPU don't generate code specific to CPU.\n\
14548 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14552 show (stream, "3900", &column, &first);
14553 show (stream, "4010", &column, &first);
14554 show (stream, "4100", &column, &first);
14555 show (stream, "4650", &column, &first);
14556 fputc ('\n', stream);
14558 fprintf (stream, _("\
14559 -mips16 generate mips16 instructions\n\
14560 -no-mips16 do not generate mips16 instructions\n"));
14561 fprintf (stream, _("\
14562 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14563 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14564 -O0 remove unneeded NOPs, do not swap branches\n\
14565 -O remove unneeded NOPs and swap branches\n\
14566 -n warn about NOPs generated from macros\n\
14567 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14568 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14569 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14571 fprintf (stream, _("\
14572 -KPIC, -call_shared generate SVR4 position independent code\n\
14573 -non_shared do not generate position independent code\n\
14574 -xgot assume a 32 bit GOT\n\
14575 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14576 -mabi=ABI create ABI conformant object file for:\n"));
14580 show (stream, "32", &column, &first);
14581 show (stream, "o64", &column, &first);
14582 show (stream, "n32", &column, &first);
14583 show (stream, "64", &column, &first);
14584 show (stream, "eabi", &column, &first);
14586 fputc ('\n', stream);
14588 fprintf (stream, _("\
14589 -32 create o32 ABI object file (default)\n\
14590 -n32 create n32 ABI object file\n\
14591 -64 create 64 ABI object file\n"));
14596 mips_dwarf2_format (void)
14598 if (mips_abi == N64_ABI)
14601 return dwarf2_format_64bit_irix;
14603 return dwarf2_format_64bit;
14607 return dwarf2_format_32bit;