1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2018 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1];
37 typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define streq(a, b) (strcmp (a, b) == 0)
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug = -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr = FALSE;
86 int mips_flag_pdr = TRUE;
91 static char *mips_regmask_frag;
92 static char *mips_flags_frag;
99 #define PIC_CALL_REG 25
107 #define ILLEGAL_REG (32)
109 #define AT mips_opts.at
111 extern int target_big_endian;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME ".rodata"
116 /* Ways in which an instruction can be "appended" to the output. */
118 /* Just add it normally. */
121 /* Add it normally and then add a nop. */
124 /* Turn an instruction with a delay slot into a "compact" version. */
127 /* Insert the instruction before the last one. */
131 /* Information about an instruction, including its format, operands
135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
136 const struct mips_opcode *insn_mo;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. If we have
140 decided to use an extended MIPS16 instruction, this includes the
142 unsigned long insn_opcode;
144 /* The frag that contains the instruction. */
147 /* The offset into FRAG of the first instruction byte. */
150 /* The relocs associated with the instruction, if any. */
153 /* True if this entry cannot be moved from its current position. */
154 unsigned int fixed_p : 1;
156 /* True if this instruction occurred in a .set noreorder block. */
157 unsigned int noreorder_p : 1;
159 /* True for mips16 instructions that jump to an absolute address. */
160 unsigned int mips16_absolute_jump_p : 1;
162 /* True if this instruction is complete. */
163 unsigned int complete_p : 1;
165 /* True if this instruction is cleared from history by unconditional
167 unsigned int cleared_p : 1;
170 /* The ABI to use. */
181 /* MIPS ABI we are using for this output file. */
182 static enum mips_abi_level mips_abi = NO_ABI;
184 /* Whether or not we have code that can call pic code. */
185 int mips_abicalls = FALSE;
187 /* Whether or not we have code which can be put into a shared
189 static bfd_boolean mips_in_shared = TRUE;
191 /* This is the set of options which may be modified by the .set
192 pseudo-op. We use a struct so that .set push and .set pop are more
195 struct mips_set_options
197 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
198 if it has not been initialized. Changed by `.set mipsN', and the
199 -mipsN command line option, and the default CPU. */
201 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
202 <asename>', by command line options, and based on the default
205 /* Whether we are assembling for the mips16 processor. 0 if we are
206 not, 1 if we are, and -1 if the value has not been initialized.
207 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
208 -nomips16 command line options, and the default CPU. */
210 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
211 1 if we are, and -1 if the value has not been initialized. Changed
212 by `.set micromips' and `.set nomicromips', and the -mmicromips
213 and -mno-micromips command line options, and the default CPU. */
215 /* Non-zero if we should not reorder instructions. Changed by `.set
216 reorder' and `.set noreorder'. */
218 /* Non-zero if we should not permit the register designated "assembler
219 temporary" to be used in instructions. The value is the register
220 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
221 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
223 /* Non-zero if we should warn when a macro instruction expands into
224 more than one machine instruction. Changed by `.set nomacro' and
226 int warn_about_macros;
227 /* Non-zero if we should not move instructions. Changed by `.set
228 move', `.set volatile', `.set nomove', and `.set novolatile'. */
230 /* Non-zero if we should not optimize branches by moving the target
231 of the branch into the delay slot. Actually, we don't perform
232 this optimization anyhow. Changed by `.set bopt' and `.set
235 /* Non-zero if we should not autoextend mips16 instructions.
236 Changed by `.set autoextend' and `.set noautoextend'. */
238 /* True if we should only emit 32-bit microMIPS instructions.
239 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
240 and -mno-insn32 command line options. */
242 /* Restrict general purpose registers and floating point registers
243 to 32 bit. This is initially determined when -mgp32 or -mfp32
244 is passed but can changed if the assembler code uses .set mipsN. */
247 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
248 command line option, and the default CPU. */
250 /* True if ".set sym32" is in effect. */
252 /* True if floating-point operations are not allowed. Changed by .set
253 softfloat or .set hardfloat, by command line options -msoft-float or
254 -mhard-float. The default is false. */
255 bfd_boolean soft_float;
257 /* True if only single-precision floating-point operations are allowed.
258 Changed by .set singlefloat or .set doublefloat, command-line options
259 -msingle-float or -mdouble-float. The default is false. */
260 bfd_boolean single_float;
262 /* 1 if single-precision operations on odd-numbered registers are
267 /* Specifies whether module level options have been checked yet. */
268 static bfd_boolean file_mips_opts_checked = FALSE;
270 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
271 value has not been initialized. Changed by `.nan legacy' and
272 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
273 options, and the default CPU. */
274 static int mips_nan2008 = -1;
276 /* This is the struct we use to hold the module level set of options.
277 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
278 fp fields to -1 to indicate that they have not been initialized. */
280 static struct mips_set_options file_mips_opts =
282 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
283 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
284 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
285 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
286 /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1
289 /* This is similar to file_mips_opts, but for the current set of options. */
291 static struct mips_set_options mips_opts =
293 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
294 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
295 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
296 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
297 /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1
300 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
301 static unsigned int file_ase_explicit;
303 /* These variables are filled in with the masks of registers used.
304 The object format code reads them and puts them in the appropriate
306 unsigned long mips_gprmask;
307 unsigned long mips_cprmask[4];
309 /* True if any MIPS16 code was produced. */
310 static int file_ase_mips16;
312 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
313 || mips_opts.isa == ISA_MIPS32R2 \
314 || mips_opts.isa == ISA_MIPS32R3 \
315 || mips_opts.isa == ISA_MIPS32R5 \
316 || mips_opts.isa == ISA_MIPS64 \
317 || mips_opts.isa == ISA_MIPS64R2 \
318 || mips_opts.isa == ISA_MIPS64R3 \
319 || mips_opts.isa == ISA_MIPS64R5)
321 /* True if any microMIPS code was produced. */
322 static int file_ase_micromips;
324 /* True if we want to create R_MIPS_JALR for jalr $25. */
326 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
328 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
329 because there's no place for any addend, the only acceptable
330 expression is a bare symbol. */
331 #define MIPS_JALR_HINT_P(EXPR) \
332 (!HAVE_IN_PLACE_ADDENDS \
333 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
336 /* The argument of the -march= flag. The architecture we are assembling. */
337 static const char *mips_arch_string;
339 /* The argument of the -mtune= flag. The architecture for which we
341 static int mips_tune = CPU_UNKNOWN;
342 static const char *mips_tune_string;
344 /* True when generating 32-bit code for a 64-bit processor. */
345 static int mips_32bitmode = 0;
347 /* True if the given ABI requires 32-bit registers. */
348 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
350 /* Likewise 64-bit registers. */
351 #define ABI_NEEDS_64BIT_REGS(ABI) \
353 || (ABI) == N64_ABI \
356 #define ISA_IS_R6(ISA) \
357 ((ISA) == ISA_MIPS32R6 \
358 || (ISA) == ISA_MIPS64R6)
360 /* Return true if ISA supports 64 bit wide gp registers. */
361 #define ISA_HAS_64BIT_REGS(ISA) \
362 ((ISA) == ISA_MIPS3 \
363 || (ISA) == ISA_MIPS4 \
364 || (ISA) == ISA_MIPS5 \
365 || (ISA) == ISA_MIPS64 \
366 || (ISA) == ISA_MIPS64R2 \
367 || (ISA) == ISA_MIPS64R3 \
368 || (ISA) == ISA_MIPS64R5 \
369 || (ISA) == ISA_MIPS64R6)
371 /* Return true if ISA supports 64 bit wide float registers. */
372 #define ISA_HAS_64BIT_FPRS(ISA) \
373 ((ISA) == ISA_MIPS3 \
374 || (ISA) == ISA_MIPS4 \
375 || (ISA) == ISA_MIPS5 \
376 || (ISA) == ISA_MIPS32R2 \
377 || (ISA) == ISA_MIPS32R3 \
378 || (ISA) == ISA_MIPS32R5 \
379 || (ISA) == ISA_MIPS32R6 \
380 || (ISA) == ISA_MIPS64 \
381 || (ISA) == ISA_MIPS64R2 \
382 || (ISA) == ISA_MIPS64R3 \
383 || (ISA) == ISA_MIPS64R5 \
384 || (ISA) == ISA_MIPS64R6)
386 /* Return true if ISA supports 64-bit right rotate (dror et al.)
388 #define ISA_HAS_DROR(ISA) \
389 ((ISA) == ISA_MIPS64R2 \
390 || (ISA) == ISA_MIPS64R3 \
391 || (ISA) == ISA_MIPS64R5 \
392 || (ISA) == ISA_MIPS64R6 \
393 || (mips_opts.micromips \
394 && ISA_HAS_64BIT_REGS (ISA)) \
397 /* Return true if ISA supports 32-bit right rotate (ror et al.)
399 #define ISA_HAS_ROR(ISA) \
400 ((ISA) == ISA_MIPS32R2 \
401 || (ISA) == ISA_MIPS32R3 \
402 || (ISA) == ISA_MIPS32R5 \
403 || (ISA) == ISA_MIPS32R6 \
404 || (ISA) == ISA_MIPS64R2 \
405 || (ISA) == ISA_MIPS64R3 \
406 || (ISA) == ISA_MIPS64R5 \
407 || (ISA) == ISA_MIPS64R6 \
408 || (mips_opts.ase & ASE_SMARTMIPS) \
409 || mips_opts.micromips \
412 /* Return true if ISA supports single-precision floats in odd registers. */
413 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
414 (((ISA) == ISA_MIPS32 \
415 || (ISA) == ISA_MIPS32R2 \
416 || (ISA) == ISA_MIPS32R3 \
417 || (ISA) == ISA_MIPS32R5 \
418 || (ISA) == ISA_MIPS32R6 \
419 || (ISA) == ISA_MIPS64 \
420 || (ISA) == ISA_MIPS64R2 \
421 || (ISA) == ISA_MIPS64R3 \
422 || (ISA) == ISA_MIPS64R5 \
423 || (ISA) == ISA_MIPS64R6 \
424 || (CPU) == CPU_R5900) \
425 && (CPU) != CPU_GS464)
427 /* Return true if ISA supports move to/from high part of a 64-bit
428 floating-point register. */
429 #define ISA_HAS_MXHC1(ISA) \
430 ((ISA) == ISA_MIPS32R2 \
431 || (ISA) == ISA_MIPS32R3 \
432 || (ISA) == ISA_MIPS32R5 \
433 || (ISA) == ISA_MIPS32R6 \
434 || (ISA) == ISA_MIPS64R2 \
435 || (ISA) == ISA_MIPS64R3 \
436 || (ISA) == ISA_MIPS64R5 \
437 || (ISA) == ISA_MIPS64R6)
439 /* Return true if ISA supports legacy NAN. */
440 #define ISA_HAS_LEGACY_NAN(ISA) \
441 ((ISA) == ISA_MIPS1 \
442 || (ISA) == ISA_MIPS2 \
443 || (ISA) == ISA_MIPS3 \
444 || (ISA) == ISA_MIPS4 \
445 || (ISA) == ISA_MIPS5 \
446 || (ISA) == ISA_MIPS32 \
447 || (ISA) == ISA_MIPS32R2 \
448 || (ISA) == ISA_MIPS32R3 \
449 || (ISA) == ISA_MIPS32R5 \
450 || (ISA) == ISA_MIPS64 \
451 || (ISA) == ISA_MIPS64R2 \
452 || (ISA) == ISA_MIPS64R3 \
453 || (ISA) == ISA_MIPS64R5)
456 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
461 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
465 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
467 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
469 /* True if relocations are stored in-place. */
470 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
472 /* The ABI-derived address size. */
473 #define HAVE_64BIT_ADDRESSES \
474 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
475 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
477 /* The size of symbolic constants (i.e., expressions of the form
478 "SYMBOL" or "SYMBOL + OFFSET"). */
479 #define HAVE_32BIT_SYMBOLS \
480 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
481 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
483 /* Addresses are loaded in different ways, depending on the address size
484 in use. The n32 ABI Documentation also mandates the use of additions
485 with overflow checking, but existing implementations don't follow it. */
486 #define ADDRESS_ADD_INSN \
487 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
489 #define ADDRESS_ADDI_INSN \
490 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
492 #define ADDRESS_LOAD_INSN \
493 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
495 #define ADDRESS_STORE_INSN \
496 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
498 /* Return true if the given CPU supports the MIPS16 ASE. */
499 #define CPU_HAS_MIPS16(cpu) \
500 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
501 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
503 /* Return true if the given CPU supports the microMIPS ASE. */
504 #define CPU_HAS_MICROMIPS(cpu) 0
506 /* True if CPU has a dror instruction. */
507 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
509 /* True if CPU has a ror instruction. */
510 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
512 /* True if CPU is in the Octeon family */
513 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
514 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
516 /* True if CPU has seq/sne and seqi/snei instructions. */
517 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
519 /* True, if CPU has support for ldc1 and sdc1. */
520 #define CPU_HAS_LDC1_SDC1(CPU) \
521 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
523 /* True if mflo and mfhi can be immediately followed by instructions
524 which write to the HI and LO registers.
526 According to MIPS specifications, MIPS ISAs I, II, and III need
527 (at least) two instructions between the reads of HI/LO and
528 instructions which write them, and later ISAs do not. Contradicting
529 the MIPS specifications, some MIPS IV processor user manuals (e.g.
530 the UM for the NEC Vr5000) document needing the instructions between
531 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
532 MIPS64 and later ISAs to have the interlocks, plus any specific
533 earlier-ISA CPUs for which CPU documentation declares that the
534 instructions are really interlocked. */
535 #define hilo_interlocks \
536 (mips_opts.isa == ISA_MIPS32 \
537 || mips_opts.isa == ISA_MIPS32R2 \
538 || mips_opts.isa == ISA_MIPS32R3 \
539 || mips_opts.isa == ISA_MIPS32R5 \
540 || mips_opts.isa == ISA_MIPS32R6 \
541 || mips_opts.isa == ISA_MIPS64 \
542 || mips_opts.isa == ISA_MIPS64R2 \
543 || mips_opts.isa == ISA_MIPS64R3 \
544 || mips_opts.isa == ISA_MIPS64R5 \
545 || mips_opts.isa == ISA_MIPS64R6 \
546 || mips_opts.arch == CPU_R4010 \
547 || mips_opts.arch == CPU_R5900 \
548 || mips_opts.arch == CPU_R10000 \
549 || mips_opts.arch == CPU_R12000 \
550 || mips_opts.arch == CPU_R14000 \
551 || mips_opts.arch == CPU_R16000 \
552 || mips_opts.arch == CPU_RM7000 \
553 || mips_opts.arch == CPU_VR5500 \
554 || mips_opts.micromips \
557 /* Whether the processor uses hardware interlocks to protect reads
558 from the GPRs after they are loaded from memory, and thus does not
559 require nops to be inserted. This applies to instructions marked
560 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
561 level I and microMIPS mode instructions are always interlocked. */
562 #define gpr_interlocks \
563 (mips_opts.isa != ISA_MIPS1 \
564 || mips_opts.arch == CPU_R3900 \
565 || mips_opts.arch == CPU_R5900 \
566 || mips_opts.micromips \
569 /* Whether the processor uses hardware interlocks to avoid delays
570 required by coprocessor instructions, and thus does not require
571 nops to be inserted. This applies to instructions marked
572 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
573 instructions marked INSN_WRITE_COND_CODE and ones marked
574 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
575 levels I, II, and III and microMIPS mode instructions are always
577 /* Itbl support may require additional care here. */
578 #define cop_interlocks \
579 ((mips_opts.isa != ISA_MIPS1 \
580 && mips_opts.isa != ISA_MIPS2 \
581 && mips_opts.isa != ISA_MIPS3) \
582 || mips_opts.arch == CPU_R4300 \
583 || mips_opts.micromips \
586 /* Whether the processor uses hardware interlocks to protect reads
587 from coprocessor registers after they are loaded from memory, and
588 thus does not require nops to be inserted. This applies to
589 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
590 requires at MIPS ISA level I and microMIPS mode instructions are
591 always interlocked. */
592 #define cop_mem_interlocks \
593 (mips_opts.isa != ISA_MIPS1 \
594 || mips_opts.micromips \
597 /* Is this a mfhi or mflo instruction? */
598 #define MF_HILO_INSN(PINFO) \
599 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
601 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
602 has been selected. This implies, in particular, that addresses of text
603 labels have their LSB set. */
604 #define HAVE_CODE_COMPRESSION \
605 ((mips_opts.mips16 | mips_opts.micromips) != 0)
607 /* The minimum and maximum signed values that can be stored in a GPR. */
608 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
609 #define GPR_SMIN (-GPR_SMAX - 1)
611 /* MIPS PIC level. */
613 enum mips_pic_level mips_pic;
615 /* 1 if we should generate 32 bit offsets from the $gp register in
616 SVR4_PIC mode. Currently has no meaning in other modes. */
617 static int mips_big_got = 0;
619 /* 1 if trap instructions should used for overflow rather than break
621 static int mips_trap = 0;
623 /* 1 if double width floating point constants should not be constructed
624 by assembling two single width halves into two single width floating
625 point registers which just happen to alias the double width destination
626 register. On some architectures this aliasing can be disabled by a bit
627 in the status register, and the setting of this bit cannot be determined
628 automatically at assemble time. */
629 static int mips_disable_float_construction;
631 /* Non-zero if any .set noreorder directives were used. */
633 static int mips_any_noreorder;
635 /* Non-zero if nops should be inserted when the register referenced in
636 an mfhi/mflo instruction is read in the next two instructions. */
637 static int mips_7000_hilo_fix;
639 /* The size of objects in the small data section. */
640 static unsigned int g_switch_value = 8;
641 /* Whether the -G option was used. */
642 static int g_switch_seen = 0;
647 /* If we can determine in advance that GP optimization won't be
648 possible, we can skip the relaxation stuff that tries to produce
649 GP-relative references. This makes delay slot optimization work
652 This function can only provide a guess, but it seems to work for
653 gcc output. It needs to guess right for gcc, otherwise gcc
654 will put what it thinks is a GP-relative instruction in a branch
657 I don't know if a fix is needed for the SVR4_PIC mode. I've only
658 fixed it for the non-PIC mode. KR 95/04/07 */
659 static int nopic_need_relax (symbolS *, int);
661 /* handle of the OPCODE hash table */
662 static struct hash_control *op_hash = NULL;
664 /* The opcode hash table we use for the mips16. */
665 static struct hash_control *mips16_op_hash = NULL;
667 /* The opcode hash table we use for the microMIPS ASE. */
668 static struct hash_control *micromips_op_hash = NULL;
670 /* This array holds the chars that always start a comment. If the
671 pre-processor is disabled, these aren't very useful */
672 const char comment_chars[] = "#";
674 /* This array holds the chars that only start a comment at the beginning of
675 a line. If the line seems to have the form '# 123 filename'
676 .line and .file directives will appear in the pre-processed output */
677 /* Note that input_file.c hand checks for '#' at the beginning of the
678 first line of the input file. This is because the compiler outputs
679 #NO_APP at the beginning of its output. */
680 /* Also note that C style comments are always supported. */
681 const char line_comment_chars[] = "#";
683 /* This array holds machine specific line separator characters. */
684 const char line_separator_chars[] = ";";
686 /* Chars that can be used to separate mant from exp in floating point nums */
687 const char EXP_CHARS[] = "eE";
689 /* Chars that mean this number is a floating point constant */
692 const char FLT_CHARS[] = "rRsSfFdDxXpP";
694 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
695 changed in read.c . Ideally it shouldn't have to know about it at all,
696 but nothing is ideal around here.
699 /* Types of printf format used for instruction-related error messages.
700 "I" means int ("%d") and "S" means string ("%s"). */
701 enum mips_insn_error_format {
707 /* Information about an error that was found while assembling the current
709 struct mips_insn_error {
710 /* We sometimes need to match an instruction against more than one
711 opcode table entry. Errors found during this matching are reported
712 against a particular syntactic argument rather than against the
713 instruction as a whole. We grade these messages so that errors
714 against argument N have a greater priority than an error against
715 any argument < N, since the former implies that arguments up to N
716 were acceptable and that the opcode entry was therefore a closer match.
717 If several matches report an error against the same argument,
718 we only use that error if it is the same in all cases.
720 min_argnum is the minimum argument number for which an error message
721 should be accepted. It is 0 if MSG is against the instruction as
725 /* The printf()-style message, including its format and arguments. */
726 enum mips_insn_error_format format;
734 /* The error that should be reported for the current instruction. */
735 static struct mips_insn_error insn_error;
737 static int auto_align = 1;
739 /* When outputting SVR4 PIC code, the assembler needs to know the
740 offset in the stack frame from which to restore the $gp register.
741 This is set by the .cprestore pseudo-op, and saved in this
743 static offsetT mips_cprestore_offset = -1;
745 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
746 more optimizations, it can use a register value instead of a memory-saved
747 offset and even an other register than $gp as global pointer. */
748 static offsetT mips_cpreturn_offset = -1;
749 static int mips_cpreturn_register = -1;
750 static int mips_gp_register = GP;
751 static int mips_gprel_offset = 0;
753 /* Whether mips_cprestore_offset has been set in the current function
754 (or whether it has already been warned about, if not). */
755 static int mips_cprestore_valid = 0;
757 /* This is the register which holds the stack frame, as set by the
758 .frame pseudo-op. This is needed to implement .cprestore. */
759 static int mips_frame_reg = SP;
761 /* Whether mips_frame_reg has been set in the current function
762 (or whether it has already been warned about, if not). */
763 static int mips_frame_reg_valid = 0;
765 /* To output NOP instructions correctly, we need to keep information
766 about the previous two instructions. */
768 /* Whether we are optimizing. The default value of 2 means to remove
769 unneeded NOPs and swap branch instructions when possible. A value
770 of 1 means to not swap branches. A value of 0 means to always
772 static int mips_optimize = 2;
774 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
775 equivalent to seeing no -g option at all. */
776 static int mips_debug = 0;
778 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
779 #define MAX_VR4130_NOPS 4
781 /* The maximum number of NOPs needed to fill delay slots. */
782 #define MAX_DELAY_NOPS 2
784 /* The maximum number of NOPs needed for any purpose. */
787 /* A list of previous instructions, with index 0 being the most recent.
788 We need to look back MAX_NOPS instructions when filling delay slots
789 or working around processor errata. We need to look back one
790 instruction further if we're thinking about using history[0] to
791 fill a branch delay slot. */
792 static struct mips_cl_insn history[1 + MAX_NOPS];
794 /* Arrays of operands for each instruction. */
795 #define MAX_OPERANDS 6
796 struct mips_operand_array {
797 const struct mips_operand *operand[MAX_OPERANDS];
799 static struct mips_operand_array *mips_operands;
800 static struct mips_operand_array *mips16_operands;
801 static struct mips_operand_array *micromips_operands;
803 /* Nop instructions used by emit_nop. */
804 static struct mips_cl_insn nop_insn;
805 static struct mips_cl_insn mips16_nop_insn;
806 static struct mips_cl_insn micromips_nop16_insn;
807 static struct mips_cl_insn micromips_nop32_insn;
809 /* The appropriate nop for the current mode. */
810 #define NOP_INSN (mips_opts.mips16 \
812 : (mips_opts.micromips \
813 ? (mips_opts.insn32 \
814 ? µmips_nop32_insn \
815 : µmips_nop16_insn) \
818 /* The size of NOP_INSN in bytes. */
819 #define NOP_INSN_SIZE ((mips_opts.mips16 \
820 || (mips_opts.micromips && !mips_opts.insn32)) \
823 /* If this is set, it points to a frag holding nop instructions which
824 were inserted before the start of a noreorder section. If those
825 nops turn out to be unnecessary, the size of the frag can be
827 static fragS *prev_nop_frag;
829 /* The number of nop instructions we created in prev_nop_frag. */
830 static int prev_nop_frag_holds;
832 /* The number of nop instructions that we know we need in
834 static int prev_nop_frag_required;
836 /* The number of instructions we've seen since prev_nop_frag. */
837 static int prev_nop_frag_since;
839 /* Relocations against symbols are sometimes done in two parts, with a HI
840 relocation and a LO relocation. Each relocation has only 16 bits of
841 space to store an addend. This means that in order for the linker to
842 handle carries correctly, it must be able to locate both the HI and
843 the LO relocation. This means that the relocations must appear in
844 order in the relocation table.
846 In order to implement this, we keep track of each unmatched HI
847 relocation. We then sort them so that they immediately precede the
848 corresponding LO relocation. */
853 struct mips_hi_fixup *next;
856 /* The section this fixup is in. */
860 /* The list of unmatched HI relocs. */
862 static struct mips_hi_fixup *mips_hi_fixup_list;
864 /* The frag containing the last explicit relocation operator.
865 Null if explicit relocations have not been used. */
867 static fragS *prev_reloc_op_frag;
869 /* Map mips16 register numbers to normal MIPS register numbers. */
871 static const unsigned int mips16_to_32_reg_map[] =
873 16, 17, 2, 3, 4, 5, 6, 7
876 /* Map microMIPS register numbers to normal MIPS register numbers. */
878 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
880 /* The microMIPS registers with type h. */
881 static const unsigned int micromips_to_32_reg_h_map1[] =
883 5, 5, 6, 4, 4, 4, 4, 4
885 static const unsigned int micromips_to_32_reg_h_map2[] =
887 6, 7, 7, 21, 22, 5, 6, 7
890 /* The microMIPS registers with type m. */
891 static const unsigned int micromips_to_32_reg_m_map[] =
893 0, 17, 2, 3, 16, 18, 19, 20
896 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
898 /* Classifies the kind of instructions we're interested in when
899 implementing -mfix-vr4120. */
900 enum fix_vr4120_class
908 NUM_FIX_VR4120_CLASSES
911 /* ...likewise -mfix-loongson2f-jump. */
912 static bfd_boolean mips_fix_loongson2f_jump;
914 /* ...likewise -mfix-loongson2f-nop. */
915 static bfd_boolean mips_fix_loongson2f_nop;
917 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
918 static bfd_boolean mips_fix_loongson2f;
920 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
921 there must be at least one other instruction between an instruction
922 of type X and an instruction of type Y. */
923 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
925 /* True if -mfix-vr4120 is in force. */
926 static int mips_fix_vr4120;
928 /* ...likewise -mfix-vr4130. */
929 static int mips_fix_vr4130;
931 /* ...likewise -mfix-24k. */
932 static int mips_fix_24k;
934 /* ...likewise -mfix-rm7000 */
935 static int mips_fix_rm7000;
937 /* ...likewise -mfix-cn63xxp1 */
938 static bfd_boolean mips_fix_cn63xxp1;
940 /* We don't relax branches by default, since this causes us to expand
941 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
942 fail to compute the offset before expanding the macro to the most
943 efficient expansion. */
945 static int mips_relax_branch;
947 /* TRUE if checks are suppressed for invalid branches between ISA modes.
948 Needed for broken assembly produced by some GCC versions and some
949 sloppy code out there, where branches to data labels are present. */
950 static bfd_boolean mips_ignore_branch_isa;
952 /* The expansion of many macros depends on the type of symbol that
953 they refer to. For example, when generating position-dependent code,
954 a macro that refers to a symbol may have two different expansions,
955 one which uses GP-relative addresses and one which uses absolute
956 addresses. When generating SVR4-style PIC, a macro may have
957 different expansions for local and global symbols.
959 We handle these situations by generating both sequences and putting
960 them in variant frags. In position-dependent code, the first sequence
961 will be the GP-relative one and the second sequence will be the
962 absolute one. In SVR4 PIC, the first sequence will be for global
963 symbols and the second will be for local symbols.
965 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
966 SECOND are the lengths of the two sequences in bytes. These fields
967 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
968 the subtype has the following flags:
971 Set if generating PIC code.
974 Set if it has been decided that we should use the second
975 sequence instead of the first.
978 Set in the first variant frag if the macro's second implementation
979 is longer than its first. This refers to the macro as a whole,
980 not an individual relaxation.
983 Set in the first variant frag if the macro appeared in a .set nomacro
984 block and if one alternative requires a warning but the other does not.
987 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
990 RELAX_DELAY_SLOT_16BIT
991 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
994 RELAX_DELAY_SLOT_SIZE_FIRST
995 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
996 the macro is of the wrong size for the branch delay slot.
998 RELAX_DELAY_SLOT_SIZE_SECOND
999 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
1000 the macro is of the wrong size for the branch delay slot.
1002 The frag's "opcode" points to the first fixup for relaxable code.
1004 Relaxable macros are generated using a sequence such as:
1006 relax_start (SYMBOL);
1007 ... generate first expansion ...
1009 ... generate second expansion ...
1012 The code and fixups for the unwanted alternative are discarded
1013 by md_convert_frag. */
1014 #define RELAX_ENCODE(FIRST, SECOND, PIC) \
1015 (((FIRST) << 8) | (SECOND) | ((PIC) ? 0x10000 : 0))
1017 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1018 #define RELAX_SECOND(X) ((X) & 0xff)
1019 #define RELAX_PIC(X) (((X) & 0x10000) != 0)
1020 #define RELAX_USE_SECOND 0x20000
1021 #define RELAX_SECOND_LONGER 0x40000
1022 #define RELAX_NOMACRO 0x80000
1023 #define RELAX_DELAY_SLOT 0x100000
1024 #define RELAX_DELAY_SLOT_16BIT 0x200000
1025 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x400000
1026 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x800000
1028 /* Branch without likely bit. If label is out of range, we turn:
1030 beq reg1, reg2, label
1040 with the following opcode replacements:
1047 bltzal <-> bgezal (with jal label instead of j label)
1049 Even though keeping the delay slot instruction in the delay slot of
1050 the branch would be more efficient, it would be very tricky to do
1051 correctly, because we'd have to introduce a variable frag *after*
1052 the delay slot instruction, and expand that instead. Let's do it
1053 the easy way for now, even if the branch-not-taken case now costs
1054 one additional instruction. Out-of-range branches are not supposed
1055 to be common, anyway.
1057 Branch likely. If label is out of range, we turn:
1059 beql reg1, reg2, label
1060 delay slot (annulled if branch not taken)
1069 delay slot (executed only if branch taken)
1072 It would be possible to generate a shorter sequence by losing the
1073 likely bit, generating something like:
1078 delay slot (executed only if branch taken)
1090 bltzall -> bgezal (with jal label instead of j label)
1091 bgezall -> bltzal (ditto)
1094 but it's not clear that it would actually improve performance. */
1095 #define RELAX_BRANCH_ENCODE(at, pic, \
1096 uncond, likely, link, toofar) \
1097 ((relax_substateT) \
1100 | ((pic) ? 0x20 : 0) \
1101 | ((toofar) ? 0x40 : 0) \
1102 | ((link) ? 0x80 : 0) \
1103 | ((likely) ? 0x100 : 0) \
1104 | ((uncond) ? 0x200 : 0)))
1105 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1106 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x200) != 0)
1107 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x100) != 0)
1108 #define RELAX_BRANCH_LINK(i) (((i) & 0x80) != 0)
1109 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x40) != 0)
1110 #define RELAX_BRANCH_PIC(i) (((i) & 0x20) != 0)
1111 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1113 /* For mips16 code, we use an entirely different form of relaxation.
1114 mips16 supports two versions of most instructions which take
1115 immediate values: a small one which takes some small value, and a
1116 larger one which takes a 16 bit value. Since branches also follow
1117 this pattern, relaxing these values is required.
1119 We can assemble both mips16 and normal MIPS code in a single
1120 object. Therefore, we need to support this type of relaxation at
1121 the same time that we support the relaxation described above. We
1122 use the high bit of the subtype field to distinguish these cases.
1124 The information we store for this type of relaxation is the
1125 argument code found in the opcode file for this relocation, whether
1126 the user explicitly requested a small or extended form, and whether
1127 the relocation is in a jump or jal delay slot. That tells us the
1128 size of the value, and how it should be stored. We also store
1129 whether the fragment is considered to be extended or not. We also
1130 store whether this is known to be a branch to a different section,
1131 whether we have tried to relax this frag yet, and whether we have
1132 ever extended a PC relative fragment because of a shift count. */
1133 #define RELAX_MIPS16_ENCODE(type, e2, pic, sym32, nomacro, \
1138 | ((e2) ? 0x100 : 0) \
1139 | ((pic) ? 0x200 : 0) \
1140 | ((sym32) ? 0x400 : 0) \
1141 | ((nomacro) ? 0x800 : 0) \
1142 | ((small) ? 0x1000 : 0) \
1143 | ((ext) ? 0x2000 : 0) \
1144 | ((dslot) ? 0x4000 : 0) \
1145 | ((jal_dslot) ? 0x8000 : 0))
1147 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1148 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1149 #define RELAX_MIPS16_E2(i) (((i) & 0x100) != 0)
1150 #define RELAX_MIPS16_PIC(i) (((i) & 0x200) != 0)
1151 #define RELAX_MIPS16_SYM32(i) (((i) & 0x400) != 0)
1152 #define RELAX_MIPS16_NOMACRO(i) (((i) & 0x800) != 0)
1153 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x1000) != 0)
1154 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x2000) != 0)
1155 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x4000) != 0)
1156 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x8000) != 0)
1158 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x10000) != 0)
1159 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x10000)
1160 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) & ~0x10000)
1161 #define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x20000) != 0)
1162 #define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x20000)
1163 #define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x20000)
1164 #define RELAX_MIPS16_MACRO(i) (((i) & 0x40000) != 0)
1165 #define RELAX_MIPS16_MARK_MACRO(i) ((i) | 0x40000)
1166 #define RELAX_MIPS16_CLEAR_MACRO(i) ((i) & ~0x40000)
1168 /* For microMIPS code, we use relaxation similar to one we use for
1169 MIPS16 code. Some instructions that take immediate values support
1170 two encodings: a small one which takes some small value, and a
1171 larger one which takes a 16 bit value. As some branches also follow
1172 this pattern, relaxing these values is required.
1174 We can assemble both microMIPS and normal MIPS code in a single
1175 object. Therefore, we need to support this type of relaxation at
1176 the same time that we support the relaxation described above. We
1177 use one of the high bits of the subtype field to distinguish these
1180 The information we store for this type of relaxation is the argument
1181 code found in the opcode file for this relocation, the register
1182 selected as the assembler temporary, whether in the 32-bit
1183 instruction mode, whether the branch is unconditional, whether it is
1184 compact, whether there is no delay-slot instruction available to fill
1185 in, whether it stores the link address implicitly in $ra, whether
1186 relaxation of out-of-range 32-bit branches to a sequence of
1187 instructions is enabled, and whether the displacement of a branch is
1188 too large to fit as an immediate argument of a 16-bit and a 32-bit
1189 branch, respectively. */
1190 #define RELAX_MICROMIPS_ENCODE(type, at, insn32, pic, \
1191 uncond, compact, link, nods, \
1192 relax32, toofar16, toofar32) \
1195 | (((at) & 0x1f) << 8) \
1196 | ((insn32) ? 0x2000 : 0) \
1197 | ((pic) ? 0x4000 : 0) \
1198 | ((uncond) ? 0x8000 : 0) \
1199 | ((compact) ? 0x10000 : 0) \
1200 | ((link) ? 0x20000 : 0) \
1201 | ((nods) ? 0x40000 : 0) \
1202 | ((relax32) ? 0x80000 : 0) \
1203 | ((toofar16) ? 0x100000 : 0) \
1204 | ((toofar32) ? 0x200000 : 0))
1205 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1206 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1207 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1208 #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0)
1209 #define RELAX_MICROMIPS_PIC(i) (((i) & 0x4000) != 0)
1210 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x8000) != 0)
1211 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x10000) != 0)
1212 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x20000) != 0)
1213 #define RELAX_MICROMIPS_NODS(i) (((i) & 0x40000) != 0)
1214 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x80000) != 0)
1216 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x100000) != 0)
1217 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x100000)
1218 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x100000)
1219 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x200000) != 0)
1220 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x200000)
1221 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x200000)
1223 /* Sign-extend 16-bit value X. */
1224 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1226 /* Is the given value a sign-extended 32-bit value? */
1227 #define IS_SEXT_32BIT_NUM(x) \
1228 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1229 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1231 /* Is the given value a sign-extended 16-bit value? */
1232 #define IS_SEXT_16BIT_NUM(x) \
1233 (((x) &~ (offsetT) 0x7fff) == 0 \
1234 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1236 /* Is the given value a sign-extended 12-bit value? */
1237 #define IS_SEXT_12BIT_NUM(x) \
1238 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1240 /* Is the given value a sign-extended 9-bit value? */
1241 #define IS_SEXT_9BIT_NUM(x) \
1242 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1244 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1245 #define IS_ZEXT_32BIT_NUM(x) \
1246 (((x) &~ (offsetT) 0xffffffff) == 0 \
1247 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1249 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1251 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1252 (((STRUCT) >> (SHIFT)) & (MASK))
1254 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1255 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1257 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1258 : EXTRACT_BITS ((INSN).insn_opcode, \
1259 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1260 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1261 EXTRACT_BITS ((INSN).insn_opcode, \
1262 MIPS16OP_MASK_##FIELD, \
1263 MIPS16OP_SH_##FIELD)
1265 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1266 #define MIPS16_EXTEND (0xf000U << 16)
1268 /* Whether or not we are emitting a branch-likely macro. */
1269 static bfd_boolean emit_branch_likely_macro = FALSE;
1271 /* Global variables used when generating relaxable macros. See the
1272 comment above RELAX_ENCODE for more details about how relaxation
1275 /* 0 if we're not emitting a relaxable macro.
1276 1 if we're emitting the first of the two relaxation alternatives.
1277 2 if we're emitting the second alternative. */
1280 /* The first relaxable fixup in the current frag. (In other words,
1281 the first fixup that refers to relaxable code.) */
1284 /* sizes[0] says how many bytes of the first alternative are stored in
1285 the current frag. Likewise sizes[1] for the second alternative. */
1286 unsigned int sizes[2];
1288 /* The symbol on which the choice of sequence depends. */
1292 /* Global variables used to decide whether a macro needs a warning. */
1294 /* True if the macro is in a branch delay slot. */
1295 bfd_boolean delay_slot_p;
1297 /* Set to the length in bytes required if the macro is in a delay slot
1298 that requires a specific length of instruction, otherwise zero. */
1299 unsigned int delay_slot_length;
1301 /* For relaxable macros, sizes[0] is the length of the first alternative
1302 in bytes and sizes[1] is the length of the second alternative.
1303 For non-relaxable macros, both elements give the length of the
1305 unsigned int sizes[2];
1307 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1308 instruction of the first alternative in bytes and first_insn_sizes[1]
1309 is the length of the first instruction of the second alternative.
1310 For non-relaxable macros, both elements give the length of the first
1311 instruction in bytes.
1313 Set to zero if we haven't yet seen the first instruction. */
1314 unsigned int first_insn_sizes[2];
1316 /* For relaxable macros, insns[0] is the number of instructions for the
1317 first alternative and insns[1] is the number of instructions for the
1320 For non-relaxable macros, both elements give the number of
1321 instructions for the macro. */
1322 unsigned int insns[2];
1324 /* The first variant frag for this macro. */
1326 } mips_macro_warning;
1328 /* Prototypes for static functions. */
1330 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1332 static void append_insn
1333 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1334 bfd_boolean expansionp);
1335 static void mips_no_prev_insn (void);
1336 static void macro_build (expressionS *, const char *, const char *, ...);
1337 static void mips16_macro_build
1338 (expressionS *, const char *, const char *, va_list *);
1339 static void load_register (int, expressionS *, int);
1340 static void macro_start (void);
1341 static void macro_end (void);
1342 static void macro (struct mips_cl_insn *ip, char *str);
1343 static void mips16_macro (struct mips_cl_insn * ip);
1344 static void mips_ip (char *str, struct mips_cl_insn * ip);
1345 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1346 static unsigned long mips16_immed_extend (offsetT, unsigned int);
1347 static void mips16_immed
1348 (const char *, unsigned int, int, bfd_reloc_code_real_type, offsetT,
1349 unsigned int, unsigned long *);
1350 static size_t my_getSmallExpression
1351 (expressionS *, bfd_reloc_code_real_type *, char *);
1352 static void my_getExpression (expressionS *, char *);
1353 static void s_align (int);
1354 static void s_change_sec (int);
1355 static void s_change_section (int);
1356 static void s_cons (int);
1357 static void s_float_cons (int);
1358 static void s_mips_globl (int);
1359 static void s_option (int);
1360 static void s_mipsset (int);
1361 static void s_abicalls (int);
1362 static void s_cpload (int);
1363 static void s_cpsetup (int);
1364 static void s_cplocal (int);
1365 static void s_cprestore (int);
1366 static void s_cpreturn (int);
1367 static void s_dtprelword (int);
1368 static void s_dtpreldword (int);
1369 static void s_tprelword (int);
1370 static void s_tpreldword (int);
1371 static void s_gpvalue (int);
1372 static void s_gpword (int);
1373 static void s_gpdword (int);
1374 static void s_ehword (int);
1375 static void s_cpadd (int);
1376 static void s_insn (int);
1377 static void s_nan (int);
1378 static void s_module (int);
1379 static void s_mips_ent (int);
1380 static void s_mips_end (int);
1381 static void s_mips_frame (int);
1382 static void s_mips_mask (int reg_type);
1383 static void s_mips_stab (int);
1384 static void s_mips_weakext (int);
1385 static void s_mips_file (int);
1386 static void s_mips_loc (int);
1387 static bfd_boolean pic_need_relax (symbolS *);
1388 static int relaxed_branch_length (fragS *, asection *, int);
1389 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1390 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1391 static void file_mips_check_options (void);
1393 /* Table and functions used to map between CPU/ISA names, and
1394 ISA levels, and CPU numbers. */
1396 struct mips_cpu_info
1398 const char *name; /* CPU or ISA name. */
1399 int flags; /* MIPS_CPU_* flags. */
1400 int ase; /* Set of ASEs implemented by the CPU. */
1401 int isa; /* ISA level. */
1402 int cpu; /* CPU number (default CPU if ISA). */
1405 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1407 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1408 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1409 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1411 /* Command-line options. */
1412 const char *md_shortopts = "O::g::G:";
1416 OPTION_MARCH = OPTION_MD_BASE,
1448 OPTION_NO_SMARTMIPS,
1458 OPTION_NO_MICROMIPS,
1473 OPTION_M7000_HILO_FIX,
1474 OPTION_MNO_7000_HILO_FIX,
1478 OPTION_NO_FIX_RM7000,
1479 OPTION_FIX_LOONGSON2F_JUMP,
1480 OPTION_NO_FIX_LOONGSON2F_JUMP,
1481 OPTION_FIX_LOONGSON2F_NOP,
1482 OPTION_NO_FIX_LOONGSON2F_NOP,
1484 OPTION_NO_FIX_VR4120,
1486 OPTION_NO_FIX_VR4130,
1487 OPTION_FIX_CN63XXP1,
1488 OPTION_NO_FIX_CN63XXP1,
1495 OPTION_CONSTRUCT_FLOATS,
1496 OPTION_NO_CONSTRUCT_FLOATS,
1500 OPTION_RELAX_BRANCH,
1501 OPTION_NO_RELAX_BRANCH,
1502 OPTION_IGNORE_BRANCH_ISA,
1503 OPTION_NO_IGNORE_BRANCH_ISA,
1512 OPTION_SINGLE_FLOAT,
1513 OPTION_DOUBLE_FLOAT,
1526 OPTION_MVXWORKS_PIC,
1529 OPTION_NO_ODD_SPREG,
1532 OPTION_LOONGSON_MMI,
1533 OPTION_NO_LOONGSON_MMI,
1534 OPTION_LOONGSON_CAM,
1535 OPTION_NO_LOONGSON_CAM,
1536 OPTION_LOONGSON_EXT,
1537 OPTION_NO_LOONGSON_EXT,
1538 OPTION_LOONGSON_EXT2,
1539 OPTION_NO_LOONGSON_EXT2,
1543 struct option md_longopts[] =
1545 /* Options which specify architecture. */
1546 {"march", required_argument, NULL, OPTION_MARCH},
1547 {"mtune", required_argument, NULL, OPTION_MTUNE},
1548 {"mips0", no_argument, NULL, OPTION_MIPS1},
1549 {"mips1", no_argument, NULL, OPTION_MIPS1},
1550 {"mips2", no_argument, NULL, OPTION_MIPS2},
1551 {"mips3", no_argument, NULL, OPTION_MIPS3},
1552 {"mips4", no_argument, NULL, OPTION_MIPS4},
1553 {"mips5", no_argument, NULL, OPTION_MIPS5},
1554 {"mips32", no_argument, NULL, OPTION_MIPS32},
1555 {"mips64", no_argument, NULL, OPTION_MIPS64},
1556 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
1557 {"mips32r3", no_argument, NULL, OPTION_MIPS32R3},
1558 {"mips32r5", no_argument, NULL, OPTION_MIPS32R5},
1559 {"mips32r6", no_argument, NULL, OPTION_MIPS32R6},
1560 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
1561 {"mips64r3", no_argument, NULL, OPTION_MIPS64R3},
1562 {"mips64r5", no_argument, NULL, OPTION_MIPS64R5},
1563 {"mips64r6", no_argument, NULL, OPTION_MIPS64R6},
1565 /* Options which specify Application Specific Extensions (ASEs). */
1566 {"mips16", no_argument, NULL, OPTION_MIPS16},
1567 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
1568 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
1569 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
1570 {"mdmx", no_argument, NULL, OPTION_MDMX},
1571 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
1572 {"mdsp", no_argument, NULL, OPTION_DSP},
1573 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
1574 {"mmt", no_argument, NULL, OPTION_MT},
1575 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
1576 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
1577 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
1578 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
1579 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
1580 {"mdspr3", no_argument, NULL, OPTION_DSPR3},
1581 {"mno-dspr3", no_argument, NULL, OPTION_NO_DSPR3},
1582 {"meva", no_argument, NULL, OPTION_EVA},
1583 {"mno-eva", no_argument, NULL, OPTION_NO_EVA},
1584 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
1585 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
1586 {"mmcu", no_argument, NULL, OPTION_MCU},
1587 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
1588 {"mvirt", no_argument, NULL, OPTION_VIRT},
1589 {"mno-virt", no_argument, NULL, OPTION_NO_VIRT},
1590 {"mmsa", no_argument, NULL, OPTION_MSA},
1591 {"mno-msa", no_argument, NULL, OPTION_NO_MSA},
1592 {"mxpa", no_argument, NULL, OPTION_XPA},
1593 {"mno-xpa", no_argument, NULL, OPTION_NO_XPA},
1594 {"mmips16e2", no_argument, NULL, OPTION_MIPS16E2},
1595 {"mno-mips16e2", no_argument, NULL, OPTION_NO_MIPS16E2},
1596 {"mcrc", no_argument, NULL, OPTION_CRC},
1597 {"mno-crc", no_argument, NULL, OPTION_NO_CRC},
1598 {"mginv", no_argument, NULL, OPTION_GINV},
1599 {"mno-ginv", no_argument, NULL, OPTION_NO_GINV},
1600 {"mloongson-mmi", no_argument, NULL, OPTION_LOONGSON_MMI},
1601 {"mno-loongson-mmi", no_argument, NULL, OPTION_NO_LOONGSON_MMI},
1602 {"mloongson-cam", no_argument, NULL, OPTION_LOONGSON_CAM},
1603 {"mno-loongson-cam", no_argument, NULL, OPTION_NO_LOONGSON_CAM},
1604 {"mloongson-ext", no_argument, NULL, OPTION_LOONGSON_EXT},
1605 {"mno-loongson-ext", no_argument, NULL, OPTION_NO_LOONGSON_EXT},
1606 {"mloongson-ext2", no_argument, NULL, OPTION_LOONGSON_EXT2},
1607 {"mno-loongson-ext2", no_argument, NULL, OPTION_NO_LOONGSON_EXT2},
1609 /* Old-style architecture options. Don't add more of these. */
1610 {"m4650", no_argument, NULL, OPTION_M4650},
1611 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
1612 {"m4010", no_argument, NULL, OPTION_M4010},
1613 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
1614 {"m4100", no_argument, NULL, OPTION_M4100},
1615 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
1616 {"m3900", no_argument, NULL, OPTION_M3900},
1617 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
1619 /* Options which enable bug fixes. */
1620 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
1621 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1622 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1623 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
1624 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
1625 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
1626 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
1627 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
1628 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
1629 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
1630 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
1631 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
1632 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
1633 {"mfix-rm7000", no_argument, NULL, OPTION_FIX_RM7000},
1634 {"mno-fix-rm7000", no_argument, NULL, OPTION_NO_FIX_RM7000},
1635 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
1636 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
1638 /* Miscellaneous options. */
1639 {"trap", no_argument, NULL, OPTION_TRAP},
1640 {"no-break", no_argument, NULL, OPTION_TRAP},
1641 {"break", no_argument, NULL, OPTION_BREAK},
1642 {"no-trap", no_argument, NULL, OPTION_BREAK},
1643 {"EB", no_argument, NULL, OPTION_EB},
1644 {"EL", no_argument, NULL, OPTION_EL},
1645 {"mfp32", no_argument, NULL, OPTION_FP32},
1646 {"mgp32", no_argument, NULL, OPTION_GP32},
1647 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
1648 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
1649 {"mfp64", no_argument, NULL, OPTION_FP64},
1650 {"mfpxx", no_argument, NULL, OPTION_FPXX},
1651 {"mgp64", no_argument, NULL, OPTION_GP64},
1652 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
1653 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
1654 {"mignore-branch-isa", no_argument, NULL, OPTION_IGNORE_BRANCH_ISA},
1655 {"mno-ignore-branch-isa", no_argument, NULL, OPTION_NO_IGNORE_BRANCH_ISA},
1656 {"minsn32", no_argument, NULL, OPTION_INSN32},
1657 {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32},
1658 {"mshared", no_argument, NULL, OPTION_MSHARED},
1659 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
1660 {"msym32", no_argument, NULL, OPTION_MSYM32},
1661 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
1662 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
1663 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
1664 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
1665 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
1666 {"modd-spreg", no_argument, NULL, OPTION_ODD_SPREG},
1667 {"mno-odd-spreg", no_argument, NULL, OPTION_NO_ODD_SPREG},
1669 /* Strictly speaking this next option is ELF specific,
1670 but we allow it for other ports as well in order to
1671 make testing easier. */
1672 {"32", no_argument, NULL, OPTION_32},
1674 /* ELF-specific options. */
1675 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
1676 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
1677 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
1678 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
1679 {"xgot", no_argument, NULL, OPTION_XGOT},
1680 {"mabi", required_argument, NULL, OPTION_MABI},
1681 {"n32", no_argument, NULL, OPTION_N32},
1682 {"64", no_argument, NULL, OPTION_64},
1683 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
1684 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
1685 {"mpdr", no_argument, NULL, OPTION_PDR},
1686 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
1687 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
1688 {"mnan", required_argument, NULL, OPTION_NAN},
1690 {NULL, no_argument, NULL, 0}
1692 size_t md_longopts_size = sizeof (md_longopts);
1694 /* Information about either an Application Specific Extension or an
1695 optional architecture feature that, for simplicity, we treat in the
1696 same way as an ASE. */
1699 /* The name of the ASE, used in both the command-line and .set options. */
1702 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1703 and 64-bit architectures, the flags here refer to the subset that
1704 is available on both. */
1707 /* The ASE_* flag used for instructions that are available on 64-bit
1708 architectures but that are not included in FLAGS. */
1709 unsigned int flags64;
1711 /* The command-line options that turn the ASE on and off. */
1715 /* The minimum required architecture revisions for MIPS32, MIPS64,
1716 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1719 int micromips32_rev;
1720 int micromips64_rev;
1722 /* The architecture where the ASE was removed or -1 if the extension has not
1727 /* A table of all supported ASEs. */
1728 static const struct mips_ase mips_ases[] = {
1729 { "dsp", ASE_DSP, ASE_DSP64,
1730 OPTION_DSP, OPTION_NO_DSP,
1734 { "dspr2", ASE_DSP | ASE_DSPR2, 0,
1735 OPTION_DSPR2, OPTION_NO_DSPR2,
1739 { "dspr3", ASE_DSP | ASE_DSPR2 | ASE_DSPR3, 0,
1740 OPTION_DSPR3, OPTION_NO_DSPR3,
1744 { "eva", ASE_EVA, 0,
1745 OPTION_EVA, OPTION_NO_EVA,
1749 { "mcu", ASE_MCU, 0,
1750 OPTION_MCU, OPTION_NO_MCU,
1754 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1755 { "mdmx", ASE_MDMX, 0,
1756 OPTION_MDMX, OPTION_NO_MDMX,
1760 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1761 { "mips3d", ASE_MIPS3D, 0,
1762 OPTION_MIPS3D, OPTION_NO_MIPS3D,
1767 OPTION_MT, OPTION_NO_MT,
1771 { "smartmips", ASE_SMARTMIPS, 0,
1772 OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS,
1776 { "virt", ASE_VIRT, ASE_VIRT64,
1777 OPTION_VIRT, OPTION_NO_VIRT,
1781 { "msa", ASE_MSA, ASE_MSA64,
1782 OPTION_MSA, OPTION_NO_MSA,
1786 { "xpa", ASE_XPA, 0,
1787 OPTION_XPA, OPTION_NO_XPA,
1791 { "mips16e2", ASE_MIPS16E2, 0,
1792 OPTION_MIPS16E2, OPTION_NO_MIPS16E2,
1796 { "crc", ASE_CRC, ASE_CRC64,
1797 OPTION_CRC, OPTION_NO_CRC,
1801 { "ginv", ASE_GINV, 0,
1802 OPTION_GINV, OPTION_NO_GINV,
1806 { "loongson-mmi", ASE_LOONGSON_MMI, 0,
1807 OPTION_LOONGSON_MMI, OPTION_NO_LOONGSON_MMI,
1811 { "loongson-cam", ASE_LOONGSON_CAM, 0,
1812 OPTION_LOONGSON_CAM, OPTION_NO_LOONGSON_CAM,
1816 { "loongson-ext", ASE_LOONGSON_EXT, 0,
1817 OPTION_LOONGSON_EXT, OPTION_NO_LOONGSON_EXT,
1821 { "loongson-ext2", ASE_LOONGSON_EXT | ASE_LOONGSON_EXT2, 0,
1822 OPTION_LOONGSON_EXT2, OPTION_NO_LOONGSON_EXT2,
1827 /* The set of ASEs that require -mfp64. */
1828 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
1830 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1831 static const unsigned int mips_ase_groups[] = {
1832 ASE_DSP | ASE_DSPR2 | ASE_DSPR3,
1833 ASE_LOONGSON_EXT | ASE_LOONGSON_EXT2
1838 The following pseudo-ops from the Kane and Heinrich MIPS book
1839 should be defined here, but are currently unsupported: .alias,
1840 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1842 The following pseudo-ops from the Kane and Heinrich MIPS book are
1843 specific to the type of debugging information being generated, and
1844 should be defined by the object format: .aent, .begin, .bend,
1845 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1848 The following pseudo-ops from the Kane and Heinrich MIPS book are
1849 not MIPS CPU specific, but are also not specific to the object file
1850 format. This file is probably the best place to define them, but
1851 they are not currently supported: .asm0, .endr, .lab, .struct. */
1853 static const pseudo_typeS mips_pseudo_table[] =
1855 /* MIPS specific pseudo-ops. */
1856 {"option", s_option, 0},
1857 {"set", s_mipsset, 0},
1858 {"rdata", s_change_sec, 'r'},
1859 {"sdata", s_change_sec, 's'},
1860 {"livereg", s_ignore, 0},
1861 {"abicalls", s_abicalls, 0},
1862 {"cpload", s_cpload, 0},
1863 {"cpsetup", s_cpsetup, 0},
1864 {"cplocal", s_cplocal, 0},
1865 {"cprestore", s_cprestore, 0},
1866 {"cpreturn", s_cpreturn, 0},
1867 {"dtprelword", s_dtprelword, 0},
1868 {"dtpreldword", s_dtpreldword, 0},
1869 {"tprelword", s_tprelword, 0},
1870 {"tpreldword", s_tpreldword, 0},
1871 {"gpvalue", s_gpvalue, 0},
1872 {"gpword", s_gpword, 0},
1873 {"gpdword", s_gpdword, 0},
1874 {"ehword", s_ehword, 0},
1875 {"cpadd", s_cpadd, 0},
1876 {"insn", s_insn, 0},
1878 {"module", s_module, 0},
1880 /* Relatively generic pseudo-ops that happen to be used on MIPS
1882 {"asciiz", stringer, 8 + 1},
1883 {"bss", s_change_sec, 'b'},
1885 {"half", s_cons, 1},
1886 {"dword", s_cons, 3},
1887 {"weakext", s_mips_weakext, 0},
1888 {"origin", s_org, 0},
1889 {"repeat", s_rept, 0},
1891 /* For MIPS this is non-standard, but we define it for consistency. */
1892 {"sbss", s_change_sec, 'B'},
1894 /* These pseudo-ops are defined in read.c, but must be overridden
1895 here for one reason or another. */
1896 {"align", s_align, 0},
1897 {"byte", s_cons, 0},
1898 {"data", s_change_sec, 'd'},
1899 {"double", s_float_cons, 'd'},
1900 {"float", s_float_cons, 'f'},
1901 {"globl", s_mips_globl, 0},
1902 {"global", s_mips_globl, 0},
1903 {"hword", s_cons, 1},
1905 {"long", s_cons, 2},
1906 {"octa", s_cons, 4},
1907 {"quad", s_cons, 3},
1908 {"section", s_change_section, 0},
1909 {"short", s_cons, 1},
1910 {"single", s_float_cons, 'f'},
1911 {"stabd", s_mips_stab, 'd'},
1912 {"stabn", s_mips_stab, 'n'},
1913 {"stabs", s_mips_stab, 's'},
1914 {"text", s_change_sec, 't'},
1915 {"word", s_cons, 2},
1917 { "extern", ecoff_directive_extern, 0},
1922 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1924 /* These pseudo-ops should be defined by the object file format.
1925 However, a.out doesn't support them, so we have versions here. */
1926 {"aent", s_mips_ent, 1},
1927 {"bgnb", s_ignore, 0},
1928 {"end", s_mips_end, 0},
1929 {"endb", s_ignore, 0},
1930 {"ent", s_mips_ent, 0},
1931 {"file", s_mips_file, 0},
1932 {"fmask", s_mips_mask, 'F'},
1933 {"frame", s_mips_frame, 0},
1934 {"loc", s_mips_loc, 0},
1935 {"mask", s_mips_mask, 'R'},
1936 {"verstamp", s_ignore, 0},
1940 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1941 purpose of the `.dc.a' internal pseudo-op. */
1944 mips_address_bytes (void)
1946 file_mips_check_options ();
1947 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1950 extern void pop_insert (const pseudo_typeS *);
1953 mips_pop_insert (void)
1955 pop_insert (mips_pseudo_table);
1956 if (! ECOFF_DEBUGGING)
1957 pop_insert (mips_nonecoff_pseudo_table);
1960 /* Symbols labelling the current insn. */
1962 struct insn_label_list
1964 struct insn_label_list *next;
1968 static struct insn_label_list *free_insn_labels;
1969 #define label_list tc_segment_info_data.labels
1971 static void mips_clear_insn_labels (void);
1972 static void mips_mark_labels (void);
1973 static void mips_compressed_mark_labels (void);
1976 mips_clear_insn_labels (void)
1978 struct insn_label_list **pl;
1979 segment_info_type *si;
1983 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1986 si = seg_info (now_seg);
1987 *pl = si->label_list;
1988 si->label_list = NULL;
1992 /* Mark instruction labels in MIPS16/microMIPS mode. */
1995 mips_mark_labels (void)
1997 if (HAVE_CODE_COMPRESSION)
1998 mips_compressed_mark_labels ();
2001 static char *expr_end;
2003 /* An expression in a macro instruction. This is set by mips_ip and
2004 mips16_ip and when populated is always an O_constant. */
2006 static expressionS imm_expr;
2008 /* The relocatable field in an instruction and the relocs associated
2009 with it. These variables are used for instructions like LUI and
2010 JAL as well as true offsets. They are also used for address
2011 operands in macros. */
2013 static expressionS offset_expr;
2014 static bfd_reloc_code_real_type offset_reloc[3]
2015 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2017 /* This is set to the resulting size of the instruction to be produced
2018 by mips16_ip if an explicit extension is used or by mips_ip if an
2019 explicit size is supplied. */
2021 static unsigned int forced_insn_length;
2023 /* True if we are assembling an instruction. All dot symbols defined during
2024 this time should be treated as code labels. */
2026 static bfd_boolean mips_assembling_insn;
2028 /* The pdr segment for per procedure frame/regmask info. Not used for
2031 static segT pdr_seg;
2033 /* The default target format to use. */
2035 #if defined (TE_FreeBSD)
2036 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
2037 #elif defined (TE_TMIPS)
2038 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
2040 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
2044 mips_target_format (void)
2046 switch (OUTPUT_FLAVOR)
2048 case bfd_target_elf_flavour:
2050 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
2051 return (target_big_endian
2052 ? "elf32-bigmips-vxworks"
2053 : "elf32-littlemips-vxworks");
2055 return (target_big_endian
2056 ? (HAVE_64BIT_OBJECTS
2057 ? ELF_TARGET ("elf64-", "big")
2059 ? ELF_TARGET ("elf32-n", "big")
2060 : ELF_TARGET ("elf32-", "big")))
2061 : (HAVE_64BIT_OBJECTS
2062 ? ELF_TARGET ("elf64-", "little")
2064 ? ELF_TARGET ("elf32-n", "little")
2065 : ELF_TARGET ("elf32-", "little"))));
2072 /* Return the ISA revision that is currently in use, or 0 if we are
2073 generating code for MIPS V or below. */
2078 if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2)
2081 if (mips_opts.isa == ISA_MIPS32R3 || mips_opts.isa == ISA_MIPS64R3)
2084 if (mips_opts.isa == ISA_MIPS32R5 || mips_opts.isa == ISA_MIPS64R5)
2087 if (mips_opts.isa == ISA_MIPS32R6 || mips_opts.isa == ISA_MIPS64R6)
2090 /* microMIPS implies revision 2 or above. */
2091 if (mips_opts.micromips)
2094 if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64)
2100 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
2103 mips_ase_mask (unsigned int flags)
2107 for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++)
2108 if (flags & mips_ase_groups[i])
2109 flags |= mips_ase_groups[i];
2113 /* Check whether the current ISA supports ASE. Issue a warning if
2117 mips_check_isa_supports_ase (const struct mips_ase *ase)
2121 static unsigned int warned_isa;
2122 static unsigned int warned_fp32;
2124 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
2125 min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev;
2127 min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev;
2128 if ((min_rev < 0 || mips_isa_rev () < min_rev)
2129 && (warned_isa & ase->flags) != ase->flags)
2131 warned_isa |= ase->flags;
2132 base = mips_opts.micromips ? "microMIPS" : "MIPS";
2133 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
2135 as_warn (_("the %d-bit %s architecture does not support the"
2136 " `%s' extension"), size, base, ase->name);
2138 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
2139 ase->name, base, size, min_rev);
2141 else if ((ase->rem_rev > 0 && mips_isa_rev () >= ase->rem_rev)
2142 && (warned_isa & ase->flags) != ase->flags)
2144 warned_isa |= ase->flags;
2145 base = mips_opts.micromips ? "microMIPS" : "MIPS";
2146 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
2147 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2148 ase->name, base, size, ase->rem_rev);
2151 if ((ase->flags & FP64_ASES)
2152 && mips_opts.fp != 64
2153 && (warned_fp32 & ase->flags) != ase->flags)
2155 warned_fp32 |= ase->flags;
2156 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase->name);
2160 /* Check all enabled ASEs to see whether they are supported by the
2161 chosen architecture. */
2164 mips_check_isa_supports_ases (void)
2166 unsigned int i, mask;
2168 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2170 mask = mips_ase_mask (mips_ases[i].flags);
2171 if ((mips_opts.ase & mask) == mips_ases[i].flags)
2172 mips_check_isa_supports_ase (&mips_ases[i]);
2176 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2177 that were affected. */
2180 mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts,
2181 bfd_boolean enabled_p)
2185 mask = mips_ase_mask (ase->flags);
2188 /* Clear combination ASE flags, which need to be recalculated based on
2189 updated regular ASE settings. */
2190 opts->ase &= ~(ASE_MIPS16E2_MT | ASE_XPA_VIRT);
2193 opts->ase |= ase->flags;
2195 /* The Virtualization ASE has eXtended Physical Addressing (XPA)
2196 instructions which are only valid when both ASEs are enabled.
2197 This sets the ASE_XPA_VIRT flag when both ASEs are present. */
2198 if ((opts->ase & (ASE_XPA | ASE_VIRT)) == (ASE_XPA | ASE_VIRT))
2200 opts->ase |= ASE_XPA_VIRT;
2201 mask |= ASE_XPA_VIRT;
2203 if ((opts->ase & (ASE_MIPS16E2 | ASE_MT)) == (ASE_MIPS16E2 | ASE_MT))
2205 opts->ase |= ASE_MIPS16E2_MT;
2206 mask |= ASE_MIPS16E2_MT;
2212 /* Return the ASE called NAME, or null if none. */
2214 static const struct mips_ase *
2215 mips_lookup_ase (const char *name)
2219 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2220 if (strcmp (name, mips_ases[i].name) == 0)
2221 return &mips_ases[i];
2225 /* Return the length of a microMIPS instruction in bytes. If bits of
2226 the mask beyond the low 16 are 0, then it is a 16-bit instruction,
2227 otherwise it is a 32-bit instruction. */
2229 static inline unsigned int
2230 micromips_insn_length (const struct mips_opcode *mo)
2232 return mips_opcode_32bit_p (mo) ? 4 : 2;
2235 /* Return the length of MIPS16 instruction OPCODE. */
2237 static inline unsigned int
2238 mips16_opcode_length (unsigned long opcode)
2240 return (opcode >> 16) == 0 ? 2 : 4;
2243 /* Return the length of instruction INSN. */
2245 static inline unsigned int
2246 insn_length (const struct mips_cl_insn *insn)
2248 if (mips_opts.micromips)
2249 return micromips_insn_length (insn->insn_mo);
2250 else if (mips_opts.mips16)
2251 return mips16_opcode_length (insn->insn_opcode);
2256 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2259 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
2264 insn->insn_opcode = mo->match;
2267 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2268 insn->fixp[i] = NULL;
2269 insn->fixed_p = (mips_opts.noreorder > 0);
2270 insn->noreorder_p = (mips_opts.noreorder > 0);
2271 insn->mips16_absolute_jump_p = 0;
2272 insn->complete_p = 0;
2273 insn->cleared_p = 0;
2276 /* Get a list of all the operands in INSN. */
2278 static const struct mips_operand_array *
2279 insn_operands (const struct mips_cl_insn *insn)
2281 if (insn->insn_mo >= &mips_opcodes[0]
2282 && insn->insn_mo < &mips_opcodes[NUMOPCODES])
2283 return &mips_operands[insn->insn_mo - &mips_opcodes[0]];
2285 if (insn->insn_mo >= &mips16_opcodes[0]
2286 && insn->insn_mo < &mips16_opcodes[bfd_mips16_num_opcodes])
2287 return &mips16_operands[insn->insn_mo - &mips16_opcodes[0]];
2289 if (insn->insn_mo >= µmips_opcodes[0]
2290 && insn->insn_mo < µmips_opcodes[bfd_micromips_num_opcodes])
2291 return µmips_operands[insn->insn_mo - µmips_opcodes[0]];
2296 /* Get a description of operand OPNO of INSN. */
2298 static const struct mips_operand *
2299 insn_opno (const struct mips_cl_insn *insn, unsigned opno)
2301 const struct mips_operand_array *operands;
2303 operands = insn_operands (insn);
2304 if (opno >= MAX_OPERANDS || !operands->operand[opno])
2306 return operands->operand[opno];
2309 /* Install UVAL as the value of OPERAND in INSN. */
2312 insn_insert_operand (struct mips_cl_insn *insn,
2313 const struct mips_operand *operand, unsigned int uval)
2315 if (mips_opts.mips16
2316 && operand->type == OP_INT && operand->lsb == 0
2317 && mips_opcode_32bit_p (insn->insn_mo))
2318 insn->insn_opcode |= mips16_immed_extend (uval, operand->size);
2320 insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval);
2323 /* Extract the value of OPERAND from INSN. */
2325 static inline unsigned
2326 insn_extract_operand (const struct mips_cl_insn *insn,
2327 const struct mips_operand *operand)
2329 return mips_extract_operand (operand, insn->insn_opcode);
2332 /* Record the current MIPS16/microMIPS mode in now_seg. */
2335 mips_record_compressed_mode (void)
2337 segment_info_type *si;
2339 si = seg_info (now_seg);
2340 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
2341 si->tc_segment_info_data.mips16 = mips_opts.mips16;
2342 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
2343 si->tc_segment_info_data.micromips = mips_opts.micromips;
2346 /* Read a standard MIPS instruction from BUF. */
2348 static unsigned long
2349 read_insn (char *buf)
2351 if (target_big_endian)
2352 return bfd_getb32 ((bfd_byte *) buf);
2354 return bfd_getl32 ((bfd_byte *) buf);
2357 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2361 write_insn (char *buf, unsigned int insn)
2363 md_number_to_chars (buf, insn, 4);
2367 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2368 has length LENGTH. */
2370 static unsigned long
2371 read_compressed_insn (char *buf, unsigned int length)
2377 for (i = 0; i < length; i += 2)
2380 if (target_big_endian)
2381 insn |= bfd_getb16 ((char *) buf);
2383 insn |= bfd_getl16 ((char *) buf);
2389 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2390 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2393 write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
2397 for (i = 0; i < length; i += 2)
2398 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
2399 return buf + length;
2402 /* Install INSN at the location specified by its "frag" and "where" fields. */
2405 install_insn (const struct mips_cl_insn *insn)
2407 char *f = insn->frag->fr_literal + insn->where;
2408 if (HAVE_CODE_COMPRESSION)
2409 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
2411 write_insn (f, insn->insn_opcode);
2412 mips_record_compressed_mode ();
2415 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2416 and install the opcode in the new location. */
2419 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
2424 insn->where = where;
2425 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2426 if (insn->fixp[i] != NULL)
2428 insn->fixp[i]->fx_frag = frag;
2429 insn->fixp[i]->fx_where = where;
2431 install_insn (insn);
2434 /* Add INSN to the end of the output. */
2437 add_fixed_insn (struct mips_cl_insn *insn)
2439 char *f = frag_more (insn_length (insn));
2440 move_insn (insn, frag_now, f - frag_now->fr_literal);
2443 /* Start a variant frag and move INSN to the start of the variant part,
2444 marking it as fixed. The other arguments are as for frag_var. */
2447 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
2448 relax_substateT subtype, symbolS *symbol, offsetT offset)
2450 frag_grow (max_chars);
2451 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
2453 frag_var (rs_machine_dependent, max_chars, var,
2454 subtype, symbol, offset, NULL);
2457 /* Insert N copies of INSN into the history buffer, starting at
2458 position FIRST. Neither FIRST nor N need to be clipped. */
2461 insert_into_history (unsigned int first, unsigned int n,
2462 const struct mips_cl_insn *insn)
2464 if (mips_relax.sequence != 2)
2468 for (i = ARRAY_SIZE (history); i-- > first;)
2470 history[i] = history[i - n];
2476 /* Clear the error in insn_error. */
2479 clear_insn_error (void)
2481 memset (&insn_error, 0, sizeof (insn_error));
2484 /* Possibly record error message MSG for the current instruction.
2485 If the error is about a particular argument, ARGNUM is the 1-based
2486 number of that argument, otherwise it is 0. FORMAT is the format
2487 of MSG. Return true if MSG was used, false if the current message
2491 set_insn_error_format (int argnum, enum mips_insn_error_format format,
2496 /* Give priority to errors against specific arguments, and to
2497 the first whole-instruction message. */
2503 /* Keep insn_error if it is against a later argument. */
2504 if (argnum < insn_error.min_argnum)
2507 /* If both errors are against the same argument but are different,
2508 give up on reporting a specific error for this argument.
2509 See the comment about mips_insn_error for details. */
2510 if (argnum == insn_error.min_argnum
2512 && strcmp (insn_error.msg, msg) != 0)
2515 insn_error.min_argnum += 1;
2519 insn_error.min_argnum = argnum;
2520 insn_error.format = format;
2521 insn_error.msg = msg;
2525 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2526 as for set_insn_error_format. */
2529 set_insn_error (int argnum, const char *msg)
2531 set_insn_error_format (argnum, ERR_FMT_PLAIN, msg);
2534 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2535 as for set_insn_error_format. */
2538 set_insn_error_i (int argnum, const char *msg, int i)
2540 if (set_insn_error_format (argnum, ERR_FMT_I, msg))
2544 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2545 are as for set_insn_error_format. */
2548 set_insn_error_ss (int argnum, const char *msg, const char *s1, const char *s2)
2550 if (set_insn_error_format (argnum, ERR_FMT_SS, msg))
2552 insn_error.u.ss[0] = s1;
2553 insn_error.u.ss[1] = s2;
2557 /* Report the error in insn_error, which is against assembly code STR. */
2560 report_insn_error (const char *str)
2562 const char *msg = concat (insn_error.msg, " `%s'", NULL);
2564 switch (insn_error.format)
2571 as_bad (msg, insn_error.u.i, str);
2575 as_bad (msg, insn_error.u.ss[0], insn_error.u.ss[1], str);
2579 free ((char *) msg);
2582 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2583 the idea is to make it obvious at a glance that each errata is
2587 init_vr4120_conflicts (void)
2589 #define CONFLICT(FIRST, SECOND) \
2590 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2592 /* Errata 21 - [D]DIV[U] after [D]MACC */
2593 CONFLICT (MACC, DIV);
2594 CONFLICT (DMACC, DIV);
2596 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2597 CONFLICT (DMULT, DMULT);
2598 CONFLICT (DMULT, DMACC);
2599 CONFLICT (DMACC, DMULT);
2600 CONFLICT (DMACC, DMACC);
2602 /* Errata 24 - MT{LO,HI} after [D]MACC */
2603 CONFLICT (MACC, MTHILO);
2604 CONFLICT (DMACC, MTHILO);
2606 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2607 instruction is executed immediately after a MACC or DMACC
2608 instruction, the result of [either instruction] is incorrect." */
2609 CONFLICT (MACC, MULT);
2610 CONFLICT (MACC, DMULT);
2611 CONFLICT (DMACC, MULT);
2612 CONFLICT (DMACC, DMULT);
2614 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2615 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2616 DDIV or DDIVU instruction, the result of the MACC or
2617 DMACC instruction is incorrect.". */
2618 CONFLICT (DMULT, MACC);
2619 CONFLICT (DMULT, DMACC);
2620 CONFLICT (DIV, MACC);
2621 CONFLICT (DIV, DMACC);
2631 #define RNUM_MASK 0x00000ff
2632 #define RTYPE_MASK 0x0ffff00
2633 #define RTYPE_NUM 0x0000100
2634 #define RTYPE_FPU 0x0000200
2635 #define RTYPE_FCC 0x0000400
2636 #define RTYPE_VEC 0x0000800
2637 #define RTYPE_GP 0x0001000
2638 #define RTYPE_CP0 0x0002000
2639 #define RTYPE_PC 0x0004000
2640 #define RTYPE_ACC 0x0008000
2641 #define RTYPE_CCC 0x0010000
2642 #define RTYPE_VI 0x0020000
2643 #define RTYPE_VF 0x0040000
2644 #define RTYPE_R5900_I 0x0080000
2645 #define RTYPE_R5900_Q 0x0100000
2646 #define RTYPE_R5900_R 0x0200000
2647 #define RTYPE_R5900_ACC 0x0400000
2648 #define RTYPE_MSA 0x0800000
2649 #define RWARN 0x8000000
2651 #define GENERIC_REGISTER_NUMBERS \
2652 {"$0", RTYPE_NUM | 0}, \
2653 {"$1", RTYPE_NUM | 1}, \
2654 {"$2", RTYPE_NUM | 2}, \
2655 {"$3", RTYPE_NUM | 3}, \
2656 {"$4", RTYPE_NUM | 4}, \
2657 {"$5", RTYPE_NUM | 5}, \
2658 {"$6", RTYPE_NUM | 6}, \
2659 {"$7", RTYPE_NUM | 7}, \
2660 {"$8", RTYPE_NUM | 8}, \
2661 {"$9", RTYPE_NUM | 9}, \
2662 {"$10", RTYPE_NUM | 10}, \
2663 {"$11", RTYPE_NUM | 11}, \
2664 {"$12", RTYPE_NUM | 12}, \
2665 {"$13", RTYPE_NUM | 13}, \
2666 {"$14", RTYPE_NUM | 14}, \
2667 {"$15", RTYPE_NUM | 15}, \
2668 {"$16", RTYPE_NUM | 16}, \
2669 {"$17", RTYPE_NUM | 17}, \
2670 {"$18", RTYPE_NUM | 18}, \
2671 {"$19", RTYPE_NUM | 19}, \
2672 {"$20", RTYPE_NUM | 20}, \
2673 {"$21", RTYPE_NUM | 21}, \
2674 {"$22", RTYPE_NUM | 22}, \
2675 {"$23", RTYPE_NUM | 23}, \
2676 {"$24", RTYPE_NUM | 24}, \
2677 {"$25", RTYPE_NUM | 25}, \
2678 {"$26", RTYPE_NUM | 26}, \
2679 {"$27", RTYPE_NUM | 27}, \
2680 {"$28", RTYPE_NUM | 28}, \
2681 {"$29", RTYPE_NUM | 29}, \
2682 {"$30", RTYPE_NUM | 30}, \
2683 {"$31", RTYPE_NUM | 31}
2685 #define FPU_REGISTER_NAMES \
2686 {"$f0", RTYPE_FPU | 0}, \
2687 {"$f1", RTYPE_FPU | 1}, \
2688 {"$f2", RTYPE_FPU | 2}, \
2689 {"$f3", RTYPE_FPU | 3}, \
2690 {"$f4", RTYPE_FPU | 4}, \
2691 {"$f5", RTYPE_FPU | 5}, \
2692 {"$f6", RTYPE_FPU | 6}, \
2693 {"$f7", RTYPE_FPU | 7}, \
2694 {"$f8", RTYPE_FPU | 8}, \
2695 {"$f9", RTYPE_FPU | 9}, \
2696 {"$f10", RTYPE_FPU | 10}, \
2697 {"$f11", RTYPE_FPU | 11}, \
2698 {"$f12", RTYPE_FPU | 12}, \
2699 {"$f13", RTYPE_FPU | 13}, \
2700 {"$f14", RTYPE_FPU | 14}, \
2701 {"$f15", RTYPE_FPU | 15}, \
2702 {"$f16", RTYPE_FPU | 16}, \
2703 {"$f17", RTYPE_FPU | 17}, \
2704 {"$f18", RTYPE_FPU | 18}, \
2705 {"$f19", RTYPE_FPU | 19}, \
2706 {"$f20", RTYPE_FPU | 20}, \
2707 {"$f21", RTYPE_FPU | 21}, \
2708 {"$f22", RTYPE_FPU | 22}, \
2709 {"$f23", RTYPE_FPU | 23}, \
2710 {"$f24", RTYPE_FPU | 24}, \
2711 {"$f25", RTYPE_FPU | 25}, \
2712 {"$f26", RTYPE_FPU | 26}, \
2713 {"$f27", RTYPE_FPU | 27}, \
2714 {"$f28", RTYPE_FPU | 28}, \
2715 {"$f29", RTYPE_FPU | 29}, \
2716 {"$f30", RTYPE_FPU | 30}, \
2717 {"$f31", RTYPE_FPU | 31}
2719 #define FPU_CONDITION_CODE_NAMES \
2720 {"$fcc0", RTYPE_FCC | 0}, \
2721 {"$fcc1", RTYPE_FCC | 1}, \
2722 {"$fcc2", RTYPE_FCC | 2}, \
2723 {"$fcc3", RTYPE_FCC | 3}, \
2724 {"$fcc4", RTYPE_FCC | 4}, \
2725 {"$fcc5", RTYPE_FCC | 5}, \
2726 {"$fcc6", RTYPE_FCC | 6}, \
2727 {"$fcc7", RTYPE_FCC | 7}
2729 #define COPROC_CONDITION_CODE_NAMES \
2730 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2731 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2732 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2733 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2734 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2735 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2736 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2737 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2739 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2740 {"$a4", RTYPE_GP | 8}, \
2741 {"$a5", RTYPE_GP | 9}, \
2742 {"$a6", RTYPE_GP | 10}, \
2743 {"$a7", RTYPE_GP | 11}, \
2744 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2745 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2746 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2747 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2748 {"$t0", RTYPE_GP | 12}, \
2749 {"$t1", RTYPE_GP | 13}, \
2750 {"$t2", RTYPE_GP | 14}, \
2751 {"$t3", RTYPE_GP | 15}
2753 #define O32_SYMBOLIC_REGISTER_NAMES \
2754 {"$t0", RTYPE_GP | 8}, \
2755 {"$t1", RTYPE_GP | 9}, \
2756 {"$t2", RTYPE_GP | 10}, \
2757 {"$t3", RTYPE_GP | 11}, \
2758 {"$t4", RTYPE_GP | 12}, \
2759 {"$t5", RTYPE_GP | 13}, \
2760 {"$t6", RTYPE_GP | 14}, \
2761 {"$t7", RTYPE_GP | 15}, \
2762 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2763 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2764 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2765 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2767 /* Remaining symbolic register names */
2768 #define SYMBOLIC_REGISTER_NAMES \
2769 {"$zero", RTYPE_GP | 0}, \
2770 {"$at", RTYPE_GP | 1}, \
2771 {"$AT", RTYPE_GP | 1}, \
2772 {"$v0", RTYPE_GP | 2}, \
2773 {"$v1", RTYPE_GP | 3}, \
2774 {"$a0", RTYPE_GP | 4}, \
2775 {"$a1", RTYPE_GP | 5}, \
2776 {"$a2", RTYPE_GP | 6}, \
2777 {"$a3", RTYPE_GP | 7}, \
2778 {"$s0", RTYPE_GP | 16}, \
2779 {"$s1", RTYPE_GP | 17}, \
2780 {"$s2", RTYPE_GP | 18}, \
2781 {"$s3", RTYPE_GP | 19}, \
2782 {"$s4", RTYPE_GP | 20}, \
2783 {"$s5", RTYPE_GP | 21}, \
2784 {"$s6", RTYPE_GP | 22}, \
2785 {"$s7", RTYPE_GP | 23}, \
2786 {"$t8", RTYPE_GP | 24}, \
2787 {"$t9", RTYPE_GP | 25}, \
2788 {"$k0", RTYPE_GP | 26}, \
2789 {"$kt0", RTYPE_GP | 26}, \
2790 {"$k1", RTYPE_GP | 27}, \
2791 {"$kt1", RTYPE_GP | 27}, \
2792 {"$gp", RTYPE_GP | 28}, \
2793 {"$sp", RTYPE_GP | 29}, \
2794 {"$s8", RTYPE_GP | 30}, \
2795 {"$fp", RTYPE_GP | 30}, \
2796 {"$ra", RTYPE_GP | 31}
2798 #define MIPS16_SPECIAL_REGISTER_NAMES \
2799 {"$pc", RTYPE_PC | 0}
2801 #define MDMX_VECTOR_REGISTER_NAMES \
2802 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2803 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2804 {"$v2", RTYPE_VEC | 2}, \
2805 {"$v3", RTYPE_VEC | 3}, \
2806 {"$v4", RTYPE_VEC | 4}, \
2807 {"$v5", RTYPE_VEC | 5}, \
2808 {"$v6", RTYPE_VEC | 6}, \
2809 {"$v7", RTYPE_VEC | 7}, \
2810 {"$v8", RTYPE_VEC | 8}, \
2811 {"$v9", RTYPE_VEC | 9}, \
2812 {"$v10", RTYPE_VEC | 10}, \
2813 {"$v11", RTYPE_VEC | 11}, \
2814 {"$v12", RTYPE_VEC | 12}, \
2815 {"$v13", RTYPE_VEC | 13}, \
2816 {"$v14", RTYPE_VEC | 14}, \
2817 {"$v15", RTYPE_VEC | 15}, \
2818 {"$v16", RTYPE_VEC | 16}, \
2819 {"$v17", RTYPE_VEC | 17}, \
2820 {"$v18", RTYPE_VEC | 18}, \
2821 {"$v19", RTYPE_VEC | 19}, \
2822 {"$v20", RTYPE_VEC | 20}, \
2823 {"$v21", RTYPE_VEC | 21}, \
2824 {"$v22", RTYPE_VEC | 22}, \
2825 {"$v23", RTYPE_VEC | 23}, \
2826 {"$v24", RTYPE_VEC | 24}, \
2827 {"$v25", RTYPE_VEC | 25}, \
2828 {"$v26", RTYPE_VEC | 26}, \
2829 {"$v27", RTYPE_VEC | 27}, \
2830 {"$v28", RTYPE_VEC | 28}, \
2831 {"$v29", RTYPE_VEC | 29}, \
2832 {"$v30", RTYPE_VEC | 30}, \
2833 {"$v31", RTYPE_VEC | 31}
2835 #define R5900_I_NAMES \
2836 {"$I", RTYPE_R5900_I | 0}
2838 #define R5900_Q_NAMES \
2839 {"$Q", RTYPE_R5900_Q | 0}
2841 #define R5900_R_NAMES \
2842 {"$R", RTYPE_R5900_R | 0}
2844 #define R5900_ACC_NAMES \
2845 {"$ACC", RTYPE_R5900_ACC | 0 }
2847 #define MIPS_DSP_ACCUMULATOR_NAMES \
2848 {"$ac0", RTYPE_ACC | 0}, \
2849 {"$ac1", RTYPE_ACC | 1}, \
2850 {"$ac2", RTYPE_ACC | 2}, \
2851 {"$ac3", RTYPE_ACC | 3}
2853 static const struct regname reg_names[] = {
2854 GENERIC_REGISTER_NUMBERS,
2856 FPU_CONDITION_CODE_NAMES,
2857 COPROC_CONDITION_CODE_NAMES,
2859 /* The $txx registers depends on the abi,
2860 these will be added later into the symbol table from
2861 one of the tables below once mips_abi is set after
2862 parsing of arguments from the command line. */
2863 SYMBOLIC_REGISTER_NAMES,
2865 MIPS16_SPECIAL_REGISTER_NAMES,
2866 MDMX_VECTOR_REGISTER_NAMES,
2871 MIPS_DSP_ACCUMULATOR_NAMES,
2875 static const struct regname reg_names_o32[] = {
2876 O32_SYMBOLIC_REGISTER_NAMES,
2880 static const struct regname reg_names_n32n64[] = {
2881 N32N64_SYMBOLIC_REGISTER_NAMES,
2885 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2886 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2887 of these register symbols, return the associated vector register,
2888 otherwise return SYMVAL itself. */
2891 mips_prefer_vec_regno (unsigned int symval)
2893 if ((symval & -2) == (RTYPE_GP | 2))
2894 return RTYPE_VEC | (symval & 1);
2898 /* Return true if string [S, E) is a valid register name, storing its
2899 symbol value in *SYMVAL_PTR if so. */
2902 mips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr)
2907 /* Terminate name. */
2911 /* Look up the name. */
2912 symbol = symbol_find (s);
2915 if (!symbol || S_GET_SEGMENT (symbol) != reg_section)
2918 *symval_ptr = S_GET_VALUE (symbol);
2922 /* Return true if the string at *SPTR is a valid register name. Allow it
2923 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2926 When returning true, move *SPTR past the register, store the
2927 register's symbol value in *SYMVAL_PTR and the channel mask in
2928 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2929 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2930 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2933 mips_parse_register (char **sptr, unsigned int *symval_ptr,
2934 unsigned int *channels_ptr)
2938 unsigned int channels, symval, bit;
2940 /* Find end of name. */
2942 if (is_name_beginner (*e))
2944 while (is_part_of_name (*e))
2948 if (!mips_parse_register_1 (s, e, &symval))
2953 /* Eat characters from the end of the string that are valid
2954 channel suffixes. The preceding register must be $ACC or
2955 end with a digit, so there is no ambiguity. */
2958 for (q = "wzyx"; *q; q++, bit <<= 1)
2959 if (m > s && m[-1] == *q)
2966 || !mips_parse_register_1 (s, m, &symval)
2967 || (symval & (RTYPE_VI | RTYPE_VF | RTYPE_R5900_ACC)) == 0)
2972 *symval_ptr = symval;
2974 *channels_ptr = channels;
2978 /* Check if SPTR points at a valid register specifier according to TYPES.
2979 If so, then return 1, advance S to consume the specifier and store
2980 the register's number in REGNOP, otherwise return 0. */
2983 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2987 if (mips_parse_register (s, ®no, NULL))
2989 if (types & RTYPE_VEC)
2990 regno = mips_prefer_vec_regno (regno);
2999 as_warn (_("unrecognized register name `%s'"), *s);
3004 return regno <= RNUM_MASK;
3007 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
3008 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
3011 mips_parse_vu0_channels (char *s, unsigned int *channels)
3016 for (i = 0; i < 4; i++)
3017 if (*s == "xyzw"[i])
3019 *channels |= 1 << (3 - i);
3025 /* Token types for parsed operand lists. */
3026 enum mips_operand_token_type {
3027 /* A plain register, e.g. $f2. */
3030 /* A 4-bit XYZW channel mask. */
3033 /* A constant vector index, e.g. [1]. */
3036 /* A register vector index, e.g. [$2]. */
3039 /* A continuous range of registers, e.g. $s0-$s4. */
3042 /* A (possibly relocated) expression. */
3045 /* A floating-point value. */
3048 /* A single character. This can be '(', ')' or ',', but '(' only appears
3052 /* A doubled character, either "--" or "++". */
3055 /* The end of the operand list. */
3059 /* A parsed operand token. */
3060 struct mips_operand_token
3062 /* The type of token. */
3063 enum mips_operand_token_type type;
3066 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
3069 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
3070 unsigned int channels;
3072 /* The integer value of an OT_INTEGER_INDEX. */
3075 /* The two register symbol values involved in an OT_REG_RANGE. */
3077 unsigned int regno1;
3078 unsigned int regno2;
3081 /* The value of an OT_INTEGER. The value is represented as an
3082 expression and the relocation operators that were applied to
3083 that expression. The reloc entries are BFD_RELOC_UNUSED if no
3084 relocation operators were used. */
3087 bfd_reloc_code_real_type relocs[3];
3090 /* The binary data for an OT_FLOAT constant, and the number of bytes
3093 unsigned char data[8];
3097 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
3102 /* An obstack used to construct lists of mips_operand_tokens. */
3103 static struct obstack mips_operand_tokens;
3105 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
3108 mips_add_token (struct mips_operand_token *token,
3109 enum mips_operand_token_type type)
3112 obstack_grow (&mips_operand_tokens, token, sizeof (*token));
3115 /* Check whether S is '(' followed by a register name. Add OT_CHAR
3116 and OT_REG tokens for them if so, and return a pointer to the first
3117 unconsumed character. Return null otherwise. */
3120 mips_parse_base_start (char *s)
3122 struct mips_operand_token token;
3123 unsigned int regno, channels;
3124 bfd_boolean decrement_p;
3130 SKIP_SPACE_TABS (s);
3132 /* Only match "--" as part of a base expression. In other contexts "--X"
3133 is a double negative. */
3134 decrement_p = (s[0] == '-' && s[1] == '-');
3138 SKIP_SPACE_TABS (s);
3141 /* Allow a channel specifier because that leads to better error messages
3142 than treating something like "$vf0x++" as an expression. */
3143 if (!mips_parse_register (&s, ®no, &channels))
3147 mips_add_token (&token, OT_CHAR);
3152 mips_add_token (&token, OT_DOUBLE_CHAR);
3155 token.u.regno = regno;
3156 mips_add_token (&token, OT_REG);
3160 token.u.channels = channels;
3161 mips_add_token (&token, OT_CHANNELS);
3164 /* For consistency, only match "++" as part of base expressions too. */
3165 SKIP_SPACE_TABS (s);
3166 if (s[0] == '+' && s[1] == '+')
3170 mips_add_token (&token, OT_DOUBLE_CHAR);
3176 /* Parse one or more tokens from S. Return a pointer to the first
3177 unconsumed character on success. Return null if an error was found
3178 and store the error text in insn_error. FLOAT_FORMAT is as for
3179 mips_parse_arguments. */
3182 mips_parse_argument_token (char *s, char float_format)
3184 char *end, *save_in;
3186 unsigned int regno1, regno2, channels;
3187 struct mips_operand_token token;
3189 /* First look for "($reg", since we want to treat that as an
3190 OT_CHAR and OT_REG rather than an expression. */
3191 end = mips_parse_base_start (s);
3195 /* Handle other characters that end up as OT_CHARs. */
3196 if (*s == ')' || *s == ',')
3199 mips_add_token (&token, OT_CHAR);
3204 /* Handle tokens that start with a register. */
3205 if (mips_parse_register (&s, ®no1, &channels))
3209 /* A register and a VU0 channel suffix. */
3210 token.u.regno = regno1;
3211 mips_add_token (&token, OT_REG);
3213 token.u.channels = channels;
3214 mips_add_token (&token, OT_CHANNELS);
3218 SKIP_SPACE_TABS (s);
3221 /* A register range. */
3223 SKIP_SPACE_TABS (s);
3224 if (!mips_parse_register (&s, ®no2, NULL))
3226 set_insn_error (0, _("invalid register range"));
3230 token.u.reg_range.regno1 = regno1;
3231 token.u.reg_range.regno2 = regno2;
3232 mips_add_token (&token, OT_REG_RANGE);
3236 /* Add the register itself. */
3237 token.u.regno = regno1;
3238 mips_add_token (&token, OT_REG);
3240 /* Check for a vector index. */
3244 SKIP_SPACE_TABS (s);
3245 if (mips_parse_register (&s, &token.u.regno, NULL))
3246 mips_add_token (&token, OT_REG_INDEX);
3249 expressionS element;
3251 my_getExpression (&element, s);
3252 if (element.X_op != O_constant)
3254 set_insn_error (0, _("vector element must be constant"));
3258 token.u.index = element.X_add_number;
3259 mips_add_token (&token, OT_INTEGER_INDEX);
3261 SKIP_SPACE_TABS (s);
3264 set_insn_error (0, _("missing `]'"));
3274 /* First try to treat expressions as floats. */
3275 save_in = input_line_pointer;
3276 input_line_pointer = s;
3277 err = md_atof (float_format, (char *) token.u.flt.data,
3278 &token.u.flt.length);
3279 end = input_line_pointer;
3280 input_line_pointer = save_in;
3283 set_insn_error (0, err);
3288 mips_add_token (&token, OT_FLOAT);
3293 /* Treat everything else as an integer expression. */
3294 token.u.integer.relocs[0] = BFD_RELOC_UNUSED;
3295 token.u.integer.relocs[1] = BFD_RELOC_UNUSED;
3296 token.u.integer.relocs[2] = BFD_RELOC_UNUSED;
3297 my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s);
3299 mips_add_token (&token, OT_INTEGER);
3303 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3304 if expressions should be treated as 32-bit floating-point constants,
3305 'd' if they should be treated as 64-bit floating-point constants,
3306 or 0 if they should be treated as integer expressions (the usual case).
3308 Return a list of tokens on success, otherwise return 0. The caller
3309 must obstack_free the list after use. */
3311 static struct mips_operand_token *
3312 mips_parse_arguments (char *s, char float_format)
3314 struct mips_operand_token token;
3316 SKIP_SPACE_TABS (s);
3319 s = mips_parse_argument_token (s, float_format);
3322 obstack_free (&mips_operand_tokens,
3323 obstack_finish (&mips_operand_tokens));
3326 SKIP_SPACE_TABS (s);
3328 mips_add_token (&token, OT_END);
3329 return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens);
3332 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3333 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3336 is_opcode_valid (const struct mips_opcode *mo)
3338 int isa = mips_opts.isa;
3339 int ase = mips_opts.ase;
3343 if (ISA_HAS_64BIT_REGS (isa))
3344 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
3345 if ((ase & mips_ases[i].flags) == mips_ases[i].flags)
3346 ase |= mips_ases[i].flags64;
3348 if (!opcode_is_member (mo, isa, ase, mips_opts.arch))
3351 /* Check whether the instruction or macro requires single-precision or
3352 double-precision floating-point support. Note that this information is
3353 stored differently in the opcode table for insns and macros. */
3354 if (mo->pinfo == INSN_MACRO)
3356 fp_s = mo->pinfo2 & INSN2_M_FP_S;
3357 fp_d = mo->pinfo2 & INSN2_M_FP_D;
3361 fp_s = mo->pinfo & FP_S;
3362 fp_d = mo->pinfo & FP_D;
3365 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
3368 if (fp_s && mips_opts.soft_float)
3374 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3375 selected ISA and architecture. */
3378 is_opcode_valid_16 (const struct mips_opcode *mo)
3380 int isa = mips_opts.isa;
3381 int ase = mips_opts.ase;
3384 if (ISA_HAS_64BIT_REGS (isa))
3385 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
3386 if ((ase & mips_ases[i].flags) == mips_ases[i].flags)
3387 ase |= mips_ases[i].flags64;
3389 return opcode_is_member (mo, isa, ase, mips_opts.arch);
3392 /* Return TRUE if the size of the microMIPS opcode MO matches one
3393 explicitly requested. Always TRUE in the standard MIPS mode.
3394 Use is_size_valid_16 for MIPS16 opcodes. */
3397 is_size_valid (const struct mips_opcode *mo)
3399 if (!mips_opts.micromips)
3402 if (mips_opts.insn32)
3404 if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4)
3406 if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0)
3409 if (!forced_insn_length)
3411 if (mo->pinfo == INSN_MACRO)
3413 return forced_insn_length == micromips_insn_length (mo);
3416 /* Return TRUE if the size of the MIPS16 opcode MO matches one
3417 explicitly requested. */
3420 is_size_valid_16 (const struct mips_opcode *mo)
3422 if (!forced_insn_length)
3424 if (mo->pinfo == INSN_MACRO)
3426 if (forced_insn_length == 2 && mips_opcode_32bit_p (mo))
3428 if (forced_insn_length == 4 && (mo->pinfo2 & INSN2_SHORT_ONLY))
3433 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3434 of the preceding instruction. Always TRUE in the standard MIPS mode.
3436 We don't accept macros in 16-bit delay slots to avoid a case where
3437 a macro expansion fails because it relies on a preceding 32-bit real
3438 instruction to have matched and does not handle the operands correctly.
3439 The only macros that may expand to 16-bit instructions are JAL that
3440 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3441 and BGT (that likewise cannot be placed in a delay slot) that decay to
3442 a NOP. In all these cases the macros precede any corresponding real
3443 instruction definitions in the opcode table, so they will match in the
3444 second pass where the size of the delay slot is ignored and therefore
3445 produce correct code. */
3448 is_delay_slot_valid (const struct mips_opcode *mo)
3450 if (!mips_opts.micromips)
3453 if (mo->pinfo == INSN_MACRO)
3454 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0;
3455 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
3456 && micromips_insn_length (mo) != 4)
3458 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
3459 && micromips_insn_length (mo) != 2)
3465 /* For consistency checking, verify that all bits of OPCODE are specified
3466 either by the match/mask part of the instruction definition, or by the
3467 operand list. Also build up a list of operands in OPERANDS.
3469 INSN_BITS says which bits of the instruction are significant.
3470 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3471 provides the mips_operand description of each operand. DECODE_OPERAND
3472 is null for MIPS16 instructions. */
3475 validate_mips_insn (const struct mips_opcode *opcode,
3476 unsigned long insn_bits,
3477 const struct mips_operand *(*decode_operand) (const char *),
3478 struct mips_operand_array *operands)
3481 unsigned long used_bits, doubled, undefined, opno, mask;
3482 const struct mips_operand *operand;
3484 mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask);
3485 if ((mask & opcode->match) != opcode->match)
3487 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3488 opcode->name, opcode->args);
3493 if (opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX)
3494 used_bits = mips_insert_operand (&mips_vu0_channel_mask, used_bits, -1);
3495 for (s = opcode->args; *s; ++s)
3508 if (!decode_operand)
3509 operand = decode_mips16_operand (*s, mips_opcode_32bit_p (opcode));
3511 operand = decode_operand (s);
3512 if (!operand && opcode->pinfo != INSN_MACRO)
3514 as_bad (_("internal: unknown operand type: %s %s"),
3515 opcode->name, opcode->args);
3518 gas_assert (opno < MAX_OPERANDS);
3519 operands->operand[opno] = operand;
3520 if (!decode_operand && operand
3521 && operand->type == OP_INT && operand->lsb == 0
3522 && mips_opcode_32bit_p (opcode))
3523 used_bits |= mips16_immed_extend (-1, operand->size);
3524 else if (operand && operand->type != OP_VU0_MATCH_SUFFIX)
3526 used_bits = mips_insert_operand (operand, used_bits, -1);
3527 if (operand->type == OP_MDMX_IMM_REG)
3528 /* Bit 5 is the format selector (OB vs QH). The opcode table
3529 has separate entries for each format. */
3530 used_bits &= ~(1 << (operand->lsb + 5));
3531 if (operand->type == OP_ENTRY_EXIT_LIST)
3532 used_bits &= ~(mask & 0x700);
3533 /* interAptiv MR2 SAVE/RESTORE instructions have a discontiguous
3534 operand field that cannot be fully described with LSB/SIZE. */
3535 if (operand->type == OP_SAVE_RESTORE_LIST && operand->lsb == 6)
3536 used_bits &= ~0x6000;
3538 /* Skip prefix characters. */
3539 if (decode_operand && (*s == '+' || *s == 'm' || *s == '-'))
3544 doubled = used_bits & mask & insn_bits;
3547 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3548 " %s %s"), doubled, opcode->name, opcode->args);
3552 undefined = ~used_bits & insn_bits;
3553 if (opcode->pinfo != INSN_MACRO && undefined)
3555 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3556 undefined, opcode->name, opcode->args);
3559 used_bits &= ~insn_bits;
3562 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3563 used_bits, opcode->name, opcode->args);
3569 /* The MIPS16 version of validate_mips_insn. */
3572 validate_mips16_insn (const struct mips_opcode *opcode,
3573 struct mips_operand_array *operands)
3575 unsigned long insn_bits = mips_opcode_32bit_p (opcode) ? 0xffffffff : 0xffff;
3577 return validate_mips_insn (opcode, insn_bits, 0, operands);
3580 /* The microMIPS version of validate_mips_insn. */
3583 validate_micromips_insn (const struct mips_opcode *opc,
3584 struct mips_operand_array *operands)
3586 unsigned long insn_bits;
3587 unsigned long major;
3588 unsigned int length;
3590 if (opc->pinfo == INSN_MACRO)
3591 return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand,
3594 length = micromips_insn_length (opc);
3595 if (length != 2 && length != 4)
3597 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3598 "%s %s"), length, opc->name, opc->args);
3601 major = opc->match >> (10 + 8 * (length - 2));
3602 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
3603 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
3605 as_bad (_("internal error: bad microMIPS opcode "
3606 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
3610 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3611 insn_bits = 1 << 4 * length;
3612 insn_bits <<= 4 * length;
3614 return validate_mips_insn (opc, insn_bits, decode_micromips_operand,
3618 /* This function is called once, at assembler startup time. It should set up
3619 all the tables, etc. that the MD part of the assembler will need. */
3624 const char *retval = NULL;
3628 if (mips_pic != NO_PIC)
3630 if (g_switch_seen && g_switch_value != 0)
3631 as_bad (_("-G may not be used in position-independent code"));
3634 else if (mips_abicalls)
3636 if (g_switch_seen && g_switch_value != 0)
3637 as_bad (_("-G may not be used with abicalls"));
3641 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch))
3642 as_warn (_("could not set architecture and machine"));
3644 op_hash = hash_new ();
3646 mips_operands = XCNEWVEC (struct mips_operand_array, NUMOPCODES);
3647 for (i = 0; i < NUMOPCODES;)
3649 const char *name = mips_opcodes[i].name;
3651 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
3654 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
3655 mips_opcodes[i].name, retval);
3656 /* Probably a memory allocation problem? Give up now. */
3657 as_fatal (_("broken assembler, no assembly attempted"));
3661 if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff,
3662 decode_mips_operand, &mips_operands[i]))
3664 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3666 create_insn (&nop_insn, mips_opcodes + i);
3667 if (mips_fix_loongson2f_nop)
3668 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
3669 nop_insn.fixed_p = 1;
3673 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
3676 mips16_op_hash = hash_new ();
3677 mips16_operands = XCNEWVEC (struct mips_operand_array,
3678 bfd_mips16_num_opcodes);
3681 while (i < bfd_mips16_num_opcodes)
3683 const char *name = mips16_opcodes[i].name;
3685 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
3687 as_fatal (_("internal: can't hash `%s': %s"),
3688 mips16_opcodes[i].name, retval);
3691 if (!validate_mips16_insn (&mips16_opcodes[i], &mips16_operands[i]))
3693 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3695 create_insn (&mips16_nop_insn, mips16_opcodes + i);
3696 mips16_nop_insn.fixed_p = 1;
3700 while (i < bfd_mips16_num_opcodes
3701 && strcmp (mips16_opcodes[i].name, name) == 0);
3704 micromips_op_hash = hash_new ();
3705 micromips_operands = XCNEWVEC (struct mips_operand_array,
3706 bfd_micromips_num_opcodes);
3709 while (i < bfd_micromips_num_opcodes)
3711 const char *name = micromips_opcodes[i].name;
3713 retval = hash_insert (micromips_op_hash, name,
3714 (void *) µmips_opcodes[i]);
3716 as_fatal (_("internal: can't hash `%s': %s"),
3717 micromips_opcodes[i].name, retval);
3720 struct mips_cl_insn *micromips_nop_insn;
3722 if (!validate_micromips_insn (µmips_opcodes[i],
3723 µmips_operands[i]))
3726 if (micromips_opcodes[i].pinfo != INSN_MACRO)
3728 if (micromips_insn_length (micromips_opcodes + i) == 2)
3729 micromips_nop_insn = µmips_nop16_insn;
3730 else if (micromips_insn_length (micromips_opcodes + i) == 4)
3731 micromips_nop_insn = µmips_nop32_insn;
3735 if (micromips_nop_insn->insn_mo == NULL
3736 && strcmp (name, "nop") == 0)
3738 create_insn (micromips_nop_insn, micromips_opcodes + i);
3739 micromips_nop_insn->fixed_p = 1;
3743 while (++i < bfd_micromips_num_opcodes
3744 && strcmp (micromips_opcodes[i].name, name) == 0);
3748 as_fatal (_("broken assembler, no assembly attempted"));
3750 /* We add all the general register names to the symbol table. This
3751 helps us detect invalid uses of them. */
3752 for (i = 0; reg_names[i].name; i++)
3753 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
3754 reg_names[i].num, /* & RNUM_MASK, */
3755 &zero_address_frag));
3757 for (i = 0; reg_names_n32n64[i].name; i++)
3758 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
3759 reg_names_n32n64[i].num, /* & RNUM_MASK, */
3760 &zero_address_frag));
3762 for (i = 0; reg_names_o32[i].name; i++)
3763 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
3764 reg_names_o32[i].num, /* & RNUM_MASK, */
3765 &zero_address_frag));
3767 for (i = 0; i < 32; i++)
3771 /* R5900 VU0 floating-point register. */
3772 sprintf (regname, "$vf%d", i);
3773 symbol_table_insert (symbol_new (regname, reg_section,
3774 RTYPE_VF | i, &zero_address_frag));
3776 /* R5900 VU0 integer register. */
3777 sprintf (regname, "$vi%d", i);
3778 symbol_table_insert (symbol_new (regname, reg_section,
3779 RTYPE_VI | i, &zero_address_frag));
3782 sprintf (regname, "$w%d", i);
3783 symbol_table_insert (symbol_new (regname, reg_section,
3784 RTYPE_MSA | i, &zero_address_frag));
3787 obstack_init (&mips_operand_tokens);
3789 mips_no_prev_insn ();
3792 mips_cprmask[0] = 0;
3793 mips_cprmask[1] = 0;
3794 mips_cprmask[2] = 0;
3795 mips_cprmask[3] = 0;
3797 /* set the default alignment for the text section (2**2) */
3798 record_alignment (text_section, 2);
3800 bfd_set_gp_size (stdoutput, g_switch_value);
3802 /* On a native system other than VxWorks, sections must be aligned
3803 to 16 byte boundaries. When configured for an embedded ELF
3804 target, we don't bother. */
3805 if (strncmp (TARGET_OS, "elf", 3) != 0
3806 && strncmp (TARGET_OS, "vxworks", 7) != 0)
3808 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
3809 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
3810 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
3813 /* Create a .reginfo section for register masks and a .mdebug
3814 section for debugging information. */
3822 subseg = now_subseg;
3824 /* The ABI says this section should be loaded so that the
3825 running program can access it. However, we don't load it
3826 if we are configured for an embedded target */
3827 flags = SEC_READONLY | SEC_DATA;
3828 if (strncmp (TARGET_OS, "elf", 3) != 0)
3829 flags |= SEC_ALLOC | SEC_LOAD;
3831 if (mips_abi != N64_ABI)
3833 sec = subseg_new (".reginfo", (subsegT) 0);
3835 bfd_set_section_flags (stdoutput, sec, flags);
3836 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
3838 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
3842 /* The 64-bit ABI uses a .MIPS.options section rather than
3843 .reginfo section. */
3844 sec = subseg_new (".MIPS.options", (subsegT) 0);
3845 bfd_set_section_flags (stdoutput, sec, flags);
3846 bfd_set_section_alignment (stdoutput, sec, 3);
3848 /* Set up the option header. */
3850 Elf_Internal_Options opthdr;
3853 opthdr.kind = ODK_REGINFO;
3854 opthdr.size = (sizeof (Elf_External_Options)
3855 + sizeof (Elf64_External_RegInfo));
3858 f = frag_more (sizeof (Elf_External_Options));
3859 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
3860 (Elf_External_Options *) f);
3862 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
3866 sec = subseg_new (".MIPS.abiflags", (subsegT) 0);
3867 bfd_set_section_flags (stdoutput, sec,
3868 SEC_READONLY | SEC_DATA | SEC_ALLOC | SEC_LOAD);
3869 bfd_set_section_alignment (stdoutput, sec, 3);
3870 mips_flags_frag = frag_more (sizeof (Elf_External_ABIFlags_v0));
3872 if (ECOFF_DEBUGGING)
3874 sec = subseg_new (".mdebug", (subsegT) 0);
3875 (void) bfd_set_section_flags (stdoutput, sec,
3876 SEC_HAS_CONTENTS | SEC_READONLY);
3877 (void) bfd_set_section_alignment (stdoutput, sec, 2);
3879 else if (mips_flag_pdr)
3881 pdr_seg = subseg_new (".pdr", (subsegT) 0);
3882 (void) bfd_set_section_flags (stdoutput, pdr_seg,
3883 SEC_READONLY | SEC_RELOC
3885 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
3888 subseg_set (seg, subseg);
3891 if (mips_fix_vr4120)
3892 init_vr4120_conflicts ();
3896 fpabi_incompatible_with (int fpabi, const char *what)
3898 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3899 Tag_GNU_MIPS_ABI_FP, fpabi, what);
3903 fpabi_requires (int fpabi, const char *what)
3905 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3906 Tag_GNU_MIPS_ABI_FP, fpabi, what);
3909 /* Check -mabi and register sizes against the specified FP ABI. */
3911 check_fpabi (int fpabi)
3915 case Val_GNU_MIPS_ABI_FP_DOUBLE:
3916 if (file_mips_opts.soft_float)
3917 fpabi_incompatible_with (fpabi, "softfloat");
3918 else if (file_mips_opts.single_float)
3919 fpabi_incompatible_with (fpabi, "singlefloat");
3920 if (file_mips_opts.gp == 64 && file_mips_opts.fp == 32)
3921 fpabi_incompatible_with (fpabi, "gp=64 fp=32");
3922 else if (file_mips_opts.gp == 32 && file_mips_opts.fp == 64)
3923 fpabi_incompatible_with (fpabi, "gp=32 fp=64");
3926 case Val_GNU_MIPS_ABI_FP_XX:
3927 if (mips_abi != O32_ABI)
3928 fpabi_requires (fpabi, "-mabi=32");
3929 else if (file_mips_opts.soft_float)
3930 fpabi_incompatible_with (fpabi, "softfloat");
3931 else if (file_mips_opts.single_float)
3932 fpabi_incompatible_with (fpabi, "singlefloat");
3933 else if (file_mips_opts.fp != 0)
3934 fpabi_requires (fpabi, "fp=xx");
3937 case Val_GNU_MIPS_ABI_FP_64A:
3938 case Val_GNU_MIPS_ABI_FP_64:
3939 if (mips_abi != O32_ABI)
3940 fpabi_requires (fpabi, "-mabi=32");
3941 else if (file_mips_opts.soft_float)
3942 fpabi_incompatible_with (fpabi, "softfloat");
3943 else if (file_mips_opts.single_float)
3944 fpabi_incompatible_with (fpabi, "singlefloat");
3945 else if (file_mips_opts.fp != 64)
3946 fpabi_requires (fpabi, "fp=64");
3947 else if (fpabi == Val_GNU_MIPS_ABI_FP_64 && !file_mips_opts.oddspreg)
3948 fpabi_incompatible_with (fpabi, "nooddspreg");
3949 else if (fpabi == Val_GNU_MIPS_ABI_FP_64A && file_mips_opts.oddspreg)
3950 fpabi_requires (fpabi, "nooddspreg");
3953 case Val_GNU_MIPS_ABI_FP_SINGLE:
3954 if (file_mips_opts.soft_float)
3955 fpabi_incompatible_with (fpabi, "softfloat");
3956 else if (!file_mips_opts.single_float)
3957 fpabi_requires (fpabi, "singlefloat");
3960 case Val_GNU_MIPS_ABI_FP_SOFT:
3961 if (!file_mips_opts.soft_float)
3962 fpabi_requires (fpabi, "softfloat");
3965 case Val_GNU_MIPS_ABI_FP_OLD_64:
3966 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
3967 Tag_GNU_MIPS_ABI_FP, fpabi);
3970 case Val_GNU_MIPS_ABI_FP_NAN2008:
3971 /* Silently ignore compatibility value. */
3975 as_warn (_(".gnu_attribute %d,%d is not a recognized"
3976 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP, fpabi);
3981 /* Perform consistency checks on the current options. */
3984 mips_check_options (struct mips_set_options *opts, bfd_boolean abi_checks)
3986 /* Check the size of integer registers agrees with the ABI and ISA. */
3987 if (opts->gp == 64 && !ISA_HAS_64BIT_REGS (opts->isa))
3988 as_bad (_("`gp=64' used with a 32-bit processor"));
3990 && opts->gp == 32 && ABI_NEEDS_64BIT_REGS (mips_abi))
3991 as_bad (_("`gp=32' used with a 64-bit ABI"));
3993 && opts->gp == 64 && ABI_NEEDS_32BIT_REGS (mips_abi))
3994 as_bad (_("`gp=64' used with a 32-bit ABI"));
3996 /* Check the size of the float registers agrees with the ABI and ISA. */
4000 if (!CPU_HAS_LDC1_SDC1 (opts->arch))
4001 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
4002 else if (opts->single_float == 1)
4003 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
4006 if (!ISA_HAS_64BIT_FPRS (opts->isa))
4007 as_bad (_("`fp=64' used with a 32-bit fpu"));
4009 && ABI_NEEDS_32BIT_REGS (mips_abi)
4010 && !ISA_HAS_MXHC1 (opts->isa))
4011 as_warn (_("`fp=64' used with a 32-bit ABI"));
4015 && ABI_NEEDS_64BIT_REGS (mips_abi))
4016 as_warn (_("`fp=32' used with a 64-bit ABI"));
4017 if (ISA_IS_R6 (opts->isa) && opts->single_float == 0)
4018 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
4021 as_bad (_("Unknown size of floating point registers"));
4025 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !opts->oddspreg)
4026 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
4028 if (opts->micromips == 1 && opts->mips16 == 1)
4029 as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips");
4030 else if (ISA_IS_R6 (opts->isa)
4031 && (opts->micromips == 1
4032 || opts->mips16 == 1))
4033 as_fatal (_("`%s' cannot be used with `%s'"),
4034 opts->micromips ? "micromips" : "mips16",
4035 mips_cpu_info_from_isa (opts->isa)->name);
4037 if (ISA_IS_R6 (opts->isa) && mips_relax_branch)
4038 as_fatal (_("branch relaxation is not supported in `%s'"),
4039 mips_cpu_info_from_isa (opts->isa)->name);
4042 /* Perform consistency checks on the module level options exactly once.
4043 This is a deferred check that happens:
4044 at the first .set directive
4045 or, at the first pseudo op that generates code (inc .dc.a)
4046 or, at the first instruction
4050 file_mips_check_options (void)
4052 const struct mips_cpu_info *arch_info = 0;
4054 if (file_mips_opts_checked)
4057 /* The following code determines the register size.
4058 Similar code was added to GCC 3.3 (see override_options() in
4059 config/mips/mips.c). The GAS and GCC code should be kept in sync
4060 as much as possible. */
4062 if (file_mips_opts.gp < 0)
4064 /* Infer the integer register size from the ABI and processor.
4065 Restrict ourselves to 32-bit registers if that's all the
4066 processor has, or if the ABI cannot handle 64-bit registers. */
4067 file_mips_opts.gp = (ABI_NEEDS_32BIT_REGS (mips_abi)
4068 || !ISA_HAS_64BIT_REGS (file_mips_opts.isa))
4072 if (file_mips_opts.fp < 0)
4074 /* No user specified float register size.
4075 ??? GAS treats single-float processors as though they had 64-bit
4076 float registers (although it complains when double-precision
4077 instructions are used). As things stand, saying they have 32-bit
4078 registers would lead to spurious "register must be even" messages.
4079 So here we assume float registers are never smaller than the
4081 if (file_mips_opts.gp == 64)
4082 /* 64-bit integer registers implies 64-bit float registers. */
4083 file_mips_opts.fp = 64;
4084 else if ((file_mips_opts.ase & FP64_ASES)
4085 && ISA_HAS_64BIT_FPRS (file_mips_opts.isa))
4086 /* Handle ASEs that require 64-bit float registers, if possible. */
4087 file_mips_opts.fp = 64;
4088 else if (ISA_IS_R6 (mips_opts.isa))
4089 /* R6 implies 64-bit float registers. */
4090 file_mips_opts.fp = 64;
4092 /* 32-bit float registers. */
4093 file_mips_opts.fp = 32;
4096 arch_info = mips_cpu_info_from_arch (file_mips_opts.arch);
4098 /* Disable operations on odd-numbered floating-point registers by default
4099 when using the FPXX ABI. */
4100 if (file_mips_opts.oddspreg < 0)
4102 if (file_mips_opts.fp == 0)
4103 file_mips_opts.oddspreg = 0;
4105 file_mips_opts.oddspreg = 1;
4108 /* End of GCC-shared inference code. */
4110 /* This flag is set when we have a 64-bit capable CPU but use only
4111 32-bit wide registers. Note that EABI does not use it. */
4112 if (ISA_HAS_64BIT_REGS (file_mips_opts.isa)
4113 && ((mips_abi == NO_ABI && file_mips_opts.gp == 32)
4114 || mips_abi == O32_ABI))
4117 if (file_mips_opts.isa == ISA_MIPS1 && mips_trap)
4118 as_bad (_("trap exception not supported at ISA 1"));
4120 /* If the selected architecture includes support for ASEs, enable
4121 generation of code for them. */
4122 if (file_mips_opts.mips16 == -1)
4123 file_mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_opts.arch)) ? 1 : 0;
4124 if (file_mips_opts.micromips == -1)
4125 file_mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_opts.arch))
4128 if (mips_nan2008 == -1)
4129 mips_nan2008 = (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) ? 0 : 1;
4130 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts.isa) && mips_nan2008 == 0)
4131 as_fatal (_("`%s' does not support legacy NaN"),
4132 mips_cpu_info_from_arch (file_mips_opts.arch)->name);
4134 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
4135 being selected implicitly. */
4136 if (file_mips_opts.fp != 64)
4137 file_ase_explicit |= ASE_MIPS3D | ASE_MDMX | ASE_MSA;
4139 /* If the user didn't explicitly select or deselect a particular ASE,
4140 use the default setting for the CPU. */
4141 file_mips_opts.ase |= (arch_info->ase & ~file_ase_explicit);
4143 /* Set up the current options. These may change throughout assembly. */
4144 mips_opts = file_mips_opts;
4146 mips_check_isa_supports_ases ();
4147 mips_check_options (&file_mips_opts, TRUE);
4148 file_mips_opts_checked = TRUE;
4150 if (!bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch))
4151 as_warn (_("could not set architecture and machine"));
4155 md_assemble (char *str)
4157 struct mips_cl_insn insn;
4158 bfd_reloc_code_real_type unused_reloc[3]
4159 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
4161 file_mips_check_options ();
4163 imm_expr.X_op = O_absent;
4164 offset_expr.X_op = O_absent;
4165 offset_reloc[0] = BFD_RELOC_UNUSED;
4166 offset_reloc[1] = BFD_RELOC_UNUSED;
4167 offset_reloc[2] = BFD_RELOC_UNUSED;
4169 mips_mark_labels ();
4170 mips_assembling_insn = TRUE;
4171 clear_insn_error ();
4173 if (mips_opts.mips16)
4174 mips16_ip (str, &insn);
4177 mips_ip (str, &insn);
4178 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4179 str, insn.insn_opcode));
4183 report_insn_error (str);
4184 else if (insn.insn_mo->pinfo == INSN_MACRO)
4187 if (mips_opts.mips16)
4188 mips16_macro (&insn);
4195 if (offset_expr.X_op != O_absent)
4196 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
4198 append_insn (&insn, NULL, unused_reloc, FALSE);
4201 mips_assembling_insn = FALSE;
4204 /* Convenience functions for abstracting away the differences between
4205 MIPS16 and non-MIPS16 relocations. */
4207 static inline bfd_boolean
4208 mips16_reloc_p (bfd_reloc_code_real_type reloc)
4212 case BFD_RELOC_MIPS16_JMP:
4213 case BFD_RELOC_MIPS16_GPREL:
4214 case BFD_RELOC_MIPS16_GOT16:
4215 case BFD_RELOC_MIPS16_CALL16:
4216 case BFD_RELOC_MIPS16_HI16_S:
4217 case BFD_RELOC_MIPS16_HI16:
4218 case BFD_RELOC_MIPS16_LO16:
4219 case BFD_RELOC_MIPS16_16_PCREL_S1:
4227 static inline bfd_boolean
4228 micromips_reloc_p (bfd_reloc_code_real_type reloc)
4232 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
4233 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
4234 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
4235 case BFD_RELOC_MICROMIPS_GPREL16:
4236 case BFD_RELOC_MICROMIPS_JMP:
4237 case BFD_RELOC_MICROMIPS_HI16:
4238 case BFD_RELOC_MICROMIPS_HI16_S:
4239 case BFD_RELOC_MICROMIPS_LO16:
4240 case BFD_RELOC_MICROMIPS_LITERAL:
4241 case BFD_RELOC_MICROMIPS_GOT16:
4242 case BFD_RELOC_MICROMIPS_CALL16:
4243 case BFD_RELOC_MICROMIPS_GOT_HI16:
4244 case BFD_RELOC_MICROMIPS_GOT_LO16:
4245 case BFD_RELOC_MICROMIPS_CALL_HI16:
4246 case BFD_RELOC_MICROMIPS_CALL_LO16:
4247 case BFD_RELOC_MICROMIPS_SUB:
4248 case BFD_RELOC_MICROMIPS_GOT_PAGE:
4249 case BFD_RELOC_MICROMIPS_GOT_OFST:
4250 case BFD_RELOC_MICROMIPS_GOT_DISP:
4251 case BFD_RELOC_MICROMIPS_HIGHEST:
4252 case BFD_RELOC_MICROMIPS_HIGHER:
4253 case BFD_RELOC_MICROMIPS_SCN_DISP:
4254 case BFD_RELOC_MICROMIPS_JALR:
4262 static inline bfd_boolean
4263 jmp_reloc_p (bfd_reloc_code_real_type reloc)
4265 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
4268 static inline bfd_boolean
4269 b_reloc_p (bfd_reloc_code_real_type reloc)
4271 return (reloc == BFD_RELOC_MIPS_26_PCREL_S2
4272 || reloc == BFD_RELOC_MIPS_21_PCREL_S2
4273 || reloc == BFD_RELOC_16_PCREL_S2
4274 || reloc == BFD_RELOC_MIPS16_16_PCREL_S1
4275 || reloc == BFD_RELOC_MICROMIPS_16_PCREL_S1
4276 || reloc == BFD_RELOC_MICROMIPS_10_PCREL_S1
4277 || reloc == BFD_RELOC_MICROMIPS_7_PCREL_S1);
4280 static inline bfd_boolean
4281 got16_reloc_p (bfd_reloc_code_real_type reloc)
4283 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
4284 || reloc == BFD_RELOC_MICROMIPS_GOT16);
4287 static inline bfd_boolean
4288 hi16_reloc_p (bfd_reloc_code_real_type reloc)
4290 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
4291 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
4294 static inline bfd_boolean
4295 lo16_reloc_p (bfd_reloc_code_real_type reloc)
4297 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
4298 || reloc == BFD_RELOC_MICROMIPS_LO16);
4301 static inline bfd_boolean
4302 jalr_reloc_p (bfd_reloc_code_real_type reloc)
4304 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
4307 static inline bfd_boolean
4308 gprel16_reloc_p (bfd_reloc_code_real_type reloc)
4310 return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL
4311 || reloc == BFD_RELOC_MICROMIPS_GPREL16);
4314 /* Return true if RELOC is a PC-relative relocation that does not have
4315 full address range. */
4317 static inline bfd_boolean
4318 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc)
4322 case BFD_RELOC_16_PCREL_S2:
4323 case BFD_RELOC_MIPS16_16_PCREL_S1:
4324 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
4325 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
4326 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
4327 case BFD_RELOC_MIPS_21_PCREL_S2:
4328 case BFD_RELOC_MIPS_26_PCREL_S2:
4329 case BFD_RELOC_MIPS_18_PCREL_S3:
4330 case BFD_RELOC_MIPS_19_PCREL_S2:
4333 case BFD_RELOC_32_PCREL:
4334 case BFD_RELOC_HI16_S_PCREL:
4335 case BFD_RELOC_LO16_PCREL:
4336 return HAVE_64BIT_ADDRESSES;
4343 /* Return true if the given relocation might need a matching %lo().
4344 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4345 need a matching %lo() when applied to local symbols. */
4347 static inline bfd_boolean
4348 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
4350 return (HAVE_IN_PLACE_ADDENDS
4351 && (hi16_reloc_p (reloc)
4352 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4353 all GOT16 relocations evaluate to "G". */
4354 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
4357 /* Return the type of %lo() reloc needed by RELOC, given that
4358 reloc_needs_lo_p. */
4360 static inline bfd_reloc_code_real_type
4361 matching_lo_reloc (bfd_reloc_code_real_type reloc)
4363 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
4364 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
4368 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
4371 static inline bfd_boolean
4372 fixup_has_matching_lo_p (fixS *fixp)
4374 return (fixp->fx_next != NULL
4375 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
4376 && fixp->fx_addsy == fixp->fx_next->fx_addsy
4377 && fixp->fx_offset == fixp->fx_next->fx_offset);
4380 /* Move all labels in LABELS to the current insertion point. TEXT_P
4381 says whether the labels refer to text or data. */
4384 mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
4386 struct insn_label_list *l;
4389 for (l = labels; l != NULL; l = l->next)
4391 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
4392 symbol_set_frag (l->label, frag_now);
4393 val = (valueT) frag_now_fix ();
4394 /* MIPS16/microMIPS text labels are stored as odd. */
4395 if (text_p && HAVE_CODE_COMPRESSION)
4397 S_SET_VALUE (l->label, val);
4401 /* Move all labels in insn_labels to the current insertion point
4402 and treat them as text labels. */
4405 mips_move_text_labels (void)
4407 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
4410 /* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */
4413 s_is_linkonce (symbolS *sym, segT from_seg)
4415 bfd_boolean linkonce = FALSE;
4416 segT symseg = S_GET_SEGMENT (sym);
4418 if (symseg != from_seg && !S_IS_LOCAL (sym))
4420 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
4422 /* The GNU toolchain uses an extension for ELF: a section
4423 beginning with the magic string .gnu.linkonce is a
4424 linkonce section. */
4425 if (strncmp (segment_name (symseg), ".gnu.linkonce",
4426 sizeof ".gnu.linkonce" - 1) == 0)
4432 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
4433 linker to handle them specially, such as generating jalx instructions
4434 when needed. We also make them odd for the duration of the assembly,
4435 in order to generate the right sort of code. We will make them even
4436 in the adjust_symtab routine, while leaving them marked. This is
4437 convenient for the debugger and the disassembler. The linker knows
4438 to make them odd again. */
4441 mips_compressed_mark_label (symbolS *label)
4443 gas_assert (HAVE_CODE_COMPRESSION);
4445 if (mips_opts.mips16)
4446 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
4448 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
4449 if ((S_GET_VALUE (label) & 1) == 0
4450 /* Don't adjust the address if the label is global or weak, or
4451 in a link-once section, since we'll be emitting symbol reloc
4452 references to it which will be patched up by the linker, and
4453 the final value of the symbol may or may not be MIPS16/microMIPS. */
4454 && !S_IS_WEAK (label)
4455 && !S_IS_EXTERNAL (label)
4456 && !s_is_linkonce (label, now_seg))
4457 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
4460 /* Mark preceding MIPS16 or microMIPS instruction labels. */
4463 mips_compressed_mark_labels (void)
4465 struct insn_label_list *l;
4467 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next)
4468 mips_compressed_mark_label (l->label);
4471 /* End the current frag. Make it a variant frag and record the
4475 relax_close_frag (void)
4477 mips_macro_warning.first_frag = frag_now;
4478 frag_var (rs_machine_dependent, 0, 0,
4479 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1],
4480 mips_pic != NO_PIC),
4481 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
4483 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
4484 mips_relax.first_fixup = 0;
4487 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
4488 See the comment above RELAX_ENCODE for more details. */
4491 relax_start (symbolS *symbol)
4493 gas_assert (mips_relax.sequence == 0);
4494 mips_relax.sequence = 1;
4495 mips_relax.symbol = symbol;
4498 /* Start generating the second version of a relaxable sequence.
4499 See the comment above RELAX_ENCODE for more details. */
4504 gas_assert (mips_relax.sequence == 1);
4505 mips_relax.sequence = 2;
4508 /* End the current relaxable sequence. */
4513 gas_assert (mips_relax.sequence == 2);
4514 relax_close_frag ();
4515 mips_relax.sequence = 0;
4518 /* Return true if IP is a delayed branch or jump. */
4520 static inline bfd_boolean
4521 delayed_branch_p (const struct mips_cl_insn *ip)
4523 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
4524 | INSN_COND_BRANCH_DELAY
4525 | INSN_COND_BRANCH_LIKELY)) != 0;
4528 /* Return true if IP is a compact branch or jump. */
4530 static inline bfd_boolean
4531 compact_branch_p (const struct mips_cl_insn *ip)
4533 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
4534 | INSN2_COND_BRANCH)) != 0;
4537 /* Return true if IP is an unconditional branch or jump. */
4539 static inline bfd_boolean
4540 uncond_branch_p (const struct mips_cl_insn *ip)
4542 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
4543 || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0);
4546 /* Return true if IP is a branch-likely instruction. */
4548 static inline bfd_boolean
4549 branch_likely_p (const struct mips_cl_insn *ip)
4551 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
4554 /* Return the type of nop that should be used to fill the delay slot
4555 of delayed branch IP. */
4557 static struct mips_cl_insn *
4558 get_delay_slot_nop (const struct mips_cl_insn *ip)
4560 if (mips_opts.micromips
4561 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
4562 return µmips_nop32_insn;
4566 /* Return a mask that has bit N set if OPCODE reads the register(s)
4570 insn_read_mask (const struct mips_opcode *opcode)
4572 return (opcode->pinfo & INSN_READ_ALL) >> INSN_READ_SHIFT;
4575 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4579 insn_write_mask (const struct mips_opcode *opcode)
4581 return (opcode->pinfo & INSN_WRITE_ALL) >> INSN_WRITE_SHIFT;
4584 /* Return a mask of the registers specified by operand OPERAND of INSN.
4585 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4589 operand_reg_mask (const struct mips_cl_insn *insn,
4590 const struct mips_operand *operand,
4591 unsigned int type_mask)
4593 unsigned int uval, vsel;
4595 switch (operand->type)
4602 case OP_ADDIUSP_INT:
4603 case OP_ENTRY_EXIT_LIST:
4604 case OP_REPEAT_DEST_REG:
4605 case OP_REPEAT_PREV_REG:
4608 case OP_VU0_MATCH_SUFFIX:
4616 case OP_OPTIONAL_REG:
4618 const struct mips_reg_operand *reg_op;
4620 reg_op = (const struct mips_reg_operand *) operand;
4621 if (!(type_mask & (1 << reg_op->reg_type)))
4623 uval = insn_extract_operand (insn, operand);
4624 return 1 << mips_decode_reg_operand (reg_op, uval);
4629 const struct mips_reg_pair_operand *pair_op;
4631 pair_op = (const struct mips_reg_pair_operand *) operand;
4632 if (!(type_mask & (1 << pair_op->reg_type)))
4634 uval = insn_extract_operand (insn, operand);
4635 return (1 << pair_op->reg1_map[uval]) | (1 << pair_op->reg2_map[uval]);
4638 case OP_CLO_CLZ_DEST:
4639 if (!(type_mask & (1 << OP_REG_GP)))
4641 uval = insn_extract_operand (insn, operand);
4642 return (1 << (uval & 31)) | (1 << (uval >> 5));
4645 if (!(type_mask & (1 << OP_REG_GP)))
4647 uval = insn_extract_operand (insn, operand);
4648 gas_assert ((uval & 31) == (uval >> 5));
4649 return 1 << (uval & 31);
4652 case OP_NON_ZERO_REG:
4653 if (!(type_mask & (1 << OP_REG_GP)))
4655 uval = insn_extract_operand (insn, operand);
4656 return 1 << (uval & 31);
4658 case OP_LWM_SWM_LIST:
4661 case OP_SAVE_RESTORE_LIST:
4664 case OP_MDMX_IMM_REG:
4665 if (!(type_mask & (1 << OP_REG_VEC)))
4667 uval = insn_extract_operand (insn, operand);
4669 if ((vsel & 0x18) == 0x18)
4671 return 1 << (uval & 31);
4674 if (!(type_mask & (1 << OP_REG_GP)))
4676 return 1 << insn_extract_operand (insn, operand);
4681 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4682 where bit N of OPNO_MASK is set if operand N should be included.
4683 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4687 insn_reg_mask (const struct mips_cl_insn *insn,
4688 unsigned int type_mask, unsigned int opno_mask)
4690 unsigned int opno, reg_mask;
4694 while (opno_mask != 0)
4697 reg_mask |= operand_reg_mask (insn, insn_opno (insn, opno), type_mask);
4704 /* Return the mask of core registers that IP reads. */
4707 gpr_read_mask (const struct mips_cl_insn *ip)
4709 unsigned long pinfo, pinfo2;
4712 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_read_mask (ip->insn_mo));
4713 pinfo = ip->insn_mo->pinfo;
4714 pinfo2 = ip->insn_mo->pinfo2;
4715 if (pinfo & INSN_UDI)
4717 /* UDI instructions have traditionally been assumed to read RS
4719 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
4720 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
4722 if (pinfo & INSN_READ_GPR_24)
4724 if (pinfo2 & INSN2_READ_GPR_16)
4726 if (pinfo2 & INSN2_READ_SP)
4728 if (pinfo2 & INSN2_READ_GPR_31)
4730 /* Don't include register 0. */
4734 /* Return the mask of core registers that IP writes. */
4737 gpr_write_mask (const struct mips_cl_insn *ip)
4739 unsigned long pinfo, pinfo2;
4742 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_write_mask (ip->insn_mo));
4743 pinfo = ip->insn_mo->pinfo;
4744 pinfo2 = ip->insn_mo->pinfo2;
4745 if (pinfo & INSN_WRITE_GPR_24)
4747 if (pinfo & INSN_WRITE_GPR_31)
4749 if (pinfo & INSN_UDI)
4750 /* UDI instructions have traditionally been assumed to write to RD. */
4751 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
4752 if (pinfo2 & INSN2_WRITE_SP)
4754 /* Don't include register 0. */
4758 /* Return the mask of floating-point registers that IP reads. */
4761 fpr_read_mask (const struct mips_cl_insn *ip)
4763 unsigned long pinfo;
4766 mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC)
4767 | (1 << OP_REG_MSA)),
4768 insn_read_mask (ip->insn_mo));
4769 pinfo = ip->insn_mo->pinfo;
4770 /* Conservatively treat all operands to an FP_D instruction are doubles.
4771 (This is overly pessimistic for things like cvt.d.s.) */
4772 if (FPR_SIZE != 64 && (pinfo & FP_D))
4777 /* Return the mask of floating-point registers that IP writes. */
4780 fpr_write_mask (const struct mips_cl_insn *ip)
4782 unsigned long pinfo;
4785 mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC)
4786 | (1 << OP_REG_MSA)),
4787 insn_write_mask (ip->insn_mo));
4788 pinfo = ip->insn_mo->pinfo;
4789 /* Conservatively treat all operands to an FP_D instruction are doubles.
4790 (This is overly pessimistic for things like cvt.s.d.) */
4791 if (FPR_SIZE != 64 && (pinfo & FP_D))
4796 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4797 Check whether that is allowed. */
4800 mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum)
4802 const char *s = insn->name;
4803 bfd_boolean oddspreg = (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa, mips_opts.arch)
4805 && mips_opts.oddspreg;
4807 if (insn->pinfo == INSN_MACRO)
4808 /* Let a macro pass, we'll catch it later when it is expanded. */
4811 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4812 otherwise it depends on oddspreg. */
4813 if ((insn->pinfo & FP_S)
4814 && (insn->pinfo & (INSN_LOAD_MEMORY | INSN_STORE_MEMORY
4815 | INSN_LOAD_COPROC | INSN_COPROC_MOVE)))
4816 return FPR_SIZE == 32 || oddspreg;
4818 /* Allow odd registers for single-precision ops and double-precision if the
4819 floating-point registers are 64-bit wide. */
4820 switch (insn->pinfo & (FP_S | FP_D))
4826 return FPR_SIZE == 64;
4831 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4832 s = strchr (insn->name, '.');
4833 if (s != NULL && opnum == 2)
4834 s = strchr (s + 1, '.');
4835 if (s != NULL && (s[1] == 'w' || s[1] == 's'))
4838 return FPR_SIZE == 64;
4841 /* Information about an instruction argument that we're trying to match. */
4842 struct mips_arg_info
4844 /* The instruction so far. */
4845 struct mips_cl_insn *insn;
4847 /* The first unconsumed operand token. */
4848 struct mips_operand_token *token;
4850 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4853 /* The 1-based argument number, for error reporting. This does not
4854 count elided optional registers, etc.. */
4857 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4858 unsigned int last_regno;
4860 /* If the first operand was an OP_REG, this is the register that it
4861 specified, otherwise it is ILLEGAL_REG. */
4862 unsigned int dest_regno;
4864 /* The value of the last OP_INT operand. Only used for OP_MSB,
4865 where it gives the lsb position. */
4866 unsigned int last_op_int;
4868 /* If true, match routines should assume that no later instruction
4869 alternative matches and should therefore be as accommodating as
4870 possible. Match routines should not report errors if something
4871 is only invalid for !LAX_MATCH. */
4872 bfd_boolean lax_match;
4874 /* True if a reference to the current AT register was seen. */
4875 bfd_boolean seen_at;
4878 /* Record that the argument is out of range. */
4881 match_out_of_range (struct mips_arg_info *arg)
4883 set_insn_error_i (arg->argnum, _("operand %d out of range"), arg->argnum);
4886 /* Record that the argument isn't constant but needs to be. */
4889 match_not_constant (struct mips_arg_info *arg)
4891 set_insn_error_i (arg->argnum, _("operand %d must be constant"),
4895 /* Try to match an OT_CHAR token for character CH. Consume the token
4896 and return true on success, otherwise return false. */
4899 match_char (struct mips_arg_info *arg, char ch)
4901 if (arg->token->type == OT_CHAR && arg->token->u.ch == ch)
4911 /* Try to get an expression from the next tokens in ARG. Consume the
4912 tokens and return true on success, storing the expression value in
4913 VALUE and relocation types in R. */
4916 match_expression (struct mips_arg_info *arg, expressionS *value,
4917 bfd_reloc_code_real_type *r)
4919 /* If the next token is a '(' that was parsed as being part of a base
4920 expression, assume we have an elided offset. The later match will fail
4921 if this turns out to be wrong. */
4922 if (arg->token->type == OT_CHAR && arg->token->u.ch == '(')
4924 value->X_op = O_constant;
4925 value->X_add_number = 0;
4926 r[0] = r[1] = r[2] = BFD_RELOC_UNUSED;
4930 /* Reject register-based expressions such as "0+$2" and "(($2))".
4931 For plain registers the default error seems more appropriate. */
4932 if (arg->token->type == OT_INTEGER
4933 && arg->token->u.integer.value.X_op == O_register)
4935 set_insn_error (arg->argnum, _("register value used as expression"));
4939 if (arg->token->type == OT_INTEGER)
4941 *value = arg->token->u.integer.value;
4942 memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r));
4948 (arg->argnum, _("operand %d must be an immediate expression"),
4953 /* Try to get a constant expression from the next tokens in ARG. Consume
4954 the tokens and return true on success, storing the constant value
4958 match_const_int (struct mips_arg_info *arg, offsetT *value)
4961 bfd_reloc_code_real_type r[3];
4963 if (!match_expression (arg, &ex, r))
4966 if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant)
4967 *value = ex.X_add_number;
4970 if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_big)
4971 match_out_of_range (arg);
4973 match_not_constant (arg);
4979 /* Return the RTYPE_* flags for a register operand of type TYPE that
4980 appears in instruction OPCODE. */
4983 convert_reg_type (const struct mips_opcode *opcode,
4984 enum mips_reg_operand_type type)
4989 return RTYPE_NUM | RTYPE_GP;
4992 /* Allow vector register names for MDMX if the instruction is a 64-bit
4993 FPR load, store or move (including moves to and from GPRs). */
4994 if ((mips_opts.ase & ASE_MDMX)
4995 && (opcode->pinfo & FP_D)
4996 && (opcode->pinfo & (INSN_COPROC_MOVE
4997 | INSN_COPROC_MEMORY_DELAY
5000 | INSN_STORE_MEMORY)))
5001 return RTYPE_FPU | RTYPE_VEC;
5005 if (opcode->pinfo & (FP_D | FP_S))
5006 return RTYPE_CCC | RTYPE_FCC;
5010 if (opcode->membership & INSN_5400)
5012 return RTYPE_FPU | RTYPE_VEC;
5018 if (opcode->name[strlen (opcode->name) - 1] == '0')
5019 return RTYPE_NUM | RTYPE_CP0;
5026 return RTYPE_NUM | RTYPE_VI;
5029 return RTYPE_NUM | RTYPE_VF;
5031 case OP_REG_R5900_I:
5032 return RTYPE_R5900_I;
5034 case OP_REG_R5900_Q:
5035 return RTYPE_R5900_Q;
5037 case OP_REG_R5900_R:
5038 return RTYPE_R5900_R;
5040 case OP_REG_R5900_ACC:
5041 return RTYPE_R5900_ACC;
5046 case OP_REG_MSA_CTRL:
5052 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
5055 check_regno (struct mips_arg_info *arg,
5056 enum mips_reg_operand_type type, unsigned int regno)
5058 if (AT && type == OP_REG_GP && regno == AT)
5059 arg->seen_at = TRUE;
5061 if (type == OP_REG_FP
5063 && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum))
5065 /* This was a warning prior to introducing O32 FPXX and FP64 support
5066 so maintain a warning for FP32 but raise an error for the new
5069 as_warn (_("float register should be even, was %d"), regno);
5071 as_bad (_("float register should be even, was %d"), regno);
5074 if (type == OP_REG_CCC)
5079 name = arg->insn->insn_mo->name;
5080 length = strlen (name);
5081 if ((regno & 1) != 0
5082 && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0)
5083 || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0)))
5084 as_warn (_("condition code register should be even for %s, was %d"),
5087 if ((regno & 3) != 0
5088 && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0))
5089 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
5094 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
5095 a register of type TYPE. Return true on success, storing the register
5096 number in *REGNO and warning about any dubious uses. */
5099 match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type,
5100 unsigned int symval, unsigned int *regno)
5102 if (type == OP_REG_VEC)
5103 symval = mips_prefer_vec_regno (symval);
5104 if (!(symval & convert_reg_type (arg->insn->insn_mo, type)))
5107 *regno = symval & RNUM_MASK;
5108 check_regno (arg, type, *regno);
5112 /* Try to interpret the next token in ARG as a register of type TYPE.
5113 Consume the token and return true on success, storing the register
5114 number in *REGNO. Return false on failure. */
5117 match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type,
5118 unsigned int *regno)
5120 if (arg->token->type == OT_REG
5121 && match_regno (arg, type, arg->token->u.regno, regno))
5129 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
5130 Consume the token and return true on success, storing the register numbers
5131 in *REGNO1 and *REGNO2. Return false on failure. */
5134 match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type,
5135 unsigned int *regno1, unsigned int *regno2)
5137 if (match_reg (arg, type, regno1))
5142 if (arg->token->type == OT_REG_RANGE
5143 && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1)
5144 && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2)
5145 && *regno1 <= *regno2)
5153 /* OP_INT matcher. */
5156 match_int_operand (struct mips_arg_info *arg,
5157 const struct mips_operand *operand_base)
5159 const struct mips_int_operand *operand;
5161 int min_val, max_val, factor;
5164 operand = (const struct mips_int_operand *) operand_base;
5165 factor = 1 << operand->shift;
5166 min_val = mips_int_operand_min (operand);
5167 max_val = mips_int_operand_max (operand);
5169 if (operand_base->lsb == 0
5170 && operand_base->size == 16
5171 && operand->shift == 0
5172 && operand->bias == 0
5173 && (operand->max_val == 32767 || operand->max_val == 65535))
5175 /* The operand can be relocated. */
5176 if (!match_expression (arg, &offset_expr, offset_reloc))
5179 if (offset_expr.X_op == O_big)
5181 match_out_of_range (arg);
5185 if (offset_reloc[0] != BFD_RELOC_UNUSED)
5186 /* Relocation operators were used. Accept the argument and
5187 leave the relocation value in offset_expr and offset_relocs
5188 for the caller to process. */
5191 if (offset_expr.X_op != O_constant)
5193 /* Accept non-constant operands if no later alternative matches,
5194 leaving it for the caller to process. */
5195 if (!arg->lax_match)
5197 match_not_constant (arg);
5200 offset_reloc[0] = BFD_RELOC_LO16;
5204 /* Clear the global state; we're going to install the operand
5206 sval = offset_expr.X_add_number;
5207 offset_expr.X_op = O_absent;
5209 /* For compatibility with older assemblers, we accept
5210 0x8000-0xffff as signed 16-bit numbers when only
5211 signed numbers are allowed. */
5214 max_val = ((1 << operand_base->size) - 1) << operand->shift;
5215 if (!arg->lax_match && sval <= max_val)
5217 match_out_of_range (arg);
5224 if (!match_const_int (arg, &sval))
5228 arg->last_op_int = sval;
5230 if (sval < min_val || sval > max_val || sval % factor)
5232 match_out_of_range (arg);
5236 uval = (unsigned int) sval >> operand->shift;
5237 uval -= operand->bias;
5239 /* Handle -mfix-cn63xxp1. */
5241 && mips_fix_cn63xxp1
5242 && !mips_opts.micromips
5243 && strcmp ("pref", arg->insn->insn_mo->name) == 0)
5258 /* The rest must be changed to 28. */
5263 insn_insert_operand (arg->insn, operand_base, uval);
5267 /* OP_MAPPED_INT matcher. */
5270 match_mapped_int_operand (struct mips_arg_info *arg,
5271 const struct mips_operand *operand_base)
5273 const struct mips_mapped_int_operand *operand;
5274 unsigned int uval, num_vals;
5277 operand = (const struct mips_mapped_int_operand *) operand_base;
5278 if (!match_const_int (arg, &sval))
5281 num_vals = 1 << operand_base->size;
5282 for (uval = 0; uval < num_vals; uval++)
5283 if (operand->int_map[uval] == sval)
5285 if (uval == num_vals)
5287 match_out_of_range (arg);
5291 insn_insert_operand (arg->insn, operand_base, uval);
5295 /* OP_MSB matcher. */
5298 match_msb_operand (struct mips_arg_info *arg,
5299 const struct mips_operand *operand_base)
5301 const struct mips_msb_operand *operand;
5302 int min_val, max_val, max_high;
5303 offsetT size, sval, high;
5305 operand = (const struct mips_msb_operand *) operand_base;
5306 min_val = operand->bias;
5307 max_val = min_val + (1 << operand_base->size) - 1;
5308 max_high = operand->opsize;
5310 if (!match_const_int (arg, &size))
5313 high = size + arg->last_op_int;
5314 sval = operand->add_lsb ? high : size;
5316 if (size < 0 || high > max_high || sval < min_val || sval > max_val)
5318 match_out_of_range (arg);
5321 insn_insert_operand (arg->insn, operand_base, sval - min_val);
5325 /* OP_REG matcher. */
5328 match_reg_operand (struct mips_arg_info *arg,
5329 const struct mips_operand *operand_base)
5331 const struct mips_reg_operand *operand;
5332 unsigned int regno, uval, num_vals;
5334 operand = (const struct mips_reg_operand *) operand_base;
5335 if (!match_reg (arg, operand->reg_type, ®no))
5338 if (operand->reg_map)
5340 num_vals = 1 << operand->root.size;
5341 for (uval = 0; uval < num_vals; uval++)
5342 if (operand->reg_map[uval] == regno)
5344 if (num_vals == uval)
5350 arg->last_regno = regno;
5351 if (arg->opnum == 1)
5352 arg->dest_regno = regno;
5353 insn_insert_operand (arg->insn, operand_base, uval);
5357 /* OP_REG_PAIR matcher. */
5360 match_reg_pair_operand (struct mips_arg_info *arg,
5361 const struct mips_operand *operand_base)
5363 const struct mips_reg_pair_operand *operand;
5364 unsigned int regno1, regno2, uval, num_vals;
5366 operand = (const struct mips_reg_pair_operand *) operand_base;
5367 if (!match_reg (arg, operand->reg_type, ®no1)
5368 || !match_char (arg, ',')
5369 || !match_reg (arg, operand->reg_type, ®no2))
5372 num_vals = 1 << operand_base->size;
5373 for (uval = 0; uval < num_vals; uval++)
5374 if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2)
5376 if (uval == num_vals)
5379 insn_insert_operand (arg->insn, operand_base, uval);
5383 /* OP_PCREL matcher. The caller chooses the relocation type. */
5386 match_pcrel_operand (struct mips_arg_info *arg)
5388 bfd_reloc_code_real_type r[3];
5390 return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED;
5393 /* OP_PERF_REG matcher. */
5396 match_perf_reg_operand (struct mips_arg_info *arg,
5397 const struct mips_operand *operand)
5401 if (!match_const_int (arg, &sval))
5406 || (mips_opts.arch == CPU_R5900
5407 && (strcmp (arg->insn->insn_mo->name, "mfps") == 0
5408 || strcmp (arg->insn->insn_mo->name, "mtps") == 0))))
5410 set_insn_error (arg->argnum, _("invalid performance register"));
5414 insn_insert_operand (arg->insn, operand, sval);
5418 /* OP_ADDIUSP matcher. */
5421 match_addiusp_operand (struct mips_arg_info *arg,
5422 const struct mips_operand *operand)
5427 if (!match_const_int (arg, &sval))
5432 match_out_of_range (arg);
5437 if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1))
5439 match_out_of_range (arg);
5443 uval = (unsigned int) sval;
5444 uval = ((uval >> 1) & ~0xff) | (uval & 0xff);
5445 insn_insert_operand (arg->insn, operand, uval);
5449 /* OP_CLO_CLZ_DEST matcher. */
5452 match_clo_clz_dest_operand (struct mips_arg_info *arg,
5453 const struct mips_operand *operand)
5457 if (!match_reg (arg, OP_REG_GP, ®no))
5460 insn_insert_operand (arg->insn, operand, regno | (regno << 5));
5464 /* OP_CHECK_PREV matcher. */
5467 match_check_prev_operand (struct mips_arg_info *arg,
5468 const struct mips_operand *operand_base)
5470 const struct mips_check_prev_operand *operand;
5473 operand = (const struct mips_check_prev_operand *) operand_base;
5475 if (!match_reg (arg, OP_REG_GP, ®no))
5478 if (!operand->zero_ok && regno == 0)
5481 if ((operand->less_than_ok && regno < arg->last_regno)
5482 || (operand->greater_than_ok && regno > arg->last_regno)
5483 || (operand->equal_ok && regno == arg->last_regno))
5485 arg->last_regno = regno;
5486 insn_insert_operand (arg->insn, operand_base, regno);
5493 /* OP_SAME_RS_RT matcher. */
5496 match_same_rs_rt_operand (struct mips_arg_info *arg,
5497 const struct mips_operand *operand)
5501 if (!match_reg (arg, OP_REG_GP, ®no))
5506 set_insn_error (arg->argnum, _("the source register must not be $0"));
5510 arg->last_regno = regno;
5512 insn_insert_operand (arg->insn, operand, regno | (regno << 5));
5516 /* OP_LWM_SWM_LIST matcher. */
5519 match_lwm_swm_list_operand (struct mips_arg_info *arg,
5520 const struct mips_operand *operand)
5522 unsigned int reglist, sregs, ra, regno1, regno2;
5523 struct mips_arg_info reset;
5526 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
5530 if (regno2 == FP && regno1 >= S0 && regno1 <= S7)
5535 reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1);
5538 while (match_char (arg, ',')
5539 && match_reg_range (arg, OP_REG_GP, ®no1, ®no2));
5542 if (operand->size == 2)
5544 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5550 and any permutations of these. */
5551 if ((reglist & 0xfff1ffff) != 0x80010000)
5554 sregs = (reglist >> 17) & 7;
5559 /* The list must include at least one of ra and s0-sN,
5560 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5561 which are $23 and $30 respectively.) E.g.:
5569 and any permutations of these. */
5570 if ((reglist & 0x3f00ffff) != 0)
5573 ra = (reglist >> 27) & 0x10;
5574 sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
5577 if ((sregs & -sregs) != sregs)
5580 insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra);
5584 /* OP_ENTRY_EXIT_LIST matcher. */
5587 match_entry_exit_operand (struct mips_arg_info *arg,
5588 const struct mips_operand *operand)
5591 bfd_boolean is_exit;
5593 /* The format is the same for both ENTRY and EXIT, but the constraints
5595 is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0;
5596 mask = (is_exit ? 7 << 3 : 0);
5599 unsigned int regno1, regno2;
5600 bfd_boolean is_freg;
5602 if (match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
5604 else if (match_reg_range (arg, OP_REG_FP, ®no1, ®no2))
5609 if (is_exit && is_freg && regno1 == 0 && regno2 < 2)
5612 mask |= (5 + regno2) << 3;
5614 else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7)
5615 mask |= (regno2 - 3) << 3;
5616 else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17)
5617 mask |= (regno2 - 15) << 1;
5618 else if (regno1 == RA && regno2 == RA)
5623 while (match_char (arg, ','));
5625 insn_insert_operand (arg->insn, operand, mask);
5629 /* Encode regular MIPS SAVE/RESTORE instruction operands according to
5630 the argument register mask AMASK, the number of static registers
5631 saved NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5632 respectively, and the frame size FRAME_SIZE. */
5635 mips_encode_save_restore (unsigned int amask, unsigned int nsreg,
5636 unsigned int ra, unsigned int s0, unsigned int s1,
5637 unsigned int frame_size)
5639 return ((nsreg << 23) | ((frame_size & 0xf0) << 15) | (amask << 15)
5640 | (ra << 12) | (s0 << 11) | (s1 << 10) | ((frame_size & 0xf) << 6));
5643 /* Encode MIPS16 SAVE/RESTORE instruction operands according to the
5644 argument register mask AMASK, the number of static registers saved
5645 NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5646 respectively, and the frame size FRAME_SIZE. */
5649 mips16_encode_save_restore (unsigned int amask, unsigned int nsreg,
5650 unsigned int ra, unsigned int s0, unsigned int s1,
5651 unsigned int frame_size)
5655 args = (ra << 6) | (s0 << 5) | (s1 << 4) | (frame_size & 0xf);
5656 if (nsreg || amask || frame_size == 0 || frame_size > 16)
5657 args |= (MIPS16_EXTEND | (nsreg << 24) | (amask << 16)
5658 | ((frame_size & 0xf0) << 16));
5662 /* OP_SAVE_RESTORE_LIST matcher. */
5665 match_save_restore_list_operand (struct mips_arg_info *arg)
5667 unsigned int opcode, args, statics, sregs;
5668 unsigned int num_frame_sizes, num_args, num_statics, num_sregs;
5669 unsigned int arg_mask, ra, s0, s1;
5672 opcode = arg->insn->insn_opcode;
5674 num_frame_sizes = 0;
5683 unsigned int regno1, regno2;
5685 if (arg->token->type == OT_INTEGER)
5687 /* Handle the frame size. */
5688 if (!match_const_int (arg, &frame_size))
5690 num_frame_sizes += 1;
5694 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
5697 while (regno1 <= regno2)
5699 if (regno1 >= 4 && regno1 <= 7)
5701 if (num_frame_sizes == 0)
5703 args |= 1 << (regno1 - 4);
5705 /* statics $a0-$a3 */
5706 statics |= 1 << (regno1 - 4);
5708 else if (regno1 >= 16 && regno1 <= 23)
5710 sregs |= 1 << (regno1 - 16);
5711 else if (regno1 == 30)
5714 else if (regno1 == 31)
5715 /* Add $ra to insn. */
5725 while (match_char (arg, ','));
5727 /* Encode args/statics combination. */
5730 else if (args == 0xf)
5731 /* All $a0-$a3 are args. */
5732 arg_mask = MIPS_SVRS_ALL_ARGS;
5733 else if (statics == 0xf)
5734 /* All $a0-$a3 are statics. */
5735 arg_mask = MIPS_SVRS_ALL_STATICS;
5738 /* Count arg registers. */
5748 /* Count static registers. */
5750 while (statics & 0x8)
5752 statics = (statics << 1) & 0xf;
5758 /* Encode args/statics. */
5759 arg_mask = (num_args << 2) | num_statics;
5762 /* Encode $s0/$s1. */
5763 if (sregs & (1 << 0)) /* $s0 */
5765 if (sregs & (1 << 1)) /* $s1 */
5769 /* Encode $s2-$s8. */
5779 /* Encode frame size. */
5780 if (num_frame_sizes == 0)
5782 set_insn_error (arg->argnum, _("missing frame size"));
5785 if (num_frame_sizes > 1)
5787 set_insn_error (arg->argnum, _("frame size specified twice"));
5790 if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8)
5792 set_insn_error (arg->argnum, _("invalid frame size"));
5797 /* Finally build the instruction. */
5798 if (mips_opts.mips16)
5799 opcode |= mips16_encode_save_restore (arg_mask, num_sregs, ra, s0, s1,
5801 else if (!mips_opts.micromips)
5802 opcode |= mips_encode_save_restore (arg_mask, num_sregs, ra, s0, s1,
5807 arg->insn->insn_opcode = opcode;
5811 /* OP_MDMX_IMM_REG matcher. */
5814 match_mdmx_imm_reg_operand (struct mips_arg_info *arg,
5815 const struct mips_operand *operand)
5817 unsigned int regno, uval;
5819 const struct mips_opcode *opcode;
5821 /* The mips_opcode records whether this is an octobyte or quadhalf
5822 instruction. Start out with that bit in place. */
5823 opcode = arg->insn->insn_mo;
5824 uval = mips_extract_operand (operand, opcode->match);
5825 is_qh = (uval != 0);
5827 if (arg->token->type == OT_REG)
5829 if ((opcode->membership & INSN_5400)
5830 && strcmp (opcode->name, "rzu.ob") == 0)
5832 set_insn_error_i (arg->argnum, _("operand %d must be an immediate"),
5837 if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no))
5841 /* Check whether this is a vector register or a broadcast of
5842 a single element. */
5843 if (arg->token->type == OT_INTEGER_INDEX)
5845 if (arg->token->u.index > (is_qh ? 3 : 7))
5847 set_insn_error (arg->argnum, _("invalid element selector"));
5850 uval |= arg->token->u.index << (is_qh ? 2 : 1) << 5;
5855 /* A full vector. */
5856 if ((opcode->membership & INSN_5400)
5857 && (strcmp (opcode->name, "sll.ob") == 0
5858 || strcmp (opcode->name, "srl.ob") == 0))
5860 set_insn_error_i (arg->argnum, _("operand %d must be scalar"),
5866 uval |= MDMX_FMTSEL_VEC_QH << 5;
5868 uval |= MDMX_FMTSEL_VEC_OB << 5;
5876 if (!match_const_int (arg, &sval))
5878 if (sval < 0 || sval > 31)
5880 match_out_of_range (arg);
5883 uval |= (sval & 31);
5885 uval |= MDMX_FMTSEL_IMM_QH << 5;
5887 uval |= MDMX_FMTSEL_IMM_OB << 5;
5889 insn_insert_operand (arg->insn, operand, uval);
5893 /* OP_IMM_INDEX matcher. */
5896 match_imm_index_operand (struct mips_arg_info *arg,
5897 const struct mips_operand *operand)
5899 unsigned int max_val;
5901 if (arg->token->type != OT_INTEGER_INDEX)
5904 max_val = (1 << operand->size) - 1;
5905 if (arg->token->u.index > max_val)
5907 match_out_of_range (arg);
5910 insn_insert_operand (arg->insn, operand, arg->token->u.index);
5915 /* OP_REG_INDEX matcher. */
5918 match_reg_index_operand (struct mips_arg_info *arg,
5919 const struct mips_operand *operand)
5923 if (arg->token->type != OT_REG_INDEX)
5926 if (!match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no))
5929 insn_insert_operand (arg->insn, operand, regno);
5934 /* OP_PC matcher. */
5937 match_pc_operand (struct mips_arg_info *arg)
5939 if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC))
5947 /* OP_REG28 matcher. */
5950 match_reg28_operand (struct mips_arg_info *arg)
5954 if (arg->token->type == OT_REG
5955 && match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no)
5964 /* OP_NON_ZERO_REG matcher. */
5967 match_non_zero_reg_operand (struct mips_arg_info *arg,
5968 const struct mips_operand *operand)
5972 if (!match_reg (arg, OP_REG_GP, ®no))
5978 arg->last_regno = regno;
5979 insn_insert_operand (arg->insn, operand, regno);
5983 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5984 register that we need to match. */
5987 match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno)
5991 return match_reg (arg, OP_REG_GP, ®no) && regno == other_regno;
5994 /* Try to match a floating-point constant from ARG for LI.S or LI.D.
5995 LENGTH is the length of the value in bytes (4 for float, 8 for double)
5996 and USING_GPRS says whether the destination is a GPR rather than an FPR.
5998 Return the constant in IMM and OFFSET as follows:
6000 - If the constant should be loaded via memory, set IMM to O_absent and
6001 OFFSET to the memory address.
6003 - Otherwise, if the constant should be loaded into two 32-bit registers,
6004 set IMM to the O_constant to load into the high register and OFFSET
6005 to the corresponding value for the low register.
6007 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
6009 These constants only appear as the last operand in an instruction,
6010 and every instruction that accepts them in any variant accepts them
6011 in all variants. This means we don't have to worry about backing out
6012 any changes if the instruction does not match. We just match
6013 unconditionally and report an error if the constant is invalid. */
6016 match_float_constant (struct mips_arg_info *arg, expressionS *imm,
6017 expressionS *offset, int length, bfd_boolean using_gprs)
6022 const char *newname;
6023 unsigned char *data;
6025 /* Where the constant is placed is based on how the MIPS assembler
6028 length == 4 && using_gprs -- immediate value only
6029 length == 8 && using_gprs -- .rdata or immediate value
6030 length == 4 && !using_gprs -- .lit4 or immediate value
6031 length == 8 && !using_gprs -- .lit8 or immediate value
6033 The .lit4 and .lit8 sections are only used if permitted by the
6035 if (arg->token->type != OT_FLOAT)
6037 set_insn_error (arg->argnum, _("floating-point expression required"));
6041 gas_assert (arg->token->u.flt.length == length);
6042 data = arg->token->u.flt.data;
6045 /* Handle 32-bit constants for which an immediate value is best. */
6048 || g_switch_value < 4
6049 || (data[0] == 0 && data[1] == 0)
6050 || (data[2] == 0 && data[3] == 0)))
6052 imm->X_op = O_constant;
6053 if (!target_big_endian)
6054 imm->X_add_number = bfd_getl32 (data);
6056 imm->X_add_number = bfd_getb32 (data);
6057 offset->X_op = O_absent;
6061 /* Handle 64-bit constants for which an immediate value is best. */
6063 && !mips_disable_float_construction
6064 /* Constants can only be constructed in GPRs and copied to FPRs if the
6065 GPRs are at least as wide as the FPRs or MTHC1 is available.
6066 Unlike most tests for 32-bit floating-point registers this check
6067 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
6068 permit 64-bit moves without MXHC1.
6069 Force the constant into memory otherwise. */
6072 || ISA_HAS_MXHC1 (mips_opts.isa)
6074 && ((data[0] == 0 && data[1] == 0)
6075 || (data[2] == 0 && data[3] == 0))
6076 && ((data[4] == 0 && data[5] == 0)
6077 || (data[6] == 0 && data[7] == 0)))
6079 /* The value is simple enough to load with a couple of instructions.
6080 If using 32-bit registers, set IMM to the high order 32 bits and
6081 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
6083 if (GPR_SIZE == 32 || (!using_gprs && FPR_SIZE != 64))
6085 imm->X_op = O_constant;
6086 offset->X_op = O_constant;
6087 if (!target_big_endian)
6089 imm->X_add_number = bfd_getl32 (data + 4);
6090 offset->X_add_number = bfd_getl32 (data);
6094 imm->X_add_number = bfd_getb32 (data);
6095 offset->X_add_number = bfd_getb32 (data + 4);
6097 if (offset->X_add_number == 0)
6098 offset->X_op = O_absent;
6102 imm->X_op = O_constant;
6103 if (!target_big_endian)
6104 imm->X_add_number = bfd_getl64 (data);
6106 imm->X_add_number = bfd_getb64 (data);
6107 offset->X_op = O_absent;
6112 /* Switch to the right section. */
6114 subseg = now_subseg;
6117 gas_assert (!using_gprs && g_switch_value >= 4);
6122 if (using_gprs || g_switch_value < 8)
6123 newname = RDATA_SECTION_NAME;
6128 new_seg = subseg_new (newname, (subsegT) 0);
6129 bfd_set_section_flags (stdoutput, new_seg,
6130 SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA);
6131 frag_align (length == 4 ? 2 : 3, 0, 0);
6132 if (strncmp (TARGET_OS, "elf", 3) != 0)
6133 record_alignment (new_seg, 4);
6135 record_alignment (new_seg, length == 4 ? 2 : 3);
6137 as_bad (_("cannot use `%s' in this section"), arg->insn->insn_mo->name);
6139 /* Set the argument to the current address in the section. */
6140 imm->X_op = O_absent;
6141 offset->X_op = O_symbol;
6142 offset->X_add_symbol = symbol_temp_new_now ();
6143 offset->X_add_number = 0;
6145 /* Put the floating point number into the section. */
6146 p = frag_more (length);
6147 memcpy (p, data, length);
6149 /* Switch back to the original section. */
6150 subseg_set (seg, subseg);
6154 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
6158 match_vu0_suffix_operand (struct mips_arg_info *arg,
6159 const struct mips_operand *operand,
6160 bfd_boolean match_p)
6164 /* The operand can be an XYZW mask or a single 2-bit channel index
6165 (with X being 0). */
6166 gas_assert (operand->size == 2 || operand->size == 4);
6168 /* The suffix can be omitted when it is already part of the opcode. */
6169 if (arg->token->type != OT_CHANNELS)
6172 uval = arg->token->u.channels;
6173 if (operand->size == 2)
6175 /* Check that a single bit is set and convert it into a 2-bit index. */
6176 if ((uval & -uval) != uval)
6178 uval = 4 - ffs (uval);
6181 if (match_p && insn_extract_operand (arg->insn, operand) != uval)
6186 insn_insert_operand (arg->insn, operand, uval);
6190 /* Try to match a token from ARG against OPERAND. Consume the token
6191 and return true on success, otherwise return false. */
6194 match_operand (struct mips_arg_info *arg,
6195 const struct mips_operand *operand)
6197 switch (operand->type)
6200 return match_int_operand (arg, operand);
6203 return match_mapped_int_operand (arg, operand);
6206 return match_msb_operand (arg, operand);
6209 case OP_OPTIONAL_REG:
6210 return match_reg_operand (arg, operand);
6213 return match_reg_pair_operand (arg, operand);
6216 return match_pcrel_operand (arg);
6219 return match_perf_reg_operand (arg, operand);
6221 case OP_ADDIUSP_INT:
6222 return match_addiusp_operand (arg, operand);
6224 case OP_CLO_CLZ_DEST:
6225 return match_clo_clz_dest_operand (arg, operand);
6227 case OP_LWM_SWM_LIST:
6228 return match_lwm_swm_list_operand (arg, operand);
6230 case OP_ENTRY_EXIT_LIST:
6231 return match_entry_exit_operand (arg, operand);
6233 case OP_SAVE_RESTORE_LIST:
6234 return match_save_restore_list_operand (arg);
6236 case OP_MDMX_IMM_REG:
6237 return match_mdmx_imm_reg_operand (arg, operand);
6239 case OP_REPEAT_DEST_REG:
6240 return match_tied_reg_operand (arg, arg->dest_regno);
6242 case OP_REPEAT_PREV_REG:
6243 return match_tied_reg_operand (arg, arg->last_regno);
6246 return match_pc_operand (arg);
6249 return match_reg28_operand (arg);
6252 return match_vu0_suffix_operand (arg, operand, FALSE);
6254 case OP_VU0_MATCH_SUFFIX:
6255 return match_vu0_suffix_operand (arg, operand, TRUE);
6258 return match_imm_index_operand (arg, operand);
6261 return match_reg_index_operand (arg, operand);
6264 return match_same_rs_rt_operand (arg, operand);
6267 return match_check_prev_operand (arg, operand);
6269 case OP_NON_ZERO_REG:
6270 return match_non_zero_reg_operand (arg, operand);
6275 /* ARG is the state after successfully matching an instruction.
6276 Issue any queued-up warnings. */
6279 check_completed_insn (struct mips_arg_info *arg)
6284 as_warn (_("used $at without \".set noat\""));
6286 as_warn (_("used $%u with \".set at=$%u\""), AT, AT);
6290 /* Return true if modifying general-purpose register REG needs a delay. */
6293 reg_needs_delay (unsigned int reg)
6295 unsigned long prev_pinfo;
6297 prev_pinfo = history[0].insn_mo->pinfo;
6298 if (!mips_opts.noreorder
6299 && (((prev_pinfo & INSN_LOAD_MEMORY) && !gpr_interlocks)
6300 || ((prev_pinfo & INSN_LOAD_COPROC) && !cop_interlocks))
6301 && (gpr_write_mask (&history[0]) & (1 << reg)))
6307 /* Classify an instruction according to the FIX_VR4120_* enumeration.
6308 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6309 by VR4120 errata. */
6312 classify_vr4120_insn (const char *name)
6314 if (strncmp (name, "macc", 4) == 0)
6315 return FIX_VR4120_MACC;
6316 if (strncmp (name, "dmacc", 5) == 0)
6317 return FIX_VR4120_DMACC;
6318 if (strncmp (name, "mult", 4) == 0)
6319 return FIX_VR4120_MULT;
6320 if (strncmp (name, "dmult", 5) == 0)
6321 return FIX_VR4120_DMULT;
6322 if (strstr (name, "div"))
6323 return FIX_VR4120_DIV;
6324 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
6325 return FIX_VR4120_MTHILO;
6326 return NUM_FIX_VR4120_CLASSES;
6329 #define INSN_ERET 0x42000018
6330 #define INSN_DERET 0x4200001f
6331 #define INSN_DMULT 0x1c
6332 #define INSN_DMULTU 0x1d
6334 /* Return the number of instructions that must separate INSN1 and INSN2,
6335 where INSN1 is the earlier instruction. Return the worst-case value
6336 for any INSN2 if INSN2 is null. */
6339 insns_between (const struct mips_cl_insn *insn1,
6340 const struct mips_cl_insn *insn2)
6342 unsigned long pinfo1, pinfo2;
6345 /* If INFO2 is null, pessimistically assume that all flags are set for
6346 the second instruction. */
6347 pinfo1 = insn1->insn_mo->pinfo;
6348 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
6350 /* For most targets, write-after-read dependencies on the HI and LO
6351 registers must be separated by at least two instructions. */
6352 if (!hilo_interlocks)
6354 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
6356 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
6360 /* If we're working around r7000 errata, there must be two instructions
6361 between an mfhi or mflo and any instruction that uses the result. */
6362 if (mips_7000_hilo_fix
6363 && !mips_opts.micromips
6364 && MF_HILO_INSN (pinfo1)
6365 && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))))
6368 /* If we're working around 24K errata, one instruction is required
6369 if an ERET or DERET is followed by a branch instruction. */
6370 if (mips_fix_24k && !mips_opts.micromips)
6372 if (insn1->insn_opcode == INSN_ERET
6373 || insn1->insn_opcode == INSN_DERET)
6376 || insn2->insn_opcode == INSN_ERET
6377 || insn2->insn_opcode == INSN_DERET
6378 || delayed_branch_p (insn2))
6383 /* If we're working around PMC RM7000 errata, there must be three
6384 nops between a dmult and a load instruction. */
6385 if (mips_fix_rm7000 && !mips_opts.micromips)
6387 if ((insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULT
6388 || (insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULTU)
6390 if (pinfo2 & INSN_LOAD_MEMORY)
6395 /* If working around VR4120 errata, check for combinations that need
6396 a single intervening instruction. */
6397 if (mips_fix_vr4120 && !mips_opts.micromips)
6399 unsigned int class1, class2;
6401 class1 = classify_vr4120_insn (insn1->insn_mo->name);
6402 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
6406 class2 = classify_vr4120_insn (insn2->insn_mo->name);
6407 if (vr4120_conflicts[class1] & (1 << class2))
6412 if (!HAVE_CODE_COMPRESSION)
6414 /* Check for GPR or coprocessor load delays. All such delays
6415 are on the RT register. */
6416 /* Itbl support may require additional care here. */
6417 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY))
6418 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC)))
6420 if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))
6424 /* Check for generic coprocessor hazards.
6426 This case is not handled very well. There is no special
6427 knowledge of CP0 handling, and the coprocessors other than
6428 the floating point unit are not distinguished at all. */
6429 /* Itbl support may require additional care here. FIXME!
6430 Need to modify this to include knowledge about
6431 user specified delays! */
6432 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE))
6433 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
6435 /* Handle cases where INSN1 writes to a known general coprocessor
6436 register. There must be a one instruction delay before INSN2
6437 if INSN2 reads that register, otherwise no delay is needed. */
6438 mask = fpr_write_mask (insn1);
6441 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
6446 /* Read-after-write dependencies on the control registers
6447 require a two-instruction gap. */
6448 if ((pinfo1 & INSN_WRITE_COND_CODE)
6449 && (pinfo2 & INSN_READ_COND_CODE))
6452 /* We don't know exactly what INSN1 does. If INSN2 is
6453 also a coprocessor instruction, assume there must be
6454 a one instruction gap. */
6455 if (pinfo2 & INSN_COP)
6460 /* Check for read-after-write dependencies on the coprocessor
6461 control registers in cases where INSN1 does not need a general
6462 coprocessor delay. This means that INSN1 is a floating point
6463 comparison instruction. */
6464 /* Itbl support may require additional care here. */
6465 else if (!cop_interlocks
6466 && (pinfo1 & INSN_WRITE_COND_CODE)
6467 && (pinfo2 & INSN_READ_COND_CODE))
6471 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6472 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6474 if ((insn1->insn_mo->pinfo2 & INSN2_FORBIDDEN_SLOT)
6475 && ((pinfo2 & INSN_NO_DELAY_SLOT)
6476 || (insn2 && delayed_branch_p (insn2))))
6482 /* Return the number of nops that would be needed to work around the
6483 VR4130 mflo/mfhi errata if instruction INSN immediately followed
6484 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6485 that are contained within the first IGNORE instructions of HIST. */
6488 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
6489 const struct mips_cl_insn *insn)
6494 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6495 are not affected by the errata. */
6497 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
6498 || strcmp (insn->insn_mo->name, "mtlo") == 0
6499 || strcmp (insn->insn_mo->name, "mthi") == 0))
6502 /* Search for the first MFLO or MFHI. */
6503 for (i = 0; i < MAX_VR4130_NOPS; i++)
6504 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
6506 /* Extract the destination register. */
6507 mask = gpr_write_mask (&hist[i]);
6509 /* No nops are needed if INSN reads that register. */
6510 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
6513 /* ...or if any of the intervening instructions do. */
6514 for (j = 0; j < i; j++)
6515 if (gpr_read_mask (&hist[j]) & mask)
6519 return MAX_VR4130_NOPS - i;
6524 #define BASE_REG_EQ(INSN1, INSN2) \
6525 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
6526 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6528 /* Return the minimum alignment for this store instruction. */
6531 fix_24k_align_to (const struct mips_opcode *mo)
6533 if (strcmp (mo->name, "sh") == 0)
6536 if (strcmp (mo->name, "swc1") == 0
6537 || strcmp (mo->name, "swc2") == 0
6538 || strcmp (mo->name, "sw") == 0
6539 || strcmp (mo->name, "sc") == 0
6540 || strcmp (mo->name, "s.s") == 0)
6543 if (strcmp (mo->name, "sdc1") == 0
6544 || strcmp (mo->name, "sdc2") == 0
6545 || strcmp (mo->name, "s.d") == 0)
6552 struct fix_24k_store_info
6554 /* Immediate offset, if any, for this store instruction. */
6556 /* Alignment required by this store instruction. */
6558 /* True for register offsets. */
6559 int register_offset;
6562 /* Comparison function used by qsort. */
6565 fix_24k_sort (const void *a, const void *b)
6567 const struct fix_24k_store_info *pos1 = a;
6568 const struct fix_24k_store_info *pos2 = b;
6570 return (pos1->off - pos2->off);
6573 /* INSN is a store instruction. Try to record the store information
6574 in STINFO. Return false if the information isn't known. */
6577 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
6578 const struct mips_cl_insn *insn)
6580 /* The instruction must have a known offset. */
6581 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
6584 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
6585 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
6589 /* Return the number of nops that would be needed to work around the 24k
6590 "lost data on stores during refill" errata if instruction INSN
6591 immediately followed the 2 instructions described by HIST.
6592 Ignore hazards that are contained within the first IGNORE
6593 instructions of HIST.
6595 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6596 for the data cache refills and store data. The following describes
6597 the scenario where the store data could be lost.
6599 * A data cache miss, due to either a load or a store, causing fill
6600 data to be supplied by the memory subsystem
6601 * The first three doublewords of fill data are returned and written
6603 * A sequence of four stores occurs in consecutive cycles around the
6604 final doubleword of the fill:
6608 * Zero, One or more instructions
6611 The four stores A-D must be to different doublewords of the line that
6612 is being filled. The fourth instruction in the sequence above permits
6613 the fill of the final doubleword to be transferred from the FSB into
6614 the cache. In the sequence above, the stores may be either integer
6615 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6616 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6617 different doublewords on the line. If the floating point unit is
6618 running in 1:2 mode, it is not possible to create the sequence above
6619 using only floating point store instructions.
6621 In this case, the cache line being filled is incorrectly marked
6622 invalid, thereby losing the data from any store to the line that
6623 occurs between the original miss and the completion of the five
6624 cycle sequence shown above.
6626 The workarounds are:
6628 * Run the data cache in write-through mode.
6629 * Insert a non-store instruction between
6630 Store A and Store B or Store B and Store C. */
6633 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
6634 const struct mips_cl_insn *insn)
6636 struct fix_24k_store_info pos[3];
6637 int align, i, base_offset;
6642 /* If the previous instruction wasn't a store, there's nothing to
6644 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
6647 /* If the instructions after the previous one are unknown, we have
6648 to assume the worst. */
6652 /* Check whether we are dealing with three consecutive stores. */
6653 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
6654 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
6657 /* If we don't know the relationship between the store addresses,
6658 assume the worst. */
6659 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
6660 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
6663 if (!fix_24k_record_store_info (&pos[0], insn)
6664 || !fix_24k_record_store_info (&pos[1], &hist[0])
6665 || !fix_24k_record_store_info (&pos[2], &hist[1]))
6668 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
6670 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6671 X bytes and such that the base register + X is known to be aligned
6674 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
6678 align = pos[0].align_to;
6679 base_offset = pos[0].off;
6680 for (i = 1; i < 3; i++)
6681 if (align < pos[i].align_to)
6683 align = pos[i].align_to;
6684 base_offset = pos[i].off;
6686 for (i = 0; i < 3; i++)
6687 pos[i].off -= base_offset;
6690 pos[0].off &= ~align + 1;
6691 pos[1].off &= ~align + 1;
6692 pos[2].off &= ~align + 1;
6694 /* If any two stores write to the same chunk, they also write to the
6695 same doubleword. The offsets are still sorted at this point. */
6696 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
6699 /* A range of at least 9 bytes is needed for the stores to be in
6700 non-overlapping doublewords. */
6701 if (pos[2].off - pos[0].off <= 8)
6704 if (pos[2].off - pos[1].off >= 24
6705 || pos[1].off - pos[0].off >= 24
6706 || pos[2].off - pos[0].off >= 32)
6712 /* Return the number of nops that would be needed if instruction INSN
6713 immediately followed the MAX_NOPS instructions given by HIST,
6714 where HIST[0] is the most recent instruction. Ignore hazards
6715 between INSN and the first IGNORE instructions in HIST.
6717 If INSN is null, return the worse-case number of nops for any
6721 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
6722 const struct mips_cl_insn *insn)
6724 int i, nops, tmp_nops;
6727 for (i = ignore; i < MAX_DELAY_NOPS; i++)
6729 tmp_nops = insns_between (hist + i, insn) - i;
6730 if (tmp_nops > nops)
6734 if (mips_fix_vr4130 && !mips_opts.micromips)
6736 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
6737 if (tmp_nops > nops)
6741 if (mips_fix_24k && !mips_opts.micromips)
6743 tmp_nops = nops_for_24k (ignore, hist, insn);
6744 if (tmp_nops > nops)
6751 /* The variable arguments provide NUM_INSNS extra instructions that
6752 might be added to HIST. Return the largest number of nops that
6753 would be needed after the extended sequence, ignoring hazards
6754 in the first IGNORE instructions. */
6757 nops_for_sequence (int num_insns, int ignore,
6758 const struct mips_cl_insn *hist, ...)
6761 struct mips_cl_insn buffer[MAX_NOPS];
6762 struct mips_cl_insn *cursor;
6765 va_start (args, hist);
6766 cursor = buffer + num_insns;
6767 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
6768 while (cursor > buffer)
6769 *--cursor = *va_arg (args, const struct mips_cl_insn *);
6771 nops = nops_for_insn (ignore, buffer, NULL);
6776 /* Like nops_for_insn, but if INSN is a branch, take into account the
6777 worst-case delay for the branch target. */
6780 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
6781 const struct mips_cl_insn *insn)
6785 nops = nops_for_insn (ignore, hist, insn);
6786 if (delayed_branch_p (insn))
6788 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
6789 hist, insn, get_delay_slot_nop (insn));
6790 if (tmp_nops > nops)
6793 else if (compact_branch_p (insn))
6795 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
6796 if (tmp_nops > nops)
6802 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6805 fix_loongson2f_nop (struct mips_cl_insn * ip)
6807 gas_assert (!HAVE_CODE_COMPRESSION);
6808 if (strcmp (ip->insn_mo->name, "nop") == 0)
6809 ip->insn_opcode = LOONGSON2F_NOP_INSN;
6812 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6813 jr target pc &= 'hffff_ffff_cfff_ffff. */
6816 fix_loongson2f_jump (struct mips_cl_insn * ip)
6818 gas_assert (!HAVE_CODE_COMPRESSION);
6819 if (strcmp (ip->insn_mo->name, "j") == 0
6820 || strcmp (ip->insn_mo->name, "jr") == 0
6821 || strcmp (ip->insn_mo->name, "jalr") == 0)
6829 sreg = EXTRACT_OPERAND (0, RS, *ip);
6830 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
6833 ep.X_op = O_constant;
6834 ep.X_add_number = 0xcfff0000;
6835 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
6836 ep.X_add_number = 0xffff;
6837 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
6838 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
6843 fix_loongson2f (struct mips_cl_insn * ip)
6845 if (mips_fix_loongson2f_nop)
6846 fix_loongson2f_nop (ip);
6848 if (mips_fix_loongson2f_jump)
6849 fix_loongson2f_jump (ip);
6852 /* IP is a branch that has a delay slot, and we need to fill it
6853 automatically. Return true if we can do that by swapping IP
6854 with the previous instruction.
6855 ADDRESS_EXPR is an operand of the instruction to be used with
6859 can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
6860 bfd_reloc_code_real_type *reloc_type)
6862 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
6863 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
6864 unsigned int fpr_read, prev_fpr_write;
6866 /* -O2 and above is required for this optimization. */
6867 if (mips_optimize < 2)
6870 /* If we have seen .set volatile or .set nomove, don't optimize. */
6871 if (mips_opts.nomove)
6874 /* We can't swap if the previous instruction's position is fixed. */
6875 if (history[0].fixed_p)
6878 /* If the previous previous insn was in a .set noreorder, we can't
6879 swap. Actually, the MIPS assembler will swap in this situation.
6880 However, gcc configured -with-gnu-as will generate code like
6888 in which we can not swap the bne and INSN. If gcc is not configured
6889 -with-gnu-as, it does not output the .set pseudo-ops. */
6890 if (history[1].noreorder_p)
6893 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6894 This means that the previous instruction was a 4-byte one anyhow. */
6895 if (mips_opts.mips16 && history[0].fixp[0])
6898 /* If the branch is itself the target of a branch, we can not swap.
6899 We cheat on this; all we check for is whether there is a label on
6900 this instruction. If there are any branches to anything other than
6901 a label, users must use .set noreorder. */
6902 if (seg_info (now_seg)->label_list)
6905 /* If the previous instruction is in a variant frag other than this
6906 branch's one, we cannot do the swap. This does not apply to
6907 MIPS16 code, which uses variant frags for different purposes. */
6908 if (!mips_opts.mips16
6910 && history[0].frag->fr_type == rs_machine_dependent)
6913 /* We do not swap with instructions that cannot architecturally
6914 be placed in a branch delay slot, such as SYNC or ERET. We
6915 also refrain from swapping with a trap instruction, since it
6916 complicates trap handlers to have the trap instruction be in
6918 prev_pinfo = history[0].insn_mo->pinfo;
6919 if (prev_pinfo & INSN_NO_DELAY_SLOT)
6922 /* Check for conflicts between the branch and the instructions
6923 before the candidate delay slot. */
6924 if (nops_for_insn (0, history + 1, ip) > 0)
6927 /* Check for conflicts between the swapped sequence and the
6928 target of the branch. */
6929 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
6932 /* If the branch reads a register that the previous
6933 instruction sets, we can not swap. */
6934 gpr_read = gpr_read_mask (ip);
6935 prev_gpr_write = gpr_write_mask (&history[0]);
6936 if (gpr_read & prev_gpr_write)
6939 fpr_read = fpr_read_mask (ip);
6940 prev_fpr_write = fpr_write_mask (&history[0]);
6941 if (fpr_read & prev_fpr_write)
6944 /* If the branch writes a register that the previous
6945 instruction sets, we can not swap. */
6946 gpr_write = gpr_write_mask (ip);
6947 if (gpr_write & prev_gpr_write)
6950 /* If the branch writes a register that the previous
6951 instruction reads, we can not swap. */
6952 prev_gpr_read = gpr_read_mask (&history[0]);
6953 if (gpr_write & prev_gpr_read)
6956 /* If one instruction sets a condition code and the
6957 other one uses a condition code, we can not swap. */
6958 pinfo = ip->insn_mo->pinfo;
6959 if ((pinfo & INSN_READ_COND_CODE)
6960 && (prev_pinfo & INSN_WRITE_COND_CODE))
6962 if ((pinfo & INSN_WRITE_COND_CODE)
6963 && (prev_pinfo & INSN_READ_COND_CODE))
6966 /* If the previous instruction uses the PC, we can not swap. */
6967 prev_pinfo2 = history[0].insn_mo->pinfo2;
6968 if (prev_pinfo2 & INSN2_READ_PC)
6971 /* If the previous instruction has an incorrect size for a fixed
6972 branch delay slot in microMIPS mode, we cannot swap. */
6973 pinfo2 = ip->insn_mo->pinfo2;
6974 if (mips_opts.micromips
6975 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
6976 && insn_length (history) != 2)
6978 if (mips_opts.micromips
6979 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
6980 && insn_length (history) != 4)
6983 /* On R5900 short loops need to be fixed by inserting a nop in
6984 the branch delay slots.
6985 A short loop can be terminated too early. */
6986 if (mips_opts.arch == CPU_R5900
6987 /* Check if instruction has a parameter, ignore "j $31". */
6988 && (address_expr != NULL)
6989 /* Parameter must be 16 bit. */
6990 && (*reloc_type == BFD_RELOC_16_PCREL_S2)
6991 /* Branch to same segment. */
6992 && (S_GET_SEGMENT (address_expr->X_add_symbol) == now_seg)
6993 /* Branch to same code fragment. */
6994 && (symbol_get_frag (address_expr->X_add_symbol) == frag_now)
6995 /* Can only calculate branch offset if value is known. */
6996 && symbol_constant_p (address_expr->X_add_symbol)
6997 /* Check if branch is really conditional. */
6998 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */
6999 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */
7000 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
7003 /* Check if loop is shorter than 6 instructions including
7004 branch and delay slot. */
7005 distance = frag_now_fix () - S_GET_VALUE (address_expr->X_add_symbol);
7012 /* When the loop includes branches or jumps,
7013 it is not a short loop. */
7014 for (i = 0; i < (distance / 4); i++)
7016 if ((history[i].cleared_p)
7017 || delayed_branch_p (&history[i]))
7025 /* Insert nop after branch to fix short loop. */
7034 /* Decide how we should add IP to the instruction stream.
7035 ADDRESS_EXPR is an operand of the instruction to be used with
7038 static enum append_method
7039 get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
7040 bfd_reloc_code_real_type *reloc_type)
7042 /* The relaxed version of a macro sequence must be inherently
7044 if (mips_relax.sequence == 2)
7047 /* We must not dabble with instructions in a ".set noreorder" block. */
7048 if (mips_opts.noreorder)
7051 /* Otherwise, it's our responsibility to fill branch delay slots. */
7052 if (delayed_branch_p (ip))
7054 if (!branch_likely_p (ip)
7055 && can_swap_branch_p (ip, address_expr, reloc_type))
7058 if (mips_opts.mips16
7059 && ISA_SUPPORTS_MIPS16E
7060 && gpr_read_mask (ip) != 0)
7061 return APPEND_ADD_COMPACT;
7063 if (mips_opts.micromips
7064 && ((ip->insn_opcode & 0xffe0) == 0x4580
7065 || (!forced_insn_length
7066 && ((ip->insn_opcode & 0xfc00) == 0xcc00
7067 || (ip->insn_opcode & 0xdc00) == 0x8c00))
7068 || (ip->insn_opcode & 0xdfe00000) == 0x94000000
7069 || (ip->insn_opcode & 0xdc1f0000) == 0x94000000))
7070 return APPEND_ADD_COMPACT;
7072 return APPEND_ADD_WITH_NOP;
7078 /* IP is an instruction whose opcode we have just changed, END points
7079 to the end of the opcode table processed. Point IP->insn_mo to the
7080 new opcode's definition. */
7083 find_altered_opcode (struct mips_cl_insn *ip, const struct mips_opcode *end)
7085 const struct mips_opcode *mo;
7087 for (mo = ip->insn_mo; mo < end; mo++)
7088 if (mo->pinfo != INSN_MACRO
7089 && (ip->insn_opcode & mo->mask) == mo->match)
7097 /* IP is a MIPS16 instruction whose opcode we have just changed.
7098 Point IP->insn_mo to the new opcode's definition. */
7101 find_altered_mips16_opcode (struct mips_cl_insn *ip)
7103 find_altered_opcode (ip, &mips16_opcodes[bfd_mips16_num_opcodes]);
7106 /* IP is a microMIPS instruction whose opcode we have just changed.
7107 Point IP->insn_mo to the new opcode's definition. */
7110 find_altered_micromips_opcode (struct mips_cl_insn *ip)
7112 find_altered_opcode (ip, µmips_opcodes[bfd_micromips_num_opcodes]);
7115 /* For microMIPS macros, we need to generate a local number label
7116 as the target of branches. */
7117 #define MICROMIPS_LABEL_CHAR '\037'
7118 static unsigned long micromips_target_label;
7119 static char micromips_target_name[32];
7122 micromips_label_name (void)
7124 char *p = micromips_target_name;
7125 char symbol_name_temporary[24];
7133 l = micromips_target_label;
7134 #ifdef LOCAL_LABEL_PREFIX
7135 *p++ = LOCAL_LABEL_PREFIX;
7138 *p++ = MICROMIPS_LABEL_CHAR;
7141 symbol_name_temporary[i++] = l % 10 + '0';
7146 *p++ = symbol_name_temporary[--i];
7149 return micromips_target_name;
7153 micromips_label_expr (expressionS *label_expr)
7155 label_expr->X_op = O_symbol;
7156 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
7157 label_expr->X_add_number = 0;
7161 micromips_label_inc (void)
7163 micromips_target_label++;
7164 *micromips_target_name = '\0';
7168 micromips_add_label (void)
7172 s = colon (micromips_label_name ());
7173 micromips_label_inc ();
7174 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
7177 /* If assembling microMIPS code, then return the microMIPS reloc
7178 corresponding to the requested one if any. Otherwise return
7179 the reloc unchanged. */
7181 static bfd_reloc_code_real_type
7182 micromips_map_reloc (bfd_reloc_code_real_type reloc)
7184 static const bfd_reloc_code_real_type relocs[][2] =
7186 /* Keep sorted incrementally by the left-hand key. */
7187 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
7188 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
7189 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
7190 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
7191 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
7192 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
7193 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
7194 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
7195 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
7196 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
7197 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
7198 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
7199 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
7200 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
7201 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
7202 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
7203 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
7204 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
7205 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
7206 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
7207 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
7208 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
7209 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
7210 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
7211 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
7212 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
7213 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
7215 bfd_reloc_code_real_type r;
7218 if (!mips_opts.micromips)
7220 for (i = 0; i < ARRAY_SIZE (relocs); i++)
7226 return relocs[i][1];
7231 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
7232 Return true on success, storing the resolved value in RESULT. */
7235 calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
7240 case BFD_RELOC_MIPS_HIGHEST:
7241 case BFD_RELOC_MICROMIPS_HIGHEST:
7242 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff;
7245 case BFD_RELOC_MIPS_HIGHER:
7246 case BFD_RELOC_MICROMIPS_HIGHER:
7247 *result = ((operand + 0x80008000ull) >> 32) & 0xffff;
7250 case BFD_RELOC_HI16_S:
7251 case BFD_RELOC_HI16_S_PCREL:
7252 case BFD_RELOC_MICROMIPS_HI16_S:
7253 case BFD_RELOC_MIPS16_HI16_S:
7254 *result = ((operand + 0x8000) >> 16) & 0xffff;
7257 case BFD_RELOC_HI16:
7258 case BFD_RELOC_MICROMIPS_HI16:
7259 case BFD_RELOC_MIPS16_HI16:
7260 *result = (operand >> 16) & 0xffff;
7263 case BFD_RELOC_LO16:
7264 case BFD_RELOC_LO16_PCREL:
7265 case BFD_RELOC_MICROMIPS_LO16:
7266 case BFD_RELOC_MIPS16_LO16:
7267 *result = operand & 0xffff;
7270 case BFD_RELOC_UNUSED:
7279 /* Output an instruction. IP is the instruction information.
7280 ADDRESS_EXPR is an operand of the instruction to be used with
7281 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
7282 a macro expansion. */
7285 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
7286 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
7288 unsigned long prev_pinfo2, pinfo;
7289 bfd_boolean relaxed_branch = FALSE;
7290 enum append_method method;
7291 bfd_boolean relax32;
7294 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
7295 fix_loongson2f (ip);
7297 file_ase_mips16 |= mips_opts.mips16;
7298 file_ase_micromips |= mips_opts.micromips;
7300 prev_pinfo2 = history[0].insn_mo->pinfo2;
7301 pinfo = ip->insn_mo->pinfo;
7303 /* Don't raise alarm about `nods' frags as they'll fill in the right
7304 kind of nop in relaxation if required. */
7305 if (mips_opts.micromips
7307 && !(history[0].frag
7308 && history[0].frag->fr_type == rs_machine_dependent
7309 && RELAX_MICROMIPS_P (history[0].frag->fr_subtype)
7310 && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype))
7311 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
7312 && micromips_insn_length (ip->insn_mo) != 2)
7313 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
7314 && micromips_insn_length (ip->insn_mo) != 4)))
7315 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
7316 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
7318 if (address_expr == NULL)
7320 else if (reloc_type[0] <= BFD_RELOC_UNUSED
7321 && reloc_type[1] == BFD_RELOC_UNUSED
7322 && reloc_type[2] == BFD_RELOC_UNUSED
7323 && address_expr->X_op == O_constant)
7325 switch (*reloc_type)
7327 case BFD_RELOC_MIPS_JMP:
7331 /* Shift is 2, unusually, for microMIPS JALX. */
7332 shift = (mips_opts.micromips
7333 && strcmp (ip->insn_mo->name, "jalx") != 0) ? 1 : 2;
7334 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7335 as_bad (_("jump to misaligned address (0x%lx)"),
7336 (unsigned long) address_expr->X_add_number);
7337 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7343 case BFD_RELOC_MIPS16_JMP:
7344 if ((address_expr->X_add_number & 3) != 0)
7345 as_bad (_("jump to misaligned address (0x%lx)"),
7346 (unsigned long) address_expr->X_add_number);
7348 (((address_expr->X_add_number & 0x7c0000) << 3)
7349 | ((address_expr->X_add_number & 0xf800000) >> 7)
7350 | ((address_expr->X_add_number & 0x3fffc) >> 2));
7354 case BFD_RELOC_16_PCREL_S2:
7358 shift = mips_opts.micromips ? 1 : 2;
7359 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7360 as_bad (_("branch to misaligned address (0x%lx)"),
7361 (unsigned long) address_expr->X_add_number);
7362 if (!mips_relax_branch)
7364 if ((address_expr->X_add_number + (1 << (shift + 15)))
7365 & ~((1 << (shift + 16)) - 1))
7366 as_bad (_("branch address range overflow (0x%lx)"),
7367 (unsigned long) address_expr->X_add_number);
7368 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7374 case BFD_RELOC_MIPS_21_PCREL_S2:
7379 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7380 as_bad (_("branch to misaligned address (0x%lx)"),
7381 (unsigned long) address_expr->X_add_number);
7382 if ((address_expr->X_add_number + (1 << (shift + 20)))
7383 & ~((1 << (shift + 21)) - 1))
7384 as_bad (_("branch address range overflow (0x%lx)"),
7385 (unsigned long) address_expr->X_add_number);
7386 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7391 case BFD_RELOC_MIPS_26_PCREL_S2:
7396 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7397 as_bad (_("branch to misaligned address (0x%lx)"),
7398 (unsigned long) address_expr->X_add_number);
7399 if ((address_expr->X_add_number + (1 << (shift + 25)))
7400 & ~((1 << (shift + 26)) - 1))
7401 as_bad (_("branch address range overflow (0x%lx)"),
7402 (unsigned long) address_expr->X_add_number);
7403 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7412 if (calculate_reloc (*reloc_type, address_expr->X_add_number,
7415 ip->insn_opcode |= value & 0xffff;
7423 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
7425 /* There are a lot of optimizations we could do that we don't.
7426 In particular, we do not, in general, reorder instructions.
7427 If you use gcc with optimization, it will reorder
7428 instructions and generally do much more optimization then we
7429 do here; repeating all that work in the assembler would only
7430 benefit hand written assembly code, and does not seem worth
7432 int nops = (mips_optimize == 0
7433 ? nops_for_insn (0, history, NULL)
7434 : nops_for_insn_or_target (0, history, ip));
7438 unsigned long old_frag_offset;
7441 old_frag = frag_now;
7442 old_frag_offset = frag_now_fix ();
7444 for (i = 0; i < nops; i++)
7445 add_fixed_insn (NOP_INSN);
7446 insert_into_history (0, nops, NOP_INSN);
7450 listing_prev_line ();
7451 /* We may be at the start of a variant frag. In case we
7452 are, make sure there is enough space for the frag
7453 after the frags created by listing_prev_line. The
7454 argument to frag_grow here must be at least as large
7455 as the argument to all other calls to frag_grow in
7456 this file. We don't have to worry about being in the
7457 middle of a variant frag, because the variants insert
7458 all needed nop instructions themselves. */
7462 mips_move_text_labels ();
7464 #ifndef NO_ECOFF_DEBUGGING
7465 if (ECOFF_DEBUGGING)
7466 ecoff_fix_loc (old_frag, old_frag_offset);
7470 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
7474 /* Work out how many nops in prev_nop_frag are needed by IP,
7475 ignoring hazards generated by the first prev_nop_frag_since
7477 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
7478 gas_assert (nops <= prev_nop_frag_holds);
7480 /* Enforce NOPS as a minimum. */
7481 if (nops > prev_nop_frag_required)
7482 prev_nop_frag_required = nops;
7484 if (prev_nop_frag_holds == prev_nop_frag_required)
7486 /* Settle for the current number of nops. Update the history
7487 accordingly (for the benefit of any future .set reorder code). */
7488 prev_nop_frag = NULL;
7489 insert_into_history (prev_nop_frag_since,
7490 prev_nop_frag_holds, NOP_INSN);
7494 /* Allow this instruction to replace one of the nops that was
7495 tentatively added to prev_nop_frag. */
7496 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
7497 prev_nop_frag_holds--;
7498 prev_nop_frag_since++;
7502 method = get_append_method (ip, address_expr, reloc_type);
7503 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
7505 dwarf2_emit_insn (0);
7506 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7507 so "move" the instruction address accordingly.
7509 Also, it doesn't seem appropriate for the assembler to reorder .loc
7510 entries. If this instruction is a branch that we are going to swap
7511 with the previous instruction, the two instructions should be
7512 treated as a unit, and the debug information for both instructions
7513 should refer to the start of the branch sequence. Using the
7514 current position is certainly wrong when swapping a 32-bit branch
7515 and a 16-bit delay slot, since the current position would then be
7516 in the middle of a branch. */
7517 dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp);
7519 relax32 = (mips_relax_branch
7520 /* Don't try branch relaxation within .set nomacro, or within
7521 .set noat if we use $at for PIC computations. If it turns
7522 out that the branch was out-of-range, we'll get an error. */
7523 && !mips_opts.warn_about_macros
7524 && (mips_opts.at || mips_pic == NO_PIC)
7525 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7526 as they have no complementing branches. */
7527 && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP)));
7529 if (!HAVE_CODE_COMPRESSION
7532 && *reloc_type == BFD_RELOC_16_PCREL_S2
7533 && delayed_branch_p (ip))
7535 relaxed_branch = TRUE;
7536 add_relaxed_insn (ip, (relaxed_branch_length
7538 uncond_branch_p (ip) ? -1
7539 : branch_likely_p (ip) ? 1
7542 (AT, mips_pic != NO_PIC,
7543 uncond_branch_p (ip),
7544 branch_likely_p (ip),
7545 pinfo & INSN_WRITE_GPR_31,
7547 address_expr->X_add_symbol,
7548 address_expr->X_add_number);
7549 *reloc_type = BFD_RELOC_UNUSED;
7551 else if (mips_opts.micromips
7553 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
7554 || *reloc_type > BFD_RELOC_UNUSED)
7555 && (delayed_branch_p (ip) || compact_branch_p (ip))
7556 /* Don't try branch relaxation when users specify
7557 16-bit/32-bit instructions. */
7558 && !forced_insn_length)
7560 bfd_boolean relax16 = (method != APPEND_ADD_COMPACT
7561 && *reloc_type > BFD_RELOC_UNUSED);
7562 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
7563 int uncond = uncond_branch_p (ip) ? -1 : 0;
7564 int compact = compact_branch_p (ip) || method == APPEND_ADD_COMPACT;
7565 int nods = method == APPEND_ADD_WITH_NOP;
7566 int al = pinfo & INSN_WRITE_GPR_31;
7567 int length32 = nods ? 8 : 4;
7569 gas_assert (address_expr != NULL);
7570 gas_assert (!mips_relax.sequence);
7572 relaxed_branch = TRUE;
7574 method = APPEND_ADD;
7576 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
7577 add_relaxed_insn (ip, length32, relax16 ? 2 : 4,
7578 RELAX_MICROMIPS_ENCODE (type, AT, mips_opts.insn32,
7580 uncond, compact, al, nods,
7582 address_expr->X_add_symbol,
7583 address_expr->X_add_number);
7584 *reloc_type = BFD_RELOC_UNUSED;
7586 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
7588 bfd_boolean require_unextended;
7589 bfd_boolean require_extended;
7593 if (forced_insn_length != 0)
7595 require_unextended = forced_insn_length == 2;
7596 require_extended = forced_insn_length == 4;
7600 require_unextended = (mips_opts.noautoextend
7601 && !mips_opcode_32bit_p (ip->insn_mo));
7602 require_extended = 0;
7605 /* We need to set up a variant frag. */
7606 gas_assert (address_expr != NULL);
7607 /* Pass any `O_symbol' expression unchanged as an `expr_section'
7608 symbol created by `make_expr_symbol' may not get a necessary
7609 external relocation produced. */
7610 if (address_expr->X_op == O_symbol)
7612 symbol = address_expr->X_add_symbol;
7613 offset = address_expr->X_add_number;
7617 symbol = make_expr_symbol (address_expr);
7618 symbol_append (symbol, symbol_lastP, &symbol_rootP, &symbol_lastP);
7621 add_relaxed_insn (ip, 12, 0,
7623 (*reloc_type - BFD_RELOC_UNUSED,
7624 mips_opts.ase & ASE_MIPS16E2,
7627 mips_opts.warn_about_macros,
7628 require_unextended, require_extended,
7629 delayed_branch_p (&history[0]),
7630 history[0].mips16_absolute_jump_p),
7633 else if (mips_opts.mips16 && insn_length (ip) == 2)
7635 if (!delayed_branch_p (ip))
7636 /* Make sure there is enough room to swap this instruction with
7637 a following jump instruction. */
7639 add_fixed_insn (ip);
7643 if (mips_opts.mips16
7644 && mips_opts.noreorder
7645 && delayed_branch_p (&history[0]))
7646 as_warn (_("extended instruction in delay slot"));
7648 if (mips_relax.sequence)
7650 /* If we've reached the end of this frag, turn it into a variant
7651 frag and record the information for the instructions we've
7653 if (frag_room () < 4)
7654 relax_close_frag ();
7655 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
7658 if (mips_relax.sequence != 2)
7660 if (mips_macro_warning.first_insn_sizes[0] == 0)
7661 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
7662 mips_macro_warning.sizes[0] += insn_length (ip);
7663 mips_macro_warning.insns[0]++;
7665 if (mips_relax.sequence != 1)
7667 if (mips_macro_warning.first_insn_sizes[1] == 0)
7668 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
7669 mips_macro_warning.sizes[1] += insn_length (ip);
7670 mips_macro_warning.insns[1]++;
7673 if (mips_opts.mips16)
7676 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
7678 add_fixed_insn (ip);
7681 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
7683 bfd_reloc_code_real_type final_type[3];
7684 reloc_howto_type *howto0;
7685 reloc_howto_type *howto;
7688 /* Perform any necessary conversion to microMIPS relocations
7689 and find out how many relocations there actually are. */
7690 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
7691 final_type[i] = micromips_map_reloc (reloc_type[i]);
7693 /* In a compound relocation, it is the final (outermost)
7694 operator that determines the relocated field. */
7695 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
7700 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
7701 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
7702 bfd_get_reloc_size (howto),
7704 howto0 && howto0->pc_relative,
7706 /* Record non-PIC mode in `fx_tcbit2' for `md_apply_fix'. */
7707 ip->fixp[0]->fx_tcbit2 = mips_pic == NO_PIC;
7709 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
7710 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
7711 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
7713 /* These relocations can have an addend that won't fit in
7714 4 octets for 64bit assembly. */
7716 && ! howto->partial_inplace
7717 && (reloc_type[0] == BFD_RELOC_16
7718 || reloc_type[0] == BFD_RELOC_32
7719 || reloc_type[0] == BFD_RELOC_MIPS_JMP
7720 || reloc_type[0] == BFD_RELOC_GPREL16
7721 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
7722 || reloc_type[0] == BFD_RELOC_GPREL32
7723 || reloc_type[0] == BFD_RELOC_64
7724 || reloc_type[0] == BFD_RELOC_CTOR
7725 || reloc_type[0] == BFD_RELOC_MIPS_SUB
7726 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
7727 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
7728 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
7729 || reloc_type[0] == BFD_RELOC_MIPS_REL16
7730 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
7731 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
7732 || hi16_reloc_p (reloc_type[0])
7733 || lo16_reloc_p (reloc_type[0])))
7734 ip->fixp[0]->fx_no_overflow = 1;
7736 /* These relocations can have an addend that won't fit in 2 octets. */
7737 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
7738 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1)
7739 ip->fixp[0]->fx_no_overflow = 1;
7741 if (mips_relax.sequence)
7743 if (mips_relax.first_fixup == 0)
7744 mips_relax.first_fixup = ip->fixp[0];
7746 else if (reloc_needs_lo_p (*reloc_type))
7748 struct mips_hi_fixup *hi_fixup;
7750 /* Reuse the last entry if it already has a matching %lo. */
7751 hi_fixup = mips_hi_fixup_list;
7753 || !fixup_has_matching_lo_p (hi_fixup->fixp))
7755 hi_fixup = XNEW (struct mips_hi_fixup);
7756 hi_fixup->next = mips_hi_fixup_list;
7757 mips_hi_fixup_list = hi_fixup;
7759 hi_fixup->fixp = ip->fixp[0];
7760 hi_fixup->seg = now_seg;
7763 /* Add fixups for the second and third relocations, if given.
7764 Note that the ABI allows the second relocation to be
7765 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
7766 moment we only use RSS_UNDEF, but we could add support
7767 for the others if it ever becomes necessary. */
7768 for (i = 1; i < 3; i++)
7769 if (reloc_type[i] != BFD_RELOC_UNUSED)
7771 ip->fixp[i] = fix_new (ip->frag, ip->where,
7772 ip->fixp[0]->fx_size, NULL, 0,
7773 FALSE, final_type[i]);
7775 /* Use fx_tcbit to mark compound relocs. */
7776 ip->fixp[0]->fx_tcbit = 1;
7777 ip->fixp[i]->fx_tcbit = 1;
7781 /* Update the register mask information. */
7782 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
7783 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
7788 insert_into_history (0, 1, ip);
7791 case APPEND_ADD_WITH_NOP:
7793 struct mips_cl_insn *nop;
7795 insert_into_history (0, 1, ip);
7796 nop = get_delay_slot_nop (ip);
7797 add_fixed_insn (nop);
7798 insert_into_history (0, 1, nop);
7799 if (mips_relax.sequence)
7800 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
7804 case APPEND_ADD_COMPACT:
7805 /* Convert MIPS16 jr/jalr into a "compact" jump. */
7806 if (mips_opts.mips16)
7808 ip->insn_opcode |= 0x0080;
7809 find_altered_mips16_opcode (ip);
7811 /* Convert microMIPS instructions. */
7812 else if (mips_opts.micromips)
7815 if ((ip->insn_opcode & 0xffe0) == 0x4580)
7816 ip->insn_opcode |= 0x0020;
7818 else if ((ip->insn_opcode & 0xfc00) == 0xcc00)
7819 ip->insn_opcode = 0x40e00000;
7820 /* beqz16->beqzc, bnez16->bnezc */
7821 else if ((ip->insn_opcode & 0xdc00) == 0x8c00)
7823 unsigned long regno;
7825 regno = ip->insn_opcode >> MICROMIPSOP_SH_MD;
7826 regno &= MICROMIPSOP_MASK_MD;
7827 regno = micromips_to_32_reg_d_map[regno];
7828 ip->insn_opcode = (((ip->insn_opcode << 9) & 0x00400000)
7829 | (regno << MICROMIPSOP_SH_RS)
7830 | 0x40a00000) ^ 0x00400000;
7832 /* beqz->beqzc, bnez->bnezc */
7833 else if ((ip->insn_opcode & 0xdfe00000) == 0x94000000)
7834 ip->insn_opcode = ((ip->insn_opcode & 0x001f0000)
7835 | ((ip->insn_opcode >> 7) & 0x00400000)
7836 | 0x40a00000) ^ 0x00400000;
7837 /* beq $0->beqzc, bne $0->bnezc */
7838 else if ((ip->insn_opcode & 0xdc1f0000) == 0x94000000)
7839 ip->insn_opcode = (((ip->insn_opcode >>
7840 (MICROMIPSOP_SH_RT - MICROMIPSOP_SH_RS))
7841 & (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS))
7842 | ((ip->insn_opcode >> 7) & 0x00400000)
7843 | 0x40a00000) ^ 0x00400000;
7846 find_altered_micromips_opcode (ip);
7851 insert_into_history (0, 1, ip);
7856 struct mips_cl_insn delay = history[0];
7858 if (relaxed_branch || delay.frag != ip->frag)
7860 /* Add the delay slot instruction to the end of the
7861 current frag and shrink the fixed part of the
7862 original frag. If the branch occupies the tail of
7863 the latter, move it backwards to cover the gap. */
7864 delay.frag->fr_fix -= branch_disp;
7865 if (delay.frag == ip->frag)
7866 move_insn (ip, ip->frag, ip->where - branch_disp);
7867 add_fixed_insn (&delay);
7871 /* If this is not a relaxed branch and we are in the
7872 same frag, then just swap the instructions. */
7873 move_insn (ip, delay.frag, delay.where);
7874 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
7878 insert_into_history (0, 1, &delay);
7883 /* If we have just completed an unconditional branch, clear the history. */
7884 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
7885 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
7889 mips_no_prev_insn ();
7891 for (i = 0; i < ARRAY_SIZE (history); i++)
7892 history[i].cleared_p = 1;
7895 /* We need to emit a label at the end of branch-likely macros. */
7896 if (emit_branch_likely_macro)
7898 emit_branch_likely_macro = FALSE;
7899 micromips_add_label ();
7902 /* We just output an insn, so the next one doesn't have a label. */
7903 mips_clear_insn_labels ();
7906 /* Forget that there was any previous instruction or label.
7907 When BRANCH is true, the branch history is also flushed. */
7910 mips_no_prev_insn (void)
7912 prev_nop_frag = NULL;
7913 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
7914 mips_clear_insn_labels ();
7917 /* This function must be called before we emit something other than
7918 instructions. It is like mips_no_prev_insn except that it inserts
7919 any NOPS that might be needed by previous instructions. */
7922 mips_emit_delays (void)
7924 if (! mips_opts.noreorder)
7926 int nops = nops_for_insn (0, history, NULL);
7930 add_fixed_insn (NOP_INSN);
7931 mips_move_text_labels ();
7934 mips_no_prev_insn ();
7937 /* Start a (possibly nested) noreorder block. */
7940 start_noreorder (void)
7942 if (mips_opts.noreorder == 0)
7947 /* None of the instructions before the .set noreorder can be moved. */
7948 for (i = 0; i < ARRAY_SIZE (history); i++)
7949 history[i].fixed_p = 1;
7951 /* Insert any nops that might be needed between the .set noreorder
7952 block and the previous instructions. We will later remove any
7953 nops that turn out not to be needed. */
7954 nops = nops_for_insn (0, history, NULL);
7957 if (mips_optimize != 0)
7959 /* Record the frag which holds the nop instructions, so
7960 that we can remove them if we don't need them. */
7961 frag_grow (nops * NOP_INSN_SIZE);
7962 prev_nop_frag = frag_now;
7963 prev_nop_frag_holds = nops;
7964 prev_nop_frag_required = 0;
7965 prev_nop_frag_since = 0;
7968 for (; nops > 0; --nops)
7969 add_fixed_insn (NOP_INSN);
7971 /* Move on to a new frag, so that it is safe to simply
7972 decrease the size of prev_nop_frag. */
7973 frag_wane (frag_now);
7975 mips_move_text_labels ();
7977 mips_mark_labels ();
7978 mips_clear_insn_labels ();
7980 mips_opts.noreorder++;
7981 mips_any_noreorder = 1;
7984 /* End a nested noreorder block. */
7987 end_noreorder (void)
7989 mips_opts.noreorder--;
7990 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
7992 /* Commit to inserting prev_nop_frag_required nops and go back to
7993 handling nop insertion the .set reorder way. */
7994 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
7996 insert_into_history (prev_nop_frag_since,
7997 prev_nop_frag_required, NOP_INSN);
7998 prev_nop_frag = NULL;
8002 /* Sign-extend 32-bit mode constants that have bit 31 set and all
8003 higher bits unset. */
8006 normalize_constant_expr (expressionS *ex)
8008 if (ex->X_op == O_constant
8009 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
8010 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
8014 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
8015 all higher bits unset. */
8018 normalize_address_expr (expressionS *ex)
8020 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
8021 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
8022 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
8023 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
8027 /* Try to match TOKENS against OPCODE, storing the result in INSN.
8028 Return true if the match was successful.
8030 OPCODE_EXTRA is a value that should be ORed into the opcode
8031 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
8032 there are more alternatives after OPCODE and SOFT_MATCH is
8033 as for mips_arg_info. */
8036 match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
8037 struct mips_operand_token *tokens, unsigned int opcode_extra,
8038 bfd_boolean lax_match, bfd_boolean complete_p)
8041 struct mips_arg_info arg;
8042 const struct mips_operand *operand;
8045 imm_expr.X_op = O_absent;
8046 offset_expr.X_op = O_absent;
8047 offset_reloc[0] = BFD_RELOC_UNUSED;
8048 offset_reloc[1] = BFD_RELOC_UNUSED;
8049 offset_reloc[2] = BFD_RELOC_UNUSED;
8051 create_insn (insn, opcode);
8052 /* When no opcode suffix is specified, assume ".xyzw". */
8053 if ((opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0 && opcode_extra == 0)
8054 insn->insn_opcode |= 0xf << mips_vu0_channel_mask.lsb;
8056 insn->insn_opcode |= opcode_extra;
8057 memset (&arg, 0, sizeof (arg));
8061 arg.last_regno = ILLEGAL_REG;
8062 arg.dest_regno = ILLEGAL_REG;
8063 arg.lax_match = lax_match;
8064 for (args = opcode->args;; ++args)
8066 if (arg.token->type == OT_END)
8068 /* Handle unary instructions in which only one operand is given.
8069 The source is then the same as the destination. */
8070 if (arg.opnum == 1 && *args == ',')
8072 operand = (mips_opts.micromips
8073 ? decode_micromips_operand (args + 1)
8074 : decode_mips_operand (args + 1));
8075 if (operand && mips_optional_operand_p (operand))
8083 /* Treat elided base registers as $0. */
8084 if (strcmp (args, "(b)") == 0)
8092 /* The register suffix is optional. */
8097 /* Fail the match if there were too few operands. */
8101 /* Successful match. */
8104 clear_insn_error ();
8105 if (arg.dest_regno == arg.last_regno
8106 && strncmp (insn->insn_mo->name, "jalr", 4) == 0)
8110 (0, _("source and destination must be different"));
8111 else if (arg.last_regno == 31)
8113 (0, _("a destination register must be supplied"));
8115 else if (arg.last_regno == 31
8116 && (strncmp (insn->insn_mo->name, "bltzal", 6) == 0
8117 || strncmp (insn->insn_mo->name, "bgezal", 6) == 0))
8118 set_insn_error (0, _("the source register must not be $31"));
8119 check_completed_insn (&arg);
8123 /* Fail the match if the line has too many operands. */
8127 /* Handle characters that need to match exactly. */
8128 if (*args == '(' || *args == ')' || *args == ',')
8130 if (match_char (&arg, *args))
8137 if (arg.token->type == OT_DOUBLE_CHAR
8138 && arg.token->u.ch == *args)
8146 /* Handle special macro operands. Work out the properties of
8155 *offset_reloc = BFD_RELOC_MIPS_19_PCREL_S2;
8159 *offset_reloc = BFD_RELOC_MIPS_18_PCREL_S3;
8168 *offset_reloc = BFD_RELOC_MIPS_JMP;
8172 *offset_reloc = BFD_RELOC_MIPS_26_PCREL_S2;
8176 *offset_reloc = BFD_RELOC_MIPS_21_PCREL_S2;
8182 if (!match_const_int (&arg, &imm_expr.X_add_number))
8184 imm_expr.X_op = O_constant;
8186 normalize_constant_expr (&imm_expr);
8190 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
8192 /* Assume that the offset has been elided and that what
8193 we saw was a base register. The match will fail later
8194 if that assumption turns out to be wrong. */
8195 offset_expr.X_op = O_constant;
8196 offset_expr.X_add_number = 0;
8200 if (!match_expression (&arg, &offset_expr, offset_reloc))
8202 normalize_address_expr (&offset_expr);
8207 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
8213 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
8219 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
8225 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
8231 *offset_reloc = BFD_RELOC_16_PCREL_S2;
8235 *offset_reloc = BFD_RELOC_MIPS_JMP;
8239 gas_assert (mips_opts.micromips);
8245 if (!forced_insn_length)
8246 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
8248 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
8250 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
8256 operand = (mips_opts.micromips
8257 ? decode_micromips_operand (args)
8258 : decode_mips_operand (args));
8262 /* Skip prefixes. */
8263 if (*args == '+' || *args == 'm' || *args == '-')
8266 if (mips_optional_operand_p (operand)
8268 && (arg.token[0].type != OT_REG
8269 || arg.token[1].type == OT_END))
8271 /* Assume that the register has been elided and is the
8272 same as the first operand. */
8277 if (!match_operand (&arg, operand))
8282 /* Like match_insn, but for MIPS16. */
8285 match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
8286 struct mips_operand_token *tokens)
8289 const struct mips_operand *operand;
8290 const struct mips_operand *ext_operand;
8291 bfd_boolean pcrel = FALSE;
8292 int required_insn_length;
8293 struct mips_arg_info arg;
8296 if (forced_insn_length)
8297 required_insn_length = forced_insn_length;
8298 else if (mips_opts.noautoextend && !mips_opcode_32bit_p (opcode))
8299 required_insn_length = 2;
8301 required_insn_length = 0;
8303 create_insn (insn, opcode);
8304 imm_expr.X_op = O_absent;
8305 offset_expr.X_op = O_absent;
8306 offset_reloc[0] = BFD_RELOC_UNUSED;
8307 offset_reloc[1] = BFD_RELOC_UNUSED;
8308 offset_reloc[2] = BFD_RELOC_UNUSED;
8311 memset (&arg, 0, sizeof (arg));
8315 arg.last_regno = ILLEGAL_REG;
8316 arg.dest_regno = ILLEGAL_REG;
8318 for (args = opcode->args;; ++args)
8322 if (arg.token->type == OT_END)
8326 /* Handle unary instructions in which only one operand is given.
8327 The source is then the same as the destination. */
8328 if (arg.opnum == 1 && *args == ',')
8330 operand = decode_mips16_operand (args[1], FALSE);
8331 if (operand && mips_optional_operand_p (operand))
8339 /* Fail the match if there were too few operands. */
8343 /* Successful match. Stuff the immediate value in now, if
8345 clear_insn_error ();
8346 if (opcode->pinfo == INSN_MACRO)
8348 gas_assert (relax_char == 0 || relax_char == 'p');
8349 gas_assert (*offset_reloc == BFD_RELOC_UNUSED);
8352 && offset_expr.X_op == O_constant
8354 && calculate_reloc (*offset_reloc,
8355 offset_expr.X_add_number,
8358 mips16_immed (NULL, 0, relax_char, *offset_reloc, value,
8359 required_insn_length, &insn->insn_opcode);
8360 offset_expr.X_op = O_absent;
8361 *offset_reloc = BFD_RELOC_UNUSED;
8363 else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED)
8365 if (required_insn_length == 2)
8366 set_insn_error (0, _("invalid unextended operand value"));
8367 else if (!mips_opcode_32bit_p (opcode))
8369 forced_insn_length = 4;
8370 insn->insn_opcode |= MIPS16_EXTEND;
8373 else if (relax_char)
8374 *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char;
8376 check_completed_insn (&arg);
8380 /* Fail the match if the line has too many operands. */
8384 /* Handle characters that need to match exactly. */
8385 if (*args == '(' || *args == ')' || *args == ',')
8387 if (match_char (&arg, *args))
8407 if (!match_const_int (&arg, &imm_expr.X_add_number))
8409 imm_expr.X_op = O_constant;
8411 normalize_constant_expr (&imm_expr);
8416 *offset_reloc = BFD_RELOC_MIPS16_JMP;
8420 operand = decode_mips16_operand (c, mips_opcode_32bit_p (opcode));
8424 if (operand->type == OP_PCREL)
8428 ext_operand = decode_mips16_operand (c, TRUE);
8429 if (operand != ext_operand)
8431 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
8433 offset_expr.X_op = O_constant;
8434 offset_expr.X_add_number = 0;
8439 if (!match_expression (&arg, &offset_expr, offset_reloc))
8442 /* '8' is used for SLTI(U) and has traditionally not
8443 been allowed to take relocation operators. */
8444 if (offset_reloc[0] != BFD_RELOC_UNUSED
8445 && (ext_operand->size != 16 || c == '8'))
8447 match_not_constant (&arg);
8451 if (offset_expr.X_op == O_big)
8453 match_out_of_range (&arg);
8462 if (mips_optional_operand_p (operand)
8464 && (arg.token[0].type != OT_REG
8465 || arg.token[1].type == OT_END))
8467 /* Assume that the register has been elided and is the
8468 same as the first operand. */
8473 if (!match_operand (&arg, operand))
8478 /* Record that the current instruction is invalid for the current ISA. */
8481 match_invalid_for_isa (void)
8484 (0, _("opcode not supported on this processor: %s (%s)"),
8485 mips_cpu_info_from_arch (mips_opts.arch)->name,
8486 mips_cpu_info_from_isa (mips_opts.isa)->name);
8489 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8490 Return true if a definite match or failure was found, storing any match
8491 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8492 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8493 tried and failed to match under normal conditions and now want to try a
8494 more relaxed match. */
8497 match_insns (struct mips_cl_insn *insn, const struct mips_opcode *first,
8498 const struct mips_opcode *past, struct mips_operand_token *tokens,
8499 int opcode_extra, bfd_boolean lax_match)
8501 const struct mips_opcode *opcode;
8502 const struct mips_opcode *invalid_delay_slot;
8503 bfd_boolean seen_valid_for_isa, seen_valid_for_size;
8505 /* Search for a match, ignoring alternatives that don't satisfy the
8506 current ISA or forced_length. */
8507 invalid_delay_slot = 0;
8508 seen_valid_for_isa = FALSE;
8509 seen_valid_for_size = FALSE;
8513 gas_assert (strcmp (opcode->name, first->name) == 0);
8514 if (is_opcode_valid (opcode))
8516 seen_valid_for_isa = TRUE;
8517 if (is_size_valid (opcode))
8519 bfd_boolean delay_slot_ok;
8521 seen_valid_for_size = TRUE;
8522 delay_slot_ok = is_delay_slot_valid (opcode);
8523 if (match_insn (insn, opcode, tokens, opcode_extra,
8524 lax_match, delay_slot_ok))
8528 if (!invalid_delay_slot)
8529 invalid_delay_slot = opcode;
8538 while (opcode < past && strcmp (opcode->name, first->name) == 0);
8540 /* If the only matches we found had the wrong length for the delay slot,
8541 pick the first such match. We'll issue an appropriate warning later. */
8542 if (invalid_delay_slot)
8544 if (match_insn (insn, invalid_delay_slot, tokens, opcode_extra,
8550 /* Handle the case where we didn't try to match an instruction because
8551 all the alternatives were incompatible with the current ISA. */
8552 if (!seen_valid_for_isa)
8554 match_invalid_for_isa ();
8558 /* Handle the case where we didn't try to match an instruction because
8559 all the alternatives were of the wrong size. */
8560 if (!seen_valid_for_size)
8562 if (mips_opts.insn32)
8563 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
8566 (0, _("unrecognized %d-bit version of microMIPS opcode"),
8567 8 * forced_insn_length);
8574 /* Like match_insns, but for MIPS16. */
8577 match_mips16_insns (struct mips_cl_insn *insn, const struct mips_opcode *first,
8578 struct mips_operand_token *tokens)
8580 const struct mips_opcode *opcode;
8581 bfd_boolean seen_valid_for_isa;
8582 bfd_boolean seen_valid_for_size;
8584 /* Search for a match, ignoring alternatives that don't satisfy the
8585 current ISA. There are no separate entries for extended forms so
8586 we deal with forced_length later. */
8587 seen_valid_for_isa = FALSE;
8588 seen_valid_for_size = FALSE;
8592 gas_assert (strcmp (opcode->name, first->name) == 0);
8593 if (is_opcode_valid_16 (opcode))
8595 seen_valid_for_isa = TRUE;
8596 if (is_size_valid_16 (opcode))
8598 seen_valid_for_size = TRUE;
8599 if (match_mips16_insn (insn, opcode, tokens))
8605 while (opcode < &mips16_opcodes[bfd_mips16_num_opcodes]
8606 && strcmp (opcode->name, first->name) == 0);
8608 /* Handle the case where we didn't try to match an instruction because
8609 all the alternatives were incompatible with the current ISA. */
8610 if (!seen_valid_for_isa)
8612 match_invalid_for_isa ();
8616 /* Handle the case where we didn't try to match an instruction because
8617 all the alternatives were of the wrong size. */
8618 if (!seen_valid_for_size)
8620 if (forced_insn_length == 2)
8622 (0, _("unrecognized unextended version of MIPS16 opcode"));
8625 (0, _("unrecognized extended version of MIPS16 opcode"));
8632 /* Set up global variables for the start of a new macro. */
8637 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
8638 memset (&mips_macro_warning.first_insn_sizes, 0,
8639 sizeof (mips_macro_warning.first_insn_sizes));
8640 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
8641 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
8642 && delayed_branch_p (&history[0]));
8644 && history[0].frag->fr_type == rs_machine_dependent
8645 && RELAX_MICROMIPS_P (history[0].frag->fr_subtype)
8646 && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype))
8647 mips_macro_warning.delay_slot_length = 0;
8649 switch (history[0].insn_mo->pinfo2
8650 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
8652 case INSN2_BRANCH_DELAY_32BIT:
8653 mips_macro_warning.delay_slot_length = 4;
8655 case INSN2_BRANCH_DELAY_16BIT:
8656 mips_macro_warning.delay_slot_length = 2;
8659 mips_macro_warning.delay_slot_length = 0;
8662 mips_macro_warning.first_frag = NULL;
8665 /* Given that a macro is longer than one instruction or of the wrong size,
8666 return the appropriate warning for it. Return null if no warning is
8667 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8668 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8669 and RELAX_NOMACRO. */
8672 macro_warning (relax_substateT subtype)
8674 if (subtype & RELAX_DELAY_SLOT)
8675 return _("macro instruction expanded into multiple instructions"
8676 " in a branch delay slot");
8677 else if (subtype & RELAX_NOMACRO)
8678 return _("macro instruction expanded into multiple instructions");
8679 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
8680 | RELAX_DELAY_SLOT_SIZE_SECOND))
8681 return ((subtype & RELAX_DELAY_SLOT_16BIT)
8682 ? _("macro instruction expanded into a wrong size instruction"
8683 " in a 16-bit branch delay slot")
8684 : _("macro instruction expanded into a wrong size instruction"
8685 " in a 32-bit branch delay slot"));
8690 /* Finish up a macro. Emit warnings as appropriate. */
8695 /* Relaxation warning flags. */
8696 relax_substateT subtype = 0;
8698 /* Check delay slot size requirements. */
8699 if (mips_macro_warning.delay_slot_length == 2)
8700 subtype |= RELAX_DELAY_SLOT_16BIT;
8701 if (mips_macro_warning.delay_slot_length != 0)
8703 if (mips_macro_warning.delay_slot_length
8704 != mips_macro_warning.first_insn_sizes[0])
8705 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
8706 if (mips_macro_warning.delay_slot_length
8707 != mips_macro_warning.first_insn_sizes[1])
8708 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
8711 /* Check instruction count requirements. */
8712 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
8714 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
8715 subtype |= RELAX_SECOND_LONGER;
8716 if (mips_opts.warn_about_macros)
8717 subtype |= RELAX_NOMACRO;
8718 if (mips_macro_warning.delay_slot_p)
8719 subtype |= RELAX_DELAY_SLOT;
8722 /* If both alternatives fail to fill a delay slot correctly,
8723 emit the warning now. */
8724 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
8725 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
8730 s = subtype & (RELAX_DELAY_SLOT_16BIT
8731 | RELAX_DELAY_SLOT_SIZE_FIRST
8732 | RELAX_DELAY_SLOT_SIZE_SECOND);
8733 msg = macro_warning (s);
8735 as_warn ("%s", msg);
8739 /* If both implementations are longer than 1 instruction, then emit the
8741 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
8746 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
8747 msg = macro_warning (s);
8749 as_warn ("%s", msg);
8753 /* If any flags still set, then one implementation might need a warning
8754 and the other either will need one of a different kind or none at all.
8755 Pass any remaining flags over to relaxation. */
8756 if (mips_macro_warning.first_frag != NULL)
8757 mips_macro_warning.first_frag->fr_subtype |= subtype;
8760 /* Instruction operand formats used in macros that vary between
8761 standard MIPS and microMIPS code. */
8763 static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } };
8764 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
8765 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
8766 static const char * const lui_fmt[2] = { "t,u", "s,u" };
8767 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
8768 static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } };
8769 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
8770 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
8772 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
8773 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8774 : cop12_fmt[mips_opts.micromips])
8775 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
8776 #define LUI_FMT (lui_fmt[mips_opts.micromips])
8777 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
8778 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
8779 : mem12_fmt[mips_opts.micromips])
8780 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
8781 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
8782 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
8784 /* Read a macro's relocation codes from *ARGS and store them in *R.
8785 The first argument in *ARGS will be either the code for a single
8786 relocation or -1 followed by the three codes that make up a
8787 composite relocation. */
8790 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
8794 next = va_arg (*args, int);
8796 r[0] = (bfd_reloc_code_real_type) next;
8799 for (i = 0; i < 3; i++)
8800 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
8801 /* This function is only used for 16-bit relocation fields.
8802 To make the macro code simpler, treat an unrelocated value
8803 in the same way as BFD_RELOC_LO16. */
8804 if (r[0] == BFD_RELOC_UNUSED)
8805 r[0] = BFD_RELOC_LO16;
8809 /* Build an instruction created by a macro expansion. This is passed
8810 a pointer to the count of instructions created so far, an
8811 expression, the name of the instruction to build, an operand format
8812 string, and corresponding arguments. */
8815 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
8817 const struct mips_opcode *mo = NULL;
8818 bfd_reloc_code_real_type r[3];
8819 const struct mips_opcode *amo;
8820 const struct mips_operand *operand;
8821 struct hash_control *hash;
8822 struct mips_cl_insn insn;
8826 va_start (args, fmt);
8828 if (mips_opts.mips16)
8830 mips16_macro_build (ep, name, fmt, &args);
8835 r[0] = BFD_RELOC_UNUSED;
8836 r[1] = BFD_RELOC_UNUSED;
8837 r[2] = BFD_RELOC_UNUSED;
8838 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
8839 amo = (struct mips_opcode *) hash_find (hash, name);
8841 gas_assert (strcmp (name, amo->name) == 0);
8845 /* Search until we get a match for NAME. It is assumed here that
8846 macros will never generate MDMX, MIPS-3D, or MT instructions.
8847 We try to match an instruction that fulfills the branch delay
8848 slot instruction length requirement (if any) of the previous
8849 instruction. While doing this we record the first instruction
8850 seen that matches all the other conditions and use it anyway
8851 if the requirement cannot be met; we will issue an appropriate
8852 warning later on. */
8853 if (strcmp (fmt, amo->args) == 0
8854 && amo->pinfo != INSN_MACRO
8855 && is_opcode_valid (amo)
8856 && is_size_valid (amo))
8858 if (is_delay_slot_valid (amo))
8868 gas_assert (amo->name);
8870 while (strcmp (name, amo->name) == 0);
8873 create_insn (&insn, mo);
8886 macro_read_relocs (&args, r);
8887 gas_assert (*r == BFD_RELOC_GPREL16
8888 || *r == BFD_RELOC_MIPS_HIGHER
8889 || *r == BFD_RELOC_HI16_S
8890 || *r == BFD_RELOC_LO16
8891 || *r == BFD_RELOC_MIPS_GOT_OFST
8892 || (mips_opts.micromips
8893 && (*r == BFD_RELOC_16
8894 || *r == BFD_RELOC_MIPS_GOT16
8895 || *r == BFD_RELOC_MIPS_CALL16
8896 || *r == BFD_RELOC_MIPS_GOT_HI16
8897 || *r == BFD_RELOC_MIPS_GOT_LO16
8898 || *r == BFD_RELOC_MIPS_CALL_HI16
8899 || *r == BFD_RELOC_MIPS_CALL_LO16
8900 || *r == BFD_RELOC_MIPS_SUB
8901 || *r == BFD_RELOC_MIPS_GOT_PAGE
8902 || *r == BFD_RELOC_MIPS_HIGHEST
8903 || *r == BFD_RELOC_MIPS_GOT_DISP
8904 || *r == BFD_RELOC_MIPS_TLS_GD
8905 || *r == BFD_RELOC_MIPS_TLS_LDM
8906 || *r == BFD_RELOC_MIPS_TLS_DTPREL_HI16
8907 || *r == BFD_RELOC_MIPS_TLS_DTPREL_LO16
8908 || *r == BFD_RELOC_MIPS_TLS_GOTTPREL
8909 || *r == BFD_RELOC_MIPS_TLS_TPREL_HI16
8910 || *r == BFD_RELOC_MIPS_TLS_TPREL_LO16)));
8914 macro_read_relocs (&args, r);
8918 macro_read_relocs (&args, r);
8919 gas_assert (ep != NULL
8920 && (ep->X_op == O_constant
8921 || (ep->X_op == O_symbol
8922 && (*r == BFD_RELOC_MIPS_HIGHEST
8923 || *r == BFD_RELOC_HI16_S
8924 || *r == BFD_RELOC_HI16
8925 || *r == BFD_RELOC_GPREL16
8926 || *r == BFD_RELOC_MIPS_GOT_HI16
8927 || *r == BFD_RELOC_MIPS_CALL_HI16))));
8931 gas_assert (ep != NULL);
8934 * This allows macro() to pass an immediate expression for
8935 * creating short branches without creating a symbol.
8937 * We don't allow branch relaxation for these branches, as
8938 * they should only appear in ".set nomacro" anyway.
8940 if (ep->X_op == O_constant)
8942 /* For microMIPS we always use relocations for branches.
8943 So we should not resolve immediate values. */
8944 gas_assert (!mips_opts.micromips);
8946 if ((ep->X_add_number & 3) != 0)
8947 as_bad (_("branch to misaligned address (0x%lx)"),
8948 (unsigned long) ep->X_add_number);
8949 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
8950 as_bad (_("branch address range overflow (0x%lx)"),
8951 (unsigned long) ep->X_add_number);
8952 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
8956 *r = BFD_RELOC_16_PCREL_S2;
8960 gas_assert (ep != NULL);
8961 *r = BFD_RELOC_MIPS_JMP;
8965 operand = (mips_opts.micromips
8966 ? decode_micromips_operand (fmt)
8967 : decode_mips_operand (fmt));
8971 uval = va_arg (args, int);
8972 if (operand->type == OP_CLO_CLZ_DEST)
8973 uval |= (uval << 5);
8974 insn_insert_operand (&insn, operand, uval);
8976 if (*fmt == '+' || *fmt == 'm' || *fmt == '-')
8982 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
8984 append_insn (&insn, ep, r, TRUE);
8988 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
8991 struct mips_opcode *mo;
8992 struct mips_cl_insn insn;
8993 const struct mips_operand *operand;
8994 bfd_reloc_code_real_type r[3]
8995 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
8997 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
8999 gas_assert (strcmp (name, mo->name) == 0);
9001 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
9004 gas_assert (mo->name);
9005 gas_assert (strcmp (name, mo->name) == 0);
9008 create_insn (&insn, mo);
9045 gas_assert (ep != NULL);
9047 if (ep->X_op != O_constant)
9048 *r = (int) BFD_RELOC_UNUSED + c;
9049 else if (calculate_reloc (*r, ep->X_add_number, &value))
9051 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode);
9053 *r = BFD_RELOC_UNUSED;
9059 operand = decode_mips16_operand (c, FALSE);
9063 insn_insert_operand (&insn, operand, va_arg (*args, int));
9068 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
9070 append_insn (&insn, ep, r, TRUE);
9074 * Generate a "jalr" instruction with a relocation hint to the called
9075 * function. This occurs in NewABI PIC code.
9078 macro_build_jalr (expressionS *ep, int cprestore)
9080 static const bfd_reloc_code_real_type jalr_relocs[2]
9081 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
9082 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
9086 if (MIPS_JALR_HINT_P (ep))
9091 if (mips_opts.micromips)
9093 jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32
9094 ? "jalr" : "jalrs");
9095 if (MIPS_JALR_HINT_P (ep)
9097 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
9098 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
9100 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
9103 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
9104 if (MIPS_JALR_HINT_P (ep))
9105 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
9109 * Generate a "lui" instruction.
9112 macro_build_lui (expressionS *ep, int regnum)
9114 gas_assert (! mips_opts.mips16);
9116 if (ep->X_op != O_constant)
9118 gas_assert (ep->X_op == O_symbol);
9119 /* _gp_disp is a special case, used from s_cpload.
9120 __gnu_local_gp is used if mips_no_shared. */
9121 gas_assert (mips_pic == NO_PIC
9123 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
9124 || (! mips_in_shared
9125 && strcmp (S_GET_NAME (ep->X_add_symbol),
9126 "__gnu_local_gp") == 0));
9129 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
9132 /* Generate a sequence of instructions to do a load or store from a constant
9133 offset off of a base register (breg) into/from a target register (treg),
9134 using AT if necessary. */
9136 macro_build_ldst_constoffset (expressionS *ep, const char *op,
9137 int treg, int breg, int dbl)
9139 gas_assert (ep->X_op == O_constant);
9141 /* Sign-extending 32-bit constants makes their handling easier. */
9143 normalize_constant_expr (ep);
9145 /* Right now, this routine can only handle signed 32-bit constants. */
9146 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
9147 as_warn (_("operand overflow"));
9149 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
9151 /* Signed 16-bit offset will fit in the op. Easy! */
9152 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
9156 /* 32-bit offset, need multiple instructions and AT, like:
9157 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
9158 addu $tempreg,$tempreg,$breg
9159 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
9160 to handle the complete offset. */
9161 macro_build_lui (ep, AT);
9162 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
9163 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
9166 as_bad (_("macro used $at after \".set noat\""));
9171 * Generates code to set the $at register to true (one)
9172 * if reg is less than the immediate expression.
9175 set_at (int reg, int unsignedp)
9177 if (imm_expr.X_add_number >= -0x8000
9178 && imm_expr.X_add_number < 0x8000)
9179 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
9180 AT, reg, BFD_RELOC_LO16);
9183 load_register (AT, &imm_expr, GPR_SIZE == 64);
9184 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
9188 /* Count the leading zeroes by performing a binary chop. This is a
9189 bulky bit of source, but performance is a LOT better for the
9190 majority of values than a simple loop to count the bits:
9191 for (lcnt = 0; (lcnt < 32); lcnt++)
9192 if ((v) & (1 << (31 - lcnt)))
9194 However it is not code size friendly, and the gain will drop a bit
9195 on certain cached systems.
9197 #define COUNT_TOP_ZEROES(v) \
9198 (((v) & ~0xffff) == 0 \
9199 ? ((v) & ~0xff) == 0 \
9200 ? ((v) & ~0xf) == 0 \
9201 ? ((v) & ~0x3) == 0 \
9202 ? ((v) & ~0x1) == 0 \
9207 : ((v) & ~0x7) == 0 \
9210 : ((v) & ~0x3f) == 0 \
9211 ? ((v) & ~0x1f) == 0 \
9214 : ((v) & ~0x7f) == 0 \
9217 : ((v) & ~0xfff) == 0 \
9218 ? ((v) & ~0x3ff) == 0 \
9219 ? ((v) & ~0x1ff) == 0 \
9222 : ((v) & ~0x7ff) == 0 \
9225 : ((v) & ~0x3fff) == 0 \
9226 ? ((v) & ~0x1fff) == 0 \
9229 : ((v) & ~0x7fff) == 0 \
9232 : ((v) & ~0xffffff) == 0 \
9233 ? ((v) & ~0xfffff) == 0 \
9234 ? ((v) & ~0x3ffff) == 0 \
9235 ? ((v) & ~0x1ffff) == 0 \
9238 : ((v) & ~0x7ffff) == 0 \
9241 : ((v) & ~0x3fffff) == 0 \
9242 ? ((v) & ~0x1fffff) == 0 \
9245 : ((v) & ~0x7fffff) == 0 \
9248 : ((v) & ~0xfffffff) == 0 \
9249 ? ((v) & ~0x3ffffff) == 0 \
9250 ? ((v) & ~0x1ffffff) == 0 \
9253 : ((v) & ~0x7ffffff) == 0 \
9256 : ((v) & ~0x3fffffff) == 0 \
9257 ? ((v) & ~0x1fffffff) == 0 \
9260 : ((v) & ~0x7fffffff) == 0 \
9265 * This routine generates the least number of instructions necessary to load
9266 * an absolute expression value into a register.
9269 load_register (int reg, expressionS *ep, int dbl)
9272 expressionS hi32, lo32;
9274 if (ep->X_op != O_big)
9276 gas_assert (ep->X_op == O_constant);
9278 /* Sign-extending 32-bit constants makes their handling easier. */
9280 normalize_constant_expr (ep);
9282 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
9284 /* We can handle 16 bit signed values with an addiu to
9285 $zero. No need to ever use daddiu here, since $zero and
9286 the result are always correct in 32 bit mode. */
9287 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
9290 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
9292 /* We can handle 16 bit unsigned values with an ori to
9294 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
9297 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
9299 /* 32 bit values require an lui. */
9300 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
9301 if ((ep->X_add_number & 0xffff) != 0)
9302 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
9307 /* The value is larger than 32 bits. */
9309 if (!dbl || GPR_SIZE == 32)
9313 sprintf_vma (value, ep->X_add_number);
9314 as_bad (_("number (0x%s) larger than 32 bits"), value);
9315 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
9319 if (ep->X_op != O_big)
9322 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
9323 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
9324 hi32.X_add_number &= 0xffffffff;
9326 lo32.X_add_number &= 0xffffffff;
9330 gas_assert (ep->X_add_number > 2);
9331 if (ep->X_add_number == 3)
9332 generic_bignum[3] = 0;
9333 else if (ep->X_add_number > 4)
9334 as_bad (_("number larger than 64 bits"));
9335 lo32.X_op = O_constant;
9336 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
9337 hi32.X_op = O_constant;
9338 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
9341 if (hi32.X_add_number == 0)
9346 unsigned long hi, lo;
9348 if (hi32.X_add_number == (offsetT) 0xffffffff)
9350 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
9352 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
9355 if (lo32.X_add_number & 0x80000000)
9357 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
9358 if (lo32.X_add_number & 0xffff)
9359 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
9364 /* Check for 16bit shifted constant. We know that hi32 is
9365 non-zero, so start the mask on the first bit of the hi32
9370 unsigned long himask, lomask;
9374 himask = 0xffff >> (32 - shift);
9375 lomask = (0xffff << shift) & 0xffffffff;
9379 himask = 0xffff << (shift - 32);
9382 if ((hi32.X_add_number & ~(offsetT) himask) == 0
9383 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
9387 tmp.X_op = O_constant;
9389 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
9390 | (lo32.X_add_number >> shift));
9392 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
9393 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
9394 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
9395 reg, reg, (shift >= 32) ? shift - 32 : shift);
9400 while (shift <= (64 - 16));
9402 /* Find the bit number of the lowest one bit, and store the
9403 shifted value in hi/lo. */
9404 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
9405 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
9409 while ((lo & 1) == 0)
9414 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
9420 while ((hi & 1) == 0)
9429 /* Optimize if the shifted value is a (power of 2) - 1. */
9430 if ((hi == 0 && ((lo + 1) & lo) == 0)
9431 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
9433 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
9438 /* This instruction will set the register to be all
9440 tmp.X_op = O_constant;
9441 tmp.X_add_number = (offsetT) -1;
9442 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
9446 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
9447 reg, reg, (bit >= 32) ? bit - 32 : bit);
9449 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
9450 reg, reg, (shift >= 32) ? shift - 32 : shift);
9455 /* Sign extend hi32 before calling load_register, because we can
9456 generally get better code when we load a sign extended value. */
9457 if ((hi32.X_add_number & 0x80000000) != 0)
9458 hi32.X_add_number |= ~(offsetT) 0xffffffff;
9459 load_register (reg, &hi32, 0);
9462 if ((lo32.X_add_number & 0xffff0000) == 0)
9466 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
9474 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
9476 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
9477 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
9483 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
9487 mid16.X_add_number >>= 16;
9488 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
9489 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
9492 if ((lo32.X_add_number & 0xffff) != 0)
9493 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
9497 load_delay_nop (void)
9499 if (!gpr_interlocks)
9500 macro_build (NULL, "nop", "");
9503 /* Load an address into a register. */
9506 load_address (int reg, expressionS *ep, int *used_at)
9508 if (ep->X_op != O_constant
9509 && ep->X_op != O_symbol)
9511 as_bad (_("expression too complex"));
9512 ep->X_op = O_constant;
9515 if (ep->X_op == O_constant)
9517 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
9521 if (mips_pic == NO_PIC)
9523 /* If this is a reference to a GP relative symbol, we want
9524 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
9526 lui $reg,<sym> (BFD_RELOC_HI16_S)
9527 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9528 If we have an addend, we always use the latter form.
9530 With 64bit address space and a usable $at we want
9531 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9532 lui $at,<sym> (BFD_RELOC_HI16_S)
9533 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9534 daddiu $at,<sym> (BFD_RELOC_LO16)
9538 If $at is already in use, we use a path which is suboptimal
9539 on superscalar processors.
9540 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9541 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9543 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9545 daddiu $reg,<sym> (BFD_RELOC_LO16)
9547 For GP relative symbols in 64bit address space we can use
9548 the same sequence as in 32bit address space. */
9549 if (HAVE_64BIT_SYMBOLS)
9551 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
9552 && !nopic_need_relax (ep->X_add_symbol, 1))
9554 relax_start (ep->X_add_symbol);
9555 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
9556 mips_gp_register, BFD_RELOC_GPREL16);
9560 if (*used_at == 0 && mips_opts.at)
9562 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
9563 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
9564 macro_build (ep, "daddiu", "t,r,j", reg, reg,
9565 BFD_RELOC_MIPS_HIGHER);
9566 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
9567 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
9568 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
9573 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
9574 macro_build (ep, "daddiu", "t,r,j", reg, reg,
9575 BFD_RELOC_MIPS_HIGHER);
9576 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
9577 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
9578 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
9579 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
9582 if (mips_relax.sequence)
9587 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
9588 && !nopic_need_relax (ep->X_add_symbol, 1))
9590 relax_start (ep->X_add_symbol);
9591 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
9592 mips_gp_register, BFD_RELOC_GPREL16);
9595 macro_build_lui (ep, reg);
9596 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
9597 reg, reg, BFD_RELOC_LO16);
9598 if (mips_relax.sequence)
9602 else if (!mips_big_got)
9606 /* If this is a reference to an external symbol, we want
9607 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9609 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9611 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9612 If there is a constant, it must be added in after.
9614 If we have NewABI, we want
9615 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9616 unless we're referencing a global symbol with a non-zero
9617 offset, in which case cst must be added separately. */
9620 if (ep->X_add_number)
9622 ex.X_add_number = ep->X_add_number;
9623 ep->X_add_number = 0;
9624 relax_start (ep->X_add_symbol);
9625 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9626 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9627 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9628 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9629 ex.X_op = O_constant;
9630 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
9631 reg, reg, BFD_RELOC_LO16);
9632 ep->X_add_number = ex.X_add_number;
9635 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9636 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9637 if (mips_relax.sequence)
9642 ex.X_add_number = ep->X_add_number;
9643 ep->X_add_number = 0;
9644 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9645 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9647 relax_start (ep->X_add_symbol);
9649 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9653 if (ex.X_add_number != 0)
9655 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9656 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9657 ex.X_op = O_constant;
9658 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
9659 reg, reg, BFD_RELOC_LO16);
9663 else if (mips_big_got)
9667 /* This is the large GOT case. If this is a reference to an
9668 external symbol, we want
9669 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9671 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
9673 Otherwise, for a reference to a local symbol in old ABI, we want
9674 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9676 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9677 If there is a constant, it must be added in after.
9679 In the NewABI, for local symbols, with or without offsets, we want:
9680 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9681 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9685 ex.X_add_number = ep->X_add_number;
9686 ep->X_add_number = 0;
9687 relax_start (ep->X_add_symbol);
9688 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
9689 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9690 reg, reg, mips_gp_register);
9691 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
9692 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
9693 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9694 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9695 else if (ex.X_add_number)
9697 ex.X_op = O_constant;
9698 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9702 ep->X_add_number = ex.X_add_number;
9704 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9705 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
9706 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9707 BFD_RELOC_MIPS_GOT_OFST);
9712 ex.X_add_number = ep->X_add_number;
9713 ep->X_add_number = 0;
9714 relax_start (ep->X_add_symbol);
9715 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
9716 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9717 reg, reg, mips_gp_register);
9718 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
9719 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
9721 if (reg_needs_delay (mips_gp_register))
9723 /* We need a nop before loading from $gp. This special
9724 check is required because the lui which starts the main
9725 instruction stream does not refer to $gp, and so will not
9726 insert the nop which may be required. */
9727 macro_build (NULL, "nop", "");
9729 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9730 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9732 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9736 if (ex.X_add_number != 0)
9738 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9739 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9740 ex.X_op = O_constant;
9741 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9749 if (!mips_opts.at && *used_at == 1)
9750 as_bad (_("macro used $at after \".set noat\""));
9753 /* Move the contents of register SOURCE into register DEST. */
9756 move_register (int dest, int source)
9758 /* Prefer to use a 16-bit microMIPS instruction unless the previous
9759 instruction specifically requires a 32-bit one. */
9760 if (mips_opts.micromips
9761 && !mips_opts.insn32
9762 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
9763 macro_build (NULL, "move", "mp,mj", dest, source);
9765 macro_build (NULL, "or", "d,v,t", dest, source, 0);
9768 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
9769 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
9770 The two alternatives are:
9772 Global symbol Local symbol
9773 ------------- ------------
9774 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
9776 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
9778 load_got_offset emits the first instruction and add_got_offset
9779 emits the second for a 16-bit offset or add_got_offset_hilo emits
9780 a sequence to add a 32-bit offset using a scratch register. */
9783 load_got_offset (int dest, expressionS *local)
9788 global.X_add_number = 0;
9790 relax_start (local->X_add_symbol);
9791 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
9792 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9794 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
9795 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9800 add_got_offset (int dest, expressionS *local)
9804 global.X_op = O_constant;
9805 global.X_op_symbol = NULL;
9806 global.X_add_symbol = NULL;
9807 global.X_add_number = local->X_add_number;
9809 relax_start (local->X_add_symbol);
9810 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
9811 dest, dest, BFD_RELOC_LO16);
9813 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
9818 add_got_offset_hilo (int dest, expressionS *local, int tmp)
9821 int hold_mips_optimize;
9823 global.X_op = O_constant;
9824 global.X_op_symbol = NULL;
9825 global.X_add_symbol = NULL;
9826 global.X_add_number = local->X_add_number;
9828 relax_start (local->X_add_symbol);
9829 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
9831 /* Set mips_optimize around the lui instruction to avoid
9832 inserting an unnecessary nop after the lw. */
9833 hold_mips_optimize = mips_optimize;
9835 macro_build_lui (&global, tmp);
9836 mips_optimize = hold_mips_optimize;
9837 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
9840 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
9843 /* Emit a sequence of instructions to emulate a branch likely operation.
9844 BR is an ordinary branch corresponding to one to be emulated. BRNEG
9845 is its complementing branch with the original condition negated.
9846 CALL is set if the original branch specified the link operation.
9847 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
9849 Code like this is produced in the noreorder mode:
9854 delay slot (executed only if branch taken)
9862 delay slot (executed only if branch taken)
9865 In the reorder mode the delay slot would be filled with a nop anyway,
9866 so code produced is simply:
9871 This function is used when producing code for the microMIPS ASE that
9872 does not implement branch likely instructions in hardware. */
9875 macro_build_branch_likely (const char *br, const char *brneg,
9876 int call, expressionS *ep, const char *fmt,
9877 unsigned int sreg, unsigned int treg)
9879 int noreorder = mips_opts.noreorder;
9882 gas_assert (mips_opts.micromips);
9886 micromips_label_expr (&expr1);
9887 macro_build (&expr1, brneg, fmt, sreg, treg);
9888 macro_build (NULL, "nop", "");
9889 macro_build (ep, call ? "bal" : "b", "p");
9891 /* Set to true so that append_insn adds a label. */
9892 emit_branch_likely_macro = TRUE;
9896 macro_build (ep, br, fmt, sreg, treg);
9897 macro_build (NULL, "nop", "");
9902 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
9903 the condition code tested. EP specifies the branch target. */
9906 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
9933 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
9936 /* Emit a two-argument branch macro specified by TYPE, using SREG as
9937 the register tested. EP specifies the branch target. */
9940 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
9942 const char *brneg = NULL;
9952 br = mips_opts.micromips ? "bgez" : "bgezl";
9956 gas_assert (mips_opts.micromips);
9957 br = mips_opts.insn32 ? "bgezal" : "bgezals";
9965 br = mips_opts.micromips ? "bgtz" : "bgtzl";
9972 br = mips_opts.micromips ? "blez" : "blezl";
9979 br = mips_opts.micromips ? "bltz" : "bltzl";
9983 gas_assert (mips_opts.micromips);
9984 br = mips_opts.insn32 ? "bltzal" : "bltzals";
9991 if (mips_opts.micromips && brneg)
9992 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
9994 macro_build (ep, br, "s,p", sreg);
9997 /* Emit a three-argument branch macro specified by TYPE, using SREG and
9998 TREG as the registers tested. EP specifies the branch target. */
10001 macro_build_branch_rsrt (int type, expressionS *ep,
10002 unsigned int sreg, unsigned int treg)
10004 const char *brneg = NULL;
10005 const int call = 0;
10016 br = mips_opts.micromips ? "beq" : "beql";
10025 br = mips_opts.micromips ? "bne" : "bnel";
10031 if (mips_opts.micromips && brneg)
10032 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
10034 macro_build (ep, br, "s,t,p", sreg, treg);
10037 /* Return the high part that should be loaded in order to make the low
10038 part of VALUE accessible using an offset of OFFBITS bits. */
10041 offset_high_part (offsetT value, unsigned int offbits)
10048 bias = 1 << (offbits - 1);
10049 low_mask = bias * 2 - 1;
10050 return (value + bias) & ~low_mask;
10053 /* Return true if the value stored in offset_expr and offset_reloc
10054 fits into a signed offset of OFFBITS bits. RANGE is the maximum
10055 amount that the caller wants to add without inducing overflow
10056 and ALIGN is the known alignment of the value in bytes. */
10059 small_offset_p (unsigned int range, unsigned int align, unsigned int offbits)
10063 /* Accept any relocation operator if overflow isn't a concern. */
10064 if (range < align && *offset_reloc != BFD_RELOC_UNUSED)
10067 /* These relocations are guaranteed not to overflow in correct links. */
10068 if (*offset_reloc == BFD_RELOC_MIPS_LITERAL
10069 || gprel16_reloc_p (*offset_reloc))
10072 if (offset_expr.X_op == O_constant
10073 && offset_high_part (offset_expr.X_add_number, offbits) == 0
10074 && offset_high_part (offset_expr.X_add_number + range, offbits) == 0)
10081 * This routine implements the seemingly endless macro or synthesized
10082 * instructions and addressing modes in the mips assembly language. Many
10083 * of these macros are simple and are similar to each other. These could
10084 * probably be handled by some kind of table or grammar approach instead of
10085 * this verbose method. Others are not simple macros but are more like
10086 * optimizing code generation.
10087 * One interesting optimization is when several store macros appear
10088 * consecutively that would load AT with the upper half of the same address.
10089 * The ensuing load upper instructions are omitted. This implies some kind
10090 * of global optimization. We currently only optimize within a single macro.
10091 * For many of the load and store macros if the address is specified as a
10092 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
10093 * first load register 'at' with zero and use it as the base register. The
10094 * mips assembler simply uses register $zero. Just one tiny optimization
10098 macro (struct mips_cl_insn *ip, char *str)
10100 const struct mips_operand_array *operands;
10101 unsigned int breg, i;
10102 unsigned int tempreg;
10105 expressionS label_expr;
10120 bfd_boolean large_offset;
10122 int hold_mips_optimize;
10123 unsigned int align;
10124 unsigned int op[MAX_OPERANDS];
10126 gas_assert (! mips_opts.mips16);
10128 operands = insn_operands (ip);
10129 for (i = 0; i < MAX_OPERANDS; i++)
10130 if (operands->operand[i])
10131 op[i] = insn_extract_operand (ip, operands->operand[i]);
10135 mask = ip->insn_mo->mask;
10137 label_expr.X_op = O_constant;
10138 label_expr.X_op_symbol = NULL;
10139 label_expr.X_add_symbol = NULL;
10140 label_expr.X_add_number = 0;
10142 expr1.X_op = O_constant;
10143 expr1.X_op_symbol = NULL;
10144 expr1.X_add_symbol = NULL;
10145 expr1.X_add_number = 1;
10152 /* Fall through. */
10160 start_noreorder ();
10162 if (mips_opts.micromips)
10163 micromips_label_expr (&label_expr);
10165 label_expr.X_add_number = 8;
10166 macro_build (&label_expr, "bgez", "s,p", op[1]);
10167 if (op[0] == op[1])
10168 macro_build (NULL, "nop", "");
10170 move_register (op[0], op[1]);
10171 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", op[0], 0, op[1]);
10172 if (mips_opts.micromips)
10173 micromips_add_label ();
10190 if (!mips_opts.micromips)
10192 if (imm_expr.X_add_number >= -0x200
10193 && imm_expr.X_add_number < 0x200)
10195 macro_build (NULL, s, "t,r,.", op[0], op[1],
10196 (int) imm_expr.X_add_number);
10205 if (imm_expr.X_add_number >= -0x8000
10206 && imm_expr.X_add_number < 0x8000)
10208 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
10213 load_register (AT, &imm_expr, dbl);
10214 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
10233 if (imm_expr.X_add_number >= 0
10234 && imm_expr.X_add_number < 0x10000)
10236 if (mask != M_NOR_I)
10237 macro_build (&imm_expr, s, "t,r,i", op[0], op[1], BFD_RELOC_LO16);
10240 macro_build (&imm_expr, "ori", "t,r,i",
10241 op[0], op[1], BFD_RELOC_LO16);
10242 macro_build (NULL, "nor", "d,v,t", op[0], op[0], 0);
10248 load_register (AT, &imm_expr, GPR_SIZE == 64);
10249 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
10253 switch (imm_expr.X_add_number)
10256 macro_build (NULL, "nop", "");
10259 macro_build (NULL, "packrl.ph", "d,s,t", op[0], op[0], op[1]);
10263 macro_build (NULL, "balign", "t,s,2", op[0], op[1],
10264 (int) imm_expr.X_add_number);
10267 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
10268 (unsigned long) imm_expr.X_add_number);
10277 gas_assert (mips_opts.micromips);
10278 macro_build_branch_ccl (mask, &offset_expr,
10279 EXTRACT_OPERAND (1, BCC, *ip));
10286 if (imm_expr.X_add_number == 0)
10292 load_register (op[1], &imm_expr, GPR_SIZE == 64);
10294 /* Fall through. */
10297 macro_build_branch_rsrt (mask, &offset_expr, op[0], op[1]);
10302 /* Fall through. */
10305 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[0]);
10306 else if (op[0] == 0)
10307 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[1]);
10311 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
10312 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10313 &offset_expr, AT, ZERO);
10323 macro_build_branch_rs (mask, &offset_expr, op[0]);
10328 /* Fall through. */
10330 /* Check for > max integer. */
10331 if (imm_expr.X_add_number >= GPR_SMAX)
10334 /* Result is always false. */
10336 macro_build (NULL, "nop", "");
10338 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
10341 ++imm_expr.X_add_number;
10345 if (mask == M_BGEL_I)
10347 if (imm_expr.X_add_number == 0)
10349 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
10350 &offset_expr, op[0]);
10353 if (imm_expr.X_add_number == 1)
10355 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
10356 &offset_expr, op[0]);
10359 if (imm_expr.X_add_number <= GPR_SMIN)
10362 /* result is always true */
10363 as_warn (_("branch %s is always true"), ip->insn_mo->name);
10364 macro_build (&offset_expr, "b", "p");
10369 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10370 &offset_expr, AT, ZERO);
10375 /* Fall through. */
10379 else if (op[0] == 0)
10380 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10381 &offset_expr, ZERO, op[1]);
10385 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
10386 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10387 &offset_expr, AT, ZERO);
10393 /* Fall through. */
10397 && imm_expr.X_add_number == -1))
10399 ++imm_expr.X_add_number;
10403 if (mask == M_BGEUL_I)
10405 if (imm_expr.X_add_number == 0)
10407 else if (imm_expr.X_add_number == 1)
10408 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10409 &offset_expr, op[0], ZERO);
10414 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10415 &offset_expr, AT, ZERO);
10421 /* Fall through. */
10424 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[0]);
10425 else if (op[0] == 0)
10426 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[1]);
10430 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
10431 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10432 &offset_expr, AT, ZERO);
10438 /* Fall through. */
10441 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10442 &offset_expr, op[0], ZERO);
10443 else if (op[0] == 0)
10448 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
10449 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10450 &offset_expr, AT, ZERO);
10456 /* Fall through. */
10459 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
10460 else if (op[0] == 0)
10461 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[1]);
10465 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
10466 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10467 &offset_expr, AT, ZERO);
10473 /* Fall through. */
10475 if (imm_expr.X_add_number >= GPR_SMAX)
10477 ++imm_expr.X_add_number;
10481 if (mask == M_BLTL_I)
10483 if (imm_expr.X_add_number == 0)
10484 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
10485 else if (imm_expr.X_add_number == 1)
10486 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
10491 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10492 &offset_expr, AT, ZERO);
10498 /* Fall through. */
10501 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10502 &offset_expr, op[0], ZERO);
10503 else if (op[0] == 0)
10508 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
10509 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10510 &offset_expr, AT, ZERO);
10516 /* Fall through. */
10520 && imm_expr.X_add_number == -1))
10522 ++imm_expr.X_add_number;
10526 if (mask == M_BLTUL_I)
10528 if (imm_expr.X_add_number == 0)
10530 else if (imm_expr.X_add_number == 1)
10531 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10532 &offset_expr, op[0], ZERO);
10537 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10538 &offset_expr, AT, ZERO);
10544 /* Fall through. */
10547 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
10548 else if (op[0] == 0)
10549 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[1]);
10553 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
10554 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10555 &offset_expr, AT, ZERO);
10561 /* Fall through. */
10565 else if (op[0] == 0)
10566 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10567 &offset_expr, ZERO, op[1]);
10571 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
10572 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10573 &offset_expr, AT, ZERO);
10579 /* Fall through. */
10585 /* Fall through. */
10591 as_warn (_("divide by zero"));
10593 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
10595 macro_build (NULL, "break", BRK_FMT, 7);
10599 start_noreorder ();
10602 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
10603 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
10607 if (mips_opts.micromips)
10608 micromips_label_expr (&label_expr);
10610 label_expr.X_add_number = 8;
10611 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
10612 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
10613 macro_build (NULL, "break", BRK_FMT, 7);
10614 if (mips_opts.micromips)
10615 micromips_add_label ();
10617 expr1.X_add_number = -1;
10619 load_register (AT, &expr1, dbl);
10620 if (mips_opts.micromips)
10621 micromips_label_expr (&label_expr);
10623 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
10624 macro_build (&label_expr, "bne", "s,t,p", op[2], AT);
10627 expr1.X_add_number = 1;
10628 load_register (AT, &expr1, dbl);
10629 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
10633 expr1.X_add_number = 0x80000000;
10634 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
10638 macro_build (NULL, "teq", TRAP_FMT, op[1], AT, 6);
10639 /* We want to close the noreorder block as soon as possible, so
10640 that later insns are available for delay slot filling. */
10645 if (mips_opts.micromips)
10646 micromips_label_expr (&label_expr);
10648 label_expr.X_add_number = 8;
10649 macro_build (&label_expr, "bne", "s,t,p", op[1], AT);
10650 macro_build (NULL, "nop", "");
10652 /* We want to close the noreorder block as soon as possible, so
10653 that later insns are available for delay slot filling. */
10656 macro_build (NULL, "break", BRK_FMT, 6);
10658 if (mips_opts.micromips)
10659 micromips_add_label ();
10660 macro_build (NULL, s, MFHL_FMT, op[0]);
10699 if (imm_expr.X_add_number == 0)
10701 as_warn (_("divide by zero"));
10703 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
10705 macro_build (NULL, "break", BRK_FMT, 7);
10708 if (imm_expr.X_add_number == 1)
10710 if (strcmp (s2, "mflo") == 0)
10711 move_register (op[0], op[1]);
10713 move_register (op[0], ZERO);
10716 if (imm_expr.X_add_number == -1 && s[strlen (s) - 1] != 'u')
10718 if (strcmp (s2, "mflo") == 0)
10719 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", op[0], op[1]);
10721 move_register (op[0], ZERO);
10726 load_register (AT, &imm_expr, dbl);
10727 macro_build (NULL, s, "z,s,t", op[1], AT);
10728 macro_build (NULL, s2, MFHL_FMT, op[0]);
10747 start_noreorder ();
10750 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
10751 macro_build (NULL, s, "z,s,t", op[1], op[2]);
10752 /* We want to close the noreorder block as soon as possible, so
10753 that later insns are available for delay slot filling. */
10758 if (mips_opts.micromips)
10759 micromips_label_expr (&label_expr);
10761 label_expr.X_add_number = 8;
10762 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
10763 macro_build (NULL, s, "z,s,t", op[1], op[2]);
10765 /* We want to close the noreorder block as soon as possible, so
10766 that later insns are available for delay slot filling. */
10768 macro_build (NULL, "break", BRK_FMT, 7);
10769 if (mips_opts.micromips)
10770 micromips_add_label ();
10772 macro_build (NULL, s2, MFHL_FMT, op[0]);
10777 /* Fall through. */
10783 /* Fall through. */
10786 /* Load the address of a symbol into a register. If breg is not
10787 zero, we then add a base register to it. */
10790 if (dbl && GPR_SIZE == 32)
10791 as_warn (_("dla used to load 32-bit register; recommend using la "
10794 if (!dbl && HAVE_64BIT_OBJECTS)
10795 as_warn (_("la used to load 64-bit address; recommend using dla "
10798 if (small_offset_p (0, align, 16))
10800 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", op[0], breg,
10801 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
10805 if (mips_opts.at && (op[0] == breg))
10813 if (offset_expr.X_op != O_symbol
10814 && offset_expr.X_op != O_constant)
10816 as_bad (_("expression too complex"));
10817 offset_expr.X_op = O_constant;
10820 if (offset_expr.X_op == O_constant)
10821 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
10822 else if (mips_pic == NO_PIC)
10824 /* If this is a reference to a GP relative symbol, we want
10825 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
10827 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10828 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10829 If we have a constant, we need two instructions anyhow,
10830 so we may as well always use the latter form.
10832 With 64bit address space and a usable $at we want
10833 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10834 lui $at,<sym> (BFD_RELOC_HI16_S)
10835 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10836 daddiu $at,<sym> (BFD_RELOC_LO16)
10838 daddu $tempreg,$tempreg,$at
10840 If $at is already in use, we use a path which is suboptimal
10841 on superscalar processors.
10842 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10843 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10845 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10847 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
10849 For GP relative symbols in 64bit address space we can use
10850 the same sequence as in 32bit address space. */
10851 if (HAVE_64BIT_SYMBOLS)
10853 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10854 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10856 relax_start (offset_expr.X_add_symbol);
10857 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10858 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
10862 if (used_at == 0 && mips_opts.at)
10864 macro_build (&offset_expr, "lui", LUI_FMT,
10865 tempreg, BFD_RELOC_MIPS_HIGHEST);
10866 macro_build (&offset_expr, "lui", LUI_FMT,
10867 AT, BFD_RELOC_HI16_S);
10868 macro_build (&offset_expr, "daddiu", "t,r,j",
10869 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
10870 macro_build (&offset_expr, "daddiu", "t,r,j",
10871 AT, AT, BFD_RELOC_LO16);
10872 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
10873 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
10878 macro_build (&offset_expr, "lui", LUI_FMT,
10879 tempreg, BFD_RELOC_MIPS_HIGHEST);
10880 macro_build (&offset_expr, "daddiu", "t,r,j",
10881 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
10882 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
10883 macro_build (&offset_expr, "daddiu", "t,r,j",
10884 tempreg, tempreg, BFD_RELOC_HI16_S);
10885 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
10886 macro_build (&offset_expr, "daddiu", "t,r,j",
10887 tempreg, tempreg, BFD_RELOC_LO16);
10890 if (mips_relax.sequence)
10895 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10896 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10898 relax_start (offset_expr.X_add_symbol);
10899 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10900 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
10903 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
10904 as_bad (_("offset too large"));
10905 macro_build_lui (&offset_expr, tempreg);
10906 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10907 tempreg, tempreg, BFD_RELOC_LO16);
10908 if (mips_relax.sequence)
10912 else if (!mips_big_got && !HAVE_NEWABI)
10914 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
10916 /* If this is a reference to an external symbol, and there
10917 is no constant, we want
10918 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10919 or for lca or if tempreg is PIC_CALL_REG
10920 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10921 For a local symbol, we want
10922 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10924 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10926 If we have a small constant, and this is a reference to
10927 an external symbol, we want
10928 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10930 addiu $tempreg,$tempreg,<constant>
10931 For a local symbol, we want the same instruction
10932 sequence, but we output a BFD_RELOC_LO16 reloc on the
10935 If we have a large constant, and this is a reference to
10936 an external symbol, we want
10937 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10938 lui $at,<hiconstant>
10939 addiu $at,$at,<loconstant>
10940 addu $tempreg,$tempreg,$at
10941 For a local symbol, we want the same instruction
10942 sequence, but we output a BFD_RELOC_LO16 reloc on the
10946 if (offset_expr.X_add_number == 0)
10948 if (mips_pic == SVR4_PIC
10950 && (call || tempreg == PIC_CALL_REG))
10951 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
10953 relax_start (offset_expr.X_add_symbol);
10954 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10955 lw_reloc_type, mips_gp_register);
10958 /* We're going to put in an addu instruction using
10959 tempreg, so we may as well insert the nop right
10964 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10965 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
10967 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10968 tempreg, tempreg, BFD_RELOC_LO16);
10970 /* FIXME: If breg == 0, and the next instruction uses
10971 $tempreg, then if this variant case is used an extra
10972 nop will be generated. */
10974 else if (offset_expr.X_add_number >= -0x8000
10975 && offset_expr.X_add_number < 0x8000)
10977 load_got_offset (tempreg, &offset_expr);
10979 add_got_offset (tempreg, &offset_expr);
10983 expr1.X_add_number = offset_expr.X_add_number;
10984 offset_expr.X_add_number =
10985 SEXT_16BIT (offset_expr.X_add_number);
10986 load_got_offset (tempreg, &offset_expr);
10987 offset_expr.X_add_number = expr1.X_add_number;
10988 /* If we are going to add in a base register, and the
10989 target register and the base register are the same,
10990 then we are using AT as a temporary register. Since
10991 we want to load the constant into AT, we add our
10992 current AT (from the global offset table) and the
10993 register into the register now, and pretend we were
10994 not using a base register. */
10998 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11003 add_got_offset_hilo (tempreg, &offset_expr, AT);
11007 else if (!mips_big_got && HAVE_NEWABI)
11009 int add_breg_early = 0;
11011 /* If this is a reference to an external, and there is no
11012 constant, or local symbol (*), with or without a
11014 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11015 or for lca or if tempreg is PIC_CALL_REG
11016 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11018 If we have a small constant, and this is a reference to
11019 an external symbol, we want
11020 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11021 addiu $tempreg,$tempreg,<constant>
11023 If we have a large constant, and this is a reference to
11024 an external symbol, we want
11025 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11026 lui $at,<hiconstant>
11027 addiu $at,$at,<loconstant>
11028 addu $tempreg,$tempreg,$at
11030 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
11031 local symbols, even though it introduces an additional
11034 if (offset_expr.X_add_number)
11036 expr1.X_add_number = offset_expr.X_add_number;
11037 offset_expr.X_add_number = 0;
11039 relax_start (offset_expr.X_add_symbol);
11040 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11041 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
11043 if (expr1.X_add_number >= -0x8000
11044 && expr1.X_add_number < 0x8000)
11046 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
11047 tempreg, tempreg, BFD_RELOC_LO16);
11049 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
11053 /* If we are going to add in a base register, and the
11054 target register and the base register are the same,
11055 then we are using AT as a temporary register. Since
11056 we want to load the constant into AT, we add our
11057 current AT (from the global offset table) and the
11058 register into the register now, and pretend we were
11059 not using a base register. */
11064 gas_assert (tempreg == AT);
11065 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11068 add_breg_early = 1;
11071 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
11072 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11078 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11081 offset_expr.X_add_number = expr1.X_add_number;
11083 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11084 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
11085 if (add_breg_early)
11087 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11088 op[0], tempreg, breg);
11094 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
11096 relax_start (offset_expr.X_add_symbol);
11097 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11098 BFD_RELOC_MIPS_CALL16, mips_gp_register);
11100 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11101 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
11106 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11107 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
11110 else if (mips_big_got && !HAVE_NEWABI)
11113 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
11114 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
11115 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
11117 /* This is the large GOT case. If this is a reference to an
11118 external symbol, and there is no constant, we want
11119 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11120 addu $tempreg,$tempreg,$gp
11121 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11122 or for lca or if tempreg is PIC_CALL_REG
11123 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11124 addu $tempreg,$tempreg,$gp
11125 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11126 For a local symbol, we want
11127 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11129 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11131 If we have a small constant, and this is a reference to
11132 an external symbol, we want
11133 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11134 addu $tempreg,$tempreg,$gp
11135 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11137 addiu $tempreg,$tempreg,<constant>
11138 For a local symbol, we want
11139 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11141 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
11143 If we have a large constant, and this is a reference to
11144 an external symbol, we want
11145 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11146 addu $tempreg,$tempreg,$gp
11147 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11148 lui $at,<hiconstant>
11149 addiu $at,$at,<loconstant>
11150 addu $tempreg,$tempreg,$at
11151 For a local symbol, we want
11152 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11153 lui $at,<hiconstant>
11154 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
11155 addu $tempreg,$tempreg,$at
11158 expr1.X_add_number = offset_expr.X_add_number;
11159 offset_expr.X_add_number = 0;
11160 relax_start (offset_expr.X_add_symbol);
11161 gpdelay = reg_needs_delay (mips_gp_register);
11162 if (expr1.X_add_number == 0 && breg == 0
11163 && (call || tempreg == PIC_CALL_REG))
11165 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
11166 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
11168 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
11169 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11170 tempreg, tempreg, mips_gp_register);
11171 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11172 tempreg, lw_reloc_type, tempreg);
11173 if (expr1.X_add_number == 0)
11177 /* We're going to put in an addu instruction using
11178 tempreg, so we may as well insert the nop right
11183 else if (expr1.X_add_number >= -0x8000
11184 && expr1.X_add_number < 0x8000)
11187 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
11188 tempreg, tempreg, BFD_RELOC_LO16);
11194 /* If we are going to add in a base register, and the
11195 target register and the base register are the same,
11196 then we are using AT as a temporary register. Since
11197 we want to load the constant into AT, we add our
11198 current AT (from the global offset table) and the
11199 register into the register now, and pretend we were
11200 not using a base register. */
11205 gas_assert (tempreg == AT);
11207 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11212 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
11213 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
11217 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number);
11222 /* This is needed because this instruction uses $gp, but
11223 the first instruction on the main stream does not. */
11224 macro_build (NULL, "nop", "");
11227 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11228 local_reloc_type, mips_gp_register);
11229 if (expr1.X_add_number >= -0x8000
11230 && expr1.X_add_number < 0x8000)
11233 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11234 tempreg, tempreg, BFD_RELOC_LO16);
11235 /* FIXME: If add_number is 0, and there was no base
11236 register, the external symbol case ended with a load,
11237 so if the symbol turns out to not be external, and
11238 the next instruction uses tempreg, an unnecessary nop
11239 will be inserted. */
11245 /* We must add in the base register now, as in the
11246 external symbol case. */
11247 gas_assert (tempreg == AT);
11249 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11252 /* We set breg to 0 because we have arranged to add
11253 it in in both cases. */
11257 macro_build_lui (&expr1, AT);
11258 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11259 AT, AT, BFD_RELOC_LO16);
11260 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11261 tempreg, tempreg, AT);
11266 else if (mips_big_got && HAVE_NEWABI)
11268 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
11269 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
11270 int add_breg_early = 0;
11272 /* This is the large GOT case. If this is a reference to an
11273 external symbol, and there is no constant, we want
11274 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11275 add $tempreg,$tempreg,$gp
11276 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11277 or for lca or if tempreg is PIC_CALL_REG
11278 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11279 add $tempreg,$tempreg,$gp
11280 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11282 If we have a small constant, and this is a reference to
11283 an external symbol, we want
11284 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11285 add $tempreg,$tempreg,$gp
11286 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11287 addi $tempreg,$tempreg,<constant>
11289 If we have a large constant, and this is a reference to
11290 an external symbol, we want
11291 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11292 addu $tempreg,$tempreg,$gp
11293 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11294 lui $at,<hiconstant>
11295 addi $at,$at,<loconstant>
11296 add $tempreg,$tempreg,$at
11298 If we have NewABI, and we know it's a local symbol, we want
11299 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11300 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
11301 otherwise we have to resort to GOT_HI16/GOT_LO16. */
11303 relax_start (offset_expr.X_add_symbol);
11305 expr1.X_add_number = offset_expr.X_add_number;
11306 offset_expr.X_add_number = 0;
11308 if (expr1.X_add_number == 0 && breg == 0
11309 && (call || tempreg == PIC_CALL_REG))
11311 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
11312 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
11314 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
11315 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11316 tempreg, tempreg, mips_gp_register);
11317 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11318 tempreg, lw_reloc_type, tempreg);
11320 if (expr1.X_add_number == 0)
11322 else if (expr1.X_add_number >= -0x8000
11323 && expr1.X_add_number < 0x8000)
11325 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
11326 tempreg, tempreg, BFD_RELOC_LO16);
11328 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
11332 /* If we are going to add in a base register, and the
11333 target register and the base register are the same,
11334 then we are using AT as a temporary register. Since
11335 we want to load the constant into AT, we add our
11336 current AT (from the global offset table) and the
11337 register into the register now, and pretend we were
11338 not using a base register. */
11343 gas_assert (tempreg == AT);
11344 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11347 add_breg_early = 1;
11350 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
11351 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
11356 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11359 offset_expr.X_add_number = expr1.X_add_number;
11360 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11361 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
11362 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
11363 tempreg, BFD_RELOC_MIPS_GOT_OFST);
11364 if (add_breg_early)
11366 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11367 op[0], tempreg, breg);
11377 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", op[0], tempreg, breg);
11381 gas_assert (!mips_opts.micromips);
11382 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x01);
11386 gas_assert (!mips_opts.micromips);
11387 macro_build (NULL, "c2", "C", 0x02);
11391 gas_assert (!mips_opts.micromips);
11392 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x02);
11396 gas_assert (!mips_opts.micromips);
11397 macro_build (NULL, "c2", "C", 3);
11401 gas_assert (!mips_opts.micromips);
11402 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x03);
11406 /* The j instruction may not be used in PIC code, since it
11407 requires an absolute address. We convert it to a b
11409 if (mips_pic == NO_PIC)
11410 macro_build (&offset_expr, "j", "a");
11412 macro_build (&offset_expr, "b", "p");
11415 /* The jal instructions must be handled as macros because when
11416 generating PIC code they expand to multi-instruction
11417 sequences. Normally they are simple instructions. */
11421 /* Fall through. */
11423 gas_assert (mips_opts.micromips);
11424 if (mips_opts.insn32)
11426 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str);
11434 /* Fall through. */
11437 if (mips_pic == NO_PIC)
11439 s = jals ? "jalrs" : "jalr";
11440 if (mips_opts.micromips
11441 && !mips_opts.insn32
11443 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
11444 macro_build (NULL, s, "mj", op[1]);
11446 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
11450 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
11451 && mips_cprestore_offset >= 0);
11453 if (op[1] != PIC_CALL_REG)
11454 as_warn (_("MIPS PIC call to register other than $25"));
11456 s = ((mips_opts.micromips
11457 && !mips_opts.insn32
11458 && (!mips_opts.noreorder || cprestore))
11459 ? "jalrs" : "jalr");
11460 if (mips_opts.micromips
11461 && !mips_opts.insn32
11463 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
11464 macro_build (NULL, s, "mj", op[1]);
11466 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
11467 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
11469 if (mips_cprestore_offset < 0)
11470 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11473 if (!mips_frame_reg_valid)
11475 as_warn (_("no .frame pseudo-op used in PIC code"));
11476 /* Quiet this warning. */
11477 mips_frame_reg_valid = 1;
11479 if (!mips_cprestore_valid)
11481 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11482 /* Quiet this warning. */
11483 mips_cprestore_valid = 1;
11485 if (mips_opts.noreorder)
11486 macro_build (NULL, "nop", "");
11487 expr1.X_add_number = mips_cprestore_offset;
11488 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
11491 HAVE_64BIT_ADDRESSES);
11499 gas_assert (mips_opts.micromips);
11500 if (mips_opts.insn32)
11502 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str);
11506 /* Fall through. */
11508 if (mips_pic == NO_PIC)
11509 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
11510 else if (mips_pic == SVR4_PIC)
11512 /* If this is a reference to an external symbol, and we are
11513 using a small GOT, we want
11514 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11518 lw $gp,cprestore($sp)
11519 The cprestore value is set using the .cprestore
11520 pseudo-op. If we are using a big GOT, we want
11521 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11523 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11527 lw $gp,cprestore($sp)
11528 If the symbol is not external, we want
11529 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11531 addiu $25,$25,<sym> (BFD_RELOC_LO16)
11534 lw $gp,cprestore($sp)
11536 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11537 sequences above, minus nops, unless the symbol is local,
11538 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11544 relax_start (offset_expr.X_add_symbol);
11545 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11546 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
11549 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11550 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
11556 relax_start (offset_expr.X_add_symbol);
11557 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
11558 BFD_RELOC_MIPS_CALL_HI16);
11559 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
11560 PIC_CALL_REG, mips_gp_register);
11561 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11562 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
11565 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11566 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
11568 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11569 PIC_CALL_REG, PIC_CALL_REG,
11570 BFD_RELOC_MIPS_GOT_OFST);
11574 macro_build_jalr (&offset_expr, 0);
11578 relax_start (offset_expr.X_add_symbol);
11581 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11582 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
11591 gpdelay = reg_needs_delay (mips_gp_register);
11592 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
11593 BFD_RELOC_MIPS_CALL_HI16);
11594 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
11595 PIC_CALL_REG, mips_gp_register);
11596 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11597 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
11602 macro_build (NULL, "nop", "");
11604 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11605 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
11608 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11609 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
11611 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
11613 if (mips_cprestore_offset < 0)
11614 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11617 if (!mips_frame_reg_valid)
11619 as_warn (_("no .frame pseudo-op used in PIC code"));
11620 /* Quiet this warning. */
11621 mips_frame_reg_valid = 1;
11623 if (!mips_cprestore_valid)
11625 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11626 /* Quiet this warning. */
11627 mips_cprestore_valid = 1;
11629 if (mips_opts.noreorder)
11630 macro_build (NULL, "nop", "");
11631 expr1.X_add_number = mips_cprestore_offset;
11632 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
11635 HAVE_64BIT_ADDRESSES);
11639 else if (mips_pic == VXWORKS_PIC)
11640 as_bad (_("non-PIC jump used in PIC library"));
11747 gas_assert (!mips_opts.micromips);
11750 /* Itbl support may require additional care here. */
11756 /* Itbl support may require additional care here. */
11762 offbits = (mips_opts.micromips ? 12
11763 : ISA_IS_R6 (mips_opts.isa) ? 11
11765 /* Itbl support may require additional care here. */
11769 gas_assert (!mips_opts.micromips);
11772 /* Itbl support may require additional care here. */
11778 offbits = (mips_opts.micromips ? 12 : 16);
11783 offbits = (mips_opts.micromips ? 12 : 16);
11788 /* Itbl support may require additional care here. */
11794 offbits = (mips_opts.micromips ? 12
11795 : ISA_IS_R6 (mips_opts.isa) ? 11
11797 /* Itbl support may require additional care here. */
11803 /* Itbl support may require additional care here. */
11809 /* Itbl support may require additional care here. */
11815 offbits = (mips_opts.micromips ? 12 : 16);
11820 offbits = (mips_opts.micromips ? 12 : 16);
11825 offbits = (mips_opts.micromips ? 12
11826 : ISA_IS_R6 (mips_opts.isa) ? 9
11832 offbits = (mips_opts.micromips ? 12
11833 : ISA_IS_R6 (mips_opts.isa) ? 9
11839 offbits = (mips_opts.micromips ? 12 : 16);
11842 gas_assert (mips_opts.micromips);
11849 gas_assert (mips_opts.micromips);
11856 gas_assert (mips_opts.micromips);
11862 gas_assert (mips_opts.micromips);
11869 /* We don't want to use $0 as tempreg. */
11870 if (op[2] == op[0] + lp || op[0] + lp == ZERO)
11873 tempreg = op[0] + lp;
11889 gas_assert (!mips_opts.micromips);
11892 /* Itbl support may require additional care here. */
11898 /* Itbl support may require additional care here. */
11904 offbits = (mips_opts.micromips ? 12
11905 : ISA_IS_R6 (mips_opts.isa) ? 11
11907 /* Itbl support may require additional care here. */
11911 gas_assert (!mips_opts.micromips);
11914 /* Itbl support may require additional care here. */
11920 offbits = (mips_opts.micromips ? 12 : 16);
11925 offbits = (mips_opts.micromips ? 12 : 16);
11930 offbits = (mips_opts.micromips ? 12
11931 : ISA_IS_R6 (mips_opts.isa) ? 9
11937 offbits = (mips_opts.micromips ? 12
11938 : ISA_IS_R6 (mips_opts.isa) ? 9
11943 fmt = (mips_opts.micromips ? "k,~(b)"
11944 : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)"
11946 offbits = (mips_opts.micromips ? 12
11947 : ISA_IS_R6 (mips_opts.isa) ? 9
11957 fmt = (mips_opts.micromips ? "k,~(b)"
11958 : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)"
11960 offbits = (mips_opts.micromips ? 12
11961 : ISA_IS_R6 (mips_opts.isa) ? 9
11973 /* Itbl support may require additional care here. */
11978 offbits = (mips_opts.micromips ? 12
11979 : ISA_IS_R6 (mips_opts.isa) ? 11
11981 /* Itbl support may require additional care here. */
11987 /* Itbl support may require additional care here. */
11991 gas_assert (!mips_opts.micromips);
11994 /* Itbl support may require additional care here. */
12000 offbits = (mips_opts.micromips ? 12 : 16);
12005 offbits = (mips_opts.micromips ? 12 : 16);
12008 gas_assert (mips_opts.micromips);
12014 gas_assert (mips_opts.micromips);
12020 gas_assert (mips_opts.micromips);
12026 gas_assert (mips_opts.micromips);
12035 if (small_offset_p (0, align, 16))
12037 /* The first case exists for M_LD_AB and M_SD_AB, which are
12038 macros for o32 but which should act like normal instructions
12041 macro_build (&offset_expr, s, fmt, op[0], -1, offset_reloc[0],
12042 offset_reloc[1], offset_reloc[2], breg);
12043 else if (small_offset_p (0, align, offbits))
12046 macro_build (NULL, s, fmt, op[0], breg);
12048 macro_build (NULL, s, fmt, op[0],
12049 (int) offset_expr.X_add_number, breg);
12055 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
12056 tempreg, breg, -1, offset_reloc[0],
12057 offset_reloc[1], offset_reloc[2]);
12059 macro_build (NULL, s, fmt, op[0], tempreg);
12061 macro_build (NULL, s, fmt, op[0], 0, tempreg);
12069 if (offset_expr.X_op != O_constant
12070 && offset_expr.X_op != O_symbol)
12072 as_bad (_("expression too complex"));
12073 offset_expr.X_op = O_constant;
12076 if (HAVE_32BIT_ADDRESSES
12077 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
12081 sprintf_vma (value, offset_expr.X_add_number);
12082 as_bad (_("number (0x%s) larger than 32 bits"), value);
12085 /* A constant expression in PIC code can be handled just as it
12086 is in non PIC code. */
12087 if (offset_expr.X_op == O_constant)
12089 expr1.X_add_number = offset_high_part (offset_expr.X_add_number,
12090 offbits == 0 ? 16 : offbits);
12091 offset_expr.X_add_number -= expr1.X_add_number;
12093 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
12095 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12096 tempreg, tempreg, breg);
12099 if (offset_expr.X_add_number != 0)
12100 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
12101 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
12102 macro_build (NULL, s, fmt, op[0], tempreg);
12104 else if (offbits == 16)
12105 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
12107 macro_build (NULL, s, fmt, op[0],
12108 (int) offset_expr.X_add_number, tempreg);
12110 else if (offbits != 16)
12112 /* The offset field is too narrow to be used for a low-part
12113 relocation, so load the whole address into the auxiliary
12115 load_address (tempreg, &offset_expr, &used_at);
12117 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12118 tempreg, tempreg, breg);
12120 macro_build (NULL, s, fmt, op[0], tempreg);
12122 macro_build (NULL, s, fmt, op[0], 0, tempreg);
12124 else if (mips_pic == NO_PIC)
12126 /* If this is a reference to a GP relative symbol, and there
12127 is no base register, we want
12128 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12129 Otherwise, if there is no base register, we want
12130 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12131 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12132 If we have a constant, we need two instructions anyhow,
12133 so we always use the latter form.
12135 If we have a base register, and this is a reference to a
12136 GP relative symbol, we want
12137 addu $tempreg,$breg,$gp
12138 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
12140 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12141 addu $tempreg,$tempreg,$breg
12142 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12143 With a constant we always use the latter case.
12145 With 64bit address space and no base register and $at usable,
12147 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12148 lui $at,<sym> (BFD_RELOC_HI16_S)
12149 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12152 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12153 If we have a base register, we want
12154 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12155 lui $at,<sym> (BFD_RELOC_HI16_S)
12156 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12160 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12162 Without $at we can't generate the optimal path for superscalar
12163 processors here since this would require two temporary registers.
12164 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12165 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12167 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12169 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12170 If we have a base register, we want
12171 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12172 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12174 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12176 daddu $tempreg,$tempreg,$breg
12177 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12179 For GP relative symbols in 64bit address space we can use
12180 the same sequence as in 32bit address space. */
12181 if (HAVE_64BIT_SYMBOLS)
12183 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
12184 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
12186 relax_start (offset_expr.X_add_symbol);
12189 macro_build (&offset_expr, s, fmt, op[0],
12190 BFD_RELOC_GPREL16, mips_gp_register);
12194 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12195 tempreg, breg, mips_gp_register);
12196 macro_build (&offset_expr, s, fmt, op[0],
12197 BFD_RELOC_GPREL16, tempreg);
12202 if (used_at == 0 && mips_opts.at)
12204 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
12205 BFD_RELOC_MIPS_HIGHEST);
12206 macro_build (&offset_expr, "lui", LUI_FMT, AT,
12208 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
12209 tempreg, BFD_RELOC_MIPS_HIGHER);
12211 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
12212 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
12213 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
12214 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16,
12220 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
12221 BFD_RELOC_MIPS_HIGHEST);
12222 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
12223 tempreg, BFD_RELOC_MIPS_HIGHER);
12224 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
12225 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
12226 tempreg, BFD_RELOC_HI16_S);
12227 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
12229 macro_build (NULL, "daddu", "d,v,t",
12230 tempreg, tempreg, breg);
12231 macro_build (&offset_expr, s, fmt, op[0],
12232 BFD_RELOC_LO16, tempreg);
12235 if (mips_relax.sequence)
12242 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
12243 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
12245 relax_start (offset_expr.X_add_symbol);
12246 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_GPREL16,
12250 macro_build_lui (&offset_expr, tempreg);
12251 macro_build (&offset_expr, s, fmt, op[0],
12252 BFD_RELOC_LO16, tempreg);
12253 if (mips_relax.sequence)
12258 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
12259 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
12261 relax_start (offset_expr.X_add_symbol);
12262 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12263 tempreg, breg, mips_gp_register);
12264 macro_build (&offset_expr, s, fmt, op[0],
12265 BFD_RELOC_GPREL16, tempreg);
12268 macro_build_lui (&offset_expr, tempreg);
12269 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12270 tempreg, tempreg, breg);
12271 macro_build (&offset_expr, s, fmt, op[0],
12272 BFD_RELOC_LO16, tempreg);
12273 if (mips_relax.sequence)
12277 else if (!mips_big_got)
12279 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
12281 /* If this is a reference to an external symbol, we want
12282 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12284 <op> op[0],0($tempreg)
12286 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12288 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12289 <op> op[0],0($tempreg)
12291 For NewABI, we want
12292 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12293 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
12295 If there is a base register, we add it to $tempreg before
12296 the <op>. If there is a constant, we stick it in the
12297 <op> instruction. We don't handle constants larger than
12298 16 bits, because we have no way to load the upper 16 bits
12299 (actually, we could handle them for the subset of cases
12300 in which we are not using $at). */
12301 gas_assert (offset_expr.X_op == O_symbol);
12304 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12305 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
12307 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12308 tempreg, tempreg, breg);
12309 macro_build (&offset_expr, s, fmt, op[0],
12310 BFD_RELOC_MIPS_GOT_OFST, tempreg);
12313 expr1.X_add_number = offset_expr.X_add_number;
12314 offset_expr.X_add_number = 0;
12315 if (expr1.X_add_number < -0x8000
12316 || expr1.X_add_number >= 0x8000)
12317 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12318 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12319 lw_reloc_type, mips_gp_register);
12321 relax_start (offset_expr.X_add_symbol);
12323 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
12324 tempreg, BFD_RELOC_LO16);
12327 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12328 tempreg, tempreg, breg);
12329 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
12331 else if (mips_big_got && !HAVE_NEWABI)
12335 /* If this is a reference to an external symbol, we want
12336 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12337 addu $tempreg,$tempreg,$gp
12338 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12339 <op> op[0],0($tempreg)
12341 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12343 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12344 <op> op[0],0($tempreg)
12345 If there is a base register, we add it to $tempreg before
12346 the <op>. If there is a constant, we stick it in the
12347 <op> instruction. We don't handle constants larger than
12348 16 bits, because we have no way to load the upper 16 bits
12349 (actually, we could handle them for the subset of cases
12350 in which we are not using $at). */
12351 gas_assert (offset_expr.X_op == O_symbol);
12352 expr1.X_add_number = offset_expr.X_add_number;
12353 offset_expr.X_add_number = 0;
12354 if (expr1.X_add_number < -0x8000
12355 || expr1.X_add_number >= 0x8000)
12356 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12357 gpdelay = reg_needs_delay (mips_gp_register);
12358 relax_start (offset_expr.X_add_symbol);
12359 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
12360 BFD_RELOC_MIPS_GOT_HI16);
12361 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
12363 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12364 BFD_RELOC_MIPS_GOT_LO16, tempreg);
12367 macro_build (NULL, "nop", "");
12368 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12369 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12371 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
12372 tempreg, BFD_RELOC_LO16);
12376 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12377 tempreg, tempreg, breg);
12378 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
12380 else if (mips_big_got && HAVE_NEWABI)
12382 /* If this is a reference to an external symbol, we want
12383 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12384 add $tempreg,$tempreg,$gp
12385 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12386 <op> op[0],<ofst>($tempreg)
12387 Otherwise, for local symbols, we want:
12388 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12389 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
12390 gas_assert (offset_expr.X_op == O_symbol);
12391 expr1.X_add_number = offset_expr.X_add_number;
12392 offset_expr.X_add_number = 0;
12393 if (expr1.X_add_number < -0x8000
12394 || expr1.X_add_number >= 0x8000)
12395 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12396 relax_start (offset_expr.X_add_symbol);
12397 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
12398 BFD_RELOC_MIPS_GOT_HI16);
12399 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
12401 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12402 BFD_RELOC_MIPS_GOT_LO16, tempreg);
12404 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12405 tempreg, tempreg, breg);
12406 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
12409 offset_expr.X_add_number = expr1.X_add_number;
12410 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12411 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
12413 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12414 tempreg, tempreg, breg);
12415 macro_build (&offset_expr, s, fmt, op[0],
12416 BFD_RELOC_MIPS_GOT_OFST, tempreg);
12425 gas_assert (mips_opts.micromips);
12426 gas_assert (mips_opts.insn32);
12427 start_noreorder ();
12428 macro_build (NULL, "jr", "s", RA);
12429 expr1.X_add_number = op[0] << 2;
12430 macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16);
12435 gas_assert (mips_opts.micromips);
12436 gas_assert (mips_opts.insn32);
12437 macro_build (NULL, "jr", "s", op[0]);
12438 if (mips_opts.noreorder)
12439 macro_build (NULL, "nop", "");
12444 load_register (op[0], &imm_expr, 0);
12448 load_register (op[0], &imm_expr, 1);
12452 if (imm_expr.X_op == O_constant)
12455 load_register (AT, &imm_expr, 0);
12456 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
12461 gas_assert (imm_expr.X_op == O_absent
12462 && offset_expr.X_op == O_symbol
12463 && strcmp (segment_name (S_GET_SEGMENT
12464 (offset_expr.X_add_symbol)),
12466 && offset_expr.X_add_number == 0);
12467 macro_build (&offset_expr, "lwc1", "T,o(b)", op[0],
12468 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
12473 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12474 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12475 order 32 bits of the value and the low order 32 bits are either
12476 zero or in OFFSET_EXPR. */
12477 if (imm_expr.X_op == O_constant)
12479 if (GPR_SIZE == 64)
12480 load_register (op[0], &imm_expr, 1);
12485 if (target_big_endian)
12497 load_register (hreg, &imm_expr, 0);
12500 if (offset_expr.X_op == O_absent)
12501 move_register (lreg, 0);
12504 gas_assert (offset_expr.X_op == O_constant);
12505 load_register (lreg, &offset_expr, 0);
12511 gas_assert (imm_expr.X_op == O_absent);
12513 /* We know that sym is in the .rdata section. First we get the
12514 upper 16 bits of the address. */
12515 if (mips_pic == NO_PIC)
12517 macro_build_lui (&offset_expr, AT);
12522 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12523 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12527 /* Now we load the register(s). */
12528 if (GPR_SIZE == 64)
12531 macro_build (&offset_expr, "ld", "t,o(b)", op[0],
12532 BFD_RELOC_LO16, AT);
12537 macro_build (&offset_expr, "lw", "t,o(b)", op[0],
12538 BFD_RELOC_LO16, AT);
12541 /* FIXME: How in the world do we deal with the possible
12543 offset_expr.X_add_number += 4;
12544 macro_build (&offset_expr, "lw", "t,o(b)",
12545 op[0] + 1, BFD_RELOC_LO16, AT);
12551 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12552 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12553 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12554 the value and the low order 32 bits are either zero or in
12556 if (imm_expr.X_op == O_constant)
12559 load_register (AT, &imm_expr, FPR_SIZE == 64);
12560 if (FPR_SIZE == 64 && GPR_SIZE == 64)
12561 macro_build (NULL, "dmtc1", "t,S", AT, op[0]);
12564 if (ISA_HAS_MXHC1 (mips_opts.isa))
12565 macro_build (NULL, "mthc1", "t,G", AT, op[0]);
12566 else if (FPR_SIZE != 32)
12567 as_bad (_("Unable to generate `%s' compliant code "
12569 (FPR_SIZE == 64) ? "fp64" : "fpxx");
12571 macro_build (NULL, "mtc1", "t,G", AT, op[0] + 1);
12572 if (offset_expr.X_op == O_absent)
12573 macro_build (NULL, "mtc1", "t,G", 0, op[0]);
12576 gas_assert (offset_expr.X_op == O_constant);
12577 load_register (AT, &offset_expr, 0);
12578 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
12584 gas_assert (imm_expr.X_op == O_absent
12585 && offset_expr.X_op == O_symbol
12586 && offset_expr.X_add_number == 0);
12587 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
12588 if (strcmp (s, ".lit8") == 0)
12590 op[2] = mips_gp_register;
12591 offset_reloc[0] = BFD_RELOC_MIPS_LITERAL;
12592 offset_reloc[1] = BFD_RELOC_UNUSED;
12593 offset_reloc[2] = BFD_RELOC_UNUSED;
12597 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
12599 if (mips_pic != NO_PIC)
12600 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12601 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12604 /* FIXME: This won't work for a 64 bit address. */
12605 macro_build_lui (&offset_expr, AT);
12609 offset_reloc[0] = BFD_RELOC_LO16;
12610 offset_reloc[1] = BFD_RELOC_UNUSED;
12611 offset_reloc[2] = BFD_RELOC_UNUSED;
12618 * The MIPS assembler seems to check for X_add_number not
12619 * being double aligned and generating:
12620 * lui at,%hi(foo+1)
12622 * addiu at,at,%lo(foo+1)
12625 * But, the resulting address is the same after relocation so why
12626 * generate the extra instruction?
12628 /* Itbl support may require additional care here. */
12631 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
12640 gas_assert (!mips_opts.micromips);
12641 /* Itbl support may require additional care here. */
12644 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
12664 if (GPR_SIZE == 64)
12674 if (GPR_SIZE == 64)
12682 /* Even on a big endian machine $fn comes before $fn+1. We have
12683 to adjust when loading from memory. We set coproc if we must
12684 load $fn+1 first. */
12685 /* Itbl support may require additional care here. */
12686 if (!target_big_endian)
12690 if (small_offset_p (0, align, 16))
12693 if (!small_offset_p (4, align, 16))
12695 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg,
12696 -1, offset_reloc[0], offset_reloc[1],
12698 expr1.X_add_number = 0;
12702 offset_reloc[0] = BFD_RELOC_LO16;
12703 offset_reloc[1] = BFD_RELOC_UNUSED;
12704 offset_reloc[2] = BFD_RELOC_UNUSED;
12706 if (strcmp (s, "lw") == 0 && op[0] == breg)
12708 ep->X_add_number += 4;
12709 macro_build (ep, s, fmt, op[0] + 1, -1, offset_reloc[0],
12710 offset_reloc[1], offset_reloc[2], breg);
12711 ep->X_add_number -= 4;
12712 macro_build (ep, s, fmt, op[0], -1, offset_reloc[0],
12713 offset_reloc[1], offset_reloc[2], breg);
12717 macro_build (ep, s, fmt, coproc ? op[0] + 1 : op[0], -1,
12718 offset_reloc[0], offset_reloc[1], offset_reloc[2],
12720 ep->X_add_number += 4;
12721 macro_build (ep, s, fmt, coproc ? op[0] : op[0] + 1, -1,
12722 offset_reloc[0], offset_reloc[1], offset_reloc[2],
12728 if (offset_expr.X_op != O_symbol
12729 && offset_expr.X_op != O_constant)
12731 as_bad (_("expression too complex"));
12732 offset_expr.X_op = O_constant;
12735 if (HAVE_32BIT_ADDRESSES
12736 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
12740 sprintf_vma (value, offset_expr.X_add_number);
12741 as_bad (_("number (0x%s) larger than 32 bits"), value);
12744 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
12746 /* If this is a reference to a GP relative symbol, we want
12747 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12748 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
12749 If we have a base register, we use this
12751 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
12752 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
12753 If this is not a GP relative symbol, we want
12754 lui $at,<sym> (BFD_RELOC_HI16_S)
12755 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12756 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12757 If there is a base register, we add it to $at after the
12758 lui instruction. If there is a constant, we always use
12760 if (offset_expr.X_op == O_symbol
12761 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
12762 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
12764 relax_start (offset_expr.X_add_symbol);
12767 tempreg = mips_gp_register;
12771 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12772 AT, breg, mips_gp_register);
12777 /* Itbl support may require additional care here. */
12778 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12779 BFD_RELOC_GPREL16, tempreg);
12780 offset_expr.X_add_number += 4;
12782 /* Set mips_optimize to 2 to avoid inserting an
12784 hold_mips_optimize = mips_optimize;
12786 /* Itbl support may require additional care here. */
12787 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12788 BFD_RELOC_GPREL16, tempreg);
12789 mips_optimize = hold_mips_optimize;
12793 offset_expr.X_add_number -= 4;
12796 if (offset_high_part (offset_expr.X_add_number, 16)
12797 != offset_high_part (offset_expr.X_add_number + 4, 16))
12799 load_address (AT, &offset_expr, &used_at);
12800 offset_expr.X_op = O_constant;
12801 offset_expr.X_add_number = 0;
12804 macro_build_lui (&offset_expr, AT);
12806 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12807 /* Itbl support may require additional care here. */
12808 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12809 BFD_RELOC_LO16, AT);
12810 /* FIXME: How do we handle overflow here? */
12811 offset_expr.X_add_number += 4;
12812 /* Itbl support may require additional care here. */
12813 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12814 BFD_RELOC_LO16, AT);
12815 if (mips_relax.sequence)
12818 else if (!mips_big_got)
12820 /* If this is a reference to an external symbol, we want
12821 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12824 <op> op[0]+1,4($at)
12826 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12828 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12829 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12830 If there is a base register we add it to $at before the
12831 lwc1 instructions. If there is a constant we include it
12832 in the lwc1 instructions. */
12834 expr1.X_add_number = offset_expr.X_add_number;
12835 if (expr1.X_add_number < -0x8000
12836 || expr1.X_add_number >= 0x8000 - 4)
12837 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12838 load_got_offset (AT, &offset_expr);
12841 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12843 /* Set mips_optimize to 2 to avoid inserting an undesired
12845 hold_mips_optimize = mips_optimize;
12848 /* Itbl support may require additional care here. */
12849 relax_start (offset_expr.X_add_symbol);
12850 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
12851 BFD_RELOC_LO16, AT);
12852 expr1.X_add_number += 4;
12853 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
12854 BFD_RELOC_LO16, AT);
12856 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12857 BFD_RELOC_LO16, AT);
12858 offset_expr.X_add_number += 4;
12859 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12860 BFD_RELOC_LO16, AT);
12863 mips_optimize = hold_mips_optimize;
12865 else if (mips_big_got)
12869 /* If this is a reference to an external symbol, we want
12870 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12872 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
12875 <op> op[0]+1,4($at)
12877 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12879 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12880 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12881 If there is a base register we add it to $at before the
12882 lwc1 instructions. If there is a constant we include it
12883 in the lwc1 instructions. */
12885 expr1.X_add_number = offset_expr.X_add_number;
12886 offset_expr.X_add_number = 0;
12887 if (expr1.X_add_number < -0x8000
12888 || expr1.X_add_number >= 0x8000 - 4)
12889 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12890 gpdelay = reg_needs_delay (mips_gp_register);
12891 relax_start (offset_expr.X_add_symbol);
12892 macro_build (&offset_expr, "lui", LUI_FMT,
12893 AT, BFD_RELOC_MIPS_GOT_HI16);
12894 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12895 AT, AT, mips_gp_register);
12896 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
12897 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
12900 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12901 /* Itbl support may require additional care here. */
12902 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
12903 BFD_RELOC_LO16, AT);
12904 expr1.X_add_number += 4;
12906 /* Set mips_optimize to 2 to avoid inserting an undesired
12908 hold_mips_optimize = mips_optimize;
12910 /* Itbl support may require additional care here. */
12911 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
12912 BFD_RELOC_LO16, AT);
12913 mips_optimize = hold_mips_optimize;
12914 expr1.X_add_number -= 4;
12917 offset_expr.X_add_number = expr1.X_add_number;
12919 macro_build (NULL, "nop", "");
12920 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12921 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12924 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12925 /* Itbl support may require additional care here. */
12926 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12927 BFD_RELOC_LO16, AT);
12928 offset_expr.X_add_number += 4;
12930 /* Set mips_optimize to 2 to avoid inserting an undesired
12932 hold_mips_optimize = mips_optimize;
12934 /* Itbl support may require additional care here. */
12935 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12936 BFD_RELOC_LO16, AT);
12937 mips_optimize = hold_mips_optimize;
12951 gas_assert (!mips_opts.micromips);
12956 /* New code added to support COPZ instructions.
12957 This code builds table entries out of the macros in mip_opcodes.
12958 R4000 uses interlocks to handle coproc delays.
12959 Other chips (like the R3000) require nops to be inserted for delays.
12961 FIXME: Currently, we require that the user handle delays.
12962 In order to fill delay slots for non-interlocked chips,
12963 we must have a way to specify delays based on the coprocessor.
12964 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
12965 What are the side-effects of the cop instruction?
12966 What cache support might we have and what are its effects?
12967 Both coprocessor & memory require delays. how long???
12968 What registers are read/set/modified?
12970 If an itbl is provided to interpret cop instructions,
12971 this knowledge can be encoded in the itbl spec. */
12985 gas_assert (!mips_opts.micromips);
12986 /* For now we just do C (same as Cz). The parameter will be
12987 stored in insn_opcode by mips_ip. */
12988 macro_build (NULL, s, "C", (int) ip->insn_opcode);
12992 move_register (op[0], op[1]);
12996 gas_assert (mips_opts.micromips);
12997 gas_assert (mips_opts.insn32);
12998 move_register (micromips_to_32_reg_h_map1[op[0]],
12999 micromips_to_32_reg_m_map[op[1]]);
13000 move_register (micromips_to_32_reg_h_map2[op[0]],
13001 micromips_to_32_reg_n_map[op[2]]);
13006 /* Fall through. */
13008 if (mips_opts.arch == CPU_R5900)
13009 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", op[0], op[1],
13013 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", op[1], op[2]);
13014 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
13020 /* Fall through. */
13022 /* The MIPS assembler some times generates shifts and adds. I'm
13023 not trying to be that fancy. GCC should do this for us
13026 load_register (AT, &imm_expr, dbl);
13027 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", op[1], AT);
13028 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
13033 /* Fall through. */
13040 /* Fall through. */
13043 start_noreorder ();
13046 load_register (AT, &imm_expr, dbl);
13047 macro_build (NULL, dbl ? "dmult" : "mult", "s,t",
13048 op[1], imm ? AT : op[2]);
13049 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
13050 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, op[0], op[0], 31);
13051 macro_build (NULL, "mfhi", MFHL_FMT, AT);
13053 macro_build (NULL, "tne", TRAP_FMT, op[0], AT, 6);
13056 if (mips_opts.micromips)
13057 micromips_label_expr (&label_expr);
13059 label_expr.X_add_number = 8;
13060 macro_build (&label_expr, "beq", "s,t,p", op[0], AT);
13061 macro_build (NULL, "nop", "");
13062 macro_build (NULL, "break", BRK_FMT, 6);
13063 if (mips_opts.micromips)
13064 micromips_add_label ();
13067 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
13072 /* Fall through. */
13079 /* Fall through. */
13082 start_noreorder ();
13085 load_register (AT, &imm_expr, dbl);
13086 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
13087 op[1], imm ? AT : op[2]);
13088 macro_build (NULL, "mfhi", MFHL_FMT, AT);
13089 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
13091 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
13094 if (mips_opts.micromips)
13095 micromips_label_expr (&label_expr);
13097 label_expr.X_add_number = 8;
13098 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
13099 macro_build (NULL, "nop", "");
13100 macro_build (NULL, "break", BRK_FMT, 6);
13101 if (mips_opts.micromips)
13102 micromips_add_label ();
13108 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
13110 if (op[0] == op[1])
13117 macro_build (NULL, "dnegu", "d,w", tempreg, op[2]);
13118 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], tempreg);
13122 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
13123 macro_build (NULL, "dsrlv", "d,t,s", AT, op[1], AT);
13124 macro_build (NULL, "dsllv", "d,t,s", op[0], op[1], op[2]);
13125 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13129 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
13131 if (op[0] == op[1])
13138 macro_build (NULL, "negu", "d,w", tempreg, op[2]);
13139 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], tempreg);
13143 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
13144 macro_build (NULL, "srlv", "d,t,s", AT, op[1], AT);
13145 macro_build (NULL, "sllv", "d,t,s", op[0], op[1], op[2]);
13146 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13155 rot = imm_expr.X_add_number & 0x3f;
13156 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
13158 rot = (64 - rot) & 0x3f;
13160 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
13162 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
13167 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
13170 l = (rot < 0x20) ? "dsll" : "dsll32";
13171 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
13174 macro_build (NULL, l, SHFT_FMT, AT, op[1], rot);
13175 macro_build (NULL, rr, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
13176 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13184 rot = imm_expr.X_add_number & 0x1f;
13185 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
13187 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1],
13188 (32 - rot) & 0x1f);
13193 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
13197 macro_build (NULL, "sll", SHFT_FMT, AT, op[1], rot);
13198 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
13199 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13204 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
13206 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], op[2]);
13210 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
13211 macro_build (NULL, "dsllv", "d,t,s", AT, op[1], AT);
13212 macro_build (NULL, "dsrlv", "d,t,s", op[0], op[1], op[2]);
13213 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13217 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
13219 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], op[2]);
13223 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
13224 macro_build (NULL, "sllv", "d,t,s", AT, op[1], AT);
13225 macro_build (NULL, "srlv", "d,t,s", op[0], op[1], op[2]);
13226 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13235 rot = imm_expr.X_add_number & 0x3f;
13236 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
13239 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
13241 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
13246 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
13249 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
13250 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
13253 macro_build (NULL, rr, SHFT_FMT, AT, op[1], rot);
13254 macro_build (NULL, l, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
13255 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13263 rot = imm_expr.X_add_number & 0x1f;
13264 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
13266 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], rot);
13271 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
13275 macro_build (NULL, "srl", SHFT_FMT, AT, op[1], rot);
13276 macro_build (NULL, "sll", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
13277 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13283 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[2], BFD_RELOC_LO16);
13284 else if (op[2] == 0)
13285 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13288 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
13289 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
13294 if (imm_expr.X_add_number == 0)
13296 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13301 as_warn (_("instruction %s: result is always false"),
13302 ip->insn_mo->name);
13303 move_register (op[0], 0);
13306 if (CPU_HAS_SEQ (mips_opts.arch)
13307 && -512 <= imm_expr.X_add_number
13308 && imm_expr.X_add_number < 512)
13310 macro_build (NULL, "seqi", "t,r,+Q", op[0], op[1],
13311 (int) imm_expr.X_add_number);
13314 if (imm_expr.X_add_number >= 0
13315 && imm_expr.X_add_number < 0x10000)
13316 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], BFD_RELOC_LO16);
13317 else if (imm_expr.X_add_number > -0x8000
13318 && imm_expr.X_add_number < 0)
13320 imm_expr.X_add_number = -imm_expr.X_add_number;
13321 macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu",
13322 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13324 else if (CPU_HAS_SEQ (mips_opts.arch))
13327 load_register (AT, &imm_expr, GPR_SIZE == 64);
13328 macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT);
13333 load_register (AT, &imm_expr, GPR_SIZE == 64);
13334 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
13337 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
13340 case M_SGE: /* X >= Y <==> not (X < Y) */
13346 macro_build (NULL, s, "d,v,t", op[0], op[1], op[2]);
13347 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
13350 case M_SGE_I: /* X >= I <==> not (X < I) */
13352 if (imm_expr.X_add_number >= -0x8000
13353 && imm_expr.X_add_number < 0x8000)
13354 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
13355 op[0], op[1], BFD_RELOC_LO16);
13358 load_register (AT, &imm_expr, GPR_SIZE == 64);
13359 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
13363 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
13366 case M_SGT: /* X > Y <==> Y < X */
13372 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
13375 case M_SGT_I: /* X > I <==> I < X */
13382 load_register (AT, &imm_expr, GPR_SIZE == 64);
13383 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
13386 case M_SLE: /* X <= Y <==> Y >= X <==> not (Y < X) */
13392 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
13393 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
13396 case M_SLE_I: /* X <= I <==> I >= X <==> not (I < X) */
13403 load_register (AT, &imm_expr, GPR_SIZE == 64);
13404 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
13405 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
13409 if (imm_expr.X_add_number >= -0x8000
13410 && imm_expr.X_add_number < 0x8000)
13412 macro_build (&imm_expr, "slti", "t,r,j", op[0], op[1],
13417 load_register (AT, &imm_expr, GPR_SIZE == 64);
13418 macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT);
13422 if (imm_expr.X_add_number >= -0x8000
13423 && imm_expr.X_add_number < 0x8000)
13425 macro_build (&imm_expr, "sltiu", "t,r,j", op[0], op[1],
13430 load_register (AT, &imm_expr, GPR_SIZE == 64);
13431 macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT);
13436 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[2]);
13437 else if (op[2] == 0)
13438 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
13441 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
13442 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
13447 if (imm_expr.X_add_number == 0)
13449 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
13454 as_warn (_("instruction %s: result is always true"),
13455 ip->insn_mo->name);
13456 macro_build (&expr1, GPR_SIZE == 32 ? "addiu" : "daddiu", "t,r,j",
13457 op[0], 0, BFD_RELOC_LO16);
13460 if (CPU_HAS_SEQ (mips_opts.arch)
13461 && -512 <= imm_expr.X_add_number
13462 && imm_expr.X_add_number < 512)
13464 macro_build (NULL, "snei", "t,r,+Q", op[0], op[1],
13465 (int) imm_expr.X_add_number);
13468 if (imm_expr.X_add_number >= 0
13469 && imm_expr.X_add_number < 0x10000)
13471 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1],
13474 else if (imm_expr.X_add_number > -0x8000
13475 && imm_expr.X_add_number < 0)
13477 imm_expr.X_add_number = -imm_expr.X_add_number;
13478 macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu",
13479 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13481 else if (CPU_HAS_SEQ (mips_opts.arch))
13484 load_register (AT, &imm_expr, GPR_SIZE == 64);
13485 macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT);
13490 load_register (AT, &imm_expr, GPR_SIZE == 64);
13491 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
13494 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
13509 if (!mips_opts.micromips)
13511 if (imm_expr.X_add_number > -0x200
13512 && imm_expr.X_add_number <= 0x200)
13514 macro_build (NULL, s, "t,r,.", op[0], op[1],
13515 (int) -imm_expr.X_add_number);
13524 if (imm_expr.X_add_number > -0x8000
13525 && imm_expr.X_add_number <= 0x8000)
13527 imm_expr.X_add_number = -imm_expr.X_add_number;
13528 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13533 load_register (AT, &imm_expr, dbl);
13534 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
13556 load_register (AT, &imm_expr, GPR_SIZE == 64);
13557 macro_build (NULL, s, "s,t", op[0], AT);
13562 gas_assert (!mips_opts.micromips);
13563 gas_assert (mips_opts.isa == ISA_MIPS1);
13567 * Is the double cfc1 instruction a bug in the mips assembler;
13568 * or is there a reason for it?
13570 start_noreorder ();
13571 macro_build (NULL, "cfc1", "t,G", op[2], RA);
13572 macro_build (NULL, "cfc1", "t,G", op[2], RA);
13573 macro_build (NULL, "nop", "");
13574 expr1.X_add_number = 3;
13575 macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16);
13576 expr1.X_add_number = 2;
13577 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
13578 macro_build (NULL, "ctc1", "t,G", AT, RA);
13579 macro_build (NULL, "nop", "");
13580 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
13582 macro_build (NULL, "ctc1", "t,G", op[2], RA);
13583 macro_build (NULL, "nop", "");
13600 offbits = (mips_opts.micromips ? 12 : 16);
13606 offbits = (mips_opts.micromips ? 12 : 16);
13618 offbits = (mips_opts.micromips ? 12 : 16);
13625 offbits = (mips_opts.micromips ? 12 : 16);
13631 large_offset = !small_offset_p (off, align, offbits);
13633 expr1.X_add_number = 0;
13638 if (small_offset_p (0, align, 16))
13639 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1,
13640 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
13643 load_address (tempreg, ep, &used_at);
13645 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
13646 tempreg, tempreg, breg);
13648 offset_reloc[0] = BFD_RELOC_LO16;
13649 offset_reloc[1] = BFD_RELOC_UNUSED;
13650 offset_reloc[2] = BFD_RELOC_UNUSED;
13655 else if (!ust && op[0] == breg)
13666 if (!target_big_endian)
13667 ep->X_add_number += off;
13669 macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg);
13671 macro_build (ep, s, "t,o(b)", tempreg, -1,
13672 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13674 if (!target_big_endian)
13675 ep->X_add_number -= off;
13677 ep->X_add_number += off;
13679 macro_build (NULL, s2, "t,~(b)",
13680 tempreg, (int) ep->X_add_number, breg);
13682 macro_build (ep, s2, "t,o(b)", tempreg, -1,
13683 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13685 /* If necessary, move the result in tempreg to the final destination. */
13686 if (!ust && op[0] != tempreg)
13688 /* Protect second load's delay slot. */
13690 move_register (op[0], tempreg);
13696 if (target_big_endian == ust)
13697 ep->X_add_number += off;
13698 tempreg = ust || large_offset ? op[0] : AT;
13699 macro_build (ep, s, "t,o(b)", tempreg, -1,
13700 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13702 /* For halfword transfers we need a temporary register to shuffle
13703 bytes. Unfortunately for M_USH_A we have none available before
13704 the next store as AT holds the base address. We deal with this
13705 case by clobbering TREG and then restoring it as with ULH. */
13706 tempreg = ust == large_offset ? op[0] : AT;
13708 macro_build (NULL, "srl", SHFT_FMT, tempreg, op[0], 8);
13710 if (target_big_endian == ust)
13711 ep->X_add_number -= off;
13713 ep->X_add_number += off;
13714 macro_build (ep, s2, "t,o(b)", tempreg, -1,
13715 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13717 /* For M_USH_A re-retrieve the LSB. */
13718 if (ust && large_offset)
13720 if (target_big_endian)
13721 ep->X_add_number += off;
13723 ep->X_add_number -= off;
13724 macro_build (&expr1, "lbu", "t,o(b)", AT, -1,
13725 offset_reloc[0], offset_reloc[1], offset_reloc[2], AT);
13727 /* For ULH and M_USH_A OR the LSB in. */
13728 if (!ust || large_offset)
13730 tempreg = !large_offset ? AT : op[0];
13731 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
13732 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13737 /* FIXME: Check if this is one of the itbl macros, since they
13738 are added dynamically. */
13739 as_bad (_("macro %s not implemented yet"), ip->insn_mo->name);
13742 if (!mips_opts.at && used_at)
13743 as_bad (_("macro used $at after \".set noat\""));
13746 /* Implement macros in mips16 mode. */
13749 mips16_macro (struct mips_cl_insn *ip)
13751 const struct mips_operand_array *operands;
13756 const char *s, *s2, *s3;
13757 unsigned int op[MAX_OPERANDS];
13760 mask = ip->insn_mo->mask;
13762 operands = insn_operands (ip);
13763 for (i = 0; i < MAX_OPERANDS; i++)
13764 if (operands->operand[i])
13765 op[i] = insn_extract_operand (ip, operands->operand[i]);
13769 expr1.X_op = O_constant;
13770 expr1.X_op_symbol = NULL;
13771 expr1.X_add_symbol = NULL;
13772 expr1.X_add_number = 1;
13783 /* Fall through. */
13789 /* Fall through. */
13793 start_noreorder ();
13794 macro_build (NULL, dbl ? "ddiv" : "div", ".,x,y", op[1], op[2]);
13795 expr1.X_add_number = 2;
13796 macro_build (&expr1, "bnez", "x,p", op[2]);
13797 macro_build (NULL, "break", "6", 7);
13799 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
13800 since that causes an overflow. We should do that as well,
13801 but I don't see how to do the comparisons without a temporary
13804 macro_build (NULL, s, "x", op[0]);
13823 start_noreorder ();
13824 macro_build (NULL, s, ".,x,y", op[1], op[2]);
13825 expr1.X_add_number = 2;
13826 macro_build (&expr1, "bnez", "x,p", op[2]);
13827 macro_build (NULL, "break", "6", 7);
13829 macro_build (NULL, s2, "x", op[0]);
13834 /* Fall through. */
13836 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", op[1], op[2]);
13837 macro_build (NULL, "mflo", "x", op[0]);
13845 imm_expr.X_add_number = -imm_expr.X_add_number;
13846 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,F", op[0], op[1]);
13850 imm_expr.X_add_number = -imm_expr.X_add_number;
13851 macro_build (&imm_expr, "addiu", "x,k", op[0]);
13855 imm_expr.X_add_number = -imm_expr.X_add_number;
13856 macro_build (&imm_expr, "daddiu", "y,j", op[0]);
13878 goto do_reverse_branch;
13882 goto do_reverse_branch;
13894 goto do_reverse_branch;
13905 macro_build (NULL, s, "x,y", op[0], op[1]);
13906 macro_build (&offset_expr, s2, "p");
13933 goto do_addone_branch_i;
13938 goto do_addone_branch_i;
13953 goto do_addone_branch_i;
13959 do_addone_branch_i:
13960 ++imm_expr.X_add_number;
13963 macro_build (&imm_expr, s, s3, op[0]);
13964 macro_build (&offset_expr, s2, "p");
13968 expr1.X_add_number = 0;
13969 macro_build (&expr1, "slti", "x,8", op[1]);
13970 if (op[0] != op[1])
13971 macro_build (NULL, "move", "y,X", op[0], mips16_to_32_reg_map[op[1]]);
13972 expr1.X_add_number = 2;
13973 macro_build (&expr1, "bteqz", "p");
13974 macro_build (NULL, "neg", "x,w", op[0], op[0]);
13979 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
13980 opcode bits in *OPCODE_EXTRA. */
13982 static struct mips_opcode *
13983 mips_lookup_insn (struct hash_control *hash, const char *start,
13984 ssize_t length, unsigned int *opcode_extra)
13986 char *name, *dot, *p;
13987 unsigned int mask, suffix;
13989 struct mips_opcode *insn;
13991 /* Make a copy of the instruction so that we can fiddle with it. */
13992 name = xstrndup (start, length);
13994 /* Look up the instruction as-is. */
13995 insn = (struct mips_opcode *) hash_find (hash, name);
13999 dot = strchr (name, '.');
14002 /* Try to interpret the text after the dot as a VU0 channel suffix. */
14003 p = mips_parse_vu0_channels (dot + 1, &mask);
14004 if (*p == 0 && mask != 0)
14007 insn = (struct mips_opcode *) hash_find (hash, name);
14009 if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0)
14011 *opcode_extra |= mask << mips_vu0_channel_mask.lsb;
14017 if (mips_opts.micromips)
14019 /* See if there's an instruction size override suffix,
14020 either `16' or `32', at the end of the mnemonic proper,
14021 that defines the operation, i.e. before the first `.'
14022 character if any. Strip it and retry. */
14023 opend = dot != NULL ? dot - name : length;
14024 if (opend >= 3 && name[opend - 2] == '1' && name[opend - 1] == '6')
14026 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
14032 memmove (name + opend - 2, name + opend, length - opend + 1);
14033 insn = (struct mips_opcode *) hash_find (hash, name);
14036 forced_insn_length = suffix;
14048 /* Assemble an instruction into its binary format. If the instruction
14049 is a macro, set imm_expr and offset_expr to the values associated
14050 with "I" and "A" operands respectively. Otherwise store the value
14051 of the relocatable field (if any) in offset_expr. In both cases
14052 set offset_reloc to the relocation operators applied to offset_expr. */
14055 mips_ip (char *str, struct mips_cl_insn *insn)
14057 const struct mips_opcode *first, *past;
14058 struct hash_control *hash;
14061 struct mips_operand_token *tokens;
14062 unsigned int opcode_extra;
14064 if (mips_opts.micromips)
14066 hash = micromips_op_hash;
14067 past = µmips_opcodes[bfd_micromips_num_opcodes];
14072 past = &mips_opcodes[NUMOPCODES];
14074 forced_insn_length = 0;
14077 /* We first try to match an instruction up to a space or to the end. */
14078 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
14081 first = mips_lookup_insn (hash, str, end, &opcode_extra);
14084 set_insn_error (0, _("unrecognized opcode"));
14088 if (strcmp (first->name, "li.s") == 0)
14090 else if (strcmp (first->name, "li.d") == 0)
14094 tokens = mips_parse_arguments (str + end, format);
14098 if (!match_insns (insn, first, past, tokens, opcode_extra, FALSE)
14099 && !match_insns (insn, first, past, tokens, opcode_extra, TRUE))
14100 set_insn_error (0, _("invalid operands"));
14102 obstack_free (&mips_operand_tokens, tokens);
14105 /* As for mips_ip, but used when assembling MIPS16 code.
14106 Also set forced_insn_length to the resulting instruction size in
14107 bytes if the user explicitly requested a small or extended instruction. */
14110 mips16_ip (char *str, struct mips_cl_insn *insn)
14113 struct mips_opcode *first;
14114 struct mips_operand_token *tokens;
14117 for (s = str; *s != '\0' && *s != '.' && *s != ' '; ++s)
14139 else if (*s == 'e')
14146 else if (*s++ == ' ')
14148 set_insn_error (0, _("unrecognized opcode"));
14151 forced_insn_length = l;
14154 first = (struct mips_opcode *) hash_find (mips16_op_hash, str);
14159 set_insn_error (0, _("unrecognized opcode"));
14163 tokens = mips_parse_arguments (s, 0);
14167 if (!match_mips16_insns (insn, first, tokens))
14168 set_insn_error (0, _("invalid operands"));
14170 obstack_free (&mips_operand_tokens, tokens);
14173 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14174 NBITS is the number of significant bits in VAL. */
14176 static unsigned long
14177 mips16_immed_extend (offsetT val, unsigned int nbits)
14182 val &= (1U << nbits) - 1;
14183 if (nbits == 16 || nbits == 9)
14185 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
14188 else if (nbits == 15)
14190 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
14193 else if (nbits == 6)
14195 extval = ((val & 0x1f) << 6) | (val & 0x20);
14198 return (extval << 16) | val;
14201 /* Like decode_mips16_operand, but require the operand to be defined and
14202 require it to be an integer. */
14204 static const struct mips_int_operand *
14205 mips16_immed_operand (int type, bfd_boolean extended_p)
14207 const struct mips_operand *operand;
14209 operand = decode_mips16_operand (type, extended_p);
14210 if (!operand || (operand->type != OP_INT && operand->type != OP_PCREL))
14212 return (const struct mips_int_operand *) operand;
14215 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
14218 mips16_immed_in_range_p (const struct mips_int_operand *operand,
14219 bfd_reloc_code_real_type reloc, offsetT sval)
14221 int min_val, max_val;
14223 min_val = mips_int_operand_min (operand);
14224 max_val = mips_int_operand_max (operand);
14225 if (reloc != BFD_RELOC_UNUSED)
14228 sval = SEXT_16BIT (sval);
14233 return (sval >= min_val
14235 && (sval & ((1 << operand->shift) - 1)) == 0);
14238 /* Install immediate value VAL into MIPS16 instruction *INSN,
14239 extending it if necessary. The instruction in *INSN may
14240 already be extended.
14242 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14243 if none. In the former case, VAL is a 16-bit number with no
14244 defined signedness.
14246 TYPE is the type of the immediate field. USER_INSN_LENGTH
14247 is the length that the user requested, or 0 if none. */
14250 mips16_immed (const char *file, unsigned int line, int type,
14251 bfd_reloc_code_real_type reloc, offsetT val,
14252 unsigned int user_insn_length, unsigned long *insn)
14254 const struct mips_int_operand *operand;
14255 unsigned int uval, length;
14257 operand = mips16_immed_operand (type, FALSE);
14258 if (!mips16_immed_in_range_p (operand, reloc, val))
14260 /* We need an extended instruction. */
14261 if (user_insn_length == 2)
14262 as_bad_where (file, line, _("invalid unextended operand value"));
14264 *insn |= MIPS16_EXTEND;
14266 else if (user_insn_length == 4)
14268 /* The operand doesn't force an unextended instruction to be extended.
14269 Warn if the user wanted an extended instruction anyway. */
14270 *insn |= MIPS16_EXTEND;
14271 as_warn_where (file, line,
14272 _("extended operand requested but not required"));
14275 length = mips16_opcode_length (*insn);
14278 operand = mips16_immed_operand (type, TRUE);
14279 if (!mips16_immed_in_range_p (operand, reloc, val))
14280 as_bad_where (file, line,
14281 _("operand value out of range for instruction"));
14283 uval = ((unsigned int) val >> operand->shift) - operand->bias;
14284 if (length == 2 || operand->root.lsb != 0)
14285 *insn = mips_insert_operand (&operand->root, *insn, uval);
14287 *insn |= mips16_immed_extend (uval, operand->root.size);
14290 struct percent_op_match
14293 bfd_reloc_code_real_type reloc;
14296 static const struct percent_op_match mips_percent_op[] =
14298 {"%lo", BFD_RELOC_LO16},
14299 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
14300 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
14301 {"%call16", BFD_RELOC_MIPS_CALL16},
14302 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
14303 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
14304 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
14305 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
14306 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
14307 {"%got", BFD_RELOC_MIPS_GOT16},
14308 {"%gp_rel", BFD_RELOC_GPREL16},
14309 {"%gprel", BFD_RELOC_GPREL16},
14310 {"%half", BFD_RELOC_16},
14311 {"%highest", BFD_RELOC_MIPS_HIGHEST},
14312 {"%higher", BFD_RELOC_MIPS_HIGHER},
14313 {"%neg", BFD_RELOC_MIPS_SUB},
14314 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
14315 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
14316 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
14317 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
14318 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
14319 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
14320 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
14321 {"%hi", BFD_RELOC_HI16_S},
14322 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL},
14323 {"%pcrel_lo", BFD_RELOC_LO16_PCREL}
14326 static const struct percent_op_match mips16_percent_op[] =
14328 {"%lo", BFD_RELOC_MIPS16_LO16},
14329 {"%gp_rel", BFD_RELOC_MIPS16_GPREL},
14330 {"%gprel", BFD_RELOC_MIPS16_GPREL},
14331 {"%got", BFD_RELOC_MIPS16_GOT16},
14332 {"%call16", BFD_RELOC_MIPS16_CALL16},
14333 {"%hi", BFD_RELOC_MIPS16_HI16_S},
14334 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
14335 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
14336 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
14337 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
14338 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
14339 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
14340 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
14344 /* Return true if *STR points to a relocation operator. When returning true,
14345 move *STR over the operator and store its relocation code in *RELOC.
14346 Leave both *STR and *RELOC alone when returning false. */
14349 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
14351 const struct percent_op_match *percent_op;
14354 if (mips_opts.mips16)
14356 percent_op = mips16_percent_op;
14357 limit = ARRAY_SIZE (mips16_percent_op);
14361 percent_op = mips_percent_op;
14362 limit = ARRAY_SIZE (mips_percent_op);
14365 for (i = 0; i < limit; i++)
14366 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
14368 int len = strlen (percent_op[i].str);
14370 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
14373 *str += strlen (percent_op[i].str);
14374 *reloc = percent_op[i].reloc;
14376 /* Check whether the output BFD supports this relocation.
14377 If not, issue an error and fall back on something safe. */
14378 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
14380 as_bad (_("relocation %s isn't supported by the current ABI"),
14381 percent_op[i].str);
14382 *reloc = BFD_RELOC_UNUSED;
14390 /* Parse string STR as a 16-bit relocatable operand. Store the
14391 expression in *EP and the relocations in the array starting
14392 at RELOC. Return the number of relocation operators used.
14394 On exit, EXPR_END points to the first character after the expression. */
14397 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
14400 bfd_reloc_code_real_type reversed_reloc[3];
14401 size_t reloc_index, i;
14402 int crux_depth, str_depth;
14405 /* Search for the start of the main expression, recoding relocations
14406 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14407 of the main expression and with CRUX_DEPTH containing the number
14408 of open brackets at that point. */
14415 crux_depth = str_depth;
14417 /* Skip over whitespace and brackets, keeping count of the number
14419 while (*str == ' ' || *str == '\t' || *str == '(')
14424 && reloc_index < (HAVE_NEWABI ? 3 : 1)
14425 && parse_relocation (&str, &reversed_reloc[reloc_index]));
14427 my_getExpression (ep, crux);
14430 /* Match every open bracket. */
14431 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
14435 if (crux_depth > 0)
14436 as_bad (_("unclosed '('"));
14440 if (reloc_index != 0)
14442 prev_reloc_op_frag = frag_now;
14443 for (i = 0; i < reloc_index; i++)
14444 reloc[i] = reversed_reloc[reloc_index - 1 - i];
14447 return reloc_index;
14451 my_getExpression (expressionS *ep, char *str)
14455 save_in = input_line_pointer;
14456 input_line_pointer = str;
14458 expr_end = input_line_pointer;
14459 input_line_pointer = save_in;
14463 md_atof (int type, char *litP, int *sizeP)
14465 return ieee_md_atof (type, litP, sizeP, target_big_endian);
14469 md_number_to_chars (char *buf, valueT val, int n)
14471 if (target_big_endian)
14472 number_to_chars_bigendian (buf, val, n);
14474 number_to_chars_littleendian (buf, val, n);
14477 static int support_64bit_objects(void)
14479 const char **list, **l;
14482 list = bfd_target_list ();
14483 for (l = list; *l != NULL; l++)
14484 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
14485 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
14487 yes = (*l != NULL);
14492 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14493 NEW_VALUE. Warn if another value was already specified. Note:
14494 we have to defer parsing the -march and -mtune arguments in order
14495 to handle 'from-abi' correctly, since the ABI might be specified
14496 in a later argument. */
14499 mips_set_option_string (const char **string_ptr, const char *new_value)
14501 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
14502 as_warn (_("a different %s was already specified, is now %s"),
14503 string_ptr == &mips_arch_string ? "-march" : "-mtune",
14506 *string_ptr = new_value;
14510 md_parse_option (int c, const char *arg)
14514 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
14515 if (c == mips_ases[i].option_on || c == mips_ases[i].option_off)
14517 file_ase_explicit |= mips_set_ase (&mips_ases[i], &file_mips_opts,
14518 c == mips_ases[i].option_on);
14524 case OPTION_CONSTRUCT_FLOATS:
14525 mips_disable_float_construction = 0;
14528 case OPTION_NO_CONSTRUCT_FLOATS:
14529 mips_disable_float_construction = 1;
14541 target_big_endian = 1;
14545 target_big_endian = 0;
14551 else if (arg[0] == '0')
14553 else if (arg[0] == '1')
14563 mips_debug = atoi (arg);
14567 file_mips_opts.isa = ISA_MIPS1;
14571 file_mips_opts.isa = ISA_MIPS2;
14575 file_mips_opts.isa = ISA_MIPS3;
14579 file_mips_opts.isa = ISA_MIPS4;
14583 file_mips_opts.isa = ISA_MIPS5;
14586 case OPTION_MIPS32:
14587 file_mips_opts.isa = ISA_MIPS32;
14590 case OPTION_MIPS32R2:
14591 file_mips_opts.isa = ISA_MIPS32R2;
14594 case OPTION_MIPS32R3:
14595 file_mips_opts.isa = ISA_MIPS32R3;
14598 case OPTION_MIPS32R5:
14599 file_mips_opts.isa = ISA_MIPS32R5;
14602 case OPTION_MIPS32R6:
14603 file_mips_opts.isa = ISA_MIPS32R6;
14606 case OPTION_MIPS64R2:
14607 file_mips_opts.isa = ISA_MIPS64R2;
14610 case OPTION_MIPS64R3:
14611 file_mips_opts.isa = ISA_MIPS64R3;
14614 case OPTION_MIPS64R5:
14615 file_mips_opts.isa = ISA_MIPS64R5;
14618 case OPTION_MIPS64R6:
14619 file_mips_opts.isa = ISA_MIPS64R6;
14622 case OPTION_MIPS64:
14623 file_mips_opts.isa = ISA_MIPS64;
14627 mips_set_option_string (&mips_tune_string, arg);
14631 mips_set_option_string (&mips_arch_string, arg);
14635 mips_set_option_string (&mips_arch_string, "4650");
14636 mips_set_option_string (&mips_tune_string, "4650");
14639 case OPTION_NO_M4650:
14643 mips_set_option_string (&mips_arch_string, "4010");
14644 mips_set_option_string (&mips_tune_string, "4010");
14647 case OPTION_NO_M4010:
14651 mips_set_option_string (&mips_arch_string, "4100");
14652 mips_set_option_string (&mips_tune_string, "4100");
14655 case OPTION_NO_M4100:
14659 mips_set_option_string (&mips_arch_string, "3900");
14660 mips_set_option_string (&mips_tune_string, "3900");
14663 case OPTION_NO_M3900:
14666 case OPTION_MICROMIPS:
14667 if (file_mips_opts.mips16 == 1)
14669 as_bad (_("-mmicromips cannot be used with -mips16"));
14672 file_mips_opts.micromips = 1;
14673 mips_no_prev_insn ();
14676 case OPTION_NO_MICROMIPS:
14677 file_mips_opts.micromips = 0;
14678 mips_no_prev_insn ();
14681 case OPTION_MIPS16:
14682 if (file_mips_opts.micromips == 1)
14684 as_bad (_("-mips16 cannot be used with -micromips"));
14687 file_mips_opts.mips16 = 1;
14688 mips_no_prev_insn ();
14691 case OPTION_NO_MIPS16:
14692 file_mips_opts.mips16 = 0;
14693 mips_no_prev_insn ();
14696 case OPTION_FIX_24K:
14700 case OPTION_NO_FIX_24K:
14704 case OPTION_FIX_RM7000:
14705 mips_fix_rm7000 = 1;
14708 case OPTION_NO_FIX_RM7000:
14709 mips_fix_rm7000 = 0;
14712 case OPTION_FIX_LOONGSON2F_JUMP:
14713 mips_fix_loongson2f_jump = TRUE;
14716 case OPTION_NO_FIX_LOONGSON2F_JUMP:
14717 mips_fix_loongson2f_jump = FALSE;
14720 case OPTION_FIX_LOONGSON2F_NOP:
14721 mips_fix_loongson2f_nop = TRUE;
14724 case OPTION_NO_FIX_LOONGSON2F_NOP:
14725 mips_fix_loongson2f_nop = FALSE;
14728 case OPTION_FIX_VR4120:
14729 mips_fix_vr4120 = 1;
14732 case OPTION_NO_FIX_VR4120:
14733 mips_fix_vr4120 = 0;
14736 case OPTION_FIX_VR4130:
14737 mips_fix_vr4130 = 1;
14740 case OPTION_NO_FIX_VR4130:
14741 mips_fix_vr4130 = 0;
14744 case OPTION_FIX_CN63XXP1:
14745 mips_fix_cn63xxp1 = TRUE;
14748 case OPTION_NO_FIX_CN63XXP1:
14749 mips_fix_cn63xxp1 = FALSE;
14752 case OPTION_RELAX_BRANCH:
14753 mips_relax_branch = 1;
14756 case OPTION_NO_RELAX_BRANCH:
14757 mips_relax_branch = 0;
14760 case OPTION_IGNORE_BRANCH_ISA:
14761 mips_ignore_branch_isa = TRUE;
14764 case OPTION_NO_IGNORE_BRANCH_ISA:
14765 mips_ignore_branch_isa = FALSE;
14768 case OPTION_INSN32:
14769 file_mips_opts.insn32 = TRUE;
14772 case OPTION_NO_INSN32:
14773 file_mips_opts.insn32 = FALSE;
14776 case OPTION_MSHARED:
14777 mips_in_shared = TRUE;
14780 case OPTION_MNO_SHARED:
14781 mips_in_shared = FALSE;
14784 case OPTION_MSYM32:
14785 file_mips_opts.sym32 = TRUE;
14788 case OPTION_MNO_SYM32:
14789 file_mips_opts.sym32 = FALSE;
14792 /* When generating ELF code, we permit -KPIC and -call_shared to
14793 select SVR4_PIC, and -non_shared to select no PIC. This is
14794 intended to be compatible with Irix 5. */
14795 case OPTION_CALL_SHARED:
14796 mips_pic = SVR4_PIC;
14797 mips_abicalls = TRUE;
14800 case OPTION_CALL_NONPIC:
14802 mips_abicalls = TRUE;
14805 case OPTION_NON_SHARED:
14807 mips_abicalls = FALSE;
14810 /* The -xgot option tells the assembler to use 32 bit offsets
14811 when accessing the got in SVR4_PIC mode. It is for Irix
14818 g_switch_value = atoi (arg);
14822 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14825 mips_abi = O32_ABI;
14829 mips_abi = N32_ABI;
14833 mips_abi = N64_ABI;
14834 if (!support_64bit_objects())
14835 as_fatal (_("no compiled in support for 64 bit object file format"));
14839 file_mips_opts.gp = 32;
14843 file_mips_opts.gp = 64;
14847 file_mips_opts.fp = 32;
14851 file_mips_opts.fp = 0;
14855 file_mips_opts.fp = 64;
14858 case OPTION_ODD_SPREG:
14859 file_mips_opts.oddspreg = 1;
14862 case OPTION_NO_ODD_SPREG:
14863 file_mips_opts.oddspreg = 0;
14866 case OPTION_SINGLE_FLOAT:
14867 file_mips_opts.single_float = 1;
14870 case OPTION_DOUBLE_FLOAT:
14871 file_mips_opts.single_float = 0;
14874 case OPTION_SOFT_FLOAT:
14875 file_mips_opts.soft_float = 1;
14878 case OPTION_HARD_FLOAT:
14879 file_mips_opts.soft_float = 0;
14883 if (strcmp (arg, "32") == 0)
14884 mips_abi = O32_ABI;
14885 else if (strcmp (arg, "o64") == 0)
14886 mips_abi = O64_ABI;
14887 else if (strcmp (arg, "n32") == 0)
14888 mips_abi = N32_ABI;
14889 else if (strcmp (arg, "64") == 0)
14891 mips_abi = N64_ABI;
14892 if (! support_64bit_objects())
14893 as_fatal (_("no compiled in support for 64 bit object file "
14896 else if (strcmp (arg, "eabi") == 0)
14897 mips_abi = EABI_ABI;
14900 as_fatal (_("invalid abi -mabi=%s"), arg);
14905 case OPTION_M7000_HILO_FIX:
14906 mips_7000_hilo_fix = TRUE;
14909 case OPTION_MNO_7000_HILO_FIX:
14910 mips_7000_hilo_fix = FALSE;
14913 case OPTION_MDEBUG:
14914 mips_flag_mdebug = TRUE;
14917 case OPTION_NO_MDEBUG:
14918 mips_flag_mdebug = FALSE;
14922 mips_flag_pdr = TRUE;
14925 case OPTION_NO_PDR:
14926 mips_flag_pdr = FALSE;
14929 case OPTION_MVXWORKS_PIC:
14930 mips_pic = VXWORKS_PIC;
14934 if (strcmp (arg, "2008") == 0)
14936 else if (strcmp (arg, "legacy") == 0)
14940 as_fatal (_("invalid NaN setting -mnan=%s"), arg);
14949 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
14954 /* Set up globals to tune for the ISA or processor described by INFO. */
14957 mips_set_tune (const struct mips_cpu_info *info)
14960 mips_tune = info->cpu;
14965 mips_after_parse_args (void)
14967 const struct mips_cpu_info *arch_info = 0;
14968 const struct mips_cpu_info *tune_info = 0;
14970 /* GP relative stuff not working for PE */
14971 if (strncmp (TARGET_OS, "pe", 2) == 0)
14973 if (g_switch_seen && g_switch_value != 0)
14974 as_bad (_("-G not supported in this configuration"));
14975 g_switch_value = 0;
14978 if (mips_abi == NO_ABI)
14979 mips_abi = MIPS_DEFAULT_ABI;
14981 /* The following code determines the architecture.
14982 Similar code was added to GCC 3.3 (see override_options() in
14983 config/mips/mips.c). The GAS and GCC code should be kept in sync
14984 as much as possible. */
14986 if (mips_arch_string != 0)
14987 arch_info = mips_parse_cpu ("-march", mips_arch_string);
14989 if (file_mips_opts.isa != ISA_UNKNOWN)
14991 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
14992 ISA level specified by -mipsN, while arch_info->isa contains
14993 the -march selection (if any). */
14994 if (arch_info != 0)
14996 /* -march takes precedence over -mipsN, since it is more descriptive.
14997 There's no harm in specifying both as long as the ISA levels
14999 if (file_mips_opts.isa != arch_info->isa)
15000 as_bad (_("-%s conflicts with the other architecture options,"
15001 " which imply -%s"),
15002 mips_cpu_info_from_isa (file_mips_opts.isa)->name,
15003 mips_cpu_info_from_isa (arch_info->isa)->name);
15006 arch_info = mips_cpu_info_from_isa (file_mips_opts.isa);
15009 if (arch_info == 0)
15011 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
15012 gas_assert (arch_info);
15015 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
15016 as_bad (_("-march=%s is not compatible with the selected ABI"),
15019 file_mips_opts.arch = arch_info->cpu;
15020 file_mips_opts.isa = arch_info->isa;
15022 /* Set up initial mips_opts state. */
15023 mips_opts = file_mips_opts;
15025 /* The register size inference code is now placed in
15026 file_mips_check_options. */
15028 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
15030 if (mips_tune_string != 0)
15031 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
15033 if (tune_info == 0)
15034 mips_set_tune (arch_info);
15036 mips_set_tune (tune_info);
15038 if (mips_flag_mdebug < 0)
15039 mips_flag_mdebug = 0;
15043 mips_init_after_args (void)
15045 /* initialize opcodes */
15046 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
15047 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
15051 md_pcrel_from (fixS *fixP)
15053 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
15054 switch (fixP->fx_r_type)
15056 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15057 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15058 /* Return the address of the delay slot. */
15061 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15062 case BFD_RELOC_MICROMIPS_JMP:
15063 case BFD_RELOC_MIPS16_16_PCREL_S1:
15064 case BFD_RELOC_16_PCREL_S2:
15065 case BFD_RELOC_MIPS_21_PCREL_S2:
15066 case BFD_RELOC_MIPS_26_PCREL_S2:
15067 case BFD_RELOC_MIPS_JMP:
15068 /* Return the address of the delay slot. */
15071 case BFD_RELOC_MIPS_18_PCREL_S3:
15072 /* Return the aligned address of the doubleword containing
15073 the instruction. */
15081 /* This is called before the symbol table is processed. In order to
15082 work with gcc when using mips-tfile, we must keep all local labels.
15083 However, in other cases, we want to discard them. If we were
15084 called with -g, but we didn't see any debugging information, it may
15085 mean that gcc is smuggling debugging information through to
15086 mips-tfile, in which case we must generate all local labels. */
15089 mips_frob_file_before_adjust (void)
15091 #ifndef NO_ECOFF_DEBUGGING
15092 if (ECOFF_DEBUGGING
15094 && ! ecoff_debugging_seen)
15095 flag_keep_locals = 1;
15099 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15100 the corresponding LO16 reloc. This is called before md_apply_fix and
15101 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15102 relocation operators.
15104 For our purposes, a %lo() expression matches a %got() or %hi()
15107 (a) it refers to the same symbol; and
15108 (b) the offset applied in the %lo() expression is no lower than
15109 the offset applied in the %got() or %hi().
15111 (b) allows us to cope with code like:
15114 lh $4,%lo(foo+2)($4)
15116 ...which is legal on RELA targets, and has a well-defined behaviour
15117 if the user knows that adding 2 to "foo" will not induce a carry to
15120 When several %lo()s match a particular %got() or %hi(), we use the
15121 following rules to distinguish them:
15123 (1) %lo()s with smaller offsets are a better match than %lo()s with
15126 (2) %lo()s with no matching %got() or %hi() are better than those
15127 that already have a matching %got() or %hi().
15129 (3) later %lo()s are better than earlier %lo()s.
15131 These rules are applied in order.
15133 (1) means, among other things, that %lo()s with identical offsets are
15134 chosen if they exist.
15136 (2) means that we won't associate several high-part relocations with
15137 the same low-part relocation unless there's no alternative. Having
15138 several high parts for the same low part is a GNU extension; this rule
15139 allows careful users to avoid it.
15141 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15142 with the last high-part relocation being at the front of the list.
15143 It therefore makes sense to choose the last matching low-part
15144 relocation, all other things being equal. It's also easier
15145 to code that way. */
15148 mips_frob_file (void)
15150 struct mips_hi_fixup *l;
15151 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
15153 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
15155 segment_info_type *seginfo;
15156 bfd_boolean matched_lo_p;
15157 fixS **hi_pos, **lo_pos, **pos;
15159 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
15161 /* If a GOT16 relocation turns out to be against a global symbol,
15162 there isn't supposed to be a matching LO. Ignore %gots against
15163 constants; we'll report an error for those later. */
15164 if (got16_reloc_p (l->fixp->fx_r_type)
15165 && !(l->fixp->fx_addsy
15166 && pic_need_relax (l->fixp->fx_addsy)))
15169 /* Check quickly whether the next fixup happens to be a matching %lo. */
15170 if (fixup_has_matching_lo_p (l->fixp))
15173 seginfo = seg_info (l->seg);
15175 /* Set HI_POS to the position of this relocation in the chain.
15176 Set LO_POS to the position of the chosen low-part relocation.
15177 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15178 relocation that matches an immediately-preceding high-part
15182 matched_lo_p = FALSE;
15183 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
15185 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
15187 if (*pos == l->fixp)
15190 if ((*pos)->fx_r_type == looking_for_rtype
15191 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
15192 && (*pos)->fx_offset >= l->fixp->fx_offset
15194 || (*pos)->fx_offset < (*lo_pos)->fx_offset
15196 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
15199 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
15200 && fixup_has_matching_lo_p (*pos));
15203 /* If we found a match, remove the high-part relocation from its
15204 current position and insert it before the low-part relocation.
15205 Make the offsets match so that fixup_has_matching_lo_p()
15208 We don't warn about unmatched high-part relocations since some
15209 versions of gcc have been known to emit dead "lui ...%hi(...)"
15211 if (lo_pos != NULL)
15213 l->fixp->fx_offset = (*lo_pos)->fx_offset;
15214 if (l->fixp->fx_next != *lo_pos)
15216 *hi_pos = l->fixp->fx_next;
15217 l->fixp->fx_next = *lo_pos;
15225 mips_force_relocation (fixS *fixp)
15227 if (generic_force_reloc (fixp))
15230 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15231 so that the linker relaxation can update targets. */
15232 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15233 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15234 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
15237 /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2
15238 and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and
15239 microMIPS symbols so that we can do cross-mode branch diagnostics
15240 and BAL to JALX conversion by the linker. */
15241 if ((fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
15242 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
15243 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2)
15245 && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp->fx_addsy)))
15248 /* We want all PC-relative relocations to be kept for R6 relaxation. */
15249 if (ISA_IS_R6 (file_mips_opts.isa)
15250 && (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
15251 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
15252 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2
15253 || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3
15254 || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2
15255 || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL
15256 || fixp->fx_r_type == BFD_RELOC_LO16_PCREL))
15262 /* Implement TC_FORCE_RELOCATION_ABS. */
15265 mips_force_relocation_abs (fixS *fixp)
15267 if (generic_force_reloc (fixp))
15270 /* These relocations do not have enough bits in the in-place addend
15271 to hold an arbitrary absolute section's offset. */
15272 if (HAVE_IN_PLACE_ADDENDS && limited_pcrel_reloc_p (fixp->fx_r_type))
15278 /* Read the instruction associated with RELOC from BUF. */
15280 static unsigned int
15281 read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc)
15283 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
15284 return read_compressed_insn (buf, 4);
15286 return read_insn (buf);
15289 /* Write instruction INSN to BUF, given that it has been relocated
15293 write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc,
15294 unsigned long insn)
15296 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
15297 write_compressed_insn (buf, insn, 4);
15299 write_insn (buf, insn);
15302 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15303 to a symbol in another ISA mode, which cannot be converted to JALX. */
15306 fix_bad_cross_mode_jump_p (fixS *fixP)
15308 unsigned long opcode;
15312 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
15315 other = S_GET_OTHER (fixP->fx_addsy);
15316 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15317 opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26;
15318 switch (fixP->fx_r_type)
15320 case BFD_RELOC_MIPS_JMP:
15321 return opcode != 0x1d && opcode != 0x03 && ELF_ST_IS_COMPRESSED (other);
15322 case BFD_RELOC_MICROMIPS_JMP:
15323 return opcode != 0x3c && opcode != 0x3d && !ELF_ST_IS_MICROMIPS (other);
15329 /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX
15330 jump to a symbol in the same ISA mode. */
15333 fix_bad_same_mode_jalx_p (fixS *fixP)
15335 unsigned long opcode;
15339 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
15342 other = S_GET_OTHER (fixP->fx_addsy);
15343 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15344 opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26;
15345 switch (fixP->fx_r_type)
15347 case BFD_RELOC_MIPS_JMP:
15348 return opcode == 0x1d && !ELF_ST_IS_COMPRESSED (other);
15349 case BFD_RELOC_MIPS16_JMP:
15350 return opcode == 0x07 && ELF_ST_IS_COMPRESSED (other);
15351 case BFD_RELOC_MICROMIPS_JMP:
15352 return opcode == 0x3c && ELF_ST_IS_COMPRESSED (other);
15358 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15359 to a symbol whose value plus addend is not aligned according to the
15360 ultimate (after linker relaxation) jump instruction's immediate field
15361 requirement, either to (1 << SHIFT), or, for jumps from microMIPS to
15362 regular MIPS code, to (1 << 2). */
15365 fix_bad_misaligned_jump_p (fixS *fixP, int shift)
15367 bfd_boolean micro_to_mips_p;
15371 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
15374 other = S_GET_OTHER (fixP->fx_addsy);
15375 val = S_GET_VALUE (fixP->fx_addsy) | ELF_ST_IS_COMPRESSED (other);
15376 val += fixP->fx_offset;
15377 micro_to_mips_p = (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP
15378 && !ELF_ST_IS_MICROMIPS (other));
15379 return ((val & ((1 << (micro_to_mips_p ? 2 : shift)) - 1))
15380 != ELF_ST_IS_COMPRESSED (other));
15383 /* Return TRUE if the instruction pointed to by FIXP is an invalid branch
15384 to a symbol whose annotation indicates another ISA mode. For absolute
15385 symbols check the ISA bit instead.
15387 We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS
15388 symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular
15389 MIPS symbols and associated with BAL instructions as these instructions
15390 may be converted to JALX by the linker. */
15393 fix_bad_cross_mode_branch_p (fixS *fixP)
15395 bfd_boolean absolute_p;
15396 unsigned long opcode;
15402 if (mips_ignore_branch_isa)
15405 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
15408 symsec = S_GET_SEGMENT (fixP->fx_addsy);
15409 absolute_p = bfd_is_abs_section (symsec);
15411 val = S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset;
15412 other = S_GET_OTHER (fixP->fx_addsy);
15414 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15415 opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 16;
15416 switch (fixP->fx_r_type)
15418 case BFD_RELOC_16_PCREL_S2:
15419 return ((absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other))
15420 && opcode != 0x0411);
15421 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15422 return ((absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other))
15423 && opcode != 0x4060);
15424 case BFD_RELOC_MIPS_21_PCREL_S2:
15425 case BFD_RELOC_MIPS_26_PCREL_S2:
15426 return absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other);
15427 case BFD_RELOC_MIPS16_16_PCREL_S1:
15428 return absolute_p ? !(val & 1) : !ELF_ST_IS_MIPS16 (other);
15429 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15430 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15431 return absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other);
15437 /* Return TRUE if the symbol plus addend associated with a regular MIPS
15438 branch instruction pointed to by FIXP is not aligned according to the
15439 branch instruction's immediate field requirement. We need the addend
15440 to preserve the ISA bit and also the sum must not have bit 2 set. We
15441 must explicitly OR in the ISA bit from symbol annotation as the bit
15442 won't be set in the symbol's value then. */
15445 fix_bad_misaligned_branch_p (fixS *fixP)
15447 bfd_boolean absolute_p;
15454 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
15457 symsec = S_GET_SEGMENT (fixP->fx_addsy);
15458 absolute_p = bfd_is_abs_section (symsec);
15460 val = S_GET_VALUE (fixP->fx_addsy);
15461 other = S_GET_OTHER (fixP->fx_addsy);
15462 off = fixP->fx_offset;
15464 isa_bit = absolute_p ? (val + off) & 1 : ELF_ST_IS_COMPRESSED (other);
15465 val |= ELF_ST_IS_COMPRESSED (other);
15467 return (val & 0x3) != isa_bit;
15470 /* Make the necessary checks on a regular MIPS branch pointed to by FIXP
15471 and its calculated value VAL. */
15474 fix_validate_branch (fixS *fixP, valueT val)
15476 if (fixP->fx_done && (val & 0x3) != 0)
15477 as_bad_where (fixP->fx_file, fixP->fx_line,
15478 _("branch to misaligned address (0x%lx)"),
15479 (long) (val + md_pcrel_from (fixP)));
15480 else if (fix_bad_cross_mode_branch_p (fixP))
15481 as_bad_where (fixP->fx_file, fixP->fx_line,
15482 _("branch to a symbol in another ISA mode"));
15483 else if (fix_bad_misaligned_branch_p (fixP))
15484 as_bad_where (fixP->fx_file, fixP->fx_line,
15485 _("branch to misaligned address (0x%lx)"),
15486 (long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset));
15487 else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x3) != 0)
15488 as_bad_where (fixP->fx_file, fixP->fx_line,
15489 _("cannot encode misaligned addend "
15490 "in the relocatable field (0x%lx)"),
15491 (long) fixP->fx_offset);
15494 /* Apply a fixup to the object file. */
15497 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
15500 unsigned long insn;
15501 reloc_howto_type *howto;
15503 if (fixP->fx_pcrel)
15504 switch (fixP->fx_r_type)
15506 case BFD_RELOC_16_PCREL_S2:
15507 case BFD_RELOC_MIPS16_16_PCREL_S1:
15508 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15509 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15510 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15511 case BFD_RELOC_32_PCREL:
15512 case BFD_RELOC_MIPS_21_PCREL_S2:
15513 case BFD_RELOC_MIPS_26_PCREL_S2:
15514 case BFD_RELOC_MIPS_18_PCREL_S3:
15515 case BFD_RELOC_MIPS_19_PCREL_S2:
15516 case BFD_RELOC_HI16_S_PCREL:
15517 case BFD_RELOC_LO16_PCREL:
15521 fixP->fx_r_type = BFD_RELOC_32_PCREL;
15525 as_bad_where (fixP->fx_file, fixP->fx_line,
15526 _("PC-relative reference to a different section"));
15530 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
15531 that have no MIPS ELF equivalent. */
15532 if (fixP->fx_r_type != BFD_RELOC_8)
15534 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
15539 gas_assert (fixP->fx_size == 2
15540 || fixP->fx_size == 4
15541 || fixP->fx_r_type == BFD_RELOC_8
15542 || fixP->fx_r_type == BFD_RELOC_16
15543 || fixP->fx_r_type == BFD_RELOC_64
15544 || fixP->fx_r_type == BFD_RELOC_CTOR
15545 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
15546 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
15547 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
15548 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
15549 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64
15550 || fixP->fx_r_type == BFD_RELOC_NONE);
15552 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15554 /* Don't treat parts of a composite relocation as done. There are two
15557 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15558 should nevertheless be emitted if the first part is.
15560 (2) In normal usage, composite relocations are never assembly-time
15561 constants. The easiest way of dealing with the pathological
15562 exceptions is to generate a relocation against STN_UNDEF and
15563 leave everything up to the linker. */
15564 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
15567 switch (fixP->fx_r_type)
15569 case BFD_RELOC_MIPS_TLS_GD:
15570 case BFD_RELOC_MIPS_TLS_LDM:
15571 case BFD_RELOC_MIPS_TLS_DTPREL32:
15572 case BFD_RELOC_MIPS_TLS_DTPREL64:
15573 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
15574 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
15575 case BFD_RELOC_MIPS_TLS_GOTTPREL:
15576 case BFD_RELOC_MIPS_TLS_TPREL32:
15577 case BFD_RELOC_MIPS_TLS_TPREL64:
15578 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
15579 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
15580 case BFD_RELOC_MICROMIPS_TLS_GD:
15581 case BFD_RELOC_MICROMIPS_TLS_LDM:
15582 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
15583 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
15584 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
15585 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
15586 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
15587 case BFD_RELOC_MIPS16_TLS_GD:
15588 case BFD_RELOC_MIPS16_TLS_LDM:
15589 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
15590 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
15591 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
15592 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
15593 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
15594 if (fixP->fx_addsy)
15595 S_SET_THREAD_LOCAL (fixP->fx_addsy);
15597 as_bad_where (fixP->fx_file, fixP->fx_line,
15598 _("TLS relocation against a constant"));
15601 case BFD_RELOC_MIPS_JMP:
15602 case BFD_RELOC_MIPS16_JMP:
15603 case BFD_RELOC_MICROMIPS_JMP:
15607 gas_assert (!fixP->fx_done);
15609 /* Shift is 2, unusually, for microMIPS JALX. */
15610 if (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP
15611 && (read_compressed_insn (buf, 4) >> 26) != 0x3c)
15616 if (fix_bad_cross_mode_jump_p (fixP))
15617 as_bad_where (fixP->fx_file, fixP->fx_line,
15618 _("jump to a symbol in another ISA mode"));
15619 else if (fix_bad_same_mode_jalx_p (fixP))
15620 as_bad_where (fixP->fx_file, fixP->fx_line,
15621 _("JALX to a symbol in the same ISA mode"));
15622 else if (fix_bad_misaligned_jump_p (fixP, shift))
15623 as_bad_where (fixP->fx_file, fixP->fx_line,
15624 _("jump to misaligned address (0x%lx)"),
15625 (long) (S_GET_VALUE (fixP->fx_addsy)
15626 + fixP->fx_offset));
15627 else if (HAVE_IN_PLACE_ADDENDS
15628 && (fixP->fx_offset & ((1 << shift) - 1)) != 0)
15629 as_bad_where (fixP->fx_file, fixP->fx_line,
15630 _("cannot encode misaligned addend "
15631 "in the relocatable field (0x%lx)"),
15632 (long) fixP->fx_offset);
15634 /* Fall through. */
15636 case BFD_RELOC_MIPS_SHIFT5:
15637 case BFD_RELOC_MIPS_SHIFT6:
15638 case BFD_RELOC_MIPS_GOT_DISP:
15639 case BFD_RELOC_MIPS_GOT_PAGE:
15640 case BFD_RELOC_MIPS_GOT_OFST:
15641 case BFD_RELOC_MIPS_SUB:
15642 case BFD_RELOC_MIPS_INSERT_A:
15643 case BFD_RELOC_MIPS_INSERT_B:
15644 case BFD_RELOC_MIPS_DELETE:
15645 case BFD_RELOC_MIPS_HIGHEST:
15646 case BFD_RELOC_MIPS_HIGHER:
15647 case BFD_RELOC_MIPS_SCN_DISP:
15648 case BFD_RELOC_MIPS_REL16:
15649 case BFD_RELOC_MIPS_RELGOT:
15650 case BFD_RELOC_MIPS_JALR:
15651 case BFD_RELOC_HI16:
15652 case BFD_RELOC_HI16_S:
15653 case BFD_RELOC_LO16:
15654 case BFD_RELOC_GPREL16:
15655 case BFD_RELOC_MIPS_LITERAL:
15656 case BFD_RELOC_MIPS_CALL16:
15657 case BFD_RELOC_MIPS_GOT16:
15658 case BFD_RELOC_GPREL32:
15659 case BFD_RELOC_MIPS_GOT_HI16:
15660 case BFD_RELOC_MIPS_GOT_LO16:
15661 case BFD_RELOC_MIPS_CALL_HI16:
15662 case BFD_RELOC_MIPS_CALL_LO16:
15663 case BFD_RELOC_HI16_S_PCREL:
15664 case BFD_RELOC_LO16_PCREL:
15665 case BFD_RELOC_MIPS16_GPREL:
15666 case BFD_RELOC_MIPS16_GOT16:
15667 case BFD_RELOC_MIPS16_CALL16:
15668 case BFD_RELOC_MIPS16_HI16:
15669 case BFD_RELOC_MIPS16_HI16_S:
15670 case BFD_RELOC_MIPS16_LO16:
15671 case BFD_RELOC_MICROMIPS_GOT_DISP:
15672 case BFD_RELOC_MICROMIPS_GOT_PAGE:
15673 case BFD_RELOC_MICROMIPS_GOT_OFST:
15674 case BFD_RELOC_MICROMIPS_SUB:
15675 case BFD_RELOC_MICROMIPS_HIGHEST:
15676 case BFD_RELOC_MICROMIPS_HIGHER:
15677 case BFD_RELOC_MICROMIPS_SCN_DISP:
15678 case BFD_RELOC_MICROMIPS_JALR:
15679 case BFD_RELOC_MICROMIPS_HI16:
15680 case BFD_RELOC_MICROMIPS_HI16_S:
15681 case BFD_RELOC_MICROMIPS_LO16:
15682 case BFD_RELOC_MICROMIPS_GPREL16:
15683 case BFD_RELOC_MICROMIPS_LITERAL:
15684 case BFD_RELOC_MICROMIPS_CALL16:
15685 case BFD_RELOC_MICROMIPS_GOT16:
15686 case BFD_RELOC_MICROMIPS_GOT_HI16:
15687 case BFD_RELOC_MICROMIPS_GOT_LO16:
15688 case BFD_RELOC_MICROMIPS_CALL_HI16:
15689 case BFD_RELOC_MICROMIPS_CALL_LO16:
15690 case BFD_RELOC_MIPS_EH:
15695 if (calculate_reloc (fixP->fx_r_type, *valP, &value))
15697 insn = read_reloc_insn (buf, fixP->fx_r_type);
15698 if (mips16_reloc_p (fixP->fx_r_type))
15699 insn |= mips16_immed_extend (value, 16);
15701 insn |= (value & 0xffff);
15702 write_reloc_insn (buf, fixP->fx_r_type, insn);
15705 as_bad_where (fixP->fx_file, fixP->fx_line,
15706 _("unsupported constant in relocation"));
15711 /* This is handled like BFD_RELOC_32, but we output a sign
15712 extended value if we are only 32 bits. */
15715 if (8 <= sizeof (valueT))
15716 md_number_to_chars (buf, *valP, 8);
15721 if ((*valP & 0x80000000) != 0)
15725 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4);
15726 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4);
15731 case BFD_RELOC_RVA:
15733 case BFD_RELOC_32_PCREL:
15736 /* If we are deleting this reloc entry, we must fill in the
15737 value now. This can happen if we have a .word which is not
15738 resolved when it appears but is later defined. */
15740 md_number_to_chars (buf, *valP, fixP->fx_size);
15743 case BFD_RELOC_MIPS_21_PCREL_S2:
15744 fix_validate_branch (fixP, *valP);
15745 if (!fixP->fx_done)
15748 if (*valP + 0x400000 <= 0x7fffff)
15750 insn = read_insn (buf);
15751 insn |= (*valP >> 2) & 0x1fffff;
15752 write_insn (buf, insn);
15755 as_bad_where (fixP->fx_file, fixP->fx_line,
15756 _("branch out of range"));
15759 case BFD_RELOC_MIPS_26_PCREL_S2:
15760 fix_validate_branch (fixP, *valP);
15761 if (!fixP->fx_done)
15764 if (*valP + 0x8000000 <= 0xfffffff)
15766 insn = read_insn (buf);
15767 insn |= (*valP >> 2) & 0x3ffffff;
15768 write_insn (buf, insn);
15771 as_bad_where (fixP->fx_file, fixP->fx_line,
15772 _("branch out of range"));
15775 case BFD_RELOC_MIPS_18_PCREL_S3:
15776 if (fixP->fx_addsy && (S_GET_VALUE (fixP->fx_addsy) & 0x7) != 0)
15777 as_bad_where (fixP->fx_file, fixP->fx_line,
15778 _("PC-relative access using misaligned symbol (%lx)"),
15779 (long) S_GET_VALUE (fixP->fx_addsy));
15780 if ((fixP->fx_offset & 0x7) != 0)
15781 as_bad_where (fixP->fx_file, fixP->fx_line,
15782 _("PC-relative access using misaligned offset (%lx)"),
15783 (long) fixP->fx_offset);
15784 if (!fixP->fx_done)
15787 if (*valP + 0x100000 <= 0x1fffff)
15789 insn = read_insn (buf);
15790 insn |= (*valP >> 3) & 0x3ffff;
15791 write_insn (buf, insn);
15794 as_bad_where (fixP->fx_file, fixP->fx_line,
15795 _("PC-relative access out of range"));
15798 case BFD_RELOC_MIPS_19_PCREL_S2:
15799 if ((*valP & 0x3) != 0)
15800 as_bad_where (fixP->fx_file, fixP->fx_line,
15801 _("PC-relative access to misaligned address (%lx)"),
15803 if (!fixP->fx_done)
15806 if (*valP + 0x100000 <= 0x1fffff)
15808 insn = read_insn (buf);
15809 insn |= (*valP >> 2) & 0x7ffff;
15810 write_insn (buf, insn);
15813 as_bad_where (fixP->fx_file, fixP->fx_line,
15814 _("PC-relative access out of range"));
15817 case BFD_RELOC_16_PCREL_S2:
15818 fix_validate_branch (fixP, *valP);
15820 /* We need to save the bits in the instruction since fixup_segment()
15821 might be deleting the relocation entry (i.e., a branch within
15822 the current segment). */
15823 if (! fixP->fx_done)
15826 /* Update old instruction data. */
15827 insn = read_insn (buf);
15829 if (*valP + 0x20000 <= 0x3ffff)
15831 insn |= (*valP >> 2) & 0xffff;
15832 write_insn (buf, insn);
15834 else if (fixP->fx_tcbit2
15836 && fixP->fx_frag->fr_address >= text_section->vma
15837 && (fixP->fx_frag->fr_address
15838 < text_section->vma + bfd_get_section_size (text_section))
15839 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
15840 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
15841 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
15843 /* The branch offset is too large. If this is an
15844 unconditional branch, and we are not generating PIC code,
15845 we can convert it to an absolute jump instruction. */
15846 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
15847 insn = 0x0c000000; /* jal */
15849 insn = 0x08000000; /* j */
15850 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
15852 fixP->fx_addsy = section_symbol (text_section);
15853 *valP += md_pcrel_from (fixP);
15854 write_insn (buf, insn);
15858 /* If we got here, we have branch-relaxation disabled,
15859 and there's nothing we can do to fix this instruction
15860 without turning it into a longer sequence. */
15861 as_bad_where (fixP->fx_file, fixP->fx_line,
15862 _("branch out of range"));
15866 case BFD_RELOC_MIPS16_16_PCREL_S1:
15867 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15868 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15869 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15870 gas_assert (!fixP->fx_done);
15871 if (fix_bad_cross_mode_branch_p (fixP))
15872 as_bad_where (fixP->fx_file, fixP->fx_line,
15873 _("branch to a symbol in another ISA mode"));
15874 else if (fixP->fx_addsy
15875 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
15876 && !bfd_is_abs_section (S_GET_SEGMENT (fixP->fx_addsy))
15877 && (fixP->fx_offset & 0x1) != 0)
15878 as_bad_where (fixP->fx_file, fixP->fx_line,
15879 _("branch to misaligned address (0x%lx)"),
15880 (long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset));
15881 else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x1) != 0)
15882 as_bad_where (fixP->fx_file, fixP->fx_line,
15883 _("cannot encode misaligned addend "
15884 "in the relocatable field (0x%lx)"),
15885 (long) fixP->fx_offset);
15888 case BFD_RELOC_VTABLE_INHERIT:
15891 && !S_IS_DEFINED (fixP->fx_addsy)
15892 && !S_IS_WEAK (fixP->fx_addsy))
15893 S_SET_WEAK (fixP->fx_addsy);
15896 case BFD_RELOC_NONE:
15897 case BFD_RELOC_VTABLE_ENTRY:
15905 /* Remember value for tc_gen_reloc. */
15906 fixP->fx_addnumber = *valP;
15916 c = get_symbol_name (&name);
15917 p = (symbolS *) symbol_find_or_make (name);
15918 (void) restore_line_pointer (c);
15922 /* Align the current frag to a given power of two. If a particular
15923 fill byte should be used, FILL points to an integer that contains
15924 that byte, otherwise FILL is null.
15926 This function used to have the comment:
15928 The MIPS assembler also automatically adjusts any preceding label.
15930 The implementation therefore applied the adjustment to a maximum of
15931 one label. However, other label adjustments are applied to batches
15932 of labels, and adjusting just one caused problems when new labels
15933 were added for the sake of debugging or unwind information.
15934 We therefore adjust all preceding labels (given as LABELS) instead. */
15937 mips_align (int to, int *fill, struct insn_label_list *labels)
15939 mips_emit_delays ();
15940 mips_record_compressed_mode ();
15941 if (fill == NULL && subseg_text_p (now_seg))
15942 frag_align_code (to, 0);
15944 frag_align (to, fill ? *fill : 0, 0);
15945 record_alignment (now_seg, to);
15946 mips_move_labels (labels, FALSE);
15949 /* Align to a given power of two. .align 0 turns off the automatic
15950 alignment used by the data creating pseudo-ops. */
15953 s_align (int x ATTRIBUTE_UNUSED)
15955 int temp, fill_value, *fill_ptr;
15956 long max_alignment = 28;
15958 /* o Note that the assembler pulls down any immediately preceding label
15959 to the aligned address.
15960 o It's not documented but auto alignment is reinstated by
15961 a .align pseudo instruction.
15962 o Note also that after auto alignment is turned off the mips assembler
15963 issues an error on attempt to assemble an improperly aligned data item.
15966 temp = get_absolute_expression ();
15967 if (temp > max_alignment)
15968 as_bad (_("alignment too large, %d assumed"), temp = max_alignment);
15971 as_warn (_("alignment negative, 0 assumed"));
15974 if (*input_line_pointer == ',')
15976 ++input_line_pointer;
15977 fill_value = get_absolute_expression ();
15978 fill_ptr = &fill_value;
15984 segment_info_type *si = seg_info (now_seg);
15985 struct insn_label_list *l = si->label_list;
15986 /* Auto alignment should be switched on by next section change. */
15988 mips_align (temp, fill_ptr, l);
15995 demand_empty_rest_of_line ();
15999 s_change_sec (int sec)
16003 /* The ELF backend needs to know that we are changing sections, so
16004 that .previous works correctly. We could do something like check
16005 for an obj_section_change_hook macro, but that might be confusing
16006 as it would not be appropriate to use it in the section changing
16007 functions in read.c, since obj-elf.c intercepts those. FIXME:
16008 This should be cleaner, somehow. */
16009 obj_elf_section_change_hook ();
16011 mips_emit_delays ();
16022 subseg_set (bss_section, (subsegT) get_absolute_expression ());
16023 demand_empty_rest_of_line ();
16027 seg = subseg_new (RDATA_SECTION_NAME,
16028 (subsegT) get_absolute_expression ());
16029 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
16030 | SEC_READONLY | SEC_RELOC
16032 if (strncmp (TARGET_OS, "elf", 3) != 0)
16033 record_alignment (seg, 4);
16034 demand_empty_rest_of_line ();
16038 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
16039 bfd_set_section_flags (stdoutput, seg,
16040 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
16041 if (strncmp (TARGET_OS, "elf", 3) != 0)
16042 record_alignment (seg, 4);
16043 demand_empty_rest_of_line ();
16047 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
16048 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
16049 if (strncmp (TARGET_OS, "elf", 3) != 0)
16050 record_alignment (seg, 4);
16051 demand_empty_rest_of_line ();
16059 s_change_section (int ignore ATTRIBUTE_UNUSED)
16062 char *section_name;
16067 int section_entry_size;
16068 int section_alignment;
16070 saved_ilp = input_line_pointer;
16071 endc = get_symbol_name (§ion_name);
16072 c = (endc == '"' ? input_line_pointer[1] : endc);
16074 next_c = input_line_pointer [(endc == '"' ? 2 : 1)];
16076 /* Do we have .section Name<,"flags">? */
16077 if (c != ',' || (c == ',' && next_c == '"'))
16079 /* Just after name is now '\0'. */
16080 (void) restore_line_pointer (endc);
16081 input_line_pointer = saved_ilp;
16082 obj_elf_section (ignore);
16086 section_name = xstrdup (section_name);
16087 c = restore_line_pointer (endc);
16089 input_line_pointer++;
16091 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16093 section_type = get_absolute_expression ();
16097 if (*input_line_pointer++ == ',')
16098 section_flag = get_absolute_expression ();
16102 if (*input_line_pointer++ == ',')
16103 section_entry_size = get_absolute_expression ();
16105 section_entry_size = 0;
16107 if (*input_line_pointer++ == ',')
16108 section_alignment = get_absolute_expression ();
16110 section_alignment = 0;
16112 /* FIXME: really ignore? */
16113 (void) section_alignment;
16115 /* When using the generic form of .section (as implemented by obj-elf.c),
16116 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16117 traditionally had to fall back on the more common @progbits instead.
16119 There's nothing really harmful in this, since bfd will correct
16120 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16121 means that, for backwards compatibility, the special_section entries
16122 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16124 Even so, we shouldn't force users of the MIPS .section syntax to
16125 incorrectly label the sections as SHT_PROGBITS. The best compromise
16126 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16127 generic type-checking code. */
16128 if (section_type == SHT_MIPS_DWARF)
16129 section_type = SHT_PROGBITS;
16131 obj_elf_change_section (section_name, section_type, 0, section_flag,
16132 section_entry_size, 0, 0, 0);
16134 if (now_seg->name != section_name)
16135 free (section_name);
16139 mips_enable_auto_align (void)
16145 s_cons (int log_size)
16147 segment_info_type *si = seg_info (now_seg);
16148 struct insn_label_list *l = si->label_list;
16150 mips_emit_delays ();
16151 if (log_size > 0 && auto_align)
16152 mips_align (log_size, 0, l);
16153 cons (1 << log_size);
16154 mips_clear_insn_labels ();
16158 s_float_cons (int type)
16160 segment_info_type *si = seg_info (now_seg);
16161 struct insn_label_list *l = si->label_list;
16163 mips_emit_delays ();
16168 mips_align (3, 0, l);
16170 mips_align (2, 0, l);
16174 mips_clear_insn_labels ();
16177 /* Handle .globl. We need to override it because on Irix 5 you are
16180 where foo is an undefined symbol, to mean that foo should be
16181 considered to be the address of a function. */
16184 s_mips_globl (int x ATTRIBUTE_UNUSED)
16193 c = get_symbol_name (&name);
16194 symbolP = symbol_find_or_make (name);
16195 S_SET_EXTERNAL (symbolP);
16197 *input_line_pointer = c;
16198 SKIP_WHITESPACE_AFTER_NAME ();
16200 /* On Irix 5, every global symbol that is not explicitly labelled as
16201 being a function is apparently labelled as being an object. */
16204 if (!is_end_of_line[(unsigned char) *input_line_pointer]
16205 && (*input_line_pointer != ','))
16210 c = get_symbol_name (&secname);
16211 sec = bfd_get_section_by_name (stdoutput, secname);
16213 as_bad (_("%s: no such section"), secname);
16214 (void) restore_line_pointer (c);
16216 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
16217 flag = BSF_FUNCTION;
16220 symbol_get_bfdsym (symbolP)->flags |= flag;
16222 c = *input_line_pointer;
16225 input_line_pointer++;
16226 SKIP_WHITESPACE ();
16227 if (is_end_of_line[(unsigned char) *input_line_pointer])
16233 demand_empty_rest_of_line ();
16237 s_option (int x ATTRIBUTE_UNUSED)
16242 c = get_symbol_name (&opt);
16246 /* FIXME: What does this mean? */
16248 else if (strncmp (opt, "pic", 3) == 0 && ISDIGIT (opt[3]) && opt[4] == '\0')
16252 i = atoi (opt + 3);
16253 if (i != 0 && i != 2)
16254 as_bad (_(".option pic%d not supported"), i);
16255 else if (mips_pic == VXWORKS_PIC)
16256 as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i);
16261 mips_pic = SVR4_PIC;
16262 mips_abicalls = TRUE;
16265 if (mips_pic == SVR4_PIC)
16267 if (g_switch_seen && g_switch_value != 0)
16268 as_warn (_("-G may not be used with SVR4 PIC code"));
16269 g_switch_value = 0;
16270 bfd_set_gp_size (stdoutput, 0);
16274 as_warn (_("unrecognized option \"%s\""), opt);
16276 (void) restore_line_pointer (c);
16277 demand_empty_rest_of_line ();
16280 /* This structure is used to hold a stack of .set values. */
16282 struct mips_option_stack
16284 struct mips_option_stack *next;
16285 struct mips_set_options options;
16288 static struct mips_option_stack *mips_opts_stack;
16290 /* Return status for .set/.module option handling. */
16292 enum code_option_type
16294 /* Unrecognized option. */
16295 OPTION_TYPE_BAD = -1,
16297 /* Ordinary option. */
16298 OPTION_TYPE_NORMAL,
16300 /* ISA changing option. */
16304 /* Handle common .set/.module options. Return status indicating option
16307 static enum code_option_type
16308 parse_code_option (char * name)
16310 bfd_boolean isa_set = FALSE;
16311 const struct mips_ase *ase;
16313 if (strncmp (name, "at=", 3) == 0)
16315 char *s = name + 3;
16317 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
16318 as_bad (_("unrecognized register name `%s'"), s);
16320 else if (strcmp (name, "at") == 0)
16321 mips_opts.at = ATREG;
16322 else if (strcmp (name, "noat") == 0)
16323 mips_opts.at = ZERO;
16324 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
16325 mips_opts.nomove = 0;
16326 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
16327 mips_opts.nomove = 1;
16328 else if (strcmp (name, "bopt") == 0)
16329 mips_opts.nobopt = 0;
16330 else if (strcmp (name, "nobopt") == 0)
16331 mips_opts.nobopt = 1;
16332 else if (strcmp (name, "gp=32") == 0)
16334 else if (strcmp (name, "gp=64") == 0)
16336 else if (strcmp (name, "fp=32") == 0)
16338 else if (strcmp (name, "fp=xx") == 0)
16340 else if (strcmp (name, "fp=64") == 0)
16342 else if (strcmp (name, "softfloat") == 0)
16343 mips_opts.soft_float = 1;
16344 else if (strcmp (name, "hardfloat") == 0)
16345 mips_opts.soft_float = 0;
16346 else if (strcmp (name, "singlefloat") == 0)
16347 mips_opts.single_float = 1;
16348 else if (strcmp (name, "doublefloat") == 0)
16349 mips_opts.single_float = 0;
16350 else if (strcmp (name, "nooddspreg") == 0)
16351 mips_opts.oddspreg = 0;
16352 else if (strcmp (name, "oddspreg") == 0)
16353 mips_opts.oddspreg = 1;
16354 else if (strcmp (name, "mips16") == 0
16355 || strcmp (name, "MIPS-16") == 0)
16356 mips_opts.mips16 = 1;
16357 else if (strcmp (name, "nomips16") == 0
16358 || strcmp (name, "noMIPS-16") == 0)
16359 mips_opts.mips16 = 0;
16360 else if (strcmp (name, "micromips") == 0)
16361 mips_opts.micromips = 1;
16362 else if (strcmp (name, "nomicromips") == 0)
16363 mips_opts.micromips = 0;
16364 else if (name[0] == 'n'
16366 && (ase = mips_lookup_ase (name + 2)))
16367 mips_set_ase (ase, &mips_opts, FALSE);
16368 else if ((ase = mips_lookup_ase (name)))
16369 mips_set_ase (ase, &mips_opts, TRUE);
16370 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
16372 /* Permit the user to change the ISA and architecture on the fly.
16373 Needless to say, misuse can cause serious problems. */
16374 if (strncmp (name, "arch=", 5) == 0)
16376 const struct mips_cpu_info *p;
16378 p = mips_parse_cpu ("internal use", name + 5);
16380 as_bad (_("unknown architecture %s"), name + 5);
16383 mips_opts.arch = p->cpu;
16384 mips_opts.isa = p->isa;
16388 else if (strncmp (name, "mips", 4) == 0)
16390 const struct mips_cpu_info *p;
16392 p = mips_parse_cpu ("internal use", name);
16394 as_bad (_("unknown ISA level %s"), name + 4);
16397 mips_opts.arch = p->cpu;
16398 mips_opts.isa = p->isa;
16403 as_bad (_("unknown ISA or architecture %s"), name);
16405 else if (strcmp (name, "autoextend") == 0)
16406 mips_opts.noautoextend = 0;
16407 else if (strcmp (name, "noautoextend") == 0)
16408 mips_opts.noautoextend = 1;
16409 else if (strcmp (name, "insn32") == 0)
16410 mips_opts.insn32 = TRUE;
16411 else if (strcmp (name, "noinsn32") == 0)
16412 mips_opts.insn32 = FALSE;
16413 else if (strcmp (name, "sym32") == 0)
16414 mips_opts.sym32 = TRUE;
16415 else if (strcmp (name, "nosym32") == 0)
16416 mips_opts.sym32 = FALSE;
16418 return OPTION_TYPE_BAD;
16420 return isa_set ? OPTION_TYPE_ISA : OPTION_TYPE_NORMAL;
16423 /* Handle the .set pseudo-op. */
16426 s_mipsset (int x ATTRIBUTE_UNUSED)
16428 enum code_option_type type = OPTION_TYPE_NORMAL;
16429 char *name = input_line_pointer, ch;
16431 file_mips_check_options ();
16433 while (!is_end_of_line[(unsigned char) *input_line_pointer])
16434 ++input_line_pointer;
16435 ch = *input_line_pointer;
16436 *input_line_pointer = '\0';
16438 if (strchr (name, ','))
16440 /* Generic ".set" directive; use the generic handler. */
16441 *input_line_pointer = ch;
16442 input_line_pointer = name;
16447 if (strcmp (name, "reorder") == 0)
16449 if (mips_opts.noreorder)
16452 else if (strcmp (name, "noreorder") == 0)
16454 if (!mips_opts.noreorder)
16455 start_noreorder ();
16457 else if (strcmp (name, "macro") == 0)
16458 mips_opts.warn_about_macros = 0;
16459 else if (strcmp (name, "nomacro") == 0)
16461 if (mips_opts.noreorder == 0)
16462 as_bad (_("`noreorder' must be set before `nomacro'"));
16463 mips_opts.warn_about_macros = 1;
16465 else if (strcmp (name, "gp=default") == 0)
16466 mips_opts.gp = file_mips_opts.gp;
16467 else if (strcmp (name, "fp=default") == 0)
16468 mips_opts.fp = file_mips_opts.fp;
16469 else if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
16471 mips_opts.isa = file_mips_opts.isa;
16472 mips_opts.arch = file_mips_opts.arch;
16473 mips_opts.gp = file_mips_opts.gp;
16474 mips_opts.fp = file_mips_opts.fp;
16476 else if (strcmp (name, "push") == 0)
16478 struct mips_option_stack *s;
16480 s = XNEW (struct mips_option_stack);
16481 s->next = mips_opts_stack;
16482 s->options = mips_opts;
16483 mips_opts_stack = s;
16485 else if (strcmp (name, "pop") == 0)
16487 struct mips_option_stack *s;
16489 s = mips_opts_stack;
16491 as_bad (_(".set pop with no .set push"));
16494 /* If we're changing the reorder mode we need to handle
16495 delay slots correctly. */
16496 if (s->options.noreorder && ! mips_opts.noreorder)
16497 start_noreorder ();
16498 else if (! s->options.noreorder && mips_opts.noreorder)
16501 mips_opts = s->options;
16502 mips_opts_stack = s->next;
16508 type = parse_code_option (name);
16509 if (type == OPTION_TYPE_BAD)
16510 as_warn (_("tried to set unrecognized symbol: %s\n"), name);
16513 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
16514 registers based on what is supported by the arch/cpu. */
16515 if (type == OPTION_TYPE_ISA)
16517 switch (mips_opts.isa)
16522 /* MIPS I cannot support FPXX. */
16524 /* fall-through. */
16531 if (mips_opts.fp != 0)
16547 if (mips_opts.fp != 0)
16549 if (mips_opts.arch == CPU_R5900)
16556 as_bad (_("unknown ISA level %s"), name + 4);
16561 mips_check_options (&mips_opts, FALSE);
16563 mips_check_isa_supports_ases ();
16564 *input_line_pointer = ch;
16565 demand_empty_rest_of_line ();
16568 /* Handle the .module pseudo-op. */
16571 s_module (int ignore ATTRIBUTE_UNUSED)
16573 char *name = input_line_pointer, ch;
16575 while (!is_end_of_line[(unsigned char) *input_line_pointer])
16576 ++input_line_pointer;
16577 ch = *input_line_pointer;
16578 *input_line_pointer = '\0';
16580 if (!file_mips_opts_checked)
16582 if (parse_code_option (name) == OPTION_TYPE_BAD)
16583 as_bad (_(".module used with unrecognized symbol: %s\n"), name);
16585 /* Update module level settings from mips_opts. */
16586 file_mips_opts = mips_opts;
16589 as_bad (_(".module is not permitted after generating code"));
16591 *input_line_pointer = ch;
16592 demand_empty_rest_of_line ();
16595 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16596 .option pic2. It means to generate SVR4 PIC calls. */
16599 s_abicalls (int ignore ATTRIBUTE_UNUSED)
16601 mips_pic = SVR4_PIC;
16602 mips_abicalls = TRUE;
16604 if (g_switch_seen && g_switch_value != 0)
16605 as_warn (_("-G may not be used with SVR4 PIC code"));
16606 g_switch_value = 0;
16608 bfd_set_gp_size (stdoutput, 0);
16609 demand_empty_rest_of_line ();
16612 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16613 PIC code. It sets the $gp register for the function based on the
16614 function address, which is in the register named in the argument.
16615 This uses a relocation against _gp_disp, which is handled specially
16616 by the linker. The result is:
16617 lui $gp,%hi(_gp_disp)
16618 addiu $gp,$gp,%lo(_gp_disp)
16619 addu $gp,$gp,.cpload argument
16620 The .cpload argument is normally $25 == $t9.
16622 The -mno-shared option changes this to:
16623 lui $gp,%hi(__gnu_local_gp)
16624 addiu $gp,$gp,%lo(__gnu_local_gp)
16625 and the argument is ignored. This saves an instruction, but the
16626 resulting code is not position independent; it uses an absolute
16627 address for __gnu_local_gp. Thus code assembled with -mno-shared
16628 can go into an ordinary executable, but not into a shared library. */
16631 s_cpload (int ignore ATTRIBUTE_UNUSED)
16637 file_mips_check_options ();
16639 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16640 .cpload is ignored. */
16641 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16647 if (mips_opts.mips16)
16649 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16650 ignore_rest_of_line ();
16654 /* .cpload should be in a .set noreorder section. */
16655 if (mips_opts.noreorder == 0)
16656 as_warn (_(".cpload not in noreorder section"));
16658 reg = tc_get_register (0);
16660 /* If we need to produce a 64-bit address, we are better off using
16661 the default instruction sequence. */
16662 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
16664 ex.X_op = O_symbol;
16665 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
16667 ex.X_op_symbol = NULL;
16668 ex.X_add_number = 0;
16670 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16671 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16673 mips_mark_labels ();
16674 mips_assembling_insn = TRUE;
16677 macro_build_lui (&ex, mips_gp_register);
16678 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16679 mips_gp_register, BFD_RELOC_LO16);
16681 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
16682 mips_gp_register, reg);
16685 mips_assembling_insn = FALSE;
16686 demand_empty_rest_of_line ();
16689 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16690 .cpsetup $reg1, offset|$reg2, label
16692 If offset is given, this results in:
16693 sd $gp, offset($sp)
16694 lui $gp, %hi(%neg(%gp_rel(label)))
16695 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16696 daddu $gp, $gp, $reg1
16698 If $reg2 is given, this results in:
16700 lui $gp, %hi(%neg(%gp_rel(label)))
16701 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16702 daddu $gp, $gp, $reg1
16703 $reg1 is normally $25 == $t9.
16705 The -mno-shared option replaces the last three instructions with
16707 addiu $gp,$gp,%lo(_gp) */
16710 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
16712 expressionS ex_off;
16713 expressionS ex_sym;
16716 file_mips_check_options ();
16718 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16719 We also need NewABI support. */
16720 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16726 if (mips_opts.mips16)
16728 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16729 ignore_rest_of_line ();
16733 reg1 = tc_get_register (0);
16734 SKIP_WHITESPACE ();
16735 if (*input_line_pointer != ',')
16737 as_bad (_("missing argument separator ',' for .cpsetup"));
16741 ++input_line_pointer;
16742 SKIP_WHITESPACE ();
16743 if (*input_line_pointer == '$')
16745 mips_cpreturn_register = tc_get_register (0);
16746 mips_cpreturn_offset = -1;
16750 mips_cpreturn_offset = get_absolute_expression ();
16751 mips_cpreturn_register = -1;
16753 SKIP_WHITESPACE ();
16754 if (*input_line_pointer != ',')
16756 as_bad (_("missing argument separator ',' for .cpsetup"));
16760 ++input_line_pointer;
16761 SKIP_WHITESPACE ();
16762 expression (&ex_sym);
16764 mips_mark_labels ();
16765 mips_assembling_insn = TRUE;
16768 if (mips_cpreturn_register == -1)
16770 ex_off.X_op = O_constant;
16771 ex_off.X_add_symbol = NULL;
16772 ex_off.X_op_symbol = NULL;
16773 ex_off.X_add_number = mips_cpreturn_offset;
16775 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
16776 BFD_RELOC_LO16, SP);
16779 move_register (mips_cpreturn_register, mips_gp_register);
16781 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
16783 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
16784 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
16787 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
16788 mips_gp_register, -1, BFD_RELOC_GPREL16,
16789 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
16791 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
16792 mips_gp_register, reg1);
16798 ex.X_op = O_symbol;
16799 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
16800 ex.X_op_symbol = NULL;
16801 ex.X_add_number = 0;
16803 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16804 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16806 macro_build_lui (&ex, mips_gp_register);
16807 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16808 mips_gp_register, BFD_RELOC_LO16);
16813 mips_assembling_insn = FALSE;
16814 demand_empty_rest_of_line ();
16818 s_cplocal (int ignore ATTRIBUTE_UNUSED)
16820 file_mips_check_options ();
16822 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16823 .cplocal is ignored. */
16824 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16830 if (mips_opts.mips16)
16832 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16833 ignore_rest_of_line ();
16837 mips_gp_register = tc_get_register (0);
16838 demand_empty_rest_of_line ();
16841 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16842 offset from $sp. The offset is remembered, and after making a PIC
16843 call $gp is restored from that location. */
16846 s_cprestore (int ignore ATTRIBUTE_UNUSED)
16850 file_mips_check_options ();
16852 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16853 .cprestore is ignored. */
16854 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16860 if (mips_opts.mips16)
16862 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16863 ignore_rest_of_line ();
16867 mips_cprestore_offset = get_absolute_expression ();
16868 mips_cprestore_valid = 1;
16870 ex.X_op = O_constant;
16871 ex.X_add_symbol = NULL;
16872 ex.X_op_symbol = NULL;
16873 ex.X_add_number = mips_cprestore_offset;
16875 mips_mark_labels ();
16876 mips_assembling_insn = TRUE;
16879 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
16880 SP, HAVE_64BIT_ADDRESSES);
16883 mips_assembling_insn = FALSE;
16884 demand_empty_rest_of_line ();
16887 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16888 was given in the preceding .cpsetup, it results in:
16889 ld $gp, offset($sp)
16891 If a register $reg2 was given there, it results in:
16892 or $gp, $reg2, $0 */
16895 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
16899 file_mips_check_options ();
16901 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16902 We also need NewABI support. */
16903 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16909 if (mips_opts.mips16)
16911 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16912 ignore_rest_of_line ();
16916 mips_mark_labels ();
16917 mips_assembling_insn = TRUE;
16920 if (mips_cpreturn_register == -1)
16922 ex.X_op = O_constant;
16923 ex.X_add_symbol = NULL;
16924 ex.X_op_symbol = NULL;
16925 ex.X_add_number = mips_cpreturn_offset;
16927 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
16930 move_register (mips_gp_register, mips_cpreturn_register);
16934 mips_assembling_insn = FALSE;
16935 demand_empty_rest_of_line ();
16938 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16939 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16940 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16941 debug information or MIPS16 TLS. */
16944 s_tls_rel_directive (const size_t bytes, const char *dirstr,
16945 bfd_reloc_code_real_type rtype)
16952 if (ex.X_op != O_symbol)
16954 as_bad (_("unsupported use of %s"), dirstr);
16955 ignore_rest_of_line ();
16958 p = frag_more (bytes);
16959 md_number_to_chars (p, 0, bytes);
16960 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
16961 demand_empty_rest_of_line ();
16962 mips_clear_insn_labels ();
16965 /* Handle .dtprelword. */
16968 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
16970 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
16973 /* Handle .dtpreldword. */
16976 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
16978 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
16981 /* Handle .tprelword. */
16984 s_tprelword (int ignore ATTRIBUTE_UNUSED)
16986 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
16989 /* Handle .tpreldword. */
16992 s_tpreldword (int ignore ATTRIBUTE_UNUSED)
16994 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
16997 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16998 code. It sets the offset to use in gp_rel relocations. */
17001 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
17003 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
17004 We also need NewABI support. */
17005 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
17011 mips_gprel_offset = get_absolute_expression ();
17013 demand_empty_rest_of_line ();
17016 /* Handle the .gpword pseudo-op. This is used when generating PIC
17017 code. It generates a 32 bit GP relative reloc. */
17020 s_gpword (int ignore ATTRIBUTE_UNUSED)
17022 segment_info_type *si;
17023 struct insn_label_list *l;
17027 /* When not generating PIC code, this is treated as .word. */
17028 if (mips_pic != SVR4_PIC)
17034 si = seg_info (now_seg);
17035 l = si->label_list;
17036 mips_emit_delays ();
17038 mips_align (2, 0, l);
17041 mips_clear_insn_labels ();
17043 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17045 as_bad (_("unsupported use of .gpword"));
17046 ignore_rest_of_line ();
17050 md_number_to_chars (p, 0, 4);
17051 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17052 BFD_RELOC_GPREL32);
17054 demand_empty_rest_of_line ();
17058 s_gpdword (int ignore ATTRIBUTE_UNUSED)
17060 segment_info_type *si;
17061 struct insn_label_list *l;
17065 /* When not generating PIC code, this is treated as .dword. */
17066 if (mips_pic != SVR4_PIC)
17072 si = seg_info (now_seg);
17073 l = si->label_list;
17074 mips_emit_delays ();
17076 mips_align (3, 0, l);
17079 mips_clear_insn_labels ();
17081 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17083 as_bad (_("unsupported use of .gpdword"));
17084 ignore_rest_of_line ();
17088 md_number_to_chars (p, 0, 8);
17089 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17090 BFD_RELOC_GPREL32)->fx_tcbit = 1;
17092 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17093 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
17094 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
17096 demand_empty_rest_of_line ();
17099 /* Handle the .ehword pseudo-op. This is used when generating unwinding
17100 tables. It generates a R_MIPS_EH reloc. */
17103 s_ehword (int ignore ATTRIBUTE_UNUSED)
17108 mips_emit_delays ();
17111 mips_clear_insn_labels ();
17113 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17115 as_bad (_("unsupported use of .ehword"));
17116 ignore_rest_of_line ();
17120 md_number_to_chars (p, 0, 4);
17121 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17122 BFD_RELOC_32_PCREL);
17124 demand_empty_rest_of_line ();
17127 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17128 tables in SVR4 PIC code. */
17131 s_cpadd (int ignore ATTRIBUTE_UNUSED)
17135 file_mips_check_options ();
17137 /* This is ignored when not generating SVR4 PIC code. */
17138 if (mips_pic != SVR4_PIC)
17144 mips_mark_labels ();
17145 mips_assembling_insn = TRUE;
17147 /* Add $gp to the register named as an argument. */
17149 reg = tc_get_register (0);
17150 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
17153 mips_assembling_insn = FALSE;
17154 demand_empty_rest_of_line ();
17157 /* Handle the .insn pseudo-op. This marks instruction labels in
17158 mips16/micromips mode. This permits the linker to handle them specially,
17159 such as generating jalx instructions when needed. We also make
17160 them odd for the duration of the assembly, in order to generate the
17161 right sort of code. We will make them even in the adjust_symtab
17162 routine, while leaving them marked. This is convenient for the
17163 debugger and the disassembler. The linker knows to make them odd
17167 s_insn (int ignore ATTRIBUTE_UNUSED)
17169 file_mips_check_options ();
17170 file_ase_mips16 |= mips_opts.mips16;
17171 file_ase_micromips |= mips_opts.micromips;
17173 mips_mark_labels ();
17175 demand_empty_rest_of_line ();
17178 /* Handle the .nan pseudo-op. */
17181 s_nan (int ignore ATTRIBUTE_UNUSED)
17183 static const char str_legacy[] = "legacy";
17184 static const char str_2008[] = "2008";
17187 for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++);
17189 if (i == sizeof (str_2008) - 1
17190 && memcmp (input_line_pointer, str_2008, i) == 0)
17192 else if (i == sizeof (str_legacy) - 1
17193 && memcmp (input_line_pointer, str_legacy, i) == 0)
17195 if (ISA_HAS_LEGACY_NAN (file_mips_opts.isa))
17198 as_bad (_("`%s' does not support legacy NaN"),
17199 mips_cpu_info_from_isa (file_mips_opts.isa)->name);
17202 as_bad (_("bad .nan directive"));
17204 input_line_pointer += i;
17205 demand_empty_rest_of_line ();
17208 /* Handle a .stab[snd] directive. Ideally these directives would be
17209 implemented in a transparent way, so that removing them would not
17210 have any effect on the generated instructions. However, s_stab
17211 internally changes the section, so in practice we need to decide
17212 now whether the preceding label marks compressed code. We do not
17213 support changing the compression mode of a label after a .stab*
17214 directive, such as in:
17220 so the current mode wins. */
17223 s_mips_stab (int type)
17225 file_mips_check_options ();
17226 mips_mark_labels ();
17230 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17233 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
17240 c = get_symbol_name (&name);
17241 symbolP = symbol_find_or_make (name);
17242 S_SET_WEAK (symbolP);
17243 *input_line_pointer = c;
17245 SKIP_WHITESPACE_AFTER_NAME ();
17247 if (! is_end_of_line[(unsigned char) *input_line_pointer])
17249 if (S_IS_DEFINED (symbolP))
17251 as_bad (_("ignoring attempt to redefine symbol %s"),
17252 S_GET_NAME (symbolP));
17253 ignore_rest_of_line ();
17257 if (*input_line_pointer == ',')
17259 ++input_line_pointer;
17260 SKIP_WHITESPACE ();
17264 if (exp.X_op != O_symbol)
17266 as_bad (_("bad .weakext directive"));
17267 ignore_rest_of_line ();
17270 symbol_set_value_expression (symbolP, &exp);
17273 demand_empty_rest_of_line ();
17276 /* Parse a register string into a number. Called from the ECOFF code
17277 to parse .frame. The argument is non-zero if this is the frame
17278 register, so that we can record it in mips_frame_reg. */
17281 tc_get_register (int frame)
17285 SKIP_WHITESPACE ();
17286 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
17290 mips_frame_reg = reg != 0 ? reg : SP;
17291 mips_frame_reg_valid = 1;
17292 mips_cprestore_valid = 0;
17298 md_section_align (asection *seg, valueT addr)
17300 int align = bfd_get_section_alignment (stdoutput, seg);
17302 /* We don't need to align ELF sections to the full alignment.
17303 However, Irix 5 may prefer that we align them at least to a 16
17304 byte boundary. We don't bother to align the sections if we
17305 are targeted for an embedded system. */
17306 if (strncmp (TARGET_OS, "elf", 3) == 0)
17311 return ((addr + (1 << align) - 1) & -(1 << align));
17314 /* Utility routine, called from above as well. If called while the
17315 input file is still being read, it's only an approximation. (For
17316 example, a symbol may later become defined which appeared to be
17317 undefined earlier.) */
17320 nopic_need_relax (symbolS *sym, int before_relaxing)
17325 if (g_switch_value > 0)
17327 const char *symname;
17330 /* Find out whether this symbol can be referenced off the $gp
17331 register. It can be if it is smaller than the -G size or if
17332 it is in the .sdata or .sbss section. Certain symbols can
17333 not be referenced off the $gp, although it appears as though
17335 symname = S_GET_NAME (sym);
17336 if (symname != (const char *) NULL
17337 && (strcmp (symname, "eprol") == 0
17338 || strcmp (symname, "etext") == 0
17339 || strcmp (symname, "_gp") == 0
17340 || strcmp (symname, "edata") == 0
17341 || strcmp (symname, "_fbss") == 0
17342 || strcmp (symname, "_fdata") == 0
17343 || strcmp (symname, "_ftext") == 0
17344 || strcmp (symname, "end") == 0
17345 || strcmp (symname, "_gp_disp") == 0))
17347 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
17349 #ifndef NO_ECOFF_DEBUGGING
17350 || (symbol_get_obj (sym)->ecoff_extern_size != 0
17351 && (symbol_get_obj (sym)->ecoff_extern_size
17352 <= g_switch_value))
17354 /* We must defer this decision until after the whole
17355 file has been read, since there might be a .extern
17356 after the first use of this symbol. */
17357 || (before_relaxing
17358 #ifndef NO_ECOFF_DEBUGGING
17359 && symbol_get_obj (sym)->ecoff_extern_size == 0
17361 && S_GET_VALUE (sym) == 0)
17362 || (S_GET_VALUE (sym) != 0
17363 && S_GET_VALUE (sym) <= g_switch_value)))
17367 const char *segname;
17369 segname = segment_name (S_GET_SEGMENT (sym));
17370 gas_assert (strcmp (segname, ".lit8") != 0
17371 && strcmp (segname, ".lit4") != 0);
17372 change = (strcmp (segname, ".sdata") != 0
17373 && strcmp (segname, ".sbss") != 0
17374 && strncmp (segname, ".sdata.", 7) != 0
17375 && strncmp (segname, ".sbss.", 6) != 0
17376 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
17377 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
17382 /* We are not optimizing for the $gp register. */
17387 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17390 pic_need_relax (symbolS *sym)
17394 /* Handle the case of a symbol equated to another symbol. */
17395 while (symbol_equated_reloc_p (sym))
17399 /* It's possible to get a loop here in a badly written program. */
17400 n = symbol_get_value_expression (sym)->X_add_symbol;
17406 if (symbol_section_p (sym))
17409 symsec = S_GET_SEGMENT (sym);
17411 /* This must duplicate the test in adjust_reloc_syms. */
17412 return (!bfd_is_und_section (symsec)
17413 && !bfd_is_abs_section (symsec)
17414 && !bfd_is_com_section (symsec)
17415 /* A global or weak symbol is treated as external. */
17416 && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym)));
17419 /* Given a MIPS16 variant frag FRAGP and PC-relative operand PCREL_OP
17420 convert a section-relative value VAL to the equivalent PC-relative
17424 mips16_pcrel_val (fragS *fragp, const struct mips_pcrel_operand *pcrel_op,
17425 offsetT val, long stretch)
17430 gas_assert (pcrel_op->root.root.type == OP_PCREL);
17432 sym_frag = symbol_get_frag (fragp->fr_symbol);
17434 /* If the relax_marker of the symbol fragment differs from the
17435 relax_marker of this fragment, we have not yet adjusted the
17436 symbol fragment fr_address. We want to add in STRETCH in
17437 order to get a better estimate of the address. This
17438 particularly matters because of the shift bits. */
17439 if (stretch != 0 && sym_frag->relax_marker != fragp->relax_marker)
17443 /* Adjust stretch for any alignment frag. Note that if have
17444 been expanding the earlier code, the symbol may be
17445 defined in what appears to be an earlier frag. FIXME:
17446 This doesn't handle the fr_subtype field, which specifies
17447 a maximum number of bytes to skip when doing an
17449 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
17451 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
17454 stretch = -(-stretch & ~((1 << (int) f->fr_offset) - 1));
17456 stretch &= ~((1 << (int) f->fr_offset) - 1);
17465 addr = fragp->fr_address + fragp->fr_fix;
17467 /* The base address rules are complicated. The base address of
17468 a branch is the following instruction. The base address of a
17469 PC relative load or add is the instruction itself, but if it
17470 is in a delay slot (in which case it can not be extended) use
17471 the address of the instruction whose delay slot it is in. */
17472 if (pcrel_op->include_isa_bit)
17476 /* If we are currently assuming that this frag should be
17477 extended, then the current address is two bytes higher. */
17478 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17481 /* Ignore the low bit in the target, since it will be set
17482 for a text label. */
17485 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17487 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17490 val -= addr & -(1 << pcrel_op->align_log2);
17495 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17496 extended opcode. SEC is the section the frag is in. */
17499 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
17501 const struct mips_int_operand *operand;
17506 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
17508 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17511 symsec = S_GET_SEGMENT (fragp->fr_symbol);
17512 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
17513 operand = mips16_immed_operand (type, FALSE);
17514 if (S_FORCE_RELOC (fragp->fr_symbol, TRUE)
17515 || (operand->root.type == OP_PCREL
17517 : !bfd_is_abs_section (symsec)))
17520 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17522 if (operand->root.type == OP_PCREL)
17524 const struct mips_pcrel_operand *pcrel_op;
17527 if (RELAX_MIPS16_ALWAYS_EXTENDED (fragp->fr_subtype))
17530 pcrel_op = (const struct mips_pcrel_operand *) operand;
17531 val = mips16_pcrel_val (fragp, pcrel_op, val, stretch);
17533 /* If any of the shifted bits are set, we must use an extended
17534 opcode. If the address depends on the size of this
17535 instruction, this can lead to a loop, so we arrange to always
17536 use an extended opcode. */
17537 if ((val & ((1 << operand->shift) - 1)) != 0)
17539 fragp->fr_subtype =
17540 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp->fr_subtype);
17544 /* If we are about to mark a frag as extended because the value
17545 is precisely the next value above maxtiny, then there is a
17546 chance of an infinite loop as in the following code:
17551 In this case when the la is extended, foo is 0x3fc bytes
17552 away, so the la can be shrunk, but then foo is 0x400 away, so
17553 the la must be extended. To avoid this loop, we mark the
17554 frag as extended if it was small, and is about to become
17555 extended with the next value above maxtiny. */
17556 maxtiny = mips_int_operand_max (operand);
17557 if (val == maxtiny + (1 << operand->shift)
17558 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17560 fragp->fr_subtype =
17561 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp->fr_subtype);
17566 return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val);
17569 /* Given a MIPS16 variant frag FRAGP, return non-zero if it needs
17570 macro expansion. SEC is the section the frag is in. We only
17571 support PC-relative instructions (LA, DLA, LW, LD) here, in
17572 non-PIC code using 32-bit addressing. */
17575 mips16_macro_frag (fragS *fragp, asection *sec, long stretch)
17577 const struct mips_pcrel_operand *pcrel_op;
17578 const struct mips_int_operand *operand;
17583 gas_assert (!RELAX_MIPS16_USER_SMALL (fragp->fr_subtype));
17585 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17587 if (!RELAX_MIPS16_SYM32 (fragp->fr_subtype))
17590 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
17596 symsec = S_GET_SEGMENT (fragp->fr_symbol);
17597 if (bfd_is_abs_section (symsec))
17599 if (RELAX_MIPS16_PIC (fragp->fr_subtype))
17601 if (S_FORCE_RELOC (fragp->fr_symbol, TRUE) || sec != symsec)
17604 operand = mips16_immed_operand (type, TRUE);
17605 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17606 pcrel_op = (const struct mips_pcrel_operand *) operand;
17607 val = mips16_pcrel_val (fragp, pcrel_op, val, stretch);
17609 return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val);
17616 /* Compute the length of a branch sequence, and adjust the
17617 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17618 worst-case length is computed, with UPDATE being used to indicate
17619 whether an unconditional (-1), branch-likely (+1) or regular (0)
17620 branch is to be computed. */
17622 relaxed_branch_length (fragS *fragp, asection *sec, int update)
17624 bfd_boolean toofar;
17628 && S_IS_DEFINED (fragp->fr_symbol)
17629 && !S_IS_WEAK (fragp->fr_symbol)
17630 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17635 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17637 addr = fragp->fr_address + fragp->fr_fix + 4;
17641 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
17644 /* If the symbol is not defined or it's in a different segment,
17645 we emit the long sequence. */
17648 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17650 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
17651 RELAX_BRANCH_PIC (fragp->fr_subtype),
17652 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
17653 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
17654 RELAX_BRANCH_LINK (fragp->fr_subtype),
17660 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
17663 if (!fragp || RELAX_BRANCH_PIC (fragp->fr_subtype))
17665 /* Additional space for PIC loading of target address. */
17667 if (mips_opts.isa == ISA_MIPS1)
17668 /* Additional space for $at-stabilizing nop. */
17672 /* If branch is conditional. */
17673 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
17680 /* Get a FRAG's branch instruction delay slot size, either from the
17681 short-delay-slot bit of a branch-and-link instruction if AL is TRUE,
17682 or SHORT_INSN_SIZE otherwise. */
17685 frag_branch_delay_slot_size (fragS *fragp, bfd_boolean al, int short_insn_size)
17687 char *buf = fragp->fr_literal + fragp->fr_fix;
17690 return (read_compressed_insn (buf, 4) & 0x02000000) ? 2 : 4;
17692 return short_insn_size;
17695 /* Compute the length of a branch sequence, and adjust the
17696 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17697 worst-case length is computed, with UPDATE being used to indicate
17698 whether an unconditional (-1), or regular (0) branch is to be
17702 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
17704 bfd_boolean insn32 = TRUE;
17705 bfd_boolean nods = TRUE;
17706 bfd_boolean pic = TRUE;
17707 bfd_boolean al = TRUE;
17708 int short_insn_size;
17709 bfd_boolean toofar;
17714 insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype);
17715 nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype);
17716 pic = RELAX_MICROMIPS_PIC (fragp->fr_subtype);
17717 al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
17719 short_insn_size = insn32 ? 4 : 2;
17722 && S_IS_DEFINED (fragp->fr_symbol)
17723 && !S_IS_WEAK (fragp->fr_symbol)
17724 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17729 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17730 /* Ignore the low bit in the target, since it will be set
17731 for a text label. */
17732 if ((val & 1) != 0)
17735 addr = fragp->fr_address + fragp->fr_fix + 4;
17739 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
17742 /* If the symbol is not defined or it's in a different segment,
17743 we emit the long sequence. */
17746 if (fragp && update
17747 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17748 fragp->fr_subtype = (toofar
17749 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
17750 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
17755 bfd_boolean compact_known = fragp != NULL;
17756 bfd_boolean compact = FALSE;
17757 bfd_boolean uncond;
17761 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17762 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
17765 uncond = update < 0;
17767 /* If label is out of range, we turn branch <br>:
17769 <br> label # 4 bytes
17776 # compact && (!PIC || insn32)
17779 if ((!pic || insn32) && (!compact_known || compact))
17780 length += short_insn_size;
17782 /* If assembling PIC code, we further turn:
17788 lw/ld at, %got(label)(gp) # 4 bytes
17789 d/addiu at, %lo(label) # 4 bytes
17790 jr/c at # 2/4 bytes
17793 length += 4 + short_insn_size;
17795 /* Add an extra nop if the jump has no compact form and we need
17796 to fill the delay slot. */
17797 if ((!pic || al) && nods)
17799 ? frag_branch_delay_slot_size (fragp, al, short_insn_size)
17800 : short_insn_size);
17802 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17804 <brneg> 0f # 4 bytes
17805 nop # 2/4 bytes if !compact
17808 length += (compact_known && compact) ? 4 : 4 + short_insn_size;
17812 /* Add an extra nop to fill the delay slot. */
17813 gas_assert (fragp);
17814 length += frag_branch_delay_slot_size (fragp, al, short_insn_size);
17820 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17821 bit accordingly. */
17824 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
17826 bfd_boolean toofar;
17829 && S_IS_DEFINED (fragp->fr_symbol)
17830 && !S_IS_WEAK (fragp->fr_symbol)
17831 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17837 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17838 /* Ignore the low bit in the target, since it will be set
17839 for a text label. */
17840 if ((val & 1) != 0)
17843 /* Assume this is a 2-byte branch. */
17844 addr = fragp->fr_address + fragp->fr_fix + 2;
17846 /* We try to avoid the infinite loop by not adding 2 more bytes for
17851 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17853 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
17854 else if (type == 'E')
17855 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
17860 /* If the symbol is not defined or it's in a different segment,
17861 we emit a normal 32-bit branch. */
17864 if (fragp && update
17865 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17867 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
17868 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
17876 /* Estimate the size of a frag before relaxing. Unless this is the
17877 mips16, we are not really relaxing here, and the final size is
17878 encoded in the subtype information. For the mips16, we have to
17879 decide whether we are using an extended opcode or not. */
17882 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
17886 if (RELAX_BRANCH_P (fragp->fr_subtype))
17889 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
17891 return fragp->fr_var;
17894 if (RELAX_MIPS16_P (fragp->fr_subtype))
17896 /* We don't want to modify the EXTENDED bit here; it might get us
17897 into infinite loops. We change it only in mips_relax_frag(). */
17898 if (RELAX_MIPS16_MACRO (fragp->fr_subtype))
17899 return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 8 : 12;
17901 return RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2;
17904 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17908 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17909 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
17910 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17911 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
17912 fragp->fr_var = length;
17917 if (mips_pic == VXWORKS_PIC)
17918 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17920 else if (RELAX_PIC (fragp->fr_subtype))
17921 change = pic_need_relax (fragp->fr_symbol);
17923 change = nopic_need_relax (fragp->fr_symbol, 0);
17927 fragp->fr_subtype |= RELAX_USE_SECOND;
17928 return -RELAX_FIRST (fragp->fr_subtype);
17931 return -RELAX_SECOND (fragp->fr_subtype);
17934 /* This is called to see whether a reloc against a defined symbol
17935 should be converted into a reloc against a section. */
17938 mips_fix_adjustable (fixS *fixp)
17940 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
17941 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17944 if (fixp->fx_addsy == NULL)
17947 /* Allow relocs used for EH tables. */
17948 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
17951 /* If symbol SYM is in a mergeable section, relocations of the form
17952 SYM + 0 can usually be made section-relative. The mergeable data
17953 is then identified by the section offset rather than by the symbol.
17955 However, if we're generating REL LO16 relocations, the offset is split
17956 between the LO16 and partnering high part relocation. The linker will
17957 need to recalculate the complete offset in order to correctly identify
17960 The linker has traditionally not looked for the partnering high part
17961 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17962 placed anywhere. Rather than break backwards compatibility by changing
17963 this, it seems better not to force the issue, and instead keep the
17964 original symbol. This will work with either linker behavior. */
17965 if ((lo16_reloc_p (fixp->fx_r_type)
17966 || reloc_needs_lo_p (fixp->fx_r_type))
17967 && HAVE_IN_PLACE_ADDENDS
17968 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
17971 /* There is no place to store an in-place offset for JALR relocations. */
17972 if (jalr_reloc_p (fixp->fx_r_type) && HAVE_IN_PLACE_ADDENDS)
17975 /* Likewise an in-range offset of limited PC-relative relocations may
17976 overflow the in-place relocatable field if recalculated against the
17977 start address of the symbol's containing section.
17979 Also, PC relative relocations for MIPS R6 need to be symbol rather than
17980 section relative to allow linker relaxations to be performed later on. */
17981 if (limited_pcrel_reloc_p (fixp->fx_r_type)
17982 && (HAVE_IN_PLACE_ADDENDS || ISA_IS_R6 (file_mips_opts.isa)))
17985 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17986 to a floating-point stub. The same is true for non-R_MIPS16_26
17987 relocations against MIPS16 functions; in this case, the stub becomes
17988 the function's canonical address.
17990 Floating-point stubs are stored in unique .mips16.call.* or
17991 .mips16.fn.* sections. If a stub T for function F is in section S,
17992 the first relocation in section S must be against F; this is how the
17993 linker determines the target function. All relocations that might
17994 resolve to T must also be against F. We therefore have the following
17995 restrictions, which are given in an intentionally-redundant way:
17997 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
18000 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
18001 if that stub might be used.
18003 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
18006 4. We cannot reduce a stub's relocations against MIPS16 symbols if
18007 that stub might be used.
18009 There is a further restriction:
18011 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
18012 R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2,
18013 R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1,
18014 R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1)
18015 against MIPS16 or microMIPS symbols because we need to keep the
18016 MIPS16 or microMIPS symbol for the purpose of mode mismatch
18017 detection and JAL or BAL to JALX instruction conversion in the
18020 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
18021 against a MIPS16 symbol. We deal with (5) by additionally leaving
18022 alone any jump and branch relocations against a microMIPS symbol.
18024 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
18025 relocation against some symbol R, no relocation against R may be
18026 reduced. (Note that this deals with (2) as well as (1) because
18027 relocations against global symbols will never be reduced on ELF
18028 targets.) This approach is a little simpler than trying to detect
18029 stub sections, and gives the "all or nothing" per-symbol consistency
18030 that we have for MIPS16 symbols. */
18031 if (fixp->fx_subsy == NULL
18032 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
18033 || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
18034 && (jmp_reloc_p (fixp->fx_r_type)
18035 || b_reloc_p (fixp->fx_r_type)))
18036 || *symbol_get_tc (fixp->fx_addsy)))
18042 /* Translate internal representation of relocation info to BFD target
18046 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
18048 static arelent *retval[4];
18050 bfd_reloc_code_real_type code;
18052 memset (retval, 0, sizeof(retval));
18053 reloc = retval[0] = XCNEW (arelent);
18054 reloc->sym_ptr_ptr = XNEW (asymbol *);
18055 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
18056 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
18058 if (fixp->fx_pcrel)
18060 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
18061 || fixp->fx_r_type == BFD_RELOC_MIPS16_16_PCREL_S1
18062 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
18063 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
18064 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
18065 || fixp->fx_r_type == BFD_RELOC_32_PCREL
18066 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
18067 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2
18068 || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3
18069 || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2
18070 || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL
18071 || fixp->fx_r_type == BFD_RELOC_LO16_PCREL);
18073 /* At this point, fx_addnumber is "symbol offset - pcrel address".
18074 Relocations want only the symbol offset. */
18075 switch (fixp->fx_r_type)
18077 case BFD_RELOC_MIPS_18_PCREL_S3:
18078 reloc->addend = fixp->fx_addnumber + (reloc->address & ~7);
18081 reloc->addend = fixp->fx_addnumber + reloc->address;
18085 else if (HAVE_IN_PLACE_ADDENDS
18086 && fixp->fx_r_type == BFD_RELOC_MICROMIPS_JMP
18087 && (read_compressed_insn (fixp->fx_frag->fr_literal
18088 + fixp->fx_where, 4) >> 26) == 0x3c)
18090 /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place
18091 addend accordingly. */
18092 reloc->addend = fixp->fx_addnumber >> 1;
18095 reloc->addend = fixp->fx_addnumber;
18097 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
18098 entry to be used in the relocation's section offset. */
18099 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
18101 reloc->address = reloc->addend;
18105 code = fixp->fx_r_type;
18107 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
18108 if (reloc->howto == NULL)
18110 as_bad_where (fixp->fx_file, fixp->fx_line,
18111 _("cannot represent %s relocation in this object file"
18113 bfd_get_reloc_code_name (code));
18120 /* Relax a machine dependent frag. This returns the amount by which
18121 the current size of the frag should change. */
18124 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
18126 if (RELAX_BRANCH_P (fragp->fr_subtype))
18128 offsetT old_var = fragp->fr_var;
18130 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
18132 return fragp->fr_var - old_var;
18135 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
18137 offsetT old_var = fragp->fr_var;
18138 offsetT new_var = 4;
18140 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
18141 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
18142 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
18143 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
18144 fragp->fr_var = new_var;
18146 return new_var - old_var;
18149 if (! RELAX_MIPS16_P (fragp->fr_subtype))
18152 if (!mips16_extended_frag (fragp, sec, stretch))
18154 if (RELAX_MIPS16_MACRO (fragp->fr_subtype))
18156 fragp->fr_subtype = RELAX_MIPS16_CLEAR_MACRO (fragp->fr_subtype);
18157 return RELAX_MIPS16_E2 (fragp->fr_subtype) ? -6 : -10;
18159 else if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18161 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
18167 else if (!mips16_macro_frag (fragp, sec, stretch))
18169 if (RELAX_MIPS16_MACRO (fragp->fr_subtype))
18171 fragp->fr_subtype = RELAX_MIPS16_CLEAR_MACRO (fragp->fr_subtype);
18172 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
18173 return RELAX_MIPS16_E2 (fragp->fr_subtype) ? -4 : -8;
18175 else if (!RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18177 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
18185 if (RELAX_MIPS16_MACRO (fragp->fr_subtype))
18187 else if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18189 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
18190 fragp->fr_subtype = RELAX_MIPS16_MARK_MACRO (fragp->fr_subtype);
18191 return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 4 : 8;
18195 fragp->fr_subtype = RELAX_MIPS16_MARK_MACRO (fragp->fr_subtype);
18196 return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 6 : 10;
18203 /* Convert a machine dependent frag. */
18206 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
18208 if (RELAX_BRANCH_P (fragp->fr_subtype))
18211 unsigned long insn;
18214 buf = fragp->fr_literal + fragp->fr_fix;
18215 insn = read_insn (buf);
18217 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
18219 /* We generate a fixup instead of applying it right now
18220 because, if there are linker relaxations, we're going to
18221 need the relocations. */
18222 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18223 fragp->fr_symbol, fragp->fr_offset,
18224 TRUE, BFD_RELOC_16_PCREL_S2);
18225 fixp->fx_file = fragp->fr_file;
18226 fixp->fx_line = fragp->fr_line;
18228 buf = write_insn (buf, insn);
18234 as_warn_where (fragp->fr_file, fragp->fr_line,
18235 _("relaxed out-of-range branch into a jump"));
18237 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
18240 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18242 /* Reverse the branch. */
18243 switch ((insn >> 28) & 0xf)
18246 if ((insn & 0xff000000) == 0x47000000
18247 || (insn & 0xff600000) == 0x45600000)
18249 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
18250 reversed by tweaking bit 23. */
18251 insn ^= 0x00800000;
18255 /* bc[0-3][tf]l? instructions can have the condition
18256 reversed by tweaking a single TF bit, and their
18257 opcodes all have 0x4???????. */
18258 gas_assert ((insn & 0xf3e00000) == 0x41000000);
18259 insn ^= 0x00010000;
18264 /* bltz 0x04000000 bgez 0x04010000
18265 bltzal 0x04100000 bgezal 0x04110000 */
18266 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
18267 insn ^= 0x00010000;
18271 /* beq 0x10000000 bne 0x14000000
18272 blez 0x18000000 bgtz 0x1c000000 */
18273 insn ^= 0x04000000;
18281 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
18283 /* Clear the and-link bit. */
18284 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
18286 /* bltzal 0x04100000 bgezal 0x04110000
18287 bltzall 0x04120000 bgezall 0x04130000 */
18288 insn &= ~0x00100000;
18291 /* Branch over the branch (if the branch was likely) or the
18292 full jump (not likely case). Compute the offset from the
18293 current instruction to branch to. */
18294 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18298 /* How many bytes in instructions we've already emitted? */
18299 i = buf - fragp->fr_literal - fragp->fr_fix;
18300 /* How many bytes in instructions from here to the end? */
18301 i = fragp->fr_var - i;
18303 /* Convert to instruction count. */
18305 /* Branch counts from the next instruction. */
18308 /* Branch over the jump. */
18309 buf = write_insn (buf, insn);
18312 buf = write_insn (buf, 0);
18314 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18316 /* beql $0, $0, 2f */
18318 /* Compute the PC offset from the current instruction to
18319 the end of the variable frag. */
18320 /* How many bytes in instructions we've already emitted? */
18321 i = buf - fragp->fr_literal - fragp->fr_fix;
18322 /* How many bytes in instructions from here to the end? */
18323 i = fragp->fr_var - i;
18324 /* Convert to instruction count. */
18326 /* Don't decrement i, because we want to branch over the
18330 buf = write_insn (buf, insn);
18331 buf = write_insn (buf, 0);
18335 if (!RELAX_BRANCH_PIC (fragp->fr_subtype))
18338 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
18339 ? 0x0c000000 : 0x08000000);
18341 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18342 fragp->fr_symbol, fragp->fr_offset,
18343 FALSE, BFD_RELOC_MIPS_JMP);
18344 fixp->fx_file = fragp->fr_file;
18345 fixp->fx_line = fragp->fr_line;
18347 buf = write_insn (buf, insn);
18351 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
18353 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18354 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
18355 insn |= at << OP_SH_RT;
18357 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18358 fragp->fr_symbol, fragp->fr_offset,
18359 FALSE, BFD_RELOC_MIPS_GOT16);
18360 fixp->fx_file = fragp->fr_file;
18361 fixp->fx_line = fragp->fr_line;
18363 buf = write_insn (buf, insn);
18365 if (mips_opts.isa == ISA_MIPS1)
18367 buf = write_insn (buf, 0);
18369 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18370 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
18371 insn |= at << OP_SH_RS | at << OP_SH_RT;
18373 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18374 fragp->fr_symbol, fragp->fr_offset,
18375 FALSE, BFD_RELOC_LO16);
18376 fixp->fx_file = fragp->fr_file;
18377 fixp->fx_line = fragp->fr_line;
18379 buf = write_insn (buf, insn);
18382 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
18386 insn |= at << OP_SH_RS;
18388 buf = write_insn (buf, insn);
18392 fragp->fr_fix += fragp->fr_var;
18393 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18397 /* Relax microMIPS branches. */
18398 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
18400 char *buf = fragp->fr_literal + fragp->fr_fix;
18401 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
18402 bfd_boolean insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype);
18403 bfd_boolean nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype);
18404 bfd_boolean pic = RELAX_MICROMIPS_PIC (fragp->fr_subtype);
18405 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
18406 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
18407 bfd_boolean short_ds;
18408 unsigned long insn;
18411 fragp->fr_fix += fragp->fr_var;
18413 /* Handle 16-bit branches that fit or are forced to fit. */
18414 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
18416 /* We generate a fixup instead of applying it right now,
18417 because if there is linker relaxation, we're going to
18418 need the relocations. */
18422 fixp = fix_new (fragp, buf - fragp->fr_literal, 2,
18423 fragp->fr_symbol, fragp->fr_offset,
18424 TRUE, BFD_RELOC_MICROMIPS_10_PCREL_S1);
18427 fixp = fix_new (fragp, buf - fragp->fr_literal, 2,
18428 fragp->fr_symbol, fragp->fr_offset,
18429 TRUE, BFD_RELOC_MICROMIPS_7_PCREL_S1);
18435 fixp->fx_file = fragp->fr_file;
18436 fixp->fx_line = fragp->fr_line;
18438 /* These relocations can have an addend that won't fit in
18440 fixp->fx_no_overflow = 1;
18445 /* Handle 32-bit branches that fit or are forced to fit. */
18446 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18447 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18449 /* We generate a fixup instead of applying it right now,
18450 because if there is linker relaxation, we're going to
18451 need the relocations. */
18452 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18453 fragp->fr_symbol, fragp->fr_offset,
18454 TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1);
18455 fixp->fx_file = fragp->fr_file;
18456 fixp->fx_line = fragp->fr_line;
18460 insn = read_compressed_insn (buf, 4);
18465 /* Check the short-delay-slot bit. */
18466 if (!al || (insn & 0x02000000) != 0)
18467 buf = write_compressed_insn (buf, 0x0c00, 2);
18469 buf = write_compressed_insn (buf, 0x00000000, 4);
18472 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18477 /* Relax 16-bit branches to 32-bit branches. */
18480 insn = read_compressed_insn (buf, 2);
18482 if ((insn & 0xfc00) == 0xcc00) /* b16 */
18483 insn = 0x94000000; /* beq */
18484 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18486 unsigned long regno;
18488 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
18489 regno = micromips_to_32_reg_d_map [regno];
18490 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
18491 insn |= regno << MICROMIPSOP_SH_RS;
18496 /* Nothing else to do, just write it out. */
18497 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18498 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18500 buf = write_compressed_insn (buf, insn, 4);
18502 buf = write_compressed_insn (buf, 0x0c00, 2);
18503 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18508 insn = read_compressed_insn (buf, 4);
18510 /* Relax 32-bit branches to a sequence of instructions. */
18511 as_warn_where (fragp->fr_file, fragp->fr_line,
18512 _("relaxed out-of-range branch into a jump"));
18514 /* Set the short-delay-slot bit. */
18515 short_ds = !al || (insn & 0x02000000) != 0;
18517 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
18521 /* Reverse the branch. */
18522 if ((insn & 0xfc000000) == 0x94000000 /* beq */
18523 || (insn & 0xfc000000) == 0xb4000000) /* bne */
18524 insn ^= 0x20000000;
18525 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
18526 || (insn & 0xffe00000) == 0x40400000 /* bgez */
18527 || (insn & 0xffe00000) == 0x40800000 /* blez */
18528 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
18529 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
18530 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
18531 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
18532 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
18533 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
18534 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
18535 insn ^= 0x00400000;
18536 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
18537 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
18538 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
18539 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
18540 insn ^= 0x00200000;
18541 else if ((insn & 0xff000000) == 0x83000000 /* BZ.df
18543 || (insn & 0xff600000) == 0x81600000) /* BZ.V
18545 insn ^= 0x00800000;
18551 /* Clear the and-link and short-delay-slot bits. */
18552 gas_assert ((insn & 0xfda00000) == 0x40200000);
18554 /* bltzal 0x40200000 bgezal 0x40600000 */
18555 /* bltzals 0x42200000 bgezals 0x42600000 */
18556 insn &= ~0x02200000;
18559 /* Make a label at the end for use with the branch. */
18560 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
18561 micromips_label_inc ();
18562 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
18565 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE,
18566 BFD_RELOC_MICROMIPS_16_PCREL_S1);
18567 fixp->fx_file = fragp->fr_file;
18568 fixp->fx_line = fragp->fr_line;
18570 /* Branch over the jump. */
18571 buf = write_compressed_insn (buf, insn, 4);
18577 buf = write_compressed_insn (buf, 0x00000000, 4);
18579 buf = write_compressed_insn (buf, 0x0c00, 2);
18585 unsigned long jal = (short_ds || nods
18586 ? 0x74000000 : 0xf4000000); /* jal/s */
18588 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18589 insn = al ? jal : 0xd4000000;
18591 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18592 fragp->fr_symbol, fragp->fr_offset,
18593 FALSE, BFD_RELOC_MICROMIPS_JMP);
18594 fixp->fx_file = fragp->fr_file;
18595 fixp->fx_line = fragp->fr_line;
18597 buf = write_compressed_insn (buf, insn, 4);
18599 if (compact || nods)
18603 buf = write_compressed_insn (buf, 0x00000000, 4);
18605 buf = write_compressed_insn (buf, 0x0c00, 2);
18610 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
18612 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18613 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
18614 insn |= at << MICROMIPSOP_SH_RT;
18616 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18617 fragp->fr_symbol, fragp->fr_offset,
18618 FALSE, BFD_RELOC_MICROMIPS_GOT16);
18619 fixp->fx_file = fragp->fr_file;
18620 fixp->fx_line = fragp->fr_line;
18622 buf = write_compressed_insn (buf, insn, 4);
18624 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18625 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
18626 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
18628 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18629 fragp->fr_symbol, fragp->fr_offset,
18630 FALSE, BFD_RELOC_MICROMIPS_LO16);
18631 fixp->fx_file = fragp->fr_file;
18632 fixp->fx_line = fragp->fr_line;
18634 buf = write_compressed_insn (buf, insn, 4);
18639 insn = 0x00000f3c | (al ? RA : ZERO) << MICROMIPSOP_SH_RT;
18640 insn |= at << MICROMIPSOP_SH_RS;
18642 buf = write_compressed_insn (buf, insn, 4);
18644 if (compact || nods)
18646 buf = write_compressed_insn (buf, 0x00000000, 4);
18650 /* jr/jrc/jalr/jalrs $at */
18651 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
18652 unsigned long jr = compact || nods ? 0x45a0 : 0x4580; /* jr/c */
18654 insn = al ? jalr : jr;
18655 insn |= at << MICROMIPSOP_SH_MJ;
18657 buf = write_compressed_insn (buf, insn, 2);
18662 buf = write_compressed_insn (buf, 0x0c00, 2);
18664 buf = write_compressed_insn (buf, 0x00000000, 4);
18669 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18673 if (RELAX_MIPS16_P (fragp->fr_subtype))
18676 const struct mips_int_operand *operand;
18679 unsigned int user_length;
18680 bfd_boolean need_reloc;
18681 unsigned long insn;
18686 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
18687 operand = mips16_immed_operand (type, FALSE);
18689 mac = RELAX_MIPS16_MACRO (fragp->fr_subtype);
18690 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
18691 val = resolve_symbol_value (fragp->fr_symbol) + fragp->fr_offset;
18693 symsec = S_GET_SEGMENT (fragp->fr_symbol);
18694 need_reloc = (S_FORCE_RELOC (fragp->fr_symbol, TRUE)
18695 || (operand->root.type == OP_PCREL && !mac
18697 : !bfd_is_abs_section (symsec)));
18699 if (operand->root.type == OP_PCREL && !mac)
18701 const struct mips_pcrel_operand *pcrel_op;
18703 pcrel_op = (const struct mips_pcrel_operand *) operand;
18705 if (pcrel_op->include_isa_bit && !need_reloc)
18707 if (!mips_ignore_branch_isa
18708 && !ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp->fr_symbol)))
18709 as_bad_where (fragp->fr_file, fragp->fr_line,
18710 _("branch to a symbol in another ISA mode"));
18711 else if ((fragp->fr_offset & 0x1) != 0)
18712 as_bad_where (fragp->fr_file, fragp->fr_line,
18713 _("branch to misaligned address (0x%lx)"),
18717 val = mips16_pcrel_val (fragp, pcrel_op, val, 0);
18719 /* Make sure the section winds up with the alignment we have
18721 if (operand->shift > 0)
18722 record_alignment (asec, operand->shift);
18725 if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
18726 || RELAX_MIPS16_DSLOT (fragp->fr_subtype))
18729 as_warn_where (fragp->fr_file, fragp->fr_line,
18730 _("macro instruction expanded into multiple "
18731 "instructions in a branch delay slot"));
18733 as_warn_where (fragp->fr_file, fragp->fr_line,
18734 _("extended instruction in a branch delay slot"));
18736 else if (RELAX_MIPS16_NOMACRO (fragp->fr_subtype) && mac)
18737 as_warn_where (fragp->fr_file, fragp->fr_line,
18738 _("macro instruction expanded into multiple "
18741 buf = fragp->fr_literal + fragp->fr_fix;
18743 insn = read_compressed_insn (buf, 2);
18745 insn |= MIPS16_EXTEND;
18747 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
18749 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
18761 gas_assert (type == 'A' || type == 'B' || type == 'E');
18762 gas_assert (RELAX_MIPS16_SYM32 (fragp->fr_subtype));
18764 e2 = RELAX_MIPS16_E2 (fragp->fr_subtype);
18770 gas_assert (!RELAX_MIPS16_PIC (fragp->fr_subtype));
18772 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18773 fragp->fr_symbol, fragp->fr_offset,
18774 FALSE, BFD_RELOC_MIPS16_HI16_S);
18775 fixp->fx_file = fragp->fr_file;
18776 fixp->fx_line = fragp->fr_line;
18778 fixp = fix_new (fragp, buf - fragp->fr_literal + (e2 ? 4 : 8), 4,
18779 fragp->fr_symbol, fragp->fr_offset,
18780 FALSE, BFD_RELOC_MIPS16_LO16);
18781 fixp->fx_file = fragp->fr_file;
18782 fixp->fx_line = fragp->fr_line;
18787 switch (insn & 0xf800)
18789 case 0x0800: /* ADDIU */
18790 reg = (insn >> 8) & 0x7;
18791 op = 0xf0004800 | (reg << 8);
18793 case 0xb000: /* LW */
18794 reg = (insn >> 8) & 0x7;
18795 op = 0xf0009800 | (reg << 8) | (reg << 5);
18797 case 0xf800: /* I64 */
18798 reg = (insn >> 5) & 0x7;
18799 switch (insn & 0x0700)
18801 case 0x0400: /* LD */
18802 op = 0xf0003800 | (reg << 8) | (reg << 5);
18804 case 0x0600: /* DADDIU */
18805 op = 0xf000fd00 | (reg << 5);
18815 new = (e2 ? 0xf0006820 : 0xf0006800) | (reg << 8); /* LUI/LI */
18816 new |= mips16_immed_extend ((val + 0x8000) >> 16, 16);
18817 buf = write_compressed_insn (buf, new, 4);
18820 new = 0xf4003000 | (reg << 8) | (reg << 5); /* SLL */
18821 buf = write_compressed_insn (buf, new, 4);
18823 op |= mips16_immed_extend (val, 16);
18824 buf = write_compressed_insn (buf, op, 4);
18826 fragp->fr_fix += e2 ? 8 : 12;
18830 unsigned int length = ext ? 4 : 2;
18834 bfd_reloc_code_real_type reloc = BFD_RELOC_NONE;
18841 reloc = BFD_RELOC_MIPS16_16_PCREL_S1;
18846 if (mac || reloc == BFD_RELOC_NONE)
18847 as_bad_where (fragp->fr_file, fragp->fr_line,
18848 _("unsupported relocation"));
18851 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18852 fragp->fr_symbol, fragp->fr_offset,
18854 fixp->fx_file = fragp->fr_file;
18855 fixp->fx_line = fragp->fr_line;
18858 as_bad_where (fragp->fr_file, fragp->fr_line,
18859 _("invalid unextended operand value"));
18862 mips16_immed (fragp->fr_file, fragp->fr_line, type,
18863 BFD_RELOC_UNUSED, val, user_length, &insn);
18865 gas_assert (mips16_opcode_length (insn) == length);
18866 write_compressed_insn (buf, insn, length);
18867 fragp->fr_fix += length;
18872 relax_substateT subtype = fragp->fr_subtype;
18873 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
18874 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
18878 first = RELAX_FIRST (subtype);
18879 second = RELAX_SECOND (subtype);
18880 fixp = (fixS *) fragp->fr_opcode;
18882 /* If the delay slot chosen does not match the size of the instruction,
18883 then emit a warning. */
18884 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
18885 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
18890 s = subtype & (RELAX_DELAY_SLOT_16BIT
18891 | RELAX_DELAY_SLOT_SIZE_FIRST
18892 | RELAX_DELAY_SLOT_SIZE_SECOND);
18893 msg = macro_warning (s);
18895 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18899 /* Possibly emit a warning if we've chosen the longer option. */
18900 if (use_second == second_longer)
18906 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
18907 msg = macro_warning (s);
18909 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18913 /* Go through all the fixups for the first sequence. Disable them
18914 (by marking them as done) if we're going to use the second
18915 sequence instead. */
18917 && fixp->fx_frag == fragp
18918 && fixp->fx_where < fragp->fr_fix - second)
18920 if (subtype & RELAX_USE_SECOND)
18922 fixp = fixp->fx_next;
18925 /* Go through the fixups for the second sequence. Disable them if
18926 we're going to use the first sequence, otherwise adjust their
18927 addresses to account for the relaxation. */
18928 while (fixp && fixp->fx_frag == fragp)
18930 if (subtype & RELAX_USE_SECOND)
18931 fixp->fx_where -= first;
18934 fixp = fixp->fx_next;
18937 /* Now modify the frag contents. */
18938 if (subtype & RELAX_USE_SECOND)
18942 start = fragp->fr_literal + fragp->fr_fix - first - second;
18943 memmove (start, start + first, second);
18944 fragp->fr_fix -= first;
18947 fragp->fr_fix -= second;
18951 /* This function is called after the relocs have been generated.
18952 We've been storing mips16 text labels as odd. Here we convert them
18953 back to even for the convenience of the debugger. */
18956 mips_frob_file_after_relocs (void)
18959 unsigned int count, i;
18961 syms = bfd_get_outsymbols (stdoutput);
18962 count = bfd_get_symcount (stdoutput);
18963 for (i = 0; i < count; i++, syms++)
18964 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
18965 && ((*syms)->value & 1) != 0)
18967 (*syms)->value &= ~1;
18968 /* If the symbol has an odd size, it was probably computed
18969 incorrectly, so adjust that as well. */
18970 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
18971 ++elf_symbol (*syms)->internal_elf_sym.st_size;
18975 /* This function is called whenever a label is defined, including fake
18976 labels instantiated off the dot special symbol. It is used when
18977 handling branch delays; if a branch has a label, we assume we cannot
18978 move it. This also bumps the value of the symbol by 1 in compressed
18982 mips_record_label (symbolS *sym)
18984 segment_info_type *si = seg_info (now_seg);
18985 struct insn_label_list *l;
18987 if (free_insn_labels == NULL)
18988 l = XNEW (struct insn_label_list);
18991 l = free_insn_labels;
18992 free_insn_labels = l->next;
18996 l->next = si->label_list;
18997 si->label_list = l;
19000 /* This function is called as tc_frob_label() whenever a label is defined
19001 and adds a DWARF-2 record we only want for true labels. */
19004 mips_define_label (symbolS *sym)
19006 mips_record_label (sym);
19007 dwarf2_emit_label (sym);
19010 /* This function is called by tc_new_dot_label whenever a new dot symbol
19014 mips_add_dot_label (symbolS *sym)
19016 mips_record_label (sym);
19017 if (mips_assembling_insn && HAVE_CODE_COMPRESSION)
19018 mips_compressed_mark_label (sym);
19021 /* Converting ASE flags from internal to .MIPS.abiflags values. */
19022 static unsigned int
19023 mips_convert_ase_flags (int ase)
19025 unsigned int ext_ases = 0;
19028 ext_ases |= AFL_ASE_DSP;
19029 if (ase & ASE_DSPR2)
19030 ext_ases |= AFL_ASE_DSPR2;
19031 if (ase & ASE_DSPR3)
19032 ext_ases |= AFL_ASE_DSPR3;
19034 ext_ases |= AFL_ASE_EVA;
19036 ext_ases |= AFL_ASE_MCU;
19037 if (ase & ASE_MDMX)
19038 ext_ases |= AFL_ASE_MDMX;
19039 if (ase & ASE_MIPS3D)
19040 ext_ases |= AFL_ASE_MIPS3D;
19042 ext_ases |= AFL_ASE_MT;
19043 if (ase & ASE_SMARTMIPS)
19044 ext_ases |= AFL_ASE_SMARTMIPS;
19045 if (ase & ASE_VIRT)
19046 ext_ases |= AFL_ASE_VIRT;
19048 ext_ases |= AFL_ASE_MSA;
19050 ext_ases |= AFL_ASE_XPA;
19051 if (ase & ASE_MIPS16E2)
19052 ext_ases |= file_ase_mips16 ? AFL_ASE_MIPS16E2 : 0;
19054 ext_ases |= AFL_ASE_CRC;
19055 if (ase & ASE_GINV)
19056 ext_ases |= AFL_ASE_GINV;
19057 if (ase & ASE_LOONGSON_MMI)
19058 ext_ases |= AFL_ASE_LOONGSON_MMI;
19059 if (ase & ASE_LOONGSON_CAM)
19060 ext_ases |= AFL_ASE_LOONGSON_CAM;
19061 if (ase & ASE_LOONGSON_EXT)
19062 ext_ases |= AFL_ASE_LOONGSON_EXT;
19063 if (ase & ASE_LOONGSON_EXT2)
19064 ext_ases |= AFL_ASE_LOONGSON_EXT2;
19068 /* Some special processing for a MIPS ELF file. */
19071 mips_elf_final_processing (void)
19074 Elf_Internal_ABIFlags_v0 flags;
19078 switch (file_mips_opts.isa)
19081 flags.isa_level = 1;
19084 flags.isa_level = 2;
19087 flags.isa_level = 3;
19090 flags.isa_level = 4;
19093 flags.isa_level = 5;
19096 flags.isa_level = 32;
19100 flags.isa_level = 32;
19104 flags.isa_level = 32;
19108 flags.isa_level = 32;
19112 flags.isa_level = 32;
19116 flags.isa_level = 64;
19120 flags.isa_level = 64;
19124 flags.isa_level = 64;
19128 flags.isa_level = 64;
19132 flags.isa_level = 64;
19137 flags.gpr_size = file_mips_opts.gp == 32 ? AFL_REG_32 : AFL_REG_64;
19138 flags.cpr1_size = file_mips_opts.soft_float ? AFL_REG_NONE
19139 : (file_mips_opts.ase & ASE_MSA) ? AFL_REG_128
19140 : (file_mips_opts.fp == 64) ? AFL_REG_64
19142 flags.cpr2_size = AFL_REG_NONE;
19143 flags.fp_abi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
19144 Tag_GNU_MIPS_ABI_FP);
19145 flags.isa_ext = bfd_mips_isa_ext (stdoutput);
19146 flags.ases = mips_convert_ase_flags (file_mips_opts.ase);
19147 if (file_ase_mips16)
19148 flags.ases |= AFL_ASE_MIPS16;
19149 if (file_ase_micromips)
19150 flags.ases |= AFL_ASE_MICROMIPS;
19152 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts.isa, file_mips_opts.arch)
19153 || file_mips_opts.fp == 64)
19154 && file_mips_opts.oddspreg)
19155 flags.flags1 |= AFL_FLAGS1_ODDSPREG;
19158 bfd_mips_elf_swap_abiflags_v0_out (stdoutput, &flags,
19159 ((Elf_External_ABIFlags_v0 *)
19162 /* Write out the register information. */
19163 if (mips_abi != N64_ABI)
19167 s.ri_gprmask = mips_gprmask;
19168 s.ri_cprmask[0] = mips_cprmask[0];
19169 s.ri_cprmask[1] = mips_cprmask[1];
19170 s.ri_cprmask[2] = mips_cprmask[2];
19171 s.ri_cprmask[3] = mips_cprmask[3];
19172 /* The gp_value field is set by the MIPS ELF backend. */
19174 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
19175 ((Elf32_External_RegInfo *)
19176 mips_regmask_frag));
19180 Elf64_Internal_RegInfo s;
19182 s.ri_gprmask = mips_gprmask;
19184 s.ri_cprmask[0] = mips_cprmask[0];
19185 s.ri_cprmask[1] = mips_cprmask[1];
19186 s.ri_cprmask[2] = mips_cprmask[2];
19187 s.ri_cprmask[3] = mips_cprmask[3];
19188 /* The gp_value field is set by the MIPS ELF backend. */
19190 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
19191 ((Elf64_External_RegInfo *)
19192 mips_regmask_frag));
19195 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
19196 sort of BFD interface for this. */
19197 if (mips_any_noreorder)
19198 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
19199 if (mips_pic != NO_PIC)
19201 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
19202 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
19205 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
19207 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
19208 defined at present; this might need to change in future. */
19209 if (file_ase_mips16)
19210 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
19211 if (file_ase_micromips)
19212 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
19213 if (file_mips_opts.ase & ASE_MDMX)
19214 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
19216 /* Set the MIPS ELF ABI flags. */
19217 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
19218 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
19219 else if (mips_abi == O64_ABI)
19220 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
19221 else if (mips_abi == EABI_ABI)
19223 if (file_mips_opts.gp == 64)
19224 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
19226 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
19229 /* Nothing to do for N32_ABI or N64_ABI. */
19231 if (mips_32bitmode)
19232 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
19234 if (mips_nan2008 == 1)
19235 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008;
19237 /* 32 bit code with 64 bit FP registers. */
19238 fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
19239 Tag_GNU_MIPS_ABI_FP);
19240 if (fpabi == Val_GNU_MIPS_ABI_FP_OLD_64)
19241 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_FP64;
19244 typedef struct proc {
19246 symbolS *func_end_sym;
19247 unsigned long reg_mask;
19248 unsigned long reg_offset;
19249 unsigned long fpreg_mask;
19250 unsigned long fpreg_offset;
19251 unsigned long frame_offset;
19252 unsigned long frame_reg;
19253 unsigned long pc_reg;
19256 static procS cur_proc;
19257 static procS *cur_proc_ptr;
19258 static int numprocs;
19260 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
19261 as "2", and a normal nop as "0". */
19263 #define NOP_OPCODE_MIPS 0
19264 #define NOP_OPCODE_MIPS16 1
19265 #define NOP_OPCODE_MICROMIPS 2
19268 mips_nop_opcode (void)
19270 if (seg_info (now_seg)->tc_segment_info_data.micromips)
19271 return NOP_OPCODE_MICROMIPS;
19272 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
19273 return NOP_OPCODE_MIPS16;
19275 return NOP_OPCODE_MIPS;
19278 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
19279 32-bit microMIPS NOPs here (if applicable). */
19282 mips_handle_align (fragS *fragp)
19286 int bytes, size, excess;
19289 if (fragp->fr_type != rs_align_code)
19292 p = fragp->fr_literal + fragp->fr_fix;
19294 switch (nop_opcode)
19296 case NOP_OPCODE_MICROMIPS:
19297 opcode = micromips_nop32_insn.insn_opcode;
19300 case NOP_OPCODE_MIPS16:
19301 opcode = mips16_nop_insn.insn_opcode;
19304 case NOP_OPCODE_MIPS:
19306 opcode = nop_insn.insn_opcode;
19311 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
19312 excess = bytes % size;
19314 /* Handle the leading part if we're not inserting a whole number of
19315 instructions, and make it the end of the fixed part of the frag.
19316 Try to fit in a short microMIPS NOP if applicable and possible,
19317 and use zeroes otherwise. */
19318 gas_assert (excess < 4);
19319 fragp->fr_fix += excess;
19324 /* Fall through. */
19326 if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32)
19328 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2);
19332 /* Fall through. */
19335 /* Fall through. */
19340 md_number_to_chars (p, opcode, size);
19341 fragp->fr_var = size;
19350 if (*input_line_pointer == '-')
19352 ++input_line_pointer;
19355 if (!ISDIGIT (*input_line_pointer))
19356 as_bad (_("expected simple number"));
19357 if (input_line_pointer[0] == '0')
19359 if (input_line_pointer[1] == 'x')
19361 input_line_pointer += 2;
19362 while (ISXDIGIT (*input_line_pointer))
19365 val |= hex_value (*input_line_pointer++);
19367 return negative ? -val : val;
19371 ++input_line_pointer;
19372 while (ISDIGIT (*input_line_pointer))
19375 val |= *input_line_pointer++ - '0';
19377 return negative ? -val : val;
19380 if (!ISDIGIT (*input_line_pointer))
19382 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
19383 *input_line_pointer, *input_line_pointer);
19384 as_warn (_("invalid number"));
19387 while (ISDIGIT (*input_line_pointer))
19390 val += *input_line_pointer++ - '0';
19392 return negative ? -val : val;
19395 /* The .file directive; just like the usual .file directive, but there
19396 is an initial number which is the ECOFF file index. In the non-ECOFF
19397 case .file implies DWARF-2. */
19400 s_mips_file (int x ATTRIBUTE_UNUSED)
19402 static int first_file_directive = 0;
19404 if (ECOFF_DEBUGGING)
19413 filename = dwarf2_directive_filename ();
19415 /* Versions of GCC up to 3.1 start files with a ".file"
19416 directive even for stabs output. Make sure that this
19417 ".file" is handled. Note that you need a version of GCC
19418 after 3.1 in order to support DWARF-2 on MIPS. */
19419 if (filename != NULL && ! first_file_directive)
19421 (void) new_logical_line (filename, -1);
19422 s_app_file_string (filename, 0);
19424 first_file_directive = 1;
19428 /* The .loc directive, implying DWARF-2. */
19431 s_mips_loc (int x ATTRIBUTE_UNUSED)
19433 if (!ECOFF_DEBUGGING)
19434 dwarf2_directive_loc (0);
19437 /* The .end directive. */
19440 s_mips_end (int x ATTRIBUTE_UNUSED)
19444 /* Following functions need their own .frame and .cprestore directives. */
19445 mips_frame_reg_valid = 0;
19446 mips_cprestore_valid = 0;
19448 if (!is_end_of_line[(unsigned char) *input_line_pointer])
19451 demand_empty_rest_of_line ();
19456 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
19457 as_warn (_(".end not in text section"));
19461 as_warn (_(".end directive without a preceding .ent directive"));
19462 demand_empty_rest_of_line ();
19468 gas_assert (S_GET_NAME (p));
19469 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
19470 as_warn (_(".end symbol does not match .ent symbol"));
19472 if (debug_type == DEBUG_STABS)
19473 stabs_generate_asm_endfunc (S_GET_NAME (p),
19477 as_warn (_(".end directive missing or unknown symbol"));
19479 /* Create an expression to calculate the size of the function. */
19480 if (p && cur_proc_ptr)
19482 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
19483 expressionS *exp = XNEW (expressionS);
19486 exp->X_op = O_subtract;
19487 exp->X_add_symbol = symbol_temp_new_now ();
19488 exp->X_op_symbol = p;
19489 exp->X_add_number = 0;
19491 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
19494 #ifdef md_flush_pending_output
19495 md_flush_pending_output ();
19498 /* Generate a .pdr section. */
19499 if (!ECOFF_DEBUGGING && mips_flag_pdr)
19501 segT saved_seg = now_seg;
19502 subsegT saved_subseg = now_subseg;
19506 gas_assert (pdr_seg);
19507 subseg_set (pdr_seg, 0);
19509 /* Write the symbol. */
19510 exp.X_op = O_symbol;
19511 exp.X_add_symbol = p;
19512 exp.X_add_number = 0;
19513 emit_expr (&exp, 4);
19515 fragp = frag_more (7 * 4);
19517 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
19518 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
19519 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
19520 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
19521 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
19522 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
19523 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
19525 subseg_set (saved_seg, saved_subseg);
19528 cur_proc_ptr = NULL;
19531 /* The .aent and .ent directives. */
19534 s_mips_ent (int aent)
19538 symbolP = get_symbol ();
19539 if (*input_line_pointer == ',')
19540 ++input_line_pointer;
19541 SKIP_WHITESPACE ();
19542 if (ISDIGIT (*input_line_pointer)
19543 || *input_line_pointer == '-')
19546 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
19547 as_warn (_(".ent or .aent not in text section"));
19549 if (!aent && cur_proc_ptr)
19550 as_warn (_("missing .end"));
19554 /* This function needs its own .frame and .cprestore directives. */
19555 mips_frame_reg_valid = 0;
19556 mips_cprestore_valid = 0;
19558 cur_proc_ptr = &cur_proc;
19559 memset (cur_proc_ptr, '\0', sizeof (procS));
19561 cur_proc_ptr->func_sym = symbolP;
19565 if (debug_type == DEBUG_STABS)
19566 stabs_generate_asm_func (S_GET_NAME (symbolP),
19567 S_GET_NAME (symbolP));
19570 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
19572 demand_empty_rest_of_line ();
19575 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19576 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19577 s_mips_frame is used so that we can set the PDR information correctly.
19578 We can't use the ecoff routines because they make reference to the ecoff
19579 symbol table (in the mdebug section). */
19582 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
19584 if (ECOFF_DEBUGGING)
19590 if (cur_proc_ptr == (procS *) NULL)
19592 as_warn (_(".frame outside of .ent"));
19593 demand_empty_rest_of_line ();
19597 cur_proc_ptr->frame_reg = tc_get_register (1);
19599 SKIP_WHITESPACE ();
19600 if (*input_line_pointer++ != ','
19601 || get_absolute_expression_and_terminator (&val) != ',')
19603 as_warn (_("bad .frame directive"));
19604 --input_line_pointer;
19605 demand_empty_rest_of_line ();
19609 cur_proc_ptr->frame_offset = val;
19610 cur_proc_ptr->pc_reg = tc_get_register (0);
19612 demand_empty_rest_of_line ();
19616 /* The .fmask and .mask directives. If the mdebug section is present
19617 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19618 embedded targets, s_mips_mask is used so that we can set the PDR
19619 information correctly. We can't use the ecoff routines because they
19620 make reference to the ecoff symbol table (in the mdebug section). */
19623 s_mips_mask (int reg_type)
19625 if (ECOFF_DEBUGGING)
19626 s_ignore (reg_type);
19631 if (cur_proc_ptr == (procS *) NULL)
19633 as_warn (_(".mask/.fmask outside of .ent"));
19634 demand_empty_rest_of_line ();
19638 if (get_absolute_expression_and_terminator (&mask) != ',')
19640 as_warn (_("bad .mask/.fmask directive"));
19641 --input_line_pointer;
19642 demand_empty_rest_of_line ();
19646 off = get_absolute_expression ();
19648 if (reg_type == 'F')
19650 cur_proc_ptr->fpreg_mask = mask;
19651 cur_proc_ptr->fpreg_offset = off;
19655 cur_proc_ptr->reg_mask = mask;
19656 cur_proc_ptr->reg_offset = off;
19659 demand_empty_rest_of_line ();
19663 /* A table describing all the processors gas knows about. Names are
19664 matched in the order listed.
19666 To ease comparison, please keep this table in the same order as
19667 gcc's mips_cpu_info_table[]. */
19668 static const struct mips_cpu_info mips_cpu_info_table[] =
19670 /* Entries for generic ISAs */
19671 { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 },
19672 { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 },
19673 { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 },
19674 { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 },
19675 { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 },
19676 { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 },
19677 { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19678 { "mips32r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R3, CPU_MIPS32R3 },
19679 { "mips32r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R5, CPU_MIPS32R5 },
19680 { "mips32r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R6, CPU_MIPS32R6 },
19681 { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 },
19682 { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 },
19683 { "mips64r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R3, CPU_MIPS64R3 },
19684 { "mips64r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R5, CPU_MIPS64R5 },
19685 { "mips64r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R6, CPU_MIPS64R6 },
19688 { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 },
19689 { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 },
19690 { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 },
19693 { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 },
19696 { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 },
19697 { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 },
19698 { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 },
19699 { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 },
19700 { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 },
19701 { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 },
19702 { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 },
19703 { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 },
19704 { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 },
19705 { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 },
19706 { "orion", 0, 0, ISA_MIPS3, CPU_R4600 },
19707 { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 },
19708 { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 },
19709 /* ST Microelectronics Loongson 2E and 2F cores */
19710 { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E },
19711 { "loongson2f", 0, ASE_LOONGSON_MMI, ISA_MIPS3, CPU_LOONGSON_2F },
19714 { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 },
19715 { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 },
19716 { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 },
19717 { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 },
19718 { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 },
19719 { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 },
19720 { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 },
19721 { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 },
19722 { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 },
19723 { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 },
19724 { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 },
19725 { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 },
19726 { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 },
19727 { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 },
19728 { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 },
19731 { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19732 { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19733 { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19734 { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
19736 /* MIPS 32 Release 2 */
19737 { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19738 { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19739 { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19740 { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
19741 { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19742 { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19743 { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19744 { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19745 { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
19746 ISA_MIPS32R2, CPU_MIPS32R2 },
19747 { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
19748 ISA_MIPS32R2, CPU_MIPS32R2 },
19749 { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19750 { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19751 { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19752 { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19753 /* Deprecated forms of the above. */
19754 { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19755 { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19756 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19757 { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19758 { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19759 { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19760 { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19761 /* Deprecated forms of the above. */
19762 { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19763 { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19764 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19765 { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19766 { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19767 { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19768 { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19769 /* Deprecated forms of the above. */
19770 { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19771 { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19772 /* 34Kn is a 34kc without DSP. */
19773 { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19774 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19775 { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19776 { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19777 { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19778 { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19779 { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19780 /* Deprecated forms of the above. */
19781 { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19782 { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19783 /* 1004K cores are multiprocessor versions of the 34K. */
19784 { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19785 { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19786 { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19787 { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19788 /* interaptiv is the new name for 1004kf */
19789 { "interaptiv", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19790 { "interaptiv-mr2", 0,
19791 ASE_DSP | ASE_EVA | ASE_MT | ASE_MIPS16E2 | ASE_MIPS16E2_MT,
19792 ISA_MIPS32R3, CPU_INTERAPTIV_MR2 },
19794 { "m5100", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 },
19795 { "m5101", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 },
19796 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
19797 { "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R5, CPU_MIPS32R5 },
19800 { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 },
19801 { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 },
19802 { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19803 { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19805 /* Broadcom SB-1 CPU core */
19806 { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
19807 /* Broadcom SB-1A CPU core */
19808 { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
19810 /* MIPS 64 Release 2 */
19811 /* Loongson CPU core */
19812 /* -march=loongson3a is an alias of -march=gs464 for compatibility */
19813 { "loongson3a", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT,
19814 ISA_MIPS64R2, CPU_GS464 },
19815 { "gs464", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT,
19816 ISA_MIPS64R2, CPU_GS464 },
19818 /* Cavium Networks Octeon CPU core */
19819 { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
19820 { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP },
19821 { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 },
19822 { "octeon3", 0, ASE_VIRT | ASE_VIRT64, ISA_MIPS64R5, CPU_OCTEON3 },
19825 { "xlr", 0, 0, ISA_MIPS64, CPU_XLR },
19828 XLP is mostly like XLR, with the prominent exception that it is
19829 MIPS64R2 rather than MIPS64. */
19830 { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
19832 /* MIPS 64 Release 6 */
19833 { "i6400", 0, ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6},
19834 { "p6600", 0, ASE_VIRT | ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6},
19837 { NULL, 0, 0, 0, 0 }
19841 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19842 with a final "000" replaced by "k". Ignore case.
19844 Note: this function is shared between GCC and GAS. */
19847 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
19849 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
19850 given++, canonical++;
19852 return ((*given == 0 && *canonical == 0)
19853 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
19857 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19858 CPU name. We've traditionally allowed a lot of variation here.
19860 Note: this function is shared between GCC and GAS. */
19863 mips_matching_cpu_name_p (const char *canonical, const char *given)
19865 /* First see if the name matches exactly, or with a final "000"
19866 turned into "k". */
19867 if (mips_strict_matching_cpu_name_p (canonical, given))
19870 /* If not, try comparing based on numerical designation alone.
19871 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19872 if (TOLOWER (*given) == 'r')
19874 if (!ISDIGIT (*given))
19877 /* Skip over some well-known prefixes in the canonical name,
19878 hoping to find a number there too. */
19879 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
19881 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
19883 else if (TOLOWER (canonical[0]) == 'r')
19886 return mips_strict_matching_cpu_name_p (canonical, given);
19890 /* Parse an option that takes the name of a processor as its argument.
19891 OPTION is the name of the option and CPU_STRING is the argument.
19892 Return the corresponding processor enumeration if the CPU_STRING is
19893 recognized, otherwise report an error and return null.
19895 A similar function exists in GCC. */
19897 static const struct mips_cpu_info *
19898 mips_parse_cpu (const char *option, const char *cpu_string)
19900 const struct mips_cpu_info *p;
19902 /* 'from-abi' selects the most compatible architecture for the given
19903 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19904 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19905 version. Look first at the -mgp options, if given, otherwise base
19906 the choice on MIPS_DEFAULT_64BIT.
19908 Treat NO_ABI like the EABIs. One reason to do this is that the
19909 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19910 architecture. This code picks MIPS I for 'mips' and MIPS III for
19911 'mips64', just as we did in the days before 'from-abi'. */
19912 if (strcasecmp (cpu_string, "from-abi") == 0)
19914 if (ABI_NEEDS_32BIT_REGS (mips_abi))
19915 return mips_cpu_info_from_isa (ISA_MIPS1);
19917 if (ABI_NEEDS_64BIT_REGS (mips_abi))
19918 return mips_cpu_info_from_isa (ISA_MIPS3);
19920 if (file_mips_opts.gp >= 0)
19921 return mips_cpu_info_from_isa (file_mips_opts.gp == 32
19922 ? ISA_MIPS1 : ISA_MIPS3);
19924 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19929 /* 'default' has traditionally been a no-op. Probably not very useful. */
19930 if (strcasecmp (cpu_string, "default") == 0)
19933 for (p = mips_cpu_info_table; p->name != 0; p++)
19934 if (mips_matching_cpu_name_p (p->name, cpu_string))
19937 as_bad (_("bad value (%s) for %s"), cpu_string, option);
19941 /* Return the canonical processor information for ISA (a member of the
19942 ISA_MIPS* enumeration). */
19944 static const struct mips_cpu_info *
19945 mips_cpu_info_from_isa (int isa)
19949 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19950 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
19951 && isa == mips_cpu_info_table[i].isa)
19952 return (&mips_cpu_info_table[i]);
19957 static const struct mips_cpu_info *
19958 mips_cpu_info_from_arch (int arch)
19962 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19963 if (arch == mips_cpu_info_table[i].cpu)
19964 return (&mips_cpu_info_table[i]);
19970 show (FILE *stream, const char *string, int *col_p, int *first_p)
19974 fprintf (stream, "%24s", "");
19979 fprintf (stream, ", ");
19983 if (*col_p + strlen (string) > 72)
19985 fprintf (stream, "\n%24s", "");
19989 fprintf (stream, "%s", string);
19990 *col_p += strlen (string);
19996 md_show_usage (FILE *stream)
20001 fprintf (stream, _("\
20003 -EB generate big endian output\n\
20004 -EL generate little endian output\n\
20005 -g, -g2 do not remove unneeded NOPs or swap branches\n\
20006 -G NUM allow referencing objects up to NUM bytes\n\
20007 implicitly with the gp register [default 8]\n"));
20008 fprintf (stream, _("\
20009 -mips1 generate MIPS ISA I instructions\n\
20010 -mips2 generate MIPS ISA II instructions\n\
20011 -mips3 generate MIPS ISA III instructions\n\
20012 -mips4 generate MIPS ISA IV instructions\n\
20013 -mips5 generate MIPS ISA V instructions\n\
20014 -mips32 generate MIPS32 ISA instructions\n\
20015 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
20016 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
20017 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
20018 -mips32r6 generate MIPS32 release 6 ISA instructions\n\
20019 -mips64 generate MIPS64 ISA instructions\n\
20020 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
20021 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
20022 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
20023 -mips64r6 generate MIPS64 release 6 ISA instructions\n\
20024 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
20028 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
20029 show (stream, mips_cpu_info_table[i].name, &column, &first);
20030 show (stream, "from-abi", &column, &first);
20031 fputc ('\n', stream);
20033 fprintf (stream, _("\
20034 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
20035 -no-mCPU don't generate code specific to CPU.\n\
20036 For -mCPU and -no-mCPU, CPU must be one of:\n"));
20040 show (stream, "3900", &column, &first);
20041 show (stream, "4010", &column, &first);
20042 show (stream, "4100", &column, &first);
20043 show (stream, "4650", &column, &first);
20044 fputc ('\n', stream);
20046 fprintf (stream, _("\
20047 -mips16 generate mips16 instructions\n\
20048 -no-mips16 do not generate mips16 instructions\n"));
20049 fprintf (stream, _("\
20050 -mmips16e2 generate MIPS16e2 instructions\n\
20051 -mno-mips16e2 do not generate MIPS16e2 instructions\n"));
20052 fprintf (stream, _("\
20053 -mmicromips generate microMIPS instructions\n\
20054 -mno-micromips do not generate microMIPS instructions\n"));
20055 fprintf (stream, _("\
20056 -msmartmips generate smartmips instructions\n\
20057 -mno-smartmips do not generate smartmips instructions\n"));
20058 fprintf (stream, _("\
20059 -mdsp generate DSP instructions\n\
20060 -mno-dsp do not generate DSP instructions\n"));
20061 fprintf (stream, _("\
20062 -mdspr2 generate DSP R2 instructions\n\
20063 -mno-dspr2 do not generate DSP R2 instructions\n"));
20064 fprintf (stream, _("\
20065 -mdspr3 generate DSP R3 instructions\n\
20066 -mno-dspr3 do not generate DSP R3 instructions\n"));
20067 fprintf (stream, _("\
20068 -mmt generate MT instructions\n\
20069 -mno-mt do not generate MT instructions\n"));
20070 fprintf (stream, _("\
20071 -mmcu generate MCU instructions\n\
20072 -mno-mcu do not generate MCU instructions\n"));
20073 fprintf (stream, _("\
20074 -mmsa generate MSA instructions\n\
20075 -mno-msa do not generate MSA instructions\n"));
20076 fprintf (stream, _("\
20077 -mxpa generate eXtended Physical Address (XPA) instructions\n\
20078 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
20079 fprintf (stream, _("\
20080 -mvirt generate Virtualization instructions\n\
20081 -mno-virt do not generate Virtualization instructions\n"));
20082 fprintf (stream, _("\
20083 -mcrc generate CRC instructions\n\
20084 -mno-crc do not generate CRC instructions\n"));
20085 fprintf (stream, _("\
20086 -mginv generate Global INValidate (GINV) instructions\n\
20087 -mno-ginv do not generate Global INValidate instructions\n"));
20088 fprintf (stream, _("\
20089 -mloongson-mmi generate Loongson MultiMedia extensions Instructions (MMI) instructions\n\
20090 -mno-loongson-mmi do not generate Loongson MultiMedia extensions Instructions\n"));
20091 fprintf (stream, _("\
20092 -mloongson-cam generate Loongson Content Address Memory (CAM) instructions\n\
20093 -mno-loongson-cam do not generate Loongson Content Address Memory Instructions\n"));
20094 fprintf (stream, _("\
20095 -mloongson-ext generate Loongson EXTensions (EXT) instructions\n\
20096 -mno-loongson-ext do not generate Loongson EXTensions Instructions\n"));
20097 fprintf (stream, _("\
20098 -mloongson-ext2 generate Loongson EXTensions R2 (EXT2) instructions\n\
20099 -mno-loongson-ext2 do not generate Loongson EXTensions R2 Instructions\n"));
20100 fprintf (stream, _("\
20101 -minsn32 only generate 32-bit microMIPS instructions\n\
20102 -mno-insn32 generate all microMIPS instructions\n"));
20103 fprintf (stream, _("\
20104 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
20105 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
20106 -mfix-vr4120 work around certain VR4120 errata\n\
20107 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
20108 -mfix-24k insert a nop after ERET and DERET instructions\n\
20109 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
20110 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
20111 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
20112 -msym32 assume all symbols have 32-bit values\n\
20113 -O0 do not remove unneeded NOPs, do not swap branches\n\
20114 -O, -O1 remove unneeded NOPs, do not swap branches\n\
20115 -O2 remove unneeded NOPs and swap branches\n\
20116 --trap, --no-break trap exception on div by 0 and mult overflow\n\
20117 --break, --no-trap break exception on div by 0 and mult overflow\n"));
20118 fprintf (stream, _("\
20119 -mhard-float allow floating-point instructions\n\
20120 -msoft-float do not allow floating-point instructions\n\
20121 -msingle-float only allow 32-bit floating-point operations\n\
20122 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
20123 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
20124 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
20125 -mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\
20126 -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\
20127 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
20131 show (stream, "legacy", &column, &first);
20132 show (stream, "2008", &column, &first);
20134 fputc ('\n', stream);
20136 fprintf (stream, _("\
20137 -KPIC, -call_shared generate SVR4 position independent code\n\
20138 -call_nonpic generate non-PIC code that can operate with DSOs\n\
20139 -mvxworks-pic generate VxWorks position independent code\n\
20140 -non_shared do not generate code that can operate with DSOs\n\
20141 -xgot assume a 32 bit GOT\n\
20142 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
20143 -mshared, -mno-shared disable/enable .cpload optimization for\n\
20144 position dependent (non shared) code\n\
20145 -mabi=ABI create ABI conformant object file for:\n"));
20149 show (stream, "32", &column, &first);
20150 show (stream, "o64", &column, &first);
20151 show (stream, "n32", &column, &first);
20152 show (stream, "64", &column, &first);
20153 show (stream, "eabi", &column, &first);
20155 fputc ('\n', stream);
20157 fprintf (stream, _("\
20158 -32 create o32 ABI object file%s\n"),
20159 MIPS_DEFAULT_ABI == O32_ABI ? _(" (default)") : "");
20160 fprintf (stream, _("\
20161 -n32 create n32 ABI object file%s\n"),
20162 MIPS_DEFAULT_ABI == N32_ABI ? _(" (default)") : "");
20163 fprintf (stream, _("\
20164 -64 create 64 ABI object file%s\n"),
20165 MIPS_DEFAULT_ABI == N64_ABI ? _(" (default)") : "");
20170 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
20172 if (HAVE_64BIT_SYMBOLS)
20173 return dwarf2_format_64bit_irix;
20175 return dwarf2_format_32bit;
20180 mips_dwarf2_addr_size (void)
20182 if (HAVE_64BIT_OBJECTS)
20188 /* Standard calling conventions leave the CFA at SP on entry. */
20190 mips_cfi_frame_initial_instructions (void)
20192 cfi_add_CFA_def_cfa_register (SP);
20196 tc_mips_regname_to_dw2regnum (char *regname)
20198 unsigned int regnum = -1;
20201 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))
20207 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
20208 Given a symbolic attribute NAME, return the proper integer value.
20209 Returns -1 if the attribute is not known. */
20212 mips_convert_symbolic_attribute (const char *name)
20214 static const struct
20219 attribute_table[] =
20221 #define T(tag) {#tag, tag}
20222 T (Tag_GNU_MIPS_ABI_FP),
20223 T (Tag_GNU_MIPS_ABI_MSA),
20231 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
20232 if (streq (name, attribute_table[i].name))
20233 return attribute_table[i].tag;
20241 int fpabi = Val_GNU_MIPS_ABI_FP_ANY;
20243 mips_emit_delays ();
20245 as_warn (_("missing .end at end of assembly"));
20247 /* Just in case no code was emitted, do the consistency check. */
20248 file_mips_check_options ();
20250 /* Set a floating-point ABI if the user did not. */
20251 if (obj_elf_seen_attribute (OBJ_ATTR_GNU, Tag_GNU_MIPS_ABI_FP))
20253 /* Perform consistency checks on the floating-point ABI. */
20254 fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
20255 Tag_GNU_MIPS_ABI_FP);
20256 if (fpabi != Val_GNU_MIPS_ABI_FP_ANY)
20257 check_fpabi (fpabi);
20261 /* Soft-float gets precedence over single-float, the two options should
20262 not be used together so this should not matter. */
20263 if (file_mips_opts.soft_float == 1)
20264 fpabi = Val_GNU_MIPS_ABI_FP_SOFT;
20265 /* Single-float gets precedence over all double_float cases. */
20266 else if (file_mips_opts.single_float == 1)
20267 fpabi = Val_GNU_MIPS_ABI_FP_SINGLE;
20270 switch (file_mips_opts.fp)
20273 if (file_mips_opts.gp == 32)
20274 fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE;
20277 fpabi = Val_GNU_MIPS_ABI_FP_XX;
20280 if (file_mips_opts.gp == 32 && !file_mips_opts.oddspreg)
20281 fpabi = Val_GNU_MIPS_ABI_FP_64A;
20282 else if (file_mips_opts.gp == 32)
20283 fpabi = Val_GNU_MIPS_ABI_FP_64;
20285 fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE;
20290 bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
20291 Tag_GNU_MIPS_ABI_FP, fpabi);
20295 /* Returns the relocation type required for a particular CFI encoding. */
20297 bfd_reloc_code_real_type
20298 mips_cfi_reloc_for_encoding (int encoding)
20300 if (encoding == (DW_EH_PE_sdata4 | DW_EH_PE_pcrel))
20301 return BFD_RELOC_32_PCREL;
20302 else return BFD_RELOC_NONE;