1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 #define AT mips_opts.at
107 /* Allow override of standard little-endian ECOFF format. */
109 #ifndef ECOFF_LITTLE_FORMAT
110 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
113 extern int target_big_endian;
115 /* The name of the readonly data section. */
116 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
124 /* Information about an instruction, including its format, operands
128 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
129 const struct mips_opcode *insn_mo;
131 /* True if this is a mips16 instruction and if we want the extended
133 bfd_boolean use_extend;
135 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
136 unsigned short extend;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. */
140 unsigned long insn_opcode;
142 /* The frag that contains the instruction. */
145 /* The offset into FRAG of the first instruction byte. */
148 /* The relocs associated with the instruction, if any. */
151 /* True if this entry cannot be moved from its current position. */
152 unsigned int fixed_p : 1;
154 /* True if this instruction occurred in a .set noreorder block. */
155 unsigned int noreorder_p : 1;
157 /* True for mips16 instructions that jump to an absolute address. */
158 unsigned int mips16_absolute_jump_p : 1;
160 /* True if this instruction is complete. */
161 unsigned int complete_p : 1;
164 /* The ABI to use. */
175 /* MIPS ABI we are using for this output file. */
176 static enum mips_abi_level mips_abi = NO_ABI;
178 /* Whether or not we have code that can call pic code. */
179 int mips_abicalls = FALSE;
181 /* Whether or not we have code which can be put into a shared
183 static bfd_boolean mips_in_shared = TRUE;
185 /* This is the set of options which may be modified by the .set
186 pseudo-op. We use a struct so that .set push and .set pop are more
189 struct mips_set_options
191 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
192 if it has not been initialized. Changed by `.set mipsN', and the
193 -mipsN command line option, and the default CPU. */
195 /* Enabled Application Specific Extensions (ASEs). These are set to -1
196 if they have not been initialized. Changed by `.set <asename>', by
197 command line options, and based on the default architecture. */
204 /* Whether we are assembling for the mips16 processor. 0 if we are
205 not, 1 if we are, and -1 if the value has not been initialized.
206 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
207 -nomips16 command line options, and the default CPU. */
209 /* Non-zero if we should not reorder instructions. Changed by `.set
210 reorder' and `.set noreorder'. */
212 /* Non-zero if we should not permit the register designated "assembler
213 temporary" to be used in instructions. The value is the register
214 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
215 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
217 /* Non-zero if we should warn when a macro instruction expands into
218 more than one machine instruction. Changed by `.set nomacro' and
220 int warn_about_macros;
221 /* Non-zero if we should not move instructions. Changed by `.set
222 move', `.set volatile', `.set nomove', and `.set novolatile'. */
224 /* Non-zero if we should not optimize branches by moving the target
225 of the branch into the delay slot. Actually, we don't perform
226 this optimization anyhow. Changed by `.set bopt' and `.set
229 /* Non-zero if we should not autoextend mips16 instructions.
230 Changed by `.set autoextend' and `.set noautoextend'. */
232 /* Restrict general purpose registers and floating point registers
233 to 32 bit. This is initially determined when -mgp32 or -mfp32
234 is passed but can changed if the assembler code uses .set mipsN. */
237 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
238 command line option, and the default CPU. */
240 /* True if ".set sym32" is in effect. */
242 /* True if floating-point operations are not allowed. Changed by .set
243 softfloat or .set hardfloat, by command line options -msoft-float or
244 -mhard-float. The default is false. */
245 bfd_boolean soft_float;
247 /* True if only single-precision floating-point operations are allowed.
248 Changed by .set singlefloat or .set doublefloat, command-line options
249 -msingle-float or -mdouble-float. The default is false. */
250 bfd_boolean single_float;
253 /* This is the struct we use to hold the current set of options. Note
254 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
255 -1 to indicate that they have not been initialized. */
257 /* True if -mgp32 was passed. */
258 static int file_mips_gp32 = -1;
260 /* True if -mfp32 was passed. */
261 static int file_mips_fp32 = -1;
263 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
264 static int file_mips_soft_float = 0;
266 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
267 static int file_mips_single_float = 0;
269 static struct mips_set_options mips_opts =
271 /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
272 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
273 /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG,
274 /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
275 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN,
276 /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE
279 /* These variables are filled in with the masks of registers used.
280 The object format code reads them and puts them in the appropriate
282 unsigned long mips_gprmask;
283 unsigned long mips_cprmask[4];
285 /* MIPS ISA we are using for this output file. */
286 static int file_mips_isa = ISA_UNKNOWN;
288 /* True if any MIPS16 code was produced. */
289 static int file_ase_mips16;
291 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
292 || mips_opts.isa == ISA_MIPS32R2 \
293 || mips_opts.isa == ISA_MIPS64 \
294 || mips_opts.isa == ISA_MIPS64R2)
296 /* True if we want to create R_MIPS_JALR for jalr $25. */
298 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
300 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
301 because there's no place for any addend, the only acceptable
302 expression is a bare symbol. */
303 #define MIPS_JALR_HINT_P(EXPR) \
304 (!HAVE_IN_PLACE_ADDENDS \
305 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
308 /* True if -mips3d was passed or implied by arguments passed on the
309 command line (e.g., by -march). */
310 static int file_ase_mips3d;
312 /* True if -mdmx was passed or implied by arguments passed on the
313 command line (e.g., by -march). */
314 static int file_ase_mdmx;
316 /* True if -msmartmips was passed or implied by arguments passed on the
317 command line (e.g., by -march). */
318 static int file_ase_smartmips;
320 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
321 || mips_opts.isa == ISA_MIPS32R2)
323 /* True if -mdsp was passed or implied by arguments passed on the
324 command line (e.g., by -march). */
325 static int file_ase_dsp;
327 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
328 || mips_opts.isa == ISA_MIPS64R2)
330 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
332 /* True if -mdspr2 was passed or implied by arguments passed on the
333 command line (e.g., by -march). */
334 static int file_ase_dspr2;
336 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
337 || mips_opts.isa == ISA_MIPS64R2)
339 /* True if -mmt was passed or implied by arguments passed on the
340 command line (e.g., by -march). */
341 static int file_ase_mt;
343 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
344 || mips_opts.isa == ISA_MIPS64R2)
346 /* The argument of the -march= flag. The architecture we are assembling. */
347 static int file_mips_arch = CPU_UNKNOWN;
348 static const char *mips_arch_string;
350 /* The argument of the -mtune= flag. The architecture for which we
352 static int mips_tune = CPU_UNKNOWN;
353 static const char *mips_tune_string;
355 /* True when generating 32-bit code for a 64-bit processor. */
356 static int mips_32bitmode = 0;
358 /* True if the given ABI requires 32-bit registers. */
359 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
361 /* Likewise 64-bit registers. */
362 #define ABI_NEEDS_64BIT_REGS(ABI) \
364 || (ABI) == N64_ABI \
367 /* Return true if ISA supports 64 bit wide gp registers. */
368 #define ISA_HAS_64BIT_REGS(ISA) \
369 ((ISA) == ISA_MIPS3 \
370 || (ISA) == ISA_MIPS4 \
371 || (ISA) == ISA_MIPS5 \
372 || (ISA) == ISA_MIPS64 \
373 || (ISA) == ISA_MIPS64R2)
375 /* Return true if ISA supports 64 bit wide float registers. */
376 #define ISA_HAS_64BIT_FPRS(ISA) \
377 ((ISA) == ISA_MIPS3 \
378 || (ISA) == ISA_MIPS4 \
379 || (ISA) == ISA_MIPS5 \
380 || (ISA) == ISA_MIPS32R2 \
381 || (ISA) == ISA_MIPS64 \
382 || (ISA) == ISA_MIPS64R2)
384 /* Return true if ISA supports 64-bit right rotate (dror et al.)
386 #define ISA_HAS_DROR(ISA) \
387 ((ISA) == ISA_MIPS64R2)
389 /* Return true if ISA supports 32-bit right rotate (ror et al.)
391 #define ISA_HAS_ROR(ISA) \
392 ((ISA) == ISA_MIPS32R2 \
393 || (ISA) == ISA_MIPS64R2 \
394 || mips_opts.ase_smartmips)
396 /* Return true if ISA supports single-precision floats in odd registers. */
397 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
398 ((ISA) == ISA_MIPS32 \
399 || (ISA) == ISA_MIPS32R2 \
400 || (ISA) == ISA_MIPS64 \
401 || (ISA) == ISA_MIPS64R2)
403 /* Return true if ISA supports move to/from high part of a 64-bit
404 floating-point register. */
405 #define ISA_HAS_MXHC1(ISA) \
406 ((ISA) == ISA_MIPS32R2 \
407 || (ISA) == ISA_MIPS64R2)
409 #define HAVE_32BIT_GPRS \
410 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
412 #define HAVE_32BIT_FPRS \
413 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
415 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
416 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
418 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
420 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
422 /* True if relocations are stored in-place. */
423 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
425 /* The ABI-derived address size. */
426 #define HAVE_64BIT_ADDRESSES \
427 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
428 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
430 /* The size of symbolic constants (i.e., expressions of the form
431 "SYMBOL" or "SYMBOL + OFFSET"). */
432 #define HAVE_32BIT_SYMBOLS \
433 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
434 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
436 /* Addresses are loaded in different ways, depending on the address size
437 in use. The n32 ABI Documentation also mandates the use of additions
438 with overflow checking, but existing implementations don't follow it. */
439 #define ADDRESS_ADD_INSN \
440 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
442 #define ADDRESS_ADDI_INSN \
443 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
445 #define ADDRESS_LOAD_INSN \
446 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
448 #define ADDRESS_STORE_INSN \
449 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
451 /* Return true if the given CPU supports the MIPS16 ASE. */
452 #define CPU_HAS_MIPS16(cpu) \
453 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
454 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
456 /* True if CPU has a dror instruction. */
457 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
459 /* True if CPU has a ror instruction. */
460 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
462 /* True if CPU has seq/sne and seqi/snei instructions. */
463 #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON)
465 /* True if CPU does not implement the all the coprocessor insns. For these
466 CPUs only those COP insns are accepted that are explicitly marked to be
467 available on the CPU. ISA membership for COP insns is ignored. */
468 #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON)
470 /* True if mflo and mfhi can be immediately followed by instructions
471 which write to the HI and LO registers.
473 According to MIPS specifications, MIPS ISAs I, II, and III need
474 (at least) two instructions between the reads of HI/LO and
475 instructions which write them, and later ISAs do not. Contradicting
476 the MIPS specifications, some MIPS IV processor user manuals (e.g.
477 the UM for the NEC Vr5000) document needing the instructions between
478 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
479 MIPS64 and later ISAs to have the interlocks, plus any specific
480 earlier-ISA CPUs for which CPU documentation declares that the
481 instructions are really interlocked. */
482 #define hilo_interlocks \
483 (mips_opts.isa == ISA_MIPS32 \
484 || mips_opts.isa == ISA_MIPS32R2 \
485 || mips_opts.isa == ISA_MIPS64 \
486 || mips_opts.isa == ISA_MIPS64R2 \
487 || mips_opts.arch == CPU_R4010 \
488 || mips_opts.arch == CPU_R10000 \
489 || mips_opts.arch == CPU_R12000 \
490 || mips_opts.arch == CPU_R14000 \
491 || mips_opts.arch == CPU_R16000 \
492 || mips_opts.arch == CPU_RM7000 \
493 || mips_opts.arch == CPU_VR5500 \
496 /* Whether the processor uses hardware interlocks to protect reads
497 from the GPRs after they are loaded from memory, and thus does not
498 require nops to be inserted. This applies to instructions marked
499 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
501 #define gpr_interlocks \
502 (mips_opts.isa != ISA_MIPS1 \
503 || mips_opts.arch == CPU_R3900)
505 /* Whether the processor uses hardware interlocks to avoid delays
506 required by coprocessor instructions, and thus does not require
507 nops to be inserted. This applies to instructions marked
508 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
509 between instructions marked INSN_WRITE_COND_CODE and ones marked
510 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
511 levels I, II, and III. */
512 /* Itbl support may require additional care here. */
513 #define cop_interlocks \
514 ((mips_opts.isa != ISA_MIPS1 \
515 && mips_opts.isa != ISA_MIPS2 \
516 && mips_opts.isa != ISA_MIPS3) \
517 || mips_opts.arch == CPU_R4300 \
520 /* Whether the processor uses hardware interlocks to protect reads
521 from coprocessor registers after they are loaded from memory, and
522 thus does not require nops to be inserted. This applies to
523 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
524 requires at MIPS ISA level I. */
525 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
527 /* Is this a mfhi or mflo instruction? */
528 #define MF_HILO_INSN(PINFO) \
529 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
531 /* Returns true for a (non floating-point) coprocessor instruction. Reading
532 or writing the condition code is only possible on the coprocessors and
533 these insns are not marked with INSN_COP. Thus for these insns use the
534 condition-code flags. */
535 #define COP_INSN(PINFO) \
536 (PINFO != INSN_MACRO \
537 && ((PINFO) & (FP_S | FP_D)) == 0 \
538 && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
540 /* MIPS PIC level. */
542 enum mips_pic_level mips_pic;
544 /* 1 if we should generate 32 bit offsets from the $gp register in
545 SVR4_PIC mode. Currently has no meaning in other modes. */
546 static int mips_big_got = 0;
548 /* 1 if trap instructions should used for overflow rather than break
550 static int mips_trap = 0;
552 /* 1 if double width floating point constants should not be constructed
553 by assembling two single width halves into two single width floating
554 point registers which just happen to alias the double width destination
555 register. On some architectures this aliasing can be disabled by a bit
556 in the status register, and the setting of this bit cannot be determined
557 automatically at assemble time. */
558 static int mips_disable_float_construction;
560 /* Non-zero if any .set noreorder directives were used. */
562 static int mips_any_noreorder;
564 /* Non-zero if nops should be inserted when the register referenced in
565 an mfhi/mflo instruction is read in the next two instructions. */
566 static int mips_7000_hilo_fix;
568 /* The size of objects in the small data section. */
569 static unsigned int g_switch_value = 8;
570 /* Whether the -G option was used. */
571 static int g_switch_seen = 0;
576 /* If we can determine in advance that GP optimization won't be
577 possible, we can skip the relaxation stuff that tries to produce
578 GP-relative references. This makes delay slot optimization work
581 This function can only provide a guess, but it seems to work for
582 gcc output. It needs to guess right for gcc, otherwise gcc
583 will put what it thinks is a GP-relative instruction in a branch
586 I don't know if a fix is needed for the SVR4_PIC mode. I've only
587 fixed it for the non-PIC mode. KR 95/04/07 */
588 static int nopic_need_relax (symbolS *, int);
590 /* handle of the OPCODE hash table */
591 static struct hash_control *op_hash = NULL;
593 /* The opcode hash table we use for the mips16. */
594 static struct hash_control *mips16_op_hash = NULL;
596 /* This array holds the chars that always start a comment. If the
597 pre-processor is disabled, these aren't very useful */
598 const char comment_chars[] = "#";
600 /* This array holds the chars that only start a comment at the beginning of
601 a line. If the line seems to have the form '# 123 filename'
602 .line and .file directives will appear in the pre-processed output */
603 /* Note that input_file.c hand checks for '#' at the beginning of the
604 first line of the input file. This is because the compiler outputs
605 #NO_APP at the beginning of its output. */
606 /* Also note that C style comments are always supported. */
607 const char line_comment_chars[] = "#";
609 /* This array holds machine specific line separator characters. */
610 const char line_separator_chars[] = ";";
612 /* Chars that can be used to separate mant from exp in floating point nums */
613 const char EXP_CHARS[] = "eE";
615 /* Chars that mean this number is a floating point constant */
618 const char FLT_CHARS[] = "rRsSfFdDxXpP";
620 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
621 changed in read.c . Ideally it shouldn't have to know about it at all,
622 but nothing is ideal around here.
625 static char *insn_error;
627 static int auto_align = 1;
629 /* When outputting SVR4 PIC code, the assembler needs to know the
630 offset in the stack frame from which to restore the $gp register.
631 This is set by the .cprestore pseudo-op, and saved in this
633 static offsetT mips_cprestore_offset = -1;
635 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
636 more optimizations, it can use a register value instead of a memory-saved
637 offset and even an other register than $gp as global pointer. */
638 static offsetT mips_cpreturn_offset = -1;
639 static int mips_cpreturn_register = -1;
640 static int mips_gp_register = GP;
641 static int mips_gprel_offset = 0;
643 /* Whether mips_cprestore_offset has been set in the current function
644 (or whether it has already been warned about, if not). */
645 static int mips_cprestore_valid = 0;
647 /* This is the register which holds the stack frame, as set by the
648 .frame pseudo-op. This is needed to implement .cprestore. */
649 static int mips_frame_reg = SP;
651 /* Whether mips_frame_reg has been set in the current function
652 (or whether it has already been warned about, if not). */
653 static int mips_frame_reg_valid = 0;
655 /* To output NOP instructions correctly, we need to keep information
656 about the previous two instructions. */
658 /* Whether we are optimizing. The default value of 2 means to remove
659 unneeded NOPs and swap branch instructions when possible. A value
660 of 1 means to not swap branches. A value of 0 means to always
662 static int mips_optimize = 2;
664 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
665 equivalent to seeing no -g option at all. */
666 static int mips_debug = 0;
668 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
669 #define MAX_VR4130_NOPS 4
671 /* The maximum number of NOPs needed to fill delay slots. */
672 #define MAX_DELAY_NOPS 2
674 /* The maximum number of NOPs needed for any purpose. */
677 /* A list of previous instructions, with index 0 being the most recent.
678 We need to look back MAX_NOPS instructions when filling delay slots
679 or working around processor errata. We need to look back one
680 instruction further if we're thinking about using history[0] to
681 fill a branch delay slot. */
682 static struct mips_cl_insn history[1 + MAX_NOPS];
684 /* Nop instructions used by emit_nop. */
685 static struct mips_cl_insn nop_insn, mips16_nop_insn;
687 /* The appropriate nop for the current mode. */
688 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
690 /* If this is set, it points to a frag holding nop instructions which
691 were inserted before the start of a noreorder section. If those
692 nops turn out to be unnecessary, the size of the frag can be
694 static fragS *prev_nop_frag;
696 /* The number of nop instructions we created in prev_nop_frag. */
697 static int prev_nop_frag_holds;
699 /* The number of nop instructions that we know we need in
701 static int prev_nop_frag_required;
703 /* The number of instructions we've seen since prev_nop_frag. */
704 static int prev_nop_frag_since;
706 /* For ECOFF and ELF, relocations against symbols are done in two
707 parts, with a HI relocation and a LO relocation. Each relocation
708 has only 16 bits of space to store an addend. This means that in
709 order for the linker to handle carries correctly, it must be able
710 to locate both the HI and the LO relocation. This means that the
711 relocations must appear in order in the relocation table.
713 In order to implement this, we keep track of each unmatched HI
714 relocation. We then sort them so that they immediately precede the
715 corresponding LO relocation. */
720 struct mips_hi_fixup *next;
723 /* The section this fixup is in. */
727 /* The list of unmatched HI relocs. */
729 static struct mips_hi_fixup *mips_hi_fixup_list;
731 /* The frag containing the last explicit relocation operator.
732 Null if explicit relocations have not been used. */
734 static fragS *prev_reloc_op_frag;
736 /* Map normal MIPS register numbers to mips16 register numbers. */
738 #define X ILLEGAL_REG
739 static const int mips32_to_16_reg_map[] =
741 X, X, 2, 3, 4, 5, 6, 7,
742 X, X, X, X, X, X, X, X,
743 0, 1, X, X, X, X, X, X,
744 X, X, X, X, X, X, X, X
748 /* Map mips16 register numbers to normal MIPS register numbers. */
750 static const unsigned int mips16_to_32_reg_map[] =
752 16, 17, 2, 3, 4, 5, 6, 7
755 /* Classifies the kind of instructions we're interested in when
756 implementing -mfix-vr4120. */
757 enum fix_vr4120_class
765 NUM_FIX_VR4120_CLASSES
768 /* ...likewise -mfix-loongson2f-jump. */
769 static bfd_boolean mips_fix_loongson2f_jump;
771 /* ...likewise -mfix-loongson2f-nop. */
772 static bfd_boolean mips_fix_loongson2f_nop;
774 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
775 static bfd_boolean mips_fix_loongson2f;
777 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
778 there must be at least one other instruction between an instruction
779 of type X and an instruction of type Y. */
780 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
782 /* True if -mfix-vr4120 is in force. */
783 static int mips_fix_vr4120;
785 /* ...likewise -mfix-vr4130. */
786 static int mips_fix_vr4130;
788 /* ...likewise -mfix-24k. */
789 static int mips_fix_24k;
791 /* ...likewise -mfix-cn63xxp1 */
792 static bfd_boolean mips_fix_cn63xxp1;
794 /* We don't relax branches by default, since this causes us to expand
795 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
796 fail to compute the offset before expanding the macro to the most
797 efficient expansion. */
799 static int mips_relax_branch;
801 /* The expansion of many macros depends on the type of symbol that
802 they refer to. For example, when generating position-dependent code,
803 a macro that refers to a symbol may have two different expansions,
804 one which uses GP-relative addresses and one which uses absolute
805 addresses. When generating SVR4-style PIC, a macro may have
806 different expansions for local and global symbols.
808 We handle these situations by generating both sequences and putting
809 them in variant frags. In position-dependent code, the first sequence
810 will be the GP-relative one and the second sequence will be the
811 absolute one. In SVR4 PIC, the first sequence will be for global
812 symbols and the second will be for local symbols.
814 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
815 SECOND are the lengths of the two sequences in bytes. These fields
816 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
817 the subtype has the following flags:
820 Set if it has been decided that we should use the second
821 sequence instead of the first.
824 Set in the first variant frag if the macro's second implementation
825 is longer than its first. This refers to the macro as a whole,
826 not an individual relaxation.
829 Set in the first variant frag if the macro appeared in a .set nomacro
830 block and if one alternative requires a warning but the other does not.
833 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
836 The frag's "opcode" points to the first fixup for relaxable code.
838 Relaxable macros are generated using a sequence such as:
840 relax_start (SYMBOL);
841 ... generate first expansion ...
843 ... generate second expansion ...
846 The code and fixups for the unwanted alternative are discarded
847 by md_convert_frag. */
848 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
850 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
851 #define RELAX_SECOND(X) ((X) & 0xff)
852 #define RELAX_USE_SECOND 0x10000
853 #define RELAX_SECOND_LONGER 0x20000
854 #define RELAX_NOMACRO 0x40000
855 #define RELAX_DELAY_SLOT 0x80000
857 /* Branch without likely bit. If label is out of range, we turn:
859 beq reg1, reg2, label
869 with the following opcode replacements:
876 bltzal <-> bgezal (with jal label instead of j label)
878 Even though keeping the delay slot instruction in the delay slot of
879 the branch would be more efficient, it would be very tricky to do
880 correctly, because we'd have to introduce a variable frag *after*
881 the delay slot instruction, and expand that instead. Let's do it
882 the easy way for now, even if the branch-not-taken case now costs
883 one additional instruction. Out-of-range branches are not supposed
884 to be common, anyway.
886 Branch likely. If label is out of range, we turn:
888 beql reg1, reg2, label
889 delay slot (annulled if branch not taken)
898 delay slot (executed only if branch taken)
901 It would be possible to generate a shorter sequence by losing the
902 likely bit, generating something like:
907 delay slot (executed only if branch taken)
919 bltzall -> bgezal (with jal label instead of j label)
920 bgezall -> bltzal (ditto)
923 but it's not clear that it would actually improve performance. */
924 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
928 | ((toofar) ? 0x20 : 0) \
929 | ((link) ? 0x40 : 0) \
930 | ((likely) ? 0x80 : 0) \
931 | ((uncond) ? 0x100 : 0)))
932 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
933 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
934 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
935 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
936 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
937 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
939 /* For mips16 code, we use an entirely different form of relaxation.
940 mips16 supports two versions of most instructions which take
941 immediate values: a small one which takes some small value, and a
942 larger one which takes a 16 bit value. Since branches also follow
943 this pattern, relaxing these values is required.
945 We can assemble both mips16 and normal MIPS code in a single
946 object. Therefore, we need to support this type of relaxation at
947 the same time that we support the relaxation described above. We
948 use the high bit of the subtype field to distinguish these cases.
950 The information we store for this type of relaxation is the
951 argument code found in the opcode file for this relocation, whether
952 the user explicitly requested a small or extended form, and whether
953 the relocation is in a jump or jal delay slot. That tells us the
954 size of the value, and how it should be stored. We also store
955 whether the fragment is considered to be extended or not. We also
956 store whether this is known to be a branch to a different section,
957 whether we have tried to relax this frag yet, and whether we have
958 ever extended a PC relative fragment because of a shift count. */
959 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
962 | ((small) ? 0x100 : 0) \
963 | ((ext) ? 0x200 : 0) \
964 | ((dslot) ? 0x400 : 0) \
965 | ((jal_dslot) ? 0x800 : 0))
966 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
967 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
968 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
969 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
970 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
971 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
972 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
973 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
974 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
975 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
976 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
977 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
979 /* Is the given value a sign-extended 32-bit value? */
980 #define IS_SEXT_32BIT_NUM(x) \
981 (((x) &~ (offsetT) 0x7fffffff) == 0 \
982 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
984 /* Is the given value a sign-extended 16-bit value? */
985 #define IS_SEXT_16BIT_NUM(x) \
986 (((x) &~ (offsetT) 0x7fff) == 0 \
987 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
989 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
990 #define IS_ZEXT_32BIT_NUM(x) \
991 (((x) &~ (offsetT) 0xffffffff) == 0 \
992 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
994 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
995 VALUE << SHIFT. VALUE is evaluated exactly once. */
996 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
997 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
998 | (((VALUE) & (MASK)) << (SHIFT)))
1000 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1002 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1003 (((STRUCT) >> (SHIFT)) & (MASK))
1005 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1006 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1008 include/opcode/mips.h specifies operand fields using the macros
1009 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1010 with "MIPS16OP" instead of "OP". */
1011 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
1012 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
1013 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1014 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1015 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1017 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1018 #define EXTRACT_OPERAND(FIELD, INSN) \
1019 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
1020 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1021 EXTRACT_BITS ((INSN).insn_opcode, \
1022 MIPS16OP_MASK_##FIELD, \
1023 MIPS16OP_SH_##FIELD)
1025 /* Global variables used when generating relaxable macros. See the
1026 comment above RELAX_ENCODE for more details about how relaxation
1029 /* 0 if we're not emitting a relaxable macro.
1030 1 if we're emitting the first of the two relaxation alternatives.
1031 2 if we're emitting the second alternative. */
1034 /* The first relaxable fixup in the current frag. (In other words,
1035 the first fixup that refers to relaxable code.) */
1038 /* sizes[0] says how many bytes of the first alternative are stored in
1039 the current frag. Likewise sizes[1] for the second alternative. */
1040 unsigned int sizes[2];
1042 /* The symbol on which the choice of sequence depends. */
1046 /* Global variables used to decide whether a macro needs a warning. */
1048 /* True if the macro is in a branch delay slot. */
1049 bfd_boolean delay_slot_p;
1051 /* For relaxable macros, sizes[0] is the length of the first alternative
1052 in bytes and sizes[1] is the length of the second alternative.
1053 For non-relaxable macros, both elements give the length of the
1055 unsigned int sizes[2];
1057 /* The first variant frag for this macro. */
1059 } mips_macro_warning;
1061 /* Prototypes for static functions. */
1063 #define internalError() \
1064 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1066 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1068 static void append_insn
1069 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *);
1070 static void mips_no_prev_insn (void);
1071 static void macro_build (expressionS *, const char *, const char *, ...);
1072 static void mips16_macro_build
1073 (expressionS *, const char *, const char *, va_list *);
1074 static void load_register (int, expressionS *, int);
1075 static void macro_start (void);
1076 static void macro_end (void);
1077 static void macro (struct mips_cl_insn * ip);
1078 static void mips16_macro (struct mips_cl_insn * ip);
1079 static void mips_ip (char *str, struct mips_cl_insn * ip);
1080 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1081 static void mips16_immed
1082 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
1083 unsigned long *, bfd_boolean *, unsigned short *);
1084 static size_t my_getSmallExpression
1085 (expressionS *, bfd_reloc_code_real_type *, char *);
1086 static void my_getExpression (expressionS *, char *);
1087 static void s_align (int);
1088 static void s_change_sec (int);
1089 static void s_change_section (int);
1090 static void s_cons (int);
1091 static void s_float_cons (int);
1092 static void s_mips_globl (int);
1093 static void s_option (int);
1094 static void s_mipsset (int);
1095 static void s_abicalls (int);
1096 static void s_cpload (int);
1097 static void s_cpsetup (int);
1098 static void s_cplocal (int);
1099 static void s_cprestore (int);
1100 static void s_cpreturn (int);
1101 static void s_dtprelword (int);
1102 static void s_dtpreldword (int);
1103 static void s_gpvalue (int);
1104 static void s_gpword (int);
1105 static void s_gpdword (int);
1106 static void s_cpadd (int);
1107 static void s_insn (int);
1108 static void md_obj_begin (void);
1109 static void md_obj_end (void);
1110 static void s_mips_ent (int);
1111 static void s_mips_end (int);
1112 static void s_mips_frame (int);
1113 static void s_mips_mask (int reg_type);
1114 static void s_mips_stab (int);
1115 static void s_mips_weakext (int);
1116 static void s_mips_file (int);
1117 static void s_mips_loc (int);
1118 static bfd_boolean pic_need_relax (symbolS *, asection *);
1119 static int relaxed_branch_length (fragS *, asection *, int);
1120 static int validate_mips_insn (const struct mips_opcode *);
1122 /* Table and functions used to map between CPU/ISA names, and
1123 ISA levels, and CPU numbers. */
1125 struct mips_cpu_info
1127 const char *name; /* CPU or ISA name. */
1128 int flags; /* ASEs available, or ISA flag. */
1129 int isa; /* ISA level. */
1130 int cpu; /* CPU number (default CPU if ISA). */
1133 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1134 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1135 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1136 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1137 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1138 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1139 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1141 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1142 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1143 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1147 The following pseudo-ops from the Kane and Heinrich MIPS book
1148 should be defined here, but are currently unsupported: .alias,
1149 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1151 The following pseudo-ops from the Kane and Heinrich MIPS book are
1152 specific to the type of debugging information being generated, and
1153 should be defined by the object format: .aent, .begin, .bend,
1154 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1157 The following pseudo-ops from the Kane and Heinrich MIPS book are
1158 not MIPS CPU specific, but are also not specific to the object file
1159 format. This file is probably the best place to define them, but
1160 they are not currently supported: .asm0, .endr, .lab, .struct. */
1162 static const pseudo_typeS mips_pseudo_table[] =
1164 /* MIPS specific pseudo-ops. */
1165 {"option", s_option, 0},
1166 {"set", s_mipsset, 0},
1167 {"rdata", s_change_sec, 'r'},
1168 {"sdata", s_change_sec, 's'},
1169 {"livereg", s_ignore, 0},
1170 {"abicalls", s_abicalls, 0},
1171 {"cpload", s_cpload, 0},
1172 {"cpsetup", s_cpsetup, 0},
1173 {"cplocal", s_cplocal, 0},
1174 {"cprestore", s_cprestore, 0},
1175 {"cpreturn", s_cpreturn, 0},
1176 {"dtprelword", s_dtprelword, 0},
1177 {"dtpreldword", s_dtpreldword, 0},
1178 {"gpvalue", s_gpvalue, 0},
1179 {"gpword", s_gpword, 0},
1180 {"gpdword", s_gpdword, 0},
1181 {"cpadd", s_cpadd, 0},
1182 {"insn", s_insn, 0},
1184 /* Relatively generic pseudo-ops that happen to be used on MIPS
1186 {"asciiz", stringer, 8 + 1},
1187 {"bss", s_change_sec, 'b'},
1189 {"half", s_cons, 1},
1190 {"dword", s_cons, 3},
1191 {"weakext", s_mips_weakext, 0},
1192 {"origin", s_org, 0},
1193 {"repeat", s_rept, 0},
1195 /* For MIPS this is non-standard, but we define it for consistency. */
1196 {"sbss", s_change_sec, 'B'},
1198 /* These pseudo-ops are defined in read.c, but must be overridden
1199 here for one reason or another. */
1200 {"align", s_align, 0},
1201 {"byte", s_cons, 0},
1202 {"data", s_change_sec, 'd'},
1203 {"double", s_float_cons, 'd'},
1204 {"float", s_float_cons, 'f'},
1205 {"globl", s_mips_globl, 0},
1206 {"global", s_mips_globl, 0},
1207 {"hword", s_cons, 1},
1209 {"long", s_cons, 2},
1210 {"octa", s_cons, 4},
1211 {"quad", s_cons, 3},
1212 {"section", s_change_section, 0},
1213 {"short", s_cons, 1},
1214 {"single", s_float_cons, 'f'},
1215 {"stabn", s_mips_stab, 'n'},
1216 {"text", s_change_sec, 't'},
1217 {"word", s_cons, 2},
1219 { "extern", ecoff_directive_extern, 0},
1224 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1226 /* These pseudo-ops should be defined by the object file format.
1227 However, a.out doesn't support them, so we have versions here. */
1228 {"aent", s_mips_ent, 1},
1229 {"bgnb", s_ignore, 0},
1230 {"end", s_mips_end, 0},
1231 {"endb", s_ignore, 0},
1232 {"ent", s_mips_ent, 0},
1233 {"file", s_mips_file, 0},
1234 {"fmask", s_mips_mask, 'F'},
1235 {"frame", s_mips_frame, 0},
1236 {"loc", s_mips_loc, 0},
1237 {"mask", s_mips_mask, 'R'},
1238 {"verstamp", s_ignore, 0},
1242 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1243 purpose of the `.dc.a' internal pseudo-op. */
1246 mips_address_bytes (void)
1248 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1251 extern void pop_insert (const pseudo_typeS *);
1254 mips_pop_insert (void)
1256 pop_insert (mips_pseudo_table);
1257 if (! ECOFF_DEBUGGING)
1258 pop_insert (mips_nonecoff_pseudo_table);
1261 /* Symbols labelling the current insn. */
1263 struct insn_label_list
1265 struct insn_label_list *next;
1269 static struct insn_label_list *free_insn_labels;
1270 #define label_list tc_segment_info_data.labels
1272 static void mips_clear_insn_labels (void);
1275 mips_clear_insn_labels (void)
1277 register struct insn_label_list **pl;
1278 segment_info_type *si;
1282 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1285 si = seg_info (now_seg);
1286 *pl = si->label_list;
1287 si->label_list = NULL;
1292 static char *expr_end;
1294 /* Expressions which appear in instructions. These are set by
1297 static expressionS imm_expr;
1298 static expressionS imm2_expr;
1299 static expressionS offset_expr;
1301 /* Relocs associated with imm_expr and offset_expr. */
1303 static bfd_reloc_code_real_type imm_reloc[3]
1304 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1305 static bfd_reloc_code_real_type offset_reloc[3]
1306 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1308 /* These are set by mips16_ip if an explicit extension is used. */
1310 static bfd_boolean mips16_small, mips16_ext;
1313 /* The pdr segment for per procedure frame/regmask info. Not used for
1316 static segT pdr_seg;
1319 /* The default target format to use. */
1321 #if defined (TE_FreeBSD)
1322 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1323 #elif defined (TE_TMIPS)
1324 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1326 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1330 mips_target_format (void)
1332 switch (OUTPUT_FLAVOR)
1334 case bfd_target_ecoff_flavour:
1335 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1336 case bfd_target_coff_flavour:
1338 case bfd_target_elf_flavour:
1340 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1341 return (target_big_endian
1342 ? "elf32-bigmips-vxworks"
1343 : "elf32-littlemips-vxworks");
1345 return (target_big_endian
1346 ? (HAVE_64BIT_OBJECTS
1347 ? ELF_TARGET ("elf64-", "big")
1349 ? ELF_TARGET ("elf32-n", "big")
1350 : ELF_TARGET ("elf32-", "big")))
1351 : (HAVE_64BIT_OBJECTS
1352 ? ELF_TARGET ("elf64-", "little")
1354 ? ELF_TARGET ("elf32-n", "little")
1355 : ELF_TARGET ("elf32-", "little"))));
1362 /* Return the length of instruction INSN. */
1364 static inline unsigned int
1365 insn_length (const struct mips_cl_insn *insn)
1367 if (!mips_opts.mips16)
1369 return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2;
1372 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1375 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1380 insn->use_extend = FALSE;
1382 insn->insn_opcode = mo->match;
1385 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1386 insn->fixp[i] = NULL;
1387 insn->fixed_p = (mips_opts.noreorder > 0);
1388 insn->noreorder_p = (mips_opts.noreorder > 0);
1389 insn->mips16_absolute_jump_p = 0;
1390 insn->complete_p = 0;
1393 /* Record the current MIPS16 mode in now_seg. */
1396 mips_record_mips16_mode (void)
1398 segment_info_type *si;
1400 si = seg_info (now_seg);
1401 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
1402 si->tc_segment_info_data.mips16 = mips_opts.mips16;
1405 /* Install INSN at the location specified by its "frag" and "where" fields. */
1408 install_insn (const struct mips_cl_insn *insn)
1410 char *f = insn->frag->fr_literal + insn->where;
1411 if (!mips_opts.mips16)
1412 md_number_to_chars (f, insn->insn_opcode, 4);
1413 else if (insn->mips16_absolute_jump_p)
1415 md_number_to_chars (f, insn->insn_opcode >> 16, 2);
1416 md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2);
1420 if (insn->use_extend)
1422 md_number_to_chars (f, 0xf000 | insn->extend, 2);
1425 md_number_to_chars (f, insn->insn_opcode, 2);
1427 mips_record_mips16_mode ();
1430 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1431 and install the opcode in the new location. */
1434 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
1439 insn->where = where;
1440 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1441 if (insn->fixp[i] != NULL)
1443 insn->fixp[i]->fx_frag = frag;
1444 insn->fixp[i]->fx_where = where;
1446 install_insn (insn);
1449 /* Add INSN to the end of the output. */
1452 add_fixed_insn (struct mips_cl_insn *insn)
1454 char *f = frag_more (insn_length (insn));
1455 move_insn (insn, frag_now, f - frag_now->fr_literal);
1458 /* Start a variant frag and move INSN to the start of the variant part,
1459 marking it as fixed. The other arguments are as for frag_var. */
1462 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
1463 relax_substateT subtype, symbolS *symbol, offsetT offset)
1465 frag_grow (max_chars);
1466 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
1468 frag_var (rs_machine_dependent, max_chars, var,
1469 subtype, symbol, offset, NULL);
1472 /* Insert N copies of INSN into the history buffer, starting at
1473 position FIRST. Neither FIRST nor N need to be clipped. */
1476 insert_into_history (unsigned int first, unsigned int n,
1477 const struct mips_cl_insn *insn)
1479 if (mips_relax.sequence != 2)
1483 for (i = ARRAY_SIZE (history); i-- > first;)
1485 history[i] = history[i - n];
1491 /* Emit a nop instruction, recording it in the history buffer. */
1496 add_fixed_insn (NOP_INSN);
1497 insert_into_history (0, 1, NOP_INSN);
1500 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1501 the idea is to make it obvious at a glance that each errata is
1505 init_vr4120_conflicts (void)
1507 #define CONFLICT(FIRST, SECOND) \
1508 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1510 /* Errata 21 - [D]DIV[U] after [D]MACC */
1511 CONFLICT (MACC, DIV);
1512 CONFLICT (DMACC, DIV);
1514 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1515 CONFLICT (DMULT, DMULT);
1516 CONFLICT (DMULT, DMACC);
1517 CONFLICT (DMACC, DMULT);
1518 CONFLICT (DMACC, DMACC);
1520 /* Errata 24 - MT{LO,HI} after [D]MACC */
1521 CONFLICT (MACC, MTHILO);
1522 CONFLICT (DMACC, MTHILO);
1524 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1525 instruction is executed immediately after a MACC or DMACC
1526 instruction, the result of [either instruction] is incorrect." */
1527 CONFLICT (MACC, MULT);
1528 CONFLICT (MACC, DMULT);
1529 CONFLICT (DMACC, MULT);
1530 CONFLICT (DMACC, DMULT);
1532 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1533 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1534 DDIV or DDIVU instruction, the result of the MACC or
1535 DMACC instruction is incorrect.". */
1536 CONFLICT (DMULT, MACC);
1537 CONFLICT (DMULT, DMACC);
1538 CONFLICT (DIV, MACC);
1539 CONFLICT (DIV, DMACC);
1549 #define RTYPE_MASK 0x1ff00
1550 #define RTYPE_NUM 0x00100
1551 #define RTYPE_FPU 0x00200
1552 #define RTYPE_FCC 0x00400
1553 #define RTYPE_VEC 0x00800
1554 #define RTYPE_GP 0x01000
1555 #define RTYPE_CP0 0x02000
1556 #define RTYPE_PC 0x04000
1557 #define RTYPE_ACC 0x08000
1558 #define RTYPE_CCC 0x10000
1559 #define RNUM_MASK 0x000ff
1560 #define RWARN 0x80000
1562 #define GENERIC_REGISTER_NUMBERS \
1563 {"$0", RTYPE_NUM | 0}, \
1564 {"$1", RTYPE_NUM | 1}, \
1565 {"$2", RTYPE_NUM | 2}, \
1566 {"$3", RTYPE_NUM | 3}, \
1567 {"$4", RTYPE_NUM | 4}, \
1568 {"$5", RTYPE_NUM | 5}, \
1569 {"$6", RTYPE_NUM | 6}, \
1570 {"$7", RTYPE_NUM | 7}, \
1571 {"$8", RTYPE_NUM | 8}, \
1572 {"$9", RTYPE_NUM | 9}, \
1573 {"$10", RTYPE_NUM | 10}, \
1574 {"$11", RTYPE_NUM | 11}, \
1575 {"$12", RTYPE_NUM | 12}, \
1576 {"$13", RTYPE_NUM | 13}, \
1577 {"$14", RTYPE_NUM | 14}, \
1578 {"$15", RTYPE_NUM | 15}, \
1579 {"$16", RTYPE_NUM | 16}, \
1580 {"$17", RTYPE_NUM | 17}, \
1581 {"$18", RTYPE_NUM | 18}, \
1582 {"$19", RTYPE_NUM | 19}, \
1583 {"$20", RTYPE_NUM | 20}, \
1584 {"$21", RTYPE_NUM | 21}, \
1585 {"$22", RTYPE_NUM | 22}, \
1586 {"$23", RTYPE_NUM | 23}, \
1587 {"$24", RTYPE_NUM | 24}, \
1588 {"$25", RTYPE_NUM | 25}, \
1589 {"$26", RTYPE_NUM | 26}, \
1590 {"$27", RTYPE_NUM | 27}, \
1591 {"$28", RTYPE_NUM | 28}, \
1592 {"$29", RTYPE_NUM | 29}, \
1593 {"$30", RTYPE_NUM | 30}, \
1594 {"$31", RTYPE_NUM | 31}
1596 #define FPU_REGISTER_NAMES \
1597 {"$f0", RTYPE_FPU | 0}, \
1598 {"$f1", RTYPE_FPU | 1}, \
1599 {"$f2", RTYPE_FPU | 2}, \
1600 {"$f3", RTYPE_FPU | 3}, \
1601 {"$f4", RTYPE_FPU | 4}, \
1602 {"$f5", RTYPE_FPU | 5}, \
1603 {"$f6", RTYPE_FPU | 6}, \
1604 {"$f7", RTYPE_FPU | 7}, \
1605 {"$f8", RTYPE_FPU | 8}, \
1606 {"$f9", RTYPE_FPU | 9}, \
1607 {"$f10", RTYPE_FPU | 10}, \
1608 {"$f11", RTYPE_FPU | 11}, \
1609 {"$f12", RTYPE_FPU | 12}, \
1610 {"$f13", RTYPE_FPU | 13}, \
1611 {"$f14", RTYPE_FPU | 14}, \
1612 {"$f15", RTYPE_FPU | 15}, \
1613 {"$f16", RTYPE_FPU | 16}, \
1614 {"$f17", RTYPE_FPU | 17}, \
1615 {"$f18", RTYPE_FPU | 18}, \
1616 {"$f19", RTYPE_FPU | 19}, \
1617 {"$f20", RTYPE_FPU | 20}, \
1618 {"$f21", RTYPE_FPU | 21}, \
1619 {"$f22", RTYPE_FPU | 22}, \
1620 {"$f23", RTYPE_FPU | 23}, \
1621 {"$f24", RTYPE_FPU | 24}, \
1622 {"$f25", RTYPE_FPU | 25}, \
1623 {"$f26", RTYPE_FPU | 26}, \
1624 {"$f27", RTYPE_FPU | 27}, \
1625 {"$f28", RTYPE_FPU | 28}, \
1626 {"$f29", RTYPE_FPU | 29}, \
1627 {"$f30", RTYPE_FPU | 30}, \
1628 {"$f31", RTYPE_FPU | 31}
1630 #define FPU_CONDITION_CODE_NAMES \
1631 {"$fcc0", RTYPE_FCC | 0}, \
1632 {"$fcc1", RTYPE_FCC | 1}, \
1633 {"$fcc2", RTYPE_FCC | 2}, \
1634 {"$fcc3", RTYPE_FCC | 3}, \
1635 {"$fcc4", RTYPE_FCC | 4}, \
1636 {"$fcc5", RTYPE_FCC | 5}, \
1637 {"$fcc6", RTYPE_FCC | 6}, \
1638 {"$fcc7", RTYPE_FCC | 7}
1640 #define COPROC_CONDITION_CODE_NAMES \
1641 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1642 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1643 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1644 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1645 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1646 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1647 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1648 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1650 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1651 {"$a4", RTYPE_GP | 8}, \
1652 {"$a5", RTYPE_GP | 9}, \
1653 {"$a6", RTYPE_GP | 10}, \
1654 {"$a7", RTYPE_GP | 11}, \
1655 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1656 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1657 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1658 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1659 {"$t0", RTYPE_GP | 12}, \
1660 {"$t1", RTYPE_GP | 13}, \
1661 {"$t2", RTYPE_GP | 14}, \
1662 {"$t3", RTYPE_GP | 15}
1664 #define O32_SYMBOLIC_REGISTER_NAMES \
1665 {"$t0", RTYPE_GP | 8}, \
1666 {"$t1", RTYPE_GP | 9}, \
1667 {"$t2", RTYPE_GP | 10}, \
1668 {"$t3", RTYPE_GP | 11}, \
1669 {"$t4", RTYPE_GP | 12}, \
1670 {"$t5", RTYPE_GP | 13}, \
1671 {"$t6", RTYPE_GP | 14}, \
1672 {"$t7", RTYPE_GP | 15}, \
1673 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1674 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1675 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1676 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1678 /* Remaining symbolic register names */
1679 #define SYMBOLIC_REGISTER_NAMES \
1680 {"$zero", RTYPE_GP | 0}, \
1681 {"$at", RTYPE_GP | 1}, \
1682 {"$AT", RTYPE_GP | 1}, \
1683 {"$v0", RTYPE_GP | 2}, \
1684 {"$v1", RTYPE_GP | 3}, \
1685 {"$a0", RTYPE_GP | 4}, \
1686 {"$a1", RTYPE_GP | 5}, \
1687 {"$a2", RTYPE_GP | 6}, \
1688 {"$a3", RTYPE_GP | 7}, \
1689 {"$s0", RTYPE_GP | 16}, \
1690 {"$s1", RTYPE_GP | 17}, \
1691 {"$s2", RTYPE_GP | 18}, \
1692 {"$s3", RTYPE_GP | 19}, \
1693 {"$s4", RTYPE_GP | 20}, \
1694 {"$s5", RTYPE_GP | 21}, \
1695 {"$s6", RTYPE_GP | 22}, \
1696 {"$s7", RTYPE_GP | 23}, \
1697 {"$t8", RTYPE_GP | 24}, \
1698 {"$t9", RTYPE_GP | 25}, \
1699 {"$k0", RTYPE_GP | 26}, \
1700 {"$kt0", RTYPE_GP | 26}, \
1701 {"$k1", RTYPE_GP | 27}, \
1702 {"$kt1", RTYPE_GP | 27}, \
1703 {"$gp", RTYPE_GP | 28}, \
1704 {"$sp", RTYPE_GP | 29}, \
1705 {"$s8", RTYPE_GP | 30}, \
1706 {"$fp", RTYPE_GP | 30}, \
1707 {"$ra", RTYPE_GP | 31}
1709 #define MIPS16_SPECIAL_REGISTER_NAMES \
1710 {"$pc", RTYPE_PC | 0}
1712 #define MDMX_VECTOR_REGISTER_NAMES \
1713 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
1714 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
1715 {"$v2", RTYPE_VEC | 2}, \
1716 {"$v3", RTYPE_VEC | 3}, \
1717 {"$v4", RTYPE_VEC | 4}, \
1718 {"$v5", RTYPE_VEC | 5}, \
1719 {"$v6", RTYPE_VEC | 6}, \
1720 {"$v7", RTYPE_VEC | 7}, \
1721 {"$v8", RTYPE_VEC | 8}, \
1722 {"$v9", RTYPE_VEC | 9}, \
1723 {"$v10", RTYPE_VEC | 10}, \
1724 {"$v11", RTYPE_VEC | 11}, \
1725 {"$v12", RTYPE_VEC | 12}, \
1726 {"$v13", RTYPE_VEC | 13}, \
1727 {"$v14", RTYPE_VEC | 14}, \
1728 {"$v15", RTYPE_VEC | 15}, \
1729 {"$v16", RTYPE_VEC | 16}, \
1730 {"$v17", RTYPE_VEC | 17}, \
1731 {"$v18", RTYPE_VEC | 18}, \
1732 {"$v19", RTYPE_VEC | 19}, \
1733 {"$v20", RTYPE_VEC | 20}, \
1734 {"$v21", RTYPE_VEC | 21}, \
1735 {"$v22", RTYPE_VEC | 22}, \
1736 {"$v23", RTYPE_VEC | 23}, \
1737 {"$v24", RTYPE_VEC | 24}, \
1738 {"$v25", RTYPE_VEC | 25}, \
1739 {"$v26", RTYPE_VEC | 26}, \
1740 {"$v27", RTYPE_VEC | 27}, \
1741 {"$v28", RTYPE_VEC | 28}, \
1742 {"$v29", RTYPE_VEC | 29}, \
1743 {"$v30", RTYPE_VEC | 30}, \
1744 {"$v31", RTYPE_VEC | 31}
1746 #define MIPS_DSP_ACCUMULATOR_NAMES \
1747 {"$ac0", RTYPE_ACC | 0}, \
1748 {"$ac1", RTYPE_ACC | 1}, \
1749 {"$ac2", RTYPE_ACC | 2}, \
1750 {"$ac3", RTYPE_ACC | 3}
1752 static const struct regname reg_names[] = {
1753 GENERIC_REGISTER_NUMBERS,
1755 FPU_CONDITION_CODE_NAMES,
1756 COPROC_CONDITION_CODE_NAMES,
1758 /* The $txx registers depends on the abi,
1759 these will be added later into the symbol table from
1760 one of the tables below once mips_abi is set after
1761 parsing of arguments from the command line. */
1762 SYMBOLIC_REGISTER_NAMES,
1764 MIPS16_SPECIAL_REGISTER_NAMES,
1765 MDMX_VECTOR_REGISTER_NAMES,
1766 MIPS_DSP_ACCUMULATOR_NAMES,
1770 static const struct regname reg_names_o32[] = {
1771 O32_SYMBOLIC_REGISTER_NAMES,
1775 static const struct regname reg_names_n32n64[] = {
1776 N32N64_SYMBOLIC_REGISTER_NAMES,
1781 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
1788 /* Find end of name. */
1790 if (is_name_beginner (*e))
1792 while (is_part_of_name (*e))
1795 /* Terminate name. */
1799 /* Look for a register symbol. */
1800 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
1802 int r = S_GET_VALUE (symbolP);
1804 reg = r & RNUM_MASK;
1805 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
1806 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
1807 reg = (r & RNUM_MASK) - 2;
1809 /* Else see if this is a register defined in an itbl entry. */
1810 else if ((types & RTYPE_GP) && itbl_have_entries)
1817 if (itbl_get_reg_val (n, &r))
1818 reg = r & RNUM_MASK;
1821 /* Advance to next token if a register was recognised. */
1824 else if (types & RWARN)
1825 as_warn (_("Unrecognized register name `%s'"), *s);
1833 /* Return TRUE if opcode MO is valid on the currently selected ISA and
1834 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
1837 is_opcode_valid (const struct mips_opcode *mo)
1839 int isa = mips_opts.isa;
1842 if (mips_opts.ase_mdmx)
1844 if (mips_opts.ase_dsp)
1846 if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
1848 if (mips_opts.ase_dspr2)
1850 if (mips_opts.ase_mt)
1852 if (mips_opts.ase_mips3d)
1854 if (mips_opts.ase_smartmips)
1855 isa |= INSN_SMARTMIPS;
1857 /* Don't accept instructions based on the ISA if the CPU does not implement
1858 all the coprocessor insns. */
1859 if (NO_ISA_COP (mips_opts.arch)
1860 && COP_INSN (mo->pinfo))
1863 if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch))
1866 /* Check whether the instruction or macro requires single-precision or
1867 double-precision floating-point support. Note that this information is
1868 stored differently in the opcode table for insns and macros. */
1869 if (mo->pinfo == INSN_MACRO)
1871 fp_s = mo->pinfo2 & INSN2_M_FP_S;
1872 fp_d = mo->pinfo2 & INSN2_M_FP_D;
1876 fp_s = mo->pinfo & FP_S;
1877 fp_d = mo->pinfo & FP_D;
1880 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
1883 if (fp_s && mips_opts.soft_float)
1889 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
1890 selected ISA and architecture. */
1893 is_opcode_valid_16 (const struct mips_opcode *mo)
1895 return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE;
1898 /* This function is called once, at assembler startup time. It should set up
1899 all the tables, etc. that the MD part of the assembler will need. */
1904 const char *retval = NULL;
1908 if (mips_pic != NO_PIC)
1910 if (g_switch_seen && g_switch_value != 0)
1911 as_bad (_("-G may not be used in position-independent code"));
1915 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
1916 as_warn (_("Could not set architecture and machine"));
1918 op_hash = hash_new ();
1920 for (i = 0; i < NUMOPCODES;)
1922 const char *name = mips_opcodes[i].name;
1924 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
1927 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1928 mips_opcodes[i].name, retval);
1929 /* Probably a memory allocation problem? Give up now. */
1930 as_fatal (_("Broken assembler. No assembly attempted."));
1934 if (mips_opcodes[i].pinfo != INSN_MACRO)
1936 if (!validate_mips_insn (&mips_opcodes[i]))
1938 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
1940 create_insn (&nop_insn, mips_opcodes + i);
1941 if (mips_fix_loongson2f_nop)
1942 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
1943 nop_insn.fixed_p = 1;
1948 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1951 mips16_op_hash = hash_new ();
1954 while (i < bfd_mips16_num_opcodes)
1956 const char *name = mips16_opcodes[i].name;
1958 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
1960 as_fatal (_("internal: can't hash `%s': %s"),
1961 mips16_opcodes[i].name, retval);
1964 if (mips16_opcodes[i].pinfo != INSN_MACRO
1965 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1966 != mips16_opcodes[i].match))
1968 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1969 mips16_opcodes[i].name, mips16_opcodes[i].args);
1972 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
1974 create_insn (&mips16_nop_insn, mips16_opcodes + i);
1975 mips16_nop_insn.fixed_p = 1;
1979 while (i < bfd_mips16_num_opcodes
1980 && strcmp (mips16_opcodes[i].name, name) == 0);
1984 as_fatal (_("Broken assembler. No assembly attempted."));
1986 /* We add all the general register names to the symbol table. This
1987 helps us detect invalid uses of them. */
1988 for (i = 0; reg_names[i].name; i++)
1989 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
1990 reg_names[i].num, /* & RNUM_MASK, */
1991 &zero_address_frag));
1993 for (i = 0; reg_names_n32n64[i].name; i++)
1994 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
1995 reg_names_n32n64[i].num, /* & RNUM_MASK, */
1996 &zero_address_frag));
1998 for (i = 0; reg_names_o32[i].name; i++)
1999 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
2000 reg_names_o32[i].num, /* & RNUM_MASK, */
2001 &zero_address_frag));
2003 mips_no_prev_insn ();
2006 mips_cprmask[0] = 0;
2007 mips_cprmask[1] = 0;
2008 mips_cprmask[2] = 0;
2009 mips_cprmask[3] = 0;
2011 /* set the default alignment for the text section (2**2) */
2012 record_alignment (text_section, 2);
2014 bfd_set_gp_size (stdoutput, g_switch_value);
2019 /* On a native system other than VxWorks, sections must be aligned
2020 to 16 byte boundaries. When configured for an embedded ELF
2021 target, we don't bother. */
2022 if (strncmp (TARGET_OS, "elf", 3) != 0
2023 && strncmp (TARGET_OS, "vxworks", 7) != 0)
2025 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
2026 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
2027 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
2030 /* Create a .reginfo section for register masks and a .mdebug
2031 section for debugging information. */
2039 subseg = now_subseg;
2041 /* The ABI says this section should be loaded so that the
2042 running program can access it. However, we don't load it
2043 if we are configured for an embedded target */
2044 flags = SEC_READONLY | SEC_DATA;
2045 if (strncmp (TARGET_OS, "elf", 3) != 0)
2046 flags |= SEC_ALLOC | SEC_LOAD;
2048 if (mips_abi != N64_ABI)
2050 sec = subseg_new (".reginfo", (subsegT) 0);
2052 bfd_set_section_flags (stdoutput, sec, flags);
2053 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
2055 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
2059 /* The 64-bit ABI uses a .MIPS.options section rather than
2060 .reginfo section. */
2061 sec = subseg_new (".MIPS.options", (subsegT) 0);
2062 bfd_set_section_flags (stdoutput, sec, flags);
2063 bfd_set_section_alignment (stdoutput, sec, 3);
2065 /* Set up the option header. */
2067 Elf_Internal_Options opthdr;
2070 opthdr.kind = ODK_REGINFO;
2071 opthdr.size = (sizeof (Elf_External_Options)
2072 + sizeof (Elf64_External_RegInfo));
2075 f = frag_more (sizeof (Elf_External_Options));
2076 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2077 (Elf_External_Options *) f);
2079 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2083 if (ECOFF_DEBUGGING)
2085 sec = subseg_new (".mdebug", (subsegT) 0);
2086 (void) bfd_set_section_flags (stdoutput, sec,
2087 SEC_HAS_CONTENTS | SEC_READONLY);
2088 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2090 else if (mips_flag_pdr)
2092 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2093 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2094 SEC_READONLY | SEC_RELOC
2096 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2099 subseg_set (seg, subseg);
2102 #endif /* OBJ_ELF */
2104 if (! ECOFF_DEBUGGING)
2107 if (mips_fix_vr4120)
2108 init_vr4120_conflicts ();
2114 if (! ECOFF_DEBUGGING)
2119 md_assemble (char *str)
2121 struct mips_cl_insn insn;
2122 bfd_reloc_code_real_type unused_reloc[3]
2123 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2125 imm_expr.X_op = O_absent;
2126 imm2_expr.X_op = O_absent;
2127 offset_expr.X_op = O_absent;
2128 imm_reloc[0] = BFD_RELOC_UNUSED;
2129 imm_reloc[1] = BFD_RELOC_UNUSED;
2130 imm_reloc[2] = BFD_RELOC_UNUSED;
2131 offset_reloc[0] = BFD_RELOC_UNUSED;
2132 offset_reloc[1] = BFD_RELOC_UNUSED;
2133 offset_reloc[2] = BFD_RELOC_UNUSED;
2135 if (mips_opts.mips16)
2136 mips16_ip (str, &insn);
2139 mips_ip (str, &insn);
2140 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2141 str, insn.insn_opcode));
2146 as_bad ("%s `%s'", insn_error, str);
2150 if (insn.insn_mo->pinfo == INSN_MACRO)
2153 if (mips_opts.mips16)
2154 mips16_macro (&insn);
2161 if (imm_expr.X_op != O_absent)
2162 append_insn (&insn, &imm_expr, imm_reloc);
2163 else if (offset_expr.X_op != O_absent)
2164 append_insn (&insn, &offset_expr, offset_reloc);
2166 append_insn (&insn, NULL, unused_reloc);
2170 /* Convenience functions for abstracting away the differences between
2171 MIPS16 and non-MIPS16 relocations. */
2173 static inline bfd_boolean
2174 mips16_reloc_p (bfd_reloc_code_real_type reloc)
2178 case BFD_RELOC_MIPS16_JMP:
2179 case BFD_RELOC_MIPS16_GPREL:
2180 case BFD_RELOC_MIPS16_GOT16:
2181 case BFD_RELOC_MIPS16_CALL16:
2182 case BFD_RELOC_MIPS16_HI16_S:
2183 case BFD_RELOC_MIPS16_HI16:
2184 case BFD_RELOC_MIPS16_LO16:
2192 static inline bfd_boolean
2193 got16_reloc_p (bfd_reloc_code_real_type reloc)
2195 return reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16;
2198 static inline bfd_boolean
2199 hi16_reloc_p (bfd_reloc_code_real_type reloc)
2201 return reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S;
2204 static inline bfd_boolean
2205 lo16_reloc_p (bfd_reloc_code_real_type reloc)
2207 return reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16;
2210 /* Return true if the given relocation might need a matching %lo().
2211 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2212 need a matching %lo() when applied to local symbols. */
2214 static inline bfd_boolean
2215 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
2217 return (HAVE_IN_PLACE_ADDENDS
2218 && (hi16_reloc_p (reloc)
2219 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2220 all GOT16 relocations evaluate to "G". */
2221 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
2224 /* Return the type of %lo() reloc needed by RELOC, given that
2225 reloc_needs_lo_p. */
2227 static inline bfd_reloc_code_real_type
2228 matching_lo_reloc (bfd_reloc_code_real_type reloc)
2230 return mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 : BFD_RELOC_LO16;
2233 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2236 static inline bfd_boolean
2237 fixup_has_matching_lo_p (fixS *fixp)
2239 return (fixp->fx_next != NULL
2240 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
2241 && fixp->fx_addsy == fixp->fx_next->fx_addsy
2242 && fixp->fx_offset == fixp->fx_next->fx_offset);
2245 /* See whether instruction IP reads register REG. CLASS is the type
2249 insn_uses_reg (const struct mips_cl_insn *ip, unsigned int reg,
2250 enum mips_regclass regclass)
2252 if (regclass == MIPS16_REG)
2254 gas_assert (mips_opts.mips16);
2255 reg = mips16_to_32_reg_map[reg];
2256 regclass = MIPS_GR_REG;
2259 /* Don't report on general register ZERO, since it never changes. */
2260 if (regclass == MIPS_GR_REG && reg == ZERO)
2263 if (regclass == MIPS_FP_REG)
2265 gas_assert (! mips_opts.mips16);
2266 /* If we are called with either $f0 or $f1, we must check $f0.
2267 This is not optimal, because it will introduce an unnecessary
2268 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
2269 need to distinguish reading both $f0 and $f1 or just one of
2270 them. Note that we don't have to check the other way,
2271 because there is no instruction that sets both $f0 and $f1
2272 and requires a delay. */
2273 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
2274 && ((EXTRACT_OPERAND (FS, *ip) & ~(unsigned) 1)
2275 == (reg &~ (unsigned) 1)))
2277 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
2278 && ((EXTRACT_OPERAND (FT, *ip) & ~(unsigned) 1)
2279 == (reg &~ (unsigned) 1)))
2281 if ((ip->insn_mo->pinfo2 & INSN2_READ_FPR_Z)
2282 && ((EXTRACT_OPERAND (FZ, *ip) & ~(unsigned) 1)
2283 == (reg &~ (unsigned) 1)))
2286 else if (! mips_opts.mips16)
2288 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
2289 && EXTRACT_OPERAND (RS, *ip) == reg)
2291 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
2292 && EXTRACT_OPERAND (RT, *ip) == reg)
2294 if ((ip->insn_mo->pinfo2 & INSN2_READ_GPR_D)
2295 && EXTRACT_OPERAND (RD, *ip) == reg)
2297 if ((ip->insn_mo->pinfo2 & INSN2_READ_GPR_Z)
2298 && EXTRACT_OPERAND (RZ, *ip) == reg)
2303 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
2304 && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)] == reg)
2306 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
2307 && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)] == reg)
2309 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
2310 && (mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]
2313 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
2315 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
2317 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
2319 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
2320 && MIPS16_EXTRACT_OPERAND (REGR32, *ip) == reg)
2327 /* This function returns true if modifying a register requires a
2331 reg_needs_delay (unsigned int reg)
2333 unsigned long prev_pinfo;
2335 prev_pinfo = history[0].insn_mo->pinfo;
2336 if (! mips_opts.noreorder
2337 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2338 && ! gpr_interlocks)
2339 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
2340 && ! cop_interlocks)))
2342 /* A load from a coprocessor or from memory. All load delays
2343 delay the use of general register rt for one instruction. */
2344 /* Itbl support may require additional care here. */
2345 know (prev_pinfo & INSN_WRITE_GPR_T);
2346 if (reg == EXTRACT_OPERAND (RT, history[0]))
2353 /* Move all labels in insn_labels to the current insertion point. */
2356 mips_move_labels (void)
2358 segment_info_type *si = seg_info (now_seg);
2359 struct insn_label_list *l;
2362 for (l = si->label_list; l != NULL; l = l->next)
2364 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
2365 symbol_set_frag (l->label, frag_now);
2366 val = (valueT) frag_now_fix ();
2367 /* mips16 text labels are stored as odd. */
2368 if (mips_opts.mips16)
2370 S_SET_VALUE (l->label, val);
2375 s_is_linkonce (symbolS *sym, segT from_seg)
2377 bfd_boolean linkonce = FALSE;
2378 segT symseg = S_GET_SEGMENT (sym);
2380 if (symseg != from_seg && !S_IS_LOCAL (sym))
2382 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
2385 /* The GNU toolchain uses an extension for ELF: a section
2386 beginning with the magic string .gnu.linkonce is a
2387 linkonce section. */
2388 if (strncmp (segment_name (symseg), ".gnu.linkonce",
2389 sizeof ".gnu.linkonce" - 1) == 0)
2396 /* Mark instruction labels in mips16 mode. This permits the linker to
2397 handle them specially, such as generating jalx instructions when
2398 needed. We also make them odd for the duration of the assembly, in
2399 order to generate the right sort of code. We will make them even
2400 in the adjust_symtab routine, while leaving them marked. This is
2401 convenient for the debugger and the disassembler. The linker knows
2402 to make them odd again. */
2405 mips16_mark_labels (void)
2407 segment_info_type *si = seg_info (now_seg);
2408 struct insn_label_list *l;
2410 if (!mips_opts.mips16)
2413 for (l = si->label_list; l != NULL; l = l->next)
2415 symbolS *label = l->label;
2417 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2419 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
2421 if ((S_GET_VALUE (label) & 1) == 0
2422 /* Don't adjust the address if the label is global or weak, or
2423 in a link-once section, since we'll be emitting symbol reloc
2424 references to it which will be patched up by the linker, and
2425 the final value of the symbol may or may not be MIPS16. */
2426 && ! S_IS_WEAK (label)
2427 && ! S_IS_EXTERNAL (label)
2428 && ! s_is_linkonce (label, now_seg))
2429 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
2433 /* End the current frag. Make it a variant frag and record the
2437 relax_close_frag (void)
2439 mips_macro_warning.first_frag = frag_now;
2440 frag_var (rs_machine_dependent, 0, 0,
2441 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
2442 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
2444 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
2445 mips_relax.first_fixup = 0;
2448 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2449 See the comment above RELAX_ENCODE for more details. */
2452 relax_start (symbolS *symbol)
2454 gas_assert (mips_relax.sequence == 0);
2455 mips_relax.sequence = 1;
2456 mips_relax.symbol = symbol;
2459 /* Start generating the second version of a relaxable sequence.
2460 See the comment above RELAX_ENCODE for more details. */
2465 gas_assert (mips_relax.sequence == 1);
2466 mips_relax.sequence = 2;
2469 /* End the current relaxable sequence. */
2474 gas_assert (mips_relax.sequence == 2);
2475 relax_close_frag ();
2476 mips_relax.sequence = 0;
2479 /* Classify an instruction according to the FIX_VR4120_* enumeration.
2480 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
2481 by VR4120 errata. */
2484 classify_vr4120_insn (const char *name)
2486 if (strncmp (name, "macc", 4) == 0)
2487 return FIX_VR4120_MACC;
2488 if (strncmp (name, "dmacc", 5) == 0)
2489 return FIX_VR4120_DMACC;
2490 if (strncmp (name, "mult", 4) == 0)
2491 return FIX_VR4120_MULT;
2492 if (strncmp (name, "dmult", 5) == 0)
2493 return FIX_VR4120_DMULT;
2494 if (strstr (name, "div"))
2495 return FIX_VR4120_DIV;
2496 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
2497 return FIX_VR4120_MTHILO;
2498 return NUM_FIX_VR4120_CLASSES;
2501 #define INSN_ERET 0x42000018
2502 #define INSN_DERET 0x4200001f
2504 /* Return the number of instructions that must separate INSN1 and INSN2,
2505 where INSN1 is the earlier instruction. Return the worst-case value
2506 for any INSN2 if INSN2 is null. */
2509 insns_between (const struct mips_cl_insn *insn1,
2510 const struct mips_cl_insn *insn2)
2512 unsigned long pinfo1, pinfo2;
2514 /* This function needs to know which pinfo flags are set for INSN2
2515 and which registers INSN2 uses. The former is stored in PINFO2 and
2516 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
2517 will have every flag set and INSN2_USES_REG will always return true. */
2518 pinfo1 = insn1->insn_mo->pinfo;
2519 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
2521 #define INSN2_USES_REG(REG, CLASS) \
2522 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
2524 /* For most targets, write-after-read dependencies on the HI and LO
2525 registers must be separated by at least two instructions. */
2526 if (!hilo_interlocks)
2528 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
2530 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
2534 /* If we're working around r7000 errata, there must be two instructions
2535 between an mfhi or mflo and any instruction that uses the result. */
2536 if (mips_7000_hilo_fix
2537 && MF_HILO_INSN (pinfo1)
2538 && INSN2_USES_REG (EXTRACT_OPERAND (RD, *insn1), MIPS_GR_REG))
2541 /* If we're working around 24K errata, one instruction is required
2542 if an ERET or DERET is followed by a branch instruction. */
2545 if (insn1->insn_opcode == INSN_ERET
2546 || insn1->insn_opcode == INSN_DERET)
2549 || insn2->insn_opcode == INSN_ERET
2550 || insn2->insn_opcode == INSN_DERET
2551 || (insn2->insn_mo->pinfo
2552 & (INSN_UNCOND_BRANCH_DELAY
2553 | INSN_COND_BRANCH_DELAY
2554 | INSN_COND_BRANCH_LIKELY)) != 0)
2559 /* If working around VR4120 errata, check for combinations that need
2560 a single intervening instruction. */
2561 if (mips_fix_vr4120)
2563 unsigned int class1, class2;
2565 class1 = classify_vr4120_insn (insn1->insn_mo->name);
2566 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
2570 class2 = classify_vr4120_insn (insn2->insn_mo->name);
2571 if (vr4120_conflicts[class1] & (1 << class2))
2576 if (!mips_opts.mips16)
2578 /* Check for GPR or coprocessor load delays. All such delays
2579 are on the RT register. */
2580 /* Itbl support may require additional care here. */
2581 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
2582 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
2584 know (pinfo1 & INSN_WRITE_GPR_T);
2585 if (INSN2_USES_REG (EXTRACT_OPERAND (RT, *insn1), MIPS_GR_REG))
2589 /* Check for generic coprocessor hazards.
2591 This case is not handled very well. There is no special
2592 knowledge of CP0 handling, and the coprocessors other than
2593 the floating point unit are not distinguished at all. */
2594 /* Itbl support may require additional care here. FIXME!
2595 Need to modify this to include knowledge about
2596 user specified delays! */
2597 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
2598 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
2600 /* Handle cases where INSN1 writes to a known general coprocessor
2601 register. There must be a one instruction delay before INSN2
2602 if INSN2 reads that register, otherwise no delay is needed. */
2603 if (pinfo1 & INSN_WRITE_FPR_T)
2605 if (INSN2_USES_REG (EXTRACT_OPERAND (FT, *insn1), MIPS_FP_REG))
2608 else if (pinfo1 & INSN_WRITE_FPR_S)
2610 if (INSN2_USES_REG (EXTRACT_OPERAND (FS, *insn1), MIPS_FP_REG))
2615 /* Read-after-write dependencies on the control registers
2616 require a two-instruction gap. */
2617 if ((pinfo1 & INSN_WRITE_COND_CODE)
2618 && (pinfo2 & INSN_READ_COND_CODE))
2621 /* We don't know exactly what INSN1 does. If INSN2 is
2622 also a coprocessor instruction, assume there must be
2623 a one instruction gap. */
2624 if (pinfo2 & INSN_COP)
2629 /* Check for read-after-write dependencies on the coprocessor
2630 control registers in cases where INSN1 does not need a general
2631 coprocessor delay. This means that INSN1 is a floating point
2632 comparison instruction. */
2633 /* Itbl support may require additional care here. */
2634 else if (!cop_interlocks
2635 && (pinfo1 & INSN_WRITE_COND_CODE)
2636 && (pinfo2 & INSN_READ_COND_CODE))
2640 #undef INSN2_USES_REG
2645 /* Return the number of nops that would be needed to work around the
2646 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2647 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
2648 that are contained within the first IGNORE instructions of HIST. */
2651 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
2652 const struct mips_cl_insn *insn)
2656 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2657 are not affected by the errata. */
2659 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
2660 || strcmp (insn->insn_mo->name, "mtlo") == 0
2661 || strcmp (insn->insn_mo->name, "mthi") == 0))
2664 /* Search for the first MFLO or MFHI. */
2665 for (i = 0; i < MAX_VR4130_NOPS; i++)
2666 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
2668 /* Extract the destination register. */
2669 if (mips_opts.mips16)
2670 reg = mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, hist[i])];
2672 reg = EXTRACT_OPERAND (RD, hist[i]);
2674 /* No nops are needed if INSN reads that register. */
2675 if (insn != NULL && insn_uses_reg (insn, reg, MIPS_GR_REG))
2678 /* ...or if any of the intervening instructions do. */
2679 for (j = 0; j < i; j++)
2680 if (insn_uses_reg (&hist[j], reg, MIPS_GR_REG))
2684 return MAX_VR4130_NOPS - i;
2689 #define BASE_REG_EQ(INSN1, INSN2) \
2690 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
2691 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
2693 /* Return the minimum alignment for this store instruction. */
2696 fix_24k_align_to (const struct mips_opcode *mo)
2698 if (strcmp (mo->name, "sh") == 0)
2701 if (strcmp (mo->name, "swc1") == 0
2702 || strcmp (mo->name, "swc2") == 0
2703 || strcmp (mo->name, "sw") == 0
2704 || strcmp (mo->name, "sc") == 0
2705 || strcmp (mo->name, "s.s") == 0)
2708 if (strcmp (mo->name, "sdc1") == 0
2709 || strcmp (mo->name, "sdc2") == 0
2710 || strcmp (mo->name, "s.d") == 0)
2717 struct fix_24k_store_info
2719 /* Immediate offset, if any, for this store instruction. */
2721 /* Alignment required by this store instruction. */
2723 /* True for register offsets. */
2724 int register_offset;
2727 /* Comparison function used by qsort. */
2730 fix_24k_sort (const void *a, const void *b)
2732 const struct fix_24k_store_info *pos1 = a;
2733 const struct fix_24k_store_info *pos2 = b;
2735 return (pos1->off - pos2->off);
2738 /* INSN is a store instruction. Try to record the store information
2739 in STINFO. Return false if the information isn't known. */
2742 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
2743 const struct mips_cl_insn *insn)
2745 /* The instruction must have a known offset. */
2746 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
2749 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
2750 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
2754 /* Return the number of nops that would be needed to work around the 24k
2755 "lost data on stores during refill" errata if instruction INSN
2756 immediately followed the 2 instructions described by HIST.
2757 Ignore hazards that are contained within the first IGNORE
2758 instructions of HIST.
2760 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
2761 for the data cache refills and store data. The following describes
2762 the scenario where the store data could be lost.
2764 * A data cache miss, due to either a load or a store, causing fill
2765 data to be supplied by the memory subsystem
2766 * The first three doublewords of fill data are returned and written
2768 * A sequence of four stores occurs in consecutive cycles around the
2769 final doubleword of the fill:
2773 * Zero, One or more instructions
2776 The four stores A-D must be to different doublewords of the line that
2777 is being filled. The fourth instruction in the sequence above permits
2778 the fill of the final doubleword to be transferred from the FSB into
2779 the cache. In the sequence above, the stores may be either integer
2780 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
2781 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
2782 different doublewords on the line. If the floating point unit is
2783 running in 1:2 mode, it is not possible to create the sequence above
2784 using only floating point store instructions.
2786 In this case, the cache line being filled is incorrectly marked
2787 invalid, thereby losing the data from any store to the line that
2788 occurs between the original miss and the completion of the five
2789 cycle sequence shown above.
2791 The workarounds are:
2793 * Run the data cache in write-through mode.
2794 * Insert a non-store instruction between
2795 Store A and Store B or Store B and Store C. */
2798 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
2799 const struct mips_cl_insn *insn)
2801 struct fix_24k_store_info pos[3];
2802 int align, i, base_offset;
2807 /* If the previous instruction wasn't a store, there's nothing to
2809 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
2812 /* If the instructions after the previous one are unknown, we have
2813 to assume the worst. */
2817 /* Check whether we are dealing with three consecutive stores. */
2818 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
2819 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
2822 /* If we don't know the relationship between the store addresses,
2823 assume the worst. */
2824 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
2825 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
2828 if (!fix_24k_record_store_info (&pos[0], insn)
2829 || !fix_24k_record_store_info (&pos[1], &hist[0])
2830 || !fix_24k_record_store_info (&pos[2], &hist[1]))
2833 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
2835 /* Pick a value of ALIGN and X such that all offsets are adjusted by
2836 X bytes and such that the base register + X is known to be aligned
2839 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
2843 align = pos[0].align_to;
2844 base_offset = pos[0].off;
2845 for (i = 1; i < 3; i++)
2846 if (align < pos[i].align_to)
2848 align = pos[i].align_to;
2849 base_offset = pos[i].off;
2851 for (i = 0; i < 3; i++)
2852 pos[i].off -= base_offset;
2855 pos[0].off &= ~align + 1;
2856 pos[1].off &= ~align + 1;
2857 pos[2].off &= ~align + 1;
2859 /* If any two stores write to the same chunk, they also write to the
2860 same doubleword. The offsets are still sorted at this point. */
2861 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
2864 /* A range of at least 9 bytes is needed for the stores to be in
2865 non-overlapping doublewords. */
2866 if (pos[2].off - pos[0].off <= 8)
2869 if (pos[2].off - pos[1].off >= 24
2870 || pos[1].off - pos[0].off >= 24
2871 || pos[2].off - pos[0].off >= 32)
2877 /* Return the number of nops that would be needed if instruction INSN
2878 immediately followed the MAX_NOPS instructions given by HIST,
2879 where HIST[0] is the most recent instruction. Ignore hazards
2880 between INSN and the first IGNORE instructions in HIST.
2882 If INSN is null, return the worse-case number of nops for any
2886 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
2887 const struct mips_cl_insn *insn)
2889 int i, nops, tmp_nops;
2892 for (i = ignore; i < MAX_DELAY_NOPS; i++)
2894 tmp_nops = insns_between (hist + i, insn) - i;
2895 if (tmp_nops > nops)
2899 if (mips_fix_vr4130)
2901 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
2902 if (tmp_nops > nops)
2908 tmp_nops = nops_for_24k (ignore, hist, insn);
2909 if (tmp_nops > nops)
2916 /* The variable arguments provide NUM_INSNS extra instructions that
2917 might be added to HIST. Return the largest number of nops that
2918 would be needed after the extended sequence, ignoring hazards
2919 in the first IGNORE instructions. */
2922 nops_for_sequence (int num_insns, int ignore,
2923 const struct mips_cl_insn *hist, ...)
2926 struct mips_cl_insn buffer[MAX_NOPS];
2927 struct mips_cl_insn *cursor;
2930 va_start (args, hist);
2931 cursor = buffer + num_insns;
2932 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
2933 while (cursor > buffer)
2934 *--cursor = *va_arg (args, const struct mips_cl_insn *);
2936 nops = nops_for_insn (ignore, buffer, NULL);
2941 /* Like nops_for_insn, but if INSN is a branch, take into account the
2942 worst-case delay for the branch target. */
2945 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
2946 const struct mips_cl_insn *insn)
2950 nops = nops_for_insn (ignore, hist, insn);
2951 if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
2952 | INSN_COND_BRANCH_DELAY
2953 | INSN_COND_BRANCH_LIKELY))
2955 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
2956 hist, insn, NOP_INSN);
2957 if (tmp_nops > nops)
2960 else if (mips_opts.mips16
2961 && (insn->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
2962 | MIPS16_INSN_COND_BRANCH)))
2964 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
2965 if (tmp_nops > nops)
2971 /* Fix NOP issue: Replace nops by "or at,at,zero". */
2974 fix_loongson2f_nop (struct mips_cl_insn * ip)
2976 if (strcmp (ip->insn_mo->name, "nop") == 0)
2977 ip->insn_opcode = LOONGSON2F_NOP_INSN;
2980 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
2981 jr target pc &= 'hffff_ffff_cfff_ffff. */
2984 fix_loongson2f_jump (struct mips_cl_insn * ip)
2986 if (strcmp (ip->insn_mo->name, "j") == 0
2987 || strcmp (ip->insn_mo->name, "jr") == 0
2988 || strcmp (ip->insn_mo->name, "jalr") == 0)
2996 sreg = EXTRACT_OPERAND (RS, *ip);
2997 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
3000 ep.X_op = O_constant;
3001 ep.X_add_number = 0xcfff0000;
3002 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
3003 ep.X_add_number = 0xffff;
3004 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
3005 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
3010 fix_loongson2f (struct mips_cl_insn * ip)
3012 if (mips_fix_loongson2f_nop)
3013 fix_loongson2f_nop (ip);
3015 if (mips_fix_loongson2f_jump)
3016 fix_loongson2f_jump (ip);
3019 /* Output an instruction. IP is the instruction information.
3020 ADDRESS_EXPR is an operand of the instruction to be used with
3024 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
3025 bfd_reloc_code_real_type *reloc_type)
3027 unsigned long prev_pinfo, pinfo;
3028 unsigned long prev_pinfo2, pinfo2;
3029 relax_stateT prev_insn_frag_type = 0;
3030 bfd_boolean relaxed_branch = FALSE;
3031 segment_info_type *si = seg_info (now_seg);
3033 if (mips_fix_loongson2f)
3034 fix_loongson2f (ip);
3036 /* Mark instruction labels in mips16 mode. */
3037 mips16_mark_labels ();
3039 file_ase_mips16 |= mips_opts.mips16;
3041 prev_pinfo = history[0].insn_mo->pinfo;
3042 prev_pinfo2 = history[0].insn_mo->pinfo2;
3043 pinfo = ip->insn_mo->pinfo;
3044 pinfo2 = ip->insn_mo->pinfo2;
3046 if (address_expr == NULL)
3048 else if (*reloc_type <= BFD_RELOC_UNUSED
3049 && address_expr->X_op == O_constant)
3054 switch (*reloc_type)
3057 ip->insn_opcode |= address_expr->X_add_number;
3060 case BFD_RELOC_MIPS_HIGHEST:
3061 tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48;
3062 ip->insn_opcode |= tmp & 0xffff;
3065 case BFD_RELOC_MIPS_HIGHER:
3066 tmp = (address_expr->X_add_number + 0x80008000ull) >> 32;
3067 ip->insn_opcode |= tmp & 0xffff;
3070 case BFD_RELOC_HI16_S:
3071 tmp = (address_expr->X_add_number + 0x8000) >> 16;
3072 ip->insn_opcode |= tmp & 0xffff;
3075 case BFD_RELOC_HI16:
3076 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
3079 case BFD_RELOC_UNUSED:
3080 case BFD_RELOC_LO16:
3081 case BFD_RELOC_MIPS_GOT_DISP:
3082 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
3085 case BFD_RELOC_MIPS_JMP:
3086 if ((address_expr->X_add_number & 3) != 0)
3087 as_bad (_("jump to misaligned address (0x%lx)"),
3088 (unsigned long) address_expr->X_add_number);
3089 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
3093 case BFD_RELOC_MIPS16_JMP:
3094 if ((address_expr->X_add_number & 3) != 0)
3095 as_bad (_("jump to misaligned address (0x%lx)"),
3096 (unsigned long) address_expr->X_add_number);
3098 (((address_expr->X_add_number & 0x7c0000) << 3)
3099 | ((address_expr->X_add_number & 0xf800000) >> 7)
3100 | ((address_expr->X_add_number & 0x3fffc) >> 2));
3104 case BFD_RELOC_16_PCREL_S2:
3105 if ((address_expr->X_add_number & 3) != 0)
3106 as_bad (_("branch to misaligned address (0x%lx)"),
3107 (unsigned long) address_expr->X_add_number);
3108 if (mips_relax_branch)
3110 if ((address_expr->X_add_number + 0x20000) & ~0x3ffff)
3111 as_bad (_("branch address range overflow (0x%lx)"),
3112 (unsigned long) address_expr->X_add_number);
3113 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff;
3122 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
3124 /* There are a lot of optimizations we could do that we don't.
3125 In particular, we do not, in general, reorder instructions.
3126 If you use gcc with optimization, it will reorder
3127 instructions and generally do much more optimization then we
3128 do here; repeating all that work in the assembler would only
3129 benefit hand written assembly code, and does not seem worth
3131 int nops = (mips_optimize == 0
3132 ? nops_for_insn (0, history, NULL)
3133 : nops_for_insn_or_target (0, history, ip));
3137 unsigned long old_frag_offset;
3140 old_frag = frag_now;
3141 old_frag_offset = frag_now_fix ();
3143 for (i = 0; i < nops; i++)
3148 listing_prev_line ();
3149 /* We may be at the start of a variant frag. In case we
3150 are, make sure there is enough space for the frag
3151 after the frags created by listing_prev_line. The
3152 argument to frag_grow here must be at least as large
3153 as the argument to all other calls to frag_grow in
3154 this file. We don't have to worry about being in the
3155 middle of a variant frag, because the variants insert
3156 all needed nop instructions themselves. */
3160 mips_move_labels ();
3162 #ifndef NO_ECOFF_DEBUGGING
3163 if (ECOFF_DEBUGGING)
3164 ecoff_fix_loc (old_frag, old_frag_offset);
3168 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
3172 /* Work out how many nops in prev_nop_frag are needed by IP,
3173 ignoring hazards generated by the first prev_nop_frag_since
3175 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
3176 gas_assert (nops <= prev_nop_frag_holds);
3178 /* Enforce NOPS as a minimum. */
3179 if (nops > prev_nop_frag_required)
3180 prev_nop_frag_required = nops;
3182 if (prev_nop_frag_holds == prev_nop_frag_required)
3184 /* Settle for the current number of nops. Update the history
3185 accordingly (for the benefit of any future .set reorder code). */
3186 prev_nop_frag = NULL;
3187 insert_into_history (prev_nop_frag_since,
3188 prev_nop_frag_holds, NOP_INSN);
3192 /* Allow this instruction to replace one of the nops that was
3193 tentatively added to prev_nop_frag. */
3194 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
3195 prev_nop_frag_holds--;
3196 prev_nop_frag_since++;
3201 /* The value passed to dwarf2_emit_insn is the distance between
3202 the beginning of the current instruction and the address that
3203 should be recorded in the debug tables. For MIPS16 debug info
3204 we want to use ISA-encoded addresses, so we pass -1 for an
3205 address higher by one than the current. */
3206 dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0);
3209 /* Record the frag type before frag_var. */
3210 if (history[0].frag)
3211 prev_insn_frag_type = history[0].frag->fr_type;
3214 && *reloc_type == BFD_RELOC_16_PCREL_S2
3215 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
3216 || pinfo & INSN_COND_BRANCH_LIKELY)
3217 && mips_relax_branch
3218 /* Don't try branch relaxation within .set nomacro, or within
3219 .set noat if we use $at for PIC computations. If it turns
3220 out that the branch was out-of-range, we'll get an error. */
3221 && !mips_opts.warn_about_macros
3222 && (mips_opts.at || mips_pic == NO_PIC)
3223 /* Don't relax BPOSGE32/64 as they have no complementing branches. */
3224 && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP))
3225 && !mips_opts.mips16)
3227 relaxed_branch = TRUE;
3228 add_relaxed_insn (ip, (relaxed_branch_length
3230 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
3231 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1
3235 pinfo & INSN_UNCOND_BRANCH_DELAY,
3236 pinfo & INSN_COND_BRANCH_LIKELY,
3237 pinfo & INSN_WRITE_GPR_31,
3239 address_expr->X_add_symbol,
3240 address_expr->X_add_number);
3241 *reloc_type = BFD_RELOC_UNUSED;
3243 else if (*reloc_type > BFD_RELOC_UNUSED)
3245 /* We need to set up a variant frag. */
3246 gas_assert (mips_opts.mips16 && address_expr != NULL);
3247 add_relaxed_insn (ip, 4, 0,
3249 (*reloc_type - BFD_RELOC_UNUSED,
3250 mips16_small, mips16_ext,
3251 prev_pinfo & INSN_UNCOND_BRANCH_DELAY,
3252 history[0].mips16_absolute_jump_p),
3253 make_expr_symbol (address_expr), 0);
3255 else if (mips_opts.mips16
3257 && *reloc_type != BFD_RELOC_MIPS16_JMP)
3259 if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0)
3260 /* Make sure there is enough room to swap this instruction with
3261 a following jump instruction. */
3263 add_fixed_insn (ip);
3267 if (mips_opts.mips16
3268 && mips_opts.noreorder
3269 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
3270 as_warn (_("extended instruction in delay slot"));
3272 if (mips_relax.sequence)
3274 /* If we've reached the end of this frag, turn it into a variant
3275 frag and record the information for the instructions we've
3277 if (frag_room () < 4)
3278 relax_close_frag ();
3279 mips_relax.sizes[mips_relax.sequence - 1] += 4;
3282 if (mips_relax.sequence != 2)
3283 mips_macro_warning.sizes[0] += 4;
3284 if (mips_relax.sequence != 1)
3285 mips_macro_warning.sizes[1] += 4;
3287 if (mips_opts.mips16)
3290 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
3292 add_fixed_insn (ip);
3295 if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED)
3298 && *reloc_type < BFD_RELOC_UNUSED)
3301 reloc_howto_type *howto;
3304 /* In a compound relocation, it is the final (outermost)
3305 operator that determines the relocated field. */
3306 for (i = 1; i < 3; i++)
3307 if (reloc_type[i] == BFD_RELOC_UNUSED)
3310 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
3313 /* To reproduce this failure try assembling gas/testsuites/
3314 gas/mips/mips16-intermix.s with a mips-ecoff targeted
3316 as_bad (_("Unsupported MIPS relocation number %d"), reloc_type[i - 1]);
3317 howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16);
3320 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
3321 bfd_get_reloc_size (howto),
3323 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
3326 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
3327 if (reloc_type[0] == BFD_RELOC_MIPS16_JMP
3328 && ip->fixp[0]->fx_addsy)
3329 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
3331 /* These relocations can have an addend that won't fit in
3332 4 octets for 64bit assembly. */
3334 && ! howto->partial_inplace
3335 && (reloc_type[0] == BFD_RELOC_16
3336 || reloc_type[0] == BFD_RELOC_32
3337 || reloc_type[0] == BFD_RELOC_MIPS_JMP
3338 || reloc_type[0] == BFD_RELOC_GPREL16
3339 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
3340 || reloc_type[0] == BFD_RELOC_GPREL32
3341 || reloc_type[0] == BFD_RELOC_64
3342 || reloc_type[0] == BFD_RELOC_CTOR
3343 || reloc_type[0] == BFD_RELOC_MIPS_SUB
3344 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
3345 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
3346 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
3347 || reloc_type[0] == BFD_RELOC_MIPS_REL16
3348 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
3349 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
3350 || hi16_reloc_p (reloc_type[0])
3351 || lo16_reloc_p (reloc_type[0])))
3352 ip->fixp[0]->fx_no_overflow = 1;
3354 if (mips_relax.sequence)
3356 if (mips_relax.first_fixup == 0)
3357 mips_relax.first_fixup = ip->fixp[0];
3359 else if (reloc_needs_lo_p (*reloc_type))
3361 struct mips_hi_fixup *hi_fixup;
3363 /* Reuse the last entry if it already has a matching %lo. */
3364 hi_fixup = mips_hi_fixup_list;
3366 || !fixup_has_matching_lo_p (hi_fixup->fixp))
3368 hi_fixup = ((struct mips_hi_fixup *)
3369 xmalloc (sizeof (struct mips_hi_fixup)));
3370 hi_fixup->next = mips_hi_fixup_list;
3371 mips_hi_fixup_list = hi_fixup;
3373 hi_fixup->fixp = ip->fixp[0];
3374 hi_fixup->seg = now_seg;
3377 /* Add fixups for the second and third relocations, if given.
3378 Note that the ABI allows the second relocation to be
3379 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
3380 moment we only use RSS_UNDEF, but we could add support
3381 for the others if it ever becomes necessary. */
3382 for (i = 1; i < 3; i++)
3383 if (reloc_type[i] != BFD_RELOC_UNUSED)
3385 ip->fixp[i] = fix_new (ip->frag, ip->where,
3386 ip->fixp[0]->fx_size, NULL, 0,
3387 FALSE, reloc_type[i]);
3389 /* Use fx_tcbit to mark compound relocs. */
3390 ip->fixp[0]->fx_tcbit = 1;
3391 ip->fixp[i]->fx_tcbit = 1;
3397 /* Update the register mask information. */
3398 if (! mips_opts.mips16)
3400 if ((pinfo & INSN_WRITE_GPR_D) || (pinfo2 & INSN2_READ_GPR_D))
3401 mips_gprmask |= 1 << EXTRACT_OPERAND (RD, *ip);
3402 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
3403 mips_gprmask |= 1 << EXTRACT_OPERAND (RT, *ip);
3404 if (pinfo & INSN_READ_GPR_S)
3405 mips_gprmask |= 1 << EXTRACT_OPERAND (RS, *ip);
3406 if (pinfo & INSN_WRITE_GPR_31)
3407 mips_gprmask |= 1 << RA;
3408 if (pinfo2 & (INSN2_WRITE_GPR_Z | INSN2_READ_GPR_Z))
3409 mips_gprmask |= 1 << EXTRACT_OPERAND (RZ, *ip);
3410 if (pinfo & INSN_WRITE_FPR_D)
3411 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FD, *ip);
3412 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
3413 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FS, *ip);
3414 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
3415 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FT, *ip);
3416 if ((pinfo & INSN_READ_FPR_R) != 0)
3417 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FR, *ip);
3418 if (pinfo2 & (INSN2_WRITE_FPR_Z | INSN2_READ_FPR_Z))
3419 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FZ, *ip);
3420 if (pinfo & INSN_COP)
3422 /* We don't keep enough information to sort these cases out.
3423 The itbl support does keep this information however, although
3424 we currently don't support itbl fprmats as part of the cop
3425 instruction. May want to add this support in the future. */
3427 /* Never set the bit for $0, which is always zero. */
3428 mips_gprmask &= ~1 << 0;
3432 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
3433 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RX, *ip);
3434 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
3435 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RY, *ip);
3436 if (pinfo & MIPS16_INSN_WRITE_Z)
3437 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RZ, *ip);
3438 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
3439 mips_gprmask |= 1 << TREG;
3440 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
3441 mips_gprmask |= 1 << SP;
3442 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
3443 mips_gprmask |= 1 << RA;
3444 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
3445 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
3446 if (pinfo & MIPS16_INSN_READ_Z)
3447 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip);
3448 if (pinfo & MIPS16_INSN_READ_GPR_X)
3449 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
3452 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
3454 /* Filling the branch delay slot is more complex. We try to
3455 switch the branch with the previous instruction, which we can
3456 do if the previous instruction does not set up a condition
3457 that the branch tests and if the branch is not itself the
3458 target of any branch. */
3459 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
3460 || (pinfo & INSN_COND_BRANCH_DELAY))
3462 if (mips_optimize < 2
3463 /* If we have seen .set volatile or .set nomove, don't
3465 || mips_opts.nomove != 0
3466 /* We can't swap if the previous instruction's position
3468 || history[0].fixed_p
3469 /* If the previous previous insn was in a .set
3470 noreorder, we can't swap. Actually, the MIPS
3471 assembler will swap in this situation. However, gcc
3472 configured -with-gnu-as will generate code like
3478 in which we can not swap the bne and INSN. If gcc is
3479 not configured -with-gnu-as, it does not output the
3481 || history[1].noreorder_p
3482 /* If the branch is itself the target of a branch, we
3483 can not swap. We cheat on this; all we check for is
3484 whether there is a label on this instruction. If
3485 there are any branches to anything other than a
3486 label, users must use .set noreorder. */
3487 || si->label_list != NULL
3488 /* If the previous instruction is in a variant frag
3489 other than this branch's one, we cannot do the swap.
3490 This does not apply to the mips16, which uses variant
3491 frags for different purposes. */
3492 || (! mips_opts.mips16
3493 && prev_insn_frag_type == rs_machine_dependent)
3494 /* Check for conflicts between the branch and the instructions
3495 before the candidate delay slot. */
3496 || nops_for_insn (0, history + 1, ip) > 0
3497 /* Check for conflicts between the swapped sequence and the
3498 target of the branch. */
3499 || nops_for_sequence (2, 0, history + 1, ip, history) > 0
3500 /* We do not swap with a trap instruction, since it
3501 complicates trap handlers to have the trap
3502 instruction be in a delay slot. */
3503 || (prev_pinfo & INSN_TRAP)
3504 /* If the branch reads a register that the previous
3505 instruction sets, we can not swap. */
3506 || (! mips_opts.mips16
3507 && (prev_pinfo & INSN_WRITE_GPR_T)
3508 && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]),
3510 || (! mips_opts.mips16
3511 && (prev_pinfo & INSN_WRITE_GPR_D)
3512 && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]),
3514 || (! mips_opts.mips16
3515 && (prev_pinfo2 & INSN2_WRITE_GPR_Z)
3516 && insn_uses_reg (ip, EXTRACT_OPERAND (RZ, history[0]),
3518 || (mips_opts.mips16
3519 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
3521 (ip, MIPS16_EXTRACT_OPERAND (RX, history[0]),
3523 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
3525 (ip, MIPS16_EXTRACT_OPERAND (RY, history[0]),
3527 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
3529 (ip, MIPS16_EXTRACT_OPERAND (RZ, history[0]),
3531 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
3532 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
3533 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
3534 && insn_uses_reg (ip, RA, MIPS_GR_REG))
3535 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
3536 && insn_uses_reg (ip,
3537 MIPS16OP_EXTRACT_REG32R
3538 (history[0].insn_opcode),
3540 /* If the branch writes a register that the previous
3541 instruction sets, we can not swap (we know that
3542 branches write only to RD or to $31). */
3543 || (! mips_opts.mips16
3544 && (prev_pinfo & INSN_WRITE_GPR_T)
3545 && (((pinfo & INSN_WRITE_GPR_D)
3546 && (EXTRACT_OPERAND (RT, history[0])
3547 == EXTRACT_OPERAND (RD, *ip)))
3548 || ((pinfo & INSN_WRITE_GPR_31)
3549 && EXTRACT_OPERAND (RT, history[0]) == RA)))
3550 || (! mips_opts.mips16
3551 && (prev_pinfo & INSN_WRITE_GPR_D)
3552 && (((pinfo & INSN_WRITE_GPR_D)
3553 && (EXTRACT_OPERAND (RD, history[0])
3554 == EXTRACT_OPERAND (RD, *ip)))
3555 || ((pinfo & INSN_WRITE_GPR_31)
3556 && EXTRACT_OPERAND (RD, history[0]) == RA)))
3557 || (mips_opts.mips16
3558 && (pinfo & MIPS16_INSN_WRITE_31)
3559 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
3560 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
3561 && (MIPS16OP_EXTRACT_REG32R (history[0].insn_opcode)
3563 /* If the branch writes a register that the previous
3564 instruction reads, we can not swap (we know that
3565 branches only write to RD or to $31). */
3566 || (! mips_opts.mips16
3567 && (pinfo & INSN_WRITE_GPR_D)
3568 && insn_uses_reg (&history[0],
3569 EXTRACT_OPERAND (RD, *ip),
3571 || (! mips_opts.mips16
3572 && (pinfo & INSN_WRITE_GPR_31)
3573 && insn_uses_reg (&history[0], RA, MIPS_GR_REG))
3574 || (mips_opts.mips16
3575 && (pinfo & MIPS16_INSN_WRITE_31)
3576 && insn_uses_reg (&history[0], RA, MIPS_GR_REG))
3577 /* If one instruction sets a condition code and the
3578 other one uses a condition code, we can not swap. */
3579 || ((pinfo & INSN_READ_COND_CODE)
3580 && (prev_pinfo & INSN_WRITE_COND_CODE))
3581 || ((pinfo & INSN_WRITE_COND_CODE)
3582 && (prev_pinfo & INSN_READ_COND_CODE))
3583 /* If the previous instruction uses the PC, we can not
3585 || (mips_opts.mips16
3586 && (prev_pinfo & MIPS16_INSN_READ_PC))
3587 /* If the previous instruction had a fixup in mips16
3588 mode, we can not swap. This normally means that the
3589 previous instruction was a 4 byte branch anyhow. */
3590 || (mips_opts.mips16 && history[0].fixp[0])
3591 /* If the previous instruction is a sync, sync.l, or
3592 sync.p, we can not swap. */
3593 || (prev_pinfo & INSN_SYNC)
3594 /* If the previous instruction is an ERET or
3595 DERET, avoid the swap. */
3596 || (history[0].insn_opcode == INSN_ERET)
3597 || (history[0].insn_opcode == INSN_DERET))
3599 if (mips_opts.mips16
3600 && (pinfo & INSN_UNCOND_BRANCH_DELAY)
3601 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))
3602 && ISA_SUPPORTS_MIPS16E)
3604 /* Convert MIPS16 jr/jalr into a "compact" jump. */
3605 ip->insn_opcode |= 0x0080;
3607 insert_into_history (0, 1, ip);
3611 /* We could do even better for unconditional branches to
3612 portions of this object file; we could pick up the
3613 instruction at the destination, put it in the delay
3614 slot, and bump the destination address. */
3615 insert_into_history (0, 1, ip);
3619 if (mips_relax.sequence)
3620 mips_relax.sizes[mips_relax.sequence - 1] += 4;
3624 /* It looks like we can actually do the swap. */
3625 struct mips_cl_insn delay = history[0];
3626 if (mips_opts.mips16)
3628 know (delay.frag == ip->frag);
3629 move_insn (ip, delay.frag, delay.where);
3630 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
3632 else if (relaxed_branch)
3634 /* Add the delay slot instruction to the end of the
3635 current frag and shrink the fixed part of the
3636 original frag. If the branch occupies the tail of
3637 the latter, move it backwards to cover the gap. */
3638 delay.frag->fr_fix -= 4;
3639 if (delay.frag == ip->frag)
3640 move_insn (ip, ip->frag, ip->where - 4);
3641 add_fixed_insn (&delay);
3645 move_insn (&delay, ip->frag, ip->where);
3646 move_insn (ip, history[0].frag, history[0].where);
3650 insert_into_history (0, 1, &delay);
3653 /* If that was an unconditional branch, forget the previous
3654 insn information. */
3655 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
3657 mips_no_prev_insn ();
3660 else if (pinfo & INSN_COND_BRANCH_LIKELY)
3662 /* We don't yet optimize a branch likely. What we should do
3663 is look at the target, copy the instruction found there
3664 into the delay slot, and increment the branch to jump to
3665 the next instruction. */
3666 insert_into_history (0, 1, ip);
3670 insert_into_history (0, 1, ip);
3673 insert_into_history (0, 1, ip);
3675 /* We just output an insn, so the next one doesn't have a label. */
3676 mips_clear_insn_labels ();
3679 /* Forget that there was any previous instruction or label. */
3682 mips_no_prev_insn (void)
3684 prev_nop_frag = NULL;
3685 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
3686 mips_clear_insn_labels ();
3689 /* This function must be called before we emit something other than
3690 instructions. It is like mips_no_prev_insn except that it inserts
3691 any NOPS that might be needed by previous instructions. */
3694 mips_emit_delays (void)
3696 if (! mips_opts.noreorder)
3698 int nops = nops_for_insn (0, history, NULL);
3702 add_fixed_insn (NOP_INSN);
3703 mips_move_labels ();
3706 mips_no_prev_insn ();
3709 /* Start a (possibly nested) noreorder block. */
3712 start_noreorder (void)
3714 if (mips_opts.noreorder == 0)
3719 /* None of the instructions before the .set noreorder can be moved. */
3720 for (i = 0; i < ARRAY_SIZE (history); i++)
3721 history[i].fixed_p = 1;
3723 /* Insert any nops that might be needed between the .set noreorder
3724 block and the previous instructions. We will later remove any
3725 nops that turn out not to be needed. */
3726 nops = nops_for_insn (0, history, NULL);
3729 if (mips_optimize != 0)
3731 /* Record the frag which holds the nop instructions, so
3732 that we can remove them if we don't need them. */
3733 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
3734 prev_nop_frag = frag_now;
3735 prev_nop_frag_holds = nops;
3736 prev_nop_frag_required = 0;
3737 prev_nop_frag_since = 0;
3740 for (; nops > 0; --nops)
3741 add_fixed_insn (NOP_INSN);
3743 /* Move on to a new frag, so that it is safe to simply
3744 decrease the size of prev_nop_frag. */
3745 frag_wane (frag_now);
3747 mips_move_labels ();
3749 mips16_mark_labels ();
3750 mips_clear_insn_labels ();
3752 mips_opts.noreorder++;
3753 mips_any_noreorder = 1;
3756 /* End a nested noreorder block. */
3759 end_noreorder (void)
3762 mips_opts.noreorder--;
3763 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
3765 /* Commit to inserting prev_nop_frag_required nops and go back to
3766 handling nop insertion the .set reorder way. */
3767 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
3768 * (mips_opts.mips16 ? 2 : 4));
3769 insert_into_history (prev_nop_frag_since,
3770 prev_nop_frag_required, NOP_INSN);
3771 prev_nop_frag = NULL;
3775 /* Set up global variables for the start of a new macro. */
3780 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
3781 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
3782 && (history[0].insn_mo->pinfo
3783 & (INSN_UNCOND_BRANCH_DELAY
3784 | INSN_COND_BRANCH_DELAY
3785 | INSN_COND_BRANCH_LIKELY)) != 0);
3788 /* Given that a macro is longer than 4 bytes, return the appropriate warning
3789 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
3790 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
3793 macro_warning (relax_substateT subtype)
3795 if (subtype & RELAX_DELAY_SLOT)
3796 return _("Macro instruction expanded into multiple instructions"
3797 " in a branch delay slot");
3798 else if (subtype & RELAX_NOMACRO)
3799 return _("Macro instruction expanded into multiple instructions");
3804 /* Finish up a macro. Emit warnings as appropriate. */
3809 if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4)
3811 relax_substateT subtype;
3813 /* Set up the relaxation warning flags. */
3815 if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0])
3816 subtype |= RELAX_SECOND_LONGER;
3817 if (mips_opts.warn_about_macros)
3818 subtype |= RELAX_NOMACRO;
3819 if (mips_macro_warning.delay_slot_p)
3820 subtype |= RELAX_DELAY_SLOT;
3822 if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4)
3824 /* Either the macro has a single implementation or both
3825 implementations are longer than 4 bytes. Emit the
3827 const char *msg = macro_warning (subtype);
3829 as_warn ("%s", msg);
3833 /* One implementation might need a warning but the other
3834 definitely doesn't. */
3835 mips_macro_warning.first_frag->fr_subtype |= subtype;
3840 /* Read a macro's relocation codes from *ARGS and store them in *R.
3841 The first argument in *ARGS will be either the code for a single
3842 relocation or -1 followed by the three codes that make up a
3843 composite relocation. */
3846 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
3850 next = va_arg (*args, int);
3852 r[0] = (bfd_reloc_code_real_type) next;
3854 for (i = 0; i < 3; i++)
3855 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
3858 /* Build an instruction created by a macro expansion. This is passed
3859 a pointer to the count of instructions created so far, an
3860 expression, the name of the instruction to build, an operand format
3861 string, and corresponding arguments. */
3864 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
3866 const struct mips_opcode *mo;
3867 struct mips_cl_insn insn;
3868 bfd_reloc_code_real_type r[3];
3871 va_start (args, fmt);
3873 if (mips_opts.mips16)
3875 mips16_macro_build (ep, name, fmt, &args);
3880 r[0] = BFD_RELOC_UNUSED;
3881 r[1] = BFD_RELOC_UNUSED;
3882 r[2] = BFD_RELOC_UNUSED;
3883 mo = (struct mips_opcode *) hash_find (op_hash, name);
3885 gas_assert (strcmp (name, mo->name) == 0);
3889 /* Search until we get a match for NAME. It is assumed here that
3890 macros will never generate MDMX, MIPS-3D, or MT instructions. */
3891 if (strcmp (fmt, mo->args) == 0
3892 && mo->pinfo != INSN_MACRO
3893 && is_opcode_valid (mo))
3897 gas_assert (mo->name);
3898 gas_assert (strcmp (name, mo->name) == 0);
3901 create_insn (&insn, mo);
3919 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
3924 /* Note that in the macro case, these arguments are already
3925 in MSB form. (When handling the instruction in the
3926 non-macro case, these arguments are sizes from which
3927 MSB values must be calculated.) */
3928 INSERT_OPERAND (INSMSB, insn, va_arg (args, int));
3934 /* Note that in the macro case, these arguments are already
3935 in MSBD form. (When handling the instruction in the
3936 non-macro case, these arguments are sizes from which
3937 MSBD values must be calculated.) */
3938 INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int));
3942 INSERT_OPERAND (SEQI, insn, va_arg (args, int));
3951 INSERT_OPERAND (BP, insn, va_arg (args, int));
3957 INSERT_OPERAND (RT, insn, va_arg (args, int));
3961 INSERT_OPERAND (CODE, insn, va_arg (args, int));
3966 INSERT_OPERAND (FT, insn, va_arg (args, int));
3972 INSERT_OPERAND (RD, insn, va_arg (args, int));
3977 int tmp = va_arg (args, int);
3979 INSERT_OPERAND (RT, insn, tmp);
3980 INSERT_OPERAND (RD, insn, tmp);
3986 INSERT_OPERAND (FS, insn, va_arg (args, int));
3993 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
3997 INSERT_OPERAND (FD, insn, va_arg (args, int));
4001 INSERT_OPERAND (CODE20, insn, va_arg (args, int));
4005 INSERT_OPERAND (CODE19, insn, va_arg (args, int));
4009 INSERT_OPERAND (CODE2, insn, va_arg (args, int));
4016 INSERT_OPERAND (RS, insn, va_arg (args, int));
4021 macro_read_relocs (&args, r);
4022 gas_assert (*r == BFD_RELOC_GPREL16
4023 || *r == BFD_RELOC_MIPS_HIGHER
4024 || *r == BFD_RELOC_HI16_S
4025 || *r == BFD_RELOC_LO16
4026 || *r == BFD_RELOC_MIPS_GOT_OFST);
4030 macro_read_relocs (&args, r);
4034 macro_read_relocs (&args, r);
4035 gas_assert (ep != NULL
4036 && (ep->X_op == O_constant
4037 || (ep->X_op == O_symbol
4038 && (*r == BFD_RELOC_MIPS_HIGHEST
4039 || *r == BFD_RELOC_HI16_S
4040 || *r == BFD_RELOC_HI16
4041 || *r == BFD_RELOC_GPREL16
4042 || *r == BFD_RELOC_MIPS_GOT_HI16
4043 || *r == BFD_RELOC_MIPS_CALL_HI16))));
4047 gas_assert (ep != NULL);
4050 * This allows macro() to pass an immediate expression for
4051 * creating short branches without creating a symbol.
4053 * We don't allow branch relaxation for these branches, as
4054 * they should only appear in ".set nomacro" anyway.
4056 if (ep->X_op == O_constant)
4058 if ((ep->X_add_number & 3) != 0)
4059 as_bad (_("branch to misaligned address (0x%lx)"),
4060 (unsigned long) ep->X_add_number);
4061 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
4062 as_bad (_("branch address range overflow (0x%lx)"),
4063 (unsigned long) ep->X_add_number);
4064 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
4068 *r = BFD_RELOC_16_PCREL_S2;
4072 gas_assert (ep != NULL);
4073 *r = BFD_RELOC_MIPS_JMP;
4077 INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long));
4081 INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long));
4090 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
4092 append_insn (&insn, ep, r);
4096 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
4099 struct mips_opcode *mo;
4100 struct mips_cl_insn insn;
4101 bfd_reloc_code_real_type r[3]
4102 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
4104 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
4106 gas_assert (strcmp (name, mo->name) == 0);
4108 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
4111 gas_assert (mo->name);
4112 gas_assert (strcmp (name, mo->name) == 0);
4115 create_insn (&insn, mo);
4133 MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int));
4138 MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int));
4142 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int));
4146 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int));
4156 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int));
4163 regno = va_arg (*args, int);
4164 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
4165 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
4186 gas_assert (ep != NULL);
4188 if (ep->X_op != O_constant)
4189 *r = (int) BFD_RELOC_UNUSED + c;
4192 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
4193 FALSE, &insn.insn_opcode, &insn.use_extend,
4196 *r = BFD_RELOC_UNUSED;
4202 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int));
4209 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
4211 append_insn (&insn, ep, r);
4215 * Sign-extend 32-bit mode constants that have bit 31 set and all
4216 * higher bits unset.
4219 normalize_constant_expr (expressionS *ex)
4221 if (ex->X_op == O_constant
4222 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
4223 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
4228 * Sign-extend 32-bit mode address offsets that have bit 31 set and
4229 * all higher bits unset.
4232 normalize_address_expr (expressionS *ex)
4234 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
4235 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
4236 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
4237 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
4242 * Generate a "jalr" instruction with a relocation hint to the called
4243 * function. This occurs in NewABI PIC code.
4246 macro_build_jalr (expressionS *ep)
4250 if (MIPS_JALR_HINT_P (ep))
4255 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
4256 if (MIPS_JALR_HINT_P (ep))
4257 fix_new_exp (frag_now, f - frag_now->fr_literal,
4258 4, ep, FALSE, BFD_RELOC_MIPS_JALR);
4262 * Generate a "lui" instruction.
4265 macro_build_lui (expressionS *ep, int regnum)
4267 expressionS high_expr;
4268 const struct mips_opcode *mo;
4269 struct mips_cl_insn insn;
4270 bfd_reloc_code_real_type r[3]
4271 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
4272 const char *name = "lui";
4273 const char *fmt = "t,u";
4275 gas_assert (! mips_opts.mips16);
4279 if (high_expr.X_op == O_constant)
4281 /* We can compute the instruction now without a relocation entry. */
4282 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
4284 *r = BFD_RELOC_UNUSED;
4288 gas_assert (ep->X_op == O_symbol);
4289 /* _gp_disp is a special case, used from s_cpload.
4290 __gnu_local_gp is used if mips_no_shared. */
4291 gas_assert (mips_pic == NO_PIC
4293 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
4294 || (! mips_in_shared
4295 && strcmp (S_GET_NAME (ep->X_add_symbol),
4296 "__gnu_local_gp") == 0));
4297 *r = BFD_RELOC_HI16_S;
4300 mo = hash_find (op_hash, name);
4301 gas_assert (strcmp (name, mo->name) == 0);
4302 gas_assert (strcmp (fmt, mo->args) == 0);
4303 create_insn (&insn, mo);
4305 insn.insn_opcode = insn.insn_mo->match;
4306 INSERT_OPERAND (RT, insn, regnum);
4307 if (*r == BFD_RELOC_UNUSED)
4309 insn.insn_opcode |= high_expr.X_add_number;
4310 append_insn (&insn, NULL, r);
4313 append_insn (&insn, &high_expr, r);
4316 /* Generate a sequence of instructions to do a load or store from a constant
4317 offset off of a base register (breg) into/from a target register (treg),
4318 using AT if necessary. */
4320 macro_build_ldst_constoffset (expressionS *ep, const char *op,
4321 int treg, int breg, int dbl)
4323 gas_assert (ep->X_op == O_constant);
4325 /* Sign-extending 32-bit constants makes their handling easier. */
4327 normalize_constant_expr (ep);
4329 /* Right now, this routine can only handle signed 32-bit constants. */
4330 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
4331 as_warn (_("operand overflow"));
4333 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
4335 /* Signed 16-bit offset will fit in the op. Easy! */
4336 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
4340 /* 32-bit offset, need multiple instructions and AT, like:
4341 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
4342 addu $tempreg,$tempreg,$breg
4343 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
4344 to handle the complete offset. */
4345 macro_build_lui (ep, AT);
4346 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
4347 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
4350 as_bad (_("Macro used $at after \".set noat\""));
4355 * Generates code to set the $at register to true (one)
4356 * if reg is less than the immediate expression.
4359 set_at (int reg, int unsignedp)
4361 if (imm_expr.X_op == O_constant
4362 && imm_expr.X_add_number >= -0x8000
4363 && imm_expr.X_add_number < 0x8000)
4364 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
4365 AT, reg, BFD_RELOC_LO16);
4368 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4369 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
4373 /* Warn if an expression is not a constant. */
4376 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
4378 if (ex->X_op == O_big)
4379 as_bad (_("unsupported large constant"));
4380 else if (ex->X_op != O_constant)
4381 as_bad (_("Instruction %s requires absolute expression"),
4384 if (HAVE_32BIT_GPRS)
4385 normalize_constant_expr (ex);
4388 /* Count the leading zeroes by performing a binary chop. This is a
4389 bulky bit of source, but performance is a LOT better for the
4390 majority of values than a simple loop to count the bits:
4391 for (lcnt = 0; (lcnt < 32); lcnt++)
4392 if ((v) & (1 << (31 - lcnt)))
4394 However it is not code size friendly, and the gain will drop a bit
4395 on certain cached systems.
4397 #define COUNT_TOP_ZEROES(v) \
4398 (((v) & ~0xffff) == 0 \
4399 ? ((v) & ~0xff) == 0 \
4400 ? ((v) & ~0xf) == 0 \
4401 ? ((v) & ~0x3) == 0 \
4402 ? ((v) & ~0x1) == 0 \
4407 : ((v) & ~0x7) == 0 \
4410 : ((v) & ~0x3f) == 0 \
4411 ? ((v) & ~0x1f) == 0 \
4414 : ((v) & ~0x7f) == 0 \
4417 : ((v) & ~0xfff) == 0 \
4418 ? ((v) & ~0x3ff) == 0 \
4419 ? ((v) & ~0x1ff) == 0 \
4422 : ((v) & ~0x7ff) == 0 \
4425 : ((v) & ~0x3fff) == 0 \
4426 ? ((v) & ~0x1fff) == 0 \
4429 : ((v) & ~0x7fff) == 0 \
4432 : ((v) & ~0xffffff) == 0 \
4433 ? ((v) & ~0xfffff) == 0 \
4434 ? ((v) & ~0x3ffff) == 0 \
4435 ? ((v) & ~0x1ffff) == 0 \
4438 : ((v) & ~0x7ffff) == 0 \
4441 : ((v) & ~0x3fffff) == 0 \
4442 ? ((v) & ~0x1fffff) == 0 \
4445 : ((v) & ~0x7fffff) == 0 \
4448 : ((v) & ~0xfffffff) == 0 \
4449 ? ((v) & ~0x3ffffff) == 0 \
4450 ? ((v) & ~0x1ffffff) == 0 \
4453 : ((v) & ~0x7ffffff) == 0 \
4456 : ((v) & ~0x3fffffff) == 0 \
4457 ? ((v) & ~0x1fffffff) == 0 \
4460 : ((v) & ~0x7fffffff) == 0 \
4465 * This routine generates the least number of instructions necessary to load
4466 * an absolute expression value into a register.
4469 load_register (int reg, expressionS *ep, int dbl)
4472 expressionS hi32, lo32;
4474 if (ep->X_op != O_big)
4476 gas_assert (ep->X_op == O_constant);
4478 /* Sign-extending 32-bit constants makes their handling easier. */
4480 normalize_constant_expr (ep);
4482 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
4484 /* We can handle 16 bit signed values with an addiu to
4485 $zero. No need to ever use daddiu here, since $zero and
4486 the result are always correct in 32 bit mode. */
4487 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4490 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
4492 /* We can handle 16 bit unsigned values with an ori to
4494 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
4497 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
4499 /* 32 bit values require an lui. */
4500 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16);
4501 if ((ep->X_add_number & 0xffff) != 0)
4502 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
4507 /* The value is larger than 32 bits. */
4509 if (!dbl || HAVE_32BIT_GPRS)
4513 sprintf_vma (value, ep->X_add_number);
4514 as_bad (_("Number (0x%s) larger than 32 bits"), value);
4515 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4519 if (ep->X_op != O_big)
4522 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
4523 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
4524 hi32.X_add_number &= 0xffffffff;
4526 lo32.X_add_number &= 0xffffffff;
4530 gas_assert (ep->X_add_number > 2);
4531 if (ep->X_add_number == 3)
4532 generic_bignum[3] = 0;
4533 else if (ep->X_add_number > 4)
4534 as_bad (_("Number larger than 64 bits"));
4535 lo32.X_op = O_constant;
4536 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
4537 hi32.X_op = O_constant;
4538 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
4541 if (hi32.X_add_number == 0)
4546 unsigned long hi, lo;
4548 if (hi32.X_add_number == (offsetT) 0xffffffff)
4550 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
4552 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4555 if (lo32.X_add_number & 0x80000000)
4557 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
4558 if (lo32.X_add_number & 0xffff)
4559 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
4564 /* Check for 16bit shifted constant. We know that hi32 is
4565 non-zero, so start the mask on the first bit of the hi32
4570 unsigned long himask, lomask;
4574 himask = 0xffff >> (32 - shift);
4575 lomask = (0xffff << shift) & 0xffffffff;
4579 himask = 0xffff << (shift - 32);
4582 if ((hi32.X_add_number & ~(offsetT) himask) == 0
4583 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
4587 tmp.X_op = O_constant;
4589 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
4590 | (lo32.X_add_number >> shift));
4592 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
4593 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
4594 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<",
4595 reg, reg, (shift >= 32) ? shift - 32 : shift);
4600 while (shift <= (64 - 16));
4602 /* Find the bit number of the lowest one bit, and store the
4603 shifted value in hi/lo. */
4604 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
4605 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
4609 while ((lo & 1) == 0)
4614 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
4620 while ((hi & 1) == 0)
4629 /* Optimize if the shifted value is a (power of 2) - 1. */
4630 if ((hi == 0 && ((lo + 1) & lo) == 0)
4631 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
4633 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
4638 /* This instruction will set the register to be all
4640 tmp.X_op = O_constant;
4641 tmp.X_add_number = (offsetT) -1;
4642 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4646 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<",
4647 reg, reg, (bit >= 32) ? bit - 32 : bit);
4649 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<",
4650 reg, reg, (shift >= 32) ? shift - 32 : shift);
4655 /* Sign extend hi32 before calling load_register, because we can
4656 generally get better code when we load a sign extended value. */
4657 if ((hi32.X_add_number & 0x80000000) != 0)
4658 hi32.X_add_number |= ~(offsetT) 0xffffffff;
4659 load_register (reg, &hi32, 0);
4662 if ((lo32.X_add_number & 0xffff0000) == 0)
4666 macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0);
4674 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
4676 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
4677 macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0);
4683 macro_build (NULL, "dsll", "d,w,<", reg, freg, 16);
4687 mid16.X_add_number >>= 16;
4688 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
4689 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4692 if ((lo32.X_add_number & 0xffff) != 0)
4693 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
4697 load_delay_nop (void)
4699 if (!gpr_interlocks)
4700 macro_build (NULL, "nop", "");
4703 /* Load an address into a register. */
4706 load_address (int reg, expressionS *ep, int *used_at)
4708 if (ep->X_op != O_constant
4709 && ep->X_op != O_symbol)
4711 as_bad (_("expression too complex"));
4712 ep->X_op = O_constant;
4715 if (ep->X_op == O_constant)
4717 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
4721 if (mips_pic == NO_PIC)
4723 /* If this is a reference to a GP relative symbol, we want
4724 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4726 lui $reg,<sym> (BFD_RELOC_HI16_S)
4727 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4728 If we have an addend, we always use the latter form.
4730 With 64bit address space and a usable $at we want
4731 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4732 lui $at,<sym> (BFD_RELOC_HI16_S)
4733 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4734 daddiu $at,<sym> (BFD_RELOC_LO16)
4738 If $at is already in use, we use a path which is suboptimal
4739 on superscalar processors.
4740 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4741 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4743 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
4745 daddiu $reg,<sym> (BFD_RELOC_LO16)
4747 For GP relative symbols in 64bit address space we can use
4748 the same sequence as in 32bit address space. */
4749 if (HAVE_64BIT_SYMBOLS)
4751 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
4752 && !nopic_need_relax (ep->X_add_symbol, 1))
4754 relax_start (ep->X_add_symbol);
4755 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4756 mips_gp_register, BFD_RELOC_GPREL16);
4760 if (*used_at == 0 && mips_opts.at)
4762 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
4763 macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S);
4764 macro_build (ep, "daddiu", "t,r,j", reg, reg,
4765 BFD_RELOC_MIPS_HIGHER);
4766 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
4767 macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0);
4768 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
4773 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
4774 macro_build (ep, "daddiu", "t,r,j", reg, reg,
4775 BFD_RELOC_MIPS_HIGHER);
4776 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4777 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
4778 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4779 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
4782 if (mips_relax.sequence)
4787 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
4788 && !nopic_need_relax (ep->X_add_symbol, 1))
4790 relax_start (ep->X_add_symbol);
4791 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4792 mips_gp_register, BFD_RELOC_GPREL16);
4795 macro_build_lui (ep, reg);
4796 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
4797 reg, reg, BFD_RELOC_LO16);
4798 if (mips_relax.sequence)
4802 else if (!mips_big_got)
4806 /* If this is a reference to an external symbol, we want
4807 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4809 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4811 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4812 If there is a constant, it must be added in after.
4814 If we have NewABI, we want
4815 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4816 unless we're referencing a global symbol with a non-zero
4817 offset, in which case cst must be added separately. */
4820 if (ep->X_add_number)
4822 ex.X_add_number = ep->X_add_number;
4823 ep->X_add_number = 0;
4824 relax_start (ep->X_add_symbol);
4825 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4826 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4827 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4828 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4829 ex.X_op = O_constant;
4830 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
4831 reg, reg, BFD_RELOC_LO16);
4832 ep->X_add_number = ex.X_add_number;
4835 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4836 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4837 if (mips_relax.sequence)
4842 ex.X_add_number = ep->X_add_number;
4843 ep->X_add_number = 0;
4844 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4845 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4847 relax_start (ep->X_add_symbol);
4849 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4853 if (ex.X_add_number != 0)
4855 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4856 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4857 ex.X_op = O_constant;
4858 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
4859 reg, reg, BFD_RELOC_LO16);
4863 else if (mips_big_got)
4867 /* This is the large GOT case. If this is a reference to an
4868 external symbol, we want
4869 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4871 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
4873 Otherwise, for a reference to a local symbol in old ABI, we want
4874 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4876 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4877 If there is a constant, it must be added in after.
4879 In the NewABI, for local symbols, with or without offsets, we want:
4880 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4881 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4885 ex.X_add_number = ep->X_add_number;
4886 ep->X_add_number = 0;
4887 relax_start (ep->X_add_symbol);
4888 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4889 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4890 reg, reg, mips_gp_register);
4891 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4892 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4893 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4894 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4895 else if (ex.X_add_number)
4897 ex.X_op = O_constant;
4898 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4902 ep->X_add_number = ex.X_add_number;
4904 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4905 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
4906 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4907 BFD_RELOC_MIPS_GOT_OFST);
4912 ex.X_add_number = ep->X_add_number;
4913 ep->X_add_number = 0;
4914 relax_start (ep->X_add_symbol);
4915 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4916 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4917 reg, reg, mips_gp_register);
4918 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4919 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4921 if (reg_needs_delay (mips_gp_register))
4923 /* We need a nop before loading from $gp. This special
4924 check is required because the lui which starts the main
4925 instruction stream does not refer to $gp, and so will not
4926 insert the nop which may be required. */
4927 macro_build (NULL, "nop", "");
4929 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4930 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4932 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4936 if (ex.X_add_number != 0)
4938 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4939 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4940 ex.X_op = O_constant;
4941 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4949 if (!mips_opts.at && *used_at == 1)
4950 as_bad (_("Macro used $at after \".set noat\""));
4953 /* Move the contents of register SOURCE into register DEST. */
4956 move_register (int dest, int source)
4958 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
4962 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4963 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4964 The two alternatives are:
4966 Global symbol Local sybmol
4967 ------------- ------------
4968 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4970 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4972 load_got_offset emits the first instruction and add_got_offset
4973 emits the second for a 16-bit offset or add_got_offset_hilo emits
4974 a sequence to add a 32-bit offset using a scratch register. */
4977 load_got_offset (int dest, expressionS *local)
4982 global.X_add_number = 0;
4984 relax_start (local->X_add_symbol);
4985 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4986 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4988 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4989 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4994 add_got_offset (int dest, expressionS *local)
4998 global.X_op = O_constant;
4999 global.X_op_symbol = NULL;
5000 global.X_add_symbol = NULL;
5001 global.X_add_number = local->X_add_number;
5003 relax_start (local->X_add_symbol);
5004 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
5005 dest, dest, BFD_RELOC_LO16);
5007 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
5012 add_got_offset_hilo (int dest, expressionS *local, int tmp)
5015 int hold_mips_optimize;
5017 global.X_op = O_constant;
5018 global.X_op_symbol = NULL;
5019 global.X_add_symbol = NULL;
5020 global.X_add_number = local->X_add_number;
5022 relax_start (local->X_add_symbol);
5023 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
5025 /* Set mips_optimize around the lui instruction to avoid
5026 inserting an unnecessary nop after the lw. */
5027 hold_mips_optimize = mips_optimize;
5029 macro_build_lui (&global, tmp);
5030 mips_optimize = hold_mips_optimize;
5031 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
5034 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
5039 * This routine implements the seemingly endless macro or synthesized
5040 * instructions and addressing modes in the mips assembly language. Many
5041 * of these macros are simple and are similar to each other. These could
5042 * probably be handled by some kind of table or grammar approach instead of
5043 * this verbose method. Others are not simple macros but are more like
5044 * optimizing code generation.
5045 * One interesting optimization is when several store macros appear
5046 * consecutively that would load AT with the upper half of the same address.
5047 * The ensuing load upper instructions are ommited. This implies some kind
5048 * of global optimization. We currently only optimize within a single macro.
5049 * For many of the load and store macros if the address is specified as a
5050 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
5051 * first load register 'at' with zero and use it as the base register. The
5052 * mips assembler simply uses register $zero. Just one tiny optimization
5056 macro (struct mips_cl_insn *ip)
5058 unsigned int treg, sreg, dreg, breg;
5059 unsigned int tempreg;
5074 bfd_reloc_code_real_type r;
5075 int hold_mips_optimize;
5077 gas_assert (! mips_opts.mips16);
5079 treg = EXTRACT_OPERAND (RT, *ip);
5080 dreg = EXTRACT_OPERAND (RD, *ip);
5081 sreg = breg = EXTRACT_OPERAND (RS, *ip);
5082 mask = ip->insn_mo->mask;
5084 expr1.X_op = O_constant;
5085 expr1.X_op_symbol = NULL;
5086 expr1.X_add_symbol = NULL;
5087 expr1.X_add_number = 1;
5101 expr1.X_add_number = 8;
5102 macro_build (&expr1, "bgez", "s,p", sreg);
5104 macro_build (NULL, "nop", "");
5106 move_register (dreg, sreg);
5107 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
5130 if (imm_expr.X_op == O_constant
5131 && imm_expr.X_add_number >= -0x8000
5132 && imm_expr.X_add_number < 0x8000)
5134 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
5138 load_register (AT, &imm_expr, dbl);
5139 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
5158 if (imm_expr.X_op == O_constant
5159 && imm_expr.X_add_number >= 0
5160 && imm_expr.X_add_number < 0x10000)
5162 if (mask != M_NOR_I)
5163 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
5166 macro_build (&imm_expr, "ori", "t,r,i",
5167 treg, sreg, BFD_RELOC_LO16);
5168 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
5174 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5175 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
5179 switch (imm_expr.X_add_number)
5182 macro_build (NULL, "nop", "");
5185 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
5188 macro_build (NULL, "balign", "t,s,2", treg, sreg,
5189 (int) imm_expr.X_add_number);
5208 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5210 macro_build (&offset_expr, s, "s,t,p", sreg, ZERO);
5214 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5215 macro_build (&offset_expr, s, "s,t,p", sreg, AT);
5223 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
5228 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg);
5232 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
5233 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5239 /* Check for > max integer. */
5240 maxnum = 0x7fffffff;
5241 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5248 if (imm_expr.X_op == O_constant
5249 && imm_expr.X_add_number >= maxnum
5250 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5253 /* Result is always false. */
5255 macro_build (NULL, "nop", "");
5257 macro_build (&offset_expr, "bnel", "s,t,p", ZERO, ZERO);
5260 if (imm_expr.X_op != O_constant)
5261 as_bad (_("Unsupported large constant"));
5262 ++imm_expr.X_add_number;
5266 if (mask == M_BGEL_I)
5268 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5270 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
5273 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5275 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
5278 maxnum = 0x7fffffff;
5279 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5286 maxnum = - maxnum - 1;
5287 if (imm_expr.X_op == O_constant
5288 && imm_expr.X_add_number <= maxnum
5289 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5292 /* result is always true */
5293 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
5294 macro_build (&offset_expr, "b", "p");
5299 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5309 macro_build (&offset_expr, likely ? "beql" : "beq",
5310 "s,t,p", ZERO, treg);
5314 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
5315 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5323 && imm_expr.X_op == O_constant
5324 && imm_expr.X_add_number == -1))
5326 if (imm_expr.X_op != O_constant)
5327 as_bad (_("Unsupported large constant"));
5328 ++imm_expr.X_add_number;
5332 if (mask == M_BGEUL_I)
5334 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5336 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5338 macro_build (&offset_expr, likely ? "bnel" : "bne",
5339 "s,t,p", sreg, ZERO);
5344 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5352 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
5357 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg);
5361 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
5362 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5370 macro_build (&offset_expr, likely ? "bnel" : "bne",
5371 "s,t,p", sreg, ZERO);
5377 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
5378 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5386 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
5391 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg);
5395 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
5396 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5402 maxnum = 0x7fffffff;
5403 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5410 if (imm_expr.X_op == O_constant
5411 && imm_expr.X_add_number >= maxnum
5412 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5414 if (imm_expr.X_op != O_constant)
5415 as_bad (_("Unsupported large constant"));
5416 ++imm_expr.X_add_number;
5420 if (mask == M_BLTL_I)
5422 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5424 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
5427 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5429 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
5434 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5442 macro_build (&offset_expr, likely ? "beql" : "beq",
5443 "s,t,p", sreg, ZERO);
5449 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
5450 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5458 && imm_expr.X_op == O_constant
5459 && imm_expr.X_add_number == -1))
5461 if (imm_expr.X_op != O_constant)
5462 as_bad (_("Unsupported large constant"));
5463 ++imm_expr.X_add_number;
5467 if (mask == M_BLTUL_I)
5469 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5471 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5473 macro_build (&offset_expr, likely ? "beql" : "beq",
5474 "s,t,p", sreg, ZERO);
5479 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5487 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
5492 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg);
5496 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
5497 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5507 macro_build (&offset_expr, likely ? "bnel" : "bne",
5508 "s,t,p", ZERO, treg);
5512 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
5513 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5518 /* Use unsigned arithmetic. */
5522 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5524 as_bad (_("Unsupported large constant"));
5529 pos = imm_expr.X_add_number;
5530 size = imm2_expr.X_add_number;
5535 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
5538 if (size == 0 || size > 64 || (pos + size - 1) > 63)
5540 as_bad (_("Improper extract size (%lu, position %lu)"),
5541 (unsigned long) size, (unsigned long) pos);
5545 if (size <= 32 && pos < 32)
5550 else if (size <= 32)
5560 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
5567 /* Use unsigned arithmetic. */
5571 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5573 as_bad (_("Unsupported large constant"));
5578 pos = imm_expr.X_add_number;
5579 size = imm2_expr.X_add_number;
5584 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
5587 if (size == 0 || size > 64 || (pos + size - 1) > 63)
5589 as_bad (_("Improper insert size (%lu, position %lu)"),
5590 (unsigned long) size, (unsigned long) pos);
5594 if (pos < 32 && (pos + size - 1) < 32)
5609 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
5610 (int) (pos + size - 1));
5626 as_warn (_("Divide by zero."));
5628 macro_build (NULL, "teq", "s,t,q", ZERO, ZERO, 7);
5630 macro_build (NULL, "break", "c", 7);
5637 macro_build (NULL, "teq", "s,t,q", treg, ZERO, 7);
5638 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
5642 expr1.X_add_number = 8;
5643 macro_build (&expr1, "bne", "s,t,p", treg, ZERO);
5644 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
5645 macro_build (NULL, "break", "c", 7);
5647 expr1.X_add_number = -1;
5649 load_register (AT, &expr1, dbl);
5650 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
5651 macro_build (&expr1, "bne", "s,t,p", treg, AT);
5654 expr1.X_add_number = 1;
5655 load_register (AT, &expr1, dbl);
5656 macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31);
5660 expr1.X_add_number = 0x80000000;
5661 macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16);
5665 macro_build (NULL, "teq", "s,t,q", sreg, AT, 6);
5666 /* We want to close the noreorder block as soon as possible, so
5667 that later insns are available for delay slot filling. */
5672 expr1.X_add_number = 8;
5673 macro_build (&expr1, "bne", "s,t,p", sreg, AT);
5674 macro_build (NULL, "nop", "");
5676 /* We want to close the noreorder block as soon as possible, so
5677 that later insns are available for delay slot filling. */
5680 macro_build (NULL, "break", "c", 6);
5682 macro_build (NULL, s, "d", dreg);
5721 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5723 as_warn (_("Divide by zero."));
5725 macro_build (NULL, "teq", "s,t,q", ZERO, ZERO, 7);
5727 macro_build (NULL, "break", "c", 7);
5730 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5732 if (strcmp (s2, "mflo") == 0)
5733 move_register (dreg, sreg);
5735 move_register (dreg, ZERO);
5738 if (imm_expr.X_op == O_constant
5739 && imm_expr.X_add_number == -1
5740 && s[strlen (s) - 1] != 'u')
5742 if (strcmp (s2, "mflo") == 0)
5744 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
5747 move_register (dreg, ZERO);
5752 load_register (AT, &imm_expr, dbl);
5753 macro_build (NULL, s, "z,s,t", sreg, AT);
5754 macro_build (NULL, s2, "d", dreg);
5776 macro_build (NULL, "teq", "s,t,q", treg, ZERO, 7);
5777 macro_build (NULL, s, "z,s,t", sreg, treg);
5778 /* We want to close the noreorder block as soon as possible, so
5779 that later insns are available for delay slot filling. */
5784 expr1.X_add_number = 8;
5785 macro_build (&expr1, "bne", "s,t,p", treg, ZERO);
5786 macro_build (NULL, s, "z,s,t", sreg, treg);
5788 /* We want to close the noreorder block as soon as possible, so
5789 that later insns are available for delay slot filling. */
5791 macro_build (NULL, "break", "c", 7);
5793 macro_build (NULL, s2, "d", dreg);
5805 /* Load the address of a symbol into a register. If breg is not
5806 zero, we then add a base register to it. */
5808 if (dbl && HAVE_32BIT_GPRS)
5809 as_warn (_("dla used to load 32-bit register"));
5811 if (!dbl && HAVE_64BIT_OBJECTS)
5812 as_warn (_("la used to load 64-bit address"));
5814 if (offset_expr.X_op == O_constant
5815 && offset_expr.X_add_number >= -0x8000
5816 && offset_expr.X_add_number < 0x8000)
5818 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
5819 "t,r,j", treg, sreg, BFD_RELOC_LO16);
5823 if (mips_opts.at && (treg == breg))
5833 if (offset_expr.X_op != O_symbol
5834 && offset_expr.X_op != O_constant)
5836 as_bad (_("Expression too complex"));
5837 offset_expr.X_op = O_constant;
5840 if (offset_expr.X_op == O_constant)
5841 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
5842 else if (mips_pic == NO_PIC)
5844 /* If this is a reference to a GP relative symbol, we want
5845 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5847 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5848 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5849 If we have a constant, we need two instructions anyhow,
5850 so we may as well always use the latter form.
5852 With 64bit address space and a usable $at we want
5853 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5854 lui $at,<sym> (BFD_RELOC_HI16_S)
5855 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5856 daddiu $at,<sym> (BFD_RELOC_LO16)
5858 daddu $tempreg,$tempreg,$at
5860 If $at is already in use, we use a path which is suboptimal
5861 on superscalar processors.
5862 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5863 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5865 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5867 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
5869 For GP relative symbols in 64bit address space we can use
5870 the same sequence as in 32bit address space. */
5871 if (HAVE_64BIT_SYMBOLS)
5873 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5874 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5876 relax_start (offset_expr.X_add_symbol);
5877 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5878 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5882 if (used_at == 0 && mips_opts.at)
5884 macro_build (&offset_expr, "lui", "t,u",
5885 tempreg, BFD_RELOC_MIPS_HIGHEST);
5886 macro_build (&offset_expr, "lui", "t,u",
5887 AT, BFD_RELOC_HI16_S);
5888 macro_build (&offset_expr, "daddiu", "t,r,j",
5889 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5890 macro_build (&offset_expr, "daddiu", "t,r,j",
5891 AT, AT, BFD_RELOC_LO16);
5892 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
5893 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
5898 macro_build (&offset_expr, "lui", "t,u",
5899 tempreg, BFD_RELOC_MIPS_HIGHEST);
5900 macro_build (&offset_expr, "daddiu", "t,r,j",
5901 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5902 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5903 macro_build (&offset_expr, "daddiu", "t,r,j",
5904 tempreg, tempreg, BFD_RELOC_HI16_S);
5905 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5906 macro_build (&offset_expr, "daddiu", "t,r,j",
5907 tempreg, tempreg, BFD_RELOC_LO16);
5910 if (mips_relax.sequence)
5915 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5916 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5918 relax_start (offset_expr.X_add_symbol);
5919 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5920 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5923 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
5924 as_bad (_("Offset too large"));
5925 macro_build_lui (&offset_expr, tempreg);
5926 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5927 tempreg, tempreg, BFD_RELOC_LO16);
5928 if (mips_relax.sequence)
5932 else if (!mips_big_got && !HAVE_NEWABI)
5934 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5936 /* If this is a reference to an external symbol, and there
5937 is no constant, we want
5938 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5939 or for lca or if tempreg is PIC_CALL_REG
5940 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5941 For a local symbol, we want
5942 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5944 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5946 If we have a small constant, and this is a reference to
5947 an external symbol, we want
5948 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5950 addiu $tempreg,$tempreg,<constant>
5951 For a local symbol, we want the same instruction
5952 sequence, but we output a BFD_RELOC_LO16 reloc on the
5955 If we have a large constant, and this is a reference to
5956 an external symbol, we want
5957 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5958 lui $at,<hiconstant>
5959 addiu $at,$at,<loconstant>
5960 addu $tempreg,$tempreg,$at
5961 For a local symbol, we want the same instruction
5962 sequence, but we output a BFD_RELOC_LO16 reloc on the
5966 if (offset_expr.X_add_number == 0)
5968 if (mips_pic == SVR4_PIC
5970 && (call || tempreg == PIC_CALL_REG))
5971 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
5973 relax_start (offset_expr.X_add_symbol);
5974 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5975 lw_reloc_type, mips_gp_register);
5978 /* We're going to put in an addu instruction using
5979 tempreg, so we may as well insert the nop right
5984 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5985 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
5987 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5988 tempreg, tempreg, BFD_RELOC_LO16);
5990 /* FIXME: If breg == 0, and the next instruction uses
5991 $tempreg, then if this variant case is used an extra
5992 nop will be generated. */
5994 else if (offset_expr.X_add_number >= -0x8000
5995 && offset_expr.X_add_number < 0x8000)
5997 load_got_offset (tempreg, &offset_expr);
5999 add_got_offset (tempreg, &offset_expr);
6003 expr1.X_add_number = offset_expr.X_add_number;
6004 offset_expr.X_add_number =
6005 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
6006 load_got_offset (tempreg, &offset_expr);
6007 offset_expr.X_add_number = expr1.X_add_number;
6008 /* If we are going to add in a base register, and the
6009 target register and the base register are the same,
6010 then we are using AT as a temporary register. Since
6011 we want to load the constant into AT, we add our
6012 current AT (from the global offset table) and the
6013 register into the register now, and pretend we were
6014 not using a base register. */
6018 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6023 add_got_offset_hilo (tempreg, &offset_expr, AT);
6027 else if (!mips_big_got && HAVE_NEWABI)
6029 int add_breg_early = 0;
6031 /* If this is a reference to an external, and there is no
6032 constant, or local symbol (*), with or without a
6034 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6035 or for lca or if tempreg is PIC_CALL_REG
6036 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
6038 If we have a small constant, and this is a reference to
6039 an external symbol, we want
6040 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6041 addiu $tempreg,$tempreg,<constant>
6043 If we have a large constant, and this is a reference to
6044 an external symbol, we want
6045 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6046 lui $at,<hiconstant>
6047 addiu $at,$at,<loconstant>
6048 addu $tempreg,$tempreg,$at
6050 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
6051 local symbols, even though it introduces an additional
6054 if (offset_expr.X_add_number)
6056 expr1.X_add_number = offset_expr.X_add_number;
6057 offset_expr.X_add_number = 0;
6059 relax_start (offset_expr.X_add_symbol);
6060 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6061 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6063 if (expr1.X_add_number >= -0x8000
6064 && expr1.X_add_number < 0x8000)
6066 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
6067 tempreg, tempreg, BFD_RELOC_LO16);
6069 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
6071 /* If we are going to add in a base register, and the
6072 target register and the base register are the same,
6073 then we are using AT as a temporary register. Since
6074 we want to load the constant into AT, we add our
6075 current AT (from the global offset table) and the
6076 register into the register now, and pretend we were
6077 not using a base register. */
6082 gas_assert (tempreg == AT);
6083 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6089 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
6090 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6096 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
6099 offset_expr.X_add_number = expr1.X_add_number;
6101 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6102 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6105 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6106 treg, tempreg, breg);
6112 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
6114 relax_start (offset_expr.X_add_symbol);
6115 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6116 BFD_RELOC_MIPS_CALL16, mips_gp_register);
6118 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6119 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6124 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6125 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6128 else if (mips_big_got && !HAVE_NEWABI)
6131 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
6132 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
6133 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6135 /* This is the large GOT case. If this is a reference to an
6136 external symbol, and there is no constant, we want
6137 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6138 addu $tempreg,$tempreg,$gp
6139 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6140 or for lca or if tempreg is PIC_CALL_REG
6141 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6142 addu $tempreg,$tempreg,$gp
6143 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
6144 For a local symbol, we want
6145 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6147 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6149 If we have a small constant, and this is a reference to
6150 an external symbol, we want
6151 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6152 addu $tempreg,$tempreg,$gp
6153 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6155 addiu $tempreg,$tempreg,<constant>
6156 For a local symbol, we want
6157 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6159 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
6161 If we have a large constant, and this is a reference to
6162 an external symbol, we want
6163 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6164 addu $tempreg,$tempreg,$gp
6165 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6166 lui $at,<hiconstant>
6167 addiu $at,$at,<loconstant>
6168 addu $tempreg,$tempreg,$at
6169 For a local symbol, we want
6170 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6171 lui $at,<hiconstant>
6172 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
6173 addu $tempreg,$tempreg,$at
6176 expr1.X_add_number = offset_expr.X_add_number;
6177 offset_expr.X_add_number = 0;
6178 relax_start (offset_expr.X_add_symbol);
6179 gpdelay = reg_needs_delay (mips_gp_register);
6180 if (expr1.X_add_number == 0 && breg == 0
6181 && (call || tempreg == PIC_CALL_REG))
6183 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
6184 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
6186 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
6187 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6188 tempreg, tempreg, mips_gp_register);
6189 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6190 tempreg, lw_reloc_type, tempreg);
6191 if (expr1.X_add_number == 0)
6195 /* We're going to put in an addu instruction using
6196 tempreg, so we may as well insert the nop right
6201 else if (expr1.X_add_number >= -0x8000
6202 && expr1.X_add_number < 0x8000)
6205 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
6206 tempreg, tempreg, BFD_RELOC_LO16);
6210 /* If we are going to add in a base register, and the
6211 target register and the base register are the same,
6212 then we are using AT as a temporary register. Since
6213 we want to load the constant into AT, we add our
6214 current AT (from the global offset table) and the
6215 register into the register now, and pretend we were
6216 not using a base register. */
6221 gas_assert (tempreg == AT);
6223 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6228 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
6229 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
6233 offset_expr.X_add_number =
6234 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000;
6239 /* This is needed because this instruction uses $gp, but
6240 the first instruction on the main stream does not. */
6241 macro_build (NULL, "nop", "");
6244 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6245 local_reloc_type, mips_gp_register);
6246 if (expr1.X_add_number >= -0x8000
6247 && expr1.X_add_number < 0x8000)
6250 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6251 tempreg, tempreg, BFD_RELOC_LO16);
6252 /* FIXME: If add_number is 0, and there was no base
6253 register, the external symbol case ended with a load,
6254 so if the symbol turns out to not be external, and
6255 the next instruction uses tempreg, an unnecessary nop
6256 will be inserted. */
6262 /* We must add in the base register now, as in the
6263 external symbol case. */
6264 gas_assert (tempreg == AT);
6266 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6269 /* We set breg to 0 because we have arranged to add
6270 it in in both cases. */
6274 macro_build_lui (&expr1, AT);
6275 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6276 AT, AT, BFD_RELOC_LO16);
6277 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6278 tempreg, tempreg, AT);
6283 else if (mips_big_got && HAVE_NEWABI)
6285 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
6286 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
6287 int add_breg_early = 0;
6289 /* This is the large GOT case. If this is a reference to an
6290 external symbol, and there is no constant, we want
6291 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6292 add $tempreg,$tempreg,$gp
6293 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6294 or for lca or if tempreg is PIC_CALL_REG
6295 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6296 add $tempreg,$tempreg,$gp
6297 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
6299 If we have a small constant, and this is a reference to
6300 an external symbol, we want
6301 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6302 add $tempreg,$tempreg,$gp
6303 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6304 addi $tempreg,$tempreg,<constant>
6306 If we have a large constant, and this is a reference to
6307 an external symbol, we want
6308 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6309 addu $tempreg,$tempreg,$gp
6310 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6311 lui $at,<hiconstant>
6312 addi $at,$at,<loconstant>
6313 add $tempreg,$tempreg,$at
6315 If we have NewABI, and we know it's a local symbol, we want
6316 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6317 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6318 otherwise we have to resort to GOT_HI16/GOT_LO16. */
6320 relax_start (offset_expr.X_add_symbol);
6322 expr1.X_add_number = offset_expr.X_add_number;
6323 offset_expr.X_add_number = 0;
6325 if (expr1.X_add_number == 0 && breg == 0
6326 && (call || tempreg == PIC_CALL_REG))
6328 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
6329 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
6331 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
6332 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6333 tempreg, tempreg, mips_gp_register);
6334 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6335 tempreg, lw_reloc_type, tempreg);
6337 if (expr1.X_add_number == 0)
6339 else if (expr1.X_add_number >= -0x8000
6340 && expr1.X_add_number < 0x8000)
6342 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
6343 tempreg, tempreg, BFD_RELOC_LO16);
6345 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
6347 /* If we are going to add in a base register, and the
6348 target register and the base register are the same,
6349 then we are using AT as a temporary register. Since
6350 we want to load the constant into AT, we add our
6351 current AT (from the global offset table) and the
6352 register into the register now, and pretend we were
6353 not using a base register. */
6358 gas_assert (tempreg == AT);
6359 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6365 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
6366 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
6371 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
6374 offset_expr.X_add_number = expr1.X_add_number;
6375 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6376 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6377 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6378 tempreg, BFD_RELOC_MIPS_GOT_OFST);
6381 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6382 treg, tempreg, breg);
6392 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
6397 unsigned long temp = (treg << 16) | (0x01);
6398 macro_build (NULL, "c2", "C", temp);
6404 unsigned long temp = (0x02);
6405 macro_build (NULL, "c2", "C", temp);
6411 unsigned long temp = (treg << 16) | (0x02);
6412 macro_build (NULL, "c2", "C", temp);
6417 macro_build (NULL, "c2", "C", 3);
6422 unsigned long temp = (treg << 16) | 0x03;
6423 macro_build (NULL, "c2", "C", temp);
6428 /* The j instruction may not be used in PIC code, since it
6429 requires an absolute address. We convert it to a b
6431 if (mips_pic == NO_PIC)
6432 macro_build (&offset_expr, "j", "a");
6434 macro_build (&offset_expr, "b", "p");
6437 /* The jal instructions must be handled as macros because when
6438 generating PIC code they expand to multi-instruction
6439 sequences. Normally they are simple instructions. */
6444 if (mips_pic == NO_PIC)
6445 macro_build (NULL, "jalr", "d,s", dreg, sreg);
6448 if (sreg != PIC_CALL_REG)
6449 as_warn (_("MIPS PIC call to register other than $25"));
6451 macro_build (NULL, "jalr", "d,s", dreg, sreg);
6452 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
6454 if (mips_cprestore_offset < 0)
6455 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6458 if (!mips_frame_reg_valid)
6460 as_warn (_("No .frame pseudo-op used in PIC code"));
6461 /* Quiet this warning. */
6462 mips_frame_reg_valid = 1;
6464 if (!mips_cprestore_valid)
6466 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6467 /* Quiet this warning. */
6468 mips_cprestore_valid = 1;
6470 if (mips_opts.noreorder)
6471 macro_build (NULL, "nop", "");
6472 expr1.X_add_number = mips_cprestore_offset;
6473 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
6476 HAVE_64BIT_ADDRESSES);
6484 if (mips_pic == NO_PIC)
6485 macro_build (&offset_expr, "jal", "a");
6486 else if (mips_pic == SVR4_PIC)
6488 /* If this is a reference to an external symbol, and we are
6489 using a small GOT, we want
6490 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
6494 lw $gp,cprestore($sp)
6495 The cprestore value is set using the .cprestore
6496 pseudo-op. If we are using a big GOT, we want
6497 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6499 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
6503 lw $gp,cprestore($sp)
6504 If the symbol is not external, we want
6505 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6507 addiu $25,$25,<sym> (BFD_RELOC_LO16)
6510 lw $gp,cprestore($sp)
6512 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
6513 sequences above, minus nops, unless the symbol is local,
6514 which enables us to use GOT_PAGE/GOT_OFST (big got) or
6520 relax_start (offset_expr.X_add_symbol);
6521 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6522 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
6525 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6526 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
6532 relax_start (offset_expr.X_add_symbol);
6533 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
6534 BFD_RELOC_MIPS_CALL_HI16);
6535 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
6536 PIC_CALL_REG, mips_gp_register);
6537 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6538 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
6541 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6542 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
6544 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6545 PIC_CALL_REG, PIC_CALL_REG,
6546 BFD_RELOC_MIPS_GOT_OFST);
6550 macro_build_jalr (&offset_expr);
6554 relax_start (offset_expr.X_add_symbol);
6557 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6558 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
6567 gpdelay = reg_needs_delay (mips_gp_register);
6568 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
6569 BFD_RELOC_MIPS_CALL_HI16);
6570 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
6571 PIC_CALL_REG, mips_gp_register);
6572 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6573 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
6578 macro_build (NULL, "nop", "");
6580 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6581 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
6584 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6585 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
6587 macro_build_jalr (&offset_expr);
6589 if (mips_cprestore_offset < 0)
6590 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6593 if (!mips_frame_reg_valid)
6595 as_warn (_("No .frame pseudo-op used in PIC code"));
6596 /* Quiet this warning. */
6597 mips_frame_reg_valid = 1;
6599 if (!mips_cprestore_valid)
6601 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6602 /* Quiet this warning. */
6603 mips_cprestore_valid = 1;
6605 if (mips_opts.noreorder)
6606 macro_build (NULL, "nop", "");
6607 expr1.X_add_number = mips_cprestore_offset;
6608 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
6611 HAVE_64BIT_ADDRESSES);
6615 else if (mips_pic == VXWORKS_PIC)
6616 as_bad (_("Non-PIC jump used in PIC library"));
6639 /* Itbl support may require additional care here. */
6644 /* Itbl support may require additional care here. */
6649 /* Itbl support may require additional care here. */
6654 /* Itbl support may require additional care here. */
6667 /* Itbl support may require additional care here. */
6672 /* Itbl support may require additional care here. */
6677 /* Itbl support may require additional care here. */
6697 if (breg == treg || coproc || lr)
6718 /* Itbl support may require additional care here. */
6723 /* Itbl support may require additional care here. */
6728 /* Itbl support may require additional care here. */
6733 /* Itbl support may require additional care here. */
6757 /* Itbl support may require additional care here. */
6761 /* Itbl support may require additional care here. */
6766 /* Itbl support may require additional care here. */
6779 && NO_ISA_COP (mips_opts.arch)
6780 && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0)
6782 as_bad (_("Opcode not supported on this processor: %s"),
6783 mips_cpu_info_from_arch (mips_opts.arch)->name);
6787 /* Itbl support may require additional care here. */
6788 if (mask == M_LWC1_AB
6789 || mask == M_SWC1_AB
6790 || mask == M_LDC1_AB
6791 || mask == M_SDC1_AB
6795 else if (mask == M_CACHE_AB || mask == M_PREF_AB)
6802 if (offset_expr.X_op != O_constant
6803 && offset_expr.X_op != O_symbol)
6805 as_bad (_("Expression too complex"));
6806 offset_expr.X_op = O_constant;
6809 if (HAVE_32BIT_ADDRESSES
6810 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
6814 sprintf_vma (value, offset_expr.X_add_number);
6815 as_bad (_("Number (0x%s) larger than 32 bits"), value);
6818 /* A constant expression in PIC code can be handled just as it
6819 is in non PIC code. */
6820 if (offset_expr.X_op == O_constant)
6822 expr1.X_add_number = offset_expr.X_add_number;
6823 normalize_address_expr (&expr1);
6824 if (!IS_SEXT_16BIT_NUM (expr1.X_add_number))
6826 expr1.X_add_number = ((expr1.X_add_number + 0x8000)
6827 & ~(bfd_vma) 0xffff);
6828 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
6830 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6831 tempreg, tempreg, breg);
6834 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg);
6836 else if (mips_pic == NO_PIC)
6838 /* If this is a reference to a GP relative symbol, and there
6839 is no base register, we want
6840 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6841 Otherwise, if there is no base register, we want
6842 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6843 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6844 If we have a constant, we need two instructions anyhow,
6845 so we always use the latter form.
6847 If we have a base register, and this is a reference to a
6848 GP relative symbol, we want
6849 addu $tempreg,$breg,$gp
6850 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6852 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6853 addu $tempreg,$tempreg,$breg
6854 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6855 With a constant we always use the latter case.
6857 With 64bit address space and no base register and $at usable,
6859 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6860 lui $at,<sym> (BFD_RELOC_HI16_S)
6861 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6864 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6865 If we have a base register, we want
6866 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6867 lui $at,<sym> (BFD_RELOC_HI16_S)
6868 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6872 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6874 Without $at we can't generate the optimal path for superscalar
6875 processors here since this would require two temporary registers.
6876 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6877 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6879 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6881 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6882 If we have a base register, we want
6883 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6884 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6886 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6888 daddu $tempreg,$tempreg,$breg
6889 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6891 For GP relative symbols in 64bit address space we can use
6892 the same sequence as in 32bit address space. */
6893 if (HAVE_64BIT_SYMBOLS)
6895 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6896 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6898 relax_start (offset_expr.X_add_symbol);
6901 macro_build (&offset_expr, s, fmt, treg,
6902 BFD_RELOC_GPREL16, mips_gp_register);
6906 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6907 tempreg, breg, mips_gp_register);
6908 macro_build (&offset_expr, s, fmt, treg,
6909 BFD_RELOC_GPREL16, tempreg);
6914 if (used_at == 0 && mips_opts.at)
6916 macro_build (&offset_expr, "lui", "t,u", tempreg,
6917 BFD_RELOC_MIPS_HIGHEST);
6918 macro_build (&offset_expr, "lui", "t,u", AT,
6920 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6921 tempreg, BFD_RELOC_MIPS_HIGHER);
6923 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
6924 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
6925 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
6926 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
6932 macro_build (&offset_expr, "lui", "t,u", tempreg,
6933 BFD_RELOC_MIPS_HIGHEST);
6934 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6935 tempreg, BFD_RELOC_MIPS_HIGHER);
6936 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6937 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6938 tempreg, BFD_RELOC_HI16_S);
6939 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6941 macro_build (NULL, "daddu", "d,v,t",
6942 tempreg, tempreg, breg);
6943 macro_build (&offset_expr, s, fmt, treg,
6944 BFD_RELOC_LO16, tempreg);
6947 if (mips_relax.sequence)
6954 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6955 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6957 relax_start (offset_expr.X_add_symbol);
6958 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
6962 macro_build_lui (&offset_expr, tempreg);
6963 macro_build (&offset_expr, s, fmt, treg,
6964 BFD_RELOC_LO16, tempreg);
6965 if (mips_relax.sequence)
6970 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6971 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6973 relax_start (offset_expr.X_add_symbol);
6974 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6975 tempreg, breg, mips_gp_register);
6976 macro_build (&offset_expr, s, fmt, treg,
6977 BFD_RELOC_GPREL16, tempreg);
6980 macro_build_lui (&offset_expr, tempreg);
6981 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6982 tempreg, tempreg, breg);
6983 macro_build (&offset_expr, s, fmt, treg,
6984 BFD_RELOC_LO16, tempreg);
6985 if (mips_relax.sequence)
6989 else if (!mips_big_got)
6991 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6993 /* If this is a reference to an external symbol, we want
6994 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6996 <op> $treg,0($tempreg)
6998 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7000 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7001 <op> $treg,0($tempreg)
7004 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7005 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
7007 If there is a base register, we add it to $tempreg before
7008 the <op>. If there is a constant, we stick it in the
7009 <op> instruction. We don't handle constants larger than
7010 16 bits, because we have no way to load the upper 16 bits
7011 (actually, we could handle them for the subset of cases
7012 in which we are not using $at). */
7013 gas_assert (offset_expr.X_op == O_symbol);
7016 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7017 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
7019 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7020 tempreg, tempreg, breg);
7021 macro_build (&offset_expr, s, fmt, treg,
7022 BFD_RELOC_MIPS_GOT_OFST, tempreg);
7025 expr1.X_add_number = offset_expr.X_add_number;
7026 offset_expr.X_add_number = 0;
7027 if (expr1.X_add_number < -0x8000
7028 || expr1.X_add_number >= 0x8000)
7029 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7030 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7031 lw_reloc_type, mips_gp_register);
7033 relax_start (offset_expr.X_add_symbol);
7035 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
7036 tempreg, BFD_RELOC_LO16);
7039 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7040 tempreg, tempreg, breg);
7041 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
7043 else if (mips_big_got && !HAVE_NEWABI)
7047 /* If this is a reference to an external symbol, we want
7048 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7049 addu $tempreg,$tempreg,$gp
7050 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7051 <op> $treg,0($tempreg)
7053 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7055 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7056 <op> $treg,0($tempreg)
7057 If there is a base register, we add it to $tempreg before
7058 the <op>. If there is a constant, we stick it in the
7059 <op> instruction. We don't handle constants larger than
7060 16 bits, because we have no way to load the upper 16 bits
7061 (actually, we could handle them for the subset of cases
7062 in which we are not using $at). */
7063 gas_assert (offset_expr.X_op == O_symbol);
7064 expr1.X_add_number = offset_expr.X_add_number;
7065 offset_expr.X_add_number = 0;
7066 if (expr1.X_add_number < -0x8000
7067 || expr1.X_add_number >= 0x8000)
7068 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7069 gpdelay = reg_needs_delay (mips_gp_register);
7070 relax_start (offset_expr.X_add_symbol);
7071 macro_build (&offset_expr, "lui", "t,u", tempreg,
7072 BFD_RELOC_MIPS_GOT_HI16);
7073 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
7075 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7076 BFD_RELOC_MIPS_GOT_LO16, tempreg);
7079 macro_build (NULL, "nop", "");
7080 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7081 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7083 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
7084 tempreg, BFD_RELOC_LO16);
7088 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7089 tempreg, tempreg, breg);
7090 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
7092 else if (mips_big_got && HAVE_NEWABI)
7094 /* If this is a reference to an external symbol, we want
7095 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7096 add $tempreg,$tempreg,$gp
7097 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7098 <op> $treg,<ofst>($tempreg)
7099 Otherwise, for local symbols, we want:
7100 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7101 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
7102 gas_assert (offset_expr.X_op == O_symbol);
7103 expr1.X_add_number = offset_expr.X_add_number;
7104 offset_expr.X_add_number = 0;
7105 if (expr1.X_add_number < -0x8000
7106 || expr1.X_add_number >= 0x8000)
7107 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7108 relax_start (offset_expr.X_add_symbol);
7109 macro_build (&offset_expr, "lui", "t,u", tempreg,
7110 BFD_RELOC_MIPS_GOT_HI16);
7111 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
7113 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7114 BFD_RELOC_MIPS_GOT_LO16, tempreg);
7116 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7117 tempreg, tempreg, breg);
7118 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
7121 offset_expr.X_add_number = expr1.X_add_number;
7122 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7123 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
7125 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7126 tempreg, tempreg, breg);
7127 macro_build (&offset_expr, s, fmt, treg,
7128 BFD_RELOC_MIPS_GOT_OFST, tempreg);
7138 load_register (treg, &imm_expr, 0);
7142 load_register (treg, &imm_expr, 1);
7146 if (imm_expr.X_op == O_constant)
7149 load_register (AT, &imm_expr, 0);
7150 macro_build (NULL, "mtc1", "t,G", AT, treg);
7155 gas_assert (offset_expr.X_op == O_symbol
7156 && strcmp (segment_name (S_GET_SEGMENT
7157 (offset_expr.X_add_symbol)),
7159 && offset_expr.X_add_number == 0);
7160 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
7161 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
7166 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
7167 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
7168 order 32 bits of the value and the low order 32 bits are either
7169 zero or in OFFSET_EXPR. */
7170 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
7172 if (HAVE_64BIT_GPRS)
7173 load_register (treg, &imm_expr, 1);
7178 if (target_big_endian)
7190 load_register (hreg, &imm_expr, 0);
7193 if (offset_expr.X_op == O_absent)
7194 move_register (lreg, 0);
7197 gas_assert (offset_expr.X_op == O_constant);
7198 load_register (lreg, &offset_expr, 0);
7205 /* We know that sym is in the .rdata section. First we get the
7206 upper 16 bits of the address. */
7207 if (mips_pic == NO_PIC)
7209 macro_build_lui (&offset_expr, AT);
7214 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7215 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7219 /* Now we load the register(s). */
7220 if (HAVE_64BIT_GPRS)
7223 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7228 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7231 /* FIXME: How in the world do we deal with the possible
7233 offset_expr.X_add_number += 4;
7234 macro_build (&offset_expr, "lw", "t,o(b)",
7235 treg + 1, BFD_RELOC_LO16, AT);
7241 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
7242 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
7243 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
7244 the value and the low order 32 bits are either zero or in
7246 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
7249 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
7250 if (HAVE_64BIT_FPRS)
7252 gas_assert (HAVE_64BIT_GPRS);
7253 macro_build (NULL, "dmtc1", "t,S", AT, treg);
7257 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
7258 if (offset_expr.X_op == O_absent)
7259 macro_build (NULL, "mtc1", "t,G", 0, treg);
7262 gas_assert (offset_expr.X_op == O_constant);
7263 load_register (AT, &offset_expr, 0);
7264 macro_build (NULL, "mtc1", "t,G", AT, treg);
7270 gas_assert (offset_expr.X_op == O_symbol
7271 && offset_expr.X_add_number == 0);
7272 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
7273 if (strcmp (s, ".lit8") == 0)
7275 if (mips_opts.isa != ISA_MIPS1)
7277 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
7278 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
7281 breg = mips_gp_register;
7282 r = BFD_RELOC_MIPS_LITERAL;
7287 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
7289 if (mips_pic != NO_PIC)
7290 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7291 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7294 /* FIXME: This won't work for a 64 bit address. */
7295 macro_build_lui (&offset_expr, AT);
7298 if (mips_opts.isa != ISA_MIPS1)
7300 macro_build (&offset_expr, "ldc1", "T,o(b)",
7301 treg, BFD_RELOC_LO16, AT);
7310 /* Even on a big endian machine $fn comes before $fn+1. We have
7311 to adjust when loading from memory. */
7314 gas_assert (mips_opts.isa == ISA_MIPS1);
7315 macro_build (&offset_expr, "lwc1", "T,o(b)",
7316 target_big_endian ? treg + 1 : treg, r, breg);
7317 /* FIXME: A possible overflow which I don't know how to deal
7319 offset_expr.X_add_number += 4;
7320 macro_build (&offset_expr, "lwc1", "T,o(b)",
7321 target_big_endian ? treg : treg + 1, r, breg);
7325 gas_assert (mips_opts.isa == ISA_MIPS1);
7326 /* Even on a big endian machine $fn comes before $fn+1. We have
7327 to adjust when storing to memory. */
7328 macro_build (&offset_expr, "swc1", "T,o(b)",
7329 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
7330 offset_expr.X_add_number += 4;
7331 macro_build (&offset_expr, "swc1", "T,o(b)",
7332 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
7337 * The MIPS assembler seems to check for X_add_number not
7338 * being double aligned and generating:
7341 * addiu at,at,%lo(foo+1)
7344 * But, the resulting address is the same after relocation so why
7345 * generate the extra instruction?
7347 /* Itbl support may require additional care here. */
7349 if (mips_opts.isa != ISA_MIPS1)
7360 if (mips_opts.isa != ISA_MIPS1)
7368 /* Itbl support may require additional care here. */
7373 if (HAVE_64BIT_GPRS)
7384 if (HAVE_64BIT_GPRS)
7394 if (offset_expr.X_op != O_symbol
7395 && offset_expr.X_op != O_constant)
7397 as_bad (_("Expression too complex"));
7398 offset_expr.X_op = O_constant;
7401 if (HAVE_32BIT_ADDRESSES
7402 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
7406 sprintf_vma (value, offset_expr.X_add_number);
7407 as_bad (_("Number (0x%s) larger than 32 bits"), value);
7410 /* Even on a big endian machine $fn comes before $fn+1. We have
7411 to adjust when loading from memory. We set coproc if we must
7412 load $fn+1 first. */
7413 /* Itbl support may require additional care here. */
7414 if (!target_big_endian)
7417 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
7419 /* If this is a reference to a GP relative symbol, we want
7420 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
7421 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
7422 If we have a base register, we use this
7424 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
7425 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
7426 If this is not a GP relative symbol, we want
7427 lui $at,<sym> (BFD_RELOC_HI16_S)
7428 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7429 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7430 If there is a base register, we add it to $at after the
7431 lui instruction. If there is a constant, we always use
7433 if (offset_expr.X_op == O_symbol
7434 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7435 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7437 relax_start (offset_expr.X_add_symbol);
7440 tempreg = mips_gp_register;
7444 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7445 AT, breg, mips_gp_register);
7450 /* Itbl support may require additional care here. */
7451 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7452 BFD_RELOC_GPREL16, tempreg);
7453 offset_expr.X_add_number += 4;
7455 /* Set mips_optimize to 2 to avoid inserting an
7457 hold_mips_optimize = mips_optimize;
7459 /* Itbl support may require additional care here. */
7460 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7461 BFD_RELOC_GPREL16, tempreg);
7462 mips_optimize = hold_mips_optimize;
7466 offset_expr.X_add_number -= 4;
7469 macro_build_lui (&offset_expr, AT);
7471 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7472 /* Itbl support may require additional care here. */
7473 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7474 BFD_RELOC_LO16, AT);
7475 /* FIXME: How do we handle overflow here? */
7476 offset_expr.X_add_number += 4;
7477 /* Itbl support may require additional care here. */
7478 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7479 BFD_RELOC_LO16, AT);
7480 if (mips_relax.sequence)
7483 else if (!mips_big_got)
7485 /* If this is a reference to an external symbol, we want
7486 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7491 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7493 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7494 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7495 If there is a base register we add it to $at before the
7496 lwc1 instructions. If there is a constant we include it
7497 in the lwc1 instructions. */
7499 expr1.X_add_number = offset_expr.X_add_number;
7500 if (expr1.X_add_number < -0x8000
7501 || expr1.X_add_number >= 0x8000 - 4)
7502 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7503 load_got_offset (AT, &offset_expr);
7506 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7508 /* Set mips_optimize to 2 to avoid inserting an undesired
7510 hold_mips_optimize = mips_optimize;
7513 /* Itbl support may require additional care here. */
7514 relax_start (offset_expr.X_add_symbol);
7515 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
7516 BFD_RELOC_LO16, AT);
7517 expr1.X_add_number += 4;
7518 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
7519 BFD_RELOC_LO16, AT);
7521 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7522 BFD_RELOC_LO16, AT);
7523 offset_expr.X_add_number += 4;
7524 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7525 BFD_RELOC_LO16, AT);
7528 mips_optimize = hold_mips_optimize;
7530 else if (mips_big_got)
7534 /* If this is a reference to an external symbol, we want
7535 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7537 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
7542 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7544 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7545 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7546 If there is a base register we add it to $at before the
7547 lwc1 instructions. If there is a constant we include it
7548 in the lwc1 instructions. */
7550 expr1.X_add_number = offset_expr.X_add_number;
7551 offset_expr.X_add_number = 0;
7552 if (expr1.X_add_number < -0x8000
7553 || expr1.X_add_number >= 0x8000 - 4)
7554 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7555 gpdelay = reg_needs_delay (mips_gp_register);
7556 relax_start (offset_expr.X_add_symbol);
7557 macro_build (&offset_expr, "lui", "t,u",
7558 AT, BFD_RELOC_MIPS_GOT_HI16);
7559 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7560 AT, AT, mips_gp_register);
7561 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7562 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
7565 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7566 /* Itbl support may require additional care here. */
7567 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
7568 BFD_RELOC_LO16, AT);
7569 expr1.X_add_number += 4;
7571 /* Set mips_optimize to 2 to avoid inserting an undesired
7573 hold_mips_optimize = mips_optimize;
7575 /* Itbl support may require additional care here. */
7576 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
7577 BFD_RELOC_LO16, AT);
7578 mips_optimize = hold_mips_optimize;
7579 expr1.X_add_number -= 4;
7582 offset_expr.X_add_number = expr1.X_add_number;
7584 macro_build (NULL, "nop", "");
7585 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7586 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7589 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7590 /* Itbl support may require additional care here. */
7591 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7592 BFD_RELOC_LO16, AT);
7593 offset_expr.X_add_number += 4;
7595 /* Set mips_optimize to 2 to avoid inserting an undesired
7597 hold_mips_optimize = mips_optimize;
7599 /* Itbl support may require additional care here. */
7600 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7601 BFD_RELOC_LO16, AT);
7602 mips_optimize = hold_mips_optimize;
7611 s = HAVE_64BIT_GPRS ? "ld" : "lw";
7614 s = HAVE_64BIT_GPRS ? "sd" : "sw";
7616 macro_build (&offset_expr, s, "t,o(b)", treg,
7617 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
7619 if (!HAVE_64BIT_GPRS)
7621 offset_expr.X_add_number += 4;
7622 macro_build (&offset_expr, s, "t,o(b)", treg + 1,
7623 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
7628 /* New code added to support COPZ instructions.
7629 This code builds table entries out of the macros in mip_opcodes.
7630 R4000 uses interlocks to handle coproc delays.
7631 Other chips (like the R3000) require nops to be inserted for delays.
7633 FIXME: Currently, we require that the user handle delays.
7634 In order to fill delay slots for non-interlocked chips,
7635 we must have a way to specify delays based on the coprocessor.
7636 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7637 What are the side-effects of the cop instruction?
7638 What cache support might we have and what are its effects?
7639 Both coprocessor & memory require delays. how long???
7640 What registers are read/set/modified?
7642 If an itbl is provided to interpret cop instructions,
7643 this knowledge can be encoded in the itbl spec. */
7657 if (NO_ISA_COP (mips_opts.arch)
7658 && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0)
7660 as_bad (_("opcode not supported on this processor: %s"),
7661 mips_cpu_info_from_arch (mips_opts.arch)->name);
7665 /* For now we just do C (same as Cz). The parameter will be
7666 stored in insn_opcode by mips_ip. */
7667 macro_build (NULL, s, "C", ip->insn_opcode);
7671 move_register (dreg, sreg);
7677 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
7678 macro_build (NULL, "mflo", "d", dreg);
7684 /* The MIPS assembler some times generates shifts and adds. I'm
7685 not trying to be that fancy. GCC should do this for us
7688 load_register (AT, &imm_expr, dbl);
7689 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
7690 macro_build (NULL, "mflo", "d", dreg);
7706 load_register (AT, &imm_expr, dbl);
7707 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
7708 macro_build (NULL, "mflo", "d", dreg);
7709 macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
7710 macro_build (NULL, "mfhi", "d", AT);
7712 macro_build (NULL, "tne", "s,t,q", dreg, AT, 6);
7715 expr1.X_add_number = 8;
7716 macro_build (&expr1, "beq", "s,t,p", dreg, AT);
7717 macro_build (NULL, "nop", "");
7718 macro_build (NULL, "break", "c", 6);
7721 macro_build (NULL, "mflo", "d", dreg);
7737 load_register (AT, &imm_expr, dbl);
7738 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
7739 sreg, imm ? AT : treg);
7740 macro_build (NULL, "mfhi", "d", AT);
7741 macro_build (NULL, "mflo", "d", dreg);
7743 macro_build (NULL, "tne", "s,t,q", AT, ZERO, 6);
7746 expr1.X_add_number = 8;
7747 macro_build (&expr1, "beq", "s,t,p", AT, ZERO);
7748 macro_build (NULL, "nop", "");
7749 macro_build (NULL, "break", "c", 6);
7755 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7766 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
7767 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
7771 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
7772 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
7773 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
7774 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7778 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7789 macro_build (NULL, "negu", "d,w", tempreg, treg);
7790 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
7794 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
7795 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
7796 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
7797 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7806 if (imm_expr.X_op != O_constant)
7807 as_bad (_("Improper rotate count"));
7808 rot = imm_expr.X_add_number & 0x3f;
7809 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7811 rot = (64 - rot) & 0x3f;
7813 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7815 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7820 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7823 l = (rot < 0x20) ? "dsll" : "dsll32";
7824 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
7827 macro_build (NULL, l, "d,w,<", AT, sreg, rot);
7828 macro_build (NULL, rr, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7829 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7837 if (imm_expr.X_op != O_constant)
7838 as_bad (_("Improper rotate count"));
7839 rot = imm_expr.X_add_number & 0x1f;
7840 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7842 macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f);
7847 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7851 macro_build (NULL, "sll", "d,w,<", AT, sreg, rot);
7852 macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7853 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7858 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7860 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
7864 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
7865 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
7866 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
7867 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7871 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7873 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
7877 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
7878 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
7879 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
7880 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7889 if (imm_expr.X_op != O_constant)
7890 as_bad (_("Improper rotate count"));
7891 rot = imm_expr.X_add_number & 0x3f;
7892 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7895 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7897 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7902 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7905 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
7906 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7909 macro_build (NULL, rr, "d,w,<", AT, sreg, rot);
7910 macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7911 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7919 if (imm_expr.X_op != O_constant)
7920 as_bad (_("Improper rotate count"));
7921 rot = imm_expr.X_add_number & 0x1f;
7922 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7924 macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot);
7929 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7933 macro_build (NULL, "srl", "d,w,<", AT, sreg, rot);
7934 macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7935 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7941 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
7943 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7946 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7947 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7952 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7954 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7959 as_warn (_("Instruction %s: result is always false"),
7961 move_register (dreg, 0);
7964 if (CPU_HAS_SEQ (mips_opts.arch)
7965 && -512 <= imm_expr.X_add_number
7966 && imm_expr.X_add_number < 512)
7968 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
7969 (int) imm_expr.X_add_number);
7972 if (imm_expr.X_op == O_constant
7973 && imm_expr.X_add_number >= 0
7974 && imm_expr.X_add_number < 0x10000)
7976 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7978 else if (imm_expr.X_op == O_constant
7979 && imm_expr.X_add_number > -0x8000
7980 && imm_expr.X_add_number < 0)
7982 imm_expr.X_add_number = -imm_expr.X_add_number;
7983 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7984 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7986 else if (CPU_HAS_SEQ (mips_opts.arch))
7989 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7990 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
7995 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7996 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7999 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
8002 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
8008 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
8009 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
8012 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
8014 if (imm_expr.X_op == O_constant
8015 && imm_expr.X_add_number >= -0x8000
8016 && imm_expr.X_add_number < 0x8000)
8018 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
8019 dreg, sreg, BFD_RELOC_LO16);
8023 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8024 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
8028 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
8031 case M_SGT: /* sreg > treg <==> treg < sreg */
8037 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
8040 case M_SGT_I: /* sreg > I <==> I < sreg */
8047 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8048 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
8051 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
8057 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
8058 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
8061 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
8068 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8069 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
8070 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
8074 if (imm_expr.X_op == O_constant
8075 && imm_expr.X_add_number >= -0x8000
8076 && imm_expr.X_add_number < 0x8000)
8078 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
8082 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8083 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
8087 if (imm_expr.X_op == O_constant
8088 && imm_expr.X_add_number >= -0x8000
8089 && imm_expr.X_add_number < 0x8000)
8091 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
8096 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8097 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
8102 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
8104 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
8107 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
8108 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
8113 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
8115 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
8120 as_warn (_("Instruction %s: result is always true"),
8122 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
8123 dreg, 0, BFD_RELOC_LO16);
8126 if (CPU_HAS_SEQ (mips_opts.arch)
8127 && -512 <= imm_expr.X_add_number
8128 && imm_expr.X_add_number < 512)
8130 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
8131 (int) imm_expr.X_add_number);
8134 if (imm_expr.X_op == O_constant
8135 && imm_expr.X_add_number >= 0
8136 && imm_expr.X_add_number < 0x10000)
8138 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
8140 else if (imm_expr.X_op == O_constant
8141 && imm_expr.X_add_number > -0x8000
8142 && imm_expr.X_add_number < 0)
8144 imm_expr.X_add_number = -imm_expr.X_add_number;
8145 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
8146 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
8148 else if (CPU_HAS_SEQ (mips_opts.arch))
8151 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8152 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
8157 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8158 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
8161 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
8167 if (imm_expr.X_op == O_constant
8168 && imm_expr.X_add_number > -0x8000
8169 && imm_expr.X_add_number <= 0x8000)
8171 imm_expr.X_add_number = -imm_expr.X_add_number;
8172 macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j",
8173 dreg, sreg, BFD_RELOC_LO16);
8177 load_register (AT, &imm_expr, dbl);
8178 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
8184 if (imm_expr.X_op == O_constant
8185 && imm_expr.X_add_number > -0x8000
8186 && imm_expr.X_add_number <= 0x8000)
8188 imm_expr.X_add_number = -imm_expr.X_add_number;
8189 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j",
8190 dreg, sreg, BFD_RELOC_LO16);
8194 load_register (AT, &imm_expr, dbl);
8195 macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
8217 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8218 macro_build (NULL, s, "s,t", sreg, AT);
8223 gas_assert (mips_opts.isa == ISA_MIPS1);
8225 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
8226 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
8229 * Is the double cfc1 instruction a bug in the mips assembler;
8230 * or is there a reason for it?
8233 macro_build (NULL, "cfc1", "t,G", treg, RA);
8234 macro_build (NULL, "cfc1", "t,G", treg, RA);
8235 macro_build (NULL, "nop", "");
8236 expr1.X_add_number = 3;
8237 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
8238 expr1.X_add_number = 2;
8239 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
8240 macro_build (NULL, "ctc1", "t,G", AT, RA);
8241 macro_build (NULL, "nop", "");
8242 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
8244 macro_build (NULL, "ctc1", "t,G", treg, RA);
8245 macro_build (NULL, "nop", "");
8256 if (offset_expr.X_add_number >= 0x7fff)
8257 as_bad (_("Operand overflow"));
8258 if (!target_big_endian)
8259 ++offset_expr.X_add_number;
8260 macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg);
8261 if (!target_big_endian)
8262 --offset_expr.X_add_number;
8264 ++offset_expr.X_add_number;
8265 macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg);
8266 macro_build (NULL, "sll", "d,w,<", AT, AT, 8);
8267 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8280 if (offset_expr.X_add_number >= 0x8000 - off)
8281 as_bad (_("Operand overflow"));
8289 if (!target_big_endian)
8290 offset_expr.X_add_number += off;
8291 macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
8292 if (!target_big_endian)
8293 offset_expr.X_add_number -= off;
8295 offset_expr.X_add_number += off;
8296 macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
8298 /* If necessary, move the result in tempreg to the final destination. */
8299 if (treg == tempreg)
8301 /* Protect second load's delay slot. */
8303 move_register (treg, tempreg);
8317 load_address (AT, &offset_expr, &used_at);
8319 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8320 if (!target_big_endian)
8321 expr1.X_add_number = off;
8323 expr1.X_add_number = 0;
8324 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8325 if (!target_big_endian)
8326 expr1.X_add_number = 0;
8328 expr1.X_add_number = off;
8329 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8335 load_address (AT, &offset_expr, &used_at);
8337 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8338 if (target_big_endian)
8339 expr1.X_add_number = 0;
8340 macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
8341 treg, BFD_RELOC_LO16, AT);
8342 if (target_big_endian)
8343 expr1.X_add_number = 1;
8345 expr1.X_add_number = 0;
8346 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
8347 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
8348 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8353 if (offset_expr.X_add_number >= 0x7fff)
8354 as_bad (_("Operand overflow"));
8355 if (target_big_endian)
8356 ++offset_expr.X_add_number;
8357 macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg);
8358 macro_build (NULL, "srl", "d,w,<", AT, treg, 8);
8359 if (target_big_endian)
8360 --offset_expr.X_add_number;
8362 ++offset_expr.X_add_number;
8363 macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg);
8376 if (offset_expr.X_add_number >= 0x8000 - off)
8377 as_bad (_("Operand overflow"));
8378 if (!target_big_endian)
8379 offset_expr.X_add_number += off;
8380 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8381 if (!target_big_endian)
8382 offset_expr.X_add_number -= off;
8384 offset_expr.X_add_number += off;
8385 macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8399 load_address (AT, &offset_expr, &used_at);
8401 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8402 if (!target_big_endian)
8403 expr1.X_add_number = off;
8405 expr1.X_add_number = 0;
8406 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8407 if (!target_big_endian)
8408 expr1.X_add_number = 0;
8410 expr1.X_add_number = off;
8411 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8416 load_address (AT, &offset_expr, &used_at);
8418 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8419 if (!target_big_endian)
8420 expr1.X_add_number = 0;
8421 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8422 macro_build (NULL, "srl", "d,w,<", treg, treg, 8);
8423 if (!target_big_endian)
8424 expr1.X_add_number = 1;
8426 expr1.X_add_number = 0;
8427 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8428 if (!target_big_endian)
8429 expr1.X_add_number = 0;
8431 expr1.X_add_number = 1;
8432 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
8433 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
8434 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8438 /* FIXME: Check if this is one of the itbl macros, since they
8439 are added dynamically. */
8440 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
8443 if (!mips_opts.at && used_at)
8444 as_bad (_("Macro used $at after \".set noat\""));
8447 /* Implement macros in mips16 mode. */
8450 mips16_macro (struct mips_cl_insn *ip)
8453 int xreg, yreg, zreg, tmp;
8456 const char *s, *s2, *s3;
8458 mask = ip->insn_mo->mask;
8460 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
8461 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
8462 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
8464 expr1.X_op = O_constant;
8465 expr1.X_op_symbol = NULL;
8466 expr1.X_add_symbol = NULL;
8467 expr1.X_add_number = 1;
8487 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
8488 expr1.X_add_number = 2;
8489 macro_build (&expr1, "bnez", "x,p", yreg);
8490 macro_build (NULL, "break", "6", 7);
8492 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
8493 since that causes an overflow. We should do that as well,
8494 but I don't see how to do the comparisons without a temporary
8497 macro_build (NULL, s, "x", zreg);
8517 macro_build (NULL, s, "0,x,y", xreg, yreg);
8518 expr1.X_add_number = 2;
8519 macro_build (&expr1, "bnez", "x,p", yreg);
8520 macro_build (NULL, "break", "6", 7);
8522 macro_build (NULL, s2, "x", zreg);
8528 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
8529 macro_build (NULL, "mflo", "x", zreg);
8537 if (imm_expr.X_op != O_constant)
8538 as_bad (_("Unsupported large constant"));
8539 imm_expr.X_add_number = -imm_expr.X_add_number;
8540 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
8544 if (imm_expr.X_op != O_constant)
8545 as_bad (_("Unsupported large constant"));
8546 imm_expr.X_add_number = -imm_expr.X_add_number;
8547 macro_build (&imm_expr, "addiu", "x,k", xreg);
8551 if (imm_expr.X_op != O_constant)
8552 as_bad (_("Unsupported large constant"));
8553 imm_expr.X_add_number = -imm_expr.X_add_number;
8554 macro_build (&imm_expr, "daddiu", "y,j", yreg);
8576 goto do_reverse_branch;
8580 goto do_reverse_branch;
8592 goto do_reverse_branch;
8603 macro_build (NULL, s, "x,y", xreg, yreg);
8604 macro_build (&offset_expr, s2, "p");
8631 goto do_addone_branch_i;
8636 goto do_addone_branch_i;
8651 goto do_addone_branch_i;
8658 if (imm_expr.X_op != O_constant)
8659 as_bad (_("Unsupported large constant"));
8660 ++imm_expr.X_add_number;
8663 macro_build (&imm_expr, s, s3, xreg);
8664 macro_build (&offset_expr, s2, "p");
8668 expr1.X_add_number = 0;
8669 macro_build (&expr1, "slti", "x,8", yreg);
8671 move_register (xreg, yreg);
8672 expr1.X_add_number = 2;
8673 macro_build (&expr1, "bteqz", "p");
8674 macro_build (NULL, "neg", "x,w", xreg, xreg);
8678 /* For consistency checking, verify that all bits are specified either
8679 by the match/mask part of the instruction definition, or by the
8682 validate_mips_insn (const struct mips_opcode *opc)
8684 const char *p = opc->args;
8686 unsigned long used_bits = opc->mask;
8688 if ((used_bits & opc->match) != opc->match)
8690 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8691 opc->name, opc->args);
8694 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8704 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
8705 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
8706 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
8707 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
8708 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8709 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8710 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8711 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
8712 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8713 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8714 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8715 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8716 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8718 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8719 case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
8720 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8721 case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
8722 case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
8723 case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
8724 case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
8725 case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
8726 case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
8727 case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
8728 case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break;
8729 case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break;
8730 case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break;
8731 case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break;
8732 case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break;
8735 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8736 c, opc->name, opc->args);
8740 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8741 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8743 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
8744 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
8745 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8746 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8748 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8749 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8751 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
8752 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8754 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
8755 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
8756 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
8757 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
8758 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8759 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
8760 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8761 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8762 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8763 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8764 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8765 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8766 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8767 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
8768 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8769 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
8770 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8772 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
8773 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8774 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8775 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
8777 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8778 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8779 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
8780 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8781 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8782 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8783 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8784 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8785 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8788 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
8789 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
8790 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8791 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
8792 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
8795 case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8796 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
8797 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
8798 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
8799 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
8800 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8801 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
8802 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
8803 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
8804 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
8805 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
8806 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
8807 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
8808 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
8809 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
8810 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
8811 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
8812 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8814 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8815 c, opc->name, opc->args);
8819 if (used_bits != 0xffffffff)
8821 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8822 ~used_bits & 0xffffffff, opc->name, opc->args);
8828 /* UDI immediates. */
8836 static const struct mips_immed mips_immed[] = {
8837 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
8838 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
8839 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
8840 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
8844 /* Check whether an odd floating-point register is allowed. */
8846 mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
8848 const char *s = insn->name;
8850 if (insn->pinfo == INSN_MACRO)
8851 /* Let a macro pass, we'll catch it later when it is expanded. */
8854 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa))
8856 /* Allow odd registers for single-precision ops. */
8857 switch (insn->pinfo & (FP_S | FP_D))
8861 return 1; /* both single precision - ok */
8863 return 0; /* both double precision - fail */
8868 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
8869 s = strchr (insn->name, '.');
8871 s = s != NULL ? strchr (s + 1, '.') : NULL;
8872 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
8875 /* Single-precision coprocessor loads and moves are OK too. */
8876 if ((insn->pinfo & FP_S)
8877 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
8878 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
8884 /* This routine assembles an instruction into its binary format. As a
8885 side effect, it sets one of the global variables imm_reloc or
8886 offset_reloc to the type of relocation to do if one of the operands
8887 is an address expression. */
8890 mips_ip (char *str, struct mips_cl_insn *ip)
8895 struct mips_opcode *insn;
8898 unsigned int lastregno;
8899 unsigned int lastpos = 0;
8900 unsigned int limlo, limhi;
8903 offsetT min_range, max_range;
8909 /* If the instruction contains a '.', we first try to match an instruction
8910 including the '.'. Then we try again without the '.'. */
8912 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
8915 /* If we stopped on whitespace, then replace the whitespace with null for
8916 the call to hash_find. Save the character we replaced just in case we
8917 have to re-parse the instruction. */
8924 insn = (struct mips_opcode *) hash_find (op_hash, str);
8926 /* If we didn't find the instruction in the opcode table, try again, but
8927 this time with just the instruction up to, but not including the
8931 /* Restore the character we overwrite above (if any). */
8935 /* Scan up to the first '.' or whitespace. */
8937 *s != '\0' && *s != '.' && !ISSPACE (*s);
8941 /* If we did not find a '.', then we can quit now. */
8944 insn_error = _("Unrecognized opcode");
8948 /* Lookup the instruction in the hash table. */
8950 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
8952 insn_error = _("Unrecognized opcode");
8962 gas_assert (strcmp (insn->name, str) == 0);
8964 ok = is_opcode_valid (insn);
8967 if (insn + 1 < &mips_opcodes[NUMOPCODES]
8968 && strcmp (insn->name, insn[1].name) == 0)
8977 static char buf[100];
8979 _("opcode not supported on this processor: %s (%s)"),
8980 mips_cpu_info_from_arch (mips_opts.arch)->name,
8981 mips_cpu_info_from_isa (mips_opts.isa)->name);
8990 create_insn (ip, insn);
8993 lastregno = 0xffffffff;
8994 for (args = insn->args;; ++args)
8998 s += strspn (s, " \t");
9002 case '\0': /* end of args */
9007 case '2': /* DSP 2-bit unsigned immediate in bit 11. */
9008 my_getExpression (&imm_expr, s);
9009 check_absolute_expr (ip, &imm_expr);
9010 if ((unsigned long) imm_expr.X_add_number != 1
9011 && (unsigned long) imm_expr.X_add_number != 3)
9013 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
9014 (unsigned long) imm_expr.X_add_number);
9016 INSERT_OPERAND (BP, *ip, imm_expr.X_add_number);
9017 imm_expr.X_op = O_absent;
9021 case '3': /* DSP 3-bit unsigned immediate in bit 21. */
9022 my_getExpression (&imm_expr, s);
9023 check_absolute_expr (ip, &imm_expr);
9024 if (imm_expr.X_add_number & ~OP_MASK_SA3)
9026 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9027 OP_MASK_SA3, (unsigned long) imm_expr.X_add_number);
9029 INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number);
9030 imm_expr.X_op = O_absent;
9034 case '4': /* DSP 4-bit unsigned immediate in bit 21. */
9035 my_getExpression (&imm_expr, s);
9036 check_absolute_expr (ip, &imm_expr);
9037 if (imm_expr.X_add_number & ~OP_MASK_SA4)
9039 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9040 OP_MASK_SA4, (unsigned long) imm_expr.X_add_number);
9042 INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number);
9043 imm_expr.X_op = O_absent;
9047 case '5': /* DSP 8-bit unsigned immediate in bit 16. */
9048 my_getExpression (&imm_expr, s);
9049 check_absolute_expr (ip, &imm_expr);
9050 if (imm_expr.X_add_number & ~OP_MASK_IMM8)
9052 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9053 OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number);
9055 INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number);
9056 imm_expr.X_op = O_absent;
9060 case '6': /* DSP 5-bit unsigned immediate in bit 21. */
9061 my_getExpression (&imm_expr, s);
9062 check_absolute_expr (ip, &imm_expr);
9063 if (imm_expr.X_add_number & ~OP_MASK_RS)
9065 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9066 OP_MASK_RS, (unsigned long) imm_expr.X_add_number);
9068 INSERT_OPERAND (RS, *ip, imm_expr.X_add_number);
9069 imm_expr.X_op = O_absent;
9073 case '7': /* Four DSP accumulators in bits 11,12. */
9074 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9075 s[3] >= '0' && s[3] <= '3')
9079 INSERT_OPERAND (DSPACC, *ip, regno);
9083 as_bad (_("Invalid dsp acc register"));
9086 case '8': /* DSP 6-bit unsigned immediate in bit 11. */
9087 my_getExpression (&imm_expr, s);
9088 check_absolute_expr (ip, &imm_expr);
9089 if (imm_expr.X_add_number & ~OP_MASK_WRDSP)
9091 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9093 (unsigned long) imm_expr.X_add_number);
9095 INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number);
9096 imm_expr.X_op = O_absent;
9100 case '9': /* Four DSP accumulators in bits 21,22. */
9101 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9102 s[3] >= '0' && s[3] <= '3')
9106 INSERT_OPERAND (DSPACC_S, *ip, regno);
9110 as_bad (_("Invalid dsp acc register"));
9113 case '0': /* DSP 6-bit signed immediate in bit 20. */
9114 my_getExpression (&imm_expr, s);
9115 check_absolute_expr (ip, &imm_expr);
9116 min_range = -((OP_MASK_DSPSFT + 1) >> 1);
9117 max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1;
9118 if (imm_expr.X_add_number < min_range ||
9119 imm_expr.X_add_number > max_range)
9121 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
9122 (long) min_range, (long) max_range,
9123 (long) imm_expr.X_add_number);
9125 INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number);
9126 imm_expr.X_op = O_absent;
9130 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
9131 my_getExpression (&imm_expr, s);
9132 check_absolute_expr (ip, &imm_expr);
9133 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
9135 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9137 (unsigned long) imm_expr.X_add_number);
9139 INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number);
9140 imm_expr.X_op = O_absent;
9144 case ':': /* DSP 7-bit signed immediate in bit 19. */
9145 my_getExpression (&imm_expr, s);
9146 check_absolute_expr (ip, &imm_expr);
9147 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
9148 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
9149 if (imm_expr.X_add_number < min_range ||
9150 imm_expr.X_add_number > max_range)
9152 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
9153 (long) min_range, (long) max_range,
9154 (long) imm_expr.X_add_number);
9156 INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number);
9157 imm_expr.X_op = O_absent;
9161 case '@': /* DSP 10-bit signed immediate in bit 16. */
9162 my_getExpression (&imm_expr, s);
9163 check_absolute_expr (ip, &imm_expr);
9164 min_range = -((OP_MASK_IMM10 + 1) >> 1);
9165 max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1;
9166 if (imm_expr.X_add_number < min_range ||
9167 imm_expr.X_add_number > max_range)
9169 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
9170 (long) min_range, (long) max_range,
9171 (long) imm_expr.X_add_number);
9173 INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number);
9174 imm_expr.X_op = O_absent;
9178 case '!': /* MT usermode flag bit. */
9179 my_getExpression (&imm_expr, s);
9180 check_absolute_expr (ip, &imm_expr);
9181 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
9182 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
9183 (unsigned long) imm_expr.X_add_number);
9184 INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number);
9185 imm_expr.X_op = O_absent;
9189 case '$': /* MT load high flag bit. */
9190 my_getExpression (&imm_expr, s);
9191 check_absolute_expr (ip, &imm_expr);
9192 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
9193 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
9194 (unsigned long) imm_expr.X_add_number);
9195 INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number);
9196 imm_expr.X_op = O_absent;
9200 case '*': /* Four DSP accumulators in bits 18,19. */
9201 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9202 s[3] >= '0' && s[3] <= '3')
9206 INSERT_OPERAND (MTACC_T, *ip, regno);
9210 as_bad (_("Invalid dsp/smartmips acc register"));
9213 case '&': /* Four DSP accumulators in bits 13,14. */
9214 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9215 s[3] >= '0' && s[3] <= '3')
9219 INSERT_OPERAND (MTACC_D, *ip, regno);
9223 as_bad (_("Invalid dsp/smartmips acc register"));
9235 INSERT_OPERAND (RS, *ip, lastregno);
9239 INSERT_OPERAND (RT, *ip, lastregno);
9243 INSERT_OPERAND (FT, *ip, lastregno);
9247 INSERT_OPERAND (FS, *ip, lastregno);
9253 /* Handle optional base register.
9254 Either the base register is omitted or
9255 we must have a left paren. */
9256 /* This is dependent on the next operand specifier
9257 is a base register specification. */
9258 gas_assert (args[1] == 'b');
9262 case ')': /* These must match exactly. */
9269 case '+': /* Opcode extension character. */
9272 case '1': /* UDI immediates. */
9277 const struct mips_immed *imm = mips_immed;
9279 while (imm->type && imm->type != *args)
9283 my_getExpression (&imm_expr, s);
9284 check_absolute_expr (ip, &imm_expr);
9285 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
9287 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
9288 imm->desc ? imm->desc : ip->insn_mo->name,
9289 (unsigned long) imm_expr.X_add_number,
9290 (unsigned long) imm_expr.X_add_number);
9291 imm_expr.X_add_number &= imm->mask;
9293 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
9295 imm_expr.X_op = O_absent;
9300 case 'A': /* ins/ext position, becomes LSB. */
9309 my_getExpression (&imm_expr, s);
9310 check_absolute_expr (ip, &imm_expr);
9311 if ((unsigned long) imm_expr.X_add_number < limlo
9312 || (unsigned long) imm_expr.X_add_number > limhi)
9314 as_bad (_("Improper position (%lu)"),
9315 (unsigned long) imm_expr.X_add_number);
9316 imm_expr.X_add_number = limlo;
9318 lastpos = imm_expr.X_add_number;
9319 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9320 imm_expr.X_op = O_absent;
9324 case 'B': /* ins size, becomes MSB. */
9333 my_getExpression (&imm_expr, s);
9334 check_absolute_expr (ip, &imm_expr);
9335 /* Check for negative input so that small negative numbers
9336 will not succeed incorrectly. The checks against
9337 (pos+size) transitively check "size" itself,
9338 assuming that "pos" is reasonable. */
9339 if ((long) imm_expr.X_add_number < 0
9340 || ((unsigned long) imm_expr.X_add_number
9342 || ((unsigned long) imm_expr.X_add_number
9345 as_bad (_("Improper insert size (%lu, position %lu)"),
9346 (unsigned long) imm_expr.X_add_number,
9347 (unsigned long) lastpos);
9348 imm_expr.X_add_number = limlo - lastpos;
9350 INSERT_OPERAND (INSMSB, *ip,
9351 lastpos + imm_expr.X_add_number - 1);
9352 imm_expr.X_op = O_absent;
9356 case 'C': /* ext size, becomes MSBD. */
9369 my_getExpression (&imm_expr, s);
9370 check_absolute_expr (ip, &imm_expr);
9371 /* Check for negative input so that small negative numbers
9372 will not succeed incorrectly. The checks against
9373 (pos+size) transitively check "size" itself,
9374 assuming that "pos" is reasonable. */
9375 if ((long) imm_expr.X_add_number < 0
9376 || ((unsigned long) imm_expr.X_add_number
9378 || ((unsigned long) imm_expr.X_add_number
9381 as_bad (_("Improper extract size (%lu, position %lu)"),
9382 (unsigned long) imm_expr.X_add_number,
9383 (unsigned long) lastpos);
9384 imm_expr.X_add_number = limlo - lastpos;
9386 INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1);
9387 imm_expr.X_op = O_absent;
9392 /* +D is for disassembly only; never match. */
9396 /* "+I" is like "I", except that imm2_expr is used. */
9397 my_getExpression (&imm2_expr, s);
9398 if (imm2_expr.X_op != O_big
9399 && imm2_expr.X_op != O_constant)
9400 insn_error = _("absolute expression required");
9401 if (HAVE_32BIT_GPRS)
9402 normalize_constant_expr (&imm2_expr);
9406 case 'T': /* Coprocessor register. */
9407 /* +T is for disassembly only; never match. */
9410 case 't': /* Coprocessor register number. */
9411 if (s[0] == '$' && ISDIGIT (s[1]))
9421 while (ISDIGIT (*s));
9423 as_bad (_("Invalid register number (%d)"), regno);
9426 INSERT_OPERAND (RT, *ip, regno);
9431 as_bad (_("Invalid coprocessor 0 register number"));
9435 /* bbit[01] and bbit[01]32 bit index. Give error if index
9436 is not in the valid range. */
9437 my_getExpression (&imm_expr, s);
9438 check_absolute_expr (ip, &imm_expr);
9439 if ((unsigned) imm_expr.X_add_number > 31)
9441 as_bad (_("Improper bit index (%lu)"),
9442 (unsigned long) imm_expr.X_add_number);
9443 imm_expr.X_add_number = 0;
9445 INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number);
9446 imm_expr.X_op = O_absent;
9451 /* bbit[01] bit index when bbit is used but we generate
9452 bbit[01]32 because the index is over 32. Move to the
9453 next candidate if index is not in the valid range. */
9454 my_getExpression (&imm_expr, s);
9455 check_absolute_expr (ip, &imm_expr);
9456 if ((unsigned) imm_expr.X_add_number < 32
9457 || (unsigned) imm_expr.X_add_number > 63)
9459 INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number - 32);
9460 imm_expr.X_op = O_absent;
9465 /* cins, cins32, exts and exts32 position field. Give error
9466 if it's not in the valid range. */
9467 my_getExpression (&imm_expr, s);
9468 check_absolute_expr (ip, &imm_expr);
9469 if ((unsigned) imm_expr.X_add_number > 31)
9471 as_bad (_("Improper position (%lu)"),
9472 (unsigned long) imm_expr.X_add_number);
9473 imm_expr.X_add_number = 0;
9475 /* Make the pos explicit to simplify +S. */
9476 lastpos = imm_expr.X_add_number + 32;
9477 INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number);
9478 imm_expr.X_op = O_absent;
9483 /* cins, cins32, exts and exts32 position field. Move to
9484 the next candidate if it's not in the valid range. */
9485 my_getExpression (&imm_expr, s);
9486 check_absolute_expr (ip, &imm_expr);
9487 if ((unsigned) imm_expr.X_add_number < 32
9488 || (unsigned) imm_expr.X_add_number > 63)
9490 lastpos = imm_expr.X_add_number;
9491 INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number - 32);
9492 imm_expr.X_op = O_absent;
9497 /* cins and exts length-minus-one field. */
9498 my_getExpression (&imm_expr, s);
9499 check_absolute_expr (ip, &imm_expr);
9500 if ((unsigned long) imm_expr.X_add_number > 31)
9502 as_bad (_("Improper size (%lu)"),
9503 (unsigned long) imm_expr.X_add_number);
9504 imm_expr.X_add_number = 0;
9506 INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number);
9507 imm_expr.X_op = O_absent;
9512 /* cins32/exts32 and cins/exts aliasing cint32/exts32
9513 length-minus-one field. */
9514 my_getExpression (&imm_expr, s);
9515 check_absolute_expr (ip, &imm_expr);
9516 if ((long) imm_expr.X_add_number < 0
9517 || (unsigned long) imm_expr.X_add_number + lastpos > 63)
9519 as_bad (_("Improper size (%lu)"),
9520 (unsigned long) imm_expr.X_add_number);
9521 imm_expr.X_add_number = 0;
9523 INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number);
9524 imm_expr.X_op = O_absent;
9529 /* seqi/snei immediate field. */
9530 my_getExpression (&imm_expr, s);
9531 check_absolute_expr (ip, &imm_expr);
9532 if ((long) imm_expr.X_add_number < -512
9533 || (long) imm_expr.X_add_number >= 512)
9535 as_bad (_("Improper immediate (%ld)"),
9536 (long) imm_expr.X_add_number);
9537 imm_expr.X_add_number = 0;
9539 INSERT_OPERAND (SEQI, *ip, imm_expr.X_add_number);
9540 imm_expr.X_op = O_absent;
9544 case 'a': /* 8-bit signed offset in bit 6 */
9545 my_getExpression (&imm_expr, s);
9546 check_absolute_expr (ip, &imm_expr);
9547 min_range = -((OP_MASK_OFFSET_A + 1) >> 1);
9548 max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1;
9549 if (imm_expr.X_add_number < min_range
9550 || imm_expr.X_add_number > max_range)
9552 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9553 (long) min_range, (long) max_range,
9554 (long) imm_expr.X_add_number);
9556 INSERT_OPERAND (OFFSET_A, *ip, imm_expr.X_add_number);
9557 imm_expr.X_op = O_absent;
9561 case 'b': /* 8-bit signed offset in bit 3 */
9562 my_getExpression (&imm_expr, s);
9563 check_absolute_expr (ip, &imm_expr);
9564 min_range = -((OP_MASK_OFFSET_B + 1) >> 1);
9565 max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1;
9566 if (imm_expr.X_add_number < min_range
9567 || imm_expr.X_add_number > max_range)
9569 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9570 (long) min_range, (long) max_range,
9571 (long) imm_expr.X_add_number);
9573 INSERT_OPERAND (OFFSET_B, *ip, imm_expr.X_add_number);
9574 imm_expr.X_op = O_absent;
9578 case 'c': /* 9-bit signed offset in bit 6 */
9579 my_getExpression (&imm_expr, s);
9580 check_absolute_expr (ip, &imm_expr);
9581 min_range = -((OP_MASK_OFFSET_C + 1) >> 1);
9582 max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1;
9583 /* We check the offset range before adjusted. */
9586 if (imm_expr.X_add_number < min_range
9587 || imm_expr.X_add_number > max_range)
9589 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9590 (long) min_range, (long) max_range,
9591 (long) imm_expr.X_add_number);
9593 if (imm_expr.X_add_number & 0xf)
9595 as_bad (_("Offset not 16 bytes alignment (%ld)"),
9596 (long) imm_expr.X_add_number);
9598 /* Right shift 4 bits to adjust the offset operand. */
9599 INSERT_OPERAND (OFFSET_C, *ip, imm_expr.X_add_number >> 4);
9600 imm_expr.X_op = O_absent;
9605 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
9607 if (regno == AT && mips_opts.at)
9609 if (mips_opts.at == ATREG)
9610 as_warn (_("used $at without \".set noat\""));
9612 as_warn (_("used $%u with \".set at=$%u\""),
9613 regno, mips_opts.at);
9615 INSERT_OPERAND (RZ, *ip, regno);
9619 if (!reg_lookup (&s, RTYPE_FPU, ®no))
9621 INSERT_OPERAND (FZ, *ip, regno);
9625 as_bad (_("Internal error: bad mips opcode "
9626 "(unknown extension operand type `+%c'): %s %s"),
9627 *args, insn->name, insn->args);
9628 /* Further processing is fruitless. */
9633 case '<': /* must be at least one digit */
9635 * According to the manual, if the shift amount is greater
9636 * than 31 or less than 0, then the shift amount should be
9637 * mod 32. In reality the mips assembler issues an error.
9638 * We issue a warning and mask out all but the low 5 bits.
9640 my_getExpression (&imm_expr, s);
9641 check_absolute_expr (ip, &imm_expr);
9642 if ((unsigned long) imm_expr.X_add_number > 31)
9643 as_warn (_("Improper shift amount (%lu)"),
9644 (unsigned long) imm_expr.X_add_number);
9645 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9646 imm_expr.X_op = O_absent;
9650 case '>': /* shift amount minus 32 */
9651 my_getExpression (&imm_expr, s);
9652 check_absolute_expr (ip, &imm_expr);
9653 if ((unsigned long) imm_expr.X_add_number < 32
9654 || (unsigned long) imm_expr.X_add_number > 63)
9656 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32);
9657 imm_expr.X_op = O_absent;
9661 case 'k': /* CACHE code. */
9662 case 'h': /* PREFX code. */
9663 case '1': /* SYNC type. */
9664 my_getExpression (&imm_expr, s);
9665 check_absolute_expr (ip, &imm_expr);
9666 if ((unsigned long) imm_expr.X_add_number > 31)
9667 as_warn (_("Invalid value for `%s' (%lu)"),
9669 (unsigned long) imm_expr.X_add_number);
9672 if (mips_fix_cn63xxp1 && strcmp ("pref", insn->name) == 0)
9673 switch (imm_expr.X_add_number)
9682 case 31: /* These are ok. */
9685 default: /* The rest must be changed to 28. */
9686 imm_expr.X_add_number = 28;
9689 INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number);
9691 else if (*args == 'h')
9692 INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number);
9694 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9695 imm_expr.X_op = O_absent;
9699 case 'c': /* BREAK code. */
9700 my_getExpression (&imm_expr, s);
9701 check_absolute_expr (ip, &imm_expr);
9702 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE)
9703 as_warn (_("Code for %s not in range 0..1023 (%lu)"),
9705 (unsigned long) imm_expr.X_add_number);
9706 INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number);
9707 imm_expr.X_op = O_absent;
9711 case 'q': /* Lower BREAK code. */
9712 my_getExpression (&imm_expr, s);
9713 check_absolute_expr (ip, &imm_expr);
9714 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2)
9715 as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
9717 (unsigned long) imm_expr.X_add_number);
9718 INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number);
9719 imm_expr.X_op = O_absent;
9723 case 'B': /* 20-bit SYSCALL/BREAK code. */
9724 my_getExpression (&imm_expr, s);
9725 check_absolute_expr (ip, &imm_expr);
9726 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
9727 as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
9729 (unsigned long) imm_expr.X_add_number);
9730 INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number);
9731 imm_expr.X_op = O_absent;
9735 case 'C': /* Coprocessor code. */
9736 my_getExpression (&imm_expr, s);
9737 check_absolute_expr (ip, &imm_expr);
9738 if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ)
9740 as_warn (_("Coproccesor code > 25 bits (%lu)"),
9741 (unsigned long) imm_expr.X_add_number);
9742 imm_expr.X_add_number &= OP_MASK_COPZ;
9744 INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number);
9745 imm_expr.X_op = O_absent;
9749 case 'J': /* 19-bit WAIT code. */
9750 my_getExpression (&imm_expr, s);
9751 check_absolute_expr (ip, &imm_expr);
9752 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
9754 as_warn (_("Illegal 19-bit code (%lu)"),
9755 (unsigned long) imm_expr.X_add_number);
9756 imm_expr.X_add_number &= OP_MASK_CODE19;
9758 INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number);
9759 imm_expr.X_op = O_absent;
9763 case 'P': /* Performance register. */
9764 my_getExpression (&imm_expr, s);
9765 check_absolute_expr (ip, &imm_expr);
9766 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
9767 as_warn (_("Invalid performance register (%lu)"),
9768 (unsigned long) imm_expr.X_add_number);
9769 INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number);
9770 imm_expr.X_op = O_absent;
9774 case 'G': /* Coprocessor destination register. */
9775 if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0)
9776 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, ®no);
9778 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
9779 INSERT_OPERAND (RD, *ip, regno);
9788 case 'b': /* Base register. */
9789 case 'd': /* Destination register. */
9790 case 's': /* Source register. */
9791 case 't': /* Target register. */
9792 case 'r': /* Both target and source. */
9793 case 'v': /* Both dest and source. */
9794 case 'w': /* Both dest and target. */
9795 case 'E': /* Coprocessor target register. */
9796 case 'K': /* RDHWR destination register. */
9797 case 'x': /* Ignore register name. */
9798 case 'z': /* Must be zero register. */
9799 case 'U': /* Destination register (CLO/CLZ). */
9800 case 'g': /* Coprocessor destination register. */
9802 if (*args == 'E' || *args == 'K')
9803 ok = reg_lookup (&s, RTYPE_NUM, ®no);
9806 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
9807 if (regno == AT && mips_opts.at)
9809 if (mips_opts.at == ATREG)
9810 as_warn (_("Used $at without \".set noat\""));
9812 as_warn (_("Used $%u with \".set at=$%u\""),
9813 regno, mips_opts.at);
9823 if (c == 'r' || c == 'v' || c == 'w')
9830 /* 'z' only matches $0. */
9831 if (c == 'z' && regno != 0)
9834 if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
9836 if (regno == lastregno)
9839 = _("Source and destination must be different");
9842 if (regno == 31 && lastregno == 0xffffffff)
9845 = _("A destination register must be supplied");
9849 /* Now that we have assembled one operand, we use the args
9850 string to figure out where it goes in the instruction. */
9857 INSERT_OPERAND (RS, *ip, regno);
9862 INSERT_OPERAND (RD, *ip, regno);
9865 INSERT_OPERAND (RD, *ip, regno);
9866 INSERT_OPERAND (RT, *ip, regno);
9871 INSERT_OPERAND (RT, *ip, regno);
9874 /* This case exists because on the r3000 trunc
9875 expands into a macro which requires a gp
9876 register. On the r6000 or r4000 it is
9877 assembled into a single instruction which
9878 ignores the register. Thus the insn version
9879 is MIPS_ISA2 and uses 'x', and the macro
9880 version is MIPS_ISA1 and uses 't'. */
9883 /* This case is for the div instruction, which
9884 acts differently if the destination argument
9885 is $0. This only matches $0, and is checked
9886 outside the switch. */
9896 INSERT_OPERAND (RS, *ip, lastregno);
9899 INSERT_OPERAND (RT, *ip, lastregno);
9904 case 'O': /* MDMX alignment immediate constant. */
9905 my_getExpression (&imm_expr, s);
9906 check_absolute_expr (ip, &imm_expr);
9907 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
9908 as_warn (_("Improper align amount (%ld), using low bits"),
9909 (long) imm_expr.X_add_number);
9910 INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number);
9911 imm_expr.X_op = O_absent;
9915 case 'Q': /* MDMX vector, element sel, or const. */
9918 /* MDMX Immediate. */
9919 my_getExpression (&imm_expr, s);
9920 check_absolute_expr (ip, &imm_expr);
9921 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
9922 as_warn (_("Invalid MDMX Immediate (%ld)"),
9923 (long) imm_expr.X_add_number);
9924 INSERT_OPERAND (FT, *ip, imm_expr.X_add_number);
9925 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
9926 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
9928 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
9929 imm_expr.X_op = O_absent;
9933 /* Not MDMX Immediate. Fall through. */
9934 case 'X': /* MDMX destination register. */
9935 case 'Y': /* MDMX source register. */
9936 case 'Z': /* MDMX target register. */
9938 case 'D': /* Floating point destination register. */
9939 case 'S': /* Floating point source register. */
9940 case 'T': /* Floating point target register. */
9941 case 'R': /* Floating point source register. */
9946 || (mips_opts.ase_mdmx
9947 && (ip->insn_mo->pinfo & FP_D)
9948 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
9949 | INSN_COPROC_MEMORY_DELAY
9950 | INSN_LOAD_COPROC_DELAY
9951 | INSN_LOAD_MEMORY_DELAY
9952 | INSN_STORE_MEMORY))))
9955 if (reg_lookup (&s, rtype, ®no))
9957 if ((regno & 1) != 0
9959 && !mips_oddfpreg_ok (ip->insn_mo, argnum))
9960 as_warn (_("Float register should be even, was %d"),
9968 if (c == 'V' || c == 'W')
9979 INSERT_OPERAND (FD, *ip, regno);
9984 INSERT_OPERAND (FS, *ip, regno);
9987 /* This is like 'Z', but also needs to fix the MDMX
9988 vector/scalar select bits. Note that the
9989 scalar immediate case is handled above. */
9992 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
9993 int max_el = (is_qh ? 3 : 7);
9995 my_getExpression(&imm_expr, s);
9996 check_absolute_expr (ip, &imm_expr);
9998 if (imm_expr.X_add_number > max_el)
9999 as_bad (_("Bad element selector %ld"),
10000 (long) imm_expr.X_add_number);
10001 imm_expr.X_add_number &= max_el;
10002 ip->insn_opcode |= (imm_expr.X_add_number
10005 imm_expr.X_op = O_absent;
10007 as_warn (_("Expecting ']' found '%s'"), s);
10013 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
10014 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
10017 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
10020 /* Fall through. */
10024 INSERT_OPERAND (FT, *ip, regno);
10027 INSERT_OPERAND (FR, *ip, regno);
10037 INSERT_OPERAND (FS, *ip, lastregno);
10040 INSERT_OPERAND (FT, *ip, lastregno);
10046 my_getExpression (&imm_expr, s);
10047 if (imm_expr.X_op != O_big
10048 && imm_expr.X_op != O_constant)
10049 insn_error = _("absolute expression required");
10050 if (HAVE_32BIT_GPRS)
10051 normalize_constant_expr (&imm_expr);
10056 my_getExpression (&offset_expr, s);
10057 normalize_address_expr (&offset_expr);
10058 *imm_reloc = BFD_RELOC_32;
10071 unsigned char temp[8];
10073 unsigned int length;
10078 /* These only appear as the last operand in an
10079 instruction, and every instruction that accepts
10080 them in any variant accepts them in all variants.
10081 This means we don't have to worry about backing out
10082 any changes if the instruction does not match.
10084 The difference between them is the size of the
10085 floating point constant and where it goes. For 'F'
10086 and 'L' the constant is 64 bits; for 'f' and 'l' it
10087 is 32 bits. Where the constant is placed is based
10088 on how the MIPS assembler does things:
10091 f -- immediate value
10094 The .lit4 and .lit8 sections are only used if
10095 permitted by the -G argument.
10097 The code below needs to know whether the target register
10098 is 32 or 64 bits wide. It relies on the fact 'f' and
10099 'F' are used with GPR-based instructions and 'l' and
10100 'L' are used with FPR-based instructions. */
10102 f64 = *args == 'F' || *args == 'L';
10103 using_gprs = *args == 'F' || *args == 'f';
10105 save_in = input_line_pointer;
10106 input_line_pointer = s;
10107 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
10109 s = input_line_pointer;
10110 input_line_pointer = save_in;
10111 if (err != NULL && *err != '\0')
10113 as_bad (_("Bad floating point constant: %s"), err);
10114 memset (temp, '\0', sizeof temp);
10115 length = f64 ? 8 : 4;
10118 gas_assert (length == (unsigned) (f64 ? 8 : 4));
10122 && (g_switch_value < 4
10123 || (temp[0] == 0 && temp[1] == 0)
10124 || (temp[2] == 0 && temp[3] == 0))))
10126 imm_expr.X_op = O_constant;
10127 if (!target_big_endian)
10128 imm_expr.X_add_number = bfd_getl32 (temp);
10130 imm_expr.X_add_number = bfd_getb32 (temp);
10132 else if (length > 4
10133 && !mips_disable_float_construction
10134 /* Constants can only be constructed in GPRs and
10135 copied to FPRs if the GPRs are at least as wide
10136 as the FPRs. Force the constant into memory if
10137 we are using 64-bit FPRs but the GPRs are only
10140 || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
10141 && ((temp[0] == 0 && temp[1] == 0)
10142 || (temp[2] == 0 && temp[3] == 0))
10143 && ((temp[4] == 0 && temp[5] == 0)
10144 || (temp[6] == 0 && temp[7] == 0)))
10146 /* The value is simple enough to load with a couple of
10147 instructions. If using 32-bit registers, set
10148 imm_expr to the high order 32 bits and offset_expr to
10149 the low order 32 bits. Otherwise, set imm_expr to
10150 the entire 64 bit constant. */
10151 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
10153 imm_expr.X_op = O_constant;
10154 offset_expr.X_op = O_constant;
10155 if (!target_big_endian)
10157 imm_expr.X_add_number = bfd_getl32 (temp + 4);
10158 offset_expr.X_add_number = bfd_getl32 (temp);
10162 imm_expr.X_add_number = bfd_getb32 (temp);
10163 offset_expr.X_add_number = bfd_getb32 (temp + 4);
10165 if (offset_expr.X_add_number == 0)
10166 offset_expr.X_op = O_absent;
10168 else if (sizeof (imm_expr.X_add_number) > 4)
10170 imm_expr.X_op = O_constant;
10171 if (!target_big_endian)
10172 imm_expr.X_add_number = bfd_getl64 (temp);
10174 imm_expr.X_add_number = bfd_getb64 (temp);
10178 imm_expr.X_op = O_big;
10179 imm_expr.X_add_number = 4;
10180 if (!target_big_endian)
10182 generic_bignum[0] = bfd_getl16 (temp);
10183 generic_bignum[1] = bfd_getl16 (temp + 2);
10184 generic_bignum[2] = bfd_getl16 (temp + 4);
10185 generic_bignum[3] = bfd_getl16 (temp + 6);
10189 generic_bignum[0] = bfd_getb16 (temp + 6);
10190 generic_bignum[1] = bfd_getb16 (temp + 4);
10191 generic_bignum[2] = bfd_getb16 (temp + 2);
10192 generic_bignum[3] = bfd_getb16 (temp);
10198 const char *newname;
10201 /* Switch to the right section. */
10203 subseg = now_subseg;
10206 default: /* unused default case avoids warnings. */
10208 newname = RDATA_SECTION_NAME;
10209 if (g_switch_value >= 8)
10213 newname = RDATA_SECTION_NAME;
10216 gas_assert (g_switch_value >= 4);
10220 new_seg = subseg_new (newname, (subsegT) 0);
10222 bfd_set_section_flags (stdoutput, new_seg,
10227 frag_align (*args == 'l' ? 2 : 3, 0, 0);
10228 if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0)
10229 record_alignment (new_seg, 4);
10231 record_alignment (new_seg, *args == 'l' ? 2 : 3);
10232 if (seg == now_seg)
10233 as_bad (_("Can't use floating point insn in this section"));
10235 /* Set the argument to the current address in the
10237 offset_expr.X_op = O_symbol;
10238 offset_expr.X_add_symbol = symbol_temp_new_now ();
10239 offset_expr.X_add_number = 0;
10241 /* Put the floating point number into the section. */
10242 p = frag_more ((int) length);
10243 memcpy (p, temp, length);
10245 /* Switch back to the original section. */
10246 subseg_set (seg, subseg);
10251 case 'i': /* 16-bit unsigned immediate. */
10252 case 'j': /* 16-bit signed immediate. */
10253 *imm_reloc = BFD_RELOC_LO16;
10254 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
10257 offsetT minval, maxval;
10259 more = (insn + 1 < &mips_opcodes[NUMOPCODES]
10260 && strcmp (insn->name, insn[1].name) == 0);
10262 /* If the expression was written as an unsigned number,
10263 only treat it as signed if there are no more
10267 && sizeof (imm_expr.X_add_number) <= 4
10268 && imm_expr.X_op == O_constant
10269 && imm_expr.X_add_number < 0
10270 && imm_expr.X_unsigned
10271 && HAVE_64BIT_GPRS)
10274 /* For compatibility with older assemblers, we accept
10275 0x8000-0xffff as signed 16-bit numbers when only
10276 signed numbers are allowed. */
10278 minval = 0, maxval = 0xffff;
10280 minval = -0x8000, maxval = 0x7fff;
10282 minval = -0x8000, maxval = 0xffff;
10284 if (imm_expr.X_op != O_constant
10285 || imm_expr.X_add_number < minval
10286 || imm_expr.X_add_number > maxval)
10290 if (imm_expr.X_op == O_constant
10291 || imm_expr.X_op == O_big)
10292 as_bad (_("Expression out of range"));
10298 case 'o': /* 16-bit offset. */
10299 offset_reloc[0] = BFD_RELOC_LO16;
10300 offset_reloc[1] = BFD_RELOC_UNUSED;
10301 offset_reloc[2] = BFD_RELOC_UNUSED;
10303 /* Check whether there is only a single bracketed expression
10304 left. If so, it must be the base register and the
10305 constant must be zero. */
10306 if (*s == '(' && strchr (s + 1, '(') == 0)
10308 offset_expr.X_op = O_constant;
10309 offset_expr.X_add_number = 0;
10313 /* If this value won't fit into a 16 bit offset, then go
10314 find a macro that will generate the 32 bit offset
10316 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
10317 && (offset_expr.X_op != O_constant
10318 || offset_expr.X_add_number >= 0x8000
10319 || offset_expr.X_add_number < -0x8000))
10325 case 'p': /* PC-relative offset. */
10326 *offset_reloc = BFD_RELOC_16_PCREL_S2;
10327 my_getExpression (&offset_expr, s);
10331 case 'u': /* Upper 16 bits. */
10332 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
10333 && imm_expr.X_op == O_constant
10334 && (imm_expr.X_add_number < 0
10335 || imm_expr.X_add_number >= 0x10000))
10336 as_bad (_("lui expression (%lu) not in range 0..65535"),
10337 (unsigned long) imm_expr.X_add_number);
10341 case 'a': /* 26-bit address. */
10342 my_getExpression (&offset_expr, s);
10344 *offset_reloc = BFD_RELOC_MIPS_JMP;
10347 case 'N': /* 3-bit branch condition code. */
10348 case 'M': /* 3-bit compare condition code. */
10350 if (ip->insn_mo->pinfo & (FP_D | FP_S))
10351 rtype |= RTYPE_FCC;
10352 if (!reg_lookup (&s, rtype, ®no))
10354 if ((strcmp (str + strlen (str) - 3, ".ps") == 0
10355 || strcmp (str + strlen (str) - 5, "any2f") == 0
10356 || strcmp (str + strlen (str) - 5, "any2t") == 0)
10357 && (regno & 1) != 0)
10358 as_warn (_("Condition code register should be even for %s, "
10361 if ((strcmp (str + strlen (str) - 5, "any4f") == 0
10362 || strcmp (str + strlen (str) - 5, "any4t") == 0)
10363 && (regno & 3) != 0)
10364 as_warn (_("Condition code register should be 0 or 4 for %s, "
10368 INSERT_OPERAND (BCC, *ip, regno);
10370 INSERT_OPERAND (CCC, *ip, regno);
10374 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
10385 while (ISDIGIT (*s));
10388 c = 8; /* Invalid sel value. */
10391 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
10392 ip->insn_opcode |= c;
10396 /* Must be at least one digit. */
10397 my_getExpression (&imm_expr, s);
10398 check_absolute_expr (ip, &imm_expr);
10400 if ((unsigned long) imm_expr.X_add_number
10401 > (unsigned long) OP_MASK_VECBYTE)
10403 as_bad (_("bad byte vector index (%ld)"),
10404 (long) imm_expr.X_add_number);
10405 imm_expr.X_add_number = 0;
10408 INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number);
10409 imm_expr.X_op = O_absent;
10414 my_getExpression (&imm_expr, s);
10415 check_absolute_expr (ip, &imm_expr);
10417 if ((unsigned long) imm_expr.X_add_number
10418 > (unsigned long) OP_MASK_VECALIGN)
10420 as_bad (_("bad byte vector index (%ld)"),
10421 (long) imm_expr.X_add_number);
10422 imm_expr.X_add_number = 0;
10425 INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number);
10426 imm_expr.X_op = O_absent;
10431 as_bad (_("Bad char = '%c'\n"), *args);
10436 /* Args don't match. */
10437 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
10438 !strcmp (insn->name, insn[1].name))
10442 insn_error = _("Illegal operands");
10446 *(--argsStart) = save_c;
10447 insn_error = _("Illegal operands");
10452 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
10454 /* This routine assembles an instruction into its binary format when
10455 assembling for the mips16. As a side effect, it sets one of the
10456 global variables imm_reloc or offset_reloc to the type of
10457 relocation to do if one of the operands is an address expression.
10458 It also sets mips16_small and mips16_ext if the user explicitly
10459 requested a small or extended instruction. */
10462 mips16_ip (char *str, struct mips_cl_insn *ip)
10466 struct mips_opcode *insn;
10468 unsigned int regno;
10469 unsigned int lastregno = 0;
10475 mips16_small = FALSE;
10476 mips16_ext = FALSE;
10478 for (s = str; ISLOWER (*s); ++s)
10490 if (s[1] == 't' && s[2] == ' ')
10493 mips16_small = TRUE;
10497 else if (s[1] == 'e' && s[2] == ' ')
10504 /* Fall through. */
10506 insn_error = _("unknown opcode");
10510 if (mips_opts.noautoextend && ! mips16_ext)
10511 mips16_small = TRUE;
10513 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
10515 insn_error = _("unrecognized opcode");
10524 gas_assert (strcmp (insn->name, str) == 0);
10526 ok = is_opcode_valid_16 (insn);
10529 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
10530 && strcmp (insn->name, insn[1].name) == 0)
10539 static char buf[100];
10541 _("opcode not supported on this processor: %s (%s)"),
10542 mips_cpu_info_from_arch (mips_opts.arch)->name,
10543 mips_cpu_info_from_isa (mips_opts.isa)->name);
10550 create_insn (ip, insn);
10551 imm_expr.X_op = O_absent;
10552 imm_reloc[0] = BFD_RELOC_UNUSED;
10553 imm_reloc[1] = BFD_RELOC_UNUSED;
10554 imm_reloc[2] = BFD_RELOC_UNUSED;
10555 imm2_expr.X_op = O_absent;
10556 offset_expr.X_op = O_absent;
10557 offset_reloc[0] = BFD_RELOC_UNUSED;
10558 offset_reloc[1] = BFD_RELOC_UNUSED;
10559 offset_reloc[2] = BFD_RELOC_UNUSED;
10560 for (args = insn->args; 1; ++args)
10567 /* In this switch statement we call break if we did not find
10568 a match, continue if we did find a match, or return if we
10577 /* Stuff the immediate value in now, if we can. */
10578 if (imm_expr.X_op == O_constant
10579 && *imm_reloc > BFD_RELOC_UNUSED
10580 && *imm_reloc != BFD_RELOC_MIPS16_GOT16
10581 && *imm_reloc != BFD_RELOC_MIPS16_CALL16
10582 && insn->pinfo != INSN_MACRO)
10586 switch (*offset_reloc)
10588 case BFD_RELOC_MIPS16_HI16_S:
10589 tmp = (imm_expr.X_add_number + 0x8000) >> 16;
10592 case BFD_RELOC_MIPS16_HI16:
10593 tmp = imm_expr.X_add_number >> 16;
10596 case BFD_RELOC_MIPS16_LO16:
10597 tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff)
10601 case BFD_RELOC_UNUSED:
10602 tmp = imm_expr.X_add_number;
10608 *offset_reloc = BFD_RELOC_UNUSED;
10610 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
10611 tmp, TRUE, mips16_small,
10612 mips16_ext, &ip->insn_opcode,
10613 &ip->use_extend, &ip->extend);
10614 imm_expr.X_op = O_absent;
10615 *imm_reloc = BFD_RELOC_UNUSED;
10629 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10632 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10648 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10650 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10654 /* Fall through. */
10665 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
10667 if (c == 'v' || c == 'w')
10670 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10672 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10683 if (c == 'v' || c == 'w')
10685 regno = mips16_to_32_reg_map[lastregno];
10699 regno = mips32_to_16_reg_map[regno];
10704 regno = ILLEGAL_REG;
10709 regno = ILLEGAL_REG;
10714 regno = ILLEGAL_REG;
10719 if (regno == AT && mips_opts.at)
10721 if (mips_opts.at == ATREG)
10722 as_warn (_("used $at without \".set noat\""));
10724 as_warn (_("used $%u with \".set at=$%u\""),
10725 regno, mips_opts.at);
10733 if (regno == ILLEGAL_REG)
10740 MIPS16_INSERT_OPERAND (RX, *ip, regno);
10744 MIPS16_INSERT_OPERAND (RY, *ip, regno);
10747 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
10750 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
10756 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
10759 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
10760 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
10770 if (strncmp (s, "$pc", 3) == 0)
10787 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
10790 if (imm_expr.X_op != O_constant)
10793 ip->use_extend = TRUE;
10798 /* We need to relax this instruction. */
10799 *offset_reloc = *imm_reloc;
10800 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10805 *imm_reloc = BFD_RELOC_UNUSED;
10806 /* Fall through. */
10813 my_getExpression (&imm_expr, s);
10814 if (imm_expr.X_op == O_register)
10816 /* What we thought was an expression turned out to
10819 if (s[0] == '(' && args[1] == '(')
10821 /* It looks like the expression was omitted
10822 before a register indirection, which means
10823 that the expression is implicitly zero. We
10824 still set up imm_expr, so that we handle
10825 explicit extensions correctly. */
10826 imm_expr.X_op = O_constant;
10827 imm_expr.X_add_number = 0;
10828 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10835 /* We need to relax this instruction. */
10836 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10845 /* We use offset_reloc rather than imm_reloc for the PC
10846 relative operands. This lets macros with both
10847 immediate and address operands work correctly. */
10848 my_getExpression (&offset_expr, s);
10850 if (offset_expr.X_op == O_register)
10853 /* We need to relax this instruction. */
10854 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
10858 case '6': /* break code */
10859 my_getExpression (&imm_expr, s);
10860 check_absolute_expr (ip, &imm_expr);
10861 if ((unsigned long) imm_expr.X_add_number > 63)
10862 as_warn (_("Invalid value for `%s' (%lu)"),
10864 (unsigned long) imm_expr.X_add_number);
10865 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
10866 imm_expr.X_op = O_absent;
10870 case 'a': /* 26 bit address */
10871 my_getExpression (&offset_expr, s);
10873 *offset_reloc = BFD_RELOC_MIPS16_JMP;
10874 ip->insn_opcode <<= 16;
10877 case 'l': /* register list for entry macro */
10878 case 'L': /* register list for exit macro */
10888 unsigned int freg, reg1, reg2;
10890 while (*s == ' ' || *s == ',')
10892 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
10894 else if (reg_lookup (&s, RTYPE_FPU, ®1))
10898 as_bad (_("can't parse register list"));
10908 if (!reg_lookup (&s, freg ? RTYPE_FPU
10909 : (RTYPE_GP | RTYPE_NUM), ®2))
10911 as_bad (_("invalid register list"));
10915 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
10917 mask &= ~ (7 << 3);
10920 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
10922 mask &= ~ (7 << 3);
10925 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
10926 mask |= (reg2 - 3) << 3;
10927 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
10928 mask |= (reg2 - 15) << 1;
10929 else if (reg1 == RA && reg2 == RA)
10933 as_bad (_("invalid register list"));
10937 /* The mask is filled in in the opcode table for the
10938 benefit of the disassembler. We remove it before
10939 applying the actual mask. */
10940 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
10941 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
10945 case 'm': /* Register list for save insn. */
10946 case 'M': /* Register list for restore insn. */
10949 int framesz = 0, seen_framesz = 0;
10950 int nargs = 0, statics = 0, sregs = 0;
10954 unsigned int reg1, reg2;
10956 SKIP_SPACE_TABS (s);
10959 SKIP_SPACE_TABS (s);
10961 my_getExpression (&imm_expr, s);
10962 if (imm_expr.X_op == O_constant)
10964 /* Handle the frame size. */
10967 as_bad (_("more than one frame size in list"));
10971 framesz = imm_expr.X_add_number;
10972 imm_expr.X_op = O_absent;
10977 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
10979 as_bad (_("can't parse register list"));
10991 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2)
10994 as_bad (_("can't parse register list"));
10999 while (reg1 <= reg2)
11001 if (reg1 >= 4 && reg1 <= 7)
11005 nargs |= 1 << (reg1 - 4);
11007 /* statics $a0-$a3 */
11008 statics |= 1 << (reg1 - 4);
11010 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
11013 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
11015 else if (reg1 == 31)
11017 /* Add $ra to insn. */
11022 as_bad (_("unexpected register in list"));
11030 /* Encode args/statics combination. */
11031 if (nargs & statics)
11032 as_bad (_("arg/static registers overlap"));
11033 else if (nargs == 0xf)
11034 /* All $a0-$a3 are args. */
11035 opcode |= MIPS16_ALL_ARGS << 16;
11036 else if (statics == 0xf)
11037 /* All $a0-$a3 are statics. */
11038 opcode |= MIPS16_ALL_STATICS << 16;
11041 int narg = 0, nstat = 0;
11043 /* Count arg registers. */
11044 while (nargs & 0x1)
11050 as_bad (_("invalid arg register list"));
11052 /* Count static registers. */
11053 while (statics & 0x8)
11055 statics = (statics << 1) & 0xf;
11059 as_bad (_("invalid static register list"));
11061 /* Encode args/statics. */
11062 opcode |= ((narg << 2) | nstat) << 16;
11065 /* Encode $s0/$s1. */
11066 if (sregs & (1 << 0)) /* $s0 */
11068 if (sregs & (1 << 1)) /* $s1 */
11074 /* Count regs $s2-$s8. */
11082 as_bad (_("invalid static register list"));
11083 /* Encode $s2-$s8. */
11084 opcode |= nsreg << 24;
11087 /* Encode frame size. */
11089 as_bad (_("missing frame size"));
11090 else if ((framesz & 7) != 0 || framesz < 0
11091 || framesz > 0xff * 8)
11092 as_bad (_("invalid frame size"));
11093 else if (framesz != 128 || (opcode >> 16) != 0)
11096 opcode |= (((framesz & 0xf0) << 16)
11097 | (framesz & 0x0f));
11100 /* Finally build the instruction. */
11101 if ((opcode >> 16) != 0 || framesz == 0)
11103 ip->use_extend = TRUE;
11104 ip->extend = opcode >> 16;
11106 ip->insn_opcode |= opcode & 0x7f;
11110 case 'e': /* extend code */
11111 my_getExpression (&imm_expr, s);
11112 check_absolute_expr (ip, &imm_expr);
11113 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
11115 as_warn (_("Invalid value for `%s' (%lu)"),
11117 (unsigned long) imm_expr.X_add_number);
11118 imm_expr.X_add_number &= 0x7ff;
11120 ip->insn_opcode |= imm_expr.X_add_number;
11121 imm_expr.X_op = O_absent;
11131 /* Args don't match. */
11132 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
11133 strcmp (insn->name, insn[1].name) == 0)
11140 insn_error = _("illegal operands");
11146 /* This structure holds information we know about a mips16 immediate
11149 struct mips16_immed_operand
11151 /* The type code used in the argument string in the opcode table. */
11153 /* The number of bits in the short form of the opcode. */
11155 /* The number of bits in the extended form of the opcode. */
11157 /* The amount by which the short form is shifted when it is used;
11158 for example, the sw instruction has a shift count of 2. */
11160 /* The amount by which the short form is shifted when it is stored
11161 into the instruction code. */
11163 /* Non-zero if the short form is unsigned. */
11165 /* Non-zero if the extended form is unsigned. */
11167 /* Non-zero if the value is PC relative. */
11171 /* The mips16 immediate operand types. */
11173 static const struct mips16_immed_operand mips16_immed_operands[] =
11175 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
11176 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
11177 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
11178 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
11179 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
11180 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
11181 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
11182 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
11183 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
11184 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
11185 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
11186 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
11187 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
11188 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
11189 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
11190 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
11191 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
11192 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
11193 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
11194 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
11195 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
11198 #define MIPS16_NUM_IMMED \
11199 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
11201 /* Handle a mips16 instruction with an immediate value. This or's the
11202 small immediate value into *INSN. It sets *USE_EXTEND to indicate
11203 whether an extended value is needed; if one is needed, it sets
11204 *EXTEND to the value. The argument type is TYPE. The value is VAL.
11205 If SMALL is true, an unextended opcode was explicitly requested.
11206 If EXT is true, an extended opcode was explicitly requested. If
11207 WARN is true, warn if EXT does not match reality. */
11210 mips16_immed (char *file, unsigned int line, int type, offsetT val,
11211 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
11212 unsigned long *insn, bfd_boolean *use_extend,
11213 unsigned short *extend)
11215 const struct mips16_immed_operand *op;
11216 int mintiny, maxtiny;
11217 bfd_boolean needext;
11219 op = mips16_immed_operands;
11220 while (op->type != type)
11223 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
11228 if (type == '<' || type == '>' || type == '[' || type == ']')
11231 maxtiny = 1 << op->nbits;
11236 maxtiny = (1 << op->nbits) - 1;
11241 mintiny = - (1 << (op->nbits - 1));
11242 maxtiny = (1 << (op->nbits - 1)) - 1;
11245 /* Branch offsets have an implicit 0 in the lowest bit. */
11246 if (type == 'p' || type == 'q')
11249 if ((val & ((1 << op->shift) - 1)) != 0
11250 || val < (mintiny << op->shift)
11251 || val > (maxtiny << op->shift))
11256 if (warn && ext && ! needext)
11257 as_warn_where (file, line,
11258 _("extended operand requested but not required"));
11259 if (small && needext)
11260 as_bad_where (file, line, _("invalid unextended operand value"));
11262 if (small || (! ext && ! needext))
11266 *use_extend = FALSE;
11267 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
11268 insnval <<= op->op_shift;
11273 long minext, maxext;
11279 maxext = (1 << op->extbits) - 1;
11283 minext = - (1 << (op->extbits - 1));
11284 maxext = (1 << (op->extbits - 1)) - 1;
11286 if (val < minext || val > maxext)
11287 as_bad_where (file, line,
11288 _("operand value out of range for instruction"));
11290 *use_extend = TRUE;
11291 if (op->extbits == 16)
11293 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
11296 else if (op->extbits == 15)
11298 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
11303 extval = ((val & 0x1f) << 6) | (val & 0x20);
11307 *extend = (unsigned short) extval;
11312 struct percent_op_match
11315 bfd_reloc_code_real_type reloc;
11318 static const struct percent_op_match mips_percent_op[] =
11320 {"%lo", BFD_RELOC_LO16},
11322 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
11323 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
11324 {"%call16", BFD_RELOC_MIPS_CALL16},
11325 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
11326 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
11327 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
11328 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
11329 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
11330 {"%got", BFD_RELOC_MIPS_GOT16},
11331 {"%gp_rel", BFD_RELOC_GPREL16},
11332 {"%half", BFD_RELOC_16},
11333 {"%highest", BFD_RELOC_MIPS_HIGHEST},
11334 {"%higher", BFD_RELOC_MIPS_HIGHER},
11335 {"%neg", BFD_RELOC_MIPS_SUB},
11336 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
11337 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
11338 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
11339 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
11340 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
11341 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
11342 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
11344 {"%hi", BFD_RELOC_HI16_S}
11347 static const struct percent_op_match mips16_percent_op[] =
11349 {"%lo", BFD_RELOC_MIPS16_LO16},
11350 {"%gprel", BFD_RELOC_MIPS16_GPREL},
11351 {"%got", BFD_RELOC_MIPS16_GOT16},
11352 {"%call16", BFD_RELOC_MIPS16_CALL16},
11353 {"%hi", BFD_RELOC_MIPS16_HI16_S}
11357 /* Return true if *STR points to a relocation operator. When returning true,
11358 move *STR over the operator and store its relocation code in *RELOC.
11359 Leave both *STR and *RELOC alone when returning false. */
11362 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
11364 const struct percent_op_match *percent_op;
11367 if (mips_opts.mips16)
11369 percent_op = mips16_percent_op;
11370 limit = ARRAY_SIZE (mips16_percent_op);
11374 percent_op = mips_percent_op;
11375 limit = ARRAY_SIZE (mips_percent_op);
11378 for (i = 0; i < limit; i++)
11379 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
11381 int len = strlen (percent_op[i].str);
11383 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
11386 *str += strlen (percent_op[i].str);
11387 *reloc = percent_op[i].reloc;
11389 /* Check whether the output BFD supports this relocation.
11390 If not, issue an error and fall back on something safe. */
11391 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
11393 as_bad (_("relocation %s isn't supported by the current ABI"),
11394 percent_op[i].str);
11395 *reloc = BFD_RELOC_UNUSED;
11403 /* Parse string STR as a 16-bit relocatable operand. Store the
11404 expression in *EP and the relocations in the array starting
11405 at RELOC. Return the number of relocation operators used.
11407 On exit, EXPR_END points to the first character after the expression. */
11410 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
11413 bfd_reloc_code_real_type reversed_reloc[3];
11414 size_t reloc_index, i;
11415 int crux_depth, str_depth;
11418 /* Search for the start of the main expression, recoding relocations
11419 in REVERSED_RELOC. End the loop with CRUX pointing to the start
11420 of the main expression and with CRUX_DEPTH containing the number
11421 of open brackets at that point. */
11428 crux_depth = str_depth;
11430 /* Skip over whitespace and brackets, keeping count of the number
11432 while (*str == ' ' || *str == '\t' || *str == '(')
11437 && reloc_index < (HAVE_NEWABI ? 3 : 1)
11438 && parse_relocation (&str, &reversed_reloc[reloc_index]));
11440 my_getExpression (ep, crux);
11443 /* Match every open bracket. */
11444 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
11448 if (crux_depth > 0)
11449 as_bad (_("unclosed '('"));
11453 if (reloc_index != 0)
11455 prev_reloc_op_frag = frag_now;
11456 for (i = 0; i < reloc_index; i++)
11457 reloc[i] = reversed_reloc[reloc_index - 1 - i];
11460 return reloc_index;
11464 my_getExpression (expressionS *ep, char *str)
11468 save_in = input_line_pointer;
11469 input_line_pointer = str;
11471 expr_end = input_line_pointer;
11472 input_line_pointer = save_in;
11476 md_atof (int type, char *litP, int *sizeP)
11478 return ieee_md_atof (type, litP, sizeP, target_big_endian);
11482 md_number_to_chars (char *buf, valueT val, int n)
11484 if (target_big_endian)
11485 number_to_chars_bigendian (buf, val, n);
11487 number_to_chars_littleendian (buf, val, n);
11491 static int support_64bit_objects(void)
11493 const char **list, **l;
11496 list = bfd_target_list ();
11497 for (l = list; *l != NULL; l++)
11498 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
11499 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
11501 yes = (*l != NULL);
11505 #endif /* OBJ_ELF */
11507 const char *md_shortopts = "O::g::G:";
11511 OPTION_MARCH = OPTION_MD_BASE,
11533 OPTION_NO_SMARTMIPS,
11536 OPTION_COMPAT_ARCH_BASE,
11545 OPTION_M7000_HILO_FIX,
11546 OPTION_MNO_7000_HILO_FIX,
11549 OPTION_FIX_LOONGSON2F_JUMP,
11550 OPTION_NO_FIX_LOONGSON2F_JUMP,
11551 OPTION_FIX_LOONGSON2F_NOP,
11552 OPTION_NO_FIX_LOONGSON2F_NOP,
11554 OPTION_NO_FIX_VR4120,
11556 OPTION_NO_FIX_VR4130,
11557 OPTION_FIX_CN63XXP1,
11558 OPTION_NO_FIX_CN63XXP1,
11565 OPTION_CONSTRUCT_FLOATS,
11566 OPTION_NO_CONSTRUCT_FLOATS,
11569 OPTION_RELAX_BRANCH,
11570 OPTION_NO_RELAX_BRANCH,
11577 OPTION_SINGLE_FLOAT,
11578 OPTION_DOUBLE_FLOAT,
11581 OPTION_CALL_SHARED,
11582 OPTION_CALL_NONPIC,
11592 OPTION_MVXWORKS_PIC,
11593 #endif /* OBJ_ELF */
11597 struct option md_longopts[] =
11599 /* Options which specify architecture. */
11600 {"march", required_argument, NULL, OPTION_MARCH},
11601 {"mtune", required_argument, NULL, OPTION_MTUNE},
11602 {"mips0", no_argument, NULL, OPTION_MIPS1},
11603 {"mips1", no_argument, NULL, OPTION_MIPS1},
11604 {"mips2", no_argument, NULL, OPTION_MIPS2},
11605 {"mips3", no_argument, NULL, OPTION_MIPS3},
11606 {"mips4", no_argument, NULL, OPTION_MIPS4},
11607 {"mips5", no_argument, NULL, OPTION_MIPS5},
11608 {"mips32", no_argument, NULL, OPTION_MIPS32},
11609 {"mips64", no_argument, NULL, OPTION_MIPS64},
11610 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
11611 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
11613 /* Options which specify Application Specific Extensions (ASEs). */
11614 {"mips16", no_argument, NULL, OPTION_MIPS16},
11615 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
11616 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
11617 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
11618 {"mdmx", no_argument, NULL, OPTION_MDMX},
11619 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
11620 {"mdsp", no_argument, NULL, OPTION_DSP},
11621 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
11622 {"mmt", no_argument, NULL, OPTION_MT},
11623 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
11624 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
11625 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
11626 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
11627 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
11629 /* Old-style architecture options. Don't add more of these. */
11630 {"m4650", no_argument, NULL, OPTION_M4650},
11631 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
11632 {"m4010", no_argument, NULL, OPTION_M4010},
11633 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
11634 {"m4100", no_argument, NULL, OPTION_M4100},
11635 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
11636 {"m3900", no_argument, NULL, OPTION_M3900},
11637 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
11639 /* Options which enable bug fixes. */
11640 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
11641 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
11642 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
11643 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
11644 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
11645 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
11646 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
11647 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
11648 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
11649 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
11650 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
11651 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
11652 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
11653 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
11654 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
11656 /* Miscellaneous options. */
11657 {"trap", no_argument, NULL, OPTION_TRAP},
11658 {"no-break", no_argument, NULL, OPTION_TRAP},
11659 {"break", no_argument, NULL, OPTION_BREAK},
11660 {"no-trap", no_argument, NULL, OPTION_BREAK},
11661 {"EB", no_argument, NULL, OPTION_EB},
11662 {"EL", no_argument, NULL, OPTION_EL},
11663 {"mfp32", no_argument, NULL, OPTION_FP32},
11664 {"mgp32", no_argument, NULL, OPTION_GP32},
11665 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
11666 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
11667 {"mfp64", no_argument, NULL, OPTION_FP64},
11668 {"mgp64", no_argument, NULL, OPTION_GP64},
11669 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
11670 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
11671 {"mshared", no_argument, NULL, OPTION_MSHARED},
11672 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
11673 {"msym32", no_argument, NULL, OPTION_MSYM32},
11674 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
11675 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
11676 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
11677 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
11678 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
11680 /* Strictly speaking this next option is ELF specific,
11681 but we allow it for other ports as well in order to
11682 make testing easier. */
11683 {"32", no_argument, NULL, OPTION_32},
11685 /* ELF-specific options. */
11687 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
11688 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
11689 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
11690 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
11691 {"xgot", no_argument, NULL, OPTION_XGOT},
11692 {"mabi", required_argument, NULL, OPTION_MABI},
11693 {"n32", no_argument, NULL, OPTION_N32},
11694 {"64", no_argument, NULL, OPTION_64},
11695 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
11696 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
11697 {"mpdr", no_argument, NULL, OPTION_PDR},
11698 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
11699 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
11700 #endif /* OBJ_ELF */
11702 {NULL, no_argument, NULL, 0}
11704 size_t md_longopts_size = sizeof (md_longopts);
11706 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
11707 NEW_VALUE. Warn if another value was already specified. Note:
11708 we have to defer parsing the -march and -mtune arguments in order
11709 to handle 'from-abi' correctly, since the ABI might be specified
11710 in a later argument. */
11713 mips_set_option_string (const char **string_ptr, const char *new_value)
11715 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
11716 as_warn (_("A different %s was already specified, is now %s"),
11717 string_ptr == &mips_arch_string ? "-march" : "-mtune",
11720 *string_ptr = new_value;
11724 md_parse_option (int c, char *arg)
11728 case OPTION_CONSTRUCT_FLOATS:
11729 mips_disable_float_construction = 0;
11732 case OPTION_NO_CONSTRUCT_FLOATS:
11733 mips_disable_float_construction = 1;
11745 target_big_endian = 1;
11749 target_big_endian = 0;
11755 else if (arg[0] == '0')
11757 else if (arg[0] == '1')
11767 mips_debug = atoi (arg);
11771 file_mips_isa = ISA_MIPS1;
11775 file_mips_isa = ISA_MIPS2;
11779 file_mips_isa = ISA_MIPS3;
11783 file_mips_isa = ISA_MIPS4;
11787 file_mips_isa = ISA_MIPS5;
11790 case OPTION_MIPS32:
11791 file_mips_isa = ISA_MIPS32;
11794 case OPTION_MIPS32R2:
11795 file_mips_isa = ISA_MIPS32R2;
11798 case OPTION_MIPS64R2:
11799 file_mips_isa = ISA_MIPS64R2;
11802 case OPTION_MIPS64:
11803 file_mips_isa = ISA_MIPS64;
11807 mips_set_option_string (&mips_tune_string, arg);
11811 mips_set_option_string (&mips_arch_string, arg);
11815 mips_set_option_string (&mips_arch_string, "4650");
11816 mips_set_option_string (&mips_tune_string, "4650");
11819 case OPTION_NO_M4650:
11823 mips_set_option_string (&mips_arch_string, "4010");
11824 mips_set_option_string (&mips_tune_string, "4010");
11827 case OPTION_NO_M4010:
11831 mips_set_option_string (&mips_arch_string, "4100");
11832 mips_set_option_string (&mips_tune_string, "4100");
11835 case OPTION_NO_M4100:
11839 mips_set_option_string (&mips_arch_string, "3900");
11840 mips_set_option_string (&mips_tune_string, "3900");
11843 case OPTION_NO_M3900:
11847 mips_opts.ase_mdmx = 1;
11850 case OPTION_NO_MDMX:
11851 mips_opts.ase_mdmx = 0;
11855 mips_opts.ase_dsp = 1;
11856 mips_opts.ase_dspr2 = 0;
11859 case OPTION_NO_DSP:
11860 mips_opts.ase_dsp = 0;
11861 mips_opts.ase_dspr2 = 0;
11865 mips_opts.ase_dspr2 = 1;
11866 mips_opts.ase_dsp = 1;
11869 case OPTION_NO_DSPR2:
11870 mips_opts.ase_dspr2 = 0;
11871 mips_opts.ase_dsp = 0;
11875 mips_opts.ase_mt = 1;
11879 mips_opts.ase_mt = 0;
11882 case OPTION_MIPS16:
11883 mips_opts.mips16 = 1;
11884 mips_no_prev_insn ();
11887 case OPTION_NO_MIPS16:
11888 mips_opts.mips16 = 0;
11889 mips_no_prev_insn ();
11892 case OPTION_MIPS3D:
11893 mips_opts.ase_mips3d = 1;
11896 case OPTION_NO_MIPS3D:
11897 mips_opts.ase_mips3d = 0;
11900 case OPTION_SMARTMIPS:
11901 mips_opts.ase_smartmips = 1;
11904 case OPTION_NO_SMARTMIPS:
11905 mips_opts.ase_smartmips = 0;
11908 case OPTION_FIX_24K:
11912 case OPTION_NO_FIX_24K:
11916 case OPTION_FIX_LOONGSON2F_JUMP:
11917 mips_fix_loongson2f_jump = TRUE;
11920 case OPTION_NO_FIX_LOONGSON2F_JUMP:
11921 mips_fix_loongson2f_jump = FALSE;
11924 case OPTION_FIX_LOONGSON2F_NOP:
11925 mips_fix_loongson2f_nop = TRUE;
11928 case OPTION_NO_FIX_LOONGSON2F_NOP:
11929 mips_fix_loongson2f_nop = FALSE;
11932 case OPTION_FIX_VR4120:
11933 mips_fix_vr4120 = 1;
11936 case OPTION_NO_FIX_VR4120:
11937 mips_fix_vr4120 = 0;
11940 case OPTION_FIX_VR4130:
11941 mips_fix_vr4130 = 1;
11944 case OPTION_NO_FIX_VR4130:
11945 mips_fix_vr4130 = 0;
11948 case OPTION_FIX_CN63XXP1:
11949 mips_fix_cn63xxp1 = TRUE;
11952 case OPTION_NO_FIX_CN63XXP1:
11953 mips_fix_cn63xxp1 = FALSE;
11956 case OPTION_RELAX_BRANCH:
11957 mips_relax_branch = 1;
11960 case OPTION_NO_RELAX_BRANCH:
11961 mips_relax_branch = 0;
11964 case OPTION_MSHARED:
11965 mips_in_shared = TRUE;
11968 case OPTION_MNO_SHARED:
11969 mips_in_shared = FALSE;
11972 case OPTION_MSYM32:
11973 mips_opts.sym32 = TRUE;
11976 case OPTION_MNO_SYM32:
11977 mips_opts.sym32 = FALSE;
11981 /* When generating ELF code, we permit -KPIC and -call_shared to
11982 select SVR4_PIC, and -non_shared to select no PIC. This is
11983 intended to be compatible with Irix 5. */
11984 case OPTION_CALL_SHARED:
11987 as_bad (_("-call_shared is supported only for ELF format"));
11990 mips_pic = SVR4_PIC;
11991 mips_abicalls = TRUE;
11994 case OPTION_CALL_NONPIC:
11997 as_bad (_("-call_nonpic is supported only for ELF format"));
12001 mips_abicalls = TRUE;
12004 case OPTION_NON_SHARED:
12007 as_bad (_("-non_shared is supported only for ELF format"));
12011 mips_abicalls = FALSE;
12014 /* The -xgot option tells the assembler to use 32 bit offsets
12015 when accessing the got in SVR4_PIC mode. It is for Irix
12020 #endif /* OBJ_ELF */
12023 g_switch_value = atoi (arg);
12027 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
12031 mips_abi = O32_ABI;
12032 /* We silently ignore -32 for non-ELF targets. This greatly
12033 simplifies the construction of the MIPS GAS test cases. */
12040 as_bad (_("-n32 is supported for ELF format only"));
12043 mips_abi = N32_ABI;
12049 as_bad (_("-64 is supported for ELF format only"));
12052 mips_abi = N64_ABI;
12053 if (!support_64bit_objects())
12054 as_fatal (_("No compiled in support for 64 bit object file format"));
12056 #endif /* OBJ_ELF */
12059 file_mips_gp32 = 1;
12063 file_mips_gp32 = 0;
12067 file_mips_fp32 = 1;
12071 file_mips_fp32 = 0;
12074 case OPTION_SINGLE_FLOAT:
12075 file_mips_single_float = 1;
12078 case OPTION_DOUBLE_FLOAT:
12079 file_mips_single_float = 0;
12082 case OPTION_SOFT_FLOAT:
12083 file_mips_soft_float = 1;
12086 case OPTION_HARD_FLOAT:
12087 file_mips_soft_float = 0;
12094 as_bad (_("-mabi is supported for ELF format only"));
12097 if (strcmp (arg, "32") == 0)
12098 mips_abi = O32_ABI;
12099 else if (strcmp (arg, "o64") == 0)
12100 mips_abi = O64_ABI;
12101 else if (strcmp (arg, "n32") == 0)
12102 mips_abi = N32_ABI;
12103 else if (strcmp (arg, "64") == 0)
12105 mips_abi = N64_ABI;
12106 if (! support_64bit_objects())
12107 as_fatal (_("No compiled in support for 64 bit object file "
12110 else if (strcmp (arg, "eabi") == 0)
12111 mips_abi = EABI_ABI;
12114 as_fatal (_("invalid abi -mabi=%s"), arg);
12118 #endif /* OBJ_ELF */
12120 case OPTION_M7000_HILO_FIX:
12121 mips_7000_hilo_fix = TRUE;
12124 case OPTION_MNO_7000_HILO_FIX:
12125 mips_7000_hilo_fix = FALSE;
12129 case OPTION_MDEBUG:
12130 mips_flag_mdebug = TRUE;
12133 case OPTION_NO_MDEBUG:
12134 mips_flag_mdebug = FALSE;
12138 mips_flag_pdr = TRUE;
12141 case OPTION_NO_PDR:
12142 mips_flag_pdr = FALSE;
12145 case OPTION_MVXWORKS_PIC:
12146 mips_pic = VXWORKS_PIC;
12148 #endif /* OBJ_ELF */
12154 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
12159 /* Set up globals to generate code for the ISA or processor
12160 described by INFO. */
12163 mips_set_architecture (const struct mips_cpu_info *info)
12167 file_mips_arch = info->cpu;
12168 mips_opts.arch = info->cpu;
12169 mips_opts.isa = info->isa;
12174 /* Likewise for tuning. */
12177 mips_set_tune (const struct mips_cpu_info *info)
12180 mips_tune = info->cpu;
12185 mips_after_parse_args (void)
12187 const struct mips_cpu_info *arch_info = 0;
12188 const struct mips_cpu_info *tune_info = 0;
12190 /* GP relative stuff not working for PE */
12191 if (strncmp (TARGET_OS, "pe", 2) == 0)
12193 if (g_switch_seen && g_switch_value != 0)
12194 as_bad (_("-G not supported in this configuration."));
12195 g_switch_value = 0;
12198 if (mips_abi == NO_ABI)
12199 mips_abi = MIPS_DEFAULT_ABI;
12201 /* The following code determines the architecture and register size.
12202 Similar code was added to GCC 3.3 (see override_options() in
12203 config/mips/mips.c). The GAS and GCC code should be kept in sync
12204 as much as possible. */
12206 if (mips_arch_string != 0)
12207 arch_info = mips_parse_cpu ("-march", mips_arch_string);
12209 if (file_mips_isa != ISA_UNKNOWN)
12211 /* Handle -mipsN. At this point, file_mips_isa contains the
12212 ISA level specified by -mipsN, while arch_info->isa contains
12213 the -march selection (if any). */
12214 if (arch_info != 0)
12216 /* -march takes precedence over -mipsN, since it is more descriptive.
12217 There's no harm in specifying both as long as the ISA levels
12219 if (file_mips_isa != arch_info->isa)
12220 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
12221 mips_cpu_info_from_isa (file_mips_isa)->name,
12222 mips_cpu_info_from_isa (arch_info->isa)->name);
12225 arch_info = mips_cpu_info_from_isa (file_mips_isa);
12228 if (arch_info == 0)
12229 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
12231 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
12232 as_bad (_("-march=%s is not compatible with the selected ABI"),
12235 mips_set_architecture (arch_info);
12237 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
12238 if (mips_tune_string != 0)
12239 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
12241 if (tune_info == 0)
12242 mips_set_tune (arch_info);
12244 mips_set_tune (tune_info);
12246 if (file_mips_gp32 >= 0)
12248 /* The user specified the size of the integer registers. Make sure
12249 it agrees with the ABI and ISA. */
12250 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
12251 as_bad (_("-mgp64 used with a 32-bit processor"));
12252 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
12253 as_bad (_("-mgp32 used with a 64-bit ABI"));
12254 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
12255 as_bad (_("-mgp64 used with a 32-bit ABI"));
12259 /* Infer the integer register size from the ABI and processor.
12260 Restrict ourselves to 32-bit registers if that's all the
12261 processor has, or if the ABI cannot handle 64-bit registers. */
12262 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
12263 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
12266 switch (file_mips_fp32)
12270 /* No user specified float register size.
12271 ??? GAS treats single-float processors as though they had 64-bit
12272 float registers (although it complains when double-precision
12273 instructions are used). As things stand, saying they have 32-bit
12274 registers would lead to spurious "register must be even" messages.
12275 So here we assume float registers are never smaller than the
12277 if (file_mips_gp32 == 0)
12278 /* 64-bit integer registers implies 64-bit float registers. */
12279 file_mips_fp32 = 0;
12280 else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
12281 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
12282 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
12283 file_mips_fp32 = 0;
12285 /* 32-bit float registers. */
12286 file_mips_fp32 = 1;
12289 /* The user specified the size of the float registers. Check if it
12290 agrees with the ABI and ISA. */
12292 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
12293 as_bad (_("-mfp64 used with a 32-bit fpu"));
12294 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
12295 && !ISA_HAS_MXHC1 (mips_opts.isa))
12296 as_warn (_("-mfp64 used with a 32-bit ABI"));
12299 if (ABI_NEEDS_64BIT_REGS (mips_abi))
12300 as_warn (_("-mfp32 used with a 64-bit ABI"));
12304 /* End of GCC-shared inference code. */
12306 /* This flag is set when we have a 64-bit capable CPU but use only
12307 32-bit wide registers. Note that EABI does not use it. */
12308 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
12309 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
12310 || mips_abi == O32_ABI))
12311 mips_32bitmode = 1;
12313 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
12314 as_bad (_("trap exception not supported at ISA 1"));
12316 /* If the selected architecture includes support for ASEs, enable
12317 generation of code for them. */
12318 if (mips_opts.mips16 == -1)
12319 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
12320 if (mips_opts.ase_mips3d == -1)
12321 mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
12322 && file_mips_fp32 == 0) ? 1 : 0;
12323 if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
12324 as_bad (_("-mfp32 used with -mips3d"));
12326 if (mips_opts.ase_mdmx == -1)
12327 mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
12328 && file_mips_fp32 == 0) ? 1 : 0;
12329 if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
12330 as_bad (_("-mfp32 used with -mdmx"));
12332 if (mips_opts.ase_smartmips == -1)
12333 mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
12334 if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
12335 as_warn (_("%s ISA does not support SmartMIPS"),
12336 mips_cpu_info_from_isa (mips_opts.isa)->name);
12338 if (mips_opts.ase_dsp == -1)
12339 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
12340 if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
12341 as_warn (_("%s ISA does not support DSP ASE"),
12342 mips_cpu_info_from_isa (mips_opts.isa)->name);
12344 if (mips_opts.ase_dspr2 == -1)
12346 mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
12347 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
12349 if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
12350 as_warn (_("%s ISA does not support DSP R2 ASE"),
12351 mips_cpu_info_from_isa (mips_opts.isa)->name);
12353 if (mips_opts.ase_mt == -1)
12354 mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
12355 if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
12356 as_warn (_("%s ISA does not support MT ASE"),
12357 mips_cpu_info_from_isa (mips_opts.isa)->name);
12359 file_mips_isa = mips_opts.isa;
12360 file_ase_mips3d = mips_opts.ase_mips3d;
12361 file_ase_mdmx = mips_opts.ase_mdmx;
12362 file_ase_smartmips = mips_opts.ase_smartmips;
12363 file_ase_dsp = mips_opts.ase_dsp;
12364 file_ase_dspr2 = mips_opts.ase_dspr2;
12365 file_ase_mt = mips_opts.ase_mt;
12366 mips_opts.gp32 = file_mips_gp32;
12367 mips_opts.fp32 = file_mips_fp32;
12368 mips_opts.soft_float = file_mips_soft_float;
12369 mips_opts.single_float = file_mips_single_float;
12371 if (mips_flag_mdebug < 0)
12373 #ifdef OBJ_MAYBE_ECOFF
12374 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
12375 mips_flag_mdebug = 1;
12377 #endif /* OBJ_MAYBE_ECOFF */
12378 mips_flag_mdebug = 0;
12383 mips_init_after_args (void)
12385 /* initialize opcodes */
12386 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
12387 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
12391 md_pcrel_from (fixS *fixP)
12393 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
12394 switch (fixP->fx_r_type)
12396 case BFD_RELOC_16_PCREL_S2:
12397 case BFD_RELOC_MIPS_JMP:
12398 /* Return the address of the delay slot. */
12401 /* We have no relocation type for PC relative MIPS16 instructions. */
12402 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
12403 as_bad_where (fixP->fx_file, fixP->fx_line,
12404 _("PC relative MIPS16 instruction references a different section"));
12409 /* This is called before the symbol table is processed. In order to
12410 work with gcc when using mips-tfile, we must keep all local labels.
12411 However, in other cases, we want to discard them. If we were
12412 called with -g, but we didn't see any debugging information, it may
12413 mean that gcc is smuggling debugging information through to
12414 mips-tfile, in which case we must generate all local labels. */
12417 mips_frob_file_before_adjust (void)
12419 #ifndef NO_ECOFF_DEBUGGING
12420 if (ECOFF_DEBUGGING
12422 && ! ecoff_debugging_seen)
12423 flag_keep_locals = 1;
12427 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
12428 the corresponding LO16 reloc. This is called before md_apply_fix and
12429 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
12430 relocation operators.
12432 For our purposes, a %lo() expression matches a %got() or %hi()
12435 (a) it refers to the same symbol; and
12436 (b) the offset applied in the %lo() expression is no lower than
12437 the offset applied in the %got() or %hi().
12439 (b) allows us to cope with code like:
12442 lh $4,%lo(foo+2)($4)
12444 ...which is legal on RELA targets, and has a well-defined behaviour
12445 if the user knows that adding 2 to "foo" will not induce a carry to
12448 When several %lo()s match a particular %got() or %hi(), we use the
12449 following rules to distinguish them:
12451 (1) %lo()s with smaller offsets are a better match than %lo()s with
12454 (2) %lo()s with no matching %got() or %hi() are better than those
12455 that already have a matching %got() or %hi().
12457 (3) later %lo()s are better than earlier %lo()s.
12459 These rules are applied in order.
12461 (1) means, among other things, that %lo()s with identical offsets are
12462 chosen if they exist.
12464 (2) means that we won't associate several high-part relocations with
12465 the same low-part relocation unless there's no alternative. Having
12466 several high parts for the same low part is a GNU extension; this rule
12467 allows careful users to avoid it.
12469 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
12470 with the last high-part relocation being at the front of the list.
12471 It therefore makes sense to choose the last matching low-part
12472 relocation, all other things being equal. It's also easier
12473 to code that way. */
12476 mips_frob_file (void)
12478 struct mips_hi_fixup *l;
12479 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
12481 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
12483 segment_info_type *seginfo;
12484 bfd_boolean matched_lo_p;
12485 fixS **hi_pos, **lo_pos, **pos;
12487 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
12489 /* If a GOT16 relocation turns out to be against a global symbol,
12490 there isn't supposed to be a matching LO. */
12491 if (got16_reloc_p (l->fixp->fx_r_type)
12492 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
12495 /* Check quickly whether the next fixup happens to be a matching %lo. */
12496 if (fixup_has_matching_lo_p (l->fixp))
12499 seginfo = seg_info (l->seg);
12501 /* Set HI_POS to the position of this relocation in the chain.
12502 Set LO_POS to the position of the chosen low-part relocation.
12503 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
12504 relocation that matches an immediately-preceding high-part
12508 matched_lo_p = FALSE;
12509 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
12511 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
12513 if (*pos == l->fixp)
12516 if ((*pos)->fx_r_type == looking_for_rtype
12517 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
12518 && (*pos)->fx_offset >= l->fixp->fx_offset
12520 || (*pos)->fx_offset < (*lo_pos)->fx_offset
12522 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
12525 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
12526 && fixup_has_matching_lo_p (*pos));
12529 /* If we found a match, remove the high-part relocation from its
12530 current position and insert it before the low-part relocation.
12531 Make the offsets match so that fixup_has_matching_lo_p()
12534 We don't warn about unmatched high-part relocations since some
12535 versions of gcc have been known to emit dead "lui ...%hi(...)"
12537 if (lo_pos != NULL)
12539 l->fixp->fx_offset = (*lo_pos)->fx_offset;
12540 if (l->fixp->fx_next != *lo_pos)
12542 *hi_pos = l->fixp->fx_next;
12543 l->fixp->fx_next = *lo_pos;
12550 /* We may have combined relocations without symbols in the N32/N64 ABI.
12551 We have to prevent gas from dropping them. */
12554 mips_force_relocation (fixS *fixp)
12556 if (generic_force_reloc (fixp))
12560 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
12561 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
12562 || hi16_reloc_p (fixp->fx_r_type)
12563 || lo16_reloc_p (fixp->fx_r_type)))
12569 /* Apply a fixup to the object file. */
12572 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
12576 reloc_howto_type *howto;
12578 /* We ignore generic BFD relocations we don't know about. */
12579 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
12583 gas_assert (fixP->fx_size == 4
12584 || fixP->fx_r_type == BFD_RELOC_16
12585 || fixP->fx_r_type == BFD_RELOC_64
12586 || fixP->fx_r_type == BFD_RELOC_CTOR
12587 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
12588 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12589 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
12590 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
12592 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
12594 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2);
12596 /* Don't treat parts of a composite relocation as done. There are two
12599 (1) The second and third parts will be against 0 (RSS_UNDEF) but
12600 should nevertheless be emitted if the first part is.
12602 (2) In normal usage, composite relocations are never assembly-time
12603 constants. The easiest way of dealing with the pathological
12604 exceptions is to generate a relocation against STN_UNDEF and
12605 leave everything up to the linker. */
12606 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
12609 switch (fixP->fx_r_type)
12611 case BFD_RELOC_MIPS_TLS_GD:
12612 case BFD_RELOC_MIPS_TLS_LDM:
12613 case BFD_RELOC_MIPS_TLS_DTPREL32:
12614 case BFD_RELOC_MIPS_TLS_DTPREL64:
12615 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
12616 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
12617 case BFD_RELOC_MIPS_TLS_GOTTPREL:
12618 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
12619 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
12620 S_SET_THREAD_LOCAL (fixP->fx_addsy);
12623 case BFD_RELOC_MIPS_JMP:
12624 case BFD_RELOC_MIPS_SHIFT5:
12625 case BFD_RELOC_MIPS_SHIFT6:
12626 case BFD_RELOC_MIPS_GOT_DISP:
12627 case BFD_RELOC_MIPS_GOT_PAGE:
12628 case BFD_RELOC_MIPS_GOT_OFST:
12629 case BFD_RELOC_MIPS_SUB:
12630 case BFD_RELOC_MIPS_INSERT_A:
12631 case BFD_RELOC_MIPS_INSERT_B:
12632 case BFD_RELOC_MIPS_DELETE:
12633 case BFD_RELOC_MIPS_HIGHEST:
12634 case BFD_RELOC_MIPS_HIGHER:
12635 case BFD_RELOC_MIPS_SCN_DISP:
12636 case BFD_RELOC_MIPS_REL16:
12637 case BFD_RELOC_MIPS_RELGOT:
12638 case BFD_RELOC_MIPS_JALR:
12639 case BFD_RELOC_HI16:
12640 case BFD_RELOC_HI16_S:
12641 case BFD_RELOC_GPREL16:
12642 case BFD_RELOC_MIPS_LITERAL:
12643 case BFD_RELOC_MIPS_CALL16:
12644 case BFD_RELOC_MIPS_GOT16:
12645 case BFD_RELOC_GPREL32:
12646 case BFD_RELOC_MIPS_GOT_HI16:
12647 case BFD_RELOC_MIPS_GOT_LO16:
12648 case BFD_RELOC_MIPS_CALL_HI16:
12649 case BFD_RELOC_MIPS_CALL_LO16:
12650 case BFD_RELOC_MIPS16_GPREL:
12651 case BFD_RELOC_MIPS16_GOT16:
12652 case BFD_RELOC_MIPS16_CALL16:
12653 case BFD_RELOC_MIPS16_HI16:
12654 case BFD_RELOC_MIPS16_HI16_S:
12655 case BFD_RELOC_MIPS16_JMP:
12656 /* Nothing needed to do. The value comes from the reloc entry. */
12660 /* This is handled like BFD_RELOC_32, but we output a sign
12661 extended value if we are only 32 bits. */
12664 if (8 <= sizeof (valueT))
12665 md_number_to_chars ((char *) buf, *valP, 8);
12670 if ((*valP & 0x80000000) != 0)
12674 md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)),
12676 md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)),
12682 case BFD_RELOC_RVA:
12685 /* If we are deleting this reloc entry, we must fill in the
12686 value now. This can happen if we have a .word which is not
12687 resolved when it appears but is later defined. */
12689 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
12692 case BFD_RELOC_LO16:
12693 case BFD_RELOC_MIPS16_LO16:
12694 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
12695 may be safe to remove, but if so it's not obvious. */
12696 /* When handling an embedded PIC switch statement, we can wind
12697 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
12700 if (*valP + 0x8000 > 0xffff)
12701 as_bad_where (fixP->fx_file, fixP->fx_line,
12702 _("relocation overflow"));
12703 if (target_big_endian)
12705 md_number_to_chars ((char *) buf, *valP, 2);
12709 case BFD_RELOC_16_PCREL_S2:
12710 if ((*valP & 0x3) != 0)
12711 as_bad_where (fixP->fx_file, fixP->fx_line,
12712 _("Branch to misaligned address (%lx)"), (long) *valP);
12714 /* We need to save the bits in the instruction since fixup_segment()
12715 might be deleting the relocation entry (i.e., a branch within
12716 the current segment). */
12717 if (! fixP->fx_done)
12720 /* Update old instruction data. */
12721 if (target_big_endian)
12722 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
12724 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
12726 if (*valP + 0x20000 <= 0x3ffff)
12728 insn |= (*valP >> 2) & 0xffff;
12729 md_number_to_chars ((char *) buf, insn, 4);
12731 else if (mips_pic == NO_PIC
12733 && fixP->fx_frag->fr_address >= text_section->vma
12734 && (fixP->fx_frag->fr_address
12735 < text_section->vma + bfd_get_section_size (text_section))
12736 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
12737 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
12738 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
12740 /* The branch offset is too large. If this is an
12741 unconditional branch, and we are not generating PIC code,
12742 we can convert it to an absolute jump instruction. */
12743 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
12744 insn = 0x0c000000; /* jal */
12746 insn = 0x08000000; /* j */
12747 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
12749 fixP->fx_addsy = section_symbol (text_section);
12750 *valP += md_pcrel_from (fixP);
12751 md_number_to_chars ((char *) buf, insn, 4);
12755 /* If we got here, we have branch-relaxation disabled,
12756 and there's nothing we can do to fix this instruction
12757 without turning it into a longer sequence. */
12758 as_bad_where (fixP->fx_file, fixP->fx_line,
12759 _("Branch out of range"));
12763 case BFD_RELOC_VTABLE_INHERIT:
12766 && !S_IS_DEFINED (fixP->fx_addsy)
12767 && !S_IS_WEAK (fixP->fx_addsy))
12768 S_SET_WEAK (fixP->fx_addsy);
12771 case BFD_RELOC_VTABLE_ENTRY:
12779 /* Remember value for tc_gen_reloc. */
12780 fixP->fx_addnumber = *valP;
12790 name = input_line_pointer;
12791 c = get_symbol_end ();
12792 p = (symbolS *) symbol_find_or_make (name);
12793 *input_line_pointer = c;
12797 /* Align the current frag to a given power of two. If a particular
12798 fill byte should be used, FILL points to an integer that contains
12799 that byte, otherwise FILL is null.
12801 The MIPS assembler also automatically adjusts any preceding
12805 mips_align (int to, int *fill, symbolS *label)
12807 mips_emit_delays ();
12808 mips_record_mips16_mode ();
12809 if (fill == NULL && subseg_text_p (now_seg))
12810 frag_align_code (to, 0);
12812 frag_align (to, fill ? *fill : 0, 0);
12813 record_alignment (now_seg, to);
12816 gas_assert (S_GET_SEGMENT (label) == now_seg);
12817 symbol_set_frag (label, frag_now);
12818 S_SET_VALUE (label, (valueT) frag_now_fix ());
12822 /* Align to a given power of two. .align 0 turns off the automatic
12823 alignment used by the data creating pseudo-ops. */
12826 s_align (int x ATTRIBUTE_UNUSED)
12828 int temp, fill_value, *fill_ptr;
12829 long max_alignment = 28;
12831 /* o Note that the assembler pulls down any immediately preceding label
12832 to the aligned address.
12833 o It's not documented but auto alignment is reinstated by
12834 a .align pseudo instruction.
12835 o Note also that after auto alignment is turned off the mips assembler
12836 issues an error on attempt to assemble an improperly aligned data item.
12839 temp = get_absolute_expression ();
12840 if (temp > max_alignment)
12841 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
12844 as_warn (_("Alignment negative: 0 assumed."));
12847 if (*input_line_pointer == ',')
12849 ++input_line_pointer;
12850 fill_value = get_absolute_expression ();
12851 fill_ptr = &fill_value;
12857 segment_info_type *si = seg_info (now_seg);
12858 struct insn_label_list *l = si->label_list;
12859 /* Auto alignment should be switched on by next section change. */
12861 mips_align (temp, fill_ptr, l != NULL ? l->label : NULL);
12868 demand_empty_rest_of_line ();
12872 s_change_sec (int sec)
12877 /* The ELF backend needs to know that we are changing sections, so
12878 that .previous works correctly. We could do something like check
12879 for an obj_section_change_hook macro, but that might be confusing
12880 as it would not be appropriate to use it in the section changing
12881 functions in read.c, since obj-elf.c intercepts those. FIXME:
12882 This should be cleaner, somehow. */
12884 obj_elf_section_change_hook ();
12887 mips_emit_delays ();
12898 subseg_set (bss_section, (subsegT) get_absolute_expression ());
12899 demand_empty_rest_of_line ();
12903 seg = subseg_new (RDATA_SECTION_NAME,
12904 (subsegT) get_absolute_expression ());
12907 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
12908 | SEC_READONLY | SEC_RELOC
12910 if (strncmp (TARGET_OS, "elf", 3) != 0)
12911 record_alignment (seg, 4);
12913 demand_empty_rest_of_line ();
12917 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
12920 bfd_set_section_flags (stdoutput, seg,
12921 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
12922 if (strncmp (TARGET_OS, "elf", 3) != 0)
12923 record_alignment (seg, 4);
12925 demand_empty_rest_of_line ();
12929 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
12932 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
12933 if (strncmp (TARGET_OS, "elf", 3) != 0)
12934 record_alignment (seg, 4);
12936 demand_empty_rest_of_line ();
12944 s_change_section (int ignore ATTRIBUTE_UNUSED)
12947 char *section_name;
12952 int section_entry_size;
12953 int section_alignment;
12958 section_name = input_line_pointer;
12959 c = get_symbol_end ();
12961 next_c = *(input_line_pointer + 1);
12963 /* Do we have .section Name<,"flags">? */
12964 if (c != ',' || (c == ',' && next_c == '"'))
12966 /* just after name is now '\0'. */
12967 *input_line_pointer = c;
12968 input_line_pointer = section_name;
12969 obj_elf_section (ignore);
12972 input_line_pointer++;
12974 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
12976 section_type = get_absolute_expression ();
12979 if (*input_line_pointer++ == ',')
12980 section_flag = get_absolute_expression ();
12983 if (*input_line_pointer++ == ',')
12984 section_entry_size = get_absolute_expression ();
12986 section_entry_size = 0;
12987 if (*input_line_pointer++ == ',')
12988 section_alignment = get_absolute_expression ();
12990 section_alignment = 0;
12991 /* FIXME: really ignore? */
12992 (void) section_alignment;
12994 section_name = xstrdup (section_name);
12996 /* When using the generic form of .section (as implemented by obj-elf.c),
12997 there's no way to set the section type to SHT_MIPS_DWARF. Users have
12998 traditionally had to fall back on the more common @progbits instead.
13000 There's nothing really harmful in this, since bfd will correct
13001 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
13002 means that, for backwards compatibility, the special_section entries
13003 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
13005 Even so, we shouldn't force users of the MIPS .section syntax to
13006 incorrectly label the sections as SHT_PROGBITS. The best compromise
13007 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
13008 generic type-checking code. */
13009 if (section_type == SHT_MIPS_DWARF)
13010 section_type = SHT_PROGBITS;
13012 obj_elf_change_section (section_name, section_type, section_flag,
13013 section_entry_size, 0, 0, 0);
13015 if (now_seg->name != section_name)
13016 free (section_name);
13017 #endif /* OBJ_ELF */
13021 mips_enable_auto_align (void)
13027 s_cons (int log_size)
13029 segment_info_type *si = seg_info (now_seg);
13030 struct insn_label_list *l = si->label_list;
13033 label = l != NULL ? l->label : NULL;
13034 mips_emit_delays ();
13035 if (log_size > 0 && auto_align)
13036 mips_align (log_size, 0, label);
13037 cons (1 << log_size);
13038 mips_clear_insn_labels ();
13042 s_float_cons (int type)
13044 segment_info_type *si = seg_info (now_seg);
13045 struct insn_label_list *l = si->label_list;
13048 label = l != NULL ? l->label : NULL;
13050 mips_emit_delays ();
13055 mips_align (3, 0, label);
13057 mips_align (2, 0, label);
13061 mips_clear_insn_labels ();
13064 /* Handle .globl. We need to override it because on Irix 5 you are
13067 where foo is an undefined symbol, to mean that foo should be
13068 considered to be the address of a function. */
13071 s_mips_globl (int x ATTRIBUTE_UNUSED)
13080 name = input_line_pointer;
13081 c = get_symbol_end ();
13082 symbolP = symbol_find_or_make (name);
13083 S_SET_EXTERNAL (symbolP);
13085 *input_line_pointer = c;
13086 SKIP_WHITESPACE ();
13088 /* On Irix 5, every global symbol that is not explicitly labelled as
13089 being a function is apparently labelled as being an object. */
13092 if (!is_end_of_line[(unsigned char) *input_line_pointer]
13093 && (*input_line_pointer != ','))
13098 secname = input_line_pointer;
13099 c = get_symbol_end ();
13100 sec = bfd_get_section_by_name (stdoutput, secname);
13102 as_bad (_("%s: no such section"), secname);
13103 *input_line_pointer = c;
13105 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
13106 flag = BSF_FUNCTION;
13109 symbol_get_bfdsym (symbolP)->flags |= flag;
13111 c = *input_line_pointer;
13114 input_line_pointer++;
13115 SKIP_WHITESPACE ();
13116 if (is_end_of_line[(unsigned char) *input_line_pointer])
13122 demand_empty_rest_of_line ();
13126 s_option (int x ATTRIBUTE_UNUSED)
13131 opt = input_line_pointer;
13132 c = get_symbol_end ();
13136 /* FIXME: What does this mean? */
13138 else if (strncmp (opt, "pic", 3) == 0)
13142 i = atoi (opt + 3);
13147 mips_pic = SVR4_PIC;
13148 mips_abicalls = TRUE;
13151 as_bad (_(".option pic%d not supported"), i);
13153 if (mips_pic == SVR4_PIC)
13155 if (g_switch_seen && g_switch_value != 0)
13156 as_warn (_("-G may not be used with SVR4 PIC code"));
13157 g_switch_value = 0;
13158 bfd_set_gp_size (stdoutput, 0);
13162 as_warn (_("Unrecognized option \"%s\""), opt);
13164 *input_line_pointer = c;
13165 demand_empty_rest_of_line ();
13168 /* This structure is used to hold a stack of .set values. */
13170 struct mips_option_stack
13172 struct mips_option_stack *next;
13173 struct mips_set_options options;
13176 static struct mips_option_stack *mips_opts_stack;
13178 /* Handle the .set pseudo-op. */
13181 s_mipsset (int x ATTRIBUTE_UNUSED)
13183 char *name = input_line_pointer, ch;
13185 while (!is_end_of_line[(unsigned char) *input_line_pointer])
13186 ++input_line_pointer;
13187 ch = *input_line_pointer;
13188 *input_line_pointer = '\0';
13190 if (strcmp (name, "reorder") == 0)
13192 if (mips_opts.noreorder)
13195 else if (strcmp (name, "noreorder") == 0)
13197 if (!mips_opts.noreorder)
13198 start_noreorder ();
13200 else if (strncmp (name, "at=", 3) == 0)
13202 char *s = name + 3;
13204 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
13205 as_bad (_("Unrecognized register name `%s'"), s);
13207 else if (strcmp (name, "at") == 0)
13209 mips_opts.at = ATREG;
13211 else if (strcmp (name, "noat") == 0)
13213 mips_opts.at = ZERO;
13215 else if (strcmp (name, "macro") == 0)
13217 mips_opts.warn_about_macros = 0;
13219 else if (strcmp (name, "nomacro") == 0)
13221 if (mips_opts.noreorder == 0)
13222 as_bad (_("`noreorder' must be set before `nomacro'"));
13223 mips_opts.warn_about_macros = 1;
13225 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
13227 mips_opts.nomove = 0;
13229 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
13231 mips_opts.nomove = 1;
13233 else if (strcmp (name, "bopt") == 0)
13235 mips_opts.nobopt = 0;
13237 else if (strcmp (name, "nobopt") == 0)
13239 mips_opts.nobopt = 1;
13241 else if (strcmp (name, "gp=default") == 0)
13242 mips_opts.gp32 = file_mips_gp32;
13243 else if (strcmp (name, "gp=32") == 0)
13244 mips_opts.gp32 = 1;
13245 else if (strcmp (name, "gp=64") == 0)
13247 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
13248 as_warn (_("%s isa does not support 64-bit registers"),
13249 mips_cpu_info_from_isa (mips_opts.isa)->name);
13250 mips_opts.gp32 = 0;
13252 else if (strcmp (name, "fp=default") == 0)
13253 mips_opts.fp32 = file_mips_fp32;
13254 else if (strcmp (name, "fp=32") == 0)
13255 mips_opts.fp32 = 1;
13256 else if (strcmp (name, "fp=64") == 0)
13258 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
13259 as_warn (_("%s isa does not support 64-bit floating point registers"),
13260 mips_cpu_info_from_isa (mips_opts.isa)->name);
13261 mips_opts.fp32 = 0;
13263 else if (strcmp (name, "softfloat") == 0)
13264 mips_opts.soft_float = 1;
13265 else if (strcmp (name, "hardfloat") == 0)
13266 mips_opts.soft_float = 0;
13267 else if (strcmp (name, "singlefloat") == 0)
13268 mips_opts.single_float = 1;
13269 else if (strcmp (name, "doublefloat") == 0)
13270 mips_opts.single_float = 0;
13271 else if (strcmp (name, "mips16") == 0
13272 || strcmp (name, "MIPS-16") == 0)
13273 mips_opts.mips16 = 1;
13274 else if (strcmp (name, "nomips16") == 0
13275 || strcmp (name, "noMIPS-16") == 0)
13276 mips_opts.mips16 = 0;
13277 else if (strcmp (name, "smartmips") == 0)
13279 if (!ISA_SUPPORTS_SMARTMIPS)
13280 as_warn (_("%s ISA does not support SmartMIPS ASE"),
13281 mips_cpu_info_from_isa (mips_opts.isa)->name);
13282 mips_opts.ase_smartmips = 1;
13284 else if (strcmp (name, "nosmartmips") == 0)
13285 mips_opts.ase_smartmips = 0;
13286 else if (strcmp (name, "mips3d") == 0)
13287 mips_opts.ase_mips3d = 1;
13288 else if (strcmp (name, "nomips3d") == 0)
13289 mips_opts.ase_mips3d = 0;
13290 else if (strcmp (name, "mdmx") == 0)
13291 mips_opts.ase_mdmx = 1;
13292 else if (strcmp (name, "nomdmx") == 0)
13293 mips_opts.ase_mdmx = 0;
13294 else if (strcmp (name, "dsp") == 0)
13296 if (!ISA_SUPPORTS_DSP_ASE)
13297 as_warn (_("%s ISA does not support DSP ASE"),
13298 mips_cpu_info_from_isa (mips_opts.isa)->name);
13299 mips_opts.ase_dsp = 1;
13300 mips_opts.ase_dspr2 = 0;
13302 else if (strcmp (name, "nodsp") == 0)
13304 mips_opts.ase_dsp = 0;
13305 mips_opts.ase_dspr2 = 0;
13307 else if (strcmp (name, "dspr2") == 0)
13309 if (!ISA_SUPPORTS_DSPR2_ASE)
13310 as_warn (_("%s ISA does not support DSP R2 ASE"),
13311 mips_cpu_info_from_isa (mips_opts.isa)->name);
13312 mips_opts.ase_dspr2 = 1;
13313 mips_opts.ase_dsp = 1;
13315 else if (strcmp (name, "nodspr2") == 0)
13317 mips_opts.ase_dspr2 = 0;
13318 mips_opts.ase_dsp = 0;
13320 else if (strcmp (name, "mt") == 0)
13322 if (!ISA_SUPPORTS_MT_ASE)
13323 as_warn (_("%s ISA does not support MT ASE"),
13324 mips_cpu_info_from_isa (mips_opts.isa)->name);
13325 mips_opts.ase_mt = 1;
13327 else if (strcmp (name, "nomt") == 0)
13328 mips_opts.ase_mt = 0;
13329 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
13333 /* Permit the user to change the ISA and architecture on the fly.
13334 Needless to say, misuse can cause serious problems. */
13335 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
13338 mips_opts.isa = file_mips_isa;
13339 mips_opts.arch = file_mips_arch;
13341 else if (strncmp (name, "arch=", 5) == 0)
13343 const struct mips_cpu_info *p;
13345 p = mips_parse_cpu("internal use", name + 5);
13347 as_bad (_("unknown architecture %s"), name + 5);
13350 mips_opts.arch = p->cpu;
13351 mips_opts.isa = p->isa;
13354 else if (strncmp (name, "mips", 4) == 0)
13356 const struct mips_cpu_info *p;
13358 p = mips_parse_cpu("internal use", name);
13360 as_bad (_("unknown ISA level %s"), name + 4);
13363 mips_opts.arch = p->cpu;
13364 mips_opts.isa = p->isa;
13368 as_bad (_("unknown ISA or architecture %s"), name);
13370 switch (mips_opts.isa)
13378 mips_opts.gp32 = 1;
13379 mips_opts.fp32 = 1;
13386 mips_opts.gp32 = 0;
13387 mips_opts.fp32 = 0;
13390 as_bad (_("unknown ISA level %s"), name + 4);
13395 mips_opts.gp32 = file_mips_gp32;
13396 mips_opts.fp32 = file_mips_fp32;
13399 else if (strcmp (name, "autoextend") == 0)
13400 mips_opts.noautoextend = 0;
13401 else if (strcmp (name, "noautoextend") == 0)
13402 mips_opts.noautoextend = 1;
13403 else if (strcmp (name, "push") == 0)
13405 struct mips_option_stack *s;
13407 s = (struct mips_option_stack *) xmalloc (sizeof *s);
13408 s->next = mips_opts_stack;
13409 s->options = mips_opts;
13410 mips_opts_stack = s;
13412 else if (strcmp (name, "pop") == 0)
13414 struct mips_option_stack *s;
13416 s = mips_opts_stack;
13418 as_bad (_(".set pop with no .set push"));
13421 /* If we're changing the reorder mode we need to handle
13422 delay slots correctly. */
13423 if (s->options.noreorder && ! mips_opts.noreorder)
13424 start_noreorder ();
13425 else if (! s->options.noreorder && mips_opts.noreorder)
13428 mips_opts = s->options;
13429 mips_opts_stack = s->next;
13433 else if (strcmp (name, "sym32") == 0)
13434 mips_opts.sym32 = TRUE;
13435 else if (strcmp (name, "nosym32") == 0)
13436 mips_opts.sym32 = FALSE;
13437 else if (strchr (name, ','))
13439 /* Generic ".set" directive; use the generic handler. */
13440 *input_line_pointer = ch;
13441 input_line_pointer = name;
13447 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
13449 *input_line_pointer = ch;
13450 demand_empty_rest_of_line ();
13453 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
13454 .option pic2. It means to generate SVR4 PIC calls. */
13457 s_abicalls (int ignore ATTRIBUTE_UNUSED)
13459 mips_pic = SVR4_PIC;
13460 mips_abicalls = TRUE;
13462 if (g_switch_seen && g_switch_value != 0)
13463 as_warn (_("-G may not be used with SVR4 PIC code"));
13464 g_switch_value = 0;
13466 bfd_set_gp_size (stdoutput, 0);
13467 demand_empty_rest_of_line ();
13470 /* Handle the .cpload pseudo-op. This is used when generating SVR4
13471 PIC code. It sets the $gp register for the function based on the
13472 function address, which is in the register named in the argument.
13473 This uses a relocation against _gp_disp, which is handled specially
13474 by the linker. The result is:
13475 lui $gp,%hi(_gp_disp)
13476 addiu $gp,$gp,%lo(_gp_disp)
13477 addu $gp,$gp,.cpload argument
13478 The .cpload argument is normally $25 == $t9.
13480 The -mno-shared option changes this to:
13481 lui $gp,%hi(__gnu_local_gp)
13482 addiu $gp,$gp,%lo(__gnu_local_gp)
13483 and the argument is ignored. This saves an instruction, but the
13484 resulting code is not position independent; it uses an absolute
13485 address for __gnu_local_gp. Thus code assembled with -mno-shared
13486 can go into an ordinary executable, but not into a shared library. */
13489 s_cpload (int ignore ATTRIBUTE_UNUSED)
13495 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13496 .cpload is ignored. */
13497 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
13503 /* .cpload should be in a .set noreorder section. */
13504 if (mips_opts.noreorder == 0)
13505 as_warn (_(".cpload not in noreorder section"));
13507 reg = tc_get_register (0);
13509 /* If we need to produce a 64-bit address, we are better off using
13510 the default instruction sequence. */
13511 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
13513 ex.X_op = O_symbol;
13514 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
13516 ex.X_op_symbol = NULL;
13517 ex.X_add_number = 0;
13519 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13520 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
13523 macro_build_lui (&ex, mips_gp_register);
13524 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
13525 mips_gp_register, BFD_RELOC_LO16);
13527 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
13528 mips_gp_register, reg);
13531 demand_empty_rest_of_line ();
13534 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
13535 .cpsetup $reg1, offset|$reg2, label
13537 If offset is given, this results in:
13538 sd $gp, offset($sp)
13539 lui $gp, %hi(%neg(%gp_rel(label)))
13540 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13541 daddu $gp, $gp, $reg1
13543 If $reg2 is given, this results in:
13544 daddu $reg2, $gp, $0
13545 lui $gp, %hi(%neg(%gp_rel(label)))
13546 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13547 daddu $gp, $gp, $reg1
13548 $reg1 is normally $25 == $t9.
13550 The -mno-shared option replaces the last three instructions with
13552 addiu $gp,$gp,%lo(_gp) */
13555 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
13557 expressionS ex_off;
13558 expressionS ex_sym;
13561 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
13562 We also need NewABI support. */
13563 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13569 reg1 = tc_get_register (0);
13570 SKIP_WHITESPACE ();
13571 if (*input_line_pointer != ',')
13573 as_bad (_("missing argument separator ',' for .cpsetup"));
13577 ++input_line_pointer;
13578 SKIP_WHITESPACE ();
13579 if (*input_line_pointer == '$')
13581 mips_cpreturn_register = tc_get_register (0);
13582 mips_cpreturn_offset = -1;
13586 mips_cpreturn_offset = get_absolute_expression ();
13587 mips_cpreturn_register = -1;
13589 SKIP_WHITESPACE ();
13590 if (*input_line_pointer != ',')
13592 as_bad (_("missing argument separator ',' for .cpsetup"));
13596 ++input_line_pointer;
13597 SKIP_WHITESPACE ();
13598 expression (&ex_sym);
13601 if (mips_cpreturn_register == -1)
13603 ex_off.X_op = O_constant;
13604 ex_off.X_add_symbol = NULL;
13605 ex_off.X_op_symbol = NULL;
13606 ex_off.X_add_number = mips_cpreturn_offset;
13608 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
13609 BFD_RELOC_LO16, SP);
13612 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
13613 mips_gp_register, 0);
13615 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
13617 macro_build (&ex_sym, "lui", "t,u", mips_gp_register,
13618 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
13621 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
13622 mips_gp_register, -1, BFD_RELOC_GPREL16,
13623 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
13625 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
13626 mips_gp_register, reg1);
13632 ex.X_op = O_symbol;
13633 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
13634 ex.X_op_symbol = NULL;
13635 ex.X_add_number = 0;
13637 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13638 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
13640 macro_build_lui (&ex, mips_gp_register);
13641 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
13642 mips_gp_register, BFD_RELOC_LO16);
13647 demand_empty_rest_of_line ();
13651 s_cplocal (int ignore ATTRIBUTE_UNUSED)
13653 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
13654 .cplocal is ignored. */
13655 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13661 mips_gp_register = tc_get_register (0);
13662 demand_empty_rest_of_line ();
13665 /* Handle the .cprestore pseudo-op. This stores $gp into a given
13666 offset from $sp. The offset is remembered, and after making a PIC
13667 call $gp is restored from that location. */
13670 s_cprestore (int ignore ATTRIBUTE_UNUSED)
13674 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13675 .cprestore is ignored. */
13676 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
13682 mips_cprestore_offset = get_absolute_expression ();
13683 mips_cprestore_valid = 1;
13685 ex.X_op = O_constant;
13686 ex.X_add_symbol = NULL;
13687 ex.X_op_symbol = NULL;
13688 ex.X_add_number = mips_cprestore_offset;
13691 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
13692 SP, HAVE_64BIT_ADDRESSES);
13695 demand_empty_rest_of_line ();
13698 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
13699 was given in the preceding .cpsetup, it results in:
13700 ld $gp, offset($sp)
13702 If a register $reg2 was given there, it results in:
13703 daddu $gp, $reg2, $0 */
13706 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
13710 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
13711 We also need NewABI support. */
13712 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13719 if (mips_cpreturn_register == -1)
13721 ex.X_op = O_constant;
13722 ex.X_add_symbol = NULL;
13723 ex.X_op_symbol = NULL;
13724 ex.X_add_number = mips_cpreturn_offset;
13726 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
13729 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
13730 mips_cpreturn_register, 0);
13733 demand_empty_rest_of_line ();
13736 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
13737 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
13738 use in DWARF debug information. */
13741 s_dtprel_internal (size_t bytes)
13748 if (ex.X_op != O_symbol)
13750 as_bad (_("Unsupported use of %s"), (bytes == 8
13753 ignore_rest_of_line ();
13756 p = frag_more (bytes);
13757 md_number_to_chars (p, 0, bytes);
13758 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
13760 ? BFD_RELOC_MIPS_TLS_DTPREL64
13761 : BFD_RELOC_MIPS_TLS_DTPREL32));
13763 demand_empty_rest_of_line ();
13766 /* Handle .dtprelword. */
13769 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
13771 s_dtprel_internal (4);
13774 /* Handle .dtpreldword. */
13777 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
13779 s_dtprel_internal (8);
13782 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
13783 code. It sets the offset to use in gp_rel relocations. */
13786 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
13788 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
13789 We also need NewABI support. */
13790 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13796 mips_gprel_offset = get_absolute_expression ();
13798 demand_empty_rest_of_line ();
13801 /* Handle the .gpword pseudo-op. This is used when generating PIC
13802 code. It generates a 32 bit GP relative reloc. */
13805 s_gpword (int ignore ATTRIBUTE_UNUSED)
13807 segment_info_type *si;
13808 struct insn_label_list *l;
13813 /* When not generating PIC code, this is treated as .word. */
13814 if (mips_pic != SVR4_PIC)
13820 si = seg_info (now_seg);
13821 l = si->label_list;
13822 label = l != NULL ? l->label : NULL;
13823 mips_emit_delays ();
13825 mips_align (2, 0, label);
13828 mips_clear_insn_labels ();
13830 if (ex.X_op != O_symbol || ex.X_add_number != 0)
13832 as_bad (_("Unsupported use of .gpword"));
13833 ignore_rest_of_line ();
13837 md_number_to_chars (p, 0, 4);
13838 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
13839 BFD_RELOC_GPREL32);
13841 demand_empty_rest_of_line ();
13845 s_gpdword (int ignore ATTRIBUTE_UNUSED)
13847 segment_info_type *si;
13848 struct insn_label_list *l;
13853 /* When not generating PIC code, this is treated as .dword. */
13854 if (mips_pic != SVR4_PIC)
13860 si = seg_info (now_seg);
13861 l = si->label_list;
13862 label = l != NULL ? l->label : NULL;
13863 mips_emit_delays ();
13865 mips_align (3, 0, label);
13868 mips_clear_insn_labels ();
13870 if (ex.X_op != O_symbol || ex.X_add_number != 0)
13872 as_bad (_("Unsupported use of .gpdword"));
13873 ignore_rest_of_line ();
13877 md_number_to_chars (p, 0, 8);
13878 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
13879 BFD_RELOC_GPREL32)->fx_tcbit = 1;
13881 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
13882 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
13883 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
13885 demand_empty_rest_of_line ();
13888 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
13889 tables in SVR4 PIC code. */
13892 s_cpadd (int ignore ATTRIBUTE_UNUSED)
13896 /* This is ignored when not generating SVR4 PIC code. */
13897 if (mips_pic != SVR4_PIC)
13903 /* Add $gp to the register named as an argument. */
13905 reg = tc_get_register (0);
13906 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
13909 demand_empty_rest_of_line ();
13912 /* Handle the .insn pseudo-op. This marks instruction labels in
13913 mips16 mode. This permits the linker to handle them specially,
13914 such as generating jalx instructions when needed. We also make
13915 them odd for the duration of the assembly, in order to generate the
13916 right sort of code. We will make them even in the adjust_symtab
13917 routine, while leaving them marked. This is convenient for the
13918 debugger and the disassembler. The linker knows to make them odd
13922 s_insn (int ignore ATTRIBUTE_UNUSED)
13924 mips16_mark_labels ();
13926 demand_empty_rest_of_line ();
13929 /* Handle a .stabn directive. We need these in order to mark a label
13930 as being a mips16 text label correctly. Sometimes the compiler
13931 will emit a label, followed by a .stabn, and then switch sections.
13932 If the label and .stabn are in mips16 mode, then the label is
13933 really a mips16 text label. */
13936 s_mips_stab (int type)
13939 mips16_mark_labels ();
13944 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
13947 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
13954 name = input_line_pointer;
13955 c = get_symbol_end ();
13956 symbolP = symbol_find_or_make (name);
13957 S_SET_WEAK (symbolP);
13958 *input_line_pointer = c;
13960 SKIP_WHITESPACE ();
13962 if (! is_end_of_line[(unsigned char) *input_line_pointer])
13964 if (S_IS_DEFINED (symbolP))
13966 as_bad (_("ignoring attempt to redefine symbol %s"),
13967 S_GET_NAME (symbolP));
13968 ignore_rest_of_line ();
13972 if (*input_line_pointer == ',')
13974 ++input_line_pointer;
13975 SKIP_WHITESPACE ();
13979 if (exp.X_op != O_symbol)
13981 as_bad (_("bad .weakext directive"));
13982 ignore_rest_of_line ();
13985 symbol_set_value_expression (symbolP, &exp);
13988 demand_empty_rest_of_line ();
13991 /* Parse a register string into a number. Called from the ECOFF code
13992 to parse .frame. The argument is non-zero if this is the frame
13993 register, so that we can record it in mips_frame_reg. */
13996 tc_get_register (int frame)
14000 SKIP_WHITESPACE ();
14001 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
14005 mips_frame_reg = reg != 0 ? reg : SP;
14006 mips_frame_reg_valid = 1;
14007 mips_cprestore_valid = 0;
14013 md_section_align (asection *seg, valueT addr)
14015 int align = bfd_get_section_alignment (stdoutput, seg);
14019 /* We don't need to align ELF sections to the full alignment.
14020 However, Irix 5 may prefer that we align them at least to a 16
14021 byte boundary. We don't bother to align the sections if we
14022 are targeted for an embedded system. */
14023 if (strncmp (TARGET_OS, "elf", 3) == 0)
14029 return ((addr + (1 << align) - 1) & (-1 << align));
14032 /* Utility routine, called from above as well. If called while the
14033 input file is still being read, it's only an approximation. (For
14034 example, a symbol may later become defined which appeared to be
14035 undefined earlier.) */
14038 nopic_need_relax (symbolS *sym, int before_relaxing)
14043 if (g_switch_value > 0)
14045 const char *symname;
14048 /* Find out whether this symbol can be referenced off the $gp
14049 register. It can be if it is smaller than the -G size or if
14050 it is in the .sdata or .sbss section. Certain symbols can
14051 not be referenced off the $gp, although it appears as though
14053 symname = S_GET_NAME (sym);
14054 if (symname != (const char *) NULL
14055 && (strcmp (symname, "eprol") == 0
14056 || strcmp (symname, "etext") == 0
14057 || strcmp (symname, "_gp") == 0
14058 || strcmp (symname, "edata") == 0
14059 || strcmp (symname, "_fbss") == 0
14060 || strcmp (symname, "_fdata") == 0
14061 || strcmp (symname, "_ftext") == 0
14062 || strcmp (symname, "end") == 0
14063 || strcmp (symname, "_gp_disp") == 0))
14065 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
14067 #ifndef NO_ECOFF_DEBUGGING
14068 || (symbol_get_obj (sym)->ecoff_extern_size != 0
14069 && (symbol_get_obj (sym)->ecoff_extern_size
14070 <= g_switch_value))
14072 /* We must defer this decision until after the whole
14073 file has been read, since there might be a .extern
14074 after the first use of this symbol. */
14075 || (before_relaxing
14076 #ifndef NO_ECOFF_DEBUGGING
14077 && symbol_get_obj (sym)->ecoff_extern_size == 0
14079 && S_GET_VALUE (sym) == 0)
14080 || (S_GET_VALUE (sym) != 0
14081 && S_GET_VALUE (sym) <= g_switch_value)))
14085 const char *segname;
14087 segname = segment_name (S_GET_SEGMENT (sym));
14088 gas_assert (strcmp (segname, ".lit8") != 0
14089 && strcmp (segname, ".lit4") != 0);
14090 change = (strcmp (segname, ".sdata") != 0
14091 && strcmp (segname, ".sbss") != 0
14092 && strncmp (segname, ".sdata.", 7) != 0
14093 && strncmp (segname, ".sbss.", 6) != 0
14094 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
14095 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
14100 /* We are not optimizing for the $gp register. */
14105 /* Return true if the given symbol should be considered local for SVR4 PIC. */
14108 pic_need_relax (symbolS *sym, asection *segtype)
14112 /* Handle the case of a symbol equated to another symbol. */
14113 while (symbol_equated_reloc_p (sym))
14117 /* It's possible to get a loop here in a badly written program. */
14118 n = symbol_get_value_expression (sym)->X_add_symbol;
14124 if (symbol_section_p (sym))
14127 symsec = S_GET_SEGMENT (sym);
14129 /* This must duplicate the test in adjust_reloc_syms. */
14130 return (symsec != &bfd_und_section
14131 && symsec != &bfd_abs_section
14132 && !bfd_is_com_section (symsec)
14133 && !s_is_linkonce (sym, segtype)
14135 /* A global or weak symbol is treated as external. */
14136 && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
14142 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
14143 extended opcode. SEC is the section the frag is in. */
14146 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
14149 const struct mips16_immed_operand *op;
14151 int mintiny, maxtiny;
14155 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
14157 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
14160 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
14161 op = mips16_immed_operands;
14162 while (op->type != type)
14165 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
14170 if (type == '<' || type == '>' || type == '[' || type == ']')
14173 maxtiny = 1 << op->nbits;
14178 maxtiny = (1 << op->nbits) - 1;
14183 mintiny = - (1 << (op->nbits - 1));
14184 maxtiny = (1 << (op->nbits - 1)) - 1;
14187 sym_frag = symbol_get_frag (fragp->fr_symbol);
14188 val = S_GET_VALUE (fragp->fr_symbol);
14189 symsec = S_GET_SEGMENT (fragp->fr_symbol);
14195 /* We won't have the section when we are called from
14196 mips_relax_frag. However, we will always have been called
14197 from md_estimate_size_before_relax first. If this is a
14198 branch to a different section, we mark it as such. If SEC is
14199 NULL, and the frag is not marked, then it must be a branch to
14200 the same section. */
14203 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
14208 /* Must have been called from md_estimate_size_before_relax. */
14211 fragp->fr_subtype =
14212 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14214 /* FIXME: We should support this, and let the linker
14215 catch branches and loads that are out of range. */
14216 as_bad_where (fragp->fr_file, fragp->fr_line,
14217 _("unsupported PC relative reference to different section"));
14221 if (fragp != sym_frag && sym_frag->fr_address == 0)
14222 /* Assume non-extended on the first relaxation pass.
14223 The address we have calculated will be bogus if this is
14224 a forward branch to another frag, as the forward frag
14225 will have fr_address == 0. */
14229 /* In this case, we know for sure that the symbol fragment is in
14230 the same section. If the relax_marker of the symbol fragment
14231 differs from the relax_marker of this fragment, we have not
14232 yet adjusted the symbol fragment fr_address. We want to add
14233 in STRETCH in order to get a better estimate of the address.
14234 This particularly matters because of the shift bits. */
14236 && sym_frag->relax_marker != fragp->relax_marker)
14240 /* Adjust stretch for any alignment frag. Note that if have
14241 been expanding the earlier code, the symbol may be
14242 defined in what appears to be an earlier frag. FIXME:
14243 This doesn't handle the fr_subtype field, which specifies
14244 a maximum number of bytes to skip when doing an
14246 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
14248 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
14251 stretch = - ((- stretch)
14252 & ~ ((1 << (int) f->fr_offset) - 1));
14254 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
14263 addr = fragp->fr_address + fragp->fr_fix;
14265 /* The base address rules are complicated. The base address of
14266 a branch is the following instruction. The base address of a
14267 PC relative load or add is the instruction itself, but if it
14268 is in a delay slot (in which case it can not be extended) use
14269 the address of the instruction whose delay slot it is in. */
14270 if (type == 'p' || type == 'q')
14274 /* If we are currently assuming that this frag should be
14275 extended, then, the current address is two bytes
14277 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14280 /* Ignore the low bit in the target, since it will be set
14281 for a text label. */
14282 if ((val & 1) != 0)
14285 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
14287 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
14290 val -= addr & ~ ((1 << op->shift) - 1);
14292 /* Branch offsets have an implicit 0 in the lowest bit. */
14293 if (type == 'p' || type == 'q')
14296 /* If any of the shifted bits are set, we must use an extended
14297 opcode. If the address depends on the size of this
14298 instruction, this can lead to a loop, so we arrange to always
14299 use an extended opcode. We only check this when we are in
14300 the main relaxation loop, when SEC is NULL. */
14301 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
14303 fragp->fr_subtype =
14304 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14308 /* If we are about to mark a frag as extended because the value
14309 is precisely maxtiny + 1, then there is a chance of an
14310 infinite loop as in the following code:
14315 In this case when the la is extended, foo is 0x3fc bytes
14316 away, so the la can be shrunk, but then foo is 0x400 away, so
14317 the la must be extended. To avoid this loop, we mark the
14318 frag as extended if it was small, and is about to become
14319 extended with a value of maxtiny + 1. */
14320 if (val == ((maxtiny + 1) << op->shift)
14321 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
14324 fragp->fr_subtype =
14325 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14329 else if (symsec != absolute_section && sec != NULL)
14330 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
14332 if ((val & ((1 << op->shift) - 1)) != 0
14333 || val < (mintiny << op->shift)
14334 || val > (maxtiny << op->shift))
14340 /* Compute the length of a branch sequence, and adjust the
14341 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
14342 worst-case length is computed, with UPDATE being used to indicate
14343 whether an unconditional (-1), branch-likely (+1) or regular (0)
14344 branch is to be computed. */
14346 relaxed_branch_length (fragS *fragp, asection *sec, int update)
14348 bfd_boolean toofar;
14352 && S_IS_DEFINED (fragp->fr_symbol)
14353 && sec == S_GET_SEGMENT (fragp->fr_symbol))
14358 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
14360 addr = fragp->fr_address + fragp->fr_fix + 4;
14364 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
14367 /* If the symbol is not defined or it's in a different segment,
14368 assume the user knows what's going on and emit a short
14374 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
14376 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
14377 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
14378 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
14379 RELAX_BRANCH_LINK (fragp->fr_subtype),
14385 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
14388 if (mips_pic != NO_PIC)
14390 /* Additional space for PIC loading of target address. */
14392 if (mips_opts.isa == ISA_MIPS1)
14393 /* Additional space for $at-stabilizing nop. */
14397 /* If branch is conditional. */
14398 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
14405 /* Estimate the size of a frag before relaxing. Unless this is the
14406 mips16, we are not really relaxing here, and the final size is
14407 encoded in the subtype information. For the mips16, we have to
14408 decide whether we are using an extended opcode or not. */
14411 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
14415 if (RELAX_BRANCH_P (fragp->fr_subtype))
14418 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
14420 return fragp->fr_var;
14423 if (RELAX_MIPS16_P (fragp->fr_subtype))
14424 /* We don't want to modify the EXTENDED bit here; it might get us
14425 into infinite loops. We change it only in mips_relax_frag(). */
14426 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
14428 if (mips_pic == NO_PIC)
14429 change = nopic_need_relax (fragp->fr_symbol, 0);
14430 else if (mips_pic == SVR4_PIC)
14431 change = pic_need_relax (fragp->fr_symbol, segtype);
14432 else if (mips_pic == VXWORKS_PIC)
14433 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
14440 fragp->fr_subtype |= RELAX_USE_SECOND;
14441 return -RELAX_FIRST (fragp->fr_subtype);
14444 return -RELAX_SECOND (fragp->fr_subtype);
14447 /* This is called to see whether a reloc against a defined symbol
14448 should be converted into a reloc against a section. */
14451 mips_fix_adjustable (fixS *fixp)
14453 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
14454 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
14457 if (fixp->fx_addsy == NULL)
14460 /* If symbol SYM is in a mergeable section, relocations of the form
14461 SYM + 0 can usually be made section-relative. The mergeable data
14462 is then identified by the section offset rather than by the symbol.
14464 However, if we're generating REL LO16 relocations, the offset is split
14465 between the LO16 and parterning high part relocation. The linker will
14466 need to recalculate the complete offset in order to correctly identify
14469 The linker has traditionally not looked for the parterning high part
14470 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
14471 placed anywhere. Rather than break backwards compatibility by changing
14472 this, it seems better not to force the issue, and instead keep the
14473 original symbol. This will work with either linker behavior. */
14474 if ((lo16_reloc_p (fixp->fx_r_type)
14475 || reloc_needs_lo_p (fixp->fx_r_type))
14476 && HAVE_IN_PLACE_ADDENDS
14477 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
14480 /* There is no place to store an in-place offset for JALR relocations.
14481 Likewise an in-range offset of PC-relative relocations may overflow
14482 the in-place relocatable field if recalculated against the start
14483 address of the symbol's containing section. */
14484 if (HAVE_IN_PLACE_ADDENDS
14485 && (fixp->fx_pcrel || fixp->fx_r_type == BFD_RELOC_MIPS_JALR))
14489 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
14490 to a floating-point stub. The same is true for non-R_MIPS16_26
14491 relocations against MIPS16 functions; in this case, the stub becomes
14492 the function's canonical address.
14494 Floating-point stubs are stored in unique .mips16.call.* or
14495 .mips16.fn.* sections. If a stub T for function F is in section S,
14496 the first relocation in section S must be against F; this is how the
14497 linker determines the target function. All relocations that might
14498 resolve to T must also be against F. We therefore have the following
14499 restrictions, which are given in an intentionally-redundant way:
14501 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
14504 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
14505 if that stub might be used.
14507 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
14510 4. We cannot reduce a stub's relocations against MIPS16 symbols if
14511 that stub might be used.
14513 There is a further restriction:
14515 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols
14516 on targets with in-place addends; the relocation field cannot
14517 encode the low bit.
14519 For simplicity, we deal with (3)-(5) by not reducing _any_ relocation
14520 against a MIPS16 symbol.
14522 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
14523 relocation against some symbol R, no relocation against R may be
14524 reduced. (Note that this deals with (2) as well as (1) because
14525 relocations against global symbols will never be reduced on ELF
14526 targets.) This approach is a little simpler than trying to detect
14527 stub sections, and gives the "all or nothing" per-symbol consistency
14528 that we have for MIPS16 symbols. */
14530 && fixp->fx_subsy == NULL
14531 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
14532 || *symbol_get_tc (fixp->fx_addsy)))
14539 /* Translate internal representation of relocation info to BFD target
14543 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
14545 static arelent *retval[4];
14547 bfd_reloc_code_real_type code;
14549 memset (retval, 0, sizeof(retval));
14550 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
14551 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
14552 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
14553 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
14555 if (fixp->fx_pcrel)
14557 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2);
14559 /* At this point, fx_addnumber is "symbol offset - pcrel address".
14560 Relocations want only the symbol offset. */
14561 reloc->addend = fixp->fx_addnumber + reloc->address;
14564 /* A gruesome hack which is a result of the gruesome gas
14565 reloc handling. What's worse, for COFF (as opposed to
14566 ECOFF), we might need yet another copy of reloc->address.
14567 See bfd_install_relocation. */
14568 reloc->addend += reloc->address;
14572 reloc->addend = fixp->fx_addnumber;
14574 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
14575 entry to be used in the relocation's section offset. */
14576 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
14578 reloc->address = reloc->addend;
14582 code = fixp->fx_r_type;
14584 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
14585 if (reloc->howto == NULL)
14587 as_bad_where (fixp->fx_file, fixp->fx_line,
14588 _("Can not represent %s relocation in this object file format"),
14589 bfd_get_reloc_code_name (code));
14596 /* Relax a machine dependent frag. This returns the amount by which
14597 the current size of the frag should change. */
14600 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
14602 if (RELAX_BRANCH_P (fragp->fr_subtype))
14604 offsetT old_var = fragp->fr_var;
14606 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
14608 return fragp->fr_var - old_var;
14611 if (! RELAX_MIPS16_P (fragp->fr_subtype))
14614 if (mips16_extended_frag (fragp, NULL, stretch))
14616 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14618 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
14623 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14625 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
14632 /* Convert a machine dependent frag. */
14635 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
14637 if (RELAX_BRANCH_P (fragp->fr_subtype))
14640 unsigned long insn;
14644 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
14646 if (target_big_endian)
14647 insn = bfd_getb32 (buf);
14649 insn = bfd_getl32 (buf);
14651 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
14653 /* We generate a fixup instead of applying it right now
14654 because, if there are linker relaxations, we're going to
14655 need the relocations. */
14656 exp.X_op = O_symbol;
14657 exp.X_add_symbol = fragp->fr_symbol;
14658 exp.X_add_number = fragp->fr_offset;
14660 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14661 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2);
14662 fixp->fx_file = fragp->fr_file;
14663 fixp->fx_line = fragp->fr_line;
14665 md_number_to_chars ((char *) buf, insn, 4);
14672 as_warn_where (fragp->fr_file, fragp->fr_line,
14673 _("Relaxed out-of-range branch into a jump"));
14675 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
14678 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14680 /* Reverse the branch. */
14681 switch ((insn >> 28) & 0xf)
14684 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
14685 have the condition reversed by tweaking a single
14686 bit, and their opcodes all have 0x4???????. */
14687 gas_assert ((insn & 0xf1000000) == 0x41000000);
14688 insn ^= 0x00010000;
14692 /* bltz 0x04000000 bgez 0x04010000
14693 bltzal 0x04100000 bgezal 0x04110000 */
14694 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
14695 insn ^= 0x00010000;
14699 /* beq 0x10000000 bne 0x14000000
14700 blez 0x18000000 bgtz 0x1c000000 */
14701 insn ^= 0x04000000;
14709 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
14711 /* Clear the and-link bit. */
14712 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
14714 /* bltzal 0x04100000 bgezal 0x04110000
14715 bltzall 0x04120000 bgezall 0x04130000 */
14716 insn &= ~0x00100000;
14719 /* Branch over the branch (if the branch was likely) or the
14720 full jump (not likely case). Compute the offset from the
14721 current instruction to branch to. */
14722 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14726 /* How many bytes in instructions we've already emitted? */
14727 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
14728 /* How many bytes in instructions from here to the end? */
14729 i = fragp->fr_var - i;
14731 /* Convert to instruction count. */
14733 /* Branch counts from the next instruction. */
14736 /* Branch over the jump. */
14737 md_number_to_chars ((char *) buf, insn, 4);
14741 md_number_to_chars ((char *) buf, 0, 4);
14744 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14746 /* beql $0, $0, 2f */
14748 /* Compute the PC offset from the current instruction to
14749 the end of the variable frag. */
14750 /* How many bytes in instructions we've already emitted? */
14751 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
14752 /* How many bytes in instructions from here to the end? */
14753 i = fragp->fr_var - i;
14754 /* Convert to instruction count. */
14756 /* Don't decrement i, because we want to branch over the
14760 md_number_to_chars ((char *) buf, insn, 4);
14763 md_number_to_chars ((char *) buf, 0, 4);
14768 if (mips_pic == NO_PIC)
14771 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
14772 ? 0x0c000000 : 0x08000000);
14773 exp.X_op = O_symbol;
14774 exp.X_add_symbol = fragp->fr_symbol;
14775 exp.X_add_number = fragp->fr_offset;
14777 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14778 4, &exp, FALSE, BFD_RELOC_MIPS_JMP);
14779 fixp->fx_file = fragp->fr_file;
14780 fixp->fx_line = fragp->fr_line;
14782 md_number_to_chars ((char *) buf, insn, 4);
14787 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
14789 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
14790 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
14791 insn |= at << OP_SH_RT;
14792 exp.X_op = O_symbol;
14793 exp.X_add_symbol = fragp->fr_symbol;
14794 exp.X_add_number = fragp->fr_offset;
14796 if (fragp->fr_offset)
14798 exp.X_add_symbol = make_expr_symbol (&exp);
14799 exp.X_add_number = 0;
14802 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14803 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16);
14804 fixp->fx_file = fragp->fr_file;
14805 fixp->fx_line = fragp->fr_line;
14807 md_number_to_chars ((char *) buf, insn, 4);
14810 if (mips_opts.isa == ISA_MIPS1)
14813 md_number_to_chars ((char *) buf, 0, 4);
14817 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
14818 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
14819 insn |= at << OP_SH_RS | at << OP_SH_RT;
14821 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14822 4, &exp, FALSE, BFD_RELOC_LO16);
14823 fixp->fx_file = fragp->fr_file;
14824 fixp->fx_line = fragp->fr_line;
14826 md_number_to_chars ((char *) buf, insn, 4);
14830 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
14834 insn |= at << OP_SH_RS;
14836 md_number_to_chars ((char *) buf, insn, 4);
14841 gas_assert (buf == (bfd_byte *)fragp->fr_literal
14842 + fragp->fr_fix + fragp->fr_var);
14844 fragp->fr_fix += fragp->fr_var;
14849 if (RELAX_MIPS16_P (fragp->fr_subtype))
14852 const struct mips16_immed_operand *op;
14853 bfd_boolean small, ext;
14856 unsigned long insn;
14857 bfd_boolean use_extend;
14858 unsigned short extend;
14860 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
14861 op = mips16_immed_operands;
14862 while (op->type != type)
14865 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14876 val = resolve_symbol_value (fragp->fr_symbol);
14881 addr = fragp->fr_address + fragp->fr_fix;
14883 /* The rules for the base address of a PC relative reloc are
14884 complicated; see mips16_extended_frag. */
14885 if (type == 'p' || type == 'q')
14890 /* Ignore the low bit in the target, since it will be
14891 set for a text label. */
14892 if ((val & 1) != 0)
14895 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
14897 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
14900 addr &= ~ (addressT) ((1 << op->shift) - 1);
14903 /* Make sure the section winds up with the alignment we have
14906 record_alignment (asec, op->shift);
14910 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
14911 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
14912 as_warn_where (fragp->fr_file, fragp->fr_line,
14913 _("extended instruction in delay slot"));
14915 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
14917 if (target_big_endian)
14918 insn = bfd_getb16 (buf);
14920 insn = bfd_getl16 (buf);
14922 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
14923 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
14924 small, ext, &insn, &use_extend, &extend);
14928 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
14929 fragp->fr_fix += 2;
14933 md_number_to_chars ((char *) buf, insn, 2);
14934 fragp->fr_fix += 2;
14942 first = RELAX_FIRST (fragp->fr_subtype);
14943 second = RELAX_SECOND (fragp->fr_subtype);
14944 fixp = (fixS *) fragp->fr_opcode;
14946 /* Possibly emit a warning if we've chosen the longer option. */
14947 if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0)
14948 == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0))
14950 const char *msg = macro_warning (fragp->fr_subtype);
14952 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
14955 /* Go through all the fixups for the first sequence. Disable them
14956 (by marking them as done) if we're going to use the second
14957 sequence instead. */
14959 && fixp->fx_frag == fragp
14960 && fixp->fx_where < fragp->fr_fix - second)
14962 if (fragp->fr_subtype & RELAX_USE_SECOND)
14964 fixp = fixp->fx_next;
14967 /* Go through the fixups for the second sequence. Disable them if
14968 we're going to use the first sequence, otherwise adjust their
14969 addresses to account for the relaxation. */
14970 while (fixp && fixp->fx_frag == fragp)
14972 if (fragp->fr_subtype & RELAX_USE_SECOND)
14973 fixp->fx_where -= first;
14976 fixp = fixp->fx_next;
14979 /* Now modify the frag contents. */
14980 if (fragp->fr_subtype & RELAX_USE_SECOND)
14984 start = fragp->fr_literal + fragp->fr_fix - first - second;
14985 memmove (start, start + first, second);
14986 fragp->fr_fix -= first;
14989 fragp->fr_fix -= second;
14995 /* This function is called after the relocs have been generated.
14996 We've been storing mips16 text labels as odd. Here we convert them
14997 back to even for the convenience of the debugger. */
15000 mips_frob_file_after_relocs (void)
15003 unsigned int count, i;
15008 syms = bfd_get_outsymbols (stdoutput);
15009 count = bfd_get_symcount (stdoutput);
15010 for (i = 0; i < count; i++, syms++)
15012 if (ELF_ST_IS_MIPS16 (elf_symbol (*syms)->internal_elf_sym.st_other)
15013 && ((*syms)->value & 1) != 0)
15015 (*syms)->value &= ~1;
15016 /* If the symbol has an odd size, it was probably computed
15017 incorrectly, so adjust that as well. */
15018 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
15019 ++elf_symbol (*syms)->internal_elf_sym.st_size;
15026 /* This function is called whenever a label is defined, including fake
15027 labels instantiated off the dot special symbol. It is used when
15028 handling branch delays; if a branch has a label, we assume we cannot
15029 move it. This also bumps the value of the symbol by 1 in compressed
15033 mips_record_label (symbolS *sym)
15035 segment_info_type *si = seg_info (now_seg);
15036 struct insn_label_list *l;
15038 if (free_insn_labels == NULL)
15039 l = (struct insn_label_list *) xmalloc (sizeof *l);
15042 l = free_insn_labels;
15043 free_insn_labels = l->next;
15047 l->next = si->label_list;
15048 si->label_list = l;
15051 /* This function is called as tc_frob_label() whenever a label is defined
15052 and adds a DWARF-2 record we only want for true labels. */
15055 mips_define_label (symbolS *sym)
15057 mips_record_label (sym);
15059 dwarf2_emit_label (sym);
15063 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15065 /* Some special processing for a MIPS ELF file. */
15068 mips_elf_final_processing (void)
15070 /* Write out the register information. */
15071 if (mips_abi != N64_ABI)
15075 s.ri_gprmask = mips_gprmask;
15076 s.ri_cprmask[0] = mips_cprmask[0];
15077 s.ri_cprmask[1] = mips_cprmask[1];
15078 s.ri_cprmask[2] = mips_cprmask[2];
15079 s.ri_cprmask[3] = mips_cprmask[3];
15080 /* The gp_value field is set by the MIPS ELF backend. */
15082 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
15083 ((Elf32_External_RegInfo *)
15084 mips_regmask_frag));
15088 Elf64_Internal_RegInfo s;
15090 s.ri_gprmask = mips_gprmask;
15092 s.ri_cprmask[0] = mips_cprmask[0];
15093 s.ri_cprmask[1] = mips_cprmask[1];
15094 s.ri_cprmask[2] = mips_cprmask[2];
15095 s.ri_cprmask[3] = mips_cprmask[3];
15096 /* The gp_value field is set by the MIPS ELF backend. */
15098 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
15099 ((Elf64_External_RegInfo *)
15100 mips_regmask_frag));
15103 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
15104 sort of BFD interface for this. */
15105 if (mips_any_noreorder)
15106 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
15107 if (mips_pic != NO_PIC)
15109 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
15110 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
15113 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
15115 /* Set MIPS ELF flags for ASEs. */
15116 /* We may need to define a new flag for DSP ASE, and set this flag when
15117 file_ase_dsp is true. */
15118 /* Same for DSP R2. */
15119 /* We may need to define a new flag for MT ASE, and set this flag when
15120 file_ase_mt is true. */
15121 if (file_ase_mips16)
15122 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
15123 #if 0 /* XXX FIXME */
15124 if (file_ase_mips3d)
15125 elf_elfheader (stdoutput)->e_flags |= ???;
15128 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
15130 /* Set the MIPS ELF ABI flags. */
15131 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
15132 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
15133 else if (mips_abi == O64_ABI)
15134 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
15135 else if (mips_abi == EABI_ABI)
15137 if (!file_mips_gp32)
15138 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
15140 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
15142 else if (mips_abi == N32_ABI)
15143 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
15145 /* Nothing to do for N64_ABI. */
15147 if (mips_32bitmode)
15148 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
15150 #if 0 /* XXX FIXME */
15151 /* 32 bit code with 64 bit FP registers. */
15152 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
15153 elf_elfheader (stdoutput)->e_flags |= ???;
15157 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
15159 typedef struct proc {
15161 symbolS *func_end_sym;
15162 unsigned long reg_mask;
15163 unsigned long reg_offset;
15164 unsigned long fpreg_mask;
15165 unsigned long fpreg_offset;
15166 unsigned long frame_offset;
15167 unsigned long frame_reg;
15168 unsigned long pc_reg;
15171 static procS cur_proc;
15172 static procS *cur_proc_ptr;
15173 static int numprocs;
15175 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal
15179 mips_nop_opcode (void)
15181 return seg_info (now_seg)->tc_segment_info_data.mips16;
15184 /* Fill in an rs_align_code fragment. This only needs to do something
15185 for MIPS16 code, where 0 is not a nop. */
15188 mips_handle_align (fragS *fragp)
15191 int bytes, size, excess;
15194 if (fragp->fr_type != rs_align_code)
15197 p = fragp->fr_literal + fragp->fr_fix;
15200 opcode = mips16_nop_insn.insn_opcode;
15205 opcode = nop_insn.insn_opcode;
15209 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
15210 excess = bytes % size;
15213 /* If we're not inserting a whole number of instructions,
15214 pad the end of the fixed part of the frag with zeros. */
15215 memset (p, 0, excess);
15217 fragp->fr_fix += excess;
15220 md_number_to_chars (p, opcode, size);
15221 fragp->fr_var = size;
15225 md_obj_begin (void)
15232 /* Check for premature end, nesting errors, etc. */
15234 as_warn (_("missing .end at end of assembly"));
15243 if (*input_line_pointer == '-')
15245 ++input_line_pointer;
15248 if (!ISDIGIT (*input_line_pointer))
15249 as_bad (_("expected simple number"));
15250 if (input_line_pointer[0] == '0')
15252 if (input_line_pointer[1] == 'x')
15254 input_line_pointer += 2;
15255 while (ISXDIGIT (*input_line_pointer))
15258 val |= hex_value (*input_line_pointer++);
15260 return negative ? -val : val;
15264 ++input_line_pointer;
15265 while (ISDIGIT (*input_line_pointer))
15268 val |= *input_line_pointer++ - '0';
15270 return negative ? -val : val;
15273 if (!ISDIGIT (*input_line_pointer))
15275 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
15276 *input_line_pointer, *input_line_pointer);
15277 as_warn (_("invalid number"));
15280 while (ISDIGIT (*input_line_pointer))
15283 val += *input_line_pointer++ - '0';
15285 return negative ? -val : val;
15288 /* The .file directive; just like the usual .file directive, but there
15289 is an initial number which is the ECOFF file index. In the non-ECOFF
15290 case .file implies DWARF-2. */
15293 s_mips_file (int x ATTRIBUTE_UNUSED)
15295 static int first_file_directive = 0;
15297 if (ECOFF_DEBUGGING)
15306 filename = dwarf2_directive_file (0);
15308 /* Versions of GCC up to 3.1 start files with a ".file"
15309 directive even for stabs output. Make sure that this
15310 ".file" is handled. Note that you need a version of GCC
15311 after 3.1 in order to support DWARF-2 on MIPS. */
15312 if (filename != NULL && ! first_file_directive)
15314 (void) new_logical_line (filename, -1);
15315 s_app_file_string (filename, 0);
15317 first_file_directive = 1;
15321 /* The .loc directive, implying DWARF-2. */
15324 s_mips_loc (int x ATTRIBUTE_UNUSED)
15326 if (!ECOFF_DEBUGGING)
15327 dwarf2_directive_loc (0);
15330 /* The .end directive. */
15333 s_mips_end (int x ATTRIBUTE_UNUSED)
15337 /* Following functions need their own .frame and .cprestore directives. */
15338 mips_frame_reg_valid = 0;
15339 mips_cprestore_valid = 0;
15341 if (!is_end_of_line[(unsigned char) *input_line_pointer])
15344 demand_empty_rest_of_line ();
15349 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
15350 as_warn (_(".end not in text section"));
15354 as_warn (_(".end directive without a preceding .ent directive."));
15355 demand_empty_rest_of_line ();
15361 gas_assert (S_GET_NAME (p));
15362 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
15363 as_warn (_(".end symbol does not match .ent symbol."));
15365 if (debug_type == DEBUG_STABS)
15366 stabs_generate_asm_endfunc (S_GET_NAME (p),
15370 as_warn (_(".end directive missing or unknown symbol"));
15373 /* Create an expression to calculate the size of the function. */
15374 if (p && cur_proc_ptr)
15376 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
15377 expressionS *exp = xmalloc (sizeof (expressionS));
15380 exp->X_op = O_subtract;
15381 exp->X_add_symbol = symbol_temp_new_now ();
15382 exp->X_op_symbol = p;
15383 exp->X_add_number = 0;
15385 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
15388 /* Generate a .pdr section. */
15389 if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr)
15391 segT saved_seg = now_seg;
15392 subsegT saved_subseg = now_subseg;
15396 #ifdef md_flush_pending_output
15397 md_flush_pending_output ();
15400 gas_assert (pdr_seg);
15401 subseg_set (pdr_seg, 0);
15403 /* Write the symbol. */
15404 exp.X_op = O_symbol;
15405 exp.X_add_symbol = p;
15406 exp.X_add_number = 0;
15407 emit_expr (&exp, 4);
15409 fragp = frag_more (7 * 4);
15411 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
15412 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
15413 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
15414 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
15415 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
15416 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
15417 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
15419 subseg_set (saved_seg, saved_subseg);
15421 #endif /* OBJ_ELF */
15423 cur_proc_ptr = NULL;
15426 /* The .aent and .ent directives. */
15429 s_mips_ent (int aent)
15433 symbolP = get_symbol ();
15434 if (*input_line_pointer == ',')
15435 ++input_line_pointer;
15436 SKIP_WHITESPACE ();
15437 if (ISDIGIT (*input_line_pointer)
15438 || *input_line_pointer == '-')
15441 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
15442 as_warn (_(".ent or .aent not in text section."));
15444 if (!aent && cur_proc_ptr)
15445 as_warn (_("missing .end"));
15449 /* This function needs its own .frame and .cprestore directives. */
15450 mips_frame_reg_valid = 0;
15451 mips_cprestore_valid = 0;
15453 cur_proc_ptr = &cur_proc;
15454 memset (cur_proc_ptr, '\0', sizeof (procS));
15456 cur_proc_ptr->func_sym = symbolP;
15460 if (debug_type == DEBUG_STABS)
15461 stabs_generate_asm_func (S_GET_NAME (symbolP),
15462 S_GET_NAME (symbolP));
15465 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
15467 demand_empty_rest_of_line ();
15470 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
15471 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
15472 s_mips_frame is used so that we can set the PDR information correctly.
15473 We can't use the ecoff routines because they make reference to the ecoff
15474 symbol table (in the mdebug section). */
15477 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
15480 if (IS_ELF && !ECOFF_DEBUGGING)
15484 if (cur_proc_ptr == (procS *) NULL)
15486 as_warn (_(".frame outside of .ent"));
15487 demand_empty_rest_of_line ();
15491 cur_proc_ptr->frame_reg = tc_get_register (1);
15493 SKIP_WHITESPACE ();
15494 if (*input_line_pointer++ != ','
15495 || get_absolute_expression_and_terminator (&val) != ',')
15497 as_warn (_("Bad .frame directive"));
15498 --input_line_pointer;
15499 demand_empty_rest_of_line ();
15503 cur_proc_ptr->frame_offset = val;
15504 cur_proc_ptr->pc_reg = tc_get_register (0);
15506 demand_empty_rest_of_line ();
15509 #endif /* OBJ_ELF */
15513 /* The .fmask and .mask directives. If the mdebug section is present
15514 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
15515 embedded targets, s_mips_mask is used so that we can set the PDR
15516 information correctly. We can't use the ecoff routines because they
15517 make reference to the ecoff symbol table (in the mdebug section). */
15520 s_mips_mask (int reg_type)
15523 if (IS_ELF && !ECOFF_DEBUGGING)
15527 if (cur_proc_ptr == (procS *) NULL)
15529 as_warn (_(".mask/.fmask outside of .ent"));
15530 demand_empty_rest_of_line ();
15534 if (get_absolute_expression_and_terminator (&mask) != ',')
15536 as_warn (_("Bad .mask/.fmask directive"));
15537 --input_line_pointer;
15538 demand_empty_rest_of_line ();
15542 off = get_absolute_expression ();
15544 if (reg_type == 'F')
15546 cur_proc_ptr->fpreg_mask = mask;
15547 cur_proc_ptr->fpreg_offset = off;
15551 cur_proc_ptr->reg_mask = mask;
15552 cur_proc_ptr->reg_offset = off;
15555 demand_empty_rest_of_line ();
15558 #endif /* OBJ_ELF */
15559 s_ignore (reg_type);
15562 /* A table describing all the processors gas knows about. Names are
15563 matched in the order listed.
15565 To ease comparison, please keep this table in the same order as
15566 gcc's mips_cpu_info_table[]. */
15567 static const struct mips_cpu_info mips_cpu_info_table[] =
15569 /* Entries for generic ISAs */
15570 { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 },
15571 { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 },
15572 { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 },
15573 { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 },
15574 { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 },
15575 { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 },
15576 { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 },
15577 { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
15578 { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
15581 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
15582 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
15583 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
15586 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
15589 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
15590 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
15591 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
15592 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
15593 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
15594 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
15595 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
15596 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
15597 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
15598 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
15599 { "orion", 0, ISA_MIPS3, CPU_R4600 },
15600 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
15601 /* ST Microelectronics Loongson 2E and 2F cores */
15602 { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E },
15603 { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F },
15606 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
15607 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
15608 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
15609 { "r14000", 0, ISA_MIPS4, CPU_R14000 },
15610 { "r16000", 0, ISA_MIPS4, CPU_R16000 },
15611 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
15612 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
15613 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
15614 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
15615 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
15616 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
15617 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
15618 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
15619 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
15620 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
15623 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
15624 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
15625 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
15626 { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
15628 /* MIPS 32 Release 2 */
15629 { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15630 { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15631 { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15632 { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
15633 { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15634 { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15635 { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15636 { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15637 { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15638 { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15639 /* Deprecated forms of the above. */
15640 { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15641 { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15642 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
15643 { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15644 { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15645 { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15646 { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15647 /* Deprecated forms of the above. */
15648 { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15649 { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15650 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
15651 { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15652 ISA_MIPS32R2, CPU_MIPS32R2 },
15653 { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15654 ISA_MIPS32R2, CPU_MIPS32R2 },
15655 { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15656 ISA_MIPS32R2, CPU_MIPS32R2 },
15657 { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15658 ISA_MIPS32R2, CPU_MIPS32R2 },
15659 /* Deprecated forms of the above. */
15660 { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15661 ISA_MIPS32R2, CPU_MIPS32R2 },
15662 { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15663 ISA_MIPS32R2, CPU_MIPS32R2 },
15664 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
15665 { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15666 ISA_MIPS32R2, CPU_MIPS32R2 },
15667 { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15668 ISA_MIPS32R2, CPU_MIPS32R2 },
15669 { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15670 ISA_MIPS32R2, CPU_MIPS32R2 },
15671 { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15672 ISA_MIPS32R2, CPU_MIPS32R2 },
15673 { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15674 ISA_MIPS32R2, CPU_MIPS32R2 },
15675 /* Deprecated forms of the above. */
15676 { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15677 ISA_MIPS32R2, CPU_MIPS32R2 },
15678 { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15679 ISA_MIPS32R2, CPU_MIPS32R2 },
15680 /* 1004K cores are multiprocessor versions of the 34K. */
15681 { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15682 ISA_MIPS32R2, CPU_MIPS32R2 },
15683 { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15684 ISA_MIPS32R2, CPU_MIPS32R2 },
15685 { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15686 ISA_MIPS32R2, CPU_MIPS32R2 },
15687 { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15688 ISA_MIPS32R2, CPU_MIPS32R2 },
15691 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
15692 { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
15693 { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
15694 { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
15696 /* Broadcom SB-1 CPU core */
15697 { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
15698 ISA_MIPS64, CPU_SB1 },
15699 /* Broadcom SB-1A CPU core */
15700 { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
15701 ISA_MIPS64, CPU_SB1 },
15703 { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A },
15705 /* MIPS 64 Release 2 */
15707 /* Cavium Networks Octeon CPU core */
15708 { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
15711 { "xlr", 0, ISA_MIPS64, CPU_XLR },
15718 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
15719 with a final "000" replaced by "k". Ignore case.
15721 Note: this function is shared between GCC and GAS. */
15724 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
15726 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
15727 given++, canonical++;
15729 return ((*given == 0 && *canonical == 0)
15730 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
15734 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
15735 CPU name. We've traditionally allowed a lot of variation here.
15737 Note: this function is shared between GCC and GAS. */
15740 mips_matching_cpu_name_p (const char *canonical, const char *given)
15742 /* First see if the name matches exactly, or with a final "000"
15743 turned into "k". */
15744 if (mips_strict_matching_cpu_name_p (canonical, given))
15747 /* If not, try comparing based on numerical designation alone.
15748 See if GIVEN is an unadorned number, or 'r' followed by a number. */
15749 if (TOLOWER (*given) == 'r')
15751 if (!ISDIGIT (*given))
15754 /* Skip over some well-known prefixes in the canonical name,
15755 hoping to find a number there too. */
15756 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
15758 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
15760 else if (TOLOWER (canonical[0]) == 'r')
15763 return mips_strict_matching_cpu_name_p (canonical, given);
15767 /* Parse an option that takes the name of a processor as its argument.
15768 OPTION is the name of the option and CPU_STRING is the argument.
15769 Return the corresponding processor enumeration if the CPU_STRING is
15770 recognized, otherwise report an error and return null.
15772 A similar function exists in GCC. */
15774 static const struct mips_cpu_info *
15775 mips_parse_cpu (const char *option, const char *cpu_string)
15777 const struct mips_cpu_info *p;
15779 /* 'from-abi' selects the most compatible architecture for the given
15780 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
15781 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15782 version. Look first at the -mgp options, if given, otherwise base
15783 the choice on MIPS_DEFAULT_64BIT.
15785 Treat NO_ABI like the EABIs. One reason to do this is that the
15786 plain 'mips' and 'mips64' configs have 'from-abi' as their default
15787 architecture. This code picks MIPS I for 'mips' and MIPS III for
15788 'mips64', just as we did in the days before 'from-abi'. */
15789 if (strcasecmp (cpu_string, "from-abi") == 0)
15791 if (ABI_NEEDS_32BIT_REGS (mips_abi))
15792 return mips_cpu_info_from_isa (ISA_MIPS1);
15794 if (ABI_NEEDS_64BIT_REGS (mips_abi))
15795 return mips_cpu_info_from_isa (ISA_MIPS3);
15797 if (file_mips_gp32 >= 0)
15798 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
15800 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
15805 /* 'default' has traditionally been a no-op. Probably not very useful. */
15806 if (strcasecmp (cpu_string, "default") == 0)
15809 for (p = mips_cpu_info_table; p->name != 0; p++)
15810 if (mips_matching_cpu_name_p (p->name, cpu_string))
15813 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
15817 /* Return the canonical processor information for ISA (a member of the
15818 ISA_MIPS* enumeration). */
15820 static const struct mips_cpu_info *
15821 mips_cpu_info_from_isa (int isa)
15825 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15826 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
15827 && isa == mips_cpu_info_table[i].isa)
15828 return (&mips_cpu_info_table[i]);
15833 static const struct mips_cpu_info *
15834 mips_cpu_info_from_arch (int arch)
15838 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15839 if (arch == mips_cpu_info_table[i].cpu)
15840 return (&mips_cpu_info_table[i]);
15846 show (FILE *stream, const char *string, int *col_p, int *first_p)
15850 fprintf (stream, "%24s", "");
15855 fprintf (stream, ", ");
15859 if (*col_p + strlen (string) > 72)
15861 fprintf (stream, "\n%24s", "");
15865 fprintf (stream, "%s", string);
15866 *col_p += strlen (string);
15872 md_show_usage (FILE *stream)
15877 fprintf (stream, _("\
15879 -EB generate big endian output\n\
15880 -EL generate little endian output\n\
15881 -g, -g2 do not remove unneeded NOPs or swap branches\n\
15882 -G NUM allow referencing objects up to NUM bytes\n\
15883 implicitly with the gp register [default 8]\n"));
15884 fprintf (stream, _("\
15885 -mips1 generate MIPS ISA I instructions\n\
15886 -mips2 generate MIPS ISA II instructions\n\
15887 -mips3 generate MIPS ISA III instructions\n\
15888 -mips4 generate MIPS ISA IV instructions\n\
15889 -mips5 generate MIPS ISA V instructions\n\
15890 -mips32 generate MIPS32 ISA instructions\n\
15891 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
15892 -mips64 generate MIPS64 ISA instructions\n\
15893 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
15894 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
15898 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15899 show (stream, mips_cpu_info_table[i].name, &column, &first);
15900 show (stream, "from-abi", &column, &first);
15901 fputc ('\n', stream);
15903 fprintf (stream, _("\
15904 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
15905 -no-mCPU don't generate code specific to CPU.\n\
15906 For -mCPU and -no-mCPU, CPU must be one of:\n"));
15910 show (stream, "3900", &column, &first);
15911 show (stream, "4010", &column, &first);
15912 show (stream, "4100", &column, &first);
15913 show (stream, "4650", &column, &first);
15914 fputc ('\n', stream);
15916 fprintf (stream, _("\
15917 -mips16 generate mips16 instructions\n\
15918 -no-mips16 do not generate mips16 instructions\n"));
15919 fprintf (stream, _("\
15920 -msmartmips generate smartmips instructions\n\
15921 -mno-smartmips do not generate smartmips instructions\n"));
15922 fprintf (stream, _("\
15923 -mdsp generate DSP instructions\n\
15924 -mno-dsp do not generate DSP instructions\n"));
15925 fprintf (stream, _("\
15926 -mdspr2 generate DSP R2 instructions\n\
15927 -mno-dspr2 do not generate DSP R2 instructions\n"));
15928 fprintf (stream, _("\
15929 -mmt generate MT instructions\n\
15930 -mno-mt do not generate MT instructions\n"));
15931 fprintf (stream, _("\
15932 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
15933 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
15934 -mfix-vr4120 work around certain VR4120 errata\n\
15935 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
15936 -mfix-24k insert a nop after ERET and DERET instructions\n\
15937 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
15938 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
15939 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
15940 -msym32 assume all symbols have 32-bit values\n\
15941 -O0 remove unneeded NOPs, do not swap branches\n\
15942 -O remove unneeded NOPs and swap branches\n\
15943 --trap, --no-break trap exception on div by 0 and mult overflow\n\
15944 --break, --no-trap break exception on div by 0 and mult overflow\n"));
15945 fprintf (stream, _("\
15946 -mhard-float allow floating-point instructions\n\
15947 -msoft-float do not allow floating-point instructions\n\
15948 -msingle-float only allow 32-bit floating-point operations\n\
15949 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
15950 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
15953 fprintf (stream, _("\
15954 -KPIC, -call_shared generate SVR4 position independent code\n\
15955 -call_nonpic generate non-PIC code that can operate with DSOs\n\
15956 -mvxworks-pic generate VxWorks position independent code\n\
15957 -non_shared do not generate code that can operate with DSOs\n\
15958 -xgot assume a 32 bit GOT\n\
15959 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
15960 -mshared, -mno-shared disable/enable .cpload optimization for\n\
15961 position dependent (non shared) code\n\
15962 -mabi=ABI create ABI conformant object file for:\n"));
15966 show (stream, "32", &column, &first);
15967 show (stream, "o64", &column, &first);
15968 show (stream, "n32", &column, &first);
15969 show (stream, "64", &column, &first);
15970 show (stream, "eabi", &column, &first);
15972 fputc ('\n', stream);
15974 fprintf (stream, _("\
15975 -32 create o32 ABI object file (default)\n\
15976 -n32 create n32 ABI object file\n\
15977 -64 create 64 ABI object file\n"));
15983 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
15985 if (HAVE_64BIT_SYMBOLS)
15986 return dwarf2_format_64bit_irix;
15988 return dwarf2_format_32bit;
15993 mips_dwarf2_addr_size (void)
15995 if (HAVE_64BIT_OBJECTS)
16001 /* Standard calling conventions leave the CFA at SP on entry. */
16003 mips_cfi_frame_initial_instructions (void)
16005 cfi_add_CFA_def_cfa_register (SP);
16009 tc_mips_regname_to_dw2regnum (char *regname)
16011 unsigned int regnum = -1;
16014 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))