1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 #define AT mips_opts.at
107 /* Allow override of standard little-endian ECOFF format. */
109 #ifndef ECOFF_LITTLE_FORMAT
110 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
113 extern int target_big_endian;
115 /* The name of the readonly data section. */
116 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
124 /* Ways in which an instruction can be "appended" to the output. */
126 /* Just add it normally. */
129 /* Add it normally and then add a nop. */
132 /* Turn an instruction with a delay slot into a "compact" version. */
135 /* Insert the instruction before the last one. */
139 /* Information about an instruction, including its format, operands
143 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
144 const struct mips_opcode *insn_mo;
146 /* True if this is a mips16 instruction and if we want the extended
148 bfd_boolean use_extend;
150 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
151 unsigned short extend;
153 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
154 a copy of INSN_MO->match with the operands filled in. */
155 unsigned long insn_opcode;
157 /* The frag that contains the instruction. */
160 /* The offset into FRAG of the first instruction byte. */
163 /* The relocs associated with the instruction, if any. */
166 /* True if this entry cannot be moved from its current position. */
167 unsigned int fixed_p : 1;
169 /* True if this instruction occurred in a .set noreorder block. */
170 unsigned int noreorder_p : 1;
172 /* True for mips16 instructions that jump to an absolute address. */
173 unsigned int mips16_absolute_jump_p : 1;
175 /* True if this instruction is complete. */
176 unsigned int complete_p : 1;
179 /* The ABI to use. */
190 /* MIPS ABI we are using for this output file. */
191 static enum mips_abi_level mips_abi = NO_ABI;
193 /* Whether or not we have code that can call pic code. */
194 int mips_abicalls = FALSE;
196 /* Whether or not we have code which can be put into a shared
198 static bfd_boolean mips_in_shared = TRUE;
200 /* This is the set of options which may be modified by the .set
201 pseudo-op. We use a struct so that .set push and .set pop are more
204 struct mips_set_options
206 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
207 if it has not been initialized. Changed by `.set mipsN', and the
208 -mipsN command line option, and the default CPU. */
210 /* Enabled Application Specific Extensions (ASEs). These are set to -1
211 if they have not been initialized. Changed by `.set <asename>', by
212 command line options, and based on the default architecture. */
219 /* Whether we are assembling for the mips16 processor. 0 if we are
220 not, 1 if we are, and -1 if the value has not been initialized.
221 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
222 -nomips16 command line options, and the default CPU. */
224 /* Non-zero if we should not reorder instructions. Changed by `.set
225 reorder' and `.set noreorder'. */
227 /* Non-zero if we should not permit the register designated "assembler
228 temporary" to be used in instructions. The value is the register
229 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
230 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
232 /* Non-zero if we should warn when a macro instruction expands into
233 more than one machine instruction. Changed by `.set nomacro' and
235 int warn_about_macros;
236 /* Non-zero if we should not move instructions. Changed by `.set
237 move', `.set volatile', `.set nomove', and `.set novolatile'. */
239 /* Non-zero if we should not optimize branches by moving the target
240 of the branch into the delay slot. Actually, we don't perform
241 this optimization anyhow. Changed by `.set bopt' and `.set
244 /* Non-zero if we should not autoextend mips16 instructions.
245 Changed by `.set autoextend' and `.set noautoextend'. */
247 /* Restrict general purpose registers and floating point registers
248 to 32 bit. This is initially determined when -mgp32 or -mfp32
249 is passed but can changed if the assembler code uses .set mipsN. */
252 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
253 command line option, and the default CPU. */
255 /* True if ".set sym32" is in effect. */
257 /* True if floating-point operations are not allowed. Changed by .set
258 softfloat or .set hardfloat, by command line options -msoft-float or
259 -mhard-float. The default is false. */
260 bfd_boolean soft_float;
262 /* True if only single-precision floating-point operations are allowed.
263 Changed by .set singlefloat or .set doublefloat, command-line options
264 -msingle-float or -mdouble-float. The default is false. */
265 bfd_boolean single_float;
268 /* This is the struct we use to hold the current set of options. Note
269 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
270 -1 to indicate that they have not been initialized. */
272 /* True if -mgp32 was passed. */
273 static int file_mips_gp32 = -1;
275 /* True if -mfp32 was passed. */
276 static int file_mips_fp32 = -1;
278 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
279 static int file_mips_soft_float = 0;
281 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
282 static int file_mips_single_float = 0;
284 static struct mips_set_options mips_opts =
286 /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
287 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
288 /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG,
289 /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
290 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN,
291 /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE
294 /* These variables are filled in with the masks of registers used.
295 The object format code reads them and puts them in the appropriate
297 unsigned long mips_gprmask;
298 unsigned long mips_cprmask[4];
300 /* MIPS ISA we are using for this output file. */
301 static int file_mips_isa = ISA_UNKNOWN;
303 /* True if any MIPS16 code was produced. */
304 static int file_ase_mips16;
306 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
307 || mips_opts.isa == ISA_MIPS32R2 \
308 || mips_opts.isa == ISA_MIPS64 \
309 || mips_opts.isa == ISA_MIPS64R2)
311 /* True if we want to create R_MIPS_JALR for jalr $25. */
313 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
315 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
316 because there's no place for any addend, the only acceptable
317 expression is a bare symbol. */
318 #define MIPS_JALR_HINT_P(EXPR) \
319 (!HAVE_IN_PLACE_ADDENDS \
320 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
323 /* True if -mips3d was passed or implied by arguments passed on the
324 command line (e.g., by -march). */
325 static int file_ase_mips3d;
327 /* True if -mdmx was passed or implied by arguments passed on the
328 command line (e.g., by -march). */
329 static int file_ase_mdmx;
331 /* True if -msmartmips was passed or implied by arguments passed on the
332 command line (e.g., by -march). */
333 static int file_ase_smartmips;
335 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
336 || mips_opts.isa == ISA_MIPS32R2)
338 /* True if -mdsp was passed or implied by arguments passed on the
339 command line (e.g., by -march). */
340 static int file_ase_dsp;
342 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
343 || mips_opts.isa == ISA_MIPS64R2)
345 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
347 /* True if -mdspr2 was passed or implied by arguments passed on the
348 command line (e.g., by -march). */
349 static int file_ase_dspr2;
351 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
352 || mips_opts.isa == ISA_MIPS64R2)
354 /* True if -mmt was passed or implied by arguments passed on the
355 command line (e.g., by -march). */
356 static int file_ase_mt;
358 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
359 || mips_opts.isa == ISA_MIPS64R2)
361 /* The argument of the -march= flag. The architecture we are assembling. */
362 static int file_mips_arch = CPU_UNKNOWN;
363 static const char *mips_arch_string;
365 /* The argument of the -mtune= flag. The architecture for which we
367 static int mips_tune = CPU_UNKNOWN;
368 static const char *mips_tune_string;
370 /* True when generating 32-bit code for a 64-bit processor. */
371 static int mips_32bitmode = 0;
373 /* True if the given ABI requires 32-bit registers. */
374 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
376 /* Likewise 64-bit registers. */
377 #define ABI_NEEDS_64BIT_REGS(ABI) \
379 || (ABI) == N64_ABI \
382 /* Return true if ISA supports 64 bit wide gp registers. */
383 #define ISA_HAS_64BIT_REGS(ISA) \
384 ((ISA) == ISA_MIPS3 \
385 || (ISA) == ISA_MIPS4 \
386 || (ISA) == ISA_MIPS5 \
387 || (ISA) == ISA_MIPS64 \
388 || (ISA) == ISA_MIPS64R2)
390 /* Return true if ISA supports 64 bit wide float registers. */
391 #define ISA_HAS_64BIT_FPRS(ISA) \
392 ((ISA) == ISA_MIPS3 \
393 || (ISA) == ISA_MIPS4 \
394 || (ISA) == ISA_MIPS5 \
395 || (ISA) == ISA_MIPS32R2 \
396 || (ISA) == ISA_MIPS64 \
397 || (ISA) == ISA_MIPS64R2)
399 /* Return true if ISA supports 64-bit right rotate (dror et al.)
401 #define ISA_HAS_DROR(ISA) \
402 ((ISA) == ISA_MIPS64R2)
404 /* Return true if ISA supports 32-bit right rotate (ror et al.)
406 #define ISA_HAS_ROR(ISA) \
407 ((ISA) == ISA_MIPS32R2 \
408 || (ISA) == ISA_MIPS64R2 \
409 || mips_opts.ase_smartmips)
411 /* Return true if ISA supports single-precision floats in odd registers. */
412 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
413 ((ISA) == ISA_MIPS32 \
414 || (ISA) == ISA_MIPS32R2 \
415 || (ISA) == ISA_MIPS64 \
416 || (ISA) == ISA_MIPS64R2)
418 /* Return true if ISA supports move to/from high part of a 64-bit
419 floating-point register. */
420 #define ISA_HAS_MXHC1(ISA) \
421 ((ISA) == ISA_MIPS32R2 \
422 || (ISA) == ISA_MIPS64R2)
424 #define HAVE_32BIT_GPRS \
425 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
427 #define HAVE_32BIT_FPRS \
428 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
430 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
431 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
433 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
435 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
437 /* True if relocations are stored in-place. */
438 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
440 /* The ABI-derived address size. */
441 #define HAVE_64BIT_ADDRESSES \
442 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
443 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
445 /* The size of symbolic constants (i.e., expressions of the form
446 "SYMBOL" or "SYMBOL + OFFSET"). */
447 #define HAVE_32BIT_SYMBOLS \
448 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
449 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
451 /* Addresses are loaded in different ways, depending on the address size
452 in use. The n32 ABI Documentation also mandates the use of additions
453 with overflow checking, but existing implementations don't follow it. */
454 #define ADDRESS_ADD_INSN \
455 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
457 #define ADDRESS_ADDI_INSN \
458 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
460 #define ADDRESS_LOAD_INSN \
461 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
463 #define ADDRESS_STORE_INSN \
464 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
466 /* Return true if the given CPU supports the MIPS16 ASE. */
467 #define CPU_HAS_MIPS16(cpu) \
468 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
469 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
471 /* True if CPU has a dror instruction. */
472 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
474 /* True if CPU has a ror instruction. */
475 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
477 /* True if CPU has seq/sne and seqi/snei instructions. */
478 #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON)
480 /* True if CPU does not implement the all the coprocessor insns. For these
481 CPUs only those COP insns are accepted that are explicitly marked to be
482 available on the CPU. ISA membership for COP insns is ignored. */
483 #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON)
485 /* True if mflo and mfhi can be immediately followed by instructions
486 which write to the HI and LO registers.
488 According to MIPS specifications, MIPS ISAs I, II, and III need
489 (at least) two instructions between the reads of HI/LO and
490 instructions which write them, and later ISAs do not. Contradicting
491 the MIPS specifications, some MIPS IV processor user manuals (e.g.
492 the UM for the NEC Vr5000) document needing the instructions between
493 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
494 MIPS64 and later ISAs to have the interlocks, plus any specific
495 earlier-ISA CPUs for which CPU documentation declares that the
496 instructions are really interlocked. */
497 #define hilo_interlocks \
498 (mips_opts.isa == ISA_MIPS32 \
499 || mips_opts.isa == ISA_MIPS32R2 \
500 || mips_opts.isa == ISA_MIPS64 \
501 || mips_opts.isa == ISA_MIPS64R2 \
502 || mips_opts.arch == CPU_R4010 \
503 || mips_opts.arch == CPU_R10000 \
504 || mips_opts.arch == CPU_R12000 \
505 || mips_opts.arch == CPU_R14000 \
506 || mips_opts.arch == CPU_R16000 \
507 || mips_opts.arch == CPU_RM7000 \
508 || mips_opts.arch == CPU_VR5500 \
511 /* Whether the processor uses hardware interlocks to protect reads
512 from the GPRs after they are loaded from memory, and thus does not
513 require nops to be inserted. This applies to instructions marked
514 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
516 #define gpr_interlocks \
517 (mips_opts.isa != ISA_MIPS1 \
518 || mips_opts.arch == CPU_R3900)
520 /* Whether the processor uses hardware interlocks to avoid delays
521 required by coprocessor instructions, and thus does not require
522 nops to be inserted. This applies to instructions marked
523 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
524 between instructions marked INSN_WRITE_COND_CODE and ones marked
525 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
526 levels I, II, and III. */
527 /* Itbl support may require additional care here. */
528 #define cop_interlocks \
529 ((mips_opts.isa != ISA_MIPS1 \
530 && mips_opts.isa != ISA_MIPS2 \
531 && mips_opts.isa != ISA_MIPS3) \
532 || mips_opts.arch == CPU_R4300 \
535 /* Whether the processor uses hardware interlocks to protect reads
536 from coprocessor registers after they are loaded from memory, and
537 thus does not require nops to be inserted. This applies to
538 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
539 requires at MIPS ISA level I. */
540 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
542 /* Is this a mfhi or mflo instruction? */
543 #define MF_HILO_INSN(PINFO) \
544 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
546 /* Returns true for a (non floating-point) coprocessor instruction. Reading
547 or writing the condition code is only possible on the coprocessors and
548 these insns are not marked with INSN_COP. Thus for these insns use the
549 condition-code flags. */
550 #define COP_INSN(PINFO) \
551 (PINFO != INSN_MACRO \
552 && ((PINFO) & (FP_S | FP_D)) == 0 \
553 && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
555 /* MIPS PIC level. */
557 enum mips_pic_level mips_pic;
559 /* 1 if we should generate 32 bit offsets from the $gp register in
560 SVR4_PIC mode. Currently has no meaning in other modes. */
561 static int mips_big_got = 0;
563 /* 1 if trap instructions should used for overflow rather than break
565 static int mips_trap = 0;
567 /* 1 if double width floating point constants should not be constructed
568 by assembling two single width halves into two single width floating
569 point registers which just happen to alias the double width destination
570 register. On some architectures this aliasing can be disabled by a bit
571 in the status register, and the setting of this bit cannot be determined
572 automatically at assemble time. */
573 static int mips_disable_float_construction;
575 /* Non-zero if any .set noreorder directives were used. */
577 static int mips_any_noreorder;
579 /* Non-zero if nops should be inserted when the register referenced in
580 an mfhi/mflo instruction is read in the next two instructions. */
581 static int mips_7000_hilo_fix;
583 /* The size of objects in the small data section. */
584 static unsigned int g_switch_value = 8;
585 /* Whether the -G option was used. */
586 static int g_switch_seen = 0;
591 /* If we can determine in advance that GP optimization won't be
592 possible, we can skip the relaxation stuff that tries to produce
593 GP-relative references. This makes delay slot optimization work
596 This function can only provide a guess, but it seems to work for
597 gcc output. It needs to guess right for gcc, otherwise gcc
598 will put what it thinks is a GP-relative instruction in a branch
601 I don't know if a fix is needed for the SVR4_PIC mode. I've only
602 fixed it for the non-PIC mode. KR 95/04/07 */
603 static int nopic_need_relax (symbolS *, int);
605 /* handle of the OPCODE hash table */
606 static struct hash_control *op_hash = NULL;
608 /* The opcode hash table we use for the mips16. */
609 static struct hash_control *mips16_op_hash = NULL;
611 /* This array holds the chars that always start a comment. If the
612 pre-processor is disabled, these aren't very useful */
613 const char comment_chars[] = "#";
615 /* This array holds the chars that only start a comment at the beginning of
616 a line. If the line seems to have the form '# 123 filename'
617 .line and .file directives will appear in the pre-processed output */
618 /* Note that input_file.c hand checks for '#' at the beginning of the
619 first line of the input file. This is because the compiler outputs
620 #NO_APP at the beginning of its output. */
621 /* Also note that C style comments are always supported. */
622 const char line_comment_chars[] = "#";
624 /* This array holds machine specific line separator characters. */
625 const char line_separator_chars[] = ";";
627 /* Chars that can be used to separate mant from exp in floating point nums */
628 const char EXP_CHARS[] = "eE";
630 /* Chars that mean this number is a floating point constant */
633 const char FLT_CHARS[] = "rRsSfFdDxXpP";
635 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
636 changed in read.c . Ideally it shouldn't have to know about it at all,
637 but nothing is ideal around here.
640 static char *insn_error;
642 static int auto_align = 1;
644 /* When outputting SVR4 PIC code, the assembler needs to know the
645 offset in the stack frame from which to restore the $gp register.
646 This is set by the .cprestore pseudo-op, and saved in this
648 static offsetT mips_cprestore_offset = -1;
650 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
651 more optimizations, it can use a register value instead of a memory-saved
652 offset and even an other register than $gp as global pointer. */
653 static offsetT mips_cpreturn_offset = -1;
654 static int mips_cpreturn_register = -1;
655 static int mips_gp_register = GP;
656 static int mips_gprel_offset = 0;
658 /* Whether mips_cprestore_offset has been set in the current function
659 (or whether it has already been warned about, if not). */
660 static int mips_cprestore_valid = 0;
662 /* This is the register which holds the stack frame, as set by the
663 .frame pseudo-op. This is needed to implement .cprestore. */
664 static int mips_frame_reg = SP;
666 /* Whether mips_frame_reg has been set in the current function
667 (or whether it has already been warned about, if not). */
668 static int mips_frame_reg_valid = 0;
670 /* To output NOP instructions correctly, we need to keep information
671 about the previous two instructions. */
673 /* Whether we are optimizing. The default value of 2 means to remove
674 unneeded NOPs and swap branch instructions when possible. A value
675 of 1 means to not swap branches. A value of 0 means to always
677 static int mips_optimize = 2;
679 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
680 equivalent to seeing no -g option at all. */
681 static int mips_debug = 0;
683 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
684 #define MAX_VR4130_NOPS 4
686 /* The maximum number of NOPs needed to fill delay slots. */
687 #define MAX_DELAY_NOPS 2
689 /* The maximum number of NOPs needed for any purpose. */
692 /* A list of previous instructions, with index 0 being the most recent.
693 We need to look back MAX_NOPS instructions when filling delay slots
694 or working around processor errata. We need to look back one
695 instruction further if we're thinking about using history[0] to
696 fill a branch delay slot. */
697 static struct mips_cl_insn history[1 + MAX_NOPS];
699 /* Nop instructions used by emit_nop. */
700 static struct mips_cl_insn nop_insn, mips16_nop_insn;
702 /* The appropriate nop for the current mode. */
703 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
705 /* If this is set, it points to a frag holding nop instructions which
706 were inserted before the start of a noreorder section. If those
707 nops turn out to be unnecessary, the size of the frag can be
709 static fragS *prev_nop_frag;
711 /* The number of nop instructions we created in prev_nop_frag. */
712 static int prev_nop_frag_holds;
714 /* The number of nop instructions that we know we need in
716 static int prev_nop_frag_required;
718 /* The number of instructions we've seen since prev_nop_frag. */
719 static int prev_nop_frag_since;
721 /* For ECOFF and ELF, relocations against symbols are done in two
722 parts, with a HI relocation and a LO relocation. Each relocation
723 has only 16 bits of space to store an addend. This means that in
724 order for the linker to handle carries correctly, it must be able
725 to locate both the HI and the LO relocation. This means that the
726 relocations must appear in order in the relocation table.
728 In order to implement this, we keep track of each unmatched HI
729 relocation. We then sort them so that they immediately precede the
730 corresponding LO relocation. */
735 struct mips_hi_fixup *next;
738 /* The section this fixup is in. */
742 /* The list of unmatched HI relocs. */
744 static struct mips_hi_fixup *mips_hi_fixup_list;
746 /* The frag containing the last explicit relocation operator.
747 Null if explicit relocations have not been used. */
749 static fragS *prev_reloc_op_frag;
751 /* Map normal MIPS register numbers to mips16 register numbers. */
753 #define X ILLEGAL_REG
754 static const int mips32_to_16_reg_map[] =
756 X, X, 2, 3, 4, 5, 6, 7,
757 X, X, X, X, X, X, X, X,
758 0, 1, X, X, X, X, X, X,
759 X, X, X, X, X, X, X, X
763 /* Map mips16 register numbers to normal MIPS register numbers. */
765 static const unsigned int mips16_to_32_reg_map[] =
767 16, 17, 2, 3, 4, 5, 6, 7
770 /* Classifies the kind of instructions we're interested in when
771 implementing -mfix-vr4120. */
772 enum fix_vr4120_class
780 NUM_FIX_VR4120_CLASSES
783 /* ...likewise -mfix-loongson2f-jump. */
784 static bfd_boolean mips_fix_loongson2f_jump;
786 /* ...likewise -mfix-loongson2f-nop. */
787 static bfd_boolean mips_fix_loongson2f_nop;
789 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
790 static bfd_boolean mips_fix_loongson2f;
792 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
793 there must be at least one other instruction between an instruction
794 of type X and an instruction of type Y. */
795 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
797 /* True if -mfix-vr4120 is in force. */
798 static int mips_fix_vr4120;
800 /* ...likewise -mfix-vr4130. */
801 static int mips_fix_vr4130;
803 /* ...likewise -mfix-24k. */
804 static int mips_fix_24k;
806 /* ...likewise -mfix-cn63xxp1 */
807 static bfd_boolean mips_fix_cn63xxp1;
809 /* We don't relax branches by default, since this causes us to expand
810 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
811 fail to compute the offset before expanding the macro to the most
812 efficient expansion. */
814 static int mips_relax_branch;
816 /* The expansion of many macros depends on the type of symbol that
817 they refer to. For example, when generating position-dependent code,
818 a macro that refers to a symbol may have two different expansions,
819 one which uses GP-relative addresses and one which uses absolute
820 addresses. When generating SVR4-style PIC, a macro may have
821 different expansions for local and global symbols.
823 We handle these situations by generating both sequences and putting
824 them in variant frags. In position-dependent code, the first sequence
825 will be the GP-relative one and the second sequence will be the
826 absolute one. In SVR4 PIC, the first sequence will be for global
827 symbols and the second will be for local symbols.
829 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
830 SECOND are the lengths of the two sequences in bytes. These fields
831 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
832 the subtype has the following flags:
835 Set if it has been decided that we should use the second
836 sequence instead of the first.
839 Set in the first variant frag if the macro's second implementation
840 is longer than its first. This refers to the macro as a whole,
841 not an individual relaxation.
844 Set in the first variant frag if the macro appeared in a .set nomacro
845 block and if one alternative requires a warning but the other does not.
848 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
851 The frag's "opcode" points to the first fixup for relaxable code.
853 Relaxable macros are generated using a sequence such as:
855 relax_start (SYMBOL);
856 ... generate first expansion ...
858 ... generate second expansion ...
861 The code and fixups for the unwanted alternative are discarded
862 by md_convert_frag. */
863 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
865 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
866 #define RELAX_SECOND(X) ((X) & 0xff)
867 #define RELAX_USE_SECOND 0x10000
868 #define RELAX_SECOND_LONGER 0x20000
869 #define RELAX_NOMACRO 0x40000
870 #define RELAX_DELAY_SLOT 0x80000
872 /* Branch without likely bit. If label is out of range, we turn:
874 beq reg1, reg2, label
884 with the following opcode replacements:
891 bltzal <-> bgezal (with jal label instead of j label)
893 Even though keeping the delay slot instruction in the delay slot of
894 the branch would be more efficient, it would be very tricky to do
895 correctly, because we'd have to introduce a variable frag *after*
896 the delay slot instruction, and expand that instead. Let's do it
897 the easy way for now, even if the branch-not-taken case now costs
898 one additional instruction. Out-of-range branches are not supposed
899 to be common, anyway.
901 Branch likely. If label is out of range, we turn:
903 beql reg1, reg2, label
904 delay slot (annulled if branch not taken)
913 delay slot (executed only if branch taken)
916 It would be possible to generate a shorter sequence by losing the
917 likely bit, generating something like:
922 delay slot (executed only if branch taken)
934 bltzall -> bgezal (with jal label instead of j label)
935 bgezall -> bltzal (ditto)
938 but it's not clear that it would actually improve performance. */
939 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
943 | ((toofar) ? 0x20 : 0) \
944 | ((link) ? 0x40 : 0) \
945 | ((likely) ? 0x80 : 0) \
946 | ((uncond) ? 0x100 : 0)))
947 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
948 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
949 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
950 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
951 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
952 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
954 /* For mips16 code, we use an entirely different form of relaxation.
955 mips16 supports two versions of most instructions which take
956 immediate values: a small one which takes some small value, and a
957 larger one which takes a 16 bit value. Since branches also follow
958 this pattern, relaxing these values is required.
960 We can assemble both mips16 and normal MIPS code in a single
961 object. Therefore, we need to support this type of relaxation at
962 the same time that we support the relaxation described above. We
963 use the high bit of the subtype field to distinguish these cases.
965 The information we store for this type of relaxation is the
966 argument code found in the opcode file for this relocation, whether
967 the user explicitly requested a small or extended form, and whether
968 the relocation is in a jump or jal delay slot. That tells us the
969 size of the value, and how it should be stored. We also store
970 whether the fragment is considered to be extended or not. We also
971 store whether this is known to be a branch to a different section,
972 whether we have tried to relax this frag yet, and whether we have
973 ever extended a PC relative fragment because of a shift count. */
974 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
977 | ((small) ? 0x100 : 0) \
978 | ((ext) ? 0x200 : 0) \
979 | ((dslot) ? 0x400 : 0) \
980 | ((jal_dslot) ? 0x800 : 0))
981 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
982 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
983 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
984 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
985 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
986 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
987 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
988 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
989 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
990 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
991 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
992 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
994 /* Is the given value a sign-extended 32-bit value? */
995 #define IS_SEXT_32BIT_NUM(x) \
996 (((x) &~ (offsetT) 0x7fffffff) == 0 \
997 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
999 /* Is the given value a sign-extended 16-bit value? */
1000 #define IS_SEXT_16BIT_NUM(x) \
1001 (((x) &~ (offsetT) 0x7fff) == 0 \
1002 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1004 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1005 #define IS_ZEXT_32BIT_NUM(x) \
1006 (((x) &~ (offsetT) 0xffffffff) == 0 \
1007 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1009 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1010 VALUE << SHIFT. VALUE is evaluated exactly once. */
1011 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1012 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1013 | (((VALUE) & (MASK)) << (SHIFT)))
1015 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1017 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1018 (((STRUCT) >> (SHIFT)) & (MASK))
1020 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1021 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1023 include/opcode/mips.h specifies operand fields using the macros
1024 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1025 with "MIPS16OP" instead of "OP". */
1026 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
1027 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
1028 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1029 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1030 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1032 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1033 #define EXTRACT_OPERAND(FIELD, INSN) \
1034 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
1035 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1036 EXTRACT_BITS ((INSN).insn_opcode, \
1037 MIPS16OP_MASK_##FIELD, \
1038 MIPS16OP_SH_##FIELD)
1040 /* Global variables used when generating relaxable macros. See the
1041 comment above RELAX_ENCODE for more details about how relaxation
1044 /* 0 if we're not emitting a relaxable macro.
1045 1 if we're emitting the first of the two relaxation alternatives.
1046 2 if we're emitting the second alternative. */
1049 /* The first relaxable fixup in the current frag. (In other words,
1050 the first fixup that refers to relaxable code.) */
1053 /* sizes[0] says how many bytes of the first alternative are stored in
1054 the current frag. Likewise sizes[1] for the second alternative. */
1055 unsigned int sizes[2];
1057 /* The symbol on which the choice of sequence depends. */
1061 /* Global variables used to decide whether a macro needs a warning. */
1063 /* True if the macro is in a branch delay slot. */
1064 bfd_boolean delay_slot_p;
1066 /* For relaxable macros, sizes[0] is the length of the first alternative
1067 in bytes and sizes[1] is the length of the second alternative.
1068 For non-relaxable macros, both elements give the length of the
1070 unsigned int sizes[2];
1072 /* The first variant frag for this macro. */
1074 } mips_macro_warning;
1076 /* Prototypes for static functions. */
1078 #define internalError() \
1079 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1081 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1083 static void append_insn
1084 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *);
1085 static void mips_no_prev_insn (void);
1086 static void macro_build (expressionS *, const char *, const char *, ...);
1087 static void mips16_macro_build
1088 (expressionS *, const char *, const char *, va_list *);
1089 static void load_register (int, expressionS *, int);
1090 static void macro_start (void);
1091 static void macro_end (void);
1092 static void macro (struct mips_cl_insn * ip);
1093 static void mips16_macro (struct mips_cl_insn * ip);
1094 static void mips_ip (char *str, struct mips_cl_insn * ip);
1095 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1096 static void mips16_immed
1097 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
1098 unsigned long *, bfd_boolean *, unsigned short *);
1099 static size_t my_getSmallExpression
1100 (expressionS *, bfd_reloc_code_real_type *, char *);
1101 static void my_getExpression (expressionS *, char *);
1102 static void s_align (int);
1103 static void s_change_sec (int);
1104 static void s_change_section (int);
1105 static void s_cons (int);
1106 static void s_float_cons (int);
1107 static void s_mips_globl (int);
1108 static void s_option (int);
1109 static void s_mipsset (int);
1110 static void s_abicalls (int);
1111 static void s_cpload (int);
1112 static void s_cpsetup (int);
1113 static void s_cplocal (int);
1114 static void s_cprestore (int);
1115 static void s_cpreturn (int);
1116 static void s_dtprelword (int);
1117 static void s_dtpreldword (int);
1118 static void s_gpvalue (int);
1119 static void s_gpword (int);
1120 static void s_gpdword (int);
1121 static void s_cpadd (int);
1122 static void s_insn (int);
1123 static void md_obj_begin (void);
1124 static void md_obj_end (void);
1125 static void s_mips_ent (int);
1126 static void s_mips_end (int);
1127 static void s_mips_frame (int);
1128 static void s_mips_mask (int reg_type);
1129 static void s_mips_stab (int);
1130 static void s_mips_weakext (int);
1131 static void s_mips_file (int);
1132 static void s_mips_loc (int);
1133 static bfd_boolean pic_need_relax (symbolS *, asection *);
1134 static int relaxed_branch_length (fragS *, asection *, int);
1135 static int validate_mips_insn (const struct mips_opcode *);
1137 /* Table and functions used to map between CPU/ISA names, and
1138 ISA levels, and CPU numbers. */
1140 struct mips_cpu_info
1142 const char *name; /* CPU or ISA name. */
1143 int flags; /* ASEs available, or ISA flag. */
1144 int isa; /* ISA level. */
1145 int cpu; /* CPU number (default CPU if ISA). */
1148 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1149 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1150 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1151 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1152 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1153 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1154 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1156 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1157 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1158 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1162 The following pseudo-ops from the Kane and Heinrich MIPS book
1163 should be defined here, but are currently unsupported: .alias,
1164 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1166 The following pseudo-ops from the Kane and Heinrich MIPS book are
1167 specific to the type of debugging information being generated, and
1168 should be defined by the object format: .aent, .begin, .bend,
1169 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1172 The following pseudo-ops from the Kane and Heinrich MIPS book are
1173 not MIPS CPU specific, but are also not specific to the object file
1174 format. This file is probably the best place to define them, but
1175 they are not currently supported: .asm0, .endr, .lab, .struct. */
1177 static const pseudo_typeS mips_pseudo_table[] =
1179 /* MIPS specific pseudo-ops. */
1180 {"option", s_option, 0},
1181 {"set", s_mipsset, 0},
1182 {"rdata", s_change_sec, 'r'},
1183 {"sdata", s_change_sec, 's'},
1184 {"livereg", s_ignore, 0},
1185 {"abicalls", s_abicalls, 0},
1186 {"cpload", s_cpload, 0},
1187 {"cpsetup", s_cpsetup, 0},
1188 {"cplocal", s_cplocal, 0},
1189 {"cprestore", s_cprestore, 0},
1190 {"cpreturn", s_cpreturn, 0},
1191 {"dtprelword", s_dtprelword, 0},
1192 {"dtpreldword", s_dtpreldword, 0},
1193 {"gpvalue", s_gpvalue, 0},
1194 {"gpword", s_gpword, 0},
1195 {"gpdword", s_gpdword, 0},
1196 {"cpadd", s_cpadd, 0},
1197 {"insn", s_insn, 0},
1199 /* Relatively generic pseudo-ops that happen to be used on MIPS
1201 {"asciiz", stringer, 8 + 1},
1202 {"bss", s_change_sec, 'b'},
1204 {"half", s_cons, 1},
1205 {"dword", s_cons, 3},
1206 {"weakext", s_mips_weakext, 0},
1207 {"origin", s_org, 0},
1208 {"repeat", s_rept, 0},
1210 /* For MIPS this is non-standard, but we define it for consistency. */
1211 {"sbss", s_change_sec, 'B'},
1213 /* These pseudo-ops are defined in read.c, but must be overridden
1214 here for one reason or another. */
1215 {"align", s_align, 0},
1216 {"byte", s_cons, 0},
1217 {"data", s_change_sec, 'd'},
1218 {"double", s_float_cons, 'd'},
1219 {"float", s_float_cons, 'f'},
1220 {"globl", s_mips_globl, 0},
1221 {"global", s_mips_globl, 0},
1222 {"hword", s_cons, 1},
1224 {"long", s_cons, 2},
1225 {"octa", s_cons, 4},
1226 {"quad", s_cons, 3},
1227 {"section", s_change_section, 0},
1228 {"short", s_cons, 1},
1229 {"single", s_float_cons, 'f'},
1230 {"stabn", s_mips_stab, 'n'},
1231 {"text", s_change_sec, 't'},
1232 {"word", s_cons, 2},
1234 { "extern", ecoff_directive_extern, 0},
1239 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1241 /* These pseudo-ops should be defined by the object file format.
1242 However, a.out doesn't support them, so we have versions here. */
1243 {"aent", s_mips_ent, 1},
1244 {"bgnb", s_ignore, 0},
1245 {"end", s_mips_end, 0},
1246 {"endb", s_ignore, 0},
1247 {"ent", s_mips_ent, 0},
1248 {"file", s_mips_file, 0},
1249 {"fmask", s_mips_mask, 'F'},
1250 {"frame", s_mips_frame, 0},
1251 {"loc", s_mips_loc, 0},
1252 {"mask", s_mips_mask, 'R'},
1253 {"verstamp", s_ignore, 0},
1257 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1258 purpose of the `.dc.a' internal pseudo-op. */
1261 mips_address_bytes (void)
1263 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1266 extern void pop_insert (const pseudo_typeS *);
1269 mips_pop_insert (void)
1271 pop_insert (mips_pseudo_table);
1272 if (! ECOFF_DEBUGGING)
1273 pop_insert (mips_nonecoff_pseudo_table);
1276 /* Symbols labelling the current insn. */
1278 struct insn_label_list
1280 struct insn_label_list *next;
1284 static struct insn_label_list *free_insn_labels;
1285 #define label_list tc_segment_info_data.labels
1287 static void mips_clear_insn_labels (void);
1290 mips_clear_insn_labels (void)
1292 register struct insn_label_list **pl;
1293 segment_info_type *si;
1297 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1300 si = seg_info (now_seg);
1301 *pl = si->label_list;
1302 si->label_list = NULL;
1307 static char *expr_end;
1309 /* Expressions which appear in instructions. These are set by
1312 static expressionS imm_expr;
1313 static expressionS imm2_expr;
1314 static expressionS offset_expr;
1316 /* Relocs associated with imm_expr and offset_expr. */
1318 static bfd_reloc_code_real_type imm_reloc[3]
1319 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1320 static bfd_reloc_code_real_type offset_reloc[3]
1321 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1323 /* These are set by mips16_ip if an explicit extension is used. */
1325 static bfd_boolean mips16_small, mips16_ext;
1328 /* The pdr segment for per procedure frame/regmask info. Not used for
1331 static segT pdr_seg;
1334 /* The default target format to use. */
1336 #if defined (TE_FreeBSD)
1337 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1338 #elif defined (TE_TMIPS)
1339 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1341 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1345 mips_target_format (void)
1347 switch (OUTPUT_FLAVOR)
1349 case bfd_target_ecoff_flavour:
1350 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1351 case bfd_target_coff_flavour:
1353 case bfd_target_elf_flavour:
1355 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1356 return (target_big_endian
1357 ? "elf32-bigmips-vxworks"
1358 : "elf32-littlemips-vxworks");
1360 return (target_big_endian
1361 ? (HAVE_64BIT_OBJECTS
1362 ? ELF_TARGET ("elf64-", "big")
1364 ? ELF_TARGET ("elf32-n", "big")
1365 : ELF_TARGET ("elf32-", "big")))
1366 : (HAVE_64BIT_OBJECTS
1367 ? ELF_TARGET ("elf64-", "little")
1369 ? ELF_TARGET ("elf32-n", "little")
1370 : ELF_TARGET ("elf32-", "little"))));
1377 /* Return the length of instruction INSN. */
1379 static inline unsigned int
1380 insn_length (const struct mips_cl_insn *insn)
1382 if (!mips_opts.mips16)
1384 return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2;
1387 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1390 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1395 insn->use_extend = FALSE;
1397 insn->insn_opcode = mo->match;
1400 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1401 insn->fixp[i] = NULL;
1402 insn->fixed_p = (mips_opts.noreorder > 0);
1403 insn->noreorder_p = (mips_opts.noreorder > 0);
1404 insn->mips16_absolute_jump_p = 0;
1405 insn->complete_p = 0;
1408 /* Record the current MIPS16 mode in now_seg. */
1411 mips_record_mips16_mode (void)
1413 segment_info_type *si;
1415 si = seg_info (now_seg);
1416 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
1417 si->tc_segment_info_data.mips16 = mips_opts.mips16;
1420 /* Install INSN at the location specified by its "frag" and "where" fields. */
1423 install_insn (const struct mips_cl_insn *insn)
1425 char *f = insn->frag->fr_literal + insn->where;
1426 if (!mips_opts.mips16)
1427 md_number_to_chars (f, insn->insn_opcode, 4);
1428 else if (insn->mips16_absolute_jump_p)
1430 md_number_to_chars (f, insn->insn_opcode >> 16, 2);
1431 md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2);
1435 if (insn->use_extend)
1437 md_number_to_chars (f, 0xf000 | insn->extend, 2);
1440 md_number_to_chars (f, insn->insn_opcode, 2);
1442 mips_record_mips16_mode ();
1445 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1446 and install the opcode in the new location. */
1449 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
1454 insn->where = where;
1455 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1456 if (insn->fixp[i] != NULL)
1458 insn->fixp[i]->fx_frag = frag;
1459 insn->fixp[i]->fx_where = where;
1461 install_insn (insn);
1464 /* Add INSN to the end of the output. */
1467 add_fixed_insn (struct mips_cl_insn *insn)
1469 char *f = frag_more (insn_length (insn));
1470 move_insn (insn, frag_now, f - frag_now->fr_literal);
1473 /* Start a variant frag and move INSN to the start of the variant part,
1474 marking it as fixed. The other arguments are as for frag_var. */
1477 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
1478 relax_substateT subtype, symbolS *symbol, offsetT offset)
1480 frag_grow (max_chars);
1481 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
1483 frag_var (rs_machine_dependent, max_chars, var,
1484 subtype, symbol, offset, NULL);
1487 /* Insert N copies of INSN into the history buffer, starting at
1488 position FIRST. Neither FIRST nor N need to be clipped. */
1491 insert_into_history (unsigned int first, unsigned int n,
1492 const struct mips_cl_insn *insn)
1494 if (mips_relax.sequence != 2)
1498 for (i = ARRAY_SIZE (history); i-- > first;)
1500 history[i] = history[i - n];
1506 /* Emit a nop instruction, recording it in the history buffer. */
1511 add_fixed_insn (NOP_INSN);
1512 insert_into_history (0, 1, NOP_INSN);
1515 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1516 the idea is to make it obvious at a glance that each errata is
1520 init_vr4120_conflicts (void)
1522 #define CONFLICT(FIRST, SECOND) \
1523 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1525 /* Errata 21 - [D]DIV[U] after [D]MACC */
1526 CONFLICT (MACC, DIV);
1527 CONFLICT (DMACC, DIV);
1529 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1530 CONFLICT (DMULT, DMULT);
1531 CONFLICT (DMULT, DMACC);
1532 CONFLICT (DMACC, DMULT);
1533 CONFLICT (DMACC, DMACC);
1535 /* Errata 24 - MT{LO,HI} after [D]MACC */
1536 CONFLICT (MACC, MTHILO);
1537 CONFLICT (DMACC, MTHILO);
1539 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1540 instruction is executed immediately after a MACC or DMACC
1541 instruction, the result of [either instruction] is incorrect." */
1542 CONFLICT (MACC, MULT);
1543 CONFLICT (MACC, DMULT);
1544 CONFLICT (DMACC, MULT);
1545 CONFLICT (DMACC, DMULT);
1547 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1548 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1549 DDIV or DDIVU instruction, the result of the MACC or
1550 DMACC instruction is incorrect.". */
1551 CONFLICT (DMULT, MACC);
1552 CONFLICT (DMULT, DMACC);
1553 CONFLICT (DIV, MACC);
1554 CONFLICT (DIV, DMACC);
1564 #define RTYPE_MASK 0x1ff00
1565 #define RTYPE_NUM 0x00100
1566 #define RTYPE_FPU 0x00200
1567 #define RTYPE_FCC 0x00400
1568 #define RTYPE_VEC 0x00800
1569 #define RTYPE_GP 0x01000
1570 #define RTYPE_CP0 0x02000
1571 #define RTYPE_PC 0x04000
1572 #define RTYPE_ACC 0x08000
1573 #define RTYPE_CCC 0x10000
1574 #define RNUM_MASK 0x000ff
1575 #define RWARN 0x80000
1577 #define GENERIC_REGISTER_NUMBERS \
1578 {"$0", RTYPE_NUM | 0}, \
1579 {"$1", RTYPE_NUM | 1}, \
1580 {"$2", RTYPE_NUM | 2}, \
1581 {"$3", RTYPE_NUM | 3}, \
1582 {"$4", RTYPE_NUM | 4}, \
1583 {"$5", RTYPE_NUM | 5}, \
1584 {"$6", RTYPE_NUM | 6}, \
1585 {"$7", RTYPE_NUM | 7}, \
1586 {"$8", RTYPE_NUM | 8}, \
1587 {"$9", RTYPE_NUM | 9}, \
1588 {"$10", RTYPE_NUM | 10}, \
1589 {"$11", RTYPE_NUM | 11}, \
1590 {"$12", RTYPE_NUM | 12}, \
1591 {"$13", RTYPE_NUM | 13}, \
1592 {"$14", RTYPE_NUM | 14}, \
1593 {"$15", RTYPE_NUM | 15}, \
1594 {"$16", RTYPE_NUM | 16}, \
1595 {"$17", RTYPE_NUM | 17}, \
1596 {"$18", RTYPE_NUM | 18}, \
1597 {"$19", RTYPE_NUM | 19}, \
1598 {"$20", RTYPE_NUM | 20}, \
1599 {"$21", RTYPE_NUM | 21}, \
1600 {"$22", RTYPE_NUM | 22}, \
1601 {"$23", RTYPE_NUM | 23}, \
1602 {"$24", RTYPE_NUM | 24}, \
1603 {"$25", RTYPE_NUM | 25}, \
1604 {"$26", RTYPE_NUM | 26}, \
1605 {"$27", RTYPE_NUM | 27}, \
1606 {"$28", RTYPE_NUM | 28}, \
1607 {"$29", RTYPE_NUM | 29}, \
1608 {"$30", RTYPE_NUM | 30}, \
1609 {"$31", RTYPE_NUM | 31}
1611 #define FPU_REGISTER_NAMES \
1612 {"$f0", RTYPE_FPU | 0}, \
1613 {"$f1", RTYPE_FPU | 1}, \
1614 {"$f2", RTYPE_FPU | 2}, \
1615 {"$f3", RTYPE_FPU | 3}, \
1616 {"$f4", RTYPE_FPU | 4}, \
1617 {"$f5", RTYPE_FPU | 5}, \
1618 {"$f6", RTYPE_FPU | 6}, \
1619 {"$f7", RTYPE_FPU | 7}, \
1620 {"$f8", RTYPE_FPU | 8}, \
1621 {"$f9", RTYPE_FPU | 9}, \
1622 {"$f10", RTYPE_FPU | 10}, \
1623 {"$f11", RTYPE_FPU | 11}, \
1624 {"$f12", RTYPE_FPU | 12}, \
1625 {"$f13", RTYPE_FPU | 13}, \
1626 {"$f14", RTYPE_FPU | 14}, \
1627 {"$f15", RTYPE_FPU | 15}, \
1628 {"$f16", RTYPE_FPU | 16}, \
1629 {"$f17", RTYPE_FPU | 17}, \
1630 {"$f18", RTYPE_FPU | 18}, \
1631 {"$f19", RTYPE_FPU | 19}, \
1632 {"$f20", RTYPE_FPU | 20}, \
1633 {"$f21", RTYPE_FPU | 21}, \
1634 {"$f22", RTYPE_FPU | 22}, \
1635 {"$f23", RTYPE_FPU | 23}, \
1636 {"$f24", RTYPE_FPU | 24}, \
1637 {"$f25", RTYPE_FPU | 25}, \
1638 {"$f26", RTYPE_FPU | 26}, \
1639 {"$f27", RTYPE_FPU | 27}, \
1640 {"$f28", RTYPE_FPU | 28}, \
1641 {"$f29", RTYPE_FPU | 29}, \
1642 {"$f30", RTYPE_FPU | 30}, \
1643 {"$f31", RTYPE_FPU | 31}
1645 #define FPU_CONDITION_CODE_NAMES \
1646 {"$fcc0", RTYPE_FCC | 0}, \
1647 {"$fcc1", RTYPE_FCC | 1}, \
1648 {"$fcc2", RTYPE_FCC | 2}, \
1649 {"$fcc3", RTYPE_FCC | 3}, \
1650 {"$fcc4", RTYPE_FCC | 4}, \
1651 {"$fcc5", RTYPE_FCC | 5}, \
1652 {"$fcc6", RTYPE_FCC | 6}, \
1653 {"$fcc7", RTYPE_FCC | 7}
1655 #define COPROC_CONDITION_CODE_NAMES \
1656 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1657 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1658 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1659 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1660 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1661 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1662 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1663 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1665 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1666 {"$a4", RTYPE_GP | 8}, \
1667 {"$a5", RTYPE_GP | 9}, \
1668 {"$a6", RTYPE_GP | 10}, \
1669 {"$a7", RTYPE_GP | 11}, \
1670 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1671 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1672 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1673 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1674 {"$t0", RTYPE_GP | 12}, \
1675 {"$t1", RTYPE_GP | 13}, \
1676 {"$t2", RTYPE_GP | 14}, \
1677 {"$t3", RTYPE_GP | 15}
1679 #define O32_SYMBOLIC_REGISTER_NAMES \
1680 {"$t0", RTYPE_GP | 8}, \
1681 {"$t1", RTYPE_GP | 9}, \
1682 {"$t2", RTYPE_GP | 10}, \
1683 {"$t3", RTYPE_GP | 11}, \
1684 {"$t4", RTYPE_GP | 12}, \
1685 {"$t5", RTYPE_GP | 13}, \
1686 {"$t6", RTYPE_GP | 14}, \
1687 {"$t7", RTYPE_GP | 15}, \
1688 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1689 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1690 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1691 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1693 /* Remaining symbolic register names */
1694 #define SYMBOLIC_REGISTER_NAMES \
1695 {"$zero", RTYPE_GP | 0}, \
1696 {"$at", RTYPE_GP | 1}, \
1697 {"$AT", RTYPE_GP | 1}, \
1698 {"$v0", RTYPE_GP | 2}, \
1699 {"$v1", RTYPE_GP | 3}, \
1700 {"$a0", RTYPE_GP | 4}, \
1701 {"$a1", RTYPE_GP | 5}, \
1702 {"$a2", RTYPE_GP | 6}, \
1703 {"$a3", RTYPE_GP | 7}, \
1704 {"$s0", RTYPE_GP | 16}, \
1705 {"$s1", RTYPE_GP | 17}, \
1706 {"$s2", RTYPE_GP | 18}, \
1707 {"$s3", RTYPE_GP | 19}, \
1708 {"$s4", RTYPE_GP | 20}, \
1709 {"$s5", RTYPE_GP | 21}, \
1710 {"$s6", RTYPE_GP | 22}, \
1711 {"$s7", RTYPE_GP | 23}, \
1712 {"$t8", RTYPE_GP | 24}, \
1713 {"$t9", RTYPE_GP | 25}, \
1714 {"$k0", RTYPE_GP | 26}, \
1715 {"$kt0", RTYPE_GP | 26}, \
1716 {"$k1", RTYPE_GP | 27}, \
1717 {"$kt1", RTYPE_GP | 27}, \
1718 {"$gp", RTYPE_GP | 28}, \
1719 {"$sp", RTYPE_GP | 29}, \
1720 {"$s8", RTYPE_GP | 30}, \
1721 {"$fp", RTYPE_GP | 30}, \
1722 {"$ra", RTYPE_GP | 31}
1724 #define MIPS16_SPECIAL_REGISTER_NAMES \
1725 {"$pc", RTYPE_PC | 0}
1727 #define MDMX_VECTOR_REGISTER_NAMES \
1728 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
1729 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
1730 {"$v2", RTYPE_VEC | 2}, \
1731 {"$v3", RTYPE_VEC | 3}, \
1732 {"$v4", RTYPE_VEC | 4}, \
1733 {"$v5", RTYPE_VEC | 5}, \
1734 {"$v6", RTYPE_VEC | 6}, \
1735 {"$v7", RTYPE_VEC | 7}, \
1736 {"$v8", RTYPE_VEC | 8}, \
1737 {"$v9", RTYPE_VEC | 9}, \
1738 {"$v10", RTYPE_VEC | 10}, \
1739 {"$v11", RTYPE_VEC | 11}, \
1740 {"$v12", RTYPE_VEC | 12}, \
1741 {"$v13", RTYPE_VEC | 13}, \
1742 {"$v14", RTYPE_VEC | 14}, \
1743 {"$v15", RTYPE_VEC | 15}, \
1744 {"$v16", RTYPE_VEC | 16}, \
1745 {"$v17", RTYPE_VEC | 17}, \
1746 {"$v18", RTYPE_VEC | 18}, \
1747 {"$v19", RTYPE_VEC | 19}, \
1748 {"$v20", RTYPE_VEC | 20}, \
1749 {"$v21", RTYPE_VEC | 21}, \
1750 {"$v22", RTYPE_VEC | 22}, \
1751 {"$v23", RTYPE_VEC | 23}, \
1752 {"$v24", RTYPE_VEC | 24}, \
1753 {"$v25", RTYPE_VEC | 25}, \
1754 {"$v26", RTYPE_VEC | 26}, \
1755 {"$v27", RTYPE_VEC | 27}, \
1756 {"$v28", RTYPE_VEC | 28}, \
1757 {"$v29", RTYPE_VEC | 29}, \
1758 {"$v30", RTYPE_VEC | 30}, \
1759 {"$v31", RTYPE_VEC | 31}
1761 #define MIPS_DSP_ACCUMULATOR_NAMES \
1762 {"$ac0", RTYPE_ACC | 0}, \
1763 {"$ac1", RTYPE_ACC | 1}, \
1764 {"$ac2", RTYPE_ACC | 2}, \
1765 {"$ac3", RTYPE_ACC | 3}
1767 static const struct regname reg_names[] = {
1768 GENERIC_REGISTER_NUMBERS,
1770 FPU_CONDITION_CODE_NAMES,
1771 COPROC_CONDITION_CODE_NAMES,
1773 /* The $txx registers depends on the abi,
1774 these will be added later into the symbol table from
1775 one of the tables below once mips_abi is set after
1776 parsing of arguments from the command line. */
1777 SYMBOLIC_REGISTER_NAMES,
1779 MIPS16_SPECIAL_REGISTER_NAMES,
1780 MDMX_VECTOR_REGISTER_NAMES,
1781 MIPS_DSP_ACCUMULATOR_NAMES,
1785 static const struct regname reg_names_o32[] = {
1786 O32_SYMBOLIC_REGISTER_NAMES,
1790 static const struct regname reg_names_n32n64[] = {
1791 N32N64_SYMBOLIC_REGISTER_NAMES,
1796 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
1803 /* Find end of name. */
1805 if (is_name_beginner (*e))
1807 while (is_part_of_name (*e))
1810 /* Terminate name. */
1814 /* Look for a register symbol. */
1815 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
1817 int r = S_GET_VALUE (symbolP);
1819 reg = r & RNUM_MASK;
1820 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
1821 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
1822 reg = (r & RNUM_MASK) - 2;
1824 /* Else see if this is a register defined in an itbl entry. */
1825 else if ((types & RTYPE_GP) && itbl_have_entries)
1832 if (itbl_get_reg_val (n, &r))
1833 reg = r & RNUM_MASK;
1836 /* Advance to next token if a register was recognised. */
1839 else if (types & RWARN)
1840 as_warn (_("Unrecognized register name `%s'"), *s);
1848 /* Return TRUE if opcode MO is valid on the currently selected ISA and
1849 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
1852 is_opcode_valid (const struct mips_opcode *mo)
1854 int isa = mips_opts.isa;
1857 if (mips_opts.ase_mdmx)
1859 if (mips_opts.ase_dsp)
1861 if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
1863 if (mips_opts.ase_dspr2)
1865 if (mips_opts.ase_mt)
1867 if (mips_opts.ase_mips3d)
1869 if (mips_opts.ase_smartmips)
1870 isa |= INSN_SMARTMIPS;
1872 /* Don't accept instructions based on the ISA if the CPU does not implement
1873 all the coprocessor insns. */
1874 if (NO_ISA_COP (mips_opts.arch)
1875 && COP_INSN (mo->pinfo))
1878 if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch))
1881 /* Check whether the instruction or macro requires single-precision or
1882 double-precision floating-point support. Note that this information is
1883 stored differently in the opcode table for insns and macros. */
1884 if (mo->pinfo == INSN_MACRO)
1886 fp_s = mo->pinfo2 & INSN2_M_FP_S;
1887 fp_d = mo->pinfo2 & INSN2_M_FP_D;
1891 fp_s = mo->pinfo & FP_S;
1892 fp_d = mo->pinfo & FP_D;
1895 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
1898 if (fp_s && mips_opts.soft_float)
1904 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
1905 selected ISA and architecture. */
1908 is_opcode_valid_16 (const struct mips_opcode *mo)
1910 return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE;
1913 /* This function is called once, at assembler startup time. It should set up
1914 all the tables, etc. that the MD part of the assembler will need. */
1919 const char *retval = NULL;
1923 if (mips_pic != NO_PIC)
1925 if (g_switch_seen && g_switch_value != 0)
1926 as_bad (_("-G may not be used in position-independent code"));
1930 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
1931 as_warn (_("Could not set architecture and machine"));
1933 op_hash = hash_new ();
1935 for (i = 0; i < NUMOPCODES;)
1937 const char *name = mips_opcodes[i].name;
1939 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
1942 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1943 mips_opcodes[i].name, retval);
1944 /* Probably a memory allocation problem? Give up now. */
1945 as_fatal (_("Broken assembler. No assembly attempted."));
1949 if (mips_opcodes[i].pinfo != INSN_MACRO)
1951 if (!validate_mips_insn (&mips_opcodes[i]))
1953 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
1955 create_insn (&nop_insn, mips_opcodes + i);
1956 if (mips_fix_loongson2f_nop)
1957 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
1958 nop_insn.fixed_p = 1;
1963 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1966 mips16_op_hash = hash_new ();
1969 while (i < bfd_mips16_num_opcodes)
1971 const char *name = mips16_opcodes[i].name;
1973 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
1975 as_fatal (_("internal: can't hash `%s': %s"),
1976 mips16_opcodes[i].name, retval);
1979 if (mips16_opcodes[i].pinfo != INSN_MACRO
1980 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1981 != mips16_opcodes[i].match))
1983 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1984 mips16_opcodes[i].name, mips16_opcodes[i].args);
1987 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
1989 create_insn (&mips16_nop_insn, mips16_opcodes + i);
1990 mips16_nop_insn.fixed_p = 1;
1994 while (i < bfd_mips16_num_opcodes
1995 && strcmp (mips16_opcodes[i].name, name) == 0);
1999 as_fatal (_("Broken assembler. No assembly attempted."));
2001 /* We add all the general register names to the symbol table. This
2002 helps us detect invalid uses of them. */
2003 for (i = 0; reg_names[i].name; i++)
2004 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
2005 reg_names[i].num, /* & RNUM_MASK, */
2006 &zero_address_frag));
2008 for (i = 0; reg_names_n32n64[i].name; i++)
2009 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
2010 reg_names_n32n64[i].num, /* & RNUM_MASK, */
2011 &zero_address_frag));
2013 for (i = 0; reg_names_o32[i].name; i++)
2014 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
2015 reg_names_o32[i].num, /* & RNUM_MASK, */
2016 &zero_address_frag));
2018 mips_no_prev_insn ();
2021 mips_cprmask[0] = 0;
2022 mips_cprmask[1] = 0;
2023 mips_cprmask[2] = 0;
2024 mips_cprmask[3] = 0;
2026 /* set the default alignment for the text section (2**2) */
2027 record_alignment (text_section, 2);
2029 bfd_set_gp_size (stdoutput, g_switch_value);
2034 /* On a native system other than VxWorks, sections must be aligned
2035 to 16 byte boundaries. When configured for an embedded ELF
2036 target, we don't bother. */
2037 if (strncmp (TARGET_OS, "elf", 3) != 0
2038 && strncmp (TARGET_OS, "vxworks", 7) != 0)
2040 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
2041 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
2042 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
2045 /* Create a .reginfo section for register masks and a .mdebug
2046 section for debugging information. */
2054 subseg = now_subseg;
2056 /* The ABI says this section should be loaded so that the
2057 running program can access it. However, we don't load it
2058 if we are configured for an embedded target */
2059 flags = SEC_READONLY | SEC_DATA;
2060 if (strncmp (TARGET_OS, "elf", 3) != 0)
2061 flags |= SEC_ALLOC | SEC_LOAD;
2063 if (mips_abi != N64_ABI)
2065 sec = subseg_new (".reginfo", (subsegT) 0);
2067 bfd_set_section_flags (stdoutput, sec, flags);
2068 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
2070 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
2074 /* The 64-bit ABI uses a .MIPS.options section rather than
2075 .reginfo section. */
2076 sec = subseg_new (".MIPS.options", (subsegT) 0);
2077 bfd_set_section_flags (stdoutput, sec, flags);
2078 bfd_set_section_alignment (stdoutput, sec, 3);
2080 /* Set up the option header. */
2082 Elf_Internal_Options opthdr;
2085 opthdr.kind = ODK_REGINFO;
2086 opthdr.size = (sizeof (Elf_External_Options)
2087 + sizeof (Elf64_External_RegInfo));
2090 f = frag_more (sizeof (Elf_External_Options));
2091 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2092 (Elf_External_Options *) f);
2094 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2098 if (ECOFF_DEBUGGING)
2100 sec = subseg_new (".mdebug", (subsegT) 0);
2101 (void) bfd_set_section_flags (stdoutput, sec,
2102 SEC_HAS_CONTENTS | SEC_READONLY);
2103 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2105 else if (mips_flag_pdr)
2107 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2108 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2109 SEC_READONLY | SEC_RELOC
2111 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2114 subseg_set (seg, subseg);
2117 #endif /* OBJ_ELF */
2119 if (! ECOFF_DEBUGGING)
2122 if (mips_fix_vr4120)
2123 init_vr4120_conflicts ();
2129 mips_emit_delays ();
2130 if (! ECOFF_DEBUGGING)
2135 md_assemble (char *str)
2137 struct mips_cl_insn insn;
2138 bfd_reloc_code_real_type unused_reloc[3]
2139 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2141 imm_expr.X_op = O_absent;
2142 imm2_expr.X_op = O_absent;
2143 offset_expr.X_op = O_absent;
2144 imm_reloc[0] = BFD_RELOC_UNUSED;
2145 imm_reloc[1] = BFD_RELOC_UNUSED;
2146 imm_reloc[2] = BFD_RELOC_UNUSED;
2147 offset_reloc[0] = BFD_RELOC_UNUSED;
2148 offset_reloc[1] = BFD_RELOC_UNUSED;
2149 offset_reloc[2] = BFD_RELOC_UNUSED;
2151 if (mips_opts.mips16)
2152 mips16_ip (str, &insn);
2155 mips_ip (str, &insn);
2156 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2157 str, insn.insn_opcode));
2162 as_bad ("%s `%s'", insn_error, str);
2166 if (insn.insn_mo->pinfo == INSN_MACRO)
2169 if (mips_opts.mips16)
2170 mips16_macro (&insn);
2177 if (imm_expr.X_op != O_absent)
2178 append_insn (&insn, &imm_expr, imm_reloc);
2179 else if (offset_expr.X_op != O_absent)
2180 append_insn (&insn, &offset_expr, offset_reloc);
2182 append_insn (&insn, NULL, unused_reloc);
2186 /* Convenience functions for abstracting away the differences between
2187 MIPS16 and non-MIPS16 relocations. */
2189 static inline bfd_boolean
2190 mips16_reloc_p (bfd_reloc_code_real_type reloc)
2194 case BFD_RELOC_MIPS16_JMP:
2195 case BFD_RELOC_MIPS16_GPREL:
2196 case BFD_RELOC_MIPS16_GOT16:
2197 case BFD_RELOC_MIPS16_CALL16:
2198 case BFD_RELOC_MIPS16_HI16_S:
2199 case BFD_RELOC_MIPS16_HI16:
2200 case BFD_RELOC_MIPS16_LO16:
2208 static inline bfd_boolean
2209 got16_reloc_p (bfd_reloc_code_real_type reloc)
2211 return reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16;
2214 static inline bfd_boolean
2215 hi16_reloc_p (bfd_reloc_code_real_type reloc)
2217 return reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S;
2220 static inline bfd_boolean
2221 lo16_reloc_p (bfd_reloc_code_real_type reloc)
2223 return reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16;
2226 /* Return true if the given relocation might need a matching %lo().
2227 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2228 need a matching %lo() when applied to local symbols. */
2230 static inline bfd_boolean
2231 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
2233 return (HAVE_IN_PLACE_ADDENDS
2234 && (hi16_reloc_p (reloc)
2235 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2236 all GOT16 relocations evaluate to "G". */
2237 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
2240 /* Return the type of %lo() reloc needed by RELOC, given that
2241 reloc_needs_lo_p. */
2243 static inline bfd_reloc_code_real_type
2244 matching_lo_reloc (bfd_reloc_code_real_type reloc)
2246 return mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 : BFD_RELOC_LO16;
2249 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2252 static inline bfd_boolean
2253 fixup_has_matching_lo_p (fixS *fixp)
2255 return (fixp->fx_next != NULL
2256 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
2257 && fixp->fx_addsy == fixp->fx_next->fx_addsy
2258 && fixp->fx_offset == fixp->fx_next->fx_offset);
2261 /* This function returns true if modifying a register requires a
2265 reg_needs_delay (unsigned int reg)
2267 unsigned long prev_pinfo;
2269 prev_pinfo = history[0].insn_mo->pinfo;
2270 if (! mips_opts.noreorder
2271 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2272 && ! gpr_interlocks)
2273 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
2274 && ! cop_interlocks)))
2276 /* A load from a coprocessor or from memory. All load delays
2277 delay the use of general register rt for one instruction. */
2278 /* Itbl support may require additional care here. */
2279 know (prev_pinfo & INSN_WRITE_GPR_T);
2280 if (reg == EXTRACT_OPERAND (RT, history[0]))
2287 /* Move all labels in insn_labels to the current insertion point. */
2290 mips_move_labels (void)
2292 segment_info_type *si = seg_info (now_seg);
2293 struct insn_label_list *l;
2296 for (l = si->label_list; l != NULL; l = l->next)
2298 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
2299 symbol_set_frag (l->label, frag_now);
2300 val = (valueT) frag_now_fix ();
2301 /* mips16 text labels are stored as odd. */
2302 if (mips_opts.mips16)
2304 S_SET_VALUE (l->label, val);
2309 s_is_linkonce (symbolS *sym, segT from_seg)
2311 bfd_boolean linkonce = FALSE;
2312 segT symseg = S_GET_SEGMENT (sym);
2314 if (symseg != from_seg && !S_IS_LOCAL (sym))
2316 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
2319 /* The GNU toolchain uses an extension for ELF: a section
2320 beginning with the magic string .gnu.linkonce is a
2321 linkonce section. */
2322 if (strncmp (segment_name (symseg), ".gnu.linkonce",
2323 sizeof ".gnu.linkonce" - 1) == 0)
2330 /* Mark instruction labels in mips16 mode. This permits the linker to
2331 handle them specially, such as generating jalx instructions when
2332 needed. We also make them odd for the duration of the assembly, in
2333 order to generate the right sort of code. We will make them even
2334 in the adjust_symtab routine, while leaving them marked. This is
2335 convenient for the debugger and the disassembler. The linker knows
2336 to make them odd again. */
2339 mips16_mark_labels (void)
2341 segment_info_type *si = seg_info (now_seg);
2342 struct insn_label_list *l;
2344 if (!mips_opts.mips16)
2347 for (l = si->label_list; l != NULL; l = l->next)
2349 symbolS *label = l->label;
2351 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2353 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
2355 if ((S_GET_VALUE (label) & 1) == 0
2356 /* Don't adjust the address if the label is global or weak, or
2357 in a link-once section, since we'll be emitting symbol reloc
2358 references to it which will be patched up by the linker, and
2359 the final value of the symbol may or may not be MIPS16. */
2360 && ! S_IS_WEAK (label)
2361 && ! S_IS_EXTERNAL (label)
2362 && ! s_is_linkonce (label, now_seg))
2363 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
2367 /* End the current frag. Make it a variant frag and record the
2371 relax_close_frag (void)
2373 mips_macro_warning.first_frag = frag_now;
2374 frag_var (rs_machine_dependent, 0, 0,
2375 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
2376 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
2378 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
2379 mips_relax.first_fixup = 0;
2382 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2383 See the comment above RELAX_ENCODE for more details. */
2386 relax_start (symbolS *symbol)
2388 gas_assert (mips_relax.sequence == 0);
2389 mips_relax.sequence = 1;
2390 mips_relax.symbol = symbol;
2393 /* Start generating the second version of a relaxable sequence.
2394 See the comment above RELAX_ENCODE for more details. */
2399 gas_assert (mips_relax.sequence == 1);
2400 mips_relax.sequence = 2;
2403 /* End the current relaxable sequence. */
2408 gas_assert (mips_relax.sequence == 2);
2409 relax_close_frag ();
2410 mips_relax.sequence = 0;
2413 /* Return the mask of core registers that IP reads. */
2416 gpr_read_mask (const struct mips_cl_insn *ip)
2418 unsigned long pinfo, pinfo2;
2422 pinfo = ip->insn_mo->pinfo;
2423 pinfo2 = ip->insn_mo->pinfo2;
2424 if (mips_opts.mips16)
2426 if (pinfo & MIPS16_INSN_READ_X)
2427 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
2428 if (pinfo & MIPS16_INSN_READ_Y)
2429 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
2430 if (pinfo & MIPS16_INSN_READ_T)
2432 if (pinfo & MIPS16_INSN_READ_SP)
2434 if (pinfo & MIPS16_INSN_READ_31)
2436 if (pinfo & MIPS16_INSN_READ_Z)
2437 mask |= 1 << (mips16_to_32_reg_map
2438 [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]);
2439 if (pinfo & MIPS16_INSN_READ_GPR_X)
2440 mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
2444 if (pinfo2 & INSN2_READ_GPR_D)
2445 mask |= 1 << EXTRACT_OPERAND (RD, *ip);
2446 if (pinfo & INSN_READ_GPR_T)
2447 mask |= 1 << EXTRACT_OPERAND (RT, *ip);
2448 if (pinfo & INSN_READ_GPR_S)
2449 mask |= 1 << EXTRACT_OPERAND (RS, *ip);
2450 if (pinfo2 & INSN2_READ_GPR_Z)
2451 mask |= 1 << EXTRACT_OPERAND (RZ, *ip);
2456 /* Return the mask of core registers that IP writes. */
2459 gpr_write_mask (const struct mips_cl_insn *ip)
2461 unsigned long pinfo, pinfo2;
2465 pinfo = ip->insn_mo->pinfo;
2466 pinfo2 = ip->insn_mo->pinfo2;
2467 if (mips_opts.mips16)
2469 if (pinfo & MIPS16_INSN_WRITE_X)
2470 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
2471 if (pinfo & MIPS16_INSN_WRITE_Y)
2472 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
2473 if (pinfo & MIPS16_INSN_WRITE_Z)
2474 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)];
2475 if (pinfo & MIPS16_INSN_WRITE_T)
2477 if (pinfo & MIPS16_INSN_WRITE_SP)
2479 if (pinfo & MIPS16_INSN_WRITE_31)
2481 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2482 mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2486 if (pinfo & INSN_WRITE_GPR_D)
2487 mask |= 1 << EXTRACT_OPERAND (RD, *ip);
2488 if (pinfo & INSN_WRITE_GPR_T)
2489 mask |= 1 << EXTRACT_OPERAND (RT, *ip);
2490 if (pinfo & INSN_WRITE_GPR_31)
2492 if (pinfo2 & INSN2_WRITE_GPR_Z)
2493 mask |= 1 << EXTRACT_OPERAND (RZ, *ip);
2498 /* Return the mask of floating-point registers that IP reads. */
2501 fpr_read_mask (const struct mips_cl_insn *ip)
2503 unsigned long pinfo, pinfo2;
2507 pinfo = ip->insn_mo->pinfo;
2508 pinfo2 = ip->insn_mo->pinfo2;
2509 if (!mips_opts.mips16)
2511 if (pinfo & INSN_READ_FPR_S)
2512 mask |= 1 << EXTRACT_OPERAND (FS, *ip);
2513 if (pinfo & INSN_READ_FPR_T)
2514 mask |= 1 << EXTRACT_OPERAND (FT, *ip);
2515 if (pinfo & INSN_READ_FPR_R)
2516 mask |= 1 << EXTRACT_OPERAND (FR, *ip);
2517 if (pinfo2 & INSN2_READ_FPR_Z)
2518 mask |= 1 << EXTRACT_OPERAND (FZ, *ip);
2520 /* Conservatively treat all operands to an FP_D instruction are doubles.
2521 (This is overly pessimistic for things like cvt.d.s.) */
2522 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
2527 /* Return the mask of floating-point registers that IP writes. */
2530 fpr_write_mask (const struct mips_cl_insn *ip)
2532 unsigned long pinfo, pinfo2;
2536 pinfo = ip->insn_mo->pinfo;
2537 pinfo2 = ip->insn_mo->pinfo2;
2538 if (!mips_opts.mips16)
2540 if (pinfo & INSN_WRITE_FPR_D)
2541 mask |= 1 << EXTRACT_OPERAND (FD, *ip);
2542 if (pinfo & INSN_WRITE_FPR_S)
2543 mask |= 1 << EXTRACT_OPERAND (FS, *ip);
2544 if (pinfo & INSN_WRITE_FPR_T)
2545 mask |= 1 << EXTRACT_OPERAND (FT, *ip);
2546 if (pinfo2 & INSN2_WRITE_FPR_Z)
2547 mask |= 1 << EXTRACT_OPERAND (FZ, *ip);
2549 /* Conservatively treat all operands to an FP_D instruction are doubles.
2550 (This is overly pessimistic for things like cvt.s.d.) */
2551 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
2556 /* Classify an instruction according to the FIX_VR4120_* enumeration.
2557 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
2558 by VR4120 errata. */
2561 classify_vr4120_insn (const char *name)
2563 if (strncmp (name, "macc", 4) == 0)
2564 return FIX_VR4120_MACC;
2565 if (strncmp (name, "dmacc", 5) == 0)
2566 return FIX_VR4120_DMACC;
2567 if (strncmp (name, "mult", 4) == 0)
2568 return FIX_VR4120_MULT;
2569 if (strncmp (name, "dmult", 5) == 0)
2570 return FIX_VR4120_DMULT;
2571 if (strstr (name, "div"))
2572 return FIX_VR4120_DIV;
2573 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
2574 return FIX_VR4120_MTHILO;
2575 return NUM_FIX_VR4120_CLASSES;
2578 #define INSN_ERET 0x42000018
2579 #define INSN_DERET 0x4200001f
2581 /* Return the number of instructions that must separate INSN1 and INSN2,
2582 where INSN1 is the earlier instruction. Return the worst-case value
2583 for any INSN2 if INSN2 is null. */
2586 insns_between (const struct mips_cl_insn *insn1,
2587 const struct mips_cl_insn *insn2)
2589 unsigned long pinfo1, pinfo2;
2592 /* This function needs to know which pinfo flags are set for INSN2
2593 and which registers INSN2 uses. The former is stored in PINFO2 and
2594 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
2595 will have every flag set and INSN2_USES_GPR will always return true. */
2596 pinfo1 = insn1->insn_mo->pinfo;
2597 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
2599 #define INSN2_USES_GPR(REG) \
2600 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
2602 /* For most targets, write-after-read dependencies on the HI and LO
2603 registers must be separated by at least two instructions. */
2604 if (!hilo_interlocks)
2606 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
2608 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
2612 /* If we're working around r7000 errata, there must be two instructions
2613 between an mfhi or mflo and any instruction that uses the result. */
2614 if (mips_7000_hilo_fix
2615 && MF_HILO_INSN (pinfo1)
2616 && INSN2_USES_GPR (EXTRACT_OPERAND (RD, *insn1)))
2619 /* If we're working around 24K errata, one instruction is required
2620 if an ERET or DERET is followed by a branch instruction. */
2623 if (insn1->insn_opcode == INSN_ERET
2624 || insn1->insn_opcode == INSN_DERET)
2627 || insn2->insn_opcode == INSN_ERET
2628 || insn2->insn_opcode == INSN_DERET
2629 || (insn2->insn_mo->pinfo
2630 & (INSN_UNCOND_BRANCH_DELAY
2631 | INSN_COND_BRANCH_DELAY
2632 | INSN_COND_BRANCH_LIKELY)) != 0)
2637 /* If working around VR4120 errata, check for combinations that need
2638 a single intervening instruction. */
2639 if (mips_fix_vr4120)
2641 unsigned int class1, class2;
2643 class1 = classify_vr4120_insn (insn1->insn_mo->name);
2644 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
2648 class2 = classify_vr4120_insn (insn2->insn_mo->name);
2649 if (vr4120_conflicts[class1] & (1 << class2))
2654 if (!mips_opts.mips16)
2656 /* Check for GPR or coprocessor load delays. All such delays
2657 are on the RT register. */
2658 /* Itbl support may require additional care here. */
2659 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
2660 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
2662 know (pinfo1 & INSN_WRITE_GPR_T);
2663 if (INSN2_USES_GPR (EXTRACT_OPERAND (RT, *insn1)))
2667 /* Check for generic coprocessor hazards.
2669 This case is not handled very well. There is no special
2670 knowledge of CP0 handling, and the coprocessors other than
2671 the floating point unit are not distinguished at all. */
2672 /* Itbl support may require additional care here. FIXME!
2673 Need to modify this to include knowledge about
2674 user specified delays! */
2675 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
2676 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
2678 /* Handle cases where INSN1 writes to a known general coprocessor
2679 register. There must be a one instruction delay before INSN2
2680 if INSN2 reads that register, otherwise no delay is needed. */
2681 mask = fpr_write_mask (insn1);
2684 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
2689 /* Read-after-write dependencies on the control registers
2690 require a two-instruction gap. */
2691 if ((pinfo1 & INSN_WRITE_COND_CODE)
2692 && (pinfo2 & INSN_READ_COND_CODE))
2695 /* We don't know exactly what INSN1 does. If INSN2 is
2696 also a coprocessor instruction, assume there must be
2697 a one instruction gap. */
2698 if (pinfo2 & INSN_COP)
2703 /* Check for read-after-write dependencies on the coprocessor
2704 control registers in cases where INSN1 does not need a general
2705 coprocessor delay. This means that INSN1 is a floating point
2706 comparison instruction. */
2707 /* Itbl support may require additional care here. */
2708 else if (!cop_interlocks
2709 && (pinfo1 & INSN_WRITE_COND_CODE)
2710 && (pinfo2 & INSN_READ_COND_CODE))
2714 #undef INSN2_USES_GPR
2719 /* Return the number of nops that would be needed to work around the
2720 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2721 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
2722 that are contained within the first IGNORE instructions of HIST. */
2725 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
2726 const struct mips_cl_insn *insn)
2731 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2732 are not affected by the errata. */
2734 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
2735 || strcmp (insn->insn_mo->name, "mtlo") == 0
2736 || strcmp (insn->insn_mo->name, "mthi") == 0))
2739 /* Search for the first MFLO or MFHI. */
2740 for (i = 0; i < MAX_VR4130_NOPS; i++)
2741 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
2743 /* Extract the destination register. */
2744 mask = gpr_write_mask (&hist[i]);
2746 /* No nops are needed if INSN reads that register. */
2747 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
2750 /* ...or if any of the intervening instructions do. */
2751 for (j = 0; j < i; j++)
2752 if (gpr_read_mask (&hist[j]) & mask)
2756 return MAX_VR4130_NOPS - i;
2761 #define BASE_REG_EQ(INSN1, INSN2) \
2762 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
2763 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
2765 /* Return the minimum alignment for this store instruction. */
2768 fix_24k_align_to (const struct mips_opcode *mo)
2770 if (strcmp (mo->name, "sh") == 0)
2773 if (strcmp (mo->name, "swc1") == 0
2774 || strcmp (mo->name, "swc2") == 0
2775 || strcmp (mo->name, "sw") == 0
2776 || strcmp (mo->name, "sc") == 0
2777 || strcmp (mo->name, "s.s") == 0)
2780 if (strcmp (mo->name, "sdc1") == 0
2781 || strcmp (mo->name, "sdc2") == 0
2782 || strcmp (mo->name, "s.d") == 0)
2789 struct fix_24k_store_info
2791 /* Immediate offset, if any, for this store instruction. */
2793 /* Alignment required by this store instruction. */
2795 /* True for register offsets. */
2796 int register_offset;
2799 /* Comparison function used by qsort. */
2802 fix_24k_sort (const void *a, const void *b)
2804 const struct fix_24k_store_info *pos1 = a;
2805 const struct fix_24k_store_info *pos2 = b;
2807 return (pos1->off - pos2->off);
2810 /* INSN is a store instruction. Try to record the store information
2811 in STINFO. Return false if the information isn't known. */
2814 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
2815 const struct mips_cl_insn *insn)
2817 /* The instruction must have a known offset. */
2818 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
2821 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
2822 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
2826 /* Return the number of nops that would be needed to work around the 24k
2827 "lost data on stores during refill" errata if instruction INSN
2828 immediately followed the 2 instructions described by HIST.
2829 Ignore hazards that are contained within the first IGNORE
2830 instructions of HIST.
2832 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
2833 for the data cache refills and store data. The following describes
2834 the scenario where the store data could be lost.
2836 * A data cache miss, due to either a load or a store, causing fill
2837 data to be supplied by the memory subsystem
2838 * The first three doublewords of fill data are returned and written
2840 * A sequence of four stores occurs in consecutive cycles around the
2841 final doubleword of the fill:
2845 * Zero, One or more instructions
2848 The four stores A-D must be to different doublewords of the line that
2849 is being filled. The fourth instruction in the sequence above permits
2850 the fill of the final doubleword to be transferred from the FSB into
2851 the cache. In the sequence above, the stores may be either integer
2852 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
2853 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
2854 different doublewords on the line. If the floating point unit is
2855 running in 1:2 mode, it is not possible to create the sequence above
2856 using only floating point store instructions.
2858 In this case, the cache line being filled is incorrectly marked
2859 invalid, thereby losing the data from any store to the line that
2860 occurs between the original miss and the completion of the five
2861 cycle sequence shown above.
2863 The workarounds are:
2865 * Run the data cache in write-through mode.
2866 * Insert a non-store instruction between
2867 Store A and Store B or Store B and Store C. */
2870 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
2871 const struct mips_cl_insn *insn)
2873 struct fix_24k_store_info pos[3];
2874 int align, i, base_offset;
2879 /* If the previous instruction wasn't a store, there's nothing to
2881 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
2884 /* If the instructions after the previous one are unknown, we have
2885 to assume the worst. */
2889 /* Check whether we are dealing with three consecutive stores. */
2890 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
2891 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
2894 /* If we don't know the relationship between the store addresses,
2895 assume the worst. */
2896 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
2897 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
2900 if (!fix_24k_record_store_info (&pos[0], insn)
2901 || !fix_24k_record_store_info (&pos[1], &hist[0])
2902 || !fix_24k_record_store_info (&pos[2], &hist[1]))
2905 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
2907 /* Pick a value of ALIGN and X such that all offsets are adjusted by
2908 X bytes and such that the base register + X is known to be aligned
2911 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
2915 align = pos[0].align_to;
2916 base_offset = pos[0].off;
2917 for (i = 1; i < 3; i++)
2918 if (align < pos[i].align_to)
2920 align = pos[i].align_to;
2921 base_offset = pos[i].off;
2923 for (i = 0; i < 3; i++)
2924 pos[i].off -= base_offset;
2927 pos[0].off &= ~align + 1;
2928 pos[1].off &= ~align + 1;
2929 pos[2].off &= ~align + 1;
2931 /* If any two stores write to the same chunk, they also write to the
2932 same doubleword. The offsets are still sorted at this point. */
2933 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
2936 /* A range of at least 9 bytes is needed for the stores to be in
2937 non-overlapping doublewords. */
2938 if (pos[2].off - pos[0].off <= 8)
2941 if (pos[2].off - pos[1].off >= 24
2942 || pos[1].off - pos[0].off >= 24
2943 || pos[2].off - pos[0].off >= 32)
2949 /* Return the number of nops that would be needed if instruction INSN
2950 immediately followed the MAX_NOPS instructions given by HIST,
2951 where HIST[0] is the most recent instruction. Ignore hazards
2952 between INSN and the first IGNORE instructions in HIST.
2954 If INSN is null, return the worse-case number of nops for any
2958 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
2959 const struct mips_cl_insn *insn)
2961 int i, nops, tmp_nops;
2964 for (i = ignore; i < MAX_DELAY_NOPS; i++)
2966 tmp_nops = insns_between (hist + i, insn) - i;
2967 if (tmp_nops > nops)
2971 if (mips_fix_vr4130)
2973 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
2974 if (tmp_nops > nops)
2980 tmp_nops = nops_for_24k (ignore, hist, insn);
2981 if (tmp_nops > nops)
2988 /* The variable arguments provide NUM_INSNS extra instructions that
2989 might be added to HIST. Return the largest number of nops that
2990 would be needed after the extended sequence, ignoring hazards
2991 in the first IGNORE instructions. */
2994 nops_for_sequence (int num_insns, int ignore,
2995 const struct mips_cl_insn *hist, ...)
2998 struct mips_cl_insn buffer[MAX_NOPS];
2999 struct mips_cl_insn *cursor;
3002 va_start (args, hist);
3003 cursor = buffer + num_insns;
3004 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
3005 while (cursor > buffer)
3006 *--cursor = *va_arg (args, const struct mips_cl_insn *);
3008 nops = nops_for_insn (ignore, buffer, NULL);
3013 /* Like nops_for_insn, but if INSN is a branch, take into account the
3014 worst-case delay for the branch target. */
3017 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
3018 const struct mips_cl_insn *insn)
3022 nops = nops_for_insn (ignore, hist, insn);
3023 if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
3024 | INSN_COND_BRANCH_DELAY
3025 | INSN_COND_BRANCH_LIKELY))
3027 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
3028 hist, insn, NOP_INSN);
3029 if (tmp_nops > nops)
3032 else if (mips_opts.mips16
3033 && (insn->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
3034 | MIPS16_INSN_COND_BRANCH)))
3036 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
3037 if (tmp_nops > nops)
3043 /* Fix NOP issue: Replace nops by "or at,at,zero". */
3046 fix_loongson2f_nop (struct mips_cl_insn * ip)
3048 if (strcmp (ip->insn_mo->name, "nop") == 0)
3049 ip->insn_opcode = LOONGSON2F_NOP_INSN;
3052 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
3053 jr target pc &= 'hffff_ffff_cfff_ffff. */
3056 fix_loongson2f_jump (struct mips_cl_insn * ip)
3058 if (strcmp (ip->insn_mo->name, "j") == 0
3059 || strcmp (ip->insn_mo->name, "jr") == 0
3060 || strcmp (ip->insn_mo->name, "jalr") == 0)
3068 sreg = EXTRACT_OPERAND (RS, *ip);
3069 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
3072 ep.X_op = O_constant;
3073 ep.X_add_number = 0xcfff0000;
3074 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
3075 ep.X_add_number = 0xffff;
3076 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
3077 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
3082 fix_loongson2f (struct mips_cl_insn * ip)
3084 if (mips_fix_loongson2f_nop)
3085 fix_loongson2f_nop (ip);
3087 if (mips_fix_loongson2f_jump)
3088 fix_loongson2f_jump (ip);
3091 /* IP is a branch that has a delay slot, and we need to fill it
3092 automatically. Return true if we can do that by swapping IP
3093 with the previous instruction. */
3096 can_swap_branch_p (struct mips_cl_insn *ip)
3098 unsigned long pinfo, prev_pinfo;
3099 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
3101 /* -O2 and above is required for this optimization. */
3102 if (mips_optimize < 2)
3105 /* If we have seen .set volatile or .set nomove, don't optimize. */
3106 if (mips_opts.nomove)
3109 /* We can't swap if the previous instruction's position is fixed. */
3110 if (history[0].fixed_p)
3113 /* If the previous previous insn was in a .set noreorder, we can't
3114 swap. Actually, the MIPS assembler will swap in this situation.
3115 However, gcc configured -with-gnu-as will generate code like
3123 in which we can not swap the bne and INSN. If gcc is not configured
3124 -with-gnu-as, it does not output the .set pseudo-ops. */
3125 if (history[1].noreorder_p)
3128 /* If the previous instruction had a fixup in mips16 mode, we can not
3129 swap. This normally means that the previous instruction was a 4
3130 byte branch anyhow. */
3131 if (mips_opts.mips16 && history[0].fixp[0])
3134 /* If the branch is itself the target of a branch, we can not swap.
3135 We cheat on this; all we check for is whether there is a label on
3136 this instruction. If there are any branches to anything other than
3137 a label, users must use .set noreorder. */
3138 if (seg_info (now_seg)->label_list)
3141 /* If the previous instruction is in a variant frag other than this
3142 branch's one, we cannot do the swap. This does not apply to the
3143 mips16, which uses variant frags for different purposes. */
3144 if (!mips_opts.mips16
3146 && history[0].frag->fr_type == rs_machine_dependent)
3149 /* We do not swap with a trap instruction, since it complicates trap
3150 handlers to have the trap instruction be in a delay slot. */
3151 prev_pinfo = history[0].insn_mo->pinfo;
3152 if (prev_pinfo & INSN_TRAP)
3155 /* If the previous instruction is a sync, sync.l, or sync.p, we can
3157 if (prev_pinfo & INSN_SYNC)
3160 /* If the previous instruction is an ERET or DERET, avoid the swap. */
3161 if (history[0].insn_opcode == INSN_ERET)
3163 if (history[0].insn_opcode == INSN_DERET)
3166 /* Check for conflicts between the branch and the instructions
3167 before the candidate delay slot. */
3168 if (nops_for_insn (0, history + 1, ip) > 0)
3171 /* Check for conflicts between the swapped sequence and the
3172 target of the branch. */
3173 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
3176 /* If the branch reads a register that the previous
3177 instruction sets, we can not swap. */
3178 gpr_read = gpr_read_mask (ip);
3179 prev_gpr_write = gpr_write_mask (&history[0]);
3180 if (gpr_read & prev_gpr_write)
3183 /* If the branch writes a register that the previous
3184 instruction sets, we can not swap. */
3185 gpr_write = gpr_write_mask (ip);
3186 if (gpr_write & prev_gpr_write)
3189 /* If the branch writes a register that the previous
3190 instruction reads, we can not swap. */
3191 prev_gpr_read = gpr_read_mask (&history[0]);
3192 if (gpr_write & prev_gpr_read)
3195 /* If one instruction sets a condition code and the
3196 other one uses a condition code, we can not swap. */
3197 pinfo = ip->insn_mo->pinfo;
3198 if ((pinfo & INSN_READ_COND_CODE)
3199 && (prev_pinfo & INSN_WRITE_COND_CODE))
3201 if ((pinfo & INSN_WRITE_COND_CODE)
3202 && (prev_pinfo & INSN_READ_COND_CODE))
3205 /* If the previous instruction uses the PC, we can not swap. */
3206 if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC))
3212 /* Decide how we should add IP to the instruction stream. */
3214 static enum append_method
3215 get_append_method (struct mips_cl_insn *ip)
3217 unsigned long pinfo;
3219 /* The relaxed version of a macro sequence must be inherently
3221 if (mips_relax.sequence == 2)
3224 /* We must not dabble with instructions in a ".set norerorder" block. */
3225 if (mips_opts.noreorder)
3228 /* Otherwise, it's our responsibility to fill branch delay slots. */
3229 pinfo = ip->insn_mo->pinfo;
3230 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
3231 || (pinfo & INSN_COND_BRANCH_DELAY))
3233 if (can_swap_branch_p (ip))
3236 if (mips_opts.mips16
3237 && ISA_SUPPORTS_MIPS16E
3238 && (pinfo & INSN_UNCOND_BRANCH_DELAY)
3239 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)))
3240 return APPEND_ADD_COMPACT;
3242 return APPEND_ADD_WITH_NOP;
3245 /* We don't bother trying to track the target of branches, so there's
3246 nothing we can use to fill a branch-likely slot. */
3247 if (pinfo & INSN_COND_BRANCH_LIKELY)
3248 return APPEND_ADD_WITH_NOP;
3253 /* IP is a MIPS16 instruction whose opcode we have just changed.
3254 Point IP->insn_mo to the new opcode's definition. */
3257 find_altered_mips16_opcode (struct mips_cl_insn *ip)
3259 const struct mips_opcode *mo, *end;
3261 end = &mips16_opcodes[bfd_mips16_num_opcodes];
3262 for (mo = ip->insn_mo; mo < end; mo++)
3263 if ((ip->insn_opcode & mo->mask) == mo->match)
3271 /* Output an instruction. IP is the instruction information.
3272 ADDRESS_EXPR is an operand of the instruction to be used with
3276 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
3277 bfd_reloc_code_real_type *reloc_type)
3279 unsigned long prev_pinfo, pinfo;
3280 unsigned long prev_pinfo2, pinfo2;
3281 bfd_boolean relaxed_branch = FALSE;
3282 enum append_method method;
3284 if (mips_fix_loongson2f)
3285 fix_loongson2f (ip);
3287 /* Mark instruction labels in mips16 mode. */
3288 mips16_mark_labels ();
3290 file_ase_mips16 |= mips_opts.mips16;
3292 prev_pinfo = history[0].insn_mo->pinfo;
3293 prev_pinfo2 = history[0].insn_mo->pinfo2;
3294 pinfo = ip->insn_mo->pinfo;
3295 pinfo2 = ip->insn_mo->pinfo2;
3297 if (address_expr == NULL)
3299 else if (*reloc_type <= BFD_RELOC_UNUSED
3300 && address_expr->X_op == O_constant)
3305 switch (*reloc_type)
3308 ip->insn_opcode |= address_expr->X_add_number;
3311 case BFD_RELOC_MIPS_HIGHEST:
3312 tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48;
3313 ip->insn_opcode |= tmp & 0xffff;
3316 case BFD_RELOC_MIPS_HIGHER:
3317 tmp = (address_expr->X_add_number + 0x80008000ull) >> 32;
3318 ip->insn_opcode |= tmp & 0xffff;
3321 case BFD_RELOC_HI16_S:
3322 tmp = (address_expr->X_add_number + 0x8000) >> 16;
3323 ip->insn_opcode |= tmp & 0xffff;
3326 case BFD_RELOC_HI16:
3327 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
3330 case BFD_RELOC_UNUSED:
3331 case BFD_RELOC_LO16:
3332 case BFD_RELOC_MIPS_GOT_DISP:
3333 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
3336 case BFD_RELOC_MIPS_JMP:
3337 if ((address_expr->X_add_number & 3) != 0)
3338 as_bad (_("jump to misaligned address (0x%lx)"),
3339 (unsigned long) address_expr->X_add_number);
3340 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
3344 case BFD_RELOC_MIPS16_JMP:
3345 if ((address_expr->X_add_number & 3) != 0)
3346 as_bad (_("jump to misaligned address (0x%lx)"),
3347 (unsigned long) address_expr->X_add_number);
3349 (((address_expr->X_add_number & 0x7c0000) << 3)
3350 | ((address_expr->X_add_number & 0xf800000) >> 7)
3351 | ((address_expr->X_add_number & 0x3fffc) >> 2));
3355 case BFD_RELOC_16_PCREL_S2:
3356 if ((address_expr->X_add_number & 3) != 0)
3357 as_bad (_("branch to misaligned address (0x%lx)"),
3358 (unsigned long) address_expr->X_add_number);
3359 if (!mips_relax_branch)
3361 if ((address_expr->X_add_number + 0x20000) & ~0x3ffff)
3362 as_bad (_("branch address range overflow (0x%lx)"),
3363 (unsigned long) address_expr->X_add_number);
3364 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff;
3374 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
3376 /* There are a lot of optimizations we could do that we don't.
3377 In particular, we do not, in general, reorder instructions.
3378 If you use gcc with optimization, it will reorder
3379 instructions and generally do much more optimization then we
3380 do here; repeating all that work in the assembler would only
3381 benefit hand written assembly code, and does not seem worth
3383 int nops = (mips_optimize == 0
3384 ? nops_for_insn (0, history, NULL)
3385 : nops_for_insn_or_target (0, history, ip));
3389 unsigned long old_frag_offset;
3392 old_frag = frag_now;
3393 old_frag_offset = frag_now_fix ();
3395 for (i = 0; i < nops; i++)
3400 listing_prev_line ();
3401 /* We may be at the start of a variant frag. In case we
3402 are, make sure there is enough space for the frag
3403 after the frags created by listing_prev_line. The
3404 argument to frag_grow here must be at least as large
3405 as the argument to all other calls to frag_grow in
3406 this file. We don't have to worry about being in the
3407 middle of a variant frag, because the variants insert
3408 all needed nop instructions themselves. */
3412 mips_move_labels ();
3414 #ifndef NO_ECOFF_DEBUGGING
3415 if (ECOFF_DEBUGGING)
3416 ecoff_fix_loc (old_frag, old_frag_offset);
3420 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
3424 /* Work out how many nops in prev_nop_frag are needed by IP,
3425 ignoring hazards generated by the first prev_nop_frag_since
3427 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
3428 gas_assert (nops <= prev_nop_frag_holds);
3430 /* Enforce NOPS as a minimum. */
3431 if (nops > prev_nop_frag_required)
3432 prev_nop_frag_required = nops;
3434 if (prev_nop_frag_holds == prev_nop_frag_required)
3436 /* Settle for the current number of nops. Update the history
3437 accordingly (for the benefit of any future .set reorder code). */
3438 prev_nop_frag = NULL;
3439 insert_into_history (prev_nop_frag_since,
3440 prev_nop_frag_holds, NOP_INSN);
3444 /* Allow this instruction to replace one of the nops that was
3445 tentatively added to prev_nop_frag. */
3446 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
3447 prev_nop_frag_holds--;
3448 prev_nop_frag_since++;
3452 method = get_append_method (ip);
3455 /* The value passed to dwarf2_emit_insn is the distance between
3456 the beginning of the current instruction and the address that
3457 should be recorded in the debug tables. For MIPS16 debug info
3458 we want to use ISA-encoded addresses, so we pass -1 for an
3459 address higher by one than the current. */
3460 dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0);
3464 && *reloc_type == BFD_RELOC_16_PCREL_S2
3465 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
3466 || pinfo & INSN_COND_BRANCH_LIKELY)
3467 && mips_relax_branch
3468 /* Don't try branch relaxation within .set nomacro, or within
3469 .set noat if we use $at for PIC computations. If it turns
3470 out that the branch was out-of-range, we'll get an error. */
3471 && !mips_opts.warn_about_macros
3472 && (mips_opts.at || mips_pic == NO_PIC)
3473 /* Don't relax BPOSGE32/64 as they have no complementing branches. */
3474 && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP))
3475 && !mips_opts.mips16)
3477 relaxed_branch = TRUE;
3478 add_relaxed_insn (ip, (relaxed_branch_length
3480 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
3481 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1
3485 pinfo & INSN_UNCOND_BRANCH_DELAY,
3486 pinfo & INSN_COND_BRANCH_LIKELY,
3487 pinfo & INSN_WRITE_GPR_31,
3489 address_expr->X_add_symbol,
3490 address_expr->X_add_number);
3491 *reloc_type = BFD_RELOC_UNUSED;
3493 else if (*reloc_type > BFD_RELOC_UNUSED)
3495 /* We need to set up a variant frag. */
3496 gas_assert (mips_opts.mips16 && address_expr != NULL);
3497 add_relaxed_insn (ip, 4, 0,
3499 (*reloc_type - BFD_RELOC_UNUSED,
3500 mips16_small, mips16_ext,
3501 prev_pinfo & INSN_UNCOND_BRANCH_DELAY,
3502 history[0].mips16_absolute_jump_p),
3503 make_expr_symbol (address_expr), 0);
3505 else if (mips_opts.mips16
3507 && *reloc_type != BFD_RELOC_MIPS16_JMP)
3509 if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0)
3510 /* Make sure there is enough room to swap this instruction with
3511 a following jump instruction. */
3513 add_fixed_insn (ip);
3517 if (mips_opts.mips16
3518 && mips_opts.noreorder
3519 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
3520 as_warn (_("extended instruction in delay slot"));
3522 if (mips_relax.sequence)
3524 /* If we've reached the end of this frag, turn it into a variant
3525 frag and record the information for the instructions we've
3527 if (frag_room () < 4)
3528 relax_close_frag ();
3529 mips_relax.sizes[mips_relax.sequence - 1] += 4;
3532 if (mips_relax.sequence != 2)
3533 mips_macro_warning.sizes[0] += 4;
3534 if (mips_relax.sequence != 1)
3535 mips_macro_warning.sizes[1] += 4;
3537 if (mips_opts.mips16)
3540 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
3542 add_fixed_insn (ip);
3545 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
3547 reloc_howto_type *howto;
3550 /* In a compound relocation, it is the final (outermost)
3551 operator that determines the relocated field. */
3552 for (i = 1; i < 3; i++)
3553 if (reloc_type[i] == BFD_RELOC_UNUSED)
3556 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
3559 /* To reproduce this failure try assembling gas/testsuites/
3560 gas/mips/mips16-intermix.s with a mips-ecoff targeted
3562 as_bad (_("Unsupported MIPS relocation number %d"), reloc_type[i - 1]);
3563 howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16);
3566 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
3567 bfd_get_reloc_size (howto),
3569 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
3572 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
3573 if (reloc_type[0] == BFD_RELOC_MIPS16_JMP
3574 && ip->fixp[0]->fx_addsy)
3575 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
3577 /* These relocations can have an addend that won't fit in
3578 4 octets for 64bit assembly. */
3580 && ! howto->partial_inplace
3581 && (reloc_type[0] == BFD_RELOC_16
3582 || reloc_type[0] == BFD_RELOC_32
3583 || reloc_type[0] == BFD_RELOC_MIPS_JMP
3584 || reloc_type[0] == BFD_RELOC_GPREL16
3585 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
3586 || reloc_type[0] == BFD_RELOC_GPREL32
3587 || reloc_type[0] == BFD_RELOC_64
3588 || reloc_type[0] == BFD_RELOC_CTOR
3589 || reloc_type[0] == BFD_RELOC_MIPS_SUB
3590 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
3591 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
3592 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
3593 || reloc_type[0] == BFD_RELOC_MIPS_REL16
3594 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
3595 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
3596 || hi16_reloc_p (reloc_type[0])
3597 || lo16_reloc_p (reloc_type[0])))
3598 ip->fixp[0]->fx_no_overflow = 1;
3600 if (mips_relax.sequence)
3602 if (mips_relax.first_fixup == 0)
3603 mips_relax.first_fixup = ip->fixp[0];
3605 else if (reloc_needs_lo_p (*reloc_type))
3607 struct mips_hi_fixup *hi_fixup;
3609 /* Reuse the last entry if it already has a matching %lo. */
3610 hi_fixup = mips_hi_fixup_list;
3612 || !fixup_has_matching_lo_p (hi_fixup->fixp))
3614 hi_fixup = ((struct mips_hi_fixup *)
3615 xmalloc (sizeof (struct mips_hi_fixup)));
3616 hi_fixup->next = mips_hi_fixup_list;
3617 mips_hi_fixup_list = hi_fixup;
3619 hi_fixup->fixp = ip->fixp[0];
3620 hi_fixup->seg = now_seg;
3623 /* Add fixups for the second and third relocations, if given.
3624 Note that the ABI allows the second relocation to be
3625 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
3626 moment we only use RSS_UNDEF, but we could add support
3627 for the others if it ever becomes necessary. */
3628 for (i = 1; i < 3; i++)
3629 if (reloc_type[i] != BFD_RELOC_UNUSED)
3631 ip->fixp[i] = fix_new (ip->frag, ip->where,
3632 ip->fixp[0]->fx_size, NULL, 0,
3633 FALSE, reloc_type[i]);
3635 /* Use fx_tcbit to mark compound relocs. */
3636 ip->fixp[0]->fx_tcbit = 1;
3637 ip->fixp[i]->fx_tcbit = 1;
3642 /* Update the register mask information. */
3643 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
3644 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
3649 insert_into_history (0, 1, ip);
3652 case APPEND_ADD_WITH_NOP:
3653 insert_into_history (0, 1, ip);
3655 if (mips_relax.sequence)
3656 mips_relax.sizes[mips_relax.sequence - 1] += 4;
3659 case APPEND_ADD_COMPACT:
3660 /* Convert MIPS16 jr/jalr into a "compact" jump. */
3661 gas_assert (mips_opts.mips16);
3662 ip->insn_opcode |= 0x0080;
3663 find_altered_mips16_opcode (ip);
3665 insert_into_history (0, 1, ip);
3670 struct mips_cl_insn delay = history[0];
3671 if (mips_opts.mips16)
3673 know (delay.frag == ip->frag);
3674 move_insn (ip, delay.frag, delay.where);
3675 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
3677 else if (relaxed_branch)
3679 /* Add the delay slot instruction to the end of the
3680 current frag and shrink the fixed part of the
3681 original frag. If the branch occupies the tail of
3682 the latter, move it backwards to cover the gap. */
3683 delay.frag->fr_fix -= 4;
3684 if (delay.frag == ip->frag)
3685 move_insn (ip, ip->frag, ip->where - 4);
3686 add_fixed_insn (&delay);
3690 move_insn (&delay, ip->frag, ip->where);
3691 move_insn (ip, history[0].frag, history[0].where);
3695 insert_into_history (0, 1, &delay);
3700 /* If we have just completed an unconditional branch, clear the history. */
3701 if ((history[1].insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY)
3702 || (mips_opts.mips16
3703 && (history[0].insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH)))
3704 mips_no_prev_insn ();
3706 /* We just output an insn, so the next one doesn't have a label. */
3707 mips_clear_insn_labels ();
3710 /* Forget that there was any previous instruction or label. */
3713 mips_no_prev_insn (void)
3715 prev_nop_frag = NULL;
3716 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
3717 mips_clear_insn_labels ();
3720 /* This function must be called before we emit something other than
3721 instructions. It is like mips_no_prev_insn except that it inserts
3722 any NOPS that might be needed by previous instructions. */
3725 mips_emit_delays (void)
3727 if (! mips_opts.noreorder)
3729 int nops = nops_for_insn (0, history, NULL);
3733 add_fixed_insn (NOP_INSN);
3734 mips_move_labels ();
3737 mips_no_prev_insn ();
3740 /* Start a (possibly nested) noreorder block. */
3743 start_noreorder (void)
3745 if (mips_opts.noreorder == 0)
3750 /* None of the instructions before the .set noreorder can be moved. */
3751 for (i = 0; i < ARRAY_SIZE (history); i++)
3752 history[i].fixed_p = 1;
3754 /* Insert any nops that might be needed between the .set noreorder
3755 block and the previous instructions. We will later remove any
3756 nops that turn out not to be needed. */
3757 nops = nops_for_insn (0, history, NULL);
3760 if (mips_optimize != 0)
3762 /* Record the frag which holds the nop instructions, so
3763 that we can remove them if we don't need them. */
3764 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
3765 prev_nop_frag = frag_now;
3766 prev_nop_frag_holds = nops;
3767 prev_nop_frag_required = 0;
3768 prev_nop_frag_since = 0;
3771 for (; nops > 0; --nops)
3772 add_fixed_insn (NOP_INSN);
3774 /* Move on to a new frag, so that it is safe to simply
3775 decrease the size of prev_nop_frag. */
3776 frag_wane (frag_now);
3778 mips_move_labels ();
3780 mips16_mark_labels ();
3781 mips_clear_insn_labels ();
3783 mips_opts.noreorder++;
3784 mips_any_noreorder = 1;
3787 /* End a nested noreorder block. */
3790 end_noreorder (void)
3793 mips_opts.noreorder--;
3794 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
3796 /* Commit to inserting prev_nop_frag_required nops and go back to
3797 handling nop insertion the .set reorder way. */
3798 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
3799 * (mips_opts.mips16 ? 2 : 4));
3800 insert_into_history (prev_nop_frag_since,
3801 prev_nop_frag_required, NOP_INSN);
3802 prev_nop_frag = NULL;
3806 /* Set up global variables for the start of a new macro. */
3811 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
3812 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
3813 && (history[0].insn_mo->pinfo
3814 & (INSN_UNCOND_BRANCH_DELAY
3815 | INSN_COND_BRANCH_DELAY
3816 | INSN_COND_BRANCH_LIKELY)) != 0);
3819 /* Given that a macro is longer than 4 bytes, return the appropriate warning
3820 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
3821 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
3824 macro_warning (relax_substateT subtype)
3826 if (subtype & RELAX_DELAY_SLOT)
3827 return _("Macro instruction expanded into multiple instructions"
3828 " in a branch delay slot");
3829 else if (subtype & RELAX_NOMACRO)
3830 return _("Macro instruction expanded into multiple instructions");
3835 /* Finish up a macro. Emit warnings as appropriate. */
3840 if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4)
3842 relax_substateT subtype;
3844 /* Set up the relaxation warning flags. */
3846 if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0])
3847 subtype |= RELAX_SECOND_LONGER;
3848 if (mips_opts.warn_about_macros)
3849 subtype |= RELAX_NOMACRO;
3850 if (mips_macro_warning.delay_slot_p)
3851 subtype |= RELAX_DELAY_SLOT;
3853 if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4)
3855 /* Either the macro has a single implementation or both
3856 implementations are longer than 4 bytes. Emit the
3858 const char *msg = macro_warning (subtype);
3860 as_warn ("%s", msg);
3864 /* One implementation might need a warning but the other
3865 definitely doesn't. */
3866 mips_macro_warning.first_frag->fr_subtype |= subtype;
3871 /* Read a macro's relocation codes from *ARGS and store them in *R.
3872 The first argument in *ARGS will be either the code for a single
3873 relocation or -1 followed by the three codes that make up a
3874 composite relocation. */
3877 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
3881 next = va_arg (*args, int);
3883 r[0] = (bfd_reloc_code_real_type) next;
3885 for (i = 0; i < 3; i++)
3886 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
3889 /* Build an instruction created by a macro expansion. This is passed
3890 a pointer to the count of instructions created so far, an
3891 expression, the name of the instruction to build, an operand format
3892 string, and corresponding arguments. */
3895 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
3897 const struct mips_opcode *mo;
3898 struct mips_cl_insn insn;
3899 bfd_reloc_code_real_type r[3];
3902 va_start (args, fmt);
3904 if (mips_opts.mips16)
3906 mips16_macro_build (ep, name, fmt, &args);
3911 r[0] = BFD_RELOC_UNUSED;
3912 r[1] = BFD_RELOC_UNUSED;
3913 r[2] = BFD_RELOC_UNUSED;
3914 mo = (struct mips_opcode *) hash_find (op_hash, name);
3916 gas_assert (strcmp (name, mo->name) == 0);
3920 /* Search until we get a match for NAME. It is assumed here that
3921 macros will never generate MDMX, MIPS-3D, or MT instructions. */
3922 if (strcmp (fmt, mo->args) == 0
3923 && mo->pinfo != INSN_MACRO
3924 && is_opcode_valid (mo))
3928 gas_assert (mo->name);
3929 gas_assert (strcmp (name, mo->name) == 0);
3932 create_insn (&insn, mo);
3950 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
3955 /* Note that in the macro case, these arguments are already
3956 in MSB form. (When handling the instruction in the
3957 non-macro case, these arguments are sizes from which
3958 MSB values must be calculated.) */
3959 INSERT_OPERAND (INSMSB, insn, va_arg (args, int));
3965 /* Note that in the macro case, these arguments are already
3966 in MSBD form. (When handling the instruction in the
3967 non-macro case, these arguments are sizes from which
3968 MSBD values must be calculated.) */
3969 INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int));
3973 INSERT_OPERAND (SEQI, insn, va_arg (args, int));
3982 INSERT_OPERAND (BP, insn, va_arg (args, int));
3988 INSERT_OPERAND (RT, insn, va_arg (args, int));
3992 INSERT_OPERAND (CODE, insn, va_arg (args, int));
3997 INSERT_OPERAND (FT, insn, va_arg (args, int));
4003 INSERT_OPERAND (RD, insn, va_arg (args, int));
4008 int tmp = va_arg (args, int);
4010 INSERT_OPERAND (RT, insn, tmp);
4011 INSERT_OPERAND (RD, insn, tmp);
4017 INSERT_OPERAND (FS, insn, va_arg (args, int));
4024 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
4028 INSERT_OPERAND (FD, insn, va_arg (args, int));
4032 INSERT_OPERAND (CODE20, insn, va_arg (args, int));
4036 INSERT_OPERAND (CODE19, insn, va_arg (args, int));
4040 INSERT_OPERAND (CODE2, insn, va_arg (args, int));
4047 INSERT_OPERAND (RS, insn, va_arg (args, int));
4052 macro_read_relocs (&args, r);
4053 gas_assert (*r == BFD_RELOC_GPREL16
4054 || *r == BFD_RELOC_MIPS_HIGHER
4055 || *r == BFD_RELOC_HI16_S
4056 || *r == BFD_RELOC_LO16
4057 || *r == BFD_RELOC_MIPS_GOT_OFST);
4061 macro_read_relocs (&args, r);
4065 macro_read_relocs (&args, r);
4066 gas_assert (ep != NULL
4067 && (ep->X_op == O_constant
4068 || (ep->X_op == O_symbol
4069 && (*r == BFD_RELOC_MIPS_HIGHEST
4070 || *r == BFD_RELOC_HI16_S
4071 || *r == BFD_RELOC_HI16
4072 || *r == BFD_RELOC_GPREL16
4073 || *r == BFD_RELOC_MIPS_GOT_HI16
4074 || *r == BFD_RELOC_MIPS_CALL_HI16))));
4078 gas_assert (ep != NULL);
4081 * This allows macro() to pass an immediate expression for
4082 * creating short branches without creating a symbol.
4084 * We don't allow branch relaxation for these branches, as
4085 * they should only appear in ".set nomacro" anyway.
4087 if (ep->X_op == O_constant)
4089 if ((ep->X_add_number & 3) != 0)
4090 as_bad (_("branch to misaligned address (0x%lx)"),
4091 (unsigned long) ep->X_add_number);
4092 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
4093 as_bad (_("branch address range overflow (0x%lx)"),
4094 (unsigned long) ep->X_add_number);
4095 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
4099 *r = BFD_RELOC_16_PCREL_S2;
4103 gas_assert (ep != NULL);
4104 *r = BFD_RELOC_MIPS_JMP;
4108 INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long));
4112 INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long));
4121 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
4123 append_insn (&insn, ep, r);
4127 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
4130 struct mips_opcode *mo;
4131 struct mips_cl_insn insn;
4132 bfd_reloc_code_real_type r[3]
4133 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
4135 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
4137 gas_assert (strcmp (name, mo->name) == 0);
4139 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
4142 gas_assert (mo->name);
4143 gas_assert (strcmp (name, mo->name) == 0);
4146 create_insn (&insn, mo);
4164 MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int));
4169 MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int));
4173 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int));
4177 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int));
4187 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int));
4194 regno = va_arg (*args, int);
4195 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
4196 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
4217 gas_assert (ep != NULL);
4219 if (ep->X_op != O_constant)
4220 *r = (int) BFD_RELOC_UNUSED + c;
4223 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
4224 FALSE, &insn.insn_opcode, &insn.use_extend,
4227 *r = BFD_RELOC_UNUSED;
4233 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int));
4240 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
4242 append_insn (&insn, ep, r);
4246 * Sign-extend 32-bit mode constants that have bit 31 set and all
4247 * higher bits unset.
4250 normalize_constant_expr (expressionS *ex)
4252 if (ex->X_op == O_constant
4253 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
4254 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
4259 * Sign-extend 32-bit mode address offsets that have bit 31 set and
4260 * all higher bits unset.
4263 normalize_address_expr (expressionS *ex)
4265 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
4266 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
4267 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
4268 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
4273 * Generate a "jalr" instruction with a relocation hint to the called
4274 * function. This occurs in NewABI PIC code.
4277 macro_build_jalr (expressionS *ep)
4281 if (MIPS_JALR_HINT_P (ep))
4286 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
4287 if (MIPS_JALR_HINT_P (ep))
4288 fix_new_exp (frag_now, f - frag_now->fr_literal,
4289 4, ep, FALSE, BFD_RELOC_MIPS_JALR);
4293 * Generate a "lui" instruction.
4296 macro_build_lui (expressionS *ep, int regnum)
4298 expressionS high_expr;
4299 const struct mips_opcode *mo;
4300 struct mips_cl_insn insn;
4301 bfd_reloc_code_real_type r[3]
4302 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
4303 const char *name = "lui";
4304 const char *fmt = "t,u";
4306 gas_assert (! mips_opts.mips16);
4310 if (high_expr.X_op == O_constant)
4312 /* We can compute the instruction now without a relocation entry. */
4313 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
4315 *r = BFD_RELOC_UNUSED;
4319 gas_assert (ep->X_op == O_symbol);
4320 /* _gp_disp is a special case, used from s_cpload.
4321 __gnu_local_gp is used if mips_no_shared. */
4322 gas_assert (mips_pic == NO_PIC
4324 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
4325 || (! mips_in_shared
4326 && strcmp (S_GET_NAME (ep->X_add_symbol),
4327 "__gnu_local_gp") == 0));
4328 *r = BFD_RELOC_HI16_S;
4331 mo = hash_find (op_hash, name);
4332 gas_assert (strcmp (name, mo->name) == 0);
4333 gas_assert (strcmp (fmt, mo->args) == 0);
4334 create_insn (&insn, mo);
4336 insn.insn_opcode = insn.insn_mo->match;
4337 INSERT_OPERAND (RT, insn, regnum);
4338 if (*r == BFD_RELOC_UNUSED)
4340 insn.insn_opcode |= high_expr.X_add_number;
4341 append_insn (&insn, NULL, r);
4344 append_insn (&insn, &high_expr, r);
4347 /* Generate a sequence of instructions to do a load or store from a constant
4348 offset off of a base register (breg) into/from a target register (treg),
4349 using AT if necessary. */
4351 macro_build_ldst_constoffset (expressionS *ep, const char *op,
4352 int treg, int breg, int dbl)
4354 gas_assert (ep->X_op == O_constant);
4356 /* Sign-extending 32-bit constants makes their handling easier. */
4358 normalize_constant_expr (ep);
4360 /* Right now, this routine can only handle signed 32-bit constants. */
4361 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
4362 as_warn (_("operand overflow"));
4364 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
4366 /* Signed 16-bit offset will fit in the op. Easy! */
4367 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
4371 /* 32-bit offset, need multiple instructions and AT, like:
4372 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
4373 addu $tempreg,$tempreg,$breg
4374 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
4375 to handle the complete offset. */
4376 macro_build_lui (ep, AT);
4377 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
4378 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
4381 as_bad (_("Macro used $at after \".set noat\""));
4386 * Generates code to set the $at register to true (one)
4387 * if reg is less than the immediate expression.
4390 set_at (int reg, int unsignedp)
4392 if (imm_expr.X_op == O_constant
4393 && imm_expr.X_add_number >= -0x8000
4394 && imm_expr.X_add_number < 0x8000)
4395 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
4396 AT, reg, BFD_RELOC_LO16);
4399 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4400 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
4404 /* Warn if an expression is not a constant. */
4407 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
4409 if (ex->X_op == O_big)
4410 as_bad (_("unsupported large constant"));
4411 else if (ex->X_op != O_constant)
4412 as_bad (_("Instruction %s requires absolute expression"),
4415 if (HAVE_32BIT_GPRS)
4416 normalize_constant_expr (ex);
4419 /* Count the leading zeroes by performing a binary chop. This is a
4420 bulky bit of source, but performance is a LOT better for the
4421 majority of values than a simple loop to count the bits:
4422 for (lcnt = 0; (lcnt < 32); lcnt++)
4423 if ((v) & (1 << (31 - lcnt)))
4425 However it is not code size friendly, and the gain will drop a bit
4426 on certain cached systems.
4428 #define COUNT_TOP_ZEROES(v) \
4429 (((v) & ~0xffff) == 0 \
4430 ? ((v) & ~0xff) == 0 \
4431 ? ((v) & ~0xf) == 0 \
4432 ? ((v) & ~0x3) == 0 \
4433 ? ((v) & ~0x1) == 0 \
4438 : ((v) & ~0x7) == 0 \
4441 : ((v) & ~0x3f) == 0 \
4442 ? ((v) & ~0x1f) == 0 \
4445 : ((v) & ~0x7f) == 0 \
4448 : ((v) & ~0xfff) == 0 \
4449 ? ((v) & ~0x3ff) == 0 \
4450 ? ((v) & ~0x1ff) == 0 \
4453 : ((v) & ~0x7ff) == 0 \
4456 : ((v) & ~0x3fff) == 0 \
4457 ? ((v) & ~0x1fff) == 0 \
4460 : ((v) & ~0x7fff) == 0 \
4463 : ((v) & ~0xffffff) == 0 \
4464 ? ((v) & ~0xfffff) == 0 \
4465 ? ((v) & ~0x3ffff) == 0 \
4466 ? ((v) & ~0x1ffff) == 0 \
4469 : ((v) & ~0x7ffff) == 0 \
4472 : ((v) & ~0x3fffff) == 0 \
4473 ? ((v) & ~0x1fffff) == 0 \
4476 : ((v) & ~0x7fffff) == 0 \
4479 : ((v) & ~0xfffffff) == 0 \
4480 ? ((v) & ~0x3ffffff) == 0 \
4481 ? ((v) & ~0x1ffffff) == 0 \
4484 : ((v) & ~0x7ffffff) == 0 \
4487 : ((v) & ~0x3fffffff) == 0 \
4488 ? ((v) & ~0x1fffffff) == 0 \
4491 : ((v) & ~0x7fffffff) == 0 \
4496 * This routine generates the least number of instructions necessary to load
4497 * an absolute expression value into a register.
4500 load_register (int reg, expressionS *ep, int dbl)
4503 expressionS hi32, lo32;
4505 if (ep->X_op != O_big)
4507 gas_assert (ep->X_op == O_constant);
4509 /* Sign-extending 32-bit constants makes their handling easier. */
4511 normalize_constant_expr (ep);
4513 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
4515 /* We can handle 16 bit signed values with an addiu to
4516 $zero. No need to ever use daddiu here, since $zero and
4517 the result are always correct in 32 bit mode. */
4518 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4521 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
4523 /* We can handle 16 bit unsigned values with an ori to
4525 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
4528 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
4530 /* 32 bit values require an lui. */
4531 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16);
4532 if ((ep->X_add_number & 0xffff) != 0)
4533 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
4538 /* The value is larger than 32 bits. */
4540 if (!dbl || HAVE_32BIT_GPRS)
4544 sprintf_vma (value, ep->X_add_number);
4545 as_bad (_("Number (0x%s) larger than 32 bits"), value);
4546 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4550 if (ep->X_op != O_big)
4553 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
4554 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
4555 hi32.X_add_number &= 0xffffffff;
4557 lo32.X_add_number &= 0xffffffff;
4561 gas_assert (ep->X_add_number > 2);
4562 if (ep->X_add_number == 3)
4563 generic_bignum[3] = 0;
4564 else if (ep->X_add_number > 4)
4565 as_bad (_("Number larger than 64 bits"));
4566 lo32.X_op = O_constant;
4567 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
4568 hi32.X_op = O_constant;
4569 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
4572 if (hi32.X_add_number == 0)
4577 unsigned long hi, lo;
4579 if (hi32.X_add_number == (offsetT) 0xffffffff)
4581 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
4583 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4586 if (lo32.X_add_number & 0x80000000)
4588 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
4589 if (lo32.X_add_number & 0xffff)
4590 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
4595 /* Check for 16bit shifted constant. We know that hi32 is
4596 non-zero, so start the mask on the first bit of the hi32
4601 unsigned long himask, lomask;
4605 himask = 0xffff >> (32 - shift);
4606 lomask = (0xffff << shift) & 0xffffffff;
4610 himask = 0xffff << (shift - 32);
4613 if ((hi32.X_add_number & ~(offsetT) himask) == 0
4614 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
4618 tmp.X_op = O_constant;
4620 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
4621 | (lo32.X_add_number >> shift));
4623 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
4624 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
4625 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<",
4626 reg, reg, (shift >= 32) ? shift - 32 : shift);
4631 while (shift <= (64 - 16));
4633 /* Find the bit number of the lowest one bit, and store the
4634 shifted value in hi/lo. */
4635 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
4636 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
4640 while ((lo & 1) == 0)
4645 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
4651 while ((hi & 1) == 0)
4660 /* Optimize if the shifted value is a (power of 2) - 1. */
4661 if ((hi == 0 && ((lo + 1) & lo) == 0)
4662 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
4664 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
4669 /* This instruction will set the register to be all
4671 tmp.X_op = O_constant;
4672 tmp.X_add_number = (offsetT) -1;
4673 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4677 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<",
4678 reg, reg, (bit >= 32) ? bit - 32 : bit);
4680 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<",
4681 reg, reg, (shift >= 32) ? shift - 32 : shift);
4686 /* Sign extend hi32 before calling load_register, because we can
4687 generally get better code when we load a sign extended value. */
4688 if ((hi32.X_add_number & 0x80000000) != 0)
4689 hi32.X_add_number |= ~(offsetT) 0xffffffff;
4690 load_register (reg, &hi32, 0);
4693 if ((lo32.X_add_number & 0xffff0000) == 0)
4697 macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0);
4705 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
4707 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
4708 macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0);
4714 macro_build (NULL, "dsll", "d,w,<", reg, freg, 16);
4718 mid16.X_add_number >>= 16;
4719 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
4720 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4723 if ((lo32.X_add_number & 0xffff) != 0)
4724 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
4728 load_delay_nop (void)
4730 if (!gpr_interlocks)
4731 macro_build (NULL, "nop", "");
4734 /* Load an address into a register. */
4737 load_address (int reg, expressionS *ep, int *used_at)
4739 if (ep->X_op != O_constant
4740 && ep->X_op != O_symbol)
4742 as_bad (_("expression too complex"));
4743 ep->X_op = O_constant;
4746 if (ep->X_op == O_constant)
4748 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
4752 if (mips_pic == NO_PIC)
4754 /* If this is a reference to a GP relative symbol, we want
4755 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4757 lui $reg,<sym> (BFD_RELOC_HI16_S)
4758 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4759 If we have an addend, we always use the latter form.
4761 With 64bit address space and a usable $at we want
4762 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4763 lui $at,<sym> (BFD_RELOC_HI16_S)
4764 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4765 daddiu $at,<sym> (BFD_RELOC_LO16)
4769 If $at is already in use, we use a path which is suboptimal
4770 on superscalar processors.
4771 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4772 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4774 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
4776 daddiu $reg,<sym> (BFD_RELOC_LO16)
4778 For GP relative symbols in 64bit address space we can use
4779 the same sequence as in 32bit address space. */
4780 if (HAVE_64BIT_SYMBOLS)
4782 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
4783 && !nopic_need_relax (ep->X_add_symbol, 1))
4785 relax_start (ep->X_add_symbol);
4786 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4787 mips_gp_register, BFD_RELOC_GPREL16);
4791 if (*used_at == 0 && mips_opts.at)
4793 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
4794 macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S);
4795 macro_build (ep, "daddiu", "t,r,j", reg, reg,
4796 BFD_RELOC_MIPS_HIGHER);
4797 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
4798 macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0);
4799 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
4804 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
4805 macro_build (ep, "daddiu", "t,r,j", reg, reg,
4806 BFD_RELOC_MIPS_HIGHER);
4807 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4808 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
4809 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4810 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
4813 if (mips_relax.sequence)
4818 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
4819 && !nopic_need_relax (ep->X_add_symbol, 1))
4821 relax_start (ep->X_add_symbol);
4822 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4823 mips_gp_register, BFD_RELOC_GPREL16);
4826 macro_build_lui (ep, reg);
4827 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
4828 reg, reg, BFD_RELOC_LO16);
4829 if (mips_relax.sequence)
4833 else if (!mips_big_got)
4837 /* If this is a reference to an external symbol, we want
4838 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4840 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4842 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4843 If there is a constant, it must be added in after.
4845 If we have NewABI, we want
4846 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4847 unless we're referencing a global symbol with a non-zero
4848 offset, in which case cst must be added separately. */
4851 if (ep->X_add_number)
4853 ex.X_add_number = ep->X_add_number;
4854 ep->X_add_number = 0;
4855 relax_start (ep->X_add_symbol);
4856 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4857 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4858 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4859 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4860 ex.X_op = O_constant;
4861 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
4862 reg, reg, BFD_RELOC_LO16);
4863 ep->X_add_number = ex.X_add_number;
4866 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4867 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4868 if (mips_relax.sequence)
4873 ex.X_add_number = ep->X_add_number;
4874 ep->X_add_number = 0;
4875 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4876 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4878 relax_start (ep->X_add_symbol);
4880 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4884 if (ex.X_add_number != 0)
4886 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4887 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4888 ex.X_op = O_constant;
4889 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
4890 reg, reg, BFD_RELOC_LO16);
4894 else if (mips_big_got)
4898 /* This is the large GOT case. If this is a reference to an
4899 external symbol, we want
4900 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4902 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
4904 Otherwise, for a reference to a local symbol in old ABI, we want
4905 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4907 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4908 If there is a constant, it must be added in after.
4910 In the NewABI, for local symbols, with or without offsets, we want:
4911 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4912 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4916 ex.X_add_number = ep->X_add_number;
4917 ep->X_add_number = 0;
4918 relax_start (ep->X_add_symbol);
4919 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4920 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4921 reg, reg, mips_gp_register);
4922 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4923 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4924 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4925 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4926 else if (ex.X_add_number)
4928 ex.X_op = O_constant;
4929 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4933 ep->X_add_number = ex.X_add_number;
4935 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4936 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
4937 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4938 BFD_RELOC_MIPS_GOT_OFST);
4943 ex.X_add_number = ep->X_add_number;
4944 ep->X_add_number = 0;
4945 relax_start (ep->X_add_symbol);
4946 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4947 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4948 reg, reg, mips_gp_register);
4949 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4950 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4952 if (reg_needs_delay (mips_gp_register))
4954 /* We need a nop before loading from $gp. This special
4955 check is required because the lui which starts the main
4956 instruction stream does not refer to $gp, and so will not
4957 insert the nop which may be required. */
4958 macro_build (NULL, "nop", "");
4960 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4961 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4963 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4967 if (ex.X_add_number != 0)
4969 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4970 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4971 ex.X_op = O_constant;
4972 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4980 if (!mips_opts.at && *used_at == 1)
4981 as_bad (_("Macro used $at after \".set noat\""));
4984 /* Move the contents of register SOURCE into register DEST. */
4987 move_register (int dest, int source)
4989 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
4993 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4994 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4995 The two alternatives are:
4997 Global symbol Local sybmol
4998 ------------- ------------
4999 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
5001 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
5003 load_got_offset emits the first instruction and add_got_offset
5004 emits the second for a 16-bit offset or add_got_offset_hilo emits
5005 a sequence to add a 32-bit offset using a scratch register. */
5008 load_got_offset (int dest, expressionS *local)
5013 global.X_add_number = 0;
5015 relax_start (local->X_add_symbol);
5016 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
5017 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5019 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
5020 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5025 add_got_offset (int dest, expressionS *local)
5029 global.X_op = O_constant;
5030 global.X_op_symbol = NULL;
5031 global.X_add_symbol = NULL;
5032 global.X_add_number = local->X_add_number;
5034 relax_start (local->X_add_symbol);
5035 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
5036 dest, dest, BFD_RELOC_LO16);
5038 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
5043 add_got_offset_hilo (int dest, expressionS *local, int tmp)
5046 int hold_mips_optimize;
5048 global.X_op = O_constant;
5049 global.X_op_symbol = NULL;
5050 global.X_add_symbol = NULL;
5051 global.X_add_number = local->X_add_number;
5053 relax_start (local->X_add_symbol);
5054 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
5056 /* Set mips_optimize around the lui instruction to avoid
5057 inserting an unnecessary nop after the lw. */
5058 hold_mips_optimize = mips_optimize;
5060 macro_build_lui (&global, tmp);
5061 mips_optimize = hold_mips_optimize;
5062 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
5065 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
5070 * This routine implements the seemingly endless macro or synthesized
5071 * instructions and addressing modes in the mips assembly language. Many
5072 * of these macros are simple and are similar to each other. These could
5073 * probably be handled by some kind of table or grammar approach instead of
5074 * this verbose method. Others are not simple macros but are more like
5075 * optimizing code generation.
5076 * One interesting optimization is when several store macros appear
5077 * consecutively that would load AT with the upper half of the same address.
5078 * The ensuing load upper instructions are ommited. This implies some kind
5079 * of global optimization. We currently only optimize within a single macro.
5080 * For many of the load and store macros if the address is specified as a
5081 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
5082 * first load register 'at' with zero and use it as the base register. The
5083 * mips assembler simply uses register $zero. Just one tiny optimization
5087 macro (struct mips_cl_insn *ip)
5089 unsigned int treg, sreg, dreg, breg;
5090 unsigned int tempreg;
5105 bfd_reloc_code_real_type r;
5106 int hold_mips_optimize;
5108 gas_assert (! mips_opts.mips16);
5110 treg = EXTRACT_OPERAND (RT, *ip);
5111 dreg = EXTRACT_OPERAND (RD, *ip);
5112 sreg = breg = EXTRACT_OPERAND (RS, *ip);
5113 mask = ip->insn_mo->mask;
5115 expr1.X_op = O_constant;
5116 expr1.X_op_symbol = NULL;
5117 expr1.X_add_symbol = NULL;
5118 expr1.X_add_number = 1;
5132 expr1.X_add_number = 8;
5133 macro_build (&expr1, "bgez", "s,p", sreg);
5135 macro_build (NULL, "nop", "");
5137 move_register (dreg, sreg);
5138 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
5161 if (imm_expr.X_op == O_constant
5162 && imm_expr.X_add_number >= -0x8000
5163 && imm_expr.X_add_number < 0x8000)
5165 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
5169 load_register (AT, &imm_expr, dbl);
5170 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
5189 if (imm_expr.X_op == O_constant
5190 && imm_expr.X_add_number >= 0
5191 && imm_expr.X_add_number < 0x10000)
5193 if (mask != M_NOR_I)
5194 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
5197 macro_build (&imm_expr, "ori", "t,r,i",
5198 treg, sreg, BFD_RELOC_LO16);
5199 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
5205 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5206 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
5210 switch (imm_expr.X_add_number)
5213 macro_build (NULL, "nop", "");
5216 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
5219 macro_build (NULL, "balign", "t,s,2", treg, sreg,
5220 (int) imm_expr.X_add_number);
5239 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5241 macro_build (&offset_expr, s, "s,t,p", sreg, ZERO);
5245 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5246 macro_build (&offset_expr, s, "s,t,p", sreg, AT);
5254 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
5259 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg);
5263 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
5264 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5270 /* Check for > max integer. */
5271 maxnum = 0x7fffffff;
5272 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5279 if (imm_expr.X_op == O_constant
5280 && imm_expr.X_add_number >= maxnum
5281 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5284 /* Result is always false. */
5286 macro_build (NULL, "nop", "");
5288 macro_build (&offset_expr, "bnel", "s,t,p", ZERO, ZERO);
5291 if (imm_expr.X_op != O_constant)
5292 as_bad (_("Unsupported large constant"));
5293 ++imm_expr.X_add_number;
5297 if (mask == M_BGEL_I)
5299 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5301 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
5304 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5306 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
5309 maxnum = 0x7fffffff;
5310 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5317 maxnum = - maxnum - 1;
5318 if (imm_expr.X_op == O_constant
5319 && imm_expr.X_add_number <= maxnum
5320 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5323 /* result is always true */
5324 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
5325 macro_build (&offset_expr, "b", "p");
5330 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5340 macro_build (&offset_expr, likely ? "beql" : "beq",
5341 "s,t,p", ZERO, treg);
5345 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
5346 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5354 && imm_expr.X_op == O_constant
5355 && imm_expr.X_add_number == -1))
5357 if (imm_expr.X_op != O_constant)
5358 as_bad (_("Unsupported large constant"));
5359 ++imm_expr.X_add_number;
5363 if (mask == M_BGEUL_I)
5365 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5367 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5369 macro_build (&offset_expr, likely ? "bnel" : "bne",
5370 "s,t,p", sreg, ZERO);
5375 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5383 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
5388 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg);
5392 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
5393 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5401 macro_build (&offset_expr, likely ? "bnel" : "bne",
5402 "s,t,p", sreg, ZERO);
5408 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
5409 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5417 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
5422 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg);
5426 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
5427 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5433 maxnum = 0x7fffffff;
5434 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5441 if (imm_expr.X_op == O_constant
5442 && imm_expr.X_add_number >= maxnum
5443 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5445 if (imm_expr.X_op != O_constant)
5446 as_bad (_("Unsupported large constant"));
5447 ++imm_expr.X_add_number;
5451 if (mask == M_BLTL_I)
5453 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5455 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
5458 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5460 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
5465 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5473 macro_build (&offset_expr, likely ? "beql" : "beq",
5474 "s,t,p", sreg, ZERO);
5480 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
5481 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5489 && imm_expr.X_op == O_constant
5490 && imm_expr.X_add_number == -1))
5492 if (imm_expr.X_op != O_constant)
5493 as_bad (_("Unsupported large constant"));
5494 ++imm_expr.X_add_number;
5498 if (mask == M_BLTUL_I)
5500 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5502 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5504 macro_build (&offset_expr, likely ? "beql" : "beq",
5505 "s,t,p", sreg, ZERO);
5510 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5518 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
5523 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg);
5527 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
5528 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5538 macro_build (&offset_expr, likely ? "bnel" : "bne",
5539 "s,t,p", ZERO, treg);
5543 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
5544 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5549 /* Use unsigned arithmetic. */
5553 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5555 as_bad (_("Unsupported large constant"));
5560 pos = imm_expr.X_add_number;
5561 size = imm2_expr.X_add_number;
5566 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
5569 if (size == 0 || size > 64 || (pos + size - 1) > 63)
5571 as_bad (_("Improper extract size (%lu, position %lu)"),
5572 (unsigned long) size, (unsigned long) pos);
5576 if (size <= 32 && pos < 32)
5581 else if (size <= 32)
5591 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
5598 /* Use unsigned arithmetic. */
5602 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5604 as_bad (_("Unsupported large constant"));
5609 pos = imm_expr.X_add_number;
5610 size = imm2_expr.X_add_number;
5615 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
5618 if (size == 0 || size > 64 || (pos + size - 1) > 63)
5620 as_bad (_("Improper insert size (%lu, position %lu)"),
5621 (unsigned long) size, (unsigned long) pos);
5625 if (pos < 32 && (pos + size - 1) < 32)
5640 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
5641 (int) (pos + size - 1));
5657 as_warn (_("Divide by zero."));
5659 macro_build (NULL, "teq", "s,t,q", ZERO, ZERO, 7);
5661 macro_build (NULL, "break", "c", 7);
5668 macro_build (NULL, "teq", "s,t,q", treg, ZERO, 7);
5669 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
5673 expr1.X_add_number = 8;
5674 macro_build (&expr1, "bne", "s,t,p", treg, ZERO);
5675 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
5676 macro_build (NULL, "break", "c", 7);
5678 expr1.X_add_number = -1;
5680 load_register (AT, &expr1, dbl);
5681 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
5682 macro_build (&expr1, "bne", "s,t,p", treg, AT);
5685 expr1.X_add_number = 1;
5686 load_register (AT, &expr1, dbl);
5687 macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31);
5691 expr1.X_add_number = 0x80000000;
5692 macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16);
5696 macro_build (NULL, "teq", "s,t,q", sreg, AT, 6);
5697 /* We want to close the noreorder block as soon as possible, so
5698 that later insns are available for delay slot filling. */
5703 expr1.X_add_number = 8;
5704 macro_build (&expr1, "bne", "s,t,p", sreg, AT);
5705 macro_build (NULL, "nop", "");
5707 /* We want to close the noreorder block as soon as possible, so
5708 that later insns are available for delay slot filling. */
5711 macro_build (NULL, "break", "c", 6);
5713 macro_build (NULL, s, "d", dreg);
5752 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5754 as_warn (_("Divide by zero."));
5756 macro_build (NULL, "teq", "s,t,q", ZERO, ZERO, 7);
5758 macro_build (NULL, "break", "c", 7);
5761 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5763 if (strcmp (s2, "mflo") == 0)
5764 move_register (dreg, sreg);
5766 move_register (dreg, ZERO);
5769 if (imm_expr.X_op == O_constant
5770 && imm_expr.X_add_number == -1
5771 && s[strlen (s) - 1] != 'u')
5773 if (strcmp (s2, "mflo") == 0)
5775 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
5778 move_register (dreg, ZERO);
5783 load_register (AT, &imm_expr, dbl);
5784 macro_build (NULL, s, "z,s,t", sreg, AT);
5785 macro_build (NULL, s2, "d", dreg);
5807 macro_build (NULL, "teq", "s,t,q", treg, ZERO, 7);
5808 macro_build (NULL, s, "z,s,t", sreg, treg);
5809 /* We want to close the noreorder block as soon as possible, so
5810 that later insns are available for delay slot filling. */
5815 expr1.X_add_number = 8;
5816 macro_build (&expr1, "bne", "s,t,p", treg, ZERO);
5817 macro_build (NULL, s, "z,s,t", sreg, treg);
5819 /* We want to close the noreorder block as soon as possible, so
5820 that later insns are available for delay slot filling. */
5822 macro_build (NULL, "break", "c", 7);
5824 macro_build (NULL, s2, "d", dreg);
5836 /* Load the address of a symbol into a register. If breg is not
5837 zero, we then add a base register to it. */
5839 if (dbl && HAVE_32BIT_GPRS)
5840 as_warn (_("dla used to load 32-bit register"));
5842 if (!dbl && HAVE_64BIT_OBJECTS)
5843 as_warn (_("la used to load 64-bit address"));
5845 if (offset_expr.X_op == O_constant
5846 && offset_expr.X_add_number >= -0x8000
5847 && offset_expr.X_add_number < 0x8000)
5849 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
5850 "t,r,j", treg, sreg, BFD_RELOC_LO16);
5854 if (mips_opts.at && (treg == breg))
5864 if (offset_expr.X_op != O_symbol
5865 && offset_expr.X_op != O_constant)
5867 as_bad (_("Expression too complex"));
5868 offset_expr.X_op = O_constant;
5871 if (offset_expr.X_op == O_constant)
5872 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
5873 else if (mips_pic == NO_PIC)
5875 /* If this is a reference to a GP relative symbol, we want
5876 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5878 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5879 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5880 If we have a constant, we need two instructions anyhow,
5881 so we may as well always use the latter form.
5883 With 64bit address space and a usable $at we want
5884 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5885 lui $at,<sym> (BFD_RELOC_HI16_S)
5886 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5887 daddiu $at,<sym> (BFD_RELOC_LO16)
5889 daddu $tempreg,$tempreg,$at
5891 If $at is already in use, we use a path which is suboptimal
5892 on superscalar processors.
5893 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5894 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5896 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5898 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
5900 For GP relative symbols in 64bit address space we can use
5901 the same sequence as in 32bit address space. */
5902 if (HAVE_64BIT_SYMBOLS)
5904 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5905 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5907 relax_start (offset_expr.X_add_symbol);
5908 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5909 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5913 if (used_at == 0 && mips_opts.at)
5915 macro_build (&offset_expr, "lui", "t,u",
5916 tempreg, BFD_RELOC_MIPS_HIGHEST);
5917 macro_build (&offset_expr, "lui", "t,u",
5918 AT, BFD_RELOC_HI16_S);
5919 macro_build (&offset_expr, "daddiu", "t,r,j",
5920 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5921 macro_build (&offset_expr, "daddiu", "t,r,j",
5922 AT, AT, BFD_RELOC_LO16);
5923 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
5924 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
5929 macro_build (&offset_expr, "lui", "t,u",
5930 tempreg, BFD_RELOC_MIPS_HIGHEST);
5931 macro_build (&offset_expr, "daddiu", "t,r,j",
5932 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5933 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5934 macro_build (&offset_expr, "daddiu", "t,r,j",
5935 tempreg, tempreg, BFD_RELOC_HI16_S);
5936 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5937 macro_build (&offset_expr, "daddiu", "t,r,j",
5938 tempreg, tempreg, BFD_RELOC_LO16);
5941 if (mips_relax.sequence)
5946 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5947 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5949 relax_start (offset_expr.X_add_symbol);
5950 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5951 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5954 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
5955 as_bad (_("Offset too large"));
5956 macro_build_lui (&offset_expr, tempreg);
5957 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5958 tempreg, tempreg, BFD_RELOC_LO16);
5959 if (mips_relax.sequence)
5963 else if (!mips_big_got && !HAVE_NEWABI)
5965 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5967 /* If this is a reference to an external symbol, and there
5968 is no constant, we want
5969 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5970 or for lca or if tempreg is PIC_CALL_REG
5971 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5972 For a local symbol, we want
5973 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5975 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5977 If we have a small constant, and this is a reference to
5978 an external symbol, we want
5979 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5981 addiu $tempreg,$tempreg,<constant>
5982 For a local symbol, we want the same instruction
5983 sequence, but we output a BFD_RELOC_LO16 reloc on the
5986 If we have a large constant, and this is a reference to
5987 an external symbol, we want
5988 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5989 lui $at,<hiconstant>
5990 addiu $at,$at,<loconstant>
5991 addu $tempreg,$tempreg,$at
5992 For a local symbol, we want the same instruction
5993 sequence, but we output a BFD_RELOC_LO16 reloc on the
5997 if (offset_expr.X_add_number == 0)
5999 if (mips_pic == SVR4_PIC
6001 && (call || tempreg == PIC_CALL_REG))
6002 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
6004 relax_start (offset_expr.X_add_symbol);
6005 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6006 lw_reloc_type, mips_gp_register);
6009 /* We're going to put in an addu instruction using
6010 tempreg, so we may as well insert the nop right
6015 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6016 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
6018 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6019 tempreg, tempreg, BFD_RELOC_LO16);
6021 /* FIXME: If breg == 0, and the next instruction uses
6022 $tempreg, then if this variant case is used an extra
6023 nop will be generated. */
6025 else if (offset_expr.X_add_number >= -0x8000
6026 && offset_expr.X_add_number < 0x8000)
6028 load_got_offset (tempreg, &offset_expr);
6030 add_got_offset (tempreg, &offset_expr);
6034 expr1.X_add_number = offset_expr.X_add_number;
6035 offset_expr.X_add_number =
6036 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
6037 load_got_offset (tempreg, &offset_expr);
6038 offset_expr.X_add_number = expr1.X_add_number;
6039 /* If we are going to add in a base register, and the
6040 target register and the base register are the same,
6041 then we are using AT as a temporary register. Since
6042 we want to load the constant into AT, we add our
6043 current AT (from the global offset table) and the
6044 register into the register now, and pretend we were
6045 not using a base register. */
6049 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6054 add_got_offset_hilo (tempreg, &offset_expr, AT);
6058 else if (!mips_big_got && HAVE_NEWABI)
6060 int add_breg_early = 0;
6062 /* If this is a reference to an external, and there is no
6063 constant, or local symbol (*), with or without a
6065 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6066 or for lca or if tempreg is PIC_CALL_REG
6067 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
6069 If we have a small constant, and this is a reference to
6070 an external symbol, we want
6071 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6072 addiu $tempreg,$tempreg,<constant>
6074 If we have a large constant, and this is a reference to
6075 an external symbol, we want
6076 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6077 lui $at,<hiconstant>
6078 addiu $at,$at,<loconstant>
6079 addu $tempreg,$tempreg,$at
6081 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
6082 local symbols, even though it introduces an additional
6085 if (offset_expr.X_add_number)
6087 expr1.X_add_number = offset_expr.X_add_number;
6088 offset_expr.X_add_number = 0;
6090 relax_start (offset_expr.X_add_symbol);
6091 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6092 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6094 if (expr1.X_add_number >= -0x8000
6095 && expr1.X_add_number < 0x8000)
6097 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
6098 tempreg, tempreg, BFD_RELOC_LO16);
6100 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
6102 /* If we are going to add in a base register, and the
6103 target register and the base register are the same,
6104 then we are using AT as a temporary register. Since
6105 we want to load the constant into AT, we add our
6106 current AT (from the global offset table) and the
6107 register into the register now, and pretend we were
6108 not using a base register. */
6113 gas_assert (tempreg == AT);
6114 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6120 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
6121 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6127 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
6130 offset_expr.X_add_number = expr1.X_add_number;
6132 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6133 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6136 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6137 treg, tempreg, breg);
6143 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
6145 relax_start (offset_expr.X_add_symbol);
6146 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6147 BFD_RELOC_MIPS_CALL16, mips_gp_register);
6149 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6150 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6155 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6156 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6159 else if (mips_big_got && !HAVE_NEWABI)
6162 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
6163 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
6164 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6166 /* This is the large GOT case. If this is a reference to an
6167 external symbol, and there is no constant, we want
6168 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6169 addu $tempreg,$tempreg,$gp
6170 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6171 or for lca or if tempreg is PIC_CALL_REG
6172 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6173 addu $tempreg,$tempreg,$gp
6174 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
6175 For a local symbol, we want
6176 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6178 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6180 If we have a small constant, and this is a reference to
6181 an external symbol, we want
6182 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6183 addu $tempreg,$tempreg,$gp
6184 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6186 addiu $tempreg,$tempreg,<constant>
6187 For a local symbol, we want
6188 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6190 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
6192 If we have a large constant, and this is a reference to
6193 an external symbol, we want
6194 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6195 addu $tempreg,$tempreg,$gp
6196 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6197 lui $at,<hiconstant>
6198 addiu $at,$at,<loconstant>
6199 addu $tempreg,$tempreg,$at
6200 For a local symbol, we want
6201 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6202 lui $at,<hiconstant>
6203 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
6204 addu $tempreg,$tempreg,$at
6207 expr1.X_add_number = offset_expr.X_add_number;
6208 offset_expr.X_add_number = 0;
6209 relax_start (offset_expr.X_add_symbol);
6210 gpdelay = reg_needs_delay (mips_gp_register);
6211 if (expr1.X_add_number == 0 && breg == 0
6212 && (call || tempreg == PIC_CALL_REG))
6214 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
6215 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
6217 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
6218 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6219 tempreg, tempreg, mips_gp_register);
6220 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6221 tempreg, lw_reloc_type, tempreg);
6222 if (expr1.X_add_number == 0)
6226 /* We're going to put in an addu instruction using
6227 tempreg, so we may as well insert the nop right
6232 else if (expr1.X_add_number >= -0x8000
6233 && expr1.X_add_number < 0x8000)
6236 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
6237 tempreg, tempreg, BFD_RELOC_LO16);
6241 /* If we are going to add in a base register, and the
6242 target register and the base register are the same,
6243 then we are using AT as a temporary register. Since
6244 we want to load the constant into AT, we add our
6245 current AT (from the global offset table) and the
6246 register into the register now, and pretend we were
6247 not using a base register. */
6252 gas_assert (tempreg == AT);
6254 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6259 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
6260 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
6264 offset_expr.X_add_number =
6265 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000;
6270 /* This is needed because this instruction uses $gp, but
6271 the first instruction on the main stream does not. */
6272 macro_build (NULL, "nop", "");
6275 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6276 local_reloc_type, mips_gp_register);
6277 if (expr1.X_add_number >= -0x8000
6278 && expr1.X_add_number < 0x8000)
6281 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6282 tempreg, tempreg, BFD_RELOC_LO16);
6283 /* FIXME: If add_number is 0, and there was no base
6284 register, the external symbol case ended with a load,
6285 so if the symbol turns out to not be external, and
6286 the next instruction uses tempreg, an unnecessary nop
6287 will be inserted. */
6293 /* We must add in the base register now, as in the
6294 external symbol case. */
6295 gas_assert (tempreg == AT);
6297 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6300 /* We set breg to 0 because we have arranged to add
6301 it in in both cases. */
6305 macro_build_lui (&expr1, AT);
6306 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6307 AT, AT, BFD_RELOC_LO16);
6308 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6309 tempreg, tempreg, AT);
6314 else if (mips_big_got && HAVE_NEWABI)
6316 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
6317 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
6318 int add_breg_early = 0;
6320 /* This is the large GOT case. If this is a reference to an
6321 external symbol, and there is no constant, we want
6322 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6323 add $tempreg,$tempreg,$gp
6324 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6325 or for lca or if tempreg is PIC_CALL_REG
6326 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6327 add $tempreg,$tempreg,$gp
6328 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
6330 If we have a small constant, and this is a reference to
6331 an external symbol, we want
6332 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6333 add $tempreg,$tempreg,$gp
6334 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6335 addi $tempreg,$tempreg,<constant>
6337 If we have a large constant, and this is a reference to
6338 an external symbol, we want
6339 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6340 addu $tempreg,$tempreg,$gp
6341 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6342 lui $at,<hiconstant>
6343 addi $at,$at,<loconstant>
6344 add $tempreg,$tempreg,$at
6346 If we have NewABI, and we know it's a local symbol, we want
6347 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6348 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6349 otherwise we have to resort to GOT_HI16/GOT_LO16. */
6351 relax_start (offset_expr.X_add_symbol);
6353 expr1.X_add_number = offset_expr.X_add_number;
6354 offset_expr.X_add_number = 0;
6356 if (expr1.X_add_number == 0 && breg == 0
6357 && (call || tempreg == PIC_CALL_REG))
6359 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
6360 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
6362 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
6363 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6364 tempreg, tempreg, mips_gp_register);
6365 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6366 tempreg, lw_reloc_type, tempreg);
6368 if (expr1.X_add_number == 0)
6370 else if (expr1.X_add_number >= -0x8000
6371 && expr1.X_add_number < 0x8000)
6373 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
6374 tempreg, tempreg, BFD_RELOC_LO16);
6376 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
6378 /* If we are going to add in a base register, and the
6379 target register and the base register are the same,
6380 then we are using AT as a temporary register. Since
6381 we want to load the constant into AT, we add our
6382 current AT (from the global offset table) and the
6383 register into the register now, and pretend we were
6384 not using a base register. */
6389 gas_assert (tempreg == AT);
6390 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6396 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
6397 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
6402 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
6405 offset_expr.X_add_number = expr1.X_add_number;
6406 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6407 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6408 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6409 tempreg, BFD_RELOC_MIPS_GOT_OFST);
6412 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6413 treg, tempreg, breg);
6423 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
6428 unsigned long temp = (treg << 16) | (0x01);
6429 macro_build (NULL, "c2", "C", temp);
6435 unsigned long temp = (0x02);
6436 macro_build (NULL, "c2", "C", temp);
6442 unsigned long temp = (treg << 16) | (0x02);
6443 macro_build (NULL, "c2", "C", temp);
6448 macro_build (NULL, "c2", "C", 3);
6453 unsigned long temp = (treg << 16) | 0x03;
6454 macro_build (NULL, "c2", "C", temp);
6459 /* The j instruction may not be used in PIC code, since it
6460 requires an absolute address. We convert it to a b
6462 if (mips_pic == NO_PIC)
6463 macro_build (&offset_expr, "j", "a");
6465 macro_build (&offset_expr, "b", "p");
6468 /* The jal instructions must be handled as macros because when
6469 generating PIC code they expand to multi-instruction
6470 sequences. Normally they are simple instructions. */
6475 if (mips_pic == NO_PIC)
6476 macro_build (NULL, "jalr", "d,s", dreg, sreg);
6479 if (sreg != PIC_CALL_REG)
6480 as_warn (_("MIPS PIC call to register other than $25"));
6482 macro_build (NULL, "jalr", "d,s", dreg, sreg);
6483 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
6485 if (mips_cprestore_offset < 0)
6486 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6489 if (!mips_frame_reg_valid)
6491 as_warn (_("No .frame pseudo-op used in PIC code"));
6492 /* Quiet this warning. */
6493 mips_frame_reg_valid = 1;
6495 if (!mips_cprestore_valid)
6497 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6498 /* Quiet this warning. */
6499 mips_cprestore_valid = 1;
6501 if (mips_opts.noreorder)
6502 macro_build (NULL, "nop", "");
6503 expr1.X_add_number = mips_cprestore_offset;
6504 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
6507 HAVE_64BIT_ADDRESSES);
6515 if (mips_pic == NO_PIC)
6516 macro_build (&offset_expr, "jal", "a");
6517 else if (mips_pic == SVR4_PIC)
6519 /* If this is a reference to an external symbol, and we are
6520 using a small GOT, we want
6521 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
6525 lw $gp,cprestore($sp)
6526 The cprestore value is set using the .cprestore
6527 pseudo-op. If we are using a big GOT, we want
6528 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6530 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
6534 lw $gp,cprestore($sp)
6535 If the symbol is not external, we want
6536 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6538 addiu $25,$25,<sym> (BFD_RELOC_LO16)
6541 lw $gp,cprestore($sp)
6543 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
6544 sequences above, minus nops, unless the symbol is local,
6545 which enables us to use GOT_PAGE/GOT_OFST (big got) or
6551 relax_start (offset_expr.X_add_symbol);
6552 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6553 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
6556 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6557 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
6563 relax_start (offset_expr.X_add_symbol);
6564 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
6565 BFD_RELOC_MIPS_CALL_HI16);
6566 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
6567 PIC_CALL_REG, mips_gp_register);
6568 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6569 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
6572 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6573 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
6575 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6576 PIC_CALL_REG, PIC_CALL_REG,
6577 BFD_RELOC_MIPS_GOT_OFST);
6581 macro_build_jalr (&offset_expr);
6585 relax_start (offset_expr.X_add_symbol);
6588 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6589 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
6598 gpdelay = reg_needs_delay (mips_gp_register);
6599 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
6600 BFD_RELOC_MIPS_CALL_HI16);
6601 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
6602 PIC_CALL_REG, mips_gp_register);
6603 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6604 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
6609 macro_build (NULL, "nop", "");
6611 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6612 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
6615 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6616 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
6618 macro_build_jalr (&offset_expr);
6620 if (mips_cprestore_offset < 0)
6621 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6624 if (!mips_frame_reg_valid)
6626 as_warn (_("No .frame pseudo-op used in PIC code"));
6627 /* Quiet this warning. */
6628 mips_frame_reg_valid = 1;
6630 if (!mips_cprestore_valid)
6632 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6633 /* Quiet this warning. */
6634 mips_cprestore_valid = 1;
6636 if (mips_opts.noreorder)
6637 macro_build (NULL, "nop", "");
6638 expr1.X_add_number = mips_cprestore_offset;
6639 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
6642 HAVE_64BIT_ADDRESSES);
6646 else if (mips_pic == VXWORKS_PIC)
6647 as_bad (_("Non-PIC jump used in PIC library"));
6670 /* Itbl support may require additional care here. */
6675 /* Itbl support may require additional care here. */
6680 /* Itbl support may require additional care here. */
6685 /* Itbl support may require additional care here. */
6698 /* Itbl support may require additional care here. */
6703 /* Itbl support may require additional care here. */
6708 /* Itbl support may require additional care here. */
6728 if (breg == treg || coproc || lr)
6749 /* Itbl support may require additional care here. */
6754 /* Itbl support may require additional care here. */
6759 /* Itbl support may require additional care here. */
6764 /* Itbl support may require additional care here. */
6788 /* Itbl support may require additional care here. */
6792 /* Itbl support may require additional care here. */
6797 /* Itbl support may require additional care here. */
6810 && NO_ISA_COP (mips_opts.arch)
6811 && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0)
6813 as_bad (_("Opcode not supported on this processor: %s"),
6814 mips_cpu_info_from_arch (mips_opts.arch)->name);
6818 /* Itbl support may require additional care here. */
6819 if (mask == M_LWC1_AB
6820 || mask == M_SWC1_AB
6821 || mask == M_LDC1_AB
6822 || mask == M_SDC1_AB
6826 else if (mask == M_CACHE_AB || mask == M_PREF_AB)
6833 if (offset_expr.X_op != O_constant
6834 && offset_expr.X_op != O_symbol)
6836 as_bad (_("Expression too complex"));
6837 offset_expr.X_op = O_constant;
6840 if (HAVE_32BIT_ADDRESSES
6841 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
6845 sprintf_vma (value, offset_expr.X_add_number);
6846 as_bad (_("Number (0x%s) larger than 32 bits"), value);
6849 /* A constant expression in PIC code can be handled just as it
6850 is in non PIC code. */
6851 if (offset_expr.X_op == O_constant)
6853 expr1.X_add_number = offset_expr.X_add_number;
6854 normalize_address_expr (&expr1);
6855 if (!IS_SEXT_16BIT_NUM (expr1.X_add_number))
6857 expr1.X_add_number = ((expr1.X_add_number + 0x8000)
6858 & ~(bfd_vma) 0xffff);
6859 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
6861 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6862 tempreg, tempreg, breg);
6865 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg);
6867 else if (mips_pic == NO_PIC)
6869 /* If this is a reference to a GP relative symbol, and there
6870 is no base register, we want
6871 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6872 Otherwise, if there is no base register, we want
6873 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6874 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6875 If we have a constant, we need two instructions anyhow,
6876 so we always use the latter form.
6878 If we have a base register, and this is a reference to a
6879 GP relative symbol, we want
6880 addu $tempreg,$breg,$gp
6881 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6883 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6884 addu $tempreg,$tempreg,$breg
6885 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6886 With a constant we always use the latter case.
6888 With 64bit address space and no base register and $at usable,
6890 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6891 lui $at,<sym> (BFD_RELOC_HI16_S)
6892 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6895 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6896 If we have a base register, we want
6897 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6898 lui $at,<sym> (BFD_RELOC_HI16_S)
6899 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6903 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6905 Without $at we can't generate the optimal path for superscalar
6906 processors here since this would require two temporary registers.
6907 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6908 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6910 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6912 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6913 If we have a base register, we want
6914 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6915 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6917 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6919 daddu $tempreg,$tempreg,$breg
6920 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6922 For GP relative symbols in 64bit address space we can use
6923 the same sequence as in 32bit address space. */
6924 if (HAVE_64BIT_SYMBOLS)
6926 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6927 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6929 relax_start (offset_expr.X_add_symbol);
6932 macro_build (&offset_expr, s, fmt, treg,
6933 BFD_RELOC_GPREL16, mips_gp_register);
6937 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6938 tempreg, breg, mips_gp_register);
6939 macro_build (&offset_expr, s, fmt, treg,
6940 BFD_RELOC_GPREL16, tempreg);
6945 if (used_at == 0 && mips_opts.at)
6947 macro_build (&offset_expr, "lui", "t,u", tempreg,
6948 BFD_RELOC_MIPS_HIGHEST);
6949 macro_build (&offset_expr, "lui", "t,u", AT,
6951 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6952 tempreg, BFD_RELOC_MIPS_HIGHER);
6954 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
6955 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
6956 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
6957 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
6963 macro_build (&offset_expr, "lui", "t,u", tempreg,
6964 BFD_RELOC_MIPS_HIGHEST);
6965 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6966 tempreg, BFD_RELOC_MIPS_HIGHER);
6967 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6968 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6969 tempreg, BFD_RELOC_HI16_S);
6970 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6972 macro_build (NULL, "daddu", "d,v,t",
6973 tempreg, tempreg, breg);
6974 macro_build (&offset_expr, s, fmt, treg,
6975 BFD_RELOC_LO16, tempreg);
6978 if (mips_relax.sequence)
6985 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6986 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6988 relax_start (offset_expr.X_add_symbol);
6989 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
6993 macro_build_lui (&offset_expr, tempreg);
6994 macro_build (&offset_expr, s, fmt, treg,
6995 BFD_RELOC_LO16, tempreg);
6996 if (mips_relax.sequence)
7001 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7002 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7004 relax_start (offset_expr.X_add_symbol);
7005 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7006 tempreg, breg, mips_gp_register);
7007 macro_build (&offset_expr, s, fmt, treg,
7008 BFD_RELOC_GPREL16, tempreg);
7011 macro_build_lui (&offset_expr, tempreg);
7012 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7013 tempreg, tempreg, breg);
7014 macro_build (&offset_expr, s, fmt, treg,
7015 BFD_RELOC_LO16, tempreg);
7016 if (mips_relax.sequence)
7020 else if (!mips_big_got)
7022 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7024 /* If this is a reference to an external symbol, we want
7025 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7027 <op> $treg,0($tempreg)
7029 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7031 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7032 <op> $treg,0($tempreg)
7035 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7036 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
7038 If there is a base register, we add it to $tempreg before
7039 the <op>. If there is a constant, we stick it in the
7040 <op> instruction. We don't handle constants larger than
7041 16 bits, because we have no way to load the upper 16 bits
7042 (actually, we could handle them for the subset of cases
7043 in which we are not using $at). */
7044 gas_assert (offset_expr.X_op == O_symbol);
7047 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7048 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
7050 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7051 tempreg, tempreg, breg);
7052 macro_build (&offset_expr, s, fmt, treg,
7053 BFD_RELOC_MIPS_GOT_OFST, tempreg);
7056 expr1.X_add_number = offset_expr.X_add_number;
7057 offset_expr.X_add_number = 0;
7058 if (expr1.X_add_number < -0x8000
7059 || expr1.X_add_number >= 0x8000)
7060 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7061 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7062 lw_reloc_type, mips_gp_register);
7064 relax_start (offset_expr.X_add_symbol);
7066 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
7067 tempreg, BFD_RELOC_LO16);
7070 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7071 tempreg, tempreg, breg);
7072 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
7074 else if (mips_big_got && !HAVE_NEWABI)
7078 /* If this is a reference to an external symbol, we want
7079 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7080 addu $tempreg,$tempreg,$gp
7081 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7082 <op> $treg,0($tempreg)
7084 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7086 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7087 <op> $treg,0($tempreg)
7088 If there is a base register, we add it to $tempreg before
7089 the <op>. If there is a constant, we stick it in the
7090 <op> instruction. We don't handle constants larger than
7091 16 bits, because we have no way to load the upper 16 bits
7092 (actually, we could handle them for the subset of cases
7093 in which we are not using $at). */
7094 gas_assert (offset_expr.X_op == O_symbol);
7095 expr1.X_add_number = offset_expr.X_add_number;
7096 offset_expr.X_add_number = 0;
7097 if (expr1.X_add_number < -0x8000
7098 || expr1.X_add_number >= 0x8000)
7099 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7100 gpdelay = reg_needs_delay (mips_gp_register);
7101 relax_start (offset_expr.X_add_symbol);
7102 macro_build (&offset_expr, "lui", "t,u", tempreg,
7103 BFD_RELOC_MIPS_GOT_HI16);
7104 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
7106 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7107 BFD_RELOC_MIPS_GOT_LO16, tempreg);
7110 macro_build (NULL, "nop", "");
7111 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7112 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7114 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
7115 tempreg, BFD_RELOC_LO16);
7119 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7120 tempreg, tempreg, breg);
7121 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
7123 else if (mips_big_got && HAVE_NEWABI)
7125 /* If this is a reference to an external symbol, we want
7126 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7127 add $tempreg,$tempreg,$gp
7128 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7129 <op> $treg,<ofst>($tempreg)
7130 Otherwise, for local symbols, we want:
7131 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7132 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
7133 gas_assert (offset_expr.X_op == O_symbol);
7134 expr1.X_add_number = offset_expr.X_add_number;
7135 offset_expr.X_add_number = 0;
7136 if (expr1.X_add_number < -0x8000
7137 || expr1.X_add_number >= 0x8000)
7138 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7139 relax_start (offset_expr.X_add_symbol);
7140 macro_build (&offset_expr, "lui", "t,u", tempreg,
7141 BFD_RELOC_MIPS_GOT_HI16);
7142 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
7144 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7145 BFD_RELOC_MIPS_GOT_LO16, tempreg);
7147 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7148 tempreg, tempreg, breg);
7149 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
7152 offset_expr.X_add_number = expr1.X_add_number;
7153 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7154 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
7156 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7157 tempreg, tempreg, breg);
7158 macro_build (&offset_expr, s, fmt, treg,
7159 BFD_RELOC_MIPS_GOT_OFST, tempreg);
7169 load_register (treg, &imm_expr, 0);
7173 load_register (treg, &imm_expr, 1);
7177 if (imm_expr.X_op == O_constant)
7180 load_register (AT, &imm_expr, 0);
7181 macro_build (NULL, "mtc1", "t,G", AT, treg);
7186 gas_assert (offset_expr.X_op == O_symbol
7187 && strcmp (segment_name (S_GET_SEGMENT
7188 (offset_expr.X_add_symbol)),
7190 && offset_expr.X_add_number == 0);
7191 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
7192 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
7197 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
7198 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
7199 order 32 bits of the value and the low order 32 bits are either
7200 zero or in OFFSET_EXPR. */
7201 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
7203 if (HAVE_64BIT_GPRS)
7204 load_register (treg, &imm_expr, 1);
7209 if (target_big_endian)
7221 load_register (hreg, &imm_expr, 0);
7224 if (offset_expr.X_op == O_absent)
7225 move_register (lreg, 0);
7228 gas_assert (offset_expr.X_op == O_constant);
7229 load_register (lreg, &offset_expr, 0);
7236 /* We know that sym is in the .rdata section. First we get the
7237 upper 16 bits of the address. */
7238 if (mips_pic == NO_PIC)
7240 macro_build_lui (&offset_expr, AT);
7245 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7246 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7250 /* Now we load the register(s). */
7251 if (HAVE_64BIT_GPRS)
7254 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7259 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7262 /* FIXME: How in the world do we deal with the possible
7264 offset_expr.X_add_number += 4;
7265 macro_build (&offset_expr, "lw", "t,o(b)",
7266 treg + 1, BFD_RELOC_LO16, AT);
7272 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
7273 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
7274 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
7275 the value and the low order 32 bits are either zero or in
7277 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
7280 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
7281 if (HAVE_64BIT_FPRS)
7283 gas_assert (HAVE_64BIT_GPRS);
7284 macro_build (NULL, "dmtc1", "t,S", AT, treg);
7288 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
7289 if (offset_expr.X_op == O_absent)
7290 macro_build (NULL, "mtc1", "t,G", 0, treg);
7293 gas_assert (offset_expr.X_op == O_constant);
7294 load_register (AT, &offset_expr, 0);
7295 macro_build (NULL, "mtc1", "t,G", AT, treg);
7301 gas_assert (offset_expr.X_op == O_symbol
7302 && offset_expr.X_add_number == 0);
7303 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
7304 if (strcmp (s, ".lit8") == 0)
7306 if (mips_opts.isa != ISA_MIPS1)
7308 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
7309 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
7312 breg = mips_gp_register;
7313 r = BFD_RELOC_MIPS_LITERAL;
7318 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
7320 if (mips_pic != NO_PIC)
7321 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7322 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7325 /* FIXME: This won't work for a 64 bit address. */
7326 macro_build_lui (&offset_expr, AT);
7329 if (mips_opts.isa != ISA_MIPS1)
7331 macro_build (&offset_expr, "ldc1", "T,o(b)",
7332 treg, BFD_RELOC_LO16, AT);
7341 /* Even on a big endian machine $fn comes before $fn+1. We have
7342 to adjust when loading from memory. */
7345 gas_assert (mips_opts.isa == ISA_MIPS1);
7346 macro_build (&offset_expr, "lwc1", "T,o(b)",
7347 target_big_endian ? treg + 1 : treg, r, breg);
7348 /* FIXME: A possible overflow which I don't know how to deal
7350 offset_expr.X_add_number += 4;
7351 macro_build (&offset_expr, "lwc1", "T,o(b)",
7352 target_big_endian ? treg : treg + 1, r, breg);
7356 gas_assert (mips_opts.isa == ISA_MIPS1);
7357 /* Even on a big endian machine $fn comes before $fn+1. We have
7358 to adjust when storing to memory. */
7359 macro_build (&offset_expr, "swc1", "T,o(b)",
7360 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
7361 offset_expr.X_add_number += 4;
7362 macro_build (&offset_expr, "swc1", "T,o(b)",
7363 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
7368 * The MIPS assembler seems to check for X_add_number not
7369 * being double aligned and generating:
7372 * addiu at,at,%lo(foo+1)
7375 * But, the resulting address is the same after relocation so why
7376 * generate the extra instruction?
7378 /* Itbl support may require additional care here. */
7380 if (mips_opts.isa != ISA_MIPS1)
7391 if (mips_opts.isa != ISA_MIPS1)
7399 /* Itbl support may require additional care here. */
7404 if (HAVE_64BIT_GPRS)
7415 if (HAVE_64BIT_GPRS)
7425 if (offset_expr.X_op != O_symbol
7426 && offset_expr.X_op != O_constant)
7428 as_bad (_("Expression too complex"));
7429 offset_expr.X_op = O_constant;
7432 if (HAVE_32BIT_ADDRESSES
7433 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
7437 sprintf_vma (value, offset_expr.X_add_number);
7438 as_bad (_("Number (0x%s) larger than 32 bits"), value);
7441 /* Even on a big endian machine $fn comes before $fn+1. We have
7442 to adjust when loading from memory. We set coproc if we must
7443 load $fn+1 first. */
7444 /* Itbl support may require additional care here. */
7445 if (!target_big_endian)
7448 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
7450 /* If this is a reference to a GP relative symbol, we want
7451 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
7452 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
7453 If we have a base register, we use this
7455 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
7456 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
7457 If this is not a GP relative symbol, we want
7458 lui $at,<sym> (BFD_RELOC_HI16_S)
7459 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7460 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7461 If there is a base register, we add it to $at after the
7462 lui instruction. If there is a constant, we always use
7464 if (offset_expr.X_op == O_symbol
7465 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7466 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7468 relax_start (offset_expr.X_add_symbol);
7471 tempreg = mips_gp_register;
7475 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7476 AT, breg, mips_gp_register);
7481 /* Itbl support may require additional care here. */
7482 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7483 BFD_RELOC_GPREL16, tempreg);
7484 offset_expr.X_add_number += 4;
7486 /* Set mips_optimize to 2 to avoid inserting an
7488 hold_mips_optimize = mips_optimize;
7490 /* Itbl support may require additional care here. */
7491 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7492 BFD_RELOC_GPREL16, tempreg);
7493 mips_optimize = hold_mips_optimize;
7497 offset_expr.X_add_number -= 4;
7500 macro_build_lui (&offset_expr, AT);
7502 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7503 /* Itbl support may require additional care here. */
7504 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7505 BFD_RELOC_LO16, AT);
7506 /* FIXME: How do we handle overflow here? */
7507 offset_expr.X_add_number += 4;
7508 /* Itbl support may require additional care here. */
7509 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7510 BFD_RELOC_LO16, AT);
7511 if (mips_relax.sequence)
7514 else if (!mips_big_got)
7516 /* If this is a reference to an external symbol, we want
7517 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7522 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7524 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7525 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7526 If there is a base register we add it to $at before the
7527 lwc1 instructions. If there is a constant we include it
7528 in the lwc1 instructions. */
7530 expr1.X_add_number = offset_expr.X_add_number;
7531 if (expr1.X_add_number < -0x8000
7532 || expr1.X_add_number >= 0x8000 - 4)
7533 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7534 load_got_offset (AT, &offset_expr);
7537 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7539 /* Set mips_optimize to 2 to avoid inserting an undesired
7541 hold_mips_optimize = mips_optimize;
7544 /* Itbl support may require additional care here. */
7545 relax_start (offset_expr.X_add_symbol);
7546 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
7547 BFD_RELOC_LO16, AT);
7548 expr1.X_add_number += 4;
7549 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
7550 BFD_RELOC_LO16, AT);
7552 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7553 BFD_RELOC_LO16, AT);
7554 offset_expr.X_add_number += 4;
7555 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7556 BFD_RELOC_LO16, AT);
7559 mips_optimize = hold_mips_optimize;
7561 else if (mips_big_got)
7565 /* If this is a reference to an external symbol, we want
7566 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7568 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
7573 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7575 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7576 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7577 If there is a base register we add it to $at before the
7578 lwc1 instructions. If there is a constant we include it
7579 in the lwc1 instructions. */
7581 expr1.X_add_number = offset_expr.X_add_number;
7582 offset_expr.X_add_number = 0;
7583 if (expr1.X_add_number < -0x8000
7584 || expr1.X_add_number >= 0x8000 - 4)
7585 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7586 gpdelay = reg_needs_delay (mips_gp_register);
7587 relax_start (offset_expr.X_add_symbol);
7588 macro_build (&offset_expr, "lui", "t,u",
7589 AT, BFD_RELOC_MIPS_GOT_HI16);
7590 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7591 AT, AT, mips_gp_register);
7592 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7593 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
7596 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7597 /* Itbl support may require additional care here. */
7598 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
7599 BFD_RELOC_LO16, AT);
7600 expr1.X_add_number += 4;
7602 /* Set mips_optimize to 2 to avoid inserting an undesired
7604 hold_mips_optimize = mips_optimize;
7606 /* Itbl support may require additional care here. */
7607 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
7608 BFD_RELOC_LO16, AT);
7609 mips_optimize = hold_mips_optimize;
7610 expr1.X_add_number -= 4;
7613 offset_expr.X_add_number = expr1.X_add_number;
7615 macro_build (NULL, "nop", "");
7616 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7617 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7620 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7621 /* Itbl support may require additional care here. */
7622 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7623 BFD_RELOC_LO16, AT);
7624 offset_expr.X_add_number += 4;
7626 /* Set mips_optimize to 2 to avoid inserting an undesired
7628 hold_mips_optimize = mips_optimize;
7630 /* Itbl support may require additional care here. */
7631 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7632 BFD_RELOC_LO16, AT);
7633 mips_optimize = hold_mips_optimize;
7642 s = HAVE_64BIT_GPRS ? "ld" : "lw";
7645 s = HAVE_64BIT_GPRS ? "sd" : "sw";
7647 macro_build (&offset_expr, s, "t,o(b)", treg,
7648 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
7650 if (!HAVE_64BIT_GPRS)
7652 offset_expr.X_add_number += 4;
7653 macro_build (&offset_expr, s, "t,o(b)", treg + 1,
7654 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
7659 /* New code added to support COPZ instructions.
7660 This code builds table entries out of the macros in mip_opcodes.
7661 R4000 uses interlocks to handle coproc delays.
7662 Other chips (like the R3000) require nops to be inserted for delays.
7664 FIXME: Currently, we require that the user handle delays.
7665 In order to fill delay slots for non-interlocked chips,
7666 we must have a way to specify delays based on the coprocessor.
7667 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7668 What are the side-effects of the cop instruction?
7669 What cache support might we have and what are its effects?
7670 Both coprocessor & memory require delays. how long???
7671 What registers are read/set/modified?
7673 If an itbl is provided to interpret cop instructions,
7674 this knowledge can be encoded in the itbl spec. */
7688 if (NO_ISA_COP (mips_opts.arch)
7689 && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0)
7691 as_bad (_("opcode not supported on this processor: %s"),
7692 mips_cpu_info_from_arch (mips_opts.arch)->name);
7696 /* For now we just do C (same as Cz). The parameter will be
7697 stored in insn_opcode by mips_ip. */
7698 macro_build (NULL, s, "C", ip->insn_opcode);
7702 move_register (dreg, sreg);
7708 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
7709 macro_build (NULL, "mflo", "d", dreg);
7715 /* The MIPS assembler some times generates shifts and adds. I'm
7716 not trying to be that fancy. GCC should do this for us
7719 load_register (AT, &imm_expr, dbl);
7720 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
7721 macro_build (NULL, "mflo", "d", dreg);
7737 load_register (AT, &imm_expr, dbl);
7738 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
7739 macro_build (NULL, "mflo", "d", dreg);
7740 macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
7741 macro_build (NULL, "mfhi", "d", AT);
7743 macro_build (NULL, "tne", "s,t,q", dreg, AT, 6);
7746 expr1.X_add_number = 8;
7747 macro_build (&expr1, "beq", "s,t,p", dreg, AT);
7748 macro_build (NULL, "nop", "");
7749 macro_build (NULL, "break", "c", 6);
7752 macro_build (NULL, "mflo", "d", dreg);
7768 load_register (AT, &imm_expr, dbl);
7769 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
7770 sreg, imm ? AT : treg);
7771 macro_build (NULL, "mfhi", "d", AT);
7772 macro_build (NULL, "mflo", "d", dreg);
7774 macro_build (NULL, "tne", "s,t,q", AT, ZERO, 6);
7777 expr1.X_add_number = 8;
7778 macro_build (&expr1, "beq", "s,t,p", AT, ZERO);
7779 macro_build (NULL, "nop", "");
7780 macro_build (NULL, "break", "c", 6);
7786 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7797 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
7798 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
7802 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
7803 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
7804 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
7805 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7809 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7820 macro_build (NULL, "negu", "d,w", tempreg, treg);
7821 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
7825 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
7826 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
7827 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
7828 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7837 if (imm_expr.X_op != O_constant)
7838 as_bad (_("Improper rotate count"));
7839 rot = imm_expr.X_add_number & 0x3f;
7840 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7842 rot = (64 - rot) & 0x3f;
7844 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7846 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7851 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7854 l = (rot < 0x20) ? "dsll" : "dsll32";
7855 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
7858 macro_build (NULL, l, "d,w,<", AT, sreg, rot);
7859 macro_build (NULL, rr, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7860 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7868 if (imm_expr.X_op != O_constant)
7869 as_bad (_("Improper rotate count"));
7870 rot = imm_expr.X_add_number & 0x1f;
7871 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7873 macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f);
7878 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7882 macro_build (NULL, "sll", "d,w,<", AT, sreg, rot);
7883 macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7884 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7889 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7891 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
7895 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
7896 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
7897 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
7898 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7902 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7904 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
7908 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
7909 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
7910 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
7911 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7920 if (imm_expr.X_op != O_constant)
7921 as_bad (_("Improper rotate count"));
7922 rot = imm_expr.X_add_number & 0x3f;
7923 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7926 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7928 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7933 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7936 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
7937 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7940 macro_build (NULL, rr, "d,w,<", AT, sreg, rot);
7941 macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7942 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7950 if (imm_expr.X_op != O_constant)
7951 as_bad (_("Improper rotate count"));
7952 rot = imm_expr.X_add_number & 0x1f;
7953 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7955 macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot);
7960 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7964 macro_build (NULL, "srl", "d,w,<", AT, sreg, rot);
7965 macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7966 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7972 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
7974 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7977 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7978 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7983 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7985 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7990 as_warn (_("Instruction %s: result is always false"),
7992 move_register (dreg, 0);
7995 if (CPU_HAS_SEQ (mips_opts.arch)
7996 && -512 <= imm_expr.X_add_number
7997 && imm_expr.X_add_number < 512)
7999 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
8000 (int) imm_expr.X_add_number);
8003 if (imm_expr.X_op == O_constant
8004 && imm_expr.X_add_number >= 0
8005 && imm_expr.X_add_number < 0x10000)
8007 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
8009 else if (imm_expr.X_op == O_constant
8010 && imm_expr.X_add_number > -0x8000
8011 && imm_expr.X_add_number < 0)
8013 imm_expr.X_add_number = -imm_expr.X_add_number;
8014 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
8015 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
8017 else if (CPU_HAS_SEQ (mips_opts.arch))
8020 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8021 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
8026 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8027 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
8030 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
8033 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
8039 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
8040 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
8043 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
8045 if (imm_expr.X_op == O_constant
8046 && imm_expr.X_add_number >= -0x8000
8047 && imm_expr.X_add_number < 0x8000)
8049 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
8050 dreg, sreg, BFD_RELOC_LO16);
8054 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8055 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
8059 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
8062 case M_SGT: /* sreg > treg <==> treg < sreg */
8068 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
8071 case M_SGT_I: /* sreg > I <==> I < sreg */
8078 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8079 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
8082 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
8088 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
8089 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
8092 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
8099 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8100 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
8101 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
8105 if (imm_expr.X_op == O_constant
8106 && imm_expr.X_add_number >= -0x8000
8107 && imm_expr.X_add_number < 0x8000)
8109 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
8113 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8114 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
8118 if (imm_expr.X_op == O_constant
8119 && imm_expr.X_add_number >= -0x8000
8120 && imm_expr.X_add_number < 0x8000)
8122 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
8127 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8128 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
8133 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
8135 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
8138 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
8139 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
8144 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
8146 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
8151 as_warn (_("Instruction %s: result is always true"),
8153 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
8154 dreg, 0, BFD_RELOC_LO16);
8157 if (CPU_HAS_SEQ (mips_opts.arch)
8158 && -512 <= imm_expr.X_add_number
8159 && imm_expr.X_add_number < 512)
8161 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
8162 (int) imm_expr.X_add_number);
8165 if (imm_expr.X_op == O_constant
8166 && imm_expr.X_add_number >= 0
8167 && imm_expr.X_add_number < 0x10000)
8169 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
8171 else if (imm_expr.X_op == O_constant
8172 && imm_expr.X_add_number > -0x8000
8173 && imm_expr.X_add_number < 0)
8175 imm_expr.X_add_number = -imm_expr.X_add_number;
8176 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
8177 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
8179 else if (CPU_HAS_SEQ (mips_opts.arch))
8182 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8183 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
8188 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8189 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
8192 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
8198 if (imm_expr.X_op == O_constant
8199 && imm_expr.X_add_number > -0x8000
8200 && imm_expr.X_add_number <= 0x8000)
8202 imm_expr.X_add_number = -imm_expr.X_add_number;
8203 macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j",
8204 dreg, sreg, BFD_RELOC_LO16);
8208 load_register (AT, &imm_expr, dbl);
8209 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
8215 if (imm_expr.X_op == O_constant
8216 && imm_expr.X_add_number > -0x8000
8217 && imm_expr.X_add_number <= 0x8000)
8219 imm_expr.X_add_number = -imm_expr.X_add_number;
8220 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j",
8221 dreg, sreg, BFD_RELOC_LO16);
8225 load_register (AT, &imm_expr, dbl);
8226 macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
8248 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8249 macro_build (NULL, s, "s,t", sreg, AT);
8254 gas_assert (mips_opts.isa == ISA_MIPS1);
8256 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
8257 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
8260 * Is the double cfc1 instruction a bug in the mips assembler;
8261 * or is there a reason for it?
8264 macro_build (NULL, "cfc1", "t,G", treg, RA);
8265 macro_build (NULL, "cfc1", "t,G", treg, RA);
8266 macro_build (NULL, "nop", "");
8267 expr1.X_add_number = 3;
8268 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
8269 expr1.X_add_number = 2;
8270 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
8271 macro_build (NULL, "ctc1", "t,G", AT, RA);
8272 macro_build (NULL, "nop", "");
8273 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
8275 macro_build (NULL, "ctc1", "t,G", treg, RA);
8276 macro_build (NULL, "nop", "");
8287 if (offset_expr.X_add_number >= 0x7fff)
8288 as_bad (_("Operand overflow"));
8289 if (!target_big_endian)
8290 ++offset_expr.X_add_number;
8291 macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg);
8292 if (!target_big_endian)
8293 --offset_expr.X_add_number;
8295 ++offset_expr.X_add_number;
8296 macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg);
8297 macro_build (NULL, "sll", "d,w,<", AT, AT, 8);
8298 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8311 if (offset_expr.X_add_number >= 0x8000 - off)
8312 as_bad (_("Operand overflow"));
8320 if (!target_big_endian)
8321 offset_expr.X_add_number += off;
8322 macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
8323 if (!target_big_endian)
8324 offset_expr.X_add_number -= off;
8326 offset_expr.X_add_number += off;
8327 macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
8329 /* If necessary, move the result in tempreg to the final destination. */
8330 if (treg == tempreg)
8332 /* Protect second load's delay slot. */
8334 move_register (treg, tempreg);
8348 load_address (AT, &offset_expr, &used_at);
8350 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8351 if (!target_big_endian)
8352 expr1.X_add_number = off;
8354 expr1.X_add_number = 0;
8355 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8356 if (!target_big_endian)
8357 expr1.X_add_number = 0;
8359 expr1.X_add_number = off;
8360 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8366 load_address (AT, &offset_expr, &used_at);
8368 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8369 if (target_big_endian)
8370 expr1.X_add_number = 0;
8371 macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
8372 treg, BFD_RELOC_LO16, AT);
8373 if (target_big_endian)
8374 expr1.X_add_number = 1;
8376 expr1.X_add_number = 0;
8377 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
8378 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
8379 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8384 if (offset_expr.X_add_number >= 0x7fff)
8385 as_bad (_("Operand overflow"));
8386 if (target_big_endian)
8387 ++offset_expr.X_add_number;
8388 macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg);
8389 macro_build (NULL, "srl", "d,w,<", AT, treg, 8);
8390 if (target_big_endian)
8391 --offset_expr.X_add_number;
8393 ++offset_expr.X_add_number;
8394 macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg);
8407 if (offset_expr.X_add_number >= 0x8000 - off)
8408 as_bad (_("Operand overflow"));
8409 if (!target_big_endian)
8410 offset_expr.X_add_number += off;
8411 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8412 if (!target_big_endian)
8413 offset_expr.X_add_number -= off;
8415 offset_expr.X_add_number += off;
8416 macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8430 load_address (AT, &offset_expr, &used_at);
8432 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8433 if (!target_big_endian)
8434 expr1.X_add_number = off;
8436 expr1.X_add_number = 0;
8437 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8438 if (!target_big_endian)
8439 expr1.X_add_number = 0;
8441 expr1.X_add_number = off;
8442 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8447 load_address (AT, &offset_expr, &used_at);
8449 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8450 if (!target_big_endian)
8451 expr1.X_add_number = 0;
8452 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8453 macro_build (NULL, "srl", "d,w,<", treg, treg, 8);
8454 if (!target_big_endian)
8455 expr1.X_add_number = 1;
8457 expr1.X_add_number = 0;
8458 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8459 if (!target_big_endian)
8460 expr1.X_add_number = 0;
8462 expr1.X_add_number = 1;
8463 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
8464 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
8465 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8469 /* FIXME: Check if this is one of the itbl macros, since they
8470 are added dynamically. */
8471 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
8474 if (!mips_opts.at && used_at)
8475 as_bad (_("Macro used $at after \".set noat\""));
8478 /* Implement macros in mips16 mode. */
8481 mips16_macro (struct mips_cl_insn *ip)
8484 int xreg, yreg, zreg, tmp;
8487 const char *s, *s2, *s3;
8489 mask = ip->insn_mo->mask;
8491 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
8492 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
8493 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
8495 expr1.X_op = O_constant;
8496 expr1.X_op_symbol = NULL;
8497 expr1.X_add_symbol = NULL;
8498 expr1.X_add_number = 1;
8518 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
8519 expr1.X_add_number = 2;
8520 macro_build (&expr1, "bnez", "x,p", yreg);
8521 macro_build (NULL, "break", "6", 7);
8523 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
8524 since that causes an overflow. We should do that as well,
8525 but I don't see how to do the comparisons without a temporary
8528 macro_build (NULL, s, "x", zreg);
8548 macro_build (NULL, s, "0,x,y", xreg, yreg);
8549 expr1.X_add_number = 2;
8550 macro_build (&expr1, "bnez", "x,p", yreg);
8551 macro_build (NULL, "break", "6", 7);
8553 macro_build (NULL, s2, "x", zreg);
8559 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
8560 macro_build (NULL, "mflo", "x", zreg);
8568 if (imm_expr.X_op != O_constant)
8569 as_bad (_("Unsupported large constant"));
8570 imm_expr.X_add_number = -imm_expr.X_add_number;
8571 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
8575 if (imm_expr.X_op != O_constant)
8576 as_bad (_("Unsupported large constant"));
8577 imm_expr.X_add_number = -imm_expr.X_add_number;
8578 macro_build (&imm_expr, "addiu", "x,k", xreg);
8582 if (imm_expr.X_op != O_constant)
8583 as_bad (_("Unsupported large constant"));
8584 imm_expr.X_add_number = -imm_expr.X_add_number;
8585 macro_build (&imm_expr, "daddiu", "y,j", yreg);
8607 goto do_reverse_branch;
8611 goto do_reverse_branch;
8623 goto do_reverse_branch;
8634 macro_build (NULL, s, "x,y", xreg, yreg);
8635 macro_build (&offset_expr, s2, "p");
8662 goto do_addone_branch_i;
8667 goto do_addone_branch_i;
8682 goto do_addone_branch_i;
8689 if (imm_expr.X_op != O_constant)
8690 as_bad (_("Unsupported large constant"));
8691 ++imm_expr.X_add_number;
8694 macro_build (&imm_expr, s, s3, xreg);
8695 macro_build (&offset_expr, s2, "p");
8699 expr1.X_add_number = 0;
8700 macro_build (&expr1, "slti", "x,8", yreg);
8702 move_register (xreg, yreg);
8703 expr1.X_add_number = 2;
8704 macro_build (&expr1, "bteqz", "p");
8705 macro_build (NULL, "neg", "x,w", xreg, xreg);
8709 /* For consistency checking, verify that all bits are specified either
8710 by the match/mask part of the instruction definition, or by the
8713 validate_mips_insn (const struct mips_opcode *opc)
8715 const char *p = opc->args;
8717 unsigned long used_bits = opc->mask;
8719 if ((used_bits & opc->match) != opc->match)
8721 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8722 opc->name, opc->args);
8725 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8735 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
8736 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
8737 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
8738 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
8739 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8740 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8741 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8742 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
8743 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8744 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8745 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8746 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8747 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8749 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8750 case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
8751 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8752 case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
8753 case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
8754 case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
8755 case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
8756 case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
8757 case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
8758 case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
8759 case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break;
8760 case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break;
8761 case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break;
8762 case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break;
8763 case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break;
8766 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8767 c, opc->name, opc->args);
8771 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8772 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8774 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
8775 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
8776 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8777 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8779 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8780 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8782 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
8783 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8785 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
8786 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
8787 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
8788 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
8789 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8790 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
8791 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8792 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8793 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8794 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8795 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8796 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8797 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8798 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
8799 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8800 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
8801 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8803 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
8804 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8805 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8806 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
8808 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8809 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8810 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
8811 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8812 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8813 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8814 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8815 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8816 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8819 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
8820 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
8821 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8822 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
8823 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
8826 case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8827 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
8828 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
8829 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
8830 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
8831 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8832 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
8833 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
8834 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
8835 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
8836 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
8837 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
8838 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
8839 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
8840 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
8841 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
8842 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
8843 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8845 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8846 c, opc->name, opc->args);
8850 if (used_bits != 0xffffffff)
8852 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8853 ~used_bits & 0xffffffff, opc->name, opc->args);
8859 /* UDI immediates. */
8867 static const struct mips_immed mips_immed[] = {
8868 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
8869 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
8870 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
8871 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
8875 /* Check whether an odd floating-point register is allowed. */
8877 mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
8879 const char *s = insn->name;
8881 if (insn->pinfo == INSN_MACRO)
8882 /* Let a macro pass, we'll catch it later when it is expanded. */
8885 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa))
8887 /* Allow odd registers for single-precision ops. */
8888 switch (insn->pinfo & (FP_S | FP_D))
8892 return 1; /* both single precision - ok */
8894 return 0; /* both double precision - fail */
8899 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
8900 s = strchr (insn->name, '.');
8902 s = s != NULL ? strchr (s + 1, '.') : NULL;
8903 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
8906 /* Single-precision coprocessor loads and moves are OK too. */
8907 if ((insn->pinfo & FP_S)
8908 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
8909 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
8915 /* This routine assembles an instruction into its binary format. As a
8916 side effect, it sets one of the global variables imm_reloc or
8917 offset_reloc to the type of relocation to do if one of the operands
8918 is an address expression. */
8921 mips_ip (char *str, struct mips_cl_insn *ip)
8926 struct mips_opcode *insn;
8929 unsigned int lastregno;
8930 unsigned int lastpos = 0;
8931 unsigned int limlo, limhi;
8934 offsetT min_range, max_range;
8940 /* If the instruction contains a '.', we first try to match an instruction
8941 including the '.'. Then we try again without the '.'. */
8943 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
8946 /* If we stopped on whitespace, then replace the whitespace with null for
8947 the call to hash_find. Save the character we replaced just in case we
8948 have to re-parse the instruction. */
8955 insn = (struct mips_opcode *) hash_find (op_hash, str);
8957 /* If we didn't find the instruction in the opcode table, try again, but
8958 this time with just the instruction up to, but not including the
8962 /* Restore the character we overwrite above (if any). */
8966 /* Scan up to the first '.' or whitespace. */
8968 *s != '\0' && *s != '.' && !ISSPACE (*s);
8972 /* If we did not find a '.', then we can quit now. */
8975 insn_error = _("Unrecognized opcode");
8979 /* Lookup the instruction in the hash table. */
8981 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
8983 insn_error = _("Unrecognized opcode");
8993 gas_assert (strcmp (insn->name, str) == 0);
8995 ok = is_opcode_valid (insn);
8998 if (insn + 1 < &mips_opcodes[NUMOPCODES]
8999 && strcmp (insn->name, insn[1].name) == 0)
9008 static char buf[100];
9010 _("opcode not supported on this processor: %s (%s)"),
9011 mips_cpu_info_from_arch (mips_opts.arch)->name,
9012 mips_cpu_info_from_isa (mips_opts.isa)->name);
9021 create_insn (ip, insn);
9024 lastregno = 0xffffffff;
9025 for (args = insn->args;; ++args)
9029 s += strspn (s, " \t");
9033 case '\0': /* end of args */
9038 case '2': /* DSP 2-bit unsigned immediate in bit 11. */
9039 my_getExpression (&imm_expr, s);
9040 check_absolute_expr (ip, &imm_expr);
9041 if ((unsigned long) imm_expr.X_add_number != 1
9042 && (unsigned long) imm_expr.X_add_number != 3)
9044 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
9045 (unsigned long) imm_expr.X_add_number);
9047 INSERT_OPERAND (BP, *ip, imm_expr.X_add_number);
9048 imm_expr.X_op = O_absent;
9052 case '3': /* DSP 3-bit unsigned immediate in bit 21. */
9053 my_getExpression (&imm_expr, s);
9054 check_absolute_expr (ip, &imm_expr);
9055 if (imm_expr.X_add_number & ~OP_MASK_SA3)
9057 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9058 OP_MASK_SA3, (unsigned long) imm_expr.X_add_number);
9060 INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number);
9061 imm_expr.X_op = O_absent;
9065 case '4': /* DSP 4-bit unsigned immediate in bit 21. */
9066 my_getExpression (&imm_expr, s);
9067 check_absolute_expr (ip, &imm_expr);
9068 if (imm_expr.X_add_number & ~OP_MASK_SA4)
9070 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9071 OP_MASK_SA4, (unsigned long) imm_expr.X_add_number);
9073 INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number);
9074 imm_expr.X_op = O_absent;
9078 case '5': /* DSP 8-bit unsigned immediate in bit 16. */
9079 my_getExpression (&imm_expr, s);
9080 check_absolute_expr (ip, &imm_expr);
9081 if (imm_expr.X_add_number & ~OP_MASK_IMM8)
9083 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9084 OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number);
9086 INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number);
9087 imm_expr.X_op = O_absent;
9091 case '6': /* DSP 5-bit unsigned immediate in bit 21. */
9092 my_getExpression (&imm_expr, s);
9093 check_absolute_expr (ip, &imm_expr);
9094 if (imm_expr.X_add_number & ~OP_MASK_RS)
9096 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9097 OP_MASK_RS, (unsigned long) imm_expr.X_add_number);
9099 INSERT_OPERAND (RS, *ip, imm_expr.X_add_number);
9100 imm_expr.X_op = O_absent;
9104 case '7': /* Four DSP accumulators in bits 11,12. */
9105 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9106 s[3] >= '0' && s[3] <= '3')
9110 INSERT_OPERAND (DSPACC, *ip, regno);
9114 as_bad (_("Invalid dsp acc register"));
9117 case '8': /* DSP 6-bit unsigned immediate in bit 11. */
9118 my_getExpression (&imm_expr, s);
9119 check_absolute_expr (ip, &imm_expr);
9120 if (imm_expr.X_add_number & ~OP_MASK_WRDSP)
9122 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9124 (unsigned long) imm_expr.X_add_number);
9126 INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number);
9127 imm_expr.X_op = O_absent;
9131 case '9': /* Four DSP accumulators in bits 21,22. */
9132 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9133 s[3] >= '0' && s[3] <= '3')
9137 INSERT_OPERAND (DSPACC_S, *ip, regno);
9141 as_bad (_("Invalid dsp acc register"));
9144 case '0': /* DSP 6-bit signed immediate in bit 20. */
9145 my_getExpression (&imm_expr, s);
9146 check_absolute_expr (ip, &imm_expr);
9147 min_range = -((OP_MASK_DSPSFT + 1) >> 1);
9148 max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1;
9149 if (imm_expr.X_add_number < min_range ||
9150 imm_expr.X_add_number > max_range)
9152 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
9153 (long) min_range, (long) max_range,
9154 (long) imm_expr.X_add_number);
9156 INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number);
9157 imm_expr.X_op = O_absent;
9161 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
9162 my_getExpression (&imm_expr, s);
9163 check_absolute_expr (ip, &imm_expr);
9164 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
9166 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9168 (unsigned long) imm_expr.X_add_number);
9170 INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number);
9171 imm_expr.X_op = O_absent;
9175 case ':': /* DSP 7-bit signed immediate in bit 19. */
9176 my_getExpression (&imm_expr, s);
9177 check_absolute_expr (ip, &imm_expr);
9178 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
9179 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
9180 if (imm_expr.X_add_number < min_range ||
9181 imm_expr.X_add_number > max_range)
9183 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
9184 (long) min_range, (long) max_range,
9185 (long) imm_expr.X_add_number);
9187 INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number);
9188 imm_expr.X_op = O_absent;
9192 case '@': /* DSP 10-bit signed immediate in bit 16. */
9193 my_getExpression (&imm_expr, s);
9194 check_absolute_expr (ip, &imm_expr);
9195 min_range = -((OP_MASK_IMM10 + 1) >> 1);
9196 max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1;
9197 if (imm_expr.X_add_number < min_range ||
9198 imm_expr.X_add_number > max_range)
9200 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
9201 (long) min_range, (long) max_range,
9202 (long) imm_expr.X_add_number);
9204 INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number);
9205 imm_expr.X_op = O_absent;
9209 case '!': /* MT usermode flag bit. */
9210 my_getExpression (&imm_expr, s);
9211 check_absolute_expr (ip, &imm_expr);
9212 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
9213 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
9214 (unsigned long) imm_expr.X_add_number);
9215 INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number);
9216 imm_expr.X_op = O_absent;
9220 case '$': /* MT load high flag bit. */
9221 my_getExpression (&imm_expr, s);
9222 check_absolute_expr (ip, &imm_expr);
9223 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
9224 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
9225 (unsigned long) imm_expr.X_add_number);
9226 INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number);
9227 imm_expr.X_op = O_absent;
9231 case '*': /* Four DSP accumulators in bits 18,19. */
9232 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9233 s[3] >= '0' && s[3] <= '3')
9237 INSERT_OPERAND (MTACC_T, *ip, regno);
9241 as_bad (_("Invalid dsp/smartmips acc register"));
9244 case '&': /* Four DSP accumulators in bits 13,14. */
9245 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9246 s[3] >= '0' && s[3] <= '3')
9250 INSERT_OPERAND (MTACC_D, *ip, regno);
9254 as_bad (_("Invalid dsp/smartmips acc register"));
9266 INSERT_OPERAND (RS, *ip, lastregno);
9270 INSERT_OPERAND (RT, *ip, lastregno);
9274 INSERT_OPERAND (FT, *ip, lastregno);
9278 INSERT_OPERAND (FS, *ip, lastregno);
9284 /* Handle optional base register.
9285 Either the base register is omitted or
9286 we must have a left paren. */
9287 /* This is dependent on the next operand specifier
9288 is a base register specification. */
9289 gas_assert (args[1] == 'b');
9293 case ')': /* These must match exactly. */
9300 case '+': /* Opcode extension character. */
9303 case '1': /* UDI immediates. */
9308 const struct mips_immed *imm = mips_immed;
9310 while (imm->type && imm->type != *args)
9314 my_getExpression (&imm_expr, s);
9315 check_absolute_expr (ip, &imm_expr);
9316 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
9318 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
9319 imm->desc ? imm->desc : ip->insn_mo->name,
9320 (unsigned long) imm_expr.X_add_number,
9321 (unsigned long) imm_expr.X_add_number);
9322 imm_expr.X_add_number &= imm->mask;
9324 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
9326 imm_expr.X_op = O_absent;
9331 case 'A': /* ins/ext position, becomes LSB. */
9340 my_getExpression (&imm_expr, s);
9341 check_absolute_expr (ip, &imm_expr);
9342 if ((unsigned long) imm_expr.X_add_number < limlo
9343 || (unsigned long) imm_expr.X_add_number > limhi)
9345 as_bad (_("Improper position (%lu)"),
9346 (unsigned long) imm_expr.X_add_number);
9347 imm_expr.X_add_number = limlo;
9349 lastpos = imm_expr.X_add_number;
9350 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9351 imm_expr.X_op = O_absent;
9355 case 'B': /* ins size, becomes MSB. */
9364 my_getExpression (&imm_expr, s);
9365 check_absolute_expr (ip, &imm_expr);
9366 /* Check for negative input so that small negative numbers
9367 will not succeed incorrectly. The checks against
9368 (pos+size) transitively check "size" itself,
9369 assuming that "pos" is reasonable. */
9370 if ((long) imm_expr.X_add_number < 0
9371 || ((unsigned long) imm_expr.X_add_number
9373 || ((unsigned long) imm_expr.X_add_number
9376 as_bad (_("Improper insert size (%lu, position %lu)"),
9377 (unsigned long) imm_expr.X_add_number,
9378 (unsigned long) lastpos);
9379 imm_expr.X_add_number = limlo - lastpos;
9381 INSERT_OPERAND (INSMSB, *ip,
9382 lastpos + imm_expr.X_add_number - 1);
9383 imm_expr.X_op = O_absent;
9387 case 'C': /* ext size, becomes MSBD. */
9400 my_getExpression (&imm_expr, s);
9401 check_absolute_expr (ip, &imm_expr);
9402 /* Check for negative input so that small negative numbers
9403 will not succeed incorrectly. The checks against
9404 (pos+size) transitively check "size" itself,
9405 assuming that "pos" is reasonable. */
9406 if ((long) imm_expr.X_add_number < 0
9407 || ((unsigned long) imm_expr.X_add_number
9409 || ((unsigned long) imm_expr.X_add_number
9412 as_bad (_("Improper extract size (%lu, position %lu)"),
9413 (unsigned long) imm_expr.X_add_number,
9414 (unsigned long) lastpos);
9415 imm_expr.X_add_number = limlo - lastpos;
9417 INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1);
9418 imm_expr.X_op = O_absent;
9423 /* +D is for disassembly only; never match. */
9427 /* "+I" is like "I", except that imm2_expr is used. */
9428 my_getExpression (&imm2_expr, s);
9429 if (imm2_expr.X_op != O_big
9430 && imm2_expr.X_op != O_constant)
9431 insn_error = _("absolute expression required");
9432 if (HAVE_32BIT_GPRS)
9433 normalize_constant_expr (&imm2_expr);
9437 case 'T': /* Coprocessor register. */
9438 /* +T is for disassembly only; never match. */
9441 case 't': /* Coprocessor register number. */
9442 if (s[0] == '$' && ISDIGIT (s[1]))
9452 while (ISDIGIT (*s));
9454 as_bad (_("Invalid register number (%d)"), regno);
9457 INSERT_OPERAND (RT, *ip, regno);
9462 as_bad (_("Invalid coprocessor 0 register number"));
9466 /* bbit[01] and bbit[01]32 bit index. Give error if index
9467 is not in the valid range. */
9468 my_getExpression (&imm_expr, s);
9469 check_absolute_expr (ip, &imm_expr);
9470 if ((unsigned) imm_expr.X_add_number > 31)
9472 as_bad (_("Improper bit index (%lu)"),
9473 (unsigned long) imm_expr.X_add_number);
9474 imm_expr.X_add_number = 0;
9476 INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number);
9477 imm_expr.X_op = O_absent;
9482 /* bbit[01] bit index when bbit is used but we generate
9483 bbit[01]32 because the index is over 32. Move to the
9484 next candidate if index is not in the valid range. */
9485 my_getExpression (&imm_expr, s);
9486 check_absolute_expr (ip, &imm_expr);
9487 if ((unsigned) imm_expr.X_add_number < 32
9488 || (unsigned) imm_expr.X_add_number > 63)
9490 INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number - 32);
9491 imm_expr.X_op = O_absent;
9496 /* cins, cins32, exts and exts32 position field. Give error
9497 if it's not in the valid range. */
9498 my_getExpression (&imm_expr, s);
9499 check_absolute_expr (ip, &imm_expr);
9500 if ((unsigned) imm_expr.X_add_number > 31)
9502 as_bad (_("Improper position (%lu)"),
9503 (unsigned long) imm_expr.X_add_number);
9504 imm_expr.X_add_number = 0;
9506 /* Make the pos explicit to simplify +S. */
9507 lastpos = imm_expr.X_add_number + 32;
9508 INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number);
9509 imm_expr.X_op = O_absent;
9514 /* cins, cins32, exts and exts32 position field. Move to
9515 the next candidate if it's not in the valid range. */
9516 my_getExpression (&imm_expr, s);
9517 check_absolute_expr (ip, &imm_expr);
9518 if ((unsigned) imm_expr.X_add_number < 32
9519 || (unsigned) imm_expr.X_add_number > 63)
9521 lastpos = imm_expr.X_add_number;
9522 INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number - 32);
9523 imm_expr.X_op = O_absent;
9528 /* cins and exts length-minus-one field. */
9529 my_getExpression (&imm_expr, s);
9530 check_absolute_expr (ip, &imm_expr);
9531 if ((unsigned long) imm_expr.X_add_number > 31)
9533 as_bad (_("Improper size (%lu)"),
9534 (unsigned long) imm_expr.X_add_number);
9535 imm_expr.X_add_number = 0;
9537 INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number);
9538 imm_expr.X_op = O_absent;
9543 /* cins32/exts32 and cins/exts aliasing cint32/exts32
9544 length-minus-one field. */
9545 my_getExpression (&imm_expr, s);
9546 check_absolute_expr (ip, &imm_expr);
9547 if ((long) imm_expr.X_add_number < 0
9548 || (unsigned long) imm_expr.X_add_number + lastpos > 63)
9550 as_bad (_("Improper size (%lu)"),
9551 (unsigned long) imm_expr.X_add_number);
9552 imm_expr.X_add_number = 0;
9554 INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number);
9555 imm_expr.X_op = O_absent;
9560 /* seqi/snei immediate field. */
9561 my_getExpression (&imm_expr, s);
9562 check_absolute_expr (ip, &imm_expr);
9563 if ((long) imm_expr.X_add_number < -512
9564 || (long) imm_expr.X_add_number >= 512)
9566 as_bad (_("Improper immediate (%ld)"),
9567 (long) imm_expr.X_add_number);
9568 imm_expr.X_add_number = 0;
9570 INSERT_OPERAND (SEQI, *ip, imm_expr.X_add_number);
9571 imm_expr.X_op = O_absent;
9575 case 'a': /* 8-bit signed offset in bit 6 */
9576 my_getExpression (&imm_expr, s);
9577 check_absolute_expr (ip, &imm_expr);
9578 min_range = -((OP_MASK_OFFSET_A + 1) >> 1);
9579 max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1;
9580 if (imm_expr.X_add_number < min_range
9581 || imm_expr.X_add_number > max_range)
9583 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9584 (long) min_range, (long) max_range,
9585 (long) imm_expr.X_add_number);
9587 INSERT_OPERAND (OFFSET_A, *ip, imm_expr.X_add_number);
9588 imm_expr.X_op = O_absent;
9592 case 'b': /* 8-bit signed offset in bit 3 */
9593 my_getExpression (&imm_expr, s);
9594 check_absolute_expr (ip, &imm_expr);
9595 min_range = -((OP_MASK_OFFSET_B + 1) >> 1);
9596 max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1;
9597 if (imm_expr.X_add_number < min_range
9598 || imm_expr.X_add_number > max_range)
9600 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9601 (long) min_range, (long) max_range,
9602 (long) imm_expr.X_add_number);
9604 INSERT_OPERAND (OFFSET_B, *ip, imm_expr.X_add_number);
9605 imm_expr.X_op = O_absent;
9609 case 'c': /* 9-bit signed offset in bit 6 */
9610 my_getExpression (&imm_expr, s);
9611 check_absolute_expr (ip, &imm_expr);
9612 min_range = -((OP_MASK_OFFSET_C + 1) >> 1);
9613 max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1;
9614 /* We check the offset range before adjusted. */
9617 if (imm_expr.X_add_number < min_range
9618 || imm_expr.X_add_number > max_range)
9620 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9621 (long) min_range, (long) max_range,
9622 (long) imm_expr.X_add_number);
9624 if (imm_expr.X_add_number & 0xf)
9626 as_bad (_("Offset not 16 bytes alignment (%ld)"),
9627 (long) imm_expr.X_add_number);
9629 /* Right shift 4 bits to adjust the offset operand. */
9630 INSERT_OPERAND (OFFSET_C, *ip, imm_expr.X_add_number >> 4);
9631 imm_expr.X_op = O_absent;
9636 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
9638 if (regno == AT && mips_opts.at)
9640 if (mips_opts.at == ATREG)
9641 as_warn (_("used $at without \".set noat\""));
9643 as_warn (_("used $%u with \".set at=$%u\""),
9644 regno, mips_opts.at);
9646 INSERT_OPERAND (RZ, *ip, regno);
9650 if (!reg_lookup (&s, RTYPE_FPU, ®no))
9652 INSERT_OPERAND (FZ, *ip, regno);
9656 as_bad (_("Internal error: bad mips opcode "
9657 "(unknown extension operand type `+%c'): %s %s"),
9658 *args, insn->name, insn->args);
9659 /* Further processing is fruitless. */
9664 case '<': /* must be at least one digit */
9666 * According to the manual, if the shift amount is greater
9667 * than 31 or less than 0, then the shift amount should be
9668 * mod 32. In reality the mips assembler issues an error.
9669 * We issue a warning and mask out all but the low 5 bits.
9671 my_getExpression (&imm_expr, s);
9672 check_absolute_expr (ip, &imm_expr);
9673 if ((unsigned long) imm_expr.X_add_number > 31)
9674 as_warn (_("Improper shift amount (%lu)"),
9675 (unsigned long) imm_expr.X_add_number);
9676 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9677 imm_expr.X_op = O_absent;
9681 case '>': /* shift amount minus 32 */
9682 my_getExpression (&imm_expr, s);
9683 check_absolute_expr (ip, &imm_expr);
9684 if ((unsigned long) imm_expr.X_add_number < 32
9685 || (unsigned long) imm_expr.X_add_number > 63)
9687 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32);
9688 imm_expr.X_op = O_absent;
9692 case 'k': /* CACHE code. */
9693 case 'h': /* PREFX code. */
9694 case '1': /* SYNC type. */
9695 my_getExpression (&imm_expr, s);
9696 check_absolute_expr (ip, &imm_expr);
9697 if ((unsigned long) imm_expr.X_add_number > 31)
9698 as_warn (_("Invalid value for `%s' (%lu)"),
9700 (unsigned long) imm_expr.X_add_number);
9703 if (mips_fix_cn63xxp1 && strcmp ("pref", insn->name) == 0)
9704 switch (imm_expr.X_add_number)
9713 case 31: /* These are ok. */
9716 default: /* The rest must be changed to 28. */
9717 imm_expr.X_add_number = 28;
9720 INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number);
9722 else if (*args == 'h')
9723 INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number);
9725 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9726 imm_expr.X_op = O_absent;
9730 case 'c': /* BREAK code. */
9731 my_getExpression (&imm_expr, s);
9732 check_absolute_expr (ip, &imm_expr);
9733 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE)
9734 as_warn (_("Code for %s not in range 0..1023 (%lu)"),
9736 (unsigned long) imm_expr.X_add_number);
9737 INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number);
9738 imm_expr.X_op = O_absent;
9742 case 'q': /* Lower BREAK code. */
9743 my_getExpression (&imm_expr, s);
9744 check_absolute_expr (ip, &imm_expr);
9745 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2)
9746 as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
9748 (unsigned long) imm_expr.X_add_number);
9749 INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number);
9750 imm_expr.X_op = O_absent;
9754 case 'B': /* 20-bit SYSCALL/BREAK code. */
9755 my_getExpression (&imm_expr, s);
9756 check_absolute_expr (ip, &imm_expr);
9757 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
9758 as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
9760 (unsigned long) imm_expr.X_add_number);
9761 INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number);
9762 imm_expr.X_op = O_absent;
9766 case 'C': /* Coprocessor code. */
9767 my_getExpression (&imm_expr, s);
9768 check_absolute_expr (ip, &imm_expr);
9769 if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ)
9771 as_warn (_("Coproccesor code > 25 bits (%lu)"),
9772 (unsigned long) imm_expr.X_add_number);
9773 imm_expr.X_add_number &= OP_MASK_COPZ;
9775 INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number);
9776 imm_expr.X_op = O_absent;
9780 case 'J': /* 19-bit WAIT code. */
9781 my_getExpression (&imm_expr, s);
9782 check_absolute_expr (ip, &imm_expr);
9783 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
9785 as_warn (_("Illegal 19-bit code (%lu)"),
9786 (unsigned long) imm_expr.X_add_number);
9787 imm_expr.X_add_number &= OP_MASK_CODE19;
9789 INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number);
9790 imm_expr.X_op = O_absent;
9794 case 'P': /* Performance register. */
9795 my_getExpression (&imm_expr, s);
9796 check_absolute_expr (ip, &imm_expr);
9797 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
9798 as_warn (_("Invalid performance register (%lu)"),
9799 (unsigned long) imm_expr.X_add_number);
9800 INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number);
9801 imm_expr.X_op = O_absent;
9805 case 'G': /* Coprocessor destination register. */
9806 if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0)
9807 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, ®no);
9809 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
9810 INSERT_OPERAND (RD, *ip, regno);
9819 case 'b': /* Base register. */
9820 case 'd': /* Destination register. */
9821 case 's': /* Source register. */
9822 case 't': /* Target register. */
9823 case 'r': /* Both target and source. */
9824 case 'v': /* Both dest and source. */
9825 case 'w': /* Both dest and target. */
9826 case 'E': /* Coprocessor target register. */
9827 case 'K': /* RDHWR destination register. */
9828 case 'x': /* Ignore register name. */
9829 case 'z': /* Must be zero register. */
9830 case 'U': /* Destination register (CLO/CLZ). */
9831 case 'g': /* Coprocessor destination register. */
9833 if (*args == 'E' || *args == 'K')
9834 ok = reg_lookup (&s, RTYPE_NUM, ®no);
9837 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
9838 if (regno == AT && mips_opts.at)
9840 if (mips_opts.at == ATREG)
9841 as_warn (_("Used $at without \".set noat\""));
9843 as_warn (_("Used $%u with \".set at=$%u\""),
9844 regno, mips_opts.at);
9854 if (c == 'r' || c == 'v' || c == 'w')
9861 /* 'z' only matches $0. */
9862 if (c == 'z' && regno != 0)
9865 if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
9867 if (regno == lastregno)
9870 = _("Source and destination must be different");
9873 if (regno == 31 && lastregno == 0xffffffff)
9876 = _("A destination register must be supplied");
9880 /* Now that we have assembled one operand, we use the args
9881 string to figure out where it goes in the instruction. */
9888 INSERT_OPERAND (RS, *ip, regno);
9893 INSERT_OPERAND (RD, *ip, regno);
9896 INSERT_OPERAND (RD, *ip, regno);
9897 INSERT_OPERAND (RT, *ip, regno);
9902 INSERT_OPERAND (RT, *ip, regno);
9905 /* This case exists because on the r3000 trunc
9906 expands into a macro which requires a gp
9907 register. On the r6000 or r4000 it is
9908 assembled into a single instruction which
9909 ignores the register. Thus the insn version
9910 is MIPS_ISA2 and uses 'x', and the macro
9911 version is MIPS_ISA1 and uses 't'. */
9914 /* This case is for the div instruction, which
9915 acts differently if the destination argument
9916 is $0. This only matches $0, and is checked
9917 outside the switch. */
9927 INSERT_OPERAND (RS, *ip, lastregno);
9930 INSERT_OPERAND (RT, *ip, lastregno);
9935 case 'O': /* MDMX alignment immediate constant. */
9936 my_getExpression (&imm_expr, s);
9937 check_absolute_expr (ip, &imm_expr);
9938 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
9939 as_warn (_("Improper align amount (%ld), using low bits"),
9940 (long) imm_expr.X_add_number);
9941 INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number);
9942 imm_expr.X_op = O_absent;
9946 case 'Q': /* MDMX vector, element sel, or const. */
9949 /* MDMX Immediate. */
9950 my_getExpression (&imm_expr, s);
9951 check_absolute_expr (ip, &imm_expr);
9952 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
9953 as_warn (_("Invalid MDMX Immediate (%ld)"),
9954 (long) imm_expr.X_add_number);
9955 INSERT_OPERAND (FT, *ip, imm_expr.X_add_number);
9956 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
9957 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
9959 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
9960 imm_expr.X_op = O_absent;
9964 /* Not MDMX Immediate. Fall through. */
9965 case 'X': /* MDMX destination register. */
9966 case 'Y': /* MDMX source register. */
9967 case 'Z': /* MDMX target register. */
9969 case 'D': /* Floating point destination register. */
9970 case 'S': /* Floating point source register. */
9971 case 'T': /* Floating point target register. */
9972 case 'R': /* Floating point source register. */
9977 || (mips_opts.ase_mdmx
9978 && (ip->insn_mo->pinfo & FP_D)
9979 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
9980 | INSN_COPROC_MEMORY_DELAY
9981 | INSN_LOAD_COPROC_DELAY
9982 | INSN_LOAD_MEMORY_DELAY
9983 | INSN_STORE_MEMORY))))
9986 if (reg_lookup (&s, rtype, ®no))
9988 if ((regno & 1) != 0
9990 && !mips_oddfpreg_ok (ip->insn_mo, argnum))
9991 as_warn (_("Float register should be even, was %d"),
9999 if (c == 'V' || c == 'W')
10010 INSERT_OPERAND (FD, *ip, regno);
10015 INSERT_OPERAND (FS, *ip, regno);
10018 /* This is like 'Z', but also needs to fix the MDMX
10019 vector/scalar select bits. Note that the
10020 scalar immediate case is handled above. */
10023 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
10024 int max_el = (is_qh ? 3 : 7);
10026 my_getExpression(&imm_expr, s);
10027 check_absolute_expr (ip, &imm_expr);
10029 if (imm_expr.X_add_number > max_el)
10030 as_bad (_("Bad element selector %ld"),
10031 (long) imm_expr.X_add_number);
10032 imm_expr.X_add_number &= max_el;
10033 ip->insn_opcode |= (imm_expr.X_add_number
10036 imm_expr.X_op = O_absent;
10038 as_warn (_("Expecting ']' found '%s'"), s);
10044 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
10045 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
10048 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
10051 /* Fall through. */
10055 INSERT_OPERAND (FT, *ip, regno);
10058 INSERT_OPERAND (FR, *ip, regno);
10068 INSERT_OPERAND (FS, *ip, lastregno);
10071 INSERT_OPERAND (FT, *ip, lastregno);
10077 my_getExpression (&imm_expr, s);
10078 if (imm_expr.X_op != O_big
10079 && imm_expr.X_op != O_constant)
10080 insn_error = _("absolute expression required");
10081 if (HAVE_32BIT_GPRS)
10082 normalize_constant_expr (&imm_expr);
10087 my_getExpression (&offset_expr, s);
10088 normalize_address_expr (&offset_expr);
10089 *imm_reloc = BFD_RELOC_32;
10102 unsigned char temp[8];
10104 unsigned int length;
10109 /* These only appear as the last operand in an
10110 instruction, and every instruction that accepts
10111 them in any variant accepts them in all variants.
10112 This means we don't have to worry about backing out
10113 any changes if the instruction does not match.
10115 The difference between them is the size of the
10116 floating point constant and where it goes. For 'F'
10117 and 'L' the constant is 64 bits; for 'f' and 'l' it
10118 is 32 bits. Where the constant is placed is based
10119 on how the MIPS assembler does things:
10122 f -- immediate value
10125 The .lit4 and .lit8 sections are only used if
10126 permitted by the -G argument.
10128 The code below needs to know whether the target register
10129 is 32 or 64 bits wide. It relies on the fact 'f' and
10130 'F' are used with GPR-based instructions and 'l' and
10131 'L' are used with FPR-based instructions. */
10133 f64 = *args == 'F' || *args == 'L';
10134 using_gprs = *args == 'F' || *args == 'f';
10136 save_in = input_line_pointer;
10137 input_line_pointer = s;
10138 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
10140 s = input_line_pointer;
10141 input_line_pointer = save_in;
10142 if (err != NULL && *err != '\0')
10144 as_bad (_("Bad floating point constant: %s"), err);
10145 memset (temp, '\0', sizeof temp);
10146 length = f64 ? 8 : 4;
10149 gas_assert (length == (unsigned) (f64 ? 8 : 4));
10153 && (g_switch_value < 4
10154 || (temp[0] == 0 && temp[1] == 0)
10155 || (temp[2] == 0 && temp[3] == 0))))
10157 imm_expr.X_op = O_constant;
10158 if (!target_big_endian)
10159 imm_expr.X_add_number = bfd_getl32 (temp);
10161 imm_expr.X_add_number = bfd_getb32 (temp);
10163 else if (length > 4
10164 && !mips_disable_float_construction
10165 /* Constants can only be constructed in GPRs and
10166 copied to FPRs if the GPRs are at least as wide
10167 as the FPRs. Force the constant into memory if
10168 we are using 64-bit FPRs but the GPRs are only
10171 || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
10172 && ((temp[0] == 0 && temp[1] == 0)
10173 || (temp[2] == 0 && temp[3] == 0))
10174 && ((temp[4] == 0 && temp[5] == 0)
10175 || (temp[6] == 0 && temp[7] == 0)))
10177 /* The value is simple enough to load with a couple of
10178 instructions. If using 32-bit registers, set
10179 imm_expr to the high order 32 bits and offset_expr to
10180 the low order 32 bits. Otherwise, set imm_expr to
10181 the entire 64 bit constant. */
10182 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
10184 imm_expr.X_op = O_constant;
10185 offset_expr.X_op = O_constant;
10186 if (!target_big_endian)
10188 imm_expr.X_add_number = bfd_getl32 (temp + 4);
10189 offset_expr.X_add_number = bfd_getl32 (temp);
10193 imm_expr.X_add_number = bfd_getb32 (temp);
10194 offset_expr.X_add_number = bfd_getb32 (temp + 4);
10196 if (offset_expr.X_add_number == 0)
10197 offset_expr.X_op = O_absent;
10199 else if (sizeof (imm_expr.X_add_number) > 4)
10201 imm_expr.X_op = O_constant;
10202 if (!target_big_endian)
10203 imm_expr.X_add_number = bfd_getl64 (temp);
10205 imm_expr.X_add_number = bfd_getb64 (temp);
10209 imm_expr.X_op = O_big;
10210 imm_expr.X_add_number = 4;
10211 if (!target_big_endian)
10213 generic_bignum[0] = bfd_getl16 (temp);
10214 generic_bignum[1] = bfd_getl16 (temp + 2);
10215 generic_bignum[2] = bfd_getl16 (temp + 4);
10216 generic_bignum[3] = bfd_getl16 (temp + 6);
10220 generic_bignum[0] = bfd_getb16 (temp + 6);
10221 generic_bignum[1] = bfd_getb16 (temp + 4);
10222 generic_bignum[2] = bfd_getb16 (temp + 2);
10223 generic_bignum[3] = bfd_getb16 (temp);
10229 const char *newname;
10232 /* Switch to the right section. */
10234 subseg = now_subseg;
10237 default: /* unused default case avoids warnings. */
10239 newname = RDATA_SECTION_NAME;
10240 if (g_switch_value >= 8)
10244 newname = RDATA_SECTION_NAME;
10247 gas_assert (g_switch_value >= 4);
10251 new_seg = subseg_new (newname, (subsegT) 0);
10253 bfd_set_section_flags (stdoutput, new_seg,
10258 frag_align (*args == 'l' ? 2 : 3, 0, 0);
10259 if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0)
10260 record_alignment (new_seg, 4);
10262 record_alignment (new_seg, *args == 'l' ? 2 : 3);
10263 if (seg == now_seg)
10264 as_bad (_("Can't use floating point insn in this section"));
10266 /* Set the argument to the current address in the
10268 offset_expr.X_op = O_symbol;
10269 offset_expr.X_add_symbol = symbol_temp_new_now ();
10270 offset_expr.X_add_number = 0;
10272 /* Put the floating point number into the section. */
10273 p = frag_more ((int) length);
10274 memcpy (p, temp, length);
10276 /* Switch back to the original section. */
10277 subseg_set (seg, subseg);
10282 case 'i': /* 16-bit unsigned immediate. */
10283 case 'j': /* 16-bit signed immediate. */
10284 *imm_reloc = BFD_RELOC_LO16;
10285 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
10288 offsetT minval, maxval;
10290 more = (insn + 1 < &mips_opcodes[NUMOPCODES]
10291 && strcmp (insn->name, insn[1].name) == 0);
10293 /* If the expression was written as an unsigned number,
10294 only treat it as signed if there are no more
10298 && sizeof (imm_expr.X_add_number) <= 4
10299 && imm_expr.X_op == O_constant
10300 && imm_expr.X_add_number < 0
10301 && imm_expr.X_unsigned
10302 && HAVE_64BIT_GPRS)
10305 /* For compatibility with older assemblers, we accept
10306 0x8000-0xffff as signed 16-bit numbers when only
10307 signed numbers are allowed. */
10309 minval = 0, maxval = 0xffff;
10311 minval = -0x8000, maxval = 0x7fff;
10313 minval = -0x8000, maxval = 0xffff;
10315 if (imm_expr.X_op != O_constant
10316 || imm_expr.X_add_number < minval
10317 || imm_expr.X_add_number > maxval)
10321 if (imm_expr.X_op == O_constant
10322 || imm_expr.X_op == O_big)
10323 as_bad (_("Expression out of range"));
10329 case 'o': /* 16-bit offset. */
10330 offset_reloc[0] = BFD_RELOC_LO16;
10331 offset_reloc[1] = BFD_RELOC_UNUSED;
10332 offset_reloc[2] = BFD_RELOC_UNUSED;
10334 /* Check whether there is only a single bracketed expression
10335 left. If so, it must be the base register and the
10336 constant must be zero. */
10337 if (*s == '(' && strchr (s + 1, '(') == 0)
10339 offset_expr.X_op = O_constant;
10340 offset_expr.X_add_number = 0;
10344 /* If this value won't fit into a 16 bit offset, then go
10345 find a macro that will generate the 32 bit offset
10347 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
10348 && (offset_expr.X_op != O_constant
10349 || offset_expr.X_add_number >= 0x8000
10350 || offset_expr.X_add_number < -0x8000))
10356 case 'p': /* PC-relative offset. */
10357 *offset_reloc = BFD_RELOC_16_PCREL_S2;
10358 my_getExpression (&offset_expr, s);
10362 case 'u': /* Upper 16 bits. */
10363 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
10364 && imm_expr.X_op == O_constant
10365 && (imm_expr.X_add_number < 0
10366 || imm_expr.X_add_number >= 0x10000))
10367 as_bad (_("lui expression (%lu) not in range 0..65535"),
10368 (unsigned long) imm_expr.X_add_number);
10372 case 'a': /* 26-bit address. */
10373 my_getExpression (&offset_expr, s);
10375 *offset_reloc = BFD_RELOC_MIPS_JMP;
10378 case 'N': /* 3-bit branch condition code. */
10379 case 'M': /* 3-bit compare condition code. */
10381 if (ip->insn_mo->pinfo & (FP_D | FP_S))
10382 rtype |= RTYPE_FCC;
10383 if (!reg_lookup (&s, rtype, ®no))
10385 if ((strcmp (str + strlen (str) - 3, ".ps") == 0
10386 || strcmp (str + strlen (str) - 5, "any2f") == 0
10387 || strcmp (str + strlen (str) - 5, "any2t") == 0)
10388 && (regno & 1) != 0)
10389 as_warn (_("Condition code register should be even for %s, "
10392 if ((strcmp (str + strlen (str) - 5, "any4f") == 0
10393 || strcmp (str + strlen (str) - 5, "any4t") == 0)
10394 && (regno & 3) != 0)
10395 as_warn (_("Condition code register should be 0 or 4 for %s, "
10399 INSERT_OPERAND (BCC, *ip, regno);
10401 INSERT_OPERAND (CCC, *ip, regno);
10405 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
10416 while (ISDIGIT (*s));
10419 c = 8; /* Invalid sel value. */
10422 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
10423 ip->insn_opcode |= c;
10427 /* Must be at least one digit. */
10428 my_getExpression (&imm_expr, s);
10429 check_absolute_expr (ip, &imm_expr);
10431 if ((unsigned long) imm_expr.X_add_number
10432 > (unsigned long) OP_MASK_VECBYTE)
10434 as_bad (_("bad byte vector index (%ld)"),
10435 (long) imm_expr.X_add_number);
10436 imm_expr.X_add_number = 0;
10439 INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number);
10440 imm_expr.X_op = O_absent;
10445 my_getExpression (&imm_expr, s);
10446 check_absolute_expr (ip, &imm_expr);
10448 if ((unsigned long) imm_expr.X_add_number
10449 > (unsigned long) OP_MASK_VECALIGN)
10451 as_bad (_("bad byte vector index (%ld)"),
10452 (long) imm_expr.X_add_number);
10453 imm_expr.X_add_number = 0;
10456 INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number);
10457 imm_expr.X_op = O_absent;
10462 as_bad (_("Bad char = '%c'\n"), *args);
10467 /* Args don't match. */
10468 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
10469 !strcmp (insn->name, insn[1].name))
10473 insn_error = _("Illegal operands");
10477 *(--argsStart) = save_c;
10478 insn_error = _("Illegal operands");
10483 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
10485 /* This routine assembles an instruction into its binary format when
10486 assembling for the mips16. As a side effect, it sets one of the
10487 global variables imm_reloc or offset_reloc to the type of
10488 relocation to do if one of the operands is an address expression.
10489 It also sets mips16_small and mips16_ext if the user explicitly
10490 requested a small or extended instruction. */
10493 mips16_ip (char *str, struct mips_cl_insn *ip)
10497 struct mips_opcode *insn;
10499 unsigned int regno;
10500 unsigned int lastregno = 0;
10506 mips16_small = FALSE;
10507 mips16_ext = FALSE;
10509 for (s = str; ISLOWER (*s); ++s)
10521 if (s[1] == 't' && s[2] == ' ')
10524 mips16_small = TRUE;
10528 else if (s[1] == 'e' && s[2] == ' ')
10535 /* Fall through. */
10537 insn_error = _("unknown opcode");
10541 if (mips_opts.noautoextend && ! mips16_ext)
10542 mips16_small = TRUE;
10544 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
10546 insn_error = _("unrecognized opcode");
10555 gas_assert (strcmp (insn->name, str) == 0);
10557 ok = is_opcode_valid_16 (insn);
10560 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
10561 && strcmp (insn->name, insn[1].name) == 0)
10570 static char buf[100];
10572 _("opcode not supported on this processor: %s (%s)"),
10573 mips_cpu_info_from_arch (mips_opts.arch)->name,
10574 mips_cpu_info_from_isa (mips_opts.isa)->name);
10581 create_insn (ip, insn);
10582 imm_expr.X_op = O_absent;
10583 imm_reloc[0] = BFD_RELOC_UNUSED;
10584 imm_reloc[1] = BFD_RELOC_UNUSED;
10585 imm_reloc[2] = BFD_RELOC_UNUSED;
10586 imm2_expr.X_op = O_absent;
10587 offset_expr.X_op = O_absent;
10588 offset_reloc[0] = BFD_RELOC_UNUSED;
10589 offset_reloc[1] = BFD_RELOC_UNUSED;
10590 offset_reloc[2] = BFD_RELOC_UNUSED;
10591 for (args = insn->args; 1; ++args)
10598 /* In this switch statement we call break if we did not find
10599 a match, continue if we did find a match, or return if we
10608 /* Stuff the immediate value in now, if we can. */
10609 if (imm_expr.X_op == O_constant
10610 && *imm_reloc > BFD_RELOC_UNUSED
10611 && *imm_reloc != BFD_RELOC_MIPS16_GOT16
10612 && *imm_reloc != BFD_RELOC_MIPS16_CALL16
10613 && insn->pinfo != INSN_MACRO)
10617 switch (*offset_reloc)
10619 case BFD_RELOC_MIPS16_HI16_S:
10620 tmp = (imm_expr.X_add_number + 0x8000) >> 16;
10623 case BFD_RELOC_MIPS16_HI16:
10624 tmp = imm_expr.X_add_number >> 16;
10627 case BFD_RELOC_MIPS16_LO16:
10628 tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff)
10632 case BFD_RELOC_UNUSED:
10633 tmp = imm_expr.X_add_number;
10639 *offset_reloc = BFD_RELOC_UNUSED;
10641 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
10642 tmp, TRUE, mips16_small,
10643 mips16_ext, &ip->insn_opcode,
10644 &ip->use_extend, &ip->extend);
10645 imm_expr.X_op = O_absent;
10646 *imm_reloc = BFD_RELOC_UNUSED;
10660 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10663 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10679 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10681 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10685 /* Fall through. */
10696 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
10698 if (c == 'v' || c == 'w')
10701 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10703 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10714 if (c == 'v' || c == 'w')
10716 regno = mips16_to_32_reg_map[lastregno];
10730 regno = mips32_to_16_reg_map[regno];
10735 regno = ILLEGAL_REG;
10740 regno = ILLEGAL_REG;
10745 regno = ILLEGAL_REG;
10750 if (regno == AT && mips_opts.at)
10752 if (mips_opts.at == ATREG)
10753 as_warn (_("used $at without \".set noat\""));
10755 as_warn (_("used $%u with \".set at=$%u\""),
10756 regno, mips_opts.at);
10764 if (regno == ILLEGAL_REG)
10771 MIPS16_INSERT_OPERAND (RX, *ip, regno);
10775 MIPS16_INSERT_OPERAND (RY, *ip, regno);
10778 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
10781 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
10787 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
10790 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
10791 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
10801 if (strncmp (s, "$pc", 3) == 0)
10818 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
10821 if (imm_expr.X_op != O_constant)
10824 ip->use_extend = TRUE;
10829 /* We need to relax this instruction. */
10830 *offset_reloc = *imm_reloc;
10831 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10836 *imm_reloc = BFD_RELOC_UNUSED;
10837 /* Fall through. */
10844 my_getExpression (&imm_expr, s);
10845 if (imm_expr.X_op == O_register)
10847 /* What we thought was an expression turned out to
10850 if (s[0] == '(' && args[1] == '(')
10852 /* It looks like the expression was omitted
10853 before a register indirection, which means
10854 that the expression is implicitly zero. We
10855 still set up imm_expr, so that we handle
10856 explicit extensions correctly. */
10857 imm_expr.X_op = O_constant;
10858 imm_expr.X_add_number = 0;
10859 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10866 /* We need to relax this instruction. */
10867 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10876 /* We use offset_reloc rather than imm_reloc for the PC
10877 relative operands. This lets macros with both
10878 immediate and address operands work correctly. */
10879 my_getExpression (&offset_expr, s);
10881 if (offset_expr.X_op == O_register)
10884 /* We need to relax this instruction. */
10885 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
10889 case '6': /* break code */
10890 my_getExpression (&imm_expr, s);
10891 check_absolute_expr (ip, &imm_expr);
10892 if ((unsigned long) imm_expr.X_add_number > 63)
10893 as_warn (_("Invalid value for `%s' (%lu)"),
10895 (unsigned long) imm_expr.X_add_number);
10896 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
10897 imm_expr.X_op = O_absent;
10901 case 'a': /* 26 bit address */
10902 my_getExpression (&offset_expr, s);
10904 *offset_reloc = BFD_RELOC_MIPS16_JMP;
10905 ip->insn_opcode <<= 16;
10908 case 'l': /* register list for entry macro */
10909 case 'L': /* register list for exit macro */
10919 unsigned int freg, reg1, reg2;
10921 while (*s == ' ' || *s == ',')
10923 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
10925 else if (reg_lookup (&s, RTYPE_FPU, ®1))
10929 as_bad (_("can't parse register list"));
10939 if (!reg_lookup (&s, freg ? RTYPE_FPU
10940 : (RTYPE_GP | RTYPE_NUM), ®2))
10942 as_bad (_("invalid register list"));
10946 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
10948 mask &= ~ (7 << 3);
10951 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
10953 mask &= ~ (7 << 3);
10956 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
10957 mask |= (reg2 - 3) << 3;
10958 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
10959 mask |= (reg2 - 15) << 1;
10960 else if (reg1 == RA && reg2 == RA)
10964 as_bad (_("invalid register list"));
10968 /* The mask is filled in in the opcode table for the
10969 benefit of the disassembler. We remove it before
10970 applying the actual mask. */
10971 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
10972 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
10976 case 'm': /* Register list for save insn. */
10977 case 'M': /* Register list for restore insn. */
10980 int framesz = 0, seen_framesz = 0;
10981 int nargs = 0, statics = 0, sregs = 0;
10985 unsigned int reg1, reg2;
10987 SKIP_SPACE_TABS (s);
10990 SKIP_SPACE_TABS (s);
10992 my_getExpression (&imm_expr, s);
10993 if (imm_expr.X_op == O_constant)
10995 /* Handle the frame size. */
10998 as_bad (_("more than one frame size in list"));
11002 framesz = imm_expr.X_add_number;
11003 imm_expr.X_op = O_absent;
11008 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
11010 as_bad (_("can't parse register list"));
11022 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2)
11025 as_bad (_("can't parse register list"));
11030 while (reg1 <= reg2)
11032 if (reg1 >= 4 && reg1 <= 7)
11036 nargs |= 1 << (reg1 - 4);
11038 /* statics $a0-$a3 */
11039 statics |= 1 << (reg1 - 4);
11041 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
11044 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
11046 else if (reg1 == 31)
11048 /* Add $ra to insn. */
11053 as_bad (_("unexpected register in list"));
11061 /* Encode args/statics combination. */
11062 if (nargs & statics)
11063 as_bad (_("arg/static registers overlap"));
11064 else if (nargs == 0xf)
11065 /* All $a0-$a3 are args. */
11066 opcode |= MIPS16_ALL_ARGS << 16;
11067 else if (statics == 0xf)
11068 /* All $a0-$a3 are statics. */
11069 opcode |= MIPS16_ALL_STATICS << 16;
11072 int narg = 0, nstat = 0;
11074 /* Count arg registers. */
11075 while (nargs & 0x1)
11081 as_bad (_("invalid arg register list"));
11083 /* Count static registers. */
11084 while (statics & 0x8)
11086 statics = (statics << 1) & 0xf;
11090 as_bad (_("invalid static register list"));
11092 /* Encode args/statics. */
11093 opcode |= ((narg << 2) | nstat) << 16;
11096 /* Encode $s0/$s1. */
11097 if (sregs & (1 << 0)) /* $s0 */
11099 if (sregs & (1 << 1)) /* $s1 */
11105 /* Count regs $s2-$s8. */
11113 as_bad (_("invalid static register list"));
11114 /* Encode $s2-$s8. */
11115 opcode |= nsreg << 24;
11118 /* Encode frame size. */
11120 as_bad (_("missing frame size"));
11121 else if ((framesz & 7) != 0 || framesz < 0
11122 || framesz > 0xff * 8)
11123 as_bad (_("invalid frame size"));
11124 else if (framesz != 128 || (opcode >> 16) != 0)
11127 opcode |= (((framesz & 0xf0) << 16)
11128 | (framesz & 0x0f));
11131 /* Finally build the instruction. */
11132 if ((opcode >> 16) != 0 || framesz == 0)
11134 ip->use_extend = TRUE;
11135 ip->extend = opcode >> 16;
11137 ip->insn_opcode |= opcode & 0x7f;
11141 case 'e': /* extend code */
11142 my_getExpression (&imm_expr, s);
11143 check_absolute_expr (ip, &imm_expr);
11144 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
11146 as_warn (_("Invalid value for `%s' (%lu)"),
11148 (unsigned long) imm_expr.X_add_number);
11149 imm_expr.X_add_number &= 0x7ff;
11151 ip->insn_opcode |= imm_expr.X_add_number;
11152 imm_expr.X_op = O_absent;
11162 /* Args don't match. */
11163 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
11164 strcmp (insn->name, insn[1].name) == 0)
11171 insn_error = _("illegal operands");
11177 /* This structure holds information we know about a mips16 immediate
11180 struct mips16_immed_operand
11182 /* The type code used in the argument string in the opcode table. */
11184 /* The number of bits in the short form of the opcode. */
11186 /* The number of bits in the extended form of the opcode. */
11188 /* The amount by which the short form is shifted when it is used;
11189 for example, the sw instruction has a shift count of 2. */
11191 /* The amount by which the short form is shifted when it is stored
11192 into the instruction code. */
11194 /* Non-zero if the short form is unsigned. */
11196 /* Non-zero if the extended form is unsigned. */
11198 /* Non-zero if the value is PC relative. */
11202 /* The mips16 immediate operand types. */
11204 static const struct mips16_immed_operand mips16_immed_operands[] =
11206 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
11207 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
11208 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
11209 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
11210 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
11211 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
11212 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
11213 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
11214 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
11215 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
11216 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
11217 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
11218 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
11219 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
11220 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
11221 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
11222 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
11223 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
11224 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
11225 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
11226 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
11229 #define MIPS16_NUM_IMMED \
11230 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
11232 /* Handle a mips16 instruction with an immediate value. This or's the
11233 small immediate value into *INSN. It sets *USE_EXTEND to indicate
11234 whether an extended value is needed; if one is needed, it sets
11235 *EXTEND to the value. The argument type is TYPE. The value is VAL.
11236 If SMALL is true, an unextended opcode was explicitly requested.
11237 If EXT is true, an extended opcode was explicitly requested. If
11238 WARN is true, warn if EXT does not match reality. */
11241 mips16_immed (char *file, unsigned int line, int type, offsetT val,
11242 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
11243 unsigned long *insn, bfd_boolean *use_extend,
11244 unsigned short *extend)
11246 const struct mips16_immed_operand *op;
11247 int mintiny, maxtiny;
11248 bfd_boolean needext;
11250 op = mips16_immed_operands;
11251 while (op->type != type)
11254 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
11259 if (type == '<' || type == '>' || type == '[' || type == ']')
11262 maxtiny = 1 << op->nbits;
11267 maxtiny = (1 << op->nbits) - 1;
11272 mintiny = - (1 << (op->nbits - 1));
11273 maxtiny = (1 << (op->nbits - 1)) - 1;
11276 /* Branch offsets have an implicit 0 in the lowest bit. */
11277 if (type == 'p' || type == 'q')
11280 if ((val & ((1 << op->shift) - 1)) != 0
11281 || val < (mintiny << op->shift)
11282 || val > (maxtiny << op->shift))
11287 if (warn && ext && ! needext)
11288 as_warn_where (file, line,
11289 _("extended operand requested but not required"));
11290 if (small && needext)
11291 as_bad_where (file, line, _("invalid unextended operand value"));
11293 if (small || (! ext && ! needext))
11297 *use_extend = FALSE;
11298 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
11299 insnval <<= op->op_shift;
11304 long minext, maxext;
11310 maxext = (1 << op->extbits) - 1;
11314 minext = - (1 << (op->extbits - 1));
11315 maxext = (1 << (op->extbits - 1)) - 1;
11317 if (val < minext || val > maxext)
11318 as_bad_where (file, line,
11319 _("operand value out of range for instruction"));
11321 *use_extend = TRUE;
11322 if (op->extbits == 16)
11324 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
11327 else if (op->extbits == 15)
11329 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
11334 extval = ((val & 0x1f) << 6) | (val & 0x20);
11338 *extend = (unsigned short) extval;
11343 struct percent_op_match
11346 bfd_reloc_code_real_type reloc;
11349 static const struct percent_op_match mips_percent_op[] =
11351 {"%lo", BFD_RELOC_LO16},
11353 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
11354 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
11355 {"%call16", BFD_RELOC_MIPS_CALL16},
11356 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
11357 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
11358 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
11359 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
11360 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
11361 {"%got", BFD_RELOC_MIPS_GOT16},
11362 {"%gp_rel", BFD_RELOC_GPREL16},
11363 {"%half", BFD_RELOC_16},
11364 {"%highest", BFD_RELOC_MIPS_HIGHEST},
11365 {"%higher", BFD_RELOC_MIPS_HIGHER},
11366 {"%neg", BFD_RELOC_MIPS_SUB},
11367 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
11368 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
11369 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
11370 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
11371 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
11372 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
11373 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
11375 {"%hi", BFD_RELOC_HI16_S}
11378 static const struct percent_op_match mips16_percent_op[] =
11380 {"%lo", BFD_RELOC_MIPS16_LO16},
11381 {"%gprel", BFD_RELOC_MIPS16_GPREL},
11382 {"%got", BFD_RELOC_MIPS16_GOT16},
11383 {"%call16", BFD_RELOC_MIPS16_CALL16},
11384 {"%hi", BFD_RELOC_MIPS16_HI16_S}
11388 /* Return true if *STR points to a relocation operator. When returning true,
11389 move *STR over the operator and store its relocation code in *RELOC.
11390 Leave both *STR and *RELOC alone when returning false. */
11393 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
11395 const struct percent_op_match *percent_op;
11398 if (mips_opts.mips16)
11400 percent_op = mips16_percent_op;
11401 limit = ARRAY_SIZE (mips16_percent_op);
11405 percent_op = mips_percent_op;
11406 limit = ARRAY_SIZE (mips_percent_op);
11409 for (i = 0; i < limit; i++)
11410 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
11412 int len = strlen (percent_op[i].str);
11414 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
11417 *str += strlen (percent_op[i].str);
11418 *reloc = percent_op[i].reloc;
11420 /* Check whether the output BFD supports this relocation.
11421 If not, issue an error and fall back on something safe. */
11422 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
11424 as_bad (_("relocation %s isn't supported by the current ABI"),
11425 percent_op[i].str);
11426 *reloc = BFD_RELOC_UNUSED;
11434 /* Parse string STR as a 16-bit relocatable operand. Store the
11435 expression in *EP and the relocations in the array starting
11436 at RELOC. Return the number of relocation operators used.
11438 On exit, EXPR_END points to the first character after the expression. */
11441 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
11444 bfd_reloc_code_real_type reversed_reloc[3];
11445 size_t reloc_index, i;
11446 int crux_depth, str_depth;
11449 /* Search for the start of the main expression, recoding relocations
11450 in REVERSED_RELOC. End the loop with CRUX pointing to the start
11451 of the main expression and with CRUX_DEPTH containing the number
11452 of open brackets at that point. */
11459 crux_depth = str_depth;
11461 /* Skip over whitespace and brackets, keeping count of the number
11463 while (*str == ' ' || *str == '\t' || *str == '(')
11468 && reloc_index < (HAVE_NEWABI ? 3 : 1)
11469 && parse_relocation (&str, &reversed_reloc[reloc_index]));
11471 my_getExpression (ep, crux);
11474 /* Match every open bracket. */
11475 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
11479 if (crux_depth > 0)
11480 as_bad (_("unclosed '('"));
11484 if (reloc_index != 0)
11486 prev_reloc_op_frag = frag_now;
11487 for (i = 0; i < reloc_index; i++)
11488 reloc[i] = reversed_reloc[reloc_index - 1 - i];
11491 return reloc_index;
11495 my_getExpression (expressionS *ep, char *str)
11499 save_in = input_line_pointer;
11500 input_line_pointer = str;
11502 expr_end = input_line_pointer;
11503 input_line_pointer = save_in;
11507 md_atof (int type, char *litP, int *sizeP)
11509 return ieee_md_atof (type, litP, sizeP, target_big_endian);
11513 md_number_to_chars (char *buf, valueT val, int n)
11515 if (target_big_endian)
11516 number_to_chars_bigendian (buf, val, n);
11518 number_to_chars_littleendian (buf, val, n);
11522 static int support_64bit_objects(void)
11524 const char **list, **l;
11527 list = bfd_target_list ();
11528 for (l = list; *l != NULL; l++)
11529 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
11530 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
11532 yes = (*l != NULL);
11536 #endif /* OBJ_ELF */
11538 const char *md_shortopts = "O::g::G:";
11542 OPTION_MARCH = OPTION_MD_BASE,
11564 OPTION_NO_SMARTMIPS,
11567 OPTION_COMPAT_ARCH_BASE,
11576 OPTION_M7000_HILO_FIX,
11577 OPTION_MNO_7000_HILO_FIX,
11580 OPTION_FIX_LOONGSON2F_JUMP,
11581 OPTION_NO_FIX_LOONGSON2F_JUMP,
11582 OPTION_FIX_LOONGSON2F_NOP,
11583 OPTION_NO_FIX_LOONGSON2F_NOP,
11585 OPTION_NO_FIX_VR4120,
11587 OPTION_NO_FIX_VR4130,
11588 OPTION_FIX_CN63XXP1,
11589 OPTION_NO_FIX_CN63XXP1,
11596 OPTION_CONSTRUCT_FLOATS,
11597 OPTION_NO_CONSTRUCT_FLOATS,
11600 OPTION_RELAX_BRANCH,
11601 OPTION_NO_RELAX_BRANCH,
11608 OPTION_SINGLE_FLOAT,
11609 OPTION_DOUBLE_FLOAT,
11612 OPTION_CALL_SHARED,
11613 OPTION_CALL_NONPIC,
11623 OPTION_MVXWORKS_PIC,
11624 #endif /* OBJ_ELF */
11628 struct option md_longopts[] =
11630 /* Options which specify architecture. */
11631 {"march", required_argument, NULL, OPTION_MARCH},
11632 {"mtune", required_argument, NULL, OPTION_MTUNE},
11633 {"mips0", no_argument, NULL, OPTION_MIPS1},
11634 {"mips1", no_argument, NULL, OPTION_MIPS1},
11635 {"mips2", no_argument, NULL, OPTION_MIPS2},
11636 {"mips3", no_argument, NULL, OPTION_MIPS3},
11637 {"mips4", no_argument, NULL, OPTION_MIPS4},
11638 {"mips5", no_argument, NULL, OPTION_MIPS5},
11639 {"mips32", no_argument, NULL, OPTION_MIPS32},
11640 {"mips64", no_argument, NULL, OPTION_MIPS64},
11641 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
11642 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
11644 /* Options which specify Application Specific Extensions (ASEs). */
11645 {"mips16", no_argument, NULL, OPTION_MIPS16},
11646 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
11647 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
11648 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
11649 {"mdmx", no_argument, NULL, OPTION_MDMX},
11650 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
11651 {"mdsp", no_argument, NULL, OPTION_DSP},
11652 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
11653 {"mmt", no_argument, NULL, OPTION_MT},
11654 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
11655 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
11656 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
11657 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
11658 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
11660 /* Old-style architecture options. Don't add more of these. */
11661 {"m4650", no_argument, NULL, OPTION_M4650},
11662 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
11663 {"m4010", no_argument, NULL, OPTION_M4010},
11664 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
11665 {"m4100", no_argument, NULL, OPTION_M4100},
11666 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
11667 {"m3900", no_argument, NULL, OPTION_M3900},
11668 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
11670 /* Options which enable bug fixes. */
11671 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
11672 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
11673 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
11674 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
11675 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
11676 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
11677 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
11678 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
11679 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
11680 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
11681 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
11682 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
11683 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
11684 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
11685 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
11687 /* Miscellaneous options. */
11688 {"trap", no_argument, NULL, OPTION_TRAP},
11689 {"no-break", no_argument, NULL, OPTION_TRAP},
11690 {"break", no_argument, NULL, OPTION_BREAK},
11691 {"no-trap", no_argument, NULL, OPTION_BREAK},
11692 {"EB", no_argument, NULL, OPTION_EB},
11693 {"EL", no_argument, NULL, OPTION_EL},
11694 {"mfp32", no_argument, NULL, OPTION_FP32},
11695 {"mgp32", no_argument, NULL, OPTION_GP32},
11696 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
11697 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
11698 {"mfp64", no_argument, NULL, OPTION_FP64},
11699 {"mgp64", no_argument, NULL, OPTION_GP64},
11700 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
11701 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
11702 {"mshared", no_argument, NULL, OPTION_MSHARED},
11703 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
11704 {"msym32", no_argument, NULL, OPTION_MSYM32},
11705 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
11706 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
11707 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
11708 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
11709 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
11711 /* Strictly speaking this next option is ELF specific,
11712 but we allow it for other ports as well in order to
11713 make testing easier. */
11714 {"32", no_argument, NULL, OPTION_32},
11716 /* ELF-specific options. */
11718 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
11719 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
11720 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
11721 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
11722 {"xgot", no_argument, NULL, OPTION_XGOT},
11723 {"mabi", required_argument, NULL, OPTION_MABI},
11724 {"n32", no_argument, NULL, OPTION_N32},
11725 {"64", no_argument, NULL, OPTION_64},
11726 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
11727 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
11728 {"mpdr", no_argument, NULL, OPTION_PDR},
11729 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
11730 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
11731 #endif /* OBJ_ELF */
11733 {NULL, no_argument, NULL, 0}
11735 size_t md_longopts_size = sizeof (md_longopts);
11737 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
11738 NEW_VALUE. Warn if another value was already specified. Note:
11739 we have to defer parsing the -march and -mtune arguments in order
11740 to handle 'from-abi' correctly, since the ABI might be specified
11741 in a later argument. */
11744 mips_set_option_string (const char **string_ptr, const char *new_value)
11746 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
11747 as_warn (_("A different %s was already specified, is now %s"),
11748 string_ptr == &mips_arch_string ? "-march" : "-mtune",
11751 *string_ptr = new_value;
11755 md_parse_option (int c, char *arg)
11759 case OPTION_CONSTRUCT_FLOATS:
11760 mips_disable_float_construction = 0;
11763 case OPTION_NO_CONSTRUCT_FLOATS:
11764 mips_disable_float_construction = 1;
11776 target_big_endian = 1;
11780 target_big_endian = 0;
11786 else if (arg[0] == '0')
11788 else if (arg[0] == '1')
11798 mips_debug = atoi (arg);
11802 file_mips_isa = ISA_MIPS1;
11806 file_mips_isa = ISA_MIPS2;
11810 file_mips_isa = ISA_MIPS3;
11814 file_mips_isa = ISA_MIPS4;
11818 file_mips_isa = ISA_MIPS5;
11821 case OPTION_MIPS32:
11822 file_mips_isa = ISA_MIPS32;
11825 case OPTION_MIPS32R2:
11826 file_mips_isa = ISA_MIPS32R2;
11829 case OPTION_MIPS64R2:
11830 file_mips_isa = ISA_MIPS64R2;
11833 case OPTION_MIPS64:
11834 file_mips_isa = ISA_MIPS64;
11838 mips_set_option_string (&mips_tune_string, arg);
11842 mips_set_option_string (&mips_arch_string, arg);
11846 mips_set_option_string (&mips_arch_string, "4650");
11847 mips_set_option_string (&mips_tune_string, "4650");
11850 case OPTION_NO_M4650:
11854 mips_set_option_string (&mips_arch_string, "4010");
11855 mips_set_option_string (&mips_tune_string, "4010");
11858 case OPTION_NO_M4010:
11862 mips_set_option_string (&mips_arch_string, "4100");
11863 mips_set_option_string (&mips_tune_string, "4100");
11866 case OPTION_NO_M4100:
11870 mips_set_option_string (&mips_arch_string, "3900");
11871 mips_set_option_string (&mips_tune_string, "3900");
11874 case OPTION_NO_M3900:
11878 mips_opts.ase_mdmx = 1;
11881 case OPTION_NO_MDMX:
11882 mips_opts.ase_mdmx = 0;
11886 mips_opts.ase_dsp = 1;
11887 mips_opts.ase_dspr2 = 0;
11890 case OPTION_NO_DSP:
11891 mips_opts.ase_dsp = 0;
11892 mips_opts.ase_dspr2 = 0;
11896 mips_opts.ase_dspr2 = 1;
11897 mips_opts.ase_dsp = 1;
11900 case OPTION_NO_DSPR2:
11901 mips_opts.ase_dspr2 = 0;
11902 mips_opts.ase_dsp = 0;
11906 mips_opts.ase_mt = 1;
11910 mips_opts.ase_mt = 0;
11913 case OPTION_MIPS16:
11914 mips_opts.mips16 = 1;
11915 mips_no_prev_insn ();
11918 case OPTION_NO_MIPS16:
11919 mips_opts.mips16 = 0;
11920 mips_no_prev_insn ();
11923 case OPTION_MIPS3D:
11924 mips_opts.ase_mips3d = 1;
11927 case OPTION_NO_MIPS3D:
11928 mips_opts.ase_mips3d = 0;
11931 case OPTION_SMARTMIPS:
11932 mips_opts.ase_smartmips = 1;
11935 case OPTION_NO_SMARTMIPS:
11936 mips_opts.ase_smartmips = 0;
11939 case OPTION_FIX_24K:
11943 case OPTION_NO_FIX_24K:
11947 case OPTION_FIX_LOONGSON2F_JUMP:
11948 mips_fix_loongson2f_jump = TRUE;
11951 case OPTION_NO_FIX_LOONGSON2F_JUMP:
11952 mips_fix_loongson2f_jump = FALSE;
11955 case OPTION_FIX_LOONGSON2F_NOP:
11956 mips_fix_loongson2f_nop = TRUE;
11959 case OPTION_NO_FIX_LOONGSON2F_NOP:
11960 mips_fix_loongson2f_nop = FALSE;
11963 case OPTION_FIX_VR4120:
11964 mips_fix_vr4120 = 1;
11967 case OPTION_NO_FIX_VR4120:
11968 mips_fix_vr4120 = 0;
11971 case OPTION_FIX_VR4130:
11972 mips_fix_vr4130 = 1;
11975 case OPTION_NO_FIX_VR4130:
11976 mips_fix_vr4130 = 0;
11979 case OPTION_FIX_CN63XXP1:
11980 mips_fix_cn63xxp1 = TRUE;
11983 case OPTION_NO_FIX_CN63XXP1:
11984 mips_fix_cn63xxp1 = FALSE;
11987 case OPTION_RELAX_BRANCH:
11988 mips_relax_branch = 1;
11991 case OPTION_NO_RELAX_BRANCH:
11992 mips_relax_branch = 0;
11995 case OPTION_MSHARED:
11996 mips_in_shared = TRUE;
11999 case OPTION_MNO_SHARED:
12000 mips_in_shared = FALSE;
12003 case OPTION_MSYM32:
12004 mips_opts.sym32 = TRUE;
12007 case OPTION_MNO_SYM32:
12008 mips_opts.sym32 = FALSE;
12012 /* When generating ELF code, we permit -KPIC and -call_shared to
12013 select SVR4_PIC, and -non_shared to select no PIC. This is
12014 intended to be compatible with Irix 5. */
12015 case OPTION_CALL_SHARED:
12018 as_bad (_("-call_shared is supported only for ELF format"));
12021 mips_pic = SVR4_PIC;
12022 mips_abicalls = TRUE;
12025 case OPTION_CALL_NONPIC:
12028 as_bad (_("-call_nonpic is supported only for ELF format"));
12032 mips_abicalls = TRUE;
12035 case OPTION_NON_SHARED:
12038 as_bad (_("-non_shared is supported only for ELF format"));
12042 mips_abicalls = FALSE;
12045 /* The -xgot option tells the assembler to use 32 bit offsets
12046 when accessing the got in SVR4_PIC mode. It is for Irix
12051 #endif /* OBJ_ELF */
12054 g_switch_value = atoi (arg);
12058 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
12062 mips_abi = O32_ABI;
12063 /* We silently ignore -32 for non-ELF targets. This greatly
12064 simplifies the construction of the MIPS GAS test cases. */
12071 as_bad (_("-n32 is supported for ELF format only"));
12074 mips_abi = N32_ABI;
12080 as_bad (_("-64 is supported for ELF format only"));
12083 mips_abi = N64_ABI;
12084 if (!support_64bit_objects())
12085 as_fatal (_("No compiled in support for 64 bit object file format"));
12087 #endif /* OBJ_ELF */
12090 file_mips_gp32 = 1;
12094 file_mips_gp32 = 0;
12098 file_mips_fp32 = 1;
12102 file_mips_fp32 = 0;
12105 case OPTION_SINGLE_FLOAT:
12106 file_mips_single_float = 1;
12109 case OPTION_DOUBLE_FLOAT:
12110 file_mips_single_float = 0;
12113 case OPTION_SOFT_FLOAT:
12114 file_mips_soft_float = 1;
12117 case OPTION_HARD_FLOAT:
12118 file_mips_soft_float = 0;
12125 as_bad (_("-mabi is supported for ELF format only"));
12128 if (strcmp (arg, "32") == 0)
12129 mips_abi = O32_ABI;
12130 else if (strcmp (arg, "o64") == 0)
12131 mips_abi = O64_ABI;
12132 else if (strcmp (arg, "n32") == 0)
12133 mips_abi = N32_ABI;
12134 else if (strcmp (arg, "64") == 0)
12136 mips_abi = N64_ABI;
12137 if (! support_64bit_objects())
12138 as_fatal (_("No compiled in support for 64 bit object file "
12141 else if (strcmp (arg, "eabi") == 0)
12142 mips_abi = EABI_ABI;
12145 as_fatal (_("invalid abi -mabi=%s"), arg);
12149 #endif /* OBJ_ELF */
12151 case OPTION_M7000_HILO_FIX:
12152 mips_7000_hilo_fix = TRUE;
12155 case OPTION_MNO_7000_HILO_FIX:
12156 mips_7000_hilo_fix = FALSE;
12160 case OPTION_MDEBUG:
12161 mips_flag_mdebug = TRUE;
12164 case OPTION_NO_MDEBUG:
12165 mips_flag_mdebug = FALSE;
12169 mips_flag_pdr = TRUE;
12172 case OPTION_NO_PDR:
12173 mips_flag_pdr = FALSE;
12176 case OPTION_MVXWORKS_PIC:
12177 mips_pic = VXWORKS_PIC;
12179 #endif /* OBJ_ELF */
12185 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
12190 /* Set up globals to generate code for the ISA or processor
12191 described by INFO. */
12194 mips_set_architecture (const struct mips_cpu_info *info)
12198 file_mips_arch = info->cpu;
12199 mips_opts.arch = info->cpu;
12200 mips_opts.isa = info->isa;
12205 /* Likewise for tuning. */
12208 mips_set_tune (const struct mips_cpu_info *info)
12211 mips_tune = info->cpu;
12216 mips_after_parse_args (void)
12218 const struct mips_cpu_info *arch_info = 0;
12219 const struct mips_cpu_info *tune_info = 0;
12221 /* GP relative stuff not working for PE */
12222 if (strncmp (TARGET_OS, "pe", 2) == 0)
12224 if (g_switch_seen && g_switch_value != 0)
12225 as_bad (_("-G not supported in this configuration."));
12226 g_switch_value = 0;
12229 if (mips_abi == NO_ABI)
12230 mips_abi = MIPS_DEFAULT_ABI;
12232 /* The following code determines the architecture and register size.
12233 Similar code was added to GCC 3.3 (see override_options() in
12234 config/mips/mips.c). The GAS and GCC code should be kept in sync
12235 as much as possible. */
12237 if (mips_arch_string != 0)
12238 arch_info = mips_parse_cpu ("-march", mips_arch_string);
12240 if (file_mips_isa != ISA_UNKNOWN)
12242 /* Handle -mipsN. At this point, file_mips_isa contains the
12243 ISA level specified by -mipsN, while arch_info->isa contains
12244 the -march selection (if any). */
12245 if (arch_info != 0)
12247 /* -march takes precedence over -mipsN, since it is more descriptive.
12248 There's no harm in specifying both as long as the ISA levels
12250 if (file_mips_isa != arch_info->isa)
12251 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
12252 mips_cpu_info_from_isa (file_mips_isa)->name,
12253 mips_cpu_info_from_isa (arch_info->isa)->name);
12256 arch_info = mips_cpu_info_from_isa (file_mips_isa);
12259 if (arch_info == 0)
12260 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
12262 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
12263 as_bad (_("-march=%s is not compatible with the selected ABI"),
12266 mips_set_architecture (arch_info);
12268 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
12269 if (mips_tune_string != 0)
12270 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
12272 if (tune_info == 0)
12273 mips_set_tune (arch_info);
12275 mips_set_tune (tune_info);
12277 if (file_mips_gp32 >= 0)
12279 /* The user specified the size of the integer registers. Make sure
12280 it agrees with the ABI and ISA. */
12281 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
12282 as_bad (_("-mgp64 used with a 32-bit processor"));
12283 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
12284 as_bad (_("-mgp32 used with a 64-bit ABI"));
12285 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
12286 as_bad (_("-mgp64 used with a 32-bit ABI"));
12290 /* Infer the integer register size from the ABI and processor.
12291 Restrict ourselves to 32-bit registers if that's all the
12292 processor has, or if the ABI cannot handle 64-bit registers. */
12293 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
12294 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
12297 switch (file_mips_fp32)
12301 /* No user specified float register size.
12302 ??? GAS treats single-float processors as though they had 64-bit
12303 float registers (although it complains when double-precision
12304 instructions are used). As things stand, saying they have 32-bit
12305 registers would lead to spurious "register must be even" messages.
12306 So here we assume float registers are never smaller than the
12308 if (file_mips_gp32 == 0)
12309 /* 64-bit integer registers implies 64-bit float registers. */
12310 file_mips_fp32 = 0;
12311 else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
12312 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
12313 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
12314 file_mips_fp32 = 0;
12316 /* 32-bit float registers. */
12317 file_mips_fp32 = 1;
12320 /* The user specified the size of the float registers. Check if it
12321 agrees with the ABI and ISA. */
12323 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
12324 as_bad (_("-mfp64 used with a 32-bit fpu"));
12325 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
12326 && !ISA_HAS_MXHC1 (mips_opts.isa))
12327 as_warn (_("-mfp64 used with a 32-bit ABI"));
12330 if (ABI_NEEDS_64BIT_REGS (mips_abi))
12331 as_warn (_("-mfp32 used with a 64-bit ABI"));
12335 /* End of GCC-shared inference code. */
12337 /* This flag is set when we have a 64-bit capable CPU but use only
12338 32-bit wide registers. Note that EABI does not use it. */
12339 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
12340 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
12341 || mips_abi == O32_ABI))
12342 mips_32bitmode = 1;
12344 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
12345 as_bad (_("trap exception not supported at ISA 1"));
12347 /* If the selected architecture includes support for ASEs, enable
12348 generation of code for them. */
12349 if (mips_opts.mips16 == -1)
12350 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
12351 if (mips_opts.ase_mips3d == -1)
12352 mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
12353 && file_mips_fp32 == 0) ? 1 : 0;
12354 if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
12355 as_bad (_("-mfp32 used with -mips3d"));
12357 if (mips_opts.ase_mdmx == -1)
12358 mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
12359 && file_mips_fp32 == 0) ? 1 : 0;
12360 if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
12361 as_bad (_("-mfp32 used with -mdmx"));
12363 if (mips_opts.ase_smartmips == -1)
12364 mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
12365 if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
12366 as_warn (_("%s ISA does not support SmartMIPS"),
12367 mips_cpu_info_from_isa (mips_opts.isa)->name);
12369 if (mips_opts.ase_dsp == -1)
12370 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
12371 if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
12372 as_warn (_("%s ISA does not support DSP ASE"),
12373 mips_cpu_info_from_isa (mips_opts.isa)->name);
12375 if (mips_opts.ase_dspr2 == -1)
12377 mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
12378 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
12380 if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
12381 as_warn (_("%s ISA does not support DSP R2 ASE"),
12382 mips_cpu_info_from_isa (mips_opts.isa)->name);
12384 if (mips_opts.ase_mt == -1)
12385 mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
12386 if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
12387 as_warn (_("%s ISA does not support MT ASE"),
12388 mips_cpu_info_from_isa (mips_opts.isa)->name);
12390 file_mips_isa = mips_opts.isa;
12391 file_ase_mips3d = mips_opts.ase_mips3d;
12392 file_ase_mdmx = mips_opts.ase_mdmx;
12393 file_ase_smartmips = mips_opts.ase_smartmips;
12394 file_ase_dsp = mips_opts.ase_dsp;
12395 file_ase_dspr2 = mips_opts.ase_dspr2;
12396 file_ase_mt = mips_opts.ase_mt;
12397 mips_opts.gp32 = file_mips_gp32;
12398 mips_opts.fp32 = file_mips_fp32;
12399 mips_opts.soft_float = file_mips_soft_float;
12400 mips_opts.single_float = file_mips_single_float;
12402 if (mips_flag_mdebug < 0)
12404 #ifdef OBJ_MAYBE_ECOFF
12405 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
12406 mips_flag_mdebug = 1;
12408 #endif /* OBJ_MAYBE_ECOFF */
12409 mips_flag_mdebug = 0;
12414 mips_init_after_args (void)
12416 /* initialize opcodes */
12417 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
12418 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
12422 md_pcrel_from (fixS *fixP)
12424 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
12425 switch (fixP->fx_r_type)
12427 case BFD_RELOC_16_PCREL_S2:
12428 case BFD_RELOC_MIPS_JMP:
12429 /* Return the address of the delay slot. */
12432 /* We have no relocation type for PC relative MIPS16 instructions. */
12433 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
12434 as_bad_where (fixP->fx_file, fixP->fx_line,
12435 _("PC relative MIPS16 instruction references a different section"));
12440 /* This is called before the symbol table is processed. In order to
12441 work with gcc when using mips-tfile, we must keep all local labels.
12442 However, in other cases, we want to discard them. If we were
12443 called with -g, but we didn't see any debugging information, it may
12444 mean that gcc is smuggling debugging information through to
12445 mips-tfile, in which case we must generate all local labels. */
12448 mips_frob_file_before_adjust (void)
12450 #ifndef NO_ECOFF_DEBUGGING
12451 if (ECOFF_DEBUGGING
12453 && ! ecoff_debugging_seen)
12454 flag_keep_locals = 1;
12458 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
12459 the corresponding LO16 reloc. This is called before md_apply_fix and
12460 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
12461 relocation operators.
12463 For our purposes, a %lo() expression matches a %got() or %hi()
12466 (a) it refers to the same symbol; and
12467 (b) the offset applied in the %lo() expression is no lower than
12468 the offset applied in the %got() or %hi().
12470 (b) allows us to cope with code like:
12473 lh $4,%lo(foo+2)($4)
12475 ...which is legal on RELA targets, and has a well-defined behaviour
12476 if the user knows that adding 2 to "foo" will not induce a carry to
12479 When several %lo()s match a particular %got() or %hi(), we use the
12480 following rules to distinguish them:
12482 (1) %lo()s with smaller offsets are a better match than %lo()s with
12485 (2) %lo()s with no matching %got() or %hi() are better than those
12486 that already have a matching %got() or %hi().
12488 (3) later %lo()s are better than earlier %lo()s.
12490 These rules are applied in order.
12492 (1) means, among other things, that %lo()s with identical offsets are
12493 chosen if they exist.
12495 (2) means that we won't associate several high-part relocations with
12496 the same low-part relocation unless there's no alternative. Having
12497 several high parts for the same low part is a GNU extension; this rule
12498 allows careful users to avoid it.
12500 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
12501 with the last high-part relocation being at the front of the list.
12502 It therefore makes sense to choose the last matching low-part
12503 relocation, all other things being equal. It's also easier
12504 to code that way. */
12507 mips_frob_file (void)
12509 struct mips_hi_fixup *l;
12510 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
12512 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
12514 segment_info_type *seginfo;
12515 bfd_boolean matched_lo_p;
12516 fixS **hi_pos, **lo_pos, **pos;
12518 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
12520 /* If a GOT16 relocation turns out to be against a global symbol,
12521 there isn't supposed to be a matching LO. */
12522 if (got16_reloc_p (l->fixp->fx_r_type)
12523 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
12526 /* Check quickly whether the next fixup happens to be a matching %lo. */
12527 if (fixup_has_matching_lo_p (l->fixp))
12530 seginfo = seg_info (l->seg);
12532 /* Set HI_POS to the position of this relocation in the chain.
12533 Set LO_POS to the position of the chosen low-part relocation.
12534 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
12535 relocation that matches an immediately-preceding high-part
12539 matched_lo_p = FALSE;
12540 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
12542 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
12544 if (*pos == l->fixp)
12547 if ((*pos)->fx_r_type == looking_for_rtype
12548 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
12549 && (*pos)->fx_offset >= l->fixp->fx_offset
12551 || (*pos)->fx_offset < (*lo_pos)->fx_offset
12553 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
12556 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
12557 && fixup_has_matching_lo_p (*pos));
12560 /* If we found a match, remove the high-part relocation from its
12561 current position and insert it before the low-part relocation.
12562 Make the offsets match so that fixup_has_matching_lo_p()
12565 We don't warn about unmatched high-part relocations since some
12566 versions of gcc have been known to emit dead "lui ...%hi(...)"
12568 if (lo_pos != NULL)
12570 l->fixp->fx_offset = (*lo_pos)->fx_offset;
12571 if (l->fixp->fx_next != *lo_pos)
12573 *hi_pos = l->fixp->fx_next;
12574 l->fixp->fx_next = *lo_pos;
12581 /* We may have combined relocations without symbols in the N32/N64 ABI.
12582 We have to prevent gas from dropping them. */
12585 mips_force_relocation (fixS *fixp)
12587 if (generic_force_reloc (fixp))
12591 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
12592 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
12593 || hi16_reloc_p (fixp->fx_r_type)
12594 || lo16_reloc_p (fixp->fx_r_type)))
12600 /* Apply a fixup to the object file. */
12603 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
12607 reloc_howto_type *howto;
12609 /* We ignore generic BFD relocations we don't know about. */
12610 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
12614 gas_assert (fixP->fx_size == 4
12615 || fixP->fx_r_type == BFD_RELOC_16
12616 || fixP->fx_r_type == BFD_RELOC_64
12617 || fixP->fx_r_type == BFD_RELOC_CTOR
12618 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
12619 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12620 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
12621 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
12623 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
12625 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2);
12627 /* Don't treat parts of a composite relocation as done. There are two
12630 (1) The second and third parts will be against 0 (RSS_UNDEF) but
12631 should nevertheless be emitted if the first part is.
12633 (2) In normal usage, composite relocations are never assembly-time
12634 constants. The easiest way of dealing with the pathological
12635 exceptions is to generate a relocation against STN_UNDEF and
12636 leave everything up to the linker. */
12637 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
12640 switch (fixP->fx_r_type)
12642 case BFD_RELOC_MIPS_TLS_GD:
12643 case BFD_RELOC_MIPS_TLS_LDM:
12644 case BFD_RELOC_MIPS_TLS_DTPREL32:
12645 case BFD_RELOC_MIPS_TLS_DTPREL64:
12646 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
12647 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
12648 case BFD_RELOC_MIPS_TLS_GOTTPREL:
12649 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
12650 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
12651 S_SET_THREAD_LOCAL (fixP->fx_addsy);
12654 case BFD_RELOC_MIPS_JMP:
12655 case BFD_RELOC_MIPS_SHIFT5:
12656 case BFD_RELOC_MIPS_SHIFT6:
12657 case BFD_RELOC_MIPS_GOT_DISP:
12658 case BFD_RELOC_MIPS_GOT_PAGE:
12659 case BFD_RELOC_MIPS_GOT_OFST:
12660 case BFD_RELOC_MIPS_SUB:
12661 case BFD_RELOC_MIPS_INSERT_A:
12662 case BFD_RELOC_MIPS_INSERT_B:
12663 case BFD_RELOC_MIPS_DELETE:
12664 case BFD_RELOC_MIPS_HIGHEST:
12665 case BFD_RELOC_MIPS_HIGHER:
12666 case BFD_RELOC_MIPS_SCN_DISP:
12667 case BFD_RELOC_MIPS_REL16:
12668 case BFD_RELOC_MIPS_RELGOT:
12669 case BFD_RELOC_MIPS_JALR:
12670 case BFD_RELOC_HI16:
12671 case BFD_RELOC_HI16_S:
12672 case BFD_RELOC_GPREL16:
12673 case BFD_RELOC_MIPS_LITERAL:
12674 case BFD_RELOC_MIPS_CALL16:
12675 case BFD_RELOC_MIPS_GOT16:
12676 case BFD_RELOC_GPREL32:
12677 case BFD_RELOC_MIPS_GOT_HI16:
12678 case BFD_RELOC_MIPS_GOT_LO16:
12679 case BFD_RELOC_MIPS_CALL_HI16:
12680 case BFD_RELOC_MIPS_CALL_LO16:
12681 case BFD_RELOC_MIPS16_GPREL:
12682 case BFD_RELOC_MIPS16_GOT16:
12683 case BFD_RELOC_MIPS16_CALL16:
12684 case BFD_RELOC_MIPS16_HI16:
12685 case BFD_RELOC_MIPS16_HI16_S:
12686 case BFD_RELOC_MIPS16_JMP:
12687 /* Nothing needed to do. The value comes from the reloc entry. */
12691 /* This is handled like BFD_RELOC_32, but we output a sign
12692 extended value if we are only 32 bits. */
12695 if (8 <= sizeof (valueT))
12696 md_number_to_chars ((char *) buf, *valP, 8);
12701 if ((*valP & 0x80000000) != 0)
12705 md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)),
12707 md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)),
12713 case BFD_RELOC_RVA:
12716 /* If we are deleting this reloc entry, we must fill in the
12717 value now. This can happen if we have a .word which is not
12718 resolved when it appears but is later defined. */
12720 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
12723 case BFD_RELOC_LO16:
12724 case BFD_RELOC_MIPS16_LO16:
12725 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
12726 may be safe to remove, but if so it's not obvious. */
12727 /* When handling an embedded PIC switch statement, we can wind
12728 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
12731 if (*valP + 0x8000 > 0xffff)
12732 as_bad_where (fixP->fx_file, fixP->fx_line,
12733 _("relocation overflow"));
12734 if (target_big_endian)
12736 md_number_to_chars ((char *) buf, *valP, 2);
12740 case BFD_RELOC_16_PCREL_S2:
12741 if ((*valP & 0x3) != 0)
12742 as_bad_where (fixP->fx_file, fixP->fx_line,
12743 _("Branch to misaligned address (%lx)"), (long) *valP);
12745 /* We need to save the bits in the instruction since fixup_segment()
12746 might be deleting the relocation entry (i.e., a branch within
12747 the current segment). */
12748 if (! fixP->fx_done)
12751 /* Update old instruction data. */
12752 if (target_big_endian)
12753 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
12755 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
12757 if (*valP + 0x20000 <= 0x3ffff)
12759 insn |= (*valP >> 2) & 0xffff;
12760 md_number_to_chars ((char *) buf, insn, 4);
12762 else if (mips_pic == NO_PIC
12764 && fixP->fx_frag->fr_address >= text_section->vma
12765 && (fixP->fx_frag->fr_address
12766 < text_section->vma + bfd_get_section_size (text_section))
12767 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
12768 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
12769 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
12771 /* The branch offset is too large. If this is an
12772 unconditional branch, and we are not generating PIC code,
12773 we can convert it to an absolute jump instruction. */
12774 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
12775 insn = 0x0c000000; /* jal */
12777 insn = 0x08000000; /* j */
12778 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
12780 fixP->fx_addsy = section_symbol (text_section);
12781 *valP += md_pcrel_from (fixP);
12782 md_number_to_chars ((char *) buf, insn, 4);
12786 /* If we got here, we have branch-relaxation disabled,
12787 and there's nothing we can do to fix this instruction
12788 without turning it into a longer sequence. */
12789 as_bad_where (fixP->fx_file, fixP->fx_line,
12790 _("Branch out of range"));
12794 case BFD_RELOC_VTABLE_INHERIT:
12797 && !S_IS_DEFINED (fixP->fx_addsy)
12798 && !S_IS_WEAK (fixP->fx_addsy))
12799 S_SET_WEAK (fixP->fx_addsy);
12802 case BFD_RELOC_VTABLE_ENTRY:
12810 /* Remember value for tc_gen_reloc. */
12811 fixP->fx_addnumber = *valP;
12821 name = input_line_pointer;
12822 c = get_symbol_end ();
12823 p = (symbolS *) symbol_find_or_make (name);
12824 *input_line_pointer = c;
12828 /* Align the current frag to a given power of two. If a particular
12829 fill byte should be used, FILL points to an integer that contains
12830 that byte, otherwise FILL is null.
12832 The MIPS assembler also automatically adjusts any preceding
12836 mips_align (int to, int *fill, symbolS *label)
12838 mips_emit_delays ();
12839 mips_record_mips16_mode ();
12840 if (fill == NULL && subseg_text_p (now_seg))
12841 frag_align_code (to, 0);
12843 frag_align (to, fill ? *fill : 0, 0);
12844 record_alignment (now_seg, to);
12847 gas_assert (S_GET_SEGMENT (label) == now_seg);
12848 symbol_set_frag (label, frag_now);
12849 S_SET_VALUE (label, (valueT) frag_now_fix ());
12853 /* Align to a given power of two. .align 0 turns off the automatic
12854 alignment used by the data creating pseudo-ops. */
12857 s_align (int x ATTRIBUTE_UNUSED)
12859 int temp, fill_value, *fill_ptr;
12860 long max_alignment = 28;
12862 /* o Note that the assembler pulls down any immediately preceding label
12863 to the aligned address.
12864 o It's not documented but auto alignment is reinstated by
12865 a .align pseudo instruction.
12866 o Note also that after auto alignment is turned off the mips assembler
12867 issues an error on attempt to assemble an improperly aligned data item.
12870 temp = get_absolute_expression ();
12871 if (temp > max_alignment)
12872 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
12875 as_warn (_("Alignment negative: 0 assumed."));
12878 if (*input_line_pointer == ',')
12880 ++input_line_pointer;
12881 fill_value = get_absolute_expression ();
12882 fill_ptr = &fill_value;
12888 segment_info_type *si = seg_info (now_seg);
12889 struct insn_label_list *l = si->label_list;
12890 /* Auto alignment should be switched on by next section change. */
12892 mips_align (temp, fill_ptr, l != NULL ? l->label : NULL);
12899 demand_empty_rest_of_line ();
12903 s_change_sec (int sec)
12908 /* The ELF backend needs to know that we are changing sections, so
12909 that .previous works correctly. We could do something like check
12910 for an obj_section_change_hook macro, but that might be confusing
12911 as it would not be appropriate to use it in the section changing
12912 functions in read.c, since obj-elf.c intercepts those. FIXME:
12913 This should be cleaner, somehow. */
12915 obj_elf_section_change_hook ();
12918 mips_emit_delays ();
12929 subseg_set (bss_section, (subsegT) get_absolute_expression ());
12930 demand_empty_rest_of_line ();
12934 seg = subseg_new (RDATA_SECTION_NAME,
12935 (subsegT) get_absolute_expression ());
12938 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
12939 | SEC_READONLY | SEC_RELOC
12941 if (strncmp (TARGET_OS, "elf", 3) != 0)
12942 record_alignment (seg, 4);
12944 demand_empty_rest_of_line ();
12948 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
12951 bfd_set_section_flags (stdoutput, seg,
12952 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
12953 if (strncmp (TARGET_OS, "elf", 3) != 0)
12954 record_alignment (seg, 4);
12956 demand_empty_rest_of_line ();
12960 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
12963 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
12964 if (strncmp (TARGET_OS, "elf", 3) != 0)
12965 record_alignment (seg, 4);
12967 demand_empty_rest_of_line ();
12975 s_change_section (int ignore ATTRIBUTE_UNUSED)
12978 char *section_name;
12983 int section_entry_size;
12984 int section_alignment;
12989 section_name = input_line_pointer;
12990 c = get_symbol_end ();
12992 next_c = *(input_line_pointer + 1);
12994 /* Do we have .section Name<,"flags">? */
12995 if (c != ',' || (c == ',' && next_c == '"'))
12997 /* just after name is now '\0'. */
12998 *input_line_pointer = c;
12999 input_line_pointer = section_name;
13000 obj_elf_section (ignore);
13003 input_line_pointer++;
13005 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
13007 section_type = get_absolute_expression ();
13010 if (*input_line_pointer++ == ',')
13011 section_flag = get_absolute_expression ();
13014 if (*input_line_pointer++ == ',')
13015 section_entry_size = get_absolute_expression ();
13017 section_entry_size = 0;
13018 if (*input_line_pointer++ == ',')
13019 section_alignment = get_absolute_expression ();
13021 section_alignment = 0;
13022 /* FIXME: really ignore? */
13023 (void) section_alignment;
13025 section_name = xstrdup (section_name);
13027 /* When using the generic form of .section (as implemented by obj-elf.c),
13028 there's no way to set the section type to SHT_MIPS_DWARF. Users have
13029 traditionally had to fall back on the more common @progbits instead.
13031 There's nothing really harmful in this, since bfd will correct
13032 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
13033 means that, for backwards compatibility, the special_section entries
13034 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
13036 Even so, we shouldn't force users of the MIPS .section syntax to
13037 incorrectly label the sections as SHT_PROGBITS. The best compromise
13038 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
13039 generic type-checking code. */
13040 if (section_type == SHT_MIPS_DWARF)
13041 section_type = SHT_PROGBITS;
13043 obj_elf_change_section (section_name, section_type, section_flag,
13044 section_entry_size, 0, 0, 0);
13046 if (now_seg->name != section_name)
13047 free (section_name);
13048 #endif /* OBJ_ELF */
13052 mips_enable_auto_align (void)
13058 s_cons (int log_size)
13060 segment_info_type *si = seg_info (now_seg);
13061 struct insn_label_list *l = si->label_list;
13064 label = l != NULL ? l->label : NULL;
13065 mips_emit_delays ();
13066 if (log_size > 0 && auto_align)
13067 mips_align (log_size, 0, label);
13068 cons (1 << log_size);
13069 mips_clear_insn_labels ();
13073 s_float_cons (int type)
13075 segment_info_type *si = seg_info (now_seg);
13076 struct insn_label_list *l = si->label_list;
13079 label = l != NULL ? l->label : NULL;
13081 mips_emit_delays ();
13086 mips_align (3, 0, label);
13088 mips_align (2, 0, label);
13092 mips_clear_insn_labels ();
13095 /* Handle .globl. We need to override it because on Irix 5 you are
13098 where foo is an undefined symbol, to mean that foo should be
13099 considered to be the address of a function. */
13102 s_mips_globl (int x ATTRIBUTE_UNUSED)
13111 name = input_line_pointer;
13112 c = get_symbol_end ();
13113 symbolP = symbol_find_or_make (name);
13114 S_SET_EXTERNAL (symbolP);
13116 *input_line_pointer = c;
13117 SKIP_WHITESPACE ();
13119 /* On Irix 5, every global symbol that is not explicitly labelled as
13120 being a function is apparently labelled as being an object. */
13123 if (!is_end_of_line[(unsigned char) *input_line_pointer]
13124 && (*input_line_pointer != ','))
13129 secname = input_line_pointer;
13130 c = get_symbol_end ();
13131 sec = bfd_get_section_by_name (stdoutput, secname);
13133 as_bad (_("%s: no such section"), secname);
13134 *input_line_pointer = c;
13136 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
13137 flag = BSF_FUNCTION;
13140 symbol_get_bfdsym (symbolP)->flags |= flag;
13142 c = *input_line_pointer;
13145 input_line_pointer++;
13146 SKIP_WHITESPACE ();
13147 if (is_end_of_line[(unsigned char) *input_line_pointer])
13153 demand_empty_rest_of_line ();
13157 s_option (int x ATTRIBUTE_UNUSED)
13162 opt = input_line_pointer;
13163 c = get_symbol_end ();
13167 /* FIXME: What does this mean? */
13169 else if (strncmp (opt, "pic", 3) == 0)
13173 i = atoi (opt + 3);
13178 mips_pic = SVR4_PIC;
13179 mips_abicalls = TRUE;
13182 as_bad (_(".option pic%d not supported"), i);
13184 if (mips_pic == SVR4_PIC)
13186 if (g_switch_seen && g_switch_value != 0)
13187 as_warn (_("-G may not be used with SVR4 PIC code"));
13188 g_switch_value = 0;
13189 bfd_set_gp_size (stdoutput, 0);
13193 as_warn (_("Unrecognized option \"%s\""), opt);
13195 *input_line_pointer = c;
13196 demand_empty_rest_of_line ();
13199 /* This structure is used to hold a stack of .set values. */
13201 struct mips_option_stack
13203 struct mips_option_stack *next;
13204 struct mips_set_options options;
13207 static struct mips_option_stack *mips_opts_stack;
13209 /* Handle the .set pseudo-op. */
13212 s_mipsset (int x ATTRIBUTE_UNUSED)
13214 char *name = input_line_pointer, ch;
13216 while (!is_end_of_line[(unsigned char) *input_line_pointer])
13217 ++input_line_pointer;
13218 ch = *input_line_pointer;
13219 *input_line_pointer = '\0';
13221 if (strcmp (name, "reorder") == 0)
13223 if (mips_opts.noreorder)
13226 else if (strcmp (name, "noreorder") == 0)
13228 if (!mips_opts.noreorder)
13229 start_noreorder ();
13231 else if (strncmp (name, "at=", 3) == 0)
13233 char *s = name + 3;
13235 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
13236 as_bad (_("Unrecognized register name `%s'"), s);
13238 else if (strcmp (name, "at") == 0)
13240 mips_opts.at = ATREG;
13242 else if (strcmp (name, "noat") == 0)
13244 mips_opts.at = ZERO;
13246 else if (strcmp (name, "macro") == 0)
13248 mips_opts.warn_about_macros = 0;
13250 else if (strcmp (name, "nomacro") == 0)
13252 if (mips_opts.noreorder == 0)
13253 as_bad (_("`noreorder' must be set before `nomacro'"));
13254 mips_opts.warn_about_macros = 1;
13256 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
13258 mips_opts.nomove = 0;
13260 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
13262 mips_opts.nomove = 1;
13264 else if (strcmp (name, "bopt") == 0)
13266 mips_opts.nobopt = 0;
13268 else if (strcmp (name, "nobopt") == 0)
13270 mips_opts.nobopt = 1;
13272 else if (strcmp (name, "gp=default") == 0)
13273 mips_opts.gp32 = file_mips_gp32;
13274 else if (strcmp (name, "gp=32") == 0)
13275 mips_opts.gp32 = 1;
13276 else if (strcmp (name, "gp=64") == 0)
13278 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
13279 as_warn (_("%s isa does not support 64-bit registers"),
13280 mips_cpu_info_from_isa (mips_opts.isa)->name);
13281 mips_opts.gp32 = 0;
13283 else if (strcmp (name, "fp=default") == 0)
13284 mips_opts.fp32 = file_mips_fp32;
13285 else if (strcmp (name, "fp=32") == 0)
13286 mips_opts.fp32 = 1;
13287 else if (strcmp (name, "fp=64") == 0)
13289 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
13290 as_warn (_("%s isa does not support 64-bit floating point registers"),
13291 mips_cpu_info_from_isa (mips_opts.isa)->name);
13292 mips_opts.fp32 = 0;
13294 else if (strcmp (name, "softfloat") == 0)
13295 mips_opts.soft_float = 1;
13296 else if (strcmp (name, "hardfloat") == 0)
13297 mips_opts.soft_float = 0;
13298 else if (strcmp (name, "singlefloat") == 0)
13299 mips_opts.single_float = 1;
13300 else if (strcmp (name, "doublefloat") == 0)
13301 mips_opts.single_float = 0;
13302 else if (strcmp (name, "mips16") == 0
13303 || strcmp (name, "MIPS-16") == 0)
13304 mips_opts.mips16 = 1;
13305 else if (strcmp (name, "nomips16") == 0
13306 || strcmp (name, "noMIPS-16") == 0)
13307 mips_opts.mips16 = 0;
13308 else if (strcmp (name, "smartmips") == 0)
13310 if (!ISA_SUPPORTS_SMARTMIPS)
13311 as_warn (_("%s ISA does not support SmartMIPS ASE"),
13312 mips_cpu_info_from_isa (mips_opts.isa)->name);
13313 mips_opts.ase_smartmips = 1;
13315 else if (strcmp (name, "nosmartmips") == 0)
13316 mips_opts.ase_smartmips = 0;
13317 else if (strcmp (name, "mips3d") == 0)
13318 mips_opts.ase_mips3d = 1;
13319 else if (strcmp (name, "nomips3d") == 0)
13320 mips_opts.ase_mips3d = 0;
13321 else if (strcmp (name, "mdmx") == 0)
13322 mips_opts.ase_mdmx = 1;
13323 else if (strcmp (name, "nomdmx") == 0)
13324 mips_opts.ase_mdmx = 0;
13325 else if (strcmp (name, "dsp") == 0)
13327 if (!ISA_SUPPORTS_DSP_ASE)
13328 as_warn (_("%s ISA does not support DSP ASE"),
13329 mips_cpu_info_from_isa (mips_opts.isa)->name);
13330 mips_opts.ase_dsp = 1;
13331 mips_opts.ase_dspr2 = 0;
13333 else if (strcmp (name, "nodsp") == 0)
13335 mips_opts.ase_dsp = 0;
13336 mips_opts.ase_dspr2 = 0;
13338 else if (strcmp (name, "dspr2") == 0)
13340 if (!ISA_SUPPORTS_DSPR2_ASE)
13341 as_warn (_("%s ISA does not support DSP R2 ASE"),
13342 mips_cpu_info_from_isa (mips_opts.isa)->name);
13343 mips_opts.ase_dspr2 = 1;
13344 mips_opts.ase_dsp = 1;
13346 else if (strcmp (name, "nodspr2") == 0)
13348 mips_opts.ase_dspr2 = 0;
13349 mips_opts.ase_dsp = 0;
13351 else if (strcmp (name, "mt") == 0)
13353 if (!ISA_SUPPORTS_MT_ASE)
13354 as_warn (_("%s ISA does not support MT ASE"),
13355 mips_cpu_info_from_isa (mips_opts.isa)->name);
13356 mips_opts.ase_mt = 1;
13358 else if (strcmp (name, "nomt") == 0)
13359 mips_opts.ase_mt = 0;
13360 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
13364 /* Permit the user to change the ISA and architecture on the fly.
13365 Needless to say, misuse can cause serious problems. */
13366 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
13369 mips_opts.isa = file_mips_isa;
13370 mips_opts.arch = file_mips_arch;
13372 else if (strncmp (name, "arch=", 5) == 0)
13374 const struct mips_cpu_info *p;
13376 p = mips_parse_cpu("internal use", name + 5);
13378 as_bad (_("unknown architecture %s"), name + 5);
13381 mips_opts.arch = p->cpu;
13382 mips_opts.isa = p->isa;
13385 else if (strncmp (name, "mips", 4) == 0)
13387 const struct mips_cpu_info *p;
13389 p = mips_parse_cpu("internal use", name);
13391 as_bad (_("unknown ISA level %s"), name + 4);
13394 mips_opts.arch = p->cpu;
13395 mips_opts.isa = p->isa;
13399 as_bad (_("unknown ISA or architecture %s"), name);
13401 switch (mips_opts.isa)
13409 mips_opts.gp32 = 1;
13410 mips_opts.fp32 = 1;
13417 mips_opts.gp32 = 0;
13418 mips_opts.fp32 = 0;
13421 as_bad (_("unknown ISA level %s"), name + 4);
13426 mips_opts.gp32 = file_mips_gp32;
13427 mips_opts.fp32 = file_mips_fp32;
13430 else if (strcmp (name, "autoextend") == 0)
13431 mips_opts.noautoextend = 0;
13432 else if (strcmp (name, "noautoextend") == 0)
13433 mips_opts.noautoextend = 1;
13434 else if (strcmp (name, "push") == 0)
13436 struct mips_option_stack *s;
13438 s = (struct mips_option_stack *) xmalloc (sizeof *s);
13439 s->next = mips_opts_stack;
13440 s->options = mips_opts;
13441 mips_opts_stack = s;
13443 else if (strcmp (name, "pop") == 0)
13445 struct mips_option_stack *s;
13447 s = mips_opts_stack;
13449 as_bad (_(".set pop with no .set push"));
13452 /* If we're changing the reorder mode we need to handle
13453 delay slots correctly. */
13454 if (s->options.noreorder && ! mips_opts.noreorder)
13455 start_noreorder ();
13456 else if (! s->options.noreorder && mips_opts.noreorder)
13459 mips_opts = s->options;
13460 mips_opts_stack = s->next;
13464 else if (strcmp (name, "sym32") == 0)
13465 mips_opts.sym32 = TRUE;
13466 else if (strcmp (name, "nosym32") == 0)
13467 mips_opts.sym32 = FALSE;
13468 else if (strchr (name, ','))
13470 /* Generic ".set" directive; use the generic handler. */
13471 *input_line_pointer = ch;
13472 input_line_pointer = name;
13478 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
13480 *input_line_pointer = ch;
13481 demand_empty_rest_of_line ();
13484 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
13485 .option pic2. It means to generate SVR4 PIC calls. */
13488 s_abicalls (int ignore ATTRIBUTE_UNUSED)
13490 mips_pic = SVR4_PIC;
13491 mips_abicalls = TRUE;
13493 if (g_switch_seen && g_switch_value != 0)
13494 as_warn (_("-G may not be used with SVR4 PIC code"));
13495 g_switch_value = 0;
13497 bfd_set_gp_size (stdoutput, 0);
13498 demand_empty_rest_of_line ();
13501 /* Handle the .cpload pseudo-op. This is used when generating SVR4
13502 PIC code. It sets the $gp register for the function based on the
13503 function address, which is in the register named in the argument.
13504 This uses a relocation against _gp_disp, which is handled specially
13505 by the linker. The result is:
13506 lui $gp,%hi(_gp_disp)
13507 addiu $gp,$gp,%lo(_gp_disp)
13508 addu $gp,$gp,.cpload argument
13509 The .cpload argument is normally $25 == $t9.
13511 The -mno-shared option changes this to:
13512 lui $gp,%hi(__gnu_local_gp)
13513 addiu $gp,$gp,%lo(__gnu_local_gp)
13514 and the argument is ignored. This saves an instruction, but the
13515 resulting code is not position independent; it uses an absolute
13516 address for __gnu_local_gp. Thus code assembled with -mno-shared
13517 can go into an ordinary executable, but not into a shared library. */
13520 s_cpload (int ignore ATTRIBUTE_UNUSED)
13526 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13527 .cpload is ignored. */
13528 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
13534 /* .cpload should be in a .set noreorder section. */
13535 if (mips_opts.noreorder == 0)
13536 as_warn (_(".cpload not in noreorder section"));
13538 reg = tc_get_register (0);
13540 /* If we need to produce a 64-bit address, we are better off using
13541 the default instruction sequence. */
13542 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
13544 ex.X_op = O_symbol;
13545 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
13547 ex.X_op_symbol = NULL;
13548 ex.X_add_number = 0;
13550 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13551 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
13554 macro_build_lui (&ex, mips_gp_register);
13555 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
13556 mips_gp_register, BFD_RELOC_LO16);
13558 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
13559 mips_gp_register, reg);
13562 demand_empty_rest_of_line ();
13565 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
13566 .cpsetup $reg1, offset|$reg2, label
13568 If offset is given, this results in:
13569 sd $gp, offset($sp)
13570 lui $gp, %hi(%neg(%gp_rel(label)))
13571 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13572 daddu $gp, $gp, $reg1
13574 If $reg2 is given, this results in:
13575 daddu $reg2, $gp, $0
13576 lui $gp, %hi(%neg(%gp_rel(label)))
13577 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13578 daddu $gp, $gp, $reg1
13579 $reg1 is normally $25 == $t9.
13581 The -mno-shared option replaces the last three instructions with
13583 addiu $gp,$gp,%lo(_gp) */
13586 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
13588 expressionS ex_off;
13589 expressionS ex_sym;
13592 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
13593 We also need NewABI support. */
13594 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13600 reg1 = tc_get_register (0);
13601 SKIP_WHITESPACE ();
13602 if (*input_line_pointer != ',')
13604 as_bad (_("missing argument separator ',' for .cpsetup"));
13608 ++input_line_pointer;
13609 SKIP_WHITESPACE ();
13610 if (*input_line_pointer == '$')
13612 mips_cpreturn_register = tc_get_register (0);
13613 mips_cpreturn_offset = -1;
13617 mips_cpreturn_offset = get_absolute_expression ();
13618 mips_cpreturn_register = -1;
13620 SKIP_WHITESPACE ();
13621 if (*input_line_pointer != ',')
13623 as_bad (_("missing argument separator ',' for .cpsetup"));
13627 ++input_line_pointer;
13628 SKIP_WHITESPACE ();
13629 expression (&ex_sym);
13632 if (mips_cpreturn_register == -1)
13634 ex_off.X_op = O_constant;
13635 ex_off.X_add_symbol = NULL;
13636 ex_off.X_op_symbol = NULL;
13637 ex_off.X_add_number = mips_cpreturn_offset;
13639 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
13640 BFD_RELOC_LO16, SP);
13643 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
13644 mips_gp_register, 0);
13646 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
13648 macro_build (&ex_sym, "lui", "t,u", mips_gp_register,
13649 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
13652 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
13653 mips_gp_register, -1, BFD_RELOC_GPREL16,
13654 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
13656 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
13657 mips_gp_register, reg1);
13663 ex.X_op = O_symbol;
13664 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
13665 ex.X_op_symbol = NULL;
13666 ex.X_add_number = 0;
13668 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13669 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
13671 macro_build_lui (&ex, mips_gp_register);
13672 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
13673 mips_gp_register, BFD_RELOC_LO16);
13678 demand_empty_rest_of_line ();
13682 s_cplocal (int ignore ATTRIBUTE_UNUSED)
13684 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
13685 .cplocal is ignored. */
13686 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13692 mips_gp_register = tc_get_register (0);
13693 demand_empty_rest_of_line ();
13696 /* Handle the .cprestore pseudo-op. This stores $gp into a given
13697 offset from $sp. The offset is remembered, and after making a PIC
13698 call $gp is restored from that location. */
13701 s_cprestore (int ignore ATTRIBUTE_UNUSED)
13705 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13706 .cprestore is ignored. */
13707 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
13713 mips_cprestore_offset = get_absolute_expression ();
13714 mips_cprestore_valid = 1;
13716 ex.X_op = O_constant;
13717 ex.X_add_symbol = NULL;
13718 ex.X_op_symbol = NULL;
13719 ex.X_add_number = mips_cprestore_offset;
13722 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
13723 SP, HAVE_64BIT_ADDRESSES);
13726 demand_empty_rest_of_line ();
13729 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
13730 was given in the preceding .cpsetup, it results in:
13731 ld $gp, offset($sp)
13733 If a register $reg2 was given there, it results in:
13734 daddu $gp, $reg2, $0 */
13737 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
13741 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
13742 We also need NewABI support. */
13743 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13750 if (mips_cpreturn_register == -1)
13752 ex.X_op = O_constant;
13753 ex.X_add_symbol = NULL;
13754 ex.X_op_symbol = NULL;
13755 ex.X_add_number = mips_cpreturn_offset;
13757 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
13760 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
13761 mips_cpreturn_register, 0);
13764 demand_empty_rest_of_line ();
13767 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
13768 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
13769 use in DWARF debug information. */
13772 s_dtprel_internal (size_t bytes)
13779 if (ex.X_op != O_symbol)
13781 as_bad (_("Unsupported use of %s"), (bytes == 8
13784 ignore_rest_of_line ();
13787 p = frag_more (bytes);
13788 md_number_to_chars (p, 0, bytes);
13789 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
13791 ? BFD_RELOC_MIPS_TLS_DTPREL64
13792 : BFD_RELOC_MIPS_TLS_DTPREL32));
13794 demand_empty_rest_of_line ();
13797 /* Handle .dtprelword. */
13800 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
13802 s_dtprel_internal (4);
13805 /* Handle .dtpreldword. */
13808 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
13810 s_dtprel_internal (8);
13813 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
13814 code. It sets the offset to use in gp_rel relocations. */
13817 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
13819 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
13820 We also need NewABI support. */
13821 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13827 mips_gprel_offset = get_absolute_expression ();
13829 demand_empty_rest_of_line ();
13832 /* Handle the .gpword pseudo-op. This is used when generating PIC
13833 code. It generates a 32 bit GP relative reloc. */
13836 s_gpword (int ignore ATTRIBUTE_UNUSED)
13838 segment_info_type *si;
13839 struct insn_label_list *l;
13844 /* When not generating PIC code, this is treated as .word. */
13845 if (mips_pic != SVR4_PIC)
13851 si = seg_info (now_seg);
13852 l = si->label_list;
13853 label = l != NULL ? l->label : NULL;
13854 mips_emit_delays ();
13856 mips_align (2, 0, label);
13859 mips_clear_insn_labels ();
13861 if (ex.X_op != O_symbol || ex.X_add_number != 0)
13863 as_bad (_("Unsupported use of .gpword"));
13864 ignore_rest_of_line ();
13868 md_number_to_chars (p, 0, 4);
13869 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
13870 BFD_RELOC_GPREL32);
13872 demand_empty_rest_of_line ();
13876 s_gpdword (int ignore ATTRIBUTE_UNUSED)
13878 segment_info_type *si;
13879 struct insn_label_list *l;
13884 /* When not generating PIC code, this is treated as .dword. */
13885 if (mips_pic != SVR4_PIC)
13891 si = seg_info (now_seg);
13892 l = si->label_list;
13893 label = l != NULL ? l->label : NULL;
13894 mips_emit_delays ();
13896 mips_align (3, 0, label);
13899 mips_clear_insn_labels ();
13901 if (ex.X_op != O_symbol || ex.X_add_number != 0)
13903 as_bad (_("Unsupported use of .gpdword"));
13904 ignore_rest_of_line ();
13908 md_number_to_chars (p, 0, 8);
13909 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
13910 BFD_RELOC_GPREL32)->fx_tcbit = 1;
13912 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
13913 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
13914 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
13916 demand_empty_rest_of_line ();
13919 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
13920 tables in SVR4 PIC code. */
13923 s_cpadd (int ignore ATTRIBUTE_UNUSED)
13927 /* This is ignored when not generating SVR4 PIC code. */
13928 if (mips_pic != SVR4_PIC)
13934 /* Add $gp to the register named as an argument. */
13936 reg = tc_get_register (0);
13937 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
13940 demand_empty_rest_of_line ();
13943 /* Handle the .insn pseudo-op. This marks instruction labels in
13944 mips16 mode. This permits the linker to handle them specially,
13945 such as generating jalx instructions when needed. We also make
13946 them odd for the duration of the assembly, in order to generate the
13947 right sort of code. We will make them even in the adjust_symtab
13948 routine, while leaving them marked. This is convenient for the
13949 debugger and the disassembler. The linker knows to make them odd
13953 s_insn (int ignore ATTRIBUTE_UNUSED)
13955 mips16_mark_labels ();
13957 demand_empty_rest_of_line ();
13960 /* Handle a .stabn directive. We need these in order to mark a label
13961 as being a mips16 text label correctly. Sometimes the compiler
13962 will emit a label, followed by a .stabn, and then switch sections.
13963 If the label and .stabn are in mips16 mode, then the label is
13964 really a mips16 text label. */
13967 s_mips_stab (int type)
13970 mips16_mark_labels ();
13975 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
13978 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
13985 name = input_line_pointer;
13986 c = get_symbol_end ();
13987 symbolP = symbol_find_or_make (name);
13988 S_SET_WEAK (symbolP);
13989 *input_line_pointer = c;
13991 SKIP_WHITESPACE ();
13993 if (! is_end_of_line[(unsigned char) *input_line_pointer])
13995 if (S_IS_DEFINED (symbolP))
13997 as_bad (_("ignoring attempt to redefine symbol %s"),
13998 S_GET_NAME (symbolP));
13999 ignore_rest_of_line ();
14003 if (*input_line_pointer == ',')
14005 ++input_line_pointer;
14006 SKIP_WHITESPACE ();
14010 if (exp.X_op != O_symbol)
14012 as_bad (_("bad .weakext directive"));
14013 ignore_rest_of_line ();
14016 symbol_set_value_expression (symbolP, &exp);
14019 demand_empty_rest_of_line ();
14022 /* Parse a register string into a number. Called from the ECOFF code
14023 to parse .frame. The argument is non-zero if this is the frame
14024 register, so that we can record it in mips_frame_reg. */
14027 tc_get_register (int frame)
14031 SKIP_WHITESPACE ();
14032 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
14036 mips_frame_reg = reg != 0 ? reg : SP;
14037 mips_frame_reg_valid = 1;
14038 mips_cprestore_valid = 0;
14044 md_section_align (asection *seg, valueT addr)
14046 int align = bfd_get_section_alignment (stdoutput, seg);
14050 /* We don't need to align ELF sections to the full alignment.
14051 However, Irix 5 may prefer that we align them at least to a 16
14052 byte boundary. We don't bother to align the sections if we
14053 are targeted for an embedded system. */
14054 if (strncmp (TARGET_OS, "elf", 3) == 0)
14060 return ((addr + (1 << align) - 1) & (-1 << align));
14063 /* Utility routine, called from above as well. If called while the
14064 input file is still being read, it's only an approximation. (For
14065 example, a symbol may later become defined which appeared to be
14066 undefined earlier.) */
14069 nopic_need_relax (symbolS *sym, int before_relaxing)
14074 if (g_switch_value > 0)
14076 const char *symname;
14079 /* Find out whether this symbol can be referenced off the $gp
14080 register. It can be if it is smaller than the -G size or if
14081 it is in the .sdata or .sbss section. Certain symbols can
14082 not be referenced off the $gp, although it appears as though
14084 symname = S_GET_NAME (sym);
14085 if (symname != (const char *) NULL
14086 && (strcmp (symname, "eprol") == 0
14087 || strcmp (symname, "etext") == 0
14088 || strcmp (symname, "_gp") == 0
14089 || strcmp (symname, "edata") == 0
14090 || strcmp (symname, "_fbss") == 0
14091 || strcmp (symname, "_fdata") == 0
14092 || strcmp (symname, "_ftext") == 0
14093 || strcmp (symname, "end") == 0
14094 || strcmp (symname, "_gp_disp") == 0))
14096 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
14098 #ifndef NO_ECOFF_DEBUGGING
14099 || (symbol_get_obj (sym)->ecoff_extern_size != 0
14100 && (symbol_get_obj (sym)->ecoff_extern_size
14101 <= g_switch_value))
14103 /* We must defer this decision until after the whole
14104 file has been read, since there might be a .extern
14105 after the first use of this symbol. */
14106 || (before_relaxing
14107 #ifndef NO_ECOFF_DEBUGGING
14108 && symbol_get_obj (sym)->ecoff_extern_size == 0
14110 && S_GET_VALUE (sym) == 0)
14111 || (S_GET_VALUE (sym) != 0
14112 && S_GET_VALUE (sym) <= g_switch_value)))
14116 const char *segname;
14118 segname = segment_name (S_GET_SEGMENT (sym));
14119 gas_assert (strcmp (segname, ".lit8") != 0
14120 && strcmp (segname, ".lit4") != 0);
14121 change = (strcmp (segname, ".sdata") != 0
14122 && strcmp (segname, ".sbss") != 0
14123 && strncmp (segname, ".sdata.", 7) != 0
14124 && strncmp (segname, ".sbss.", 6) != 0
14125 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
14126 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
14131 /* We are not optimizing for the $gp register. */
14136 /* Return true if the given symbol should be considered local for SVR4 PIC. */
14139 pic_need_relax (symbolS *sym, asection *segtype)
14143 /* Handle the case of a symbol equated to another symbol. */
14144 while (symbol_equated_reloc_p (sym))
14148 /* It's possible to get a loop here in a badly written program. */
14149 n = symbol_get_value_expression (sym)->X_add_symbol;
14155 if (symbol_section_p (sym))
14158 symsec = S_GET_SEGMENT (sym);
14160 /* This must duplicate the test in adjust_reloc_syms. */
14161 return (symsec != &bfd_und_section
14162 && symsec != &bfd_abs_section
14163 && !bfd_is_com_section (symsec)
14164 && !s_is_linkonce (sym, segtype)
14166 /* A global or weak symbol is treated as external. */
14167 && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
14173 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
14174 extended opcode. SEC is the section the frag is in. */
14177 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
14180 const struct mips16_immed_operand *op;
14182 int mintiny, maxtiny;
14186 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
14188 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
14191 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
14192 op = mips16_immed_operands;
14193 while (op->type != type)
14196 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
14201 if (type == '<' || type == '>' || type == '[' || type == ']')
14204 maxtiny = 1 << op->nbits;
14209 maxtiny = (1 << op->nbits) - 1;
14214 mintiny = - (1 << (op->nbits - 1));
14215 maxtiny = (1 << (op->nbits - 1)) - 1;
14218 sym_frag = symbol_get_frag (fragp->fr_symbol);
14219 val = S_GET_VALUE (fragp->fr_symbol);
14220 symsec = S_GET_SEGMENT (fragp->fr_symbol);
14226 /* We won't have the section when we are called from
14227 mips_relax_frag. However, we will always have been called
14228 from md_estimate_size_before_relax first. If this is a
14229 branch to a different section, we mark it as such. If SEC is
14230 NULL, and the frag is not marked, then it must be a branch to
14231 the same section. */
14234 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
14239 /* Must have been called from md_estimate_size_before_relax. */
14242 fragp->fr_subtype =
14243 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14245 /* FIXME: We should support this, and let the linker
14246 catch branches and loads that are out of range. */
14247 as_bad_where (fragp->fr_file, fragp->fr_line,
14248 _("unsupported PC relative reference to different section"));
14252 if (fragp != sym_frag && sym_frag->fr_address == 0)
14253 /* Assume non-extended on the first relaxation pass.
14254 The address we have calculated will be bogus if this is
14255 a forward branch to another frag, as the forward frag
14256 will have fr_address == 0. */
14260 /* In this case, we know for sure that the symbol fragment is in
14261 the same section. If the relax_marker of the symbol fragment
14262 differs from the relax_marker of this fragment, we have not
14263 yet adjusted the symbol fragment fr_address. We want to add
14264 in STRETCH in order to get a better estimate of the address.
14265 This particularly matters because of the shift bits. */
14267 && sym_frag->relax_marker != fragp->relax_marker)
14271 /* Adjust stretch for any alignment frag. Note that if have
14272 been expanding the earlier code, the symbol may be
14273 defined in what appears to be an earlier frag. FIXME:
14274 This doesn't handle the fr_subtype field, which specifies
14275 a maximum number of bytes to skip when doing an
14277 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
14279 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
14282 stretch = - ((- stretch)
14283 & ~ ((1 << (int) f->fr_offset) - 1));
14285 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
14294 addr = fragp->fr_address + fragp->fr_fix;
14296 /* The base address rules are complicated. The base address of
14297 a branch is the following instruction. The base address of a
14298 PC relative load or add is the instruction itself, but if it
14299 is in a delay slot (in which case it can not be extended) use
14300 the address of the instruction whose delay slot it is in. */
14301 if (type == 'p' || type == 'q')
14305 /* If we are currently assuming that this frag should be
14306 extended, then, the current address is two bytes
14308 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14311 /* Ignore the low bit in the target, since it will be set
14312 for a text label. */
14313 if ((val & 1) != 0)
14316 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
14318 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
14321 val -= addr & ~ ((1 << op->shift) - 1);
14323 /* Branch offsets have an implicit 0 in the lowest bit. */
14324 if (type == 'p' || type == 'q')
14327 /* If any of the shifted bits are set, we must use an extended
14328 opcode. If the address depends on the size of this
14329 instruction, this can lead to a loop, so we arrange to always
14330 use an extended opcode. We only check this when we are in
14331 the main relaxation loop, when SEC is NULL. */
14332 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
14334 fragp->fr_subtype =
14335 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14339 /* If we are about to mark a frag as extended because the value
14340 is precisely maxtiny + 1, then there is a chance of an
14341 infinite loop as in the following code:
14346 In this case when the la is extended, foo is 0x3fc bytes
14347 away, so the la can be shrunk, but then foo is 0x400 away, so
14348 the la must be extended. To avoid this loop, we mark the
14349 frag as extended if it was small, and is about to become
14350 extended with a value of maxtiny + 1. */
14351 if (val == ((maxtiny + 1) << op->shift)
14352 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
14355 fragp->fr_subtype =
14356 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14360 else if (symsec != absolute_section && sec != NULL)
14361 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
14363 if ((val & ((1 << op->shift) - 1)) != 0
14364 || val < (mintiny << op->shift)
14365 || val > (maxtiny << op->shift))
14371 /* Compute the length of a branch sequence, and adjust the
14372 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
14373 worst-case length is computed, with UPDATE being used to indicate
14374 whether an unconditional (-1), branch-likely (+1) or regular (0)
14375 branch is to be computed. */
14377 relaxed_branch_length (fragS *fragp, asection *sec, int update)
14379 bfd_boolean toofar;
14383 && S_IS_DEFINED (fragp->fr_symbol)
14384 && sec == S_GET_SEGMENT (fragp->fr_symbol))
14389 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
14391 addr = fragp->fr_address + fragp->fr_fix + 4;
14395 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
14398 /* If the symbol is not defined or it's in a different segment,
14399 assume the user knows what's going on and emit a short
14405 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
14407 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
14408 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
14409 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
14410 RELAX_BRANCH_LINK (fragp->fr_subtype),
14416 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
14419 if (mips_pic != NO_PIC)
14421 /* Additional space for PIC loading of target address. */
14423 if (mips_opts.isa == ISA_MIPS1)
14424 /* Additional space for $at-stabilizing nop. */
14428 /* If branch is conditional. */
14429 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
14436 /* Estimate the size of a frag before relaxing. Unless this is the
14437 mips16, we are not really relaxing here, and the final size is
14438 encoded in the subtype information. For the mips16, we have to
14439 decide whether we are using an extended opcode or not. */
14442 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
14446 if (RELAX_BRANCH_P (fragp->fr_subtype))
14449 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
14451 return fragp->fr_var;
14454 if (RELAX_MIPS16_P (fragp->fr_subtype))
14455 /* We don't want to modify the EXTENDED bit here; it might get us
14456 into infinite loops. We change it only in mips_relax_frag(). */
14457 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
14459 if (mips_pic == NO_PIC)
14460 change = nopic_need_relax (fragp->fr_symbol, 0);
14461 else if (mips_pic == SVR4_PIC)
14462 change = pic_need_relax (fragp->fr_symbol, segtype);
14463 else if (mips_pic == VXWORKS_PIC)
14464 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
14471 fragp->fr_subtype |= RELAX_USE_SECOND;
14472 return -RELAX_FIRST (fragp->fr_subtype);
14475 return -RELAX_SECOND (fragp->fr_subtype);
14478 /* This is called to see whether a reloc against a defined symbol
14479 should be converted into a reloc against a section. */
14482 mips_fix_adjustable (fixS *fixp)
14484 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
14485 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
14488 if (fixp->fx_addsy == NULL)
14491 /* If symbol SYM is in a mergeable section, relocations of the form
14492 SYM + 0 can usually be made section-relative. The mergeable data
14493 is then identified by the section offset rather than by the symbol.
14495 However, if we're generating REL LO16 relocations, the offset is split
14496 between the LO16 and parterning high part relocation. The linker will
14497 need to recalculate the complete offset in order to correctly identify
14500 The linker has traditionally not looked for the parterning high part
14501 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
14502 placed anywhere. Rather than break backwards compatibility by changing
14503 this, it seems better not to force the issue, and instead keep the
14504 original symbol. This will work with either linker behavior. */
14505 if ((lo16_reloc_p (fixp->fx_r_type)
14506 || reloc_needs_lo_p (fixp->fx_r_type))
14507 && HAVE_IN_PLACE_ADDENDS
14508 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
14511 /* There is no place to store an in-place offset for JALR relocations.
14512 Likewise an in-range offset of PC-relative relocations may overflow
14513 the in-place relocatable field if recalculated against the start
14514 address of the symbol's containing section. */
14515 if (HAVE_IN_PLACE_ADDENDS
14516 && (fixp->fx_pcrel || fixp->fx_r_type == BFD_RELOC_MIPS_JALR))
14520 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
14521 to a floating-point stub. The same is true for non-R_MIPS16_26
14522 relocations against MIPS16 functions; in this case, the stub becomes
14523 the function's canonical address.
14525 Floating-point stubs are stored in unique .mips16.call.* or
14526 .mips16.fn.* sections. If a stub T for function F is in section S,
14527 the first relocation in section S must be against F; this is how the
14528 linker determines the target function. All relocations that might
14529 resolve to T must also be against F. We therefore have the following
14530 restrictions, which are given in an intentionally-redundant way:
14532 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
14535 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
14536 if that stub might be used.
14538 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
14541 4. We cannot reduce a stub's relocations against MIPS16 symbols if
14542 that stub might be used.
14544 There is a further restriction:
14546 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols
14547 on targets with in-place addends; the relocation field cannot
14548 encode the low bit.
14550 For simplicity, we deal with (3)-(5) by not reducing _any_ relocation
14551 against a MIPS16 symbol.
14553 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
14554 relocation against some symbol R, no relocation against R may be
14555 reduced. (Note that this deals with (2) as well as (1) because
14556 relocations against global symbols will never be reduced on ELF
14557 targets.) This approach is a little simpler than trying to detect
14558 stub sections, and gives the "all or nothing" per-symbol consistency
14559 that we have for MIPS16 symbols. */
14561 && fixp->fx_subsy == NULL
14562 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
14563 || *symbol_get_tc (fixp->fx_addsy)))
14570 /* Translate internal representation of relocation info to BFD target
14574 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
14576 static arelent *retval[4];
14578 bfd_reloc_code_real_type code;
14580 memset (retval, 0, sizeof(retval));
14581 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
14582 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
14583 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
14584 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
14586 if (fixp->fx_pcrel)
14588 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2);
14590 /* At this point, fx_addnumber is "symbol offset - pcrel address".
14591 Relocations want only the symbol offset. */
14592 reloc->addend = fixp->fx_addnumber + reloc->address;
14595 /* A gruesome hack which is a result of the gruesome gas
14596 reloc handling. What's worse, for COFF (as opposed to
14597 ECOFF), we might need yet another copy of reloc->address.
14598 See bfd_install_relocation. */
14599 reloc->addend += reloc->address;
14603 reloc->addend = fixp->fx_addnumber;
14605 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
14606 entry to be used in the relocation's section offset. */
14607 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
14609 reloc->address = reloc->addend;
14613 code = fixp->fx_r_type;
14615 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
14616 if (reloc->howto == NULL)
14618 as_bad_where (fixp->fx_file, fixp->fx_line,
14619 _("Can not represent %s relocation in this object file format"),
14620 bfd_get_reloc_code_name (code));
14627 /* Relax a machine dependent frag. This returns the amount by which
14628 the current size of the frag should change. */
14631 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
14633 if (RELAX_BRANCH_P (fragp->fr_subtype))
14635 offsetT old_var = fragp->fr_var;
14637 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
14639 return fragp->fr_var - old_var;
14642 if (! RELAX_MIPS16_P (fragp->fr_subtype))
14645 if (mips16_extended_frag (fragp, NULL, stretch))
14647 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14649 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
14654 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14656 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
14663 /* Convert a machine dependent frag. */
14666 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
14668 if (RELAX_BRANCH_P (fragp->fr_subtype))
14671 unsigned long insn;
14675 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
14677 if (target_big_endian)
14678 insn = bfd_getb32 (buf);
14680 insn = bfd_getl32 (buf);
14682 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
14684 /* We generate a fixup instead of applying it right now
14685 because, if there are linker relaxations, we're going to
14686 need the relocations. */
14687 exp.X_op = O_symbol;
14688 exp.X_add_symbol = fragp->fr_symbol;
14689 exp.X_add_number = fragp->fr_offset;
14691 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14692 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2);
14693 fixp->fx_file = fragp->fr_file;
14694 fixp->fx_line = fragp->fr_line;
14696 md_number_to_chars ((char *) buf, insn, 4);
14703 as_warn_where (fragp->fr_file, fragp->fr_line,
14704 _("Relaxed out-of-range branch into a jump"));
14706 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
14709 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14711 /* Reverse the branch. */
14712 switch ((insn >> 28) & 0xf)
14715 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
14716 have the condition reversed by tweaking a single
14717 bit, and their opcodes all have 0x4???????. */
14718 gas_assert ((insn & 0xf1000000) == 0x41000000);
14719 insn ^= 0x00010000;
14723 /* bltz 0x04000000 bgez 0x04010000
14724 bltzal 0x04100000 bgezal 0x04110000 */
14725 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
14726 insn ^= 0x00010000;
14730 /* beq 0x10000000 bne 0x14000000
14731 blez 0x18000000 bgtz 0x1c000000 */
14732 insn ^= 0x04000000;
14740 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
14742 /* Clear the and-link bit. */
14743 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
14745 /* bltzal 0x04100000 bgezal 0x04110000
14746 bltzall 0x04120000 bgezall 0x04130000 */
14747 insn &= ~0x00100000;
14750 /* Branch over the branch (if the branch was likely) or the
14751 full jump (not likely case). Compute the offset from the
14752 current instruction to branch to. */
14753 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14757 /* How many bytes in instructions we've already emitted? */
14758 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
14759 /* How many bytes in instructions from here to the end? */
14760 i = fragp->fr_var - i;
14762 /* Convert to instruction count. */
14764 /* Branch counts from the next instruction. */
14767 /* Branch over the jump. */
14768 md_number_to_chars ((char *) buf, insn, 4);
14772 md_number_to_chars ((char *) buf, 0, 4);
14775 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14777 /* beql $0, $0, 2f */
14779 /* Compute the PC offset from the current instruction to
14780 the end of the variable frag. */
14781 /* How many bytes in instructions we've already emitted? */
14782 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
14783 /* How many bytes in instructions from here to the end? */
14784 i = fragp->fr_var - i;
14785 /* Convert to instruction count. */
14787 /* Don't decrement i, because we want to branch over the
14791 md_number_to_chars ((char *) buf, insn, 4);
14794 md_number_to_chars ((char *) buf, 0, 4);
14799 if (mips_pic == NO_PIC)
14802 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
14803 ? 0x0c000000 : 0x08000000);
14804 exp.X_op = O_symbol;
14805 exp.X_add_symbol = fragp->fr_symbol;
14806 exp.X_add_number = fragp->fr_offset;
14808 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14809 4, &exp, FALSE, BFD_RELOC_MIPS_JMP);
14810 fixp->fx_file = fragp->fr_file;
14811 fixp->fx_line = fragp->fr_line;
14813 md_number_to_chars ((char *) buf, insn, 4);
14818 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
14820 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
14821 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
14822 insn |= at << OP_SH_RT;
14823 exp.X_op = O_symbol;
14824 exp.X_add_symbol = fragp->fr_symbol;
14825 exp.X_add_number = fragp->fr_offset;
14827 if (fragp->fr_offset)
14829 exp.X_add_symbol = make_expr_symbol (&exp);
14830 exp.X_add_number = 0;
14833 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14834 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16);
14835 fixp->fx_file = fragp->fr_file;
14836 fixp->fx_line = fragp->fr_line;
14838 md_number_to_chars ((char *) buf, insn, 4);
14841 if (mips_opts.isa == ISA_MIPS1)
14844 md_number_to_chars ((char *) buf, 0, 4);
14848 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
14849 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
14850 insn |= at << OP_SH_RS | at << OP_SH_RT;
14852 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14853 4, &exp, FALSE, BFD_RELOC_LO16);
14854 fixp->fx_file = fragp->fr_file;
14855 fixp->fx_line = fragp->fr_line;
14857 md_number_to_chars ((char *) buf, insn, 4);
14861 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
14865 insn |= at << OP_SH_RS;
14867 md_number_to_chars ((char *) buf, insn, 4);
14872 gas_assert (buf == (bfd_byte *)fragp->fr_literal
14873 + fragp->fr_fix + fragp->fr_var);
14875 fragp->fr_fix += fragp->fr_var;
14880 if (RELAX_MIPS16_P (fragp->fr_subtype))
14883 const struct mips16_immed_operand *op;
14884 bfd_boolean small, ext;
14887 unsigned long insn;
14888 bfd_boolean use_extend;
14889 unsigned short extend;
14891 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
14892 op = mips16_immed_operands;
14893 while (op->type != type)
14896 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14907 val = resolve_symbol_value (fragp->fr_symbol);
14912 addr = fragp->fr_address + fragp->fr_fix;
14914 /* The rules for the base address of a PC relative reloc are
14915 complicated; see mips16_extended_frag. */
14916 if (type == 'p' || type == 'q')
14921 /* Ignore the low bit in the target, since it will be
14922 set for a text label. */
14923 if ((val & 1) != 0)
14926 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
14928 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
14931 addr &= ~ (addressT) ((1 << op->shift) - 1);
14934 /* Make sure the section winds up with the alignment we have
14937 record_alignment (asec, op->shift);
14941 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
14942 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
14943 as_warn_where (fragp->fr_file, fragp->fr_line,
14944 _("extended instruction in delay slot"));
14946 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
14948 if (target_big_endian)
14949 insn = bfd_getb16 (buf);
14951 insn = bfd_getl16 (buf);
14953 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
14954 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
14955 small, ext, &insn, &use_extend, &extend);
14959 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
14960 fragp->fr_fix += 2;
14964 md_number_to_chars ((char *) buf, insn, 2);
14965 fragp->fr_fix += 2;
14973 first = RELAX_FIRST (fragp->fr_subtype);
14974 second = RELAX_SECOND (fragp->fr_subtype);
14975 fixp = (fixS *) fragp->fr_opcode;
14977 /* Possibly emit a warning if we've chosen the longer option. */
14978 if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0)
14979 == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0))
14981 const char *msg = macro_warning (fragp->fr_subtype);
14983 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
14986 /* Go through all the fixups for the first sequence. Disable them
14987 (by marking them as done) if we're going to use the second
14988 sequence instead. */
14990 && fixp->fx_frag == fragp
14991 && fixp->fx_where < fragp->fr_fix - second)
14993 if (fragp->fr_subtype & RELAX_USE_SECOND)
14995 fixp = fixp->fx_next;
14998 /* Go through the fixups for the second sequence. Disable them if
14999 we're going to use the first sequence, otherwise adjust their
15000 addresses to account for the relaxation. */
15001 while (fixp && fixp->fx_frag == fragp)
15003 if (fragp->fr_subtype & RELAX_USE_SECOND)
15004 fixp->fx_where -= first;
15007 fixp = fixp->fx_next;
15010 /* Now modify the frag contents. */
15011 if (fragp->fr_subtype & RELAX_USE_SECOND)
15015 start = fragp->fr_literal + fragp->fr_fix - first - second;
15016 memmove (start, start + first, second);
15017 fragp->fr_fix -= first;
15020 fragp->fr_fix -= second;
15026 /* This function is called after the relocs have been generated.
15027 We've been storing mips16 text labels as odd. Here we convert them
15028 back to even for the convenience of the debugger. */
15031 mips_frob_file_after_relocs (void)
15034 unsigned int count, i;
15039 syms = bfd_get_outsymbols (stdoutput);
15040 count = bfd_get_symcount (stdoutput);
15041 for (i = 0; i < count; i++, syms++)
15043 if (ELF_ST_IS_MIPS16 (elf_symbol (*syms)->internal_elf_sym.st_other)
15044 && ((*syms)->value & 1) != 0)
15046 (*syms)->value &= ~1;
15047 /* If the symbol has an odd size, it was probably computed
15048 incorrectly, so adjust that as well. */
15049 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
15050 ++elf_symbol (*syms)->internal_elf_sym.st_size;
15057 /* This function is called whenever a label is defined, including fake
15058 labels instantiated off the dot special symbol. It is used when
15059 handling branch delays; if a branch has a label, we assume we cannot
15060 move it. This also bumps the value of the symbol by 1 in compressed
15064 mips_record_label (symbolS *sym)
15066 segment_info_type *si = seg_info (now_seg);
15067 struct insn_label_list *l;
15069 if (free_insn_labels == NULL)
15070 l = (struct insn_label_list *) xmalloc (sizeof *l);
15073 l = free_insn_labels;
15074 free_insn_labels = l->next;
15078 l->next = si->label_list;
15079 si->label_list = l;
15082 /* This function is called as tc_frob_label() whenever a label is defined
15083 and adds a DWARF-2 record we only want for true labels. */
15086 mips_define_label (symbolS *sym)
15088 mips_record_label (sym);
15090 dwarf2_emit_label (sym);
15094 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15096 /* Some special processing for a MIPS ELF file. */
15099 mips_elf_final_processing (void)
15101 /* Write out the register information. */
15102 if (mips_abi != N64_ABI)
15106 s.ri_gprmask = mips_gprmask;
15107 s.ri_cprmask[0] = mips_cprmask[0];
15108 s.ri_cprmask[1] = mips_cprmask[1];
15109 s.ri_cprmask[2] = mips_cprmask[2];
15110 s.ri_cprmask[3] = mips_cprmask[3];
15111 /* The gp_value field is set by the MIPS ELF backend. */
15113 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
15114 ((Elf32_External_RegInfo *)
15115 mips_regmask_frag));
15119 Elf64_Internal_RegInfo s;
15121 s.ri_gprmask = mips_gprmask;
15123 s.ri_cprmask[0] = mips_cprmask[0];
15124 s.ri_cprmask[1] = mips_cprmask[1];
15125 s.ri_cprmask[2] = mips_cprmask[2];
15126 s.ri_cprmask[3] = mips_cprmask[3];
15127 /* The gp_value field is set by the MIPS ELF backend. */
15129 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
15130 ((Elf64_External_RegInfo *)
15131 mips_regmask_frag));
15134 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
15135 sort of BFD interface for this. */
15136 if (mips_any_noreorder)
15137 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
15138 if (mips_pic != NO_PIC)
15140 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
15141 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
15144 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
15146 /* Set MIPS ELF flags for ASEs. */
15147 /* We may need to define a new flag for DSP ASE, and set this flag when
15148 file_ase_dsp is true. */
15149 /* Same for DSP R2. */
15150 /* We may need to define a new flag for MT ASE, and set this flag when
15151 file_ase_mt is true. */
15152 if (file_ase_mips16)
15153 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
15154 #if 0 /* XXX FIXME */
15155 if (file_ase_mips3d)
15156 elf_elfheader (stdoutput)->e_flags |= ???;
15159 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
15161 /* Set the MIPS ELF ABI flags. */
15162 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
15163 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
15164 else if (mips_abi == O64_ABI)
15165 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
15166 else if (mips_abi == EABI_ABI)
15168 if (!file_mips_gp32)
15169 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
15171 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
15173 else if (mips_abi == N32_ABI)
15174 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
15176 /* Nothing to do for N64_ABI. */
15178 if (mips_32bitmode)
15179 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
15181 #if 0 /* XXX FIXME */
15182 /* 32 bit code with 64 bit FP registers. */
15183 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
15184 elf_elfheader (stdoutput)->e_flags |= ???;
15188 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
15190 typedef struct proc {
15192 symbolS *func_end_sym;
15193 unsigned long reg_mask;
15194 unsigned long reg_offset;
15195 unsigned long fpreg_mask;
15196 unsigned long fpreg_offset;
15197 unsigned long frame_offset;
15198 unsigned long frame_reg;
15199 unsigned long pc_reg;
15202 static procS cur_proc;
15203 static procS *cur_proc_ptr;
15204 static int numprocs;
15206 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal
15210 mips_nop_opcode (void)
15212 return seg_info (now_seg)->tc_segment_info_data.mips16;
15215 /* Fill in an rs_align_code fragment. This only needs to do something
15216 for MIPS16 code, where 0 is not a nop. */
15219 mips_handle_align (fragS *fragp)
15222 int bytes, size, excess;
15225 if (fragp->fr_type != rs_align_code)
15228 p = fragp->fr_literal + fragp->fr_fix;
15231 opcode = mips16_nop_insn.insn_opcode;
15236 opcode = nop_insn.insn_opcode;
15240 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
15241 excess = bytes % size;
15244 /* If we're not inserting a whole number of instructions,
15245 pad the end of the fixed part of the frag with zeros. */
15246 memset (p, 0, excess);
15248 fragp->fr_fix += excess;
15251 md_number_to_chars (p, opcode, size);
15252 fragp->fr_var = size;
15256 md_obj_begin (void)
15263 /* Check for premature end, nesting errors, etc. */
15265 as_warn (_("missing .end at end of assembly"));
15274 if (*input_line_pointer == '-')
15276 ++input_line_pointer;
15279 if (!ISDIGIT (*input_line_pointer))
15280 as_bad (_("expected simple number"));
15281 if (input_line_pointer[0] == '0')
15283 if (input_line_pointer[1] == 'x')
15285 input_line_pointer += 2;
15286 while (ISXDIGIT (*input_line_pointer))
15289 val |= hex_value (*input_line_pointer++);
15291 return negative ? -val : val;
15295 ++input_line_pointer;
15296 while (ISDIGIT (*input_line_pointer))
15299 val |= *input_line_pointer++ - '0';
15301 return negative ? -val : val;
15304 if (!ISDIGIT (*input_line_pointer))
15306 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
15307 *input_line_pointer, *input_line_pointer);
15308 as_warn (_("invalid number"));
15311 while (ISDIGIT (*input_line_pointer))
15314 val += *input_line_pointer++ - '0';
15316 return negative ? -val : val;
15319 /* The .file directive; just like the usual .file directive, but there
15320 is an initial number which is the ECOFF file index. In the non-ECOFF
15321 case .file implies DWARF-2. */
15324 s_mips_file (int x ATTRIBUTE_UNUSED)
15326 static int first_file_directive = 0;
15328 if (ECOFF_DEBUGGING)
15337 filename = dwarf2_directive_file (0);
15339 /* Versions of GCC up to 3.1 start files with a ".file"
15340 directive even for stabs output. Make sure that this
15341 ".file" is handled. Note that you need a version of GCC
15342 after 3.1 in order to support DWARF-2 on MIPS. */
15343 if (filename != NULL && ! first_file_directive)
15345 (void) new_logical_line (filename, -1);
15346 s_app_file_string (filename, 0);
15348 first_file_directive = 1;
15352 /* The .loc directive, implying DWARF-2. */
15355 s_mips_loc (int x ATTRIBUTE_UNUSED)
15357 if (!ECOFF_DEBUGGING)
15358 dwarf2_directive_loc (0);
15361 /* The .end directive. */
15364 s_mips_end (int x ATTRIBUTE_UNUSED)
15368 /* Following functions need their own .frame and .cprestore directives. */
15369 mips_frame_reg_valid = 0;
15370 mips_cprestore_valid = 0;
15372 if (!is_end_of_line[(unsigned char) *input_line_pointer])
15375 demand_empty_rest_of_line ();
15380 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
15381 as_warn (_(".end not in text section"));
15385 as_warn (_(".end directive without a preceding .ent directive."));
15386 demand_empty_rest_of_line ();
15392 gas_assert (S_GET_NAME (p));
15393 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
15394 as_warn (_(".end symbol does not match .ent symbol."));
15396 if (debug_type == DEBUG_STABS)
15397 stabs_generate_asm_endfunc (S_GET_NAME (p),
15401 as_warn (_(".end directive missing or unknown symbol"));
15404 /* Create an expression to calculate the size of the function. */
15405 if (p && cur_proc_ptr)
15407 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
15408 expressionS *exp = xmalloc (sizeof (expressionS));
15411 exp->X_op = O_subtract;
15412 exp->X_add_symbol = symbol_temp_new_now ();
15413 exp->X_op_symbol = p;
15414 exp->X_add_number = 0;
15416 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
15419 /* Generate a .pdr section. */
15420 if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr)
15422 segT saved_seg = now_seg;
15423 subsegT saved_subseg = now_subseg;
15427 #ifdef md_flush_pending_output
15428 md_flush_pending_output ();
15431 gas_assert (pdr_seg);
15432 subseg_set (pdr_seg, 0);
15434 /* Write the symbol. */
15435 exp.X_op = O_symbol;
15436 exp.X_add_symbol = p;
15437 exp.X_add_number = 0;
15438 emit_expr (&exp, 4);
15440 fragp = frag_more (7 * 4);
15442 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
15443 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
15444 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
15445 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
15446 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
15447 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
15448 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
15450 subseg_set (saved_seg, saved_subseg);
15452 #endif /* OBJ_ELF */
15454 cur_proc_ptr = NULL;
15457 /* The .aent and .ent directives. */
15460 s_mips_ent (int aent)
15464 symbolP = get_symbol ();
15465 if (*input_line_pointer == ',')
15466 ++input_line_pointer;
15467 SKIP_WHITESPACE ();
15468 if (ISDIGIT (*input_line_pointer)
15469 || *input_line_pointer == '-')
15472 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
15473 as_warn (_(".ent or .aent not in text section."));
15475 if (!aent && cur_proc_ptr)
15476 as_warn (_("missing .end"));
15480 /* This function needs its own .frame and .cprestore directives. */
15481 mips_frame_reg_valid = 0;
15482 mips_cprestore_valid = 0;
15484 cur_proc_ptr = &cur_proc;
15485 memset (cur_proc_ptr, '\0', sizeof (procS));
15487 cur_proc_ptr->func_sym = symbolP;
15491 if (debug_type == DEBUG_STABS)
15492 stabs_generate_asm_func (S_GET_NAME (symbolP),
15493 S_GET_NAME (symbolP));
15496 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
15498 demand_empty_rest_of_line ();
15501 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
15502 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
15503 s_mips_frame is used so that we can set the PDR information correctly.
15504 We can't use the ecoff routines because they make reference to the ecoff
15505 symbol table (in the mdebug section). */
15508 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
15511 if (IS_ELF && !ECOFF_DEBUGGING)
15515 if (cur_proc_ptr == (procS *) NULL)
15517 as_warn (_(".frame outside of .ent"));
15518 demand_empty_rest_of_line ();
15522 cur_proc_ptr->frame_reg = tc_get_register (1);
15524 SKIP_WHITESPACE ();
15525 if (*input_line_pointer++ != ','
15526 || get_absolute_expression_and_terminator (&val) != ',')
15528 as_warn (_("Bad .frame directive"));
15529 --input_line_pointer;
15530 demand_empty_rest_of_line ();
15534 cur_proc_ptr->frame_offset = val;
15535 cur_proc_ptr->pc_reg = tc_get_register (0);
15537 demand_empty_rest_of_line ();
15540 #endif /* OBJ_ELF */
15544 /* The .fmask and .mask directives. If the mdebug section is present
15545 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
15546 embedded targets, s_mips_mask is used so that we can set the PDR
15547 information correctly. We can't use the ecoff routines because they
15548 make reference to the ecoff symbol table (in the mdebug section). */
15551 s_mips_mask (int reg_type)
15554 if (IS_ELF && !ECOFF_DEBUGGING)
15558 if (cur_proc_ptr == (procS *) NULL)
15560 as_warn (_(".mask/.fmask outside of .ent"));
15561 demand_empty_rest_of_line ();
15565 if (get_absolute_expression_and_terminator (&mask) != ',')
15567 as_warn (_("Bad .mask/.fmask directive"));
15568 --input_line_pointer;
15569 demand_empty_rest_of_line ();
15573 off = get_absolute_expression ();
15575 if (reg_type == 'F')
15577 cur_proc_ptr->fpreg_mask = mask;
15578 cur_proc_ptr->fpreg_offset = off;
15582 cur_proc_ptr->reg_mask = mask;
15583 cur_proc_ptr->reg_offset = off;
15586 demand_empty_rest_of_line ();
15589 #endif /* OBJ_ELF */
15590 s_ignore (reg_type);
15593 /* A table describing all the processors gas knows about. Names are
15594 matched in the order listed.
15596 To ease comparison, please keep this table in the same order as
15597 gcc's mips_cpu_info_table[]. */
15598 static const struct mips_cpu_info mips_cpu_info_table[] =
15600 /* Entries for generic ISAs */
15601 { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 },
15602 { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 },
15603 { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 },
15604 { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 },
15605 { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 },
15606 { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 },
15607 { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 },
15608 { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
15609 { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
15612 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
15613 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
15614 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
15617 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
15620 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
15621 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
15622 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
15623 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
15624 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
15625 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
15626 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
15627 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
15628 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
15629 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
15630 { "orion", 0, ISA_MIPS3, CPU_R4600 },
15631 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
15632 /* ST Microelectronics Loongson 2E and 2F cores */
15633 { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E },
15634 { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F },
15637 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
15638 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
15639 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
15640 { "r14000", 0, ISA_MIPS4, CPU_R14000 },
15641 { "r16000", 0, ISA_MIPS4, CPU_R16000 },
15642 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
15643 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
15644 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
15645 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
15646 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
15647 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
15648 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
15649 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
15650 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
15651 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
15654 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
15655 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
15656 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
15657 { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
15659 /* MIPS 32 Release 2 */
15660 { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15661 { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15662 { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15663 { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
15664 { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15665 { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15666 { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15667 { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15668 { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15669 { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15670 /* Deprecated forms of the above. */
15671 { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15672 { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15673 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
15674 { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15675 { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15676 { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15677 { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15678 /* Deprecated forms of the above. */
15679 { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15680 { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15681 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
15682 { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15683 ISA_MIPS32R2, CPU_MIPS32R2 },
15684 { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15685 ISA_MIPS32R2, CPU_MIPS32R2 },
15686 { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15687 ISA_MIPS32R2, CPU_MIPS32R2 },
15688 { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15689 ISA_MIPS32R2, CPU_MIPS32R2 },
15690 /* Deprecated forms of the above. */
15691 { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15692 ISA_MIPS32R2, CPU_MIPS32R2 },
15693 { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15694 ISA_MIPS32R2, CPU_MIPS32R2 },
15695 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
15696 { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15697 ISA_MIPS32R2, CPU_MIPS32R2 },
15698 { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15699 ISA_MIPS32R2, CPU_MIPS32R2 },
15700 { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15701 ISA_MIPS32R2, CPU_MIPS32R2 },
15702 { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15703 ISA_MIPS32R2, CPU_MIPS32R2 },
15704 { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15705 ISA_MIPS32R2, CPU_MIPS32R2 },
15706 /* Deprecated forms of the above. */
15707 { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15708 ISA_MIPS32R2, CPU_MIPS32R2 },
15709 { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15710 ISA_MIPS32R2, CPU_MIPS32R2 },
15711 /* 1004K cores are multiprocessor versions of the 34K. */
15712 { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15713 ISA_MIPS32R2, CPU_MIPS32R2 },
15714 { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15715 ISA_MIPS32R2, CPU_MIPS32R2 },
15716 { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15717 ISA_MIPS32R2, CPU_MIPS32R2 },
15718 { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15719 ISA_MIPS32R2, CPU_MIPS32R2 },
15722 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
15723 { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
15724 { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
15725 { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
15727 /* Broadcom SB-1 CPU core */
15728 { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
15729 ISA_MIPS64, CPU_SB1 },
15730 /* Broadcom SB-1A CPU core */
15731 { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
15732 ISA_MIPS64, CPU_SB1 },
15734 { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A },
15736 /* MIPS 64 Release 2 */
15738 /* Cavium Networks Octeon CPU core */
15739 { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
15742 { "xlr", 0, ISA_MIPS64, CPU_XLR },
15749 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
15750 with a final "000" replaced by "k". Ignore case.
15752 Note: this function is shared between GCC and GAS. */
15755 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
15757 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
15758 given++, canonical++;
15760 return ((*given == 0 && *canonical == 0)
15761 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
15765 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
15766 CPU name. We've traditionally allowed a lot of variation here.
15768 Note: this function is shared between GCC and GAS. */
15771 mips_matching_cpu_name_p (const char *canonical, const char *given)
15773 /* First see if the name matches exactly, or with a final "000"
15774 turned into "k". */
15775 if (mips_strict_matching_cpu_name_p (canonical, given))
15778 /* If not, try comparing based on numerical designation alone.
15779 See if GIVEN is an unadorned number, or 'r' followed by a number. */
15780 if (TOLOWER (*given) == 'r')
15782 if (!ISDIGIT (*given))
15785 /* Skip over some well-known prefixes in the canonical name,
15786 hoping to find a number there too. */
15787 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
15789 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
15791 else if (TOLOWER (canonical[0]) == 'r')
15794 return mips_strict_matching_cpu_name_p (canonical, given);
15798 /* Parse an option that takes the name of a processor as its argument.
15799 OPTION is the name of the option and CPU_STRING is the argument.
15800 Return the corresponding processor enumeration if the CPU_STRING is
15801 recognized, otherwise report an error and return null.
15803 A similar function exists in GCC. */
15805 static const struct mips_cpu_info *
15806 mips_parse_cpu (const char *option, const char *cpu_string)
15808 const struct mips_cpu_info *p;
15810 /* 'from-abi' selects the most compatible architecture for the given
15811 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
15812 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15813 version. Look first at the -mgp options, if given, otherwise base
15814 the choice on MIPS_DEFAULT_64BIT.
15816 Treat NO_ABI like the EABIs. One reason to do this is that the
15817 plain 'mips' and 'mips64' configs have 'from-abi' as their default
15818 architecture. This code picks MIPS I for 'mips' and MIPS III for
15819 'mips64', just as we did in the days before 'from-abi'. */
15820 if (strcasecmp (cpu_string, "from-abi") == 0)
15822 if (ABI_NEEDS_32BIT_REGS (mips_abi))
15823 return mips_cpu_info_from_isa (ISA_MIPS1);
15825 if (ABI_NEEDS_64BIT_REGS (mips_abi))
15826 return mips_cpu_info_from_isa (ISA_MIPS3);
15828 if (file_mips_gp32 >= 0)
15829 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
15831 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
15836 /* 'default' has traditionally been a no-op. Probably not very useful. */
15837 if (strcasecmp (cpu_string, "default") == 0)
15840 for (p = mips_cpu_info_table; p->name != 0; p++)
15841 if (mips_matching_cpu_name_p (p->name, cpu_string))
15844 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
15848 /* Return the canonical processor information for ISA (a member of the
15849 ISA_MIPS* enumeration). */
15851 static const struct mips_cpu_info *
15852 mips_cpu_info_from_isa (int isa)
15856 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15857 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
15858 && isa == mips_cpu_info_table[i].isa)
15859 return (&mips_cpu_info_table[i]);
15864 static const struct mips_cpu_info *
15865 mips_cpu_info_from_arch (int arch)
15869 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15870 if (arch == mips_cpu_info_table[i].cpu)
15871 return (&mips_cpu_info_table[i]);
15877 show (FILE *stream, const char *string, int *col_p, int *first_p)
15881 fprintf (stream, "%24s", "");
15886 fprintf (stream, ", ");
15890 if (*col_p + strlen (string) > 72)
15892 fprintf (stream, "\n%24s", "");
15896 fprintf (stream, "%s", string);
15897 *col_p += strlen (string);
15903 md_show_usage (FILE *stream)
15908 fprintf (stream, _("\
15910 -EB generate big endian output\n\
15911 -EL generate little endian output\n\
15912 -g, -g2 do not remove unneeded NOPs or swap branches\n\
15913 -G NUM allow referencing objects up to NUM bytes\n\
15914 implicitly with the gp register [default 8]\n"));
15915 fprintf (stream, _("\
15916 -mips1 generate MIPS ISA I instructions\n\
15917 -mips2 generate MIPS ISA II instructions\n\
15918 -mips3 generate MIPS ISA III instructions\n\
15919 -mips4 generate MIPS ISA IV instructions\n\
15920 -mips5 generate MIPS ISA V instructions\n\
15921 -mips32 generate MIPS32 ISA instructions\n\
15922 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
15923 -mips64 generate MIPS64 ISA instructions\n\
15924 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
15925 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
15929 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15930 show (stream, mips_cpu_info_table[i].name, &column, &first);
15931 show (stream, "from-abi", &column, &first);
15932 fputc ('\n', stream);
15934 fprintf (stream, _("\
15935 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
15936 -no-mCPU don't generate code specific to CPU.\n\
15937 For -mCPU and -no-mCPU, CPU must be one of:\n"));
15941 show (stream, "3900", &column, &first);
15942 show (stream, "4010", &column, &first);
15943 show (stream, "4100", &column, &first);
15944 show (stream, "4650", &column, &first);
15945 fputc ('\n', stream);
15947 fprintf (stream, _("\
15948 -mips16 generate mips16 instructions\n\
15949 -no-mips16 do not generate mips16 instructions\n"));
15950 fprintf (stream, _("\
15951 -msmartmips generate smartmips instructions\n\
15952 -mno-smartmips do not generate smartmips instructions\n"));
15953 fprintf (stream, _("\
15954 -mdsp generate DSP instructions\n\
15955 -mno-dsp do not generate DSP instructions\n"));
15956 fprintf (stream, _("\
15957 -mdspr2 generate DSP R2 instructions\n\
15958 -mno-dspr2 do not generate DSP R2 instructions\n"));
15959 fprintf (stream, _("\
15960 -mmt generate MT instructions\n\
15961 -mno-mt do not generate MT instructions\n"));
15962 fprintf (stream, _("\
15963 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
15964 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
15965 -mfix-vr4120 work around certain VR4120 errata\n\
15966 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
15967 -mfix-24k insert a nop after ERET and DERET instructions\n\
15968 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
15969 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
15970 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
15971 -msym32 assume all symbols have 32-bit values\n\
15972 -O0 remove unneeded NOPs, do not swap branches\n\
15973 -O remove unneeded NOPs and swap branches\n\
15974 --trap, --no-break trap exception on div by 0 and mult overflow\n\
15975 --break, --no-trap break exception on div by 0 and mult overflow\n"));
15976 fprintf (stream, _("\
15977 -mhard-float allow floating-point instructions\n\
15978 -msoft-float do not allow floating-point instructions\n\
15979 -msingle-float only allow 32-bit floating-point operations\n\
15980 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
15981 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
15984 fprintf (stream, _("\
15985 -KPIC, -call_shared generate SVR4 position independent code\n\
15986 -call_nonpic generate non-PIC code that can operate with DSOs\n\
15987 -mvxworks-pic generate VxWorks position independent code\n\
15988 -non_shared do not generate code that can operate with DSOs\n\
15989 -xgot assume a 32 bit GOT\n\
15990 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
15991 -mshared, -mno-shared disable/enable .cpload optimization for\n\
15992 position dependent (non shared) code\n\
15993 -mabi=ABI create ABI conformant object file for:\n"));
15997 show (stream, "32", &column, &first);
15998 show (stream, "o64", &column, &first);
15999 show (stream, "n32", &column, &first);
16000 show (stream, "64", &column, &first);
16001 show (stream, "eabi", &column, &first);
16003 fputc ('\n', stream);
16005 fprintf (stream, _("\
16006 -32 create o32 ABI object file (default)\n\
16007 -n32 create n32 ABI object file\n\
16008 -64 create 64 ABI object file\n"));
16014 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
16016 if (HAVE_64BIT_SYMBOLS)
16017 return dwarf2_format_64bit_irix;
16019 return dwarf2_format_32bit;
16024 mips_dwarf2_addr_size (void)
16026 if (HAVE_64BIT_OBJECTS)
16032 /* Standard calling conventions leave the CFA at SP on entry. */
16034 mips_cfi_frame_initial_instructions (void)
16036 cfi_add_CFA_def_cfa_register (SP);
16040 tc_mips_regname_to_dw2regnum (char *regname)
16042 unsigned int regnum = -1;
16045 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))