1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR; }
51 #undef OBJ_PROCESS_STAB
58 #undef obj_frob_file_after_relocs
59 #undef obj_frob_symbol
61 #undef obj_sec_sym_ok_for_reloc
62 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
65 /* Fix any of them that we actually care about. */
67 #define OUTPUT_FLAVOR mips_output_flavor()
74 #ifndef ECOFF_DEBUGGING
75 #define NO_ECOFF_DEBUGGING
76 #define ECOFF_DEBUGGING 0
81 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
82 static char *mips_regmask_frag;
88 #define PIC_CALL_REG 25
96 #define ILLEGAL_REG (32)
98 /* Allow override of standard little-endian ECOFF format. */
100 #ifndef ECOFF_LITTLE_FORMAT
101 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
104 extern int target_big_endian;
106 /* The name of the readonly data section. */
107 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
109 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
111 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
113 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
117 /* The ABI to use. */
128 /* MIPS ABI we are using for this output file. */
129 static enum mips_abi_level file_mips_abi = NO_ABI;
131 /* This is the set of options which may be modified by the .set
132 pseudo-op. We use a struct so that .set push and .set pop are more
135 struct mips_set_options
137 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
138 if it has not been initialized. Changed by `.set mipsN', and the
139 -mipsN command line option, and the default CPU. */
141 /* Enabled Application Specific Extensions (ASEs). These are set to -1
142 if they have not been initialized. Changed by `.set <asename>', by
143 command line options, and based on the default architecture. */
146 /* Whether we are assembling for the mips16 processor. 0 if we are
147 not, 1 if we are, and -1 if the value has not been initialized.
148 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
149 -nomips16 command line options, and the default CPU. */
151 /* Non-zero if we should not reorder instructions. Changed by `.set
152 reorder' and `.set noreorder'. */
154 /* Non-zero if we should not permit the $at ($1) register to be used
155 in instructions. Changed by `.set at' and `.set noat'. */
157 /* Non-zero if we should warn when a macro instruction expands into
158 more than one machine instruction. Changed by `.set nomacro' and
160 int warn_about_macros;
161 /* Non-zero if we should not move instructions. Changed by `.set
162 move', `.set volatile', `.set nomove', and `.set novolatile'. */
164 /* Non-zero if we should not optimize branches by moving the target
165 of the branch into the delay slot. Actually, we don't perform
166 this optimization anyhow. Changed by `.set bopt' and `.set
169 /* Non-zero if we should not autoextend mips16 instructions.
170 Changed by `.set autoextend' and `.set noautoextend'. */
172 /* Restrict general purpose registers and floating point registers
173 to 32 bit. This is initially determined when -mgp32 or -mfp32
174 is passed but can changed if the assembler code uses .set mipsN. */
177 /* The ABI currently in use. This is changed by .set mipsN to loosen
178 restrictions and doesn't affect the whole file. */
179 enum mips_abi_level abi;
182 /* True if -mgp32 was passed. */
183 static int file_mips_gp32 = -1;
185 /* True if -mfp32 was passed. */
186 static int file_mips_fp32 = -1;
188 /* This is the struct we use to hold the current set of options. Note
189 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
190 -1 to indicate that they have not been initialized. */
192 static struct mips_set_options mips_opts =
194 ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, NO_ABI
197 /* These variables are filled in with the masks of registers used.
198 The object format code reads them and puts them in the appropriate
200 unsigned long mips_gprmask;
201 unsigned long mips_cprmask[4];
203 /* MIPS ISA we are using for this output file. */
204 static int file_mips_isa = ISA_UNKNOWN;
206 /* True if -mips16 was passed or implied by arguments passed on the
207 command line (e.g., by -march). */
208 static int file_ase_mips16;
210 /* True if -mips3d was passed or implied by arguments passed on the
211 command line (e.g., by -march). */
212 static int file_ase_mips3d;
214 /* True if -mdmx was passed or implied by arguments passed on the
215 command line (e.g., by -march). */
216 static int file_ase_mdmx;
218 /* The argument of the -mcpu= flag. Historical for code generation. */
219 static int mips_cpu = CPU_UNKNOWN;
221 /* The argument of the -march= flag. The architecture we are assembling. */
222 static int mips_arch = CPU_UNKNOWN;
224 /* The argument of the -mtune= flag. The architecture for which we
226 static int mips_tune = CPU_UNKNOWN;
228 /* If they asked for mips1 or mips2 and a cpu that is
229 mips3 or greater, then mark the object file 32BITMODE. */
230 static int mips_32bitmode = 0;
232 /* Some ISA's have delay slots for instructions which read or write
233 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
234 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
235 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
236 delay slot in this ISA. The uses of this macro assume that any
237 ISA that has delay slots for one of these, has them for all. They
238 also assume that ISAs which don't have delays for these insns, don't
239 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
240 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
242 || (ISA) == ISA_MIPS2 \
243 || (ISA) == ISA_MIPS3 \
246 /* Return true if ISA supports 64 bit gp register instructions. */
247 #define ISA_HAS_64BIT_REGS(ISA) ( \
249 || (ISA) == ISA_MIPS4 \
250 || (ISA) == ISA_MIPS5 \
251 || (ISA) == ISA_MIPS64 \
254 #define HAVE_32BIT_GPRS \
256 || mips_opts.abi == O32_ABI \
257 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
259 #define HAVE_32BIT_FPRS \
261 || mips_opts.abi == O32_ABI \
262 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
264 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
265 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
267 #define HAVE_NEWABI (mips_opts.abi == N32_ABI || mips_opts.abi == N64_ABI)
269 #define HAVE_64BIT_OBJECTS (mips_opts.abi == N64_ABI)
271 /* We can only have 64bit addresses if the object file format
273 #define HAVE_32BIT_ADDRESSES \
275 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
276 || ! HAVE_64BIT_OBJECTS) \
277 && mips_pic != EMBEDDED_PIC))
279 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
281 /* Return true if the given CPU supports the MIPS16 ASE. */
282 #define CPU_HAS_MIPS16(cpu) \
283 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0)
285 /* Return true if the given CPU supports the MIPS3D ASE. */
286 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
289 /* Return true if the given CPU supports the MDMX ASE. */
290 #define CPU_HAS_MDMX(cpu) (false \
293 /* Whether the processor uses hardware interlocks to protect
294 reads from the HI and LO registers, and thus does not
295 require nops to be inserted. */
297 #define hilo_interlocks (mips_arch == CPU_R4010 \
298 || mips_arch == CPU_SB1 \
301 /* Whether the processor uses hardware interlocks to protect reads
302 from the GPRs, and thus does not require nops to be inserted. */
303 #define gpr_interlocks \
304 (mips_opts.isa != ISA_MIPS1 \
305 || mips_arch == CPU_R3900)
307 /* As with other "interlocks" this is used by hardware that has FP
308 (co-processor) interlocks. */
309 /* Itbl support may require additional care here. */
310 #define cop_interlocks (mips_arch == CPU_R4300 \
311 || mips_arch == CPU_SB1 \
314 /* Is this a mfhi or mflo instruction? */
315 #define MF_HILO_INSN(PINFO) \
316 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
318 /* MIPS PIC level. */
322 /* Do not generate PIC code. */
325 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
326 not sure what it is supposed to do. */
329 /* Generate PIC code as in the SVR4 MIPS ABI. */
332 /* Generate PIC code without using a global offset table: the data
333 segment has a maximum size of 64K, all data references are off
334 the $gp register, and all text references are PC relative. This
335 is used on some embedded systems. */
339 static enum mips_pic_level mips_pic;
341 /* Warn about all NOPS that the assembler generates. */
342 static int warn_nops = 0;
344 /* 1 if we should generate 32 bit offsets from the $gp register in
345 SVR4_PIC mode. Currently has no meaning in other modes. */
346 static int mips_big_got = 0;
348 /* 1 if trap instructions should used for overflow rather than break
350 static int mips_trap = 0;
352 /* 1 if double width floating point constants should not be constructed
353 by assembling two single width halves into two single width floating
354 point registers which just happen to alias the double width destination
355 register. On some architectures this aliasing can be disabled by a bit
356 in the status register, and the setting of this bit cannot be determined
357 automatically at assemble time. */
358 static int mips_disable_float_construction;
360 /* Non-zero if any .set noreorder directives were used. */
362 static int mips_any_noreorder;
364 /* Non-zero if nops should be inserted when the register referenced in
365 an mfhi/mflo instruction is read in the next two instructions. */
366 static int mips_7000_hilo_fix;
368 /* The size of the small data section. */
369 static unsigned int g_switch_value = 8;
370 /* Whether the -G option was used. */
371 static int g_switch_seen = 0;
376 /* If we can determine in advance that GP optimization won't be
377 possible, we can skip the relaxation stuff that tries to produce
378 GP-relative references. This makes delay slot optimization work
381 This function can only provide a guess, but it seems to work for
382 gcc output. It needs to guess right for gcc, otherwise gcc
383 will put what it thinks is a GP-relative instruction in a branch
386 I don't know if a fix is needed for the SVR4_PIC mode. I've only
387 fixed it for the non-PIC mode. KR 95/04/07 */
388 static int nopic_need_relax PARAMS ((symbolS *, int));
390 /* handle of the OPCODE hash table */
391 static struct hash_control *op_hash = NULL;
393 /* The opcode hash table we use for the mips16. */
394 static struct hash_control *mips16_op_hash = NULL;
396 /* This array holds the chars that always start a comment. If the
397 pre-processor is disabled, these aren't very useful */
398 const char comment_chars[] = "#";
400 /* This array holds the chars that only start a comment at the beginning of
401 a line. If the line seems to have the form '# 123 filename'
402 .line and .file directives will appear in the pre-processed output */
403 /* Note that input_file.c hand checks for '#' at the beginning of the
404 first line of the input file. This is because the compiler outputs
405 #NO_APP at the beginning of its output. */
406 /* Also note that C style comments are always supported. */
407 const char line_comment_chars[] = "#";
409 /* This array holds machine specific line separator characters. */
410 const char line_separator_chars[] = ";";
412 /* Chars that can be used to separate mant from exp in floating point nums */
413 const char EXP_CHARS[] = "eE";
415 /* Chars that mean this number is a floating point constant */
418 const char FLT_CHARS[] = "rRsSfFdDxXpP";
420 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
421 changed in read.c . Ideally it shouldn't have to know about it at all,
422 but nothing is ideal around here.
425 static char *insn_error;
427 static int auto_align = 1;
429 /* When outputting SVR4 PIC code, the assembler needs to know the
430 offset in the stack frame from which to restore the $gp register.
431 This is set by the .cprestore pseudo-op, and saved in this
433 static offsetT mips_cprestore_offset = -1;
435 /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some
436 more optimizations, it can use a register value instead of a memory-saved
437 offset and even an other register than $gp as global pointer. */
438 static offsetT mips_cpreturn_offset = -1;
439 static int mips_cpreturn_register = -1;
440 static int mips_gp_register = GP;
441 static int mips_gprel_offset = 0;
443 /* Whether mips_cprestore_offset has been set in the current function
444 (or whether it has already been warned about, if not). */
445 static int mips_cprestore_valid = 0;
447 /* This is the register which holds the stack frame, as set by the
448 .frame pseudo-op. This is needed to implement .cprestore. */
449 static int mips_frame_reg = SP;
451 /* Whether mips_frame_reg has been set in the current function
452 (or whether it has already been warned about, if not). */
453 static int mips_frame_reg_valid = 0;
455 /* To output NOP instructions correctly, we need to keep information
456 about the previous two instructions. */
458 /* Whether we are optimizing. The default value of 2 means to remove
459 unneeded NOPs and swap branch instructions when possible. A value
460 of 1 means to not swap branches. A value of 0 means to always
462 static int mips_optimize = 2;
464 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
465 equivalent to seeing no -g option at all. */
466 static int mips_debug = 0;
468 /* The previous instruction. */
469 static struct mips_cl_insn prev_insn;
471 /* The instruction before prev_insn. */
472 static struct mips_cl_insn prev_prev_insn;
474 /* If we don't want information for prev_insn or prev_prev_insn, we
475 point the insn_mo field at this dummy integer. */
476 static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 };
478 /* Non-zero if prev_insn is valid. */
479 static int prev_insn_valid;
481 /* The frag for the previous instruction. */
482 static struct frag *prev_insn_frag;
484 /* The offset into prev_insn_frag for the previous instruction. */
485 static long prev_insn_where;
487 /* The reloc type for the previous instruction, if any. */
488 static bfd_reloc_code_real_type prev_insn_reloc_type[3];
490 /* The reloc for the previous instruction, if any. */
491 static fixS *prev_insn_fixp[3];
493 /* Non-zero if the previous instruction was in a delay slot. */
494 static int prev_insn_is_delay_slot;
496 /* Non-zero if the previous instruction was in a .set noreorder. */
497 static int prev_insn_unreordered;
499 /* Non-zero if the previous instruction uses an extend opcode (if
501 static int prev_insn_extended;
503 /* Non-zero if the previous previous instruction was in a .set
505 static int prev_prev_insn_unreordered;
507 /* If this is set, it points to a frag holding nop instructions which
508 were inserted before the start of a noreorder section. If those
509 nops turn out to be unnecessary, the size of the frag can be
511 static fragS *prev_nop_frag;
513 /* The number of nop instructions we created in prev_nop_frag. */
514 static int prev_nop_frag_holds;
516 /* The number of nop instructions that we know we need in
518 static int prev_nop_frag_required;
520 /* The number of instructions we've seen since prev_nop_frag. */
521 static int prev_nop_frag_since;
523 /* For ECOFF and ELF, relocations against symbols are done in two
524 parts, with a HI relocation and a LO relocation. Each relocation
525 has only 16 bits of space to store an addend. This means that in
526 order for the linker to handle carries correctly, it must be able
527 to locate both the HI and the LO relocation. This means that the
528 relocations must appear in order in the relocation table.
530 In order to implement this, we keep track of each unmatched HI
531 relocation. We then sort them so that they immediately precede the
532 corresponding LO relocation. */
537 struct mips_hi_fixup *next;
540 /* The section this fixup is in. */
544 /* The list of unmatched HI relocs. */
546 static struct mips_hi_fixup *mips_hi_fixup_list;
548 /* Map normal MIPS register numbers to mips16 register numbers. */
550 #define X ILLEGAL_REG
551 static const int mips32_to_16_reg_map[] =
553 X, X, 2, 3, 4, 5, 6, 7,
554 X, X, X, X, X, X, X, X,
555 0, 1, X, X, X, X, X, X,
556 X, X, X, X, X, X, X, X
560 /* Map mips16 register numbers to normal MIPS register numbers. */
562 static const unsigned int mips16_to_32_reg_map[] =
564 16, 17, 2, 3, 4, 5, 6, 7
567 /* Since the MIPS does not have multiple forms of PC relative
568 instructions, we do not have to do relaxing as is done on other
569 platforms. However, we do have to handle GP relative addressing
570 correctly, which turns out to be a similar problem.
572 Every macro that refers to a symbol can occur in (at least) two
573 forms, one with GP relative addressing and one without. For
574 example, loading a global variable into a register generally uses
575 a macro instruction like this:
577 If i can be addressed off the GP register (this is true if it is in
578 the .sbss or .sdata section, or if it is known to be smaller than
579 the -G argument) this will generate the following instruction:
581 This instruction will use a GPREL reloc. If i can not be addressed
582 off the GP register, the following instruction sequence will be used:
585 In this case the first instruction will have a HI16 reloc, and the
586 second reloc will have a LO16 reloc. Both relocs will be against
589 The issue here is that we may not know whether i is GP addressable
590 until after we see the instruction that uses it. Therefore, we
591 want to be able to choose the final instruction sequence only at
592 the end of the assembly. This is similar to the way other
593 platforms choose the size of a PC relative instruction only at the
596 When generating position independent code we do not use GP
597 addressing in quite the same way, but the issue still arises as
598 external symbols and local symbols must be handled differently.
600 We handle these issues by actually generating both possible
601 instruction sequences. The longer one is put in a frag_var with
602 type rs_machine_dependent. We encode what to do with the frag in
603 the subtype field. We encode (1) the number of existing bytes to
604 replace, (2) the number of new bytes to use, (3) the offset from
605 the start of the existing bytes to the first reloc we must generate
606 (that is, the offset is applied from the start of the existing
607 bytes after they are replaced by the new bytes, if any), (4) the
608 offset from the start of the existing bytes to the second reloc,
609 (5) whether a third reloc is needed (the third reloc is always four
610 bytes after the second reloc), and (6) whether to warn if this
611 variant is used (this is sometimes needed if .set nomacro or .set
612 noat is in effect). All these numbers are reasonably small.
614 Generating two instruction sequences must be handled carefully to
615 ensure that delay slots are handled correctly. Fortunately, there
616 are a limited number of cases. When the second instruction
617 sequence is generated, append_insn is directed to maintain the
618 existing delay slot information, so it continues to apply to any
619 code after the second instruction sequence. This means that the
620 second instruction sequence must not impose any requirements not
621 required by the first instruction sequence.
623 These variant frags are then handled in functions called by the
624 machine independent code. md_estimate_size_before_relax returns
625 the final size of the frag. md_convert_frag sets up the final form
626 of the frag. tc_gen_reloc adjust the first reloc and adds a second
628 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
632 | (((reloc1) + 64) << 9) \
633 | (((reloc2) + 64) << 2) \
634 | ((reloc3) ? (1 << 1) : 0) \
636 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
637 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
638 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
639 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
640 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
641 #define RELAX_WARN(i) ((i) & 1)
643 /* For mips16 code, we use an entirely different form of relaxation.
644 mips16 supports two versions of most instructions which take
645 immediate values: a small one which takes some small value, and a
646 larger one which takes a 16 bit value. Since branches also follow
647 this pattern, relaxing these values is required.
649 We can assemble both mips16 and normal MIPS code in a single
650 object. Therefore, we need to support this type of relaxation at
651 the same time that we support the relaxation described above. We
652 use the high bit of the subtype field to distinguish these cases.
654 The information we store for this type of relaxation is the
655 argument code found in the opcode file for this relocation, whether
656 the user explicitly requested a small or extended form, and whether
657 the relocation is in a jump or jal delay slot. That tells us the
658 size of the value, and how it should be stored. We also store
659 whether the fragment is considered to be extended or not. We also
660 store whether this is known to be a branch to a different section,
661 whether we have tried to relax this frag yet, and whether we have
662 ever extended a PC relative fragment because of a shift count. */
663 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
666 | ((small) ? 0x100 : 0) \
667 | ((ext) ? 0x200 : 0) \
668 | ((dslot) ? 0x400 : 0) \
669 | ((jal_dslot) ? 0x800 : 0))
670 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
671 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
672 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
673 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
674 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
675 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
676 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
677 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
678 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
679 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
680 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
681 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
683 /* Prototypes for static functions. */
686 #define internalError() \
687 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
689 #define internalError() as_fatal (_("MIPS internal Error"));
692 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
694 static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip,
695 unsigned int reg, enum mips_regclass class));
696 static int reg_needs_delay PARAMS ((unsigned int));
697 static void mips16_mark_labels PARAMS ((void));
698 static void append_insn PARAMS ((char *place,
699 struct mips_cl_insn * ip,
701 bfd_reloc_code_real_type *r,
703 static void mips_no_prev_insn PARAMS ((int));
704 static void mips_emit_delays PARAMS ((boolean));
706 static void macro_build PARAMS ((char *place, int *counter, expressionS * ep,
707 const char *name, const char *fmt,
710 static void macro_build ();
712 static void mips16_macro_build PARAMS ((char *, int *, expressionS *,
713 const char *, const char *,
715 static void macro_build_jalr PARAMS ((int, expressionS *));
716 static void macro_build_lui PARAMS ((char *place, int *counter,
717 expressionS * ep, int regnum));
718 static void set_at PARAMS ((int *counter, int reg, int unsignedp));
719 static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip,
721 static void load_register PARAMS ((int *, int, expressionS *, int));
722 static void load_address PARAMS ((int *, int, expressionS *, int *));
723 static void move_register PARAMS ((int *, int, int));
724 static void macro PARAMS ((struct mips_cl_insn * ip));
725 static void mips16_macro PARAMS ((struct mips_cl_insn * ip));
726 #ifdef LOSING_COMPILER
727 static void macro2 PARAMS ((struct mips_cl_insn * ip));
729 static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip));
730 static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip));
731 static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean,
732 boolean, boolean, unsigned long *,
733 boolean *, unsigned short *));
734 static int my_getPercentOp PARAMS ((char **, unsigned int *, int *));
735 static int my_getSmallParser PARAMS ((char **, unsigned int *, int *));
736 static int my_getSmallExpression PARAMS ((expressionS *, char *));
737 static void my_getExpression PARAMS ((expressionS *, char *));
739 static int support_64bit_objects PARAMS((void));
741 static symbolS *get_symbol PARAMS ((void));
742 static void mips_align PARAMS ((int to, int fill, symbolS *label));
743 static void s_align PARAMS ((int));
744 static void s_change_sec PARAMS ((int));
745 static void s_cons PARAMS ((int));
746 static void s_float_cons PARAMS ((int));
747 static void s_mips_globl PARAMS ((int));
748 static void s_option PARAMS ((int));
749 static void s_mipsset PARAMS ((int));
750 static void s_abicalls PARAMS ((int));
751 static void s_cpload PARAMS ((int));
752 static void s_cpsetup PARAMS ((int));
753 static void s_cplocal PARAMS ((int));
754 static void s_cprestore PARAMS ((int));
755 static void s_cpreturn PARAMS ((int));
756 static void s_gpvalue PARAMS ((int));
757 static void s_gpword PARAMS ((int));
758 static void s_cpadd PARAMS ((int));
759 static void s_insn PARAMS ((int));
760 static void md_obj_begin PARAMS ((void));
761 static void md_obj_end PARAMS ((void));
762 static long get_number PARAMS ((void));
763 static void s_mips_ent PARAMS ((int));
764 static void s_mips_end PARAMS ((int));
765 static void s_mips_frame PARAMS ((int));
766 static void s_mips_mask PARAMS ((int));
767 static void s_mips_stab PARAMS ((int));
768 static void s_mips_weakext PARAMS ((int));
769 static void s_file PARAMS ((int));
770 static int mips16_extended_frag PARAMS ((fragS *, asection *, long));
771 static const char *mips_isa_to_str PARAMS ((int));
772 static const char *mips_cpu_to_str PARAMS ((int));
773 static int validate_mips_insn PARAMS ((const struct mips_opcode *));
774 static void show PARAMS ((FILE *, char *, int *, int *));
776 static int mips_need_elf_addend_fixup PARAMS ((fixS *));
779 /* Return values of my_getSmallExpression(). */
786 /* Direct relocation creation by %percent_op(). */
805 /* Table and functions used to map between CPU/ISA names, and
806 ISA levels, and CPU numbers. */
810 const char *name; /* CPU or ISA name. */
811 int is_isa; /* Is this an ISA? (If 0, a CPU.) */
812 int isa; /* ISA level. */
813 int cpu; /* CPU number (default CPU if ISA). */
816 static const struct mips_cpu_info *mips_cpu_info_from_name PARAMS ((const char *));
817 static const struct mips_cpu_info *mips_cpu_info_from_isa PARAMS ((int));
818 static const struct mips_cpu_info *mips_cpu_info_from_cpu PARAMS ((int));
822 The following pseudo-ops from the Kane and Heinrich MIPS book
823 should be defined here, but are currently unsupported: .alias,
824 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
826 The following pseudo-ops from the Kane and Heinrich MIPS book are
827 specific to the type of debugging information being generated, and
828 should be defined by the object format: .aent, .begin, .bend,
829 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
832 The following pseudo-ops from the Kane and Heinrich MIPS book are
833 not MIPS CPU specific, but are also not specific to the object file
834 format. This file is probably the best place to define them, but
835 they are not currently supported: .asm0, .endr, .lab, .repeat,
838 static const pseudo_typeS mips_pseudo_table[] =
840 /* MIPS specific pseudo-ops. */
841 {"option", s_option, 0},
842 {"set", s_mipsset, 0},
843 {"rdata", s_change_sec, 'r'},
844 {"sdata", s_change_sec, 's'},
845 {"livereg", s_ignore, 0},
846 {"abicalls", s_abicalls, 0},
847 {"cpload", s_cpload, 0},
848 {"cpsetup", s_cpsetup, 0},
849 {"cplocal", s_cplocal, 0},
850 {"cprestore", s_cprestore, 0},
851 {"cpreturn", s_cpreturn, 0},
852 {"gpvalue", s_gpvalue, 0},
853 {"gpword", s_gpword, 0},
854 {"cpadd", s_cpadd, 0},
857 /* Relatively generic pseudo-ops that happen to be used on MIPS
859 {"asciiz", stringer, 1},
860 {"bss", s_change_sec, 'b'},
863 {"dword", s_cons, 3},
864 {"weakext", s_mips_weakext, 0},
866 /* These pseudo-ops are defined in read.c, but must be overridden
867 here for one reason or another. */
868 {"align", s_align, 0},
870 {"data", s_change_sec, 'd'},
871 {"double", s_float_cons, 'd'},
872 {"float", s_float_cons, 'f'},
873 {"globl", s_mips_globl, 0},
874 {"global", s_mips_globl, 0},
875 {"hword", s_cons, 1},
880 {"short", s_cons, 1},
881 {"single", s_float_cons, 'f'},
882 {"stabn", s_mips_stab, 'n'},
883 {"text", s_change_sec, 't'},
886 #ifdef MIPS_STABS_ELF
887 { "extern", ecoff_directive_extern, 0},
893 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
895 /* These pseudo-ops should be defined by the object file format.
896 However, a.out doesn't support them, so we have versions here. */
897 {"aent", s_mips_ent, 1},
898 {"bgnb", s_ignore, 0},
899 {"end", s_mips_end, 0},
900 {"endb", s_ignore, 0},
901 {"ent", s_mips_ent, 0},
903 {"fmask", s_mips_mask, 'F'},
904 {"frame", s_mips_frame, 0},
905 {"loc", s_ignore, 0},
906 {"mask", s_mips_mask, 'R'},
907 {"verstamp", s_ignore, 0},
911 extern void pop_insert PARAMS ((const pseudo_typeS *));
916 pop_insert (mips_pseudo_table);
917 if (! ECOFF_DEBUGGING)
918 pop_insert (mips_nonecoff_pseudo_table);
921 /* Symbols labelling the current insn. */
923 struct insn_label_list
925 struct insn_label_list *next;
929 static struct insn_label_list *insn_labels;
930 static struct insn_label_list *free_insn_labels;
932 static void mips_clear_insn_labels PARAMS ((void));
935 mips_clear_insn_labels ()
937 register struct insn_label_list **pl;
939 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
945 static char *expr_end;
947 /* Expressions which appear in instructions. These are set by
950 static expressionS imm_expr;
951 static expressionS offset_expr;
953 /* Relocs associated with imm_expr and offset_expr. */
955 static bfd_reloc_code_real_type imm_reloc[3]
956 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
957 static bfd_reloc_code_real_type offset_reloc[3]
958 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
960 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
962 static boolean imm_unmatched_hi;
964 /* These are set by mips16_ip if an explicit extension is used. */
966 static boolean mips16_small, mips16_ext;
968 #ifdef MIPS_STABS_ELF
969 /* The pdr segment for per procedure frame/regmask info */
975 mips_isa_to_str (isa)
978 const struct mips_cpu_info *ci;
981 ci = mips_cpu_info_from_isa (isa);
985 sprintf (s, "ISA#%d", isa);
990 mips_cpu_to_str (cpu)
993 const struct mips_cpu_info *ci;
996 ci = mips_cpu_info_from_cpu (cpu);
1000 sprintf (s, "CPU#%d", cpu);
1004 /* The default target format to use. */
1007 mips_target_format ()
1009 switch (OUTPUT_FLAVOR)
1011 case bfd_target_aout_flavour:
1012 return target_big_endian ? "a.out-mips-big" : "a.out-mips-little";
1013 case bfd_target_ecoff_flavour:
1014 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1015 case bfd_target_coff_flavour:
1017 case bfd_target_elf_flavour:
1019 /* This is traditional mips */
1020 return (target_big_endian
1021 ? (HAVE_64BIT_OBJECTS ? "elf64-tradbigmips"
1022 : "elf32-tradbigmips")
1023 : (HAVE_64BIT_OBJECTS ? "elf64-tradlittlemips"
1024 : "elf32-tradlittlemips"));
1026 return (target_big_endian
1027 ? (HAVE_64BIT_OBJECTS ? "elf64-bigmips" : "elf32-bigmips")
1028 : (HAVE_64BIT_OBJECTS ? "elf64-littlemips"
1029 : "elf32-littlemips"));
1037 /* This function is called once, at assembler startup time. It should
1038 set up all the tables, etc. that the MD part of the assembler will need. */
1043 register const char *retval = NULL;
1047 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_arch))
1048 as_warn (_("Could not set architecture and machine"));
1050 op_hash = hash_new ();
1052 for (i = 0; i < NUMOPCODES;)
1054 const char *name = mips_opcodes[i].name;
1056 retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]);
1059 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1060 mips_opcodes[i].name, retval);
1061 /* Probably a memory allocation problem? Give up now. */
1062 as_fatal (_("Broken assembler. No assembly attempted."));
1066 if (mips_opcodes[i].pinfo != INSN_MACRO)
1068 if (!validate_mips_insn (&mips_opcodes[i]))
1073 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1076 mips16_op_hash = hash_new ();
1079 while (i < bfd_mips16_num_opcodes)
1081 const char *name = mips16_opcodes[i].name;
1083 retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]);
1085 as_fatal (_("internal: can't hash `%s': %s"),
1086 mips16_opcodes[i].name, retval);
1089 if (mips16_opcodes[i].pinfo != INSN_MACRO
1090 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1091 != mips16_opcodes[i].match))
1093 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1094 mips16_opcodes[i].name, mips16_opcodes[i].args);
1099 while (i < bfd_mips16_num_opcodes
1100 && strcmp (mips16_opcodes[i].name, name) == 0);
1104 as_fatal (_("Broken assembler. No assembly attempted."));
1106 /* We add all the general register names to the symbol table. This
1107 helps us detect invalid uses of them. */
1108 for (i = 0; i < 32; i++)
1112 sprintf (buf, "$%d", i);
1113 symbol_table_insert (symbol_new (buf, reg_section, i,
1114 &zero_address_frag));
1116 symbol_table_insert (symbol_new ("$ra", reg_section, RA,
1117 &zero_address_frag));
1118 symbol_table_insert (symbol_new ("$fp", reg_section, FP,
1119 &zero_address_frag));
1120 symbol_table_insert (symbol_new ("$sp", reg_section, SP,
1121 &zero_address_frag));
1122 symbol_table_insert (symbol_new ("$gp", reg_section, GP,
1123 &zero_address_frag));
1124 symbol_table_insert (symbol_new ("$at", reg_section, AT,
1125 &zero_address_frag));
1126 symbol_table_insert (symbol_new ("$kt0", reg_section, KT0,
1127 &zero_address_frag));
1128 symbol_table_insert (symbol_new ("$kt1", reg_section, KT1,
1129 &zero_address_frag));
1130 symbol_table_insert (symbol_new ("$zero", reg_section, ZERO,
1131 &zero_address_frag));
1132 symbol_table_insert (symbol_new ("$pc", reg_section, -1,
1133 &zero_address_frag));
1135 mips_no_prev_insn (false);
1138 mips_cprmask[0] = 0;
1139 mips_cprmask[1] = 0;
1140 mips_cprmask[2] = 0;
1141 mips_cprmask[3] = 0;
1143 /* set the default alignment for the text section (2**2) */
1144 record_alignment (text_section, 2);
1146 if (USE_GLOBAL_POINTER_OPT)
1147 bfd_set_gp_size (stdoutput, g_switch_value);
1149 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1151 /* On a native system, sections must be aligned to 16 byte
1152 boundaries. When configured for an embedded ELF target, we
1154 if (strcmp (TARGET_OS, "elf") != 0)
1156 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
1157 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
1158 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
1161 /* Create a .reginfo section for register masks and a .mdebug
1162 section for debugging information. */
1170 subseg = now_subseg;
1172 /* The ABI says this section should be loaded so that the
1173 running program can access it. However, we don't load it
1174 if we are configured for an embedded target */
1175 flags = SEC_READONLY | SEC_DATA;
1176 if (strcmp (TARGET_OS, "elf") != 0)
1177 flags |= SEC_ALLOC | SEC_LOAD;
1179 if (file_mips_abi != N64_ABI)
1181 sec = subseg_new (".reginfo", (subsegT) 0);
1183 bfd_set_section_flags (stdoutput, sec, flags);
1184 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
1187 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
1192 /* The 64-bit ABI uses a .MIPS.options section rather than
1193 .reginfo section. */
1194 sec = subseg_new (".MIPS.options", (subsegT) 0);
1195 bfd_set_section_flags (stdoutput, sec, flags);
1196 bfd_set_section_alignment (stdoutput, sec, 3);
1199 /* Set up the option header. */
1201 Elf_Internal_Options opthdr;
1204 opthdr.kind = ODK_REGINFO;
1205 opthdr.size = (sizeof (Elf_External_Options)
1206 + sizeof (Elf64_External_RegInfo));
1209 f = frag_more (sizeof (Elf_External_Options));
1210 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
1211 (Elf_External_Options *) f);
1213 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
1218 if (ECOFF_DEBUGGING)
1220 sec = subseg_new (".mdebug", (subsegT) 0);
1221 (void) bfd_set_section_flags (stdoutput, sec,
1222 SEC_HAS_CONTENTS | SEC_READONLY);
1223 (void) bfd_set_section_alignment (stdoutput, sec, 2);
1226 #ifdef MIPS_STABS_ELF
1227 pdr_seg = subseg_new (".pdr", (subsegT) 0);
1228 (void) bfd_set_section_flags (stdoutput, pdr_seg,
1229 SEC_READONLY | SEC_RELOC | SEC_DEBUGGING);
1230 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
1233 subseg_set (seg, subseg);
1237 if (! ECOFF_DEBUGGING)
1244 if (! ECOFF_DEBUGGING)
1252 struct mips_cl_insn insn;
1253 bfd_reloc_code_real_type unused_reloc[3]
1254 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1256 imm_expr.X_op = O_absent;
1257 imm_unmatched_hi = false;
1258 offset_expr.X_op = O_absent;
1259 imm_reloc[0] = BFD_RELOC_UNUSED;
1260 imm_reloc[1] = BFD_RELOC_UNUSED;
1261 imm_reloc[2] = BFD_RELOC_UNUSED;
1262 offset_reloc[0] = BFD_RELOC_UNUSED;
1263 offset_reloc[1] = BFD_RELOC_UNUSED;
1264 offset_reloc[2] = BFD_RELOC_UNUSED;
1266 if (mips_opts.mips16)
1267 mips16_ip (str, &insn);
1270 mips_ip (str, &insn);
1271 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1272 str, insn.insn_opcode));
1277 as_bad ("%s `%s'", insn_error, str);
1281 if (insn.insn_mo->pinfo == INSN_MACRO)
1283 if (mips_opts.mips16)
1284 mips16_macro (&insn);
1290 if (imm_expr.X_op != O_absent)
1291 append_insn (NULL, &insn, &imm_expr, imm_reloc, imm_unmatched_hi);
1292 else if (offset_expr.X_op != O_absent)
1293 append_insn (NULL, &insn, &offset_expr, offset_reloc, false);
1295 append_insn (NULL, &insn, NULL, unused_reloc, false);
1299 /* See whether instruction IP reads register REG. CLASS is the type
1303 insn_uses_reg (ip, reg, class)
1304 struct mips_cl_insn *ip;
1306 enum mips_regclass class;
1308 if (class == MIPS16_REG)
1310 assert (mips_opts.mips16);
1311 reg = mips16_to_32_reg_map[reg];
1312 class = MIPS_GR_REG;
1315 /* Don't report on general register ZERO, since it never changes. */
1316 if (class == MIPS_GR_REG && reg == ZERO)
1319 if (class == MIPS_FP_REG)
1321 assert (! mips_opts.mips16);
1322 /* If we are called with either $f0 or $f1, we must check $f0.
1323 This is not optimal, because it will introduce an unnecessary
1324 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1325 need to distinguish reading both $f0 and $f1 or just one of
1326 them. Note that we don't have to check the other way,
1327 because there is no instruction that sets both $f0 and $f1
1328 and requires a delay. */
1329 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
1330 && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1)
1331 == (reg &~ (unsigned) 1)))
1333 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
1334 && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1)
1335 == (reg &~ (unsigned) 1)))
1338 else if (! mips_opts.mips16)
1340 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
1341 && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg)
1343 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
1344 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg)
1349 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
1350 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX)
1351 & MIPS16OP_MASK_RX)]
1354 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
1355 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY)
1356 & MIPS16OP_MASK_RY)]
1359 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
1360 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
1361 & MIPS16OP_MASK_MOVE32Z)]
1364 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
1366 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
1368 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
1370 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
1371 && ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
1372 & MIPS16OP_MASK_REGR32) == reg)
1379 /* This function returns true if modifying a register requires a
1383 reg_needs_delay (reg)
1386 unsigned long prev_pinfo;
1388 prev_pinfo = prev_insn.insn_mo->pinfo;
1389 if (! mips_opts.noreorder
1390 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1391 && ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1392 || (! gpr_interlocks
1393 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
1395 /* A load from a coprocessor or from memory. All load
1396 delays delay the use of general register rt for one
1397 instruction on the r3000. The r6000 and r4000 use
1399 /* Itbl support may require additional care here. */
1400 know (prev_pinfo & INSN_WRITE_GPR_T);
1401 if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT))
1408 /* Mark instruction labels in mips16 mode. This permits the linker to
1409 handle them specially, such as generating jalx instructions when
1410 needed. We also make them odd for the duration of the assembly, in
1411 order to generate the right sort of code. We will make them even
1412 in the adjust_symtab routine, while leaving them marked. This is
1413 convenient for the debugger and the disassembler. The linker knows
1414 to make them odd again. */
1417 mips16_mark_labels ()
1419 if (mips_opts.mips16)
1421 struct insn_label_list *l;
1424 for (l = insn_labels; l != NULL; l = l->next)
1427 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1428 S_SET_OTHER (l->label, STO_MIPS16);
1430 val = S_GET_VALUE (l->label);
1432 S_SET_VALUE (l->label, val + 1);
1437 /* Output an instruction. PLACE is where to put the instruction; if
1438 it is NULL, this uses frag_more to get room. IP is the instruction
1439 information. ADDRESS_EXPR is an operand of the instruction to be
1440 used with RELOC_TYPE. */
1443 append_insn (place, ip, address_expr, reloc_type, unmatched_hi)
1445 struct mips_cl_insn *ip;
1446 expressionS *address_expr;
1447 bfd_reloc_code_real_type *reloc_type;
1448 boolean unmatched_hi;
1450 register unsigned long prev_pinfo, pinfo;
1455 /* Mark instruction labels in mips16 mode. */
1456 mips16_mark_labels ();
1458 prev_pinfo = prev_insn.insn_mo->pinfo;
1459 pinfo = ip->insn_mo->pinfo;
1461 if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL))
1465 /* If the previous insn required any delay slots, see if we need
1466 to insert a NOP or two. There are eight kinds of possible
1467 hazards, of which an instruction can have at most one type.
1468 (1) a load from memory delay
1469 (2) a load from a coprocessor delay
1470 (3) an unconditional branch delay
1471 (4) a conditional branch delay
1472 (5) a move to coprocessor register delay
1473 (6) a load coprocessor register from memory delay
1474 (7) a coprocessor condition code delay
1475 (8) a HI/LO special register delay
1477 There are a lot of optimizations we could do that we don't.
1478 In particular, we do not, in general, reorder instructions.
1479 If you use gcc with optimization, it will reorder
1480 instructions and generally do much more optimization then we
1481 do here; repeating all that work in the assembler would only
1482 benefit hand written assembly code, and does not seem worth
1485 /* This is how a NOP is emitted. */
1486 #define emit_nop() \
1488 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1489 : md_number_to_chars (frag_more (4), 0, 4))
1491 /* The previous insn might require a delay slot, depending upon
1492 the contents of the current insn. */
1493 if (! mips_opts.mips16
1494 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1495 && (((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1496 && ! cop_interlocks)
1497 || (! gpr_interlocks
1498 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
1500 /* A load from a coprocessor or from memory. All load
1501 delays delay the use of general register rt for one
1502 instruction on the r3000. The r6000 and r4000 use
1504 /* Itbl support may require additional care here. */
1505 know (prev_pinfo & INSN_WRITE_GPR_T);
1506 if (mips_optimize == 0
1507 || insn_uses_reg (ip,
1508 ((prev_insn.insn_opcode >> OP_SH_RT)
1513 else if (! mips_opts.mips16
1514 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1515 && (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
1516 && ! cop_interlocks)
1517 || (mips_opts.isa == ISA_MIPS1
1518 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))))
1520 /* A generic coprocessor delay. The previous instruction
1521 modified a coprocessor general or control register. If
1522 it modified a control register, we need to avoid any
1523 coprocessor instruction (this is probably not always
1524 required, but it sometimes is). If it modified a general
1525 register, we avoid using that register.
1527 On the r6000 and r4000 loading a coprocessor register
1528 from memory is interlocked, and does not require a delay.
1530 This case is not handled very well. There is no special
1531 knowledge of CP0 handling, and the coprocessors other
1532 than the floating point unit are not distinguished at
1534 /* Itbl support may require additional care here. FIXME!
1535 Need to modify this to include knowledge about
1536 user specified delays! */
1537 if (prev_pinfo & INSN_WRITE_FPR_T)
1539 if (mips_optimize == 0
1540 || insn_uses_reg (ip,
1541 ((prev_insn.insn_opcode >> OP_SH_FT)
1546 else if (prev_pinfo & INSN_WRITE_FPR_S)
1548 if (mips_optimize == 0
1549 || insn_uses_reg (ip,
1550 ((prev_insn.insn_opcode >> OP_SH_FS)
1557 /* We don't know exactly what the previous instruction
1558 does. If the current instruction uses a coprocessor
1559 register, we must insert a NOP. If previous
1560 instruction may set the condition codes, and the
1561 current instruction uses them, we must insert two
1563 /* Itbl support may require additional care here. */
1564 if (mips_optimize == 0
1565 || ((prev_pinfo & INSN_WRITE_COND_CODE)
1566 && (pinfo & INSN_READ_COND_CODE)))
1568 else if (pinfo & INSN_COP)
1572 else if (! mips_opts.mips16
1573 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1574 && (prev_pinfo & INSN_WRITE_COND_CODE)
1575 && ! cop_interlocks)
1577 /* The previous instruction sets the coprocessor condition
1578 codes, but does not require a general coprocessor delay
1579 (this means it is a floating point comparison
1580 instruction). If this instruction uses the condition
1581 codes, we need to insert a single NOP. */
1582 /* Itbl support may require additional care here. */
1583 if (mips_optimize == 0
1584 || (pinfo & INSN_READ_COND_CODE))
1588 /* If we're fixing up mfhi/mflo for the r7000 and the
1589 previous insn was an mfhi/mflo and the current insn
1590 reads the register that the mfhi/mflo wrote to, then
1593 else if (mips_7000_hilo_fix
1594 && MF_HILO_INSN (prev_pinfo)
1595 && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD)
1602 /* If we're fixing up mfhi/mflo for the r7000 and the
1603 2nd previous insn was an mfhi/mflo and the current insn
1604 reads the register that the mfhi/mflo wrote to, then
1607 else if (mips_7000_hilo_fix
1608 && MF_HILO_INSN (prev_prev_insn.insn_opcode)
1609 && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD)
1617 else if (prev_pinfo & INSN_READ_LO)
1619 /* The previous instruction reads the LO register; if the
1620 current instruction writes to the LO register, we must
1621 insert two NOPS. Some newer processors have interlocks.
1622 Also the tx39's multiply instructions can be exectuted
1623 immediatly after a read from HI/LO (without the delay),
1624 though the tx39's divide insns still do require the
1626 if (! (hilo_interlocks
1627 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
1628 && (mips_optimize == 0
1629 || (pinfo & INSN_WRITE_LO)))
1631 /* Most mips16 branch insns don't have a delay slot.
1632 If a read from LO is immediately followed by a branch
1633 to a write to LO we have a read followed by a write
1634 less than 2 insns away. We assume the target of
1635 a branch might be a write to LO, and insert a nop
1636 between a read and an immediately following branch. */
1637 else if (mips_opts.mips16
1638 && (mips_optimize == 0
1639 || (pinfo & MIPS16_INSN_BRANCH)))
1642 else if (prev_insn.insn_mo->pinfo & INSN_READ_HI)
1644 /* The previous instruction reads the HI register; if the
1645 current instruction writes to the HI register, we must
1646 insert a NOP. Some newer processors have interlocks.
1647 Also the note tx39's multiply above. */
1648 if (! (hilo_interlocks
1649 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
1650 && (mips_optimize == 0
1651 || (pinfo & INSN_WRITE_HI)))
1653 /* Most mips16 branch insns don't have a delay slot.
1654 If a read from HI is immediately followed by a branch
1655 to a write to HI we have a read followed by a write
1656 less than 2 insns away. We assume the target of
1657 a branch might be a write to HI, and insert a nop
1658 between a read and an immediately following branch. */
1659 else if (mips_opts.mips16
1660 && (mips_optimize == 0
1661 || (pinfo & MIPS16_INSN_BRANCH)))
1665 /* If the previous instruction was in a noreorder section, then
1666 we don't want to insert the nop after all. */
1667 /* Itbl support may require additional care here. */
1668 if (prev_insn_unreordered)
1671 /* There are two cases which require two intervening
1672 instructions: 1) setting the condition codes using a move to
1673 coprocessor instruction which requires a general coprocessor
1674 delay and then reading the condition codes 2) reading the HI
1675 or LO register and then writing to it (except on processors
1676 which have interlocks). If we are not already emitting a NOP
1677 instruction, we must check for these cases compared to the
1678 instruction previous to the previous instruction. */
1679 if ((! mips_opts.mips16
1680 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1681 && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
1682 && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
1683 && (pinfo & INSN_READ_COND_CODE)
1684 && ! cop_interlocks)
1685 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
1686 && (pinfo & INSN_WRITE_LO)
1687 && ! (hilo_interlocks
1688 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))))
1689 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
1690 && (pinfo & INSN_WRITE_HI)
1691 && ! (hilo_interlocks
1692 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))))
1697 if (prev_prev_insn_unreordered)
1700 if (prev_prev_nop && nops == 0)
1703 /* If we are being given a nop instruction, don't bother with
1704 one of the nops we would otherwise output. This will only
1705 happen when a nop instruction is used with mips_optimize set
1708 && ! mips_opts.noreorder
1709 && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0))
1712 /* Now emit the right number of NOP instructions. */
1713 if (nops > 0 && ! mips_opts.noreorder)
1716 unsigned long old_frag_offset;
1718 struct insn_label_list *l;
1720 old_frag = frag_now;
1721 old_frag_offset = frag_now_fix ();
1723 for (i = 0; i < nops; i++)
1728 listing_prev_line ();
1729 /* We may be at the start of a variant frag. In case we
1730 are, make sure there is enough space for the frag
1731 after the frags created by listing_prev_line. The
1732 argument to frag_grow here must be at least as large
1733 as the argument to all other calls to frag_grow in
1734 this file. We don't have to worry about being in the
1735 middle of a variant frag, because the variants insert
1736 all needed nop instructions themselves. */
1740 for (l = insn_labels; l != NULL; l = l->next)
1744 assert (S_GET_SEGMENT (l->label) == now_seg);
1745 symbol_set_frag (l->label, frag_now);
1746 val = (valueT) frag_now_fix ();
1747 /* mips16 text labels are stored as odd. */
1748 if (mips_opts.mips16)
1750 S_SET_VALUE (l->label, val);
1753 #ifndef NO_ECOFF_DEBUGGING
1754 if (ECOFF_DEBUGGING)
1755 ecoff_fix_loc (old_frag, old_frag_offset);
1758 else if (prev_nop_frag != NULL)
1760 /* We have a frag holding nops we may be able to remove. If
1761 we don't need any nops, we can decrease the size of
1762 prev_nop_frag by the size of one instruction. If we do
1763 need some nops, we count them in prev_nops_required. */
1764 if (prev_nop_frag_since == 0)
1768 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1769 --prev_nop_frag_holds;
1772 prev_nop_frag_required += nops;
1776 if (prev_prev_nop == 0)
1778 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1779 --prev_nop_frag_holds;
1782 ++prev_nop_frag_required;
1785 if (prev_nop_frag_holds <= prev_nop_frag_required)
1786 prev_nop_frag = NULL;
1788 ++prev_nop_frag_since;
1790 /* Sanity check: by the time we reach the second instruction
1791 after prev_nop_frag, we should have used up all the nops
1792 one way or another. */
1793 assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL);
1797 if (*reloc_type > BFD_RELOC_UNUSED)
1799 /* We need to set up a variant frag. */
1800 assert (mips_opts.mips16 && address_expr != NULL);
1801 f = frag_var (rs_machine_dependent, 4, 0,
1802 RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED,
1803 mips16_small, mips16_ext,
1805 & INSN_UNCOND_BRANCH_DELAY),
1806 (*prev_insn_reloc_type
1807 == BFD_RELOC_MIPS16_JMP)),
1808 make_expr_symbol (address_expr), 0, NULL);
1810 else if (place != NULL)
1812 else if (mips_opts.mips16
1814 && *reloc_type != BFD_RELOC_MIPS16_JMP)
1816 /* Make sure there is enough room to swap this instruction with
1817 a following jump instruction. */
1823 if (mips_opts.mips16
1824 && mips_opts.noreorder
1825 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1826 as_warn (_("extended instruction in delay slot"));
1831 fixp[0] = fixp[1] = fixp[2] = NULL;
1832 if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED)
1834 if (address_expr->X_op == O_constant)
1838 switch (*reloc_type)
1841 ip->insn_opcode |= address_expr->X_add_number;
1844 case BFD_RELOC_MIPS_HIGHEST:
1845 tmp = (address_expr->X_add_number + 0x800080008000) >> 16;
1847 ip->insn_opcode |= (tmp >> 16) & 0xffff;
1850 case BFD_RELOC_MIPS_HIGHER:
1851 tmp = (address_expr->X_add_number + 0x80008000) >> 16;
1852 ip->insn_opcode |= (tmp >> 16) & 0xffff;
1855 case BFD_RELOC_HI16_S:
1856 ip->insn_opcode |= ((address_expr->X_add_number + 0x8000)
1860 case BFD_RELOC_HI16:
1861 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
1864 case BFD_RELOC_LO16:
1865 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
1868 case BFD_RELOC_MIPS_JMP:
1869 if ((address_expr->X_add_number & 3) != 0)
1870 as_bad (_("jump to misaligned address (0x%lx)"),
1871 (unsigned long) address_expr->X_add_number);
1872 if (address_expr->X_add_number & ~0xfffffff
1873 || address_expr->X_add_number > 0x7fffffc)
1874 as_bad (_("jump address range overflow (0x%lx)"),
1875 (unsigned long) address_expr->X_add_number);
1876 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
1879 case BFD_RELOC_MIPS16_JMP:
1880 if ((address_expr->X_add_number & 3) != 0)
1881 as_bad (_("jump to misaligned address (0x%lx)"),
1882 (unsigned long) address_expr->X_add_number);
1883 if (address_expr->X_add_number & ~0xfffffff
1884 || address_expr->X_add_number > 0x7fffffc)
1885 as_bad (_("jump address range overflow (0x%lx)"),
1886 (unsigned long) address_expr->X_add_number);
1888 (((address_expr->X_add_number & 0x7c0000) << 3)
1889 | ((address_expr->X_add_number & 0xf800000) >> 7)
1890 | ((address_expr->X_add_number & 0x3fffc) >> 2));
1893 case BFD_RELOC_16_PCREL:
1894 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
1897 case BFD_RELOC_16_PCREL_S2:
1907 /* Don't generate a reloc if we are writing into a variant frag. */
1910 fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal, 4,
1912 (*reloc_type == BFD_RELOC_16_PCREL
1913 || *reloc_type == BFD_RELOC_16_PCREL_S2),
1916 /* These relocations can have an addend that won't fit in
1917 4 octets for 64bit assembly. */
1918 if (HAVE_64BIT_GPRS &&
1919 (*reloc_type == BFD_RELOC_16
1920 || *reloc_type == BFD_RELOC_32
1921 || *reloc_type == BFD_RELOC_MIPS_JMP
1922 || *reloc_type == BFD_RELOC_HI16_S
1923 || *reloc_type == BFD_RELOC_LO16
1924 || *reloc_type == BFD_RELOC_GPREL16
1925 || *reloc_type == BFD_RELOC_MIPS_LITERAL
1926 || *reloc_type == BFD_RELOC_GPREL32
1927 || *reloc_type == BFD_RELOC_64
1928 || *reloc_type == BFD_RELOC_CTOR
1929 || *reloc_type == BFD_RELOC_MIPS_SUB
1930 || *reloc_type == BFD_RELOC_MIPS_HIGHEST
1931 || *reloc_type == BFD_RELOC_MIPS_HIGHER
1932 || *reloc_type == BFD_RELOC_MIPS_SCN_DISP
1933 || *reloc_type == BFD_RELOC_MIPS_REL16
1934 || *reloc_type == BFD_RELOC_MIPS_RELGOT))
1935 fixp[0]->fx_no_overflow = 1;
1939 struct mips_hi_fixup *hi_fixup;
1941 assert (*reloc_type == BFD_RELOC_HI16_S);
1942 hi_fixup = ((struct mips_hi_fixup *)
1943 xmalloc (sizeof (struct mips_hi_fixup)));
1944 hi_fixup->fixp = fixp[0];
1945 hi_fixup->seg = now_seg;
1946 hi_fixup->next = mips_hi_fixup_list;
1947 mips_hi_fixup_list = hi_fixup;
1950 if (reloc_type[1] != BFD_RELOC_UNUSED)
1952 /* FIXME: This symbol can be one of
1953 RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */
1954 address_expr->X_op = O_absent;
1955 address_expr->X_add_symbol = 0;
1956 address_expr->X_add_number = 0;
1958 fixp[1] = fix_new_exp (frag_now, f - frag_now->fr_literal,
1959 4, address_expr, false,
1962 /* These relocations can have an addend that won't fit in
1963 4 octets for 64bit assembly. */
1964 if (HAVE_64BIT_GPRS &&
1965 (*reloc_type == BFD_RELOC_16
1966 || *reloc_type == BFD_RELOC_32
1967 || *reloc_type == BFD_RELOC_MIPS_JMP
1968 || *reloc_type == BFD_RELOC_HI16_S
1969 || *reloc_type == BFD_RELOC_LO16
1970 || *reloc_type == BFD_RELOC_GPREL16
1971 || *reloc_type == BFD_RELOC_MIPS_LITERAL
1972 || *reloc_type == BFD_RELOC_GPREL32
1973 || *reloc_type == BFD_RELOC_64
1974 || *reloc_type == BFD_RELOC_CTOR
1975 || *reloc_type == BFD_RELOC_MIPS_SUB
1976 || *reloc_type == BFD_RELOC_MIPS_HIGHEST
1977 || *reloc_type == BFD_RELOC_MIPS_HIGHER
1978 || *reloc_type == BFD_RELOC_MIPS_SCN_DISP
1979 || *reloc_type == BFD_RELOC_MIPS_REL16
1980 || *reloc_type == BFD_RELOC_MIPS_RELGOT))
1981 fixp[1]->fx_no_overflow = 1;
1983 if (reloc_type[2] != BFD_RELOC_UNUSED)
1985 address_expr->X_op = O_absent;
1986 address_expr->X_add_symbol = 0;
1987 address_expr->X_add_number = 0;
1989 fixp[2] = fix_new_exp (frag_now,
1990 f - frag_now->fr_literal, 4,
1991 address_expr, false,
1994 /* These relocations can have an addend that won't fit in
1995 4 octets for 64bit assembly. */
1996 if (HAVE_64BIT_GPRS &&
1997 (*reloc_type == BFD_RELOC_16
1998 || *reloc_type == BFD_RELOC_32
1999 || *reloc_type == BFD_RELOC_MIPS_JMP
2000 || *reloc_type == BFD_RELOC_HI16_S
2001 || *reloc_type == BFD_RELOC_LO16
2002 || *reloc_type == BFD_RELOC_GPREL16
2003 || *reloc_type == BFD_RELOC_MIPS_LITERAL
2004 || *reloc_type == BFD_RELOC_GPREL32
2005 || *reloc_type == BFD_RELOC_64
2006 || *reloc_type == BFD_RELOC_CTOR
2007 || *reloc_type == BFD_RELOC_MIPS_SUB
2008 || *reloc_type == BFD_RELOC_MIPS_HIGHEST
2009 || *reloc_type == BFD_RELOC_MIPS_HIGHER
2010 || *reloc_type == BFD_RELOC_MIPS_SCN_DISP
2011 || *reloc_type == BFD_RELOC_MIPS_REL16
2012 || *reloc_type == BFD_RELOC_MIPS_RELGOT))
2013 fixp[2]->fx_no_overflow = 1;
2020 if (! mips_opts.mips16)
2021 md_number_to_chars (f, ip->insn_opcode, 4);
2022 else if (*reloc_type == BFD_RELOC_MIPS16_JMP)
2024 md_number_to_chars (f, ip->insn_opcode >> 16, 2);
2025 md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2);
2031 md_number_to_chars (f, 0xf000 | ip->extend, 2);
2034 md_number_to_chars (f, ip->insn_opcode, 2);
2037 /* Update the register mask information. */
2038 if (! mips_opts.mips16)
2040 if (pinfo & INSN_WRITE_GPR_D)
2041 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD);
2042 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
2043 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT);
2044 if (pinfo & INSN_READ_GPR_S)
2045 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS);
2046 if (pinfo & INSN_WRITE_GPR_31)
2047 mips_gprmask |= 1 << RA;
2048 if (pinfo & INSN_WRITE_FPR_D)
2049 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD);
2050 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
2051 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS);
2052 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
2053 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT);
2054 if ((pinfo & INSN_READ_FPR_R) != 0)
2055 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR);
2056 if (pinfo & INSN_COP)
2058 /* We don't keep enough information to sort these cases out.
2059 The itbl support does keep this information however, although
2060 we currently don't support itbl fprmats as part of the cop
2061 instruction. May want to add this support in the future. */
2063 /* Never set the bit for $0, which is always zero. */
2064 mips_gprmask &= ~1 << 0;
2068 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
2069 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX)
2070 & MIPS16OP_MASK_RX);
2071 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
2072 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY)
2073 & MIPS16OP_MASK_RY);
2074 if (pinfo & MIPS16_INSN_WRITE_Z)
2075 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ)
2076 & MIPS16OP_MASK_RZ);
2077 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
2078 mips_gprmask |= 1 << TREG;
2079 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
2080 mips_gprmask |= 1 << SP;
2081 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
2082 mips_gprmask |= 1 << RA;
2083 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2084 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2085 if (pinfo & MIPS16_INSN_READ_Z)
2086 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
2087 & MIPS16OP_MASK_MOVE32Z);
2088 if (pinfo & MIPS16_INSN_READ_GPR_X)
2089 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
2090 & MIPS16OP_MASK_REGR32);
2093 if (place == NULL && ! mips_opts.noreorder)
2095 /* Filling the branch delay slot is more complex. We try to
2096 switch the branch with the previous instruction, which we can
2097 do if the previous instruction does not set up a condition
2098 that the branch tests and if the branch is not itself the
2099 target of any branch. */
2100 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
2101 || (pinfo & INSN_COND_BRANCH_DELAY))
2103 if (mips_optimize < 2
2104 /* If we have seen .set volatile or .set nomove, don't
2106 || mips_opts.nomove != 0
2107 /* If we had to emit any NOP instructions, then we
2108 already know we can not swap. */
2110 /* If we don't even know the previous insn, we can not
2112 || ! prev_insn_valid
2113 /* If the previous insn is already in a branch delay
2114 slot, then we can not swap. */
2115 || prev_insn_is_delay_slot
2116 /* If the previous previous insn was in a .set
2117 noreorder, we can't swap. Actually, the MIPS
2118 assembler will swap in this situation. However, gcc
2119 configured -with-gnu-as will generate code like
2125 in which we can not swap the bne and INSN. If gcc is
2126 not configured -with-gnu-as, it does not output the
2127 .set pseudo-ops. We don't have to check
2128 prev_insn_unreordered, because prev_insn_valid will
2129 be 0 in that case. We don't want to use
2130 prev_prev_insn_valid, because we do want to be able
2131 to swap at the start of a function. */
2132 || prev_prev_insn_unreordered
2133 /* If the branch is itself the target of a branch, we
2134 can not swap. We cheat on this; all we check for is
2135 whether there is a label on this instruction. If
2136 there are any branches to anything other than a
2137 label, users must use .set noreorder. */
2138 || insn_labels != NULL
2139 /* If the previous instruction is in a variant frag, we
2140 can not do the swap. This does not apply to the
2141 mips16, which uses variant frags for different
2143 || (! mips_opts.mips16
2144 && prev_insn_frag->fr_type == rs_machine_dependent)
2145 /* If the branch reads the condition codes, we don't
2146 even try to swap, because in the sequence
2151 we can not swap, and I don't feel like handling that
2153 || (! mips_opts.mips16
2154 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2155 && (pinfo & INSN_READ_COND_CODE))
2156 /* We can not swap with an instruction that requires a
2157 delay slot, becase the target of the branch might
2158 interfere with that instruction. */
2159 || (! mips_opts.mips16
2160 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2162 /* Itbl support may require additional care here. */
2163 & (INSN_LOAD_COPROC_DELAY
2164 | INSN_COPROC_MOVE_DELAY
2165 | INSN_WRITE_COND_CODE)))
2166 || (! (hilo_interlocks
2167 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
2171 || (! mips_opts.mips16
2173 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))
2174 || (! mips_opts.mips16
2175 && mips_opts.isa == ISA_MIPS1
2176 /* Itbl support may require additional care here. */
2177 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))
2178 /* We can not swap with a branch instruction. */
2180 & (INSN_UNCOND_BRANCH_DELAY
2181 | INSN_COND_BRANCH_DELAY
2182 | INSN_COND_BRANCH_LIKELY))
2183 /* We do not swap with a trap instruction, since it
2184 complicates trap handlers to have the trap
2185 instruction be in a delay slot. */
2186 || (prev_pinfo & INSN_TRAP)
2187 /* If the branch reads a register that the previous
2188 instruction sets, we can not swap. */
2189 || (! mips_opts.mips16
2190 && (prev_pinfo & INSN_WRITE_GPR_T)
2191 && insn_uses_reg (ip,
2192 ((prev_insn.insn_opcode >> OP_SH_RT)
2195 || (! mips_opts.mips16
2196 && (prev_pinfo & INSN_WRITE_GPR_D)
2197 && insn_uses_reg (ip,
2198 ((prev_insn.insn_opcode >> OP_SH_RD)
2201 || (mips_opts.mips16
2202 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
2203 && insn_uses_reg (ip,
2204 ((prev_insn.insn_opcode
2206 & MIPS16OP_MASK_RX),
2208 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
2209 && insn_uses_reg (ip,
2210 ((prev_insn.insn_opcode
2212 & MIPS16OP_MASK_RY),
2214 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
2215 && insn_uses_reg (ip,
2216 ((prev_insn.insn_opcode
2218 & MIPS16OP_MASK_RZ),
2220 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
2221 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
2222 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
2223 && insn_uses_reg (ip, RA, MIPS_GR_REG))
2224 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2225 && insn_uses_reg (ip,
2226 MIPS16OP_EXTRACT_REG32R (prev_insn.
2229 /* If the branch writes a register that the previous
2230 instruction sets, we can not swap (we know that
2231 branches write only to RD or to $31). */
2232 || (! mips_opts.mips16
2233 && (prev_pinfo & INSN_WRITE_GPR_T)
2234 && (((pinfo & INSN_WRITE_GPR_D)
2235 && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)
2236 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2237 || ((pinfo & INSN_WRITE_GPR_31)
2238 && (((prev_insn.insn_opcode >> OP_SH_RT)
2241 || (! mips_opts.mips16
2242 && (prev_pinfo & INSN_WRITE_GPR_D)
2243 && (((pinfo & INSN_WRITE_GPR_D)
2244 && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD)
2245 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2246 || ((pinfo & INSN_WRITE_GPR_31)
2247 && (((prev_insn.insn_opcode >> OP_SH_RD)
2250 || (mips_opts.mips16
2251 && (pinfo & MIPS16_INSN_WRITE_31)
2252 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
2253 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2254 && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode)
2256 /* If the branch writes a register that the previous
2257 instruction reads, we can not swap (we know that
2258 branches only write to RD or to $31). */
2259 || (! mips_opts.mips16
2260 && (pinfo & INSN_WRITE_GPR_D)
2261 && insn_uses_reg (&prev_insn,
2262 ((ip->insn_opcode >> OP_SH_RD)
2265 || (! mips_opts.mips16
2266 && (pinfo & INSN_WRITE_GPR_31)
2267 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2268 || (mips_opts.mips16
2269 && (pinfo & MIPS16_INSN_WRITE_31)
2270 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2271 /* If we are generating embedded PIC code, the branch
2272 might be expanded into a sequence which uses $at, so
2273 we can't swap with an instruction which reads it. */
2274 || (mips_pic == EMBEDDED_PIC
2275 && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG))
2276 /* If the previous previous instruction has a load
2277 delay, and sets a register that the branch reads, we
2279 || (! mips_opts.mips16
2280 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2281 /* Itbl support may require additional care here. */
2282 && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
2283 || (! gpr_interlocks
2284 && (prev_prev_insn.insn_mo->pinfo
2285 & INSN_LOAD_MEMORY_DELAY)))
2286 && insn_uses_reg (ip,
2287 ((prev_prev_insn.insn_opcode >> OP_SH_RT)
2290 /* If one instruction sets a condition code and the
2291 other one uses a condition code, we can not swap. */
2292 || ((pinfo & INSN_READ_COND_CODE)
2293 && (prev_pinfo & INSN_WRITE_COND_CODE))
2294 || ((pinfo & INSN_WRITE_COND_CODE)
2295 && (prev_pinfo & INSN_READ_COND_CODE))
2296 /* If the previous instruction uses the PC, we can not
2298 || (mips_opts.mips16
2299 && (prev_pinfo & MIPS16_INSN_READ_PC))
2300 /* If the previous instruction was extended, we can not
2302 || (mips_opts.mips16 && prev_insn_extended)
2303 /* If the previous instruction had a fixup in mips16
2304 mode, we can not swap. This normally means that the
2305 previous instruction was a 4 byte branch anyhow. */
2306 || (mips_opts.mips16 && prev_insn_fixp[0])
2307 /* If the previous instruction is a sync, sync.l, or
2308 sync.p, we can not swap. */
2309 || (prev_pinfo & INSN_SYNC))
2311 /* We could do even better for unconditional branches to
2312 portions of this object file; we could pick up the
2313 instruction at the destination, put it in the delay
2314 slot, and bump the destination address. */
2316 /* Update the previous insn information. */
2317 prev_prev_insn = *ip;
2318 prev_insn.insn_mo = &dummy_opcode;
2322 /* It looks like we can actually do the swap. */
2323 if (! mips_opts.mips16)
2328 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2329 memcpy (temp, prev_f, 4);
2330 memcpy (prev_f, f, 4);
2331 memcpy (f, temp, 4);
2332 if (prev_insn_fixp[0])
2334 prev_insn_fixp[0]->fx_frag = frag_now;
2335 prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal;
2337 if (prev_insn_fixp[1])
2339 prev_insn_fixp[1]->fx_frag = frag_now;
2340 prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal;
2342 if (prev_insn_fixp[2])
2344 prev_insn_fixp[2]->fx_frag = frag_now;
2345 prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal;
2349 fixp[0]->fx_frag = prev_insn_frag;
2350 fixp[0]->fx_where = prev_insn_where;
2354 fixp[1]->fx_frag = prev_insn_frag;
2355 fixp[1]->fx_where = prev_insn_where;
2359 fixp[2]->fx_frag = prev_insn_frag;
2360 fixp[2]->fx_where = prev_insn_where;
2368 assert (prev_insn_fixp[0] == NULL);
2369 assert (prev_insn_fixp[1] == NULL);
2370 assert (prev_insn_fixp[2] == NULL);
2371 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2372 memcpy (temp, prev_f, 2);
2373 memcpy (prev_f, f, 2);
2374 if (*reloc_type != BFD_RELOC_MIPS16_JMP)
2376 assert (*reloc_type == BFD_RELOC_UNUSED);
2377 memcpy (f, temp, 2);
2381 memcpy (f, f + 2, 2);
2382 memcpy (f + 2, temp, 2);
2386 fixp[0]->fx_frag = prev_insn_frag;
2387 fixp[0]->fx_where = prev_insn_where;
2391 fixp[1]->fx_frag = prev_insn_frag;
2392 fixp[1]->fx_where = prev_insn_where;
2396 fixp[2]->fx_frag = prev_insn_frag;
2397 fixp[2]->fx_where = prev_insn_where;
2401 /* Update the previous insn information; leave prev_insn
2403 prev_prev_insn = *ip;
2405 prev_insn_is_delay_slot = 1;
2407 /* If that was an unconditional branch, forget the previous
2408 insn information. */
2409 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
2411 prev_prev_insn.insn_mo = &dummy_opcode;
2412 prev_insn.insn_mo = &dummy_opcode;
2415 prev_insn_fixp[0] = NULL;
2416 prev_insn_fixp[1] = NULL;
2417 prev_insn_fixp[2] = NULL;
2418 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2419 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2420 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2421 prev_insn_extended = 0;
2423 else if (pinfo & INSN_COND_BRANCH_LIKELY)
2425 /* We don't yet optimize a branch likely. What we should do
2426 is look at the target, copy the instruction found there
2427 into the delay slot, and increment the branch to jump to
2428 the next instruction. */
2430 /* Update the previous insn information. */
2431 prev_prev_insn = *ip;
2432 prev_insn.insn_mo = &dummy_opcode;
2433 prev_insn_fixp[0] = NULL;
2434 prev_insn_fixp[1] = NULL;
2435 prev_insn_fixp[2] = NULL;
2436 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2437 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2438 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2439 prev_insn_extended = 0;
2443 /* Update the previous insn information. */
2445 prev_prev_insn.insn_mo = &dummy_opcode;
2447 prev_prev_insn = prev_insn;
2450 /* Any time we see a branch, we always fill the delay slot
2451 immediately; since this insn is not a branch, we know it
2452 is not in a delay slot. */
2453 prev_insn_is_delay_slot = 0;
2455 prev_insn_fixp[0] = fixp[0];
2456 prev_insn_fixp[1] = fixp[1];
2457 prev_insn_fixp[2] = fixp[2];
2458 prev_insn_reloc_type[0] = reloc_type[0];
2459 prev_insn_reloc_type[1] = reloc_type[1];
2460 prev_insn_reloc_type[2] = reloc_type[2];
2461 if (mips_opts.mips16)
2462 prev_insn_extended = (ip->use_extend
2463 || *reloc_type > BFD_RELOC_UNUSED);
2466 prev_prev_insn_unreordered = prev_insn_unreordered;
2467 prev_insn_unreordered = 0;
2468 prev_insn_frag = frag_now;
2469 prev_insn_where = f - frag_now->fr_literal;
2470 prev_insn_valid = 1;
2472 else if (place == NULL)
2474 /* We need to record a bit of information even when we are not
2475 reordering, in order to determine the base address for mips16
2476 PC relative relocs. */
2477 prev_prev_insn = prev_insn;
2479 prev_insn_reloc_type[0] = reloc_type[0];
2480 prev_insn_reloc_type[1] = reloc_type[1];
2481 prev_insn_reloc_type[2] = reloc_type[2];
2482 prev_prev_insn_unreordered = prev_insn_unreordered;
2483 prev_insn_unreordered = 1;
2486 /* We just output an insn, so the next one doesn't have a label. */
2487 mips_clear_insn_labels ();
2489 /* We must ensure that a fixup associated with an unmatched %hi
2490 reloc does not become a variant frag. Otherwise, the
2491 rearrangement of %hi relocs in frob_file may confuse
2495 frag_wane (frag_now);
2500 /* This function forgets that there was any previous instruction or
2501 label. If PRESERVE is non-zero, it remembers enough information to
2502 know whether nops are needed before a noreorder section. */
2505 mips_no_prev_insn (preserve)
2510 prev_insn.insn_mo = &dummy_opcode;
2511 prev_prev_insn.insn_mo = &dummy_opcode;
2512 prev_nop_frag = NULL;
2513 prev_nop_frag_holds = 0;
2514 prev_nop_frag_required = 0;
2515 prev_nop_frag_since = 0;
2517 prev_insn_valid = 0;
2518 prev_insn_is_delay_slot = 0;
2519 prev_insn_unreordered = 0;
2520 prev_insn_extended = 0;
2521 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2522 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2523 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2524 prev_prev_insn_unreordered = 0;
2525 mips_clear_insn_labels ();
2528 /* This function must be called whenever we turn on noreorder or emit
2529 something other than instructions. It inserts any NOPS which might
2530 be needed by the previous instruction, and clears the information
2531 kept for the previous instructions. The INSNS parameter is true if
2532 instructions are to follow. */
2535 mips_emit_delays (insns)
2538 if (! mips_opts.noreorder)
2543 if ((! mips_opts.mips16
2544 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2545 && (! cop_interlocks
2546 && (prev_insn.insn_mo->pinfo
2547 & (INSN_LOAD_COPROC_DELAY
2548 | INSN_COPROC_MOVE_DELAY
2549 | INSN_WRITE_COND_CODE))))
2550 || (! hilo_interlocks
2551 && (prev_insn.insn_mo->pinfo
2554 || (! mips_opts.mips16
2556 && (prev_insn.insn_mo->pinfo
2557 & INSN_LOAD_MEMORY_DELAY))
2558 || (! mips_opts.mips16
2559 && mips_opts.isa == ISA_MIPS1
2560 && (prev_insn.insn_mo->pinfo
2561 & INSN_COPROC_MEMORY_DELAY)))
2563 /* Itbl support may require additional care here. */
2565 if ((! mips_opts.mips16
2566 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2567 && (! cop_interlocks
2568 && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
2569 || (! hilo_interlocks
2570 && ((prev_insn.insn_mo->pinfo & INSN_READ_HI)
2571 || (prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2574 if (prev_insn_unreordered)
2577 else if ((! mips_opts.mips16
2578 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2579 && (! cop_interlocks
2580 && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
2581 || (! hilo_interlocks
2582 && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
2583 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2585 /* Itbl support may require additional care here. */
2586 if (! prev_prev_insn_unreordered)
2592 struct insn_label_list *l;
2596 /* Record the frag which holds the nop instructions, so
2597 that we can remove them if we don't need them. */
2598 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
2599 prev_nop_frag = frag_now;
2600 prev_nop_frag_holds = nops;
2601 prev_nop_frag_required = 0;
2602 prev_nop_frag_since = 0;
2605 for (; nops > 0; --nops)
2610 /* Move on to a new frag, so that it is safe to simply
2611 decrease the size of prev_nop_frag. */
2612 frag_wane (frag_now);
2616 for (l = insn_labels; l != NULL; l = l->next)
2620 assert (S_GET_SEGMENT (l->label) == now_seg);
2621 symbol_set_frag (l->label, frag_now);
2622 val = (valueT) frag_now_fix ();
2623 /* mips16 text labels are stored as odd. */
2624 if (mips_opts.mips16)
2626 S_SET_VALUE (l->label, val);
2631 /* Mark instruction labels in mips16 mode. */
2633 mips16_mark_labels ();
2635 mips_no_prev_insn (insns);
2638 /* Build an instruction created by a macro expansion. This is passed
2639 a pointer to the count of instructions created so far, an
2640 expression, the name of the instruction to build, an operand format
2641 string, and corresponding arguments. */
2645 macro_build (char *place,
2653 macro_build (place, counter, ep, name, fmt, va_alist)
2662 struct mips_cl_insn insn;
2663 bfd_reloc_code_real_type r[3];
2667 va_start (args, fmt);
2673 * If the macro is about to expand into a second instruction,
2674 * print a warning if needed. We need to pass ip as a parameter
2675 * to generate a better warning message here...
2677 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
2678 as_warn (_("Macro instruction expanded into multiple instructions"));
2681 * If the macro is about to expand into a second instruction,
2682 * and it is in a delay slot, print a warning.
2686 && mips_opts.noreorder
2687 && (prev_prev_insn.insn_mo->pinfo
2688 & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY
2689 | INSN_COND_BRANCH_LIKELY)) != 0)
2690 as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot"));
2693 ++*counter; /* bump instruction counter */
2695 if (mips_opts.mips16)
2697 mips16_macro_build (place, counter, ep, name, fmt, args);
2702 r[0] = BFD_RELOC_UNUSED;
2703 r[1] = BFD_RELOC_UNUSED;
2704 r[2] = BFD_RELOC_UNUSED;
2705 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
2706 assert (insn.insn_mo);
2707 assert (strcmp (name, insn.insn_mo->name) == 0);
2709 /* Search until we get a match for NAME. */
2712 /* It is assumed here that macros will never generate
2713 MDMX or MIPS-3D instructions. */
2714 if (strcmp (fmt, insn.insn_mo->args) == 0
2715 && insn.insn_mo->pinfo != INSN_MACRO
2716 && OPCODE_IS_MEMBER (insn.insn_mo, mips_opts.isa, mips_arch)
2717 && (mips_arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
2721 assert (insn.insn_mo->name);
2722 assert (strcmp (name, insn.insn_mo->name) == 0);
2725 insn.insn_opcode = insn.insn_mo->match;
2741 insn.insn_opcode |= va_arg (args, int) << OP_SH_RT;
2745 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE;
2750 insn.insn_opcode |= va_arg (args, int) << OP_SH_FT;
2755 insn.insn_opcode |= va_arg (args, int) << OP_SH_RD;
2760 int tmp = va_arg (args, int);
2762 insn.insn_opcode |= tmp << OP_SH_RT;
2763 insn.insn_opcode |= tmp << OP_SH_RD;
2769 insn.insn_opcode |= va_arg (args, int) << OP_SH_FS;
2776 insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT;
2780 insn.insn_opcode |= va_arg (args, int) << OP_SH_FD;
2784 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20;
2788 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19;
2792 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2;
2799 insn.insn_opcode |= va_arg (args, int) << OP_SH_RS;
2805 *r = (bfd_reloc_code_real_type) va_arg (args, int);
2806 assert (*r == BFD_RELOC_GPREL16
2807 || *r == BFD_RELOC_MIPS_LITERAL
2808 || *r == BFD_RELOC_MIPS_HIGHER
2809 || *r == BFD_RELOC_HI16_S
2810 || *r == BFD_RELOC_LO16
2811 || *r == BFD_RELOC_MIPS_GOT16
2812 || *r == BFD_RELOC_MIPS_CALL16
2813 || *r == BFD_RELOC_MIPS_GOT_DISP
2814 || *r == BFD_RELOC_MIPS_GOT_PAGE
2815 || *r == BFD_RELOC_MIPS_GOT_OFST
2816 || *r == BFD_RELOC_MIPS_GOT_LO16
2817 || *r == BFD_RELOC_MIPS_CALL_LO16
2818 || (ep->X_op == O_subtract
2819 && *r == BFD_RELOC_PCREL_LO16));
2823 *r = (bfd_reloc_code_real_type) va_arg (args, int);
2825 && (ep->X_op == O_constant
2826 || (ep->X_op == O_symbol
2827 && (*r == BFD_RELOC_MIPS_HIGHEST
2828 || *r == BFD_RELOC_HI16_S
2829 || *r == BFD_RELOC_HI16
2830 || *r == BFD_RELOC_GPREL16
2831 || *r == BFD_RELOC_MIPS_GOT_HI16
2832 || *r == BFD_RELOC_MIPS_CALL_HI16))
2833 || (ep->X_op == O_subtract
2834 && *r == BFD_RELOC_PCREL_HI16_S)));
2838 assert (ep != NULL);
2840 * This allows macro() to pass an immediate expression for
2841 * creating short branches without creating a symbol.
2842 * Note that the expression still might come from the assembly
2843 * input, in which case the value is not checked for range nor
2844 * is a relocation entry generated (yuck).
2846 if (ep->X_op == O_constant)
2848 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
2852 if (mips_pic == EMBEDDED_PIC)
2853 *r = BFD_RELOC_16_PCREL_S2;
2855 *r = BFD_RELOC_16_PCREL;
2859 assert (ep != NULL);
2860 *r = BFD_RELOC_MIPS_JMP;
2864 insn.insn_opcode |= va_arg (args, unsigned long);
2873 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
2875 append_insn (place, &insn, ep, r, false);
2879 mips16_macro_build (place, counter, ep, name, fmt, args)
2881 int *counter ATTRIBUTE_UNUSED;
2887 struct mips_cl_insn insn;
2888 bfd_reloc_code_real_type r[3]
2889 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2891 insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
2892 assert (insn.insn_mo);
2893 assert (strcmp (name, insn.insn_mo->name) == 0);
2895 while (strcmp (fmt, insn.insn_mo->args) != 0
2896 || insn.insn_mo->pinfo == INSN_MACRO)
2899 assert (insn.insn_mo->name);
2900 assert (strcmp (name, insn.insn_mo->name) == 0);
2903 insn.insn_opcode = insn.insn_mo->match;
2904 insn.use_extend = false;
2923 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY;
2928 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX;
2932 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ;
2936 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z;
2946 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32;
2953 regno = va_arg (args, int);
2954 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
2955 insn.insn_opcode |= regno << MIPS16OP_SH_REG32R;
2976 assert (ep != NULL);
2978 if (ep->X_op != O_constant)
2979 *r = (int) BFD_RELOC_UNUSED + c;
2982 mips16_immed (NULL, 0, c, ep->X_add_number, false, false,
2983 false, &insn.insn_opcode, &insn.use_extend,
2986 *r = BFD_RELOC_UNUSED;
2992 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6;
2999 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3001 append_insn (place, &insn, ep, r, false);
3005 * Generate a "jalr" instruction with a relocation hint to the called
3006 * function. This occurs in NewABI PIC code.
3009 macro_build_jalr (icnt, ep)
3015 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", "d,s",
3018 fix_new_exp (frag_now, 0, 0, ep, false, BFD_RELOC_MIPS_JALR);
3022 * Generate a "lui" instruction.
3025 macro_build_lui (place, counter, ep, regnum)
3031 expressionS high_expr;
3032 struct mips_cl_insn insn;
3033 bfd_reloc_code_real_type r[3]
3034 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3035 CONST char *name = "lui";
3036 CONST char *fmt = "t,u";
3038 assert (! mips_opts.mips16);
3044 high_expr.X_op = O_constant;
3045 high_expr.X_add_number = ep->X_add_number;
3048 if (high_expr.X_op == O_constant)
3050 /* we can compute the instruction now without a relocation entry */
3051 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
3053 *r = BFD_RELOC_UNUSED;
3055 else if (! HAVE_NEWABI)
3057 assert (ep->X_op == O_symbol);
3058 /* _gp_disp is a special case, used from s_cpload. */
3059 assert (mips_pic == NO_PIC
3060 || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0);
3061 *r = BFD_RELOC_HI16_S;
3065 * If the macro is about to expand into a second instruction,
3066 * print a warning if needed. We need to pass ip as a parameter
3067 * to generate a better warning message here...
3069 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
3070 as_warn (_("Macro instruction expanded into multiple instructions"));
3073 ++*counter; /* bump instruction counter */
3075 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
3076 assert (insn.insn_mo);
3077 assert (strcmp (name, insn.insn_mo->name) == 0);
3078 assert (strcmp (fmt, insn.insn_mo->args) == 0);
3080 insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT);
3081 if (*r == BFD_RELOC_UNUSED)
3083 insn.insn_opcode |= high_expr.X_add_number;
3084 append_insn (place, &insn, NULL, r, false);
3087 append_insn (place, &insn, &high_expr, r, false);
3091 * Generates code to set the $at register to true (one)
3092 * if reg is less than the immediate expression.
3095 set_at (counter, reg, unsignedp)
3100 if (imm_expr.X_op == O_constant
3101 && imm_expr.X_add_number >= -0x8000
3102 && imm_expr.X_add_number < 0x8000)
3103 macro_build ((char *) NULL, counter, &imm_expr,
3104 unsignedp ? "sltiu" : "slti",
3105 "t,r,j", AT, reg, (int) BFD_RELOC_LO16);
3108 load_register (counter, AT, &imm_expr, HAVE_64BIT_GPRS);
3109 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3110 unsignedp ? "sltu" : "slt",
3111 "d,v,t", AT, reg, AT);
3115 /* Warn if an expression is not a constant. */
3118 check_absolute_expr (ip, ex)
3119 struct mips_cl_insn *ip;
3122 if (ex->X_op == O_big)
3123 as_bad (_("unsupported large constant"));
3124 else if (ex->X_op != O_constant)
3125 as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name);
3128 /* Count the leading zeroes by performing a binary chop. This is a
3129 bulky bit of source, but performance is a LOT better for the
3130 majority of values than a simple loop to count the bits:
3131 for (lcnt = 0; (lcnt < 32); lcnt++)
3132 if ((v) & (1 << (31 - lcnt)))
3134 However it is not code size friendly, and the gain will drop a bit
3135 on certain cached systems.
3137 #define COUNT_TOP_ZEROES(v) \
3138 (((v) & ~0xffff) == 0 \
3139 ? ((v) & ~0xff) == 0 \
3140 ? ((v) & ~0xf) == 0 \
3141 ? ((v) & ~0x3) == 0 \
3142 ? ((v) & ~0x1) == 0 \
3147 : ((v) & ~0x7) == 0 \
3150 : ((v) & ~0x3f) == 0 \
3151 ? ((v) & ~0x1f) == 0 \
3154 : ((v) & ~0x7f) == 0 \
3157 : ((v) & ~0xfff) == 0 \
3158 ? ((v) & ~0x3ff) == 0 \
3159 ? ((v) & ~0x1ff) == 0 \
3162 : ((v) & ~0x7ff) == 0 \
3165 : ((v) & ~0x3fff) == 0 \
3166 ? ((v) & ~0x1fff) == 0 \
3169 : ((v) & ~0x7fff) == 0 \
3172 : ((v) & ~0xffffff) == 0 \
3173 ? ((v) & ~0xfffff) == 0 \
3174 ? ((v) & ~0x3ffff) == 0 \
3175 ? ((v) & ~0x1ffff) == 0 \
3178 : ((v) & ~0x7ffff) == 0 \
3181 : ((v) & ~0x3fffff) == 0 \
3182 ? ((v) & ~0x1fffff) == 0 \
3185 : ((v) & ~0x7fffff) == 0 \
3188 : ((v) & ~0xfffffff) == 0 \
3189 ? ((v) & ~0x3ffffff) == 0 \
3190 ? ((v) & ~0x1ffffff) == 0 \
3193 : ((v) & ~0x7ffffff) == 0 \
3196 : ((v) & ~0x3fffffff) == 0 \
3197 ? ((v) & ~0x1fffffff) == 0 \
3200 : ((v) & ~0x7fffffff) == 0 \
3204 /* Is the given value a sign-extended 32-bit value? */
3205 #define IS_SEXT_32BIT_NUM(x) \
3206 (((x) &~ (offsetT) 0x7fffffff) == 0 \
3207 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
3210 * This routine generates the least number of instructions neccessary to load
3211 * an absolute expression value into a register.
3214 load_register (counter, reg, ep, dbl)
3221 expressionS hi32, lo32;
3223 if (ep->X_op != O_big)
3225 assert (ep->X_op == O_constant);
3226 if (ep->X_add_number < 0x8000
3227 && (ep->X_add_number >= 0
3228 || (ep->X_add_number >= -0x8000
3231 || sizeof (ep->X_add_number) > 4))))
3233 /* We can handle 16 bit signed values with an addiu to
3234 $zero. No need to ever use daddiu here, since $zero and
3235 the result are always correct in 32 bit mode. */
3236 macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3237 (int) BFD_RELOC_LO16);
3240 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
3242 /* We can handle 16 bit unsigned values with an ori to
3244 macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0,
3245 (int) BFD_RELOC_LO16);
3248 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)
3251 || sizeof (ep->X_add_number) > 4
3252 || (ep->X_add_number & 0x80000000) == 0))
3253 || ((HAVE_32BIT_GPRS || ! dbl)
3254 && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0)
3257 && ((ep->X_add_number &~ (offsetT) 0xffffffff)
3258 == ~ (offsetT) 0xffffffff)))
3260 /* 32 bit values require an lui. */
3261 macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg,
3262 (int) BFD_RELOC_HI16);
3263 if ((ep->X_add_number & 0xffff) != 0)
3264 macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg,
3265 (int) BFD_RELOC_LO16);
3270 /* The value is larger than 32 bits. */
3272 if (HAVE_32BIT_GPRS)
3274 as_bad (_("Number (0x%lx) larger than 32 bits"),
3275 (unsigned long) ep->X_add_number);
3276 macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3277 (int) BFD_RELOC_LO16);
3281 if (ep->X_op != O_big)
3284 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3285 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3286 hi32.X_add_number &= 0xffffffff;
3288 lo32.X_add_number &= 0xffffffff;
3292 assert (ep->X_add_number > 2);
3293 if (ep->X_add_number == 3)
3294 generic_bignum[3] = 0;
3295 else if (ep->X_add_number > 4)
3296 as_bad (_("Number larger than 64 bits"));
3297 lo32.X_op = O_constant;
3298 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
3299 hi32.X_op = O_constant;
3300 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
3303 if (hi32.X_add_number == 0)
3308 unsigned long hi, lo;
3310 if (hi32.X_add_number == (offsetT) 0xffffffff)
3312 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
3314 macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j",
3315 reg, 0, (int) BFD_RELOC_LO16);
3318 if (lo32.X_add_number & 0x80000000)
3320 macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg,
3321 (int) BFD_RELOC_HI16);
3322 if (lo32.X_add_number & 0xffff)
3323 macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i",
3324 reg, reg, (int) BFD_RELOC_LO16);
3329 /* Check for 16bit shifted constant. We know that hi32 is
3330 non-zero, so start the mask on the first bit of the hi32
3335 unsigned long himask, lomask;
3339 himask = 0xffff >> (32 - shift);
3340 lomask = (0xffff << shift) & 0xffffffff;
3344 himask = 0xffff << (shift - 32);
3347 if ((hi32.X_add_number & ~(offsetT) himask) == 0
3348 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
3352 tmp.X_op = O_constant;
3354 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
3355 | (lo32.X_add_number >> shift));
3357 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
3358 macro_build ((char *) NULL, counter, &tmp,
3359 "ori", "t,r,i", reg, 0,
3360 (int) BFD_RELOC_LO16);
3361 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3362 (shift >= 32) ? "dsll32" : "dsll",
3364 (shift >= 32) ? shift - 32 : shift);
3369 while (shift <= (64 - 16));
3371 /* Find the bit number of the lowest one bit, and store the
3372 shifted value in hi/lo. */
3373 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
3374 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
3378 while ((lo & 1) == 0)
3383 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
3389 while ((hi & 1) == 0)
3398 /* Optimize if the shifted value is a (power of 2) - 1. */
3399 if ((hi == 0 && ((lo + 1) & lo) == 0)
3400 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
3402 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
3407 /* This instruction will set the register to be all
3409 tmp.X_op = O_constant;
3410 tmp.X_add_number = (offsetT) -1;
3411 macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j",
3412 reg, 0, (int) BFD_RELOC_LO16);
3416 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3417 (bit >= 32) ? "dsll32" : "dsll",
3419 (bit >= 32) ? bit - 32 : bit);
3421 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3422 (shift >= 32) ? "dsrl32" : "dsrl",
3424 (shift >= 32) ? shift - 32 : shift);
3429 /* Sign extend hi32 before calling load_register, because we can
3430 generally get better code when we load a sign extended value. */
3431 if ((hi32.X_add_number & 0x80000000) != 0)
3432 hi32.X_add_number |= ~(offsetT) 0xffffffff;
3433 load_register (counter, reg, &hi32, 0);
3436 if ((lo32.X_add_number & 0xffff0000) == 0)
3440 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3441 "dsll32", "d,w,<", reg, freg, 0);
3449 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
3451 macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg,
3452 (int) BFD_RELOC_HI16);
3453 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3454 "dsrl32", "d,w,<", reg, reg, 0);
3460 macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll",
3461 "d,w,<", reg, freg, 16);
3465 mid16.X_add_number >>= 16;
3466 macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg,
3467 freg, (int) BFD_RELOC_LO16);
3468 macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll",
3469 "d,w,<", reg, reg, 16);
3472 if ((lo32.X_add_number & 0xffff) != 0)
3473 macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg,
3474 (int) BFD_RELOC_LO16);
3477 /* Load an address into a register. */
3480 load_address (counter, reg, ep, used_at)
3488 if (ep->X_op != O_constant
3489 && ep->X_op != O_symbol)
3491 as_bad (_("expression too complex"));
3492 ep->X_op = O_constant;
3495 if (ep->X_op == O_constant)
3497 load_register (counter, reg, ep, HAVE_64BIT_ADDRESSES);
3501 if (mips_pic == NO_PIC)
3503 /* If this is a reference to a GP relative symbol, we want
3504 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3506 lui $reg,<sym> (BFD_RELOC_HI16_S)
3507 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3508 If we have an addend, we always use the latter form.
3510 With 64bit address space and a usable $at we want
3511 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3512 lui $at,<sym> (BFD_RELOC_HI16_S)
3513 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3514 daddiu $at,<sym> (BFD_RELOC_LO16)
3518 If $at is already in use, we use an path which is suboptimal
3519 on superscalar processors.
3520 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3521 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3523 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3525 daddiu $reg,<sym> (BFD_RELOC_LO16)
3527 if (HAVE_64BIT_ADDRESSES)
3529 /* We don't do GP optimization for now because RELAX_ENCODE can't
3530 hold the data for such large chunks. */
3534 macro_build (p, counter, ep, "lui", "t,u",
3535 reg, (int) BFD_RELOC_MIPS_HIGHEST);
3536 macro_build (p, counter, ep, "lui", "t,u",
3537 AT, (int) BFD_RELOC_HI16_S);
3538 macro_build (p, counter, ep, "daddiu", "t,r,j",
3539 reg, reg, (int) BFD_RELOC_MIPS_HIGHER);
3540 macro_build (p, counter, ep, "daddiu", "t,r,j",
3541 AT, AT, (int) BFD_RELOC_LO16);
3542 macro_build (p, counter, (expressionS *) NULL, "dsll32",
3543 "d,w,<", reg, reg, 0);
3544 macro_build (p, counter, (expressionS *) NULL, "dadd",
3545 "d,v,t", reg, reg, AT);
3550 macro_build (p, counter, ep, "lui", "t,u",
3551 reg, (int) BFD_RELOC_MIPS_HIGHEST);
3552 macro_build (p, counter, ep, "daddiu", "t,r,j",
3553 reg, reg, (int) BFD_RELOC_MIPS_HIGHER);
3554 macro_build (p, counter, (expressionS *) NULL, "dsll",
3555 "d,w,<", reg, reg, 16);
3556 macro_build (p, counter, ep, "daddiu", "t,r,j",
3557 reg, reg, (int) BFD_RELOC_HI16_S);
3558 macro_build (p, counter, (expressionS *) NULL, "dsll",
3559 "d,w,<", reg, reg, 16);
3560 macro_build (p, counter, ep, "daddiu", "t,r,j",
3561 reg, reg, (int) BFD_RELOC_LO16);
3566 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
3567 && ! nopic_need_relax (ep->X_add_symbol, 1))
3570 macro_build ((char *) NULL, counter, ep,
3571 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j",
3572 reg, mips_gp_register, (int) BFD_RELOC_GPREL16);
3573 p = frag_var (rs_machine_dependent, 8, 0,
3574 RELAX_ENCODE (4, 8, 0, 4, 0,
3575 mips_opts.warn_about_macros),
3576 ep->X_add_symbol, 0, NULL);
3578 macro_build_lui (p, counter, ep, reg);
3581 macro_build (p, counter, ep,
3582 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3583 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3586 else if (mips_pic == SVR4_PIC && ! mips_big_got)
3590 /* If this is a reference to an external symbol, we want
3591 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3593 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3595 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3596 If there is a constant, it must be added in after. */
3597 ex.X_add_number = ep->X_add_number;
3598 ep->X_add_number = 0;
3600 macro_build ((char *) NULL, counter, ep,
3601 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)",
3602 reg, (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
3603 macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", "");
3604 p = frag_var (rs_machine_dependent, 4, 0,
3605 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros),
3606 ep->X_add_symbol, (offsetT) 0, (char *) NULL);
3607 macro_build (p, counter, ep,
3608 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3609 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3610 if (ex.X_add_number != 0)
3612 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3613 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3614 ex.X_op = O_constant;
3615 macro_build ((char *) NULL, counter, &ex,
3616 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3617 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3620 else if (mips_pic == SVR4_PIC)
3625 /* This is the large GOT case. If this is a reference to an
3626 external symbol, we want
3627 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3629 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3630 Otherwise, for a reference to a local symbol, we want
3631 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3633 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3634 If we have NewABI, we want
3635 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3636 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3637 If there is a constant, it must be added in after. */
3638 ex.X_add_number = ep->X_add_number;
3639 ep->X_add_number = 0;
3642 macro_build ((char *) NULL, counter, ep,
3643 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg,
3644 (int) BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
3645 macro_build (p, counter, ep,
3646 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j",
3647 reg, reg, (int) BFD_RELOC_MIPS_GOT_OFST);
3651 if (reg_needs_delay (mips_gp_register))
3656 macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg,
3657 (int) BFD_RELOC_MIPS_GOT_HI16);
3658 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3659 HAVE_32BIT_ADDRESSES ? "addu" : "daddu", "d,v,t", reg,
3660 reg, mips_gp_register);
3661 macro_build ((char *) NULL, counter, ep,
3662 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
3663 "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg);
3664 p = frag_var (rs_machine_dependent, 12 + off, 0,
3665 RELAX_ENCODE (12, 12 + off, off, 8 + off, 0,
3666 mips_opts.warn_about_macros),
3667 ep->X_add_symbol, 0, NULL);
3670 /* We need a nop before loading from $gp. This special
3671 check is required because the lui which starts the main
3672 instruction stream does not refer to $gp, and so will not
3673 insert the nop which may be required. */
3674 macro_build (p, counter, (expressionS *) NULL, "nop", "");
3677 macro_build (p, counter, ep,
3678 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg,
3679 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
3681 macro_build (p, counter, (expressionS *) NULL, "nop", "");
3683 macro_build (p, counter, ep,
3684 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3685 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3688 if (ex.X_add_number != 0)
3690 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3691 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3692 ex.X_op = O_constant;
3693 macro_build ((char *) NULL, counter, &ex,
3694 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3695 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3698 else if (mips_pic == EMBEDDED_PIC)
3701 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3703 macro_build ((char *) NULL, counter, ep,
3704 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3705 "t,r,j", reg, mips_gp_register, (int) BFD_RELOC_GPREL16);
3711 /* Move the contents of register SOURCE into register DEST. */
3714 move_register (counter, dest, source)
3719 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3720 HAVE_32BIT_GPRS ? "addu" : "daddu",
3721 "d,v,t", dest, source, 0);
3726 * This routine implements the seemingly endless macro or synthesized
3727 * instructions and addressing modes in the mips assembly language. Many
3728 * of these macros are simple and are similar to each other. These could
3729 * probably be handled by some kind of table or grammer aproach instead of
3730 * this verbose method. Others are not simple macros but are more like
3731 * optimizing code generation.
3732 * One interesting optimization is when several store macros appear
3733 * consecutivly that would load AT with the upper half of the same address.
3734 * The ensuing load upper instructions are ommited. This implies some kind
3735 * of global optimization. We currently only optimize within a single macro.
3736 * For many of the load and store macros if the address is specified as a
3737 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3738 * first load register 'at' with zero and use it as the base register. The
3739 * mips assembler simply uses register $zero. Just one tiny optimization
3744 struct mips_cl_insn *ip;
3746 register int treg, sreg, dreg, breg;
3762 bfd_reloc_code_real_type r;
3763 int hold_mips_optimize;
3765 assert (! mips_opts.mips16);
3767 treg = (ip->insn_opcode >> 16) & 0x1f;
3768 dreg = (ip->insn_opcode >> 11) & 0x1f;
3769 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
3770 mask = ip->insn_mo->mask;
3772 expr1.X_op = O_constant;
3773 expr1.X_op_symbol = NULL;
3774 expr1.X_add_symbol = NULL;
3775 expr1.X_add_number = 1;
3787 mips_emit_delays (true);
3788 ++mips_opts.noreorder;
3789 mips_any_noreorder = 1;
3791 expr1.X_add_number = 8;
3792 macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg);
3794 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
3797 move_register (&icnt, dreg, sreg);
3798 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
3799 dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
3801 --mips_opts.noreorder;
3822 if (imm_expr.X_op == O_constant
3823 && imm_expr.X_add_number >= -0x8000
3824 && imm_expr.X_add_number < 0x8000)
3826 macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg,
3827 (int) BFD_RELOC_LO16);
3830 load_register (&icnt, AT, &imm_expr, dbl);
3831 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t",
3851 if (imm_expr.X_op == O_constant
3852 && imm_expr.X_add_number >= 0
3853 && imm_expr.X_add_number < 0x10000)
3855 if (mask != M_NOR_I)
3856 macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg,
3857 sreg, (int) BFD_RELOC_LO16);
3860 macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i",
3861 treg, sreg, (int) BFD_RELOC_LO16);
3862 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nor",
3863 "d,v,t", treg, treg, 0);
3868 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
3869 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t",
3887 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
3889 macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg,
3893 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
3894 macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT);
3902 macro_build ((char *) NULL, &icnt, &offset_expr,
3903 likely ? "bgezl" : "bgez", "s,p", sreg);
3908 macro_build ((char *) NULL, &icnt, &offset_expr,
3909 likely ? "blezl" : "blez", "s,p", treg);
3912 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
3914 macro_build ((char *) NULL, &icnt, &offset_expr,
3915 likely ? "beql" : "beq", "s,t,p", AT, 0);
3921 /* check for > max integer */
3922 maxnum = 0x7fffffff;
3923 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
3930 if (imm_expr.X_op == O_constant
3931 && imm_expr.X_add_number >= maxnum
3932 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
3935 /* result is always false */
3939 as_warn (_("Branch %s is always false (nop)"),
3941 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop",
3947 as_warn (_("Branch likely %s is always false"),
3949 macro_build ((char *) NULL, &icnt, &offset_expr, "bnel",
3954 if (imm_expr.X_op != O_constant)
3955 as_bad (_("Unsupported large constant"));
3956 ++imm_expr.X_add_number;
3960 if (mask == M_BGEL_I)
3962 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
3964 macro_build ((char *) NULL, &icnt, &offset_expr,
3965 likely ? "bgezl" : "bgez", "s,p", sreg);
3968 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
3970 macro_build ((char *) NULL, &icnt, &offset_expr,
3971 likely ? "bgtzl" : "bgtz", "s,p", sreg);
3974 maxnum = 0x7fffffff;
3975 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
3982 maxnum = - maxnum - 1;
3983 if (imm_expr.X_op == O_constant
3984 && imm_expr.X_add_number <= maxnum
3985 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
3988 /* result is always true */
3989 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
3990 macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p");
3993 set_at (&icnt, sreg, 0);
3994 macro_build ((char *) NULL, &icnt, &offset_expr,
3995 likely ? "beql" : "beq", "s,t,p", AT, 0);
4005 macro_build ((char *) NULL, &icnt, &offset_expr,
4006 likely ? "beql" : "beq", "s,t,p", 0, treg);
4009 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4010 "d,v,t", AT, sreg, treg);
4011 macro_build ((char *) NULL, &icnt, &offset_expr,
4012 likely ? "beql" : "beq", "s,t,p", AT, 0);
4020 && imm_expr.X_op == O_constant
4021 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4023 if (imm_expr.X_op != O_constant)
4024 as_bad (_("Unsupported large constant"));
4025 ++imm_expr.X_add_number;
4029 if (mask == M_BGEUL_I)
4031 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4033 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4035 macro_build ((char *) NULL, &icnt, &offset_expr,
4036 likely ? "bnel" : "bne", "s,t,p", sreg, 0);
4039 set_at (&icnt, sreg, 1);
4040 macro_build ((char *) NULL, &icnt, &offset_expr,
4041 likely ? "beql" : "beq", "s,t,p", AT, 0);
4049 macro_build ((char *) NULL, &icnt, &offset_expr,
4050 likely ? "bgtzl" : "bgtz", "s,p", sreg);
4055 macro_build ((char *) NULL, &icnt, &offset_expr,
4056 likely ? "bltzl" : "bltz", "s,p", treg);
4059 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4061 macro_build ((char *) NULL, &icnt, &offset_expr,
4062 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4070 macro_build ((char *) NULL, &icnt, &offset_expr,
4071 likely ? "bnel" : "bne", "s,t,p", sreg, 0);
4076 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4077 "d,v,t", AT, treg, sreg);
4078 macro_build ((char *) NULL, &icnt, &offset_expr,
4079 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4087 macro_build ((char *) NULL, &icnt, &offset_expr,
4088 likely ? "blezl" : "blez", "s,p", sreg);
4093 macro_build ((char *) NULL, &icnt, &offset_expr,
4094 likely ? "bgezl" : "bgez", "s,p", treg);
4097 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4099 macro_build ((char *) NULL, &icnt, &offset_expr,
4100 likely ? "beql" : "beq", "s,t,p", AT, 0);
4106 maxnum = 0x7fffffff;
4107 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4114 if (imm_expr.X_op == O_constant
4115 && imm_expr.X_add_number >= maxnum
4116 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4118 if (imm_expr.X_op != O_constant)
4119 as_bad (_("Unsupported large constant"));
4120 ++imm_expr.X_add_number;
4124 if (mask == M_BLTL_I)
4126 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4128 macro_build ((char *) NULL, &icnt, &offset_expr,
4129 likely ? "bltzl" : "bltz", "s,p", sreg);
4132 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4134 macro_build ((char *) NULL, &icnt, &offset_expr,
4135 likely ? "blezl" : "blez", "s,p", sreg);
4138 set_at (&icnt, sreg, 0);
4139 macro_build ((char *) NULL, &icnt, &offset_expr,
4140 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4148 macro_build ((char *) NULL, &icnt, &offset_expr,
4149 likely ? "beql" : "beq", "s,t,p", sreg, 0);
4154 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4155 "d,v,t", AT, treg, sreg);
4156 macro_build ((char *) NULL, &icnt, &offset_expr,
4157 likely ? "beql" : "beq", "s,t,p", AT, 0);
4165 && imm_expr.X_op == O_constant
4166 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4168 if (imm_expr.X_op != O_constant)
4169 as_bad (_("Unsupported large constant"));
4170 ++imm_expr.X_add_number;
4174 if (mask == M_BLTUL_I)
4176 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4178 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4180 macro_build ((char *) NULL, &icnt, &offset_expr,
4181 likely ? "beql" : "beq",
4185 set_at (&icnt, sreg, 1);
4186 macro_build ((char *) NULL, &icnt, &offset_expr,
4187 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4195 macro_build ((char *) NULL, &icnt, &offset_expr,
4196 likely ? "bltzl" : "bltz", "s,p", sreg);
4201 macro_build ((char *) NULL, &icnt, &offset_expr,
4202 likely ? "bgtzl" : "bgtz", "s,p", treg);
4205 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4207 macro_build ((char *) NULL, &icnt, &offset_expr,
4208 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4218 macro_build ((char *) NULL, &icnt, &offset_expr,
4219 likely ? "bnel" : "bne", "s,t,p", 0, treg);
4222 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4225 macro_build ((char *) NULL, &icnt, &offset_expr,
4226 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4241 as_warn (_("Divide by zero."));
4243 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4246 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4251 mips_emit_delays (true);
4252 ++mips_opts.noreorder;
4253 mips_any_noreorder = 1;
4256 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4258 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4259 dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4263 expr1.X_add_number = 8;
4264 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4265 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4266 dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4267 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4270 expr1.X_add_number = -1;
4271 macro_build ((char *) NULL, &icnt, &expr1,
4272 dbl ? "daddiu" : "addiu",
4273 "t,r,j", AT, 0, (int) BFD_RELOC_LO16);
4274 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
4275 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT);
4278 expr1.X_add_number = 1;
4279 macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0,
4280 (int) BFD_RELOC_LO16);
4281 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsll32",
4282 "d,w,<", AT, AT, 31);
4286 expr1.X_add_number = 0x80000000;
4287 macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT,
4288 (int) BFD_RELOC_HI16);
4292 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4294 /* We want to close the noreorder block as soon as possible, so
4295 that later insns are available for delay slot filling. */
4296 --mips_opts.noreorder;
4300 expr1.X_add_number = 8;
4301 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT);
4302 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
4305 /* We want to close the noreorder block as soon as possible, so
4306 that later insns are available for delay slot filling. */
4307 --mips_opts.noreorder;
4309 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4312 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d", dreg);
4351 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4353 as_warn (_("Divide by zero."));
4355 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4358 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4362 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4364 if (strcmp (s2, "mflo") == 0)
4365 move_register (&icnt, dreg, sreg);
4367 move_register (&icnt, dreg, 0);
4370 if (imm_expr.X_op == O_constant
4371 && imm_expr.X_add_number == -1
4372 && s[strlen (s) - 1] != 'u')
4374 if (strcmp (s2, "mflo") == 0)
4376 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4377 dbl ? "dneg" : "neg", "d,w", dreg, sreg);
4380 move_register (&icnt, dreg, 0);
4384 load_register (&icnt, AT, &imm_expr, dbl);
4385 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4387 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg);
4406 mips_emit_delays (true);
4407 ++mips_opts.noreorder;
4408 mips_any_noreorder = 1;
4411 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4413 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4415 /* We want to close the noreorder block as soon as possible, so
4416 that later insns are available for delay slot filling. */
4417 --mips_opts.noreorder;
4421 expr1.X_add_number = 8;
4422 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4423 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4426 /* We want to close the noreorder block as soon as possible, so
4427 that later insns are available for delay slot filling. */
4428 --mips_opts.noreorder;
4429 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4432 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg);
4438 /* Load the address of a symbol into a register. If breg is not
4439 zero, we then add a base register to it. */
4441 if (dbl && HAVE_32BIT_GPRS)
4442 as_warn (_("dla used to load 32-bit register"));
4444 if (! dbl && HAVE_64BIT_OBJECTS)
4445 as_warn (_("la used to load 64-bit address"));
4458 /* When generating embedded PIC code, we permit expressions of
4461 la $treg,foo-bar($breg)
4462 where bar is an address in the current section. These are used
4463 when getting the addresses of functions. We don't permit
4464 X_add_number to be non-zero, because if the symbol is
4465 external the relaxing code needs to know that any addend is
4466 purely the offset to X_op_symbol. */
4467 if (mips_pic == EMBEDDED_PIC
4468 && offset_expr.X_op == O_subtract
4469 && (symbol_constant_p (offset_expr.X_op_symbol)
4470 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
4471 : (symbol_equated_p (offset_expr.X_op_symbol)
4473 (symbol_get_value_expression (offset_expr.X_op_symbol)
4476 && (offset_expr.X_add_number == 0
4477 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
4483 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4484 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
4488 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4489 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
4490 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4491 (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu",
4492 "d,v,t", tempreg, tempreg, breg);
4494 macro_build ((char *) NULL, &icnt, &offset_expr,
4495 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4496 "t,r,j", treg, tempreg, (int) BFD_RELOC_PCREL_LO16);
4502 if (offset_expr.X_op != O_symbol
4503 && offset_expr.X_op != O_constant)
4505 as_bad (_("expression too complex"));
4506 offset_expr.X_op = O_constant;
4509 if (offset_expr.X_op == O_constant)
4510 load_register (&icnt, tempreg, &offset_expr,
4511 ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
4512 ? (dbl || HAVE_64BIT_ADDRESSES)
4513 : HAVE_64BIT_ADDRESSES));
4514 else if (mips_pic == NO_PIC)
4516 /* If this is a reference to a GP relative symbol, we want
4517 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4519 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4520 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4521 If we have a constant, we need two instructions anyhow,
4522 so we may as well always use the latter form.
4524 With 64bit address space and a usable $at we want
4525 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4526 lui $at,<sym> (BFD_RELOC_HI16_S)
4527 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4528 daddiu $at,<sym> (BFD_RELOC_LO16)
4530 dadd $tempreg,$tempreg,$at
4532 If $at is already in use, we use an path which is suboptimal
4533 on superscalar processors.
4534 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4535 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4537 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4539 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4542 if (HAVE_64BIT_ADDRESSES)
4544 /* We don't do GP optimization for now because RELAX_ENCODE can't
4545 hold the data for such large chunks. */
4549 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4550 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
4551 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4552 AT, (int) BFD_RELOC_HI16_S);
4553 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4554 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
4555 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4556 AT, AT, (int) BFD_RELOC_LO16);
4557 macro_build (p, &icnt, (expressionS *) NULL, "dsll32",
4558 "d,w,<", tempreg, tempreg, 0);
4559 macro_build (p, &icnt, (expressionS *) NULL, "dadd", "d,v,t",
4560 tempreg, tempreg, AT);
4565 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4566 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
4567 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4568 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
4569 macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<",
4570 tempreg, tempreg, 16);
4571 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4572 tempreg, tempreg, (int) BFD_RELOC_HI16_S);
4573 macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<",
4574 tempreg, tempreg, 16);
4575 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4576 tempreg, tempreg, (int) BFD_RELOC_LO16);
4581 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
4582 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
4585 macro_build ((char *) NULL, &icnt, &offset_expr, "addiu",
4586 "t,r,j", tempreg, mips_gp_register,
4587 (int) BFD_RELOC_GPREL16);
4588 p = frag_var (rs_machine_dependent, 8, 0,
4589 RELAX_ENCODE (4, 8, 0, 4, 0,
4590 mips_opts.warn_about_macros),
4591 offset_expr.X_add_symbol, 0, NULL);
4593 macro_build_lui (p, &icnt, &offset_expr, tempreg);
4596 macro_build (p, &icnt, &offset_expr, "addiu",
4597 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4600 else if (mips_pic == SVR4_PIC && ! mips_big_got)
4602 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
4604 /* If this is a reference to an external symbol, and there
4605 is no constant, we want
4606 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4607 or if tempreg is PIC_CALL_REG
4608 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4609 For a local symbol, we want
4610 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4612 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4614 If we have a small constant, and this is a reference to
4615 an external symbol, we want
4616 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4618 addiu $tempreg,$tempreg,<constant>
4619 For a local symbol, we want the same instruction
4620 sequence, but we output a BFD_RELOC_LO16 reloc on the
4623 If we have a large constant, and this is a reference to
4624 an external symbol, we want
4625 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4626 lui $at,<hiconstant>
4627 addiu $at,$at,<loconstant>
4628 addu $tempreg,$tempreg,$at
4629 For a local symbol, we want the same instruction
4630 sequence, but we output a BFD_RELOC_LO16 reloc on the
4631 addiu instruction. */
4632 expr1.X_add_number = offset_expr.X_add_number;
4633 offset_expr.X_add_number = 0;
4635 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
4636 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
4637 macro_build ((char *) NULL, &icnt, &offset_expr,
4638 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
4639 "t,o(b)", tempreg, lw_reloc_type, mips_gp_register);
4640 if (expr1.X_add_number == 0)
4649 /* We're going to put in an addu instruction using
4650 tempreg, so we may as well insert the nop right
4652 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4656 p = frag_var (rs_machine_dependent, 8 - off, 0,
4657 RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0,
4659 ? mips_opts.warn_about_macros
4661 offset_expr.X_add_symbol, 0, NULL);
4664 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
4667 macro_build (p, &icnt, &expr1,
4668 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4669 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4670 /* FIXME: If breg == 0, and the next instruction uses
4671 $tempreg, then if this variant case is used an extra
4672 nop will be generated. */
4674 else if (expr1.X_add_number >= -0x8000
4675 && expr1.X_add_number < 0x8000)
4677 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4679 macro_build ((char *) NULL, &icnt, &expr1,
4680 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4681 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4682 frag_var (rs_machine_dependent, 0, 0,
4683 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4684 offset_expr.X_add_symbol, 0, NULL);
4690 /* If we are going to add in a base register, and the
4691 target register and the base register are the same,
4692 then we are using AT as a temporary register. Since
4693 we want to load the constant into AT, we add our
4694 current AT (from the global offset table) and the
4695 register into the register now, and pretend we were
4696 not using a base register. */
4701 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4703 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4704 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4705 "d,v,t", treg, AT, breg);
4711 /* Set mips_optimize around the lui instruction to avoid
4712 inserting an unnecessary nop after the lw. */
4713 hold_mips_optimize = mips_optimize;
4715 macro_build_lui (NULL, &icnt, &expr1, AT);
4716 mips_optimize = hold_mips_optimize;
4718 macro_build ((char *) NULL, &icnt, &expr1,
4719 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4720 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
4721 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4722 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4723 "d,v,t", tempreg, tempreg, AT);
4724 frag_var (rs_machine_dependent, 0, 0,
4725 RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0),
4726 offset_expr.X_add_symbol, 0, NULL);
4730 else if (mips_pic == SVR4_PIC)
4734 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
4735 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
4737 /* This is the large GOT case. If this is a reference to an
4738 external symbol, and there is no constant, we want
4739 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4740 addu $tempreg,$tempreg,$gp
4741 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4742 or if tempreg is PIC_CALL_REG
4743 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4744 addu $tempreg,$tempreg,$gp
4745 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
4746 For a local symbol, we want
4747 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4749 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4751 If we have a small constant, and this is a reference to
4752 an external symbol, we want
4753 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4754 addu $tempreg,$tempreg,$gp
4755 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4757 addiu $tempreg,$tempreg,<constant>
4758 For a local symbol, we want
4759 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4761 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4763 If we have a large constant, and this is a reference to
4764 an external symbol, we want
4765 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4766 addu $tempreg,$tempreg,$gp
4767 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4768 lui $at,<hiconstant>
4769 addiu $at,$at,<loconstant>
4770 addu $tempreg,$tempreg,$at
4771 For a local symbol, we want
4772 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4773 lui $at,<hiconstant>
4774 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4775 addu $tempreg,$tempreg,$at
4777 For NewABI, we want for data addresses
4778 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4779 If tempreg is PIC_CALL_REG pointing to a external symbol, we want
4780 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4784 int reloc_type = (tempreg == PIC_CALL_REG
4785 ? BFD_RELOC_MIPS_CALL16
4786 : BFD_RELOC_MIPS_GOT_DISP);
4788 macro_build ((char *) NULL, &icnt, &offset_expr,
4789 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
4790 "t,o(b)", tempreg, reloc_type, mips_gp_register);
4793 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4794 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4795 "d,v,t", treg, tempreg, breg);
4802 expr1.X_add_number = offset_expr.X_add_number;
4803 offset_expr.X_add_number = 0;
4805 if (reg_needs_delay (mips_gp_register))
4809 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
4811 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
4812 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
4814 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4815 tempreg, lui_reloc_type);
4816 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4817 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4818 "d,v,t", tempreg, tempreg, mips_gp_register);
4819 macro_build ((char *) NULL, &icnt, &offset_expr,
4820 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
4821 "t,o(b)", tempreg, lw_reloc_type, tempreg);
4822 if (expr1.X_add_number == 0)
4830 /* We're going to put in an addu instruction using
4831 tempreg, so we may as well insert the nop right
4833 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4838 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
4839 RELAX_ENCODE (12 + off, 12 + gpdel, gpdel,
4842 ? mips_opts.warn_about_macros
4844 offset_expr.X_add_symbol, 0, NULL);
4846 else if (expr1.X_add_number >= -0x8000
4847 && expr1.X_add_number < 0x8000)
4849 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4851 macro_build ((char *) NULL, &icnt, &expr1,
4852 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4853 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4855 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
4856 RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0,
4858 ? mips_opts.warn_about_macros
4860 offset_expr.X_add_symbol, 0, NULL);
4866 /* If we are going to add in a base register, and the
4867 target register and the base register are the same,
4868 then we are using AT as a temporary register. Since
4869 we want to load the constant into AT, we add our
4870 current AT (from the global offset table) and the
4871 register into the register now, and pretend we were
4872 not using a base register. */
4880 assert (tempreg == AT);
4881 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4883 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4884 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4885 "d,v,t", treg, AT, breg);
4890 /* Set mips_optimize around the lui instruction to avoid
4891 inserting an unnecessary nop after the lw. */
4892 hold_mips_optimize = mips_optimize;
4894 macro_build_lui (NULL, &icnt, &expr1, AT);
4895 mips_optimize = hold_mips_optimize;
4897 macro_build ((char *) NULL, &icnt, &expr1,
4898 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4899 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
4900 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4901 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4902 "d,v,t", dreg, dreg, AT);
4904 p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0,
4905 RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel,
4908 ? mips_opts.warn_about_macros
4910 offset_expr.X_add_symbol, 0, NULL);
4917 /* This is needed because this instruction uses $gp, but
4918 the first instruction on the main stream does not. */
4919 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
4922 macro_build (p, &icnt, &offset_expr,
4923 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
4924 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16,
4927 if (expr1.X_add_number >= -0x8000
4928 && expr1.X_add_number < 0x8000)
4930 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
4932 macro_build (p, &icnt, &expr1,
4933 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4934 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4935 /* FIXME: If add_number is 0, and there was no base
4936 register, the external symbol case ended with a load,
4937 so if the symbol turns out to not be external, and
4938 the next instruction uses tempreg, an unnecessary nop
4939 will be inserted. */
4945 /* We must add in the base register now, as in the
4946 external symbol case. */
4947 assert (tempreg == AT);
4948 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
4950 macro_build (p, &icnt, (expressionS *) NULL,
4951 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4952 "d,v,t", treg, AT, breg);
4955 /* We set breg to 0 because we have arranged to add
4956 it in in both cases. */
4960 macro_build_lui (p, &icnt, &expr1, AT);
4962 macro_build (p, &icnt, &expr1,
4963 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4964 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
4966 macro_build (p, &icnt, (expressionS *) NULL,
4967 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4968 "d,v,t", tempreg, tempreg, AT);
4972 else if (mips_pic == EMBEDDED_PIC)
4975 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4977 macro_build ((char *) NULL, &icnt, &offset_expr,
4978 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j",
4979 tempreg, mips_gp_register, (int) BFD_RELOC_GPREL16);
4988 if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
4989 s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu";
4991 s = HAVE_64BIT_ADDRESSES ? "daddu" : "addu";
4993 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s,
4994 "d,v,t", treg, tempreg, breg);
5003 /* The j instruction may not be used in PIC code, since it
5004 requires an absolute address. We convert it to a b
5006 if (mips_pic == NO_PIC)
5007 macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a");
5009 macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p");
5012 /* The jal instructions must be handled as macros because when
5013 generating PIC code they expand to multi-instruction
5014 sequences. Normally they are simple instructions. */
5019 if (mips_pic == NO_PIC
5020 || mips_pic == EMBEDDED_PIC)
5021 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr",
5023 else if (mips_pic == SVR4_PIC)
5025 if (sreg != PIC_CALL_REG)
5026 as_warn (_("MIPS PIC call to register other than $25"));
5028 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr",
5032 if (mips_cprestore_offset < 0)
5033 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5036 if (! mips_frame_reg_valid)
5038 as_warn (_("No .frame pseudo-op used in PIC code"));
5039 /* Quiet this warning. */
5040 mips_frame_reg_valid = 1;
5042 if (! mips_cprestore_valid)
5044 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5045 /* Quiet this warning. */
5046 mips_cprestore_valid = 1;
5048 expr1.X_add_number = mips_cprestore_offset;
5049 macro_build ((char *) NULL, &icnt, &expr1,
5050 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)",
5051 mips_gp_register, (int) BFD_RELOC_LO16,
5062 if (mips_pic == NO_PIC)
5063 macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a");
5064 else if (mips_pic == SVR4_PIC)
5068 /* If this is a reference to an external symbol, and we are
5069 using a small GOT, we want
5070 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5074 lw $gp,cprestore($sp)
5075 The cprestore value is set using the .cprestore
5076 pseudo-op. If we are using a big GOT, we want
5077 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5079 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5083 lw $gp,cprestore($sp)
5084 If the symbol is not external, we want
5085 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5087 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5090 lw $gp,cprestore($sp)
5092 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5093 jalr $ra,$25 (BFD_RELOC_MIPS_JALR)
5097 macro_build ((char *) NULL, &icnt, &offset_expr,
5098 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5099 "t,o(b)", PIC_CALL_REG,
5100 (int) BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5101 macro_build_jalr (icnt, &offset_expr);
5108 macro_build ((char *) NULL, &icnt, &offset_expr,
5109 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5110 "t,o(b)", PIC_CALL_REG,
5111 (int) BFD_RELOC_MIPS_CALL16, mips_gp_register);
5112 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5114 p = frag_var (rs_machine_dependent, 4, 0,
5115 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5116 offset_expr.X_add_symbol, 0, NULL);
5122 if (reg_needs_delay (mips_gp_register))
5126 macro_build ((char *) NULL, &icnt, &offset_expr, "lui",
5127 "t,u", PIC_CALL_REG,
5128 (int) BFD_RELOC_MIPS_CALL_HI16);
5129 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5130 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5131 "d,v,t", PIC_CALL_REG, PIC_CALL_REG,
5133 macro_build ((char *) NULL, &icnt, &offset_expr,
5134 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5135 "t,o(b)", PIC_CALL_REG,
5136 (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
5137 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5139 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5140 RELAX_ENCODE (16, 12 + gpdel, gpdel,
5142 offset_expr.X_add_symbol, 0, NULL);
5145 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5148 macro_build (p, &icnt, &offset_expr,
5149 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5150 "t,o(b)", PIC_CALL_REG,
5151 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
5153 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5156 macro_build (p, &icnt, &offset_expr,
5157 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5158 "t,r,j", PIC_CALL_REG, PIC_CALL_REG,
5159 (int) BFD_RELOC_LO16);
5160 macro_build_jalr (icnt, &offset_expr);
5162 if (mips_cprestore_offset < 0)
5163 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5166 if (! mips_frame_reg_valid)
5168 as_warn (_("No .frame pseudo-op used in PIC code"));
5169 /* Quiet this warning. */
5170 mips_frame_reg_valid = 1;
5172 if (! mips_cprestore_valid)
5174 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5175 /* Quiet this warning. */
5176 mips_cprestore_valid = 1;
5178 if (mips_opts.noreorder)
5179 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5181 expr1.X_add_number = mips_cprestore_offset;
5182 macro_build ((char *) NULL, &icnt, &expr1,
5183 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)",
5184 mips_gp_register, (int) BFD_RELOC_LO16,
5189 else if (mips_pic == EMBEDDED_PIC)
5191 macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p");
5192 /* The linker may expand the call to a longer sequence which
5193 uses $at, so we must break rather than return. */
5218 /* Itbl support may require additional care here. */
5223 /* Itbl support may require additional care here. */
5228 /* Itbl support may require additional care here. */
5233 /* Itbl support may require additional care here. */
5245 if (mips_arch == CPU_R4650)
5247 as_bad (_("opcode not supported on this processor"));
5251 /* Itbl support may require additional care here. */
5256 /* Itbl support may require additional care here. */
5261 /* Itbl support may require additional care here. */
5281 if (breg == treg || coproc || lr)
5303 /* Itbl support may require additional care here. */
5308 /* Itbl support may require additional care here. */
5313 /* Itbl support may require additional care here. */
5318 /* Itbl support may require additional care here. */
5334 if (mips_arch == CPU_R4650)
5336 as_bad (_("opcode not supported on this processor"));
5341 /* Itbl support may require additional care here. */
5345 /* Itbl support may require additional care here. */
5350 /* Itbl support may require additional care here. */
5362 /* Itbl support may require additional care here. */
5363 if (mask == M_LWC1_AB
5364 || mask == M_SWC1_AB
5365 || mask == M_LDC1_AB
5366 || mask == M_SDC1_AB
5375 /* For embedded PIC, we allow loads where the offset is calculated
5376 by subtracting a symbol in the current segment from an unknown
5377 symbol, relative to a base register, e.g.:
5378 <op> $treg, <sym>-<localsym>($breg)
5379 This is used by the compiler for switch statements. */
5380 if (mips_pic == EMBEDDED_PIC
5381 && offset_expr.X_op == O_subtract
5382 && (symbol_constant_p (offset_expr.X_op_symbol)
5383 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
5384 : (symbol_equated_p (offset_expr.X_op_symbol)
5386 (symbol_get_value_expression (offset_expr.X_op_symbol)
5390 && (offset_expr.X_add_number == 0
5391 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
5393 /* For this case, we output the instructions:
5394 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5395 addiu $tempreg,$tempreg,$breg
5396 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5397 If the relocation would fit entirely in 16 bits, it would be
5399 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5400 instead, but that seems quite difficult. */
5401 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
5402 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
5403 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5404 ((bfd_arch_bits_per_address (stdoutput) == 32
5405 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
5406 ? "addu" : "daddu"),
5407 "d,v,t", tempreg, tempreg, breg);
5408 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, treg,
5409 (int) BFD_RELOC_PCREL_LO16, tempreg);
5415 if (offset_expr.X_op != O_constant
5416 && offset_expr.X_op != O_symbol)
5418 as_bad (_("expression too complex"));
5419 offset_expr.X_op = O_constant;
5422 /* A constant expression in PIC code can be handled just as it
5423 is in non PIC code. */
5424 if (mips_pic == NO_PIC
5425 || offset_expr.X_op == O_constant)
5429 /* If this is a reference to a GP relative symbol, and there
5430 is no base register, we want
5431 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5432 Otherwise, if there is no base register, we want
5433 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5434 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5435 If we have a constant, we need two instructions anyhow,
5436 so we always use the latter form.
5438 If we have a base register, and this is a reference to a
5439 GP relative symbol, we want
5440 addu $tempreg,$breg,$gp
5441 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5443 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5444 addu $tempreg,$tempreg,$breg
5445 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5446 With a constant we always use the latter case.
5448 With 64bit address space and no base register and $at usable,
5450 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5451 lui $at,<sym> (BFD_RELOC_HI16_S)
5452 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5455 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5456 If we have a base register, we want
5457 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5458 lui $at,<sym> (BFD_RELOC_HI16_S)
5459 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5463 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5465 Without $at we can't generate the optimal path for superscalar
5466 processors here since this would require two temporary registers.
5467 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5468 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5470 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5472 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5473 If we have a base register, we want
5474 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5475 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5477 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5479 daddu $tempreg,$tempreg,$breg
5480 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5482 If we have 64-bit addresses, as an optimization, for
5483 addresses which are 32-bit constants (e.g. kseg0/kseg1
5484 addresses) we fall back to the 32-bit address generation
5485 mechanism since it is more efficient. This code should
5486 probably attempt to generate 64-bit constants more
5487 efficiently in general.
5489 if (HAVE_64BIT_ADDRESSES
5490 && !(offset_expr.X_op == O_constant
5491 && IS_SEXT_32BIT_NUM (offset_expr.X_add_number)))
5495 /* We don't do GP optimization for now because RELAX_ENCODE can't
5496 hold the data for such large chunks. */
5500 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5501 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
5502 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5503 AT, (int) BFD_RELOC_HI16_S);
5504 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5505 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
5507 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
5508 "d,v,t", AT, AT, breg);
5509 macro_build (p, &icnt, (expressionS *) NULL, "dsll32",
5510 "d,w,<", tempreg, tempreg, 0);
5511 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
5512 "d,v,t", tempreg, tempreg, AT);
5513 macro_build (p, &icnt, &offset_expr, s,
5514 fmt, treg, (int) BFD_RELOC_LO16, tempreg);
5519 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5520 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
5521 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5522 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
5523 macro_build (p, &icnt, (expressionS *) NULL, "dsll",
5524 "d,w,<", tempreg, tempreg, 16);
5525 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5526 tempreg, tempreg, (int) BFD_RELOC_HI16_S);
5527 macro_build (p, &icnt, (expressionS *) NULL, "dsll",
5528 "d,w,<", tempreg, tempreg, 16);
5530 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
5531 "d,v,t", tempreg, tempreg, breg);
5532 macro_build (p, &icnt, &offset_expr, s,
5533 fmt, treg, (int) BFD_RELOC_LO16, tempreg);
5541 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
5542 || nopic_need_relax (offset_expr.X_add_symbol, 1))
5547 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5548 treg, (int) BFD_RELOC_GPREL16,
5550 p = frag_var (rs_machine_dependent, 8, 0,
5551 RELAX_ENCODE (4, 8, 0, 4, 0,
5552 (mips_opts.warn_about_macros
5554 && mips_opts.noat))),
5555 offset_expr.X_add_symbol, 0, NULL);
5558 macro_build_lui (p, &icnt, &offset_expr, tempreg);
5561 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
5562 (int) BFD_RELOC_LO16, tempreg);
5566 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
5567 || nopic_need_relax (offset_expr.X_add_symbol, 1))
5572 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5573 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5574 "d,v,t", tempreg, breg, mips_gp_register);
5575 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5576 treg, (int) BFD_RELOC_GPREL16, tempreg);
5577 p = frag_var (rs_machine_dependent, 12, 0,
5578 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5579 offset_expr.X_add_symbol, 0, NULL);
5581 macro_build_lui (p, &icnt, &offset_expr, tempreg);
5584 macro_build (p, &icnt, (expressionS *) NULL,
5585 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5586 "d,v,t", tempreg, tempreg, breg);
5589 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
5590 (int) BFD_RELOC_LO16, tempreg);
5593 else if (mips_pic == SVR4_PIC && ! mips_big_got)
5597 /* If this is a reference to an external symbol, we want
5598 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5600 <op> $treg,0($tempreg)
5602 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5604 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5605 <op> $treg,0($tempreg)
5606 If there is a base register, we add it to $tempreg before
5607 the <op>. If there is a constant, we stick it in the
5608 <op> instruction. We don't handle constants larger than
5609 16 bits, because we have no way to load the upper 16 bits
5610 (actually, we could handle them for the subset of cases
5611 in which we are not using $at). */
5612 assert (offset_expr.X_op == O_symbol);
5613 expr1.X_add_number = offset_expr.X_add_number;
5614 offset_expr.X_add_number = 0;
5615 if (expr1.X_add_number < -0x8000
5616 || expr1.X_add_number >= 0x8000)
5617 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5619 macro_build ((char *) NULL, &icnt, &offset_expr,
5620 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", tempreg,
5621 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
5622 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
5623 p = frag_var (rs_machine_dependent, 4, 0,
5624 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5625 offset_expr.X_add_symbol, 0, NULL);
5626 macro_build (p, &icnt, &offset_expr,
5627 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5628 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5630 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5631 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5632 "d,v,t", tempreg, tempreg, breg);
5633 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
5634 (int) BFD_RELOC_LO16, tempreg);
5636 else if (mips_pic == SVR4_PIC)
5641 /* If this is a reference to an external symbol, we want
5642 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5643 addu $tempreg,$tempreg,$gp
5644 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5645 <op> $treg,0($tempreg)
5647 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5649 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5650 <op> $treg,0($tempreg)
5651 If there is a base register, we add it to $tempreg before
5652 the <op>. If there is a constant, we stick it in the
5653 <op> instruction. We don't handle constants larger than
5654 16 bits, because we have no way to load the upper 16 bits
5655 (actually, we could handle them for the subset of cases
5656 in which we are not using $at).
5659 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5660 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5661 <op> $treg,0($tempreg)
5663 assert (offset_expr.X_op == O_symbol);
5664 expr1.X_add_number = offset_expr.X_add_number;
5665 offset_expr.X_add_number = 0;
5666 if (expr1.X_add_number < -0x8000
5667 || expr1.X_add_number >= 0x8000)
5668 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5671 macro_build ((char *) NULL, &icnt, &offset_expr,
5672 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5673 "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_PAGE,
5675 macro_build ((char *) NULL, &icnt, &offset_expr,
5676 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5677 "t,r,j", tempreg, tempreg,
5678 BFD_RELOC_MIPS_GOT_OFST);
5680 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5681 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5682 "d,v,t", tempreg, tempreg, breg);
5683 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
5684 (int) BFD_RELOC_LO16, tempreg);
5691 if (reg_needs_delay (mips_gp_register))
5696 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
5697 tempreg, (int) BFD_RELOC_MIPS_GOT_HI16);
5698 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5699 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5700 "d,v,t", tempreg, tempreg, mips_gp_register);
5701 macro_build ((char *) NULL, &icnt, &offset_expr,
5702 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5703 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16,
5705 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5706 RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0),
5707 offset_expr.X_add_symbol, 0, NULL);
5710 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5713 macro_build (p, &icnt, &offset_expr,
5714 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5715 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16,
5718 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5720 macro_build (p, &icnt, &offset_expr,
5721 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5722 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5724 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5725 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5726 "d,v,t", tempreg, tempreg, breg);
5727 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
5728 (int) BFD_RELOC_LO16, tempreg);
5730 else if (mips_pic == EMBEDDED_PIC)
5732 /* If there is no base register, we want
5733 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5734 If there is a base register, we want
5735 addu $tempreg,$breg,$gp
5736 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5738 assert (offset_expr.X_op == O_symbol);
5741 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5742 treg, (int) BFD_RELOC_GPREL16, mips_gp_register);
5747 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5748 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5749 "d,v,t", tempreg, breg, mips_gp_register);
5750 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5751 treg, (int) BFD_RELOC_GPREL16, tempreg);
5764 load_register (&icnt, treg, &imm_expr, 0);
5768 load_register (&icnt, treg, &imm_expr, 1);
5772 if (imm_expr.X_op == O_constant)
5774 load_register (&icnt, AT, &imm_expr, 0);
5775 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5776 "mtc1", "t,G", AT, treg);
5781 assert (offset_expr.X_op == O_symbol
5782 && strcmp (segment_name (S_GET_SEGMENT
5783 (offset_expr.X_add_symbol)),
5785 && offset_expr.X_add_number == 0);
5786 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
5787 treg, (int) BFD_RELOC_MIPS_LITERAL, mips_gp_register);
5792 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
5793 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
5794 order 32 bits of the value and the low order 32 bits are either
5795 zero or in OFFSET_EXPR. */
5796 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
5798 if (HAVE_64BIT_GPRS)
5799 load_register (&icnt, treg, &imm_expr, 1);
5804 if (target_big_endian)
5816 load_register (&icnt, hreg, &imm_expr, 0);
5819 if (offset_expr.X_op == O_absent)
5820 move_register (&icnt, lreg, 0);
5823 assert (offset_expr.X_op == O_constant);
5824 load_register (&icnt, lreg, &offset_expr, 0);
5831 /* We know that sym is in the .rdata section. First we get the
5832 upper 16 bits of the address. */
5833 if (mips_pic == NO_PIC)
5835 macro_build_lui (NULL, &icnt, &offset_expr, AT);
5837 else if (mips_pic == SVR4_PIC)
5839 macro_build ((char *) NULL, &icnt, &offset_expr,
5840 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5841 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
5844 else if (mips_pic == EMBEDDED_PIC)
5846 /* For embedded PIC we pick up the entire address off $gp in
5847 a single instruction. */
5848 macro_build ((char *) NULL, &icnt, &offset_expr,
5849 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j", AT,
5850 mips_gp_register, (int) BFD_RELOC_GPREL16);
5851 offset_expr.X_op = O_constant;
5852 offset_expr.X_add_number = 0;
5857 /* Now we load the register(s). */
5858 if (HAVE_64BIT_GPRS)
5859 macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)",
5860 treg, (int) BFD_RELOC_LO16, AT);
5863 macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)",
5864 treg, (int) BFD_RELOC_LO16, AT);
5867 /* FIXME: How in the world do we deal with the possible
5869 offset_expr.X_add_number += 4;
5870 macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)",
5871 treg + 1, (int) BFD_RELOC_LO16, AT);
5875 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5876 does not become a variant frag. */
5877 frag_wane (frag_now);
5883 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
5884 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
5885 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
5886 the value and the low order 32 bits are either zero or in
5888 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
5890 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS);
5891 if (HAVE_64BIT_FPRS)
5893 assert (HAVE_64BIT_GPRS);
5894 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5895 "dmtc1", "t,S", AT, treg);
5899 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5900 "mtc1", "t,G", AT, treg + 1);
5901 if (offset_expr.X_op == O_absent)
5902 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5903 "mtc1", "t,G", 0, treg);
5906 assert (offset_expr.X_op == O_constant);
5907 load_register (&icnt, AT, &offset_expr, 0);
5908 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5909 "mtc1", "t,G", AT, treg);
5915 assert (offset_expr.X_op == O_symbol
5916 && offset_expr.X_add_number == 0);
5917 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
5918 if (strcmp (s, ".lit8") == 0)
5920 if (mips_opts.isa != ISA_MIPS1)
5922 macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
5923 "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL,
5927 breg = mips_gp_register;
5928 r = BFD_RELOC_MIPS_LITERAL;
5933 assert (strcmp (s, RDATA_SECTION_NAME) == 0);
5934 if (mips_pic == SVR4_PIC)
5935 macro_build ((char *) NULL, &icnt, &offset_expr,
5936 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5937 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
5941 /* FIXME: This won't work for a 64 bit address. */
5942 macro_build_lui (NULL, &icnt, &offset_expr, AT);
5945 if (mips_opts.isa != ISA_MIPS1)
5947 macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
5948 "T,o(b)", treg, (int) BFD_RELOC_LO16, AT);
5950 /* To avoid confusion in tc_gen_reloc, we must ensure
5951 that this does not become a variant frag. */
5952 frag_wane (frag_now);
5963 if (mips_arch == CPU_R4650)
5965 as_bad (_("opcode not supported on this processor"));
5968 /* Even on a big endian machine $fn comes before $fn+1. We have
5969 to adjust when loading from memory. */
5972 assert (mips_opts.isa == ISA_MIPS1);
5973 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
5974 target_big_endian ? treg + 1 : treg,
5976 /* FIXME: A possible overflow which I don't know how to deal
5978 offset_expr.X_add_number += 4;
5979 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
5980 target_big_endian ? treg : treg + 1,
5983 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5984 does not become a variant frag. */
5985 frag_wane (frag_now);
5994 * The MIPS assembler seems to check for X_add_number not
5995 * being double aligned and generating:
5998 * addiu at,at,%lo(foo+1)
6001 * But, the resulting address is the same after relocation so why
6002 * generate the extra instruction?
6004 if (mips_arch == CPU_R4650)
6006 as_bad (_("opcode not supported on this processor"));
6009 /* Itbl support may require additional care here. */
6011 if (mips_opts.isa != ISA_MIPS1)
6022 if (mips_arch == CPU_R4650)
6024 as_bad (_("opcode not supported on this processor"));
6028 if (mips_opts.isa != ISA_MIPS1)
6036 /* Itbl support may require additional care here. */
6041 if (HAVE_64BIT_GPRS)
6052 if (HAVE_64BIT_GPRS)
6062 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6063 loads for the case of doing a pair of loads to simulate an 'ld'.
6064 This is not currently done by the compiler, and assembly coders
6065 writing embedded-pic code can cope. */
6067 if (offset_expr.X_op != O_symbol
6068 && offset_expr.X_op != O_constant)
6070 as_bad (_("expression too complex"));
6071 offset_expr.X_op = O_constant;
6074 /* Even on a big endian machine $fn comes before $fn+1. We have
6075 to adjust when loading from memory. We set coproc if we must
6076 load $fn+1 first. */
6077 /* Itbl support may require additional care here. */
6078 if (! target_big_endian)
6081 if (mips_pic == NO_PIC
6082 || offset_expr.X_op == O_constant)
6086 /* If this is a reference to a GP relative symbol, we want
6087 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6088 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6089 If we have a base register, we use this
6091 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6092 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6093 If this is not a GP relative symbol, we want
6094 lui $at,<sym> (BFD_RELOC_HI16_S)
6095 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6096 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6097 If there is a base register, we add it to $at after the
6098 lui instruction. If there is a constant, we always use
6100 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6101 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6113 tempreg = mips_gp_register;
6120 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6121 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6122 "d,v,t", AT, breg, mips_gp_register);
6128 /* Itbl support may require additional care here. */
6129 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6130 coproc ? treg + 1 : treg,
6131 (int) BFD_RELOC_GPREL16, tempreg);
6132 offset_expr.X_add_number += 4;
6134 /* Set mips_optimize to 2 to avoid inserting an
6136 hold_mips_optimize = mips_optimize;
6138 /* Itbl support may require additional care here. */
6139 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6140 coproc ? treg : treg + 1,
6141 (int) BFD_RELOC_GPREL16, tempreg);
6142 mips_optimize = hold_mips_optimize;
6144 p = frag_var (rs_machine_dependent, 12 + off, 0,
6145 RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1,
6146 used_at && mips_opts.noat),
6147 offset_expr.X_add_symbol, 0, NULL);
6149 /* We just generated two relocs. When tc_gen_reloc
6150 handles this case, it will skip the first reloc and
6151 handle the second. The second reloc already has an
6152 extra addend of 4, which we added above. We must
6153 subtract it out, and then subtract another 4 to make
6154 the first reloc come out right. The second reloc
6155 will come out right because we are going to add 4 to
6156 offset_expr when we build its instruction below.
6158 If we have a symbol, then we don't want to include
6159 the offset, because it will wind up being included
6160 when we generate the reloc. */
6162 if (offset_expr.X_op == O_constant)
6163 offset_expr.X_add_number -= 8;
6166 offset_expr.X_add_number = -4;
6167 offset_expr.X_op = O_constant;
6170 macro_build_lui (p, &icnt, &offset_expr, AT);
6175 macro_build (p, &icnt, (expressionS *) NULL,
6176 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6177 "d,v,t", AT, breg, AT);
6181 /* Itbl support may require additional care here. */
6182 macro_build (p, &icnt, &offset_expr, s, fmt,
6183 coproc ? treg + 1 : treg,
6184 (int) BFD_RELOC_LO16, AT);
6187 /* FIXME: How do we handle overflow here? */
6188 offset_expr.X_add_number += 4;
6189 /* Itbl support may require additional care here. */
6190 macro_build (p, &icnt, &offset_expr, s, fmt,
6191 coproc ? treg : treg + 1,
6192 (int) BFD_RELOC_LO16, AT);
6194 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6198 /* If this is a reference to an external symbol, we want
6199 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6204 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6206 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6207 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6208 If there is a base register we add it to $at before the
6209 lwc1 instructions. If there is a constant we include it
6210 in the lwc1 instructions. */
6212 expr1.X_add_number = offset_expr.X_add_number;
6213 offset_expr.X_add_number = 0;
6214 if (expr1.X_add_number < -0x8000
6215 || expr1.X_add_number >= 0x8000 - 4)
6216 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6221 frag_grow (24 + off);
6222 macro_build ((char *) NULL, &icnt, &offset_expr,
6223 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", AT,
6224 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
6225 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
6227 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6228 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6229 "d,v,t", AT, breg, AT);
6230 /* Itbl support may require additional care here. */
6231 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6232 coproc ? treg + 1 : treg,
6233 (int) BFD_RELOC_LO16, AT);
6234 expr1.X_add_number += 4;
6236 /* Set mips_optimize to 2 to avoid inserting an undesired
6238 hold_mips_optimize = mips_optimize;
6240 /* Itbl support may require additional care here. */
6241 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6242 coproc ? treg : treg + 1,
6243 (int) BFD_RELOC_LO16, AT);
6244 mips_optimize = hold_mips_optimize;
6246 (void) frag_var (rs_machine_dependent, 0, 0,
6247 RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0),
6248 offset_expr.X_add_symbol, 0, NULL);
6250 else if (mips_pic == SVR4_PIC)
6255 /* If this is a reference to an external symbol, we want
6256 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6258 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6263 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6265 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6266 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6267 If there is a base register we add it to $at before the
6268 lwc1 instructions. If there is a constant we include it
6269 in the lwc1 instructions. */
6271 expr1.X_add_number = offset_expr.X_add_number;
6272 offset_expr.X_add_number = 0;
6273 if (expr1.X_add_number < -0x8000
6274 || expr1.X_add_number >= 0x8000 - 4)
6275 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6276 if (reg_needs_delay (mips_gp_register))
6285 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
6286 AT, (int) BFD_RELOC_MIPS_GOT_HI16);
6287 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6288 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6289 "d,v,t", AT, AT, mips_gp_register);
6290 macro_build ((char *) NULL, &icnt, &offset_expr,
6291 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6292 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT);
6293 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
6295 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6296 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6297 "d,v,t", AT, breg, AT);
6298 /* Itbl support may require additional care here. */
6299 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6300 coproc ? treg + 1 : treg,
6301 (int) BFD_RELOC_LO16, AT);
6302 expr1.X_add_number += 4;
6304 /* Set mips_optimize to 2 to avoid inserting an undesired
6306 hold_mips_optimize = mips_optimize;
6308 /* Itbl support may require additional care here. */
6309 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6310 coproc ? treg : treg + 1,
6311 (int) BFD_RELOC_LO16, AT);
6312 mips_optimize = hold_mips_optimize;
6313 expr1.X_add_number -= 4;
6315 p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0,
6316 RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel,
6317 8 + gpdel + off, 1, 0),
6318 offset_expr.X_add_symbol, 0, NULL);
6321 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
6324 macro_build (p, &icnt, &offset_expr,
6325 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6326 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
6329 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
6333 macro_build (p, &icnt, (expressionS *) NULL,
6334 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6335 "d,v,t", AT, breg, AT);
6338 /* Itbl support may require additional care here. */
6339 macro_build (p, &icnt, &expr1, s, fmt,
6340 coproc ? treg + 1 : treg,
6341 (int) BFD_RELOC_LO16, AT);
6343 expr1.X_add_number += 4;
6345 /* Set mips_optimize to 2 to avoid inserting an undesired
6347 hold_mips_optimize = mips_optimize;
6349 /* Itbl support may require additional care here. */
6350 macro_build (p, &icnt, &expr1, s, fmt,
6351 coproc ? treg : treg + 1,
6352 (int) BFD_RELOC_LO16, AT);
6353 mips_optimize = hold_mips_optimize;
6355 else if (mips_pic == EMBEDDED_PIC)
6357 /* If there is no base register, we use
6358 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6359 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6360 If we have a base register, we use
6362 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6363 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6367 tempreg = mips_gp_register;
6372 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6373 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6374 "d,v,t", AT, breg, mips_gp_register);
6379 /* Itbl support may require additional care here. */
6380 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6381 coproc ? treg + 1 : treg,
6382 (int) BFD_RELOC_GPREL16, tempreg);
6383 offset_expr.X_add_number += 4;
6384 /* Itbl support may require additional care here. */
6385 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6386 coproc ? treg : treg + 1,
6387 (int) BFD_RELOC_GPREL16, tempreg);
6403 assert (HAVE_32BIT_ADDRESSES);
6404 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
6405 (int) BFD_RELOC_LO16, breg);
6406 offset_expr.X_add_number += 4;
6407 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1,
6408 (int) BFD_RELOC_LO16, breg);
6411 /* New code added to support COPZ instructions.
6412 This code builds table entries out of the macros in mip_opcodes.
6413 R4000 uses interlocks to handle coproc delays.
6414 Other chips (like the R3000) require nops to be inserted for delays.
6416 FIXME: Currently, we require that the user handle delays.
6417 In order to fill delay slots for non-interlocked chips,
6418 we must have a way to specify delays based on the coprocessor.
6419 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6420 What are the side-effects of the cop instruction?
6421 What cache support might we have and what are its effects?
6422 Both coprocessor & memory require delays. how long???
6423 What registers are read/set/modified?
6425 If an itbl is provided to interpret cop instructions,
6426 this knowledge can be encoded in the itbl spec. */
6440 /* For now we just do C (same as Cz). The parameter will be
6441 stored in insn_opcode by mips_ip. */
6442 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "C",
6447 move_register (&icnt, dreg, sreg);
6450 #ifdef LOSING_COMPILER
6452 /* Try and see if this is a new itbl instruction.
6453 This code builds table entries out of the macros in mip_opcodes.
6454 FIXME: For now we just assemble the expression and pass it's
6455 value along as a 32-bit immediate.
6456 We may want to have the assembler assemble this value,
6457 so that we gain the assembler's knowledge of delay slots,
6459 Would it be more efficient to use mask (id) here? */
6460 if (itbl_have_entries
6461 && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
6463 s = ip->insn_mo->name;
6465 coproc = ITBL_DECODE_PNUM (immed_expr);;
6466 macro_build ((char *) NULL, &icnt, &immed_expr, s, "C");
6473 as_warn (_("Macro used $at after \".set noat\""));
6478 struct mips_cl_insn *ip;
6480 register int treg, sreg, dreg, breg;
6496 bfd_reloc_code_real_type r;
6499 treg = (ip->insn_opcode >> 16) & 0x1f;
6500 dreg = (ip->insn_opcode >> 11) & 0x1f;
6501 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
6502 mask = ip->insn_mo->mask;
6504 expr1.X_op = O_constant;
6505 expr1.X_op_symbol = NULL;
6506 expr1.X_add_symbol = NULL;
6507 expr1.X_add_number = 1;
6511 #endif /* LOSING_COMPILER */
6516 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6517 dbl ? "dmultu" : "multu", "s,t", sreg, treg);
6518 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6525 /* The MIPS assembler some times generates shifts and adds. I'm
6526 not trying to be that fancy. GCC should do this for us
6528 load_register (&icnt, AT, &imm_expr, dbl);
6529 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6530 dbl ? "dmult" : "mult", "s,t", sreg, AT);
6531 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6545 mips_emit_delays (true);
6546 ++mips_opts.noreorder;
6547 mips_any_noreorder = 1;
6549 load_register (&icnt, AT, &imm_expr, dbl);
6550 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6551 dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
6552 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6554 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6555 dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
6556 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d",
6559 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne", "s,t",
6563 expr1.X_add_number = 8;
6564 macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg,
6566 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
6568 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
6571 --mips_opts.noreorder;
6572 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", dreg);
6585 mips_emit_delays (true);
6586 ++mips_opts.noreorder;
6587 mips_any_noreorder = 1;
6589 load_register (&icnt, AT, &imm_expr, dbl);
6590 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6591 dbl ? "dmultu" : "multu",
6592 "s,t", sreg, imm ? AT : treg);
6593 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d",
6595 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6598 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne", "s,t",
6602 expr1.X_add_number = 8;
6603 macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0);
6604 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
6606 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
6609 --mips_opts.noreorder;
6613 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
6614 "d,v,t", AT, 0, treg);
6615 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
6616 "d,t,s", AT, sreg, AT);
6617 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
6618 "d,t,s", dreg, sreg, treg);
6619 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6620 "d,v,t", dreg, dreg, AT);
6624 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
6625 "d,v,t", AT, 0, treg);
6626 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv",
6627 "d,t,s", AT, sreg, AT);
6628 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv",
6629 "d,t,s", dreg, sreg, treg);
6630 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6631 "d,v,t", dreg, dreg, AT);
6639 if (imm_expr.X_op != O_constant)
6640 as_bad (_("rotate count too large"));
6641 rot = imm_expr.X_add_number & 0x3f;
6644 l = (rot < 0x20) ? "dsll" : "dsll32";
6645 r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
6647 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
6648 "d,w,<", AT, sreg, rot);
6649 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
6650 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6651 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6652 "d,v,t", dreg, dreg, AT);
6660 if (imm_expr.X_op != O_constant)
6661 as_bad (_("rotate count too large"));
6662 rot = imm_expr.X_add_number & 0x1f;
6665 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
6666 "d,w,<", AT, sreg, rot);
6667 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
6668 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6669 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6670 "d,v,t", dreg, dreg, AT);
6675 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
6676 "d,v,t", AT, 0, treg);
6677 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
6678 "d,t,s", AT, sreg, AT);
6679 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
6680 "d,t,s", dreg, sreg, treg);
6681 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6682 "d,v,t", dreg, dreg, AT);
6686 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
6687 "d,v,t", AT, 0, treg);
6688 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv",
6689 "d,t,s", AT, sreg, AT);
6690 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv",
6691 "d,t,s", dreg, sreg, treg);
6692 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6693 "d,v,t", dreg, dreg, AT);
6701 if (imm_expr.X_op != O_constant)
6702 as_bad (_("rotate count too large"));
6703 rot = imm_expr.X_add_number & 0x3f;
6706 r = (rot < 0x20) ? "dsrl" : "dsrl32";
6707 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
6709 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
6710 "d,w,<", AT, sreg, rot);
6711 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
6712 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6713 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6714 "d,v,t", dreg, dreg, AT);
6722 if (imm_expr.X_op != O_constant)
6723 as_bad (_("rotate count too large"));
6724 rot = imm_expr.X_add_number & 0x1f;
6727 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
6728 "d,w,<", AT, sreg, rot);
6729 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
6730 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6731 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6732 "d,v,t", dreg, dreg, AT);
6737 if (mips_arch == CPU_R4650)
6739 as_bad (_("opcode not supported on this processor"));
6742 assert (mips_opts.isa == ISA_MIPS1);
6743 /* Even on a big endian machine $fn comes before $fn+1. We have
6744 to adjust when storing to memory. */
6745 macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
6746 target_big_endian ? treg + 1 : treg,
6747 (int) BFD_RELOC_LO16, breg);
6748 offset_expr.X_add_number += 4;
6749 macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
6750 target_big_endian ? treg : treg + 1,
6751 (int) BFD_RELOC_LO16, breg);
6756 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6757 treg, (int) BFD_RELOC_LO16);
6759 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6760 sreg, (int) BFD_RELOC_LO16);
6763 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
6764 "d,v,t", dreg, sreg, treg);
6765 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6766 dreg, (int) BFD_RELOC_LO16);
6771 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6773 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6774 sreg, (int) BFD_RELOC_LO16);
6779 as_warn (_("Instruction %s: result is always false"),
6781 move_register (&icnt, dreg, 0);
6784 if (imm_expr.X_op == O_constant
6785 && imm_expr.X_add_number >= 0
6786 && imm_expr.X_add_number < 0x10000)
6788 macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg,
6789 sreg, (int) BFD_RELOC_LO16);
6792 else if (imm_expr.X_op == O_constant
6793 && imm_expr.X_add_number > -0x8000
6794 && imm_expr.X_add_number < 0)
6796 imm_expr.X_add_number = -imm_expr.X_add_number;
6797 macro_build ((char *) NULL, &icnt, &imm_expr,
6798 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
6799 "t,r,j", dreg, sreg,
6800 (int) BFD_RELOC_LO16);
6805 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6806 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
6807 "d,v,t", dreg, sreg, AT);
6810 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg,
6811 (int) BFD_RELOC_LO16);
6816 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
6822 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6824 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6825 (int) BFD_RELOC_LO16);
6828 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
6830 if (imm_expr.X_op == O_constant
6831 && imm_expr.X_add_number >= -0x8000
6832 && imm_expr.X_add_number < 0x8000)
6834 macro_build ((char *) NULL, &icnt, &imm_expr,
6835 mask == M_SGE_I ? "slti" : "sltiu",
6836 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
6841 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6842 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6843 mask == M_SGE_I ? "slt" : "sltu", "d,v,t", dreg, sreg,
6847 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6848 (int) BFD_RELOC_LO16);
6853 case M_SGT: /* sreg > treg <==> treg < sreg */
6859 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6863 case M_SGT_I: /* sreg > I <==> I < sreg */
6869 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6870 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6874 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6880 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6882 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6883 (int) BFD_RELOC_LO16);
6886 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6892 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6893 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6895 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6896 (int) BFD_RELOC_LO16);
6900 if (imm_expr.X_op == O_constant
6901 && imm_expr.X_add_number >= -0x8000
6902 && imm_expr.X_add_number < 0x8000)
6904 macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j",
6905 dreg, sreg, (int) BFD_RELOC_LO16);
6908 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6909 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
6914 if (imm_expr.X_op == O_constant
6915 && imm_expr.X_add_number >= -0x8000
6916 && imm_expr.X_add_number < 0x8000)
6918 macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j",
6919 dreg, sreg, (int) BFD_RELOC_LO16);
6922 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6923 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6924 "d,v,t", dreg, sreg, AT);
6929 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6930 "d,v,t", dreg, 0, treg);
6932 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6933 "d,v,t", dreg, 0, sreg);
6936 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
6937 "d,v,t", dreg, sreg, treg);
6938 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6939 "d,v,t", dreg, 0, dreg);
6944 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6946 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6947 "d,v,t", dreg, 0, sreg);
6952 as_warn (_("Instruction %s: result is always true"),
6954 macro_build ((char *) NULL, &icnt, &expr1,
6955 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
6956 "t,r,j", dreg, 0, (int) BFD_RELOC_LO16);
6959 if (imm_expr.X_op == O_constant
6960 && imm_expr.X_add_number >= 0
6961 && imm_expr.X_add_number < 0x10000)
6963 macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i",
6964 dreg, sreg, (int) BFD_RELOC_LO16);
6967 else if (imm_expr.X_op == O_constant
6968 && imm_expr.X_add_number > -0x8000
6969 && imm_expr.X_add_number < 0)
6971 imm_expr.X_add_number = -imm_expr.X_add_number;
6972 macro_build ((char *) NULL, &icnt, &imm_expr,
6973 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
6974 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
6979 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6980 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
6981 "d,v,t", dreg, sreg, AT);
6984 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6985 "d,v,t", dreg, 0, dreg);
6993 if (imm_expr.X_op == O_constant
6994 && imm_expr.X_add_number > -0x8000
6995 && imm_expr.X_add_number <= 0x8000)
6997 imm_expr.X_add_number = -imm_expr.X_add_number;
6998 macro_build ((char *) NULL, &icnt, &imm_expr,
6999 dbl ? "daddi" : "addi",
7000 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
7003 load_register (&icnt, AT, &imm_expr, dbl);
7004 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7005 dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
7011 if (imm_expr.X_op == O_constant
7012 && imm_expr.X_add_number > -0x8000
7013 && imm_expr.X_add_number <= 0x8000)
7015 imm_expr.X_add_number = -imm_expr.X_add_number;
7016 macro_build ((char *) NULL, &icnt, &imm_expr,
7017 dbl ? "daddiu" : "addiu",
7018 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
7021 load_register (&icnt, AT, &imm_expr, dbl);
7022 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7023 dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
7044 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7045 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "s,t", sreg,
7051 assert (mips_opts.isa == ISA_MIPS1);
7052 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
7053 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
7056 * Is the double cfc1 instruction a bug in the mips assembler;
7057 * or is there a reason for it?
7059 mips_emit_delays (true);
7060 ++mips_opts.noreorder;
7061 mips_any_noreorder = 1;
7062 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G",
7064 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G",
7066 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7067 expr1.X_add_number = 3;
7068 macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg,
7069 (int) BFD_RELOC_LO16);
7070 expr1.X_add_number = 2;
7071 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT,
7072 (int) BFD_RELOC_LO16);
7073 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G",
7075 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7076 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7077 mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg);
7078 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G",
7080 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7081 --mips_opts.noreorder;
7090 if (offset_expr.X_add_number >= 0x7fff)
7091 as_bad (_("operand overflow"));
7092 /* avoid load delay */
7093 if (! target_big_endian)
7094 ++offset_expr.X_add_number;
7095 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7096 (int) BFD_RELOC_LO16, breg);
7097 if (! target_big_endian)
7098 --offset_expr.X_add_number;
7100 ++offset_expr.X_add_number;
7101 macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT,
7102 (int) BFD_RELOC_LO16, breg);
7103 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7105 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7119 if (offset_expr.X_add_number >= 0x8000 - off)
7120 as_bad (_("operand overflow"));
7121 if (! target_big_endian)
7122 offset_expr.X_add_number += off;
7123 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7124 (int) BFD_RELOC_LO16, breg);
7125 if (! target_big_endian)
7126 offset_expr.X_add_number -= off;
7128 offset_expr.X_add_number += off;
7129 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
7130 (int) BFD_RELOC_LO16, breg);
7144 load_address (&icnt, AT, &offset_expr, &used_at);
7146 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7147 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7148 "d,v,t", AT, AT, breg);
7149 if (! target_big_endian)
7150 expr1.X_add_number = off;
7152 expr1.X_add_number = 0;
7153 macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg,
7154 (int) BFD_RELOC_LO16, AT);
7155 if (! target_big_endian)
7156 expr1.X_add_number = 0;
7158 expr1.X_add_number = off;
7159 macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7160 (int) BFD_RELOC_LO16, AT);
7166 load_address (&icnt, AT, &offset_expr, &used_at);
7168 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7169 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7170 "d,v,t", AT, AT, breg);
7171 if (target_big_endian)
7172 expr1.X_add_number = 0;
7173 macro_build ((char *) NULL, &icnt, &expr1,
7174 mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg,
7175 (int) BFD_RELOC_LO16, AT);
7176 if (target_big_endian)
7177 expr1.X_add_number = 1;
7179 expr1.X_add_number = 0;
7180 macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
7181 (int) BFD_RELOC_LO16, AT);
7182 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7184 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7189 if (offset_expr.X_add_number >= 0x7fff)
7190 as_bad (_("operand overflow"));
7191 if (target_big_endian)
7192 ++offset_expr.X_add_number;
7193 macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg,
7194 (int) BFD_RELOC_LO16, breg);
7195 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
7197 if (target_big_endian)
7198 --offset_expr.X_add_number;
7200 ++offset_expr.X_add_number;
7201 macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT,
7202 (int) BFD_RELOC_LO16, breg);
7215 if (offset_expr.X_add_number >= 0x8000 - off)
7216 as_bad (_("operand overflow"));
7217 if (! target_big_endian)
7218 offset_expr.X_add_number += off;
7219 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7220 (int) BFD_RELOC_LO16, breg);
7221 if (! target_big_endian)
7222 offset_expr.X_add_number -= off;
7224 offset_expr.X_add_number += off;
7225 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
7226 (int) BFD_RELOC_LO16, breg);
7240 load_address (&icnt, AT, &offset_expr, &used_at);
7242 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7243 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7244 "d,v,t", AT, AT, breg);
7245 if (! target_big_endian)
7246 expr1.X_add_number = off;
7248 expr1.X_add_number = 0;
7249 macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg,
7250 (int) BFD_RELOC_LO16, AT);
7251 if (! target_big_endian)
7252 expr1.X_add_number = 0;
7254 expr1.X_add_number = off;
7255 macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7256 (int) BFD_RELOC_LO16, AT);
7261 load_address (&icnt, AT, &offset_expr, &used_at);
7263 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7264 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7265 "d,v,t", AT, AT, breg);
7266 if (! target_big_endian)
7267 expr1.X_add_number = 0;
7268 macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7269 (int) BFD_RELOC_LO16, AT);
7270 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
7272 if (! target_big_endian)
7273 expr1.X_add_number = 1;
7275 expr1.X_add_number = 0;
7276 macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7277 (int) BFD_RELOC_LO16, AT);
7278 if (! target_big_endian)
7279 expr1.X_add_number = 0;
7281 expr1.X_add_number = 1;
7282 macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
7283 (int) BFD_RELOC_LO16, AT);
7284 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7286 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7291 /* FIXME: Check if this is one of the itbl macros, since they
7292 are added dynamically. */
7293 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
7297 as_warn (_("Macro used $at after \".set noat\""));
7300 /* Implement macros in mips16 mode. */
7304 struct mips_cl_insn *ip;
7307 int xreg, yreg, zreg, tmp;
7311 const char *s, *s2, *s3;
7313 mask = ip->insn_mo->mask;
7315 xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
7316 yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY;
7317 zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
7321 expr1.X_op = O_constant;
7322 expr1.X_op_symbol = NULL;
7323 expr1.X_add_symbol = NULL;
7324 expr1.X_add_number = 1;
7343 mips_emit_delays (true);
7344 ++mips_opts.noreorder;
7345 mips_any_noreorder = 1;
7346 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7347 dbl ? "ddiv" : "div",
7348 "0,x,y", xreg, yreg);
7349 expr1.X_add_number = 2;
7350 macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg);
7351 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", "6",
7354 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7355 since that causes an overflow. We should do that as well,
7356 but I don't see how to do the comparisons without a temporary
7358 --mips_opts.noreorder;
7359 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x", zreg);
7378 mips_emit_delays (true);
7379 ++mips_opts.noreorder;
7380 mips_any_noreorder = 1;
7381 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "0,x,y",
7383 expr1.X_add_number = 2;
7384 macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg);
7385 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
7387 --mips_opts.noreorder;
7388 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "x", zreg);
7394 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7395 dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
7396 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "x",
7405 if (imm_expr.X_op != O_constant)
7406 as_bad (_("Unsupported large constant"));
7407 imm_expr.X_add_number = -imm_expr.X_add_number;
7408 macro_build ((char *) NULL, &icnt, &imm_expr,
7409 dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
7413 if (imm_expr.X_op != O_constant)
7414 as_bad (_("Unsupported large constant"));
7415 imm_expr.X_add_number = -imm_expr.X_add_number;
7416 macro_build ((char *) NULL, &icnt, &imm_expr, "addiu",
7421 if (imm_expr.X_op != O_constant)
7422 as_bad (_("Unsupported large constant"));
7423 imm_expr.X_add_number = -imm_expr.X_add_number;
7424 macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu",
7447 goto do_reverse_branch;
7451 goto do_reverse_branch;
7463 goto do_reverse_branch;
7474 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y",
7476 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p");
7503 goto do_addone_branch_i;
7508 goto do_addone_branch_i;
7523 goto do_addone_branch_i;
7530 if (imm_expr.X_op != O_constant)
7531 as_bad (_("Unsupported large constant"));
7532 ++imm_expr.X_add_number;
7535 macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg);
7536 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p");
7540 expr1.X_add_number = 0;
7541 macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg);
7543 move_register (&icnt, xreg, yreg);
7544 expr1.X_add_number = 2;
7545 macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p");
7546 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7547 "neg", "x,w", xreg, xreg);
7551 /* For consistency checking, verify that all bits are specified either
7552 by the match/mask part of the instruction definition, or by the
7555 validate_mips_insn (opc)
7556 const struct mips_opcode *opc;
7558 const char *p = opc->args;
7560 unsigned long used_bits = opc->mask;
7562 if ((used_bits & opc->match) != opc->match)
7564 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7565 opc->name, opc->args);
7568 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7575 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7576 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7578 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
7579 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
7580 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
7581 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7583 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7584 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
7586 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
7588 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
7589 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
7590 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
7591 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
7592 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7593 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
7594 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7595 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7596 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7597 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7598 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
7599 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7600 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7601 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
7602 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7603 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
7604 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7606 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
7607 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
7608 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7609 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
7611 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7612 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7613 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
7614 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7615 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7616 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7617 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
7618 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7619 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7622 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
7623 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
7624 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7626 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7627 c, opc->name, opc->args);
7631 if (used_bits != 0xffffffff)
7633 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7634 ~used_bits & 0xffffffff, opc->name, opc->args);
7640 /* This routine assembles an instruction into its binary format. As a
7641 side effect, it sets one of the global variables imm_reloc or
7642 offset_reloc to the type of relocation to do if one of the operands
7643 is an address expression. */
7648 struct mips_cl_insn *ip;
7653 struct mips_opcode *insn;
7656 unsigned int lastregno = 0;
7662 /* If the instruction contains a '.', we first try to match an instruction
7663 including the '.'. Then we try again without the '.'. */
7665 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
7668 /* If we stopped on whitespace, then replace the whitespace with null for
7669 the call to hash_find. Save the character we replaced just in case we
7670 have to re-parse the instruction. */
7677 insn = (struct mips_opcode *) hash_find (op_hash, str);
7679 /* If we didn't find the instruction in the opcode table, try again, but
7680 this time with just the instruction up to, but not including the
7684 /* Restore the character we overwrite above (if any). */
7688 /* Scan up to the first '.' or whitespace. */
7690 *s != '\0' && *s != '.' && !ISSPACE (*s);
7694 /* If we did not find a '.', then we can quit now. */
7697 insn_error = "unrecognized opcode";
7701 /* Lookup the instruction in the hash table. */
7703 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
7705 insn_error = "unrecognized opcode";
7715 assert (strcmp (insn->name, str) == 0);
7717 if (OPCODE_IS_MEMBER (insn,
7719 | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
7720 | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
7726 if (insn->pinfo != INSN_MACRO)
7728 if (mips_arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)
7734 if (insn + 1 < &mips_opcodes[NUMOPCODES]
7735 && strcmp (insn->name, insn[1].name) == 0)
7744 static char buf[100];
7746 _("opcode not supported on this processor: %s (%s)"),
7747 mips_cpu_to_str (mips_arch),
7748 mips_isa_to_str (mips_opts.isa));
7759 ip->insn_opcode = insn->match;
7761 for (args = insn->args;; ++args)
7765 s += strspn (s, " \t");
7769 case '\0': /* end of args */
7782 ip->insn_opcode |= lastregno << OP_SH_RS;
7786 ip->insn_opcode |= lastregno << OP_SH_RT;
7790 ip->insn_opcode |= lastregno << OP_SH_FT;
7794 ip->insn_opcode |= lastregno << OP_SH_FS;
7800 /* Handle optional base register.
7801 Either the base register is omitted or
7802 we must have a left paren. */
7803 /* This is dependent on the next operand specifier
7804 is a base register specification. */
7805 assert (args[1] == 'b' || args[1] == '5'
7806 || args[1] == '-' || args[1] == '4');
7810 case ')': /* these must match exactly */
7815 case '<': /* must be at least one digit */
7817 * According to the manual, if the shift amount is greater
7818 * than 31 or less than 0, then the shift amount should be
7819 * mod 32. In reality the mips assembler issues an error.
7820 * We issue a warning and mask out all but the low 5 bits.
7822 my_getExpression (&imm_expr, s);
7823 check_absolute_expr (ip, &imm_expr);
7824 if ((unsigned long) imm_expr.X_add_number > 31)
7826 as_warn (_("Improper shift amount (%lu)"),
7827 (unsigned long) imm_expr.X_add_number);
7828 imm_expr.X_add_number &= OP_MASK_SHAMT;
7830 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT;
7831 imm_expr.X_op = O_absent;
7835 case '>': /* shift amount minus 32 */
7836 my_getExpression (&imm_expr, s);
7837 check_absolute_expr (ip, &imm_expr);
7838 if ((unsigned long) imm_expr.X_add_number < 32
7839 || (unsigned long) imm_expr.X_add_number > 63)
7841 ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT;
7842 imm_expr.X_op = O_absent;
7846 case 'k': /* cache code */
7847 case 'h': /* prefx code */
7848 my_getExpression (&imm_expr, s);
7849 check_absolute_expr (ip, &imm_expr);
7850 if ((unsigned long) imm_expr.X_add_number > 31)
7852 as_warn (_("Invalid value for `%s' (%lu)"),
7854 (unsigned long) imm_expr.X_add_number);
7855 imm_expr.X_add_number &= 0x1f;
7858 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE;
7860 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX;
7861 imm_expr.X_op = O_absent;
7865 case 'c': /* break code */
7866 my_getExpression (&imm_expr, s);
7867 check_absolute_expr (ip, &imm_expr);
7868 if ((unsigned long) imm_expr.X_add_number > 1023)
7870 as_warn (_("Illegal break code (%lu)"),
7871 (unsigned long) imm_expr.X_add_number);
7872 imm_expr.X_add_number &= OP_MASK_CODE;
7874 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE;
7875 imm_expr.X_op = O_absent;
7879 case 'q': /* lower break code */
7880 my_getExpression (&imm_expr, s);
7881 check_absolute_expr (ip, &imm_expr);
7882 if ((unsigned long) imm_expr.X_add_number > 1023)
7884 as_warn (_("Illegal lower break code (%lu)"),
7885 (unsigned long) imm_expr.X_add_number);
7886 imm_expr.X_add_number &= OP_MASK_CODE2;
7888 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2;
7889 imm_expr.X_op = O_absent;
7893 case 'B': /* 20-bit syscall/break code. */
7894 my_getExpression (&imm_expr, s);
7895 check_absolute_expr (ip, &imm_expr);
7896 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
7897 as_warn (_("Illegal 20-bit code (%lu)"),
7898 (unsigned long) imm_expr.X_add_number);
7899 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20;
7900 imm_expr.X_op = O_absent;
7904 case 'C': /* Coprocessor code */
7905 my_getExpression (&imm_expr, s);
7906 check_absolute_expr (ip, &imm_expr);
7907 if ((unsigned long) imm_expr.X_add_number >= (1 << 25))
7909 as_warn (_("Coproccesor code > 25 bits (%lu)"),
7910 (unsigned long) imm_expr.X_add_number);
7911 imm_expr.X_add_number &= ((1 << 25) - 1);
7913 ip->insn_opcode |= imm_expr.X_add_number;
7914 imm_expr.X_op = O_absent;
7918 case 'J': /* 19-bit wait code. */
7919 my_getExpression (&imm_expr, s);
7920 check_absolute_expr (ip, &imm_expr);
7921 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
7922 as_warn (_("Illegal 19-bit code (%lu)"),
7923 (unsigned long) imm_expr.X_add_number);
7924 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19;
7925 imm_expr.X_op = O_absent;
7929 case 'P': /* Performance register */
7930 my_getExpression (&imm_expr, s);
7931 check_absolute_expr (ip, &imm_expr);
7932 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
7934 as_warn (_("Invalid performance register (%lu)"),
7935 (unsigned long) imm_expr.X_add_number);
7936 imm_expr.X_add_number &= OP_MASK_PERFREG;
7938 ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG);
7939 imm_expr.X_op = O_absent;
7943 case 'b': /* base register */
7944 case 'd': /* destination register */
7945 case 's': /* source register */
7946 case 't': /* target register */
7947 case 'r': /* both target and source */
7948 case 'v': /* both dest and source */
7949 case 'w': /* both dest and target */
7950 case 'E': /* coprocessor target register */
7951 case 'G': /* coprocessor destination register */
7952 case 'x': /* ignore register name */
7953 case 'z': /* must be zero register */
7954 case 'U': /* destination register (clo/clz). */
7969 while (ISDIGIT (*s));
7971 as_bad (_("Invalid register number (%d)"), regno);
7973 else if (*args == 'E' || *args == 'G')
7977 if (s[1] == 'r' && s[2] == 'a')
7982 else if (s[1] == 'f' && s[2] == 'p')
7987 else if (s[1] == 's' && s[2] == 'p')
7992 else if (s[1] == 'g' && s[2] == 'p')
7997 else if (s[1] == 'a' && s[2] == 't')
8002 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
8007 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
8012 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
8017 else if (itbl_have_entries)
8022 p = s + 1; /* advance past '$' */
8023 n = itbl_get_field (&p); /* n is name */
8025 /* See if this is a register defined in an
8027 if (itbl_get_reg_val (n, &r))
8029 /* Get_field advances to the start of
8030 the next field, so we need to back
8031 rack to the end of the last field. */
8035 s = strchr (s, '\0');
8048 as_warn (_("Used $at without \".set noat\""));
8054 if (c == 'r' || c == 'v' || c == 'w')
8061 /* 'z' only matches $0. */
8062 if (c == 'z' && regno != 0)
8065 /* Now that we have assembled one operand, we use the args string
8066 * to figure out where it goes in the instruction. */
8073 ip->insn_opcode |= regno << OP_SH_RS;
8077 ip->insn_opcode |= regno << OP_SH_RD;
8080 ip->insn_opcode |= regno << OP_SH_RD;
8081 ip->insn_opcode |= regno << OP_SH_RT;
8086 ip->insn_opcode |= regno << OP_SH_RT;
8089 /* This case exists because on the r3000 trunc
8090 expands into a macro which requires a gp
8091 register. On the r6000 or r4000 it is
8092 assembled into a single instruction which
8093 ignores the register. Thus the insn version
8094 is MIPS_ISA2 and uses 'x', and the macro
8095 version is MIPS_ISA1 and uses 't'. */
8098 /* This case is for the div instruction, which
8099 acts differently if the destination argument
8100 is $0. This only matches $0, and is checked
8101 outside the switch. */
8104 /* Itbl operand; not yet implemented. FIXME ?? */
8106 /* What about all other operands like 'i', which
8107 can be specified in the opcode table? */
8117 ip->insn_opcode |= lastregno << OP_SH_RS;
8120 ip->insn_opcode |= lastregno << OP_SH_RT;
8125 case 'O': /* MDMX alignment immediate constant. */
8126 my_getExpression (&imm_expr, s);
8127 check_absolute_expr (ip, &imm_expr);
8128 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
8130 as_warn ("Improper align amount (%ld), using low bits",
8131 (long) imm_expr.X_add_number);
8132 imm_expr.X_add_number &= OP_MASK_ALN;
8134 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN;
8135 imm_expr.X_op = O_absent;
8139 case 'Q': /* MDMX vector, element sel, or const. */
8142 /* MDMX Immediate. */
8143 my_getExpression (&imm_expr, s);
8144 check_absolute_expr (ip, &imm_expr);
8145 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
8147 as_warn (_("Invalid MDMX Immediate (%ld)"),
8148 (long) imm_expr.X_add_number);
8149 imm_expr.X_add_number &= OP_MASK_FT;
8151 imm_expr.X_add_number &= OP_MASK_FT;
8152 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8153 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
8155 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
8156 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT;
8157 imm_expr.X_op = O_absent;
8161 /* Not MDMX Immediate. Fall through. */
8162 case 'X': /* MDMX destination register. */
8163 case 'Y': /* MDMX source register. */
8164 case 'Z': /* MDMX target register. */
8166 case 'D': /* floating point destination register */
8167 case 'S': /* floating point source register */
8168 case 'T': /* floating point target register */
8169 case 'R': /* floating point source register */
8173 /* Accept $fN for FP and MDMX register numbers, and in
8174 addition accept $vN for MDMX register numbers. */
8175 if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2]))
8176 || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v'
8187 while (ISDIGIT (*s));
8190 as_bad (_("Invalid float register number (%d)"), regno);
8192 if ((regno & 1) != 0
8194 && ! (strcmp (str, "mtc1") == 0
8195 || strcmp (str, "mfc1") == 0
8196 || strcmp (str, "lwc1") == 0
8197 || strcmp (str, "swc1") == 0
8198 || strcmp (str, "l.s") == 0
8199 || strcmp (str, "s.s") == 0))
8200 as_warn (_("Float register should be even, was %d"),
8208 if (c == 'V' || c == 'W')
8219 ip->insn_opcode |= regno << OP_SH_FD;
8224 ip->insn_opcode |= regno << OP_SH_FS;
8227 /* This is like 'Z', but also needs to fix the MDMX
8228 vector/scalar select bits. Note that the
8229 scalar immediate case is handled above. */
8232 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
8233 int max_el = (is_qh ? 3 : 7);
8235 my_getExpression(&imm_expr, s);
8236 check_absolute_expr (ip, &imm_expr);
8238 if (imm_expr.X_add_number > max_el)
8239 as_bad(_("Bad element selector %ld"),
8240 (long) imm_expr.X_add_number);
8241 imm_expr.X_add_number &= max_el;
8242 ip->insn_opcode |= (imm_expr.X_add_number
8246 as_warn(_("Expecting ']' found '%s'"), s);
8252 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8253 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
8256 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
8263 ip->insn_opcode |= regno << OP_SH_FT;
8266 ip->insn_opcode |= regno << OP_SH_FR;
8276 ip->insn_opcode |= lastregno << OP_SH_FS;
8279 ip->insn_opcode |= lastregno << OP_SH_FT;
8285 my_getExpression (&imm_expr, s);
8286 if (imm_expr.X_op != O_big
8287 && imm_expr.X_op != O_constant)
8288 insn_error = _("absolute expression required");
8293 my_getExpression (&offset_expr, s);
8294 *imm_reloc = BFD_RELOC_32;
8307 unsigned char temp[8];
8309 unsigned int length;
8314 /* These only appear as the last operand in an
8315 instruction, and every instruction that accepts
8316 them in any variant accepts them in all variants.
8317 This means we don't have to worry about backing out
8318 any changes if the instruction does not match.
8320 The difference between them is the size of the
8321 floating point constant and where it goes. For 'F'
8322 and 'L' the constant is 64 bits; for 'f' and 'l' it
8323 is 32 bits. Where the constant is placed is based
8324 on how the MIPS assembler does things:
8327 f -- immediate value
8330 The .lit4 and .lit8 sections are only used if
8331 permitted by the -G argument.
8333 When generating embedded PIC code, we use the
8334 .lit8 section but not the .lit4 section (we can do
8335 .lit4 inline easily; we need to put .lit8
8336 somewhere in the data segment, and using .lit8
8337 permits the linker to eventually combine identical
8340 The code below needs to know whether the target register
8341 is 32 or 64 bits wide. It relies on the fact 'f' and
8342 'F' are used with GPR-based instructions and 'l' and
8343 'L' are used with FPR-based instructions. */
8345 f64 = *args == 'F' || *args == 'L';
8346 using_gprs = *args == 'F' || *args == 'f';
8348 save_in = input_line_pointer;
8349 input_line_pointer = s;
8350 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
8352 s = input_line_pointer;
8353 input_line_pointer = save_in;
8354 if (err != NULL && *err != '\0')
8356 as_bad (_("Bad floating point constant: %s"), err);
8357 memset (temp, '\0', sizeof temp);
8358 length = f64 ? 8 : 4;
8361 assert (length == (unsigned) (f64 ? 8 : 4));
8365 && (! USE_GLOBAL_POINTER_OPT
8366 || mips_pic == EMBEDDED_PIC
8367 || g_switch_value < 4
8368 || (temp[0] == 0 && temp[1] == 0)
8369 || (temp[2] == 0 && temp[3] == 0))))
8371 imm_expr.X_op = O_constant;
8372 if (! target_big_endian)
8373 imm_expr.X_add_number = bfd_getl32 (temp);
8375 imm_expr.X_add_number = bfd_getb32 (temp);
8378 && ! mips_disable_float_construction
8379 /* Constants can only be constructed in GPRs and
8380 copied to FPRs if the GPRs are at least as wide
8381 as the FPRs. Force the constant into memory if
8382 we are using 64-bit FPRs but the GPRs are only
8385 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
8386 && ((temp[0] == 0 && temp[1] == 0)
8387 || (temp[2] == 0 && temp[3] == 0))
8388 && ((temp[4] == 0 && temp[5] == 0)
8389 || (temp[6] == 0 && temp[7] == 0)))
8391 /* The value is simple enough to load with a couple of
8392 instructions. If using 32-bit registers, set
8393 imm_expr to the high order 32 bits and offset_expr to
8394 the low order 32 bits. Otherwise, set imm_expr to
8395 the entire 64 bit constant. */
8396 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
8398 imm_expr.X_op = O_constant;
8399 offset_expr.X_op = O_constant;
8400 if (! target_big_endian)
8402 imm_expr.X_add_number = bfd_getl32 (temp + 4);
8403 offset_expr.X_add_number = bfd_getl32 (temp);
8407 imm_expr.X_add_number = bfd_getb32 (temp);
8408 offset_expr.X_add_number = bfd_getb32 (temp + 4);
8410 if (offset_expr.X_add_number == 0)
8411 offset_expr.X_op = O_absent;
8413 else if (sizeof (imm_expr.X_add_number) > 4)
8415 imm_expr.X_op = O_constant;
8416 if (! target_big_endian)
8417 imm_expr.X_add_number = bfd_getl64 (temp);
8419 imm_expr.X_add_number = bfd_getb64 (temp);
8423 imm_expr.X_op = O_big;
8424 imm_expr.X_add_number = 4;
8425 if (! target_big_endian)
8427 generic_bignum[0] = bfd_getl16 (temp);
8428 generic_bignum[1] = bfd_getl16 (temp + 2);
8429 generic_bignum[2] = bfd_getl16 (temp + 4);
8430 generic_bignum[3] = bfd_getl16 (temp + 6);
8434 generic_bignum[0] = bfd_getb16 (temp + 6);
8435 generic_bignum[1] = bfd_getb16 (temp + 4);
8436 generic_bignum[2] = bfd_getb16 (temp + 2);
8437 generic_bignum[3] = bfd_getb16 (temp);
8443 const char *newname;
8446 /* Switch to the right section. */
8448 subseg = now_subseg;
8451 default: /* unused default case avoids warnings. */
8453 newname = RDATA_SECTION_NAME;
8454 if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8)
8455 || mips_pic == EMBEDDED_PIC)
8459 if (mips_pic == EMBEDDED_PIC)
8462 newname = RDATA_SECTION_NAME;
8465 assert (!USE_GLOBAL_POINTER_OPT
8466 || g_switch_value >= 4);
8470 new_seg = subseg_new (newname, (subsegT) 0);
8471 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
8472 bfd_set_section_flags (stdoutput, new_seg,
8477 frag_align (*args == 'l' ? 2 : 3, 0, 0);
8478 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
8479 && strcmp (TARGET_OS, "elf") != 0)
8480 record_alignment (new_seg, 4);
8482 record_alignment (new_seg, *args == 'l' ? 2 : 3);
8484 as_bad (_("Can't use floating point insn in this section"));
8486 /* Set the argument to the current address in the
8488 offset_expr.X_op = O_symbol;
8489 offset_expr.X_add_symbol =
8490 symbol_new ("L0\001", now_seg,
8491 (valueT) frag_now_fix (), frag_now);
8492 offset_expr.X_add_number = 0;
8494 /* Put the floating point number into the section. */
8495 p = frag_more ((int) length);
8496 memcpy (p, temp, length);
8498 /* Switch back to the original section. */
8499 subseg_set (seg, subseg);
8504 case 'i': /* 16 bit unsigned immediate */
8505 case 'j': /* 16 bit signed immediate */
8506 *imm_reloc = BFD_RELOC_LO16;
8507 c = my_getSmallExpression (&imm_expr, s);
8512 if (imm_expr.X_op == O_constant)
8513 imm_expr.X_add_number =
8514 (imm_expr.X_add_number >> 16) & 0xffff;
8516 else if (c == S_EX_HIGHEST)
8517 *imm_reloc = BFD_RELOC_MIPS_HIGHEST;
8518 else if (c == S_EX_HIGHER)
8519 *imm_reloc = BFD_RELOC_MIPS_HIGHER;
8520 else if (c == S_EX_GP_REL)
8522 /* This occurs in NewABI only. */
8523 c = my_getSmallExpression (&imm_expr, s);
8525 as_bad (_("bad composition of relocations"));
8528 c = my_getSmallExpression (&imm_expr, s);
8530 as_bad (_("bad composition of relocations"));
8533 imm_reloc[0] = BFD_RELOC_GPREL16;
8534 imm_reloc[1] = BFD_RELOC_MIPS_SUB;
8535 imm_reloc[2] = BFD_RELOC_LO16;
8540 else if (c == S_EX_HI)
8542 *imm_reloc = BFD_RELOC_HI16_S;
8543 imm_unmatched_hi = true;
8546 *imm_reloc = BFD_RELOC_HI16;
8548 else if (imm_expr.X_op == O_constant)
8549 imm_expr.X_add_number &= 0xffff;
8553 if ((c == S_EX_NONE && imm_expr.X_op != O_constant)
8554 || ((imm_expr.X_add_number < 0
8555 || imm_expr.X_add_number >= 0x10000)
8556 && imm_expr.X_op == O_constant))
8558 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
8559 !strcmp (insn->name, insn[1].name))
8561 if (imm_expr.X_op == O_constant
8562 || imm_expr.X_op == O_big)
8563 as_bad (_("16 bit expression not in range 0..65535"));
8571 /* The upper bound should be 0x8000, but
8572 unfortunately the MIPS assembler accepts numbers
8573 from 0x8000 to 0xffff and sign extends them, and
8574 we want to be compatible. We only permit this
8575 extended range for an instruction which does not
8576 provide any further alternates, since those
8577 alternates may handle other cases. People should
8578 use the numbers they mean, rather than relying on
8579 a mysterious sign extension. */
8580 more = (insn + 1 < &mips_opcodes[NUMOPCODES] &&
8581 strcmp (insn->name, insn[1].name) == 0);
8586 if ((c == S_EX_NONE && imm_expr.X_op != O_constant)
8587 || ((imm_expr.X_add_number < -0x8000
8588 || imm_expr.X_add_number >= max)
8589 && imm_expr.X_op == O_constant)
8591 && imm_expr.X_add_number < 0
8593 && imm_expr.X_unsigned
8594 && sizeof (imm_expr.X_add_number) <= 4))
8598 if (imm_expr.X_op == O_constant
8599 || imm_expr.X_op == O_big)
8600 as_bad (_("16 bit expression not in range -32768..32767"));
8606 case 'o': /* 16 bit offset */
8607 c = my_getSmallExpression (&offset_expr, s);
8609 /* If this value won't fit into a 16 bit offset, then go
8610 find a macro that will generate the 32 bit offset
8613 && (offset_expr.X_op != O_constant
8614 || offset_expr.X_add_number >= 0x8000
8615 || offset_expr.X_add_number < -0x8000))
8620 if (offset_expr.X_op != O_constant)
8622 offset_expr.X_add_number =
8623 (offset_expr.X_add_number >> 16) & 0xffff;
8625 *offset_reloc = BFD_RELOC_LO16;
8629 case 'p': /* pc relative offset */
8630 if (mips_pic == EMBEDDED_PIC)
8631 *offset_reloc = BFD_RELOC_16_PCREL_S2;
8633 *offset_reloc = BFD_RELOC_16_PCREL;
8634 my_getExpression (&offset_expr, s);
8638 case 'u': /* upper 16 bits */
8639 c = my_getSmallExpression (&imm_expr, s);
8640 *imm_reloc = BFD_RELOC_LO16;
8645 if (imm_expr.X_op == O_constant)
8646 imm_expr.X_add_number =
8647 (imm_expr.X_add_number >> 16) & 0xffff;
8648 else if (c == S_EX_HI)
8650 *imm_reloc = BFD_RELOC_HI16_S;
8651 imm_unmatched_hi = true;
8654 else if (c == S_EX_HIGHEST)
8655 *imm_reloc = BFD_RELOC_MIPS_HIGHEST;
8656 else if (c == S_EX_GP_REL)
8658 /* This occurs in NewABI only. */
8659 c = my_getSmallExpression (&imm_expr, s);
8661 as_bad (_("bad composition of relocations"));
8664 c = my_getSmallExpression (&imm_expr, s);
8666 as_bad (_("bad composition of relocations"));
8669 imm_reloc[0] = BFD_RELOC_GPREL16;
8670 imm_reloc[1] = BFD_RELOC_MIPS_SUB;
8671 imm_reloc[2] = BFD_RELOC_HI16_S;
8677 *imm_reloc = BFD_RELOC_HI16;
8679 else if (imm_expr.X_op == O_constant)
8680 imm_expr.X_add_number &= 0xffff;
8682 if (imm_expr.X_op == O_constant
8683 && (imm_expr.X_add_number < 0
8684 || imm_expr.X_add_number >= 0x10000))
8685 as_bad (_("lui expression not in range 0..65535"));
8689 case 'a': /* 26 bit address */
8690 my_getExpression (&offset_expr, s);
8692 *offset_reloc = BFD_RELOC_MIPS_JMP;
8695 case 'N': /* 3 bit branch condition code */
8696 case 'M': /* 3 bit compare condition code */
8697 if (strncmp (s, "$fcc", 4) != 0)
8707 while (ISDIGIT (*s));
8709 as_bad (_("invalid condition code register $fcc%d"), regno);
8711 ip->insn_opcode |= regno << OP_SH_BCC;
8713 ip->insn_opcode |= regno << OP_SH_CCC;
8717 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
8728 while (ISDIGIT (*s));
8731 c = 8; /* Invalid sel value. */
8734 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
8735 ip->insn_opcode |= c;
8739 as_bad (_("bad char = '%c'\n"), *args);
8744 /* Args don't match. */
8745 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
8746 !strcmp (insn->name, insn[1].name))
8750 insn_error = _("illegal operands");
8755 insn_error = _("illegal operands");
8760 /* This routine assembles an instruction into its binary format when
8761 assembling for the mips16. As a side effect, it sets one of the
8762 global variables imm_reloc or offset_reloc to the type of
8763 relocation to do if one of the operands is an address expression.
8764 It also sets mips16_small and mips16_ext if the user explicitly
8765 requested a small or extended instruction. */
8770 struct mips_cl_insn *ip;
8774 struct mips_opcode *insn;
8777 unsigned int lastregno = 0;
8782 mips16_small = false;
8785 for (s = str; ISLOWER (*s); ++s)
8797 if (s[1] == 't' && s[2] == ' ')
8800 mips16_small = true;
8804 else if (s[1] == 'e' && s[2] == ' ')
8813 insn_error = _("unknown opcode");
8817 if (mips_opts.noautoextend && ! mips16_ext)
8818 mips16_small = true;
8820 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
8822 insn_error = _("unrecognized opcode");
8829 assert (strcmp (insn->name, str) == 0);
8832 ip->insn_opcode = insn->match;
8833 ip->use_extend = false;
8834 imm_expr.X_op = O_absent;
8835 imm_reloc[0] = BFD_RELOC_UNUSED;
8836 imm_reloc[1] = BFD_RELOC_UNUSED;
8837 imm_reloc[2] = BFD_RELOC_UNUSED;
8838 offset_expr.X_op = O_absent;
8839 offset_reloc[0] = BFD_RELOC_UNUSED;
8840 offset_reloc[1] = BFD_RELOC_UNUSED;
8841 offset_reloc[2] = BFD_RELOC_UNUSED;
8842 for (args = insn->args; 1; ++args)
8849 /* In this switch statement we call break if we did not find
8850 a match, continue if we did find a match, or return if we
8859 /* Stuff the immediate value in now, if we can. */
8860 if (imm_expr.X_op == O_constant
8861 && *imm_reloc > BFD_RELOC_UNUSED
8862 && insn->pinfo != INSN_MACRO)
8864 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
8865 imm_expr.X_add_number, true, mips16_small,
8866 mips16_ext, &ip->insn_opcode,
8867 &ip->use_extend, &ip->extend);
8868 imm_expr.X_op = O_absent;
8869 *imm_reloc = BFD_RELOC_UNUSED;
8883 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
8886 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
8902 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
8904 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
8931 while (ISDIGIT (*s));
8934 as_bad (_("invalid register number (%d)"), regno);
8940 if (s[1] == 'r' && s[2] == 'a')
8945 else if (s[1] == 'f' && s[2] == 'p')
8950 else if (s[1] == 's' && s[2] == 'p')
8955 else if (s[1] == 'g' && s[2] == 'p')
8960 else if (s[1] == 'a' && s[2] == 't')
8965 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
8970 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
8975 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
8988 if (c == 'v' || c == 'w')
8990 regno = mips16_to_32_reg_map[lastregno];
9004 regno = mips32_to_16_reg_map[regno];
9009 regno = ILLEGAL_REG;
9014 regno = ILLEGAL_REG;
9019 regno = ILLEGAL_REG;
9024 if (regno == AT && ! mips_opts.noat)
9025 as_warn (_("used $at without \".set noat\""));
9032 if (regno == ILLEGAL_REG)
9039 ip->insn_opcode |= regno << MIPS16OP_SH_RX;
9043 ip->insn_opcode |= regno << MIPS16OP_SH_RY;
9046 ip->insn_opcode |= regno << MIPS16OP_SH_RZ;
9049 ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z;
9055 ip->insn_opcode |= regno << MIPS16OP_SH_REGR32;
9058 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
9059 ip->insn_opcode |= regno << MIPS16OP_SH_REG32R;
9069 if (strncmp (s, "$pc", 3) == 0)
9093 && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0)
9095 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9096 and generate the appropriate reloc. If the text
9097 inside %gprel is not a symbol name with an
9098 optional offset, then we generate a normal reloc
9099 and will probably fail later. */
9100 my_getExpression (&imm_expr, s + sizeof "%gprel" - 1);
9101 if (imm_expr.X_op == O_symbol)
9104 *imm_reloc = BFD_RELOC_MIPS16_GPREL;
9106 ip->use_extend = true;
9113 /* Just pick up a normal expression. */
9114 my_getExpression (&imm_expr, s);
9117 if (imm_expr.X_op == O_register)
9119 /* What we thought was an expression turned out to
9122 if (s[0] == '(' && args[1] == '(')
9124 /* It looks like the expression was omitted
9125 before a register indirection, which means
9126 that the expression is implicitly zero. We
9127 still set up imm_expr, so that we handle
9128 explicit extensions correctly. */
9129 imm_expr.X_op = O_constant;
9130 imm_expr.X_add_number = 0;
9131 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9138 /* We need to relax this instruction. */
9139 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9148 /* We use offset_reloc rather than imm_reloc for the PC
9149 relative operands. This lets macros with both
9150 immediate and address operands work correctly. */
9151 my_getExpression (&offset_expr, s);
9153 if (offset_expr.X_op == O_register)
9156 /* We need to relax this instruction. */
9157 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
9161 case '6': /* break code */
9162 my_getExpression (&imm_expr, s);
9163 check_absolute_expr (ip, &imm_expr);
9164 if ((unsigned long) imm_expr.X_add_number > 63)
9166 as_warn (_("Invalid value for `%s' (%lu)"),
9168 (unsigned long) imm_expr.X_add_number);
9169 imm_expr.X_add_number &= 0x3f;
9171 ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6;
9172 imm_expr.X_op = O_absent;
9176 case 'a': /* 26 bit address */
9177 my_getExpression (&offset_expr, s);
9179 *offset_reloc = BFD_RELOC_MIPS16_JMP;
9180 ip->insn_opcode <<= 16;
9183 case 'l': /* register list for entry macro */
9184 case 'L': /* register list for exit macro */
9194 int freg, reg1, reg2;
9196 while (*s == ' ' || *s == ',')
9200 as_bad (_("can't parse register list"));
9212 while (ISDIGIT (*s))
9234 as_bad (_("invalid register list"));
9239 while (ISDIGIT (*s))
9246 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
9251 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
9256 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
9257 mask |= (reg2 - 3) << 3;
9258 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
9259 mask |= (reg2 - 15) << 1;
9260 else if (reg1 == RA && reg2 == RA)
9264 as_bad (_("invalid register list"));
9268 /* The mask is filled in in the opcode table for the
9269 benefit of the disassembler. We remove it before
9270 applying the actual mask. */
9271 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
9272 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
9276 case 'e': /* extend code */
9277 my_getExpression (&imm_expr, s);
9278 check_absolute_expr (ip, &imm_expr);
9279 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
9281 as_warn (_("Invalid value for `%s' (%lu)"),
9283 (unsigned long) imm_expr.X_add_number);
9284 imm_expr.X_add_number &= 0x7ff;
9286 ip->insn_opcode |= imm_expr.X_add_number;
9287 imm_expr.X_op = O_absent;
9297 /* Args don't match. */
9298 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
9299 strcmp (insn->name, insn[1].name) == 0)
9306 insn_error = _("illegal operands");
9312 /* This structure holds information we know about a mips16 immediate
9315 struct mips16_immed_operand
9317 /* The type code used in the argument string in the opcode table. */
9319 /* The number of bits in the short form of the opcode. */
9321 /* The number of bits in the extended form of the opcode. */
9323 /* The amount by which the short form is shifted when it is used;
9324 for example, the sw instruction has a shift count of 2. */
9326 /* The amount by which the short form is shifted when it is stored
9327 into the instruction code. */
9329 /* Non-zero if the short form is unsigned. */
9331 /* Non-zero if the extended form is unsigned. */
9333 /* Non-zero if the value is PC relative. */
9337 /* The mips16 immediate operand types. */
9339 static const struct mips16_immed_operand mips16_immed_operands[] =
9341 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9342 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9343 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9344 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9345 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
9346 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
9347 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
9348 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
9349 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
9350 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
9351 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
9352 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
9353 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
9354 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
9355 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
9356 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
9357 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9358 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9359 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
9360 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
9361 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
9364 #define MIPS16_NUM_IMMED \
9365 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9367 /* Handle a mips16 instruction with an immediate value. This or's the
9368 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9369 whether an extended value is needed; if one is needed, it sets
9370 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9371 If SMALL is true, an unextended opcode was explicitly requested.
9372 If EXT is true, an extended opcode was explicitly requested. If
9373 WARN is true, warn if EXT does not match reality. */
9376 mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend,
9385 unsigned long *insn;
9386 boolean *use_extend;
9387 unsigned short *extend;
9389 register const struct mips16_immed_operand *op;
9390 int mintiny, maxtiny;
9393 op = mips16_immed_operands;
9394 while (op->type != type)
9397 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
9402 if (type == '<' || type == '>' || type == '[' || type == ']')
9405 maxtiny = 1 << op->nbits;
9410 maxtiny = (1 << op->nbits) - 1;
9415 mintiny = - (1 << (op->nbits - 1));
9416 maxtiny = (1 << (op->nbits - 1)) - 1;
9419 /* Branch offsets have an implicit 0 in the lowest bit. */
9420 if (type == 'p' || type == 'q')
9423 if ((val & ((1 << op->shift) - 1)) != 0
9424 || val < (mintiny << op->shift)
9425 || val > (maxtiny << op->shift))
9430 if (warn && ext && ! needext)
9431 as_warn_where (file, line,
9432 _("extended operand requested but not required"));
9433 if (small && needext)
9434 as_bad_where (file, line, _("invalid unextended operand value"));
9436 if (small || (! ext && ! needext))
9440 *use_extend = false;
9441 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
9442 insnval <<= op->op_shift;
9447 long minext, maxext;
9453 maxext = (1 << op->extbits) - 1;
9457 minext = - (1 << (op->extbits - 1));
9458 maxext = (1 << (op->extbits - 1)) - 1;
9460 if (val < minext || val > maxext)
9461 as_bad_where (file, line,
9462 _("operand value out of range for instruction"));
9465 if (op->extbits == 16)
9467 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
9470 else if (op->extbits == 15)
9472 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
9477 extval = ((val & 0x1f) << 6) | (val & 0x20);
9481 *extend = (unsigned short) extval;
9486 static struct percent_op_match
9489 const enum small_ex_type type;
9494 {"%call_hi", S_EX_CALL_HI},
9495 {"%call_lo", S_EX_CALL_LO},
9496 {"%call16", S_EX_CALL16},
9497 {"%got_disp", S_EX_GOT_DISP},
9498 {"%got_page", S_EX_GOT_PAGE},
9499 {"%got_ofst", S_EX_GOT_OFST},
9500 {"%got_hi", S_EX_GOT_HI},
9501 {"%got_lo", S_EX_GOT_LO},
9503 {"%gp_rel", S_EX_GP_REL},
9504 {"%half", S_EX_HALF},
9505 {"%highest", S_EX_HIGHEST},
9506 {"%higher", S_EX_HIGHER},
9512 /* Parse small expression input. STR gets adjusted to eat up whitespace.
9513 It detects valid "%percent_op(...)" and "($reg)" strings. Percent_op's
9514 can be nested, this is handled by blanking the innermost, parsing the
9515 rest by subsequent calls. */
9518 my_getSmallParser (str, len, nestlevel)
9524 *str += strspn (*str, " \t");
9525 /* Check for expression in parentheses. */
9528 char *b = *str + 1 + strspn (*str + 1, " \t");
9531 /* Check for base register. */
9535 && (e = b + strcspn (b, ") \t"))
9536 && e - b > 1 && e - b < 4)
9539 && ((b[1] == 'f' && b[2] == 'p')
9540 || (b[1] == 's' && b[2] == 'p')
9541 || (b[1] == 'g' && b[2] == 'p')
9542 || (b[1] == 'a' && b[2] == 't')
9544 && ISDIGIT (b[2]))))
9545 || (ISDIGIT (b[1])))
9547 *len = strcspn (*str, ")") + 1;
9548 return S_EX_REGISTER;
9552 /* Check for percent_op (in parentheses). */
9553 else if (b[0] == '%')
9556 return my_getPercentOp (str, len, nestlevel);
9559 /* Some other expression in the parentheses, which can contain
9560 parentheses itself. Attempt to find the matching one. */
9566 for (s = *str + 1; *s && pcnt; s++, (*len)++)
9575 /* Check for percent_op (outside of parentheses). */
9576 else if (*str[0] == '%')
9577 return my_getPercentOp (str, len, nestlevel);
9579 /* Any other expression. */
9584 my_getPercentOp (str, len, nestlevel)
9589 char *tmp = *str + 1;
9592 while (ISALPHA (*tmp) || *tmp == '_')
9594 *tmp = TOLOWER (*tmp);
9597 while (i < (sizeof (percent_op) / sizeof (struct percent_op_match)))
9599 if (strncmp (*str, percent_op[i].str, strlen (percent_op[i].str)))
9603 int type = percent_op[i].type;
9605 /* Only %hi and %lo are allowed for OldABI. */
9606 if (! HAVE_NEWABI && type != S_EX_HI && type != S_EX_LO)
9609 *len = strlen (percent_op[i].str);
9618 my_getSmallExpression (ep, str)
9622 static char *oldstr = NULL;
9628 /* Don't update oldstr if the last call had nested percent_op's. We need
9629 it to parse the outer ones later. */
9636 c = my_getSmallParser (&str, &len, &nestlevel);
9637 if (c != S_EX_NONE && c != S_EX_REGISTER)
9640 while (c != S_EX_NONE && c != S_EX_REGISTER);
9644 /* A percent_op was encountered. Don't try to get an expression if
9645 it is already blanked out. */
9646 if (*(str + strspn (str + 1, " )")) != ')')
9650 /* Let my_getExpression() stop at the closing parenthesis. */
9651 save = *(str + len);
9652 *(str + len) = '\0';
9653 my_getExpression (ep, str);
9654 *(str + len) = save;
9658 /* Blank out including the % sign and the proper matching
9661 char *s = strrchr (oldstr, '%');
9664 for (end = strchr (s, '(') + 1; *end && pcnt; end++)
9668 else if (*end == ')')
9672 memset (s, ' ', end - s);
9676 expr_end = str + len;
9680 else if (c == S_EX_NONE)
9682 my_getExpression (ep, str);
9684 else if (c == S_EX_REGISTER)
9686 ep->X_op = O_constant;
9688 ep->X_add_symbol = NULL;
9689 ep->X_op_symbol = NULL;
9690 ep->X_add_number = 0;
9694 as_fatal (_("internal error"));
9698 /* All percent_op's have been handled. */
9705 my_getExpression (ep, str)
9712 save_in = input_line_pointer;
9713 input_line_pointer = str;
9715 expr_end = input_line_pointer;
9716 input_line_pointer = save_in;
9718 /* If we are in mips16 mode, and this is an expression based on `.',
9719 then we bump the value of the symbol by 1 since that is how other
9720 text symbols are handled. We don't bother to handle complex
9721 expressions, just `.' plus or minus a constant. */
9722 if (mips_opts.mips16
9723 && ep->X_op == O_symbol
9724 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
9725 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg
9726 && symbol_get_frag (ep->X_add_symbol) == frag_now
9727 && symbol_constant_p (ep->X_add_symbol)
9728 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
9729 S_SET_VALUE (ep->X_add_symbol, val + 1);
9732 /* Turn a string in input_line_pointer into a floating point constant
9733 of type TYPE, and store the appropriate bytes in *LITP. The number
9734 of LITTLENUMS emitted is stored in *SIZEP. An error message is
9735 returned, or NULL on OK. */
9738 md_atof (type, litP, sizeP)
9744 LITTLENUM_TYPE words[4];
9760 return _("bad call to md_atof");
9763 t = atof_ieee (input_line_pointer, type, words);
9765 input_line_pointer = t;
9769 if (! target_big_endian)
9771 for (i = prec - 1; i >= 0; i--)
9773 md_number_to_chars (litP, (valueT) words[i], 2);
9779 for (i = 0; i < prec; i++)
9781 md_number_to_chars (litP, (valueT) words[i], 2);
9790 md_number_to_chars (buf, val, n)
9795 if (target_big_endian)
9796 number_to_chars_bigendian (buf, val, n);
9798 number_to_chars_littleendian (buf, val, n);
9802 static int support_64bit_objects(void)
9804 const char **list, **l;
9806 list = bfd_target_list ();
9807 for (l = list; *l != NULL; l++)
9809 /* This is traditional mips */
9810 if (strcmp (*l, "elf64-tradbigmips") == 0
9811 || strcmp (*l, "elf64-tradlittlemips") == 0)
9813 if (strcmp (*l, "elf64-bigmips") == 0
9814 || strcmp (*l, "elf64-littlemips") == 0)
9818 return (*l != NULL);
9820 #endif /* OBJ_ELF */
9822 CONST char *md_shortopts = "nO::g::G:";
9824 struct option md_longopts[] =
9826 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
9827 {"mips0", no_argument, NULL, OPTION_MIPS1},
9828 {"mips1", no_argument, NULL, OPTION_MIPS1},
9829 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
9830 {"mips2", no_argument, NULL, OPTION_MIPS2},
9831 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
9832 {"mips3", no_argument, NULL, OPTION_MIPS3},
9833 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
9834 {"mips4", no_argument, NULL, OPTION_MIPS4},
9835 #define OPTION_MIPS5 (OPTION_MD_BASE + 5)
9836 {"mips5", no_argument, NULL, OPTION_MIPS5},
9837 #define OPTION_MIPS32 (OPTION_MD_BASE + 6)
9838 {"mips32", no_argument, NULL, OPTION_MIPS32},
9839 #define OPTION_MIPS64 (OPTION_MD_BASE + 7)
9840 {"mips64", no_argument, NULL, OPTION_MIPS64},
9841 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 8)
9842 {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC},
9843 #define OPTION_TRAP (OPTION_MD_BASE + 9)
9844 {"trap", no_argument, NULL, OPTION_TRAP},
9845 {"no-break", no_argument, NULL, OPTION_TRAP},
9846 #define OPTION_BREAK (OPTION_MD_BASE + 10)
9847 {"break", no_argument, NULL, OPTION_BREAK},
9848 {"no-trap", no_argument, NULL, OPTION_BREAK},
9849 #define OPTION_EB (OPTION_MD_BASE + 11)
9850 {"EB", no_argument, NULL, OPTION_EB},
9851 #define OPTION_EL (OPTION_MD_BASE + 12)
9852 {"EL", no_argument, NULL, OPTION_EL},
9853 #define OPTION_MIPS16 (OPTION_MD_BASE + 13)
9854 {"mips16", no_argument, NULL, OPTION_MIPS16},
9855 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 14)
9856 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
9857 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 15)
9858 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
9859 #define OPTION_MNO_7000_HILO_FIX (OPTION_MD_BASE + 16)
9860 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
9861 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
9862 #define OPTION_FP32 (OPTION_MD_BASE + 17)
9863 {"mfp32", no_argument, NULL, OPTION_FP32},
9864 #define OPTION_GP32 (OPTION_MD_BASE + 18)
9865 {"mgp32", no_argument, NULL, OPTION_GP32},
9866 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 19)
9867 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
9868 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 20)
9869 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
9870 #define OPTION_MARCH (OPTION_MD_BASE + 21)
9871 {"march", required_argument, NULL, OPTION_MARCH},
9872 #define OPTION_MTUNE (OPTION_MD_BASE + 22)
9873 {"mtune", required_argument, NULL, OPTION_MTUNE},
9874 #define OPTION_MCPU (OPTION_MD_BASE + 23)
9875 {"mcpu", required_argument, NULL, OPTION_MCPU},
9876 #define OPTION_M4650 (OPTION_MD_BASE + 24)
9877 {"m4650", no_argument, NULL, OPTION_M4650},
9878 #define OPTION_NO_M4650 (OPTION_MD_BASE + 25)
9879 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
9880 #define OPTION_M4010 (OPTION_MD_BASE + 26)
9881 {"m4010", no_argument, NULL, OPTION_M4010},
9882 #define OPTION_NO_M4010 (OPTION_MD_BASE + 27)
9883 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
9884 #define OPTION_M4100 (OPTION_MD_BASE + 28)
9885 {"m4100", no_argument, NULL, OPTION_M4100},
9886 #define OPTION_NO_M4100 (OPTION_MD_BASE + 29)
9887 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
9888 #define OPTION_M3900 (OPTION_MD_BASE + 30)
9889 {"m3900", no_argument, NULL, OPTION_M3900},
9890 #define OPTION_NO_M3900 (OPTION_MD_BASE + 31)
9891 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
9892 #define OPTION_GP64 (OPTION_MD_BASE + 32)
9893 {"mgp64", no_argument, NULL, OPTION_GP64},
9894 #define OPTION_MIPS3D (OPTION_MD_BASE + 33)
9895 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
9896 #define OPTION_NO_MIPS3D (OPTION_MD_BASE + 34)
9897 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
9898 #define OPTION_MDMX (OPTION_MD_BASE + 35)
9899 {"mdmx", no_argument, NULL, OPTION_MDMX},
9900 #define OPTION_NO_MDMX (OPTION_MD_BASE + 36)
9901 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
9903 #define OPTION_ELF_BASE (OPTION_MD_BASE + 37)
9904 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
9905 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
9906 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
9907 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
9908 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
9909 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
9910 {"xgot", no_argument, NULL, OPTION_XGOT},
9911 #define OPTION_MABI (OPTION_ELF_BASE + 3)
9912 {"mabi", required_argument, NULL, OPTION_MABI},
9913 #define OPTION_32 (OPTION_ELF_BASE + 4)
9914 {"32", no_argument, NULL, OPTION_32},
9915 #define OPTION_N32 (OPTION_ELF_BASE + 5)
9916 {"n32", no_argument, NULL, OPTION_N32},
9917 #define OPTION_64 (OPTION_ELF_BASE + 6)
9918 {"64", no_argument, NULL, OPTION_64},
9919 #endif /* OBJ_ELF */
9920 {NULL, no_argument, NULL, 0}
9922 size_t md_longopts_size = sizeof (md_longopts);
9925 md_parse_option (c, arg)
9931 case OPTION_CONSTRUCT_FLOATS:
9932 mips_disable_float_construction = 0;
9935 case OPTION_NO_CONSTRUCT_FLOATS:
9936 mips_disable_float_construction = 1;
9948 target_big_endian = 1;
9952 target_big_endian = 0;
9960 if (arg && arg[1] == '0')
9970 mips_debug = atoi (arg);
9971 /* When the MIPS assembler sees -g or -g2, it does not do
9972 optimizations which limit full symbolic debugging. We take
9973 that to be equivalent to -O0. */
9974 if (mips_debug == 2)
9979 mips_opts.isa = ISA_MIPS1;
9983 mips_opts.isa = ISA_MIPS2;
9987 mips_opts.isa = ISA_MIPS3;
9991 mips_opts.isa = ISA_MIPS4;
9995 mips_opts.isa = ISA_MIPS5;
9999 mips_opts.isa = ISA_MIPS32;
10002 case OPTION_MIPS64:
10003 mips_opts.isa = ISA_MIPS64;
10010 int cpu = CPU_UNKNOWN;
10012 /* Identify the processor type. */
10013 if (strcasecmp (arg, "default") != 0)
10015 const struct mips_cpu_info *ci;
10017 ci = mips_cpu_info_from_name (arg);
10018 if (ci == NULL || ci->is_isa)
10023 as_fatal (_("invalid architecture -mtune=%s"), arg);
10026 as_fatal (_("invalid architecture -march=%s"), arg);
10029 as_fatal (_("invalid architecture -mcpu=%s"), arg);
10040 if (mips_tune != CPU_UNKNOWN && mips_tune != cpu)
10041 as_warn (_("A different -mtune= was already specified, is now "
10042 "-mtune=%s"), arg);
10046 if (mips_arch != CPU_UNKNOWN && mips_arch != cpu)
10047 as_warn (_("A different -march= was already specified, is now "
10048 "-march=%s"), arg);
10052 if (mips_cpu != CPU_UNKNOWN && mips_cpu != cpu)
10053 as_warn (_("A different -mcpu= was already specified, is now "
10061 if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R4650)
10062 || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R4650))
10063 as_warn (_("A different -march= or -mtune= was already specified, "
10065 mips_arch = CPU_R4650;
10066 mips_tune = CPU_R4650;
10069 case OPTION_NO_M4650:
10073 if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R4010)
10074 || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R4010))
10075 as_warn (_("A different -march= or -mtune= was already specified, "
10077 mips_arch = CPU_R4010;
10078 mips_tune = CPU_R4010;
10081 case OPTION_NO_M4010:
10085 if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_VR4100)
10086 || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_VR4100))
10087 as_warn (_("A different -march= or -mtune= was already specified, "
10089 mips_arch = CPU_VR4100;
10090 mips_tune = CPU_VR4100;
10093 case OPTION_NO_M4100:
10097 if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R3900)
10098 || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R3900))
10099 as_warn (_("A different -march= or -mtune= was already specified, "
10101 mips_arch = CPU_R3900;
10102 mips_tune = CPU_R3900;
10105 case OPTION_NO_M3900:
10109 mips_opts.ase_mdmx = 1;
10112 case OPTION_NO_MDMX:
10113 mips_opts.ase_mdmx = 0;
10116 case OPTION_MIPS16:
10117 mips_opts.mips16 = 1;
10118 mips_no_prev_insn (false);
10121 case OPTION_NO_MIPS16:
10122 mips_opts.mips16 = 0;
10123 mips_no_prev_insn (false);
10126 case OPTION_MIPS3D:
10127 mips_opts.ase_mips3d = 1;
10130 case OPTION_NO_MIPS3D:
10131 mips_opts.ase_mips3d = 0;
10134 case OPTION_MEMBEDDED_PIC:
10135 mips_pic = EMBEDDED_PIC;
10136 if (USE_GLOBAL_POINTER_OPT && g_switch_seen)
10138 as_bad (_("-G may not be used with embedded PIC code"));
10141 g_switch_value = 0x7fffffff;
10145 /* When generating ELF code, we permit -KPIC and -call_shared to
10146 select SVR4_PIC, and -non_shared to select no PIC. This is
10147 intended to be compatible with Irix 5. */
10148 case OPTION_CALL_SHARED:
10149 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10151 as_bad (_("-call_shared is supported only for ELF format"));
10154 mips_pic = SVR4_PIC;
10155 if (g_switch_seen && g_switch_value != 0)
10157 as_bad (_("-G may not be used with SVR4 PIC code"));
10160 g_switch_value = 0;
10163 case OPTION_NON_SHARED:
10164 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10166 as_bad (_("-non_shared is supported only for ELF format"));
10172 /* The -xgot option tells the assembler to use 32 offsets when
10173 accessing the got in SVR4_PIC mode. It is for Irix
10178 #endif /* OBJ_ELF */
10181 if (! USE_GLOBAL_POINTER_OPT)
10183 as_bad (_("-G is not supported for this configuration"));
10186 else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC)
10188 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
10192 g_switch_value = atoi (arg);
10197 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10200 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10202 as_bad (_("-32 is supported for ELF format only"));
10205 mips_opts.abi = O32_ABI;
10209 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10211 as_bad (_("-n32 is supported for ELF format only"));
10214 mips_opts.abi = N32_ABI;
10218 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10220 as_bad (_("-64 is supported for ELF format only"));
10223 mips_opts.abi = N64_ABI;
10224 if (! support_64bit_objects())
10225 as_fatal (_("No compiled in support for 64 bit object file format"));
10227 #endif /* OBJ_ELF */
10230 file_mips_gp32 = 1;
10231 if (mips_opts.abi != O32_ABI)
10232 mips_opts.abi = NO_ABI;
10236 file_mips_gp32 = 0;
10237 if (mips_opts.abi == O32_ABI)
10238 mips_opts.abi = NO_ABI;
10242 file_mips_fp32 = 1;
10243 if (mips_opts.abi != O32_ABI)
10244 mips_opts.abi = NO_ABI;
10249 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10251 as_bad (_("-mabi is supported for ELF format only"));
10254 if (strcmp (arg, "32") == 0)
10255 mips_opts.abi = O32_ABI;
10256 else if (strcmp (arg, "o64") == 0)
10257 mips_opts.abi = O64_ABI;
10258 else if (strcmp (arg, "n32") == 0)
10259 mips_opts.abi = N32_ABI;
10260 else if (strcmp (arg, "64") == 0)
10262 mips_opts.abi = N64_ABI;
10263 if (! support_64bit_objects())
10264 as_fatal (_("No compiled in support for 64 bit object file "
10267 else if (strcmp (arg, "eabi") == 0)
10268 mips_opts.abi = EABI_ABI;
10271 as_fatal (_("invalid abi -mabi=%s"), arg);
10275 #endif /* OBJ_ELF */
10277 case OPTION_M7000_HILO_FIX:
10278 mips_7000_hilo_fix = true;
10281 case OPTION_MNO_7000_HILO_FIX:
10282 mips_7000_hilo_fix = false;
10293 show (stream, string, col_p, first_p)
10301 fprintf (stream, "%24s", "");
10306 fprintf (stream, ", ");
10310 if (*col_p + strlen (string) > 72)
10312 fprintf (stream, "\n%24s", "");
10316 fprintf (stream, "%s", string);
10317 *col_p += strlen (string);
10323 md_show_usage (stream)
10328 fprintf (stream, _("\
10330 -membedded-pic generate embedded position independent code\n\
10331 -EB generate big endian output\n\
10332 -EL generate little endian output\n\
10333 -g, -g2 do not remove unneeded NOPs or swap branches\n\
10334 -G NUM allow referencing objects up to NUM bytes\n\
10335 implicitly with the gp register [default 8]\n"));
10336 fprintf (stream, _("\
10337 -mips1 generate MIPS ISA I instructions\n\
10338 -mips2 generate MIPS ISA II instructions\n\
10339 -mips3 generate MIPS ISA III instructions\n\
10340 -mips4 generate MIPS ISA IV instructions\n\
10341 -mips5 generate MIPS ISA V instructions\n\
10342 -mips32 generate MIPS32 ISA instructions\n\
10343 -mips64 generate MIPS64 ISA instructions\n\
10344 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
10348 show (stream, "2000", &column, &first);
10349 show (stream, "3000", &column, &first);
10350 show (stream, "3900", &column, &first);
10351 show (stream, "4000", &column, &first);
10352 show (stream, "4010", &column, &first);
10353 show (stream, "4100", &column, &first);
10354 show (stream, "4111", &column, &first);
10355 show (stream, "4300", &column, &first);
10356 show (stream, "4400", &column, &first);
10357 show (stream, "4600", &column, &first);
10358 show (stream, "4650", &column, &first);
10359 show (stream, "5000", &column, &first);
10360 show (stream, "5200", &column, &first);
10361 show (stream, "5230", &column, &first);
10362 show (stream, "5231", &column, &first);
10363 show (stream, "5261", &column, &first);
10364 show (stream, "5721", &column, &first);
10365 show (stream, "6000", &column, &first);
10366 show (stream, "8000", &column, &first);
10367 show (stream, "10000", &column, &first);
10368 show (stream, "12000", &column, &first);
10369 show (stream, "sb1", &column, &first);
10370 fputc ('\n', stream);
10372 fprintf (stream, _("\
10373 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
10374 -no-mCPU don't generate code specific to CPU.\n\
10375 For -mCPU and -no-mCPU, CPU must be one of:\n"));
10379 show (stream, "3900", &column, &first);
10380 show (stream, "4010", &column, &first);
10381 show (stream, "4100", &column, &first);
10382 show (stream, "4650", &column, &first);
10383 fputc ('\n', stream);
10385 fprintf (stream, _("\
10386 -mips16 generate mips16 instructions\n\
10387 -no-mips16 do not generate mips16 instructions\n"));
10388 fprintf (stream, _("\
10389 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
10390 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
10391 -O0 remove unneeded NOPs, do not swap branches\n\
10392 -O remove unneeded NOPs and swap branches\n\
10393 -n warn about NOPs generated from macros\n\
10394 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
10395 --trap, --no-break trap exception on div by 0 and mult overflow\n\
10396 --break, --no-trap break exception on div by 0 and mult overflow\n"));
10398 fprintf (stream, _("\
10399 -KPIC, -call_shared generate SVR4 position independent code\n\
10400 -non_shared do not generate position independent code\n\
10401 -xgot assume a 32 bit GOT\n\
10402 -mabi=ABI create ABI conformant object file for:\n"));
10406 show (stream, "32", &column, &first);
10407 show (stream, "o64", &column, &first);
10408 show (stream, "n32", &column, &first);
10409 show (stream, "64", &column, &first);
10410 show (stream, "eabi", &column, &first);
10412 fputc ('\n', stream);
10414 fprintf (stream, _("\
10415 -32 create o32 ABI object file (default)\n\
10416 -n32 create n32 ABI object file\n\
10417 -64 create 64 ABI object file\n"));
10422 mips_after_parse_args ()
10426 int mips_isa_from_cpu;
10427 const struct mips_cpu_info *ci;
10429 /* GP relative stuff not working for PE */
10430 if (strncmp (TARGET_OS, "pe", 2) == 0
10431 && g_switch_value != 0)
10434 as_bad (_("-G not supported in this configuration."));
10435 g_switch_value = 0;
10439 if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0)
10441 a = xmalloc (sizeof TARGET_CPU);
10442 strcpy (a, TARGET_CPU);
10443 a[(sizeof TARGET_CPU) - 3] = '\0';
10447 /* Backward compatibility for historic -mcpu= option. Check for
10448 incompatible options, warn if -mcpu is used. */
10449 if (mips_cpu != CPU_UNKNOWN
10450 && mips_arch != CPU_UNKNOWN
10451 && mips_cpu != mips_arch)
10453 as_fatal (_("The -mcpu option can't be used together with -march. "
10454 "Use -mtune instead of -mcpu."));
10457 if (mips_cpu != CPU_UNKNOWN
10458 && mips_tune != CPU_UNKNOWN
10459 && mips_cpu != mips_tune)
10461 as_fatal (_("The -mcpu option can't be used together with -mtune. "
10462 "Use -march instead of -mcpu."));
10466 /* For backward compatibility, let -mipsN set various defaults. */
10467 /* This code should go away, to be replaced with something rather more
10468 draconian. Until GCC 3.1 has been released for some reasonable
10469 amount of time, however, we need to support this. */
10470 if (mips_opts.isa != ISA_UNKNOWN)
10472 /* Translate -mipsN to the appropriate settings of file_mips_gp32
10473 and file_mips_fp32. Tag binaries as using the mipsN ISA. */
10474 if (file_mips_gp32 < 0)
10476 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
10477 file_mips_gp32 = 0;
10479 file_mips_gp32 = 1;
10481 if (file_mips_fp32 < 0)
10483 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
10484 file_mips_fp32 = 0;
10486 file_mips_fp32 = 1;
10489 ci = mips_cpu_info_from_isa (mips_opts.isa);
10490 assert (ci != NULL);
10491 /* -mipsN has higher priority than -mcpu but lower than -march. */
10492 if (mips_arch == CPU_UNKNOWN)
10493 mips_arch = ci->cpu;
10495 /* Default mips_abi. */
10496 if (mips_opts.abi == NO_ABI)
10498 if (mips_opts.isa == ISA_MIPS1 || mips_opts.isa == ISA_MIPS2)
10499 mips_opts.abi = O32_ABI;
10500 else if (mips_opts.isa == ISA_MIPS3 || mips_opts.isa == ISA_MIPS4)
10501 mips_opts.abi = O64_ABI;
10505 if (mips_arch == CPU_UNKNOWN && mips_cpu != CPU_UNKNOWN)
10507 ci = mips_cpu_info_from_cpu (mips_cpu);
10508 assert (ci != NULL);
10509 mips_arch = ci->cpu;
10510 as_warn (_("The -mcpu option is deprecated. Please use -march and "
10511 "-mtune instead."));
10514 /* Set tune from -mcpu, not from -mipsN. */
10515 if (mips_tune == CPU_UNKNOWN && mips_cpu != CPU_UNKNOWN)
10517 ci = mips_cpu_info_from_cpu (mips_cpu);
10518 assert (ci != NULL);
10519 mips_tune = ci->cpu;
10522 /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was
10523 specified on the command line, or some other value if one was.
10524 Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on
10525 the command line, or will be set otherwise if one was. */
10527 if (mips_arch != CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN)
10528 /* Handled above. */;
10530 if (mips_arch == CPU_UNKNOWN && mips_cpu != CPU_UNKNOWN)
10532 ci = mips_cpu_info_from_cpu (mips_cpu);
10533 assert (ci != NULL);
10534 mips_arch = ci->cpu;
10535 as_warn (_("The -mcpu option is deprecated. Please use -march and "
10536 "-mtune instead."));
10539 /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was
10540 specified on the command line, or some other value if one was.
10541 Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on
10542 the command line, or will be set otherwise if one was. */
10544 if (mips_arch != CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN)
10546 /* We have to check if the isa is the default isa of arch. Otherwise
10547 we'll get invalid object file headers. */
10548 ci = mips_cpu_info_from_cpu (mips_arch);
10549 assert (ci != NULL);
10550 if (mips_opts.isa != ci->isa)
10552 /* This really should be an error instead of a warning, but old
10553 compilers only have -mcpu which sets both arch and tune. For
10554 now, we discard arch and preserve tune. */
10555 as_warn (_("The -march option is incompatible to -mipsN and "
10556 "therefore ignored."));
10557 if (mips_tune == CPU_UNKNOWN)
10558 mips_tune = mips_arch;
10559 ci = mips_cpu_info_from_isa (mips_opts.isa);
10560 assert (ci != NULL);
10561 mips_arch = ci->cpu;
10565 else if (mips_arch != CPU_UNKNOWN && mips_opts.isa == ISA_UNKNOWN)
10567 /* We have ARCH, we need ISA. */
10568 ci = mips_cpu_info_from_cpu (mips_arch);
10569 assert (ci != NULL);
10570 mips_opts.isa = ci->isa;
10572 else if (mips_arch == CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN)
10574 /* We have ISA, we need default ARCH. */
10575 ci = mips_cpu_info_from_isa (mips_opts.isa);
10576 assert (ci != NULL);
10577 mips_arch = ci->cpu;
10581 /* We need to set both ISA and ARCH from target cpu. */
10582 ci = mips_cpu_info_from_name (cpu);
10584 ci = mips_cpu_info_from_cpu (CPU_R3000);
10585 assert (ci != NULL);
10586 mips_opts.isa = ci->isa;
10587 mips_arch = ci->cpu;
10590 if (mips_tune == CPU_UNKNOWN)
10591 mips_tune = mips_arch;
10593 ci = mips_cpu_info_from_cpu (mips_arch);
10594 assert (ci != NULL);
10595 mips_isa_from_cpu = ci->isa;
10597 /* End of TARGET_CPU processing, get rid of malloced memory
10606 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
10607 as_bad (_("trap exception not supported at ISA 1"));
10609 /* If they asked for mips1 or mips2 and a cpu that is
10610 mips3 or greater, then mark the object file 32BITMODE. */
10611 if (mips_isa_from_cpu != ISA_UNKNOWN
10612 && ! ISA_HAS_64BIT_REGS (mips_opts.isa)
10613 && ISA_HAS_64BIT_REGS (mips_isa_from_cpu))
10614 mips_32bitmode = 1;
10616 /* If the selected architecture includes support for ASEs, enable
10617 generation of code for them. */
10618 if (mips_opts.mips16 == -1)
10619 mips_opts.mips16 = (CPU_HAS_MIPS16 (mips_arch)) ? 1 : 0;
10620 if (mips_opts.ase_mips3d == -1)
10621 mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (mips_arch)) ? 1 : 0;
10622 if (mips_opts.ase_mdmx == -1)
10623 mips_opts.ase_mdmx = (CPU_HAS_MDMX (mips_arch)) ? 1 : 0;
10625 if (file_mips_gp32 < 0)
10626 file_mips_gp32 = 0;
10627 if (file_mips_fp32 < 0)
10628 file_mips_fp32 = 0;
10630 file_mips_isa = mips_opts.isa;
10631 file_mips_abi = mips_opts.abi;
10632 file_ase_mips16 = mips_opts.mips16;
10633 file_ase_mips3d = mips_opts.ase_mips3d;
10634 file_ase_mdmx = mips_opts.ase_mdmx;
10635 mips_opts.gp32 = file_mips_gp32;
10636 mips_opts.fp32 = file_mips_fp32;
10643 mips_init_after_args ()
10645 /* initialize opcodes */
10646 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
10647 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
10651 md_pcrel_from (fixP)
10654 if (OUTPUT_FLAVOR != bfd_target_aout_flavour
10655 && fixP->fx_addsy != (symbolS *) NULL
10656 && ! S_IS_DEFINED (fixP->fx_addsy))
10658 /* This makes a branch to an undefined symbol be a branch to the
10659 current location. */
10660 if (mips_pic == EMBEDDED_PIC)
10666 /* Return the address of the delay slot. */
10667 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10670 /* This is called before the symbol table is processed. In order to
10671 work with gcc when using mips-tfile, we must keep all local labels.
10672 However, in other cases, we want to discard them. If we were
10673 called with -g, but we didn't see any debugging information, it may
10674 mean that gcc is smuggling debugging information through to
10675 mips-tfile, in which case we must generate all local labels. */
10678 mips_frob_file_before_adjust ()
10680 #ifndef NO_ECOFF_DEBUGGING
10681 if (ECOFF_DEBUGGING
10683 && ! ecoff_debugging_seen)
10684 flag_keep_locals = 1;
10688 /* Sort any unmatched HI16_S relocs so that they immediately precede
10689 the corresponding LO reloc. This is called before md_apply_fix3 and
10690 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10691 explicit use of the %hi modifier. */
10696 struct mips_hi_fixup *l;
10698 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
10700 segment_info_type *seginfo;
10703 assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S);
10705 /* Check quickly whether the next fixup happens to be a matching
10707 if (l->fixp->fx_next != NULL
10708 && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16
10709 && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
10710 && l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
10713 /* Look through the fixups for this segment for a matching %lo.
10714 When we find one, move the %hi just in front of it. We do
10715 this in two passes. In the first pass, we try to find a
10716 unique %lo. In the second pass, we permit multiple %hi
10717 relocs for a single %lo (this is a GNU extension). */
10718 seginfo = seg_info (l->seg);
10719 for (pass = 0; pass < 2; pass++)
10724 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
10726 /* Check whether this is a %lo fixup which matches l->fixp. */
10727 if (f->fx_r_type == BFD_RELOC_LO16
10728 && f->fx_addsy == l->fixp->fx_addsy
10729 && f->fx_offset == l->fixp->fx_offset
10732 || prev->fx_r_type != BFD_RELOC_HI16_S
10733 || prev->fx_addsy != f->fx_addsy
10734 || prev->fx_offset != f->fx_offset))
10738 /* Move l->fixp before f. */
10739 for (pf = &seginfo->fix_root;
10741 pf = &(*pf)->fx_next)
10742 assert (*pf != NULL);
10744 *pf = l->fixp->fx_next;
10746 l->fixp->fx_next = f;
10748 seginfo->fix_root = l->fixp;
10750 prev->fx_next = l->fixp;
10761 #if 0 /* GCC code motion plus incomplete dead code elimination
10762 can leave a %hi without a %lo. */
10764 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
10765 _("Unmatched %%hi reloc"));
10771 /* When generating embedded PIC code we need to use a special
10772 relocation to represent the difference of two symbols in the .text
10773 section (switch tables use a difference of this sort). See
10774 include/coff/mips.h for details. This macro checks whether this
10775 fixup requires the special reloc. */
10776 #define SWITCH_TABLE(fixp) \
10777 ((fixp)->fx_r_type == BFD_RELOC_32 \
10778 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
10779 && (fixp)->fx_addsy != NULL \
10780 && (fixp)->fx_subsy != NULL \
10781 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
10782 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
10784 /* When generating embedded PIC code we must keep all PC relative
10785 relocations, in case the linker has to relax a call. We also need
10786 to keep relocations for switch table entries.
10788 We may have combined relocations without symbols in the N32/N64 ABI.
10789 We have to prevent gas from dropping them. */
10792 mips_force_relocation (fixp)
10795 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
10796 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10800 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
10801 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
10802 || fixp->fx_r_type == BFD_RELOC_HI16_S
10803 || fixp->fx_r_type == BFD_RELOC_LO16))
10806 return (mips_pic == EMBEDDED_PIC
10808 || SWITCH_TABLE (fixp)
10809 || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S
10810 || fixp->fx_r_type == BFD_RELOC_PCREL_LO16));
10815 mips_need_elf_addend_fixup (fixP)
10818 if (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16)
10820 if (mips_pic == EMBEDDED_PIC
10821 && S_IS_WEAK (fixP->fx_addsy))
10823 if (mips_pic != EMBEDDED_PIC
10824 && (S_IS_WEAK (fixP->fx_addsy)
10825 || S_IS_EXTERN (fixP->fx_addsy))
10826 && !S_IS_COMMON (fixP->fx_addsy))
10828 if (symbol_used_in_reloc_p (fixP->fx_addsy)
10829 && (((bfd_get_section_flags (stdoutput,
10830 S_GET_SEGMENT (fixP->fx_addsy))
10831 & SEC_LINK_ONCE) != 0)
10832 || !strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)),
10834 sizeof (".gnu.linkonce") - 1)))
10840 /* Apply a fixup to the object file. */
10843 md_apply_fix3 (fixP, valP, seg)
10846 segT seg ATTRIBUTE_UNUSED;
10852 assert (fixP->fx_size == 4
10853 || fixP->fx_r_type == BFD_RELOC_16
10854 || fixP->fx_r_type == BFD_RELOC_32
10855 || fixP->fx_r_type == BFD_RELOC_MIPS_JMP
10856 || fixP->fx_r_type == BFD_RELOC_HI16_S
10857 || fixP->fx_r_type == BFD_RELOC_LO16
10858 || fixP->fx_r_type == BFD_RELOC_GPREL16
10859 || fixP->fx_r_type == BFD_RELOC_MIPS_LITERAL
10860 || fixP->fx_r_type == BFD_RELOC_GPREL32
10861 || fixP->fx_r_type == BFD_RELOC_64
10862 || fixP->fx_r_type == BFD_RELOC_CTOR
10863 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
10864 || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHEST
10865 || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHER
10866 || fixP->fx_r_type == BFD_RELOC_MIPS_SCN_DISP
10867 || fixP->fx_r_type == BFD_RELOC_MIPS_REL16
10868 || fixP->fx_r_type == BFD_RELOC_MIPS_RELGOT
10869 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
10870 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
10871 || fixP->fx_r_type == BFD_RELOC_MIPS_JALR);
10875 /* If we aren't adjusting this fixup to be against the section
10876 symbol, we need to adjust the value. */
10878 if (fixP->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour)
10880 if (mips_need_elf_addend_fixup (fixP))
10882 valueT symval = S_GET_VALUE (fixP->fx_addsy);
10885 if (value != 0 && ! fixP->fx_pcrel)
10887 /* In this case, the bfd_install_relocation routine will
10888 incorrectly add the symbol value back in. We just want
10889 the addend to appear in the object file. */
10892 /* Make sure the addend is still non-zero. If it became zero
10893 after the last operation, set it to a spurious value and
10894 subtract the same value from the object file's contents. */
10899 /* The in-place addends for LO16 relocations are signed;
10900 leave the matching HI16 in-place addends as zero. */
10901 if (fixP->fx_r_type != BFD_RELOC_HI16_S)
10903 reloc_howto_type *howto;
10904 bfd_vma contents, mask, field;
10906 howto = bfd_reloc_type_lookup (stdoutput,
10909 contents = bfd_get_bits (fixP->fx_frag->fr_literal
10912 target_big_endian);
10914 /* MASK has bits set where the relocation should go.
10915 FIELD is -value, shifted into the appropriate place
10916 for this relocation. */
10917 mask = 1 << (howto->bitsize - 1);
10918 mask = (((mask - 1) << 1) | 1) << howto->bitpos;
10919 field = (-value >> howto->rightshift) << howto->bitpos;
10921 bfd_put_bits ((field & mask) | (contents & ~mask),
10922 fixP->fx_frag->fr_literal + fixP->fx_where,
10924 target_big_endian);
10930 /* This code was generated using trial and error and so is
10931 fragile and not trustworthy. If you change it, you should
10932 rerun the elf-rel, elf-rel2, and empic testcases and ensure
10933 they still pass. */
10934 if (fixP->fx_pcrel || fixP->fx_subsy != NULL)
10936 value += fixP->fx_frag->fr_address + fixP->fx_where;
10938 /* BFD's REL handling, for MIPS, is _very_ weird.
10939 This gives the right results, but it can't possibly
10940 be the way things are supposed to work. */
10941 if ((fixP->fx_r_type != BFD_RELOC_16_PCREL
10942 && fixP->fx_r_type != BFD_RELOC_16_PCREL_S2)
10943 || S_GET_SEGMENT (fixP->fx_addsy) != undefined_section)
10944 value += fixP->fx_frag->fr_address + fixP->fx_where;
10949 fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc. */
10951 if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel)
10954 switch (fixP->fx_r_type)
10956 case BFD_RELOC_MIPS_JMP:
10957 case BFD_RELOC_MIPS_SHIFT5:
10958 case BFD_RELOC_MIPS_SHIFT6:
10959 case BFD_RELOC_MIPS_GOT_DISP:
10960 case BFD_RELOC_MIPS_GOT_PAGE:
10961 case BFD_RELOC_MIPS_GOT_OFST:
10962 case BFD_RELOC_MIPS_SUB:
10963 case BFD_RELOC_MIPS_INSERT_A:
10964 case BFD_RELOC_MIPS_INSERT_B:
10965 case BFD_RELOC_MIPS_DELETE:
10966 case BFD_RELOC_MIPS_HIGHEST:
10967 case BFD_RELOC_MIPS_HIGHER:
10968 case BFD_RELOC_MIPS_SCN_DISP:
10969 case BFD_RELOC_MIPS_REL16:
10970 case BFD_RELOC_MIPS_RELGOT:
10971 case BFD_RELOC_MIPS_JALR:
10972 case BFD_RELOC_HI16:
10973 case BFD_RELOC_HI16_S:
10974 case BFD_RELOC_GPREL16:
10975 case BFD_RELOC_MIPS_LITERAL:
10976 case BFD_RELOC_MIPS_CALL16:
10977 case BFD_RELOC_MIPS_GOT16:
10978 case BFD_RELOC_GPREL32:
10979 case BFD_RELOC_MIPS_GOT_HI16:
10980 case BFD_RELOC_MIPS_GOT_LO16:
10981 case BFD_RELOC_MIPS_CALL_HI16:
10982 case BFD_RELOC_MIPS_CALL_LO16:
10983 case BFD_RELOC_MIPS16_GPREL:
10984 if (fixP->fx_pcrel)
10985 as_bad_where (fixP->fx_file, fixP->fx_line,
10986 _("Invalid PC relative reloc"));
10987 /* Nothing needed to do. The value comes from the reloc entry */
10990 case BFD_RELOC_MIPS16_JMP:
10991 /* We currently always generate a reloc against a symbol, which
10992 means that we don't want an addend even if the symbol is
10994 fixP->fx_addnumber = 0;
10997 case BFD_RELOC_PCREL_HI16_S:
10998 /* The addend for this is tricky if it is internal, so we just
10999 do everything here rather than in bfd_install_relocation. */
11000 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
11005 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
11007 /* For an external symbol adjust by the address to make it
11008 pcrel_offset. We use the address of the RELLO reloc
11009 which follows this one. */
11010 value += (fixP->fx_next->fx_frag->fr_address
11011 + fixP->fx_next->fx_where);
11013 value = ((value + 0x8000) >> 16) & 0xffff;
11014 buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where;
11015 if (target_big_endian)
11017 md_number_to_chars ((char *) buf, value, 2);
11020 case BFD_RELOC_PCREL_LO16:
11021 /* The addend for this is tricky if it is internal, so we just
11022 do everything here rather than in bfd_install_relocation. */
11023 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
11028 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
11029 value += fixP->fx_frag->fr_address + fixP->fx_where;
11030 buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where;
11031 if (target_big_endian)
11033 md_number_to_chars ((char *) buf, value, 2);
11037 /* This is handled like BFD_RELOC_32, but we output a sign
11038 extended value if we are only 32 bits. */
11040 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
11042 if (8 <= sizeof (valueT))
11043 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
11050 w1 = w2 = fixP->fx_where;
11051 if (target_big_endian)
11055 md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4);
11056 if ((value & 0x80000000) != 0)
11060 md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4);
11065 case BFD_RELOC_RVA:
11067 /* If we are deleting this reloc entry, we must fill in the
11068 value now. This can happen if we have a .word which is not
11069 resolved when it appears but is later defined. We also need
11070 to fill in the value if this is an embedded PIC switch table
11073 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
11074 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
11079 /* If we are deleting this reloc entry, we must fill in the
11081 assert (fixP->fx_size == 2);
11083 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
11087 case BFD_RELOC_LO16:
11088 /* When handling an embedded PIC switch statement, we can wind
11089 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11092 if (value + 0x8000 > 0xffff)
11093 as_bad_where (fixP->fx_file, fixP->fx_line,
11094 _("relocation overflow"));
11095 buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where;
11096 if (target_big_endian)
11098 md_number_to_chars ((char *) buf, value, 2);
11102 case BFD_RELOC_16_PCREL_S2:
11103 if ((value & 0x3) != 0)
11104 as_bad_where (fixP->fx_file, fixP->fx_line,
11105 _("Branch to odd address (%lx)"), (long) value);
11107 /* Fall through. */
11109 case BFD_RELOC_16_PCREL:
11111 * We need to save the bits in the instruction since fixup_segment()
11112 * might be deleting the relocation entry (i.e., a branch within
11113 * the current segment).
11115 if (!fixP->fx_done && value != 0)
11117 /* If 'value' is zero, the remaining reloc code won't actually
11118 do the store, so it must be done here. This is probably
11119 a bug somewhere. */
11121 && (fixP->fx_r_type != BFD_RELOC_16_PCREL_S2
11122 || fixP->fx_addsy == NULL /* ??? */
11123 || ! S_IS_DEFINED (fixP->fx_addsy)))
11124 value -= fixP->fx_frag->fr_address + fixP->fx_where;
11126 value = (offsetT) value >> 2;
11128 /* update old instruction data */
11129 buf = (bfd_byte *) (fixP->fx_where + fixP->fx_frag->fr_literal);
11130 if (target_big_endian)
11131 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
11133 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
11135 if (value + 0x8000 <= 0xffff)
11136 insn |= value & 0xffff;
11139 /* The branch offset is too large. If this is an
11140 unconditional branch, and we are not generating PIC code,
11141 we can convert it to an absolute jump instruction. */
11142 if (mips_pic == NO_PIC
11144 && fixP->fx_frag->fr_address >= text_section->vma
11145 && (fixP->fx_frag->fr_address
11146 < text_section->vma + text_section->_raw_size)
11147 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
11148 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
11149 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
11151 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
11152 insn = 0x0c000000; /* jal */
11154 insn = 0x08000000; /* j */
11155 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
11157 fixP->fx_addsy = section_symbol (text_section);
11158 fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP);
11162 /* FIXME. It would be possible in principle to handle
11163 conditional branches which overflow. They could be
11164 transformed into a branch around a jump. This would
11165 require setting up variant frags for each different
11166 branch type. The native MIPS assembler attempts to
11167 handle these cases, but it appears to do it
11169 as_bad_where (fixP->fx_file, fixP->fx_line,
11170 _("Branch out of range"));
11174 md_number_to_chars ((char *) buf, (valueT) insn, 4);
11177 case BFD_RELOC_VTABLE_INHERIT:
11180 && !S_IS_DEFINED (fixP->fx_addsy)
11181 && !S_IS_WEAK (fixP->fx_addsy))
11182 S_SET_WEAK (fixP->fx_addsy);
11185 case BFD_RELOC_VTABLE_ENTRY:
11199 const struct mips_opcode *p;
11200 int treg, sreg, dreg, shamt;
11205 for (i = 0; i < NUMOPCODES; ++i)
11207 p = &mips_opcodes[i];
11208 if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO))
11210 printf ("%08lx %s\t", oc, p->name);
11211 treg = (oc >> 16) & 0x1f;
11212 sreg = (oc >> 21) & 0x1f;
11213 dreg = (oc >> 11) & 0x1f;
11214 shamt = (oc >> 6) & 0x1f;
11216 for (args = p->args;; ++args)
11227 printf ("%c", *args);
11231 assert (treg == sreg);
11232 printf ("$%d,$%d", treg, sreg);
11237 printf ("$%d", dreg);
11242 printf ("$%d", treg);
11246 printf ("0x%x", treg);
11251 printf ("$%d", sreg);
11255 printf ("0x%08lx", oc & 0x1ffffff);
11262 printf ("%d", imm);
11267 printf ("$%d", shamt);
11278 printf (_("%08lx UNDEFINED\n"), oc);
11289 name = input_line_pointer;
11290 c = get_symbol_end ();
11291 p = (symbolS *) symbol_find_or_make (name);
11292 *input_line_pointer = c;
11296 /* Align the current frag to a given power of two. The MIPS assembler
11297 also automatically adjusts any preceding label. */
11300 mips_align (to, fill, label)
11305 mips_emit_delays (false);
11306 frag_align (to, fill, 0);
11307 record_alignment (now_seg, to);
11310 assert (S_GET_SEGMENT (label) == now_seg);
11311 symbol_set_frag (label, frag_now);
11312 S_SET_VALUE (label, (valueT) frag_now_fix ());
11316 /* Align to a given power of two. .align 0 turns off the automatic
11317 alignment used by the data creating pseudo-ops. */
11321 int x ATTRIBUTE_UNUSED;
11324 register long temp_fill;
11325 long max_alignment = 15;
11329 o Note that the assembler pulls down any immediately preceeding label
11330 to the aligned address.
11331 o It's not documented but auto alignment is reinstated by
11332 a .align pseudo instruction.
11333 o Note also that after auto alignment is turned off the mips assembler
11334 issues an error on attempt to assemble an improperly aligned data item.
11339 temp = get_absolute_expression ();
11340 if (temp > max_alignment)
11341 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
11344 as_warn (_("Alignment negative: 0 assumed."));
11347 if (*input_line_pointer == ',')
11349 ++input_line_pointer;
11350 temp_fill = get_absolute_expression ();
11357 mips_align (temp, (int) temp_fill,
11358 insn_labels != NULL ? insn_labels->label : NULL);
11365 demand_empty_rest_of_line ();
11369 mips_flush_pending_output ()
11371 mips_emit_delays (false);
11372 mips_clear_insn_labels ();
11381 /* When generating embedded PIC code, we only use the .text, .lit8,
11382 .sdata and .sbss sections. We change the .data and .rdata
11383 pseudo-ops to use .sdata. */
11384 if (mips_pic == EMBEDDED_PIC
11385 && (sec == 'd' || sec == 'r'))
11389 /* The ELF backend needs to know that we are changing sections, so
11390 that .previous works correctly. We could do something like check
11391 for an obj_section_change_hook macro, but that might be confusing
11392 as it would not be appropriate to use it in the section changing
11393 functions in read.c, since obj-elf.c intercepts those. FIXME:
11394 This should be cleaner, somehow. */
11395 obj_elf_section_change_hook ();
11398 mips_emit_delays (false);
11408 subseg_set (bss_section, (subsegT) get_absolute_expression ());
11409 demand_empty_rest_of_line ();
11413 if (USE_GLOBAL_POINTER_OPT)
11415 seg = subseg_new (RDATA_SECTION_NAME,
11416 (subsegT) get_absolute_expression ());
11417 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11419 bfd_set_section_flags (stdoutput, seg,
11425 if (strcmp (TARGET_OS, "elf") != 0)
11426 record_alignment (seg, 4);
11428 demand_empty_rest_of_line ();
11432 as_bad (_("No read only data section in this object file format"));
11433 demand_empty_rest_of_line ();
11439 if (USE_GLOBAL_POINTER_OPT)
11441 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
11442 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11444 bfd_set_section_flags (stdoutput, seg,
11445 SEC_ALLOC | SEC_LOAD | SEC_RELOC
11447 if (strcmp (TARGET_OS, "elf") != 0)
11448 record_alignment (seg, 4);
11450 demand_empty_rest_of_line ();
11455 as_bad (_("Global pointers not supported; recompile -G 0"));
11456 demand_empty_rest_of_line ();
11465 mips_enable_auto_align ()
11476 label = insn_labels != NULL ? insn_labels->label : NULL;
11477 mips_emit_delays (false);
11478 if (log_size > 0 && auto_align)
11479 mips_align (log_size, 0, label);
11480 mips_clear_insn_labels ();
11481 cons (1 << log_size);
11485 s_float_cons (type)
11490 label = insn_labels != NULL ? insn_labels->label : NULL;
11492 mips_emit_delays (false);
11497 mips_align (3, 0, label);
11499 mips_align (2, 0, label);
11502 mips_clear_insn_labels ();
11507 /* Handle .globl. We need to override it because on Irix 5 you are
11510 where foo is an undefined symbol, to mean that foo should be
11511 considered to be the address of a function. */
11515 int x ATTRIBUTE_UNUSED;
11522 name = input_line_pointer;
11523 c = get_symbol_end ();
11524 symbolP = symbol_find_or_make (name);
11525 *input_line_pointer = c;
11526 SKIP_WHITESPACE ();
11528 /* On Irix 5, every global symbol that is not explicitly labelled as
11529 being a function is apparently labelled as being an object. */
11532 if (! is_end_of_line[(unsigned char) *input_line_pointer])
11537 secname = input_line_pointer;
11538 c = get_symbol_end ();
11539 sec = bfd_get_section_by_name (stdoutput, secname);
11541 as_bad (_("%s: no such section"), secname);
11542 *input_line_pointer = c;
11544 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
11545 flag = BSF_FUNCTION;
11548 symbol_get_bfdsym (symbolP)->flags |= flag;
11550 S_SET_EXTERNAL (symbolP);
11551 demand_empty_rest_of_line ();
11556 int x ATTRIBUTE_UNUSED;
11561 opt = input_line_pointer;
11562 c = get_symbol_end ();
11566 /* FIXME: What does this mean? */
11568 else if (strncmp (opt, "pic", 3) == 0)
11572 i = atoi (opt + 3);
11576 mips_pic = SVR4_PIC;
11578 as_bad (_(".option pic%d not supported"), i);
11580 if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC)
11582 if (g_switch_seen && g_switch_value != 0)
11583 as_warn (_("-G may not be used with SVR4 PIC code"));
11584 g_switch_value = 0;
11585 bfd_set_gp_size (stdoutput, 0);
11589 as_warn (_("Unrecognized option \"%s\""), opt);
11591 *input_line_pointer = c;
11592 demand_empty_rest_of_line ();
11595 /* This structure is used to hold a stack of .set values. */
11597 struct mips_option_stack
11599 struct mips_option_stack *next;
11600 struct mips_set_options options;
11603 static struct mips_option_stack *mips_opts_stack;
11605 /* Handle the .set pseudo-op. */
11609 int x ATTRIBUTE_UNUSED;
11611 char *name = input_line_pointer, ch;
11613 while (!is_end_of_line[(unsigned char) *input_line_pointer])
11614 ++input_line_pointer;
11615 ch = *input_line_pointer;
11616 *input_line_pointer = '\0';
11618 if (strcmp (name, "reorder") == 0)
11620 if (mips_opts.noreorder && prev_nop_frag != NULL)
11622 /* If we still have pending nops, we can discard them. The
11623 usual nop handling will insert any that are still
11625 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11626 * (mips_opts.mips16 ? 2 : 4));
11627 prev_nop_frag = NULL;
11629 mips_opts.noreorder = 0;
11631 else if (strcmp (name, "noreorder") == 0)
11633 mips_emit_delays (true);
11634 mips_opts.noreorder = 1;
11635 mips_any_noreorder = 1;
11637 else if (strcmp (name, "at") == 0)
11639 mips_opts.noat = 0;
11641 else if (strcmp (name, "noat") == 0)
11643 mips_opts.noat = 1;
11645 else if (strcmp (name, "macro") == 0)
11647 mips_opts.warn_about_macros = 0;
11649 else if (strcmp (name, "nomacro") == 0)
11651 if (mips_opts.noreorder == 0)
11652 as_bad (_("`noreorder' must be set before `nomacro'"));
11653 mips_opts.warn_about_macros = 1;
11655 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
11657 mips_opts.nomove = 0;
11659 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
11661 mips_opts.nomove = 1;
11663 else if (strcmp (name, "bopt") == 0)
11665 mips_opts.nobopt = 0;
11667 else if (strcmp (name, "nobopt") == 0)
11669 mips_opts.nobopt = 1;
11671 else if (strcmp (name, "mips16") == 0
11672 || strcmp (name, "MIPS-16") == 0)
11673 mips_opts.mips16 = 1;
11674 else if (strcmp (name, "nomips16") == 0
11675 || strcmp (name, "noMIPS-16") == 0)
11676 mips_opts.mips16 = 0;
11677 else if (strcmp (name, "mips3d") == 0)
11678 mips_opts.ase_mips3d = 1;
11679 else if (strcmp (name, "nomips3d") == 0)
11680 mips_opts.ase_mips3d = 0;
11681 else if (strcmp (name, "mdmx") == 0)
11682 mips_opts.ase_mdmx = 1;
11683 else if (strcmp (name, "nomdmx") == 0)
11684 mips_opts.ase_mdmx = 0;
11685 else if (strncmp (name, "mips", 4) == 0)
11689 /* Permit the user to change the ISA on the fly. Needless to
11690 say, misuse can cause serious problems. */
11691 isa = atoi (name + 4);
11695 mips_opts.gp32 = file_mips_gp32;
11696 mips_opts.fp32 = file_mips_fp32;
11697 mips_opts.abi = file_mips_abi;
11702 mips_opts.gp32 = 1;
11703 mips_opts.fp32 = 1;
11709 /* Loosen ABI register width restriction. */
11710 if (mips_opts.abi == O32_ABI)
11711 mips_opts.abi = NO_ABI;
11712 mips_opts.gp32 = 0;
11713 mips_opts.fp32 = 0;
11716 as_bad (_("unknown ISA level %s"), name + 4);
11722 case 0: mips_opts.isa = file_mips_isa; break;
11723 case 1: mips_opts.isa = ISA_MIPS1; break;
11724 case 2: mips_opts.isa = ISA_MIPS2; break;
11725 case 3: mips_opts.isa = ISA_MIPS3; break;
11726 case 4: mips_opts.isa = ISA_MIPS4; break;
11727 case 5: mips_opts.isa = ISA_MIPS5; break;
11728 case 32: mips_opts.isa = ISA_MIPS32; break;
11729 case 64: mips_opts.isa = ISA_MIPS64; break;
11730 default: as_bad (_("unknown ISA level %s"), name + 4); break;
11733 else if (strcmp (name, "autoextend") == 0)
11734 mips_opts.noautoextend = 0;
11735 else if (strcmp (name, "noautoextend") == 0)
11736 mips_opts.noautoextend = 1;
11737 else if (strcmp (name, "push") == 0)
11739 struct mips_option_stack *s;
11741 s = (struct mips_option_stack *) xmalloc (sizeof *s);
11742 s->next = mips_opts_stack;
11743 s->options = mips_opts;
11744 mips_opts_stack = s;
11746 else if (strcmp (name, "pop") == 0)
11748 struct mips_option_stack *s;
11750 s = mips_opts_stack;
11752 as_bad (_(".set pop with no .set push"));
11755 /* If we're changing the reorder mode we need to handle
11756 delay slots correctly. */
11757 if (s->options.noreorder && ! mips_opts.noreorder)
11758 mips_emit_delays (true);
11759 else if (! s->options.noreorder && mips_opts.noreorder)
11761 if (prev_nop_frag != NULL)
11763 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11764 * (mips_opts.mips16 ? 2 : 4));
11765 prev_nop_frag = NULL;
11769 mips_opts = s->options;
11770 mips_opts_stack = s->next;
11776 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
11778 *input_line_pointer = ch;
11779 demand_empty_rest_of_line ();
11782 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11783 .option pic2. It means to generate SVR4 PIC calls. */
11786 s_abicalls (ignore)
11787 int ignore ATTRIBUTE_UNUSED;
11789 mips_pic = SVR4_PIC;
11790 if (USE_GLOBAL_POINTER_OPT)
11792 if (g_switch_seen && g_switch_value != 0)
11793 as_warn (_("-G may not be used with SVR4 PIC code"));
11794 g_switch_value = 0;
11796 bfd_set_gp_size (stdoutput, 0);
11797 demand_empty_rest_of_line ();
11800 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11801 PIC code. It sets the $gp register for the function based on the
11802 function address, which is in the register named in the argument.
11803 This uses a relocation against _gp_disp, which is handled specially
11804 by the linker. The result is:
11805 lui $gp,%hi(_gp_disp)
11806 addiu $gp,$gp,%lo(_gp_disp)
11807 addu $gp,$gp,.cpload argument
11808 The .cpload argument is normally $25 == $t9. */
11812 int ignore ATTRIBUTE_UNUSED;
11817 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11818 .cpload is ignored. */
11819 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
11825 /* .cpload should be in a .set noreorder section. */
11826 if (mips_opts.noreorder == 0)
11827 as_warn (_(".cpload not in noreorder section"));
11829 ex.X_op = O_symbol;
11830 ex.X_add_symbol = symbol_find_or_make ("_gp_disp");
11831 ex.X_op_symbol = NULL;
11832 ex.X_add_number = 0;
11834 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11835 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
11837 macro_build_lui (NULL, &icnt, &ex, mips_gp_register);
11838 macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j",
11839 mips_gp_register, mips_gp_register, (int) BFD_RELOC_LO16);
11841 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t",
11842 mips_gp_register, mips_gp_register, tc_get_register (0));
11844 demand_empty_rest_of_line ();
11847 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11848 .cpsetup $reg1, offset|$reg2, label
11850 If offset is given, this results in:
11851 sd $gp, offset($sp)
11852 lui $gp, %hi(%neg(%gp_rel(label)))
11853 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11854 daddu $gp, $gp, $reg1
11856 If $reg2 is given, this results in:
11857 daddu $reg2, $gp, $0
11858 lui $gp, %hi(%neg(%gp_rel(label)))
11859 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11860 daddu $gp, $gp, $reg1
11861 $reg1 is normally $25 == $t9. */
11864 int ignore ATTRIBUTE_UNUSED;
11866 expressionS ex_off;
11867 expressionS ex_sym;
11872 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
11873 We also need NewABI support. */
11874 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11880 reg1 = tc_get_register (0);
11881 SKIP_WHITESPACE ();
11882 if (*input_line_pointer != ',')
11884 as_bad (_("missing argument separator ',' for .cpsetup"));
11888 ++input_line_pointer;
11889 SKIP_WHITESPACE ();
11890 if (*input_line_pointer == '$')
11892 mips_cpreturn_register = tc_get_register (0);
11893 mips_cpreturn_offset = -1;
11897 mips_cpreturn_offset = get_absolute_expression ();
11898 mips_cpreturn_register = -1;
11900 SKIP_WHITESPACE ();
11901 if (*input_line_pointer != ',')
11903 as_bad (_("missing argument separator ',' for .cpsetup"));
11907 ++input_line_pointer;
11908 SKIP_WHITESPACE ();
11909 sym = input_line_pointer;
11910 while (ISALNUM (*input_line_pointer))
11911 ++input_line_pointer;
11912 *input_line_pointer = 0;
11914 ex_sym.X_op = O_symbol;
11915 ex_sym.X_add_symbol = symbol_find_or_make (sym);
11916 ex_sym.X_op_symbol = NULL;
11917 ex_sym.X_add_number = 0;
11919 if (mips_cpreturn_register == -1)
11921 ex_off.X_op = O_constant;
11922 ex_off.X_add_symbol = NULL;
11923 ex_off.X_op_symbol = NULL;
11924 ex_off.X_add_number = mips_cpreturn_offset;
11926 macro_build ((char *) NULL, &icnt, &ex_off, "sd", "t,o(b)",
11927 mips_gp_register, (int) BFD_RELOC_LO16, SP);
11930 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu",
11931 "d,v,t", mips_cpreturn_register, mips_gp_register, 0);
11933 macro_build ((char *) NULL, &icnt, &ex_sym, "lui", "t,u", mips_gp_register,
11934 (int) BFD_RELOC_GPREL16);
11935 fix_new (frag_now, prev_insn_where, 0, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
11936 fix_new (frag_now, prev_insn_where, 0, NULL, 0, 0, BFD_RELOC_HI16_S);
11937 macro_build ((char *) NULL, &icnt, &ex_sym, "addiu", "t,r,j",
11938 mips_gp_register, mips_gp_register, (int) BFD_RELOC_GPREL16);
11939 fix_new (frag_now, prev_insn_where, 0, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
11940 fix_new (frag_now, prev_insn_where, 0, NULL, 0, 0, BFD_RELOC_LO16);
11941 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
11942 HAVE_64BIT_ADDRESSES ? "daddu" : "addu", "d,v,t",
11943 mips_gp_register, mips_gp_register, reg1);
11945 demand_empty_rest_of_line ();
11950 int ignore ATTRIBUTE_UNUSED;
11952 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11953 .cplocal is ignored. */
11954 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11960 mips_gp_register = tc_get_register (0);
11961 demand_empty_rest_of_line ();
11964 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11965 offset from $sp. The offset is remembered, and after making a PIC
11966 call $gp is restored from that location. */
11969 s_cprestore (ignore)
11970 int ignore ATTRIBUTE_UNUSED;
11975 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11976 .cprestore is ignored. */
11977 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
11983 mips_cprestore_offset = get_absolute_expression ();
11984 mips_cprestore_valid = 1;
11986 ex.X_op = O_constant;
11987 ex.X_add_symbol = NULL;
11988 ex.X_op_symbol = NULL;
11989 ex.X_add_number = mips_cprestore_offset;
11991 macro_build ((char *) NULL, &icnt, &ex, HAVE_32BIT_ADDRESSES ? "sw" : "sd",
11992 "t,o(b)", mips_gp_register, (int) BFD_RELOC_LO16, SP);
11994 demand_empty_rest_of_line ();
11997 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
11998 was given in the preceeding .gpsetup, it results in:
11999 ld $gp, offset($sp)
12001 If a register $reg2 was given there, it results in:
12002 daddiu $gp, $gp, $reg2
12005 s_cpreturn (ignore)
12006 int ignore ATTRIBUTE_UNUSED;
12011 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12012 We also need NewABI support. */
12013 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12019 if (mips_cpreturn_register == -1)
12021 ex.X_op = O_constant;
12022 ex.X_add_symbol = NULL;
12023 ex.X_op_symbol = NULL;
12024 ex.X_add_number = mips_cpreturn_offset;
12026 macro_build ((char *) NULL, &icnt, &ex, "ld", "t,o(b)",
12027 mips_gp_register, (int) BFD_RELOC_LO16, SP);
12030 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu",
12031 "d,v,t", mips_gp_register, mips_cpreturn_register, 0);
12033 demand_empty_rest_of_line ();
12036 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12037 code. It sets the offset to use in gp_rel relocations. */
12041 int ignore ATTRIBUTE_UNUSED;
12043 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12044 We also need NewABI support. */
12045 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12051 mips_gprel_offset = get_absolute_expression ();
12053 demand_empty_rest_of_line ();
12056 /* Handle the .gpword pseudo-op. This is used when generating PIC
12057 code. It generates a 32 bit GP relative reloc. */
12061 int ignore ATTRIBUTE_UNUSED;
12067 /* When not generating PIC code, this is treated as .word. */
12068 if (mips_pic != SVR4_PIC)
12074 label = insn_labels != NULL ? insn_labels->label : NULL;
12075 mips_emit_delays (true);
12077 mips_align (2, 0, label);
12078 mips_clear_insn_labels ();
12082 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12084 as_bad (_("Unsupported use of .gpword"));
12085 ignore_rest_of_line ();
12089 md_number_to_chars (p, (valueT) 0, 4);
12090 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, false,
12091 BFD_RELOC_GPREL32);
12093 demand_empty_rest_of_line ();
12096 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12097 tables in SVR4 PIC code. */
12101 int ignore ATTRIBUTE_UNUSED;
12106 /* This is ignored when not generating SVR4 PIC code or if this is NewABI
12108 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12114 /* Add $gp to the register named as an argument. */
12115 reg = tc_get_register (0);
12116 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
12117 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
12118 "d,v,t", reg, reg, mips_gp_register);
12120 demand_empty_rest_of_line ();
12123 /* Handle the .insn pseudo-op. This marks instruction labels in
12124 mips16 mode. This permits the linker to handle them specially,
12125 such as generating jalx instructions when needed. We also make
12126 them odd for the duration of the assembly, in order to generate the
12127 right sort of code. We will make them even in the adjust_symtab
12128 routine, while leaving them marked. This is convenient for the
12129 debugger and the disassembler. The linker knows to make them odd
12134 int ignore ATTRIBUTE_UNUSED;
12136 mips16_mark_labels ();
12138 demand_empty_rest_of_line ();
12141 /* Handle a .stabn directive. We need these in order to mark a label
12142 as being a mips16 text label correctly. Sometimes the compiler
12143 will emit a label, followed by a .stabn, and then switch sections.
12144 If the label and .stabn are in mips16 mode, then the label is
12145 really a mips16 text label. */
12152 mips16_mark_labels ();
12157 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12161 s_mips_weakext (ignore)
12162 int ignore ATTRIBUTE_UNUSED;
12169 name = input_line_pointer;
12170 c = get_symbol_end ();
12171 symbolP = symbol_find_or_make (name);
12172 S_SET_WEAK (symbolP);
12173 *input_line_pointer = c;
12175 SKIP_WHITESPACE ();
12177 if (! is_end_of_line[(unsigned char) *input_line_pointer])
12179 if (S_IS_DEFINED (symbolP))
12181 as_bad ("ignoring attempt to redefine symbol %s",
12182 S_GET_NAME (symbolP));
12183 ignore_rest_of_line ();
12187 if (*input_line_pointer == ',')
12189 ++input_line_pointer;
12190 SKIP_WHITESPACE ();
12194 if (exp.X_op != O_symbol)
12196 as_bad ("bad .weakext directive");
12197 ignore_rest_of_line ();
12200 symbol_set_value_expression (symbolP, &exp);
12203 demand_empty_rest_of_line ();
12206 /* Parse a register string into a number. Called from the ECOFF code
12207 to parse .frame. The argument is non-zero if this is the frame
12208 register, so that we can record it in mips_frame_reg. */
12211 tc_get_register (frame)
12216 SKIP_WHITESPACE ();
12217 if (*input_line_pointer++ != '$')
12219 as_warn (_("expected `$'"));
12222 else if (ISDIGIT (*input_line_pointer))
12224 reg = get_absolute_expression ();
12225 if (reg < 0 || reg >= 32)
12227 as_warn (_("Bad register number"));
12233 if (strncmp (input_line_pointer, "ra", 2) == 0)
12236 input_line_pointer += 2;
12238 else if (strncmp (input_line_pointer, "fp", 2) == 0)
12241 input_line_pointer += 2;
12243 else if (strncmp (input_line_pointer, "sp", 2) == 0)
12246 input_line_pointer += 2;
12248 else if (strncmp (input_line_pointer, "gp", 2) == 0)
12251 input_line_pointer += 2;
12253 else if (strncmp (input_line_pointer, "at", 2) == 0)
12256 input_line_pointer += 2;
12258 else if (strncmp (input_line_pointer, "kt0", 3) == 0)
12261 input_line_pointer += 3;
12263 else if (strncmp (input_line_pointer, "kt1", 3) == 0)
12266 input_line_pointer += 3;
12268 else if (strncmp (input_line_pointer, "zero", 4) == 0)
12271 input_line_pointer += 4;
12275 as_warn (_("Unrecognized register name"));
12277 while (ISALNUM(*input_line_pointer))
12278 input_line_pointer++;
12283 mips_frame_reg = reg != 0 ? reg : SP;
12284 mips_frame_reg_valid = 1;
12285 mips_cprestore_valid = 0;
12291 md_section_align (seg, addr)
12295 int align = bfd_get_section_alignment (stdoutput, seg);
12298 /* We don't need to align ELF sections to the full alignment.
12299 However, Irix 5 may prefer that we align them at least to a 16
12300 byte boundary. We don't bother to align the sections if we are
12301 targeted for an embedded system. */
12302 if (strcmp (TARGET_OS, "elf") == 0)
12308 return ((addr + (1 << align) - 1) & (-1 << align));
12311 /* Utility routine, called from above as well. If called while the
12312 input file is still being read, it's only an approximation. (For
12313 example, a symbol may later become defined which appeared to be
12314 undefined earlier.) */
12317 nopic_need_relax (sym, before_relaxing)
12319 int before_relaxing;
12324 if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0)
12326 const char *symname;
12329 /* Find out whether this symbol can be referenced off the $gp
12330 register. It can be if it is smaller than the -G size or if
12331 it is in the .sdata or .sbss section. Certain symbols can
12332 not be referenced off the $gp, although it appears as though
12334 symname = S_GET_NAME (sym);
12335 if (symname != (const char *) NULL
12336 && (strcmp (symname, "eprol") == 0
12337 || strcmp (symname, "etext") == 0
12338 || strcmp (symname, "_gp") == 0
12339 || strcmp (symname, "edata") == 0
12340 || strcmp (symname, "_fbss") == 0
12341 || strcmp (symname, "_fdata") == 0
12342 || strcmp (symname, "_ftext") == 0
12343 || strcmp (symname, "end") == 0
12344 || strcmp (symname, "_gp_disp") == 0))
12346 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
12348 #ifndef NO_ECOFF_DEBUGGING
12349 || (symbol_get_obj (sym)->ecoff_extern_size != 0
12350 && (symbol_get_obj (sym)->ecoff_extern_size
12351 <= g_switch_value))
12353 /* We must defer this decision until after the whole
12354 file has been read, since there might be a .extern
12355 after the first use of this symbol. */
12356 || (before_relaxing
12357 #ifndef NO_ECOFF_DEBUGGING
12358 && symbol_get_obj (sym)->ecoff_extern_size == 0
12360 && S_GET_VALUE (sym) == 0)
12361 || (S_GET_VALUE (sym) != 0
12362 && S_GET_VALUE (sym) <= g_switch_value)))
12366 const char *segname;
12368 segname = segment_name (S_GET_SEGMENT (sym));
12369 assert (strcmp (segname, ".lit8") != 0
12370 && strcmp (segname, ".lit4") != 0);
12371 change = (strcmp (segname, ".sdata") != 0
12372 && strcmp (segname, ".sbss") != 0
12373 && strncmp (segname, ".sdata.", 7) != 0
12374 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
12379 /* We are not optimizing for the $gp register. */
12383 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12384 extended opcode. SEC is the section the frag is in. */
12387 mips16_extended_frag (fragp, sec, stretch)
12393 register const struct mips16_immed_operand *op;
12395 int mintiny, maxtiny;
12399 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
12401 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
12404 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
12405 op = mips16_immed_operands;
12406 while (op->type != type)
12409 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
12414 if (type == '<' || type == '>' || type == '[' || type == ']')
12417 maxtiny = 1 << op->nbits;
12422 maxtiny = (1 << op->nbits) - 1;
12427 mintiny = - (1 << (op->nbits - 1));
12428 maxtiny = (1 << (op->nbits - 1)) - 1;
12431 sym_frag = symbol_get_frag (fragp->fr_symbol);
12432 val = S_GET_VALUE (fragp->fr_symbol);
12433 symsec = S_GET_SEGMENT (fragp->fr_symbol);
12439 /* We won't have the section when we are called from
12440 mips_relax_frag. However, we will always have been called
12441 from md_estimate_size_before_relax first. If this is a
12442 branch to a different section, we mark it as such. If SEC is
12443 NULL, and the frag is not marked, then it must be a branch to
12444 the same section. */
12447 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
12452 /* Must have been called from md_estimate_size_before_relax. */
12455 fragp->fr_subtype =
12456 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12458 /* FIXME: We should support this, and let the linker
12459 catch branches and loads that are out of range. */
12460 as_bad_where (fragp->fr_file, fragp->fr_line,
12461 _("unsupported PC relative reference to different section"));
12465 if (fragp != sym_frag && sym_frag->fr_address == 0)
12466 /* Assume non-extended on the first relaxation pass.
12467 The address we have calculated will be bogus if this is
12468 a forward branch to another frag, as the forward frag
12469 will have fr_address == 0. */
12473 /* In this case, we know for sure that the symbol fragment is in
12474 the same section. If the relax_marker of the symbol fragment
12475 differs from the relax_marker of this fragment, we have not
12476 yet adjusted the symbol fragment fr_address. We want to add
12477 in STRETCH in order to get a better estimate of the address.
12478 This particularly matters because of the shift bits. */
12480 && sym_frag->relax_marker != fragp->relax_marker)
12484 /* Adjust stretch for any alignment frag. Note that if have
12485 been expanding the earlier code, the symbol may be
12486 defined in what appears to be an earlier frag. FIXME:
12487 This doesn't handle the fr_subtype field, which specifies
12488 a maximum number of bytes to skip when doing an
12490 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
12492 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
12495 stretch = - ((- stretch)
12496 & ~ ((1 << (int) f->fr_offset) - 1));
12498 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
12507 addr = fragp->fr_address + fragp->fr_fix;
12509 /* The base address rules are complicated. The base address of
12510 a branch is the following instruction. The base address of a
12511 PC relative load or add is the instruction itself, but if it
12512 is in a delay slot (in which case it can not be extended) use
12513 the address of the instruction whose delay slot it is in. */
12514 if (type == 'p' || type == 'q')
12518 /* If we are currently assuming that this frag should be
12519 extended, then, the current address is two bytes
12521 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12524 /* Ignore the low bit in the target, since it will be set
12525 for a text label. */
12526 if ((val & 1) != 0)
12529 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
12531 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
12534 val -= addr & ~ ((1 << op->shift) - 1);
12536 /* Branch offsets have an implicit 0 in the lowest bit. */
12537 if (type == 'p' || type == 'q')
12540 /* If any of the shifted bits are set, we must use an extended
12541 opcode. If the address depends on the size of this
12542 instruction, this can lead to a loop, so we arrange to always
12543 use an extended opcode. We only check this when we are in
12544 the main relaxation loop, when SEC is NULL. */
12545 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
12547 fragp->fr_subtype =
12548 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12552 /* If we are about to mark a frag as extended because the value
12553 is precisely maxtiny + 1, then there is a chance of an
12554 infinite loop as in the following code:
12559 In this case when the la is extended, foo is 0x3fc bytes
12560 away, so the la can be shrunk, but then foo is 0x400 away, so
12561 the la must be extended. To avoid this loop, we mark the
12562 frag as extended if it was small, and is about to become
12563 extended with a value of maxtiny + 1. */
12564 if (val == ((maxtiny + 1) << op->shift)
12565 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
12568 fragp->fr_subtype =
12569 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12573 else if (symsec != absolute_section && sec != NULL)
12574 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
12576 if ((val & ((1 << op->shift) - 1)) != 0
12577 || val < (mintiny << op->shift)
12578 || val > (maxtiny << op->shift))
12584 /* Estimate the size of a frag before relaxing. Unless this is the
12585 mips16, we are not really relaxing here, and the final size is
12586 encoded in the subtype information. For the mips16, we have to
12587 decide whether we are using an extended opcode or not. */
12590 md_estimate_size_before_relax (fragp, segtype)
12595 boolean linkonce = false;
12597 if (RELAX_MIPS16_P (fragp->fr_subtype))
12598 /* We don't want to modify the EXTENDED bit here; it might get us
12599 into infinite loops. We change it only in mips_relax_frag(). */
12600 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
12602 if (mips_pic == NO_PIC)
12604 change = nopic_need_relax (fragp->fr_symbol, 0);
12606 else if (mips_pic == SVR4_PIC)
12611 sym = fragp->fr_symbol;
12613 /* Handle the case of a symbol equated to another symbol. */
12614 while (symbol_equated_reloc_p (sym))
12618 /* It's possible to get a loop here in a badly written
12620 n = symbol_get_value_expression (sym)->X_add_symbol;
12626 symsec = S_GET_SEGMENT (sym);
12628 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12629 if (symsec != segtype && ! S_IS_LOCAL (sym))
12631 if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE)
12635 /* The GNU toolchain uses an extension for ELF: a section
12636 beginning with the magic string .gnu.linkonce is a linkonce
12638 if (strncmp (segment_name (symsec), ".gnu.linkonce",
12639 sizeof ".gnu.linkonce" - 1) == 0)
12643 /* This must duplicate the test in adjust_reloc_syms. */
12644 change = (symsec != &bfd_und_section
12645 && symsec != &bfd_abs_section
12646 && ! bfd_is_com_section (symsec)
12649 /* A global or weak symbol is treated as external. */
12650 && (OUTPUT_FLAVOR != bfd_target_elf_flavour
12651 || (! S_IS_WEAK (sym)
12652 && (! S_IS_EXTERN (sym) || mips_pic == EMBEDDED_PIC)))
12661 /* Record the offset to the first reloc in the fr_opcode field.
12662 This lets md_convert_frag and tc_gen_reloc know that the code
12663 must be expanded. */
12664 fragp->fr_opcode = (fragp->fr_literal
12666 - RELAX_OLD (fragp->fr_subtype)
12667 + RELAX_RELOC1 (fragp->fr_subtype));
12668 /* FIXME: This really needs as_warn_where. */
12669 if (RELAX_WARN (fragp->fr_subtype))
12670 as_warn (_("AT used after \".set noat\" or macro used after "
12671 "\".set nomacro\""));
12673 return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype);
12679 /* This is called to see whether a reloc against a defined symbol
12680 should be converted into a reloc against a section. Don't adjust
12681 MIPS16 jump relocations, so we don't have to worry about the format
12682 of the offset in the .o file. Don't adjust relocations against
12683 mips16 symbols, so that the linker can find them if it needs to set
12687 mips_fix_adjustable (fixp)
12691 /* Prevent all adjustments to global symbols. */
12692 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
12693 && mips_pic != EMBEDDED_PIC
12694 && (S_IS_EXTERN (fixp->fx_addsy) || S_IS_WEAK (fixp->fx_addsy)))
12697 if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
12699 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12700 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12702 if (fixp->fx_addsy == NULL)
12705 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
12706 && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
12707 && fixp->fx_subsy == NULL)
12713 /* Translate internal representation of relocation info to BFD target
12717 tc_gen_reloc (section, fixp)
12718 asection *section ATTRIBUTE_UNUSED;
12721 static arelent *retval[4];
12723 bfd_reloc_code_real_type code;
12725 reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent));
12728 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
12729 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
12730 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
12732 if (mips_pic == EMBEDDED_PIC
12733 && SWITCH_TABLE (fixp))
12735 /* For a switch table entry we use a special reloc. The addend
12736 is actually the difference between the reloc address and the
12738 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
12739 if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour)
12740 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
12741 fixp->fx_r_type = BFD_RELOC_GPREL32;
12743 else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16)
12745 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
12746 reloc->addend = fixp->fx_addnumber;
12749 /* We use a special addend for an internal RELLO reloc. */
12750 if (symbol_section_p (fixp->fx_addsy))
12751 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
12753 reloc->addend = fixp->fx_addnumber + reloc->address;
12756 else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
12758 assert (fixp->fx_next != NULL
12759 && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16);
12761 /* The reloc is relative to the RELLO; adjust the addend
12763 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
12764 reloc->addend = fixp->fx_next->fx_addnumber;
12767 /* We use a special addend for an internal RELHI reloc. */
12768 if (symbol_section_p (fixp->fx_addsy))
12769 reloc->addend = (fixp->fx_next->fx_frag->fr_address
12770 + fixp->fx_next->fx_where
12771 - S_GET_VALUE (fixp->fx_subsy));
12773 reloc->addend = (fixp->fx_addnumber
12774 + fixp->fx_next->fx_frag->fr_address
12775 + fixp->fx_next->fx_where);
12778 else if (fixp->fx_pcrel == 0 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
12779 reloc->addend = fixp->fx_addnumber;
12782 if (OUTPUT_FLAVOR != bfd_target_aout_flavour)
12783 /* A gruesome hack which is a result of the gruesome gas reloc
12785 reloc->addend = reloc->address;
12787 reloc->addend = -reloc->address;
12790 /* If this is a variant frag, we may need to adjust the existing
12791 reloc and generate a new one. */
12792 if (fixp->fx_frag->fr_opcode != NULL
12793 && (fixp->fx_r_type == BFD_RELOC_GPREL16
12794 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
12795 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16
12796 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
12797 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16
12798 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
12799 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)
12804 assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype));
12806 /* If this is not the last reloc in this frag, then we have two
12807 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
12808 CALL_HI16/CALL_LO16, both of which are being replaced. Let
12809 the second one handle all of them. */
12810 if (fixp->fx_next != NULL
12811 && fixp->fx_frag == fixp->fx_next->fx_frag)
12813 assert ((fixp->fx_r_type == BFD_RELOC_GPREL16
12814 && fixp->fx_next->fx_r_type == BFD_RELOC_GPREL16)
12815 || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
12816 && (fixp->fx_next->fx_r_type
12817 == BFD_RELOC_MIPS_GOT_LO16))
12818 || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
12819 && (fixp->fx_next->fx_r_type
12820 == BFD_RELOC_MIPS_CALL_LO16)));
12825 fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal;
12826 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
12827 reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent));
12829 reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
12830 *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
12831 reloc2->address = (reloc->address
12832 + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype)
12833 - RELAX_RELOC1 (fixp->fx_frag->fr_subtype)));
12834 reloc2->addend = fixp->fx_addnumber;
12835 reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16);
12836 assert (reloc2->howto != NULL);
12838 if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype))
12842 reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent));
12845 reloc3->address += 4;
12848 if (mips_pic == NO_PIC)
12850 assert (fixp->fx_r_type == BFD_RELOC_GPREL16);
12851 fixp->fx_r_type = BFD_RELOC_HI16_S;
12853 else if (mips_pic == SVR4_PIC)
12855 switch (fixp->fx_r_type)
12859 case BFD_RELOC_MIPS_GOT16:
12861 case BFD_RELOC_MIPS_CALL16:
12862 case BFD_RELOC_MIPS_GOT_LO16:
12863 case BFD_RELOC_MIPS_CALL_LO16:
12864 fixp->fx_r_type = BFD_RELOC_MIPS_GOT16;
12872 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
12873 entry to be used in the relocation's section offset. */
12874 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12876 reloc->address = reloc->addend;
12880 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
12881 fixup_segment converted a non-PC relative reloc into a PC
12882 relative reloc. In such a case, we need to convert the reloc
12884 code = fixp->fx_r_type;
12885 if (fixp->fx_pcrel)
12890 code = BFD_RELOC_8_PCREL;
12893 code = BFD_RELOC_16_PCREL;
12896 code = BFD_RELOC_32_PCREL;
12899 code = BFD_RELOC_64_PCREL;
12901 case BFD_RELOC_8_PCREL:
12902 case BFD_RELOC_16_PCREL:
12903 case BFD_RELOC_32_PCREL:
12904 case BFD_RELOC_64_PCREL:
12905 case BFD_RELOC_16_PCREL_S2:
12906 case BFD_RELOC_PCREL_HI16_S:
12907 case BFD_RELOC_PCREL_LO16:
12910 as_bad_where (fixp->fx_file, fixp->fx_line,
12911 _("Cannot make %s relocation PC relative"),
12912 bfd_get_reloc_code_name (code));
12917 /* md_apply_fix3 has a double-subtraction hack to get
12918 bfd_install_relocation to behave nicely. GPREL relocations are
12919 handled correctly without this hack, so undo it here. We can't
12920 stop md_apply_fix3 from subtracting twice in the first place since
12921 the fake addend is required for variant frags above. */
12922 if (fixp->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour
12923 && code == BFD_RELOC_GPREL16
12924 && reloc->addend != 0
12925 && mips_need_elf_addend_fixup (fixp))
12926 reloc->addend += S_GET_VALUE (fixp->fx_addsy);
12929 /* To support a PC relative reloc when generating embedded PIC code
12930 for ECOFF, we use a Cygnus extension. We check for that here to
12931 make sure that we don't let such a reloc escape normally. */
12932 if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
12933 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
12934 && code == BFD_RELOC_16_PCREL_S2
12935 && mips_pic != EMBEDDED_PIC)
12936 reloc->howto = NULL;
12938 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
12940 if (reloc->howto == NULL)
12942 as_bad_where (fixp->fx_file, fixp->fx_line,
12943 _("Can not represent %s relocation in this object file format"),
12944 bfd_get_reloc_code_name (code));
12951 /* Relax a machine dependent frag. This returns the amount by which
12952 the current size of the frag should change. */
12955 mips_relax_frag (fragp, stretch)
12959 if (! RELAX_MIPS16_P (fragp->fr_subtype))
12962 if (mips16_extended_frag (fragp, NULL, stretch))
12964 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12966 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
12971 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12973 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
12980 /* Convert a machine dependent frag. */
12983 md_convert_frag (abfd, asec, fragp)
12984 bfd *abfd ATTRIBUTE_UNUSED;
12991 if (RELAX_MIPS16_P (fragp->fr_subtype))
12994 register const struct mips16_immed_operand *op;
12995 boolean small, ext;
12998 unsigned long insn;
12999 boolean use_extend;
13000 unsigned short extend;
13002 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
13003 op = mips16_immed_operands;
13004 while (op->type != type)
13007 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13018 resolve_symbol_value (fragp->fr_symbol);
13019 val = S_GET_VALUE (fragp->fr_symbol);
13024 addr = fragp->fr_address + fragp->fr_fix;
13026 /* The rules for the base address of a PC relative reloc are
13027 complicated; see mips16_extended_frag. */
13028 if (type == 'p' || type == 'q')
13033 /* Ignore the low bit in the target, since it will be
13034 set for a text label. */
13035 if ((val & 1) != 0)
13038 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
13040 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
13043 addr &= ~ (addressT) ((1 << op->shift) - 1);
13046 /* Make sure the section winds up with the alignment we have
13049 record_alignment (asec, op->shift);
13053 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
13054 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
13055 as_warn_where (fragp->fr_file, fragp->fr_line,
13056 _("extended instruction in delay slot"));
13058 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
13060 if (target_big_endian)
13061 insn = bfd_getb16 (buf);
13063 insn = bfd_getl16 (buf);
13065 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
13066 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
13067 small, ext, &insn, &use_extend, &extend);
13071 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
13072 fragp->fr_fix += 2;
13076 md_number_to_chars ((char *) buf, insn, 2);
13077 fragp->fr_fix += 2;
13082 if (fragp->fr_opcode == NULL)
13085 old = RELAX_OLD (fragp->fr_subtype);
13086 new = RELAX_NEW (fragp->fr_subtype);
13087 fixptr = fragp->fr_literal + fragp->fr_fix;
13090 memcpy (fixptr - old, fixptr, new);
13092 fragp->fr_fix += new - old;
13098 /* This function is called after the relocs have been generated.
13099 We've been storing mips16 text labels as odd. Here we convert them
13100 back to even for the convenience of the debugger. */
13103 mips_frob_file_after_relocs ()
13106 unsigned int count, i;
13108 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
13111 syms = bfd_get_outsymbols (stdoutput);
13112 count = bfd_get_symcount (stdoutput);
13113 for (i = 0; i < count; i++, syms++)
13115 if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16
13116 && ((*syms)->value & 1) != 0)
13118 (*syms)->value &= ~1;
13119 /* If the symbol has an odd size, it was probably computed
13120 incorrectly, so adjust that as well. */
13121 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
13122 ++elf_symbol (*syms)->internal_elf_sym.st_size;
13129 /* This function is called whenever a label is defined. It is used
13130 when handling branch delays; if a branch has a label, we assume we
13131 can not move it. */
13134 mips_define_label (sym)
13137 struct insn_label_list *l;
13139 if (free_insn_labels == NULL)
13140 l = (struct insn_label_list *) xmalloc (sizeof *l);
13143 l = free_insn_labels;
13144 free_insn_labels = l->next;
13148 l->next = insn_labels;
13152 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13154 /* Some special processing for a MIPS ELF file. */
13157 mips_elf_final_processing ()
13159 /* Write out the register information. */
13160 if (file_mips_abi != N64_ABI)
13164 s.ri_gprmask = mips_gprmask;
13165 s.ri_cprmask[0] = mips_cprmask[0];
13166 s.ri_cprmask[1] = mips_cprmask[1];
13167 s.ri_cprmask[2] = mips_cprmask[2];
13168 s.ri_cprmask[3] = mips_cprmask[3];
13169 /* The gp_value field is set by the MIPS ELF backend. */
13171 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
13172 ((Elf32_External_RegInfo *)
13173 mips_regmask_frag));
13177 Elf64_Internal_RegInfo s;
13179 s.ri_gprmask = mips_gprmask;
13181 s.ri_cprmask[0] = mips_cprmask[0];
13182 s.ri_cprmask[1] = mips_cprmask[1];
13183 s.ri_cprmask[2] = mips_cprmask[2];
13184 s.ri_cprmask[3] = mips_cprmask[3];
13185 /* The gp_value field is set by the MIPS ELF backend. */
13187 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
13188 ((Elf64_External_RegInfo *)
13189 mips_regmask_frag));
13192 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13193 sort of BFD interface for this. */
13194 if (mips_any_noreorder)
13195 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
13196 if (mips_pic != NO_PIC)
13197 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
13199 /* Set MIPS ELF flags for ASEs. */
13200 if (file_ase_mips16)
13201 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
13202 #if 0 /* XXX FIXME */
13203 if (file_ase_mips3d)
13204 elf_elfheader (stdoutput)->e_flags |= ???;
13207 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
13209 /* Set the MIPS ELF ABI flags. */
13210 if (file_mips_abi == NO_ABI)
13212 else if (file_mips_abi == O32_ABI)
13213 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
13214 else if (file_mips_abi == O64_ABI)
13215 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
13216 else if (file_mips_abi == EABI_ABI)
13218 /* Set the EABI kind based on the ISA. This isn't really
13219 the best, but then neither is basing the abi on the isa. */
13220 if (ISA_HAS_64BIT_REGS (file_mips_isa))
13221 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
13223 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
13225 else if (file_mips_abi == N32_ABI)
13226 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
13228 /* Nothing to do for N64_ABI. */
13230 if (mips_32bitmode)
13231 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
13234 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13236 typedef struct proc {
13238 unsigned long reg_mask;
13239 unsigned long reg_offset;
13240 unsigned long fpreg_mask;
13241 unsigned long fpreg_offset;
13242 unsigned long frame_offset;
13243 unsigned long frame_reg;
13244 unsigned long pc_reg;
13247 static procS cur_proc;
13248 static procS *cur_proc_ptr;
13249 static int numprocs;
13251 /* Fill in an rs_align_code fragment. */
13254 mips_handle_align (fragp)
13257 if (fragp->fr_type != rs_align_code)
13260 if (mips_opts.mips16)
13262 static const unsigned char be_nop[] = { 0x65, 0x00 };
13263 static const unsigned char le_nop[] = { 0x00, 0x65 };
13268 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
13269 p = fragp->fr_literal + fragp->fr_fix;
13277 memcpy (p, (target_big_endian ? be_nop : le_nop), 2);
13281 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13292 /* check for premature end, nesting errors, etc */
13294 as_warn (_("missing .end at end of assembly"));
13303 if (*input_line_pointer == '-')
13305 ++input_line_pointer;
13308 if (!ISDIGIT (*input_line_pointer))
13309 as_bad (_("expected simple number"));
13310 if (input_line_pointer[0] == '0')
13312 if (input_line_pointer[1] == 'x')
13314 input_line_pointer += 2;
13315 while (ISXDIGIT (*input_line_pointer))
13318 val |= hex_value (*input_line_pointer++);
13320 return negative ? -val : val;
13324 ++input_line_pointer;
13325 while (ISDIGIT (*input_line_pointer))
13328 val |= *input_line_pointer++ - '0';
13330 return negative ? -val : val;
13333 if (!ISDIGIT (*input_line_pointer))
13335 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13336 *input_line_pointer, *input_line_pointer);
13337 as_warn (_("invalid number"));
13340 while (ISDIGIT (*input_line_pointer))
13343 val += *input_line_pointer++ - '0';
13345 return negative ? -val : val;
13348 /* The .file directive; just like the usual .file directive, but there
13349 is an initial number which is the ECOFF file index. */
13353 int x ATTRIBUTE_UNUSED;
13359 /* The .end directive. */
13363 int x ATTRIBUTE_UNUSED;
13368 /* Following functions need their own .frame and .cprestore directives. */
13369 mips_frame_reg_valid = 0;
13370 mips_cprestore_valid = 0;
13372 if (!is_end_of_line[(unsigned char) *input_line_pointer])
13375 demand_empty_rest_of_line ();
13380 #ifdef BFD_ASSEMBLER
13381 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
13386 if (now_seg != data_section && now_seg != bss_section)
13393 as_warn (_(".end not in text section"));
13397 as_warn (_(".end directive without a preceding .ent directive."));
13398 demand_empty_rest_of_line ();
13404 assert (S_GET_NAME (p));
13405 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym)))
13406 as_warn (_(".end symbol does not match .ent symbol."));
13409 as_warn (_(".end directive missing or unknown symbol"));
13411 #ifdef MIPS_STABS_ELF
13413 segT saved_seg = now_seg;
13414 subsegT saved_subseg = now_subseg;
13419 dot = frag_now_fix ();
13421 #ifdef md_flush_pending_output
13422 md_flush_pending_output ();
13426 subseg_set (pdr_seg, 0);
13428 /* Write the symbol. */
13429 exp.X_op = O_symbol;
13430 exp.X_add_symbol = p;
13431 exp.X_add_number = 0;
13432 emit_expr (&exp, 4);
13434 fragp = frag_more (7 * 4);
13436 md_number_to_chars (fragp, (valueT) cur_proc_ptr->reg_mask, 4);
13437 md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4);
13438 md_number_to_chars (fragp + 8, (valueT) cur_proc_ptr->fpreg_mask, 4);
13439 md_number_to_chars (fragp + 12, (valueT) cur_proc_ptr->fpreg_offset, 4);
13440 md_number_to_chars (fragp + 16, (valueT) cur_proc_ptr->frame_offset, 4);
13441 md_number_to_chars (fragp + 20, (valueT) cur_proc_ptr->frame_reg, 4);
13442 md_number_to_chars (fragp + 24, (valueT) cur_proc_ptr->pc_reg, 4);
13444 subseg_set (saved_seg, saved_subseg);
13446 #endif /* MIPS_STABS_ELF */
13448 cur_proc_ptr = NULL;
13451 /* The .aent and .ent directives. */
13460 symbolP = get_symbol ();
13461 if (*input_line_pointer == ',')
13462 ++input_line_pointer;
13463 SKIP_WHITESPACE ();
13464 if (ISDIGIT (*input_line_pointer)
13465 || *input_line_pointer == '-')
13468 #ifdef BFD_ASSEMBLER
13469 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
13474 if (now_seg != data_section && now_seg != bss_section)
13481 as_warn (_(".ent or .aent not in text section."));
13483 if (!aent && cur_proc_ptr)
13484 as_warn (_("missing .end"));
13488 /* This function needs its own .frame and .cprestore directives. */
13489 mips_frame_reg_valid = 0;
13490 mips_cprestore_valid = 0;
13492 cur_proc_ptr = &cur_proc;
13493 memset (cur_proc_ptr, '\0', sizeof (procS));
13495 cur_proc_ptr->isym = symbolP;
13497 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
13502 demand_empty_rest_of_line ();
13505 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13506 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13507 s_mips_frame is used so that we can set the PDR information correctly.
13508 We can't use the ecoff routines because they make reference to the ecoff
13509 symbol table (in the mdebug section). */
13512 s_mips_frame (ignore)
13513 int ignore ATTRIBUTE_UNUSED;
13515 #ifdef MIPS_STABS_ELF
13519 if (cur_proc_ptr == (procS *) NULL)
13521 as_warn (_(".frame outside of .ent"));
13522 demand_empty_rest_of_line ();
13526 cur_proc_ptr->frame_reg = tc_get_register (1);
13528 SKIP_WHITESPACE ();
13529 if (*input_line_pointer++ != ','
13530 || get_absolute_expression_and_terminator (&val) != ',')
13532 as_warn (_("Bad .frame directive"));
13533 --input_line_pointer;
13534 demand_empty_rest_of_line ();
13538 cur_proc_ptr->frame_offset = val;
13539 cur_proc_ptr->pc_reg = tc_get_register (0);
13541 demand_empty_rest_of_line ();
13544 #endif /* MIPS_STABS_ELF */
13547 /* The .fmask and .mask directives. If the mdebug section is present
13548 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13549 embedded targets, s_mips_mask is used so that we can set the PDR
13550 information correctly. We can't use the ecoff routines because they
13551 make reference to the ecoff symbol table (in the mdebug section). */
13554 s_mips_mask (reg_type)
13557 #ifdef MIPS_STABS_ELF
13560 if (cur_proc_ptr == (procS *) NULL)
13562 as_warn (_(".mask/.fmask outside of .ent"));
13563 demand_empty_rest_of_line ();
13567 if (get_absolute_expression_and_terminator (&mask) != ',')
13569 as_warn (_("Bad .mask/.fmask directive"));
13570 --input_line_pointer;
13571 demand_empty_rest_of_line ();
13575 off = get_absolute_expression ();
13577 if (reg_type == 'F')
13579 cur_proc_ptr->fpreg_mask = mask;
13580 cur_proc_ptr->fpreg_offset = off;
13584 cur_proc_ptr->reg_mask = mask;
13585 cur_proc_ptr->reg_offset = off;
13588 demand_empty_rest_of_line ();
13590 s_ignore (reg_type);
13591 #endif /* MIPS_STABS_ELF */
13594 /* The .loc directive. */
13605 assert (now_seg == text_section);
13607 lineno = get_number ();
13608 addroff = frag_now_fix ();
13610 symbolP = symbol_new ("", N_SLINE, addroff, frag_now);
13611 S_SET_TYPE (symbolP, N_SLINE);
13612 S_SET_OTHER (symbolP, 0);
13613 S_SET_DESC (symbolP, lineno);
13614 symbolP->sy_segment = now_seg;
13618 /* CPU name/ISA/number mapping table.
13620 Entries are grouped by type. The first matching CPU or ISA entry
13621 gets chosen by CPU or ISA, so it should be the 'canonical' name
13622 for that type. Entries after that within the type are sorted
13625 Case is ignored in comparison, so put the canonical entry in the
13626 appropriate case but everything else in lower case to ease eye pain. */
13627 static const struct mips_cpu_info mips_cpu_info_table[] =
13630 { "MIPS1", 1, ISA_MIPS1, CPU_R3000, },
13631 { "mips", 1, ISA_MIPS1, CPU_R3000, },
13634 { "MIPS2", 1, ISA_MIPS2, CPU_R6000, },
13637 { "MIPS3", 1, ISA_MIPS3, CPU_R4000, },
13640 { "MIPS4", 1, ISA_MIPS4, CPU_R8000, },
13643 { "MIPS5", 1, ISA_MIPS5, CPU_MIPS5, },
13644 { "Generic-MIPS5", 0, ISA_MIPS5, CPU_MIPS5, },
13647 { "MIPS32", 1, ISA_MIPS32, CPU_MIPS32, },
13648 { "mipsisa32", 0, ISA_MIPS32, CPU_MIPS32, },
13649 { "Generic-MIPS32", 0, ISA_MIPS32, CPU_MIPS32, },
13650 { "4kc", 0, ISA_MIPS32, CPU_MIPS32, },
13651 { "4km", 0, ISA_MIPS32, CPU_MIPS32, },
13652 { "4kp", 0, ISA_MIPS32, CPU_MIPS32, },
13654 /* For historical reasons. */
13655 { "MIPS64", 1, ISA_MIPS3, CPU_R4000, },
13658 { "mipsisa64", 1, ISA_MIPS64, CPU_MIPS64, },
13659 { "Generic-MIPS64", 0, ISA_MIPS64, CPU_MIPS64, },
13660 { "5kc", 0, ISA_MIPS64, CPU_MIPS64, },
13661 { "20kc", 0, ISA_MIPS64, CPU_MIPS64, },
13664 { "R2000", 0, ISA_MIPS1, CPU_R2000, },
13665 { "2000", 0, ISA_MIPS1, CPU_R2000, },
13666 { "2k", 0, ISA_MIPS1, CPU_R2000, },
13667 { "r2k", 0, ISA_MIPS1, CPU_R2000, },
13670 { "R3000", 0, ISA_MIPS1, CPU_R3000, },
13671 { "3000", 0, ISA_MIPS1, CPU_R3000, },
13672 { "3k", 0, ISA_MIPS1, CPU_R3000, },
13673 { "r3k", 0, ISA_MIPS1, CPU_R3000, },
13676 { "R3900", 0, ISA_MIPS1, CPU_R3900, },
13677 { "3900", 0, ISA_MIPS1, CPU_R3900, },
13678 { "mipstx39", 0, ISA_MIPS1, CPU_R3900, },
13681 { "R4000", 0, ISA_MIPS3, CPU_R4000, },
13682 { "4000", 0, ISA_MIPS3, CPU_R4000, },
13683 { "4k", 0, ISA_MIPS3, CPU_R4000, }, /* beware */
13684 { "r4k", 0, ISA_MIPS3, CPU_R4000, },
13687 { "R4010", 0, ISA_MIPS2, CPU_R4010, },
13688 { "4010", 0, ISA_MIPS2, CPU_R4010, },
13691 { "R4400", 0, ISA_MIPS3, CPU_R4400, },
13692 { "4400", 0, ISA_MIPS3, CPU_R4400, },
13695 { "R4600", 0, ISA_MIPS3, CPU_R4600, },
13696 { "4600", 0, ISA_MIPS3, CPU_R4600, },
13697 { "mips64orion", 0, ISA_MIPS3, CPU_R4600, },
13698 { "orion", 0, ISA_MIPS3, CPU_R4600, },
13701 { "R4650", 0, ISA_MIPS3, CPU_R4650, },
13702 { "4650", 0, ISA_MIPS3, CPU_R4650, },
13705 { "R6000", 0, ISA_MIPS2, CPU_R6000, },
13706 { "6000", 0, ISA_MIPS2, CPU_R6000, },
13707 { "6k", 0, ISA_MIPS2, CPU_R6000, },
13708 { "r6k", 0, ISA_MIPS2, CPU_R6000, },
13711 { "R8000", 0, ISA_MIPS4, CPU_R8000, },
13712 { "8000", 0, ISA_MIPS4, CPU_R8000, },
13713 { "8k", 0, ISA_MIPS4, CPU_R8000, },
13714 { "r8k", 0, ISA_MIPS4, CPU_R8000, },
13717 { "R10000", 0, ISA_MIPS4, CPU_R10000, },
13718 { "10000", 0, ISA_MIPS4, CPU_R10000, },
13719 { "10k", 0, ISA_MIPS4, CPU_R10000, },
13720 { "r10k", 0, ISA_MIPS4, CPU_R10000, },
13723 { "R12000", 0, ISA_MIPS4, CPU_R12000, },
13724 { "12000", 0, ISA_MIPS4, CPU_R12000, },
13725 { "12k", 0, ISA_MIPS4, CPU_R12000, },
13726 { "r12k", 0, ISA_MIPS4, CPU_R12000, },
13729 { "VR4100", 0, ISA_MIPS3, CPU_VR4100, },
13730 { "4100", 0, ISA_MIPS3, CPU_VR4100, },
13731 { "mips64vr4100", 0, ISA_MIPS3, CPU_VR4100, },
13732 { "r4100", 0, ISA_MIPS3, CPU_VR4100, },
13735 { "VR4111", 0, ISA_MIPS3, CPU_R4111, },
13736 { "4111", 0, ISA_MIPS3, CPU_R4111, },
13737 { "mips64vr4111", 0, ISA_MIPS3, CPU_R4111, },
13738 { "r4111", 0, ISA_MIPS3, CPU_R4111, },
13741 { "VR4300", 0, ISA_MIPS3, CPU_R4300, },
13742 { "4300", 0, ISA_MIPS3, CPU_R4300, },
13743 { "mips64vr4300", 0, ISA_MIPS3, CPU_R4300, },
13744 { "r4300", 0, ISA_MIPS3, CPU_R4300, },
13747 { "VR5000", 0, ISA_MIPS4, CPU_R5000, },
13748 { "5000", 0, ISA_MIPS4, CPU_R5000, },
13749 { "5k", 0, ISA_MIPS4, CPU_R5000, },
13750 { "mips64vr5000", 0, ISA_MIPS4, CPU_R5000, },
13751 { "r5000", 0, ISA_MIPS4, CPU_R5000, },
13752 { "r5200", 0, ISA_MIPS4, CPU_R5000, },
13753 { "rm5200", 0, ISA_MIPS4, CPU_R5000, },
13754 { "r5230", 0, ISA_MIPS4, CPU_R5000, },
13755 { "rm5230", 0, ISA_MIPS4, CPU_R5000, },
13756 { "r5231", 0, ISA_MIPS4, CPU_R5000, },
13757 { "rm5231", 0, ISA_MIPS4, CPU_R5000, },
13758 { "r5261", 0, ISA_MIPS4, CPU_R5000, },
13759 { "rm5261", 0, ISA_MIPS4, CPU_R5000, },
13760 { "r5721", 0, ISA_MIPS4, CPU_R5000, },
13761 { "rm5721", 0, ISA_MIPS4, CPU_R5000, },
13762 { "r5k", 0, ISA_MIPS4, CPU_R5000, },
13763 { "r7000", 0, ISA_MIPS4, CPU_R5000, },
13765 /* Broadcom SB-1 CPU */
13766 { "SB-1", 0, ISA_MIPS64, CPU_SB1, },
13767 { "sb-1250", 0, ISA_MIPS64, CPU_SB1, },
13768 { "sb1", 0, ISA_MIPS64, CPU_SB1, },
13769 { "sb1250", 0, ISA_MIPS64, CPU_SB1, },
13772 { NULL, 0, 0, 0, },
13775 static const struct mips_cpu_info *
13776 mips_cpu_info_from_name (name)
13781 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
13782 if (strcasecmp (name, mips_cpu_info_table[i].name) == 0)
13783 return (&mips_cpu_info_table[i]);
13788 static const struct mips_cpu_info *
13789 mips_cpu_info_from_isa (isa)
13794 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
13795 if (mips_cpu_info_table[i].is_isa
13796 && isa == mips_cpu_info_table[i].isa)
13797 return (&mips_cpu_info_table[i]);
13802 static const struct mips_cpu_info *
13803 mips_cpu_info_from_cpu (cpu)
13808 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
13809 if (!mips_cpu_info_table[i].is_isa
13810 && cpu == mips_cpu_info_table[i].cpu)
13811 return (&mips_cpu_info_table[i]);