1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
38 #include "opcode/mips.h"
40 #include "dwarf2dbg.h"
43 #define DBG(x) printf x
49 /* Clean up namespace so we can include obj-elf.h too. */
50 static int mips_output_flavor PARAMS ((void));
51 static int mips_output_flavor () { return OUTPUT_FLAVOR; }
52 #undef OBJ_PROCESS_STAB
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
80 int mips_flag_mdebug = -1;
84 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
85 static char *mips_regmask_frag;
91 #define PIC_CALL_REG 25
99 #define ILLEGAL_REG (32)
101 /* Allow override of standard little-endian ECOFF format. */
103 #ifndef ECOFF_LITTLE_FORMAT
104 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
107 extern int target_big_endian;
109 /* The name of the readonly data section. */
110 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
112 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
114 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
120 /* The ABI to use. */
131 /* MIPS ABI we are using for this output file. */
132 static enum mips_abi_level mips_abi = NO_ABI;
134 /* This is the set of options which may be modified by the .set
135 pseudo-op. We use a struct so that .set push and .set pop are more
138 struct mips_set_options
140 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
141 if it has not been initialized. Changed by `.set mipsN', and the
142 -mipsN command line option, and the default CPU. */
144 /* Enabled Application Specific Extensions (ASEs). These are set to -1
145 if they have not been initialized. Changed by `.set <asename>', by
146 command line options, and based on the default architecture. */
149 /* Whether we are assembling for the mips16 processor. 0 if we are
150 not, 1 if we are, and -1 if the value has not been initialized.
151 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
152 -nomips16 command line options, and the default CPU. */
154 /* Non-zero if we should not reorder instructions. Changed by `.set
155 reorder' and `.set noreorder'. */
157 /* Non-zero if we should not permit the $at ($1) register to be used
158 in instructions. Changed by `.set at' and `.set noat'. */
160 /* Non-zero if we should warn when a macro instruction expands into
161 more than one machine instruction. Changed by `.set nomacro' and
163 int warn_about_macros;
164 /* Non-zero if we should not move instructions. Changed by `.set
165 move', `.set volatile', `.set nomove', and `.set novolatile'. */
167 /* Non-zero if we should not optimize branches by moving the target
168 of the branch into the delay slot. Actually, we don't perform
169 this optimization anyhow. Changed by `.set bopt' and `.set
172 /* Non-zero if we should not autoextend mips16 instructions.
173 Changed by `.set autoextend' and `.set noautoextend'. */
175 /* Restrict general purpose registers and floating point registers
176 to 32 bit. This is initially determined when -mgp32 or -mfp32
177 is passed but can changed if the assembler code uses .set mipsN. */
182 /* True if -mgp32 was passed. */
183 static int file_mips_gp32 = -1;
185 /* True if -mfp32 was passed. */
186 static int file_mips_fp32 = -1;
188 /* This is the struct we use to hold the current set of options. Note
189 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
190 -1 to indicate that they have not been initialized. */
192 static struct mips_set_options mips_opts =
194 ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0
197 /* These variables are filled in with the masks of registers used.
198 The object format code reads them and puts them in the appropriate
200 unsigned long mips_gprmask;
201 unsigned long mips_cprmask[4];
203 /* MIPS ISA we are using for this output file. */
204 static int file_mips_isa = ISA_UNKNOWN;
206 /* True if -mips16 was passed or implied by arguments passed on the
207 command line (e.g., by -march). */
208 static int file_ase_mips16;
210 /* True if -mips3d was passed or implied by arguments passed on the
211 command line (e.g., by -march). */
212 static int file_ase_mips3d;
214 /* True if -mdmx was passed or implied by arguments passed on the
215 command line (e.g., by -march). */
216 static int file_ase_mdmx;
218 /* The argument of the -march= flag. The architecture we are assembling. */
219 static int mips_arch = CPU_UNKNOWN;
220 static const char *mips_arch_string;
221 static const struct mips_cpu_info *mips_arch_info;
223 /* The argument of the -mtune= flag. The architecture for which we
225 static int mips_tune = CPU_UNKNOWN;
226 static const char *mips_tune_string;
227 static const struct mips_cpu_info *mips_tune_info;
229 /* True when generating 32-bit code for a 64-bit processor. */
230 static int mips_32bitmode = 0;
232 /* Some ISA's have delay slots for instructions which read or write
233 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
234 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
235 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
236 delay slot in this ISA. The uses of this macro assume that any
237 ISA that has delay slots for one of these, has them for all. They
238 also assume that ISAs which don't have delays for these insns, don't
239 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
240 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
242 || (ISA) == ISA_MIPS2 \
243 || (ISA) == ISA_MIPS3 \
246 /* True if the given ABI requires 32-bit registers. */
247 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
249 /* Likewise 64-bit registers. */
250 #define ABI_NEEDS_64BIT_REGS(ABI) \
252 || (ABI) == N64_ABI \
255 /* Return true if ISA supports 64 bit gp register instructions. */
256 #define ISA_HAS_64BIT_REGS(ISA) ( \
258 || (ISA) == ISA_MIPS4 \
259 || (ISA) == ISA_MIPS5 \
260 || (ISA) == ISA_MIPS64 \
263 #define HAVE_32BIT_GPRS \
264 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
266 #define HAVE_32BIT_FPRS \
267 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
269 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
270 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
272 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
274 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
276 /* We can only have 64bit addresses if the object file format
278 #define HAVE_32BIT_ADDRESSES \
280 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
281 || ! HAVE_64BIT_OBJECTS) \
282 && mips_pic != EMBEDDED_PIC))
284 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
286 /* Return true if the given CPU supports the MIPS16 ASE. */
287 #define CPU_HAS_MIPS16(cpu) \
288 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0)
290 /* Return true if the given CPU supports the MIPS3D ASE. */
291 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
294 /* Return true if the given CPU supports the MDMX ASE. */
295 #define CPU_HAS_MDMX(cpu) (false \
298 /* Whether the processor uses hardware interlocks to protect
299 reads from the HI and LO registers, and thus does not
300 require nops to be inserted. */
302 #define hilo_interlocks (mips_arch == CPU_R4010 \
303 || mips_arch == CPU_SB1 \
306 /* Whether the processor uses hardware interlocks to protect reads
307 from the GPRs, and thus does not require nops to be inserted. */
308 #define gpr_interlocks \
309 (mips_opts.isa != ISA_MIPS1 \
310 || mips_arch == CPU_R3900)
312 /* As with other "interlocks" this is used by hardware that has FP
313 (co-processor) interlocks. */
314 /* Itbl support may require additional care here. */
315 #define cop_interlocks (mips_arch == CPU_R4300 \
316 || mips_arch == CPU_SB1 \
319 /* Is this a mfhi or mflo instruction? */
320 #define MF_HILO_INSN(PINFO) \
321 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
323 /* MIPS PIC level. */
325 enum mips_pic_level mips_pic;
327 /* Warn about all NOPS that the assembler generates. */
328 static int warn_nops = 0;
330 /* 1 if we should generate 32 bit offsets from the $gp register in
331 SVR4_PIC mode. Currently has no meaning in other modes. */
332 static int mips_big_got = 0;
334 /* 1 if trap instructions should used for overflow rather than break
336 static int mips_trap = 0;
338 /* 1 if double width floating point constants should not be constructed
339 by assembling two single width halves into two single width floating
340 point registers which just happen to alias the double width destination
341 register. On some architectures this aliasing can be disabled by a bit
342 in the status register, and the setting of this bit cannot be determined
343 automatically at assemble time. */
344 static int mips_disable_float_construction;
346 /* Non-zero if any .set noreorder directives were used. */
348 static int mips_any_noreorder;
350 /* Non-zero if nops should be inserted when the register referenced in
351 an mfhi/mflo instruction is read in the next two instructions. */
352 static int mips_7000_hilo_fix;
354 /* The size of the small data section. */
355 static unsigned int g_switch_value = 8;
356 /* Whether the -G option was used. */
357 static int g_switch_seen = 0;
362 /* If we can determine in advance that GP optimization won't be
363 possible, we can skip the relaxation stuff that tries to produce
364 GP-relative references. This makes delay slot optimization work
367 This function can only provide a guess, but it seems to work for
368 gcc output. It needs to guess right for gcc, otherwise gcc
369 will put what it thinks is a GP-relative instruction in a branch
372 I don't know if a fix is needed for the SVR4_PIC mode. I've only
373 fixed it for the non-PIC mode. KR 95/04/07 */
374 static int nopic_need_relax PARAMS ((symbolS *, int));
376 /* handle of the OPCODE hash table */
377 static struct hash_control *op_hash = NULL;
379 /* The opcode hash table we use for the mips16. */
380 static struct hash_control *mips16_op_hash = NULL;
382 /* This array holds the chars that always start a comment. If the
383 pre-processor is disabled, these aren't very useful */
384 const char comment_chars[] = "#";
386 /* This array holds the chars that only start a comment at the beginning of
387 a line. If the line seems to have the form '# 123 filename'
388 .line and .file directives will appear in the pre-processed output */
389 /* Note that input_file.c hand checks for '#' at the beginning of the
390 first line of the input file. This is because the compiler outputs
391 #NO_APP at the beginning of its output. */
392 /* Also note that C style comments are always supported. */
393 const char line_comment_chars[] = "#";
395 /* This array holds machine specific line separator characters. */
396 const char line_separator_chars[] = ";";
398 /* Chars that can be used to separate mant from exp in floating point nums */
399 const char EXP_CHARS[] = "eE";
401 /* Chars that mean this number is a floating point constant */
404 const char FLT_CHARS[] = "rRsSfFdDxXpP";
406 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
407 changed in read.c . Ideally it shouldn't have to know about it at all,
408 but nothing is ideal around here.
411 static char *insn_error;
413 static int auto_align = 1;
415 /* When outputting SVR4 PIC code, the assembler needs to know the
416 offset in the stack frame from which to restore the $gp register.
417 This is set by the .cprestore pseudo-op, and saved in this
419 static offsetT mips_cprestore_offset = -1;
421 /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some
422 more optimizations, it can use a register value instead of a memory-saved
423 offset and even an other register than $gp as global pointer. */
424 static offsetT mips_cpreturn_offset = -1;
425 static int mips_cpreturn_register = -1;
426 static int mips_gp_register = GP;
427 static int mips_gprel_offset = 0;
429 /* Whether mips_cprestore_offset has been set in the current function
430 (or whether it has already been warned about, if not). */
431 static int mips_cprestore_valid = 0;
433 /* This is the register which holds the stack frame, as set by the
434 .frame pseudo-op. This is needed to implement .cprestore. */
435 static int mips_frame_reg = SP;
437 /* Whether mips_frame_reg has been set in the current function
438 (or whether it has already been warned about, if not). */
439 static int mips_frame_reg_valid = 0;
441 /* To output NOP instructions correctly, we need to keep information
442 about the previous two instructions. */
444 /* Whether we are optimizing. The default value of 2 means to remove
445 unneeded NOPs and swap branch instructions when possible. A value
446 of 1 means to not swap branches. A value of 0 means to always
448 static int mips_optimize = 2;
450 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
451 equivalent to seeing no -g option at all. */
452 static int mips_debug = 0;
454 /* The previous instruction. */
455 static struct mips_cl_insn prev_insn;
457 /* The instruction before prev_insn. */
458 static struct mips_cl_insn prev_prev_insn;
460 /* If we don't want information for prev_insn or prev_prev_insn, we
461 point the insn_mo field at this dummy integer. */
462 static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 };
464 /* Non-zero if prev_insn is valid. */
465 static int prev_insn_valid;
467 /* The frag for the previous instruction. */
468 static struct frag *prev_insn_frag;
470 /* The offset into prev_insn_frag for the previous instruction. */
471 static long prev_insn_where;
473 /* The reloc type for the previous instruction, if any. */
474 static bfd_reloc_code_real_type prev_insn_reloc_type[3];
476 /* The reloc for the previous instruction, if any. */
477 static fixS *prev_insn_fixp[3];
479 /* Non-zero if the previous instruction was in a delay slot. */
480 static int prev_insn_is_delay_slot;
482 /* Non-zero if the previous instruction was in a .set noreorder. */
483 static int prev_insn_unreordered;
485 /* Non-zero if the previous instruction uses an extend opcode (if
487 static int prev_insn_extended;
489 /* Non-zero if the previous previous instruction was in a .set
491 static int prev_prev_insn_unreordered;
493 /* If this is set, it points to a frag holding nop instructions which
494 were inserted before the start of a noreorder section. If those
495 nops turn out to be unnecessary, the size of the frag can be
497 static fragS *prev_nop_frag;
499 /* The number of nop instructions we created in prev_nop_frag. */
500 static int prev_nop_frag_holds;
502 /* The number of nop instructions that we know we need in
504 static int prev_nop_frag_required;
506 /* The number of instructions we've seen since prev_nop_frag. */
507 static int prev_nop_frag_since;
509 /* For ECOFF and ELF, relocations against symbols are done in two
510 parts, with a HI relocation and a LO relocation. Each relocation
511 has only 16 bits of space to store an addend. This means that in
512 order for the linker to handle carries correctly, it must be able
513 to locate both the HI and the LO relocation. This means that the
514 relocations must appear in order in the relocation table.
516 In order to implement this, we keep track of each unmatched HI
517 relocation. We then sort them so that they immediately precede the
518 corresponding LO relocation. */
523 struct mips_hi_fixup *next;
526 /* The section this fixup is in. */
530 /* The list of unmatched HI relocs. */
532 static struct mips_hi_fixup *mips_hi_fixup_list;
534 /* Map normal MIPS register numbers to mips16 register numbers. */
536 #define X ILLEGAL_REG
537 static const int mips32_to_16_reg_map[] =
539 X, X, 2, 3, 4, 5, 6, 7,
540 X, X, X, X, X, X, X, X,
541 0, 1, X, X, X, X, X, X,
542 X, X, X, X, X, X, X, X
546 /* Map mips16 register numbers to normal MIPS register numbers. */
548 static const unsigned int mips16_to_32_reg_map[] =
550 16, 17, 2, 3, 4, 5, 6, 7
553 /* Since the MIPS does not have multiple forms of PC relative
554 instructions, we do not have to do relaxing as is done on other
555 platforms. However, we do have to handle GP relative addressing
556 correctly, which turns out to be a similar problem.
558 Every macro that refers to a symbol can occur in (at least) two
559 forms, one with GP relative addressing and one without. For
560 example, loading a global variable into a register generally uses
561 a macro instruction like this:
563 If i can be addressed off the GP register (this is true if it is in
564 the .sbss or .sdata section, or if it is known to be smaller than
565 the -G argument) this will generate the following instruction:
567 This instruction will use a GPREL reloc. If i can not be addressed
568 off the GP register, the following instruction sequence will be used:
571 In this case the first instruction will have a HI16 reloc, and the
572 second reloc will have a LO16 reloc. Both relocs will be against
575 The issue here is that we may not know whether i is GP addressable
576 until after we see the instruction that uses it. Therefore, we
577 want to be able to choose the final instruction sequence only at
578 the end of the assembly. This is similar to the way other
579 platforms choose the size of a PC relative instruction only at the
582 When generating position independent code we do not use GP
583 addressing in quite the same way, but the issue still arises as
584 external symbols and local symbols must be handled differently.
586 We handle these issues by actually generating both possible
587 instruction sequences. The longer one is put in a frag_var with
588 type rs_machine_dependent. We encode what to do with the frag in
589 the subtype field. We encode (1) the number of existing bytes to
590 replace, (2) the number of new bytes to use, (3) the offset from
591 the start of the existing bytes to the first reloc we must generate
592 (that is, the offset is applied from the start of the existing
593 bytes after they are replaced by the new bytes, if any), (4) the
594 offset from the start of the existing bytes to the second reloc,
595 (5) whether a third reloc is needed (the third reloc is always four
596 bytes after the second reloc), and (6) whether to warn if this
597 variant is used (this is sometimes needed if .set nomacro or .set
598 noat is in effect). All these numbers are reasonably small.
600 Generating two instruction sequences must be handled carefully to
601 ensure that delay slots are handled correctly. Fortunately, there
602 are a limited number of cases. When the second instruction
603 sequence is generated, append_insn is directed to maintain the
604 existing delay slot information, so it continues to apply to any
605 code after the second instruction sequence. This means that the
606 second instruction sequence must not impose any requirements not
607 required by the first instruction sequence.
609 These variant frags are then handled in functions called by the
610 machine independent code. md_estimate_size_before_relax returns
611 the final size of the frag. md_convert_frag sets up the final form
612 of the frag. tc_gen_reloc adjust the first reloc and adds a second
614 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
618 | (((reloc1) + 64) << 9) \
619 | (((reloc2) + 64) << 2) \
620 | ((reloc3) ? (1 << 1) : 0) \
622 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
623 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
624 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
625 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
626 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
627 #define RELAX_WARN(i) ((i) & 1)
629 /* For mips16 code, we use an entirely different form of relaxation.
630 mips16 supports two versions of most instructions which take
631 immediate values: a small one which takes some small value, and a
632 larger one which takes a 16 bit value. Since branches also follow
633 this pattern, relaxing these values is required.
635 We can assemble both mips16 and normal MIPS code in a single
636 object. Therefore, we need to support this type of relaxation at
637 the same time that we support the relaxation described above. We
638 use the high bit of the subtype field to distinguish these cases.
640 The information we store for this type of relaxation is the
641 argument code found in the opcode file for this relocation, whether
642 the user explicitly requested a small or extended form, and whether
643 the relocation is in a jump or jal delay slot. That tells us the
644 size of the value, and how it should be stored. We also store
645 whether the fragment is considered to be extended or not. We also
646 store whether this is known to be a branch to a different section,
647 whether we have tried to relax this frag yet, and whether we have
648 ever extended a PC relative fragment because of a shift count. */
649 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
652 | ((small) ? 0x100 : 0) \
653 | ((ext) ? 0x200 : 0) \
654 | ((dslot) ? 0x400 : 0) \
655 | ((jal_dslot) ? 0x800 : 0))
656 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
657 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
658 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
659 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
660 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
661 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
662 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
663 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
664 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
665 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
666 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
667 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
669 /* Prototypes for static functions. */
672 #define internalError() \
673 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
675 #define internalError() as_fatal (_("MIPS internal Error"));
678 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
680 static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip,
681 unsigned int reg, enum mips_regclass class));
682 static int reg_needs_delay PARAMS ((unsigned int));
683 static void mips16_mark_labels PARAMS ((void));
684 static void append_insn PARAMS ((char *place,
685 struct mips_cl_insn * ip,
687 bfd_reloc_code_real_type *r,
689 static void mips_no_prev_insn PARAMS ((int));
690 static void mips_emit_delays PARAMS ((boolean));
692 static void macro_build PARAMS ((char *place, int *counter, expressionS * ep,
693 const char *name, const char *fmt,
696 static void macro_build ();
698 static void mips16_macro_build PARAMS ((char *, int *, expressionS *,
699 const char *, const char *,
701 static void macro_build_jalr PARAMS ((int, expressionS *));
702 static void macro_build_lui PARAMS ((char *place, int *counter,
703 expressionS * ep, int regnum));
704 static void set_at PARAMS ((int *counter, int reg, int unsignedp));
705 static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip,
707 static void load_register PARAMS ((int *, int, expressionS *, int));
708 static void load_address PARAMS ((int *, int, expressionS *, int *));
709 static void move_register PARAMS ((int *, int, int));
710 static void macro PARAMS ((struct mips_cl_insn * ip));
711 static void mips16_macro PARAMS ((struct mips_cl_insn * ip));
712 #ifdef LOSING_COMPILER
713 static void macro2 PARAMS ((struct mips_cl_insn * ip));
715 static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip));
716 static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip));
717 static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean,
718 boolean, boolean, unsigned long *,
719 boolean *, unsigned short *));
720 static int my_getPercentOp PARAMS ((char **, unsigned int *, int *));
721 static int my_getSmallParser PARAMS ((char **, unsigned int *, int *));
722 static int my_getSmallExpression PARAMS ((expressionS *, char *));
723 static void my_getExpression PARAMS ((expressionS *, char *));
725 static int support_64bit_objects PARAMS((void));
727 static void mips_set_option_string PARAMS ((const char **, const char *));
728 static symbolS *get_symbol PARAMS ((void));
729 static void mips_align PARAMS ((int to, int fill, symbolS *label));
730 static void s_align PARAMS ((int));
731 static void s_change_sec PARAMS ((int));
732 static void s_change_section PARAMS ((int));
733 static void s_cons PARAMS ((int));
734 static void s_float_cons PARAMS ((int));
735 static void s_mips_globl PARAMS ((int));
736 static void s_option PARAMS ((int));
737 static void s_mipsset PARAMS ((int));
738 static void s_abicalls PARAMS ((int));
739 static void s_cpload PARAMS ((int));
740 static void s_cpsetup PARAMS ((int));
741 static void s_cplocal PARAMS ((int));
742 static void s_cprestore PARAMS ((int));
743 static void s_cpreturn PARAMS ((int));
744 static void s_gpvalue PARAMS ((int));
745 static void s_gpword PARAMS ((int));
746 static void s_cpadd PARAMS ((int));
747 static void s_insn PARAMS ((int));
748 static void md_obj_begin PARAMS ((void));
749 static void md_obj_end PARAMS ((void));
750 static long get_number PARAMS ((void));
751 static void s_mips_ent PARAMS ((int));
752 static void s_mips_end PARAMS ((int));
753 static void s_mips_frame PARAMS ((int));
754 static void s_mips_mask PARAMS ((int));
755 static void s_mips_stab PARAMS ((int));
756 static void s_mips_weakext PARAMS ((int));
757 static void s_mips_file PARAMS ((int));
758 static void s_mips_loc PARAMS ((int));
759 static int mips16_extended_frag PARAMS ((fragS *, asection *, long));
760 static int validate_mips_insn PARAMS ((const struct mips_opcode *));
761 static void show PARAMS ((FILE *, const char *, int *, int *));
763 static int mips_need_elf_addend_fixup PARAMS ((fixS *));
766 /* Return values of my_getSmallExpression(). */
773 /* Direct relocation creation by %percent_op(). */
792 /* Table and functions used to map between CPU/ISA names, and
793 ISA levels, and CPU numbers. */
797 const char *name; /* CPU or ISA name. */
798 int is_isa; /* Is this an ISA? (If 0, a CPU.) */
799 int isa; /* ISA level. */
800 int cpu; /* CPU number (default CPU if ISA). */
803 static void mips_set_architecture PARAMS ((const struct mips_cpu_info *));
804 static void mips_set_tune PARAMS ((const struct mips_cpu_info *));
805 static boolean mips_strict_matching_cpu_name_p PARAMS ((const char *,
807 static boolean mips_matching_cpu_name_p PARAMS ((const char *, const char *));
808 static const struct mips_cpu_info *mips_parse_cpu PARAMS ((const char *,
810 static const struct mips_cpu_info *mips_cpu_info_from_isa PARAMS ((int));
814 The following pseudo-ops from the Kane and Heinrich MIPS book
815 should be defined here, but are currently unsupported: .alias,
816 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
818 The following pseudo-ops from the Kane and Heinrich MIPS book are
819 specific to the type of debugging information being generated, and
820 should be defined by the object format: .aent, .begin, .bend,
821 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
824 The following pseudo-ops from the Kane and Heinrich MIPS book are
825 not MIPS CPU specific, but are also not specific to the object file
826 format. This file is probably the best place to define them, but
827 they are not currently supported: .asm0, .endr, .lab, .repeat,
830 static const pseudo_typeS mips_pseudo_table[] =
832 /* MIPS specific pseudo-ops. */
833 {"option", s_option, 0},
834 {"set", s_mipsset, 0},
835 {"rdata", s_change_sec, 'r'},
836 {"sdata", s_change_sec, 's'},
837 {"livereg", s_ignore, 0},
838 {"abicalls", s_abicalls, 0},
839 {"cpload", s_cpload, 0},
840 {"cpsetup", s_cpsetup, 0},
841 {"cplocal", s_cplocal, 0},
842 {"cprestore", s_cprestore, 0},
843 {"cpreturn", s_cpreturn, 0},
844 {"gpvalue", s_gpvalue, 0},
845 {"gpword", s_gpword, 0},
846 {"cpadd", s_cpadd, 0},
849 /* Relatively generic pseudo-ops that happen to be used on MIPS
851 {"asciiz", stringer, 1},
852 {"bss", s_change_sec, 'b'},
855 {"dword", s_cons, 3},
856 {"weakext", s_mips_weakext, 0},
858 /* These pseudo-ops are defined in read.c, but must be overridden
859 here for one reason or another. */
860 {"align", s_align, 0},
862 {"data", s_change_sec, 'd'},
863 {"double", s_float_cons, 'd'},
864 {"float", s_float_cons, 'f'},
865 {"globl", s_mips_globl, 0},
866 {"global", s_mips_globl, 0},
867 {"hword", s_cons, 1},
872 {"section", s_change_section, 0},
873 {"short", s_cons, 1},
874 {"single", s_float_cons, 'f'},
875 {"stabn", s_mips_stab, 'n'},
876 {"text", s_change_sec, 't'},
879 { "extern", ecoff_directive_extern, 0},
884 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
886 /* These pseudo-ops should be defined by the object file format.
887 However, a.out doesn't support them, so we have versions here. */
888 {"aent", s_mips_ent, 1},
889 {"bgnb", s_ignore, 0},
890 {"end", s_mips_end, 0},
891 {"endb", s_ignore, 0},
892 {"ent", s_mips_ent, 0},
893 {"file", s_mips_file, 0},
894 {"fmask", s_mips_mask, 'F'},
895 {"frame", s_mips_frame, 0},
896 {"loc", s_mips_loc, 0},
897 {"mask", s_mips_mask, 'R'},
898 {"verstamp", s_ignore, 0},
902 extern void pop_insert PARAMS ((const pseudo_typeS *));
907 pop_insert (mips_pseudo_table);
908 if (! ECOFF_DEBUGGING)
909 pop_insert (mips_nonecoff_pseudo_table);
912 /* Symbols labelling the current insn. */
914 struct insn_label_list
916 struct insn_label_list *next;
920 static struct insn_label_list *insn_labels;
921 static struct insn_label_list *free_insn_labels;
923 static void mips_clear_insn_labels PARAMS ((void));
926 mips_clear_insn_labels ()
928 register struct insn_label_list **pl;
930 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
936 static char *expr_end;
938 /* Expressions which appear in instructions. These are set by
941 static expressionS imm_expr;
942 static expressionS offset_expr;
944 /* Relocs associated with imm_expr and offset_expr. */
946 static bfd_reloc_code_real_type imm_reloc[3]
947 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
948 static bfd_reloc_code_real_type offset_reloc[3]
949 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
951 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
953 static boolean imm_unmatched_hi;
955 /* These are set by mips16_ip if an explicit extension is used. */
957 static boolean mips16_small, mips16_ext;
959 /* The pdr segment for per procedure frame/regmask info. Not used for
964 /* The default target format to use. */
967 mips_target_format ()
969 switch (OUTPUT_FLAVOR)
971 case bfd_target_aout_flavour:
972 return target_big_endian ? "a.out-mips-big" : "a.out-mips-little";
973 case bfd_target_ecoff_flavour:
974 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
975 case bfd_target_coff_flavour:
977 case bfd_target_elf_flavour:
979 /* This is traditional mips. */
980 return (target_big_endian
981 ? (HAVE_64BIT_OBJECTS
982 ? "elf64-tradbigmips"
984 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
985 : (HAVE_64BIT_OBJECTS
986 ? "elf64-tradlittlemips"
988 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
990 return (target_big_endian
991 ? (HAVE_64BIT_OBJECTS
994 ? "elf32-nbigmips" : "elf32-bigmips"))
995 : (HAVE_64BIT_OBJECTS
998 ? "elf32-nlittlemips" : "elf32-littlemips")));
1006 /* This function is called once, at assembler startup time. It should
1007 set up all the tables, etc. that the MD part of the assembler will need. */
1012 register const char *retval = NULL;
1016 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_arch))
1017 as_warn (_("Could not set architecture and machine"));
1019 op_hash = hash_new ();
1021 for (i = 0; i < NUMOPCODES;)
1023 const char *name = mips_opcodes[i].name;
1025 retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]);
1028 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1029 mips_opcodes[i].name, retval);
1030 /* Probably a memory allocation problem? Give up now. */
1031 as_fatal (_("Broken assembler. No assembly attempted."));
1035 if (mips_opcodes[i].pinfo != INSN_MACRO)
1037 if (!validate_mips_insn (&mips_opcodes[i]))
1042 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1045 mips16_op_hash = hash_new ();
1048 while (i < bfd_mips16_num_opcodes)
1050 const char *name = mips16_opcodes[i].name;
1052 retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]);
1054 as_fatal (_("internal: can't hash `%s': %s"),
1055 mips16_opcodes[i].name, retval);
1058 if (mips16_opcodes[i].pinfo != INSN_MACRO
1059 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1060 != mips16_opcodes[i].match))
1062 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1063 mips16_opcodes[i].name, mips16_opcodes[i].args);
1068 while (i < bfd_mips16_num_opcodes
1069 && strcmp (mips16_opcodes[i].name, name) == 0);
1073 as_fatal (_("Broken assembler. No assembly attempted."));
1075 /* We add all the general register names to the symbol table. This
1076 helps us detect invalid uses of them. */
1077 for (i = 0; i < 32; i++)
1081 sprintf (buf, "$%d", i);
1082 symbol_table_insert (symbol_new (buf, reg_section, i,
1083 &zero_address_frag));
1085 symbol_table_insert (symbol_new ("$ra", reg_section, RA,
1086 &zero_address_frag));
1087 symbol_table_insert (symbol_new ("$fp", reg_section, FP,
1088 &zero_address_frag));
1089 symbol_table_insert (symbol_new ("$sp", reg_section, SP,
1090 &zero_address_frag));
1091 symbol_table_insert (symbol_new ("$gp", reg_section, GP,
1092 &zero_address_frag));
1093 symbol_table_insert (symbol_new ("$at", reg_section, AT,
1094 &zero_address_frag));
1095 symbol_table_insert (symbol_new ("$kt0", reg_section, KT0,
1096 &zero_address_frag));
1097 symbol_table_insert (symbol_new ("$kt1", reg_section, KT1,
1098 &zero_address_frag));
1099 symbol_table_insert (symbol_new ("$zero", reg_section, ZERO,
1100 &zero_address_frag));
1101 symbol_table_insert (symbol_new ("$pc", reg_section, -1,
1102 &zero_address_frag));
1104 mips_no_prev_insn (false);
1107 mips_cprmask[0] = 0;
1108 mips_cprmask[1] = 0;
1109 mips_cprmask[2] = 0;
1110 mips_cprmask[3] = 0;
1112 /* set the default alignment for the text section (2**2) */
1113 record_alignment (text_section, 2);
1115 if (USE_GLOBAL_POINTER_OPT)
1116 bfd_set_gp_size (stdoutput, g_switch_value);
1118 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1120 /* On a native system, sections must be aligned to 16 byte
1121 boundaries. When configured for an embedded ELF target, we
1123 if (strcmp (TARGET_OS, "elf") != 0)
1125 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
1126 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
1127 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
1130 /* Create a .reginfo section for register masks and a .mdebug
1131 section for debugging information. */
1139 subseg = now_subseg;
1141 /* The ABI says this section should be loaded so that the
1142 running program can access it. However, we don't load it
1143 if we are configured for an embedded target */
1144 flags = SEC_READONLY | SEC_DATA;
1145 if (strcmp (TARGET_OS, "elf") != 0)
1146 flags |= SEC_ALLOC | SEC_LOAD;
1148 if (mips_abi != N64_ABI)
1150 sec = subseg_new (".reginfo", (subsegT) 0);
1152 bfd_set_section_flags (stdoutput, sec, flags);
1153 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
1156 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
1161 /* The 64-bit ABI uses a .MIPS.options section rather than
1162 .reginfo section. */
1163 sec = subseg_new (".MIPS.options", (subsegT) 0);
1164 bfd_set_section_flags (stdoutput, sec, flags);
1165 bfd_set_section_alignment (stdoutput, sec, 3);
1168 /* Set up the option header. */
1170 Elf_Internal_Options opthdr;
1173 opthdr.kind = ODK_REGINFO;
1174 opthdr.size = (sizeof (Elf_External_Options)
1175 + sizeof (Elf64_External_RegInfo));
1178 f = frag_more (sizeof (Elf_External_Options));
1179 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
1180 (Elf_External_Options *) f);
1182 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
1187 if (ECOFF_DEBUGGING)
1189 sec = subseg_new (".mdebug", (subsegT) 0);
1190 (void) bfd_set_section_flags (stdoutput, sec,
1191 SEC_HAS_CONTENTS | SEC_READONLY);
1192 (void) bfd_set_section_alignment (stdoutput, sec, 2);
1195 else if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1197 pdr_seg = subseg_new (".pdr", (subsegT) 0);
1198 (void) bfd_set_section_flags (stdoutput, pdr_seg,
1199 SEC_READONLY | SEC_RELOC
1201 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
1205 subseg_set (seg, subseg);
1209 if (! ECOFF_DEBUGGING)
1216 if (! ECOFF_DEBUGGING)
1224 struct mips_cl_insn insn;
1225 bfd_reloc_code_real_type unused_reloc[3]
1226 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1228 imm_expr.X_op = O_absent;
1229 imm_unmatched_hi = false;
1230 offset_expr.X_op = O_absent;
1231 imm_reloc[0] = BFD_RELOC_UNUSED;
1232 imm_reloc[1] = BFD_RELOC_UNUSED;
1233 imm_reloc[2] = BFD_RELOC_UNUSED;
1234 offset_reloc[0] = BFD_RELOC_UNUSED;
1235 offset_reloc[1] = BFD_RELOC_UNUSED;
1236 offset_reloc[2] = BFD_RELOC_UNUSED;
1238 if (mips_opts.mips16)
1239 mips16_ip (str, &insn);
1242 mips_ip (str, &insn);
1243 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1244 str, insn.insn_opcode));
1249 as_bad ("%s `%s'", insn_error, str);
1253 if (insn.insn_mo->pinfo == INSN_MACRO)
1255 if (mips_opts.mips16)
1256 mips16_macro (&insn);
1262 if (imm_expr.X_op != O_absent)
1263 append_insn (NULL, &insn, &imm_expr, imm_reloc, imm_unmatched_hi);
1264 else if (offset_expr.X_op != O_absent)
1265 append_insn (NULL, &insn, &offset_expr, offset_reloc, false);
1267 append_insn (NULL, &insn, NULL, unused_reloc, false);
1271 /* See whether instruction IP reads register REG. CLASS is the type
1275 insn_uses_reg (ip, reg, class)
1276 struct mips_cl_insn *ip;
1278 enum mips_regclass class;
1280 if (class == MIPS16_REG)
1282 assert (mips_opts.mips16);
1283 reg = mips16_to_32_reg_map[reg];
1284 class = MIPS_GR_REG;
1287 /* Don't report on general register ZERO, since it never changes. */
1288 if (class == MIPS_GR_REG && reg == ZERO)
1291 if (class == MIPS_FP_REG)
1293 assert (! mips_opts.mips16);
1294 /* If we are called with either $f0 or $f1, we must check $f0.
1295 This is not optimal, because it will introduce an unnecessary
1296 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1297 need to distinguish reading both $f0 and $f1 or just one of
1298 them. Note that we don't have to check the other way,
1299 because there is no instruction that sets both $f0 and $f1
1300 and requires a delay. */
1301 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
1302 && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1)
1303 == (reg &~ (unsigned) 1)))
1305 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
1306 && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1)
1307 == (reg &~ (unsigned) 1)))
1310 else if (! mips_opts.mips16)
1312 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
1313 && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg)
1315 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
1316 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg)
1321 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
1322 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX)
1323 & MIPS16OP_MASK_RX)]
1326 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
1327 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY)
1328 & MIPS16OP_MASK_RY)]
1331 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
1332 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
1333 & MIPS16OP_MASK_MOVE32Z)]
1336 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
1338 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
1340 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
1342 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
1343 && ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
1344 & MIPS16OP_MASK_REGR32) == reg)
1351 /* This function returns true if modifying a register requires a
1355 reg_needs_delay (reg)
1358 unsigned long prev_pinfo;
1360 prev_pinfo = prev_insn.insn_mo->pinfo;
1361 if (! mips_opts.noreorder
1362 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1363 && ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1364 || (! gpr_interlocks
1365 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
1367 /* A load from a coprocessor or from memory. All load
1368 delays delay the use of general register rt for one
1369 instruction on the r3000. The r6000 and r4000 use
1371 /* Itbl support may require additional care here. */
1372 know (prev_pinfo & INSN_WRITE_GPR_T);
1373 if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT))
1380 /* Mark instruction labels in mips16 mode. This permits the linker to
1381 handle them specially, such as generating jalx instructions when
1382 needed. We also make them odd for the duration of the assembly, in
1383 order to generate the right sort of code. We will make them even
1384 in the adjust_symtab routine, while leaving them marked. This is
1385 convenient for the debugger and the disassembler. The linker knows
1386 to make them odd again. */
1389 mips16_mark_labels ()
1391 if (mips_opts.mips16)
1393 struct insn_label_list *l;
1396 for (l = insn_labels; l != NULL; l = l->next)
1399 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1400 S_SET_OTHER (l->label, STO_MIPS16);
1402 val = S_GET_VALUE (l->label);
1404 S_SET_VALUE (l->label, val + 1);
1409 /* Output an instruction. PLACE is where to put the instruction; if
1410 it is NULL, this uses frag_more to get room. IP is the instruction
1411 information. ADDRESS_EXPR is an operand of the instruction to be
1412 used with RELOC_TYPE. */
1415 append_insn (place, ip, address_expr, reloc_type, unmatched_hi)
1417 struct mips_cl_insn *ip;
1418 expressionS *address_expr;
1419 bfd_reloc_code_real_type *reloc_type;
1420 boolean unmatched_hi;
1422 register unsigned long prev_pinfo, pinfo;
1427 /* Mark instruction labels in mips16 mode. */
1428 mips16_mark_labels ();
1430 prev_pinfo = prev_insn.insn_mo->pinfo;
1431 pinfo = ip->insn_mo->pinfo;
1433 if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL))
1437 /* If the previous insn required any delay slots, see if we need
1438 to insert a NOP or two. There are eight kinds of possible
1439 hazards, of which an instruction can have at most one type.
1440 (1) a load from memory delay
1441 (2) a load from a coprocessor delay
1442 (3) an unconditional branch delay
1443 (4) a conditional branch delay
1444 (5) a move to coprocessor register delay
1445 (6) a load coprocessor register from memory delay
1446 (7) a coprocessor condition code delay
1447 (8) a HI/LO special register delay
1449 There are a lot of optimizations we could do that we don't.
1450 In particular, we do not, in general, reorder instructions.
1451 If you use gcc with optimization, it will reorder
1452 instructions and generally do much more optimization then we
1453 do here; repeating all that work in the assembler would only
1454 benefit hand written assembly code, and does not seem worth
1457 /* This is how a NOP is emitted. */
1458 #define emit_nop() \
1460 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1461 : md_number_to_chars (frag_more (4), 0, 4))
1463 /* The previous insn might require a delay slot, depending upon
1464 the contents of the current insn. */
1465 if (! mips_opts.mips16
1466 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1467 && (((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1468 && ! cop_interlocks)
1469 || (! gpr_interlocks
1470 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
1472 /* A load from a coprocessor or from memory. All load
1473 delays delay the use of general register rt for one
1474 instruction on the r3000. The r6000 and r4000 use
1476 /* Itbl support may require additional care here. */
1477 know (prev_pinfo & INSN_WRITE_GPR_T);
1478 if (mips_optimize == 0
1479 || insn_uses_reg (ip,
1480 ((prev_insn.insn_opcode >> OP_SH_RT)
1485 else if (! mips_opts.mips16
1486 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1487 && (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
1488 && ! cop_interlocks)
1489 || (mips_opts.isa == ISA_MIPS1
1490 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))))
1492 /* A generic coprocessor delay. The previous instruction
1493 modified a coprocessor general or control register. If
1494 it modified a control register, we need to avoid any
1495 coprocessor instruction (this is probably not always
1496 required, but it sometimes is). If it modified a general
1497 register, we avoid using that register.
1499 On the r6000 and r4000 loading a coprocessor register
1500 from memory is interlocked, and does not require a delay.
1502 This case is not handled very well. There is no special
1503 knowledge of CP0 handling, and the coprocessors other
1504 than the floating point unit are not distinguished at
1506 /* Itbl support may require additional care here. FIXME!
1507 Need to modify this to include knowledge about
1508 user specified delays! */
1509 if (prev_pinfo & INSN_WRITE_FPR_T)
1511 if (mips_optimize == 0
1512 || insn_uses_reg (ip,
1513 ((prev_insn.insn_opcode >> OP_SH_FT)
1518 else if (prev_pinfo & INSN_WRITE_FPR_S)
1520 if (mips_optimize == 0
1521 || insn_uses_reg (ip,
1522 ((prev_insn.insn_opcode >> OP_SH_FS)
1529 /* We don't know exactly what the previous instruction
1530 does. If the current instruction uses a coprocessor
1531 register, we must insert a NOP. If previous
1532 instruction may set the condition codes, and the
1533 current instruction uses them, we must insert two
1535 /* Itbl support may require additional care here. */
1536 if (mips_optimize == 0
1537 || ((prev_pinfo & INSN_WRITE_COND_CODE)
1538 && (pinfo & INSN_READ_COND_CODE)))
1540 else if (pinfo & INSN_COP)
1544 else if (! mips_opts.mips16
1545 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1546 && (prev_pinfo & INSN_WRITE_COND_CODE)
1547 && ! cop_interlocks)
1549 /* The previous instruction sets the coprocessor condition
1550 codes, but does not require a general coprocessor delay
1551 (this means it is a floating point comparison
1552 instruction). If this instruction uses the condition
1553 codes, we need to insert a single NOP. */
1554 /* Itbl support may require additional care here. */
1555 if (mips_optimize == 0
1556 || (pinfo & INSN_READ_COND_CODE))
1560 /* If we're fixing up mfhi/mflo for the r7000 and the
1561 previous insn was an mfhi/mflo and the current insn
1562 reads the register that the mfhi/mflo wrote to, then
1565 else if (mips_7000_hilo_fix
1566 && MF_HILO_INSN (prev_pinfo)
1567 && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD)
1574 /* If we're fixing up mfhi/mflo for the r7000 and the
1575 2nd previous insn was an mfhi/mflo and the current insn
1576 reads the register that the mfhi/mflo wrote to, then
1579 else if (mips_7000_hilo_fix
1580 && MF_HILO_INSN (prev_prev_insn.insn_opcode)
1581 && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD)
1589 else if (prev_pinfo & INSN_READ_LO)
1591 /* The previous instruction reads the LO register; if the
1592 current instruction writes to the LO register, we must
1593 insert two NOPS. Some newer processors have interlocks.
1594 Also the tx39's multiply instructions can be exectuted
1595 immediatly after a read from HI/LO (without the delay),
1596 though the tx39's divide insns still do require the
1598 if (! (hilo_interlocks
1599 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
1600 && (mips_optimize == 0
1601 || (pinfo & INSN_WRITE_LO)))
1603 /* Most mips16 branch insns don't have a delay slot.
1604 If a read from LO is immediately followed by a branch
1605 to a write to LO we have a read followed by a write
1606 less than 2 insns away. We assume the target of
1607 a branch might be a write to LO, and insert a nop
1608 between a read and an immediately following branch. */
1609 else if (mips_opts.mips16
1610 && (mips_optimize == 0
1611 || (pinfo & MIPS16_INSN_BRANCH)))
1614 else if (prev_insn.insn_mo->pinfo & INSN_READ_HI)
1616 /* The previous instruction reads the HI register; if the
1617 current instruction writes to the HI register, we must
1618 insert a NOP. Some newer processors have interlocks.
1619 Also the note tx39's multiply above. */
1620 if (! (hilo_interlocks
1621 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
1622 && (mips_optimize == 0
1623 || (pinfo & INSN_WRITE_HI)))
1625 /* Most mips16 branch insns don't have a delay slot.
1626 If a read from HI is immediately followed by a branch
1627 to a write to HI we have a read followed by a write
1628 less than 2 insns away. We assume the target of
1629 a branch might be a write to HI, and insert a nop
1630 between a read and an immediately following branch. */
1631 else if (mips_opts.mips16
1632 && (mips_optimize == 0
1633 || (pinfo & MIPS16_INSN_BRANCH)))
1637 /* If the previous instruction was in a noreorder section, then
1638 we don't want to insert the nop after all. */
1639 /* Itbl support may require additional care here. */
1640 if (prev_insn_unreordered)
1643 /* There are two cases which require two intervening
1644 instructions: 1) setting the condition codes using a move to
1645 coprocessor instruction which requires a general coprocessor
1646 delay and then reading the condition codes 2) reading the HI
1647 or LO register and then writing to it (except on processors
1648 which have interlocks). If we are not already emitting a NOP
1649 instruction, we must check for these cases compared to the
1650 instruction previous to the previous instruction. */
1651 if ((! mips_opts.mips16
1652 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1653 && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
1654 && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
1655 && (pinfo & INSN_READ_COND_CODE)
1656 && ! cop_interlocks)
1657 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
1658 && (pinfo & INSN_WRITE_LO)
1659 && ! (hilo_interlocks
1660 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))))
1661 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
1662 && (pinfo & INSN_WRITE_HI)
1663 && ! (hilo_interlocks
1664 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))))
1669 if (prev_prev_insn_unreordered)
1672 if (prev_prev_nop && nops == 0)
1675 /* If we are being given a nop instruction, don't bother with
1676 one of the nops we would otherwise output. This will only
1677 happen when a nop instruction is used with mips_optimize set
1680 && ! mips_opts.noreorder
1681 && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0))
1684 /* Now emit the right number of NOP instructions. */
1685 if (nops > 0 && ! mips_opts.noreorder)
1688 unsigned long old_frag_offset;
1690 struct insn_label_list *l;
1692 old_frag = frag_now;
1693 old_frag_offset = frag_now_fix ();
1695 for (i = 0; i < nops; i++)
1700 listing_prev_line ();
1701 /* We may be at the start of a variant frag. In case we
1702 are, make sure there is enough space for the frag
1703 after the frags created by listing_prev_line. The
1704 argument to frag_grow here must be at least as large
1705 as the argument to all other calls to frag_grow in
1706 this file. We don't have to worry about being in the
1707 middle of a variant frag, because the variants insert
1708 all needed nop instructions themselves. */
1712 for (l = insn_labels; l != NULL; l = l->next)
1716 assert (S_GET_SEGMENT (l->label) == now_seg);
1717 symbol_set_frag (l->label, frag_now);
1718 val = (valueT) frag_now_fix ();
1719 /* mips16 text labels are stored as odd. */
1720 if (mips_opts.mips16)
1722 S_SET_VALUE (l->label, val);
1725 #ifndef NO_ECOFF_DEBUGGING
1726 if (ECOFF_DEBUGGING)
1727 ecoff_fix_loc (old_frag, old_frag_offset);
1730 else if (prev_nop_frag != NULL)
1732 /* We have a frag holding nops we may be able to remove. If
1733 we don't need any nops, we can decrease the size of
1734 prev_nop_frag by the size of one instruction. If we do
1735 need some nops, we count them in prev_nops_required. */
1736 if (prev_nop_frag_since == 0)
1740 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1741 --prev_nop_frag_holds;
1744 prev_nop_frag_required += nops;
1748 if (prev_prev_nop == 0)
1750 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1751 --prev_nop_frag_holds;
1754 ++prev_nop_frag_required;
1757 if (prev_nop_frag_holds <= prev_nop_frag_required)
1758 prev_nop_frag = NULL;
1760 ++prev_nop_frag_since;
1762 /* Sanity check: by the time we reach the second instruction
1763 after prev_nop_frag, we should have used up all the nops
1764 one way or another. */
1765 assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL);
1769 if (*reloc_type > BFD_RELOC_UNUSED)
1771 /* We need to set up a variant frag. */
1772 assert (mips_opts.mips16 && address_expr != NULL);
1773 f = frag_var (rs_machine_dependent, 4, 0,
1774 RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED,
1775 mips16_small, mips16_ext,
1777 & INSN_UNCOND_BRANCH_DELAY),
1778 (*prev_insn_reloc_type
1779 == BFD_RELOC_MIPS16_JMP)),
1780 make_expr_symbol (address_expr), 0, NULL);
1782 else if (place != NULL)
1784 else if (mips_opts.mips16
1786 && *reloc_type != BFD_RELOC_MIPS16_JMP)
1788 /* Make sure there is enough room to swap this instruction with
1789 a following jump instruction. */
1795 if (mips_opts.mips16
1796 && mips_opts.noreorder
1797 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1798 as_warn (_("extended instruction in delay slot"));
1803 fixp[0] = fixp[1] = fixp[2] = NULL;
1804 if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED)
1806 if (address_expr->X_op == O_constant)
1810 switch (*reloc_type)
1813 ip->insn_opcode |= address_expr->X_add_number;
1816 case BFD_RELOC_MIPS_HIGHEST:
1817 tmp = (address_expr->X_add_number + 0x800080008000) >> 16;
1819 ip->insn_opcode |= (tmp >> 16) & 0xffff;
1822 case BFD_RELOC_MIPS_HIGHER:
1823 tmp = (address_expr->X_add_number + 0x80008000) >> 16;
1824 ip->insn_opcode |= (tmp >> 16) & 0xffff;
1827 case BFD_RELOC_HI16_S:
1828 ip->insn_opcode |= ((address_expr->X_add_number + 0x8000)
1832 case BFD_RELOC_HI16:
1833 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
1836 case BFD_RELOC_LO16:
1837 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
1840 case BFD_RELOC_MIPS_JMP:
1841 if ((address_expr->X_add_number & 3) != 0)
1842 as_bad (_("jump to misaligned address (0x%lx)"),
1843 (unsigned long) address_expr->X_add_number);
1844 if (address_expr->X_add_number & ~0xfffffff
1845 || address_expr->X_add_number > 0x7fffffc)
1846 as_bad (_("jump address range overflow (0x%lx)"),
1847 (unsigned long) address_expr->X_add_number);
1848 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
1851 case BFD_RELOC_MIPS16_JMP:
1852 if ((address_expr->X_add_number & 3) != 0)
1853 as_bad (_("jump to misaligned address (0x%lx)"),
1854 (unsigned long) address_expr->X_add_number);
1855 if (address_expr->X_add_number & ~0xfffffff
1856 || address_expr->X_add_number > 0x7fffffc)
1857 as_bad (_("jump address range overflow (0x%lx)"),
1858 (unsigned long) address_expr->X_add_number);
1860 (((address_expr->X_add_number & 0x7c0000) << 3)
1861 | ((address_expr->X_add_number & 0xf800000) >> 7)
1862 | ((address_expr->X_add_number & 0x3fffc) >> 2));
1865 case BFD_RELOC_16_PCREL:
1866 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
1869 case BFD_RELOC_16_PCREL_S2:
1879 /* Don't generate a reloc if we are writing into a variant frag. */
1882 fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal, 4,
1884 (*reloc_type == BFD_RELOC_16_PCREL
1885 || *reloc_type == BFD_RELOC_16_PCREL_S2),
1888 /* These relocations can have an addend that won't fit in
1889 4 octets for 64bit assembly. */
1890 if (HAVE_64BIT_GPRS &&
1891 (*reloc_type == BFD_RELOC_16
1892 || *reloc_type == BFD_RELOC_32
1893 || *reloc_type == BFD_RELOC_MIPS_JMP
1894 || *reloc_type == BFD_RELOC_HI16_S
1895 || *reloc_type == BFD_RELOC_LO16
1896 || *reloc_type == BFD_RELOC_GPREL16
1897 || *reloc_type == BFD_RELOC_MIPS_LITERAL
1898 || *reloc_type == BFD_RELOC_GPREL32
1899 || *reloc_type == BFD_RELOC_64
1900 || *reloc_type == BFD_RELOC_CTOR
1901 || *reloc_type == BFD_RELOC_MIPS_SUB
1902 || *reloc_type == BFD_RELOC_MIPS_HIGHEST
1903 || *reloc_type == BFD_RELOC_MIPS_HIGHER
1904 || *reloc_type == BFD_RELOC_MIPS_SCN_DISP
1905 || *reloc_type == BFD_RELOC_MIPS_REL16
1906 || *reloc_type == BFD_RELOC_MIPS_RELGOT))
1907 fixp[0]->fx_no_overflow = 1;
1911 struct mips_hi_fixup *hi_fixup;
1913 assert (*reloc_type == BFD_RELOC_HI16_S);
1914 hi_fixup = ((struct mips_hi_fixup *)
1915 xmalloc (sizeof (struct mips_hi_fixup)));
1916 hi_fixup->fixp = fixp[0];
1917 hi_fixup->seg = now_seg;
1918 hi_fixup->next = mips_hi_fixup_list;
1919 mips_hi_fixup_list = hi_fixup;
1922 if (reloc_type[1] != BFD_RELOC_UNUSED)
1924 /* FIXME: This symbol can be one of
1925 RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */
1926 address_expr->X_op = O_absent;
1927 address_expr->X_add_symbol = 0;
1928 address_expr->X_add_number = 0;
1930 fixp[1] = fix_new_exp (frag_now, f - frag_now->fr_literal,
1931 4, address_expr, false,
1934 /* These relocations can have an addend that won't fit in
1935 4 octets for 64bit assembly. */
1936 if (HAVE_64BIT_GPRS &&
1937 (*reloc_type == BFD_RELOC_16
1938 || *reloc_type == BFD_RELOC_32
1939 || *reloc_type == BFD_RELOC_MIPS_JMP
1940 || *reloc_type == BFD_RELOC_HI16_S
1941 || *reloc_type == BFD_RELOC_LO16
1942 || *reloc_type == BFD_RELOC_GPREL16
1943 || *reloc_type == BFD_RELOC_MIPS_LITERAL
1944 || *reloc_type == BFD_RELOC_GPREL32
1945 || *reloc_type == BFD_RELOC_64
1946 || *reloc_type == BFD_RELOC_CTOR
1947 || *reloc_type == BFD_RELOC_MIPS_SUB
1948 || *reloc_type == BFD_RELOC_MIPS_HIGHEST
1949 || *reloc_type == BFD_RELOC_MIPS_HIGHER
1950 || *reloc_type == BFD_RELOC_MIPS_SCN_DISP
1951 || *reloc_type == BFD_RELOC_MIPS_REL16
1952 || *reloc_type == BFD_RELOC_MIPS_RELGOT))
1953 fixp[1]->fx_no_overflow = 1;
1955 if (reloc_type[2] != BFD_RELOC_UNUSED)
1957 address_expr->X_op = O_absent;
1958 address_expr->X_add_symbol = 0;
1959 address_expr->X_add_number = 0;
1961 fixp[2] = fix_new_exp (frag_now,
1962 f - frag_now->fr_literal, 4,
1963 address_expr, false,
1966 /* These relocations can have an addend that won't fit in
1967 4 octets for 64bit assembly. */
1968 if (HAVE_64BIT_GPRS &&
1969 (*reloc_type == BFD_RELOC_16
1970 || *reloc_type == BFD_RELOC_32
1971 || *reloc_type == BFD_RELOC_MIPS_JMP
1972 || *reloc_type == BFD_RELOC_HI16_S
1973 || *reloc_type == BFD_RELOC_LO16
1974 || *reloc_type == BFD_RELOC_GPREL16
1975 || *reloc_type == BFD_RELOC_MIPS_LITERAL
1976 || *reloc_type == BFD_RELOC_GPREL32
1977 || *reloc_type == BFD_RELOC_64
1978 || *reloc_type == BFD_RELOC_CTOR
1979 || *reloc_type == BFD_RELOC_MIPS_SUB
1980 || *reloc_type == BFD_RELOC_MIPS_HIGHEST
1981 || *reloc_type == BFD_RELOC_MIPS_HIGHER
1982 || *reloc_type == BFD_RELOC_MIPS_SCN_DISP
1983 || *reloc_type == BFD_RELOC_MIPS_REL16
1984 || *reloc_type == BFD_RELOC_MIPS_RELGOT))
1985 fixp[2]->fx_no_overflow = 1;
1992 if (! mips_opts.mips16)
1994 md_number_to_chars (f, ip->insn_opcode, 4);
1996 dwarf2_emit_insn (4);
1999 else if (*reloc_type == BFD_RELOC_MIPS16_JMP)
2001 md_number_to_chars (f, ip->insn_opcode >> 16, 2);
2002 md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2);
2004 dwarf2_emit_insn (4);
2011 md_number_to_chars (f, 0xf000 | ip->extend, 2);
2014 md_number_to_chars (f, ip->insn_opcode, 2);
2016 dwarf2_emit_insn (ip->use_extend ? 4 : 2);
2020 /* Update the register mask information. */
2021 if (! mips_opts.mips16)
2023 if (pinfo & INSN_WRITE_GPR_D)
2024 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD);
2025 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
2026 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT);
2027 if (pinfo & INSN_READ_GPR_S)
2028 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS);
2029 if (pinfo & INSN_WRITE_GPR_31)
2030 mips_gprmask |= 1 << RA;
2031 if (pinfo & INSN_WRITE_FPR_D)
2032 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD);
2033 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
2034 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS);
2035 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
2036 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT);
2037 if ((pinfo & INSN_READ_FPR_R) != 0)
2038 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR);
2039 if (pinfo & INSN_COP)
2041 /* We don't keep enough information to sort these cases out.
2042 The itbl support does keep this information however, although
2043 we currently don't support itbl fprmats as part of the cop
2044 instruction. May want to add this support in the future. */
2046 /* Never set the bit for $0, which is always zero. */
2047 mips_gprmask &= ~1 << 0;
2051 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
2052 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX)
2053 & MIPS16OP_MASK_RX);
2054 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
2055 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY)
2056 & MIPS16OP_MASK_RY);
2057 if (pinfo & MIPS16_INSN_WRITE_Z)
2058 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ)
2059 & MIPS16OP_MASK_RZ);
2060 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
2061 mips_gprmask |= 1 << TREG;
2062 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
2063 mips_gprmask |= 1 << SP;
2064 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
2065 mips_gprmask |= 1 << RA;
2066 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2067 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2068 if (pinfo & MIPS16_INSN_READ_Z)
2069 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
2070 & MIPS16OP_MASK_MOVE32Z);
2071 if (pinfo & MIPS16_INSN_READ_GPR_X)
2072 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
2073 & MIPS16OP_MASK_REGR32);
2076 if (place == NULL && ! mips_opts.noreorder)
2078 /* Filling the branch delay slot is more complex. We try to
2079 switch the branch with the previous instruction, which we can
2080 do if the previous instruction does not set up a condition
2081 that the branch tests and if the branch is not itself the
2082 target of any branch. */
2083 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
2084 || (pinfo & INSN_COND_BRANCH_DELAY))
2086 if (mips_optimize < 2
2087 /* If we have seen .set volatile or .set nomove, don't
2089 || mips_opts.nomove != 0
2090 /* If we had to emit any NOP instructions, then we
2091 already know we can not swap. */
2093 /* If we don't even know the previous insn, we can not
2095 || ! prev_insn_valid
2096 /* If the previous insn is already in a branch delay
2097 slot, then we can not swap. */
2098 || prev_insn_is_delay_slot
2099 /* If the previous previous insn was in a .set
2100 noreorder, we can't swap. Actually, the MIPS
2101 assembler will swap in this situation. However, gcc
2102 configured -with-gnu-as will generate code like
2108 in which we can not swap the bne and INSN. If gcc is
2109 not configured -with-gnu-as, it does not output the
2110 .set pseudo-ops. We don't have to check
2111 prev_insn_unreordered, because prev_insn_valid will
2112 be 0 in that case. We don't want to use
2113 prev_prev_insn_valid, because we do want to be able
2114 to swap at the start of a function. */
2115 || prev_prev_insn_unreordered
2116 /* If the branch is itself the target of a branch, we
2117 can not swap. We cheat on this; all we check for is
2118 whether there is a label on this instruction. If
2119 there are any branches to anything other than a
2120 label, users must use .set noreorder. */
2121 || insn_labels != NULL
2122 /* If the previous instruction is in a variant frag, we
2123 can not do the swap. This does not apply to the
2124 mips16, which uses variant frags for different
2126 || (! mips_opts.mips16
2127 && prev_insn_frag->fr_type == rs_machine_dependent)
2128 /* If the branch reads the condition codes, we don't
2129 even try to swap, because in the sequence
2134 we can not swap, and I don't feel like handling that
2136 || (! mips_opts.mips16
2137 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2138 && (pinfo & INSN_READ_COND_CODE))
2139 /* We can not swap with an instruction that requires a
2140 delay slot, becase the target of the branch might
2141 interfere with that instruction. */
2142 || (! mips_opts.mips16
2143 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2145 /* Itbl support may require additional care here. */
2146 & (INSN_LOAD_COPROC_DELAY
2147 | INSN_COPROC_MOVE_DELAY
2148 | INSN_WRITE_COND_CODE)))
2149 || (! (hilo_interlocks
2150 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
2154 || (! mips_opts.mips16
2156 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))
2157 || (! mips_opts.mips16
2158 && mips_opts.isa == ISA_MIPS1
2159 /* Itbl support may require additional care here. */
2160 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))
2161 /* We can not swap with a branch instruction. */
2163 & (INSN_UNCOND_BRANCH_DELAY
2164 | INSN_COND_BRANCH_DELAY
2165 | INSN_COND_BRANCH_LIKELY))
2166 /* We do not swap with a trap instruction, since it
2167 complicates trap handlers to have the trap
2168 instruction be in a delay slot. */
2169 || (prev_pinfo & INSN_TRAP)
2170 /* If the branch reads a register that the previous
2171 instruction sets, we can not swap. */
2172 || (! mips_opts.mips16
2173 && (prev_pinfo & INSN_WRITE_GPR_T)
2174 && insn_uses_reg (ip,
2175 ((prev_insn.insn_opcode >> OP_SH_RT)
2178 || (! mips_opts.mips16
2179 && (prev_pinfo & INSN_WRITE_GPR_D)
2180 && insn_uses_reg (ip,
2181 ((prev_insn.insn_opcode >> OP_SH_RD)
2184 || (mips_opts.mips16
2185 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
2186 && insn_uses_reg (ip,
2187 ((prev_insn.insn_opcode
2189 & MIPS16OP_MASK_RX),
2191 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
2192 && insn_uses_reg (ip,
2193 ((prev_insn.insn_opcode
2195 & MIPS16OP_MASK_RY),
2197 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
2198 && insn_uses_reg (ip,
2199 ((prev_insn.insn_opcode
2201 & MIPS16OP_MASK_RZ),
2203 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
2204 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
2205 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
2206 && insn_uses_reg (ip, RA, MIPS_GR_REG))
2207 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2208 && insn_uses_reg (ip,
2209 MIPS16OP_EXTRACT_REG32R (prev_insn.
2212 /* If the branch writes a register that the previous
2213 instruction sets, we can not swap (we know that
2214 branches write only to RD or to $31). */
2215 || (! mips_opts.mips16
2216 && (prev_pinfo & INSN_WRITE_GPR_T)
2217 && (((pinfo & INSN_WRITE_GPR_D)
2218 && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)
2219 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2220 || ((pinfo & INSN_WRITE_GPR_31)
2221 && (((prev_insn.insn_opcode >> OP_SH_RT)
2224 || (! mips_opts.mips16
2225 && (prev_pinfo & INSN_WRITE_GPR_D)
2226 && (((pinfo & INSN_WRITE_GPR_D)
2227 && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD)
2228 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2229 || ((pinfo & INSN_WRITE_GPR_31)
2230 && (((prev_insn.insn_opcode >> OP_SH_RD)
2233 || (mips_opts.mips16
2234 && (pinfo & MIPS16_INSN_WRITE_31)
2235 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
2236 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2237 && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode)
2239 /* If the branch writes a register that the previous
2240 instruction reads, we can not swap (we know that
2241 branches only write to RD or to $31). */
2242 || (! mips_opts.mips16
2243 && (pinfo & INSN_WRITE_GPR_D)
2244 && insn_uses_reg (&prev_insn,
2245 ((ip->insn_opcode >> OP_SH_RD)
2248 || (! mips_opts.mips16
2249 && (pinfo & INSN_WRITE_GPR_31)
2250 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2251 || (mips_opts.mips16
2252 && (pinfo & MIPS16_INSN_WRITE_31)
2253 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2254 /* If we are generating embedded PIC code, the branch
2255 might be expanded into a sequence which uses $at, so
2256 we can't swap with an instruction which reads it. */
2257 || (mips_pic == EMBEDDED_PIC
2258 && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG))
2259 /* If the previous previous instruction has a load
2260 delay, and sets a register that the branch reads, we
2262 || (! mips_opts.mips16
2263 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2264 /* Itbl support may require additional care here. */
2265 && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
2266 || (! gpr_interlocks
2267 && (prev_prev_insn.insn_mo->pinfo
2268 & INSN_LOAD_MEMORY_DELAY)))
2269 && insn_uses_reg (ip,
2270 ((prev_prev_insn.insn_opcode >> OP_SH_RT)
2273 /* If one instruction sets a condition code and the
2274 other one uses a condition code, we can not swap. */
2275 || ((pinfo & INSN_READ_COND_CODE)
2276 && (prev_pinfo & INSN_WRITE_COND_CODE))
2277 || ((pinfo & INSN_WRITE_COND_CODE)
2278 && (prev_pinfo & INSN_READ_COND_CODE))
2279 /* If the previous instruction uses the PC, we can not
2281 || (mips_opts.mips16
2282 && (prev_pinfo & MIPS16_INSN_READ_PC))
2283 /* If the previous instruction was extended, we can not
2285 || (mips_opts.mips16 && prev_insn_extended)
2286 /* If the previous instruction had a fixup in mips16
2287 mode, we can not swap. This normally means that the
2288 previous instruction was a 4 byte branch anyhow. */
2289 || (mips_opts.mips16 && prev_insn_fixp[0])
2290 /* If the previous instruction is a sync, sync.l, or
2291 sync.p, we can not swap. */
2292 || (prev_pinfo & INSN_SYNC))
2294 /* We could do even better for unconditional branches to
2295 portions of this object file; we could pick up the
2296 instruction at the destination, put it in the delay
2297 slot, and bump the destination address. */
2299 /* Update the previous insn information. */
2300 prev_prev_insn = *ip;
2301 prev_insn.insn_mo = &dummy_opcode;
2305 /* It looks like we can actually do the swap. */
2306 if (! mips_opts.mips16)
2311 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2312 memcpy (temp, prev_f, 4);
2313 memcpy (prev_f, f, 4);
2314 memcpy (f, temp, 4);
2315 if (prev_insn_fixp[0])
2317 prev_insn_fixp[0]->fx_frag = frag_now;
2318 prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal;
2320 if (prev_insn_fixp[1])
2322 prev_insn_fixp[1]->fx_frag = frag_now;
2323 prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal;
2325 if (prev_insn_fixp[2])
2327 prev_insn_fixp[2]->fx_frag = frag_now;
2328 prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal;
2332 fixp[0]->fx_frag = prev_insn_frag;
2333 fixp[0]->fx_where = prev_insn_where;
2337 fixp[1]->fx_frag = prev_insn_frag;
2338 fixp[1]->fx_where = prev_insn_where;
2342 fixp[2]->fx_frag = prev_insn_frag;
2343 fixp[2]->fx_where = prev_insn_where;
2351 assert (prev_insn_fixp[0] == NULL);
2352 assert (prev_insn_fixp[1] == NULL);
2353 assert (prev_insn_fixp[2] == NULL);
2354 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2355 memcpy (temp, prev_f, 2);
2356 memcpy (prev_f, f, 2);
2357 if (*reloc_type != BFD_RELOC_MIPS16_JMP)
2359 assert (*reloc_type == BFD_RELOC_UNUSED);
2360 memcpy (f, temp, 2);
2364 memcpy (f, f + 2, 2);
2365 memcpy (f + 2, temp, 2);
2369 fixp[0]->fx_frag = prev_insn_frag;
2370 fixp[0]->fx_where = prev_insn_where;
2374 fixp[1]->fx_frag = prev_insn_frag;
2375 fixp[1]->fx_where = prev_insn_where;
2379 fixp[2]->fx_frag = prev_insn_frag;
2380 fixp[2]->fx_where = prev_insn_where;
2384 /* Update the previous insn information; leave prev_insn
2386 prev_prev_insn = *ip;
2388 prev_insn_is_delay_slot = 1;
2390 /* If that was an unconditional branch, forget the previous
2391 insn information. */
2392 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
2394 prev_prev_insn.insn_mo = &dummy_opcode;
2395 prev_insn.insn_mo = &dummy_opcode;
2398 prev_insn_fixp[0] = NULL;
2399 prev_insn_fixp[1] = NULL;
2400 prev_insn_fixp[2] = NULL;
2401 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2402 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2403 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2404 prev_insn_extended = 0;
2406 else if (pinfo & INSN_COND_BRANCH_LIKELY)
2408 /* We don't yet optimize a branch likely. What we should do
2409 is look at the target, copy the instruction found there
2410 into the delay slot, and increment the branch to jump to
2411 the next instruction. */
2413 /* Update the previous insn information. */
2414 prev_prev_insn = *ip;
2415 prev_insn.insn_mo = &dummy_opcode;
2416 prev_insn_fixp[0] = NULL;
2417 prev_insn_fixp[1] = NULL;
2418 prev_insn_fixp[2] = NULL;
2419 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2420 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2421 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2422 prev_insn_extended = 0;
2426 /* Update the previous insn information. */
2428 prev_prev_insn.insn_mo = &dummy_opcode;
2430 prev_prev_insn = prev_insn;
2433 /* Any time we see a branch, we always fill the delay slot
2434 immediately; since this insn is not a branch, we know it
2435 is not in a delay slot. */
2436 prev_insn_is_delay_slot = 0;
2438 prev_insn_fixp[0] = fixp[0];
2439 prev_insn_fixp[1] = fixp[1];
2440 prev_insn_fixp[2] = fixp[2];
2441 prev_insn_reloc_type[0] = reloc_type[0];
2442 prev_insn_reloc_type[1] = reloc_type[1];
2443 prev_insn_reloc_type[2] = reloc_type[2];
2444 if (mips_opts.mips16)
2445 prev_insn_extended = (ip->use_extend
2446 || *reloc_type > BFD_RELOC_UNUSED);
2449 prev_prev_insn_unreordered = prev_insn_unreordered;
2450 prev_insn_unreordered = 0;
2451 prev_insn_frag = frag_now;
2452 prev_insn_where = f - frag_now->fr_literal;
2453 prev_insn_valid = 1;
2455 else if (place == NULL)
2457 /* We need to record a bit of information even when we are not
2458 reordering, in order to determine the base address for mips16
2459 PC relative relocs. */
2460 prev_prev_insn = prev_insn;
2462 prev_insn_reloc_type[0] = reloc_type[0];
2463 prev_insn_reloc_type[1] = reloc_type[1];
2464 prev_insn_reloc_type[2] = reloc_type[2];
2465 prev_prev_insn_unreordered = prev_insn_unreordered;
2466 prev_insn_unreordered = 1;
2469 /* We just output an insn, so the next one doesn't have a label. */
2470 mips_clear_insn_labels ();
2472 /* We must ensure that a fixup associated with an unmatched %hi
2473 reloc does not become a variant frag. Otherwise, the
2474 rearrangement of %hi relocs in frob_file may confuse
2478 frag_wane (frag_now);
2483 /* This function forgets that there was any previous instruction or
2484 label. If PRESERVE is non-zero, it remembers enough information to
2485 know whether nops are needed before a noreorder section. */
2488 mips_no_prev_insn (preserve)
2493 prev_insn.insn_mo = &dummy_opcode;
2494 prev_prev_insn.insn_mo = &dummy_opcode;
2495 prev_nop_frag = NULL;
2496 prev_nop_frag_holds = 0;
2497 prev_nop_frag_required = 0;
2498 prev_nop_frag_since = 0;
2500 prev_insn_valid = 0;
2501 prev_insn_is_delay_slot = 0;
2502 prev_insn_unreordered = 0;
2503 prev_insn_extended = 0;
2504 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2505 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2506 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2507 prev_prev_insn_unreordered = 0;
2508 mips_clear_insn_labels ();
2511 /* This function must be called whenever we turn on noreorder or emit
2512 something other than instructions. It inserts any NOPS which might
2513 be needed by the previous instruction, and clears the information
2514 kept for the previous instructions. The INSNS parameter is true if
2515 instructions are to follow. */
2518 mips_emit_delays (insns)
2521 if (! mips_opts.noreorder)
2526 if ((! mips_opts.mips16
2527 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2528 && (! cop_interlocks
2529 && (prev_insn.insn_mo->pinfo
2530 & (INSN_LOAD_COPROC_DELAY
2531 | INSN_COPROC_MOVE_DELAY
2532 | INSN_WRITE_COND_CODE))))
2533 || (! hilo_interlocks
2534 && (prev_insn.insn_mo->pinfo
2537 || (! mips_opts.mips16
2539 && (prev_insn.insn_mo->pinfo
2540 & INSN_LOAD_MEMORY_DELAY))
2541 || (! mips_opts.mips16
2542 && mips_opts.isa == ISA_MIPS1
2543 && (prev_insn.insn_mo->pinfo
2544 & INSN_COPROC_MEMORY_DELAY)))
2546 /* Itbl support may require additional care here. */
2548 if ((! mips_opts.mips16
2549 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2550 && (! cop_interlocks
2551 && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
2552 || (! hilo_interlocks
2553 && ((prev_insn.insn_mo->pinfo & INSN_READ_HI)
2554 || (prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2557 if (prev_insn_unreordered)
2560 else if ((! mips_opts.mips16
2561 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2562 && (! cop_interlocks
2563 && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
2564 || (! hilo_interlocks
2565 && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
2566 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2568 /* Itbl support may require additional care here. */
2569 if (! prev_prev_insn_unreordered)
2575 struct insn_label_list *l;
2579 /* Record the frag which holds the nop instructions, so
2580 that we can remove them if we don't need them. */
2581 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
2582 prev_nop_frag = frag_now;
2583 prev_nop_frag_holds = nops;
2584 prev_nop_frag_required = 0;
2585 prev_nop_frag_since = 0;
2588 for (; nops > 0; --nops)
2593 /* Move on to a new frag, so that it is safe to simply
2594 decrease the size of prev_nop_frag. */
2595 frag_wane (frag_now);
2599 for (l = insn_labels; l != NULL; l = l->next)
2603 assert (S_GET_SEGMENT (l->label) == now_seg);
2604 symbol_set_frag (l->label, frag_now);
2605 val = (valueT) frag_now_fix ();
2606 /* mips16 text labels are stored as odd. */
2607 if (mips_opts.mips16)
2609 S_SET_VALUE (l->label, val);
2614 /* Mark instruction labels in mips16 mode. */
2616 mips16_mark_labels ();
2618 mips_no_prev_insn (insns);
2621 /* Build an instruction created by a macro expansion. This is passed
2622 a pointer to the count of instructions created so far, an
2623 expression, the name of the instruction to build, an operand format
2624 string, and corresponding arguments. */
2628 macro_build (char *place,
2636 macro_build (place, counter, ep, name, fmt, va_alist)
2645 struct mips_cl_insn insn;
2646 bfd_reloc_code_real_type r[3];
2650 va_start (args, fmt);
2656 * If the macro is about to expand into a second instruction,
2657 * print a warning if needed. We need to pass ip as a parameter
2658 * to generate a better warning message here...
2660 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
2661 as_warn (_("Macro instruction expanded into multiple instructions"));
2664 * If the macro is about to expand into a second instruction,
2665 * and it is in a delay slot, print a warning.
2669 && mips_opts.noreorder
2670 && (prev_prev_insn.insn_mo->pinfo
2671 & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY
2672 | INSN_COND_BRANCH_LIKELY)) != 0)
2673 as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot"));
2676 ++*counter; /* bump instruction counter */
2678 if (mips_opts.mips16)
2680 mips16_macro_build (place, counter, ep, name, fmt, args);
2685 r[0] = BFD_RELOC_UNUSED;
2686 r[1] = BFD_RELOC_UNUSED;
2687 r[2] = BFD_RELOC_UNUSED;
2688 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
2689 assert (insn.insn_mo);
2690 assert (strcmp (name, insn.insn_mo->name) == 0);
2692 /* Search until we get a match for NAME. */
2695 /* It is assumed here that macros will never generate
2696 MDMX or MIPS-3D instructions. */
2697 if (strcmp (fmt, insn.insn_mo->args) == 0
2698 && insn.insn_mo->pinfo != INSN_MACRO
2699 && OPCODE_IS_MEMBER (insn.insn_mo,
2701 | (mips_opts.mips16 ? INSN_MIPS16 : 0)),
2703 && (mips_arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
2707 assert (insn.insn_mo->name);
2708 assert (strcmp (name, insn.insn_mo->name) == 0);
2711 insn.insn_opcode = insn.insn_mo->match;
2727 insn.insn_opcode |= va_arg (args, int) << OP_SH_RT;
2731 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE;
2736 insn.insn_opcode |= va_arg (args, int) << OP_SH_FT;
2741 insn.insn_opcode |= va_arg (args, int) << OP_SH_RD;
2746 int tmp = va_arg (args, int);
2748 insn.insn_opcode |= tmp << OP_SH_RT;
2749 insn.insn_opcode |= tmp << OP_SH_RD;
2755 insn.insn_opcode |= va_arg (args, int) << OP_SH_FS;
2762 insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT;
2766 insn.insn_opcode |= va_arg (args, int) << OP_SH_FD;
2770 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20;
2774 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19;
2778 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2;
2785 insn.insn_opcode |= va_arg (args, int) << OP_SH_RS;
2791 *r = (bfd_reloc_code_real_type) va_arg (args, int);
2792 assert (*r == BFD_RELOC_GPREL16
2793 || *r == BFD_RELOC_MIPS_LITERAL
2794 || *r == BFD_RELOC_MIPS_HIGHER
2795 || *r == BFD_RELOC_HI16_S
2796 || *r == BFD_RELOC_LO16
2797 || *r == BFD_RELOC_MIPS_GOT16
2798 || *r == BFD_RELOC_MIPS_CALL16
2799 || *r == BFD_RELOC_MIPS_GOT_DISP
2800 || *r == BFD_RELOC_MIPS_GOT_PAGE
2801 || *r == BFD_RELOC_MIPS_GOT_OFST
2802 || *r == BFD_RELOC_MIPS_GOT_LO16
2803 || *r == BFD_RELOC_MIPS_CALL_LO16
2804 || (ep->X_op == O_subtract
2805 && *r == BFD_RELOC_PCREL_LO16));
2809 *r = (bfd_reloc_code_real_type) va_arg (args, int);
2811 && (ep->X_op == O_constant
2812 || (ep->X_op == O_symbol
2813 && (*r == BFD_RELOC_MIPS_HIGHEST
2814 || *r == BFD_RELOC_HI16_S
2815 || *r == BFD_RELOC_HI16
2816 || *r == BFD_RELOC_GPREL16
2817 || *r == BFD_RELOC_MIPS_GOT_HI16
2818 || *r == BFD_RELOC_MIPS_CALL_HI16))
2819 || (ep->X_op == O_subtract
2820 && *r == BFD_RELOC_PCREL_HI16_S)));
2824 assert (ep != NULL);
2826 * This allows macro() to pass an immediate expression for
2827 * creating short branches without creating a symbol.
2828 * Note that the expression still might come from the assembly
2829 * input, in which case the value is not checked for range nor
2830 * is a relocation entry generated (yuck).
2832 if (ep->X_op == O_constant)
2834 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
2838 if (mips_pic == EMBEDDED_PIC)
2839 *r = BFD_RELOC_16_PCREL_S2;
2841 *r = BFD_RELOC_16_PCREL;
2845 assert (ep != NULL);
2846 *r = BFD_RELOC_MIPS_JMP;
2850 insn.insn_opcode |= va_arg (args, unsigned long);
2859 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
2861 append_insn (place, &insn, ep, r, false);
2865 mips16_macro_build (place, counter, ep, name, fmt, args)
2867 int *counter ATTRIBUTE_UNUSED;
2873 struct mips_cl_insn insn;
2874 bfd_reloc_code_real_type r[3]
2875 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2877 insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
2878 assert (insn.insn_mo);
2879 assert (strcmp (name, insn.insn_mo->name) == 0);
2881 while (strcmp (fmt, insn.insn_mo->args) != 0
2882 || insn.insn_mo->pinfo == INSN_MACRO)
2885 assert (insn.insn_mo->name);
2886 assert (strcmp (name, insn.insn_mo->name) == 0);
2889 insn.insn_opcode = insn.insn_mo->match;
2890 insn.use_extend = false;
2909 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY;
2914 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX;
2918 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ;
2922 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z;
2932 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32;
2939 regno = va_arg (args, int);
2940 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
2941 insn.insn_opcode |= regno << MIPS16OP_SH_REG32R;
2962 assert (ep != NULL);
2964 if (ep->X_op != O_constant)
2965 *r = (int) BFD_RELOC_UNUSED + c;
2968 mips16_immed (NULL, 0, c, ep->X_add_number, false, false,
2969 false, &insn.insn_opcode, &insn.use_extend,
2972 *r = BFD_RELOC_UNUSED;
2978 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6;
2985 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
2987 append_insn (place, &insn, ep, r, false);
2991 * Generate a "jalr" instruction with a relocation hint to the called
2992 * function. This occurs in NewABI PIC code.
2995 macro_build_jalr (icnt, ep)
3006 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", "d,s",
3009 fix_new_exp (frag_now, f - frag_now->fr_literal,
3010 0, ep, false, BFD_RELOC_MIPS_JALR);
3014 * Generate a "lui" instruction.
3017 macro_build_lui (place, counter, ep, regnum)
3023 expressionS high_expr;
3024 struct mips_cl_insn insn;
3025 bfd_reloc_code_real_type r[3]
3026 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3027 const char *name = "lui";
3028 const char *fmt = "t,u";
3030 assert (! mips_opts.mips16);
3036 high_expr.X_op = O_constant;
3037 high_expr.X_add_number = ep->X_add_number;
3040 if (high_expr.X_op == O_constant)
3042 /* we can compute the instruction now without a relocation entry */
3043 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
3045 *r = BFD_RELOC_UNUSED;
3047 else if (! HAVE_NEWABI)
3049 assert (ep->X_op == O_symbol);
3050 /* _gp_disp is a special case, used from s_cpload. */
3051 assert (mips_pic == NO_PIC
3052 || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0);
3053 *r = BFD_RELOC_HI16_S;
3057 * If the macro is about to expand into a second instruction,
3058 * print a warning if needed. We need to pass ip as a parameter
3059 * to generate a better warning message here...
3061 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
3062 as_warn (_("Macro instruction expanded into multiple instructions"));
3065 ++*counter; /* bump instruction counter */
3067 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
3068 assert (insn.insn_mo);
3069 assert (strcmp (name, insn.insn_mo->name) == 0);
3070 assert (strcmp (fmt, insn.insn_mo->args) == 0);
3072 insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT);
3073 if (*r == BFD_RELOC_UNUSED)
3075 insn.insn_opcode |= high_expr.X_add_number;
3076 append_insn (place, &insn, NULL, r, false);
3079 append_insn (place, &insn, &high_expr, r, false);
3083 * Generates code to set the $at register to true (one)
3084 * if reg is less than the immediate expression.
3087 set_at (counter, reg, unsignedp)
3092 if (imm_expr.X_op == O_constant
3093 && imm_expr.X_add_number >= -0x8000
3094 && imm_expr.X_add_number < 0x8000)
3095 macro_build ((char *) NULL, counter, &imm_expr,
3096 unsignedp ? "sltiu" : "slti",
3097 "t,r,j", AT, reg, (int) BFD_RELOC_LO16);
3100 load_register (counter, AT, &imm_expr, HAVE_64BIT_GPRS);
3101 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3102 unsignedp ? "sltu" : "slt",
3103 "d,v,t", AT, reg, AT);
3107 /* Warn if an expression is not a constant. */
3110 check_absolute_expr (ip, ex)
3111 struct mips_cl_insn *ip;
3114 if (ex->X_op == O_big)
3115 as_bad (_("unsupported large constant"));
3116 else if (ex->X_op != O_constant)
3117 as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name);
3120 /* Count the leading zeroes by performing a binary chop. This is a
3121 bulky bit of source, but performance is a LOT better for the
3122 majority of values than a simple loop to count the bits:
3123 for (lcnt = 0; (lcnt < 32); lcnt++)
3124 if ((v) & (1 << (31 - lcnt)))
3126 However it is not code size friendly, and the gain will drop a bit
3127 on certain cached systems.
3129 #define COUNT_TOP_ZEROES(v) \
3130 (((v) & ~0xffff) == 0 \
3131 ? ((v) & ~0xff) == 0 \
3132 ? ((v) & ~0xf) == 0 \
3133 ? ((v) & ~0x3) == 0 \
3134 ? ((v) & ~0x1) == 0 \
3139 : ((v) & ~0x7) == 0 \
3142 : ((v) & ~0x3f) == 0 \
3143 ? ((v) & ~0x1f) == 0 \
3146 : ((v) & ~0x7f) == 0 \
3149 : ((v) & ~0xfff) == 0 \
3150 ? ((v) & ~0x3ff) == 0 \
3151 ? ((v) & ~0x1ff) == 0 \
3154 : ((v) & ~0x7ff) == 0 \
3157 : ((v) & ~0x3fff) == 0 \
3158 ? ((v) & ~0x1fff) == 0 \
3161 : ((v) & ~0x7fff) == 0 \
3164 : ((v) & ~0xffffff) == 0 \
3165 ? ((v) & ~0xfffff) == 0 \
3166 ? ((v) & ~0x3ffff) == 0 \
3167 ? ((v) & ~0x1ffff) == 0 \
3170 : ((v) & ~0x7ffff) == 0 \
3173 : ((v) & ~0x3fffff) == 0 \
3174 ? ((v) & ~0x1fffff) == 0 \
3177 : ((v) & ~0x7fffff) == 0 \
3180 : ((v) & ~0xfffffff) == 0 \
3181 ? ((v) & ~0x3ffffff) == 0 \
3182 ? ((v) & ~0x1ffffff) == 0 \
3185 : ((v) & ~0x7ffffff) == 0 \
3188 : ((v) & ~0x3fffffff) == 0 \
3189 ? ((v) & ~0x1fffffff) == 0 \
3192 : ((v) & ~0x7fffffff) == 0 \
3196 /* Is the given value a sign-extended 32-bit value? */
3197 #define IS_SEXT_32BIT_NUM(x) \
3198 (((x) &~ (offsetT) 0x7fffffff) == 0 \
3199 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
3202 * This routine generates the least number of instructions neccessary to load
3203 * an absolute expression value into a register.
3206 load_register (counter, reg, ep, dbl)
3213 expressionS hi32, lo32;
3215 if (ep->X_op != O_big)
3217 assert (ep->X_op == O_constant);
3218 if (ep->X_add_number < 0x8000
3219 && (ep->X_add_number >= 0
3220 || (ep->X_add_number >= -0x8000
3223 || sizeof (ep->X_add_number) > 4))))
3225 /* We can handle 16 bit signed values with an addiu to
3226 $zero. No need to ever use daddiu here, since $zero and
3227 the result are always correct in 32 bit mode. */
3228 macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3229 (int) BFD_RELOC_LO16);
3232 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
3234 /* We can handle 16 bit unsigned values with an ori to
3236 macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0,
3237 (int) BFD_RELOC_LO16);
3240 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)
3243 || sizeof (ep->X_add_number) > 4
3244 || (ep->X_add_number & 0x80000000) == 0))
3245 || ((HAVE_32BIT_GPRS || ! dbl)
3246 && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0)
3249 && ((ep->X_add_number &~ (offsetT) 0xffffffff)
3250 == ~ (offsetT) 0xffffffff)))
3252 /* 32 bit values require an lui. */
3253 macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg,
3254 (int) BFD_RELOC_HI16);
3255 if ((ep->X_add_number & 0xffff) != 0)
3256 macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg,
3257 (int) BFD_RELOC_LO16);
3262 /* The value is larger than 32 bits. */
3264 if (HAVE_32BIT_GPRS)
3266 as_bad (_("Number (0x%lx) larger than 32 bits"),
3267 (unsigned long) ep->X_add_number);
3268 macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3269 (int) BFD_RELOC_LO16);
3273 if (ep->X_op != O_big)
3276 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3277 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3278 hi32.X_add_number &= 0xffffffff;
3280 lo32.X_add_number &= 0xffffffff;
3284 assert (ep->X_add_number > 2);
3285 if (ep->X_add_number == 3)
3286 generic_bignum[3] = 0;
3287 else if (ep->X_add_number > 4)
3288 as_bad (_("Number larger than 64 bits"));
3289 lo32.X_op = O_constant;
3290 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
3291 hi32.X_op = O_constant;
3292 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
3295 if (hi32.X_add_number == 0)
3300 unsigned long hi, lo;
3302 if (hi32.X_add_number == (offsetT) 0xffffffff)
3304 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
3306 macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j",
3307 reg, 0, (int) BFD_RELOC_LO16);
3310 if (lo32.X_add_number & 0x80000000)
3312 macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg,
3313 (int) BFD_RELOC_HI16);
3314 if (lo32.X_add_number & 0xffff)
3315 macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i",
3316 reg, reg, (int) BFD_RELOC_LO16);
3321 /* Check for 16bit shifted constant. We know that hi32 is
3322 non-zero, so start the mask on the first bit of the hi32
3327 unsigned long himask, lomask;
3331 himask = 0xffff >> (32 - shift);
3332 lomask = (0xffff << shift) & 0xffffffff;
3336 himask = 0xffff << (shift - 32);
3339 if ((hi32.X_add_number & ~(offsetT) himask) == 0
3340 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
3344 tmp.X_op = O_constant;
3346 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
3347 | (lo32.X_add_number >> shift));
3349 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
3350 macro_build ((char *) NULL, counter, &tmp,
3351 "ori", "t,r,i", reg, 0,
3352 (int) BFD_RELOC_LO16);
3353 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3354 (shift >= 32) ? "dsll32" : "dsll",
3356 (shift >= 32) ? shift - 32 : shift);
3361 while (shift <= (64 - 16));
3363 /* Find the bit number of the lowest one bit, and store the
3364 shifted value in hi/lo. */
3365 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
3366 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
3370 while ((lo & 1) == 0)
3375 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
3381 while ((hi & 1) == 0)
3390 /* Optimize if the shifted value is a (power of 2) - 1. */
3391 if ((hi == 0 && ((lo + 1) & lo) == 0)
3392 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
3394 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
3399 /* This instruction will set the register to be all
3401 tmp.X_op = O_constant;
3402 tmp.X_add_number = (offsetT) -1;
3403 macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j",
3404 reg, 0, (int) BFD_RELOC_LO16);
3408 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3409 (bit >= 32) ? "dsll32" : "dsll",
3411 (bit >= 32) ? bit - 32 : bit);
3413 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3414 (shift >= 32) ? "dsrl32" : "dsrl",
3416 (shift >= 32) ? shift - 32 : shift);
3421 /* Sign extend hi32 before calling load_register, because we can
3422 generally get better code when we load a sign extended value. */
3423 if ((hi32.X_add_number & 0x80000000) != 0)
3424 hi32.X_add_number |= ~(offsetT) 0xffffffff;
3425 load_register (counter, reg, &hi32, 0);
3428 if ((lo32.X_add_number & 0xffff0000) == 0)
3432 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3433 "dsll32", "d,w,<", reg, freg, 0);
3441 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
3443 macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg,
3444 (int) BFD_RELOC_HI16);
3445 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3446 "dsrl32", "d,w,<", reg, reg, 0);
3452 macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll",
3453 "d,w,<", reg, freg, 16);
3457 mid16.X_add_number >>= 16;
3458 macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg,
3459 freg, (int) BFD_RELOC_LO16);
3460 macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll",
3461 "d,w,<", reg, reg, 16);
3464 if ((lo32.X_add_number & 0xffff) != 0)
3465 macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg,
3466 (int) BFD_RELOC_LO16);
3469 /* Load an address into a register. */
3472 load_address (counter, reg, ep, used_at)
3480 if (ep->X_op != O_constant
3481 && ep->X_op != O_symbol)
3483 as_bad (_("expression too complex"));
3484 ep->X_op = O_constant;
3487 if (ep->X_op == O_constant)
3489 load_register (counter, reg, ep, HAVE_64BIT_ADDRESSES);
3493 if (mips_pic == NO_PIC)
3495 /* If this is a reference to a GP relative symbol, we want
3496 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3498 lui $reg,<sym> (BFD_RELOC_HI16_S)
3499 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3500 If we have an addend, we always use the latter form.
3502 With 64bit address space and a usable $at we want
3503 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3504 lui $at,<sym> (BFD_RELOC_HI16_S)
3505 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3506 daddiu $at,<sym> (BFD_RELOC_LO16)
3510 If $at is already in use, we use an path which is suboptimal
3511 on superscalar processors.
3512 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3513 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3515 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3517 daddiu $reg,<sym> (BFD_RELOC_LO16)
3519 if (HAVE_64BIT_ADDRESSES)
3521 /* We don't do GP optimization for now because RELAX_ENCODE can't
3522 hold the data for such large chunks. */
3524 if (*used_at == 0 && ! mips_opts.noat)
3526 macro_build (p, counter, ep, "lui", "t,u",
3527 reg, (int) BFD_RELOC_MIPS_HIGHEST);
3528 macro_build (p, counter, ep, "lui", "t,u",
3529 AT, (int) BFD_RELOC_HI16_S);
3530 macro_build (p, counter, ep, "daddiu", "t,r,j",
3531 reg, reg, (int) BFD_RELOC_MIPS_HIGHER);
3532 macro_build (p, counter, ep, "daddiu", "t,r,j",
3533 AT, AT, (int) BFD_RELOC_LO16);
3534 macro_build (p, counter, (expressionS *) NULL, "dsll32",
3535 "d,w,<", reg, reg, 0);
3536 macro_build (p, counter, (expressionS *) NULL, "daddu",
3537 "d,v,t", reg, reg, AT);
3542 macro_build (p, counter, ep, "lui", "t,u",
3543 reg, (int) BFD_RELOC_MIPS_HIGHEST);
3544 macro_build (p, counter, ep, "daddiu", "t,r,j",
3545 reg, reg, (int) BFD_RELOC_MIPS_HIGHER);
3546 macro_build (p, counter, (expressionS *) NULL, "dsll",
3547 "d,w,<", reg, reg, 16);
3548 macro_build (p, counter, ep, "daddiu", "t,r,j",
3549 reg, reg, (int) BFD_RELOC_HI16_S);
3550 macro_build (p, counter, (expressionS *) NULL, "dsll",
3551 "d,w,<", reg, reg, 16);
3552 macro_build (p, counter, ep, "daddiu", "t,r,j",
3553 reg, reg, (int) BFD_RELOC_LO16);
3558 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
3559 && ! nopic_need_relax (ep->X_add_symbol, 1))
3562 macro_build ((char *) NULL, counter, ep,
3563 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j",
3564 reg, mips_gp_register, (int) BFD_RELOC_GPREL16);
3565 p = frag_var (rs_machine_dependent, 8, 0,
3566 RELAX_ENCODE (4, 8, 0, 4, 0,
3567 mips_opts.warn_about_macros),
3568 ep->X_add_symbol, 0, NULL);
3570 macro_build_lui (p, counter, ep, reg);
3573 macro_build (p, counter, ep,
3574 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3575 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3578 else if (mips_pic == SVR4_PIC && ! mips_big_got)
3582 /* If this is a reference to an external symbol, we want
3583 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3585 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3587 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3588 If there is a constant, it must be added in after. */
3589 ex.X_add_number = ep->X_add_number;
3590 ep->X_add_number = 0;
3592 macro_build ((char *) NULL, counter, ep,
3593 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)",
3594 reg, (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
3595 macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", "");
3596 p = frag_var (rs_machine_dependent, 4, 0,
3597 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros),
3598 ep->X_add_symbol, (offsetT) 0, (char *) NULL);
3599 macro_build (p, counter, ep,
3600 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3601 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3602 if (ex.X_add_number != 0)
3604 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3605 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3606 ex.X_op = O_constant;
3607 macro_build ((char *) NULL, counter, &ex,
3608 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3609 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3612 else if (mips_pic == SVR4_PIC)
3617 /* This is the large GOT case. If this is a reference to an
3618 external symbol, we want
3619 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3621 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3622 Otherwise, for a reference to a local symbol, we want
3623 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3625 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3626 If we have NewABI, we want
3627 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3628 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3629 If there is a constant, it must be added in after. */
3630 ex.X_add_number = ep->X_add_number;
3631 ep->X_add_number = 0;
3634 macro_build ((char *) NULL, counter, ep,
3635 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg,
3636 (int) BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
3637 macro_build (p, counter, ep,
3638 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j",
3639 reg, reg, (int) BFD_RELOC_MIPS_GOT_OFST);
3643 if (reg_needs_delay (mips_gp_register))
3648 macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg,
3649 (int) BFD_RELOC_MIPS_GOT_HI16);
3650 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3651 HAVE_32BIT_ADDRESSES ? "addu" : "daddu", "d,v,t", reg,
3652 reg, mips_gp_register);
3653 macro_build ((char *) NULL, counter, ep,
3654 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
3655 "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg);
3656 p = frag_var (rs_machine_dependent, 12 + off, 0,
3657 RELAX_ENCODE (12, 12 + off, off, 8 + off, 0,
3658 mips_opts.warn_about_macros),
3659 ep->X_add_symbol, 0, NULL);
3662 /* We need a nop before loading from $gp. This special
3663 check is required because the lui which starts the main
3664 instruction stream does not refer to $gp, and so will not
3665 insert the nop which may be required. */
3666 macro_build (p, counter, (expressionS *) NULL, "nop", "");
3669 macro_build (p, counter, ep,
3670 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg,
3671 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
3673 macro_build (p, counter, (expressionS *) NULL, "nop", "");
3675 macro_build (p, counter, ep,
3676 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3677 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3680 if (ex.X_add_number != 0)
3682 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3683 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3684 ex.X_op = O_constant;
3685 macro_build ((char *) NULL, counter, &ex,
3686 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3687 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3690 else if (mips_pic == EMBEDDED_PIC)
3693 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3695 macro_build ((char *) NULL, counter, ep,
3696 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3697 "t,r,j", reg, mips_gp_register, (int) BFD_RELOC_GPREL16);
3703 /* Move the contents of register SOURCE into register DEST. */
3706 move_register (counter, dest, source)
3711 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3712 HAVE_32BIT_GPRS ? "addu" : "daddu",
3713 "d,v,t", dest, source, 0);
3718 * This routine implements the seemingly endless macro or synthesized
3719 * instructions and addressing modes in the mips assembly language. Many
3720 * of these macros are simple and are similar to each other. These could
3721 * probably be handled by some kind of table or grammer aproach instead of
3722 * this verbose method. Others are not simple macros but are more like
3723 * optimizing code generation.
3724 * One interesting optimization is when several store macros appear
3725 * consecutivly that would load AT with the upper half of the same address.
3726 * The ensuing load upper instructions are ommited. This implies some kind
3727 * of global optimization. We currently only optimize within a single macro.
3728 * For many of the load and store macros if the address is specified as a
3729 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3730 * first load register 'at' with zero and use it as the base register. The
3731 * mips assembler simply uses register $zero. Just one tiny optimization
3736 struct mips_cl_insn *ip;
3738 register int treg, sreg, dreg, breg;
3754 bfd_reloc_code_real_type r;
3755 int hold_mips_optimize;
3757 assert (! mips_opts.mips16);
3759 treg = (ip->insn_opcode >> 16) & 0x1f;
3760 dreg = (ip->insn_opcode >> 11) & 0x1f;
3761 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
3762 mask = ip->insn_mo->mask;
3764 expr1.X_op = O_constant;
3765 expr1.X_op_symbol = NULL;
3766 expr1.X_add_symbol = NULL;
3767 expr1.X_add_number = 1;
3779 mips_emit_delays (true);
3780 ++mips_opts.noreorder;
3781 mips_any_noreorder = 1;
3783 expr1.X_add_number = 8;
3784 macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg);
3786 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
3789 move_register (&icnt, dreg, sreg);
3790 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
3791 dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
3793 --mips_opts.noreorder;
3814 if (imm_expr.X_op == O_constant
3815 && imm_expr.X_add_number >= -0x8000
3816 && imm_expr.X_add_number < 0x8000)
3818 macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg,
3819 (int) BFD_RELOC_LO16);
3822 load_register (&icnt, AT, &imm_expr, dbl);
3823 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t",
3843 if (imm_expr.X_op == O_constant
3844 && imm_expr.X_add_number >= 0
3845 && imm_expr.X_add_number < 0x10000)
3847 if (mask != M_NOR_I)
3848 macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg,
3849 sreg, (int) BFD_RELOC_LO16);
3852 macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i",
3853 treg, sreg, (int) BFD_RELOC_LO16);
3854 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nor",
3855 "d,v,t", treg, treg, 0);
3860 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
3861 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t",
3879 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
3881 macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg,
3885 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
3886 macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT);
3894 macro_build ((char *) NULL, &icnt, &offset_expr,
3895 likely ? "bgezl" : "bgez", "s,p", sreg);
3900 macro_build ((char *) NULL, &icnt, &offset_expr,
3901 likely ? "blezl" : "blez", "s,p", treg);
3904 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
3906 macro_build ((char *) NULL, &icnt, &offset_expr,
3907 likely ? "beql" : "beq", "s,t,p", AT, 0);
3913 /* check for > max integer */
3914 maxnum = 0x7fffffff;
3915 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
3922 if (imm_expr.X_op == O_constant
3923 && imm_expr.X_add_number >= maxnum
3924 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
3927 /* result is always false */
3931 as_warn (_("Branch %s is always false (nop)"),
3933 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop",
3939 as_warn (_("Branch likely %s is always false"),
3941 macro_build ((char *) NULL, &icnt, &offset_expr, "bnel",
3946 if (imm_expr.X_op != O_constant)
3947 as_bad (_("Unsupported large constant"));
3948 ++imm_expr.X_add_number;
3952 if (mask == M_BGEL_I)
3954 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
3956 macro_build ((char *) NULL, &icnt, &offset_expr,
3957 likely ? "bgezl" : "bgez", "s,p", sreg);
3960 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
3962 macro_build ((char *) NULL, &icnt, &offset_expr,
3963 likely ? "bgtzl" : "bgtz", "s,p", sreg);
3966 maxnum = 0x7fffffff;
3967 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
3974 maxnum = - maxnum - 1;
3975 if (imm_expr.X_op == O_constant
3976 && imm_expr.X_add_number <= maxnum
3977 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
3980 /* result is always true */
3981 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
3982 macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p");
3985 set_at (&icnt, sreg, 0);
3986 macro_build ((char *) NULL, &icnt, &offset_expr,
3987 likely ? "beql" : "beq", "s,t,p", AT, 0);
3997 macro_build ((char *) NULL, &icnt, &offset_expr,
3998 likely ? "beql" : "beq", "s,t,p", 0, treg);
4001 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4002 "d,v,t", AT, sreg, treg);
4003 macro_build ((char *) NULL, &icnt, &offset_expr,
4004 likely ? "beql" : "beq", "s,t,p", AT, 0);
4012 && imm_expr.X_op == O_constant
4013 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4015 if (imm_expr.X_op != O_constant)
4016 as_bad (_("Unsupported large constant"));
4017 ++imm_expr.X_add_number;
4021 if (mask == M_BGEUL_I)
4023 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4025 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4027 macro_build ((char *) NULL, &icnt, &offset_expr,
4028 likely ? "bnel" : "bne", "s,t,p", sreg, 0);
4031 set_at (&icnt, sreg, 1);
4032 macro_build ((char *) NULL, &icnt, &offset_expr,
4033 likely ? "beql" : "beq", "s,t,p", AT, 0);
4041 macro_build ((char *) NULL, &icnt, &offset_expr,
4042 likely ? "bgtzl" : "bgtz", "s,p", sreg);
4047 macro_build ((char *) NULL, &icnt, &offset_expr,
4048 likely ? "bltzl" : "bltz", "s,p", treg);
4051 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4053 macro_build ((char *) NULL, &icnt, &offset_expr,
4054 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4062 macro_build ((char *) NULL, &icnt, &offset_expr,
4063 likely ? "bnel" : "bne", "s,t,p", sreg, 0);
4068 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4069 "d,v,t", AT, treg, sreg);
4070 macro_build ((char *) NULL, &icnt, &offset_expr,
4071 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4079 macro_build ((char *) NULL, &icnt, &offset_expr,
4080 likely ? "blezl" : "blez", "s,p", sreg);
4085 macro_build ((char *) NULL, &icnt, &offset_expr,
4086 likely ? "bgezl" : "bgez", "s,p", treg);
4089 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4091 macro_build ((char *) NULL, &icnt, &offset_expr,
4092 likely ? "beql" : "beq", "s,t,p", AT, 0);
4098 maxnum = 0x7fffffff;
4099 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4106 if (imm_expr.X_op == O_constant
4107 && imm_expr.X_add_number >= maxnum
4108 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4110 if (imm_expr.X_op != O_constant)
4111 as_bad (_("Unsupported large constant"));
4112 ++imm_expr.X_add_number;
4116 if (mask == M_BLTL_I)
4118 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4120 macro_build ((char *) NULL, &icnt, &offset_expr,
4121 likely ? "bltzl" : "bltz", "s,p", sreg);
4124 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4126 macro_build ((char *) NULL, &icnt, &offset_expr,
4127 likely ? "blezl" : "blez", "s,p", sreg);
4130 set_at (&icnt, sreg, 0);
4131 macro_build ((char *) NULL, &icnt, &offset_expr,
4132 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4140 macro_build ((char *) NULL, &icnt, &offset_expr,
4141 likely ? "beql" : "beq", "s,t,p", sreg, 0);
4146 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4147 "d,v,t", AT, treg, sreg);
4148 macro_build ((char *) NULL, &icnt, &offset_expr,
4149 likely ? "beql" : "beq", "s,t,p", AT, 0);
4157 && imm_expr.X_op == O_constant
4158 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4160 if (imm_expr.X_op != O_constant)
4161 as_bad (_("Unsupported large constant"));
4162 ++imm_expr.X_add_number;
4166 if (mask == M_BLTUL_I)
4168 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4170 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4172 macro_build ((char *) NULL, &icnt, &offset_expr,
4173 likely ? "beql" : "beq",
4177 set_at (&icnt, sreg, 1);
4178 macro_build ((char *) NULL, &icnt, &offset_expr,
4179 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4187 macro_build ((char *) NULL, &icnt, &offset_expr,
4188 likely ? "bltzl" : "bltz", "s,p", sreg);
4193 macro_build ((char *) NULL, &icnt, &offset_expr,
4194 likely ? "bgtzl" : "bgtz", "s,p", treg);
4197 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4199 macro_build ((char *) NULL, &icnt, &offset_expr,
4200 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4210 macro_build ((char *) NULL, &icnt, &offset_expr,
4211 likely ? "bnel" : "bne", "s,t,p", 0, treg);
4214 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4217 macro_build ((char *) NULL, &icnt, &offset_expr,
4218 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4233 as_warn (_("Divide by zero."));
4235 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4238 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4243 mips_emit_delays (true);
4244 ++mips_opts.noreorder;
4245 mips_any_noreorder = 1;
4248 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4249 "s,t,q", treg, 0, 7);
4250 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4251 dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4255 expr1.X_add_number = 8;
4256 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4257 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4258 dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4259 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4262 expr1.X_add_number = -1;
4263 macro_build ((char *) NULL, &icnt, &expr1,
4264 dbl ? "daddiu" : "addiu",
4265 "t,r,j", AT, 0, (int) BFD_RELOC_LO16);
4266 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
4267 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT);
4270 expr1.X_add_number = 1;
4271 macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0,
4272 (int) BFD_RELOC_LO16);
4273 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsll32",
4274 "d,w,<", AT, AT, 31);
4278 expr1.X_add_number = 0x80000000;
4279 macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT,
4280 (int) BFD_RELOC_HI16);
4284 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4285 "s,t,q", sreg, AT, 6);
4286 /* We want to close the noreorder block as soon as possible, so
4287 that later insns are available for delay slot filling. */
4288 --mips_opts.noreorder;
4292 expr1.X_add_number = 8;
4293 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT);
4294 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
4297 /* We want to close the noreorder block as soon as possible, so
4298 that later insns are available for delay slot filling. */
4299 --mips_opts.noreorder;
4301 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4304 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d", dreg);
4343 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4345 as_warn (_("Divide by zero."));
4347 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4350 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4354 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4356 if (strcmp (s2, "mflo") == 0)
4357 move_register (&icnt, dreg, sreg);
4359 move_register (&icnt, dreg, 0);
4362 if (imm_expr.X_op == O_constant
4363 && imm_expr.X_add_number == -1
4364 && s[strlen (s) - 1] != 'u')
4366 if (strcmp (s2, "mflo") == 0)
4368 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4369 dbl ? "dneg" : "neg", "d,w", dreg, sreg);
4372 move_register (&icnt, dreg, 0);
4376 load_register (&icnt, AT, &imm_expr, dbl);
4377 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4379 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg);
4398 mips_emit_delays (true);
4399 ++mips_opts.noreorder;
4400 mips_any_noreorder = 1;
4403 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4404 "s,t,q", treg, 0, 7);
4405 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4407 /* We want to close the noreorder block as soon as possible, so
4408 that later insns are available for delay slot filling. */
4409 --mips_opts.noreorder;
4413 expr1.X_add_number = 8;
4414 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4415 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4418 /* We want to close the noreorder block as soon as possible, so
4419 that later insns are available for delay slot filling. */
4420 --mips_opts.noreorder;
4421 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4424 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg);
4430 /* Load the address of a symbol into a register. If breg is not
4431 zero, we then add a base register to it. */
4433 if (dbl && HAVE_32BIT_GPRS)
4434 as_warn (_("dla used to load 32-bit register"));
4436 if (! dbl && HAVE_64BIT_OBJECTS)
4437 as_warn (_("la used to load 64-bit address"));
4439 if (offset_expr.X_op == O_constant
4440 && offset_expr.X_add_number >= -0x8000
4441 && offset_expr.X_add_number < 0x8000)
4443 macro_build ((char *) NULL, &icnt, &offset_expr,
4444 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4445 "t,r,j", treg, sreg, (int) BFD_RELOC_LO16);
4460 /* When generating embedded PIC code, we permit expressions of
4463 la $treg,foo-bar($breg)
4464 where bar is an address in the current section. These are used
4465 when getting the addresses of functions. We don't permit
4466 X_add_number to be non-zero, because if the symbol is
4467 external the relaxing code needs to know that any addend is
4468 purely the offset to X_op_symbol. */
4469 if (mips_pic == EMBEDDED_PIC
4470 && offset_expr.X_op == O_subtract
4471 && (symbol_constant_p (offset_expr.X_op_symbol)
4472 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
4473 : (symbol_equated_p (offset_expr.X_op_symbol)
4475 (symbol_get_value_expression (offset_expr.X_op_symbol)
4478 && (offset_expr.X_add_number == 0
4479 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
4485 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4486 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
4490 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4491 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
4492 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4493 (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu",
4494 "d,v,t", tempreg, tempreg, breg);
4496 macro_build ((char *) NULL, &icnt, &offset_expr,
4497 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4498 "t,r,j", treg, tempreg, (int) BFD_RELOC_PCREL_LO16);
4504 if (offset_expr.X_op != O_symbol
4505 && offset_expr.X_op != O_constant)
4507 as_bad (_("expression too complex"));
4508 offset_expr.X_op = O_constant;
4511 if (offset_expr.X_op == O_constant)
4512 load_register (&icnt, tempreg, &offset_expr,
4513 ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
4514 ? (dbl || HAVE_64BIT_ADDRESSES)
4515 : HAVE_64BIT_ADDRESSES));
4516 else if (mips_pic == NO_PIC)
4518 /* If this is a reference to a GP relative symbol, we want
4519 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4521 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4522 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4523 If we have a constant, we need two instructions anyhow,
4524 so we may as well always use the latter form.
4526 With 64bit address space and a usable $at we want
4527 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4528 lui $at,<sym> (BFD_RELOC_HI16_S)
4529 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4530 daddiu $at,<sym> (BFD_RELOC_LO16)
4532 daddu $tempreg,$tempreg,$at
4534 If $at is already in use, we use an path which is suboptimal
4535 on superscalar processors.
4536 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4537 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4539 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4541 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4544 if (HAVE_64BIT_ADDRESSES)
4546 /* We don't do GP optimization for now because RELAX_ENCODE can't
4547 hold the data for such large chunks. */
4549 if (used_at == 0 && ! mips_opts.noat)
4551 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4552 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
4553 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4554 AT, (int) BFD_RELOC_HI16_S);
4555 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4556 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
4557 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4558 AT, AT, (int) BFD_RELOC_LO16);
4559 macro_build (p, &icnt, (expressionS *) NULL, "dsll32",
4560 "d,w,<", tempreg, tempreg, 0);
4561 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
4562 "d,v,t", tempreg, tempreg, AT);
4567 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4568 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
4569 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4570 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
4571 macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<",
4572 tempreg, tempreg, 16);
4573 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4574 tempreg, tempreg, (int) BFD_RELOC_HI16_S);
4575 macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<",
4576 tempreg, tempreg, 16);
4577 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4578 tempreg, tempreg, (int) BFD_RELOC_LO16);
4583 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
4584 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
4587 macro_build ((char *) NULL, &icnt, &offset_expr, "addiu",
4588 "t,r,j", tempreg, mips_gp_register,
4589 (int) BFD_RELOC_GPREL16);
4590 p = frag_var (rs_machine_dependent, 8, 0,
4591 RELAX_ENCODE (4, 8, 0, 4, 0,
4592 mips_opts.warn_about_macros),
4593 offset_expr.X_add_symbol, 0, NULL);
4595 macro_build_lui (p, &icnt, &offset_expr, tempreg);
4598 macro_build (p, &icnt, &offset_expr, "addiu",
4599 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4602 else if (mips_pic == SVR4_PIC && ! mips_big_got)
4604 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
4606 /* If this is a reference to an external symbol, and there
4607 is no constant, we want
4608 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4609 or if tempreg is PIC_CALL_REG
4610 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4611 For a local symbol, we want
4612 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4614 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4616 If we have a small constant, and this is a reference to
4617 an external symbol, we want
4618 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4620 addiu $tempreg,$tempreg,<constant>
4621 For a local symbol, we want the same instruction
4622 sequence, but we output a BFD_RELOC_LO16 reloc on the
4625 If we have a large constant, and this is a reference to
4626 an external symbol, we want
4627 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4628 lui $at,<hiconstant>
4629 addiu $at,$at,<loconstant>
4630 addu $tempreg,$tempreg,$at
4631 For a local symbol, we want the same instruction
4632 sequence, but we output a BFD_RELOC_LO16 reloc on the
4633 addiu instruction. */
4634 expr1.X_add_number = offset_expr.X_add_number;
4635 offset_expr.X_add_number = 0;
4637 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
4638 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
4639 macro_build ((char *) NULL, &icnt, &offset_expr,
4640 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
4641 "t,o(b)", tempreg, lw_reloc_type, mips_gp_register);
4642 if (expr1.X_add_number == 0)
4651 /* We're going to put in an addu instruction using
4652 tempreg, so we may as well insert the nop right
4654 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4658 p = frag_var (rs_machine_dependent, 8 - off, 0,
4659 RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0,
4661 ? mips_opts.warn_about_macros
4663 offset_expr.X_add_symbol, 0, NULL);
4666 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
4669 macro_build (p, &icnt, &expr1,
4670 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4671 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4672 /* FIXME: If breg == 0, and the next instruction uses
4673 $tempreg, then if this variant case is used an extra
4674 nop will be generated. */
4676 else if (expr1.X_add_number >= -0x8000
4677 && expr1.X_add_number < 0x8000)
4679 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4681 macro_build ((char *) NULL, &icnt, &expr1,
4682 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4683 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4684 frag_var (rs_machine_dependent, 0, 0,
4685 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4686 offset_expr.X_add_symbol, 0, NULL);
4692 /* If we are going to add in a base register, and the
4693 target register and the base register are the same,
4694 then we are using AT as a temporary register. Since
4695 we want to load the constant into AT, we add our
4696 current AT (from the global offset table) and the
4697 register into the register now, and pretend we were
4698 not using a base register. */
4703 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4705 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4706 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4707 "d,v,t", treg, AT, breg);
4713 /* Set mips_optimize around the lui instruction to avoid
4714 inserting an unnecessary nop after the lw. */
4715 hold_mips_optimize = mips_optimize;
4717 macro_build_lui (NULL, &icnt, &expr1, AT);
4718 mips_optimize = hold_mips_optimize;
4720 macro_build ((char *) NULL, &icnt, &expr1,
4721 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4722 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
4723 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4724 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4725 "d,v,t", tempreg, tempreg, AT);
4726 frag_var (rs_machine_dependent, 0, 0,
4727 RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0),
4728 offset_expr.X_add_symbol, 0, NULL);
4732 else if (mips_pic == SVR4_PIC)
4736 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
4737 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
4739 /* This is the large GOT case. If this is a reference to an
4740 external symbol, and there is no constant, we want
4741 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4742 addu $tempreg,$tempreg,$gp
4743 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4744 or if tempreg is PIC_CALL_REG
4745 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4746 addu $tempreg,$tempreg,$gp
4747 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
4748 For a local symbol, we want
4749 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4751 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4753 If we have a small constant, and this is a reference to
4754 an external symbol, we want
4755 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4756 addu $tempreg,$tempreg,$gp
4757 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4759 addiu $tempreg,$tempreg,<constant>
4760 For a local symbol, we want
4761 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4763 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4765 If we have a large constant, and this is a reference to
4766 an external symbol, we want
4767 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4768 addu $tempreg,$tempreg,$gp
4769 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4770 lui $at,<hiconstant>
4771 addiu $at,$at,<loconstant>
4772 addu $tempreg,$tempreg,$at
4773 For a local symbol, we want
4774 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4775 lui $at,<hiconstant>
4776 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4777 addu $tempreg,$tempreg,$at
4779 For NewABI, we want for data addresses
4780 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4781 If tempreg is PIC_CALL_REG pointing to a external symbol, we want
4782 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4786 int reloc_type = (tempreg == PIC_CALL_REG
4787 ? BFD_RELOC_MIPS_CALL16
4788 : BFD_RELOC_MIPS_GOT_DISP);
4790 macro_build ((char *) NULL, &icnt, &offset_expr,
4791 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
4792 "t,o(b)", tempreg, reloc_type, mips_gp_register);
4795 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4796 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4797 "d,v,t", treg, tempreg, breg);
4804 expr1.X_add_number = offset_expr.X_add_number;
4805 offset_expr.X_add_number = 0;
4807 if (reg_needs_delay (mips_gp_register))
4811 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
4813 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
4814 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
4816 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4817 tempreg, lui_reloc_type);
4818 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4819 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4820 "d,v,t", tempreg, tempreg, mips_gp_register);
4821 macro_build ((char *) NULL, &icnt, &offset_expr,
4822 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
4823 "t,o(b)", tempreg, lw_reloc_type, tempreg);
4824 if (expr1.X_add_number == 0)
4832 /* We're going to put in an addu instruction using
4833 tempreg, so we may as well insert the nop right
4835 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4840 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
4841 RELAX_ENCODE (12 + off, 12 + gpdel, gpdel,
4844 ? mips_opts.warn_about_macros
4846 offset_expr.X_add_symbol, 0, NULL);
4848 else if (expr1.X_add_number >= -0x8000
4849 && expr1.X_add_number < 0x8000)
4851 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4853 macro_build ((char *) NULL, &icnt, &expr1,
4854 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4855 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4857 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
4858 RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0,
4860 ? mips_opts.warn_about_macros
4862 offset_expr.X_add_symbol, 0, NULL);
4868 /* If we are going to add in a base register, and the
4869 target register and the base register are the same,
4870 then we are using AT as a temporary register. Since
4871 we want to load the constant into AT, we add our
4872 current AT (from the global offset table) and the
4873 register into the register now, and pretend we were
4874 not using a base register. */
4882 assert (tempreg == AT);
4883 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4885 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4886 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4887 "d,v,t", treg, AT, breg);
4892 /* Set mips_optimize around the lui instruction to avoid
4893 inserting an unnecessary nop after the lw. */
4894 hold_mips_optimize = mips_optimize;
4896 macro_build_lui (NULL, &icnt, &expr1, AT);
4897 mips_optimize = hold_mips_optimize;
4899 macro_build ((char *) NULL, &icnt, &expr1,
4900 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4901 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
4902 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4903 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4904 "d,v,t", dreg, dreg, AT);
4906 p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0,
4907 RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel,
4910 ? mips_opts.warn_about_macros
4912 offset_expr.X_add_symbol, 0, NULL);
4919 /* This is needed because this instruction uses $gp, but
4920 the first instruction on the main stream does not. */
4921 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
4924 macro_build (p, &icnt, &offset_expr,
4925 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
4926 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16,
4929 if (expr1.X_add_number >= -0x8000
4930 && expr1.X_add_number < 0x8000)
4932 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
4934 macro_build (p, &icnt, &expr1,
4935 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4936 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4937 /* FIXME: If add_number is 0, and there was no base
4938 register, the external symbol case ended with a load,
4939 so if the symbol turns out to not be external, and
4940 the next instruction uses tempreg, an unnecessary nop
4941 will be inserted. */
4947 /* We must add in the base register now, as in the
4948 external symbol case. */
4949 assert (tempreg == AT);
4950 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
4952 macro_build (p, &icnt, (expressionS *) NULL,
4953 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4954 "d,v,t", treg, AT, breg);
4957 /* We set breg to 0 because we have arranged to add
4958 it in in both cases. */
4962 macro_build_lui (p, &icnt, &expr1, AT);
4964 macro_build (p, &icnt, &expr1,
4965 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4966 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
4968 macro_build (p, &icnt, (expressionS *) NULL,
4969 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4970 "d,v,t", tempreg, tempreg, AT);
4974 else if (mips_pic == EMBEDDED_PIC)
4977 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4979 macro_build ((char *) NULL, &icnt, &offset_expr,
4980 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j",
4981 tempreg, mips_gp_register, (int) BFD_RELOC_GPREL16);
4990 if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
4991 s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu";
4993 s = HAVE_64BIT_ADDRESSES ? "daddu" : "addu";
4995 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s,
4996 "d,v,t", treg, tempreg, breg);
5005 /* The j instruction may not be used in PIC code, since it
5006 requires an absolute address. We convert it to a b
5008 if (mips_pic == NO_PIC)
5009 macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a");
5011 macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p");
5014 /* The jal instructions must be handled as macros because when
5015 generating PIC code they expand to multi-instruction
5016 sequences. Normally they are simple instructions. */
5021 if (mips_pic == NO_PIC
5022 || mips_pic == EMBEDDED_PIC)
5023 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr",
5025 else if (mips_pic == SVR4_PIC)
5027 if (sreg != PIC_CALL_REG)
5028 as_warn (_("MIPS PIC call to register other than $25"));
5030 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr",
5034 if (mips_cprestore_offset < 0)
5035 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5038 if (! mips_frame_reg_valid)
5040 as_warn (_("No .frame pseudo-op used in PIC code"));
5041 /* Quiet this warning. */
5042 mips_frame_reg_valid = 1;
5044 if (! mips_cprestore_valid)
5046 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5047 /* Quiet this warning. */
5048 mips_cprestore_valid = 1;
5050 expr1.X_add_number = mips_cprestore_offset;
5051 macro_build ((char *) NULL, &icnt, &expr1,
5052 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)",
5053 mips_gp_register, (int) BFD_RELOC_LO16,
5064 if (mips_pic == NO_PIC)
5065 macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a");
5066 else if (mips_pic == SVR4_PIC)
5070 /* If this is a reference to an external symbol, and we are
5071 using a small GOT, we want
5072 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5076 lw $gp,cprestore($sp)
5077 The cprestore value is set using the .cprestore
5078 pseudo-op. If we are using a big GOT, we want
5079 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5081 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5085 lw $gp,cprestore($sp)
5086 If the symbol is not external, we want
5087 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5089 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5092 lw $gp,cprestore($sp)
5094 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5095 jalr $ra,$25 (BFD_RELOC_MIPS_JALR)
5099 macro_build ((char *) NULL, &icnt, &offset_expr,
5100 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5101 "t,o(b)", PIC_CALL_REG,
5102 (int) BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5103 macro_build_jalr (icnt, &offset_expr);
5110 macro_build ((char *) NULL, &icnt, &offset_expr,
5111 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5112 "t,o(b)", PIC_CALL_REG,
5113 (int) BFD_RELOC_MIPS_CALL16, mips_gp_register);
5114 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5116 p = frag_var (rs_machine_dependent, 4, 0,
5117 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5118 offset_expr.X_add_symbol, 0, NULL);
5124 if (reg_needs_delay (mips_gp_register))
5128 macro_build ((char *) NULL, &icnt, &offset_expr, "lui",
5129 "t,u", PIC_CALL_REG,
5130 (int) BFD_RELOC_MIPS_CALL_HI16);
5131 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5132 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5133 "d,v,t", PIC_CALL_REG, PIC_CALL_REG,
5135 macro_build ((char *) NULL, &icnt, &offset_expr,
5136 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5137 "t,o(b)", PIC_CALL_REG,
5138 (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
5139 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5141 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5142 RELAX_ENCODE (16, 12 + gpdel, gpdel,
5144 offset_expr.X_add_symbol, 0, NULL);
5147 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5150 macro_build (p, &icnt, &offset_expr,
5151 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5152 "t,o(b)", PIC_CALL_REG,
5153 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
5155 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5158 macro_build (p, &icnt, &offset_expr,
5159 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5160 "t,r,j", PIC_CALL_REG, PIC_CALL_REG,
5161 (int) BFD_RELOC_LO16);
5162 macro_build_jalr (icnt, &offset_expr);
5164 if (mips_cprestore_offset < 0)
5165 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5168 if (! mips_frame_reg_valid)
5170 as_warn (_("No .frame pseudo-op used in PIC code"));
5171 /* Quiet this warning. */
5172 mips_frame_reg_valid = 1;
5174 if (! mips_cprestore_valid)
5176 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5177 /* Quiet this warning. */
5178 mips_cprestore_valid = 1;
5180 if (mips_opts.noreorder)
5181 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5183 expr1.X_add_number = mips_cprestore_offset;
5184 macro_build ((char *) NULL, &icnt, &expr1,
5185 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)",
5186 mips_gp_register, (int) BFD_RELOC_LO16,
5191 else if (mips_pic == EMBEDDED_PIC)
5193 macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p");
5194 /* The linker may expand the call to a longer sequence which
5195 uses $at, so we must break rather than return. */
5220 /* Itbl support may require additional care here. */
5225 /* Itbl support may require additional care here. */
5230 /* Itbl support may require additional care here. */
5235 /* Itbl support may require additional care here. */
5247 if (mips_arch == CPU_R4650)
5249 as_bad (_("opcode not supported on this processor"));
5253 /* Itbl support may require additional care here. */
5258 /* Itbl support may require additional care here. */
5263 /* Itbl support may require additional care here. */
5283 if (breg == treg || coproc || lr)
5305 /* Itbl support may require additional care here. */
5310 /* Itbl support may require additional care here. */
5315 /* Itbl support may require additional care here. */
5320 /* Itbl support may require additional care here. */
5336 if (mips_arch == CPU_R4650)
5338 as_bad (_("opcode not supported on this processor"));
5343 /* Itbl support may require additional care here. */
5347 /* Itbl support may require additional care here. */
5352 /* Itbl support may require additional care here. */
5364 /* Itbl support may require additional care here. */
5365 if (mask == M_LWC1_AB
5366 || mask == M_SWC1_AB
5367 || mask == M_LDC1_AB
5368 || mask == M_SDC1_AB
5377 /* For embedded PIC, we allow loads where the offset is calculated
5378 by subtracting a symbol in the current segment from an unknown
5379 symbol, relative to a base register, e.g.:
5380 <op> $treg, <sym>-<localsym>($breg)
5381 This is used by the compiler for switch statements. */
5382 if (mips_pic == EMBEDDED_PIC
5383 && offset_expr.X_op == O_subtract
5384 && (symbol_constant_p (offset_expr.X_op_symbol)
5385 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
5386 : (symbol_equated_p (offset_expr.X_op_symbol)
5388 (symbol_get_value_expression (offset_expr.X_op_symbol)
5392 && (offset_expr.X_add_number == 0
5393 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
5395 /* For this case, we output the instructions:
5396 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5397 addiu $tempreg,$tempreg,$breg
5398 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5399 If the relocation would fit entirely in 16 bits, it would be
5401 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5402 instead, but that seems quite difficult. */
5403 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
5404 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
5405 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5406 ((bfd_arch_bits_per_address (stdoutput) == 32
5407 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
5408 ? "addu" : "daddu"),
5409 "d,v,t", tempreg, tempreg, breg);
5410 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, treg,
5411 (int) BFD_RELOC_PCREL_LO16, tempreg);
5417 if (offset_expr.X_op != O_constant
5418 && offset_expr.X_op != O_symbol)
5420 as_bad (_("expression too complex"));
5421 offset_expr.X_op = O_constant;
5424 /* A constant expression in PIC code can be handled just as it
5425 is in non PIC code. */
5426 if (mips_pic == NO_PIC
5427 || offset_expr.X_op == O_constant)
5431 /* If this is a reference to a GP relative symbol, and there
5432 is no base register, we want
5433 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5434 Otherwise, if there is no base register, we want
5435 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5436 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5437 If we have a constant, we need two instructions anyhow,
5438 so we always use the latter form.
5440 If we have a base register, and this is a reference to a
5441 GP relative symbol, we want
5442 addu $tempreg,$breg,$gp
5443 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5445 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5446 addu $tempreg,$tempreg,$breg
5447 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5448 With a constant we always use the latter case.
5450 With 64bit address space and no base register and $at usable,
5452 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5453 lui $at,<sym> (BFD_RELOC_HI16_S)
5454 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5457 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5458 If we have a base register, we want
5459 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5460 lui $at,<sym> (BFD_RELOC_HI16_S)
5461 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5465 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5467 Without $at we can't generate the optimal path for superscalar
5468 processors here since this would require two temporary registers.
5469 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5470 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5472 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5474 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5475 If we have a base register, we want
5476 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5477 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5479 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5481 daddu $tempreg,$tempreg,$breg
5482 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5484 If we have 64-bit addresses, as an optimization, for
5485 addresses which are 32-bit constants (e.g. kseg0/kseg1
5486 addresses) we fall back to the 32-bit address generation
5487 mechanism since it is more efficient. Note that due to
5488 the signed offset used by memory operations, the 32-bit
5489 range is shifted down by 32768 here. This code should
5490 probably attempt to generate 64-bit constants more
5491 efficiently in general.
5493 if (HAVE_64BIT_ADDRESSES
5494 && !(offset_expr.X_op == O_constant
5495 && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
5499 /* We don't do GP optimization for now because RELAX_ENCODE can't
5500 hold the data for such large chunks. */
5502 if (used_at == 0 && ! mips_opts.noat)
5504 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5505 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
5506 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5507 AT, (int) BFD_RELOC_HI16_S);
5508 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5509 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
5511 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
5512 "d,v,t", AT, AT, breg);
5513 macro_build (p, &icnt, (expressionS *) NULL, "dsll32",
5514 "d,w,<", tempreg, tempreg, 0);
5515 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
5516 "d,v,t", tempreg, tempreg, AT);
5517 macro_build (p, &icnt, &offset_expr, s,
5518 fmt, treg, (int) BFD_RELOC_LO16, tempreg);
5523 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5524 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
5525 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5526 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
5527 macro_build (p, &icnt, (expressionS *) NULL, "dsll",
5528 "d,w,<", tempreg, tempreg, 16);
5529 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5530 tempreg, tempreg, (int) BFD_RELOC_HI16_S);
5531 macro_build (p, &icnt, (expressionS *) NULL, "dsll",
5532 "d,w,<", tempreg, tempreg, 16);
5534 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
5535 "d,v,t", tempreg, tempreg, breg);
5536 macro_build (p, &icnt, &offset_expr, s,
5537 fmt, treg, (int) BFD_RELOC_LO16, tempreg);
5545 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
5546 || nopic_need_relax (offset_expr.X_add_symbol, 1))
5551 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5552 treg, (int) BFD_RELOC_GPREL16,
5554 p = frag_var (rs_machine_dependent, 8, 0,
5555 RELAX_ENCODE (4, 8, 0, 4, 0,
5556 (mips_opts.warn_about_macros
5558 && mips_opts.noat))),
5559 offset_expr.X_add_symbol, 0, NULL);
5562 macro_build_lui (p, &icnt, &offset_expr, tempreg);
5565 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
5566 (int) BFD_RELOC_LO16, tempreg);
5570 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
5571 || nopic_need_relax (offset_expr.X_add_symbol, 1))
5576 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5577 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5578 "d,v,t", tempreg, breg, mips_gp_register);
5579 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5580 treg, (int) BFD_RELOC_GPREL16, tempreg);
5581 p = frag_var (rs_machine_dependent, 12, 0,
5582 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5583 offset_expr.X_add_symbol, 0, NULL);
5585 macro_build_lui (p, &icnt, &offset_expr, tempreg);
5588 macro_build (p, &icnt, (expressionS *) NULL,
5589 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5590 "d,v,t", tempreg, tempreg, breg);
5593 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
5594 (int) BFD_RELOC_LO16, tempreg);
5597 else if (mips_pic == SVR4_PIC && ! mips_big_got)
5601 /* If this is a reference to an external symbol, we want
5602 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5604 <op> $treg,0($tempreg)
5606 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5608 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5609 <op> $treg,0($tempreg)
5610 If there is a base register, we add it to $tempreg before
5611 the <op>. If there is a constant, we stick it in the
5612 <op> instruction. We don't handle constants larger than
5613 16 bits, because we have no way to load the upper 16 bits
5614 (actually, we could handle them for the subset of cases
5615 in which we are not using $at). */
5616 assert (offset_expr.X_op == O_symbol);
5617 expr1.X_add_number = offset_expr.X_add_number;
5618 offset_expr.X_add_number = 0;
5619 if (expr1.X_add_number < -0x8000
5620 || expr1.X_add_number >= 0x8000)
5621 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5623 macro_build ((char *) NULL, &icnt, &offset_expr,
5624 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", tempreg,
5625 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
5626 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
5627 p = frag_var (rs_machine_dependent, 4, 0,
5628 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5629 offset_expr.X_add_symbol, 0, NULL);
5630 macro_build (p, &icnt, &offset_expr,
5631 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5632 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5634 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5635 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5636 "d,v,t", tempreg, tempreg, breg);
5637 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
5638 (int) BFD_RELOC_LO16, tempreg);
5640 else if (mips_pic == SVR4_PIC)
5645 /* If this is a reference to an external symbol, we want
5646 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5647 addu $tempreg,$tempreg,$gp
5648 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5649 <op> $treg,0($tempreg)
5651 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5653 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5654 <op> $treg,0($tempreg)
5655 If there is a base register, we add it to $tempreg before
5656 the <op>. If there is a constant, we stick it in the
5657 <op> instruction. We don't handle constants larger than
5658 16 bits, because we have no way to load the upper 16 bits
5659 (actually, we could handle them for the subset of cases
5660 in which we are not using $at).
5663 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5664 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5665 <op> $treg,0($tempreg)
5667 assert (offset_expr.X_op == O_symbol);
5668 expr1.X_add_number = offset_expr.X_add_number;
5669 offset_expr.X_add_number = 0;
5670 if (expr1.X_add_number < -0x8000
5671 || expr1.X_add_number >= 0x8000)
5672 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5675 macro_build ((char *) NULL, &icnt, &offset_expr,
5676 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5677 "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_PAGE,
5679 macro_build ((char *) NULL, &icnt, &offset_expr,
5680 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5681 "t,r,j", tempreg, tempreg,
5682 BFD_RELOC_MIPS_GOT_OFST);
5684 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5685 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5686 "d,v,t", tempreg, tempreg, breg);
5687 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
5688 (int) BFD_RELOC_LO16, tempreg);
5695 if (reg_needs_delay (mips_gp_register))
5700 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
5701 tempreg, (int) BFD_RELOC_MIPS_GOT_HI16);
5702 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5703 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5704 "d,v,t", tempreg, tempreg, mips_gp_register);
5705 macro_build ((char *) NULL, &icnt, &offset_expr,
5706 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5707 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16,
5709 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5710 RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0),
5711 offset_expr.X_add_symbol, 0, NULL);
5714 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5717 macro_build (p, &icnt, &offset_expr,
5718 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5719 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16,
5722 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5724 macro_build (p, &icnt, &offset_expr,
5725 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5726 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5728 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5729 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5730 "d,v,t", tempreg, tempreg, breg);
5731 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
5732 (int) BFD_RELOC_LO16, tempreg);
5734 else if (mips_pic == EMBEDDED_PIC)
5736 /* If there is no base register, we want
5737 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5738 If there is a base register, we want
5739 addu $tempreg,$breg,$gp
5740 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5742 assert (offset_expr.X_op == O_symbol);
5745 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5746 treg, (int) BFD_RELOC_GPREL16, mips_gp_register);
5751 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5752 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5753 "d,v,t", tempreg, breg, mips_gp_register);
5754 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5755 treg, (int) BFD_RELOC_GPREL16, tempreg);
5768 load_register (&icnt, treg, &imm_expr, 0);
5772 load_register (&icnt, treg, &imm_expr, 1);
5776 if (imm_expr.X_op == O_constant)
5778 load_register (&icnt, AT, &imm_expr, 0);
5779 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5780 "mtc1", "t,G", AT, treg);
5785 assert (offset_expr.X_op == O_symbol
5786 && strcmp (segment_name (S_GET_SEGMENT
5787 (offset_expr.X_add_symbol)),
5789 && offset_expr.X_add_number == 0);
5790 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
5791 treg, (int) BFD_RELOC_MIPS_LITERAL, mips_gp_register);
5796 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
5797 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
5798 order 32 bits of the value and the low order 32 bits are either
5799 zero or in OFFSET_EXPR. */
5800 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
5802 if (HAVE_64BIT_GPRS)
5803 load_register (&icnt, treg, &imm_expr, 1);
5808 if (target_big_endian)
5820 load_register (&icnt, hreg, &imm_expr, 0);
5823 if (offset_expr.X_op == O_absent)
5824 move_register (&icnt, lreg, 0);
5827 assert (offset_expr.X_op == O_constant);
5828 load_register (&icnt, lreg, &offset_expr, 0);
5835 /* We know that sym is in the .rdata section. First we get the
5836 upper 16 bits of the address. */
5837 if (mips_pic == NO_PIC)
5839 macro_build_lui (NULL, &icnt, &offset_expr, AT);
5841 else if (mips_pic == SVR4_PIC)
5843 macro_build ((char *) NULL, &icnt, &offset_expr,
5844 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5845 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
5848 else if (mips_pic == EMBEDDED_PIC)
5850 /* For embedded PIC we pick up the entire address off $gp in
5851 a single instruction. */
5852 macro_build ((char *) NULL, &icnt, &offset_expr,
5853 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j", AT,
5854 mips_gp_register, (int) BFD_RELOC_GPREL16);
5855 offset_expr.X_op = O_constant;
5856 offset_expr.X_add_number = 0;
5861 /* Now we load the register(s). */
5862 if (HAVE_64BIT_GPRS)
5863 macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)",
5864 treg, (int) BFD_RELOC_LO16, AT);
5867 macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)",
5868 treg, (int) BFD_RELOC_LO16, AT);
5871 /* FIXME: How in the world do we deal with the possible
5873 offset_expr.X_add_number += 4;
5874 macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)",
5875 treg + 1, (int) BFD_RELOC_LO16, AT);
5879 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5880 does not become a variant frag. */
5881 frag_wane (frag_now);
5887 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
5888 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
5889 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
5890 the value and the low order 32 bits are either zero or in
5892 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
5894 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS);
5895 if (HAVE_64BIT_FPRS)
5897 assert (HAVE_64BIT_GPRS);
5898 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5899 "dmtc1", "t,S", AT, treg);
5903 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5904 "mtc1", "t,G", AT, treg + 1);
5905 if (offset_expr.X_op == O_absent)
5906 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5907 "mtc1", "t,G", 0, treg);
5910 assert (offset_expr.X_op == O_constant);
5911 load_register (&icnt, AT, &offset_expr, 0);
5912 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5913 "mtc1", "t,G", AT, treg);
5919 assert (offset_expr.X_op == O_symbol
5920 && offset_expr.X_add_number == 0);
5921 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
5922 if (strcmp (s, ".lit8") == 0)
5924 if (mips_opts.isa != ISA_MIPS1)
5926 macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
5927 "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL,
5931 breg = mips_gp_register;
5932 r = BFD_RELOC_MIPS_LITERAL;
5937 assert (strcmp (s, RDATA_SECTION_NAME) == 0);
5938 if (mips_pic == SVR4_PIC)
5939 macro_build ((char *) NULL, &icnt, &offset_expr,
5940 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5941 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
5945 /* FIXME: This won't work for a 64 bit address. */
5946 macro_build_lui (NULL, &icnt, &offset_expr, AT);
5949 if (mips_opts.isa != ISA_MIPS1)
5951 macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
5952 "T,o(b)", treg, (int) BFD_RELOC_LO16, AT);
5954 /* To avoid confusion in tc_gen_reloc, we must ensure
5955 that this does not become a variant frag. */
5956 frag_wane (frag_now);
5967 if (mips_arch == CPU_R4650)
5969 as_bad (_("opcode not supported on this processor"));
5972 /* Even on a big endian machine $fn comes before $fn+1. We have
5973 to adjust when loading from memory. */
5976 assert (mips_opts.isa == ISA_MIPS1);
5977 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
5978 target_big_endian ? treg + 1 : treg,
5980 /* FIXME: A possible overflow which I don't know how to deal
5982 offset_expr.X_add_number += 4;
5983 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
5984 target_big_endian ? treg : treg + 1,
5987 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5988 does not become a variant frag. */
5989 frag_wane (frag_now);
5998 * The MIPS assembler seems to check for X_add_number not
5999 * being double aligned and generating:
6002 * addiu at,at,%lo(foo+1)
6005 * But, the resulting address is the same after relocation so why
6006 * generate the extra instruction?
6008 if (mips_arch == CPU_R4650)
6010 as_bad (_("opcode not supported on this processor"));
6013 /* Itbl support may require additional care here. */
6015 if (mips_opts.isa != ISA_MIPS1)
6026 if (mips_arch == CPU_R4650)
6028 as_bad (_("opcode not supported on this processor"));
6032 if (mips_opts.isa != ISA_MIPS1)
6040 /* Itbl support may require additional care here. */
6045 if (HAVE_64BIT_GPRS)
6056 if (HAVE_64BIT_GPRS)
6066 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6067 loads for the case of doing a pair of loads to simulate an 'ld'.
6068 This is not currently done by the compiler, and assembly coders
6069 writing embedded-pic code can cope. */
6071 if (offset_expr.X_op != O_symbol
6072 && offset_expr.X_op != O_constant)
6074 as_bad (_("expression too complex"));
6075 offset_expr.X_op = O_constant;
6078 /* Even on a big endian machine $fn comes before $fn+1. We have
6079 to adjust when loading from memory. We set coproc if we must
6080 load $fn+1 first. */
6081 /* Itbl support may require additional care here. */
6082 if (! target_big_endian)
6085 if (mips_pic == NO_PIC
6086 || offset_expr.X_op == O_constant)
6090 /* If this is a reference to a GP relative symbol, we want
6091 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6092 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6093 If we have a base register, we use this
6095 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6096 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6097 If this is not a GP relative symbol, we want
6098 lui $at,<sym> (BFD_RELOC_HI16_S)
6099 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6100 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6101 If there is a base register, we add it to $at after the
6102 lui instruction. If there is a constant, we always use
6104 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6105 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6117 tempreg = mips_gp_register;
6124 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6125 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6126 "d,v,t", AT, breg, mips_gp_register);
6132 /* Itbl support may require additional care here. */
6133 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6134 coproc ? treg + 1 : treg,
6135 (int) BFD_RELOC_GPREL16, tempreg);
6136 offset_expr.X_add_number += 4;
6138 /* Set mips_optimize to 2 to avoid inserting an
6140 hold_mips_optimize = mips_optimize;
6142 /* Itbl support may require additional care here. */
6143 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6144 coproc ? treg : treg + 1,
6145 (int) BFD_RELOC_GPREL16, tempreg);
6146 mips_optimize = hold_mips_optimize;
6148 p = frag_var (rs_machine_dependent, 12 + off, 0,
6149 RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1,
6150 used_at && mips_opts.noat),
6151 offset_expr.X_add_symbol, 0, NULL);
6153 /* We just generated two relocs. When tc_gen_reloc
6154 handles this case, it will skip the first reloc and
6155 handle the second. The second reloc already has an
6156 extra addend of 4, which we added above. We must
6157 subtract it out, and then subtract another 4 to make
6158 the first reloc come out right. The second reloc
6159 will come out right because we are going to add 4 to
6160 offset_expr when we build its instruction below.
6162 If we have a symbol, then we don't want to include
6163 the offset, because it will wind up being included
6164 when we generate the reloc. */
6166 if (offset_expr.X_op == O_constant)
6167 offset_expr.X_add_number -= 8;
6170 offset_expr.X_add_number = -4;
6171 offset_expr.X_op = O_constant;
6174 macro_build_lui (p, &icnt, &offset_expr, AT);
6179 macro_build (p, &icnt, (expressionS *) NULL,
6180 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6181 "d,v,t", AT, breg, AT);
6185 /* Itbl support may require additional care here. */
6186 macro_build (p, &icnt, &offset_expr, s, fmt,
6187 coproc ? treg + 1 : treg,
6188 (int) BFD_RELOC_LO16, AT);
6191 /* FIXME: How do we handle overflow here? */
6192 offset_expr.X_add_number += 4;
6193 /* Itbl support may require additional care here. */
6194 macro_build (p, &icnt, &offset_expr, s, fmt,
6195 coproc ? treg : treg + 1,
6196 (int) BFD_RELOC_LO16, AT);
6198 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6202 /* If this is a reference to an external symbol, we want
6203 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6208 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6210 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6211 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6212 If there is a base register we add it to $at before the
6213 lwc1 instructions. If there is a constant we include it
6214 in the lwc1 instructions. */
6216 expr1.X_add_number = offset_expr.X_add_number;
6217 offset_expr.X_add_number = 0;
6218 if (expr1.X_add_number < -0x8000
6219 || expr1.X_add_number >= 0x8000 - 4)
6220 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6225 frag_grow (24 + off);
6226 macro_build ((char *) NULL, &icnt, &offset_expr,
6227 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", AT,
6228 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
6229 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
6231 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6232 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6233 "d,v,t", AT, breg, AT);
6234 /* Itbl support may require additional care here. */
6235 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6236 coproc ? treg + 1 : treg,
6237 (int) BFD_RELOC_LO16, AT);
6238 expr1.X_add_number += 4;
6240 /* Set mips_optimize to 2 to avoid inserting an undesired
6242 hold_mips_optimize = mips_optimize;
6244 /* Itbl support may require additional care here. */
6245 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6246 coproc ? treg : treg + 1,
6247 (int) BFD_RELOC_LO16, AT);
6248 mips_optimize = hold_mips_optimize;
6250 (void) frag_var (rs_machine_dependent, 0, 0,
6251 RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0),
6252 offset_expr.X_add_symbol, 0, NULL);
6254 else if (mips_pic == SVR4_PIC)
6259 /* If this is a reference to an external symbol, we want
6260 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6262 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6267 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6269 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6270 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6271 If there is a base register we add it to $at before the
6272 lwc1 instructions. If there is a constant we include it
6273 in the lwc1 instructions. */
6275 expr1.X_add_number = offset_expr.X_add_number;
6276 offset_expr.X_add_number = 0;
6277 if (expr1.X_add_number < -0x8000
6278 || expr1.X_add_number >= 0x8000 - 4)
6279 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6280 if (reg_needs_delay (mips_gp_register))
6289 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
6290 AT, (int) BFD_RELOC_MIPS_GOT_HI16);
6291 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6292 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6293 "d,v,t", AT, AT, mips_gp_register);
6294 macro_build ((char *) NULL, &icnt, &offset_expr,
6295 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6296 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT);
6297 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
6299 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6300 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6301 "d,v,t", AT, breg, AT);
6302 /* Itbl support may require additional care here. */
6303 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6304 coproc ? treg + 1 : treg,
6305 (int) BFD_RELOC_LO16, AT);
6306 expr1.X_add_number += 4;
6308 /* Set mips_optimize to 2 to avoid inserting an undesired
6310 hold_mips_optimize = mips_optimize;
6312 /* Itbl support may require additional care here. */
6313 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6314 coproc ? treg : treg + 1,
6315 (int) BFD_RELOC_LO16, AT);
6316 mips_optimize = hold_mips_optimize;
6317 expr1.X_add_number -= 4;
6319 p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0,
6320 RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel,
6321 8 + gpdel + off, 1, 0),
6322 offset_expr.X_add_symbol, 0, NULL);
6325 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
6328 macro_build (p, &icnt, &offset_expr,
6329 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6330 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
6333 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
6337 macro_build (p, &icnt, (expressionS *) NULL,
6338 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6339 "d,v,t", AT, breg, AT);
6342 /* Itbl support may require additional care here. */
6343 macro_build (p, &icnt, &expr1, s, fmt,
6344 coproc ? treg + 1 : treg,
6345 (int) BFD_RELOC_LO16, AT);
6347 expr1.X_add_number += 4;
6349 /* Set mips_optimize to 2 to avoid inserting an undesired
6351 hold_mips_optimize = mips_optimize;
6353 /* Itbl support may require additional care here. */
6354 macro_build (p, &icnt, &expr1, s, fmt,
6355 coproc ? treg : treg + 1,
6356 (int) BFD_RELOC_LO16, AT);
6357 mips_optimize = hold_mips_optimize;
6359 else if (mips_pic == EMBEDDED_PIC)
6361 /* If there is no base register, we use
6362 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6363 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6364 If we have a base register, we use
6366 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6367 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6371 tempreg = mips_gp_register;
6376 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6377 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6378 "d,v,t", AT, breg, mips_gp_register);
6383 /* Itbl support may require additional care here. */
6384 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6385 coproc ? treg + 1 : treg,
6386 (int) BFD_RELOC_GPREL16, tempreg);
6387 offset_expr.X_add_number += 4;
6388 /* Itbl support may require additional care here. */
6389 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6390 coproc ? treg : treg + 1,
6391 (int) BFD_RELOC_GPREL16, tempreg);
6407 assert (HAVE_32BIT_ADDRESSES);
6408 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
6409 (int) BFD_RELOC_LO16, breg);
6410 offset_expr.X_add_number += 4;
6411 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1,
6412 (int) BFD_RELOC_LO16, breg);
6415 /* New code added to support COPZ instructions.
6416 This code builds table entries out of the macros in mip_opcodes.
6417 R4000 uses interlocks to handle coproc delays.
6418 Other chips (like the R3000) require nops to be inserted for delays.
6420 FIXME: Currently, we require that the user handle delays.
6421 In order to fill delay slots for non-interlocked chips,
6422 we must have a way to specify delays based on the coprocessor.
6423 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6424 What are the side-effects of the cop instruction?
6425 What cache support might we have and what are its effects?
6426 Both coprocessor & memory require delays. how long???
6427 What registers are read/set/modified?
6429 If an itbl is provided to interpret cop instructions,
6430 this knowledge can be encoded in the itbl spec. */
6444 /* For now we just do C (same as Cz). The parameter will be
6445 stored in insn_opcode by mips_ip. */
6446 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "C",
6451 move_register (&icnt, dreg, sreg);
6454 #ifdef LOSING_COMPILER
6456 /* Try and see if this is a new itbl instruction.
6457 This code builds table entries out of the macros in mip_opcodes.
6458 FIXME: For now we just assemble the expression and pass it's
6459 value along as a 32-bit immediate.
6460 We may want to have the assembler assemble this value,
6461 so that we gain the assembler's knowledge of delay slots,
6463 Would it be more efficient to use mask (id) here? */
6464 if (itbl_have_entries
6465 && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
6467 s = ip->insn_mo->name;
6469 coproc = ITBL_DECODE_PNUM (immed_expr);;
6470 macro_build ((char *) NULL, &icnt, &immed_expr, s, "C");
6477 as_warn (_("Macro used $at after \".set noat\""));
6482 struct mips_cl_insn *ip;
6484 register int treg, sreg, dreg, breg;
6500 bfd_reloc_code_real_type r;
6503 treg = (ip->insn_opcode >> 16) & 0x1f;
6504 dreg = (ip->insn_opcode >> 11) & 0x1f;
6505 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
6506 mask = ip->insn_mo->mask;
6508 expr1.X_op = O_constant;
6509 expr1.X_op_symbol = NULL;
6510 expr1.X_add_symbol = NULL;
6511 expr1.X_add_number = 1;
6515 #endif /* LOSING_COMPILER */
6520 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6521 dbl ? "dmultu" : "multu", "s,t", sreg, treg);
6522 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6529 /* The MIPS assembler some times generates shifts and adds. I'm
6530 not trying to be that fancy. GCC should do this for us
6532 load_register (&icnt, AT, &imm_expr, dbl);
6533 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6534 dbl ? "dmult" : "mult", "s,t", sreg, AT);
6535 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6549 mips_emit_delays (true);
6550 ++mips_opts.noreorder;
6551 mips_any_noreorder = 1;
6553 load_register (&icnt, AT, &imm_expr, dbl);
6554 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6555 dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
6556 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6558 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6559 dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
6560 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d",
6563 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne",
6564 "s,t,q", dreg, AT, 6);
6567 expr1.X_add_number = 8;
6568 macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg,
6570 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
6572 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
6575 --mips_opts.noreorder;
6576 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", dreg);
6589 mips_emit_delays (true);
6590 ++mips_opts.noreorder;
6591 mips_any_noreorder = 1;
6593 load_register (&icnt, AT, &imm_expr, dbl);
6594 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6595 dbl ? "dmultu" : "multu",
6596 "s,t", sreg, imm ? AT : treg);
6597 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d",
6599 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6602 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne",
6606 expr1.X_add_number = 8;
6607 macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0);
6608 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
6610 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
6613 --mips_opts.noreorder;
6617 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
6618 "d,v,t", AT, 0, treg);
6619 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
6620 "d,t,s", AT, sreg, AT);
6621 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
6622 "d,t,s", dreg, sreg, treg);
6623 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6624 "d,v,t", dreg, dreg, AT);
6628 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
6629 "d,v,t", AT, 0, treg);
6630 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv",
6631 "d,t,s", AT, sreg, AT);
6632 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv",
6633 "d,t,s", dreg, sreg, treg);
6634 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6635 "d,v,t", dreg, dreg, AT);
6642 if (imm_expr.X_op != O_constant)
6643 as_bad (_("rotate count too large"));
6644 rot = imm_expr.X_add_number & 0x3f;
6646 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrl",
6647 "d,w,<", dreg, sreg, 0);
6652 l = (rot < 0x20) ? "dsll" : "dsll32";
6653 r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
6655 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
6656 "d,w,<", AT, sreg, rot);
6657 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
6658 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6659 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6660 "d,v,t", dreg, dreg, AT);
6669 if (imm_expr.X_op != O_constant)
6670 as_bad (_("rotate count too large"));
6671 rot = imm_expr.X_add_number & 0x1f;
6673 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
6674 "d,w,<", dreg, sreg, 0);
6677 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
6678 "d,w,<", AT, sreg, rot);
6679 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
6680 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6681 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6682 "d,v,t", dreg, dreg, AT);
6688 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
6689 "d,v,t", AT, 0, treg);
6690 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
6691 "d,t,s", AT, sreg, AT);
6692 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
6693 "d,t,s", dreg, sreg, treg);
6694 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6695 "d,v,t", dreg, dreg, AT);
6699 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
6700 "d,v,t", AT, 0, treg);
6701 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv",
6702 "d,t,s", AT, sreg, AT);
6703 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv",
6704 "d,t,s", dreg, sreg, treg);
6705 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6706 "d,v,t", dreg, dreg, AT);
6713 if (imm_expr.X_op != O_constant)
6714 as_bad (_("rotate count too large"));
6715 rot = imm_expr.X_add_number & 0x3f;
6717 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrl",
6718 "d,w,<", dreg, sreg, 0);
6723 r = (rot < 0x20) ? "dsrl" : "dsrl32";
6724 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
6726 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
6727 "d,w,<", AT, sreg, rot);
6728 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
6729 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6730 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6731 "d,v,t", dreg, dreg, AT);
6740 if (imm_expr.X_op != O_constant)
6741 as_bad (_("rotate count too large"));
6742 rot = imm_expr.X_add_number & 0x1f;
6744 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
6745 "d,w,<", dreg, sreg, 0);
6748 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
6749 "d,w,<", AT, sreg, rot);
6750 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
6751 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6752 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6753 "d,v,t", dreg, dreg, AT);
6759 if (mips_arch == CPU_R4650)
6761 as_bad (_("opcode not supported on this processor"));
6764 assert (mips_opts.isa == ISA_MIPS1);
6765 /* Even on a big endian machine $fn comes before $fn+1. We have
6766 to adjust when storing to memory. */
6767 macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
6768 target_big_endian ? treg + 1 : treg,
6769 (int) BFD_RELOC_LO16, breg);
6770 offset_expr.X_add_number += 4;
6771 macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
6772 target_big_endian ? treg : treg + 1,
6773 (int) BFD_RELOC_LO16, breg);
6778 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6779 treg, (int) BFD_RELOC_LO16);
6781 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6782 sreg, (int) BFD_RELOC_LO16);
6785 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
6786 "d,v,t", dreg, sreg, treg);
6787 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6788 dreg, (int) BFD_RELOC_LO16);
6793 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6795 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6796 sreg, (int) BFD_RELOC_LO16);
6801 as_warn (_("Instruction %s: result is always false"),
6803 move_register (&icnt, dreg, 0);
6806 if (imm_expr.X_op == O_constant
6807 && imm_expr.X_add_number >= 0
6808 && imm_expr.X_add_number < 0x10000)
6810 macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg,
6811 sreg, (int) BFD_RELOC_LO16);
6814 else if (imm_expr.X_op == O_constant
6815 && imm_expr.X_add_number > -0x8000
6816 && imm_expr.X_add_number < 0)
6818 imm_expr.X_add_number = -imm_expr.X_add_number;
6819 macro_build ((char *) NULL, &icnt, &imm_expr,
6820 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
6821 "t,r,j", dreg, sreg,
6822 (int) BFD_RELOC_LO16);
6827 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6828 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
6829 "d,v,t", dreg, sreg, AT);
6832 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg,
6833 (int) BFD_RELOC_LO16);
6838 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
6844 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6846 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6847 (int) BFD_RELOC_LO16);
6850 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
6852 if (imm_expr.X_op == O_constant
6853 && imm_expr.X_add_number >= -0x8000
6854 && imm_expr.X_add_number < 0x8000)
6856 macro_build ((char *) NULL, &icnt, &imm_expr,
6857 mask == M_SGE_I ? "slti" : "sltiu",
6858 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
6863 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6864 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6865 mask == M_SGE_I ? "slt" : "sltu", "d,v,t", dreg, sreg,
6869 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6870 (int) BFD_RELOC_LO16);
6875 case M_SGT: /* sreg > treg <==> treg < sreg */
6881 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6885 case M_SGT_I: /* sreg > I <==> I < sreg */
6891 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6892 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6896 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6902 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6904 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6905 (int) BFD_RELOC_LO16);
6908 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6914 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6915 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6917 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6918 (int) BFD_RELOC_LO16);
6922 if (imm_expr.X_op == O_constant
6923 && imm_expr.X_add_number >= -0x8000
6924 && imm_expr.X_add_number < 0x8000)
6926 macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j",
6927 dreg, sreg, (int) BFD_RELOC_LO16);
6930 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6931 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
6936 if (imm_expr.X_op == O_constant
6937 && imm_expr.X_add_number >= -0x8000
6938 && imm_expr.X_add_number < 0x8000)
6940 macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j",
6941 dreg, sreg, (int) BFD_RELOC_LO16);
6944 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6945 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6946 "d,v,t", dreg, sreg, AT);
6951 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6952 "d,v,t", dreg, 0, treg);
6954 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6955 "d,v,t", dreg, 0, sreg);
6958 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
6959 "d,v,t", dreg, sreg, treg);
6960 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6961 "d,v,t", dreg, 0, dreg);
6966 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6968 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6969 "d,v,t", dreg, 0, sreg);
6974 as_warn (_("Instruction %s: result is always true"),
6976 macro_build ((char *) NULL, &icnt, &expr1,
6977 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
6978 "t,r,j", dreg, 0, (int) BFD_RELOC_LO16);
6981 if (imm_expr.X_op == O_constant
6982 && imm_expr.X_add_number >= 0
6983 && imm_expr.X_add_number < 0x10000)
6985 macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i",
6986 dreg, sreg, (int) BFD_RELOC_LO16);
6989 else if (imm_expr.X_op == O_constant
6990 && imm_expr.X_add_number > -0x8000
6991 && imm_expr.X_add_number < 0)
6993 imm_expr.X_add_number = -imm_expr.X_add_number;
6994 macro_build ((char *) NULL, &icnt, &imm_expr,
6995 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
6996 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
7001 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7002 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
7003 "d,v,t", dreg, sreg, AT);
7006 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
7007 "d,v,t", dreg, 0, dreg);
7015 if (imm_expr.X_op == O_constant
7016 && imm_expr.X_add_number > -0x8000
7017 && imm_expr.X_add_number <= 0x8000)
7019 imm_expr.X_add_number = -imm_expr.X_add_number;
7020 macro_build ((char *) NULL, &icnt, &imm_expr,
7021 dbl ? "daddi" : "addi",
7022 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
7025 load_register (&icnt, AT, &imm_expr, dbl);
7026 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7027 dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
7033 if (imm_expr.X_op == O_constant
7034 && imm_expr.X_add_number > -0x8000
7035 && imm_expr.X_add_number <= 0x8000)
7037 imm_expr.X_add_number = -imm_expr.X_add_number;
7038 macro_build ((char *) NULL, &icnt, &imm_expr,
7039 dbl ? "daddiu" : "addiu",
7040 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
7043 load_register (&icnt, AT, &imm_expr, dbl);
7044 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7045 dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
7066 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7067 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "s,t", sreg,
7073 assert (mips_opts.isa == ISA_MIPS1);
7074 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
7075 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
7078 * Is the double cfc1 instruction a bug in the mips assembler;
7079 * or is there a reason for it?
7081 mips_emit_delays (true);
7082 ++mips_opts.noreorder;
7083 mips_any_noreorder = 1;
7084 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G",
7086 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G",
7088 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7089 expr1.X_add_number = 3;
7090 macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg,
7091 (int) BFD_RELOC_LO16);
7092 expr1.X_add_number = 2;
7093 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT,
7094 (int) BFD_RELOC_LO16);
7095 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G",
7097 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7098 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7099 mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg);
7100 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G",
7102 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7103 --mips_opts.noreorder;
7112 if (offset_expr.X_add_number >= 0x7fff)
7113 as_bad (_("operand overflow"));
7114 /* avoid load delay */
7115 if (! target_big_endian)
7116 ++offset_expr.X_add_number;
7117 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7118 (int) BFD_RELOC_LO16, breg);
7119 if (! target_big_endian)
7120 --offset_expr.X_add_number;
7122 ++offset_expr.X_add_number;
7123 macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT,
7124 (int) BFD_RELOC_LO16, breg);
7125 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7127 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7141 if (offset_expr.X_add_number >= 0x8000 - off)
7142 as_bad (_("operand overflow"));
7143 if (! target_big_endian)
7144 offset_expr.X_add_number += off;
7145 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7146 (int) BFD_RELOC_LO16, breg);
7147 if (! target_big_endian)
7148 offset_expr.X_add_number -= off;
7150 offset_expr.X_add_number += off;
7151 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
7152 (int) BFD_RELOC_LO16, breg);
7166 load_address (&icnt, AT, &offset_expr, &used_at);
7168 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7169 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7170 "d,v,t", AT, AT, breg);
7171 if (! target_big_endian)
7172 expr1.X_add_number = off;
7174 expr1.X_add_number = 0;
7175 macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg,
7176 (int) BFD_RELOC_LO16, AT);
7177 if (! target_big_endian)
7178 expr1.X_add_number = 0;
7180 expr1.X_add_number = off;
7181 macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7182 (int) BFD_RELOC_LO16, AT);
7188 load_address (&icnt, AT, &offset_expr, &used_at);
7190 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7191 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7192 "d,v,t", AT, AT, breg);
7193 if (target_big_endian)
7194 expr1.X_add_number = 0;
7195 macro_build ((char *) NULL, &icnt, &expr1,
7196 mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg,
7197 (int) BFD_RELOC_LO16, AT);
7198 if (target_big_endian)
7199 expr1.X_add_number = 1;
7201 expr1.X_add_number = 0;
7202 macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
7203 (int) BFD_RELOC_LO16, AT);
7204 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7206 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7211 if (offset_expr.X_add_number >= 0x7fff)
7212 as_bad (_("operand overflow"));
7213 if (target_big_endian)
7214 ++offset_expr.X_add_number;
7215 macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg,
7216 (int) BFD_RELOC_LO16, breg);
7217 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
7219 if (target_big_endian)
7220 --offset_expr.X_add_number;
7222 ++offset_expr.X_add_number;
7223 macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT,
7224 (int) BFD_RELOC_LO16, breg);
7237 if (offset_expr.X_add_number >= 0x8000 - off)
7238 as_bad (_("operand overflow"));
7239 if (! target_big_endian)
7240 offset_expr.X_add_number += off;
7241 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7242 (int) BFD_RELOC_LO16, breg);
7243 if (! target_big_endian)
7244 offset_expr.X_add_number -= off;
7246 offset_expr.X_add_number += off;
7247 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
7248 (int) BFD_RELOC_LO16, breg);
7262 load_address (&icnt, AT, &offset_expr, &used_at);
7264 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7265 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7266 "d,v,t", AT, AT, breg);
7267 if (! target_big_endian)
7268 expr1.X_add_number = off;
7270 expr1.X_add_number = 0;
7271 macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg,
7272 (int) BFD_RELOC_LO16, AT);
7273 if (! target_big_endian)
7274 expr1.X_add_number = 0;
7276 expr1.X_add_number = off;
7277 macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7278 (int) BFD_RELOC_LO16, AT);
7283 load_address (&icnt, AT, &offset_expr, &used_at);
7285 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7286 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7287 "d,v,t", AT, AT, breg);
7288 if (! target_big_endian)
7289 expr1.X_add_number = 0;
7290 macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7291 (int) BFD_RELOC_LO16, AT);
7292 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
7294 if (! target_big_endian)
7295 expr1.X_add_number = 1;
7297 expr1.X_add_number = 0;
7298 macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7299 (int) BFD_RELOC_LO16, AT);
7300 if (! target_big_endian)
7301 expr1.X_add_number = 0;
7303 expr1.X_add_number = 1;
7304 macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
7305 (int) BFD_RELOC_LO16, AT);
7306 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7308 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7313 /* FIXME: Check if this is one of the itbl macros, since they
7314 are added dynamically. */
7315 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
7319 as_warn (_("Macro used $at after \".set noat\""));
7322 /* Implement macros in mips16 mode. */
7326 struct mips_cl_insn *ip;
7329 int xreg, yreg, zreg, tmp;
7333 const char *s, *s2, *s3;
7335 mask = ip->insn_mo->mask;
7337 xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
7338 yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY;
7339 zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
7343 expr1.X_op = O_constant;
7344 expr1.X_op_symbol = NULL;
7345 expr1.X_add_symbol = NULL;
7346 expr1.X_add_number = 1;
7365 mips_emit_delays (true);
7366 ++mips_opts.noreorder;
7367 mips_any_noreorder = 1;
7368 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7369 dbl ? "ddiv" : "div",
7370 "0,x,y", xreg, yreg);
7371 expr1.X_add_number = 2;
7372 macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg);
7373 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", "6",
7376 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7377 since that causes an overflow. We should do that as well,
7378 but I don't see how to do the comparisons without a temporary
7380 --mips_opts.noreorder;
7381 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x", zreg);
7400 mips_emit_delays (true);
7401 ++mips_opts.noreorder;
7402 mips_any_noreorder = 1;
7403 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "0,x,y",
7405 expr1.X_add_number = 2;
7406 macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg);
7407 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
7409 --mips_opts.noreorder;
7410 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "x", zreg);
7416 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7417 dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
7418 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "x",
7427 if (imm_expr.X_op != O_constant)
7428 as_bad (_("Unsupported large constant"));
7429 imm_expr.X_add_number = -imm_expr.X_add_number;
7430 macro_build ((char *) NULL, &icnt, &imm_expr,
7431 dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
7435 if (imm_expr.X_op != O_constant)
7436 as_bad (_("Unsupported large constant"));
7437 imm_expr.X_add_number = -imm_expr.X_add_number;
7438 macro_build ((char *) NULL, &icnt, &imm_expr, "addiu",
7443 if (imm_expr.X_op != O_constant)
7444 as_bad (_("Unsupported large constant"));
7445 imm_expr.X_add_number = -imm_expr.X_add_number;
7446 macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu",
7469 goto do_reverse_branch;
7473 goto do_reverse_branch;
7485 goto do_reverse_branch;
7496 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y",
7498 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p");
7525 goto do_addone_branch_i;
7530 goto do_addone_branch_i;
7545 goto do_addone_branch_i;
7552 if (imm_expr.X_op != O_constant)
7553 as_bad (_("Unsupported large constant"));
7554 ++imm_expr.X_add_number;
7557 macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg);
7558 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p");
7562 expr1.X_add_number = 0;
7563 macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg);
7565 move_register (&icnt, xreg, yreg);
7566 expr1.X_add_number = 2;
7567 macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p");
7568 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7569 "neg", "x,w", xreg, xreg);
7573 /* For consistency checking, verify that all bits are specified either
7574 by the match/mask part of the instruction definition, or by the
7577 validate_mips_insn (opc)
7578 const struct mips_opcode *opc;
7580 const char *p = opc->args;
7582 unsigned long used_bits = opc->mask;
7584 if ((used_bits & opc->match) != opc->match)
7586 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7587 opc->name, opc->args);
7590 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7597 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7598 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7600 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
7601 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
7602 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
7603 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7605 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7606 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
7608 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
7610 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
7611 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
7612 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
7613 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
7614 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7615 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
7616 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7617 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7618 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7619 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7620 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
7621 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7622 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7623 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
7624 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7625 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
7626 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7628 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
7629 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
7630 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7631 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
7633 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7634 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7635 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
7636 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7637 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7638 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7639 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
7640 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7641 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7644 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
7645 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
7646 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7648 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7649 c, opc->name, opc->args);
7653 if (used_bits != 0xffffffff)
7655 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7656 ~used_bits & 0xffffffff, opc->name, opc->args);
7662 /* This routine assembles an instruction into its binary format. As a
7663 side effect, it sets one of the global variables imm_reloc or
7664 offset_reloc to the type of relocation to do if one of the operands
7665 is an address expression. */
7670 struct mips_cl_insn *ip;
7675 struct mips_opcode *insn;
7678 unsigned int lastregno = 0;
7684 /* If the instruction contains a '.', we first try to match an instruction
7685 including the '.'. Then we try again without the '.'. */
7687 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
7690 /* If we stopped on whitespace, then replace the whitespace with null for
7691 the call to hash_find. Save the character we replaced just in case we
7692 have to re-parse the instruction. */
7699 insn = (struct mips_opcode *) hash_find (op_hash, str);
7701 /* If we didn't find the instruction in the opcode table, try again, but
7702 this time with just the instruction up to, but not including the
7706 /* Restore the character we overwrite above (if any). */
7710 /* Scan up to the first '.' or whitespace. */
7712 *s != '\0' && *s != '.' && !ISSPACE (*s);
7716 /* If we did not find a '.', then we can quit now. */
7719 insn_error = "unrecognized opcode";
7723 /* Lookup the instruction in the hash table. */
7725 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
7727 insn_error = "unrecognized opcode";
7737 assert (strcmp (insn->name, str) == 0);
7739 if (OPCODE_IS_MEMBER (insn,
7741 | (mips_opts.mips16 ? INSN_MIPS16 : 0)
7742 | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
7743 | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
7749 if (insn->pinfo != INSN_MACRO)
7751 if (mips_arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)
7757 if (insn + 1 < &mips_opcodes[NUMOPCODES]
7758 && strcmp (insn->name, insn[1].name) == 0)
7767 static char buf[100];
7768 if (mips_arch_info->is_isa)
7770 _("opcode not supported at this ISA level (%s)"),
7771 mips_cpu_info_from_isa (mips_opts.isa)->name);
7774 _("opcode not supported on this processor: %s (%s)"),
7775 mips_arch_info->name,
7776 mips_cpu_info_from_isa (mips_opts.isa)->name);
7786 ip->insn_opcode = insn->match;
7788 for (args = insn->args;; ++args)
7792 s += strspn (s, " \t");
7796 case '\0': /* end of args */
7809 ip->insn_opcode |= lastregno << OP_SH_RS;
7813 ip->insn_opcode |= lastregno << OP_SH_RT;
7817 ip->insn_opcode |= lastregno << OP_SH_FT;
7821 ip->insn_opcode |= lastregno << OP_SH_FS;
7827 /* Handle optional base register.
7828 Either the base register is omitted or
7829 we must have a left paren. */
7830 /* This is dependent on the next operand specifier
7831 is a base register specification. */
7832 assert (args[1] == 'b' || args[1] == '5'
7833 || args[1] == '-' || args[1] == '4');
7837 case ')': /* these must match exactly */
7842 case '<': /* must be at least one digit */
7844 * According to the manual, if the shift amount is greater
7845 * than 31 or less than 0, then the shift amount should be
7846 * mod 32. In reality the mips assembler issues an error.
7847 * We issue a warning and mask out all but the low 5 bits.
7849 my_getExpression (&imm_expr, s);
7850 check_absolute_expr (ip, &imm_expr);
7851 if ((unsigned long) imm_expr.X_add_number > 31)
7853 as_warn (_("Improper shift amount (%lu)"),
7854 (unsigned long) imm_expr.X_add_number);
7855 imm_expr.X_add_number &= OP_MASK_SHAMT;
7857 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT;
7858 imm_expr.X_op = O_absent;
7862 case '>': /* shift amount minus 32 */
7863 my_getExpression (&imm_expr, s);
7864 check_absolute_expr (ip, &imm_expr);
7865 if ((unsigned long) imm_expr.X_add_number < 32
7866 || (unsigned long) imm_expr.X_add_number > 63)
7868 ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT;
7869 imm_expr.X_op = O_absent;
7873 case 'k': /* cache code */
7874 case 'h': /* prefx code */
7875 my_getExpression (&imm_expr, s);
7876 check_absolute_expr (ip, &imm_expr);
7877 if ((unsigned long) imm_expr.X_add_number > 31)
7879 as_warn (_("Invalid value for `%s' (%lu)"),
7881 (unsigned long) imm_expr.X_add_number);
7882 imm_expr.X_add_number &= 0x1f;
7885 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE;
7887 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX;
7888 imm_expr.X_op = O_absent;
7892 case 'c': /* break code */
7893 my_getExpression (&imm_expr, s);
7894 check_absolute_expr (ip, &imm_expr);
7895 if ((unsigned long) imm_expr.X_add_number > 1023)
7897 as_warn (_("Illegal break code (%lu)"),
7898 (unsigned long) imm_expr.X_add_number);
7899 imm_expr.X_add_number &= OP_MASK_CODE;
7901 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE;
7902 imm_expr.X_op = O_absent;
7906 case 'q': /* lower break code */
7907 my_getExpression (&imm_expr, s);
7908 check_absolute_expr (ip, &imm_expr);
7909 if ((unsigned long) imm_expr.X_add_number > 1023)
7911 as_warn (_("Illegal lower break code (%lu)"),
7912 (unsigned long) imm_expr.X_add_number);
7913 imm_expr.X_add_number &= OP_MASK_CODE2;
7915 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2;
7916 imm_expr.X_op = O_absent;
7920 case 'B': /* 20-bit syscall/break code. */
7921 my_getExpression (&imm_expr, s);
7922 check_absolute_expr (ip, &imm_expr);
7923 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
7924 as_warn (_("Illegal 20-bit code (%lu)"),
7925 (unsigned long) imm_expr.X_add_number);
7926 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20;
7927 imm_expr.X_op = O_absent;
7931 case 'C': /* Coprocessor code */
7932 my_getExpression (&imm_expr, s);
7933 check_absolute_expr (ip, &imm_expr);
7934 if ((unsigned long) imm_expr.X_add_number >= (1 << 25))
7936 as_warn (_("Coproccesor code > 25 bits (%lu)"),
7937 (unsigned long) imm_expr.X_add_number);
7938 imm_expr.X_add_number &= ((1 << 25) - 1);
7940 ip->insn_opcode |= imm_expr.X_add_number;
7941 imm_expr.X_op = O_absent;
7945 case 'J': /* 19-bit wait code. */
7946 my_getExpression (&imm_expr, s);
7947 check_absolute_expr (ip, &imm_expr);
7948 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
7949 as_warn (_("Illegal 19-bit code (%lu)"),
7950 (unsigned long) imm_expr.X_add_number);
7951 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19;
7952 imm_expr.X_op = O_absent;
7956 case 'P': /* Performance register */
7957 my_getExpression (&imm_expr, s);
7958 check_absolute_expr (ip, &imm_expr);
7959 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
7961 as_warn (_("Invalid performance register (%lu)"),
7962 (unsigned long) imm_expr.X_add_number);
7963 imm_expr.X_add_number &= OP_MASK_PERFREG;
7965 ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG);
7966 imm_expr.X_op = O_absent;
7970 case 'b': /* base register */
7971 case 'd': /* destination register */
7972 case 's': /* source register */
7973 case 't': /* target register */
7974 case 'r': /* both target and source */
7975 case 'v': /* both dest and source */
7976 case 'w': /* both dest and target */
7977 case 'E': /* coprocessor target register */
7978 case 'G': /* coprocessor destination register */
7979 case 'x': /* ignore register name */
7980 case 'z': /* must be zero register */
7981 case 'U': /* destination register (clo/clz). */
7996 while (ISDIGIT (*s));
7998 as_bad (_("Invalid register number (%d)"), regno);
8000 else if (*args == 'E' || *args == 'G')
8004 if (s[1] == 'r' && s[2] == 'a')
8009 else if (s[1] == 'f' && s[2] == 'p')
8014 else if (s[1] == 's' && s[2] == 'p')
8019 else if (s[1] == 'g' && s[2] == 'p')
8024 else if (s[1] == 'a' && s[2] == 't')
8029 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
8034 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
8039 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
8044 else if (itbl_have_entries)
8049 p = s + 1; /* advance past '$' */
8050 n = itbl_get_field (&p); /* n is name */
8052 /* See if this is a register defined in an
8054 if (itbl_get_reg_val (n, &r))
8056 /* Get_field advances to the start of
8057 the next field, so we need to back
8058 rack to the end of the last field. */
8062 s = strchr (s, '\0');
8075 as_warn (_("Used $at without \".set noat\""));
8081 if (c == 'r' || c == 'v' || c == 'w')
8088 /* 'z' only matches $0. */
8089 if (c == 'z' && regno != 0)
8092 /* Now that we have assembled one operand, we use the args string
8093 * to figure out where it goes in the instruction. */
8100 ip->insn_opcode |= regno << OP_SH_RS;
8104 ip->insn_opcode |= regno << OP_SH_RD;
8107 ip->insn_opcode |= regno << OP_SH_RD;
8108 ip->insn_opcode |= regno << OP_SH_RT;
8113 ip->insn_opcode |= regno << OP_SH_RT;
8116 /* This case exists because on the r3000 trunc
8117 expands into a macro which requires a gp
8118 register. On the r6000 or r4000 it is
8119 assembled into a single instruction which
8120 ignores the register. Thus the insn version
8121 is MIPS_ISA2 and uses 'x', and the macro
8122 version is MIPS_ISA1 and uses 't'. */
8125 /* This case is for the div instruction, which
8126 acts differently if the destination argument
8127 is $0. This only matches $0, and is checked
8128 outside the switch. */
8131 /* Itbl operand; not yet implemented. FIXME ?? */
8133 /* What about all other operands like 'i', which
8134 can be specified in the opcode table? */
8144 ip->insn_opcode |= lastregno << OP_SH_RS;
8147 ip->insn_opcode |= lastregno << OP_SH_RT;
8152 case 'O': /* MDMX alignment immediate constant. */
8153 my_getExpression (&imm_expr, s);
8154 check_absolute_expr (ip, &imm_expr);
8155 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
8157 as_warn ("Improper align amount (%ld), using low bits",
8158 (long) imm_expr.X_add_number);
8159 imm_expr.X_add_number &= OP_MASK_ALN;
8161 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN;
8162 imm_expr.X_op = O_absent;
8166 case 'Q': /* MDMX vector, element sel, or const. */
8169 /* MDMX Immediate. */
8170 my_getExpression (&imm_expr, s);
8171 check_absolute_expr (ip, &imm_expr);
8172 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
8174 as_warn (_("Invalid MDMX Immediate (%ld)"),
8175 (long) imm_expr.X_add_number);
8176 imm_expr.X_add_number &= OP_MASK_FT;
8178 imm_expr.X_add_number &= OP_MASK_FT;
8179 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8180 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
8182 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
8183 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT;
8184 imm_expr.X_op = O_absent;
8188 /* Not MDMX Immediate. Fall through. */
8189 case 'X': /* MDMX destination register. */
8190 case 'Y': /* MDMX source register. */
8191 case 'Z': /* MDMX target register. */
8193 case 'D': /* floating point destination register */
8194 case 'S': /* floating point source register */
8195 case 'T': /* floating point target register */
8196 case 'R': /* floating point source register */
8200 /* Accept $fN for FP and MDMX register numbers, and in
8201 addition accept $vN for MDMX register numbers. */
8202 if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2]))
8203 || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v'
8214 while (ISDIGIT (*s));
8217 as_bad (_("Invalid float register number (%d)"), regno);
8219 if ((regno & 1) != 0
8221 && ! (strcmp (str, "mtc1") == 0
8222 || strcmp (str, "mfc1") == 0
8223 || strcmp (str, "lwc1") == 0
8224 || strcmp (str, "swc1") == 0
8225 || strcmp (str, "l.s") == 0
8226 || strcmp (str, "s.s") == 0))
8227 as_warn (_("Float register should be even, was %d"),
8235 if (c == 'V' || c == 'W')
8246 ip->insn_opcode |= regno << OP_SH_FD;
8251 ip->insn_opcode |= regno << OP_SH_FS;
8254 /* This is like 'Z', but also needs to fix the MDMX
8255 vector/scalar select bits. Note that the
8256 scalar immediate case is handled above. */
8259 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
8260 int max_el = (is_qh ? 3 : 7);
8262 my_getExpression(&imm_expr, s);
8263 check_absolute_expr (ip, &imm_expr);
8265 if (imm_expr.X_add_number > max_el)
8266 as_bad(_("Bad element selector %ld"),
8267 (long) imm_expr.X_add_number);
8268 imm_expr.X_add_number &= max_el;
8269 ip->insn_opcode |= (imm_expr.X_add_number
8273 as_warn(_("Expecting ']' found '%s'"), s);
8279 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8280 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
8283 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
8290 ip->insn_opcode |= regno << OP_SH_FT;
8293 ip->insn_opcode |= regno << OP_SH_FR;
8303 ip->insn_opcode |= lastregno << OP_SH_FS;
8306 ip->insn_opcode |= lastregno << OP_SH_FT;
8312 my_getExpression (&imm_expr, s);
8313 if (imm_expr.X_op != O_big
8314 && imm_expr.X_op != O_constant)
8315 insn_error = _("absolute expression required");
8320 my_getExpression (&offset_expr, s);
8321 *imm_reloc = BFD_RELOC_32;
8334 unsigned char temp[8];
8336 unsigned int length;
8341 /* These only appear as the last operand in an
8342 instruction, and every instruction that accepts
8343 them in any variant accepts them in all variants.
8344 This means we don't have to worry about backing out
8345 any changes if the instruction does not match.
8347 The difference between them is the size of the
8348 floating point constant and where it goes. For 'F'
8349 and 'L' the constant is 64 bits; for 'f' and 'l' it
8350 is 32 bits. Where the constant is placed is based
8351 on how the MIPS assembler does things:
8354 f -- immediate value
8357 The .lit4 and .lit8 sections are only used if
8358 permitted by the -G argument.
8360 When generating embedded PIC code, we use the
8361 .lit8 section but not the .lit4 section (we can do
8362 .lit4 inline easily; we need to put .lit8
8363 somewhere in the data segment, and using .lit8
8364 permits the linker to eventually combine identical
8367 The code below needs to know whether the target register
8368 is 32 or 64 bits wide. It relies on the fact 'f' and
8369 'F' are used with GPR-based instructions and 'l' and
8370 'L' are used with FPR-based instructions. */
8372 f64 = *args == 'F' || *args == 'L';
8373 using_gprs = *args == 'F' || *args == 'f';
8375 save_in = input_line_pointer;
8376 input_line_pointer = s;
8377 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
8379 s = input_line_pointer;
8380 input_line_pointer = save_in;
8381 if (err != NULL && *err != '\0')
8383 as_bad (_("Bad floating point constant: %s"), err);
8384 memset (temp, '\0', sizeof temp);
8385 length = f64 ? 8 : 4;
8388 assert (length == (unsigned) (f64 ? 8 : 4));
8392 && (! USE_GLOBAL_POINTER_OPT
8393 || mips_pic == EMBEDDED_PIC
8394 || g_switch_value < 4
8395 || (temp[0] == 0 && temp[1] == 0)
8396 || (temp[2] == 0 && temp[3] == 0))))
8398 imm_expr.X_op = O_constant;
8399 if (! target_big_endian)
8400 imm_expr.X_add_number = bfd_getl32 (temp);
8402 imm_expr.X_add_number = bfd_getb32 (temp);
8405 && ! mips_disable_float_construction
8406 /* Constants can only be constructed in GPRs and
8407 copied to FPRs if the GPRs are at least as wide
8408 as the FPRs. Force the constant into memory if
8409 we are using 64-bit FPRs but the GPRs are only
8412 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
8413 && ((temp[0] == 0 && temp[1] == 0)
8414 || (temp[2] == 0 && temp[3] == 0))
8415 && ((temp[4] == 0 && temp[5] == 0)
8416 || (temp[6] == 0 && temp[7] == 0)))
8418 /* The value is simple enough to load with a couple of
8419 instructions. If using 32-bit registers, set
8420 imm_expr to the high order 32 bits and offset_expr to
8421 the low order 32 bits. Otherwise, set imm_expr to
8422 the entire 64 bit constant. */
8423 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
8425 imm_expr.X_op = O_constant;
8426 offset_expr.X_op = O_constant;
8427 if (! target_big_endian)
8429 imm_expr.X_add_number = bfd_getl32 (temp + 4);
8430 offset_expr.X_add_number = bfd_getl32 (temp);
8434 imm_expr.X_add_number = bfd_getb32 (temp);
8435 offset_expr.X_add_number = bfd_getb32 (temp + 4);
8437 if (offset_expr.X_add_number == 0)
8438 offset_expr.X_op = O_absent;
8440 else if (sizeof (imm_expr.X_add_number) > 4)
8442 imm_expr.X_op = O_constant;
8443 if (! target_big_endian)
8444 imm_expr.X_add_number = bfd_getl64 (temp);
8446 imm_expr.X_add_number = bfd_getb64 (temp);
8450 imm_expr.X_op = O_big;
8451 imm_expr.X_add_number = 4;
8452 if (! target_big_endian)
8454 generic_bignum[0] = bfd_getl16 (temp);
8455 generic_bignum[1] = bfd_getl16 (temp + 2);
8456 generic_bignum[2] = bfd_getl16 (temp + 4);
8457 generic_bignum[3] = bfd_getl16 (temp + 6);
8461 generic_bignum[0] = bfd_getb16 (temp + 6);
8462 generic_bignum[1] = bfd_getb16 (temp + 4);
8463 generic_bignum[2] = bfd_getb16 (temp + 2);
8464 generic_bignum[3] = bfd_getb16 (temp);
8470 const char *newname;
8473 /* Switch to the right section. */
8475 subseg = now_subseg;
8478 default: /* unused default case avoids warnings. */
8480 newname = RDATA_SECTION_NAME;
8481 if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8)
8482 || mips_pic == EMBEDDED_PIC)
8486 if (mips_pic == EMBEDDED_PIC)
8489 newname = RDATA_SECTION_NAME;
8492 assert (!USE_GLOBAL_POINTER_OPT
8493 || g_switch_value >= 4);
8497 new_seg = subseg_new (newname, (subsegT) 0);
8498 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
8499 bfd_set_section_flags (stdoutput, new_seg,
8504 frag_align (*args == 'l' ? 2 : 3, 0, 0);
8505 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
8506 && strcmp (TARGET_OS, "elf") != 0)
8507 record_alignment (new_seg, 4);
8509 record_alignment (new_seg, *args == 'l' ? 2 : 3);
8511 as_bad (_("Can't use floating point insn in this section"));
8513 /* Set the argument to the current address in the
8515 offset_expr.X_op = O_symbol;
8516 offset_expr.X_add_symbol =
8517 symbol_new ("L0\001", now_seg,
8518 (valueT) frag_now_fix (), frag_now);
8519 offset_expr.X_add_number = 0;
8521 /* Put the floating point number into the section. */
8522 p = frag_more ((int) length);
8523 memcpy (p, temp, length);
8525 /* Switch back to the original section. */
8526 subseg_set (seg, subseg);
8531 case 'i': /* 16 bit unsigned immediate */
8532 case 'j': /* 16 bit signed immediate */
8533 *imm_reloc = BFD_RELOC_LO16;
8534 c = my_getSmallExpression (&imm_expr, s);
8541 *imm_reloc = BFD_RELOC_HI16_S;
8542 imm_unmatched_hi = true;
8545 else if (c == S_EX_HIGHEST)
8546 *imm_reloc = BFD_RELOC_MIPS_HIGHEST;
8547 else if (c == S_EX_HIGHER)
8548 *imm_reloc = BFD_RELOC_MIPS_HIGHER;
8549 else if (c == S_EX_GP_REL)
8551 /* This occurs in NewABI only. */
8552 c = my_getSmallExpression (&imm_expr, s);
8554 as_bad (_("bad composition of relocations"));
8557 c = my_getSmallExpression (&imm_expr, s);
8559 as_bad (_("bad composition of relocations"));
8562 imm_reloc[0] = BFD_RELOC_GPREL16;
8563 imm_reloc[1] = BFD_RELOC_MIPS_SUB;
8564 imm_reloc[2] = BFD_RELOC_LO16;
8570 *imm_reloc = BFD_RELOC_HI16;
8572 else if (imm_expr.X_op == O_constant)
8573 imm_expr.X_add_number &= 0xffff;
8577 if ((c == S_EX_NONE && imm_expr.X_op != O_constant)
8578 || ((imm_expr.X_add_number < 0
8579 || imm_expr.X_add_number >= 0x10000)
8580 && imm_expr.X_op == O_constant))
8582 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
8583 !strcmp (insn->name, insn[1].name))
8585 if (imm_expr.X_op == O_constant
8586 || imm_expr.X_op == O_big)
8587 as_bad (_("16 bit expression not in range 0..65535"));
8595 /* The upper bound should be 0x8000, but
8596 unfortunately the MIPS assembler accepts numbers
8597 from 0x8000 to 0xffff and sign extends them, and
8598 we want to be compatible. We only permit this
8599 extended range for an instruction which does not
8600 provide any further alternates, since those
8601 alternates may handle other cases. People should
8602 use the numbers they mean, rather than relying on
8603 a mysterious sign extension. */
8604 more = (insn + 1 < &mips_opcodes[NUMOPCODES] &&
8605 strcmp (insn->name, insn[1].name) == 0);
8610 if ((c == S_EX_NONE && imm_expr.X_op != O_constant)
8611 || ((imm_expr.X_add_number < -0x8000
8612 || imm_expr.X_add_number >= max)
8613 && imm_expr.X_op == O_constant)
8615 && imm_expr.X_add_number < 0
8617 && imm_expr.X_unsigned
8618 && sizeof (imm_expr.X_add_number) <= 4))
8622 if (imm_expr.X_op == O_constant
8623 || imm_expr.X_op == O_big)
8624 as_bad (_("16 bit expression not in range -32768..32767"));
8630 case 'o': /* 16 bit offset */
8631 c = my_getSmallExpression (&offset_expr, s);
8633 /* If this value won't fit into a 16 bit offset, then go
8634 find a macro that will generate the 32 bit offset
8637 && (offset_expr.X_op != O_constant
8638 || offset_expr.X_add_number >= 0x8000
8639 || offset_expr.X_add_number < -0x8000))
8644 if (offset_expr.X_op != O_constant)
8646 offset_expr.X_add_number =
8647 (offset_expr.X_add_number >> 16) & 0xffff;
8649 *offset_reloc = BFD_RELOC_LO16;
8653 case 'p': /* pc relative offset */
8654 if (mips_pic == EMBEDDED_PIC)
8655 *offset_reloc = BFD_RELOC_16_PCREL_S2;
8657 *offset_reloc = BFD_RELOC_16_PCREL;
8658 my_getExpression (&offset_expr, s);
8662 case 'u': /* upper 16 bits */
8663 c = my_getSmallExpression (&imm_expr, s);
8664 *imm_reloc = BFD_RELOC_LO16;
8671 *imm_reloc = BFD_RELOC_HI16_S;
8672 imm_unmatched_hi = true;
8675 else if (c == S_EX_HIGHEST)
8676 *imm_reloc = BFD_RELOC_MIPS_HIGHEST;
8677 else if (c == S_EX_GP_REL)
8679 /* This occurs in NewABI only. */
8680 c = my_getSmallExpression (&imm_expr, s);
8682 as_bad (_("bad composition of relocations"));
8685 c = my_getSmallExpression (&imm_expr, s);
8687 as_bad (_("bad composition of relocations"));
8690 imm_reloc[0] = BFD_RELOC_GPREL16;
8691 imm_reloc[1] = BFD_RELOC_MIPS_SUB;
8692 imm_reloc[2] = BFD_RELOC_HI16_S;
8698 *imm_reloc = BFD_RELOC_HI16;
8700 else if (imm_expr.X_op == O_constant)
8701 imm_expr.X_add_number &= 0xffff;
8703 else if (imm_expr.X_op == O_constant
8704 && (imm_expr.X_add_number < 0
8705 || imm_expr.X_add_number >= 0x10000))
8706 as_bad (_("lui expression not in range 0..65535"));
8710 case 'a': /* 26 bit address */
8711 my_getExpression (&offset_expr, s);
8713 *offset_reloc = BFD_RELOC_MIPS_JMP;
8716 case 'N': /* 3 bit branch condition code */
8717 case 'M': /* 3 bit compare condition code */
8718 if (strncmp (s, "$fcc", 4) != 0)
8728 while (ISDIGIT (*s));
8730 as_bad (_("invalid condition code register $fcc%d"), regno);
8732 ip->insn_opcode |= regno << OP_SH_BCC;
8734 ip->insn_opcode |= regno << OP_SH_CCC;
8738 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
8749 while (ISDIGIT (*s));
8752 c = 8; /* Invalid sel value. */
8755 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
8756 ip->insn_opcode |= c;
8760 as_bad (_("bad char = '%c'\n"), *args);
8765 /* Args don't match. */
8766 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
8767 !strcmp (insn->name, insn[1].name))
8771 insn_error = _("illegal operands");
8776 insn_error = _("illegal operands");
8781 /* This routine assembles an instruction into its binary format when
8782 assembling for the mips16. As a side effect, it sets one of the
8783 global variables imm_reloc or offset_reloc to the type of
8784 relocation to do if one of the operands is an address expression.
8785 It also sets mips16_small and mips16_ext if the user explicitly
8786 requested a small or extended instruction. */
8791 struct mips_cl_insn *ip;
8795 struct mips_opcode *insn;
8798 unsigned int lastregno = 0;
8803 mips16_small = false;
8806 for (s = str; ISLOWER (*s); ++s)
8818 if (s[1] == 't' && s[2] == ' ')
8821 mips16_small = true;
8825 else if (s[1] == 'e' && s[2] == ' ')
8834 insn_error = _("unknown opcode");
8838 if (mips_opts.noautoextend && ! mips16_ext)
8839 mips16_small = true;
8841 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
8843 insn_error = _("unrecognized opcode");
8850 assert (strcmp (insn->name, str) == 0);
8853 ip->insn_opcode = insn->match;
8854 ip->use_extend = false;
8855 imm_expr.X_op = O_absent;
8856 imm_reloc[0] = BFD_RELOC_UNUSED;
8857 imm_reloc[1] = BFD_RELOC_UNUSED;
8858 imm_reloc[2] = BFD_RELOC_UNUSED;
8859 offset_expr.X_op = O_absent;
8860 offset_reloc[0] = BFD_RELOC_UNUSED;
8861 offset_reloc[1] = BFD_RELOC_UNUSED;
8862 offset_reloc[2] = BFD_RELOC_UNUSED;
8863 for (args = insn->args; 1; ++args)
8870 /* In this switch statement we call break if we did not find
8871 a match, continue if we did find a match, or return if we
8880 /* Stuff the immediate value in now, if we can. */
8881 if (imm_expr.X_op == O_constant
8882 && *imm_reloc > BFD_RELOC_UNUSED
8883 && insn->pinfo != INSN_MACRO)
8885 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
8886 imm_expr.X_add_number, true, mips16_small,
8887 mips16_ext, &ip->insn_opcode,
8888 &ip->use_extend, &ip->extend);
8889 imm_expr.X_op = O_absent;
8890 *imm_reloc = BFD_RELOC_UNUSED;
8904 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
8907 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
8923 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
8925 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
8952 while (ISDIGIT (*s));
8955 as_bad (_("invalid register number (%d)"), regno);
8961 if (s[1] == 'r' && s[2] == 'a')
8966 else if (s[1] == 'f' && s[2] == 'p')
8971 else if (s[1] == 's' && s[2] == 'p')
8976 else if (s[1] == 'g' && s[2] == 'p')
8981 else if (s[1] == 'a' && s[2] == 't')
8986 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
8991 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
8996 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
9009 if (c == 'v' || c == 'w')
9011 regno = mips16_to_32_reg_map[lastregno];
9025 regno = mips32_to_16_reg_map[regno];
9030 regno = ILLEGAL_REG;
9035 regno = ILLEGAL_REG;
9040 regno = ILLEGAL_REG;
9045 if (regno == AT && ! mips_opts.noat)
9046 as_warn (_("used $at without \".set noat\""));
9053 if (regno == ILLEGAL_REG)
9060 ip->insn_opcode |= regno << MIPS16OP_SH_RX;
9064 ip->insn_opcode |= regno << MIPS16OP_SH_RY;
9067 ip->insn_opcode |= regno << MIPS16OP_SH_RZ;
9070 ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z;
9076 ip->insn_opcode |= regno << MIPS16OP_SH_REGR32;
9079 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
9080 ip->insn_opcode |= regno << MIPS16OP_SH_REG32R;
9090 if (strncmp (s, "$pc", 3) == 0)
9114 && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0)
9116 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9117 and generate the appropriate reloc. If the text
9118 inside %gprel is not a symbol name with an
9119 optional offset, then we generate a normal reloc
9120 and will probably fail later. */
9121 my_getExpression (&imm_expr, s + sizeof "%gprel" - 1);
9122 if (imm_expr.X_op == O_symbol)
9125 *imm_reloc = BFD_RELOC_MIPS16_GPREL;
9127 ip->use_extend = true;
9134 /* Just pick up a normal expression. */
9135 my_getExpression (&imm_expr, s);
9138 if (imm_expr.X_op == O_register)
9140 /* What we thought was an expression turned out to
9143 if (s[0] == '(' && args[1] == '(')
9145 /* It looks like the expression was omitted
9146 before a register indirection, which means
9147 that the expression is implicitly zero. We
9148 still set up imm_expr, so that we handle
9149 explicit extensions correctly. */
9150 imm_expr.X_op = O_constant;
9151 imm_expr.X_add_number = 0;
9152 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9159 /* We need to relax this instruction. */
9160 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9169 /* We use offset_reloc rather than imm_reloc for the PC
9170 relative operands. This lets macros with both
9171 immediate and address operands work correctly. */
9172 my_getExpression (&offset_expr, s);
9174 if (offset_expr.X_op == O_register)
9177 /* We need to relax this instruction. */
9178 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
9182 case '6': /* break code */
9183 my_getExpression (&imm_expr, s);
9184 check_absolute_expr (ip, &imm_expr);
9185 if ((unsigned long) imm_expr.X_add_number > 63)
9187 as_warn (_("Invalid value for `%s' (%lu)"),
9189 (unsigned long) imm_expr.X_add_number);
9190 imm_expr.X_add_number &= 0x3f;
9192 ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6;
9193 imm_expr.X_op = O_absent;
9197 case 'a': /* 26 bit address */
9198 my_getExpression (&offset_expr, s);
9200 *offset_reloc = BFD_RELOC_MIPS16_JMP;
9201 ip->insn_opcode <<= 16;
9204 case 'l': /* register list for entry macro */
9205 case 'L': /* register list for exit macro */
9215 int freg, reg1, reg2;
9217 while (*s == ' ' || *s == ',')
9221 as_bad (_("can't parse register list"));
9233 while (ISDIGIT (*s))
9255 as_bad (_("invalid register list"));
9260 while (ISDIGIT (*s))
9267 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
9272 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
9277 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
9278 mask |= (reg2 - 3) << 3;
9279 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
9280 mask |= (reg2 - 15) << 1;
9281 else if (reg1 == RA && reg2 == RA)
9285 as_bad (_("invalid register list"));
9289 /* The mask is filled in in the opcode table for the
9290 benefit of the disassembler. We remove it before
9291 applying the actual mask. */
9292 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
9293 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
9297 case 'e': /* extend code */
9298 my_getExpression (&imm_expr, s);
9299 check_absolute_expr (ip, &imm_expr);
9300 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
9302 as_warn (_("Invalid value for `%s' (%lu)"),
9304 (unsigned long) imm_expr.X_add_number);
9305 imm_expr.X_add_number &= 0x7ff;
9307 ip->insn_opcode |= imm_expr.X_add_number;
9308 imm_expr.X_op = O_absent;
9318 /* Args don't match. */
9319 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
9320 strcmp (insn->name, insn[1].name) == 0)
9327 insn_error = _("illegal operands");
9333 /* This structure holds information we know about a mips16 immediate
9336 struct mips16_immed_operand
9338 /* The type code used in the argument string in the opcode table. */
9340 /* The number of bits in the short form of the opcode. */
9342 /* The number of bits in the extended form of the opcode. */
9344 /* The amount by which the short form is shifted when it is used;
9345 for example, the sw instruction has a shift count of 2. */
9347 /* The amount by which the short form is shifted when it is stored
9348 into the instruction code. */
9350 /* Non-zero if the short form is unsigned. */
9352 /* Non-zero if the extended form is unsigned. */
9354 /* Non-zero if the value is PC relative. */
9358 /* The mips16 immediate operand types. */
9360 static const struct mips16_immed_operand mips16_immed_operands[] =
9362 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9363 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9364 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9365 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9366 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
9367 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
9368 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
9369 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
9370 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
9371 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
9372 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
9373 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
9374 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
9375 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
9376 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
9377 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
9378 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9379 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9380 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
9381 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
9382 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
9385 #define MIPS16_NUM_IMMED \
9386 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9388 /* Handle a mips16 instruction with an immediate value. This or's the
9389 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9390 whether an extended value is needed; if one is needed, it sets
9391 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9392 If SMALL is true, an unextended opcode was explicitly requested.
9393 If EXT is true, an extended opcode was explicitly requested. If
9394 WARN is true, warn if EXT does not match reality. */
9397 mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend,
9406 unsigned long *insn;
9407 boolean *use_extend;
9408 unsigned short *extend;
9410 register const struct mips16_immed_operand *op;
9411 int mintiny, maxtiny;
9414 op = mips16_immed_operands;
9415 while (op->type != type)
9418 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
9423 if (type == '<' || type == '>' || type == '[' || type == ']')
9426 maxtiny = 1 << op->nbits;
9431 maxtiny = (1 << op->nbits) - 1;
9436 mintiny = - (1 << (op->nbits - 1));
9437 maxtiny = (1 << (op->nbits - 1)) - 1;
9440 /* Branch offsets have an implicit 0 in the lowest bit. */
9441 if (type == 'p' || type == 'q')
9444 if ((val & ((1 << op->shift) - 1)) != 0
9445 || val < (mintiny << op->shift)
9446 || val > (maxtiny << op->shift))
9451 if (warn && ext && ! needext)
9452 as_warn_where (file, line,
9453 _("extended operand requested but not required"));
9454 if (small && needext)
9455 as_bad_where (file, line, _("invalid unextended operand value"));
9457 if (small || (! ext && ! needext))
9461 *use_extend = false;
9462 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
9463 insnval <<= op->op_shift;
9468 long minext, maxext;
9474 maxext = (1 << op->extbits) - 1;
9478 minext = - (1 << (op->extbits - 1));
9479 maxext = (1 << (op->extbits - 1)) - 1;
9481 if (val < minext || val > maxext)
9482 as_bad_where (file, line,
9483 _("operand value out of range for instruction"));
9486 if (op->extbits == 16)
9488 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
9491 else if (op->extbits == 15)
9493 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
9498 extval = ((val & 0x1f) << 6) | (val & 0x20);
9502 *extend = (unsigned short) extval;
9507 static struct percent_op_match
9510 const enum small_ex_type type;
9515 {"%call_hi", S_EX_CALL_HI},
9516 {"%call_lo", S_EX_CALL_LO},
9517 {"%call16", S_EX_CALL16},
9518 {"%got_disp", S_EX_GOT_DISP},
9519 {"%got_page", S_EX_GOT_PAGE},
9520 {"%got_ofst", S_EX_GOT_OFST},
9521 {"%got_hi", S_EX_GOT_HI},
9522 {"%got_lo", S_EX_GOT_LO},
9524 {"%gp_rel", S_EX_GP_REL},
9525 {"%half", S_EX_HALF},
9526 {"%highest", S_EX_HIGHEST},
9527 {"%higher", S_EX_HIGHER},
9533 /* Parse small expression input. STR gets adjusted to eat up whitespace.
9534 It detects valid "%percent_op(...)" and "($reg)" strings. Percent_op's
9535 can be nested, this is handled by blanking the innermost, parsing the
9536 rest by subsequent calls. */
9539 my_getSmallParser (str, len, nestlevel)
9545 *str += strspn (*str, " \t");
9546 /* Check for expression in parentheses. */
9549 char *b = *str + 1 + strspn (*str + 1, " \t");
9552 /* Check for base register. */
9556 && (e = b + strcspn (b, ") \t"))
9557 && e - b > 1 && e - b < 4)
9560 && ((b[1] == 'f' && b[2] == 'p')
9561 || (b[1] == 's' && b[2] == 'p')
9562 || (b[1] == 'g' && b[2] == 'p')
9563 || (b[1] == 'a' && b[2] == 't')
9565 && ISDIGIT (b[2]))))
9566 || (ISDIGIT (b[1])))
9568 *len = strcspn (*str, ")") + 1;
9569 return S_EX_REGISTER;
9573 /* Check for percent_op (in parentheses). */
9574 else if (b[0] == '%')
9577 return my_getPercentOp (str, len, nestlevel);
9580 /* Some other expression in the parentheses, which can contain
9581 parentheses itself. Attempt to find the matching one. */
9587 for (s = *str + 1; *s && pcnt; s++, (*len)++)
9596 /* Check for percent_op (outside of parentheses). */
9597 else if (*str[0] == '%')
9598 return my_getPercentOp (str, len, nestlevel);
9600 /* Any other expression. */
9605 my_getPercentOp (str, len, nestlevel)
9610 char *tmp = *str + 1;
9613 while (ISALPHA (*tmp) || *tmp == '_')
9615 *tmp = TOLOWER (*tmp);
9618 while (i < (sizeof (percent_op) / sizeof (struct percent_op_match)))
9620 if (strncmp (*str, percent_op[i].str, strlen (percent_op[i].str)))
9624 int type = percent_op[i].type;
9626 /* Only %hi and %lo are allowed for OldABI. */
9627 if (! HAVE_NEWABI && type != S_EX_HI && type != S_EX_LO)
9630 *len = strlen (percent_op[i].str);
9639 my_getSmallExpression (ep, str)
9643 static char *oldstr = NULL;
9649 /* Don't update oldstr if the last call had nested percent_op's. We need
9650 it to parse the outer ones later. */
9657 c = my_getSmallParser (&str, &len, &nestlevel);
9658 if (c != S_EX_NONE && c != S_EX_REGISTER)
9661 while (c != S_EX_NONE && c != S_EX_REGISTER);
9665 /* A percent_op was encountered. Don't try to get an expression if
9666 it is already blanked out. */
9667 if (*(str + strspn (str + 1, " )")) != ')')
9671 /* Let my_getExpression() stop at the closing parenthesis. */
9672 save = *(str + len);
9673 *(str + len) = '\0';
9674 my_getExpression (ep, str);
9675 *(str + len) = save;
9679 /* Blank out including the % sign and the proper matching
9682 char *s = strrchr (oldstr, '%');
9685 for (end = strchr (s, '(') + 1; *end && pcnt; end++)
9689 else if (*end == ')')
9693 memset (s, ' ', end - s);
9697 expr_end = str + len;
9701 else if (c == S_EX_NONE)
9703 my_getExpression (ep, str);
9705 else if (c == S_EX_REGISTER)
9707 ep->X_op = O_constant;
9709 ep->X_add_symbol = NULL;
9710 ep->X_op_symbol = NULL;
9711 ep->X_add_number = 0;
9715 as_fatal (_("internal error"));
9719 /* All percent_op's have been handled. */
9726 my_getExpression (ep, str)
9733 save_in = input_line_pointer;
9734 input_line_pointer = str;
9736 expr_end = input_line_pointer;
9737 input_line_pointer = save_in;
9739 /* If we are in mips16 mode, and this is an expression based on `.',
9740 then we bump the value of the symbol by 1 since that is how other
9741 text symbols are handled. We don't bother to handle complex
9742 expressions, just `.' plus or minus a constant. */
9743 if (mips_opts.mips16
9744 && ep->X_op == O_symbol
9745 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
9746 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg
9747 && symbol_get_frag (ep->X_add_symbol) == frag_now
9748 && symbol_constant_p (ep->X_add_symbol)
9749 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
9750 S_SET_VALUE (ep->X_add_symbol, val + 1);
9753 /* Turn a string in input_line_pointer into a floating point constant
9754 of type TYPE, and store the appropriate bytes in *LITP. The number
9755 of LITTLENUMS emitted is stored in *SIZEP. An error message is
9756 returned, or NULL on OK. */
9759 md_atof (type, litP, sizeP)
9765 LITTLENUM_TYPE words[4];
9781 return _("bad call to md_atof");
9784 t = atof_ieee (input_line_pointer, type, words);
9786 input_line_pointer = t;
9790 if (! target_big_endian)
9792 for (i = prec - 1; i >= 0; i--)
9794 md_number_to_chars (litP, (valueT) words[i], 2);
9800 for (i = 0; i < prec; i++)
9802 md_number_to_chars (litP, (valueT) words[i], 2);
9811 md_number_to_chars (buf, val, n)
9816 if (target_big_endian)
9817 number_to_chars_bigendian (buf, val, n);
9819 number_to_chars_littleendian (buf, val, n);
9823 static int support_64bit_objects(void)
9825 const char **list, **l;
9827 list = bfd_target_list ();
9828 for (l = list; *l != NULL; l++)
9830 /* This is traditional mips */
9831 if (strcmp (*l, "elf64-tradbigmips") == 0
9832 || strcmp (*l, "elf64-tradlittlemips") == 0)
9834 if (strcmp (*l, "elf64-bigmips") == 0
9835 || strcmp (*l, "elf64-littlemips") == 0)
9839 return (*l != NULL);
9841 #endif /* OBJ_ELF */
9843 const char *md_shortopts = "nO::g::G:";
9845 struct option md_longopts[] =
9847 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
9848 {"mips0", no_argument, NULL, OPTION_MIPS1},
9849 {"mips1", no_argument, NULL, OPTION_MIPS1},
9850 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
9851 {"mips2", no_argument, NULL, OPTION_MIPS2},
9852 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
9853 {"mips3", no_argument, NULL, OPTION_MIPS3},
9854 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
9855 {"mips4", no_argument, NULL, OPTION_MIPS4},
9856 #define OPTION_MIPS5 (OPTION_MD_BASE + 5)
9857 {"mips5", no_argument, NULL, OPTION_MIPS5},
9858 #define OPTION_MIPS32 (OPTION_MD_BASE + 6)
9859 {"mips32", no_argument, NULL, OPTION_MIPS32},
9860 #define OPTION_MIPS64 (OPTION_MD_BASE + 7)
9861 {"mips64", no_argument, NULL, OPTION_MIPS64},
9862 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 8)
9863 {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC},
9864 #define OPTION_TRAP (OPTION_MD_BASE + 9)
9865 {"trap", no_argument, NULL, OPTION_TRAP},
9866 {"no-break", no_argument, NULL, OPTION_TRAP},
9867 #define OPTION_BREAK (OPTION_MD_BASE + 10)
9868 {"break", no_argument, NULL, OPTION_BREAK},
9869 {"no-trap", no_argument, NULL, OPTION_BREAK},
9870 #define OPTION_EB (OPTION_MD_BASE + 11)
9871 {"EB", no_argument, NULL, OPTION_EB},
9872 #define OPTION_EL (OPTION_MD_BASE + 12)
9873 {"EL", no_argument, NULL, OPTION_EL},
9874 #define OPTION_MIPS16 (OPTION_MD_BASE + 13)
9875 {"mips16", no_argument, NULL, OPTION_MIPS16},
9876 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 14)
9877 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
9878 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 15)
9879 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
9880 #define OPTION_MNO_7000_HILO_FIX (OPTION_MD_BASE + 16)
9881 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
9882 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
9883 #define OPTION_FP32 (OPTION_MD_BASE + 17)
9884 {"mfp32", no_argument, NULL, OPTION_FP32},
9885 #define OPTION_GP32 (OPTION_MD_BASE + 18)
9886 {"mgp32", no_argument, NULL, OPTION_GP32},
9887 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 19)
9888 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
9889 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 20)
9890 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
9891 #define OPTION_MARCH (OPTION_MD_BASE + 21)
9892 {"march", required_argument, NULL, OPTION_MARCH},
9893 #define OPTION_MTUNE (OPTION_MD_BASE + 22)
9894 {"mtune", required_argument, NULL, OPTION_MTUNE},
9895 #define OPTION_FP64 (OPTION_MD_BASE + 23)
9896 {"mfp64", no_argument, NULL, OPTION_FP64},
9897 #define OPTION_M4650 (OPTION_MD_BASE + 24)
9898 {"m4650", no_argument, NULL, OPTION_M4650},
9899 #define OPTION_NO_M4650 (OPTION_MD_BASE + 25)
9900 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
9901 #define OPTION_M4010 (OPTION_MD_BASE + 26)
9902 {"m4010", no_argument, NULL, OPTION_M4010},
9903 #define OPTION_NO_M4010 (OPTION_MD_BASE + 27)
9904 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
9905 #define OPTION_M4100 (OPTION_MD_BASE + 28)
9906 {"m4100", no_argument, NULL, OPTION_M4100},
9907 #define OPTION_NO_M4100 (OPTION_MD_BASE + 29)
9908 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
9909 #define OPTION_M3900 (OPTION_MD_BASE + 30)
9910 {"m3900", no_argument, NULL, OPTION_M3900},
9911 #define OPTION_NO_M3900 (OPTION_MD_BASE + 31)
9912 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
9913 #define OPTION_GP64 (OPTION_MD_BASE + 32)
9914 {"mgp64", no_argument, NULL, OPTION_GP64},
9915 #define OPTION_MIPS3D (OPTION_MD_BASE + 33)
9916 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
9917 #define OPTION_NO_MIPS3D (OPTION_MD_BASE + 34)
9918 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
9919 #define OPTION_MDMX (OPTION_MD_BASE + 35)
9920 {"mdmx", no_argument, NULL, OPTION_MDMX},
9921 #define OPTION_NO_MDMX (OPTION_MD_BASE + 36)
9922 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
9924 #define OPTION_ELF_BASE (OPTION_MD_BASE + 37)
9925 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
9926 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
9927 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
9928 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
9929 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
9930 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
9931 {"xgot", no_argument, NULL, OPTION_XGOT},
9932 #define OPTION_MABI (OPTION_ELF_BASE + 3)
9933 {"mabi", required_argument, NULL, OPTION_MABI},
9934 #define OPTION_32 (OPTION_ELF_BASE + 4)
9935 {"32", no_argument, NULL, OPTION_32},
9936 #define OPTION_N32 (OPTION_ELF_BASE + 5)
9937 {"n32", no_argument, NULL, OPTION_N32},
9938 #define OPTION_64 (OPTION_ELF_BASE + 6)
9939 {"64", no_argument, NULL, OPTION_64},
9940 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
9941 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
9942 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
9943 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
9944 #endif /* OBJ_ELF */
9945 {NULL, no_argument, NULL, 0}
9947 size_t md_longopts_size = sizeof (md_longopts);
9949 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
9950 NEW_VALUE. Warn if another value was already specified. Note:
9951 we have to defer parsing the -march and -mtune arguments in order
9952 to handle 'from-abi' correctly, since the ABI might be specified
9953 in a later argument. */
9956 mips_set_option_string (string_ptr, new_value)
9957 const char **string_ptr, *new_value;
9959 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
9960 as_warn (_("A different %s was already specified, is now %s"),
9961 string_ptr == &mips_arch_string ? "-march" : "-mtune",
9964 *string_ptr = new_value;
9968 md_parse_option (c, arg)
9974 case OPTION_CONSTRUCT_FLOATS:
9975 mips_disable_float_construction = 0;
9978 case OPTION_NO_CONSTRUCT_FLOATS:
9979 mips_disable_float_construction = 1;
9991 target_big_endian = 1;
9995 target_big_endian = 0;
10003 if (arg && arg[1] == '0')
10013 mips_debug = atoi (arg);
10014 /* When the MIPS assembler sees -g or -g2, it does not do
10015 optimizations which limit full symbolic debugging. We take
10016 that to be equivalent to -O0. */
10017 if (mips_debug == 2)
10022 file_mips_isa = ISA_MIPS1;
10026 file_mips_isa = ISA_MIPS2;
10030 file_mips_isa = ISA_MIPS3;
10034 file_mips_isa = ISA_MIPS4;
10038 file_mips_isa = ISA_MIPS5;
10041 case OPTION_MIPS32:
10042 file_mips_isa = ISA_MIPS32;
10045 case OPTION_MIPS64:
10046 file_mips_isa = ISA_MIPS64;
10050 mips_set_option_string (&mips_tune_string, arg);
10054 mips_set_option_string (&mips_arch_string, arg);
10058 mips_set_option_string (&mips_arch_string, "4650");
10059 mips_set_option_string (&mips_tune_string, "4650");
10062 case OPTION_NO_M4650:
10066 mips_set_option_string (&mips_arch_string, "4010");
10067 mips_set_option_string (&mips_tune_string, "4010");
10070 case OPTION_NO_M4010:
10074 mips_set_option_string (&mips_arch_string, "4100");
10075 mips_set_option_string (&mips_tune_string, "4100");
10078 case OPTION_NO_M4100:
10082 mips_set_option_string (&mips_arch_string, "3900");
10083 mips_set_option_string (&mips_tune_string, "3900");
10086 case OPTION_NO_M3900:
10090 mips_opts.ase_mdmx = 1;
10093 case OPTION_NO_MDMX:
10094 mips_opts.ase_mdmx = 0;
10097 case OPTION_MIPS16:
10098 mips_opts.mips16 = 1;
10099 mips_no_prev_insn (false);
10102 case OPTION_NO_MIPS16:
10103 mips_opts.mips16 = 0;
10104 mips_no_prev_insn (false);
10107 case OPTION_MIPS3D:
10108 mips_opts.ase_mips3d = 1;
10111 case OPTION_NO_MIPS3D:
10112 mips_opts.ase_mips3d = 0;
10115 case OPTION_MEMBEDDED_PIC:
10116 mips_pic = EMBEDDED_PIC;
10117 if (USE_GLOBAL_POINTER_OPT && g_switch_seen)
10119 as_bad (_("-G may not be used with embedded PIC code"));
10122 g_switch_value = 0x7fffffff;
10126 /* When generating ELF code, we permit -KPIC and -call_shared to
10127 select SVR4_PIC, and -non_shared to select no PIC. This is
10128 intended to be compatible with Irix 5. */
10129 case OPTION_CALL_SHARED:
10130 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10132 as_bad (_("-call_shared is supported only for ELF format"));
10135 mips_pic = SVR4_PIC;
10136 if (g_switch_seen && g_switch_value != 0)
10138 as_bad (_("-G may not be used with SVR4 PIC code"));
10141 g_switch_value = 0;
10144 case OPTION_NON_SHARED:
10145 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10147 as_bad (_("-non_shared is supported only for ELF format"));
10153 /* The -xgot option tells the assembler to use 32 offsets when
10154 accessing the got in SVR4_PIC mode. It is for Irix
10159 #endif /* OBJ_ELF */
10162 if (! USE_GLOBAL_POINTER_OPT)
10164 as_bad (_("-G is not supported for this configuration"));
10167 else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC)
10169 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
10173 g_switch_value = atoi (arg);
10178 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10181 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10183 as_bad (_("-32 is supported for ELF format only"));
10186 mips_abi = O32_ABI;
10190 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10192 as_bad (_("-n32 is supported for ELF format only"));
10195 mips_abi = N32_ABI;
10199 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10201 as_bad (_("-64 is supported for ELF format only"));
10204 mips_abi = N64_ABI;
10205 if (! support_64bit_objects())
10206 as_fatal (_("No compiled in support for 64 bit object file format"));
10208 #endif /* OBJ_ELF */
10211 file_mips_gp32 = 1;
10215 file_mips_gp32 = 0;
10219 file_mips_fp32 = 1;
10223 file_mips_fp32 = 0;
10228 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10230 as_bad (_("-mabi is supported for ELF format only"));
10233 if (strcmp (arg, "32") == 0)
10234 mips_abi = O32_ABI;
10235 else if (strcmp (arg, "o64") == 0)
10236 mips_abi = O64_ABI;
10237 else if (strcmp (arg, "n32") == 0)
10238 mips_abi = N32_ABI;
10239 else if (strcmp (arg, "64") == 0)
10241 mips_abi = N64_ABI;
10242 if (! support_64bit_objects())
10243 as_fatal (_("No compiled in support for 64 bit object file "
10246 else if (strcmp (arg, "eabi") == 0)
10247 mips_abi = EABI_ABI;
10250 as_fatal (_("invalid abi -mabi=%s"), arg);
10254 #endif /* OBJ_ELF */
10256 case OPTION_M7000_HILO_FIX:
10257 mips_7000_hilo_fix = true;
10260 case OPTION_MNO_7000_HILO_FIX:
10261 mips_7000_hilo_fix = false;
10265 case OPTION_MDEBUG:
10266 mips_flag_mdebug = true;
10269 case OPTION_NO_MDEBUG:
10270 mips_flag_mdebug = false;
10272 #endif /* OBJ_ELF */
10281 /* Set up globals to generate code for the ISA or processor
10282 described by INFO. */
10285 mips_set_architecture (info)
10286 const struct mips_cpu_info *info;
10290 mips_arch_info = info;
10291 mips_arch = info->cpu;
10292 mips_opts.isa = info->isa;
10297 /* Likewise for tuning. */
10300 mips_set_tune (info)
10301 const struct mips_cpu_info *info;
10305 mips_tune_info = info;
10306 mips_tune = info->cpu;
10312 mips_after_parse_args ()
10314 /* GP relative stuff not working for PE */
10315 if (strncmp (TARGET_OS, "pe", 2) == 0
10316 && g_switch_value != 0)
10319 as_bad (_("-G not supported in this configuration."));
10320 g_switch_value = 0;
10323 /* The following code determines the architecture and register size.
10324 Similar code was added to GCC 3.3 (see override_options() in
10325 config/mips/mips.c). The GAS and GCC code should be kept in sync
10326 as much as possible. */
10328 if (mips_arch_string != 0)
10329 mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string));
10331 if (mips_tune_string != 0)
10332 mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string));
10334 if (file_mips_isa != ISA_UNKNOWN)
10336 /* Handle -mipsN. At this point, file_mips_isa contains the
10337 ISA level specified by -mipsN, while mips_opts.isa contains
10338 the -march selection (if any). */
10339 if (mips_arch_info != 0)
10341 /* -march takes precedence over -mipsN, since it is more descriptive.
10342 There's no harm in specifying both as long as the ISA levels
10344 if (file_mips_isa != mips_opts.isa)
10345 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10346 mips_cpu_info_from_isa (file_mips_isa)->name,
10347 mips_cpu_info_from_isa (mips_opts.isa)->name);
10350 mips_set_architecture (mips_cpu_info_from_isa (file_mips_isa));
10353 if (mips_arch_info == 0)
10354 mips_set_architecture (mips_parse_cpu ("default CPU",
10355 MIPS_CPU_STRING_DEFAULT));
10357 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (mips_opts.isa))
10358 as_bad ("-march=%s is not compatible with the selected ABI",
10359 mips_arch_info->name);
10361 /* Optimize for mips_arch, unless -mtune selects a different processor. */
10362 if (mips_tune_info == 0)
10363 mips_set_tune (mips_arch_info);
10365 if (file_mips_gp32 >= 0)
10367 /* The user specified the size of the integer registers. Make sure
10368 it agrees with the ABI and ISA. */
10369 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
10370 as_bad (_("-mgp64 used with a 32-bit processor"));
10371 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
10372 as_bad (_("-mgp32 used with a 64-bit ABI"));
10373 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
10374 as_bad (_("-mgp64 used with a 32-bit ABI"));
10378 /* Infer the integer register size from the ABI and processor.
10379 Restrict ourselves to 32-bit registers if that's all the
10380 processor has, or if the ABI cannot handle 64-bit registers. */
10381 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
10382 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
10385 /* ??? GAS treats single-float processors as though they had 64-bit
10386 float registers (although it complains when double-precision
10387 instructions are used). As things stand, saying they have 32-bit
10388 registers would lead to spurious "register must be even" messages.
10389 So here we assume float registers are always the same size as
10390 integer ones, unless the user says otherwise. */
10391 if (file_mips_fp32 < 0)
10392 file_mips_fp32 = file_mips_gp32;
10394 /* End of GCC-shared inference code. */
10396 /* ??? When do we want this flag to be set? Who uses it? */
10397 if (file_mips_gp32 == 1
10398 && mips_abi == NO_ABI
10399 && ISA_HAS_64BIT_REGS (mips_opts.isa))
10400 mips_32bitmode = 1;
10402 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
10403 as_bad (_("trap exception not supported at ISA 1"));
10405 /* If the selected architecture includes support for ASEs, enable
10406 generation of code for them. */
10407 if (mips_opts.mips16 == -1)
10408 mips_opts.mips16 = (CPU_HAS_MIPS16 (mips_arch)) ? 1 : 0;
10409 if (mips_opts.ase_mips3d == -1)
10410 mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (mips_arch)) ? 1 : 0;
10411 if (mips_opts.ase_mdmx == -1)
10412 mips_opts.ase_mdmx = (CPU_HAS_MDMX (mips_arch)) ? 1 : 0;
10414 file_mips_isa = mips_opts.isa;
10415 file_ase_mips16 = mips_opts.mips16;
10416 file_ase_mips3d = mips_opts.ase_mips3d;
10417 file_ase_mdmx = mips_opts.ase_mdmx;
10418 mips_opts.gp32 = file_mips_gp32;
10419 mips_opts.fp32 = file_mips_fp32;
10424 if (mips_flag_mdebug < 0)
10426 #ifdef OBJ_MAYBE_ECOFF
10427 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
10428 mips_flag_mdebug = 1;
10430 #endif /* OBJ_MAYBE_ECOFF */
10431 mips_flag_mdebug = 0;
10436 mips_init_after_args ()
10438 /* initialize opcodes */
10439 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
10440 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
10444 md_pcrel_from (fixP)
10447 if (OUTPUT_FLAVOR != bfd_target_aout_flavour
10448 && fixP->fx_addsy != (symbolS *) NULL
10449 && ! S_IS_DEFINED (fixP->fx_addsy))
10451 /* This makes a branch to an undefined symbol be a branch to the
10452 current location. */
10453 if (mips_pic == EMBEDDED_PIC)
10459 /* Return the address of the delay slot. */
10460 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10463 /* This is called before the symbol table is processed. In order to
10464 work with gcc when using mips-tfile, we must keep all local labels.
10465 However, in other cases, we want to discard them. If we were
10466 called with -g, but we didn't see any debugging information, it may
10467 mean that gcc is smuggling debugging information through to
10468 mips-tfile, in which case we must generate all local labels. */
10471 mips_frob_file_before_adjust ()
10473 #ifndef NO_ECOFF_DEBUGGING
10474 if (ECOFF_DEBUGGING
10476 && ! ecoff_debugging_seen)
10477 flag_keep_locals = 1;
10481 /* Sort any unmatched HI16_S relocs so that they immediately precede
10482 the corresponding LO reloc. This is called before md_apply_fix3 and
10483 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10484 explicit use of the %hi modifier. */
10489 struct mips_hi_fixup *l;
10491 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
10493 segment_info_type *seginfo;
10496 assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S);
10498 /* Check quickly whether the next fixup happens to be a matching
10500 if (l->fixp->fx_next != NULL
10501 && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16
10502 && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
10503 && l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
10506 /* Look through the fixups for this segment for a matching %lo.
10507 When we find one, move the %hi just in front of it. We do
10508 this in two passes. In the first pass, we try to find a
10509 unique %lo. In the second pass, we permit multiple %hi
10510 relocs for a single %lo (this is a GNU extension). */
10511 seginfo = seg_info (l->seg);
10512 for (pass = 0; pass < 2; pass++)
10517 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
10519 /* Check whether this is a %lo fixup which matches l->fixp. */
10520 if (f->fx_r_type == BFD_RELOC_LO16
10521 && f->fx_addsy == l->fixp->fx_addsy
10522 && f->fx_offset == l->fixp->fx_offset
10525 || prev->fx_r_type != BFD_RELOC_HI16_S
10526 || prev->fx_addsy != f->fx_addsy
10527 || prev->fx_offset != f->fx_offset))
10531 /* Move l->fixp before f. */
10532 for (pf = &seginfo->fix_root;
10534 pf = &(*pf)->fx_next)
10535 assert (*pf != NULL);
10537 *pf = l->fixp->fx_next;
10539 l->fixp->fx_next = f;
10541 seginfo->fix_root = l->fixp;
10543 prev->fx_next = l->fixp;
10554 #if 0 /* GCC code motion plus incomplete dead code elimination
10555 can leave a %hi without a %lo. */
10557 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
10558 _("Unmatched %%hi reloc"));
10564 /* When generating embedded PIC code we need to use a special
10565 relocation to represent the difference of two symbols in the .text
10566 section (switch tables use a difference of this sort). See
10567 include/coff/mips.h for details. This macro checks whether this
10568 fixup requires the special reloc. */
10569 #define SWITCH_TABLE(fixp) \
10570 ((fixp)->fx_r_type == BFD_RELOC_32 \
10571 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
10572 && (fixp)->fx_addsy != NULL \
10573 && (fixp)->fx_subsy != NULL \
10574 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
10575 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
10577 /* When generating embedded PIC code we must keep all PC relative
10578 relocations, in case the linker has to relax a call. We also need
10579 to keep relocations for switch table entries.
10581 We may have combined relocations without symbols in the N32/N64 ABI.
10582 We have to prevent gas from dropping them. */
10585 mips_force_relocation (fixp)
10588 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
10589 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY
10590 || S_FORCE_RELOC (fixp->fx_addsy))
10594 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
10595 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
10596 || fixp->fx_r_type == BFD_RELOC_HI16_S
10597 || fixp->fx_r_type == BFD_RELOC_LO16))
10600 return (mips_pic == EMBEDDED_PIC
10602 || SWITCH_TABLE (fixp)
10603 || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S
10604 || fixp->fx_r_type == BFD_RELOC_PCREL_LO16));
10609 mips_need_elf_addend_fixup (fixP)
10612 if (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16)
10614 if (mips_pic == EMBEDDED_PIC
10615 && S_IS_WEAK (fixP->fx_addsy))
10617 if (mips_pic != EMBEDDED_PIC
10618 && (S_IS_WEAK (fixP->fx_addsy)
10619 || S_IS_EXTERNAL (fixP->fx_addsy))
10620 && !S_IS_COMMON (fixP->fx_addsy))
10622 if (symbol_used_in_reloc_p (fixP->fx_addsy)
10623 && (((bfd_get_section_flags (stdoutput,
10624 S_GET_SEGMENT (fixP->fx_addsy))
10625 & SEC_LINK_ONCE) != 0)
10626 || !strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)),
10628 sizeof (".gnu.linkonce") - 1)))
10634 /* Apply a fixup to the object file. */
10637 md_apply_fix3 (fixP, valP, seg)
10640 segT seg ATTRIBUTE_UNUSED;
10646 assert (fixP->fx_size == 4
10647 || fixP->fx_r_type == BFD_RELOC_16
10648 || fixP->fx_r_type == BFD_RELOC_32
10649 || fixP->fx_r_type == BFD_RELOC_MIPS_JMP
10650 || fixP->fx_r_type == BFD_RELOC_HI16_S
10651 || fixP->fx_r_type == BFD_RELOC_LO16
10652 || fixP->fx_r_type == BFD_RELOC_GPREL16
10653 || fixP->fx_r_type == BFD_RELOC_MIPS_LITERAL
10654 || fixP->fx_r_type == BFD_RELOC_GPREL32
10655 || fixP->fx_r_type == BFD_RELOC_64
10656 || fixP->fx_r_type == BFD_RELOC_CTOR
10657 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
10658 || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHEST
10659 || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHER
10660 || fixP->fx_r_type == BFD_RELOC_MIPS_SCN_DISP
10661 || fixP->fx_r_type == BFD_RELOC_MIPS_REL16
10662 || fixP->fx_r_type == BFD_RELOC_MIPS_RELGOT
10663 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
10664 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
10665 || fixP->fx_r_type == BFD_RELOC_MIPS_JALR);
10669 /* If we aren't adjusting this fixup to be against the section
10670 symbol, we need to adjust the value. */
10672 if (fixP->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour)
10674 if (mips_need_elf_addend_fixup (fixP))
10676 reloc_howto_type *howto;
10677 valueT symval = S_GET_VALUE (fixP->fx_addsy);
10681 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
10682 if (value != 0 && howto->partial_inplace && ! fixP->fx_pcrel)
10684 /* In this case, the bfd_install_relocation routine will
10685 incorrectly add the symbol value back in. We just want
10686 the addend to appear in the object file. */
10689 /* Make sure the addend is still non-zero. If it became zero
10690 after the last operation, set it to a spurious value and
10691 subtract the same value from the object file's contents. */
10696 /* The in-place addends for LO16 relocations are signed;
10697 leave the matching HI16 in-place addends as zero. */
10698 if (fixP->fx_r_type != BFD_RELOC_HI16_S)
10700 bfd_vma contents, mask, field;
10702 contents = bfd_get_bits (fixP->fx_frag->fr_literal
10705 target_big_endian);
10707 /* MASK has bits set where the relocation should go.
10708 FIELD is -value, shifted into the appropriate place
10709 for this relocation. */
10710 mask = 1 << (howto->bitsize - 1);
10711 mask = (((mask - 1) << 1) | 1) << howto->bitpos;
10712 field = (-value >> howto->rightshift) << howto->bitpos;
10714 bfd_put_bits ((field & mask) | (contents & ~mask),
10715 fixP->fx_frag->fr_literal + fixP->fx_where,
10717 target_big_endian);
10723 /* This code was generated using trial and error and so is
10724 fragile and not trustworthy. If you change it, you should
10725 rerun the elf-rel, elf-rel2, and empic testcases and ensure
10726 they still pass. */
10727 if (fixP->fx_pcrel || fixP->fx_subsy != NULL)
10729 value += fixP->fx_frag->fr_address + fixP->fx_where;
10731 /* BFD's REL handling, for MIPS, is _very_ weird.
10732 This gives the right results, but it can't possibly
10733 be the way things are supposed to work. */
10734 if ((fixP->fx_r_type != BFD_RELOC_16_PCREL
10735 && fixP->fx_r_type != BFD_RELOC_16_PCREL_S2)
10736 || S_GET_SEGMENT (fixP->fx_addsy) != undefined_section)
10737 value += fixP->fx_frag->fr_address + fixP->fx_where;
10742 fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc. */
10744 if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel)
10747 switch (fixP->fx_r_type)
10749 case BFD_RELOC_MIPS_JMP:
10750 case BFD_RELOC_MIPS_SHIFT5:
10751 case BFD_RELOC_MIPS_SHIFT6:
10752 case BFD_RELOC_MIPS_GOT_DISP:
10753 case BFD_RELOC_MIPS_GOT_PAGE:
10754 case BFD_RELOC_MIPS_GOT_OFST:
10755 case BFD_RELOC_MIPS_SUB:
10756 case BFD_RELOC_MIPS_INSERT_A:
10757 case BFD_RELOC_MIPS_INSERT_B:
10758 case BFD_RELOC_MIPS_DELETE:
10759 case BFD_RELOC_MIPS_HIGHEST:
10760 case BFD_RELOC_MIPS_HIGHER:
10761 case BFD_RELOC_MIPS_SCN_DISP:
10762 case BFD_RELOC_MIPS_REL16:
10763 case BFD_RELOC_MIPS_RELGOT:
10764 case BFD_RELOC_MIPS_JALR:
10765 case BFD_RELOC_HI16:
10766 case BFD_RELOC_HI16_S:
10767 case BFD_RELOC_GPREL16:
10768 case BFD_RELOC_MIPS_LITERAL:
10769 case BFD_RELOC_MIPS_CALL16:
10770 case BFD_RELOC_MIPS_GOT16:
10771 case BFD_RELOC_GPREL32:
10772 case BFD_RELOC_MIPS_GOT_HI16:
10773 case BFD_RELOC_MIPS_GOT_LO16:
10774 case BFD_RELOC_MIPS_CALL_HI16:
10775 case BFD_RELOC_MIPS_CALL_LO16:
10776 case BFD_RELOC_MIPS16_GPREL:
10777 if (fixP->fx_pcrel)
10778 as_bad_where (fixP->fx_file, fixP->fx_line,
10779 _("Invalid PC relative reloc"));
10780 /* Nothing needed to do. The value comes from the reloc entry */
10783 case BFD_RELOC_MIPS16_JMP:
10784 /* We currently always generate a reloc against a symbol, which
10785 means that we don't want an addend even if the symbol is
10787 fixP->fx_addnumber = 0;
10790 case BFD_RELOC_PCREL_HI16_S:
10791 /* The addend for this is tricky if it is internal, so we just
10792 do everything here rather than in bfd_install_relocation. */
10793 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
10798 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
10800 /* For an external symbol adjust by the address to make it
10801 pcrel_offset. We use the address of the RELLO reloc
10802 which follows this one. */
10803 value += (fixP->fx_next->fx_frag->fr_address
10804 + fixP->fx_next->fx_where);
10806 value = ((value + 0x8000) >> 16) & 0xffff;
10807 buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where;
10808 if (target_big_endian)
10810 md_number_to_chars ((char *) buf, value, 2);
10813 case BFD_RELOC_PCREL_LO16:
10814 /* The addend for this is tricky if it is internal, so we just
10815 do everything here rather than in bfd_install_relocation. */
10816 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
10821 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
10822 value += fixP->fx_frag->fr_address + fixP->fx_where;
10823 buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where;
10824 if (target_big_endian)
10826 md_number_to_chars ((char *) buf, value, 2);
10830 /* This is handled like BFD_RELOC_32, but we output a sign
10831 extended value if we are only 32 bits. */
10833 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
10835 if (8 <= sizeof (valueT))
10836 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
10843 w1 = w2 = fixP->fx_where;
10844 if (target_big_endian)
10848 md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4);
10849 if ((value & 0x80000000) != 0)
10853 md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4);
10858 case BFD_RELOC_RVA:
10860 /* If we are deleting this reloc entry, we must fill in the
10861 value now. This can happen if we have a .word which is not
10862 resolved when it appears but is later defined. We also need
10863 to fill in the value if this is an embedded PIC switch table
10866 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
10867 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
10872 /* If we are deleting this reloc entry, we must fill in the
10874 assert (fixP->fx_size == 2);
10876 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
10880 case BFD_RELOC_LO16:
10881 /* When handling an embedded PIC switch statement, we can wind
10882 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
10885 if (value + 0x8000 > 0xffff)
10886 as_bad_where (fixP->fx_file, fixP->fx_line,
10887 _("relocation overflow"));
10888 buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where;
10889 if (target_big_endian)
10891 md_number_to_chars ((char *) buf, value, 2);
10895 case BFD_RELOC_16_PCREL_S2:
10896 if ((value & 0x3) != 0)
10897 as_bad_where (fixP->fx_file, fixP->fx_line,
10898 _("Branch to odd address (%lx)"), (long) value);
10900 /* Fall through. */
10902 case BFD_RELOC_16_PCREL:
10904 * We need to save the bits in the instruction since fixup_segment()
10905 * might be deleting the relocation entry (i.e., a branch within
10906 * the current segment).
10908 if (!fixP->fx_done && value != 0)
10910 /* If 'value' is zero, the remaining reloc code won't actually
10911 do the store, so it must be done here. This is probably
10912 a bug somewhere. */
10914 && (fixP->fx_r_type != BFD_RELOC_16_PCREL_S2
10915 || fixP->fx_addsy == NULL /* ??? */
10916 || ! S_IS_DEFINED (fixP->fx_addsy)))
10917 value -= fixP->fx_frag->fr_address + fixP->fx_where;
10919 value = (offsetT) value >> 2;
10921 /* update old instruction data */
10922 buf = (bfd_byte *) (fixP->fx_where + fixP->fx_frag->fr_literal);
10923 if (target_big_endian)
10924 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
10926 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
10928 if (value + 0x8000 <= 0xffff)
10929 insn |= value & 0xffff;
10932 /* The branch offset is too large. If this is an
10933 unconditional branch, and we are not generating PIC code,
10934 we can convert it to an absolute jump instruction. */
10935 if (mips_pic == NO_PIC
10937 && fixP->fx_frag->fr_address >= text_section->vma
10938 && (fixP->fx_frag->fr_address
10939 < text_section->vma + text_section->_raw_size)
10940 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
10941 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
10942 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
10944 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
10945 insn = 0x0c000000; /* jal */
10947 insn = 0x08000000; /* j */
10948 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
10950 fixP->fx_addsy = section_symbol (text_section);
10951 fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP);
10955 /* FIXME. It would be possible in principle to handle
10956 conditional branches which overflow. They could be
10957 transformed into a branch around a jump. This would
10958 require setting up variant frags for each different
10959 branch type. The native MIPS assembler attempts to
10960 handle these cases, but it appears to do it
10962 as_bad_where (fixP->fx_file, fixP->fx_line,
10963 _("Branch out of range"));
10967 md_number_to_chars ((char *) buf, (valueT) insn, 4);
10970 case BFD_RELOC_VTABLE_INHERIT:
10973 && !S_IS_DEFINED (fixP->fx_addsy)
10974 && !S_IS_WEAK (fixP->fx_addsy))
10975 S_SET_WEAK (fixP->fx_addsy);
10978 case BFD_RELOC_VTABLE_ENTRY:
10992 const struct mips_opcode *p;
10993 int treg, sreg, dreg, shamt;
10998 for (i = 0; i < NUMOPCODES; ++i)
11000 p = &mips_opcodes[i];
11001 if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO))
11003 printf ("%08lx %s\t", oc, p->name);
11004 treg = (oc >> 16) & 0x1f;
11005 sreg = (oc >> 21) & 0x1f;
11006 dreg = (oc >> 11) & 0x1f;
11007 shamt = (oc >> 6) & 0x1f;
11009 for (args = p->args;; ++args)
11020 printf ("%c", *args);
11024 assert (treg == sreg);
11025 printf ("$%d,$%d", treg, sreg);
11030 printf ("$%d", dreg);
11035 printf ("$%d", treg);
11039 printf ("0x%x", treg);
11044 printf ("$%d", sreg);
11048 printf ("0x%08lx", oc & 0x1ffffff);
11055 printf ("%d", imm);
11060 printf ("$%d", shamt);
11071 printf (_("%08lx UNDEFINED\n"), oc);
11082 name = input_line_pointer;
11083 c = get_symbol_end ();
11084 p = (symbolS *) symbol_find_or_make (name);
11085 *input_line_pointer = c;
11089 /* Align the current frag to a given power of two. The MIPS assembler
11090 also automatically adjusts any preceding label. */
11093 mips_align (to, fill, label)
11098 mips_emit_delays (false);
11099 frag_align (to, fill, 0);
11100 record_alignment (now_seg, to);
11103 assert (S_GET_SEGMENT (label) == now_seg);
11104 symbol_set_frag (label, frag_now);
11105 S_SET_VALUE (label, (valueT) frag_now_fix ());
11109 /* Align to a given power of two. .align 0 turns off the automatic
11110 alignment used by the data creating pseudo-ops. */
11114 int x ATTRIBUTE_UNUSED;
11117 register long temp_fill;
11118 long max_alignment = 15;
11122 o Note that the assembler pulls down any immediately preceeding label
11123 to the aligned address.
11124 o It's not documented but auto alignment is reinstated by
11125 a .align pseudo instruction.
11126 o Note also that after auto alignment is turned off the mips assembler
11127 issues an error on attempt to assemble an improperly aligned data item.
11132 temp = get_absolute_expression ();
11133 if (temp > max_alignment)
11134 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
11137 as_warn (_("Alignment negative: 0 assumed."));
11140 if (*input_line_pointer == ',')
11142 ++input_line_pointer;
11143 temp_fill = get_absolute_expression ();
11150 mips_align (temp, (int) temp_fill,
11151 insn_labels != NULL ? insn_labels->label : NULL);
11158 demand_empty_rest_of_line ();
11162 mips_flush_pending_output ()
11164 mips_emit_delays (false);
11165 mips_clear_insn_labels ();
11174 /* When generating embedded PIC code, we only use the .text, .lit8,
11175 .sdata and .sbss sections. We change the .data and .rdata
11176 pseudo-ops to use .sdata. */
11177 if (mips_pic == EMBEDDED_PIC
11178 && (sec == 'd' || sec == 'r'))
11182 /* The ELF backend needs to know that we are changing sections, so
11183 that .previous works correctly. We could do something like check
11184 for an obj_section_change_hook macro, but that might be confusing
11185 as it would not be appropriate to use it in the section changing
11186 functions in read.c, since obj-elf.c intercepts those. FIXME:
11187 This should be cleaner, somehow. */
11188 obj_elf_section_change_hook ();
11191 mips_emit_delays (false);
11201 subseg_set (bss_section, (subsegT) get_absolute_expression ());
11202 demand_empty_rest_of_line ();
11206 if (USE_GLOBAL_POINTER_OPT)
11208 seg = subseg_new (RDATA_SECTION_NAME,
11209 (subsegT) get_absolute_expression ());
11210 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11212 bfd_set_section_flags (stdoutput, seg,
11218 if (strcmp (TARGET_OS, "elf") != 0)
11219 record_alignment (seg, 4);
11221 demand_empty_rest_of_line ();
11225 as_bad (_("No read only data section in this object file format"));
11226 demand_empty_rest_of_line ();
11232 if (USE_GLOBAL_POINTER_OPT)
11234 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
11235 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11237 bfd_set_section_flags (stdoutput, seg,
11238 SEC_ALLOC | SEC_LOAD | SEC_RELOC
11240 if (strcmp (TARGET_OS, "elf") != 0)
11241 record_alignment (seg, 4);
11243 demand_empty_rest_of_line ();
11248 as_bad (_("Global pointers not supported; recompile -G 0"));
11249 demand_empty_rest_of_line ();
11258 s_change_section (ignore)
11259 int ignore ATTRIBUTE_UNUSED;
11261 expressionS rep_exp;
11263 char *section_name;
11269 int section_entry_size;
11270 int section_alignment;
11274 section_name = input_line_pointer;
11275 c = get_symbol_end ();
11276 next_c = input_line_pointer + 1;
11277 /* just after name is now '\0' */
11278 p = input_line_pointer;
11280 /* Do we have .section Name<,"flags"> */
11281 if (c == '\n' || (c == ',' && *next_c == '"') || c == '"')
11284 input_line_pointer = section_name;
11285 obj_elf_section (ignore);
11288 input_line_pointer++;
11290 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11292 section_type = get_absolute_expression ();
11295 if (*input_line_pointer++ == ',')
11296 section_flag = get_absolute_expression ();
11299 if (*input_line_pointer++ == ',')
11300 section_entry_size = get_absolute_expression ();
11302 section_entry_size = 0;
11303 if (*input_line_pointer++ == ',')
11304 section_alignment = get_absolute_expression ();
11306 section_alignment = 0;
11308 obj_elf_change_section (section_name, section_type, section_flag,
11309 section_entry_size, 0, 0, 0);
11313 mips_enable_auto_align ()
11324 label = insn_labels != NULL ? insn_labels->label : NULL;
11325 mips_emit_delays (false);
11326 if (log_size > 0 && auto_align)
11327 mips_align (log_size, 0, label);
11328 mips_clear_insn_labels ();
11329 cons (1 << log_size);
11333 s_float_cons (type)
11338 label = insn_labels != NULL ? insn_labels->label : NULL;
11340 mips_emit_delays (false);
11345 mips_align (3, 0, label);
11347 mips_align (2, 0, label);
11350 mips_clear_insn_labels ();
11355 /* Handle .globl. We need to override it because on Irix 5 you are
11358 where foo is an undefined symbol, to mean that foo should be
11359 considered to be the address of a function. */
11363 int x ATTRIBUTE_UNUSED;
11370 name = input_line_pointer;
11371 c = get_symbol_end ();
11372 symbolP = symbol_find_or_make (name);
11373 *input_line_pointer = c;
11374 SKIP_WHITESPACE ();
11376 /* On Irix 5, every global symbol that is not explicitly labelled as
11377 being a function is apparently labelled as being an object. */
11380 if (! is_end_of_line[(unsigned char) *input_line_pointer])
11385 secname = input_line_pointer;
11386 c = get_symbol_end ();
11387 sec = bfd_get_section_by_name (stdoutput, secname);
11389 as_bad (_("%s: no such section"), secname);
11390 *input_line_pointer = c;
11392 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
11393 flag = BSF_FUNCTION;
11396 symbol_get_bfdsym (symbolP)->flags |= flag;
11398 S_SET_EXTERNAL (symbolP);
11399 demand_empty_rest_of_line ();
11404 int x ATTRIBUTE_UNUSED;
11409 opt = input_line_pointer;
11410 c = get_symbol_end ();
11414 /* FIXME: What does this mean? */
11416 else if (strncmp (opt, "pic", 3) == 0)
11420 i = atoi (opt + 3);
11424 mips_pic = SVR4_PIC;
11426 as_bad (_(".option pic%d not supported"), i);
11428 if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC)
11430 if (g_switch_seen && g_switch_value != 0)
11431 as_warn (_("-G may not be used with SVR4 PIC code"));
11432 g_switch_value = 0;
11433 bfd_set_gp_size (stdoutput, 0);
11437 as_warn (_("Unrecognized option \"%s\""), opt);
11439 *input_line_pointer = c;
11440 demand_empty_rest_of_line ();
11443 /* This structure is used to hold a stack of .set values. */
11445 struct mips_option_stack
11447 struct mips_option_stack *next;
11448 struct mips_set_options options;
11451 static struct mips_option_stack *mips_opts_stack;
11453 /* Handle the .set pseudo-op. */
11457 int x ATTRIBUTE_UNUSED;
11459 char *name = input_line_pointer, ch;
11461 while (!is_end_of_line[(unsigned char) *input_line_pointer])
11462 ++input_line_pointer;
11463 ch = *input_line_pointer;
11464 *input_line_pointer = '\0';
11466 if (strcmp (name, "reorder") == 0)
11468 if (mips_opts.noreorder && prev_nop_frag != NULL)
11470 /* If we still have pending nops, we can discard them. The
11471 usual nop handling will insert any that are still
11473 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11474 * (mips_opts.mips16 ? 2 : 4));
11475 prev_nop_frag = NULL;
11477 mips_opts.noreorder = 0;
11479 else if (strcmp (name, "noreorder") == 0)
11481 mips_emit_delays (true);
11482 mips_opts.noreorder = 1;
11483 mips_any_noreorder = 1;
11485 else if (strcmp (name, "at") == 0)
11487 mips_opts.noat = 0;
11489 else if (strcmp (name, "noat") == 0)
11491 mips_opts.noat = 1;
11493 else if (strcmp (name, "macro") == 0)
11495 mips_opts.warn_about_macros = 0;
11497 else if (strcmp (name, "nomacro") == 0)
11499 if (mips_opts.noreorder == 0)
11500 as_bad (_("`noreorder' must be set before `nomacro'"));
11501 mips_opts.warn_about_macros = 1;
11503 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
11505 mips_opts.nomove = 0;
11507 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
11509 mips_opts.nomove = 1;
11511 else if (strcmp (name, "bopt") == 0)
11513 mips_opts.nobopt = 0;
11515 else if (strcmp (name, "nobopt") == 0)
11517 mips_opts.nobopt = 1;
11519 else if (strcmp (name, "mips16") == 0
11520 || strcmp (name, "MIPS-16") == 0)
11521 mips_opts.mips16 = 1;
11522 else if (strcmp (name, "nomips16") == 0
11523 || strcmp (name, "noMIPS-16") == 0)
11524 mips_opts.mips16 = 0;
11525 else if (strcmp (name, "mips3d") == 0)
11526 mips_opts.ase_mips3d = 1;
11527 else if (strcmp (name, "nomips3d") == 0)
11528 mips_opts.ase_mips3d = 0;
11529 else if (strcmp (name, "mdmx") == 0)
11530 mips_opts.ase_mdmx = 1;
11531 else if (strcmp (name, "nomdmx") == 0)
11532 mips_opts.ase_mdmx = 0;
11533 else if (strncmp (name, "mips", 4) == 0)
11537 /* Permit the user to change the ISA on the fly. Needless to
11538 say, misuse can cause serious problems. */
11539 isa = atoi (name + 4);
11543 mips_opts.gp32 = file_mips_gp32;
11544 mips_opts.fp32 = file_mips_fp32;
11549 mips_opts.gp32 = 1;
11550 mips_opts.fp32 = 1;
11556 mips_opts.gp32 = 0;
11557 mips_opts.fp32 = 0;
11560 as_bad (_("unknown ISA level %s"), name + 4);
11566 case 0: mips_opts.isa = file_mips_isa; break;
11567 case 1: mips_opts.isa = ISA_MIPS1; break;
11568 case 2: mips_opts.isa = ISA_MIPS2; break;
11569 case 3: mips_opts.isa = ISA_MIPS3; break;
11570 case 4: mips_opts.isa = ISA_MIPS4; break;
11571 case 5: mips_opts.isa = ISA_MIPS5; break;
11572 case 32: mips_opts.isa = ISA_MIPS32; break;
11573 case 64: mips_opts.isa = ISA_MIPS64; break;
11574 default: as_bad (_("unknown ISA level %s"), name + 4); break;
11577 else if (strcmp (name, "autoextend") == 0)
11578 mips_opts.noautoextend = 0;
11579 else if (strcmp (name, "noautoextend") == 0)
11580 mips_opts.noautoextend = 1;
11581 else if (strcmp (name, "push") == 0)
11583 struct mips_option_stack *s;
11585 s = (struct mips_option_stack *) xmalloc (sizeof *s);
11586 s->next = mips_opts_stack;
11587 s->options = mips_opts;
11588 mips_opts_stack = s;
11590 else if (strcmp (name, "pop") == 0)
11592 struct mips_option_stack *s;
11594 s = mips_opts_stack;
11596 as_bad (_(".set pop with no .set push"));
11599 /* If we're changing the reorder mode we need to handle
11600 delay slots correctly. */
11601 if (s->options.noreorder && ! mips_opts.noreorder)
11602 mips_emit_delays (true);
11603 else if (! s->options.noreorder && mips_opts.noreorder)
11605 if (prev_nop_frag != NULL)
11607 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11608 * (mips_opts.mips16 ? 2 : 4));
11609 prev_nop_frag = NULL;
11613 mips_opts = s->options;
11614 mips_opts_stack = s->next;
11620 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
11622 *input_line_pointer = ch;
11623 demand_empty_rest_of_line ();
11626 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11627 .option pic2. It means to generate SVR4 PIC calls. */
11630 s_abicalls (ignore)
11631 int ignore ATTRIBUTE_UNUSED;
11633 mips_pic = SVR4_PIC;
11634 if (USE_GLOBAL_POINTER_OPT)
11636 if (g_switch_seen && g_switch_value != 0)
11637 as_warn (_("-G may not be used with SVR4 PIC code"));
11638 g_switch_value = 0;
11640 bfd_set_gp_size (stdoutput, 0);
11641 demand_empty_rest_of_line ();
11644 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11645 PIC code. It sets the $gp register for the function based on the
11646 function address, which is in the register named in the argument.
11647 This uses a relocation against _gp_disp, which is handled specially
11648 by the linker. The result is:
11649 lui $gp,%hi(_gp_disp)
11650 addiu $gp,$gp,%lo(_gp_disp)
11651 addu $gp,$gp,.cpload argument
11652 The .cpload argument is normally $25 == $t9. */
11656 int ignore ATTRIBUTE_UNUSED;
11661 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11662 .cpload is ignored. */
11663 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
11669 /* .cpload should be in a .set noreorder section. */
11670 if (mips_opts.noreorder == 0)
11671 as_warn (_(".cpload not in noreorder section"));
11673 ex.X_op = O_symbol;
11674 ex.X_add_symbol = symbol_find_or_make ("_gp_disp");
11675 ex.X_op_symbol = NULL;
11676 ex.X_add_number = 0;
11678 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11679 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
11681 macro_build_lui (NULL, &icnt, &ex, mips_gp_register);
11682 macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j",
11683 mips_gp_register, mips_gp_register, (int) BFD_RELOC_LO16);
11685 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t",
11686 mips_gp_register, mips_gp_register, tc_get_register (0));
11688 demand_empty_rest_of_line ();
11691 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11692 .cpsetup $reg1, offset|$reg2, label
11694 If offset is given, this results in:
11695 sd $gp, offset($sp)
11696 lui $gp, %hi(%neg(%gp_rel(label)))
11697 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11698 daddu $gp, $gp, $reg1
11700 If $reg2 is given, this results in:
11701 daddu $reg2, $gp, $0
11702 lui $gp, %hi(%neg(%gp_rel(label)))
11703 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11704 daddu $gp, $gp, $reg1
11705 $reg1 is normally $25 == $t9. */
11708 int ignore ATTRIBUTE_UNUSED;
11710 expressionS ex_off;
11711 expressionS ex_sym;
11716 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
11717 We also need NewABI support. */
11718 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11724 reg1 = tc_get_register (0);
11725 SKIP_WHITESPACE ();
11726 if (*input_line_pointer != ',')
11728 as_bad (_("missing argument separator ',' for .cpsetup"));
11732 ++input_line_pointer;
11733 SKIP_WHITESPACE ();
11734 if (*input_line_pointer == '$')
11736 mips_cpreturn_register = tc_get_register (0);
11737 mips_cpreturn_offset = -1;
11741 mips_cpreturn_offset = get_absolute_expression ();
11742 mips_cpreturn_register = -1;
11744 SKIP_WHITESPACE ();
11745 if (*input_line_pointer != ',')
11747 as_bad (_("missing argument separator ',' for .cpsetup"));
11751 ++input_line_pointer;
11752 SKIP_WHITESPACE ();
11753 expression (&ex_sym);
11755 if (mips_cpreturn_register == -1)
11757 ex_off.X_op = O_constant;
11758 ex_off.X_add_symbol = NULL;
11759 ex_off.X_op_symbol = NULL;
11760 ex_off.X_add_number = mips_cpreturn_offset;
11762 macro_build ((char *) NULL, &icnt, &ex_off, "sd", "t,o(b)",
11763 mips_gp_register, (int) BFD_RELOC_LO16, SP);
11766 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu",
11767 "d,v,t", mips_cpreturn_register, mips_gp_register, 0);
11769 /* Ensure there's room for the next two instructions, so that `f'
11770 doesn't end up with an address in the wrong frag. */
11773 macro_build ((char *) NULL, &icnt, &ex_sym, "lui", "t,u", mips_gp_register,
11774 (int) BFD_RELOC_GPREL16);
11775 fix_new (frag_now, f - frag_now->fr_literal,
11776 0, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
11777 fix_new (frag_now, f - frag_now->fr_literal,
11778 0, NULL, 0, 0, BFD_RELOC_HI16_S);
11781 macro_build ((char *) NULL, &icnt, &ex_sym, "addiu", "t,r,j",
11782 mips_gp_register, mips_gp_register, (int) BFD_RELOC_GPREL16);
11783 fix_new (frag_now, f - frag_now->fr_literal,
11784 0, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
11785 fix_new (frag_now, f - frag_now->fr_literal,
11786 0, NULL, 0, 0, BFD_RELOC_LO16);
11788 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
11789 HAVE_64BIT_ADDRESSES ? "daddu" : "addu", "d,v,t",
11790 mips_gp_register, mips_gp_register, reg1);
11792 demand_empty_rest_of_line ();
11797 int ignore ATTRIBUTE_UNUSED;
11799 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11800 .cplocal is ignored. */
11801 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11807 mips_gp_register = tc_get_register (0);
11808 demand_empty_rest_of_line ();
11811 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11812 offset from $sp. The offset is remembered, and after making a PIC
11813 call $gp is restored from that location. */
11816 s_cprestore (ignore)
11817 int ignore ATTRIBUTE_UNUSED;
11822 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11823 .cprestore is ignored. */
11824 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
11830 mips_cprestore_offset = get_absolute_expression ();
11831 mips_cprestore_valid = 1;
11833 ex.X_op = O_constant;
11834 ex.X_add_symbol = NULL;
11835 ex.X_op_symbol = NULL;
11836 ex.X_add_number = mips_cprestore_offset;
11838 macro_build ((char *) NULL, &icnt, &ex, HAVE_32BIT_ADDRESSES ? "sw" : "sd",
11839 "t,o(b)", mips_gp_register, (int) BFD_RELOC_LO16, SP);
11841 demand_empty_rest_of_line ();
11844 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
11845 was given in the preceeding .gpsetup, it results in:
11846 ld $gp, offset($sp)
11848 If a register $reg2 was given there, it results in:
11849 daddiu $gp, $gp, $reg2
11852 s_cpreturn (ignore)
11853 int ignore ATTRIBUTE_UNUSED;
11858 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
11859 We also need NewABI support. */
11860 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11866 if (mips_cpreturn_register == -1)
11868 ex.X_op = O_constant;
11869 ex.X_add_symbol = NULL;
11870 ex.X_op_symbol = NULL;
11871 ex.X_add_number = mips_cpreturn_offset;
11873 macro_build ((char *) NULL, &icnt, &ex, "ld", "t,o(b)",
11874 mips_gp_register, (int) BFD_RELOC_LO16, SP);
11877 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu",
11878 "d,v,t", mips_gp_register, mips_cpreturn_register, 0);
11880 demand_empty_rest_of_line ();
11883 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
11884 code. It sets the offset to use in gp_rel relocations. */
11888 int ignore ATTRIBUTE_UNUSED;
11890 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
11891 We also need NewABI support. */
11892 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11898 mips_gprel_offset = get_absolute_expression ();
11900 demand_empty_rest_of_line ();
11903 /* Handle the .gpword pseudo-op. This is used when generating PIC
11904 code. It generates a 32 bit GP relative reloc. */
11908 int ignore ATTRIBUTE_UNUSED;
11914 /* When not generating PIC code, this is treated as .word. */
11915 if (mips_pic != SVR4_PIC)
11921 label = insn_labels != NULL ? insn_labels->label : NULL;
11922 mips_emit_delays (true);
11924 mips_align (2, 0, label);
11925 mips_clear_insn_labels ();
11929 if (ex.X_op != O_symbol || ex.X_add_number != 0)
11931 as_bad (_("Unsupported use of .gpword"));
11932 ignore_rest_of_line ();
11936 md_number_to_chars (p, (valueT) 0, 4);
11937 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, false,
11938 BFD_RELOC_GPREL32);
11940 demand_empty_rest_of_line ();
11943 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
11944 tables in SVR4 PIC code. */
11948 int ignore ATTRIBUTE_UNUSED;
11953 /* This is ignored when not generating SVR4 PIC code or if this is NewABI
11955 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
11961 /* Add $gp to the register named as an argument. */
11962 reg = tc_get_register (0);
11963 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
11964 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
11965 "d,v,t", reg, reg, mips_gp_register);
11967 demand_empty_rest_of_line ();
11970 /* Handle the .insn pseudo-op. This marks instruction labels in
11971 mips16 mode. This permits the linker to handle them specially,
11972 such as generating jalx instructions when needed. We also make
11973 them odd for the duration of the assembly, in order to generate the
11974 right sort of code. We will make them even in the adjust_symtab
11975 routine, while leaving them marked. This is convenient for the
11976 debugger and the disassembler. The linker knows to make them odd
11981 int ignore ATTRIBUTE_UNUSED;
11983 mips16_mark_labels ();
11985 demand_empty_rest_of_line ();
11988 /* Handle a .stabn directive. We need these in order to mark a label
11989 as being a mips16 text label correctly. Sometimes the compiler
11990 will emit a label, followed by a .stabn, and then switch sections.
11991 If the label and .stabn are in mips16 mode, then the label is
11992 really a mips16 text label. */
11999 mips16_mark_labels ();
12004 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12008 s_mips_weakext (ignore)
12009 int ignore ATTRIBUTE_UNUSED;
12016 name = input_line_pointer;
12017 c = get_symbol_end ();
12018 symbolP = symbol_find_or_make (name);
12019 S_SET_WEAK (symbolP);
12020 *input_line_pointer = c;
12022 SKIP_WHITESPACE ();
12024 if (! is_end_of_line[(unsigned char) *input_line_pointer])
12026 if (S_IS_DEFINED (symbolP))
12028 as_bad ("ignoring attempt to redefine symbol %s",
12029 S_GET_NAME (symbolP));
12030 ignore_rest_of_line ();
12034 if (*input_line_pointer == ',')
12036 ++input_line_pointer;
12037 SKIP_WHITESPACE ();
12041 if (exp.X_op != O_symbol)
12043 as_bad ("bad .weakext directive");
12044 ignore_rest_of_line ();
12047 symbol_set_value_expression (symbolP, &exp);
12050 demand_empty_rest_of_line ();
12053 /* Parse a register string into a number. Called from the ECOFF code
12054 to parse .frame. The argument is non-zero if this is the frame
12055 register, so that we can record it in mips_frame_reg. */
12058 tc_get_register (frame)
12063 SKIP_WHITESPACE ();
12064 if (*input_line_pointer++ != '$')
12066 as_warn (_("expected `$'"));
12069 else if (ISDIGIT (*input_line_pointer))
12071 reg = get_absolute_expression ();
12072 if (reg < 0 || reg >= 32)
12074 as_warn (_("Bad register number"));
12080 if (strncmp (input_line_pointer, "ra", 2) == 0)
12083 input_line_pointer += 2;
12085 else if (strncmp (input_line_pointer, "fp", 2) == 0)
12088 input_line_pointer += 2;
12090 else if (strncmp (input_line_pointer, "sp", 2) == 0)
12093 input_line_pointer += 2;
12095 else if (strncmp (input_line_pointer, "gp", 2) == 0)
12098 input_line_pointer += 2;
12100 else if (strncmp (input_line_pointer, "at", 2) == 0)
12103 input_line_pointer += 2;
12105 else if (strncmp (input_line_pointer, "kt0", 3) == 0)
12108 input_line_pointer += 3;
12110 else if (strncmp (input_line_pointer, "kt1", 3) == 0)
12113 input_line_pointer += 3;
12115 else if (strncmp (input_line_pointer, "zero", 4) == 0)
12118 input_line_pointer += 4;
12122 as_warn (_("Unrecognized register name"));
12124 while (ISALNUM(*input_line_pointer))
12125 input_line_pointer++;
12130 mips_frame_reg = reg != 0 ? reg : SP;
12131 mips_frame_reg_valid = 1;
12132 mips_cprestore_valid = 0;
12138 md_section_align (seg, addr)
12142 int align = bfd_get_section_alignment (stdoutput, seg);
12145 /* We don't need to align ELF sections to the full alignment.
12146 However, Irix 5 may prefer that we align them at least to a 16
12147 byte boundary. We don't bother to align the sections if we are
12148 targeted for an embedded system. */
12149 if (strcmp (TARGET_OS, "elf") == 0)
12155 return ((addr + (1 << align) - 1) & (-1 << align));
12158 /* Utility routine, called from above as well. If called while the
12159 input file is still being read, it's only an approximation. (For
12160 example, a symbol may later become defined which appeared to be
12161 undefined earlier.) */
12164 nopic_need_relax (sym, before_relaxing)
12166 int before_relaxing;
12171 if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0)
12173 const char *symname;
12176 /* Find out whether this symbol can be referenced off the $gp
12177 register. It can be if it is smaller than the -G size or if
12178 it is in the .sdata or .sbss section. Certain symbols can
12179 not be referenced off the $gp, although it appears as though
12181 symname = S_GET_NAME (sym);
12182 if (symname != (const char *) NULL
12183 && (strcmp (symname, "eprol") == 0
12184 || strcmp (symname, "etext") == 0
12185 || strcmp (symname, "_gp") == 0
12186 || strcmp (symname, "edata") == 0
12187 || strcmp (symname, "_fbss") == 0
12188 || strcmp (symname, "_fdata") == 0
12189 || strcmp (symname, "_ftext") == 0
12190 || strcmp (symname, "end") == 0
12191 || strcmp (symname, "_gp_disp") == 0))
12193 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
12195 #ifndef NO_ECOFF_DEBUGGING
12196 || (symbol_get_obj (sym)->ecoff_extern_size != 0
12197 && (symbol_get_obj (sym)->ecoff_extern_size
12198 <= g_switch_value))
12200 /* We must defer this decision until after the whole
12201 file has been read, since there might be a .extern
12202 after the first use of this symbol. */
12203 || (before_relaxing
12204 #ifndef NO_ECOFF_DEBUGGING
12205 && symbol_get_obj (sym)->ecoff_extern_size == 0
12207 && S_GET_VALUE (sym) == 0)
12208 || (S_GET_VALUE (sym) != 0
12209 && S_GET_VALUE (sym) <= g_switch_value)))
12213 const char *segname;
12215 segname = segment_name (S_GET_SEGMENT (sym));
12216 assert (strcmp (segname, ".lit8") != 0
12217 && strcmp (segname, ".lit4") != 0);
12218 change = (strcmp (segname, ".sdata") != 0
12219 && strcmp (segname, ".sbss") != 0
12220 && strncmp (segname, ".sdata.", 7) != 0
12221 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
12226 /* We are not optimizing for the $gp register. */
12230 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12231 extended opcode. SEC is the section the frag is in. */
12234 mips16_extended_frag (fragp, sec, stretch)
12240 register const struct mips16_immed_operand *op;
12242 int mintiny, maxtiny;
12246 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
12248 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
12251 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
12252 op = mips16_immed_operands;
12253 while (op->type != type)
12256 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
12261 if (type == '<' || type == '>' || type == '[' || type == ']')
12264 maxtiny = 1 << op->nbits;
12269 maxtiny = (1 << op->nbits) - 1;
12274 mintiny = - (1 << (op->nbits - 1));
12275 maxtiny = (1 << (op->nbits - 1)) - 1;
12278 sym_frag = symbol_get_frag (fragp->fr_symbol);
12279 val = S_GET_VALUE (fragp->fr_symbol);
12280 symsec = S_GET_SEGMENT (fragp->fr_symbol);
12286 /* We won't have the section when we are called from
12287 mips_relax_frag. However, we will always have been called
12288 from md_estimate_size_before_relax first. If this is a
12289 branch to a different section, we mark it as such. If SEC is
12290 NULL, and the frag is not marked, then it must be a branch to
12291 the same section. */
12294 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
12299 /* Must have been called from md_estimate_size_before_relax. */
12302 fragp->fr_subtype =
12303 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12305 /* FIXME: We should support this, and let the linker
12306 catch branches and loads that are out of range. */
12307 as_bad_where (fragp->fr_file, fragp->fr_line,
12308 _("unsupported PC relative reference to different section"));
12312 if (fragp != sym_frag && sym_frag->fr_address == 0)
12313 /* Assume non-extended on the first relaxation pass.
12314 The address we have calculated will be bogus if this is
12315 a forward branch to another frag, as the forward frag
12316 will have fr_address == 0. */
12320 /* In this case, we know for sure that the symbol fragment is in
12321 the same section. If the relax_marker of the symbol fragment
12322 differs from the relax_marker of this fragment, we have not
12323 yet adjusted the symbol fragment fr_address. We want to add
12324 in STRETCH in order to get a better estimate of the address.
12325 This particularly matters because of the shift bits. */
12327 && sym_frag->relax_marker != fragp->relax_marker)
12331 /* Adjust stretch for any alignment frag. Note that if have
12332 been expanding the earlier code, the symbol may be
12333 defined in what appears to be an earlier frag. FIXME:
12334 This doesn't handle the fr_subtype field, which specifies
12335 a maximum number of bytes to skip when doing an
12337 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
12339 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
12342 stretch = - ((- stretch)
12343 & ~ ((1 << (int) f->fr_offset) - 1));
12345 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
12354 addr = fragp->fr_address + fragp->fr_fix;
12356 /* The base address rules are complicated. The base address of
12357 a branch is the following instruction. The base address of a
12358 PC relative load or add is the instruction itself, but if it
12359 is in a delay slot (in which case it can not be extended) use
12360 the address of the instruction whose delay slot it is in. */
12361 if (type == 'p' || type == 'q')
12365 /* If we are currently assuming that this frag should be
12366 extended, then, the current address is two bytes
12368 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12371 /* Ignore the low bit in the target, since it will be set
12372 for a text label. */
12373 if ((val & 1) != 0)
12376 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
12378 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
12381 val -= addr & ~ ((1 << op->shift) - 1);
12383 /* Branch offsets have an implicit 0 in the lowest bit. */
12384 if (type == 'p' || type == 'q')
12387 /* If any of the shifted bits are set, we must use an extended
12388 opcode. If the address depends on the size of this
12389 instruction, this can lead to a loop, so we arrange to always
12390 use an extended opcode. We only check this when we are in
12391 the main relaxation loop, when SEC is NULL. */
12392 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
12394 fragp->fr_subtype =
12395 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12399 /* If we are about to mark a frag as extended because the value
12400 is precisely maxtiny + 1, then there is a chance of an
12401 infinite loop as in the following code:
12406 In this case when the la is extended, foo is 0x3fc bytes
12407 away, so the la can be shrunk, but then foo is 0x400 away, so
12408 the la must be extended. To avoid this loop, we mark the
12409 frag as extended if it was small, and is about to become
12410 extended with a value of maxtiny + 1. */
12411 if (val == ((maxtiny + 1) << op->shift)
12412 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
12415 fragp->fr_subtype =
12416 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12420 else if (symsec != absolute_section && sec != NULL)
12421 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
12423 if ((val & ((1 << op->shift) - 1)) != 0
12424 || val < (mintiny << op->shift)
12425 || val > (maxtiny << op->shift))
12431 /* Estimate the size of a frag before relaxing. Unless this is the
12432 mips16, we are not really relaxing here, and the final size is
12433 encoded in the subtype information. For the mips16, we have to
12434 decide whether we are using an extended opcode or not. */
12437 md_estimate_size_before_relax (fragp, segtype)
12442 boolean linkonce = false;
12444 if (RELAX_MIPS16_P (fragp->fr_subtype))
12445 /* We don't want to modify the EXTENDED bit here; it might get us
12446 into infinite loops. We change it only in mips_relax_frag(). */
12447 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
12449 if (mips_pic == NO_PIC)
12451 change = nopic_need_relax (fragp->fr_symbol, 0);
12453 else if (mips_pic == SVR4_PIC)
12458 sym = fragp->fr_symbol;
12460 /* Handle the case of a symbol equated to another symbol. */
12461 while (symbol_equated_reloc_p (sym))
12465 /* It's possible to get a loop here in a badly written
12467 n = symbol_get_value_expression (sym)->X_add_symbol;
12473 symsec = S_GET_SEGMENT (sym);
12475 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12476 if (symsec != segtype && ! S_IS_LOCAL (sym))
12478 if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE)
12482 /* The GNU toolchain uses an extension for ELF: a section
12483 beginning with the magic string .gnu.linkonce is a linkonce
12485 if (strncmp (segment_name (symsec), ".gnu.linkonce",
12486 sizeof ".gnu.linkonce" - 1) == 0)
12490 /* This must duplicate the test in adjust_reloc_syms. */
12491 change = (symsec != &bfd_und_section
12492 && symsec != &bfd_abs_section
12493 && ! bfd_is_com_section (symsec)
12496 /* A global or weak symbol is treated as external. */
12497 && (OUTPUT_FLAVOR != bfd_target_elf_flavour
12498 || (! S_IS_WEAK (sym)
12499 && (! S_IS_EXTERNAL (sym)
12500 || mips_pic == EMBEDDED_PIC)))
12509 /* Record the offset to the first reloc in the fr_opcode field.
12510 This lets md_convert_frag and tc_gen_reloc know that the code
12511 must be expanded. */
12512 fragp->fr_opcode = (fragp->fr_literal
12514 - RELAX_OLD (fragp->fr_subtype)
12515 + RELAX_RELOC1 (fragp->fr_subtype));
12516 /* FIXME: This really needs as_warn_where. */
12517 if (RELAX_WARN (fragp->fr_subtype))
12518 as_warn (_("AT used after \".set noat\" or macro used after "
12519 "\".set nomacro\""));
12521 return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype);
12527 /* This is called to see whether a reloc against a defined symbol
12528 should be converted into a reloc against a section. Don't adjust
12529 MIPS16 jump relocations, so we don't have to worry about the format
12530 of the offset in the .o file. Don't adjust relocations against
12531 mips16 symbols, so that the linker can find them if it needs to set
12535 mips_fix_adjustable (fixp)
12538 if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
12541 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12542 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12545 if (fixp->fx_addsy == NULL)
12549 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
12550 && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
12551 && fixp->fx_subsy == NULL)
12558 /* Translate internal representation of relocation info to BFD target
12562 tc_gen_reloc (section, fixp)
12563 asection *section ATTRIBUTE_UNUSED;
12566 static arelent *retval[4];
12568 bfd_reloc_code_real_type code;
12570 reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent));
12573 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
12574 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
12575 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
12577 if (mips_pic == EMBEDDED_PIC
12578 && SWITCH_TABLE (fixp))
12580 /* For a switch table entry we use a special reloc. The addend
12581 is actually the difference between the reloc address and the
12583 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
12584 if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour)
12585 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
12586 fixp->fx_r_type = BFD_RELOC_GPREL32;
12588 else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16)
12590 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
12591 reloc->addend = fixp->fx_addnumber;
12594 /* We use a special addend for an internal RELLO reloc. */
12595 if (symbol_section_p (fixp->fx_addsy))
12596 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
12598 reloc->addend = fixp->fx_addnumber + reloc->address;
12601 else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
12603 assert (fixp->fx_next != NULL
12604 && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16);
12606 /* The reloc is relative to the RELLO; adjust the addend
12608 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
12609 reloc->addend = fixp->fx_next->fx_addnumber;
12612 /* We use a special addend for an internal RELHI reloc. */
12613 if (symbol_section_p (fixp->fx_addsy))
12614 reloc->addend = (fixp->fx_next->fx_frag->fr_address
12615 + fixp->fx_next->fx_where
12616 - S_GET_VALUE (fixp->fx_subsy));
12618 reloc->addend = (fixp->fx_addnumber
12619 + fixp->fx_next->fx_frag->fr_address
12620 + fixp->fx_next->fx_where);
12623 else if (fixp->fx_pcrel == 0 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
12624 reloc->addend = fixp->fx_addnumber;
12627 if (OUTPUT_FLAVOR != bfd_target_aout_flavour)
12628 /* A gruesome hack which is a result of the gruesome gas reloc
12630 reloc->addend = reloc->address;
12632 reloc->addend = -reloc->address;
12635 /* If this is a variant frag, we may need to adjust the existing
12636 reloc and generate a new one. */
12637 if (fixp->fx_frag->fr_opcode != NULL
12638 && (fixp->fx_r_type == BFD_RELOC_GPREL16
12639 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
12640 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16
12641 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
12642 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16
12643 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
12644 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)
12649 assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype));
12651 /* If this is not the last reloc in this frag, then we have two
12652 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
12653 CALL_HI16/CALL_LO16, both of which are being replaced. Let
12654 the second one handle all of them. */
12655 if (fixp->fx_next != NULL
12656 && fixp->fx_frag == fixp->fx_next->fx_frag)
12658 assert ((fixp->fx_r_type == BFD_RELOC_GPREL16
12659 && fixp->fx_next->fx_r_type == BFD_RELOC_GPREL16)
12660 || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
12661 && (fixp->fx_next->fx_r_type
12662 == BFD_RELOC_MIPS_GOT_LO16))
12663 || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
12664 && (fixp->fx_next->fx_r_type
12665 == BFD_RELOC_MIPS_CALL_LO16)));
12670 fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal;
12671 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
12672 reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent));
12674 reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
12675 *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
12676 reloc2->address = (reloc->address
12677 + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype)
12678 - RELAX_RELOC1 (fixp->fx_frag->fr_subtype)));
12679 reloc2->addend = fixp->fx_addnumber;
12680 reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16);
12681 assert (reloc2->howto != NULL);
12683 if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype))
12687 reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent));
12690 reloc3->address += 4;
12693 if (mips_pic == NO_PIC)
12695 assert (fixp->fx_r_type == BFD_RELOC_GPREL16);
12696 fixp->fx_r_type = BFD_RELOC_HI16_S;
12698 else if (mips_pic == SVR4_PIC)
12700 switch (fixp->fx_r_type)
12704 case BFD_RELOC_MIPS_GOT16:
12706 case BFD_RELOC_MIPS_CALL16:
12707 case BFD_RELOC_MIPS_GOT_LO16:
12708 case BFD_RELOC_MIPS_CALL_LO16:
12709 fixp->fx_r_type = BFD_RELOC_MIPS_GOT16;
12717 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
12718 entry to be used in the relocation's section offset. */
12719 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12721 reloc->address = reloc->addend;
12725 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
12726 fixup_segment converted a non-PC relative reloc into a PC
12727 relative reloc. In such a case, we need to convert the reloc
12729 code = fixp->fx_r_type;
12730 if (fixp->fx_pcrel)
12735 code = BFD_RELOC_8_PCREL;
12738 code = BFD_RELOC_16_PCREL;
12741 code = BFD_RELOC_32_PCREL;
12744 code = BFD_RELOC_64_PCREL;
12746 case BFD_RELOC_8_PCREL:
12747 case BFD_RELOC_16_PCREL:
12748 case BFD_RELOC_32_PCREL:
12749 case BFD_RELOC_64_PCREL:
12750 case BFD_RELOC_16_PCREL_S2:
12751 case BFD_RELOC_PCREL_HI16_S:
12752 case BFD_RELOC_PCREL_LO16:
12755 as_bad_where (fixp->fx_file, fixp->fx_line,
12756 _("Cannot make %s relocation PC relative"),
12757 bfd_get_reloc_code_name (code));
12762 /* md_apply_fix3 has a double-subtraction hack to get
12763 bfd_install_relocation to behave nicely. GPREL relocations are
12764 handled correctly without this hack, so undo it here. We can't
12765 stop md_apply_fix3 from subtracting twice in the first place since
12766 the fake addend is required for variant frags above. */
12767 if (fixp->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour
12768 && (code == BFD_RELOC_GPREL16 || code == BFD_RELOC_MIPS16_GPREL)
12769 && reloc->addend != 0
12770 && mips_need_elf_addend_fixup (fixp))
12771 reloc->addend += S_GET_VALUE (fixp->fx_addsy);
12774 /* To support a PC relative reloc when generating embedded PIC code
12775 for ECOFF, we use a Cygnus extension. We check for that here to
12776 make sure that we don't let such a reloc escape normally. */
12777 if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
12778 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
12779 && code == BFD_RELOC_16_PCREL_S2
12780 && mips_pic != EMBEDDED_PIC)
12781 reloc->howto = NULL;
12783 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
12785 if (reloc->howto == NULL)
12787 as_bad_where (fixp->fx_file, fixp->fx_line,
12788 _("Can not represent %s relocation in this object file format"),
12789 bfd_get_reloc_code_name (code));
12796 /* Relax a machine dependent frag. This returns the amount by which
12797 the current size of the frag should change. */
12800 mips_relax_frag (fragp, stretch)
12804 if (! RELAX_MIPS16_P (fragp->fr_subtype))
12807 if (mips16_extended_frag (fragp, NULL, stretch))
12809 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12811 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
12816 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12818 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
12825 /* Convert a machine dependent frag. */
12828 md_convert_frag (abfd, asec, fragp)
12829 bfd *abfd ATTRIBUTE_UNUSED;
12836 if (RELAX_MIPS16_P (fragp->fr_subtype))
12839 register const struct mips16_immed_operand *op;
12840 boolean small, ext;
12843 unsigned long insn;
12844 boolean use_extend;
12845 unsigned short extend;
12847 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
12848 op = mips16_immed_operands;
12849 while (op->type != type)
12852 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12863 resolve_symbol_value (fragp->fr_symbol);
12864 val = S_GET_VALUE (fragp->fr_symbol);
12869 addr = fragp->fr_address + fragp->fr_fix;
12871 /* The rules for the base address of a PC relative reloc are
12872 complicated; see mips16_extended_frag. */
12873 if (type == 'p' || type == 'q')
12878 /* Ignore the low bit in the target, since it will be
12879 set for a text label. */
12880 if ((val & 1) != 0)
12883 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
12885 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
12888 addr &= ~ (addressT) ((1 << op->shift) - 1);
12891 /* Make sure the section winds up with the alignment we have
12894 record_alignment (asec, op->shift);
12898 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
12899 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
12900 as_warn_where (fragp->fr_file, fragp->fr_line,
12901 _("extended instruction in delay slot"));
12903 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
12905 if (target_big_endian)
12906 insn = bfd_getb16 (buf);
12908 insn = bfd_getl16 (buf);
12910 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
12911 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
12912 small, ext, &insn, &use_extend, &extend);
12916 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
12917 fragp->fr_fix += 2;
12921 md_number_to_chars ((char *) buf, insn, 2);
12922 fragp->fr_fix += 2;
12927 if (fragp->fr_opcode == NULL)
12930 old = RELAX_OLD (fragp->fr_subtype);
12931 new = RELAX_NEW (fragp->fr_subtype);
12932 fixptr = fragp->fr_literal + fragp->fr_fix;
12935 memcpy (fixptr - old, fixptr, new);
12937 fragp->fr_fix += new - old;
12943 /* This function is called after the relocs have been generated.
12944 We've been storing mips16 text labels as odd. Here we convert them
12945 back to even for the convenience of the debugger. */
12948 mips_frob_file_after_relocs ()
12951 unsigned int count, i;
12953 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
12956 syms = bfd_get_outsymbols (stdoutput);
12957 count = bfd_get_symcount (stdoutput);
12958 for (i = 0; i < count; i++, syms++)
12960 if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16
12961 && ((*syms)->value & 1) != 0)
12963 (*syms)->value &= ~1;
12964 /* If the symbol has an odd size, it was probably computed
12965 incorrectly, so adjust that as well. */
12966 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
12967 ++elf_symbol (*syms)->internal_elf_sym.st_size;
12974 /* This function is called whenever a label is defined. It is used
12975 when handling branch delays; if a branch has a label, we assume we
12976 can not move it. */
12979 mips_define_label (sym)
12982 struct insn_label_list *l;
12984 if (free_insn_labels == NULL)
12985 l = (struct insn_label_list *) xmalloc (sizeof *l);
12988 l = free_insn_labels;
12989 free_insn_labels = l->next;
12993 l->next = insn_labels;
12997 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12999 /* Some special processing for a MIPS ELF file. */
13002 mips_elf_final_processing ()
13004 /* Write out the register information. */
13005 if (mips_abi != N64_ABI)
13009 s.ri_gprmask = mips_gprmask;
13010 s.ri_cprmask[0] = mips_cprmask[0];
13011 s.ri_cprmask[1] = mips_cprmask[1];
13012 s.ri_cprmask[2] = mips_cprmask[2];
13013 s.ri_cprmask[3] = mips_cprmask[3];
13014 /* The gp_value field is set by the MIPS ELF backend. */
13016 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
13017 ((Elf32_External_RegInfo *)
13018 mips_regmask_frag));
13022 Elf64_Internal_RegInfo s;
13024 s.ri_gprmask = mips_gprmask;
13026 s.ri_cprmask[0] = mips_cprmask[0];
13027 s.ri_cprmask[1] = mips_cprmask[1];
13028 s.ri_cprmask[2] = mips_cprmask[2];
13029 s.ri_cprmask[3] = mips_cprmask[3];
13030 /* The gp_value field is set by the MIPS ELF backend. */
13032 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
13033 ((Elf64_External_RegInfo *)
13034 mips_regmask_frag));
13037 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13038 sort of BFD interface for this. */
13039 if (mips_any_noreorder)
13040 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
13041 if (mips_pic != NO_PIC)
13042 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
13044 /* Set MIPS ELF flags for ASEs. */
13045 if (file_ase_mips16)
13046 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
13047 #if 0 /* XXX FIXME */
13048 if (file_ase_mips3d)
13049 elf_elfheader (stdoutput)->e_flags |= ???;
13052 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
13054 /* Set the MIPS ELF ABI flags. */
13055 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
13056 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
13057 else if (mips_abi == O64_ABI)
13058 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
13059 else if (mips_abi == EABI_ABI)
13061 if (!file_mips_gp32)
13062 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
13064 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
13066 else if (mips_abi == N32_ABI)
13067 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
13069 /* Nothing to do for N64_ABI. */
13071 if (mips_32bitmode)
13072 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
13075 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13077 typedef struct proc {
13079 unsigned long reg_mask;
13080 unsigned long reg_offset;
13081 unsigned long fpreg_mask;
13082 unsigned long fpreg_offset;
13083 unsigned long frame_offset;
13084 unsigned long frame_reg;
13085 unsigned long pc_reg;
13088 static procS cur_proc;
13089 static procS *cur_proc_ptr;
13090 static int numprocs;
13092 /* Fill in an rs_align_code fragment. */
13095 mips_handle_align (fragp)
13098 if (fragp->fr_type != rs_align_code)
13101 if (mips_opts.mips16)
13103 static const unsigned char be_nop[] = { 0x65, 0x00 };
13104 static const unsigned char le_nop[] = { 0x00, 0x65 };
13109 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
13110 p = fragp->fr_literal + fragp->fr_fix;
13118 memcpy (p, (target_big_endian ? be_nop : le_nop), 2);
13122 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13133 /* check for premature end, nesting errors, etc */
13135 as_warn (_("missing .end at end of assembly"));
13144 if (*input_line_pointer == '-')
13146 ++input_line_pointer;
13149 if (!ISDIGIT (*input_line_pointer))
13150 as_bad (_("expected simple number"));
13151 if (input_line_pointer[0] == '0')
13153 if (input_line_pointer[1] == 'x')
13155 input_line_pointer += 2;
13156 while (ISXDIGIT (*input_line_pointer))
13159 val |= hex_value (*input_line_pointer++);
13161 return negative ? -val : val;
13165 ++input_line_pointer;
13166 while (ISDIGIT (*input_line_pointer))
13169 val |= *input_line_pointer++ - '0';
13171 return negative ? -val : val;
13174 if (!ISDIGIT (*input_line_pointer))
13176 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13177 *input_line_pointer, *input_line_pointer);
13178 as_warn (_("invalid number"));
13181 while (ISDIGIT (*input_line_pointer))
13184 val += *input_line_pointer++ - '0';
13186 return negative ? -val : val;
13189 /* The .file directive; just like the usual .file directive, but there
13190 is an initial number which is the ECOFF file index. In the non-ECOFF
13191 case .file implies DWARF-2. */
13195 int x ATTRIBUTE_UNUSED;
13197 static int first_file_directive = 0;
13199 if (ECOFF_DEBUGGING)
13208 filename = dwarf2_directive_file (0);
13210 /* Versions of GCC up to 3.1 start files with a ".file"
13211 directive even for stabs output. Make sure that this
13212 ".file" is handled. Note that you need a version of GCC
13213 after 3.1 in order to support DWARF-2 on MIPS. */
13214 if (filename != NULL && ! first_file_directive)
13216 (void) new_logical_line (filename, -1);
13217 s_app_file_string (filename);
13219 first_file_directive = 1;
13223 /* The .loc directive, implying DWARF-2. */
13227 int x ATTRIBUTE_UNUSED;
13229 if (!ECOFF_DEBUGGING)
13230 dwarf2_directive_loc (0);
13233 /* The .end directive. */
13237 int x ATTRIBUTE_UNUSED;
13242 /* Following functions need their own .frame and .cprestore directives. */
13243 mips_frame_reg_valid = 0;
13244 mips_cprestore_valid = 0;
13246 if (!is_end_of_line[(unsigned char) *input_line_pointer])
13249 demand_empty_rest_of_line ();
13254 #ifdef BFD_ASSEMBLER
13255 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
13260 if (now_seg != data_section && now_seg != bss_section)
13267 as_warn (_(".end not in text section"));
13271 as_warn (_(".end directive without a preceding .ent directive."));
13272 demand_empty_rest_of_line ();
13278 assert (S_GET_NAME (p));
13279 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym)))
13280 as_warn (_(".end symbol does not match .ent symbol."));
13282 if (debug_type == DEBUG_STABS)
13283 stabs_generate_asm_endfunc (S_GET_NAME (p),
13287 as_warn (_(".end directive missing or unknown symbol"));
13290 /* Generate a .pdr section. */
13291 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
13293 segT saved_seg = now_seg;
13294 subsegT saved_subseg = now_subseg;
13299 dot = frag_now_fix ();
13301 #ifdef md_flush_pending_output
13302 md_flush_pending_output ();
13306 subseg_set (pdr_seg, 0);
13308 /* Write the symbol. */
13309 exp.X_op = O_symbol;
13310 exp.X_add_symbol = p;
13311 exp.X_add_number = 0;
13312 emit_expr (&exp, 4);
13314 fragp = frag_more (7 * 4);
13316 md_number_to_chars (fragp, (valueT) cur_proc_ptr->reg_mask, 4);
13317 md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4);
13318 md_number_to_chars (fragp + 8, (valueT) cur_proc_ptr->fpreg_mask, 4);
13319 md_number_to_chars (fragp + 12, (valueT) cur_proc_ptr->fpreg_offset, 4);
13320 md_number_to_chars (fragp + 16, (valueT) cur_proc_ptr->frame_offset, 4);
13321 md_number_to_chars (fragp + 20, (valueT) cur_proc_ptr->frame_reg, 4);
13322 md_number_to_chars (fragp + 24, (valueT) cur_proc_ptr->pc_reg, 4);
13324 subseg_set (saved_seg, saved_subseg);
13326 #endif /* OBJ_ELF */
13328 cur_proc_ptr = NULL;
13331 /* The .aent and .ent directives. */
13340 symbolP = get_symbol ();
13341 if (*input_line_pointer == ',')
13342 ++input_line_pointer;
13343 SKIP_WHITESPACE ();
13344 if (ISDIGIT (*input_line_pointer)
13345 || *input_line_pointer == '-')
13348 #ifdef BFD_ASSEMBLER
13349 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
13354 if (now_seg != data_section && now_seg != bss_section)
13361 as_warn (_(".ent or .aent not in text section."));
13363 if (!aent && cur_proc_ptr)
13364 as_warn (_("missing .end"));
13368 /* This function needs its own .frame and .cprestore directives. */
13369 mips_frame_reg_valid = 0;
13370 mips_cprestore_valid = 0;
13372 cur_proc_ptr = &cur_proc;
13373 memset (cur_proc_ptr, '\0', sizeof (procS));
13375 cur_proc_ptr->isym = symbolP;
13377 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
13381 if (debug_type == DEBUG_STABS)
13382 stabs_generate_asm_func (S_GET_NAME (symbolP),
13383 S_GET_NAME (symbolP));
13386 demand_empty_rest_of_line ();
13389 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13390 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13391 s_mips_frame is used so that we can set the PDR information correctly.
13392 We can't use the ecoff routines because they make reference to the ecoff
13393 symbol table (in the mdebug section). */
13396 s_mips_frame (ignore)
13397 int ignore ATTRIBUTE_UNUSED;
13400 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
13404 if (cur_proc_ptr == (procS *) NULL)
13406 as_warn (_(".frame outside of .ent"));
13407 demand_empty_rest_of_line ();
13411 cur_proc_ptr->frame_reg = tc_get_register (1);
13413 SKIP_WHITESPACE ();
13414 if (*input_line_pointer++ != ','
13415 || get_absolute_expression_and_terminator (&val) != ',')
13417 as_warn (_("Bad .frame directive"));
13418 --input_line_pointer;
13419 demand_empty_rest_of_line ();
13423 cur_proc_ptr->frame_offset = val;
13424 cur_proc_ptr->pc_reg = tc_get_register (0);
13426 demand_empty_rest_of_line ();
13429 #endif /* OBJ_ELF */
13433 /* The .fmask and .mask directives. If the mdebug section is present
13434 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13435 embedded targets, s_mips_mask is used so that we can set the PDR
13436 information correctly. We can't use the ecoff routines because they
13437 make reference to the ecoff symbol table (in the mdebug section). */
13440 s_mips_mask (reg_type)
13444 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
13448 if (cur_proc_ptr == (procS *) NULL)
13450 as_warn (_(".mask/.fmask outside of .ent"));
13451 demand_empty_rest_of_line ();
13455 if (get_absolute_expression_and_terminator (&mask) != ',')
13457 as_warn (_("Bad .mask/.fmask directive"));
13458 --input_line_pointer;
13459 demand_empty_rest_of_line ();
13463 off = get_absolute_expression ();
13465 if (reg_type == 'F')
13467 cur_proc_ptr->fpreg_mask = mask;
13468 cur_proc_ptr->fpreg_offset = off;
13472 cur_proc_ptr->reg_mask = mask;
13473 cur_proc_ptr->reg_offset = off;
13476 demand_empty_rest_of_line ();
13479 #endif /* OBJ_ELF */
13480 s_ignore (reg_type);
13483 /* The .loc directive. */
13494 assert (now_seg == text_section);
13496 lineno = get_number ();
13497 addroff = frag_now_fix ();
13499 symbolP = symbol_new ("", N_SLINE, addroff, frag_now);
13500 S_SET_TYPE (symbolP, N_SLINE);
13501 S_SET_OTHER (symbolP, 0);
13502 S_SET_DESC (symbolP, lineno);
13503 symbolP->sy_segment = now_seg;
13507 /* A table describing all the processors gas knows about. Names are
13508 matched in the order listed.
13510 To ease comparison, please keep this table in the same order as
13511 gcc's mips_cpu_info_table[]. */
13512 static const struct mips_cpu_info mips_cpu_info_table[] =
13514 /* Entries for generic ISAs */
13515 { "mips1", 1, ISA_MIPS1, CPU_R3000 },
13516 { "mips2", 1, ISA_MIPS2, CPU_R6000 },
13517 { "mips3", 1, ISA_MIPS3, CPU_R4000 },
13518 { "mips4", 1, ISA_MIPS4, CPU_R8000 },
13519 { "mips5", 1, ISA_MIPS5, CPU_MIPS5 },
13520 { "mips32", 1, ISA_MIPS32, CPU_MIPS32 },
13521 { "mips64", 1, ISA_MIPS64, CPU_MIPS64 },
13524 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
13525 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
13526 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
13529 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
13532 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
13533 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
13534 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
13535 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
13536 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
13537 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
13538 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
13539 { "orion", 0, ISA_MIPS3, CPU_R4600 },
13540 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
13543 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
13544 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
13545 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
13546 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
13547 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
13548 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
13549 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
13550 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
13551 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
13552 { "r7000", 0, ISA_MIPS4, CPU_R5000 },
13555 { "4kc", 0, ISA_MIPS32, CPU_MIPS32, },
13556 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
13557 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
13560 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
13561 { "20kc", 0, ISA_MIPS64, CPU_MIPS64 },
13563 /* Broadcom SB-1 CPU core */
13564 { "sb1", 0, ISA_MIPS64, CPU_SB1 },
13571 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
13572 with a final "000" replaced by "k". Ignore case.
13574 Note: this function is shared between GCC and GAS. */
13577 mips_strict_matching_cpu_name_p (canonical, given)
13578 const char *canonical, *given;
13580 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
13581 given++, canonical++;
13583 return ((*given == 0 && *canonical == 0)
13584 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
13588 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
13589 CPU name. We've traditionally allowed a lot of variation here.
13591 Note: this function is shared between GCC and GAS. */
13594 mips_matching_cpu_name_p (canonical, given)
13595 const char *canonical, *given;
13597 /* First see if the name matches exactly, or with a final "000"
13598 turned into "k". */
13599 if (mips_strict_matching_cpu_name_p (canonical, given))
13602 /* If not, try comparing based on numerical designation alone.
13603 See if GIVEN is an unadorned number, or 'r' followed by a number. */
13604 if (TOLOWER (*given) == 'r')
13606 if (!ISDIGIT (*given))
13609 /* Skip over some well-known prefixes in the canonical name,
13610 hoping to find a number there too. */
13611 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
13613 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
13615 else if (TOLOWER (canonical[0]) == 'r')
13618 return mips_strict_matching_cpu_name_p (canonical, given);
13622 /* Parse an option that takes the name of a processor as its argument.
13623 OPTION is the name of the option and CPU_STRING is the argument.
13624 Return the corresponding processor enumeration if the CPU_STRING is
13625 recognized, otherwise report an error and return null.
13627 A similar function exists in GCC. */
13629 static const struct mips_cpu_info *
13630 mips_parse_cpu (option, cpu_string)
13631 const char *option, *cpu_string;
13633 const struct mips_cpu_info *p;
13635 /* 'from-abi' selects the most compatible architecture for the given
13636 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
13637 EABIs, we have to decide whether we're using the 32-bit or 64-bit
13638 version. Look first at the -mgp options, if given, otherwise base
13639 the choice on MIPS_DEFAULT_64BIT.
13641 Treat NO_ABI like the EABIs. One reason to do this is that the
13642 plain 'mips' and 'mips64' configs have 'from-abi' as their default
13643 architecture. This code picks MIPS I for 'mips' and MIPS III for
13644 'mips64', just as we did in the days before 'from-abi'. */
13645 if (strcasecmp (cpu_string, "from-abi") == 0)
13647 if (ABI_NEEDS_32BIT_REGS (mips_abi))
13648 return mips_cpu_info_from_isa (ISA_MIPS1);
13650 if (ABI_NEEDS_64BIT_REGS (mips_abi))
13651 return mips_cpu_info_from_isa (ISA_MIPS3);
13653 if (file_mips_gp32 >= 0)
13654 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
13656 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
13661 /* 'default' has traditionally been a no-op. Probably not very useful. */
13662 if (strcasecmp (cpu_string, "default") == 0)
13665 for (p = mips_cpu_info_table; p->name != 0; p++)
13666 if (mips_matching_cpu_name_p (p->name, cpu_string))
13669 as_bad ("Bad value (%s) for %s", cpu_string, option);
13673 /* Return the canonical processor information for ISA (a member of the
13674 ISA_MIPS* enumeration). */
13676 static const struct mips_cpu_info *
13677 mips_cpu_info_from_isa (isa)
13682 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
13683 if (mips_cpu_info_table[i].is_isa
13684 && isa == mips_cpu_info_table[i].isa)
13685 return (&mips_cpu_info_table[i]);
13691 show (stream, string, col_p, first_p)
13693 const char *string;
13699 fprintf (stream, "%24s", "");
13704 fprintf (stream, ", ");
13708 if (*col_p + strlen (string) > 72)
13710 fprintf (stream, "\n%24s", "");
13714 fprintf (stream, "%s", string);
13715 *col_p += strlen (string);
13721 md_show_usage (stream)
13727 fprintf (stream, _("\
13729 -membedded-pic generate embedded position independent code\n\
13730 -EB generate big endian output\n\
13731 -EL generate little endian output\n\
13732 -g, -g2 do not remove unneeded NOPs or swap branches\n\
13733 -G NUM allow referencing objects up to NUM bytes\n\
13734 implicitly with the gp register [default 8]\n"));
13735 fprintf (stream, _("\
13736 -mips1 generate MIPS ISA I instructions\n\
13737 -mips2 generate MIPS ISA II instructions\n\
13738 -mips3 generate MIPS ISA III instructions\n\
13739 -mips4 generate MIPS ISA IV instructions\n\
13740 -mips5 generate MIPS ISA V instructions\n\
13741 -mips32 generate MIPS32 ISA instructions\n\
13742 -mips64 generate MIPS64 ISA instructions\n\
13743 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
13747 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
13748 show (stream, mips_cpu_info_table[i].name, &column, &first);
13749 show (stream, "from-abi", &column, &first);
13750 fputc ('\n', stream);
13752 fprintf (stream, _("\
13753 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
13754 -no-mCPU don't generate code specific to CPU.\n\
13755 For -mCPU and -no-mCPU, CPU must be one of:\n"));
13759 show (stream, "3900", &column, &first);
13760 show (stream, "4010", &column, &first);
13761 show (stream, "4100", &column, &first);
13762 show (stream, "4650", &column, &first);
13763 fputc ('\n', stream);
13765 fprintf (stream, _("\
13766 -mips16 generate mips16 instructions\n\
13767 -no-mips16 do not generate mips16 instructions\n"));
13768 fprintf (stream, _("\
13769 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
13770 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
13771 -O0 remove unneeded NOPs, do not swap branches\n\
13772 -O remove unneeded NOPs and swap branches\n\
13773 -n warn about NOPs generated from macros\n\
13774 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
13775 --trap, --no-break trap exception on div by 0 and mult overflow\n\
13776 --break, --no-trap break exception on div by 0 and mult overflow\n"));
13778 fprintf (stream, _("\
13779 -KPIC, -call_shared generate SVR4 position independent code\n\
13780 -non_shared do not generate position independent code\n\
13781 -xgot assume a 32 bit GOT\n\
13782 -mabi=ABI create ABI conformant object file for:\n"));
13786 show (stream, "32", &column, &first);
13787 show (stream, "o64", &column, &first);
13788 show (stream, "n32", &column, &first);
13789 show (stream, "64", &column, &first);
13790 show (stream, "eabi", &column, &first);
13792 fputc ('\n', stream);
13794 fprintf (stream, _("\
13795 -32 create o32 ABI object file (default)\n\
13796 -n32 create n32 ABI object file\n\
13797 -64 create 64 ABI object file\n"));