1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 #define AT mips_opts.at
107 /* Allow override of standard little-endian ECOFF format. */
109 #ifndef ECOFF_LITTLE_FORMAT
110 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
113 extern int target_big_endian;
115 /* The name of the readonly data section. */
116 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
124 /* Information about an instruction, including its format, operands
128 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
129 const struct mips_opcode *insn_mo;
131 /* True if this is a mips16 instruction and if we want the extended
133 bfd_boolean use_extend;
135 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
136 unsigned short extend;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. */
140 unsigned long insn_opcode;
142 /* The frag that contains the instruction. */
145 /* The offset into FRAG of the first instruction byte. */
148 /* The relocs associated with the instruction, if any. */
151 /* True if this entry cannot be moved from its current position. */
152 unsigned int fixed_p : 1;
154 /* True if this instruction occurred in a .set noreorder block. */
155 unsigned int noreorder_p : 1;
157 /* True for mips16 instructions that jump to an absolute address. */
158 unsigned int mips16_absolute_jump_p : 1;
160 /* True if this instruction is complete. */
161 unsigned int complete_p : 1;
164 /* The ABI to use. */
175 /* MIPS ABI we are using for this output file. */
176 static enum mips_abi_level mips_abi = NO_ABI;
178 /* Whether or not we have code that can call pic code. */
179 int mips_abicalls = FALSE;
181 /* Whether or not we have code which can be put into a shared
183 static bfd_boolean mips_in_shared = TRUE;
185 /* This is the set of options which may be modified by the .set
186 pseudo-op. We use a struct so that .set push and .set pop are more
189 struct mips_set_options
191 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
192 if it has not been initialized. Changed by `.set mipsN', and the
193 -mipsN command line option, and the default CPU. */
195 /* Enabled Application Specific Extensions (ASEs). These are set to -1
196 if they have not been initialized. Changed by `.set <asename>', by
197 command line options, and based on the default architecture. */
204 /* Whether we are assembling for the mips16 processor. 0 if we are
205 not, 1 if we are, and -1 if the value has not been initialized.
206 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
207 -nomips16 command line options, and the default CPU. */
209 /* Non-zero if we should not reorder instructions. Changed by `.set
210 reorder' and `.set noreorder'. */
212 /* Non-zero if we should not permit the register designated "assembler
213 temporary" to be used in instructions. The value is the register
214 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
215 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
217 /* Non-zero if we should warn when a macro instruction expands into
218 more than one machine instruction. Changed by `.set nomacro' and
220 int warn_about_macros;
221 /* Non-zero if we should not move instructions. Changed by `.set
222 move', `.set volatile', `.set nomove', and `.set novolatile'. */
224 /* Non-zero if we should not optimize branches by moving the target
225 of the branch into the delay slot. Actually, we don't perform
226 this optimization anyhow. Changed by `.set bopt' and `.set
229 /* Non-zero if we should not autoextend mips16 instructions.
230 Changed by `.set autoextend' and `.set noautoextend'. */
232 /* Restrict general purpose registers and floating point registers
233 to 32 bit. This is initially determined when -mgp32 or -mfp32
234 is passed but can changed if the assembler code uses .set mipsN. */
237 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
238 command line option, and the default CPU. */
240 /* True if ".set sym32" is in effect. */
242 /* True if floating-point operations are not allowed. Changed by .set
243 softfloat or .set hardfloat, by command line options -msoft-float or
244 -mhard-float. The default is false. */
245 bfd_boolean soft_float;
247 /* True if only single-precision floating-point operations are allowed.
248 Changed by .set singlefloat or .set doublefloat, command-line options
249 -msingle-float or -mdouble-float. The default is false. */
250 bfd_boolean single_float;
253 /* This is the struct we use to hold the current set of options. Note
254 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
255 -1 to indicate that they have not been initialized. */
257 /* True if -mgp32 was passed. */
258 static int file_mips_gp32 = -1;
260 /* True if -mfp32 was passed. */
261 static int file_mips_fp32 = -1;
263 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
264 static int file_mips_soft_float = 0;
266 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
267 static int file_mips_single_float = 0;
269 static struct mips_set_options mips_opts =
271 /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
272 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
273 /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG,
274 /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
275 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN,
276 /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE
279 /* These variables are filled in with the masks of registers used.
280 The object format code reads them and puts them in the appropriate
282 unsigned long mips_gprmask;
283 unsigned long mips_cprmask[4];
285 /* MIPS ISA we are using for this output file. */
286 static int file_mips_isa = ISA_UNKNOWN;
288 /* True if any MIPS16 code was produced. */
289 static int file_ase_mips16;
291 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
292 || mips_opts.isa == ISA_MIPS32R2 \
293 || mips_opts.isa == ISA_MIPS64 \
294 || mips_opts.isa == ISA_MIPS64R2)
296 /* True if we want to create R_MIPS_JALR for jalr $25. */
298 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
300 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
301 because there's no place for any addend, the only acceptable
302 expression is a bare symbol. */
303 #define MIPS_JALR_HINT_P(EXPR) \
304 (!HAVE_IN_PLACE_ADDENDS \
305 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
308 /* True if -mips3d was passed or implied by arguments passed on the
309 command line (e.g., by -march). */
310 static int file_ase_mips3d;
312 /* True if -mdmx was passed or implied by arguments passed on the
313 command line (e.g., by -march). */
314 static int file_ase_mdmx;
316 /* True if -msmartmips was passed or implied by arguments passed on the
317 command line (e.g., by -march). */
318 static int file_ase_smartmips;
320 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
321 || mips_opts.isa == ISA_MIPS32R2)
323 /* True if -mdsp was passed or implied by arguments passed on the
324 command line (e.g., by -march). */
325 static int file_ase_dsp;
327 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
328 || mips_opts.isa == ISA_MIPS64R2)
330 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
332 /* True if -mdspr2 was passed or implied by arguments passed on the
333 command line (e.g., by -march). */
334 static int file_ase_dspr2;
336 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
337 || mips_opts.isa == ISA_MIPS64R2)
339 /* True if -mmt was passed or implied by arguments passed on the
340 command line (e.g., by -march). */
341 static int file_ase_mt;
343 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
344 || mips_opts.isa == ISA_MIPS64R2)
346 /* The argument of the -march= flag. The architecture we are assembling. */
347 static int file_mips_arch = CPU_UNKNOWN;
348 static const char *mips_arch_string;
350 /* The argument of the -mtune= flag. The architecture for which we
352 static int mips_tune = CPU_UNKNOWN;
353 static const char *mips_tune_string;
355 /* True when generating 32-bit code for a 64-bit processor. */
356 static int mips_32bitmode = 0;
358 /* True if the given ABI requires 32-bit registers. */
359 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
361 /* Likewise 64-bit registers. */
362 #define ABI_NEEDS_64BIT_REGS(ABI) \
364 || (ABI) == N64_ABI \
367 /* Return true if ISA supports 64 bit wide gp registers. */
368 #define ISA_HAS_64BIT_REGS(ISA) \
369 ((ISA) == ISA_MIPS3 \
370 || (ISA) == ISA_MIPS4 \
371 || (ISA) == ISA_MIPS5 \
372 || (ISA) == ISA_MIPS64 \
373 || (ISA) == ISA_MIPS64R2)
375 /* Return true if ISA supports 64 bit wide float registers. */
376 #define ISA_HAS_64BIT_FPRS(ISA) \
377 ((ISA) == ISA_MIPS3 \
378 || (ISA) == ISA_MIPS4 \
379 || (ISA) == ISA_MIPS5 \
380 || (ISA) == ISA_MIPS32R2 \
381 || (ISA) == ISA_MIPS64 \
382 || (ISA) == ISA_MIPS64R2)
384 /* Return true if ISA supports 64-bit right rotate (dror et al.)
386 #define ISA_HAS_DROR(ISA) \
387 ((ISA) == ISA_MIPS64R2)
389 /* Return true if ISA supports 32-bit right rotate (ror et al.)
391 #define ISA_HAS_ROR(ISA) \
392 ((ISA) == ISA_MIPS32R2 \
393 || (ISA) == ISA_MIPS64R2 \
394 || mips_opts.ase_smartmips)
396 /* Return true if ISA supports single-precision floats in odd registers. */
397 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
398 ((ISA) == ISA_MIPS32 \
399 || (ISA) == ISA_MIPS32R2 \
400 || (ISA) == ISA_MIPS64 \
401 || (ISA) == ISA_MIPS64R2)
403 /* Return true if ISA supports move to/from high part of a 64-bit
404 floating-point register. */
405 #define ISA_HAS_MXHC1(ISA) \
406 ((ISA) == ISA_MIPS32R2 \
407 || (ISA) == ISA_MIPS64R2)
409 #define HAVE_32BIT_GPRS \
410 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
412 #define HAVE_32BIT_FPRS \
413 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
415 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
416 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
418 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
420 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
422 /* True if relocations are stored in-place. */
423 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
425 /* The ABI-derived address size. */
426 #define HAVE_64BIT_ADDRESSES \
427 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
428 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
430 /* The size of symbolic constants (i.e., expressions of the form
431 "SYMBOL" or "SYMBOL + OFFSET"). */
432 #define HAVE_32BIT_SYMBOLS \
433 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
434 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
436 /* Addresses are loaded in different ways, depending on the address size
437 in use. The n32 ABI Documentation also mandates the use of additions
438 with overflow checking, but existing implementations don't follow it. */
439 #define ADDRESS_ADD_INSN \
440 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
442 #define ADDRESS_ADDI_INSN \
443 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
445 #define ADDRESS_LOAD_INSN \
446 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
448 #define ADDRESS_STORE_INSN \
449 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
451 /* Return true if the given CPU supports the MIPS16 ASE. */
452 #define CPU_HAS_MIPS16(cpu) \
453 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
454 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
456 /* True if CPU has a dror instruction. */
457 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
459 /* True if CPU has a ror instruction. */
460 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
462 /* True if CPU has seq/sne and seqi/snei instructions. */
463 #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON)
465 /* True if CPU does not implement the all the coprocessor insns. For these
466 CPUs only those COP insns are accepted that are explicitly marked to be
467 available on the CPU. ISA membership for COP insns is ignored. */
468 #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON)
470 /* True if mflo and mfhi can be immediately followed by instructions
471 which write to the HI and LO registers.
473 According to MIPS specifications, MIPS ISAs I, II, and III need
474 (at least) two instructions between the reads of HI/LO and
475 instructions which write them, and later ISAs do not. Contradicting
476 the MIPS specifications, some MIPS IV processor user manuals (e.g.
477 the UM for the NEC Vr5000) document needing the instructions between
478 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
479 MIPS64 and later ISAs to have the interlocks, plus any specific
480 earlier-ISA CPUs for which CPU documentation declares that the
481 instructions are really interlocked. */
482 #define hilo_interlocks \
483 (mips_opts.isa == ISA_MIPS32 \
484 || mips_opts.isa == ISA_MIPS32R2 \
485 || mips_opts.isa == ISA_MIPS64 \
486 || mips_opts.isa == ISA_MIPS64R2 \
487 || mips_opts.arch == CPU_R4010 \
488 || mips_opts.arch == CPU_R10000 \
489 || mips_opts.arch == CPU_R12000 \
490 || mips_opts.arch == CPU_R14000 \
491 || mips_opts.arch == CPU_R16000 \
492 || mips_opts.arch == CPU_RM7000 \
493 || mips_opts.arch == CPU_VR5500 \
496 /* Whether the processor uses hardware interlocks to protect reads
497 from the GPRs after they are loaded from memory, and thus does not
498 require nops to be inserted. This applies to instructions marked
499 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
501 #define gpr_interlocks \
502 (mips_opts.isa != ISA_MIPS1 \
503 || mips_opts.arch == CPU_R3900)
505 /* Whether the processor uses hardware interlocks to avoid delays
506 required by coprocessor instructions, and thus does not require
507 nops to be inserted. This applies to instructions marked
508 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
509 between instructions marked INSN_WRITE_COND_CODE and ones marked
510 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
511 levels I, II, and III. */
512 /* Itbl support may require additional care here. */
513 #define cop_interlocks \
514 ((mips_opts.isa != ISA_MIPS1 \
515 && mips_opts.isa != ISA_MIPS2 \
516 && mips_opts.isa != ISA_MIPS3) \
517 || mips_opts.arch == CPU_R4300 \
520 /* Whether the processor uses hardware interlocks to protect reads
521 from coprocessor registers after they are loaded from memory, and
522 thus does not require nops to be inserted. This applies to
523 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
524 requires at MIPS ISA level I. */
525 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
527 /* Is this a mfhi or mflo instruction? */
528 #define MF_HILO_INSN(PINFO) \
529 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
531 /* Returns true for a (non floating-point) coprocessor instruction. Reading
532 or writing the condition code is only possible on the coprocessors and
533 these insns are not marked with INSN_COP. Thus for these insns use the
534 condition-code flags. */
535 #define COP_INSN(PINFO) \
536 (PINFO != INSN_MACRO \
537 && ((PINFO) & (FP_S | FP_D)) == 0 \
538 && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
540 /* MIPS PIC level. */
542 enum mips_pic_level mips_pic;
544 /* 1 if we should generate 32 bit offsets from the $gp register in
545 SVR4_PIC mode. Currently has no meaning in other modes. */
546 static int mips_big_got = 0;
548 /* 1 if trap instructions should used for overflow rather than break
550 static int mips_trap = 0;
552 /* 1 if double width floating point constants should not be constructed
553 by assembling two single width halves into two single width floating
554 point registers which just happen to alias the double width destination
555 register. On some architectures this aliasing can be disabled by a bit
556 in the status register, and the setting of this bit cannot be determined
557 automatically at assemble time. */
558 static int mips_disable_float_construction;
560 /* Non-zero if any .set noreorder directives were used. */
562 static int mips_any_noreorder;
564 /* Non-zero if nops should be inserted when the register referenced in
565 an mfhi/mflo instruction is read in the next two instructions. */
566 static int mips_7000_hilo_fix;
568 /* The size of objects in the small data section. */
569 static unsigned int g_switch_value = 8;
570 /* Whether the -G option was used. */
571 static int g_switch_seen = 0;
576 /* If we can determine in advance that GP optimization won't be
577 possible, we can skip the relaxation stuff that tries to produce
578 GP-relative references. This makes delay slot optimization work
581 This function can only provide a guess, but it seems to work for
582 gcc output. It needs to guess right for gcc, otherwise gcc
583 will put what it thinks is a GP-relative instruction in a branch
586 I don't know if a fix is needed for the SVR4_PIC mode. I've only
587 fixed it for the non-PIC mode. KR 95/04/07 */
588 static int nopic_need_relax (symbolS *, int);
590 /* handle of the OPCODE hash table */
591 static struct hash_control *op_hash = NULL;
593 /* The opcode hash table we use for the mips16. */
594 static struct hash_control *mips16_op_hash = NULL;
596 /* This array holds the chars that always start a comment. If the
597 pre-processor is disabled, these aren't very useful */
598 const char comment_chars[] = "#";
600 /* This array holds the chars that only start a comment at the beginning of
601 a line. If the line seems to have the form '# 123 filename'
602 .line and .file directives will appear in the pre-processed output */
603 /* Note that input_file.c hand checks for '#' at the beginning of the
604 first line of the input file. This is because the compiler outputs
605 #NO_APP at the beginning of its output. */
606 /* Also note that C style comments are always supported. */
607 const char line_comment_chars[] = "#";
609 /* This array holds machine specific line separator characters. */
610 const char line_separator_chars[] = ";";
612 /* Chars that can be used to separate mant from exp in floating point nums */
613 const char EXP_CHARS[] = "eE";
615 /* Chars that mean this number is a floating point constant */
618 const char FLT_CHARS[] = "rRsSfFdDxXpP";
620 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
621 changed in read.c . Ideally it shouldn't have to know about it at all,
622 but nothing is ideal around here.
625 static char *insn_error;
627 static int auto_align = 1;
629 /* When outputting SVR4 PIC code, the assembler needs to know the
630 offset in the stack frame from which to restore the $gp register.
631 This is set by the .cprestore pseudo-op, and saved in this
633 static offsetT mips_cprestore_offset = -1;
635 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
636 more optimizations, it can use a register value instead of a memory-saved
637 offset and even an other register than $gp as global pointer. */
638 static offsetT mips_cpreturn_offset = -1;
639 static int mips_cpreturn_register = -1;
640 static int mips_gp_register = GP;
641 static int mips_gprel_offset = 0;
643 /* Whether mips_cprestore_offset has been set in the current function
644 (or whether it has already been warned about, if not). */
645 static int mips_cprestore_valid = 0;
647 /* This is the register which holds the stack frame, as set by the
648 .frame pseudo-op. This is needed to implement .cprestore. */
649 static int mips_frame_reg = SP;
651 /* Whether mips_frame_reg has been set in the current function
652 (or whether it has already been warned about, if not). */
653 static int mips_frame_reg_valid = 0;
655 /* To output NOP instructions correctly, we need to keep information
656 about the previous two instructions. */
658 /* Whether we are optimizing. The default value of 2 means to remove
659 unneeded NOPs and swap branch instructions when possible. A value
660 of 1 means to not swap branches. A value of 0 means to always
662 static int mips_optimize = 2;
664 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
665 equivalent to seeing no -g option at all. */
666 static int mips_debug = 0;
668 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
669 #define MAX_VR4130_NOPS 4
671 /* The maximum number of NOPs needed to fill delay slots. */
672 #define MAX_DELAY_NOPS 2
674 /* The maximum number of NOPs needed for any purpose. */
677 /* A list of previous instructions, with index 0 being the most recent.
678 We need to look back MAX_NOPS instructions when filling delay slots
679 or working around processor errata. We need to look back one
680 instruction further if we're thinking about using history[0] to
681 fill a branch delay slot. */
682 static struct mips_cl_insn history[1 + MAX_NOPS];
684 /* Nop instructions used by emit_nop. */
685 static struct mips_cl_insn nop_insn, mips16_nop_insn;
687 /* The appropriate nop for the current mode. */
688 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
690 /* If this is set, it points to a frag holding nop instructions which
691 were inserted before the start of a noreorder section. If those
692 nops turn out to be unnecessary, the size of the frag can be
694 static fragS *prev_nop_frag;
696 /* The number of nop instructions we created in prev_nop_frag. */
697 static int prev_nop_frag_holds;
699 /* The number of nop instructions that we know we need in
701 static int prev_nop_frag_required;
703 /* The number of instructions we've seen since prev_nop_frag. */
704 static int prev_nop_frag_since;
706 /* For ECOFF and ELF, relocations against symbols are done in two
707 parts, with a HI relocation and a LO relocation. Each relocation
708 has only 16 bits of space to store an addend. This means that in
709 order for the linker to handle carries correctly, it must be able
710 to locate both the HI and the LO relocation. This means that the
711 relocations must appear in order in the relocation table.
713 In order to implement this, we keep track of each unmatched HI
714 relocation. We then sort them so that they immediately precede the
715 corresponding LO relocation. */
720 struct mips_hi_fixup *next;
723 /* The section this fixup is in. */
727 /* The list of unmatched HI relocs. */
729 static struct mips_hi_fixup *mips_hi_fixup_list;
731 /* The frag containing the last explicit relocation operator.
732 Null if explicit relocations have not been used. */
734 static fragS *prev_reloc_op_frag;
736 /* Map normal MIPS register numbers to mips16 register numbers. */
738 #define X ILLEGAL_REG
739 static const int mips32_to_16_reg_map[] =
741 X, X, 2, 3, 4, 5, 6, 7,
742 X, X, X, X, X, X, X, X,
743 0, 1, X, X, X, X, X, X,
744 X, X, X, X, X, X, X, X
748 /* Map mips16 register numbers to normal MIPS register numbers. */
750 static const unsigned int mips16_to_32_reg_map[] =
752 16, 17, 2, 3, 4, 5, 6, 7
755 /* Classifies the kind of instructions we're interested in when
756 implementing -mfix-vr4120. */
757 enum fix_vr4120_class
765 NUM_FIX_VR4120_CLASSES
768 /* ...likewise -mfix-loongson2f-jump. */
769 static bfd_boolean mips_fix_loongson2f_jump;
771 /* ...likewise -mfix-loongson2f-nop. */
772 static bfd_boolean mips_fix_loongson2f_nop;
774 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
775 static bfd_boolean mips_fix_loongson2f;
777 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
778 there must be at least one other instruction between an instruction
779 of type X and an instruction of type Y. */
780 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
782 /* True if -mfix-vr4120 is in force. */
783 static int mips_fix_vr4120;
785 /* ...likewise -mfix-vr4130. */
786 static int mips_fix_vr4130;
788 /* ...likewise -mfix-24k. */
789 static int mips_fix_24k;
791 /* ...likewise -mfix-cn63xxp1 */
792 static bfd_boolean mips_fix_cn63xxp1;
794 /* We don't relax branches by default, since this causes us to expand
795 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
796 fail to compute the offset before expanding the macro to the most
797 efficient expansion. */
799 static int mips_relax_branch;
801 /* The expansion of many macros depends on the type of symbol that
802 they refer to. For example, when generating position-dependent code,
803 a macro that refers to a symbol may have two different expansions,
804 one which uses GP-relative addresses and one which uses absolute
805 addresses. When generating SVR4-style PIC, a macro may have
806 different expansions for local and global symbols.
808 We handle these situations by generating both sequences and putting
809 them in variant frags. In position-dependent code, the first sequence
810 will be the GP-relative one and the second sequence will be the
811 absolute one. In SVR4 PIC, the first sequence will be for global
812 symbols and the second will be for local symbols.
814 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
815 SECOND are the lengths of the two sequences in bytes. These fields
816 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
817 the subtype has the following flags:
820 Set if it has been decided that we should use the second
821 sequence instead of the first.
824 Set in the first variant frag if the macro's second implementation
825 is longer than its first. This refers to the macro as a whole,
826 not an individual relaxation.
829 Set in the first variant frag if the macro appeared in a .set nomacro
830 block and if one alternative requires a warning but the other does not.
833 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
836 The frag's "opcode" points to the first fixup for relaxable code.
838 Relaxable macros are generated using a sequence such as:
840 relax_start (SYMBOL);
841 ... generate first expansion ...
843 ... generate second expansion ...
846 The code and fixups for the unwanted alternative are discarded
847 by md_convert_frag. */
848 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
850 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
851 #define RELAX_SECOND(X) ((X) & 0xff)
852 #define RELAX_USE_SECOND 0x10000
853 #define RELAX_SECOND_LONGER 0x20000
854 #define RELAX_NOMACRO 0x40000
855 #define RELAX_DELAY_SLOT 0x80000
857 /* Branch without likely bit. If label is out of range, we turn:
859 beq reg1, reg2, label
869 with the following opcode replacements:
876 bltzal <-> bgezal (with jal label instead of j label)
878 Even though keeping the delay slot instruction in the delay slot of
879 the branch would be more efficient, it would be very tricky to do
880 correctly, because we'd have to introduce a variable frag *after*
881 the delay slot instruction, and expand that instead. Let's do it
882 the easy way for now, even if the branch-not-taken case now costs
883 one additional instruction. Out-of-range branches are not supposed
884 to be common, anyway.
886 Branch likely. If label is out of range, we turn:
888 beql reg1, reg2, label
889 delay slot (annulled if branch not taken)
898 delay slot (executed only if branch taken)
901 It would be possible to generate a shorter sequence by losing the
902 likely bit, generating something like:
907 delay slot (executed only if branch taken)
919 bltzall -> bgezal (with jal label instead of j label)
920 bgezall -> bltzal (ditto)
923 but it's not clear that it would actually improve performance. */
924 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
928 | ((toofar) ? 0x20 : 0) \
929 | ((link) ? 0x40 : 0) \
930 | ((likely) ? 0x80 : 0) \
931 | ((uncond) ? 0x100 : 0)))
932 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
933 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
934 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
935 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
936 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
937 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
939 /* For mips16 code, we use an entirely different form of relaxation.
940 mips16 supports two versions of most instructions which take
941 immediate values: a small one which takes some small value, and a
942 larger one which takes a 16 bit value. Since branches also follow
943 this pattern, relaxing these values is required.
945 We can assemble both mips16 and normal MIPS code in a single
946 object. Therefore, we need to support this type of relaxation at
947 the same time that we support the relaxation described above. We
948 use the high bit of the subtype field to distinguish these cases.
950 The information we store for this type of relaxation is the
951 argument code found in the opcode file for this relocation, whether
952 the user explicitly requested a small or extended form, and whether
953 the relocation is in a jump or jal delay slot. That tells us the
954 size of the value, and how it should be stored. We also store
955 whether the fragment is considered to be extended or not. We also
956 store whether this is known to be a branch to a different section,
957 whether we have tried to relax this frag yet, and whether we have
958 ever extended a PC relative fragment because of a shift count. */
959 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
962 | ((small) ? 0x100 : 0) \
963 | ((ext) ? 0x200 : 0) \
964 | ((dslot) ? 0x400 : 0) \
965 | ((jal_dslot) ? 0x800 : 0))
966 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
967 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
968 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
969 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
970 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
971 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
972 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
973 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
974 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
975 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
976 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
977 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
979 /* Is the given value a sign-extended 32-bit value? */
980 #define IS_SEXT_32BIT_NUM(x) \
981 (((x) &~ (offsetT) 0x7fffffff) == 0 \
982 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
984 /* Is the given value a sign-extended 16-bit value? */
985 #define IS_SEXT_16BIT_NUM(x) \
986 (((x) &~ (offsetT) 0x7fff) == 0 \
987 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
989 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
990 #define IS_ZEXT_32BIT_NUM(x) \
991 (((x) &~ (offsetT) 0xffffffff) == 0 \
992 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
994 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
995 VALUE << SHIFT. VALUE is evaluated exactly once. */
996 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
997 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
998 | (((VALUE) & (MASK)) << (SHIFT)))
1000 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1002 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1003 (((STRUCT) >> (SHIFT)) & (MASK))
1005 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1006 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1008 include/opcode/mips.h specifies operand fields using the macros
1009 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1010 with "MIPS16OP" instead of "OP". */
1011 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
1012 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
1013 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1014 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1015 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1017 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1018 #define EXTRACT_OPERAND(FIELD, INSN) \
1019 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
1020 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1021 EXTRACT_BITS ((INSN).insn_opcode, \
1022 MIPS16OP_MASK_##FIELD, \
1023 MIPS16OP_SH_##FIELD)
1025 /* Global variables used when generating relaxable macros. See the
1026 comment above RELAX_ENCODE for more details about how relaxation
1029 /* 0 if we're not emitting a relaxable macro.
1030 1 if we're emitting the first of the two relaxation alternatives.
1031 2 if we're emitting the second alternative. */
1034 /* The first relaxable fixup in the current frag. (In other words,
1035 the first fixup that refers to relaxable code.) */
1038 /* sizes[0] says how many bytes of the first alternative are stored in
1039 the current frag. Likewise sizes[1] for the second alternative. */
1040 unsigned int sizes[2];
1042 /* The symbol on which the choice of sequence depends. */
1046 /* Global variables used to decide whether a macro needs a warning. */
1048 /* True if the macro is in a branch delay slot. */
1049 bfd_boolean delay_slot_p;
1051 /* For relaxable macros, sizes[0] is the length of the first alternative
1052 in bytes and sizes[1] is the length of the second alternative.
1053 For non-relaxable macros, both elements give the length of the
1055 unsigned int sizes[2];
1057 /* The first variant frag for this macro. */
1059 } mips_macro_warning;
1061 /* Prototypes for static functions. */
1063 #define internalError() \
1064 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1066 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1068 static void append_insn
1069 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *);
1070 static void mips_no_prev_insn (void);
1071 static void macro_build (expressionS *, const char *, const char *, ...);
1072 static void mips16_macro_build
1073 (expressionS *, const char *, const char *, va_list *);
1074 static void load_register (int, expressionS *, int);
1075 static void macro_start (void);
1076 static void macro_end (void);
1077 static void macro (struct mips_cl_insn * ip);
1078 static void mips16_macro (struct mips_cl_insn * ip);
1079 static void mips_ip (char *str, struct mips_cl_insn * ip);
1080 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1081 static void mips16_immed
1082 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
1083 unsigned long *, bfd_boolean *, unsigned short *);
1084 static size_t my_getSmallExpression
1085 (expressionS *, bfd_reloc_code_real_type *, char *);
1086 static void my_getExpression (expressionS *, char *);
1087 static void s_align (int);
1088 static void s_change_sec (int);
1089 static void s_change_section (int);
1090 static void s_cons (int);
1091 static void s_float_cons (int);
1092 static void s_mips_globl (int);
1093 static void s_option (int);
1094 static void s_mipsset (int);
1095 static void s_abicalls (int);
1096 static void s_cpload (int);
1097 static void s_cpsetup (int);
1098 static void s_cplocal (int);
1099 static void s_cprestore (int);
1100 static void s_cpreturn (int);
1101 static void s_dtprelword (int);
1102 static void s_dtpreldword (int);
1103 static void s_gpvalue (int);
1104 static void s_gpword (int);
1105 static void s_gpdword (int);
1106 static void s_cpadd (int);
1107 static void s_insn (int);
1108 static void md_obj_begin (void);
1109 static void md_obj_end (void);
1110 static void s_mips_ent (int);
1111 static void s_mips_end (int);
1112 static void s_mips_frame (int);
1113 static void s_mips_mask (int reg_type);
1114 static void s_mips_stab (int);
1115 static void s_mips_weakext (int);
1116 static void s_mips_file (int);
1117 static void s_mips_loc (int);
1118 static bfd_boolean pic_need_relax (symbolS *, asection *);
1119 static int relaxed_branch_length (fragS *, asection *, int);
1120 static int validate_mips_insn (const struct mips_opcode *);
1122 /* Table and functions used to map between CPU/ISA names, and
1123 ISA levels, and CPU numbers. */
1125 struct mips_cpu_info
1127 const char *name; /* CPU or ISA name. */
1128 int flags; /* ASEs available, or ISA flag. */
1129 int isa; /* ISA level. */
1130 int cpu; /* CPU number (default CPU if ISA). */
1133 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1134 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1135 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1136 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1137 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1138 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1139 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1141 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1142 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1143 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1147 The following pseudo-ops from the Kane and Heinrich MIPS book
1148 should be defined here, but are currently unsupported: .alias,
1149 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1151 The following pseudo-ops from the Kane and Heinrich MIPS book are
1152 specific to the type of debugging information being generated, and
1153 should be defined by the object format: .aent, .begin, .bend,
1154 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1157 The following pseudo-ops from the Kane and Heinrich MIPS book are
1158 not MIPS CPU specific, but are also not specific to the object file
1159 format. This file is probably the best place to define them, but
1160 they are not currently supported: .asm0, .endr, .lab, .struct. */
1162 static const pseudo_typeS mips_pseudo_table[] =
1164 /* MIPS specific pseudo-ops. */
1165 {"option", s_option, 0},
1166 {"set", s_mipsset, 0},
1167 {"rdata", s_change_sec, 'r'},
1168 {"sdata", s_change_sec, 's'},
1169 {"livereg", s_ignore, 0},
1170 {"abicalls", s_abicalls, 0},
1171 {"cpload", s_cpload, 0},
1172 {"cpsetup", s_cpsetup, 0},
1173 {"cplocal", s_cplocal, 0},
1174 {"cprestore", s_cprestore, 0},
1175 {"cpreturn", s_cpreturn, 0},
1176 {"dtprelword", s_dtprelword, 0},
1177 {"dtpreldword", s_dtpreldword, 0},
1178 {"gpvalue", s_gpvalue, 0},
1179 {"gpword", s_gpword, 0},
1180 {"gpdword", s_gpdword, 0},
1181 {"cpadd", s_cpadd, 0},
1182 {"insn", s_insn, 0},
1184 /* Relatively generic pseudo-ops that happen to be used on MIPS
1186 {"asciiz", stringer, 8 + 1},
1187 {"bss", s_change_sec, 'b'},
1189 {"half", s_cons, 1},
1190 {"dword", s_cons, 3},
1191 {"weakext", s_mips_weakext, 0},
1192 {"origin", s_org, 0},
1193 {"repeat", s_rept, 0},
1195 /* For MIPS this is non-standard, but we define it for consistency. */
1196 {"sbss", s_change_sec, 'B'},
1198 /* These pseudo-ops are defined in read.c, but must be overridden
1199 here for one reason or another. */
1200 {"align", s_align, 0},
1201 {"byte", s_cons, 0},
1202 {"data", s_change_sec, 'd'},
1203 {"double", s_float_cons, 'd'},
1204 {"float", s_float_cons, 'f'},
1205 {"globl", s_mips_globl, 0},
1206 {"global", s_mips_globl, 0},
1207 {"hword", s_cons, 1},
1209 {"long", s_cons, 2},
1210 {"octa", s_cons, 4},
1211 {"quad", s_cons, 3},
1212 {"section", s_change_section, 0},
1213 {"short", s_cons, 1},
1214 {"single", s_float_cons, 'f'},
1215 {"stabn", s_mips_stab, 'n'},
1216 {"text", s_change_sec, 't'},
1217 {"word", s_cons, 2},
1219 { "extern", ecoff_directive_extern, 0},
1224 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1226 /* These pseudo-ops should be defined by the object file format.
1227 However, a.out doesn't support them, so we have versions here. */
1228 {"aent", s_mips_ent, 1},
1229 {"bgnb", s_ignore, 0},
1230 {"end", s_mips_end, 0},
1231 {"endb", s_ignore, 0},
1232 {"ent", s_mips_ent, 0},
1233 {"file", s_mips_file, 0},
1234 {"fmask", s_mips_mask, 'F'},
1235 {"frame", s_mips_frame, 0},
1236 {"loc", s_mips_loc, 0},
1237 {"mask", s_mips_mask, 'R'},
1238 {"verstamp", s_ignore, 0},
1242 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1243 purpose of the `.dc.a' internal pseudo-op. */
1246 mips_address_bytes (void)
1248 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1251 extern void pop_insert (const pseudo_typeS *);
1254 mips_pop_insert (void)
1256 pop_insert (mips_pseudo_table);
1257 if (! ECOFF_DEBUGGING)
1258 pop_insert (mips_nonecoff_pseudo_table);
1261 /* Symbols labelling the current insn. */
1263 struct insn_label_list
1265 struct insn_label_list *next;
1269 static struct insn_label_list *free_insn_labels;
1270 #define label_list tc_segment_info_data.labels
1272 static void mips_clear_insn_labels (void);
1275 mips_clear_insn_labels (void)
1277 register struct insn_label_list **pl;
1278 segment_info_type *si;
1282 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1285 si = seg_info (now_seg);
1286 *pl = si->label_list;
1287 si->label_list = NULL;
1292 static char *expr_end;
1294 /* Expressions which appear in instructions. These are set by
1297 static expressionS imm_expr;
1298 static expressionS imm2_expr;
1299 static expressionS offset_expr;
1301 /* Relocs associated with imm_expr and offset_expr. */
1303 static bfd_reloc_code_real_type imm_reloc[3]
1304 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1305 static bfd_reloc_code_real_type offset_reloc[3]
1306 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1308 /* These are set by mips16_ip if an explicit extension is used. */
1310 static bfd_boolean mips16_small, mips16_ext;
1313 /* The pdr segment for per procedure frame/regmask info. Not used for
1316 static segT pdr_seg;
1319 /* The default target format to use. */
1321 #if defined (TE_FreeBSD)
1322 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1323 #elif defined (TE_TMIPS)
1324 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1326 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1330 mips_target_format (void)
1332 switch (OUTPUT_FLAVOR)
1334 case bfd_target_ecoff_flavour:
1335 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1336 case bfd_target_coff_flavour:
1338 case bfd_target_elf_flavour:
1340 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1341 return (target_big_endian
1342 ? "elf32-bigmips-vxworks"
1343 : "elf32-littlemips-vxworks");
1345 return (target_big_endian
1346 ? (HAVE_64BIT_OBJECTS
1347 ? ELF_TARGET ("elf64-", "big")
1349 ? ELF_TARGET ("elf32-n", "big")
1350 : ELF_TARGET ("elf32-", "big")))
1351 : (HAVE_64BIT_OBJECTS
1352 ? ELF_TARGET ("elf64-", "little")
1354 ? ELF_TARGET ("elf32-n", "little")
1355 : ELF_TARGET ("elf32-", "little"))));
1362 /* Return the length of instruction INSN. */
1364 static inline unsigned int
1365 insn_length (const struct mips_cl_insn *insn)
1367 if (!mips_opts.mips16)
1369 return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2;
1372 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1375 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1380 insn->use_extend = FALSE;
1382 insn->insn_opcode = mo->match;
1385 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1386 insn->fixp[i] = NULL;
1387 insn->fixed_p = (mips_opts.noreorder > 0);
1388 insn->noreorder_p = (mips_opts.noreorder > 0);
1389 insn->mips16_absolute_jump_p = 0;
1390 insn->complete_p = 0;
1393 /* Record the current MIPS16 mode in now_seg. */
1396 mips_record_mips16_mode (void)
1398 segment_info_type *si;
1400 si = seg_info (now_seg);
1401 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
1402 si->tc_segment_info_data.mips16 = mips_opts.mips16;
1405 /* Install INSN at the location specified by its "frag" and "where" fields. */
1408 install_insn (const struct mips_cl_insn *insn)
1410 char *f = insn->frag->fr_literal + insn->where;
1411 if (!mips_opts.mips16)
1412 md_number_to_chars (f, insn->insn_opcode, 4);
1413 else if (insn->mips16_absolute_jump_p)
1415 md_number_to_chars (f, insn->insn_opcode >> 16, 2);
1416 md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2);
1420 if (insn->use_extend)
1422 md_number_to_chars (f, 0xf000 | insn->extend, 2);
1425 md_number_to_chars (f, insn->insn_opcode, 2);
1427 mips_record_mips16_mode ();
1430 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1431 and install the opcode in the new location. */
1434 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
1439 insn->where = where;
1440 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1441 if (insn->fixp[i] != NULL)
1443 insn->fixp[i]->fx_frag = frag;
1444 insn->fixp[i]->fx_where = where;
1446 install_insn (insn);
1449 /* Add INSN to the end of the output. */
1452 add_fixed_insn (struct mips_cl_insn *insn)
1454 char *f = frag_more (insn_length (insn));
1455 move_insn (insn, frag_now, f - frag_now->fr_literal);
1458 /* Start a variant frag and move INSN to the start of the variant part,
1459 marking it as fixed. The other arguments are as for frag_var. */
1462 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
1463 relax_substateT subtype, symbolS *symbol, offsetT offset)
1465 frag_grow (max_chars);
1466 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
1468 frag_var (rs_machine_dependent, max_chars, var,
1469 subtype, symbol, offset, NULL);
1472 /* Insert N copies of INSN into the history buffer, starting at
1473 position FIRST. Neither FIRST nor N need to be clipped. */
1476 insert_into_history (unsigned int first, unsigned int n,
1477 const struct mips_cl_insn *insn)
1479 if (mips_relax.sequence != 2)
1483 for (i = ARRAY_SIZE (history); i-- > first;)
1485 history[i] = history[i - n];
1491 /* Emit a nop instruction, recording it in the history buffer. */
1496 add_fixed_insn (NOP_INSN);
1497 insert_into_history (0, 1, NOP_INSN);
1500 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1501 the idea is to make it obvious at a glance that each errata is
1505 init_vr4120_conflicts (void)
1507 #define CONFLICT(FIRST, SECOND) \
1508 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1510 /* Errata 21 - [D]DIV[U] after [D]MACC */
1511 CONFLICT (MACC, DIV);
1512 CONFLICT (DMACC, DIV);
1514 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1515 CONFLICT (DMULT, DMULT);
1516 CONFLICT (DMULT, DMACC);
1517 CONFLICT (DMACC, DMULT);
1518 CONFLICT (DMACC, DMACC);
1520 /* Errata 24 - MT{LO,HI} after [D]MACC */
1521 CONFLICT (MACC, MTHILO);
1522 CONFLICT (DMACC, MTHILO);
1524 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1525 instruction is executed immediately after a MACC or DMACC
1526 instruction, the result of [either instruction] is incorrect." */
1527 CONFLICT (MACC, MULT);
1528 CONFLICT (MACC, DMULT);
1529 CONFLICT (DMACC, MULT);
1530 CONFLICT (DMACC, DMULT);
1532 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1533 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1534 DDIV or DDIVU instruction, the result of the MACC or
1535 DMACC instruction is incorrect.". */
1536 CONFLICT (DMULT, MACC);
1537 CONFLICT (DMULT, DMACC);
1538 CONFLICT (DIV, MACC);
1539 CONFLICT (DIV, DMACC);
1549 #define RTYPE_MASK 0x1ff00
1550 #define RTYPE_NUM 0x00100
1551 #define RTYPE_FPU 0x00200
1552 #define RTYPE_FCC 0x00400
1553 #define RTYPE_VEC 0x00800
1554 #define RTYPE_GP 0x01000
1555 #define RTYPE_CP0 0x02000
1556 #define RTYPE_PC 0x04000
1557 #define RTYPE_ACC 0x08000
1558 #define RTYPE_CCC 0x10000
1559 #define RNUM_MASK 0x000ff
1560 #define RWARN 0x80000
1562 #define GENERIC_REGISTER_NUMBERS \
1563 {"$0", RTYPE_NUM | 0}, \
1564 {"$1", RTYPE_NUM | 1}, \
1565 {"$2", RTYPE_NUM | 2}, \
1566 {"$3", RTYPE_NUM | 3}, \
1567 {"$4", RTYPE_NUM | 4}, \
1568 {"$5", RTYPE_NUM | 5}, \
1569 {"$6", RTYPE_NUM | 6}, \
1570 {"$7", RTYPE_NUM | 7}, \
1571 {"$8", RTYPE_NUM | 8}, \
1572 {"$9", RTYPE_NUM | 9}, \
1573 {"$10", RTYPE_NUM | 10}, \
1574 {"$11", RTYPE_NUM | 11}, \
1575 {"$12", RTYPE_NUM | 12}, \
1576 {"$13", RTYPE_NUM | 13}, \
1577 {"$14", RTYPE_NUM | 14}, \
1578 {"$15", RTYPE_NUM | 15}, \
1579 {"$16", RTYPE_NUM | 16}, \
1580 {"$17", RTYPE_NUM | 17}, \
1581 {"$18", RTYPE_NUM | 18}, \
1582 {"$19", RTYPE_NUM | 19}, \
1583 {"$20", RTYPE_NUM | 20}, \
1584 {"$21", RTYPE_NUM | 21}, \
1585 {"$22", RTYPE_NUM | 22}, \
1586 {"$23", RTYPE_NUM | 23}, \
1587 {"$24", RTYPE_NUM | 24}, \
1588 {"$25", RTYPE_NUM | 25}, \
1589 {"$26", RTYPE_NUM | 26}, \
1590 {"$27", RTYPE_NUM | 27}, \
1591 {"$28", RTYPE_NUM | 28}, \
1592 {"$29", RTYPE_NUM | 29}, \
1593 {"$30", RTYPE_NUM | 30}, \
1594 {"$31", RTYPE_NUM | 31}
1596 #define FPU_REGISTER_NAMES \
1597 {"$f0", RTYPE_FPU | 0}, \
1598 {"$f1", RTYPE_FPU | 1}, \
1599 {"$f2", RTYPE_FPU | 2}, \
1600 {"$f3", RTYPE_FPU | 3}, \
1601 {"$f4", RTYPE_FPU | 4}, \
1602 {"$f5", RTYPE_FPU | 5}, \
1603 {"$f6", RTYPE_FPU | 6}, \
1604 {"$f7", RTYPE_FPU | 7}, \
1605 {"$f8", RTYPE_FPU | 8}, \
1606 {"$f9", RTYPE_FPU | 9}, \
1607 {"$f10", RTYPE_FPU | 10}, \
1608 {"$f11", RTYPE_FPU | 11}, \
1609 {"$f12", RTYPE_FPU | 12}, \
1610 {"$f13", RTYPE_FPU | 13}, \
1611 {"$f14", RTYPE_FPU | 14}, \
1612 {"$f15", RTYPE_FPU | 15}, \
1613 {"$f16", RTYPE_FPU | 16}, \
1614 {"$f17", RTYPE_FPU | 17}, \
1615 {"$f18", RTYPE_FPU | 18}, \
1616 {"$f19", RTYPE_FPU | 19}, \
1617 {"$f20", RTYPE_FPU | 20}, \
1618 {"$f21", RTYPE_FPU | 21}, \
1619 {"$f22", RTYPE_FPU | 22}, \
1620 {"$f23", RTYPE_FPU | 23}, \
1621 {"$f24", RTYPE_FPU | 24}, \
1622 {"$f25", RTYPE_FPU | 25}, \
1623 {"$f26", RTYPE_FPU | 26}, \
1624 {"$f27", RTYPE_FPU | 27}, \
1625 {"$f28", RTYPE_FPU | 28}, \
1626 {"$f29", RTYPE_FPU | 29}, \
1627 {"$f30", RTYPE_FPU | 30}, \
1628 {"$f31", RTYPE_FPU | 31}
1630 #define FPU_CONDITION_CODE_NAMES \
1631 {"$fcc0", RTYPE_FCC | 0}, \
1632 {"$fcc1", RTYPE_FCC | 1}, \
1633 {"$fcc2", RTYPE_FCC | 2}, \
1634 {"$fcc3", RTYPE_FCC | 3}, \
1635 {"$fcc4", RTYPE_FCC | 4}, \
1636 {"$fcc5", RTYPE_FCC | 5}, \
1637 {"$fcc6", RTYPE_FCC | 6}, \
1638 {"$fcc7", RTYPE_FCC | 7}
1640 #define COPROC_CONDITION_CODE_NAMES \
1641 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1642 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1643 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1644 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1645 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1646 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1647 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1648 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1650 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1651 {"$a4", RTYPE_GP | 8}, \
1652 {"$a5", RTYPE_GP | 9}, \
1653 {"$a6", RTYPE_GP | 10}, \
1654 {"$a7", RTYPE_GP | 11}, \
1655 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1656 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1657 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1658 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1659 {"$t0", RTYPE_GP | 12}, \
1660 {"$t1", RTYPE_GP | 13}, \
1661 {"$t2", RTYPE_GP | 14}, \
1662 {"$t3", RTYPE_GP | 15}
1664 #define O32_SYMBOLIC_REGISTER_NAMES \
1665 {"$t0", RTYPE_GP | 8}, \
1666 {"$t1", RTYPE_GP | 9}, \
1667 {"$t2", RTYPE_GP | 10}, \
1668 {"$t3", RTYPE_GP | 11}, \
1669 {"$t4", RTYPE_GP | 12}, \
1670 {"$t5", RTYPE_GP | 13}, \
1671 {"$t6", RTYPE_GP | 14}, \
1672 {"$t7", RTYPE_GP | 15}, \
1673 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1674 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1675 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1676 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1678 /* Remaining symbolic register names */
1679 #define SYMBOLIC_REGISTER_NAMES \
1680 {"$zero", RTYPE_GP | 0}, \
1681 {"$at", RTYPE_GP | 1}, \
1682 {"$AT", RTYPE_GP | 1}, \
1683 {"$v0", RTYPE_GP | 2}, \
1684 {"$v1", RTYPE_GP | 3}, \
1685 {"$a0", RTYPE_GP | 4}, \
1686 {"$a1", RTYPE_GP | 5}, \
1687 {"$a2", RTYPE_GP | 6}, \
1688 {"$a3", RTYPE_GP | 7}, \
1689 {"$s0", RTYPE_GP | 16}, \
1690 {"$s1", RTYPE_GP | 17}, \
1691 {"$s2", RTYPE_GP | 18}, \
1692 {"$s3", RTYPE_GP | 19}, \
1693 {"$s4", RTYPE_GP | 20}, \
1694 {"$s5", RTYPE_GP | 21}, \
1695 {"$s6", RTYPE_GP | 22}, \
1696 {"$s7", RTYPE_GP | 23}, \
1697 {"$t8", RTYPE_GP | 24}, \
1698 {"$t9", RTYPE_GP | 25}, \
1699 {"$k0", RTYPE_GP | 26}, \
1700 {"$kt0", RTYPE_GP | 26}, \
1701 {"$k1", RTYPE_GP | 27}, \
1702 {"$kt1", RTYPE_GP | 27}, \
1703 {"$gp", RTYPE_GP | 28}, \
1704 {"$sp", RTYPE_GP | 29}, \
1705 {"$s8", RTYPE_GP | 30}, \
1706 {"$fp", RTYPE_GP | 30}, \
1707 {"$ra", RTYPE_GP | 31}
1709 #define MIPS16_SPECIAL_REGISTER_NAMES \
1710 {"$pc", RTYPE_PC | 0}
1712 #define MDMX_VECTOR_REGISTER_NAMES \
1713 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
1714 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
1715 {"$v2", RTYPE_VEC | 2}, \
1716 {"$v3", RTYPE_VEC | 3}, \
1717 {"$v4", RTYPE_VEC | 4}, \
1718 {"$v5", RTYPE_VEC | 5}, \
1719 {"$v6", RTYPE_VEC | 6}, \
1720 {"$v7", RTYPE_VEC | 7}, \
1721 {"$v8", RTYPE_VEC | 8}, \
1722 {"$v9", RTYPE_VEC | 9}, \
1723 {"$v10", RTYPE_VEC | 10}, \
1724 {"$v11", RTYPE_VEC | 11}, \
1725 {"$v12", RTYPE_VEC | 12}, \
1726 {"$v13", RTYPE_VEC | 13}, \
1727 {"$v14", RTYPE_VEC | 14}, \
1728 {"$v15", RTYPE_VEC | 15}, \
1729 {"$v16", RTYPE_VEC | 16}, \
1730 {"$v17", RTYPE_VEC | 17}, \
1731 {"$v18", RTYPE_VEC | 18}, \
1732 {"$v19", RTYPE_VEC | 19}, \
1733 {"$v20", RTYPE_VEC | 20}, \
1734 {"$v21", RTYPE_VEC | 21}, \
1735 {"$v22", RTYPE_VEC | 22}, \
1736 {"$v23", RTYPE_VEC | 23}, \
1737 {"$v24", RTYPE_VEC | 24}, \
1738 {"$v25", RTYPE_VEC | 25}, \
1739 {"$v26", RTYPE_VEC | 26}, \
1740 {"$v27", RTYPE_VEC | 27}, \
1741 {"$v28", RTYPE_VEC | 28}, \
1742 {"$v29", RTYPE_VEC | 29}, \
1743 {"$v30", RTYPE_VEC | 30}, \
1744 {"$v31", RTYPE_VEC | 31}
1746 #define MIPS_DSP_ACCUMULATOR_NAMES \
1747 {"$ac0", RTYPE_ACC | 0}, \
1748 {"$ac1", RTYPE_ACC | 1}, \
1749 {"$ac2", RTYPE_ACC | 2}, \
1750 {"$ac3", RTYPE_ACC | 3}
1752 static const struct regname reg_names[] = {
1753 GENERIC_REGISTER_NUMBERS,
1755 FPU_CONDITION_CODE_NAMES,
1756 COPROC_CONDITION_CODE_NAMES,
1758 /* The $txx registers depends on the abi,
1759 these will be added later into the symbol table from
1760 one of the tables below once mips_abi is set after
1761 parsing of arguments from the command line. */
1762 SYMBOLIC_REGISTER_NAMES,
1764 MIPS16_SPECIAL_REGISTER_NAMES,
1765 MDMX_VECTOR_REGISTER_NAMES,
1766 MIPS_DSP_ACCUMULATOR_NAMES,
1770 static const struct regname reg_names_o32[] = {
1771 O32_SYMBOLIC_REGISTER_NAMES,
1775 static const struct regname reg_names_n32n64[] = {
1776 N32N64_SYMBOLIC_REGISTER_NAMES,
1781 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
1788 /* Find end of name. */
1790 if (is_name_beginner (*e))
1792 while (is_part_of_name (*e))
1795 /* Terminate name. */
1799 /* Look for a register symbol. */
1800 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
1802 int r = S_GET_VALUE (symbolP);
1804 reg = r & RNUM_MASK;
1805 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
1806 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
1807 reg = (r & RNUM_MASK) - 2;
1809 /* Else see if this is a register defined in an itbl entry. */
1810 else if ((types & RTYPE_GP) && itbl_have_entries)
1817 if (itbl_get_reg_val (n, &r))
1818 reg = r & RNUM_MASK;
1821 /* Advance to next token if a register was recognised. */
1824 else if (types & RWARN)
1825 as_warn (_("Unrecognized register name `%s'"), *s);
1833 /* Return TRUE if opcode MO is valid on the currently selected ISA and
1834 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
1837 is_opcode_valid (const struct mips_opcode *mo)
1839 int isa = mips_opts.isa;
1842 if (mips_opts.ase_mdmx)
1844 if (mips_opts.ase_dsp)
1846 if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
1848 if (mips_opts.ase_dspr2)
1850 if (mips_opts.ase_mt)
1852 if (mips_opts.ase_mips3d)
1854 if (mips_opts.ase_smartmips)
1855 isa |= INSN_SMARTMIPS;
1857 /* Don't accept instructions based on the ISA if the CPU does not implement
1858 all the coprocessor insns. */
1859 if (NO_ISA_COP (mips_opts.arch)
1860 && COP_INSN (mo->pinfo))
1863 if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch))
1866 /* Check whether the instruction or macro requires single-precision or
1867 double-precision floating-point support. Note that this information is
1868 stored differently in the opcode table for insns and macros. */
1869 if (mo->pinfo == INSN_MACRO)
1871 fp_s = mo->pinfo2 & INSN2_M_FP_S;
1872 fp_d = mo->pinfo2 & INSN2_M_FP_D;
1876 fp_s = mo->pinfo & FP_S;
1877 fp_d = mo->pinfo & FP_D;
1880 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
1883 if (fp_s && mips_opts.soft_float)
1889 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
1890 selected ISA and architecture. */
1893 is_opcode_valid_16 (const struct mips_opcode *mo)
1895 return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE;
1898 /* This function is called once, at assembler startup time. It should set up
1899 all the tables, etc. that the MD part of the assembler will need. */
1904 const char *retval = NULL;
1908 if (mips_pic != NO_PIC)
1910 if (g_switch_seen && g_switch_value != 0)
1911 as_bad (_("-G may not be used in position-independent code"));
1915 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
1916 as_warn (_("Could not set architecture and machine"));
1918 op_hash = hash_new ();
1920 for (i = 0; i < NUMOPCODES;)
1922 const char *name = mips_opcodes[i].name;
1924 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
1927 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1928 mips_opcodes[i].name, retval);
1929 /* Probably a memory allocation problem? Give up now. */
1930 as_fatal (_("Broken assembler. No assembly attempted."));
1934 if (mips_opcodes[i].pinfo != INSN_MACRO)
1936 if (!validate_mips_insn (&mips_opcodes[i]))
1938 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
1940 create_insn (&nop_insn, mips_opcodes + i);
1941 if (mips_fix_loongson2f_nop)
1942 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
1943 nop_insn.fixed_p = 1;
1948 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1951 mips16_op_hash = hash_new ();
1954 while (i < bfd_mips16_num_opcodes)
1956 const char *name = mips16_opcodes[i].name;
1958 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
1960 as_fatal (_("internal: can't hash `%s': %s"),
1961 mips16_opcodes[i].name, retval);
1964 if (mips16_opcodes[i].pinfo != INSN_MACRO
1965 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1966 != mips16_opcodes[i].match))
1968 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1969 mips16_opcodes[i].name, mips16_opcodes[i].args);
1972 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
1974 create_insn (&mips16_nop_insn, mips16_opcodes + i);
1975 mips16_nop_insn.fixed_p = 1;
1979 while (i < bfd_mips16_num_opcodes
1980 && strcmp (mips16_opcodes[i].name, name) == 0);
1984 as_fatal (_("Broken assembler. No assembly attempted."));
1986 /* We add all the general register names to the symbol table. This
1987 helps us detect invalid uses of them. */
1988 for (i = 0; reg_names[i].name; i++)
1989 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
1990 reg_names[i].num, /* & RNUM_MASK, */
1991 &zero_address_frag));
1993 for (i = 0; reg_names_n32n64[i].name; i++)
1994 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
1995 reg_names_n32n64[i].num, /* & RNUM_MASK, */
1996 &zero_address_frag));
1998 for (i = 0; reg_names_o32[i].name; i++)
1999 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
2000 reg_names_o32[i].num, /* & RNUM_MASK, */
2001 &zero_address_frag));
2003 mips_no_prev_insn ();
2006 mips_cprmask[0] = 0;
2007 mips_cprmask[1] = 0;
2008 mips_cprmask[2] = 0;
2009 mips_cprmask[3] = 0;
2011 /* set the default alignment for the text section (2**2) */
2012 record_alignment (text_section, 2);
2014 bfd_set_gp_size (stdoutput, g_switch_value);
2019 /* On a native system other than VxWorks, sections must be aligned
2020 to 16 byte boundaries. When configured for an embedded ELF
2021 target, we don't bother. */
2022 if (strncmp (TARGET_OS, "elf", 3) != 0
2023 && strncmp (TARGET_OS, "vxworks", 7) != 0)
2025 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
2026 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
2027 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
2030 /* Create a .reginfo section for register masks and a .mdebug
2031 section for debugging information. */
2039 subseg = now_subseg;
2041 /* The ABI says this section should be loaded so that the
2042 running program can access it. However, we don't load it
2043 if we are configured for an embedded target */
2044 flags = SEC_READONLY | SEC_DATA;
2045 if (strncmp (TARGET_OS, "elf", 3) != 0)
2046 flags |= SEC_ALLOC | SEC_LOAD;
2048 if (mips_abi != N64_ABI)
2050 sec = subseg_new (".reginfo", (subsegT) 0);
2052 bfd_set_section_flags (stdoutput, sec, flags);
2053 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
2055 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
2059 /* The 64-bit ABI uses a .MIPS.options section rather than
2060 .reginfo section. */
2061 sec = subseg_new (".MIPS.options", (subsegT) 0);
2062 bfd_set_section_flags (stdoutput, sec, flags);
2063 bfd_set_section_alignment (stdoutput, sec, 3);
2065 /* Set up the option header. */
2067 Elf_Internal_Options opthdr;
2070 opthdr.kind = ODK_REGINFO;
2071 opthdr.size = (sizeof (Elf_External_Options)
2072 + sizeof (Elf64_External_RegInfo));
2075 f = frag_more (sizeof (Elf_External_Options));
2076 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2077 (Elf_External_Options *) f);
2079 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2083 if (ECOFF_DEBUGGING)
2085 sec = subseg_new (".mdebug", (subsegT) 0);
2086 (void) bfd_set_section_flags (stdoutput, sec,
2087 SEC_HAS_CONTENTS | SEC_READONLY);
2088 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2090 else if (mips_flag_pdr)
2092 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2093 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2094 SEC_READONLY | SEC_RELOC
2096 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2099 subseg_set (seg, subseg);
2102 #endif /* OBJ_ELF */
2104 if (! ECOFF_DEBUGGING)
2107 if (mips_fix_vr4120)
2108 init_vr4120_conflicts ();
2114 if (! ECOFF_DEBUGGING)
2119 md_assemble (char *str)
2121 struct mips_cl_insn insn;
2122 bfd_reloc_code_real_type unused_reloc[3]
2123 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2125 imm_expr.X_op = O_absent;
2126 imm2_expr.X_op = O_absent;
2127 offset_expr.X_op = O_absent;
2128 imm_reloc[0] = BFD_RELOC_UNUSED;
2129 imm_reloc[1] = BFD_RELOC_UNUSED;
2130 imm_reloc[2] = BFD_RELOC_UNUSED;
2131 offset_reloc[0] = BFD_RELOC_UNUSED;
2132 offset_reloc[1] = BFD_RELOC_UNUSED;
2133 offset_reloc[2] = BFD_RELOC_UNUSED;
2135 if (mips_opts.mips16)
2136 mips16_ip (str, &insn);
2139 mips_ip (str, &insn);
2140 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2141 str, insn.insn_opcode));
2146 as_bad ("%s `%s'", insn_error, str);
2150 if (insn.insn_mo->pinfo == INSN_MACRO)
2153 if (mips_opts.mips16)
2154 mips16_macro (&insn);
2161 if (imm_expr.X_op != O_absent)
2162 append_insn (&insn, &imm_expr, imm_reloc);
2163 else if (offset_expr.X_op != O_absent)
2164 append_insn (&insn, &offset_expr, offset_reloc);
2166 append_insn (&insn, NULL, unused_reloc);
2170 /* Convenience functions for abstracting away the differences between
2171 MIPS16 and non-MIPS16 relocations. */
2173 static inline bfd_boolean
2174 mips16_reloc_p (bfd_reloc_code_real_type reloc)
2178 case BFD_RELOC_MIPS16_JMP:
2179 case BFD_RELOC_MIPS16_GPREL:
2180 case BFD_RELOC_MIPS16_GOT16:
2181 case BFD_RELOC_MIPS16_CALL16:
2182 case BFD_RELOC_MIPS16_HI16_S:
2183 case BFD_RELOC_MIPS16_HI16:
2184 case BFD_RELOC_MIPS16_LO16:
2192 static inline bfd_boolean
2193 got16_reloc_p (bfd_reloc_code_real_type reloc)
2195 return reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16;
2198 static inline bfd_boolean
2199 hi16_reloc_p (bfd_reloc_code_real_type reloc)
2201 return reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S;
2204 static inline bfd_boolean
2205 lo16_reloc_p (bfd_reloc_code_real_type reloc)
2207 return reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16;
2210 /* Return true if the given relocation might need a matching %lo().
2211 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2212 need a matching %lo() when applied to local symbols. */
2214 static inline bfd_boolean
2215 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
2217 return (HAVE_IN_PLACE_ADDENDS
2218 && (hi16_reloc_p (reloc)
2219 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2220 all GOT16 relocations evaluate to "G". */
2221 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
2224 /* Return the type of %lo() reloc needed by RELOC, given that
2225 reloc_needs_lo_p. */
2227 static inline bfd_reloc_code_real_type
2228 matching_lo_reloc (bfd_reloc_code_real_type reloc)
2230 return mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 : BFD_RELOC_LO16;
2233 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2236 static inline bfd_boolean
2237 fixup_has_matching_lo_p (fixS *fixp)
2239 return (fixp->fx_next != NULL
2240 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
2241 && fixp->fx_addsy == fixp->fx_next->fx_addsy
2242 && fixp->fx_offset == fixp->fx_next->fx_offset);
2245 /* This function returns true if modifying a register requires a
2249 reg_needs_delay (unsigned int reg)
2251 unsigned long prev_pinfo;
2253 prev_pinfo = history[0].insn_mo->pinfo;
2254 if (! mips_opts.noreorder
2255 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2256 && ! gpr_interlocks)
2257 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
2258 && ! cop_interlocks)))
2260 /* A load from a coprocessor or from memory. All load delays
2261 delay the use of general register rt for one instruction. */
2262 /* Itbl support may require additional care here. */
2263 know (prev_pinfo & INSN_WRITE_GPR_T);
2264 if (reg == EXTRACT_OPERAND (RT, history[0]))
2271 /* Move all labels in insn_labels to the current insertion point. */
2274 mips_move_labels (void)
2276 segment_info_type *si = seg_info (now_seg);
2277 struct insn_label_list *l;
2280 for (l = si->label_list; l != NULL; l = l->next)
2282 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
2283 symbol_set_frag (l->label, frag_now);
2284 val = (valueT) frag_now_fix ();
2285 /* mips16 text labels are stored as odd. */
2286 if (mips_opts.mips16)
2288 S_SET_VALUE (l->label, val);
2293 s_is_linkonce (symbolS *sym, segT from_seg)
2295 bfd_boolean linkonce = FALSE;
2296 segT symseg = S_GET_SEGMENT (sym);
2298 if (symseg != from_seg && !S_IS_LOCAL (sym))
2300 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
2303 /* The GNU toolchain uses an extension for ELF: a section
2304 beginning with the magic string .gnu.linkonce is a
2305 linkonce section. */
2306 if (strncmp (segment_name (symseg), ".gnu.linkonce",
2307 sizeof ".gnu.linkonce" - 1) == 0)
2314 /* Mark instruction labels in mips16 mode. This permits the linker to
2315 handle them specially, such as generating jalx instructions when
2316 needed. We also make them odd for the duration of the assembly, in
2317 order to generate the right sort of code. We will make them even
2318 in the adjust_symtab routine, while leaving them marked. This is
2319 convenient for the debugger and the disassembler. The linker knows
2320 to make them odd again. */
2323 mips16_mark_labels (void)
2325 segment_info_type *si = seg_info (now_seg);
2326 struct insn_label_list *l;
2328 if (!mips_opts.mips16)
2331 for (l = si->label_list; l != NULL; l = l->next)
2333 symbolS *label = l->label;
2335 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2337 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
2339 if ((S_GET_VALUE (label) & 1) == 0
2340 /* Don't adjust the address if the label is global or weak, or
2341 in a link-once section, since we'll be emitting symbol reloc
2342 references to it which will be patched up by the linker, and
2343 the final value of the symbol may or may not be MIPS16. */
2344 && ! S_IS_WEAK (label)
2345 && ! S_IS_EXTERNAL (label)
2346 && ! s_is_linkonce (label, now_seg))
2347 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
2351 /* End the current frag. Make it a variant frag and record the
2355 relax_close_frag (void)
2357 mips_macro_warning.first_frag = frag_now;
2358 frag_var (rs_machine_dependent, 0, 0,
2359 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
2360 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
2362 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
2363 mips_relax.first_fixup = 0;
2366 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2367 See the comment above RELAX_ENCODE for more details. */
2370 relax_start (symbolS *symbol)
2372 gas_assert (mips_relax.sequence == 0);
2373 mips_relax.sequence = 1;
2374 mips_relax.symbol = symbol;
2377 /* Start generating the second version of a relaxable sequence.
2378 See the comment above RELAX_ENCODE for more details. */
2383 gas_assert (mips_relax.sequence == 1);
2384 mips_relax.sequence = 2;
2387 /* End the current relaxable sequence. */
2392 gas_assert (mips_relax.sequence == 2);
2393 relax_close_frag ();
2394 mips_relax.sequence = 0;
2397 /* Return the mask of core registers that IP reads. */
2400 gpr_read_mask (const struct mips_cl_insn *ip)
2402 unsigned long pinfo, pinfo2;
2406 pinfo = ip->insn_mo->pinfo;
2407 pinfo2 = ip->insn_mo->pinfo2;
2408 if (mips_opts.mips16)
2410 if (pinfo & MIPS16_INSN_READ_X)
2411 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
2412 if (pinfo & MIPS16_INSN_READ_Y)
2413 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
2414 if (pinfo & MIPS16_INSN_READ_T)
2416 if (pinfo & MIPS16_INSN_READ_SP)
2418 if (pinfo & MIPS16_INSN_READ_31)
2420 if (pinfo & MIPS16_INSN_READ_Z)
2421 mask |= 1 << (mips16_to_32_reg_map
2422 [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]);
2423 if (pinfo & MIPS16_INSN_READ_GPR_X)
2424 mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
2428 if (pinfo2 & INSN2_READ_GPR_D)
2429 mask |= 1 << EXTRACT_OPERAND (RD, *ip);
2430 if (pinfo & INSN_READ_GPR_T)
2431 mask |= 1 << EXTRACT_OPERAND (RT, *ip);
2432 if (pinfo & INSN_READ_GPR_S)
2433 mask |= 1 << EXTRACT_OPERAND (RS, *ip);
2434 if (pinfo2 & INSN2_READ_GPR_Z)
2435 mask |= 1 << EXTRACT_OPERAND (RZ, *ip);
2440 /* Return the mask of core registers that IP writes. */
2443 gpr_write_mask (const struct mips_cl_insn *ip)
2445 unsigned long pinfo, pinfo2;
2449 pinfo = ip->insn_mo->pinfo;
2450 pinfo2 = ip->insn_mo->pinfo2;
2451 if (mips_opts.mips16)
2453 if (pinfo & MIPS16_INSN_WRITE_X)
2454 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
2455 if (pinfo & MIPS16_INSN_WRITE_Y)
2456 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
2457 if (pinfo & MIPS16_INSN_WRITE_Z)
2458 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)];
2459 if (pinfo & MIPS16_INSN_WRITE_T)
2461 if (pinfo & MIPS16_INSN_WRITE_SP)
2463 if (pinfo & MIPS16_INSN_WRITE_31)
2465 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2466 mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2470 if (pinfo & INSN_WRITE_GPR_D)
2471 mask |= 1 << EXTRACT_OPERAND (RD, *ip);
2472 if (pinfo & INSN_WRITE_GPR_T)
2473 mask |= 1 << EXTRACT_OPERAND (RT, *ip);
2474 if (pinfo & INSN_WRITE_GPR_31)
2476 if (pinfo2 & INSN2_WRITE_GPR_Z)
2477 mask |= 1 << EXTRACT_OPERAND (RZ, *ip);
2482 /* Return the mask of floating-point registers that IP reads. */
2485 fpr_read_mask (const struct mips_cl_insn *ip)
2487 unsigned long pinfo, pinfo2;
2491 pinfo = ip->insn_mo->pinfo;
2492 pinfo2 = ip->insn_mo->pinfo2;
2493 if (!mips_opts.mips16)
2495 if (pinfo & INSN_READ_FPR_S)
2496 mask |= 1 << EXTRACT_OPERAND (FS, *ip);
2497 if (pinfo & INSN_READ_FPR_T)
2498 mask |= 1 << EXTRACT_OPERAND (FT, *ip);
2499 if (pinfo & INSN_READ_FPR_R)
2500 mask |= 1 << EXTRACT_OPERAND (FR, *ip);
2501 if (pinfo2 & INSN2_READ_FPR_Z)
2502 mask |= 1 << EXTRACT_OPERAND (FZ, *ip);
2507 /* Return the mask of floating-point registers that IP writes. */
2510 fpr_write_mask (const struct mips_cl_insn *ip)
2512 unsigned long pinfo, pinfo2;
2516 pinfo = ip->insn_mo->pinfo;
2517 pinfo2 = ip->insn_mo->pinfo2;
2518 if (!mips_opts.mips16)
2520 if (pinfo & INSN_WRITE_FPR_D)
2521 mask |= 1 << EXTRACT_OPERAND (FD, *ip);
2522 if (pinfo & INSN_WRITE_FPR_S)
2523 mask |= 1 << EXTRACT_OPERAND (FS, *ip);
2524 if (pinfo & INSN_WRITE_FPR_T)
2525 mask |= 1 << EXTRACT_OPERAND (FT, *ip);
2526 if (pinfo2 & INSN2_WRITE_FPR_Z)
2527 mask |= 1 << EXTRACT_OPERAND (FZ, *ip);
2532 /* Classify an instruction according to the FIX_VR4120_* enumeration.
2533 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
2534 by VR4120 errata. */
2537 classify_vr4120_insn (const char *name)
2539 if (strncmp (name, "macc", 4) == 0)
2540 return FIX_VR4120_MACC;
2541 if (strncmp (name, "dmacc", 5) == 0)
2542 return FIX_VR4120_DMACC;
2543 if (strncmp (name, "mult", 4) == 0)
2544 return FIX_VR4120_MULT;
2545 if (strncmp (name, "dmult", 5) == 0)
2546 return FIX_VR4120_DMULT;
2547 if (strstr (name, "div"))
2548 return FIX_VR4120_DIV;
2549 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
2550 return FIX_VR4120_MTHILO;
2551 return NUM_FIX_VR4120_CLASSES;
2554 #define INSN_ERET 0x42000018
2555 #define INSN_DERET 0x4200001f
2557 /* Return the number of instructions that must separate INSN1 and INSN2,
2558 where INSN1 is the earlier instruction. Return the worst-case value
2559 for any INSN2 if INSN2 is null. */
2562 insns_between (const struct mips_cl_insn *insn1,
2563 const struct mips_cl_insn *insn2)
2565 unsigned long pinfo1, pinfo2;
2568 /* This function needs to know which pinfo flags are set for INSN2
2569 and which registers INSN2 uses. The former is stored in PINFO2 and
2570 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
2571 will have every flag set and INSN2_USES_GPR will always return true. */
2572 pinfo1 = insn1->insn_mo->pinfo;
2573 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
2575 #define INSN2_USES_GPR(REG) \
2576 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
2578 /* For most targets, write-after-read dependencies on the HI and LO
2579 registers must be separated by at least two instructions. */
2580 if (!hilo_interlocks)
2582 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
2584 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
2588 /* If we're working around r7000 errata, there must be two instructions
2589 between an mfhi or mflo and any instruction that uses the result. */
2590 if (mips_7000_hilo_fix
2591 && MF_HILO_INSN (pinfo1)
2592 && INSN2_USES_GPR (EXTRACT_OPERAND (RD, *insn1)))
2595 /* If we're working around 24K errata, one instruction is required
2596 if an ERET or DERET is followed by a branch instruction. */
2599 if (insn1->insn_opcode == INSN_ERET
2600 || insn1->insn_opcode == INSN_DERET)
2603 || insn2->insn_opcode == INSN_ERET
2604 || insn2->insn_opcode == INSN_DERET
2605 || (insn2->insn_mo->pinfo
2606 & (INSN_UNCOND_BRANCH_DELAY
2607 | INSN_COND_BRANCH_DELAY
2608 | INSN_COND_BRANCH_LIKELY)) != 0)
2613 /* If working around VR4120 errata, check for combinations that need
2614 a single intervening instruction. */
2615 if (mips_fix_vr4120)
2617 unsigned int class1, class2;
2619 class1 = classify_vr4120_insn (insn1->insn_mo->name);
2620 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
2624 class2 = classify_vr4120_insn (insn2->insn_mo->name);
2625 if (vr4120_conflicts[class1] & (1 << class2))
2630 if (!mips_opts.mips16)
2632 /* Check for GPR or coprocessor load delays. All such delays
2633 are on the RT register. */
2634 /* Itbl support may require additional care here. */
2635 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
2636 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
2638 know (pinfo1 & INSN_WRITE_GPR_T);
2639 if (INSN2_USES_GPR (EXTRACT_OPERAND (RT, *insn1)))
2643 /* Check for generic coprocessor hazards.
2645 This case is not handled very well. There is no special
2646 knowledge of CP0 handling, and the coprocessors other than
2647 the floating point unit are not distinguished at all. */
2648 /* Itbl support may require additional care here. FIXME!
2649 Need to modify this to include knowledge about
2650 user specified delays! */
2651 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
2652 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
2654 /* Handle cases where INSN1 writes to a known general coprocessor
2655 register. There must be a one instruction delay before INSN2
2656 if INSN2 reads that register, otherwise no delay is needed. */
2657 mask = fpr_write_mask (insn1);
2660 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
2665 /* Read-after-write dependencies on the control registers
2666 require a two-instruction gap. */
2667 if ((pinfo1 & INSN_WRITE_COND_CODE)
2668 && (pinfo2 & INSN_READ_COND_CODE))
2671 /* We don't know exactly what INSN1 does. If INSN2 is
2672 also a coprocessor instruction, assume there must be
2673 a one instruction gap. */
2674 if (pinfo2 & INSN_COP)
2679 /* Check for read-after-write dependencies on the coprocessor
2680 control registers in cases where INSN1 does not need a general
2681 coprocessor delay. This means that INSN1 is a floating point
2682 comparison instruction. */
2683 /* Itbl support may require additional care here. */
2684 else if (!cop_interlocks
2685 && (pinfo1 & INSN_WRITE_COND_CODE)
2686 && (pinfo2 & INSN_READ_COND_CODE))
2690 #undef INSN2_USES_GPR
2695 /* Return the number of nops that would be needed to work around the
2696 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2697 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
2698 that are contained within the first IGNORE instructions of HIST. */
2701 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
2702 const struct mips_cl_insn *insn)
2707 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2708 are not affected by the errata. */
2710 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
2711 || strcmp (insn->insn_mo->name, "mtlo") == 0
2712 || strcmp (insn->insn_mo->name, "mthi") == 0))
2715 /* Search for the first MFLO or MFHI. */
2716 for (i = 0; i < MAX_VR4130_NOPS; i++)
2717 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
2719 /* Extract the destination register. */
2720 mask = gpr_write_mask (&hist[i]);
2722 /* No nops are needed if INSN reads that register. */
2723 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
2726 /* ...or if any of the intervening instructions do. */
2727 for (j = 0; j < i; j++)
2728 if (gpr_read_mask (&hist[j]) & mask)
2732 return MAX_VR4130_NOPS - i;
2737 #define BASE_REG_EQ(INSN1, INSN2) \
2738 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
2739 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
2741 /* Return the minimum alignment for this store instruction. */
2744 fix_24k_align_to (const struct mips_opcode *mo)
2746 if (strcmp (mo->name, "sh") == 0)
2749 if (strcmp (mo->name, "swc1") == 0
2750 || strcmp (mo->name, "swc2") == 0
2751 || strcmp (mo->name, "sw") == 0
2752 || strcmp (mo->name, "sc") == 0
2753 || strcmp (mo->name, "s.s") == 0)
2756 if (strcmp (mo->name, "sdc1") == 0
2757 || strcmp (mo->name, "sdc2") == 0
2758 || strcmp (mo->name, "s.d") == 0)
2765 struct fix_24k_store_info
2767 /* Immediate offset, if any, for this store instruction. */
2769 /* Alignment required by this store instruction. */
2771 /* True for register offsets. */
2772 int register_offset;
2775 /* Comparison function used by qsort. */
2778 fix_24k_sort (const void *a, const void *b)
2780 const struct fix_24k_store_info *pos1 = a;
2781 const struct fix_24k_store_info *pos2 = b;
2783 return (pos1->off - pos2->off);
2786 /* INSN is a store instruction. Try to record the store information
2787 in STINFO. Return false if the information isn't known. */
2790 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
2791 const struct mips_cl_insn *insn)
2793 /* The instruction must have a known offset. */
2794 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
2797 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
2798 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
2802 /* Return the number of nops that would be needed to work around the 24k
2803 "lost data on stores during refill" errata if instruction INSN
2804 immediately followed the 2 instructions described by HIST.
2805 Ignore hazards that are contained within the first IGNORE
2806 instructions of HIST.
2808 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
2809 for the data cache refills and store data. The following describes
2810 the scenario where the store data could be lost.
2812 * A data cache miss, due to either a load or a store, causing fill
2813 data to be supplied by the memory subsystem
2814 * The first three doublewords of fill data are returned and written
2816 * A sequence of four stores occurs in consecutive cycles around the
2817 final doubleword of the fill:
2821 * Zero, One or more instructions
2824 The four stores A-D must be to different doublewords of the line that
2825 is being filled. The fourth instruction in the sequence above permits
2826 the fill of the final doubleword to be transferred from the FSB into
2827 the cache. In the sequence above, the stores may be either integer
2828 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
2829 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
2830 different doublewords on the line. If the floating point unit is
2831 running in 1:2 mode, it is not possible to create the sequence above
2832 using only floating point store instructions.
2834 In this case, the cache line being filled is incorrectly marked
2835 invalid, thereby losing the data from any store to the line that
2836 occurs between the original miss and the completion of the five
2837 cycle sequence shown above.
2839 The workarounds are:
2841 * Run the data cache in write-through mode.
2842 * Insert a non-store instruction between
2843 Store A and Store B or Store B and Store C. */
2846 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
2847 const struct mips_cl_insn *insn)
2849 struct fix_24k_store_info pos[3];
2850 int align, i, base_offset;
2855 /* If the previous instruction wasn't a store, there's nothing to
2857 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
2860 /* If the instructions after the previous one are unknown, we have
2861 to assume the worst. */
2865 /* Check whether we are dealing with three consecutive stores. */
2866 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
2867 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
2870 /* If we don't know the relationship between the store addresses,
2871 assume the worst. */
2872 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
2873 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
2876 if (!fix_24k_record_store_info (&pos[0], insn)
2877 || !fix_24k_record_store_info (&pos[1], &hist[0])
2878 || !fix_24k_record_store_info (&pos[2], &hist[1]))
2881 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
2883 /* Pick a value of ALIGN and X such that all offsets are adjusted by
2884 X bytes and such that the base register + X is known to be aligned
2887 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
2891 align = pos[0].align_to;
2892 base_offset = pos[0].off;
2893 for (i = 1; i < 3; i++)
2894 if (align < pos[i].align_to)
2896 align = pos[i].align_to;
2897 base_offset = pos[i].off;
2899 for (i = 0; i < 3; i++)
2900 pos[i].off -= base_offset;
2903 pos[0].off &= ~align + 1;
2904 pos[1].off &= ~align + 1;
2905 pos[2].off &= ~align + 1;
2907 /* If any two stores write to the same chunk, they also write to the
2908 same doubleword. The offsets are still sorted at this point. */
2909 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
2912 /* A range of at least 9 bytes is needed for the stores to be in
2913 non-overlapping doublewords. */
2914 if (pos[2].off - pos[0].off <= 8)
2917 if (pos[2].off - pos[1].off >= 24
2918 || pos[1].off - pos[0].off >= 24
2919 || pos[2].off - pos[0].off >= 32)
2925 /* Return the number of nops that would be needed if instruction INSN
2926 immediately followed the MAX_NOPS instructions given by HIST,
2927 where HIST[0] is the most recent instruction. Ignore hazards
2928 between INSN and the first IGNORE instructions in HIST.
2930 If INSN is null, return the worse-case number of nops for any
2934 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
2935 const struct mips_cl_insn *insn)
2937 int i, nops, tmp_nops;
2940 for (i = ignore; i < MAX_DELAY_NOPS; i++)
2942 tmp_nops = insns_between (hist + i, insn) - i;
2943 if (tmp_nops > nops)
2947 if (mips_fix_vr4130)
2949 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
2950 if (tmp_nops > nops)
2956 tmp_nops = nops_for_24k (ignore, hist, insn);
2957 if (tmp_nops > nops)
2964 /* The variable arguments provide NUM_INSNS extra instructions that
2965 might be added to HIST. Return the largest number of nops that
2966 would be needed after the extended sequence, ignoring hazards
2967 in the first IGNORE instructions. */
2970 nops_for_sequence (int num_insns, int ignore,
2971 const struct mips_cl_insn *hist, ...)
2974 struct mips_cl_insn buffer[MAX_NOPS];
2975 struct mips_cl_insn *cursor;
2978 va_start (args, hist);
2979 cursor = buffer + num_insns;
2980 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
2981 while (cursor > buffer)
2982 *--cursor = *va_arg (args, const struct mips_cl_insn *);
2984 nops = nops_for_insn (ignore, buffer, NULL);
2989 /* Like nops_for_insn, but if INSN is a branch, take into account the
2990 worst-case delay for the branch target. */
2993 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
2994 const struct mips_cl_insn *insn)
2998 nops = nops_for_insn (ignore, hist, insn);
2999 if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
3000 | INSN_COND_BRANCH_DELAY
3001 | INSN_COND_BRANCH_LIKELY))
3003 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
3004 hist, insn, NOP_INSN);
3005 if (tmp_nops > nops)
3008 else if (mips_opts.mips16
3009 && (insn->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
3010 | MIPS16_INSN_COND_BRANCH)))
3012 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
3013 if (tmp_nops > nops)
3019 /* Fix NOP issue: Replace nops by "or at,at,zero". */
3022 fix_loongson2f_nop (struct mips_cl_insn * ip)
3024 if (strcmp (ip->insn_mo->name, "nop") == 0)
3025 ip->insn_opcode = LOONGSON2F_NOP_INSN;
3028 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
3029 jr target pc &= 'hffff_ffff_cfff_ffff. */
3032 fix_loongson2f_jump (struct mips_cl_insn * ip)
3034 if (strcmp (ip->insn_mo->name, "j") == 0
3035 || strcmp (ip->insn_mo->name, "jr") == 0
3036 || strcmp (ip->insn_mo->name, "jalr") == 0)
3044 sreg = EXTRACT_OPERAND (RS, *ip);
3045 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
3048 ep.X_op = O_constant;
3049 ep.X_add_number = 0xcfff0000;
3050 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
3051 ep.X_add_number = 0xffff;
3052 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
3053 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
3058 fix_loongson2f (struct mips_cl_insn * ip)
3060 if (mips_fix_loongson2f_nop)
3061 fix_loongson2f_nop (ip);
3063 if (mips_fix_loongson2f_jump)
3064 fix_loongson2f_jump (ip);
3067 /* Output an instruction. IP is the instruction information.
3068 ADDRESS_EXPR is an operand of the instruction to be used with
3072 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
3073 bfd_reloc_code_real_type *reloc_type)
3075 unsigned long prev_pinfo, pinfo;
3076 unsigned long prev_pinfo2, pinfo2;
3077 relax_stateT prev_insn_frag_type = 0;
3078 bfd_boolean relaxed_branch = FALSE;
3079 segment_info_type *si = seg_info (now_seg);
3081 if (mips_fix_loongson2f)
3082 fix_loongson2f (ip);
3084 /* Mark instruction labels in mips16 mode. */
3085 mips16_mark_labels ();
3087 file_ase_mips16 |= mips_opts.mips16;
3089 prev_pinfo = history[0].insn_mo->pinfo;
3090 prev_pinfo2 = history[0].insn_mo->pinfo2;
3091 pinfo = ip->insn_mo->pinfo;
3092 pinfo2 = ip->insn_mo->pinfo2;
3094 if (address_expr == NULL)
3096 else if (*reloc_type <= BFD_RELOC_UNUSED
3097 && address_expr->X_op == O_constant)
3102 switch (*reloc_type)
3105 ip->insn_opcode |= address_expr->X_add_number;
3108 case BFD_RELOC_MIPS_HIGHEST:
3109 tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48;
3110 ip->insn_opcode |= tmp & 0xffff;
3113 case BFD_RELOC_MIPS_HIGHER:
3114 tmp = (address_expr->X_add_number + 0x80008000ull) >> 32;
3115 ip->insn_opcode |= tmp & 0xffff;
3118 case BFD_RELOC_HI16_S:
3119 tmp = (address_expr->X_add_number + 0x8000) >> 16;
3120 ip->insn_opcode |= tmp & 0xffff;
3123 case BFD_RELOC_HI16:
3124 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
3127 case BFD_RELOC_UNUSED:
3128 case BFD_RELOC_LO16:
3129 case BFD_RELOC_MIPS_GOT_DISP:
3130 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
3133 case BFD_RELOC_MIPS_JMP:
3134 if ((address_expr->X_add_number & 3) != 0)
3135 as_bad (_("jump to misaligned address (0x%lx)"),
3136 (unsigned long) address_expr->X_add_number);
3137 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
3141 case BFD_RELOC_MIPS16_JMP:
3142 if ((address_expr->X_add_number & 3) != 0)
3143 as_bad (_("jump to misaligned address (0x%lx)"),
3144 (unsigned long) address_expr->X_add_number);
3146 (((address_expr->X_add_number & 0x7c0000) << 3)
3147 | ((address_expr->X_add_number & 0xf800000) >> 7)
3148 | ((address_expr->X_add_number & 0x3fffc) >> 2));
3152 case BFD_RELOC_16_PCREL_S2:
3153 if ((address_expr->X_add_number & 3) != 0)
3154 as_bad (_("branch to misaligned address (0x%lx)"),
3155 (unsigned long) address_expr->X_add_number);
3156 if (mips_relax_branch)
3158 if ((address_expr->X_add_number + 0x20000) & ~0x3ffff)
3159 as_bad (_("branch address range overflow (0x%lx)"),
3160 (unsigned long) address_expr->X_add_number);
3161 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff;
3170 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
3172 /* There are a lot of optimizations we could do that we don't.
3173 In particular, we do not, in general, reorder instructions.
3174 If you use gcc with optimization, it will reorder
3175 instructions and generally do much more optimization then we
3176 do here; repeating all that work in the assembler would only
3177 benefit hand written assembly code, and does not seem worth
3179 int nops = (mips_optimize == 0
3180 ? nops_for_insn (0, history, NULL)
3181 : nops_for_insn_or_target (0, history, ip));
3185 unsigned long old_frag_offset;
3188 old_frag = frag_now;
3189 old_frag_offset = frag_now_fix ();
3191 for (i = 0; i < nops; i++)
3196 listing_prev_line ();
3197 /* We may be at the start of a variant frag. In case we
3198 are, make sure there is enough space for the frag
3199 after the frags created by listing_prev_line. The
3200 argument to frag_grow here must be at least as large
3201 as the argument to all other calls to frag_grow in
3202 this file. We don't have to worry about being in the
3203 middle of a variant frag, because the variants insert
3204 all needed nop instructions themselves. */
3208 mips_move_labels ();
3210 #ifndef NO_ECOFF_DEBUGGING
3211 if (ECOFF_DEBUGGING)
3212 ecoff_fix_loc (old_frag, old_frag_offset);
3216 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
3220 /* Work out how many nops in prev_nop_frag are needed by IP,
3221 ignoring hazards generated by the first prev_nop_frag_since
3223 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
3224 gas_assert (nops <= prev_nop_frag_holds);
3226 /* Enforce NOPS as a minimum. */
3227 if (nops > prev_nop_frag_required)
3228 prev_nop_frag_required = nops;
3230 if (prev_nop_frag_holds == prev_nop_frag_required)
3232 /* Settle for the current number of nops. Update the history
3233 accordingly (for the benefit of any future .set reorder code). */
3234 prev_nop_frag = NULL;
3235 insert_into_history (prev_nop_frag_since,
3236 prev_nop_frag_holds, NOP_INSN);
3240 /* Allow this instruction to replace one of the nops that was
3241 tentatively added to prev_nop_frag. */
3242 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
3243 prev_nop_frag_holds--;
3244 prev_nop_frag_since++;
3249 /* The value passed to dwarf2_emit_insn is the distance between
3250 the beginning of the current instruction and the address that
3251 should be recorded in the debug tables. For MIPS16 debug info
3252 we want to use ISA-encoded addresses, so we pass -1 for an
3253 address higher by one than the current. */
3254 dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0);
3257 /* Record the frag type before frag_var. */
3258 if (history[0].frag)
3259 prev_insn_frag_type = history[0].frag->fr_type;
3262 && *reloc_type == BFD_RELOC_16_PCREL_S2
3263 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
3264 || pinfo & INSN_COND_BRANCH_LIKELY)
3265 && mips_relax_branch
3266 /* Don't try branch relaxation within .set nomacro, or within
3267 .set noat if we use $at for PIC computations. If it turns
3268 out that the branch was out-of-range, we'll get an error. */
3269 && !mips_opts.warn_about_macros
3270 && (mips_opts.at || mips_pic == NO_PIC)
3271 /* Don't relax BPOSGE32/64 as they have no complementing branches. */
3272 && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP))
3273 && !mips_opts.mips16)
3275 relaxed_branch = TRUE;
3276 add_relaxed_insn (ip, (relaxed_branch_length
3278 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
3279 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1
3283 pinfo & INSN_UNCOND_BRANCH_DELAY,
3284 pinfo & INSN_COND_BRANCH_LIKELY,
3285 pinfo & INSN_WRITE_GPR_31,
3287 address_expr->X_add_symbol,
3288 address_expr->X_add_number);
3289 *reloc_type = BFD_RELOC_UNUSED;
3291 else if (*reloc_type > BFD_RELOC_UNUSED)
3293 /* We need to set up a variant frag. */
3294 gas_assert (mips_opts.mips16 && address_expr != NULL);
3295 add_relaxed_insn (ip, 4, 0,
3297 (*reloc_type - BFD_RELOC_UNUSED,
3298 mips16_small, mips16_ext,
3299 prev_pinfo & INSN_UNCOND_BRANCH_DELAY,
3300 history[0].mips16_absolute_jump_p),
3301 make_expr_symbol (address_expr), 0);
3303 else if (mips_opts.mips16
3305 && *reloc_type != BFD_RELOC_MIPS16_JMP)
3307 if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0)
3308 /* Make sure there is enough room to swap this instruction with
3309 a following jump instruction. */
3311 add_fixed_insn (ip);
3315 if (mips_opts.mips16
3316 && mips_opts.noreorder
3317 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
3318 as_warn (_("extended instruction in delay slot"));
3320 if (mips_relax.sequence)
3322 /* If we've reached the end of this frag, turn it into a variant
3323 frag and record the information for the instructions we've
3325 if (frag_room () < 4)
3326 relax_close_frag ();
3327 mips_relax.sizes[mips_relax.sequence - 1] += 4;
3330 if (mips_relax.sequence != 2)
3331 mips_macro_warning.sizes[0] += 4;
3332 if (mips_relax.sequence != 1)
3333 mips_macro_warning.sizes[1] += 4;
3335 if (mips_opts.mips16)
3338 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
3340 add_fixed_insn (ip);
3343 if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED)
3346 && *reloc_type < BFD_RELOC_UNUSED)
3349 reloc_howto_type *howto;
3352 /* In a compound relocation, it is the final (outermost)
3353 operator that determines the relocated field. */
3354 for (i = 1; i < 3; i++)
3355 if (reloc_type[i] == BFD_RELOC_UNUSED)
3358 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
3361 /* To reproduce this failure try assembling gas/testsuites/
3362 gas/mips/mips16-intermix.s with a mips-ecoff targeted
3364 as_bad (_("Unsupported MIPS relocation number %d"), reloc_type[i - 1]);
3365 howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16);
3368 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
3369 bfd_get_reloc_size (howto),
3371 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
3374 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
3375 if (reloc_type[0] == BFD_RELOC_MIPS16_JMP
3376 && ip->fixp[0]->fx_addsy)
3377 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
3379 /* These relocations can have an addend that won't fit in
3380 4 octets for 64bit assembly. */
3382 && ! howto->partial_inplace
3383 && (reloc_type[0] == BFD_RELOC_16
3384 || reloc_type[0] == BFD_RELOC_32
3385 || reloc_type[0] == BFD_RELOC_MIPS_JMP
3386 || reloc_type[0] == BFD_RELOC_GPREL16
3387 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
3388 || reloc_type[0] == BFD_RELOC_GPREL32
3389 || reloc_type[0] == BFD_RELOC_64
3390 || reloc_type[0] == BFD_RELOC_CTOR
3391 || reloc_type[0] == BFD_RELOC_MIPS_SUB
3392 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
3393 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
3394 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
3395 || reloc_type[0] == BFD_RELOC_MIPS_REL16
3396 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
3397 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
3398 || hi16_reloc_p (reloc_type[0])
3399 || lo16_reloc_p (reloc_type[0])))
3400 ip->fixp[0]->fx_no_overflow = 1;
3402 if (mips_relax.sequence)
3404 if (mips_relax.first_fixup == 0)
3405 mips_relax.first_fixup = ip->fixp[0];
3407 else if (reloc_needs_lo_p (*reloc_type))
3409 struct mips_hi_fixup *hi_fixup;
3411 /* Reuse the last entry if it already has a matching %lo. */
3412 hi_fixup = mips_hi_fixup_list;
3414 || !fixup_has_matching_lo_p (hi_fixup->fixp))
3416 hi_fixup = ((struct mips_hi_fixup *)
3417 xmalloc (sizeof (struct mips_hi_fixup)));
3418 hi_fixup->next = mips_hi_fixup_list;
3419 mips_hi_fixup_list = hi_fixup;
3421 hi_fixup->fixp = ip->fixp[0];
3422 hi_fixup->seg = now_seg;
3425 /* Add fixups for the second and third relocations, if given.
3426 Note that the ABI allows the second relocation to be
3427 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
3428 moment we only use RSS_UNDEF, but we could add support
3429 for the others if it ever becomes necessary. */
3430 for (i = 1; i < 3; i++)
3431 if (reloc_type[i] != BFD_RELOC_UNUSED)
3433 ip->fixp[i] = fix_new (ip->frag, ip->where,
3434 ip->fixp[0]->fx_size, NULL, 0,
3435 FALSE, reloc_type[i]);
3437 /* Use fx_tcbit to mark compound relocs. */
3438 ip->fixp[0]->fx_tcbit = 1;
3439 ip->fixp[i]->fx_tcbit = 1;
3445 /* Update the register mask information. */
3446 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
3447 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
3449 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
3451 /* Filling the branch delay slot is more complex. We try to
3452 switch the branch with the previous instruction, which we can
3453 do if the previous instruction does not set up a condition
3454 that the branch tests and if the branch is not itself the
3455 target of any branch. */
3456 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
3457 || (pinfo & INSN_COND_BRANCH_DELAY))
3459 if (mips_optimize < 2
3460 /* If we have seen .set volatile or .set nomove, don't
3462 || mips_opts.nomove != 0
3463 /* We can't swap if the previous instruction's position
3465 || history[0].fixed_p
3466 /* If the previous previous insn was in a .set
3467 noreorder, we can't swap. Actually, the MIPS
3468 assembler will swap in this situation. However, gcc
3469 configured -with-gnu-as will generate code like
3475 in which we can not swap the bne and INSN. If gcc is
3476 not configured -with-gnu-as, it does not output the
3478 || history[1].noreorder_p
3479 /* If the branch is itself the target of a branch, we
3480 can not swap. We cheat on this; all we check for is
3481 whether there is a label on this instruction. If
3482 there are any branches to anything other than a
3483 label, users must use .set noreorder. */
3484 || si->label_list != NULL
3485 /* If the previous instruction is in a variant frag
3486 other than this branch's one, we cannot do the swap.
3487 This does not apply to the mips16, which uses variant
3488 frags for different purposes. */
3489 || (! mips_opts.mips16
3490 && prev_insn_frag_type == rs_machine_dependent)
3491 /* Check for conflicts between the branch and the instructions
3492 before the candidate delay slot. */
3493 || nops_for_insn (0, history + 1, ip) > 0
3494 /* Check for conflicts between the swapped sequence and the
3495 target of the branch. */
3496 || nops_for_sequence (2, 0, history + 1, ip, history) > 0
3497 /* We do not swap with a trap instruction, since it
3498 complicates trap handlers to have the trap
3499 instruction be in a delay slot. */
3500 || (prev_pinfo & INSN_TRAP)
3501 /* If the branch reads a register that the previous
3502 instruction sets, we can not swap. */
3503 || (gpr_read_mask (ip) & gpr_write_mask (&history[0])) != 0
3504 /* If the branch writes a register that the previous
3505 instruction sets, we can not swap. */
3506 || (gpr_write_mask (ip) & gpr_write_mask (&history[0])) != 0
3507 /* If the branch writes a register that the previous
3508 instruction reads, we can not swap. */
3509 || (gpr_write_mask (ip) & gpr_read_mask (&history[0])) != 0
3510 /* If one instruction sets a condition code and the
3511 other one uses a condition code, we can not swap. */
3512 || ((pinfo & INSN_READ_COND_CODE)
3513 && (prev_pinfo & INSN_WRITE_COND_CODE))
3514 || ((pinfo & INSN_WRITE_COND_CODE)
3515 && (prev_pinfo & INSN_READ_COND_CODE))
3516 /* If the previous instruction uses the PC, we can not
3518 || (mips_opts.mips16
3519 && (prev_pinfo & MIPS16_INSN_READ_PC))
3520 /* If the previous instruction had a fixup in mips16
3521 mode, we can not swap. This normally means that the
3522 previous instruction was a 4 byte branch anyhow. */
3523 || (mips_opts.mips16 && history[0].fixp[0])
3524 /* If the previous instruction is a sync, sync.l, or
3525 sync.p, we can not swap. */
3526 || (prev_pinfo & INSN_SYNC)
3527 /* If the previous instruction is an ERET or
3528 DERET, avoid the swap. */
3529 || (history[0].insn_opcode == INSN_ERET)
3530 || (history[0].insn_opcode == INSN_DERET))
3532 if (mips_opts.mips16
3533 && (pinfo & INSN_UNCOND_BRANCH_DELAY)
3534 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))
3535 && ISA_SUPPORTS_MIPS16E)
3537 /* Convert MIPS16 jr/jalr into a "compact" jump. */
3538 ip->insn_opcode |= 0x0080;
3540 insert_into_history (0, 1, ip);
3544 /* We could do even better for unconditional branches to
3545 portions of this object file; we could pick up the
3546 instruction at the destination, put it in the delay
3547 slot, and bump the destination address. */
3548 insert_into_history (0, 1, ip);
3552 if (mips_relax.sequence)
3553 mips_relax.sizes[mips_relax.sequence - 1] += 4;
3557 /* It looks like we can actually do the swap. */
3558 struct mips_cl_insn delay = history[0];
3559 if (mips_opts.mips16)
3561 know (delay.frag == ip->frag);
3562 move_insn (ip, delay.frag, delay.where);
3563 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
3565 else if (relaxed_branch)
3567 /* Add the delay slot instruction to the end of the
3568 current frag and shrink the fixed part of the
3569 original frag. If the branch occupies the tail of
3570 the latter, move it backwards to cover the gap. */
3571 delay.frag->fr_fix -= 4;
3572 if (delay.frag == ip->frag)
3573 move_insn (ip, ip->frag, ip->where - 4);
3574 add_fixed_insn (&delay);
3578 move_insn (&delay, ip->frag, ip->where);
3579 move_insn (ip, history[0].frag, history[0].where);
3583 insert_into_history (0, 1, &delay);
3586 /* If that was an unconditional branch, forget the previous
3587 insn information. */
3588 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
3590 mips_no_prev_insn ();
3593 else if (pinfo & INSN_COND_BRANCH_LIKELY)
3595 /* We don't yet optimize a branch likely. What we should do
3596 is look at the target, copy the instruction found there
3597 into the delay slot, and increment the branch to jump to
3598 the next instruction. */
3599 insert_into_history (0, 1, ip);
3603 insert_into_history (0, 1, ip);
3606 insert_into_history (0, 1, ip);
3608 /* We just output an insn, so the next one doesn't have a label. */
3609 mips_clear_insn_labels ();
3612 /* Forget that there was any previous instruction or label. */
3615 mips_no_prev_insn (void)
3617 prev_nop_frag = NULL;
3618 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
3619 mips_clear_insn_labels ();
3622 /* This function must be called before we emit something other than
3623 instructions. It is like mips_no_prev_insn except that it inserts
3624 any NOPS that might be needed by previous instructions. */
3627 mips_emit_delays (void)
3629 if (! mips_opts.noreorder)
3631 int nops = nops_for_insn (0, history, NULL);
3635 add_fixed_insn (NOP_INSN);
3636 mips_move_labels ();
3639 mips_no_prev_insn ();
3642 /* Start a (possibly nested) noreorder block. */
3645 start_noreorder (void)
3647 if (mips_opts.noreorder == 0)
3652 /* None of the instructions before the .set noreorder can be moved. */
3653 for (i = 0; i < ARRAY_SIZE (history); i++)
3654 history[i].fixed_p = 1;
3656 /* Insert any nops that might be needed between the .set noreorder
3657 block and the previous instructions. We will later remove any
3658 nops that turn out not to be needed. */
3659 nops = nops_for_insn (0, history, NULL);
3662 if (mips_optimize != 0)
3664 /* Record the frag which holds the nop instructions, so
3665 that we can remove them if we don't need them. */
3666 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
3667 prev_nop_frag = frag_now;
3668 prev_nop_frag_holds = nops;
3669 prev_nop_frag_required = 0;
3670 prev_nop_frag_since = 0;
3673 for (; nops > 0; --nops)
3674 add_fixed_insn (NOP_INSN);
3676 /* Move on to a new frag, so that it is safe to simply
3677 decrease the size of prev_nop_frag. */
3678 frag_wane (frag_now);
3680 mips_move_labels ();
3682 mips16_mark_labels ();
3683 mips_clear_insn_labels ();
3685 mips_opts.noreorder++;
3686 mips_any_noreorder = 1;
3689 /* End a nested noreorder block. */
3692 end_noreorder (void)
3695 mips_opts.noreorder--;
3696 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
3698 /* Commit to inserting prev_nop_frag_required nops and go back to
3699 handling nop insertion the .set reorder way. */
3700 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
3701 * (mips_opts.mips16 ? 2 : 4));
3702 insert_into_history (prev_nop_frag_since,
3703 prev_nop_frag_required, NOP_INSN);
3704 prev_nop_frag = NULL;
3708 /* Set up global variables for the start of a new macro. */
3713 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
3714 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
3715 && (history[0].insn_mo->pinfo
3716 & (INSN_UNCOND_BRANCH_DELAY
3717 | INSN_COND_BRANCH_DELAY
3718 | INSN_COND_BRANCH_LIKELY)) != 0);
3721 /* Given that a macro is longer than 4 bytes, return the appropriate warning
3722 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
3723 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
3726 macro_warning (relax_substateT subtype)
3728 if (subtype & RELAX_DELAY_SLOT)
3729 return _("Macro instruction expanded into multiple instructions"
3730 " in a branch delay slot");
3731 else if (subtype & RELAX_NOMACRO)
3732 return _("Macro instruction expanded into multiple instructions");
3737 /* Finish up a macro. Emit warnings as appropriate. */
3742 if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4)
3744 relax_substateT subtype;
3746 /* Set up the relaxation warning flags. */
3748 if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0])
3749 subtype |= RELAX_SECOND_LONGER;
3750 if (mips_opts.warn_about_macros)
3751 subtype |= RELAX_NOMACRO;
3752 if (mips_macro_warning.delay_slot_p)
3753 subtype |= RELAX_DELAY_SLOT;
3755 if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4)
3757 /* Either the macro has a single implementation or both
3758 implementations are longer than 4 bytes. Emit the
3760 const char *msg = macro_warning (subtype);
3762 as_warn ("%s", msg);
3766 /* One implementation might need a warning but the other
3767 definitely doesn't. */
3768 mips_macro_warning.first_frag->fr_subtype |= subtype;
3773 /* Read a macro's relocation codes from *ARGS and store them in *R.
3774 The first argument in *ARGS will be either the code for a single
3775 relocation or -1 followed by the three codes that make up a
3776 composite relocation. */
3779 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
3783 next = va_arg (*args, int);
3785 r[0] = (bfd_reloc_code_real_type) next;
3787 for (i = 0; i < 3; i++)
3788 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
3791 /* Build an instruction created by a macro expansion. This is passed
3792 a pointer to the count of instructions created so far, an
3793 expression, the name of the instruction to build, an operand format
3794 string, and corresponding arguments. */
3797 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
3799 const struct mips_opcode *mo;
3800 struct mips_cl_insn insn;
3801 bfd_reloc_code_real_type r[3];
3804 va_start (args, fmt);
3806 if (mips_opts.mips16)
3808 mips16_macro_build (ep, name, fmt, &args);
3813 r[0] = BFD_RELOC_UNUSED;
3814 r[1] = BFD_RELOC_UNUSED;
3815 r[2] = BFD_RELOC_UNUSED;
3816 mo = (struct mips_opcode *) hash_find (op_hash, name);
3818 gas_assert (strcmp (name, mo->name) == 0);
3822 /* Search until we get a match for NAME. It is assumed here that
3823 macros will never generate MDMX, MIPS-3D, or MT instructions. */
3824 if (strcmp (fmt, mo->args) == 0
3825 && mo->pinfo != INSN_MACRO
3826 && is_opcode_valid (mo))
3830 gas_assert (mo->name);
3831 gas_assert (strcmp (name, mo->name) == 0);
3834 create_insn (&insn, mo);
3852 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
3857 /* Note that in the macro case, these arguments are already
3858 in MSB form. (When handling the instruction in the
3859 non-macro case, these arguments are sizes from which
3860 MSB values must be calculated.) */
3861 INSERT_OPERAND (INSMSB, insn, va_arg (args, int));
3867 /* Note that in the macro case, these arguments are already
3868 in MSBD form. (When handling the instruction in the
3869 non-macro case, these arguments are sizes from which
3870 MSBD values must be calculated.) */
3871 INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int));
3875 INSERT_OPERAND (SEQI, insn, va_arg (args, int));
3884 INSERT_OPERAND (BP, insn, va_arg (args, int));
3890 INSERT_OPERAND (RT, insn, va_arg (args, int));
3894 INSERT_OPERAND (CODE, insn, va_arg (args, int));
3899 INSERT_OPERAND (FT, insn, va_arg (args, int));
3905 INSERT_OPERAND (RD, insn, va_arg (args, int));
3910 int tmp = va_arg (args, int);
3912 INSERT_OPERAND (RT, insn, tmp);
3913 INSERT_OPERAND (RD, insn, tmp);
3919 INSERT_OPERAND (FS, insn, va_arg (args, int));
3926 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
3930 INSERT_OPERAND (FD, insn, va_arg (args, int));
3934 INSERT_OPERAND (CODE20, insn, va_arg (args, int));
3938 INSERT_OPERAND (CODE19, insn, va_arg (args, int));
3942 INSERT_OPERAND (CODE2, insn, va_arg (args, int));
3949 INSERT_OPERAND (RS, insn, va_arg (args, int));
3954 macro_read_relocs (&args, r);
3955 gas_assert (*r == BFD_RELOC_GPREL16
3956 || *r == BFD_RELOC_MIPS_HIGHER
3957 || *r == BFD_RELOC_HI16_S
3958 || *r == BFD_RELOC_LO16
3959 || *r == BFD_RELOC_MIPS_GOT_OFST);
3963 macro_read_relocs (&args, r);
3967 macro_read_relocs (&args, r);
3968 gas_assert (ep != NULL
3969 && (ep->X_op == O_constant
3970 || (ep->X_op == O_symbol
3971 && (*r == BFD_RELOC_MIPS_HIGHEST
3972 || *r == BFD_RELOC_HI16_S
3973 || *r == BFD_RELOC_HI16
3974 || *r == BFD_RELOC_GPREL16
3975 || *r == BFD_RELOC_MIPS_GOT_HI16
3976 || *r == BFD_RELOC_MIPS_CALL_HI16))));
3980 gas_assert (ep != NULL);
3983 * This allows macro() to pass an immediate expression for
3984 * creating short branches without creating a symbol.
3986 * We don't allow branch relaxation for these branches, as
3987 * they should only appear in ".set nomacro" anyway.
3989 if (ep->X_op == O_constant)
3991 if ((ep->X_add_number & 3) != 0)
3992 as_bad (_("branch to misaligned address (0x%lx)"),
3993 (unsigned long) ep->X_add_number);
3994 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
3995 as_bad (_("branch address range overflow (0x%lx)"),
3996 (unsigned long) ep->X_add_number);
3997 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
4001 *r = BFD_RELOC_16_PCREL_S2;
4005 gas_assert (ep != NULL);
4006 *r = BFD_RELOC_MIPS_JMP;
4010 INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long));
4014 INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long));
4023 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
4025 append_insn (&insn, ep, r);
4029 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
4032 struct mips_opcode *mo;
4033 struct mips_cl_insn insn;
4034 bfd_reloc_code_real_type r[3]
4035 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
4037 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
4039 gas_assert (strcmp (name, mo->name) == 0);
4041 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
4044 gas_assert (mo->name);
4045 gas_assert (strcmp (name, mo->name) == 0);
4048 create_insn (&insn, mo);
4066 MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int));
4071 MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int));
4075 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int));
4079 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int));
4089 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int));
4096 regno = va_arg (*args, int);
4097 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
4098 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
4119 gas_assert (ep != NULL);
4121 if (ep->X_op != O_constant)
4122 *r = (int) BFD_RELOC_UNUSED + c;
4125 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
4126 FALSE, &insn.insn_opcode, &insn.use_extend,
4129 *r = BFD_RELOC_UNUSED;
4135 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int));
4142 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
4144 append_insn (&insn, ep, r);
4148 * Sign-extend 32-bit mode constants that have bit 31 set and all
4149 * higher bits unset.
4152 normalize_constant_expr (expressionS *ex)
4154 if (ex->X_op == O_constant
4155 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
4156 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
4161 * Sign-extend 32-bit mode address offsets that have bit 31 set and
4162 * all higher bits unset.
4165 normalize_address_expr (expressionS *ex)
4167 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
4168 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
4169 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
4170 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
4175 * Generate a "jalr" instruction with a relocation hint to the called
4176 * function. This occurs in NewABI PIC code.
4179 macro_build_jalr (expressionS *ep)
4183 if (MIPS_JALR_HINT_P (ep))
4188 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
4189 if (MIPS_JALR_HINT_P (ep))
4190 fix_new_exp (frag_now, f - frag_now->fr_literal,
4191 4, ep, FALSE, BFD_RELOC_MIPS_JALR);
4195 * Generate a "lui" instruction.
4198 macro_build_lui (expressionS *ep, int regnum)
4200 expressionS high_expr;
4201 const struct mips_opcode *mo;
4202 struct mips_cl_insn insn;
4203 bfd_reloc_code_real_type r[3]
4204 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
4205 const char *name = "lui";
4206 const char *fmt = "t,u";
4208 gas_assert (! mips_opts.mips16);
4212 if (high_expr.X_op == O_constant)
4214 /* We can compute the instruction now without a relocation entry. */
4215 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
4217 *r = BFD_RELOC_UNUSED;
4221 gas_assert (ep->X_op == O_symbol);
4222 /* _gp_disp is a special case, used from s_cpload.
4223 __gnu_local_gp is used if mips_no_shared. */
4224 gas_assert (mips_pic == NO_PIC
4226 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
4227 || (! mips_in_shared
4228 && strcmp (S_GET_NAME (ep->X_add_symbol),
4229 "__gnu_local_gp") == 0));
4230 *r = BFD_RELOC_HI16_S;
4233 mo = hash_find (op_hash, name);
4234 gas_assert (strcmp (name, mo->name) == 0);
4235 gas_assert (strcmp (fmt, mo->args) == 0);
4236 create_insn (&insn, mo);
4238 insn.insn_opcode = insn.insn_mo->match;
4239 INSERT_OPERAND (RT, insn, regnum);
4240 if (*r == BFD_RELOC_UNUSED)
4242 insn.insn_opcode |= high_expr.X_add_number;
4243 append_insn (&insn, NULL, r);
4246 append_insn (&insn, &high_expr, r);
4249 /* Generate a sequence of instructions to do a load or store from a constant
4250 offset off of a base register (breg) into/from a target register (treg),
4251 using AT if necessary. */
4253 macro_build_ldst_constoffset (expressionS *ep, const char *op,
4254 int treg, int breg, int dbl)
4256 gas_assert (ep->X_op == O_constant);
4258 /* Sign-extending 32-bit constants makes their handling easier. */
4260 normalize_constant_expr (ep);
4262 /* Right now, this routine can only handle signed 32-bit constants. */
4263 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
4264 as_warn (_("operand overflow"));
4266 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
4268 /* Signed 16-bit offset will fit in the op. Easy! */
4269 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
4273 /* 32-bit offset, need multiple instructions and AT, like:
4274 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
4275 addu $tempreg,$tempreg,$breg
4276 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
4277 to handle the complete offset. */
4278 macro_build_lui (ep, AT);
4279 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
4280 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
4283 as_bad (_("Macro used $at after \".set noat\""));
4288 * Generates code to set the $at register to true (one)
4289 * if reg is less than the immediate expression.
4292 set_at (int reg, int unsignedp)
4294 if (imm_expr.X_op == O_constant
4295 && imm_expr.X_add_number >= -0x8000
4296 && imm_expr.X_add_number < 0x8000)
4297 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
4298 AT, reg, BFD_RELOC_LO16);
4301 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4302 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
4306 /* Warn if an expression is not a constant. */
4309 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
4311 if (ex->X_op == O_big)
4312 as_bad (_("unsupported large constant"));
4313 else if (ex->X_op != O_constant)
4314 as_bad (_("Instruction %s requires absolute expression"),
4317 if (HAVE_32BIT_GPRS)
4318 normalize_constant_expr (ex);
4321 /* Count the leading zeroes by performing a binary chop. This is a
4322 bulky bit of source, but performance is a LOT better for the
4323 majority of values than a simple loop to count the bits:
4324 for (lcnt = 0; (lcnt < 32); lcnt++)
4325 if ((v) & (1 << (31 - lcnt)))
4327 However it is not code size friendly, and the gain will drop a bit
4328 on certain cached systems.
4330 #define COUNT_TOP_ZEROES(v) \
4331 (((v) & ~0xffff) == 0 \
4332 ? ((v) & ~0xff) == 0 \
4333 ? ((v) & ~0xf) == 0 \
4334 ? ((v) & ~0x3) == 0 \
4335 ? ((v) & ~0x1) == 0 \
4340 : ((v) & ~0x7) == 0 \
4343 : ((v) & ~0x3f) == 0 \
4344 ? ((v) & ~0x1f) == 0 \
4347 : ((v) & ~0x7f) == 0 \
4350 : ((v) & ~0xfff) == 0 \
4351 ? ((v) & ~0x3ff) == 0 \
4352 ? ((v) & ~0x1ff) == 0 \
4355 : ((v) & ~0x7ff) == 0 \
4358 : ((v) & ~0x3fff) == 0 \
4359 ? ((v) & ~0x1fff) == 0 \
4362 : ((v) & ~0x7fff) == 0 \
4365 : ((v) & ~0xffffff) == 0 \
4366 ? ((v) & ~0xfffff) == 0 \
4367 ? ((v) & ~0x3ffff) == 0 \
4368 ? ((v) & ~0x1ffff) == 0 \
4371 : ((v) & ~0x7ffff) == 0 \
4374 : ((v) & ~0x3fffff) == 0 \
4375 ? ((v) & ~0x1fffff) == 0 \
4378 : ((v) & ~0x7fffff) == 0 \
4381 : ((v) & ~0xfffffff) == 0 \
4382 ? ((v) & ~0x3ffffff) == 0 \
4383 ? ((v) & ~0x1ffffff) == 0 \
4386 : ((v) & ~0x7ffffff) == 0 \
4389 : ((v) & ~0x3fffffff) == 0 \
4390 ? ((v) & ~0x1fffffff) == 0 \
4393 : ((v) & ~0x7fffffff) == 0 \
4398 * This routine generates the least number of instructions necessary to load
4399 * an absolute expression value into a register.
4402 load_register (int reg, expressionS *ep, int dbl)
4405 expressionS hi32, lo32;
4407 if (ep->X_op != O_big)
4409 gas_assert (ep->X_op == O_constant);
4411 /* Sign-extending 32-bit constants makes their handling easier. */
4413 normalize_constant_expr (ep);
4415 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
4417 /* We can handle 16 bit signed values with an addiu to
4418 $zero. No need to ever use daddiu here, since $zero and
4419 the result are always correct in 32 bit mode. */
4420 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4423 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
4425 /* We can handle 16 bit unsigned values with an ori to
4427 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
4430 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
4432 /* 32 bit values require an lui. */
4433 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16);
4434 if ((ep->X_add_number & 0xffff) != 0)
4435 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
4440 /* The value is larger than 32 bits. */
4442 if (!dbl || HAVE_32BIT_GPRS)
4446 sprintf_vma (value, ep->X_add_number);
4447 as_bad (_("Number (0x%s) larger than 32 bits"), value);
4448 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4452 if (ep->X_op != O_big)
4455 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
4456 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
4457 hi32.X_add_number &= 0xffffffff;
4459 lo32.X_add_number &= 0xffffffff;
4463 gas_assert (ep->X_add_number > 2);
4464 if (ep->X_add_number == 3)
4465 generic_bignum[3] = 0;
4466 else if (ep->X_add_number > 4)
4467 as_bad (_("Number larger than 64 bits"));
4468 lo32.X_op = O_constant;
4469 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
4470 hi32.X_op = O_constant;
4471 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
4474 if (hi32.X_add_number == 0)
4479 unsigned long hi, lo;
4481 if (hi32.X_add_number == (offsetT) 0xffffffff)
4483 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
4485 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4488 if (lo32.X_add_number & 0x80000000)
4490 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
4491 if (lo32.X_add_number & 0xffff)
4492 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
4497 /* Check for 16bit shifted constant. We know that hi32 is
4498 non-zero, so start the mask on the first bit of the hi32
4503 unsigned long himask, lomask;
4507 himask = 0xffff >> (32 - shift);
4508 lomask = (0xffff << shift) & 0xffffffff;
4512 himask = 0xffff << (shift - 32);
4515 if ((hi32.X_add_number & ~(offsetT) himask) == 0
4516 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
4520 tmp.X_op = O_constant;
4522 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
4523 | (lo32.X_add_number >> shift));
4525 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
4526 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
4527 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<",
4528 reg, reg, (shift >= 32) ? shift - 32 : shift);
4533 while (shift <= (64 - 16));
4535 /* Find the bit number of the lowest one bit, and store the
4536 shifted value in hi/lo. */
4537 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
4538 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
4542 while ((lo & 1) == 0)
4547 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
4553 while ((hi & 1) == 0)
4562 /* Optimize if the shifted value is a (power of 2) - 1. */
4563 if ((hi == 0 && ((lo + 1) & lo) == 0)
4564 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
4566 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
4571 /* This instruction will set the register to be all
4573 tmp.X_op = O_constant;
4574 tmp.X_add_number = (offsetT) -1;
4575 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4579 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<",
4580 reg, reg, (bit >= 32) ? bit - 32 : bit);
4582 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<",
4583 reg, reg, (shift >= 32) ? shift - 32 : shift);
4588 /* Sign extend hi32 before calling load_register, because we can
4589 generally get better code when we load a sign extended value. */
4590 if ((hi32.X_add_number & 0x80000000) != 0)
4591 hi32.X_add_number |= ~(offsetT) 0xffffffff;
4592 load_register (reg, &hi32, 0);
4595 if ((lo32.X_add_number & 0xffff0000) == 0)
4599 macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0);
4607 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
4609 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
4610 macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0);
4616 macro_build (NULL, "dsll", "d,w,<", reg, freg, 16);
4620 mid16.X_add_number >>= 16;
4621 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
4622 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4625 if ((lo32.X_add_number & 0xffff) != 0)
4626 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
4630 load_delay_nop (void)
4632 if (!gpr_interlocks)
4633 macro_build (NULL, "nop", "");
4636 /* Load an address into a register. */
4639 load_address (int reg, expressionS *ep, int *used_at)
4641 if (ep->X_op != O_constant
4642 && ep->X_op != O_symbol)
4644 as_bad (_("expression too complex"));
4645 ep->X_op = O_constant;
4648 if (ep->X_op == O_constant)
4650 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
4654 if (mips_pic == NO_PIC)
4656 /* If this is a reference to a GP relative symbol, we want
4657 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4659 lui $reg,<sym> (BFD_RELOC_HI16_S)
4660 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4661 If we have an addend, we always use the latter form.
4663 With 64bit address space and a usable $at we want
4664 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4665 lui $at,<sym> (BFD_RELOC_HI16_S)
4666 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4667 daddiu $at,<sym> (BFD_RELOC_LO16)
4671 If $at is already in use, we use a path which is suboptimal
4672 on superscalar processors.
4673 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4674 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4676 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
4678 daddiu $reg,<sym> (BFD_RELOC_LO16)
4680 For GP relative symbols in 64bit address space we can use
4681 the same sequence as in 32bit address space. */
4682 if (HAVE_64BIT_SYMBOLS)
4684 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
4685 && !nopic_need_relax (ep->X_add_symbol, 1))
4687 relax_start (ep->X_add_symbol);
4688 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4689 mips_gp_register, BFD_RELOC_GPREL16);
4693 if (*used_at == 0 && mips_opts.at)
4695 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
4696 macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S);
4697 macro_build (ep, "daddiu", "t,r,j", reg, reg,
4698 BFD_RELOC_MIPS_HIGHER);
4699 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
4700 macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0);
4701 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
4706 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
4707 macro_build (ep, "daddiu", "t,r,j", reg, reg,
4708 BFD_RELOC_MIPS_HIGHER);
4709 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4710 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
4711 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4712 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
4715 if (mips_relax.sequence)
4720 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
4721 && !nopic_need_relax (ep->X_add_symbol, 1))
4723 relax_start (ep->X_add_symbol);
4724 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4725 mips_gp_register, BFD_RELOC_GPREL16);
4728 macro_build_lui (ep, reg);
4729 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
4730 reg, reg, BFD_RELOC_LO16);
4731 if (mips_relax.sequence)
4735 else if (!mips_big_got)
4739 /* If this is a reference to an external symbol, we want
4740 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4742 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4744 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4745 If there is a constant, it must be added in after.
4747 If we have NewABI, we want
4748 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4749 unless we're referencing a global symbol with a non-zero
4750 offset, in which case cst must be added separately. */
4753 if (ep->X_add_number)
4755 ex.X_add_number = ep->X_add_number;
4756 ep->X_add_number = 0;
4757 relax_start (ep->X_add_symbol);
4758 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4759 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4760 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4761 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4762 ex.X_op = O_constant;
4763 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
4764 reg, reg, BFD_RELOC_LO16);
4765 ep->X_add_number = ex.X_add_number;
4768 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4769 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4770 if (mips_relax.sequence)
4775 ex.X_add_number = ep->X_add_number;
4776 ep->X_add_number = 0;
4777 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4778 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4780 relax_start (ep->X_add_symbol);
4782 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4786 if (ex.X_add_number != 0)
4788 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4789 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4790 ex.X_op = O_constant;
4791 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
4792 reg, reg, BFD_RELOC_LO16);
4796 else if (mips_big_got)
4800 /* This is the large GOT case. If this is a reference to an
4801 external symbol, we want
4802 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4804 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
4806 Otherwise, for a reference to a local symbol in old ABI, we want
4807 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4809 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4810 If there is a constant, it must be added in after.
4812 In the NewABI, for local symbols, with or without offsets, we want:
4813 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4814 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4818 ex.X_add_number = ep->X_add_number;
4819 ep->X_add_number = 0;
4820 relax_start (ep->X_add_symbol);
4821 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4822 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4823 reg, reg, mips_gp_register);
4824 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4825 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4826 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4827 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4828 else if (ex.X_add_number)
4830 ex.X_op = O_constant;
4831 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4835 ep->X_add_number = ex.X_add_number;
4837 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4838 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
4839 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4840 BFD_RELOC_MIPS_GOT_OFST);
4845 ex.X_add_number = ep->X_add_number;
4846 ep->X_add_number = 0;
4847 relax_start (ep->X_add_symbol);
4848 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4849 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4850 reg, reg, mips_gp_register);
4851 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4852 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4854 if (reg_needs_delay (mips_gp_register))
4856 /* We need a nop before loading from $gp. This special
4857 check is required because the lui which starts the main
4858 instruction stream does not refer to $gp, and so will not
4859 insert the nop which may be required. */
4860 macro_build (NULL, "nop", "");
4862 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4863 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4865 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4869 if (ex.X_add_number != 0)
4871 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4872 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4873 ex.X_op = O_constant;
4874 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4882 if (!mips_opts.at && *used_at == 1)
4883 as_bad (_("Macro used $at after \".set noat\""));
4886 /* Move the contents of register SOURCE into register DEST. */
4889 move_register (int dest, int source)
4891 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
4895 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4896 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4897 The two alternatives are:
4899 Global symbol Local sybmol
4900 ------------- ------------
4901 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4903 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4905 load_got_offset emits the first instruction and add_got_offset
4906 emits the second for a 16-bit offset or add_got_offset_hilo emits
4907 a sequence to add a 32-bit offset using a scratch register. */
4910 load_got_offset (int dest, expressionS *local)
4915 global.X_add_number = 0;
4917 relax_start (local->X_add_symbol);
4918 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4919 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4921 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4922 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4927 add_got_offset (int dest, expressionS *local)
4931 global.X_op = O_constant;
4932 global.X_op_symbol = NULL;
4933 global.X_add_symbol = NULL;
4934 global.X_add_number = local->X_add_number;
4936 relax_start (local->X_add_symbol);
4937 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
4938 dest, dest, BFD_RELOC_LO16);
4940 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
4945 add_got_offset_hilo (int dest, expressionS *local, int tmp)
4948 int hold_mips_optimize;
4950 global.X_op = O_constant;
4951 global.X_op_symbol = NULL;
4952 global.X_add_symbol = NULL;
4953 global.X_add_number = local->X_add_number;
4955 relax_start (local->X_add_symbol);
4956 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
4958 /* Set mips_optimize around the lui instruction to avoid
4959 inserting an unnecessary nop after the lw. */
4960 hold_mips_optimize = mips_optimize;
4962 macro_build_lui (&global, tmp);
4963 mips_optimize = hold_mips_optimize;
4964 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
4967 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
4972 * This routine implements the seemingly endless macro or synthesized
4973 * instructions and addressing modes in the mips assembly language. Many
4974 * of these macros are simple and are similar to each other. These could
4975 * probably be handled by some kind of table or grammar approach instead of
4976 * this verbose method. Others are not simple macros but are more like
4977 * optimizing code generation.
4978 * One interesting optimization is when several store macros appear
4979 * consecutively that would load AT with the upper half of the same address.
4980 * The ensuing load upper instructions are ommited. This implies some kind
4981 * of global optimization. We currently only optimize within a single macro.
4982 * For many of the load and store macros if the address is specified as a
4983 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4984 * first load register 'at' with zero and use it as the base register. The
4985 * mips assembler simply uses register $zero. Just one tiny optimization
4989 macro (struct mips_cl_insn *ip)
4991 unsigned int treg, sreg, dreg, breg;
4992 unsigned int tempreg;
5007 bfd_reloc_code_real_type r;
5008 int hold_mips_optimize;
5010 gas_assert (! mips_opts.mips16);
5012 treg = EXTRACT_OPERAND (RT, *ip);
5013 dreg = EXTRACT_OPERAND (RD, *ip);
5014 sreg = breg = EXTRACT_OPERAND (RS, *ip);
5015 mask = ip->insn_mo->mask;
5017 expr1.X_op = O_constant;
5018 expr1.X_op_symbol = NULL;
5019 expr1.X_add_symbol = NULL;
5020 expr1.X_add_number = 1;
5034 expr1.X_add_number = 8;
5035 macro_build (&expr1, "bgez", "s,p", sreg);
5037 macro_build (NULL, "nop", "");
5039 move_register (dreg, sreg);
5040 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
5063 if (imm_expr.X_op == O_constant
5064 && imm_expr.X_add_number >= -0x8000
5065 && imm_expr.X_add_number < 0x8000)
5067 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
5071 load_register (AT, &imm_expr, dbl);
5072 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
5091 if (imm_expr.X_op == O_constant
5092 && imm_expr.X_add_number >= 0
5093 && imm_expr.X_add_number < 0x10000)
5095 if (mask != M_NOR_I)
5096 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
5099 macro_build (&imm_expr, "ori", "t,r,i",
5100 treg, sreg, BFD_RELOC_LO16);
5101 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
5107 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5108 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
5112 switch (imm_expr.X_add_number)
5115 macro_build (NULL, "nop", "");
5118 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
5121 macro_build (NULL, "balign", "t,s,2", treg, sreg,
5122 (int) imm_expr.X_add_number);
5141 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5143 macro_build (&offset_expr, s, "s,t,p", sreg, ZERO);
5147 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5148 macro_build (&offset_expr, s, "s,t,p", sreg, AT);
5156 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
5161 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg);
5165 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
5166 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5172 /* Check for > max integer. */
5173 maxnum = 0x7fffffff;
5174 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5181 if (imm_expr.X_op == O_constant
5182 && imm_expr.X_add_number >= maxnum
5183 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5186 /* Result is always false. */
5188 macro_build (NULL, "nop", "");
5190 macro_build (&offset_expr, "bnel", "s,t,p", ZERO, ZERO);
5193 if (imm_expr.X_op != O_constant)
5194 as_bad (_("Unsupported large constant"));
5195 ++imm_expr.X_add_number;
5199 if (mask == M_BGEL_I)
5201 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5203 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
5206 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5208 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
5211 maxnum = 0x7fffffff;
5212 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5219 maxnum = - maxnum - 1;
5220 if (imm_expr.X_op == O_constant
5221 && imm_expr.X_add_number <= maxnum
5222 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5225 /* result is always true */
5226 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
5227 macro_build (&offset_expr, "b", "p");
5232 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5242 macro_build (&offset_expr, likely ? "beql" : "beq",
5243 "s,t,p", ZERO, treg);
5247 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
5248 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5256 && imm_expr.X_op == O_constant
5257 && imm_expr.X_add_number == -1))
5259 if (imm_expr.X_op != O_constant)
5260 as_bad (_("Unsupported large constant"));
5261 ++imm_expr.X_add_number;
5265 if (mask == M_BGEUL_I)
5267 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5269 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5271 macro_build (&offset_expr, likely ? "bnel" : "bne",
5272 "s,t,p", sreg, ZERO);
5277 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5285 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
5290 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg);
5294 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
5295 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5303 macro_build (&offset_expr, likely ? "bnel" : "bne",
5304 "s,t,p", sreg, ZERO);
5310 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
5311 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5319 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
5324 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg);
5328 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
5329 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5335 maxnum = 0x7fffffff;
5336 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5343 if (imm_expr.X_op == O_constant
5344 && imm_expr.X_add_number >= maxnum
5345 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5347 if (imm_expr.X_op != O_constant)
5348 as_bad (_("Unsupported large constant"));
5349 ++imm_expr.X_add_number;
5353 if (mask == M_BLTL_I)
5355 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5357 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
5360 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5362 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
5367 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5375 macro_build (&offset_expr, likely ? "beql" : "beq",
5376 "s,t,p", sreg, ZERO);
5382 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
5383 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5391 && imm_expr.X_op == O_constant
5392 && imm_expr.X_add_number == -1))
5394 if (imm_expr.X_op != O_constant)
5395 as_bad (_("Unsupported large constant"));
5396 ++imm_expr.X_add_number;
5400 if (mask == M_BLTUL_I)
5402 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5404 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5406 macro_build (&offset_expr, likely ? "beql" : "beq",
5407 "s,t,p", sreg, ZERO);
5412 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5420 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
5425 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg);
5429 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
5430 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5440 macro_build (&offset_expr, likely ? "bnel" : "bne",
5441 "s,t,p", ZERO, treg);
5445 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
5446 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5451 /* Use unsigned arithmetic. */
5455 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5457 as_bad (_("Unsupported large constant"));
5462 pos = imm_expr.X_add_number;
5463 size = imm2_expr.X_add_number;
5468 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
5471 if (size == 0 || size > 64 || (pos + size - 1) > 63)
5473 as_bad (_("Improper extract size (%lu, position %lu)"),
5474 (unsigned long) size, (unsigned long) pos);
5478 if (size <= 32 && pos < 32)
5483 else if (size <= 32)
5493 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
5500 /* Use unsigned arithmetic. */
5504 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5506 as_bad (_("Unsupported large constant"));
5511 pos = imm_expr.X_add_number;
5512 size = imm2_expr.X_add_number;
5517 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
5520 if (size == 0 || size > 64 || (pos + size - 1) > 63)
5522 as_bad (_("Improper insert size (%lu, position %lu)"),
5523 (unsigned long) size, (unsigned long) pos);
5527 if (pos < 32 && (pos + size - 1) < 32)
5542 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
5543 (int) (pos + size - 1));
5559 as_warn (_("Divide by zero."));
5561 macro_build (NULL, "teq", "s,t,q", ZERO, ZERO, 7);
5563 macro_build (NULL, "break", "c", 7);
5570 macro_build (NULL, "teq", "s,t,q", treg, ZERO, 7);
5571 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
5575 expr1.X_add_number = 8;
5576 macro_build (&expr1, "bne", "s,t,p", treg, ZERO);
5577 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
5578 macro_build (NULL, "break", "c", 7);
5580 expr1.X_add_number = -1;
5582 load_register (AT, &expr1, dbl);
5583 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
5584 macro_build (&expr1, "bne", "s,t,p", treg, AT);
5587 expr1.X_add_number = 1;
5588 load_register (AT, &expr1, dbl);
5589 macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31);
5593 expr1.X_add_number = 0x80000000;
5594 macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16);
5598 macro_build (NULL, "teq", "s,t,q", sreg, AT, 6);
5599 /* We want to close the noreorder block as soon as possible, so
5600 that later insns are available for delay slot filling. */
5605 expr1.X_add_number = 8;
5606 macro_build (&expr1, "bne", "s,t,p", sreg, AT);
5607 macro_build (NULL, "nop", "");
5609 /* We want to close the noreorder block as soon as possible, so
5610 that later insns are available for delay slot filling. */
5613 macro_build (NULL, "break", "c", 6);
5615 macro_build (NULL, s, "d", dreg);
5654 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5656 as_warn (_("Divide by zero."));
5658 macro_build (NULL, "teq", "s,t,q", ZERO, ZERO, 7);
5660 macro_build (NULL, "break", "c", 7);
5663 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5665 if (strcmp (s2, "mflo") == 0)
5666 move_register (dreg, sreg);
5668 move_register (dreg, ZERO);
5671 if (imm_expr.X_op == O_constant
5672 && imm_expr.X_add_number == -1
5673 && s[strlen (s) - 1] != 'u')
5675 if (strcmp (s2, "mflo") == 0)
5677 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
5680 move_register (dreg, ZERO);
5685 load_register (AT, &imm_expr, dbl);
5686 macro_build (NULL, s, "z,s,t", sreg, AT);
5687 macro_build (NULL, s2, "d", dreg);
5709 macro_build (NULL, "teq", "s,t,q", treg, ZERO, 7);
5710 macro_build (NULL, s, "z,s,t", sreg, treg);
5711 /* We want to close the noreorder block as soon as possible, so
5712 that later insns are available for delay slot filling. */
5717 expr1.X_add_number = 8;
5718 macro_build (&expr1, "bne", "s,t,p", treg, ZERO);
5719 macro_build (NULL, s, "z,s,t", sreg, treg);
5721 /* We want to close the noreorder block as soon as possible, so
5722 that later insns are available for delay slot filling. */
5724 macro_build (NULL, "break", "c", 7);
5726 macro_build (NULL, s2, "d", dreg);
5738 /* Load the address of a symbol into a register. If breg is not
5739 zero, we then add a base register to it. */
5741 if (dbl && HAVE_32BIT_GPRS)
5742 as_warn (_("dla used to load 32-bit register"));
5744 if (!dbl && HAVE_64BIT_OBJECTS)
5745 as_warn (_("la used to load 64-bit address"));
5747 if (offset_expr.X_op == O_constant
5748 && offset_expr.X_add_number >= -0x8000
5749 && offset_expr.X_add_number < 0x8000)
5751 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
5752 "t,r,j", treg, sreg, BFD_RELOC_LO16);
5756 if (mips_opts.at && (treg == breg))
5766 if (offset_expr.X_op != O_symbol
5767 && offset_expr.X_op != O_constant)
5769 as_bad (_("Expression too complex"));
5770 offset_expr.X_op = O_constant;
5773 if (offset_expr.X_op == O_constant)
5774 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
5775 else if (mips_pic == NO_PIC)
5777 /* If this is a reference to a GP relative symbol, we want
5778 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5780 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5781 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5782 If we have a constant, we need two instructions anyhow,
5783 so we may as well always use the latter form.
5785 With 64bit address space and a usable $at we want
5786 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5787 lui $at,<sym> (BFD_RELOC_HI16_S)
5788 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5789 daddiu $at,<sym> (BFD_RELOC_LO16)
5791 daddu $tempreg,$tempreg,$at
5793 If $at is already in use, we use a path which is suboptimal
5794 on superscalar processors.
5795 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5796 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5798 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5800 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
5802 For GP relative symbols in 64bit address space we can use
5803 the same sequence as in 32bit address space. */
5804 if (HAVE_64BIT_SYMBOLS)
5806 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5807 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5809 relax_start (offset_expr.X_add_symbol);
5810 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5811 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5815 if (used_at == 0 && mips_opts.at)
5817 macro_build (&offset_expr, "lui", "t,u",
5818 tempreg, BFD_RELOC_MIPS_HIGHEST);
5819 macro_build (&offset_expr, "lui", "t,u",
5820 AT, BFD_RELOC_HI16_S);
5821 macro_build (&offset_expr, "daddiu", "t,r,j",
5822 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5823 macro_build (&offset_expr, "daddiu", "t,r,j",
5824 AT, AT, BFD_RELOC_LO16);
5825 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
5826 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
5831 macro_build (&offset_expr, "lui", "t,u",
5832 tempreg, BFD_RELOC_MIPS_HIGHEST);
5833 macro_build (&offset_expr, "daddiu", "t,r,j",
5834 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5835 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5836 macro_build (&offset_expr, "daddiu", "t,r,j",
5837 tempreg, tempreg, BFD_RELOC_HI16_S);
5838 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5839 macro_build (&offset_expr, "daddiu", "t,r,j",
5840 tempreg, tempreg, BFD_RELOC_LO16);
5843 if (mips_relax.sequence)
5848 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5849 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5851 relax_start (offset_expr.X_add_symbol);
5852 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5853 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5856 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
5857 as_bad (_("Offset too large"));
5858 macro_build_lui (&offset_expr, tempreg);
5859 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5860 tempreg, tempreg, BFD_RELOC_LO16);
5861 if (mips_relax.sequence)
5865 else if (!mips_big_got && !HAVE_NEWABI)
5867 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5869 /* If this is a reference to an external symbol, and there
5870 is no constant, we want
5871 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5872 or for lca or if tempreg is PIC_CALL_REG
5873 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5874 For a local symbol, we want
5875 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5877 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5879 If we have a small constant, and this is a reference to
5880 an external symbol, we want
5881 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5883 addiu $tempreg,$tempreg,<constant>
5884 For a local symbol, we want the same instruction
5885 sequence, but we output a BFD_RELOC_LO16 reloc on the
5888 If we have a large constant, and this is a reference to
5889 an external symbol, we want
5890 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5891 lui $at,<hiconstant>
5892 addiu $at,$at,<loconstant>
5893 addu $tempreg,$tempreg,$at
5894 For a local symbol, we want the same instruction
5895 sequence, but we output a BFD_RELOC_LO16 reloc on the
5899 if (offset_expr.X_add_number == 0)
5901 if (mips_pic == SVR4_PIC
5903 && (call || tempreg == PIC_CALL_REG))
5904 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
5906 relax_start (offset_expr.X_add_symbol);
5907 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5908 lw_reloc_type, mips_gp_register);
5911 /* We're going to put in an addu instruction using
5912 tempreg, so we may as well insert the nop right
5917 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5918 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
5920 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5921 tempreg, tempreg, BFD_RELOC_LO16);
5923 /* FIXME: If breg == 0, and the next instruction uses
5924 $tempreg, then if this variant case is used an extra
5925 nop will be generated. */
5927 else if (offset_expr.X_add_number >= -0x8000
5928 && offset_expr.X_add_number < 0x8000)
5930 load_got_offset (tempreg, &offset_expr);
5932 add_got_offset (tempreg, &offset_expr);
5936 expr1.X_add_number = offset_expr.X_add_number;
5937 offset_expr.X_add_number =
5938 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
5939 load_got_offset (tempreg, &offset_expr);
5940 offset_expr.X_add_number = expr1.X_add_number;
5941 /* If we are going to add in a base register, and the
5942 target register and the base register are the same,
5943 then we are using AT as a temporary register. Since
5944 we want to load the constant into AT, we add our
5945 current AT (from the global offset table) and the
5946 register into the register now, and pretend we were
5947 not using a base register. */
5951 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5956 add_got_offset_hilo (tempreg, &offset_expr, AT);
5960 else if (!mips_big_got && HAVE_NEWABI)
5962 int add_breg_early = 0;
5964 /* If this is a reference to an external, and there is no
5965 constant, or local symbol (*), with or without a
5967 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5968 or for lca or if tempreg is PIC_CALL_REG
5969 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5971 If we have a small constant, and this is a reference to
5972 an external symbol, we want
5973 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5974 addiu $tempreg,$tempreg,<constant>
5976 If we have a large constant, and this is a reference to
5977 an external symbol, we want
5978 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5979 lui $at,<hiconstant>
5980 addiu $at,$at,<loconstant>
5981 addu $tempreg,$tempreg,$at
5983 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5984 local symbols, even though it introduces an additional
5987 if (offset_expr.X_add_number)
5989 expr1.X_add_number = offset_expr.X_add_number;
5990 offset_expr.X_add_number = 0;
5992 relax_start (offset_expr.X_add_symbol);
5993 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5994 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5996 if (expr1.X_add_number >= -0x8000
5997 && expr1.X_add_number < 0x8000)
5999 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
6000 tempreg, tempreg, BFD_RELOC_LO16);
6002 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
6004 /* If we are going to add in a base register, and the
6005 target register and the base register are the same,
6006 then we are using AT as a temporary register. Since
6007 we want to load the constant into AT, we add our
6008 current AT (from the global offset table) and the
6009 register into the register now, and pretend we were
6010 not using a base register. */
6015 gas_assert (tempreg == AT);
6016 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6022 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
6023 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6029 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
6032 offset_expr.X_add_number = expr1.X_add_number;
6034 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6035 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6038 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6039 treg, tempreg, breg);
6045 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
6047 relax_start (offset_expr.X_add_symbol);
6048 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6049 BFD_RELOC_MIPS_CALL16, mips_gp_register);
6051 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6052 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6057 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6058 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6061 else if (mips_big_got && !HAVE_NEWABI)
6064 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
6065 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
6066 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6068 /* This is the large GOT case. If this is a reference to an
6069 external symbol, and there is no constant, we want
6070 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6071 addu $tempreg,$tempreg,$gp
6072 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6073 or for lca or if tempreg is PIC_CALL_REG
6074 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6075 addu $tempreg,$tempreg,$gp
6076 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
6077 For a local symbol, we want
6078 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6080 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6082 If we have a small constant, and this is a reference to
6083 an external symbol, we want
6084 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6085 addu $tempreg,$tempreg,$gp
6086 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6088 addiu $tempreg,$tempreg,<constant>
6089 For a local symbol, we want
6090 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6092 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
6094 If we have a large constant, and this is a reference to
6095 an external symbol, we want
6096 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6097 addu $tempreg,$tempreg,$gp
6098 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6099 lui $at,<hiconstant>
6100 addiu $at,$at,<loconstant>
6101 addu $tempreg,$tempreg,$at
6102 For a local symbol, we want
6103 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6104 lui $at,<hiconstant>
6105 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
6106 addu $tempreg,$tempreg,$at
6109 expr1.X_add_number = offset_expr.X_add_number;
6110 offset_expr.X_add_number = 0;
6111 relax_start (offset_expr.X_add_symbol);
6112 gpdelay = reg_needs_delay (mips_gp_register);
6113 if (expr1.X_add_number == 0 && breg == 0
6114 && (call || tempreg == PIC_CALL_REG))
6116 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
6117 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
6119 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
6120 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6121 tempreg, tempreg, mips_gp_register);
6122 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6123 tempreg, lw_reloc_type, tempreg);
6124 if (expr1.X_add_number == 0)
6128 /* We're going to put in an addu instruction using
6129 tempreg, so we may as well insert the nop right
6134 else if (expr1.X_add_number >= -0x8000
6135 && expr1.X_add_number < 0x8000)
6138 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
6139 tempreg, tempreg, BFD_RELOC_LO16);
6143 /* If we are going to add in a base register, and the
6144 target register and the base register are the same,
6145 then we are using AT as a temporary register. Since
6146 we want to load the constant into AT, we add our
6147 current AT (from the global offset table) and the
6148 register into the register now, and pretend we were
6149 not using a base register. */
6154 gas_assert (tempreg == AT);
6156 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6161 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
6162 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
6166 offset_expr.X_add_number =
6167 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000;
6172 /* This is needed because this instruction uses $gp, but
6173 the first instruction on the main stream does not. */
6174 macro_build (NULL, "nop", "");
6177 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6178 local_reloc_type, mips_gp_register);
6179 if (expr1.X_add_number >= -0x8000
6180 && expr1.X_add_number < 0x8000)
6183 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6184 tempreg, tempreg, BFD_RELOC_LO16);
6185 /* FIXME: If add_number is 0, and there was no base
6186 register, the external symbol case ended with a load,
6187 so if the symbol turns out to not be external, and
6188 the next instruction uses tempreg, an unnecessary nop
6189 will be inserted. */
6195 /* We must add in the base register now, as in the
6196 external symbol case. */
6197 gas_assert (tempreg == AT);
6199 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6202 /* We set breg to 0 because we have arranged to add
6203 it in in both cases. */
6207 macro_build_lui (&expr1, AT);
6208 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6209 AT, AT, BFD_RELOC_LO16);
6210 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6211 tempreg, tempreg, AT);
6216 else if (mips_big_got && HAVE_NEWABI)
6218 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
6219 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
6220 int add_breg_early = 0;
6222 /* This is the large GOT case. If this is a reference to an
6223 external symbol, and there is no constant, we want
6224 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6225 add $tempreg,$tempreg,$gp
6226 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6227 or for lca or if tempreg is PIC_CALL_REG
6228 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6229 add $tempreg,$tempreg,$gp
6230 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
6232 If we have a small constant, and this is a reference to
6233 an external symbol, we want
6234 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6235 add $tempreg,$tempreg,$gp
6236 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6237 addi $tempreg,$tempreg,<constant>
6239 If we have a large constant, and this is a reference to
6240 an external symbol, we want
6241 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6242 addu $tempreg,$tempreg,$gp
6243 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6244 lui $at,<hiconstant>
6245 addi $at,$at,<loconstant>
6246 add $tempreg,$tempreg,$at
6248 If we have NewABI, and we know it's a local symbol, we want
6249 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6250 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6251 otherwise we have to resort to GOT_HI16/GOT_LO16. */
6253 relax_start (offset_expr.X_add_symbol);
6255 expr1.X_add_number = offset_expr.X_add_number;
6256 offset_expr.X_add_number = 0;
6258 if (expr1.X_add_number == 0 && breg == 0
6259 && (call || tempreg == PIC_CALL_REG))
6261 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
6262 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
6264 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
6265 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6266 tempreg, tempreg, mips_gp_register);
6267 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6268 tempreg, lw_reloc_type, tempreg);
6270 if (expr1.X_add_number == 0)
6272 else if (expr1.X_add_number >= -0x8000
6273 && expr1.X_add_number < 0x8000)
6275 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
6276 tempreg, tempreg, BFD_RELOC_LO16);
6278 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
6280 /* If we are going to add in a base register, and the
6281 target register and the base register are the same,
6282 then we are using AT as a temporary register. Since
6283 we want to load the constant into AT, we add our
6284 current AT (from the global offset table) and the
6285 register into the register now, and pretend we were
6286 not using a base register. */
6291 gas_assert (tempreg == AT);
6292 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6298 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
6299 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
6304 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
6307 offset_expr.X_add_number = expr1.X_add_number;
6308 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6309 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6310 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6311 tempreg, BFD_RELOC_MIPS_GOT_OFST);
6314 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6315 treg, tempreg, breg);
6325 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
6330 unsigned long temp = (treg << 16) | (0x01);
6331 macro_build (NULL, "c2", "C", temp);
6337 unsigned long temp = (0x02);
6338 macro_build (NULL, "c2", "C", temp);
6344 unsigned long temp = (treg << 16) | (0x02);
6345 macro_build (NULL, "c2", "C", temp);
6350 macro_build (NULL, "c2", "C", 3);
6355 unsigned long temp = (treg << 16) | 0x03;
6356 macro_build (NULL, "c2", "C", temp);
6361 /* The j instruction may not be used in PIC code, since it
6362 requires an absolute address. We convert it to a b
6364 if (mips_pic == NO_PIC)
6365 macro_build (&offset_expr, "j", "a");
6367 macro_build (&offset_expr, "b", "p");
6370 /* The jal instructions must be handled as macros because when
6371 generating PIC code they expand to multi-instruction
6372 sequences. Normally they are simple instructions. */
6377 if (mips_pic == NO_PIC)
6378 macro_build (NULL, "jalr", "d,s", dreg, sreg);
6381 if (sreg != PIC_CALL_REG)
6382 as_warn (_("MIPS PIC call to register other than $25"));
6384 macro_build (NULL, "jalr", "d,s", dreg, sreg);
6385 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
6387 if (mips_cprestore_offset < 0)
6388 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6391 if (!mips_frame_reg_valid)
6393 as_warn (_("No .frame pseudo-op used in PIC code"));
6394 /* Quiet this warning. */
6395 mips_frame_reg_valid = 1;
6397 if (!mips_cprestore_valid)
6399 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6400 /* Quiet this warning. */
6401 mips_cprestore_valid = 1;
6403 if (mips_opts.noreorder)
6404 macro_build (NULL, "nop", "");
6405 expr1.X_add_number = mips_cprestore_offset;
6406 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
6409 HAVE_64BIT_ADDRESSES);
6417 if (mips_pic == NO_PIC)
6418 macro_build (&offset_expr, "jal", "a");
6419 else if (mips_pic == SVR4_PIC)
6421 /* If this is a reference to an external symbol, and we are
6422 using a small GOT, we want
6423 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
6427 lw $gp,cprestore($sp)
6428 The cprestore value is set using the .cprestore
6429 pseudo-op. If we are using a big GOT, we want
6430 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6432 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
6436 lw $gp,cprestore($sp)
6437 If the symbol is not external, we want
6438 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6440 addiu $25,$25,<sym> (BFD_RELOC_LO16)
6443 lw $gp,cprestore($sp)
6445 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
6446 sequences above, minus nops, unless the symbol is local,
6447 which enables us to use GOT_PAGE/GOT_OFST (big got) or
6453 relax_start (offset_expr.X_add_symbol);
6454 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6455 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
6458 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6459 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
6465 relax_start (offset_expr.X_add_symbol);
6466 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
6467 BFD_RELOC_MIPS_CALL_HI16);
6468 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
6469 PIC_CALL_REG, mips_gp_register);
6470 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6471 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
6474 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6475 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
6477 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6478 PIC_CALL_REG, PIC_CALL_REG,
6479 BFD_RELOC_MIPS_GOT_OFST);
6483 macro_build_jalr (&offset_expr);
6487 relax_start (offset_expr.X_add_symbol);
6490 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6491 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
6500 gpdelay = reg_needs_delay (mips_gp_register);
6501 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
6502 BFD_RELOC_MIPS_CALL_HI16);
6503 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
6504 PIC_CALL_REG, mips_gp_register);
6505 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6506 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
6511 macro_build (NULL, "nop", "");
6513 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6514 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
6517 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6518 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
6520 macro_build_jalr (&offset_expr);
6522 if (mips_cprestore_offset < 0)
6523 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6526 if (!mips_frame_reg_valid)
6528 as_warn (_("No .frame pseudo-op used in PIC code"));
6529 /* Quiet this warning. */
6530 mips_frame_reg_valid = 1;
6532 if (!mips_cprestore_valid)
6534 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6535 /* Quiet this warning. */
6536 mips_cprestore_valid = 1;
6538 if (mips_opts.noreorder)
6539 macro_build (NULL, "nop", "");
6540 expr1.X_add_number = mips_cprestore_offset;
6541 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
6544 HAVE_64BIT_ADDRESSES);
6548 else if (mips_pic == VXWORKS_PIC)
6549 as_bad (_("Non-PIC jump used in PIC library"));
6572 /* Itbl support may require additional care here. */
6577 /* Itbl support may require additional care here. */
6582 /* Itbl support may require additional care here. */
6587 /* Itbl support may require additional care here. */
6600 /* Itbl support may require additional care here. */
6605 /* Itbl support may require additional care here. */
6610 /* Itbl support may require additional care here. */
6630 if (breg == treg || coproc || lr)
6651 /* Itbl support may require additional care here. */
6656 /* Itbl support may require additional care here. */
6661 /* Itbl support may require additional care here. */
6666 /* Itbl support may require additional care here. */
6690 /* Itbl support may require additional care here. */
6694 /* Itbl support may require additional care here. */
6699 /* Itbl support may require additional care here. */
6712 && NO_ISA_COP (mips_opts.arch)
6713 && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0)
6715 as_bad (_("Opcode not supported on this processor: %s"),
6716 mips_cpu_info_from_arch (mips_opts.arch)->name);
6720 /* Itbl support may require additional care here. */
6721 if (mask == M_LWC1_AB
6722 || mask == M_SWC1_AB
6723 || mask == M_LDC1_AB
6724 || mask == M_SDC1_AB
6728 else if (mask == M_CACHE_AB || mask == M_PREF_AB)
6735 if (offset_expr.X_op != O_constant
6736 && offset_expr.X_op != O_symbol)
6738 as_bad (_("Expression too complex"));
6739 offset_expr.X_op = O_constant;
6742 if (HAVE_32BIT_ADDRESSES
6743 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
6747 sprintf_vma (value, offset_expr.X_add_number);
6748 as_bad (_("Number (0x%s) larger than 32 bits"), value);
6751 /* A constant expression in PIC code can be handled just as it
6752 is in non PIC code. */
6753 if (offset_expr.X_op == O_constant)
6755 expr1.X_add_number = offset_expr.X_add_number;
6756 normalize_address_expr (&expr1);
6757 if (!IS_SEXT_16BIT_NUM (expr1.X_add_number))
6759 expr1.X_add_number = ((expr1.X_add_number + 0x8000)
6760 & ~(bfd_vma) 0xffff);
6761 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
6763 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6764 tempreg, tempreg, breg);
6767 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg);
6769 else if (mips_pic == NO_PIC)
6771 /* If this is a reference to a GP relative symbol, and there
6772 is no base register, we want
6773 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6774 Otherwise, if there is no base register, we want
6775 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6776 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6777 If we have a constant, we need two instructions anyhow,
6778 so we always use the latter form.
6780 If we have a base register, and this is a reference to a
6781 GP relative symbol, we want
6782 addu $tempreg,$breg,$gp
6783 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6785 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6786 addu $tempreg,$tempreg,$breg
6787 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6788 With a constant we always use the latter case.
6790 With 64bit address space and no base register and $at usable,
6792 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6793 lui $at,<sym> (BFD_RELOC_HI16_S)
6794 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6797 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6798 If we have a base register, we want
6799 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6800 lui $at,<sym> (BFD_RELOC_HI16_S)
6801 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6805 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6807 Without $at we can't generate the optimal path for superscalar
6808 processors here since this would require two temporary registers.
6809 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6810 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6812 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6814 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6815 If we have a base register, we want
6816 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6817 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6819 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6821 daddu $tempreg,$tempreg,$breg
6822 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6824 For GP relative symbols in 64bit address space we can use
6825 the same sequence as in 32bit address space. */
6826 if (HAVE_64BIT_SYMBOLS)
6828 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6829 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6831 relax_start (offset_expr.X_add_symbol);
6834 macro_build (&offset_expr, s, fmt, treg,
6835 BFD_RELOC_GPREL16, mips_gp_register);
6839 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6840 tempreg, breg, mips_gp_register);
6841 macro_build (&offset_expr, s, fmt, treg,
6842 BFD_RELOC_GPREL16, tempreg);
6847 if (used_at == 0 && mips_opts.at)
6849 macro_build (&offset_expr, "lui", "t,u", tempreg,
6850 BFD_RELOC_MIPS_HIGHEST);
6851 macro_build (&offset_expr, "lui", "t,u", AT,
6853 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6854 tempreg, BFD_RELOC_MIPS_HIGHER);
6856 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
6857 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
6858 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
6859 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
6865 macro_build (&offset_expr, "lui", "t,u", tempreg,
6866 BFD_RELOC_MIPS_HIGHEST);
6867 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6868 tempreg, BFD_RELOC_MIPS_HIGHER);
6869 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6870 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6871 tempreg, BFD_RELOC_HI16_S);
6872 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6874 macro_build (NULL, "daddu", "d,v,t",
6875 tempreg, tempreg, breg);
6876 macro_build (&offset_expr, s, fmt, treg,
6877 BFD_RELOC_LO16, tempreg);
6880 if (mips_relax.sequence)
6887 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6888 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6890 relax_start (offset_expr.X_add_symbol);
6891 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
6895 macro_build_lui (&offset_expr, tempreg);
6896 macro_build (&offset_expr, s, fmt, treg,
6897 BFD_RELOC_LO16, tempreg);
6898 if (mips_relax.sequence)
6903 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6904 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6906 relax_start (offset_expr.X_add_symbol);
6907 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6908 tempreg, breg, mips_gp_register);
6909 macro_build (&offset_expr, s, fmt, treg,
6910 BFD_RELOC_GPREL16, tempreg);
6913 macro_build_lui (&offset_expr, tempreg);
6914 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6915 tempreg, tempreg, breg);
6916 macro_build (&offset_expr, s, fmt, treg,
6917 BFD_RELOC_LO16, tempreg);
6918 if (mips_relax.sequence)
6922 else if (!mips_big_got)
6924 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6926 /* If this is a reference to an external symbol, we want
6927 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6929 <op> $treg,0($tempreg)
6931 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6933 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6934 <op> $treg,0($tempreg)
6937 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6938 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6940 If there is a base register, we add it to $tempreg before
6941 the <op>. If there is a constant, we stick it in the
6942 <op> instruction. We don't handle constants larger than
6943 16 bits, because we have no way to load the upper 16 bits
6944 (actually, we could handle them for the subset of cases
6945 in which we are not using $at). */
6946 gas_assert (offset_expr.X_op == O_symbol);
6949 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6950 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6952 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6953 tempreg, tempreg, breg);
6954 macro_build (&offset_expr, s, fmt, treg,
6955 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6958 expr1.X_add_number = offset_expr.X_add_number;
6959 offset_expr.X_add_number = 0;
6960 if (expr1.X_add_number < -0x8000
6961 || expr1.X_add_number >= 0x8000)
6962 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6963 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6964 lw_reloc_type, mips_gp_register);
6966 relax_start (offset_expr.X_add_symbol);
6968 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6969 tempreg, BFD_RELOC_LO16);
6972 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6973 tempreg, tempreg, breg);
6974 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6976 else if (mips_big_got && !HAVE_NEWABI)
6980 /* If this is a reference to an external symbol, we want
6981 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6982 addu $tempreg,$tempreg,$gp
6983 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6984 <op> $treg,0($tempreg)
6986 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6988 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6989 <op> $treg,0($tempreg)
6990 If there is a base register, we add it to $tempreg before
6991 the <op>. If there is a constant, we stick it in the
6992 <op> instruction. We don't handle constants larger than
6993 16 bits, because we have no way to load the upper 16 bits
6994 (actually, we could handle them for the subset of cases
6995 in which we are not using $at). */
6996 gas_assert (offset_expr.X_op == O_symbol);
6997 expr1.X_add_number = offset_expr.X_add_number;
6998 offset_expr.X_add_number = 0;
6999 if (expr1.X_add_number < -0x8000
7000 || expr1.X_add_number >= 0x8000)
7001 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7002 gpdelay = reg_needs_delay (mips_gp_register);
7003 relax_start (offset_expr.X_add_symbol);
7004 macro_build (&offset_expr, "lui", "t,u", tempreg,
7005 BFD_RELOC_MIPS_GOT_HI16);
7006 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
7008 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7009 BFD_RELOC_MIPS_GOT_LO16, tempreg);
7012 macro_build (NULL, "nop", "");
7013 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7014 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7016 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
7017 tempreg, BFD_RELOC_LO16);
7021 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7022 tempreg, tempreg, breg);
7023 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
7025 else if (mips_big_got && HAVE_NEWABI)
7027 /* If this is a reference to an external symbol, we want
7028 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7029 add $tempreg,$tempreg,$gp
7030 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7031 <op> $treg,<ofst>($tempreg)
7032 Otherwise, for local symbols, we want:
7033 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7034 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
7035 gas_assert (offset_expr.X_op == O_symbol);
7036 expr1.X_add_number = offset_expr.X_add_number;
7037 offset_expr.X_add_number = 0;
7038 if (expr1.X_add_number < -0x8000
7039 || expr1.X_add_number >= 0x8000)
7040 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7041 relax_start (offset_expr.X_add_symbol);
7042 macro_build (&offset_expr, "lui", "t,u", tempreg,
7043 BFD_RELOC_MIPS_GOT_HI16);
7044 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
7046 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7047 BFD_RELOC_MIPS_GOT_LO16, tempreg);
7049 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7050 tempreg, tempreg, breg);
7051 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
7054 offset_expr.X_add_number = expr1.X_add_number;
7055 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7056 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
7058 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7059 tempreg, tempreg, breg);
7060 macro_build (&offset_expr, s, fmt, treg,
7061 BFD_RELOC_MIPS_GOT_OFST, tempreg);
7071 load_register (treg, &imm_expr, 0);
7075 load_register (treg, &imm_expr, 1);
7079 if (imm_expr.X_op == O_constant)
7082 load_register (AT, &imm_expr, 0);
7083 macro_build (NULL, "mtc1", "t,G", AT, treg);
7088 gas_assert (offset_expr.X_op == O_symbol
7089 && strcmp (segment_name (S_GET_SEGMENT
7090 (offset_expr.X_add_symbol)),
7092 && offset_expr.X_add_number == 0);
7093 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
7094 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
7099 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
7100 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
7101 order 32 bits of the value and the low order 32 bits are either
7102 zero or in OFFSET_EXPR. */
7103 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
7105 if (HAVE_64BIT_GPRS)
7106 load_register (treg, &imm_expr, 1);
7111 if (target_big_endian)
7123 load_register (hreg, &imm_expr, 0);
7126 if (offset_expr.X_op == O_absent)
7127 move_register (lreg, 0);
7130 gas_assert (offset_expr.X_op == O_constant);
7131 load_register (lreg, &offset_expr, 0);
7138 /* We know that sym is in the .rdata section. First we get the
7139 upper 16 bits of the address. */
7140 if (mips_pic == NO_PIC)
7142 macro_build_lui (&offset_expr, AT);
7147 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7148 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7152 /* Now we load the register(s). */
7153 if (HAVE_64BIT_GPRS)
7156 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7161 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7164 /* FIXME: How in the world do we deal with the possible
7166 offset_expr.X_add_number += 4;
7167 macro_build (&offset_expr, "lw", "t,o(b)",
7168 treg + 1, BFD_RELOC_LO16, AT);
7174 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
7175 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
7176 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
7177 the value and the low order 32 bits are either zero or in
7179 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
7182 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
7183 if (HAVE_64BIT_FPRS)
7185 gas_assert (HAVE_64BIT_GPRS);
7186 macro_build (NULL, "dmtc1", "t,S", AT, treg);
7190 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
7191 if (offset_expr.X_op == O_absent)
7192 macro_build (NULL, "mtc1", "t,G", 0, treg);
7195 gas_assert (offset_expr.X_op == O_constant);
7196 load_register (AT, &offset_expr, 0);
7197 macro_build (NULL, "mtc1", "t,G", AT, treg);
7203 gas_assert (offset_expr.X_op == O_symbol
7204 && offset_expr.X_add_number == 0);
7205 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
7206 if (strcmp (s, ".lit8") == 0)
7208 if (mips_opts.isa != ISA_MIPS1)
7210 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
7211 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
7214 breg = mips_gp_register;
7215 r = BFD_RELOC_MIPS_LITERAL;
7220 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
7222 if (mips_pic != NO_PIC)
7223 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7224 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7227 /* FIXME: This won't work for a 64 bit address. */
7228 macro_build_lui (&offset_expr, AT);
7231 if (mips_opts.isa != ISA_MIPS1)
7233 macro_build (&offset_expr, "ldc1", "T,o(b)",
7234 treg, BFD_RELOC_LO16, AT);
7243 /* Even on a big endian machine $fn comes before $fn+1. We have
7244 to adjust when loading from memory. */
7247 gas_assert (mips_opts.isa == ISA_MIPS1);
7248 macro_build (&offset_expr, "lwc1", "T,o(b)",
7249 target_big_endian ? treg + 1 : treg, r, breg);
7250 /* FIXME: A possible overflow which I don't know how to deal
7252 offset_expr.X_add_number += 4;
7253 macro_build (&offset_expr, "lwc1", "T,o(b)",
7254 target_big_endian ? treg : treg + 1, r, breg);
7258 gas_assert (mips_opts.isa == ISA_MIPS1);
7259 /* Even on a big endian machine $fn comes before $fn+1. We have
7260 to adjust when storing to memory. */
7261 macro_build (&offset_expr, "swc1", "T,o(b)",
7262 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
7263 offset_expr.X_add_number += 4;
7264 macro_build (&offset_expr, "swc1", "T,o(b)",
7265 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
7270 * The MIPS assembler seems to check for X_add_number not
7271 * being double aligned and generating:
7274 * addiu at,at,%lo(foo+1)
7277 * But, the resulting address is the same after relocation so why
7278 * generate the extra instruction?
7280 /* Itbl support may require additional care here. */
7282 if (mips_opts.isa != ISA_MIPS1)
7293 if (mips_opts.isa != ISA_MIPS1)
7301 /* Itbl support may require additional care here. */
7306 if (HAVE_64BIT_GPRS)
7317 if (HAVE_64BIT_GPRS)
7327 if (offset_expr.X_op != O_symbol
7328 && offset_expr.X_op != O_constant)
7330 as_bad (_("Expression too complex"));
7331 offset_expr.X_op = O_constant;
7334 if (HAVE_32BIT_ADDRESSES
7335 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
7339 sprintf_vma (value, offset_expr.X_add_number);
7340 as_bad (_("Number (0x%s) larger than 32 bits"), value);
7343 /* Even on a big endian machine $fn comes before $fn+1. We have
7344 to adjust when loading from memory. We set coproc if we must
7345 load $fn+1 first. */
7346 /* Itbl support may require additional care here. */
7347 if (!target_big_endian)
7350 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
7352 /* If this is a reference to a GP relative symbol, we want
7353 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
7354 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
7355 If we have a base register, we use this
7357 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
7358 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
7359 If this is not a GP relative symbol, we want
7360 lui $at,<sym> (BFD_RELOC_HI16_S)
7361 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7362 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7363 If there is a base register, we add it to $at after the
7364 lui instruction. If there is a constant, we always use
7366 if (offset_expr.X_op == O_symbol
7367 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7368 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7370 relax_start (offset_expr.X_add_symbol);
7373 tempreg = mips_gp_register;
7377 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7378 AT, breg, mips_gp_register);
7383 /* Itbl support may require additional care here. */
7384 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7385 BFD_RELOC_GPREL16, tempreg);
7386 offset_expr.X_add_number += 4;
7388 /* Set mips_optimize to 2 to avoid inserting an
7390 hold_mips_optimize = mips_optimize;
7392 /* Itbl support may require additional care here. */
7393 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7394 BFD_RELOC_GPREL16, tempreg);
7395 mips_optimize = hold_mips_optimize;
7399 offset_expr.X_add_number -= 4;
7402 macro_build_lui (&offset_expr, AT);
7404 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7405 /* Itbl support may require additional care here. */
7406 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7407 BFD_RELOC_LO16, AT);
7408 /* FIXME: How do we handle overflow here? */
7409 offset_expr.X_add_number += 4;
7410 /* Itbl support may require additional care here. */
7411 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7412 BFD_RELOC_LO16, AT);
7413 if (mips_relax.sequence)
7416 else if (!mips_big_got)
7418 /* If this is a reference to an external symbol, we want
7419 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7424 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7426 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7427 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7428 If there is a base register we add it to $at before the
7429 lwc1 instructions. If there is a constant we include it
7430 in the lwc1 instructions. */
7432 expr1.X_add_number = offset_expr.X_add_number;
7433 if (expr1.X_add_number < -0x8000
7434 || expr1.X_add_number >= 0x8000 - 4)
7435 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7436 load_got_offset (AT, &offset_expr);
7439 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7441 /* Set mips_optimize to 2 to avoid inserting an undesired
7443 hold_mips_optimize = mips_optimize;
7446 /* Itbl support may require additional care here. */
7447 relax_start (offset_expr.X_add_symbol);
7448 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
7449 BFD_RELOC_LO16, AT);
7450 expr1.X_add_number += 4;
7451 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
7452 BFD_RELOC_LO16, AT);
7454 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7455 BFD_RELOC_LO16, AT);
7456 offset_expr.X_add_number += 4;
7457 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7458 BFD_RELOC_LO16, AT);
7461 mips_optimize = hold_mips_optimize;
7463 else if (mips_big_got)
7467 /* If this is a reference to an external symbol, we want
7468 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7470 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
7475 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7477 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7478 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7479 If there is a base register we add it to $at before the
7480 lwc1 instructions. If there is a constant we include it
7481 in the lwc1 instructions. */
7483 expr1.X_add_number = offset_expr.X_add_number;
7484 offset_expr.X_add_number = 0;
7485 if (expr1.X_add_number < -0x8000
7486 || expr1.X_add_number >= 0x8000 - 4)
7487 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7488 gpdelay = reg_needs_delay (mips_gp_register);
7489 relax_start (offset_expr.X_add_symbol);
7490 macro_build (&offset_expr, "lui", "t,u",
7491 AT, BFD_RELOC_MIPS_GOT_HI16);
7492 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7493 AT, AT, mips_gp_register);
7494 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7495 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
7498 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7499 /* Itbl support may require additional care here. */
7500 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
7501 BFD_RELOC_LO16, AT);
7502 expr1.X_add_number += 4;
7504 /* Set mips_optimize to 2 to avoid inserting an undesired
7506 hold_mips_optimize = mips_optimize;
7508 /* Itbl support may require additional care here. */
7509 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
7510 BFD_RELOC_LO16, AT);
7511 mips_optimize = hold_mips_optimize;
7512 expr1.X_add_number -= 4;
7515 offset_expr.X_add_number = expr1.X_add_number;
7517 macro_build (NULL, "nop", "");
7518 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7519 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7522 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7523 /* Itbl support may require additional care here. */
7524 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7525 BFD_RELOC_LO16, AT);
7526 offset_expr.X_add_number += 4;
7528 /* Set mips_optimize to 2 to avoid inserting an undesired
7530 hold_mips_optimize = mips_optimize;
7532 /* Itbl support may require additional care here. */
7533 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7534 BFD_RELOC_LO16, AT);
7535 mips_optimize = hold_mips_optimize;
7544 s = HAVE_64BIT_GPRS ? "ld" : "lw";
7547 s = HAVE_64BIT_GPRS ? "sd" : "sw";
7549 macro_build (&offset_expr, s, "t,o(b)", treg,
7550 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
7552 if (!HAVE_64BIT_GPRS)
7554 offset_expr.X_add_number += 4;
7555 macro_build (&offset_expr, s, "t,o(b)", treg + 1,
7556 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
7561 /* New code added to support COPZ instructions.
7562 This code builds table entries out of the macros in mip_opcodes.
7563 R4000 uses interlocks to handle coproc delays.
7564 Other chips (like the R3000) require nops to be inserted for delays.
7566 FIXME: Currently, we require that the user handle delays.
7567 In order to fill delay slots for non-interlocked chips,
7568 we must have a way to specify delays based on the coprocessor.
7569 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7570 What are the side-effects of the cop instruction?
7571 What cache support might we have and what are its effects?
7572 Both coprocessor & memory require delays. how long???
7573 What registers are read/set/modified?
7575 If an itbl is provided to interpret cop instructions,
7576 this knowledge can be encoded in the itbl spec. */
7590 if (NO_ISA_COP (mips_opts.arch)
7591 && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0)
7593 as_bad (_("opcode not supported on this processor: %s"),
7594 mips_cpu_info_from_arch (mips_opts.arch)->name);
7598 /* For now we just do C (same as Cz). The parameter will be
7599 stored in insn_opcode by mips_ip. */
7600 macro_build (NULL, s, "C", ip->insn_opcode);
7604 move_register (dreg, sreg);
7610 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
7611 macro_build (NULL, "mflo", "d", dreg);
7617 /* The MIPS assembler some times generates shifts and adds. I'm
7618 not trying to be that fancy. GCC should do this for us
7621 load_register (AT, &imm_expr, dbl);
7622 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
7623 macro_build (NULL, "mflo", "d", dreg);
7639 load_register (AT, &imm_expr, dbl);
7640 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
7641 macro_build (NULL, "mflo", "d", dreg);
7642 macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
7643 macro_build (NULL, "mfhi", "d", AT);
7645 macro_build (NULL, "tne", "s,t,q", dreg, AT, 6);
7648 expr1.X_add_number = 8;
7649 macro_build (&expr1, "beq", "s,t,p", dreg, AT);
7650 macro_build (NULL, "nop", "");
7651 macro_build (NULL, "break", "c", 6);
7654 macro_build (NULL, "mflo", "d", dreg);
7670 load_register (AT, &imm_expr, dbl);
7671 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
7672 sreg, imm ? AT : treg);
7673 macro_build (NULL, "mfhi", "d", AT);
7674 macro_build (NULL, "mflo", "d", dreg);
7676 macro_build (NULL, "tne", "s,t,q", AT, ZERO, 6);
7679 expr1.X_add_number = 8;
7680 macro_build (&expr1, "beq", "s,t,p", AT, ZERO);
7681 macro_build (NULL, "nop", "");
7682 macro_build (NULL, "break", "c", 6);
7688 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7699 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
7700 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
7704 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
7705 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
7706 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
7707 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7711 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7722 macro_build (NULL, "negu", "d,w", tempreg, treg);
7723 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
7727 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
7728 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
7729 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
7730 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7739 if (imm_expr.X_op != O_constant)
7740 as_bad (_("Improper rotate count"));
7741 rot = imm_expr.X_add_number & 0x3f;
7742 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7744 rot = (64 - rot) & 0x3f;
7746 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7748 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7753 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7756 l = (rot < 0x20) ? "dsll" : "dsll32";
7757 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
7760 macro_build (NULL, l, "d,w,<", AT, sreg, rot);
7761 macro_build (NULL, rr, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7762 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7770 if (imm_expr.X_op != O_constant)
7771 as_bad (_("Improper rotate count"));
7772 rot = imm_expr.X_add_number & 0x1f;
7773 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7775 macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f);
7780 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7784 macro_build (NULL, "sll", "d,w,<", AT, sreg, rot);
7785 macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7786 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7791 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7793 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
7797 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
7798 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
7799 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
7800 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7804 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7806 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
7810 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
7811 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
7812 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
7813 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7822 if (imm_expr.X_op != O_constant)
7823 as_bad (_("Improper rotate count"));
7824 rot = imm_expr.X_add_number & 0x3f;
7825 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7828 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7830 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7835 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7838 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
7839 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7842 macro_build (NULL, rr, "d,w,<", AT, sreg, rot);
7843 macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7844 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7852 if (imm_expr.X_op != O_constant)
7853 as_bad (_("Improper rotate count"));
7854 rot = imm_expr.X_add_number & 0x1f;
7855 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7857 macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot);
7862 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7866 macro_build (NULL, "srl", "d,w,<", AT, sreg, rot);
7867 macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7868 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7874 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
7876 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7879 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7880 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7885 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7887 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7892 as_warn (_("Instruction %s: result is always false"),
7894 move_register (dreg, 0);
7897 if (CPU_HAS_SEQ (mips_opts.arch)
7898 && -512 <= imm_expr.X_add_number
7899 && imm_expr.X_add_number < 512)
7901 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
7902 (int) imm_expr.X_add_number);
7905 if (imm_expr.X_op == O_constant
7906 && imm_expr.X_add_number >= 0
7907 && imm_expr.X_add_number < 0x10000)
7909 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7911 else if (imm_expr.X_op == O_constant
7912 && imm_expr.X_add_number > -0x8000
7913 && imm_expr.X_add_number < 0)
7915 imm_expr.X_add_number = -imm_expr.X_add_number;
7916 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7917 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7919 else if (CPU_HAS_SEQ (mips_opts.arch))
7922 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7923 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
7928 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7929 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7932 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7935 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
7941 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
7942 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7945 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
7947 if (imm_expr.X_op == O_constant
7948 && imm_expr.X_add_number >= -0x8000
7949 && imm_expr.X_add_number < 0x8000)
7951 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
7952 dreg, sreg, BFD_RELOC_LO16);
7956 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7957 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
7961 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7964 case M_SGT: /* sreg > treg <==> treg < sreg */
7970 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7973 case M_SGT_I: /* sreg > I <==> I < sreg */
7980 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7981 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7984 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7990 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7991 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7994 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
8001 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8002 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
8003 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
8007 if (imm_expr.X_op == O_constant
8008 && imm_expr.X_add_number >= -0x8000
8009 && imm_expr.X_add_number < 0x8000)
8011 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
8015 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8016 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
8020 if (imm_expr.X_op == O_constant
8021 && imm_expr.X_add_number >= -0x8000
8022 && imm_expr.X_add_number < 0x8000)
8024 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
8029 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8030 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
8035 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
8037 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
8040 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
8041 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
8046 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
8048 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
8053 as_warn (_("Instruction %s: result is always true"),
8055 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
8056 dreg, 0, BFD_RELOC_LO16);
8059 if (CPU_HAS_SEQ (mips_opts.arch)
8060 && -512 <= imm_expr.X_add_number
8061 && imm_expr.X_add_number < 512)
8063 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
8064 (int) imm_expr.X_add_number);
8067 if (imm_expr.X_op == O_constant
8068 && imm_expr.X_add_number >= 0
8069 && imm_expr.X_add_number < 0x10000)
8071 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
8073 else if (imm_expr.X_op == O_constant
8074 && imm_expr.X_add_number > -0x8000
8075 && imm_expr.X_add_number < 0)
8077 imm_expr.X_add_number = -imm_expr.X_add_number;
8078 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
8079 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
8081 else if (CPU_HAS_SEQ (mips_opts.arch))
8084 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8085 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
8090 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8091 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
8094 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
8100 if (imm_expr.X_op == O_constant
8101 && imm_expr.X_add_number > -0x8000
8102 && imm_expr.X_add_number <= 0x8000)
8104 imm_expr.X_add_number = -imm_expr.X_add_number;
8105 macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j",
8106 dreg, sreg, BFD_RELOC_LO16);
8110 load_register (AT, &imm_expr, dbl);
8111 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
8117 if (imm_expr.X_op == O_constant
8118 && imm_expr.X_add_number > -0x8000
8119 && imm_expr.X_add_number <= 0x8000)
8121 imm_expr.X_add_number = -imm_expr.X_add_number;
8122 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j",
8123 dreg, sreg, BFD_RELOC_LO16);
8127 load_register (AT, &imm_expr, dbl);
8128 macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
8150 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8151 macro_build (NULL, s, "s,t", sreg, AT);
8156 gas_assert (mips_opts.isa == ISA_MIPS1);
8158 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
8159 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
8162 * Is the double cfc1 instruction a bug in the mips assembler;
8163 * or is there a reason for it?
8166 macro_build (NULL, "cfc1", "t,G", treg, RA);
8167 macro_build (NULL, "cfc1", "t,G", treg, RA);
8168 macro_build (NULL, "nop", "");
8169 expr1.X_add_number = 3;
8170 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
8171 expr1.X_add_number = 2;
8172 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
8173 macro_build (NULL, "ctc1", "t,G", AT, RA);
8174 macro_build (NULL, "nop", "");
8175 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
8177 macro_build (NULL, "ctc1", "t,G", treg, RA);
8178 macro_build (NULL, "nop", "");
8189 if (offset_expr.X_add_number >= 0x7fff)
8190 as_bad (_("Operand overflow"));
8191 if (!target_big_endian)
8192 ++offset_expr.X_add_number;
8193 macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg);
8194 if (!target_big_endian)
8195 --offset_expr.X_add_number;
8197 ++offset_expr.X_add_number;
8198 macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg);
8199 macro_build (NULL, "sll", "d,w,<", AT, AT, 8);
8200 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8213 if (offset_expr.X_add_number >= 0x8000 - off)
8214 as_bad (_("Operand overflow"));
8222 if (!target_big_endian)
8223 offset_expr.X_add_number += off;
8224 macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
8225 if (!target_big_endian)
8226 offset_expr.X_add_number -= off;
8228 offset_expr.X_add_number += off;
8229 macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
8231 /* If necessary, move the result in tempreg to the final destination. */
8232 if (treg == tempreg)
8234 /* Protect second load's delay slot. */
8236 move_register (treg, tempreg);
8250 load_address (AT, &offset_expr, &used_at);
8252 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8253 if (!target_big_endian)
8254 expr1.X_add_number = off;
8256 expr1.X_add_number = 0;
8257 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8258 if (!target_big_endian)
8259 expr1.X_add_number = 0;
8261 expr1.X_add_number = off;
8262 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8268 load_address (AT, &offset_expr, &used_at);
8270 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8271 if (target_big_endian)
8272 expr1.X_add_number = 0;
8273 macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
8274 treg, BFD_RELOC_LO16, AT);
8275 if (target_big_endian)
8276 expr1.X_add_number = 1;
8278 expr1.X_add_number = 0;
8279 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
8280 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
8281 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8286 if (offset_expr.X_add_number >= 0x7fff)
8287 as_bad (_("Operand overflow"));
8288 if (target_big_endian)
8289 ++offset_expr.X_add_number;
8290 macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg);
8291 macro_build (NULL, "srl", "d,w,<", AT, treg, 8);
8292 if (target_big_endian)
8293 --offset_expr.X_add_number;
8295 ++offset_expr.X_add_number;
8296 macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg);
8309 if (offset_expr.X_add_number >= 0x8000 - off)
8310 as_bad (_("Operand overflow"));
8311 if (!target_big_endian)
8312 offset_expr.X_add_number += off;
8313 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8314 if (!target_big_endian)
8315 offset_expr.X_add_number -= off;
8317 offset_expr.X_add_number += off;
8318 macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8332 load_address (AT, &offset_expr, &used_at);
8334 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8335 if (!target_big_endian)
8336 expr1.X_add_number = off;
8338 expr1.X_add_number = 0;
8339 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8340 if (!target_big_endian)
8341 expr1.X_add_number = 0;
8343 expr1.X_add_number = off;
8344 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8349 load_address (AT, &offset_expr, &used_at);
8351 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8352 if (!target_big_endian)
8353 expr1.X_add_number = 0;
8354 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8355 macro_build (NULL, "srl", "d,w,<", treg, treg, 8);
8356 if (!target_big_endian)
8357 expr1.X_add_number = 1;
8359 expr1.X_add_number = 0;
8360 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8361 if (!target_big_endian)
8362 expr1.X_add_number = 0;
8364 expr1.X_add_number = 1;
8365 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
8366 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
8367 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8371 /* FIXME: Check if this is one of the itbl macros, since they
8372 are added dynamically. */
8373 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
8376 if (!mips_opts.at && used_at)
8377 as_bad (_("Macro used $at after \".set noat\""));
8380 /* Implement macros in mips16 mode. */
8383 mips16_macro (struct mips_cl_insn *ip)
8386 int xreg, yreg, zreg, tmp;
8389 const char *s, *s2, *s3;
8391 mask = ip->insn_mo->mask;
8393 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
8394 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
8395 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
8397 expr1.X_op = O_constant;
8398 expr1.X_op_symbol = NULL;
8399 expr1.X_add_symbol = NULL;
8400 expr1.X_add_number = 1;
8420 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
8421 expr1.X_add_number = 2;
8422 macro_build (&expr1, "bnez", "x,p", yreg);
8423 macro_build (NULL, "break", "6", 7);
8425 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
8426 since that causes an overflow. We should do that as well,
8427 but I don't see how to do the comparisons without a temporary
8430 macro_build (NULL, s, "x", zreg);
8450 macro_build (NULL, s, "0,x,y", xreg, yreg);
8451 expr1.X_add_number = 2;
8452 macro_build (&expr1, "bnez", "x,p", yreg);
8453 macro_build (NULL, "break", "6", 7);
8455 macro_build (NULL, s2, "x", zreg);
8461 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
8462 macro_build (NULL, "mflo", "x", zreg);
8470 if (imm_expr.X_op != O_constant)
8471 as_bad (_("Unsupported large constant"));
8472 imm_expr.X_add_number = -imm_expr.X_add_number;
8473 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
8477 if (imm_expr.X_op != O_constant)
8478 as_bad (_("Unsupported large constant"));
8479 imm_expr.X_add_number = -imm_expr.X_add_number;
8480 macro_build (&imm_expr, "addiu", "x,k", xreg);
8484 if (imm_expr.X_op != O_constant)
8485 as_bad (_("Unsupported large constant"));
8486 imm_expr.X_add_number = -imm_expr.X_add_number;
8487 macro_build (&imm_expr, "daddiu", "y,j", yreg);
8509 goto do_reverse_branch;
8513 goto do_reverse_branch;
8525 goto do_reverse_branch;
8536 macro_build (NULL, s, "x,y", xreg, yreg);
8537 macro_build (&offset_expr, s2, "p");
8564 goto do_addone_branch_i;
8569 goto do_addone_branch_i;
8584 goto do_addone_branch_i;
8591 if (imm_expr.X_op != O_constant)
8592 as_bad (_("Unsupported large constant"));
8593 ++imm_expr.X_add_number;
8596 macro_build (&imm_expr, s, s3, xreg);
8597 macro_build (&offset_expr, s2, "p");
8601 expr1.X_add_number = 0;
8602 macro_build (&expr1, "slti", "x,8", yreg);
8604 move_register (xreg, yreg);
8605 expr1.X_add_number = 2;
8606 macro_build (&expr1, "bteqz", "p");
8607 macro_build (NULL, "neg", "x,w", xreg, xreg);
8611 /* For consistency checking, verify that all bits are specified either
8612 by the match/mask part of the instruction definition, or by the
8615 validate_mips_insn (const struct mips_opcode *opc)
8617 const char *p = opc->args;
8619 unsigned long used_bits = opc->mask;
8621 if ((used_bits & opc->match) != opc->match)
8623 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8624 opc->name, opc->args);
8627 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8637 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
8638 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
8639 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
8640 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
8641 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8642 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8643 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8644 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
8645 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8646 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8647 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8648 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8649 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8651 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8652 case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
8653 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8654 case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
8655 case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
8656 case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
8657 case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
8658 case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
8659 case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
8660 case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
8661 case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break;
8662 case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break;
8663 case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break;
8664 case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break;
8665 case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break;
8668 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8669 c, opc->name, opc->args);
8673 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8674 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8676 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
8677 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
8678 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8679 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8681 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8682 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8684 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
8685 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8687 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
8688 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
8689 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
8690 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
8691 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8692 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
8693 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8694 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8695 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8696 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8697 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8698 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8699 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8700 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
8701 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8702 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
8703 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8705 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
8706 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8707 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8708 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
8710 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8711 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8712 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
8713 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8714 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8715 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8716 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8717 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8718 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8721 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
8722 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
8723 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8724 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
8725 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
8728 case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8729 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
8730 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
8731 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
8732 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
8733 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8734 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
8735 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
8736 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
8737 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
8738 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
8739 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
8740 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
8741 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
8742 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
8743 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
8744 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
8745 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8747 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8748 c, opc->name, opc->args);
8752 if (used_bits != 0xffffffff)
8754 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8755 ~used_bits & 0xffffffff, opc->name, opc->args);
8761 /* UDI immediates. */
8769 static const struct mips_immed mips_immed[] = {
8770 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
8771 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
8772 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
8773 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
8777 /* Check whether an odd floating-point register is allowed. */
8779 mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
8781 const char *s = insn->name;
8783 if (insn->pinfo == INSN_MACRO)
8784 /* Let a macro pass, we'll catch it later when it is expanded. */
8787 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa))
8789 /* Allow odd registers for single-precision ops. */
8790 switch (insn->pinfo & (FP_S | FP_D))
8794 return 1; /* both single precision - ok */
8796 return 0; /* both double precision - fail */
8801 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
8802 s = strchr (insn->name, '.');
8804 s = s != NULL ? strchr (s + 1, '.') : NULL;
8805 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
8808 /* Single-precision coprocessor loads and moves are OK too. */
8809 if ((insn->pinfo & FP_S)
8810 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
8811 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
8817 /* This routine assembles an instruction into its binary format. As a
8818 side effect, it sets one of the global variables imm_reloc or
8819 offset_reloc to the type of relocation to do if one of the operands
8820 is an address expression. */
8823 mips_ip (char *str, struct mips_cl_insn *ip)
8828 struct mips_opcode *insn;
8831 unsigned int lastregno;
8832 unsigned int lastpos = 0;
8833 unsigned int limlo, limhi;
8836 offsetT min_range, max_range;
8842 /* If the instruction contains a '.', we first try to match an instruction
8843 including the '.'. Then we try again without the '.'. */
8845 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
8848 /* If we stopped on whitespace, then replace the whitespace with null for
8849 the call to hash_find. Save the character we replaced just in case we
8850 have to re-parse the instruction. */
8857 insn = (struct mips_opcode *) hash_find (op_hash, str);
8859 /* If we didn't find the instruction in the opcode table, try again, but
8860 this time with just the instruction up to, but not including the
8864 /* Restore the character we overwrite above (if any). */
8868 /* Scan up to the first '.' or whitespace. */
8870 *s != '\0' && *s != '.' && !ISSPACE (*s);
8874 /* If we did not find a '.', then we can quit now. */
8877 insn_error = _("Unrecognized opcode");
8881 /* Lookup the instruction in the hash table. */
8883 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
8885 insn_error = _("Unrecognized opcode");
8895 gas_assert (strcmp (insn->name, str) == 0);
8897 ok = is_opcode_valid (insn);
8900 if (insn + 1 < &mips_opcodes[NUMOPCODES]
8901 && strcmp (insn->name, insn[1].name) == 0)
8910 static char buf[100];
8912 _("opcode not supported on this processor: %s (%s)"),
8913 mips_cpu_info_from_arch (mips_opts.arch)->name,
8914 mips_cpu_info_from_isa (mips_opts.isa)->name);
8923 create_insn (ip, insn);
8926 lastregno = 0xffffffff;
8927 for (args = insn->args;; ++args)
8931 s += strspn (s, " \t");
8935 case '\0': /* end of args */
8940 case '2': /* DSP 2-bit unsigned immediate in bit 11. */
8941 my_getExpression (&imm_expr, s);
8942 check_absolute_expr (ip, &imm_expr);
8943 if ((unsigned long) imm_expr.X_add_number != 1
8944 && (unsigned long) imm_expr.X_add_number != 3)
8946 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
8947 (unsigned long) imm_expr.X_add_number);
8949 INSERT_OPERAND (BP, *ip, imm_expr.X_add_number);
8950 imm_expr.X_op = O_absent;
8954 case '3': /* DSP 3-bit unsigned immediate in bit 21. */
8955 my_getExpression (&imm_expr, s);
8956 check_absolute_expr (ip, &imm_expr);
8957 if (imm_expr.X_add_number & ~OP_MASK_SA3)
8959 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8960 OP_MASK_SA3, (unsigned long) imm_expr.X_add_number);
8962 INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number);
8963 imm_expr.X_op = O_absent;
8967 case '4': /* DSP 4-bit unsigned immediate in bit 21. */
8968 my_getExpression (&imm_expr, s);
8969 check_absolute_expr (ip, &imm_expr);
8970 if (imm_expr.X_add_number & ~OP_MASK_SA4)
8972 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8973 OP_MASK_SA4, (unsigned long) imm_expr.X_add_number);
8975 INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number);
8976 imm_expr.X_op = O_absent;
8980 case '5': /* DSP 8-bit unsigned immediate in bit 16. */
8981 my_getExpression (&imm_expr, s);
8982 check_absolute_expr (ip, &imm_expr);
8983 if (imm_expr.X_add_number & ~OP_MASK_IMM8)
8985 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8986 OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number);
8988 INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number);
8989 imm_expr.X_op = O_absent;
8993 case '6': /* DSP 5-bit unsigned immediate in bit 21. */
8994 my_getExpression (&imm_expr, s);
8995 check_absolute_expr (ip, &imm_expr);
8996 if (imm_expr.X_add_number & ~OP_MASK_RS)
8998 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8999 OP_MASK_RS, (unsigned long) imm_expr.X_add_number);
9001 INSERT_OPERAND (RS, *ip, imm_expr.X_add_number);
9002 imm_expr.X_op = O_absent;
9006 case '7': /* Four DSP accumulators in bits 11,12. */
9007 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9008 s[3] >= '0' && s[3] <= '3')
9012 INSERT_OPERAND (DSPACC, *ip, regno);
9016 as_bad (_("Invalid dsp acc register"));
9019 case '8': /* DSP 6-bit unsigned immediate in bit 11. */
9020 my_getExpression (&imm_expr, s);
9021 check_absolute_expr (ip, &imm_expr);
9022 if (imm_expr.X_add_number & ~OP_MASK_WRDSP)
9024 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9026 (unsigned long) imm_expr.X_add_number);
9028 INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number);
9029 imm_expr.X_op = O_absent;
9033 case '9': /* Four DSP accumulators in bits 21,22. */
9034 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9035 s[3] >= '0' && s[3] <= '3')
9039 INSERT_OPERAND (DSPACC_S, *ip, regno);
9043 as_bad (_("Invalid dsp acc register"));
9046 case '0': /* DSP 6-bit signed immediate in bit 20. */
9047 my_getExpression (&imm_expr, s);
9048 check_absolute_expr (ip, &imm_expr);
9049 min_range = -((OP_MASK_DSPSFT + 1) >> 1);
9050 max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1;
9051 if (imm_expr.X_add_number < min_range ||
9052 imm_expr.X_add_number > max_range)
9054 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
9055 (long) min_range, (long) max_range,
9056 (long) imm_expr.X_add_number);
9058 INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number);
9059 imm_expr.X_op = O_absent;
9063 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
9064 my_getExpression (&imm_expr, s);
9065 check_absolute_expr (ip, &imm_expr);
9066 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
9068 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9070 (unsigned long) imm_expr.X_add_number);
9072 INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number);
9073 imm_expr.X_op = O_absent;
9077 case ':': /* DSP 7-bit signed immediate in bit 19. */
9078 my_getExpression (&imm_expr, s);
9079 check_absolute_expr (ip, &imm_expr);
9080 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
9081 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
9082 if (imm_expr.X_add_number < min_range ||
9083 imm_expr.X_add_number > max_range)
9085 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
9086 (long) min_range, (long) max_range,
9087 (long) imm_expr.X_add_number);
9089 INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number);
9090 imm_expr.X_op = O_absent;
9094 case '@': /* DSP 10-bit signed immediate in bit 16. */
9095 my_getExpression (&imm_expr, s);
9096 check_absolute_expr (ip, &imm_expr);
9097 min_range = -((OP_MASK_IMM10 + 1) >> 1);
9098 max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1;
9099 if (imm_expr.X_add_number < min_range ||
9100 imm_expr.X_add_number > max_range)
9102 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
9103 (long) min_range, (long) max_range,
9104 (long) imm_expr.X_add_number);
9106 INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number);
9107 imm_expr.X_op = O_absent;
9111 case '!': /* MT usermode flag bit. */
9112 my_getExpression (&imm_expr, s);
9113 check_absolute_expr (ip, &imm_expr);
9114 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
9115 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
9116 (unsigned long) imm_expr.X_add_number);
9117 INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number);
9118 imm_expr.X_op = O_absent;
9122 case '$': /* MT load high flag bit. */
9123 my_getExpression (&imm_expr, s);
9124 check_absolute_expr (ip, &imm_expr);
9125 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
9126 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
9127 (unsigned long) imm_expr.X_add_number);
9128 INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number);
9129 imm_expr.X_op = O_absent;
9133 case '*': /* Four DSP accumulators in bits 18,19. */
9134 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9135 s[3] >= '0' && s[3] <= '3')
9139 INSERT_OPERAND (MTACC_T, *ip, regno);
9143 as_bad (_("Invalid dsp/smartmips acc register"));
9146 case '&': /* Four DSP accumulators in bits 13,14. */
9147 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9148 s[3] >= '0' && s[3] <= '3')
9152 INSERT_OPERAND (MTACC_D, *ip, regno);
9156 as_bad (_("Invalid dsp/smartmips acc register"));
9168 INSERT_OPERAND (RS, *ip, lastregno);
9172 INSERT_OPERAND (RT, *ip, lastregno);
9176 INSERT_OPERAND (FT, *ip, lastregno);
9180 INSERT_OPERAND (FS, *ip, lastregno);
9186 /* Handle optional base register.
9187 Either the base register is omitted or
9188 we must have a left paren. */
9189 /* This is dependent on the next operand specifier
9190 is a base register specification. */
9191 gas_assert (args[1] == 'b');
9195 case ')': /* These must match exactly. */
9202 case '+': /* Opcode extension character. */
9205 case '1': /* UDI immediates. */
9210 const struct mips_immed *imm = mips_immed;
9212 while (imm->type && imm->type != *args)
9216 my_getExpression (&imm_expr, s);
9217 check_absolute_expr (ip, &imm_expr);
9218 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
9220 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
9221 imm->desc ? imm->desc : ip->insn_mo->name,
9222 (unsigned long) imm_expr.X_add_number,
9223 (unsigned long) imm_expr.X_add_number);
9224 imm_expr.X_add_number &= imm->mask;
9226 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
9228 imm_expr.X_op = O_absent;
9233 case 'A': /* ins/ext position, becomes LSB. */
9242 my_getExpression (&imm_expr, s);
9243 check_absolute_expr (ip, &imm_expr);
9244 if ((unsigned long) imm_expr.X_add_number < limlo
9245 || (unsigned long) imm_expr.X_add_number > limhi)
9247 as_bad (_("Improper position (%lu)"),
9248 (unsigned long) imm_expr.X_add_number);
9249 imm_expr.X_add_number = limlo;
9251 lastpos = imm_expr.X_add_number;
9252 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9253 imm_expr.X_op = O_absent;
9257 case 'B': /* ins size, becomes MSB. */
9266 my_getExpression (&imm_expr, s);
9267 check_absolute_expr (ip, &imm_expr);
9268 /* Check for negative input so that small negative numbers
9269 will not succeed incorrectly. The checks against
9270 (pos+size) transitively check "size" itself,
9271 assuming that "pos" is reasonable. */
9272 if ((long) imm_expr.X_add_number < 0
9273 || ((unsigned long) imm_expr.X_add_number
9275 || ((unsigned long) imm_expr.X_add_number
9278 as_bad (_("Improper insert size (%lu, position %lu)"),
9279 (unsigned long) imm_expr.X_add_number,
9280 (unsigned long) lastpos);
9281 imm_expr.X_add_number = limlo - lastpos;
9283 INSERT_OPERAND (INSMSB, *ip,
9284 lastpos + imm_expr.X_add_number - 1);
9285 imm_expr.X_op = O_absent;
9289 case 'C': /* ext size, becomes MSBD. */
9302 my_getExpression (&imm_expr, s);
9303 check_absolute_expr (ip, &imm_expr);
9304 /* Check for negative input so that small negative numbers
9305 will not succeed incorrectly. The checks against
9306 (pos+size) transitively check "size" itself,
9307 assuming that "pos" is reasonable. */
9308 if ((long) imm_expr.X_add_number < 0
9309 || ((unsigned long) imm_expr.X_add_number
9311 || ((unsigned long) imm_expr.X_add_number
9314 as_bad (_("Improper extract size (%lu, position %lu)"),
9315 (unsigned long) imm_expr.X_add_number,
9316 (unsigned long) lastpos);
9317 imm_expr.X_add_number = limlo - lastpos;
9319 INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1);
9320 imm_expr.X_op = O_absent;
9325 /* +D is for disassembly only; never match. */
9329 /* "+I" is like "I", except that imm2_expr is used. */
9330 my_getExpression (&imm2_expr, s);
9331 if (imm2_expr.X_op != O_big
9332 && imm2_expr.X_op != O_constant)
9333 insn_error = _("absolute expression required");
9334 if (HAVE_32BIT_GPRS)
9335 normalize_constant_expr (&imm2_expr);
9339 case 'T': /* Coprocessor register. */
9340 /* +T is for disassembly only; never match. */
9343 case 't': /* Coprocessor register number. */
9344 if (s[0] == '$' && ISDIGIT (s[1]))
9354 while (ISDIGIT (*s));
9356 as_bad (_("Invalid register number (%d)"), regno);
9359 INSERT_OPERAND (RT, *ip, regno);
9364 as_bad (_("Invalid coprocessor 0 register number"));
9368 /* bbit[01] and bbit[01]32 bit index. Give error if index
9369 is not in the valid range. */
9370 my_getExpression (&imm_expr, s);
9371 check_absolute_expr (ip, &imm_expr);
9372 if ((unsigned) imm_expr.X_add_number > 31)
9374 as_bad (_("Improper bit index (%lu)"),
9375 (unsigned long) imm_expr.X_add_number);
9376 imm_expr.X_add_number = 0;
9378 INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number);
9379 imm_expr.X_op = O_absent;
9384 /* bbit[01] bit index when bbit is used but we generate
9385 bbit[01]32 because the index is over 32. Move to the
9386 next candidate if index is not in the valid range. */
9387 my_getExpression (&imm_expr, s);
9388 check_absolute_expr (ip, &imm_expr);
9389 if ((unsigned) imm_expr.X_add_number < 32
9390 || (unsigned) imm_expr.X_add_number > 63)
9392 INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number - 32);
9393 imm_expr.X_op = O_absent;
9398 /* cins, cins32, exts and exts32 position field. Give error
9399 if it's not in the valid range. */
9400 my_getExpression (&imm_expr, s);
9401 check_absolute_expr (ip, &imm_expr);
9402 if ((unsigned) imm_expr.X_add_number > 31)
9404 as_bad (_("Improper position (%lu)"),
9405 (unsigned long) imm_expr.X_add_number);
9406 imm_expr.X_add_number = 0;
9408 /* Make the pos explicit to simplify +S. */
9409 lastpos = imm_expr.X_add_number + 32;
9410 INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number);
9411 imm_expr.X_op = O_absent;
9416 /* cins, cins32, exts and exts32 position field. Move to
9417 the next candidate if it's not in the valid range. */
9418 my_getExpression (&imm_expr, s);
9419 check_absolute_expr (ip, &imm_expr);
9420 if ((unsigned) imm_expr.X_add_number < 32
9421 || (unsigned) imm_expr.X_add_number > 63)
9423 lastpos = imm_expr.X_add_number;
9424 INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number - 32);
9425 imm_expr.X_op = O_absent;
9430 /* cins and exts length-minus-one field. */
9431 my_getExpression (&imm_expr, s);
9432 check_absolute_expr (ip, &imm_expr);
9433 if ((unsigned long) imm_expr.X_add_number > 31)
9435 as_bad (_("Improper size (%lu)"),
9436 (unsigned long) imm_expr.X_add_number);
9437 imm_expr.X_add_number = 0;
9439 INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number);
9440 imm_expr.X_op = O_absent;
9445 /* cins32/exts32 and cins/exts aliasing cint32/exts32
9446 length-minus-one field. */
9447 my_getExpression (&imm_expr, s);
9448 check_absolute_expr (ip, &imm_expr);
9449 if ((long) imm_expr.X_add_number < 0
9450 || (unsigned long) imm_expr.X_add_number + lastpos > 63)
9452 as_bad (_("Improper size (%lu)"),
9453 (unsigned long) imm_expr.X_add_number);
9454 imm_expr.X_add_number = 0;
9456 INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number);
9457 imm_expr.X_op = O_absent;
9462 /* seqi/snei immediate field. */
9463 my_getExpression (&imm_expr, s);
9464 check_absolute_expr (ip, &imm_expr);
9465 if ((long) imm_expr.X_add_number < -512
9466 || (long) imm_expr.X_add_number >= 512)
9468 as_bad (_("Improper immediate (%ld)"),
9469 (long) imm_expr.X_add_number);
9470 imm_expr.X_add_number = 0;
9472 INSERT_OPERAND (SEQI, *ip, imm_expr.X_add_number);
9473 imm_expr.X_op = O_absent;
9477 case 'a': /* 8-bit signed offset in bit 6 */
9478 my_getExpression (&imm_expr, s);
9479 check_absolute_expr (ip, &imm_expr);
9480 min_range = -((OP_MASK_OFFSET_A + 1) >> 1);
9481 max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1;
9482 if (imm_expr.X_add_number < min_range
9483 || imm_expr.X_add_number > max_range)
9485 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9486 (long) min_range, (long) max_range,
9487 (long) imm_expr.X_add_number);
9489 INSERT_OPERAND (OFFSET_A, *ip, imm_expr.X_add_number);
9490 imm_expr.X_op = O_absent;
9494 case 'b': /* 8-bit signed offset in bit 3 */
9495 my_getExpression (&imm_expr, s);
9496 check_absolute_expr (ip, &imm_expr);
9497 min_range = -((OP_MASK_OFFSET_B + 1) >> 1);
9498 max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1;
9499 if (imm_expr.X_add_number < min_range
9500 || imm_expr.X_add_number > max_range)
9502 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9503 (long) min_range, (long) max_range,
9504 (long) imm_expr.X_add_number);
9506 INSERT_OPERAND (OFFSET_B, *ip, imm_expr.X_add_number);
9507 imm_expr.X_op = O_absent;
9511 case 'c': /* 9-bit signed offset in bit 6 */
9512 my_getExpression (&imm_expr, s);
9513 check_absolute_expr (ip, &imm_expr);
9514 min_range = -((OP_MASK_OFFSET_C + 1) >> 1);
9515 max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1;
9516 /* We check the offset range before adjusted. */
9519 if (imm_expr.X_add_number < min_range
9520 || imm_expr.X_add_number > max_range)
9522 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9523 (long) min_range, (long) max_range,
9524 (long) imm_expr.X_add_number);
9526 if (imm_expr.X_add_number & 0xf)
9528 as_bad (_("Offset not 16 bytes alignment (%ld)"),
9529 (long) imm_expr.X_add_number);
9531 /* Right shift 4 bits to adjust the offset operand. */
9532 INSERT_OPERAND (OFFSET_C, *ip, imm_expr.X_add_number >> 4);
9533 imm_expr.X_op = O_absent;
9538 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
9540 if (regno == AT && mips_opts.at)
9542 if (mips_opts.at == ATREG)
9543 as_warn (_("used $at without \".set noat\""));
9545 as_warn (_("used $%u with \".set at=$%u\""),
9546 regno, mips_opts.at);
9548 INSERT_OPERAND (RZ, *ip, regno);
9552 if (!reg_lookup (&s, RTYPE_FPU, ®no))
9554 INSERT_OPERAND (FZ, *ip, regno);
9558 as_bad (_("Internal error: bad mips opcode "
9559 "(unknown extension operand type `+%c'): %s %s"),
9560 *args, insn->name, insn->args);
9561 /* Further processing is fruitless. */
9566 case '<': /* must be at least one digit */
9568 * According to the manual, if the shift amount is greater
9569 * than 31 or less than 0, then the shift amount should be
9570 * mod 32. In reality the mips assembler issues an error.
9571 * We issue a warning and mask out all but the low 5 bits.
9573 my_getExpression (&imm_expr, s);
9574 check_absolute_expr (ip, &imm_expr);
9575 if ((unsigned long) imm_expr.X_add_number > 31)
9576 as_warn (_("Improper shift amount (%lu)"),
9577 (unsigned long) imm_expr.X_add_number);
9578 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9579 imm_expr.X_op = O_absent;
9583 case '>': /* shift amount minus 32 */
9584 my_getExpression (&imm_expr, s);
9585 check_absolute_expr (ip, &imm_expr);
9586 if ((unsigned long) imm_expr.X_add_number < 32
9587 || (unsigned long) imm_expr.X_add_number > 63)
9589 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32);
9590 imm_expr.X_op = O_absent;
9594 case 'k': /* CACHE code. */
9595 case 'h': /* PREFX code. */
9596 case '1': /* SYNC type. */
9597 my_getExpression (&imm_expr, s);
9598 check_absolute_expr (ip, &imm_expr);
9599 if ((unsigned long) imm_expr.X_add_number > 31)
9600 as_warn (_("Invalid value for `%s' (%lu)"),
9602 (unsigned long) imm_expr.X_add_number);
9605 if (mips_fix_cn63xxp1 && strcmp ("pref", insn->name) == 0)
9606 switch (imm_expr.X_add_number)
9615 case 31: /* These are ok. */
9618 default: /* The rest must be changed to 28. */
9619 imm_expr.X_add_number = 28;
9622 INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number);
9624 else if (*args == 'h')
9625 INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number);
9627 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9628 imm_expr.X_op = O_absent;
9632 case 'c': /* BREAK code. */
9633 my_getExpression (&imm_expr, s);
9634 check_absolute_expr (ip, &imm_expr);
9635 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE)
9636 as_warn (_("Code for %s not in range 0..1023 (%lu)"),
9638 (unsigned long) imm_expr.X_add_number);
9639 INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number);
9640 imm_expr.X_op = O_absent;
9644 case 'q': /* Lower BREAK code. */
9645 my_getExpression (&imm_expr, s);
9646 check_absolute_expr (ip, &imm_expr);
9647 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2)
9648 as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
9650 (unsigned long) imm_expr.X_add_number);
9651 INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number);
9652 imm_expr.X_op = O_absent;
9656 case 'B': /* 20-bit SYSCALL/BREAK code. */
9657 my_getExpression (&imm_expr, s);
9658 check_absolute_expr (ip, &imm_expr);
9659 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
9660 as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
9662 (unsigned long) imm_expr.X_add_number);
9663 INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number);
9664 imm_expr.X_op = O_absent;
9668 case 'C': /* Coprocessor code. */
9669 my_getExpression (&imm_expr, s);
9670 check_absolute_expr (ip, &imm_expr);
9671 if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ)
9673 as_warn (_("Coproccesor code > 25 bits (%lu)"),
9674 (unsigned long) imm_expr.X_add_number);
9675 imm_expr.X_add_number &= OP_MASK_COPZ;
9677 INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number);
9678 imm_expr.X_op = O_absent;
9682 case 'J': /* 19-bit WAIT code. */
9683 my_getExpression (&imm_expr, s);
9684 check_absolute_expr (ip, &imm_expr);
9685 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
9687 as_warn (_("Illegal 19-bit code (%lu)"),
9688 (unsigned long) imm_expr.X_add_number);
9689 imm_expr.X_add_number &= OP_MASK_CODE19;
9691 INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number);
9692 imm_expr.X_op = O_absent;
9696 case 'P': /* Performance register. */
9697 my_getExpression (&imm_expr, s);
9698 check_absolute_expr (ip, &imm_expr);
9699 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
9700 as_warn (_("Invalid performance register (%lu)"),
9701 (unsigned long) imm_expr.X_add_number);
9702 INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number);
9703 imm_expr.X_op = O_absent;
9707 case 'G': /* Coprocessor destination register. */
9708 if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0)
9709 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, ®no);
9711 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
9712 INSERT_OPERAND (RD, *ip, regno);
9721 case 'b': /* Base register. */
9722 case 'd': /* Destination register. */
9723 case 's': /* Source register. */
9724 case 't': /* Target register. */
9725 case 'r': /* Both target and source. */
9726 case 'v': /* Both dest and source. */
9727 case 'w': /* Both dest and target. */
9728 case 'E': /* Coprocessor target register. */
9729 case 'K': /* RDHWR destination register. */
9730 case 'x': /* Ignore register name. */
9731 case 'z': /* Must be zero register. */
9732 case 'U': /* Destination register (CLO/CLZ). */
9733 case 'g': /* Coprocessor destination register. */
9735 if (*args == 'E' || *args == 'K')
9736 ok = reg_lookup (&s, RTYPE_NUM, ®no);
9739 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
9740 if (regno == AT && mips_opts.at)
9742 if (mips_opts.at == ATREG)
9743 as_warn (_("Used $at without \".set noat\""));
9745 as_warn (_("Used $%u with \".set at=$%u\""),
9746 regno, mips_opts.at);
9756 if (c == 'r' || c == 'v' || c == 'w')
9763 /* 'z' only matches $0. */
9764 if (c == 'z' && regno != 0)
9767 if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
9769 if (regno == lastregno)
9772 = _("Source and destination must be different");
9775 if (regno == 31 && lastregno == 0xffffffff)
9778 = _("A destination register must be supplied");
9782 /* Now that we have assembled one operand, we use the args
9783 string to figure out where it goes in the instruction. */
9790 INSERT_OPERAND (RS, *ip, regno);
9795 INSERT_OPERAND (RD, *ip, regno);
9798 INSERT_OPERAND (RD, *ip, regno);
9799 INSERT_OPERAND (RT, *ip, regno);
9804 INSERT_OPERAND (RT, *ip, regno);
9807 /* This case exists because on the r3000 trunc
9808 expands into a macro which requires a gp
9809 register. On the r6000 or r4000 it is
9810 assembled into a single instruction which
9811 ignores the register. Thus the insn version
9812 is MIPS_ISA2 and uses 'x', and the macro
9813 version is MIPS_ISA1 and uses 't'. */
9816 /* This case is for the div instruction, which
9817 acts differently if the destination argument
9818 is $0. This only matches $0, and is checked
9819 outside the switch. */
9829 INSERT_OPERAND (RS, *ip, lastregno);
9832 INSERT_OPERAND (RT, *ip, lastregno);
9837 case 'O': /* MDMX alignment immediate constant. */
9838 my_getExpression (&imm_expr, s);
9839 check_absolute_expr (ip, &imm_expr);
9840 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
9841 as_warn (_("Improper align amount (%ld), using low bits"),
9842 (long) imm_expr.X_add_number);
9843 INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number);
9844 imm_expr.X_op = O_absent;
9848 case 'Q': /* MDMX vector, element sel, or const. */
9851 /* MDMX Immediate. */
9852 my_getExpression (&imm_expr, s);
9853 check_absolute_expr (ip, &imm_expr);
9854 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
9855 as_warn (_("Invalid MDMX Immediate (%ld)"),
9856 (long) imm_expr.X_add_number);
9857 INSERT_OPERAND (FT, *ip, imm_expr.X_add_number);
9858 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
9859 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
9861 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
9862 imm_expr.X_op = O_absent;
9866 /* Not MDMX Immediate. Fall through. */
9867 case 'X': /* MDMX destination register. */
9868 case 'Y': /* MDMX source register. */
9869 case 'Z': /* MDMX target register. */
9871 case 'D': /* Floating point destination register. */
9872 case 'S': /* Floating point source register. */
9873 case 'T': /* Floating point target register. */
9874 case 'R': /* Floating point source register. */
9879 || (mips_opts.ase_mdmx
9880 && (ip->insn_mo->pinfo & FP_D)
9881 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
9882 | INSN_COPROC_MEMORY_DELAY
9883 | INSN_LOAD_COPROC_DELAY
9884 | INSN_LOAD_MEMORY_DELAY
9885 | INSN_STORE_MEMORY))))
9888 if (reg_lookup (&s, rtype, ®no))
9890 if ((regno & 1) != 0
9892 && !mips_oddfpreg_ok (ip->insn_mo, argnum))
9893 as_warn (_("Float register should be even, was %d"),
9901 if (c == 'V' || c == 'W')
9912 INSERT_OPERAND (FD, *ip, regno);
9917 INSERT_OPERAND (FS, *ip, regno);
9920 /* This is like 'Z', but also needs to fix the MDMX
9921 vector/scalar select bits. Note that the
9922 scalar immediate case is handled above. */
9925 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
9926 int max_el = (is_qh ? 3 : 7);
9928 my_getExpression(&imm_expr, s);
9929 check_absolute_expr (ip, &imm_expr);
9931 if (imm_expr.X_add_number > max_el)
9932 as_bad (_("Bad element selector %ld"),
9933 (long) imm_expr.X_add_number);
9934 imm_expr.X_add_number &= max_el;
9935 ip->insn_opcode |= (imm_expr.X_add_number
9938 imm_expr.X_op = O_absent;
9940 as_warn (_("Expecting ']' found '%s'"), s);
9946 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
9947 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
9950 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
9957 INSERT_OPERAND (FT, *ip, regno);
9960 INSERT_OPERAND (FR, *ip, regno);
9970 INSERT_OPERAND (FS, *ip, lastregno);
9973 INSERT_OPERAND (FT, *ip, lastregno);
9979 my_getExpression (&imm_expr, s);
9980 if (imm_expr.X_op != O_big
9981 && imm_expr.X_op != O_constant)
9982 insn_error = _("absolute expression required");
9983 if (HAVE_32BIT_GPRS)
9984 normalize_constant_expr (&imm_expr);
9989 my_getExpression (&offset_expr, s);
9990 normalize_address_expr (&offset_expr);
9991 *imm_reloc = BFD_RELOC_32;
10004 unsigned char temp[8];
10006 unsigned int length;
10011 /* These only appear as the last operand in an
10012 instruction, and every instruction that accepts
10013 them in any variant accepts them in all variants.
10014 This means we don't have to worry about backing out
10015 any changes if the instruction does not match.
10017 The difference between them is the size of the
10018 floating point constant and where it goes. For 'F'
10019 and 'L' the constant is 64 bits; for 'f' and 'l' it
10020 is 32 bits. Where the constant is placed is based
10021 on how the MIPS assembler does things:
10024 f -- immediate value
10027 The .lit4 and .lit8 sections are only used if
10028 permitted by the -G argument.
10030 The code below needs to know whether the target register
10031 is 32 or 64 bits wide. It relies on the fact 'f' and
10032 'F' are used with GPR-based instructions and 'l' and
10033 'L' are used with FPR-based instructions. */
10035 f64 = *args == 'F' || *args == 'L';
10036 using_gprs = *args == 'F' || *args == 'f';
10038 save_in = input_line_pointer;
10039 input_line_pointer = s;
10040 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
10042 s = input_line_pointer;
10043 input_line_pointer = save_in;
10044 if (err != NULL && *err != '\0')
10046 as_bad (_("Bad floating point constant: %s"), err);
10047 memset (temp, '\0', sizeof temp);
10048 length = f64 ? 8 : 4;
10051 gas_assert (length == (unsigned) (f64 ? 8 : 4));
10055 && (g_switch_value < 4
10056 || (temp[0] == 0 && temp[1] == 0)
10057 || (temp[2] == 0 && temp[3] == 0))))
10059 imm_expr.X_op = O_constant;
10060 if (!target_big_endian)
10061 imm_expr.X_add_number = bfd_getl32 (temp);
10063 imm_expr.X_add_number = bfd_getb32 (temp);
10065 else if (length > 4
10066 && !mips_disable_float_construction
10067 /* Constants can only be constructed in GPRs and
10068 copied to FPRs if the GPRs are at least as wide
10069 as the FPRs. Force the constant into memory if
10070 we are using 64-bit FPRs but the GPRs are only
10073 || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
10074 && ((temp[0] == 0 && temp[1] == 0)
10075 || (temp[2] == 0 && temp[3] == 0))
10076 && ((temp[4] == 0 && temp[5] == 0)
10077 || (temp[6] == 0 && temp[7] == 0)))
10079 /* The value is simple enough to load with a couple of
10080 instructions. If using 32-bit registers, set
10081 imm_expr to the high order 32 bits and offset_expr to
10082 the low order 32 bits. Otherwise, set imm_expr to
10083 the entire 64 bit constant. */
10084 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
10086 imm_expr.X_op = O_constant;
10087 offset_expr.X_op = O_constant;
10088 if (!target_big_endian)
10090 imm_expr.X_add_number = bfd_getl32 (temp + 4);
10091 offset_expr.X_add_number = bfd_getl32 (temp);
10095 imm_expr.X_add_number = bfd_getb32 (temp);
10096 offset_expr.X_add_number = bfd_getb32 (temp + 4);
10098 if (offset_expr.X_add_number == 0)
10099 offset_expr.X_op = O_absent;
10101 else if (sizeof (imm_expr.X_add_number) > 4)
10103 imm_expr.X_op = O_constant;
10104 if (!target_big_endian)
10105 imm_expr.X_add_number = bfd_getl64 (temp);
10107 imm_expr.X_add_number = bfd_getb64 (temp);
10111 imm_expr.X_op = O_big;
10112 imm_expr.X_add_number = 4;
10113 if (!target_big_endian)
10115 generic_bignum[0] = bfd_getl16 (temp);
10116 generic_bignum[1] = bfd_getl16 (temp + 2);
10117 generic_bignum[2] = bfd_getl16 (temp + 4);
10118 generic_bignum[3] = bfd_getl16 (temp + 6);
10122 generic_bignum[0] = bfd_getb16 (temp + 6);
10123 generic_bignum[1] = bfd_getb16 (temp + 4);
10124 generic_bignum[2] = bfd_getb16 (temp + 2);
10125 generic_bignum[3] = bfd_getb16 (temp);
10131 const char *newname;
10134 /* Switch to the right section. */
10136 subseg = now_subseg;
10139 default: /* unused default case avoids warnings. */
10141 newname = RDATA_SECTION_NAME;
10142 if (g_switch_value >= 8)
10146 newname = RDATA_SECTION_NAME;
10149 gas_assert (g_switch_value >= 4);
10153 new_seg = subseg_new (newname, (subsegT) 0);
10155 bfd_set_section_flags (stdoutput, new_seg,
10160 frag_align (*args == 'l' ? 2 : 3, 0, 0);
10161 if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0)
10162 record_alignment (new_seg, 4);
10164 record_alignment (new_seg, *args == 'l' ? 2 : 3);
10165 if (seg == now_seg)
10166 as_bad (_("Can't use floating point insn in this section"));
10168 /* Set the argument to the current address in the
10170 offset_expr.X_op = O_symbol;
10171 offset_expr.X_add_symbol = symbol_temp_new_now ();
10172 offset_expr.X_add_number = 0;
10174 /* Put the floating point number into the section. */
10175 p = frag_more ((int) length);
10176 memcpy (p, temp, length);
10178 /* Switch back to the original section. */
10179 subseg_set (seg, subseg);
10184 case 'i': /* 16-bit unsigned immediate. */
10185 case 'j': /* 16-bit signed immediate. */
10186 *imm_reloc = BFD_RELOC_LO16;
10187 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
10190 offsetT minval, maxval;
10192 more = (insn + 1 < &mips_opcodes[NUMOPCODES]
10193 && strcmp (insn->name, insn[1].name) == 0);
10195 /* If the expression was written as an unsigned number,
10196 only treat it as signed if there are no more
10200 && sizeof (imm_expr.X_add_number) <= 4
10201 && imm_expr.X_op == O_constant
10202 && imm_expr.X_add_number < 0
10203 && imm_expr.X_unsigned
10204 && HAVE_64BIT_GPRS)
10207 /* For compatibility with older assemblers, we accept
10208 0x8000-0xffff as signed 16-bit numbers when only
10209 signed numbers are allowed. */
10211 minval = 0, maxval = 0xffff;
10213 minval = -0x8000, maxval = 0x7fff;
10215 minval = -0x8000, maxval = 0xffff;
10217 if (imm_expr.X_op != O_constant
10218 || imm_expr.X_add_number < minval
10219 || imm_expr.X_add_number > maxval)
10223 if (imm_expr.X_op == O_constant
10224 || imm_expr.X_op == O_big)
10225 as_bad (_("Expression out of range"));
10231 case 'o': /* 16-bit offset. */
10232 offset_reloc[0] = BFD_RELOC_LO16;
10233 offset_reloc[1] = BFD_RELOC_UNUSED;
10234 offset_reloc[2] = BFD_RELOC_UNUSED;
10236 /* Check whether there is only a single bracketed expression
10237 left. If so, it must be the base register and the
10238 constant must be zero. */
10239 if (*s == '(' && strchr (s + 1, '(') == 0)
10241 offset_expr.X_op = O_constant;
10242 offset_expr.X_add_number = 0;
10246 /* If this value won't fit into a 16 bit offset, then go
10247 find a macro that will generate the 32 bit offset
10249 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
10250 && (offset_expr.X_op != O_constant
10251 || offset_expr.X_add_number >= 0x8000
10252 || offset_expr.X_add_number < -0x8000))
10258 case 'p': /* PC-relative offset. */
10259 *offset_reloc = BFD_RELOC_16_PCREL_S2;
10260 my_getExpression (&offset_expr, s);
10264 case 'u': /* Upper 16 bits. */
10265 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
10266 && imm_expr.X_op == O_constant
10267 && (imm_expr.X_add_number < 0
10268 || imm_expr.X_add_number >= 0x10000))
10269 as_bad (_("lui expression (%lu) not in range 0..65535"),
10270 (unsigned long) imm_expr.X_add_number);
10274 case 'a': /* 26-bit address. */
10275 my_getExpression (&offset_expr, s);
10277 *offset_reloc = BFD_RELOC_MIPS_JMP;
10280 case 'N': /* 3-bit branch condition code. */
10281 case 'M': /* 3-bit compare condition code. */
10283 if (ip->insn_mo->pinfo & (FP_D | FP_S))
10284 rtype |= RTYPE_FCC;
10285 if (!reg_lookup (&s, rtype, ®no))
10287 if ((strcmp (str + strlen (str) - 3, ".ps") == 0
10288 || strcmp (str + strlen (str) - 5, "any2f") == 0
10289 || strcmp (str + strlen (str) - 5, "any2t") == 0)
10290 && (regno & 1) != 0)
10291 as_warn (_("Condition code register should be even for %s, "
10294 if ((strcmp (str + strlen (str) - 5, "any4f") == 0
10295 || strcmp (str + strlen (str) - 5, "any4t") == 0)
10296 && (regno & 3) != 0)
10297 as_warn (_("Condition code register should be 0 or 4 for %s, "
10301 INSERT_OPERAND (BCC, *ip, regno);
10303 INSERT_OPERAND (CCC, *ip, regno);
10307 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
10318 while (ISDIGIT (*s));
10321 c = 8; /* Invalid sel value. */
10324 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
10325 ip->insn_opcode |= c;
10329 /* Must be at least one digit. */
10330 my_getExpression (&imm_expr, s);
10331 check_absolute_expr (ip, &imm_expr);
10333 if ((unsigned long) imm_expr.X_add_number
10334 > (unsigned long) OP_MASK_VECBYTE)
10336 as_bad (_("bad byte vector index (%ld)"),
10337 (long) imm_expr.X_add_number);
10338 imm_expr.X_add_number = 0;
10341 INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number);
10342 imm_expr.X_op = O_absent;
10347 my_getExpression (&imm_expr, s);
10348 check_absolute_expr (ip, &imm_expr);
10350 if ((unsigned long) imm_expr.X_add_number
10351 > (unsigned long) OP_MASK_VECALIGN)
10353 as_bad (_("bad byte vector index (%ld)"),
10354 (long) imm_expr.X_add_number);
10355 imm_expr.X_add_number = 0;
10358 INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number);
10359 imm_expr.X_op = O_absent;
10364 as_bad (_("Bad char = '%c'\n"), *args);
10369 /* Args don't match. */
10370 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
10371 !strcmp (insn->name, insn[1].name))
10375 insn_error = _("Illegal operands");
10379 *(--argsStart) = save_c;
10380 insn_error = _("Illegal operands");
10385 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
10387 /* This routine assembles an instruction into its binary format when
10388 assembling for the mips16. As a side effect, it sets one of the
10389 global variables imm_reloc or offset_reloc to the type of
10390 relocation to do if one of the operands is an address expression.
10391 It also sets mips16_small and mips16_ext if the user explicitly
10392 requested a small or extended instruction. */
10395 mips16_ip (char *str, struct mips_cl_insn *ip)
10399 struct mips_opcode *insn;
10401 unsigned int regno;
10402 unsigned int lastregno = 0;
10408 mips16_small = FALSE;
10409 mips16_ext = FALSE;
10411 for (s = str; ISLOWER (*s); ++s)
10423 if (s[1] == 't' && s[2] == ' ')
10426 mips16_small = TRUE;
10430 else if (s[1] == 'e' && s[2] == ' ')
10437 /* Fall through. */
10439 insn_error = _("unknown opcode");
10443 if (mips_opts.noautoextend && ! mips16_ext)
10444 mips16_small = TRUE;
10446 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
10448 insn_error = _("unrecognized opcode");
10457 gas_assert (strcmp (insn->name, str) == 0);
10459 ok = is_opcode_valid_16 (insn);
10462 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
10463 && strcmp (insn->name, insn[1].name) == 0)
10472 static char buf[100];
10474 _("opcode not supported on this processor: %s (%s)"),
10475 mips_cpu_info_from_arch (mips_opts.arch)->name,
10476 mips_cpu_info_from_isa (mips_opts.isa)->name);
10483 create_insn (ip, insn);
10484 imm_expr.X_op = O_absent;
10485 imm_reloc[0] = BFD_RELOC_UNUSED;
10486 imm_reloc[1] = BFD_RELOC_UNUSED;
10487 imm_reloc[2] = BFD_RELOC_UNUSED;
10488 imm2_expr.X_op = O_absent;
10489 offset_expr.X_op = O_absent;
10490 offset_reloc[0] = BFD_RELOC_UNUSED;
10491 offset_reloc[1] = BFD_RELOC_UNUSED;
10492 offset_reloc[2] = BFD_RELOC_UNUSED;
10493 for (args = insn->args; 1; ++args)
10500 /* In this switch statement we call break if we did not find
10501 a match, continue if we did find a match, or return if we
10510 /* Stuff the immediate value in now, if we can. */
10511 if (imm_expr.X_op == O_constant
10512 && *imm_reloc > BFD_RELOC_UNUSED
10513 && *imm_reloc != BFD_RELOC_MIPS16_GOT16
10514 && *imm_reloc != BFD_RELOC_MIPS16_CALL16
10515 && insn->pinfo != INSN_MACRO)
10519 switch (*offset_reloc)
10521 case BFD_RELOC_MIPS16_HI16_S:
10522 tmp = (imm_expr.X_add_number + 0x8000) >> 16;
10525 case BFD_RELOC_MIPS16_HI16:
10526 tmp = imm_expr.X_add_number >> 16;
10529 case BFD_RELOC_MIPS16_LO16:
10530 tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff)
10534 case BFD_RELOC_UNUSED:
10535 tmp = imm_expr.X_add_number;
10541 *offset_reloc = BFD_RELOC_UNUSED;
10543 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
10544 tmp, TRUE, mips16_small,
10545 mips16_ext, &ip->insn_opcode,
10546 &ip->use_extend, &ip->extend);
10547 imm_expr.X_op = O_absent;
10548 *imm_reloc = BFD_RELOC_UNUSED;
10562 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10565 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10581 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10583 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10587 /* Fall through. */
10598 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
10600 if (c == 'v' || c == 'w')
10603 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10605 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10616 if (c == 'v' || c == 'w')
10618 regno = mips16_to_32_reg_map[lastregno];
10632 regno = mips32_to_16_reg_map[regno];
10637 regno = ILLEGAL_REG;
10642 regno = ILLEGAL_REG;
10647 regno = ILLEGAL_REG;
10652 if (regno == AT && mips_opts.at)
10654 if (mips_opts.at == ATREG)
10655 as_warn (_("used $at without \".set noat\""));
10657 as_warn (_("used $%u with \".set at=$%u\""),
10658 regno, mips_opts.at);
10666 if (regno == ILLEGAL_REG)
10673 MIPS16_INSERT_OPERAND (RX, *ip, regno);
10677 MIPS16_INSERT_OPERAND (RY, *ip, regno);
10680 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
10683 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
10689 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
10692 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
10693 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
10703 if (strncmp (s, "$pc", 3) == 0)
10720 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
10723 if (imm_expr.X_op != O_constant)
10726 ip->use_extend = TRUE;
10731 /* We need to relax this instruction. */
10732 *offset_reloc = *imm_reloc;
10733 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10738 *imm_reloc = BFD_RELOC_UNUSED;
10739 /* Fall through. */
10746 my_getExpression (&imm_expr, s);
10747 if (imm_expr.X_op == O_register)
10749 /* What we thought was an expression turned out to
10752 if (s[0] == '(' && args[1] == '(')
10754 /* It looks like the expression was omitted
10755 before a register indirection, which means
10756 that the expression is implicitly zero. We
10757 still set up imm_expr, so that we handle
10758 explicit extensions correctly. */
10759 imm_expr.X_op = O_constant;
10760 imm_expr.X_add_number = 0;
10761 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10768 /* We need to relax this instruction. */
10769 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10778 /* We use offset_reloc rather than imm_reloc for the PC
10779 relative operands. This lets macros with both
10780 immediate and address operands work correctly. */
10781 my_getExpression (&offset_expr, s);
10783 if (offset_expr.X_op == O_register)
10786 /* We need to relax this instruction. */
10787 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
10791 case '6': /* break code */
10792 my_getExpression (&imm_expr, s);
10793 check_absolute_expr (ip, &imm_expr);
10794 if ((unsigned long) imm_expr.X_add_number > 63)
10795 as_warn (_("Invalid value for `%s' (%lu)"),
10797 (unsigned long) imm_expr.X_add_number);
10798 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
10799 imm_expr.X_op = O_absent;
10803 case 'a': /* 26 bit address */
10804 my_getExpression (&offset_expr, s);
10806 *offset_reloc = BFD_RELOC_MIPS16_JMP;
10807 ip->insn_opcode <<= 16;
10810 case 'l': /* register list for entry macro */
10811 case 'L': /* register list for exit macro */
10821 unsigned int freg, reg1, reg2;
10823 while (*s == ' ' || *s == ',')
10825 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
10827 else if (reg_lookup (&s, RTYPE_FPU, ®1))
10831 as_bad (_("can't parse register list"));
10841 if (!reg_lookup (&s, freg ? RTYPE_FPU
10842 : (RTYPE_GP | RTYPE_NUM), ®2))
10844 as_bad (_("invalid register list"));
10848 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
10850 mask &= ~ (7 << 3);
10853 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
10855 mask &= ~ (7 << 3);
10858 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
10859 mask |= (reg2 - 3) << 3;
10860 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
10861 mask |= (reg2 - 15) << 1;
10862 else if (reg1 == RA && reg2 == RA)
10866 as_bad (_("invalid register list"));
10870 /* The mask is filled in in the opcode table for the
10871 benefit of the disassembler. We remove it before
10872 applying the actual mask. */
10873 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
10874 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
10878 case 'm': /* Register list for save insn. */
10879 case 'M': /* Register list for restore insn. */
10882 int framesz = 0, seen_framesz = 0;
10883 int nargs = 0, statics = 0, sregs = 0;
10887 unsigned int reg1, reg2;
10889 SKIP_SPACE_TABS (s);
10892 SKIP_SPACE_TABS (s);
10894 my_getExpression (&imm_expr, s);
10895 if (imm_expr.X_op == O_constant)
10897 /* Handle the frame size. */
10900 as_bad (_("more than one frame size in list"));
10904 framesz = imm_expr.X_add_number;
10905 imm_expr.X_op = O_absent;
10910 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
10912 as_bad (_("can't parse register list"));
10924 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2)
10927 as_bad (_("can't parse register list"));
10932 while (reg1 <= reg2)
10934 if (reg1 >= 4 && reg1 <= 7)
10938 nargs |= 1 << (reg1 - 4);
10940 /* statics $a0-$a3 */
10941 statics |= 1 << (reg1 - 4);
10943 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
10946 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
10948 else if (reg1 == 31)
10950 /* Add $ra to insn. */
10955 as_bad (_("unexpected register in list"));
10963 /* Encode args/statics combination. */
10964 if (nargs & statics)
10965 as_bad (_("arg/static registers overlap"));
10966 else if (nargs == 0xf)
10967 /* All $a0-$a3 are args. */
10968 opcode |= MIPS16_ALL_ARGS << 16;
10969 else if (statics == 0xf)
10970 /* All $a0-$a3 are statics. */
10971 opcode |= MIPS16_ALL_STATICS << 16;
10974 int narg = 0, nstat = 0;
10976 /* Count arg registers. */
10977 while (nargs & 0x1)
10983 as_bad (_("invalid arg register list"));
10985 /* Count static registers. */
10986 while (statics & 0x8)
10988 statics = (statics << 1) & 0xf;
10992 as_bad (_("invalid static register list"));
10994 /* Encode args/statics. */
10995 opcode |= ((narg << 2) | nstat) << 16;
10998 /* Encode $s0/$s1. */
10999 if (sregs & (1 << 0)) /* $s0 */
11001 if (sregs & (1 << 1)) /* $s1 */
11007 /* Count regs $s2-$s8. */
11015 as_bad (_("invalid static register list"));
11016 /* Encode $s2-$s8. */
11017 opcode |= nsreg << 24;
11020 /* Encode frame size. */
11022 as_bad (_("missing frame size"));
11023 else if ((framesz & 7) != 0 || framesz < 0
11024 || framesz > 0xff * 8)
11025 as_bad (_("invalid frame size"));
11026 else if (framesz != 128 || (opcode >> 16) != 0)
11029 opcode |= (((framesz & 0xf0) << 16)
11030 | (framesz & 0x0f));
11033 /* Finally build the instruction. */
11034 if ((opcode >> 16) != 0 || framesz == 0)
11036 ip->use_extend = TRUE;
11037 ip->extend = opcode >> 16;
11039 ip->insn_opcode |= opcode & 0x7f;
11043 case 'e': /* extend code */
11044 my_getExpression (&imm_expr, s);
11045 check_absolute_expr (ip, &imm_expr);
11046 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
11048 as_warn (_("Invalid value for `%s' (%lu)"),
11050 (unsigned long) imm_expr.X_add_number);
11051 imm_expr.X_add_number &= 0x7ff;
11053 ip->insn_opcode |= imm_expr.X_add_number;
11054 imm_expr.X_op = O_absent;
11064 /* Args don't match. */
11065 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
11066 strcmp (insn->name, insn[1].name) == 0)
11073 insn_error = _("illegal operands");
11079 /* This structure holds information we know about a mips16 immediate
11082 struct mips16_immed_operand
11084 /* The type code used in the argument string in the opcode table. */
11086 /* The number of bits in the short form of the opcode. */
11088 /* The number of bits in the extended form of the opcode. */
11090 /* The amount by which the short form is shifted when it is used;
11091 for example, the sw instruction has a shift count of 2. */
11093 /* The amount by which the short form is shifted when it is stored
11094 into the instruction code. */
11096 /* Non-zero if the short form is unsigned. */
11098 /* Non-zero if the extended form is unsigned. */
11100 /* Non-zero if the value is PC relative. */
11104 /* The mips16 immediate operand types. */
11106 static const struct mips16_immed_operand mips16_immed_operands[] =
11108 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
11109 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
11110 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
11111 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
11112 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
11113 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
11114 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
11115 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
11116 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
11117 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
11118 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
11119 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
11120 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
11121 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
11122 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
11123 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
11124 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
11125 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
11126 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
11127 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
11128 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
11131 #define MIPS16_NUM_IMMED \
11132 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
11134 /* Handle a mips16 instruction with an immediate value. This or's the
11135 small immediate value into *INSN. It sets *USE_EXTEND to indicate
11136 whether an extended value is needed; if one is needed, it sets
11137 *EXTEND to the value. The argument type is TYPE. The value is VAL.
11138 If SMALL is true, an unextended opcode was explicitly requested.
11139 If EXT is true, an extended opcode was explicitly requested. If
11140 WARN is true, warn if EXT does not match reality. */
11143 mips16_immed (char *file, unsigned int line, int type, offsetT val,
11144 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
11145 unsigned long *insn, bfd_boolean *use_extend,
11146 unsigned short *extend)
11148 const struct mips16_immed_operand *op;
11149 int mintiny, maxtiny;
11150 bfd_boolean needext;
11152 op = mips16_immed_operands;
11153 while (op->type != type)
11156 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
11161 if (type == '<' || type == '>' || type == '[' || type == ']')
11164 maxtiny = 1 << op->nbits;
11169 maxtiny = (1 << op->nbits) - 1;
11174 mintiny = - (1 << (op->nbits - 1));
11175 maxtiny = (1 << (op->nbits - 1)) - 1;
11178 /* Branch offsets have an implicit 0 in the lowest bit. */
11179 if (type == 'p' || type == 'q')
11182 if ((val & ((1 << op->shift) - 1)) != 0
11183 || val < (mintiny << op->shift)
11184 || val > (maxtiny << op->shift))
11189 if (warn && ext && ! needext)
11190 as_warn_where (file, line,
11191 _("extended operand requested but not required"));
11192 if (small && needext)
11193 as_bad_where (file, line, _("invalid unextended operand value"));
11195 if (small || (! ext && ! needext))
11199 *use_extend = FALSE;
11200 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
11201 insnval <<= op->op_shift;
11206 long minext, maxext;
11212 maxext = (1 << op->extbits) - 1;
11216 minext = - (1 << (op->extbits - 1));
11217 maxext = (1 << (op->extbits - 1)) - 1;
11219 if (val < minext || val > maxext)
11220 as_bad_where (file, line,
11221 _("operand value out of range for instruction"));
11223 *use_extend = TRUE;
11224 if (op->extbits == 16)
11226 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
11229 else if (op->extbits == 15)
11231 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
11236 extval = ((val & 0x1f) << 6) | (val & 0x20);
11240 *extend = (unsigned short) extval;
11245 struct percent_op_match
11248 bfd_reloc_code_real_type reloc;
11251 static const struct percent_op_match mips_percent_op[] =
11253 {"%lo", BFD_RELOC_LO16},
11255 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
11256 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
11257 {"%call16", BFD_RELOC_MIPS_CALL16},
11258 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
11259 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
11260 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
11261 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
11262 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
11263 {"%got", BFD_RELOC_MIPS_GOT16},
11264 {"%gp_rel", BFD_RELOC_GPREL16},
11265 {"%half", BFD_RELOC_16},
11266 {"%highest", BFD_RELOC_MIPS_HIGHEST},
11267 {"%higher", BFD_RELOC_MIPS_HIGHER},
11268 {"%neg", BFD_RELOC_MIPS_SUB},
11269 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
11270 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
11271 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
11272 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
11273 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
11274 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
11275 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
11277 {"%hi", BFD_RELOC_HI16_S}
11280 static const struct percent_op_match mips16_percent_op[] =
11282 {"%lo", BFD_RELOC_MIPS16_LO16},
11283 {"%gprel", BFD_RELOC_MIPS16_GPREL},
11284 {"%got", BFD_RELOC_MIPS16_GOT16},
11285 {"%call16", BFD_RELOC_MIPS16_CALL16},
11286 {"%hi", BFD_RELOC_MIPS16_HI16_S}
11290 /* Return true if *STR points to a relocation operator. When returning true,
11291 move *STR over the operator and store its relocation code in *RELOC.
11292 Leave both *STR and *RELOC alone when returning false. */
11295 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
11297 const struct percent_op_match *percent_op;
11300 if (mips_opts.mips16)
11302 percent_op = mips16_percent_op;
11303 limit = ARRAY_SIZE (mips16_percent_op);
11307 percent_op = mips_percent_op;
11308 limit = ARRAY_SIZE (mips_percent_op);
11311 for (i = 0; i < limit; i++)
11312 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
11314 int len = strlen (percent_op[i].str);
11316 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
11319 *str += strlen (percent_op[i].str);
11320 *reloc = percent_op[i].reloc;
11322 /* Check whether the output BFD supports this relocation.
11323 If not, issue an error and fall back on something safe. */
11324 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
11326 as_bad (_("relocation %s isn't supported by the current ABI"),
11327 percent_op[i].str);
11328 *reloc = BFD_RELOC_UNUSED;
11336 /* Parse string STR as a 16-bit relocatable operand. Store the
11337 expression in *EP and the relocations in the array starting
11338 at RELOC. Return the number of relocation operators used.
11340 On exit, EXPR_END points to the first character after the expression. */
11343 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
11346 bfd_reloc_code_real_type reversed_reloc[3];
11347 size_t reloc_index, i;
11348 int crux_depth, str_depth;
11351 /* Search for the start of the main expression, recoding relocations
11352 in REVERSED_RELOC. End the loop with CRUX pointing to the start
11353 of the main expression and with CRUX_DEPTH containing the number
11354 of open brackets at that point. */
11361 crux_depth = str_depth;
11363 /* Skip over whitespace and brackets, keeping count of the number
11365 while (*str == ' ' || *str == '\t' || *str == '(')
11370 && reloc_index < (HAVE_NEWABI ? 3 : 1)
11371 && parse_relocation (&str, &reversed_reloc[reloc_index]));
11373 my_getExpression (ep, crux);
11376 /* Match every open bracket. */
11377 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
11381 if (crux_depth > 0)
11382 as_bad (_("unclosed '('"));
11386 if (reloc_index != 0)
11388 prev_reloc_op_frag = frag_now;
11389 for (i = 0; i < reloc_index; i++)
11390 reloc[i] = reversed_reloc[reloc_index - 1 - i];
11393 return reloc_index;
11397 my_getExpression (expressionS *ep, char *str)
11401 save_in = input_line_pointer;
11402 input_line_pointer = str;
11404 expr_end = input_line_pointer;
11405 input_line_pointer = save_in;
11409 md_atof (int type, char *litP, int *sizeP)
11411 return ieee_md_atof (type, litP, sizeP, target_big_endian);
11415 md_number_to_chars (char *buf, valueT val, int n)
11417 if (target_big_endian)
11418 number_to_chars_bigendian (buf, val, n);
11420 number_to_chars_littleendian (buf, val, n);
11424 static int support_64bit_objects(void)
11426 const char **list, **l;
11429 list = bfd_target_list ();
11430 for (l = list; *l != NULL; l++)
11431 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
11432 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
11434 yes = (*l != NULL);
11438 #endif /* OBJ_ELF */
11440 const char *md_shortopts = "O::g::G:";
11444 OPTION_MARCH = OPTION_MD_BASE,
11466 OPTION_NO_SMARTMIPS,
11469 OPTION_COMPAT_ARCH_BASE,
11478 OPTION_M7000_HILO_FIX,
11479 OPTION_MNO_7000_HILO_FIX,
11482 OPTION_FIX_LOONGSON2F_JUMP,
11483 OPTION_NO_FIX_LOONGSON2F_JUMP,
11484 OPTION_FIX_LOONGSON2F_NOP,
11485 OPTION_NO_FIX_LOONGSON2F_NOP,
11487 OPTION_NO_FIX_VR4120,
11489 OPTION_NO_FIX_VR4130,
11490 OPTION_FIX_CN63XXP1,
11491 OPTION_NO_FIX_CN63XXP1,
11498 OPTION_CONSTRUCT_FLOATS,
11499 OPTION_NO_CONSTRUCT_FLOATS,
11502 OPTION_RELAX_BRANCH,
11503 OPTION_NO_RELAX_BRANCH,
11510 OPTION_SINGLE_FLOAT,
11511 OPTION_DOUBLE_FLOAT,
11514 OPTION_CALL_SHARED,
11515 OPTION_CALL_NONPIC,
11525 OPTION_MVXWORKS_PIC,
11526 #endif /* OBJ_ELF */
11530 struct option md_longopts[] =
11532 /* Options which specify architecture. */
11533 {"march", required_argument, NULL, OPTION_MARCH},
11534 {"mtune", required_argument, NULL, OPTION_MTUNE},
11535 {"mips0", no_argument, NULL, OPTION_MIPS1},
11536 {"mips1", no_argument, NULL, OPTION_MIPS1},
11537 {"mips2", no_argument, NULL, OPTION_MIPS2},
11538 {"mips3", no_argument, NULL, OPTION_MIPS3},
11539 {"mips4", no_argument, NULL, OPTION_MIPS4},
11540 {"mips5", no_argument, NULL, OPTION_MIPS5},
11541 {"mips32", no_argument, NULL, OPTION_MIPS32},
11542 {"mips64", no_argument, NULL, OPTION_MIPS64},
11543 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
11544 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
11546 /* Options which specify Application Specific Extensions (ASEs). */
11547 {"mips16", no_argument, NULL, OPTION_MIPS16},
11548 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
11549 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
11550 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
11551 {"mdmx", no_argument, NULL, OPTION_MDMX},
11552 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
11553 {"mdsp", no_argument, NULL, OPTION_DSP},
11554 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
11555 {"mmt", no_argument, NULL, OPTION_MT},
11556 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
11557 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
11558 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
11559 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
11560 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
11562 /* Old-style architecture options. Don't add more of these. */
11563 {"m4650", no_argument, NULL, OPTION_M4650},
11564 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
11565 {"m4010", no_argument, NULL, OPTION_M4010},
11566 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
11567 {"m4100", no_argument, NULL, OPTION_M4100},
11568 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
11569 {"m3900", no_argument, NULL, OPTION_M3900},
11570 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
11572 /* Options which enable bug fixes. */
11573 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
11574 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
11575 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
11576 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
11577 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
11578 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
11579 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
11580 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
11581 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
11582 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
11583 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
11584 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
11585 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
11586 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
11587 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
11589 /* Miscellaneous options. */
11590 {"trap", no_argument, NULL, OPTION_TRAP},
11591 {"no-break", no_argument, NULL, OPTION_TRAP},
11592 {"break", no_argument, NULL, OPTION_BREAK},
11593 {"no-trap", no_argument, NULL, OPTION_BREAK},
11594 {"EB", no_argument, NULL, OPTION_EB},
11595 {"EL", no_argument, NULL, OPTION_EL},
11596 {"mfp32", no_argument, NULL, OPTION_FP32},
11597 {"mgp32", no_argument, NULL, OPTION_GP32},
11598 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
11599 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
11600 {"mfp64", no_argument, NULL, OPTION_FP64},
11601 {"mgp64", no_argument, NULL, OPTION_GP64},
11602 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
11603 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
11604 {"mshared", no_argument, NULL, OPTION_MSHARED},
11605 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
11606 {"msym32", no_argument, NULL, OPTION_MSYM32},
11607 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
11608 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
11609 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
11610 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
11611 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
11613 /* Strictly speaking this next option is ELF specific,
11614 but we allow it for other ports as well in order to
11615 make testing easier. */
11616 {"32", no_argument, NULL, OPTION_32},
11618 /* ELF-specific options. */
11620 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
11621 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
11622 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
11623 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
11624 {"xgot", no_argument, NULL, OPTION_XGOT},
11625 {"mabi", required_argument, NULL, OPTION_MABI},
11626 {"n32", no_argument, NULL, OPTION_N32},
11627 {"64", no_argument, NULL, OPTION_64},
11628 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
11629 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
11630 {"mpdr", no_argument, NULL, OPTION_PDR},
11631 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
11632 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
11633 #endif /* OBJ_ELF */
11635 {NULL, no_argument, NULL, 0}
11637 size_t md_longopts_size = sizeof (md_longopts);
11639 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
11640 NEW_VALUE. Warn if another value was already specified. Note:
11641 we have to defer parsing the -march and -mtune arguments in order
11642 to handle 'from-abi' correctly, since the ABI might be specified
11643 in a later argument. */
11646 mips_set_option_string (const char **string_ptr, const char *new_value)
11648 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
11649 as_warn (_("A different %s was already specified, is now %s"),
11650 string_ptr == &mips_arch_string ? "-march" : "-mtune",
11653 *string_ptr = new_value;
11657 md_parse_option (int c, char *arg)
11661 case OPTION_CONSTRUCT_FLOATS:
11662 mips_disable_float_construction = 0;
11665 case OPTION_NO_CONSTRUCT_FLOATS:
11666 mips_disable_float_construction = 1;
11678 target_big_endian = 1;
11682 target_big_endian = 0;
11688 else if (arg[0] == '0')
11690 else if (arg[0] == '1')
11700 mips_debug = atoi (arg);
11704 file_mips_isa = ISA_MIPS1;
11708 file_mips_isa = ISA_MIPS2;
11712 file_mips_isa = ISA_MIPS3;
11716 file_mips_isa = ISA_MIPS4;
11720 file_mips_isa = ISA_MIPS5;
11723 case OPTION_MIPS32:
11724 file_mips_isa = ISA_MIPS32;
11727 case OPTION_MIPS32R2:
11728 file_mips_isa = ISA_MIPS32R2;
11731 case OPTION_MIPS64R2:
11732 file_mips_isa = ISA_MIPS64R2;
11735 case OPTION_MIPS64:
11736 file_mips_isa = ISA_MIPS64;
11740 mips_set_option_string (&mips_tune_string, arg);
11744 mips_set_option_string (&mips_arch_string, arg);
11748 mips_set_option_string (&mips_arch_string, "4650");
11749 mips_set_option_string (&mips_tune_string, "4650");
11752 case OPTION_NO_M4650:
11756 mips_set_option_string (&mips_arch_string, "4010");
11757 mips_set_option_string (&mips_tune_string, "4010");
11760 case OPTION_NO_M4010:
11764 mips_set_option_string (&mips_arch_string, "4100");
11765 mips_set_option_string (&mips_tune_string, "4100");
11768 case OPTION_NO_M4100:
11772 mips_set_option_string (&mips_arch_string, "3900");
11773 mips_set_option_string (&mips_tune_string, "3900");
11776 case OPTION_NO_M3900:
11780 mips_opts.ase_mdmx = 1;
11783 case OPTION_NO_MDMX:
11784 mips_opts.ase_mdmx = 0;
11788 mips_opts.ase_dsp = 1;
11789 mips_opts.ase_dspr2 = 0;
11792 case OPTION_NO_DSP:
11793 mips_opts.ase_dsp = 0;
11794 mips_opts.ase_dspr2 = 0;
11798 mips_opts.ase_dspr2 = 1;
11799 mips_opts.ase_dsp = 1;
11802 case OPTION_NO_DSPR2:
11803 mips_opts.ase_dspr2 = 0;
11804 mips_opts.ase_dsp = 0;
11808 mips_opts.ase_mt = 1;
11812 mips_opts.ase_mt = 0;
11815 case OPTION_MIPS16:
11816 mips_opts.mips16 = 1;
11817 mips_no_prev_insn ();
11820 case OPTION_NO_MIPS16:
11821 mips_opts.mips16 = 0;
11822 mips_no_prev_insn ();
11825 case OPTION_MIPS3D:
11826 mips_opts.ase_mips3d = 1;
11829 case OPTION_NO_MIPS3D:
11830 mips_opts.ase_mips3d = 0;
11833 case OPTION_SMARTMIPS:
11834 mips_opts.ase_smartmips = 1;
11837 case OPTION_NO_SMARTMIPS:
11838 mips_opts.ase_smartmips = 0;
11841 case OPTION_FIX_24K:
11845 case OPTION_NO_FIX_24K:
11849 case OPTION_FIX_LOONGSON2F_JUMP:
11850 mips_fix_loongson2f_jump = TRUE;
11853 case OPTION_NO_FIX_LOONGSON2F_JUMP:
11854 mips_fix_loongson2f_jump = FALSE;
11857 case OPTION_FIX_LOONGSON2F_NOP:
11858 mips_fix_loongson2f_nop = TRUE;
11861 case OPTION_NO_FIX_LOONGSON2F_NOP:
11862 mips_fix_loongson2f_nop = FALSE;
11865 case OPTION_FIX_VR4120:
11866 mips_fix_vr4120 = 1;
11869 case OPTION_NO_FIX_VR4120:
11870 mips_fix_vr4120 = 0;
11873 case OPTION_FIX_VR4130:
11874 mips_fix_vr4130 = 1;
11877 case OPTION_NO_FIX_VR4130:
11878 mips_fix_vr4130 = 0;
11881 case OPTION_FIX_CN63XXP1:
11882 mips_fix_cn63xxp1 = TRUE;
11885 case OPTION_NO_FIX_CN63XXP1:
11886 mips_fix_cn63xxp1 = FALSE;
11889 case OPTION_RELAX_BRANCH:
11890 mips_relax_branch = 1;
11893 case OPTION_NO_RELAX_BRANCH:
11894 mips_relax_branch = 0;
11897 case OPTION_MSHARED:
11898 mips_in_shared = TRUE;
11901 case OPTION_MNO_SHARED:
11902 mips_in_shared = FALSE;
11905 case OPTION_MSYM32:
11906 mips_opts.sym32 = TRUE;
11909 case OPTION_MNO_SYM32:
11910 mips_opts.sym32 = FALSE;
11914 /* When generating ELF code, we permit -KPIC and -call_shared to
11915 select SVR4_PIC, and -non_shared to select no PIC. This is
11916 intended to be compatible with Irix 5. */
11917 case OPTION_CALL_SHARED:
11920 as_bad (_("-call_shared is supported only for ELF format"));
11923 mips_pic = SVR4_PIC;
11924 mips_abicalls = TRUE;
11927 case OPTION_CALL_NONPIC:
11930 as_bad (_("-call_nonpic is supported only for ELF format"));
11934 mips_abicalls = TRUE;
11937 case OPTION_NON_SHARED:
11940 as_bad (_("-non_shared is supported only for ELF format"));
11944 mips_abicalls = FALSE;
11947 /* The -xgot option tells the assembler to use 32 bit offsets
11948 when accessing the got in SVR4_PIC mode. It is for Irix
11953 #endif /* OBJ_ELF */
11956 g_switch_value = atoi (arg);
11960 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
11964 mips_abi = O32_ABI;
11965 /* We silently ignore -32 for non-ELF targets. This greatly
11966 simplifies the construction of the MIPS GAS test cases. */
11973 as_bad (_("-n32 is supported for ELF format only"));
11976 mips_abi = N32_ABI;
11982 as_bad (_("-64 is supported for ELF format only"));
11985 mips_abi = N64_ABI;
11986 if (!support_64bit_objects())
11987 as_fatal (_("No compiled in support for 64 bit object file format"));
11989 #endif /* OBJ_ELF */
11992 file_mips_gp32 = 1;
11996 file_mips_gp32 = 0;
12000 file_mips_fp32 = 1;
12004 file_mips_fp32 = 0;
12007 case OPTION_SINGLE_FLOAT:
12008 file_mips_single_float = 1;
12011 case OPTION_DOUBLE_FLOAT:
12012 file_mips_single_float = 0;
12015 case OPTION_SOFT_FLOAT:
12016 file_mips_soft_float = 1;
12019 case OPTION_HARD_FLOAT:
12020 file_mips_soft_float = 0;
12027 as_bad (_("-mabi is supported for ELF format only"));
12030 if (strcmp (arg, "32") == 0)
12031 mips_abi = O32_ABI;
12032 else if (strcmp (arg, "o64") == 0)
12033 mips_abi = O64_ABI;
12034 else if (strcmp (arg, "n32") == 0)
12035 mips_abi = N32_ABI;
12036 else if (strcmp (arg, "64") == 0)
12038 mips_abi = N64_ABI;
12039 if (! support_64bit_objects())
12040 as_fatal (_("No compiled in support for 64 bit object file "
12043 else if (strcmp (arg, "eabi") == 0)
12044 mips_abi = EABI_ABI;
12047 as_fatal (_("invalid abi -mabi=%s"), arg);
12051 #endif /* OBJ_ELF */
12053 case OPTION_M7000_HILO_FIX:
12054 mips_7000_hilo_fix = TRUE;
12057 case OPTION_MNO_7000_HILO_FIX:
12058 mips_7000_hilo_fix = FALSE;
12062 case OPTION_MDEBUG:
12063 mips_flag_mdebug = TRUE;
12066 case OPTION_NO_MDEBUG:
12067 mips_flag_mdebug = FALSE;
12071 mips_flag_pdr = TRUE;
12074 case OPTION_NO_PDR:
12075 mips_flag_pdr = FALSE;
12078 case OPTION_MVXWORKS_PIC:
12079 mips_pic = VXWORKS_PIC;
12081 #endif /* OBJ_ELF */
12087 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
12092 /* Set up globals to generate code for the ISA or processor
12093 described by INFO. */
12096 mips_set_architecture (const struct mips_cpu_info *info)
12100 file_mips_arch = info->cpu;
12101 mips_opts.arch = info->cpu;
12102 mips_opts.isa = info->isa;
12107 /* Likewise for tuning. */
12110 mips_set_tune (const struct mips_cpu_info *info)
12113 mips_tune = info->cpu;
12118 mips_after_parse_args (void)
12120 const struct mips_cpu_info *arch_info = 0;
12121 const struct mips_cpu_info *tune_info = 0;
12123 /* GP relative stuff not working for PE */
12124 if (strncmp (TARGET_OS, "pe", 2) == 0)
12126 if (g_switch_seen && g_switch_value != 0)
12127 as_bad (_("-G not supported in this configuration."));
12128 g_switch_value = 0;
12131 if (mips_abi == NO_ABI)
12132 mips_abi = MIPS_DEFAULT_ABI;
12134 /* The following code determines the architecture and register size.
12135 Similar code was added to GCC 3.3 (see override_options() in
12136 config/mips/mips.c). The GAS and GCC code should be kept in sync
12137 as much as possible. */
12139 if (mips_arch_string != 0)
12140 arch_info = mips_parse_cpu ("-march", mips_arch_string);
12142 if (file_mips_isa != ISA_UNKNOWN)
12144 /* Handle -mipsN. At this point, file_mips_isa contains the
12145 ISA level specified by -mipsN, while arch_info->isa contains
12146 the -march selection (if any). */
12147 if (arch_info != 0)
12149 /* -march takes precedence over -mipsN, since it is more descriptive.
12150 There's no harm in specifying both as long as the ISA levels
12152 if (file_mips_isa != arch_info->isa)
12153 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
12154 mips_cpu_info_from_isa (file_mips_isa)->name,
12155 mips_cpu_info_from_isa (arch_info->isa)->name);
12158 arch_info = mips_cpu_info_from_isa (file_mips_isa);
12161 if (arch_info == 0)
12162 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
12164 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
12165 as_bad (_("-march=%s is not compatible with the selected ABI"),
12168 mips_set_architecture (arch_info);
12170 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
12171 if (mips_tune_string != 0)
12172 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
12174 if (tune_info == 0)
12175 mips_set_tune (arch_info);
12177 mips_set_tune (tune_info);
12179 if (file_mips_gp32 >= 0)
12181 /* The user specified the size of the integer registers. Make sure
12182 it agrees with the ABI and ISA. */
12183 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
12184 as_bad (_("-mgp64 used with a 32-bit processor"));
12185 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
12186 as_bad (_("-mgp32 used with a 64-bit ABI"));
12187 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
12188 as_bad (_("-mgp64 used with a 32-bit ABI"));
12192 /* Infer the integer register size from the ABI and processor.
12193 Restrict ourselves to 32-bit registers if that's all the
12194 processor has, or if the ABI cannot handle 64-bit registers. */
12195 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
12196 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
12199 switch (file_mips_fp32)
12203 /* No user specified float register size.
12204 ??? GAS treats single-float processors as though they had 64-bit
12205 float registers (although it complains when double-precision
12206 instructions are used). As things stand, saying they have 32-bit
12207 registers would lead to spurious "register must be even" messages.
12208 So here we assume float registers are never smaller than the
12210 if (file_mips_gp32 == 0)
12211 /* 64-bit integer registers implies 64-bit float registers. */
12212 file_mips_fp32 = 0;
12213 else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
12214 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
12215 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
12216 file_mips_fp32 = 0;
12218 /* 32-bit float registers. */
12219 file_mips_fp32 = 1;
12222 /* The user specified the size of the float registers. Check if it
12223 agrees with the ABI and ISA. */
12225 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
12226 as_bad (_("-mfp64 used with a 32-bit fpu"));
12227 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
12228 && !ISA_HAS_MXHC1 (mips_opts.isa))
12229 as_warn (_("-mfp64 used with a 32-bit ABI"));
12232 if (ABI_NEEDS_64BIT_REGS (mips_abi))
12233 as_warn (_("-mfp32 used with a 64-bit ABI"));
12237 /* End of GCC-shared inference code. */
12239 /* This flag is set when we have a 64-bit capable CPU but use only
12240 32-bit wide registers. Note that EABI does not use it. */
12241 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
12242 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
12243 || mips_abi == O32_ABI))
12244 mips_32bitmode = 1;
12246 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
12247 as_bad (_("trap exception not supported at ISA 1"));
12249 /* If the selected architecture includes support for ASEs, enable
12250 generation of code for them. */
12251 if (mips_opts.mips16 == -1)
12252 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
12253 if (mips_opts.ase_mips3d == -1)
12254 mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
12255 && file_mips_fp32 == 0) ? 1 : 0;
12256 if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
12257 as_bad (_("-mfp32 used with -mips3d"));
12259 if (mips_opts.ase_mdmx == -1)
12260 mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
12261 && file_mips_fp32 == 0) ? 1 : 0;
12262 if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
12263 as_bad (_("-mfp32 used with -mdmx"));
12265 if (mips_opts.ase_smartmips == -1)
12266 mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
12267 if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
12268 as_warn (_("%s ISA does not support SmartMIPS"),
12269 mips_cpu_info_from_isa (mips_opts.isa)->name);
12271 if (mips_opts.ase_dsp == -1)
12272 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
12273 if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
12274 as_warn (_("%s ISA does not support DSP ASE"),
12275 mips_cpu_info_from_isa (mips_opts.isa)->name);
12277 if (mips_opts.ase_dspr2 == -1)
12279 mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
12280 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
12282 if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
12283 as_warn (_("%s ISA does not support DSP R2 ASE"),
12284 mips_cpu_info_from_isa (mips_opts.isa)->name);
12286 if (mips_opts.ase_mt == -1)
12287 mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
12288 if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
12289 as_warn (_("%s ISA does not support MT ASE"),
12290 mips_cpu_info_from_isa (mips_opts.isa)->name);
12292 file_mips_isa = mips_opts.isa;
12293 file_ase_mips3d = mips_opts.ase_mips3d;
12294 file_ase_mdmx = mips_opts.ase_mdmx;
12295 file_ase_smartmips = mips_opts.ase_smartmips;
12296 file_ase_dsp = mips_opts.ase_dsp;
12297 file_ase_dspr2 = mips_opts.ase_dspr2;
12298 file_ase_mt = mips_opts.ase_mt;
12299 mips_opts.gp32 = file_mips_gp32;
12300 mips_opts.fp32 = file_mips_fp32;
12301 mips_opts.soft_float = file_mips_soft_float;
12302 mips_opts.single_float = file_mips_single_float;
12304 if (mips_flag_mdebug < 0)
12306 #ifdef OBJ_MAYBE_ECOFF
12307 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
12308 mips_flag_mdebug = 1;
12310 #endif /* OBJ_MAYBE_ECOFF */
12311 mips_flag_mdebug = 0;
12316 mips_init_after_args (void)
12318 /* initialize opcodes */
12319 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
12320 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
12324 md_pcrel_from (fixS *fixP)
12326 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
12327 switch (fixP->fx_r_type)
12329 case BFD_RELOC_16_PCREL_S2:
12330 case BFD_RELOC_MIPS_JMP:
12331 /* Return the address of the delay slot. */
12334 /* We have no relocation type for PC relative MIPS16 instructions. */
12335 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
12336 as_bad_where (fixP->fx_file, fixP->fx_line,
12337 _("PC relative MIPS16 instruction references a different section"));
12342 /* This is called before the symbol table is processed. In order to
12343 work with gcc when using mips-tfile, we must keep all local labels.
12344 However, in other cases, we want to discard them. If we were
12345 called with -g, but we didn't see any debugging information, it may
12346 mean that gcc is smuggling debugging information through to
12347 mips-tfile, in which case we must generate all local labels. */
12350 mips_frob_file_before_adjust (void)
12352 #ifndef NO_ECOFF_DEBUGGING
12353 if (ECOFF_DEBUGGING
12355 && ! ecoff_debugging_seen)
12356 flag_keep_locals = 1;
12360 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
12361 the corresponding LO16 reloc. This is called before md_apply_fix and
12362 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
12363 relocation operators.
12365 For our purposes, a %lo() expression matches a %got() or %hi()
12368 (a) it refers to the same symbol; and
12369 (b) the offset applied in the %lo() expression is no lower than
12370 the offset applied in the %got() or %hi().
12372 (b) allows us to cope with code like:
12375 lh $4,%lo(foo+2)($4)
12377 ...which is legal on RELA targets, and has a well-defined behaviour
12378 if the user knows that adding 2 to "foo" will not induce a carry to
12381 When several %lo()s match a particular %got() or %hi(), we use the
12382 following rules to distinguish them:
12384 (1) %lo()s with smaller offsets are a better match than %lo()s with
12387 (2) %lo()s with no matching %got() or %hi() are better than those
12388 that already have a matching %got() or %hi().
12390 (3) later %lo()s are better than earlier %lo()s.
12392 These rules are applied in order.
12394 (1) means, among other things, that %lo()s with identical offsets are
12395 chosen if they exist.
12397 (2) means that we won't associate several high-part relocations with
12398 the same low-part relocation unless there's no alternative. Having
12399 several high parts for the same low part is a GNU extension; this rule
12400 allows careful users to avoid it.
12402 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
12403 with the last high-part relocation being at the front of the list.
12404 It therefore makes sense to choose the last matching low-part
12405 relocation, all other things being equal. It's also easier
12406 to code that way. */
12409 mips_frob_file (void)
12411 struct mips_hi_fixup *l;
12412 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
12414 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
12416 segment_info_type *seginfo;
12417 bfd_boolean matched_lo_p;
12418 fixS **hi_pos, **lo_pos, **pos;
12420 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
12422 /* If a GOT16 relocation turns out to be against a global symbol,
12423 there isn't supposed to be a matching LO. */
12424 if (got16_reloc_p (l->fixp->fx_r_type)
12425 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
12428 /* Check quickly whether the next fixup happens to be a matching %lo. */
12429 if (fixup_has_matching_lo_p (l->fixp))
12432 seginfo = seg_info (l->seg);
12434 /* Set HI_POS to the position of this relocation in the chain.
12435 Set LO_POS to the position of the chosen low-part relocation.
12436 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
12437 relocation that matches an immediately-preceding high-part
12441 matched_lo_p = FALSE;
12442 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
12444 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
12446 if (*pos == l->fixp)
12449 if ((*pos)->fx_r_type == looking_for_rtype
12450 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
12451 && (*pos)->fx_offset >= l->fixp->fx_offset
12453 || (*pos)->fx_offset < (*lo_pos)->fx_offset
12455 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
12458 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
12459 && fixup_has_matching_lo_p (*pos));
12462 /* If we found a match, remove the high-part relocation from its
12463 current position and insert it before the low-part relocation.
12464 Make the offsets match so that fixup_has_matching_lo_p()
12467 We don't warn about unmatched high-part relocations since some
12468 versions of gcc have been known to emit dead "lui ...%hi(...)"
12470 if (lo_pos != NULL)
12472 l->fixp->fx_offset = (*lo_pos)->fx_offset;
12473 if (l->fixp->fx_next != *lo_pos)
12475 *hi_pos = l->fixp->fx_next;
12476 l->fixp->fx_next = *lo_pos;
12483 /* We may have combined relocations without symbols in the N32/N64 ABI.
12484 We have to prevent gas from dropping them. */
12487 mips_force_relocation (fixS *fixp)
12489 if (generic_force_reloc (fixp))
12493 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
12494 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
12495 || hi16_reloc_p (fixp->fx_r_type)
12496 || lo16_reloc_p (fixp->fx_r_type)))
12502 /* Apply a fixup to the object file. */
12505 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
12509 reloc_howto_type *howto;
12511 /* We ignore generic BFD relocations we don't know about. */
12512 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
12516 gas_assert (fixP->fx_size == 4
12517 || fixP->fx_r_type == BFD_RELOC_16
12518 || fixP->fx_r_type == BFD_RELOC_64
12519 || fixP->fx_r_type == BFD_RELOC_CTOR
12520 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
12521 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12522 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
12523 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
12525 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
12527 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2);
12529 /* Don't treat parts of a composite relocation as done. There are two
12532 (1) The second and third parts will be against 0 (RSS_UNDEF) but
12533 should nevertheless be emitted if the first part is.
12535 (2) In normal usage, composite relocations are never assembly-time
12536 constants. The easiest way of dealing with the pathological
12537 exceptions is to generate a relocation against STN_UNDEF and
12538 leave everything up to the linker. */
12539 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
12542 switch (fixP->fx_r_type)
12544 case BFD_RELOC_MIPS_TLS_GD:
12545 case BFD_RELOC_MIPS_TLS_LDM:
12546 case BFD_RELOC_MIPS_TLS_DTPREL32:
12547 case BFD_RELOC_MIPS_TLS_DTPREL64:
12548 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
12549 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
12550 case BFD_RELOC_MIPS_TLS_GOTTPREL:
12551 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
12552 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
12553 S_SET_THREAD_LOCAL (fixP->fx_addsy);
12556 case BFD_RELOC_MIPS_JMP:
12557 case BFD_RELOC_MIPS_SHIFT5:
12558 case BFD_RELOC_MIPS_SHIFT6:
12559 case BFD_RELOC_MIPS_GOT_DISP:
12560 case BFD_RELOC_MIPS_GOT_PAGE:
12561 case BFD_RELOC_MIPS_GOT_OFST:
12562 case BFD_RELOC_MIPS_SUB:
12563 case BFD_RELOC_MIPS_INSERT_A:
12564 case BFD_RELOC_MIPS_INSERT_B:
12565 case BFD_RELOC_MIPS_DELETE:
12566 case BFD_RELOC_MIPS_HIGHEST:
12567 case BFD_RELOC_MIPS_HIGHER:
12568 case BFD_RELOC_MIPS_SCN_DISP:
12569 case BFD_RELOC_MIPS_REL16:
12570 case BFD_RELOC_MIPS_RELGOT:
12571 case BFD_RELOC_MIPS_JALR:
12572 case BFD_RELOC_HI16:
12573 case BFD_RELOC_HI16_S:
12574 case BFD_RELOC_GPREL16:
12575 case BFD_RELOC_MIPS_LITERAL:
12576 case BFD_RELOC_MIPS_CALL16:
12577 case BFD_RELOC_MIPS_GOT16:
12578 case BFD_RELOC_GPREL32:
12579 case BFD_RELOC_MIPS_GOT_HI16:
12580 case BFD_RELOC_MIPS_GOT_LO16:
12581 case BFD_RELOC_MIPS_CALL_HI16:
12582 case BFD_RELOC_MIPS_CALL_LO16:
12583 case BFD_RELOC_MIPS16_GPREL:
12584 case BFD_RELOC_MIPS16_GOT16:
12585 case BFD_RELOC_MIPS16_CALL16:
12586 case BFD_RELOC_MIPS16_HI16:
12587 case BFD_RELOC_MIPS16_HI16_S:
12588 case BFD_RELOC_MIPS16_JMP:
12589 /* Nothing needed to do. The value comes from the reloc entry. */
12593 /* This is handled like BFD_RELOC_32, but we output a sign
12594 extended value if we are only 32 bits. */
12597 if (8 <= sizeof (valueT))
12598 md_number_to_chars ((char *) buf, *valP, 8);
12603 if ((*valP & 0x80000000) != 0)
12607 md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)),
12609 md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)),
12615 case BFD_RELOC_RVA:
12618 /* If we are deleting this reloc entry, we must fill in the
12619 value now. This can happen if we have a .word which is not
12620 resolved when it appears but is later defined. */
12622 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
12625 case BFD_RELOC_LO16:
12626 case BFD_RELOC_MIPS16_LO16:
12627 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
12628 may be safe to remove, but if so it's not obvious. */
12629 /* When handling an embedded PIC switch statement, we can wind
12630 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
12633 if (*valP + 0x8000 > 0xffff)
12634 as_bad_where (fixP->fx_file, fixP->fx_line,
12635 _("relocation overflow"));
12636 if (target_big_endian)
12638 md_number_to_chars ((char *) buf, *valP, 2);
12642 case BFD_RELOC_16_PCREL_S2:
12643 if ((*valP & 0x3) != 0)
12644 as_bad_where (fixP->fx_file, fixP->fx_line,
12645 _("Branch to misaligned address (%lx)"), (long) *valP);
12647 /* We need to save the bits in the instruction since fixup_segment()
12648 might be deleting the relocation entry (i.e., a branch within
12649 the current segment). */
12650 if (! fixP->fx_done)
12653 /* Update old instruction data. */
12654 if (target_big_endian)
12655 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
12657 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
12659 if (*valP + 0x20000 <= 0x3ffff)
12661 insn |= (*valP >> 2) & 0xffff;
12662 md_number_to_chars ((char *) buf, insn, 4);
12664 else if (mips_pic == NO_PIC
12666 && fixP->fx_frag->fr_address >= text_section->vma
12667 && (fixP->fx_frag->fr_address
12668 < text_section->vma + bfd_get_section_size (text_section))
12669 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
12670 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
12671 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
12673 /* The branch offset is too large. If this is an
12674 unconditional branch, and we are not generating PIC code,
12675 we can convert it to an absolute jump instruction. */
12676 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
12677 insn = 0x0c000000; /* jal */
12679 insn = 0x08000000; /* j */
12680 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
12682 fixP->fx_addsy = section_symbol (text_section);
12683 *valP += md_pcrel_from (fixP);
12684 md_number_to_chars ((char *) buf, insn, 4);
12688 /* If we got here, we have branch-relaxation disabled,
12689 and there's nothing we can do to fix this instruction
12690 without turning it into a longer sequence. */
12691 as_bad_where (fixP->fx_file, fixP->fx_line,
12692 _("Branch out of range"));
12696 case BFD_RELOC_VTABLE_INHERIT:
12699 && !S_IS_DEFINED (fixP->fx_addsy)
12700 && !S_IS_WEAK (fixP->fx_addsy))
12701 S_SET_WEAK (fixP->fx_addsy);
12704 case BFD_RELOC_VTABLE_ENTRY:
12712 /* Remember value for tc_gen_reloc. */
12713 fixP->fx_addnumber = *valP;
12723 name = input_line_pointer;
12724 c = get_symbol_end ();
12725 p = (symbolS *) symbol_find_or_make (name);
12726 *input_line_pointer = c;
12730 /* Align the current frag to a given power of two. If a particular
12731 fill byte should be used, FILL points to an integer that contains
12732 that byte, otherwise FILL is null.
12734 The MIPS assembler also automatically adjusts any preceding
12738 mips_align (int to, int *fill, symbolS *label)
12740 mips_emit_delays ();
12741 mips_record_mips16_mode ();
12742 if (fill == NULL && subseg_text_p (now_seg))
12743 frag_align_code (to, 0);
12745 frag_align (to, fill ? *fill : 0, 0);
12746 record_alignment (now_seg, to);
12749 gas_assert (S_GET_SEGMENT (label) == now_seg);
12750 symbol_set_frag (label, frag_now);
12751 S_SET_VALUE (label, (valueT) frag_now_fix ());
12755 /* Align to a given power of two. .align 0 turns off the automatic
12756 alignment used by the data creating pseudo-ops. */
12759 s_align (int x ATTRIBUTE_UNUSED)
12761 int temp, fill_value, *fill_ptr;
12762 long max_alignment = 28;
12764 /* o Note that the assembler pulls down any immediately preceding label
12765 to the aligned address.
12766 o It's not documented but auto alignment is reinstated by
12767 a .align pseudo instruction.
12768 o Note also that after auto alignment is turned off the mips assembler
12769 issues an error on attempt to assemble an improperly aligned data item.
12772 temp = get_absolute_expression ();
12773 if (temp > max_alignment)
12774 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
12777 as_warn (_("Alignment negative: 0 assumed."));
12780 if (*input_line_pointer == ',')
12782 ++input_line_pointer;
12783 fill_value = get_absolute_expression ();
12784 fill_ptr = &fill_value;
12790 segment_info_type *si = seg_info (now_seg);
12791 struct insn_label_list *l = si->label_list;
12792 /* Auto alignment should be switched on by next section change. */
12794 mips_align (temp, fill_ptr, l != NULL ? l->label : NULL);
12801 demand_empty_rest_of_line ();
12805 s_change_sec (int sec)
12810 /* The ELF backend needs to know that we are changing sections, so
12811 that .previous works correctly. We could do something like check
12812 for an obj_section_change_hook macro, but that might be confusing
12813 as it would not be appropriate to use it in the section changing
12814 functions in read.c, since obj-elf.c intercepts those. FIXME:
12815 This should be cleaner, somehow. */
12817 obj_elf_section_change_hook ();
12820 mips_emit_delays ();
12831 subseg_set (bss_section, (subsegT) get_absolute_expression ());
12832 demand_empty_rest_of_line ();
12836 seg = subseg_new (RDATA_SECTION_NAME,
12837 (subsegT) get_absolute_expression ());
12840 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
12841 | SEC_READONLY | SEC_RELOC
12843 if (strncmp (TARGET_OS, "elf", 3) != 0)
12844 record_alignment (seg, 4);
12846 demand_empty_rest_of_line ();
12850 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
12853 bfd_set_section_flags (stdoutput, seg,
12854 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
12855 if (strncmp (TARGET_OS, "elf", 3) != 0)
12856 record_alignment (seg, 4);
12858 demand_empty_rest_of_line ();
12862 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
12865 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
12866 if (strncmp (TARGET_OS, "elf", 3) != 0)
12867 record_alignment (seg, 4);
12869 demand_empty_rest_of_line ();
12877 s_change_section (int ignore ATTRIBUTE_UNUSED)
12880 char *section_name;
12885 int section_entry_size;
12886 int section_alignment;
12891 section_name = input_line_pointer;
12892 c = get_symbol_end ();
12894 next_c = *(input_line_pointer + 1);
12896 /* Do we have .section Name<,"flags">? */
12897 if (c != ',' || (c == ',' && next_c == '"'))
12899 /* just after name is now '\0'. */
12900 *input_line_pointer = c;
12901 input_line_pointer = section_name;
12902 obj_elf_section (ignore);
12905 input_line_pointer++;
12907 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
12909 section_type = get_absolute_expression ();
12912 if (*input_line_pointer++ == ',')
12913 section_flag = get_absolute_expression ();
12916 if (*input_line_pointer++ == ',')
12917 section_entry_size = get_absolute_expression ();
12919 section_entry_size = 0;
12920 if (*input_line_pointer++ == ',')
12921 section_alignment = get_absolute_expression ();
12923 section_alignment = 0;
12924 /* FIXME: really ignore? */
12925 (void) section_alignment;
12927 section_name = xstrdup (section_name);
12929 /* When using the generic form of .section (as implemented by obj-elf.c),
12930 there's no way to set the section type to SHT_MIPS_DWARF. Users have
12931 traditionally had to fall back on the more common @progbits instead.
12933 There's nothing really harmful in this, since bfd will correct
12934 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
12935 means that, for backwards compatibility, the special_section entries
12936 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
12938 Even so, we shouldn't force users of the MIPS .section syntax to
12939 incorrectly label the sections as SHT_PROGBITS. The best compromise
12940 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
12941 generic type-checking code. */
12942 if (section_type == SHT_MIPS_DWARF)
12943 section_type = SHT_PROGBITS;
12945 obj_elf_change_section (section_name, section_type, section_flag,
12946 section_entry_size, 0, 0, 0);
12948 if (now_seg->name != section_name)
12949 free (section_name);
12950 #endif /* OBJ_ELF */
12954 mips_enable_auto_align (void)
12960 s_cons (int log_size)
12962 segment_info_type *si = seg_info (now_seg);
12963 struct insn_label_list *l = si->label_list;
12966 label = l != NULL ? l->label : NULL;
12967 mips_emit_delays ();
12968 if (log_size > 0 && auto_align)
12969 mips_align (log_size, 0, label);
12970 cons (1 << log_size);
12971 mips_clear_insn_labels ();
12975 s_float_cons (int type)
12977 segment_info_type *si = seg_info (now_seg);
12978 struct insn_label_list *l = si->label_list;
12981 label = l != NULL ? l->label : NULL;
12983 mips_emit_delays ();
12988 mips_align (3, 0, label);
12990 mips_align (2, 0, label);
12994 mips_clear_insn_labels ();
12997 /* Handle .globl. We need to override it because on Irix 5 you are
13000 where foo is an undefined symbol, to mean that foo should be
13001 considered to be the address of a function. */
13004 s_mips_globl (int x ATTRIBUTE_UNUSED)
13013 name = input_line_pointer;
13014 c = get_symbol_end ();
13015 symbolP = symbol_find_or_make (name);
13016 S_SET_EXTERNAL (symbolP);
13018 *input_line_pointer = c;
13019 SKIP_WHITESPACE ();
13021 /* On Irix 5, every global symbol that is not explicitly labelled as
13022 being a function is apparently labelled as being an object. */
13025 if (!is_end_of_line[(unsigned char) *input_line_pointer]
13026 && (*input_line_pointer != ','))
13031 secname = input_line_pointer;
13032 c = get_symbol_end ();
13033 sec = bfd_get_section_by_name (stdoutput, secname);
13035 as_bad (_("%s: no such section"), secname);
13036 *input_line_pointer = c;
13038 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
13039 flag = BSF_FUNCTION;
13042 symbol_get_bfdsym (symbolP)->flags |= flag;
13044 c = *input_line_pointer;
13047 input_line_pointer++;
13048 SKIP_WHITESPACE ();
13049 if (is_end_of_line[(unsigned char) *input_line_pointer])
13055 demand_empty_rest_of_line ();
13059 s_option (int x ATTRIBUTE_UNUSED)
13064 opt = input_line_pointer;
13065 c = get_symbol_end ();
13069 /* FIXME: What does this mean? */
13071 else if (strncmp (opt, "pic", 3) == 0)
13075 i = atoi (opt + 3);
13080 mips_pic = SVR4_PIC;
13081 mips_abicalls = TRUE;
13084 as_bad (_(".option pic%d not supported"), i);
13086 if (mips_pic == SVR4_PIC)
13088 if (g_switch_seen && g_switch_value != 0)
13089 as_warn (_("-G may not be used with SVR4 PIC code"));
13090 g_switch_value = 0;
13091 bfd_set_gp_size (stdoutput, 0);
13095 as_warn (_("Unrecognized option \"%s\""), opt);
13097 *input_line_pointer = c;
13098 demand_empty_rest_of_line ();
13101 /* This structure is used to hold a stack of .set values. */
13103 struct mips_option_stack
13105 struct mips_option_stack *next;
13106 struct mips_set_options options;
13109 static struct mips_option_stack *mips_opts_stack;
13111 /* Handle the .set pseudo-op. */
13114 s_mipsset (int x ATTRIBUTE_UNUSED)
13116 char *name = input_line_pointer, ch;
13118 while (!is_end_of_line[(unsigned char) *input_line_pointer])
13119 ++input_line_pointer;
13120 ch = *input_line_pointer;
13121 *input_line_pointer = '\0';
13123 if (strcmp (name, "reorder") == 0)
13125 if (mips_opts.noreorder)
13128 else if (strcmp (name, "noreorder") == 0)
13130 if (!mips_opts.noreorder)
13131 start_noreorder ();
13133 else if (strncmp (name, "at=", 3) == 0)
13135 char *s = name + 3;
13137 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
13138 as_bad (_("Unrecognized register name `%s'"), s);
13140 else if (strcmp (name, "at") == 0)
13142 mips_opts.at = ATREG;
13144 else if (strcmp (name, "noat") == 0)
13146 mips_opts.at = ZERO;
13148 else if (strcmp (name, "macro") == 0)
13150 mips_opts.warn_about_macros = 0;
13152 else if (strcmp (name, "nomacro") == 0)
13154 if (mips_opts.noreorder == 0)
13155 as_bad (_("`noreorder' must be set before `nomacro'"));
13156 mips_opts.warn_about_macros = 1;
13158 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
13160 mips_opts.nomove = 0;
13162 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
13164 mips_opts.nomove = 1;
13166 else if (strcmp (name, "bopt") == 0)
13168 mips_opts.nobopt = 0;
13170 else if (strcmp (name, "nobopt") == 0)
13172 mips_opts.nobopt = 1;
13174 else if (strcmp (name, "gp=default") == 0)
13175 mips_opts.gp32 = file_mips_gp32;
13176 else if (strcmp (name, "gp=32") == 0)
13177 mips_opts.gp32 = 1;
13178 else if (strcmp (name, "gp=64") == 0)
13180 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
13181 as_warn (_("%s isa does not support 64-bit registers"),
13182 mips_cpu_info_from_isa (mips_opts.isa)->name);
13183 mips_opts.gp32 = 0;
13185 else if (strcmp (name, "fp=default") == 0)
13186 mips_opts.fp32 = file_mips_fp32;
13187 else if (strcmp (name, "fp=32") == 0)
13188 mips_opts.fp32 = 1;
13189 else if (strcmp (name, "fp=64") == 0)
13191 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
13192 as_warn (_("%s isa does not support 64-bit floating point registers"),
13193 mips_cpu_info_from_isa (mips_opts.isa)->name);
13194 mips_opts.fp32 = 0;
13196 else if (strcmp (name, "softfloat") == 0)
13197 mips_opts.soft_float = 1;
13198 else if (strcmp (name, "hardfloat") == 0)
13199 mips_opts.soft_float = 0;
13200 else if (strcmp (name, "singlefloat") == 0)
13201 mips_opts.single_float = 1;
13202 else if (strcmp (name, "doublefloat") == 0)
13203 mips_opts.single_float = 0;
13204 else if (strcmp (name, "mips16") == 0
13205 || strcmp (name, "MIPS-16") == 0)
13206 mips_opts.mips16 = 1;
13207 else if (strcmp (name, "nomips16") == 0
13208 || strcmp (name, "noMIPS-16") == 0)
13209 mips_opts.mips16 = 0;
13210 else if (strcmp (name, "smartmips") == 0)
13212 if (!ISA_SUPPORTS_SMARTMIPS)
13213 as_warn (_("%s ISA does not support SmartMIPS ASE"),
13214 mips_cpu_info_from_isa (mips_opts.isa)->name);
13215 mips_opts.ase_smartmips = 1;
13217 else if (strcmp (name, "nosmartmips") == 0)
13218 mips_opts.ase_smartmips = 0;
13219 else if (strcmp (name, "mips3d") == 0)
13220 mips_opts.ase_mips3d = 1;
13221 else if (strcmp (name, "nomips3d") == 0)
13222 mips_opts.ase_mips3d = 0;
13223 else if (strcmp (name, "mdmx") == 0)
13224 mips_opts.ase_mdmx = 1;
13225 else if (strcmp (name, "nomdmx") == 0)
13226 mips_opts.ase_mdmx = 0;
13227 else if (strcmp (name, "dsp") == 0)
13229 if (!ISA_SUPPORTS_DSP_ASE)
13230 as_warn (_("%s ISA does not support DSP ASE"),
13231 mips_cpu_info_from_isa (mips_opts.isa)->name);
13232 mips_opts.ase_dsp = 1;
13233 mips_opts.ase_dspr2 = 0;
13235 else if (strcmp (name, "nodsp") == 0)
13237 mips_opts.ase_dsp = 0;
13238 mips_opts.ase_dspr2 = 0;
13240 else if (strcmp (name, "dspr2") == 0)
13242 if (!ISA_SUPPORTS_DSPR2_ASE)
13243 as_warn (_("%s ISA does not support DSP R2 ASE"),
13244 mips_cpu_info_from_isa (mips_opts.isa)->name);
13245 mips_opts.ase_dspr2 = 1;
13246 mips_opts.ase_dsp = 1;
13248 else if (strcmp (name, "nodspr2") == 0)
13250 mips_opts.ase_dspr2 = 0;
13251 mips_opts.ase_dsp = 0;
13253 else if (strcmp (name, "mt") == 0)
13255 if (!ISA_SUPPORTS_MT_ASE)
13256 as_warn (_("%s ISA does not support MT ASE"),
13257 mips_cpu_info_from_isa (mips_opts.isa)->name);
13258 mips_opts.ase_mt = 1;
13260 else if (strcmp (name, "nomt") == 0)
13261 mips_opts.ase_mt = 0;
13262 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
13266 /* Permit the user to change the ISA and architecture on the fly.
13267 Needless to say, misuse can cause serious problems. */
13268 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
13271 mips_opts.isa = file_mips_isa;
13272 mips_opts.arch = file_mips_arch;
13274 else if (strncmp (name, "arch=", 5) == 0)
13276 const struct mips_cpu_info *p;
13278 p = mips_parse_cpu("internal use", name + 5);
13280 as_bad (_("unknown architecture %s"), name + 5);
13283 mips_opts.arch = p->cpu;
13284 mips_opts.isa = p->isa;
13287 else if (strncmp (name, "mips", 4) == 0)
13289 const struct mips_cpu_info *p;
13291 p = mips_parse_cpu("internal use", name);
13293 as_bad (_("unknown ISA level %s"), name + 4);
13296 mips_opts.arch = p->cpu;
13297 mips_opts.isa = p->isa;
13301 as_bad (_("unknown ISA or architecture %s"), name);
13303 switch (mips_opts.isa)
13311 mips_opts.gp32 = 1;
13312 mips_opts.fp32 = 1;
13319 mips_opts.gp32 = 0;
13320 mips_opts.fp32 = 0;
13323 as_bad (_("unknown ISA level %s"), name + 4);
13328 mips_opts.gp32 = file_mips_gp32;
13329 mips_opts.fp32 = file_mips_fp32;
13332 else if (strcmp (name, "autoextend") == 0)
13333 mips_opts.noautoextend = 0;
13334 else if (strcmp (name, "noautoextend") == 0)
13335 mips_opts.noautoextend = 1;
13336 else if (strcmp (name, "push") == 0)
13338 struct mips_option_stack *s;
13340 s = (struct mips_option_stack *) xmalloc (sizeof *s);
13341 s->next = mips_opts_stack;
13342 s->options = mips_opts;
13343 mips_opts_stack = s;
13345 else if (strcmp (name, "pop") == 0)
13347 struct mips_option_stack *s;
13349 s = mips_opts_stack;
13351 as_bad (_(".set pop with no .set push"));
13354 /* If we're changing the reorder mode we need to handle
13355 delay slots correctly. */
13356 if (s->options.noreorder && ! mips_opts.noreorder)
13357 start_noreorder ();
13358 else if (! s->options.noreorder && mips_opts.noreorder)
13361 mips_opts = s->options;
13362 mips_opts_stack = s->next;
13366 else if (strcmp (name, "sym32") == 0)
13367 mips_opts.sym32 = TRUE;
13368 else if (strcmp (name, "nosym32") == 0)
13369 mips_opts.sym32 = FALSE;
13370 else if (strchr (name, ','))
13372 /* Generic ".set" directive; use the generic handler. */
13373 *input_line_pointer = ch;
13374 input_line_pointer = name;
13380 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
13382 *input_line_pointer = ch;
13383 demand_empty_rest_of_line ();
13386 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
13387 .option pic2. It means to generate SVR4 PIC calls. */
13390 s_abicalls (int ignore ATTRIBUTE_UNUSED)
13392 mips_pic = SVR4_PIC;
13393 mips_abicalls = TRUE;
13395 if (g_switch_seen && g_switch_value != 0)
13396 as_warn (_("-G may not be used with SVR4 PIC code"));
13397 g_switch_value = 0;
13399 bfd_set_gp_size (stdoutput, 0);
13400 demand_empty_rest_of_line ();
13403 /* Handle the .cpload pseudo-op. This is used when generating SVR4
13404 PIC code. It sets the $gp register for the function based on the
13405 function address, which is in the register named in the argument.
13406 This uses a relocation against _gp_disp, which is handled specially
13407 by the linker. The result is:
13408 lui $gp,%hi(_gp_disp)
13409 addiu $gp,$gp,%lo(_gp_disp)
13410 addu $gp,$gp,.cpload argument
13411 The .cpload argument is normally $25 == $t9.
13413 The -mno-shared option changes this to:
13414 lui $gp,%hi(__gnu_local_gp)
13415 addiu $gp,$gp,%lo(__gnu_local_gp)
13416 and the argument is ignored. This saves an instruction, but the
13417 resulting code is not position independent; it uses an absolute
13418 address for __gnu_local_gp. Thus code assembled with -mno-shared
13419 can go into an ordinary executable, but not into a shared library. */
13422 s_cpload (int ignore ATTRIBUTE_UNUSED)
13428 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13429 .cpload is ignored. */
13430 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
13436 /* .cpload should be in a .set noreorder section. */
13437 if (mips_opts.noreorder == 0)
13438 as_warn (_(".cpload not in noreorder section"));
13440 reg = tc_get_register (0);
13442 /* If we need to produce a 64-bit address, we are better off using
13443 the default instruction sequence. */
13444 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
13446 ex.X_op = O_symbol;
13447 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
13449 ex.X_op_symbol = NULL;
13450 ex.X_add_number = 0;
13452 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13453 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
13456 macro_build_lui (&ex, mips_gp_register);
13457 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
13458 mips_gp_register, BFD_RELOC_LO16);
13460 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
13461 mips_gp_register, reg);
13464 demand_empty_rest_of_line ();
13467 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
13468 .cpsetup $reg1, offset|$reg2, label
13470 If offset is given, this results in:
13471 sd $gp, offset($sp)
13472 lui $gp, %hi(%neg(%gp_rel(label)))
13473 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13474 daddu $gp, $gp, $reg1
13476 If $reg2 is given, this results in:
13477 daddu $reg2, $gp, $0
13478 lui $gp, %hi(%neg(%gp_rel(label)))
13479 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13480 daddu $gp, $gp, $reg1
13481 $reg1 is normally $25 == $t9.
13483 The -mno-shared option replaces the last three instructions with
13485 addiu $gp,$gp,%lo(_gp) */
13488 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
13490 expressionS ex_off;
13491 expressionS ex_sym;
13494 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
13495 We also need NewABI support. */
13496 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13502 reg1 = tc_get_register (0);
13503 SKIP_WHITESPACE ();
13504 if (*input_line_pointer != ',')
13506 as_bad (_("missing argument separator ',' for .cpsetup"));
13510 ++input_line_pointer;
13511 SKIP_WHITESPACE ();
13512 if (*input_line_pointer == '$')
13514 mips_cpreturn_register = tc_get_register (0);
13515 mips_cpreturn_offset = -1;
13519 mips_cpreturn_offset = get_absolute_expression ();
13520 mips_cpreturn_register = -1;
13522 SKIP_WHITESPACE ();
13523 if (*input_line_pointer != ',')
13525 as_bad (_("missing argument separator ',' for .cpsetup"));
13529 ++input_line_pointer;
13530 SKIP_WHITESPACE ();
13531 expression (&ex_sym);
13534 if (mips_cpreturn_register == -1)
13536 ex_off.X_op = O_constant;
13537 ex_off.X_add_symbol = NULL;
13538 ex_off.X_op_symbol = NULL;
13539 ex_off.X_add_number = mips_cpreturn_offset;
13541 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
13542 BFD_RELOC_LO16, SP);
13545 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
13546 mips_gp_register, 0);
13548 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
13550 macro_build (&ex_sym, "lui", "t,u", mips_gp_register,
13551 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
13554 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
13555 mips_gp_register, -1, BFD_RELOC_GPREL16,
13556 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
13558 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
13559 mips_gp_register, reg1);
13565 ex.X_op = O_symbol;
13566 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
13567 ex.X_op_symbol = NULL;
13568 ex.X_add_number = 0;
13570 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13571 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
13573 macro_build_lui (&ex, mips_gp_register);
13574 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
13575 mips_gp_register, BFD_RELOC_LO16);
13580 demand_empty_rest_of_line ();
13584 s_cplocal (int ignore ATTRIBUTE_UNUSED)
13586 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
13587 .cplocal is ignored. */
13588 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13594 mips_gp_register = tc_get_register (0);
13595 demand_empty_rest_of_line ();
13598 /* Handle the .cprestore pseudo-op. This stores $gp into a given
13599 offset from $sp. The offset is remembered, and after making a PIC
13600 call $gp is restored from that location. */
13603 s_cprestore (int ignore ATTRIBUTE_UNUSED)
13607 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13608 .cprestore is ignored. */
13609 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
13615 mips_cprestore_offset = get_absolute_expression ();
13616 mips_cprestore_valid = 1;
13618 ex.X_op = O_constant;
13619 ex.X_add_symbol = NULL;
13620 ex.X_op_symbol = NULL;
13621 ex.X_add_number = mips_cprestore_offset;
13624 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
13625 SP, HAVE_64BIT_ADDRESSES);
13628 demand_empty_rest_of_line ();
13631 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
13632 was given in the preceding .cpsetup, it results in:
13633 ld $gp, offset($sp)
13635 If a register $reg2 was given there, it results in:
13636 daddu $gp, $reg2, $0 */
13639 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
13643 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
13644 We also need NewABI support. */
13645 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13652 if (mips_cpreturn_register == -1)
13654 ex.X_op = O_constant;
13655 ex.X_add_symbol = NULL;
13656 ex.X_op_symbol = NULL;
13657 ex.X_add_number = mips_cpreturn_offset;
13659 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
13662 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
13663 mips_cpreturn_register, 0);
13666 demand_empty_rest_of_line ();
13669 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
13670 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
13671 use in DWARF debug information. */
13674 s_dtprel_internal (size_t bytes)
13681 if (ex.X_op != O_symbol)
13683 as_bad (_("Unsupported use of %s"), (bytes == 8
13686 ignore_rest_of_line ();
13689 p = frag_more (bytes);
13690 md_number_to_chars (p, 0, bytes);
13691 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
13693 ? BFD_RELOC_MIPS_TLS_DTPREL64
13694 : BFD_RELOC_MIPS_TLS_DTPREL32));
13696 demand_empty_rest_of_line ();
13699 /* Handle .dtprelword. */
13702 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
13704 s_dtprel_internal (4);
13707 /* Handle .dtpreldword. */
13710 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
13712 s_dtprel_internal (8);
13715 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
13716 code. It sets the offset to use in gp_rel relocations. */
13719 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
13721 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
13722 We also need NewABI support. */
13723 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13729 mips_gprel_offset = get_absolute_expression ();
13731 demand_empty_rest_of_line ();
13734 /* Handle the .gpword pseudo-op. This is used when generating PIC
13735 code. It generates a 32 bit GP relative reloc. */
13738 s_gpword (int ignore ATTRIBUTE_UNUSED)
13740 segment_info_type *si;
13741 struct insn_label_list *l;
13746 /* When not generating PIC code, this is treated as .word. */
13747 if (mips_pic != SVR4_PIC)
13753 si = seg_info (now_seg);
13754 l = si->label_list;
13755 label = l != NULL ? l->label : NULL;
13756 mips_emit_delays ();
13758 mips_align (2, 0, label);
13761 mips_clear_insn_labels ();
13763 if (ex.X_op != O_symbol || ex.X_add_number != 0)
13765 as_bad (_("Unsupported use of .gpword"));
13766 ignore_rest_of_line ();
13770 md_number_to_chars (p, 0, 4);
13771 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
13772 BFD_RELOC_GPREL32);
13774 demand_empty_rest_of_line ();
13778 s_gpdword (int ignore ATTRIBUTE_UNUSED)
13780 segment_info_type *si;
13781 struct insn_label_list *l;
13786 /* When not generating PIC code, this is treated as .dword. */
13787 if (mips_pic != SVR4_PIC)
13793 si = seg_info (now_seg);
13794 l = si->label_list;
13795 label = l != NULL ? l->label : NULL;
13796 mips_emit_delays ();
13798 mips_align (3, 0, label);
13801 mips_clear_insn_labels ();
13803 if (ex.X_op != O_symbol || ex.X_add_number != 0)
13805 as_bad (_("Unsupported use of .gpdword"));
13806 ignore_rest_of_line ();
13810 md_number_to_chars (p, 0, 8);
13811 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
13812 BFD_RELOC_GPREL32)->fx_tcbit = 1;
13814 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
13815 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
13816 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
13818 demand_empty_rest_of_line ();
13821 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
13822 tables in SVR4 PIC code. */
13825 s_cpadd (int ignore ATTRIBUTE_UNUSED)
13829 /* This is ignored when not generating SVR4 PIC code. */
13830 if (mips_pic != SVR4_PIC)
13836 /* Add $gp to the register named as an argument. */
13838 reg = tc_get_register (0);
13839 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
13842 demand_empty_rest_of_line ();
13845 /* Handle the .insn pseudo-op. This marks instruction labels in
13846 mips16 mode. This permits the linker to handle them specially,
13847 such as generating jalx instructions when needed. We also make
13848 them odd for the duration of the assembly, in order to generate the
13849 right sort of code. We will make them even in the adjust_symtab
13850 routine, while leaving them marked. This is convenient for the
13851 debugger and the disassembler. The linker knows to make them odd
13855 s_insn (int ignore ATTRIBUTE_UNUSED)
13857 mips16_mark_labels ();
13859 demand_empty_rest_of_line ();
13862 /* Handle a .stabn directive. We need these in order to mark a label
13863 as being a mips16 text label correctly. Sometimes the compiler
13864 will emit a label, followed by a .stabn, and then switch sections.
13865 If the label and .stabn are in mips16 mode, then the label is
13866 really a mips16 text label. */
13869 s_mips_stab (int type)
13872 mips16_mark_labels ();
13877 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
13880 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
13887 name = input_line_pointer;
13888 c = get_symbol_end ();
13889 symbolP = symbol_find_or_make (name);
13890 S_SET_WEAK (symbolP);
13891 *input_line_pointer = c;
13893 SKIP_WHITESPACE ();
13895 if (! is_end_of_line[(unsigned char) *input_line_pointer])
13897 if (S_IS_DEFINED (symbolP))
13899 as_bad (_("ignoring attempt to redefine symbol %s"),
13900 S_GET_NAME (symbolP));
13901 ignore_rest_of_line ();
13905 if (*input_line_pointer == ',')
13907 ++input_line_pointer;
13908 SKIP_WHITESPACE ();
13912 if (exp.X_op != O_symbol)
13914 as_bad (_("bad .weakext directive"));
13915 ignore_rest_of_line ();
13918 symbol_set_value_expression (symbolP, &exp);
13921 demand_empty_rest_of_line ();
13924 /* Parse a register string into a number. Called from the ECOFF code
13925 to parse .frame. The argument is non-zero if this is the frame
13926 register, so that we can record it in mips_frame_reg. */
13929 tc_get_register (int frame)
13933 SKIP_WHITESPACE ();
13934 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
13938 mips_frame_reg = reg != 0 ? reg : SP;
13939 mips_frame_reg_valid = 1;
13940 mips_cprestore_valid = 0;
13946 md_section_align (asection *seg, valueT addr)
13948 int align = bfd_get_section_alignment (stdoutput, seg);
13952 /* We don't need to align ELF sections to the full alignment.
13953 However, Irix 5 may prefer that we align them at least to a 16
13954 byte boundary. We don't bother to align the sections if we
13955 are targeted for an embedded system. */
13956 if (strncmp (TARGET_OS, "elf", 3) == 0)
13962 return ((addr + (1 << align) - 1) & (-1 << align));
13965 /* Utility routine, called from above as well. If called while the
13966 input file is still being read, it's only an approximation. (For
13967 example, a symbol may later become defined which appeared to be
13968 undefined earlier.) */
13971 nopic_need_relax (symbolS *sym, int before_relaxing)
13976 if (g_switch_value > 0)
13978 const char *symname;
13981 /* Find out whether this symbol can be referenced off the $gp
13982 register. It can be if it is smaller than the -G size or if
13983 it is in the .sdata or .sbss section. Certain symbols can
13984 not be referenced off the $gp, although it appears as though
13986 symname = S_GET_NAME (sym);
13987 if (symname != (const char *) NULL
13988 && (strcmp (symname, "eprol") == 0
13989 || strcmp (symname, "etext") == 0
13990 || strcmp (symname, "_gp") == 0
13991 || strcmp (symname, "edata") == 0
13992 || strcmp (symname, "_fbss") == 0
13993 || strcmp (symname, "_fdata") == 0
13994 || strcmp (symname, "_ftext") == 0
13995 || strcmp (symname, "end") == 0
13996 || strcmp (symname, "_gp_disp") == 0))
13998 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
14000 #ifndef NO_ECOFF_DEBUGGING
14001 || (symbol_get_obj (sym)->ecoff_extern_size != 0
14002 && (symbol_get_obj (sym)->ecoff_extern_size
14003 <= g_switch_value))
14005 /* We must defer this decision until after the whole
14006 file has been read, since there might be a .extern
14007 after the first use of this symbol. */
14008 || (before_relaxing
14009 #ifndef NO_ECOFF_DEBUGGING
14010 && symbol_get_obj (sym)->ecoff_extern_size == 0
14012 && S_GET_VALUE (sym) == 0)
14013 || (S_GET_VALUE (sym) != 0
14014 && S_GET_VALUE (sym) <= g_switch_value)))
14018 const char *segname;
14020 segname = segment_name (S_GET_SEGMENT (sym));
14021 gas_assert (strcmp (segname, ".lit8") != 0
14022 && strcmp (segname, ".lit4") != 0);
14023 change = (strcmp (segname, ".sdata") != 0
14024 && strcmp (segname, ".sbss") != 0
14025 && strncmp (segname, ".sdata.", 7) != 0
14026 && strncmp (segname, ".sbss.", 6) != 0
14027 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
14028 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
14033 /* We are not optimizing for the $gp register. */
14038 /* Return true if the given symbol should be considered local for SVR4 PIC. */
14041 pic_need_relax (symbolS *sym, asection *segtype)
14045 /* Handle the case of a symbol equated to another symbol. */
14046 while (symbol_equated_reloc_p (sym))
14050 /* It's possible to get a loop here in a badly written program. */
14051 n = symbol_get_value_expression (sym)->X_add_symbol;
14057 if (symbol_section_p (sym))
14060 symsec = S_GET_SEGMENT (sym);
14062 /* This must duplicate the test in adjust_reloc_syms. */
14063 return (symsec != &bfd_und_section
14064 && symsec != &bfd_abs_section
14065 && !bfd_is_com_section (symsec)
14066 && !s_is_linkonce (sym, segtype)
14068 /* A global or weak symbol is treated as external. */
14069 && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
14075 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
14076 extended opcode. SEC is the section the frag is in. */
14079 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
14082 const struct mips16_immed_operand *op;
14084 int mintiny, maxtiny;
14088 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
14090 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
14093 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
14094 op = mips16_immed_operands;
14095 while (op->type != type)
14098 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
14103 if (type == '<' || type == '>' || type == '[' || type == ']')
14106 maxtiny = 1 << op->nbits;
14111 maxtiny = (1 << op->nbits) - 1;
14116 mintiny = - (1 << (op->nbits - 1));
14117 maxtiny = (1 << (op->nbits - 1)) - 1;
14120 sym_frag = symbol_get_frag (fragp->fr_symbol);
14121 val = S_GET_VALUE (fragp->fr_symbol);
14122 symsec = S_GET_SEGMENT (fragp->fr_symbol);
14128 /* We won't have the section when we are called from
14129 mips_relax_frag. However, we will always have been called
14130 from md_estimate_size_before_relax first. If this is a
14131 branch to a different section, we mark it as such. If SEC is
14132 NULL, and the frag is not marked, then it must be a branch to
14133 the same section. */
14136 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
14141 /* Must have been called from md_estimate_size_before_relax. */
14144 fragp->fr_subtype =
14145 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14147 /* FIXME: We should support this, and let the linker
14148 catch branches and loads that are out of range. */
14149 as_bad_where (fragp->fr_file, fragp->fr_line,
14150 _("unsupported PC relative reference to different section"));
14154 if (fragp != sym_frag && sym_frag->fr_address == 0)
14155 /* Assume non-extended on the first relaxation pass.
14156 The address we have calculated will be bogus if this is
14157 a forward branch to another frag, as the forward frag
14158 will have fr_address == 0. */
14162 /* In this case, we know for sure that the symbol fragment is in
14163 the same section. If the relax_marker of the symbol fragment
14164 differs from the relax_marker of this fragment, we have not
14165 yet adjusted the symbol fragment fr_address. We want to add
14166 in STRETCH in order to get a better estimate of the address.
14167 This particularly matters because of the shift bits. */
14169 && sym_frag->relax_marker != fragp->relax_marker)
14173 /* Adjust stretch for any alignment frag. Note that if have
14174 been expanding the earlier code, the symbol may be
14175 defined in what appears to be an earlier frag. FIXME:
14176 This doesn't handle the fr_subtype field, which specifies
14177 a maximum number of bytes to skip when doing an
14179 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
14181 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
14184 stretch = - ((- stretch)
14185 & ~ ((1 << (int) f->fr_offset) - 1));
14187 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
14196 addr = fragp->fr_address + fragp->fr_fix;
14198 /* The base address rules are complicated. The base address of
14199 a branch is the following instruction. The base address of a
14200 PC relative load or add is the instruction itself, but if it
14201 is in a delay slot (in which case it can not be extended) use
14202 the address of the instruction whose delay slot it is in. */
14203 if (type == 'p' || type == 'q')
14207 /* If we are currently assuming that this frag should be
14208 extended, then, the current address is two bytes
14210 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14213 /* Ignore the low bit in the target, since it will be set
14214 for a text label. */
14215 if ((val & 1) != 0)
14218 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
14220 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
14223 val -= addr & ~ ((1 << op->shift) - 1);
14225 /* Branch offsets have an implicit 0 in the lowest bit. */
14226 if (type == 'p' || type == 'q')
14229 /* If any of the shifted bits are set, we must use an extended
14230 opcode. If the address depends on the size of this
14231 instruction, this can lead to a loop, so we arrange to always
14232 use an extended opcode. We only check this when we are in
14233 the main relaxation loop, when SEC is NULL. */
14234 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
14236 fragp->fr_subtype =
14237 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14241 /* If we are about to mark a frag as extended because the value
14242 is precisely maxtiny + 1, then there is a chance of an
14243 infinite loop as in the following code:
14248 In this case when the la is extended, foo is 0x3fc bytes
14249 away, so the la can be shrunk, but then foo is 0x400 away, so
14250 the la must be extended. To avoid this loop, we mark the
14251 frag as extended if it was small, and is about to become
14252 extended with a value of maxtiny + 1. */
14253 if (val == ((maxtiny + 1) << op->shift)
14254 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
14257 fragp->fr_subtype =
14258 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14262 else if (symsec != absolute_section && sec != NULL)
14263 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
14265 if ((val & ((1 << op->shift) - 1)) != 0
14266 || val < (mintiny << op->shift)
14267 || val > (maxtiny << op->shift))
14273 /* Compute the length of a branch sequence, and adjust the
14274 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
14275 worst-case length is computed, with UPDATE being used to indicate
14276 whether an unconditional (-1), branch-likely (+1) or regular (0)
14277 branch is to be computed. */
14279 relaxed_branch_length (fragS *fragp, asection *sec, int update)
14281 bfd_boolean toofar;
14285 && S_IS_DEFINED (fragp->fr_symbol)
14286 && sec == S_GET_SEGMENT (fragp->fr_symbol))
14291 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
14293 addr = fragp->fr_address + fragp->fr_fix + 4;
14297 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
14300 /* If the symbol is not defined or it's in a different segment,
14301 assume the user knows what's going on and emit a short
14307 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
14309 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
14310 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
14311 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
14312 RELAX_BRANCH_LINK (fragp->fr_subtype),
14318 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
14321 if (mips_pic != NO_PIC)
14323 /* Additional space for PIC loading of target address. */
14325 if (mips_opts.isa == ISA_MIPS1)
14326 /* Additional space for $at-stabilizing nop. */
14330 /* If branch is conditional. */
14331 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
14338 /* Estimate the size of a frag before relaxing. Unless this is the
14339 mips16, we are not really relaxing here, and the final size is
14340 encoded in the subtype information. For the mips16, we have to
14341 decide whether we are using an extended opcode or not. */
14344 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
14348 if (RELAX_BRANCH_P (fragp->fr_subtype))
14351 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
14353 return fragp->fr_var;
14356 if (RELAX_MIPS16_P (fragp->fr_subtype))
14357 /* We don't want to modify the EXTENDED bit here; it might get us
14358 into infinite loops. We change it only in mips_relax_frag(). */
14359 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
14361 if (mips_pic == NO_PIC)
14362 change = nopic_need_relax (fragp->fr_symbol, 0);
14363 else if (mips_pic == SVR4_PIC)
14364 change = pic_need_relax (fragp->fr_symbol, segtype);
14365 else if (mips_pic == VXWORKS_PIC)
14366 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
14373 fragp->fr_subtype |= RELAX_USE_SECOND;
14374 return -RELAX_FIRST (fragp->fr_subtype);
14377 return -RELAX_SECOND (fragp->fr_subtype);
14380 /* This is called to see whether a reloc against a defined symbol
14381 should be converted into a reloc against a section. */
14384 mips_fix_adjustable (fixS *fixp)
14386 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
14387 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
14390 if (fixp->fx_addsy == NULL)
14393 /* If symbol SYM is in a mergeable section, relocations of the form
14394 SYM + 0 can usually be made section-relative. The mergeable data
14395 is then identified by the section offset rather than by the symbol.
14397 However, if we're generating REL LO16 relocations, the offset is split
14398 between the LO16 and parterning high part relocation. The linker will
14399 need to recalculate the complete offset in order to correctly identify
14402 The linker has traditionally not looked for the parterning high part
14403 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
14404 placed anywhere. Rather than break backwards compatibility by changing
14405 this, it seems better not to force the issue, and instead keep the
14406 original symbol. This will work with either linker behavior. */
14407 if ((lo16_reloc_p (fixp->fx_r_type)
14408 || reloc_needs_lo_p (fixp->fx_r_type))
14409 && HAVE_IN_PLACE_ADDENDS
14410 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
14413 /* There is no place to store an in-place offset for JALR relocations.
14414 Likewise an in-range offset of PC-relative relocations may overflow
14415 the in-place relocatable field if recalculated against the start
14416 address of the symbol's containing section. */
14417 if (HAVE_IN_PLACE_ADDENDS
14418 && (fixp->fx_pcrel || fixp->fx_r_type == BFD_RELOC_MIPS_JALR))
14422 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
14423 to a floating-point stub. The same is true for non-R_MIPS16_26
14424 relocations against MIPS16 functions; in this case, the stub becomes
14425 the function's canonical address.
14427 Floating-point stubs are stored in unique .mips16.call.* or
14428 .mips16.fn.* sections. If a stub T for function F is in section S,
14429 the first relocation in section S must be against F; this is how the
14430 linker determines the target function. All relocations that might
14431 resolve to T must also be against F. We therefore have the following
14432 restrictions, which are given in an intentionally-redundant way:
14434 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
14437 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
14438 if that stub might be used.
14440 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
14443 4. We cannot reduce a stub's relocations against MIPS16 symbols if
14444 that stub might be used.
14446 There is a further restriction:
14448 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols
14449 on targets with in-place addends; the relocation field cannot
14450 encode the low bit.
14452 For simplicity, we deal with (3)-(5) by not reducing _any_ relocation
14453 against a MIPS16 symbol.
14455 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
14456 relocation against some symbol R, no relocation against R may be
14457 reduced. (Note that this deals with (2) as well as (1) because
14458 relocations against global symbols will never be reduced on ELF
14459 targets.) This approach is a little simpler than trying to detect
14460 stub sections, and gives the "all or nothing" per-symbol consistency
14461 that we have for MIPS16 symbols. */
14463 && fixp->fx_subsy == NULL
14464 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
14465 || *symbol_get_tc (fixp->fx_addsy)))
14472 /* Translate internal representation of relocation info to BFD target
14476 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
14478 static arelent *retval[4];
14480 bfd_reloc_code_real_type code;
14482 memset (retval, 0, sizeof(retval));
14483 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
14484 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
14485 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
14486 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
14488 if (fixp->fx_pcrel)
14490 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2);
14492 /* At this point, fx_addnumber is "symbol offset - pcrel address".
14493 Relocations want only the symbol offset. */
14494 reloc->addend = fixp->fx_addnumber + reloc->address;
14497 /* A gruesome hack which is a result of the gruesome gas
14498 reloc handling. What's worse, for COFF (as opposed to
14499 ECOFF), we might need yet another copy of reloc->address.
14500 See bfd_install_relocation. */
14501 reloc->addend += reloc->address;
14505 reloc->addend = fixp->fx_addnumber;
14507 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
14508 entry to be used in the relocation's section offset. */
14509 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
14511 reloc->address = reloc->addend;
14515 code = fixp->fx_r_type;
14517 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
14518 if (reloc->howto == NULL)
14520 as_bad_where (fixp->fx_file, fixp->fx_line,
14521 _("Can not represent %s relocation in this object file format"),
14522 bfd_get_reloc_code_name (code));
14529 /* Relax a machine dependent frag. This returns the amount by which
14530 the current size of the frag should change. */
14533 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
14535 if (RELAX_BRANCH_P (fragp->fr_subtype))
14537 offsetT old_var = fragp->fr_var;
14539 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
14541 return fragp->fr_var - old_var;
14544 if (! RELAX_MIPS16_P (fragp->fr_subtype))
14547 if (mips16_extended_frag (fragp, NULL, stretch))
14549 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14551 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
14556 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14558 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
14565 /* Convert a machine dependent frag. */
14568 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
14570 if (RELAX_BRANCH_P (fragp->fr_subtype))
14573 unsigned long insn;
14577 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
14579 if (target_big_endian)
14580 insn = bfd_getb32 (buf);
14582 insn = bfd_getl32 (buf);
14584 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
14586 /* We generate a fixup instead of applying it right now
14587 because, if there are linker relaxations, we're going to
14588 need the relocations. */
14589 exp.X_op = O_symbol;
14590 exp.X_add_symbol = fragp->fr_symbol;
14591 exp.X_add_number = fragp->fr_offset;
14593 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14594 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2);
14595 fixp->fx_file = fragp->fr_file;
14596 fixp->fx_line = fragp->fr_line;
14598 md_number_to_chars ((char *) buf, insn, 4);
14605 as_warn_where (fragp->fr_file, fragp->fr_line,
14606 _("Relaxed out-of-range branch into a jump"));
14608 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
14611 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14613 /* Reverse the branch. */
14614 switch ((insn >> 28) & 0xf)
14617 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
14618 have the condition reversed by tweaking a single
14619 bit, and their opcodes all have 0x4???????. */
14620 gas_assert ((insn & 0xf1000000) == 0x41000000);
14621 insn ^= 0x00010000;
14625 /* bltz 0x04000000 bgez 0x04010000
14626 bltzal 0x04100000 bgezal 0x04110000 */
14627 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
14628 insn ^= 0x00010000;
14632 /* beq 0x10000000 bne 0x14000000
14633 blez 0x18000000 bgtz 0x1c000000 */
14634 insn ^= 0x04000000;
14642 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
14644 /* Clear the and-link bit. */
14645 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
14647 /* bltzal 0x04100000 bgezal 0x04110000
14648 bltzall 0x04120000 bgezall 0x04130000 */
14649 insn &= ~0x00100000;
14652 /* Branch over the branch (if the branch was likely) or the
14653 full jump (not likely case). Compute the offset from the
14654 current instruction to branch to. */
14655 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14659 /* How many bytes in instructions we've already emitted? */
14660 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
14661 /* How many bytes in instructions from here to the end? */
14662 i = fragp->fr_var - i;
14664 /* Convert to instruction count. */
14666 /* Branch counts from the next instruction. */
14669 /* Branch over the jump. */
14670 md_number_to_chars ((char *) buf, insn, 4);
14674 md_number_to_chars ((char *) buf, 0, 4);
14677 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14679 /* beql $0, $0, 2f */
14681 /* Compute the PC offset from the current instruction to
14682 the end of the variable frag. */
14683 /* How many bytes in instructions we've already emitted? */
14684 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
14685 /* How many bytes in instructions from here to the end? */
14686 i = fragp->fr_var - i;
14687 /* Convert to instruction count. */
14689 /* Don't decrement i, because we want to branch over the
14693 md_number_to_chars ((char *) buf, insn, 4);
14696 md_number_to_chars ((char *) buf, 0, 4);
14701 if (mips_pic == NO_PIC)
14704 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
14705 ? 0x0c000000 : 0x08000000);
14706 exp.X_op = O_symbol;
14707 exp.X_add_symbol = fragp->fr_symbol;
14708 exp.X_add_number = fragp->fr_offset;
14710 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14711 4, &exp, FALSE, BFD_RELOC_MIPS_JMP);
14712 fixp->fx_file = fragp->fr_file;
14713 fixp->fx_line = fragp->fr_line;
14715 md_number_to_chars ((char *) buf, insn, 4);
14720 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
14722 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
14723 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
14724 insn |= at << OP_SH_RT;
14725 exp.X_op = O_symbol;
14726 exp.X_add_symbol = fragp->fr_symbol;
14727 exp.X_add_number = fragp->fr_offset;
14729 if (fragp->fr_offset)
14731 exp.X_add_symbol = make_expr_symbol (&exp);
14732 exp.X_add_number = 0;
14735 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14736 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16);
14737 fixp->fx_file = fragp->fr_file;
14738 fixp->fx_line = fragp->fr_line;
14740 md_number_to_chars ((char *) buf, insn, 4);
14743 if (mips_opts.isa == ISA_MIPS1)
14746 md_number_to_chars ((char *) buf, 0, 4);
14750 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
14751 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
14752 insn |= at << OP_SH_RS | at << OP_SH_RT;
14754 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14755 4, &exp, FALSE, BFD_RELOC_LO16);
14756 fixp->fx_file = fragp->fr_file;
14757 fixp->fx_line = fragp->fr_line;
14759 md_number_to_chars ((char *) buf, insn, 4);
14763 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
14767 insn |= at << OP_SH_RS;
14769 md_number_to_chars ((char *) buf, insn, 4);
14774 gas_assert (buf == (bfd_byte *)fragp->fr_literal
14775 + fragp->fr_fix + fragp->fr_var);
14777 fragp->fr_fix += fragp->fr_var;
14782 if (RELAX_MIPS16_P (fragp->fr_subtype))
14785 const struct mips16_immed_operand *op;
14786 bfd_boolean small, ext;
14789 unsigned long insn;
14790 bfd_boolean use_extend;
14791 unsigned short extend;
14793 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
14794 op = mips16_immed_operands;
14795 while (op->type != type)
14798 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14809 val = resolve_symbol_value (fragp->fr_symbol);
14814 addr = fragp->fr_address + fragp->fr_fix;
14816 /* The rules for the base address of a PC relative reloc are
14817 complicated; see mips16_extended_frag. */
14818 if (type == 'p' || type == 'q')
14823 /* Ignore the low bit in the target, since it will be
14824 set for a text label. */
14825 if ((val & 1) != 0)
14828 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
14830 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
14833 addr &= ~ (addressT) ((1 << op->shift) - 1);
14836 /* Make sure the section winds up with the alignment we have
14839 record_alignment (asec, op->shift);
14843 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
14844 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
14845 as_warn_where (fragp->fr_file, fragp->fr_line,
14846 _("extended instruction in delay slot"));
14848 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
14850 if (target_big_endian)
14851 insn = bfd_getb16 (buf);
14853 insn = bfd_getl16 (buf);
14855 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
14856 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
14857 small, ext, &insn, &use_extend, &extend);
14861 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
14862 fragp->fr_fix += 2;
14866 md_number_to_chars ((char *) buf, insn, 2);
14867 fragp->fr_fix += 2;
14875 first = RELAX_FIRST (fragp->fr_subtype);
14876 second = RELAX_SECOND (fragp->fr_subtype);
14877 fixp = (fixS *) fragp->fr_opcode;
14879 /* Possibly emit a warning if we've chosen the longer option. */
14880 if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0)
14881 == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0))
14883 const char *msg = macro_warning (fragp->fr_subtype);
14885 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
14888 /* Go through all the fixups for the first sequence. Disable them
14889 (by marking them as done) if we're going to use the second
14890 sequence instead. */
14892 && fixp->fx_frag == fragp
14893 && fixp->fx_where < fragp->fr_fix - second)
14895 if (fragp->fr_subtype & RELAX_USE_SECOND)
14897 fixp = fixp->fx_next;
14900 /* Go through the fixups for the second sequence. Disable them if
14901 we're going to use the first sequence, otherwise adjust their
14902 addresses to account for the relaxation. */
14903 while (fixp && fixp->fx_frag == fragp)
14905 if (fragp->fr_subtype & RELAX_USE_SECOND)
14906 fixp->fx_where -= first;
14909 fixp = fixp->fx_next;
14912 /* Now modify the frag contents. */
14913 if (fragp->fr_subtype & RELAX_USE_SECOND)
14917 start = fragp->fr_literal + fragp->fr_fix - first - second;
14918 memmove (start, start + first, second);
14919 fragp->fr_fix -= first;
14922 fragp->fr_fix -= second;
14928 /* This function is called after the relocs have been generated.
14929 We've been storing mips16 text labels as odd. Here we convert them
14930 back to even for the convenience of the debugger. */
14933 mips_frob_file_after_relocs (void)
14936 unsigned int count, i;
14941 syms = bfd_get_outsymbols (stdoutput);
14942 count = bfd_get_symcount (stdoutput);
14943 for (i = 0; i < count; i++, syms++)
14945 if (ELF_ST_IS_MIPS16 (elf_symbol (*syms)->internal_elf_sym.st_other)
14946 && ((*syms)->value & 1) != 0)
14948 (*syms)->value &= ~1;
14949 /* If the symbol has an odd size, it was probably computed
14950 incorrectly, so adjust that as well. */
14951 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
14952 ++elf_symbol (*syms)->internal_elf_sym.st_size;
14959 /* This function is called whenever a label is defined, including fake
14960 labels instantiated off the dot special symbol. It is used when
14961 handling branch delays; if a branch has a label, we assume we cannot
14962 move it. This also bumps the value of the symbol by 1 in compressed
14966 mips_record_label (symbolS *sym)
14968 segment_info_type *si = seg_info (now_seg);
14969 struct insn_label_list *l;
14971 if (free_insn_labels == NULL)
14972 l = (struct insn_label_list *) xmalloc (sizeof *l);
14975 l = free_insn_labels;
14976 free_insn_labels = l->next;
14980 l->next = si->label_list;
14981 si->label_list = l;
14984 /* This function is called as tc_frob_label() whenever a label is defined
14985 and adds a DWARF-2 record we only want for true labels. */
14988 mips_define_label (symbolS *sym)
14990 mips_record_label (sym);
14992 dwarf2_emit_label (sym);
14996 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14998 /* Some special processing for a MIPS ELF file. */
15001 mips_elf_final_processing (void)
15003 /* Write out the register information. */
15004 if (mips_abi != N64_ABI)
15008 s.ri_gprmask = mips_gprmask;
15009 s.ri_cprmask[0] = mips_cprmask[0];
15010 s.ri_cprmask[1] = mips_cprmask[1];
15011 s.ri_cprmask[2] = mips_cprmask[2];
15012 s.ri_cprmask[3] = mips_cprmask[3];
15013 /* The gp_value field is set by the MIPS ELF backend. */
15015 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
15016 ((Elf32_External_RegInfo *)
15017 mips_regmask_frag));
15021 Elf64_Internal_RegInfo s;
15023 s.ri_gprmask = mips_gprmask;
15025 s.ri_cprmask[0] = mips_cprmask[0];
15026 s.ri_cprmask[1] = mips_cprmask[1];
15027 s.ri_cprmask[2] = mips_cprmask[2];
15028 s.ri_cprmask[3] = mips_cprmask[3];
15029 /* The gp_value field is set by the MIPS ELF backend. */
15031 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
15032 ((Elf64_External_RegInfo *)
15033 mips_regmask_frag));
15036 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
15037 sort of BFD interface for this. */
15038 if (mips_any_noreorder)
15039 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
15040 if (mips_pic != NO_PIC)
15042 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
15043 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
15046 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
15048 /* Set MIPS ELF flags for ASEs. */
15049 /* We may need to define a new flag for DSP ASE, and set this flag when
15050 file_ase_dsp is true. */
15051 /* Same for DSP R2. */
15052 /* We may need to define a new flag for MT ASE, and set this flag when
15053 file_ase_mt is true. */
15054 if (file_ase_mips16)
15055 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
15056 #if 0 /* XXX FIXME */
15057 if (file_ase_mips3d)
15058 elf_elfheader (stdoutput)->e_flags |= ???;
15061 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
15063 /* Set the MIPS ELF ABI flags. */
15064 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
15065 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
15066 else if (mips_abi == O64_ABI)
15067 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
15068 else if (mips_abi == EABI_ABI)
15070 if (!file_mips_gp32)
15071 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
15073 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
15075 else if (mips_abi == N32_ABI)
15076 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
15078 /* Nothing to do for N64_ABI. */
15080 if (mips_32bitmode)
15081 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
15083 #if 0 /* XXX FIXME */
15084 /* 32 bit code with 64 bit FP registers. */
15085 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
15086 elf_elfheader (stdoutput)->e_flags |= ???;
15090 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
15092 typedef struct proc {
15094 symbolS *func_end_sym;
15095 unsigned long reg_mask;
15096 unsigned long reg_offset;
15097 unsigned long fpreg_mask;
15098 unsigned long fpreg_offset;
15099 unsigned long frame_offset;
15100 unsigned long frame_reg;
15101 unsigned long pc_reg;
15104 static procS cur_proc;
15105 static procS *cur_proc_ptr;
15106 static int numprocs;
15108 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal
15112 mips_nop_opcode (void)
15114 return seg_info (now_seg)->tc_segment_info_data.mips16;
15117 /* Fill in an rs_align_code fragment. This only needs to do something
15118 for MIPS16 code, where 0 is not a nop. */
15121 mips_handle_align (fragS *fragp)
15124 int bytes, size, excess;
15127 if (fragp->fr_type != rs_align_code)
15130 p = fragp->fr_literal + fragp->fr_fix;
15133 opcode = mips16_nop_insn.insn_opcode;
15138 opcode = nop_insn.insn_opcode;
15142 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
15143 excess = bytes % size;
15146 /* If we're not inserting a whole number of instructions,
15147 pad the end of the fixed part of the frag with zeros. */
15148 memset (p, 0, excess);
15150 fragp->fr_fix += excess;
15153 md_number_to_chars (p, opcode, size);
15154 fragp->fr_var = size;
15158 md_obj_begin (void)
15165 /* Check for premature end, nesting errors, etc. */
15167 as_warn (_("missing .end at end of assembly"));
15176 if (*input_line_pointer == '-')
15178 ++input_line_pointer;
15181 if (!ISDIGIT (*input_line_pointer))
15182 as_bad (_("expected simple number"));
15183 if (input_line_pointer[0] == '0')
15185 if (input_line_pointer[1] == 'x')
15187 input_line_pointer += 2;
15188 while (ISXDIGIT (*input_line_pointer))
15191 val |= hex_value (*input_line_pointer++);
15193 return negative ? -val : val;
15197 ++input_line_pointer;
15198 while (ISDIGIT (*input_line_pointer))
15201 val |= *input_line_pointer++ - '0';
15203 return negative ? -val : val;
15206 if (!ISDIGIT (*input_line_pointer))
15208 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
15209 *input_line_pointer, *input_line_pointer);
15210 as_warn (_("invalid number"));
15213 while (ISDIGIT (*input_line_pointer))
15216 val += *input_line_pointer++ - '0';
15218 return negative ? -val : val;
15221 /* The .file directive; just like the usual .file directive, but there
15222 is an initial number which is the ECOFF file index. In the non-ECOFF
15223 case .file implies DWARF-2. */
15226 s_mips_file (int x ATTRIBUTE_UNUSED)
15228 static int first_file_directive = 0;
15230 if (ECOFF_DEBUGGING)
15239 filename = dwarf2_directive_file (0);
15241 /* Versions of GCC up to 3.1 start files with a ".file"
15242 directive even for stabs output. Make sure that this
15243 ".file" is handled. Note that you need a version of GCC
15244 after 3.1 in order to support DWARF-2 on MIPS. */
15245 if (filename != NULL && ! first_file_directive)
15247 (void) new_logical_line (filename, -1);
15248 s_app_file_string (filename, 0);
15250 first_file_directive = 1;
15254 /* The .loc directive, implying DWARF-2. */
15257 s_mips_loc (int x ATTRIBUTE_UNUSED)
15259 if (!ECOFF_DEBUGGING)
15260 dwarf2_directive_loc (0);
15263 /* The .end directive. */
15266 s_mips_end (int x ATTRIBUTE_UNUSED)
15270 /* Following functions need their own .frame and .cprestore directives. */
15271 mips_frame_reg_valid = 0;
15272 mips_cprestore_valid = 0;
15274 if (!is_end_of_line[(unsigned char) *input_line_pointer])
15277 demand_empty_rest_of_line ();
15282 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
15283 as_warn (_(".end not in text section"));
15287 as_warn (_(".end directive without a preceding .ent directive."));
15288 demand_empty_rest_of_line ();
15294 gas_assert (S_GET_NAME (p));
15295 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
15296 as_warn (_(".end symbol does not match .ent symbol."));
15298 if (debug_type == DEBUG_STABS)
15299 stabs_generate_asm_endfunc (S_GET_NAME (p),
15303 as_warn (_(".end directive missing or unknown symbol"));
15306 /* Create an expression to calculate the size of the function. */
15307 if (p && cur_proc_ptr)
15309 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
15310 expressionS *exp = xmalloc (sizeof (expressionS));
15313 exp->X_op = O_subtract;
15314 exp->X_add_symbol = symbol_temp_new_now ();
15315 exp->X_op_symbol = p;
15316 exp->X_add_number = 0;
15318 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
15321 /* Generate a .pdr section. */
15322 if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr)
15324 segT saved_seg = now_seg;
15325 subsegT saved_subseg = now_subseg;
15329 #ifdef md_flush_pending_output
15330 md_flush_pending_output ();
15333 gas_assert (pdr_seg);
15334 subseg_set (pdr_seg, 0);
15336 /* Write the symbol. */
15337 exp.X_op = O_symbol;
15338 exp.X_add_symbol = p;
15339 exp.X_add_number = 0;
15340 emit_expr (&exp, 4);
15342 fragp = frag_more (7 * 4);
15344 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
15345 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
15346 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
15347 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
15348 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
15349 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
15350 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
15352 subseg_set (saved_seg, saved_subseg);
15354 #endif /* OBJ_ELF */
15356 cur_proc_ptr = NULL;
15359 /* The .aent and .ent directives. */
15362 s_mips_ent (int aent)
15366 symbolP = get_symbol ();
15367 if (*input_line_pointer == ',')
15368 ++input_line_pointer;
15369 SKIP_WHITESPACE ();
15370 if (ISDIGIT (*input_line_pointer)
15371 || *input_line_pointer == '-')
15374 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
15375 as_warn (_(".ent or .aent not in text section."));
15377 if (!aent && cur_proc_ptr)
15378 as_warn (_("missing .end"));
15382 /* This function needs its own .frame and .cprestore directives. */
15383 mips_frame_reg_valid = 0;
15384 mips_cprestore_valid = 0;
15386 cur_proc_ptr = &cur_proc;
15387 memset (cur_proc_ptr, '\0', sizeof (procS));
15389 cur_proc_ptr->func_sym = symbolP;
15393 if (debug_type == DEBUG_STABS)
15394 stabs_generate_asm_func (S_GET_NAME (symbolP),
15395 S_GET_NAME (symbolP));
15398 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
15400 demand_empty_rest_of_line ();
15403 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
15404 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
15405 s_mips_frame is used so that we can set the PDR information correctly.
15406 We can't use the ecoff routines because they make reference to the ecoff
15407 symbol table (in the mdebug section). */
15410 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
15413 if (IS_ELF && !ECOFF_DEBUGGING)
15417 if (cur_proc_ptr == (procS *) NULL)
15419 as_warn (_(".frame outside of .ent"));
15420 demand_empty_rest_of_line ();
15424 cur_proc_ptr->frame_reg = tc_get_register (1);
15426 SKIP_WHITESPACE ();
15427 if (*input_line_pointer++ != ','
15428 || get_absolute_expression_and_terminator (&val) != ',')
15430 as_warn (_("Bad .frame directive"));
15431 --input_line_pointer;
15432 demand_empty_rest_of_line ();
15436 cur_proc_ptr->frame_offset = val;
15437 cur_proc_ptr->pc_reg = tc_get_register (0);
15439 demand_empty_rest_of_line ();
15442 #endif /* OBJ_ELF */
15446 /* The .fmask and .mask directives. If the mdebug section is present
15447 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
15448 embedded targets, s_mips_mask is used so that we can set the PDR
15449 information correctly. We can't use the ecoff routines because they
15450 make reference to the ecoff symbol table (in the mdebug section). */
15453 s_mips_mask (int reg_type)
15456 if (IS_ELF && !ECOFF_DEBUGGING)
15460 if (cur_proc_ptr == (procS *) NULL)
15462 as_warn (_(".mask/.fmask outside of .ent"));
15463 demand_empty_rest_of_line ();
15467 if (get_absolute_expression_and_terminator (&mask) != ',')
15469 as_warn (_("Bad .mask/.fmask directive"));
15470 --input_line_pointer;
15471 demand_empty_rest_of_line ();
15475 off = get_absolute_expression ();
15477 if (reg_type == 'F')
15479 cur_proc_ptr->fpreg_mask = mask;
15480 cur_proc_ptr->fpreg_offset = off;
15484 cur_proc_ptr->reg_mask = mask;
15485 cur_proc_ptr->reg_offset = off;
15488 demand_empty_rest_of_line ();
15491 #endif /* OBJ_ELF */
15492 s_ignore (reg_type);
15495 /* A table describing all the processors gas knows about. Names are
15496 matched in the order listed.
15498 To ease comparison, please keep this table in the same order as
15499 gcc's mips_cpu_info_table[]. */
15500 static const struct mips_cpu_info mips_cpu_info_table[] =
15502 /* Entries for generic ISAs */
15503 { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 },
15504 { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 },
15505 { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 },
15506 { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 },
15507 { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 },
15508 { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 },
15509 { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 },
15510 { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
15511 { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
15514 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
15515 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
15516 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
15519 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
15522 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
15523 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
15524 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
15525 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
15526 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
15527 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
15528 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
15529 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
15530 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
15531 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
15532 { "orion", 0, ISA_MIPS3, CPU_R4600 },
15533 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
15534 /* ST Microelectronics Loongson 2E and 2F cores */
15535 { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E },
15536 { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F },
15539 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
15540 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
15541 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
15542 { "r14000", 0, ISA_MIPS4, CPU_R14000 },
15543 { "r16000", 0, ISA_MIPS4, CPU_R16000 },
15544 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
15545 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
15546 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
15547 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
15548 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
15549 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
15550 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
15551 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
15552 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
15553 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
15556 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
15557 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
15558 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
15559 { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
15561 /* MIPS 32 Release 2 */
15562 { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15563 { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15564 { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15565 { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
15566 { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15567 { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15568 { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15569 { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15570 { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15571 { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15572 /* Deprecated forms of the above. */
15573 { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15574 { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15575 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
15576 { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15577 { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15578 { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15579 { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15580 /* Deprecated forms of the above. */
15581 { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15582 { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15583 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
15584 { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15585 ISA_MIPS32R2, CPU_MIPS32R2 },
15586 { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15587 ISA_MIPS32R2, CPU_MIPS32R2 },
15588 { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15589 ISA_MIPS32R2, CPU_MIPS32R2 },
15590 { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15591 ISA_MIPS32R2, CPU_MIPS32R2 },
15592 /* Deprecated forms of the above. */
15593 { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15594 ISA_MIPS32R2, CPU_MIPS32R2 },
15595 { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15596 ISA_MIPS32R2, CPU_MIPS32R2 },
15597 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
15598 { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15599 ISA_MIPS32R2, CPU_MIPS32R2 },
15600 { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15601 ISA_MIPS32R2, CPU_MIPS32R2 },
15602 { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15603 ISA_MIPS32R2, CPU_MIPS32R2 },
15604 { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15605 ISA_MIPS32R2, CPU_MIPS32R2 },
15606 { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15607 ISA_MIPS32R2, CPU_MIPS32R2 },
15608 /* Deprecated forms of the above. */
15609 { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15610 ISA_MIPS32R2, CPU_MIPS32R2 },
15611 { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15612 ISA_MIPS32R2, CPU_MIPS32R2 },
15613 /* 1004K cores are multiprocessor versions of the 34K. */
15614 { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15615 ISA_MIPS32R2, CPU_MIPS32R2 },
15616 { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15617 ISA_MIPS32R2, CPU_MIPS32R2 },
15618 { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15619 ISA_MIPS32R2, CPU_MIPS32R2 },
15620 { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15621 ISA_MIPS32R2, CPU_MIPS32R2 },
15624 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
15625 { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
15626 { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
15627 { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
15629 /* Broadcom SB-1 CPU core */
15630 { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
15631 ISA_MIPS64, CPU_SB1 },
15632 /* Broadcom SB-1A CPU core */
15633 { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
15634 ISA_MIPS64, CPU_SB1 },
15636 { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A },
15638 /* MIPS 64 Release 2 */
15640 /* Cavium Networks Octeon CPU core */
15641 { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
15644 { "xlr", 0, ISA_MIPS64, CPU_XLR },
15651 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
15652 with a final "000" replaced by "k". Ignore case.
15654 Note: this function is shared between GCC and GAS. */
15657 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
15659 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
15660 given++, canonical++;
15662 return ((*given == 0 && *canonical == 0)
15663 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
15667 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
15668 CPU name. We've traditionally allowed a lot of variation here.
15670 Note: this function is shared between GCC and GAS. */
15673 mips_matching_cpu_name_p (const char *canonical, const char *given)
15675 /* First see if the name matches exactly, or with a final "000"
15676 turned into "k". */
15677 if (mips_strict_matching_cpu_name_p (canonical, given))
15680 /* If not, try comparing based on numerical designation alone.
15681 See if GIVEN is an unadorned number, or 'r' followed by a number. */
15682 if (TOLOWER (*given) == 'r')
15684 if (!ISDIGIT (*given))
15687 /* Skip over some well-known prefixes in the canonical name,
15688 hoping to find a number there too. */
15689 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
15691 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
15693 else if (TOLOWER (canonical[0]) == 'r')
15696 return mips_strict_matching_cpu_name_p (canonical, given);
15700 /* Parse an option that takes the name of a processor as its argument.
15701 OPTION is the name of the option and CPU_STRING is the argument.
15702 Return the corresponding processor enumeration if the CPU_STRING is
15703 recognized, otherwise report an error and return null.
15705 A similar function exists in GCC. */
15707 static const struct mips_cpu_info *
15708 mips_parse_cpu (const char *option, const char *cpu_string)
15710 const struct mips_cpu_info *p;
15712 /* 'from-abi' selects the most compatible architecture for the given
15713 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
15714 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15715 version. Look first at the -mgp options, if given, otherwise base
15716 the choice on MIPS_DEFAULT_64BIT.
15718 Treat NO_ABI like the EABIs. One reason to do this is that the
15719 plain 'mips' and 'mips64' configs have 'from-abi' as their default
15720 architecture. This code picks MIPS I for 'mips' and MIPS III for
15721 'mips64', just as we did in the days before 'from-abi'. */
15722 if (strcasecmp (cpu_string, "from-abi") == 0)
15724 if (ABI_NEEDS_32BIT_REGS (mips_abi))
15725 return mips_cpu_info_from_isa (ISA_MIPS1);
15727 if (ABI_NEEDS_64BIT_REGS (mips_abi))
15728 return mips_cpu_info_from_isa (ISA_MIPS3);
15730 if (file_mips_gp32 >= 0)
15731 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
15733 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
15738 /* 'default' has traditionally been a no-op. Probably not very useful. */
15739 if (strcasecmp (cpu_string, "default") == 0)
15742 for (p = mips_cpu_info_table; p->name != 0; p++)
15743 if (mips_matching_cpu_name_p (p->name, cpu_string))
15746 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
15750 /* Return the canonical processor information for ISA (a member of the
15751 ISA_MIPS* enumeration). */
15753 static const struct mips_cpu_info *
15754 mips_cpu_info_from_isa (int isa)
15758 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15759 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
15760 && isa == mips_cpu_info_table[i].isa)
15761 return (&mips_cpu_info_table[i]);
15766 static const struct mips_cpu_info *
15767 mips_cpu_info_from_arch (int arch)
15771 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15772 if (arch == mips_cpu_info_table[i].cpu)
15773 return (&mips_cpu_info_table[i]);
15779 show (FILE *stream, const char *string, int *col_p, int *first_p)
15783 fprintf (stream, "%24s", "");
15788 fprintf (stream, ", ");
15792 if (*col_p + strlen (string) > 72)
15794 fprintf (stream, "\n%24s", "");
15798 fprintf (stream, "%s", string);
15799 *col_p += strlen (string);
15805 md_show_usage (FILE *stream)
15810 fprintf (stream, _("\
15812 -EB generate big endian output\n\
15813 -EL generate little endian output\n\
15814 -g, -g2 do not remove unneeded NOPs or swap branches\n\
15815 -G NUM allow referencing objects up to NUM bytes\n\
15816 implicitly with the gp register [default 8]\n"));
15817 fprintf (stream, _("\
15818 -mips1 generate MIPS ISA I instructions\n\
15819 -mips2 generate MIPS ISA II instructions\n\
15820 -mips3 generate MIPS ISA III instructions\n\
15821 -mips4 generate MIPS ISA IV instructions\n\
15822 -mips5 generate MIPS ISA V instructions\n\
15823 -mips32 generate MIPS32 ISA instructions\n\
15824 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
15825 -mips64 generate MIPS64 ISA instructions\n\
15826 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
15827 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
15831 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15832 show (stream, mips_cpu_info_table[i].name, &column, &first);
15833 show (stream, "from-abi", &column, &first);
15834 fputc ('\n', stream);
15836 fprintf (stream, _("\
15837 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
15838 -no-mCPU don't generate code specific to CPU.\n\
15839 For -mCPU and -no-mCPU, CPU must be one of:\n"));
15843 show (stream, "3900", &column, &first);
15844 show (stream, "4010", &column, &first);
15845 show (stream, "4100", &column, &first);
15846 show (stream, "4650", &column, &first);
15847 fputc ('\n', stream);
15849 fprintf (stream, _("\
15850 -mips16 generate mips16 instructions\n\
15851 -no-mips16 do not generate mips16 instructions\n"));
15852 fprintf (stream, _("\
15853 -msmartmips generate smartmips instructions\n\
15854 -mno-smartmips do not generate smartmips instructions\n"));
15855 fprintf (stream, _("\
15856 -mdsp generate DSP instructions\n\
15857 -mno-dsp do not generate DSP instructions\n"));
15858 fprintf (stream, _("\
15859 -mdspr2 generate DSP R2 instructions\n\
15860 -mno-dspr2 do not generate DSP R2 instructions\n"));
15861 fprintf (stream, _("\
15862 -mmt generate MT instructions\n\
15863 -mno-mt do not generate MT instructions\n"));
15864 fprintf (stream, _("\
15865 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
15866 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
15867 -mfix-vr4120 work around certain VR4120 errata\n\
15868 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
15869 -mfix-24k insert a nop after ERET and DERET instructions\n\
15870 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
15871 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
15872 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
15873 -msym32 assume all symbols have 32-bit values\n\
15874 -O0 remove unneeded NOPs, do not swap branches\n\
15875 -O remove unneeded NOPs and swap branches\n\
15876 --trap, --no-break trap exception on div by 0 and mult overflow\n\
15877 --break, --no-trap break exception on div by 0 and mult overflow\n"));
15878 fprintf (stream, _("\
15879 -mhard-float allow floating-point instructions\n\
15880 -msoft-float do not allow floating-point instructions\n\
15881 -msingle-float only allow 32-bit floating-point operations\n\
15882 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
15883 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
15886 fprintf (stream, _("\
15887 -KPIC, -call_shared generate SVR4 position independent code\n\
15888 -call_nonpic generate non-PIC code that can operate with DSOs\n\
15889 -mvxworks-pic generate VxWorks position independent code\n\
15890 -non_shared do not generate code that can operate with DSOs\n\
15891 -xgot assume a 32 bit GOT\n\
15892 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
15893 -mshared, -mno-shared disable/enable .cpload optimization for\n\
15894 position dependent (non shared) code\n\
15895 -mabi=ABI create ABI conformant object file for:\n"));
15899 show (stream, "32", &column, &first);
15900 show (stream, "o64", &column, &first);
15901 show (stream, "n32", &column, &first);
15902 show (stream, "64", &column, &first);
15903 show (stream, "eabi", &column, &first);
15905 fputc ('\n', stream);
15907 fprintf (stream, _("\
15908 -32 create o32 ABI object file (default)\n\
15909 -n32 create n32 ABI object file\n\
15910 -64 create 64 ABI object file\n"));
15916 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
15918 if (HAVE_64BIT_SYMBOLS)
15919 return dwarf2_format_64bit_irix;
15921 return dwarf2_format_32bit;
15926 mips_dwarf2_addr_size (void)
15928 if (HAVE_64BIT_OBJECTS)
15934 /* Standard calling conventions leave the CFA at SP on entry. */
15936 mips_cfi_frame_initial_instructions (void)
15938 cfi_add_CFA_def_cfa_register (SP);
15942 tc_mips_regname_to_dw2regnum (char *regname)
15944 unsigned int regnum = -1;
15947 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))