1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 #define AT mips_opts.at
107 /* Allow override of standard little-endian ECOFF format. */
109 #ifndef ECOFF_LITTLE_FORMAT
110 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
113 extern int target_big_endian;
115 /* The name of the readonly data section. */
116 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
124 /* Information about an instruction, including its format, operands
128 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
129 const struct mips_opcode *insn_mo;
131 /* True if this is a mips16 instruction and if we want the extended
133 bfd_boolean use_extend;
135 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
136 unsigned short extend;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. */
140 unsigned long insn_opcode;
142 /* The frag that contains the instruction. */
145 /* The offset into FRAG of the first instruction byte. */
148 /* The relocs associated with the instruction, if any. */
151 /* True if this entry cannot be moved from its current position. */
152 unsigned int fixed_p : 1;
154 /* True if this instruction occurred in a .set noreorder block. */
155 unsigned int noreorder_p : 1;
157 /* True for mips16 instructions that jump to an absolute address. */
158 unsigned int mips16_absolute_jump_p : 1;
160 /* True if this instruction is complete. */
161 unsigned int complete_p : 1;
164 /* The ABI to use. */
175 /* MIPS ABI we are using for this output file. */
176 static enum mips_abi_level mips_abi = NO_ABI;
178 /* Whether or not we have code that can call pic code. */
179 int mips_abicalls = FALSE;
181 /* Whether or not we have code which can be put into a shared
183 static bfd_boolean mips_in_shared = TRUE;
185 /* This is the set of options which may be modified by the .set
186 pseudo-op. We use a struct so that .set push and .set pop are more
189 struct mips_set_options
191 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
192 if it has not been initialized. Changed by `.set mipsN', and the
193 -mipsN command line option, and the default CPU. */
195 /* Enabled Application Specific Extensions (ASEs). These are set to -1
196 if they have not been initialized. Changed by `.set <asename>', by
197 command line options, and based on the default architecture. */
204 /* Whether we are assembling for the mips16 processor. 0 if we are
205 not, 1 if we are, and -1 if the value has not been initialized.
206 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
207 -nomips16 command line options, and the default CPU. */
209 /* Non-zero if we should not reorder instructions. Changed by `.set
210 reorder' and `.set noreorder'. */
212 /* Non-zero if we should not permit the register designated "assembler
213 temporary" to be used in instructions. The value is the register
214 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
215 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
217 /* Non-zero if we should warn when a macro instruction expands into
218 more than one machine instruction. Changed by `.set nomacro' and
220 int warn_about_macros;
221 /* Non-zero if we should not move instructions. Changed by `.set
222 move', `.set volatile', `.set nomove', and `.set novolatile'. */
224 /* Non-zero if we should not optimize branches by moving the target
225 of the branch into the delay slot. Actually, we don't perform
226 this optimization anyhow. Changed by `.set bopt' and `.set
229 /* Non-zero if we should not autoextend mips16 instructions.
230 Changed by `.set autoextend' and `.set noautoextend'. */
232 /* Restrict general purpose registers and floating point registers
233 to 32 bit. This is initially determined when -mgp32 or -mfp32
234 is passed but can changed if the assembler code uses .set mipsN. */
237 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
238 command line option, and the default CPU. */
240 /* True if ".set sym32" is in effect. */
242 /* True if floating-point operations are not allowed. Changed by .set
243 softfloat or .set hardfloat, by command line options -msoft-float or
244 -mhard-float. The default is false. */
245 bfd_boolean soft_float;
247 /* True if only single-precision floating-point operations are allowed.
248 Changed by .set singlefloat or .set doublefloat, command-line options
249 -msingle-float or -mdouble-float. The default is false. */
250 bfd_boolean single_float;
253 /* This is the struct we use to hold the current set of options. Note
254 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
255 -1 to indicate that they have not been initialized. */
257 /* True if -mgp32 was passed. */
258 static int file_mips_gp32 = -1;
260 /* True if -mfp32 was passed. */
261 static int file_mips_fp32 = -1;
263 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
264 static int file_mips_soft_float = 0;
266 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
267 static int file_mips_single_float = 0;
269 static struct mips_set_options mips_opts =
271 /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
272 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
273 /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG,
274 /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
275 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN,
276 /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE
279 /* These variables are filled in with the masks of registers used.
280 The object format code reads them and puts them in the appropriate
282 unsigned long mips_gprmask;
283 unsigned long mips_cprmask[4];
285 /* MIPS ISA we are using for this output file. */
286 static int file_mips_isa = ISA_UNKNOWN;
288 /* True if any MIPS16 code was produced. */
289 static int file_ase_mips16;
291 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
292 || mips_opts.isa == ISA_MIPS32R2 \
293 || mips_opts.isa == ISA_MIPS64 \
294 || mips_opts.isa == ISA_MIPS64R2)
296 /* True if we want to create R_MIPS_JALR for jalr $25. */
298 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
300 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
301 because there's no place for any addend, the only acceptable
302 expression is a bare symbol. */
303 #define MIPS_JALR_HINT_P(EXPR) \
304 (!HAVE_IN_PLACE_ADDENDS \
305 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
308 /* True if -mips3d was passed or implied by arguments passed on the
309 command line (e.g., by -march). */
310 static int file_ase_mips3d;
312 /* True if -mdmx was passed or implied by arguments passed on the
313 command line (e.g., by -march). */
314 static int file_ase_mdmx;
316 /* True if -msmartmips was passed or implied by arguments passed on the
317 command line (e.g., by -march). */
318 static int file_ase_smartmips;
320 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
321 || mips_opts.isa == ISA_MIPS32R2)
323 /* True if -mdsp was passed or implied by arguments passed on the
324 command line (e.g., by -march). */
325 static int file_ase_dsp;
327 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
328 || mips_opts.isa == ISA_MIPS64R2)
330 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
332 /* True if -mdspr2 was passed or implied by arguments passed on the
333 command line (e.g., by -march). */
334 static int file_ase_dspr2;
336 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
337 || mips_opts.isa == ISA_MIPS64R2)
339 /* True if -mmt was passed or implied by arguments passed on the
340 command line (e.g., by -march). */
341 static int file_ase_mt;
343 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
344 || mips_opts.isa == ISA_MIPS64R2)
346 /* The argument of the -march= flag. The architecture we are assembling. */
347 static int file_mips_arch = CPU_UNKNOWN;
348 static const char *mips_arch_string;
350 /* The argument of the -mtune= flag. The architecture for which we
352 static int mips_tune = CPU_UNKNOWN;
353 static const char *mips_tune_string;
355 /* True when generating 32-bit code for a 64-bit processor. */
356 static int mips_32bitmode = 0;
358 /* True if the given ABI requires 32-bit registers. */
359 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
361 /* Likewise 64-bit registers. */
362 #define ABI_NEEDS_64BIT_REGS(ABI) \
364 || (ABI) == N64_ABI \
367 /* Return true if ISA supports 64 bit wide gp registers. */
368 #define ISA_HAS_64BIT_REGS(ISA) \
369 ((ISA) == ISA_MIPS3 \
370 || (ISA) == ISA_MIPS4 \
371 || (ISA) == ISA_MIPS5 \
372 || (ISA) == ISA_MIPS64 \
373 || (ISA) == ISA_MIPS64R2)
375 /* Return true if ISA supports 64 bit wide float registers. */
376 #define ISA_HAS_64BIT_FPRS(ISA) \
377 ((ISA) == ISA_MIPS3 \
378 || (ISA) == ISA_MIPS4 \
379 || (ISA) == ISA_MIPS5 \
380 || (ISA) == ISA_MIPS32R2 \
381 || (ISA) == ISA_MIPS64 \
382 || (ISA) == ISA_MIPS64R2)
384 /* Return true if ISA supports 64-bit right rotate (dror et al.)
386 #define ISA_HAS_DROR(ISA) \
387 ((ISA) == ISA_MIPS64R2)
389 /* Return true if ISA supports 32-bit right rotate (ror et al.)
391 #define ISA_HAS_ROR(ISA) \
392 ((ISA) == ISA_MIPS32R2 \
393 || (ISA) == ISA_MIPS64R2 \
394 || mips_opts.ase_smartmips)
396 /* Return true if ISA supports single-precision floats in odd registers. */
397 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
398 ((ISA) == ISA_MIPS32 \
399 || (ISA) == ISA_MIPS32R2 \
400 || (ISA) == ISA_MIPS64 \
401 || (ISA) == ISA_MIPS64R2)
403 /* Return true if ISA supports move to/from high part of a 64-bit
404 floating-point register. */
405 #define ISA_HAS_MXHC1(ISA) \
406 ((ISA) == ISA_MIPS32R2 \
407 || (ISA) == ISA_MIPS64R2)
409 #define HAVE_32BIT_GPRS \
410 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
412 #define HAVE_32BIT_FPRS \
413 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
415 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
416 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
418 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
420 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
422 /* True if relocations are stored in-place. */
423 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
425 /* The ABI-derived address size. */
426 #define HAVE_64BIT_ADDRESSES \
427 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
428 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
430 /* The size of symbolic constants (i.e., expressions of the form
431 "SYMBOL" or "SYMBOL + OFFSET"). */
432 #define HAVE_32BIT_SYMBOLS \
433 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
434 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
436 /* Addresses are loaded in different ways, depending on the address size
437 in use. The n32 ABI Documentation also mandates the use of additions
438 with overflow checking, but existing implementations don't follow it. */
439 #define ADDRESS_ADD_INSN \
440 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
442 #define ADDRESS_ADDI_INSN \
443 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
445 #define ADDRESS_LOAD_INSN \
446 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
448 #define ADDRESS_STORE_INSN \
449 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
451 /* Return true if the given CPU supports the MIPS16 ASE. */
452 #define CPU_HAS_MIPS16(cpu) \
453 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
454 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
456 /* True if CPU has a dror instruction. */
457 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
459 /* True if CPU has a ror instruction. */
460 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
462 /* True if CPU has seq/sne and seqi/snei instructions. */
463 #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON)
465 /* True if CPU does not implement the all the coprocessor insns. For these
466 CPUs only those COP insns are accepted that are explicitly marked to be
467 available on the CPU. ISA membership for COP insns is ignored. */
468 #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON)
470 /* True if mflo and mfhi can be immediately followed by instructions
471 which write to the HI and LO registers.
473 According to MIPS specifications, MIPS ISAs I, II, and III need
474 (at least) two instructions between the reads of HI/LO and
475 instructions which write them, and later ISAs do not. Contradicting
476 the MIPS specifications, some MIPS IV processor user manuals (e.g.
477 the UM for the NEC Vr5000) document needing the instructions between
478 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
479 MIPS64 and later ISAs to have the interlocks, plus any specific
480 earlier-ISA CPUs for which CPU documentation declares that the
481 instructions are really interlocked. */
482 #define hilo_interlocks \
483 (mips_opts.isa == ISA_MIPS32 \
484 || mips_opts.isa == ISA_MIPS32R2 \
485 || mips_opts.isa == ISA_MIPS64 \
486 || mips_opts.isa == ISA_MIPS64R2 \
487 || mips_opts.arch == CPU_R4010 \
488 || mips_opts.arch == CPU_R10000 \
489 || mips_opts.arch == CPU_R12000 \
490 || mips_opts.arch == CPU_R14000 \
491 || mips_opts.arch == CPU_R16000 \
492 || mips_opts.arch == CPU_RM7000 \
493 || mips_opts.arch == CPU_VR5500 \
496 /* Whether the processor uses hardware interlocks to protect reads
497 from the GPRs after they are loaded from memory, and thus does not
498 require nops to be inserted. This applies to instructions marked
499 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
501 #define gpr_interlocks \
502 (mips_opts.isa != ISA_MIPS1 \
503 || mips_opts.arch == CPU_R3900)
505 /* Whether the processor uses hardware interlocks to avoid delays
506 required by coprocessor instructions, and thus does not require
507 nops to be inserted. This applies to instructions marked
508 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
509 between instructions marked INSN_WRITE_COND_CODE and ones marked
510 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
511 levels I, II, and III. */
512 /* Itbl support may require additional care here. */
513 #define cop_interlocks \
514 ((mips_opts.isa != ISA_MIPS1 \
515 && mips_opts.isa != ISA_MIPS2 \
516 && mips_opts.isa != ISA_MIPS3) \
517 || mips_opts.arch == CPU_R4300 \
520 /* Whether the processor uses hardware interlocks to protect reads
521 from coprocessor registers after they are loaded from memory, and
522 thus does not require nops to be inserted. This applies to
523 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
524 requires at MIPS ISA level I. */
525 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
527 /* Is this a mfhi or mflo instruction? */
528 #define MF_HILO_INSN(PINFO) \
529 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
531 /* Returns true for a (non floating-point) coprocessor instruction. Reading
532 or writing the condition code is only possible on the coprocessors and
533 these insns are not marked with INSN_COP. Thus for these insns use the
534 condition-code flags. */
535 #define COP_INSN(PINFO) \
536 (PINFO != INSN_MACRO \
537 && ((PINFO) & (FP_S | FP_D)) == 0 \
538 && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
540 /* MIPS PIC level. */
542 enum mips_pic_level mips_pic;
544 /* 1 if we should generate 32 bit offsets from the $gp register in
545 SVR4_PIC mode. Currently has no meaning in other modes. */
546 static int mips_big_got = 0;
548 /* 1 if trap instructions should used for overflow rather than break
550 static int mips_trap = 0;
552 /* 1 if double width floating point constants should not be constructed
553 by assembling two single width halves into two single width floating
554 point registers which just happen to alias the double width destination
555 register. On some architectures this aliasing can be disabled by a bit
556 in the status register, and the setting of this bit cannot be determined
557 automatically at assemble time. */
558 static int mips_disable_float_construction;
560 /* Non-zero if any .set noreorder directives were used. */
562 static int mips_any_noreorder;
564 /* Non-zero if nops should be inserted when the register referenced in
565 an mfhi/mflo instruction is read in the next two instructions. */
566 static int mips_7000_hilo_fix;
568 /* The size of objects in the small data section. */
569 static unsigned int g_switch_value = 8;
570 /* Whether the -G option was used. */
571 static int g_switch_seen = 0;
576 /* If we can determine in advance that GP optimization won't be
577 possible, we can skip the relaxation stuff that tries to produce
578 GP-relative references. This makes delay slot optimization work
581 This function can only provide a guess, but it seems to work for
582 gcc output. It needs to guess right for gcc, otherwise gcc
583 will put what it thinks is a GP-relative instruction in a branch
586 I don't know if a fix is needed for the SVR4_PIC mode. I've only
587 fixed it for the non-PIC mode. KR 95/04/07 */
588 static int nopic_need_relax (symbolS *, int);
590 /* handle of the OPCODE hash table */
591 static struct hash_control *op_hash = NULL;
593 /* The opcode hash table we use for the mips16. */
594 static struct hash_control *mips16_op_hash = NULL;
596 /* This array holds the chars that always start a comment. If the
597 pre-processor is disabled, these aren't very useful */
598 const char comment_chars[] = "#";
600 /* This array holds the chars that only start a comment at the beginning of
601 a line. If the line seems to have the form '# 123 filename'
602 .line and .file directives will appear in the pre-processed output */
603 /* Note that input_file.c hand checks for '#' at the beginning of the
604 first line of the input file. This is because the compiler outputs
605 #NO_APP at the beginning of its output. */
606 /* Also note that C style comments are always supported. */
607 const char line_comment_chars[] = "#";
609 /* This array holds machine specific line separator characters. */
610 const char line_separator_chars[] = ";";
612 /* Chars that can be used to separate mant from exp in floating point nums */
613 const char EXP_CHARS[] = "eE";
615 /* Chars that mean this number is a floating point constant */
618 const char FLT_CHARS[] = "rRsSfFdDxXpP";
620 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
621 changed in read.c . Ideally it shouldn't have to know about it at all,
622 but nothing is ideal around here.
625 static char *insn_error;
627 static int auto_align = 1;
629 /* When outputting SVR4 PIC code, the assembler needs to know the
630 offset in the stack frame from which to restore the $gp register.
631 This is set by the .cprestore pseudo-op, and saved in this
633 static offsetT mips_cprestore_offset = -1;
635 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
636 more optimizations, it can use a register value instead of a memory-saved
637 offset and even an other register than $gp as global pointer. */
638 static offsetT mips_cpreturn_offset = -1;
639 static int mips_cpreturn_register = -1;
640 static int mips_gp_register = GP;
641 static int mips_gprel_offset = 0;
643 /* Whether mips_cprestore_offset has been set in the current function
644 (or whether it has already been warned about, if not). */
645 static int mips_cprestore_valid = 0;
647 /* This is the register which holds the stack frame, as set by the
648 .frame pseudo-op. This is needed to implement .cprestore. */
649 static int mips_frame_reg = SP;
651 /* Whether mips_frame_reg has been set in the current function
652 (or whether it has already been warned about, if not). */
653 static int mips_frame_reg_valid = 0;
655 /* To output NOP instructions correctly, we need to keep information
656 about the previous two instructions. */
658 /* Whether we are optimizing. The default value of 2 means to remove
659 unneeded NOPs and swap branch instructions when possible. A value
660 of 1 means to not swap branches. A value of 0 means to always
662 static int mips_optimize = 2;
664 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
665 equivalent to seeing no -g option at all. */
666 static int mips_debug = 0;
668 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
669 #define MAX_VR4130_NOPS 4
671 /* The maximum number of NOPs needed to fill delay slots. */
672 #define MAX_DELAY_NOPS 2
674 /* The maximum number of NOPs needed for any purpose. */
677 /* A list of previous instructions, with index 0 being the most recent.
678 We need to look back MAX_NOPS instructions when filling delay slots
679 or working around processor errata. We need to look back one
680 instruction further if we're thinking about using history[0] to
681 fill a branch delay slot. */
682 static struct mips_cl_insn history[1 + MAX_NOPS];
684 /* Nop instructions used by emit_nop. */
685 static struct mips_cl_insn nop_insn, mips16_nop_insn;
687 /* The appropriate nop for the current mode. */
688 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
690 /* If this is set, it points to a frag holding nop instructions which
691 were inserted before the start of a noreorder section. If those
692 nops turn out to be unnecessary, the size of the frag can be
694 static fragS *prev_nop_frag;
696 /* The number of nop instructions we created in prev_nop_frag. */
697 static int prev_nop_frag_holds;
699 /* The number of nop instructions that we know we need in
701 static int prev_nop_frag_required;
703 /* The number of instructions we've seen since prev_nop_frag. */
704 static int prev_nop_frag_since;
706 /* For ECOFF and ELF, relocations against symbols are done in two
707 parts, with a HI relocation and a LO relocation. Each relocation
708 has only 16 bits of space to store an addend. This means that in
709 order for the linker to handle carries correctly, it must be able
710 to locate both the HI and the LO relocation. This means that the
711 relocations must appear in order in the relocation table.
713 In order to implement this, we keep track of each unmatched HI
714 relocation. We then sort them so that they immediately precede the
715 corresponding LO relocation. */
720 struct mips_hi_fixup *next;
723 /* The section this fixup is in. */
727 /* The list of unmatched HI relocs. */
729 static struct mips_hi_fixup *mips_hi_fixup_list;
731 /* The frag containing the last explicit relocation operator.
732 Null if explicit relocations have not been used. */
734 static fragS *prev_reloc_op_frag;
736 /* Map normal MIPS register numbers to mips16 register numbers. */
738 #define X ILLEGAL_REG
739 static const int mips32_to_16_reg_map[] =
741 X, X, 2, 3, 4, 5, 6, 7,
742 X, X, X, X, X, X, X, X,
743 0, 1, X, X, X, X, X, X,
744 X, X, X, X, X, X, X, X
748 /* Map mips16 register numbers to normal MIPS register numbers. */
750 static const unsigned int mips16_to_32_reg_map[] =
752 16, 17, 2, 3, 4, 5, 6, 7
755 /* Classifies the kind of instructions we're interested in when
756 implementing -mfix-vr4120. */
757 enum fix_vr4120_class
765 NUM_FIX_VR4120_CLASSES
768 /* ...likewise -mfix-loongson2f-jump. */
769 static bfd_boolean mips_fix_loongson2f_jump;
771 /* ...likewise -mfix-loongson2f-nop. */
772 static bfd_boolean mips_fix_loongson2f_nop;
774 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
775 static bfd_boolean mips_fix_loongson2f;
777 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
778 there must be at least one other instruction between an instruction
779 of type X and an instruction of type Y. */
780 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
782 /* True if -mfix-vr4120 is in force. */
783 static int mips_fix_vr4120;
785 /* ...likewise -mfix-vr4130. */
786 static int mips_fix_vr4130;
788 /* ...likewise -mfix-24k. */
789 static int mips_fix_24k;
791 /* ...likewise -mfix-cn63xxp1 */
792 static bfd_boolean mips_fix_cn63xxp1;
794 /* We don't relax branches by default, since this causes us to expand
795 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
796 fail to compute the offset before expanding the macro to the most
797 efficient expansion. */
799 static int mips_relax_branch;
801 /* The expansion of many macros depends on the type of symbol that
802 they refer to. For example, when generating position-dependent code,
803 a macro that refers to a symbol may have two different expansions,
804 one which uses GP-relative addresses and one which uses absolute
805 addresses. When generating SVR4-style PIC, a macro may have
806 different expansions for local and global symbols.
808 We handle these situations by generating both sequences and putting
809 them in variant frags. In position-dependent code, the first sequence
810 will be the GP-relative one and the second sequence will be the
811 absolute one. In SVR4 PIC, the first sequence will be for global
812 symbols and the second will be for local symbols.
814 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
815 SECOND are the lengths of the two sequences in bytes. These fields
816 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
817 the subtype has the following flags:
820 Set if it has been decided that we should use the second
821 sequence instead of the first.
824 Set in the first variant frag if the macro's second implementation
825 is longer than its first. This refers to the macro as a whole,
826 not an individual relaxation.
829 Set in the first variant frag if the macro appeared in a .set nomacro
830 block and if one alternative requires a warning but the other does not.
833 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
836 The frag's "opcode" points to the first fixup for relaxable code.
838 Relaxable macros are generated using a sequence such as:
840 relax_start (SYMBOL);
841 ... generate first expansion ...
843 ... generate second expansion ...
846 The code and fixups for the unwanted alternative are discarded
847 by md_convert_frag. */
848 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
850 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
851 #define RELAX_SECOND(X) ((X) & 0xff)
852 #define RELAX_USE_SECOND 0x10000
853 #define RELAX_SECOND_LONGER 0x20000
854 #define RELAX_NOMACRO 0x40000
855 #define RELAX_DELAY_SLOT 0x80000
857 /* Branch without likely bit. If label is out of range, we turn:
859 beq reg1, reg2, label
869 with the following opcode replacements:
876 bltzal <-> bgezal (with jal label instead of j label)
878 Even though keeping the delay slot instruction in the delay slot of
879 the branch would be more efficient, it would be very tricky to do
880 correctly, because we'd have to introduce a variable frag *after*
881 the delay slot instruction, and expand that instead. Let's do it
882 the easy way for now, even if the branch-not-taken case now costs
883 one additional instruction. Out-of-range branches are not supposed
884 to be common, anyway.
886 Branch likely. If label is out of range, we turn:
888 beql reg1, reg2, label
889 delay slot (annulled if branch not taken)
898 delay slot (executed only if branch taken)
901 It would be possible to generate a shorter sequence by losing the
902 likely bit, generating something like:
907 delay slot (executed only if branch taken)
919 bltzall -> bgezal (with jal label instead of j label)
920 bgezall -> bltzal (ditto)
923 but it's not clear that it would actually improve performance. */
924 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
928 | ((toofar) ? 0x20 : 0) \
929 | ((link) ? 0x40 : 0) \
930 | ((likely) ? 0x80 : 0) \
931 | ((uncond) ? 0x100 : 0)))
932 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
933 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
934 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
935 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
936 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
937 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
939 /* For mips16 code, we use an entirely different form of relaxation.
940 mips16 supports two versions of most instructions which take
941 immediate values: a small one which takes some small value, and a
942 larger one which takes a 16 bit value. Since branches also follow
943 this pattern, relaxing these values is required.
945 We can assemble both mips16 and normal MIPS code in a single
946 object. Therefore, we need to support this type of relaxation at
947 the same time that we support the relaxation described above. We
948 use the high bit of the subtype field to distinguish these cases.
950 The information we store for this type of relaxation is the
951 argument code found in the opcode file for this relocation, whether
952 the user explicitly requested a small or extended form, and whether
953 the relocation is in a jump or jal delay slot. That tells us the
954 size of the value, and how it should be stored. We also store
955 whether the fragment is considered to be extended or not. We also
956 store whether this is known to be a branch to a different section,
957 whether we have tried to relax this frag yet, and whether we have
958 ever extended a PC relative fragment because of a shift count. */
959 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
962 | ((small) ? 0x100 : 0) \
963 | ((ext) ? 0x200 : 0) \
964 | ((dslot) ? 0x400 : 0) \
965 | ((jal_dslot) ? 0x800 : 0))
966 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
967 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
968 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
969 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
970 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
971 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
972 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
973 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
974 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
975 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
976 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
977 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
979 /* Is the given value a sign-extended 32-bit value? */
980 #define IS_SEXT_32BIT_NUM(x) \
981 (((x) &~ (offsetT) 0x7fffffff) == 0 \
982 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
984 /* Is the given value a sign-extended 16-bit value? */
985 #define IS_SEXT_16BIT_NUM(x) \
986 (((x) &~ (offsetT) 0x7fff) == 0 \
987 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
989 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
990 #define IS_ZEXT_32BIT_NUM(x) \
991 (((x) &~ (offsetT) 0xffffffff) == 0 \
992 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
994 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
995 VALUE << SHIFT. VALUE is evaluated exactly once. */
996 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
997 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
998 | (((VALUE) & (MASK)) << (SHIFT)))
1000 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1002 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1003 (((STRUCT) >> (SHIFT)) & (MASK))
1005 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1006 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1008 include/opcode/mips.h specifies operand fields using the macros
1009 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1010 with "MIPS16OP" instead of "OP". */
1011 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
1012 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
1013 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1014 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1015 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1017 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1018 #define EXTRACT_OPERAND(FIELD, INSN) \
1019 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
1020 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1021 EXTRACT_BITS ((INSN).insn_opcode, \
1022 MIPS16OP_MASK_##FIELD, \
1023 MIPS16OP_SH_##FIELD)
1025 /* Global variables used when generating relaxable macros. See the
1026 comment above RELAX_ENCODE for more details about how relaxation
1029 /* 0 if we're not emitting a relaxable macro.
1030 1 if we're emitting the first of the two relaxation alternatives.
1031 2 if we're emitting the second alternative. */
1034 /* The first relaxable fixup in the current frag. (In other words,
1035 the first fixup that refers to relaxable code.) */
1038 /* sizes[0] says how many bytes of the first alternative are stored in
1039 the current frag. Likewise sizes[1] for the second alternative. */
1040 unsigned int sizes[2];
1042 /* The symbol on which the choice of sequence depends. */
1046 /* Global variables used to decide whether a macro needs a warning. */
1048 /* True if the macro is in a branch delay slot. */
1049 bfd_boolean delay_slot_p;
1051 /* For relaxable macros, sizes[0] is the length of the first alternative
1052 in bytes and sizes[1] is the length of the second alternative.
1053 For non-relaxable macros, both elements give the length of the
1055 unsigned int sizes[2];
1057 /* The first variant frag for this macro. */
1059 } mips_macro_warning;
1061 /* Prototypes for static functions. */
1063 #define internalError() \
1064 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1066 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1068 static void append_insn
1069 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *);
1070 static void mips_no_prev_insn (void);
1071 static void macro_build (expressionS *, const char *, const char *, ...);
1072 static void mips16_macro_build
1073 (expressionS *, const char *, const char *, va_list *);
1074 static void load_register (int, expressionS *, int);
1075 static void macro_start (void);
1076 static void macro_end (void);
1077 static void macro (struct mips_cl_insn * ip);
1078 static void mips16_macro (struct mips_cl_insn * ip);
1079 static void mips_ip (char *str, struct mips_cl_insn * ip);
1080 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1081 static void mips16_immed
1082 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
1083 unsigned long *, bfd_boolean *, unsigned short *);
1084 static size_t my_getSmallExpression
1085 (expressionS *, bfd_reloc_code_real_type *, char *);
1086 static void my_getExpression (expressionS *, char *);
1087 static void s_align (int);
1088 static void s_change_sec (int);
1089 static void s_change_section (int);
1090 static void s_cons (int);
1091 static void s_float_cons (int);
1092 static void s_mips_globl (int);
1093 static void s_option (int);
1094 static void s_mipsset (int);
1095 static void s_abicalls (int);
1096 static void s_cpload (int);
1097 static void s_cpsetup (int);
1098 static void s_cplocal (int);
1099 static void s_cprestore (int);
1100 static void s_cpreturn (int);
1101 static void s_dtprelword (int);
1102 static void s_dtpreldword (int);
1103 static void s_gpvalue (int);
1104 static void s_gpword (int);
1105 static void s_gpdword (int);
1106 static void s_cpadd (int);
1107 static void s_insn (int);
1108 static void md_obj_begin (void);
1109 static void md_obj_end (void);
1110 static void s_mips_ent (int);
1111 static void s_mips_end (int);
1112 static void s_mips_frame (int);
1113 static void s_mips_mask (int reg_type);
1114 static void s_mips_stab (int);
1115 static void s_mips_weakext (int);
1116 static void s_mips_file (int);
1117 static void s_mips_loc (int);
1118 static bfd_boolean pic_need_relax (symbolS *, asection *);
1119 static int relaxed_branch_length (fragS *, asection *, int);
1120 static int validate_mips_insn (const struct mips_opcode *);
1122 /* Table and functions used to map between CPU/ISA names, and
1123 ISA levels, and CPU numbers. */
1125 struct mips_cpu_info
1127 const char *name; /* CPU or ISA name. */
1128 int flags; /* ASEs available, or ISA flag. */
1129 int isa; /* ISA level. */
1130 int cpu; /* CPU number (default CPU if ISA). */
1133 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1134 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1135 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1136 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1137 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1138 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1139 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1141 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1142 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1143 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1147 The following pseudo-ops from the Kane and Heinrich MIPS book
1148 should be defined here, but are currently unsupported: .alias,
1149 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1151 The following pseudo-ops from the Kane and Heinrich MIPS book are
1152 specific to the type of debugging information being generated, and
1153 should be defined by the object format: .aent, .begin, .bend,
1154 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1157 The following pseudo-ops from the Kane and Heinrich MIPS book are
1158 not MIPS CPU specific, but are also not specific to the object file
1159 format. This file is probably the best place to define them, but
1160 they are not currently supported: .asm0, .endr, .lab, .struct. */
1162 static const pseudo_typeS mips_pseudo_table[] =
1164 /* MIPS specific pseudo-ops. */
1165 {"option", s_option, 0},
1166 {"set", s_mipsset, 0},
1167 {"rdata", s_change_sec, 'r'},
1168 {"sdata", s_change_sec, 's'},
1169 {"livereg", s_ignore, 0},
1170 {"abicalls", s_abicalls, 0},
1171 {"cpload", s_cpload, 0},
1172 {"cpsetup", s_cpsetup, 0},
1173 {"cplocal", s_cplocal, 0},
1174 {"cprestore", s_cprestore, 0},
1175 {"cpreturn", s_cpreturn, 0},
1176 {"dtprelword", s_dtprelword, 0},
1177 {"dtpreldword", s_dtpreldword, 0},
1178 {"gpvalue", s_gpvalue, 0},
1179 {"gpword", s_gpword, 0},
1180 {"gpdword", s_gpdword, 0},
1181 {"cpadd", s_cpadd, 0},
1182 {"insn", s_insn, 0},
1184 /* Relatively generic pseudo-ops that happen to be used on MIPS
1186 {"asciiz", stringer, 8 + 1},
1187 {"bss", s_change_sec, 'b'},
1189 {"half", s_cons, 1},
1190 {"dword", s_cons, 3},
1191 {"weakext", s_mips_weakext, 0},
1192 {"origin", s_org, 0},
1193 {"repeat", s_rept, 0},
1195 /* For MIPS this is non-standard, but we define it for consistency. */
1196 {"sbss", s_change_sec, 'B'},
1198 /* These pseudo-ops are defined in read.c, but must be overridden
1199 here for one reason or another. */
1200 {"align", s_align, 0},
1201 {"byte", s_cons, 0},
1202 {"data", s_change_sec, 'd'},
1203 {"double", s_float_cons, 'd'},
1204 {"float", s_float_cons, 'f'},
1205 {"globl", s_mips_globl, 0},
1206 {"global", s_mips_globl, 0},
1207 {"hword", s_cons, 1},
1209 {"long", s_cons, 2},
1210 {"octa", s_cons, 4},
1211 {"quad", s_cons, 3},
1212 {"section", s_change_section, 0},
1213 {"short", s_cons, 1},
1214 {"single", s_float_cons, 'f'},
1215 {"stabn", s_mips_stab, 'n'},
1216 {"text", s_change_sec, 't'},
1217 {"word", s_cons, 2},
1219 { "extern", ecoff_directive_extern, 0},
1224 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1226 /* These pseudo-ops should be defined by the object file format.
1227 However, a.out doesn't support them, so we have versions here. */
1228 {"aent", s_mips_ent, 1},
1229 {"bgnb", s_ignore, 0},
1230 {"end", s_mips_end, 0},
1231 {"endb", s_ignore, 0},
1232 {"ent", s_mips_ent, 0},
1233 {"file", s_mips_file, 0},
1234 {"fmask", s_mips_mask, 'F'},
1235 {"frame", s_mips_frame, 0},
1236 {"loc", s_mips_loc, 0},
1237 {"mask", s_mips_mask, 'R'},
1238 {"verstamp", s_ignore, 0},
1242 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1243 purpose of the `.dc.a' internal pseudo-op. */
1246 mips_address_bytes (void)
1248 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1251 extern void pop_insert (const pseudo_typeS *);
1254 mips_pop_insert (void)
1256 pop_insert (mips_pseudo_table);
1257 if (! ECOFF_DEBUGGING)
1258 pop_insert (mips_nonecoff_pseudo_table);
1261 /* Symbols labelling the current insn. */
1263 struct insn_label_list
1265 struct insn_label_list *next;
1269 static struct insn_label_list *free_insn_labels;
1270 #define label_list tc_segment_info_data.labels
1272 static void mips_clear_insn_labels (void);
1275 mips_clear_insn_labels (void)
1277 register struct insn_label_list **pl;
1278 segment_info_type *si;
1282 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1285 si = seg_info (now_seg);
1286 *pl = si->label_list;
1287 si->label_list = NULL;
1292 static char *expr_end;
1294 /* Expressions which appear in instructions. These are set by
1297 static expressionS imm_expr;
1298 static expressionS imm2_expr;
1299 static expressionS offset_expr;
1301 /* Relocs associated with imm_expr and offset_expr. */
1303 static bfd_reloc_code_real_type imm_reloc[3]
1304 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1305 static bfd_reloc_code_real_type offset_reloc[3]
1306 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1308 /* These are set by mips16_ip if an explicit extension is used. */
1310 static bfd_boolean mips16_small, mips16_ext;
1313 /* The pdr segment for per procedure frame/regmask info. Not used for
1316 static segT pdr_seg;
1319 /* The default target format to use. */
1321 #if defined (TE_FreeBSD)
1322 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1323 #elif defined (TE_TMIPS)
1324 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1326 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1330 mips_target_format (void)
1332 switch (OUTPUT_FLAVOR)
1334 case bfd_target_ecoff_flavour:
1335 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1336 case bfd_target_coff_flavour:
1338 case bfd_target_elf_flavour:
1340 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1341 return (target_big_endian
1342 ? "elf32-bigmips-vxworks"
1343 : "elf32-littlemips-vxworks");
1345 return (target_big_endian
1346 ? (HAVE_64BIT_OBJECTS
1347 ? ELF_TARGET ("elf64-", "big")
1349 ? ELF_TARGET ("elf32-n", "big")
1350 : ELF_TARGET ("elf32-", "big")))
1351 : (HAVE_64BIT_OBJECTS
1352 ? ELF_TARGET ("elf64-", "little")
1354 ? ELF_TARGET ("elf32-n", "little")
1355 : ELF_TARGET ("elf32-", "little"))));
1362 /* Return the length of instruction INSN. */
1364 static inline unsigned int
1365 insn_length (const struct mips_cl_insn *insn)
1367 if (!mips_opts.mips16)
1369 return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2;
1372 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1375 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1380 insn->use_extend = FALSE;
1382 insn->insn_opcode = mo->match;
1385 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1386 insn->fixp[i] = NULL;
1387 insn->fixed_p = (mips_opts.noreorder > 0);
1388 insn->noreorder_p = (mips_opts.noreorder > 0);
1389 insn->mips16_absolute_jump_p = 0;
1390 insn->complete_p = 0;
1393 /* Record the current MIPS16 mode in now_seg. */
1396 mips_record_mips16_mode (void)
1398 segment_info_type *si;
1400 si = seg_info (now_seg);
1401 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
1402 si->tc_segment_info_data.mips16 = mips_opts.mips16;
1405 /* Install INSN at the location specified by its "frag" and "where" fields. */
1408 install_insn (const struct mips_cl_insn *insn)
1410 char *f = insn->frag->fr_literal + insn->where;
1411 if (!mips_opts.mips16)
1412 md_number_to_chars (f, insn->insn_opcode, 4);
1413 else if (insn->mips16_absolute_jump_p)
1415 md_number_to_chars (f, insn->insn_opcode >> 16, 2);
1416 md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2);
1420 if (insn->use_extend)
1422 md_number_to_chars (f, 0xf000 | insn->extend, 2);
1425 md_number_to_chars (f, insn->insn_opcode, 2);
1427 mips_record_mips16_mode ();
1430 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1431 and install the opcode in the new location. */
1434 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
1439 insn->where = where;
1440 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1441 if (insn->fixp[i] != NULL)
1443 insn->fixp[i]->fx_frag = frag;
1444 insn->fixp[i]->fx_where = where;
1446 install_insn (insn);
1449 /* Add INSN to the end of the output. */
1452 add_fixed_insn (struct mips_cl_insn *insn)
1454 char *f = frag_more (insn_length (insn));
1455 move_insn (insn, frag_now, f - frag_now->fr_literal);
1458 /* Start a variant frag and move INSN to the start of the variant part,
1459 marking it as fixed. The other arguments are as for frag_var. */
1462 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
1463 relax_substateT subtype, symbolS *symbol, offsetT offset)
1465 frag_grow (max_chars);
1466 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
1468 frag_var (rs_machine_dependent, max_chars, var,
1469 subtype, symbol, offset, NULL);
1472 /* Insert N copies of INSN into the history buffer, starting at
1473 position FIRST. Neither FIRST nor N need to be clipped. */
1476 insert_into_history (unsigned int first, unsigned int n,
1477 const struct mips_cl_insn *insn)
1479 if (mips_relax.sequence != 2)
1483 for (i = ARRAY_SIZE (history); i-- > first;)
1485 history[i] = history[i - n];
1491 /* Emit a nop instruction, recording it in the history buffer. */
1496 add_fixed_insn (NOP_INSN);
1497 insert_into_history (0, 1, NOP_INSN);
1500 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1501 the idea is to make it obvious at a glance that each errata is
1505 init_vr4120_conflicts (void)
1507 #define CONFLICT(FIRST, SECOND) \
1508 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1510 /* Errata 21 - [D]DIV[U] after [D]MACC */
1511 CONFLICT (MACC, DIV);
1512 CONFLICT (DMACC, DIV);
1514 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1515 CONFLICT (DMULT, DMULT);
1516 CONFLICT (DMULT, DMACC);
1517 CONFLICT (DMACC, DMULT);
1518 CONFLICT (DMACC, DMACC);
1520 /* Errata 24 - MT{LO,HI} after [D]MACC */
1521 CONFLICT (MACC, MTHILO);
1522 CONFLICT (DMACC, MTHILO);
1524 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1525 instruction is executed immediately after a MACC or DMACC
1526 instruction, the result of [either instruction] is incorrect." */
1527 CONFLICT (MACC, MULT);
1528 CONFLICT (MACC, DMULT);
1529 CONFLICT (DMACC, MULT);
1530 CONFLICT (DMACC, DMULT);
1532 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1533 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1534 DDIV or DDIVU instruction, the result of the MACC or
1535 DMACC instruction is incorrect.". */
1536 CONFLICT (DMULT, MACC);
1537 CONFLICT (DMULT, DMACC);
1538 CONFLICT (DIV, MACC);
1539 CONFLICT (DIV, DMACC);
1549 #define RTYPE_MASK 0x1ff00
1550 #define RTYPE_NUM 0x00100
1551 #define RTYPE_FPU 0x00200
1552 #define RTYPE_FCC 0x00400
1553 #define RTYPE_VEC 0x00800
1554 #define RTYPE_GP 0x01000
1555 #define RTYPE_CP0 0x02000
1556 #define RTYPE_PC 0x04000
1557 #define RTYPE_ACC 0x08000
1558 #define RTYPE_CCC 0x10000
1559 #define RNUM_MASK 0x000ff
1560 #define RWARN 0x80000
1562 #define GENERIC_REGISTER_NUMBERS \
1563 {"$0", RTYPE_NUM | 0}, \
1564 {"$1", RTYPE_NUM | 1}, \
1565 {"$2", RTYPE_NUM | 2}, \
1566 {"$3", RTYPE_NUM | 3}, \
1567 {"$4", RTYPE_NUM | 4}, \
1568 {"$5", RTYPE_NUM | 5}, \
1569 {"$6", RTYPE_NUM | 6}, \
1570 {"$7", RTYPE_NUM | 7}, \
1571 {"$8", RTYPE_NUM | 8}, \
1572 {"$9", RTYPE_NUM | 9}, \
1573 {"$10", RTYPE_NUM | 10}, \
1574 {"$11", RTYPE_NUM | 11}, \
1575 {"$12", RTYPE_NUM | 12}, \
1576 {"$13", RTYPE_NUM | 13}, \
1577 {"$14", RTYPE_NUM | 14}, \
1578 {"$15", RTYPE_NUM | 15}, \
1579 {"$16", RTYPE_NUM | 16}, \
1580 {"$17", RTYPE_NUM | 17}, \
1581 {"$18", RTYPE_NUM | 18}, \
1582 {"$19", RTYPE_NUM | 19}, \
1583 {"$20", RTYPE_NUM | 20}, \
1584 {"$21", RTYPE_NUM | 21}, \
1585 {"$22", RTYPE_NUM | 22}, \
1586 {"$23", RTYPE_NUM | 23}, \
1587 {"$24", RTYPE_NUM | 24}, \
1588 {"$25", RTYPE_NUM | 25}, \
1589 {"$26", RTYPE_NUM | 26}, \
1590 {"$27", RTYPE_NUM | 27}, \
1591 {"$28", RTYPE_NUM | 28}, \
1592 {"$29", RTYPE_NUM | 29}, \
1593 {"$30", RTYPE_NUM | 30}, \
1594 {"$31", RTYPE_NUM | 31}
1596 #define FPU_REGISTER_NAMES \
1597 {"$f0", RTYPE_FPU | 0}, \
1598 {"$f1", RTYPE_FPU | 1}, \
1599 {"$f2", RTYPE_FPU | 2}, \
1600 {"$f3", RTYPE_FPU | 3}, \
1601 {"$f4", RTYPE_FPU | 4}, \
1602 {"$f5", RTYPE_FPU | 5}, \
1603 {"$f6", RTYPE_FPU | 6}, \
1604 {"$f7", RTYPE_FPU | 7}, \
1605 {"$f8", RTYPE_FPU | 8}, \
1606 {"$f9", RTYPE_FPU | 9}, \
1607 {"$f10", RTYPE_FPU | 10}, \
1608 {"$f11", RTYPE_FPU | 11}, \
1609 {"$f12", RTYPE_FPU | 12}, \
1610 {"$f13", RTYPE_FPU | 13}, \
1611 {"$f14", RTYPE_FPU | 14}, \
1612 {"$f15", RTYPE_FPU | 15}, \
1613 {"$f16", RTYPE_FPU | 16}, \
1614 {"$f17", RTYPE_FPU | 17}, \
1615 {"$f18", RTYPE_FPU | 18}, \
1616 {"$f19", RTYPE_FPU | 19}, \
1617 {"$f20", RTYPE_FPU | 20}, \
1618 {"$f21", RTYPE_FPU | 21}, \
1619 {"$f22", RTYPE_FPU | 22}, \
1620 {"$f23", RTYPE_FPU | 23}, \
1621 {"$f24", RTYPE_FPU | 24}, \
1622 {"$f25", RTYPE_FPU | 25}, \
1623 {"$f26", RTYPE_FPU | 26}, \
1624 {"$f27", RTYPE_FPU | 27}, \
1625 {"$f28", RTYPE_FPU | 28}, \
1626 {"$f29", RTYPE_FPU | 29}, \
1627 {"$f30", RTYPE_FPU | 30}, \
1628 {"$f31", RTYPE_FPU | 31}
1630 #define FPU_CONDITION_CODE_NAMES \
1631 {"$fcc0", RTYPE_FCC | 0}, \
1632 {"$fcc1", RTYPE_FCC | 1}, \
1633 {"$fcc2", RTYPE_FCC | 2}, \
1634 {"$fcc3", RTYPE_FCC | 3}, \
1635 {"$fcc4", RTYPE_FCC | 4}, \
1636 {"$fcc5", RTYPE_FCC | 5}, \
1637 {"$fcc6", RTYPE_FCC | 6}, \
1638 {"$fcc7", RTYPE_FCC | 7}
1640 #define COPROC_CONDITION_CODE_NAMES \
1641 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1642 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1643 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1644 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1645 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1646 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1647 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1648 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1650 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1651 {"$a4", RTYPE_GP | 8}, \
1652 {"$a5", RTYPE_GP | 9}, \
1653 {"$a6", RTYPE_GP | 10}, \
1654 {"$a7", RTYPE_GP | 11}, \
1655 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1656 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1657 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1658 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1659 {"$t0", RTYPE_GP | 12}, \
1660 {"$t1", RTYPE_GP | 13}, \
1661 {"$t2", RTYPE_GP | 14}, \
1662 {"$t3", RTYPE_GP | 15}
1664 #define O32_SYMBOLIC_REGISTER_NAMES \
1665 {"$t0", RTYPE_GP | 8}, \
1666 {"$t1", RTYPE_GP | 9}, \
1667 {"$t2", RTYPE_GP | 10}, \
1668 {"$t3", RTYPE_GP | 11}, \
1669 {"$t4", RTYPE_GP | 12}, \
1670 {"$t5", RTYPE_GP | 13}, \
1671 {"$t6", RTYPE_GP | 14}, \
1672 {"$t7", RTYPE_GP | 15}, \
1673 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1674 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1675 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1676 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1678 /* Remaining symbolic register names */
1679 #define SYMBOLIC_REGISTER_NAMES \
1680 {"$zero", RTYPE_GP | 0}, \
1681 {"$at", RTYPE_GP | 1}, \
1682 {"$AT", RTYPE_GP | 1}, \
1683 {"$v0", RTYPE_GP | 2}, \
1684 {"$v1", RTYPE_GP | 3}, \
1685 {"$a0", RTYPE_GP | 4}, \
1686 {"$a1", RTYPE_GP | 5}, \
1687 {"$a2", RTYPE_GP | 6}, \
1688 {"$a3", RTYPE_GP | 7}, \
1689 {"$s0", RTYPE_GP | 16}, \
1690 {"$s1", RTYPE_GP | 17}, \
1691 {"$s2", RTYPE_GP | 18}, \
1692 {"$s3", RTYPE_GP | 19}, \
1693 {"$s4", RTYPE_GP | 20}, \
1694 {"$s5", RTYPE_GP | 21}, \
1695 {"$s6", RTYPE_GP | 22}, \
1696 {"$s7", RTYPE_GP | 23}, \
1697 {"$t8", RTYPE_GP | 24}, \
1698 {"$t9", RTYPE_GP | 25}, \
1699 {"$k0", RTYPE_GP | 26}, \
1700 {"$kt0", RTYPE_GP | 26}, \
1701 {"$k1", RTYPE_GP | 27}, \
1702 {"$kt1", RTYPE_GP | 27}, \
1703 {"$gp", RTYPE_GP | 28}, \
1704 {"$sp", RTYPE_GP | 29}, \
1705 {"$s8", RTYPE_GP | 30}, \
1706 {"$fp", RTYPE_GP | 30}, \
1707 {"$ra", RTYPE_GP | 31}
1709 #define MIPS16_SPECIAL_REGISTER_NAMES \
1710 {"$pc", RTYPE_PC | 0}
1712 #define MDMX_VECTOR_REGISTER_NAMES \
1713 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
1714 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
1715 {"$v2", RTYPE_VEC | 2}, \
1716 {"$v3", RTYPE_VEC | 3}, \
1717 {"$v4", RTYPE_VEC | 4}, \
1718 {"$v5", RTYPE_VEC | 5}, \
1719 {"$v6", RTYPE_VEC | 6}, \
1720 {"$v7", RTYPE_VEC | 7}, \
1721 {"$v8", RTYPE_VEC | 8}, \
1722 {"$v9", RTYPE_VEC | 9}, \
1723 {"$v10", RTYPE_VEC | 10}, \
1724 {"$v11", RTYPE_VEC | 11}, \
1725 {"$v12", RTYPE_VEC | 12}, \
1726 {"$v13", RTYPE_VEC | 13}, \
1727 {"$v14", RTYPE_VEC | 14}, \
1728 {"$v15", RTYPE_VEC | 15}, \
1729 {"$v16", RTYPE_VEC | 16}, \
1730 {"$v17", RTYPE_VEC | 17}, \
1731 {"$v18", RTYPE_VEC | 18}, \
1732 {"$v19", RTYPE_VEC | 19}, \
1733 {"$v20", RTYPE_VEC | 20}, \
1734 {"$v21", RTYPE_VEC | 21}, \
1735 {"$v22", RTYPE_VEC | 22}, \
1736 {"$v23", RTYPE_VEC | 23}, \
1737 {"$v24", RTYPE_VEC | 24}, \
1738 {"$v25", RTYPE_VEC | 25}, \
1739 {"$v26", RTYPE_VEC | 26}, \
1740 {"$v27", RTYPE_VEC | 27}, \
1741 {"$v28", RTYPE_VEC | 28}, \
1742 {"$v29", RTYPE_VEC | 29}, \
1743 {"$v30", RTYPE_VEC | 30}, \
1744 {"$v31", RTYPE_VEC | 31}
1746 #define MIPS_DSP_ACCUMULATOR_NAMES \
1747 {"$ac0", RTYPE_ACC | 0}, \
1748 {"$ac1", RTYPE_ACC | 1}, \
1749 {"$ac2", RTYPE_ACC | 2}, \
1750 {"$ac3", RTYPE_ACC | 3}
1752 static const struct regname reg_names[] = {
1753 GENERIC_REGISTER_NUMBERS,
1755 FPU_CONDITION_CODE_NAMES,
1756 COPROC_CONDITION_CODE_NAMES,
1758 /* The $txx registers depends on the abi,
1759 these will be added later into the symbol table from
1760 one of the tables below once mips_abi is set after
1761 parsing of arguments from the command line. */
1762 SYMBOLIC_REGISTER_NAMES,
1764 MIPS16_SPECIAL_REGISTER_NAMES,
1765 MDMX_VECTOR_REGISTER_NAMES,
1766 MIPS_DSP_ACCUMULATOR_NAMES,
1770 static const struct regname reg_names_o32[] = {
1771 O32_SYMBOLIC_REGISTER_NAMES,
1775 static const struct regname reg_names_n32n64[] = {
1776 N32N64_SYMBOLIC_REGISTER_NAMES,
1781 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
1788 /* Find end of name. */
1790 if (is_name_beginner (*e))
1792 while (is_part_of_name (*e))
1795 /* Terminate name. */
1799 /* Look for a register symbol. */
1800 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
1802 int r = S_GET_VALUE (symbolP);
1804 reg = r & RNUM_MASK;
1805 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
1806 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
1807 reg = (r & RNUM_MASK) - 2;
1809 /* Else see if this is a register defined in an itbl entry. */
1810 else if ((types & RTYPE_GP) && itbl_have_entries)
1817 if (itbl_get_reg_val (n, &r))
1818 reg = r & RNUM_MASK;
1821 /* Advance to next token if a register was recognised. */
1824 else if (types & RWARN)
1825 as_warn (_("Unrecognized register name `%s'"), *s);
1833 /* Return TRUE if opcode MO is valid on the currently selected ISA and
1834 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
1837 is_opcode_valid (const struct mips_opcode *mo)
1839 int isa = mips_opts.isa;
1842 if (mips_opts.ase_mdmx)
1844 if (mips_opts.ase_dsp)
1846 if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
1848 if (mips_opts.ase_dspr2)
1850 if (mips_opts.ase_mt)
1852 if (mips_opts.ase_mips3d)
1854 if (mips_opts.ase_smartmips)
1855 isa |= INSN_SMARTMIPS;
1857 /* Don't accept instructions based on the ISA if the CPU does not implement
1858 all the coprocessor insns. */
1859 if (NO_ISA_COP (mips_opts.arch)
1860 && COP_INSN (mo->pinfo))
1863 if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch))
1866 /* Check whether the instruction or macro requires single-precision or
1867 double-precision floating-point support. Note that this information is
1868 stored differently in the opcode table for insns and macros. */
1869 if (mo->pinfo == INSN_MACRO)
1871 fp_s = mo->pinfo2 & INSN2_M_FP_S;
1872 fp_d = mo->pinfo2 & INSN2_M_FP_D;
1876 fp_s = mo->pinfo & FP_S;
1877 fp_d = mo->pinfo & FP_D;
1880 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
1883 if (fp_s && mips_opts.soft_float)
1889 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
1890 selected ISA and architecture. */
1893 is_opcode_valid_16 (const struct mips_opcode *mo)
1895 return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE;
1898 /* This function is called once, at assembler startup time. It should set up
1899 all the tables, etc. that the MD part of the assembler will need. */
1904 const char *retval = NULL;
1908 if (mips_pic != NO_PIC)
1910 if (g_switch_seen && g_switch_value != 0)
1911 as_bad (_("-G may not be used in position-independent code"));
1915 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
1916 as_warn (_("Could not set architecture and machine"));
1918 op_hash = hash_new ();
1920 for (i = 0; i < NUMOPCODES;)
1922 const char *name = mips_opcodes[i].name;
1924 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
1927 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1928 mips_opcodes[i].name, retval);
1929 /* Probably a memory allocation problem? Give up now. */
1930 as_fatal (_("Broken assembler. No assembly attempted."));
1934 if (mips_opcodes[i].pinfo != INSN_MACRO)
1936 if (!validate_mips_insn (&mips_opcodes[i]))
1938 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
1940 create_insn (&nop_insn, mips_opcodes + i);
1941 if (mips_fix_loongson2f_nop)
1942 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
1943 nop_insn.fixed_p = 1;
1948 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1951 mips16_op_hash = hash_new ();
1954 while (i < bfd_mips16_num_opcodes)
1956 const char *name = mips16_opcodes[i].name;
1958 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
1960 as_fatal (_("internal: can't hash `%s': %s"),
1961 mips16_opcodes[i].name, retval);
1964 if (mips16_opcodes[i].pinfo != INSN_MACRO
1965 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1966 != mips16_opcodes[i].match))
1968 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1969 mips16_opcodes[i].name, mips16_opcodes[i].args);
1972 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
1974 create_insn (&mips16_nop_insn, mips16_opcodes + i);
1975 mips16_nop_insn.fixed_p = 1;
1979 while (i < bfd_mips16_num_opcodes
1980 && strcmp (mips16_opcodes[i].name, name) == 0);
1984 as_fatal (_("Broken assembler. No assembly attempted."));
1986 /* We add all the general register names to the symbol table. This
1987 helps us detect invalid uses of them. */
1988 for (i = 0; reg_names[i].name; i++)
1989 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
1990 reg_names[i].num, /* & RNUM_MASK, */
1991 &zero_address_frag));
1993 for (i = 0; reg_names_n32n64[i].name; i++)
1994 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
1995 reg_names_n32n64[i].num, /* & RNUM_MASK, */
1996 &zero_address_frag));
1998 for (i = 0; reg_names_o32[i].name; i++)
1999 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
2000 reg_names_o32[i].num, /* & RNUM_MASK, */
2001 &zero_address_frag));
2003 mips_no_prev_insn ();
2006 mips_cprmask[0] = 0;
2007 mips_cprmask[1] = 0;
2008 mips_cprmask[2] = 0;
2009 mips_cprmask[3] = 0;
2011 /* set the default alignment for the text section (2**2) */
2012 record_alignment (text_section, 2);
2014 bfd_set_gp_size (stdoutput, g_switch_value);
2019 /* On a native system other than VxWorks, sections must be aligned
2020 to 16 byte boundaries. When configured for an embedded ELF
2021 target, we don't bother. */
2022 if (strncmp (TARGET_OS, "elf", 3) != 0
2023 && strncmp (TARGET_OS, "vxworks", 7) != 0)
2025 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
2026 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
2027 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
2030 /* Create a .reginfo section for register masks and a .mdebug
2031 section for debugging information. */
2039 subseg = now_subseg;
2041 /* The ABI says this section should be loaded so that the
2042 running program can access it. However, we don't load it
2043 if we are configured for an embedded target */
2044 flags = SEC_READONLY | SEC_DATA;
2045 if (strncmp (TARGET_OS, "elf", 3) != 0)
2046 flags |= SEC_ALLOC | SEC_LOAD;
2048 if (mips_abi != N64_ABI)
2050 sec = subseg_new (".reginfo", (subsegT) 0);
2052 bfd_set_section_flags (stdoutput, sec, flags);
2053 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
2055 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
2059 /* The 64-bit ABI uses a .MIPS.options section rather than
2060 .reginfo section. */
2061 sec = subseg_new (".MIPS.options", (subsegT) 0);
2062 bfd_set_section_flags (stdoutput, sec, flags);
2063 bfd_set_section_alignment (stdoutput, sec, 3);
2065 /* Set up the option header. */
2067 Elf_Internal_Options opthdr;
2070 opthdr.kind = ODK_REGINFO;
2071 opthdr.size = (sizeof (Elf_External_Options)
2072 + sizeof (Elf64_External_RegInfo));
2075 f = frag_more (sizeof (Elf_External_Options));
2076 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2077 (Elf_External_Options *) f);
2079 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2083 if (ECOFF_DEBUGGING)
2085 sec = subseg_new (".mdebug", (subsegT) 0);
2086 (void) bfd_set_section_flags (stdoutput, sec,
2087 SEC_HAS_CONTENTS | SEC_READONLY);
2088 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2090 else if (mips_flag_pdr)
2092 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2093 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2094 SEC_READONLY | SEC_RELOC
2096 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2099 subseg_set (seg, subseg);
2102 #endif /* OBJ_ELF */
2104 if (! ECOFF_DEBUGGING)
2107 if (mips_fix_vr4120)
2108 init_vr4120_conflicts ();
2114 if (! ECOFF_DEBUGGING)
2119 md_assemble (char *str)
2121 struct mips_cl_insn insn;
2122 bfd_reloc_code_real_type unused_reloc[3]
2123 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2125 imm_expr.X_op = O_absent;
2126 imm2_expr.X_op = O_absent;
2127 offset_expr.X_op = O_absent;
2128 imm_reloc[0] = BFD_RELOC_UNUSED;
2129 imm_reloc[1] = BFD_RELOC_UNUSED;
2130 imm_reloc[2] = BFD_RELOC_UNUSED;
2131 offset_reloc[0] = BFD_RELOC_UNUSED;
2132 offset_reloc[1] = BFD_RELOC_UNUSED;
2133 offset_reloc[2] = BFD_RELOC_UNUSED;
2135 if (mips_opts.mips16)
2136 mips16_ip (str, &insn);
2139 mips_ip (str, &insn);
2140 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2141 str, insn.insn_opcode));
2146 as_bad ("%s `%s'", insn_error, str);
2150 if (insn.insn_mo->pinfo == INSN_MACRO)
2153 if (mips_opts.mips16)
2154 mips16_macro (&insn);
2161 if (imm_expr.X_op != O_absent)
2162 append_insn (&insn, &imm_expr, imm_reloc);
2163 else if (offset_expr.X_op != O_absent)
2164 append_insn (&insn, &offset_expr, offset_reloc);
2166 append_insn (&insn, NULL, unused_reloc);
2170 /* Convenience functions for abstracting away the differences between
2171 MIPS16 and non-MIPS16 relocations. */
2173 static inline bfd_boolean
2174 mips16_reloc_p (bfd_reloc_code_real_type reloc)
2178 case BFD_RELOC_MIPS16_JMP:
2179 case BFD_RELOC_MIPS16_GPREL:
2180 case BFD_RELOC_MIPS16_GOT16:
2181 case BFD_RELOC_MIPS16_CALL16:
2182 case BFD_RELOC_MIPS16_HI16_S:
2183 case BFD_RELOC_MIPS16_HI16:
2184 case BFD_RELOC_MIPS16_LO16:
2192 static inline bfd_boolean
2193 got16_reloc_p (bfd_reloc_code_real_type reloc)
2195 return reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16;
2198 static inline bfd_boolean
2199 hi16_reloc_p (bfd_reloc_code_real_type reloc)
2201 return reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S;
2204 static inline bfd_boolean
2205 lo16_reloc_p (bfd_reloc_code_real_type reloc)
2207 return reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16;
2210 /* Return true if the given relocation might need a matching %lo().
2211 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2212 need a matching %lo() when applied to local symbols. */
2214 static inline bfd_boolean
2215 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
2217 return (HAVE_IN_PLACE_ADDENDS
2218 && (hi16_reloc_p (reloc)
2219 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2220 all GOT16 relocations evaluate to "G". */
2221 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
2224 /* Return the type of %lo() reloc needed by RELOC, given that
2225 reloc_needs_lo_p. */
2227 static inline bfd_reloc_code_real_type
2228 matching_lo_reloc (bfd_reloc_code_real_type reloc)
2230 return mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 : BFD_RELOC_LO16;
2233 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2236 static inline bfd_boolean
2237 fixup_has_matching_lo_p (fixS *fixp)
2239 return (fixp->fx_next != NULL
2240 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
2241 && fixp->fx_addsy == fixp->fx_next->fx_addsy
2242 && fixp->fx_offset == fixp->fx_next->fx_offset);
2245 /* See whether instruction IP reads register REG. CLASS is the type
2249 insn_uses_reg (const struct mips_cl_insn *ip, unsigned int reg,
2250 enum mips_regclass regclass)
2252 if (regclass == MIPS16_REG)
2254 gas_assert (mips_opts.mips16);
2255 reg = mips16_to_32_reg_map[reg];
2256 regclass = MIPS_GR_REG;
2259 /* Don't report on general register ZERO, since it never changes. */
2260 if (regclass == MIPS_GR_REG && reg == ZERO)
2263 if (regclass == MIPS_FP_REG)
2265 gas_assert (! mips_opts.mips16);
2266 /* If we are called with either $f0 or $f1, we must check $f0.
2267 This is not optimal, because it will introduce an unnecessary
2268 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
2269 need to distinguish reading both $f0 and $f1 or just one of
2270 them. Note that we don't have to check the other way,
2271 because there is no instruction that sets both $f0 and $f1
2272 and requires a delay. */
2273 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
2274 && ((EXTRACT_OPERAND (FS, *ip) & ~(unsigned) 1)
2275 == (reg &~ (unsigned) 1)))
2277 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
2278 && ((EXTRACT_OPERAND (FT, *ip) & ~(unsigned) 1)
2279 == (reg &~ (unsigned) 1)))
2281 if ((ip->insn_mo->pinfo2 & INSN2_READ_FPR_Z)
2282 && ((EXTRACT_OPERAND (FZ, *ip) & ~(unsigned) 1)
2283 == (reg &~ (unsigned) 1)))
2286 else if (! mips_opts.mips16)
2288 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
2289 && EXTRACT_OPERAND (RS, *ip) == reg)
2291 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
2292 && EXTRACT_OPERAND (RT, *ip) == reg)
2294 if ((ip->insn_mo->pinfo2 & INSN2_READ_GPR_D)
2295 && EXTRACT_OPERAND (RD, *ip) == reg)
2297 if ((ip->insn_mo->pinfo2 & INSN2_READ_GPR_Z)
2298 && EXTRACT_OPERAND (RZ, *ip) == reg)
2303 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
2304 && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)] == reg)
2306 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
2307 && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)] == reg)
2309 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
2310 && (mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]
2313 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
2315 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
2317 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
2319 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
2320 && MIPS16_EXTRACT_OPERAND (REGR32, *ip) == reg)
2327 /* This function returns true if modifying a register requires a
2331 reg_needs_delay (unsigned int reg)
2333 unsigned long prev_pinfo;
2335 prev_pinfo = history[0].insn_mo->pinfo;
2336 if (! mips_opts.noreorder
2337 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2338 && ! gpr_interlocks)
2339 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
2340 && ! cop_interlocks)))
2342 /* A load from a coprocessor or from memory. All load delays
2343 delay the use of general register rt for one instruction. */
2344 /* Itbl support may require additional care here. */
2345 know (prev_pinfo & INSN_WRITE_GPR_T);
2346 if (reg == EXTRACT_OPERAND (RT, history[0]))
2353 /* Move all labels in insn_labels to the current insertion point. */
2356 mips_move_labels (void)
2358 segment_info_type *si = seg_info (now_seg);
2359 struct insn_label_list *l;
2362 for (l = si->label_list; l != NULL; l = l->next)
2364 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
2365 symbol_set_frag (l->label, frag_now);
2366 val = (valueT) frag_now_fix ();
2367 /* mips16 text labels are stored as odd. */
2368 if (mips_opts.mips16)
2370 S_SET_VALUE (l->label, val);
2375 s_is_linkonce (symbolS *sym, segT from_seg)
2377 bfd_boolean linkonce = FALSE;
2378 segT symseg = S_GET_SEGMENT (sym);
2380 if (symseg != from_seg && !S_IS_LOCAL (sym))
2382 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
2385 /* The GNU toolchain uses an extension for ELF: a section
2386 beginning with the magic string .gnu.linkonce is a
2387 linkonce section. */
2388 if (strncmp (segment_name (symseg), ".gnu.linkonce",
2389 sizeof ".gnu.linkonce" - 1) == 0)
2396 /* Mark instruction labels in mips16 mode. This permits the linker to
2397 handle them specially, such as generating jalx instructions when
2398 needed. We also make them odd for the duration of the assembly, in
2399 order to generate the right sort of code. We will make them even
2400 in the adjust_symtab routine, while leaving them marked. This is
2401 convenient for the debugger and the disassembler. The linker knows
2402 to make them odd again. */
2405 mips16_mark_labels (void)
2407 segment_info_type *si = seg_info (now_seg);
2408 struct insn_label_list *l;
2410 if (!mips_opts.mips16)
2413 for (l = si->label_list; l != NULL; l = l->next)
2415 symbolS *label = l->label;
2417 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2419 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
2421 if ((S_GET_VALUE (label) & 1) == 0
2422 /* Don't adjust the address if the label is global or weak, or
2423 in a link-once section, since we'll be emitting symbol reloc
2424 references to it which will be patched up by the linker, and
2425 the final value of the symbol may or may not be MIPS16. */
2426 && ! S_IS_WEAK (label)
2427 && ! S_IS_EXTERNAL (label)
2428 && ! s_is_linkonce (label, now_seg))
2429 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
2433 /* End the current frag. Make it a variant frag and record the
2437 relax_close_frag (void)
2439 mips_macro_warning.first_frag = frag_now;
2440 frag_var (rs_machine_dependent, 0, 0,
2441 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
2442 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
2444 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
2445 mips_relax.first_fixup = 0;
2448 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2449 See the comment above RELAX_ENCODE for more details. */
2452 relax_start (symbolS *symbol)
2454 gas_assert (mips_relax.sequence == 0);
2455 mips_relax.sequence = 1;
2456 mips_relax.symbol = symbol;
2459 /* Start generating the second version of a relaxable sequence.
2460 See the comment above RELAX_ENCODE for more details. */
2465 gas_assert (mips_relax.sequence == 1);
2466 mips_relax.sequence = 2;
2469 /* End the current relaxable sequence. */
2474 gas_assert (mips_relax.sequence == 2);
2475 relax_close_frag ();
2476 mips_relax.sequence = 0;
2479 /* Classify an instruction according to the FIX_VR4120_* enumeration.
2480 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
2481 by VR4120 errata. */
2484 classify_vr4120_insn (const char *name)
2486 if (strncmp (name, "macc", 4) == 0)
2487 return FIX_VR4120_MACC;
2488 if (strncmp (name, "dmacc", 5) == 0)
2489 return FIX_VR4120_DMACC;
2490 if (strncmp (name, "mult", 4) == 0)
2491 return FIX_VR4120_MULT;
2492 if (strncmp (name, "dmult", 5) == 0)
2493 return FIX_VR4120_DMULT;
2494 if (strstr (name, "div"))
2495 return FIX_VR4120_DIV;
2496 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
2497 return FIX_VR4120_MTHILO;
2498 return NUM_FIX_VR4120_CLASSES;
2501 #define INSN_ERET 0x42000018
2502 #define INSN_DERET 0x4200001f
2504 /* Return the number of instructions that must separate INSN1 and INSN2,
2505 where INSN1 is the earlier instruction. Return the worst-case value
2506 for any INSN2 if INSN2 is null. */
2509 insns_between (const struct mips_cl_insn *insn1,
2510 const struct mips_cl_insn *insn2)
2512 unsigned long pinfo1, pinfo2;
2514 /* This function needs to know which pinfo flags are set for INSN2
2515 and which registers INSN2 uses. The former is stored in PINFO2 and
2516 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
2517 will have every flag set and INSN2_USES_REG will always return true. */
2518 pinfo1 = insn1->insn_mo->pinfo;
2519 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
2521 #define INSN2_USES_REG(REG, CLASS) \
2522 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
2524 /* For most targets, write-after-read dependencies on the HI and LO
2525 registers must be separated by at least two instructions. */
2526 if (!hilo_interlocks)
2528 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
2530 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
2534 /* If we're working around r7000 errata, there must be two instructions
2535 between an mfhi or mflo and any instruction that uses the result. */
2536 if (mips_7000_hilo_fix
2537 && MF_HILO_INSN (pinfo1)
2538 && INSN2_USES_REG (EXTRACT_OPERAND (RD, *insn1), MIPS_GR_REG))
2541 /* If we're working around 24K errata, one instruction is required
2542 if an ERET or DERET is followed by a branch instruction. */
2545 if (insn1->insn_opcode == INSN_ERET
2546 || insn1->insn_opcode == INSN_DERET)
2549 || insn2->insn_opcode == INSN_ERET
2550 || insn2->insn_opcode == INSN_DERET
2551 || (insn2->insn_mo->pinfo
2552 & (INSN_UNCOND_BRANCH_DELAY
2553 | INSN_COND_BRANCH_DELAY
2554 | INSN_COND_BRANCH_LIKELY)) != 0)
2559 /* If working around VR4120 errata, check for combinations that need
2560 a single intervening instruction. */
2561 if (mips_fix_vr4120)
2563 unsigned int class1, class2;
2565 class1 = classify_vr4120_insn (insn1->insn_mo->name);
2566 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
2570 class2 = classify_vr4120_insn (insn2->insn_mo->name);
2571 if (vr4120_conflicts[class1] & (1 << class2))
2576 if (!mips_opts.mips16)
2578 /* Check for GPR or coprocessor load delays. All such delays
2579 are on the RT register. */
2580 /* Itbl support may require additional care here. */
2581 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
2582 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
2584 know (pinfo1 & INSN_WRITE_GPR_T);
2585 if (INSN2_USES_REG (EXTRACT_OPERAND (RT, *insn1), MIPS_GR_REG))
2589 /* Check for generic coprocessor hazards.
2591 This case is not handled very well. There is no special
2592 knowledge of CP0 handling, and the coprocessors other than
2593 the floating point unit are not distinguished at all. */
2594 /* Itbl support may require additional care here. FIXME!
2595 Need to modify this to include knowledge about
2596 user specified delays! */
2597 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
2598 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
2600 /* Handle cases where INSN1 writes to a known general coprocessor
2601 register. There must be a one instruction delay before INSN2
2602 if INSN2 reads that register, otherwise no delay is needed. */
2603 if (pinfo1 & INSN_WRITE_FPR_T)
2605 if (INSN2_USES_REG (EXTRACT_OPERAND (FT, *insn1), MIPS_FP_REG))
2608 else if (pinfo1 & INSN_WRITE_FPR_S)
2610 if (INSN2_USES_REG (EXTRACT_OPERAND (FS, *insn1), MIPS_FP_REG))
2615 /* Read-after-write dependencies on the control registers
2616 require a two-instruction gap. */
2617 if ((pinfo1 & INSN_WRITE_COND_CODE)
2618 && (pinfo2 & INSN_READ_COND_CODE))
2621 /* We don't know exactly what INSN1 does. If INSN2 is
2622 also a coprocessor instruction, assume there must be
2623 a one instruction gap. */
2624 if (pinfo2 & INSN_COP)
2629 /* Check for read-after-write dependencies on the coprocessor
2630 control registers in cases where INSN1 does not need a general
2631 coprocessor delay. This means that INSN1 is a floating point
2632 comparison instruction. */
2633 /* Itbl support may require additional care here. */
2634 else if (!cop_interlocks
2635 && (pinfo1 & INSN_WRITE_COND_CODE)
2636 && (pinfo2 & INSN_READ_COND_CODE))
2640 #undef INSN2_USES_REG
2645 /* Return the number of nops that would be needed to work around the
2646 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2647 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
2648 that are contained within the first IGNORE instructions of HIST. */
2651 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
2652 const struct mips_cl_insn *insn)
2656 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2657 are not affected by the errata. */
2659 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
2660 || strcmp (insn->insn_mo->name, "mtlo") == 0
2661 || strcmp (insn->insn_mo->name, "mthi") == 0))
2664 /* Search for the first MFLO or MFHI. */
2665 for (i = 0; i < MAX_VR4130_NOPS; i++)
2666 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
2668 /* Extract the destination register. */
2669 if (mips_opts.mips16)
2670 reg = mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, hist[i])];
2672 reg = EXTRACT_OPERAND (RD, hist[i]);
2674 /* No nops are needed if INSN reads that register. */
2675 if (insn != NULL && insn_uses_reg (insn, reg, MIPS_GR_REG))
2678 /* ...or if any of the intervening instructions do. */
2679 for (j = 0; j < i; j++)
2680 if (insn_uses_reg (&hist[j], reg, MIPS_GR_REG))
2684 return MAX_VR4130_NOPS - i;
2689 #define BASE_REG_EQ(INSN1, INSN2) \
2690 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
2691 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
2693 /* Return the minimum alignment for this store instruction. */
2696 fix_24k_align_to (const struct mips_opcode *mo)
2698 if (strcmp (mo->name, "sh") == 0)
2701 if (strcmp (mo->name, "swc1") == 0
2702 || strcmp (mo->name, "swc2") == 0
2703 || strcmp (mo->name, "sw") == 0
2704 || strcmp (mo->name, "sc") == 0
2705 || strcmp (mo->name, "s.s") == 0)
2708 if (strcmp (mo->name, "sdc1") == 0
2709 || strcmp (mo->name, "sdc2") == 0
2710 || strcmp (mo->name, "s.d") == 0)
2717 struct fix_24k_store_info
2719 /* Immediate offset, if any, for this store instruction. */
2721 /* Alignment required by this store instruction. */
2723 /* True for register offsets. */
2724 int register_offset;
2727 /* Comparison function used by qsort. */
2730 fix_24k_sort (const void *a, const void *b)
2732 const struct fix_24k_store_info *pos1 = a;
2733 const struct fix_24k_store_info *pos2 = b;
2735 return (pos1->off - pos2->off);
2738 /* INSN is a store instruction. Try to record the store information
2739 in STINFO. Return false if the information isn't known. */
2742 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
2743 const struct mips_cl_insn *insn)
2745 /* The instruction must have a known offset. */
2746 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
2749 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
2750 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
2754 /* Return the number of nops that would be needed to work around the 24k
2755 "lost data on stores during refill" errata if instruction INSN
2756 immediately followed the 2 instructions described by HIST.
2757 Ignore hazards that are contained within the first IGNORE
2758 instructions of HIST.
2760 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
2761 for the data cache refills and store data. The following describes
2762 the scenario where the store data could be lost.
2764 * A data cache miss, due to either a load or a store, causing fill
2765 data to be supplied by the memory subsystem
2766 * The first three doublewords of fill data are returned and written
2768 * A sequence of four stores occurs in consecutive cycles around the
2769 final doubleword of the fill:
2773 * Zero, One or more instructions
2776 The four stores A-D must be to different doublewords of the line that
2777 is being filled. The fourth instruction in the sequence above permits
2778 the fill of the final doubleword to be transferred from the FSB into
2779 the cache. In the sequence above, the stores may be either integer
2780 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
2781 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
2782 different doublewords on the line. If the floating point unit is
2783 running in 1:2 mode, it is not possible to create the sequence above
2784 using only floating point store instructions.
2786 In this case, the cache line being filled is incorrectly marked
2787 invalid, thereby losing the data from any store to the line that
2788 occurs between the original miss and the completion of the five
2789 cycle sequence shown above.
2791 The workarounds are:
2793 * Run the data cache in write-through mode.
2794 * Insert a non-store instruction between
2795 Store A and Store B or Store B and Store C. */
2798 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
2799 const struct mips_cl_insn *insn)
2801 struct fix_24k_store_info pos[3];
2802 int align, i, base_offset;
2807 /* If INSN is definitely not a store, there's nothing to worry about. */
2808 if (insn && (insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
2811 /* Likewise, the previous instruction wasn't a store. */
2812 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
2815 /* If we don't know what came before, assume the worst. */
2816 if (hist[1].frag == NULL)
2819 /* If the instruction was not a store, there's nothing to worry about. */
2820 if ((hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
2823 /* If we don't know the relationship between the store addresses,
2824 assume the worst. */
2826 || !BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
2827 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
2830 if (!fix_24k_record_store_info (&pos[0], insn)
2831 || !fix_24k_record_store_info (&pos[1], &hist[0])
2832 || !fix_24k_record_store_info (&pos[2], &hist[1]))
2835 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
2837 /* Pick a value of ALIGN and X such that all offsets are adjusted by
2838 X bytes and such that the base register + X is known to be aligned
2841 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
2845 align = pos[0].align_to;
2846 base_offset = pos[0].off;
2847 for (i = 1; i < 3; i++)
2848 if (align < pos[i].align_to)
2850 align = pos[i].align_to;
2851 base_offset = pos[i].off;
2853 for (i = 0; i < 3; i++)
2854 pos[i].off -= base_offset;
2857 pos[0].off &= ~align + 1;
2858 pos[1].off &= ~align + 1;
2859 pos[2].off &= ~align + 1;
2861 /* If any two stores write to the same chunk, they also write to the
2862 same doubleword. The offsets are still sorted at this point. */
2863 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
2866 /* A range of at least 9 bytes is needed for the stores to be in
2867 non-overlapping doublewords. */
2868 if (pos[2].off - pos[0].off <= 8)
2871 if (pos[2].off - pos[1].off >= 24
2872 || pos[1].off - pos[0].off >= 24
2873 || pos[2].off - pos[0].off >= 32)
2879 /* Return the number of nops that would be needed if instruction INSN
2880 immediately followed the MAX_NOPS instructions given by HIST,
2881 where HIST[0] is the most recent instruction. Ignore hazards
2882 between INSN and the first IGNORE instructions in HIST.
2884 If INSN is null, return the worse-case number of nops for any
2888 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
2889 const struct mips_cl_insn *insn)
2891 int i, nops, tmp_nops;
2894 for (i = ignore; i < MAX_DELAY_NOPS; i++)
2896 tmp_nops = insns_between (hist + i, insn) - i;
2897 if (tmp_nops > nops)
2901 if (mips_fix_vr4130)
2903 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
2904 if (tmp_nops > nops)
2910 tmp_nops = nops_for_24k (ignore, hist, insn);
2911 if (tmp_nops > nops)
2918 /* The variable arguments provide NUM_INSNS extra instructions that
2919 might be added to HIST. Return the largest number of nops that
2920 would be needed after the extended sequence, ignoring hazards
2921 in the first IGNORE instructions. */
2924 nops_for_sequence (int num_insns, int ignore,
2925 const struct mips_cl_insn *hist, ...)
2928 struct mips_cl_insn buffer[MAX_NOPS];
2929 struct mips_cl_insn *cursor;
2932 va_start (args, hist);
2933 cursor = buffer + num_insns;
2934 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
2935 while (cursor > buffer)
2936 *--cursor = *va_arg (args, const struct mips_cl_insn *);
2938 nops = nops_for_insn (ignore, buffer, NULL);
2943 /* Like nops_for_insn, but if INSN is a branch, take into account the
2944 worst-case delay for the branch target. */
2947 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
2948 const struct mips_cl_insn *insn)
2952 nops = nops_for_insn (ignore, hist, insn);
2953 if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
2954 | INSN_COND_BRANCH_DELAY
2955 | INSN_COND_BRANCH_LIKELY))
2957 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
2958 hist, insn, NOP_INSN);
2959 if (tmp_nops > nops)
2962 else if (mips_opts.mips16
2963 && (insn->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
2964 | MIPS16_INSN_COND_BRANCH)))
2966 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
2967 if (tmp_nops > nops)
2973 /* Fix NOP issue: Replace nops by "or at,at,zero". */
2976 fix_loongson2f_nop (struct mips_cl_insn * ip)
2978 if (strcmp (ip->insn_mo->name, "nop") == 0)
2979 ip->insn_opcode = LOONGSON2F_NOP_INSN;
2982 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
2983 jr target pc &= 'hffff_ffff_cfff_ffff. */
2986 fix_loongson2f_jump (struct mips_cl_insn * ip)
2988 if (strcmp (ip->insn_mo->name, "j") == 0
2989 || strcmp (ip->insn_mo->name, "jr") == 0
2990 || strcmp (ip->insn_mo->name, "jalr") == 0)
2998 sreg = EXTRACT_OPERAND (RS, *ip);
2999 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
3002 ep.X_op = O_constant;
3003 ep.X_add_number = 0xcfff0000;
3004 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
3005 ep.X_add_number = 0xffff;
3006 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
3007 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
3012 fix_loongson2f (struct mips_cl_insn * ip)
3014 if (mips_fix_loongson2f_nop)
3015 fix_loongson2f_nop (ip);
3017 if (mips_fix_loongson2f_jump)
3018 fix_loongson2f_jump (ip);
3021 /* Output an instruction. IP is the instruction information.
3022 ADDRESS_EXPR is an operand of the instruction to be used with
3026 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
3027 bfd_reloc_code_real_type *reloc_type)
3029 unsigned long prev_pinfo, pinfo;
3030 unsigned long prev_pinfo2, pinfo2;
3031 relax_stateT prev_insn_frag_type = 0;
3032 bfd_boolean relaxed_branch = FALSE;
3033 segment_info_type *si = seg_info (now_seg);
3035 if (mips_fix_loongson2f)
3036 fix_loongson2f (ip);
3038 /* Mark instruction labels in mips16 mode. */
3039 mips16_mark_labels ();
3041 file_ase_mips16 |= mips_opts.mips16;
3043 prev_pinfo = history[0].insn_mo->pinfo;
3044 prev_pinfo2 = history[0].insn_mo->pinfo2;
3045 pinfo = ip->insn_mo->pinfo;
3046 pinfo2 = ip->insn_mo->pinfo2;
3048 if (address_expr == NULL)
3050 else if (*reloc_type <= BFD_RELOC_UNUSED
3051 && address_expr->X_op == O_constant)
3056 switch (*reloc_type)
3059 ip->insn_opcode |= address_expr->X_add_number;
3062 case BFD_RELOC_MIPS_HIGHEST:
3063 tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48;
3064 ip->insn_opcode |= tmp & 0xffff;
3067 case BFD_RELOC_MIPS_HIGHER:
3068 tmp = (address_expr->X_add_number + 0x80008000ull) >> 32;
3069 ip->insn_opcode |= tmp & 0xffff;
3072 case BFD_RELOC_HI16_S:
3073 tmp = (address_expr->X_add_number + 0x8000) >> 16;
3074 ip->insn_opcode |= tmp & 0xffff;
3077 case BFD_RELOC_HI16:
3078 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
3081 case BFD_RELOC_UNUSED:
3082 case BFD_RELOC_LO16:
3083 case BFD_RELOC_MIPS_GOT_DISP:
3084 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
3087 case BFD_RELOC_MIPS_JMP:
3088 if ((address_expr->X_add_number & 3) != 0)
3089 as_bad (_("jump to misaligned address (0x%lx)"),
3090 (unsigned long) address_expr->X_add_number);
3091 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
3095 case BFD_RELOC_MIPS16_JMP:
3096 if ((address_expr->X_add_number & 3) != 0)
3097 as_bad (_("jump to misaligned address (0x%lx)"),
3098 (unsigned long) address_expr->X_add_number);
3100 (((address_expr->X_add_number & 0x7c0000) << 3)
3101 | ((address_expr->X_add_number & 0xf800000) >> 7)
3102 | ((address_expr->X_add_number & 0x3fffc) >> 2));
3106 case BFD_RELOC_16_PCREL_S2:
3107 if ((address_expr->X_add_number & 3) != 0)
3108 as_bad (_("branch to misaligned address (0x%lx)"),
3109 (unsigned long) address_expr->X_add_number);
3110 if (mips_relax_branch)
3112 if ((address_expr->X_add_number + 0x20000) & ~0x3ffff)
3113 as_bad (_("branch address range overflow (0x%lx)"),
3114 (unsigned long) address_expr->X_add_number);
3115 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff;
3124 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
3126 /* There are a lot of optimizations we could do that we don't.
3127 In particular, we do not, in general, reorder instructions.
3128 If you use gcc with optimization, it will reorder
3129 instructions and generally do much more optimization then we
3130 do here; repeating all that work in the assembler would only
3131 benefit hand written assembly code, and does not seem worth
3133 int nops = (mips_optimize == 0
3134 ? nops_for_insn (0, history, NULL)
3135 : nops_for_insn_or_target (0, history, ip));
3139 unsigned long old_frag_offset;
3142 old_frag = frag_now;
3143 old_frag_offset = frag_now_fix ();
3145 for (i = 0; i < nops; i++)
3150 listing_prev_line ();
3151 /* We may be at the start of a variant frag. In case we
3152 are, make sure there is enough space for the frag
3153 after the frags created by listing_prev_line. The
3154 argument to frag_grow here must be at least as large
3155 as the argument to all other calls to frag_grow in
3156 this file. We don't have to worry about being in the
3157 middle of a variant frag, because the variants insert
3158 all needed nop instructions themselves. */
3162 mips_move_labels ();
3164 #ifndef NO_ECOFF_DEBUGGING
3165 if (ECOFF_DEBUGGING)
3166 ecoff_fix_loc (old_frag, old_frag_offset);
3170 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
3174 /* Work out how many nops in prev_nop_frag are needed by IP,
3175 ignoring hazards generated by the first prev_nop_frag_since
3177 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
3178 gas_assert (nops <= prev_nop_frag_holds);
3180 /* Enforce NOPS as a minimum. */
3181 if (nops > prev_nop_frag_required)
3182 prev_nop_frag_required = nops;
3184 if (prev_nop_frag_holds == prev_nop_frag_required)
3186 /* Settle for the current number of nops. Update the history
3187 accordingly (for the benefit of any future .set reorder code). */
3188 prev_nop_frag = NULL;
3189 insert_into_history (prev_nop_frag_since,
3190 prev_nop_frag_holds, NOP_INSN);
3194 /* Allow this instruction to replace one of the nops that was
3195 tentatively added to prev_nop_frag. */
3196 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
3197 prev_nop_frag_holds--;
3198 prev_nop_frag_since++;
3203 /* The value passed to dwarf2_emit_insn is the distance between
3204 the beginning of the current instruction and the address that
3205 should be recorded in the debug tables. For MIPS16 debug info
3206 we want to use ISA-encoded addresses, so we pass -1 for an
3207 address higher by one than the current. */
3208 dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0);
3211 /* Record the frag type before frag_var. */
3212 if (history[0].frag)
3213 prev_insn_frag_type = history[0].frag->fr_type;
3216 && *reloc_type == BFD_RELOC_16_PCREL_S2
3217 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
3218 || pinfo & INSN_COND_BRANCH_LIKELY)
3219 && mips_relax_branch
3220 /* Don't try branch relaxation within .set nomacro, or within
3221 .set noat if we use $at for PIC computations. If it turns
3222 out that the branch was out-of-range, we'll get an error. */
3223 && !mips_opts.warn_about_macros
3224 && (mips_opts.at || mips_pic == NO_PIC)
3225 /* Don't relax BPOSGE32/64 as they have no complementing branches. */
3226 && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP))
3227 && !mips_opts.mips16)
3229 relaxed_branch = TRUE;
3230 add_relaxed_insn (ip, (relaxed_branch_length
3232 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
3233 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1
3237 pinfo & INSN_UNCOND_BRANCH_DELAY,
3238 pinfo & INSN_COND_BRANCH_LIKELY,
3239 pinfo & INSN_WRITE_GPR_31,
3241 address_expr->X_add_symbol,
3242 address_expr->X_add_number);
3243 *reloc_type = BFD_RELOC_UNUSED;
3245 else if (*reloc_type > BFD_RELOC_UNUSED)
3247 /* We need to set up a variant frag. */
3248 gas_assert (mips_opts.mips16 && address_expr != NULL);
3249 add_relaxed_insn (ip, 4, 0,
3251 (*reloc_type - BFD_RELOC_UNUSED,
3252 mips16_small, mips16_ext,
3253 prev_pinfo & INSN_UNCOND_BRANCH_DELAY,
3254 history[0].mips16_absolute_jump_p),
3255 make_expr_symbol (address_expr), 0);
3257 else if (mips_opts.mips16
3259 && *reloc_type != BFD_RELOC_MIPS16_JMP)
3261 if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0)
3262 /* Make sure there is enough room to swap this instruction with
3263 a following jump instruction. */
3265 add_fixed_insn (ip);
3269 if (mips_opts.mips16
3270 && mips_opts.noreorder
3271 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
3272 as_warn (_("extended instruction in delay slot"));
3274 if (mips_relax.sequence)
3276 /* If we've reached the end of this frag, turn it into a variant
3277 frag and record the information for the instructions we've
3279 if (frag_room () < 4)
3280 relax_close_frag ();
3281 mips_relax.sizes[mips_relax.sequence - 1] += 4;
3284 if (mips_relax.sequence != 2)
3285 mips_macro_warning.sizes[0] += 4;
3286 if (mips_relax.sequence != 1)
3287 mips_macro_warning.sizes[1] += 4;
3289 if (mips_opts.mips16)
3292 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
3294 add_fixed_insn (ip);
3297 if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED)
3300 && *reloc_type < BFD_RELOC_UNUSED)
3303 reloc_howto_type *howto;
3306 /* In a compound relocation, it is the final (outermost)
3307 operator that determines the relocated field. */
3308 for (i = 1; i < 3; i++)
3309 if (reloc_type[i] == BFD_RELOC_UNUSED)
3312 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
3315 /* To reproduce this failure try assembling gas/testsuites/
3316 gas/mips/mips16-intermix.s with a mips-ecoff targeted
3318 as_bad (_("Unsupported MIPS relocation number %d"), reloc_type[i - 1]);
3319 howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16);
3322 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
3323 bfd_get_reloc_size (howto),
3325 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
3328 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
3329 if (reloc_type[0] == BFD_RELOC_MIPS16_JMP
3330 && ip->fixp[0]->fx_addsy)
3331 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
3333 /* These relocations can have an addend that won't fit in
3334 4 octets for 64bit assembly. */
3336 && ! howto->partial_inplace
3337 && (reloc_type[0] == BFD_RELOC_16
3338 || reloc_type[0] == BFD_RELOC_32
3339 || reloc_type[0] == BFD_RELOC_MIPS_JMP
3340 || reloc_type[0] == BFD_RELOC_GPREL16
3341 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
3342 || reloc_type[0] == BFD_RELOC_GPREL32
3343 || reloc_type[0] == BFD_RELOC_64
3344 || reloc_type[0] == BFD_RELOC_CTOR
3345 || reloc_type[0] == BFD_RELOC_MIPS_SUB
3346 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
3347 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
3348 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
3349 || reloc_type[0] == BFD_RELOC_MIPS_REL16
3350 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
3351 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
3352 || hi16_reloc_p (reloc_type[0])
3353 || lo16_reloc_p (reloc_type[0])))
3354 ip->fixp[0]->fx_no_overflow = 1;
3356 if (mips_relax.sequence)
3358 if (mips_relax.first_fixup == 0)
3359 mips_relax.first_fixup = ip->fixp[0];
3361 else if (reloc_needs_lo_p (*reloc_type))
3363 struct mips_hi_fixup *hi_fixup;
3365 /* Reuse the last entry if it already has a matching %lo. */
3366 hi_fixup = mips_hi_fixup_list;
3368 || !fixup_has_matching_lo_p (hi_fixup->fixp))
3370 hi_fixup = ((struct mips_hi_fixup *)
3371 xmalloc (sizeof (struct mips_hi_fixup)));
3372 hi_fixup->next = mips_hi_fixup_list;
3373 mips_hi_fixup_list = hi_fixup;
3375 hi_fixup->fixp = ip->fixp[0];
3376 hi_fixup->seg = now_seg;
3379 /* Add fixups for the second and third relocations, if given.
3380 Note that the ABI allows the second relocation to be
3381 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
3382 moment we only use RSS_UNDEF, but we could add support
3383 for the others if it ever becomes necessary. */
3384 for (i = 1; i < 3; i++)
3385 if (reloc_type[i] != BFD_RELOC_UNUSED)
3387 ip->fixp[i] = fix_new (ip->frag, ip->where,
3388 ip->fixp[0]->fx_size, NULL, 0,
3389 FALSE, reloc_type[i]);
3391 /* Use fx_tcbit to mark compound relocs. */
3392 ip->fixp[0]->fx_tcbit = 1;
3393 ip->fixp[i]->fx_tcbit = 1;
3399 /* Update the register mask information. */
3400 if (! mips_opts.mips16)
3402 if ((pinfo & INSN_WRITE_GPR_D) || (pinfo2 & INSN2_READ_GPR_D))
3403 mips_gprmask |= 1 << EXTRACT_OPERAND (RD, *ip);
3404 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
3405 mips_gprmask |= 1 << EXTRACT_OPERAND (RT, *ip);
3406 if (pinfo & INSN_READ_GPR_S)
3407 mips_gprmask |= 1 << EXTRACT_OPERAND (RS, *ip);
3408 if (pinfo & INSN_WRITE_GPR_31)
3409 mips_gprmask |= 1 << RA;
3410 if (pinfo2 & (INSN2_WRITE_GPR_Z | INSN2_READ_GPR_Z))
3411 mips_gprmask |= 1 << EXTRACT_OPERAND (RZ, *ip);
3412 if (pinfo & INSN_WRITE_FPR_D)
3413 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FD, *ip);
3414 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
3415 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FS, *ip);
3416 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
3417 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FT, *ip);
3418 if ((pinfo & INSN_READ_FPR_R) != 0)
3419 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FR, *ip);
3420 if (pinfo2 & (INSN2_WRITE_FPR_Z | INSN2_READ_FPR_Z))
3421 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FZ, *ip);
3422 if (pinfo & INSN_COP)
3424 /* We don't keep enough information to sort these cases out.
3425 The itbl support does keep this information however, although
3426 we currently don't support itbl fprmats as part of the cop
3427 instruction. May want to add this support in the future. */
3429 /* Never set the bit for $0, which is always zero. */
3430 mips_gprmask &= ~1 << 0;
3434 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
3435 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RX, *ip);
3436 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
3437 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RY, *ip);
3438 if (pinfo & MIPS16_INSN_WRITE_Z)
3439 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RZ, *ip);
3440 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
3441 mips_gprmask |= 1 << TREG;
3442 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
3443 mips_gprmask |= 1 << SP;
3444 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
3445 mips_gprmask |= 1 << RA;
3446 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
3447 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
3448 if (pinfo & MIPS16_INSN_READ_Z)
3449 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip);
3450 if (pinfo & MIPS16_INSN_READ_GPR_X)
3451 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
3454 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
3456 /* Filling the branch delay slot is more complex. We try to
3457 switch the branch with the previous instruction, which we can
3458 do if the previous instruction does not set up a condition
3459 that the branch tests and if the branch is not itself the
3460 target of any branch. */
3461 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
3462 || (pinfo & INSN_COND_BRANCH_DELAY))
3464 if (mips_optimize < 2
3465 /* If we have seen .set volatile or .set nomove, don't
3467 || mips_opts.nomove != 0
3468 /* We can't swap if the previous instruction's position
3470 || history[0].fixed_p
3471 /* If the previous previous insn was in a .set
3472 noreorder, we can't swap. Actually, the MIPS
3473 assembler will swap in this situation. However, gcc
3474 configured -with-gnu-as will generate code like
3480 in which we can not swap the bne and INSN. If gcc is
3481 not configured -with-gnu-as, it does not output the
3483 || history[1].noreorder_p
3484 /* If the branch is itself the target of a branch, we
3485 can not swap. We cheat on this; all we check for is
3486 whether there is a label on this instruction. If
3487 there are any branches to anything other than a
3488 label, users must use .set noreorder. */
3489 || si->label_list != NULL
3490 /* If the previous instruction is in a variant frag
3491 other than this branch's one, we cannot do the swap.
3492 This does not apply to the mips16, which uses variant
3493 frags for different purposes. */
3494 || (! mips_opts.mips16
3495 && prev_insn_frag_type == rs_machine_dependent)
3496 /* Check for conflicts between the branch and the instructions
3497 before the candidate delay slot. */
3498 || nops_for_insn (0, history + 1, ip) > 0
3499 /* Check for conflicts between the swapped sequence and the
3500 target of the branch. */
3501 || nops_for_sequence (2, 0, history + 1, ip, history) > 0
3502 /* We do not swap with a trap instruction, since it
3503 complicates trap handlers to have the trap
3504 instruction be in a delay slot. */
3505 || (prev_pinfo & INSN_TRAP)
3506 /* If the branch reads a register that the previous
3507 instruction sets, we can not swap. */
3508 || (! mips_opts.mips16
3509 && (prev_pinfo & INSN_WRITE_GPR_T)
3510 && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]),
3512 || (! mips_opts.mips16
3513 && (prev_pinfo & INSN_WRITE_GPR_D)
3514 && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]),
3516 || (! mips_opts.mips16
3517 && (prev_pinfo2 & INSN2_WRITE_GPR_Z)
3518 && insn_uses_reg (ip, EXTRACT_OPERAND (RZ, history[0]),
3520 || (mips_opts.mips16
3521 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
3523 (ip, MIPS16_EXTRACT_OPERAND (RX, history[0]),
3525 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
3527 (ip, MIPS16_EXTRACT_OPERAND (RY, history[0]),
3529 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
3531 (ip, MIPS16_EXTRACT_OPERAND (RZ, history[0]),
3533 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
3534 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
3535 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
3536 && insn_uses_reg (ip, RA, MIPS_GR_REG))
3537 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
3538 && insn_uses_reg (ip,
3539 MIPS16OP_EXTRACT_REG32R
3540 (history[0].insn_opcode),
3542 /* If the branch writes a register that the previous
3543 instruction sets, we can not swap (we know that
3544 branches write only to RD or to $31). */
3545 || (! mips_opts.mips16
3546 && (prev_pinfo & INSN_WRITE_GPR_T)
3547 && (((pinfo & INSN_WRITE_GPR_D)
3548 && (EXTRACT_OPERAND (RT, history[0])
3549 == EXTRACT_OPERAND (RD, *ip)))
3550 || ((pinfo & INSN_WRITE_GPR_31)
3551 && EXTRACT_OPERAND (RT, history[0]) == RA)))
3552 || (! mips_opts.mips16
3553 && (prev_pinfo & INSN_WRITE_GPR_D)
3554 && (((pinfo & INSN_WRITE_GPR_D)
3555 && (EXTRACT_OPERAND (RD, history[0])
3556 == EXTRACT_OPERAND (RD, *ip)))
3557 || ((pinfo & INSN_WRITE_GPR_31)
3558 && EXTRACT_OPERAND (RD, history[0]) == RA)))
3559 || (mips_opts.mips16
3560 && (pinfo & MIPS16_INSN_WRITE_31)
3561 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
3562 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
3563 && (MIPS16OP_EXTRACT_REG32R (history[0].insn_opcode)
3565 /* If the branch writes a register that the previous
3566 instruction reads, we can not swap (we know that
3567 branches only write to RD or to $31). */
3568 || (! mips_opts.mips16
3569 && (pinfo & INSN_WRITE_GPR_D)
3570 && insn_uses_reg (&history[0],
3571 EXTRACT_OPERAND (RD, *ip),
3573 || (! mips_opts.mips16
3574 && (pinfo & INSN_WRITE_GPR_31)
3575 && insn_uses_reg (&history[0], RA, MIPS_GR_REG))
3576 || (mips_opts.mips16
3577 && (pinfo & MIPS16_INSN_WRITE_31)
3578 && insn_uses_reg (&history[0], RA, MIPS_GR_REG))
3579 /* If one instruction sets a condition code and the
3580 other one uses a condition code, we can not swap. */
3581 || ((pinfo & INSN_READ_COND_CODE)
3582 && (prev_pinfo & INSN_WRITE_COND_CODE))
3583 || ((pinfo & INSN_WRITE_COND_CODE)
3584 && (prev_pinfo & INSN_READ_COND_CODE))
3585 /* If the previous instruction uses the PC, we can not
3587 || (mips_opts.mips16
3588 && (prev_pinfo & MIPS16_INSN_READ_PC))
3589 /* If the previous instruction had a fixup in mips16
3590 mode, we can not swap. This normally means that the
3591 previous instruction was a 4 byte branch anyhow. */
3592 || (mips_opts.mips16 && history[0].fixp[0])
3593 /* If the previous instruction is a sync, sync.l, or
3594 sync.p, we can not swap. */
3595 || (prev_pinfo & INSN_SYNC)
3596 /* If the previous instruction is an ERET or
3597 DERET, avoid the swap. */
3598 || (history[0].insn_opcode == INSN_ERET)
3599 || (history[0].insn_opcode == INSN_DERET))
3601 if (mips_opts.mips16
3602 && (pinfo & INSN_UNCOND_BRANCH_DELAY)
3603 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))
3604 && ISA_SUPPORTS_MIPS16E)
3606 /* Convert MIPS16 jr/jalr into a "compact" jump. */
3607 ip->insn_opcode |= 0x0080;
3609 insert_into_history (0, 1, ip);
3613 /* We could do even better for unconditional branches to
3614 portions of this object file; we could pick up the
3615 instruction at the destination, put it in the delay
3616 slot, and bump the destination address. */
3617 insert_into_history (0, 1, ip);
3621 if (mips_relax.sequence)
3622 mips_relax.sizes[mips_relax.sequence - 1] += 4;
3626 /* It looks like we can actually do the swap. */
3627 struct mips_cl_insn delay = history[0];
3628 if (mips_opts.mips16)
3630 know (delay.frag == ip->frag);
3631 move_insn (ip, delay.frag, delay.where);
3632 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
3634 else if (relaxed_branch)
3636 /* Add the delay slot instruction to the end of the
3637 current frag and shrink the fixed part of the
3638 original frag. If the branch occupies the tail of
3639 the latter, move it backwards to cover the gap. */
3640 delay.frag->fr_fix -= 4;
3641 if (delay.frag == ip->frag)
3642 move_insn (ip, ip->frag, ip->where - 4);
3643 add_fixed_insn (&delay);
3647 move_insn (&delay, ip->frag, ip->where);
3648 move_insn (ip, history[0].frag, history[0].where);
3652 insert_into_history (0, 1, &delay);
3655 /* If that was an unconditional branch, forget the previous
3656 insn information. */
3657 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
3659 mips_no_prev_insn ();
3662 else if (pinfo & INSN_COND_BRANCH_LIKELY)
3664 /* We don't yet optimize a branch likely. What we should do
3665 is look at the target, copy the instruction found there
3666 into the delay slot, and increment the branch to jump to
3667 the next instruction. */
3668 insert_into_history (0, 1, ip);
3672 insert_into_history (0, 1, ip);
3675 insert_into_history (0, 1, ip);
3677 /* We just output an insn, so the next one doesn't have a label. */
3678 mips_clear_insn_labels ();
3681 /* Forget that there was any previous instruction or label. */
3684 mips_no_prev_insn (void)
3686 prev_nop_frag = NULL;
3687 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
3688 mips_clear_insn_labels ();
3691 /* This function must be called before we emit something other than
3692 instructions. It is like mips_no_prev_insn except that it inserts
3693 any NOPS that might be needed by previous instructions. */
3696 mips_emit_delays (void)
3698 if (! mips_opts.noreorder)
3700 int nops = nops_for_insn (0, history, NULL);
3704 add_fixed_insn (NOP_INSN);
3705 mips_move_labels ();
3708 mips_no_prev_insn ();
3711 /* Start a (possibly nested) noreorder block. */
3714 start_noreorder (void)
3716 if (mips_opts.noreorder == 0)
3721 /* None of the instructions before the .set noreorder can be moved. */
3722 for (i = 0; i < ARRAY_SIZE (history); i++)
3723 history[i].fixed_p = 1;
3725 /* Insert any nops that might be needed between the .set noreorder
3726 block and the previous instructions. We will later remove any
3727 nops that turn out not to be needed. */
3728 nops = nops_for_insn (0, history, NULL);
3731 if (mips_optimize != 0)
3733 /* Record the frag which holds the nop instructions, so
3734 that we can remove them if we don't need them. */
3735 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
3736 prev_nop_frag = frag_now;
3737 prev_nop_frag_holds = nops;
3738 prev_nop_frag_required = 0;
3739 prev_nop_frag_since = 0;
3742 for (; nops > 0; --nops)
3743 add_fixed_insn (NOP_INSN);
3745 /* Move on to a new frag, so that it is safe to simply
3746 decrease the size of prev_nop_frag. */
3747 frag_wane (frag_now);
3749 mips_move_labels ();
3751 mips16_mark_labels ();
3752 mips_clear_insn_labels ();
3754 mips_opts.noreorder++;
3755 mips_any_noreorder = 1;
3758 /* End a nested noreorder block. */
3761 end_noreorder (void)
3764 mips_opts.noreorder--;
3765 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
3767 /* Commit to inserting prev_nop_frag_required nops and go back to
3768 handling nop insertion the .set reorder way. */
3769 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
3770 * (mips_opts.mips16 ? 2 : 4));
3771 insert_into_history (prev_nop_frag_since,
3772 prev_nop_frag_required, NOP_INSN);
3773 prev_nop_frag = NULL;
3777 /* Set up global variables for the start of a new macro. */
3782 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
3783 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
3784 && (history[0].insn_mo->pinfo
3785 & (INSN_UNCOND_BRANCH_DELAY
3786 | INSN_COND_BRANCH_DELAY
3787 | INSN_COND_BRANCH_LIKELY)) != 0);
3790 /* Given that a macro is longer than 4 bytes, return the appropriate warning
3791 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
3792 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
3795 macro_warning (relax_substateT subtype)
3797 if (subtype & RELAX_DELAY_SLOT)
3798 return _("Macro instruction expanded into multiple instructions"
3799 " in a branch delay slot");
3800 else if (subtype & RELAX_NOMACRO)
3801 return _("Macro instruction expanded into multiple instructions");
3806 /* Finish up a macro. Emit warnings as appropriate. */
3811 if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4)
3813 relax_substateT subtype;
3815 /* Set up the relaxation warning flags. */
3817 if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0])
3818 subtype |= RELAX_SECOND_LONGER;
3819 if (mips_opts.warn_about_macros)
3820 subtype |= RELAX_NOMACRO;
3821 if (mips_macro_warning.delay_slot_p)
3822 subtype |= RELAX_DELAY_SLOT;
3824 if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4)
3826 /* Either the macro has a single implementation or both
3827 implementations are longer than 4 bytes. Emit the
3829 const char *msg = macro_warning (subtype);
3831 as_warn ("%s", msg);
3835 /* One implementation might need a warning but the other
3836 definitely doesn't. */
3837 mips_macro_warning.first_frag->fr_subtype |= subtype;
3842 /* Read a macro's relocation codes from *ARGS and store them in *R.
3843 The first argument in *ARGS will be either the code for a single
3844 relocation or -1 followed by the three codes that make up a
3845 composite relocation. */
3848 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
3852 next = va_arg (*args, int);
3854 r[0] = (bfd_reloc_code_real_type) next;
3856 for (i = 0; i < 3; i++)
3857 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
3860 /* Build an instruction created by a macro expansion. This is passed
3861 a pointer to the count of instructions created so far, an
3862 expression, the name of the instruction to build, an operand format
3863 string, and corresponding arguments. */
3866 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
3868 const struct mips_opcode *mo;
3869 struct mips_cl_insn insn;
3870 bfd_reloc_code_real_type r[3];
3873 va_start (args, fmt);
3875 if (mips_opts.mips16)
3877 mips16_macro_build (ep, name, fmt, &args);
3882 r[0] = BFD_RELOC_UNUSED;
3883 r[1] = BFD_RELOC_UNUSED;
3884 r[2] = BFD_RELOC_UNUSED;
3885 mo = (struct mips_opcode *) hash_find (op_hash, name);
3887 gas_assert (strcmp (name, mo->name) == 0);
3891 /* Search until we get a match for NAME. It is assumed here that
3892 macros will never generate MDMX, MIPS-3D, or MT instructions. */
3893 if (strcmp (fmt, mo->args) == 0
3894 && mo->pinfo != INSN_MACRO
3895 && is_opcode_valid (mo))
3899 gas_assert (mo->name);
3900 gas_assert (strcmp (name, mo->name) == 0);
3903 create_insn (&insn, mo);
3921 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
3926 /* Note that in the macro case, these arguments are already
3927 in MSB form. (When handling the instruction in the
3928 non-macro case, these arguments are sizes from which
3929 MSB values must be calculated.) */
3930 INSERT_OPERAND (INSMSB, insn, va_arg (args, int));
3936 /* Note that in the macro case, these arguments are already
3937 in MSBD form. (When handling the instruction in the
3938 non-macro case, these arguments are sizes from which
3939 MSBD values must be calculated.) */
3940 INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int));
3944 INSERT_OPERAND (SEQI, insn, va_arg (args, int));
3953 INSERT_OPERAND (BP, insn, va_arg (args, int));
3959 INSERT_OPERAND (RT, insn, va_arg (args, int));
3963 INSERT_OPERAND (CODE, insn, va_arg (args, int));
3968 INSERT_OPERAND (FT, insn, va_arg (args, int));
3974 INSERT_OPERAND (RD, insn, va_arg (args, int));
3979 int tmp = va_arg (args, int);
3981 INSERT_OPERAND (RT, insn, tmp);
3982 INSERT_OPERAND (RD, insn, tmp);
3988 INSERT_OPERAND (FS, insn, va_arg (args, int));
3995 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
3999 INSERT_OPERAND (FD, insn, va_arg (args, int));
4003 INSERT_OPERAND (CODE20, insn, va_arg (args, int));
4007 INSERT_OPERAND (CODE19, insn, va_arg (args, int));
4011 INSERT_OPERAND (CODE2, insn, va_arg (args, int));
4018 INSERT_OPERAND (RS, insn, va_arg (args, int));
4023 macro_read_relocs (&args, r);
4024 gas_assert (*r == BFD_RELOC_GPREL16
4025 || *r == BFD_RELOC_MIPS_HIGHER
4026 || *r == BFD_RELOC_HI16_S
4027 || *r == BFD_RELOC_LO16
4028 || *r == BFD_RELOC_MIPS_GOT_OFST);
4032 macro_read_relocs (&args, r);
4036 macro_read_relocs (&args, r);
4037 gas_assert (ep != NULL
4038 && (ep->X_op == O_constant
4039 || (ep->X_op == O_symbol
4040 && (*r == BFD_RELOC_MIPS_HIGHEST
4041 || *r == BFD_RELOC_HI16_S
4042 || *r == BFD_RELOC_HI16
4043 || *r == BFD_RELOC_GPREL16
4044 || *r == BFD_RELOC_MIPS_GOT_HI16
4045 || *r == BFD_RELOC_MIPS_CALL_HI16))));
4049 gas_assert (ep != NULL);
4052 * This allows macro() to pass an immediate expression for
4053 * creating short branches without creating a symbol.
4055 * We don't allow branch relaxation for these branches, as
4056 * they should only appear in ".set nomacro" anyway.
4058 if (ep->X_op == O_constant)
4060 if ((ep->X_add_number & 3) != 0)
4061 as_bad (_("branch to misaligned address (0x%lx)"),
4062 (unsigned long) ep->X_add_number);
4063 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
4064 as_bad (_("branch address range overflow (0x%lx)"),
4065 (unsigned long) ep->X_add_number);
4066 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
4070 *r = BFD_RELOC_16_PCREL_S2;
4074 gas_assert (ep != NULL);
4075 *r = BFD_RELOC_MIPS_JMP;
4079 INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long));
4083 INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long));
4092 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
4094 append_insn (&insn, ep, r);
4098 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
4101 struct mips_opcode *mo;
4102 struct mips_cl_insn insn;
4103 bfd_reloc_code_real_type r[3]
4104 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
4106 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
4108 gas_assert (strcmp (name, mo->name) == 0);
4110 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
4113 gas_assert (mo->name);
4114 gas_assert (strcmp (name, mo->name) == 0);
4117 create_insn (&insn, mo);
4135 MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int));
4140 MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int));
4144 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int));
4148 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int));
4158 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int));
4165 regno = va_arg (*args, int);
4166 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
4167 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
4188 gas_assert (ep != NULL);
4190 if (ep->X_op != O_constant)
4191 *r = (int) BFD_RELOC_UNUSED + c;
4194 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
4195 FALSE, &insn.insn_opcode, &insn.use_extend,
4198 *r = BFD_RELOC_UNUSED;
4204 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int));
4211 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
4213 append_insn (&insn, ep, r);
4217 * Sign-extend 32-bit mode constants that have bit 31 set and all
4218 * higher bits unset.
4221 normalize_constant_expr (expressionS *ex)
4223 if (ex->X_op == O_constant
4224 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
4225 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
4230 * Sign-extend 32-bit mode address offsets that have bit 31 set and
4231 * all higher bits unset.
4234 normalize_address_expr (expressionS *ex)
4236 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
4237 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
4238 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
4239 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
4244 * Generate a "jalr" instruction with a relocation hint to the called
4245 * function. This occurs in NewABI PIC code.
4248 macro_build_jalr (expressionS *ep)
4252 if (MIPS_JALR_HINT_P (ep))
4257 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
4258 if (MIPS_JALR_HINT_P (ep))
4259 fix_new_exp (frag_now, f - frag_now->fr_literal,
4260 4, ep, FALSE, BFD_RELOC_MIPS_JALR);
4264 * Generate a "lui" instruction.
4267 macro_build_lui (expressionS *ep, int regnum)
4269 expressionS high_expr;
4270 const struct mips_opcode *mo;
4271 struct mips_cl_insn insn;
4272 bfd_reloc_code_real_type r[3]
4273 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
4274 const char *name = "lui";
4275 const char *fmt = "t,u";
4277 gas_assert (! mips_opts.mips16);
4281 if (high_expr.X_op == O_constant)
4283 /* We can compute the instruction now without a relocation entry. */
4284 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
4286 *r = BFD_RELOC_UNUSED;
4290 gas_assert (ep->X_op == O_symbol);
4291 /* _gp_disp is a special case, used from s_cpload.
4292 __gnu_local_gp is used if mips_no_shared. */
4293 gas_assert (mips_pic == NO_PIC
4295 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
4296 || (! mips_in_shared
4297 && strcmp (S_GET_NAME (ep->X_add_symbol),
4298 "__gnu_local_gp") == 0));
4299 *r = BFD_RELOC_HI16_S;
4302 mo = hash_find (op_hash, name);
4303 gas_assert (strcmp (name, mo->name) == 0);
4304 gas_assert (strcmp (fmt, mo->args) == 0);
4305 create_insn (&insn, mo);
4307 insn.insn_opcode = insn.insn_mo->match;
4308 INSERT_OPERAND (RT, insn, regnum);
4309 if (*r == BFD_RELOC_UNUSED)
4311 insn.insn_opcode |= high_expr.X_add_number;
4312 append_insn (&insn, NULL, r);
4315 append_insn (&insn, &high_expr, r);
4318 /* Generate a sequence of instructions to do a load or store from a constant
4319 offset off of a base register (breg) into/from a target register (treg),
4320 using AT if necessary. */
4322 macro_build_ldst_constoffset (expressionS *ep, const char *op,
4323 int treg, int breg, int dbl)
4325 gas_assert (ep->X_op == O_constant);
4327 /* Sign-extending 32-bit constants makes their handling easier. */
4329 normalize_constant_expr (ep);
4331 /* Right now, this routine can only handle signed 32-bit constants. */
4332 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
4333 as_warn (_("operand overflow"));
4335 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
4337 /* Signed 16-bit offset will fit in the op. Easy! */
4338 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
4342 /* 32-bit offset, need multiple instructions and AT, like:
4343 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
4344 addu $tempreg,$tempreg,$breg
4345 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
4346 to handle the complete offset. */
4347 macro_build_lui (ep, AT);
4348 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
4349 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
4352 as_bad (_("Macro used $at after \".set noat\""));
4357 * Generates code to set the $at register to true (one)
4358 * if reg is less than the immediate expression.
4361 set_at (int reg, int unsignedp)
4363 if (imm_expr.X_op == O_constant
4364 && imm_expr.X_add_number >= -0x8000
4365 && imm_expr.X_add_number < 0x8000)
4366 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
4367 AT, reg, BFD_RELOC_LO16);
4370 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4371 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
4375 /* Warn if an expression is not a constant. */
4378 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
4380 if (ex->X_op == O_big)
4381 as_bad (_("unsupported large constant"));
4382 else if (ex->X_op != O_constant)
4383 as_bad (_("Instruction %s requires absolute expression"),
4386 if (HAVE_32BIT_GPRS)
4387 normalize_constant_expr (ex);
4390 /* Count the leading zeroes by performing a binary chop. This is a
4391 bulky bit of source, but performance is a LOT better for the
4392 majority of values than a simple loop to count the bits:
4393 for (lcnt = 0; (lcnt < 32); lcnt++)
4394 if ((v) & (1 << (31 - lcnt)))
4396 However it is not code size friendly, and the gain will drop a bit
4397 on certain cached systems.
4399 #define COUNT_TOP_ZEROES(v) \
4400 (((v) & ~0xffff) == 0 \
4401 ? ((v) & ~0xff) == 0 \
4402 ? ((v) & ~0xf) == 0 \
4403 ? ((v) & ~0x3) == 0 \
4404 ? ((v) & ~0x1) == 0 \
4409 : ((v) & ~0x7) == 0 \
4412 : ((v) & ~0x3f) == 0 \
4413 ? ((v) & ~0x1f) == 0 \
4416 : ((v) & ~0x7f) == 0 \
4419 : ((v) & ~0xfff) == 0 \
4420 ? ((v) & ~0x3ff) == 0 \
4421 ? ((v) & ~0x1ff) == 0 \
4424 : ((v) & ~0x7ff) == 0 \
4427 : ((v) & ~0x3fff) == 0 \
4428 ? ((v) & ~0x1fff) == 0 \
4431 : ((v) & ~0x7fff) == 0 \
4434 : ((v) & ~0xffffff) == 0 \
4435 ? ((v) & ~0xfffff) == 0 \
4436 ? ((v) & ~0x3ffff) == 0 \
4437 ? ((v) & ~0x1ffff) == 0 \
4440 : ((v) & ~0x7ffff) == 0 \
4443 : ((v) & ~0x3fffff) == 0 \
4444 ? ((v) & ~0x1fffff) == 0 \
4447 : ((v) & ~0x7fffff) == 0 \
4450 : ((v) & ~0xfffffff) == 0 \
4451 ? ((v) & ~0x3ffffff) == 0 \
4452 ? ((v) & ~0x1ffffff) == 0 \
4455 : ((v) & ~0x7ffffff) == 0 \
4458 : ((v) & ~0x3fffffff) == 0 \
4459 ? ((v) & ~0x1fffffff) == 0 \
4462 : ((v) & ~0x7fffffff) == 0 \
4467 * This routine generates the least number of instructions necessary to load
4468 * an absolute expression value into a register.
4471 load_register (int reg, expressionS *ep, int dbl)
4474 expressionS hi32, lo32;
4476 if (ep->X_op != O_big)
4478 gas_assert (ep->X_op == O_constant);
4480 /* Sign-extending 32-bit constants makes their handling easier. */
4482 normalize_constant_expr (ep);
4484 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
4486 /* We can handle 16 bit signed values with an addiu to
4487 $zero. No need to ever use daddiu here, since $zero and
4488 the result are always correct in 32 bit mode. */
4489 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4492 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
4494 /* We can handle 16 bit unsigned values with an ori to
4496 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
4499 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
4501 /* 32 bit values require an lui. */
4502 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16);
4503 if ((ep->X_add_number & 0xffff) != 0)
4504 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
4509 /* The value is larger than 32 bits. */
4511 if (!dbl || HAVE_32BIT_GPRS)
4515 sprintf_vma (value, ep->X_add_number);
4516 as_bad (_("Number (0x%s) larger than 32 bits"), value);
4517 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4521 if (ep->X_op != O_big)
4524 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
4525 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
4526 hi32.X_add_number &= 0xffffffff;
4528 lo32.X_add_number &= 0xffffffff;
4532 gas_assert (ep->X_add_number > 2);
4533 if (ep->X_add_number == 3)
4534 generic_bignum[3] = 0;
4535 else if (ep->X_add_number > 4)
4536 as_bad (_("Number larger than 64 bits"));
4537 lo32.X_op = O_constant;
4538 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
4539 hi32.X_op = O_constant;
4540 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
4543 if (hi32.X_add_number == 0)
4548 unsigned long hi, lo;
4550 if (hi32.X_add_number == (offsetT) 0xffffffff)
4552 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
4554 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4557 if (lo32.X_add_number & 0x80000000)
4559 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
4560 if (lo32.X_add_number & 0xffff)
4561 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
4566 /* Check for 16bit shifted constant. We know that hi32 is
4567 non-zero, so start the mask on the first bit of the hi32
4572 unsigned long himask, lomask;
4576 himask = 0xffff >> (32 - shift);
4577 lomask = (0xffff << shift) & 0xffffffff;
4581 himask = 0xffff << (shift - 32);
4584 if ((hi32.X_add_number & ~(offsetT) himask) == 0
4585 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
4589 tmp.X_op = O_constant;
4591 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
4592 | (lo32.X_add_number >> shift));
4594 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
4595 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
4596 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<",
4597 reg, reg, (shift >= 32) ? shift - 32 : shift);
4602 while (shift <= (64 - 16));
4604 /* Find the bit number of the lowest one bit, and store the
4605 shifted value in hi/lo. */
4606 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
4607 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
4611 while ((lo & 1) == 0)
4616 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
4622 while ((hi & 1) == 0)
4631 /* Optimize if the shifted value is a (power of 2) - 1. */
4632 if ((hi == 0 && ((lo + 1) & lo) == 0)
4633 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
4635 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
4640 /* This instruction will set the register to be all
4642 tmp.X_op = O_constant;
4643 tmp.X_add_number = (offsetT) -1;
4644 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4648 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<",
4649 reg, reg, (bit >= 32) ? bit - 32 : bit);
4651 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<",
4652 reg, reg, (shift >= 32) ? shift - 32 : shift);
4657 /* Sign extend hi32 before calling load_register, because we can
4658 generally get better code when we load a sign extended value. */
4659 if ((hi32.X_add_number & 0x80000000) != 0)
4660 hi32.X_add_number |= ~(offsetT) 0xffffffff;
4661 load_register (reg, &hi32, 0);
4664 if ((lo32.X_add_number & 0xffff0000) == 0)
4668 macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0);
4676 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
4678 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
4679 macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0);
4685 macro_build (NULL, "dsll", "d,w,<", reg, freg, 16);
4689 mid16.X_add_number >>= 16;
4690 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
4691 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4694 if ((lo32.X_add_number & 0xffff) != 0)
4695 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
4699 load_delay_nop (void)
4701 if (!gpr_interlocks)
4702 macro_build (NULL, "nop", "");
4705 /* Load an address into a register. */
4708 load_address (int reg, expressionS *ep, int *used_at)
4710 if (ep->X_op != O_constant
4711 && ep->X_op != O_symbol)
4713 as_bad (_("expression too complex"));
4714 ep->X_op = O_constant;
4717 if (ep->X_op == O_constant)
4719 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
4723 if (mips_pic == NO_PIC)
4725 /* If this is a reference to a GP relative symbol, we want
4726 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4728 lui $reg,<sym> (BFD_RELOC_HI16_S)
4729 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4730 If we have an addend, we always use the latter form.
4732 With 64bit address space and a usable $at we want
4733 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4734 lui $at,<sym> (BFD_RELOC_HI16_S)
4735 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4736 daddiu $at,<sym> (BFD_RELOC_LO16)
4740 If $at is already in use, we use a path which is suboptimal
4741 on superscalar processors.
4742 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4743 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4745 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
4747 daddiu $reg,<sym> (BFD_RELOC_LO16)
4749 For GP relative symbols in 64bit address space we can use
4750 the same sequence as in 32bit address space. */
4751 if (HAVE_64BIT_SYMBOLS)
4753 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
4754 && !nopic_need_relax (ep->X_add_symbol, 1))
4756 relax_start (ep->X_add_symbol);
4757 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4758 mips_gp_register, BFD_RELOC_GPREL16);
4762 if (*used_at == 0 && mips_opts.at)
4764 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
4765 macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S);
4766 macro_build (ep, "daddiu", "t,r,j", reg, reg,
4767 BFD_RELOC_MIPS_HIGHER);
4768 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
4769 macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0);
4770 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
4775 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
4776 macro_build (ep, "daddiu", "t,r,j", reg, reg,
4777 BFD_RELOC_MIPS_HIGHER);
4778 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4779 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
4780 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4781 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
4784 if (mips_relax.sequence)
4789 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
4790 && !nopic_need_relax (ep->X_add_symbol, 1))
4792 relax_start (ep->X_add_symbol);
4793 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4794 mips_gp_register, BFD_RELOC_GPREL16);
4797 macro_build_lui (ep, reg);
4798 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
4799 reg, reg, BFD_RELOC_LO16);
4800 if (mips_relax.sequence)
4804 else if (!mips_big_got)
4808 /* If this is a reference to an external symbol, we want
4809 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4811 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4813 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4814 If there is a constant, it must be added in after.
4816 If we have NewABI, we want
4817 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4818 unless we're referencing a global symbol with a non-zero
4819 offset, in which case cst must be added separately. */
4822 if (ep->X_add_number)
4824 ex.X_add_number = ep->X_add_number;
4825 ep->X_add_number = 0;
4826 relax_start (ep->X_add_symbol);
4827 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4828 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4829 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4830 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4831 ex.X_op = O_constant;
4832 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
4833 reg, reg, BFD_RELOC_LO16);
4834 ep->X_add_number = ex.X_add_number;
4837 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4838 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4839 if (mips_relax.sequence)
4844 ex.X_add_number = ep->X_add_number;
4845 ep->X_add_number = 0;
4846 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4847 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4849 relax_start (ep->X_add_symbol);
4851 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4855 if (ex.X_add_number != 0)
4857 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4858 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4859 ex.X_op = O_constant;
4860 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
4861 reg, reg, BFD_RELOC_LO16);
4865 else if (mips_big_got)
4869 /* This is the large GOT case. If this is a reference to an
4870 external symbol, we want
4871 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4873 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
4875 Otherwise, for a reference to a local symbol in old ABI, we want
4876 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4878 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4879 If there is a constant, it must be added in after.
4881 In the NewABI, for local symbols, with or without offsets, we want:
4882 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4883 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4887 ex.X_add_number = ep->X_add_number;
4888 ep->X_add_number = 0;
4889 relax_start (ep->X_add_symbol);
4890 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4891 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4892 reg, reg, mips_gp_register);
4893 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4894 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4895 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4896 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4897 else if (ex.X_add_number)
4899 ex.X_op = O_constant;
4900 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4904 ep->X_add_number = ex.X_add_number;
4906 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4907 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
4908 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4909 BFD_RELOC_MIPS_GOT_OFST);
4914 ex.X_add_number = ep->X_add_number;
4915 ep->X_add_number = 0;
4916 relax_start (ep->X_add_symbol);
4917 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4918 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4919 reg, reg, mips_gp_register);
4920 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4921 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4923 if (reg_needs_delay (mips_gp_register))
4925 /* We need a nop before loading from $gp. This special
4926 check is required because the lui which starts the main
4927 instruction stream does not refer to $gp, and so will not
4928 insert the nop which may be required. */
4929 macro_build (NULL, "nop", "");
4931 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4932 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4934 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4938 if (ex.X_add_number != 0)
4940 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4941 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4942 ex.X_op = O_constant;
4943 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4951 if (!mips_opts.at && *used_at == 1)
4952 as_bad (_("Macro used $at after \".set noat\""));
4955 /* Move the contents of register SOURCE into register DEST. */
4958 move_register (int dest, int source)
4960 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
4964 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4965 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4966 The two alternatives are:
4968 Global symbol Local sybmol
4969 ------------- ------------
4970 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4972 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4974 load_got_offset emits the first instruction and add_got_offset
4975 emits the second for a 16-bit offset or add_got_offset_hilo emits
4976 a sequence to add a 32-bit offset using a scratch register. */
4979 load_got_offset (int dest, expressionS *local)
4984 global.X_add_number = 0;
4986 relax_start (local->X_add_symbol);
4987 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4988 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4990 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4991 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4996 add_got_offset (int dest, expressionS *local)
5000 global.X_op = O_constant;
5001 global.X_op_symbol = NULL;
5002 global.X_add_symbol = NULL;
5003 global.X_add_number = local->X_add_number;
5005 relax_start (local->X_add_symbol);
5006 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
5007 dest, dest, BFD_RELOC_LO16);
5009 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
5014 add_got_offset_hilo (int dest, expressionS *local, int tmp)
5017 int hold_mips_optimize;
5019 global.X_op = O_constant;
5020 global.X_op_symbol = NULL;
5021 global.X_add_symbol = NULL;
5022 global.X_add_number = local->X_add_number;
5024 relax_start (local->X_add_symbol);
5025 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
5027 /* Set mips_optimize around the lui instruction to avoid
5028 inserting an unnecessary nop after the lw. */
5029 hold_mips_optimize = mips_optimize;
5031 macro_build_lui (&global, tmp);
5032 mips_optimize = hold_mips_optimize;
5033 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
5036 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
5041 * This routine implements the seemingly endless macro or synthesized
5042 * instructions and addressing modes in the mips assembly language. Many
5043 * of these macros are simple and are similar to each other. These could
5044 * probably be handled by some kind of table or grammar approach instead of
5045 * this verbose method. Others are not simple macros but are more like
5046 * optimizing code generation.
5047 * One interesting optimization is when several store macros appear
5048 * consecutively that would load AT with the upper half of the same address.
5049 * The ensuing load upper instructions are ommited. This implies some kind
5050 * of global optimization. We currently only optimize within a single macro.
5051 * For many of the load and store macros if the address is specified as a
5052 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
5053 * first load register 'at' with zero and use it as the base register. The
5054 * mips assembler simply uses register $zero. Just one tiny optimization
5058 macro (struct mips_cl_insn *ip)
5060 unsigned int treg, sreg, dreg, breg;
5061 unsigned int tempreg;
5076 bfd_reloc_code_real_type r;
5077 int hold_mips_optimize;
5079 gas_assert (! mips_opts.mips16);
5081 treg = EXTRACT_OPERAND (RT, *ip);
5082 dreg = EXTRACT_OPERAND (RD, *ip);
5083 sreg = breg = EXTRACT_OPERAND (RS, *ip);
5084 mask = ip->insn_mo->mask;
5086 expr1.X_op = O_constant;
5087 expr1.X_op_symbol = NULL;
5088 expr1.X_add_symbol = NULL;
5089 expr1.X_add_number = 1;
5103 expr1.X_add_number = 8;
5104 macro_build (&expr1, "bgez", "s,p", sreg);
5106 macro_build (NULL, "nop", "");
5108 move_register (dreg, sreg);
5109 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
5132 if (imm_expr.X_op == O_constant
5133 && imm_expr.X_add_number >= -0x8000
5134 && imm_expr.X_add_number < 0x8000)
5136 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
5140 load_register (AT, &imm_expr, dbl);
5141 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
5160 if (imm_expr.X_op == O_constant
5161 && imm_expr.X_add_number >= 0
5162 && imm_expr.X_add_number < 0x10000)
5164 if (mask != M_NOR_I)
5165 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
5168 macro_build (&imm_expr, "ori", "t,r,i",
5169 treg, sreg, BFD_RELOC_LO16);
5170 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
5176 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5177 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
5181 switch (imm_expr.X_add_number)
5184 macro_build (NULL, "nop", "");
5187 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
5190 macro_build (NULL, "balign", "t,s,2", treg, sreg,
5191 (int) imm_expr.X_add_number);
5210 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5212 macro_build (&offset_expr, s, "s,t,p", sreg, ZERO);
5216 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5217 macro_build (&offset_expr, s, "s,t,p", sreg, AT);
5225 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
5230 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg);
5234 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
5235 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5241 /* Check for > max integer. */
5242 maxnum = 0x7fffffff;
5243 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5250 if (imm_expr.X_op == O_constant
5251 && imm_expr.X_add_number >= maxnum
5252 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5255 /* Result is always false. */
5257 macro_build (NULL, "nop", "");
5259 macro_build (&offset_expr, "bnel", "s,t,p", ZERO, ZERO);
5262 if (imm_expr.X_op != O_constant)
5263 as_bad (_("Unsupported large constant"));
5264 ++imm_expr.X_add_number;
5268 if (mask == M_BGEL_I)
5270 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5272 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
5275 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5277 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
5280 maxnum = 0x7fffffff;
5281 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5288 maxnum = - maxnum - 1;
5289 if (imm_expr.X_op == O_constant
5290 && imm_expr.X_add_number <= maxnum
5291 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5294 /* result is always true */
5295 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
5296 macro_build (&offset_expr, "b", "p");
5301 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5311 macro_build (&offset_expr, likely ? "beql" : "beq",
5312 "s,t,p", ZERO, treg);
5316 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
5317 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5325 && imm_expr.X_op == O_constant
5326 && imm_expr.X_add_number == -1))
5328 if (imm_expr.X_op != O_constant)
5329 as_bad (_("Unsupported large constant"));
5330 ++imm_expr.X_add_number;
5334 if (mask == M_BGEUL_I)
5336 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5338 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5340 macro_build (&offset_expr, likely ? "bnel" : "bne",
5341 "s,t,p", sreg, ZERO);
5346 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5354 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
5359 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg);
5363 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
5364 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5372 macro_build (&offset_expr, likely ? "bnel" : "bne",
5373 "s,t,p", sreg, ZERO);
5379 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
5380 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5388 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
5393 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg);
5397 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
5398 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5404 maxnum = 0x7fffffff;
5405 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5412 if (imm_expr.X_op == O_constant
5413 && imm_expr.X_add_number >= maxnum
5414 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5416 if (imm_expr.X_op != O_constant)
5417 as_bad (_("Unsupported large constant"));
5418 ++imm_expr.X_add_number;
5422 if (mask == M_BLTL_I)
5424 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5426 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
5429 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5431 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
5436 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5444 macro_build (&offset_expr, likely ? "beql" : "beq",
5445 "s,t,p", sreg, ZERO);
5451 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
5452 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5460 && imm_expr.X_op == O_constant
5461 && imm_expr.X_add_number == -1))
5463 if (imm_expr.X_op != O_constant)
5464 as_bad (_("Unsupported large constant"));
5465 ++imm_expr.X_add_number;
5469 if (mask == M_BLTUL_I)
5471 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5473 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5475 macro_build (&offset_expr, likely ? "beql" : "beq",
5476 "s,t,p", sreg, ZERO);
5481 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5489 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
5494 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg);
5498 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
5499 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5509 macro_build (&offset_expr, likely ? "bnel" : "bne",
5510 "s,t,p", ZERO, treg);
5514 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
5515 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5520 /* Use unsigned arithmetic. */
5524 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5526 as_bad (_("Unsupported large constant"));
5531 pos = imm_expr.X_add_number;
5532 size = imm2_expr.X_add_number;
5537 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
5540 if (size == 0 || size > 64 || (pos + size - 1) > 63)
5542 as_bad (_("Improper extract size (%lu, position %lu)"),
5543 (unsigned long) size, (unsigned long) pos);
5547 if (size <= 32 && pos < 32)
5552 else if (size <= 32)
5562 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
5569 /* Use unsigned arithmetic. */
5573 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5575 as_bad (_("Unsupported large constant"));
5580 pos = imm_expr.X_add_number;
5581 size = imm2_expr.X_add_number;
5586 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
5589 if (size == 0 || size > 64 || (pos + size - 1) > 63)
5591 as_bad (_("Improper insert size (%lu, position %lu)"),
5592 (unsigned long) size, (unsigned long) pos);
5596 if (pos < 32 && (pos + size - 1) < 32)
5611 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
5612 (int) (pos + size - 1));
5628 as_warn (_("Divide by zero."));
5630 macro_build (NULL, "teq", "s,t,q", ZERO, ZERO, 7);
5632 macro_build (NULL, "break", "c", 7);
5639 macro_build (NULL, "teq", "s,t,q", treg, ZERO, 7);
5640 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
5644 expr1.X_add_number = 8;
5645 macro_build (&expr1, "bne", "s,t,p", treg, ZERO);
5646 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
5647 macro_build (NULL, "break", "c", 7);
5649 expr1.X_add_number = -1;
5651 load_register (AT, &expr1, dbl);
5652 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
5653 macro_build (&expr1, "bne", "s,t,p", treg, AT);
5656 expr1.X_add_number = 1;
5657 load_register (AT, &expr1, dbl);
5658 macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31);
5662 expr1.X_add_number = 0x80000000;
5663 macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16);
5667 macro_build (NULL, "teq", "s,t,q", sreg, AT, 6);
5668 /* We want to close the noreorder block as soon as possible, so
5669 that later insns are available for delay slot filling. */
5674 expr1.X_add_number = 8;
5675 macro_build (&expr1, "bne", "s,t,p", sreg, AT);
5676 macro_build (NULL, "nop", "");
5678 /* We want to close the noreorder block as soon as possible, so
5679 that later insns are available for delay slot filling. */
5682 macro_build (NULL, "break", "c", 6);
5684 macro_build (NULL, s, "d", dreg);
5723 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5725 as_warn (_("Divide by zero."));
5727 macro_build (NULL, "teq", "s,t,q", ZERO, ZERO, 7);
5729 macro_build (NULL, "break", "c", 7);
5732 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5734 if (strcmp (s2, "mflo") == 0)
5735 move_register (dreg, sreg);
5737 move_register (dreg, ZERO);
5740 if (imm_expr.X_op == O_constant
5741 && imm_expr.X_add_number == -1
5742 && s[strlen (s) - 1] != 'u')
5744 if (strcmp (s2, "mflo") == 0)
5746 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
5749 move_register (dreg, ZERO);
5754 load_register (AT, &imm_expr, dbl);
5755 macro_build (NULL, s, "z,s,t", sreg, AT);
5756 macro_build (NULL, s2, "d", dreg);
5778 macro_build (NULL, "teq", "s,t,q", treg, ZERO, 7);
5779 macro_build (NULL, s, "z,s,t", sreg, treg);
5780 /* We want to close the noreorder block as soon as possible, so
5781 that later insns are available for delay slot filling. */
5786 expr1.X_add_number = 8;
5787 macro_build (&expr1, "bne", "s,t,p", treg, ZERO);
5788 macro_build (NULL, s, "z,s,t", sreg, treg);
5790 /* We want to close the noreorder block as soon as possible, so
5791 that later insns are available for delay slot filling. */
5793 macro_build (NULL, "break", "c", 7);
5795 macro_build (NULL, s2, "d", dreg);
5807 /* Load the address of a symbol into a register. If breg is not
5808 zero, we then add a base register to it. */
5810 if (dbl && HAVE_32BIT_GPRS)
5811 as_warn (_("dla used to load 32-bit register"));
5813 if (!dbl && HAVE_64BIT_OBJECTS)
5814 as_warn (_("la used to load 64-bit address"));
5816 if (offset_expr.X_op == O_constant
5817 && offset_expr.X_add_number >= -0x8000
5818 && offset_expr.X_add_number < 0x8000)
5820 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
5821 "t,r,j", treg, sreg, BFD_RELOC_LO16);
5825 if (mips_opts.at && (treg == breg))
5835 if (offset_expr.X_op != O_symbol
5836 && offset_expr.X_op != O_constant)
5838 as_bad (_("Expression too complex"));
5839 offset_expr.X_op = O_constant;
5842 if (offset_expr.X_op == O_constant)
5843 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
5844 else if (mips_pic == NO_PIC)
5846 /* If this is a reference to a GP relative symbol, we want
5847 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5849 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5850 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5851 If we have a constant, we need two instructions anyhow,
5852 so we may as well always use the latter form.
5854 With 64bit address space and a usable $at we want
5855 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5856 lui $at,<sym> (BFD_RELOC_HI16_S)
5857 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5858 daddiu $at,<sym> (BFD_RELOC_LO16)
5860 daddu $tempreg,$tempreg,$at
5862 If $at is already in use, we use a path which is suboptimal
5863 on superscalar processors.
5864 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5865 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5867 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5869 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
5871 For GP relative symbols in 64bit address space we can use
5872 the same sequence as in 32bit address space. */
5873 if (HAVE_64BIT_SYMBOLS)
5875 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5876 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5878 relax_start (offset_expr.X_add_symbol);
5879 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5880 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5884 if (used_at == 0 && mips_opts.at)
5886 macro_build (&offset_expr, "lui", "t,u",
5887 tempreg, BFD_RELOC_MIPS_HIGHEST);
5888 macro_build (&offset_expr, "lui", "t,u",
5889 AT, BFD_RELOC_HI16_S);
5890 macro_build (&offset_expr, "daddiu", "t,r,j",
5891 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5892 macro_build (&offset_expr, "daddiu", "t,r,j",
5893 AT, AT, BFD_RELOC_LO16);
5894 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
5895 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
5900 macro_build (&offset_expr, "lui", "t,u",
5901 tempreg, BFD_RELOC_MIPS_HIGHEST);
5902 macro_build (&offset_expr, "daddiu", "t,r,j",
5903 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5904 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5905 macro_build (&offset_expr, "daddiu", "t,r,j",
5906 tempreg, tempreg, BFD_RELOC_HI16_S);
5907 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5908 macro_build (&offset_expr, "daddiu", "t,r,j",
5909 tempreg, tempreg, BFD_RELOC_LO16);
5912 if (mips_relax.sequence)
5917 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5918 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5920 relax_start (offset_expr.X_add_symbol);
5921 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5922 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5925 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
5926 as_bad (_("Offset too large"));
5927 macro_build_lui (&offset_expr, tempreg);
5928 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5929 tempreg, tempreg, BFD_RELOC_LO16);
5930 if (mips_relax.sequence)
5934 else if (!mips_big_got && !HAVE_NEWABI)
5936 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5938 /* If this is a reference to an external symbol, and there
5939 is no constant, we want
5940 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5941 or for lca or if tempreg is PIC_CALL_REG
5942 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5943 For a local symbol, we want
5944 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5946 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5948 If we have a small constant, and this is a reference to
5949 an external symbol, we want
5950 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5952 addiu $tempreg,$tempreg,<constant>
5953 For a local symbol, we want the same instruction
5954 sequence, but we output a BFD_RELOC_LO16 reloc on the
5957 If we have a large constant, and this is a reference to
5958 an external symbol, we want
5959 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5960 lui $at,<hiconstant>
5961 addiu $at,$at,<loconstant>
5962 addu $tempreg,$tempreg,$at
5963 For a local symbol, we want the same instruction
5964 sequence, but we output a BFD_RELOC_LO16 reloc on the
5968 if (offset_expr.X_add_number == 0)
5970 if (mips_pic == SVR4_PIC
5972 && (call || tempreg == PIC_CALL_REG))
5973 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
5975 relax_start (offset_expr.X_add_symbol);
5976 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5977 lw_reloc_type, mips_gp_register);
5980 /* We're going to put in an addu instruction using
5981 tempreg, so we may as well insert the nop right
5986 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5987 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
5989 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5990 tempreg, tempreg, BFD_RELOC_LO16);
5992 /* FIXME: If breg == 0, and the next instruction uses
5993 $tempreg, then if this variant case is used an extra
5994 nop will be generated. */
5996 else if (offset_expr.X_add_number >= -0x8000
5997 && offset_expr.X_add_number < 0x8000)
5999 load_got_offset (tempreg, &offset_expr);
6001 add_got_offset (tempreg, &offset_expr);
6005 expr1.X_add_number = offset_expr.X_add_number;
6006 offset_expr.X_add_number =
6007 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
6008 load_got_offset (tempreg, &offset_expr);
6009 offset_expr.X_add_number = expr1.X_add_number;
6010 /* If we are going to add in a base register, and the
6011 target register and the base register are the same,
6012 then we are using AT as a temporary register. Since
6013 we want to load the constant into AT, we add our
6014 current AT (from the global offset table) and the
6015 register into the register now, and pretend we were
6016 not using a base register. */
6020 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6025 add_got_offset_hilo (tempreg, &offset_expr, AT);
6029 else if (!mips_big_got && HAVE_NEWABI)
6031 int add_breg_early = 0;
6033 /* If this is a reference to an external, and there is no
6034 constant, or local symbol (*), with or without a
6036 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6037 or for lca or if tempreg is PIC_CALL_REG
6038 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
6040 If we have a small constant, and this is a reference to
6041 an external symbol, we want
6042 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6043 addiu $tempreg,$tempreg,<constant>
6045 If we have a large constant, and this is a reference to
6046 an external symbol, we want
6047 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6048 lui $at,<hiconstant>
6049 addiu $at,$at,<loconstant>
6050 addu $tempreg,$tempreg,$at
6052 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
6053 local symbols, even though it introduces an additional
6056 if (offset_expr.X_add_number)
6058 expr1.X_add_number = offset_expr.X_add_number;
6059 offset_expr.X_add_number = 0;
6061 relax_start (offset_expr.X_add_symbol);
6062 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6063 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6065 if (expr1.X_add_number >= -0x8000
6066 && expr1.X_add_number < 0x8000)
6068 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
6069 tempreg, tempreg, BFD_RELOC_LO16);
6071 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
6073 /* If we are going to add in a base register, and the
6074 target register and the base register are the same,
6075 then we are using AT as a temporary register. Since
6076 we want to load the constant into AT, we add our
6077 current AT (from the global offset table) and the
6078 register into the register now, and pretend we were
6079 not using a base register. */
6084 gas_assert (tempreg == AT);
6085 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6091 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
6092 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6098 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
6101 offset_expr.X_add_number = expr1.X_add_number;
6103 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6104 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6107 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6108 treg, tempreg, breg);
6114 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
6116 relax_start (offset_expr.X_add_symbol);
6117 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6118 BFD_RELOC_MIPS_CALL16, mips_gp_register);
6120 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6121 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6126 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6127 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6130 else if (mips_big_got && !HAVE_NEWABI)
6133 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
6134 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
6135 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6137 /* This is the large GOT case. If this is a reference to an
6138 external symbol, and there is no constant, we want
6139 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6140 addu $tempreg,$tempreg,$gp
6141 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6142 or for lca or if tempreg is PIC_CALL_REG
6143 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6144 addu $tempreg,$tempreg,$gp
6145 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
6146 For a local symbol, we want
6147 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6149 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6151 If we have a small constant, and this is a reference to
6152 an external symbol, we want
6153 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6154 addu $tempreg,$tempreg,$gp
6155 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6157 addiu $tempreg,$tempreg,<constant>
6158 For a local symbol, we want
6159 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6161 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
6163 If we have a large constant, and this is a reference to
6164 an external symbol, we want
6165 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6166 addu $tempreg,$tempreg,$gp
6167 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6168 lui $at,<hiconstant>
6169 addiu $at,$at,<loconstant>
6170 addu $tempreg,$tempreg,$at
6171 For a local symbol, we want
6172 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6173 lui $at,<hiconstant>
6174 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
6175 addu $tempreg,$tempreg,$at
6178 expr1.X_add_number = offset_expr.X_add_number;
6179 offset_expr.X_add_number = 0;
6180 relax_start (offset_expr.X_add_symbol);
6181 gpdelay = reg_needs_delay (mips_gp_register);
6182 if (expr1.X_add_number == 0 && breg == 0
6183 && (call || tempreg == PIC_CALL_REG))
6185 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
6186 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
6188 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
6189 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6190 tempreg, tempreg, mips_gp_register);
6191 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6192 tempreg, lw_reloc_type, tempreg);
6193 if (expr1.X_add_number == 0)
6197 /* We're going to put in an addu instruction using
6198 tempreg, so we may as well insert the nop right
6203 else if (expr1.X_add_number >= -0x8000
6204 && expr1.X_add_number < 0x8000)
6207 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
6208 tempreg, tempreg, BFD_RELOC_LO16);
6212 /* If we are going to add in a base register, and the
6213 target register and the base register are the same,
6214 then we are using AT as a temporary register. Since
6215 we want to load the constant into AT, we add our
6216 current AT (from the global offset table) and the
6217 register into the register now, and pretend we were
6218 not using a base register. */
6223 gas_assert (tempreg == AT);
6225 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6230 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
6231 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
6235 offset_expr.X_add_number =
6236 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000;
6241 /* This is needed because this instruction uses $gp, but
6242 the first instruction on the main stream does not. */
6243 macro_build (NULL, "nop", "");
6246 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6247 local_reloc_type, mips_gp_register);
6248 if (expr1.X_add_number >= -0x8000
6249 && expr1.X_add_number < 0x8000)
6252 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6253 tempreg, tempreg, BFD_RELOC_LO16);
6254 /* FIXME: If add_number is 0, and there was no base
6255 register, the external symbol case ended with a load,
6256 so if the symbol turns out to not be external, and
6257 the next instruction uses tempreg, an unnecessary nop
6258 will be inserted. */
6264 /* We must add in the base register now, as in the
6265 external symbol case. */
6266 gas_assert (tempreg == AT);
6268 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6271 /* We set breg to 0 because we have arranged to add
6272 it in in both cases. */
6276 macro_build_lui (&expr1, AT);
6277 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6278 AT, AT, BFD_RELOC_LO16);
6279 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6280 tempreg, tempreg, AT);
6285 else if (mips_big_got && HAVE_NEWABI)
6287 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
6288 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
6289 int add_breg_early = 0;
6291 /* This is the large GOT case. If this is a reference to an
6292 external symbol, and there is no constant, we want
6293 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6294 add $tempreg,$tempreg,$gp
6295 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6296 or for lca or if tempreg is PIC_CALL_REG
6297 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6298 add $tempreg,$tempreg,$gp
6299 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
6301 If we have a small constant, and this is a reference to
6302 an external symbol, we want
6303 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6304 add $tempreg,$tempreg,$gp
6305 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6306 addi $tempreg,$tempreg,<constant>
6308 If we have a large constant, and this is a reference to
6309 an external symbol, we want
6310 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6311 addu $tempreg,$tempreg,$gp
6312 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6313 lui $at,<hiconstant>
6314 addi $at,$at,<loconstant>
6315 add $tempreg,$tempreg,$at
6317 If we have NewABI, and we know it's a local symbol, we want
6318 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6319 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6320 otherwise we have to resort to GOT_HI16/GOT_LO16. */
6322 relax_start (offset_expr.X_add_symbol);
6324 expr1.X_add_number = offset_expr.X_add_number;
6325 offset_expr.X_add_number = 0;
6327 if (expr1.X_add_number == 0 && breg == 0
6328 && (call || tempreg == PIC_CALL_REG))
6330 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
6331 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
6333 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
6334 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6335 tempreg, tempreg, mips_gp_register);
6336 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6337 tempreg, lw_reloc_type, tempreg);
6339 if (expr1.X_add_number == 0)
6341 else if (expr1.X_add_number >= -0x8000
6342 && expr1.X_add_number < 0x8000)
6344 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
6345 tempreg, tempreg, BFD_RELOC_LO16);
6347 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
6349 /* If we are going to add in a base register, and the
6350 target register and the base register are the same,
6351 then we are using AT as a temporary register. Since
6352 we want to load the constant into AT, we add our
6353 current AT (from the global offset table) and the
6354 register into the register now, and pretend we were
6355 not using a base register. */
6360 gas_assert (tempreg == AT);
6361 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6367 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
6368 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
6373 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
6376 offset_expr.X_add_number = expr1.X_add_number;
6377 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6378 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6379 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6380 tempreg, BFD_RELOC_MIPS_GOT_OFST);
6383 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6384 treg, tempreg, breg);
6394 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
6399 unsigned long temp = (treg << 16) | (0x01);
6400 macro_build (NULL, "c2", "C", temp);
6406 unsigned long temp = (0x02);
6407 macro_build (NULL, "c2", "C", temp);
6413 unsigned long temp = (treg << 16) | (0x02);
6414 macro_build (NULL, "c2", "C", temp);
6419 macro_build (NULL, "c2", "C", 3);
6424 unsigned long temp = (treg << 16) | 0x03;
6425 macro_build (NULL, "c2", "C", temp);
6430 /* The j instruction may not be used in PIC code, since it
6431 requires an absolute address. We convert it to a b
6433 if (mips_pic == NO_PIC)
6434 macro_build (&offset_expr, "j", "a");
6436 macro_build (&offset_expr, "b", "p");
6439 /* The jal instructions must be handled as macros because when
6440 generating PIC code they expand to multi-instruction
6441 sequences. Normally they are simple instructions. */
6446 if (mips_pic == NO_PIC)
6447 macro_build (NULL, "jalr", "d,s", dreg, sreg);
6450 if (sreg != PIC_CALL_REG)
6451 as_warn (_("MIPS PIC call to register other than $25"));
6453 macro_build (NULL, "jalr", "d,s", dreg, sreg);
6454 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
6456 if (mips_cprestore_offset < 0)
6457 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6460 if (!mips_frame_reg_valid)
6462 as_warn (_("No .frame pseudo-op used in PIC code"));
6463 /* Quiet this warning. */
6464 mips_frame_reg_valid = 1;
6466 if (!mips_cprestore_valid)
6468 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6469 /* Quiet this warning. */
6470 mips_cprestore_valid = 1;
6472 if (mips_opts.noreorder)
6473 macro_build (NULL, "nop", "");
6474 expr1.X_add_number = mips_cprestore_offset;
6475 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
6478 HAVE_64BIT_ADDRESSES);
6486 if (mips_pic == NO_PIC)
6487 macro_build (&offset_expr, "jal", "a");
6488 else if (mips_pic == SVR4_PIC)
6490 /* If this is a reference to an external symbol, and we are
6491 using a small GOT, we want
6492 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
6496 lw $gp,cprestore($sp)
6497 The cprestore value is set using the .cprestore
6498 pseudo-op. If we are using a big GOT, we want
6499 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6501 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
6505 lw $gp,cprestore($sp)
6506 If the symbol is not external, we want
6507 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6509 addiu $25,$25,<sym> (BFD_RELOC_LO16)
6512 lw $gp,cprestore($sp)
6514 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
6515 sequences above, minus nops, unless the symbol is local,
6516 which enables us to use GOT_PAGE/GOT_OFST (big got) or
6522 relax_start (offset_expr.X_add_symbol);
6523 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6524 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
6527 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6528 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
6534 relax_start (offset_expr.X_add_symbol);
6535 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
6536 BFD_RELOC_MIPS_CALL_HI16);
6537 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
6538 PIC_CALL_REG, mips_gp_register);
6539 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6540 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
6543 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6544 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
6546 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6547 PIC_CALL_REG, PIC_CALL_REG,
6548 BFD_RELOC_MIPS_GOT_OFST);
6552 macro_build_jalr (&offset_expr);
6556 relax_start (offset_expr.X_add_symbol);
6559 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6560 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
6569 gpdelay = reg_needs_delay (mips_gp_register);
6570 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
6571 BFD_RELOC_MIPS_CALL_HI16);
6572 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
6573 PIC_CALL_REG, mips_gp_register);
6574 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6575 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
6580 macro_build (NULL, "nop", "");
6582 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6583 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
6586 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6587 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
6589 macro_build_jalr (&offset_expr);
6591 if (mips_cprestore_offset < 0)
6592 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6595 if (!mips_frame_reg_valid)
6597 as_warn (_("No .frame pseudo-op used in PIC code"));
6598 /* Quiet this warning. */
6599 mips_frame_reg_valid = 1;
6601 if (!mips_cprestore_valid)
6603 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6604 /* Quiet this warning. */
6605 mips_cprestore_valid = 1;
6607 if (mips_opts.noreorder)
6608 macro_build (NULL, "nop", "");
6609 expr1.X_add_number = mips_cprestore_offset;
6610 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
6613 HAVE_64BIT_ADDRESSES);
6617 else if (mips_pic == VXWORKS_PIC)
6618 as_bad (_("Non-PIC jump used in PIC library"));
6641 /* Itbl support may require additional care here. */
6646 /* Itbl support may require additional care here. */
6651 /* Itbl support may require additional care here. */
6656 /* Itbl support may require additional care here. */
6669 /* Itbl support may require additional care here. */
6674 /* Itbl support may require additional care here. */
6679 /* Itbl support may require additional care here. */
6699 if (breg == treg || coproc || lr)
6720 /* Itbl support may require additional care here. */
6725 /* Itbl support may require additional care here. */
6730 /* Itbl support may require additional care here. */
6735 /* Itbl support may require additional care here. */
6759 /* Itbl support may require additional care here. */
6763 /* Itbl support may require additional care here. */
6768 /* Itbl support may require additional care here. */
6781 && NO_ISA_COP (mips_opts.arch)
6782 && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0)
6784 as_bad (_("Opcode not supported on this processor: %s"),
6785 mips_cpu_info_from_arch (mips_opts.arch)->name);
6789 /* Itbl support may require additional care here. */
6790 if (mask == M_LWC1_AB
6791 || mask == M_SWC1_AB
6792 || mask == M_LDC1_AB
6793 || mask == M_SDC1_AB
6797 else if (mask == M_CACHE_AB || mask == M_PREF_AB)
6804 if (offset_expr.X_op != O_constant
6805 && offset_expr.X_op != O_symbol)
6807 as_bad (_("Expression too complex"));
6808 offset_expr.X_op = O_constant;
6811 if (HAVE_32BIT_ADDRESSES
6812 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
6816 sprintf_vma (value, offset_expr.X_add_number);
6817 as_bad (_("Number (0x%s) larger than 32 bits"), value);
6820 /* A constant expression in PIC code can be handled just as it
6821 is in non PIC code. */
6822 if (offset_expr.X_op == O_constant)
6824 expr1.X_add_number = offset_expr.X_add_number;
6825 normalize_address_expr (&expr1);
6826 if (!IS_SEXT_16BIT_NUM (expr1.X_add_number))
6828 expr1.X_add_number = ((expr1.X_add_number + 0x8000)
6829 & ~(bfd_vma) 0xffff);
6830 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
6832 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6833 tempreg, tempreg, breg);
6836 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg);
6838 else if (mips_pic == NO_PIC)
6840 /* If this is a reference to a GP relative symbol, and there
6841 is no base register, we want
6842 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6843 Otherwise, if there is no base register, we want
6844 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6845 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6846 If we have a constant, we need two instructions anyhow,
6847 so we always use the latter form.
6849 If we have a base register, and this is a reference to a
6850 GP relative symbol, we want
6851 addu $tempreg,$breg,$gp
6852 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6854 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6855 addu $tempreg,$tempreg,$breg
6856 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6857 With a constant we always use the latter case.
6859 With 64bit address space and no base register and $at usable,
6861 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6862 lui $at,<sym> (BFD_RELOC_HI16_S)
6863 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6866 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6867 If we have a base register, we want
6868 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6869 lui $at,<sym> (BFD_RELOC_HI16_S)
6870 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6874 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6876 Without $at we can't generate the optimal path for superscalar
6877 processors here since this would require two temporary registers.
6878 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6879 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6881 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6883 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6884 If we have a base register, we want
6885 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6886 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6888 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6890 daddu $tempreg,$tempreg,$breg
6891 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6893 For GP relative symbols in 64bit address space we can use
6894 the same sequence as in 32bit address space. */
6895 if (HAVE_64BIT_SYMBOLS)
6897 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6898 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6900 relax_start (offset_expr.X_add_symbol);
6903 macro_build (&offset_expr, s, fmt, treg,
6904 BFD_RELOC_GPREL16, mips_gp_register);
6908 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6909 tempreg, breg, mips_gp_register);
6910 macro_build (&offset_expr, s, fmt, treg,
6911 BFD_RELOC_GPREL16, tempreg);
6916 if (used_at == 0 && mips_opts.at)
6918 macro_build (&offset_expr, "lui", "t,u", tempreg,
6919 BFD_RELOC_MIPS_HIGHEST);
6920 macro_build (&offset_expr, "lui", "t,u", AT,
6922 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6923 tempreg, BFD_RELOC_MIPS_HIGHER);
6925 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
6926 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
6927 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
6928 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
6934 macro_build (&offset_expr, "lui", "t,u", tempreg,
6935 BFD_RELOC_MIPS_HIGHEST);
6936 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6937 tempreg, BFD_RELOC_MIPS_HIGHER);
6938 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6939 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6940 tempreg, BFD_RELOC_HI16_S);
6941 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6943 macro_build (NULL, "daddu", "d,v,t",
6944 tempreg, tempreg, breg);
6945 macro_build (&offset_expr, s, fmt, treg,
6946 BFD_RELOC_LO16, tempreg);
6949 if (mips_relax.sequence)
6956 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6957 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6959 relax_start (offset_expr.X_add_symbol);
6960 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
6964 macro_build_lui (&offset_expr, tempreg);
6965 macro_build (&offset_expr, s, fmt, treg,
6966 BFD_RELOC_LO16, tempreg);
6967 if (mips_relax.sequence)
6972 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6973 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6975 relax_start (offset_expr.X_add_symbol);
6976 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6977 tempreg, breg, mips_gp_register);
6978 macro_build (&offset_expr, s, fmt, treg,
6979 BFD_RELOC_GPREL16, tempreg);
6982 macro_build_lui (&offset_expr, tempreg);
6983 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6984 tempreg, tempreg, breg);
6985 macro_build (&offset_expr, s, fmt, treg,
6986 BFD_RELOC_LO16, tempreg);
6987 if (mips_relax.sequence)
6991 else if (!mips_big_got)
6993 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6995 /* If this is a reference to an external symbol, we want
6996 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6998 <op> $treg,0($tempreg)
7000 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7002 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7003 <op> $treg,0($tempreg)
7006 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7007 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
7009 If there is a base register, we add it to $tempreg before
7010 the <op>. If there is a constant, we stick it in the
7011 <op> instruction. We don't handle constants larger than
7012 16 bits, because we have no way to load the upper 16 bits
7013 (actually, we could handle them for the subset of cases
7014 in which we are not using $at). */
7015 gas_assert (offset_expr.X_op == O_symbol);
7018 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7019 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
7021 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7022 tempreg, tempreg, breg);
7023 macro_build (&offset_expr, s, fmt, treg,
7024 BFD_RELOC_MIPS_GOT_OFST, tempreg);
7027 expr1.X_add_number = offset_expr.X_add_number;
7028 offset_expr.X_add_number = 0;
7029 if (expr1.X_add_number < -0x8000
7030 || expr1.X_add_number >= 0x8000)
7031 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7032 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7033 lw_reloc_type, mips_gp_register);
7035 relax_start (offset_expr.X_add_symbol);
7037 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
7038 tempreg, BFD_RELOC_LO16);
7041 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7042 tempreg, tempreg, breg);
7043 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
7045 else if (mips_big_got && !HAVE_NEWABI)
7049 /* If this is a reference to an external symbol, we want
7050 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7051 addu $tempreg,$tempreg,$gp
7052 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7053 <op> $treg,0($tempreg)
7055 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7057 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7058 <op> $treg,0($tempreg)
7059 If there is a base register, we add it to $tempreg before
7060 the <op>. If there is a constant, we stick it in the
7061 <op> instruction. We don't handle constants larger than
7062 16 bits, because we have no way to load the upper 16 bits
7063 (actually, we could handle them for the subset of cases
7064 in which we are not using $at). */
7065 gas_assert (offset_expr.X_op == O_symbol);
7066 expr1.X_add_number = offset_expr.X_add_number;
7067 offset_expr.X_add_number = 0;
7068 if (expr1.X_add_number < -0x8000
7069 || expr1.X_add_number >= 0x8000)
7070 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7071 gpdelay = reg_needs_delay (mips_gp_register);
7072 relax_start (offset_expr.X_add_symbol);
7073 macro_build (&offset_expr, "lui", "t,u", tempreg,
7074 BFD_RELOC_MIPS_GOT_HI16);
7075 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
7077 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7078 BFD_RELOC_MIPS_GOT_LO16, tempreg);
7081 macro_build (NULL, "nop", "");
7082 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7083 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7085 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
7086 tempreg, BFD_RELOC_LO16);
7090 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7091 tempreg, tempreg, breg);
7092 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
7094 else if (mips_big_got && HAVE_NEWABI)
7096 /* If this is a reference to an external symbol, we want
7097 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7098 add $tempreg,$tempreg,$gp
7099 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7100 <op> $treg,<ofst>($tempreg)
7101 Otherwise, for local symbols, we want:
7102 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7103 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
7104 gas_assert (offset_expr.X_op == O_symbol);
7105 expr1.X_add_number = offset_expr.X_add_number;
7106 offset_expr.X_add_number = 0;
7107 if (expr1.X_add_number < -0x8000
7108 || expr1.X_add_number >= 0x8000)
7109 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7110 relax_start (offset_expr.X_add_symbol);
7111 macro_build (&offset_expr, "lui", "t,u", tempreg,
7112 BFD_RELOC_MIPS_GOT_HI16);
7113 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
7115 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7116 BFD_RELOC_MIPS_GOT_LO16, tempreg);
7118 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7119 tempreg, tempreg, breg);
7120 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
7123 offset_expr.X_add_number = expr1.X_add_number;
7124 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7125 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
7127 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7128 tempreg, tempreg, breg);
7129 macro_build (&offset_expr, s, fmt, treg,
7130 BFD_RELOC_MIPS_GOT_OFST, tempreg);
7140 load_register (treg, &imm_expr, 0);
7144 load_register (treg, &imm_expr, 1);
7148 if (imm_expr.X_op == O_constant)
7151 load_register (AT, &imm_expr, 0);
7152 macro_build (NULL, "mtc1", "t,G", AT, treg);
7157 gas_assert (offset_expr.X_op == O_symbol
7158 && strcmp (segment_name (S_GET_SEGMENT
7159 (offset_expr.X_add_symbol)),
7161 && offset_expr.X_add_number == 0);
7162 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
7163 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
7168 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
7169 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
7170 order 32 bits of the value and the low order 32 bits are either
7171 zero or in OFFSET_EXPR. */
7172 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
7174 if (HAVE_64BIT_GPRS)
7175 load_register (treg, &imm_expr, 1);
7180 if (target_big_endian)
7192 load_register (hreg, &imm_expr, 0);
7195 if (offset_expr.X_op == O_absent)
7196 move_register (lreg, 0);
7199 gas_assert (offset_expr.X_op == O_constant);
7200 load_register (lreg, &offset_expr, 0);
7207 /* We know that sym is in the .rdata section. First we get the
7208 upper 16 bits of the address. */
7209 if (mips_pic == NO_PIC)
7211 macro_build_lui (&offset_expr, AT);
7216 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7217 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7221 /* Now we load the register(s). */
7222 if (HAVE_64BIT_GPRS)
7225 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7230 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7233 /* FIXME: How in the world do we deal with the possible
7235 offset_expr.X_add_number += 4;
7236 macro_build (&offset_expr, "lw", "t,o(b)",
7237 treg + 1, BFD_RELOC_LO16, AT);
7243 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
7244 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
7245 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
7246 the value and the low order 32 bits are either zero or in
7248 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
7251 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
7252 if (HAVE_64BIT_FPRS)
7254 gas_assert (HAVE_64BIT_GPRS);
7255 macro_build (NULL, "dmtc1", "t,S", AT, treg);
7259 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
7260 if (offset_expr.X_op == O_absent)
7261 macro_build (NULL, "mtc1", "t,G", 0, treg);
7264 gas_assert (offset_expr.X_op == O_constant);
7265 load_register (AT, &offset_expr, 0);
7266 macro_build (NULL, "mtc1", "t,G", AT, treg);
7272 gas_assert (offset_expr.X_op == O_symbol
7273 && offset_expr.X_add_number == 0);
7274 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
7275 if (strcmp (s, ".lit8") == 0)
7277 if (mips_opts.isa != ISA_MIPS1)
7279 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
7280 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
7283 breg = mips_gp_register;
7284 r = BFD_RELOC_MIPS_LITERAL;
7289 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
7291 if (mips_pic != NO_PIC)
7292 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7293 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7296 /* FIXME: This won't work for a 64 bit address. */
7297 macro_build_lui (&offset_expr, AT);
7300 if (mips_opts.isa != ISA_MIPS1)
7302 macro_build (&offset_expr, "ldc1", "T,o(b)",
7303 treg, BFD_RELOC_LO16, AT);
7312 /* Even on a big endian machine $fn comes before $fn+1. We have
7313 to adjust when loading from memory. */
7316 gas_assert (mips_opts.isa == ISA_MIPS1);
7317 macro_build (&offset_expr, "lwc1", "T,o(b)",
7318 target_big_endian ? treg + 1 : treg, r, breg);
7319 /* FIXME: A possible overflow which I don't know how to deal
7321 offset_expr.X_add_number += 4;
7322 macro_build (&offset_expr, "lwc1", "T,o(b)",
7323 target_big_endian ? treg : treg + 1, r, breg);
7327 gas_assert (mips_opts.isa == ISA_MIPS1);
7328 /* Even on a big endian machine $fn comes before $fn+1. We have
7329 to adjust when storing to memory. */
7330 macro_build (&offset_expr, "swc1", "T,o(b)",
7331 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
7332 offset_expr.X_add_number += 4;
7333 macro_build (&offset_expr, "swc1", "T,o(b)",
7334 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
7339 * The MIPS assembler seems to check for X_add_number not
7340 * being double aligned and generating:
7343 * addiu at,at,%lo(foo+1)
7346 * But, the resulting address is the same after relocation so why
7347 * generate the extra instruction?
7349 /* Itbl support may require additional care here. */
7351 if (mips_opts.isa != ISA_MIPS1)
7362 if (mips_opts.isa != ISA_MIPS1)
7370 /* Itbl support may require additional care here. */
7375 if (HAVE_64BIT_GPRS)
7386 if (HAVE_64BIT_GPRS)
7396 if (offset_expr.X_op != O_symbol
7397 && offset_expr.X_op != O_constant)
7399 as_bad (_("Expression too complex"));
7400 offset_expr.X_op = O_constant;
7403 if (HAVE_32BIT_ADDRESSES
7404 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
7408 sprintf_vma (value, offset_expr.X_add_number);
7409 as_bad (_("Number (0x%s) larger than 32 bits"), value);
7412 /* Even on a big endian machine $fn comes before $fn+1. We have
7413 to adjust when loading from memory. We set coproc if we must
7414 load $fn+1 first. */
7415 /* Itbl support may require additional care here. */
7416 if (!target_big_endian)
7419 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
7421 /* If this is a reference to a GP relative symbol, we want
7422 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
7423 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
7424 If we have a base register, we use this
7426 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
7427 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
7428 If this is not a GP relative symbol, we want
7429 lui $at,<sym> (BFD_RELOC_HI16_S)
7430 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7431 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7432 If there is a base register, we add it to $at after the
7433 lui instruction. If there is a constant, we always use
7435 if (offset_expr.X_op == O_symbol
7436 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7437 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7439 relax_start (offset_expr.X_add_symbol);
7442 tempreg = mips_gp_register;
7446 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7447 AT, breg, mips_gp_register);
7452 /* Itbl support may require additional care here. */
7453 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7454 BFD_RELOC_GPREL16, tempreg);
7455 offset_expr.X_add_number += 4;
7457 /* Set mips_optimize to 2 to avoid inserting an
7459 hold_mips_optimize = mips_optimize;
7461 /* Itbl support may require additional care here. */
7462 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7463 BFD_RELOC_GPREL16, tempreg);
7464 mips_optimize = hold_mips_optimize;
7468 offset_expr.X_add_number -= 4;
7471 macro_build_lui (&offset_expr, AT);
7473 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7474 /* Itbl support may require additional care here. */
7475 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7476 BFD_RELOC_LO16, AT);
7477 /* FIXME: How do we handle overflow here? */
7478 offset_expr.X_add_number += 4;
7479 /* Itbl support may require additional care here. */
7480 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7481 BFD_RELOC_LO16, AT);
7482 if (mips_relax.sequence)
7485 else if (!mips_big_got)
7487 /* If this is a reference to an external symbol, we want
7488 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7493 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7495 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7496 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7497 If there is a base register we add it to $at before the
7498 lwc1 instructions. If there is a constant we include it
7499 in the lwc1 instructions. */
7501 expr1.X_add_number = offset_expr.X_add_number;
7502 if (expr1.X_add_number < -0x8000
7503 || expr1.X_add_number >= 0x8000 - 4)
7504 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7505 load_got_offset (AT, &offset_expr);
7508 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7510 /* Set mips_optimize to 2 to avoid inserting an undesired
7512 hold_mips_optimize = mips_optimize;
7515 /* Itbl support may require additional care here. */
7516 relax_start (offset_expr.X_add_symbol);
7517 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
7518 BFD_RELOC_LO16, AT);
7519 expr1.X_add_number += 4;
7520 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
7521 BFD_RELOC_LO16, AT);
7523 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7524 BFD_RELOC_LO16, AT);
7525 offset_expr.X_add_number += 4;
7526 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7527 BFD_RELOC_LO16, AT);
7530 mips_optimize = hold_mips_optimize;
7532 else if (mips_big_got)
7536 /* If this is a reference to an external symbol, we want
7537 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7539 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
7544 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7546 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7547 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7548 If there is a base register we add it to $at before the
7549 lwc1 instructions. If there is a constant we include it
7550 in the lwc1 instructions. */
7552 expr1.X_add_number = offset_expr.X_add_number;
7553 offset_expr.X_add_number = 0;
7554 if (expr1.X_add_number < -0x8000
7555 || expr1.X_add_number >= 0x8000 - 4)
7556 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7557 gpdelay = reg_needs_delay (mips_gp_register);
7558 relax_start (offset_expr.X_add_symbol);
7559 macro_build (&offset_expr, "lui", "t,u",
7560 AT, BFD_RELOC_MIPS_GOT_HI16);
7561 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7562 AT, AT, mips_gp_register);
7563 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7564 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
7567 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7568 /* Itbl support may require additional care here. */
7569 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
7570 BFD_RELOC_LO16, AT);
7571 expr1.X_add_number += 4;
7573 /* Set mips_optimize to 2 to avoid inserting an undesired
7575 hold_mips_optimize = mips_optimize;
7577 /* Itbl support may require additional care here. */
7578 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
7579 BFD_RELOC_LO16, AT);
7580 mips_optimize = hold_mips_optimize;
7581 expr1.X_add_number -= 4;
7584 offset_expr.X_add_number = expr1.X_add_number;
7586 macro_build (NULL, "nop", "");
7587 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7588 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7591 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7592 /* Itbl support may require additional care here. */
7593 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7594 BFD_RELOC_LO16, AT);
7595 offset_expr.X_add_number += 4;
7597 /* Set mips_optimize to 2 to avoid inserting an undesired
7599 hold_mips_optimize = mips_optimize;
7601 /* Itbl support may require additional care here. */
7602 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7603 BFD_RELOC_LO16, AT);
7604 mips_optimize = hold_mips_optimize;
7613 s = HAVE_64BIT_GPRS ? "ld" : "lw";
7616 s = HAVE_64BIT_GPRS ? "sd" : "sw";
7618 macro_build (&offset_expr, s, "t,o(b)", treg,
7619 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
7621 if (!HAVE_64BIT_GPRS)
7623 offset_expr.X_add_number += 4;
7624 macro_build (&offset_expr, s, "t,o(b)", treg + 1,
7625 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
7630 /* New code added to support COPZ instructions.
7631 This code builds table entries out of the macros in mip_opcodes.
7632 R4000 uses interlocks to handle coproc delays.
7633 Other chips (like the R3000) require nops to be inserted for delays.
7635 FIXME: Currently, we require that the user handle delays.
7636 In order to fill delay slots for non-interlocked chips,
7637 we must have a way to specify delays based on the coprocessor.
7638 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7639 What are the side-effects of the cop instruction?
7640 What cache support might we have and what are its effects?
7641 Both coprocessor & memory require delays. how long???
7642 What registers are read/set/modified?
7644 If an itbl is provided to interpret cop instructions,
7645 this knowledge can be encoded in the itbl spec. */
7659 if (NO_ISA_COP (mips_opts.arch)
7660 && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0)
7662 as_bad (_("opcode not supported on this processor: %s"),
7663 mips_cpu_info_from_arch (mips_opts.arch)->name);
7667 /* For now we just do C (same as Cz). The parameter will be
7668 stored in insn_opcode by mips_ip. */
7669 macro_build (NULL, s, "C", ip->insn_opcode);
7673 move_register (dreg, sreg);
7679 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
7680 macro_build (NULL, "mflo", "d", dreg);
7686 /* The MIPS assembler some times generates shifts and adds. I'm
7687 not trying to be that fancy. GCC should do this for us
7690 load_register (AT, &imm_expr, dbl);
7691 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
7692 macro_build (NULL, "mflo", "d", dreg);
7708 load_register (AT, &imm_expr, dbl);
7709 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
7710 macro_build (NULL, "mflo", "d", dreg);
7711 macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
7712 macro_build (NULL, "mfhi", "d", AT);
7714 macro_build (NULL, "tne", "s,t,q", dreg, AT, 6);
7717 expr1.X_add_number = 8;
7718 macro_build (&expr1, "beq", "s,t,p", dreg, AT);
7719 macro_build (NULL, "nop", "");
7720 macro_build (NULL, "break", "c", 6);
7723 macro_build (NULL, "mflo", "d", dreg);
7739 load_register (AT, &imm_expr, dbl);
7740 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
7741 sreg, imm ? AT : treg);
7742 macro_build (NULL, "mfhi", "d", AT);
7743 macro_build (NULL, "mflo", "d", dreg);
7745 macro_build (NULL, "tne", "s,t,q", AT, ZERO, 6);
7748 expr1.X_add_number = 8;
7749 macro_build (&expr1, "beq", "s,t,p", AT, ZERO);
7750 macro_build (NULL, "nop", "");
7751 macro_build (NULL, "break", "c", 6);
7757 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7768 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
7769 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
7773 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
7774 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
7775 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
7776 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7780 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7791 macro_build (NULL, "negu", "d,w", tempreg, treg);
7792 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
7796 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
7797 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
7798 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
7799 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7808 if (imm_expr.X_op != O_constant)
7809 as_bad (_("Improper rotate count"));
7810 rot = imm_expr.X_add_number & 0x3f;
7811 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7813 rot = (64 - rot) & 0x3f;
7815 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7817 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7822 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7825 l = (rot < 0x20) ? "dsll" : "dsll32";
7826 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
7829 macro_build (NULL, l, "d,w,<", AT, sreg, rot);
7830 macro_build (NULL, rr, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7831 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7839 if (imm_expr.X_op != O_constant)
7840 as_bad (_("Improper rotate count"));
7841 rot = imm_expr.X_add_number & 0x1f;
7842 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7844 macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f);
7849 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7853 macro_build (NULL, "sll", "d,w,<", AT, sreg, rot);
7854 macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7855 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7860 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7862 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
7866 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
7867 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
7868 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
7869 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7873 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7875 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
7879 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
7880 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
7881 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
7882 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7891 if (imm_expr.X_op != O_constant)
7892 as_bad (_("Improper rotate count"));
7893 rot = imm_expr.X_add_number & 0x3f;
7894 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7897 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7899 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7904 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7907 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
7908 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7911 macro_build (NULL, rr, "d,w,<", AT, sreg, rot);
7912 macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7913 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7921 if (imm_expr.X_op != O_constant)
7922 as_bad (_("Improper rotate count"));
7923 rot = imm_expr.X_add_number & 0x1f;
7924 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7926 macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot);
7931 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7935 macro_build (NULL, "srl", "d,w,<", AT, sreg, rot);
7936 macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7937 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7943 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
7945 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7948 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7949 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7954 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7956 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7961 as_warn (_("Instruction %s: result is always false"),
7963 move_register (dreg, 0);
7966 if (CPU_HAS_SEQ (mips_opts.arch)
7967 && -512 <= imm_expr.X_add_number
7968 && imm_expr.X_add_number < 512)
7970 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
7971 (int) imm_expr.X_add_number);
7974 if (imm_expr.X_op == O_constant
7975 && imm_expr.X_add_number >= 0
7976 && imm_expr.X_add_number < 0x10000)
7978 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7980 else if (imm_expr.X_op == O_constant
7981 && imm_expr.X_add_number > -0x8000
7982 && imm_expr.X_add_number < 0)
7984 imm_expr.X_add_number = -imm_expr.X_add_number;
7985 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7986 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7988 else if (CPU_HAS_SEQ (mips_opts.arch))
7991 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7992 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
7997 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7998 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
8001 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
8004 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
8010 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
8011 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
8014 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
8016 if (imm_expr.X_op == O_constant
8017 && imm_expr.X_add_number >= -0x8000
8018 && imm_expr.X_add_number < 0x8000)
8020 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
8021 dreg, sreg, BFD_RELOC_LO16);
8025 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8026 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
8030 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
8033 case M_SGT: /* sreg > treg <==> treg < sreg */
8039 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
8042 case M_SGT_I: /* sreg > I <==> I < sreg */
8049 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8050 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
8053 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
8059 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
8060 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
8063 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
8070 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8071 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
8072 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
8076 if (imm_expr.X_op == O_constant
8077 && imm_expr.X_add_number >= -0x8000
8078 && imm_expr.X_add_number < 0x8000)
8080 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
8084 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8085 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
8089 if (imm_expr.X_op == O_constant
8090 && imm_expr.X_add_number >= -0x8000
8091 && imm_expr.X_add_number < 0x8000)
8093 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
8098 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8099 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
8104 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
8106 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
8109 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
8110 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
8115 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
8117 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
8122 as_warn (_("Instruction %s: result is always true"),
8124 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
8125 dreg, 0, BFD_RELOC_LO16);
8128 if (CPU_HAS_SEQ (mips_opts.arch)
8129 && -512 <= imm_expr.X_add_number
8130 && imm_expr.X_add_number < 512)
8132 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
8133 (int) imm_expr.X_add_number);
8136 if (imm_expr.X_op == O_constant
8137 && imm_expr.X_add_number >= 0
8138 && imm_expr.X_add_number < 0x10000)
8140 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
8142 else if (imm_expr.X_op == O_constant
8143 && imm_expr.X_add_number > -0x8000
8144 && imm_expr.X_add_number < 0)
8146 imm_expr.X_add_number = -imm_expr.X_add_number;
8147 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
8148 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
8150 else if (CPU_HAS_SEQ (mips_opts.arch))
8153 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8154 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
8159 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8160 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
8163 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
8169 if (imm_expr.X_op == O_constant
8170 && imm_expr.X_add_number > -0x8000
8171 && imm_expr.X_add_number <= 0x8000)
8173 imm_expr.X_add_number = -imm_expr.X_add_number;
8174 macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j",
8175 dreg, sreg, BFD_RELOC_LO16);
8179 load_register (AT, &imm_expr, dbl);
8180 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
8186 if (imm_expr.X_op == O_constant
8187 && imm_expr.X_add_number > -0x8000
8188 && imm_expr.X_add_number <= 0x8000)
8190 imm_expr.X_add_number = -imm_expr.X_add_number;
8191 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j",
8192 dreg, sreg, BFD_RELOC_LO16);
8196 load_register (AT, &imm_expr, dbl);
8197 macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
8219 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8220 macro_build (NULL, s, "s,t", sreg, AT);
8225 gas_assert (mips_opts.isa == ISA_MIPS1);
8227 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
8228 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
8231 * Is the double cfc1 instruction a bug in the mips assembler;
8232 * or is there a reason for it?
8235 macro_build (NULL, "cfc1", "t,G", treg, RA);
8236 macro_build (NULL, "cfc1", "t,G", treg, RA);
8237 macro_build (NULL, "nop", "");
8238 expr1.X_add_number = 3;
8239 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
8240 expr1.X_add_number = 2;
8241 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
8242 macro_build (NULL, "ctc1", "t,G", AT, RA);
8243 macro_build (NULL, "nop", "");
8244 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
8246 macro_build (NULL, "ctc1", "t,G", treg, RA);
8247 macro_build (NULL, "nop", "");
8258 if (offset_expr.X_add_number >= 0x7fff)
8259 as_bad (_("Operand overflow"));
8260 if (!target_big_endian)
8261 ++offset_expr.X_add_number;
8262 macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg);
8263 if (!target_big_endian)
8264 --offset_expr.X_add_number;
8266 ++offset_expr.X_add_number;
8267 macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg);
8268 macro_build (NULL, "sll", "d,w,<", AT, AT, 8);
8269 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8282 if (offset_expr.X_add_number >= 0x8000 - off)
8283 as_bad (_("Operand overflow"));
8291 if (!target_big_endian)
8292 offset_expr.X_add_number += off;
8293 macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
8294 if (!target_big_endian)
8295 offset_expr.X_add_number -= off;
8297 offset_expr.X_add_number += off;
8298 macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
8300 /* If necessary, move the result in tempreg to the final destination. */
8301 if (treg == tempreg)
8303 /* Protect second load's delay slot. */
8305 move_register (treg, tempreg);
8319 load_address (AT, &offset_expr, &used_at);
8321 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8322 if (!target_big_endian)
8323 expr1.X_add_number = off;
8325 expr1.X_add_number = 0;
8326 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8327 if (!target_big_endian)
8328 expr1.X_add_number = 0;
8330 expr1.X_add_number = off;
8331 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8337 load_address (AT, &offset_expr, &used_at);
8339 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8340 if (target_big_endian)
8341 expr1.X_add_number = 0;
8342 macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
8343 treg, BFD_RELOC_LO16, AT);
8344 if (target_big_endian)
8345 expr1.X_add_number = 1;
8347 expr1.X_add_number = 0;
8348 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
8349 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
8350 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8355 if (offset_expr.X_add_number >= 0x7fff)
8356 as_bad (_("Operand overflow"));
8357 if (target_big_endian)
8358 ++offset_expr.X_add_number;
8359 macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg);
8360 macro_build (NULL, "srl", "d,w,<", AT, treg, 8);
8361 if (target_big_endian)
8362 --offset_expr.X_add_number;
8364 ++offset_expr.X_add_number;
8365 macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg);
8378 if (offset_expr.X_add_number >= 0x8000 - off)
8379 as_bad (_("Operand overflow"));
8380 if (!target_big_endian)
8381 offset_expr.X_add_number += off;
8382 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8383 if (!target_big_endian)
8384 offset_expr.X_add_number -= off;
8386 offset_expr.X_add_number += off;
8387 macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8401 load_address (AT, &offset_expr, &used_at);
8403 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8404 if (!target_big_endian)
8405 expr1.X_add_number = off;
8407 expr1.X_add_number = 0;
8408 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8409 if (!target_big_endian)
8410 expr1.X_add_number = 0;
8412 expr1.X_add_number = off;
8413 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8418 load_address (AT, &offset_expr, &used_at);
8420 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8421 if (!target_big_endian)
8422 expr1.X_add_number = 0;
8423 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8424 macro_build (NULL, "srl", "d,w,<", treg, treg, 8);
8425 if (!target_big_endian)
8426 expr1.X_add_number = 1;
8428 expr1.X_add_number = 0;
8429 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8430 if (!target_big_endian)
8431 expr1.X_add_number = 0;
8433 expr1.X_add_number = 1;
8434 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
8435 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
8436 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8440 /* FIXME: Check if this is one of the itbl macros, since they
8441 are added dynamically. */
8442 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
8445 if (!mips_opts.at && used_at)
8446 as_bad (_("Macro used $at after \".set noat\""));
8449 /* Implement macros in mips16 mode. */
8452 mips16_macro (struct mips_cl_insn *ip)
8455 int xreg, yreg, zreg, tmp;
8458 const char *s, *s2, *s3;
8460 mask = ip->insn_mo->mask;
8462 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
8463 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
8464 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
8466 expr1.X_op = O_constant;
8467 expr1.X_op_symbol = NULL;
8468 expr1.X_add_symbol = NULL;
8469 expr1.X_add_number = 1;
8489 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
8490 expr1.X_add_number = 2;
8491 macro_build (&expr1, "bnez", "x,p", yreg);
8492 macro_build (NULL, "break", "6", 7);
8494 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
8495 since that causes an overflow. We should do that as well,
8496 but I don't see how to do the comparisons without a temporary
8499 macro_build (NULL, s, "x", zreg);
8519 macro_build (NULL, s, "0,x,y", xreg, yreg);
8520 expr1.X_add_number = 2;
8521 macro_build (&expr1, "bnez", "x,p", yreg);
8522 macro_build (NULL, "break", "6", 7);
8524 macro_build (NULL, s2, "x", zreg);
8530 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
8531 macro_build (NULL, "mflo", "x", zreg);
8539 if (imm_expr.X_op != O_constant)
8540 as_bad (_("Unsupported large constant"));
8541 imm_expr.X_add_number = -imm_expr.X_add_number;
8542 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
8546 if (imm_expr.X_op != O_constant)
8547 as_bad (_("Unsupported large constant"));
8548 imm_expr.X_add_number = -imm_expr.X_add_number;
8549 macro_build (&imm_expr, "addiu", "x,k", xreg);
8553 if (imm_expr.X_op != O_constant)
8554 as_bad (_("Unsupported large constant"));
8555 imm_expr.X_add_number = -imm_expr.X_add_number;
8556 macro_build (&imm_expr, "daddiu", "y,j", yreg);
8578 goto do_reverse_branch;
8582 goto do_reverse_branch;
8594 goto do_reverse_branch;
8605 macro_build (NULL, s, "x,y", xreg, yreg);
8606 macro_build (&offset_expr, s2, "p");
8633 goto do_addone_branch_i;
8638 goto do_addone_branch_i;
8653 goto do_addone_branch_i;
8660 if (imm_expr.X_op != O_constant)
8661 as_bad (_("Unsupported large constant"));
8662 ++imm_expr.X_add_number;
8665 macro_build (&imm_expr, s, s3, xreg);
8666 macro_build (&offset_expr, s2, "p");
8670 expr1.X_add_number = 0;
8671 macro_build (&expr1, "slti", "x,8", yreg);
8673 move_register (xreg, yreg);
8674 expr1.X_add_number = 2;
8675 macro_build (&expr1, "bteqz", "p");
8676 macro_build (NULL, "neg", "x,w", xreg, xreg);
8680 /* For consistency checking, verify that all bits are specified either
8681 by the match/mask part of the instruction definition, or by the
8684 validate_mips_insn (const struct mips_opcode *opc)
8686 const char *p = opc->args;
8688 unsigned long used_bits = opc->mask;
8690 if ((used_bits & opc->match) != opc->match)
8692 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8693 opc->name, opc->args);
8696 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8706 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
8707 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
8708 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
8709 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
8710 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8711 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8712 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8713 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
8714 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8715 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8716 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8717 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8718 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8720 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8721 case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
8722 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8723 case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
8724 case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
8725 case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
8726 case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
8727 case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
8728 case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
8729 case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
8730 case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break;
8731 case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break;
8732 case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break;
8733 case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break;
8734 case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break;
8737 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8738 c, opc->name, opc->args);
8742 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8743 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8745 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
8746 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
8747 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8748 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8750 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8751 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8753 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
8754 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8756 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
8757 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
8758 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
8759 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
8760 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8761 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
8762 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8763 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8764 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8765 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8766 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8767 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8768 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8769 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
8770 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8771 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
8772 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8774 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
8775 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8776 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8777 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
8779 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8780 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8781 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
8782 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8783 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8784 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8785 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8786 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8787 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8790 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
8791 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
8792 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8793 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
8794 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
8797 case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8798 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
8799 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
8800 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
8801 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
8802 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8803 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
8804 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
8805 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
8806 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
8807 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
8808 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
8809 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
8810 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
8811 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
8812 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
8813 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
8814 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8816 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8817 c, opc->name, opc->args);
8821 if (used_bits != 0xffffffff)
8823 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8824 ~used_bits & 0xffffffff, opc->name, opc->args);
8830 /* UDI immediates. */
8838 static const struct mips_immed mips_immed[] = {
8839 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
8840 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
8841 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
8842 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
8846 /* Check whether an odd floating-point register is allowed. */
8848 mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
8850 const char *s = insn->name;
8852 if (insn->pinfo == INSN_MACRO)
8853 /* Let a macro pass, we'll catch it later when it is expanded. */
8856 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa))
8858 /* Allow odd registers for single-precision ops. */
8859 switch (insn->pinfo & (FP_S | FP_D))
8863 return 1; /* both single precision - ok */
8865 return 0; /* both double precision - fail */
8870 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
8871 s = strchr (insn->name, '.');
8873 s = s != NULL ? strchr (s + 1, '.') : NULL;
8874 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
8877 /* Single-precision coprocessor loads and moves are OK too. */
8878 if ((insn->pinfo & FP_S)
8879 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
8880 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
8886 /* This routine assembles an instruction into its binary format. As a
8887 side effect, it sets one of the global variables imm_reloc or
8888 offset_reloc to the type of relocation to do if one of the operands
8889 is an address expression. */
8892 mips_ip (char *str, struct mips_cl_insn *ip)
8897 struct mips_opcode *insn;
8900 unsigned int lastregno;
8901 unsigned int lastpos = 0;
8902 unsigned int limlo, limhi;
8905 offsetT min_range, max_range;
8911 /* If the instruction contains a '.', we first try to match an instruction
8912 including the '.'. Then we try again without the '.'. */
8914 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
8917 /* If we stopped on whitespace, then replace the whitespace with null for
8918 the call to hash_find. Save the character we replaced just in case we
8919 have to re-parse the instruction. */
8926 insn = (struct mips_opcode *) hash_find (op_hash, str);
8928 /* If we didn't find the instruction in the opcode table, try again, but
8929 this time with just the instruction up to, but not including the
8933 /* Restore the character we overwrite above (if any). */
8937 /* Scan up to the first '.' or whitespace. */
8939 *s != '\0' && *s != '.' && !ISSPACE (*s);
8943 /* If we did not find a '.', then we can quit now. */
8946 insn_error = _("Unrecognized opcode");
8950 /* Lookup the instruction in the hash table. */
8952 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
8954 insn_error = _("Unrecognized opcode");
8964 gas_assert (strcmp (insn->name, str) == 0);
8966 ok = is_opcode_valid (insn);
8969 if (insn + 1 < &mips_opcodes[NUMOPCODES]
8970 && strcmp (insn->name, insn[1].name) == 0)
8979 static char buf[100];
8981 _("opcode not supported on this processor: %s (%s)"),
8982 mips_cpu_info_from_arch (mips_opts.arch)->name,
8983 mips_cpu_info_from_isa (mips_opts.isa)->name);
8992 create_insn (ip, insn);
8995 lastregno = 0xffffffff;
8996 for (args = insn->args;; ++args)
9000 s += strspn (s, " \t");
9004 case '\0': /* end of args */
9009 case '2': /* DSP 2-bit unsigned immediate in bit 11. */
9010 my_getExpression (&imm_expr, s);
9011 check_absolute_expr (ip, &imm_expr);
9012 if ((unsigned long) imm_expr.X_add_number != 1
9013 && (unsigned long) imm_expr.X_add_number != 3)
9015 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
9016 (unsigned long) imm_expr.X_add_number);
9018 INSERT_OPERAND (BP, *ip, imm_expr.X_add_number);
9019 imm_expr.X_op = O_absent;
9023 case '3': /* DSP 3-bit unsigned immediate in bit 21. */
9024 my_getExpression (&imm_expr, s);
9025 check_absolute_expr (ip, &imm_expr);
9026 if (imm_expr.X_add_number & ~OP_MASK_SA3)
9028 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9029 OP_MASK_SA3, (unsigned long) imm_expr.X_add_number);
9031 INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number);
9032 imm_expr.X_op = O_absent;
9036 case '4': /* DSP 4-bit unsigned immediate in bit 21. */
9037 my_getExpression (&imm_expr, s);
9038 check_absolute_expr (ip, &imm_expr);
9039 if (imm_expr.X_add_number & ~OP_MASK_SA4)
9041 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9042 OP_MASK_SA4, (unsigned long) imm_expr.X_add_number);
9044 INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number);
9045 imm_expr.X_op = O_absent;
9049 case '5': /* DSP 8-bit unsigned immediate in bit 16. */
9050 my_getExpression (&imm_expr, s);
9051 check_absolute_expr (ip, &imm_expr);
9052 if (imm_expr.X_add_number & ~OP_MASK_IMM8)
9054 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9055 OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number);
9057 INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number);
9058 imm_expr.X_op = O_absent;
9062 case '6': /* DSP 5-bit unsigned immediate in bit 21. */
9063 my_getExpression (&imm_expr, s);
9064 check_absolute_expr (ip, &imm_expr);
9065 if (imm_expr.X_add_number & ~OP_MASK_RS)
9067 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9068 OP_MASK_RS, (unsigned long) imm_expr.X_add_number);
9070 INSERT_OPERAND (RS, *ip, imm_expr.X_add_number);
9071 imm_expr.X_op = O_absent;
9075 case '7': /* Four DSP accumulators in bits 11,12. */
9076 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9077 s[3] >= '0' && s[3] <= '3')
9081 INSERT_OPERAND (DSPACC, *ip, regno);
9085 as_bad (_("Invalid dsp acc register"));
9088 case '8': /* DSP 6-bit unsigned immediate in bit 11. */
9089 my_getExpression (&imm_expr, s);
9090 check_absolute_expr (ip, &imm_expr);
9091 if (imm_expr.X_add_number & ~OP_MASK_WRDSP)
9093 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9095 (unsigned long) imm_expr.X_add_number);
9097 INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number);
9098 imm_expr.X_op = O_absent;
9102 case '9': /* Four DSP accumulators in bits 21,22. */
9103 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9104 s[3] >= '0' && s[3] <= '3')
9108 INSERT_OPERAND (DSPACC_S, *ip, regno);
9112 as_bad (_("Invalid dsp acc register"));
9115 case '0': /* DSP 6-bit signed immediate in bit 20. */
9116 my_getExpression (&imm_expr, s);
9117 check_absolute_expr (ip, &imm_expr);
9118 min_range = -((OP_MASK_DSPSFT + 1) >> 1);
9119 max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1;
9120 if (imm_expr.X_add_number < min_range ||
9121 imm_expr.X_add_number > max_range)
9123 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
9124 (long) min_range, (long) max_range,
9125 (long) imm_expr.X_add_number);
9127 INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number);
9128 imm_expr.X_op = O_absent;
9132 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
9133 my_getExpression (&imm_expr, s);
9134 check_absolute_expr (ip, &imm_expr);
9135 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
9137 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9139 (unsigned long) imm_expr.X_add_number);
9141 INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number);
9142 imm_expr.X_op = O_absent;
9146 case ':': /* DSP 7-bit signed immediate in bit 19. */
9147 my_getExpression (&imm_expr, s);
9148 check_absolute_expr (ip, &imm_expr);
9149 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
9150 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
9151 if (imm_expr.X_add_number < min_range ||
9152 imm_expr.X_add_number > max_range)
9154 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
9155 (long) min_range, (long) max_range,
9156 (long) imm_expr.X_add_number);
9158 INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number);
9159 imm_expr.X_op = O_absent;
9163 case '@': /* DSP 10-bit signed immediate in bit 16. */
9164 my_getExpression (&imm_expr, s);
9165 check_absolute_expr (ip, &imm_expr);
9166 min_range = -((OP_MASK_IMM10 + 1) >> 1);
9167 max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1;
9168 if (imm_expr.X_add_number < min_range ||
9169 imm_expr.X_add_number > max_range)
9171 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
9172 (long) min_range, (long) max_range,
9173 (long) imm_expr.X_add_number);
9175 INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number);
9176 imm_expr.X_op = O_absent;
9180 case '!': /* MT usermode flag bit. */
9181 my_getExpression (&imm_expr, s);
9182 check_absolute_expr (ip, &imm_expr);
9183 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
9184 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
9185 (unsigned long) imm_expr.X_add_number);
9186 INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number);
9187 imm_expr.X_op = O_absent;
9191 case '$': /* MT load high flag bit. */
9192 my_getExpression (&imm_expr, s);
9193 check_absolute_expr (ip, &imm_expr);
9194 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
9195 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
9196 (unsigned long) imm_expr.X_add_number);
9197 INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number);
9198 imm_expr.X_op = O_absent;
9202 case '*': /* Four DSP accumulators in bits 18,19. */
9203 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9204 s[3] >= '0' && s[3] <= '3')
9208 INSERT_OPERAND (MTACC_T, *ip, regno);
9212 as_bad (_("Invalid dsp/smartmips acc register"));
9215 case '&': /* Four DSP accumulators in bits 13,14. */
9216 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9217 s[3] >= '0' && s[3] <= '3')
9221 INSERT_OPERAND (MTACC_D, *ip, regno);
9225 as_bad (_("Invalid dsp/smartmips acc register"));
9237 INSERT_OPERAND (RS, *ip, lastregno);
9241 INSERT_OPERAND (RT, *ip, lastregno);
9245 INSERT_OPERAND (FT, *ip, lastregno);
9249 INSERT_OPERAND (FS, *ip, lastregno);
9255 /* Handle optional base register.
9256 Either the base register is omitted or
9257 we must have a left paren. */
9258 /* This is dependent on the next operand specifier
9259 is a base register specification. */
9260 gas_assert (args[1] == 'b');
9264 case ')': /* These must match exactly. */
9271 case '+': /* Opcode extension character. */
9274 case '1': /* UDI immediates. */
9279 const struct mips_immed *imm = mips_immed;
9281 while (imm->type && imm->type != *args)
9285 my_getExpression (&imm_expr, s);
9286 check_absolute_expr (ip, &imm_expr);
9287 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
9289 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
9290 imm->desc ? imm->desc : ip->insn_mo->name,
9291 (unsigned long) imm_expr.X_add_number,
9292 (unsigned long) imm_expr.X_add_number);
9293 imm_expr.X_add_number &= imm->mask;
9295 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
9297 imm_expr.X_op = O_absent;
9302 case 'A': /* ins/ext position, becomes LSB. */
9311 my_getExpression (&imm_expr, s);
9312 check_absolute_expr (ip, &imm_expr);
9313 if ((unsigned long) imm_expr.X_add_number < limlo
9314 || (unsigned long) imm_expr.X_add_number > limhi)
9316 as_bad (_("Improper position (%lu)"),
9317 (unsigned long) imm_expr.X_add_number);
9318 imm_expr.X_add_number = limlo;
9320 lastpos = imm_expr.X_add_number;
9321 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9322 imm_expr.X_op = O_absent;
9326 case 'B': /* ins size, becomes MSB. */
9335 my_getExpression (&imm_expr, s);
9336 check_absolute_expr (ip, &imm_expr);
9337 /* Check for negative input so that small negative numbers
9338 will not succeed incorrectly. The checks against
9339 (pos+size) transitively check "size" itself,
9340 assuming that "pos" is reasonable. */
9341 if ((long) imm_expr.X_add_number < 0
9342 || ((unsigned long) imm_expr.X_add_number
9344 || ((unsigned long) imm_expr.X_add_number
9347 as_bad (_("Improper insert size (%lu, position %lu)"),
9348 (unsigned long) imm_expr.X_add_number,
9349 (unsigned long) lastpos);
9350 imm_expr.X_add_number = limlo - lastpos;
9352 INSERT_OPERAND (INSMSB, *ip,
9353 lastpos + imm_expr.X_add_number - 1);
9354 imm_expr.X_op = O_absent;
9358 case 'C': /* ext size, becomes MSBD. */
9371 my_getExpression (&imm_expr, s);
9372 check_absolute_expr (ip, &imm_expr);
9373 /* Check for negative input so that small negative numbers
9374 will not succeed incorrectly. The checks against
9375 (pos+size) transitively check "size" itself,
9376 assuming that "pos" is reasonable. */
9377 if ((long) imm_expr.X_add_number < 0
9378 || ((unsigned long) imm_expr.X_add_number
9380 || ((unsigned long) imm_expr.X_add_number
9383 as_bad (_("Improper extract size (%lu, position %lu)"),
9384 (unsigned long) imm_expr.X_add_number,
9385 (unsigned long) lastpos);
9386 imm_expr.X_add_number = limlo - lastpos;
9388 INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1);
9389 imm_expr.X_op = O_absent;
9394 /* +D is for disassembly only; never match. */
9398 /* "+I" is like "I", except that imm2_expr is used. */
9399 my_getExpression (&imm2_expr, s);
9400 if (imm2_expr.X_op != O_big
9401 && imm2_expr.X_op != O_constant)
9402 insn_error = _("absolute expression required");
9403 if (HAVE_32BIT_GPRS)
9404 normalize_constant_expr (&imm2_expr);
9408 case 'T': /* Coprocessor register. */
9409 /* +T is for disassembly only; never match. */
9412 case 't': /* Coprocessor register number. */
9413 if (s[0] == '$' && ISDIGIT (s[1]))
9423 while (ISDIGIT (*s));
9425 as_bad (_("Invalid register number (%d)"), regno);
9428 INSERT_OPERAND (RT, *ip, regno);
9433 as_bad (_("Invalid coprocessor 0 register number"));
9437 /* bbit[01] and bbit[01]32 bit index. Give error if index
9438 is not in the valid range. */
9439 my_getExpression (&imm_expr, s);
9440 check_absolute_expr (ip, &imm_expr);
9441 if ((unsigned) imm_expr.X_add_number > 31)
9443 as_bad (_("Improper bit index (%lu)"),
9444 (unsigned long) imm_expr.X_add_number);
9445 imm_expr.X_add_number = 0;
9447 INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number);
9448 imm_expr.X_op = O_absent;
9453 /* bbit[01] bit index when bbit is used but we generate
9454 bbit[01]32 because the index is over 32. Move to the
9455 next candidate if index is not in the valid range. */
9456 my_getExpression (&imm_expr, s);
9457 check_absolute_expr (ip, &imm_expr);
9458 if ((unsigned) imm_expr.X_add_number < 32
9459 || (unsigned) imm_expr.X_add_number > 63)
9461 INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number - 32);
9462 imm_expr.X_op = O_absent;
9467 /* cins, cins32, exts and exts32 position field. Give error
9468 if it's not in the valid range. */
9469 my_getExpression (&imm_expr, s);
9470 check_absolute_expr (ip, &imm_expr);
9471 if ((unsigned) imm_expr.X_add_number > 31)
9473 as_bad (_("Improper position (%lu)"),
9474 (unsigned long) imm_expr.X_add_number);
9475 imm_expr.X_add_number = 0;
9477 /* Make the pos explicit to simplify +S. */
9478 lastpos = imm_expr.X_add_number + 32;
9479 INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number);
9480 imm_expr.X_op = O_absent;
9485 /* cins, cins32, exts and exts32 position field. Move to
9486 the next candidate if it's not in the valid range. */
9487 my_getExpression (&imm_expr, s);
9488 check_absolute_expr (ip, &imm_expr);
9489 if ((unsigned) imm_expr.X_add_number < 32
9490 || (unsigned) imm_expr.X_add_number > 63)
9492 lastpos = imm_expr.X_add_number;
9493 INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number - 32);
9494 imm_expr.X_op = O_absent;
9499 /* cins and exts length-minus-one field. */
9500 my_getExpression (&imm_expr, s);
9501 check_absolute_expr (ip, &imm_expr);
9502 if ((unsigned long) imm_expr.X_add_number > 31)
9504 as_bad (_("Improper size (%lu)"),
9505 (unsigned long) imm_expr.X_add_number);
9506 imm_expr.X_add_number = 0;
9508 INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number);
9509 imm_expr.X_op = O_absent;
9514 /* cins32/exts32 and cins/exts aliasing cint32/exts32
9515 length-minus-one field. */
9516 my_getExpression (&imm_expr, s);
9517 check_absolute_expr (ip, &imm_expr);
9518 if ((long) imm_expr.X_add_number < 0
9519 || (unsigned long) imm_expr.X_add_number + lastpos > 63)
9521 as_bad (_("Improper size (%lu)"),
9522 (unsigned long) imm_expr.X_add_number);
9523 imm_expr.X_add_number = 0;
9525 INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number);
9526 imm_expr.X_op = O_absent;
9531 /* seqi/snei immediate field. */
9532 my_getExpression (&imm_expr, s);
9533 check_absolute_expr (ip, &imm_expr);
9534 if ((long) imm_expr.X_add_number < -512
9535 || (long) imm_expr.X_add_number >= 512)
9537 as_bad (_("Improper immediate (%ld)"),
9538 (long) imm_expr.X_add_number);
9539 imm_expr.X_add_number = 0;
9541 INSERT_OPERAND (SEQI, *ip, imm_expr.X_add_number);
9542 imm_expr.X_op = O_absent;
9546 case 'a': /* 8-bit signed offset in bit 6 */
9547 my_getExpression (&imm_expr, s);
9548 check_absolute_expr (ip, &imm_expr);
9549 min_range = -((OP_MASK_OFFSET_A + 1) >> 1);
9550 max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1;
9551 if (imm_expr.X_add_number < min_range
9552 || imm_expr.X_add_number > max_range)
9554 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9555 (long) min_range, (long) max_range,
9556 (long) imm_expr.X_add_number);
9558 INSERT_OPERAND (OFFSET_A, *ip, imm_expr.X_add_number);
9559 imm_expr.X_op = O_absent;
9563 case 'b': /* 8-bit signed offset in bit 3 */
9564 my_getExpression (&imm_expr, s);
9565 check_absolute_expr (ip, &imm_expr);
9566 min_range = -((OP_MASK_OFFSET_B + 1) >> 1);
9567 max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1;
9568 if (imm_expr.X_add_number < min_range
9569 || imm_expr.X_add_number > max_range)
9571 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9572 (long) min_range, (long) max_range,
9573 (long) imm_expr.X_add_number);
9575 INSERT_OPERAND (OFFSET_B, *ip, imm_expr.X_add_number);
9576 imm_expr.X_op = O_absent;
9580 case 'c': /* 9-bit signed offset in bit 6 */
9581 my_getExpression (&imm_expr, s);
9582 check_absolute_expr (ip, &imm_expr);
9583 min_range = -((OP_MASK_OFFSET_C + 1) >> 1);
9584 max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1;
9585 /* We check the offset range before adjusted. */
9588 if (imm_expr.X_add_number < min_range
9589 || imm_expr.X_add_number > max_range)
9591 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9592 (long) min_range, (long) max_range,
9593 (long) imm_expr.X_add_number);
9595 if (imm_expr.X_add_number & 0xf)
9597 as_bad (_("Offset not 16 bytes alignment (%ld)"),
9598 (long) imm_expr.X_add_number);
9600 /* Right shift 4 bits to adjust the offset operand. */
9601 INSERT_OPERAND (OFFSET_C, *ip, imm_expr.X_add_number >> 4);
9602 imm_expr.X_op = O_absent;
9607 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
9609 if (regno == AT && mips_opts.at)
9611 if (mips_opts.at == ATREG)
9612 as_warn (_("used $at without \".set noat\""));
9614 as_warn (_("used $%u with \".set at=$%u\""),
9615 regno, mips_opts.at);
9617 INSERT_OPERAND (RZ, *ip, regno);
9621 if (!reg_lookup (&s, RTYPE_FPU, ®no))
9623 INSERT_OPERAND (FZ, *ip, regno);
9627 as_bad (_("Internal error: bad mips opcode "
9628 "(unknown extension operand type `+%c'): %s %s"),
9629 *args, insn->name, insn->args);
9630 /* Further processing is fruitless. */
9635 case '<': /* must be at least one digit */
9637 * According to the manual, if the shift amount is greater
9638 * than 31 or less than 0, then the shift amount should be
9639 * mod 32. In reality the mips assembler issues an error.
9640 * We issue a warning and mask out all but the low 5 bits.
9642 my_getExpression (&imm_expr, s);
9643 check_absolute_expr (ip, &imm_expr);
9644 if ((unsigned long) imm_expr.X_add_number > 31)
9645 as_warn (_("Improper shift amount (%lu)"),
9646 (unsigned long) imm_expr.X_add_number);
9647 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9648 imm_expr.X_op = O_absent;
9652 case '>': /* shift amount minus 32 */
9653 my_getExpression (&imm_expr, s);
9654 check_absolute_expr (ip, &imm_expr);
9655 if ((unsigned long) imm_expr.X_add_number < 32
9656 || (unsigned long) imm_expr.X_add_number > 63)
9658 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32);
9659 imm_expr.X_op = O_absent;
9663 case 'k': /* CACHE code. */
9664 case 'h': /* PREFX code. */
9665 case '1': /* SYNC type. */
9666 my_getExpression (&imm_expr, s);
9667 check_absolute_expr (ip, &imm_expr);
9668 if ((unsigned long) imm_expr.X_add_number > 31)
9669 as_warn (_("Invalid value for `%s' (%lu)"),
9671 (unsigned long) imm_expr.X_add_number);
9674 if (mips_fix_cn63xxp1 && strcmp ("pref", insn->name) == 0)
9675 switch (imm_expr.X_add_number)
9684 case 31: /* These are ok. */
9687 default: /* The rest must be changed to 28. */
9688 imm_expr.X_add_number = 28;
9691 INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number);
9693 else if (*args == 'h')
9694 INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number);
9696 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9697 imm_expr.X_op = O_absent;
9701 case 'c': /* BREAK code. */
9702 my_getExpression (&imm_expr, s);
9703 check_absolute_expr (ip, &imm_expr);
9704 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE)
9705 as_warn (_("Code for %s not in range 0..1023 (%lu)"),
9707 (unsigned long) imm_expr.X_add_number);
9708 INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number);
9709 imm_expr.X_op = O_absent;
9713 case 'q': /* Lower BREAK code. */
9714 my_getExpression (&imm_expr, s);
9715 check_absolute_expr (ip, &imm_expr);
9716 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2)
9717 as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
9719 (unsigned long) imm_expr.X_add_number);
9720 INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number);
9721 imm_expr.X_op = O_absent;
9725 case 'B': /* 20-bit SYSCALL/BREAK code. */
9726 my_getExpression (&imm_expr, s);
9727 check_absolute_expr (ip, &imm_expr);
9728 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
9729 as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
9731 (unsigned long) imm_expr.X_add_number);
9732 INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number);
9733 imm_expr.X_op = O_absent;
9737 case 'C': /* Coprocessor code. */
9738 my_getExpression (&imm_expr, s);
9739 check_absolute_expr (ip, &imm_expr);
9740 if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ)
9742 as_warn (_("Coproccesor code > 25 bits (%lu)"),
9743 (unsigned long) imm_expr.X_add_number);
9744 imm_expr.X_add_number &= OP_MASK_COPZ;
9746 INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number);
9747 imm_expr.X_op = O_absent;
9751 case 'J': /* 19-bit WAIT code. */
9752 my_getExpression (&imm_expr, s);
9753 check_absolute_expr (ip, &imm_expr);
9754 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
9756 as_warn (_("Illegal 19-bit code (%lu)"),
9757 (unsigned long) imm_expr.X_add_number);
9758 imm_expr.X_add_number &= OP_MASK_CODE19;
9760 INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number);
9761 imm_expr.X_op = O_absent;
9765 case 'P': /* Performance register. */
9766 my_getExpression (&imm_expr, s);
9767 check_absolute_expr (ip, &imm_expr);
9768 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
9769 as_warn (_("Invalid performance register (%lu)"),
9770 (unsigned long) imm_expr.X_add_number);
9771 INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number);
9772 imm_expr.X_op = O_absent;
9776 case 'G': /* Coprocessor destination register. */
9777 if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0)
9778 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, ®no);
9780 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
9781 INSERT_OPERAND (RD, *ip, regno);
9790 case 'b': /* Base register. */
9791 case 'd': /* Destination register. */
9792 case 's': /* Source register. */
9793 case 't': /* Target register. */
9794 case 'r': /* Both target and source. */
9795 case 'v': /* Both dest and source. */
9796 case 'w': /* Both dest and target. */
9797 case 'E': /* Coprocessor target register. */
9798 case 'K': /* RDHWR destination register. */
9799 case 'x': /* Ignore register name. */
9800 case 'z': /* Must be zero register. */
9801 case 'U': /* Destination register (CLO/CLZ). */
9802 case 'g': /* Coprocessor destination register. */
9804 if (*args == 'E' || *args == 'K')
9805 ok = reg_lookup (&s, RTYPE_NUM, ®no);
9808 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
9809 if (regno == AT && mips_opts.at)
9811 if (mips_opts.at == ATREG)
9812 as_warn (_("Used $at without \".set noat\""));
9814 as_warn (_("Used $%u with \".set at=$%u\""),
9815 regno, mips_opts.at);
9825 if (c == 'r' || c == 'v' || c == 'w')
9832 /* 'z' only matches $0. */
9833 if (c == 'z' && regno != 0)
9836 if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
9838 if (regno == lastregno)
9841 = _("Source and destination must be different");
9844 if (regno == 31 && lastregno == 0xffffffff)
9847 = _("A destination register must be supplied");
9851 /* Now that we have assembled one operand, we use the args
9852 string to figure out where it goes in the instruction. */
9859 INSERT_OPERAND (RS, *ip, regno);
9864 INSERT_OPERAND (RD, *ip, regno);
9867 INSERT_OPERAND (RD, *ip, regno);
9868 INSERT_OPERAND (RT, *ip, regno);
9873 INSERT_OPERAND (RT, *ip, regno);
9876 /* This case exists because on the r3000 trunc
9877 expands into a macro which requires a gp
9878 register. On the r6000 or r4000 it is
9879 assembled into a single instruction which
9880 ignores the register. Thus the insn version
9881 is MIPS_ISA2 and uses 'x', and the macro
9882 version is MIPS_ISA1 and uses 't'. */
9885 /* This case is for the div instruction, which
9886 acts differently if the destination argument
9887 is $0. This only matches $0, and is checked
9888 outside the switch. */
9898 INSERT_OPERAND (RS, *ip, lastregno);
9901 INSERT_OPERAND (RT, *ip, lastregno);
9906 case 'O': /* MDMX alignment immediate constant. */
9907 my_getExpression (&imm_expr, s);
9908 check_absolute_expr (ip, &imm_expr);
9909 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
9910 as_warn (_("Improper align amount (%ld), using low bits"),
9911 (long) imm_expr.X_add_number);
9912 INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number);
9913 imm_expr.X_op = O_absent;
9917 case 'Q': /* MDMX vector, element sel, or const. */
9920 /* MDMX Immediate. */
9921 my_getExpression (&imm_expr, s);
9922 check_absolute_expr (ip, &imm_expr);
9923 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
9924 as_warn (_("Invalid MDMX Immediate (%ld)"),
9925 (long) imm_expr.X_add_number);
9926 INSERT_OPERAND (FT, *ip, imm_expr.X_add_number);
9927 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
9928 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
9930 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
9931 imm_expr.X_op = O_absent;
9935 /* Not MDMX Immediate. Fall through. */
9936 case 'X': /* MDMX destination register. */
9937 case 'Y': /* MDMX source register. */
9938 case 'Z': /* MDMX target register. */
9940 case 'D': /* Floating point destination register. */
9941 case 'S': /* Floating point source register. */
9942 case 'T': /* Floating point target register. */
9943 case 'R': /* Floating point source register. */
9948 || (mips_opts.ase_mdmx
9949 && (ip->insn_mo->pinfo & FP_D)
9950 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
9951 | INSN_COPROC_MEMORY_DELAY
9952 | INSN_LOAD_COPROC_DELAY
9953 | INSN_LOAD_MEMORY_DELAY
9954 | INSN_STORE_MEMORY))))
9957 if (reg_lookup (&s, rtype, ®no))
9959 if ((regno & 1) != 0
9961 && !mips_oddfpreg_ok (ip->insn_mo, argnum))
9962 as_warn (_("Float register should be even, was %d"),
9970 if (c == 'V' || c == 'W')
9981 INSERT_OPERAND (FD, *ip, regno);
9986 INSERT_OPERAND (FS, *ip, regno);
9989 /* This is like 'Z', but also needs to fix the MDMX
9990 vector/scalar select bits. Note that the
9991 scalar immediate case is handled above. */
9994 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
9995 int max_el = (is_qh ? 3 : 7);
9997 my_getExpression(&imm_expr, s);
9998 check_absolute_expr (ip, &imm_expr);
10000 if (imm_expr.X_add_number > max_el)
10001 as_bad (_("Bad element selector %ld"),
10002 (long) imm_expr.X_add_number);
10003 imm_expr.X_add_number &= max_el;
10004 ip->insn_opcode |= (imm_expr.X_add_number
10007 imm_expr.X_op = O_absent;
10009 as_warn (_("Expecting ']' found '%s'"), s);
10015 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
10016 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
10019 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
10022 /* Fall through. */
10026 INSERT_OPERAND (FT, *ip, regno);
10029 INSERT_OPERAND (FR, *ip, regno);
10039 INSERT_OPERAND (FS, *ip, lastregno);
10042 INSERT_OPERAND (FT, *ip, lastregno);
10048 my_getExpression (&imm_expr, s);
10049 if (imm_expr.X_op != O_big
10050 && imm_expr.X_op != O_constant)
10051 insn_error = _("absolute expression required");
10052 if (HAVE_32BIT_GPRS)
10053 normalize_constant_expr (&imm_expr);
10058 my_getExpression (&offset_expr, s);
10059 normalize_address_expr (&offset_expr);
10060 *imm_reloc = BFD_RELOC_32;
10073 unsigned char temp[8];
10075 unsigned int length;
10080 /* These only appear as the last operand in an
10081 instruction, and every instruction that accepts
10082 them in any variant accepts them in all variants.
10083 This means we don't have to worry about backing out
10084 any changes if the instruction does not match.
10086 The difference between them is the size of the
10087 floating point constant and where it goes. For 'F'
10088 and 'L' the constant is 64 bits; for 'f' and 'l' it
10089 is 32 bits. Where the constant is placed is based
10090 on how the MIPS assembler does things:
10093 f -- immediate value
10096 The .lit4 and .lit8 sections are only used if
10097 permitted by the -G argument.
10099 The code below needs to know whether the target register
10100 is 32 or 64 bits wide. It relies on the fact 'f' and
10101 'F' are used with GPR-based instructions and 'l' and
10102 'L' are used with FPR-based instructions. */
10104 f64 = *args == 'F' || *args == 'L';
10105 using_gprs = *args == 'F' || *args == 'f';
10107 save_in = input_line_pointer;
10108 input_line_pointer = s;
10109 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
10111 s = input_line_pointer;
10112 input_line_pointer = save_in;
10113 if (err != NULL && *err != '\0')
10115 as_bad (_("Bad floating point constant: %s"), err);
10116 memset (temp, '\0', sizeof temp);
10117 length = f64 ? 8 : 4;
10120 gas_assert (length == (unsigned) (f64 ? 8 : 4));
10124 && (g_switch_value < 4
10125 || (temp[0] == 0 && temp[1] == 0)
10126 || (temp[2] == 0 && temp[3] == 0))))
10128 imm_expr.X_op = O_constant;
10129 if (!target_big_endian)
10130 imm_expr.X_add_number = bfd_getl32 (temp);
10132 imm_expr.X_add_number = bfd_getb32 (temp);
10134 else if (length > 4
10135 && !mips_disable_float_construction
10136 /* Constants can only be constructed in GPRs and
10137 copied to FPRs if the GPRs are at least as wide
10138 as the FPRs. Force the constant into memory if
10139 we are using 64-bit FPRs but the GPRs are only
10142 || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
10143 && ((temp[0] == 0 && temp[1] == 0)
10144 || (temp[2] == 0 && temp[3] == 0))
10145 && ((temp[4] == 0 && temp[5] == 0)
10146 || (temp[6] == 0 && temp[7] == 0)))
10148 /* The value is simple enough to load with a couple of
10149 instructions. If using 32-bit registers, set
10150 imm_expr to the high order 32 bits and offset_expr to
10151 the low order 32 bits. Otherwise, set imm_expr to
10152 the entire 64 bit constant. */
10153 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
10155 imm_expr.X_op = O_constant;
10156 offset_expr.X_op = O_constant;
10157 if (!target_big_endian)
10159 imm_expr.X_add_number = bfd_getl32 (temp + 4);
10160 offset_expr.X_add_number = bfd_getl32 (temp);
10164 imm_expr.X_add_number = bfd_getb32 (temp);
10165 offset_expr.X_add_number = bfd_getb32 (temp + 4);
10167 if (offset_expr.X_add_number == 0)
10168 offset_expr.X_op = O_absent;
10170 else if (sizeof (imm_expr.X_add_number) > 4)
10172 imm_expr.X_op = O_constant;
10173 if (!target_big_endian)
10174 imm_expr.X_add_number = bfd_getl64 (temp);
10176 imm_expr.X_add_number = bfd_getb64 (temp);
10180 imm_expr.X_op = O_big;
10181 imm_expr.X_add_number = 4;
10182 if (!target_big_endian)
10184 generic_bignum[0] = bfd_getl16 (temp);
10185 generic_bignum[1] = bfd_getl16 (temp + 2);
10186 generic_bignum[2] = bfd_getl16 (temp + 4);
10187 generic_bignum[3] = bfd_getl16 (temp + 6);
10191 generic_bignum[0] = bfd_getb16 (temp + 6);
10192 generic_bignum[1] = bfd_getb16 (temp + 4);
10193 generic_bignum[2] = bfd_getb16 (temp + 2);
10194 generic_bignum[3] = bfd_getb16 (temp);
10200 const char *newname;
10203 /* Switch to the right section. */
10205 subseg = now_subseg;
10208 default: /* unused default case avoids warnings. */
10210 newname = RDATA_SECTION_NAME;
10211 if (g_switch_value >= 8)
10215 newname = RDATA_SECTION_NAME;
10218 gas_assert (g_switch_value >= 4);
10222 new_seg = subseg_new (newname, (subsegT) 0);
10224 bfd_set_section_flags (stdoutput, new_seg,
10229 frag_align (*args == 'l' ? 2 : 3, 0, 0);
10230 if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0)
10231 record_alignment (new_seg, 4);
10233 record_alignment (new_seg, *args == 'l' ? 2 : 3);
10234 if (seg == now_seg)
10235 as_bad (_("Can't use floating point insn in this section"));
10237 /* Set the argument to the current address in the
10239 offset_expr.X_op = O_symbol;
10240 offset_expr.X_add_symbol = symbol_temp_new_now ();
10241 offset_expr.X_add_number = 0;
10243 /* Put the floating point number into the section. */
10244 p = frag_more ((int) length);
10245 memcpy (p, temp, length);
10247 /* Switch back to the original section. */
10248 subseg_set (seg, subseg);
10253 case 'i': /* 16-bit unsigned immediate. */
10254 case 'j': /* 16-bit signed immediate. */
10255 *imm_reloc = BFD_RELOC_LO16;
10256 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
10259 offsetT minval, maxval;
10261 more = (insn + 1 < &mips_opcodes[NUMOPCODES]
10262 && strcmp (insn->name, insn[1].name) == 0);
10264 /* If the expression was written as an unsigned number,
10265 only treat it as signed if there are no more
10269 && sizeof (imm_expr.X_add_number) <= 4
10270 && imm_expr.X_op == O_constant
10271 && imm_expr.X_add_number < 0
10272 && imm_expr.X_unsigned
10273 && HAVE_64BIT_GPRS)
10276 /* For compatibility with older assemblers, we accept
10277 0x8000-0xffff as signed 16-bit numbers when only
10278 signed numbers are allowed. */
10280 minval = 0, maxval = 0xffff;
10282 minval = -0x8000, maxval = 0x7fff;
10284 minval = -0x8000, maxval = 0xffff;
10286 if (imm_expr.X_op != O_constant
10287 || imm_expr.X_add_number < minval
10288 || imm_expr.X_add_number > maxval)
10292 if (imm_expr.X_op == O_constant
10293 || imm_expr.X_op == O_big)
10294 as_bad (_("Expression out of range"));
10300 case 'o': /* 16-bit offset. */
10301 offset_reloc[0] = BFD_RELOC_LO16;
10302 offset_reloc[1] = BFD_RELOC_UNUSED;
10303 offset_reloc[2] = BFD_RELOC_UNUSED;
10305 /* Check whether there is only a single bracketed expression
10306 left. If so, it must be the base register and the
10307 constant must be zero. */
10308 if (*s == '(' && strchr (s + 1, '(') == 0)
10310 offset_expr.X_op = O_constant;
10311 offset_expr.X_add_number = 0;
10315 /* If this value won't fit into a 16 bit offset, then go
10316 find a macro that will generate the 32 bit offset
10318 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
10319 && (offset_expr.X_op != O_constant
10320 || offset_expr.X_add_number >= 0x8000
10321 || offset_expr.X_add_number < -0x8000))
10327 case 'p': /* PC-relative offset. */
10328 *offset_reloc = BFD_RELOC_16_PCREL_S2;
10329 my_getExpression (&offset_expr, s);
10333 case 'u': /* Upper 16 bits. */
10334 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
10335 && imm_expr.X_op == O_constant
10336 && (imm_expr.X_add_number < 0
10337 || imm_expr.X_add_number >= 0x10000))
10338 as_bad (_("lui expression (%lu) not in range 0..65535"),
10339 (unsigned long) imm_expr.X_add_number);
10343 case 'a': /* 26-bit address. */
10344 my_getExpression (&offset_expr, s);
10346 *offset_reloc = BFD_RELOC_MIPS_JMP;
10349 case 'N': /* 3-bit branch condition code. */
10350 case 'M': /* 3-bit compare condition code. */
10352 if (ip->insn_mo->pinfo & (FP_D | FP_S))
10353 rtype |= RTYPE_FCC;
10354 if (!reg_lookup (&s, rtype, ®no))
10356 if ((strcmp (str + strlen (str) - 3, ".ps") == 0
10357 || strcmp (str + strlen (str) - 5, "any2f") == 0
10358 || strcmp (str + strlen (str) - 5, "any2t") == 0)
10359 && (regno & 1) != 0)
10360 as_warn (_("Condition code register should be even for %s, "
10363 if ((strcmp (str + strlen (str) - 5, "any4f") == 0
10364 || strcmp (str + strlen (str) - 5, "any4t") == 0)
10365 && (regno & 3) != 0)
10366 as_warn (_("Condition code register should be 0 or 4 for %s, "
10370 INSERT_OPERAND (BCC, *ip, regno);
10372 INSERT_OPERAND (CCC, *ip, regno);
10376 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
10387 while (ISDIGIT (*s));
10390 c = 8; /* Invalid sel value. */
10393 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
10394 ip->insn_opcode |= c;
10398 /* Must be at least one digit. */
10399 my_getExpression (&imm_expr, s);
10400 check_absolute_expr (ip, &imm_expr);
10402 if ((unsigned long) imm_expr.X_add_number
10403 > (unsigned long) OP_MASK_VECBYTE)
10405 as_bad (_("bad byte vector index (%ld)"),
10406 (long) imm_expr.X_add_number);
10407 imm_expr.X_add_number = 0;
10410 INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number);
10411 imm_expr.X_op = O_absent;
10416 my_getExpression (&imm_expr, s);
10417 check_absolute_expr (ip, &imm_expr);
10419 if ((unsigned long) imm_expr.X_add_number
10420 > (unsigned long) OP_MASK_VECALIGN)
10422 as_bad (_("bad byte vector index (%ld)"),
10423 (long) imm_expr.X_add_number);
10424 imm_expr.X_add_number = 0;
10427 INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number);
10428 imm_expr.X_op = O_absent;
10433 as_bad (_("Bad char = '%c'\n"), *args);
10438 /* Args don't match. */
10439 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
10440 !strcmp (insn->name, insn[1].name))
10444 insn_error = _("Illegal operands");
10448 *(--argsStart) = save_c;
10449 insn_error = _("Illegal operands");
10454 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
10456 /* This routine assembles an instruction into its binary format when
10457 assembling for the mips16. As a side effect, it sets one of the
10458 global variables imm_reloc or offset_reloc to the type of
10459 relocation to do if one of the operands is an address expression.
10460 It also sets mips16_small and mips16_ext if the user explicitly
10461 requested a small or extended instruction. */
10464 mips16_ip (char *str, struct mips_cl_insn *ip)
10468 struct mips_opcode *insn;
10470 unsigned int regno;
10471 unsigned int lastregno = 0;
10477 mips16_small = FALSE;
10478 mips16_ext = FALSE;
10480 for (s = str; ISLOWER (*s); ++s)
10492 if (s[1] == 't' && s[2] == ' ')
10495 mips16_small = TRUE;
10499 else if (s[1] == 'e' && s[2] == ' ')
10506 /* Fall through. */
10508 insn_error = _("unknown opcode");
10512 if (mips_opts.noautoextend && ! mips16_ext)
10513 mips16_small = TRUE;
10515 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
10517 insn_error = _("unrecognized opcode");
10526 gas_assert (strcmp (insn->name, str) == 0);
10528 ok = is_opcode_valid_16 (insn);
10531 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
10532 && strcmp (insn->name, insn[1].name) == 0)
10541 static char buf[100];
10543 _("opcode not supported on this processor: %s (%s)"),
10544 mips_cpu_info_from_arch (mips_opts.arch)->name,
10545 mips_cpu_info_from_isa (mips_opts.isa)->name);
10552 create_insn (ip, insn);
10553 imm_expr.X_op = O_absent;
10554 imm_reloc[0] = BFD_RELOC_UNUSED;
10555 imm_reloc[1] = BFD_RELOC_UNUSED;
10556 imm_reloc[2] = BFD_RELOC_UNUSED;
10557 imm2_expr.X_op = O_absent;
10558 offset_expr.X_op = O_absent;
10559 offset_reloc[0] = BFD_RELOC_UNUSED;
10560 offset_reloc[1] = BFD_RELOC_UNUSED;
10561 offset_reloc[2] = BFD_RELOC_UNUSED;
10562 for (args = insn->args; 1; ++args)
10569 /* In this switch statement we call break if we did not find
10570 a match, continue if we did find a match, or return if we
10579 /* Stuff the immediate value in now, if we can. */
10580 if (imm_expr.X_op == O_constant
10581 && *imm_reloc > BFD_RELOC_UNUSED
10582 && *imm_reloc != BFD_RELOC_MIPS16_GOT16
10583 && *imm_reloc != BFD_RELOC_MIPS16_CALL16
10584 && insn->pinfo != INSN_MACRO)
10588 switch (*offset_reloc)
10590 case BFD_RELOC_MIPS16_HI16_S:
10591 tmp = (imm_expr.X_add_number + 0x8000) >> 16;
10594 case BFD_RELOC_MIPS16_HI16:
10595 tmp = imm_expr.X_add_number >> 16;
10598 case BFD_RELOC_MIPS16_LO16:
10599 tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff)
10603 case BFD_RELOC_UNUSED:
10604 tmp = imm_expr.X_add_number;
10610 *offset_reloc = BFD_RELOC_UNUSED;
10612 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
10613 tmp, TRUE, mips16_small,
10614 mips16_ext, &ip->insn_opcode,
10615 &ip->use_extend, &ip->extend);
10616 imm_expr.X_op = O_absent;
10617 *imm_reloc = BFD_RELOC_UNUSED;
10631 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10634 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10650 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10652 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10656 /* Fall through. */
10667 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
10669 if (c == 'v' || c == 'w')
10672 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10674 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10685 if (c == 'v' || c == 'w')
10687 regno = mips16_to_32_reg_map[lastregno];
10701 regno = mips32_to_16_reg_map[regno];
10706 regno = ILLEGAL_REG;
10711 regno = ILLEGAL_REG;
10716 regno = ILLEGAL_REG;
10721 if (regno == AT && mips_opts.at)
10723 if (mips_opts.at == ATREG)
10724 as_warn (_("used $at without \".set noat\""));
10726 as_warn (_("used $%u with \".set at=$%u\""),
10727 regno, mips_opts.at);
10735 if (regno == ILLEGAL_REG)
10742 MIPS16_INSERT_OPERAND (RX, *ip, regno);
10746 MIPS16_INSERT_OPERAND (RY, *ip, regno);
10749 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
10752 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
10758 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
10761 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
10762 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
10772 if (strncmp (s, "$pc", 3) == 0)
10789 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
10792 if (imm_expr.X_op != O_constant)
10795 ip->use_extend = TRUE;
10800 /* We need to relax this instruction. */
10801 *offset_reloc = *imm_reloc;
10802 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10807 *imm_reloc = BFD_RELOC_UNUSED;
10808 /* Fall through. */
10815 my_getExpression (&imm_expr, s);
10816 if (imm_expr.X_op == O_register)
10818 /* What we thought was an expression turned out to
10821 if (s[0] == '(' && args[1] == '(')
10823 /* It looks like the expression was omitted
10824 before a register indirection, which means
10825 that the expression is implicitly zero. We
10826 still set up imm_expr, so that we handle
10827 explicit extensions correctly. */
10828 imm_expr.X_op = O_constant;
10829 imm_expr.X_add_number = 0;
10830 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10837 /* We need to relax this instruction. */
10838 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10847 /* We use offset_reloc rather than imm_reloc for the PC
10848 relative operands. This lets macros with both
10849 immediate and address operands work correctly. */
10850 my_getExpression (&offset_expr, s);
10852 if (offset_expr.X_op == O_register)
10855 /* We need to relax this instruction. */
10856 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
10860 case '6': /* break code */
10861 my_getExpression (&imm_expr, s);
10862 check_absolute_expr (ip, &imm_expr);
10863 if ((unsigned long) imm_expr.X_add_number > 63)
10864 as_warn (_("Invalid value for `%s' (%lu)"),
10866 (unsigned long) imm_expr.X_add_number);
10867 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
10868 imm_expr.X_op = O_absent;
10872 case 'a': /* 26 bit address */
10873 my_getExpression (&offset_expr, s);
10875 *offset_reloc = BFD_RELOC_MIPS16_JMP;
10876 ip->insn_opcode <<= 16;
10879 case 'l': /* register list for entry macro */
10880 case 'L': /* register list for exit macro */
10890 unsigned int freg, reg1, reg2;
10892 while (*s == ' ' || *s == ',')
10894 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
10896 else if (reg_lookup (&s, RTYPE_FPU, ®1))
10900 as_bad (_("can't parse register list"));
10910 if (!reg_lookup (&s, freg ? RTYPE_FPU
10911 : (RTYPE_GP | RTYPE_NUM), ®2))
10913 as_bad (_("invalid register list"));
10917 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
10919 mask &= ~ (7 << 3);
10922 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
10924 mask &= ~ (7 << 3);
10927 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
10928 mask |= (reg2 - 3) << 3;
10929 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
10930 mask |= (reg2 - 15) << 1;
10931 else if (reg1 == RA && reg2 == RA)
10935 as_bad (_("invalid register list"));
10939 /* The mask is filled in in the opcode table for the
10940 benefit of the disassembler. We remove it before
10941 applying the actual mask. */
10942 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
10943 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
10947 case 'm': /* Register list for save insn. */
10948 case 'M': /* Register list for restore insn. */
10951 int framesz = 0, seen_framesz = 0;
10952 int nargs = 0, statics = 0, sregs = 0;
10956 unsigned int reg1, reg2;
10958 SKIP_SPACE_TABS (s);
10961 SKIP_SPACE_TABS (s);
10963 my_getExpression (&imm_expr, s);
10964 if (imm_expr.X_op == O_constant)
10966 /* Handle the frame size. */
10969 as_bad (_("more than one frame size in list"));
10973 framesz = imm_expr.X_add_number;
10974 imm_expr.X_op = O_absent;
10979 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
10981 as_bad (_("can't parse register list"));
10993 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2)
10996 as_bad (_("can't parse register list"));
11001 while (reg1 <= reg2)
11003 if (reg1 >= 4 && reg1 <= 7)
11007 nargs |= 1 << (reg1 - 4);
11009 /* statics $a0-$a3 */
11010 statics |= 1 << (reg1 - 4);
11012 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
11015 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
11017 else if (reg1 == 31)
11019 /* Add $ra to insn. */
11024 as_bad (_("unexpected register in list"));
11032 /* Encode args/statics combination. */
11033 if (nargs & statics)
11034 as_bad (_("arg/static registers overlap"));
11035 else if (nargs == 0xf)
11036 /* All $a0-$a3 are args. */
11037 opcode |= MIPS16_ALL_ARGS << 16;
11038 else if (statics == 0xf)
11039 /* All $a0-$a3 are statics. */
11040 opcode |= MIPS16_ALL_STATICS << 16;
11043 int narg = 0, nstat = 0;
11045 /* Count arg registers. */
11046 while (nargs & 0x1)
11052 as_bad (_("invalid arg register list"));
11054 /* Count static registers. */
11055 while (statics & 0x8)
11057 statics = (statics << 1) & 0xf;
11061 as_bad (_("invalid static register list"));
11063 /* Encode args/statics. */
11064 opcode |= ((narg << 2) | nstat) << 16;
11067 /* Encode $s0/$s1. */
11068 if (sregs & (1 << 0)) /* $s0 */
11070 if (sregs & (1 << 1)) /* $s1 */
11076 /* Count regs $s2-$s8. */
11084 as_bad (_("invalid static register list"));
11085 /* Encode $s2-$s8. */
11086 opcode |= nsreg << 24;
11089 /* Encode frame size. */
11091 as_bad (_("missing frame size"));
11092 else if ((framesz & 7) != 0 || framesz < 0
11093 || framesz > 0xff * 8)
11094 as_bad (_("invalid frame size"));
11095 else if (framesz != 128 || (opcode >> 16) != 0)
11098 opcode |= (((framesz & 0xf0) << 16)
11099 | (framesz & 0x0f));
11102 /* Finally build the instruction. */
11103 if ((opcode >> 16) != 0 || framesz == 0)
11105 ip->use_extend = TRUE;
11106 ip->extend = opcode >> 16;
11108 ip->insn_opcode |= opcode & 0x7f;
11112 case 'e': /* extend code */
11113 my_getExpression (&imm_expr, s);
11114 check_absolute_expr (ip, &imm_expr);
11115 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
11117 as_warn (_("Invalid value for `%s' (%lu)"),
11119 (unsigned long) imm_expr.X_add_number);
11120 imm_expr.X_add_number &= 0x7ff;
11122 ip->insn_opcode |= imm_expr.X_add_number;
11123 imm_expr.X_op = O_absent;
11133 /* Args don't match. */
11134 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
11135 strcmp (insn->name, insn[1].name) == 0)
11142 insn_error = _("illegal operands");
11148 /* This structure holds information we know about a mips16 immediate
11151 struct mips16_immed_operand
11153 /* The type code used in the argument string in the opcode table. */
11155 /* The number of bits in the short form of the opcode. */
11157 /* The number of bits in the extended form of the opcode. */
11159 /* The amount by which the short form is shifted when it is used;
11160 for example, the sw instruction has a shift count of 2. */
11162 /* The amount by which the short form is shifted when it is stored
11163 into the instruction code. */
11165 /* Non-zero if the short form is unsigned. */
11167 /* Non-zero if the extended form is unsigned. */
11169 /* Non-zero if the value is PC relative. */
11173 /* The mips16 immediate operand types. */
11175 static const struct mips16_immed_operand mips16_immed_operands[] =
11177 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
11178 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
11179 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
11180 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
11181 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
11182 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
11183 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
11184 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
11185 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
11186 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
11187 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
11188 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
11189 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
11190 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
11191 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
11192 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
11193 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
11194 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
11195 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
11196 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
11197 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
11200 #define MIPS16_NUM_IMMED \
11201 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
11203 /* Handle a mips16 instruction with an immediate value. This or's the
11204 small immediate value into *INSN. It sets *USE_EXTEND to indicate
11205 whether an extended value is needed; if one is needed, it sets
11206 *EXTEND to the value. The argument type is TYPE. The value is VAL.
11207 If SMALL is true, an unextended opcode was explicitly requested.
11208 If EXT is true, an extended opcode was explicitly requested. If
11209 WARN is true, warn if EXT does not match reality. */
11212 mips16_immed (char *file, unsigned int line, int type, offsetT val,
11213 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
11214 unsigned long *insn, bfd_boolean *use_extend,
11215 unsigned short *extend)
11217 const struct mips16_immed_operand *op;
11218 int mintiny, maxtiny;
11219 bfd_boolean needext;
11221 op = mips16_immed_operands;
11222 while (op->type != type)
11225 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
11230 if (type == '<' || type == '>' || type == '[' || type == ']')
11233 maxtiny = 1 << op->nbits;
11238 maxtiny = (1 << op->nbits) - 1;
11243 mintiny = - (1 << (op->nbits - 1));
11244 maxtiny = (1 << (op->nbits - 1)) - 1;
11247 /* Branch offsets have an implicit 0 in the lowest bit. */
11248 if (type == 'p' || type == 'q')
11251 if ((val & ((1 << op->shift) - 1)) != 0
11252 || val < (mintiny << op->shift)
11253 || val > (maxtiny << op->shift))
11258 if (warn && ext && ! needext)
11259 as_warn_where (file, line,
11260 _("extended operand requested but not required"));
11261 if (small && needext)
11262 as_bad_where (file, line, _("invalid unextended operand value"));
11264 if (small || (! ext && ! needext))
11268 *use_extend = FALSE;
11269 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
11270 insnval <<= op->op_shift;
11275 long minext, maxext;
11281 maxext = (1 << op->extbits) - 1;
11285 minext = - (1 << (op->extbits - 1));
11286 maxext = (1 << (op->extbits - 1)) - 1;
11288 if (val < minext || val > maxext)
11289 as_bad_where (file, line,
11290 _("operand value out of range for instruction"));
11292 *use_extend = TRUE;
11293 if (op->extbits == 16)
11295 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
11298 else if (op->extbits == 15)
11300 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
11305 extval = ((val & 0x1f) << 6) | (val & 0x20);
11309 *extend = (unsigned short) extval;
11314 struct percent_op_match
11317 bfd_reloc_code_real_type reloc;
11320 static const struct percent_op_match mips_percent_op[] =
11322 {"%lo", BFD_RELOC_LO16},
11324 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
11325 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
11326 {"%call16", BFD_RELOC_MIPS_CALL16},
11327 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
11328 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
11329 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
11330 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
11331 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
11332 {"%got", BFD_RELOC_MIPS_GOT16},
11333 {"%gp_rel", BFD_RELOC_GPREL16},
11334 {"%half", BFD_RELOC_16},
11335 {"%highest", BFD_RELOC_MIPS_HIGHEST},
11336 {"%higher", BFD_RELOC_MIPS_HIGHER},
11337 {"%neg", BFD_RELOC_MIPS_SUB},
11338 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
11339 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
11340 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
11341 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
11342 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
11343 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
11344 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
11346 {"%hi", BFD_RELOC_HI16_S}
11349 static const struct percent_op_match mips16_percent_op[] =
11351 {"%lo", BFD_RELOC_MIPS16_LO16},
11352 {"%gprel", BFD_RELOC_MIPS16_GPREL},
11353 {"%got", BFD_RELOC_MIPS16_GOT16},
11354 {"%call16", BFD_RELOC_MIPS16_CALL16},
11355 {"%hi", BFD_RELOC_MIPS16_HI16_S}
11359 /* Return true if *STR points to a relocation operator. When returning true,
11360 move *STR over the operator and store its relocation code in *RELOC.
11361 Leave both *STR and *RELOC alone when returning false. */
11364 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
11366 const struct percent_op_match *percent_op;
11369 if (mips_opts.mips16)
11371 percent_op = mips16_percent_op;
11372 limit = ARRAY_SIZE (mips16_percent_op);
11376 percent_op = mips_percent_op;
11377 limit = ARRAY_SIZE (mips_percent_op);
11380 for (i = 0; i < limit; i++)
11381 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
11383 int len = strlen (percent_op[i].str);
11385 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
11388 *str += strlen (percent_op[i].str);
11389 *reloc = percent_op[i].reloc;
11391 /* Check whether the output BFD supports this relocation.
11392 If not, issue an error and fall back on something safe. */
11393 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
11395 as_bad (_("relocation %s isn't supported by the current ABI"),
11396 percent_op[i].str);
11397 *reloc = BFD_RELOC_UNUSED;
11405 /* Parse string STR as a 16-bit relocatable operand. Store the
11406 expression in *EP and the relocations in the array starting
11407 at RELOC. Return the number of relocation operators used.
11409 On exit, EXPR_END points to the first character after the expression. */
11412 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
11415 bfd_reloc_code_real_type reversed_reloc[3];
11416 size_t reloc_index, i;
11417 int crux_depth, str_depth;
11420 /* Search for the start of the main expression, recoding relocations
11421 in REVERSED_RELOC. End the loop with CRUX pointing to the start
11422 of the main expression and with CRUX_DEPTH containing the number
11423 of open brackets at that point. */
11430 crux_depth = str_depth;
11432 /* Skip over whitespace and brackets, keeping count of the number
11434 while (*str == ' ' || *str == '\t' || *str == '(')
11439 && reloc_index < (HAVE_NEWABI ? 3 : 1)
11440 && parse_relocation (&str, &reversed_reloc[reloc_index]));
11442 my_getExpression (ep, crux);
11445 /* Match every open bracket. */
11446 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
11450 if (crux_depth > 0)
11451 as_bad (_("unclosed '('"));
11455 if (reloc_index != 0)
11457 prev_reloc_op_frag = frag_now;
11458 for (i = 0; i < reloc_index; i++)
11459 reloc[i] = reversed_reloc[reloc_index - 1 - i];
11462 return reloc_index;
11466 my_getExpression (expressionS *ep, char *str)
11470 save_in = input_line_pointer;
11471 input_line_pointer = str;
11473 expr_end = input_line_pointer;
11474 input_line_pointer = save_in;
11478 md_atof (int type, char *litP, int *sizeP)
11480 return ieee_md_atof (type, litP, sizeP, target_big_endian);
11484 md_number_to_chars (char *buf, valueT val, int n)
11486 if (target_big_endian)
11487 number_to_chars_bigendian (buf, val, n);
11489 number_to_chars_littleendian (buf, val, n);
11493 static int support_64bit_objects(void)
11495 const char **list, **l;
11498 list = bfd_target_list ();
11499 for (l = list; *l != NULL; l++)
11500 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
11501 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
11503 yes = (*l != NULL);
11507 #endif /* OBJ_ELF */
11509 const char *md_shortopts = "O::g::G:";
11513 OPTION_MARCH = OPTION_MD_BASE,
11535 OPTION_NO_SMARTMIPS,
11538 OPTION_COMPAT_ARCH_BASE,
11547 OPTION_M7000_HILO_FIX,
11548 OPTION_MNO_7000_HILO_FIX,
11551 OPTION_FIX_LOONGSON2F_JUMP,
11552 OPTION_NO_FIX_LOONGSON2F_JUMP,
11553 OPTION_FIX_LOONGSON2F_NOP,
11554 OPTION_NO_FIX_LOONGSON2F_NOP,
11556 OPTION_NO_FIX_VR4120,
11558 OPTION_NO_FIX_VR4130,
11559 OPTION_FIX_CN63XXP1,
11560 OPTION_NO_FIX_CN63XXP1,
11567 OPTION_CONSTRUCT_FLOATS,
11568 OPTION_NO_CONSTRUCT_FLOATS,
11571 OPTION_RELAX_BRANCH,
11572 OPTION_NO_RELAX_BRANCH,
11579 OPTION_SINGLE_FLOAT,
11580 OPTION_DOUBLE_FLOAT,
11583 OPTION_CALL_SHARED,
11584 OPTION_CALL_NONPIC,
11594 OPTION_MVXWORKS_PIC,
11595 #endif /* OBJ_ELF */
11599 struct option md_longopts[] =
11601 /* Options which specify architecture. */
11602 {"march", required_argument, NULL, OPTION_MARCH},
11603 {"mtune", required_argument, NULL, OPTION_MTUNE},
11604 {"mips0", no_argument, NULL, OPTION_MIPS1},
11605 {"mips1", no_argument, NULL, OPTION_MIPS1},
11606 {"mips2", no_argument, NULL, OPTION_MIPS2},
11607 {"mips3", no_argument, NULL, OPTION_MIPS3},
11608 {"mips4", no_argument, NULL, OPTION_MIPS4},
11609 {"mips5", no_argument, NULL, OPTION_MIPS5},
11610 {"mips32", no_argument, NULL, OPTION_MIPS32},
11611 {"mips64", no_argument, NULL, OPTION_MIPS64},
11612 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
11613 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
11615 /* Options which specify Application Specific Extensions (ASEs). */
11616 {"mips16", no_argument, NULL, OPTION_MIPS16},
11617 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
11618 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
11619 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
11620 {"mdmx", no_argument, NULL, OPTION_MDMX},
11621 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
11622 {"mdsp", no_argument, NULL, OPTION_DSP},
11623 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
11624 {"mmt", no_argument, NULL, OPTION_MT},
11625 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
11626 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
11627 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
11628 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
11629 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
11631 /* Old-style architecture options. Don't add more of these. */
11632 {"m4650", no_argument, NULL, OPTION_M4650},
11633 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
11634 {"m4010", no_argument, NULL, OPTION_M4010},
11635 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
11636 {"m4100", no_argument, NULL, OPTION_M4100},
11637 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
11638 {"m3900", no_argument, NULL, OPTION_M3900},
11639 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
11641 /* Options which enable bug fixes. */
11642 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
11643 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
11644 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
11645 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
11646 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
11647 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
11648 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
11649 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
11650 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
11651 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
11652 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
11653 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
11654 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
11655 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
11656 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
11658 /* Miscellaneous options. */
11659 {"trap", no_argument, NULL, OPTION_TRAP},
11660 {"no-break", no_argument, NULL, OPTION_TRAP},
11661 {"break", no_argument, NULL, OPTION_BREAK},
11662 {"no-trap", no_argument, NULL, OPTION_BREAK},
11663 {"EB", no_argument, NULL, OPTION_EB},
11664 {"EL", no_argument, NULL, OPTION_EL},
11665 {"mfp32", no_argument, NULL, OPTION_FP32},
11666 {"mgp32", no_argument, NULL, OPTION_GP32},
11667 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
11668 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
11669 {"mfp64", no_argument, NULL, OPTION_FP64},
11670 {"mgp64", no_argument, NULL, OPTION_GP64},
11671 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
11672 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
11673 {"mshared", no_argument, NULL, OPTION_MSHARED},
11674 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
11675 {"msym32", no_argument, NULL, OPTION_MSYM32},
11676 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
11677 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
11678 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
11679 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
11680 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
11682 /* Strictly speaking this next option is ELF specific,
11683 but we allow it for other ports as well in order to
11684 make testing easier. */
11685 {"32", no_argument, NULL, OPTION_32},
11687 /* ELF-specific options. */
11689 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
11690 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
11691 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
11692 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
11693 {"xgot", no_argument, NULL, OPTION_XGOT},
11694 {"mabi", required_argument, NULL, OPTION_MABI},
11695 {"n32", no_argument, NULL, OPTION_N32},
11696 {"64", no_argument, NULL, OPTION_64},
11697 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
11698 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
11699 {"mpdr", no_argument, NULL, OPTION_PDR},
11700 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
11701 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
11702 #endif /* OBJ_ELF */
11704 {NULL, no_argument, NULL, 0}
11706 size_t md_longopts_size = sizeof (md_longopts);
11708 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
11709 NEW_VALUE. Warn if another value was already specified. Note:
11710 we have to defer parsing the -march and -mtune arguments in order
11711 to handle 'from-abi' correctly, since the ABI might be specified
11712 in a later argument. */
11715 mips_set_option_string (const char **string_ptr, const char *new_value)
11717 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
11718 as_warn (_("A different %s was already specified, is now %s"),
11719 string_ptr == &mips_arch_string ? "-march" : "-mtune",
11722 *string_ptr = new_value;
11726 md_parse_option (int c, char *arg)
11730 case OPTION_CONSTRUCT_FLOATS:
11731 mips_disable_float_construction = 0;
11734 case OPTION_NO_CONSTRUCT_FLOATS:
11735 mips_disable_float_construction = 1;
11747 target_big_endian = 1;
11751 target_big_endian = 0;
11757 else if (arg[0] == '0')
11759 else if (arg[0] == '1')
11769 mips_debug = atoi (arg);
11773 file_mips_isa = ISA_MIPS1;
11777 file_mips_isa = ISA_MIPS2;
11781 file_mips_isa = ISA_MIPS3;
11785 file_mips_isa = ISA_MIPS4;
11789 file_mips_isa = ISA_MIPS5;
11792 case OPTION_MIPS32:
11793 file_mips_isa = ISA_MIPS32;
11796 case OPTION_MIPS32R2:
11797 file_mips_isa = ISA_MIPS32R2;
11800 case OPTION_MIPS64R2:
11801 file_mips_isa = ISA_MIPS64R2;
11804 case OPTION_MIPS64:
11805 file_mips_isa = ISA_MIPS64;
11809 mips_set_option_string (&mips_tune_string, arg);
11813 mips_set_option_string (&mips_arch_string, arg);
11817 mips_set_option_string (&mips_arch_string, "4650");
11818 mips_set_option_string (&mips_tune_string, "4650");
11821 case OPTION_NO_M4650:
11825 mips_set_option_string (&mips_arch_string, "4010");
11826 mips_set_option_string (&mips_tune_string, "4010");
11829 case OPTION_NO_M4010:
11833 mips_set_option_string (&mips_arch_string, "4100");
11834 mips_set_option_string (&mips_tune_string, "4100");
11837 case OPTION_NO_M4100:
11841 mips_set_option_string (&mips_arch_string, "3900");
11842 mips_set_option_string (&mips_tune_string, "3900");
11845 case OPTION_NO_M3900:
11849 mips_opts.ase_mdmx = 1;
11852 case OPTION_NO_MDMX:
11853 mips_opts.ase_mdmx = 0;
11857 mips_opts.ase_dsp = 1;
11858 mips_opts.ase_dspr2 = 0;
11861 case OPTION_NO_DSP:
11862 mips_opts.ase_dsp = 0;
11863 mips_opts.ase_dspr2 = 0;
11867 mips_opts.ase_dspr2 = 1;
11868 mips_opts.ase_dsp = 1;
11871 case OPTION_NO_DSPR2:
11872 mips_opts.ase_dspr2 = 0;
11873 mips_opts.ase_dsp = 0;
11877 mips_opts.ase_mt = 1;
11881 mips_opts.ase_mt = 0;
11884 case OPTION_MIPS16:
11885 mips_opts.mips16 = 1;
11886 mips_no_prev_insn ();
11889 case OPTION_NO_MIPS16:
11890 mips_opts.mips16 = 0;
11891 mips_no_prev_insn ();
11894 case OPTION_MIPS3D:
11895 mips_opts.ase_mips3d = 1;
11898 case OPTION_NO_MIPS3D:
11899 mips_opts.ase_mips3d = 0;
11902 case OPTION_SMARTMIPS:
11903 mips_opts.ase_smartmips = 1;
11906 case OPTION_NO_SMARTMIPS:
11907 mips_opts.ase_smartmips = 0;
11910 case OPTION_FIX_24K:
11914 case OPTION_NO_FIX_24K:
11918 case OPTION_FIX_LOONGSON2F_JUMP:
11919 mips_fix_loongson2f_jump = TRUE;
11922 case OPTION_NO_FIX_LOONGSON2F_JUMP:
11923 mips_fix_loongson2f_jump = FALSE;
11926 case OPTION_FIX_LOONGSON2F_NOP:
11927 mips_fix_loongson2f_nop = TRUE;
11930 case OPTION_NO_FIX_LOONGSON2F_NOP:
11931 mips_fix_loongson2f_nop = FALSE;
11934 case OPTION_FIX_VR4120:
11935 mips_fix_vr4120 = 1;
11938 case OPTION_NO_FIX_VR4120:
11939 mips_fix_vr4120 = 0;
11942 case OPTION_FIX_VR4130:
11943 mips_fix_vr4130 = 1;
11946 case OPTION_NO_FIX_VR4130:
11947 mips_fix_vr4130 = 0;
11950 case OPTION_FIX_CN63XXP1:
11951 mips_fix_cn63xxp1 = TRUE;
11954 case OPTION_NO_FIX_CN63XXP1:
11955 mips_fix_cn63xxp1 = FALSE;
11958 case OPTION_RELAX_BRANCH:
11959 mips_relax_branch = 1;
11962 case OPTION_NO_RELAX_BRANCH:
11963 mips_relax_branch = 0;
11966 case OPTION_MSHARED:
11967 mips_in_shared = TRUE;
11970 case OPTION_MNO_SHARED:
11971 mips_in_shared = FALSE;
11974 case OPTION_MSYM32:
11975 mips_opts.sym32 = TRUE;
11978 case OPTION_MNO_SYM32:
11979 mips_opts.sym32 = FALSE;
11983 /* When generating ELF code, we permit -KPIC and -call_shared to
11984 select SVR4_PIC, and -non_shared to select no PIC. This is
11985 intended to be compatible with Irix 5. */
11986 case OPTION_CALL_SHARED:
11989 as_bad (_("-call_shared is supported only for ELF format"));
11992 mips_pic = SVR4_PIC;
11993 mips_abicalls = TRUE;
11996 case OPTION_CALL_NONPIC:
11999 as_bad (_("-call_nonpic is supported only for ELF format"));
12003 mips_abicalls = TRUE;
12006 case OPTION_NON_SHARED:
12009 as_bad (_("-non_shared is supported only for ELF format"));
12013 mips_abicalls = FALSE;
12016 /* The -xgot option tells the assembler to use 32 bit offsets
12017 when accessing the got in SVR4_PIC mode. It is for Irix
12022 #endif /* OBJ_ELF */
12025 g_switch_value = atoi (arg);
12029 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
12033 mips_abi = O32_ABI;
12034 /* We silently ignore -32 for non-ELF targets. This greatly
12035 simplifies the construction of the MIPS GAS test cases. */
12042 as_bad (_("-n32 is supported for ELF format only"));
12045 mips_abi = N32_ABI;
12051 as_bad (_("-64 is supported for ELF format only"));
12054 mips_abi = N64_ABI;
12055 if (!support_64bit_objects())
12056 as_fatal (_("No compiled in support for 64 bit object file format"));
12058 #endif /* OBJ_ELF */
12061 file_mips_gp32 = 1;
12065 file_mips_gp32 = 0;
12069 file_mips_fp32 = 1;
12073 file_mips_fp32 = 0;
12076 case OPTION_SINGLE_FLOAT:
12077 file_mips_single_float = 1;
12080 case OPTION_DOUBLE_FLOAT:
12081 file_mips_single_float = 0;
12084 case OPTION_SOFT_FLOAT:
12085 file_mips_soft_float = 1;
12088 case OPTION_HARD_FLOAT:
12089 file_mips_soft_float = 0;
12096 as_bad (_("-mabi is supported for ELF format only"));
12099 if (strcmp (arg, "32") == 0)
12100 mips_abi = O32_ABI;
12101 else if (strcmp (arg, "o64") == 0)
12102 mips_abi = O64_ABI;
12103 else if (strcmp (arg, "n32") == 0)
12104 mips_abi = N32_ABI;
12105 else if (strcmp (arg, "64") == 0)
12107 mips_abi = N64_ABI;
12108 if (! support_64bit_objects())
12109 as_fatal (_("No compiled in support for 64 bit object file "
12112 else if (strcmp (arg, "eabi") == 0)
12113 mips_abi = EABI_ABI;
12116 as_fatal (_("invalid abi -mabi=%s"), arg);
12120 #endif /* OBJ_ELF */
12122 case OPTION_M7000_HILO_FIX:
12123 mips_7000_hilo_fix = TRUE;
12126 case OPTION_MNO_7000_HILO_FIX:
12127 mips_7000_hilo_fix = FALSE;
12131 case OPTION_MDEBUG:
12132 mips_flag_mdebug = TRUE;
12135 case OPTION_NO_MDEBUG:
12136 mips_flag_mdebug = FALSE;
12140 mips_flag_pdr = TRUE;
12143 case OPTION_NO_PDR:
12144 mips_flag_pdr = FALSE;
12147 case OPTION_MVXWORKS_PIC:
12148 mips_pic = VXWORKS_PIC;
12150 #endif /* OBJ_ELF */
12156 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
12161 /* Set up globals to generate code for the ISA or processor
12162 described by INFO. */
12165 mips_set_architecture (const struct mips_cpu_info *info)
12169 file_mips_arch = info->cpu;
12170 mips_opts.arch = info->cpu;
12171 mips_opts.isa = info->isa;
12176 /* Likewise for tuning. */
12179 mips_set_tune (const struct mips_cpu_info *info)
12182 mips_tune = info->cpu;
12187 mips_after_parse_args (void)
12189 const struct mips_cpu_info *arch_info = 0;
12190 const struct mips_cpu_info *tune_info = 0;
12192 /* GP relative stuff not working for PE */
12193 if (strncmp (TARGET_OS, "pe", 2) == 0)
12195 if (g_switch_seen && g_switch_value != 0)
12196 as_bad (_("-G not supported in this configuration."));
12197 g_switch_value = 0;
12200 if (mips_abi == NO_ABI)
12201 mips_abi = MIPS_DEFAULT_ABI;
12203 /* The following code determines the architecture and register size.
12204 Similar code was added to GCC 3.3 (see override_options() in
12205 config/mips/mips.c). The GAS and GCC code should be kept in sync
12206 as much as possible. */
12208 if (mips_arch_string != 0)
12209 arch_info = mips_parse_cpu ("-march", mips_arch_string);
12211 if (file_mips_isa != ISA_UNKNOWN)
12213 /* Handle -mipsN. At this point, file_mips_isa contains the
12214 ISA level specified by -mipsN, while arch_info->isa contains
12215 the -march selection (if any). */
12216 if (arch_info != 0)
12218 /* -march takes precedence over -mipsN, since it is more descriptive.
12219 There's no harm in specifying both as long as the ISA levels
12221 if (file_mips_isa != arch_info->isa)
12222 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
12223 mips_cpu_info_from_isa (file_mips_isa)->name,
12224 mips_cpu_info_from_isa (arch_info->isa)->name);
12227 arch_info = mips_cpu_info_from_isa (file_mips_isa);
12230 if (arch_info == 0)
12231 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
12233 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
12234 as_bad (_("-march=%s is not compatible with the selected ABI"),
12237 mips_set_architecture (arch_info);
12239 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
12240 if (mips_tune_string != 0)
12241 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
12243 if (tune_info == 0)
12244 mips_set_tune (arch_info);
12246 mips_set_tune (tune_info);
12248 if (file_mips_gp32 >= 0)
12250 /* The user specified the size of the integer registers. Make sure
12251 it agrees with the ABI and ISA. */
12252 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
12253 as_bad (_("-mgp64 used with a 32-bit processor"));
12254 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
12255 as_bad (_("-mgp32 used with a 64-bit ABI"));
12256 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
12257 as_bad (_("-mgp64 used with a 32-bit ABI"));
12261 /* Infer the integer register size from the ABI and processor.
12262 Restrict ourselves to 32-bit registers if that's all the
12263 processor has, or if the ABI cannot handle 64-bit registers. */
12264 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
12265 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
12268 switch (file_mips_fp32)
12272 /* No user specified float register size.
12273 ??? GAS treats single-float processors as though they had 64-bit
12274 float registers (although it complains when double-precision
12275 instructions are used). As things stand, saying they have 32-bit
12276 registers would lead to spurious "register must be even" messages.
12277 So here we assume float registers are never smaller than the
12279 if (file_mips_gp32 == 0)
12280 /* 64-bit integer registers implies 64-bit float registers. */
12281 file_mips_fp32 = 0;
12282 else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
12283 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
12284 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
12285 file_mips_fp32 = 0;
12287 /* 32-bit float registers. */
12288 file_mips_fp32 = 1;
12291 /* The user specified the size of the float registers. Check if it
12292 agrees with the ABI and ISA. */
12294 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
12295 as_bad (_("-mfp64 used with a 32-bit fpu"));
12296 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
12297 && !ISA_HAS_MXHC1 (mips_opts.isa))
12298 as_warn (_("-mfp64 used with a 32-bit ABI"));
12301 if (ABI_NEEDS_64BIT_REGS (mips_abi))
12302 as_warn (_("-mfp32 used with a 64-bit ABI"));
12306 /* End of GCC-shared inference code. */
12308 /* This flag is set when we have a 64-bit capable CPU but use only
12309 32-bit wide registers. Note that EABI does not use it. */
12310 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
12311 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
12312 || mips_abi == O32_ABI))
12313 mips_32bitmode = 1;
12315 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
12316 as_bad (_("trap exception not supported at ISA 1"));
12318 /* If the selected architecture includes support for ASEs, enable
12319 generation of code for them. */
12320 if (mips_opts.mips16 == -1)
12321 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
12322 if (mips_opts.ase_mips3d == -1)
12323 mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
12324 && file_mips_fp32 == 0) ? 1 : 0;
12325 if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
12326 as_bad (_("-mfp32 used with -mips3d"));
12328 if (mips_opts.ase_mdmx == -1)
12329 mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
12330 && file_mips_fp32 == 0) ? 1 : 0;
12331 if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
12332 as_bad (_("-mfp32 used with -mdmx"));
12334 if (mips_opts.ase_smartmips == -1)
12335 mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
12336 if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
12337 as_warn (_("%s ISA does not support SmartMIPS"),
12338 mips_cpu_info_from_isa (mips_opts.isa)->name);
12340 if (mips_opts.ase_dsp == -1)
12341 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
12342 if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
12343 as_warn (_("%s ISA does not support DSP ASE"),
12344 mips_cpu_info_from_isa (mips_opts.isa)->name);
12346 if (mips_opts.ase_dspr2 == -1)
12348 mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
12349 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
12351 if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
12352 as_warn (_("%s ISA does not support DSP R2 ASE"),
12353 mips_cpu_info_from_isa (mips_opts.isa)->name);
12355 if (mips_opts.ase_mt == -1)
12356 mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
12357 if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
12358 as_warn (_("%s ISA does not support MT ASE"),
12359 mips_cpu_info_from_isa (mips_opts.isa)->name);
12361 file_mips_isa = mips_opts.isa;
12362 file_ase_mips3d = mips_opts.ase_mips3d;
12363 file_ase_mdmx = mips_opts.ase_mdmx;
12364 file_ase_smartmips = mips_opts.ase_smartmips;
12365 file_ase_dsp = mips_opts.ase_dsp;
12366 file_ase_dspr2 = mips_opts.ase_dspr2;
12367 file_ase_mt = mips_opts.ase_mt;
12368 mips_opts.gp32 = file_mips_gp32;
12369 mips_opts.fp32 = file_mips_fp32;
12370 mips_opts.soft_float = file_mips_soft_float;
12371 mips_opts.single_float = file_mips_single_float;
12373 if (mips_flag_mdebug < 0)
12375 #ifdef OBJ_MAYBE_ECOFF
12376 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
12377 mips_flag_mdebug = 1;
12379 #endif /* OBJ_MAYBE_ECOFF */
12380 mips_flag_mdebug = 0;
12385 mips_init_after_args (void)
12387 /* initialize opcodes */
12388 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
12389 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
12393 md_pcrel_from (fixS *fixP)
12395 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
12396 switch (fixP->fx_r_type)
12398 case BFD_RELOC_16_PCREL_S2:
12399 case BFD_RELOC_MIPS_JMP:
12400 /* Return the address of the delay slot. */
12403 /* We have no relocation type for PC relative MIPS16 instructions. */
12404 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
12405 as_bad_where (fixP->fx_file, fixP->fx_line,
12406 _("PC relative MIPS16 instruction references a different section"));
12411 /* This is called before the symbol table is processed. In order to
12412 work with gcc when using mips-tfile, we must keep all local labels.
12413 However, in other cases, we want to discard them. If we were
12414 called with -g, but we didn't see any debugging information, it may
12415 mean that gcc is smuggling debugging information through to
12416 mips-tfile, in which case we must generate all local labels. */
12419 mips_frob_file_before_adjust (void)
12421 #ifndef NO_ECOFF_DEBUGGING
12422 if (ECOFF_DEBUGGING
12424 && ! ecoff_debugging_seen)
12425 flag_keep_locals = 1;
12429 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
12430 the corresponding LO16 reloc. This is called before md_apply_fix and
12431 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
12432 relocation operators.
12434 For our purposes, a %lo() expression matches a %got() or %hi()
12437 (a) it refers to the same symbol; and
12438 (b) the offset applied in the %lo() expression is no lower than
12439 the offset applied in the %got() or %hi().
12441 (b) allows us to cope with code like:
12444 lh $4,%lo(foo+2)($4)
12446 ...which is legal on RELA targets, and has a well-defined behaviour
12447 if the user knows that adding 2 to "foo" will not induce a carry to
12450 When several %lo()s match a particular %got() or %hi(), we use the
12451 following rules to distinguish them:
12453 (1) %lo()s with smaller offsets are a better match than %lo()s with
12456 (2) %lo()s with no matching %got() or %hi() are better than those
12457 that already have a matching %got() or %hi().
12459 (3) later %lo()s are better than earlier %lo()s.
12461 These rules are applied in order.
12463 (1) means, among other things, that %lo()s with identical offsets are
12464 chosen if they exist.
12466 (2) means that we won't associate several high-part relocations with
12467 the same low-part relocation unless there's no alternative. Having
12468 several high parts for the same low part is a GNU extension; this rule
12469 allows careful users to avoid it.
12471 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
12472 with the last high-part relocation being at the front of the list.
12473 It therefore makes sense to choose the last matching low-part
12474 relocation, all other things being equal. It's also easier
12475 to code that way. */
12478 mips_frob_file (void)
12480 struct mips_hi_fixup *l;
12481 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
12483 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
12485 segment_info_type *seginfo;
12486 bfd_boolean matched_lo_p;
12487 fixS **hi_pos, **lo_pos, **pos;
12489 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
12491 /* If a GOT16 relocation turns out to be against a global symbol,
12492 there isn't supposed to be a matching LO. */
12493 if (got16_reloc_p (l->fixp->fx_r_type)
12494 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
12497 /* Check quickly whether the next fixup happens to be a matching %lo. */
12498 if (fixup_has_matching_lo_p (l->fixp))
12501 seginfo = seg_info (l->seg);
12503 /* Set HI_POS to the position of this relocation in the chain.
12504 Set LO_POS to the position of the chosen low-part relocation.
12505 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
12506 relocation that matches an immediately-preceding high-part
12510 matched_lo_p = FALSE;
12511 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
12513 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
12515 if (*pos == l->fixp)
12518 if ((*pos)->fx_r_type == looking_for_rtype
12519 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
12520 && (*pos)->fx_offset >= l->fixp->fx_offset
12522 || (*pos)->fx_offset < (*lo_pos)->fx_offset
12524 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
12527 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
12528 && fixup_has_matching_lo_p (*pos));
12531 /* If we found a match, remove the high-part relocation from its
12532 current position and insert it before the low-part relocation.
12533 Make the offsets match so that fixup_has_matching_lo_p()
12536 We don't warn about unmatched high-part relocations since some
12537 versions of gcc have been known to emit dead "lui ...%hi(...)"
12539 if (lo_pos != NULL)
12541 l->fixp->fx_offset = (*lo_pos)->fx_offset;
12542 if (l->fixp->fx_next != *lo_pos)
12544 *hi_pos = l->fixp->fx_next;
12545 l->fixp->fx_next = *lo_pos;
12552 /* We may have combined relocations without symbols in the N32/N64 ABI.
12553 We have to prevent gas from dropping them. */
12556 mips_force_relocation (fixS *fixp)
12558 if (generic_force_reloc (fixp))
12562 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
12563 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
12564 || hi16_reloc_p (fixp->fx_r_type)
12565 || lo16_reloc_p (fixp->fx_r_type)))
12571 /* Apply a fixup to the object file. */
12574 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
12578 reloc_howto_type *howto;
12580 /* We ignore generic BFD relocations we don't know about. */
12581 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
12585 gas_assert (fixP->fx_size == 4
12586 || fixP->fx_r_type == BFD_RELOC_16
12587 || fixP->fx_r_type == BFD_RELOC_64
12588 || fixP->fx_r_type == BFD_RELOC_CTOR
12589 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
12590 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12591 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
12592 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
12594 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
12596 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2);
12598 /* Don't treat parts of a composite relocation as done. There are two
12601 (1) The second and third parts will be against 0 (RSS_UNDEF) but
12602 should nevertheless be emitted if the first part is.
12604 (2) In normal usage, composite relocations are never assembly-time
12605 constants. The easiest way of dealing with the pathological
12606 exceptions is to generate a relocation against STN_UNDEF and
12607 leave everything up to the linker. */
12608 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
12611 switch (fixP->fx_r_type)
12613 case BFD_RELOC_MIPS_TLS_GD:
12614 case BFD_RELOC_MIPS_TLS_LDM:
12615 case BFD_RELOC_MIPS_TLS_DTPREL32:
12616 case BFD_RELOC_MIPS_TLS_DTPREL64:
12617 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
12618 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
12619 case BFD_RELOC_MIPS_TLS_GOTTPREL:
12620 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
12621 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
12622 S_SET_THREAD_LOCAL (fixP->fx_addsy);
12625 case BFD_RELOC_MIPS_JMP:
12626 case BFD_RELOC_MIPS_SHIFT5:
12627 case BFD_RELOC_MIPS_SHIFT6:
12628 case BFD_RELOC_MIPS_GOT_DISP:
12629 case BFD_RELOC_MIPS_GOT_PAGE:
12630 case BFD_RELOC_MIPS_GOT_OFST:
12631 case BFD_RELOC_MIPS_SUB:
12632 case BFD_RELOC_MIPS_INSERT_A:
12633 case BFD_RELOC_MIPS_INSERT_B:
12634 case BFD_RELOC_MIPS_DELETE:
12635 case BFD_RELOC_MIPS_HIGHEST:
12636 case BFD_RELOC_MIPS_HIGHER:
12637 case BFD_RELOC_MIPS_SCN_DISP:
12638 case BFD_RELOC_MIPS_REL16:
12639 case BFD_RELOC_MIPS_RELGOT:
12640 case BFD_RELOC_MIPS_JALR:
12641 case BFD_RELOC_HI16:
12642 case BFD_RELOC_HI16_S:
12643 case BFD_RELOC_GPREL16:
12644 case BFD_RELOC_MIPS_LITERAL:
12645 case BFD_RELOC_MIPS_CALL16:
12646 case BFD_RELOC_MIPS_GOT16:
12647 case BFD_RELOC_GPREL32:
12648 case BFD_RELOC_MIPS_GOT_HI16:
12649 case BFD_RELOC_MIPS_GOT_LO16:
12650 case BFD_RELOC_MIPS_CALL_HI16:
12651 case BFD_RELOC_MIPS_CALL_LO16:
12652 case BFD_RELOC_MIPS16_GPREL:
12653 case BFD_RELOC_MIPS16_GOT16:
12654 case BFD_RELOC_MIPS16_CALL16:
12655 case BFD_RELOC_MIPS16_HI16:
12656 case BFD_RELOC_MIPS16_HI16_S:
12657 case BFD_RELOC_MIPS16_JMP:
12658 /* Nothing needed to do. The value comes from the reloc entry. */
12662 /* This is handled like BFD_RELOC_32, but we output a sign
12663 extended value if we are only 32 bits. */
12666 if (8 <= sizeof (valueT))
12667 md_number_to_chars ((char *) buf, *valP, 8);
12672 if ((*valP & 0x80000000) != 0)
12676 md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)),
12678 md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)),
12684 case BFD_RELOC_RVA:
12687 /* If we are deleting this reloc entry, we must fill in the
12688 value now. This can happen if we have a .word which is not
12689 resolved when it appears but is later defined. */
12691 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
12694 case BFD_RELOC_LO16:
12695 case BFD_RELOC_MIPS16_LO16:
12696 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
12697 may be safe to remove, but if so it's not obvious. */
12698 /* When handling an embedded PIC switch statement, we can wind
12699 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
12702 if (*valP + 0x8000 > 0xffff)
12703 as_bad_where (fixP->fx_file, fixP->fx_line,
12704 _("relocation overflow"));
12705 if (target_big_endian)
12707 md_number_to_chars ((char *) buf, *valP, 2);
12711 case BFD_RELOC_16_PCREL_S2:
12712 if ((*valP & 0x3) != 0)
12713 as_bad_where (fixP->fx_file, fixP->fx_line,
12714 _("Branch to misaligned address (%lx)"), (long) *valP);
12716 /* We need to save the bits in the instruction since fixup_segment()
12717 might be deleting the relocation entry (i.e., a branch within
12718 the current segment). */
12719 if (! fixP->fx_done)
12722 /* Update old instruction data. */
12723 if (target_big_endian)
12724 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
12726 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
12728 if (*valP + 0x20000 <= 0x3ffff)
12730 insn |= (*valP >> 2) & 0xffff;
12731 md_number_to_chars ((char *) buf, insn, 4);
12733 else if (mips_pic == NO_PIC
12735 && fixP->fx_frag->fr_address >= text_section->vma
12736 && (fixP->fx_frag->fr_address
12737 < text_section->vma + bfd_get_section_size (text_section))
12738 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
12739 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
12740 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
12742 /* The branch offset is too large. If this is an
12743 unconditional branch, and we are not generating PIC code,
12744 we can convert it to an absolute jump instruction. */
12745 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
12746 insn = 0x0c000000; /* jal */
12748 insn = 0x08000000; /* j */
12749 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
12751 fixP->fx_addsy = section_symbol (text_section);
12752 *valP += md_pcrel_from (fixP);
12753 md_number_to_chars ((char *) buf, insn, 4);
12757 /* If we got here, we have branch-relaxation disabled,
12758 and there's nothing we can do to fix this instruction
12759 without turning it into a longer sequence. */
12760 as_bad_where (fixP->fx_file, fixP->fx_line,
12761 _("Branch out of range"));
12765 case BFD_RELOC_VTABLE_INHERIT:
12768 && !S_IS_DEFINED (fixP->fx_addsy)
12769 && !S_IS_WEAK (fixP->fx_addsy))
12770 S_SET_WEAK (fixP->fx_addsy);
12773 case BFD_RELOC_VTABLE_ENTRY:
12781 /* Remember value for tc_gen_reloc. */
12782 fixP->fx_addnumber = *valP;
12792 name = input_line_pointer;
12793 c = get_symbol_end ();
12794 p = (symbolS *) symbol_find_or_make (name);
12795 *input_line_pointer = c;
12799 /* Align the current frag to a given power of two. If a particular
12800 fill byte should be used, FILL points to an integer that contains
12801 that byte, otherwise FILL is null.
12803 The MIPS assembler also automatically adjusts any preceding
12807 mips_align (int to, int *fill, symbolS *label)
12809 mips_emit_delays ();
12810 mips_record_mips16_mode ();
12811 if (fill == NULL && subseg_text_p (now_seg))
12812 frag_align_code (to, 0);
12814 frag_align (to, fill ? *fill : 0, 0);
12815 record_alignment (now_seg, to);
12818 gas_assert (S_GET_SEGMENT (label) == now_seg);
12819 symbol_set_frag (label, frag_now);
12820 S_SET_VALUE (label, (valueT) frag_now_fix ());
12824 /* Align to a given power of two. .align 0 turns off the automatic
12825 alignment used by the data creating pseudo-ops. */
12828 s_align (int x ATTRIBUTE_UNUSED)
12830 int temp, fill_value, *fill_ptr;
12831 long max_alignment = 28;
12833 /* o Note that the assembler pulls down any immediately preceding label
12834 to the aligned address.
12835 o It's not documented but auto alignment is reinstated by
12836 a .align pseudo instruction.
12837 o Note also that after auto alignment is turned off the mips assembler
12838 issues an error on attempt to assemble an improperly aligned data item.
12841 temp = get_absolute_expression ();
12842 if (temp > max_alignment)
12843 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
12846 as_warn (_("Alignment negative: 0 assumed."));
12849 if (*input_line_pointer == ',')
12851 ++input_line_pointer;
12852 fill_value = get_absolute_expression ();
12853 fill_ptr = &fill_value;
12859 segment_info_type *si = seg_info (now_seg);
12860 struct insn_label_list *l = si->label_list;
12861 /* Auto alignment should be switched on by next section change. */
12863 mips_align (temp, fill_ptr, l != NULL ? l->label : NULL);
12870 demand_empty_rest_of_line ();
12874 s_change_sec (int sec)
12879 /* The ELF backend needs to know that we are changing sections, so
12880 that .previous works correctly. We could do something like check
12881 for an obj_section_change_hook macro, but that might be confusing
12882 as it would not be appropriate to use it in the section changing
12883 functions in read.c, since obj-elf.c intercepts those. FIXME:
12884 This should be cleaner, somehow. */
12886 obj_elf_section_change_hook ();
12889 mips_emit_delays ();
12900 subseg_set (bss_section, (subsegT) get_absolute_expression ());
12901 demand_empty_rest_of_line ();
12905 seg = subseg_new (RDATA_SECTION_NAME,
12906 (subsegT) get_absolute_expression ());
12909 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
12910 | SEC_READONLY | SEC_RELOC
12912 if (strncmp (TARGET_OS, "elf", 3) != 0)
12913 record_alignment (seg, 4);
12915 demand_empty_rest_of_line ();
12919 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
12922 bfd_set_section_flags (stdoutput, seg,
12923 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
12924 if (strncmp (TARGET_OS, "elf", 3) != 0)
12925 record_alignment (seg, 4);
12927 demand_empty_rest_of_line ();
12931 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
12934 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
12935 if (strncmp (TARGET_OS, "elf", 3) != 0)
12936 record_alignment (seg, 4);
12938 demand_empty_rest_of_line ();
12946 s_change_section (int ignore ATTRIBUTE_UNUSED)
12949 char *section_name;
12954 int section_entry_size;
12955 int section_alignment;
12960 section_name = input_line_pointer;
12961 c = get_symbol_end ();
12963 next_c = *(input_line_pointer + 1);
12965 /* Do we have .section Name<,"flags">? */
12966 if (c != ',' || (c == ',' && next_c == '"'))
12968 /* just after name is now '\0'. */
12969 *input_line_pointer = c;
12970 input_line_pointer = section_name;
12971 obj_elf_section (ignore);
12974 input_line_pointer++;
12976 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
12978 section_type = get_absolute_expression ();
12981 if (*input_line_pointer++ == ',')
12982 section_flag = get_absolute_expression ();
12985 if (*input_line_pointer++ == ',')
12986 section_entry_size = get_absolute_expression ();
12988 section_entry_size = 0;
12989 if (*input_line_pointer++ == ',')
12990 section_alignment = get_absolute_expression ();
12992 section_alignment = 0;
12993 /* FIXME: really ignore? */
12994 (void) section_alignment;
12996 section_name = xstrdup (section_name);
12998 /* When using the generic form of .section (as implemented by obj-elf.c),
12999 there's no way to set the section type to SHT_MIPS_DWARF. Users have
13000 traditionally had to fall back on the more common @progbits instead.
13002 There's nothing really harmful in this, since bfd will correct
13003 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
13004 means that, for backwards compatibility, the special_section entries
13005 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
13007 Even so, we shouldn't force users of the MIPS .section syntax to
13008 incorrectly label the sections as SHT_PROGBITS. The best compromise
13009 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
13010 generic type-checking code. */
13011 if (section_type == SHT_MIPS_DWARF)
13012 section_type = SHT_PROGBITS;
13014 obj_elf_change_section (section_name, section_type, section_flag,
13015 section_entry_size, 0, 0, 0);
13017 if (now_seg->name != section_name)
13018 free (section_name);
13019 #endif /* OBJ_ELF */
13023 mips_enable_auto_align (void)
13029 s_cons (int log_size)
13031 segment_info_type *si = seg_info (now_seg);
13032 struct insn_label_list *l = si->label_list;
13035 label = l != NULL ? l->label : NULL;
13036 mips_emit_delays ();
13037 if (log_size > 0 && auto_align)
13038 mips_align (log_size, 0, label);
13039 cons (1 << log_size);
13040 mips_clear_insn_labels ();
13044 s_float_cons (int type)
13046 segment_info_type *si = seg_info (now_seg);
13047 struct insn_label_list *l = si->label_list;
13050 label = l != NULL ? l->label : NULL;
13052 mips_emit_delays ();
13057 mips_align (3, 0, label);
13059 mips_align (2, 0, label);
13063 mips_clear_insn_labels ();
13066 /* Handle .globl. We need to override it because on Irix 5 you are
13069 where foo is an undefined symbol, to mean that foo should be
13070 considered to be the address of a function. */
13073 s_mips_globl (int x ATTRIBUTE_UNUSED)
13082 name = input_line_pointer;
13083 c = get_symbol_end ();
13084 symbolP = symbol_find_or_make (name);
13085 S_SET_EXTERNAL (symbolP);
13087 *input_line_pointer = c;
13088 SKIP_WHITESPACE ();
13090 /* On Irix 5, every global symbol that is not explicitly labelled as
13091 being a function is apparently labelled as being an object. */
13094 if (!is_end_of_line[(unsigned char) *input_line_pointer]
13095 && (*input_line_pointer != ','))
13100 secname = input_line_pointer;
13101 c = get_symbol_end ();
13102 sec = bfd_get_section_by_name (stdoutput, secname);
13104 as_bad (_("%s: no such section"), secname);
13105 *input_line_pointer = c;
13107 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
13108 flag = BSF_FUNCTION;
13111 symbol_get_bfdsym (symbolP)->flags |= flag;
13113 c = *input_line_pointer;
13116 input_line_pointer++;
13117 SKIP_WHITESPACE ();
13118 if (is_end_of_line[(unsigned char) *input_line_pointer])
13124 demand_empty_rest_of_line ();
13128 s_option (int x ATTRIBUTE_UNUSED)
13133 opt = input_line_pointer;
13134 c = get_symbol_end ();
13138 /* FIXME: What does this mean? */
13140 else if (strncmp (opt, "pic", 3) == 0)
13144 i = atoi (opt + 3);
13149 mips_pic = SVR4_PIC;
13150 mips_abicalls = TRUE;
13153 as_bad (_(".option pic%d not supported"), i);
13155 if (mips_pic == SVR4_PIC)
13157 if (g_switch_seen && g_switch_value != 0)
13158 as_warn (_("-G may not be used with SVR4 PIC code"));
13159 g_switch_value = 0;
13160 bfd_set_gp_size (stdoutput, 0);
13164 as_warn (_("Unrecognized option \"%s\""), opt);
13166 *input_line_pointer = c;
13167 demand_empty_rest_of_line ();
13170 /* This structure is used to hold a stack of .set values. */
13172 struct mips_option_stack
13174 struct mips_option_stack *next;
13175 struct mips_set_options options;
13178 static struct mips_option_stack *mips_opts_stack;
13180 /* Handle the .set pseudo-op. */
13183 s_mipsset (int x ATTRIBUTE_UNUSED)
13185 char *name = input_line_pointer, ch;
13187 while (!is_end_of_line[(unsigned char) *input_line_pointer])
13188 ++input_line_pointer;
13189 ch = *input_line_pointer;
13190 *input_line_pointer = '\0';
13192 if (strcmp (name, "reorder") == 0)
13194 if (mips_opts.noreorder)
13197 else if (strcmp (name, "noreorder") == 0)
13199 if (!mips_opts.noreorder)
13200 start_noreorder ();
13202 else if (strncmp (name, "at=", 3) == 0)
13204 char *s = name + 3;
13206 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
13207 as_bad (_("Unrecognized register name `%s'"), s);
13209 else if (strcmp (name, "at") == 0)
13211 mips_opts.at = ATREG;
13213 else if (strcmp (name, "noat") == 0)
13215 mips_opts.at = ZERO;
13217 else if (strcmp (name, "macro") == 0)
13219 mips_opts.warn_about_macros = 0;
13221 else if (strcmp (name, "nomacro") == 0)
13223 if (mips_opts.noreorder == 0)
13224 as_bad (_("`noreorder' must be set before `nomacro'"));
13225 mips_opts.warn_about_macros = 1;
13227 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
13229 mips_opts.nomove = 0;
13231 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
13233 mips_opts.nomove = 1;
13235 else if (strcmp (name, "bopt") == 0)
13237 mips_opts.nobopt = 0;
13239 else if (strcmp (name, "nobopt") == 0)
13241 mips_opts.nobopt = 1;
13243 else if (strcmp (name, "gp=default") == 0)
13244 mips_opts.gp32 = file_mips_gp32;
13245 else if (strcmp (name, "gp=32") == 0)
13246 mips_opts.gp32 = 1;
13247 else if (strcmp (name, "gp=64") == 0)
13249 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
13250 as_warn (_("%s isa does not support 64-bit registers"),
13251 mips_cpu_info_from_isa (mips_opts.isa)->name);
13252 mips_opts.gp32 = 0;
13254 else if (strcmp (name, "fp=default") == 0)
13255 mips_opts.fp32 = file_mips_fp32;
13256 else if (strcmp (name, "fp=32") == 0)
13257 mips_opts.fp32 = 1;
13258 else if (strcmp (name, "fp=64") == 0)
13260 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
13261 as_warn (_("%s isa does not support 64-bit floating point registers"),
13262 mips_cpu_info_from_isa (mips_opts.isa)->name);
13263 mips_opts.fp32 = 0;
13265 else if (strcmp (name, "softfloat") == 0)
13266 mips_opts.soft_float = 1;
13267 else if (strcmp (name, "hardfloat") == 0)
13268 mips_opts.soft_float = 0;
13269 else if (strcmp (name, "singlefloat") == 0)
13270 mips_opts.single_float = 1;
13271 else if (strcmp (name, "doublefloat") == 0)
13272 mips_opts.single_float = 0;
13273 else if (strcmp (name, "mips16") == 0
13274 || strcmp (name, "MIPS-16") == 0)
13275 mips_opts.mips16 = 1;
13276 else if (strcmp (name, "nomips16") == 0
13277 || strcmp (name, "noMIPS-16") == 0)
13278 mips_opts.mips16 = 0;
13279 else if (strcmp (name, "smartmips") == 0)
13281 if (!ISA_SUPPORTS_SMARTMIPS)
13282 as_warn (_("%s ISA does not support SmartMIPS ASE"),
13283 mips_cpu_info_from_isa (mips_opts.isa)->name);
13284 mips_opts.ase_smartmips = 1;
13286 else if (strcmp (name, "nosmartmips") == 0)
13287 mips_opts.ase_smartmips = 0;
13288 else if (strcmp (name, "mips3d") == 0)
13289 mips_opts.ase_mips3d = 1;
13290 else if (strcmp (name, "nomips3d") == 0)
13291 mips_opts.ase_mips3d = 0;
13292 else if (strcmp (name, "mdmx") == 0)
13293 mips_opts.ase_mdmx = 1;
13294 else if (strcmp (name, "nomdmx") == 0)
13295 mips_opts.ase_mdmx = 0;
13296 else if (strcmp (name, "dsp") == 0)
13298 if (!ISA_SUPPORTS_DSP_ASE)
13299 as_warn (_("%s ISA does not support DSP ASE"),
13300 mips_cpu_info_from_isa (mips_opts.isa)->name);
13301 mips_opts.ase_dsp = 1;
13302 mips_opts.ase_dspr2 = 0;
13304 else if (strcmp (name, "nodsp") == 0)
13306 mips_opts.ase_dsp = 0;
13307 mips_opts.ase_dspr2 = 0;
13309 else if (strcmp (name, "dspr2") == 0)
13311 if (!ISA_SUPPORTS_DSPR2_ASE)
13312 as_warn (_("%s ISA does not support DSP R2 ASE"),
13313 mips_cpu_info_from_isa (mips_opts.isa)->name);
13314 mips_opts.ase_dspr2 = 1;
13315 mips_opts.ase_dsp = 1;
13317 else if (strcmp (name, "nodspr2") == 0)
13319 mips_opts.ase_dspr2 = 0;
13320 mips_opts.ase_dsp = 0;
13322 else if (strcmp (name, "mt") == 0)
13324 if (!ISA_SUPPORTS_MT_ASE)
13325 as_warn (_("%s ISA does not support MT ASE"),
13326 mips_cpu_info_from_isa (mips_opts.isa)->name);
13327 mips_opts.ase_mt = 1;
13329 else if (strcmp (name, "nomt") == 0)
13330 mips_opts.ase_mt = 0;
13331 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
13335 /* Permit the user to change the ISA and architecture on the fly.
13336 Needless to say, misuse can cause serious problems. */
13337 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
13340 mips_opts.isa = file_mips_isa;
13341 mips_opts.arch = file_mips_arch;
13343 else if (strncmp (name, "arch=", 5) == 0)
13345 const struct mips_cpu_info *p;
13347 p = mips_parse_cpu("internal use", name + 5);
13349 as_bad (_("unknown architecture %s"), name + 5);
13352 mips_opts.arch = p->cpu;
13353 mips_opts.isa = p->isa;
13356 else if (strncmp (name, "mips", 4) == 0)
13358 const struct mips_cpu_info *p;
13360 p = mips_parse_cpu("internal use", name);
13362 as_bad (_("unknown ISA level %s"), name + 4);
13365 mips_opts.arch = p->cpu;
13366 mips_opts.isa = p->isa;
13370 as_bad (_("unknown ISA or architecture %s"), name);
13372 switch (mips_opts.isa)
13380 mips_opts.gp32 = 1;
13381 mips_opts.fp32 = 1;
13388 mips_opts.gp32 = 0;
13389 mips_opts.fp32 = 0;
13392 as_bad (_("unknown ISA level %s"), name + 4);
13397 mips_opts.gp32 = file_mips_gp32;
13398 mips_opts.fp32 = file_mips_fp32;
13401 else if (strcmp (name, "autoextend") == 0)
13402 mips_opts.noautoextend = 0;
13403 else if (strcmp (name, "noautoextend") == 0)
13404 mips_opts.noautoextend = 1;
13405 else if (strcmp (name, "push") == 0)
13407 struct mips_option_stack *s;
13409 s = (struct mips_option_stack *) xmalloc (sizeof *s);
13410 s->next = mips_opts_stack;
13411 s->options = mips_opts;
13412 mips_opts_stack = s;
13414 else if (strcmp (name, "pop") == 0)
13416 struct mips_option_stack *s;
13418 s = mips_opts_stack;
13420 as_bad (_(".set pop with no .set push"));
13423 /* If we're changing the reorder mode we need to handle
13424 delay slots correctly. */
13425 if (s->options.noreorder && ! mips_opts.noreorder)
13426 start_noreorder ();
13427 else if (! s->options.noreorder && mips_opts.noreorder)
13430 mips_opts = s->options;
13431 mips_opts_stack = s->next;
13435 else if (strcmp (name, "sym32") == 0)
13436 mips_opts.sym32 = TRUE;
13437 else if (strcmp (name, "nosym32") == 0)
13438 mips_opts.sym32 = FALSE;
13439 else if (strchr (name, ','))
13441 /* Generic ".set" directive; use the generic handler. */
13442 *input_line_pointer = ch;
13443 input_line_pointer = name;
13449 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
13451 *input_line_pointer = ch;
13452 demand_empty_rest_of_line ();
13455 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
13456 .option pic2. It means to generate SVR4 PIC calls. */
13459 s_abicalls (int ignore ATTRIBUTE_UNUSED)
13461 mips_pic = SVR4_PIC;
13462 mips_abicalls = TRUE;
13464 if (g_switch_seen && g_switch_value != 0)
13465 as_warn (_("-G may not be used with SVR4 PIC code"));
13466 g_switch_value = 0;
13468 bfd_set_gp_size (stdoutput, 0);
13469 demand_empty_rest_of_line ();
13472 /* Handle the .cpload pseudo-op. This is used when generating SVR4
13473 PIC code. It sets the $gp register for the function based on the
13474 function address, which is in the register named in the argument.
13475 This uses a relocation against _gp_disp, which is handled specially
13476 by the linker. The result is:
13477 lui $gp,%hi(_gp_disp)
13478 addiu $gp,$gp,%lo(_gp_disp)
13479 addu $gp,$gp,.cpload argument
13480 The .cpload argument is normally $25 == $t9.
13482 The -mno-shared option changes this to:
13483 lui $gp,%hi(__gnu_local_gp)
13484 addiu $gp,$gp,%lo(__gnu_local_gp)
13485 and the argument is ignored. This saves an instruction, but the
13486 resulting code is not position independent; it uses an absolute
13487 address for __gnu_local_gp. Thus code assembled with -mno-shared
13488 can go into an ordinary executable, but not into a shared library. */
13491 s_cpload (int ignore ATTRIBUTE_UNUSED)
13497 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13498 .cpload is ignored. */
13499 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
13505 /* .cpload should be in a .set noreorder section. */
13506 if (mips_opts.noreorder == 0)
13507 as_warn (_(".cpload not in noreorder section"));
13509 reg = tc_get_register (0);
13511 /* If we need to produce a 64-bit address, we are better off using
13512 the default instruction sequence. */
13513 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
13515 ex.X_op = O_symbol;
13516 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
13518 ex.X_op_symbol = NULL;
13519 ex.X_add_number = 0;
13521 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13522 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
13525 macro_build_lui (&ex, mips_gp_register);
13526 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
13527 mips_gp_register, BFD_RELOC_LO16);
13529 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
13530 mips_gp_register, reg);
13533 demand_empty_rest_of_line ();
13536 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
13537 .cpsetup $reg1, offset|$reg2, label
13539 If offset is given, this results in:
13540 sd $gp, offset($sp)
13541 lui $gp, %hi(%neg(%gp_rel(label)))
13542 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13543 daddu $gp, $gp, $reg1
13545 If $reg2 is given, this results in:
13546 daddu $reg2, $gp, $0
13547 lui $gp, %hi(%neg(%gp_rel(label)))
13548 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13549 daddu $gp, $gp, $reg1
13550 $reg1 is normally $25 == $t9.
13552 The -mno-shared option replaces the last three instructions with
13554 addiu $gp,$gp,%lo(_gp) */
13557 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
13559 expressionS ex_off;
13560 expressionS ex_sym;
13563 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
13564 We also need NewABI support. */
13565 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13571 reg1 = tc_get_register (0);
13572 SKIP_WHITESPACE ();
13573 if (*input_line_pointer != ',')
13575 as_bad (_("missing argument separator ',' for .cpsetup"));
13579 ++input_line_pointer;
13580 SKIP_WHITESPACE ();
13581 if (*input_line_pointer == '$')
13583 mips_cpreturn_register = tc_get_register (0);
13584 mips_cpreturn_offset = -1;
13588 mips_cpreturn_offset = get_absolute_expression ();
13589 mips_cpreturn_register = -1;
13591 SKIP_WHITESPACE ();
13592 if (*input_line_pointer != ',')
13594 as_bad (_("missing argument separator ',' for .cpsetup"));
13598 ++input_line_pointer;
13599 SKIP_WHITESPACE ();
13600 expression (&ex_sym);
13603 if (mips_cpreturn_register == -1)
13605 ex_off.X_op = O_constant;
13606 ex_off.X_add_symbol = NULL;
13607 ex_off.X_op_symbol = NULL;
13608 ex_off.X_add_number = mips_cpreturn_offset;
13610 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
13611 BFD_RELOC_LO16, SP);
13614 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
13615 mips_gp_register, 0);
13617 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
13619 macro_build (&ex_sym, "lui", "t,u", mips_gp_register,
13620 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
13623 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
13624 mips_gp_register, -1, BFD_RELOC_GPREL16,
13625 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
13627 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
13628 mips_gp_register, reg1);
13634 ex.X_op = O_symbol;
13635 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
13636 ex.X_op_symbol = NULL;
13637 ex.X_add_number = 0;
13639 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13640 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
13642 macro_build_lui (&ex, mips_gp_register);
13643 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
13644 mips_gp_register, BFD_RELOC_LO16);
13649 demand_empty_rest_of_line ();
13653 s_cplocal (int ignore ATTRIBUTE_UNUSED)
13655 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
13656 .cplocal is ignored. */
13657 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13663 mips_gp_register = tc_get_register (0);
13664 demand_empty_rest_of_line ();
13667 /* Handle the .cprestore pseudo-op. This stores $gp into a given
13668 offset from $sp. The offset is remembered, and after making a PIC
13669 call $gp is restored from that location. */
13672 s_cprestore (int ignore ATTRIBUTE_UNUSED)
13676 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13677 .cprestore is ignored. */
13678 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
13684 mips_cprestore_offset = get_absolute_expression ();
13685 mips_cprestore_valid = 1;
13687 ex.X_op = O_constant;
13688 ex.X_add_symbol = NULL;
13689 ex.X_op_symbol = NULL;
13690 ex.X_add_number = mips_cprestore_offset;
13693 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
13694 SP, HAVE_64BIT_ADDRESSES);
13697 demand_empty_rest_of_line ();
13700 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
13701 was given in the preceding .cpsetup, it results in:
13702 ld $gp, offset($sp)
13704 If a register $reg2 was given there, it results in:
13705 daddu $gp, $reg2, $0 */
13708 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
13712 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
13713 We also need NewABI support. */
13714 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13721 if (mips_cpreturn_register == -1)
13723 ex.X_op = O_constant;
13724 ex.X_add_symbol = NULL;
13725 ex.X_op_symbol = NULL;
13726 ex.X_add_number = mips_cpreturn_offset;
13728 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
13731 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
13732 mips_cpreturn_register, 0);
13735 demand_empty_rest_of_line ();
13738 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
13739 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
13740 use in DWARF debug information. */
13743 s_dtprel_internal (size_t bytes)
13750 if (ex.X_op != O_symbol)
13752 as_bad (_("Unsupported use of %s"), (bytes == 8
13755 ignore_rest_of_line ();
13758 p = frag_more (bytes);
13759 md_number_to_chars (p, 0, bytes);
13760 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
13762 ? BFD_RELOC_MIPS_TLS_DTPREL64
13763 : BFD_RELOC_MIPS_TLS_DTPREL32));
13765 demand_empty_rest_of_line ();
13768 /* Handle .dtprelword. */
13771 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
13773 s_dtprel_internal (4);
13776 /* Handle .dtpreldword. */
13779 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
13781 s_dtprel_internal (8);
13784 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
13785 code. It sets the offset to use in gp_rel relocations. */
13788 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
13790 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
13791 We also need NewABI support. */
13792 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13798 mips_gprel_offset = get_absolute_expression ();
13800 demand_empty_rest_of_line ();
13803 /* Handle the .gpword pseudo-op. This is used when generating PIC
13804 code. It generates a 32 bit GP relative reloc. */
13807 s_gpword (int ignore ATTRIBUTE_UNUSED)
13809 segment_info_type *si;
13810 struct insn_label_list *l;
13815 /* When not generating PIC code, this is treated as .word. */
13816 if (mips_pic != SVR4_PIC)
13822 si = seg_info (now_seg);
13823 l = si->label_list;
13824 label = l != NULL ? l->label : NULL;
13825 mips_emit_delays ();
13827 mips_align (2, 0, label);
13830 mips_clear_insn_labels ();
13832 if (ex.X_op != O_symbol || ex.X_add_number != 0)
13834 as_bad (_("Unsupported use of .gpword"));
13835 ignore_rest_of_line ();
13839 md_number_to_chars (p, 0, 4);
13840 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
13841 BFD_RELOC_GPREL32);
13843 demand_empty_rest_of_line ();
13847 s_gpdword (int ignore ATTRIBUTE_UNUSED)
13849 segment_info_type *si;
13850 struct insn_label_list *l;
13855 /* When not generating PIC code, this is treated as .dword. */
13856 if (mips_pic != SVR4_PIC)
13862 si = seg_info (now_seg);
13863 l = si->label_list;
13864 label = l != NULL ? l->label : NULL;
13865 mips_emit_delays ();
13867 mips_align (3, 0, label);
13870 mips_clear_insn_labels ();
13872 if (ex.X_op != O_symbol || ex.X_add_number != 0)
13874 as_bad (_("Unsupported use of .gpdword"));
13875 ignore_rest_of_line ();
13879 md_number_to_chars (p, 0, 8);
13880 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
13881 BFD_RELOC_GPREL32)->fx_tcbit = 1;
13883 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
13884 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
13885 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
13887 demand_empty_rest_of_line ();
13890 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
13891 tables in SVR4 PIC code. */
13894 s_cpadd (int ignore ATTRIBUTE_UNUSED)
13898 /* This is ignored when not generating SVR4 PIC code. */
13899 if (mips_pic != SVR4_PIC)
13905 /* Add $gp to the register named as an argument. */
13907 reg = tc_get_register (0);
13908 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
13911 demand_empty_rest_of_line ();
13914 /* Handle the .insn pseudo-op. This marks instruction labels in
13915 mips16 mode. This permits the linker to handle them specially,
13916 such as generating jalx instructions when needed. We also make
13917 them odd for the duration of the assembly, in order to generate the
13918 right sort of code. We will make them even in the adjust_symtab
13919 routine, while leaving them marked. This is convenient for the
13920 debugger and the disassembler. The linker knows to make them odd
13924 s_insn (int ignore ATTRIBUTE_UNUSED)
13926 mips16_mark_labels ();
13928 demand_empty_rest_of_line ();
13931 /* Handle a .stabn directive. We need these in order to mark a label
13932 as being a mips16 text label correctly. Sometimes the compiler
13933 will emit a label, followed by a .stabn, and then switch sections.
13934 If the label and .stabn are in mips16 mode, then the label is
13935 really a mips16 text label. */
13938 s_mips_stab (int type)
13941 mips16_mark_labels ();
13946 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
13949 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
13956 name = input_line_pointer;
13957 c = get_symbol_end ();
13958 symbolP = symbol_find_or_make (name);
13959 S_SET_WEAK (symbolP);
13960 *input_line_pointer = c;
13962 SKIP_WHITESPACE ();
13964 if (! is_end_of_line[(unsigned char) *input_line_pointer])
13966 if (S_IS_DEFINED (symbolP))
13968 as_bad (_("ignoring attempt to redefine symbol %s"),
13969 S_GET_NAME (symbolP));
13970 ignore_rest_of_line ();
13974 if (*input_line_pointer == ',')
13976 ++input_line_pointer;
13977 SKIP_WHITESPACE ();
13981 if (exp.X_op != O_symbol)
13983 as_bad (_("bad .weakext directive"));
13984 ignore_rest_of_line ();
13987 symbol_set_value_expression (symbolP, &exp);
13990 demand_empty_rest_of_line ();
13993 /* Parse a register string into a number. Called from the ECOFF code
13994 to parse .frame. The argument is non-zero if this is the frame
13995 register, so that we can record it in mips_frame_reg. */
13998 tc_get_register (int frame)
14002 SKIP_WHITESPACE ();
14003 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
14007 mips_frame_reg = reg != 0 ? reg : SP;
14008 mips_frame_reg_valid = 1;
14009 mips_cprestore_valid = 0;
14015 md_section_align (asection *seg, valueT addr)
14017 int align = bfd_get_section_alignment (stdoutput, seg);
14021 /* We don't need to align ELF sections to the full alignment.
14022 However, Irix 5 may prefer that we align them at least to a 16
14023 byte boundary. We don't bother to align the sections if we
14024 are targeted for an embedded system. */
14025 if (strncmp (TARGET_OS, "elf", 3) == 0)
14031 return ((addr + (1 << align) - 1) & (-1 << align));
14034 /* Utility routine, called from above as well. If called while the
14035 input file is still being read, it's only an approximation. (For
14036 example, a symbol may later become defined which appeared to be
14037 undefined earlier.) */
14040 nopic_need_relax (symbolS *sym, int before_relaxing)
14045 if (g_switch_value > 0)
14047 const char *symname;
14050 /* Find out whether this symbol can be referenced off the $gp
14051 register. It can be if it is smaller than the -G size or if
14052 it is in the .sdata or .sbss section. Certain symbols can
14053 not be referenced off the $gp, although it appears as though
14055 symname = S_GET_NAME (sym);
14056 if (symname != (const char *) NULL
14057 && (strcmp (symname, "eprol") == 0
14058 || strcmp (symname, "etext") == 0
14059 || strcmp (symname, "_gp") == 0
14060 || strcmp (symname, "edata") == 0
14061 || strcmp (symname, "_fbss") == 0
14062 || strcmp (symname, "_fdata") == 0
14063 || strcmp (symname, "_ftext") == 0
14064 || strcmp (symname, "end") == 0
14065 || strcmp (symname, "_gp_disp") == 0))
14067 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
14069 #ifndef NO_ECOFF_DEBUGGING
14070 || (symbol_get_obj (sym)->ecoff_extern_size != 0
14071 && (symbol_get_obj (sym)->ecoff_extern_size
14072 <= g_switch_value))
14074 /* We must defer this decision until after the whole
14075 file has been read, since there might be a .extern
14076 after the first use of this symbol. */
14077 || (before_relaxing
14078 #ifndef NO_ECOFF_DEBUGGING
14079 && symbol_get_obj (sym)->ecoff_extern_size == 0
14081 && S_GET_VALUE (sym) == 0)
14082 || (S_GET_VALUE (sym) != 0
14083 && S_GET_VALUE (sym) <= g_switch_value)))
14087 const char *segname;
14089 segname = segment_name (S_GET_SEGMENT (sym));
14090 gas_assert (strcmp (segname, ".lit8") != 0
14091 && strcmp (segname, ".lit4") != 0);
14092 change = (strcmp (segname, ".sdata") != 0
14093 && strcmp (segname, ".sbss") != 0
14094 && strncmp (segname, ".sdata.", 7) != 0
14095 && strncmp (segname, ".sbss.", 6) != 0
14096 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
14097 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
14102 /* We are not optimizing for the $gp register. */
14107 /* Return true if the given symbol should be considered local for SVR4 PIC. */
14110 pic_need_relax (symbolS *sym, asection *segtype)
14114 /* Handle the case of a symbol equated to another symbol. */
14115 while (symbol_equated_reloc_p (sym))
14119 /* It's possible to get a loop here in a badly written program. */
14120 n = symbol_get_value_expression (sym)->X_add_symbol;
14126 if (symbol_section_p (sym))
14129 symsec = S_GET_SEGMENT (sym);
14131 /* This must duplicate the test in adjust_reloc_syms. */
14132 return (symsec != &bfd_und_section
14133 && symsec != &bfd_abs_section
14134 && !bfd_is_com_section (symsec)
14135 && !s_is_linkonce (sym, segtype)
14137 /* A global or weak symbol is treated as external. */
14138 && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
14144 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
14145 extended opcode. SEC is the section the frag is in. */
14148 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
14151 const struct mips16_immed_operand *op;
14153 int mintiny, maxtiny;
14157 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
14159 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
14162 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
14163 op = mips16_immed_operands;
14164 while (op->type != type)
14167 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
14172 if (type == '<' || type == '>' || type == '[' || type == ']')
14175 maxtiny = 1 << op->nbits;
14180 maxtiny = (1 << op->nbits) - 1;
14185 mintiny = - (1 << (op->nbits - 1));
14186 maxtiny = (1 << (op->nbits - 1)) - 1;
14189 sym_frag = symbol_get_frag (fragp->fr_symbol);
14190 val = S_GET_VALUE (fragp->fr_symbol);
14191 symsec = S_GET_SEGMENT (fragp->fr_symbol);
14197 /* We won't have the section when we are called from
14198 mips_relax_frag. However, we will always have been called
14199 from md_estimate_size_before_relax first. If this is a
14200 branch to a different section, we mark it as such. If SEC is
14201 NULL, and the frag is not marked, then it must be a branch to
14202 the same section. */
14205 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
14210 /* Must have been called from md_estimate_size_before_relax. */
14213 fragp->fr_subtype =
14214 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14216 /* FIXME: We should support this, and let the linker
14217 catch branches and loads that are out of range. */
14218 as_bad_where (fragp->fr_file, fragp->fr_line,
14219 _("unsupported PC relative reference to different section"));
14223 if (fragp != sym_frag && sym_frag->fr_address == 0)
14224 /* Assume non-extended on the first relaxation pass.
14225 The address we have calculated will be bogus if this is
14226 a forward branch to another frag, as the forward frag
14227 will have fr_address == 0. */
14231 /* In this case, we know for sure that the symbol fragment is in
14232 the same section. If the relax_marker of the symbol fragment
14233 differs from the relax_marker of this fragment, we have not
14234 yet adjusted the symbol fragment fr_address. We want to add
14235 in STRETCH in order to get a better estimate of the address.
14236 This particularly matters because of the shift bits. */
14238 && sym_frag->relax_marker != fragp->relax_marker)
14242 /* Adjust stretch for any alignment frag. Note that if have
14243 been expanding the earlier code, the symbol may be
14244 defined in what appears to be an earlier frag. FIXME:
14245 This doesn't handle the fr_subtype field, which specifies
14246 a maximum number of bytes to skip when doing an
14248 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
14250 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
14253 stretch = - ((- stretch)
14254 & ~ ((1 << (int) f->fr_offset) - 1));
14256 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
14265 addr = fragp->fr_address + fragp->fr_fix;
14267 /* The base address rules are complicated. The base address of
14268 a branch is the following instruction. The base address of a
14269 PC relative load or add is the instruction itself, but if it
14270 is in a delay slot (in which case it can not be extended) use
14271 the address of the instruction whose delay slot it is in. */
14272 if (type == 'p' || type == 'q')
14276 /* If we are currently assuming that this frag should be
14277 extended, then, the current address is two bytes
14279 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14282 /* Ignore the low bit in the target, since it will be set
14283 for a text label. */
14284 if ((val & 1) != 0)
14287 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
14289 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
14292 val -= addr & ~ ((1 << op->shift) - 1);
14294 /* Branch offsets have an implicit 0 in the lowest bit. */
14295 if (type == 'p' || type == 'q')
14298 /* If any of the shifted bits are set, we must use an extended
14299 opcode. If the address depends on the size of this
14300 instruction, this can lead to a loop, so we arrange to always
14301 use an extended opcode. We only check this when we are in
14302 the main relaxation loop, when SEC is NULL. */
14303 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
14305 fragp->fr_subtype =
14306 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14310 /* If we are about to mark a frag as extended because the value
14311 is precisely maxtiny + 1, then there is a chance of an
14312 infinite loop as in the following code:
14317 In this case when the la is extended, foo is 0x3fc bytes
14318 away, so the la can be shrunk, but then foo is 0x400 away, so
14319 the la must be extended. To avoid this loop, we mark the
14320 frag as extended if it was small, and is about to become
14321 extended with a value of maxtiny + 1. */
14322 if (val == ((maxtiny + 1) << op->shift)
14323 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
14326 fragp->fr_subtype =
14327 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14331 else if (symsec != absolute_section && sec != NULL)
14332 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
14334 if ((val & ((1 << op->shift) - 1)) != 0
14335 || val < (mintiny << op->shift)
14336 || val > (maxtiny << op->shift))
14342 /* Compute the length of a branch sequence, and adjust the
14343 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
14344 worst-case length is computed, with UPDATE being used to indicate
14345 whether an unconditional (-1), branch-likely (+1) or regular (0)
14346 branch is to be computed. */
14348 relaxed_branch_length (fragS *fragp, asection *sec, int update)
14350 bfd_boolean toofar;
14354 && S_IS_DEFINED (fragp->fr_symbol)
14355 && sec == S_GET_SEGMENT (fragp->fr_symbol))
14360 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
14362 addr = fragp->fr_address + fragp->fr_fix + 4;
14366 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
14369 /* If the symbol is not defined or it's in a different segment,
14370 assume the user knows what's going on and emit a short
14376 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
14378 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
14379 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
14380 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
14381 RELAX_BRANCH_LINK (fragp->fr_subtype),
14387 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
14390 if (mips_pic != NO_PIC)
14392 /* Additional space for PIC loading of target address. */
14394 if (mips_opts.isa == ISA_MIPS1)
14395 /* Additional space for $at-stabilizing nop. */
14399 /* If branch is conditional. */
14400 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
14407 /* Estimate the size of a frag before relaxing. Unless this is the
14408 mips16, we are not really relaxing here, and the final size is
14409 encoded in the subtype information. For the mips16, we have to
14410 decide whether we are using an extended opcode or not. */
14413 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
14417 if (RELAX_BRANCH_P (fragp->fr_subtype))
14420 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
14422 return fragp->fr_var;
14425 if (RELAX_MIPS16_P (fragp->fr_subtype))
14426 /* We don't want to modify the EXTENDED bit here; it might get us
14427 into infinite loops. We change it only in mips_relax_frag(). */
14428 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
14430 if (mips_pic == NO_PIC)
14431 change = nopic_need_relax (fragp->fr_symbol, 0);
14432 else if (mips_pic == SVR4_PIC)
14433 change = pic_need_relax (fragp->fr_symbol, segtype);
14434 else if (mips_pic == VXWORKS_PIC)
14435 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
14442 fragp->fr_subtype |= RELAX_USE_SECOND;
14443 return -RELAX_FIRST (fragp->fr_subtype);
14446 return -RELAX_SECOND (fragp->fr_subtype);
14449 /* This is called to see whether a reloc against a defined symbol
14450 should be converted into a reloc against a section. */
14453 mips_fix_adjustable (fixS *fixp)
14455 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
14456 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
14459 if (fixp->fx_addsy == NULL)
14462 /* If symbol SYM is in a mergeable section, relocations of the form
14463 SYM + 0 can usually be made section-relative. The mergeable data
14464 is then identified by the section offset rather than by the symbol.
14466 However, if we're generating REL LO16 relocations, the offset is split
14467 between the LO16 and parterning high part relocation. The linker will
14468 need to recalculate the complete offset in order to correctly identify
14471 The linker has traditionally not looked for the parterning high part
14472 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
14473 placed anywhere. Rather than break backwards compatibility by changing
14474 this, it seems better not to force the issue, and instead keep the
14475 original symbol. This will work with either linker behavior. */
14476 if ((lo16_reloc_p (fixp->fx_r_type)
14477 || reloc_needs_lo_p (fixp->fx_r_type))
14478 && HAVE_IN_PLACE_ADDENDS
14479 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
14482 /* There is no place to store an in-place offset for JALR relocations.
14483 Likewise an in-range offset of PC-relative relocations may overflow
14484 the in-place relocatable field if recalculated against the start
14485 address of the symbol's containing section. */
14486 if (HAVE_IN_PLACE_ADDENDS
14487 && (fixp->fx_pcrel || fixp->fx_r_type == BFD_RELOC_MIPS_JALR))
14491 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
14492 to a floating-point stub. The same is true for non-R_MIPS16_26
14493 relocations against MIPS16 functions; in this case, the stub becomes
14494 the function's canonical address.
14496 Floating-point stubs are stored in unique .mips16.call.* or
14497 .mips16.fn.* sections. If a stub T for function F is in section S,
14498 the first relocation in section S must be against F; this is how the
14499 linker determines the target function. All relocations that might
14500 resolve to T must also be against F. We therefore have the following
14501 restrictions, which are given in an intentionally-redundant way:
14503 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
14506 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
14507 if that stub might be used.
14509 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
14512 4. We cannot reduce a stub's relocations against MIPS16 symbols if
14513 that stub might be used.
14515 There is a further restriction:
14517 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols
14518 on targets with in-place addends; the relocation field cannot
14519 encode the low bit.
14521 For simplicity, we deal with (3)-(5) by not reducing _any_ relocation
14522 against a MIPS16 symbol.
14524 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
14525 relocation against some symbol R, no relocation against R may be
14526 reduced. (Note that this deals with (2) as well as (1) because
14527 relocations against global symbols will never be reduced on ELF
14528 targets.) This approach is a little simpler than trying to detect
14529 stub sections, and gives the "all or nothing" per-symbol consistency
14530 that we have for MIPS16 symbols. */
14532 && fixp->fx_subsy == NULL
14533 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
14534 || *symbol_get_tc (fixp->fx_addsy)))
14541 /* Translate internal representation of relocation info to BFD target
14545 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
14547 static arelent *retval[4];
14549 bfd_reloc_code_real_type code;
14551 memset (retval, 0, sizeof(retval));
14552 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
14553 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
14554 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
14555 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
14557 if (fixp->fx_pcrel)
14559 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2);
14561 /* At this point, fx_addnumber is "symbol offset - pcrel address".
14562 Relocations want only the symbol offset. */
14563 reloc->addend = fixp->fx_addnumber + reloc->address;
14566 /* A gruesome hack which is a result of the gruesome gas
14567 reloc handling. What's worse, for COFF (as opposed to
14568 ECOFF), we might need yet another copy of reloc->address.
14569 See bfd_install_relocation. */
14570 reloc->addend += reloc->address;
14574 reloc->addend = fixp->fx_addnumber;
14576 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
14577 entry to be used in the relocation's section offset. */
14578 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
14580 reloc->address = reloc->addend;
14584 code = fixp->fx_r_type;
14586 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
14587 if (reloc->howto == NULL)
14589 as_bad_where (fixp->fx_file, fixp->fx_line,
14590 _("Can not represent %s relocation in this object file format"),
14591 bfd_get_reloc_code_name (code));
14598 /* Relax a machine dependent frag. This returns the amount by which
14599 the current size of the frag should change. */
14602 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
14604 if (RELAX_BRANCH_P (fragp->fr_subtype))
14606 offsetT old_var = fragp->fr_var;
14608 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
14610 return fragp->fr_var - old_var;
14613 if (! RELAX_MIPS16_P (fragp->fr_subtype))
14616 if (mips16_extended_frag (fragp, NULL, stretch))
14618 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14620 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
14625 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14627 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
14634 /* Convert a machine dependent frag. */
14637 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
14639 if (RELAX_BRANCH_P (fragp->fr_subtype))
14642 unsigned long insn;
14646 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
14648 if (target_big_endian)
14649 insn = bfd_getb32 (buf);
14651 insn = bfd_getl32 (buf);
14653 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
14655 /* We generate a fixup instead of applying it right now
14656 because, if there are linker relaxations, we're going to
14657 need the relocations. */
14658 exp.X_op = O_symbol;
14659 exp.X_add_symbol = fragp->fr_symbol;
14660 exp.X_add_number = fragp->fr_offset;
14662 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14663 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2);
14664 fixp->fx_file = fragp->fr_file;
14665 fixp->fx_line = fragp->fr_line;
14667 md_number_to_chars ((char *) buf, insn, 4);
14674 as_warn_where (fragp->fr_file, fragp->fr_line,
14675 _("Relaxed out-of-range branch into a jump"));
14677 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
14680 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14682 /* Reverse the branch. */
14683 switch ((insn >> 28) & 0xf)
14686 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
14687 have the condition reversed by tweaking a single
14688 bit, and their opcodes all have 0x4???????. */
14689 gas_assert ((insn & 0xf1000000) == 0x41000000);
14690 insn ^= 0x00010000;
14694 /* bltz 0x04000000 bgez 0x04010000
14695 bltzal 0x04100000 bgezal 0x04110000 */
14696 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
14697 insn ^= 0x00010000;
14701 /* beq 0x10000000 bne 0x14000000
14702 blez 0x18000000 bgtz 0x1c000000 */
14703 insn ^= 0x04000000;
14711 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
14713 /* Clear the and-link bit. */
14714 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
14716 /* bltzal 0x04100000 bgezal 0x04110000
14717 bltzall 0x04120000 bgezall 0x04130000 */
14718 insn &= ~0x00100000;
14721 /* Branch over the branch (if the branch was likely) or the
14722 full jump (not likely case). Compute the offset from the
14723 current instruction to branch to. */
14724 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14728 /* How many bytes in instructions we've already emitted? */
14729 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
14730 /* How many bytes in instructions from here to the end? */
14731 i = fragp->fr_var - i;
14733 /* Convert to instruction count. */
14735 /* Branch counts from the next instruction. */
14738 /* Branch over the jump. */
14739 md_number_to_chars ((char *) buf, insn, 4);
14743 md_number_to_chars ((char *) buf, 0, 4);
14746 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14748 /* beql $0, $0, 2f */
14750 /* Compute the PC offset from the current instruction to
14751 the end of the variable frag. */
14752 /* How many bytes in instructions we've already emitted? */
14753 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
14754 /* How many bytes in instructions from here to the end? */
14755 i = fragp->fr_var - i;
14756 /* Convert to instruction count. */
14758 /* Don't decrement i, because we want to branch over the
14762 md_number_to_chars ((char *) buf, insn, 4);
14765 md_number_to_chars ((char *) buf, 0, 4);
14770 if (mips_pic == NO_PIC)
14773 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
14774 ? 0x0c000000 : 0x08000000);
14775 exp.X_op = O_symbol;
14776 exp.X_add_symbol = fragp->fr_symbol;
14777 exp.X_add_number = fragp->fr_offset;
14779 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14780 4, &exp, FALSE, BFD_RELOC_MIPS_JMP);
14781 fixp->fx_file = fragp->fr_file;
14782 fixp->fx_line = fragp->fr_line;
14784 md_number_to_chars ((char *) buf, insn, 4);
14789 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
14791 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
14792 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
14793 insn |= at << OP_SH_RT;
14794 exp.X_op = O_symbol;
14795 exp.X_add_symbol = fragp->fr_symbol;
14796 exp.X_add_number = fragp->fr_offset;
14798 if (fragp->fr_offset)
14800 exp.X_add_symbol = make_expr_symbol (&exp);
14801 exp.X_add_number = 0;
14804 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14805 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16);
14806 fixp->fx_file = fragp->fr_file;
14807 fixp->fx_line = fragp->fr_line;
14809 md_number_to_chars ((char *) buf, insn, 4);
14812 if (mips_opts.isa == ISA_MIPS1)
14815 md_number_to_chars ((char *) buf, 0, 4);
14819 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
14820 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
14821 insn |= at << OP_SH_RS | at << OP_SH_RT;
14823 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14824 4, &exp, FALSE, BFD_RELOC_LO16);
14825 fixp->fx_file = fragp->fr_file;
14826 fixp->fx_line = fragp->fr_line;
14828 md_number_to_chars ((char *) buf, insn, 4);
14832 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
14836 insn |= at << OP_SH_RS;
14838 md_number_to_chars ((char *) buf, insn, 4);
14843 gas_assert (buf == (bfd_byte *)fragp->fr_literal
14844 + fragp->fr_fix + fragp->fr_var);
14846 fragp->fr_fix += fragp->fr_var;
14851 if (RELAX_MIPS16_P (fragp->fr_subtype))
14854 const struct mips16_immed_operand *op;
14855 bfd_boolean small, ext;
14858 unsigned long insn;
14859 bfd_boolean use_extend;
14860 unsigned short extend;
14862 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
14863 op = mips16_immed_operands;
14864 while (op->type != type)
14867 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14878 val = resolve_symbol_value (fragp->fr_symbol);
14883 addr = fragp->fr_address + fragp->fr_fix;
14885 /* The rules for the base address of a PC relative reloc are
14886 complicated; see mips16_extended_frag. */
14887 if (type == 'p' || type == 'q')
14892 /* Ignore the low bit in the target, since it will be
14893 set for a text label. */
14894 if ((val & 1) != 0)
14897 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
14899 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
14902 addr &= ~ (addressT) ((1 << op->shift) - 1);
14905 /* Make sure the section winds up with the alignment we have
14908 record_alignment (asec, op->shift);
14912 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
14913 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
14914 as_warn_where (fragp->fr_file, fragp->fr_line,
14915 _("extended instruction in delay slot"));
14917 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
14919 if (target_big_endian)
14920 insn = bfd_getb16 (buf);
14922 insn = bfd_getl16 (buf);
14924 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
14925 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
14926 small, ext, &insn, &use_extend, &extend);
14930 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
14931 fragp->fr_fix += 2;
14935 md_number_to_chars ((char *) buf, insn, 2);
14936 fragp->fr_fix += 2;
14944 first = RELAX_FIRST (fragp->fr_subtype);
14945 second = RELAX_SECOND (fragp->fr_subtype);
14946 fixp = (fixS *) fragp->fr_opcode;
14948 /* Possibly emit a warning if we've chosen the longer option. */
14949 if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0)
14950 == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0))
14952 const char *msg = macro_warning (fragp->fr_subtype);
14954 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
14957 /* Go through all the fixups for the first sequence. Disable them
14958 (by marking them as done) if we're going to use the second
14959 sequence instead. */
14961 && fixp->fx_frag == fragp
14962 && fixp->fx_where < fragp->fr_fix - second)
14964 if (fragp->fr_subtype & RELAX_USE_SECOND)
14966 fixp = fixp->fx_next;
14969 /* Go through the fixups for the second sequence. Disable them if
14970 we're going to use the first sequence, otherwise adjust their
14971 addresses to account for the relaxation. */
14972 while (fixp && fixp->fx_frag == fragp)
14974 if (fragp->fr_subtype & RELAX_USE_SECOND)
14975 fixp->fx_where -= first;
14978 fixp = fixp->fx_next;
14981 /* Now modify the frag contents. */
14982 if (fragp->fr_subtype & RELAX_USE_SECOND)
14986 start = fragp->fr_literal + fragp->fr_fix - first - second;
14987 memmove (start, start + first, second);
14988 fragp->fr_fix -= first;
14991 fragp->fr_fix -= second;
14997 /* This function is called after the relocs have been generated.
14998 We've been storing mips16 text labels as odd. Here we convert them
14999 back to even for the convenience of the debugger. */
15002 mips_frob_file_after_relocs (void)
15005 unsigned int count, i;
15010 syms = bfd_get_outsymbols (stdoutput);
15011 count = bfd_get_symcount (stdoutput);
15012 for (i = 0; i < count; i++, syms++)
15014 if (ELF_ST_IS_MIPS16 (elf_symbol (*syms)->internal_elf_sym.st_other)
15015 && ((*syms)->value & 1) != 0)
15017 (*syms)->value &= ~1;
15018 /* If the symbol has an odd size, it was probably computed
15019 incorrectly, so adjust that as well. */
15020 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
15021 ++elf_symbol (*syms)->internal_elf_sym.st_size;
15028 /* This function is called whenever a label is defined, including fake
15029 labels instantiated off the dot special symbol. It is used when
15030 handling branch delays; if a branch has a label, we assume we cannot
15031 move it. This also bumps the value of the symbol by 1 in compressed
15035 mips_record_label (symbolS *sym)
15037 segment_info_type *si = seg_info (now_seg);
15038 struct insn_label_list *l;
15040 if (free_insn_labels == NULL)
15041 l = (struct insn_label_list *) xmalloc (sizeof *l);
15044 l = free_insn_labels;
15045 free_insn_labels = l->next;
15049 l->next = si->label_list;
15050 si->label_list = l;
15053 /* This function is called as tc_frob_label() whenever a label is defined
15054 and adds a DWARF-2 record we only want for true labels. */
15057 mips_define_label (symbolS *sym)
15059 mips_record_label (sym);
15061 dwarf2_emit_label (sym);
15065 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15067 /* Some special processing for a MIPS ELF file. */
15070 mips_elf_final_processing (void)
15072 /* Write out the register information. */
15073 if (mips_abi != N64_ABI)
15077 s.ri_gprmask = mips_gprmask;
15078 s.ri_cprmask[0] = mips_cprmask[0];
15079 s.ri_cprmask[1] = mips_cprmask[1];
15080 s.ri_cprmask[2] = mips_cprmask[2];
15081 s.ri_cprmask[3] = mips_cprmask[3];
15082 /* The gp_value field is set by the MIPS ELF backend. */
15084 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
15085 ((Elf32_External_RegInfo *)
15086 mips_regmask_frag));
15090 Elf64_Internal_RegInfo s;
15092 s.ri_gprmask = mips_gprmask;
15094 s.ri_cprmask[0] = mips_cprmask[0];
15095 s.ri_cprmask[1] = mips_cprmask[1];
15096 s.ri_cprmask[2] = mips_cprmask[2];
15097 s.ri_cprmask[3] = mips_cprmask[3];
15098 /* The gp_value field is set by the MIPS ELF backend. */
15100 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
15101 ((Elf64_External_RegInfo *)
15102 mips_regmask_frag));
15105 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
15106 sort of BFD interface for this. */
15107 if (mips_any_noreorder)
15108 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
15109 if (mips_pic != NO_PIC)
15111 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
15112 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
15115 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
15117 /* Set MIPS ELF flags for ASEs. */
15118 /* We may need to define a new flag for DSP ASE, and set this flag when
15119 file_ase_dsp is true. */
15120 /* Same for DSP R2. */
15121 /* We may need to define a new flag for MT ASE, and set this flag when
15122 file_ase_mt is true. */
15123 if (file_ase_mips16)
15124 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
15125 #if 0 /* XXX FIXME */
15126 if (file_ase_mips3d)
15127 elf_elfheader (stdoutput)->e_flags |= ???;
15130 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
15132 /* Set the MIPS ELF ABI flags. */
15133 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
15134 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
15135 else if (mips_abi == O64_ABI)
15136 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
15137 else if (mips_abi == EABI_ABI)
15139 if (!file_mips_gp32)
15140 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
15142 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
15144 else if (mips_abi == N32_ABI)
15145 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
15147 /* Nothing to do for N64_ABI. */
15149 if (mips_32bitmode)
15150 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
15152 #if 0 /* XXX FIXME */
15153 /* 32 bit code with 64 bit FP registers. */
15154 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
15155 elf_elfheader (stdoutput)->e_flags |= ???;
15159 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
15161 typedef struct proc {
15163 symbolS *func_end_sym;
15164 unsigned long reg_mask;
15165 unsigned long reg_offset;
15166 unsigned long fpreg_mask;
15167 unsigned long fpreg_offset;
15168 unsigned long frame_offset;
15169 unsigned long frame_reg;
15170 unsigned long pc_reg;
15173 static procS cur_proc;
15174 static procS *cur_proc_ptr;
15175 static int numprocs;
15177 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal
15181 mips_nop_opcode (void)
15183 return seg_info (now_seg)->tc_segment_info_data.mips16;
15186 /* Fill in an rs_align_code fragment. This only needs to do something
15187 for MIPS16 code, where 0 is not a nop. */
15190 mips_handle_align (fragS *fragp)
15193 int bytes, size, excess;
15196 if (fragp->fr_type != rs_align_code)
15199 p = fragp->fr_literal + fragp->fr_fix;
15202 opcode = mips16_nop_insn.insn_opcode;
15207 opcode = nop_insn.insn_opcode;
15211 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
15212 excess = bytes % size;
15215 /* If we're not inserting a whole number of instructions,
15216 pad the end of the fixed part of the frag with zeros. */
15217 memset (p, 0, excess);
15219 fragp->fr_fix += excess;
15222 md_number_to_chars (p, opcode, size);
15223 fragp->fr_var = size;
15227 md_obj_begin (void)
15234 /* Check for premature end, nesting errors, etc. */
15236 as_warn (_("missing .end at end of assembly"));
15245 if (*input_line_pointer == '-')
15247 ++input_line_pointer;
15250 if (!ISDIGIT (*input_line_pointer))
15251 as_bad (_("expected simple number"));
15252 if (input_line_pointer[0] == '0')
15254 if (input_line_pointer[1] == 'x')
15256 input_line_pointer += 2;
15257 while (ISXDIGIT (*input_line_pointer))
15260 val |= hex_value (*input_line_pointer++);
15262 return negative ? -val : val;
15266 ++input_line_pointer;
15267 while (ISDIGIT (*input_line_pointer))
15270 val |= *input_line_pointer++ - '0';
15272 return negative ? -val : val;
15275 if (!ISDIGIT (*input_line_pointer))
15277 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
15278 *input_line_pointer, *input_line_pointer);
15279 as_warn (_("invalid number"));
15282 while (ISDIGIT (*input_line_pointer))
15285 val += *input_line_pointer++ - '0';
15287 return negative ? -val : val;
15290 /* The .file directive; just like the usual .file directive, but there
15291 is an initial number which is the ECOFF file index. In the non-ECOFF
15292 case .file implies DWARF-2. */
15295 s_mips_file (int x ATTRIBUTE_UNUSED)
15297 static int first_file_directive = 0;
15299 if (ECOFF_DEBUGGING)
15308 filename = dwarf2_directive_file (0);
15310 /* Versions of GCC up to 3.1 start files with a ".file"
15311 directive even for stabs output. Make sure that this
15312 ".file" is handled. Note that you need a version of GCC
15313 after 3.1 in order to support DWARF-2 on MIPS. */
15314 if (filename != NULL && ! first_file_directive)
15316 (void) new_logical_line (filename, -1);
15317 s_app_file_string (filename, 0);
15319 first_file_directive = 1;
15323 /* The .loc directive, implying DWARF-2. */
15326 s_mips_loc (int x ATTRIBUTE_UNUSED)
15328 if (!ECOFF_DEBUGGING)
15329 dwarf2_directive_loc (0);
15332 /* The .end directive. */
15335 s_mips_end (int x ATTRIBUTE_UNUSED)
15339 /* Following functions need their own .frame and .cprestore directives. */
15340 mips_frame_reg_valid = 0;
15341 mips_cprestore_valid = 0;
15343 if (!is_end_of_line[(unsigned char) *input_line_pointer])
15346 demand_empty_rest_of_line ();
15351 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
15352 as_warn (_(".end not in text section"));
15356 as_warn (_(".end directive without a preceding .ent directive."));
15357 demand_empty_rest_of_line ();
15363 gas_assert (S_GET_NAME (p));
15364 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
15365 as_warn (_(".end symbol does not match .ent symbol."));
15367 if (debug_type == DEBUG_STABS)
15368 stabs_generate_asm_endfunc (S_GET_NAME (p),
15372 as_warn (_(".end directive missing or unknown symbol"));
15375 /* Create an expression to calculate the size of the function. */
15376 if (p && cur_proc_ptr)
15378 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
15379 expressionS *exp = xmalloc (sizeof (expressionS));
15382 exp->X_op = O_subtract;
15383 exp->X_add_symbol = symbol_temp_new_now ();
15384 exp->X_op_symbol = p;
15385 exp->X_add_number = 0;
15387 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
15390 /* Generate a .pdr section. */
15391 if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr)
15393 segT saved_seg = now_seg;
15394 subsegT saved_subseg = now_subseg;
15398 #ifdef md_flush_pending_output
15399 md_flush_pending_output ();
15402 gas_assert (pdr_seg);
15403 subseg_set (pdr_seg, 0);
15405 /* Write the symbol. */
15406 exp.X_op = O_symbol;
15407 exp.X_add_symbol = p;
15408 exp.X_add_number = 0;
15409 emit_expr (&exp, 4);
15411 fragp = frag_more (7 * 4);
15413 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
15414 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
15415 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
15416 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
15417 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
15418 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
15419 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
15421 subseg_set (saved_seg, saved_subseg);
15423 #endif /* OBJ_ELF */
15425 cur_proc_ptr = NULL;
15428 /* The .aent and .ent directives. */
15431 s_mips_ent (int aent)
15435 symbolP = get_symbol ();
15436 if (*input_line_pointer == ',')
15437 ++input_line_pointer;
15438 SKIP_WHITESPACE ();
15439 if (ISDIGIT (*input_line_pointer)
15440 || *input_line_pointer == '-')
15443 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
15444 as_warn (_(".ent or .aent not in text section."));
15446 if (!aent && cur_proc_ptr)
15447 as_warn (_("missing .end"));
15451 /* This function needs its own .frame and .cprestore directives. */
15452 mips_frame_reg_valid = 0;
15453 mips_cprestore_valid = 0;
15455 cur_proc_ptr = &cur_proc;
15456 memset (cur_proc_ptr, '\0', sizeof (procS));
15458 cur_proc_ptr->func_sym = symbolP;
15462 if (debug_type == DEBUG_STABS)
15463 stabs_generate_asm_func (S_GET_NAME (symbolP),
15464 S_GET_NAME (symbolP));
15467 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
15469 demand_empty_rest_of_line ();
15472 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
15473 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
15474 s_mips_frame is used so that we can set the PDR information correctly.
15475 We can't use the ecoff routines because they make reference to the ecoff
15476 symbol table (in the mdebug section). */
15479 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
15482 if (IS_ELF && !ECOFF_DEBUGGING)
15486 if (cur_proc_ptr == (procS *) NULL)
15488 as_warn (_(".frame outside of .ent"));
15489 demand_empty_rest_of_line ();
15493 cur_proc_ptr->frame_reg = tc_get_register (1);
15495 SKIP_WHITESPACE ();
15496 if (*input_line_pointer++ != ','
15497 || get_absolute_expression_and_terminator (&val) != ',')
15499 as_warn (_("Bad .frame directive"));
15500 --input_line_pointer;
15501 demand_empty_rest_of_line ();
15505 cur_proc_ptr->frame_offset = val;
15506 cur_proc_ptr->pc_reg = tc_get_register (0);
15508 demand_empty_rest_of_line ();
15511 #endif /* OBJ_ELF */
15515 /* The .fmask and .mask directives. If the mdebug section is present
15516 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
15517 embedded targets, s_mips_mask is used so that we can set the PDR
15518 information correctly. We can't use the ecoff routines because they
15519 make reference to the ecoff symbol table (in the mdebug section). */
15522 s_mips_mask (int reg_type)
15525 if (IS_ELF && !ECOFF_DEBUGGING)
15529 if (cur_proc_ptr == (procS *) NULL)
15531 as_warn (_(".mask/.fmask outside of .ent"));
15532 demand_empty_rest_of_line ();
15536 if (get_absolute_expression_and_terminator (&mask) != ',')
15538 as_warn (_("Bad .mask/.fmask directive"));
15539 --input_line_pointer;
15540 demand_empty_rest_of_line ();
15544 off = get_absolute_expression ();
15546 if (reg_type == 'F')
15548 cur_proc_ptr->fpreg_mask = mask;
15549 cur_proc_ptr->fpreg_offset = off;
15553 cur_proc_ptr->reg_mask = mask;
15554 cur_proc_ptr->reg_offset = off;
15557 demand_empty_rest_of_line ();
15560 #endif /* OBJ_ELF */
15561 s_ignore (reg_type);
15564 /* A table describing all the processors gas knows about. Names are
15565 matched in the order listed.
15567 To ease comparison, please keep this table in the same order as
15568 gcc's mips_cpu_info_table[]. */
15569 static const struct mips_cpu_info mips_cpu_info_table[] =
15571 /* Entries for generic ISAs */
15572 { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 },
15573 { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 },
15574 { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 },
15575 { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 },
15576 { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 },
15577 { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 },
15578 { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 },
15579 { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
15580 { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
15583 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
15584 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
15585 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
15588 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
15591 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
15592 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
15593 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
15594 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
15595 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
15596 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
15597 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
15598 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
15599 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
15600 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
15601 { "orion", 0, ISA_MIPS3, CPU_R4600 },
15602 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
15603 /* ST Microelectronics Loongson 2E and 2F cores */
15604 { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E },
15605 { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F },
15608 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
15609 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
15610 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
15611 { "r14000", 0, ISA_MIPS4, CPU_R14000 },
15612 { "r16000", 0, ISA_MIPS4, CPU_R16000 },
15613 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
15614 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
15615 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
15616 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
15617 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
15618 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
15619 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
15620 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
15621 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
15622 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
15625 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
15626 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
15627 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
15628 { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
15630 /* MIPS 32 Release 2 */
15631 { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15632 { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15633 { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15634 { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
15635 { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15636 { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15637 { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15638 { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15639 { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15640 { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15641 /* Deprecated forms of the above. */
15642 { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15643 { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15644 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
15645 { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15646 { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15647 { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15648 { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15649 /* Deprecated forms of the above. */
15650 { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15651 { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15652 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
15653 { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15654 ISA_MIPS32R2, CPU_MIPS32R2 },
15655 { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15656 ISA_MIPS32R2, CPU_MIPS32R2 },
15657 { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15658 ISA_MIPS32R2, CPU_MIPS32R2 },
15659 { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15660 ISA_MIPS32R2, CPU_MIPS32R2 },
15661 /* Deprecated forms of the above. */
15662 { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15663 ISA_MIPS32R2, CPU_MIPS32R2 },
15664 { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15665 ISA_MIPS32R2, CPU_MIPS32R2 },
15666 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
15667 { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15668 ISA_MIPS32R2, CPU_MIPS32R2 },
15669 { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15670 ISA_MIPS32R2, CPU_MIPS32R2 },
15671 { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15672 ISA_MIPS32R2, CPU_MIPS32R2 },
15673 { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15674 ISA_MIPS32R2, CPU_MIPS32R2 },
15675 { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15676 ISA_MIPS32R2, CPU_MIPS32R2 },
15677 /* Deprecated forms of the above. */
15678 { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15679 ISA_MIPS32R2, CPU_MIPS32R2 },
15680 { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15681 ISA_MIPS32R2, CPU_MIPS32R2 },
15682 /* 1004K cores are multiprocessor versions of the 34K. */
15683 { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15684 ISA_MIPS32R2, CPU_MIPS32R2 },
15685 { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15686 ISA_MIPS32R2, CPU_MIPS32R2 },
15687 { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15688 ISA_MIPS32R2, CPU_MIPS32R2 },
15689 { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15690 ISA_MIPS32R2, CPU_MIPS32R2 },
15693 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
15694 { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
15695 { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
15696 { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
15698 /* Broadcom SB-1 CPU core */
15699 { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
15700 ISA_MIPS64, CPU_SB1 },
15701 /* Broadcom SB-1A CPU core */
15702 { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
15703 ISA_MIPS64, CPU_SB1 },
15705 { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A },
15707 /* MIPS 64 Release 2 */
15709 /* Cavium Networks Octeon CPU core */
15710 { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
15713 { "xlr", 0, ISA_MIPS64, CPU_XLR },
15720 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
15721 with a final "000" replaced by "k". Ignore case.
15723 Note: this function is shared between GCC and GAS. */
15726 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
15728 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
15729 given++, canonical++;
15731 return ((*given == 0 && *canonical == 0)
15732 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
15736 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
15737 CPU name. We've traditionally allowed a lot of variation here.
15739 Note: this function is shared between GCC and GAS. */
15742 mips_matching_cpu_name_p (const char *canonical, const char *given)
15744 /* First see if the name matches exactly, or with a final "000"
15745 turned into "k". */
15746 if (mips_strict_matching_cpu_name_p (canonical, given))
15749 /* If not, try comparing based on numerical designation alone.
15750 See if GIVEN is an unadorned number, or 'r' followed by a number. */
15751 if (TOLOWER (*given) == 'r')
15753 if (!ISDIGIT (*given))
15756 /* Skip over some well-known prefixes in the canonical name,
15757 hoping to find a number there too. */
15758 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
15760 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
15762 else if (TOLOWER (canonical[0]) == 'r')
15765 return mips_strict_matching_cpu_name_p (canonical, given);
15769 /* Parse an option that takes the name of a processor as its argument.
15770 OPTION is the name of the option and CPU_STRING is the argument.
15771 Return the corresponding processor enumeration if the CPU_STRING is
15772 recognized, otherwise report an error and return null.
15774 A similar function exists in GCC. */
15776 static const struct mips_cpu_info *
15777 mips_parse_cpu (const char *option, const char *cpu_string)
15779 const struct mips_cpu_info *p;
15781 /* 'from-abi' selects the most compatible architecture for the given
15782 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
15783 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15784 version. Look first at the -mgp options, if given, otherwise base
15785 the choice on MIPS_DEFAULT_64BIT.
15787 Treat NO_ABI like the EABIs. One reason to do this is that the
15788 plain 'mips' and 'mips64' configs have 'from-abi' as their default
15789 architecture. This code picks MIPS I for 'mips' and MIPS III for
15790 'mips64', just as we did in the days before 'from-abi'. */
15791 if (strcasecmp (cpu_string, "from-abi") == 0)
15793 if (ABI_NEEDS_32BIT_REGS (mips_abi))
15794 return mips_cpu_info_from_isa (ISA_MIPS1);
15796 if (ABI_NEEDS_64BIT_REGS (mips_abi))
15797 return mips_cpu_info_from_isa (ISA_MIPS3);
15799 if (file_mips_gp32 >= 0)
15800 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
15802 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
15807 /* 'default' has traditionally been a no-op. Probably not very useful. */
15808 if (strcasecmp (cpu_string, "default") == 0)
15811 for (p = mips_cpu_info_table; p->name != 0; p++)
15812 if (mips_matching_cpu_name_p (p->name, cpu_string))
15815 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
15819 /* Return the canonical processor information for ISA (a member of the
15820 ISA_MIPS* enumeration). */
15822 static const struct mips_cpu_info *
15823 mips_cpu_info_from_isa (int isa)
15827 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15828 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
15829 && isa == mips_cpu_info_table[i].isa)
15830 return (&mips_cpu_info_table[i]);
15835 static const struct mips_cpu_info *
15836 mips_cpu_info_from_arch (int arch)
15840 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15841 if (arch == mips_cpu_info_table[i].cpu)
15842 return (&mips_cpu_info_table[i]);
15848 show (FILE *stream, const char *string, int *col_p, int *first_p)
15852 fprintf (stream, "%24s", "");
15857 fprintf (stream, ", ");
15861 if (*col_p + strlen (string) > 72)
15863 fprintf (stream, "\n%24s", "");
15867 fprintf (stream, "%s", string);
15868 *col_p += strlen (string);
15874 md_show_usage (FILE *stream)
15879 fprintf (stream, _("\
15881 -EB generate big endian output\n\
15882 -EL generate little endian output\n\
15883 -g, -g2 do not remove unneeded NOPs or swap branches\n\
15884 -G NUM allow referencing objects up to NUM bytes\n\
15885 implicitly with the gp register [default 8]\n"));
15886 fprintf (stream, _("\
15887 -mips1 generate MIPS ISA I instructions\n\
15888 -mips2 generate MIPS ISA II instructions\n\
15889 -mips3 generate MIPS ISA III instructions\n\
15890 -mips4 generate MIPS ISA IV instructions\n\
15891 -mips5 generate MIPS ISA V instructions\n\
15892 -mips32 generate MIPS32 ISA instructions\n\
15893 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
15894 -mips64 generate MIPS64 ISA instructions\n\
15895 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
15896 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
15900 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15901 show (stream, mips_cpu_info_table[i].name, &column, &first);
15902 show (stream, "from-abi", &column, &first);
15903 fputc ('\n', stream);
15905 fprintf (stream, _("\
15906 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
15907 -no-mCPU don't generate code specific to CPU.\n\
15908 For -mCPU and -no-mCPU, CPU must be one of:\n"));
15912 show (stream, "3900", &column, &first);
15913 show (stream, "4010", &column, &first);
15914 show (stream, "4100", &column, &first);
15915 show (stream, "4650", &column, &first);
15916 fputc ('\n', stream);
15918 fprintf (stream, _("\
15919 -mips16 generate mips16 instructions\n\
15920 -no-mips16 do not generate mips16 instructions\n"));
15921 fprintf (stream, _("\
15922 -msmartmips generate smartmips instructions\n\
15923 -mno-smartmips do not generate smartmips instructions\n"));
15924 fprintf (stream, _("\
15925 -mdsp generate DSP instructions\n\
15926 -mno-dsp do not generate DSP instructions\n"));
15927 fprintf (stream, _("\
15928 -mdspr2 generate DSP R2 instructions\n\
15929 -mno-dspr2 do not generate DSP R2 instructions\n"));
15930 fprintf (stream, _("\
15931 -mmt generate MT instructions\n\
15932 -mno-mt do not generate MT instructions\n"));
15933 fprintf (stream, _("\
15934 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
15935 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
15936 -mfix-vr4120 work around certain VR4120 errata\n\
15937 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
15938 -mfix-24k insert a nop after ERET and DERET instructions\n\
15939 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
15940 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
15941 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
15942 -msym32 assume all symbols have 32-bit values\n\
15943 -O0 remove unneeded NOPs, do not swap branches\n\
15944 -O remove unneeded NOPs and swap branches\n\
15945 --trap, --no-break trap exception on div by 0 and mult overflow\n\
15946 --break, --no-trap break exception on div by 0 and mult overflow\n"));
15947 fprintf (stream, _("\
15948 -mhard-float allow floating-point instructions\n\
15949 -msoft-float do not allow floating-point instructions\n\
15950 -msingle-float only allow 32-bit floating-point operations\n\
15951 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
15952 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
15955 fprintf (stream, _("\
15956 -KPIC, -call_shared generate SVR4 position independent code\n\
15957 -call_nonpic generate non-PIC code that can operate with DSOs\n\
15958 -mvxworks-pic generate VxWorks position independent code\n\
15959 -non_shared do not generate code that can operate with DSOs\n\
15960 -xgot assume a 32 bit GOT\n\
15961 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
15962 -mshared, -mno-shared disable/enable .cpload optimization for\n\
15963 position dependent (non shared) code\n\
15964 -mabi=ABI create ABI conformant object file for:\n"));
15968 show (stream, "32", &column, &first);
15969 show (stream, "o64", &column, &first);
15970 show (stream, "n32", &column, &first);
15971 show (stream, "64", &column, &first);
15972 show (stream, "eabi", &column, &first);
15974 fputc ('\n', stream);
15976 fprintf (stream, _("\
15977 -32 create o32 ABI object file (default)\n\
15978 -n32 create n32 ABI object file\n\
15979 -64 create 64 ABI object file\n"));
15985 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
15987 if (HAVE_64BIT_SYMBOLS)
15988 return dwarf2_format_64bit_irix;
15990 return dwarf2_format_32bit;
15995 mips_dwarf2_addr_size (void)
15997 if (HAVE_64BIT_OBJECTS)
16003 /* Standard calling conventions leave the CFA at SP on entry. */
16005 mips_cfi_frame_initial_instructions (void)
16007 cfi_add_CFA_def_cfa_register (SP);
16011 tc_mips_regname_to_dw2regnum (char *regname)
16013 unsigned int regnum = -1;
16016 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))