1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
37 /* Check assumptions made in this file. */
38 typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1];
39 typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1];
42 #define DBG(x) printf x
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug = -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr = FALSE;
86 int mips_flag_pdr = TRUE;
91 static char *mips_regmask_frag;
98 #define PIC_CALL_REG 25
106 #define ILLEGAL_REG (32)
108 #define AT mips_opts.at
110 extern int target_big_endian;
112 /* The name of the readonly data section. */
113 #define RDATA_SECTION_NAME ".rodata"
115 /* Ways in which an instruction can be "appended" to the output. */
117 /* Just add it normally. */
120 /* Add it normally and then add a nop. */
123 /* Turn an instruction with a delay slot into a "compact" version. */
126 /* Insert the instruction before the last one. */
130 /* Information about an instruction, including its format, operands
134 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
135 const struct mips_opcode *insn_mo;
137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
138 a copy of INSN_MO->match with the operands filled in. If we have
139 decided to use an extended MIPS16 instruction, this includes the
141 unsigned long insn_opcode;
143 /* The frag that contains the instruction. */
146 /* The offset into FRAG of the first instruction byte. */
149 /* The relocs associated with the instruction, if any. */
152 /* True if this entry cannot be moved from its current position. */
153 unsigned int fixed_p : 1;
155 /* True if this instruction occurred in a .set noreorder block. */
156 unsigned int noreorder_p : 1;
158 /* True for mips16 instructions that jump to an absolute address. */
159 unsigned int mips16_absolute_jump_p : 1;
161 /* True if this instruction is complete. */
162 unsigned int complete_p : 1;
164 /* True if this instruction is cleared from history by unconditional
166 unsigned int cleared_p : 1;
169 /* The ABI to use. */
180 /* MIPS ABI we are using for this output file. */
181 static enum mips_abi_level mips_abi = NO_ABI;
183 /* Whether or not we have code that can call pic code. */
184 int mips_abicalls = FALSE;
186 /* Whether or not we have code which can be put into a shared
188 static bfd_boolean mips_in_shared = TRUE;
190 /* This is the set of options which may be modified by the .set
191 pseudo-op. We use a struct so that .set push and .set pop are more
194 struct mips_set_options
196 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
197 if it has not been initialized. Changed by `.set mipsN', and the
198 -mipsN command line option, and the default CPU. */
200 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
201 <asename>', by command line options, and based on the default
204 /* Whether we are assembling for the mips16 processor. 0 if we are
205 not, 1 if we are, and -1 if the value has not been initialized.
206 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
207 -nomips16 command line options, and the default CPU. */
209 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
210 1 if we are, and -1 if the value has not been initialized. Changed
211 by `.set micromips' and `.set nomicromips', and the -mmicromips
212 and -mno-micromips command line options, and the default CPU. */
214 /* Non-zero if we should not reorder instructions. Changed by `.set
215 reorder' and `.set noreorder'. */
217 /* Non-zero if we should not permit the register designated "assembler
218 temporary" to be used in instructions. The value is the register
219 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
220 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
222 /* Non-zero if we should warn when a macro instruction expands into
223 more than one machine instruction. Changed by `.set nomacro' and
225 int warn_about_macros;
226 /* Non-zero if we should not move instructions. Changed by `.set
227 move', `.set volatile', `.set nomove', and `.set novolatile'. */
229 /* Non-zero if we should not optimize branches by moving the target
230 of the branch into the delay slot. Actually, we don't perform
231 this optimization anyhow. Changed by `.set bopt' and `.set
234 /* Non-zero if we should not autoextend mips16 instructions.
235 Changed by `.set autoextend' and `.set noautoextend'. */
237 /* True if we should only emit 32-bit microMIPS instructions.
238 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
239 and -mno-insn32 command line options. */
241 /* Restrict general purpose registers and floating point registers
242 to 32 bit. This is initially determined when -mgp32 or -mfp32
243 is passed but can changed if the assembler code uses .set mipsN. */
246 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
247 command line option, and the default CPU. */
249 /* True if ".set sym32" is in effect. */
251 /* True if floating-point operations are not allowed. Changed by .set
252 softfloat or .set hardfloat, by command line options -msoft-float or
253 -mhard-float. The default is false. */
254 bfd_boolean soft_float;
256 /* True if only single-precision floating-point operations are allowed.
257 Changed by .set singlefloat or .set doublefloat, command-line options
258 -msingle-float or -mdouble-float. The default is false. */
259 bfd_boolean single_float;
262 /* This is the struct we use to hold the current set of options. Note
263 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
264 -1 to indicate that they have not been initialized. */
266 /* True if -mgp32 was passed. */
267 static int file_mips_gp32 = -1;
269 /* True if -mfp32 was passed. */
270 static int file_mips_fp32 = -1;
272 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
273 static int file_mips_soft_float = 0;
275 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
276 static int file_mips_single_float = 0;
278 /* True if -mnan=2008, false if -mnan=legacy. */
279 static bfd_boolean mips_flag_nan2008 = FALSE;
281 static struct mips_set_options mips_opts =
283 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
284 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
285 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
286 /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
287 /* soft_float */ FALSE, /* single_float */ FALSE
290 /* The set of ASEs that were selected on the command line, either
291 explicitly via ASE options or implicitly through things like -march. */
292 static unsigned int file_ase;
294 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
295 static unsigned int file_ase_explicit;
297 /* These variables are filled in with the masks of registers used.
298 The object format code reads them and puts them in the appropriate
300 unsigned long mips_gprmask;
301 unsigned long mips_cprmask[4];
303 /* MIPS ISA we are using for this output file. */
304 static int file_mips_isa = ISA_UNKNOWN;
306 /* True if any MIPS16 code was produced. */
307 static int file_ase_mips16;
309 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
310 || mips_opts.isa == ISA_MIPS32R2 \
311 || mips_opts.isa == ISA_MIPS64 \
312 || mips_opts.isa == ISA_MIPS64R2)
314 /* True if any microMIPS code was produced. */
315 static int file_ase_micromips;
317 /* True if we want to create R_MIPS_JALR for jalr $25. */
319 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
321 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
322 because there's no place for any addend, the only acceptable
323 expression is a bare symbol. */
324 #define MIPS_JALR_HINT_P(EXPR) \
325 (!HAVE_IN_PLACE_ADDENDS \
326 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
329 /* The argument of the -march= flag. The architecture we are assembling. */
330 static int file_mips_arch = CPU_UNKNOWN;
331 static const char *mips_arch_string;
333 /* The argument of the -mtune= flag. The architecture for which we
335 static int mips_tune = CPU_UNKNOWN;
336 static const char *mips_tune_string;
338 /* True when generating 32-bit code for a 64-bit processor. */
339 static int mips_32bitmode = 0;
341 /* True if the given ABI requires 32-bit registers. */
342 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
344 /* Likewise 64-bit registers. */
345 #define ABI_NEEDS_64BIT_REGS(ABI) \
347 || (ABI) == N64_ABI \
350 /* Return true if ISA supports 64 bit wide gp registers. */
351 #define ISA_HAS_64BIT_REGS(ISA) \
352 ((ISA) == ISA_MIPS3 \
353 || (ISA) == ISA_MIPS4 \
354 || (ISA) == ISA_MIPS5 \
355 || (ISA) == ISA_MIPS64 \
356 || (ISA) == ISA_MIPS64R2)
358 /* Return true if ISA supports 64 bit wide float registers. */
359 #define ISA_HAS_64BIT_FPRS(ISA) \
360 ((ISA) == ISA_MIPS3 \
361 || (ISA) == ISA_MIPS4 \
362 || (ISA) == ISA_MIPS5 \
363 || (ISA) == ISA_MIPS32R2 \
364 || (ISA) == ISA_MIPS64 \
365 || (ISA) == ISA_MIPS64R2)
367 /* Return true if ISA supports 64-bit right rotate (dror et al.)
369 #define ISA_HAS_DROR(ISA) \
370 ((ISA) == ISA_MIPS64R2 \
371 || (mips_opts.micromips \
372 && ISA_HAS_64BIT_REGS (ISA)) \
375 /* Return true if ISA supports 32-bit right rotate (ror et al.)
377 #define ISA_HAS_ROR(ISA) \
378 ((ISA) == ISA_MIPS32R2 \
379 || (ISA) == ISA_MIPS64R2 \
380 || (mips_opts.ase & ASE_SMARTMIPS) \
381 || mips_opts.micromips \
384 /* Return true if ISA supports single-precision floats in odd registers. */
385 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
386 ((ISA) == ISA_MIPS32 \
387 || (ISA) == ISA_MIPS32R2 \
388 || (ISA) == ISA_MIPS64 \
389 || (ISA) == ISA_MIPS64R2)
391 /* Return true if ISA supports move to/from high part of a 64-bit
392 floating-point register. */
393 #define ISA_HAS_MXHC1(ISA) \
394 ((ISA) == ISA_MIPS32R2 \
395 || (ISA) == ISA_MIPS64R2)
397 #define HAVE_32BIT_GPRS \
398 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
400 #define HAVE_32BIT_FPRS \
401 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
403 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
404 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
406 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
408 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
410 /* True if relocations are stored in-place. */
411 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
413 /* The ABI-derived address size. */
414 #define HAVE_64BIT_ADDRESSES \
415 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
416 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
418 /* The size of symbolic constants (i.e., expressions of the form
419 "SYMBOL" or "SYMBOL + OFFSET"). */
420 #define HAVE_32BIT_SYMBOLS \
421 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
422 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
424 /* Addresses are loaded in different ways, depending on the address size
425 in use. The n32 ABI Documentation also mandates the use of additions
426 with overflow checking, but existing implementations don't follow it. */
427 #define ADDRESS_ADD_INSN \
428 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
430 #define ADDRESS_ADDI_INSN \
431 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
433 #define ADDRESS_LOAD_INSN \
434 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
436 #define ADDRESS_STORE_INSN \
437 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
439 /* Return true if the given CPU supports the MIPS16 ASE. */
440 #define CPU_HAS_MIPS16(cpu) \
441 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
442 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
444 /* Return true if the given CPU supports the microMIPS ASE. */
445 #define CPU_HAS_MICROMIPS(cpu) 0
447 /* True if CPU has a dror instruction. */
448 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
450 /* True if CPU has a ror instruction. */
451 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
453 /* True if CPU is in the Octeon family */
454 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
456 /* True if CPU has seq/sne and seqi/snei instructions. */
457 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
459 /* True, if CPU has support for ldc1 and sdc1. */
460 #define CPU_HAS_LDC1_SDC1(CPU) \
461 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
463 /* True if mflo and mfhi can be immediately followed by instructions
464 which write to the HI and LO registers.
466 According to MIPS specifications, MIPS ISAs I, II, and III need
467 (at least) two instructions between the reads of HI/LO and
468 instructions which write them, and later ISAs do not. Contradicting
469 the MIPS specifications, some MIPS IV processor user manuals (e.g.
470 the UM for the NEC Vr5000) document needing the instructions between
471 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
472 MIPS64 and later ISAs to have the interlocks, plus any specific
473 earlier-ISA CPUs for which CPU documentation declares that the
474 instructions are really interlocked. */
475 #define hilo_interlocks \
476 (mips_opts.isa == ISA_MIPS32 \
477 || mips_opts.isa == ISA_MIPS32R2 \
478 || mips_opts.isa == ISA_MIPS64 \
479 || mips_opts.isa == ISA_MIPS64R2 \
480 || mips_opts.arch == CPU_R4010 \
481 || mips_opts.arch == CPU_R5900 \
482 || mips_opts.arch == CPU_R10000 \
483 || mips_opts.arch == CPU_R12000 \
484 || mips_opts.arch == CPU_R14000 \
485 || mips_opts.arch == CPU_R16000 \
486 || mips_opts.arch == CPU_RM7000 \
487 || mips_opts.arch == CPU_VR5500 \
488 || mips_opts.micromips \
491 /* Whether the processor uses hardware interlocks to protect reads
492 from the GPRs after they are loaded from memory, and thus does not
493 require nops to be inserted. This applies to instructions marked
494 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
495 level I and microMIPS mode instructions are always interlocked. */
496 #define gpr_interlocks \
497 (mips_opts.isa != ISA_MIPS1 \
498 || mips_opts.arch == CPU_R3900 \
499 || mips_opts.arch == CPU_R5900 \
500 || mips_opts.micromips \
503 /* Whether the processor uses hardware interlocks to avoid delays
504 required by coprocessor instructions, and thus does not require
505 nops to be inserted. This applies to instructions marked
506 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
507 between instructions marked INSN_WRITE_COND_CODE and ones marked
508 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
509 levels I, II, and III and microMIPS mode instructions are always
511 /* Itbl support may require additional care here. */
512 #define cop_interlocks \
513 ((mips_opts.isa != ISA_MIPS1 \
514 && mips_opts.isa != ISA_MIPS2 \
515 && mips_opts.isa != ISA_MIPS3) \
516 || mips_opts.arch == CPU_R4300 \
517 || mips_opts.micromips \
520 /* Whether the processor uses hardware interlocks to protect reads
521 from coprocessor registers after they are loaded from memory, and
522 thus does not require nops to be inserted. This applies to
523 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
524 requires at MIPS ISA level I and microMIPS mode instructions are
525 always interlocked. */
526 #define cop_mem_interlocks \
527 (mips_opts.isa != ISA_MIPS1 \
528 || mips_opts.micromips \
531 /* Is this a mfhi or mflo instruction? */
532 #define MF_HILO_INSN(PINFO) \
533 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
535 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
536 has been selected. This implies, in particular, that addresses of text
537 labels have their LSB set. */
538 #define HAVE_CODE_COMPRESSION \
539 ((mips_opts.mips16 | mips_opts.micromips) != 0)
541 /* The minimum and maximum signed values that can be stored in a GPR. */
542 #define GPR_SMAX ((offsetT) (((valueT) 1 << (HAVE_64BIT_GPRS ? 63 : 31)) - 1))
543 #define GPR_SMIN (-GPR_SMAX - 1)
545 /* MIPS PIC level. */
547 enum mips_pic_level mips_pic;
549 /* 1 if we should generate 32 bit offsets from the $gp register in
550 SVR4_PIC mode. Currently has no meaning in other modes. */
551 static int mips_big_got = 0;
553 /* 1 if trap instructions should used for overflow rather than break
555 static int mips_trap = 0;
557 /* 1 if double width floating point constants should not be constructed
558 by assembling two single width halves into two single width floating
559 point registers which just happen to alias the double width destination
560 register. On some architectures this aliasing can be disabled by a bit
561 in the status register, and the setting of this bit cannot be determined
562 automatically at assemble time. */
563 static int mips_disable_float_construction;
565 /* Non-zero if any .set noreorder directives were used. */
567 static int mips_any_noreorder;
569 /* Non-zero if nops should be inserted when the register referenced in
570 an mfhi/mflo instruction is read in the next two instructions. */
571 static int mips_7000_hilo_fix;
573 /* The size of objects in the small data section. */
574 static unsigned int g_switch_value = 8;
575 /* Whether the -G option was used. */
576 static int g_switch_seen = 0;
581 /* If we can determine in advance that GP optimization won't be
582 possible, we can skip the relaxation stuff that tries to produce
583 GP-relative references. This makes delay slot optimization work
586 This function can only provide a guess, but it seems to work for
587 gcc output. It needs to guess right for gcc, otherwise gcc
588 will put what it thinks is a GP-relative instruction in a branch
591 I don't know if a fix is needed for the SVR4_PIC mode. I've only
592 fixed it for the non-PIC mode. KR 95/04/07 */
593 static int nopic_need_relax (symbolS *, int);
595 /* handle of the OPCODE hash table */
596 static struct hash_control *op_hash = NULL;
598 /* The opcode hash table we use for the mips16. */
599 static struct hash_control *mips16_op_hash = NULL;
601 /* The opcode hash table we use for the microMIPS ASE. */
602 static struct hash_control *micromips_op_hash = NULL;
604 /* This array holds the chars that always start a comment. If the
605 pre-processor is disabled, these aren't very useful */
606 const char comment_chars[] = "#";
608 /* This array holds the chars that only start a comment at the beginning of
609 a line. If the line seems to have the form '# 123 filename'
610 .line and .file directives will appear in the pre-processed output */
611 /* Note that input_file.c hand checks for '#' at the beginning of the
612 first line of the input file. This is because the compiler outputs
613 #NO_APP at the beginning of its output. */
614 /* Also note that C style comments are always supported. */
615 const char line_comment_chars[] = "#";
617 /* This array holds machine specific line separator characters. */
618 const char line_separator_chars[] = ";";
620 /* Chars that can be used to separate mant from exp in floating point nums */
621 const char EXP_CHARS[] = "eE";
623 /* Chars that mean this number is a floating point constant */
626 const char FLT_CHARS[] = "rRsSfFdDxXpP";
628 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
629 changed in read.c . Ideally it shouldn't have to know about it at all,
630 but nothing is ideal around here.
633 static char *insn_error;
635 static int auto_align = 1;
637 /* When outputting SVR4 PIC code, the assembler needs to know the
638 offset in the stack frame from which to restore the $gp register.
639 This is set by the .cprestore pseudo-op, and saved in this
641 static offsetT mips_cprestore_offset = -1;
643 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
644 more optimizations, it can use a register value instead of a memory-saved
645 offset and even an other register than $gp as global pointer. */
646 static offsetT mips_cpreturn_offset = -1;
647 static int mips_cpreturn_register = -1;
648 static int mips_gp_register = GP;
649 static int mips_gprel_offset = 0;
651 /* Whether mips_cprestore_offset has been set in the current function
652 (or whether it has already been warned about, if not). */
653 static int mips_cprestore_valid = 0;
655 /* This is the register which holds the stack frame, as set by the
656 .frame pseudo-op. This is needed to implement .cprestore. */
657 static int mips_frame_reg = SP;
659 /* Whether mips_frame_reg has been set in the current function
660 (or whether it has already been warned about, if not). */
661 static int mips_frame_reg_valid = 0;
663 /* To output NOP instructions correctly, we need to keep information
664 about the previous two instructions. */
666 /* Whether we are optimizing. The default value of 2 means to remove
667 unneeded NOPs and swap branch instructions when possible. A value
668 of 1 means to not swap branches. A value of 0 means to always
670 static int mips_optimize = 2;
672 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
673 equivalent to seeing no -g option at all. */
674 static int mips_debug = 0;
676 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
677 #define MAX_VR4130_NOPS 4
679 /* The maximum number of NOPs needed to fill delay slots. */
680 #define MAX_DELAY_NOPS 2
682 /* The maximum number of NOPs needed for any purpose. */
685 /* A list of previous instructions, with index 0 being the most recent.
686 We need to look back MAX_NOPS instructions when filling delay slots
687 or working around processor errata. We need to look back one
688 instruction further if we're thinking about using history[0] to
689 fill a branch delay slot. */
690 static struct mips_cl_insn history[1 + MAX_NOPS];
692 /* Nop instructions used by emit_nop. */
693 static struct mips_cl_insn nop_insn;
694 static struct mips_cl_insn mips16_nop_insn;
695 static struct mips_cl_insn micromips_nop16_insn;
696 static struct mips_cl_insn micromips_nop32_insn;
698 /* The appropriate nop for the current mode. */
699 #define NOP_INSN (mips_opts.mips16 \
701 : (mips_opts.micromips \
702 ? (mips_opts.insn32 \
703 ? µmips_nop32_insn \
704 : µmips_nop16_insn) \
707 /* The size of NOP_INSN in bytes. */
708 #define NOP_INSN_SIZE ((mips_opts.mips16 \
709 || (mips_opts.micromips && !mips_opts.insn32)) \
712 /* If this is set, it points to a frag holding nop instructions which
713 were inserted before the start of a noreorder section. If those
714 nops turn out to be unnecessary, the size of the frag can be
716 static fragS *prev_nop_frag;
718 /* The number of nop instructions we created in prev_nop_frag. */
719 static int prev_nop_frag_holds;
721 /* The number of nop instructions that we know we need in
723 static int prev_nop_frag_required;
725 /* The number of instructions we've seen since prev_nop_frag. */
726 static int prev_nop_frag_since;
728 /* Relocations against symbols are sometimes done in two parts, with a HI
729 relocation and a LO relocation. Each relocation has only 16 bits of
730 space to store an addend. This means that in order for the linker to
731 handle carries correctly, it must be able to locate both the HI and
732 the LO relocation. This means that the relocations must appear in
733 order in the relocation table.
735 In order to implement this, we keep track of each unmatched HI
736 relocation. We then sort them so that they immediately precede the
737 corresponding LO relocation. */
742 struct mips_hi_fixup *next;
745 /* The section this fixup is in. */
749 /* The list of unmatched HI relocs. */
751 static struct mips_hi_fixup *mips_hi_fixup_list;
753 /* The frag containing the last explicit relocation operator.
754 Null if explicit relocations have not been used. */
756 static fragS *prev_reloc_op_frag;
758 /* Map mips16 register numbers to normal MIPS register numbers. */
760 static const unsigned int mips16_to_32_reg_map[] =
762 16, 17, 2, 3, 4, 5, 6, 7
765 /* Map microMIPS register numbers to normal MIPS register numbers. */
767 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
768 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
769 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
770 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
771 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
772 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
774 /* The microMIPS registers with type h. */
775 static const unsigned int micromips_to_32_reg_h_map1[] =
777 5, 5, 6, 4, 4, 4, 4, 4
779 static const unsigned int micromips_to_32_reg_h_map2[] =
781 6, 7, 7, 21, 22, 5, 6, 7
784 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
786 /* The microMIPS registers with type m. */
787 static const unsigned int micromips_to_32_reg_m_map[] =
789 0, 17, 2, 3, 16, 18, 19, 20
792 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
794 /* The microMIPS registers with type q. */
795 static const unsigned int micromips_to_32_reg_q_map[] =
797 0, 17, 2, 3, 4, 5, 6, 7
800 /* Classifies the kind of instructions we're interested in when
801 implementing -mfix-vr4120. */
802 enum fix_vr4120_class
810 NUM_FIX_VR4120_CLASSES
813 /* ...likewise -mfix-loongson2f-jump. */
814 static bfd_boolean mips_fix_loongson2f_jump;
816 /* ...likewise -mfix-loongson2f-nop. */
817 static bfd_boolean mips_fix_loongson2f_nop;
819 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
820 static bfd_boolean mips_fix_loongson2f;
822 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
823 there must be at least one other instruction between an instruction
824 of type X and an instruction of type Y. */
825 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
827 /* True if -mfix-vr4120 is in force. */
828 static int mips_fix_vr4120;
830 /* ...likewise -mfix-vr4130. */
831 static int mips_fix_vr4130;
833 /* ...likewise -mfix-24k. */
834 static int mips_fix_24k;
836 /* ...likewise -mfix-cn63xxp1 */
837 static bfd_boolean mips_fix_cn63xxp1;
839 /* We don't relax branches by default, since this causes us to expand
840 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
841 fail to compute the offset before expanding the macro to the most
842 efficient expansion. */
844 static int mips_relax_branch;
846 /* The expansion of many macros depends on the type of symbol that
847 they refer to. For example, when generating position-dependent code,
848 a macro that refers to a symbol may have two different expansions,
849 one which uses GP-relative addresses and one which uses absolute
850 addresses. When generating SVR4-style PIC, a macro may have
851 different expansions for local and global symbols.
853 We handle these situations by generating both sequences and putting
854 them in variant frags. In position-dependent code, the first sequence
855 will be the GP-relative one and the second sequence will be the
856 absolute one. In SVR4 PIC, the first sequence will be for global
857 symbols and the second will be for local symbols.
859 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
860 SECOND are the lengths of the two sequences in bytes. These fields
861 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
862 the subtype has the following flags:
865 Set if it has been decided that we should use the second
866 sequence instead of the first.
869 Set in the first variant frag if the macro's second implementation
870 is longer than its first. This refers to the macro as a whole,
871 not an individual relaxation.
874 Set in the first variant frag if the macro appeared in a .set nomacro
875 block and if one alternative requires a warning but the other does not.
878 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
881 RELAX_DELAY_SLOT_16BIT
882 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
885 RELAX_DELAY_SLOT_SIZE_FIRST
886 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
887 the macro is of the wrong size for the branch delay slot.
889 RELAX_DELAY_SLOT_SIZE_SECOND
890 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
891 the macro is of the wrong size for the branch delay slot.
893 The frag's "opcode" points to the first fixup for relaxable code.
895 Relaxable macros are generated using a sequence such as:
897 relax_start (SYMBOL);
898 ... generate first expansion ...
900 ... generate second expansion ...
903 The code and fixups for the unwanted alternative are discarded
904 by md_convert_frag. */
905 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
907 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
908 #define RELAX_SECOND(X) ((X) & 0xff)
909 #define RELAX_USE_SECOND 0x10000
910 #define RELAX_SECOND_LONGER 0x20000
911 #define RELAX_NOMACRO 0x40000
912 #define RELAX_DELAY_SLOT 0x80000
913 #define RELAX_DELAY_SLOT_16BIT 0x100000
914 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
915 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
917 /* Branch without likely bit. If label is out of range, we turn:
919 beq reg1, reg2, label
929 with the following opcode replacements:
936 bltzal <-> bgezal (with jal label instead of j label)
938 Even though keeping the delay slot instruction in the delay slot of
939 the branch would be more efficient, it would be very tricky to do
940 correctly, because we'd have to introduce a variable frag *after*
941 the delay slot instruction, and expand that instead. Let's do it
942 the easy way for now, even if the branch-not-taken case now costs
943 one additional instruction. Out-of-range branches are not supposed
944 to be common, anyway.
946 Branch likely. If label is out of range, we turn:
948 beql reg1, reg2, label
949 delay slot (annulled if branch not taken)
958 delay slot (executed only if branch taken)
961 It would be possible to generate a shorter sequence by losing the
962 likely bit, generating something like:
967 delay slot (executed only if branch taken)
979 bltzall -> bgezal (with jal label instead of j label)
980 bgezall -> bltzal (ditto)
983 but it's not clear that it would actually improve performance. */
984 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
988 | ((toofar) ? 0x20 : 0) \
989 | ((link) ? 0x40 : 0) \
990 | ((likely) ? 0x80 : 0) \
991 | ((uncond) ? 0x100 : 0)))
992 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
993 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
994 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
995 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
996 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
997 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
999 /* For mips16 code, we use an entirely different form of relaxation.
1000 mips16 supports two versions of most instructions which take
1001 immediate values: a small one which takes some small value, and a
1002 larger one which takes a 16 bit value. Since branches also follow
1003 this pattern, relaxing these values is required.
1005 We can assemble both mips16 and normal MIPS code in a single
1006 object. Therefore, we need to support this type of relaxation at
1007 the same time that we support the relaxation described above. We
1008 use the high bit of the subtype field to distinguish these cases.
1010 The information we store for this type of relaxation is the
1011 argument code found in the opcode file for this relocation, whether
1012 the user explicitly requested a small or extended form, and whether
1013 the relocation is in a jump or jal delay slot. That tells us the
1014 size of the value, and how it should be stored. We also store
1015 whether the fragment is considered to be extended or not. We also
1016 store whether this is known to be a branch to a different section,
1017 whether we have tried to relax this frag yet, and whether we have
1018 ever extended a PC relative fragment because of a shift count. */
1019 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1022 | ((small) ? 0x100 : 0) \
1023 | ((ext) ? 0x200 : 0) \
1024 | ((dslot) ? 0x400 : 0) \
1025 | ((jal_dslot) ? 0x800 : 0))
1026 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1027 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1028 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1029 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1030 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1031 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1032 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1033 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1034 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1035 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1036 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1037 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1039 /* For microMIPS code, we use relaxation similar to one we use for
1040 MIPS16 code. Some instructions that take immediate values support
1041 two encodings: a small one which takes some small value, and a
1042 larger one which takes a 16 bit value. As some branches also follow
1043 this pattern, relaxing these values is required.
1045 We can assemble both microMIPS and normal MIPS code in a single
1046 object. Therefore, we need to support this type of relaxation at
1047 the same time that we support the relaxation described above. We
1048 use one of the high bits of the subtype field to distinguish these
1051 The information we store for this type of relaxation is the argument
1052 code found in the opcode file for this relocation, the register
1053 selected as the assembler temporary, whether the branch is
1054 unconditional, whether it is compact, whether it stores the link
1055 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1056 branches to a sequence of instructions is enabled, and whether the
1057 displacement of a branch is too large to fit as an immediate argument
1058 of a 16-bit and a 32-bit branch, respectively. */
1059 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1060 relax32, toofar16, toofar32) \
1063 | (((at) & 0x1f) << 8) \
1064 | ((uncond) ? 0x2000 : 0) \
1065 | ((compact) ? 0x4000 : 0) \
1066 | ((link) ? 0x8000 : 0) \
1067 | ((relax32) ? 0x10000 : 0) \
1068 | ((toofar16) ? 0x20000 : 0) \
1069 | ((toofar32) ? 0x40000 : 0))
1070 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1071 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1072 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1073 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1074 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1075 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1076 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1078 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1079 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1080 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1081 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1082 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1083 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1085 /* Sign-extend 16-bit value X. */
1086 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1088 /* Is the given value a sign-extended 32-bit value? */
1089 #define IS_SEXT_32BIT_NUM(x) \
1090 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1091 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1093 /* Is the given value a sign-extended 16-bit value? */
1094 #define IS_SEXT_16BIT_NUM(x) \
1095 (((x) &~ (offsetT) 0x7fff) == 0 \
1096 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1098 /* Is the given value a sign-extended 12-bit value? */
1099 #define IS_SEXT_12BIT_NUM(x) \
1100 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1102 /* Is the given value a sign-extended 9-bit value? */
1103 #define IS_SEXT_9BIT_NUM(x) \
1104 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1106 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1107 #define IS_ZEXT_32BIT_NUM(x) \
1108 (((x) &~ (offsetT) 0xffffffff) == 0 \
1109 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1111 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1113 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1114 (((STRUCT) >> (SHIFT)) & (MASK))
1116 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1117 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1119 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1120 : EXTRACT_BITS ((INSN).insn_opcode, \
1121 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1122 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1123 EXTRACT_BITS ((INSN).insn_opcode, \
1124 MIPS16OP_MASK_##FIELD, \
1125 MIPS16OP_SH_##FIELD)
1127 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1128 #define MIPS16_EXTEND (0xf000U << 16)
1130 /* Whether or not we are emitting a branch-likely macro. */
1131 static bfd_boolean emit_branch_likely_macro = FALSE;
1133 /* Global variables used when generating relaxable macros. See the
1134 comment above RELAX_ENCODE for more details about how relaxation
1137 /* 0 if we're not emitting a relaxable macro.
1138 1 if we're emitting the first of the two relaxation alternatives.
1139 2 if we're emitting the second alternative. */
1142 /* The first relaxable fixup in the current frag. (In other words,
1143 the first fixup that refers to relaxable code.) */
1146 /* sizes[0] says how many bytes of the first alternative are stored in
1147 the current frag. Likewise sizes[1] for the second alternative. */
1148 unsigned int sizes[2];
1150 /* The symbol on which the choice of sequence depends. */
1154 /* Global variables used to decide whether a macro needs a warning. */
1156 /* True if the macro is in a branch delay slot. */
1157 bfd_boolean delay_slot_p;
1159 /* Set to the length in bytes required if the macro is in a delay slot
1160 that requires a specific length of instruction, otherwise zero. */
1161 unsigned int delay_slot_length;
1163 /* For relaxable macros, sizes[0] is the length of the first alternative
1164 in bytes and sizes[1] is the length of the second alternative.
1165 For non-relaxable macros, both elements give the length of the
1167 unsigned int sizes[2];
1169 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1170 instruction of the first alternative in bytes and first_insn_sizes[1]
1171 is the length of the first instruction of the second alternative.
1172 For non-relaxable macros, both elements give the length of the first
1173 instruction in bytes.
1175 Set to zero if we haven't yet seen the first instruction. */
1176 unsigned int first_insn_sizes[2];
1178 /* For relaxable macros, insns[0] is the number of instructions for the
1179 first alternative and insns[1] is the number of instructions for the
1182 For non-relaxable macros, both elements give the number of
1183 instructions for the macro. */
1184 unsigned int insns[2];
1186 /* The first variant frag for this macro. */
1188 } mips_macro_warning;
1190 /* Prototypes for static functions. */
1192 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1194 static void append_insn
1195 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1196 bfd_boolean expansionp);
1197 static void mips_no_prev_insn (void);
1198 static void macro_build (expressionS *, const char *, const char *, ...);
1199 static void mips16_macro_build
1200 (expressionS *, const char *, const char *, va_list *);
1201 static void load_register (int, expressionS *, int);
1202 static void macro_start (void);
1203 static void macro_end (void);
1204 static void macro (struct mips_cl_insn *ip, char *str);
1205 static void mips16_macro (struct mips_cl_insn * ip);
1206 static void mips_ip (char *str, struct mips_cl_insn * ip);
1207 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1208 static void mips16_immed
1209 (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT,
1210 unsigned int, unsigned long *);
1211 static size_t my_getSmallExpression
1212 (expressionS *, bfd_reloc_code_real_type *, char *);
1213 static void my_getExpression (expressionS *, char *);
1214 static void s_align (int);
1215 static void s_change_sec (int);
1216 static void s_change_section (int);
1217 static void s_cons (int);
1218 static void s_float_cons (int);
1219 static void s_mips_globl (int);
1220 static void s_option (int);
1221 static void s_mipsset (int);
1222 static void s_abicalls (int);
1223 static void s_cpload (int);
1224 static void s_cpsetup (int);
1225 static void s_cplocal (int);
1226 static void s_cprestore (int);
1227 static void s_cpreturn (int);
1228 static void s_dtprelword (int);
1229 static void s_dtpreldword (int);
1230 static void s_tprelword (int);
1231 static void s_tpreldword (int);
1232 static void s_gpvalue (int);
1233 static void s_gpword (int);
1234 static void s_gpdword (int);
1235 static void s_ehword (int);
1236 static void s_cpadd (int);
1237 static void s_insn (int);
1238 static void s_nan (int);
1239 static void md_obj_begin (void);
1240 static void md_obj_end (void);
1241 static void s_mips_ent (int);
1242 static void s_mips_end (int);
1243 static void s_mips_frame (int);
1244 static void s_mips_mask (int reg_type);
1245 static void s_mips_stab (int);
1246 static void s_mips_weakext (int);
1247 static void s_mips_file (int);
1248 static void s_mips_loc (int);
1249 static bfd_boolean pic_need_relax (symbolS *, asection *);
1250 static int relaxed_branch_length (fragS *, asection *, int);
1251 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1252 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1254 /* Table and functions used to map between CPU/ISA names, and
1255 ISA levels, and CPU numbers. */
1257 struct mips_cpu_info
1259 const char *name; /* CPU or ISA name. */
1260 int flags; /* MIPS_CPU_* flags. */
1261 int ase; /* Set of ASEs implemented by the CPU. */
1262 int isa; /* ISA level. */
1263 int cpu; /* CPU number (default CPU if ISA). */
1266 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1268 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1269 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1270 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1272 /* Command-line options. */
1273 const char *md_shortopts = "O::g::G:";
1277 OPTION_MARCH = OPTION_MD_BASE,
1301 OPTION_NO_SMARTMIPS,
1307 OPTION_NO_MICROMIPS,
1310 OPTION_COMPAT_ARCH_BASE,
1319 OPTION_M7000_HILO_FIX,
1320 OPTION_MNO_7000_HILO_FIX,
1323 OPTION_FIX_LOONGSON2F_JUMP,
1324 OPTION_NO_FIX_LOONGSON2F_JUMP,
1325 OPTION_FIX_LOONGSON2F_NOP,
1326 OPTION_NO_FIX_LOONGSON2F_NOP,
1328 OPTION_NO_FIX_VR4120,
1330 OPTION_NO_FIX_VR4130,
1331 OPTION_FIX_CN63XXP1,
1332 OPTION_NO_FIX_CN63XXP1,
1339 OPTION_CONSTRUCT_FLOATS,
1340 OPTION_NO_CONSTRUCT_FLOATS,
1343 OPTION_RELAX_BRANCH,
1344 OPTION_NO_RELAX_BRANCH,
1353 OPTION_SINGLE_FLOAT,
1354 OPTION_DOUBLE_FLOAT,
1367 OPTION_MVXWORKS_PIC,
1372 struct option md_longopts[] =
1374 /* Options which specify architecture. */
1375 {"march", required_argument, NULL, OPTION_MARCH},
1376 {"mtune", required_argument, NULL, OPTION_MTUNE},
1377 {"mips0", no_argument, NULL, OPTION_MIPS1},
1378 {"mips1", no_argument, NULL, OPTION_MIPS1},
1379 {"mips2", no_argument, NULL, OPTION_MIPS2},
1380 {"mips3", no_argument, NULL, OPTION_MIPS3},
1381 {"mips4", no_argument, NULL, OPTION_MIPS4},
1382 {"mips5", no_argument, NULL, OPTION_MIPS5},
1383 {"mips32", no_argument, NULL, OPTION_MIPS32},
1384 {"mips64", no_argument, NULL, OPTION_MIPS64},
1385 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
1386 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
1388 /* Options which specify Application Specific Extensions (ASEs). */
1389 {"mips16", no_argument, NULL, OPTION_MIPS16},
1390 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
1391 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
1392 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
1393 {"mdmx", no_argument, NULL, OPTION_MDMX},
1394 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
1395 {"mdsp", no_argument, NULL, OPTION_DSP},
1396 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
1397 {"mmt", no_argument, NULL, OPTION_MT},
1398 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
1399 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
1400 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
1401 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
1402 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
1403 {"meva", no_argument, NULL, OPTION_EVA},
1404 {"mno-eva", no_argument, NULL, OPTION_NO_EVA},
1405 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
1406 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
1407 {"mmcu", no_argument, NULL, OPTION_MCU},
1408 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
1409 {"mvirt", no_argument, NULL, OPTION_VIRT},
1410 {"mno-virt", no_argument, NULL, OPTION_NO_VIRT},
1412 /* Old-style architecture options. Don't add more of these. */
1413 {"m4650", no_argument, NULL, OPTION_M4650},
1414 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
1415 {"m4010", no_argument, NULL, OPTION_M4010},
1416 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
1417 {"m4100", no_argument, NULL, OPTION_M4100},
1418 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
1419 {"m3900", no_argument, NULL, OPTION_M3900},
1420 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
1422 /* Options which enable bug fixes. */
1423 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
1424 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1425 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1426 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
1427 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
1428 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
1429 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
1430 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
1431 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
1432 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
1433 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
1434 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
1435 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
1436 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
1437 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
1439 /* Miscellaneous options. */
1440 {"trap", no_argument, NULL, OPTION_TRAP},
1441 {"no-break", no_argument, NULL, OPTION_TRAP},
1442 {"break", no_argument, NULL, OPTION_BREAK},
1443 {"no-trap", no_argument, NULL, OPTION_BREAK},
1444 {"EB", no_argument, NULL, OPTION_EB},
1445 {"EL", no_argument, NULL, OPTION_EL},
1446 {"mfp32", no_argument, NULL, OPTION_FP32},
1447 {"mgp32", no_argument, NULL, OPTION_GP32},
1448 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
1449 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
1450 {"mfp64", no_argument, NULL, OPTION_FP64},
1451 {"mgp64", no_argument, NULL, OPTION_GP64},
1452 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
1453 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
1454 {"minsn32", no_argument, NULL, OPTION_INSN32},
1455 {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32},
1456 {"mshared", no_argument, NULL, OPTION_MSHARED},
1457 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
1458 {"msym32", no_argument, NULL, OPTION_MSYM32},
1459 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
1460 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
1461 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
1462 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
1463 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
1465 /* Strictly speaking this next option is ELF specific,
1466 but we allow it for other ports as well in order to
1467 make testing easier. */
1468 {"32", no_argument, NULL, OPTION_32},
1470 /* ELF-specific options. */
1471 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
1472 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
1473 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
1474 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
1475 {"xgot", no_argument, NULL, OPTION_XGOT},
1476 {"mabi", required_argument, NULL, OPTION_MABI},
1477 {"n32", no_argument, NULL, OPTION_N32},
1478 {"64", no_argument, NULL, OPTION_64},
1479 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
1480 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
1481 {"mpdr", no_argument, NULL, OPTION_PDR},
1482 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
1483 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
1484 {"mnan", required_argument, NULL, OPTION_NAN},
1486 {NULL, no_argument, NULL, 0}
1488 size_t md_longopts_size = sizeof (md_longopts);
1490 /* Information about either an Application Specific Extension or an
1491 optional architecture feature that, for simplicity, we treat in the
1492 same way as an ASE. */
1495 /* The name of the ASE, used in both the command-line and .set options. */
1498 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1499 and 64-bit architectures, the flags here refer to the subset that
1500 is available on both. */
1503 /* The ASE_* flag used for instructions that are available on 64-bit
1504 architectures but that are not included in FLAGS. */
1505 unsigned int flags64;
1507 /* The command-line options that turn the ASE on and off. */
1511 /* The minimum required architecture revisions for MIPS32, MIPS64,
1512 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1515 int micromips32_rev;
1516 int micromips64_rev;
1519 /* A table of all supported ASEs. */
1520 static const struct mips_ase mips_ases[] = {
1521 { "dsp", ASE_DSP, ASE_DSP64,
1522 OPTION_DSP, OPTION_NO_DSP,
1525 { "dspr2", ASE_DSP | ASE_DSPR2, 0,
1526 OPTION_DSPR2, OPTION_NO_DSPR2,
1529 { "eva", ASE_EVA, 0,
1530 OPTION_EVA, OPTION_NO_EVA,
1533 { "mcu", ASE_MCU, 0,
1534 OPTION_MCU, OPTION_NO_MCU,
1537 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1538 { "mdmx", ASE_MDMX, 0,
1539 OPTION_MDMX, OPTION_NO_MDMX,
1542 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1543 { "mips3d", ASE_MIPS3D, 0,
1544 OPTION_MIPS3D, OPTION_NO_MIPS3D,
1548 OPTION_MT, OPTION_NO_MT,
1551 { "smartmips", ASE_SMARTMIPS, 0,
1552 OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS,
1555 { "virt", ASE_VIRT, ASE_VIRT64,
1556 OPTION_VIRT, OPTION_NO_VIRT,
1560 /* The set of ASEs that require -mfp64. */
1561 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX)
1563 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1564 static const unsigned int mips_ase_groups[] = {
1570 The following pseudo-ops from the Kane and Heinrich MIPS book
1571 should be defined here, but are currently unsupported: .alias,
1572 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1574 The following pseudo-ops from the Kane and Heinrich MIPS book are
1575 specific to the type of debugging information being generated, and
1576 should be defined by the object format: .aent, .begin, .bend,
1577 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1580 The following pseudo-ops from the Kane and Heinrich MIPS book are
1581 not MIPS CPU specific, but are also not specific to the object file
1582 format. This file is probably the best place to define them, but
1583 they are not currently supported: .asm0, .endr, .lab, .struct. */
1585 static const pseudo_typeS mips_pseudo_table[] =
1587 /* MIPS specific pseudo-ops. */
1588 {"option", s_option, 0},
1589 {"set", s_mipsset, 0},
1590 {"rdata", s_change_sec, 'r'},
1591 {"sdata", s_change_sec, 's'},
1592 {"livereg", s_ignore, 0},
1593 {"abicalls", s_abicalls, 0},
1594 {"cpload", s_cpload, 0},
1595 {"cpsetup", s_cpsetup, 0},
1596 {"cplocal", s_cplocal, 0},
1597 {"cprestore", s_cprestore, 0},
1598 {"cpreturn", s_cpreturn, 0},
1599 {"dtprelword", s_dtprelword, 0},
1600 {"dtpreldword", s_dtpreldword, 0},
1601 {"tprelword", s_tprelword, 0},
1602 {"tpreldword", s_tpreldword, 0},
1603 {"gpvalue", s_gpvalue, 0},
1604 {"gpword", s_gpword, 0},
1605 {"gpdword", s_gpdword, 0},
1606 {"ehword", s_ehword, 0},
1607 {"cpadd", s_cpadd, 0},
1608 {"insn", s_insn, 0},
1611 /* Relatively generic pseudo-ops that happen to be used on MIPS
1613 {"asciiz", stringer, 8 + 1},
1614 {"bss", s_change_sec, 'b'},
1616 {"half", s_cons, 1},
1617 {"dword", s_cons, 3},
1618 {"weakext", s_mips_weakext, 0},
1619 {"origin", s_org, 0},
1620 {"repeat", s_rept, 0},
1622 /* For MIPS this is non-standard, but we define it for consistency. */
1623 {"sbss", s_change_sec, 'B'},
1625 /* These pseudo-ops are defined in read.c, but must be overridden
1626 here for one reason or another. */
1627 {"align", s_align, 0},
1628 {"byte", s_cons, 0},
1629 {"data", s_change_sec, 'd'},
1630 {"double", s_float_cons, 'd'},
1631 {"float", s_float_cons, 'f'},
1632 {"globl", s_mips_globl, 0},
1633 {"global", s_mips_globl, 0},
1634 {"hword", s_cons, 1},
1636 {"long", s_cons, 2},
1637 {"octa", s_cons, 4},
1638 {"quad", s_cons, 3},
1639 {"section", s_change_section, 0},
1640 {"short", s_cons, 1},
1641 {"single", s_float_cons, 'f'},
1642 {"stabd", s_mips_stab, 'd'},
1643 {"stabn", s_mips_stab, 'n'},
1644 {"stabs", s_mips_stab, 's'},
1645 {"text", s_change_sec, 't'},
1646 {"word", s_cons, 2},
1648 { "extern", ecoff_directive_extern, 0},
1653 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1655 /* These pseudo-ops should be defined by the object file format.
1656 However, a.out doesn't support them, so we have versions here. */
1657 {"aent", s_mips_ent, 1},
1658 {"bgnb", s_ignore, 0},
1659 {"end", s_mips_end, 0},
1660 {"endb", s_ignore, 0},
1661 {"ent", s_mips_ent, 0},
1662 {"file", s_mips_file, 0},
1663 {"fmask", s_mips_mask, 'F'},
1664 {"frame", s_mips_frame, 0},
1665 {"loc", s_mips_loc, 0},
1666 {"mask", s_mips_mask, 'R'},
1667 {"verstamp", s_ignore, 0},
1671 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1672 purpose of the `.dc.a' internal pseudo-op. */
1675 mips_address_bytes (void)
1677 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1680 extern void pop_insert (const pseudo_typeS *);
1683 mips_pop_insert (void)
1685 pop_insert (mips_pseudo_table);
1686 if (! ECOFF_DEBUGGING)
1687 pop_insert (mips_nonecoff_pseudo_table);
1690 /* Symbols labelling the current insn. */
1692 struct insn_label_list
1694 struct insn_label_list *next;
1698 static struct insn_label_list *free_insn_labels;
1699 #define label_list tc_segment_info_data.labels
1701 static void mips_clear_insn_labels (void);
1702 static void mips_mark_labels (void);
1703 static void mips_compressed_mark_labels (void);
1706 mips_clear_insn_labels (void)
1708 register struct insn_label_list **pl;
1709 segment_info_type *si;
1713 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1716 si = seg_info (now_seg);
1717 *pl = si->label_list;
1718 si->label_list = NULL;
1722 /* Mark instruction labels in MIPS16/microMIPS mode. */
1725 mips_mark_labels (void)
1727 if (HAVE_CODE_COMPRESSION)
1728 mips_compressed_mark_labels ();
1731 static char *expr_end;
1733 /* Expressions which appear in macro instructions. These are set by
1734 mips_ip and read by macro. */
1736 static expressionS imm_expr;
1737 static expressionS imm2_expr;
1739 /* The relocatable field in an instruction and the relocs associated
1740 with it. These variables are used for instructions like LUI and
1741 JAL as well as true offsets. They are also used for address
1742 operands in macros. */
1744 static expressionS offset_expr;
1745 static bfd_reloc_code_real_type offset_reloc[3]
1746 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1748 /* This is set to the resulting size of the instruction to be produced
1749 by mips16_ip if an explicit extension is used or by mips_ip if an
1750 explicit size is supplied. */
1752 static unsigned int forced_insn_length;
1754 /* True if we are assembling an instruction. All dot symbols defined during
1755 this time should be treated as code labels. */
1757 static bfd_boolean mips_assembling_insn;
1759 /* The pdr segment for per procedure frame/regmask info. Not used for
1762 static segT pdr_seg;
1764 /* The default target format to use. */
1766 #if defined (TE_FreeBSD)
1767 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1768 #elif defined (TE_TMIPS)
1769 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1771 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1775 mips_target_format (void)
1777 switch (OUTPUT_FLAVOR)
1779 case bfd_target_elf_flavour:
1781 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1782 return (target_big_endian
1783 ? "elf32-bigmips-vxworks"
1784 : "elf32-littlemips-vxworks");
1786 return (target_big_endian
1787 ? (HAVE_64BIT_OBJECTS
1788 ? ELF_TARGET ("elf64-", "big")
1790 ? ELF_TARGET ("elf32-n", "big")
1791 : ELF_TARGET ("elf32-", "big")))
1792 : (HAVE_64BIT_OBJECTS
1793 ? ELF_TARGET ("elf64-", "little")
1795 ? ELF_TARGET ("elf32-n", "little")
1796 : ELF_TARGET ("elf32-", "little"))));
1803 /* Return the ISA revision that is currently in use, or 0 if we are
1804 generating code for MIPS V or below. */
1809 if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2)
1812 /* microMIPS implies revision 2 or above. */
1813 if (mips_opts.micromips)
1816 if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64)
1822 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1825 mips_ase_mask (unsigned int flags)
1829 for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++)
1830 if (flags & mips_ase_groups[i])
1831 flags |= mips_ase_groups[i];
1835 /* Check whether the current ISA supports ASE. Issue a warning if
1839 mips_check_isa_supports_ase (const struct mips_ase *ase)
1843 static unsigned int warned_isa;
1844 static unsigned int warned_fp32;
1846 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
1847 min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev;
1849 min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev;
1850 if ((min_rev < 0 || mips_isa_rev () < min_rev)
1851 && (warned_isa & ase->flags) != ase->flags)
1853 warned_isa |= ase->flags;
1854 base = mips_opts.micromips ? "microMIPS" : "MIPS";
1855 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
1857 as_warn (_("The %d-bit %s architecture does not support the"
1858 " `%s' extension"), size, base, ase->name);
1860 as_warn (_("The `%s' extension requires %s%d revision %d or greater"),
1861 ase->name, base, size, min_rev);
1863 if ((ase->flags & FP64_ASES)
1865 && (warned_fp32 & ase->flags) != ase->flags)
1867 warned_fp32 |= ase->flags;
1868 as_warn (_("The `%s' extension requires 64-bit FPRs"), ase->name);
1872 /* Check all enabled ASEs to see whether they are supported by the
1873 chosen architecture. */
1876 mips_check_isa_supports_ases (void)
1878 unsigned int i, mask;
1880 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
1882 mask = mips_ase_mask (mips_ases[i].flags);
1883 if ((mips_opts.ase & mask) == mips_ases[i].flags)
1884 mips_check_isa_supports_ase (&mips_ases[i]);
1888 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
1889 that were affected. */
1892 mips_set_ase (const struct mips_ase *ase, bfd_boolean enabled_p)
1896 mask = mips_ase_mask (ase->flags);
1897 mips_opts.ase &= ~mask;
1899 mips_opts.ase |= ase->flags;
1903 /* Return the ASE called NAME, or null if none. */
1905 static const struct mips_ase *
1906 mips_lookup_ase (const char *name)
1910 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
1911 if (strcmp (name, mips_ases[i].name) == 0)
1912 return &mips_ases[i];
1916 /* Return the length of a microMIPS instruction in bytes. If bits of
1917 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1918 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1919 major opcode) will require further modifications to the opcode
1922 static inline unsigned int
1923 micromips_insn_length (const struct mips_opcode *mo)
1925 return (mo->mask >> 16) == 0 ? 2 : 4;
1928 /* Return the length of MIPS16 instruction OPCODE. */
1930 static inline unsigned int
1931 mips16_opcode_length (unsigned long opcode)
1933 return (opcode >> 16) == 0 ? 2 : 4;
1936 /* Return the length of instruction INSN. */
1938 static inline unsigned int
1939 insn_length (const struct mips_cl_insn *insn)
1941 if (mips_opts.micromips)
1942 return micromips_insn_length (insn->insn_mo);
1943 else if (mips_opts.mips16)
1944 return mips16_opcode_length (insn->insn_opcode);
1949 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1952 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1957 insn->insn_opcode = mo->match;
1960 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1961 insn->fixp[i] = NULL;
1962 insn->fixed_p = (mips_opts.noreorder > 0);
1963 insn->noreorder_p = (mips_opts.noreorder > 0);
1964 insn->mips16_absolute_jump_p = 0;
1965 insn->complete_p = 0;
1966 insn->cleared_p = 0;
1969 /* Install UVAL as the value of OPERAND in INSN. */
1972 insn_insert_operand (struct mips_cl_insn *insn,
1973 const struct mips_operand *operand, unsigned int uval)
1975 insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval);
1978 /* Record the current MIPS16/microMIPS mode in now_seg. */
1981 mips_record_compressed_mode (void)
1983 segment_info_type *si;
1985 si = seg_info (now_seg);
1986 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
1987 si->tc_segment_info_data.mips16 = mips_opts.mips16;
1988 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
1989 si->tc_segment_info_data.micromips = mips_opts.micromips;
1992 /* Read a standard MIPS instruction from BUF. */
1994 static unsigned long
1995 read_insn (char *buf)
1997 if (target_big_endian)
1998 return bfd_getb32 ((bfd_byte *) buf);
2000 return bfd_getl32 ((bfd_byte *) buf);
2003 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2007 write_insn (char *buf, unsigned int insn)
2009 md_number_to_chars (buf, insn, 4);
2013 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2014 has length LENGTH. */
2016 static unsigned long
2017 read_compressed_insn (char *buf, unsigned int length)
2023 for (i = 0; i < length; i += 2)
2026 if (target_big_endian)
2027 insn |= bfd_getb16 ((char *) buf);
2029 insn |= bfd_getl16 ((char *) buf);
2035 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2036 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2039 write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
2043 for (i = 0; i < length; i += 2)
2044 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
2045 return buf + length;
2048 /* Install INSN at the location specified by its "frag" and "where" fields. */
2051 install_insn (const struct mips_cl_insn *insn)
2053 char *f = insn->frag->fr_literal + insn->where;
2054 if (HAVE_CODE_COMPRESSION)
2055 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
2057 write_insn (f, insn->insn_opcode);
2058 mips_record_compressed_mode ();
2061 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2062 and install the opcode in the new location. */
2065 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
2070 insn->where = where;
2071 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2072 if (insn->fixp[i] != NULL)
2074 insn->fixp[i]->fx_frag = frag;
2075 insn->fixp[i]->fx_where = where;
2077 install_insn (insn);
2080 /* Add INSN to the end of the output. */
2083 add_fixed_insn (struct mips_cl_insn *insn)
2085 char *f = frag_more (insn_length (insn));
2086 move_insn (insn, frag_now, f - frag_now->fr_literal);
2089 /* Start a variant frag and move INSN to the start of the variant part,
2090 marking it as fixed. The other arguments are as for frag_var. */
2093 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
2094 relax_substateT subtype, symbolS *symbol, offsetT offset)
2096 frag_grow (max_chars);
2097 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
2099 frag_var (rs_machine_dependent, max_chars, var,
2100 subtype, symbol, offset, NULL);
2103 /* Insert N copies of INSN into the history buffer, starting at
2104 position FIRST. Neither FIRST nor N need to be clipped. */
2107 insert_into_history (unsigned int first, unsigned int n,
2108 const struct mips_cl_insn *insn)
2110 if (mips_relax.sequence != 2)
2114 for (i = ARRAY_SIZE (history); i-- > first;)
2116 history[i] = history[i - n];
2122 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2123 the idea is to make it obvious at a glance that each errata is
2127 init_vr4120_conflicts (void)
2129 #define CONFLICT(FIRST, SECOND) \
2130 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2132 /* Errata 21 - [D]DIV[U] after [D]MACC */
2133 CONFLICT (MACC, DIV);
2134 CONFLICT (DMACC, DIV);
2136 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2137 CONFLICT (DMULT, DMULT);
2138 CONFLICT (DMULT, DMACC);
2139 CONFLICT (DMACC, DMULT);
2140 CONFLICT (DMACC, DMACC);
2142 /* Errata 24 - MT{LO,HI} after [D]MACC */
2143 CONFLICT (MACC, MTHILO);
2144 CONFLICT (DMACC, MTHILO);
2146 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2147 instruction is executed immediately after a MACC or DMACC
2148 instruction, the result of [either instruction] is incorrect." */
2149 CONFLICT (MACC, MULT);
2150 CONFLICT (MACC, DMULT);
2151 CONFLICT (DMACC, MULT);
2152 CONFLICT (DMACC, DMULT);
2154 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2155 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2156 DDIV or DDIVU instruction, the result of the MACC or
2157 DMACC instruction is incorrect.". */
2158 CONFLICT (DMULT, MACC);
2159 CONFLICT (DMULT, DMACC);
2160 CONFLICT (DIV, MACC);
2161 CONFLICT (DIV, DMACC);
2171 #define RTYPE_MASK 0x1ff00
2172 #define RTYPE_NUM 0x00100
2173 #define RTYPE_FPU 0x00200
2174 #define RTYPE_FCC 0x00400
2175 #define RTYPE_VEC 0x00800
2176 #define RTYPE_GP 0x01000
2177 #define RTYPE_CP0 0x02000
2178 #define RTYPE_PC 0x04000
2179 #define RTYPE_ACC 0x08000
2180 #define RTYPE_CCC 0x10000
2181 #define RNUM_MASK 0x000ff
2182 #define RWARN 0x80000
2184 #define GENERIC_REGISTER_NUMBERS \
2185 {"$0", RTYPE_NUM | 0}, \
2186 {"$1", RTYPE_NUM | 1}, \
2187 {"$2", RTYPE_NUM | 2}, \
2188 {"$3", RTYPE_NUM | 3}, \
2189 {"$4", RTYPE_NUM | 4}, \
2190 {"$5", RTYPE_NUM | 5}, \
2191 {"$6", RTYPE_NUM | 6}, \
2192 {"$7", RTYPE_NUM | 7}, \
2193 {"$8", RTYPE_NUM | 8}, \
2194 {"$9", RTYPE_NUM | 9}, \
2195 {"$10", RTYPE_NUM | 10}, \
2196 {"$11", RTYPE_NUM | 11}, \
2197 {"$12", RTYPE_NUM | 12}, \
2198 {"$13", RTYPE_NUM | 13}, \
2199 {"$14", RTYPE_NUM | 14}, \
2200 {"$15", RTYPE_NUM | 15}, \
2201 {"$16", RTYPE_NUM | 16}, \
2202 {"$17", RTYPE_NUM | 17}, \
2203 {"$18", RTYPE_NUM | 18}, \
2204 {"$19", RTYPE_NUM | 19}, \
2205 {"$20", RTYPE_NUM | 20}, \
2206 {"$21", RTYPE_NUM | 21}, \
2207 {"$22", RTYPE_NUM | 22}, \
2208 {"$23", RTYPE_NUM | 23}, \
2209 {"$24", RTYPE_NUM | 24}, \
2210 {"$25", RTYPE_NUM | 25}, \
2211 {"$26", RTYPE_NUM | 26}, \
2212 {"$27", RTYPE_NUM | 27}, \
2213 {"$28", RTYPE_NUM | 28}, \
2214 {"$29", RTYPE_NUM | 29}, \
2215 {"$30", RTYPE_NUM | 30}, \
2216 {"$31", RTYPE_NUM | 31}
2218 #define FPU_REGISTER_NAMES \
2219 {"$f0", RTYPE_FPU | 0}, \
2220 {"$f1", RTYPE_FPU | 1}, \
2221 {"$f2", RTYPE_FPU | 2}, \
2222 {"$f3", RTYPE_FPU | 3}, \
2223 {"$f4", RTYPE_FPU | 4}, \
2224 {"$f5", RTYPE_FPU | 5}, \
2225 {"$f6", RTYPE_FPU | 6}, \
2226 {"$f7", RTYPE_FPU | 7}, \
2227 {"$f8", RTYPE_FPU | 8}, \
2228 {"$f9", RTYPE_FPU | 9}, \
2229 {"$f10", RTYPE_FPU | 10}, \
2230 {"$f11", RTYPE_FPU | 11}, \
2231 {"$f12", RTYPE_FPU | 12}, \
2232 {"$f13", RTYPE_FPU | 13}, \
2233 {"$f14", RTYPE_FPU | 14}, \
2234 {"$f15", RTYPE_FPU | 15}, \
2235 {"$f16", RTYPE_FPU | 16}, \
2236 {"$f17", RTYPE_FPU | 17}, \
2237 {"$f18", RTYPE_FPU | 18}, \
2238 {"$f19", RTYPE_FPU | 19}, \
2239 {"$f20", RTYPE_FPU | 20}, \
2240 {"$f21", RTYPE_FPU | 21}, \
2241 {"$f22", RTYPE_FPU | 22}, \
2242 {"$f23", RTYPE_FPU | 23}, \
2243 {"$f24", RTYPE_FPU | 24}, \
2244 {"$f25", RTYPE_FPU | 25}, \
2245 {"$f26", RTYPE_FPU | 26}, \
2246 {"$f27", RTYPE_FPU | 27}, \
2247 {"$f28", RTYPE_FPU | 28}, \
2248 {"$f29", RTYPE_FPU | 29}, \
2249 {"$f30", RTYPE_FPU | 30}, \
2250 {"$f31", RTYPE_FPU | 31}
2252 #define FPU_CONDITION_CODE_NAMES \
2253 {"$fcc0", RTYPE_FCC | 0}, \
2254 {"$fcc1", RTYPE_FCC | 1}, \
2255 {"$fcc2", RTYPE_FCC | 2}, \
2256 {"$fcc3", RTYPE_FCC | 3}, \
2257 {"$fcc4", RTYPE_FCC | 4}, \
2258 {"$fcc5", RTYPE_FCC | 5}, \
2259 {"$fcc6", RTYPE_FCC | 6}, \
2260 {"$fcc7", RTYPE_FCC | 7}
2262 #define COPROC_CONDITION_CODE_NAMES \
2263 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2264 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2265 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2266 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2267 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2268 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2269 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2270 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2272 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2273 {"$a4", RTYPE_GP | 8}, \
2274 {"$a5", RTYPE_GP | 9}, \
2275 {"$a6", RTYPE_GP | 10}, \
2276 {"$a7", RTYPE_GP | 11}, \
2277 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2278 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2279 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2280 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2281 {"$t0", RTYPE_GP | 12}, \
2282 {"$t1", RTYPE_GP | 13}, \
2283 {"$t2", RTYPE_GP | 14}, \
2284 {"$t3", RTYPE_GP | 15}
2286 #define O32_SYMBOLIC_REGISTER_NAMES \
2287 {"$t0", RTYPE_GP | 8}, \
2288 {"$t1", RTYPE_GP | 9}, \
2289 {"$t2", RTYPE_GP | 10}, \
2290 {"$t3", RTYPE_GP | 11}, \
2291 {"$t4", RTYPE_GP | 12}, \
2292 {"$t5", RTYPE_GP | 13}, \
2293 {"$t6", RTYPE_GP | 14}, \
2294 {"$t7", RTYPE_GP | 15}, \
2295 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2296 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2297 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2298 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2300 /* Remaining symbolic register names */
2301 #define SYMBOLIC_REGISTER_NAMES \
2302 {"$zero", RTYPE_GP | 0}, \
2303 {"$at", RTYPE_GP | 1}, \
2304 {"$AT", RTYPE_GP | 1}, \
2305 {"$v0", RTYPE_GP | 2}, \
2306 {"$v1", RTYPE_GP | 3}, \
2307 {"$a0", RTYPE_GP | 4}, \
2308 {"$a1", RTYPE_GP | 5}, \
2309 {"$a2", RTYPE_GP | 6}, \
2310 {"$a3", RTYPE_GP | 7}, \
2311 {"$s0", RTYPE_GP | 16}, \
2312 {"$s1", RTYPE_GP | 17}, \
2313 {"$s2", RTYPE_GP | 18}, \
2314 {"$s3", RTYPE_GP | 19}, \
2315 {"$s4", RTYPE_GP | 20}, \
2316 {"$s5", RTYPE_GP | 21}, \
2317 {"$s6", RTYPE_GP | 22}, \
2318 {"$s7", RTYPE_GP | 23}, \
2319 {"$t8", RTYPE_GP | 24}, \
2320 {"$t9", RTYPE_GP | 25}, \
2321 {"$k0", RTYPE_GP | 26}, \
2322 {"$kt0", RTYPE_GP | 26}, \
2323 {"$k1", RTYPE_GP | 27}, \
2324 {"$kt1", RTYPE_GP | 27}, \
2325 {"$gp", RTYPE_GP | 28}, \
2326 {"$sp", RTYPE_GP | 29}, \
2327 {"$s8", RTYPE_GP | 30}, \
2328 {"$fp", RTYPE_GP | 30}, \
2329 {"$ra", RTYPE_GP | 31}
2331 #define MIPS16_SPECIAL_REGISTER_NAMES \
2332 {"$pc", RTYPE_PC | 0}
2334 #define MDMX_VECTOR_REGISTER_NAMES \
2335 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2336 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2337 {"$v2", RTYPE_VEC | 2}, \
2338 {"$v3", RTYPE_VEC | 3}, \
2339 {"$v4", RTYPE_VEC | 4}, \
2340 {"$v5", RTYPE_VEC | 5}, \
2341 {"$v6", RTYPE_VEC | 6}, \
2342 {"$v7", RTYPE_VEC | 7}, \
2343 {"$v8", RTYPE_VEC | 8}, \
2344 {"$v9", RTYPE_VEC | 9}, \
2345 {"$v10", RTYPE_VEC | 10}, \
2346 {"$v11", RTYPE_VEC | 11}, \
2347 {"$v12", RTYPE_VEC | 12}, \
2348 {"$v13", RTYPE_VEC | 13}, \
2349 {"$v14", RTYPE_VEC | 14}, \
2350 {"$v15", RTYPE_VEC | 15}, \
2351 {"$v16", RTYPE_VEC | 16}, \
2352 {"$v17", RTYPE_VEC | 17}, \
2353 {"$v18", RTYPE_VEC | 18}, \
2354 {"$v19", RTYPE_VEC | 19}, \
2355 {"$v20", RTYPE_VEC | 20}, \
2356 {"$v21", RTYPE_VEC | 21}, \
2357 {"$v22", RTYPE_VEC | 22}, \
2358 {"$v23", RTYPE_VEC | 23}, \
2359 {"$v24", RTYPE_VEC | 24}, \
2360 {"$v25", RTYPE_VEC | 25}, \
2361 {"$v26", RTYPE_VEC | 26}, \
2362 {"$v27", RTYPE_VEC | 27}, \
2363 {"$v28", RTYPE_VEC | 28}, \
2364 {"$v29", RTYPE_VEC | 29}, \
2365 {"$v30", RTYPE_VEC | 30}, \
2366 {"$v31", RTYPE_VEC | 31}
2368 #define MIPS_DSP_ACCUMULATOR_NAMES \
2369 {"$ac0", RTYPE_ACC | 0}, \
2370 {"$ac1", RTYPE_ACC | 1}, \
2371 {"$ac2", RTYPE_ACC | 2}, \
2372 {"$ac3", RTYPE_ACC | 3}
2374 static const struct regname reg_names[] = {
2375 GENERIC_REGISTER_NUMBERS,
2377 FPU_CONDITION_CODE_NAMES,
2378 COPROC_CONDITION_CODE_NAMES,
2380 /* The $txx registers depends on the abi,
2381 these will be added later into the symbol table from
2382 one of the tables below once mips_abi is set after
2383 parsing of arguments from the command line. */
2384 SYMBOLIC_REGISTER_NAMES,
2386 MIPS16_SPECIAL_REGISTER_NAMES,
2387 MDMX_VECTOR_REGISTER_NAMES,
2388 MIPS_DSP_ACCUMULATOR_NAMES,
2392 static const struct regname reg_names_o32[] = {
2393 O32_SYMBOLIC_REGISTER_NAMES,
2397 static const struct regname reg_names_n32n64[] = {
2398 N32N64_SYMBOLIC_REGISTER_NAMES,
2402 /* Check if S points at a valid register specifier according to TYPES.
2403 If so, then return 1, advance S to consume the specifier and store
2404 the register's number in REGNOP, otherwise return 0. */
2407 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2414 /* Find end of name. */
2416 if (is_name_beginner (*e))
2418 while (is_part_of_name (*e))
2421 /* Terminate name. */
2425 /* Look for a register symbol. */
2426 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
2428 int r = S_GET_VALUE (symbolP);
2430 reg = r & RNUM_MASK;
2431 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
2432 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2433 reg = (r & RNUM_MASK) - 2;
2435 /* Else see if this is a register defined in an itbl entry. */
2436 else if ((types & RTYPE_GP) && itbl_have_entries)
2443 if (itbl_get_reg_val (n, &r))
2444 reg = r & RNUM_MASK;
2447 /* Advance to next token if a register was recognised. */
2450 else if (types & RWARN)
2451 as_warn (_("Unrecognized register name `%s'"), *s);
2459 /* Check if S points at a valid register list according to TYPES.
2460 If so, then return 1, advance S to consume the list and store
2461 the registers present on the list as a bitmask of ones in REGLISTP,
2462 otherwise return 0. A valid list comprises a comma-separated
2463 enumeration of valid single registers and/or dash-separated
2464 contiguous register ranges as determined by their numbers.
2466 As a special exception if one of s0-s7 registers is specified as
2467 the range's lower delimiter and s8 (fp) is its upper one, then no
2468 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2469 are selected; they have to be listed separately if needed. */
2472 reglist_lookup (char **s, unsigned int types, unsigned int *reglistp)
2474 unsigned int reglist = 0;
2475 unsigned int lastregno;
2476 bfd_boolean ok = TRUE;
2477 unsigned int regmask;
2478 char *s_endlist = *s;
2482 while (reg_lookup (s, types, ®no))
2488 ok = reg_lookup (s, types, &lastregno);
2489 if (ok && lastregno < regno)
2495 if (lastregno == FP && regno >= S0 && regno <= S7)
2500 regmask = 1 << lastregno;
2501 regmask = (regmask << 1) - 1;
2502 regmask ^= (1 << regno) - 1;
2516 *reglistp = reglist;
2517 return ok && reglist != 0;
2520 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
2521 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2524 is_opcode_valid (const struct mips_opcode *mo)
2526 int isa = mips_opts.isa;
2527 int ase = mips_opts.ase;
2531 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
2532 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2533 if ((ase & mips_ases[i].flags) == mips_ases[i].flags)
2534 ase |= mips_ases[i].flags64;
2536 if (!opcode_is_member (mo, isa, ase, mips_opts.arch))
2539 /* Check whether the instruction or macro requires single-precision or
2540 double-precision floating-point support. Note that this information is
2541 stored differently in the opcode table for insns and macros. */
2542 if (mo->pinfo == INSN_MACRO)
2544 fp_s = mo->pinfo2 & INSN2_M_FP_S;
2545 fp_d = mo->pinfo2 & INSN2_M_FP_D;
2549 fp_s = mo->pinfo & FP_S;
2550 fp_d = mo->pinfo & FP_D;
2553 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
2556 if (fp_s && mips_opts.soft_float)
2562 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2563 selected ISA and architecture. */
2566 is_opcode_valid_16 (const struct mips_opcode *mo)
2568 return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch);
2571 /* Return TRUE if the size of the microMIPS opcode MO matches one
2572 explicitly requested. Always TRUE in the standard MIPS mode. */
2575 is_size_valid (const struct mips_opcode *mo)
2577 if (!mips_opts.micromips)
2580 if (mips_opts.insn32)
2582 if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4)
2584 if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0)
2587 if (!forced_insn_length)
2589 if (mo->pinfo == INSN_MACRO)
2591 return forced_insn_length == micromips_insn_length (mo);
2594 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2595 of the preceding instruction. Always TRUE in the standard MIPS mode.
2597 We don't accept macros in 16-bit delay slots to avoid a case where
2598 a macro expansion fails because it relies on a preceding 32-bit real
2599 instruction to have matched and does not handle the operands correctly.
2600 The only macros that may expand to 16-bit instructions are JAL that
2601 cannot be placed in a delay slot anyway, and corner cases of BALIGN
2602 and BGT (that likewise cannot be placed in a delay slot) that decay to
2603 a NOP. In all these cases the macros precede any corresponding real
2604 instruction definitions in the opcode table, so they will match in the
2605 second pass where the size of the delay slot is ignored and therefore
2606 produce correct code. */
2609 is_delay_slot_valid (const struct mips_opcode *mo)
2611 if (!mips_opts.micromips)
2614 if (mo->pinfo == INSN_MACRO)
2615 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0;
2616 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
2617 && micromips_insn_length (mo) != 4)
2619 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
2620 && micromips_insn_length (mo) != 2)
2626 /* For consistency checking, verify that all bits of OPCODE are
2627 specified either by the match/mask part of the instruction
2628 definition, or by the operand list. INSN_BITS says which
2629 bits of the instruction are significant and DECODE_OPERAND
2630 provides the mips_operand description of each operand. */
2633 validate_mips_insn (const struct mips_opcode *opcode,
2634 unsigned long insn_bits,
2635 const struct mips_operand *(*decode_operand) (const char *))
2638 unsigned long used_bits, doubled, undefined;
2639 const struct mips_operand *operand;
2641 if ((opcode->mask & opcode->match) != opcode->match)
2643 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
2644 opcode->name, opcode->args);
2648 for (s = opcode->args; *s; ++s)
2657 operand = decode_operand (s);
2660 as_bad (_("internal: unknown operand type: %s %s"),
2661 opcode->name, opcode->args);
2664 used_bits |= ((1 << operand->size) - 1) << operand->lsb;
2665 if (operand->type == OP_MDMX_IMM_REG)
2666 /* Bit 5 is the format selector (OB vs QH). The opcode table
2667 has separate entries for each format. */
2668 used_bits &= ~(1 << (operand->lsb + 5));
2669 /* Skip prefix characters. */
2670 if (*s == '+' || *s == 'm')
2674 doubled = used_bits & opcode->mask & insn_bits;
2677 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
2678 " %s %s"), doubled, opcode->name, opcode->args);
2681 used_bits |= opcode->mask;
2682 undefined = ~used_bits & insn_bits;
2685 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
2686 undefined, opcode->name, opcode->args);
2689 used_bits &= ~insn_bits;
2692 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
2693 used_bits, opcode->name, opcode->args);
2699 /* The microMIPS version of validate_mips_insn. */
2702 validate_micromips_insn (const struct mips_opcode *opc)
2704 unsigned long insn_bits;
2705 unsigned long major;
2706 unsigned int length;
2708 length = micromips_insn_length (opc);
2709 if (length != 2 && length != 4)
2711 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
2712 "%s %s"), length, opc->name, opc->args);
2715 major = opc->match >> (10 + 8 * (length - 2));
2716 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
2717 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
2719 as_bad (_("Internal error: bad microMIPS opcode "
2720 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
2724 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
2725 insn_bits = 1 << 4 * length;
2726 insn_bits <<= 4 * length;
2728 return validate_mips_insn (opc, insn_bits, decode_micromips_operand);
2731 /* This function is called once, at assembler startup time. It should set up
2732 all the tables, etc. that the MD part of the assembler will need. */
2737 const char *retval = NULL;
2741 if (mips_pic != NO_PIC)
2743 if (g_switch_seen && g_switch_value != 0)
2744 as_bad (_("-G may not be used in position-independent code"));
2748 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
2749 as_warn (_("Could not set architecture and machine"));
2751 op_hash = hash_new ();
2753 for (i = 0; i < NUMOPCODES;)
2755 const char *name = mips_opcodes[i].name;
2757 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
2760 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
2761 mips_opcodes[i].name, retval);
2762 /* Probably a memory allocation problem? Give up now. */
2763 as_fatal (_("Broken assembler. No assembly attempted."));
2767 if (mips_opcodes[i].pinfo != INSN_MACRO)
2769 if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff,
2770 decode_mips_operand))
2772 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2774 create_insn (&nop_insn, mips_opcodes + i);
2775 if (mips_fix_loongson2f_nop)
2776 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
2777 nop_insn.fixed_p = 1;
2782 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
2785 mips16_op_hash = hash_new ();
2788 while (i < bfd_mips16_num_opcodes)
2790 const char *name = mips16_opcodes[i].name;
2792 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
2794 as_fatal (_("internal: can't hash `%s': %s"),
2795 mips16_opcodes[i].name, retval);
2798 if (mips16_opcodes[i].pinfo != INSN_MACRO
2799 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
2800 != mips16_opcodes[i].match))
2802 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
2803 mips16_opcodes[i].name, mips16_opcodes[i].args);
2806 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2808 create_insn (&mips16_nop_insn, mips16_opcodes + i);
2809 mips16_nop_insn.fixed_p = 1;
2813 while (i < bfd_mips16_num_opcodes
2814 && strcmp (mips16_opcodes[i].name, name) == 0);
2817 micromips_op_hash = hash_new ();
2820 while (i < bfd_micromips_num_opcodes)
2822 const char *name = micromips_opcodes[i].name;
2824 retval = hash_insert (micromips_op_hash, name,
2825 (void *) µmips_opcodes[i]);
2827 as_fatal (_("internal: can't hash `%s': %s"),
2828 micromips_opcodes[i].name, retval);
2830 if (micromips_opcodes[i].pinfo != INSN_MACRO)
2832 struct mips_cl_insn *micromips_nop_insn;
2834 if (!validate_micromips_insn (µmips_opcodes[i]))
2837 if (micromips_insn_length (micromips_opcodes + i) == 2)
2838 micromips_nop_insn = µmips_nop16_insn;
2839 else if (micromips_insn_length (micromips_opcodes + i) == 4)
2840 micromips_nop_insn = µmips_nop32_insn;
2844 if (micromips_nop_insn->insn_mo == NULL
2845 && strcmp (name, "nop") == 0)
2847 create_insn (micromips_nop_insn, micromips_opcodes + i);
2848 micromips_nop_insn->fixed_p = 1;
2851 while (++i < bfd_micromips_num_opcodes
2852 && strcmp (micromips_opcodes[i].name, name) == 0);
2856 as_fatal (_("Broken assembler. No assembly attempted."));
2858 /* We add all the general register names to the symbol table. This
2859 helps us detect invalid uses of them. */
2860 for (i = 0; reg_names[i].name; i++)
2861 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
2862 reg_names[i].num, /* & RNUM_MASK, */
2863 &zero_address_frag));
2865 for (i = 0; reg_names_n32n64[i].name; i++)
2866 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
2867 reg_names_n32n64[i].num, /* & RNUM_MASK, */
2868 &zero_address_frag));
2870 for (i = 0; reg_names_o32[i].name; i++)
2871 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
2872 reg_names_o32[i].num, /* & RNUM_MASK, */
2873 &zero_address_frag));
2875 mips_no_prev_insn ();
2878 mips_cprmask[0] = 0;
2879 mips_cprmask[1] = 0;
2880 mips_cprmask[2] = 0;
2881 mips_cprmask[3] = 0;
2883 /* set the default alignment for the text section (2**2) */
2884 record_alignment (text_section, 2);
2886 bfd_set_gp_size (stdoutput, g_switch_value);
2888 /* On a native system other than VxWorks, sections must be aligned
2889 to 16 byte boundaries. When configured for an embedded ELF
2890 target, we don't bother. */
2891 if (strncmp (TARGET_OS, "elf", 3) != 0
2892 && strncmp (TARGET_OS, "vxworks", 7) != 0)
2894 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
2895 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
2896 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
2899 /* Create a .reginfo section for register masks and a .mdebug
2900 section for debugging information. */
2908 subseg = now_subseg;
2910 /* The ABI says this section should be loaded so that the
2911 running program can access it. However, we don't load it
2912 if we are configured for an embedded target */
2913 flags = SEC_READONLY | SEC_DATA;
2914 if (strncmp (TARGET_OS, "elf", 3) != 0)
2915 flags |= SEC_ALLOC | SEC_LOAD;
2917 if (mips_abi != N64_ABI)
2919 sec = subseg_new (".reginfo", (subsegT) 0);
2921 bfd_set_section_flags (stdoutput, sec, flags);
2922 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
2924 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
2928 /* The 64-bit ABI uses a .MIPS.options section rather than
2929 .reginfo section. */
2930 sec = subseg_new (".MIPS.options", (subsegT) 0);
2931 bfd_set_section_flags (stdoutput, sec, flags);
2932 bfd_set_section_alignment (stdoutput, sec, 3);
2934 /* Set up the option header. */
2936 Elf_Internal_Options opthdr;
2939 opthdr.kind = ODK_REGINFO;
2940 opthdr.size = (sizeof (Elf_External_Options)
2941 + sizeof (Elf64_External_RegInfo));
2944 f = frag_more (sizeof (Elf_External_Options));
2945 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2946 (Elf_External_Options *) f);
2948 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2952 if (ECOFF_DEBUGGING)
2954 sec = subseg_new (".mdebug", (subsegT) 0);
2955 (void) bfd_set_section_flags (stdoutput, sec,
2956 SEC_HAS_CONTENTS | SEC_READONLY);
2957 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2959 else if (mips_flag_pdr)
2961 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2962 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2963 SEC_READONLY | SEC_RELOC
2965 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2968 subseg_set (seg, subseg);
2971 if (! ECOFF_DEBUGGING)
2974 if (mips_fix_vr4120)
2975 init_vr4120_conflicts ();
2981 mips_emit_delays ();
2982 if (! ECOFF_DEBUGGING)
2987 md_assemble (char *str)
2989 struct mips_cl_insn insn;
2990 bfd_reloc_code_real_type unused_reloc[3]
2991 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2993 imm_expr.X_op = O_absent;
2994 imm2_expr.X_op = O_absent;
2995 offset_expr.X_op = O_absent;
2996 offset_reloc[0] = BFD_RELOC_UNUSED;
2997 offset_reloc[1] = BFD_RELOC_UNUSED;
2998 offset_reloc[2] = BFD_RELOC_UNUSED;
3000 mips_mark_labels ();
3001 mips_assembling_insn = TRUE;
3003 if (mips_opts.mips16)
3004 mips16_ip (str, &insn);
3007 mips_ip (str, &insn);
3008 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
3009 str, insn.insn_opcode));
3013 as_bad ("%s `%s'", insn_error, str);
3014 else if (insn.insn_mo->pinfo == INSN_MACRO)
3017 if (mips_opts.mips16)
3018 mips16_macro (&insn);
3025 if (offset_expr.X_op != O_absent)
3026 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
3028 append_insn (&insn, NULL, unused_reloc, FALSE);
3031 mips_assembling_insn = FALSE;
3034 /* Convenience functions for abstracting away the differences between
3035 MIPS16 and non-MIPS16 relocations. */
3037 static inline bfd_boolean
3038 mips16_reloc_p (bfd_reloc_code_real_type reloc)
3042 case BFD_RELOC_MIPS16_JMP:
3043 case BFD_RELOC_MIPS16_GPREL:
3044 case BFD_RELOC_MIPS16_GOT16:
3045 case BFD_RELOC_MIPS16_CALL16:
3046 case BFD_RELOC_MIPS16_HI16_S:
3047 case BFD_RELOC_MIPS16_HI16:
3048 case BFD_RELOC_MIPS16_LO16:
3056 static inline bfd_boolean
3057 micromips_reloc_p (bfd_reloc_code_real_type reloc)
3061 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
3062 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
3063 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
3064 case BFD_RELOC_MICROMIPS_GPREL16:
3065 case BFD_RELOC_MICROMIPS_JMP:
3066 case BFD_RELOC_MICROMIPS_HI16:
3067 case BFD_RELOC_MICROMIPS_HI16_S:
3068 case BFD_RELOC_MICROMIPS_LO16:
3069 case BFD_RELOC_MICROMIPS_LITERAL:
3070 case BFD_RELOC_MICROMIPS_GOT16:
3071 case BFD_RELOC_MICROMIPS_CALL16:
3072 case BFD_RELOC_MICROMIPS_GOT_HI16:
3073 case BFD_RELOC_MICROMIPS_GOT_LO16:
3074 case BFD_RELOC_MICROMIPS_CALL_HI16:
3075 case BFD_RELOC_MICROMIPS_CALL_LO16:
3076 case BFD_RELOC_MICROMIPS_SUB:
3077 case BFD_RELOC_MICROMIPS_GOT_PAGE:
3078 case BFD_RELOC_MICROMIPS_GOT_OFST:
3079 case BFD_RELOC_MICROMIPS_GOT_DISP:
3080 case BFD_RELOC_MICROMIPS_HIGHEST:
3081 case BFD_RELOC_MICROMIPS_HIGHER:
3082 case BFD_RELOC_MICROMIPS_SCN_DISP:
3083 case BFD_RELOC_MICROMIPS_JALR:
3091 static inline bfd_boolean
3092 jmp_reloc_p (bfd_reloc_code_real_type reloc)
3094 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
3097 static inline bfd_boolean
3098 got16_reloc_p (bfd_reloc_code_real_type reloc)
3100 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
3101 || reloc == BFD_RELOC_MICROMIPS_GOT16);
3104 static inline bfd_boolean
3105 hi16_reloc_p (bfd_reloc_code_real_type reloc)
3107 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
3108 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
3111 static inline bfd_boolean
3112 lo16_reloc_p (bfd_reloc_code_real_type reloc)
3114 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
3115 || reloc == BFD_RELOC_MICROMIPS_LO16);
3118 static inline bfd_boolean
3119 jalr_reloc_p (bfd_reloc_code_real_type reloc)
3121 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
3124 static inline bfd_boolean
3125 gprel16_reloc_p (bfd_reloc_code_real_type reloc)
3127 return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL
3128 || reloc == BFD_RELOC_MICROMIPS_GPREL16);
3131 /* Return true if RELOC is a PC-relative relocation that does not have
3132 full address range. */
3134 static inline bfd_boolean
3135 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc)
3139 case BFD_RELOC_16_PCREL_S2:
3140 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
3141 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
3142 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
3145 case BFD_RELOC_32_PCREL:
3146 return HAVE_64BIT_ADDRESSES;
3153 /* Return true if the given relocation might need a matching %lo().
3154 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
3155 need a matching %lo() when applied to local symbols. */
3157 static inline bfd_boolean
3158 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
3160 return (HAVE_IN_PLACE_ADDENDS
3161 && (hi16_reloc_p (reloc)
3162 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
3163 all GOT16 relocations evaluate to "G". */
3164 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
3167 /* Return the type of %lo() reloc needed by RELOC, given that
3168 reloc_needs_lo_p. */
3170 static inline bfd_reloc_code_real_type
3171 matching_lo_reloc (bfd_reloc_code_real_type reloc)
3173 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
3174 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
3178 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
3181 static inline bfd_boolean
3182 fixup_has_matching_lo_p (fixS *fixp)
3184 return (fixp->fx_next != NULL
3185 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
3186 && fixp->fx_addsy == fixp->fx_next->fx_addsy
3187 && fixp->fx_offset == fixp->fx_next->fx_offset);
3190 /* This function returns true if modifying a register requires a
3194 reg_needs_delay (unsigned int reg)
3196 unsigned long prev_pinfo;
3198 prev_pinfo = history[0].insn_mo->pinfo;
3199 if (! mips_opts.noreorder
3200 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
3201 && ! gpr_interlocks)
3202 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
3203 && ! cop_interlocks)))
3205 /* A load from a coprocessor or from memory. All load delays
3206 delay the use of general register rt for one instruction. */
3207 /* Itbl support may require additional care here. */
3208 know (prev_pinfo & INSN_WRITE_GPR_T);
3209 if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0]))
3216 /* Move all labels in LABELS to the current insertion point. TEXT_P
3217 says whether the labels refer to text or data. */
3220 mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
3222 struct insn_label_list *l;
3225 for (l = labels; l != NULL; l = l->next)
3227 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
3228 symbol_set_frag (l->label, frag_now);
3229 val = (valueT) frag_now_fix ();
3230 /* MIPS16/microMIPS text labels are stored as odd. */
3231 if (text_p && HAVE_CODE_COMPRESSION)
3233 S_SET_VALUE (l->label, val);
3237 /* Move all labels in insn_labels to the current insertion point
3238 and treat them as text labels. */
3241 mips_move_text_labels (void)
3243 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
3247 s_is_linkonce (symbolS *sym, segT from_seg)
3249 bfd_boolean linkonce = FALSE;
3250 segT symseg = S_GET_SEGMENT (sym);
3252 if (symseg != from_seg && !S_IS_LOCAL (sym))
3254 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
3256 /* The GNU toolchain uses an extension for ELF: a section
3257 beginning with the magic string .gnu.linkonce is a
3258 linkonce section. */
3259 if (strncmp (segment_name (symseg), ".gnu.linkonce",
3260 sizeof ".gnu.linkonce" - 1) == 0)
3266 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
3267 linker to handle them specially, such as generating jalx instructions
3268 when needed. We also make them odd for the duration of the assembly,
3269 in order to generate the right sort of code. We will make them even
3270 in the adjust_symtab routine, while leaving them marked. This is
3271 convenient for the debugger and the disassembler. The linker knows
3272 to make them odd again. */
3275 mips_compressed_mark_label (symbolS *label)
3277 gas_assert (HAVE_CODE_COMPRESSION);
3279 if (mips_opts.mips16)
3280 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
3282 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
3283 if ((S_GET_VALUE (label) & 1) == 0
3284 /* Don't adjust the address if the label is global or weak, or
3285 in a link-once section, since we'll be emitting symbol reloc
3286 references to it which will be patched up by the linker, and
3287 the final value of the symbol may or may not be MIPS16/microMIPS. */
3288 && !S_IS_WEAK (label)
3289 && !S_IS_EXTERNAL (label)
3290 && !s_is_linkonce (label, now_seg))
3291 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
3294 /* Mark preceding MIPS16 or microMIPS instruction labels. */
3297 mips_compressed_mark_labels (void)
3299 struct insn_label_list *l;
3301 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next)
3302 mips_compressed_mark_label (l->label);
3305 /* End the current frag. Make it a variant frag and record the
3309 relax_close_frag (void)
3311 mips_macro_warning.first_frag = frag_now;
3312 frag_var (rs_machine_dependent, 0, 0,
3313 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
3314 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
3316 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
3317 mips_relax.first_fixup = 0;
3320 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
3321 See the comment above RELAX_ENCODE for more details. */
3324 relax_start (symbolS *symbol)
3326 gas_assert (mips_relax.sequence == 0);
3327 mips_relax.sequence = 1;
3328 mips_relax.symbol = symbol;
3331 /* Start generating the second version of a relaxable sequence.
3332 See the comment above RELAX_ENCODE for more details. */
3337 gas_assert (mips_relax.sequence == 1);
3338 mips_relax.sequence = 2;
3341 /* End the current relaxable sequence. */
3346 gas_assert (mips_relax.sequence == 2);
3347 relax_close_frag ();
3348 mips_relax.sequence = 0;
3351 /* Return true if IP is a delayed branch or jump. */
3353 static inline bfd_boolean
3354 delayed_branch_p (const struct mips_cl_insn *ip)
3356 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
3357 | INSN_COND_BRANCH_DELAY
3358 | INSN_COND_BRANCH_LIKELY)) != 0;
3361 /* Return true if IP is a compact branch or jump. */
3363 static inline bfd_boolean
3364 compact_branch_p (const struct mips_cl_insn *ip)
3366 if (mips_opts.mips16)
3367 return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
3368 | MIPS16_INSN_COND_BRANCH)) != 0;
3370 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
3371 | INSN2_COND_BRANCH)) != 0;
3374 /* Return true if IP is an unconditional branch or jump. */
3376 static inline bfd_boolean
3377 uncond_branch_p (const struct mips_cl_insn *ip)
3379 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
3380 || (mips_opts.mips16
3381 ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0
3382 : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0));
3385 /* Return true if IP is a branch-likely instruction. */
3387 static inline bfd_boolean
3388 branch_likely_p (const struct mips_cl_insn *ip)
3390 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
3393 /* Return the type of nop that should be used to fill the delay slot
3394 of delayed branch IP. */
3396 static struct mips_cl_insn *
3397 get_delay_slot_nop (const struct mips_cl_insn *ip)
3399 if (mips_opts.micromips
3400 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
3401 return µmips_nop32_insn;
3405 /* Return the mask of core registers that IP reads or writes. */
3408 gpr_mod_mask (const struct mips_cl_insn *ip)
3410 unsigned long pinfo2;
3414 pinfo2 = ip->insn_mo->pinfo2;
3415 if (mips_opts.micromips)
3417 if (pinfo2 & INSN2_MOD_GPR_MD)
3418 mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)];
3419 if (pinfo2 & INSN2_MOD_GPR_MF)
3420 mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)];
3421 if (pinfo2 & INSN2_MOD_SP)
3427 /* Return the mask of core registers that IP reads. */
3430 gpr_read_mask (const struct mips_cl_insn *ip)
3432 unsigned long pinfo, pinfo2;
3435 mask = gpr_mod_mask (ip);
3436 pinfo = ip->insn_mo->pinfo;
3437 pinfo2 = ip->insn_mo->pinfo2;
3438 if (mips_opts.mips16)
3440 if (pinfo & MIPS16_INSN_READ_X)
3441 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3442 if (pinfo & MIPS16_INSN_READ_Y)
3443 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3444 if (pinfo & MIPS16_INSN_READ_T)
3446 if (pinfo & MIPS16_INSN_READ_SP)
3448 if (pinfo & MIPS16_INSN_READ_31)
3450 if (pinfo & MIPS16_INSN_READ_Z)
3451 mask |= 1 << (mips16_to_32_reg_map
3452 [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]);
3453 if (pinfo & MIPS16_INSN_READ_GPR_X)
3454 mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
3458 if (pinfo2 & INSN2_READ_GPR_D)
3459 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3460 if (pinfo & INSN_READ_GPR_T)
3461 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3462 if (pinfo & INSN_READ_GPR_S)
3463 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3464 if (pinfo2 & INSN2_READ_GP)
3466 if (pinfo2 & INSN2_READ_GPR_31)
3468 if (pinfo2 & INSN2_READ_GPR_Z)
3469 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3471 if (mips_opts.micromips)
3473 if (pinfo2 & INSN2_READ_GPR_MC)
3474 mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)];
3475 if (pinfo2 & INSN2_READ_GPR_ME)
3476 mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)];
3477 if (pinfo2 & INSN2_READ_GPR_MG)
3478 mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)];
3479 if (pinfo2 & INSN2_READ_GPR_MJ)
3480 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3481 if (pinfo2 & INSN2_READ_GPR_MMN)
3483 mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)];
3484 mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)];
3486 if (pinfo2 & INSN2_READ_GPR_MP)
3487 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3488 if (pinfo2 & INSN2_READ_GPR_MQ)
3489 mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)];
3491 /* Don't include register 0. */
3495 /* Return the mask of core registers that IP writes. */
3498 gpr_write_mask (const struct mips_cl_insn *ip)
3500 unsigned long pinfo, pinfo2;
3503 mask = gpr_mod_mask (ip);
3504 pinfo = ip->insn_mo->pinfo;
3505 pinfo2 = ip->insn_mo->pinfo2;
3506 if (mips_opts.mips16)
3508 if (pinfo & MIPS16_INSN_WRITE_X)
3509 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3510 if (pinfo & MIPS16_INSN_WRITE_Y)
3511 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3512 if (pinfo & MIPS16_INSN_WRITE_Z)
3513 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)];
3514 if (pinfo & MIPS16_INSN_WRITE_T)
3516 if (pinfo & MIPS16_INSN_WRITE_SP)
3518 if (pinfo & MIPS16_INSN_WRITE_31)
3520 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
3521 mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
3525 if (pinfo & INSN_WRITE_GPR_D)
3526 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3527 if (pinfo & INSN_WRITE_GPR_T)
3528 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3529 if (pinfo & INSN_WRITE_GPR_S)
3530 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3531 if (pinfo & INSN_WRITE_GPR_31)
3533 if (pinfo2 & INSN2_WRITE_GPR_Z)
3534 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3536 if (mips_opts.micromips)
3538 if (pinfo2 & INSN2_WRITE_GPR_MB)
3539 mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)];
3540 if (pinfo2 & INSN2_WRITE_GPR_MH)
3542 mask |= 1 << micromips_to_32_reg_h_map1[EXTRACT_OPERAND (1, MH, *ip)];
3543 mask |= 1 << micromips_to_32_reg_h_map2[EXTRACT_OPERAND (1, MH, *ip)];
3545 if (pinfo2 & INSN2_WRITE_GPR_MJ)
3546 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3547 if (pinfo2 & INSN2_WRITE_GPR_MP)
3548 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3550 /* Don't include register 0. */
3554 /* Return the mask of floating-point registers that IP reads. */
3557 fpr_read_mask (const struct mips_cl_insn *ip)
3559 unsigned long pinfo, pinfo2;
3563 pinfo = ip->insn_mo->pinfo;
3564 pinfo2 = ip->insn_mo->pinfo2;
3565 if (!mips_opts.mips16)
3567 if (pinfo2 & INSN2_READ_FPR_D)
3568 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3569 if (pinfo & INSN_READ_FPR_S)
3570 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3571 if (pinfo & INSN_READ_FPR_T)
3572 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3573 if (pinfo & INSN_READ_FPR_R)
3574 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip);
3575 if (pinfo2 & INSN2_READ_FPR_Z)
3576 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3578 /* Conservatively treat all operands to an FP_D instruction are doubles.
3579 (This is overly pessimistic for things like cvt.d.s.) */
3580 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3585 /* Return the mask of floating-point registers that IP writes. */
3588 fpr_write_mask (const struct mips_cl_insn *ip)
3590 unsigned long pinfo, pinfo2;
3594 pinfo = ip->insn_mo->pinfo;
3595 pinfo2 = ip->insn_mo->pinfo2;
3596 if (!mips_opts.mips16)
3598 if (pinfo & INSN_WRITE_FPR_D)
3599 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3600 if (pinfo & INSN_WRITE_FPR_S)
3601 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3602 if (pinfo & INSN_WRITE_FPR_T)
3603 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3604 if (pinfo2 & INSN2_WRITE_FPR_Z)
3605 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3607 /* Conservatively treat all operands to an FP_D instruction are doubles.
3608 (This is overly pessimistic for things like cvt.s.d.) */
3609 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3614 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
3615 Check whether that is allowed. */
3618 mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum)
3620 const char *s = insn->name;
3622 if (insn->pinfo == INSN_MACRO)
3623 /* Let a macro pass, we'll catch it later when it is expanded. */
3626 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || mips_opts.arch == CPU_R5900)
3628 /* Allow odd registers for single-precision ops. */
3629 switch (insn->pinfo & (FP_S | FP_D))
3640 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
3641 s = strchr (insn->name, '.');
3642 if (s != NULL && opnum == 2)
3643 s = strchr (s + 1, '.');
3644 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
3647 /* Single-precision coprocessor loads and moves are OK too. */
3648 if ((insn->pinfo & FP_S)
3649 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
3650 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
3656 /* Report that user-supplied argument ARGNUM for INSN was VAL, but should
3657 have been in the range [MIN_VAL, MAX_VAL]. PRINT_HEX says whether
3658 this operand is normally printed in hex or decimal. */
3661 report_bad_range (struct mips_cl_insn *insn, int argnum,
3662 offsetT val, int min_val, int max_val,
3663 bfd_boolean print_hex)
3665 if (print_hex && val >= 0)
3666 as_bad (_("Operand %d of `%s' must be in the range [0x%x, 0x%x],"
3668 argnum, insn->insn_mo->name, min_val, max_val, (unsigned long) val);
3670 as_bad (_("Operand %d of `%s' must be in the range [0x%x, 0x%x],"
3672 argnum, insn->insn_mo->name, min_val, max_val, (unsigned long) val);
3674 as_bad (_("Operand %d of `%s' must be in the range [%d, %d],"
3676 argnum, insn->insn_mo->name, min_val, max_val, (unsigned long) val);
3679 /* Report an invalid combination of position and size operands for a bitfield
3680 operation. POS and SIZE are the values that were given. */
3683 report_bad_field (offsetT pos, offsetT size)
3685 as_bad (_("Invalid field specification (position %ld, size %ld)"),
3686 (unsigned long) pos, (unsigned long) size);
3689 /* Information about an instruction argument that we're trying to match. */
3690 struct mips_arg_info
3692 /* The instruction so far. */
3693 struct mips_cl_insn *insn;
3695 /* The 1-based operand number, in terms of insn->insn_mo->args. */
3698 /* The 1-based argument number, for error reporting. This does not
3699 count elided optional registers, etc.. */
3702 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
3703 unsigned int last_regno;
3705 /* If the first operand was an OP_REG, this is the register that it
3706 specified, otherwise it is ILLEGAL_REG. */
3707 unsigned int dest_regno;
3709 /* The value of the last OP_INT operand. Only used for OP_MSB,
3710 where it gives the lsb position. */
3711 unsigned int last_op_int;
3713 /* If true, match routines should silently reject invalid arguments.
3714 If false, match routines can accept invalid arguments as long as
3715 they report an appropriate error. They still have the option of
3716 silently rejecting arguments, in which case a generic "Invalid operands"
3717 style of error will be used instead. */
3718 bfd_boolean soft_match;
3720 /* If true, the OP_INT match routine should treat plain symbolic operands
3721 as if a relocation operator like %lo(...) had been used. This is only
3722 ever true if the operand can be relocated. */
3723 bfd_boolean allow_nonconst;
3725 /* When true, the OP_INT match routine should allow unsigned N-bit
3726 arguments to be used where a signed N-bit operand is expected. */
3727 bfd_boolean lax_max;
3729 /* When true, the OP_REG match routine should assume that another operand
3730 appears after this one. It should fail the match if the register it
3731 sees is at the end of the argument list. */
3732 bfd_boolean optional_reg;
3734 /* True if a reference to the current AT register was seen. */
3735 bfd_boolean seen_at;
3738 /* Match a constant integer at S for ARG. Return null if the match failed.
3739 Otherwise return the end of the matched string and store the constant value
3740 in *VALUE. In the latter case, use FALLBACK as the value if the match
3741 succeeded with an error. */
3744 match_const_int (struct mips_arg_info *arg, char *s, offsetT *value,
3748 bfd_reloc_code_real_type r[3];
3751 num_relocs = my_getSmallExpression (&ex, r, s);
3752 if (*s == '(' && ex.X_op == O_register)
3754 /* Assume that the constant has been elided and that S is a base
3755 register. The rest of the match will fail if the assumption
3756 turns out to be wrong. */
3761 if (num_relocs == 0 && ex.X_op == O_constant)
3762 *value = ex.X_add_number;
3765 /* If we got a register rather than an expression, the default
3766 "Invalid operands" style of error seems more appropriate. */
3767 if (arg->soft_match || ex.X_op == O_register)
3769 as_bad (_("Operand %d of `%s' must be constant"),
3770 arg->argnum, arg->insn->insn_mo->name);
3776 /* Return the RTYPE_* flags for a register operand of type TYPE that
3777 appears in instruction OPCODE. */
3780 convert_reg_type (const struct mips_opcode *opcode,
3781 enum mips_reg_operand_type type)
3786 return RTYPE_NUM | RTYPE_GP;
3789 /* Allow vector register names for MDMX if the instruction is a 64-bit
3790 FPR load, store or move (including moves to and from GPRs). */
3791 if ((mips_opts.ase & ASE_MDMX)
3792 && (opcode->pinfo & FP_D)
3793 && (opcode->pinfo & (INSN_COPROC_MOVE_DELAY
3794 | INSN_COPROC_MEMORY_DELAY
3795 | INSN_LOAD_COPROC_DELAY
3796 | INSN_LOAD_MEMORY_DELAY
3797 | INSN_STORE_MEMORY)))
3798 return RTYPE_FPU | RTYPE_VEC;
3802 if (opcode->pinfo & (FP_D | FP_S))
3803 return RTYPE_CCC | RTYPE_FCC;
3807 if (opcode->membership & INSN_5400)
3809 return RTYPE_FPU | RTYPE_VEC;
3815 if (opcode->name[strlen (opcode->name) - 1] == '0')
3816 return RTYPE_NUM | RTYPE_CP0;
3825 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
3828 check_regno (struct mips_arg_info *arg,
3829 enum mips_reg_operand_type type, unsigned int regno)
3831 if (AT && type == OP_REG_GP && regno == AT)
3832 arg->seen_at = TRUE;
3834 if (type == OP_REG_FP
3837 && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum))
3838 as_warn (_("Float register should be even, was %d"), regno);
3840 if (type == OP_REG_CCC)
3845 name = arg->insn->insn_mo->name;
3846 length = strlen (name);
3847 if ((regno & 1) != 0
3848 && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0)
3849 || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0)))
3850 as_warn (_("Condition code register should be even for %s, was %d"),
3853 if ((regno & 3) != 0
3854 && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0))
3855 as_warn (_("Condition code register should be 0 or 4 for %s, was %d"),
3860 /* OP_INT matcher. */
3863 match_int_operand (struct mips_arg_info *arg,
3864 const struct mips_operand *operand_base, char *s)
3866 const struct mips_int_operand *operand;
3867 unsigned int uval, mask;
3868 int min_val, max_val, factor;
3870 bfd_boolean print_hex;
3872 operand = (const struct mips_int_operand *) operand_base;
3873 factor = 1 << operand->shift;
3874 mask = (1 << operand_base->size) - 1;
3875 max_val = (operand->max_val + operand->bias) << operand->shift;
3876 min_val = max_val - (mask << operand->shift);
3878 max_val = mask << operand->shift;
3880 if (operand_base->lsb == 0
3881 && operand_base->size == 16
3882 && operand->shift == 0
3883 && operand->bias == 0
3884 && (operand->max_val == 32767 || operand->max_val == 65535))
3886 /* The operand can be relocated. */
3887 offset_reloc[0] = BFD_RELOC_LO16;
3888 offset_reloc[1] = BFD_RELOC_UNUSED;
3889 offset_reloc[2] = BFD_RELOC_UNUSED;
3890 if (my_getSmallExpression (&offset_expr, offset_reloc, s) > 0)
3891 /* Relocation operators were used. Accept the arguent and
3892 leave the relocation value in offset_expr and offset_relocs
3893 for the caller to process. */
3895 if (*s == '(' && offset_expr.X_op == O_register)
3896 /* Assume that the constant has been elided and that S is a base
3897 register. The rest of the match will fail if the assumption
3898 turns out to be wrong. */
3903 if (offset_expr.X_op != O_constant)
3904 /* If non-constant operands are allowed then leave them for
3905 the caller to process, otherwise fail the match. */
3906 return arg->allow_nonconst ? s : 0;
3907 sval = offset_expr.X_add_number;
3909 /* Clear the global state; we're going to install the operand
3911 offset_reloc[0] = BFD_RELOC_UNUSED;
3912 offset_expr.X_op = O_absent;
3916 s = match_const_int (arg, s, &sval, min_val);
3921 arg->last_op_int = sval;
3923 /* Check the range. If there's a problem, record the lowest acceptable
3924 value in arg->last_op_int in order to prevent an unhelpful error
3927 Bit counts have traditionally been printed in hex by the disassembler
3928 but printed as decimal in error messages. Only resort to hex if
3929 the operand is bigger than 6 bits. */
3930 print_hex = operand->print_hex && operand_base->size > 6;
3931 if (sval < min_val || sval > max_val)
3933 if (arg->soft_match)
3935 report_bad_range (arg->insn, arg->argnum, sval, min_val, max_val,
3937 arg->last_op_int = min_val;
3939 else if (sval % factor)
3941 if (arg->soft_match)
3943 as_bad (print_hex && sval >= 0
3944 ? _("Operand %d of `%s' must be a factor of %d, was 0x%lx.")
3945 : _("Operand %d of `%s' must be a factor of %d, was %ld."),
3946 arg->argnum, arg->insn->insn_mo->name, factor,
3947 (unsigned long) sval);
3948 arg->last_op_int = min_val;
3951 uval = (unsigned int) sval >> operand->shift;
3952 uval -= operand->bias;
3954 /* Handle -mfix-cn63xxp1. */
3956 && mips_fix_cn63xxp1
3957 && !mips_opts.micromips
3958 && strcmp ("pref", arg->insn->insn_mo->name) == 0)
3973 /* The rest must be changed to 28. */
3978 insn_insert_operand (arg->insn, operand_base, uval);
3982 /* OP_MAPPED_INT matcher. */
3985 match_mapped_int_operand (struct mips_arg_info *arg,
3986 const struct mips_operand *operand_base, char *s)
3988 const struct mips_mapped_int_operand *operand;
3989 unsigned int uval, num_vals;
3992 operand = (const struct mips_mapped_int_operand *) operand_base;
3993 s = match_const_int (arg, s, &sval, operand->int_map[0]);
3997 num_vals = 1 << operand_base->size;
3998 for (uval = 0; uval < num_vals; uval++)
3999 if (operand->int_map[uval] == sval)
4001 if (uval == num_vals)
4004 insn_insert_operand (arg->insn, operand_base, uval);
4008 /* OP_MSB matcher. */
4011 match_msb_operand (struct mips_arg_info *arg,
4012 const struct mips_operand *operand_base, char *s)
4014 const struct mips_msb_operand *operand;
4015 int min_val, max_val, max_high;
4016 offsetT size, sval, high;
4018 operand = (const struct mips_msb_operand *) operand_base;
4019 min_val = operand->bias;
4020 max_val = min_val + (1 << operand_base->size) - 1;
4021 max_high = operand->opsize;
4023 s = match_const_int (arg, s, &size, 1);
4027 high = size + arg->last_op_int;
4028 sval = operand->add_lsb ? high : size;
4030 if (size < 0 || high > max_high || sval < min_val || sval > max_val)
4032 if (arg->soft_match)
4034 report_bad_field (arg->last_op_int, size);
4037 insn_insert_operand (arg->insn, operand_base, sval - min_val);
4041 /* OP_REG matcher. */
4044 match_reg_operand (struct mips_arg_info *arg,
4045 const struct mips_operand *operand_base, char *s)
4047 const struct mips_reg_operand *operand;
4048 unsigned int regno, uval, num_vals, types;
4050 operand = (const struct mips_reg_operand *) operand_base;
4051 types = convert_reg_type (arg->insn->insn_mo, operand->reg_type);
4052 if (!reg_lookup (&s, types, ®no))
4055 SKIP_SPACE_TABS (s);
4056 if (arg->optional_reg && *s == 0)
4059 if (operand->reg_map)
4061 num_vals = 1 << operand->root.size;
4062 for (uval = 0; uval < num_vals; uval++)
4063 if (operand->reg_map[uval] == regno)
4065 if (num_vals == uval)
4071 check_regno (arg, operand->reg_type, regno);
4072 arg->last_regno = regno;
4073 if (arg->opnum == 1)
4074 arg->dest_regno = regno;
4075 insn_insert_operand (arg->insn, operand_base, uval);
4079 /* OP_REG_PAIR matcher. */
4082 match_reg_pair_operand (struct mips_arg_info *arg,
4083 const struct mips_operand *operand_base, char *s)
4085 const struct mips_reg_pair_operand *operand;
4086 unsigned int regno1, regno2, uval, num_vals, types;
4088 operand = (const struct mips_reg_pair_operand *) operand_base;
4089 types = convert_reg_type (arg->insn->insn_mo, operand->reg_type);
4091 if (!reg_lookup (&s, types, ®no1))
4094 SKIP_SPACE_TABS (s);
4099 if (!reg_lookup (&s, types, ®no2))
4102 num_vals = 1 << operand_base->size;
4103 for (uval = 0; uval < num_vals; uval++)
4104 if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2)
4106 if (uval == num_vals)
4109 check_regno (arg, operand->reg_type, regno1);
4110 check_regno (arg, operand->reg_type, regno2);
4111 insn_insert_operand (arg->insn, operand_base, uval);
4115 /* OP_PCREL matcher. The caller chooses the relocation type. */
4118 match_pcrel_operand (char *s)
4120 my_getExpression (&offset_expr, s);
4124 /* OP_PERF_REG matcher. */
4127 match_perf_reg_operand (struct mips_arg_info *arg,
4128 const struct mips_operand *operand, char *s)
4132 s = match_const_int (arg, s, &sval, 0);
4138 || (mips_opts.arch == CPU_R5900
4139 && (strcmp (arg->insn->insn_mo->name, "mfps") == 0
4140 || strcmp (arg->insn->insn_mo->name, "mtps") == 0))))
4142 if (arg->soft_match)
4144 as_bad (_("Invalid performance register (%ld)"), (unsigned long) sval);
4147 insn_insert_operand (arg->insn, operand, sval);
4151 /* OP_ADDIUSP matcher. */
4154 match_addiusp_operand (struct mips_arg_info *arg,
4155 const struct mips_operand *operand, char *s)
4160 s = match_const_int (arg, s, &sval, -256);
4168 if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1))
4171 uval = (unsigned int) sval;
4172 uval = ((uval >> 1) & ~0xff) | (uval & 0xff);
4173 insn_insert_operand (arg->insn, operand, uval);
4177 /* OP_CLO_CLZ_DEST matcher. */
4180 match_clo_clz_dest_operand (struct mips_arg_info *arg,
4181 const struct mips_operand *operand, char *s)
4185 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
4188 check_regno (arg, OP_REG_GP, regno);
4189 insn_insert_operand (arg->insn, operand, regno | (regno << 5));
4193 /* OP_LWM_SWM_LIST matcher. */
4196 match_lwm_swm_list_operand (struct mips_arg_info *arg,
4197 const struct mips_operand *operand, char *s)
4199 unsigned int reglist, sregs, ra;
4201 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
4204 if (operand->size == 2)
4206 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
4212 and any permutations of these. */
4213 if ((reglist & 0xfff1ffff) != 0x80010000)
4216 sregs = (reglist >> 17) & 7;
4221 /* The list must include at least one of ra and s0-sN,
4222 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
4223 which are $23 and $30 respectively.) E.g.:
4231 and any permutations of these. */
4232 if ((reglist & 0x3f00ffff) != 0)
4235 ra = (reglist >> 27) & 0x10;
4236 sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
4239 if ((sregs & -sregs) != sregs)
4242 insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra);
4246 /* OP_ENTRY_EXIT_LIST matcher. */
4249 match_entry_exit_operand (struct mips_arg_info *arg,
4250 const struct mips_operand *operand, char *s)
4253 bfd_boolean is_exit;
4255 /* The format is the same for both ENTRY and EXIT, but the constraints
4257 is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0;
4258 mask = (is_exit ? 7 << 3 : 0);
4261 unsigned int regno1, regno2;
4262 bfd_boolean is_freg;
4264 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®no1))
4266 else if (reg_lookup (&s, RTYPE_FPU, ®no1))
4271 SKIP_SPACE_TABS (s);
4275 SKIP_SPACE_TABS (s);
4276 if (!reg_lookup (&s, (is_freg ? RTYPE_FPU
4277 : RTYPE_GP | RTYPE_NUM), ®no2))
4279 SKIP_SPACE_TABS (s);
4284 if (is_exit && is_freg && regno1 == 0 && regno2 < 2)
4287 mask |= (5 + regno2) << 3;
4289 else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7)
4290 mask |= (regno2 - 3) << 3;
4291 else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17)
4292 mask |= (regno2 - 15) << 1;
4293 else if (regno1 == RA && regno2 == RA)
4304 SKIP_SPACE_TABS (s);
4306 insn_insert_operand (arg->insn, operand, mask);
4310 /* OP_SAVE_RESTORE_LIST matcher. */
4313 match_save_restore_list_operand (struct mips_arg_info *arg, char *s)
4315 unsigned int opcode, args, statics, sregs;
4316 unsigned int num_frame_sizes, num_args, num_statics, num_sregs;
4322 opcode = arg->insn->insn_opcode;
4324 num_frame_sizes = 0;
4330 unsigned int regno1, regno2;
4332 my_getExpression (&value, s);
4333 if (value.X_op == O_constant)
4335 /* Handle the frame size. */
4336 num_frame_sizes += 1;
4337 frame_size = value.X_add_number;
4339 SKIP_SPACE_TABS (s);
4343 if (!reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®no1))
4346 SKIP_SPACE_TABS (s);
4350 SKIP_SPACE_TABS (s);
4351 if (!reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®no2)
4354 SKIP_SPACE_TABS (s);
4359 while (regno1 <= regno2)
4361 if (regno1 >= 4 && regno1 <= 7)
4363 if (num_frame_sizes == 0)
4365 args |= 1 << (regno1 - 4);
4367 /* statics $a0-$a3 */
4368 statics |= 1 << (regno1 - 4);
4370 else if (regno1 >= 16 && regno1 <= 23)
4372 sregs |= 1 << (regno1 - 16);
4373 else if (regno1 == 30)
4376 else if (regno1 == 31)
4377 /* Add $ra to insn. */
4392 SKIP_SPACE_TABS (s);
4395 /* Encode args/statics combination. */
4398 else if (args == 0xf)
4399 /* All $a0-$a3 are args. */
4400 opcode |= MIPS16_ALL_ARGS << 16;
4401 else if (statics == 0xf)
4402 /* All $a0-$a3 are statics. */
4403 opcode |= MIPS16_ALL_STATICS << 16;
4406 /* Count arg registers. */
4416 /* Count static registers. */
4418 while (statics & 0x8)
4420 statics = (statics << 1) & 0xf;
4426 /* Encode args/statics. */
4427 opcode |= ((num_args << 2) | num_statics) << 16;
4430 /* Encode $s0/$s1. */
4431 if (sregs & (1 << 0)) /* $s0 */
4433 if (sregs & (1 << 1)) /* $s1 */
4437 /* Encode $s2-$s8. */
4446 opcode |= num_sregs << 24;
4448 /* Encode frame size. */
4449 if (num_frame_sizes == 0)
4450 error = _("Missing frame size");
4451 else if (num_frame_sizes > 1)
4452 error = _("Frame size specified twice");
4453 else if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8)
4454 error = _("Invalid frame size");
4455 else if (frame_size != 128 || (opcode >> 16) != 0)
4458 opcode |= (((frame_size & 0xf0) << 16)
4459 | (frame_size & 0x0f));
4464 if (arg->soft_match)
4469 /* Finally build the instruction. */
4470 if ((opcode >> 16) != 0 || frame_size == 0)
4471 opcode |= MIPS16_EXTEND;
4472 arg->insn->insn_opcode = opcode;
4476 /* OP_MDMX_IMM_REG matcher. */
4479 match_mdmx_imm_reg_operand (struct mips_arg_info *arg,
4480 const struct mips_operand *operand, char *s)
4482 unsigned int regno, uval, types;
4484 const struct mips_opcode *opcode;
4486 /* The mips_opcode records whether this is an octobyte or quadhalf
4487 instruction. Start out with that bit in place. */
4488 opcode = arg->insn->insn_mo;
4489 uval = mips_extract_operand (operand, opcode->match);
4490 is_qh = (uval != 0);
4492 types = convert_reg_type (arg->insn->insn_mo, OP_REG_VEC);
4493 if (reg_lookup (&s, types, ®no))
4495 if ((opcode->membership & INSN_5400)
4496 && strcmp (opcode->name, "rzu.ob") == 0)
4498 if (arg->soft_match)
4500 as_bad (_("Operand %d of `%s' must be an immediate"),
4501 arg->argnum, opcode->name);
4504 /* Check whether this is a vector register or a broadcast of
4505 a single element. */
4506 SKIP_SPACE_TABS (s);
4509 /* Read the element number. */
4513 SKIP_SPACE_TABS (s);
4514 my_getExpression (&value, s);
4516 if (value.X_op != O_constant
4517 || value.X_add_number < 0
4518 || value.X_add_number > (is_qh ? 3 : 7))
4520 if (arg->soft_match)
4522 as_bad (_("Invalid element selector"));
4523 value.X_add_number = 0;
4525 uval |= (unsigned int) value.X_add_number << (is_qh ? 2 : 1) << 5;
4526 SKIP_SPACE_TABS (s);
4531 if (arg->soft_match)
4533 as_bad (_("Expecting ']' found '%s'"), s);
4538 /* A full vector. */
4539 if ((opcode->membership & INSN_5400)
4540 && (strcmp (opcode->name, "sll.ob") == 0
4541 || strcmp (opcode->name, "srl.ob") == 0))
4543 if (arg->soft_match)
4545 as_bad (_("Operand %d of `%s' must be scalar"),
4546 arg->argnum, opcode->name);
4550 uval |= MDMX_FMTSEL_VEC_QH << 5;
4552 uval |= MDMX_FMTSEL_VEC_OB << 5;
4554 check_regno (arg, OP_REG_FP, regno);
4561 s = match_const_int (arg, s, &sval, 0);
4564 if (sval < 0 || sval > 31)
4566 if (arg->soft_match)
4568 report_bad_range (arg->insn, arg->argnum, sval, 0, 31, FALSE);
4570 uval |= (sval & 31);
4572 uval |= MDMX_FMTSEL_IMM_QH << 5;
4574 uval |= MDMX_FMTSEL_IMM_OB << 5;
4576 insn_insert_operand (arg->insn, operand, uval);
4580 /* OP_PC matcher. */
4583 match_pc_operand (char *s)
4585 if (strncmp (s, "$pc", 3) != 0)
4588 SKIP_SPACE_TABS (s);
4592 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
4593 register that we need to match. */
4596 match_tied_reg_operand (struct mips_arg_info *arg, char *s,
4597 unsigned int other_regno)
4601 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)
4602 || regno != other_regno)
4604 SKIP_SPACE_TABS (s);
4605 if (arg->optional_reg && *s == 0)
4610 /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
4611 the length of the value in bytes (4 for float, 8 for double) and
4612 USING_GPRS says whether the destination is a GPR rather than an FPR.
4614 Return the constant in IMM and OFFSET as follows:
4616 - If the constant should be loaded via memory, set IMM to O_absent and
4617 OFFSET to the memory address.
4619 - Otherwise, if the constant should be loaded into two 32-bit registers,
4620 set IMM to the O_constant to load into the high register and OFFSET
4621 to the corresponding value for the low register.
4623 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
4625 These constants only appear as the last operand in an instruction,
4626 and every instruction that accepts them in any variant accepts them
4627 in all variants. This means we don't have to worry about backing out
4628 any changes if the instruction does not match. We just match
4629 unconditionally and report an error if the constant is invalid. */
4632 parse_float_constant (char *s, expressionS *imm, expressionS *offset,
4633 int length, bfd_boolean using_gprs)
4635 char *save_in, *p, *err;
4636 unsigned char data[8];
4640 const char *newname;
4642 /* Where the constant is placed is based on how the MIPS assembler
4645 length == 4 && using_gprs -- immediate value only
4646 length == 8 && using_gprs -- .rdata or immediate value
4647 length == 4 && !using_gprs -- .lit4 or immediate value
4648 length == 8 && !using_gprs -- .lit8 or immediate value
4650 The .lit4 and .lit8 sections are only used if permitted by the
4652 save_in = input_line_pointer;
4653 input_line_pointer = s;
4654 err = md_atof (length == 8 ? 'd' : 'f', (char *) data, &atof_length);
4655 s = input_line_pointer;
4656 input_line_pointer = save_in;
4659 as_bad (_("Bad floating point constant: %s"), err);
4660 memset (data, '\0', sizeof (data));
4663 gas_assert (atof_length == length);
4665 /* Handle 32-bit constants for which an immediate value is best. */
4668 || g_switch_value < 4
4669 || (data[0] == 0 && data[1] == 0)
4670 || (data[2] == 0 && data[3] == 0)))
4672 imm->X_op = O_constant;
4673 if (!target_big_endian)
4674 imm->X_add_number = bfd_getl32 (data);
4676 imm->X_add_number = bfd_getb32 (data);
4677 offset->X_op = O_absent;
4681 /* Handle 64-bit constants for which an immediate value is best. */
4683 && !mips_disable_float_construction
4684 /* Constants can only be constructed in GPRs and copied
4685 to FPRs if the GPRs are at least as wide as the FPRs.
4686 Force the constant into memory if we are using 64-bit FPRs
4687 but the GPRs are only 32 bits wide. */
4688 /* ??? No longer true with the addition of MTHC1, but this
4689 is legacy code... */
4690 && (using_gprs || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
4691 && ((data[0] == 0 && data[1] == 0)
4692 || (data[2] == 0 && data[3] == 0))
4693 && ((data[4] == 0 && data[5] == 0)
4694 || (data[6] == 0 && data[7] == 0)))
4696 /* The value is simple enough to load with a couple of instructions.
4697 If using 32-bit registers, set IMM to the high order 32 bits and
4698 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
4700 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
4702 imm->X_op = O_constant;
4703 offset->X_op = O_constant;
4704 if (!target_big_endian)
4706 imm->X_add_number = bfd_getl32 (data + 4);
4707 offset->X_add_number = bfd_getl32 (data);
4711 imm->X_add_number = bfd_getb32 (data);
4712 offset->X_add_number = bfd_getb32 (data + 4);
4714 if (offset->X_add_number == 0)
4715 offset->X_op = O_absent;
4719 imm->X_op = O_constant;
4720 if (!target_big_endian)
4721 imm->X_add_number = bfd_getl64 (data);
4723 imm->X_add_number = bfd_getb64 (data);
4724 offset->X_op = O_absent;
4729 /* Switch to the right section. */
4731 subseg = now_subseg;
4734 gas_assert (!using_gprs && g_switch_value >= 4);
4739 if (using_gprs || g_switch_value < 8)
4740 newname = RDATA_SECTION_NAME;
4745 new_seg = subseg_new (newname, (subsegT) 0);
4746 bfd_set_section_flags (stdoutput, new_seg,
4747 SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA);
4748 frag_align (length == 4 ? 2 : 3, 0, 0);
4749 if (strncmp (TARGET_OS, "elf", 3) != 0)
4750 record_alignment (new_seg, 4);
4752 record_alignment (new_seg, length == 4 ? 2 : 3);
4754 as_bad (_("Can't use floating point insn in this section"));
4756 /* Set the argument to the current address in the section. */
4757 imm->X_op = O_absent;
4758 offset->X_op = O_symbol;
4759 offset->X_add_symbol = symbol_temp_new_now ();
4760 offset->X_add_number = 0;
4762 /* Put the floating point number into the section. */
4763 p = frag_more (length);
4764 memcpy (p, data, length);
4766 /* Switch back to the original section. */
4767 subseg_set (seg, subseg);
4771 /* S is the text seen for ARG. Match it against OPERAND. Return the end
4772 of the argument text if the match is successful, otherwise return null. */
4775 match_operand (struct mips_arg_info *arg,
4776 const struct mips_operand *operand, char *s)
4778 switch (operand->type)
4781 return match_int_operand (arg, operand, s);
4784 return match_mapped_int_operand (arg, operand, s);
4787 return match_msb_operand (arg, operand, s);
4790 return match_reg_operand (arg, operand, s);
4793 return match_reg_pair_operand (arg, operand, s);
4796 return match_pcrel_operand (s);
4799 return match_perf_reg_operand (arg, operand, s);
4801 case OP_ADDIUSP_INT:
4802 return match_addiusp_operand (arg, operand, s);
4804 case OP_CLO_CLZ_DEST:
4805 return match_clo_clz_dest_operand (arg, operand, s);
4807 case OP_LWM_SWM_LIST:
4808 return match_lwm_swm_list_operand (arg, operand, s);
4810 case OP_ENTRY_EXIT_LIST:
4811 return match_entry_exit_operand (arg, operand, s);
4813 case OP_SAVE_RESTORE_LIST:
4814 return match_save_restore_list_operand (arg, s);
4816 case OP_MDMX_IMM_REG:
4817 return match_mdmx_imm_reg_operand (arg, operand, s);
4819 case OP_REPEAT_DEST_REG:
4820 return match_tied_reg_operand (arg, s, arg->dest_regno);
4822 case OP_REPEAT_PREV_REG:
4823 return match_tied_reg_operand (arg, s, arg->last_regno);
4826 return match_pc_operand (s);
4831 /* ARG is the state after successfully matching an instruction.
4832 Issue any queued-up warnings. */
4835 check_completed_insn (struct mips_arg_info *arg)
4840 as_warn (_("Used $at without \".set noat\""));
4842 as_warn (_("Used $%u with \".set at=$%u\""), AT, AT);
4846 /* Classify an instruction according to the FIX_VR4120_* enumeration.
4847 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
4848 by VR4120 errata. */
4851 classify_vr4120_insn (const char *name)
4853 if (strncmp (name, "macc", 4) == 0)
4854 return FIX_VR4120_MACC;
4855 if (strncmp (name, "dmacc", 5) == 0)
4856 return FIX_VR4120_DMACC;
4857 if (strncmp (name, "mult", 4) == 0)
4858 return FIX_VR4120_MULT;
4859 if (strncmp (name, "dmult", 5) == 0)
4860 return FIX_VR4120_DMULT;
4861 if (strstr (name, "div"))
4862 return FIX_VR4120_DIV;
4863 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
4864 return FIX_VR4120_MTHILO;
4865 return NUM_FIX_VR4120_CLASSES;
4868 #define INSN_ERET 0x42000018
4869 #define INSN_DERET 0x4200001f
4871 /* Return the number of instructions that must separate INSN1 and INSN2,
4872 where INSN1 is the earlier instruction. Return the worst-case value
4873 for any INSN2 if INSN2 is null. */
4876 insns_between (const struct mips_cl_insn *insn1,
4877 const struct mips_cl_insn *insn2)
4879 unsigned long pinfo1, pinfo2;
4882 /* This function needs to know which pinfo flags are set for INSN2
4883 and which registers INSN2 uses. The former is stored in PINFO2 and
4884 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
4885 will have every flag set and INSN2_USES_GPR will always return true. */
4886 pinfo1 = insn1->insn_mo->pinfo;
4887 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
4889 #define INSN2_USES_GPR(REG) \
4890 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
4892 /* For most targets, write-after-read dependencies on the HI and LO
4893 registers must be separated by at least two instructions. */
4894 if (!hilo_interlocks)
4896 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
4898 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
4902 /* If we're working around r7000 errata, there must be two instructions
4903 between an mfhi or mflo and any instruction that uses the result. */
4904 if (mips_7000_hilo_fix
4905 && !mips_opts.micromips
4906 && MF_HILO_INSN (pinfo1)
4907 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1)))
4910 /* If we're working around 24K errata, one instruction is required
4911 if an ERET or DERET is followed by a branch instruction. */
4912 if (mips_fix_24k && !mips_opts.micromips)
4914 if (insn1->insn_opcode == INSN_ERET
4915 || insn1->insn_opcode == INSN_DERET)
4918 || insn2->insn_opcode == INSN_ERET
4919 || insn2->insn_opcode == INSN_DERET
4920 || delayed_branch_p (insn2))
4925 /* If working around VR4120 errata, check for combinations that need
4926 a single intervening instruction. */
4927 if (mips_fix_vr4120 && !mips_opts.micromips)
4929 unsigned int class1, class2;
4931 class1 = classify_vr4120_insn (insn1->insn_mo->name);
4932 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
4936 class2 = classify_vr4120_insn (insn2->insn_mo->name);
4937 if (vr4120_conflicts[class1] & (1 << class2))
4942 if (!HAVE_CODE_COMPRESSION)
4944 /* Check for GPR or coprocessor load delays. All such delays
4945 are on the RT register. */
4946 /* Itbl support may require additional care here. */
4947 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
4948 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
4950 know (pinfo1 & INSN_WRITE_GPR_T);
4951 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1)))
4955 /* Check for generic coprocessor hazards.
4957 This case is not handled very well. There is no special
4958 knowledge of CP0 handling, and the coprocessors other than
4959 the floating point unit are not distinguished at all. */
4960 /* Itbl support may require additional care here. FIXME!
4961 Need to modify this to include knowledge about
4962 user specified delays! */
4963 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
4964 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
4966 /* Handle cases where INSN1 writes to a known general coprocessor
4967 register. There must be a one instruction delay before INSN2
4968 if INSN2 reads that register, otherwise no delay is needed. */
4969 mask = fpr_write_mask (insn1);
4972 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
4977 /* Read-after-write dependencies on the control registers
4978 require a two-instruction gap. */
4979 if ((pinfo1 & INSN_WRITE_COND_CODE)
4980 && (pinfo2 & INSN_READ_COND_CODE))
4983 /* We don't know exactly what INSN1 does. If INSN2 is
4984 also a coprocessor instruction, assume there must be
4985 a one instruction gap. */
4986 if (pinfo2 & INSN_COP)
4991 /* Check for read-after-write dependencies on the coprocessor
4992 control registers in cases where INSN1 does not need a general
4993 coprocessor delay. This means that INSN1 is a floating point
4994 comparison instruction. */
4995 /* Itbl support may require additional care here. */
4996 else if (!cop_interlocks
4997 && (pinfo1 & INSN_WRITE_COND_CODE)
4998 && (pinfo2 & INSN_READ_COND_CODE))
5002 #undef INSN2_USES_GPR
5007 /* Return the number of nops that would be needed to work around the
5008 VR4130 mflo/mfhi errata if instruction INSN immediately followed
5009 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
5010 that are contained within the first IGNORE instructions of HIST. */
5013 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
5014 const struct mips_cl_insn *insn)
5019 /* Check if the instruction writes to HI or LO. MTHI and MTLO
5020 are not affected by the errata. */
5022 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
5023 || strcmp (insn->insn_mo->name, "mtlo") == 0
5024 || strcmp (insn->insn_mo->name, "mthi") == 0))
5027 /* Search for the first MFLO or MFHI. */
5028 for (i = 0; i < MAX_VR4130_NOPS; i++)
5029 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
5031 /* Extract the destination register. */
5032 mask = gpr_write_mask (&hist[i]);
5034 /* No nops are needed if INSN reads that register. */
5035 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
5038 /* ...or if any of the intervening instructions do. */
5039 for (j = 0; j < i; j++)
5040 if (gpr_read_mask (&hist[j]) & mask)
5044 return MAX_VR4130_NOPS - i;
5049 #define BASE_REG_EQ(INSN1, INSN2) \
5050 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
5051 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
5053 /* Return the minimum alignment for this store instruction. */
5056 fix_24k_align_to (const struct mips_opcode *mo)
5058 if (strcmp (mo->name, "sh") == 0)
5061 if (strcmp (mo->name, "swc1") == 0
5062 || strcmp (mo->name, "swc2") == 0
5063 || strcmp (mo->name, "sw") == 0
5064 || strcmp (mo->name, "sc") == 0
5065 || strcmp (mo->name, "s.s") == 0)
5068 if (strcmp (mo->name, "sdc1") == 0
5069 || strcmp (mo->name, "sdc2") == 0
5070 || strcmp (mo->name, "s.d") == 0)
5077 struct fix_24k_store_info
5079 /* Immediate offset, if any, for this store instruction. */
5081 /* Alignment required by this store instruction. */
5083 /* True for register offsets. */
5084 int register_offset;
5087 /* Comparison function used by qsort. */
5090 fix_24k_sort (const void *a, const void *b)
5092 const struct fix_24k_store_info *pos1 = a;
5093 const struct fix_24k_store_info *pos2 = b;
5095 return (pos1->off - pos2->off);
5098 /* INSN is a store instruction. Try to record the store information
5099 in STINFO. Return false if the information isn't known. */
5102 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
5103 const struct mips_cl_insn *insn)
5105 /* The instruction must have a known offset. */
5106 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
5109 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
5110 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
5114 /* Return the number of nops that would be needed to work around the 24k
5115 "lost data on stores during refill" errata if instruction INSN
5116 immediately followed the 2 instructions described by HIST.
5117 Ignore hazards that are contained within the first IGNORE
5118 instructions of HIST.
5120 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
5121 for the data cache refills and store data. The following describes
5122 the scenario where the store data could be lost.
5124 * A data cache miss, due to either a load or a store, causing fill
5125 data to be supplied by the memory subsystem
5126 * The first three doublewords of fill data are returned and written
5128 * A sequence of four stores occurs in consecutive cycles around the
5129 final doubleword of the fill:
5133 * Zero, One or more instructions
5136 The four stores A-D must be to different doublewords of the line that
5137 is being filled. The fourth instruction in the sequence above permits
5138 the fill of the final doubleword to be transferred from the FSB into
5139 the cache. In the sequence above, the stores may be either integer
5140 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
5141 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
5142 different doublewords on the line. If the floating point unit is
5143 running in 1:2 mode, it is not possible to create the sequence above
5144 using only floating point store instructions.
5146 In this case, the cache line being filled is incorrectly marked
5147 invalid, thereby losing the data from any store to the line that
5148 occurs between the original miss and the completion of the five
5149 cycle sequence shown above.
5151 The workarounds are:
5153 * Run the data cache in write-through mode.
5154 * Insert a non-store instruction between
5155 Store A and Store B or Store B and Store C. */
5158 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
5159 const struct mips_cl_insn *insn)
5161 struct fix_24k_store_info pos[3];
5162 int align, i, base_offset;
5167 /* If the previous instruction wasn't a store, there's nothing to
5169 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
5172 /* If the instructions after the previous one are unknown, we have
5173 to assume the worst. */
5177 /* Check whether we are dealing with three consecutive stores. */
5178 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
5179 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
5182 /* If we don't know the relationship between the store addresses,
5183 assume the worst. */
5184 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
5185 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
5188 if (!fix_24k_record_store_info (&pos[0], insn)
5189 || !fix_24k_record_store_info (&pos[1], &hist[0])
5190 || !fix_24k_record_store_info (&pos[2], &hist[1]))
5193 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
5195 /* Pick a value of ALIGN and X such that all offsets are adjusted by
5196 X bytes and such that the base register + X is known to be aligned
5199 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
5203 align = pos[0].align_to;
5204 base_offset = pos[0].off;
5205 for (i = 1; i < 3; i++)
5206 if (align < pos[i].align_to)
5208 align = pos[i].align_to;
5209 base_offset = pos[i].off;
5211 for (i = 0; i < 3; i++)
5212 pos[i].off -= base_offset;
5215 pos[0].off &= ~align + 1;
5216 pos[1].off &= ~align + 1;
5217 pos[2].off &= ~align + 1;
5219 /* If any two stores write to the same chunk, they also write to the
5220 same doubleword. The offsets are still sorted at this point. */
5221 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
5224 /* A range of at least 9 bytes is needed for the stores to be in
5225 non-overlapping doublewords. */
5226 if (pos[2].off - pos[0].off <= 8)
5229 if (pos[2].off - pos[1].off >= 24
5230 || pos[1].off - pos[0].off >= 24
5231 || pos[2].off - pos[0].off >= 32)
5237 /* Return the number of nops that would be needed if instruction INSN
5238 immediately followed the MAX_NOPS instructions given by HIST,
5239 where HIST[0] is the most recent instruction. Ignore hazards
5240 between INSN and the first IGNORE instructions in HIST.
5242 If INSN is null, return the worse-case number of nops for any
5246 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
5247 const struct mips_cl_insn *insn)
5249 int i, nops, tmp_nops;
5252 for (i = ignore; i < MAX_DELAY_NOPS; i++)
5254 tmp_nops = insns_between (hist + i, insn) - i;
5255 if (tmp_nops > nops)
5259 if (mips_fix_vr4130 && !mips_opts.micromips)
5261 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
5262 if (tmp_nops > nops)
5266 if (mips_fix_24k && !mips_opts.micromips)
5268 tmp_nops = nops_for_24k (ignore, hist, insn);
5269 if (tmp_nops > nops)
5276 /* The variable arguments provide NUM_INSNS extra instructions that
5277 might be added to HIST. Return the largest number of nops that
5278 would be needed after the extended sequence, ignoring hazards
5279 in the first IGNORE instructions. */
5282 nops_for_sequence (int num_insns, int ignore,
5283 const struct mips_cl_insn *hist, ...)
5286 struct mips_cl_insn buffer[MAX_NOPS];
5287 struct mips_cl_insn *cursor;
5290 va_start (args, hist);
5291 cursor = buffer + num_insns;
5292 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
5293 while (cursor > buffer)
5294 *--cursor = *va_arg (args, const struct mips_cl_insn *);
5296 nops = nops_for_insn (ignore, buffer, NULL);
5301 /* Like nops_for_insn, but if INSN is a branch, take into account the
5302 worst-case delay for the branch target. */
5305 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
5306 const struct mips_cl_insn *insn)
5310 nops = nops_for_insn (ignore, hist, insn);
5311 if (delayed_branch_p (insn))
5313 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
5314 hist, insn, get_delay_slot_nop (insn));
5315 if (tmp_nops > nops)
5318 else if (compact_branch_p (insn))
5320 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
5321 if (tmp_nops > nops)
5327 /* Fix NOP issue: Replace nops by "or at,at,zero". */
5330 fix_loongson2f_nop (struct mips_cl_insn * ip)
5332 gas_assert (!HAVE_CODE_COMPRESSION);
5333 if (strcmp (ip->insn_mo->name, "nop") == 0)
5334 ip->insn_opcode = LOONGSON2F_NOP_INSN;
5337 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
5338 jr target pc &= 'hffff_ffff_cfff_ffff. */
5341 fix_loongson2f_jump (struct mips_cl_insn * ip)
5343 gas_assert (!HAVE_CODE_COMPRESSION);
5344 if (strcmp (ip->insn_mo->name, "j") == 0
5345 || strcmp (ip->insn_mo->name, "jr") == 0
5346 || strcmp (ip->insn_mo->name, "jalr") == 0)
5354 sreg = EXTRACT_OPERAND (0, RS, *ip);
5355 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
5358 ep.X_op = O_constant;
5359 ep.X_add_number = 0xcfff0000;
5360 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
5361 ep.X_add_number = 0xffff;
5362 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
5363 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
5368 fix_loongson2f (struct mips_cl_insn * ip)
5370 if (mips_fix_loongson2f_nop)
5371 fix_loongson2f_nop (ip);
5373 if (mips_fix_loongson2f_jump)
5374 fix_loongson2f_jump (ip);
5377 /* IP is a branch that has a delay slot, and we need to fill it
5378 automatically. Return true if we can do that by swapping IP
5379 with the previous instruction.
5380 ADDRESS_EXPR is an operand of the instruction to be used with
5384 can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
5385 bfd_reloc_code_real_type *reloc_type)
5387 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
5388 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
5390 /* -O2 and above is required for this optimization. */
5391 if (mips_optimize < 2)
5394 /* If we have seen .set volatile or .set nomove, don't optimize. */
5395 if (mips_opts.nomove)
5398 /* We can't swap if the previous instruction's position is fixed. */
5399 if (history[0].fixed_p)
5402 /* If the previous previous insn was in a .set noreorder, we can't
5403 swap. Actually, the MIPS assembler will swap in this situation.
5404 However, gcc configured -with-gnu-as will generate code like
5412 in which we can not swap the bne and INSN. If gcc is not configured
5413 -with-gnu-as, it does not output the .set pseudo-ops. */
5414 if (history[1].noreorder_p)
5417 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
5418 This means that the previous instruction was a 4-byte one anyhow. */
5419 if (mips_opts.mips16 && history[0].fixp[0])
5422 /* If the branch is itself the target of a branch, we can not swap.
5423 We cheat on this; all we check for is whether there is a label on
5424 this instruction. If there are any branches to anything other than
5425 a label, users must use .set noreorder. */
5426 if (seg_info (now_seg)->label_list)
5429 /* If the previous instruction is in a variant frag other than this
5430 branch's one, we cannot do the swap. This does not apply to
5431 MIPS16 code, which uses variant frags for different purposes. */
5432 if (!mips_opts.mips16
5434 && history[0].frag->fr_type == rs_machine_dependent)
5437 /* We do not swap with instructions that cannot architecturally
5438 be placed in a branch delay slot, such as SYNC or ERET. We
5439 also refrain from swapping with a trap instruction, since it
5440 complicates trap handlers to have the trap instruction be in
5442 prev_pinfo = history[0].insn_mo->pinfo;
5443 if (prev_pinfo & INSN_NO_DELAY_SLOT)
5446 /* Check for conflicts between the branch and the instructions
5447 before the candidate delay slot. */
5448 if (nops_for_insn (0, history + 1, ip) > 0)
5451 /* Check for conflicts between the swapped sequence and the
5452 target of the branch. */
5453 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
5456 /* If the branch reads a register that the previous
5457 instruction sets, we can not swap. */
5458 gpr_read = gpr_read_mask (ip);
5459 prev_gpr_write = gpr_write_mask (&history[0]);
5460 if (gpr_read & prev_gpr_write)
5463 /* If the branch writes a register that the previous
5464 instruction sets, we can not swap. */
5465 gpr_write = gpr_write_mask (ip);
5466 if (gpr_write & prev_gpr_write)
5469 /* If the branch writes a register that the previous
5470 instruction reads, we can not swap. */
5471 prev_gpr_read = gpr_read_mask (&history[0]);
5472 if (gpr_write & prev_gpr_read)
5475 /* If one instruction sets a condition code and the
5476 other one uses a condition code, we can not swap. */
5477 pinfo = ip->insn_mo->pinfo;
5478 if ((pinfo & INSN_READ_COND_CODE)
5479 && (prev_pinfo & INSN_WRITE_COND_CODE))
5481 if ((pinfo & INSN_WRITE_COND_CODE)
5482 && (prev_pinfo & INSN_READ_COND_CODE))
5485 /* If the previous instruction uses the PC, we can not swap. */
5486 prev_pinfo2 = history[0].insn_mo->pinfo2;
5487 if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC))
5489 if (mips_opts.micromips && (prev_pinfo2 & INSN2_READ_PC))
5492 /* If the previous instruction has an incorrect size for a fixed
5493 branch delay slot in microMIPS mode, we cannot swap. */
5494 pinfo2 = ip->insn_mo->pinfo2;
5495 if (mips_opts.micromips
5496 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
5497 && insn_length (history) != 2)
5499 if (mips_opts.micromips
5500 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
5501 && insn_length (history) != 4)
5504 /* On R5900 short loops need to be fixed by inserting a nop in
5505 the branch delay slots.
5506 A short loop can be terminated too early. */
5507 if (mips_opts.arch == CPU_R5900
5508 /* Check if instruction has a parameter, ignore "j $31". */
5509 && (address_expr != NULL)
5510 /* Parameter must be 16 bit. */
5511 && (*reloc_type == BFD_RELOC_16_PCREL_S2)
5512 /* Branch to same segment. */
5513 && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg)
5514 /* Branch to same code fragment. */
5515 && (symbol_get_frag(address_expr->X_add_symbol) == frag_now)
5516 /* Can only calculate branch offset if value is known. */
5517 && symbol_constant_p(address_expr->X_add_symbol)
5518 /* Check if branch is really conditional. */
5519 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */
5520 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */
5521 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
5524 /* Check if loop is shorter than 6 instructions including
5525 branch and delay slot. */
5526 distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol);
5533 /* When the loop includes branches or jumps,
5534 it is not a short loop. */
5535 for (i = 0; i < (distance / 4); i++)
5537 if ((history[i].cleared_p)
5538 || delayed_branch_p(&history[i]))
5546 /* Insert nop after branch to fix short loop. */
5555 /* Decide how we should add IP to the instruction stream.
5556 ADDRESS_EXPR is an operand of the instruction to be used with
5559 static enum append_method
5560 get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
5561 bfd_reloc_code_real_type *reloc_type)
5563 unsigned long pinfo;
5565 /* The relaxed version of a macro sequence must be inherently
5567 if (mips_relax.sequence == 2)
5570 /* We must not dabble with instructions in a ".set norerorder" block. */
5571 if (mips_opts.noreorder)
5574 /* Otherwise, it's our responsibility to fill branch delay slots. */
5575 if (delayed_branch_p (ip))
5577 if (!branch_likely_p (ip)
5578 && can_swap_branch_p (ip, address_expr, reloc_type))
5581 pinfo = ip->insn_mo->pinfo;
5582 if (mips_opts.mips16
5583 && ISA_SUPPORTS_MIPS16E
5584 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)))
5585 return APPEND_ADD_COMPACT;
5587 return APPEND_ADD_WITH_NOP;
5593 /* IP is a MIPS16 instruction whose opcode we have just changed.
5594 Point IP->insn_mo to the new opcode's definition. */
5597 find_altered_mips16_opcode (struct mips_cl_insn *ip)
5599 const struct mips_opcode *mo, *end;
5601 end = &mips16_opcodes[bfd_mips16_num_opcodes];
5602 for (mo = ip->insn_mo; mo < end; mo++)
5603 if ((ip->insn_opcode & mo->mask) == mo->match)
5611 /* For microMIPS macros, we need to generate a local number label
5612 as the target of branches. */
5613 #define MICROMIPS_LABEL_CHAR '\037'
5614 static unsigned long micromips_target_label;
5615 static char micromips_target_name[32];
5618 micromips_label_name (void)
5620 char *p = micromips_target_name;
5621 char symbol_name_temporary[24];
5629 l = micromips_target_label;
5630 #ifdef LOCAL_LABEL_PREFIX
5631 *p++ = LOCAL_LABEL_PREFIX;
5634 *p++ = MICROMIPS_LABEL_CHAR;
5637 symbol_name_temporary[i++] = l % 10 + '0';
5642 *p++ = symbol_name_temporary[--i];
5645 return micromips_target_name;
5649 micromips_label_expr (expressionS *label_expr)
5651 label_expr->X_op = O_symbol;
5652 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
5653 label_expr->X_add_number = 0;
5657 micromips_label_inc (void)
5659 micromips_target_label++;
5660 *micromips_target_name = '\0';
5664 micromips_add_label (void)
5668 s = colon (micromips_label_name ());
5669 micromips_label_inc ();
5670 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
5673 /* If assembling microMIPS code, then return the microMIPS reloc
5674 corresponding to the requested one if any. Otherwise return
5675 the reloc unchanged. */
5677 static bfd_reloc_code_real_type
5678 micromips_map_reloc (bfd_reloc_code_real_type reloc)
5680 static const bfd_reloc_code_real_type relocs[][2] =
5682 /* Keep sorted incrementally by the left-hand key. */
5683 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
5684 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
5685 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
5686 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
5687 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
5688 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
5689 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
5690 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
5691 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
5692 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
5693 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
5694 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
5695 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
5696 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
5697 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
5698 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
5699 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
5700 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
5701 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
5702 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
5703 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
5704 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
5705 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
5706 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
5707 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
5708 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
5709 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
5711 bfd_reloc_code_real_type r;
5714 if (!mips_opts.micromips)
5716 for (i = 0; i < ARRAY_SIZE (relocs); i++)
5722 return relocs[i][1];
5727 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
5728 Return true on success, storing the resolved value in RESULT. */
5731 calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
5736 case BFD_RELOC_MIPS_HIGHEST:
5737 case BFD_RELOC_MICROMIPS_HIGHEST:
5738 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff;
5741 case BFD_RELOC_MIPS_HIGHER:
5742 case BFD_RELOC_MICROMIPS_HIGHER:
5743 *result = ((operand + 0x80008000ull) >> 32) & 0xffff;
5746 case BFD_RELOC_HI16_S:
5747 case BFD_RELOC_MICROMIPS_HI16_S:
5748 case BFD_RELOC_MIPS16_HI16_S:
5749 *result = ((operand + 0x8000) >> 16) & 0xffff;
5752 case BFD_RELOC_HI16:
5753 case BFD_RELOC_MICROMIPS_HI16:
5754 case BFD_RELOC_MIPS16_HI16:
5755 *result = (operand >> 16) & 0xffff;
5758 case BFD_RELOC_LO16:
5759 case BFD_RELOC_MICROMIPS_LO16:
5760 case BFD_RELOC_MIPS16_LO16:
5761 *result = operand & 0xffff;
5764 case BFD_RELOC_UNUSED:
5773 /* Output an instruction. IP is the instruction information.
5774 ADDRESS_EXPR is an operand of the instruction to be used with
5775 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
5776 a macro expansion. */
5779 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
5780 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
5782 unsigned long prev_pinfo2, pinfo;
5783 bfd_boolean relaxed_branch = FALSE;
5784 enum append_method method;
5785 bfd_boolean relax32;
5788 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
5789 fix_loongson2f (ip);
5791 file_ase_mips16 |= mips_opts.mips16;
5792 file_ase_micromips |= mips_opts.micromips;
5794 prev_pinfo2 = history[0].insn_mo->pinfo2;
5795 pinfo = ip->insn_mo->pinfo;
5797 if (mips_opts.micromips
5799 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
5800 && micromips_insn_length (ip->insn_mo) != 2)
5801 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
5802 && micromips_insn_length (ip->insn_mo) != 4)))
5803 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
5804 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
5806 if (address_expr == NULL)
5808 else if (reloc_type[0] <= BFD_RELOC_UNUSED
5809 && reloc_type[1] == BFD_RELOC_UNUSED
5810 && reloc_type[2] == BFD_RELOC_UNUSED
5811 && address_expr->X_op == O_constant)
5813 switch (*reloc_type)
5815 case BFD_RELOC_MIPS_JMP:
5819 shift = mips_opts.micromips ? 1 : 2;
5820 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
5821 as_bad (_("jump to misaligned address (0x%lx)"),
5822 (unsigned long) address_expr->X_add_number);
5823 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
5829 case BFD_RELOC_MIPS16_JMP:
5830 if ((address_expr->X_add_number & 3) != 0)
5831 as_bad (_("jump to misaligned address (0x%lx)"),
5832 (unsigned long) address_expr->X_add_number);
5834 (((address_expr->X_add_number & 0x7c0000) << 3)
5835 | ((address_expr->X_add_number & 0xf800000) >> 7)
5836 | ((address_expr->X_add_number & 0x3fffc) >> 2));
5840 case BFD_RELOC_16_PCREL_S2:
5844 shift = mips_opts.micromips ? 1 : 2;
5845 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
5846 as_bad (_("branch to misaligned address (0x%lx)"),
5847 (unsigned long) address_expr->X_add_number);
5848 if (!mips_relax_branch)
5850 if ((address_expr->X_add_number + (1 << (shift + 15)))
5851 & ~((1 << (shift + 16)) - 1))
5852 as_bad (_("branch address range overflow (0x%lx)"),
5853 (unsigned long) address_expr->X_add_number);
5854 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
5864 if (calculate_reloc (*reloc_type, address_expr->X_add_number,
5867 ip->insn_opcode |= value & 0xffff;
5875 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
5877 /* There are a lot of optimizations we could do that we don't.
5878 In particular, we do not, in general, reorder instructions.
5879 If you use gcc with optimization, it will reorder
5880 instructions and generally do much more optimization then we
5881 do here; repeating all that work in the assembler would only
5882 benefit hand written assembly code, and does not seem worth
5884 int nops = (mips_optimize == 0
5885 ? nops_for_insn (0, history, NULL)
5886 : nops_for_insn_or_target (0, history, ip));
5890 unsigned long old_frag_offset;
5893 old_frag = frag_now;
5894 old_frag_offset = frag_now_fix ();
5896 for (i = 0; i < nops; i++)
5897 add_fixed_insn (NOP_INSN);
5898 insert_into_history (0, nops, NOP_INSN);
5902 listing_prev_line ();
5903 /* We may be at the start of a variant frag. In case we
5904 are, make sure there is enough space for the frag
5905 after the frags created by listing_prev_line. The
5906 argument to frag_grow here must be at least as large
5907 as the argument to all other calls to frag_grow in
5908 this file. We don't have to worry about being in the
5909 middle of a variant frag, because the variants insert
5910 all needed nop instructions themselves. */
5914 mips_move_text_labels ();
5916 #ifndef NO_ECOFF_DEBUGGING
5917 if (ECOFF_DEBUGGING)
5918 ecoff_fix_loc (old_frag, old_frag_offset);
5922 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
5926 /* Work out how many nops in prev_nop_frag are needed by IP,
5927 ignoring hazards generated by the first prev_nop_frag_since
5929 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
5930 gas_assert (nops <= prev_nop_frag_holds);
5932 /* Enforce NOPS as a minimum. */
5933 if (nops > prev_nop_frag_required)
5934 prev_nop_frag_required = nops;
5936 if (prev_nop_frag_holds == prev_nop_frag_required)
5938 /* Settle for the current number of nops. Update the history
5939 accordingly (for the benefit of any future .set reorder code). */
5940 prev_nop_frag = NULL;
5941 insert_into_history (prev_nop_frag_since,
5942 prev_nop_frag_holds, NOP_INSN);
5946 /* Allow this instruction to replace one of the nops that was
5947 tentatively added to prev_nop_frag. */
5948 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
5949 prev_nop_frag_holds--;
5950 prev_nop_frag_since++;
5954 method = get_append_method (ip, address_expr, reloc_type);
5955 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
5957 dwarf2_emit_insn (0);
5958 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
5959 so "move" the instruction address accordingly.
5961 Also, it doesn't seem appropriate for the assembler to reorder .loc
5962 entries. If this instruction is a branch that we are going to swap
5963 with the previous instruction, the two instructions should be
5964 treated as a unit, and the debug information for both instructions
5965 should refer to the start of the branch sequence. Using the
5966 current position is certainly wrong when swapping a 32-bit branch
5967 and a 16-bit delay slot, since the current position would then be
5968 in the middle of a branch. */
5969 dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp);
5971 relax32 = (mips_relax_branch
5972 /* Don't try branch relaxation within .set nomacro, or within
5973 .set noat if we use $at for PIC computations. If it turns
5974 out that the branch was out-of-range, we'll get an error. */
5975 && !mips_opts.warn_about_macros
5976 && (mips_opts.at || mips_pic == NO_PIC)
5977 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
5978 as they have no complementing branches. */
5979 && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP)));
5981 if (!HAVE_CODE_COMPRESSION
5984 && *reloc_type == BFD_RELOC_16_PCREL_S2
5985 && delayed_branch_p (ip))
5987 relaxed_branch = TRUE;
5988 add_relaxed_insn (ip, (relaxed_branch_length
5990 uncond_branch_p (ip) ? -1
5991 : branch_likely_p (ip) ? 1
5995 uncond_branch_p (ip),
5996 branch_likely_p (ip),
5997 pinfo & INSN_WRITE_GPR_31,
5999 address_expr->X_add_symbol,
6000 address_expr->X_add_number);
6001 *reloc_type = BFD_RELOC_UNUSED;
6003 else if (mips_opts.micromips
6005 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
6006 || *reloc_type > BFD_RELOC_UNUSED)
6007 && (delayed_branch_p (ip) || compact_branch_p (ip))
6008 /* Don't try branch relaxation when users specify
6009 16-bit/32-bit instructions. */
6010 && !forced_insn_length)
6012 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
6013 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
6014 int uncond = uncond_branch_p (ip) ? -1 : 0;
6015 int compact = compact_branch_p (ip);
6016 int al = pinfo & INSN_WRITE_GPR_31;
6019 gas_assert (address_expr != NULL);
6020 gas_assert (!mips_relax.sequence);
6022 relaxed_branch = TRUE;
6023 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
6024 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
6025 RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al,
6027 address_expr->X_add_symbol,
6028 address_expr->X_add_number);
6029 *reloc_type = BFD_RELOC_UNUSED;
6031 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
6033 /* We need to set up a variant frag. */
6034 gas_assert (address_expr != NULL);
6035 add_relaxed_insn (ip, 4, 0,
6037 (*reloc_type - BFD_RELOC_UNUSED,
6038 forced_insn_length == 2, forced_insn_length == 4,
6039 delayed_branch_p (&history[0]),
6040 history[0].mips16_absolute_jump_p),
6041 make_expr_symbol (address_expr), 0);
6043 else if (mips_opts.mips16 && insn_length (ip) == 2)
6045 if (!delayed_branch_p (ip))
6046 /* Make sure there is enough room to swap this instruction with
6047 a following jump instruction. */
6049 add_fixed_insn (ip);
6053 if (mips_opts.mips16
6054 && mips_opts.noreorder
6055 && delayed_branch_p (&history[0]))
6056 as_warn (_("extended instruction in delay slot"));
6058 if (mips_relax.sequence)
6060 /* If we've reached the end of this frag, turn it into a variant
6061 frag and record the information for the instructions we've
6063 if (frag_room () < 4)
6064 relax_close_frag ();
6065 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
6068 if (mips_relax.sequence != 2)
6070 if (mips_macro_warning.first_insn_sizes[0] == 0)
6071 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
6072 mips_macro_warning.sizes[0] += insn_length (ip);
6073 mips_macro_warning.insns[0]++;
6075 if (mips_relax.sequence != 1)
6077 if (mips_macro_warning.first_insn_sizes[1] == 0)
6078 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
6079 mips_macro_warning.sizes[1] += insn_length (ip);
6080 mips_macro_warning.insns[1]++;
6083 if (mips_opts.mips16)
6086 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
6088 add_fixed_insn (ip);
6091 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
6093 bfd_reloc_code_real_type final_type[3];
6094 reloc_howto_type *howto0;
6095 reloc_howto_type *howto;
6098 /* Perform any necessary conversion to microMIPS relocations
6099 and find out how many relocations there actually are. */
6100 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
6101 final_type[i] = micromips_map_reloc (reloc_type[i]);
6103 /* In a compound relocation, it is the final (outermost)
6104 operator that determines the relocated field. */
6105 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
6110 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
6111 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
6112 bfd_get_reloc_size (howto),
6114 howto0 && howto0->pc_relative,
6117 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
6118 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
6119 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
6121 /* These relocations can have an addend that won't fit in
6122 4 octets for 64bit assembly. */
6124 && ! howto->partial_inplace
6125 && (reloc_type[0] == BFD_RELOC_16
6126 || reloc_type[0] == BFD_RELOC_32
6127 || reloc_type[0] == BFD_RELOC_MIPS_JMP
6128 || reloc_type[0] == BFD_RELOC_GPREL16
6129 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
6130 || reloc_type[0] == BFD_RELOC_GPREL32
6131 || reloc_type[0] == BFD_RELOC_64
6132 || reloc_type[0] == BFD_RELOC_CTOR
6133 || reloc_type[0] == BFD_RELOC_MIPS_SUB
6134 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
6135 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
6136 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
6137 || reloc_type[0] == BFD_RELOC_MIPS_REL16
6138 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
6139 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
6140 || hi16_reloc_p (reloc_type[0])
6141 || lo16_reloc_p (reloc_type[0])))
6142 ip->fixp[0]->fx_no_overflow = 1;
6144 /* These relocations can have an addend that won't fit in 2 octets. */
6145 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
6146 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1)
6147 ip->fixp[0]->fx_no_overflow = 1;
6149 if (mips_relax.sequence)
6151 if (mips_relax.first_fixup == 0)
6152 mips_relax.first_fixup = ip->fixp[0];
6154 else if (reloc_needs_lo_p (*reloc_type))
6156 struct mips_hi_fixup *hi_fixup;
6158 /* Reuse the last entry if it already has a matching %lo. */
6159 hi_fixup = mips_hi_fixup_list;
6161 || !fixup_has_matching_lo_p (hi_fixup->fixp))
6163 hi_fixup = ((struct mips_hi_fixup *)
6164 xmalloc (sizeof (struct mips_hi_fixup)));
6165 hi_fixup->next = mips_hi_fixup_list;
6166 mips_hi_fixup_list = hi_fixup;
6168 hi_fixup->fixp = ip->fixp[0];
6169 hi_fixup->seg = now_seg;
6172 /* Add fixups for the second and third relocations, if given.
6173 Note that the ABI allows the second relocation to be
6174 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
6175 moment we only use RSS_UNDEF, but we could add support
6176 for the others if it ever becomes necessary. */
6177 for (i = 1; i < 3; i++)
6178 if (reloc_type[i] != BFD_RELOC_UNUSED)
6180 ip->fixp[i] = fix_new (ip->frag, ip->where,
6181 ip->fixp[0]->fx_size, NULL, 0,
6182 FALSE, final_type[i]);
6184 /* Use fx_tcbit to mark compound relocs. */
6185 ip->fixp[0]->fx_tcbit = 1;
6186 ip->fixp[i]->fx_tcbit = 1;
6191 /* Update the register mask information. */
6192 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
6193 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
6198 insert_into_history (0, 1, ip);
6201 case APPEND_ADD_WITH_NOP:
6203 struct mips_cl_insn *nop;
6205 insert_into_history (0, 1, ip);
6206 nop = get_delay_slot_nop (ip);
6207 add_fixed_insn (nop);
6208 insert_into_history (0, 1, nop);
6209 if (mips_relax.sequence)
6210 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
6214 case APPEND_ADD_COMPACT:
6215 /* Convert MIPS16 jr/jalr into a "compact" jump. */
6216 gas_assert (mips_opts.mips16);
6217 ip->insn_opcode |= 0x0080;
6218 find_altered_mips16_opcode (ip);
6220 insert_into_history (0, 1, ip);
6225 struct mips_cl_insn delay = history[0];
6226 if (mips_opts.mips16)
6228 know (delay.frag == ip->frag);
6229 move_insn (ip, delay.frag, delay.where);
6230 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
6232 else if (relaxed_branch || delay.frag != ip->frag)
6234 /* Add the delay slot instruction to the end of the
6235 current frag and shrink the fixed part of the
6236 original frag. If the branch occupies the tail of
6237 the latter, move it backwards to cover the gap. */
6238 delay.frag->fr_fix -= branch_disp;
6239 if (delay.frag == ip->frag)
6240 move_insn (ip, ip->frag, ip->where - branch_disp);
6241 add_fixed_insn (&delay);
6245 move_insn (&delay, ip->frag,
6246 ip->where - branch_disp + insn_length (ip));
6247 move_insn (ip, history[0].frag, history[0].where);
6251 insert_into_history (0, 1, &delay);
6256 /* If we have just completed an unconditional branch, clear the history. */
6257 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
6258 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
6262 mips_no_prev_insn ();
6264 for (i = 0; i < ARRAY_SIZE (history); i++)
6265 history[i].cleared_p = 1;
6268 /* We need to emit a label at the end of branch-likely macros. */
6269 if (emit_branch_likely_macro)
6271 emit_branch_likely_macro = FALSE;
6272 micromips_add_label ();
6275 /* We just output an insn, so the next one doesn't have a label. */
6276 mips_clear_insn_labels ();
6279 /* Forget that there was any previous instruction or label.
6280 When BRANCH is true, the branch history is also flushed. */
6283 mips_no_prev_insn (void)
6285 prev_nop_frag = NULL;
6286 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
6287 mips_clear_insn_labels ();
6290 /* This function must be called before we emit something other than
6291 instructions. It is like mips_no_prev_insn except that it inserts
6292 any NOPS that might be needed by previous instructions. */
6295 mips_emit_delays (void)
6297 if (! mips_opts.noreorder)
6299 int nops = nops_for_insn (0, history, NULL);
6303 add_fixed_insn (NOP_INSN);
6304 mips_move_text_labels ();
6307 mips_no_prev_insn ();
6310 /* Start a (possibly nested) noreorder block. */
6313 start_noreorder (void)
6315 if (mips_opts.noreorder == 0)
6320 /* None of the instructions before the .set noreorder can be moved. */
6321 for (i = 0; i < ARRAY_SIZE (history); i++)
6322 history[i].fixed_p = 1;
6324 /* Insert any nops that might be needed between the .set noreorder
6325 block and the previous instructions. We will later remove any
6326 nops that turn out not to be needed. */
6327 nops = nops_for_insn (0, history, NULL);
6330 if (mips_optimize != 0)
6332 /* Record the frag which holds the nop instructions, so
6333 that we can remove them if we don't need them. */
6334 frag_grow (nops * NOP_INSN_SIZE);
6335 prev_nop_frag = frag_now;
6336 prev_nop_frag_holds = nops;
6337 prev_nop_frag_required = 0;
6338 prev_nop_frag_since = 0;
6341 for (; nops > 0; --nops)
6342 add_fixed_insn (NOP_INSN);
6344 /* Move on to a new frag, so that it is safe to simply
6345 decrease the size of prev_nop_frag. */
6346 frag_wane (frag_now);
6348 mips_move_text_labels ();
6350 mips_mark_labels ();
6351 mips_clear_insn_labels ();
6353 mips_opts.noreorder++;
6354 mips_any_noreorder = 1;
6357 /* End a nested noreorder block. */
6360 end_noreorder (void)
6362 mips_opts.noreorder--;
6363 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
6365 /* Commit to inserting prev_nop_frag_required nops and go back to
6366 handling nop insertion the .set reorder way. */
6367 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
6369 insert_into_history (prev_nop_frag_since,
6370 prev_nop_frag_required, NOP_INSN);
6371 prev_nop_frag = NULL;
6375 /* Set up global variables for the start of a new macro. */
6380 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
6381 memset (&mips_macro_warning.first_insn_sizes, 0,
6382 sizeof (mips_macro_warning.first_insn_sizes));
6383 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
6384 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
6385 && delayed_branch_p (&history[0]));
6386 switch (history[0].insn_mo->pinfo2
6387 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
6389 case INSN2_BRANCH_DELAY_32BIT:
6390 mips_macro_warning.delay_slot_length = 4;
6392 case INSN2_BRANCH_DELAY_16BIT:
6393 mips_macro_warning.delay_slot_length = 2;
6396 mips_macro_warning.delay_slot_length = 0;
6399 mips_macro_warning.first_frag = NULL;
6402 /* Given that a macro is longer than one instruction or of the wrong size,
6403 return the appropriate warning for it. Return null if no warning is
6404 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
6405 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
6406 and RELAX_NOMACRO. */
6409 macro_warning (relax_substateT subtype)
6411 if (subtype & RELAX_DELAY_SLOT)
6412 return _("Macro instruction expanded into multiple instructions"
6413 " in a branch delay slot");
6414 else if (subtype & RELAX_NOMACRO)
6415 return _("Macro instruction expanded into multiple instructions");
6416 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
6417 | RELAX_DELAY_SLOT_SIZE_SECOND))
6418 return ((subtype & RELAX_DELAY_SLOT_16BIT)
6419 ? _("Macro instruction expanded into a wrong size instruction"
6420 " in a 16-bit branch delay slot")
6421 : _("Macro instruction expanded into a wrong size instruction"
6422 " in a 32-bit branch delay slot"));
6427 /* Finish up a macro. Emit warnings as appropriate. */
6432 /* Relaxation warning flags. */
6433 relax_substateT subtype = 0;
6435 /* Check delay slot size requirements. */
6436 if (mips_macro_warning.delay_slot_length == 2)
6437 subtype |= RELAX_DELAY_SLOT_16BIT;
6438 if (mips_macro_warning.delay_slot_length != 0)
6440 if (mips_macro_warning.delay_slot_length
6441 != mips_macro_warning.first_insn_sizes[0])
6442 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
6443 if (mips_macro_warning.delay_slot_length
6444 != mips_macro_warning.first_insn_sizes[1])
6445 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
6448 /* Check instruction count requirements. */
6449 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
6451 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
6452 subtype |= RELAX_SECOND_LONGER;
6453 if (mips_opts.warn_about_macros)
6454 subtype |= RELAX_NOMACRO;
6455 if (mips_macro_warning.delay_slot_p)
6456 subtype |= RELAX_DELAY_SLOT;
6459 /* If both alternatives fail to fill a delay slot correctly,
6460 emit the warning now. */
6461 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
6462 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
6467 s = subtype & (RELAX_DELAY_SLOT_16BIT
6468 | RELAX_DELAY_SLOT_SIZE_FIRST
6469 | RELAX_DELAY_SLOT_SIZE_SECOND);
6470 msg = macro_warning (s);
6472 as_warn ("%s", msg);
6476 /* If both implementations are longer than 1 instruction, then emit the
6478 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
6483 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
6484 msg = macro_warning (s);
6486 as_warn ("%s", msg);
6490 /* If any flags still set, then one implementation might need a warning
6491 and the other either will need one of a different kind or none at all.
6492 Pass any remaining flags over to relaxation. */
6493 if (mips_macro_warning.first_frag != NULL)
6494 mips_macro_warning.first_frag->fr_subtype |= subtype;
6497 /* Instruction operand formats used in macros that vary between
6498 standard MIPS and microMIPS code. */
6500 static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } };
6501 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
6502 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
6503 static const char * const lui_fmt[2] = { "t,u", "s,u" };
6504 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
6505 static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } };
6506 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
6507 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
6509 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
6510 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
6511 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
6512 #define LUI_FMT (lui_fmt[mips_opts.micromips])
6513 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
6514 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
6515 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
6516 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
6518 /* Read a macro's relocation codes from *ARGS and store them in *R.
6519 The first argument in *ARGS will be either the code for a single
6520 relocation or -1 followed by the three codes that make up a
6521 composite relocation. */
6524 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
6528 next = va_arg (*args, int);
6530 r[0] = (bfd_reloc_code_real_type) next;
6533 for (i = 0; i < 3; i++)
6534 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
6535 /* This function is only used for 16-bit relocation fields.
6536 To make the macro code simpler, treat an unrelocated value
6537 in the same way as BFD_RELOC_LO16. */
6538 if (r[0] == BFD_RELOC_UNUSED)
6539 r[0] = BFD_RELOC_LO16;
6543 /* Build an instruction created by a macro expansion. This is passed
6544 a pointer to the count of instructions created so far, an
6545 expression, the name of the instruction to build, an operand format
6546 string, and corresponding arguments. */
6549 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
6551 const struct mips_opcode *mo = NULL;
6552 bfd_reloc_code_real_type r[3];
6553 const struct mips_opcode *amo;
6554 const struct mips_operand *operand;
6555 struct hash_control *hash;
6556 struct mips_cl_insn insn;
6560 va_start (args, fmt);
6562 if (mips_opts.mips16)
6564 mips16_macro_build (ep, name, fmt, &args);
6569 r[0] = BFD_RELOC_UNUSED;
6570 r[1] = BFD_RELOC_UNUSED;
6571 r[2] = BFD_RELOC_UNUSED;
6572 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
6573 amo = (struct mips_opcode *) hash_find (hash, name);
6575 gas_assert (strcmp (name, amo->name) == 0);
6579 /* Search until we get a match for NAME. It is assumed here that
6580 macros will never generate MDMX, MIPS-3D, or MT instructions.
6581 We try to match an instruction that fulfils the branch delay
6582 slot instruction length requirement (if any) of the previous
6583 instruction. While doing this we record the first instruction
6584 seen that matches all the other conditions and use it anyway
6585 if the requirement cannot be met; we will issue an appropriate
6586 warning later on. */
6587 if (strcmp (fmt, amo->args) == 0
6588 && amo->pinfo != INSN_MACRO
6589 && is_opcode_valid (amo)
6590 && is_size_valid (amo))
6592 if (is_delay_slot_valid (amo))
6602 gas_assert (amo->name);
6604 while (strcmp (name, amo->name) == 0);
6607 create_insn (&insn, mo);
6620 macro_read_relocs (&args, r);
6621 gas_assert (*r == BFD_RELOC_GPREL16
6622 || *r == BFD_RELOC_MIPS_HIGHER
6623 || *r == BFD_RELOC_HI16_S
6624 || *r == BFD_RELOC_LO16
6625 || *r == BFD_RELOC_MIPS_GOT_OFST);
6629 macro_read_relocs (&args, r);
6633 macro_read_relocs (&args, r);
6634 gas_assert (ep != NULL
6635 && (ep->X_op == O_constant
6636 || (ep->X_op == O_symbol
6637 && (*r == BFD_RELOC_MIPS_HIGHEST
6638 || *r == BFD_RELOC_HI16_S
6639 || *r == BFD_RELOC_HI16
6640 || *r == BFD_RELOC_GPREL16
6641 || *r == BFD_RELOC_MIPS_GOT_HI16
6642 || *r == BFD_RELOC_MIPS_CALL_HI16))));
6646 gas_assert (ep != NULL);
6649 * This allows macro() to pass an immediate expression for
6650 * creating short branches without creating a symbol.
6652 * We don't allow branch relaxation for these branches, as
6653 * they should only appear in ".set nomacro" anyway.
6655 if (ep->X_op == O_constant)
6657 /* For microMIPS we always use relocations for branches.
6658 So we should not resolve immediate values. */
6659 gas_assert (!mips_opts.micromips);
6661 if ((ep->X_add_number & 3) != 0)
6662 as_bad (_("branch to misaligned address (0x%lx)"),
6663 (unsigned long) ep->X_add_number);
6664 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
6665 as_bad (_("branch address range overflow (0x%lx)"),
6666 (unsigned long) ep->X_add_number);
6667 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
6671 *r = BFD_RELOC_16_PCREL_S2;
6675 gas_assert (ep != NULL);
6676 *r = BFD_RELOC_MIPS_JMP;
6680 operand = (mips_opts.micromips
6681 ? decode_micromips_operand (fmt)
6682 : decode_mips_operand (fmt));
6686 uval = va_arg (args, int);
6687 if (operand->type == OP_CLO_CLZ_DEST)
6688 uval |= (uval << 5);
6689 insn_insert_operand (&insn, operand, uval);
6691 if (*fmt == '+' || *fmt == 'm')
6697 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
6699 append_insn (&insn, ep, r, TRUE);
6703 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
6706 struct mips_opcode *mo;
6707 struct mips_cl_insn insn;
6708 const struct mips_operand *operand;
6709 bfd_reloc_code_real_type r[3]
6710 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
6712 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
6714 gas_assert (strcmp (name, mo->name) == 0);
6716 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
6719 gas_assert (mo->name);
6720 gas_assert (strcmp (name, mo->name) == 0);
6723 create_insn (&insn, mo);
6761 gas_assert (ep != NULL);
6763 if (ep->X_op != O_constant)
6764 *r = (int) BFD_RELOC_UNUSED + c;
6765 else if (calculate_reloc (*r, ep->X_add_number, &value))
6767 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode);
6769 *r = BFD_RELOC_UNUSED;
6775 operand = decode_mips16_operand (c, FALSE);
6779 insn_insert_operand (&insn, operand, va_arg (args, int));
6784 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
6786 append_insn (&insn, ep, r, TRUE);
6790 * Sign-extend 32-bit mode constants that have bit 31 set and all
6791 * higher bits unset.
6794 normalize_constant_expr (expressionS *ex)
6796 if (ex->X_op == O_constant
6797 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
6798 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
6803 * Sign-extend 32-bit mode address offsets that have bit 31 set and
6804 * all higher bits unset.
6807 normalize_address_expr (expressionS *ex)
6809 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
6810 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
6811 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
6812 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
6817 * Generate a "jalr" instruction with a relocation hint to the called
6818 * function. This occurs in NewABI PIC code.
6821 macro_build_jalr (expressionS *ep, int cprestore)
6823 static const bfd_reloc_code_real_type jalr_relocs[2]
6824 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
6825 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
6829 if (MIPS_JALR_HINT_P (ep))
6834 if (mips_opts.micromips)
6836 jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32
6837 ? "jalr" : "jalrs");
6838 if (MIPS_JALR_HINT_P (ep)
6840 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
6841 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
6843 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
6846 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
6847 if (MIPS_JALR_HINT_P (ep))
6848 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
6852 * Generate a "lui" instruction.
6855 macro_build_lui (expressionS *ep, int regnum)
6857 gas_assert (! mips_opts.mips16);
6859 if (ep->X_op != O_constant)
6861 gas_assert (ep->X_op == O_symbol);
6862 /* _gp_disp is a special case, used from s_cpload.
6863 __gnu_local_gp is used if mips_no_shared. */
6864 gas_assert (mips_pic == NO_PIC
6866 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
6867 || (! mips_in_shared
6868 && strcmp (S_GET_NAME (ep->X_add_symbol),
6869 "__gnu_local_gp") == 0));
6872 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
6875 /* Generate a sequence of instructions to do a load or store from a constant
6876 offset off of a base register (breg) into/from a target register (treg),
6877 using AT if necessary. */
6879 macro_build_ldst_constoffset (expressionS *ep, const char *op,
6880 int treg, int breg, int dbl)
6882 gas_assert (ep->X_op == O_constant);
6884 /* Sign-extending 32-bit constants makes their handling easier. */
6886 normalize_constant_expr (ep);
6888 /* Right now, this routine can only handle signed 32-bit constants. */
6889 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
6890 as_warn (_("operand overflow"));
6892 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
6894 /* Signed 16-bit offset will fit in the op. Easy! */
6895 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
6899 /* 32-bit offset, need multiple instructions and AT, like:
6900 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
6901 addu $tempreg,$tempreg,$breg
6902 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
6903 to handle the complete offset. */
6904 macro_build_lui (ep, AT);
6905 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
6906 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
6909 as_bad (_("Macro used $at after \".set noat\""));
6914 * Generates code to set the $at register to true (one)
6915 * if reg is less than the immediate expression.
6918 set_at (int reg, int unsignedp)
6920 if (imm_expr.X_op == O_constant
6921 && imm_expr.X_add_number >= -0x8000
6922 && imm_expr.X_add_number < 0x8000)
6923 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
6924 AT, reg, BFD_RELOC_LO16);
6927 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
6928 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
6932 /* Count the leading zeroes by performing a binary chop. This is a
6933 bulky bit of source, but performance is a LOT better for the
6934 majority of values than a simple loop to count the bits:
6935 for (lcnt = 0; (lcnt < 32); lcnt++)
6936 if ((v) & (1 << (31 - lcnt)))
6938 However it is not code size friendly, and the gain will drop a bit
6939 on certain cached systems.
6941 #define COUNT_TOP_ZEROES(v) \
6942 (((v) & ~0xffff) == 0 \
6943 ? ((v) & ~0xff) == 0 \
6944 ? ((v) & ~0xf) == 0 \
6945 ? ((v) & ~0x3) == 0 \
6946 ? ((v) & ~0x1) == 0 \
6951 : ((v) & ~0x7) == 0 \
6954 : ((v) & ~0x3f) == 0 \
6955 ? ((v) & ~0x1f) == 0 \
6958 : ((v) & ~0x7f) == 0 \
6961 : ((v) & ~0xfff) == 0 \
6962 ? ((v) & ~0x3ff) == 0 \
6963 ? ((v) & ~0x1ff) == 0 \
6966 : ((v) & ~0x7ff) == 0 \
6969 : ((v) & ~0x3fff) == 0 \
6970 ? ((v) & ~0x1fff) == 0 \
6973 : ((v) & ~0x7fff) == 0 \
6976 : ((v) & ~0xffffff) == 0 \
6977 ? ((v) & ~0xfffff) == 0 \
6978 ? ((v) & ~0x3ffff) == 0 \
6979 ? ((v) & ~0x1ffff) == 0 \
6982 : ((v) & ~0x7ffff) == 0 \
6985 : ((v) & ~0x3fffff) == 0 \
6986 ? ((v) & ~0x1fffff) == 0 \
6989 : ((v) & ~0x7fffff) == 0 \
6992 : ((v) & ~0xfffffff) == 0 \
6993 ? ((v) & ~0x3ffffff) == 0 \
6994 ? ((v) & ~0x1ffffff) == 0 \
6997 : ((v) & ~0x7ffffff) == 0 \
7000 : ((v) & ~0x3fffffff) == 0 \
7001 ? ((v) & ~0x1fffffff) == 0 \
7004 : ((v) & ~0x7fffffff) == 0 \
7009 * This routine generates the least number of instructions necessary to load
7010 * an absolute expression value into a register.
7013 load_register (int reg, expressionS *ep, int dbl)
7016 expressionS hi32, lo32;
7018 if (ep->X_op != O_big)
7020 gas_assert (ep->X_op == O_constant);
7022 /* Sign-extending 32-bit constants makes their handling easier. */
7024 normalize_constant_expr (ep);
7026 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
7028 /* We can handle 16 bit signed values with an addiu to
7029 $zero. No need to ever use daddiu here, since $zero and
7030 the result are always correct in 32 bit mode. */
7031 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
7034 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
7036 /* We can handle 16 bit unsigned values with an ori to
7038 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
7041 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
7043 /* 32 bit values require an lui. */
7044 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
7045 if ((ep->X_add_number & 0xffff) != 0)
7046 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
7051 /* The value is larger than 32 bits. */
7053 if (!dbl || HAVE_32BIT_GPRS)
7057 sprintf_vma (value, ep->X_add_number);
7058 as_bad (_("Number (0x%s) larger than 32 bits"), value);
7059 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
7063 if (ep->X_op != O_big)
7066 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
7067 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
7068 hi32.X_add_number &= 0xffffffff;
7070 lo32.X_add_number &= 0xffffffff;
7074 gas_assert (ep->X_add_number > 2);
7075 if (ep->X_add_number == 3)
7076 generic_bignum[3] = 0;
7077 else if (ep->X_add_number > 4)
7078 as_bad (_("Number larger than 64 bits"));
7079 lo32.X_op = O_constant;
7080 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
7081 hi32.X_op = O_constant;
7082 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
7085 if (hi32.X_add_number == 0)
7090 unsigned long hi, lo;
7092 if (hi32.X_add_number == (offsetT) 0xffffffff)
7094 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
7096 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
7099 if (lo32.X_add_number & 0x80000000)
7101 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
7102 if (lo32.X_add_number & 0xffff)
7103 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
7108 /* Check for 16bit shifted constant. We know that hi32 is
7109 non-zero, so start the mask on the first bit of the hi32
7114 unsigned long himask, lomask;
7118 himask = 0xffff >> (32 - shift);
7119 lomask = (0xffff << shift) & 0xffffffff;
7123 himask = 0xffff << (shift - 32);
7126 if ((hi32.X_add_number & ~(offsetT) himask) == 0
7127 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
7131 tmp.X_op = O_constant;
7133 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
7134 | (lo32.X_add_number >> shift));
7136 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
7137 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
7138 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
7139 reg, reg, (shift >= 32) ? shift - 32 : shift);
7144 while (shift <= (64 - 16));
7146 /* Find the bit number of the lowest one bit, and store the
7147 shifted value in hi/lo. */
7148 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
7149 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
7153 while ((lo & 1) == 0)
7158 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
7164 while ((hi & 1) == 0)
7173 /* Optimize if the shifted value is a (power of 2) - 1. */
7174 if ((hi == 0 && ((lo + 1) & lo) == 0)
7175 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
7177 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
7182 /* This instruction will set the register to be all
7184 tmp.X_op = O_constant;
7185 tmp.X_add_number = (offsetT) -1;
7186 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
7190 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
7191 reg, reg, (bit >= 32) ? bit - 32 : bit);
7193 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
7194 reg, reg, (shift >= 32) ? shift - 32 : shift);
7199 /* Sign extend hi32 before calling load_register, because we can
7200 generally get better code when we load a sign extended value. */
7201 if ((hi32.X_add_number & 0x80000000) != 0)
7202 hi32.X_add_number |= ~(offsetT) 0xffffffff;
7203 load_register (reg, &hi32, 0);
7206 if ((lo32.X_add_number & 0xffff0000) == 0)
7210 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
7218 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
7220 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
7221 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
7227 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
7231 mid16.X_add_number >>= 16;
7232 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
7233 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
7236 if ((lo32.X_add_number & 0xffff) != 0)
7237 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
7241 load_delay_nop (void)
7243 if (!gpr_interlocks)
7244 macro_build (NULL, "nop", "");
7247 /* Load an address into a register. */
7250 load_address (int reg, expressionS *ep, int *used_at)
7252 if (ep->X_op != O_constant
7253 && ep->X_op != O_symbol)
7255 as_bad (_("expression too complex"));
7256 ep->X_op = O_constant;
7259 if (ep->X_op == O_constant)
7261 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
7265 if (mips_pic == NO_PIC)
7267 /* If this is a reference to a GP relative symbol, we want
7268 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
7270 lui $reg,<sym> (BFD_RELOC_HI16_S)
7271 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
7272 If we have an addend, we always use the latter form.
7274 With 64bit address space and a usable $at we want
7275 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7276 lui $at,<sym> (BFD_RELOC_HI16_S)
7277 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
7278 daddiu $at,<sym> (BFD_RELOC_LO16)
7282 If $at is already in use, we use a path which is suboptimal
7283 on superscalar processors.
7284 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7285 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
7287 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
7289 daddiu $reg,<sym> (BFD_RELOC_LO16)
7291 For GP relative symbols in 64bit address space we can use
7292 the same sequence as in 32bit address space. */
7293 if (HAVE_64BIT_SYMBOLS)
7295 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
7296 && !nopic_need_relax (ep->X_add_symbol, 1))
7298 relax_start (ep->X_add_symbol);
7299 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
7300 mips_gp_register, BFD_RELOC_GPREL16);
7304 if (*used_at == 0 && mips_opts.at)
7306 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
7307 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
7308 macro_build (ep, "daddiu", "t,r,j", reg, reg,
7309 BFD_RELOC_MIPS_HIGHER);
7310 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
7311 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
7312 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
7317 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
7318 macro_build (ep, "daddiu", "t,r,j", reg, reg,
7319 BFD_RELOC_MIPS_HIGHER);
7320 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
7321 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
7322 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
7323 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
7326 if (mips_relax.sequence)
7331 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
7332 && !nopic_need_relax (ep->X_add_symbol, 1))
7334 relax_start (ep->X_add_symbol);
7335 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
7336 mips_gp_register, BFD_RELOC_GPREL16);
7339 macro_build_lui (ep, reg);
7340 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
7341 reg, reg, BFD_RELOC_LO16);
7342 if (mips_relax.sequence)
7346 else if (!mips_big_got)
7350 /* If this is a reference to an external symbol, we want
7351 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7353 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7355 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
7356 If there is a constant, it must be added in after.
7358 If we have NewABI, we want
7359 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7360 unless we're referencing a global symbol with a non-zero
7361 offset, in which case cst must be added separately. */
7364 if (ep->X_add_number)
7366 ex.X_add_number = ep->X_add_number;
7367 ep->X_add_number = 0;
7368 relax_start (ep->X_add_symbol);
7369 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
7370 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7371 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
7372 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7373 ex.X_op = O_constant;
7374 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
7375 reg, reg, BFD_RELOC_LO16);
7376 ep->X_add_number = ex.X_add_number;
7379 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
7380 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7381 if (mips_relax.sequence)
7386 ex.X_add_number = ep->X_add_number;
7387 ep->X_add_number = 0;
7388 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
7389 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7391 relax_start (ep->X_add_symbol);
7393 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
7397 if (ex.X_add_number != 0)
7399 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
7400 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7401 ex.X_op = O_constant;
7402 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
7403 reg, reg, BFD_RELOC_LO16);
7407 else if (mips_big_got)
7411 /* This is the large GOT case. If this is a reference to an
7412 external symbol, we want
7413 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7415 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
7417 Otherwise, for a reference to a local symbol in old ABI, we want
7418 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7420 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
7421 If there is a constant, it must be added in after.
7423 In the NewABI, for local symbols, with or without offsets, we want:
7424 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7425 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
7429 ex.X_add_number = ep->X_add_number;
7430 ep->X_add_number = 0;
7431 relax_start (ep->X_add_symbol);
7432 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
7433 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7434 reg, reg, mips_gp_register);
7435 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
7436 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
7437 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
7438 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7439 else if (ex.X_add_number)
7441 ex.X_op = O_constant;
7442 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
7446 ep->X_add_number = ex.X_add_number;
7448 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
7449 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
7450 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
7451 BFD_RELOC_MIPS_GOT_OFST);
7456 ex.X_add_number = ep->X_add_number;
7457 ep->X_add_number = 0;
7458 relax_start (ep->X_add_symbol);
7459 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
7460 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7461 reg, reg, mips_gp_register);
7462 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
7463 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
7465 if (reg_needs_delay (mips_gp_register))
7467 /* We need a nop before loading from $gp. This special
7468 check is required because the lui which starts the main
7469 instruction stream does not refer to $gp, and so will not
7470 insert the nop which may be required. */
7471 macro_build (NULL, "nop", "");
7473 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
7474 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7476 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
7480 if (ex.X_add_number != 0)
7482 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
7483 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7484 ex.X_op = O_constant;
7485 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
7493 if (!mips_opts.at && *used_at == 1)
7494 as_bad (_("Macro used $at after \".set noat\""));
7497 /* Move the contents of register SOURCE into register DEST. */
7500 move_register (int dest, int source)
7502 /* Prefer to use a 16-bit microMIPS instruction unless the previous
7503 instruction specifically requires a 32-bit one. */
7504 if (mips_opts.micromips
7505 && !mips_opts.insn32
7506 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
7507 macro_build (NULL, "move", "mp,mj", dest, source);
7509 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
7513 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
7514 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
7515 The two alternatives are:
7517 Global symbol Local sybmol
7518 ------------- ------------
7519 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
7521 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
7523 load_got_offset emits the first instruction and add_got_offset
7524 emits the second for a 16-bit offset or add_got_offset_hilo emits
7525 a sequence to add a 32-bit offset using a scratch register. */
7528 load_got_offset (int dest, expressionS *local)
7533 global.X_add_number = 0;
7535 relax_start (local->X_add_symbol);
7536 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
7537 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7539 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
7540 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7545 add_got_offset (int dest, expressionS *local)
7549 global.X_op = O_constant;
7550 global.X_op_symbol = NULL;
7551 global.X_add_symbol = NULL;
7552 global.X_add_number = local->X_add_number;
7554 relax_start (local->X_add_symbol);
7555 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
7556 dest, dest, BFD_RELOC_LO16);
7558 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
7563 add_got_offset_hilo (int dest, expressionS *local, int tmp)
7566 int hold_mips_optimize;
7568 global.X_op = O_constant;
7569 global.X_op_symbol = NULL;
7570 global.X_add_symbol = NULL;
7571 global.X_add_number = local->X_add_number;
7573 relax_start (local->X_add_symbol);
7574 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
7576 /* Set mips_optimize around the lui instruction to avoid
7577 inserting an unnecessary nop after the lw. */
7578 hold_mips_optimize = mips_optimize;
7580 macro_build_lui (&global, tmp);
7581 mips_optimize = hold_mips_optimize;
7582 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
7585 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
7588 /* Emit a sequence of instructions to emulate a branch likely operation.
7589 BR is an ordinary branch corresponding to one to be emulated. BRNEG
7590 is its complementing branch with the original condition negated.
7591 CALL is set if the original branch specified the link operation.
7592 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
7594 Code like this is produced in the noreorder mode:
7599 delay slot (executed only if branch taken)
7607 delay slot (executed only if branch taken)
7610 In the reorder mode the delay slot would be filled with a nop anyway,
7611 so code produced is simply:
7616 This function is used when producing code for the microMIPS ASE that
7617 does not implement branch likely instructions in hardware. */
7620 macro_build_branch_likely (const char *br, const char *brneg,
7621 int call, expressionS *ep, const char *fmt,
7622 unsigned int sreg, unsigned int treg)
7624 int noreorder = mips_opts.noreorder;
7627 gas_assert (mips_opts.micromips);
7631 micromips_label_expr (&expr1);
7632 macro_build (&expr1, brneg, fmt, sreg, treg);
7633 macro_build (NULL, "nop", "");
7634 macro_build (ep, call ? "bal" : "b", "p");
7636 /* Set to true so that append_insn adds a label. */
7637 emit_branch_likely_macro = TRUE;
7641 macro_build (ep, br, fmt, sreg, treg);
7642 macro_build (NULL, "nop", "");
7647 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
7648 the condition code tested. EP specifies the branch target. */
7651 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
7678 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
7681 /* Emit a two-argument branch macro specified by TYPE, using SREG as
7682 the register tested. EP specifies the branch target. */
7685 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
7687 const char *brneg = NULL;
7697 br = mips_opts.micromips ? "bgez" : "bgezl";
7701 gas_assert (mips_opts.micromips);
7702 br = mips_opts.insn32 ? "bgezal" : "bgezals";
7710 br = mips_opts.micromips ? "bgtz" : "bgtzl";
7717 br = mips_opts.micromips ? "blez" : "blezl";
7724 br = mips_opts.micromips ? "bltz" : "bltzl";
7728 gas_assert (mips_opts.micromips);
7729 br = mips_opts.insn32 ? "bltzal" : "bltzals";
7736 if (mips_opts.micromips && brneg)
7737 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
7739 macro_build (ep, br, "s,p", sreg);
7742 /* Emit a three-argument branch macro specified by TYPE, using SREG and
7743 TREG as the registers tested. EP specifies the branch target. */
7746 macro_build_branch_rsrt (int type, expressionS *ep,
7747 unsigned int sreg, unsigned int treg)
7749 const char *brneg = NULL;
7761 br = mips_opts.micromips ? "beq" : "beql";
7770 br = mips_opts.micromips ? "bne" : "bnel";
7776 if (mips_opts.micromips && brneg)
7777 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
7779 macro_build (ep, br, "s,t,p", sreg, treg);
7782 /* Return the high part that should be loaded in order to make the low
7783 part of VALUE accessible using an offset of OFFBITS bits. */
7786 offset_high_part (offsetT value, unsigned int offbits)
7793 bias = 1 << (offbits - 1);
7794 low_mask = bias * 2 - 1;
7795 return (value + bias) & ~low_mask;
7798 /* Return true if the value stored in offset_expr and offset_reloc
7799 fits into a signed offset of OFFBITS bits. RANGE is the maximum
7800 amount that the caller wants to add without inducing overflow
7801 and ALIGN is the known alignment of the value in bytes. */
7804 small_offset_p (unsigned int range, unsigned int align, unsigned int offbits)
7808 /* Accept any relocation operator if overflow isn't a concern. */
7809 if (range < align && *offset_reloc != BFD_RELOC_UNUSED)
7812 /* These relocations are guaranteed not to overflow in correct links. */
7813 if (*offset_reloc == BFD_RELOC_MIPS_LITERAL
7814 || gprel16_reloc_p (*offset_reloc))
7817 if (offset_expr.X_op == O_constant
7818 && offset_high_part (offset_expr.X_add_number, offbits) == 0
7819 && offset_high_part (offset_expr.X_add_number + range, offbits) == 0)
7826 * This routine implements the seemingly endless macro or synthesized
7827 * instructions and addressing modes in the mips assembly language. Many
7828 * of these macros are simple and are similar to each other. These could
7829 * probably be handled by some kind of table or grammar approach instead of
7830 * this verbose method. Others are not simple macros but are more like
7831 * optimizing code generation.
7832 * One interesting optimization is when several store macros appear
7833 * consecutively that would load AT with the upper half of the same address.
7834 * The ensuing load upper instructions are ommited. This implies some kind
7835 * of global optimization. We currently only optimize within a single macro.
7836 * For many of the load and store macros if the address is specified as a
7837 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
7838 * first load register 'at' with zero and use it as the base register. The
7839 * mips assembler simply uses register $zero. Just one tiny optimization
7843 macro (struct mips_cl_insn *ip, char *str)
7845 unsigned int treg, sreg, dreg, breg;
7846 unsigned int tempreg;
7849 expressionS label_expr;
7864 bfd_boolean large_offset;
7866 int hold_mips_optimize;
7869 gas_assert (! mips_opts.mips16);
7871 treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
7872 dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
7873 sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
7874 mask = ip->insn_mo->mask;
7876 label_expr.X_op = O_constant;
7877 label_expr.X_op_symbol = NULL;
7878 label_expr.X_add_symbol = NULL;
7879 label_expr.X_add_number = 0;
7881 expr1.X_op = O_constant;
7882 expr1.X_op_symbol = NULL;
7883 expr1.X_add_symbol = NULL;
7884 expr1.X_add_number = 1;
7900 if (mips_opts.micromips)
7901 micromips_label_expr (&label_expr);
7903 label_expr.X_add_number = 8;
7904 macro_build (&label_expr, "bgez", "s,p", sreg);
7906 macro_build (NULL, "nop", "");
7908 move_register (dreg, sreg);
7909 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
7910 if (mips_opts.micromips)
7911 micromips_add_label ();
7928 if (!mips_opts.micromips)
7930 if (imm_expr.X_op == O_constant
7931 && imm_expr.X_add_number >= -0x200
7932 && imm_expr.X_add_number < 0x200)
7934 macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number);
7943 if (imm_expr.X_op == O_constant
7944 && imm_expr.X_add_number >= -0x8000
7945 && imm_expr.X_add_number < 0x8000)
7947 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
7952 load_register (AT, &imm_expr, dbl);
7953 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
7972 if (imm_expr.X_op == O_constant
7973 && imm_expr.X_add_number >= 0
7974 && imm_expr.X_add_number < 0x10000)
7976 if (mask != M_NOR_I)
7977 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
7980 macro_build (&imm_expr, "ori", "t,r,i",
7981 treg, sreg, BFD_RELOC_LO16);
7982 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
7988 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7989 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
7993 switch (imm_expr.X_add_number)
7996 macro_build (NULL, "nop", "");
7999 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
8003 macro_build (NULL, "balign", "t,s,2", treg, sreg,
8004 (int) imm_expr.X_add_number);
8007 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
8008 (unsigned long) imm_expr.X_add_number);
8017 gas_assert (mips_opts.micromips);
8018 macro_build_branch_ccl (mask, &offset_expr,
8019 EXTRACT_OPERAND (1, BCC, *ip));
8026 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
8032 load_register (treg, &imm_expr, HAVE_64BIT_GPRS);
8037 macro_build_branch_rsrt (mask, &offset_expr, sreg, treg);
8044 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg);
8046 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg);
8050 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
8051 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8052 &offset_expr, AT, ZERO);
8062 macro_build_branch_rs (mask, &offset_expr, sreg);
8068 /* Check for > max integer. */
8069 if (imm_expr.X_op == O_constant && imm_expr.X_add_number >= GPR_SMAX)
8072 /* Result is always false. */
8074 macro_build (NULL, "nop", "");
8076 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
8079 if (imm_expr.X_op != O_constant)
8080 as_bad (_("Unsupported large constant"));
8081 ++imm_expr.X_add_number;
8085 if (mask == M_BGEL_I)
8087 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
8089 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
8090 &offset_expr, sreg);
8093 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
8095 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
8096 &offset_expr, sreg);
8099 if (imm_expr.X_op == O_constant && imm_expr.X_add_number <= GPR_SMIN)
8102 /* result is always true */
8103 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
8104 macro_build (&offset_expr, "b", "p");
8109 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8110 &offset_expr, AT, ZERO);
8119 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8120 &offset_expr, ZERO, treg);
8124 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
8125 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8126 &offset_expr, AT, ZERO);
8135 && imm_expr.X_op == O_constant
8136 && imm_expr.X_add_number == -1))
8138 if (imm_expr.X_op != O_constant)
8139 as_bad (_("Unsupported large constant"));
8140 ++imm_expr.X_add_number;
8144 if (mask == M_BGEUL_I)
8146 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
8148 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
8149 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8150 &offset_expr, sreg, ZERO);
8155 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8156 &offset_expr, AT, ZERO);
8164 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg);
8166 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg);
8170 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
8171 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8172 &offset_expr, AT, ZERO);
8180 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8181 &offset_expr, sreg, ZERO);
8187 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
8188 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8189 &offset_expr, AT, ZERO);
8197 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
8199 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg);
8203 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
8204 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8205 &offset_expr, AT, ZERO);
8212 if (imm_expr.X_op == O_constant && imm_expr.X_add_number >= GPR_SMAX)
8214 if (imm_expr.X_op != O_constant)
8215 as_bad (_("Unsupported large constant"));
8216 ++imm_expr.X_add_number;
8220 if (mask == M_BLTL_I)
8222 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
8223 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
8224 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
8225 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
8230 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8231 &offset_expr, AT, ZERO);
8239 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8240 &offset_expr, sreg, ZERO);
8246 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
8247 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8248 &offset_expr, AT, ZERO);
8257 && imm_expr.X_op == O_constant
8258 && imm_expr.X_add_number == -1))
8260 if (imm_expr.X_op != O_constant)
8261 as_bad (_("Unsupported large constant"));
8262 ++imm_expr.X_add_number;
8266 if (mask == M_BLTUL_I)
8268 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
8270 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
8271 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8272 &offset_expr, sreg, ZERO);
8277 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8278 &offset_expr, AT, ZERO);
8286 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
8288 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg);
8292 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
8293 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8294 &offset_expr, AT, ZERO);
8304 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8305 &offset_expr, ZERO, treg);
8309 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
8310 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8311 &offset_expr, AT, ZERO);
8317 /* Use unsigned arithmetic. */
8321 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
8323 as_bad (_("Unsupported large constant"));
8328 pos = imm_expr.X_add_number;
8329 size = imm2_expr.X_add_number;
8334 report_bad_range (ip, 3, pos, 0, 63, FALSE);
8337 if (size == 0 || size > 64 || (pos + size - 1) > 63)
8339 report_bad_field (pos, size);
8343 if (size <= 32 && pos < 32)
8348 else if (size <= 32)
8358 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
8365 /* Use unsigned arithmetic. */
8369 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
8371 as_bad (_("Unsupported large constant"));
8376 pos = imm_expr.X_add_number;
8377 size = imm2_expr.X_add_number;
8382 report_bad_range (ip, 3, pos, 0, 63, FALSE);
8385 if (size == 0 || size > 64 || (pos + size - 1) > 63)
8387 report_bad_field (pos, size);
8391 if (pos < 32 && (pos + size - 1) < 32)
8406 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
8407 (int) (pos + size - 1));
8423 as_warn (_("Divide by zero."));
8425 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
8427 macro_build (NULL, "break", BRK_FMT, 7);
8434 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
8435 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
8439 if (mips_opts.micromips)
8440 micromips_label_expr (&label_expr);
8442 label_expr.X_add_number = 8;
8443 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
8444 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
8445 macro_build (NULL, "break", BRK_FMT, 7);
8446 if (mips_opts.micromips)
8447 micromips_add_label ();
8449 expr1.X_add_number = -1;
8451 load_register (AT, &expr1, dbl);
8452 if (mips_opts.micromips)
8453 micromips_label_expr (&label_expr);
8455 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
8456 macro_build (&label_expr, "bne", "s,t,p", treg, AT);
8459 expr1.X_add_number = 1;
8460 load_register (AT, &expr1, dbl);
8461 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
8465 expr1.X_add_number = 0x80000000;
8466 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
8470 macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6);
8471 /* We want to close the noreorder block as soon as possible, so
8472 that later insns are available for delay slot filling. */
8477 if (mips_opts.micromips)
8478 micromips_label_expr (&label_expr);
8480 label_expr.X_add_number = 8;
8481 macro_build (&label_expr, "bne", "s,t,p", sreg, AT);
8482 macro_build (NULL, "nop", "");
8484 /* We want to close the noreorder block as soon as possible, so
8485 that later insns are available for delay slot filling. */
8488 macro_build (NULL, "break", BRK_FMT, 6);
8490 if (mips_opts.micromips)
8491 micromips_add_label ();
8492 macro_build (NULL, s, MFHL_FMT, dreg);
8531 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
8533 as_warn (_("Divide by zero."));
8535 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
8537 macro_build (NULL, "break", BRK_FMT, 7);
8540 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
8542 if (strcmp (s2, "mflo") == 0)
8543 move_register (dreg, sreg);
8545 move_register (dreg, ZERO);
8548 if (imm_expr.X_op == O_constant
8549 && imm_expr.X_add_number == -1
8550 && s[strlen (s) - 1] != 'u')
8552 if (strcmp (s2, "mflo") == 0)
8554 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
8557 move_register (dreg, ZERO);
8562 load_register (AT, &imm_expr, dbl);
8563 macro_build (NULL, s, "z,s,t", sreg, AT);
8564 macro_build (NULL, s2, MFHL_FMT, dreg);
8586 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
8587 macro_build (NULL, s, "z,s,t", sreg, treg);
8588 /* We want to close the noreorder block as soon as possible, so
8589 that later insns are available for delay slot filling. */
8594 if (mips_opts.micromips)
8595 micromips_label_expr (&label_expr);
8597 label_expr.X_add_number = 8;
8598 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
8599 macro_build (NULL, s, "z,s,t", sreg, treg);
8601 /* We want to close the noreorder block as soon as possible, so
8602 that later insns are available for delay slot filling. */
8604 macro_build (NULL, "break", BRK_FMT, 7);
8605 if (mips_opts.micromips)
8606 micromips_add_label ();
8608 macro_build (NULL, s2, MFHL_FMT, dreg);
8620 /* Load the address of a symbol into a register. If breg is not
8621 zero, we then add a base register to it. */
8623 if (dbl && HAVE_32BIT_GPRS)
8624 as_warn (_("dla used to load 32-bit register"));
8626 if (!dbl && HAVE_64BIT_OBJECTS)
8627 as_warn (_("la used to load 64-bit address"));
8629 if (small_offset_p (0, align, 16))
8631 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", treg, breg,
8632 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
8636 if (mips_opts.at && (treg == breg))
8646 if (offset_expr.X_op != O_symbol
8647 && offset_expr.X_op != O_constant)
8649 as_bad (_("Expression too complex"));
8650 offset_expr.X_op = O_constant;
8653 if (offset_expr.X_op == O_constant)
8654 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
8655 else if (mips_pic == NO_PIC)
8657 /* If this is a reference to a GP relative symbol, we want
8658 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
8660 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8661 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8662 If we have a constant, we need two instructions anyhow,
8663 so we may as well always use the latter form.
8665 With 64bit address space and a usable $at we want
8666 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8667 lui $at,<sym> (BFD_RELOC_HI16_S)
8668 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8669 daddiu $at,<sym> (BFD_RELOC_LO16)
8671 daddu $tempreg,$tempreg,$at
8673 If $at is already in use, we use a path which is suboptimal
8674 on superscalar processors.
8675 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8676 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8678 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8680 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
8682 For GP relative symbols in 64bit address space we can use
8683 the same sequence as in 32bit address space. */
8684 if (HAVE_64BIT_SYMBOLS)
8686 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8687 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8689 relax_start (offset_expr.X_add_symbol);
8690 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8691 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
8695 if (used_at == 0 && mips_opts.at)
8697 macro_build (&offset_expr, "lui", LUI_FMT,
8698 tempreg, BFD_RELOC_MIPS_HIGHEST);
8699 macro_build (&offset_expr, "lui", LUI_FMT,
8700 AT, BFD_RELOC_HI16_S);
8701 macro_build (&offset_expr, "daddiu", "t,r,j",
8702 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
8703 macro_build (&offset_expr, "daddiu", "t,r,j",
8704 AT, AT, BFD_RELOC_LO16);
8705 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
8706 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
8711 macro_build (&offset_expr, "lui", LUI_FMT,
8712 tempreg, BFD_RELOC_MIPS_HIGHEST);
8713 macro_build (&offset_expr, "daddiu", "t,r,j",
8714 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
8715 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
8716 macro_build (&offset_expr, "daddiu", "t,r,j",
8717 tempreg, tempreg, BFD_RELOC_HI16_S);
8718 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
8719 macro_build (&offset_expr, "daddiu", "t,r,j",
8720 tempreg, tempreg, BFD_RELOC_LO16);
8723 if (mips_relax.sequence)
8728 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8729 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8731 relax_start (offset_expr.X_add_symbol);
8732 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8733 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
8736 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
8737 as_bad (_("Offset too large"));
8738 macro_build_lui (&offset_expr, tempreg);
8739 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8740 tempreg, tempreg, BFD_RELOC_LO16);
8741 if (mips_relax.sequence)
8745 else if (!mips_big_got && !HAVE_NEWABI)
8747 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
8749 /* If this is a reference to an external symbol, and there
8750 is no constant, we want
8751 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8752 or for lca or if tempreg is PIC_CALL_REG
8753 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
8754 For a local symbol, we want
8755 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8757 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8759 If we have a small constant, and this is a reference to
8760 an external symbol, we want
8761 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8763 addiu $tempreg,$tempreg,<constant>
8764 For a local symbol, we want the same instruction
8765 sequence, but we output a BFD_RELOC_LO16 reloc on the
8768 If we have a large constant, and this is a reference to
8769 an external symbol, we want
8770 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8771 lui $at,<hiconstant>
8772 addiu $at,$at,<loconstant>
8773 addu $tempreg,$tempreg,$at
8774 For a local symbol, we want the same instruction
8775 sequence, but we output a BFD_RELOC_LO16 reloc on the
8779 if (offset_expr.X_add_number == 0)
8781 if (mips_pic == SVR4_PIC
8783 && (call || tempreg == PIC_CALL_REG))
8784 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
8786 relax_start (offset_expr.X_add_symbol);
8787 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8788 lw_reloc_type, mips_gp_register);
8791 /* We're going to put in an addu instruction using
8792 tempreg, so we may as well insert the nop right
8797 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8798 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
8800 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8801 tempreg, tempreg, BFD_RELOC_LO16);
8803 /* FIXME: If breg == 0, and the next instruction uses
8804 $tempreg, then if this variant case is used an extra
8805 nop will be generated. */
8807 else if (offset_expr.X_add_number >= -0x8000
8808 && offset_expr.X_add_number < 0x8000)
8810 load_got_offset (tempreg, &offset_expr);
8812 add_got_offset (tempreg, &offset_expr);
8816 expr1.X_add_number = offset_expr.X_add_number;
8817 offset_expr.X_add_number =
8818 SEXT_16BIT (offset_expr.X_add_number);
8819 load_got_offset (tempreg, &offset_expr);
8820 offset_expr.X_add_number = expr1.X_add_number;
8821 /* If we are going to add in a base register, and the
8822 target register and the base register are the same,
8823 then we are using AT as a temporary register. Since
8824 we want to load the constant into AT, we add our
8825 current AT (from the global offset table) and the
8826 register into the register now, and pretend we were
8827 not using a base register. */
8831 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8836 add_got_offset_hilo (tempreg, &offset_expr, AT);
8840 else if (!mips_big_got && HAVE_NEWABI)
8842 int add_breg_early = 0;
8844 /* If this is a reference to an external, and there is no
8845 constant, or local symbol (*), with or without a
8847 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
8848 or for lca or if tempreg is PIC_CALL_REG
8849 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
8851 If we have a small constant, and this is a reference to
8852 an external symbol, we want
8853 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
8854 addiu $tempreg,$tempreg,<constant>
8856 If we have a large constant, and this is a reference to
8857 an external symbol, we want
8858 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
8859 lui $at,<hiconstant>
8860 addiu $at,$at,<loconstant>
8861 addu $tempreg,$tempreg,$at
8863 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
8864 local symbols, even though it introduces an additional
8867 if (offset_expr.X_add_number)
8869 expr1.X_add_number = offset_expr.X_add_number;
8870 offset_expr.X_add_number = 0;
8872 relax_start (offset_expr.X_add_symbol);
8873 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8874 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
8876 if (expr1.X_add_number >= -0x8000
8877 && expr1.X_add_number < 0x8000)
8879 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
8880 tempreg, tempreg, BFD_RELOC_LO16);
8882 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
8884 /* If we are going to add in a base register, and the
8885 target register and the base register are the same,
8886 then we are using AT as a temporary register. Since
8887 we want to load the constant into AT, we add our
8888 current AT (from the global offset table) and the
8889 register into the register now, and pretend we were
8890 not using a base register. */
8895 gas_assert (tempreg == AT);
8896 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8902 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
8903 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8909 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
8912 offset_expr.X_add_number = expr1.X_add_number;
8914 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8915 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
8918 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8919 treg, tempreg, breg);
8925 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
8927 relax_start (offset_expr.X_add_symbol);
8928 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8929 BFD_RELOC_MIPS_CALL16, mips_gp_register);
8931 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8932 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
8937 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8938 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
8941 else if (mips_big_got && !HAVE_NEWABI)
8944 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
8945 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
8946 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
8948 /* This is the large GOT case. If this is a reference to an
8949 external symbol, and there is no constant, we want
8950 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8951 addu $tempreg,$tempreg,$gp
8952 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8953 or for lca or if tempreg is PIC_CALL_REG
8954 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
8955 addu $tempreg,$tempreg,$gp
8956 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
8957 For a local symbol, we want
8958 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8960 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8962 If we have a small constant, and this is a reference to
8963 an external symbol, we want
8964 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8965 addu $tempreg,$tempreg,$gp
8966 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8968 addiu $tempreg,$tempreg,<constant>
8969 For a local symbol, we want
8970 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8972 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
8974 If we have a large constant, and this is a reference to
8975 an external symbol, we want
8976 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8977 addu $tempreg,$tempreg,$gp
8978 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8979 lui $at,<hiconstant>
8980 addiu $at,$at,<loconstant>
8981 addu $tempreg,$tempreg,$at
8982 For a local symbol, we want
8983 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8984 lui $at,<hiconstant>
8985 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
8986 addu $tempreg,$tempreg,$at
8989 expr1.X_add_number = offset_expr.X_add_number;
8990 offset_expr.X_add_number = 0;
8991 relax_start (offset_expr.X_add_symbol);
8992 gpdelay = reg_needs_delay (mips_gp_register);
8993 if (expr1.X_add_number == 0 && breg == 0
8994 && (call || tempreg == PIC_CALL_REG))
8996 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
8997 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
8999 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
9000 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9001 tempreg, tempreg, mips_gp_register);
9002 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9003 tempreg, lw_reloc_type, tempreg);
9004 if (expr1.X_add_number == 0)
9008 /* We're going to put in an addu instruction using
9009 tempreg, so we may as well insert the nop right
9014 else if (expr1.X_add_number >= -0x8000
9015 && expr1.X_add_number < 0x8000)
9018 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
9019 tempreg, tempreg, BFD_RELOC_LO16);
9023 /* If we are going to add in a base register, and the
9024 target register and the base register are the same,
9025 then we are using AT as a temporary register. Since
9026 we want to load the constant into AT, we add our
9027 current AT (from the global offset table) and the
9028 register into the register now, and pretend we were
9029 not using a base register. */
9034 gas_assert (tempreg == AT);
9036 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9041 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
9042 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
9046 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number);
9051 /* This is needed because this instruction uses $gp, but
9052 the first instruction on the main stream does not. */
9053 macro_build (NULL, "nop", "");
9056 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9057 local_reloc_type, mips_gp_register);
9058 if (expr1.X_add_number >= -0x8000
9059 && expr1.X_add_number < 0x8000)
9062 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9063 tempreg, tempreg, BFD_RELOC_LO16);
9064 /* FIXME: If add_number is 0, and there was no base
9065 register, the external symbol case ended with a load,
9066 so if the symbol turns out to not be external, and
9067 the next instruction uses tempreg, an unnecessary nop
9068 will be inserted. */
9074 /* We must add in the base register now, as in the
9075 external symbol case. */
9076 gas_assert (tempreg == AT);
9078 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9081 /* We set breg to 0 because we have arranged to add
9082 it in in both cases. */
9086 macro_build_lui (&expr1, AT);
9087 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9088 AT, AT, BFD_RELOC_LO16);
9089 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9090 tempreg, tempreg, AT);
9095 else if (mips_big_got && HAVE_NEWABI)
9097 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
9098 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
9099 int add_breg_early = 0;
9101 /* This is the large GOT case. If this is a reference to an
9102 external symbol, and there is no constant, we want
9103 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9104 add $tempreg,$tempreg,$gp
9105 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9106 or for lca or if tempreg is PIC_CALL_REG
9107 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
9108 add $tempreg,$tempreg,$gp
9109 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
9111 If we have a small constant, and this is a reference to
9112 an external symbol, we want
9113 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9114 add $tempreg,$tempreg,$gp
9115 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9116 addi $tempreg,$tempreg,<constant>
9118 If we have a large constant, and this is a reference to
9119 an external symbol, we want
9120 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9121 addu $tempreg,$tempreg,$gp
9122 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9123 lui $at,<hiconstant>
9124 addi $at,$at,<loconstant>
9125 add $tempreg,$tempreg,$at
9127 If we have NewABI, and we know it's a local symbol, we want
9128 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9129 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9130 otherwise we have to resort to GOT_HI16/GOT_LO16. */
9132 relax_start (offset_expr.X_add_symbol);
9134 expr1.X_add_number = offset_expr.X_add_number;
9135 offset_expr.X_add_number = 0;
9137 if (expr1.X_add_number == 0 && breg == 0
9138 && (call || tempreg == PIC_CALL_REG))
9140 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
9141 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
9143 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
9144 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9145 tempreg, tempreg, mips_gp_register);
9146 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9147 tempreg, lw_reloc_type, tempreg);
9149 if (expr1.X_add_number == 0)
9151 else if (expr1.X_add_number >= -0x8000
9152 && expr1.X_add_number < 0x8000)
9154 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
9155 tempreg, tempreg, BFD_RELOC_LO16);
9157 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
9159 /* If we are going to add in a base register, and the
9160 target register and the base register are the same,
9161 then we are using AT as a temporary register. Since
9162 we want to load the constant into AT, we add our
9163 current AT (from the global offset table) and the
9164 register into the register now, and pretend we were
9165 not using a base register. */
9170 gas_assert (tempreg == AT);
9171 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9177 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
9178 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
9183 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
9186 offset_expr.X_add_number = expr1.X_add_number;
9187 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9188 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
9189 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
9190 tempreg, BFD_RELOC_MIPS_GOT_OFST);
9193 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9194 treg, tempreg, breg);
9204 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
9208 gas_assert (!mips_opts.micromips);
9209 macro_build (NULL, "c2", "C", (treg << 16) | 0x01);
9213 gas_assert (!mips_opts.micromips);
9214 macro_build (NULL, "c2", "C", 0x02);
9218 gas_assert (!mips_opts.micromips);
9219 macro_build (NULL, "c2", "C", (treg << 16) | 0x02);
9223 gas_assert (!mips_opts.micromips);
9224 macro_build (NULL, "c2", "C", 3);
9228 gas_assert (!mips_opts.micromips);
9229 macro_build (NULL, "c2", "C", (treg << 16) | 0x03);
9233 /* The j instruction may not be used in PIC code, since it
9234 requires an absolute address. We convert it to a b
9236 if (mips_pic == NO_PIC)
9237 macro_build (&offset_expr, "j", "a");
9239 macro_build (&offset_expr, "b", "p");
9242 /* The jal instructions must be handled as macros because when
9243 generating PIC code they expand to multi-instruction
9244 sequences. Normally they are simple instructions. */
9249 gas_assert (mips_opts.micromips);
9250 if (mips_opts.insn32)
9252 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str);
9262 if (mips_pic == NO_PIC)
9264 s = jals ? "jalrs" : "jalr";
9265 if (mips_opts.micromips
9266 && !mips_opts.insn32
9268 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
9269 macro_build (NULL, s, "mj", sreg);
9271 macro_build (NULL, s, JALR_FMT, dreg, sreg);
9275 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
9276 && mips_cprestore_offset >= 0);
9278 if (sreg != PIC_CALL_REG)
9279 as_warn (_("MIPS PIC call to register other than $25"));
9281 s = ((mips_opts.micromips
9282 && !mips_opts.insn32
9283 && (!mips_opts.noreorder || cprestore))
9284 ? "jalrs" : "jalr");
9285 if (mips_opts.micromips
9286 && !mips_opts.insn32
9288 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
9289 macro_build (NULL, s, "mj", sreg);
9291 macro_build (NULL, s, JALR_FMT, dreg, sreg);
9292 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
9294 if (mips_cprestore_offset < 0)
9295 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9298 if (!mips_frame_reg_valid)
9300 as_warn (_("No .frame pseudo-op used in PIC code"));
9301 /* Quiet this warning. */
9302 mips_frame_reg_valid = 1;
9304 if (!mips_cprestore_valid)
9306 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9307 /* Quiet this warning. */
9308 mips_cprestore_valid = 1;
9310 if (mips_opts.noreorder)
9311 macro_build (NULL, "nop", "");
9312 expr1.X_add_number = mips_cprestore_offset;
9313 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
9316 HAVE_64BIT_ADDRESSES);
9324 gas_assert (mips_opts.micromips);
9325 if (mips_opts.insn32)
9327 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str);
9333 if (mips_pic == NO_PIC)
9334 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
9335 else if (mips_pic == SVR4_PIC)
9337 /* If this is a reference to an external symbol, and we are
9338 using a small GOT, we want
9339 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9343 lw $gp,cprestore($sp)
9344 The cprestore value is set using the .cprestore
9345 pseudo-op. If we are using a big GOT, we want
9346 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
9348 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
9352 lw $gp,cprestore($sp)
9353 If the symbol is not external, we want
9354 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9356 addiu $25,$25,<sym> (BFD_RELOC_LO16)
9359 lw $gp,cprestore($sp)
9361 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
9362 sequences above, minus nops, unless the symbol is local,
9363 which enables us to use GOT_PAGE/GOT_OFST (big got) or
9369 relax_start (offset_expr.X_add_symbol);
9370 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9371 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
9374 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9375 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
9381 relax_start (offset_expr.X_add_symbol);
9382 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
9383 BFD_RELOC_MIPS_CALL_HI16);
9384 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
9385 PIC_CALL_REG, mips_gp_register);
9386 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9387 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
9390 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9391 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
9393 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9394 PIC_CALL_REG, PIC_CALL_REG,
9395 BFD_RELOC_MIPS_GOT_OFST);
9399 macro_build_jalr (&offset_expr, 0);
9403 relax_start (offset_expr.X_add_symbol);
9406 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9407 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
9416 gpdelay = reg_needs_delay (mips_gp_register);
9417 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
9418 BFD_RELOC_MIPS_CALL_HI16);
9419 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
9420 PIC_CALL_REG, mips_gp_register);
9421 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9422 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
9427 macro_build (NULL, "nop", "");
9429 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9430 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
9433 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9434 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
9436 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
9438 if (mips_cprestore_offset < 0)
9439 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9442 if (!mips_frame_reg_valid)
9444 as_warn (_("No .frame pseudo-op used in PIC code"));
9445 /* Quiet this warning. */
9446 mips_frame_reg_valid = 1;
9448 if (!mips_cprestore_valid)
9450 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9451 /* Quiet this warning. */
9452 mips_cprestore_valid = 1;
9454 if (mips_opts.noreorder)
9455 macro_build (NULL, "nop", "");
9456 expr1.X_add_number = mips_cprestore_offset;
9457 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
9460 HAVE_64BIT_ADDRESSES);
9464 else if (mips_pic == VXWORKS_PIC)
9465 as_bad (_("Non-PIC jump used in PIC library"));
9543 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
9549 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
9574 gas_assert (!mips_opts.micromips);
9577 /* Itbl support may require additional care here. */
9583 /* Itbl support may require additional care here. */
9589 offbits = (mips_opts.micromips ? 12 : 16);
9590 /* Itbl support may require additional care here. */
9594 gas_assert (!mips_opts.micromips);
9597 /* Itbl support may require additional care here. */
9603 offbits = (mips_opts.micromips ? 12 : 16);
9608 offbits = (mips_opts.micromips ? 12 : 16);
9613 /* Itbl support may require additional care here. */
9619 offbits = (mips_opts.micromips ? 12 : 16);
9620 /* Itbl support may require additional care here. */
9626 /* Itbl support may require additional care here. */
9632 /* Itbl support may require additional care here. */
9638 offbits = (mips_opts.micromips ? 12 : 16);
9643 offbits = (mips_opts.micromips ? 12 : 16);
9648 offbits = (mips_opts.micromips ? 12 : 16);
9653 offbits = (mips_opts.micromips ? 12 : 16);
9658 offbits = (mips_opts.micromips ? 12 : 16);
9661 gas_assert (mips_opts.micromips);
9668 gas_assert (mips_opts.micromips);
9675 gas_assert (mips_opts.micromips);
9681 gas_assert (mips_opts.micromips);
9688 /* We don't want to use $0 as tempreg. */
9689 if (breg == treg + lp || treg + lp == ZERO)
9692 tempreg = treg + lp;
9708 gas_assert (!mips_opts.micromips);
9711 /* Itbl support may require additional care here. */
9717 /* Itbl support may require additional care here. */
9723 offbits = (mips_opts.micromips ? 12 : 16);
9724 /* Itbl support may require additional care here. */
9728 gas_assert (!mips_opts.micromips);
9731 /* Itbl support may require additional care here. */
9737 offbits = (mips_opts.micromips ? 12 : 16);
9742 offbits = (mips_opts.micromips ? 12 : 16);
9747 offbits = (mips_opts.micromips ? 12 : 16);
9752 offbits = (mips_opts.micromips ? 12 : 16);
9756 fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)";
9757 offbits = (mips_opts.micromips ? 12 : 16);
9766 fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)";
9767 offbits = (mips_opts.micromips ? 12 : 16);
9778 /* Itbl support may require additional care here. */
9783 offbits = (mips_opts.micromips ? 12 : 16);
9784 /* Itbl support may require additional care here. */
9790 /* Itbl support may require additional care here. */
9794 gas_assert (!mips_opts.micromips);
9797 /* Itbl support may require additional care here. */
9803 offbits = (mips_opts.micromips ? 12 : 16);
9808 offbits = (mips_opts.micromips ? 12 : 16);
9811 gas_assert (mips_opts.micromips);
9817 gas_assert (mips_opts.micromips);
9823 gas_assert (mips_opts.micromips);
9829 gas_assert (mips_opts.micromips);
9837 if (small_offset_p (0, align, 16))
9839 /* The first case exists for M_LD_AB and M_SD_AB, which are
9840 macros for o32 but which should act like normal instructions
9843 macro_build (&offset_expr, s, fmt, treg, -1, offset_reloc[0],
9844 offset_reloc[1], offset_reloc[2], breg);
9845 else if (small_offset_p (0, align, offbits))
9848 macro_build (NULL, s, fmt, treg, breg);
9850 macro_build (NULL, s, fmt, treg,
9851 (int) offset_expr.X_add_number, breg);
9857 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9858 tempreg, breg, -1, offset_reloc[0],
9859 offset_reloc[1], offset_reloc[2]);
9861 macro_build (NULL, s, fmt, treg, tempreg);
9863 macro_build (NULL, s, fmt, treg, 0, tempreg);
9871 if (offset_expr.X_op != O_constant
9872 && offset_expr.X_op != O_symbol)
9874 as_bad (_("Expression too complex"));
9875 offset_expr.X_op = O_constant;
9878 if (HAVE_32BIT_ADDRESSES
9879 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
9883 sprintf_vma (value, offset_expr.X_add_number);
9884 as_bad (_("Number (0x%s) larger than 32 bits"), value);
9887 /* A constant expression in PIC code can be handled just as it
9888 is in non PIC code. */
9889 if (offset_expr.X_op == O_constant)
9891 expr1.X_add_number = offset_high_part (offset_expr.X_add_number,
9892 offbits == 0 ? 16 : offbits);
9893 offset_expr.X_add_number -= expr1.X_add_number;
9895 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
9897 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9898 tempreg, tempreg, breg);
9901 if (offset_expr.X_add_number != 0)
9902 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
9903 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
9904 macro_build (NULL, s, fmt, treg, tempreg);
9906 else if (offbits == 16)
9907 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg);
9909 macro_build (NULL, s, fmt, treg,
9910 (int) offset_expr.X_add_number, tempreg);
9912 else if (offbits != 16)
9914 /* The offset field is too narrow to be used for a low-part
9915 relocation, so load the whole address into the auxillary
9917 load_address (tempreg, &offset_expr, &used_at);
9919 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9920 tempreg, tempreg, breg);
9922 macro_build (NULL, s, fmt, treg, tempreg);
9924 macro_build (NULL, s, fmt, treg, 0, tempreg);
9926 else if (mips_pic == NO_PIC)
9928 /* If this is a reference to a GP relative symbol, and there
9929 is no base register, we want
9930 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
9931 Otherwise, if there is no base register, we want
9932 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
9933 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
9934 If we have a constant, we need two instructions anyhow,
9935 so we always use the latter form.
9937 If we have a base register, and this is a reference to a
9938 GP relative symbol, we want
9939 addu $tempreg,$breg,$gp
9940 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
9942 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
9943 addu $tempreg,$tempreg,$breg
9944 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
9945 With a constant we always use the latter case.
9947 With 64bit address space and no base register and $at usable,
9949 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9950 lui $at,<sym> (BFD_RELOC_HI16_S)
9951 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9954 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
9955 If we have a base register, we want
9956 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9957 lui $at,<sym> (BFD_RELOC_HI16_S)
9958 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9962 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
9964 Without $at we can't generate the optimal path for superscalar
9965 processors here since this would require two temporary registers.
9966 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9967 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9969 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
9971 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
9972 If we have a base register, we want
9973 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9974 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9976 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
9978 daddu $tempreg,$tempreg,$breg
9979 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
9981 For GP relative symbols in 64bit address space we can use
9982 the same sequence as in 32bit address space. */
9983 if (HAVE_64BIT_SYMBOLS)
9985 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
9986 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
9988 relax_start (offset_expr.X_add_symbol);
9991 macro_build (&offset_expr, s, fmt, treg,
9992 BFD_RELOC_GPREL16, mips_gp_register);
9996 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9997 tempreg, breg, mips_gp_register);
9998 macro_build (&offset_expr, s, fmt, treg,
9999 BFD_RELOC_GPREL16, tempreg);
10004 if (used_at == 0 && mips_opts.at)
10006 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
10007 BFD_RELOC_MIPS_HIGHEST);
10008 macro_build (&offset_expr, "lui", LUI_FMT, AT,
10010 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
10011 tempreg, BFD_RELOC_MIPS_HIGHER);
10013 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
10014 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
10015 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
10016 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
10022 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
10023 BFD_RELOC_MIPS_HIGHEST);
10024 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
10025 tempreg, BFD_RELOC_MIPS_HIGHER);
10026 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
10027 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
10028 tempreg, BFD_RELOC_HI16_S);
10029 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
10031 macro_build (NULL, "daddu", "d,v,t",
10032 tempreg, tempreg, breg);
10033 macro_build (&offset_expr, s, fmt, treg,
10034 BFD_RELOC_LO16, tempreg);
10037 if (mips_relax.sequence)
10044 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10045 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10047 relax_start (offset_expr.X_add_symbol);
10048 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
10052 macro_build_lui (&offset_expr, tempreg);
10053 macro_build (&offset_expr, s, fmt, treg,
10054 BFD_RELOC_LO16, tempreg);
10055 if (mips_relax.sequence)
10060 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10061 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10063 relax_start (offset_expr.X_add_symbol);
10064 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10065 tempreg, breg, mips_gp_register);
10066 macro_build (&offset_expr, s, fmt, treg,
10067 BFD_RELOC_GPREL16, tempreg);
10070 macro_build_lui (&offset_expr, tempreg);
10071 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10072 tempreg, tempreg, breg);
10073 macro_build (&offset_expr, s, fmt, treg,
10074 BFD_RELOC_LO16, tempreg);
10075 if (mips_relax.sequence)
10079 else if (!mips_big_got)
10081 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
10083 /* If this is a reference to an external symbol, we want
10084 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10086 <op> $treg,0($tempreg)
10088 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10090 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10091 <op> $treg,0($tempreg)
10093 For NewABI, we want
10094 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10095 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
10097 If there is a base register, we add it to $tempreg before
10098 the <op>. If there is a constant, we stick it in the
10099 <op> instruction. We don't handle constants larger than
10100 16 bits, because we have no way to load the upper 16 bits
10101 (actually, we could handle them for the subset of cases
10102 in which we are not using $at). */
10103 gas_assert (offset_expr.X_op == O_symbol);
10106 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10107 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
10109 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10110 tempreg, tempreg, breg);
10111 macro_build (&offset_expr, s, fmt, treg,
10112 BFD_RELOC_MIPS_GOT_OFST, tempreg);
10115 expr1.X_add_number = offset_expr.X_add_number;
10116 offset_expr.X_add_number = 0;
10117 if (expr1.X_add_number < -0x8000
10118 || expr1.X_add_number >= 0x8000)
10119 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10120 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10121 lw_reloc_type, mips_gp_register);
10123 relax_start (offset_expr.X_add_symbol);
10125 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
10126 tempreg, BFD_RELOC_LO16);
10129 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10130 tempreg, tempreg, breg);
10131 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
10133 else if (mips_big_got && !HAVE_NEWABI)
10137 /* If this is a reference to an external symbol, we want
10138 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10139 addu $tempreg,$tempreg,$gp
10140 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10141 <op> $treg,0($tempreg)
10143 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10145 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10146 <op> $treg,0($tempreg)
10147 If there is a base register, we add it to $tempreg before
10148 the <op>. If there is a constant, we stick it in the
10149 <op> instruction. We don't handle constants larger than
10150 16 bits, because we have no way to load the upper 16 bits
10151 (actually, we could handle them for the subset of cases
10152 in which we are not using $at). */
10153 gas_assert (offset_expr.X_op == O_symbol);
10154 expr1.X_add_number = offset_expr.X_add_number;
10155 offset_expr.X_add_number = 0;
10156 if (expr1.X_add_number < -0x8000
10157 || expr1.X_add_number >= 0x8000)
10158 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10159 gpdelay = reg_needs_delay (mips_gp_register);
10160 relax_start (offset_expr.X_add_symbol);
10161 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
10162 BFD_RELOC_MIPS_GOT_HI16);
10163 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
10165 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10166 BFD_RELOC_MIPS_GOT_LO16, tempreg);
10169 macro_build (NULL, "nop", "");
10170 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10171 BFD_RELOC_MIPS_GOT16, mips_gp_register);
10173 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
10174 tempreg, BFD_RELOC_LO16);
10178 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10179 tempreg, tempreg, breg);
10180 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
10182 else if (mips_big_got && HAVE_NEWABI)
10184 /* If this is a reference to an external symbol, we want
10185 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10186 add $tempreg,$tempreg,$gp
10187 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10188 <op> $treg,<ofst>($tempreg)
10189 Otherwise, for local symbols, we want:
10190 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10191 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
10192 gas_assert (offset_expr.X_op == O_symbol);
10193 expr1.X_add_number = offset_expr.X_add_number;
10194 offset_expr.X_add_number = 0;
10195 if (expr1.X_add_number < -0x8000
10196 || expr1.X_add_number >= 0x8000)
10197 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10198 relax_start (offset_expr.X_add_symbol);
10199 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
10200 BFD_RELOC_MIPS_GOT_HI16);
10201 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
10203 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10204 BFD_RELOC_MIPS_GOT_LO16, tempreg);
10206 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10207 tempreg, tempreg, breg);
10208 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
10211 offset_expr.X_add_number = expr1.X_add_number;
10212 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10213 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
10215 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10216 tempreg, tempreg, breg);
10217 macro_build (&offset_expr, s, fmt, treg,
10218 BFD_RELOC_MIPS_GOT_OFST, tempreg);
10227 gas_assert (mips_opts.micromips);
10228 gas_assert (mips_opts.insn32);
10229 start_noreorder ();
10230 macro_build (NULL, "jr", "s", RA);
10231 expr1.X_add_number = EXTRACT_OPERAND (1, IMMP, *ip) << 2;
10232 macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16);
10237 gas_assert (mips_opts.micromips);
10238 gas_assert (mips_opts.insn32);
10239 macro_build (NULL, "jr", "s", sreg);
10240 if (mips_opts.noreorder)
10241 macro_build (NULL, "nop", "");
10246 load_register (treg, &imm_expr, 0);
10250 load_register (treg, &imm_expr, 1);
10254 if (imm_expr.X_op == O_constant)
10257 load_register (AT, &imm_expr, 0);
10258 macro_build (NULL, "mtc1", "t,G", AT, treg);
10263 gas_assert (offset_expr.X_op == O_symbol
10264 && strcmp (segment_name (S_GET_SEGMENT
10265 (offset_expr.X_add_symbol)),
10267 && offset_expr.X_add_number == 0);
10268 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
10269 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
10274 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
10275 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
10276 order 32 bits of the value and the low order 32 bits are either
10277 zero or in OFFSET_EXPR. */
10278 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
10280 if (HAVE_64BIT_GPRS)
10281 load_register (treg, &imm_expr, 1);
10286 if (target_big_endian)
10298 load_register (hreg, &imm_expr, 0);
10301 if (offset_expr.X_op == O_absent)
10302 move_register (lreg, 0);
10305 gas_assert (offset_expr.X_op == O_constant);
10306 load_register (lreg, &offset_expr, 0);
10313 /* We know that sym is in the .rdata section. First we get the
10314 upper 16 bits of the address. */
10315 if (mips_pic == NO_PIC)
10317 macro_build_lui (&offset_expr, AT);
10322 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
10323 BFD_RELOC_MIPS_GOT16, mips_gp_register);
10327 /* Now we load the register(s). */
10328 if (HAVE_64BIT_GPRS)
10331 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
10336 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
10339 /* FIXME: How in the world do we deal with the possible
10341 offset_expr.X_add_number += 4;
10342 macro_build (&offset_expr, "lw", "t,o(b)",
10343 treg + 1, BFD_RELOC_LO16, AT);
10349 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
10350 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
10351 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
10352 the value and the low order 32 bits are either zero or in
10354 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
10357 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
10358 if (HAVE_64BIT_FPRS)
10360 gas_assert (HAVE_64BIT_GPRS);
10361 macro_build (NULL, "dmtc1", "t,S", AT, treg);
10365 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
10366 if (offset_expr.X_op == O_absent)
10367 macro_build (NULL, "mtc1", "t,G", 0, treg);
10370 gas_assert (offset_expr.X_op == O_constant);
10371 load_register (AT, &offset_expr, 0);
10372 macro_build (NULL, "mtc1", "t,G", AT, treg);
10378 gas_assert (offset_expr.X_op == O_symbol
10379 && offset_expr.X_add_number == 0);
10380 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
10381 if (strcmp (s, ".lit8") == 0)
10383 breg = mips_gp_register;
10384 offset_reloc[0] = BFD_RELOC_MIPS_LITERAL;
10385 offset_reloc[1] = BFD_RELOC_UNUSED;
10386 offset_reloc[2] = BFD_RELOC_UNUSED;
10390 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
10392 if (mips_pic != NO_PIC)
10393 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
10394 BFD_RELOC_MIPS_GOT16, mips_gp_register);
10397 /* FIXME: This won't work for a 64 bit address. */
10398 macro_build_lui (&offset_expr, AT);
10402 offset_reloc[0] = BFD_RELOC_LO16;
10403 offset_reloc[1] = BFD_RELOC_UNUSED;
10404 offset_reloc[2] = BFD_RELOC_UNUSED;
10411 * The MIPS assembler seems to check for X_add_number not
10412 * being double aligned and generating:
10413 * lui at,%hi(foo+1)
10415 * addiu at,at,%lo(foo+1)
10418 * But, the resulting address is the same after relocation so why
10419 * generate the extra instruction?
10421 /* Itbl support may require additional care here. */
10424 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
10433 gas_assert (!mips_opts.micromips);
10434 /* Itbl support may require additional care here. */
10437 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
10457 if (HAVE_64BIT_GPRS)
10467 if (HAVE_64BIT_GPRS)
10475 /* Even on a big endian machine $fn comes before $fn+1. We have
10476 to adjust when loading from memory. We set coproc if we must
10477 load $fn+1 first. */
10478 /* Itbl support may require additional care here. */
10479 if (!target_big_endian)
10482 if (small_offset_p (0, align, 16))
10485 if (!small_offset_p (4, align, 16))
10487 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg,
10488 -1, offset_reloc[0], offset_reloc[1],
10490 expr1.X_add_number = 0;
10494 offset_reloc[0] = BFD_RELOC_LO16;
10495 offset_reloc[1] = BFD_RELOC_UNUSED;
10496 offset_reloc[2] = BFD_RELOC_UNUSED;
10498 if (strcmp (s, "lw") == 0 && treg == breg)
10500 ep->X_add_number += 4;
10501 macro_build (ep, s, fmt, treg + 1, -1, offset_reloc[0],
10502 offset_reloc[1], offset_reloc[2], breg);
10503 ep->X_add_number -= 4;
10504 macro_build (ep, s, fmt, treg, -1, offset_reloc[0],
10505 offset_reloc[1], offset_reloc[2], breg);
10509 macro_build (ep, s, fmt, coproc ? treg + 1 : treg, -1,
10510 offset_reloc[0], offset_reloc[1], offset_reloc[2],
10512 ep->X_add_number += 4;
10513 macro_build (ep, s, fmt, coproc ? treg : treg + 1, -1,
10514 offset_reloc[0], offset_reloc[1], offset_reloc[2],
10520 if (offset_expr.X_op != O_symbol
10521 && offset_expr.X_op != O_constant)
10523 as_bad (_("Expression too complex"));
10524 offset_expr.X_op = O_constant;
10527 if (HAVE_32BIT_ADDRESSES
10528 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
10532 sprintf_vma (value, offset_expr.X_add_number);
10533 as_bad (_("Number (0x%s) larger than 32 bits"), value);
10536 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
10538 /* If this is a reference to a GP relative symbol, we want
10539 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
10540 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
10541 If we have a base register, we use this
10543 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
10544 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
10545 If this is not a GP relative symbol, we want
10546 lui $at,<sym> (BFD_RELOC_HI16_S)
10547 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
10548 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
10549 If there is a base register, we add it to $at after the
10550 lui instruction. If there is a constant, we always use
10552 if (offset_expr.X_op == O_symbol
10553 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10554 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10556 relax_start (offset_expr.X_add_symbol);
10559 tempreg = mips_gp_register;
10563 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10564 AT, breg, mips_gp_register);
10569 /* Itbl support may require additional care here. */
10570 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
10571 BFD_RELOC_GPREL16, tempreg);
10572 offset_expr.X_add_number += 4;
10574 /* Set mips_optimize to 2 to avoid inserting an
10576 hold_mips_optimize = mips_optimize;
10578 /* Itbl support may require additional care here. */
10579 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
10580 BFD_RELOC_GPREL16, tempreg);
10581 mips_optimize = hold_mips_optimize;
10585 offset_expr.X_add_number -= 4;
10588 if (offset_high_part (offset_expr.X_add_number, 16)
10589 != offset_high_part (offset_expr.X_add_number + 4, 16))
10591 load_address (AT, &offset_expr, &used_at);
10592 offset_expr.X_op = O_constant;
10593 offset_expr.X_add_number = 0;
10596 macro_build_lui (&offset_expr, AT);
10598 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
10599 /* Itbl support may require additional care here. */
10600 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
10601 BFD_RELOC_LO16, AT);
10602 /* FIXME: How do we handle overflow here? */
10603 offset_expr.X_add_number += 4;
10604 /* Itbl support may require additional care here. */
10605 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
10606 BFD_RELOC_LO16, AT);
10607 if (mips_relax.sequence)
10610 else if (!mips_big_got)
10612 /* If this is a reference to an external symbol, we want
10613 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10616 <op> $treg+1,4($at)
10618 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10620 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
10621 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
10622 If there is a base register we add it to $at before the
10623 lwc1 instructions. If there is a constant we include it
10624 in the lwc1 instructions. */
10626 expr1.X_add_number = offset_expr.X_add_number;
10627 if (expr1.X_add_number < -0x8000
10628 || expr1.X_add_number >= 0x8000 - 4)
10629 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10630 load_got_offset (AT, &offset_expr);
10633 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
10635 /* Set mips_optimize to 2 to avoid inserting an undesired
10637 hold_mips_optimize = mips_optimize;
10640 /* Itbl support may require additional care here. */
10641 relax_start (offset_expr.X_add_symbol);
10642 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
10643 BFD_RELOC_LO16, AT);
10644 expr1.X_add_number += 4;
10645 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
10646 BFD_RELOC_LO16, AT);
10648 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
10649 BFD_RELOC_LO16, AT);
10650 offset_expr.X_add_number += 4;
10651 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
10652 BFD_RELOC_LO16, AT);
10655 mips_optimize = hold_mips_optimize;
10657 else if (mips_big_got)
10661 /* If this is a reference to an external symbol, we want
10662 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10664 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
10667 <op> $treg+1,4($at)
10669 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10671 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
10672 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
10673 If there is a base register we add it to $at before the
10674 lwc1 instructions. If there is a constant we include it
10675 in the lwc1 instructions. */
10677 expr1.X_add_number = offset_expr.X_add_number;
10678 offset_expr.X_add_number = 0;
10679 if (expr1.X_add_number < -0x8000
10680 || expr1.X_add_number >= 0x8000 - 4)
10681 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10682 gpdelay = reg_needs_delay (mips_gp_register);
10683 relax_start (offset_expr.X_add_symbol);
10684 macro_build (&offset_expr, "lui", LUI_FMT,
10685 AT, BFD_RELOC_MIPS_GOT_HI16);
10686 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10687 AT, AT, mips_gp_register);
10688 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10689 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
10692 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
10693 /* Itbl support may require additional care here. */
10694 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
10695 BFD_RELOC_LO16, AT);
10696 expr1.X_add_number += 4;
10698 /* Set mips_optimize to 2 to avoid inserting an undesired
10700 hold_mips_optimize = mips_optimize;
10702 /* Itbl support may require additional care here. */
10703 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
10704 BFD_RELOC_LO16, AT);
10705 mips_optimize = hold_mips_optimize;
10706 expr1.X_add_number -= 4;
10709 offset_expr.X_add_number = expr1.X_add_number;
10711 macro_build (NULL, "nop", "");
10712 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
10713 BFD_RELOC_MIPS_GOT16, mips_gp_register);
10716 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
10717 /* Itbl support may require additional care here. */
10718 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
10719 BFD_RELOC_LO16, AT);
10720 offset_expr.X_add_number += 4;
10722 /* Set mips_optimize to 2 to avoid inserting an undesired
10724 hold_mips_optimize = mips_optimize;
10726 /* Itbl support may require additional care here. */
10727 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
10728 BFD_RELOC_LO16, AT);
10729 mips_optimize = hold_mips_optimize;
10748 /* New code added to support COPZ instructions.
10749 This code builds table entries out of the macros in mip_opcodes.
10750 R4000 uses interlocks to handle coproc delays.
10751 Other chips (like the R3000) require nops to be inserted for delays.
10753 FIXME: Currently, we require that the user handle delays.
10754 In order to fill delay slots for non-interlocked chips,
10755 we must have a way to specify delays based on the coprocessor.
10756 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
10757 What are the side-effects of the cop instruction?
10758 What cache support might we have and what are its effects?
10759 Both coprocessor & memory require delays. how long???
10760 What registers are read/set/modified?
10762 If an itbl is provided to interpret cop instructions,
10763 this knowledge can be encoded in the itbl spec. */
10777 gas_assert (!mips_opts.micromips);
10778 /* For now we just do C (same as Cz). The parameter will be
10779 stored in insn_opcode by mips_ip. */
10780 macro_build (NULL, s, "C", (int) ip->insn_opcode);
10784 move_register (dreg, sreg);
10788 gas_assert (mips_opts.micromips);
10789 gas_assert (mips_opts.insn32);
10790 dreg = micromips_to_32_reg_h_map1[EXTRACT_OPERAND (1, MH, *ip)];
10791 breg = micromips_to_32_reg_h_map2[EXTRACT_OPERAND (1, MH, *ip)];
10792 sreg = micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)];
10793 treg = micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)];
10794 move_register (dreg, sreg);
10795 move_register (breg, treg);
10801 if (mips_opts.arch == CPU_R5900)
10803 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", dreg, sreg, treg);
10807 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
10808 macro_build (NULL, "mflo", MFHL_FMT, dreg);
10815 /* The MIPS assembler some times generates shifts and adds. I'm
10816 not trying to be that fancy. GCC should do this for us
10819 load_register (AT, &imm_expr, dbl);
10820 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
10821 macro_build (NULL, "mflo", MFHL_FMT, dreg);
10834 start_noreorder ();
10837 load_register (AT, &imm_expr, dbl);
10838 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
10839 macro_build (NULL, "mflo", MFHL_FMT, dreg);
10840 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA);
10841 macro_build (NULL, "mfhi", MFHL_FMT, AT);
10843 macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6);
10846 if (mips_opts.micromips)
10847 micromips_label_expr (&label_expr);
10849 label_expr.X_add_number = 8;
10850 macro_build (&label_expr, "beq", "s,t,p", dreg, AT);
10851 macro_build (NULL, "nop", "");
10852 macro_build (NULL, "break", BRK_FMT, 6);
10853 if (mips_opts.micromips)
10854 micromips_add_label ();
10857 macro_build (NULL, "mflo", MFHL_FMT, dreg);
10870 start_noreorder ();
10873 load_register (AT, &imm_expr, dbl);
10874 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
10875 sreg, imm ? AT : treg);
10876 macro_build (NULL, "mfhi", MFHL_FMT, AT);
10877 macro_build (NULL, "mflo", MFHL_FMT, dreg);
10879 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
10882 if (mips_opts.micromips)
10883 micromips_label_expr (&label_expr);
10885 label_expr.X_add_number = 8;
10886 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
10887 macro_build (NULL, "nop", "");
10888 macro_build (NULL, "break", BRK_FMT, 6);
10889 if (mips_opts.micromips)
10890 micromips_add_label ();
10896 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
10907 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
10908 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
10912 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
10913 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
10914 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
10915 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
10919 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
10930 macro_build (NULL, "negu", "d,w", tempreg, treg);
10931 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
10935 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
10936 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
10937 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
10938 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
10947 if (imm_expr.X_op != O_constant)
10948 as_bad (_("Improper rotate count"));
10949 rot = imm_expr.X_add_number & 0x3f;
10950 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
10952 rot = (64 - rot) & 0x3f;
10954 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
10956 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
10961 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
10964 l = (rot < 0x20) ? "dsll" : "dsll32";
10965 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
10968 macro_build (NULL, l, SHFT_FMT, AT, sreg, rot);
10969 macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
10970 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
10978 if (imm_expr.X_op != O_constant)
10979 as_bad (_("Improper rotate count"));
10980 rot = imm_expr.X_add_number & 0x1f;
10981 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
10983 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f);
10988 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
10992 macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot);
10993 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
10994 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
10999 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
11001 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
11005 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
11006 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
11007 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
11008 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
11012 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
11014 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
11018 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
11019 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
11020 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
11021 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
11030 if (imm_expr.X_op != O_constant)
11031 as_bad (_("Improper rotate count"));
11032 rot = imm_expr.X_add_number & 0x3f;
11033 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
11036 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
11038 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
11043 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
11046 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
11047 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
11050 macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot);
11051 macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
11052 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
11060 if (imm_expr.X_op != O_constant)
11061 as_bad (_("Improper rotate count"));
11062 rot = imm_expr.X_add_number & 0x1f;
11063 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
11065 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot);
11070 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
11074 macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot);
11075 macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
11076 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
11082 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
11083 else if (treg == 0)
11084 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
11087 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
11088 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
11093 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
11095 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
11100 as_warn (_("Instruction %s: result is always false"),
11101 ip->insn_mo->name);
11102 move_register (dreg, 0);
11105 if (CPU_HAS_SEQ (mips_opts.arch)
11106 && -512 <= imm_expr.X_add_number
11107 && imm_expr.X_add_number < 512)
11109 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
11110 (int) imm_expr.X_add_number);
11113 if (imm_expr.X_op == O_constant
11114 && imm_expr.X_add_number >= 0
11115 && imm_expr.X_add_number < 0x10000)
11117 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
11119 else if (imm_expr.X_op == O_constant
11120 && imm_expr.X_add_number > -0x8000
11121 && imm_expr.X_add_number < 0)
11123 imm_expr.X_add_number = -imm_expr.X_add_number;
11124 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
11125 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
11127 else if (CPU_HAS_SEQ (mips_opts.arch))
11130 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11131 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
11136 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11137 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
11140 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
11143 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
11149 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
11150 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
11153 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
11155 if (imm_expr.X_op == O_constant
11156 && imm_expr.X_add_number >= -0x8000
11157 && imm_expr.X_add_number < 0x8000)
11159 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
11160 dreg, sreg, BFD_RELOC_LO16);
11164 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11165 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
11169 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
11172 case M_SGT: /* sreg > treg <==> treg < sreg */
11178 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
11181 case M_SGT_I: /* sreg > I <==> I < sreg */
11188 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11189 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
11192 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
11198 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
11199 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
11202 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
11209 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11210 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
11211 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
11215 if (imm_expr.X_op == O_constant
11216 && imm_expr.X_add_number >= -0x8000
11217 && imm_expr.X_add_number < 0x8000)
11219 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
11223 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11224 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
11228 if (imm_expr.X_op == O_constant
11229 && imm_expr.X_add_number >= -0x8000
11230 && imm_expr.X_add_number < 0x8000)
11232 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
11237 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11238 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
11243 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
11244 else if (treg == 0)
11245 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
11248 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
11249 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
11254 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
11256 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
11261 as_warn (_("Instruction %s: result is always true"),
11262 ip->insn_mo->name);
11263 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
11264 dreg, 0, BFD_RELOC_LO16);
11267 if (CPU_HAS_SEQ (mips_opts.arch)
11268 && -512 <= imm_expr.X_add_number
11269 && imm_expr.X_add_number < 512)
11271 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
11272 (int) imm_expr.X_add_number);
11275 if (imm_expr.X_op == O_constant
11276 && imm_expr.X_add_number >= 0
11277 && imm_expr.X_add_number < 0x10000)
11279 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
11281 else if (imm_expr.X_op == O_constant
11282 && imm_expr.X_add_number > -0x8000
11283 && imm_expr.X_add_number < 0)
11285 imm_expr.X_add_number = -imm_expr.X_add_number;
11286 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
11287 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
11289 else if (CPU_HAS_SEQ (mips_opts.arch))
11292 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11293 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
11298 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11299 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
11302 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
11317 if (!mips_opts.micromips)
11319 if (imm_expr.X_op == O_constant
11320 && imm_expr.X_add_number > -0x200
11321 && imm_expr.X_add_number <= 0x200)
11323 macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number);
11332 if (imm_expr.X_op == O_constant
11333 && imm_expr.X_add_number > -0x8000
11334 && imm_expr.X_add_number <= 0x8000)
11336 imm_expr.X_add_number = -imm_expr.X_add_number;
11337 macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16);
11342 load_register (AT, &imm_expr, dbl);
11343 macro_build (NULL, s2, "d,v,t", dreg, sreg, AT);
11365 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11366 macro_build (NULL, s, "s,t", sreg, AT);
11371 gas_assert (!mips_opts.micromips);
11372 gas_assert (mips_opts.isa == ISA_MIPS1);
11374 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
11375 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
11378 * Is the double cfc1 instruction a bug in the mips assembler;
11379 * or is there a reason for it?
11381 start_noreorder ();
11382 macro_build (NULL, "cfc1", "t,G", treg, RA);
11383 macro_build (NULL, "cfc1", "t,G", treg, RA);
11384 macro_build (NULL, "nop", "");
11385 expr1.X_add_number = 3;
11386 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
11387 expr1.X_add_number = 2;
11388 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
11389 macro_build (NULL, "ctc1", "t,G", AT, RA);
11390 macro_build (NULL, "nop", "");
11391 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
11393 macro_build (NULL, "ctc1", "t,G", treg, RA);
11394 macro_build (NULL, "nop", "");
11411 offbits = (mips_opts.micromips ? 12 : 16);
11417 offbits = (mips_opts.micromips ? 12 : 16);
11429 offbits = (mips_opts.micromips ? 12 : 16);
11436 offbits = (mips_opts.micromips ? 12 : 16);
11441 large_offset = !small_offset_p (off, align, offbits);
11443 expr1.X_add_number = 0;
11448 if (small_offset_p (0, align, 16))
11449 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1,
11450 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
11453 load_address (tempreg, ep, &used_at);
11455 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11456 tempreg, tempreg, breg);
11458 offset_reloc[0] = BFD_RELOC_LO16;
11459 offset_reloc[1] = BFD_RELOC_UNUSED;
11460 offset_reloc[2] = BFD_RELOC_UNUSED;
11465 else if (!ust && treg == breg)
11476 if (!target_big_endian)
11477 ep->X_add_number += off;
11479 macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg);
11481 macro_build (ep, s, "t,o(b)", tempreg, -1,
11482 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
11484 if (!target_big_endian)
11485 ep->X_add_number -= off;
11487 ep->X_add_number += off;
11489 macro_build (NULL, s2, "t,~(b)",
11490 tempreg, (int) ep->X_add_number, breg);
11492 macro_build (ep, s2, "t,o(b)", tempreg, -1,
11493 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
11495 /* If necessary, move the result in tempreg to the final destination. */
11496 if (!ust && treg != tempreg)
11498 /* Protect second load's delay slot. */
11500 move_register (treg, tempreg);
11506 if (target_big_endian == ust)
11507 ep->X_add_number += off;
11508 tempreg = ust || large_offset ? treg : AT;
11509 macro_build (ep, s, "t,o(b)", tempreg, -1,
11510 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
11512 /* For halfword transfers we need a temporary register to shuffle
11513 bytes. Unfortunately for M_USH_A we have none available before
11514 the next store as AT holds the base address. We deal with this
11515 case by clobbering TREG and then restoring it as with ULH. */
11516 tempreg = ust == large_offset ? treg : AT;
11518 macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8);
11520 if (target_big_endian == ust)
11521 ep->X_add_number -= off;
11523 ep->X_add_number += off;
11524 macro_build (ep, s2, "t,o(b)", tempreg, -1,
11525 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
11527 /* For M_USH_A re-retrieve the LSB. */
11528 if (ust && large_offset)
11530 if (target_big_endian)
11531 ep->X_add_number += off;
11533 ep->X_add_number -= off;
11534 macro_build (&expr1, "lbu", "t,o(b)", AT, -1,
11535 offset_reloc[0], offset_reloc[1], offset_reloc[2], AT);
11537 /* For ULH and M_USH_A OR the LSB in. */
11538 if (!ust || large_offset)
11540 tempreg = !large_offset ? AT : treg;
11541 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
11542 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
11547 /* FIXME: Check if this is one of the itbl macros, since they
11548 are added dynamically. */
11549 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
11552 if (!mips_opts.at && used_at)
11553 as_bad (_("Macro used $at after \".set noat\""));
11556 /* Implement macros in mips16 mode. */
11559 mips16_macro (struct mips_cl_insn *ip)
11562 int xreg, yreg, zreg, tmp;
11565 const char *s, *s2, *s3;
11567 mask = ip->insn_mo->mask;
11569 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
11570 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
11571 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
11573 expr1.X_op = O_constant;
11574 expr1.X_op_symbol = NULL;
11575 expr1.X_add_symbol = NULL;
11576 expr1.X_add_number = 1;
11595 start_noreorder ();
11596 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
11597 expr1.X_add_number = 2;
11598 macro_build (&expr1, "bnez", "x,p", yreg);
11599 macro_build (NULL, "break", "6", 7);
11601 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
11602 since that causes an overflow. We should do that as well,
11603 but I don't see how to do the comparisons without a temporary
11606 macro_build (NULL, s, "x", zreg);
11625 start_noreorder ();
11626 macro_build (NULL, s, "0,x,y", xreg, yreg);
11627 expr1.X_add_number = 2;
11628 macro_build (&expr1, "bnez", "x,p", yreg);
11629 macro_build (NULL, "break", "6", 7);
11631 macro_build (NULL, s2, "x", zreg);
11637 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
11638 macro_build (NULL, "mflo", "x", zreg);
11646 if (imm_expr.X_op != O_constant)
11647 as_bad (_("Unsupported large constant"));
11648 imm_expr.X_add_number = -imm_expr.X_add_number;
11649 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
11653 if (imm_expr.X_op != O_constant)
11654 as_bad (_("Unsupported large constant"));
11655 imm_expr.X_add_number = -imm_expr.X_add_number;
11656 macro_build (&imm_expr, "addiu", "x,k", xreg);
11660 if (imm_expr.X_op != O_constant)
11661 as_bad (_("Unsupported large constant"));
11662 imm_expr.X_add_number = -imm_expr.X_add_number;
11663 macro_build (&imm_expr, "daddiu", "y,j", yreg);
11685 goto do_reverse_branch;
11689 goto do_reverse_branch;
11701 goto do_reverse_branch;
11712 macro_build (NULL, s, "x,y", xreg, yreg);
11713 macro_build (&offset_expr, s2, "p");
11740 goto do_addone_branch_i;
11745 goto do_addone_branch_i;
11760 goto do_addone_branch_i;
11766 do_addone_branch_i:
11767 if (imm_expr.X_op != O_constant)
11768 as_bad (_("Unsupported large constant"));
11769 ++imm_expr.X_add_number;
11772 macro_build (&imm_expr, s, s3, xreg);
11773 macro_build (&offset_expr, s2, "p");
11777 expr1.X_add_number = 0;
11778 macro_build (&expr1, "slti", "x,8", yreg);
11780 move_register (xreg, yreg);
11781 expr1.X_add_number = 2;
11782 macro_build (&expr1, "bteqz", "p");
11783 macro_build (NULL, "neg", "x,w", xreg, xreg);
11787 /* Assemble an instruction into its binary format. If the instruction
11788 is a macro, set imm_expr, imm2_expr and offset_expr to the values
11789 associated with "I", "+I" and "A" operands respectively. Otherwise
11790 store the value of the relocatable field (if any) in offset_expr.
11791 In both cases set offset_reloc to the relocation operators applied
11795 mips_ip (char *str, struct mips_cl_insn *ip)
11797 bfd_boolean wrong_delay_slot_insns = FALSE;
11798 bfd_boolean need_delay_slot_ok = TRUE;
11799 struct mips_opcode *firstinsn = NULL;
11800 const struct mips_opcode *past;
11801 struct hash_control *hash;
11805 struct mips_opcode *insn;
11811 const struct mips_operand *operand;
11812 struct mips_arg_info arg;
11816 if (mips_opts.micromips)
11818 hash = micromips_op_hash;
11819 past = µmips_opcodes[bfd_micromips_num_opcodes];
11824 past = &mips_opcodes[NUMOPCODES];
11826 forced_insn_length = 0;
11829 /* We first try to match an instruction up to a space or to the end. */
11830 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
11833 /* Make a copy of the instruction so that we can fiddle with it. */
11834 name = alloca (end + 1);
11835 memcpy (name, str, end);
11840 insn = (struct mips_opcode *) hash_find (hash, name);
11842 if (insn != NULL || !mips_opts.micromips)
11844 if (forced_insn_length)
11847 /* See if there's an instruction size override suffix,
11848 either `16' or `32', at the end of the mnemonic proper,
11849 that defines the operation, i.e. before the first `.'
11850 character if any. Strip it and retry. */
11851 dot = strchr (name, '.');
11852 opend = dot != NULL ? dot - name : end;
11855 if (name[opend - 2] == '1' && name[opend - 1] == '6')
11856 forced_insn_length = 2;
11857 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
11858 forced_insn_length = 4;
11861 memcpy (name + opend - 2, name + opend, end - opend + 1);
11865 insn_error = _("Unrecognized opcode");
11869 /* For microMIPS instructions placed in a fixed-length branch delay slot
11870 we make up to two passes over the relevant fragment of the opcode
11871 table. First we try instructions that meet the delay slot's length
11872 requirement. If none matched, then we retry with the remaining ones
11873 and if one matches, then we use it and then issue an appropriate
11874 warning later on. */
11875 argsStart = s = str + end;
11878 bfd_boolean delay_slot_ok;
11879 bfd_boolean size_ok;
11881 bfd_boolean more_alts;
11883 gas_assert (strcmp (insn->name, name) == 0);
11885 ok = is_opcode_valid (insn);
11886 size_ok = is_size_valid (insn);
11887 delay_slot_ok = is_delay_slot_valid (insn);
11888 if (!delay_slot_ok && !wrong_delay_slot_insns)
11891 wrong_delay_slot_insns = TRUE;
11893 more_alts = (insn + 1 < past
11894 && strcmp (insn[0].name, insn[1].name) == 0);
11895 if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok)
11897 static char buf[256];
11904 if (wrong_delay_slot_insns && need_delay_slot_ok)
11906 gas_assert (firstinsn);
11907 need_delay_slot_ok = FALSE;
11917 sprintf (buf, _("Opcode not supported on this processor: %s (%s)"),
11918 mips_cpu_info_from_arch (mips_opts.arch)->name,
11919 mips_cpu_info_from_isa (mips_opts.isa)->name);
11920 else if (mips_opts.insn32)
11921 sprintf (buf, _("Opcode not supported in the `insn32' mode"));
11923 sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"),
11924 8 * forced_insn_length);
11930 imm_expr.X_op = O_absent;
11931 imm2_expr.X_op = O_absent;
11932 offset_expr.X_op = O_absent;
11933 offset_reloc[0] = BFD_RELOC_UNUSED;
11934 offset_reloc[1] = BFD_RELOC_UNUSED;
11935 offset_reloc[2] = BFD_RELOC_UNUSED;
11937 create_insn (ip, insn);
11939 memset (&arg, 0, sizeof (arg));
11942 arg.last_regno = ILLEGAL_REG;
11943 arg.dest_regno = ILLEGAL_REG;
11944 arg.soft_match = (more_alts
11945 || (wrong_delay_slot_insns && need_delay_slot_ok));
11946 for (args = insn->args;; ++args)
11948 SKIP_SPACE_TABS (s);
11951 /* Handle unary instructions in which only one operand is given.
11952 The source is then the same as the destination. */
11953 if (arg.opnum == 1 && *args == ',')
11966 /* Treat elided base registers as $0. */
11967 if (strcmp (args, "(b)") == 0)
11970 /* Fail the match if there were too few operands. */
11974 /* Successful match. */
11975 if (arg.dest_regno == arg.last_regno
11976 && strncmp (ip->insn_mo->name, "jalr", 4) == 0)
11978 if (arg.opnum == 2)
11979 as_bad (_("Source and destination must be different"));
11980 else if (arg.last_regno == 31)
11981 as_bad (_("A destination register must be supplied"));
11983 check_completed_insn (&arg);
11987 /* Fail the match if the line has too many operands. */
11991 /* Handle characters that need to match exactly. */
11992 if (*args == '(' || *args == ')' || *args == ',')
12002 /* Handle special macro operands. Work out the properties of
12005 arg.optional_reg = FALSE;
12006 arg.lax_max = FALSE;
12025 /* If these integer forms come last, there is no other
12026 form of the instruction that could match. Prefer to
12027 give detailed error messages where possible. */
12029 arg.soft_match = FALSE;
12033 /* "+I" is like "I", except that imm2_expr is used. */
12034 my_getExpression (&imm2_expr, s);
12035 if (imm2_expr.X_op != O_big
12036 && imm2_expr.X_op != O_constant)
12037 insn_error = _("absolute expression required");
12038 if (HAVE_32BIT_GPRS)
12039 normalize_constant_expr (&imm2_expr);
12045 *offset_reloc = BFD_RELOC_MIPS_JMP;
12075 /* If these integer forms come last, there is no other
12076 form of the instruction that could match. Prefer to
12077 give detailed error messages where possible. */
12079 arg.soft_match = FALSE;
12087 /* We have already matched a comma by this point, so the register
12088 is only optional if there is another operand to come. */
12089 gas_assert (arg.opnum == 2);
12090 arg.optional_reg = (args[1] == ',');
12094 my_getExpression (&imm_expr, s);
12095 if (imm_expr.X_op != O_big
12096 && imm_expr.X_op != O_constant)
12097 insn_error = _("absolute expression required");
12098 if (HAVE_32BIT_GPRS)
12099 normalize_constant_expr (&imm_expr);
12104 my_getSmallExpression (&offset_expr, offset_reloc, s);
12105 if (offset_expr.X_op == O_register)
12107 /* Assume that the offset has been elided and that what
12108 we saw was a base register. The match will fail later
12109 if that assumption turns out to be wrong. */
12110 offset_expr.X_op = O_constant;
12111 offset_expr.X_add_number = 0;
12115 normalize_address_expr (&offset_expr);
12121 s = parse_float_constant (s, &imm_expr, &offset_expr, 8, TRUE);
12125 s = parse_float_constant (s, &imm_expr, &offset_expr, 8, FALSE);
12129 s = parse_float_constant (s, &imm_expr, &offset_expr, 4, TRUE);
12133 s = parse_float_constant (s, &imm_expr, &offset_expr, 4, FALSE);
12136 /* ??? This is the traditional behavior, but is flaky if
12137 there are alternative versions of the same instruction
12138 for different subarchitectures. The next alternative
12139 might not be suitable. */
12141 /* For compatibility with older assemblers, we accept
12142 0x8000-0xffff as signed 16-bit numbers when only
12143 signed numbers are allowed. */
12144 arg.lax_max = !more_alts;
12146 /* Only accept non-constant operands if this is the
12147 final alternative. Later alternatives might include
12148 a macro implementation. */
12149 arg.allow_nonconst = !more_alts;
12153 /* There are no macro implementations for out-of-range values. */
12154 arg.allow_nonconst = TRUE;
12158 /* There should always be a macro implementation. */
12159 arg.allow_nonconst = FALSE;
12163 *offset_reloc = BFD_RELOC_16_PCREL_S2;
12167 *offset_reloc = BFD_RELOC_MIPS_JMP;
12171 gas_assert (mips_opts.micromips);
12178 /* We have already matched a comma by this point,
12179 so the register is only optional if there is another
12180 operand to come. */
12181 gas_assert (arg.opnum == 2);
12182 arg.optional_reg = (args[2] == ',');
12187 if (!forced_insn_length)
12188 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
12190 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
12192 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
12198 operand = (mips_opts.micromips
12199 ? decode_micromips_operand (args)
12200 : decode_mips_operand (args));
12204 s = match_operand (&arg, operand, s);
12205 if (!s && arg.optional_reg)
12207 /* Assume that the register has been elided and is the
12208 same as the first operand. */
12209 arg.optional_reg = FALSE;
12212 SKIP_SPACE_TABS (s);
12213 s = match_operand (&arg, operand, s);
12218 /* Skip prefixes. */
12219 if (*args == '+' || *args == 'm')
12224 /* Args don't match. */
12226 insn_error = _("Illegal operands");
12232 if (wrong_delay_slot_insns && need_delay_slot_ok)
12234 gas_assert (firstinsn);
12235 need_delay_slot_ok = FALSE;
12244 /* As for mips_ip, but used when assembling MIPS16 code.
12245 Also set forced_insn_length to the resulting instruction size in
12246 bytes if the user explicitly requested a small or extended instruction. */
12249 mips16_ip (char *str, struct mips_cl_insn *ip)
12253 struct mips_opcode *insn;
12256 const struct mips_operand *operand;
12257 const struct mips_operand *ext_operand;
12258 struct mips_arg_info arg;
12262 forced_insn_length = 0;
12264 for (s = str; ISLOWER (*s); ++s)
12276 if (s[1] == 't' && s[2] == ' ')
12279 forced_insn_length = 2;
12283 else if (s[1] == 'e' && s[2] == ' ')
12286 forced_insn_length = 4;
12290 /* Fall through. */
12292 insn_error = _("unknown opcode");
12296 if (mips_opts.noautoextend && !forced_insn_length)
12297 forced_insn_length = 2;
12299 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
12301 insn_error = _("unrecognized opcode");
12309 bfd_boolean more_alts;
12312 gas_assert (strcmp (insn->name, str) == 0);
12314 ok = is_opcode_valid_16 (insn);
12315 more_alts = (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
12316 && strcmp (insn[0].name, insn[1].name) == 0);
12328 static char buf[100];
12330 _("Opcode not supported on this processor: %s (%s)"),
12331 mips_cpu_info_from_arch (mips_opts.arch)->name,
12332 mips_cpu_info_from_isa (mips_opts.isa)->name);
12339 create_insn (ip, insn);
12340 imm_expr.X_op = O_absent;
12341 imm2_expr.X_op = O_absent;
12342 offset_expr.X_op = O_absent;
12343 offset_reloc[0] = BFD_RELOC_UNUSED;
12344 offset_reloc[1] = BFD_RELOC_UNUSED;
12345 offset_reloc[2] = BFD_RELOC_UNUSED;
12348 memset (&arg, 0, sizeof (arg));
12351 arg.last_regno = ILLEGAL_REG;
12352 arg.dest_regno = ILLEGAL_REG;
12353 arg.soft_match = more_alts;
12355 for (args = insn->args; 1; ++args)
12359 SKIP_SPACE_TABS (s);
12364 /* Handle unary instructions in which only one operand is given.
12365 The source is then the same as the destination. */
12366 if (arg.opnum == 1 && *args == ',')
12376 /* Fail the match if there were too few operands. */
12380 /* Successful match. Stuff the immediate value in now, if
12382 if (insn->pinfo == INSN_MACRO)
12384 gas_assert (relax_char == 0);
12385 gas_assert (*offset_reloc == BFD_RELOC_UNUSED);
12387 else if (relax_char
12388 && offset_expr.X_op == O_constant
12389 && calculate_reloc (*offset_reloc,
12390 offset_expr.X_add_number,
12393 mips16_immed (NULL, 0, relax_char, *offset_reloc, value,
12394 forced_insn_length, &ip->insn_opcode);
12395 offset_expr.X_op = O_absent;
12396 *offset_reloc = BFD_RELOC_UNUSED;
12398 else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED)
12400 if (forced_insn_length == 2)
12401 as_bad (_("invalid unextended operand value"));
12402 forced_insn_length = 4;
12403 ip->insn_opcode |= MIPS16_EXTEND;
12405 else if (relax_char)
12406 *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char;
12408 check_completed_insn (&arg);
12412 /* Fail the match if the line has too many operands. */
12416 /* Handle characters that need to match exactly. */
12417 if (*args == '(' || *args == ')' || *args == ',')
12428 arg.optional_reg = FALSE;
12434 arg.optional_reg = (args[1] == ',');
12446 my_getExpression (&imm_expr, s);
12447 if (imm_expr.X_op != O_big
12448 && imm_expr.X_op != O_constant)
12449 insn_error = _("absolute expression required");
12450 if (HAVE_32BIT_GPRS)
12451 normalize_constant_expr (&imm_expr);
12457 *offset_reloc = BFD_RELOC_MIPS16_JMP;
12458 ip->insn_opcode <<= 16;
12462 operand = decode_mips16_operand (c, FALSE);
12466 /* '6' is a special case. It is used for BREAK and SDBBP,
12467 whose operands are only meaningful to the software that decodes
12468 them. This means that there is no architectural reason why
12469 they cannot be prefixed by EXTEND, but in practice,
12470 exception handlers will only look at the instruction
12471 itself. We therefore allow '6' to be extended when
12472 disassembling but not when assembling. */
12473 if (operand->type != OP_PCREL && c != '6')
12475 ext_operand = decode_mips16_operand (c, TRUE);
12476 if (operand != ext_operand)
12478 /* Parse the expression, allowing relocation operators. */
12479 i = my_getSmallExpression (&offset_expr, offset_reloc, s);
12482 if (offset_expr.X_op == O_register)
12484 /* Handle elided offsets, which are equivalent to 0. */
12487 offset_expr.X_op = O_constant;
12488 offset_expr.X_add_number = 0;
12492 /* Fail the match. */
12495 /* '8' is used for SLTI(U) and has traditionally not
12496 been allowed to take relocation operators. */
12497 if (i > 0 && (ext_operand->size != 16 || c == '8'))
12504 s = match_operand (&arg, operand, s);
12505 if (!s && arg.optional_reg)
12507 /* Assume that the register has been elided and is the
12508 same as the first operand. */
12509 arg.optional_reg = FALSE;
12512 SKIP_SPACE_TABS (s);
12513 s = match_operand (&arg, operand, s);
12520 /* Args don't match. */
12528 insn_error = _("illegal operands");
12534 /* This structure holds information we know about a mips16 immediate
12537 struct mips16_immed_operand
12539 /* The type code used in the argument string in the opcode table. */
12541 /* The number of bits in the short form of the opcode. */
12543 /* The number of bits in the extended form of the opcode. */
12545 /* The amount by which the short form is shifted when it is used;
12546 for example, the sw instruction has a shift count of 2. */
12548 /* The amount by which the short form is shifted when it is stored
12549 into the instruction code. */
12551 /* Non-zero if the short form is unsigned. */
12553 /* Non-zero if the extended form is unsigned. */
12555 /* Non-zero if the value is PC relative. */
12559 /* The mips16 immediate operand types. */
12561 static const struct mips16_immed_operand mips16_immed_operands[] =
12563 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
12564 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
12565 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
12566 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
12567 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
12568 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
12569 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
12570 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
12571 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
12572 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
12573 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
12574 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
12575 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
12576 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
12577 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
12578 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
12579 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
12580 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
12581 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
12582 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
12583 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
12586 #define MIPS16_NUM_IMMED \
12587 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
12589 /* Marshal immediate value VAL for an extended MIPS16 instruction.
12590 NBITS is the number of significant bits in VAL. */
12592 static unsigned long
12593 mips16_immed_extend (offsetT val, unsigned int nbits)
12598 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
12601 else if (nbits == 15)
12603 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
12608 extval = ((val & 0x1f) << 6) | (val & 0x20);
12611 return (extval << 16) | val;
12614 /* Install immediate value VAL into MIPS16 instruction *INSN,
12615 extending it if necessary. The instruction in *INSN may
12616 already be extended.
12618 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
12619 if none. In the former case, VAL is a 16-bit number with no
12620 defined signedness.
12622 TYPE is the type of the immediate field. USER_INSN_LENGTH
12623 is the length that the user requested, or 0 if none. */
12626 mips16_immed (char *file, unsigned int line, int type,
12627 bfd_reloc_code_real_type reloc, offsetT val,
12628 unsigned int user_insn_length, unsigned long *insn)
12630 const struct mips16_immed_operand *op;
12631 int mintiny, maxtiny;
12633 op = mips16_immed_operands;
12634 while (op->type != type)
12637 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
12642 if (type == '<' || type == '>' || type == '[' || type == ']')
12645 maxtiny = 1 << op->nbits;
12650 maxtiny = (1 << op->nbits) - 1;
12652 if (reloc != BFD_RELOC_UNUSED)
12657 mintiny = - (1 << (op->nbits - 1));
12658 maxtiny = (1 << (op->nbits - 1)) - 1;
12659 if (reloc != BFD_RELOC_UNUSED)
12660 val = SEXT_16BIT (val);
12663 /* Branch offsets have an implicit 0 in the lowest bit. */
12664 if (type == 'p' || type == 'q')
12667 if ((val & ((1 << op->shift) - 1)) != 0
12668 || val < (mintiny << op->shift)
12669 || val > (maxtiny << op->shift))
12671 /* We need an extended instruction. */
12672 if (user_insn_length == 2)
12673 as_bad_where (file, line, _("invalid unextended operand value"));
12675 *insn |= MIPS16_EXTEND;
12677 else if (user_insn_length == 4)
12679 /* The operand doesn't force an unextended instruction to be extended.
12680 Warn if the user wanted an extended instruction anyway. */
12681 *insn |= MIPS16_EXTEND;
12682 as_warn_where (file, line,
12683 _("extended operand requested but not required"));
12686 if (mips16_opcode_length (*insn) == 2)
12690 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
12691 insnval <<= op->op_shift;
12696 long minext, maxext;
12698 if (reloc == BFD_RELOC_UNUSED)
12703 maxext = (1 << op->extbits) - 1;
12707 minext = - (1 << (op->extbits - 1));
12708 maxext = (1 << (op->extbits - 1)) - 1;
12710 if (val < minext || val > maxext)
12711 as_bad_where (file, line,
12712 _("operand value out of range for instruction"));
12715 *insn |= mips16_immed_extend (val, op->extbits);
12719 struct percent_op_match
12722 bfd_reloc_code_real_type reloc;
12725 static const struct percent_op_match mips_percent_op[] =
12727 {"%lo", BFD_RELOC_LO16},
12728 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
12729 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
12730 {"%call16", BFD_RELOC_MIPS_CALL16},
12731 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
12732 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
12733 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
12734 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
12735 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
12736 {"%got", BFD_RELOC_MIPS_GOT16},
12737 {"%gp_rel", BFD_RELOC_GPREL16},
12738 {"%half", BFD_RELOC_16},
12739 {"%highest", BFD_RELOC_MIPS_HIGHEST},
12740 {"%higher", BFD_RELOC_MIPS_HIGHER},
12741 {"%neg", BFD_RELOC_MIPS_SUB},
12742 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
12743 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
12744 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
12745 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
12746 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
12747 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
12748 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
12749 {"%hi", BFD_RELOC_HI16_S}
12752 static const struct percent_op_match mips16_percent_op[] =
12754 {"%lo", BFD_RELOC_MIPS16_LO16},
12755 {"%gprel", BFD_RELOC_MIPS16_GPREL},
12756 {"%got", BFD_RELOC_MIPS16_GOT16},
12757 {"%call16", BFD_RELOC_MIPS16_CALL16},
12758 {"%hi", BFD_RELOC_MIPS16_HI16_S},
12759 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
12760 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
12761 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
12762 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
12763 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
12764 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
12765 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
12769 /* Return true if *STR points to a relocation operator. When returning true,
12770 move *STR over the operator and store its relocation code in *RELOC.
12771 Leave both *STR and *RELOC alone when returning false. */
12774 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
12776 const struct percent_op_match *percent_op;
12779 if (mips_opts.mips16)
12781 percent_op = mips16_percent_op;
12782 limit = ARRAY_SIZE (mips16_percent_op);
12786 percent_op = mips_percent_op;
12787 limit = ARRAY_SIZE (mips_percent_op);
12790 for (i = 0; i < limit; i++)
12791 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
12793 int len = strlen (percent_op[i].str);
12795 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
12798 *str += strlen (percent_op[i].str);
12799 *reloc = percent_op[i].reloc;
12801 /* Check whether the output BFD supports this relocation.
12802 If not, issue an error and fall back on something safe. */
12803 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
12805 as_bad (_("relocation %s isn't supported by the current ABI"),
12806 percent_op[i].str);
12807 *reloc = BFD_RELOC_UNUSED;
12815 /* Parse string STR as a 16-bit relocatable operand. Store the
12816 expression in *EP and the relocations in the array starting
12817 at RELOC. Return the number of relocation operators used.
12819 On exit, EXPR_END points to the first character after the expression. */
12822 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
12825 bfd_reloc_code_real_type reversed_reloc[3];
12826 size_t reloc_index, i;
12827 int crux_depth, str_depth;
12830 /* Search for the start of the main expression, recoding relocations
12831 in REVERSED_RELOC. End the loop with CRUX pointing to the start
12832 of the main expression and with CRUX_DEPTH containing the number
12833 of open brackets at that point. */
12840 crux_depth = str_depth;
12842 /* Skip over whitespace and brackets, keeping count of the number
12844 while (*str == ' ' || *str == '\t' || *str == '(')
12849 && reloc_index < (HAVE_NEWABI ? 3 : 1)
12850 && parse_relocation (&str, &reversed_reloc[reloc_index]));
12852 my_getExpression (ep, crux);
12855 /* Match every open bracket. */
12856 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
12860 if (crux_depth > 0)
12861 as_bad (_("unclosed '('"));
12865 if (reloc_index != 0)
12867 prev_reloc_op_frag = frag_now;
12868 for (i = 0; i < reloc_index; i++)
12869 reloc[i] = reversed_reloc[reloc_index - 1 - i];
12872 return reloc_index;
12876 my_getExpression (expressionS *ep, char *str)
12880 save_in = input_line_pointer;
12881 input_line_pointer = str;
12883 expr_end = input_line_pointer;
12884 input_line_pointer = save_in;
12888 md_atof (int type, char *litP, int *sizeP)
12890 return ieee_md_atof (type, litP, sizeP, target_big_endian);
12894 md_number_to_chars (char *buf, valueT val, int n)
12896 if (target_big_endian)
12897 number_to_chars_bigendian (buf, val, n);
12899 number_to_chars_littleendian (buf, val, n);
12902 static int support_64bit_objects(void)
12904 const char **list, **l;
12907 list = bfd_target_list ();
12908 for (l = list; *l != NULL; l++)
12909 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
12910 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
12912 yes = (*l != NULL);
12917 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
12918 NEW_VALUE. Warn if another value was already specified. Note:
12919 we have to defer parsing the -march and -mtune arguments in order
12920 to handle 'from-abi' correctly, since the ABI might be specified
12921 in a later argument. */
12924 mips_set_option_string (const char **string_ptr, const char *new_value)
12926 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
12927 as_warn (_("A different %s was already specified, is now %s"),
12928 string_ptr == &mips_arch_string ? "-march" : "-mtune",
12931 *string_ptr = new_value;
12935 md_parse_option (int c, char *arg)
12939 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
12940 if (c == mips_ases[i].option_on || c == mips_ases[i].option_off)
12942 file_ase_explicit |= mips_set_ase (&mips_ases[i],
12943 c == mips_ases[i].option_on);
12949 case OPTION_CONSTRUCT_FLOATS:
12950 mips_disable_float_construction = 0;
12953 case OPTION_NO_CONSTRUCT_FLOATS:
12954 mips_disable_float_construction = 1;
12966 target_big_endian = 1;
12970 target_big_endian = 0;
12976 else if (arg[0] == '0')
12978 else if (arg[0] == '1')
12988 mips_debug = atoi (arg);
12992 file_mips_isa = ISA_MIPS1;
12996 file_mips_isa = ISA_MIPS2;
13000 file_mips_isa = ISA_MIPS3;
13004 file_mips_isa = ISA_MIPS4;
13008 file_mips_isa = ISA_MIPS5;
13011 case OPTION_MIPS32:
13012 file_mips_isa = ISA_MIPS32;
13015 case OPTION_MIPS32R2:
13016 file_mips_isa = ISA_MIPS32R2;
13019 case OPTION_MIPS64R2:
13020 file_mips_isa = ISA_MIPS64R2;
13023 case OPTION_MIPS64:
13024 file_mips_isa = ISA_MIPS64;
13028 mips_set_option_string (&mips_tune_string, arg);
13032 mips_set_option_string (&mips_arch_string, arg);
13036 mips_set_option_string (&mips_arch_string, "4650");
13037 mips_set_option_string (&mips_tune_string, "4650");
13040 case OPTION_NO_M4650:
13044 mips_set_option_string (&mips_arch_string, "4010");
13045 mips_set_option_string (&mips_tune_string, "4010");
13048 case OPTION_NO_M4010:
13052 mips_set_option_string (&mips_arch_string, "4100");
13053 mips_set_option_string (&mips_tune_string, "4100");
13056 case OPTION_NO_M4100:
13060 mips_set_option_string (&mips_arch_string, "3900");
13061 mips_set_option_string (&mips_tune_string, "3900");
13064 case OPTION_NO_M3900:
13067 case OPTION_MICROMIPS:
13068 if (mips_opts.mips16 == 1)
13070 as_bad (_("-mmicromips cannot be used with -mips16"));
13073 mips_opts.micromips = 1;
13074 mips_no_prev_insn ();
13077 case OPTION_NO_MICROMIPS:
13078 mips_opts.micromips = 0;
13079 mips_no_prev_insn ();
13082 case OPTION_MIPS16:
13083 if (mips_opts.micromips == 1)
13085 as_bad (_("-mips16 cannot be used with -micromips"));
13088 mips_opts.mips16 = 1;
13089 mips_no_prev_insn ();
13092 case OPTION_NO_MIPS16:
13093 mips_opts.mips16 = 0;
13094 mips_no_prev_insn ();
13097 case OPTION_FIX_24K:
13101 case OPTION_NO_FIX_24K:
13105 case OPTION_FIX_LOONGSON2F_JUMP:
13106 mips_fix_loongson2f_jump = TRUE;
13109 case OPTION_NO_FIX_LOONGSON2F_JUMP:
13110 mips_fix_loongson2f_jump = FALSE;
13113 case OPTION_FIX_LOONGSON2F_NOP:
13114 mips_fix_loongson2f_nop = TRUE;
13117 case OPTION_NO_FIX_LOONGSON2F_NOP:
13118 mips_fix_loongson2f_nop = FALSE;
13121 case OPTION_FIX_VR4120:
13122 mips_fix_vr4120 = 1;
13125 case OPTION_NO_FIX_VR4120:
13126 mips_fix_vr4120 = 0;
13129 case OPTION_FIX_VR4130:
13130 mips_fix_vr4130 = 1;
13133 case OPTION_NO_FIX_VR4130:
13134 mips_fix_vr4130 = 0;
13137 case OPTION_FIX_CN63XXP1:
13138 mips_fix_cn63xxp1 = TRUE;
13141 case OPTION_NO_FIX_CN63XXP1:
13142 mips_fix_cn63xxp1 = FALSE;
13145 case OPTION_RELAX_BRANCH:
13146 mips_relax_branch = 1;
13149 case OPTION_NO_RELAX_BRANCH:
13150 mips_relax_branch = 0;
13153 case OPTION_INSN32:
13154 mips_opts.insn32 = TRUE;
13157 case OPTION_NO_INSN32:
13158 mips_opts.insn32 = FALSE;
13161 case OPTION_MSHARED:
13162 mips_in_shared = TRUE;
13165 case OPTION_MNO_SHARED:
13166 mips_in_shared = FALSE;
13169 case OPTION_MSYM32:
13170 mips_opts.sym32 = TRUE;
13173 case OPTION_MNO_SYM32:
13174 mips_opts.sym32 = FALSE;
13177 /* When generating ELF code, we permit -KPIC and -call_shared to
13178 select SVR4_PIC, and -non_shared to select no PIC. This is
13179 intended to be compatible with Irix 5. */
13180 case OPTION_CALL_SHARED:
13181 mips_pic = SVR4_PIC;
13182 mips_abicalls = TRUE;
13185 case OPTION_CALL_NONPIC:
13187 mips_abicalls = TRUE;
13190 case OPTION_NON_SHARED:
13192 mips_abicalls = FALSE;
13195 /* The -xgot option tells the assembler to use 32 bit offsets
13196 when accessing the got in SVR4_PIC mode. It is for Irix
13203 g_switch_value = atoi (arg);
13207 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
13210 mips_abi = O32_ABI;
13214 mips_abi = N32_ABI;
13218 mips_abi = N64_ABI;
13219 if (!support_64bit_objects())
13220 as_fatal (_("No compiled in support for 64 bit object file format"));
13224 file_mips_gp32 = 1;
13228 file_mips_gp32 = 0;
13232 file_mips_fp32 = 1;
13236 file_mips_fp32 = 0;
13239 case OPTION_SINGLE_FLOAT:
13240 file_mips_single_float = 1;
13243 case OPTION_DOUBLE_FLOAT:
13244 file_mips_single_float = 0;
13247 case OPTION_SOFT_FLOAT:
13248 file_mips_soft_float = 1;
13251 case OPTION_HARD_FLOAT:
13252 file_mips_soft_float = 0;
13256 if (strcmp (arg, "32") == 0)
13257 mips_abi = O32_ABI;
13258 else if (strcmp (arg, "o64") == 0)
13259 mips_abi = O64_ABI;
13260 else if (strcmp (arg, "n32") == 0)
13261 mips_abi = N32_ABI;
13262 else if (strcmp (arg, "64") == 0)
13264 mips_abi = N64_ABI;
13265 if (! support_64bit_objects())
13266 as_fatal (_("No compiled in support for 64 bit object file "
13269 else if (strcmp (arg, "eabi") == 0)
13270 mips_abi = EABI_ABI;
13273 as_fatal (_("invalid abi -mabi=%s"), arg);
13278 case OPTION_M7000_HILO_FIX:
13279 mips_7000_hilo_fix = TRUE;
13282 case OPTION_MNO_7000_HILO_FIX:
13283 mips_7000_hilo_fix = FALSE;
13286 case OPTION_MDEBUG:
13287 mips_flag_mdebug = TRUE;
13290 case OPTION_NO_MDEBUG:
13291 mips_flag_mdebug = FALSE;
13295 mips_flag_pdr = TRUE;
13298 case OPTION_NO_PDR:
13299 mips_flag_pdr = FALSE;
13302 case OPTION_MVXWORKS_PIC:
13303 mips_pic = VXWORKS_PIC;
13307 if (strcmp (arg, "2008") == 0)
13308 mips_flag_nan2008 = TRUE;
13309 else if (strcmp (arg, "legacy") == 0)
13310 mips_flag_nan2008 = FALSE;
13313 as_fatal (_("Invalid NaN setting -mnan=%s"), arg);
13322 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
13327 /* Set up globals to generate code for the ISA or processor
13328 described by INFO. */
13331 mips_set_architecture (const struct mips_cpu_info *info)
13335 file_mips_arch = info->cpu;
13336 mips_opts.arch = info->cpu;
13337 mips_opts.isa = info->isa;
13342 /* Likewise for tuning. */
13345 mips_set_tune (const struct mips_cpu_info *info)
13348 mips_tune = info->cpu;
13353 mips_after_parse_args (void)
13355 const struct mips_cpu_info *arch_info = 0;
13356 const struct mips_cpu_info *tune_info = 0;
13358 /* GP relative stuff not working for PE */
13359 if (strncmp (TARGET_OS, "pe", 2) == 0)
13361 if (g_switch_seen && g_switch_value != 0)
13362 as_bad (_("-G not supported in this configuration."));
13363 g_switch_value = 0;
13366 if (mips_abi == NO_ABI)
13367 mips_abi = MIPS_DEFAULT_ABI;
13369 /* The following code determines the architecture and register size.
13370 Similar code was added to GCC 3.3 (see override_options() in
13371 config/mips/mips.c). The GAS and GCC code should be kept in sync
13372 as much as possible. */
13374 if (mips_arch_string != 0)
13375 arch_info = mips_parse_cpu ("-march", mips_arch_string);
13377 if (file_mips_isa != ISA_UNKNOWN)
13379 /* Handle -mipsN. At this point, file_mips_isa contains the
13380 ISA level specified by -mipsN, while arch_info->isa contains
13381 the -march selection (if any). */
13382 if (arch_info != 0)
13384 /* -march takes precedence over -mipsN, since it is more descriptive.
13385 There's no harm in specifying both as long as the ISA levels
13387 if (file_mips_isa != arch_info->isa)
13388 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
13389 mips_cpu_info_from_isa (file_mips_isa)->name,
13390 mips_cpu_info_from_isa (arch_info->isa)->name);
13393 arch_info = mips_cpu_info_from_isa (file_mips_isa);
13396 if (arch_info == 0)
13398 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
13399 gas_assert (arch_info);
13402 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
13403 as_bad (_("-march=%s is not compatible with the selected ABI"),
13406 mips_set_architecture (arch_info);
13408 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
13409 if (mips_tune_string != 0)
13410 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
13412 if (tune_info == 0)
13413 mips_set_tune (arch_info);
13415 mips_set_tune (tune_info);
13417 if (file_mips_gp32 >= 0)
13419 /* The user specified the size of the integer registers. Make sure
13420 it agrees with the ABI and ISA. */
13421 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
13422 as_bad (_("-mgp64 used with a 32-bit processor"));
13423 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
13424 as_bad (_("-mgp32 used with a 64-bit ABI"));
13425 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
13426 as_bad (_("-mgp64 used with a 32-bit ABI"));
13430 /* Infer the integer register size from the ABI and processor.
13431 Restrict ourselves to 32-bit registers if that's all the
13432 processor has, or if the ABI cannot handle 64-bit registers. */
13433 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
13434 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
13437 switch (file_mips_fp32)
13441 /* No user specified float register size.
13442 ??? GAS treats single-float processors as though they had 64-bit
13443 float registers (although it complains when double-precision
13444 instructions are used). As things stand, saying they have 32-bit
13445 registers would lead to spurious "register must be even" messages.
13446 So here we assume float registers are never smaller than the
13448 if (file_mips_gp32 == 0)
13449 /* 64-bit integer registers implies 64-bit float registers. */
13450 file_mips_fp32 = 0;
13451 else if ((mips_opts.ase & FP64_ASES)
13452 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
13453 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
13454 file_mips_fp32 = 0;
13456 /* 32-bit float registers. */
13457 file_mips_fp32 = 1;
13460 /* The user specified the size of the float registers. Check if it
13461 agrees with the ABI and ISA. */
13463 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
13464 as_bad (_("-mfp64 used with a 32-bit fpu"));
13465 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
13466 && !ISA_HAS_MXHC1 (mips_opts.isa))
13467 as_warn (_("-mfp64 used with a 32-bit ABI"));
13470 if (ABI_NEEDS_64BIT_REGS (mips_abi))
13471 as_warn (_("-mfp32 used with a 64-bit ABI"));
13475 /* End of GCC-shared inference code. */
13477 /* This flag is set when we have a 64-bit capable CPU but use only
13478 32-bit wide registers. Note that EABI does not use it. */
13479 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
13480 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
13481 || mips_abi == O32_ABI))
13482 mips_32bitmode = 1;
13484 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
13485 as_bad (_("trap exception not supported at ISA 1"));
13487 /* If the selected architecture includes support for ASEs, enable
13488 generation of code for them. */
13489 if (mips_opts.mips16 == -1)
13490 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
13491 if (mips_opts.micromips == -1)
13492 mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0;
13494 /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those
13495 ASEs from being selected implicitly. */
13496 if (file_mips_fp32 == 1)
13497 file_ase_explicit |= ASE_MIPS3D | ASE_MDMX;
13499 /* If the user didn't explicitly select or deselect a particular ASE,
13500 use the default setting for the CPU. */
13501 mips_opts.ase |= (arch_info->ase & ~file_ase_explicit);
13503 file_mips_isa = mips_opts.isa;
13504 file_ase = mips_opts.ase;
13505 mips_opts.gp32 = file_mips_gp32;
13506 mips_opts.fp32 = file_mips_fp32;
13507 mips_opts.soft_float = file_mips_soft_float;
13508 mips_opts.single_float = file_mips_single_float;
13510 mips_check_isa_supports_ases ();
13512 if (mips_flag_mdebug < 0)
13513 mips_flag_mdebug = 0;
13517 mips_init_after_args (void)
13519 /* initialize opcodes */
13520 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
13521 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
13525 md_pcrel_from (fixS *fixP)
13527 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
13528 switch (fixP->fx_r_type)
13530 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
13531 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
13532 /* Return the address of the delay slot. */
13535 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
13536 case BFD_RELOC_MICROMIPS_JMP:
13537 case BFD_RELOC_16_PCREL_S2:
13538 case BFD_RELOC_MIPS_JMP:
13539 /* Return the address of the delay slot. */
13542 case BFD_RELOC_32_PCREL:
13546 /* We have no relocation type for PC relative MIPS16 instructions. */
13547 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
13548 as_bad_where (fixP->fx_file, fixP->fx_line,
13549 _("PC relative MIPS16 instruction references a different section"));
13554 /* This is called before the symbol table is processed. In order to
13555 work with gcc when using mips-tfile, we must keep all local labels.
13556 However, in other cases, we want to discard them. If we were
13557 called with -g, but we didn't see any debugging information, it may
13558 mean that gcc is smuggling debugging information through to
13559 mips-tfile, in which case we must generate all local labels. */
13562 mips_frob_file_before_adjust (void)
13564 #ifndef NO_ECOFF_DEBUGGING
13565 if (ECOFF_DEBUGGING
13567 && ! ecoff_debugging_seen)
13568 flag_keep_locals = 1;
13572 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
13573 the corresponding LO16 reloc. This is called before md_apply_fix and
13574 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
13575 relocation operators.
13577 For our purposes, a %lo() expression matches a %got() or %hi()
13580 (a) it refers to the same symbol; and
13581 (b) the offset applied in the %lo() expression is no lower than
13582 the offset applied in the %got() or %hi().
13584 (b) allows us to cope with code like:
13587 lh $4,%lo(foo+2)($4)
13589 ...which is legal on RELA targets, and has a well-defined behaviour
13590 if the user knows that adding 2 to "foo" will not induce a carry to
13593 When several %lo()s match a particular %got() or %hi(), we use the
13594 following rules to distinguish them:
13596 (1) %lo()s with smaller offsets are a better match than %lo()s with
13599 (2) %lo()s with no matching %got() or %hi() are better than those
13600 that already have a matching %got() or %hi().
13602 (3) later %lo()s are better than earlier %lo()s.
13604 These rules are applied in order.
13606 (1) means, among other things, that %lo()s with identical offsets are
13607 chosen if they exist.
13609 (2) means that we won't associate several high-part relocations with
13610 the same low-part relocation unless there's no alternative. Having
13611 several high parts for the same low part is a GNU extension; this rule
13612 allows careful users to avoid it.
13614 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
13615 with the last high-part relocation being at the front of the list.
13616 It therefore makes sense to choose the last matching low-part
13617 relocation, all other things being equal. It's also easier
13618 to code that way. */
13621 mips_frob_file (void)
13623 struct mips_hi_fixup *l;
13624 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
13626 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
13628 segment_info_type *seginfo;
13629 bfd_boolean matched_lo_p;
13630 fixS **hi_pos, **lo_pos, **pos;
13632 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
13634 /* If a GOT16 relocation turns out to be against a global symbol,
13635 there isn't supposed to be a matching LO. Ignore %gots against
13636 constants; we'll report an error for those later. */
13637 if (got16_reloc_p (l->fixp->fx_r_type)
13638 && !(l->fixp->fx_addsy
13639 && pic_need_relax (l->fixp->fx_addsy, l->seg)))
13642 /* Check quickly whether the next fixup happens to be a matching %lo. */
13643 if (fixup_has_matching_lo_p (l->fixp))
13646 seginfo = seg_info (l->seg);
13648 /* Set HI_POS to the position of this relocation in the chain.
13649 Set LO_POS to the position of the chosen low-part relocation.
13650 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
13651 relocation that matches an immediately-preceding high-part
13655 matched_lo_p = FALSE;
13656 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
13658 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
13660 if (*pos == l->fixp)
13663 if ((*pos)->fx_r_type == looking_for_rtype
13664 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
13665 && (*pos)->fx_offset >= l->fixp->fx_offset
13667 || (*pos)->fx_offset < (*lo_pos)->fx_offset
13669 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
13672 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
13673 && fixup_has_matching_lo_p (*pos));
13676 /* If we found a match, remove the high-part relocation from its
13677 current position and insert it before the low-part relocation.
13678 Make the offsets match so that fixup_has_matching_lo_p()
13681 We don't warn about unmatched high-part relocations since some
13682 versions of gcc have been known to emit dead "lui ...%hi(...)"
13684 if (lo_pos != NULL)
13686 l->fixp->fx_offset = (*lo_pos)->fx_offset;
13687 if (l->fixp->fx_next != *lo_pos)
13689 *hi_pos = l->fixp->fx_next;
13690 l->fixp->fx_next = *lo_pos;
13698 mips_force_relocation (fixS *fixp)
13700 if (generic_force_reloc (fixp))
13703 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
13704 so that the linker relaxation can update targets. */
13705 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
13706 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
13707 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
13713 /* Read the instruction associated with RELOC from BUF. */
13715 static unsigned int
13716 read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc)
13718 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
13719 return read_compressed_insn (buf, 4);
13721 return read_insn (buf);
13724 /* Write instruction INSN to BUF, given that it has been relocated
13728 write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc,
13729 unsigned long insn)
13731 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
13732 write_compressed_insn (buf, insn, 4);
13734 write_insn (buf, insn);
13737 /* Apply a fixup to the object file. */
13740 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
13743 unsigned long insn;
13744 reloc_howto_type *howto;
13746 /* We ignore generic BFD relocations we don't know about. */
13747 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
13751 gas_assert (fixP->fx_size == 2
13752 || fixP->fx_size == 4
13753 || fixP->fx_r_type == BFD_RELOC_16
13754 || fixP->fx_r_type == BFD_RELOC_64
13755 || fixP->fx_r_type == BFD_RELOC_CTOR
13756 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
13757 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
13758 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
13759 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
13760 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
13762 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
13764 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
13765 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
13766 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
13767 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
13768 || fixP->fx_r_type == BFD_RELOC_32_PCREL);
13770 /* Don't treat parts of a composite relocation as done. There are two
13773 (1) The second and third parts will be against 0 (RSS_UNDEF) but
13774 should nevertheless be emitted if the first part is.
13776 (2) In normal usage, composite relocations are never assembly-time
13777 constants. The easiest way of dealing with the pathological
13778 exceptions is to generate a relocation against STN_UNDEF and
13779 leave everything up to the linker. */
13780 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
13783 switch (fixP->fx_r_type)
13785 case BFD_RELOC_MIPS_TLS_GD:
13786 case BFD_RELOC_MIPS_TLS_LDM:
13787 case BFD_RELOC_MIPS_TLS_DTPREL32:
13788 case BFD_RELOC_MIPS_TLS_DTPREL64:
13789 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
13790 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
13791 case BFD_RELOC_MIPS_TLS_GOTTPREL:
13792 case BFD_RELOC_MIPS_TLS_TPREL32:
13793 case BFD_RELOC_MIPS_TLS_TPREL64:
13794 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
13795 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
13796 case BFD_RELOC_MICROMIPS_TLS_GD:
13797 case BFD_RELOC_MICROMIPS_TLS_LDM:
13798 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
13799 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
13800 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
13801 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
13802 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
13803 case BFD_RELOC_MIPS16_TLS_GD:
13804 case BFD_RELOC_MIPS16_TLS_LDM:
13805 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
13806 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
13807 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
13808 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
13809 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
13810 if (!fixP->fx_addsy)
13812 as_bad_where (fixP->fx_file, fixP->fx_line,
13813 _("TLS relocation against a constant"));
13816 S_SET_THREAD_LOCAL (fixP->fx_addsy);
13819 case BFD_RELOC_MIPS_JMP:
13820 case BFD_RELOC_MIPS_SHIFT5:
13821 case BFD_RELOC_MIPS_SHIFT6:
13822 case BFD_RELOC_MIPS_GOT_DISP:
13823 case BFD_RELOC_MIPS_GOT_PAGE:
13824 case BFD_RELOC_MIPS_GOT_OFST:
13825 case BFD_RELOC_MIPS_SUB:
13826 case BFD_RELOC_MIPS_INSERT_A:
13827 case BFD_RELOC_MIPS_INSERT_B:
13828 case BFD_RELOC_MIPS_DELETE:
13829 case BFD_RELOC_MIPS_HIGHEST:
13830 case BFD_RELOC_MIPS_HIGHER:
13831 case BFD_RELOC_MIPS_SCN_DISP:
13832 case BFD_RELOC_MIPS_REL16:
13833 case BFD_RELOC_MIPS_RELGOT:
13834 case BFD_RELOC_MIPS_JALR:
13835 case BFD_RELOC_HI16:
13836 case BFD_RELOC_HI16_S:
13837 case BFD_RELOC_LO16:
13838 case BFD_RELOC_GPREL16:
13839 case BFD_RELOC_MIPS_LITERAL:
13840 case BFD_RELOC_MIPS_CALL16:
13841 case BFD_RELOC_MIPS_GOT16:
13842 case BFD_RELOC_GPREL32:
13843 case BFD_RELOC_MIPS_GOT_HI16:
13844 case BFD_RELOC_MIPS_GOT_LO16:
13845 case BFD_RELOC_MIPS_CALL_HI16:
13846 case BFD_RELOC_MIPS_CALL_LO16:
13847 case BFD_RELOC_MIPS16_GPREL:
13848 case BFD_RELOC_MIPS16_GOT16:
13849 case BFD_RELOC_MIPS16_CALL16:
13850 case BFD_RELOC_MIPS16_HI16:
13851 case BFD_RELOC_MIPS16_HI16_S:
13852 case BFD_RELOC_MIPS16_LO16:
13853 case BFD_RELOC_MIPS16_JMP:
13854 case BFD_RELOC_MICROMIPS_JMP:
13855 case BFD_RELOC_MICROMIPS_GOT_DISP:
13856 case BFD_RELOC_MICROMIPS_GOT_PAGE:
13857 case BFD_RELOC_MICROMIPS_GOT_OFST:
13858 case BFD_RELOC_MICROMIPS_SUB:
13859 case BFD_RELOC_MICROMIPS_HIGHEST:
13860 case BFD_RELOC_MICROMIPS_HIGHER:
13861 case BFD_RELOC_MICROMIPS_SCN_DISP:
13862 case BFD_RELOC_MICROMIPS_JALR:
13863 case BFD_RELOC_MICROMIPS_HI16:
13864 case BFD_RELOC_MICROMIPS_HI16_S:
13865 case BFD_RELOC_MICROMIPS_LO16:
13866 case BFD_RELOC_MICROMIPS_GPREL16:
13867 case BFD_RELOC_MICROMIPS_LITERAL:
13868 case BFD_RELOC_MICROMIPS_CALL16:
13869 case BFD_RELOC_MICROMIPS_GOT16:
13870 case BFD_RELOC_MICROMIPS_GOT_HI16:
13871 case BFD_RELOC_MICROMIPS_GOT_LO16:
13872 case BFD_RELOC_MICROMIPS_CALL_HI16:
13873 case BFD_RELOC_MICROMIPS_CALL_LO16:
13874 case BFD_RELOC_MIPS_EH:
13879 if (calculate_reloc (fixP->fx_r_type, *valP, &value))
13881 insn = read_reloc_insn (buf, fixP->fx_r_type);
13882 if (mips16_reloc_p (fixP->fx_r_type))
13883 insn |= mips16_immed_extend (value, 16);
13885 insn |= (value & 0xffff);
13886 write_reloc_insn (buf, fixP->fx_r_type, insn);
13889 as_bad_where (fixP->fx_file, fixP->fx_line,
13890 _("Unsupported constant in relocation"));
13895 /* This is handled like BFD_RELOC_32, but we output a sign
13896 extended value if we are only 32 bits. */
13899 if (8 <= sizeof (valueT))
13900 md_number_to_chars (buf, *valP, 8);
13905 if ((*valP & 0x80000000) != 0)
13909 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4);
13910 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4);
13915 case BFD_RELOC_RVA:
13917 case BFD_RELOC_32_PCREL:
13919 /* If we are deleting this reloc entry, we must fill in the
13920 value now. This can happen if we have a .word which is not
13921 resolved when it appears but is later defined. */
13923 md_number_to_chars (buf, *valP, fixP->fx_size);
13926 case BFD_RELOC_16_PCREL_S2:
13927 if ((*valP & 0x3) != 0)
13928 as_bad_where (fixP->fx_file, fixP->fx_line,
13929 _("Branch to misaligned address (%lx)"), (long) *valP);
13931 /* We need to save the bits in the instruction since fixup_segment()
13932 might be deleting the relocation entry (i.e., a branch within
13933 the current segment). */
13934 if (! fixP->fx_done)
13937 /* Update old instruction data. */
13938 insn = read_insn (buf);
13940 if (*valP + 0x20000 <= 0x3ffff)
13942 insn |= (*valP >> 2) & 0xffff;
13943 write_insn (buf, insn);
13945 else if (mips_pic == NO_PIC
13947 && fixP->fx_frag->fr_address >= text_section->vma
13948 && (fixP->fx_frag->fr_address
13949 < text_section->vma + bfd_get_section_size (text_section))
13950 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
13951 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
13952 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
13954 /* The branch offset is too large. If this is an
13955 unconditional branch, and we are not generating PIC code,
13956 we can convert it to an absolute jump instruction. */
13957 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
13958 insn = 0x0c000000; /* jal */
13960 insn = 0x08000000; /* j */
13961 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
13963 fixP->fx_addsy = section_symbol (text_section);
13964 *valP += md_pcrel_from (fixP);
13965 write_insn (buf, insn);
13969 /* If we got here, we have branch-relaxation disabled,
13970 and there's nothing we can do to fix this instruction
13971 without turning it into a longer sequence. */
13972 as_bad_where (fixP->fx_file, fixP->fx_line,
13973 _("Branch out of range"));
13977 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
13978 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
13979 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
13980 /* We adjust the offset back to even. */
13981 if ((*valP & 0x1) != 0)
13984 if (! fixP->fx_done)
13987 /* Should never visit here, because we keep the relocation. */
13991 case BFD_RELOC_VTABLE_INHERIT:
13994 && !S_IS_DEFINED (fixP->fx_addsy)
13995 && !S_IS_WEAK (fixP->fx_addsy))
13996 S_SET_WEAK (fixP->fx_addsy);
13999 case BFD_RELOC_VTABLE_ENTRY:
14007 /* Remember value for tc_gen_reloc. */
14008 fixP->fx_addnumber = *valP;
14018 name = input_line_pointer;
14019 c = get_symbol_end ();
14020 p = (symbolS *) symbol_find_or_make (name);
14021 *input_line_pointer = c;
14025 /* Align the current frag to a given power of two. If a particular
14026 fill byte should be used, FILL points to an integer that contains
14027 that byte, otherwise FILL is null.
14029 This function used to have the comment:
14031 The MIPS assembler also automatically adjusts any preceding label.
14033 The implementation therefore applied the adjustment to a maximum of
14034 one label. However, other label adjustments are applied to batches
14035 of labels, and adjusting just one caused problems when new labels
14036 were added for the sake of debugging or unwind information.
14037 We therefore adjust all preceding labels (given as LABELS) instead. */
14040 mips_align (int to, int *fill, struct insn_label_list *labels)
14042 mips_emit_delays ();
14043 mips_record_compressed_mode ();
14044 if (fill == NULL && subseg_text_p (now_seg))
14045 frag_align_code (to, 0);
14047 frag_align (to, fill ? *fill : 0, 0);
14048 record_alignment (now_seg, to);
14049 mips_move_labels (labels, FALSE);
14052 /* Align to a given power of two. .align 0 turns off the automatic
14053 alignment used by the data creating pseudo-ops. */
14056 s_align (int x ATTRIBUTE_UNUSED)
14058 int temp, fill_value, *fill_ptr;
14059 long max_alignment = 28;
14061 /* o Note that the assembler pulls down any immediately preceding label
14062 to the aligned address.
14063 o It's not documented but auto alignment is reinstated by
14064 a .align pseudo instruction.
14065 o Note also that after auto alignment is turned off the mips assembler
14066 issues an error on attempt to assemble an improperly aligned data item.
14069 temp = get_absolute_expression ();
14070 if (temp > max_alignment)
14071 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
14074 as_warn (_("Alignment negative: 0 assumed."));
14077 if (*input_line_pointer == ',')
14079 ++input_line_pointer;
14080 fill_value = get_absolute_expression ();
14081 fill_ptr = &fill_value;
14087 segment_info_type *si = seg_info (now_seg);
14088 struct insn_label_list *l = si->label_list;
14089 /* Auto alignment should be switched on by next section change. */
14091 mips_align (temp, fill_ptr, l);
14098 demand_empty_rest_of_line ();
14102 s_change_sec (int sec)
14106 /* The ELF backend needs to know that we are changing sections, so
14107 that .previous works correctly. We could do something like check
14108 for an obj_section_change_hook macro, but that might be confusing
14109 as it would not be appropriate to use it in the section changing
14110 functions in read.c, since obj-elf.c intercepts those. FIXME:
14111 This should be cleaner, somehow. */
14112 obj_elf_section_change_hook ();
14114 mips_emit_delays ();
14125 subseg_set (bss_section, (subsegT) get_absolute_expression ());
14126 demand_empty_rest_of_line ();
14130 seg = subseg_new (RDATA_SECTION_NAME,
14131 (subsegT) get_absolute_expression ());
14132 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
14133 | SEC_READONLY | SEC_RELOC
14135 if (strncmp (TARGET_OS, "elf", 3) != 0)
14136 record_alignment (seg, 4);
14137 demand_empty_rest_of_line ();
14141 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
14142 bfd_set_section_flags (stdoutput, seg,
14143 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
14144 if (strncmp (TARGET_OS, "elf", 3) != 0)
14145 record_alignment (seg, 4);
14146 demand_empty_rest_of_line ();
14150 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
14151 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
14152 if (strncmp (TARGET_OS, "elf", 3) != 0)
14153 record_alignment (seg, 4);
14154 demand_empty_rest_of_line ();
14162 s_change_section (int ignore ATTRIBUTE_UNUSED)
14164 char *section_name;
14169 int section_entry_size;
14170 int section_alignment;
14172 section_name = input_line_pointer;
14173 c = get_symbol_end ();
14175 next_c = *(input_line_pointer + 1);
14177 /* Do we have .section Name<,"flags">? */
14178 if (c != ',' || (c == ',' && next_c == '"'))
14180 /* just after name is now '\0'. */
14181 *input_line_pointer = c;
14182 input_line_pointer = section_name;
14183 obj_elf_section (ignore);
14186 input_line_pointer++;
14188 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
14190 section_type = get_absolute_expression ();
14193 if (*input_line_pointer++ == ',')
14194 section_flag = get_absolute_expression ();
14197 if (*input_line_pointer++ == ',')
14198 section_entry_size = get_absolute_expression ();
14200 section_entry_size = 0;
14201 if (*input_line_pointer++ == ',')
14202 section_alignment = get_absolute_expression ();
14204 section_alignment = 0;
14205 /* FIXME: really ignore? */
14206 (void) section_alignment;
14208 section_name = xstrdup (section_name);
14210 /* When using the generic form of .section (as implemented by obj-elf.c),
14211 there's no way to set the section type to SHT_MIPS_DWARF. Users have
14212 traditionally had to fall back on the more common @progbits instead.
14214 There's nothing really harmful in this, since bfd will correct
14215 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
14216 means that, for backwards compatibility, the special_section entries
14217 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
14219 Even so, we shouldn't force users of the MIPS .section syntax to
14220 incorrectly label the sections as SHT_PROGBITS. The best compromise
14221 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
14222 generic type-checking code. */
14223 if (section_type == SHT_MIPS_DWARF)
14224 section_type = SHT_PROGBITS;
14226 obj_elf_change_section (section_name, section_type, section_flag,
14227 section_entry_size, 0, 0, 0);
14229 if (now_seg->name != section_name)
14230 free (section_name);
14234 mips_enable_auto_align (void)
14240 s_cons (int log_size)
14242 segment_info_type *si = seg_info (now_seg);
14243 struct insn_label_list *l = si->label_list;
14245 mips_emit_delays ();
14246 if (log_size > 0 && auto_align)
14247 mips_align (log_size, 0, l);
14248 cons (1 << log_size);
14249 mips_clear_insn_labels ();
14253 s_float_cons (int type)
14255 segment_info_type *si = seg_info (now_seg);
14256 struct insn_label_list *l = si->label_list;
14258 mips_emit_delays ();
14263 mips_align (3, 0, l);
14265 mips_align (2, 0, l);
14269 mips_clear_insn_labels ();
14272 /* Handle .globl. We need to override it because on Irix 5 you are
14275 where foo is an undefined symbol, to mean that foo should be
14276 considered to be the address of a function. */
14279 s_mips_globl (int x ATTRIBUTE_UNUSED)
14288 name = input_line_pointer;
14289 c = get_symbol_end ();
14290 symbolP = symbol_find_or_make (name);
14291 S_SET_EXTERNAL (symbolP);
14293 *input_line_pointer = c;
14294 SKIP_WHITESPACE ();
14296 /* On Irix 5, every global symbol that is not explicitly labelled as
14297 being a function is apparently labelled as being an object. */
14300 if (!is_end_of_line[(unsigned char) *input_line_pointer]
14301 && (*input_line_pointer != ','))
14306 secname = input_line_pointer;
14307 c = get_symbol_end ();
14308 sec = bfd_get_section_by_name (stdoutput, secname);
14310 as_bad (_("%s: no such section"), secname);
14311 *input_line_pointer = c;
14313 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
14314 flag = BSF_FUNCTION;
14317 symbol_get_bfdsym (symbolP)->flags |= flag;
14319 c = *input_line_pointer;
14322 input_line_pointer++;
14323 SKIP_WHITESPACE ();
14324 if (is_end_of_line[(unsigned char) *input_line_pointer])
14330 demand_empty_rest_of_line ();
14334 s_option (int x ATTRIBUTE_UNUSED)
14339 opt = input_line_pointer;
14340 c = get_symbol_end ();
14344 /* FIXME: What does this mean? */
14346 else if (strncmp (opt, "pic", 3) == 0)
14350 i = atoi (opt + 3);
14355 mips_pic = SVR4_PIC;
14356 mips_abicalls = TRUE;
14359 as_bad (_(".option pic%d not supported"), i);
14361 if (mips_pic == SVR4_PIC)
14363 if (g_switch_seen && g_switch_value != 0)
14364 as_warn (_("-G may not be used with SVR4 PIC code"));
14365 g_switch_value = 0;
14366 bfd_set_gp_size (stdoutput, 0);
14370 as_warn (_("Unrecognized option \"%s\""), opt);
14372 *input_line_pointer = c;
14373 demand_empty_rest_of_line ();
14376 /* This structure is used to hold a stack of .set values. */
14378 struct mips_option_stack
14380 struct mips_option_stack *next;
14381 struct mips_set_options options;
14384 static struct mips_option_stack *mips_opts_stack;
14386 /* Handle the .set pseudo-op. */
14389 s_mipsset (int x ATTRIBUTE_UNUSED)
14391 char *name = input_line_pointer, ch;
14392 const struct mips_ase *ase;
14394 while (!is_end_of_line[(unsigned char) *input_line_pointer])
14395 ++input_line_pointer;
14396 ch = *input_line_pointer;
14397 *input_line_pointer = '\0';
14399 if (strcmp (name, "reorder") == 0)
14401 if (mips_opts.noreorder)
14404 else if (strcmp (name, "noreorder") == 0)
14406 if (!mips_opts.noreorder)
14407 start_noreorder ();
14409 else if (strncmp (name, "at=", 3) == 0)
14411 char *s = name + 3;
14413 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
14414 as_bad (_("Unrecognized register name `%s'"), s);
14416 else if (strcmp (name, "at") == 0)
14418 mips_opts.at = ATREG;
14420 else if (strcmp (name, "noat") == 0)
14422 mips_opts.at = ZERO;
14424 else if (strcmp (name, "macro") == 0)
14426 mips_opts.warn_about_macros = 0;
14428 else if (strcmp (name, "nomacro") == 0)
14430 if (mips_opts.noreorder == 0)
14431 as_bad (_("`noreorder' must be set before `nomacro'"));
14432 mips_opts.warn_about_macros = 1;
14434 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
14436 mips_opts.nomove = 0;
14438 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
14440 mips_opts.nomove = 1;
14442 else if (strcmp (name, "bopt") == 0)
14444 mips_opts.nobopt = 0;
14446 else if (strcmp (name, "nobopt") == 0)
14448 mips_opts.nobopt = 1;
14450 else if (strcmp (name, "gp=default") == 0)
14451 mips_opts.gp32 = file_mips_gp32;
14452 else if (strcmp (name, "gp=32") == 0)
14453 mips_opts.gp32 = 1;
14454 else if (strcmp (name, "gp=64") == 0)
14456 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
14457 as_warn (_("%s isa does not support 64-bit registers"),
14458 mips_cpu_info_from_isa (mips_opts.isa)->name);
14459 mips_opts.gp32 = 0;
14461 else if (strcmp (name, "fp=default") == 0)
14462 mips_opts.fp32 = file_mips_fp32;
14463 else if (strcmp (name, "fp=32") == 0)
14464 mips_opts.fp32 = 1;
14465 else if (strcmp (name, "fp=64") == 0)
14467 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
14468 as_warn (_("%s isa does not support 64-bit floating point registers"),
14469 mips_cpu_info_from_isa (mips_opts.isa)->name);
14470 mips_opts.fp32 = 0;
14472 else if (strcmp (name, "softfloat") == 0)
14473 mips_opts.soft_float = 1;
14474 else if (strcmp (name, "hardfloat") == 0)
14475 mips_opts.soft_float = 0;
14476 else if (strcmp (name, "singlefloat") == 0)
14477 mips_opts.single_float = 1;
14478 else if (strcmp (name, "doublefloat") == 0)
14479 mips_opts.single_float = 0;
14480 else if (strcmp (name, "mips16") == 0
14481 || strcmp (name, "MIPS-16") == 0)
14483 if (mips_opts.micromips == 1)
14484 as_fatal (_("`mips16' cannot be used with `micromips'"));
14485 mips_opts.mips16 = 1;
14487 else if (strcmp (name, "nomips16") == 0
14488 || strcmp (name, "noMIPS-16") == 0)
14489 mips_opts.mips16 = 0;
14490 else if (strcmp (name, "micromips") == 0)
14492 if (mips_opts.mips16 == 1)
14493 as_fatal (_("`micromips' cannot be used with `mips16'"));
14494 mips_opts.micromips = 1;
14496 else if (strcmp (name, "nomicromips") == 0)
14497 mips_opts.micromips = 0;
14498 else if (name[0] == 'n'
14500 && (ase = mips_lookup_ase (name + 2)))
14501 mips_set_ase (ase, FALSE);
14502 else if ((ase = mips_lookup_ase (name)))
14503 mips_set_ase (ase, TRUE);
14504 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
14508 /* Permit the user to change the ISA and architecture on the fly.
14509 Needless to say, misuse can cause serious problems. */
14510 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
14513 mips_opts.isa = file_mips_isa;
14514 mips_opts.arch = file_mips_arch;
14516 else if (strncmp (name, "arch=", 5) == 0)
14518 const struct mips_cpu_info *p;
14520 p = mips_parse_cpu("internal use", name + 5);
14522 as_bad (_("unknown architecture %s"), name + 5);
14525 mips_opts.arch = p->cpu;
14526 mips_opts.isa = p->isa;
14529 else if (strncmp (name, "mips", 4) == 0)
14531 const struct mips_cpu_info *p;
14533 p = mips_parse_cpu("internal use", name);
14535 as_bad (_("unknown ISA level %s"), name + 4);
14538 mips_opts.arch = p->cpu;
14539 mips_opts.isa = p->isa;
14543 as_bad (_("unknown ISA or architecture %s"), name);
14545 switch (mips_opts.isa)
14553 mips_opts.gp32 = 1;
14554 mips_opts.fp32 = 1;
14561 mips_opts.gp32 = 0;
14562 if (mips_opts.arch == CPU_R5900)
14564 mips_opts.fp32 = 1;
14568 mips_opts.fp32 = 0;
14572 as_bad (_("unknown ISA level %s"), name + 4);
14577 mips_opts.gp32 = file_mips_gp32;
14578 mips_opts.fp32 = file_mips_fp32;
14581 else if (strcmp (name, "autoextend") == 0)
14582 mips_opts.noautoextend = 0;
14583 else if (strcmp (name, "noautoextend") == 0)
14584 mips_opts.noautoextend = 1;
14585 else if (strcmp (name, "insn32") == 0)
14586 mips_opts.insn32 = TRUE;
14587 else if (strcmp (name, "noinsn32") == 0)
14588 mips_opts.insn32 = FALSE;
14589 else if (strcmp (name, "push") == 0)
14591 struct mips_option_stack *s;
14593 s = (struct mips_option_stack *) xmalloc (sizeof *s);
14594 s->next = mips_opts_stack;
14595 s->options = mips_opts;
14596 mips_opts_stack = s;
14598 else if (strcmp (name, "pop") == 0)
14600 struct mips_option_stack *s;
14602 s = mips_opts_stack;
14604 as_bad (_(".set pop with no .set push"));
14607 /* If we're changing the reorder mode we need to handle
14608 delay slots correctly. */
14609 if (s->options.noreorder && ! mips_opts.noreorder)
14610 start_noreorder ();
14611 else if (! s->options.noreorder && mips_opts.noreorder)
14614 mips_opts = s->options;
14615 mips_opts_stack = s->next;
14619 else if (strcmp (name, "sym32") == 0)
14620 mips_opts.sym32 = TRUE;
14621 else if (strcmp (name, "nosym32") == 0)
14622 mips_opts.sym32 = FALSE;
14623 else if (strchr (name, ','))
14625 /* Generic ".set" directive; use the generic handler. */
14626 *input_line_pointer = ch;
14627 input_line_pointer = name;
14633 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
14635 mips_check_isa_supports_ases ();
14636 *input_line_pointer = ch;
14637 demand_empty_rest_of_line ();
14640 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
14641 .option pic2. It means to generate SVR4 PIC calls. */
14644 s_abicalls (int ignore ATTRIBUTE_UNUSED)
14646 mips_pic = SVR4_PIC;
14647 mips_abicalls = TRUE;
14649 if (g_switch_seen && g_switch_value != 0)
14650 as_warn (_("-G may not be used with SVR4 PIC code"));
14651 g_switch_value = 0;
14653 bfd_set_gp_size (stdoutput, 0);
14654 demand_empty_rest_of_line ();
14657 /* Handle the .cpload pseudo-op. This is used when generating SVR4
14658 PIC code. It sets the $gp register for the function based on the
14659 function address, which is in the register named in the argument.
14660 This uses a relocation against _gp_disp, which is handled specially
14661 by the linker. The result is:
14662 lui $gp,%hi(_gp_disp)
14663 addiu $gp,$gp,%lo(_gp_disp)
14664 addu $gp,$gp,.cpload argument
14665 The .cpload argument is normally $25 == $t9.
14667 The -mno-shared option changes this to:
14668 lui $gp,%hi(__gnu_local_gp)
14669 addiu $gp,$gp,%lo(__gnu_local_gp)
14670 and the argument is ignored. This saves an instruction, but the
14671 resulting code is not position independent; it uses an absolute
14672 address for __gnu_local_gp. Thus code assembled with -mno-shared
14673 can go into an ordinary executable, but not into a shared library. */
14676 s_cpload (int ignore ATTRIBUTE_UNUSED)
14682 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
14683 .cpload is ignored. */
14684 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
14690 if (mips_opts.mips16)
14692 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
14693 ignore_rest_of_line ();
14697 /* .cpload should be in a .set noreorder section. */
14698 if (mips_opts.noreorder == 0)
14699 as_warn (_(".cpload not in noreorder section"));
14701 reg = tc_get_register (0);
14703 /* If we need to produce a 64-bit address, we are better off using
14704 the default instruction sequence. */
14705 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
14707 ex.X_op = O_symbol;
14708 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
14710 ex.X_op_symbol = NULL;
14711 ex.X_add_number = 0;
14713 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
14714 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
14716 mips_mark_labels ();
14717 mips_assembling_insn = TRUE;
14720 macro_build_lui (&ex, mips_gp_register);
14721 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
14722 mips_gp_register, BFD_RELOC_LO16);
14724 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
14725 mips_gp_register, reg);
14728 mips_assembling_insn = FALSE;
14729 demand_empty_rest_of_line ();
14732 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
14733 .cpsetup $reg1, offset|$reg2, label
14735 If offset is given, this results in:
14736 sd $gp, offset($sp)
14737 lui $gp, %hi(%neg(%gp_rel(label)))
14738 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
14739 daddu $gp, $gp, $reg1
14741 If $reg2 is given, this results in:
14742 daddu $reg2, $gp, $0
14743 lui $gp, %hi(%neg(%gp_rel(label)))
14744 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
14745 daddu $gp, $gp, $reg1
14746 $reg1 is normally $25 == $t9.
14748 The -mno-shared option replaces the last three instructions with
14750 addiu $gp,$gp,%lo(_gp) */
14753 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
14755 expressionS ex_off;
14756 expressionS ex_sym;
14759 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
14760 We also need NewABI support. */
14761 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
14767 if (mips_opts.mips16)
14769 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
14770 ignore_rest_of_line ();
14774 reg1 = tc_get_register (0);
14775 SKIP_WHITESPACE ();
14776 if (*input_line_pointer != ',')
14778 as_bad (_("missing argument separator ',' for .cpsetup"));
14782 ++input_line_pointer;
14783 SKIP_WHITESPACE ();
14784 if (*input_line_pointer == '$')
14786 mips_cpreturn_register = tc_get_register (0);
14787 mips_cpreturn_offset = -1;
14791 mips_cpreturn_offset = get_absolute_expression ();
14792 mips_cpreturn_register = -1;
14794 SKIP_WHITESPACE ();
14795 if (*input_line_pointer != ',')
14797 as_bad (_("missing argument separator ',' for .cpsetup"));
14801 ++input_line_pointer;
14802 SKIP_WHITESPACE ();
14803 expression (&ex_sym);
14805 mips_mark_labels ();
14806 mips_assembling_insn = TRUE;
14809 if (mips_cpreturn_register == -1)
14811 ex_off.X_op = O_constant;
14812 ex_off.X_add_symbol = NULL;
14813 ex_off.X_op_symbol = NULL;
14814 ex_off.X_add_number = mips_cpreturn_offset;
14816 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
14817 BFD_RELOC_LO16, SP);
14820 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
14821 mips_gp_register, 0);
14823 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
14825 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
14826 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
14829 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
14830 mips_gp_register, -1, BFD_RELOC_GPREL16,
14831 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
14833 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
14834 mips_gp_register, reg1);
14840 ex.X_op = O_symbol;
14841 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
14842 ex.X_op_symbol = NULL;
14843 ex.X_add_number = 0;
14845 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
14846 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
14848 macro_build_lui (&ex, mips_gp_register);
14849 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
14850 mips_gp_register, BFD_RELOC_LO16);
14855 mips_assembling_insn = FALSE;
14856 demand_empty_rest_of_line ();
14860 s_cplocal (int ignore ATTRIBUTE_UNUSED)
14862 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
14863 .cplocal is ignored. */
14864 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
14870 if (mips_opts.mips16)
14872 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
14873 ignore_rest_of_line ();
14877 mips_gp_register = tc_get_register (0);
14878 demand_empty_rest_of_line ();
14881 /* Handle the .cprestore pseudo-op. This stores $gp into a given
14882 offset from $sp. The offset is remembered, and after making a PIC
14883 call $gp is restored from that location. */
14886 s_cprestore (int ignore ATTRIBUTE_UNUSED)
14890 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
14891 .cprestore is ignored. */
14892 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
14898 if (mips_opts.mips16)
14900 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
14901 ignore_rest_of_line ();
14905 mips_cprestore_offset = get_absolute_expression ();
14906 mips_cprestore_valid = 1;
14908 ex.X_op = O_constant;
14909 ex.X_add_symbol = NULL;
14910 ex.X_op_symbol = NULL;
14911 ex.X_add_number = mips_cprestore_offset;
14913 mips_mark_labels ();
14914 mips_assembling_insn = TRUE;
14917 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
14918 SP, HAVE_64BIT_ADDRESSES);
14921 mips_assembling_insn = FALSE;
14922 demand_empty_rest_of_line ();
14925 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
14926 was given in the preceding .cpsetup, it results in:
14927 ld $gp, offset($sp)
14929 If a register $reg2 was given there, it results in:
14930 daddu $gp, $reg2, $0 */
14933 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
14937 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
14938 We also need NewABI support. */
14939 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
14945 if (mips_opts.mips16)
14947 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
14948 ignore_rest_of_line ();
14952 mips_mark_labels ();
14953 mips_assembling_insn = TRUE;
14956 if (mips_cpreturn_register == -1)
14958 ex.X_op = O_constant;
14959 ex.X_add_symbol = NULL;
14960 ex.X_op_symbol = NULL;
14961 ex.X_add_number = mips_cpreturn_offset;
14963 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
14966 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
14967 mips_cpreturn_register, 0);
14970 mips_assembling_insn = FALSE;
14971 demand_empty_rest_of_line ();
14974 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
14975 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
14976 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
14977 debug information or MIPS16 TLS. */
14980 s_tls_rel_directive (const size_t bytes, const char *dirstr,
14981 bfd_reloc_code_real_type rtype)
14988 if (ex.X_op != O_symbol)
14990 as_bad (_("Unsupported use of %s"), dirstr);
14991 ignore_rest_of_line ();
14994 p = frag_more (bytes);
14995 md_number_to_chars (p, 0, bytes);
14996 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
14997 demand_empty_rest_of_line ();
14998 mips_clear_insn_labels ();
15001 /* Handle .dtprelword. */
15004 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
15006 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
15009 /* Handle .dtpreldword. */
15012 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
15014 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
15017 /* Handle .tprelword. */
15020 s_tprelword (int ignore ATTRIBUTE_UNUSED)
15022 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
15025 /* Handle .tpreldword. */
15028 s_tpreldword (int ignore ATTRIBUTE_UNUSED)
15030 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
15033 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
15034 code. It sets the offset to use in gp_rel relocations. */
15037 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
15039 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
15040 We also need NewABI support. */
15041 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15047 mips_gprel_offset = get_absolute_expression ();
15049 demand_empty_rest_of_line ();
15052 /* Handle the .gpword pseudo-op. This is used when generating PIC
15053 code. It generates a 32 bit GP relative reloc. */
15056 s_gpword (int ignore ATTRIBUTE_UNUSED)
15058 segment_info_type *si;
15059 struct insn_label_list *l;
15063 /* When not generating PIC code, this is treated as .word. */
15064 if (mips_pic != SVR4_PIC)
15070 si = seg_info (now_seg);
15071 l = si->label_list;
15072 mips_emit_delays ();
15074 mips_align (2, 0, l);
15077 mips_clear_insn_labels ();
15079 if (ex.X_op != O_symbol || ex.X_add_number != 0)
15081 as_bad (_("Unsupported use of .gpword"));
15082 ignore_rest_of_line ();
15086 md_number_to_chars (p, 0, 4);
15087 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
15088 BFD_RELOC_GPREL32);
15090 demand_empty_rest_of_line ();
15094 s_gpdword (int ignore ATTRIBUTE_UNUSED)
15096 segment_info_type *si;
15097 struct insn_label_list *l;
15101 /* When not generating PIC code, this is treated as .dword. */
15102 if (mips_pic != SVR4_PIC)
15108 si = seg_info (now_seg);
15109 l = si->label_list;
15110 mips_emit_delays ();
15112 mips_align (3, 0, l);
15115 mips_clear_insn_labels ();
15117 if (ex.X_op != O_symbol || ex.X_add_number != 0)
15119 as_bad (_("Unsupported use of .gpdword"));
15120 ignore_rest_of_line ();
15124 md_number_to_chars (p, 0, 8);
15125 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
15126 BFD_RELOC_GPREL32)->fx_tcbit = 1;
15128 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
15129 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
15130 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
15132 demand_empty_rest_of_line ();
15135 /* Handle the .ehword pseudo-op. This is used when generating unwinding
15136 tables. It generates a R_MIPS_EH reloc. */
15139 s_ehword (int ignore ATTRIBUTE_UNUSED)
15144 mips_emit_delays ();
15147 mips_clear_insn_labels ();
15149 if (ex.X_op != O_symbol || ex.X_add_number != 0)
15151 as_bad (_("Unsupported use of .ehword"));
15152 ignore_rest_of_line ();
15156 md_number_to_chars (p, 0, 4);
15157 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
15158 BFD_RELOC_MIPS_EH);
15160 demand_empty_rest_of_line ();
15163 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
15164 tables in SVR4 PIC code. */
15167 s_cpadd (int ignore ATTRIBUTE_UNUSED)
15171 /* This is ignored when not generating SVR4 PIC code. */
15172 if (mips_pic != SVR4_PIC)
15178 mips_mark_labels ();
15179 mips_assembling_insn = TRUE;
15181 /* Add $gp to the register named as an argument. */
15183 reg = tc_get_register (0);
15184 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
15187 mips_assembling_insn = FALSE;
15188 demand_empty_rest_of_line ();
15191 /* Handle the .insn pseudo-op. This marks instruction labels in
15192 mips16/micromips mode. This permits the linker to handle them specially,
15193 such as generating jalx instructions when needed. We also make
15194 them odd for the duration of the assembly, in order to generate the
15195 right sort of code. We will make them even in the adjust_symtab
15196 routine, while leaving them marked. This is convenient for the
15197 debugger and the disassembler. The linker knows to make them odd
15201 s_insn (int ignore ATTRIBUTE_UNUSED)
15203 mips_mark_labels ();
15205 demand_empty_rest_of_line ();
15208 /* Handle the .nan pseudo-op. */
15211 s_nan (int ignore ATTRIBUTE_UNUSED)
15213 static const char str_legacy[] = "legacy";
15214 static const char str_2008[] = "2008";
15217 for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++);
15219 if (i == sizeof (str_2008) - 1
15220 && memcmp (input_line_pointer, str_2008, i) == 0)
15221 mips_flag_nan2008 = TRUE;
15222 else if (i == sizeof (str_legacy) - 1
15223 && memcmp (input_line_pointer, str_legacy, i) == 0)
15224 mips_flag_nan2008 = FALSE;
15226 as_bad (_("Bad .nan directive"));
15228 input_line_pointer += i;
15229 demand_empty_rest_of_line ();
15232 /* Handle a .stab[snd] directive. Ideally these directives would be
15233 implemented in a transparent way, so that removing them would not
15234 have any effect on the generated instructions. However, s_stab
15235 internally changes the section, so in practice we need to decide
15236 now whether the preceding label marks compressed code. We do not
15237 support changing the compression mode of a label after a .stab*
15238 directive, such as in:
15244 so the current mode wins. */
15247 s_mips_stab (int type)
15249 mips_mark_labels ();
15253 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
15256 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
15263 name = input_line_pointer;
15264 c = get_symbol_end ();
15265 symbolP = symbol_find_or_make (name);
15266 S_SET_WEAK (symbolP);
15267 *input_line_pointer = c;
15269 SKIP_WHITESPACE ();
15271 if (! is_end_of_line[(unsigned char) *input_line_pointer])
15273 if (S_IS_DEFINED (symbolP))
15275 as_bad (_("ignoring attempt to redefine symbol %s"),
15276 S_GET_NAME (symbolP));
15277 ignore_rest_of_line ();
15281 if (*input_line_pointer == ',')
15283 ++input_line_pointer;
15284 SKIP_WHITESPACE ();
15288 if (exp.X_op != O_symbol)
15290 as_bad (_("bad .weakext directive"));
15291 ignore_rest_of_line ();
15294 symbol_set_value_expression (symbolP, &exp);
15297 demand_empty_rest_of_line ();
15300 /* Parse a register string into a number. Called from the ECOFF code
15301 to parse .frame. The argument is non-zero if this is the frame
15302 register, so that we can record it in mips_frame_reg. */
15305 tc_get_register (int frame)
15309 SKIP_WHITESPACE ();
15310 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
15314 mips_frame_reg = reg != 0 ? reg : SP;
15315 mips_frame_reg_valid = 1;
15316 mips_cprestore_valid = 0;
15322 md_section_align (asection *seg, valueT addr)
15324 int align = bfd_get_section_alignment (stdoutput, seg);
15326 /* We don't need to align ELF sections to the full alignment.
15327 However, Irix 5 may prefer that we align them at least to a 16
15328 byte boundary. We don't bother to align the sections if we
15329 are targeted for an embedded system. */
15330 if (strncmp (TARGET_OS, "elf", 3) == 0)
15335 return ((addr + (1 << align) - 1) & (-1 << align));
15338 /* Utility routine, called from above as well. If called while the
15339 input file is still being read, it's only an approximation. (For
15340 example, a symbol may later become defined which appeared to be
15341 undefined earlier.) */
15344 nopic_need_relax (symbolS *sym, int before_relaxing)
15349 if (g_switch_value > 0)
15351 const char *symname;
15354 /* Find out whether this symbol can be referenced off the $gp
15355 register. It can be if it is smaller than the -G size or if
15356 it is in the .sdata or .sbss section. Certain symbols can
15357 not be referenced off the $gp, although it appears as though
15359 symname = S_GET_NAME (sym);
15360 if (symname != (const char *) NULL
15361 && (strcmp (symname, "eprol") == 0
15362 || strcmp (symname, "etext") == 0
15363 || strcmp (symname, "_gp") == 0
15364 || strcmp (symname, "edata") == 0
15365 || strcmp (symname, "_fbss") == 0
15366 || strcmp (symname, "_fdata") == 0
15367 || strcmp (symname, "_ftext") == 0
15368 || strcmp (symname, "end") == 0
15369 || strcmp (symname, "_gp_disp") == 0))
15371 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
15373 #ifndef NO_ECOFF_DEBUGGING
15374 || (symbol_get_obj (sym)->ecoff_extern_size != 0
15375 && (symbol_get_obj (sym)->ecoff_extern_size
15376 <= g_switch_value))
15378 /* We must defer this decision until after the whole
15379 file has been read, since there might be a .extern
15380 after the first use of this symbol. */
15381 || (before_relaxing
15382 #ifndef NO_ECOFF_DEBUGGING
15383 && symbol_get_obj (sym)->ecoff_extern_size == 0
15385 && S_GET_VALUE (sym) == 0)
15386 || (S_GET_VALUE (sym) != 0
15387 && S_GET_VALUE (sym) <= g_switch_value)))
15391 const char *segname;
15393 segname = segment_name (S_GET_SEGMENT (sym));
15394 gas_assert (strcmp (segname, ".lit8") != 0
15395 && strcmp (segname, ".lit4") != 0);
15396 change = (strcmp (segname, ".sdata") != 0
15397 && strcmp (segname, ".sbss") != 0
15398 && strncmp (segname, ".sdata.", 7) != 0
15399 && strncmp (segname, ".sbss.", 6) != 0
15400 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
15401 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
15406 /* We are not optimizing for the $gp register. */
15411 /* Return true if the given symbol should be considered local for SVR4 PIC. */
15414 pic_need_relax (symbolS *sym, asection *segtype)
15418 /* Handle the case of a symbol equated to another symbol. */
15419 while (symbol_equated_reloc_p (sym))
15423 /* It's possible to get a loop here in a badly written program. */
15424 n = symbol_get_value_expression (sym)->X_add_symbol;
15430 if (symbol_section_p (sym))
15433 symsec = S_GET_SEGMENT (sym);
15435 /* This must duplicate the test in adjust_reloc_syms. */
15436 return (!bfd_is_und_section (symsec)
15437 && !bfd_is_abs_section (symsec)
15438 && !bfd_is_com_section (symsec)
15439 && !s_is_linkonce (sym, segtype)
15440 /* A global or weak symbol is treated as external. */
15441 && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym)));
15445 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
15446 extended opcode. SEC is the section the frag is in. */
15449 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
15452 const struct mips16_immed_operand *op;
15454 int mintiny, maxtiny;
15458 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
15460 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
15463 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
15464 op = mips16_immed_operands;
15465 while (op->type != type)
15468 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
15473 if (type == '<' || type == '>' || type == '[' || type == ']')
15476 maxtiny = 1 << op->nbits;
15481 maxtiny = (1 << op->nbits) - 1;
15486 mintiny = - (1 << (op->nbits - 1));
15487 maxtiny = (1 << (op->nbits - 1)) - 1;
15490 sym_frag = symbol_get_frag (fragp->fr_symbol);
15491 val = S_GET_VALUE (fragp->fr_symbol);
15492 symsec = S_GET_SEGMENT (fragp->fr_symbol);
15498 /* We won't have the section when we are called from
15499 mips_relax_frag. However, we will always have been called
15500 from md_estimate_size_before_relax first. If this is a
15501 branch to a different section, we mark it as such. If SEC is
15502 NULL, and the frag is not marked, then it must be a branch to
15503 the same section. */
15506 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
15511 /* Must have been called from md_estimate_size_before_relax. */
15514 fragp->fr_subtype =
15515 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
15517 /* FIXME: We should support this, and let the linker
15518 catch branches and loads that are out of range. */
15519 as_bad_where (fragp->fr_file, fragp->fr_line,
15520 _("unsupported PC relative reference to different section"));
15524 if (fragp != sym_frag && sym_frag->fr_address == 0)
15525 /* Assume non-extended on the first relaxation pass.
15526 The address we have calculated will be bogus if this is
15527 a forward branch to another frag, as the forward frag
15528 will have fr_address == 0. */
15532 /* In this case, we know for sure that the symbol fragment is in
15533 the same section. If the relax_marker of the symbol fragment
15534 differs from the relax_marker of this fragment, we have not
15535 yet adjusted the symbol fragment fr_address. We want to add
15536 in STRETCH in order to get a better estimate of the address.
15537 This particularly matters because of the shift bits. */
15539 && sym_frag->relax_marker != fragp->relax_marker)
15543 /* Adjust stretch for any alignment frag. Note that if have
15544 been expanding the earlier code, the symbol may be
15545 defined in what appears to be an earlier frag. FIXME:
15546 This doesn't handle the fr_subtype field, which specifies
15547 a maximum number of bytes to skip when doing an
15549 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
15551 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
15554 stretch = - ((- stretch)
15555 & ~ ((1 << (int) f->fr_offset) - 1));
15557 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
15566 addr = fragp->fr_address + fragp->fr_fix;
15568 /* The base address rules are complicated. The base address of
15569 a branch is the following instruction. The base address of a
15570 PC relative load or add is the instruction itself, but if it
15571 is in a delay slot (in which case it can not be extended) use
15572 the address of the instruction whose delay slot it is in. */
15573 if (type == 'p' || type == 'q')
15577 /* If we are currently assuming that this frag should be
15578 extended, then, the current address is two bytes
15580 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
15583 /* Ignore the low bit in the target, since it will be set
15584 for a text label. */
15585 if ((val & 1) != 0)
15588 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
15590 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
15593 val -= addr & ~ ((1 << op->shift) - 1);
15595 /* Branch offsets have an implicit 0 in the lowest bit. */
15596 if (type == 'p' || type == 'q')
15599 /* If any of the shifted bits are set, we must use an extended
15600 opcode. If the address depends on the size of this
15601 instruction, this can lead to a loop, so we arrange to always
15602 use an extended opcode. We only check this when we are in
15603 the main relaxation loop, when SEC is NULL. */
15604 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
15606 fragp->fr_subtype =
15607 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
15611 /* If we are about to mark a frag as extended because the value
15612 is precisely maxtiny + 1, then there is a chance of an
15613 infinite loop as in the following code:
15618 In this case when the la is extended, foo is 0x3fc bytes
15619 away, so the la can be shrunk, but then foo is 0x400 away, so
15620 the la must be extended. To avoid this loop, we mark the
15621 frag as extended if it was small, and is about to become
15622 extended with a value of maxtiny + 1. */
15623 if (val == ((maxtiny + 1) << op->shift)
15624 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
15627 fragp->fr_subtype =
15628 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
15632 else if (symsec != absolute_section && sec != NULL)
15633 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
15635 if ((val & ((1 << op->shift) - 1)) != 0
15636 || val < (mintiny << op->shift)
15637 || val > (maxtiny << op->shift))
15643 /* Compute the length of a branch sequence, and adjust the
15644 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
15645 worst-case length is computed, with UPDATE being used to indicate
15646 whether an unconditional (-1), branch-likely (+1) or regular (0)
15647 branch is to be computed. */
15649 relaxed_branch_length (fragS *fragp, asection *sec, int update)
15651 bfd_boolean toofar;
15655 && S_IS_DEFINED (fragp->fr_symbol)
15656 && sec == S_GET_SEGMENT (fragp->fr_symbol))
15661 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
15663 addr = fragp->fr_address + fragp->fr_fix + 4;
15667 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
15670 /* If the symbol is not defined or it's in a different segment,
15671 assume the user knows what's going on and emit a short
15677 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
15679 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
15680 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
15681 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
15682 RELAX_BRANCH_LINK (fragp->fr_subtype),
15688 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
15691 if (mips_pic != NO_PIC)
15693 /* Additional space for PIC loading of target address. */
15695 if (mips_opts.isa == ISA_MIPS1)
15696 /* Additional space for $at-stabilizing nop. */
15700 /* If branch is conditional. */
15701 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
15708 /* Compute the length of a branch sequence, and adjust the
15709 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
15710 worst-case length is computed, with UPDATE being used to indicate
15711 whether an unconditional (-1), or regular (0) branch is to be
15715 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
15717 bfd_boolean toofar;
15721 && S_IS_DEFINED (fragp->fr_symbol)
15722 && sec == S_GET_SEGMENT (fragp->fr_symbol))
15727 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
15728 /* Ignore the low bit in the target, since it will be set
15729 for a text label. */
15730 if ((val & 1) != 0)
15733 addr = fragp->fr_address + fragp->fr_fix + 4;
15737 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
15740 /* If the symbol is not defined or it's in a different segment,
15741 assume the user knows what's going on and emit a short
15747 if (fragp && update
15748 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
15749 fragp->fr_subtype = (toofar
15750 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
15751 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
15756 bfd_boolean compact_known = fragp != NULL;
15757 bfd_boolean compact = FALSE;
15758 bfd_boolean uncond;
15761 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
15763 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
15765 uncond = update < 0;
15767 /* If label is out of range, we turn branch <br>:
15769 <br> label # 4 bytes
15775 nop # 2 bytes if compact && !PIC
15778 if (mips_pic == NO_PIC && (!compact_known || compact))
15781 /* If assembling PIC code, we further turn:
15787 lw/ld at, %got(label)(gp) # 4 bytes
15788 d/addiu at, %lo(label) # 4 bytes
15791 if (mips_pic != NO_PIC)
15794 /* If branch <br> is conditional, we prepend negated branch <brneg>:
15796 <brneg> 0f # 4 bytes
15797 nop # 2 bytes if !compact
15800 length += (compact_known && compact) ? 4 : 6;
15806 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
15807 bit accordingly. */
15810 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
15812 bfd_boolean toofar;
15815 && S_IS_DEFINED (fragp->fr_symbol)
15816 && sec == S_GET_SEGMENT (fragp->fr_symbol))
15822 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
15823 /* Ignore the low bit in the target, since it will be set
15824 for a text label. */
15825 if ((val & 1) != 0)
15828 /* Assume this is a 2-byte branch. */
15829 addr = fragp->fr_address + fragp->fr_fix + 2;
15831 /* We try to avoid the infinite loop by not adding 2 more bytes for
15836 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
15838 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
15839 else if (type == 'E')
15840 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
15845 /* If the symbol is not defined or it's in a different segment,
15846 we emit a normal 32-bit branch. */
15849 if (fragp && update
15850 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
15852 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
15853 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
15861 /* Estimate the size of a frag before relaxing. Unless this is the
15862 mips16, we are not really relaxing here, and the final size is
15863 encoded in the subtype information. For the mips16, we have to
15864 decide whether we are using an extended opcode or not. */
15867 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
15871 if (RELAX_BRANCH_P (fragp->fr_subtype))
15874 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
15876 return fragp->fr_var;
15879 if (RELAX_MIPS16_P (fragp->fr_subtype))
15880 /* We don't want to modify the EXTENDED bit here; it might get us
15881 into infinite loops. We change it only in mips_relax_frag(). */
15882 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
15884 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
15888 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
15889 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
15890 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
15891 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
15892 fragp->fr_var = length;
15897 if (mips_pic == NO_PIC)
15898 change = nopic_need_relax (fragp->fr_symbol, 0);
15899 else if (mips_pic == SVR4_PIC)
15900 change = pic_need_relax (fragp->fr_symbol, segtype);
15901 else if (mips_pic == VXWORKS_PIC)
15902 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
15909 fragp->fr_subtype |= RELAX_USE_SECOND;
15910 return -RELAX_FIRST (fragp->fr_subtype);
15913 return -RELAX_SECOND (fragp->fr_subtype);
15916 /* This is called to see whether a reloc against a defined symbol
15917 should be converted into a reloc against a section. */
15920 mips_fix_adjustable (fixS *fixp)
15922 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
15923 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
15926 if (fixp->fx_addsy == NULL)
15929 /* If symbol SYM is in a mergeable section, relocations of the form
15930 SYM + 0 can usually be made section-relative. The mergeable data
15931 is then identified by the section offset rather than by the symbol.
15933 However, if we're generating REL LO16 relocations, the offset is split
15934 between the LO16 and parterning high part relocation. The linker will
15935 need to recalculate the complete offset in order to correctly identify
15938 The linker has traditionally not looked for the parterning high part
15939 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
15940 placed anywhere. Rather than break backwards compatibility by changing
15941 this, it seems better not to force the issue, and instead keep the
15942 original symbol. This will work with either linker behavior. */
15943 if ((lo16_reloc_p (fixp->fx_r_type)
15944 || reloc_needs_lo_p (fixp->fx_r_type))
15945 && HAVE_IN_PLACE_ADDENDS
15946 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
15949 /* There is no place to store an in-place offset for JALR relocations.
15950 Likewise an in-range offset of limited PC-relative relocations may
15951 overflow the in-place relocatable field if recalculated against the
15952 start address of the symbol's containing section. */
15953 if (HAVE_IN_PLACE_ADDENDS
15954 && (limited_pcrel_reloc_p (fixp->fx_r_type)
15955 || jalr_reloc_p (fixp->fx_r_type)))
15958 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
15959 to a floating-point stub. The same is true for non-R_MIPS16_26
15960 relocations against MIPS16 functions; in this case, the stub becomes
15961 the function's canonical address.
15963 Floating-point stubs are stored in unique .mips16.call.* or
15964 .mips16.fn.* sections. If a stub T for function F is in section S,
15965 the first relocation in section S must be against F; this is how the
15966 linker determines the target function. All relocations that might
15967 resolve to T must also be against F. We therefore have the following
15968 restrictions, which are given in an intentionally-redundant way:
15970 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
15973 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
15974 if that stub might be used.
15976 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
15979 4. We cannot reduce a stub's relocations against MIPS16 symbols if
15980 that stub might be used.
15982 There is a further restriction:
15984 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
15985 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
15986 targets with in-place addends; the relocation field cannot
15987 encode the low bit.
15989 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
15990 against a MIPS16 symbol. We deal with (5) by by not reducing any
15991 such relocations on REL targets.
15993 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
15994 relocation against some symbol R, no relocation against R may be
15995 reduced. (Note that this deals with (2) as well as (1) because
15996 relocations against global symbols will never be reduced on ELF
15997 targets.) This approach is a little simpler than trying to detect
15998 stub sections, and gives the "all or nothing" per-symbol consistency
15999 that we have for MIPS16 symbols. */
16000 if (fixp->fx_subsy == NULL
16001 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
16002 || *symbol_get_tc (fixp->fx_addsy)
16003 || (HAVE_IN_PLACE_ADDENDS
16004 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
16005 && jmp_reloc_p (fixp->fx_r_type))))
16011 /* Translate internal representation of relocation info to BFD target
16015 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
16017 static arelent *retval[4];
16019 bfd_reloc_code_real_type code;
16021 memset (retval, 0, sizeof(retval));
16022 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
16023 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
16024 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
16025 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
16027 if (fixp->fx_pcrel)
16029 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
16030 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
16031 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
16032 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
16033 || fixp->fx_r_type == BFD_RELOC_32_PCREL);
16035 /* At this point, fx_addnumber is "symbol offset - pcrel address".
16036 Relocations want only the symbol offset. */
16037 reloc->addend = fixp->fx_addnumber + reloc->address;
16040 reloc->addend = fixp->fx_addnumber;
16042 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
16043 entry to be used in the relocation's section offset. */
16044 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
16046 reloc->address = reloc->addend;
16050 code = fixp->fx_r_type;
16052 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
16053 if (reloc->howto == NULL)
16055 as_bad_where (fixp->fx_file, fixp->fx_line,
16056 _("Can not represent %s relocation in this object file format"),
16057 bfd_get_reloc_code_name (code));
16064 /* Relax a machine dependent frag. This returns the amount by which
16065 the current size of the frag should change. */
16068 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
16070 if (RELAX_BRANCH_P (fragp->fr_subtype))
16072 offsetT old_var = fragp->fr_var;
16074 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
16076 return fragp->fr_var - old_var;
16079 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
16081 offsetT old_var = fragp->fr_var;
16082 offsetT new_var = 4;
16084 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
16085 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
16086 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
16087 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
16088 fragp->fr_var = new_var;
16090 return new_var - old_var;
16093 if (! RELAX_MIPS16_P (fragp->fr_subtype))
16096 if (mips16_extended_frag (fragp, NULL, stretch))
16098 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
16100 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
16105 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
16107 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
16114 /* Convert a machine dependent frag. */
16117 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
16119 if (RELAX_BRANCH_P (fragp->fr_subtype))
16122 unsigned long insn;
16126 buf = fragp->fr_literal + fragp->fr_fix;
16127 insn = read_insn (buf);
16129 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
16131 /* We generate a fixup instead of applying it right now
16132 because, if there are linker relaxations, we're going to
16133 need the relocations. */
16134 exp.X_op = O_symbol;
16135 exp.X_add_symbol = fragp->fr_symbol;
16136 exp.X_add_number = fragp->fr_offset;
16138 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
16139 BFD_RELOC_16_PCREL_S2);
16140 fixp->fx_file = fragp->fr_file;
16141 fixp->fx_line = fragp->fr_line;
16143 buf = write_insn (buf, insn);
16149 as_warn_where (fragp->fr_file, fragp->fr_line,
16150 _("Relaxed out-of-range branch into a jump"));
16152 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
16155 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
16157 /* Reverse the branch. */
16158 switch ((insn >> 28) & 0xf)
16161 /* bc[0-3][tf]l? instructions can have the condition
16162 reversed by tweaking a single TF bit, and their
16163 opcodes all have 0x4???????. */
16164 gas_assert ((insn & 0xf3e00000) == 0x41000000);
16165 insn ^= 0x00010000;
16169 /* bltz 0x04000000 bgez 0x04010000
16170 bltzal 0x04100000 bgezal 0x04110000 */
16171 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
16172 insn ^= 0x00010000;
16176 /* beq 0x10000000 bne 0x14000000
16177 blez 0x18000000 bgtz 0x1c000000 */
16178 insn ^= 0x04000000;
16186 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
16188 /* Clear the and-link bit. */
16189 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
16191 /* bltzal 0x04100000 bgezal 0x04110000
16192 bltzall 0x04120000 bgezall 0x04130000 */
16193 insn &= ~0x00100000;
16196 /* Branch over the branch (if the branch was likely) or the
16197 full jump (not likely case). Compute the offset from the
16198 current instruction to branch to. */
16199 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
16203 /* How many bytes in instructions we've already emitted? */
16204 i = buf - fragp->fr_literal - fragp->fr_fix;
16205 /* How many bytes in instructions from here to the end? */
16206 i = fragp->fr_var - i;
16208 /* Convert to instruction count. */
16210 /* Branch counts from the next instruction. */
16213 /* Branch over the jump. */
16214 buf = write_insn (buf, insn);
16217 buf = write_insn (buf, 0);
16219 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
16221 /* beql $0, $0, 2f */
16223 /* Compute the PC offset from the current instruction to
16224 the end of the variable frag. */
16225 /* How many bytes in instructions we've already emitted? */
16226 i = buf - fragp->fr_literal - fragp->fr_fix;
16227 /* How many bytes in instructions from here to the end? */
16228 i = fragp->fr_var - i;
16229 /* Convert to instruction count. */
16231 /* Don't decrement i, because we want to branch over the
16235 buf = write_insn (buf, insn);
16236 buf = write_insn (buf, 0);
16240 if (mips_pic == NO_PIC)
16243 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
16244 ? 0x0c000000 : 0x08000000);
16245 exp.X_op = O_symbol;
16246 exp.X_add_symbol = fragp->fr_symbol;
16247 exp.X_add_number = fragp->fr_offset;
16249 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
16250 FALSE, BFD_RELOC_MIPS_JMP);
16251 fixp->fx_file = fragp->fr_file;
16252 fixp->fx_line = fragp->fr_line;
16254 buf = write_insn (buf, insn);
16258 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
16260 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
16261 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
16262 insn |= at << OP_SH_RT;
16263 exp.X_op = O_symbol;
16264 exp.X_add_symbol = fragp->fr_symbol;
16265 exp.X_add_number = fragp->fr_offset;
16267 if (fragp->fr_offset)
16269 exp.X_add_symbol = make_expr_symbol (&exp);
16270 exp.X_add_number = 0;
16273 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
16274 FALSE, BFD_RELOC_MIPS_GOT16);
16275 fixp->fx_file = fragp->fr_file;
16276 fixp->fx_line = fragp->fr_line;
16278 buf = write_insn (buf, insn);
16280 if (mips_opts.isa == ISA_MIPS1)
16282 buf = write_insn (buf, 0);
16284 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
16285 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
16286 insn |= at << OP_SH_RS | at << OP_SH_RT;
16288 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
16289 FALSE, BFD_RELOC_LO16);
16290 fixp->fx_file = fragp->fr_file;
16291 fixp->fx_line = fragp->fr_line;
16293 buf = write_insn (buf, insn);
16296 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
16300 insn |= at << OP_SH_RS;
16302 buf = write_insn (buf, insn);
16306 fragp->fr_fix += fragp->fr_var;
16307 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
16311 /* Relax microMIPS branches. */
16312 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
16314 char *buf = fragp->fr_literal + fragp->fr_fix;
16315 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
16316 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
16317 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
16318 bfd_boolean short_ds;
16319 unsigned long insn;
16323 exp.X_op = O_symbol;
16324 exp.X_add_symbol = fragp->fr_symbol;
16325 exp.X_add_number = fragp->fr_offset;
16327 fragp->fr_fix += fragp->fr_var;
16329 /* Handle 16-bit branches that fit or are forced to fit. */
16330 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
16332 /* We generate a fixup instead of applying it right now,
16333 because if there is linker relaxation, we're going to
16334 need the relocations. */
16336 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
16337 BFD_RELOC_MICROMIPS_10_PCREL_S1);
16338 else if (type == 'E')
16339 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
16340 BFD_RELOC_MICROMIPS_7_PCREL_S1);
16344 fixp->fx_file = fragp->fr_file;
16345 fixp->fx_line = fragp->fr_line;
16347 /* These relocations can have an addend that won't fit in
16349 fixp->fx_no_overflow = 1;
16354 /* Handle 32-bit branches that fit or are forced to fit. */
16355 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
16356 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
16358 /* We generate a fixup instead of applying it right now,
16359 because if there is linker relaxation, we're going to
16360 need the relocations. */
16361 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
16362 BFD_RELOC_MICROMIPS_16_PCREL_S1);
16363 fixp->fx_file = fragp->fr_file;
16364 fixp->fx_line = fragp->fr_line;
16370 /* Relax 16-bit branches to 32-bit branches. */
16373 insn = read_compressed_insn (buf, 2);
16375 if ((insn & 0xfc00) == 0xcc00) /* b16 */
16376 insn = 0x94000000; /* beq */
16377 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
16379 unsigned long regno;
16381 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
16382 regno = micromips_to_32_reg_d_map [regno];
16383 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
16384 insn |= regno << MICROMIPSOP_SH_RS;
16389 /* Nothing else to do, just write it out. */
16390 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
16391 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
16393 buf = write_compressed_insn (buf, insn, 4);
16394 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
16399 insn = read_compressed_insn (buf, 4);
16401 /* Relax 32-bit branches to a sequence of instructions. */
16402 as_warn_where (fragp->fr_file, fragp->fr_line,
16403 _("Relaxed out-of-range branch into a jump"));
16405 /* Set the short-delay-slot bit. */
16406 short_ds = al && (insn & 0x02000000) != 0;
16408 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
16412 /* Reverse the branch. */
16413 if ((insn & 0xfc000000) == 0x94000000 /* beq */
16414 || (insn & 0xfc000000) == 0xb4000000) /* bne */
16415 insn ^= 0x20000000;
16416 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
16417 || (insn & 0xffe00000) == 0x40400000 /* bgez */
16418 || (insn & 0xffe00000) == 0x40800000 /* blez */
16419 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
16420 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
16421 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
16422 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
16423 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
16424 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
16425 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
16426 insn ^= 0x00400000;
16427 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
16428 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
16429 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
16430 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
16431 insn ^= 0x00200000;
16437 /* Clear the and-link and short-delay-slot bits. */
16438 gas_assert ((insn & 0xfda00000) == 0x40200000);
16440 /* bltzal 0x40200000 bgezal 0x40600000 */
16441 /* bltzals 0x42200000 bgezals 0x42600000 */
16442 insn &= ~0x02200000;
16445 /* Make a label at the end for use with the branch. */
16446 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
16447 micromips_label_inc ();
16448 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
16451 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE,
16452 BFD_RELOC_MICROMIPS_16_PCREL_S1);
16453 fixp->fx_file = fragp->fr_file;
16454 fixp->fx_line = fragp->fr_line;
16456 /* Branch over the jump. */
16457 buf = write_compressed_insn (buf, insn, 4);
16460 buf = write_compressed_insn (buf, 0x0c00, 2);
16463 if (mips_pic == NO_PIC)
16465 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
16467 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
16468 insn = al ? jal : 0xd4000000;
16470 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
16471 BFD_RELOC_MICROMIPS_JMP);
16472 fixp->fx_file = fragp->fr_file;
16473 fixp->fx_line = fragp->fr_line;
16475 buf = write_compressed_insn (buf, insn, 4);
16478 buf = write_compressed_insn (buf, 0x0c00, 2);
16482 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
16483 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
16484 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
16486 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
16487 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
16488 insn |= at << MICROMIPSOP_SH_RT;
16490 if (exp.X_add_number)
16492 exp.X_add_symbol = make_expr_symbol (&exp);
16493 exp.X_add_number = 0;
16496 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
16497 BFD_RELOC_MICROMIPS_GOT16);
16498 fixp->fx_file = fragp->fr_file;
16499 fixp->fx_line = fragp->fr_line;
16501 buf = write_compressed_insn (buf, insn, 4);
16503 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
16504 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
16505 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
16507 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
16508 BFD_RELOC_MICROMIPS_LO16);
16509 fixp->fx_file = fragp->fr_file;
16510 fixp->fx_line = fragp->fr_line;
16512 buf = write_compressed_insn (buf, insn, 4);
16514 /* jr/jrc/jalr/jalrs $at */
16515 insn = al ? jalr : jr;
16516 insn |= at << MICROMIPSOP_SH_MJ;
16518 buf = write_compressed_insn (buf, insn, 2);
16521 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
16525 if (RELAX_MIPS16_P (fragp->fr_subtype))
16528 const struct mips16_immed_operand *op;
16531 unsigned int user_length, length;
16532 unsigned long insn;
16535 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
16536 op = mips16_immed_operands;
16537 while (op->type != type)
16540 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
16541 val = resolve_symbol_value (fragp->fr_symbol);
16546 addr = fragp->fr_address + fragp->fr_fix;
16548 /* The rules for the base address of a PC relative reloc are
16549 complicated; see mips16_extended_frag. */
16550 if (type == 'p' || type == 'q')
16555 /* Ignore the low bit in the target, since it will be
16556 set for a text label. */
16557 if ((val & 1) != 0)
16560 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
16562 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
16565 addr &= ~ (addressT) ((1 << op->shift) - 1);
16568 /* Make sure the section winds up with the alignment we have
16571 record_alignment (asec, op->shift);
16575 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
16576 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
16577 as_warn_where (fragp->fr_file, fragp->fr_line,
16578 _("extended instruction in delay slot"));
16580 buf = fragp->fr_literal + fragp->fr_fix;
16582 insn = read_compressed_insn (buf, 2);
16584 insn |= MIPS16_EXTEND;
16586 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
16588 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
16593 mips16_immed (fragp->fr_file, fragp->fr_line, type,
16594 BFD_RELOC_UNUSED, val, user_length, &insn);
16596 length = (ext ? 4 : 2);
16597 gas_assert (mips16_opcode_length (insn) == length);
16598 write_compressed_insn (buf, insn, length);
16599 fragp->fr_fix += length;
16603 relax_substateT subtype = fragp->fr_subtype;
16604 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
16605 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
16609 first = RELAX_FIRST (subtype);
16610 second = RELAX_SECOND (subtype);
16611 fixp = (fixS *) fragp->fr_opcode;
16613 /* If the delay slot chosen does not match the size of the instruction,
16614 then emit a warning. */
16615 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
16616 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
16621 s = subtype & (RELAX_DELAY_SLOT_16BIT
16622 | RELAX_DELAY_SLOT_SIZE_FIRST
16623 | RELAX_DELAY_SLOT_SIZE_SECOND);
16624 msg = macro_warning (s);
16626 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
16630 /* Possibly emit a warning if we've chosen the longer option. */
16631 if (use_second == second_longer)
16637 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
16638 msg = macro_warning (s);
16640 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
16644 /* Go through all the fixups for the first sequence. Disable them
16645 (by marking them as done) if we're going to use the second
16646 sequence instead. */
16648 && fixp->fx_frag == fragp
16649 && fixp->fx_where < fragp->fr_fix - second)
16651 if (subtype & RELAX_USE_SECOND)
16653 fixp = fixp->fx_next;
16656 /* Go through the fixups for the second sequence. Disable them if
16657 we're going to use the first sequence, otherwise adjust their
16658 addresses to account for the relaxation. */
16659 while (fixp && fixp->fx_frag == fragp)
16661 if (subtype & RELAX_USE_SECOND)
16662 fixp->fx_where -= first;
16665 fixp = fixp->fx_next;
16668 /* Now modify the frag contents. */
16669 if (subtype & RELAX_USE_SECOND)
16673 start = fragp->fr_literal + fragp->fr_fix - first - second;
16674 memmove (start, start + first, second);
16675 fragp->fr_fix -= first;
16678 fragp->fr_fix -= second;
16682 /* This function is called after the relocs have been generated.
16683 We've been storing mips16 text labels as odd. Here we convert them
16684 back to even for the convenience of the debugger. */
16687 mips_frob_file_after_relocs (void)
16690 unsigned int count, i;
16692 syms = bfd_get_outsymbols (stdoutput);
16693 count = bfd_get_symcount (stdoutput);
16694 for (i = 0; i < count; i++, syms++)
16695 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
16696 && ((*syms)->value & 1) != 0)
16698 (*syms)->value &= ~1;
16699 /* If the symbol has an odd size, it was probably computed
16700 incorrectly, so adjust that as well. */
16701 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
16702 ++elf_symbol (*syms)->internal_elf_sym.st_size;
16706 /* This function is called whenever a label is defined, including fake
16707 labels instantiated off the dot special symbol. It is used when
16708 handling branch delays; if a branch has a label, we assume we cannot
16709 move it. This also bumps the value of the symbol by 1 in compressed
16713 mips_record_label (symbolS *sym)
16715 segment_info_type *si = seg_info (now_seg);
16716 struct insn_label_list *l;
16718 if (free_insn_labels == NULL)
16719 l = (struct insn_label_list *) xmalloc (sizeof *l);
16722 l = free_insn_labels;
16723 free_insn_labels = l->next;
16727 l->next = si->label_list;
16728 si->label_list = l;
16731 /* This function is called as tc_frob_label() whenever a label is defined
16732 and adds a DWARF-2 record we only want for true labels. */
16735 mips_define_label (symbolS *sym)
16737 mips_record_label (sym);
16738 dwarf2_emit_label (sym);
16741 /* This function is called by tc_new_dot_label whenever a new dot symbol
16745 mips_add_dot_label (symbolS *sym)
16747 mips_record_label (sym);
16748 if (mips_assembling_insn && HAVE_CODE_COMPRESSION)
16749 mips_compressed_mark_label (sym);
16752 /* Some special processing for a MIPS ELF file. */
16755 mips_elf_final_processing (void)
16757 /* Write out the register information. */
16758 if (mips_abi != N64_ABI)
16762 s.ri_gprmask = mips_gprmask;
16763 s.ri_cprmask[0] = mips_cprmask[0];
16764 s.ri_cprmask[1] = mips_cprmask[1];
16765 s.ri_cprmask[2] = mips_cprmask[2];
16766 s.ri_cprmask[3] = mips_cprmask[3];
16767 /* The gp_value field is set by the MIPS ELF backend. */
16769 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
16770 ((Elf32_External_RegInfo *)
16771 mips_regmask_frag));
16775 Elf64_Internal_RegInfo s;
16777 s.ri_gprmask = mips_gprmask;
16779 s.ri_cprmask[0] = mips_cprmask[0];
16780 s.ri_cprmask[1] = mips_cprmask[1];
16781 s.ri_cprmask[2] = mips_cprmask[2];
16782 s.ri_cprmask[3] = mips_cprmask[3];
16783 /* The gp_value field is set by the MIPS ELF backend. */
16785 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
16786 ((Elf64_External_RegInfo *)
16787 mips_regmask_frag));
16790 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
16791 sort of BFD interface for this. */
16792 if (mips_any_noreorder)
16793 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
16794 if (mips_pic != NO_PIC)
16796 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
16797 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
16800 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
16802 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
16803 defined at present; this might need to change in future. */
16804 if (file_ase_mips16)
16805 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
16806 if (file_ase_micromips)
16807 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
16808 if (file_ase & ASE_MDMX)
16809 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
16811 /* Set the MIPS ELF ABI flags. */
16812 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
16813 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
16814 else if (mips_abi == O64_ABI)
16815 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
16816 else if (mips_abi == EABI_ABI)
16818 if (!file_mips_gp32)
16819 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
16821 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
16823 else if (mips_abi == N32_ABI)
16824 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
16826 /* Nothing to do for N64_ABI. */
16828 if (mips_32bitmode)
16829 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
16831 if (mips_flag_nan2008)
16832 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008;
16834 #if 0 /* XXX FIXME */
16835 /* 32 bit code with 64 bit FP registers. */
16836 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
16837 elf_elfheader (stdoutput)->e_flags |= ???;
16841 typedef struct proc {
16843 symbolS *func_end_sym;
16844 unsigned long reg_mask;
16845 unsigned long reg_offset;
16846 unsigned long fpreg_mask;
16847 unsigned long fpreg_offset;
16848 unsigned long frame_offset;
16849 unsigned long frame_reg;
16850 unsigned long pc_reg;
16853 static procS cur_proc;
16854 static procS *cur_proc_ptr;
16855 static int numprocs;
16857 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
16858 as "2", and a normal nop as "0". */
16860 #define NOP_OPCODE_MIPS 0
16861 #define NOP_OPCODE_MIPS16 1
16862 #define NOP_OPCODE_MICROMIPS 2
16865 mips_nop_opcode (void)
16867 if (seg_info (now_seg)->tc_segment_info_data.micromips)
16868 return NOP_OPCODE_MICROMIPS;
16869 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
16870 return NOP_OPCODE_MIPS16;
16872 return NOP_OPCODE_MIPS;
16875 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
16876 32-bit microMIPS NOPs here (if applicable). */
16879 mips_handle_align (fragS *fragp)
16883 int bytes, size, excess;
16886 if (fragp->fr_type != rs_align_code)
16889 p = fragp->fr_literal + fragp->fr_fix;
16891 switch (nop_opcode)
16893 case NOP_OPCODE_MICROMIPS:
16894 opcode = micromips_nop32_insn.insn_opcode;
16897 case NOP_OPCODE_MIPS16:
16898 opcode = mips16_nop_insn.insn_opcode;
16901 case NOP_OPCODE_MIPS:
16903 opcode = nop_insn.insn_opcode;
16908 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
16909 excess = bytes % size;
16911 /* Handle the leading part if we're not inserting a whole number of
16912 instructions, and make it the end of the fixed part of the frag.
16913 Try to fit in a short microMIPS NOP if applicable and possible,
16914 and use zeroes otherwise. */
16915 gas_assert (excess < 4);
16916 fragp->fr_fix += excess;
16921 /* Fall through. */
16923 if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32)
16925 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2);
16929 /* Fall through. */
16932 /* Fall through. */
16937 md_number_to_chars (p, opcode, size);
16938 fragp->fr_var = size;
16942 md_obj_begin (void)
16949 /* Check for premature end, nesting errors, etc. */
16951 as_warn (_("missing .end at end of assembly"));
16960 if (*input_line_pointer == '-')
16962 ++input_line_pointer;
16965 if (!ISDIGIT (*input_line_pointer))
16966 as_bad (_("expected simple number"));
16967 if (input_line_pointer[0] == '0')
16969 if (input_line_pointer[1] == 'x')
16971 input_line_pointer += 2;
16972 while (ISXDIGIT (*input_line_pointer))
16975 val |= hex_value (*input_line_pointer++);
16977 return negative ? -val : val;
16981 ++input_line_pointer;
16982 while (ISDIGIT (*input_line_pointer))
16985 val |= *input_line_pointer++ - '0';
16987 return negative ? -val : val;
16990 if (!ISDIGIT (*input_line_pointer))
16992 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
16993 *input_line_pointer, *input_line_pointer);
16994 as_warn (_("invalid number"));
16997 while (ISDIGIT (*input_line_pointer))
17000 val += *input_line_pointer++ - '0';
17002 return negative ? -val : val;
17005 /* The .file directive; just like the usual .file directive, but there
17006 is an initial number which is the ECOFF file index. In the non-ECOFF
17007 case .file implies DWARF-2. */
17010 s_mips_file (int x ATTRIBUTE_UNUSED)
17012 static int first_file_directive = 0;
17014 if (ECOFF_DEBUGGING)
17023 filename = dwarf2_directive_file (0);
17025 /* Versions of GCC up to 3.1 start files with a ".file"
17026 directive even for stabs output. Make sure that this
17027 ".file" is handled. Note that you need a version of GCC
17028 after 3.1 in order to support DWARF-2 on MIPS. */
17029 if (filename != NULL && ! first_file_directive)
17031 (void) new_logical_line (filename, -1);
17032 s_app_file_string (filename, 0);
17034 first_file_directive = 1;
17038 /* The .loc directive, implying DWARF-2. */
17041 s_mips_loc (int x ATTRIBUTE_UNUSED)
17043 if (!ECOFF_DEBUGGING)
17044 dwarf2_directive_loc (0);
17047 /* The .end directive. */
17050 s_mips_end (int x ATTRIBUTE_UNUSED)
17054 /* Following functions need their own .frame and .cprestore directives. */
17055 mips_frame_reg_valid = 0;
17056 mips_cprestore_valid = 0;
17058 if (!is_end_of_line[(unsigned char) *input_line_pointer])
17061 demand_empty_rest_of_line ();
17066 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
17067 as_warn (_(".end not in text section"));
17071 as_warn (_(".end directive without a preceding .ent directive."));
17072 demand_empty_rest_of_line ();
17078 gas_assert (S_GET_NAME (p));
17079 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
17080 as_warn (_(".end symbol does not match .ent symbol."));
17082 if (debug_type == DEBUG_STABS)
17083 stabs_generate_asm_endfunc (S_GET_NAME (p),
17087 as_warn (_(".end directive missing or unknown symbol"));
17089 /* Create an expression to calculate the size of the function. */
17090 if (p && cur_proc_ptr)
17092 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
17093 expressionS *exp = xmalloc (sizeof (expressionS));
17096 exp->X_op = O_subtract;
17097 exp->X_add_symbol = symbol_temp_new_now ();
17098 exp->X_op_symbol = p;
17099 exp->X_add_number = 0;
17101 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
17104 /* Generate a .pdr section. */
17105 if (!ECOFF_DEBUGGING && mips_flag_pdr)
17107 segT saved_seg = now_seg;
17108 subsegT saved_subseg = now_subseg;
17112 #ifdef md_flush_pending_output
17113 md_flush_pending_output ();
17116 gas_assert (pdr_seg);
17117 subseg_set (pdr_seg, 0);
17119 /* Write the symbol. */
17120 exp.X_op = O_symbol;
17121 exp.X_add_symbol = p;
17122 exp.X_add_number = 0;
17123 emit_expr (&exp, 4);
17125 fragp = frag_more (7 * 4);
17127 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
17128 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
17129 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
17130 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
17131 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
17132 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
17133 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
17135 subseg_set (saved_seg, saved_subseg);
17138 cur_proc_ptr = NULL;
17141 /* The .aent and .ent directives. */
17144 s_mips_ent (int aent)
17148 symbolP = get_symbol ();
17149 if (*input_line_pointer == ',')
17150 ++input_line_pointer;
17151 SKIP_WHITESPACE ();
17152 if (ISDIGIT (*input_line_pointer)
17153 || *input_line_pointer == '-')
17156 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
17157 as_warn (_(".ent or .aent not in text section."));
17159 if (!aent && cur_proc_ptr)
17160 as_warn (_("missing .end"));
17164 /* This function needs its own .frame and .cprestore directives. */
17165 mips_frame_reg_valid = 0;
17166 mips_cprestore_valid = 0;
17168 cur_proc_ptr = &cur_proc;
17169 memset (cur_proc_ptr, '\0', sizeof (procS));
17171 cur_proc_ptr->func_sym = symbolP;
17175 if (debug_type == DEBUG_STABS)
17176 stabs_generate_asm_func (S_GET_NAME (symbolP),
17177 S_GET_NAME (symbolP));
17180 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
17182 demand_empty_rest_of_line ();
17185 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
17186 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
17187 s_mips_frame is used so that we can set the PDR information correctly.
17188 We can't use the ecoff routines because they make reference to the ecoff
17189 symbol table (in the mdebug section). */
17192 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
17194 if (ECOFF_DEBUGGING)
17200 if (cur_proc_ptr == (procS *) NULL)
17202 as_warn (_(".frame outside of .ent"));
17203 demand_empty_rest_of_line ();
17207 cur_proc_ptr->frame_reg = tc_get_register (1);
17209 SKIP_WHITESPACE ();
17210 if (*input_line_pointer++ != ','
17211 || get_absolute_expression_and_terminator (&val) != ',')
17213 as_warn (_("Bad .frame directive"));
17214 --input_line_pointer;
17215 demand_empty_rest_of_line ();
17219 cur_proc_ptr->frame_offset = val;
17220 cur_proc_ptr->pc_reg = tc_get_register (0);
17222 demand_empty_rest_of_line ();
17226 /* The .fmask and .mask directives. If the mdebug section is present
17227 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
17228 embedded targets, s_mips_mask is used so that we can set the PDR
17229 information correctly. We can't use the ecoff routines because they
17230 make reference to the ecoff symbol table (in the mdebug section). */
17233 s_mips_mask (int reg_type)
17235 if (ECOFF_DEBUGGING)
17236 s_ignore (reg_type);
17241 if (cur_proc_ptr == (procS *) NULL)
17243 as_warn (_(".mask/.fmask outside of .ent"));
17244 demand_empty_rest_of_line ();
17248 if (get_absolute_expression_and_terminator (&mask) != ',')
17250 as_warn (_("Bad .mask/.fmask directive"));
17251 --input_line_pointer;
17252 demand_empty_rest_of_line ();
17256 off = get_absolute_expression ();
17258 if (reg_type == 'F')
17260 cur_proc_ptr->fpreg_mask = mask;
17261 cur_proc_ptr->fpreg_offset = off;
17265 cur_proc_ptr->reg_mask = mask;
17266 cur_proc_ptr->reg_offset = off;
17269 demand_empty_rest_of_line ();
17273 /* A table describing all the processors gas knows about. Names are
17274 matched in the order listed.
17276 To ease comparison, please keep this table in the same order as
17277 gcc's mips_cpu_info_table[]. */
17278 static const struct mips_cpu_info mips_cpu_info_table[] =
17280 /* Entries for generic ISAs */
17281 { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 },
17282 { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 },
17283 { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 },
17284 { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 },
17285 { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 },
17286 { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 },
17287 { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17288 { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 },
17289 { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 },
17292 { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 },
17293 { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 },
17294 { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 },
17297 { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 },
17300 { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 },
17301 { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 },
17302 { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 },
17303 { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 },
17304 { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 },
17305 { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 },
17306 { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 },
17307 { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 },
17308 { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 },
17309 { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 },
17310 { "orion", 0, 0, ISA_MIPS3, CPU_R4600 },
17311 { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 },
17312 { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 },
17313 /* ST Microelectronics Loongson 2E and 2F cores */
17314 { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E },
17315 { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F },
17318 { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 },
17319 { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 },
17320 { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 },
17321 { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 },
17322 { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 },
17323 { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 },
17324 { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 },
17325 { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 },
17326 { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 },
17327 { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 },
17328 { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 },
17329 { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 },
17330 { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 },
17331 { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 },
17332 { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 },
17335 { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 },
17336 { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 },
17337 { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 },
17338 { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
17340 /* MIPS 32 Release 2 */
17341 { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17342 { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17343 { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17344 { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
17345 { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17346 { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17347 { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
17348 { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
17349 { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
17350 ISA_MIPS32R2, CPU_MIPS32R2 },
17351 { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
17352 ISA_MIPS32R2, CPU_MIPS32R2 },
17353 { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17354 { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17355 { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17356 { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17357 /* Deprecated forms of the above. */
17358 { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17359 { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17360 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
17361 { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17362 { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17363 { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17364 { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17365 /* Deprecated forms of the above. */
17366 { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17367 { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17368 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
17369 { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17370 { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17371 { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17372 { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17373 /* Deprecated forms of the above. */
17374 { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17375 { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17376 /* 34Kn is a 34kc without DSP. */
17377 { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17378 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
17379 { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17380 { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17381 { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17382 { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17383 { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17384 /* Deprecated forms of the above. */
17385 { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17386 { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17387 /* 1004K cores are multiprocessor versions of the 34K. */
17388 { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17389 { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17390 { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17391 { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17394 { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 },
17395 { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 },
17396 { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
17397 { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
17399 /* Broadcom SB-1 CPU core */
17400 { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
17401 /* Broadcom SB-1A CPU core */
17402 { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
17404 { "loongson3a", 0, 0, ISA_MIPS64, CPU_LOONGSON_3A },
17406 /* MIPS 64 Release 2 */
17408 /* Cavium Networks Octeon CPU core */
17409 { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
17410 { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP },
17411 { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 },
17414 { "xlr", 0, 0, ISA_MIPS64, CPU_XLR },
17417 XLP is mostly like XLR, with the prominent exception that it is
17418 MIPS64R2 rather than MIPS64. */
17419 { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
17422 { NULL, 0, 0, 0, 0 }
17426 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
17427 with a final "000" replaced by "k". Ignore case.
17429 Note: this function is shared between GCC and GAS. */
17432 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
17434 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
17435 given++, canonical++;
17437 return ((*given == 0 && *canonical == 0)
17438 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
17442 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
17443 CPU name. We've traditionally allowed a lot of variation here.
17445 Note: this function is shared between GCC and GAS. */
17448 mips_matching_cpu_name_p (const char *canonical, const char *given)
17450 /* First see if the name matches exactly, or with a final "000"
17451 turned into "k". */
17452 if (mips_strict_matching_cpu_name_p (canonical, given))
17455 /* If not, try comparing based on numerical designation alone.
17456 See if GIVEN is an unadorned number, or 'r' followed by a number. */
17457 if (TOLOWER (*given) == 'r')
17459 if (!ISDIGIT (*given))
17462 /* Skip over some well-known prefixes in the canonical name,
17463 hoping to find a number there too. */
17464 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
17466 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
17468 else if (TOLOWER (canonical[0]) == 'r')
17471 return mips_strict_matching_cpu_name_p (canonical, given);
17475 /* Parse an option that takes the name of a processor as its argument.
17476 OPTION is the name of the option and CPU_STRING is the argument.
17477 Return the corresponding processor enumeration if the CPU_STRING is
17478 recognized, otherwise report an error and return null.
17480 A similar function exists in GCC. */
17482 static const struct mips_cpu_info *
17483 mips_parse_cpu (const char *option, const char *cpu_string)
17485 const struct mips_cpu_info *p;
17487 /* 'from-abi' selects the most compatible architecture for the given
17488 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
17489 EABIs, we have to decide whether we're using the 32-bit or 64-bit
17490 version. Look first at the -mgp options, if given, otherwise base
17491 the choice on MIPS_DEFAULT_64BIT.
17493 Treat NO_ABI like the EABIs. One reason to do this is that the
17494 plain 'mips' and 'mips64' configs have 'from-abi' as their default
17495 architecture. This code picks MIPS I for 'mips' and MIPS III for
17496 'mips64', just as we did in the days before 'from-abi'. */
17497 if (strcasecmp (cpu_string, "from-abi") == 0)
17499 if (ABI_NEEDS_32BIT_REGS (mips_abi))
17500 return mips_cpu_info_from_isa (ISA_MIPS1);
17502 if (ABI_NEEDS_64BIT_REGS (mips_abi))
17503 return mips_cpu_info_from_isa (ISA_MIPS3);
17505 if (file_mips_gp32 >= 0)
17506 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
17508 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
17513 /* 'default' has traditionally been a no-op. Probably not very useful. */
17514 if (strcasecmp (cpu_string, "default") == 0)
17517 for (p = mips_cpu_info_table; p->name != 0; p++)
17518 if (mips_matching_cpu_name_p (p->name, cpu_string))
17521 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
17525 /* Return the canonical processor information for ISA (a member of the
17526 ISA_MIPS* enumeration). */
17528 static const struct mips_cpu_info *
17529 mips_cpu_info_from_isa (int isa)
17533 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
17534 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
17535 && isa == mips_cpu_info_table[i].isa)
17536 return (&mips_cpu_info_table[i]);
17541 static const struct mips_cpu_info *
17542 mips_cpu_info_from_arch (int arch)
17546 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
17547 if (arch == mips_cpu_info_table[i].cpu)
17548 return (&mips_cpu_info_table[i]);
17554 show (FILE *stream, const char *string, int *col_p, int *first_p)
17558 fprintf (stream, "%24s", "");
17563 fprintf (stream, ", ");
17567 if (*col_p + strlen (string) > 72)
17569 fprintf (stream, "\n%24s", "");
17573 fprintf (stream, "%s", string);
17574 *col_p += strlen (string);
17580 md_show_usage (FILE *stream)
17585 fprintf (stream, _("\
17587 -EB generate big endian output\n\
17588 -EL generate little endian output\n\
17589 -g, -g2 do not remove unneeded NOPs or swap branches\n\
17590 -G NUM allow referencing objects up to NUM bytes\n\
17591 implicitly with the gp register [default 8]\n"));
17592 fprintf (stream, _("\
17593 -mips1 generate MIPS ISA I instructions\n\
17594 -mips2 generate MIPS ISA II instructions\n\
17595 -mips3 generate MIPS ISA III instructions\n\
17596 -mips4 generate MIPS ISA IV instructions\n\
17597 -mips5 generate MIPS ISA V instructions\n\
17598 -mips32 generate MIPS32 ISA instructions\n\
17599 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
17600 -mips64 generate MIPS64 ISA instructions\n\
17601 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
17602 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
17606 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
17607 show (stream, mips_cpu_info_table[i].name, &column, &first);
17608 show (stream, "from-abi", &column, &first);
17609 fputc ('\n', stream);
17611 fprintf (stream, _("\
17612 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
17613 -no-mCPU don't generate code specific to CPU.\n\
17614 For -mCPU and -no-mCPU, CPU must be one of:\n"));
17618 show (stream, "3900", &column, &first);
17619 show (stream, "4010", &column, &first);
17620 show (stream, "4100", &column, &first);
17621 show (stream, "4650", &column, &first);
17622 fputc ('\n', stream);
17624 fprintf (stream, _("\
17625 -mips16 generate mips16 instructions\n\
17626 -no-mips16 do not generate mips16 instructions\n"));
17627 fprintf (stream, _("\
17628 -mmicromips generate microMIPS instructions\n\
17629 -mno-micromips do not generate microMIPS instructions\n"));
17630 fprintf (stream, _("\
17631 -msmartmips generate smartmips instructions\n\
17632 -mno-smartmips do not generate smartmips instructions\n"));
17633 fprintf (stream, _("\
17634 -mdsp generate DSP instructions\n\
17635 -mno-dsp do not generate DSP instructions\n"));
17636 fprintf (stream, _("\
17637 -mdspr2 generate DSP R2 instructions\n\
17638 -mno-dspr2 do not generate DSP R2 instructions\n"));
17639 fprintf (stream, _("\
17640 -mmt generate MT instructions\n\
17641 -mno-mt do not generate MT instructions\n"));
17642 fprintf (stream, _("\
17643 -mmcu generate MCU instructions\n\
17644 -mno-mcu do not generate MCU instructions\n"));
17645 fprintf (stream, _("\
17646 -mvirt generate Virtualization instructions\n\
17647 -mno-virt do not generate Virtualization instructions\n"));
17648 fprintf (stream, _("\
17649 -minsn32 only generate 32-bit microMIPS instructions\n\
17650 -mno-insn32 generate all microMIPS instructions\n"));
17651 fprintf (stream, _("\
17652 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
17653 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
17654 -mfix-vr4120 work around certain VR4120 errata\n\
17655 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
17656 -mfix-24k insert a nop after ERET and DERET instructions\n\
17657 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
17658 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
17659 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
17660 -msym32 assume all symbols have 32-bit values\n\
17661 -O0 remove unneeded NOPs, do not swap branches\n\
17662 -O remove unneeded NOPs and swap branches\n\
17663 --trap, --no-break trap exception on div by 0 and mult overflow\n\
17664 --break, --no-trap break exception on div by 0 and mult overflow\n"));
17665 fprintf (stream, _("\
17666 -mhard-float allow floating-point instructions\n\
17667 -msoft-float do not allow floating-point instructions\n\
17668 -msingle-float only allow 32-bit floating-point operations\n\
17669 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
17670 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
17671 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
17672 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
17676 show (stream, "legacy", &column, &first);
17677 show (stream, "2008", &column, &first);
17679 fputc ('\n', stream);
17681 fprintf (stream, _("\
17682 -KPIC, -call_shared generate SVR4 position independent code\n\
17683 -call_nonpic generate non-PIC code that can operate with DSOs\n\
17684 -mvxworks-pic generate VxWorks position independent code\n\
17685 -non_shared do not generate code that can operate with DSOs\n\
17686 -xgot assume a 32 bit GOT\n\
17687 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
17688 -mshared, -mno-shared disable/enable .cpload optimization for\n\
17689 position dependent (non shared) code\n\
17690 -mabi=ABI create ABI conformant object file for:\n"));
17694 show (stream, "32", &column, &first);
17695 show (stream, "o64", &column, &first);
17696 show (stream, "n32", &column, &first);
17697 show (stream, "64", &column, &first);
17698 show (stream, "eabi", &column, &first);
17700 fputc ('\n', stream);
17702 fprintf (stream, _("\
17703 -32 create o32 ABI object file (default)\n\
17704 -n32 create n32 ABI object file\n\
17705 -64 create 64 ABI object file\n"));
17710 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
17712 if (HAVE_64BIT_SYMBOLS)
17713 return dwarf2_format_64bit_irix;
17715 return dwarf2_format_32bit;
17720 mips_dwarf2_addr_size (void)
17722 if (HAVE_64BIT_OBJECTS)
17728 /* Standard calling conventions leave the CFA at SP on entry. */
17730 mips_cfi_frame_initial_instructions (void)
17732 cfi_add_CFA_def_cfa_register (SP);
17736 tc_mips_regname_to_dw2regnum (char *regname)
17738 unsigned int regnum = -1;
17741 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))