1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 #define AT mips_opts.at
107 /* Allow override of standard little-endian ECOFF format. */
109 #ifndef ECOFF_LITTLE_FORMAT
110 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
113 extern int target_big_endian;
115 /* The name of the readonly data section. */
116 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
124 /* Information about an instruction, including its format, operands
128 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
129 const struct mips_opcode *insn_mo;
131 /* True if this is a mips16 instruction and if we want the extended
133 bfd_boolean use_extend;
135 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
136 unsigned short extend;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. */
140 unsigned long insn_opcode;
142 /* The frag that contains the instruction. */
145 /* The offset into FRAG of the first instruction byte. */
148 /* The relocs associated with the instruction, if any. */
151 /* True if this entry cannot be moved from its current position. */
152 unsigned int fixed_p : 1;
154 /* True if this instruction occurred in a .set noreorder block. */
155 unsigned int noreorder_p : 1;
157 /* True for mips16 instructions that jump to an absolute address. */
158 unsigned int mips16_absolute_jump_p : 1;
161 /* The ABI to use. */
172 /* MIPS ABI we are using for this output file. */
173 static enum mips_abi_level mips_abi = NO_ABI;
175 /* Whether or not we have code that can call pic code. */
176 int mips_abicalls = FALSE;
178 /* Whether or not we have code which can be put into a shared
180 static bfd_boolean mips_in_shared = TRUE;
182 /* This is the set of options which may be modified by the .set
183 pseudo-op. We use a struct so that .set push and .set pop are more
186 struct mips_set_options
188 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
189 if it has not been initialized. Changed by `.set mipsN', and the
190 -mipsN command line option, and the default CPU. */
192 /* Enabled Application Specific Extensions (ASEs). These are set to -1
193 if they have not been initialized. Changed by `.set <asename>', by
194 command line options, and based on the default architecture. */
201 /* Whether we are assembling for the mips16 processor. 0 if we are
202 not, 1 if we are, and -1 if the value has not been initialized.
203 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
204 -nomips16 command line options, and the default CPU. */
206 /* Non-zero if we should not reorder instructions. Changed by `.set
207 reorder' and `.set noreorder'. */
209 /* Non-zero if we should not permit the register designated "assembler
210 temporary" to be used in instructions. The value is the register
211 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
212 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
214 /* Non-zero if we should warn when a macro instruction expands into
215 more than one machine instruction. Changed by `.set nomacro' and
217 int warn_about_macros;
218 /* Non-zero if we should not move instructions. Changed by `.set
219 move', `.set volatile', `.set nomove', and `.set novolatile'. */
221 /* Non-zero if we should not optimize branches by moving the target
222 of the branch into the delay slot. Actually, we don't perform
223 this optimization anyhow. Changed by `.set bopt' and `.set
226 /* Non-zero if we should not autoextend mips16 instructions.
227 Changed by `.set autoextend' and `.set noautoextend'. */
229 /* Restrict general purpose registers and floating point registers
230 to 32 bit. This is initially determined when -mgp32 or -mfp32
231 is passed but can changed if the assembler code uses .set mipsN. */
234 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
235 command line option, and the default CPU. */
237 /* True if ".set sym32" is in effect. */
239 /* True if floating-point operations are not allowed. Changed by .set
240 softfloat or .set hardfloat, by command line options -msoft-float or
241 -mhard-float. The default is false. */
242 bfd_boolean soft_float;
244 /* True if only single-precision floating-point operations are allowed.
245 Changed by .set singlefloat or .set doublefloat, command-line options
246 -msingle-float or -mdouble-float. The default is false. */
247 bfd_boolean single_float;
250 /* This is the struct we use to hold the current set of options. Note
251 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
252 -1 to indicate that they have not been initialized. */
254 /* True if -mgp32 was passed. */
255 static int file_mips_gp32 = -1;
257 /* True if -mfp32 was passed. */
258 static int file_mips_fp32 = -1;
260 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
261 static int file_mips_soft_float = 0;
263 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
264 static int file_mips_single_float = 0;
266 static struct mips_set_options mips_opts =
268 /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
269 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
270 /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG,
271 /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
272 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN,
273 /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE
276 /* These variables are filled in with the masks of registers used.
277 The object format code reads them and puts them in the appropriate
279 unsigned long mips_gprmask;
280 unsigned long mips_cprmask[4];
282 /* MIPS ISA we are using for this output file. */
283 static int file_mips_isa = ISA_UNKNOWN;
285 /* True if -mips16 was passed or implied by arguments passed on the
286 command line (e.g., by -march). */
287 static int file_ase_mips16;
289 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
290 || mips_opts.isa == ISA_MIPS32R2 \
291 || mips_opts.isa == ISA_MIPS64 \
292 || mips_opts.isa == ISA_MIPS64R2)
294 /* True if we want to create R_MIPS_JALR for jalr $25. */
296 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
298 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
299 because there's no place for any addend, the only acceptable
300 expression is a bare symbol. */
301 #define MIPS_JALR_HINT_P(EXPR) \
302 (!HAVE_IN_PLACE_ADDENDS \
303 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
306 /* True if -mips3d was passed or implied by arguments passed on the
307 command line (e.g., by -march). */
308 static int file_ase_mips3d;
310 /* True if -mdmx was passed or implied by arguments passed on the
311 command line (e.g., by -march). */
312 static int file_ase_mdmx;
314 /* True if -msmartmips was passed or implied by arguments passed on the
315 command line (e.g., by -march). */
316 static int file_ase_smartmips;
318 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
319 || mips_opts.isa == ISA_MIPS32R2)
321 /* True if -mdsp was passed or implied by arguments passed on the
322 command line (e.g., by -march). */
323 static int file_ase_dsp;
325 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
326 || mips_opts.isa == ISA_MIPS64R2)
328 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
330 /* True if -mdspr2 was passed or implied by arguments passed on the
331 command line (e.g., by -march). */
332 static int file_ase_dspr2;
334 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
335 || mips_opts.isa == ISA_MIPS64R2)
337 /* True if -mmt was passed or implied by arguments passed on the
338 command line (e.g., by -march). */
339 static int file_ase_mt;
341 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
342 || mips_opts.isa == ISA_MIPS64R2)
344 /* The argument of the -march= flag. The architecture we are assembling. */
345 static int file_mips_arch = CPU_UNKNOWN;
346 static const char *mips_arch_string;
348 /* The argument of the -mtune= flag. The architecture for which we
350 static int mips_tune = CPU_UNKNOWN;
351 static const char *mips_tune_string;
353 /* True when generating 32-bit code for a 64-bit processor. */
354 static int mips_32bitmode = 0;
356 /* True if the given ABI requires 32-bit registers. */
357 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
359 /* Likewise 64-bit registers. */
360 #define ABI_NEEDS_64BIT_REGS(ABI) \
362 || (ABI) == N64_ABI \
365 /* Return true if ISA supports 64 bit wide gp registers. */
366 #define ISA_HAS_64BIT_REGS(ISA) \
367 ((ISA) == ISA_MIPS3 \
368 || (ISA) == ISA_MIPS4 \
369 || (ISA) == ISA_MIPS5 \
370 || (ISA) == ISA_MIPS64 \
371 || (ISA) == ISA_MIPS64R2)
373 /* Return true if ISA supports 64 bit wide float registers. */
374 #define ISA_HAS_64BIT_FPRS(ISA) \
375 ((ISA) == ISA_MIPS3 \
376 || (ISA) == ISA_MIPS4 \
377 || (ISA) == ISA_MIPS5 \
378 || (ISA) == ISA_MIPS32R2 \
379 || (ISA) == ISA_MIPS64 \
380 || (ISA) == ISA_MIPS64R2)
382 /* Return true if ISA supports 64-bit right rotate (dror et al.)
384 #define ISA_HAS_DROR(ISA) \
385 ((ISA) == ISA_MIPS64R2)
387 /* Return true if ISA supports 32-bit right rotate (ror et al.)
389 #define ISA_HAS_ROR(ISA) \
390 ((ISA) == ISA_MIPS32R2 \
391 || (ISA) == ISA_MIPS64R2 \
392 || mips_opts.ase_smartmips)
394 /* Return true if ISA supports single-precision floats in odd registers. */
395 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
396 ((ISA) == ISA_MIPS32 \
397 || (ISA) == ISA_MIPS32R2 \
398 || (ISA) == ISA_MIPS64 \
399 || (ISA) == ISA_MIPS64R2)
401 /* Return true if ISA supports move to/from high part of a 64-bit
402 floating-point register. */
403 #define ISA_HAS_MXHC1(ISA) \
404 ((ISA) == ISA_MIPS32R2 \
405 || (ISA) == ISA_MIPS64R2)
407 #define HAVE_32BIT_GPRS \
408 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
410 #define HAVE_32BIT_FPRS \
411 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
413 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
414 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
416 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
418 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
420 /* True if relocations are stored in-place. */
421 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
423 /* The ABI-derived address size. */
424 #define HAVE_64BIT_ADDRESSES \
425 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
426 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
428 /* The size of symbolic constants (i.e., expressions of the form
429 "SYMBOL" or "SYMBOL + OFFSET"). */
430 #define HAVE_32BIT_SYMBOLS \
431 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
432 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
434 /* Addresses are loaded in different ways, depending on the address size
435 in use. The n32 ABI Documentation also mandates the use of additions
436 with overflow checking, but existing implementations don't follow it. */
437 #define ADDRESS_ADD_INSN \
438 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
440 #define ADDRESS_ADDI_INSN \
441 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
443 #define ADDRESS_LOAD_INSN \
444 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
446 #define ADDRESS_STORE_INSN \
447 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
449 /* Return true if the given CPU supports the MIPS16 ASE. */
450 #define CPU_HAS_MIPS16(cpu) \
451 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
452 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
454 /* True if CPU has a dror instruction. */
455 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
457 /* True if CPU has a ror instruction. */
458 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
460 /* True if CPU has seq/sne and seqi/snei instructions. */
461 #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON)
463 /* True if CPU does not implement the all the coprocessor insns. For these
464 CPUs only those COP insns are accepted that are explicitly marked to be
465 available on the CPU. ISA membership for COP insns is ignored. */
466 #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON)
468 /* True if mflo and mfhi can be immediately followed by instructions
469 which write to the HI and LO registers.
471 According to MIPS specifications, MIPS ISAs I, II, and III need
472 (at least) two instructions between the reads of HI/LO and
473 instructions which write them, and later ISAs do not. Contradicting
474 the MIPS specifications, some MIPS IV processor user manuals (e.g.
475 the UM for the NEC Vr5000) document needing the instructions between
476 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
477 MIPS64 and later ISAs to have the interlocks, plus any specific
478 earlier-ISA CPUs for which CPU documentation declares that the
479 instructions are really interlocked. */
480 #define hilo_interlocks \
481 (mips_opts.isa == ISA_MIPS32 \
482 || mips_opts.isa == ISA_MIPS32R2 \
483 || mips_opts.isa == ISA_MIPS64 \
484 || mips_opts.isa == ISA_MIPS64R2 \
485 || mips_opts.arch == CPU_R4010 \
486 || mips_opts.arch == CPU_R10000 \
487 || mips_opts.arch == CPU_R12000 \
488 || mips_opts.arch == CPU_R14000 \
489 || mips_opts.arch == CPU_R16000 \
490 || mips_opts.arch == CPU_RM7000 \
491 || mips_opts.arch == CPU_VR5500 \
494 /* Whether the processor uses hardware interlocks to protect reads
495 from the GPRs after they are loaded from memory, and thus does not
496 require nops to be inserted. This applies to instructions marked
497 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
499 #define gpr_interlocks \
500 (mips_opts.isa != ISA_MIPS1 \
501 || mips_opts.arch == CPU_R3900)
503 /* Whether the processor uses hardware interlocks to avoid delays
504 required by coprocessor instructions, and thus does not require
505 nops to be inserted. This applies to instructions marked
506 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
507 between instructions marked INSN_WRITE_COND_CODE and ones marked
508 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
509 levels I, II, and III. */
510 /* Itbl support may require additional care here. */
511 #define cop_interlocks \
512 ((mips_opts.isa != ISA_MIPS1 \
513 && mips_opts.isa != ISA_MIPS2 \
514 && mips_opts.isa != ISA_MIPS3) \
515 || mips_opts.arch == CPU_R4300 \
518 /* Whether the processor uses hardware interlocks to protect reads
519 from coprocessor registers after they are loaded from memory, and
520 thus does not require nops to be inserted. This applies to
521 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
522 requires at MIPS ISA level I. */
523 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
525 /* Is this a mfhi or mflo instruction? */
526 #define MF_HILO_INSN(PINFO) \
527 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
529 /* Returns true for a (non floating-point) coprocessor instruction. Reading
530 or writing the condition code is only possible on the coprocessors and
531 these insns are not marked with INSN_COP. Thus for these insns use the
532 condition-code flags. */
533 #define COP_INSN(PINFO) \
534 (PINFO != INSN_MACRO \
535 && ((PINFO) & (FP_S | FP_D)) == 0 \
536 && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
538 /* MIPS PIC level. */
540 enum mips_pic_level mips_pic;
542 /* 1 if we should generate 32 bit offsets from the $gp register in
543 SVR4_PIC mode. Currently has no meaning in other modes. */
544 static int mips_big_got = 0;
546 /* 1 if trap instructions should used for overflow rather than break
548 static int mips_trap = 0;
550 /* 1 if double width floating point constants should not be constructed
551 by assembling two single width halves into two single width floating
552 point registers which just happen to alias the double width destination
553 register. On some architectures this aliasing can be disabled by a bit
554 in the status register, and the setting of this bit cannot be determined
555 automatically at assemble time. */
556 static int mips_disable_float_construction;
558 /* Non-zero if any .set noreorder directives were used. */
560 static int mips_any_noreorder;
562 /* Non-zero if nops should be inserted when the register referenced in
563 an mfhi/mflo instruction is read in the next two instructions. */
564 static int mips_7000_hilo_fix;
566 /* The size of objects in the small data section. */
567 static unsigned int g_switch_value = 8;
568 /* Whether the -G option was used. */
569 static int g_switch_seen = 0;
574 /* If we can determine in advance that GP optimization won't be
575 possible, we can skip the relaxation stuff that tries to produce
576 GP-relative references. This makes delay slot optimization work
579 This function can only provide a guess, but it seems to work for
580 gcc output. It needs to guess right for gcc, otherwise gcc
581 will put what it thinks is a GP-relative instruction in a branch
584 I don't know if a fix is needed for the SVR4_PIC mode. I've only
585 fixed it for the non-PIC mode. KR 95/04/07 */
586 static int nopic_need_relax (symbolS *, int);
588 /* handle of the OPCODE hash table */
589 static struct hash_control *op_hash = NULL;
591 /* The opcode hash table we use for the mips16. */
592 static struct hash_control *mips16_op_hash = NULL;
594 /* This array holds the chars that always start a comment. If the
595 pre-processor is disabled, these aren't very useful */
596 const char comment_chars[] = "#";
598 /* This array holds the chars that only start a comment at the beginning of
599 a line. If the line seems to have the form '# 123 filename'
600 .line and .file directives will appear in the pre-processed output */
601 /* Note that input_file.c hand checks for '#' at the beginning of the
602 first line of the input file. This is because the compiler outputs
603 #NO_APP at the beginning of its output. */
604 /* Also note that C style comments are always supported. */
605 const char line_comment_chars[] = "#";
607 /* This array holds machine specific line separator characters. */
608 const char line_separator_chars[] = ";";
610 /* Chars that can be used to separate mant from exp in floating point nums */
611 const char EXP_CHARS[] = "eE";
613 /* Chars that mean this number is a floating point constant */
616 const char FLT_CHARS[] = "rRsSfFdDxXpP";
618 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
619 changed in read.c . Ideally it shouldn't have to know about it at all,
620 but nothing is ideal around here.
623 static char *insn_error;
625 static int auto_align = 1;
627 /* When outputting SVR4 PIC code, the assembler needs to know the
628 offset in the stack frame from which to restore the $gp register.
629 This is set by the .cprestore pseudo-op, and saved in this
631 static offsetT mips_cprestore_offset = -1;
633 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
634 more optimizations, it can use a register value instead of a memory-saved
635 offset and even an other register than $gp as global pointer. */
636 static offsetT mips_cpreturn_offset = -1;
637 static int mips_cpreturn_register = -1;
638 static int mips_gp_register = GP;
639 static int mips_gprel_offset = 0;
641 /* Whether mips_cprestore_offset has been set in the current function
642 (or whether it has already been warned about, if not). */
643 static int mips_cprestore_valid = 0;
645 /* This is the register which holds the stack frame, as set by the
646 .frame pseudo-op. This is needed to implement .cprestore. */
647 static int mips_frame_reg = SP;
649 /* Whether mips_frame_reg has been set in the current function
650 (or whether it has already been warned about, if not). */
651 static int mips_frame_reg_valid = 0;
653 /* To output NOP instructions correctly, we need to keep information
654 about the previous two instructions. */
656 /* Whether we are optimizing. The default value of 2 means to remove
657 unneeded NOPs and swap branch instructions when possible. A value
658 of 1 means to not swap branches. A value of 0 means to always
660 static int mips_optimize = 2;
662 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
663 equivalent to seeing no -g option at all. */
664 static int mips_debug = 0;
666 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
667 #define MAX_VR4130_NOPS 4
669 /* The maximum number of NOPs needed to fill delay slots. */
670 #define MAX_DELAY_NOPS 2
672 /* The maximum number of NOPs needed for any purpose. */
675 /* A list of previous instructions, with index 0 being the most recent.
676 We need to look back MAX_NOPS instructions when filling delay slots
677 or working around processor errata. We need to look back one
678 instruction further if we're thinking about using history[0] to
679 fill a branch delay slot. */
680 static struct mips_cl_insn history[1 + MAX_NOPS];
682 /* Nop instructions used by emit_nop. */
683 static struct mips_cl_insn nop_insn, mips16_nop_insn;
685 /* The appropriate nop for the current mode. */
686 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
688 /* If this is set, it points to a frag holding nop instructions which
689 were inserted before the start of a noreorder section. If those
690 nops turn out to be unnecessary, the size of the frag can be
692 static fragS *prev_nop_frag;
694 /* The number of nop instructions we created in prev_nop_frag. */
695 static int prev_nop_frag_holds;
697 /* The number of nop instructions that we know we need in
699 static int prev_nop_frag_required;
701 /* The number of instructions we've seen since prev_nop_frag. */
702 static int prev_nop_frag_since;
704 /* For ECOFF and ELF, relocations against symbols are done in two
705 parts, with a HI relocation and a LO relocation. Each relocation
706 has only 16 bits of space to store an addend. This means that in
707 order for the linker to handle carries correctly, it must be able
708 to locate both the HI and the LO relocation. This means that the
709 relocations must appear in order in the relocation table.
711 In order to implement this, we keep track of each unmatched HI
712 relocation. We then sort them so that they immediately precede the
713 corresponding LO relocation. */
718 struct mips_hi_fixup *next;
721 /* The section this fixup is in. */
725 /* The list of unmatched HI relocs. */
727 static struct mips_hi_fixup *mips_hi_fixup_list;
729 /* The frag containing the last explicit relocation operator.
730 Null if explicit relocations have not been used. */
732 static fragS *prev_reloc_op_frag;
734 /* Map normal MIPS register numbers to mips16 register numbers. */
736 #define X ILLEGAL_REG
737 static const int mips32_to_16_reg_map[] =
739 X, X, 2, 3, 4, 5, 6, 7,
740 X, X, X, X, X, X, X, X,
741 0, 1, X, X, X, X, X, X,
742 X, X, X, X, X, X, X, X
746 /* Map mips16 register numbers to normal MIPS register numbers. */
748 static const unsigned int mips16_to_32_reg_map[] =
750 16, 17, 2, 3, 4, 5, 6, 7
753 /* Classifies the kind of instructions we're interested in when
754 implementing -mfix-vr4120. */
755 enum fix_vr4120_class
763 NUM_FIX_VR4120_CLASSES
766 /* ...likewise -mfix-loongson2f-jump. */
767 static bfd_boolean mips_fix_loongson2f_jump;
769 /* ...likewise -mfix-loongson2f-nop. */
770 static bfd_boolean mips_fix_loongson2f_nop;
772 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
773 static bfd_boolean mips_fix_loongson2f;
775 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
776 there must be at least one other instruction between an instruction
777 of type X and an instruction of type Y. */
778 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
780 /* True if -mfix-vr4120 is in force. */
781 static int mips_fix_vr4120;
783 /* ...likewise -mfix-vr4130. */
784 static int mips_fix_vr4130;
786 /* ...likewise -mfix-24k. */
787 static int mips_fix_24k;
789 /* ...likewise -mfix-cn63xxp1 */
790 static bfd_boolean mips_fix_cn63xxp1;
792 /* We don't relax branches by default, since this causes us to expand
793 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
794 fail to compute the offset before expanding the macro to the most
795 efficient expansion. */
797 static int mips_relax_branch;
799 /* The expansion of many macros depends on the type of symbol that
800 they refer to. For example, when generating position-dependent code,
801 a macro that refers to a symbol may have two different expansions,
802 one which uses GP-relative addresses and one which uses absolute
803 addresses. When generating SVR4-style PIC, a macro may have
804 different expansions for local and global symbols.
806 We handle these situations by generating both sequences and putting
807 them in variant frags. In position-dependent code, the first sequence
808 will be the GP-relative one and the second sequence will be the
809 absolute one. In SVR4 PIC, the first sequence will be for global
810 symbols and the second will be for local symbols.
812 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
813 SECOND are the lengths of the two sequences in bytes. These fields
814 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
815 the subtype has the following flags:
818 Set if it has been decided that we should use the second
819 sequence instead of the first.
822 Set in the first variant frag if the macro's second implementation
823 is longer than its first. This refers to the macro as a whole,
824 not an individual relaxation.
827 Set in the first variant frag if the macro appeared in a .set nomacro
828 block and if one alternative requires a warning but the other does not.
831 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
834 The frag's "opcode" points to the first fixup for relaxable code.
836 Relaxable macros are generated using a sequence such as:
838 relax_start (SYMBOL);
839 ... generate first expansion ...
841 ... generate second expansion ...
844 The code and fixups for the unwanted alternative are discarded
845 by md_convert_frag. */
846 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
848 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
849 #define RELAX_SECOND(X) ((X) & 0xff)
850 #define RELAX_USE_SECOND 0x10000
851 #define RELAX_SECOND_LONGER 0x20000
852 #define RELAX_NOMACRO 0x40000
853 #define RELAX_DELAY_SLOT 0x80000
855 /* Branch without likely bit. If label is out of range, we turn:
857 beq reg1, reg2, label
867 with the following opcode replacements:
874 bltzal <-> bgezal (with jal label instead of j label)
876 Even though keeping the delay slot instruction in the delay slot of
877 the branch would be more efficient, it would be very tricky to do
878 correctly, because we'd have to introduce a variable frag *after*
879 the delay slot instruction, and expand that instead. Let's do it
880 the easy way for now, even if the branch-not-taken case now costs
881 one additional instruction. Out-of-range branches are not supposed
882 to be common, anyway.
884 Branch likely. If label is out of range, we turn:
886 beql reg1, reg2, label
887 delay slot (annulled if branch not taken)
896 delay slot (executed only if branch taken)
899 It would be possible to generate a shorter sequence by losing the
900 likely bit, generating something like:
905 delay slot (executed only if branch taken)
917 bltzall -> bgezal (with jal label instead of j label)
918 bgezall -> bltzal (ditto)
921 but it's not clear that it would actually improve performance. */
922 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
925 | ((toofar) ? 1 : 0) \
927 | ((likely) ? 4 : 0) \
928 | ((uncond) ? 8 : 0)))
929 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
930 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
931 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
932 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
933 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
935 /* For mips16 code, we use an entirely different form of relaxation.
936 mips16 supports two versions of most instructions which take
937 immediate values: a small one which takes some small value, and a
938 larger one which takes a 16 bit value. Since branches also follow
939 this pattern, relaxing these values is required.
941 We can assemble both mips16 and normal MIPS code in a single
942 object. Therefore, we need to support this type of relaxation at
943 the same time that we support the relaxation described above. We
944 use the high bit of the subtype field to distinguish these cases.
946 The information we store for this type of relaxation is the
947 argument code found in the opcode file for this relocation, whether
948 the user explicitly requested a small or extended form, and whether
949 the relocation is in a jump or jal delay slot. That tells us the
950 size of the value, and how it should be stored. We also store
951 whether the fragment is considered to be extended or not. We also
952 store whether this is known to be a branch to a different section,
953 whether we have tried to relax this frag yet, and whether we have
954 ever extended a PC relative fragment because of a shift count. */
955 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
958 | ((small) ? 0x100 : 0) \
959 | ((ext) ? 0x200 : 0) \
960 | ((dslot) ? 0x400 : 0) \
961 | ((jal_dslot) ? 0x800 : 0))
962 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
963 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
964 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
965 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
966 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
967 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
968 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
969 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
970 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
971 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
972 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
973 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
975 /* Is the given value a sign-extended 32-bit value? */
976 #define IS_SEXT_32BIT_NUM(x) \
977 (((x) &~ (offsetT) 0x7fffffff) == 0 \
978 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
980 /* Is the given value a sign-extended 16-bit value? */
981 #define IS_SEXT_16BIT_NUM(x) \
982 (((x) &~ (offsetT) 0x7fff) == 0 \
983 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
985 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
986 #define IS_ZEXT_32BIT_NUM(x) \
987 (((x) &~ (offsetT) 0xffffffff) == 0 \
988 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
990 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
991 VALUE << SHIFT. VALUE is evaluated exactly once. */
992 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
993 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
994 | (((VALUE) & (MASK)) << (SHIFT)))
996 /* Extract bits MASK << SHIFT from STRUCT and shift them right
998 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
999 (((STRUCT) >> (SHIFT)) & (MASK))
1001 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1002 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1004 include/opcode/mips.h specifies operand fields using the macros
1005 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1006 with "MIPS16OP" instead of "OP". */
1007 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
1008 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
1009 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1010 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1011 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1013 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1014 #define EXTRACT_OPERAND(FIELD, INSN) \
1015 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
1016 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1017 EXTRACT_BITS ((INSN).insn_opcode, \
1018 MIPS16OP_MASK_##FIELD, \
1019 MIPS16OP_SH_##FIELD)
1021 /* Global variables used when generating relaxable macros. See the
1022 comment above RELAX_ENCODE for more details about how relaxation
1025 /* 0 if we're not emitting a relaxable macro.
1026 1 if we're emitting the first of the two relaxation alternatives.
1027 2 if we're emitting the second alternative. */
1030 /* The first relaxable fixup in the current frag. (In other words,
1031 the first fixup that refers to relaxable code.) */
1034 /* sizes[0] says how many bytes of the first alternative are stored in
1035 the current frag. Likewise sizes[1] for the second alternative. */
1036 unsigned int sizes[2];
1038 /* The symbol on which the choice of sequence depends. */
1042 /* Global variables used to decide whether a macro needs a warning. */
1044 /* True if the macro is in a branch delay slot. */
1045 bfd_boolean delay_slot_p;
1047 /* For relaxable macros, sizes[0] is the length of the first alternative
1048 in bytes and sizes[1] is the length of the second alternative.
1049 For non-relaxable macros, both elements give the length of the
1051 unsigned int sizes[2];
1053 /* The first variant frag for this macro. */
1055 } mips_macro_warning;
1057 /* Prototypes for static functions. */
1059 #define internalError() \
1060 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1062 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1064 static void append_insn
1065 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *);
1066 static void mips_no_prev_insn (void);
1067 static void macro_build (expressionS *, const char *, const char *, ...);
1068 static void mips16_macro_build
1069 (expressionS *, const char *, const char *, va_list *);
1070 static void load_register (int, expressionS *, int);
1071 static void macro_start (void);
1072 static void macro_end (void);
1073 static void macro (struct mips_cl_insn * ip);
1074 static void mips16_macro (struct mips_cl_insn * ip);
1075 static void mips_ip (char *str, struct mips_cl_insn * ip);
1076 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1077 static void mips16_immed
1078 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
1079 unsigned long *, bfd_boolean *, unsigned short *);
1080 static size_t my_getSmallExpression
1081 (expressionS *, bfd_reloc_code_real_type *, char *);
1082 static void my_getExpression (expressionS *, char *);
1083 static void s_align (int);
1084 static void s_change_sec (int);
1085 static void s_change_section (int);
1086 static void s_cons (int);
1087 static void s_float_cons (int);
1088 static void s_mips_globl (int);
1089 static void s_option (int);
1090 static void s_mipsset (int);
1091 static void s_abicalls (int);
1092 static void s_cpload (int);
1093 static void s_cpsetup (int);
1094 static void s_cplocal (int);
1095 static void s_cprestore (int);
1096 static void s_cpreturn (int);
1097 static void s_dtprelword (int);
1098 static void s_dtpreldword (int);
1099 static void s_gpvalue (int);
1100 static void s_gpword (int);
1101 static void s_gpdword (int);
1102 static void s_cpadd (int);
1103 static void s_insn (int);
1104 static void md_obj_begin (void);
1105 static void md_obj_end (void);
1106 static void s_mips_ent (int);
1107 static void s_mips_end (int);
1108 static void s_mips_frame (int);
1109 static void s_mips_mask (int reg_type);
1110 static void s_mips_stab (int);
1111 static void s_mips_weakext (int);
1112 static void s_mips_file (int);
1113 static void s_mips_loc (int);
1114 static bfd_boolean pic_need_relax (symbolS *, asection *);
1115 static int relaxed_branch_length (fragS *, asection *, int);
1116 static int validate_mips_insn (const struct mips_opcode *);
1118 /* Table and functions used to map between CPU/ISA names, and
1119 ISA levels, and CPU numbers. */
1121 struct mips_cpu_info
1123 const char *name; /* CPU or ISA name. */
1124 int flags; /* ASEs available, or ISA flag. */
1125 int isa; /* ISA level. */
1126 int cpu; /* CPU number (default CPU if ISA). */
1129 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1130 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1131 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1132 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1133 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1134 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1135 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1137 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1138 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1139 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1143 The following pseudo-ops from the Kane and Heinrich MIPS book
1144 should be defined here, but are currently unsupported: .alias,
1145 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1147 The following pseudo-ops from the Kane and Heinrich MIPS book are
1148 specific to the type of debugging information being generated, and
1149 should be defined by the object format: .aent, .begin, .bend,
1150 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1153 The following pseudo-ops from the Kane and Heinrich MIPS book are
1154 not MIPS CPU specific, but are also not specific to the object file
1155 format. This file is probably the best place to define them, but
1156 they are not currently supported: .asm0, .endr, .lab, .struct. */
1158 static const pseudo_typeS mips_pseudo_table[] =
1160 /* MIPS specific pseudo-ops. */
1161 {"option", s_option, 0},
1162 {"set", s_mipsset, 0},
1163 {"rdata", s_change_sec, 'r'},
1164 {"sdata", s_change_sec, 's'},
1165 {"livereg", s_ignore, 0},
1166 {"abicalls", s_abicalls, 0},
1167 {"cpload", s_cpload, 0},
1168 {"cpsetup", s_cpsetup, 0},
1169 {"cplocal", s_cplocal, 0},
1170 {"cprestore", s_cprestore, 0},
1171 {"cpreturn", s_cpreturn, 0},
1172 {"dtprelword", s_dtprelword, 0},
1173 {"dtpreldword", s_dtpreldword, 0},
1174 {"gpvalue", s_gpvalue, 0},
1175 {"gpword", s_gpword, 0},
1176 {"gpdword", s_gpdword, 0},
1177 {"cpadd", s_cpadd, 0},
1178 {"insn", s_insn, 0},
1180 /* Relatively generic pseudo-ops that happen to be used on MIPS
1182 {"asciiz", stringer, 8 + 1},
1183 {"bss", s_change_sec, 'b'},
1185 {"half", s_cons, 1},
1186 {"dword", s_cons, 3},
1187 {"weakext", s_mips_weakext, 0},
1188 {"origin", s_org, 0},
1189 {"repeat", s_rept, 0},
1191 /* For MIPS this is non-standard, but we define it for consistency. */
1192 {"sbss", s_change_sec, 'B'},
1194 /* These pseudo-ops are defined in read.c, but must be overridden
1195 here for one reason or another. */
1196 {"align", s_align, 0},
1197 {"byte", s_cons, 0},
1198 {"data", s_change_sec, 'd'},
1199 {"double", s_float_cons, 'd'},
1200 {"float", s_float_cons, 'f'},
1201 {"globl", s_mips_globl, 0},
1202 {"global", s_mips_globl, 0},
1203 {"hword", s_cons, 1},
1205 {"long", s_cons, 2},
1206 {"octa", s_cons, 4},
1207 {"quad", s_cons, 3},
1208 {"section", s_change_section, 0},
1209 {"short", s_cons, 1},
1210 {"single", s_float_cons, 'f'},
1211 {"stabn", s_mips_stab, 'n'},
1212 {"text", s_change_sec, 't'},
1213 {"word", s_cons, 2},
1215 { "extern", ecoff_directive_extern, 0},
1220 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1222 /* These pseudo-ops should be defined by the object file format.
1223 However, a.out doesn't support them, so we have versions here. */
1224 {"aent", s_mips_ent, 1},
1225 {"bgnb", s_ignore, 0},
1226 {"end", s_mips_end, 0},
1227 {"endb", s_ignore, 0},
1228 {"ent", s_mips_ent, 0},
1229 {"file", s_mips_file, 0},
1230 {"fmask", s_mips_mask, 'F'},
1231 {"frame", s_mips_frame, 0},
1232 {"loc", s_mips_loc, 0},
1233 {"mask", s_mips_mask, 'R'},
1234 {"verstamp", s_ignore, 0},
1238 extern void pop_insert (const pseudo_typeS *);
1241 mips_pop_insert (void)
1243 pop_insert (mips_pseudo_table);
1244 if (! ECOFF_DEBUGGING)
1245 pop_insert (mips_nonecoff_pseudo_table);
1248 /* Symbols labelling the current insn. */
1250 struct insn_label_list
1252 struct insn_label_list *next;
1256 static struct insn_label_list *free_insn_labels;
1257 #define label_list tc_segment_info_data.labels
1259 static void mips_clear_insn_labels (void);
1262 mips_clear_insn_labels (void)
1264 register struct insn_label_list **pl;
1265 segment_info_type *si;
1269 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1272 si = seg_info (now_seg);
1273 *pl = si->label_list;
1274 si->label_list = NULL;
1279 static char *expr_end;
1281 /* Expressions which appear in instructions. These are set by
1284 static expressionS imm_expr;
1285 static expressionS imm2_expr;
1286 static expressionS offset_expr;
1288 /* Relocs associated with imm_expr and offset_expr. */
1290 static bfd_reloc_code_real_type imm_reloc[3]
1291 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1292 static bfd_reloc_code_real_type offset_reloc[3]
1293 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1295 /* These are set by mips16_ip if an explicit extension is used. */
1297 static bfd_boolean mips16_small, mips16_ext;
1300 /* The pdr segment for per procedure frame/regmask info. Not used for
1303 static segT pdr_seg;
1306 /* The default target format to use. */
1309 mips_target_format (void)
1311 switch (OUTPUT_FLAVOR)
1313 case bfd_target_ecoff_flavour:
1314 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1315 case bfd_target_coff_flavour:
1317 case bfd_target_elf_flavour:
1319 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1320 return (target_big_endian
1321 ? "elf32-bigmips-vxworks"
1322 : "elf32-littlemips-vxworks");
1325 /* This is traditional mips. */
1326 return (target_big_endian
1327 ? (HAVE_64BIT_OBJECTS
1328 ? "elf64-tradbigmips"
1330 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1331 : (HAVE_64BIT_OBJECTS
1332 ? "elf64-tradlittlemips"
1334 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1336 return (target_big_endian
1337 ? (HAVE_64BIT_OBJECTS
1340 ? "elf32-nbigmips" : "elf32-bigmips"))
1341 : (HAVE_64BIT_OBJECTS
1342 ? "elf64-littlemips"
1344 ? "elf32-nlittlemips" : "elf32-littlemips")));
1352 /* Return the length of instruction INSN. */
1354 static inline unsigned int
1355 insn_length (const struct mips_cl_insn *insn)
1357 if (!mips_opts.mips16)
1359 return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2;
1362 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1365 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1370 insn->use_extend = FALSE;
1372 insn->insn_opcode = mo->match;
1375 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1376 insn->fixp[i] = NULL;
1377 insn->fixed_p = (mips_opts.noreorder > 0);
1378 insn->noreorder_p = (mips_opts.noreorder > 0);
1379 insn->mips16_absolute_jump_p = 0;
1382 /* Record the current MIPS16 mode in now_seg. */
1385 mips_record_mips16_mode (void)
1387 segment_info_type *si;
1389 si = seg_info (now_seg);
1390 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
1391 si->tc_segment_info_data.mips16 = mips_opts.mips16;
1394 /* Install INSN at the location specified by its "frag" and "where" fields. */
1397 install_insn (const struct mips_cl_insn *insn)
1399 char *f = insn->frag->fr_literal + insn->where;
1400 if (!mips_opts.mips16)
1401 md_number_to_chars (f, insn->insn_opcode, 4);
1402 else if (insn->mips16_absolute_jump_p)
1404 md_number_to_chars (f, insn->insn_opcode >> 16, 2);
1405 md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2);
1409 if (insn->use_extend)
1411 md_number_to_chars (f, 0xf000 | insn->extend, 2);
1414 md_number_to_chars (f, insn->insn_opcode, 2);
1416 mips_record_mips16_mode ();
1419 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1420 and install the opcode in the new location. */
1423 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
1428 insn->where = where;
1429 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1430 if (insn->fixp[i] != NULL)
1432 insn->fixp[i]->fx_frag = frag;
1433 insn->fixp[i]->fx_where = where;
1435 install_insn (insn);
1438 /* Add INSN to the end of the output. */
1441 add_fixed_insn (struct mips_cl_insn *insn)
1443 char *f = frag_more (insn_length (insn));
1444 move_insn (insn, frag_now, f - frag_now->fr_literal);
1447 /* Start a variant frag and move INSN to the start of the variant part,
1448 marking it as fixed. The other arguments are as for frag_var. */
1451 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
1452 relax_substateT subtype, symbolS *symbol, offsetT offset)
1454 frag_grow (max_chars);
1455 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
1457 frag_var (rs_machine_dependent, max_chars, var,
1458 subtype, symbol, offset, NULL);
1461 /* Insert N copies of INSN into the history buffer, starting at
1462 position FIRST. Neither FIRST nor N need to be clipped. */
1465 insert_into_history (unsigned int first, unsigned int n,
1466 const struct mips_cl_insn *insn)
1468 if (mips_relax.sequence != 2)
1472 for (i = ARRAY_SIZE (history); i-- > first;)
1474 history[i] = history[i - n];
1480 /* Emit a nop instruction, recording it in the history buffer. */
1485 add_fixed_insn (NOP_INSN);
1486 insert_into_history (0, 1, NOP_INSN);
1489 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1490 the idea is to make it obvious at a glance that each errata is
1494 init_vr4120_conflicts (void)
1496 #define CONFLICT(FIRST, SECOND) \
1497 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1499 /* Errata 21 - [D]DIV[U] after [D]MACC */
1500 CONFLICT (MACC, DIV);
1501 CONFLICT (DMACC, DIV);
1503 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1504 CONFLICT (DMULT, DMULT);
1505 CONFLICT (DMULT, DMACC);
1506 CONFLICT (DMACC, DMULT);
1507 CONFLICT (DMACC, DMACC);
1509 /* Errata 24 - MT{LO,HI} after [D]MACC */
1510 CONFLICT (MACC, MTHILO);
1511 CONFLICT (DMACC, MTHILO);
1513 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1514 instruction is executed immediately after a MACC or DMACC
1515 instruction, the result of [either instruction] is incorrect." */
1516 CONFLICT (MACC, MULT);
1517 CONFLICT (MACC, DMULT);
1518 CONFLICT (DMACC, MULT);
1519 CONFLICT (DMACC, DMULT);
1521 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1522 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1523 DDIV or DDIVU instruction, the result of the MACC or
1524 DMACC instruction is incorrect.". */
1525 CONFLICT (DMULT, MACC);
1526 CONFLICT (DMULT, DMACC);
1527 CONFLICT (DIV, MACC);
1528 CONFLICT (DIV, DMACC);
1538 #define RTYPE_MASK 0x1ff00
1539 #define RTYPE_NUM 0x00100
1540 #define RTYPE_FPU 0x00200
1541 #define RTYPE_FCC 0x00400
1542 #define RTYPE_VEC 0x00800
1543 #define RTYPE_GP 0x01000
1544 #define RTYPE_CP0 0x02000
1545 #define RTYPE_PC 0x04000
1546 #define RTYPE_ACC 0x08000
1547 #define RTYPE_CCC 0x10000
1548 #define RNUM_MASK 0x000ff
1549 #define RWARN 0x80000
1551 #define GENERIC_REGISTER_NUMBERS \
1552 {"$0", RTYPE_NUM | 0}, \
1553 {"$1", RTYPE_NUM | 1}, \
1554 {"$2", RTYPE_NUM | 2}, \
1555 {"$3", RTYPE_NUM | 3}, \
1556 {"$4", RTYPE_NUM | 4}, \
1557 {"$5", RTYPE_NUM | 5}, \
1558 {"$6", RTYPE_NUM | 6}, \
1559 {"$7", RTYPE_NUM | 7}, \
1560 {"$8", RTYPE_NUM | 8}, \
1561 {"$9", RTYPE_NUM | 9}, \
1562 {"$10", RTYPE_NUM | 10}, \
1563 {"$11", RTYPE_NUM | 11}, \
1564 {"$12", RTYPE_NUM | 12}, \
1565 {"$13", RTYPE_NUM | 13}, \
1566 {"$14", RTYPE_NUM | 14}, \
1567 {"$15", RTYPE_NUM | 15}, \
1568 {"$16", RTYPE_NUM | 16}, \
1569 {"$17", RTYPE_NUM | 17}, \
1570 {"$18", RTYPE_NUM | 18}, \
1571 {"$19", RTYPE_NUM | 19}, \
1572 {"$20", RTYPE_NUM | 20}, \
1573 {"$21", RTYPE_NUM | 21}, \
1574 {"$22", RTYPE_NUM | 22}, \
1575 {"$23", RTYPE_NUM | 23}, \
1576 {"$24", RTYPE_NUM | 24}, \
1577 {"$25", RTYPE_NUM | 25}, \
1578 {"$26", RTYPE_NUM | 26}, \
1579 {"$27", RTYPE_NUM | 27}, \
1580 {"$28", RTYPE_NUM | 28}, \
1581 {"$29", RTYPE_NUM | 29}, \
1582 {"$30", RTYPE_NUM | 30}, \
1583 {"$31", RTYPE_NUM | 31}
1585 #define FPU_REGISTER_NAMES \
1586 {"$f0", RTYPE_FPU | 0}, \
1587 {"$f1", RTYPE_FPU | 1}, \
1588 {"$f2", RTYPE_FPU | 2}, \
1589 {"$f3", RTYPE_FPU | 3}, \
1590 {"$f4", RTYPE_FPU | 4}, \
1591 {"$f5", RTYPE_FPU | 5}, \
1592 {"$f6", RTYPE_FPU | 6}, \
1593 {"$f7", RTYPE_FPU | 7}, \
1594 {"$f8", RTYPE_FPU | 8}, \
1595 {"$f9", RTYPE_FPU | 9}, \
1596 {"$f10", RTYPE_FPU | 10}, \
1597 {"$f11", RTYPE_FPU | 11}, \
1598 {"$f12", RTYPE_FPU | 12}, \
1599 {"$f13", RTYPE_FPU | 13}, \
1600 {"$f14", RTYPE_FPU | 14}, \
1601 {"$f15", RTYPE_FPU | 15}, \
1602 {"$f16", RTYPE_FPU | 16}, \
1603 {"$f17", RTYPE_FPU | 17}, \
1604 {"$f18", RTYPE_FPU | 18}, \
1605 {"$f19", RTYPE_FPU | 19}, \
1606 {"$f20", RTYPE_FPU | 20}, \
1607 {"$f21", RTYPE_FPU | 21}, \
1608 {"$f22", RTYPE_FPU | 22}, \
1609 {"$f23", RTYPE_FPU | 23}, \
1610 {"$f24", RTYPE_FPU | 24}, \
1611 {"$f25", RTYPE_FPU | 25}, \
1612 {"$f26", RTYPE_FPU | 26}, \
1613 {"$f27", RTYPE_FPU | 27}, \
1614 {"$f28", RTYPE_FPU | 28}, \
1615 {"$f29", RTYPE_FPU | 29}, \
1616 {"$f30", RTYPE_FPU | 30}, \
1617 {"$f31", RTYPE_FPU | 31}
1619 #define FPU_CONDITION_CODE_NAMES \
1620 {"$fcc0", RTYPE_FCC | 0}, \
1621 {"$fcc1", RTYPE_FCC | 1}, \
1622 {"$fcc2", RTYPE_FCC | 2}, \
1623 {"$fcc3", RTYPE_FCC | 3}, \
1624 {"$fcc4", RTYPE_FCC | 4}, \
1625 {"$fcc5", RTYPE_FCC | 5}, \
1626 {"$fcc6", RTYPE_FCC | 6}, \
1627 {"$fcc7", RTYPE_FCC | 7}
1629 #define COPROC_CONDITION_CODE_NAMES \
1630 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1631 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1632 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1633 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1634 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1635 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1636 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1637 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1639 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1640 {"$a4", RTYPE_GP | 8}, \
1641 {"$a5", RTYPE_GP | 9}, \
1642 {"$a6", RTYPE_GP | 10}, \
1643 {"$a7", RTYPE_GP | 11}, \
1644 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1645 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1646 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1647 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1648 {"$t0", RTYPE_GP | 12}, \
1649 {"$t1", RTYPE_GP | 13}, \
1650 {"$t2", RTYPE_GP | 14}, \
1651 {"$t3", RTYPE_GP | 15}
1653 #define O32_SYMBOLIC_REGISTER_NAMES \
1654 {"$t0", RTYPE_GP | 8}, \
1655 {"$t1", RTYPE_GP | 9}, \
1656 {"$t2", RTYPE_GP | 10}, \
1657 {"$t3", RTYPE_GP | 11}, \
1658 {"$t4", RTYPE_GP | 12}, \
1659 {"$t5", RTYPE_GP | 13}, \
1660 {"$t6", RTYPE_GP | 14}, \
1661 {"$t7", RTYPE_GP | 15}, \
1662 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1663 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1664 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1665 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1667 /* Remaining symbolic register names */
1668 #define SYMBOLIC_REGISTER_NAMES \
1669 {"$zero", RTYPE_GP | 0}, \
1670 {"$at", RTYPE_GP | 1}, \
1671 {"$AT", RTYPE_GP | 1}, \
1672 {"$v0", RTYPE_GP | 2}, \
1673 {"$v1", RTYPE_GP | 3}, \
1674 {"$a0", RTYPE_GP | 4}, \
1675 {"$a1", RTYPE_GP | 5}, \
1676 {"$a2", RTYPE_GP | 6}, \
1677 {"$a3", RTYPE_GP | 7}, \
1678 {"$s0", RTYPE_GP | 16}, \
1679 {"$s1", RTYPE_GP | 17}, \
1680 {"$s2", RTYPE_GP | 18}, \
1681 {"$s3", RTYPE_GP | 19}, \
1682 {"$s4", RTYPE_GP | 20}, \
1683 {"$s5", RTYPE_GP | 21}, \
1684 {"$s6", RTYPE_GP | 22}, \
1685 {"$s7", RTYPE_GP | 23}, \
1686 {"$t8", RTYPE_GP | 24}, \
1687 {"$t9", RTYPE_GP | 25}, \
1688 {"$k0", RTYPE_GP | 26}, \
1689 {"$kt0", RTYPE_GP | 26}, \
1690 {"$k1", RTYPE_GP | 27}, \
1691 {"$kt1", RTYPE_GP | 27}, \
1692 {"$gp", RTYPE_GP | 28}, \
1693 {"$sp", RTYPE_GP | 29}, \
1694 {"$s8", RTYPE_GP | 30}, \
1695 {"$fp", RTYPE_GP | 30}, \
1696 {"$ra", RTYPE_GP | 31}
1698 #define MIPS16_SPECIAL_REGISTER_NAMES \
1699 {"$pc", RTYPE_PC | 0}
1701 #define MDMX_VECTOR_REGISTER_NAMES \
1702 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
1703 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
1704 {"$v2", RTYPE_VEC | 2}, \
1705 {"$v3", RTYPE_VEC | 3}, \
1706 {"$v4", RTYPE_VEC | 4}, \
1707 {"$v5", RTYPE_VEC | 5}, \
1708 {"$v6", RTYPE_VEC | 6}, \
1709 {"$v7", RTYPE_VEC | 7}, \
1710 {"$v8", RTYPE_VEC | 8}, \
1711 {"$v9", RTYPE_VEC | 9}, \
1712 {"$v10", RTYPE_VEC | 10}, \
1713 {"$v11", RTYPE_VEC | 11}, \
1714 {"$v12", RTYPE_VEC | 12}, \
1715 {"$v13", RTYPE_VEC | 13}, \
1716 {"$v14", RTYPE_VEC | 14}, \
1717 {"$v15", RTYPE_VEC | 15}, \
1718 {"$v16", RTYPE_VEC | 16}, \
1719 {"$v17", RTYPE_VEC | 17}, \
1720 {"$v18", RTYPE_VEC | 18}, \
1721 {"$v19", RTYPE_VEC | 19}, \
1722 {"$v20", RTYPE_VEC | 20}, \
1723 {"$v21", RTYPE_VEC | 21}, \
1724 {"$v22", RTYPE_VEC | 22}, \
1725 {"$v23", RTYPE_VEC | 23}, \
1726 {"$v24", RTYPE_VEC | 24}, \
1727 {"$v25", RTYPE_VEC | 25}, \
1728 {"$v26", RTYPE_VEC | 26}, \
1729 {"$v27", RTYPE_VEC | 27}, \
1730 {"$v28", RTYPE_VEC | 28}, \
1731 {"$v29", RTYPE_VEC | 29}, \
1732 {"$v30", RTYPE_VEC | 30}, \
1733 {"$v31", RTYPE_VEC | 31}
1735 #define MIPS_DSP_ACCUMULATOR_NAMES \
1736 {"$ac0", RTYPE_ACC | 0}, \
1737 {"$ac1", RTYPE_ACC | 1}, \
1738 {"$ac2", RTYPE_ACC | 2}, \
1739 {"$ac3", RTYPE_ACC | 3}
1741 static const struct regname reg_names[] = {
1742 GENERIC_REGISTER_NUMBERS,
1744 FPU_CONDITION_CODE_NAMES,
1745 COPROC_CONDITION_CODE_NAMES,
1747 /* The $txx registers depends on the abi,
1748 these will be added later into the symbol table from
1749 one of the tables below once mips_abi is set after
1750 parsing of arguments from the command line. */
1751 SYMBOLIC_REGISTER_NAMES,
1753 MIPS16_SPECIAL_REGISTER_NAMES,
1754 MDMX_VECTOR_REGISTER_NAMES,
1755 MIPS_DSP_ACCUMULATOR_NAMES,
1759 static const struct regname reg_names_o32[] = {
1760 O32_SYMBOLIC_REGISTER_NAMES,
1764 static const struct regname reg_names_n32n64[] = {
1765 N32N64_SYMBOLIC_REGISTER_NAMES,
1770 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
1777 /* Find end of name. */
1779 if (is_name_beginner (*e))
1781 while (is_part_of_name (*e))
1784 /* Terminate name. */
1788 /* Look for a register symbol. */
1789 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
1791 int r = S_GET_VALUE (symbolP);
1793 reg = r & RNUM_MASK;
1794 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
1795 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
1796 reg = (r & RNUM_MASK) - 2;
1798 /* Else see if this is a register defined in an itbl entry. */
1799 else if ((types & RTYPE_GP) && itbl_have_entries)
1806 if (itbl_get_reg_val (n, &r))
1807 reg = r & RNUM_MASK;
1810 /* Advance to next token if a register was recognised. */
1813 else if (types & RWARN)
1814 as_warn (_("Unrecognized register name `%s'"), *s);
1822 /* Return TRUE if opcode MO is valid on the currently selected ISA and
1823 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
1826 is_opcode_valid (const struct mips_opcode *mo)
1828 int isa = mips_opts.isa;
1831 if (mips_opts.ase_mdmx)
1833 if (mips_opts.ase_dsp)
1835 if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
1837 if (mips_opts.ase_dspr2)
1839 if (mips_opts.ase_mt)
1841 if (mips_opts.ase_mips3d)
1843 if (mips_opts.ase_smartmips)
1844 isa |= INSN_SMARTMIPS;
1846 /* Don't accept instructions based on the ISA if the CPU does not implement
1847 all the coprocessor insns. */
1848 if (NO_ISA_COP (mips_opts.arch)
1849 && COP_INSN (mo->pinfo))
1852 if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch))
1855 /* Check whether the instruction or macro requires single-precision or
1856 double-precision floating-point support. Note that this information is
1857 stored differently in the opcode table for insns and macros. */
1858 if (mo->pinfo == INSN_MACRO)
1860 fp_s = mo->pinfo2 & INSN2_M_FP_S;
1861 fp_d = mo->pinfo2 & INSN2_M_FP_D;
1865 fp_s = mo->pinfo & FP_S;
1866 fp_d = mo->pinfo & FP_D;
1869 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
1872 if (fp_s && mips_opts.soft_float)
1878 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
1879 selected ISA and architecture. */
1882 is_opcode_valid_16 (const struct mips_opcode *mo)
1884 return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE;
1887 /* This function is called once, at assembler startup time. It should set up
1888 all the tables, etc. that the MD part of the assembler will need. */
1893 const char *retval = NULL;
1897 if (mips_pic != NO_PIC)
1899 if (g_switch_seen && g_switch_value != 0)
1900 as_bad (_("-G may not be used in position-independent code"));
1904 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
1905 as_warn (_("Could not set architecture and machine"));
1907 op_hash = hash_new ();
1909 for (i = 0; i < NUMOPCODES;)
1911 const char *name = mips_opcodes[i].name;
1913 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
1916 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1917 mips_opcodes[i].name, retval);
1918 /* Probably a memory allocation problem? Give up now. */
1919 as_fatal (_("Broken assembler. No assembly attempted."));
1923 if (mips_opcodes[i].pinfo != INSN_MACRO)
1925 if (!validate_mips_insn (&mips_opcodes[i]))
1927 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
1929 create_insn (&nop_insn, mips_opcodes + i);
1930 if (mips_fix_loongson2f_nop)
1931 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
1932 nop_insn.fixed_p = 1;
1937 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1940 mips16_op_hash = hash_new ();
1943 while (i < bfd_mips16_num_opcodes)
1945 const char *name = mips16_opcodes[i].name;
1947 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
1949 as_fatal (_("internal: can't hash `%s': %s"),
1950 mips16_opcodes[i].name, retval);
1953 if (mips16_opcodes[i].pinfo != INSN_MACRO
1954 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1955 != mips16_opcodes[i].match))
1957 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1958 mips16_opcodes[i].name, mips16_opcodes[i].args);
1961 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
1963 create_insn (&mips16_nop_insn, mips16_opcodes + i);
1964 mips16_nop_insn.fixed_p = 1;
1968 while (i < bfd_mips16_num_opcodes
1969 && strcmp (mips16_opcodes[i].name, name) == 0);
1973 as_fatal (_("Broken assembler. No assembly attempted."));
1975 /* We add all the general register names to the symbol table. This
1976 helps us detect invalid uses of them. */
1977 for (i = 0; reg_names[i].name; i++)
1978 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
1979 reg_names[i].num, /* & RNUM_MASK, */
1980 &zero_address_frag));
1982 for (i = 0; reg_names_n32n64[i].name; i++)
1983 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
1984 reg_names_n32n64[i].num, /* & RNUM_MASK, */
1985 &zero_address_frag));
1987 for (i = 0; reg_names_o32[i].name; i++)
1988 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
1989 reg_names_o32[i].num, /* & RNUM_MASK, */
1990 &zero_address_frag));
1992 mips_no_prev_insn ();
1995 mips_cprmask[0] = 0;
1996 mips_cprmask[1] = 0;
1997 mips_cprmask[2] = 0;
1998 mips_cprmask[3] = 0;
2000 /* set the default alignment for the text section (2**2) */
2001 record_alignment (text_section, 2);
2003 bfd_set_gp_size (stdoutput, g_switch_value);
2008 /* On a native system other than VxWorks, sections must be aligned
2009 to 16 byte boundaries. When configured for an embedded ELF
2010 target, we don't bother. */
2011 if (strncmp (TARGET_OS, "elf", 3) != 0
2012 && strncmp (TARGET_OS, "vxworks", 7) != 0)
2014 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
2015 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
2016 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
2019 /* Create a .reginfo section for register masks and a .mdebug
2020 section for debugging information. */
2028 subseg = now_subseg;
2030 /* The ABI says this section should be loaded so that the
2031 running program can access it. However, we don't load it
2032 if we are configured for an embedded target */
2033 flags = SEC_READONLY | SEC_DATA;
2034 if (strncmp (TARGET_OS, "elf", 3) != 0)
2035 flags |= SEC_ALLOC | SEC_LOAD;
2037 if (mips_abi != N64_ABI)
2039 sec = subseg_new (".reginfo", (subsegT) 0);
2041 bfd_set_section_flags (stdoutput, sec, flags);
2042 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
2044 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
2048 /* The 64-bit ABI uses a .MIPS.options section rather than
2049 .reginfo section. */
2050 sec = subseg_new (".MIPS.options", (subsegT) 0);
2051 bfd_set_section_flags (stdoutput, sec, flags);
2052 bfd_set_section_alignment (stdoutput, sec, 3);
2054 /* Set up the option header. */
2056 Elf_Internal_Options opthdr;
2059 opthdr.kind = ODK_REGINFO;
2060 opthdr.size = (sizeof (Elf_External_Options)
2061 + sizeof (Elf64_External_RegInfo));
2064 f = frag_more (sizeof (Elf_External_Options));
2065 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2066 (Elf_External_Options *) f);
2068 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2072 if (ECOFF_DEBUGGING)
2074 sec = subseg_new (".mdebug", (subsegT) 0);
2075 (void) bfd_set_section_flags (stdoutput, sec,
2076 SEC_HAS_CONTENTS | SEC_READONLY);
2077 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2079 else if (mips_flag_pdr)
2081 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2082 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2083 SEC_READONLY | SEC_RELOC
2085 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2088 subseg_set (seg, subseg);
2091 #endif /* OBJ_ELF */
2093 if (! ECOFF_DEBUGGING)
2096 if (mips_fix_vr4120)
2097 init_vr4120_conflicts ();
2103 if (! ECOFF_DEBUGGING)
2108 md_assemble (char *str)
2110 struct mips_cl_insn insn;
2111 bfd_reloc_code_real_type unused_reloc[3]
2112 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2114 imm_expr.X_op = O_absent;
2115 imm2_expr.X_op = O_absent;
2116 offset_expr.X_op = O_absent;
2117 imm_reloc[0] = BFD_RELOC_UNUSED;
2118 imm_reloc[1] = BFD_RELOC_UNUSED;
2119 imm_reloc[2] = BFD_RELOC_UNUSED;
2120 offset_reloc[0] = BFD_RELOC_UNUSED;
2121 offset_reloc[1] = BFD_RELOC_UNUSED;
2122 offset_reloc[2] = BFD_RELOC_UNUSED;
2124 if (mips_opts.mips16)
2125 mips16_ip (str, &insn);
2128 mips_ip (str, &insn);
2129 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2130 str, insn.insn_opcode));
2135 as_bad ("%s `%s'", insn_error, str);
2139 if (insn.insn_mo->pinfo == INSN_MACRO)
2142 if (mips_opts.mips16)
2143 mips16_macro (&insn);
2150 if (imm_expr.X_op != O_absent)
2151 append_insn (&insn, &imm_expr, imm_reloc);
2152 else if (offset_expr.X_op != O_absent)
2153 append_insn (&insn, &offset_expr, offset_reloc);
2155 append_insn (&insn, NULL, unused_reloc);
2159 /* Convenience functions for abstracting away the differences between
2160 MIPS16 and non-MIPS16 relocations. */
2162 static inline bfd_boolean
2163 mips16_reloc_p (bfd_reloc_code_real_type reloc)
2167 case BFD_RELOC_MIPS16_JMP:
2168 case BFD_RELOC_MIPS16_GPREL:
2169 case BFD_RELOC_MIPS16_GOT16:
2170 case BFD_RELOC_MIPS16_CALL16:
2171 case BFD_RELOC_MIPS16_HI16_S:
2172 case BFD_RELOC_MIPS16_HI16:
2173 case BFD_RELOC_MIPS16_LO16:
2181 static inline bfd_boolean
2182 got16_reloc_p (bfd_reloc_code_real_type reloc)
2184 return reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16;
2187 static inline bfd_boolean
2188 hi16_reloc_p (bfd_reloc_code_real_type reloc)
2190 return reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S;
2193 static inline bfd_boolean
2194 lo16_reloc_p (bfd_reloc_code_real_type reloc)
2196 return reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16;
2199 /* Return true if the given relocation might need a matching %lo().
2200 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2201 need a matching %lo() when applied to local symbols. */
2203 static inline bfd_boolean
2204 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
2206 return (HAVE_IN_PLACE_ADDENDS
2207 && (hi16_reloc_p (reloc)
2208 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2209 all GOT16 relocations evaluate to "G". */
2210 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
2213 /* Return the type of %lo() reloc needed by RELOC, given that
2214 reloc_needs_lo_p. */
2216 static inline bfd_reloc_code_real_type
2217 matching_lo_reloc (bfd_reloc_code_real_type reloc)
2219 return mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 : BFD_RELOC_LO16;
2222 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2225 static inline bfd_boolean
2226 fixup_has_matching_lo_p (fixS *fixp)
2228 return (fixp->fx_next != NULL
2229 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
2230 && fixp->fx_addsy == fixp->fx_next->fx_addsy
2231 && fixp->fx_offset == fixp->fx_next->fx_offset);
2234 /* See whether instruction IP reads register REG. CLASS is the type
2238 insn_uses_reg (const struct mips_cl_insn *ip, unsigned int reg,
2239 enum mips_regclass regclass)
2241 if (regclass == MIPS16_REG)
2243 gas_assert (mips_opts.mips16);
2244 reg = mips16_to_32_reg_map[reg];
2245 regclass = MIPS_GR_REG;
2248 /* Don't report on general register ZERO, since it never changes. */
2249 if (regclass == MIPS_GR_REG && reg == ZERO)
2252 if (regclass == MIPS_FP_REG)
2254 gas_assert (! mips_opts.mips16);
2255 /* If we are called with either $f0 or $f1, we must check $f0.
2256 This is not optimal, because it will introduce an unnecessary
2257 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
2258 need to distinguish reading both $f0 and $f1 or just one of
2259 them. Note that we don't have to check the other way,
2260 because there is no instruction that sets both $f0 and $f1
2261 and requires a delay. */
2262 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
2263 && ((EXTRACT_OPERAND (FS, *ip) & ~(unsigned) 1)
2264 == (reg &~ (unsigned) 1)))
2266 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
2267 && ((EXTRACT_OPERAND (FT, *ip) & ~(unsigned) 1)
2268 == (reg &~ (unsigned) 1)))
2271 else if (! mips_opts.mips16)
2273 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
2274 && EXTRACT_OPERAND (RS, *ip) == reg)
2276 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
2277 && EXTRACT_OPERAND (RT, *ip) == reg)
2282 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
2283 && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)] == reg)
2285 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
2286 && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)] == reg)
2288 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
2289 && (mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]
2292 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
2294 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
2296 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
2298 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
2299 && MIPS16_EXTRACT_OPERAND (REGR32, *ip) == reg)
2306 /* This function returns true if modifying a register requires a
2310 reg_needs_delay (unsigned int reg)
2312 unsigned long prev_pinfo;
2314 prev_pinfo = history[0].insn_mo->pinfo;
2315 if (! mips_opts.noreorder
2316 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2317 && ! gpr_interlocks)
2318 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
2319 && ! cop_interlocks)))
2321 /* A load from a coprocessor or from memory. All load delays
2322 delay the use of general register rt for one instruction. */
2323 /* Itbl support may require additional care here. */
2324 know (prev_pinfo & INSN_WRITE_GPR_T);
2325 if (reg == EXTRACT_OPERAND (RT, history[0]))
2332 /* Move all labels in insn_labels to the current insertion point. */
2335 mips_move_labels (void)
2337 segment_info_type *si = seg_info (now_seg);
2338 struct insn_label_list *l;
2341 for (l = si->label_list; l != NULL; l = l->next)
2343 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
2344 symbol_set_frag (l->label, frag_now);
2345 val = (valueT) frag_now_fix ();
2346 /* mips16 text labels are stored as odd. */
2347 if (mips_opts.mips16)
2349 S_SET_VALUE (l->label, val);
2354 s_is_linkonce (symbolS *sym, segT from_seg)
2356 bfd_boolean linkonce = FALSE;
2357 segT symseg = S_GET_SEGMENT (sym);
2359 if (symseg != from_seg && !S_IS_LOCAL (sym))
2361 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
2364 /* The GNU toolchain uses an extension for ELF: a section
2365 beginning with the magic string .gnu.linkonce is a
2366 linkonce section. */
2367 if (strncmp (segment_name (symseg), ".gnu.linkonce",
2368 sizeof ".gnu.linkonce" - 1) == 0)
2375 /* Mark instruction labels in mips16 mode. This permits the linker to
2376 handle them specially, such as generating jalx instructions when
2377 needed. We also make them odd for the duration of the assembly, in
2378 order to generate the right sort of code. We will make them even
2379 in the adjust_symtab routine, while leaving them marked. This is
2380 convenient for the debugger and the disassembler. The linker knows
2381 to make them odd again. */
2384 mips16_mark_labels (void)
2386 segment_info_type *si = seg_info (now_seg);
2387 struct insn_label_list *l;
2389 if (!mips_opts.mips16)
2392 for (l = si->label_list; l != NULL; l = l->next)
2394 symbolS *label = l->label;
2396 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2398 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
2400 if ((S_GET_VALUE (label) & 1) == 0
2401 /* Don't adjust the address if the label is global or weak, or
2402 in a link-once section, since we'll be emitting symbol reloc
2403 references to it which will be patched up by the linker, and
2404 the final value of the symbol may or may not be MIPS16. */
2405 && ! S_IS_WEAK (label)
2406 && ! S_IS_EXTERNAL (label)
2407 && ! s_is_linkonce (label, now_seg))
2408 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
2412 /* End the current frag. Make it a variant frag and record the
2416 relax_close_frag (void)
2418 mips_macro_warning.first_frag = frag_now;
2419 frag_var (rs_machine_dependent, 0, 0,
2420 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
2421 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
2423 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
2424 mips_relax.first_fixup = 0;
2427 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2428 See the comment above RELAX_ENCODE for more details. */
2431 relax_start (symbolS *symbol)
2433 gas_assert (mips_relax.sequence == 0);
2434 mips_relax.sequence = 1;
2435 mips_relax.symbol = symbol;
2438 /* Start generating the second version of a relaxable sequence.
2439 See the comment above RELAX_ENCODE for more details. */
2444 gas_assert (mips_relax.sequence == 1);
2445 mips_relax.sequence = 2;
2448 /* End the current relaxable sequence. */
2453 gas_assert (mips_relax.sequence == 2);
2454 relax_close_frag ();
2455 mips_relax.sequence = 0;
2458 /* Classify an instruction according to the FIX_VR4120_* enumeration.
2459 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
2460 by VR4120 errata. */
2463 classify_vr4120_insn (const char *name)
2465 if (strncmp (name, "macc", 4) == 0)
2466 return FIX_VR4120_MACC;
2467 if (strncmp (name, "dmacc", 5) == 0)
2468 return FIX_VR4120_DMACC;
2469 if (strncmp (name, "mult", 4) == 0)
2470 return FIX_VR4120_MULT;
2471 if (strncmp (name, "dmult", 5) == 0)
2472 return FIX_VR4120_DMULT;
2473 if (strstr (name, "div"))
2474 return FIX_VR4120_DIV;
2475 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
2476 return FIX_VR4120_MTHILO;
2477 return NUM_FIX_VR4120_CLASSES;
2480 #define INSN_ERET 0x42000018
2481 #define INSN_DERET 0x4200001f
2483 /* Return the number of instructions that must separate INSN1 and INSN2,
2484 where INSN1 is the earlier instruction. Return the worst-case value
2485 for any INSN2 if INSN2 is null. */
2488 insns_between (const struct mips_cl_insn *insn1,
2489 const struct mips_cl_insn *insn2)
2491 unsigned long pinfo1, pinfo2;
2493 /* This function needs to know which pinfo flags are set for INSN2
2494 and which registers INSN2 uses. The former is stored in PINFO2 and
2495 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
2496 will have every flag set and INSN2_USES_REG will always return true. */
2497 pinfo1 = insn1->insn_mo->pinfo;
2498 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
2500 #define INSN2_USES_REG(REG, CLASS) \
2501 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
2503 /* For most targets, write-after-read dependencies on the HI and LO
2504 registers must be separated by at least two instructions. */
2505 if (!hilo_interlocks)
2507 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
2509 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
2513 /* If we're working around r7000 errata, there must be two instructions
2514 between an mfhi or mflo and any instruction that uses the result. */
2515 if (mips_7000_hilo_fix
2516 && MF_HILO_INSN (pinfo1)
2517 && INSN2_USES_REG (EXTRACT_OPERAND (RD, *insn1), MIPS_GR_REG))
2520 /* If we're working around 24K errata, one instruction is required
2521 if an ERET or DERET is followed by a branch instruction. */
2524 if (insn1->insn_opcode == INSN_ERET
2525 || insn1->insn_opcode == INSN_DERET)
2528 || insn2->insn_opcode == INSN_ERET
2529 || insn2->insn_opcode == INSN_DERET
2530 || (insn2->insn_mo->pinfo
2531 & (INSN_UNCOND_BRANCH_DELAY
2532 | INSN_COND_BRANCH_DELAY
2533 | INSN_COND_BRANCH_LIKELY)) != 0)
2538 /* If working around VR4120 errata, check for combinations that need
2539 a single intervening instruction. */
2540 if (mips_fix_vr4120)
2542 unsigned int class1, class2;
2544 class1 = classify_vr4120_insn (insn1->insn_mo->name);
2545 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
2549 class2 = classify_vr4120_insn (insn2->insn_mo->name);
2550 if (vr4120_conflicts[class1] & (1 << class2))
2555 if (!mips_opts.mips16)
2557 /* Check for GPR or coprocessor load delays. All such delays
2558 are on the RT register. */
2559 /* Itbl support may require additional care here. */
2560 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
2561 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
2563 know (pinfo1 & INSN_WRITE_GPR_T);
2564 if (INSN2_USES_REG (EXTRACT_OPERAND (RT, *insn1), MIPS_GR_REG))
2568 /* Check for generic coprocessor hazards.
2570 This case is not handled very well. There is no special
2571 knowledge of CP0 handling, and the coprocessors other than
2572 the floating point unit are not distinguished at all. */
2573 /* Itbl support may require additional care here. FIXME!
2574 Need to modify this to include knowledge about
2575 user specified delays! */
2576 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
2577 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
2579 /* Handle cases where INSN1 writes to a known general coprocessor
2580 register. There must be a one instruction delay before INSN2
2581 if INSN2 reads that register, otherwise no delay is needed. */
2582 if (pinfo1 & INSN_WRITE_FPR_T)
2584 if (INSN2_USES_REG (EXTRACT_OPERAND (FT, *insn1), MIPS_FP_REG))
2587 else if (pinfo1 & INSN_WRITE_FPR_S)
2589 if (INSN2_USES_REG (EXTRACT_OPERAND (FS, *insn1), MIPS_FP_REG))
2594 /* Read-after-write dependencies on the control registers
2595 require a two-instruction gap. */
2596 if ((pinfo1 & INSN_WRITE_COND_CODE)
2597 && (pinfo2 & INSN_READ_COND_CODE))
2600 /* We don't know exactly what INSN1 does. If INSN2 is
2601 also a coprocessor instruction, assume there must be
2602 a one instruction gap. */
2603 if (pinfo2 & INSN_COP)
2608 /* Check for read-after-write dependencies on the coprocessor
2609 control registers in cases where INSN1 does not need a general
2610 coprocessor delay. This means that INSN1 is a floating point
2611 comparison instruction. */
2612 /* Itbl support may require additional care here. */
2613 else if (!cop_interlocks
2614 && (pinfo1 & INSN_WRITE_COND_CODE)
2615 && (pinfo2 & INSN_READ_COND_CODE))
2619 #undef INSN2_USES_REG
2624 /* Return the number of nops that would be needed to work around the
2625 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2626 the MAX_VR4130_NOPS instructions described by HIST. */
2629 nops_for_vr4130 (const struct mips_cl_insn *hist,
2630 const struct mips_cl_insn *insn)
2634 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2635 are not affected by the errata. */
2637 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
2638 || strcmp (insn->insn_mo->name, "mtlo") == 0
2639 || strcmp (insn->insn_mo->name, "mthi") == 0))
2642 /* Search for the first MFLO or MFHI. */
2643 for (i = 0; i < MAX_VR4130_NOPS; i++)
2644 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
2646 /* Extract the destination register. */
2647 if (mips_opts.mips16)
2648 reg = mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, hist[i])];
2650 reg = EXTRACT_OPERAND (RD, hist[i]);
2652 /* No nops are needed if INSN reads that register. */
2653 if (insn != NULL && insn_uses_reg (insn, reg, MIPS_GR_REG))
2656 /* ...or if any of the intervening instructions do. */
2657 for (j = 0; j < i; j++)
2658 if (insn_uses_reg (&hist[j], reg, MIPS_GR_REG))
2661 return MAX_VR4130_NOPS - i;
2666 /* Return the number of nops that would be needed if instruction INSN
2667 immediately followed the MAX_NOPS instructions given by HIST,
2668 where HIST[0] is the most recent instruction. If INSN is null,
2669 return the worse-case number of nops for any instruction. */
2672 nops_for_insn (const struct mips_cl_insn *hist,
2673 const struct mips_cl_insn *insn)
2675 int i, nops, tmp_nops;
2678 for (i = 0; i < MAX_DELAY_NOPS; i++)
2680 tmp_nops = insns_between (hist + i, insn) - i;
2681 if (tmp_nops > nops)
2685 if (mips_fix_vr4130)
2687 tmp_nops = nops_for_vr4130 (hist, insn);
2688 if (tmp_nops > nops)
2695 /* The variable arguments provide NUM_INSNS extra instructions that
2696 might be added to HIST. Return the largest number of nops that
2697 would be needed after the extended sequence. */
2700 nops_for_sequence (int num_insns, const struct mips_cl_insn *hist, ...)
2703 struct mips_cl_insn buffer[MAX_NOPS];
2704 struct mips_cl_insn *cursor;
2707 va_start (args, hist);
2708 cursor = buffer + num_insns;
2709 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
2710 while (cursor > buffer)
2711 *--cursor = *va_arg (args, const struct mips_cl_insn *);
2713 nops = nops_for_insn (buffer, NULL);
2718 /* Like nops_for_insn, but if INSN is a branch, take into account the
2719 worst-case delay for the branch target. */
2722 nops_for_insn_or_target (const struct mips_cl_insn *hist,
2723 const struct mips_cl_insn *insn)
2727 nops = nops_for_insn (hist, insn);
2728 if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
2729 | INSN_COND_BRANCH_DELAY
2730 | INSN_COND_BRANCH_LIKELY))
2732 tmp_nops = nops_for_sequence (2, hist, insn, NOP_INSN);
2733 if (tmp_nops > nops)
2736 else if (mips_opts.mips16
2737 && (insn->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
2738 | MIPS16_INSN_COND_BRANCH)))
2740 tmp_nops = nops_for_sequence (1, hist, insn);
2741 if (tmp_nops > nops)
2747 /* Fix NOP issue: Replace nops by "or at,at,zero". */
2750 fix_loongson2f_nop (struct mips_cl_insn * ip)
2752 if (strcmp (ip->insn_mo->name, "nop") == 0)
2753 ip->insn_opcode = LOONGSON2F_NOP_INSN;
2756 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
2757 jr target pc &= 'hffff_ffff_cfff_ffff. */
2760 fix_loongson2f_jump (struct mips_cl_insn * ip)
2762 if (strcmp (ip->insn_mo->name, "j") == 0
2763 || strcmp (ip->insn_mo->name, "jr") == 0
2764 || strcmp (ip->insn_mo->name, "jalr") == 0)
2772 sreg = EXTRACT_OPERAND (RS, *ip);
2773 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
2776 ep.X_op = O_constant;
2777 ep.X_add_number = 0xcfff0000;
2778 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
2779 ep.X_add_number = 0xffff;
2780 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
2781 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
2786 fix_loongson2f (struct mips_cl_insn * ip)
2788 if (mips_fix_loongson2f_nop)
2789 fix_loongson2f_nop (ip);
2791 if (mips_fix_loongson2f_jump)
2792 fix_loongson2f_jump (ip);
2795 /* Output an instruction. IP is the instruction information.
2796 ADDRESS_EXPR is an operand of the instruction to be used with
2800 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
2801 bfd_reloc_code_real_type *reloc_type)
2803 unsigned long prev_pinfo, pinfo;
2804 relax_stateT prev_insn_frag_type = 0;
2805 bfd_boolean relaxed_branch = FALSE;
2806 segment_info_type *si = seg_info (now_seg);
2808 if (mips_fix_loongson2f)
2809 fix_loongson2f (ip);
2811 /* Mark instruction labels in mips16 mode. */
2812 mips16_mark_labels ();
2814 prev_pinfo = history[0].insn_mo->pinfo;
2815 pinfo = ip->insn_mo->pinfo;
2817 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
2819 /* There are a lot of optimizations we could do that we don't.
2820 In particular, we do not, in general, reorder instructions.
2821 If you use gcc with optimization, it will reorder
2822 instructions and generally do much more optimization then we
2823 do here; repeating all that work in the assembler would only
2824 benefit hand written assembly code, and does not seem worth
2826 int nops = (mips_optimize == 0
2827 ? nops_for_insn (history, NULL)
2828 : nops_for_insn_or_target (history, ip));
2832 unsigned long old_frag_offset;
2835 old_frag = frag_now;
2836 old_frag_offset = frag_now_fix ();
2838 for (i = 0; i < nops; i++)
2843 listing_prev_line ();
2844 /* We may be at the start of a variant frag. In case we
2845 are, make sure there is enough space for the frag
2846 after the frags created by listing_prev_line. The
2847 argument to frag_grow here must be at least as large
2848 as the argument to all other calls to frag_grow in
2849 this file. We don't have to worry about being in the
2850 middle of a variant frag, because the variants insert
2851 all needed nop instructions themselves. */
2855 mips_move_labels ();
2857 #ifndef NO_ECOFF_DEBUGGING
2858 if (ECOFF_DEBUGGING)
2859 ecoff_fix_loc (old_frag, old_frag_offset);
2863 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
2865 /* Work out how many nops in prev_nop_frag are needed by IP. */
2866 int nops = nops_for_insn_or_target (history, ip);
2867 gas_assert (nops <= prev_nop_frag_holds);
2869 /* Enforce NOPS as a minimum. */
2870 if (nops > prev_nop_frag_required)
2871 prev_nop_frag_required = nops;
2873 if (prev_nop_frag_holds == prev_nop_frag_required)
2875 /* Settle for the current number of nops. Update the history
2876 accordingly (for the benefit of any future .set reorder code). */
2877 prev_nop_frag = NULL;
2878 insert_into_history (prev_nop_frag_since,
2879 prev_nop_frag_holds, NOP_INSN);
2883 /* Allow this instruction to replace one of the nops that was
2884 tentatively added to prev_nop_frag. */
2885 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
2886 prev_nop_frag_holds--;
2887 prev_nop_frag_since++;
2892 /* The value passed to dwarf2_emit_insn is the distance between
2893 the beginning of the current instruction and the address that
2894 should be recorded in the debug tables. For MIPS16 debug info
2895 we want to use ISA-encoded addresses, so we pass -1 for an
2896 address higher by one than the current. */
2897 dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0);
2900 /* Record the frag type before frag_var. */
2901 if (history[0].frag)
2902 prev_insn_frag_type = history[0].frag->fr_type;
2905 && *reloc_type == BFD_RELOC_16_PCREL_S2
2906 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
2907 || pinfo & INSN_COND_BRANCH_LIKELY)
2908 && mips_relax_branch
2909 /* Don't try branch relaxation within .set nomacro, or within
2910 .set noat if we use $at for PIC computations. If it turns
2911 out that the branch was out-of-range, we'll get an error. */
2912 && !mips_opts.warn_about_macros
2913 && (mips_opts.at || mips_pic == NO_PIC)
2914 && !mips_opts.mips16)
2916 relaxed_branch = TRUE;
2917 add_relaxed_insn (ip, (relaxed_branch_length
2919 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
2920 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1
2923 (pinfo & INSN_UNCOND_BRANCH_DELAY,
2924 pinfo & INSN_COND_BRANCH_LIKELY,
2925 pinfo & INSN_WRITE_GPR_31,
2927 address_expr->X_add_symbol,
2928 address_expr->X_add_number);
2929 *reloc_type = BFD_RELOC_UNUSED;
2931 else if (*reloc_type > BFD_RELOC_UNUSED)
2933 /* We need to set up a variant frag. */
2934 gas_assert (mips_opts.mips16 && address_expr != NULL);
2935 add_relaxed_insn (ip, 4, 0,
2937 (*reloc_type - BFD_RELOC_UNUSED,
2938 mips16_small, mips16_ext,
2939 prev_pinfo & INSN_UNCOND_BRANCH_DELAY,
2940 history[0].mips16_absolute_jump_p),
2941 make_expr_symbol (address_expr), 0);
2943 else if (mips_opts.mips16
2945 && *reloc_type != BFD_RELOC_MIPS16_JMP)
2947 if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0)
2948 /* Make sure there is enough room to swap this instruction with
2949 a following jump instruction. */
2951 add_fixed_insn (ip);
2955 if (mips_opts.mips16
2956 && mips_opts.noreorder
2957 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2958 as_warn (_("extended instruction in delay slot"));
2960 if (mips_relax.sequence)
2962 /* If we've reached the end of this frag, turn it into a variant
2963 frag and record the information for the instructions we've
2965 if (frag_room () < 4)
2966 relax_close_frag ();
2967 mips_relax.sizes[mips_relax.sequence - 1] += 4;
2970 if (mips_relax.sequence != 2)
2971 mips_macro_warning.sizes[0] += 4;
2972 if (mips_relax.sequence != 1)
2973 mips_macro_warning.sizes[1] += 4;
2975 if (mips_opts.mips16)
2978 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
2980 add_fixed_insn (ip);
2983 if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED)
2985 if (address_expr->X_op == O_constant)
2989 switch (*reloc_type)
2992 ip->insn_opcode |= address_expr->X_add_number;
2995 case BFD_RELOC_MIPS_HIGHEST:
2996 tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48;
2997 ip->insn_opcode |= tmp & 0xffff;
3000 case BFD_RELOC_MIPS_HIGHER:
3001 tmp = (address_expr->X_add_number + 0x80008000ull) >> 32;
3002 ip->insn_opcode |= tmp & 0xffff;
3005 case BFD_RELOC_HI16_S:
3006 tmp = (address_expr->X_add_number + 0x8000) >> 16;
3007 ip->insn_opcode |= tmp & 0xffff;
3010 case BFD_RELOC_HI16:
3011 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
3014 case BFD_RELOC_UNUSED:
3015 case BFD_RELOC_LO16:
3016 case BFD_RELOC_MIPS_GOT_DISP:
3017 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
3020 case BFD_RELOC_MIPS_JMP:
3021 if ((address_expr->X_add_number & 3) != 0)
3022 as_bad (_("jump to misaligned address (0x%lx)"),
3023 (unsigned long) address_expr->X_add_number);
3024 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
3027 case BFD_RELOC_MIPS16_JMP:
3028 if ((address_expr->X_add_number & 3) != 0)
3029 as_bad (_("jump to misaligned address (0x%lx)"),
3030 (unsigned long) address_expr->X_add_number);
3032 (((address_expr->X_add_number & 0x7c0000) << 3)
3033 | ((address_expr->X_add_number & 0xf800000) >> 7)
3034 | ((address_expr->X_add_number & 0x3fffc) >> 2));
3037 case BFD_RELOC_16_PCREL_S2:
3038 if ((address_expr->X_add_number & 3) != 0)
3039 as_bad (_("branch to misaligned address (0x%lx)"),
3040 (unsigned long) address_expr->X_add_number);
3041 if (mips_relax_branch)
3043 if ((address_expr->X_add_number + 0x20000) & ~0x3ffff)
3044 as_bad (_("branch address range overflow (0x%lx)"),
3045 (unsigned long) address_expr->X_add_number);
3046 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff;
3053 else if (*reloc_type < BFD_RELOC_UNUSED)
3056 reloc_howto_type *howto;
3059 /* In a compound relocation, it is the final (outermost)
3060 operator that determines the relocated field. */
3061 for (i = 1; i < 3; i++)
3062 if (reloc_type[i] == BFD_RELOC_UNUSED)
3065 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
3068 /* To reproduce this failure try assembling gas/testsuites/
3069 gas/mips/mips16-intermix.s with a mips-ecoff targeted
3071 as_bad (_("Unsupported MIPS relocation number %d"), reloc_type[i - 1]);
3072 howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16);
3075 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
3076 bfd_get_reloc_size (howto),
3078 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
3081 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
3082 if (reloc_type[0] == BFD_RELOC_MIPS16_JMP
3083 && ip->fixp[0]->fx_addsy)
3084 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
3086 /* These relocations can have an addend that won't fit in
3087 4 octets for 64bit assembly. */
3089 && ! howto->partial_inplace
3090 && (reloc_type[0] == BFD_RELOC_16
3091 || reloc_type[0] == BFD_RELOC_32
3092 || reloc_type[0] == BFD_RELOC_MIPS_JMP
3093 || reloc_type[0] == BFD_RELOC_GPREL16
3094 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
3095 || reloc_type[0] == BFD_RELOC_GPREL32
3096 || reloc_type[0] == BFD_RELOC_64
3097 || reloc_type[0] == BFD_RELOC_CTOR
3098 || reloc_type[0] == BFD_RELOC_MIPS_SUB
3099 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
3100 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
3101 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
3102 || reloc_type[0] == BFD_RELOC_MIPS_REL16
3103 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
3104 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
3105 || hi16_reloc_p (reloc_type[0])
3106 || lo16_reloc_p (reloc_type[0])))
3107 ip->fixp[0]->fx_no_overflow = 1;
3109 if (mips_relax.sequence)
3111 if (mips_relax.first_fixup == 0)
3112 mips_relax.first_fixup = ip->fixp[0];
3114 else if (reloc_needs_lo_p (*reloc_type))
3116 struct mips_hi_fixup *hi_fixup;
3118 /* Reuse the last entry if it already has a matching %lo. */
3119 hi_fixup = mips_hi_fixup_list;
3121 || !fixup_has_matching_lo_p (hi_fixup->fixp))
3123 hi_fixup = ((struct mips_hi_fixup *)
3124 xmalloc (sizeof (struct mips_hi_fixup)));
3125 hi_fixup->next = mips_hi_fixup_list;
3126 mips_hi_fixup_list = hi_fixup;
3128 hi_fixup->fixp = ip->fixp[0];
3129 hi_fixup->seg = now_seg;
3132 /* Add fixups for the second and third relocations, if given.
3133 Note that the ABI allows the second relocation to be
3134 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
3135 moment we only use RSS_UNDEF, but we could add support
3136 for the others if it ever becomes necessary. */
3137 for (i = 1; i < 3; i++)
3138 if (reloc_type[i] != BFD_RELOC_UNUSED)
3140 ip->fixp[i] = fix_new (ip->frag, ip->where,
3141 ip->fixp[0]->fx_size, NULL, 0,
3142 FALSE, reloc_type[i]);
3144 /* Use fx_tcbit to mark compound relocs. */
3145 ip->fixp[0]->fx_tcbit = 1;
3146 ip->fixp[i]->fx_tcbit = 1;
3152 /* Update the register mask information. */
3153 if (! mips_opts.mips16)
3155 if (pinfo & INSN_WRITE_GPR_D)
3156 mips_gprmask |= 1 << EXTRACT_OPERAND (RD, *ip);
3157 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
3158 mips_gprmask |= 1 << EXTRACT_OPERAND (RT, *ip);
3159 if (pinfo & INSN_READ_GPR_S)
3160 mips_gprmask |= 1 << EXTRACT_OPERAND (RS, *ip);
3161 if (pinfo & INSN_WRITE_GPR_31)
3162 mips_gprmask |= 1 << RA;
3163 if (pinfo & INSN_WRITE_FPR_D)
3164 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FD, *ip);
3165 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
3166 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FS, *ip);
3167 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
3168 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FT, *ip);
3169 if ((pinfo & INSN_READ_FPR_R) != 0)
3170 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FR, *ip);
3171 if (pinfo & INSN_COP)
3173 /* We don't keep enough information to sort these cases out.
3174 The itbl support does keep this information however, although
3175 we currently don't support itbl fprmats as part of the cop
3176 instruction. May want to add this support in the future. */
3178 /* Never set the bit for $0, which is always zero. */
3179 mips_gprmask &= ~1 << 0;
3183 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
3184 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RX, *ip);
3185 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
3186 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RY, *ip);
3187 if (pinfo & MIPS16_INSN_WRITE_Z)
3188 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RZ, *ip);
3189 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
3190 mips_gprmask |= 1 << TREG;
3191 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
3192 mips_gprmask |= 1 << SP;
3193 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
3194 mips_gprmask |= 1 << RA;
3195 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
3196 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
3197 if (pinfo & MIPS16_INSN_READ_Z)
3198 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip);
3199 if (pinfo & MIPS16_INSN_READ_GPR_X)
3200 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
3203 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
3205 /* Filling the branch delay slot is more complex. We try to
3206 switch the branch with the previous instruction, which we can
3207 do if the previous instruction does not set up a condition
3208 that the branch tests and if the branch is not itself the
3209 target of any branch. */
3210 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
3211 || (pinfo & INSN_COND_BRANCH_DELAY))
3213 if (mips_optimize < 2
3214 /* If we have seen .set volatile or .set nomove, don't
3216 || mips_opts.nomove != 0
3217 /* We can't swap if the previous instruction's position
3219 || history[0].fixed_p
3220 /* If the previous previous insn was in a .set
3221 noreorder, we can't swap. Actually, the MIPS
3222 assembler will swap in this situation. However, gcc
3223 configured -with-gnu-as will generate code like
3229 in which we can not swap the bne and INSN. If gcc is
3230 not configured -with-gnu-as, it does not output the
3232 || history[1].noreorder_p
3233 /* If the branch is itself the target of a branch, we
3234 can not swap. We cheat on this; all we check for is
3235 whether there is a label on this instruction. If
3236 there are any branches to anything other than a
3237 label, users must use .set noreorder. */
3238 || si->label_list != NULL
3239 /* If the previous instruction is in a variant frag
3240 other than this branch's one, we cannot do the swap.
3241 This does not apply to the mips16, which uses variant
3242 frags for different purposes. */
3243 || (! mips_opts.mips16
3244 && prev_insn_frag_type == rs_machine_dependent)
3245 /* Check for conflicts between the branch and the instructions
3246 before the candidate delay slot. */
3247 || nops_for_insn (history + 1, ip) > 0
3248 /* Check for conflicts between the swapped sequence and the
3249 target of the branch. */
3250 || nops_for_sequence (2, history + 1, ip, history) > 0
3251 /* We do not swap with a trap instruction, since it
3252 complicates trap handlers to have the trap
3253 instruction be in a delay slot. */
3254 || (prev_pinfo & INSN_TRAP)
3255 /* If the branch reads a register that the previous
3256 instruction sets, we can not swap. */
3257 || (! mips_opts.mips16
3258 && (prev_pinfo & INSN_WRITE_GPR_T)
3259 && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]),
3261 || (! mips_opts.mips16
3262 && (prev_pinfo & INSN_WRITE_GPR_D)
3263 && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]),
3265 || (mips_opts.mips16
3266 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
3268 (ip, MIPS16_EXTRACT_OPERAND (RX, history[0]),
3270 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
3272 (ip, MIPS16_EXTRACT_OPERAND (RY, history[0]),
3274 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
3276 (ip, MIPS16_EXTRACT_OPERAND (RZ, history[0]),
3278 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
3279 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
3280 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
3281 && insn_uses_reg (ip, RA, MIPS_GR_REG))
3282 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
3283 && insn_uses_reg (ip,
3284 MIPS16OP_EXTRACT_REG32R
3285 (history[0].insn_opcode),
3287 /* If the branch writes a register that the previous
3288 instruction sets, we can not swap (we know that
3289 branches write only to RD or to $31). */
3290 || (! mips_opts.mips16
3291 && (prev_pinfo & INSN_WRITE_GPR_T)
3292 && (((pinfo & INSN_WRITE_GPR_D)
3293 && (EXTRACT_OPERAND (RT, history[0])
3294 == EXTRACT_OPERAND (RD, *ip)))
3295 || ((pinfo & INSN_WRITE_GPR_31)
3296 && EXTRACT_OPERAND (RT, history[0]) == RA)))
3297 || (! mips_opts.mips16
3298 && (prev_pinfo & INSN_WRITE_GPR_D)
3299 && (((pinfo & INSN_WRITE_GPR_D)
3300 && (EXTRACT_OPERAND (RD, history[0])
3301 == EXTRACT_OPERAND (RD, *ip)))
3302 || ((pinfo & INSN_WRITE_GPR_31)
3303 && EXTRACT_OPERAND (RD, history[0]) == RA)))
3304 || (mips_opts.mips16
3305 && (pinfo & MIPS16_INSN_WRITE_31)
3306 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
3307 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
3308 && (MIPS16OP_EXTRACT_REG32R (history[0].insn_opcode)
3310 /* If the branch writes a register that the previous
3311 instruction reads, we can not swap (we know that
3312 branches only write to RD or to $31). */
3313 || (! mips_opts.mips16
3314 && (pinfo & INSN_WRITE_GPR_D)
3315 && insn_uses_reg (&history[0],
3316 EXTRACT_OPERAND (RD, *ip),
3318 || (! mips_opts.mips16
3319 && (pinfo & INSN_WRITE_GPR_31)
3320 && insn_uses_reg (&history[0], RA, MIPS_GR_REG))
3321 || (mips_opts.mips16
3322 && (pinfo & MIPS16_INSN_WRITE_31)
3323 && insn_uses_reg (&history[0], RA, MIPS_GR_REG))
3324 /* If one instruction sets a condition code and the
3325 other one uses a condition code, we can not swap. */
3326 || ((pinfo & INSN_READ_COND_CODE)
3327 && (prev_pinfo & INSN_WRITE_COND_CODE))
3328 || ((pinfo & INSN_WRITE_COND_CODE)
3329 && (prev_pinfo & INSN_READ_COND_CODE))
3330 /* If the previous instruction uses the PC, we can not
3332 || (mips_opts.mips16
3333 && (prev_pinfo & MIPS16_INSN_READ_PC))
3334 /* If the previous instruction had a fixup in mips16
3335 mode, we can not swap. This normally means that the
3336 previous instruction was a 4 byte branch anyhow. */
3337 || (mips_opts.mips16 && history[0].fixp[0])
3338 /* If the previous instruction is a sync, sync.l, or
3339 sync.p, we can not swap. */
3340 || (prev_pinfo & INSN_SYNC)
3341 /* If the previous instruction is an ERET or
3342 DERET, avoid the swap. */
3343 || (history[0].insn_opcode == INSN_ERET)
3344 || (history[0].insn_opcode == INSN_DERET))
3346 if (mips_opts.mips16
3347 && (pinfo & INSN_UNCOND_BRANCH_DELAY)
3348 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))
3349 && ISA_SUPPORTS_MIPS16E)
3351 /* Convert MIPS16 jr/jalr into a "compact" jump. */
3352 ip->insn_opcode |= 0x0080;
3354 insert_into_history (0, 1, ip);
3358 /* We could do even better for unconditional branches to
3359 portions of this object file; we could pick up the
3360 instruction at the destination, put it in the delay
3361 slot, and bump the destination address. */
3362 insert_into_history (0, 1, ip);
3366 if (mips_relax.sequence)
3367 mips_relax.sizes[mips_relax.sequence - 1] += 4;
3371 /* It looks like we can actually do the swap. */
3372 struct mips_cl_insn delay = history[0];
3373 if (mips_opts.mips16)
3375 know (delay.frag == ip->frag);
3376 move_insn (ip, delay.frag, delay.where);
3377 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
3379 else if (relaxed_branch)
3381 /* Add the delay slot instruction to the end of the
3382 current frag and shrink the fixed part of the
3383 original frag. If the branch occupies the tail of
3384 the latter, move it backwards to cover the gap. */
3385 delay.frag->fr_fix -= 4;
3386 if (delay.frag == ip->frag)
3387 move_insn (ip, ip->frag, ip->where - 4);
3388 add_fixed_insn (&delay);
3392 move_insn (&delay, ip->frag, ip->where);
3393 move_insn (ip, history[0].frag, history[0].where);
3397 insert_into_history (0, 1, &delay);
3400 /* If that was an unconditional branch, forget the previous
3401 insn information. */
3402 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
3404 mips_no_prev_insn ();
3407 else if (pinfo & INSN_COND_BRANCH_LIKELY)
3409 /* We don't yet optimize a branch likely. What we should do
3410 is look at the target, copy the instruction found there
3411 into the delay slot, and increment the branch to jump to
3412 the next instruction. */
3413 insert_into_history (0, 1, ip);
3417 insert_into_history (0, 1, ip);
3420 insert_into_history (0, 1, ip);
3422 /* We just output an insn, so the next one doesn't have a label. */
3423 mips_clear_insn_labels ();
3426 /* Forget that there was any previous instruction or label. */
3429 mips_no_prev_insn (void)
3431 prev_nop_frag = NULL;
3432 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
3433 mips_clear_insn_labels ();
3436 /* This function must be called before we emit something other than
3437 instructions. It is like mips_no_prev_insn except that it inserts
3438 any NOPS that might be needed by previous instructions. */
3441 mips_emit_delays (void)
3443 if (! mips_opts.noreorder)
3445 int nops = nops_for_insn (history, NULL);
3449 add_fixed_insn (NOP_INSN);
3450 mips_move_labels ();
3453 mips_no_prev_insn ();
3456 /* Start a (possibly nested) noreorder block. */
3459 start_noreorder (void)
3461 if (mips_opts.noreorder == 0)
3466 /* None of the instructions before the .set noreorder can be moved. */
3467 for (i = 0; i < ARRAY_SIZE (history); i++)
3468 history[i].fixed_p = 1;
3470 /* Insert any nops that might be needed between the .set noreorder
3471 block and the previous instructions. We will later remove any
3472 nops that turn out not to be needed. */
3473 nops = nops_for_insn (history, NULL);
3476 if (mips_optimize != 0)
3478 /* Record the frag which holds the nop instructions, so
3479 that we can remove them if we don't need them. */
3480 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
3481 prev_nop_frag = frag_now;
3482 prev_nop_frag_holds = nops;
3483 prev_nop_frag_required = 0;
3484 prev_nop_frag_since = 0;
3487 for (; nops > 0; --nops)
3488 add_fixed_insn (NOP_INSN);
3490 /* Move on to a new frag, so that it is safe to simply
3491 decrease the size of prev_nop_frag. */
3492 frag_wane (frag_now);
3494 mips_move_labels ();
3496 mips16_mark_labels ();
3497 mips_clear_insn_labels ();
3499 mips_opts.noreorder++;
3500 mips_any_noreorder = 1;
3503 /* End a nested noreorder block. */
3506 end_noreorder (void)
3509 mips_opts.noreorder--;
3510 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
3512 /* Commit to inserting prev_nop_frag_required nops and go back to
3513 handling nop insertion the .set reorder way. */
3514 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
3515 * (mips_opts.mips16 ? 2 : 4));
3516 insert_into_history (prev_nop_frag_since,
3517 prev_nop_frag_required, NOP_INSN);
3518 prev_nop_frag = NULL;
3522 /* Set up global variables for the start of a new macro. */
3527 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
3528 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
3529 && (history[0].insn_mo->pinfo
3530 & (INSN_UNCOND_BRANCH_DELAY
3531 | INSN_COND_BRANCH_DELAY
3532 | INSN_COND_BRANCH_LIKELY)) != 0);
3535 /* Given that a macro is longer than 4 bytes, return the appropriate warning
3536 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
3537 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
3540 macro_warning (relax_substateT subtype)
3542 if (subtype & RELAX_DELAY_SLOT)
3543 return _("Macro instruction expanded into multiple instructions"
3544 " in a branch delay slot");
3545 else if (subtype & RELAX_NOMACRO)
3546 return _("Macro instruction expanded into multiple instructions");
3551 /* Finish up a macro. Emit warnings as appropriate. */
3556 if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4)
3558 relax_substateT subtype;
3560 /* Set up the relaxation warning flags. */
3562 if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0])
3563 subtype |= RELAX_SECOND_LONGER;
3564 if (mips_opts.warn_about_macros)
3565 subtype |= RELAX_NOMACRO;
3566 if (mips_macro_warning.delay_slot_p)
3567 subtype |= RELAX_DELAY_SLOT;
3569 if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4)
3571 /* Either the macro has a single implementation or both
3572 implementations are longer than 4 bytes. Emit the
3574 const char *msg = macro_warning (subtype);
3576 as_warn ("%s", msg);
3580 /* One implementation might need a warning but the other
3581 definitely doesn't. */
3582 mips_macro_warning.first_frag->fr_subtype |= subtype;
3587 /* Read a macro's relocation codes from *ARGS and store them in *R.
3588 The first argument in *ARGS will be either the code for a single
3589 relocation or -1 followed by the three codes that make up a
3590 composite relocation. */
3593 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
3597 next = va_arg (*args, int);
3599 r[0] = (bfd_reloc_code_real_type) next;
3601 for (i = 0; i < 3; i++)
3602 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
3605 /* Build an instruction created by a macro expansion. This is passed
3606 a pointer to the count of instructions created so far, an
3607 expression, the name of the instruction to build, an operand format
3608 string, and corresponding arguments. */
3611 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
3613 const struct mips_opcode *mo;
3614 struct mips_cl_insn insn;
3615 bfd_reloc_code_real_type r[3];
3618 va_start (args, fmt);
3620 if (mips_opts.mips16)
3622 mips16_macro_build (ep, name, fmt, &args);
3627 r[0] = BFD_RELOC_UNUSED;
3628 r[1] = BFD_RELOC_UNUSED;
3629 r[2] = BFD_RELOC_UNUSED;
3630 mo = (struct mips_opcode *) hash_find (op_hash, name);
3632 gas_assert (strcmp (name, mo->name) == 0);
3636 /* Search until we get a match for NAME. It is assumed here that
3637 macros will never generate MDMX, MIPS-3D, or MT instructions. */
3638 if (strcmp (fmt, mo->args) == 0
3639 && mo->pinfo != INSN_MACRO
3640 && is_opcode_valid (mo))
3644 gas_assert (mo->name);
3645 gas_assert (strcmp (name, mo->name) == 0);
3648 create_insn (&insn, mo);
3666 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
3671 /* Note that in the macro case, these arguments are already
3672 in MSB form. (When handling the instruction in the
3673 non-macro case, these arguments are sizes from which
3674 MSB values must be calculated.) */
3675 INSERT_OPERAND (INSMSB, insn, va_arg (args, int));
3681 /* Note that in the macro case, these arguments are already
3682 in MSBD form. (When handling the instruction in the
3683 non-macro case, these arguments are sizes from which
3684 MSBD values must be calculated.) */
3685 INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int));
3689 INSERT_OPERAND (SEQI, insn, va_arg (args, int));
3698 INSERT_OPERAND (BP, insn, va_arg (args, int));
3704 INSERT_OPERAND (RT, insn, va_arg (args, int));
3708 INSERT_OPERAND (CODE, insn, va_arg (args, int));
3713 INSERT_OPERAND (FT, insn, va_arg (args, int));
3719 INSERT_OPERAND (RD, insn, va_arg (args, int));
3724 int tmp = va_arg (args, int);
3726 INSERT_OPERAND (RT, insn, tmp);
3727 INSERT_OPERAND (RD, insn, tmp);
3733 INSERT_OPERAND (FS, insn, va_arg (args, int));
3740 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
3744 INSERT_OPERAND (FD, insn, va_arg (args, int));
3748 INSERT_OPERAND (CODE20, insn, va_arg (args, int));
3752 INSERT_OPERAND (CODE19, insn, va_arg (args, int));
3756 INSERT_OPERAND (CODE2, insn, va_arg (args, int));
3763 INSERT_OPERAND (RS, insn, va_arg (args, int));
3768 macro_read_relocs (&args, r);
3769 gas_assert (*r == BFD_RELOC_GPREL16
3770 || *r == BFD_RELOC_MIPS_HIGHER
3771 || *r == BFD_RELOC_HI16_S
3772 || *r == BFD_RELOC_LO16
3773 || *r == BFD_RELOC_MIPS_GOT_OFST);
3777 macro_read_relocs (&args, r);
3781 macro_read_relocs (&args, r);
3782 gas_assert (ep != NULL
3783 && (ep->X_op == O_constant
3784 || (ep->X_op == O_symbol
3785 && (*r == BFD_RELOC_MIPS_HIGHEST
3786 || *r == BFD_RELOC_HI16_S
3787 || *r == BFD_RELOC_HI16
3788 || *r == BFD_RELOC_GPREL16
3789 || *r == BFD_RELOC_MIPS_GOT_HI16
3790 || *r == BFD_RELOC_MIPS_CALL_HI16))));
3794 gas_assert (ep != NULL);
3797 * This allows macro() to pass an immediate expression for
3798 * creating short branches without creating a symbol.
3800 * We don't allow branch relaxation for these branches, as
3801 * they should only appear in ".set nomacro" anyway.
3803 if (ep->X_op == O_constant)
3805 if ((ep->X_add_number & 3) != 0)
3806 as_bad (_("branch to misaligned address (0x%lx)"),
3807 (unsigned long) ep->X_add_number);
3808 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
3809 as_bad (_("branch address range overflow (0x%lx)"),
3810 (unsigned long) ep->X_add_number);
3811 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
3815 *r = BFD_RELOC_16_PCREL_S2;
3819 gas_assert (ep != NULL);
3820 *r = BFD_RELOC_MIPS_JMP;
3824 INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long));
3828 INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long));
3837 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3839 append_insn (&insn, ep, r);
3843 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
3846 struct mips_opcode *mo;
3847 struct mips_cl_insn insn;
3848 bfd_reloc_code_real_type r[3]
3849 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3851 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
3853 gas_assert (strcmp (name, mo->name) == 0);
3855 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
3858 gas_assert (mo->name);
3859 gas_assert (strcmp (name, mo->name) == 0);
3862 create_insn (&insn, mo);
3880 MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int));
3885 MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int));
3889 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int));
3893 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int));
3903 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int));
3910 regno = va_arg (*args, int);
3911 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
3912 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
3933 gas_assert (ep != NULL);
3935 if (ep->X_op != O_constant)
3936 *r = (int) BFD_RELOC_UNUSED + c;
3939 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
3940 FALSE, &insn.insn_opcode, &insn.use_extend,
3943 *r = BFD_RELOC_UNUSED;
3949 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int));
3956 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3958 append_insn (&insn, ep, r);
3962 * Sign-extend 32-bit mode constants that have bit 31 set and all
3963 * higher bits unset.
3966 normalize_constant_expr (expressionS *ex)
3968 if (ex->X_op == O_constant
3969 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
3970 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
3975 * Sign-extend 32-bit mode address offsets that have bit 31 set and
3976 * all higher bits unset.
3979 normalize_address_expr (expressionS *ex)
3981 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
3982 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
3983 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
3984 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
3989 * Generate a "jalr" instruction with a relocation hint to the called
3990 * function. This occurs in NewABI PIC code.
3993 macro_build_jalr (expressionS *ep)
3997 if (MIPS_JALR_HINT_P (ep))
4002 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
4003 if (MIPS_JALR_HINT_P (ep))
4004 fix_new_exp (frag_now, f - frag_now->fr_literal,
4005 4, ep, FALSE, BFD_RELOC_MIPS_JALR);
4009 * Generate a "lui" instruction.
4012 macro_build_lui (expressionS *ep, int regnum)
4014 expressionS high_expr;
4015 const struct mips_opcode *mo;
4016 struct mips_cl_insn insn;
4017 bfd_reloc_code_real_type r[3]
4018 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
4019 const char *name = "lui";
4020 const char *fmt = "t,u";
4022 gas_assert (! mips_opts.mips16);
4026 if (high_expr.X_op == O_constant)
4028 /* We can compute the instruction now without a relocation entry. */
4029 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
4031 *r = BFD_RELOC_UNUSED;
4035 gas_assert (ep->X_op == O_symbol);
4036 /* _gp_disp is a special case, used from s_cpload.
4037 __gnu_local_gp is used if mips_no_shared. */
4038 gas_assert (mips_pic == NO_PIC
4040 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
4041 || (! mips_in_shared
4042 && strcmp (S_GET_NAME (ep->X_add_symbol),
4043 "__gnu_local_gp") == 0));
4044 *r = BFD_RELOC_HI16_S;
4047 mo = hash_find (op_hash, name);
4048 gas_assert (strcmp (name, mo->name) == 0);
4049 gas_assert (strcmp (fmt, mo->args) == 0);
4050 create_insn (&insn, mo);
4052 insn.insn_opcode = insn.insn_mo->match;
4053 INSERT_OPERAND (RT, insn, regnum);
4054 if (*r == BFD_RELOC_UNUSED)
4056 insn.insn_opcode |= high_expr.X_add_number;
4057 append_insn (&insn, NULL, r);
4060 append_insn (&insn, &high_expr, r);
4063 /* Generate a sequence of instructions to do a load or store from a constant
4064 offset off of a base register (breg) into/from a target register (treg),
4065 using AT if necessary. */
4067 macro_build_ldst_constoffset (expressionS *ep, const char *op,
4068 int treg, int breg, int dbl)
4070 gas_assert (ep->X_op == O_constant);
4072 /* Sign-extending 32-bit constants makes their handling easier. */
4074 normalize_constant_expr (ep);
4076 /* Right now, this routine can only handle signed 32-bit constants. */
4077 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
4078 as_warn (_("operand overflow"));
4080 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
4082 /* Signed 16-bit offset will fit in the op. Easy! */
4083 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
4087 /* 32-bit offset, need multiple instructions and AT, like:
4088 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
4089 addu $tempreg,$tempreg,$breg
4090 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
4091 to handle the complete offset. */
4092 macro_build_lui (ep, AT);
4093 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
4094 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
4097 as_bad (_("Macro used $at after \".set noat\""));
4102 * Generates code to set the $at register to true (one)
4103 * if reg is less than the immediate expression.
4106 set_at (int reg, int unsignedp)
4108 if (imm_expr.X_op == O_constant
4109 && imm_expr.X_add_number >= -0x8000
4110 && imm_expr.X_add_number < 0x8000)
4111 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
4112 AT, reg, BFD_RELOC_LO16);
4115 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4116 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
4120 /* Warn if an expression is not a constant. */
4123 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
4125 if (ex->X_op == O_big)
4126 as_bad (_("unsupported large constant"));
4127 else if (ex->X_op != O_constant)
4128 as_bad (_("Instruction %s requires absolute expression"),
4131 if (HAVE_32BIT_GPRS)
4132 normalize_constant_expr (ex);
4135 /* Count the leading zeroes by performing a binary chop. This is a
4136 bulky bit of source, but performance is a LOT better for the
4137 majority of values than a simple loop to count the bits:
4138 for (lcnt = 0; (lcnt < 32); lcnt++)
4139 if ((v) & (1 << (31 - lcnt)))
4141 However it is not code size friendly, and the gain will drop a bit
4142 on certain cached systems.
4144 #define COUNT_TOP_ZEROES(v) \
4145 (((v) & ~0xffff) == 0 \
4146 ? ((v) & ~0xff) == 0 \
4147 ? ((v) & ~0xf) == 0 \
4148 ? ((v) & ~0x3) == 0 \
4149 ? ((v) & ~0x1) == 0 \
4154 : ((v) & ~0x7) == 0 \
4157 : ((v) & ~0x3f) == 0 \
4158 ? ((v) & ~0x1f) == 0 \
4161 : ((v) & ~0x7f) == 0 \
4164 : ((v) & ~0xfff) == 0 \
4165 ? ((v) & ~0x3ff) == 0 \
4166 ? ((v) & ~0x1ff) == 0 \
4169 : ((v) & ~0x7ff) == 0 \
4172 : ((v) & ~0x3fff) == 0 \
4173 ? ((v) & ~0x1fff) == 0 \
4176 : ((v) & ~0x7fff) == 0 \
4179 : ((v) & ~0xffffff) == 0 \
4180 ? ((v) & ~0xfffff) == 0 \
4181 ? ((v) & ~0x3ffff) == 0 \
4182 ? ((v) & ~0x1ffff) == 0 \
4185 : ((v) & ~0x7ffff) == 0 \
4188 : ((v) & ~0x3fffff) == 0 \
4189 ? ((v) & ~0x1fffff) == 0 \
4192 : ((v) & ~0x7fffff) == 0 \
4195 : ((v) & ~0xfffffff) == 0 \
4196 ? ((v) & ~0x3ffffff) == 0 \
4197 ? ((v) & ~0x1ffffff) == 0 \
4200 : ((v) & ~0x7ffffff) == 0 \
4203 : ((v) & ~0x3fffffff) == 0 \
4204 ? ((v) & ~0x1fffffff) == 0 \
4207 : ((v) & ~0x7fffffff) == 0 \
4212 * This routine generates the least number of instructions necessary to load
4213 * an absolute expression value into a register.
4216 load_register (int reg, expressionS *ep, int dbl)
4219 expressionS hi32, lo32;
4221 if (ep->X_op != O_big)
4223 gas_assert (ep->X_op == O_constant);
4225 /* Sign-extending 32-bit constants makes their handling easier. */
4227 normalize_constant_expr (ep);
4229 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
4231 /* We can handle 16 bit signed values with an addiu to
4232 $zero. No need to ever use daddiu here, since $zero and
4233 the result are always correct in 32 bit mode. */
4234 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4237 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
4239 /* We can handle 16 bit unsigned values with an ori to
4241 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
4244 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
4246 /* 32 bit values require an lui. */
4247 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16);
4248 if ((ep->X_add_number & 0xffff) != 0)
4249 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
4254 /* The value is larger than 32 bits. */
4256 if (!dbl || HAVE_32BIT_GPRS)
4260 sprintf_vma (value, ep->X_add_number);
4261 as_bad (_("Number (0x%s) larger than 32 bits"), value);
4262 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4266 if (ep->X_op != O_big)
4269 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
4270 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
4271 hi32.X_add_number &= 0xffffffff;
4273 lo32.X_add_number &= 0xffffffff;
4277 gas_assert (ep->X_add_number > 2);
4278 if (ep->X_add_number == 3)
4279 generic_bignum[3] = 0;
4280 else if (ep->X_add_number > 4)
4281 as_bad (_("Number larger than 64 bits"));
4282 lo32.X_op = O_constant;
4283 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
4284 hi32.X_op = O_constant;
4285 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
4288 if (hi32.X_add_number == 0)
4293 unsigned long hi, lo;
4295 if (hi32.X_add_number == (offsetT) 0xffffffff)
4297 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
4299 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4302 if (lo32.X_add_number & 0x80000000)
4304 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
4305 if (lo32.X_add_number & 0xffff)
4306 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
4311 /* Check for 16bit shifted constant. We know that hi32 is
4312 non-zero, so start the mask on the first bit of the hi32
4317 unsigned long himask, lomask;
4321 himask = 0xffff >> (32 - shift);
4322 lomask = (0xffff << shift) & 0xffffffff;
4326 himask = 0xffff << (shift - 32);
4329 if ((hi32.X_add_number & ~(offsetT) himask) == 0
4330 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
4334 tmp.X_op = O_constant;
4336 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
4337 | (lo32.X_add_number >> shift));
4339 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
4340 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
4341 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<",
4342 reg, reg, (shift >= 32) ? shift - 32 : shift);
4347 while (shift <= (64 - 16));
4349 /* Find the bit number of the lowest one bit, and store the
4350 shifted value in hi/lo. */
4351 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
4352 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
4356 while ((lo & 1) == 0)
4361 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
4367 while ((hi & 1) == 0)
4376 /* Optimize if the shifted value is a (power of 2) - 1. */
4377 if ((hi == 0 && ((lo + 1) & lo) == 0)
4378 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
4380 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
4385 /* This instruction will set the register to be all
4387 tmp.X_op = O_constant;
4388 tmp.X_add_number = (offsetT) -1;
4389 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4393 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<",
4394 reg, reg, (bit >= 32) ? bit - 32 : bit);
4396 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<",
4397 reg, reg, (shift >= 32) ? shift - 32 : shift);
4402 /* Sign extend hi32 before calling load_register, because we can
4403 generally get better code when we load a sign extended value. */
4404 if ((hi32.X_add_number & 0x80000000) != 0)
4405 hi32.X_add_number |= ~(offsetT) 0xffffffff;
4406 load_register (reg, &hi32, 0);
4409 if ((lo32.X_add_number & 0xffff0000) == 0)
4413 macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0);
4421 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
4423 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
4424 macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0);
4430 macro_build (NULL, "dsll", "d,w,<", reg, freg, 16);
4434 mid16.X_add_number >>= 16;
4435 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
4436 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4439 if ((lo32.X_add_number & 0xffff) != 0)
4440 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
4444 load_delay_nop (void)
4446 if (!gpr_interlocks)
4447 macro_build (NULL, "nop", "");
4450 /* Load an address into a register. */
4453 load_address (int reg, expressionS *ep, int *used_at)
4455 if (ep->X_op != O_constant
4456 && ep->X_op != O_symbol)
4458 as_bad (_("expression too complex"));
4459 ep->X_op = O_constant;
4462 if (ep->X_op == O_constant)
4464 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
4468 if (mips_pic == NO_PIC)
4470 /* If this is a reference to a GP relative symbol, we want
4471 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4473 lui $reg,<sym> (BFD_RELOC_HI16_S)
4474 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4475 If we have an addend, we always use the latter form.
4477 With 64bit address space and a usable $at we want
4478 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4479 lui $at,<sym> (BFD_RELOC_HI16_S)
4480 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4481 daddiu $at,<sym> (BFD_RELOC_LO16)
4485 If $at is already in use, we use a path which is suboptimal
4486 on superscalar processors.
4487 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4488 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4490 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
4492 daddiu $reg,<sym> (BFD_RELOC_LO16)
4494 For GP relative symbols in 64bit address space we can use
4495 the same sequence as in 32bit address space. */
4496 if (HAVE_64BIT_SYMBOLS)
4498 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
4499 && !nopic_need_relax (ep->X_add_symbol, 1))
4501 relax_start (ep->X_add_symbol);
4502 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4503 mips_gp_register, BFD_RELOC_GPREL16);
4507 if (*used_at == 0 && mips_opts.at)
4509 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
4510 macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S);
4511 macro_build (ep, "daddiu", "t,r,j", reg, reg,
4512 BFD_RELOC_MIPS_HIGHER);
4513 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
4514 macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0);
4515 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
4520 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
4521 macro_build (ep, "daddiu", "t,r,j", reg, reg,
4522 BFD_RELOC_MIPS_HIGHER);
4523 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4524 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
4525 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4526 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
4529 if (mips_relax.sequence)
4534 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
4535 && !nopic_need_relax (ep->X_add_symbol, 1))
4537 relax_start (ep->X_add_symbol);
4538 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4539 mips_gp_register, BFD_RELOC_GPREL16);
4542 macro_build_lui (ep, reg);
4543 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
4544 reg, reg, BFD_RELOC_LO16);
4545 if (mips_relax.sequence)
4549 else if (!mips_big_got)
4553 /* If this is a reference to an external symbol, we want
4554 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4556 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4558 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4559 If there is a constant, it must be added in after.
4561 If we have NewABI, we want
4562 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4563 unless we're referencing a global symbol with a non-zero
4564 offset, in which case cst must be added separately. */
4567 if (ep->X_add_number)
4569 ex.X_add_number = ep->X_add_number;
4570 ep->X_add_number = 0;
4571 relax_start (ep->X_add_symbol);
4572 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4573 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4574 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4575 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4576 ex.X_op = O_constant;
4577 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
4578 reg, reg, BFD_RELOC_LO16);
4579 ep->X_add_number = ex.X_add_number;
4582 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4583 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4584 if (mips_relax.sequence)
4589 ex.X_add_number = ep->X_add_number;
4590 ep->X_add_number = 0;
4591 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4592 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4594 relax_start (ep->X_add_symbol);
4596 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4600 if (ex.X_add_number != 0)
4602 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4603 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4604 ex.X_op = O_constant;
4605 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
4606 reg, reg, BFD_RELOC_LO16);
4610 else if (mips_big_got)
4614 /* This is the large GOT case. If this is a reference to an
4615 external symbol, we want
4616 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4618 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
4620 Otherwise, for a reference to a local symbol in old ABI, we want
4621 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4623 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4624 If there is a constant, it must be added in after.
4626 In the NewABI, for local symbols, with or without offsets, we want:
4627 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4628 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4632 ex.X_add_number = ep->X_add_number;
4633 ep->X_add_number = 0;
4634 relax_start (ep->X_add_symbol);
4635 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4636 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4637 reg, reg, mips_gp_register);
4638 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4639 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4640 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4641 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4642 else if (ex.X_add_number)
4644 ex.X_op = O_constant;
4645 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4649 ep->X_add_number = ex.X_add_number;
4651 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4652 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
4653 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4654 BFD_RELOC_MIPS_GOT_OFST);
4659 ex.X_add_number = ep->X_add_number;
4660 ep->X_add_number = 0;
4661 relax_start (ep->X_add_symbol);
4662 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4663 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4664 reg, reg, mips_gp_register);
4665 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4666 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4668 if (reg_needs_delay (mips_gp_register))
4670 /* We need a nop before loading from $gp. This special
4671 check is required because the lui which starts the main
4672 instruction stream does not refer to $gp, and so will not
4673 insert the nop which may be required. */
4674 macro_build (NULL, "nop", "");
4676 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4677 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4679 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4683 if (ex.X_add_number != 0)
4685 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4686 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4687 ex.X_op = O_constant;
4688 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4696 if (!mips_opts.at && *used_at == 1)
4697 as_bad (_("Macro used $at after \".set noat\""));
4700 /* Move the contents of register SOURCE into register DEST. */
4703 move_register (int dest, int source)
4705 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
4709 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4710 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4711 The two alternatives are:
4713 Global symbol Local sybmol
4714 ------------- ------------
4715 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4717 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4719 load_got_offset emits the first instruction and add_got_offset
4720 emits the second for a 16-bit offset or add_got_offset_hilo emits
4721 a sequence to add a 32-bit offset using a scratch register. */
4724 load_got_offset (int dest, expressionS *local)
4729 global.X_add_number = 0;
4731 relax_start (local->X_add_symbol);
4732 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4733 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4735 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4736 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4741 add_got_offset (int dest, expressionS *local)
4745 global.X_op = O_constant;
4746 global.X_op_symbol = NULL;
4747 global.X_add_symbol = NULL;
4748 global.X_add_number = local->X_add_number;
4750 relax_start (local->X_add_symbol);
4751 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
4752 dest, dest, BFD_RELOC_LO16);
4754 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
4759 add_got_offset_hilo (int dest, expressionS *local, int tmp)
4762 int hold_mips_optimize;
4764 global.X_op = O_constant;
4765 global.X_op_symbol = NULL;
4766 global.X_add_symbol = NULL;
4767 global.X_add_number = local->X_add_number;
4769 relax_start (local->X_add_symbol);
4770 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
4772 /* Set mips_optimize around the lui instruction to avoid
4773 inserting an unnecessary nop after the lw. */
4774 hold_mips_optimize = mips_optimize;
4776 macro_build_lui (&global, tmp);
4777 mips_optimize = hold_mips_optimize;
4778 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
4781 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
4786 * This routine implements the seemingly endless macro or synthesized
4787 * instructions and addressing modes in the mips assembly language. Many
4788 * of these macros are simple and are similar to each other. These could
4789 * probably be handled by some kind of table or grammar approach instead of
4790 * this verbose method. Others are not simple macros but are more like
4791 * optimizing code generation.
4792 * One interesting optimization is when several store macros appear
4793 * consecutively that would load AT with the upper half of the same address.
4794 * The ensuing load upper instructions are ommited. This implies some kind
4795 * of global optimization. We currently only optimize within a single macro.
4796 * For many of the load and store macros if the address is specified as a
4797 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4798 * first load register 'at' with zero and use it as the base register. The
4799 * mips assembler simply uses register $zero. Just one tiny optimization
4803 macro (struct mips_cl_insn *ip)
4805 unsigned int treg, sreg, dreg, breg;
4806 unsigned int tempreg;
4821 bfd_reloc_code_real_type r;
4822 int hold_mips_optimize;
4824 gas_assert (! mips_opts.mips16);
4826 treg = EXTRACT_OPERAND (RT, *ip);
4827 dreg = EXTRACT_OPERAND (RD, *ip);
4828 sreg = breg = EXTRACT_OPERAND (RS, *ip);
4829 mask = ip->insn_mo->mask;
4831 expr1.X_op = O_constant;
4832 expr1.X_op_symbol = NULL;
4833 expr1.X_add_symbol = NULL;
4834 expr1.X_add_number = 1;
4848 expr1.X_add_number = 8;
4849 macro_build (&expr1, "bgez", "s,p", sreg);
4851 macro_build (NULL, "nop", "");
4853 move_register (dreg, sreg);
4854 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
4877 if (imm_expr.X_op == O_constant
4878 && imm_expr.X_add_number >= -0x8000
4879 && imm_expr.X_add_number < 0x8000)
4881 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
4885 load_register (AT, &imm_expr, dbl);
4886 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4905 if (imm_expr.X_op == O_constant
4906 && imm_expr.X_add_number >= 0
4907 && imm_expr.X_add_number < 0x10000)
4909 if (mask != M_NOR_I)
4910 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
4913 macro_build (&imm_expr, "ori", "t,r,i",
4914 treg, sreg, BFD_RELOC_LO16);
4915 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
4921 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4922 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4926 switch (imm_expr.X_add_number)
4929 macro_build (NULL, "nop", "");
4932 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
4935 macro_build (NULL, "balign", "t,s,2", treg, sreg,
4936 (int) imm_expr.X_add_number);
4955 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4957 macro_build (&offset_expr, s, "s,t,p", sreg, ZERO);
4961 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4962 macro_build (&offset_expr, s, "s,t,p", sreg, AT);
4970 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
4975 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg);
4979 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
4980 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
4986 /* Check for > max integer. */
4987 maxnum = 0x7fffffff;
4988 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4995 if (imm_expr.X_op == O_constant
4996 && imm_expr.X_add_number >= maxnum
4997 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5000 /* Result is always false. */
5002 macro_build (NULL, "nop", "");
5004 macro_build (&offset_expr, "bnel", "s,t,p", ZERO, ZERO);
5007 if (imm_expr.X_op != O_constant)
5008 as_bad (_("Unsupported large constant"));
5009 ++imm_expr.X_add_number;
5013 if (mask == M_BGEL_I)
5015 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5017 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
5020 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5022 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
5025 maxnum = 0x7fffffff;
5026 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5033 maxnum = - maxnum - 1;
5034 if (imm_expr.X_op == O_constant
5035 && imm_expr.X_add_number <= maxnum
5036 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5039 /* result is always true */
5040 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
5041 macro_build (&offset_expr, "b", "p");
5046 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5056 macro_build (&offset_expr, likely ? "beql" : "beq",
5057 "s,t,p", ZERO, treg);
5061 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
5062 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5070 && imm_expr.X_op == O_constant
5071 && imm_expr.X_add_number == -1))
5073 if (imm_expr.X_op != O_constant)
5074 as_bad (_("Unsupported large constant"));
5075 ++imm_expr.X_add_number;
5079 if (mask == M_BGEUL_I)
5081 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5083 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5085 macro_build (&offset_expr, likely ? "bnel" : "bne",
5086 "s,t,p", sreg, ZERO);
5091 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5099 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
5104 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg);
5108 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
5109 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5117 macro_build (&offset_expr, likely ? "bnel" : "bne",
5118 "s,t,p", sreg, ZERO);
5124 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
5125 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5133 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
5138 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg);
5142 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
5143 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5149 maxnum = 0x7fffffff;
5150 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5157 if (imm_expr.X_op == O_constant
5158 && imm_expr.X_add_number >= maxnum
5159 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5161 if (imm_expr.X_op != O_constant)
5162 as_bad (_("Unsupported large constant"));
5163 ++imm_expr.X_add_number;
5167 if (mask == M_BLTL_I)
5169 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5171 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
5174 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5176 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
5181 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5189 macro_build (&offset_expr, likely ? "beql" : "beq",
5190 "s,t,p", sreg, ZERO);
5196 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
5197 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5205 && imm_expr.X_op == O_constant
5206 && imm_expr.X_add_number == -1))
5208 if (imm_expr.X_op != O_constant)
5209 as_bad (_("Unsupported large constant"));
5210 ++imm_expr.X_add_number;
5214 if (mask == M_BLTUL_I)
5216 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5218 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5220 macro_build (&offset_expr, likely ? "beql" : "beq",
5221 "s,t,p", sreg, ZERO);
5226 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5234 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
5239 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg);
5243 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
5244 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5254 macro_build (&offset_expr, likely ? "bnel" : "bne",
5255 "s,t,p", ZERO, treg);
5259 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
5260 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5268 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5270 as_bad (_("Unsupported large constant"));
5275 pos = (unsigned long) imm_expr.X_add_number;
5276 size = (unsigned long) imm2_expr.X_add_number;
5281 as_bad (_("Improper position (%lu)"), pos);
5284 if (size == 0 || size > 64 || (pos + size - 1) > 63)
5286 as_bad (_("Improper extract size (%lu, position %lu)"),
5291 if (size <= 32 && pos < 32)
5296 else if (size <= 32)
5306 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1);
5315 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5317 as_bad (_("Unsupported large constant"));
5322 pos = (unsigned long) imm_expr.X_add_number;
5323 size = (unsigned long) imm2_expr.X_add_number;
5328 as_bad (_("Improper position (%lu)"), pos);
5331 if (size == 0 || size > 64 || (pos + size - 1) > 63)
5333 as_bad (_("Improper insert size (%lu, position %lu)"),
5338 if (pos < 32 && (pos + size - 1) < 32)
5353 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
5354 (int) (pos + size - 1));
5370 as_warn (_("Divide by zero."));
5372 macro_build (NULL, "teq", "s,t,q", ZERO, ZERO, 7);
5374 macro_build (NULL, "break", "c", 7);
5381 macro_build (NULL, "teq", "s,t,q", treg, ZERO, 7);
5382 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
5386 expr1.X_add_number = 8;
5387 macro_build (&expr1, "bne", "s,t,p", treg, ZERO);
5388 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
5389 macro_build (NULL, "break", "c", 7);
5391 expr1.X_add_number = -1;
5393 load_register (AT, &expr1, dbl);
5394 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
5395 macro_build (&expr1, "bne", "s,t,p", treg, AT);
5398 expr1.X_add_number = 1;
5399 load_register (AT, &expr1, dbl);
5400 macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31);
5404 expr1.X_add_number = 0x80000000;
5405 macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16);
5409 macro_build (NULL, "teq", "s,t,q", sreg, AT, 6);
5410 /* We want to close the noreorder block as soon as possible, so
5411 that later insns are available for delay slot filling. */
5416 expr1.X_add_number = 8;
5417 macro_build (&expr1, "bne", "s,t,p", sreg, AT);
5418 macro_build (NULL, "nop", "");
5420 /* We want to close the noreorder block as soon as possible, so
5421 that later insns are available for delay slot filling. */
5424 macro_build (NULL, "break", "c", 6);
5426 macro_build (NULL, s, "d", dreg);
5465 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5467 as_warn (_("Divide by zero."));
5469 macro_build (NULL, "teq", "s,t,q", ZERO, ZERO, 7);
5471 macro_build (NULL, "break", "c", 7);
5474 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5476 if (strcmp (s2, "mflo") == 0)
5477 move_register (dreg, sreg);
5479 move_register (dreg, ZERO);
5482 if (imm_expr.X_op == O_constant
5483 && imm_expr.X_add_number == -1
5484 && s[strlen (s) - 1] != 'u')
5486 if (strcmp (s2, "mflo") == 0)
5488 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
5491 move_register (dreg, ZERO);
5496 load_register (AT, &imm_expr, dbl);
5497 macro_build (NULL, s, "z,s,t", sreg, AT);
5498 macro_build (NULL, s2, "d", dreg);
5520 macro_build (NULL, "teq", "s,t,q", treg, ZERO, 7);
5521 macro_build (NULL, s, "z,s,t", sreg, treg);
5522 /* We want to close the noreorder block as soon as possible, so
5523 that later insns are available for delay slot filling. */
5528 expr1.X_add_number = 8;
5529 macro_build (&expr1, "bne", "s,t,p", treg, ZERO);
5530 macro_build (NULL, s, "z,s,t", sreg, treg);
5532 /* We want to close the noreorder block as soon as possible, so
5533 that later insns are available for delay slot filling. */
5535 macro_build (NULL, "break", "c", 7);
5537 macro_build (NULL, s2, "d", dreg);
5549 /* Load the address of a symbol into a register. If breg is not
5550 zero, we then add a base register to it. */
5552 if (dbl && HAVE_32BIT_GPRS)
5553 as_warn (_("dla used to load 32-bit register"));
5555 if (!dbl && HAVE_64BIT_OBJECTS)
5556 as_warn (_("la used to load 64-bit address"));
5558 if (offset_expr.X_op == O_constant
5559 && offset_expr.X_add_number >= -0x8000
5560 && offset_expr.X_add_number < 0x8000)
5562 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
5563 "t,r,j", treg, sreg, BFD_RELOC_LO16);
5567 if (mips_opts.at && (treg == breg))
5577 if (offset_expr.X_op != O_symbol
5578 && offset_expr.X_op != O_constant)
5580 as_bad (_("Expression too complex"));
5581 offset_expr.X_op = O_constant;
5584 if (offset_expr.X_op == O_constant)
5585 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
5586 else if (mips_pic == NO_PIC)
5588 /* If this is a reference to a GP relative symbol, we want
5589 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5591 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5592 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5593 If we have a constant, we need two instructions anyhow,
5594 so we may as well always use the latter form.
5596 With 64bit address space and a usable $at we want
5597 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5598 lui $at,<sym> (BFD_RELOC_HI16_S)
5599 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5600 daddiu $at,<sym> (BFD_RELOC_LO16)
5602 daddu $tempreg,$tempreg,$at
5604 If $at is already in use, we use a path which is suboptimal
5605 on superscalar processors.
5606 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5607 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5609 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5611 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
5613 For GP relative symbols in 64bit address space we can use
5614 the same sequence as in 32bit address space. */
5615 if (HAVE_64BIT_SYMBOLS)
5617 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5618 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5620 relax_start (offset_expr.X_add_symbol);
5621 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5622 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5626 if (used_at == 0 && mips_opts.at)
5628 macro_build (&offset_expr, "lui", "t,u",
5629 tempreg, BFD_RELOC_MIPS_HIGHEST);
5630 macro_build (&offset_expr, "lui", "t,u",
5631 AT, BFD_RELOC_HI16_S);
5632 macro_build (&offset_expr, "daddiu", "t,r,j",
5633 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5634 macro_build (&offset_expr, "daddiu", "t,r,j",
5635 AT, AT, BFD_RELOC_LO16);
5636 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
5637 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
5642 macro_build (&offset_expr, "lui", "t,u",
5643 tempreg, BFD_RELOC_MIPS_HIGHEST);
5644 macro_build (&offset_expr, "daddiu", "t,r,j",
5645 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5646 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5647 macro_build (&offset_expr, "daddiu", "t,r,j",
5648 tempreg, tempreg, BFD_RELOC_HI16_S);
5649 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5650 macro_build (&offset_expr, "daddiu", "t,r,j",
5651 tempreg, tempreg, BFD_RELOC_LO16);
5654 if (mips_relax.sequence)
5659 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5660 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5662 relax_start (offset_expr.X_add_symbol);
5663 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5664 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5667 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
5668 as_bad (_("Offset too large"));
5669 macro_build_lui (&offset_expr, tempreg);
5670 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5671 tempreg, tempreg, BFD_RELOC_LO16);
5672 if (mips_relax.sequence)
5676 else if (!mips_big_got && !HAVE_NEWABI)
5678 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5680 /* If this is a reference to an external symbol, and there
5681 is no constant, we want
5682 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5683 or for lca or if tempreg is PIC_CALL_REG
5684 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5685 For a local symbol, we want
5686 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5688 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5690 If we have a small constant, and this is a reference to
5691 an external symbol, we want
5692 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5694 addiu $tempreg,$tempreg,<constant>
5695 For a local symbol, we want the same instruction
5696 sequence, but we output a BFD_RELOC_LO16 reloc on the
5699 If we have a large constant, and this is a reference to
5700 an external symbol, we want
5701 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5702 lui $at,<hiconstant>
5703 addiu $at,$at,<loconstant>
5704 addu $tempreg,$tempreg,$at
5705 For a local symbol, we want the same instruction
5706 sequence, but we output a BFD_RELOC_LO16 reloc on the
5710 if (offset_expr.X_add_number == 0)
5712 if (mips_pic == SVR4_PIC
5714 && (call || tempreg == PIC_CALL_REG))
5715 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
5717 relax_start (offset_expr.X_add_symbol);
5718 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5719 lw_reloc_type, mips_gp_register);
5722 /* We're going to put in an addu instruction using
5723 tempreg, so we may as well insert the nop right
5728 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5729 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
5731 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5732 tempreg, tempreg, BFD_RELOC_LO16);
5734 /* FIXME: If breg == 0, and the next instruction uses
5735 $tempreg, then if this variant case is used an extra
5736 nop will be generated. */
5738 else if (offset_expr.X_add_number >= -0x8000
5739 && offset_expr.X_add_number < 0x8000)
5741 load_got_offset (tempreg, &offset_expr);
5743 add_got_offset (tempreg, &offset_expr);
5747 expr1.X_add_number = offset_expr.X_add_number;
5748 offset_expr.X_add_number =
5749 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
5750 load_got_offset (tempreg, &offset_expr);
5751 offset_expr.X_add_number = expr1.X_add_number;
5752 /* If we are going to add in a base register, and the
5753 target register and the base register are the same,
5754 then we are using AT as a temporary register. Since
5755 we want to load the constant into AT, we add our
5756 current AT (from the global offset table) and the
5757 register into the register now, and pretend we were
5758 not using a base register. */
5762 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5767 add_got_offset_hilo (tempreg, &offset_expr, AT);
5771 else if (!mips_big_got && HAVE_NEWABI)
5773 int add_breg_early = 0;
5775 /* If this is a reference to an external, and there is no
5776 constant, or local symbol (*), with or without a
5778 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5779 or for lca or if tempreg is PIC_CALL_REG
5780 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5782 If we have a small constant, and this is a reference to
5783 an external symbol, we want
5784 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5785 addiu $tempreg,$tempreg,<constant>
5787 If we have a large constant, and this is a reference to
5788 an external symbol, we want
5789 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5790 lui $at,<hiconstant>
5791 addiu $at,$at,<loconstant>
5792 addu $tempreg,$tempreg,$at
5794 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5795 local symbols, even though it introduces an additional
5798 if (offset_expr.X_add_number)
5800 expr1.X_add_number = offset_expr.X_add_number;
5801 offset_expr.X_add_number = 0;
5803 relax_start (offset_expr.X_add_symbol);
5804 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5805 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5807 if (expr1.X_add_number >= -0x8000
5808 && expr1.X_add_number < 0x8000)
5810 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5811 tempreg, tempreg, BFD_RELOC_LO16);
5813 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
5815 /* If we are going to add in a base register, and the
5816 target register and the base register are the same,
5817 then we are using AT as a temporary register. Since
5818 we want to load the constant into AT, we add our
5819 current AT (from the global offset table) and the
5820 register into the register now, and pretend we were
5821 not using a base register. */
5826 gas_assert (tempreg == AT);
5827 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5833 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5834 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5840 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5843 offset_expr.X_add_number = expr1.X_add_number;
5845 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5846 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5849 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5850 treg, tempreg, breg);
5856 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
5858 relax_start (offset_expr.X_add_symbol);
5859 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5860 BFD_RELOC_MIPS_CALL16, mips_gp_register);
5862 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5863 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5868 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5869 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5872 else if (mips_big_got && !HAVE_NEWABI)
5875 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5876 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5877 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5879 /* This is the large GOT case. If this is a reference to an
5880 external symbol, and there is no constant, we want
5881 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5882 addu $tempreg,$tempreg,$gp
5883 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5884 or for lca or if tempreg is PIC_CALL_REG
5885 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5886 addu $tempreg,$tempreg,$gp
5887 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5888 For a local symbol, we want
5889 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5891 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5893 If we have a small constant, and this is a reference to
5894 an external symbol, we want
5895 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5896 addu $tempreg,$tempreg,$gp
5897 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5899 addiu $tempreg,$tempreg,<constant>
5900 For a local symbol, we want
5901 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5903 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5905 If we have a large constant, and this is a reference to
5906 an external symbol, we want
5907 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5908 addu $tempreg,$tempreg,$gp
5909 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5910 lui $at,<hiconstant>
5911 addiu $at,$at,<loconstant>
5912 addu $tempreg,$tempreg,$at
5913 For a local symbol, we want
5914 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5915 lui $at,<hiconstant>
5916 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5917 addu $tempreg,$tempreg,$at
5920 expr1.X_add_number = offset_expr.X_add_number;
5921 offset_expr.X_add_number = 0;
5922 relax_start (offset_expr.X_add_symbol);
5923 gpdelay = reg_needs_delay (mips_gp_register);
5924 if (expr1.X_add_number == 0 && breg == 0
5925 && (call || tempreg == PIC_CALL_REG))
5927 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5928 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5930 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
5931 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5932 tempreg, tempreg, mips_gp_register);
5933 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5934 tempreg, lw_reloc_type, tempreg);
5935 if (expr1.X_add_number == 0)
5939 /* We're going to put in an addu instruction using
5940 tempreg, so we may as well insert the nop right
5945 else if (expr1.X_add_number >= -0x8000
5946 && expr1.X_add_number < 0x8000)
5949 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5950 tempreg, tempreg, BFD_RELOC_LO16);
5954 /* If we are going to add in a base register, and the
5955 target register and the base register are the same,
5956 then we are using AT as a temporary register. Since
5957 we want to load the constant into AT, we add our
5958 current AT (from the global offset table) and the
5959 register into the register now, and pretend we were
5960 not using a base register. */
5965 gas_assert (tempreg == AT);
5967 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5972 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5973 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
5977 offset_expr.X_add_number =
5978 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000;
5983 /* This is needed because this instruction uses $gp, but
5984 the first instruction on the main stream does not. */
5985 macro_build (NULL, "nop", "");
5988 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5989 local_reloc_type, mips_gp_register);
5990 if (expr1.X_add_number >= -0x8000
5991 && expr1.X_add_number < 0x8000)
5994 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5995 tempreg, tempreg, BFD_RELOC_LO16);
5996 /* FIXME: If add_number is 0, and there was no base
5997 register, the external symbol case ended with a load,
5998 so if the symbol turns out to not be external, and
5999 the next instruction uses tempreg, an unnecessary nop
6000 will be inserted. */
6006 /* We must add in the base register now, as in the
6007 external symbol case. */
6008 gas_assert (tempreg == AT);
6010 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6013 /* We set breg to 0 because we have arranged to add
6014 it in in both cases. */
6018 macro_build_lui (&expr1, AT);
6019 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6020 AT, AT, BFD_RELOC_LO16);
6021 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6022 tempreg, tempreg, AT);
6027 else if (mips_big_got && HAVE_NEWABI)
6029 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
6030 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
6031 int add_breg_early = 0;
6033 /* This is the large GOT case. If this is a reference to an
6034 external symbol, and there is no constant, we want
6035 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6036 add $tempreg,$tempreg,$gp
6037 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6038 or for lca or if tempreg is PIC_CALL_REG
6039 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6040 add $tempreg,$tempreg,$gp
6041 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
6043 If we have a small constant, and this is a reference to
6044 an external symbol, we want
6045 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6046 add $tempreg,$tempreg,$gp
6047 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6048 addi $tempreg,$tempreg,<constant>
6050 If we have a large constant, and this is a reference to
6051 an external symbol, we want
6052 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6053 addu $tempreg,$tempreg,$gp
6054 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6055 lui $at,<hiconstant>
6056 addi $at,$at,<loconstant>
6057 add $tempreg,$tempreg,$at
6059 If we have NewABI, and we know it's a local symbol, we want
6060 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6061 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6062 otherwise we have to resort to GOT_HI16/GOT_LO16. */
6064 relax_start (offset_expr.X_add_symbol);
6066 expr1.X_add_number = offset_expr.X_add_number;
6067 offset_expr.X_add_number = 0;
6069 if (expr1.X_add_number == 0 && breg == 0
6070 && (call || tempreg == PIC_CALL_REG))
6072 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
6073 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
6075 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
6076 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6077 tempreg, tempreg, mips_gp_register);
6078 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6079 tempreg, lw_reloc_type, tempreg);
6081 if (expr1.X_add_number == 0)
6083 else if (expr1.X_add_number >= -0x8000
6084 && expr1.X_add_number < 0x8000)
6086 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
6087 tempreg, tempreg, BFD_RELOC_LO16);
6089 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
6091 /* If we are going to add in a base register, and the
6092 target register and the base register are the same,
6093 then we are using AT as a temporary register. Since
6094 we want to load the constant into AT, we add our
6095 current AT (from the global offset table) and the
6096 register into the register now, and pretend we were
6097 not using a base register. */
6102 gas_assert (tempreg == AT);
6103 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6109 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
6110 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
6115 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
6118 offset_expr.X_add_number = expr1.X_add_number;
6119 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6120 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6121 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6122 tempreg, BFD_RELOC_MIPS_GOT_OFST);
6125 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6126 treg, tempreg, breg);
6136 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
6141 unsigned long temp = (treg << 16) | (0x01);
6142 macro_build (NULL, "c2", "C", temp);
6144 /* AT is not used, just return */
6149 unsigned long temp = (0x02);
6150 macro_build (NULL, "c2", "C", temp);
6152 /* AT is not used, just return */
6157 unsigned long temp = (treg << 16) | (0x02);
6158 macro_build (NULL, "c2", "C", temp);
6160 /* AT is not used, just return */
6164 macro_build (NULL, "c2", "C", 3);
6165 /* AT is not used, just return */
6170 unsigned long temp = (treg << 16) | 0x03;
6171 macro_build (NULL, "c2", "C", temp);
6173 /* AT is not used, just return */
6177 /* The j instruction may not be used in PIC code, since it
6178 requires an absolute address. We convert it to a b
6180 if (mips_pic == NO_PIC)
6181 macro_build (&offset_expr, "j", "a");
6183 macro_build (&offset_expr, "b", "p");
6186 /* The jal instructions must be handled as macros because when
6187 generating PIC code they expand to multi-instruction
6188 sequences. Normally they are simple instructions. */
6193 if (mips_pic == NO_PIC)
6194 macro_build (NULL, "jalr", "d,s", dreg, sreg);
6197 if (sreg != PIC_CALL_REG)
6198 as_warn (_("MIPS PIC call to register other than $25"));
6200 macro_build (NULL, "jalr", "d,s", dreg, sreg);
6201 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
6203 if (mips_cprestore_offset < 0)
6204 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6207 if (!mips_frame_reg_valid)
6209 as_warn (_("No .frame pseudo-op used in PIC code"));
6210 /* Quiet this warning. */
6211 mips_frame_reg_valid = 1;
6213 if (!mips_cprestore_valid)
6215 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6216 /* Quiet this warning. */
6217 mips_cprestore_valid = 1;
6219 if (mips_opts.noreorder)
6220 macro_build (NULL, "nop", "");
6221 expr1.X_add_number = mips_cprestore_offset;
6222 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
6225 HAVE_64BIT_ADDRESSES);
6233 if (mips_pic == NO_PIC)
6234 macro_build (&offset_expr, "jal", "a");
6235 else if (mips_pic == SVR4_PIC)
6237 /* If this is a reference to an external symbol, and we are
6238 using a small GOT, we want
6239 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
6243 lw $gp,cprestore($sp)
6244 The cprestore value is set using the .cprestore
6245 pseudo-op. If we are using a big GOT, we want
6246 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6248 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
6252 lw $gp,cprestore($sp)
6253 If the symbol is not external, we want
6254 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6256 addiu $25,$25,<sym> (BFD_RELOC_LO16)
6259 lw $gp,cprestore($sp)
6261 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
6262 sequences above, minus nops, unless the symbol is local,
6263 which enables us to use GOT_PAGE/GOT_OFST (big got) or
6269 relax_start (offset_expr.X_add_symbol);
6270 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6271 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
6274 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6275 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
6281 relax_start (offset_expr.X_add_symbol);
6282 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
6283 BFD_RELOC_MIPS_CALL_HI16);
6284 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
6285 PIC_CALL_REG, mips_gp_register);
6286 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6287 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
6290 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6291 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
6293 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6294 PIC_CALL_REG, PIC_CALL_REG,
6295 BFD_RELOC_MIPS_GOT_OFST);
6299 macro_build_jalr (&offset_expr);
6303 relax_start (offset_expr.X_add_symbol);
6306 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6307 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
6316 gpdelay = reg_needs_delay (mips_gp_register);
6317 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
6318 BFD_RELOC_MIPS_CALL_HI16);
6319 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
6320 PIC_CALL_REG, mips_gp_register);
6321 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6322 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
6327 macro_build (NULL, "nop", "");
6329 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6330 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
6333 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6334 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
6336 macro_build_jalr (&offset_expr);
6338 if (mips_cprestore_offset < 0)
6339 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6342 if (!mips_frame_reg_valid)
6344 as_warn (_("No .frame pseudo-op used in PIC code"));
6345 /* Quiet this warning. */
6346 mips_frame_reg_valid = 1;
6348 if (!mips_cprestore_valid)
6350 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6351 /* Quiet this warning. */
6352 mips_cprestore_valid = 1;
6354 if (mips_opts.noreorder)
6355 macro_build (NULL, "nop", "");
6356 expr1.X_add_number = mips_cprestore_offset;
6357 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
6360 HAVE_64BIT_ADDRESSES);
6364 else if (mips_pic == VXWORKS_PIC)
6365 as_bad (_("Non-PIC jump used in PIC library"));
6388 /* Itbl support may require additional care here. */
6393 /* Itbl support may require additional care here. */
6398 /* Itbl support may require additional care here. */
6403 /* Itbl support may require additional care here. */
6416 /* Itbl support may require additional care here. */
6421 /* Itbl support may require additional care here. */
6426 /* Itbl support may require additional care here. */
6446 if (breg == treg || coproc || lr)
6467 /* Itbl support may require additional care here. */
6472 /* Itbl support may require additional care here. */
6477 /* Itbl support may require additional care here. */
6482 /* Itbl support may require additional care here. */
6503 /* Itbl support may require additional care here. */
6507 /* Itbl support may require additional care here. */
6512 /* Itbl support may require additional care here. */
6525 && NO_ISA_COP (mips_opts.arch)
6526 && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0)
6528 as_bad (_("Opcode not supported on this processor: %s"),
6529 mips_cpu_info_from_arch (mips_opts.arch)->name);
6533 /* Itbl support may require additional care here. */
6534 if (mask == M_LWC1_AB
6535 || mask == M_SWC1_AB
6536 || mask == M_LDC1_AB
6537 || mask == M_SDC1_AB
6541 else if (mask == M_CACHE_AB)
6548 if (offset_expr.X_op != O_constant
6549 && offset_expr.X_op != O_symbol)
6551 as_bad (_("Expression too complex"));
6552 offset_expr.X_op = O_constant;
6555 if (HAVE_32BIT_ADDRESSES
6556 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
6560 sprintf_vma (value, offset_expr.X_add_number);
6561 as_bad (_("Number (0x%s) larger than 32 bits"), value);
6564 /* A constant expression in PIC code can be handled just as it
6565 is in non PIC code. */
6566 if (offset_expr.X_op == O_constant)
6568 expr1.X_add_number = ((offset_expr.X_add_number + 0x8000)
6569 & ~(bfd_vma) 0xffff);
6570 normalize_address_expr (&expr1);
6571 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
6573 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6574 tempreg, tempreg, breg);
6575 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6577 else if (mips_pic == NO_PIC)
6579 /* If this is a reference to a GP relative symbol, and there
6580 is no base register, we want
6581 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6582 Otherwise, if there is no base register, we want
6583 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6584 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6585 If we have a constant, we need two instructions anyhow,
6586 so we always use the latter form.
6588 If we have a base register, and this is a reference to a
6589 GP relative symbol, we want
6590 addu $tempreg,$breg,$gp
6591 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6593 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6594 addu $tempreg,$tempreg,$breg
6595 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6596 With a constant we always use the latter case.
6598 With 64bit address space and no base register and $at usable,
6600 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6601 lui $at,<sym> (BFD_RELOC_HI16_S)
6602 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6605 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6606 If we have a base register, we want
6607 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6608 lui $at,<sym> (BFD_RELOC_HI16_S)
6609 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6613 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6615 Without $at we can't generate the optimal path for superscalar
6616 processors here since this would require two temporary registers.
6617 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6618 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6620 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6622 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6623 If we have a base register, we want
6624 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6625 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6627 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6629 daddu $tempreg,$tempreg,$breg
6630 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6632 For GP relative symbols in 64bit address space we can use
6633 the same sequence as in 32bit address space. */
6634 if (HAVE_64BIT_SYMBOLS)
6636 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6637 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6639 relax_start (offset_expr.X_add_symbol);
6642 macro_build (&offset_expr, s, fmt, treg,
6643 BFD_RELOC_GPREL16, mips_gp_register);
6647 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6648 tempreg, breg, mips_gp_register);
6649 macro_build (&offset_expr, s, fmt, treg,
6650 BFD_RELOC_GPREL16, tempreg);
6655 if (used_at == 0 && mips_opts.at)
6657 macro_build (&offset_expr, "lui", "t,u", tempreg,
6658 BFD_RELOC_MIPS_HIGHEST);
6659 macro_build (&offset_expr, "lui", "t,u", AT,
6661 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6662 tempreg, BFD_RELOC_MIPS_HIGHER);
6664 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
6665 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
6666 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
6667 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
6673 macro_build (&offset_expr, "lui", "t,u", tempreg,
6674 BFD_RELOC_MIPS_HIGHEST);
6675 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6676 tempreg, BFD_RELOC_MIPS_HIGHER);
6677 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6678 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6679 tempreg, BFD_RELOC_HI16_S);
6680 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6682 macro_build (NULL, "daddu", "d,v,t",
6683 tempreg, tempreg, breg);
6684 macro_build (&offset_expr, s, fmt, treg,
6685 BFD_RELOC_LO16, tempreg);
6688 if (mips_relax.sequence)
6695 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6696 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6698 relax_start (offset_expr.X_add_symbol);
6699 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
6703 macro_build_lui (&offset_expr, tempreg);
6704 macro_build (&offset_expr, s, fmt, treg,
6705 BFD_RELOC_LO16, tempreg);
6706 if (mips_relax.sequence)
6711 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6712 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6714 relax_start (offset_expr.X_add_symbol);
6715 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6716 tempreg, breg, mips_gp_register);
6717 macro_build (&offset_expr, s, fmt, treg,
6718 BFD_RELOC_GPREL16, tempreg);
6721 macro_build_lui (&offset_expr, tempreg);
6722 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6723 tempreg, tempreg, breg);
6724 macro_build (&offset_expr, s, fmt, treg,
6725 BFD_RELOC_LO16, tempreg);
6726 if (mips_relax.sequence)
6730 else if (!mips_big_got)
6732 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6734 /* If this is a reference to an external symbol, we want
6735 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6737 <op> $treg,0($tempreg)
6739 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6741 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6742 <op> $treg,0($tempreg)
6745 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6746 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6748 If there is a base register, we add it to $tempreg before
6749 the <op>. If there is a constant, we stick it in the
6750 <op> instruction. We don't handle constants larger than
6751 16 bits, because we have no way to load the upper 16 bits
6752 (actually, we could handle them for the subset of cases
6753 in which we are not using $at). */
6754 gas_assert (offset_expr.X_op == O_symbol);
6757 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6758 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6760 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6761 tempreg, tempreg, breg);
6762 macro_build (&offset_expr, s, fmt, treg,
6763 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6766 expr1.X_add_number = offset_expr.X_add_number;
6767 offset_expr.X_add_number = 0;
6768 if (expr1.X_add_number < -0x8000
6769 || expr1.X_add_number >= 0x8000)
6770 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6771 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6772 lw_reloc_type, mips_gp_register);
6774 relax_start (offset_expr.X_add_symbol);
6776 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6777 tempreg, BFD_RELOC_LO16);
6780 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6781 tempreg, tempreg, breg);
6782 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6784 else if (mips_big_got && !HAVE_NEWABI)
6788 /* If this is a reference to an external symbol, we want
6789 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6790 addu $tempreg,$tempreg,$gp
6791 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6792 <op> $treg,0($tempreg)
6794 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6796 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6797 <op> $treg,0($tempreg)
6798 If there is a base register, we add it to $tempreg before
6799 the <op>. If there is a constant, we stick it in the
6800 <op> instruction. We don't handle constants larger than
6801 16 bits, because we have no way to load the upper 16 bits
6802 (actually, we could handle them for the subset of cases
6803 in which we are not using $at). */
6804 gas_assert (offset_expr.X_op == O_symbol);
6805 expr1.X_add_number = offset_expr.X_add_number;
6806 offset_expr.X_add_number = 0;
6807 if (expr1.X_add_number < -0x8000
6808 || expr1.X_add_number >= 0x8000)
6809 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6810 gpdelay = reg_needs_delay (mips_gp_register);
6811 relax_start (offset_expr.X_add_symbol);
6812 macro_build (&offset_expr, "lui", "t,u", tempreg,
6813 BFD_RELOC_MIPS_GOT_HI16);
6814 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
6816 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6817 BFD_RELOC_MIPS_GOT_LO16, tempreg);
6820 macro_build (NULL, "nop", "");
6821 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6822 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6824 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6825 tempreg, BFD_RELOC_LO16);
6829 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6830 tempreg, tempreg, breg);
6831 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6833 else if (mips_big_got && HAVE_NEWABI)
6835 /* If this is a reference to an external symbol, we want
6836 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6837 add $tempreg,$tempreg,$gp
6838 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6839 <op> $treg,<ofst>($tempreg)
6840 Otherwise, for local symbols, we want:
6841 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6842 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6843 gas_assert (offset_expr.X_op == O_symbol);
6844 expr1.X_add_number = offset_expr.X_add_number;
6845 offset_expr.X_add_number = 0;
6846 if (expr1.X_add_number < -0x8000
6847 || expr1.X_add_number >= 0x8000)
6848 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6849 relax_start (offset_expr.X_add_symbol);
6850 macro_build (&offset_expr, "lui", "t,u", tempreg,
6851 BFD_RELOC_MIPS_GOT_HI16);
6852 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
6854 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6855 BFD_RELOC_MIPS_GOT_LO16, tempreg);
6857 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6858 tempreg, tempreg, breg);
6859 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6862 offset_expr.X_add_number = expr1.X_add_number;
6863 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6864 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6866 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6867 tempreg, tempreg, breg);
6868 macro_build (&offset_expr, s, fmt, treg,
6869 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6879 load_register (treg, &imm_expr, 0);
6883 load_register (treg, &imm_expr, 1);
6887 if (imm_expr.X_op == O_constant)
6890 load_register (AT, &imm_expr, 0);
6891 macro_build (NULL, "mtc1", "t,G", AT, treg);
6896 gas_assert (offset_expr.X_op == O_symbol
6897 && strcmp (segment_name (S_GET_SEGMENT
6898 (offset_expr.X_add_symbol)),
6900 && offset_expr.X_add_number == 0);
6901 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
6902 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6907 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6908 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6909 order 32 bits of the value and the low order 32 bits are either
6910 zero or in OFFSET_EXPR. */
6911 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6913 if (HAVE_64BIT_GPRS)
6914 load_register (treg, &imm_expr, 1);
6919 if (target_big_endian)
6931 load_register (hreg, &imm_expr, 0);
6934 if (offset_expr.X_op == O_absent)
6935 move_register (lreg, 0);
6938 gas_assert (offset_expr.X_op == O_constant);
6939 load_register (lreg, &offset_expr, 0);
6946 /* We know that sym is in the .rdata section. First we get the
6947 upper 16 bits of the address. */
6948 if (mips_pic == NO_PIC)
6950 macro_build_lui (&offset_expr, AT);
6955 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6956 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6960 /* Now we load the register(s). */
6961 if (HAVE_64BIT_GPRS)
6964 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
6969 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
6972 /* FIXME: How in the world do we deal with the possible
6974 offset_expr.X_add_number += 4;
6975 macro_build (&offset_expr, "lw", "t,o(b)",
6976 treg + 1, BFD_RELOC_LO16, AT);
6982 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6983 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6984 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6985 the value and the low order 32 bits are either zero or in
6987 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6990 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
6991 if (HAVE_64BIT_FPRS)
6993 gas_assert (HAVE_64BIT_GPRS);
6994 macro_build (NULL, "dmtc1", "t,S", AT, treg);
6998 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
6999 if (offset_expr.X_op == O_absent)
7000 macro_build (NULL, "mtc1", "t,G", 0, treg);
7003 gas_assert (offset_expr.X_op == O_constant);
7004 load_register (AT, &offset_expr, 0);
7005 macro_build (NULL, "mtc1", "t,G", AT, treg);
7011 gas_assert (offset_expr.X_op == O_symbol
7012 && offset_expr.X_add_number == 0);
7013 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
7014 if (strcmp (s, ".lit8") == 0)
7016 if (mips_opts.isa != ISA_MIPS1)
7018 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
7019 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
7022 breg = mips_gp_register;
7023 r = BFD_RELOC_MIPS_LITERAL;
7028 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
7030 if (mips_pic != NO_PIC)
7031 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7032 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7035 /* FIXME: This won't work for a 64 bit address. */
7036 macro_build_lui (&offset_expr, AT);
7039 if (mips_opts.isa != ISA_MIPS1)
7041 macro_build (&offset_expr, "ldc1", "T,o(b)",
7042 treg, BFD_RELOC_LO16, AT);
7051 /* Even on a big endian machine $fn comes before $fn+1. We have
7052 to adjust when loading from memory. */
7055 gas_assert (mips_opts.isa == ISA_MIPS1);
7056 macro_build (&offset_expr, "lwc1", "T,o(b)",
7057 target_big_endian ? treg + 1 : treg, r, breg);
7058 /* FIXME: A possible overflow which I don't know how to deal
7060 offset_expr.X_add_number += 4;
7061 macro_build (&offset_expr, "lwc1", "T,o(b)",
7062 target_big_endian ? treg : treg + 1, r, breg);
7067 * The MIPS assembler seems to check for X_add_number not
7068 * being double aligned and generating:
7071 * addiu at,at,%lo(foo+1)
7074 * But, the resulting address is the same after relocation so why
7075 * generate the extra instruction?
7077 /* Itbl support may require additional care here. */
7079 if (mips_opts.isa != ISA_MIPS1)
7090 if (mips_opts.isa != ISA_MIPS1)
7098 /* Itbl support may require additional care here. */
7103 if (HAVE_64BIT_GPRS)
7114 if (HAVE_64BIT_GPRS)
7124 if (offset_expr.X_op != O_symbol
7125 && offset_expr.X_op != O_constant)
7127 as_bad (_("Expression too complex"));
7128 offset_expr.X_op = O_constant;
7131 if (HAVE_32BIT_ADDRESSES
7132 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
7136 sprintf_vma (value, offset_expr.X_add_number);
7137 as_bad (_("Number (0x%s) larger than 32 bits"), value);
7140 /* Even on a big endian machine $fn comes before $fn+1. We have
7141 to adjust when loading from memory. We set coproc if we must
7142 load $fn+1 first. */
7143 /* Itbl support may require additional care here. */
7144 if (!target_big_endian)
7147 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
7149 /* If this is a reference to a GP relative symbol, we want
7150 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
7151 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
7152 If we have a base register, we use this
7154 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
7155 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
7156 If this is not a GP relative symbol, we want
7157 lui $at,<sym> (BFD_RELOC_HI16_S)
7158 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7159 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7160 If there is a base register, we add it to $at after the
7161 lui instruction. If there is a constant, we always use
7163 if (offset_expr.X_op == O_symbol
7164 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7165 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7167 relax_start (offset_expr.X_add_symbol);
7170 tempreg = mips_gp_register;
7174 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7175 AT, breg, mips_gp_register);
7180 /* Itbl support may require additional care here. */
7181 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7182 BFD_RELOC_GPREL16, tempreg);
7183 offset_expr.X_add_number += 4;
7185 /* Set mips_optimize to 2 to avoid inserting an
7187 hold_mips_optimize = mips_optimize;
7189 /* Itbl support may require additional care here. */
7190 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7191 BFD_RELOC_GPREL16, tempreg);
7192 mips_optimize = hold_mips_optimize;
7196 offset_expr.X_add_number -= 4;
7199 macro_build_lui (&offset_expr, AT);
7201 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7202 /* Itbl support may require additional care here. */
7203 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7204 BFD_RELOC_LO16, AT);
7205 /* FIXME: How do we handle overflow here? */
7206 offset_expr.X_add_number += 4;
7207 /* Itbl support may require additional care here. */
7208 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7209 BFD_RELOC_LO16, AT);
7210 if (mips_relax.sequence)
7213 else if (!mips_big_got)
7215 /* If this is a reference to an external symbol, we want
7216 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7221 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7223 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7224 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7225 If there is a base register we add it to $at before the
7226 lwc1 instructions. If there is a constant we include it
7227 in the lwc1 instructions. */
7229 expr1.X_add_number = offset_expr.X_add_number;
7230 if (expr1.X_add_number < -0x8000
7231 || expr1.X_add_number >= 0x8000 - 4)
7232 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7233 load_got_offset (AT, &offset_expr);
7236 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7238 /* Set mips_optimize to 2 to avoid inserting an undesired
7240 hold_mips_optimize = mips_optimize;
7243 /* Itbl support may require additional care here. */
7244 relax_start (offset_expr.X_add_symbol);
7245 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
7246 BFD_RELOC_LO16, AT);
7247 expr1.X_add_number += 4;
7248 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
7249 BFD_RELOC_LO16, AT);
7251 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7252 BFD_RELOC_LO16, AT);
7253 offset_expr.X_add_number += 4;
7254 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7255 BFD_RELOC_LO16, AT);
7258 mips_optimize = hold_mips_optimize;
7260 else if (mips_big_got)
7264 /* If this is a reference to an external symbol, we want
7265 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7267 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
7272 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7274 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7275 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7276 If there is a base register we add it to $at before the
7277 lwc1 instructions. If there is a constant we include it
7278 in the lwc1 instructions. */
7280 expr1.X_add_number = offset_expr.X_add_number;
7281 offset_expr.X_add_number = 0;
7282 if (expr1.X_add_number < -0x8000
7283 || expr1.X_add_number >= 0x8000 - 4)
7284 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7285 gpdelay = reg_needs_delay (mips_gp_register);
7286 relax_start (offset_expr.X_add_symbol);
7287 macro_build (&offset_expr, "lui", "t,u",
7288 AT, BFD_RELOC_MIPS_GOT_HI16);
7289 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7290 AT, AT, mips_gp_register);
7291 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7292 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
7295 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7296 /* Itbl support may require additional care here. */
7297 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
7298 BFD_RELOC_LO16, AT);
7299 expr1.X_add_number += 4;
7301 /* Set mips_optimize to 2 to avoid inserting an undesired
7303 hold_mips_optimize = mips_optimize;
7305 /* Itbl support may require additional care here. */
7306 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
7307 BFD_RELOC_LO16, AT);
7308 mips_optimize = hold_mips_optimize;
7309 expr1.X_add_number -= 4;
7312 offset_expr.X_add_number = expr1.X_add_number;
7314 macro_build (NULL, "nop", "");
7315 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7316 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7319 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7320 /* Itbl support may require additional care here. */
7321 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7322 BFD_RELOC_LO16, AT);
7323 offset_expr.X_add_number += 4;
7325 /* Set mips_optimize to 2 to avoid inserting an undesired
7327 hold_mips_optimize = mips_optimize;
7329 /* Itbl support may require additional care here. */
7330 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7331 BFD_RELOC_LO16, AT);
7332 mips_optimize = hold_mips_optimize;
7341 s = HAVE_64BIT_GPRS ? "ld" : "lw";
7344 s = HAVE_64BIT_GPRS ? "sd" : "sw";
7346 macro_build (&offset_expr, s, "t,o(b)", treg,
7347 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
7349 if (!HAVE_64BIT_GPRS)
7351 offset_expr.X_add_number += 4;
7352 macro_build (&offset_expr, s, "t,o(b)", treg + 1,
7353 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
7358 /* New code added to support COPZ instructions.
7359 This code builds table entries out of the macros in mip_opcodes.
7360 R4000 uses interlocks to handle coproc delays.
7361 Other chips (like the R3000) require nops to be inserted for delays.
7363 FIXME: Currently, we require that the user handle delays.
7364 In order to fill delay slots for non-interlocked chips,
7365 we must have a way to specify delays based on the coprocessor.
7366 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7367 What are the side-effects of the cop instruction?
7368 What cache support might we have and what are its effects?
7369 Both coprocessor & memory require delays. how long???
7370 What registers are read/set/modified?
7372 If an itbl is provided to interpret cop instructions,
7373 this knowledge can be encoded in the itbl spec. */
7387 if (NO_ISA_COP (mips_opts.arch)
7388 && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0)
7390 as_bad (_("opcode not supported on this processor: %s"),
7391 mips_cpu_info_from_arch (mips_opts.arch)->name);
7395 /* For now we just do C (same as Cz). The parameter will be
7396 stored in insn_opcode by mips_ip. */
7397 macro_build (NULL, s, "C", ip->insn_opcode);
7401 move_register (dreg, sreg);
7407 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
7408 macro_build (NULL, "mflo", "d", dreg);
7414 /* The MIPS assembler some times generates shifts and adds. I'm
7415 not trying to be that fancy. GCC should do this for us
7418 load_register (AT, &imm_expr, dbl);
7419 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
7420 macro_build (NULL, "mflo", "d", dreg);
7436 load_register (AT, &imm_expr, dbl);
7437 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
7438 macro_build (NULL, "mflo", "d", dreg);
7439 macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
7440 macro_build (NULL, "mfhi", "d", AT);
7442 macro_build (NULL, "tne", "s,t,q", dreg, AT, 6);
7445 expr1.X_add_number = 8;
7446 macro_build (&expr1, "beq", "s,t,p", dreg, AT);
7447 macro_build (NULL, "nop", "");
7448 macro_build (NULL, "break", "c", 6);
7451 macro_build (NULL, "mflo", "d", dreg);
7467 load_register (AT, &imm_expr, dbl);
7468 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
7469 sreg, imm ? AT : treg);
7470 macro_build (NULL, "mfhi", "d", AT);
7471 macro_build (NULL, "mflo", "d", dreg);
7473 macro_build (NULL, "tne", "s,t,q", AT, ZERO, 6);
7476 expr1.X_add_number = 8;
7477 macro_build (&expr1, "beq", "s,t,p", AT, ZERO);
7478 macro_build (NULL, "nop", "");
7479 macro_build (NULL, "break", "c", 6);
7485 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7496 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
7497 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
7501 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
7502 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
7503 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
7504 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7508 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7519 macro_build (NULL, "negu", "d,w", tempreg, treg);
7520 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
7524 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
7525 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
7526 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
7527 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7536 if (imm_expr.X_op != O_constant)
7537 as_bad (_("Improper rotate count"));
7538 rot = imm_expr.X_add_number & 0x3f;
7539 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7541 rot = (64 - rot) & 0x3f;
7543 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7545 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7550 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7553 l = (rot < 0x20) ? "dsll" : "dsll32";
7554 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
7557 macro_build (NULL, l, "d,w,<", AT, sreg, rot);
7558 macro_build (NULL, rr, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7559 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7567 if (imm_expr.X_op != O_constant)
7568 as_bad (_("Improper rotate count"));
7569 rot = imm_expr.X_add_number & 0x1f;
7570 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7572 macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f);
7577 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7581 macro_build (NULL, "sll", "d,w,<", AT, sreg, rot);
7582 macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7583 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7588 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7590 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
7594 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
7595 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
7596 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
7597 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7601 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7603 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
7607 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
7608 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
7609 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
7610 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7619 if (imm_expr.X_op != O_constant)
7620 as_bad (_("Improper rotate count"));
7621 rot = imm_expr.X_add_number & 0x3f;
7622 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7625 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7627 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7632 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7635 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
7636 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7639 macro_build (NULL, rr, "d,w,<", AT, sreg, rot);
7640 macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7641 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7649 if (imm_expr.X_op != O_constant)
7650 as_bad (_("Improper rotate count"));
7651 rot = imm_expr.X_add_number & 0x1f;
7652 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7654 macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot);
7659 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7663 macro_build (NULL, "srl", "d,w,<", AT, sreg, rot);
7664 macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7665 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7670 gas_assert (mips_opts.isa == ISA_MIPS1);
7671 /* Even on a big endian machine $fn comes before $fn+1. We have
7672 to adjust when storing to memory. */
7673 macro_build (&offset_expr, "swc1", "T,o(b)",
7674 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
7675 offset_expr.X_add_number += 4;
7676 macro_build (&offset_expr, "swc1", "T,o(b)",
7677 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
7682 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
7684 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7687 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7688 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7693 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7695 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7700 as_warn (_("Instruction %s: result is always false"),
7702 move_register (dreg, 0);
7705 if (CPU_HAS_SEQ (mips_opts.arch)
7706 && -512 <= imm_expr.X_add_number
7707 && imm_expr.X_add_number < 512)
7709 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
7710 (int) imm_expr.X_add_number);
7713 if (imm_expr.X_op == O_constant
7714 && imm_expr.X_add_number >= 0
7715 && imm_expr.X_add_number < 0x10000)
7717 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7719 else if (imm_expr.X_op == O_constant
7720 && imm_expr.X_add_number > -0x8000
7721 && imm_expr.X_add_number < 0)
7723 imm_expr.X_add_number = -imm_expr.X_add_number;
7724 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7725 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7727 else if (CPU_HAS_SEQ (mips_opts.arch))
7730 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7731 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
7736 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7737 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7740 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7743 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
7749 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
7750 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7753 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
7755 if (imm_expr.X_op == O_constant
7756 && imm_expr.X_add_number >= -0x8000
7757 && imm_expr.X_add_number < 0x8000)
7759 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
7760 dreg, sreg, BFD_RELOC_LO16);
7764 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7765 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
7769 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7772 case M_SGT: /* sreg > treg <==> treg < sreg */
7778 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7781 case M_SGT_I: /* sreg > I <==> I < sreg */
7788 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7789 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7792 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7798 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7799 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7802 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7809 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7810 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7811 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7815 if (imm_expr.X_op == O_constant
7816 && imm_expr.X_add_number >= -0x8000
7817 && imm_expr.X_add_number < 0x8000)
7819 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7823 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7824 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
7828 if (imm_expr.X_op == O_constant
7829 && imm_expr.X_add_number >= -0x8000
7830 && imm_expr.X_add_number < 0x8000)
7832 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
7837 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7838 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
7843 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
7845 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
7848 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7849 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
7854 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7856 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
7861 as_warn (_("Instruction %s: result is always true"),
7863 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
7864 dreg, 0, BFD_RELOC_LO16);
7867 if (CPU_HAS_SEQ (mips_opts.arch)
7868 && -512 <= imm_expr.X_add_number
7869 && imm_expr.X_add_number < 512)
7871 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
7872 (int) imm_expr.X_add_number);
7875 if (imm_expr.X_op == O_constant
7876 && imm_expr.X_add_number >= 0
7877 && imm_expr.X_add_number < 0x10000)
7879 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7881 else if (imm_expr.X_op == O_constant
7882 && imm_expr.X_add_number > -0x8000
7883 && imm_expr.X_add_number < 0)
7885 imm_expr.X_add_number = -imm_expr.X_add_number;
7886 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7887 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7889 else if (CPU_HAS_SEQ (mips_opts.arch))
7892 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7893 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
7898 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7899 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7902 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
7908 if (imm_expr.X_op == O_constant
7909 && imm_expr.X_add_number > -0x8000
7910 && imm_expr.X_add_number <= 0x8000)
7912 imm_expr.X_add_number = -imm_expr.X_add_number;
7913 macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j",
7914 dreg, sreg, BFD_RELOC_LO16);
7918 load_register (AT, &imm_expr, dbl);
7919 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
7925 if (imm_expr.X_op == O_constant
7926 && imm_expr.X_add_number > -0x8000
7927 && imm_expr.X_add_number <= 0x8000)
7929 imm_expr.X_add_number = -imm_expr.X_add_number;
7930 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j",
7931 dreg, sreg, BFD_RELOC_LO16);
7935 load_register (AT, &imm_expr, dbl);
7936 macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
7958 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7959 macro_build (NULL, s, "s,t", sreg, AT);
7964 gas_assert (mips_opts.isa == ISA_MIPS1);
7966 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
7967 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
7970 * Is the double cfc1 instruction a bug in the mips assembler;
7971 * or is there a reason for it?
7974 macro_build (NULL, "cfc1", "t,G", treg, RA);
7975 macro_build (NULL, "cfc1", "t,G", treg, RA);
7976 macro_build (NULL, "nop", "");
7977 expr1.X_add_number = 3;
7978 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
7979 expr1.X_add_number = 2;
7980 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
7981 macro_build (NULL, "ctc1", "t,G", AT, RA);
7982 macro_build (NULL, "nop", "");
7983 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
7985 macro_build (NULL, "ctc1", "t,G", treg, RA);
7986 macro_build (NULL, "nop", "");
7997 if (offset_expr.X_add_number >= 0x7fff)
7998 as_bad (_("Operand overflow"));
7999 if (!target_big_endian)
8000 ++offset_expr.X_add_number;
8001 macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg);
8002 if (!target_big_endian)
8003 --offset_expr.X_add_number;
8005 ++offset_expr.X_add_number;
8006 macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg);
8007 macro_build (NULL, "sll", "d,w,<", AT, AT, 8);
8008 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8021 if (offset_expr.X_add_number >= 0x8000 - off)
8022 as_bad (_("Operand overflow"));
8030 if (!target_big_endian)
8031 offset_expr.X_add_number += off;
8032 macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
8033 if (!target_big_endian)
8034 offset_expr.X_add_number -= off;
8036 offset_expr.X_add_number += off;
8037 macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
8039 /* If necessary, move the result in tempreg to the final destination. */
8040 if (treg == tempreg)
8042 /* Protect second load's delay slot. */
8044 move_register (treg, tempreg);
8058 load_address (AT, &offset_expr, &used_at);
8060 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8061 if (!target_big_endian)
8062 expr1.X_add_number = off;
8064 expr1.X_add_number = 0;
8065 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8066 if (!target_big_endian)
8067 expr1.X_add_number = 0;
8069 expr1.X_add_number = off;
8070 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8076 load_address (AT, &offset_expr, &used_at);
8078 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8079 if (target_big_endian)
8080 expr1.X_add_number = 0;
8081 macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
8082 treg, BFD_RELOC_LO16, AT);
8083 if (target_big_endian)
8084 expr1.X_add_number = 1;
8086 expr1.X_add_number = 0;
8087 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
8088 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
8089 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8094 if (offset_expr.X_add_number >= 0x7fff)
8095 as_bad (_("Operand overflow"));
8096 if (target_big_endian)
8097 ++offset_expr.X_add_number;
8098 macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg);
8099 macro_build (NULL, "srl", "d,w,<", AT, treg, 8);
8100 if (target_big_endian)
8101 --offset_expr.X_add_number;
8103 ++offset_expr.X_add_number;
8104 macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg);
8117 if (offset_expr.X_add_number >= 0x8000 - off)
8118 as_bad (_("Operand overflow"));
8119 if (!target_big_endian)
8120 offset_expr.X_add_number += off;
8121 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8122 if (!target_big_endian)
8123 offset_expr.X_add_number -= off;
8125 offset_expr.X_add_number += off;
8126 macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8140 load_address (AT, &offset_expr, &used_at);
8142 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8143 if (!target_big_endian)
8144 expr1.X_add_number = off;
8146 expr1.X_add_number = 0;
8147 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8148 if (!target_big_endian)
8149 expr1.X_add_number = 0;
8151 expr1.X_add_number = off;
8152 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8157 load_address (AT, &offset_expr, &used_at);
8159 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8160 if (!target_big_endian)
8161 expr1.X_add_number = 0;
8162 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8163 macro_build (NULL, "srl", "d,w,<", treg, treg, 8);
8164 if (!target_big_endian)
8165 expr1.X_add_number = 1;
8167 expr1.X_add_number = 0;
8168 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8169 if (!target_big_endian)
8170 expr1.X_add_number = 0;
8172 expr1.X_add_number = 1;
8173 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
8174 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
8175 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8179 /* FIXME: Check if this is one of the itbl macros, since they
8180 are added dynamically. */
8181 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
8184 if (!mips_opts.at && used_at)
8185 as_bad (_("Macro used $at after \".set noat\""));
8188 /* Implement macros in mips16 mode. */
8191 mips16_macro (struct mips_cl_insn *ip)
8194 int xreg, yreg, zreg, tmp;
8197 const char *s, *s2, *s3;
8199 mask = ip->insn_mo->mask;
8201 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
8202 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
8203 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
8205 expr1.X_op = O_constant;
8206 expr1.X_op_symbol = NULL;
8207 expr1.X_add_symbol = NULL;
8208 expr1.X_add_number = 1;
8228 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
8229 expr1.X_add_number = 2;
8230 macro_build (&expr1, "bnez", "x,p", yreg);
8231 macro_build (NULL, "break", "6", 7);
8233 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
8234 since that causes an overflow. We should do that as well,
8235 but I don't see how to do the comparisons without a temporary
8238 macro_build (NULL, s, "x", zreg);
8258 macro_build (NULL, s, "0,x,y", xreg, yreg);
8259 expr1.X_add_number = 2;
8260 macro_build (&expr1, "bnez", "x,p", yreg);
8261 macro_build (NULL, "break", "6", 7);
8263 macro_build (NULL, s2, "x", zreg);
8269 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
8270 macro_build (NULL, "mflo", "x", zreg);
8278 if (imm_expr.X_op != O_constant)
8279 as_bad (_("Unsupported large constant"));
8280 imm_expr.X_add_number = -imm_expr.X_add_number;
8281 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
8285 if (imm_expr.X_op != O_constant)
8286 as_bad (_("Unsupported large constant"));
8287 imm_expr.X_add_number = -imm_expr.X_add_number;
8288 macro_build (&imm_expr, "addiu", "x,k", xreg);
8292 if (imm_expr.X_op != O_constant)
8293 as_bad (_("Unsupported large constant"));
8294 imm_expr.X_add_number = -imm_expr.X_add_number;
8295 macro_build (&imm_expr, "daddiu", "y,j", yreg);
8317 goto do_reverse_branch;
8321 goto do_reverse_branch;
8333 goto do_reverse_branch;
8344 macro_build (NULL, s, "x,y", xreg, yreg);
8345 macro_build (&offset_expr, s2, "p");
8372 goto do_addone_branch_i;
8377 goto do_addone_branch_i;
8392 goto do_addone_branch_i;
8399 if (imm_expr.X_op != O_constant)
8400 as_bad (_("Unsupported large constant"));
8401 ++imm_expr.X_add_number;
8404 macro_build (&imm_expr, s, s3, xreg);
8405 macro_build (&offset_expr, s2, "p");
8409 expr1.X_add_number = 0;
8410 macro_build (&expr1, "slti", "x,8", yreg);
8412 move_register (xreg, yreg);
8413 expr1.X_add_number = 2;
8414 macro_build (&expr1, "bteqz", "p");
8415 macro_build (NULL, "neg", "x,w", xreg, xreg);
8419 /* For consistency checking, verify that all bits are specified either
8420 by the match/mask part of the instruction definition, or by the
8423 validate_mips_insn (const struct mips_opcode *opc)
8425 const char *p = opc->args;
8427 unsigned long used_bits = opc->mask;
8429 if ((used_bits & opc->match) != opc->match)
8431 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8432 opc->name, opc->args);
8435 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8445 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
8446 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
8447 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
8448 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
8449 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8450 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8451 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8452 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
8453 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8454 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8455 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8456 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8457 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8459 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8460 case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
8461 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8462 case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
8463 case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
8464 case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
8465 case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
8466 case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
8467 case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
8468 case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
8471 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8472 c, opc->name, opc->args);
8476 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8477 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8479 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
8480 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
8481 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8482 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8484 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8485 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8487 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
8488 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8490 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
8491 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
8492 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
8493 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
8494 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8495 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
8496 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8497 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8498 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8499 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8500 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8501 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8502 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8503 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
8504 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8505 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
8506 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8508 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
8509 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8510 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8511 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
8513 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8514 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8515 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
8516 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8517 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8518 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8519 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8520 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8521 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8524 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
8525 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
8526 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8527 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
8528 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
8531 case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8532 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
8533 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
8534 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
8535 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
8536 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8537 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
8538 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
8539 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
8540 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
8541 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
8542 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
8543 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
8544 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
8545 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
8546 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
8547 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
8548 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8550 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8551 c, opc->name, opc->args);
8555 if (used_bits != 0xffffffff)
8557 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8558 ~used_bits & 0xffffffff, opc->name, opc->args);
8564 /* UDI immediates. */
8572 static const struct mips_immed mips_immed[] = {
8573 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
8574 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
8575 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
8576 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
8580 /* Check whether an odd floating-point register is allowed. */
8582 mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
8584 const char *s = insn->name;
8586 if (insn->pinfo == INSN_MACRO)
8587 /* Let a macro pass, we'll catch it later when it is expanded. */
8590 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa))
8592 /* Allow odd registers for single-precision ops. */
8593 switch (insn->pinfo & (FP_S | FP_D))
8597 return 1; /* both single precision - ok */
8599 return 0; /* both double precision - fail */
8604 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
8605 s = strchr (insn->name, '.');
8607 s = s != NULL ? strchr (s + 1, '.') : NULL;
8608 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
8611 /* Single-precision coprocessor loads and moves are OK too. */
8612 if ((insn->pinfo & FP_S)
8613 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
8614 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
8620 /* This routine assembles an instruction into its binary format. As a
8621 side effect, it sets one of the global variables imm_reloc or
8622 offset_reloc to the type of relocation to do if one of the operands
8623 is an address expression. */
8626 mips_ip (char *str, struct mips_cl_insn *ip)
8631 struct mips_opcode *insn;
8634 unsigned int lastregno = 0;
8635 unsigned int lastpos = 0;
8636 unsigned int limlo, limhi;
8639 offsetT min_range, max_range;
8645 /* If the instruction contains a '.', we first try to match an instruction
8646 including the '.'. Then we try again without the '.'. */
8648 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
8651 /* If we stopped on whitespace, then replace the whitespace with null for
8652 the call to hash_find. Save the character we replaced just in case we
8653 have to re-parse the instruction. */
8660 insn = (struct mips_opcode *) hash_find (op_hash, str);
8662 /* If we didn't find the instruction in the opcode table, try again, but
8663 this time with just the instruction up to, but not including the
8667 /* Restore the character we overwrite above (if any). */
8671 /* Scan up to the first '.' or whitespace. */
8673 *s != '\0' && *s != '.' && !ISSPACE (*s);
8677 /* If we did not find a '.', then we can quit now. */
8680 insn_error = _("Unrecognized opcode");
8684 /* Lookup the instruction in the hash table. */
8686 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
8688 insn_error = _("Unrecognized opcode");
8698 gas_assert (strcmp (insn->name, str) == 0);
8700 ok = is_opcode_valid (insn);
8703 if (insn + 1 < &mips_opcodes[NUMOPCODES]
8704 && strcmp (insn->name, insn[1].name) == 0)
8713 static char buf[100];
8715 _("opcode not supported on this processor: %s (%s)"),
8716 mips_cpu_info_from_arch (mips_opts.arch)->name,
8717 mips_cpu_info_from_isa (mips_opts.isa)->name);
8726 create_insn (ip, insn);
8729 lastregno = 0xffffffff;
8730 for (args = insn->args;; ++args)
8734 s += strspn (s, " \t");
8738 case '\0': /* end of args */
8743 case '2': /* DSP 2-bit unsigned immediate in bit 11. */
8744 my_getExpression (&imm_expr, s);
8745 check_absolute_expr (ip, &imm_expr);
8746 if ((unsigned long) imm_expr.X_add_number != 1
8747 && (unsigned long) imm_expr.X_add_number != 3)
8749 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
8750 (unsigned long) imm_expr.X_add_number);
8752 INSERT_OPERAND (BP, *ip, imm_expr.X_add_number);
8753 imm_expr.X_op = O_absent;
8757 case '3': /* DSP 3-bit unsigned immediate in bit 21. */
8758 my_getExpression (&imm_expr, s);
8759 check_absolute_expr (ip, &imm_expr);
8760 if (imm_expr.X_add_number & ~OP_MASK_SA3)
8762 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8763 OP_MASK_SA3, (unsigned long) imm_expr.X_add_number);
8765 INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number);
8766 imm_expr.X_op = O_absent;
8770 case '4': /* DSP 4-bit unsigned immediate in bit 21. */
8771 my_getExpression (&imm_expr, s);
8772 check_absolute_expr (ip, &imm_expr);
8773 if (imm_expr.X_add_number & ~OP_MASK_SA4)
8775 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8776 OP_MASK_SA4, (unsigned long) imm_expr.X_add_number);
8778 INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number);
8779 imm_expr.X_op = O_absent;
8783 case '5': /* DSP 8-bit unsigned immediate in bit 16. */
8784 my_getExpression (&imm_expr, s);
8785 check_absolute_expr (ip, &imm_expr);
8786 if (imm_expr.X_add_number & ~OP_MASK_IMM8)
8788 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8789 OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number);
8791 INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number);
8792 imm_expr.X_op = O_absent;
8796 case '6': /* DSP 5-bit unsigned immediate in bit 21. */
8797 my_getExpression (&imm_expr, s);
8798 check_absolute_expr (ip, &imm_expr);
8799 if (imm_expr.X_add_number & ~OP_MASK_RS)
8801 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8802 OP_MASK_RS, (unsigned long) imm_expr.X_add_number);
8804 INSERT_OPERAND (RS, *ip, imm_expr.X_add_number);
8805 imm_expr.X_op = O_absent;
8809 case '7': /* Four DSP accumulators in bits 11,12. */
8810 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8811 s[3] >= '0' && s[3] <= '3')
8815 INSERT_OPERAND (DSPACC, *ip, regno);
8819 as_bad (_("Invalid dsp acc register"));
8822 case '8': /* DSP 6-bit unsigned immediate in bit 11. */
8823 my_getExpression (&imm_expr, s);
8824 check_absolute_expr (ip, &imm_expr);
8825 if (imm_expr.X_add_number & ~OP_MASK_WRDSP)
8827 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8829 (unsigned long) imm_expr.X_add_number);
8831 INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number);
8832 imm_expr.X_op = O_absent;
8836 case '9': /* Four DSP accumulators in bits 21,22. */
8837 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8838 s[3] >= '0' && s[3] <= '3')
8842 INSERT_OPERAND (DSPACC_S, *ip, regno);
8846 as_bad (_("Invalid dsp acc register"));
8849 case '0': /* DSP 6-bit signed immediate in bit 20. */
8850 my_getExpression (&imm_expr, s);
8851 check_absolute_expr (ip, &imm_expr);
8852 min_range = -((OP_MASK_DSPSFT + 1) >> 1);
8853 max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1;
8854 if (imm_expr.X_add_number < min_range ||
8855 imm_expr.X_add_number > max_range)
8857 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8858 (long) min_range, (long) max_range,
8859 (long) imm_expr.X_add_number);
8861 INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number);
8862 imm_expr.X_op = O_absent;
8866 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
8867 my_getExpression (&imm_expr, s);
8868 check_absolute_expr (ip, &imm_expr);
8869 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
8871 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8873 (unsigned long) imm_expr.X_add_number);
8875 INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number);
8876 imm_expr.X_op = O_absent;
8880 case ':': /* DSP 7-bit signed immediate in bit 19. */
8881 my_getExpression (&imm_expr, s);
8882 check_absolute_expr (ip, &imm_expr);
8883 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
8884 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
8885 if (imm_expr.X_add_number < min_range ||
8886 imm_expr.X_add_number > max_range)
8888 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8889 (long) min_range, (long) max_range,
8890 (long) imm_expr.X_add_number);
8892 INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number);
8893 imm_expr.X_op = O_absent;
8897 case '@': /* DSP 10-bit signed immediate in bit 16. */
8898 my_getExpression (&imm_expr, s);
8899 check_absolute_expr (ip, &imm_expr);
8900 min_range = -((OP_MASK_IMM10 + 1) >> 1);
8901 max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1;
8902 if (imm_expr.X_add_number < min_range ||
8903 imm_expr.X_add_number > max_range)
8905 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8906 (long) min_range, (long) max_range,
8907 (long) imm_expr.X_add_number);
8909 INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number);
8910 imm_expr.X_op = O_absent;
8914 case '!': /* MT usermode flag bit. */
8915 my_getExpression (&imm_expr, s);
8916 check_absolute_expr (ip, &imm_expr);
8917 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
8918 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
8919 (unsigned long) imm_expr.X_add_number);
8920 INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number);
8921 imm_expr.X_op = O_absent;
8925 case '$': /* MT load high flag bit. */
8926 my_getExpression (&imm_expr, s);
8927 check_absolute_expr (ip, &imm_expr);
8928 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
8929 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
8930 (unsigned long) imm_expr.X_add_number);
8931 INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number);
8932 imm_expr.X_op = O_absent;
8936 case '*': /* Four DSP accumulators in bits 18,19. */
8937 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8938 s[3] >= '0' && s[3] <= '3')
8942 INSERT_OPERAND (MTACC_T, *ip, regno);
8946 as_bad (_("Invalid dsp/smartmips acc register"));
8949 case '&': /* Four DSP accumulators in bits 13,14. */
8950 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8951 s[3] >= '0' && s[3] <= '3')
8955 INSERT_OPERAND (MTACC_D, *ip, regno);
8959 as_bad (_("Invalid dsp/smartmips acc register"));
8971 INSERT_OPERAND (RS, *ip, lastregno);
8975 INSERT_OPERAND (RT, *ip, lastregno);
8979 INSERT_OPERAND (FT, *ip, lastregno);
8983 INSERT_OPERAND (FS, *ip, lastregno);
8989 /* Handle optional base register.
8990 Either the base register is omitted or
8991 we must have a left paren. */
8992 /* This is dependent on the next operand specifier
8993 is a base register specification. */
8994 gas_assert (args[1] == 'b' || args[1] == '5'
8995 || args[1] == '-' || args[1] == '4');
8999 case ')': /* These must match exactly. */
9006 case '+': /* Opcode extension character. */
9009 case '1': /* UDI immediates. */
9014 const struct mips_immed *imm = mips_immed;
9016 while (imm->type && imm->type != *args)
9020 my_getExpression (&imm_expr, s);
9021 check_absolute_expr (ip, &imm_expr);
9022 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
9024 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
9025 imm->desc ? imm->desc : ip->insn_mo->name,
9026 (unsigned long) imm_expr.X_add_number,
9027 (unsigned long) imm_expr.X_add_number);
9028 imm_expr.X_add_number &= imm->mask;
9030 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
9032 imm_expr.X_op = O_absent;
9037 case 'A': /* ins/ext position, becomes LSB. */
9046 my_getExpression (&imm_expr, s);
9047 check_absolute_expr (ip, &imm_expr);
9048 if ((unsigned long) imm_expr.X_add_number < limlo
9049 || (unsigned long) imm_expr.X_add_number > limhi)
9051 as_bad (_("Improper position (%lu)"),
9052 (unsigned long) imm_expr.X_add_number);
9053 imm_expr.X_add_number = limlo;
9055 lastpos = imm_expr.X_add_number;
9056 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9057 imm_expr.X_op = O_absent;
9061 case 'B': /* ins size, becomes MSB. */
9070 my_getExpression (&imm_expr, s);
9071 check_absolute_expr (ip, &imm_expr);
9072 /* Check for negative input so that small negative numbers
9073 will not succeed incorrectly. The checks against
9074 (pos+size) transitively check "size" itself,
9075 assuming that "pos" is reasonable. */
9076 if ((long) imm_expr.X_add_number < 0
9077 || ((unsigned long) imm_expr.X_add_number
9079 || ((unsigned long) imm_expr.X_add_number
9082 as_bad (_("Improper insert size (%lu, position %lu)"),
9083 (unsigned long) imm_expr.X_add_number,
9084 (unsigned long) lastpos);
9085 imm_expr.X_add_number = limlo - lastpos;
9087 INSERT_OPERAND (INSMSB, *ip,
9088 lastpos + imm_expr.X_add_number - 1);
9089 imm_expr.X_op = O_absent;
9093 case 'C': /* ext size, becomes MSBD. */
9106 my_getExpression (&imm_expr, s);
9107 check_absolute_expr (ip, &imm_expr);
9108 /* Check for negative input so that small negative numbers
9109 will not succeed incorrectly. The checks against
9110 (pos+size) transitively check "size" itself,
9111 assuming that "pos" is reasonable. */
9112 if ((long) imm_expr.X_add_number < 0
9113 || ((unsigned long) imm_expr.X_add_number
9115 || ((unsigned long) imm_expr.X_add_number
9118 as_bad (_("Improper extract size (%lu, position %lu)"),
9119 (unsigned long) imm_expr.X_add_number,
9120 (unsigned long) lastpos);
9121 imm_expr.X_add_number = limlo - lastpos;
9123 INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1);
9124 imm_expr.X_op = O_absent;
9129 /* +D is for disassembly only; never match. */
9133 /* "+I" is like "I", except that imm2_expr is used. */
9134 my_getExpression (&imm2_expr, s);
9135 if (imm2_expr.X_op != O_big
9136 && imm2_expr.X_op != O_constant)
9137 insn_error = _("absolute expression required");
9138 if (HAVE_32BIT_GPRS)
9139 normalize_constant_expr (&imm2_expr);
9143 case 'T': /* Coprocessor register. */
9144 /* +T is for disassembly only; never match. */
9147 case 't': /* Coprocessor register number. */
9148 if (s[0] == '$' && ISDIGIT (s[1]))
9158 while (ISDIGIT (*s));
9160 as_bad (_("Invalid register number (%d)"), regno);
9163 INSERT_OPERAND (RT, *ip, regno);
9168 as_bad (_("Invalid coprocessor 0 register number"));
9172 /* bbit[01] and bbit[01]32 bit index. Give error if index
9173 is not in the valid range. */
9174 my_getExpression (&imm_expr, s);
9175 check_absolute_expr (ip, &imm_expr);
9176 if ((unsigned) imm_expr.X_add_number > 31)
9178 as_bad (_("Improper bit index (%lu)"),
9179 (unsigned long) imm_expr.X_add_number);
9180 imm_expr.X_add_number = 0;
9182 INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number);
9183 imm_expr.X_op = O_absent;
9188 /* bbit[01] bit index when bbit is used but we generate
9189 bbit[01]32 because the index is over 32. Move to the
9190 next candidate if index is not in the valid range. */
9191 my_getExpression (&imm_expr, s);
9192 check_absolute_expr (ip, &imm_expr);
9193 if ((unsigned) imm_expr.X_add_number < 32
9194 || (unsigned) imm_expr.X_add_number > 63)
9196 INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number - 32);
9197 imm_expr.X_op = O_absent;
9202 /* cins, cins32, exts and exts32 position field. Give error
9203 if it's not in the valid range. */
9204 my_getExpression (&imm_expr, s);
9205 check_absolute_expr (ip, &imm_expr);
9206 if ((unsigned) imm_expr.X_add_number > 31)
9208 as_bad (_("Improper position (%lu)"),
9209 (unsigned long) imm_expr.X_add_number);
9210 imm_expr.X_add_number = 0;
9212 /* Make the pos explicit to simplify +S. */
9213 lastpos = imm_expr.X_add_number + 32;
9214 INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number);
9215 imm_expr.X_op = O_absent;
9220 /* cins, cins32, exts and exts32 position field. Move to
9221 the next candidate if it's not in the valid range. */
9222 my_getExpression (&imm_expr, s);
9223 check_absolute_expr (ip, &imm_expr);
9224 if ((unsigned) imm_expr.X_add_number < 32
9225 || (unsigned) imm_expr.X_add_number > 63)
9227 lastpos = imm_expr.X_add_number;
9228 INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number - 32);
9229 imm_expr.X_op = O_absent;
9234 /* cins and exts length-minus-one field. */
9235 my_getExpression (&imm_expr, s);
9236 check_absolute_expr (ip, &imm_expr);
9237 if ((unsigned long) imm_expr.X_add_number > 31)
9239 as_bad (_("Improper size (%lu)"),
9240 (unsigned long) imm_expr.X_add_number);
9241 imm_expr.X_add_number = 0;
9243 INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number);
9244 imm_expr.X_op = O_absent;
9249 /* cins32/exts32 and cins/exts aliasing cint32/exts32
9250 length-minus-one field. */
9251 my_getExpression (&imm_expr, s);
9252 check_absolute_expr (ip, &imm_expr);
9253 if ((long) imm_expr.X_add_number < 0
9254 || (unsigned long) imm_expr.X_add_number + lastpos > 63)
9256 as_bad (_("Improper size (%lu)"),
9257 (unsigned long) imm_expr.X_add_number);
9258 imm_expr.X_add_number = 0;
9260 INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number);
9261 imm_expr.X_op = O_absent;
9266 /* seqi/snei immediate field. */
9267 my_getExpression (&imm_expr, s);
9268 check_absolute_expr (ip, &imm_expr);
9269 if ((long) imm_expr.X_add_number < -512
9270 || (long) imm_expr.X_add_number >= 512)
9272 as_bad (_("Improper immediate (%ld)"),
9273 (long) imm_expr.X_add_number);
9274 imm_expr.X_add_number = 0;
9276 INSERT_OPERAND (SEQI, *ip, imm_expr.X_add_number);
9277 imm_expr.X_op = O_absent;
9282 as_bad (_("Internal error: bad mips opcode "
9283 "(unknown extension operand type `+%c'): %s %s"),
9284 *args, insn->name, insn->args);
9285 /* Further processing is fruitless. */
9290 case '<': /* must be at least one digit */
9292 * According to the manual, if the shift amount is greater
9293 * than 31 or less than 0, then the shift amount should be
9294 * mod 32. In reality the mips assembler issues an error.
9295 * We issue a warning and mask out all but the low 5 bits.
9297 my_getExpression (&imm_expr, s);
9298 check_absolute_expr (ip, &imm_expr);
9299 if ((unsigned long) imm_expr.X_add_number > 31)
9300 as_warn (_("Improper shift amount (%lu)"),
9301 (unsigned long) imm_expr.X_add_number);
9302 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9303 imm_expr.X_op = O_absent;
9307 case '>': /* shift amount minus 32 */
9308 my_getExpression (&imm_expr, s);
9309 check_absolute_expr (ip, &imm_expr);
9310 if ((unsigned long) imm_expr.X_add_number < 32
9311 || (unsigned long) imm_expr.X_add_number > 63)
9313 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32);
9314 imm_expr.X_op = O_absent;
9318 case 'k': /* CACHE code. */
9319 case 'h': /* PREFX code. */
9320 case '1': /* SYNC type. */
9321 my_getExpression (&imm_expr, s);
9322 check_absolute_expr (ip, &imm_expr);
9323 if ((unsigned long) imm_expr.X_add_number > 31)
9324 as_warn (_("Invalid value for `%s' (%lu)"),
9326 (unsigned long) imm_expr.X_add_number);
9329 if (mips_fix_cn63xxp1 && strcmp ("pref", insn->name) == 0)
9330 switch (imm_expr.X_add_number)
9339 case 31: /* These are ok. */
9342 default: /* The rest must be changed to 28. */
9343 imm_expr.X_add_number = 28;
9346 INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number);
9348 else if (*args == 'h')
9349 INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number);
9351 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9352 imm_expr.X_op = O_absent;
9356 case 'c': /* BREAK code. */
9357 my_getExpression (&imm_expr, s);
9358 check_absolute_expr (ip, &imm_expr);
9359 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE)
9360 as_warn (_("Code for %s not in range 0..1023 (%lu)"),
9362 (unsigned long) imm_expr.X_add_number);
9363 INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number);
9364 imm_expr.X_op = O_absent;
9368 case 'q': /* Lower BREAK code. */
9369 my_getExpression (&imm_expr, s);
9370 check_absolute_expr (ip, &imm_expr);
9371 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2)
9372 as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
9374 (unsigned long) imm_expr.X_add_number);
9375 INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number);
9376 imm_expr.X_op = O_absent;
9380 case 'B': /* 20-bit SYSCALL/BREAK code. */
9381 my_getExpression (&imm_expr, s);
9382 check_absolute_expr (ip, &imm_expr);
9383 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
9384 as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
9386 (unsigned long) imm_expr.X_add_number);
9387 INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number);
9388 imm_expr.X_op = O_absent;
9392 case 'C': /* Coprocessor code. */
9393 my_getExpression (&imm_expr, s);
9394 check_absolute_expr (ip, &imm_expr);
9395 if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ)
9397 as_warn (_("Coproccesor code > 25 bits (%lu)"),
9398 (unsigned long) imm_expr.X_add_number);
9399 imm_expr.X_add_number &= OP_MASK_COPZ;
9401 INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number);
9402 imm_expr.X_op = O_absent;
9406 case 'J': /* 19-bit WAIT code. */
9407 my_getExpression (&imm_expr, s);
9408 check_absolute_expr (ip, &imm_expr);
9409 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
9411 as_warn (_("Illegal 19-bit code (%lu)"),
9412 (unsigned long) imm_expr.X_add_number);
9413 imm_expr.X_add_number &= OP_MASK_CODE19;
9415 INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number);
9416 imm_expr.X_op = O_absent;
9420 case 'P': /* Performance register. */
9421 my_getExpression (&imm_expr, s);
9422 check_absolute_expr (ip, &imm_expr);
9423 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
9424 as_warn (_("Invalid performance register (%lu)"),
9425 (unsigned long) imm_expr.X_add_number);
9426 INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number);
9427 imm_expr.X_op = O_absent;
9431 case 'G': /* Coprocessor destination register. */
9432 if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0)
9433 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, ®no);
9435 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
9436 INSERT_OPERAND (RD, *ip, regno);
9445 case 'b': /* Base register. */
9446 case 'd': /* Destination register. */
9447 case 's': /* Source register. */
9448 case 't': /* Target register. */
9449 case 'r': /* Both target and source. */
9450 case 'v': /* Both dest and source. */
9451 case 'w': /* Both dest and target. */
9452 case 'E': /* Coprocessor target register. */
9453 case 'K': /* RDHWR destination register. */
9454 case 'x': /* Ignore register name. */
9455 case 'z': /* Must be zero register. */
9456 case 'U': /* Destination register (CLO/CLZ). */
9457 case 'g': /* Coprocessor destination register. */
9459 if (*args == 'E' || *args == 'K')
9460 ok = reg_lookup (&s, RTYPE_NUM, ®no);
9463 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
9464 if (regno == AT && mips_opts.at)
9466 if (mips_opts.at == ATREG)
9467 as_warn (_("Used $at without \".set noat\""));
9469 as_warn (_("Used $%u with \".set at=$%u\""),
9470 regno, mips_opts.at);
9480 if (c == 'r' || c == 'v' || c == 'w')
9487 /* 'z' only matches $0. */
9488 if (c == 'z' && regno != 0)
9491 if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
9493 if (regno == lastregno)
9496 = _("Source and destination must be different");
9499 if (regno == 31 && lastregno == 0xffffffff)
9502 = _("A destination register must be supplied");
9506 /* Now that we have assembled one operand, we use the args
9507 string to figure out where it goes in the instruction. */
9514 INSERT_OPERAND (RS, *ip, regno);
9520 INSERT_OPERAND (RD, *ip, regno);
9523 INSERT_OPERAND (RD, *ip, regno);
9524 INSERT_OPERAND (RT, *ip, regno);
9529 INSERT_OPERAND (RT, *ip, regno);
9532 /* This case exists because on the r3000 trunc
9533 expands into a macro which requires a gp
9534 register. On the r6000 or r4000 it is
9535 assembled into a single instruction which
9536 ignores the register. Thus the insn version
9537 is MIPS_ISA2 and uses 'x', and the macro
9538 version is MIPS_ISA1 and uses 't'. */
9541 /* This case is for the div instruction, which
9542 acts differently if the destination argument
9543 is $0. This only matches $0, and is checked
9544 outside the switch. */
9547 /* Itbl operand; not yet implemented. FIXME ?? */
9549 /* What about all other operands like 'i', which
9550 can be specified in the opcode table? */
9559 INSERT_OPERAND (RS, *ip, lastregno);
9562 INSERT_OPERAND (RT, *ip, lastregno);
9567 case 'O': /* MDMX alignment immediate constant. */
9568 my_getExpression (&imm_expr, s);
9569 check_absolute_expr (ip, &imm_expr);
9570 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
9571 as_warn (_("Improper align amount (%ld), using low bits"),
9572 (long) imm_expr.X_add_number);
9573 INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number);
9574 imm_expr.X_op = O_absent;
9578 case 'Q': /* MDMX vector, element sel, or const. */
9581 /* MDMX Immediate. */
9582 my_getExpression (&imm_expr, s);
9583 check_absolute_expr (ip, &imm_expr);
9584 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
9585 as_warn (_("Invalid MDMX Immediate (%ld)"),
9586 (long) imm_expr.X_add_number);
9587 INSERT_OPERAND (FT, *ip, imm_expr.X_add_number);
9588 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
9589 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
9591 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
9592 imm_expr.X_op = O_absent;
9596 /* Not MDMX Immediate. Fall through. */
9597 case 'X': /* MDMX destination register. */
9598 case 'Y': /* MDMX source register. */
9599 case 'Z': /* MDMX target register. */
9601 case 'D': /* Floating point destination register. */
9602 case 'S': /* Floating point source register. */
9603 case 'T': /* Floating point target register. */
9604 case 'R': /* Floating point source register. */
9609 || (mips_opts.ase_mdmx
9610 && (ip->insn_mo->pinfo & FP_D)
9611 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
9612 | INSN_COPROC_MEMORY_DELAY
9613 | INSN_LOAD_COPROC_DELAY
9614 | INSN_LOAD_MEMORY_DELAY
9615 | INSN_STORE_MEMORY))))
9618 if (reg_lookup (&s, rtype, ®no))
9620 if ((regno & 1) != 0
9622 && !mips_oddfpreg_ok (ip->insn_mo, argnum))
9623 as_warn (_("Float register should be even, was %d"),
9631 if (c == 'V' || c == 'W')
9642 INSERT_OPERAND (FD, *ip, regno);
9647 INSERT_OPERAND (FS, *ip, regno);
9650 /* This is like 'Z', but also needs to fix the MDMX
9651 vector/scalar select bits. Note that the
9652 scalar immediate case is handled above. */
9655 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
9656 int max_el = (is_qh ? 3 : 7);
9658 my_getExpression(&imm_expr, s);
9659 check_absolute_expr (ip, &imm_expr);
9661 if (imm_expr.X_add_number > max_el)
9662 as_bad (_("Bad element selector %ld"),
9663 (long) imm_expr.X_add_number);
9664 imm_expr.X_add_number &= max_el;
9665 ip->insn_opcode |= (imm_expr.X_add_number
9668 imm_expr.X_op = O_absent;
9670 as_warn (_("Expecting ']' found '%s'"), s);
9676 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
9677 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
9680 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
9687 INSERT_OPERAND (FT, *ip, regno);
9690 INSERT_OPERAND (FR, *ip, regno);
9700 INSERT_OPERAND (FS, *ip, lastregno);
9703 INSERT_OPERAND (FT, *ip, lastregno);
9709 my_getExpression (&imm_expr, s);
9710 if (imm_expr.X_op != O_big
9711 && imm_expr.X_op != O_constant)
9712 insn_error = _("absolute expression required");
9713 if (HAVE_32BIT_GPRS)
9714 normalize_constant_expr (&imm_expr);
9719 my_getExpression (&offset_expr, s);
9720 normalize_address_expr (&offset_expr);
9721 *imm_reloc = BFD_RELOC_32;
9734 unsigned char temp[8];
9736 unsigned int length;
9741 /* These only appear as the last operand in an
9742 instruction, and every instruction that accepts
9743 them in any variant accepts them in all variants.
9744 This means we don't have to worry about backing out
9745 any changes if the instruction does not match.
9747 The difference between them is the size of the
9748 floating point constant and where it goes. For 'F'
9749 and 'L' the constant is 64 bits; for 'f' and 'l' it
9750 is 32 bits. Where the constant is placed is based
9751 on how the MIPS assembler does things:
9754 f -- immediate value
9757 The .lit4 and .lit8 sections are only used if
9758 permitted by the -G argument.
9760 The code below needs to know whether the target register
9761 is 32 or 64 bits wide. It relies on the fact 'f' and
9762 'F' are used with GPR-based instructions and 'l' and
9763 'L' are used with FPR-based instructions. */
9765 f64 = *args == 'F' || *args == 'L';
9766 using_gprs = *args == 'F' || *args == 'f';
9768 save_in = input_line_pointer;
9769 input_line_pointer = s;
9770 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
9772 s = input_line_pointer;
9773 input_line_pointer = save_in;
9774 if (err != NULL && *err != '\0')
9776 as_bad (_("Bad floating point constant: %s"), err);
9777 memset (temp, '\0', sizeof temp);
9778 length = f64 ? 8 : 4;
9781 gas_assert (length == (unsigned) (f64 ? 8 : 4));
9785 && (g_switch_value < 4
9786 || (temp[0] == 0 && temp[1] == 0)
9787 || (temp[2] == 0 && temp[3] == 0))))
9789 imm_expr.X_op = O_constant;
9790 if (!target_big_endian)
9791 imm_expr.X_add_number = bfd_getl32 (temp);
9793 imm_expr.X_add_number = bfd_getb32 (temp);
9796 && !mips_disable_float_construction
9797 /* Constants can only be constructed in GPRs and
9798 copied to FPRs if the GPRs are at least as wide
9799 as the FPRs. Force the constant into memory if
9800 we are using 64-bit FPRs but the GPRs are only
9803 || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
9804 && ((temp[0] == 0 && temp[1] == 0)
9805 || (temp[2] == 0 && temp[3] == 0))
9806 && ((temp[4] == 0 && temp[5] == 0)
9807 || (temp[6] == 0 && temp[7] == 0)))
9809 /* The value is simple enough to load with a couple of
9810 instructions. If using 32-bit registers, set
9811 imm_expr to the high order 32 bits and offset_expr to
9812 the low order 32 bits. Otherwise, set imm_expr to
9813 the entire 64 bit constant. */
9814 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
9816 imm_expr.X_op = O_constant;
9817 offset_expr.X_op = O_constant;
9818 if (!target_big_endian)
9820 imm_expr.X_add_number = bfd_getl32 (temp + 4);
9821 offset_expr.X_add_number = bfd_getl32 (temp);
9825 imm_expr.X_add_number = bfd_getb32 (temp);
9826 offset_expr.X_add_number = bfd_getb32 (temp + 4);
9828 if (offset_expr.X_add_number == 0)
9829 offset_expr.X_op = O_absent;
9831 else if (sizeof (imm_expr.X_add_number) > 4)
9833 imm_expr.X_op = O_constant;
9834 if (!target_big_endian)
9835 imm_expr.X_add_number = bfd_getl64 (temp);
9837 imm_expr.X_add_number = bfd_getb64 (temp);
9841 imm_expr.X_op = O_big;
9842 imm_expr.X_add_number = 4;
9843 if (!target_big_endian)
9845 generic_bignum[0] = bfd_getl16 (temp);
9846 generic_bignum[1] = bfd_getl16 (temp + 2);
9847 generic_bignum[2] = bfd_getl16 (temp + 4);
9848 generic_bignum[3] = bfd_getl16 (temp + 6);
9852 generic_bignum[0] = bfd_getb16 (temp + 6);
9853 generic_bignum[1] = bfd_getb16 (temp + 4);
9854 generic_bignum[2] = bfd_getb16 (temp + 2);
9855 generic_bignum[3] = bfd_getb16 (temp);
9861 const char *newname;
9864 /* Switch to the right section. */
9866 subseg = now_subseg;
9869 default: /* unused default case avoids warnings. */
9871 newname = RDATA_SECTION_NAME;
9872 if (g_switch_value >= 8)
9876 newname = RDATA_SECTION_NAME;
9879 gas_assert (g_switch_value >= 4);
9883 new_seg = subseg_new (newname, (subsegT) 0);
9885 bfd_set_section_flags (stdoutput, new_seg,
9890 frag_align (*args == 'l' ? 2 : 3, 0, 0);
9891 if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0)
9892 record_alignment (new_seg, 4);
9894 record_alignment (new_seg, *args == 'l' ? 2 : 3);
9896 as_bad (_("Can't use floating point insn in this section"));
9898 /* Set the argument to the current address in the
9900 offset_expr.X_op = O_symbol;
9901 offset_expr.X_add_symbol = symbol_temp_new_now ();
9902 offset_expr.X_add_number = 0;
9904 /* Put the floating point number into the section. */
9905 p = frag_more ((int) length);
9906 memcpy (p, temp, length);
9908 /* Switch back to the original section. */
9909 subseg_set (seg, subseg);
9914 case 'i': /* 16-bit unsigned immediate. */
9915 case 'j': /* 16-bit signed immediate. */
9916 *imm_reloc = BFD_RELOC_LO16;
9917 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
9920 offsetT minval, maxval;
9922 more = (insn + 1 < &mips_opcodes[NUMOPCODES]
9923 && strcmp (insn->name, insn[1].name) == 0);
9925 /* If the expression was written as an unsigned number,
9926 only treat it as signed if there are no more
9930 && sizeof (imm_expr.X_add_number) <= 4
9931 && imm_expr.X_op == O_constant
9932 && imm_expr.X_add_number < 0
9933 && imm_expr.X_unsigned
9937 /* For compatibility with older assemblers, we accept
9938 0x8000-0xffff as signed 16-bit numbers when only
9939 signed numbers are allowed. */
9941 minval = 0, maxval = 0xffff;
9943 minval = -0x8000, maxval = 0x7fff;
9945 minval = -0x8000, maxval = 0xffff;
9947 if (imm_expr.X_op != O_constant
9948 || imm_expr.X_add_number < minval
9949 || imm_expr.X_add_number > maxval)
9953 if (imm_expr.X_op == O_constant
9954 || imm_expr.X_op == O_big)
9955 as_bad (_("Expression out of range"));
9961 case 'o': /* 16-bit offset. */
9962 offset_reloc[0] = BFD_RELOC_LO16;
9963 offset_reloc[1] = BFD_RELOC_UNUSED;
9964 offset_reloc[2] = BFD_RELOC_UNUSED;
9966 /* Check whether there is only a single bracketed expression
9967 left. If so, it must be the base register and the
9968 constant must be zero. */
9969 offset_reloc[0] = BFD_RELOC_LO16;
9970 offset_reloc[1] = BFD_RELOC_UNUSED;
9971 offset_reloc[2] = BFD_RELOC_UNUSED;
9972 if (*s == '(' && strchr (s + 1, '(') == 0)
9974 offset_expr.X_op = O_constant;
9975 offset_expr.X_add_number = 0;
9979 /* If this value won't fit into a 16 bit offset, then go
9980 find a macro that will generate the 32 bit offset
9982 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
9983 && (offset_expr.X_op != O_constant
9984 || offset_expr.X_add_number >= 0x8000
9985 || offset_expr.X_add_number < -0x8000))
9991 case 'p': /* PC-relative offset. */
9992 *offset_reloc = BFD_RELOC_16_PCREL_S2;
9993 my_getExpression (&offset_expr, s);
9997 case 'u': /* Upper 16 bits. */
9998 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
9999 && imm_expr.X_op == O_constant
10000 && (imm_expr.X_add_number < 0
10001 || imm_expr.X_add_number >= 0x10000))
10002 as_bad (_("lui expression (%lu) not in range 0..65535"),
10003 (unsigned long) imm_expr.X_add_number);
10007 case 'a': /* 26-bit address. */
10008 my_getExpression (&offset_expr, s);
10010 *offset_reloc = BFD_RELOC_MIPS_JMP;
10013 case 'N': /* 3-bit branch condition code. */
10014 case 'M': /* 3-bit compare condition code. */
10016 if (ip->insn_mo->pinfo & (FP_D | FP_S))
10017 rtype |= RTYPE_FCC;
10018 if (!reg_lookup (&s, rtype, ®no))
10020 if ((strcmp (str + strlen (str) - 3, ".ps") == 0
10021 || strcmp (str + strlen (str) - 5, "any2f") == 0
10022 || strcmp (str + strlen (str) - 5, "any2t") == 0)
10023 && (regno & 1) != 0)
10024 as_warn (_("Condition code register should be even for %s, "
10027 if ((strcmp (str + strlen (str) - 5, "any4f") == 0
10028 || strcmp (str + strlen (str) - 5, "any4t") == 0)
10029 && (regno & 3) != 0)
10030 as_warn (_("Condition code register should be 0 or 4 for %s, "
10034 INSERT_OPERAND (BCC, *ip, regno);
10036 INSERT_OPERAND (CCC, *ip, regno);
10040 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
10051 while (ISDIGIT (*s));
10054 c = 8; /* Invalid sel value. */
10057 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
10058 ip->insn_opcode |= c;
10062 /* Must be at least one digit. */
10063 my_getExpression (&imm_expr, s);
10064 check_absolute_expr (ip, &imm_expr);
10066 if ((unsigned long) imm_expr.X_add_number
10067 > (unsigned long) OP_MASK_VECBYTE)
10069 as_bad (_("bad byte vector index (%ld)"),
10070 (long) imm_expr.X_add_number);
10071 imm_expr.X_add_number = 0;
10074 INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number);
10075 imm_expr.X_op = O_absent;
10080 my_getExpression (&imm_expr, s);
10081 check_absolute_expr (ip, &imm_expr);
10083 if ((unsigned long) imm_expr.X_add_number
10084 > (unsigned long) OP_MASK_VECALIGN)
10086 as_bad (_("bad byte vector index (%ld)"),
10087 (long) imm_expr.X_add_number);
10088 imm_expr.X_add_number = 0;
10091 INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number);
10092 imm_expr.X_op = O_absent;
10097 as_bad (_("Bad char = '%c'\n"), *args);
10102 /* Args don't match. */
10103 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
10104 !strcmp (insn->name, insn[1].name))
10108 insn_error = _("Illegal operands");
10112 *(--argsStart) = save_c;
10113 insn_error = _("Illegal operands");
10118 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
10120 /* This routine assembles an instruction into its binary format when
10121 assembling for the mips16. As a side effect, it sets one of the
10122 global variables imm_reloc or offset_reloc to the type of
10123 relocation to do if one of the operands is an address expression.
10124 It also sets mips16_small and mips16_ext if the user explicitly
10125 requested a small or extended instruction. */
10128 mips16_ip (char *str, struct mips_cl_insn *ip)
10132 struct mips_opcode *insn;
10134 unsigned int regno;
10135 unsigned int lastregno = 0;
10141 mips16_small = FALSE;
10142 mips16_ext = FALSE;
10144 for (s = str; ISLOWER (*s); ++s)
10156 if (s[1] == 't' && s[2] == ' ')
10159 mips16_small = TRUE;
10163 else if (s[1] == 'e' && s[2] == ' ')
10170 /* Fall through. */
10172 insn_error = _("unknown opcode");
10176 if (mips_opts.noautoextend && ! mips16_ext)
10177 mips16_small = TRUE;
10179 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
10181 insn_error = _("unrecognized opcode");
10190 gas_assert (strcmp (insn->name, str) == 0);
10192 ok = is_opcode_valid_16 (insn);
10195 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
10196 && strcmp (insn->name, insn[1].name) == 0)
10205 static char buf[100];
10207 _("opcode not supported on this processor: %s (%s)"),
10208 mips_cpu_info_from_arch (mips_opts.arch)->name,
10209 mips_cpu_info_from_isa (mips_opts.isa)->name);
10216 create_insn (ip, insn);
10217 imm_expr.X_op = O_absent;
10218 imm_reloc[0] = BFD_RELOC_UNUSED;
10219 imm_reloc[1] = BFD_RELOC_UNUSED;
10220 imm_reloc[2] = BFD_RELOC_UNUSED;
10221 imm2_expr.X_op = O_absent;
10222 offset_expr.X_op = O_absent;
10223 offset_reloc[0] = BFD_RELOC_UNUSED;
10224 offset_reloc[1] = BFD_RELOC_UNUSED;
10225 offset_reloc[2] = BFD_RELOC_UNUSED;
10226 for (args = insn->args; 1; ++args)
10233 /* In this switch statement we call break if we did not find
10234 a match, continue if we did find a match, or return if we
10243 /* Stuff the immediate value in now, if we can. */
10244 if (imm_expr.X_op == O_constant
10245 && *imm_reloc > BFD_RELOC_UNUSED
10246 && *imm_reloc != BFD_RELOC_MIPS16_GOT16
10247 && *imm_reloc != BFD_RELOC_MIPS16_CALL16
10248 && insn->pinfo != INSN_MACRO)
10252 switch (*offset_reloc)
10254 case BFD_RELOC_MIPS16_HI16_S:
10255 tmp = (imm_expr.X_add_number + 0x8000) >> 16;
10258 case BFD_RELOC_MIPS16_HI16:
10259 tmp = imm_expr.X_add_number >> 16;
10262 case BFD_RELOC_MIPS16_LO16:
10263 tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff)
10267 case BFD_RELOC_UNUSED:
10268 tmp = imm_expr.X_add_number;
10274 *offset_reloc = BFD_RELOC_UNUSED;
10276 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
10277 tmp, TRUE, mips16_small,
10278 mips16_ext, &ip->insn_opcode,
10279 &ip->use_extend, &ip->extend);
10280 imm_expr.X_op = O_absent;
10281 *imm_reloc = BFD_RELOC_UNUSED;
10295 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10298 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10314 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10316 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10320 /* Fall through. */
10331 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
10333 if (c == 'v' || c == 'w')
10336 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10338 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10349 if (c == 'v' || c == 'w')
10351 regno = mips16_to_32_reg_map[lastregno];
10365 regno = mips32_to_16_reg_map[regno];
10370 regno = ILLEGAL_REG;
10375 regno = ILLEGAL_REG;
10380 regno = ILLEGAL_REG;
10385 if (regno == AT && mips_opts.at)
10387 if (mips_opts.at == ATREG)
10388 as_warn (_("used $at without \".set noat\""));
10390 as_warn (_("used $%u with \".set at=$%u\""),
10391 regno, mips_opts.at);
10399 if (regno == ILLEGAL_REG)
10406 MIPS16_INSERT_OPERAND (RX, *ip, regno);
10410 MIPS16_INSERT_OPERAND (RY, *ip, regno);
10413 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
10416 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
10422 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
10425 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
10426 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
10436 if (strncmp (s, "$pc", 3) == 0)
10453 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
10456 if (imm_expr.X_op != O_constant)
10459 ip->use_extend = TRUE;
10464 /* We need to relax this instruction. */
10465 *offset_reloc = *imm_reloc;
10466 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10471 *imm_reloc = BFD_RELOC_UNUSED;
10472 /* Fall through. */
10479 my_getExpression (&imm_expr, s);
10480 if (imm_expr.X_op == O_register)
10482 /* What we thought was an expression turned out to
10485 if (s[0] == '(' && args[1] == '(')
10487 /* It looks like the expression was omitted
10488 before a register indirection, which means
10489 that the expression is implicitly zero. We
10490 still set up imm_expr, so that we handle
10491 explicit extensions correctly. */
10492 imm_expr.X_op = O_constant;
10493 imm_expr.X_add_number = 0;
10494 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10501 /* We need to relax this instruction. */
10502 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10511 /* We use offset_reloc rather than imm_reloc for the PC
10512 relative operands. This lets macros with both
10513 immediate and address operands work correctly. */
10514 my_getExpression (&offset_expr, s);
10516 if (offset_expr.X_op == O_register)
10519 /* We need to relax this instruction. */
10520 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
10524 case '6': /* break code */
10525 my_getExpression (&imm_expr, s);
10526 check_absolute_expr (ip, &imm_expr);
10527 if ((unsigned long) imm_expr.X_add_number > 63)
10528 as_warn (_("Invalid value for `%s' (%lu)"),
10530 (unsigned long) imm_expr.X_add_number);
10531 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
10532 imm_expr.X_op = O_absent;
10536 case 'a': /* 26 bit address */
10537 my_getExpression (&offset_expr, s);
10539 *offset_reloc = BFD_RELOC_MIPS16_JMP;
10540 ip->insn_opcode <<= 16;
10543 case 'l': /* register list for entry macro */
10544 case 'L': /* register list for exit macro */
10554 unsigned int freg, reg1, reg2;
10556 while (*s == ' ' || *s == ',')
10558 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
10560 else if (reg_lookup (&s, RTYPE_FPU, ®1))
10564 as_bad (_("can't parse register list"));
10574 if (!reg_lookup (&s, freg ? RTYPE_FPU
10575 : (RTYPE_GP | RTYPE_NUM), ®2))
10577 as_bad (_("invalid register list"));
10581 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
10583 mask &= ~ (7 << 3);
10586 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
10588 mask &= ~ (7 << 3);
10591 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
10592 mask |= (reg2 - 3) << 3;
10593 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
10594 mask |= (reg2 - 15) << 1;
10595 else if (reg1 == RA && reg2 == RA)
10599 as_bad (_("invalid register list"));
10603 /* The mask is filled in in the opcode table for the
10604 benefit of the disassembler. We remove it before
10605 applying the actual mask. */
10606 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
10607 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
10611 case 'm': /* Register list for save insn. */
10612 case 'M': /* Register list for restore insn. */
10615 int framesz = 0, seen_framesz = 0;
10616 int nargs = 0, statics = 0, sregs = 0;
10620 unsigned int reg1, reg2;
10622 SKIP_SPACE_TABS (s);
10625 SKIP_SPACE_TABS (s);
10627 my_getExpression (&imm_expr, s);
10628 if (imm_expr.X_op == O_constant)
10630 /* Handle the frame size. */
10633 as_bad (_("more than one frame size in list"));
10637 framesz = imm_expr.X_add_number;
10638 imm_expr.X_op = O_absent;
10643 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
10645 as_bad (_("can't parse register list"));
10657 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2)
10660 as_bad (_("can't parse register list"));
10665 while (reg1 <= reg2)
10667 if (reg1 >= 4 && reg1 <= 7)
10671 nargs |= 1 << (reg1 - 4);
10673 /* statics $a0-$a3 */
10674 statics |= 1 << (reg1 - 4);
10676 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
10679 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
10681 else if (reg1 == 31)
10683 /* Add $ra to insn. */
10688 as_bad (_("unexpected register in list"));
10696 /* Encode args/statics combination. */
10697 if (nargs & statics)
10698 as_bad (_("arg/static registers overlap"));
10699 else if (nargs == 0xf)
10700 /* All $a0-$a3 are args. */
10701 opcode |= MIPS16_ALL_ARGS << 16;
10702 else if (statics == 0xf)
10703 /* All $a0-$a3 are statics. */
10704 opcode |= MIPS16_ALL_STATICS << 16;
10707 int narg = 0, nstat = 0;
10709 /* Count arg registers. */
10710 while (nargs & 0x1)
10716 as_bad (_("invalid arg register list"));
10718 /* Count static registers. */
10719 while (statics & 0x8)
10721 statics = (statics << 1) & 0xf;
10725 as_bad (_("invalid static register list"));
10727 /* Encode args/statics. */
10728 opcode |= ((narg << 2) | nstat) << 16;
10731 /* Encode $s0/$s1. */
10732 if (sregs & (1 << 0)) /* $s0 */
10734 if (sregs & (1 << 1)) /* $s1 */
10740 /* Count regs $s2-$s8. */
10748 as_bad (_("invalid static register list"));
10749 /* Encode $s2-$s8. */
10750 opcode |= nsreg << 24;
10753 /* Encode frame size. */
10755 as_bad (_("missing frame size"));
10756 else if ((framesz & 7) != 0 || framesz < 0
10757 || framesz > 0xff * 8)
10758 as_bad (_("invalid frame size"));
10759 else if (framesz != 128 || (opcode >> 16) != 0)
10762 opcode |= (((framesz & 0xf0) << 16)
10763 | (framesz & 0x0f));
10766 /* Finally build the instruction. */
10767 if ((opcode >> 16) != 0 || framesz == 0)
10769 ip->use_extend = TRUE;
10770 ip->extend = opcode >> 16;
10772 ip->insn_opcode |= opcode & 0x7f;
10776 case 'e': /* extend code */
10777 my_getExpression (&imm_expr, s);
10778 check_absolute_expr (ip, &imm_expr);
10779 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
10781 as_warn (_("Invalid value for `%s' (%lu)"),
10783 (unsigned long) imm_expr.X_add_number);
10784 imm_expr.X_add_number &= 0x7ff;
10786 ip->insn_opcode |= imm_expr.X_add_number;
10787 imm_expr.X_op = O_absent;
10797 /* Args don't match. */
10798 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
10799 strcmp (insn->name, insn[1].name) == 0)
10806 insn_error = _("illegal operands");
10812 /* This structure holds information we know about a mips16 immediate
10815 struct mips16_immed_operand
10817 /* The type code used in the argument string in the opcode table. */
10819 /* The number of bits in the short form of the opcode. */
10821 /* The number of bits in the extended form of the opcode. */
10823 /* The amount by which the short form is shifted when it is used;
10824 for example, the sw instruction has a shift count of 2. */
10826 /* The amount by which the short form is shifted when it is stored
10827 into the instruction code. */
10829 /* Non-zero if the short form is unsigned. */
10831 /* Non-zero if the extended form is unsigned. */
10833 /* Non-zero if the value is PC relative. */
10837 /* The mips16 immediate operand types. */
10839 static const struct mips16_immed_operand mips16_immed_operands[] =
10841 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
10842 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
10843 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
10844 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
10845 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
10846 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
10847 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
10848 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
10849 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
10850 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
10851 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
10852 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
10853 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
10854 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
10855 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
10856 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
10857 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
10858 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
10859 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
10860 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
10861 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
10864 #define MIPS16_NUM_IMMED \
10865 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
10867 /* Handle a mips16 instruction with an immediate value. This or's the
10868 small immediate value into *INSN. It sets *USE_EXTEND to indicate
10869 whether an extended value is needed; if one is needed, it sets
10870 *EXTEND to the value. The argument type is TYPE. The value is VAL.
10871 If SMALL is true, an unextended opcode was explicitly requested.
10872 If EXT is true, an extended opcode was explicitly requested. If
10873 WARN is true, warn if EXT does not match reality. */
10876 mips16_immed (char *file, unsigned int line, int type, offsetT val,
10877 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
10878 unsigned long *insn, bfd_boolean *use_extend,
10879 unsigned short *extend)
10881 const struct mips16_immed_operand *op;
10882 int mintiny, maxtiny;
10883 bfd_boolean needext;
10885 op = mips16_immed_operands;
10886 while (op->type != type)
10889 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
10894 if (type == '<' || type == '>' || type == '[' || type == ']')
10897 maxtiny = 1 << op->nbits;
10902 maxtiny = (1 << op->nbits) - 1;
10907 mintiny = - (1 << (op->nbits - 1));
10908 maxtiny = (1 << (op->nbits - 1)) - 1;
10911 /* Branch offsets have an implicit 0 in the lowest bit. */
10912 if (type == 'p' || type == 'q')
10915 if ((val & ((1 << op->shift) - 1)) != 0
10916 || val < (mintiny << op->shift)
10917 || val > (maxtiny << op->shift))
10922 if (warn && ext && ! needext)
10923 as_warn_where (file, line,
10924 _("extended operand requested but not required"));
10925 if (small && needext)
10926 as_bad_where (file, line, _("invalid unextended operand value"));
10928 if (small || (! ext && ! needext))
10932 *use_extend = FALSE;
10933 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
10934 insnval <<= op->op_shift;
10939 long minext, maxext;
10945 maxext = (1 << op->extbits) - 1;
10949 minext = - (1 << (op->extbits - 1));
10950 maxext = (1 << (op->extbits - 1)) - 1;
10952 if (val < minext || val > maxext)
10953 as_bad_where (file, line,
10954 _("operand value out of range for instruction"));
10956 *use_extend = TRUE;
10957 if (op->extbits == 16)
10959 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
10962 else if (op->extbits == 15)
10964 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
10969 extval = ((val & 0x1f) << 6) | (val & 0x20);
10973 *extend = (unsigned short) extval;
10978 struct percent_op_match
10981 bfd_reloc_code_real_type reloc;
10984 static const struct percent_op_match mips_percent_op[] =
10986 {"%lo", BFD_RELOC_LO16},
10988 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
10989 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
10990 {"%call16", BFD_RELOC_MIPS_CALL16},
10991 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
10992 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
10993 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
10994 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
10995 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
10996 {"%got", BFD_RELOC_MIPS_GOT16},
10997 {"%gp_rel", BFD_RELOC_GPREL16},
10998 {"%half", BFD_RELOC_16},
10999 {"%highest", BFD_RELOC_MIPS_HIGHEST},
11000 {"%higher", BFD_RELOC_MIPS_HIGHER},
11001 {"%neg", BFD_RELOC_MIPS_SUB},
11002 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
11003 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
11004 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
11005 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
11006 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
11007 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
11008 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
11010 {"%hi", BFD_RELOC_HI16_S}
11013 static const struct percent_op_match mips16_percent_op[] =
11015 {"%lo", BFD_RELOC_MIPS16_LO16},
11016 {"%gprel", BFD_RELOC_MIPS16_GPREL},
11017 {"%got", BFD_RELOC_MIPS16_GOT16},
11018 {"%call16", BFD_RELOC_MIPS16_CALL16},
11019 {"%hi", BFD_RELOC_MIPS16_HI16_S}
11023 /* Return true if *STR points to a relocation operator. When returning true,
11024 move *STR over the operator and store its relocation code in *RELOC.
11025 Leave both *STR and *RELOC alone when returning false. */
11028 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
11030 const struct percent_op_match *percent_op;
11033 if (mips_opts.mips16)
11035 percent_op = mips16_percent_op;
11036 limit = ARRAY_SIZE (mips16_percent_op);
11040 percent_op = mips_percent_op;
11041 limit = ARRAY_SIZE (mips_percent_op);
11044 for (i = 0; i < limit; i++)
11045 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
11047 int len = strlen (percent_op[i].str);
11049 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
11052 *str += strlen (percent_op[i].str);
11053 *reloc = percent_op[i].reloc;
11055 /* Check whether the output BFD supports this relocation.
11056 If not, issue an error and fall back on something safe. */
11057 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
11059 as_bad (_("relocation %s isn't supported by the current ABI"),
11060 percent_op[i].str);
11061 *reloc = BFD_RELOC_UNUSED;
11069 /* Parse string STR as a 16-bit relocatable operand. Store the
11070 expression in *EP and the relocations in the array starting
11071 at RELOC. Return the number of relocation operators used.
11073 On exit, EXPR_END points to the first character after the expression. */
11076 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
11079 bfd_reloc_code_real_type reversed_reloc[3];
11080 size_t reloc_index, i;
11081 int crux_depth, str_depth;
11084 /* Search for the start of the main expression, recoding relocations
11085 in REVERSED_RELOC. End the loop with CRUX pointing to the start
11086 of the main expression and with CRUX_DEPTH containing the number
11087 of open brackets at that point. */
11094 crux_depth = str_depth;
11096 /* Skip over whitespace and brackets, keeping count of the number
11098 while (*str == ' ' || *str == '\t' || *str == '(')
11103 && reloc_index < (HAVE_NEWABI ? 3 : 1)
11104 && parse_relocation (&str, &reversed_reloc[reloc_index]));
11106 my_getExpression (ep, crux);
11109 /* Match every open bracket. */
11110 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
11114 if (crux_depth > 0)
11115 as_bad (_("unclosed '('"));
11119 if (reloc_index != 0)
11121 prev_reloc_op_frag = frag_now;
11122 for (i = 0; i < reloc_index; i++)
11123 reloc[i] = reversed_reloc[reloc_index - 1 - i];
11126 return reloc_index;
11130 my_getExpression (expressionS *ep, char *str)
11135 save_in = input_line_pointer;
11136 input_line_pointer = str;
11138 expr_end = input_line_pointer;
11139 input_line_pointer = save_in;
11141 /* If we are in mips16 mode, and this is an expression based on `.',
11142 then we bump the value of the symbol by 1 since that is how other
11143 text symbols are handled. We don't bother to handle complex
11144 expressions, just `.' plus or minus a constant. */
11145 if (mips_opts.mips16
11146 && ep->X_op == O_symbol
11147 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
11148 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg
11149 && symbol_get_frag (ep->X_add_symbol) == frag_now
11150 && symbol_constant_p (ep->X_add_symbol)
11151 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
11152 S_SET_VALUE (ep->X_add_symbol, val + 1);
11156 md_atof (int type, char *litP, int *sizeP)
11158 return ieee_md_atof (type, litP, sizeP, target_big_endian);
11162 md_number_to_chars (char *buf, valueT val, int n)
11164 if (target_big_endian)
11165 number_to_chars_bigendian (buf, val, n);
11167 number_to_chars_littleendian (buf, val, n);
11171 static int support_64bit_objects(void)
11173 const char **list, **l;
11176 list = bfd_target_list ();
11177 for (l = list; *l != NULL; l++)
11179 /* This is traditional mips */
11180 if (strcmp (*l, "elf64-tradbigmips") == 0
11181 || strcmp (*l, "elf64-tradlittlemips") == 0)
11183 if (strcmp (*l, "elf64-bigmips") == 0
11184 || strcmp (*l, "elf64-littlemips") == 0)
11187 yes = (*l != NULL);
11191 #endif /* OBJ_ELF */
11193 const char *md_shortopts = "O::g::G:";
11197 OPTION_MARCH = OPTION_MD_BASE,
11219 OPTION_NO_SMARTMIPS,
11222 OPTION_COMPAT_ARCH_BASE,
11231 OPTION_M7000_HILO_FIX,
11232 OPTION_MNO_7000_HILO_FIX,
11235 OPTION_FIX_LOONGSON2F_JUMP,
11236 OPTION_NO_FIX_LOONGSON2F_JUMP,
11237 OPTION_FIX_LOONGSON2F_NOP,
11238 OPTION_NO_FIX_LOONGSON2F_NOP,
11240 OPTION_NO_FIX_VR4120,
11242 OPTION_NO_FIX_VR4130,
11243 OPTION_FIX_CN63XXP1,
11244 OPTION_NO_FIX_CN63XXP1,
11251 OPTION_CONSTRUCT_FLOATS,
11252 OPTION_NO_CONSTRUCT_FLOATS,
11255 OPTION_RELAX_BRANCH,
11256 OPTION_NO_RELAX_BRANCH,
11263 OPTION_SINGLE_FLOAT,
11264 OPTION_DOUBLE_FLOAT,
11267 OPTION_CALL_SHARED,
11268 OPTION_CALL_NONPIC,
11278 OPTION_MVXWORKS_PIC,
11279 #endif /* OBJ_ELF */
11283 struct option md_longopts[] =
11285 /* Options which specify architecture. */
11286 {"march", required_argument, NULL, OPTION_MARCH},
11287 {"mtune", required_argument, NULL, OPTION_MTUNE},
11288 {"mips0", no_argument, NULL, OPTION_MIPS1},
11289 {"mips1", no_argument, NULL, OPTION_MIPS1},
11290 {"mips2", no_argument, NULL, OPTION_MIPS2},
11291 {"mips3", no_argument, NULL, OPTION_MIPS3},
11292 {"mips4", no_argument, NULL, OPTION_MIPS4},
11293 {"mips5", no_argument, NULL, OPTION_MIPS5},
11294 {"mips32", no_argument, NULL, OPTION_MIPS32},
11295 {"mips64", no_argument, NULL, OPTION_MIPS64},
11296 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
11297 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
11299 /* Options which specify Application Specific Extensions (ASEs). */
11300 {"mips16", no_argument, NULL, OPTION_MIPS16},
11301 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
11302 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
11303 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
11304 {"mdmx", no_argument, NULL, OPTION_MDMX},
11305 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
11306 {"mdsp", no_argument, NULL, OPTION_DSP},
11307 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
11308 {"mmt", no_argument, NULL, OPTION_MT},
11309 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
11310 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
11311 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
11312 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
11313 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
11315 /* Old-style architecture options. Don't add more of these. */
11316 {"m4650", no_argument, NULL, OPTION_M4650},
11317 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
11318 {"m4010", no_argument, NULL, OPTION_M4010},
11319 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
11320 {"m4100", no_argument, NULL, OPTION_M4100},
11321 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
11322 {"m3900", no_argument, NULL, OPTION_M3900},
11323 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
11325 /* Options which enable bug fixes. */
11326 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
11327 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
11328 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
11329 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
11330 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
11331 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
11332 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
11333 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
11334 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
11335 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
11336 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
11337 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
11338 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
11339 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
11340 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
11342 /* Miscellaneous options. */
11343 {"trap", no_argument, NULL, OPTION_TRAP},
11344 {"no-break", no_argument, NULL, OPTION_TRAP},
11345 {"break", no_argument, NULL, OPTION_BREAK},
11346 {"no-trap", no_argument, NULL, OPTION_BREAK},
11347 {"EB", no_argument, NULL, OPTION_EB},
11348 {"EL", no_argument, NULL, OPTION_EL},
11349 {"mfp32", no_argument, NULL, OPTION_FP32},
11350 {"mgp32", no_argument, NULL, OPTION_GP32},
11351 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
11352 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
11353 {"mfp64", no_argument, NULL, OPTION_FP64},
11354 {"mgp64", no_argument, NULL, OPTION_GP64},
11355 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
11356 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
11357 {"mshared", no_argument, NULL, OPTION_MSHARED},
11358 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
11359 {"msym32", no_argument, NULL, OPTION_MSYM32},
11360 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
11361 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
11362 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
11363 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
11364 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
11366 /* Strictly speaking this next option is ELF specific,
11367 but we allow it for other ports as well in order to
11368 make testing easier. */
11369 {"32", no_argument, NULL, OPTION_32},
11371 /* ELF-specific options. */
11373 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
11374 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
11375 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
11376 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
11377 {"xgot", no_argument, NULL, OPTION_XGOT},
11378 {"mabi", required_argument, NULL, OPTION_MABI},
11379 {"n32", no_argument, NULL, OPTION_N32},
11380 {"64", no_argument, NULL, OPTION_64},
11381 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
11382 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
11383 {"mpdr", no_argument, NULL, OPTION_PDR},
11384 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
11385 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
11386 #endif /* OBJ_ELF */
11388 {NULL, no_argument, NULL, 0}
11390 size_t md_longopts_size = sizeof (md_longopts);
11392 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
11393 NEW_VALUE. Warn if another value was already specified. Note:
11394 we have to defer parsing the -march and -mtune arguments in order
11395 to handle 'from-abi' correctly, since the ABI might be specified
11396 in a later argument. */
11399 mips_set_option_string (const char **string_ptr, const char *new_value)
11401 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
11402 as_warn (_("A different %s was already specified, is now %s"),
11403 string_ptr == &mips_arch_string ? "-march" : "-mtune",
11406 *string_ptr = new_value;
11410 md_parse_option (int c, char *arg)
11414 case OPTION_CONSTRUCT_FLOATS:
11415 mips_disable_float_construction = 0;
11418 case OPTION_NO_CONSTRUCT_FLOATS:
11419 mips_disable_float_construction = 1;
11431 target_big_endian = 1;
11435 target_big_endian = 0;
11441 else if (arg[0] == '0')
11443 else if (arg[0] == '1')
11453 mips_debug = atoi (arg);
11457 file_mips_isa = ISA_MIPS1;
11461 file_mips_isa = ISA_MIPS2;
11465 file_mips_isa = ISA_MIPS3;
11469 file_mips_isa = ISA_MIPS4;
11473 file_mips_isa = ISA_MIPS5;
11476 case OPTION_MIPS32:
11477 file_mips_isa = ISA_MIPS32;
11480 case OPTION_MIPS32R2:
11481 file_mips_isa = ISA_MIPS32R2;
11484 case OPTION_MIPS64R2:
11485 file_mips_isa = ISA_MIPS64R2;
11488 case OPTION_MIPS64:
11489 file_mips_isa = ISA_MIPS64;
11493 mips_set_option_string (&mips_tune_string, arg);
11497 mips_set_option_string (&mips_arch_string, arg);
11501 mips_set_option_string (&mips_arch_string, "4650");
11502 mips_set_option_string (&mips_tune_string, "4650");
11505 case OPTION_NO_M4650:
11509 mips_set_option_string (&mips_arch_string, "4010");
11510 mips_set_option_string (&mips_tune_string, "4010");
11513 case OPTION_NO_M4010:
11517 mips_set_option_string (&mips_arch_string, "4100");
11518 mips_set_option_string (&mips_tune_string, "4100");
11521 case OPTION_NO_M4100:
11525 mips_set_option_string (&mips_arch_string, "3900");
11526 mips_set_option_string (&mips_tune_string, "3900");
11529 case OPTION_NO_M3900:
11533 mips_opts.ase_mdmx = 1;
11536 case OPTION_NO_MDMX:
11537 mips_opts.ase_mdmx = 0;
11541 mips_opts.ase_dsp = 1;
11542 mips_opts.ase_dspr2 = 0;
11545 case OPTION_NO_DSP:
11546 mips_opts.ase_dsp = 0;
11547 mips_opts.ase_dspr2 = 0;
11551 mips_opts.ase_dspr2 = 1;
11552 mips_opts.ase_dsp = 1;
11555 case OPTION_NO_DSPR2:
11556 mips_opts.ase_dspr2 = 0;
11557 mips_opts.ase_dsp = 0;
11561 mips_opts.ase_mt = 1;
11565 mips_opts.ase_mt = 0;
11568 case OPTION_MIPS16:
11569 mips_opts.mips16 = 1;
11570 mips_no_prev_insn ();
11573 case OPTION_NO_MIPS16:
11574 mips_opts.mips16 = 0;
11575 mips_no_prev_insn ();
11578 case OPTION_MIPS3D:
11579 mips_opts.ase_mips3d = 1;
11582 case OPTION_NO_MIPS3D:
11583 mips_opts.ase_mips3d = 0;
11586 case OPTION_SMARTMIPS:
11587 mips_opts.ase_smartmips = 1;
11590 case OPTION_NO_SMARTMIPS:
11591 mips_opts.ase_smartmips = 0;
11594 case OPTION_FIX_24K:
11598 case OPTION_NO_FIX_24K:
11602 case OPTION_FIX_LOONGSON2F_JUMP:
11603 mips_fix_loongson2f_jump = TRUE;
11606 case OPTION_NO_FIX_LOONGSON2F_JUMP:
11607 mips_fix_loongson2f_jump = FALSE;
11610 case OPTION_FIX_LOONGSON2F_NOP:
11611 mips_fix_loongson2f_nop = TRUE;
11614 case OPTION_NO_FIX_LOONGSON2F_NOP:
11615 mips_fix_loongson2f_nop = FALSE;
11618 case OPTION_FIX_VR4120:
11619 mips_fix_vr4120 = 1;
11622 case OPTION_NO_FIX_VR4120:
11623 mips_fix_vr4120 = 0;
11626 case OPTION_FIX_VR4130:
11627 mips_fix_vr4130 = 1;
11630 case OPTION_NO_FIX_VR4130:
11631 mips_fix_vr4130 = 0;
11634 case OPTION_FIX_CN63XXP1:
11635 mips_fix_cn63xxp1 = TRUE;
11638 case OPTION_NO_FIX_CN63XXP1:
11639 mips_fix_cn63xxp1 = FALSE;
11642 case OPTION_RELAX_BRANCH:
11643 mips_relax_branch = 1;
11646 case OPTION_NO_RELAX_BRANCH:
11647 mips_relax_branch = 0;
11650 case OPTION_MSHARED:
11651 mips_in_shared = TRUE;
11654 case OPTION_MNO_SHARED:
11655 mips_in_shared = FALSE;
11658 case OPTION_MSYM32:
11659 mips_opts.sym32 = TRUE;
11662 case OPTION_MNO_SYM32:
11663 mips_opts.sym32 = FALSE;
11667 /* When generating ELF code, we permit -KPIC and -call_shared to
11668 select SVR4_PIC, and -non_shared to select no PIC. This is
11669 intended to be compatible with Irix 5. */
11670 case OPTION_CALL_SHARED:
11673 as_bad (_("-call_shared is supported only for ELF format"));
11676 mips_pic = SVR4_PIC;
11677 mips_abicalls = TRUE;
11680 case OPTION_CALL_NONPIC:
11683 as_bad (_("-call_nonpic is supported only for ELF format"));
11687 mips_abicalls = TRUE;
11690 case OPTION_NON_SHARED:
11693 as_bad (_("-non_shared is supported only for ELF format"));
11697 mips_abicalls = FALSE;
11700 /* The -xgot option tells the assembler to use 32 bit offsets
11701 when accessing the got in SVR4_PIC mode. It is for Irix
11706 #endif /* OBJ_ELF */
11709 g_switch_value = atoi (arg);
11713 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
11717 mips_abi = O32_ABI;
11718 /* We silently ignore -32 for non-ELF targets. This greatly
11719 simplifies the construction of the MIPS GAS test cases. */
11726 as_bad (_("-n32 is supported for ELF format only"));
11729 mips_abi = N32_ABI;
11735 as_bad (_("-64 is supported for ELF format only"));
11738 mips_abi = N64_ABI;
11739 if (!support_64bit_objects())
11740 as_fatal (_("No compiled in support for 64 bit object file format"));
11742 #endif /* OBJ_ELF */
11745 file_mips_gp32 = 1;
11749 file_mips_gp32 = 0;
11753 file_mips_fp32 = 1;
11757 file_mips_fp32 = 0;
11760 case OPTION_SINGLE_FLOAT:
11761 file_mips_single_float = 1;
11764 case OPTION_DOUBLE_FLOAT:
11765 file_mips_single_float = 0;
11768 case OPTION_SOFT_FLOAT:
11769 file_mips_soft_float = 1;
11772 case OPTION_HARD_FLOAT:
11773 file_mips_soft_float = 0;
11780 as_bad (_("-mabi is supported for ELF format only"));
11783 if (strcmp (arg, "32") == 0)
11784 mips_abi = O32_ABI;
11785 else if (strcmp (arg, "o64") == 0)
11786 mips_abi = O64_ABI;
11787 else if (strcmp (arg, "n32") == 0)
11788 mips_abi = N32_ABI;
11789 else if (strcmp (arg, "64") == 0)
11791 mips_abi = N64_ABI;
11792 if (! support_64bit_objects())
11793 as_fatal (_("No compiled in support for 64 bit object file "
11796 else if (strcmp (arg, "eabi") == 0)
11797 mips_abi = EABI_ABI;
11800 as_fatal (_("invalid abi -mabi=%s"), arg);
11804 #endif /* OBJ_ELF */
11806 case OPTION_M7000_HILO_FIX:
11807 mips_7000_hilo_fix = TRUE;
11810 case OPTION_MNO_7000_HILO_FIX:
11811 mips_7000_hilo_fix = FALSE;
11815 case OPTION_MDEBUG:
11816 mips_flag_mdebug = TRUE;
11819 case OPTION_NO_MDEBUG:
11820 mips_flag_mdebug = FALSE;
11824 mips_flag_pdr = TRUE;
11827 case OPTION_NO_PDR:
11828 mips_flag_pdr = FALSE;
11831 case OPTION_MVXWORKS_PIC:
11832 mips_pic = VXWORKS_PIC;
11834 #endif /* OBJ_ELF */
11840 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
11845 /* Set up globals to generate code for the ISA or processor
11846 described by INFO. */
11849 mips_set_architecture (const struct mips_cpu_info *info)
11853 file_mips_arch = info->cpu;
11854 mips_opts.arch = info->cpu;
11855 mips_opts.isa = info->isa;
11860 /* Likewise for tuning. */
11863 mips_set_tune (const struct mips_cpu_info *info)
11866 mips_tune = info->cpu;
11871 mips_after_parse_args (void)
11873 const struct mips_cpu_info *arch_info = 0;
11874 const struct mips_cpu_info *tune_info = 0;
11876 /* GP relative stuff not working for PE */
11877 if (strncmp (TARGET_OS, "pe", 2) == 0)
11879 if (g_switch_seen && g_switch_value != 0)
11880 as_bad (_("-G not supported in this configuration."));
11881 g_switch_value = 0;
11884 if (mips_abi == NO_ABI)
11885 mips_abi = MIPS_DEFAULT_ABI;
11887 /* The following code determines the architecture and register size.
11888 Similar code was added to GCC 3.3 (see override_options() in
11889 config/mips/mips.c). The GAS and GCC code should be kept in sync
11890 as much as possible. */
11892 if (mips_arch_string != 0)
11893 arch_info = mips_parse_cpu ("-march", mips_arch_string);
11895 if (file_mips_isa != ISA_UNKNOWN)
11897 /* Handle -mipsN. At this point, file_mips_isa contains the
11898 ISA level specified by -mipsN, while arch_info->isa contains
11899 the -march selection (if any). */
11900 if (arch_info != 0)
11902 /* -march takes precedence over -mipsN, since it is more descriptive.
11903 There's no harm in specifying both as long as the ISA levels
11905 if (file_mips_isa != arch_info->isa)
11906 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
11907 mips_cpu_info_from_isa (file_mips_isa)->name,
11908 mips_cpu_info_from_isa (arch_info->isa)->name);
11911 arch_info = mips_cpu_info_from_isa (file_mips_isa);
11914 if (arch_info == 0)
11915 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
11917 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
11918 as_bad (_("-march=%s is not compatible with the selected ABI"),
11921 mips_set_architecture (arch_info);
11923 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
11924 if (mips_tune_string != 0)
11925 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
11927 if (tune_info == 0)
11928 mips_set_tune (arch_info);
11930 mips_set_tune (tune_info);
11932 if (file_mips_gp32 >= 0)
11934 /* The user specified the size of the integer registers. Make sure
11935 it agrees with the ABI and ISA. */
11936 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
11937 as_bad (_("-mgp64 used with a 32-bit processor"));
11938 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
11939 as_bad (_("-mgp32 used with a 64-bit ABI"));
11940 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
11941 as_bad (_("-mgp64 used with a 32-bit ABI"));
11945 /* Infer the integer register size from the ABI and processor.
11946 Restrict ourselves to 32-bit registers if that's all the
11947 processor has, or if the ABI cannot handle 64-bit registers. */
11948 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
11949 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
11952 switch (file_mips_fp32)
11956 /* No user specified float register size.
11957 ??? GAS treats single-float processors as though they had 64-bit
11958 float registers (although it complains when double-precision
11959 instructions are used). As things stand, saying they have 32-bit
11960 registers would lead to spurious "register must be even" messages.
11961 So here we assume float registers are never smaller than the
11963 if (file_mips_gp32 == 0)
11964 /* 64-bit integer registers implies 64-bit float registers. */
11965 file_mips_fp32 = 0;
11966 else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
11967 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
11968 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
11969 file_mips_fp32 = 0;
11971 /* 32-bit float registers. */
11972 file_mips_fp32 = 1;
11975 /* The user specified the size of the float registers. Check if it
11976 agrees with the ABI and ISA. */
11978 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
11979 as_bad (_("-mfp64 used with a 32-bit fpu"));
11980 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
11981 && !ISA_HAS_MXHC1 (mips_opts.isa))
11982 as_warn (_("-mfp64 used with a 32-bit ABI"));
11985 if (ABI_NEEDS_64BIT_REGS (mips_abi))
11986 as_warn (_("-mfp32 used with a 64-bit ABI"));
11990 /* End of GCC-shared inference code. */
11992 /* This flag is set when we have a 64-bit capable CPU but use only
11993 32-bit wide registers. Note that EABI does not use it. */
11994 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
11995 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
11996 || mips_abi == O32_ABI))
11997 mips_32bitmode = 1;
11999 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
12000 as_bad (_("trap exception not supported at ISA 1"));
12002 /* If the selected architecture includes support for ASEs, enable
12003 generation of code for them. */
12004 if (mips_opts.mips16 == -1)
12005 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
12006 if (mips_opts.ase_mips3d == -1)
12007 mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
12008 && file_mips_fp32 == 0) ? 1 : 0;
12009 if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
12010 as_bad (_("-mfp32 used with -mips3d"));
12012 if (mips_opts.ase_mdmx == -1)
12013 mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
12014 && file_mips_fp32 == 0) ? 1 : 0;
12015 if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
12016 as_bad (_("-mfp32 used with -mdmx"));
12018 if (mips_opts.ase_smartmips == -1)
12019 mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
12020 if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
12021 as_warn (_("%s ISA does not support SmartMIPS"),
12022 mips_cpu_info_from_isa (mips_opts.isa)->name);
12024 if (mips_opts.ase_dsp == -1)
12025 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
12026 if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
12027 as_warn (_("%s ISA does not support DSP ASE"),
12028 mips_cpu_info_from_isa (mips_opts.isa)->name);
12030 if (mips_opts.ase_dspr2 == -1)
12032 mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
12033 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
12035 if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
12036 as_warn (_("%s ISA does not support DSP R2 ASE"),
12037 mips_cpu_info_from_isa (mips_opts.isa)->name);
12039 if (mips_opts.ase_mt == -1)
12040 mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
12041 if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
12042 as_warn (_("%s ISA does not support MT ASE"),
12043 mips_cpu_info_from_isa (mips_opts.isa)->name);
12045 file_mips_isa = mips_opts.isa;
12046 file_ase_mips16 = mips_opts.mips16;
12047 file_ase_mips3d = mips_opts.ase_mips3d;
12048 file_ase_mdmx = mips_opts.ase_mdmx;
12049 file_ase_smartmips = mips_opts.ase_smartmips;
12050 file_ase_dsp = mips_opts.ase_dsp;
12051 file_ase_dspr2 = mips_opts.ase_dspr2;
12052 file_ase_mt = mips_opts.ase_mt;
12053 mips_opts.gp32 = file_mips_gp32;
12054 mips_opts.fp32 = file_mips_fp32;
12055 mips_opts.soft_float = file_mips_soft_float;
12056 mips_opts.single_float = file_mips_single_float;
12058 if (mips_flag_mdebug < 0)
12060 #ifdef OBJ_MAYBE_ECOFF
12061 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
12062 mips_flag_mdebug = 1;
12064 #endif /* OBJ_MAYBE_ECOFF */
12065 mips_flag_mdebug = 0;
12070 mips_init_after_args (void)
12072 /* initialize opcodes */
12073 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
12074 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
12078 md_pcrel_from (fixS *fixP)
12080 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
12081 switch (fixP->fx_r_type)
12083 case BFD_RELOC_16_PCREL_S2:
12084 case BFD_RELOC_MIPS_JMP:
12085 /* Return the address of the delay slot. */
12088 /* We have no relocation type for PC relative MIPS16 instructions. */
12089 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
12090 as_bad_where (fixP->fx_file, fixP->fx_line,
12091 _("PC relative MIPS16 instruction references a different section"));
12096 /* This is called before the symbol table is processed. In order to
12097 work with gcc when using mips-tfile, we must keep all local labels.
12098 However, in other cases, we want to discard them. If we were
12099 called with -g, but we didn't see any debugging information, it may
12100 mean that gcc is smuggling debugging information through to
12101 mips-tfile, in which case we must generate all local labels. */
12104 mips_frob_file_before_adjust (void)
12106 #ifndef NO_ECOFF_DEBUGGING
12107 if (ECOFF_DEBUGGING
12109 && ! ecoff_debugging_seen)
12110 flag_keep_locals = 1;
12114 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
12115 the corresponding LO16 reloc. This is called before md_apply_fix and
12116 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
12117 relocation operators.
12119 For our purposes, a %lo() expression matches a %got() or %hi()
12122 (a) it refers to the same symbol; and
12123 (b) the offset applied in the %lo() expression is no lower than
12124 the offset applied in the %got() or %hi().
12126 (b) allows us to cope with code like:
12129 lh $4,%lo(foo+2)($4)
12131 ...which is legal on RELA targets, and has a well-defined behaviour
12132 if the user knows that adding 2 to "foo" will not induce a carry to
12135 When several %lo()s match a particular %got() or %hi(), we use the
12136 following rules to distinguish them:
12138 (1) %lo()s with smaller offsets are a better match than %lo()s with
12141 (2) %lo()s with no matching %got() or %hi() are better than those
12142 that already have a matching %got() or %hi().
12144 (3) later %lo()s are better than earlier %lo()s.
12146 These rules are applied in order.
12148 (1) means, among other things, that %lo()s with identical offsets are
12149 chosen if they exist.
12151 (2) means that we won't associate several high-part relocations with
12152 the same low-part relocation unless there's no alternative. Having
12153 several high parts for the same low part is a GNU extension; this rule
12154 allows careful users to avoid it.
12156 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
12157 with the last high-part relocation being at the front of the list.
12158 It therefore makes sense to choose the last matching low-part
12159 relocation, all other things being equal. It's also easier
12160 to code that way. */
12163 mips_frob_file (void)
12165 struct mips_hi_fixup *l;
12166 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
12168 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
12170 segment_info_type *seginfo;
12171 bfd_boolean matched_lo_p;
12172 fixS **hi_pos, **lo_pos, **pos;
12174 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
12176 /* If a GOT16 relocation turns out to be against a global symbol,
12177 there isn't supposed to be a matching LO. */
12178 if (got16_reloc_p (l->fixp->fx_r_type)
12179 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
12182 /* Check quickly whether the next fixup happens to be a matching %lo. */
12183 if (fixup_has_matching_lo_p (l->fixp))
12186 seginfo = seg_info (l->seg);
12188 /* Set HI_POS to the position of this relocation in the chain.
12189 Set LO_POS to the position of the chosen low-part relocation.
12190 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
12191 relocation that matches an immediately-preceding high-part
12195 matched_lo_p = FALSE;
12196 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
12198 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
12200 if (*pos == l->fixp)
12203 if ((*pos)->fx_r_type == looking_for_rtype
12204 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
12205 && (*pos)->fx_offset >= l->fixp->fx_offset
12207 || (*pos)->fx_offset < (*lo_pos)->fx_offset
12209 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
12212 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
12213 && fixup_has_matching_lo_p (*pos));
12216 /* If we found a match, remove the high-part relocation from its
12217 current position and insert it before the low-part relocation.
12218 Make the offsets match so that fixup_has_matching_lo_p()
12221 We don't warn about unmatched high-part relocations since some
12222 versions of gcc have been known to emit dead "lui ...%hi(...)"
12224 if (lo_pos != NULL)
12226 l->fixp->fx_offset = (*lo_pos)->fx_offset;
12227 if (l->fixp->fx_next != *lo_pos)
12229 *hi_pos = l->fixp->fx_next;
12230 l->fixp->fx_next = *lo_pos;
12237 /* We may have combined relocations without symbols in the N32/N64 ABI.
12238 We have to prevent gas from dropping them. */
12241 mips_force_relocation (fixS *fixp)
12243 if (generic_force_reloc (fixp))
12247 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
12248 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
12249 || hi16_reloc_p (fixp->fx_r_type)
12250 || lo16_reloc_p (fixp->fx_r_type)))
12256 /* Apply a fixup to the object file. */
12259 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
12263 reloc_howto_type *howto;
12265 /* We ignore generic BFD relocations we don't know about. */
12266 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
12270 gas_assert (fixP->fx_size == 4
12271 || fixP->fx_r_type == BFD_RELOC_16
12272 || fixP->fx_r_type == BFD_RELOC_64
12273 || fixP->fx_r_type == BFD_RELOC_CTOR
12274 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
12275 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12276 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
12277 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
12279 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
12281 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2);
12283 /* Don't treat parts of a composite relocation as done. There are two
12286 (1) The second and third parts will be against 0 (RSS_UNDEF) but
12287 should nevertheless be emitted if the first part is.
12289 (2) In normal usage, composite relocations are never assembly-time
12290 constants. The easiest way of dealing with the pathological
12291 exceptions is to generate a relocation against STN_UNDEF and
12292 leave everything up to the linker. */
12293 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
12296 switch (fixP->fx_r_type)
12298 case BFD_RELOC_MIPS_TLS_GD:
12299 case BFD_RELOC_MIPS_TLS_LDM:
12300 case BFD_RELOC_MIPS_TLS_DTPREL32:
12301 case BFD_RELOC_MIPS_TLS_DTPREL64:
12302 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
12303 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
12304 case BFD_RELOC_MIPS_TLS_GOTTPREL:
12305 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
12306 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
12307 S_SET_THREAD_LOCAL (fixP->fx_addsy);
12310 case BFD_RELOC_MIPS_JMP:
12311 case BFD_RELOC_MIPS_SHIFT5:
12312 case BFD_RELOC_MIPS_SHIFT6:
12313 case BFD_RELOC_MIPS_GOT_DISP:
12314 case BFD_RELOC_MIPS_GOT_PAGE:
12315 case BFD_RELOC_MIPS_GOT_OFST:
12316 case BFD_RELOC_MIPS_SUB:
12317 case BFD_RELOC_MIPS_INSERT_A:
12318 case BFD_RELOC_MIPS_INSERT_B:
12319 case BFD_RELOC_MIPS_DELETE:
12320 case BFD_RELOC_MIPS_HIGHEST:
12321 case BFD_RELOC_MIPS_HIGHER:
12322 case BFD_RELOC_MIPS_SCN_DISP:
12323 case BFD_RELOC_MIPS_REL16:
12324 case BFD_RELOC_MIPS_RELGOT:
12325 case BFD_RELOC_MIPS_JALR:
12326 case BFD_RELOC_HI16:
12327 case BFD_RELOC_HI16_S:
12328 case BFD_RELOC_GPREL16:
12329 case BFD_RELOC_MIPS_LITERAL:
12330 case BFD_RELOC_MIPS_CALL16:
12331 case BFD_RELOC_MIPS_GOT16:
12332 case BFD_RELOC_GPREL32:
12333 case BFD_RELOC_MIPS_GOT_HI16:
12334 case BFD_RELOC_MIPS_GOT_LO16:
12335 case BFD_RELOC_MIPS_CALL_HI16:
12336 case BFD_RELOC_MIPS_CALL_LO16:
12337 case BFD_RELOC_MIPS16_GPREL:
12338 case BFD_RELOC_MIPS16_GOT16:
12339 case BFD_RELOC_MIPS16_CALL16:
12340 case BFD_RELOC_MIPS16_HI16:
12341 case BFD_RELOC_MIPS16_HI16_S:
12342 case BFD_RELOC_MIPS16_JMP:
12343 /* Nothing needed to do. The value comes from the reloc entry. */
12347 /* This is handled like BFD_RELOC_32, but we output a sign
12348 extended value if we are only 32 bits. */
12351 if (8 <= sizeof (valueT))
12352 md_number_to_chars ((char *) buf, *valP, 8);
12357 if ((*valP & 0x80000000) != 0)
12361 md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)),
12363 md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)),
12369 case BFD_RELOC_RVA:
12372 /* If we are deleting this reloc entry, we must fill in the
12373 value now. This can happen if we have a .word which is not
12374 resolved when it appears but is later defined. */
12376 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
12379 case BFD_RELOC_LO16:
12380 case BFD_RELOC_MIPS16_LO16:
12381 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
12382 may be safe to remove, but if so it's not obvious. */
12383 /* When handling an embedded PIC switch statement, we can wind
12384 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
12387 if (*valP + 0x8000 > 0xffff)
12388 as_bad_where (fixP->fx_file, fixP->fx_line,
12389 _("relocation overflow"));
12390 if (target_big_endian)
12392 md_number_to_chars ((char *) buf, *valP, 2);
12396 case BFD_RELOC_16_PCREL_S2:
12397 if ((*valP & 0x3) != 0)
12398 as_bad_where (fixP->fx_file, fixP->fx_line,
12399 _("Branch to misaligned address (%lx)"), (long) *valP);
12401 /* We need to save the bits in the instruction since fixup_segment()
12402 might be deleting the relocation entry (i.e., a branch within
12403 the current segment). */
12404 if (! fixP->fx_done)
12407 /* Update old instruction data. */
12408 if (target_big_endian)
12409 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
12411 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
12413 if (*valP + 0x20000 <= 0x3ffff)
12415 insn |= (*valP >> 2) & 0xffff;
12416 md_number_to_chars ((char *) buf, insn, 4);
12418 else if (mips_pic == NO_PIC
12420 && fixP->fx_frag->fr_address >= text_section->vma
12421 && (fixP->fx_frag->fr_address
12422 < text_section->vma + bfd_get_section_size (text_section))
12423 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
12424 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
12425 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
12427 /* The branch offset is too large. If this is an
12428 unconditional branch, and we are not generating PIC code,
12429 we can convert it to an absolute jump instruction. */
12430 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
12431 insn = 0x0c000000; /* jal */
12433 insn = 0x08000000; /* j */
12434 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
12436 fixP->fx_addsy = section_symbol (text_section);
12437 *valP += md_pcrel_from (fixP);
12438 md_number_to_chars ((char *) buf, insn, 4);
12442 /* If we got here, we have branch-relaxation disabled,
12443 and there's nothing we can do to fix this instruction
12444 without turning it into a longer sequence. */
12445 as_bad_where (fixP->fx_file, fixP->fx_line,
12446 _("Branch out of range"));
12450 case BFD_RELOC_VTABLE_INHERIT:
12453 && !S_IS_DEFINED (fixP->fx_addsy)
12454 && !S_IS_WEAK (fixP->fx_addsy))
12455 S_SET_WEAK (fixP->fx_addsy);
12458 case BFD_RELOC_VTABLE_ENTRY:
12466 /* Remember value for tc_gen_reloc. */
12467 fixP->fx_addnumber = *valP;
12477 name = input_line_pointer;
12478 c = get_symbol_end ();
12479 p = (symbolS *) symbol_find_or_make (name);
12480 *input_line_pointer = c;
12484 /* Align the current frag to a given power of two. If a particular
12485 fill byte should be used, FILL points to an integer that contains
12486 that byte, otherwise FILL is null.
12488 The MIPS assembler also automatically adjusts any preceding
12492 mips_align (int to, int *fill, symbolS *label)
12494 mips_emit_delays ();
12495 mips_record_mips16_mode ();
12496 if (fill == NULL && subseg_text_p (now_seg))
12497 frag_align_code (to, 0);
12499 frag_align (to, fill ? *fill : 0, 0);
12500 record_alignment (now_seg, to);
12503 gas_assert (S_GET_SEGMENT (label) == now_seg);
12504 symbol_set_frag (label, frag_now);
12505 S_SET_VALUE (label, (valueT) frag_now_fix ());
12509 /* Align to a given power of two. .align 0 turns off the automatic
12510 alignment used by the data creating pseudo-ops. */
12513 s_align (int x ATTRIBUTE_UNUSED)
12515 int temp, fill_value, *fill_ptr;
12516 long max_alignment = 28;
12518 /* o Note that the assembler pulls down any immediately preceding label
12519 to the aligned address.
12520 o It's not documented but auto alignment is reinstated by
12521 a .align pseudo instruction.
12522 o Note also that after auto alignment is turned off the mips assembler
12523 issues an error on attempt to assemble an improperly aligned data item.
12526 temp = get_absolute_expression ();
12527 if (temp > max_alignment)
12528 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
12531 as_warn (_("Alignment negative: 0 assumed."));
12534 if (*input_line_pointer == ',')
12536 ++input_line_pointer;
12537 fill_value = get_absolute_expression ();
12538 fill_ptr = &fill_value;
12544 segment_info_type *si = seg_info (now_seg);
12545 struct insn_label_list *l = si->label_list;
12546 /* Auto alignment should be switched on by next section change. */
12548 mips_align (temp, fill_ptr, l != NULL ? l->label : NULL);
12555 demand_empty_rest_of_line ();
12559 s_change_sec (int sec)
12564 /* The ELF backend needs to know that we are changing sections, so
12565 that .previous works correctly. We could do something like check
12566 for an obj_section_change_hook macro, but that might be confusing
12567 as it would not be appropriate to use it in the section changing
12568 functions in read.c, since obj-elf.c intercepts those. FIXME:
12569 This should be cleaner, somehow. */
12571 obj_elf_section_change_hook ();
12574 mips_emit_delays ();
12585 subseg_set (bss_section, (subsegT) get_absolute_expression ());
12586 demand_empty_rest_of_line ();
12590 seg = subseg_new (RDATA_SECTION_NAME,
12591 (subsegT) get_absolute_expression ());
12594 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
12595 | SEC_READONLY | SEC_RELOC
12597 if (strncmp (TARGET_OS, "elf", 3) != 0)
12598 record_alignment (seg, 4);
12600 demand_empty_rest_of_line ();
12604 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
12607 bfd_set_section_flags (stdoutput, seg,
12608 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
12609 if (strncmp (TARGET_OS, "elf", 3) != 0)
12610 record_alignment (seg, 4);
12612 demand_empty_rest_of_line ();
12616 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
12619 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
12620 if (strncmp (TARGET_OS, "elf", 3) != 0)
12621 record_alignment (seg, 4);
12623 demand_empty_rest_of_line ();
12631 s_change_section (int ignore ATTRIBUTE_UNUSED)
12634 char *section_name;
12639 int section_entry_size;
12640 int section_alignment;
12645 section_name = input_line_pointer;
12646 c = get_symbol_end ();
12648 next_c = *(input_line_pointer + 1);
12650 /* Do we have .section Name<,"flags">? */
12651 if (c != ',' || (c == ',' && next_c == '"'))
12653 /* just after name is now '\0'. */
12654 *input_line_pointer = c;
12655 input_line_pointer = section_name;
12656 obj_elf_section (ignore);
12659 input_line_pointer++;
12661 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
12663 section_type = get_absolute_expression ();
12666 if (*input_line_pointer++ == ',')
12667 section_flag = get_absolute_expression ();
12670 if (*input_line_pointer++ == ',')
12671 section_entry_size = get_absolute_expression ();
12673 section_entry_size = 0;
12674 if (*input_line_pointer++ == ',')
12675 section_alignment = get_absolute_expression ();
12677 section_alignment = 0;
12678 /* FIXME: really ignore? */
12679 (void) section_alignment;
12681 section_name = xstrdup (section_name);
12683 /* When using the generic form of .section (as implemented by obj-elf.c),
12684 there's no way to set the section type to SHT_MIPS_DWARF. Users have
12685 traditionally had to fall back on the more common @progbits instead.
12687 There's nothing really harmful in this, since bfd will correct
12688 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
12689 means that, for backwards compatibility, the special_section entries
12690 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
12692 Even so, we shouldn't force users of the MIPS .section syntax to
12693 incorrectly label the sections as SHT_PROGBITS. The best compromise
12694 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
12695 generic type-checking code. */
12696 if (section_type == SHT_MIPS_DWARF)
12697 section_type = SHT_PROGBITS;
12699 obj_elf_change_section (section_name, section_type, section_flag,
12700 section_entry_size, 0, 0, 0);
12702 if (now_seg->name != section_name)
12703 free (section_name);
12704 #endif /* OBJ_ELF */
12708 mips_enable_auto_align (void)
12714 s_cons (int log_size)
12716 segment_info_type *si = seg_info (now_seg);
12717 struct insn_label_list *l = si->label_list;
12720 label = l != NULL ? l->label : NULL;
12721 mips_emit_delays ();
12722 if (log_size > 0 && auto_align)
12723 mips_align (log_size, 0, label);
12724 mips_clear_insn_labels ();
12725 cons (1 << log_size);
12729 s_float_cons (int type)
12731 segment_info_type *si = seg_info (now_seg);
12732 struct insn_label_list *l = si->label_list;
12735 label = l != NULL ? l->label : NULL;
12737 mips_emit_delays ();
12742 mips_align (3, 0, label);
12744 mips_align (2, 0, label);
12747 mips_clear_insn_labels ();
12752 /* Handle .globl. We need to override it because on Irix 5 you are
12755 where foo is an undefined symbol, to mean that foo should be
12756 considered to be the address of a function. */
12759 s_mips_globl (int x ATTRIBUTE_UNUSED)
12768 name = input_line_pointer;
12769 c = get_symbol_end ();
12770 symbolP = symbol_find_or_make (name);
12771 S_SET_EXTERNAL (symbolP);
12773 *input_line_pointer = c;
12774 SKIP_WHITESPACE ();
12776 /* On Irix 5, every global symbol that is not explicitly labelled as
12777 being a function is apparently labelled as being an object. */
12780 if (!is_end_of_line[(unsigned char) *input_line_pointer]
12781 && (*input_line_pointer != ','))
12786 secname = input_line_pointer;
12787 c = get_symbol_end ();
12788 sec = bfd_get_section_by_name (stdoutput, secname);
12790 as_bad (_("%s: no such section"), secname);
12791 *input_line_pointer = c;
12793 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
12794 flag = BSF_FUNCTION;
12797 symbol_get_bfdsym (symbolP)->flags |= flag;
12799 c = *input_line_pointer;
12802 input_line_pointer++;
12803 SKIP_WHITESPACE ();
12804 if (is_end_of_line[(unsigned char) *input_line_pointer])
12810 demand_empty_rest_of_line ();
12814 s_option (int x ATTRIBUTE_UNUSED)
12819 opt = input_line_pointer;
12820 c = get_symbol_end ();
12824 /* FIXME: What does this mean? */
12826 else if (strncmp (opt, "pic", 3) == 0)
12830 i = atoi (opt + 3);
12835 mips_pic = SVR4_PIC;
12836 mips_abicalls = TRUE;
12839 as_bad (_(".option pic%d not supported"), i);
12841 if (mips_pic == SVR4_PIC)
12843 if (g_switch_seen && g_switch_value != 0)
12844 as_warn (_("-G may not be used with SVR4 PIC code"));
12845 g_switch_value = 0;
12846 bfd_set_gp_size (stdoutput, 0);
12850 as_warn (_("Unrecognized option \"%s\""), opt);
12852 *input_line_pointer = c;
12853 demand_empty_rest_of_line ();
12856 /* This structure is used to hold a stack of .set values. */
12858 struct mips_option_stack
12860 struct mips_option_stack *next;
12861 struct mips_set_options options;
12864 static struct mips_option_stack *mips_opts_stack;
12866 /* Handle the .set pseudo-op. */
12869 s_mipsset (int x ATTRIBUTE_UNUSED)
12871 char *name = input_line_pointer, ch;
12873 while (!is_end_of_line[(unsigned char) *input_line_pointer])
12874 ++input_line_pointer;
12875 ch = *input_line_pointer;
12876 *input_line_pointer = '\0';
12878 if (strcmp (name, "reorder") == 0)
12880 if (mips_opts.noreorder)
12883 else if (strcmp (name, "noreorder") == 0)
12885 if (!mips_opts.noreorder)
12886 start_noreorder ();
12888 else if (strncmp (name, "at=", 3) == 0)
12890 char *s = name + 3;
12892 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
12893 as_bad (_("Unrecognized register name `%s'"), s);
12895 else if (strcmp (name, "at") == 0)
12897 mips_opts.at = ATREG;
12899 else if (strcmp (name, "noat") == 0)
12901 mips_opts.at = ZERO;
12903 else if (strcmp (name, "macro") == 0)
12905 mips_opts.warn_about_macros = 0;
12907 else if (strcmp (name, "nomacro") == 0)
12909 if (mips_opts.noreorder == 0)
12910 as_bad (_("`noreorder' must be set before `nomacro'"));
12911 mips_opts.warn_about_macros = 1;
12913 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
12915 mips_opts.nomove = 0;
12917 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
12919 mips_opts.nomove = 1;
12921 else if (strcmp (name, "bopt") == 0)
12923 mips_opts.nobopt = 0;
12925 else if (strcmp (name, "nobopt") == 0)
12927 mips_opts.nobopt = 1;
12929 else if (strcmp (name, "gp=default") == 0)
12930 mips_opts.gp32 = file_mips_gp32;
12931 else if (strcmp (name, "gp=32") == 0)
12932 mips_opts.gp32 = 1;
12933 else if (strcmp (name, "gp=64") == 0)
12935 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
12936 as_warn (_("%s isa does not support 64-bit registers"),
12937 mips_cpu_info_from_isa (mips_opts.isa)->name);
12938 mips_opts.gp32 = 0;
12940 else if (strcmp (name, "fp=default") == 0)
12941 mips_opts.fp32 = file_mips_fp32;
12942 else if (strcmp (name, "fp=32") == 0)
12943 mips_opts.fp32 = 1;
12944 else if (strcmp (name, "fp=64") == 0)
12946 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
12947 as_warn (_("%s isa does not support 64-bit floating point registers"),
12948 mips_cpu_info_from_isa (mips_opts.isa)->name);
12949 mips_opts.fp32 = 0;
12951 else if (strcmp (name, "softfloat") == 0)
12952 mips_opts.soft_float = 1;
12953 else if (strcmp (name, "hardfloat") == 0)
12954 mips_opts.soft_float = 0;
12955 else if (strcmp (name, "singlefloat") == 0)
12956 mips_opts.single_float = 1;
12957 else if (strcmp (name, "doublefloat") == 0)
12958 mips_opts.single_float = 0;
12959 else if (strcmp (name, "mips16") == 0
12960 || strcmp (name, "MIPS-16") == 0)
12961 mips_opts.mips16 = 1;
12962 else if (strcmp (name, "nomips16") == 0
12963 || strcmp (name, "noMIPS-16") == 0)
12964 mips_opts.mips16 = 0;
12965 else if (strcmp (name, "smartmips") == 0)
12967 if (!ISA_SUPPORTS_SMARTMIPS)
12968 as_warn (_("%s ISA does not support SmartMIPS ASE"),
12969 mips_cpu_info_from_isa (mips_opts.isa)->name);
12970 mips_opts.ase_smartmips = 1;
12972 else if (strcmp (name, "nosmartmips") == 0)
12973 mips_opts.ase_smartmips = 0;
12974 else if (strcmp (name, "mips3d") == 0)
12975 mips_opts.ase_mips3d = 1;
12976 else if (strcmp (name, "nomips3d") == 0)
12977 mips_opts.ase_mips3d = 0;
12978 else if (strcmp (name, "mdmx") == 0)
12979 mips_opts.ase_mdmx = 1;
12980 else if (strcmp (name, "nomdmx") == 0)
12981 mips_opts.ase_mdmx = 0;
12982 else if (strcmp (name, "dsp") == 0)
12984 if (!ISA_SUPPORTS_DSP_ASE)
12985 as_warn (_("%s ISA does not support DSP ASE"),
12986 mips_cpu_info_from_isa (mips_opts.isa)->name);
12987 mips_opts.ase_dsp = 1;
12988 mips_opts.ase_dspr2 = 0;
12990 else if (strcmp (name, "nodsp") == 0)
12992 mips_opts.ase_dsp = 0;
12993 mips_opts.ase_dspr2 = 0;
12995 else if (strcmp (name, "dspr2") == 0)
12997 if (!ISA_SUPPORTS_DSPR2_ASE)
12998 as_warn (_("%s ISA does not support DSP R2 ASE"),
12999 mips_cpu_info_from_isa (mips_opts.isa)->name);
13000 mips_opts.ase_dspr2 = 1;
13001 mips_opts.ase_dsp = 1;
13003 else if (strcmp (name, "nodspr2") == 0)
13005 mips_opts.ase_dspr2 = 0;
13006 mips_opts.ase_dsp = 0;
13008 else if (strcmp (name, "mt") == 0)
13010 if (!ISA_SUPPORTS_MT_ASE)
13011 as_warn (_("%s ISA does not support MT ASE"),
13012 mips_cpu_info_from_isa (mips_opts.isa)->name);
13013 mips_opts.ase_mt = 1;
13015 else if (strcmp (name, "nomt") == 0)
13016 mips_opts.ase_mt = 0;
13017 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
13021 /* Permit the user to change the ISA and architecture on the fly.
13022 Needless to say, misuse can cause serious problems. */
13023 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
13026 mips_opts.isa = file_mips_isa;
13027 mips_opts.arch = file_mips_arch;
13029 else if (strncmp (name, "arch=", 5) == 0)
13031 const struct mips_cpu_info *p;
13033 p = mips_parse_cpu("internal use", name + 5);
13035 as_bad (_("unknown architecture %s"), name + 5);
13038 mips_opts.arch = p->cpu;
13039 mips_opts.isa = p->isa;
13042 else if (strncmp (name, "mips", 4) == 0)
13044 const struct mips_cpu_info *p;
13046 p = mips_parse_cpu("internal use", name);
13048 as_bad (_("unknown ISA level %s"), name + 4);
13051 mips_opts.arch = p->cpu;
13052 mips_opts.isa = p->isa;
13056 as_bad (_("unknown ISA or architecture %s"), name);
13058 switch (mips_opts.isa)
13066 mips_opts.gp32 = 1;
13067 mips_opts.fp32 = 1;
13074 mips_opts.gp32 = 0;
13075 mips_opts.fp32 = 0;
13078 as_bad (_("unknown ISA level %s"), name + 4);
13083 mips_opts.gp32 = file_mips_gp32;
13084 mips_opts.fp32 = file_mips_fp32;
13087 else if (strcmp (name, "autoextend") == 0)
13088 mips_opts.noautoextend = 0;
13089 else if (strcmp (name, "noautoextend") == 0)
13090 mips_opts.noautoextend = 1;
13091 else if (strcmp (name, "push") == 0)
13093 struct mips_option_stack *s;
13095 s = (struct mips_option_stack *) xmalloc (sizeof *s);
13096 s->next = mips_opts_stack;
13097 s->options = mips_opts;
13098 mips_opts_stack = s;
13100 else if (strcmp (name, "pop") == 0)
13102 struct mips_option_stack *s;
13104 s = mips_opts_stack;
13106 as_bad (_(".set pop with no .set push"));
13109 /* If we're changing the reorder mode we need to handle
13110 delay slots correctly. */
13111 if (s->options.noreorder && ! mips_opts.noreorder)
13112 start_noreorder ();
13113 else if (! s->options.noreorder && mips_opts.noreorder)
13116 mips_opts = s->options;
13117 mips_opts_stack = s->next;
13121 else if (strcmp (name, "sym32") == 0)
13122 mips_opts.sym32 = TRUE;
13123 else if (strcmp (name, "nosym32") == 0)
13124 mips_opts.sym32 = FALSE;
13125 else if (strchr (name, ','))
13127 /* Generic ".set" directive; use the generic handler. */
13128 *input_line_pointer = ch;
13129 input_line_pointer = name;
13135 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
13137 *input_line_pointer = ch;
13138 demand_empty_rest_of_line ();
13141 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
13142 .option pic2. It means to generate SVR4 PIC calls. */
13145 s_abicalls (int ignore ATTRIBUTE_UNUSED)
13147 mips_pic = SVR4_PIC;
13148 mips_abicalls = TRUE;
13150 if (g_switch_seen && g_switch_value != 0)
13151 as_warn (_("-G may not be used with SVR4 PIC code"));
13152 g_switch_value = 0;
13154 bfd_set_gp_size (stdoutput, 0);
13155 demand_empty_rest_of_line ();
13158 /* Handle the .cpload pseudo-op. This is used when generating SVR4
13159 PIC code. It sets the $gp register for the function based on the
13160 function address, which is in the register named in the argument.
13161 This uses a relocation against _gp_disp, which is handled specially
13162 by the linker. The result is:
13163 lui $gp,%hi(_gp_disp)
13164 addiu $gp,$gp,%lo(_gp_disp)
13165 addu $gp,$gp,.cpload argument
13166 The .cpload argument is normally $25 == $t9.
13168 The -mno-shared option changes this to:
13169 lui $gp,%hi(__gnu_local_gp)
13170 addiu $gp,$gp,%lo(__gnu_local_gp)
13171 and the argument is ignored. This saves an instruction, but the
13172 resulting code is not position independent; it uses an absolute
13173 address for __gnu_local_gp. Thus code assembled with -mno-shared
13174 can go into an ordinary executable, but not into a shared library. */
13177 s_cpload (int ignore ATTRIBUTE_UNUSED)
13183 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13184 .cpload is ignored. */
13185 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
13191 /* .cpload should be in a .set noreorder section. */
13192 if (mips_opts.noreorder == 0)
13193 as_warn (_(".cpload not in noreorder section"));
13195 reg = tc_get_register (0);
13197 /* If we need to produce a 64-bit address, we are better off using
13198 the default instruction sequence. */
13199 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
13201 ex.X_op = O_symbol;
13202 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
13204 ex.X_op_symbol = NULL;
13205 ex.X_add_number = 0;
13207 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13208 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
13211 macro_build_lui (&ex, mips_gp_register);
13212 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
13213 mips_gp_register, BFD_RELOC_LO16);
13215 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
13216 mips_gp_register, reg);
13219 demand_empty_rest_of_line ();
13222 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
13223 .cpsetup $reg1, offset|$reg2, label
13225 If offset is given, this results in:
13226 sd $gp, offset($sp)
13227 lui $gp, %hi(%neg(%gp_rel(label)))
13228 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13229 daddu $gp, $gp, $reg1
13231 If $reg2 is given, this results in:
13232 daddu $reg2, $gp, $0
13233 lui $gp, %hi(%neg(%gp_rel(label)))
13234 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13235 daddu $gp, $gp, $reg1
13236 $reg1 is normally $25 == $t9.
13238 The -mno-shared option replaces the last three instructions with
13240 addiu $gp,$gp,%lo(_gp) */
13243 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
13245 expressionS ex_off;
13246 expressionS ex_sym;
13249 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
13250 We also need NewABI support. */
13251 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13257 reg1 = tc_get_register (0);
13258 SKIP_WHITESPACE ();
13259 if (*input_line_pointer != ',')
13261 as_bad (_("missing argument separator ',' for .cpsetup"));
13265 ++input_line_pointer;
13266 SKIP_WHITESPACE ();
13267 if (*input_line_pointer == '$')
13269 mips_cpreturn_register = tc_get_register (0);
13270 mips_cpreturn_offset = -1;
13274 mips_cpreturn_offset = get_absolute_expression ();
13275 mips_cpreturn_register = -1;
13277 SKIP_WHITESPACE ();
13278 if (*input_line_pointer != ',')
13280 as_bad (_("missing argument separator ',' for .cpsetup"));
13284 ++input_line_pointer;
13285 SKIP_WHITESPACE ();
13286 expression (&ex_sym);
13289 if (mips_cpreturn_register == -1)
13291 ex_off.X_op = O_constant;
13292 ex_off.X_add_symbol = NULL;
13293 ex_off.X_op_symbol = NULL;
13294 ex_off.X_add_number = mips_cpreturn_offset;
13296 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
13297 BFD_RELOC_LO16, SP);
13300 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
13301 mips_gp_register, 0);
13303 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
13305 macro_build (&ex_sym, "lui", "t,u", mips_gp_register,
13306 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
13309 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
13310 mips_gp_register, -1, BFD_RELOC_GPREL16,
13311 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
13313 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
13314 mips_gp_register, reg1);
13320 ex.X_op = O_symbol;
13321 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
13322 ex.X_op_symbol = NULL;
13323 ex.X_add_number = 0;
13325 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13326 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
13328 macro_build_lui (&ex, mips_gp_register);
13329 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
13330 mips_gp_register, BFD_RELOC_LO16);
13335 demand_empty_rest_of_line ();
13339 s_cplocal (int ignore ATTRIBUTE_UNUSED)
13341 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
13342 .cplocal is ignored. */
13343 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13349 mips_gp_register = tc_get_register (0);
13350 demand_empty_rest_of_line ();
13353 /* Handle the .cprestore pseudo-op. This stores $gp into a given
13354 offset from $sp. The offset is remembered, and after making a PIC
13355 call $gp is restored from that location. */
13358 s_cprestore (int ignore ATTRIBUTE_UNUSED)
13362 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13363 .cprestore is ignored. */
13364 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
13370 mips_cprestore_offset = get_absolute_expression ();
13371 mips_cprestore_valid = 1;
13373 ex.X_op = O_constant;
13374 ex.X_add_symbol = NULL;
13375 ex.X_op_symbol = NULL;
13376 ex.X_add_number = mips_cprestore_offset;
13379 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
13380 SP, HAVE_64BIT_ADDRESSES);
13383 demand_empty_rest_of_line ();
13386 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
13387 was given in the preceding .cpsetup, it results in:
13388 ld $gp, offset($sp)
13390 If a register $reg2 was given there, it results in:
13391 daddu $gp, $reg2, $0 */
13394 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
13398 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
13399 We also need NewABI support. */
13400 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13407 if (mips_cpreturn_register == -1)
13409 ex.X_op = O_constant;
13410 ex.X_add_symbol = NULL;
13411 ex.X_op_symbol = NULL;
13412 ex.X_add_number = mips_cpreturn_offset;
13414 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
13417 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
13418 mips_cpreturn_register, 0);
13421 demand_empty_rest_of_line ();
13424 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
13425 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
13426 use in DWARF debug information. */
13429 s_dtprel_internal (size_t bytes)
13436 if (ex.X_op != O_symbol)
13438 as_bad (_("Unsupported use of %s"), (bytes == 8
13441 ignore_rest_of_line ();
13444 p = frag_more (bytes);
13445 md_number_to_chars (p, 0, bytes);
13446 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
13448 ? BFD_RELOC_MIPS_TLS_DTPREL64
13449 : BFD_RELOC_MIPS_TLS_DTPREL32));
13451 demand_empty_rest_of_line ();
13454 /* Handle .dtprelword. */
13457 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
13459 s_dtprel_internal (4);
13462 /* Handle .dtpreldword. */
13465 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
13467 s_dtprel_internal (8);
13470 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
13471 code. It sets the offset to use in gp_rel relocations. */
13474 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
13476 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
13477 We also need NewABI support. */
13478 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13484 mips_gprel_offset = get_absolute_expression ();
13486 demand_empty_rest_of_line ();
13489 /* Handle the .gpword pseudo-op. This is used when generating PIC
13490 code. It generates a 32 bit GP relative reloc. */
13493 s_gpword (int ignore ATTRIBUTE_UNUSED)
13495 segment_info_type *si;
13496 struct insn_label_list *l;
13501 /* When not generating PIC code, this is treated as .word. */
13502 if (mips_pic != SVR4_PIC)
13508 si = seg_info (now_seg);
13509 l = si->label_list;
13510 label = l != NULL ? l->label : NULL;
13511 mips_emit_delays ();
13513 mips_align (2, 0, label);
13514 mips_clear_insn_labels ();
13518 if (ex.X_op != O_symbol || ex.X_add_number != 0)
13520 as_bad (_("Unsupported use of .gpword"));
13521 ignore_rest_of_line ();
13525 md_number_to_chars (p, 0, 4);
13526 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
13527 BFD_RELOC_GPREL32);
13529 demand_empty_rest_of_line ();
13533 s_gpdword (int ignore ATTRIBUTE_UNUSED)
13535 segment_info_type *si;
13536 struct insn_label_list *l;
13541 /* When not generating PIC code, this is treated as .dword. */
13542 if (mips_pic != SVR4_PIC)
13548 si = seg_info (now_seg);
13549 l = si->label_list;
13550 label = l != NULL ? l->label : NULL;
13551 mips_emit_delays ();
13553 mips_align (3, 0, label);
13554 mips_clear_insn_labels ();
13558 if (ex.X_op != O_symbol || ex.X_add_number != 0)
13560 as_bad (_("Unsupported use of .gpdword"));
13561 ignore_rest_of_line ();
13565 md_number_to_chars (p, 0, 8);
13566 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
13567 BFD_RELOC_GPREL32)->fx_tcbit = 1;
13569 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
13570 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
13571 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
13573 demand_empty_rest_of_line ();
13576 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
13577 tables in SVR4 PIC code. */
13580 s_cpadd (int ignore ATTRIBUTE_UNUSED)
13584 /* This is ignored when not generating SVR4 PIC code. */
13585 if (mips_pic != SVR4_PIC)
13591 /* Add $gp to the register named as an argument. */
13593 reg = tc_get_register (0);
13594 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
13597 demand_empty_rest_of_line ();
13600 /* Handle the .insn pseudo-op. This marks instruction labels in
13601 mips16 mode. This permits the linker to handle them specially,
13602 such as generating jalx instructions when needed. We also make
13603 them odd for the duration of the assembly, in order to generate the
13604 right sort of code. We will make them even in the adjust_symtab
13605 routine, while leaving them marked. This is convenient for the
13606 debugger and the disassembler. The linker knows to make them odd
13610 s_insn (int ignore ATTRIBUTE_UNUSED)
13612 mips16_mark_labels ();
13614 demand_empty_rest_of_line ();
13617 /* Handle a .stabn directive. We need these in order to mark a label
13618 as being a mips16 text label correctly. Sometimes the compiler
13619 will emit a label, followed by a .stabn, and then switch sections.
13620 If the label and .stabn are in mips16 mode, then the label is
13621 really a mips16 text label. */
13624 s_mips_stab (int type)
13627 mips16_mark_labels ();
13632 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
13635 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
13642 name = input_line_pointer;
13643 c = get_symbol_end ();
13644 symbolP = symbol_find_or_make (name);
13645 S_SET_WEAK (symbolP);
13646 *input_line_pointer = c;
13648 SKIP_WHITESPACE ();
13650 if (! is_end_of_line[(unsigned char) *input_line_pointer])
13652 if (S_IS_DEFINED (symbolP))
13654 as_bad (_("ignoring attempt to redefine symbol %s"),
13655 S_GET_NAME (symbolP));
13656 ignore_rest_of_line ();
13660 if (*input_line_pointer == ',')
13662 ++input_line_pointer;
13663 SKIP_WHITESPACE ();
13667 if (exp.X_op != O_symbol)
13669 as_bad (_("bad .weakext directive"));
13670 ignore_rest_of_line ();
13673 symbol_set_value_expression (symbolP, &exp);
13676 demand_empty_rest_of_line ();
13679 /* Parse a register string into a number. Called from the ECOFF code
13680 to parse .frame. The argument is non-zero if this is the frame
13681 register, so that we can record it in mips_frame_reg. */
13684 tc_get_register (int frame)
13688 SKIP_WHITESPACE ();
13689 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
13693 mips_frame_reg = reg != 0 ? reg : SP;
13694 mips_frame_reg_valid = 1;
13695 mips_cprestore_valid = 0;
13701 md_section_align (asection *seg, valueT addr)
13703 int align = bfd_get_section_alignment (stdoutput, seg);
13707 /* We don't need to align ELF sections to the full alignment.
13708 However, Irix 5 may prefer that we align them at least to a 16
13709 byte boundary. We don't bother to align the sections if we
13710 are targeted for an embedded system. */
13711 if (strncmp (TARGET_OS, "elf", 3) == 0)
13717 return ((addr + (1 << align) - 1) & (-1 << align));
13720 /* Utility routine, called from above as well. If called while the
13721 input file is still being read, it's only an approximation. (For
13722 example, a symbol may later become defined which appeared to be
13723 undefined earlier.) */
13726 nopic_need_relax (symbolS *sym, int before_relaxing)
13731 if (g_switch_value > 0)
13733 const char *symname;
13736 /* Find out whether this symbol can be referenced off the $gp
13737 register. It can be if it is smaller than the -G size or if
13738 it is in the .sdata or .sbss section. Certain symbols can
13739 not be referenced off the $gp, although it appears as though
13741 symname = S_GET_NAME (sym);
13742 if (symname != (const char *) NULL
13743 && (strcmp (symname, "eprol") == 0
13744 || strcmp (symname, "etext") == 0
13745 || strcmp (symname, "_gp") == 0
13746 || strcmp (symname, "edata") == 0
13747 || strcmp (symname, "_fbss") == 0
13748 || strcmp (symname, "_fdata") == 0
13749 || strcmp (symname, "_ftext") == 0
13750 || strcmp (symname, "end") == 0
13751 || strcmp (symname, "_gp_disp") == 0))
13753 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
13755 #ifndef NO_ECOFF_DEBUGGING
13756 || (symbol_get_obj (sym)->ecoff_extern_size != 0
13757 && (symbol_get_obj (sym)->ecoff_extern_size
13758 <= g_switch_value))
13760 /* We must defer this decision until after the whole
13761 file has been read, since there might be a .extern
13762 after the first use of this symbol. */
13763 || (before_relaxing
13764 #ifndef NO_ECOFF_DEBUGGING
13765 && symbol_get_obj (sym)->ecoff_extern_size == 0
13767 && S_GET_VALUE (sym) == 0)
13768 || (S_GET_VALUE (sym) != 0
13769 && S_GET_VALUE (sym) <= g_switch_value)))
13773 const char *segname;
13775 segname = segment_name (S_GET_SEGMENT (sym));
13776 gas_assert (strcmp (segname, ".lit8") != 0
13777 && strcmp (segname, ".lit4") != 0);
13778 change = (strcmp (segname, ".sdata") != 0
13779 && strcmp (segname, ".sbss") != 0
13780 && strncmp (segname, ".sdata.", 7) != 0
13781 && strncmp (segname, ".sbss.", 6) != 0
13782 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
13783 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
13788 /* We are not optimizing for the $gp register. */
13793 /* Return true if the given symbol should be considered local for SVR4 PIC. */
13796 pic_need_relax (symbolS *sym, asection *segtype)
13800 /* Handle the case of a symbol equated to another symbol. */
13801 while (symbol_equated_reloc_p (sym))
13805 /* It's possible to get a loop here in a badly written program. */
13806 n = symbol_get_value_expression (sym)->X_add_symbol;
13812 if (symbol_section_p (sym))
13815 symsec = S_GET_SEGMENT (sym);
13817 /* This must duplicate the test in adjust_reloc_syms. */
13818 return (symsec != &bfd_und_section
13819 && symsec != &bfd_abs_section
13820 && !bfd_is_com_section (symsec)
13821 && !s_is_linkonce (sym, segtype)
13823 /* A global or weak symbol is treated as external. */
13824 && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
13830 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
13831 extended opcode. SEC is the section the frag is in. */
13834 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
13837 const struct mips16_immed_operand *op;
13839 int mintiny, maxtiny;
13843 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
13845 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
13848 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
13849 op = mips16_immed_operands;
13850 while (op->type != type)
13853 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
13858 if (type == '<' || type == '>' || type == '[' || type == ']')
13861 maxtiny = 1 << op->nbits;
13866 maxtiny = (1 << op->nbits) - 1;
13871 mintiny = - (1 << (op->nbits - 1));
13872 maxtiny = (1 << (op->nbits - 1)) - 1;
13875 sym_frag = symbol_get_frag (fragp->fr_symbol);
13876 val = S_GET_VALUE (fragp->fr_symbol);
13877 symsec = S_GET_SEGMENT (fragp->fr_symbol);
13883 /* We won't have the section when we are called from
13884 mips_relax_frag. However, we will always have been called
13885 from md_estimate_size_before_relax first. If this is a
13886 branch to a different section, we mark it as such. If SEC is
13887 NULL, and the frag is not marked, then it must be a branch to
13888 the same section. */
13891 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
13896 /* Must have been called from md_estimate_size_before_relax. */
13899 fragp->fr_subtype =
13900 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
13902 /* FIXME: We should support this, and let the linker
13903 catch branches and loads that are out of range. */
13904 as_bad_where (fragp->fr_file, fragp->fr_line,
13905 _("unsupported PC relative reference to different section"));
13909 if (fragp != sym_frag && sym_frag->fr_address == 0)
13910 /* Assume non-extended on the first relaxation pass.
13911 The address we have calculated will be bogus if this is
13912 a forward branch to another frag, as the forward frag
13913 will have fr_address == 0. */
13917 /* In this case, we know for sure that the symbol fragment is in
13918 the same section. If the relax_marker of the symbol fragment
13919 differs from the relax_marker of this fragment, we have not
13920 yet adjusted the symbol fragment fr_address. We want to add
13921 in STRETCH in order to get a better estimate of the address.
13922 This particularly matters because of the shift bits. */
13924 && sym_frag->relax_marker != fragp->relax_marker)
13928 /* Adjust stretch for any alignment frag. Note that if have
13929 been expanding the earlier code, the symbol may be
13930 defined in what appears to be an earlier frag. FIXME:
13931 This doesn't handle the fr_subtype field, which specifies
13932 a maximum number of bytes to skip when doing an
13934 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
13936 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
13939 stretch = - ((- stretch)
13940 & ~ ((1 << (int) f->fr_offset) - 1));
13942 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
13951 addr = fragp->fr_address + fragp->fr_fix;
13953 /* The base address rules are complicated. The base address of
13954 a branch is the following instruction. The base address of a
13955 PC relative load or add is the instruction itself, but if it
13956 is in a delay slot (in which case it can not be extended) use
13957 the address of the instruction whose delay slot it is in. */
13958 if (type == 'p' || type == 'q')
13962 /* If we are currently assuming that this frag should be
13963 extended, then, the current address is two bytes
13965 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13968 /* Ignore the low bit in the target, since it will be set
13969 for a text label. */
13970 if ((val & 1) != 0)
13973 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
13975 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
13978 val -= addr & ~ ((1 << op->shift) - 1);
13980 /* Branch offsets have an implicit 0 in the lowest bit. */
13981 if (type == 'p' || type == 'q')
13984 /* If any of the shifted bits are set, we must use an extended
13985 opcode. If the address depends on the size of this
13986 instruction, this can lead to a loop, so we arrange to always
13987 use an extended opcode. We only check this when we are in
13988 the main relaxation loop, when SEC is NULL. */
13989 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
13991 fragp->fr_subtype =
13992 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
13996 /* If we are about to mark a frag as extended because the value
13997 is precisely maxtiny + 1, then there is a chance of an
13998 infinite loop as in the following code:
14003 In this case when the la is extended, foo is 0x3fc bytes
14004 away, so the la can be shrunk, but then foo is 0x400 away, so
14005 the la must be extended. To avoid this loop, we mark the
14006 frag as extended if it was small, and is about to become
14007 extended with a value of maxtiny + 1. */
14008 if (val == ((maxtiny + 1) << op->shift)
14009 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
14012 fragp->fr_subtype =
14013 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14017 else if (symsec != absolute_section && sec != NULL)
14018 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
14020 if ((val & ((1 << op->shift) - 1)) != 0
14021 || val < (mintiny << op->shift)
14022 || val > (maxtiny << op->shift))
14028 /* Compute the length of a branch sequence, and adjust the
14029 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
14030 worst-case length is computed, with UPDATE being used to indicate
14031 whether an unconditional (-1), branch-likely (+1) or regular (0)
14032 branch is to be computed. */
14034 relaxed_branch_length (fragS *fragp, asection *sec, int update)
14036 bfd_boolean toofar;
14040 && S_IS_DEFINED (fragp->fr_symbol)
14041 && sec == S_GET_SEGMENT (fragp->fr_symbol))
14046 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
14048 addr = fragp->fr_address + fragp->fr_fix + 4;
14052 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
14055 /* If the symbol is not defined or it's in a different segment,
14056 assume the user knows what's going on and emit a short
14062 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
14064 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype),
14065 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
14066 RELAX_BRANCH_LINK (fragp->fr_subtype),
14072 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
14075 if (mips_pic != NO_PIC)
14077 /* Additional space for PIC loading of target address. */
14079 if (mips_opts.isa == ISA_MIPS1)
14080 /* Additional space for $at-stabilizing nop. */
14084 /* If branch is conditional. */
14085 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
14092 /* Estimate the size of a frag before relaxing. Unless this is the
14093 mips16, we are not really relaxing here, and the final size is
14094 encoded in the subtype information. For the mips16, we have to
14095 decide whether we are using an extended opcode or not. */
14098 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
14102 if (RELAX_BRANCH_P (fragp->fr_subtype))
14105 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
14107 return fragp->fr_var;
14110 if (RELAX_MIPS16_P (fragp->fr_subtype))
14111 /* We don't want to modify the EXTENDED bit here; it might get us
14112 into infinite loops. We change it only in mips_relax_frag(). */
14113 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
14115 if (mips_pic == NO_PIC)
14116 change = nopic_need_relax (fragp->fr_symbol, 0);
14117 else if (mips_pic == SVR4_PIC)
14118 change = pic_need_relax (fragp->fr_symbol, segtype);
14119 else if (mips_pic == VXWORKS_PIC)
14120 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
14127 fragp->fr_subtype |= RELAX_USE_SECOND;
14128 return -RELAX_FIRST (fragp->fr_subtype);
14131 return -RELAX_SECOND (fragp->fr_subtype);
14134 /* This is called to see whether a reloc against a defined symbol
14135 should be converted into a reloc against a section. */
14138 mips_fix_adjustable (fixS *fixp)
14140 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
14141 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
14144 if (fixp->fx_addsy == NULL)
14147 /* If symbol SYM is in a mergeable section, relocations of the form
14148 SYM + 0 can usually be made section-relative. The mergeable data
14149 is then identified by the section offset rather than by the symbol.
14151 However, if we're generating REL LO16 relocations, the offset is split
14152 between the LO16 and parterning high part relocation. The linker will
14153 need to recalculate the complete offset in order to correctly identify
14156 The linker has traditionally not looked for the parterning high part
14157 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
14158 placed anywhere. Rather than break backwards compatibility by changing
14159 this, it seems better not to force the issue, and instead keep the
14160 original symbol. This will work with either linker behavior. */
14161 if ((lo16_reloc_p (fixp->fx_r_type)
14162 || reloc_needs_lo_p (fixp->fx_r_type))
14163 && HAVE_IN_PLACE_ADDENDS
14164 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
14167 /* There is no place to store an in-place offset for JALR relocations. */
14168 if (fixp->fx_r_type == BFD_RELOC_MIPS_JALR && HAVE_IN_PLACE_ADDENDS)
14172 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
14173 to a floating-point stub. The same is true for non-R_MIPS16_26
14174 relocations against MIPS16 functions; in this case, the stub becomes
14175 the function's canonical address.
14177 Floating-point stubs are stored in unique .mips16.call.* or
14178 .mips16.fn.* sections. If a stub T for function F is in section S,
14179 the first relocation in section S must be against F; this is how the
14180 linker determines the target function. All relocations that might
14181 resolve to T must also be against F. We therefore have the following
14182 restrictions, which are given in an intentionally-redundant way:
14184 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
14187 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
14188 if that stub might be used.
14190 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
14193 4. We cannot reduce a stub's relocations against MIPS16 symbols if
14194 that stub might be used.
14196 There is a further restriction:
14198 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols
14199 on targets with in-place addends; the relocation field cannot
14200 encode the low bit.
14202 For simplicity, we deal with (3)-(5) by not reducing _any_ relocation
14203 against a MIPS16 symbol.
14205 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
14206 relocation against some symbol R, no relocation against R may be
14207 reduced. (Note that this deals with (2) as well as (1) because
14208 relocations against global symbols will never be reduced on ELF
14209 targets.) This approach is a little simpler than trying to detect
14210 stub sections, and gives the "all or nothing" per-symbol consistency
14211 that we have for MIPS16 symbols. */
14213 && fixp->fx_subsy == NULL
14214 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
14215 || *symbol_get_tc (fixp->fx_addsy)))
14222 /* Translate internal representation of relocation info to BFD target
14226 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
14228 static arelent *retval[4];
14230 bfd_reloc_code_real_type code;
14232 memset (retval, 0, sizeof(retval));
14233 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
14234 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
14235 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
14236 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
14238 if (fixp->fx_pcrel)
14240 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2);
14242 /* At this point, fx_addnumber is "symbol offset - pcrel address".
14243 Relocations want only the symbol offset. */
14244 reloc->addend = fixp->fx_addnumber + reloc->address;
14247 /* A gruesome hack which is a result of the gruesome gas
14248 reloc handling. What's worse, for COFF (as opposed to
14249 ECOFF), we might need yet another copy of reloc->address.
14250 See bfd_install_relocation. */
14251 reloc->addend += reloc->address;
14255 reloc->addend = fixp->fx_addnumber;
14257 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
14258 entry to be used in the relocation's section offset. */
14259 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
14261 reloc->address = reloc->addend;
14265 code = fixp->fx_r_type;
14267 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
14268 if (reloc->howto == NULL)
14270 as_bad_where (fixp->fx_file, fixp->fx_line,
14271 _("Can not represent %s relocation in this object file format"),
14272 bfd_get_reloc_code_name (code));
14279 /* Relax a machine dependent frag. This returns the amount by which
14280 the current size of the frag should change. */
14283 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
14285 if (RELAX_BRANCH_P (fragp->fr_subtype))
14287 offsetT old_var = fragp->fr_var;
14289 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
14291 return fragp->fr_var - old_var;
14294 if (! RELAX_MIPS16_P (fragp->fr_subtype))
14297 if (mips16_extended_frag (fragp, NULL, stretch))
14299 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14301 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
14306 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14308 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
14315 /* Convert a machine dependent frag. */
14318 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
14320 if (RELAX_BRANCH_P (fragp->fr_subtype))
14323 unsigned long insn;
14327 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
14329 if (target_big_endian)
14330 insn = bfd_getb32 (buf);
14332 insn = bfd_getl32 (buf);
14334 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
14336 /* We generate a fixup instead of applying it right now
14337 because, if there are linker relaxations, we're going to
14338 need the relocations. */
14339 exp.X_op = O_symbol;
14340 exp.X_add_symbol = fragp->fr_symbol;
14341 exp.X_add_number = fragp->fr_offset;
14343 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14344 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2);
14345 fixp->fx_file = fragp->fr_file;
14346 fixp->fx_line = fragp->fr_line;
14348 md_number_to_chars ((char *) buf, insn, 4);
14355 as_warn_where (fragp->fr_file, fragp->fr_line,
14356 _("relaxed out-of-range branch into a jump"));
14358 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
14361 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14363 /* Reverse the branch. */
14364 switch ((insn >> 28) & 0xf)
14367 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
14368 have the condition reversed by tweaking a single
14369 bit, and their opcodes all have 0x4???????. */
14370 gas_assert ((insn & 0xf1000000) == 0x41000000);
14371 insn ^= 0x00010000;
14375 /* bltz 0x04000000 bgez 0x04010000
14376 bltzal 0x04100000 bgezal 0x04110000 */
14377 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
14378 insn ^= 0x00010000;
14382 /* beq 0x10000000 bne 0x14000000
14383 blez 0x18000000 bgtz 0x1c000000 */
14384 insn ^= 0x04000000;
14392 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
14394 /* Clear the and-link bit. */
14395 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
14397 /* bltzal 0x04100000 bgezal 0x04110000
14398 bltzall 0x04120000 bgezall 0x04130000 */
14399 insn &= ~0x00100000;
14402 /* Branch over the branch (if the branch was likely) or the
14403 full jump (not likely case). Compute the offset from the
14404 current instruction to branch to. */
14405 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14409 /* How many bytes in instructions we've already emitted? */
14410 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
14411 /* How many bytes in instructions from here to the end? */
14412 i = fragp->fr_var - i;
14414 /* Convert to instruction count. */
14416 /* Branch counts from the next instruction. */
14419 /* Branch over the jump. */
14420 md_number_to_chars ((char *) buf, insn, 4);
14424 md_number_to_chars ((char *) buf, 0, 4);
14427 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14429 /* beql $0, $0, 2f */
14431 /* Compute the PC offset from the current instruction to
14432 the end of the variable frag. */
14433 /* How many bytes in instructions we've already emitted? */
14434 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
14435 /* How many bytes in instructions from here to the end? */
14436 i = fragp->fr_var - i;
14437 /* Convert to instruction count. */
14439 /* Don't decrement i, because we want to branch over the
14443 md_number_to_chars ((char *) buf, insn, 4);
14446 md_number_to_chars ((char *) buf, 0, 4);
14451 if (mips_pic == NO_PIC)
14454 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
14455 ? 0x0c000000 : 0x08000000);
14456 exp.X_op = O_symbol;
14457 exp.X_add_symbol = fragp->fr_symbol;
14458 exp.X_add_number = fragp->fr_offset;
14460 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14461 4, &exp, FALSE, BFD_RELOC_MIPS_JMP);
14462 fixp->fx_file = fragp->fr_file;
14463 fixp->fx_line = fragp->fr_line;
14465 md_number_to_chars ((char *) buf, insn, 4);
14470 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
14471 insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000;
14472 exp.X_op = O_symbol;
14473 exp.X_add_symbol = fragp->fr_symbol;
14474 exp.X_add_number = fragp->fr_offset;
14476 if (fragp->fr_offset)
14478 exp.X_add_symbol = make_expr_symbol (&exp);
14479 exp.X_add_number = 0;
14482 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14483 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16);
14484 fixp->fx_file = fragp->fr_file;
14485 fixp->fx_line = fragp->fr_line;
14487 md_number_to_chars ((char *) buf, insn, 4);
14490 if (mips_opts.isa == ISA_MIPS1)
14493 md_number_to_chars ((char *) buf, 0, 4);
14497 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
14498 insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000;
14500 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14501 4, &exp, FALSE, BFD_RELOC_LO16);
14502 fixp->fx_file = fragp->fr_file;
14503 fixp->fx_line = fragp->fr_line;
14505 md_number_to_chars ((char *) buf, insn, 4);
14509 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
14514 md_number_to_chars ((char *) buf, insn, 4);
14519 gas_assert (buf == (bfd_byte *)fragp->fr_literal
14520 + fragp->fr_fix + fragp->fr_var);
14522 fragp->fr_fix += fragp->fr_var;
14527 if (RELAX_MIPS16_P (fragp->fr_subtype))
14530 const struct mips16_immed_operand *op;
14531 bfd_boolean small, ext;
14534 unsigned long insn;
14535 bfd_boolean use_extend;
14536 unsigned short extend;
14538 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
14539 op = mips16_immed_operands;
14540 while (op->type != type)
14543 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14554 val = resolve_symbol_value (fragp->fr_symbol);
14559 addr = fragp->fr_address + fragp->fr_fix;
14561 /* The rules for the base address of a PC relative reloc are
14562 complicated; see mips16_extended_frag. */
14563 if (type == 'p' || type == 'q')
14568 /* Ignore the low bit in the target, since it will be
14569 set for a text label. */
14570 if ((val & 1) != 0)
14573 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
14575 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
14578 addr &= ~ (addressT) ((1 << op->shift) - 1);
14581 /* Make sure the section winds up with the alignment we have
14584 record_alignment (asec, op->shift);
14588 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
14589 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
14590 as_warn_where (fragp->fr_file, fragp->fr_line,
14591 _("extended instruction in delay slot"));
14593 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
14595 if (target_big_endian)
14596 insn = bfd_getb16 (buf);
14598 insn = bfd_getl16 (buf);
14600 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
14601 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
14602 small, ext, &insn, &use_extend, &extend);
14606 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
14607 fragp->fr_fix += 2;
14611 md_number_to_chars ((char *) buf, insn, 2);
14612 fragp->fr_fix += 2;
14620 first = RELAX_FIRST (fragp->fr_subtype);
14621 second = RELAX_SECOND (fragp->fr_subtype);
14622 fixp = (fixS *) fragp->fr_opcode;
14624 /* Possibly emit a warning if we've chosen the longer option. */
14625 if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0)
14626 == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0))
14628 const char *msg = macro_warning (fragp->fr_subtype);
14630 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
14633 /* Go through all the fixups for the first sequence. Disable them
14634 (by marking them as done) if we're going to use the second
14635 sequence instead. */
14637 && fixp->fx_frag == fragp
14638 && fixp->fx_where < fragp->fr_fix - second)
14640 if (fragp->fr_subtype & RELAX_USE_SECOND)
14642 fixp = fixp->fx_next;
14645 /* Go through the fixups for the second sequence. Disable them if
14646 we're going to use the first sequence, otherwise adjust their
14647 addresses to account for the relaxation. */
14648 while (fixp && fixp->fx_frag == fragp)
14650 if (fragp->fr_subtype & RELAX_USE_SECOND)
14651 fixp->fx_where -= first;
14654 fixp = fixp->fx_next;
14657 /* Now modify the frag contents. */
14658 if (fragp->fr_subtype & RELAX_USE_SECOND)
14662 start = fragp->fr_literal + fragp->fr_fix - first - second;
14663 memmove (start, start + first, second);
14664 fragp->fr_fix -= first;
14667 fragp->fr_fix -= second;
14673 /* This function is called after the relocs have been generated.
14674 We've been storing mips16 text labels as odd. Here we convert them
14675 back to even for the convenience of the debugger. */
14678 mips_frob_file_after_relocs (void)
14681 unsigned int count, i;
14686 syms = bfd_get_outsymbols (stdoutput);
14687 count = bfd_get_symcount (stdoutput);
14688 for (i = 0; i < count; i++, syms++)
14690 if (ELF_ST_IS_MIPS16 (elf_symbol (*syms)->internal_elf_sym.st_other)
14691 && ((*syms)->value & 1) != 0)
14693 (*syms)->value &= ~1;
14694 /* If the symbol has an odd size, it was probably computed
14695 incorrectly, so adjust that as well. */
14696 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
14697 ++elf_symbol (*syms)->internal_elf_sym.st_size;
14704 /* This function is called whenever a label is defined. It is used
14705 when handling branch delays; if a branch has a label, we assume we
14706 can not move it. */
14709 mips_define_label (symbolS *sym)
14711 segment_info_type *si = seg_info (now_seg);
14712 struct insn_label_list *l;
14714 if (free_insn_labels == NULL)
14715 l = (struct insn_label_list *) xmalloc (sizeof *l);
14718 l = free_insn_labels;
14719 free_insn_labels = l->next;
14723 l->next = si->label_list;
14724 si->label_list = l;
14727 dwarf2_emit_label (sym);
14731 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14733 /* Some special processing for a MIPS ELF file. */
14736 mips_elf_final_processing (void)
14738 /* Write out the register information. */
14739 if (mips_abi != N64_ABI)
14743 s.ri_gprmask = mips_gprmask;
14744 s.ri_cprmask[0] = mips_cprmask[0];
14745 s.ri_cprmask[1] = mips_cprmask[1];
14746 s.ri_cprmask[2] = mips_cprmask[2];
14747 s.ri_cprmask[3] = mips_cprmask[3];
14748 /* The gp_value field is set by the MIPS ELF backend. */
14750 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
14751 ((Elf32_External_RegInfo *)
14752 mips_regmask_frag));
14756 Elf64_Internal_RegInfo s;
14758 s.ri_gprmask = mips_gprmask;
14760 s.ri_cprmask[0] = mips_cprmask[0];
14761 s.ri_cprmask[1] = mips_cprmask[1];
14762 s.ri_cprmask[2] = mips_cprmask[2];
14763 s.ri_cprmask[3] = mips_cprmask[3];
14764 /* The gp_value field is set by the MIPS ELF backend. */
14766 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
14767 ((Elf64_External_RegInfo *)
14768 mips_regmask_frag));
14771 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
14772 sort of BFD interface for this. */
14773 if (mips_any_noreorder)
14774 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
14775 if (mips_pic != NO_PIC)
14777 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
14778 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
14781 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
14783 /* Set MIPS ELF flags for ASEs. */
14784 /* We may need to define a new flag for DSP ASE, and set this flag when
14785 file_ase_dsp is true. */
14786 /* Same for DSP R2. */
14787 /* We may need to define a new flag for MT ASE, and set this flag when
14788 file_ase_mt is true. */
14789 if (file_ase_mips16)
14790 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
14791 #if 0 /* XXX FIXME */
14792 if (file_ase_mips3d)
14793 elf_elfheader (stdoutput)->e_flags |= ???;
14796 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
14798 /* Set the MIPS ELF ABI flags. */
14799 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
14800 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
14801 else if (mips_abi == O64_ABI)
14802 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
14803 else if (mips_abi == EABI_ABI)
14805 if (!file_mips_gp32)
14806 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
14808 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
14810 else if (mips_abi == N32_ABI)
14811 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
14813 /* Nothing to do for N64_ABI. */
14815 if (mips_32bitmode)
14816 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
14818 #if 0 /* XXX FIXME */
14819 /* 32 bit code with 64 bit FP registers. */
14820 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
14821 elf_elfheader (stdoutput)->e_flags |= ???;
14825 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
14827 typedef struct proc {
14829 symbolS *func_end_sym;
14830 unsigned long reg_mask;
14831 unsigned long reg_offset;
14832 unsigned long fpreg_mask;
14833 unsigned long fpreg_offset;
14834 unsigned long frame_offset;
14835 unsigned long frame_reg;
14836 unsigned long pc_reg;
14839 static procS cur_proc;
14840 static procS *cur_proc_ptr;
14841 static int numprocs;
14843 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal
14847 mips_nop_opcode (void)
14849 return seg_info (now_seg)->tc_segment_info_data.mips16;
14852 /* Fill in an rs_align_code fragment. This only needs to do something
14853 for MIPS16 code, where 0 is not a nop. */
14856 mips_handle_align (fragS *fragp)
14859 int bytes, size, excess;
14862 if (fragp->fr_type != rs_align_code)
14865 p = fragp->fr_literal + fragp->fr_fix;
14868 opcode = mips16_nop_insn.insn_opcode;
14873 opcode = nop_insn.insn_opcode;
14877 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
14878 excess = bytes % size;
14881 /* If we're not inserting a whole number of instructions,
14882 pad the end of the fixed part of the frag with zeros. */
14883 memset (p, 0, excess);
14885 fragp->fr_fix += excess;
14888 md_number_to_chars (p, opcode, size);
14889 fragp->fr_var = size;
14893 md_obj_begin (void)
14900 /* Check for premature end, nesting errors, etc. */
14902 as_warn (_("missing .end at end of assembly"));
14911 if (*input_line_pointer == '-')
14913 ++input_line_pointer;
14916 if (!ISDIGIT (*input_line_pointer))
14917 as_bad (_("expected simple number"));
14918 if (input_line_pointer[0] == '0')
14920 if (input_line_pointer[1] == 'x')
14922 input_line_pointer += 2;
14923 while (ISXDIGIT (*input_line_pointer))
14926 val |= hex_value (*input_line_pointer++);
14928 return negative ? -val : val;
14932 ++input_line_pointer;
14933 while (ISDIGIT (*input_line_pointer))
14936 val |= *input_line_pointer++ - '0';
14938 return negative ? -val : val;
14941 if (!ISDIGIT (*input_line_pointer))
14943 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
14944 *input_line_pointer, *input_line_pointer);
14945 as_warn (_("invalid number"));
14948 while (ISDIGIT (*input_line_pointer))
14951 val += *input_line_pointer++ - '0';
14953 return negative ? -val : val;
14956 /* The .file directive; just like the usual .file directive, but there
14957 is an initial number which is the ECOFF file index. In the non-ECOFF
14958 case .file implies DWARF-2. */
14961 s_mips_file (int x ATTRIBUTE_UNUSED)
14963 static int first_file_directive = 0;
14965 if (ECOFF_DEBUGGING)
14974 filename = dwarf2_directive_file (0);
14976 /* Versions of GCC up to 3.1 start files with a ".file"
14977 directive even for stabs output. Make sure that this
14978 ".file" is handled. Note that you need a version of GCC
14979 after 3.1 in order to support DWARF-2 on MIPS. */
14980 if (filename != NULL && ! first_file_directive)
14982 (void) new_logical_line (filename, -1);
14983 s_app_file_string (filename, 0);
14985 first_file_directive = 1;
14989 /* The .loc directive, implying DWARF-2. */
14992 s_mips_loc (int x ATTRIBUTE_UNUSED)
14994 if (!ECOFF_DEBUGGING)
14995 dwarf2_directive_loc (0);
14998 /* The .end directive. */
15001 s_mips_end (int x ATTRIBUTE_UNUSED)
15005 /* Following functions need their own .frame and .cprestore directives. */
15006 mips_frame_reg_valid = 0;
15007 mips_cprestore_valid = 0;
15009 if (!is_end_of_line[(unsigned char) *input_line_pointer])
15012 demand_empty_rest_of_line ();
15017 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
15018 as_warn (_(".end not in text section"));
15022 as_warn (_(".end directive without a preceding .ent directive."));
15023 demand_empty_rest_of_line ();
15029 gas_assert (S_GET_NAME (p));
15030 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
15031 as_warn (_(".end symbol does not match .ent symbol."));
15033 if (debug_type == DEBUG_STABS)
15034 stabs_generate_asm_endfunc (S_GET_NAME (p),
15038 as_warn (_(".end directive missing or unknown symbol"));
15041 /* Create an expression to calculate the size of the function. */
15042 if (p && cur_proc_ptr)
15044 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
15045 expressionS *exp = xmalloc (sizeof (expressionS));
15048 exp->X_op = O_subtract;
15049 exp->X_add_symbol = symbol_temp_new_now ();
15050 exp->X_op_symbol = p;
15051 exp->X_add_number = 0;
15053 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
15056 /* Generate a .pdr section. */
15057 if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr)
15059 segT saved_seg = now_seg;
15060 subsegT saved_subseg = now_subseg;
15064 #ifdef md_flush_pending_output
15065 md_flush_pending_output ();
15068 gas_assert (pdr_seg);
15069 subseg_set (pdr_seg, 0);
15071 /* Write the symbol. */
15072 exp.X_op = O_symbol;
15073 exp.X_add_symbol = p;
15074 exp.X_add_number = 0;
15075 emit_expr (&exp, 4);
15077 fragp = frag_more (7 * 4);
15079 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
15080 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
15081 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
15082 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
15083 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
15084 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
15085 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
15087 subseg_set (saved_seg, saved_subseg);
15089 #endif /* OBJ_ELF */
15091 cur_proc_ptr = NULL;
15094 /* The .aent and .ent directives. */
15097 s_mips_ent (int aent)
15101 symbolP = get_symbol ();
15102 if (*input_line_pointer == ',')
15103 ++input_line_pointer;
15104 SKIP_WHITESPACE ();
15105 if (ISDIGIT (*input_line_pointer)
15106 || *input_line_pointer == '-')
15109 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
15110 as_warn (_(".ent or .aent not in text section."));
15112 if (!aent && cur_proc_ptr)
15113 as_warn (_("missing .end"));
15117 /* This function needs its own .frame and .cprestore directives. */
15118 mips_frame_reg_valid = 0;
15119 mips_cprestore_valid = 0;
15121 cur_proc_ptr = &cur_proc;
15122 memset (cur_proc_ptr, '\0', sizeof (procS));
15124 cur_proc_ptr->func_sym = symbolP;
15128 if (debug_type == DEBUG_STABS)
15129 stabs_generate_asm_func (S_GET_NAME (symbolP),
15130 S_GET_NAME (symbolP));
15133 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
15135 demand_empty_rest_of_line ();
15138 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
15139 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
15140 s_mips_frame is used so that we can set the PDR information correctly.
15141 We can't use the ecoff routines because they make reference to the ecoff
15142 symbol table (in the mdebug section). */
15145 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
15148 if (IS_ELF && !ECOFF_DEBUGGING)
15152 if (cur_proc_ptr == (procS *) NULL)
15154 as_warn (_(".frame outside of .ent"));
15155 demand_empty_rest_of_line ();
15159 cur_proc_ptr->frame_reg = tc_get_register (1);
15161 SKIP_WHITESPACE ();
15162 if (*input_line_pointer++ != ','
15163 || get_absolute_expression_and_terminator (&val) != ',')
15165 as_warn (_("Bad .frame directive"));
15166 --input_line_pointer;
15167 demand_empty_rest_of_line ();
15171 cur_proc_ptr->frame_offset = val;
15172 cur_proc_ptr->pc_reg = tc_get_register (0);
15174 demand_empty_rest_of_line ();
15177 #endif /* OBJ_ELF */
15181 /* The .fmask and .mask directives. If the mdebug section is present
15182 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
15183 embedded targets, s_mips_mask is used so that we can set the PDR
15184 information correctly. We can't use the ecoff routines because they
15185 make reference to the ecoff symbol table (in the mdebug section). */
15188 s_mips_mask (int reg_type)
15191 if (IS_ELF && !ECOFF_DEBUGGING)
15195 if (cur_proc_ptr == (procS *) NULL)
15197 as_warn (_(".mask/.fmask outside of .ent"));
15198 demand_empty_rest_of_line ();
15202 if (get_absolute_expression_and_terminator (&mask) != ',')
15204 as_warn (_("Bad .mask/.fmask directive"));
15205 --input_line_pointer;
15206 demand_empty_rest_of_line ();
15210 off = get_absolute_expression ();
15212 if (reg_type == 'F')
15214 cur_proc_ptr->fpreg_mask = mask;
15215 cur_proc_ptr->fpreg_offset = off;
15219 cur_proc_ptr->reg_mask = mask;
15220 cur_proc_ptr->reg_offset = off;
15223 demand_empty_rest_of_line ();
15226 #endif /* OBJ_ELF */
15227 s_ignore (reg_type);
15230 /* A table describing all the processors gas knows about. Names are
15231 matched in the order listed.
15233 To ease comparison, please keep this table in the same order as
15234 gcc's mips_cpu_info_table[]. */
15235 static const struct mips_cpu_info mips_cpu_info_table[] =
15237 /* Entries for generic ISAs */
15238 { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 },
15239 { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 },
15240 { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 },
15241 { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 },
15242 { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 },
15243 { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 },
15244 { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 },
15245 { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
15246 { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
15249 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
15250 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
15251 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
15254 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
15257 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
15258 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
15259 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
15260 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
15261 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
15262 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
15263 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
15264 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
15265 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
15266 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
15267 { "orion", 0, ISA_MIPS3, CPU_R4600 },
15268 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
15269 /* ST Microelectronics Loongson 2E and 2F cores */
15270 { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E },
15271 { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F },
15274 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
15275 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
15276 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
15277 { "r14000", 0, ISA_MIPS4, CPU_R14000 },
15278 { "r16000", 0, ISA_MIPS4, CPU_R16000 },
15279 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
15280 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
15281 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
15282 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
15283 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
15284 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
15285 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
15286 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
15287 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
15288 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
15291 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
15292 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
15293 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
15294 { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
15296 /* MIPS 32 Release 2 */
15297 { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15298 { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15299 { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15300 { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
15301 { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15302 { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15303 { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15304 { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15305 { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15306 { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15307 /* Deprecated forms of the above. */
15308 { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15309 { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15310 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
15311 { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15312 { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15313 { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15314 { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15315 /* Deprecated forms of the above. */
15316 { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15317 { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15318 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
15319 { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15320 ISA_MIPS32R2, CPU_MIPS32R2 },
15321 { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15322 ISA_MIPS32R2, CPU_MIPS32R2 },
15323 { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15324 ISA_MIPS32R2, CPU_MIPS32R2 },
15325 { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15326 ISA_MIPS32R2, CPU_MIPS32R2 },
15327 /* Deprecated forms of the above. */
15328 { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15329 ISA_MIPS32R2, CPU_MIPS32R2 },
15330 { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15331 ISA_MIPS32R2, CPU_MIPS32R2 },
15332 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
15333 { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15334 ISA_MIPS32R2, CPU_MIPS32R2 },
15335 { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15336 ISA_MIPS32R2, CPU_MIPS32R2 },
15337 { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15338 ISA_MIPS32R2, CPU_MIPS32R2 },
15339 { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15340 ISA_MIPS32R2, CPU_MIPS32R2 },
15341 { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15342 ISA_MIPS32R2, CPU_MIPS32R2 },
15343 /* Deprecated forms of the above. */
15344 { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15345 ISA_MIPS32R2, CPU_MIPS32R2 },
15346 { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15347 ISA_MIPS32R2, CPU_MIPS32R2 },
15348 /* 1004K cores are multiprocessor versions of the 34K. */
15349 { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15350 ISA_MIPS32R2, CPU_MIPS32R2 },
15351 { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15352 ISA_MIPS32R2, CPU_MIPS32R2 },
15353 { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15354 ISA_MIPS32R2, CPU_MIPS32R2 },
15355 { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15356 ISA_MIPS32R2, CPU_MIPS32R2 },
15359 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
15360 { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
15361 { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
15362 { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
15364 /* Broadcom SB-1 CPU core */
15365 { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
15366 ISA_MIPS64, CPU_SB1 },
15367 /* Broadcom SB-1A CPU core */
15368 { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
15369 ISA_MIPS64, CPU_SB1 },
15371 { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A },
15373 /* MIPS 64 Release 2 */
15375 /* Cavium Networks Octeon CPU core */
15376 { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
15379 { "xlr", 0, ISA_MIPS64, CPU_XLR },
15386 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
15387 with a final "000" replaced by "k". Ignore case.
15389 Note: this function is shared between GCC and GAS. */
15392 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
15394 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
15395 given++, canonical++;
15397 return ((*given == 0 && *canonical == 0)
15398 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
15402 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
15403 CPU name. We've traditionally allowed a lot of variation here.
15405 Note: this function is shared between GCC and GAS. */
15408 mips_matching_cpu_name_p (const char *canonical, const char *given)
15410 /* First see if the name matches exactly, or with a final "000"
15411 turned into "k". */
15412 if (mips_strict_matching_cpu_name_p (canonical, given))
15415 /* If not, try comparing based on numerical designation alone.
15416 See if GIVEN is an unadorned number, or 'r' followed by a number. */
15417 if (TOLOWER (*given) == 'r')
15419 if (!ISDIGIT (*given))
15422 /* Skip over some well-known prefixes in the canonical name,
15423 hoping to find a number there too. */
15424 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
15426 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
15428 else if (TOLOWER (canonical[0]) == 'r')
15431 return mips_strict_matching_cpu_name_p (canonical, given);
15435 /* Parse an option that takes the name of a processor as its argument.
15436 OPTION is the name of the option and CPU_STRING is the argument.
15437 Return the corresponding processor enumeration if the CPU_STRING is
15438 recognized, otherwise report an error and return null.
15440 A similar function exists in GCC. */
15442 static const struct mips_cpu_info *
15443 mips_parse_cpu (const char *option, const char *cpu_string)
15445 const struct mips_cpu_info *p;
15447 /* 'from-abi' selects the most compatible architecture for the given
15448 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
15449 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15450 version. Look first at the -mgp options, if given, otherwise base
15451 the choice on MIPS_DEFAULT_64BIT.
15453 Treat NO_ABI like the EABIs. One reason to do this is that the
15454 plain 'mips' and 'mips64' configs have 'from-abi' as their default
15455 architecture. This code picks MIPS I for 'mips' and MIPS III for
15456 'mips64', just as we did in the days before 'from-abi'. */
15457 if (strcasecmp (cpu_string, "from-abi") == 0)
15459 if (ABI_NEEDS_32BIT_REGS (mips_abi))
15460 return mips_cpu_info_from_isa (ISA_MIPS1);
15462 if (ABI_NEEDS_64BIT_REGS (mips_abi))
15463 return mips_cpu_info_from_isa (ISA_MIPS3);
15465 if (file_mips_gp32 >= 0)
15466 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
15468 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
15473 /* 'default' has traditionally been a no-op. Probably not very useful. */
15474 if (strcasecmp (cpu_string, "default") == 0)
15477 for (p = mips_cpu_info_table; p->name != 0; p++)
15478 if (mips_matching_cpu_name_p (p->name, cpu_string))
15481 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
15485 /* Return the canonical processor information for ISA (a member of the
15486 ISA_MIPS* enumeration). */
15488 static const struct mips_cpu_info *
15489 mips_cpu_info_from_isa (int isa)
15493 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15494 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
15495 && isa == mips_cpu_info_table[i].isa)
15496 return (&mips_cpu_info_table[i]);
15501 static const struct mips_cpu_info *
15502 mips_cpu_info_from_arch (int arch)
15506 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15507 if (arch == mips_cpu_info_table[i].cpu)
15508 return (&mips_cpu_info_table[i]);
15514 show (FILE *stream, const char *string, int *col_p, int *first_p)
15518 fprintf (stream, "%24s", "");
15523 fprintf (stream, ", ");
15527 if (*col_p + strlen (string) > 72)
15529 fprintf (stream, "\n%24s", "");
15533 fprintf (stream, "%s", string);
15534 *col_p += strlen (string);
15540 md_show_usage (FILE *stream)
15545 fprintf (stream, _("\
15547 -EB generate big endian output\n\
15548 -EL generate little endian output\n\
15549 -g, -g2 do not remove unneeded NOPs or swap branches\n\
15550 -G NUM allow referencing objects up to NUM bytes\n\
15551 implicitly with the gp register [default 8]\n"));
15552 fprintf (stream, _("\
15553 -mips1 generate MIPS ISA I instructions\n\
15554 -mips2 generate MIPS ISA II instructions\n\
15555 -mips3 generate MIPS ISA III instructions\n\
15556 -mips4 generate MIPS ISA IV instructions\n\
15557 -mips5 generate MIPS ISA V instructions\n\
15558 -mips32 generate MIPS32 ISA instructions\n\
15559 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
15560 -mips64 generate MIPS64 ISA instructions\n\
15561 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
15562 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
15566 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15567 show (stream, mips_cpu_info_table[i].name, &column, &first);
15568 show (stream, "from-abi", &column, &first);
15569 fputc ('\n', stream);
15571 fprintf (stream, _("\
15572 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
15573 -no-mCPU don't generate code specific to CPU.\n\
15574 For -mCPU and -no-mCPU, CPU must be one of:\n"));
15578 show (stream, "3900", &column, &first);
15579 show (stream, "4010", &column, &first);
15580 show (stream, "4100", &column, &first);
15581 show (stream, "4650", &column, &first);
15582 fputc ('\n', stream);
15584 fprintf (stream, _("\
15585 -mips16 generate mips16 instructions\n\
15586 -no-mips16 do not generate mips16 instructions\n"));
15587 fprintf (stream, _("\
15588 -msmartmips generate smartmips instructions\n\
15589 -mno-smartmips do not generate smartmips instructions\n"));
15590 fprintf (stream, _("\
15591 -mdsp generate DSP instructions\n\
15592 -mno-dsp do not generate DSP instructions\n"));
15593 fprintf (stream, _("\
15594 -mdspr2 generate DSP R2 instructions\n\
15595 -mno-dspr2 do not generate DSP R2 instructions\n"));
15596 fprintf (stream, _("\
15597 -mmt generate MT instructions\n\
15598 -mno-mt do not generate MT instructions\n"));
15599 fprintf (stream, _("\
15600 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
15601 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
15602 -mfix-vr4120 work around certain VR4120 errata\n\
15603 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
15604 -mfix-24k insert a nop after ERET and DERET instructions\n\
15605 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
15606 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
15607 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
15608 -msym32 assume all symbols have 32-bit values\n\
15609 -O0 remove unneeded NOPs, do not swap branches\n\
15610 -O remove unneeded NOPs and swap branches\n\
15611 --trap, --no-break trap exception on div by 0 and mult overflow\n\
15612 --break, --no-trap break exception on div by 0 and mult overflow\n"));
15613 fprintf (stream, _("\
15614 -mhard-float allow floating-point instructions\n\
15615 -msoft-float do not allow floating-point instructions\n\
15616 -msingle-float only allow 32-bit floating-point operations\n\
15617 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
15618 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
15621 fprintf (stream, _("\
15622 -KPIC, -call_shared generate SVR4 position independent code\n\
15623 -call_nonpic generate non-PIC code that can operate with DSOs\n\
15624 -mvxworks-pic generate VxWorks position independent code\n\
15625 -non_shared do not generate code that can operate with DSOs\n\
15626 -xgot assume a 32 bit GOT\n\
15627 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
15628 -mshared, -mno-shared disable/enable .cpload optimization for\n\
15629 position dependent (non shared) code\n\
15630 -mabi=ABI create ABI conformant object file for:\n"));
15634 show (stream, "32", &column, &first);
15635 show (stream, "o64", &column, &first);
15636 show (stream, "n32", &column, &first);
15637 show (stream, "64", &column, &first);
15638 show (stream, "eabi", &column, &first);
15640 fputc ('\n', stream);
15642 fprintf (stream, _("\
15643 -32 create o32 ABI object file (default)\n\
15644 -n32 create n32 ABI object file\n\
15645 -64 create 64 ABI object file\n"));
15651 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
15653 if (HAVE_64BIT_SYMBOLS)
15654 return dwarf2_format_64bit_irix;
15656 return dwarf2_format_32bit;
15661 mips_dwarf2_addr_size (void)
15663 if (HAVE_64BIT_OBJECTS)
15669 /* Standard calling conventions leave the CFA at SP on entry. */
15671 mips_cfi_frame_initial_instructions (void)
15673 cfi_add_CFA_def_cfa_register (SP);
15677 tc_mips_regname_to_dw2regnum (char *regname)
15679 unsigned int regnum = -1;
15682 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))