1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
97 #define PIC_CALL_REG 25
105 #define ILLEGAL_REG (32)
107 #define AT mips_opts.at
109 /* Allow override of standard little-endian ECOFF format. */
111 #ifndef ECOFF_LITTLE_FORMAT
112 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
115 extern int target_big_endian;
117 /* The name of the readonly data section. */
118 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
122 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
126 /* Ways in which an instruction can be "appended" to the output. */
128 /* Just add it normally. */
131 /* Add it normally and then add a nop. */
134 /* Turn an instruction with a delay slot into a "compact" version. */
137 /* Insert the instruction before the last one. */
141 /* Information about an instruction, including its format, operands
145 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
146 const struct mips_opcode *insn_mo;
148 /* True if this is a mips16 instruction and if we want the extended
150 bfd_boolean use_extend;
152 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
153 unsigned short extend;
155 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
156 a copy of INSN_MO->match with the operands filled in. */
157 unsigned long insn_opcode;
159 /* The frag that contains the instruction. */
162 /* The offset into FRAG of the first instruction byte. */
165 /* The relocs associated with the instruction, if any. */
168 /* True if this entry cannot be moved from its current position. */
169 unsigned int fixed_p : 1;
171 /* True if this instruction occurred in a .set noreorder block. */
172 unsigned int noreorder_p : 1;
174 /* True for mips16 instructions that jump to an absolute address. */
175 unsigned int mips16_absolute_jump_p : 1;
177 /* True if this instruction is complete. */
178 unsigned int complete_p : 1;
181 /* The ABI to use. */
192 /* MIPS ABI we are using for this output file. */
193 static enum mips_abi_level mips_abi = NO_ABI;
195 /* Whether or not we have code that can call pic code. */
196 int mips_abicalls = FALSE;
198 /* Whether or not we have code which can be put into a shared
200 static bfd_boolean mips_in_shared = TRUE;
202 /* This is the set of options which may be modified by the .set
203 pseudo-op. We use a struct so that .set push and .set pop are more
206 struct mips_set_options
208 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
209 if it has not been initialized. Changed by `.set mipsN', and the
210 -mipsN command line option, and the default CPU. */
212 /* Enabled Application Specific Extensions (ASEs). These are set to -1
213 if they have not been initialized. Changed by `.set <asename>', by
214 command line options, and based on the default architecture. */
222 /* Whether we are assembling for the mips16 processor. 0 if we are
223 not, 1 if we are, and -1 if the value has not been initialized.
224 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
225 -nomips16 command line options, and the default CPU. */
227 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
228 1 if we are, and -1 if the value has not been initialized. Changed
229 by `.set micromips' and `.set nomicromips', and the -mmicromips
230 and -mno-micromips command line options, and the default CPU. */
232 /* Non-zero if we should not reorder instructions. Changed by `.set
233 reorder' and `.set noreorder'. */
235 /* Non-zero if we should not permit the register designated "assembler
236 temporary" to be used in instructions. The value is the register
237 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
238 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
240 /* Non-zero if we should warn when a macro instruction expands into
241 more than one machine instruction. Changed by `.set nomacro' and
243 int warn_about_macros;
244 /* Non-zero if we should not move instructions. Changed by `.set
245 move', `.set volatile', `.set nomove', and `.set novolatile'. */
247 /* Non-zero if we should not optimize branches by moving the target
248 of the branch into the delay slot. Actually, we don't perform
249 this optimization anyhow. Changed by `.set bopt' and `.set
252 /* Non-zero if we should not autoextend mips16 instructions.
253 Changed by `.set autoextend' and `.set noautoextend'. */
255 /* Restrict general purpose registers and floating point registers
256 to 32 bit. This is initially determined when -mgp32 or -mfp32
257 is passed but can changed if the assembler code uses .set mipsN. */
260 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
261 command line option, and the default CPU. */
263 /* True if ".set sym32" is in effect. */
265 /* True if floating-point operations are not allowed. Changed by .set
266 softfloat or .set hardfloat, by command line options -msoft-float or
267 -mhard-float. The default is false. */
268 bfd_boolean soft_float;
270 /* True if only single-precision floating-point operations are allowed.
271 Changed by .set singlefloat or .set doublefloat, command-line options
272 -msingle-float or -mdouble-float. The default is false. */
273 bfd_boolean single_float;
276 /* This is the struct we use to hold the current set of options. Note
277 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
278 -1 to indicate that they have not been initialized. */
280 /* True if -mgp32 was passed. */
281 static int file_mips_gp32 = -1;
283 /* True if -mfp32 was passed. */
284 static int file_mips_fp32 = -1;
286 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
287 static int file_mips_soft_float = 0;
289 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
290 static int file_mips_single_float = 0;
292 static struct mips_set_options mips_opts =
294 /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
295 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
296 /* ase_mcu */ -1, /* mips16 */ -1, /* micromips */ -1, /* noreorder */ 0,
297 /* at */ ATREG, /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
298 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN,
299 /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE
302 /* These variables are filled in with the masks of registers used.
303 The object format code reads them and puts them in the appropriate
305 unsigned long mips_gprmask;
306 unsigned long mips_cprmask[4];
308 /* MIPS ISA we are using for this output file. */
309 static int file_mips_isa = ISA_UNKNOWN;
311 /* True if any MIPS16 code was produced. */
312 static int file_ase_mips16;
314 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
315 || mips_opts.isa == ISA_MIPS32R2 \
316 || mips_opts.isa == ISA_MIPS64 \
317 || mips_opts.isa == ISA_MIPS64R2)
319 /* True if any microMIPS code was produced. */
320 static int file_ase_micromips;
322 /* True if we want to create R_MIPS_JALR for jalr $25. */
324 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
326 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
327 because there's no place for any addend, the only acceptable
328 expression is a bare symbol. */
329 #define MIPS_JALR_HINT_P(EXPR) \
330 (!HAVE_IN_PLACE_ADDENDS \
331 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
334 /* True if -mips3d was passed or implied by arguments passed on the
335 command line (e.g., by -march). */
336 static int file_ase_mips3d;
338 /* True if -mdmx was passed or implied by arguments passed on the
339 command line (e.g., by -march). */
340 static int file_ase_mdmx;
342 /* True if -msmartmips was passed or implied by arguments passed on the
343 command line (e.g., by -march). */
344 static int file_ase_smartmips;
346 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
347 || mips_opts.isa == ISA_MIPS32R2)
349 /* True if -mdsp was passed or implied by arguments passed on the
350 command line (e.g., by -march). */
351 static int file_ase_dsp;
353 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
354 || mips_opts.isa == ISA_MIPS64R2)
356 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
358 /* True if -mdspr2 was passed or implied by arguments passed on the
359 command line (e.g., by -march). */
360 static int file_ase_dspr2;
362 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
363 || mips_opts.isa == ISA_MIPS64R2)
365 /* True if -mmt was passed or implied by arguments passed on the
366 command line (e.g., by -march). */
367 static int file_ase_mt;
369 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
370 || mips_opts.isa == ISA_MIPS64R2)
372 #define ISA_SUPPORTS_MCU_ASE (mips_opts.isa == ISA_MIPS32R2 \
373 || mips_opts.isa == ISA_MIPS64R2)
375 /* The argument of the -march= flag. The architecture we are assembling. */
376 static int file_mips_arch = CPU_UNKNOWN;
377 static const char *mips_arch_string;
379 /* The argument of the -mtune= flag. The architecture for which we
381 static int mips_tune = CPU_UNKNOWN;
382 static const char *mips_tune_string;
384 /* True when generating 32-bit code for a 64-bit processor. */
385 static int mips_32bitmode = 0;
387 /* True if the given ABI requires 32-bit registers. */
388 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
390 /* Likewise 64-bit registers. */
391 #define ABI_NEEDS_64BIT_REGS(ABI) \
393 || (ABI) == N64_ABI \
396 /* Return true if ISA supports 64 bit wide gp registers. */
397 #define ISA_HAS_64BIT_REGS(ISA) \
398 ((ISA) == ISA_MIPS3 \
399 || (ISA) == ISA_MIPS4 \
400 || (ISA) == ISA_MIPS5 \
401 || (ISA) == ISA_MIPS64 \
402 || (ISA) == ISA_MIPS64R2)
404 /* Return true if ISA supports 64 bit wide float registers. */
405 #define ISA_HAS_64BIT_FPRS(ISA) \
406 ((ISA) == ISA_MIPS3 \
407 || (ISA) == ISA_MIPS4 \
408 || (ISA) == ISA_MIPS5 \
409 || (ISA) == ISA_MIPS32R2 \
410 || (ISA) == ISA_MIPS64 \
411 || (ISA) == ISA_MIPS64R2)
413 /* Return true if ISA supports 64-bit right rotate (dror et al.)
415 #define ISA_HAS_DROR(ISA) \
416 ((ISA) == ISA_MIPS64R2 \
417 || (mips_opts.micromips \
418 && ISA_HAS_64BIT_REGS (ISA)) \
421 /* Return true if ISA supports 32-bit right rotate (ror et al.)
423 #define ISA_HAS_ROR(ISA) \
424 ((ISA) == ISA_MIPS32R2 \
425 || (ISA) == ISA_MIPS64R2 \
426 || mips_opts.ase_smartmips \
427 || mips_opts.micromips \
430 /* Return true if ISA supports single-precision floats in odd registers. */
431 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
432 ((ISA) == ISA_MIPS32 \
433 || (ISA) == ISA_MIPS32R2 \
434 || (ISA) == ISA_MIPS64 \
435 || (ISA) == ISA_MIPS64R2)
437 /* Return true if ISA supports move to/from high part of a 64-bit
438 floating-point register. */
439 #define ISA_HAS_MXHC1(ISA) \
440 ((ISA) == ISA_MIPS32R2 \
441 || (ISA) == ISA_MIPS64R2)
443 #define HAVE_32BIT_GPRS \
444 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
446 #define HAVE_32BIT_FPRS \
447 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
449 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
450 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
452 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
454 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
456 /* True if relocations are stored in-place. */
457 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
459 /* The ABI-derived address size. */
460 #define HAVE_64BIT_ADDRESSES \
461 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
462 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
464 /* The size of symbolic constants (i.e., expressions of the form
465 "SYMBOL" or "SYMBOL + OFFSET"). */
466 #define HAVE_32BIT_SYMBOLS \
467 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
468 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
470 /* Addresses are loaded in different ways, depending on the address size
471 in use. The n32 ABI Documentation also mandates the use of additions
472 with overflow checking, but existing implementations don't follow it. */
473 #define ADDRESS_ADD_INSN \
474 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
476 #define ADDRESS_ADDI_INSN \
477 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
479 #define ADDRESS_LOAD_INSN \
480 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
482 #define ADDRESS_STORE_INSN \
483 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
485 /* Return true if the given CPU supports the MIPS16 ASE. */
486 #define CPU_HAS_MIPS16(cpu) \
487 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
488 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
490 /* Return true if the given CPU supports the microMIPS ASE. */
491 #define CPU_HAS_MICROMIPS(cpu) 0
493 /* True if CPU has a dror instruction. */
494 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
496 /* True if CPU has a ror instruction. */
497 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
499 /* True if CPU has seq/sne and seqi/snei instructions. */
500 #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON)
502 /* True if CPU does not implement the all the coprocessor insns. For these
503 CPUs only those COP insns are accepted that are explicitly marked to be
504 available on the CPU. ISA membership for COP insns is ignored. */
505 #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON)
507 /* True if mflo and mfhi can be immediately followed by instructions
508 which write to the HI and LO registers.
510 According to MIPS specifications, MIPS ISAs I, II, and III need
511 (at least) two instructions between the reads of HI/LO and
512 instructions which write them, and later ISAs do not. Contradicting
513 the MIPS specifications, some MIPS IV processor user manuals (e.g.
514 the UM for the NEC Vr5000) document needing the instructions between
515 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
516 MIPS64 and later ISAs to have the interlocks, plus any specific
517 earlier-ISA CPUs for which CPU documentation declares that the
518 instructions are really interlocked. */
519 #define hilo_interlocks \
520 (mips_opts.isa == ISA_MIPS32 \
521 || mips_opts.isa == ISA_MIPS32R2 \
522 || mips_opts.isa == ISA_MIPS64 \
523 || mips_opts.isa == ISA_MIPS64R2 \
524 || mips_opts.arch == CPU_R4010 \
525 || mips_opts.arch == CPU_R10000 \
526 || mips_opts.arch == CPU_R12000 \
527 || mips_opts.arch == CPU_R14000 \
528 || mips_opts.arch == CPU_R16000 \
529 || mips_opts.arch == CPU_RM7000 \
530 || mips_opts.arch == CPU_VR5500 \
531 || mips_opts.micromips \
534 /* Whether the processor uses hardware interlocks to protect reads
535 from the GPRs after they are loaded from memory, and thus does not
536 require nops to be inserted. This applies to instructions marked
537 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
538 level I and microMIPS mode instructions are always interlocked. */
539 #define gpr_interlocks \
540 (mips_opts.isa != ISA_MIPS1 \
541 || mips_opts.arch == CPU_R3900 \
542 || mips_opts.micromips \
545 /* Whether the processor uses hardware interlocks to avoid delays
546 required by coprocessor instructions, and thus does not require
547 nops to be inserted. This applies to instructions marked
548 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
549 between instructions marked INSN_WRITE_COND_CODE and ones marked
550 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
551 levels I, II, and III and microMIPS mode instructions are always
553 /* Itbl support may require additional care here. */
554 #define cop_interlocks \
555 ((mips_opts.isa != ISA_MIPS1 \
556 && mips_opts.isa != ISA_MIPS2 \
557 && mips_opts.isa != ISA_MIPS3) \
558 || mips_opts.arch == CPU_R4300 \
559 || mips_opts.micromips \
562 /* Whether the processor uses hardware interlocks to protect reads
563 from coprocessor registers after they are loaded from memory, and
564 thus does not require nops to be inserted. This applies to
565 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
566 requires at MIPS ISA level I and microMIPS mode instructions are
567 always interlocked. */
568 #define cop_mem_interlocks \
569 (mips_opts.isa != ISA_MIPS1 \
570 || mips_opts.micromips \
573 /* Is this a mfhi or mflo instruction? */
574 #define MF_HILO_INSN(PINFO) \
575 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
577 /* Returns true for a (non floating-point) coprocessor instruction. Reading
578 or writing the condition code is only possible on the coprocessors and
579 these insns are not marked with INSN_COP. Thus for these insns use the
580 condition-code flags. */
581 #define COP_INSN(PINFO) \
582 (PINFO != INSN_MACRO \
583 && ((PINFO) & (FP_S | FP_D)) == 0 \
584 && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
586 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
587 has been selected. This implies, in particular, that addresses of text
588 labels have their LSB set. */
589 #define HAVE_CODE_COMPRESSION \
590 ((mips_opts.mips16 | mips_opts.micromips) != 0)
592 /* MIPS PIC level. */
594 enum mips_pic_level mips_pic;
596 /* 1 if we should generate 32 bit offsets from the $gp register in
597 SVR4_PIC mode. Currently has no meaning in other modes. */
598 static int mips_big_got = 0;
600 /* 1 if trap instructions should used for overflow rather than break
602 static int mips_trap = 0;
604 /* 1 if double width floating point constants should not be constructed
605 by assembling two single width halves into two single width floating
606 point registers which just happen to alias the double width destination
607 register. On some architectures this aliasing can be disabled by a bit
608 in the status register, and the setting of this bit cannot be determined
609 automatically at assemble time. */
610 static int mips_disable_float_construction;
612 /* Non-zero if any .set noreorder directives were used. */
614 static int mips_any_noreorder;
616 /* Non-zero if nops should be inserted when the register referenced in
617 an mfhi/mflo instruction is read in the next two instructions. */
618 static int mips_7000_hilo_fix;
620 /* The size of objects in the small data section. */
621 static unsigned int g_switch_value = 8;
622 /* Whether the -G option was used. */
623 static int g_switch_seen = 0;
628 /* If we can determine in advance that GP optimization won't be
629 possible, we can skip the relaxation stuff that tries to produce
630 GP-relative references. This makes delay slot optimization work
633 This function can only provide a guess, but it seems to work for
634 gcc output. It needs to guess right for gcc, otherwise gcc
635 will put what it thinks is a GP-relative instruction in a branch
638 I don't know if a fix is needed for the SVR4_PIC mode. I've only
639 fixed it for the non-PIC mode. KR 95/04/07 */
640 static int nopic_need_relax (symbolS *, int);
642 /* handle of the OPCODE hash table */
643 static struct hash_control *op_hash = NULL;
645 /* The opcode hash table we use for the mips16. */
646 static struct hash_control *mips16_op_hash = NULL;
648 /* The opcode hash table we use for the microMIPS ASE. */
649 static struct hash_control *micromips_op_hash = NULL;
651 /* This array holds the chars that always start a comment. If the
652 pre-processor is disabled, these aren't very useful */
653 const char comment_chars[] = "#";
655 /* This array holds the chars that only start a comment at the beginning of
656 a line. If the line seems to have the form '# 123 filename'
657 .line and .file directives will appear in the pre-processed output */
658 /* Note that input_file.c hand checks for '#' at the beginning of the
659 first line of the input file. This is because the compiler outputs
660 #NO_APP at the beginning of its output. */
661 /* Also note that C style comments are always supported. */
662 const char line_comment_chars[] = "#";
664 /* This array holds machine specific line separator characters. */
665 const char line_separator_chars[] = ";";
667 /* Chars that can be used to separate mant from exp in floating point nums */
668 const char EXP_CHARS[] = "eE";
670 /* Chars that mean this number is a floating point constant */
673 const char FLT_CHARS[] = "rRsSfFdDxXpP";
675 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
676 changed in read.c . Ideally it shouldn't have to know about it at all,
677 but nothing is ideal around here.
680 static char *insn_error;
682 static int auto_align = 1;
684 /* When outputting SVR4 PIC code, the assembler needs to know the
685 offset in the stack frame from which to restore the $gp register.
686 This is set by the .cprestore pseudo-op, and saved in this
688 static offsetT mips_cprestore_offset = -1;
690 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
691 more optimizations, it can use a register value instead of a memory-saved
692 offset and even an other register than $gp as global pointer. */
693 static offsetT mips_cpreturn_offset = -1;
694 static int mips_cpreturn_register = -1;
695 static int mips_gp_register = GP;
696 static int mips_gprel_offset = 0;
698 /* Whether mips_cprestore_offset has been set in the current function
699 (or whether it has already been warned about, if not). */
700 static int mips_cprestore_valid = 0;
702 /* This is the register which holds the stack frame, as set by the
703 .frame pseudo-op. This is needed to implement .cprestore. */
704 static int mips_frame_reg = SP;
706 /* Whether mips_frame_reg has been set in the current function
707 (or whether it has already been warned about, if not). */
708 static int mips_frame_reg_valid = 0;
710 /* To output NOP instructions correctly, we need to keep information
711 about the previous two instructions. */
713 /* Whether we are optimizing. The default value of 2 means to remove
714 unneeded NOPs and swap branch instructions when possible. A value
715 of 1 means to not swap branches. A value of 0 means to always
717 static int mips_optimize = 2;
719 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
720 equivalent to seeing no -g option at all. */
721 static int mips_debug = 0;
723 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
724 #define MAX_VR4130_NOPS 4
726 /* The maximum number of NOPs needed to fill delay slots. */
727 #define MAX_DELAY_NOPS 2
729 /* The maximum number of NOPs needed for any purpose. */
732 /* A list of previous instructions, with index 0 being the most recent.
733 We need to look back MAX_NOPS instructions when filling delay slots
734 or working around processor errata. We need to look back one
735 instruction further if we're thinking about using history[0] to
736 fill a branch delay slot. */
737 static struct mips_cl_insn history[1 + MAX_NOPS];
739 /* Nop instructions used by emit_nop. */
740 static struct mips_cl_insn nop_insn;
741 static struct mips_cl_insn mips16_nop_insn;
742 static struct mips_cl_insn micromips_nop16_insn;
743 static struct mips_cl_insn micromips_nop32_insn;
745 /* The appropriate nop for the current mode. */
746 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \
747 : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn))
749 /* The size of NOP_INSN in bytes. */
750 #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4)
752 /* If this is set, it points to a frag holding nop instructions which
753 were inserted before the start of a noreorder section. If those
754 nops turn out to be unnecessary, the size of the frag can be
756 static fragS *prev_nop_frag;
758 /* The number of nop instructions we created in prev_nop_frag. */
759 static int prev_nop_frag_holds;
761 /* The number of nop instructions that we know we need in
763 static int prev_nop_frag_required;
765 /* The number of instructions we've seen since prev_nop_frag. */
766 static int prev_nop_frag_since;
768 /* For ECOFF and ELF, relocations against symbols are done in two
769 parts, with a HI relocation and a LO relocation. Each relocation
770 has only 16 bits of space to store an addend. This means that in
771 order for the linker to handle carries correctly, it must be able
772 to locate both the HI and the LO relocation. This means that the
773 relocations must appear in order in the relocation table.
775 In order to implement this, we keep track of each unmatched HI
776 relocation. We then sort them so that they immediately precede the
777 corresponding LO relocation. */
782 struct mips_hi_fixup *next;
785 /* The section this fixup is in. */
789 /* The list of unmatched HI relocs. */
791 static struct mips_hi_fixup *mips_hi_fixup_list;
793 /* The frag containing the last explicit relocation operator.
794 Null if explicit relocations have not been used. */
796 static fragS *prev_reloc_op_frag;
798 /* Map normal MIPS register numbers to mips16 register numbers. */
800 #define X ILLEGAL_REG
801 static const int mips32_to_16_reg_map[] =
803 X, X, 2, 3, 4, 5, 6, 7,
804 X, X, X, X, X, X, X, X,
805 0, 1, X, X, X, X, X, X,
806 X, X, X, X, X, X, X, X
810 /* Map mips16 register numbers to normal MIPS register numbers. */
812 static const unsigned int mips16_to_32_reg_map[] =
814 16, 17, 2, 3, 4, 5, 6, 7
817 /* Map normal MIPS register numbers to microMIPS register numbers. */
819 #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map
820 #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map
821 #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map
822 #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map
823 #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map
824 #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map
825 #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
827 #define X ILLEGAL_REG
828 /* reg type h: 4, 5, 6. */
829 static const int mips32_to_micromips_reg_h_map[] =
831 X, X, X, X, 4, 5, 6, X,
832 X, X, X, X, X, X, X, X,
833 X, X, X, X, X, X, X, X,
834 X, X, X, X, X, X, X, X
837 /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
838 static const int mips32_to_micromips_reg_m_map[] =
840 0, X, 2, 3, X, X, X, X,
841 X, X, X, X, X, X, X, X,
842 4, 1, 5, 6, 7, X, X, X,
843 X, X, X, X, X, X, X, X
846 /* reg type q: 0, 2-7. 17. */
847 static const int mips32_to_micromips_reg_q_map[] =
849 0, X, 2, 3, 4, 5, 6, 7,
850 X, X, X, X, X, X, X, X,
851 X, 1, X, X, X, X, X, X,
852 X, X, X, X, X, X, X, X
855 #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map
858 /* Map microMIPS register numbers to normal MIPS register numbers. */
860 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
861 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
862 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
863 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
864 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
865 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
867 /* The microMIPS registers with type h. */
868 static const unsigned int micromips_to_32_reg_h_map[] =
870 5, 5, 6, 4, 4, 4, 4, 4
873 /* The microMIPS registers with type i. */
874 static const unsigned int micromips_to_32_reg_i_map[] =
876 6, 7, 7, 21, 22, 5, 6, 7
879 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
881 /* The microMIPS registers with type m. */
882 static const unsigned int micromips_to_32_reg_m_map[] =
884 0, 17, 2, 3, 16, 18, 19, 20
887 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
889 /* The microMIPS registers with type q. */
890 static const unsigned int micromips_to_32_reg_q_map[] =
892 0, 17, 2, 3, 4, 5, 6, 7
895 /* microMIPS imm type B. */
896 static const int micromips_imm_b_map[] =
898 1, 4, 8, 12, 16, 20, 24, -1
901 /* microMIPS imm type C. */
902 static const int micromips_imm_c_map[] =
904 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
907 /* Classifies the kind of instructions we're interested in when
908 implementing -mfix-vr4120. */
909 enum fix_vr4120_class
917 NUM_FIX_VR4120_CLASSES
920 /* ...likewise -mfix-loongson2f-jump. */
921 static bfd_boolean mips_fix_loongson2f_jump;
923 /* ...likewise -mfix-loongson2f-nop. */
924 static bfd_boolean mips_fix_loongson2f_nop;
926 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
927 static bfd_boolean mips_fix_loongson2f;
929 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
930 there must be at least one other instruction between an instruction
931 of type X and an instruction of type Y. */
932 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
934 /* True if -mfix-vr4120 is in force. */
935 static int mips_fix_vr4120;
937 /* ...likewise -mfix-vr4130. */
938 static int mips_fix_vr4130;
940 /* ...likewise -mfix-24k. */
941 static int mips_fix_24k;
943 /* ...likewise -mfix-cn63xxp1 */
944 static bfd_boolean mips_fix_cn63xxp1;
946 /* We don't relax branches by default, since this causes us to expand
947 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
948 fail to compute the offset before expanding the macro to the most
949 efficient expansion. */
951 static int mips_relax_branch;
953 /* The expansion of many macros depends on the type of symbol that
954 they refer to. For example, when generating position-dependent code,
955 a macro that refers to a symbol may have two different expansions,
956 one which uses GP-relative addresses and one which uses absolute
957 addresses. When generating SVR4-style PIC, a macro may have
958 different expansions for local and global symbols.
960 We handle these situations by generating both sequences and putting
961 them in variant frags. In position-dependent code, the first sequence
962 will be the GP-relative one and the second sequence will be the
963 absolute one. In SVR4 PIC, the first sequence will be for global
964 symbols and the second will be for local symbols.
966 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
967 SECOND are the lengths of the two sequences in bytes. These fields
968 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
969 the subtype has the following flags:
972 Set if it has been decided that we should use the second
973 sequence instead of the first.
976 Set in the first variant frag if the macro's second implementation
977 is longer than its first. This refers to the macro as a whole,
978 not an individual relaxation.
981 Set in the first variant frag if the macro appeared in a .set nomacro
982 block and if one alternative requires a warning but the other does not.
985 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
988 RELAX_DELAY_SLOT_16BIT
989 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
992 RELAX_DELAY_SLOT_SIZE_FIRST
993 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
994 the macro is of the wrong size for the branch delay slot.
996 RELAX_DELAY_SLOT_SIZE_SECOND
997 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
998 the macro is of the wrong size for the branch delay slot.
1000 The frag's "opcode" points to the first fixup for relaxable code.
1002 Relaxable macros are generated using a sequence such as:
1004 relax_start (SYMBOL);
1005 ... generate first expansion ...
1007 ... generate second expansion ...
1010 The code and fixups for the unwanted alternative are discarded
1011 by md_convert_frag. */
1012 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
1014 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1015 #define RELAX_SECOND(X) ((X) & 0xff)
1016 #define RELAX_USE_SECOND 0x10000
1017 #define RELAX_SECOND_LONGER 0x20000
1018 #define RELAX_NOMACRO 0x40000
1019 #define RELAX_DELAY_SLOT 0x80000
1020 #define RELAX_DELAY_SLOT_16BIT 0x100000
1021 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1022 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
1024 /* Branch without likely bit. If label is out of range, we turn:
1026 beq reg1, reg2, label
1036 with the following opcode replacements:
1043 bltzal <-> bgezal (with jal label instead of j label)
1045 Even though keeping the delay slot instruction in the delay slot of
1046 the branch would be more efficient, it would be very tricky to do
1047 correctly, because we'd have to introduce a variable frag *after*
1048 the delay slot instruction, and expand that instead. Let's do it
1049 the easy way for now, even if the branch-not-taken case now costs
1050 one additional instruction. Out-of-range branches are not supposed
1051 to be common, anyway.
1053 Branch likely. If label is out of range, we turn:
1055 beql reg1, reg2, label
1056 delay slot (annulled if branch not taken)
1065 delay slot (executed only if branch taken)
1068 It would be possible to generate a shorter sequence by losing the
1069 likely bit, generating something like:
1074 delay slot (executed only if branch taken)
1086 bltzall -> bgezal (with jal label instead of j label)
1087 bgezall -> bltzal (ditto)
1090 but it's not clear that it would actually improve performance. */
1091 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1092 ((relax_substateT) \
1095 | ((toofar) ? 0x20 : 0) \
1096 | ((link) ? 0x40 : 0) \
1097 | ((likely) ? 0x80 : 0) \
1098 | ((uncond) ? 0x100 : 0)))
1099 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1100 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1101 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1102 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1103 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1104 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1106 /* For mips16 code, we use an entirely different form of relaxation.
1107 mips16 supports two versions of most instructions which take
1108 immediate values: a small one which takes some small value, and a
1109 larger one which takes a 16 bit value. Since branches also follow
1110 this pattern, relaxing these values is required.
1112 We can assemble both mips16 and normal MIPS code in a single
1113 object. Therefore, we need to support this type of relaxation at
1114 the same time that we support the relaxation described above. We
1115 use the high bit of the subtype field to distinguish these cases.
1117 The information we store for this type of relaxation is the
1118 argument code found in the opcode file for this relocation, whether
1119 the user explicitly requested a small or extended form, and whether
1120 the relocation is in a jump or jal delay slot. That tells us the
1121 size of the value, and how it should be stored. We also store
1122 whether the fragment is considered to be extended or not. We also
1123 store whether this is known to be a branch to a different section,
1124 whether we have tried to relax this frag yet, and whether we have
1125 ever extended a PC relative fragment because of a shift count. */
1126 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1129 | ((small) ? 0x100 : 0) \
1130 | ((ext) ? 0x200 : 0) \
1131 | ((dslot) ? 0x400 : 0) \
1132 | ((jal_dslot) ? 0x800 : 0))
1133 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1134 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1135 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1136 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1137 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1138 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1139 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1140 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1141 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1142 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1143 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1144 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1146 /* For microMIPS code, we use relaxation similar to one we use for
1147 MIPS16 code. Some instructions that take immediate values support
1148 two encodings: a small one which takes some small value, and a
1149 larger one which takes a 16 bit value. As some branches also follow
1150 this pattern, relaxing these values is required.
1152 We can assemble both microMIPS and normal MIPS code in a single
1153 object. Therefore, we need to support this type of relaxation at
1154 the same time that we support the relaxation described above. We
1155 use one of the high bits of the subtype field to distinguish these
1158 The information we store for this type of relaxation is the argument
1159 code found in the opcode file for this relocation, the register
1160 selected as the assembler temporary, whether the branch is
1161 unconditional, whether it is compact, whether it stores the link
1162 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1163 branches to a sequence of instructions is enabled, and whether the
1164 displacement of a branch is too large to fit as an immediate argument
1165 of a 16-bit and a 32-bit branch, respectively. */
1166 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1167 relax32, toofar16, toofar32) \
1170 | (((at) & 0x1f) << 8) \
1171 | ((uncond) ? 0x2000 : 0) \
1172 | ((compact) ? 0x4000 : 0) \
1173 | ((link) ? 0x8000 : 0) \
1174 | ((relax32) ? 0x10000 : 0) \
1175 | ((toofar16) ? 0x20000 : 0) \
1176 | ((toofar32) ? 0x40000 : 0))
1177 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1178 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1179 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1180 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1181 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1182 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1183 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1185 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1186 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1187 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1188 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1189 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1190 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1192 /* Is the given value a sign-extended 32-bit value? */
1193 #define IS_SEXT_32BIT_NUM(x) \
1194 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1195 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1197 /* Is the given value a sign-extended 16-bit value? */
1198 #define IS_SEXT_16BIT_NUM(x) \
1199 (((x) &~ (offsetT) 0x7fff) == 0 \
1200 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1202 /* Is the given value a sign-extended 12-bit value? */
1203 #define IS_SEXT_12BIT_NUM(x) \
1204 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1206 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1207 #define IS_ZEXT_32BIT_NUM(x) \
1208 (((x) &~ (offsetT) 0xffffffff) == 0 \
1209 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1211 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1212 VALUE << SHIFT. VALUE is evaluated exactly once. */
1213 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1214 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1215 | (((VALUE) & (MASK)) << (SHIFT)))
1217 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1219 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1220 (((STRUCT) >> (SHIFT)) & (MASK))
1222 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1223 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1225 include/opcode/mips.h specifies operand fields using the macros
1226 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1227 with "MIPS16OP" instead of "OP". */
1228 #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \
1231 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1232 OP_MASK_##FIELD, OP_SH_##FIELD); \
1234 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1235 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \
1237 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1238 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1239 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1241 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1242 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1244 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1245 : EXTRACT_BITS ((INSN).insn_opcode, \
1246 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1247 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1248 EXTRACT_BITS ((INSN).insn_opcode, \
1249 MIPS16OP_MASK_##FIELD, \
1250 MIPS16OP_SH_##FIELD)
1252 /* Whether or not we are emitting a branch-likely macro. */
1253 static bfd_boolean emit_branch_likely_macro = FALSE;
1255 /* Global variables used when generating relaxable macros. See the
1256 comment above RELAX_ENCODE for more details about how relaxation
1259 /* 0 if we're not emitting a relaxable macro.
1260 1 if we're emitting the first of the two relaxation alternatives.
1261 2 if we're emitting the second alternative. */
1264 /* The first relaxable fixup in the current frag. (In other words,
1265 the first fixup that refers to relaxable code.) */
1268 /* sizes[0] says how many bytes of the first alternative are stored in
1269 the current frag. Likewise sizes[1] for the second alternative. */
1270 unsigned int sizes[2];
1272 /* The symbol on which the choice of sequence depends. */
1276 /* Global variables used to decide whether a macro needs a warning. */
1278 /* True if the macro is in a branch delay slot. */
1279 bfd_boolean delay_slot_p;
1281 /* Set to the length in bytes required if the macro is in a delay slot
1282 that requires a specific length of instruction, otherwise zero. */
1283 unsigned int delay_slot_length;
1285 /* For relaxable macros, sizes[0] is the length of the first alternative
1286 in bytes and sizes[1] is the length of the second alternative.
1287 For non-relaxable macros, both elements give the length of the
1289 unsigned int sizes[2];
1291 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1292 instruction of the first alternative in bytes and first_insn_sizes[1]
1293 is the length of the first instruction of the second alternative.
1294 For non-relaxable macros, both elements give the length of the first
1295 instruction in bytes.
1297 Set to zero if we haven't yet seen the first instruction. */
1298 unsigned int first_insn_sizes[2];
1300 /* For relaxable macros, insns[0] is the number of instructions for the
1301 first alternative and insns[1] is the number of instructions for the
1304 For non-relaxable macros, both elements give the number of
1305 instructions for the macro. */
1306 unsigned int insns[2];
1308 /* The first variant frag for this macro. */
1310 } mips_macro_warning;
1312 /* Prototypes for static functions. */
1314 #define internalError() \
1315 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1317 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1319 static void append_insn
1320 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1321 bfd_boolean expansionp);
1322 static void mips_no_prev_insn (void);
1323 static void macro_build (expressionS *, const char *, const char *, ...);
1324 static void mips16_macro_build
1325 (expressionS *, const char *, const char *, va_list *);
1326 static void load_register (int, expressionS *, int);
1327 static void macro_start (void);
1328 static void macro_end (void);
1329 static void macro (struct mips_cl_insn * ip);
1330 static void mips16_macro (struct mips_cl_insn * ip);
1331 static void mips_ip (char *str, struct mips_cl_insn * ip);
1332 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1333 static void mips16_immed
1334 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
1335 unsigned long *, bfd_boolean *, unsigned short *);
1336 static size_t my_getSmallExpression
1337 (expressionS *, bfd_reloc_code_real_type *, char *);
1338 static void my_getExpression (expressionS *, char *);
1339 static void s_align (int);
1340 static void s_change_sec (int);
1341 static void s_change_section (int);
1342 static void s_cons (int);
1343 static void s_float_cons (int);
1344 static void s_mips_globl (int);
1345 static void s_option (int);
1346 static void s_mipsset (int);
1347 static void s_abicalls (int);
1348 static void s_cpload (int);
1349 static void s_cpsetup (int);
1350 static void s_cplocal (int);
1351 static void s_cprestore (int);
1352 static void s_cpreturn (int);
1353 static void s_dtprelword (int);
1354 static void s_dtpreldword (int);
1355 static void s_gpvalue (int);
1356 static void s_gpword (int);
1357 static void s_gpdword (int);
1358 static void s_cpadd (int);
1359 static void s_insn (int);
1360 static void md_obj_begin (void);
1361 static void md_obj_end (void);
1362 static void s_mips_ent (int);
1363 static void s_mips_end (int);
1364 static void s_mips_frame (int);
1365 static void s_mips_mask (int reg_type);
1366 static void s_mips_stab (int);
1367 static void s_mips_weakext (int);
1368 static void s_mips_file (int);
1369 static void s_mips_loc (int);
1370 static bfd_boolean pic_need_relax (symbolS *, asection *);
1371 static int relaxed_branch_length (fragS *, asection *, int);
1372 static int validate_mips_insn (const struct mips_opcode *);
1373 static int validate_micromips_insn (const struct mips_opcode *);
1374 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1375 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1377 /* Table and functions used to map between CPU/ISA names, and
1378 ISA levels, and CPU numbers. */
1380 struct mips_cpu_info
1382 const char *name; /* CPU or ISA name. */
1383 int flags; /* ASEs available, or ISA flag. */
1384 int isa; /* ISA level. */
1385 int cpu; /* CPU number (default CPU if ISA). */
1388 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1389 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1390 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1391 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1392 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1393 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1394 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1395 #define MIPS_CPU_ASE_MCU 0x0080 /* CPU implements MCU ASE */
1397 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1398 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1399 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1403 The following pseudo-ops from the Kane and Heinrich MIPS book
1404 should be defined here, but are currently unsupported: .alias,
1405 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1407 The following pseudo-ops from the Kane and Heinrich MIPS book are
1408 specific to the type of debugging information being generated, and
1409 should be defined by the object format: .aent, .begin, .bend,
1410 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1413 The following pseudo-ops from the Kane and Heinrich MIPS book are
1414 not MIPS CPU specific, but are also not specific to the object file
1415 format. This file is probably the best place to define them, but
1416 they are not currently supported: .asm0, .endr, .lab, .struct. */
1418 static const pseudo_typeS mips_pseudo_table[] =
1420 /* MIPS specific pseudo-ops. */
1421 {"option", s_option, 0},
1422 {"set", s_mipsset, 0},
1423 {"rdata", s_change_sec, 'r'},
1424 {"sdata", s_change_sec, 's'},
1425 {"livereg", s_ignore, 0},
1426 {"abicalls", s_abicalls, 0},
1427 {"cpload", s_cpload, 0},
1428 {"cpsetup", s_cpsetup, 0},
1429 {"cplocal", s_cplocal, 0},
1430 {"cprestore", s_cprestore, 0},
1431 {"cpreturn", s_cpreturn, 0},
1432 {"dtprelword", s_dtprelword, 0},
1433 {"dtpreldword", s_dtpreldword, 0},
1434 {"gpvalue", s_gpvalue, 0},
1435 {"gpword", s_gpword, 0},
1436 {"gpdword", s_gpdword, 0},
1437 {"cpadd", s_cpadd, 0},
1438 {"insn", s_insn, 0},
1440 /* Relatively generic pseudo-ops that happen to be used on MIPS
1442 {"asciiz", stringer, 8 + 1},
1443 {"bss", s_change_sec, 'b'},
1445 {"half", s_cons, 1},
1446 {"dword", s_cons, 3},
1447 {"weakext", s_mips_weakext, 0},
1448 {"origin", s_org, 0},
1449 {"repeat", s_rept, 0},
1451 /* For MIPS this is non-standard, but we define it for consistency. */
1452 {"sbss", s_change_sec, 'B'},
1454 /* These pseudo-ops are defined in read.c, but must be overridden
1455 here for one reason or another. */
1456 {"align", s_align, 0},
1457 {"byte", s_cons, 0},
1458 {"data", s_change_sec, 'd'},
1459 {"double", s_float_cons, 'd'},
1460 {"float", s_float_cons, 'f'},
1461 {"globl", s_mips_globl, 0},
1462 {"global", s_mips_globl, 0},
1463 {"hword", s_cons, 1},
1465 {"long", s_cons, 2},
1466 {"octa", s_cons, 4},
1467 {"quad", s_cons, 3},
1468 {"section", s_change_section, 0},
1469 {"short", s_cons, 1},
1470 {"single", s_float_cons, 'f'},
1471 {"stabn", s_mips_stab, 'n'},
1472 {"text", s_change_sec, 't'},
1473 {"word", s_cons, 2},
1475 { "extern", ecoff_directive_extern, 0},
1480 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1482 /* These pseudo-ops should be defined by the object file format.
1483 However, a.out doesn't support them, so we have versions here. */
1484 {"aent", s_mips_ent, 1},
1485 {"bgnb", s_ignore, 0},
1486 {"end", s_mips_end, 0},
1487 {"endb", s_ignore, 0},
1488 {"ent", s_mips_ent, 0},
1489 {"file", s_mips_file, 0},
1490 {"fmask", s_mips_mask, 'F'},
1491 {"frame", s_mips_frame, 0},
1492 {"loc", s_mips_loc, 0},
1493 {"mask", s_mips_mask, 'R'},
1494 {"verstamp", s_ignore, 0},
1498 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1499 purpose of the `.dc.a' internal pseudo-op. */
1502 mips_address_bytes (void)
1504 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1507 extern void pop_insert (const pseudo_typeS *);
1510 mips_pop_insert (void)
1512 pop_insert (mips_pseudo_table);
1513 if (! ECOFF_DEBUGGING)
1514 pop_insert (mips_nonecoff_pseudo_table);
1517 /* Symbols labelling the current insn. */
1519 struct insn_label_list
1521 struct insn_label_list *next;
1525 static struct insn_label_list *free_insn_labels;
1526 #define label_list tc_segment_info_data.labels
1528 static void mips_clear_insn_labels (void);
1529 static void mips_mark_labels (void);
1530 static void mips_compressed_mark_labels (void);
1533 mips_clear_insn_labels (void)
1535 register struct insn_label_list **pl;
1536 segment_info_type *si;
1540 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1543 si = seg_info (now_seg);
1544 *pl = si->label_list;
1545 si->label_list = NULL;
1549 /* Mark instruction labels in MIPS16/microMIPS mode. */
1552 mips_mark_labels (void)
1554 if (HAVE_CODE_COMPRESSION)
1555 mips_compressed_mark_labels ();
1558 static char *expr_end;
1560 /* Expressions which appear in instructions. These are set by
1563 static expressionS imm_expr;
1564 static expressionS imm2_expr;
1565 static expressionS offset_expr;
1567 /* Relocs associated with imm_expr and offset_expr. */
1569 static bfd_reloc_code_real_type imm_reloc[3]
1570 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1571 static bfd_reloc_code_real_type offset_reloc[3]
1572 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1574 /* This is set to the resulting size of the instruction to be produced
1575 by mips16_ip if an explicit extension is used or by mips_ip if an
1576 explicit size is supplied. */
1578 static unsigned int forced_insn_length;
1581 /* The pdr segment for per procedure frame/regmask info. Not used for
1584 static segT pdr_seg;
1587 /* The default target format to use. */
1589 #if defined (TE_FreeBSD)
1590 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1591 #elif defined (TE_TMIPS)
1592 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1594 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1598 mips_target_format (void)
1600 switch (OUTPUT_FLAVOR)
1602 case bfd_target_ecoff_flavour:
1603 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1604 case bfd_target_coff_flavour:
1606 case bfd_target_elf_flavour:
1608 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1609 return (target_big_endian
1610 ? "elf32-bigmips-vxworks"
1611 : "elf32-littlemips-vxworks");
1613 return (target_big_endian
1614 ? (HAVE_64BIT_OBJECTS
1615 ? ELF_TARGET ("elf64-", "big")
1617 ? ELF_TARGET ("elf32-n", "big")
1618 : ELF_TARGET ("elf32-", "big")))
1619 : (HAVE_64BIT_OBJECTS
1620 ? ELF_TARGET ("elf64-", "little")
1622 ? ELF_TARGET ("elf32-n", "little")
1623 : ELF_TARGET ("elf32-", "little"))));
1630 /* Return the length of a microMIPS instruction in bytes. If bits of
1631 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1632 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1633 major opcode) will require further modifications to the opcode
1636 static inline unsigned int
1637 micromips_insn_length (const struct mips_opcode *mo)
1639 return (mo->mask >> 16) == 0 ? 2 : 4;
1642 /* Return the length of instruction INSN. */
1644 static inline unsigned int
1645 insn_length (const struct mips_cl_insn *insn)
1647 if (mips_opts.micromips)
1648 return micromips_insn_length (insn->insn_mo);
1649 else if (mips_opts.mips16)
1650 return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2;
1655 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1658 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1663 insn->use_extend = FALSE;
1665 insn->insn_opcode = mo->match;
1668 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1669 insn->fixp[i] = NULL;
1670 insn->fixed_p = (mips_opts.noreorder > 0);
1671 insn->noreorder_p = (mips_opts.noreorder > 0);
1672 insn->mips16_absolute_jump_p = 0;
1673 insn->complete_p = 0;
1676 /* Record the current MIPS16/microMIPS mode in now_seg. */
1679 mips_record_compressed_mode (void)
1681 segment_info_type *si;
1683 si = seg_info (now_seg);
1684 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
1685 si->tc_segment_info_data.mips16 = mips_opts.mips16;
1686 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
1687 si->tc_segment_info_data.micromips = mips_opts.micromips;
1690 /* Install INSN at the location specified by its "frag" and "where" fields. */
1693 install_insn (const struct mips_cl_insn *insn)
1695 char *f = insn->frag->fr_literal + insn->where;
1696 if (!HAVE_CODE_COMPRESSION)
1697 md_number_to_chars (f, insn->insn_opcode, 4);
1698 else if (mips_opts.micromips)
1700 unsigned int length = insn_length (insn);
1702 md_number_to_chars (f, insn->insn_opcode, 2);
1703 else if (length == 4)
1705 md_number_to_chars (f, insn->insn_opcode >> 16, 2);
1707 md_number_to_chars (f, insn->insn_opcode & 0xffff, 2);
1710 as_bad (_("48-bit microMIPS instructions are not supported"));
1712 else if (insn->mips16_absolute_jump_p)
1714 md_number_to_chars (f, insn->insn_opcode >> 16, 2);
1715 md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2);
1719 if (insn->use_extend)
1721 md_number_to_chars (f, 0xf000 | insn->extend, 2);
1724 md_number_to_chars (f, insn->insn_opcode, 2);
1726 mips_record_compressed_mode ();
1729 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1730 and install the opcode in the new location. */
1733 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
1738 insn->where = where;
1739 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1740 if (insn->fixp[i] != NULL)
1742 insn->fixp[i]->fx_frag = frag;
1743 insn->fixp[i]->fx_where = where;
1745 install_insn (insn);
1748 /* Add INSN to the end of the output. */
1751 add_fixed_insn (struct mips_cl_insn *insn)
1753 char *f = frag_more (insn_length (insn));
1754 move_insn (insn, frag_now, f - frag_now->fr_literal);
1757 /* Start a variant frag and move INSN to the start of the variant part,
1758 marking it as fixed. The other arguments are as for frag_var. */
1761 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
1762 relax_substateT subtype, symbolS *symbol, offsetT offset)
1764 frag_grow (max_chars);
1765 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
1767 frag_var (rs_machine_dependent, max_chars, var,
1768 subtype, symbol, offset, NULL);
1771 /* Insert N copies of INSN into the history buffer, starting at
1772 position FIRST. Neither FIRST nor N need to be clipped. */
1775 insert_into_history (unsigned int first, unsigned int n,
1776 const struct mips_cl_insn *insn)
1778 if (mips_relax.sequence != 2)
1782 for (i = ARRAY_SIZE (history); i-- > first;)
1784 history[i] = history[i - n];
1790 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1791 the idea is to make it obvious at a glance that each errata is
1795 init_vr4120_conflicts (void)
1797 #define CONFLICT(FIRST, SECOND) \
1798 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1800 /* Errata 21 - [D]DIV[U] after [D]MACC */
1801 CONFLICT (MACC, DIV);
1802 CONFLICT (DMACC, DIV);
1804 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1805 CONFLICT (DMULT, DMULT);
1806 CONFLICT (DMULT, DMACC);
1807 CONFLICT (DMACC, DMULT);
1808 CONFLICT (DMACC, DMACC);
1810 /* Errata 24 - MT{LO,HI} after [D]MACC */
1811 CONFLICT (MACC, MTHILO);
1812 CONFLICT (DMACC, MTHILO);
1814 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1815 instruction is executed immediately after a MACC or DMACC
1816 instruction, the result of [either instruction] is incorrect." */
1817 CONFLICT (MACC, MULT);
1818 CONFLICT (MACC, DMULT);
1819 CONFLICT (DMACC, MULT);
1820 CONFLICT (DMACC, DMULT);
1822 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1823 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1824 DDIV or DDIVU instruction, the result of the MACC or
1825 DMACC instruction is incorrect.". */
1826 CONFLICT (DMULT, MACC);
1827 CONFLICT (DMULT, DMACC);
1828 CONFLICT (DIV, MACC);
1829 CONFLICT (DIV, DMACC);
1839 #define RTYPE_MASK 0x1ff00
1840 #define RTYPE_NUM 0x00100
1841 #define RTYPE_FPU 0x00200
1842 #define RTYPE_FCC 0x00400
1843 #define RTYPE_VEC 0x00800
1844 #define RTYPE_GP 0x01000
1845 #define RTYPE_CP0 0x02000
1846 #define RTYPE_PC 0x04000
1847 #define RTYPE_ACC 0x08000
1848 #define RTYPE_CCC 0x10000
1849 #define RNUM_MASK 0x000ff
1850 #define RWARN 0x80000
1852 #define GENERIC_REGISTER_NUMBERS \
1853 {"$0", RTYPE_NUM | 0}, \
1854 {"$1", RTYPE_NUM | 1}, \
1855 {"$2", RTYPE_NUM | 2}, \
1856 {"$3", RTYPE_NUM | 3}, \
1857 {"$4", RTYPE_NUM | 4}, \
1858 {"$5", RTYPE_NUM | 5}, \
1859 {"$6", RTYPE_NUM | 6}, \
1860 {"$7", RTYPE_NUM | 7}, \
1861 {"$8", RTYPE_NUM | 8}, \
1862 {"$9", RTYPE_NUM | 9}, \
1863 {"$10", RTYPE_NUM | 10}, \
1864 {"$11", RTYPE_NUM | 11}, \
1865 {"$12", RTYPE_NUM | 12}, \
1866 {"$13", RTYPE_NUM | 13}, \
1867 {"$14", RTYPE_NUM | 14}, \
1868 {"$15", RTYPE_NUM | 15}, \
1869 {"$16", RTYPE_NUM | 16}, \
1870 {"$17", RTYPE_NUM | 17}, \
1871 {"$18", RTYPE_NUM | 18}, \
1872 {"$19", RTYPE_NUM | 19}, \
1873 {"$20", RTYPE_NUM | 20}, \
1874 {"$21", RTYPE_NUM | 21}, \
1875 {"$22", RTYPE_NUM | 22}, \
1876 {"$23", RTYPE_NUM | 23}, \
1877 {"$24", RTYPE_NUM | 24}, \
1878 {"$25", RTYPE_NUM | 25}, \
1879 {"$26", RTYPE_NUM | 26}, \
1880 {"$27", RTYPE_NUM | 27}, \
1881 {"$28", RTYPE_NUM | 28}, \
1882 {"$29", RTYPE_NUM | 29}, \
1883 {"$30", RTYPE_NUM | 30}, \
1884 {"$31", RTYPE_NUM | 31}
1886 #define FPU_REGISTER_NAMES \
1887 {"$f0", RTYPE_FPU | 0}, \
1888 {"$f1", RTYPE_FPU | 1}, \
1889 {"$f2", RTYPE_FPU | 2}, \
1890 {"$f3", RTYPE_FPU | 3}, \
1891 {"$f4", RTYPE_FPU | 4}, \
1892 {"$f5", RTYPE_FPU | 5}, \
1893 {"$f6", RTYPE_FPU | 6}, \
1894 {"$f7", RTYPE_FPU | 7}, \
1895 {"$f8", RTYPE_FPU | 8}, \
1896 {"$f9", RTYPE_FPU | 9}, \
1897 {"$f10", RTYPE_FPU | 10}, \
1898 {"$f11", RTYPE_FPU | 11}, \
1899 {"$f12", RTYPE_FPU | 12}, \
1900 {"$f13", RTYPE_FPU | 13}, \
1901 {"$f14", RTYPE_FPU | 14}, \
1902 {"$f15", RTYPE_FPU | 15}, \
1903 {"$f16", RTYPE_FPU | 16}, \
1904 {"$f17", RTYPE_FPU | 17}, \
1905 {"$f18", RTYPE_FPU | 18}, \
1906 {"$f19", RTYPE_FPU | 19}, \
1907 {"$f20", RTYPE_FPU | 20}, \
1908 {"$f21", RTYPE_FPU | 21}, \
1909 {"$f22", RTYPE_FPU | 22}, \
1910 {"$f23", RTYPE_FPU | 23}, \
1911 {"$f24", RTYPE_FPU | 24}, \
1912 {"$f25", RTYPE_FPU | 25}, \
1913 {"$f26", RTYPE_FPU | 26}, \
1914 {"$f27", RTYPE_FPU | 27}, \
1915 {"$f28", RTYPE_FPU | 28}, \
1916 {"$f29", RTYPE_FPU | 29}, \
1917 {"$f30", RTYPE_FPU | 30}, \
1918 {"$f31", RTYPE_FPU | 31}
1920 #define FPU_CONDITION_CODE_NAMES \
1921 {"$fcc0", RTYPE_FCC | 0}, \
1922 {"$fcc1", RTYPE_FCC | 1}, \
1923 {"$fcc2", RTYPE_FCC | 2}, \
1924 {"$fcc3", RTYPE_FCC | 3}, \
1925 {"$fcc4", RTYPE_FCC | 4}, \
1926 {"$fcc5", RTYPE_FCC | 5}, \
1927 {"$fcc6", RTYPE_FCC | 6}, \
1928 {"$fcc7", RTYPE_FCC | 7}
1930 #define COPROC_CONDITION_CODE_NAMES \
1931 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1932 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1933 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1934 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1935 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1936 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1937 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1938 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1940 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1941 {"$a4", RTYPE_GP | 8}, \
1942 {"$a5", RTYPE_GP | 9}, \
1943 {"$a6", RTYPE_GP | 10}, \
1944 {"$a7", RTYPE_GP | 11}, \
1945 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1946 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1947 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1948 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1949 {"$t0", RTYPE_GP | 12}, \
1950 {"$t1", RTYPE_GP | 13}, \
1951 {"$t2", RTYPE_GP | 14}, \
1952 {"$t3", RTYPE_GP | 15}
1954 #define O32_SYMBOLIC_REGISTER_NAMES \
1955 {"$t0", RTYPE_GP | 8}, \
1956 {"$t1", RTYPE_GP | 9}, \
1957 {"$t2", RTYPE_GP | 10}, \
1958 {"$t3", RTYPE_GP | 11}, \
1959 {"$t4", RTYPE_GP | 12}, \
1960 {"$t5", RTYPE_GP | 13}, \
1961 {"$t6", RTYPE_GP | 14}, \
1962 {"$t7", RTYPE_GP | 15}, \
1963 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1964 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1965 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1966 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1968 /* Remaining symbolic register names */
1969 #define SYMBOLIC_REGISTER_NAMES \
1970 {"$zero", RTYPE_GP | 0}, \
1971 {"$at", RTYPE_GP | 1}, \
1972 {"$AT", RTYPE_GP | 1}, \
1973 {"$v0", RTYPE_GP | 2}, \
1974 {"$v1", RTYPE_GP | 3}, \
1975 {"$a0", RTYPE_GP | 4}, \
1976 {"$a1", RTYPE_GP | 5}, \
1977 {"$a2", RTYPE_GP | 6}, \
1978 {"$a3", RTYPE_GP | 7}, \
1979 {"$s0", RTYPE_GP | 16}, \
1980 {"$s1", RTYPE_GP | 17}, \
1981 {"$s2", RTYPE_GP | 18}, \
1982 {"$s3", RTYPE_GP | 19}, \
1983 {"$s4", RTYPE_GP | 20}, \
1984 {"$s5", RTYPE_GP | 21}, \
1985 {"$s6", RTYPE_GP | 22}, \
1986 {"$s7", RTYPE_GP | 23}, \
1987 {"$t8", RTYPE_GP | 24}, \
1988 {"$t9", RTYPE_GP | 25}, \
1989 {"$k0", RTYPE_GP | 26}, \
1990 {"$kt0", RTYPE_GP | 26}, \
1991 {"$k1", RTYPE_GP | 27}, \
1992 {"$kt1", RTYPE_GP | 27}, \
1993 {"$gp", RTYPE_GP | 28}, \
1994 {"$sp", RTYPE_GP | 29}, \
1995 {"$s8", RTYPE_GP | 30}, \
1996 {"$fp", RTYPE_GP | 30}, \
1997 {"$ra", RTYPE_GP | 31}
1999 #define MIPS16_SPECIAL_REGISTER_NAMES \
2000 {"$pc", RTYPE_PC | 0}
2002 #define MDMX_VECTOR_REGISTER_NAMES \
2003 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2004 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2005 {"$v2", RTYPE_VEC | 2}, \
2006 {"$v3", RTYPE_VEC | 3}, \
2007 {"$v4", RTYPE_VEC | 4}, \
2008 {"$v5", RTYPE_VEC | 5}, \
2009 {"$v6", RTYPE_VEC | 6}, \
2010 {"$v7", RTYPE_VEC | 7}, \
2011 {"$v8", RTYPE_VEC | 8}, \
2012 {"$v9", RTYPE_VEC | 9}, \
2013 {"$v10", RTYPE_VEC | 10}, \
2014 {"$v11", RTYPE_VEC | 11}, \
2015 {"$v12", RTYPE_VEC | 12}, \
2016 {"$v13", RTYPE_VEC | 13}, \
2017 {"$v14", RTYPE_VEC | 14}, \
2018 {"$v15", RTYPE_VEC | 15}, \
2019 {"$v16", RTYPE_VEC | 16}, \
2020 {"$v17", RTYPE_VEC | 17}, \
2021 {"$v18", RTYPE_VEC | 18}, \
2022 {"$v19", RTYPE_VEC | 19}, \
2023 {"$v20", RTYPE_VEC | 20}, \
2024 {"$v21", RTYPE_VEC | 21}, \
2025 {"$v22", RTYPE_VEC | 22}, \
2026 {"$v23", RTYPE_VEC | 23}, \
2027 {"$v24", RTYPE_VEC | 24}, \
2028 {"$v25", RTYPE_VEC | 25}, \
2029 {"$v26", RTYPE_VEC | 26}, \
2030 {"$v27", RTYPE_VEC | 27}, \
2031 {"$v28", RTYPE_VEC | 28}, \
2032 {"$v29", RTYPE_VEC | 29}, \
2033 {"$v30", RTYPE_VEC | 30}, \
2034 {"$v31", RTYPE_VEC | 31}
2036 #define MIPS_DSP_ACCUMULATOR_NAMES \
2037 {"$ac0", RTYPE_ACC | 0}, \
2038 {"$ac1", RTYPE_ACC | 1}, \
2039 {"$ac2", RTYPE_ACC | 2}, \
2040 {"$ac3", RTYPE_ACC | 3}
2042 static const struct regname reg_names[] = {
2043 GENERIC_REGISTER_NUMBERS,
2045 FPU_CONDITION_CODE_NAMES,
2046 COPROC_CONDITION_CODE_NAMES,
2048 /* The $txx registers depends on the abi,
2049 these will be added later into the symbol table from
2050 one of the tables below once mips_abi is set after
2051 parsing of arguments from the command line. */
2052 SYMBOLIC_REGISTER_NAMES,
2054 MIPS16_SPECIAL_REGISTER_NAMES,
2055 MDMX_VECTOR_REGISTER_NAMES,
2056 MIPS_DSP_ACCUMULATOR_NAMES,
2060 static const struct regname reg_names_o32[] = {
2061 O32_SYMBOLIC_REGISTER_NAMES,
2065 static const struct regname reg_names_n32n64[] = {
2066 N32N64_SYMBOLIC_REGISTER_NAMES,
2070 /* Check if S points at a valid register specifier according to TYPES.
2071 If so, then return 1, advance S to consume the specifier and store
2072 the register's number in REGNOP, otherwise return 0. */
2075 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2082 /* Find end of name. */
2084 if (is_name_beginner (*e))
2086 while (is_part_of_name (*e))
2089 /* Terminate name. */
2093 /* Look for a register symbol. */
2094 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
2096 int r = S_GET_VALUE (symbolP);
2098 reg = r & RNUM_MASK;
2099 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
2100 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2101 reg = (r & RNUM_MASK) - 2;
2103 /* Else see if this is a register defined in an itbl entry. */
2104 else if ((types & RTYPE_GP) && itbl_have_entries)
2111 if (itbl_get_reg_val (n, &r))
2112 reg = r & RNUM_MASK;
2115 /* Advance to next token if a register was recognised. */
2118 else if (types & RWARN)
2119 as_warn (_("Unrecognized register name `%s'"), *s);
2127 /* Check if S points at a valid register list according to TYPES.
2128 If so, then return 1, advance S to consume the list and store
2129 the registers present on the list as a bitmask of ones in REGLISTP,
2130 otherwise return 0. A valid list comprises a comma-separated
2131 enumeration of valid single registers and/or dash-separated
2132 contiguous register ranges as determined by their numbers.
2134 As a special exception if one of s0-s7 registers is specified as
2135 the range's lower delimiter and s8 (fp) is its upper one, then no
2136 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2137 are selected; they have to be listed separately if needed. */
2140 reglist_lookup (char **s, unsigned int types, unsigned int *reglistp)
2142 unsigned int reglist = 0;
2143 unsigned int lastregno;
2144 bfd_boolean ok = TRUE;
2145 unsigned int regmask;
2146 char *s_endlist = *s;
2150 while (reg_lookup (s, types, ®no))
2156 ok = reg_lookup (s, types, &lastregno);
2157 if (ok && lastregno < regno)
2163 if (lastregno == FP && regno >= S0 && regno <= S7)
2168 regmask = 1 << lastregno;
2169 regmask = (regmask << 1) - 1;
2170 regmask ^= (1 << regno) - 1;
2184 *reglistp = reglist;
2185 return ok && reglist != 0;
2188 /* Return TRUE if opcode MO is valid on the currently selected ISA and
2189 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2192 is_opcode_valid (const struct mips_opcode *mo)
2194 int isa = mips_opts.isa;
2197 if (mips_opts.ase_mdmx)
2199 if (mips_opts.ase_dsp)
2201 if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
2203 if (mips_opts.ase_dspr2)
2205 if (mips_opts.ase_mt)
2207 if (mips_opts.ase_mips3d)
2209 if (mips_opts.ase_smartmips)
2210 isa |= INSN_SMARTMIPS;
2211 if (mips_opts.ase_mcu)
2214 /* Don't accept instructions based on the ISA if the CPU does not implement
2215 all the coprocessor insns. */
2216 if (NO_ISA_COP (mips_opts.arch)
2217 && COP_INSN (mo->pinfo))
2220 if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch))
2223 /* Check whether the instruction or macro requires single-precision or
2224 double-precision floating-point support. Note that this information is
2225 stored differently in the opcode table for insns and macros. */
2226 if (mo->pinfo == INSN_MACRO)
2228 fp_s = mo->pinfo2 & INSN2_M_FP_S;
2229 fp_d = mo->pinfo2 & INSN2_M_FP_D;
2233 fp_s = mo->pinfo & FP_S;
2234 fp_d = mo->pinfo & FP_D;
2237 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
2240 if (fp_s && mips_opts.soft_float)
2246 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2247 selected ISA and architecture. */
2250 is_opcode_valid_16 (const struct mips_opcode *mo)
2252 return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE;
2255 /* Return TRUE if the size of the microMIPS opcode MO matches one
2256 explicitly requested. Always TRUE in the standard MIPS mode. */
2259 is_size_valid (const struct mips_opcode *mo)
2261 if (!mips_opts.micromips)
2264 if (!forced_insn_length)
2266 if (mo->pinfo == INSN_MACRO)
2268 return forced_insn_length == micromips_insn_length (mo);
2271 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2272 of the preceding instruction. Always TRUE in the standard MIPS mode. */
2275 is_delay_slot_valid (const struct mips_opcode *mo)
2277 if (!mips_opts.micromips)
2280 if (mo->pinfo == INSN_MACRO)
2282 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
2283 && micromips_insn_length (mo) != 4)
2285 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
2286 && micromips_insn_length (mo) != 2)
2292 /* This function is called once, at assembler startup time. It should set up
2293 all the tables, etc. that the MD part of the assembler will need. */
2298 const char *retval = NULL;
2302 if (mips_pic != NO_PIC)
2304 if (g_switch_seen && g_switch_value != 0)
2305 as_bad (_("-G may not be used in position-independent code"));
2309 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
2310 as_warn (_("Could not set architecture and machine"));
2312 op_hash = hash_new ();
2314 for (i = 0; i < NUMOPCODES;)
2316 const char *name = mips_opcodes[i].name;
2318 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
2321 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
2322 mips_opcodes[i].name, retval);
2323 /* Probably a memory allocation problem? Give up now. */
2324 as_fatal (_("Broken assembler. No assembly attempted."));
2328 if (mips_opcodes[i].pinfo != INSN_MACRO)
2330 if (!validate_mips_insn (&mips_opcodes[i]))
2332 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2334 create_insn (&nop_insn, mips_opcodes + i);
2335 if (mips_fix_loongson2f_nop)
2336 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
2337 nop_insn.fixed_p = 1;
2342 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
2345 mips16_op_hash = hash_new ();
2348 while (i < bfd_mips16_num_opcodes)
2350 const char *name = mips16_opcodes[i].name;
2352 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
2354 as_fatal (_("internal: can't hash `%s': %s"),
2355 mips16_opcodes[i].name, retval);
2358 if (mips16_opcodes[i].pinfo != INSN_MACRO
2359 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
2360 != mips16_opcodes[i].match))
2362 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
2363 mips16_opcodes[i].name, mips16_opcodes[i].args);
2366 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2368 create_insn (&mips16_nop_insn, mips16_opcodes + i);
2369 mips16_nop_insn.fixed_p = 1;
2373 while (i < bfd_mips16_num_opcodes
2374 && strcmp (mips16_opcodes[i].name, name) == 0);
2377 micromips_op_hash = hash_new ();
2380 while (i < bfd_micromips_num_opcodes)
2382 const char *name = micromips_opcodes[i].name;
2384 retval = hash_insert (micromips_op_hash, name,
2385 (void *) µmips_opcodes[i]);
2387 as_fatal (_("internal: can't hash `%s': %s"),
2388 micromips_opcodes[i].name, retval);
2390 if (micromips_opcodes[i].pinfo != INSN_MACRO)
2392 struct mips_cl_insn *micromips_nop_insn;
2394 if (!validate_micromips_insn (µmips_opcodes[i]))
2397 if (micromips_insn_length (micromips_opcodes + i) == 2)
2398 micromips_nop_insn = µmips_nop16_insn;
2399 else if (micromips_insn_length (micromips_opcodes + i) == 4)
2400 micromips_nop_insn = µmips_nop32_insn;
2404 if (micromips_nop_insn->insn_mo == NULL
2405 && strcmp (name, "nop") == 0)
2407 create_insn (micromips_nop_insn, micromips_opcodes + i);
2408 micromips_nop_insn->fixed_p = 1;
2411 while (++i < bfd_micromips_num_opcodes
2412 && strcmp (micromips_opcodes[i].name, name) == 0);
2416 as_fatal (_("Broken assembler. No assembly attempted."));
2418 /* We add all the general register names to the symbol table. This
2419 helps us detect invalid uses of them. */
2420 for (i = 0; reg_names[i].name; i++)
2421 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
2422 reg_names[i].num, /* & RNUM_MASK, */
2423 &zero_address_frag));
2425 for (i = 0; reg_names_n32n64[i].name; i++)
2426 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
2427 reg_names_n32n64[i].num, /* & RNUM_MASK, */
2428 &zero_address_frag));
2430 for (i = 0; reg_names_o32[i].name; i++)
2431 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
2432 reg_names_o32[i].num, /* & RNUM_MASK, */
2433 &zero_address_frag));
2435 mips_no_prev_insn ();
2438 mips_cprmask[0] = 0;
2439 mips_cprmask[1] = 0;
2440 mips_cprmask[2] = 0;
2441 mips_cprmask[3] = 0;
2443 /* set the default alignment for the text section (2**2) */
2444 record_alignment (text_section, 2);
2446 bfd_set_gp_size (stdoutput, g_switch_value);
2451 /* On a native system other than VxWorks, sections must be aligned
2452 to 16 byte boundaries. When configured for an embedded ELF
2453 target, we don't bother. */
2454 if (strncmp (TARGET_OS, "elf", 3) != 0
2455 && strncmp (TARGET_OS, "vxworks", 7) != 0)
2457 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
2458 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
2459 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
2462 /* Create a .reginfo section for register masks and a .mdebug
2463 section for debugging information. */
2471 subseg = now_subseg;
2473 /* The ABI says this section should be loaded so that the
2474 running program can access it. However, we don't load it
2475 if we are configured for an embedded target */
2476 flags = SEC_READONLY | SEC_DATA;
2477 if (strncmp (TARGET_OS, "elf", 3) != 0)
2478 flags |= SEC_ALLOC | SEC_LOAD;
2480 if (mips_abi != N64_ABI)
2482 sec = subseg_new (".reginfo", (subsegT) 0);
2484 bfd_set_section_flags (stdoutput, sec, flags);
2485 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
2487 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
2491 /* The 64-bit ABI uses a .MIPS.options section rather than
2492 .reginfo section. */
2493 sec = subseg_new (".MIPS.options", (subsegT) 0);
2494 bfd_set_section_flags (stdoutput, sec, flags);
2495 bfd_set_section_alignment (stdoutput, sec, 3);
2497 /* Set up the option header. */
2499 Elf_Internal_Options opthdr;
2502 opthdr.kind = ODK_REGINFO;
2503 opthdr.size = (sizeof (Elf_External_Options)
2504 + sizeof (Elf64_External_RegInfo));
2507 f = frag_more (sizeof (Elf_External_Options));
2508 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2509 (Elf_External_Options *) f);
2511 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2515 if (ECOFF_DEBUGGING)
2517 sec = subseg_new (".mdebug", (subsegT) 0);
2518 (void) bfd_set_section_flags (stdoutput, sec,
2519 SEC_HAS_CONTENTS | SEC_READONLY);
2520 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2522 else if (mips_flag_pdr)
2524 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2525 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2526 SEC_READONLY | SEC_RELOC
2528 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2531 subseg_set (seg, subseg);
2534 #endif /* OBJ_ELF */
2536 if (! ECOFF_DEBUGGING)
2539 if (mips_fix_vr4120)
2540 init_vr4120_conflicts ();
2546 mips_emit_delays ();
2547 if (! ECOFF_DEBUGGING)
2552 md_assemble (char *str)
2554 struct mips_cl_insn insn;
2555 bfd_reloc_code_real_type unused_reloc[3]
2556 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2558 imm_expr.X_op = O_absent;
2559 imm2_expr.X_op = O_absent;
2560 offset_expr.X_op = O_absent;
2561 imm_reloc[0] = BFD_RELOC_UNUSED;
2562 imm_reloc[1] = BFD_RELOC_UNUSED;
2563 imm_reloc[2] = BFD_RELOC_UNUSED;
2564 offset_reloc[0] = BFD_RELOC_UNUSED;
2565 offset_reloc[1] = BFD_RELOC_UNUSED;
2566 offset_reloc[2] = BFD_RELOC_UNUSED;
2568 if (mips_opts.mips16)
2569 mips16_ip (str, &insn);
2572 mips_ip (str, &insn);
2573 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2574 str, insn.insn_opcode));
2579 as_bad ("%s `%s'", insn_error, str);
2583 if (insn.insn_mo->pinfo == INSN_MACRO)
2586 if (mips_opts.mips16)
2587 mips16_macro (&insn);
2594 if (imm_expr.X_op != O_absent)
2595 append_insn (&insn, &imm_expr, imm_reloc, FALSE);
2596 else if (offset_expr.X_op != O_absent)
2597 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
2599 append_insn (&insn, NULL, unused_reloc, FALSE);
2603 /* Convenience functions for abstracting away the differences between
2604 MIPS16 and non-MIPS16 relocations. */
2606 static inline bfd_boolean
2607 mips16_reloc_p (bfd_reloc_code_real_type reloc)
2611 case BFD_RELOC_MIPS16_JMP:
2612 case BFD_RELOC_MIPS16_GPREL:
2613 case BFD_RELOC_MIPS16_GOT16:
2614 case BFD_RELOC_MIPS16_CALL16:
2615 case BFD_RELOC_MIPS16_HI16_S:
2616 case BFD_RELOC_MIPS16_HI16:
2617 case BFD_RELOC_MIPS16_LO16:
2625 static inline bfd_boolean
2626 micromips_reloc_p (bfd_reloc_code_real_type reloc)
2630 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
2631 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
2632 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
2633 case BFD_RELOC_MICROMIPS_GPREL16:
2634 case BFD_RELOC_MICROMIPS_JMP:
2635 case BFD_RELOC_MICROMIPS_HI16:
2636 case BFD_RELOC_MICROMIPS_HI16_S:
2637 case BFD_RELOC_MICROMIPS_LO16:
2638 case BFD_RELOC_MICROMIPS_LITERAL:
2639 case BFD_RELOC_MICROMIPS_GOT16:
2640 case BFD_RELOC_MICROMIPS_CALL16:
2641 case BFD_RELOC_MICROMIPS_GOT_HI16:
2642 case BFD_RELOC_MICROMIPS_GOT_LO16:
2643 case BFD_RELOC_MICROMIPS_CALL_HI16:
2644 case BFD_RELOC_MICROMIPS_CALL_LO16:
2645 case BFD_RELOC_MICROMIPS_SUB:
2646 case BFD_RELOC_MICROMIPS_GOT_PAGE:
2647 case BFD_RELOC_MICROMIPS_GOT_OFST:
2648 case BFD_RELOC_MICROMIPS_GOT_DISP:
2649 case BFD_RELOC_MICROMIPS_HIGHEST:
2650 case BFD_RELOC_MICROMIPS_HIGHER:
2651 case BFD_RELOC_MICROMIPS_SCN_DISP:
2652 case BFD_RELOC_MICROMIPS_JALR:
2660 static inline bfd_boolean
2661 jmp_reloc_p (bfd_reloc_code_real_type reloc)
2663 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
2666 static inline bfd_boolean
2667 got16_reloc_p (bfd_reloc_code_real_type reloc)
2669 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
2670 || reloc == BFD_RELOC_MICROMIPS_GOT16);
2673 static inline bfd_boolean
2674 hi16_reloc_p (bfd_reloc_code_real_type reloc)
2676 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
2677 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
2680 static inline bfd_boolean
2681 lo16_reloc_p (bfd_reloc_code_real_type reloc)
2683 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
2684 || reloc == BFD_RELOC_MICROMIPS_LO16);
2687 static inline bfd_boolean
2688 jalr_reloc_p (bfd_reloc_code_real_type reloc)
2690 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
2693 /* Return true if the given relocation might need a matching %lo().
2694 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2695 need a matching %lo() when applied to local symbols. */
2697 static inline bfd_boolean
2698 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
2700 return (HAVE_IN_PLACE_ADDENDS
2701 && (hi16_reloc_p (reloc)
2702 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2703 all GOT16 relocations evaluate to "G". */
2704 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
2707 /* Return the type of %lo() reloc needed by RELOC, given that
2708 reloc_needs_lo_p. */
2710 static inline bfd_reloc_code_real_type
2711 matching_lo_reloc (bfd_reloc_code_real_type reloc)
2713 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
2714 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
2718 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2721 static inline bfd_boolean
2722 fixup_has_matching_lo_p (fixS *fixp)
2724 return (fixp->fx_next != NULL
2725 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
2726 && fixp->fx_addsy == fixp->fx_next->fx_addsy
2727 && fixp->fx_offset == fixp->fx_next->fx_offset);
2730 /* This function returns true if modifying a register requires a
2734 reg_needs_delay (unsigned int reg)
2736 unsigned long prev_pinfo;
2738 prev_pinfo = history[0].insn_mo->pinfo;
2739 if (! mips_opts.noreorder
2740 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2741 && ! gpr_interlocks)
2742 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
2743 && ! cop_interlocks)))
2745 /* A load from a coprocessor or from memory. All load delays
2746 delay the use of general register rt for one instruction. */
2747 /* Itbl support may require additional care here. */
2748 know (prev_pinfo & INSN_WRITE_GPR_T);
2749 if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0]))
2756 /* Move all labels in insn_labels to the current insertion point. */
2759 mips_move_labels (void)
2761 segment_info_type *si = seg_info (now_seg);
2762 struct insn_label_list *l;
2765 for (l = si->label_list; l != NULL; l = l->next)
2767 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
2768 symbol_set_frag (l->label, frag_now);
2769 val = (valueT) frag_now_fix ();
2770 /* MIPS16/microMIPS text labels are stored as odd. */
2771 if (HAVE_CODE_COMPRESSION)
2773 S_SET_VALUE (l->label, val);
2778 s_is_linkonce (symbolS *sym, segT from_seg)
2780 bfd_boolean linkonce = FALSE;
2781 segT symseg = S_GET_SEGMENT (sym);
2783 if (symseg != from_seg && !S_IS_LOCAL (sym))
2785 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
2788 /* The GNU toolchain uses an extension for ELF: a section
2789 beginning with the magic string .gnu.linkonce is a
2790 linkonce section. */
2791 if (strncmp (segment_name (symseg), ".gnu.linkonce",
2792 sizeof ".gnu.linkonce" - 1) == 0)
2799 /* Mark instruction labels in MIPS16/microMIPS mode. This permits the
2800 linker to handle them specially, such as generating jalx instructions
2801 when needed. We also make them odd for the duration of the assembly,
2802 in order to generate the right sort of code. We will make them even
2803 in the adjust_symtab routine, while leaving them marked. This is
2804 convenient for the debugger and the disassembler. The linker knows
2805 to make them odd again. */
2808 mips_compressed_mark_labels (void)
2810 segment_info_type *si = seg_info (now_seg);
2811 struct insn_label_list *l;
2813 gas_assert (HAVE_CODE_COMPRESSION);
2815 for (l = si->label_list; l != NULL; l = l->next)
2817 symbolS *label = l->label;
2819 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2822 if (mips_opts.mips16)
2823 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
2825 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
2828 if ((S_GET_VALUE (label) & 1) == 0
2829 /* Don't adjust the address if the label is global or weak, or
2830 in a link-once section, since we'll be emitting symbol reloc
2831 references to it which will be patched up by the linker, and
2832 the final value of the symbol may or may not be MIPS16/microMIPS. */
2833 && ! S_IS_WEAK (label)
2834 && ! S_IS_EXTERNAL (label)
2835 && ! s_is_linkonce (label, now_seg))
2836 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
2840 /* End the current frag. Make it a variant frag and record the
2844 relax_close_frag (void)
2846 mips_macro_warning.first_frag = frag_now;
2847 frag_var (rs_machine_dependent, 0, 0,
2848 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
2849 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
2851 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
2852 mips_relax.first_fixup = 0;
2855 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2856 See the comment above RELAX_ENCODE for more details. */
2859 relax_start (symbolS *symbol)
2861 gas_assert (mips_relax.sequence == 0);
2862 mips_relax.sequence = 1;
2863 mips_relax.symbol = symbol;
2866 /* Start generating the second version of a relaxable sequence.
2867 See the comment above RELAX_ENCODE for more details. */
2872 gas_assert (mips_relax.sequence == 1);
2873 mips_relax.sequence = 2;
2876 /* End the current relaxable sequence. */
2881 gas_assert (mips_relax.sequence == 2);
2882 relax_close_frag ();
2883 mips_relax.sequence = 0;
2886 /* Return true if IP is a delayed branch or jump. */
2888 static inline bfd_boolean
2889 delayed_branch_p (const struct mips_cl_insn *ip)
2891 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
2892 | INSN_COND_BRANCH_DELAY
2893 | INSN_COND_BRANCH_LIKELY)) != 0;
2896 /* Return true if IP is a compact branch or jump. */
2898 static inline bfd_boolean
2899 compact_branch_p (const struct mips_cl_insn *ip)
2901 if (mips_opts.mips16)
2902 return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
2903 | MIPS16_INSN_COND_BRANCH)) != 0;
2905 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
2906 | INSN2_COND_BRANCH)) != 0;
2909 /* Return true if IP is an unconditional branch or jump. */
2911 static inline bfd_boolean
2912 uncond_branch_p (const struct mips_cl_insn *ip)
2914 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
2915 || (mips_opts.mips16
2916 ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0
2917 : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0));
2920 /* Return true if IP is a branch-likely instruction. */
2922 static inline bfd_boolean
2923 branch_likely_p (const struct mips_cl_insn *ip)
2925 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
2928 /* Return the type of nop that should be used to fill the delay slot
2929 of delayed branch IP. */
2931 static struct mips_cl_insn *
2932 get_delay_slot_nop (const struct mips_cl_insn *ip)
2934 if (mips_opts.micromips
2935 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
2936 return µmips_nop32_insn;
2940 /* Return the mask of core registers that IP reads or writes. */
2943 gpr_mod_mask (const struct mips_cl_insn *ip)
2945 unsigned long pinfo2;
2949 pinfo2 = ip->insn_mo->pinfo2;
2950 if (mips_opts.micromips)
2952 if (pinfo2 & INSN2_MOD_GPR_MD)
2953 mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)];
2954 if (pinfo2 & INSN2_MOD_GPR_MF)
2955 mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)];
2956 if (pinfo2 & INSN2_MOD_SP)
2962 /* Return the mask of core registers that IP reads. */
2965 gpr_read_mask (const struct mips_cl_insn *ip)
2967 unsigned long pinfo, pinfo2;
2970 mask = gpr_mod_mask (ip);
2971 pinfo = ip->insn_mo->pinfo;
2972 pinfo2 = ip->insn_mo->pinfo2;
2973 if (mips_opts.mips16)
2975 if (pinfo & MIPS16_INSN_READ_X)
2976 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
2977 if (pinfo & MIPS16_INSN_READ_Y)
2978 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
2979 if (pinfo & MIPS16_INSN_READ_T)
2981 if (pinfo & MIPS16_INSN_READ_SP)
2983 if (pinfo & MIPS16_INSN_READ_31)
2985 if (pinfo & MIPS16_INSN_READ_Z)
2986 mask |= 1 << (mips16_to_32_reg_map
2987 [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]);
2988 if (pinfo & MIPS16_INSN_READ_GPR_X)
2989 mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
2993 if (pinfo2 & INSN2_READ_GPR_D)
2994 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
2995 if (pinfo & INSN_READ_GPR_T)
2996 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
2997 if (pinfo & INSN_READ_GPR_S)
2998 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
2999 if (pinfo2 & INSN2_READ_GP)
3001 if (pinfo2 & INSN2_READ_GPR_31)
3003 if (pinfo2 & INSN2_READ_GPR_Z)
3004 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3006 if (mips_opts.micromips)
3008 if (pinfo2 & INSN2_READ_GPR_MC)
3009 mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)];
3010 if (pinfo2 & INSN2_READ_GPR_ME)
3011 mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)];
3012 if (pinfo2 & INSN2_READ_GPR_MG)
3013 mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)];
3014 if (pinfo2 & INSN2_READ_GPR_MJ)
3015 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3016 if (pinfo2 & INSN2_READ_GPR_MMN)
3018 mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)];
3019 mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)];
3021 if (pinfo2 & INSN2_READ_GPR_MP)
3022 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3023 if (pinfo2 & INSN2_READ_GPR_MQ)
3024 mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)];
3026 /* Don't include register 0. */
3030 /* Return the mask of core registers that IP writes. */
3033 gpr_write_mask (const struct mips_cl_insn *ip)
3035 unsigned long pinfo, pinfo2;
3038 mask = gpr_mod_mask (ip);
3039 pinfo = ip->insn_mo->pinfo;
3040 pinfo2 = ip->insn_mo->pinfo2;
3041 if (mips_opts.mips16)
3043 if (pinfo & MIPS16_INSN_WRITE_X)
3044 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3045 if (pinfo & MIPS16_INSN_WRITE_Y)
3046 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3047 if (pinfo & MIPS16_INSN_WRITE_Z)
3048 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)];
3049 if (pinfo & MIPS16_INSN_WRITE_T)
3051 if (pinfo & MIPS16_INSN_WRITE_SP)
3053 if (pinfo & MIPS16_INSN_WRITE_31)
3055 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
3056 mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
3060 if (pinfo & INSN_WRITE_GPR_D)
3061 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3062 if (pinfo & INSN_WRITE_GPR_T)
3063 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3064 if (pinfo & INSN_WRITE_GPR_S)
3065 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3066 if (pinfo & INSN_WRITE_GPR_31)
3068 if (pinfo2 & INSN2_WRITE_GPR_Z)
3069 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3071 if (mips_opts.micromips)
3073 if (pinfo2 & INSN2_WRITE_GPR_MB)
3074 mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)];
3075 if (pinfo2 & INSN2_WRITE_GPR_MHI)
3077 mask |= 1 << micromips_to_32_reg_h_map[EXTRACT_OPERAND (1, MH, *ip)];
3078 mask |= 1 << micromips_to_32_reg_i_map[EXTRACT_OPERAND (1, MI, *ip)];
3080 if (pinfo2 & INSN2_WRITE_GPR_MJ)
3081 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3082 if (pinfo2 & INSN2_WRITE_GPR_MP)
3083 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3085 /* Don't include register 0. */
3089 /* Return the mask of floating-point registers that IP reads. */
3092 fpr_read_mask (const struct mips_cl_insn *ip)
3094 unsigned long pinfo, pinfo2;
3098 pinfo = ip->insn_mo->pinfo;
3099 pinfo2 = ip->insn_mo->pinfo2;
3100 if (!mips_opts.mips16)
3102 if (pinfo2 & INSN2_READ_FPR_D)
3103 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3104 if (pinfo & INSN_READ_FPR_S)
3105 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3106 if (pinfo & INSN_READ_FPR_T)
3107 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3108 if (pinfo & INSN_READ_FPR_R)
3109 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip);
3110 if (pinfo2 & INSN2_READ_FPR_Z)
3111 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3113 /* Conservatively treat all operands to an FP_D instruction are doubles.
3114 (This is overly pessimistic for things like cvt.d.s.) */
3115 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3120 /* Return the mask of floating-point registers that IP writes. */
3123 fpr_write_mask (const struct mips_cl_insn *ip)
3125 unsigned long pinfo, pinfo2;
3129 pinfo = ip->insn_mo->pinfo;
3130 pinfo2 = ip->insn_mo->pinfo2;
3131 if (!mips_opts.mips16)
3133 if (pinfo & INSN_WRITE_FPR_D)
3134 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3135 if (pinfo & INSN_WRITE_FPR_S)
3136 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3137 if (pinfo & INSN_WRITE_FPR_T)
3138 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3139 if (pinfo2 & INSN2_WRITE_FPR_Z)
3140 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3142 /* Conservatively treat all operands to an FP_D instruction are doubles.
3143 (This is overly pessimistic for things like cvt.s.d.) */
3144 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3149 /* Classify an instruction according to the FIX_VR4120_* enumeration.
3150 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
3151 by VR4120 errata. */
3154 classify_vr4120_insn (const char *name)
3156 if (strncmp (name, "macc", 4) == 0)
3157 return FIX_VR4120_MACC;
3158 if (strncmp (name, "dmacc", 5) == 0)
3159 return FIX_VR4120_DMACC;
3160 if (strncmp (name, "mult", 4) == 0)
3161 return FIX_VR4120_MULT;
3162 if (strncmp (name, "dmult", 5) == 0)
3163 return FIX_VR4120_DMULT;
3164 if (strstr (name, "div"))
3165 return FIX_VR4120_DIV;
3166 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
3167 return FIX_VR4120_MTHILO;
3168 return NUM_FIX_VR4120_CLASSES;
3171 #define INSN_ERET 0x42000018
3172 #define INSN_DERET 0x4200001f
3174 /* Return the number of instructions that must separate INSN1 and INSN2,
3175 where INSN1 is the earlier instruction. Return the worst-case value
3176 for any INSN2 if INSN2 is null. */
3179 insns_between (const struct mips_cl_insn *insn1,
3180 const struct mips_cl_insn *insn2)
3182 unsigned long pinfo1, pinfo2;
3185 /* This function needs to know which pinfo flags are set for INSN2
3186 and which registers INSN2 uses. The former is stored in PINFO2 and
3187 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
3188 will have every flag set and INSN2_USES_GPR will always return true. */
3189 pinfo1 = insn1->insn_mo->pinfo;
3190 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
3192 #define INSN2_USES_GPR(REG) \
3193 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
3195 /* For most targets, write-after-read dependencies on the HI and LO
3196 registers must be separated by at least two instructions. */
3197 if (!hilo_interlocks)
3199 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
3201 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
3205 /* If we're working around r7000 errata, there must be two instructions
3206 between an mfhi or mflo and any instruction that uses the result. */
3207 if (mips_7000_hilo_fix
3208 && !mips_opts.micromips
3209 && MF_HILO_INSN (pinfo1)
3210 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1)))
3213 /* If we're working around 24K errata, one instruction is required
3214 if an ERET or DERET is followed by a branch instruction. */
3215 if (mips_fix_24k && !mips_opts.micromips)
3217 if (insn1->insn_opcode == INSN_ERET
3218 || insn1->insn_opcode == INSN_DERET)
3221 || insn2->insn_opcode == INSN_ERET
3222 || insn2->insn_opcode == INSN_DERET
3223 || delayed_branch_p (insn2))
3228 /* If working around VR4120 errata, check for combinations that need
3229 a single intervening instruction. */
3230 if (mips_fix_vr4120 && !mips_opts.micromips)
3232 unsigned int class1, class2;
3234 class1 = classify_vr4120_insn (insn1->insn_mo->name);
3235 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
3239 class2 = classify_vr4120_insn (insn2->insn_mo->name);
3240 if (vr4120_conflicts[class1] & (1 << class2))
3245 if (!HAVE_CODE_COMPRESSION)
3247 /* Check for GPR or coprocessor load delays. All such delays
3248 are on the RT register. */
3249 /* Itbl support may require additional care here. */
3250 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
3251 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
3253 know (pinfo1 & INSN_WRITE_GPR_T);
3254 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1)))
3258 /* Check for generic coprocessor hazards.
3260 This case is not handled very well. There is no special
3261 knowledge of CP0 handling, and the coprocessors other than
3262 the floating point unit are not distinguished at all. */
3263 /* Itbl support may require additional care here. FIXME!
3264 Need to modify this to include knowledge about
3265 user specified delays! */
3266 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
3267 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
3269 /* Handle cases where INSN1 writes to a known general coprocessor
3270 register. There must be a one instruction delay before INSN2
3271 if INSN2 reads that register, otherwise no delay is needed. */
3272 mask = fpr_write_mask (insn1);
3275 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
3280 /* Read-after-write dependencies on the control registers
3281 require a two-instruction gap. */
3282 if ((pinfo1 & INSN_WRITE_COND_CODE)
3283 && (pinfo2 & INSN_READ_COND_CODE))
3286 /* We don't know exactly what INSN1 does. If INSN2 is
3287 also a coprocessor instruction, assume there must be
3288 a one instruction gap. */
3289 if (pinfo2 & INSN_COP)
3294 /* Check for read-after-write dependencies on the coprocessor
3295 control registers in cases where INSN1 does not need a general
3296 coprocessor delay. This means that INSN1 is a floating point
3297 comparison instruction. */
3298 /* Itbl support may require additional care here. */
3299 else if (!cop_interlocks
3300 && (pinfo1 & INSN_WRITE_COND_CODE)
3301 && (pinfo2 & INSN_READ_COND_CODE))
3305 #undef INSN2_USES_GPR
3310 /* Return the number of nops that would be needed to work around the
3311 VR4130 mflo/mfhi errata if instruction INSN immediately followed
3312 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
3313 that are contained within the first IGNORE instructions of HIST. */
3316 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
3317 const struct mips_cl_insn *insn)
3322 /* Check if the instruction writes to HI or LO. MTHI and MTLO
3323 are not affected by the errata. */
3325 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
3326 || strcmp (insn->insn_mo->name, "mtlo") == 0
3327 || strcmp (insn->insn_mo->name, "mthi") == 0))
3330 /* Search for the first MFLO or MFHI. */
3331 for (i = 0; i < MAX_VR4130_NOPS; i++)
3332 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
3334 /* Extract the destination register. */
3335 mask = gpr_write_mask (&hist[i]);
3337 /* No nops are needed if INSN reads that register. */
3338 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
3341 /* ...or if any of the intervening instructions do. */
3342 for (j = 0; j < i; j++)
3343 if (gpr_read_mask (&hist[j]) & mask)
3347 return MAX_VR4130_NOPS - i;
3352 #define BASE_REG_EQ(INSN1, INSN2) \
3353 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
3354 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
3356 /* Return the minimum alignment for this store instruction. */
3359 fix_24k_align_to (const struct mips_opcode *mo)
3361 if (strcmp (mo->name, "sh") == 0)
3364 if (strcmp (mo->name, "swc1") == 0
3365 || strcmp (mo->name, "swc2") == 0
3366 || strcmp (mo->name, "sw") == 0
3367 || strcmp (mo->name, "sc") == 0
3368 || strcmp (mo->name, "s.s") == 0)
3371 if (strcmp (mo->name, "sdc1") == 0
3372 || strcmp (mo->name, "sdc2") == 0
3373 || strcmp (mo->name, "s.d") == 0)
3380 struct fix_24k_store_info
3382 /* Immediate offset, if any, for this store instruction. */
3384 /* Alignment required by this store instruction. */
3386 /* True for register offsets. */
3387 int register_offset;
3390 /* Comparison function used by qsort. */
3393 fix_24k_sort (const void *a, const void *b)
3395 const struct fix_24k_store_info *pos1 = a;
3396 const struct fix_24k_store_info *pos2 = b;
3398 return (pos1->off - pos2->off);
3401 /* INSN is a store instruction. Try to record the store information
3402 in STINFO. Return false if the information isn't known. */
3405 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
3406 const struct mips_cl_insn *insn)
3408 /* The instruction must have a known offset. */
3409 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
3412 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
3413 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
3417 /* Return the number of nops that would be needed to work around the 24k
3418 "lost data on stores during refill" errata if instruction INSN
3419 immediately followed the 2 instructions described by HIST.
3420 Ignore hazards that are contained within the first IGNORE
3421 instructions of HIST.
3423 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
3424 for the data cache refills and store data. The following describes
3425 the scenario where the store data could be lost.
3427 * A data cache miss, due to either a load or a store, causing fill
3428 data to be supplied by the memory subsystem
3429 * The first three doublewords of fill data are returned and written
3431 * A sequence of four stores occurs in consecutive cycles around the
3432 final doubleword of the fill:
3436 * Zero, One or more instructions
3439 The four stores A-D must be to different doublewords of the line that
3440 is being filled. The fourth instruction in the sequence above permits
3441 the fill of the final doubleword to be transferred from the FSB into
3442 the cache. In the sequence above, the stores may be either integer
3443 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
3444 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
3445 different doublewords on the line. If the floating point unit is
3446 running in 1:2 mode, it is not possible to create the sequence above
3447 using only floating point store instructions.
3449 In this case, the cache line being filled is incorrectly marked
3450 invalid, thereby losing the data from any store to the line that
3451 occurs between the original miss and the completion of the five
3452 cycle sequence shown above.
3454 The workarounds are:
3456 * Run the data cache in write-through mode.
3457 * Insert a non-store instruction between
3458 Store A and Store B or Store B and Store C. */
3461 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
3462 const struct mips_cl_insn *insn)
3464 struct fix_24k_store_info pos[3];
3465 int align, i, base_offset;
3470 /* If the previous instruction wasn't a store, there's nothing to
3472 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3475 /* If the instructions after the previous one are unknown, we have
3476 to assume the worst. */
3480 /* Check whether we are dealing with three consecutive stores. */
3481 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
3482 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3485 /* If we don't know the relationship between the store addresses,
3486 assume the worst. */
3487 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
3488 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
3491 if (!fix_24k_record_store_info (&pos[0], insn)
3492 || !fix_24k_record_store_info (&pos[1], &hist[0])
3493 || !fix_24k_record_store_info (&pos[2], &hist[1]))
3496 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
3498 /* Pick a value of ALIGN and X such that all offsets are adjusted by
3499 X bytes and such that the base register + X is known to be aligned
3502 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
3506 align = pos[0].align_to;
3507 base_offset = pos[0].off;
3508 for (i = 1; i < 3; i++)
3509 if (align < pos[i].align_to)
3511 align = pos[i].align_to;
3512 base_offset = pos[i].off;
3514 for (i = 0; i < 3; i++)
3515 pos[i].off -= base_offset;
3518 pos[0].off &= ~align + 1;
3519 pos[1].off &= ~align + 1;
3520 pos[2].off &= ~align + 1;
3522 /* If any two stores write to the same chunk, they also write to the
3523 same doubleword. The offsets are still sorted at this point. */
3524 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
3527 /* A range of at least 9 bytes is needed for the stores to be in
3528 non-overlapping doublewords. */
3529 if (pos[2].off - pos[0].off <= 8)
3532 if (pos[2].off - pos[1].off >= 24
3533 || pos[1].off - pos[0].off >= 24
3534 || pos[2].off - pos[0].off >= 32)
3540 /* Return the number of nops that would be needed if instruction INSN
3541 immediately followed the MAX_NOPS instructions given by HIST,
3542 where HIST[0] is the most recent instruction. Ignore hazards
3543 between INSN and the first IGNORE instructions in HIST.
3545 If INSN is null, return the worse-case number of nops for any
3549 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
3550 const struct mips_cl_insn *insn)
3552 int i, nops, tmp_nops;
3555 for (i = ignore; i < MAX_DELAY_NOPS; i++)
3557 tmp_nops = insns_between (hist + i, insn) - i;
3558 if (tmp_nops > nops)
3562 if (mips_fix_vr4130 && !mips_opts.micromips)
3564 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
3565 if (tmp_nops > nops)
3569 if (mips_fix_24k && !mips_opts.micromips)
3571 tmp_nops = nops_for_24k (ignore, hist, insn);
3572 if (tmp_nops > nops)
3579 /* The variable arguments provide NUM_INSNS extra instructions that
3580 might be added to HIST. Return the largest number of nops that
3581 would be needed after the extended sequence, ignoring hazards
3582 in the first IGNORE instructions. */
3585 nops_for_sequence (int num_insns, int ignore,
3586 const struct mips_cl_insn *hist, ...)
3589 struct mips_cl_insn buffer[MAX_NOPS];
3590 struct mips_cl_insn *cursor;
3593 va_start (args, hist);
3594 cursor = buffer + num_insns;
3595 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
3596 while (cursor > buffer)
3597 *--cursor = *va_arg (args, const struct mips_cl_insn *);
3599 nops = nops_for_insn (ignore, buffer, NULL);
3604 /* Like nops_for_insn, but if INSN is a branch, take into account the
3605 worst-case delay for the branch target. */
3608 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
3609 const struct mips_cl_insn *insn)
3613 nops = nops_for_insn (ignore, hist, insn);
3614 if (delayed_branch_p (insn))
3616 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
3617 hist, insn, get_delay_slot_nop (insn));
3618 if (tmp_nops > nops)
3621 else if (compact_branch_p (insn))
3623 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
3624 if (tmp_nops > nops)
3630 /* Fix NOP issue: Replace nops by "or at,at,zero". */
3633 fix_loongson2f_nop (struct mips_cl_insn * ip)
3635 gas_assert (!HAVE_CODE_COMPRESSION);
3636 if (strcmp (ip->insn_mo->name, "nop") == 0)
3637 ip->insn_opcode = LOONGSON2F_NOP_INSN;
3640 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
3641 jr target pc &= 'hffff_ffff_cfff_ffff. */
3644 fix_loongson2f_jump (struct mips_cl_insn * ip)
3646 gas_assert (!HAVE_CODE_COMPRESSION);
3647 if (strcmp (ip->insn_mo->name, "j") == 0
3648 || strcmp (ip->insn_mo->name, "jr") == 0
3649 || strcmp (ip->insn_mo->name, "jalr") == 0)
3657 sreg = EXTRACT_OPERAND (0, RS, *ip);
3658 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
3661 ep.X_op = O_constant;
3662 ep.X_add_number = 0xcfff0000;
3663 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
3664 ep.X_add_number = 0xffff;
3665 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
3666 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
3671 fix_loongson2f (struct mips_cl_insn * ip)
3673 if (mips_fix_loongson2f_nop)
3674 fix_loongson2f_nop (ip);
3676 if (mips_fix_loongson2f_jump)
3677 fix_loongson2f_jump (ip);
3680 /* IP is a branch that has a delay slot, and we need to fill it
3681 automatically. Return true if we can do that by swapping IP
3682 with the previous instruction. */
3685 can_swap_branch_p (struct mips_cl_insn *ip)
3687 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
3688 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
3690 /* -O2 and above is required for this optimization. */
3691 if (mips_optimize < 2)
3694 /* If we have seen .set volatile or .set nomove, don't optimize. */
3695 if (mips_opts.nomove)
3698 /* We can't swap if the previous instruction's position is fixed. */
3699 if (history[0].fixed_p)
3702 /* If the previous previous insn was in a .set noreorder, we can't
3703 swap. Actually, the MIPS assembler will swap in this situation.
3704 However, gcc configured -with-gnu-as will generate code like
3712 in which we can not swap the bne and INSN. If gcc is not configured
3713 -with-gnu-as, it does not output the .set pseudo-ops. */
3714 if (history[1].noreorder_p)
3717 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
3718 This means that the previous instruction was a 4-byte one anyhow. */
3719 if (mips_opts.mips16 && history[0].fixp[0])
3722 /* If the branch is itself the target of a branch, we can not swap.
3723 We cheat on this; all we check for is whether there is a label on
3724 this instruction. If there are any branches to anything other than
3725 a label, users must use .set noreorder. */
3726 if (seg_info (now_seg)->label_list)
3729 /* If the previous instruction is in a variant frag other than this
3730 branch's one, we cannot do the swap. This does not apply to
3731 MIPS16 code, which uses variant frags for different purposes. */
3732 if (!mips_opts.mips16
3734 && history[0].frag->fr_type == rs_machine_dependent)
3737 /* We do not swap with instructions that cannot architecturally
3738 be placed in a branch delay slot, such as SYNC or ERET. We
3739 also refrain from swapping with a trap instruction, since it
3740 complicates trap handlers to have the trap instruction be in
3742 prev_pinfo = history[0].insn_mo->pinfo;
3743 if (prev_pinfo & INSN_NO_DELAY_SLOT)
3746 /* Check for conflicts between the branch and the instructions
3747 before the candidate delay slot. */
3748 if (nops_for_insn (0, history + 1, ip) > 0)
3751 /* Check for conflicts between the swapped sequence and the
3752 target of the branch. */
3753 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
3756 /* If the branch reads a register that the previous
3757 instruction sets, we can not swap. */
3758 gpr_read = gpr_read_mask (ip);
3759 prev_gpr_write = gpr_write_mask (&history[0]);
3760 if (gpr_read & prev_gpr_write)
3763 /* If the branch writes a register that the previous
3764 instruction sets, we can not swap. */
3765 gpr_write = gpr_write_mask (ip);
3766 if (gpr_write & prev_gpr_write)
3769 /* If the branch writes a register that the previous
3770 instruction reads, we can not swap. */
3771 prev_gpr_read = gpr_read_mask (&history[0]);
3772 if (gpr_write & prev_gpr_read)
3775 /* If one instruction sets a condition code and the
3776 other one uses a condition code, we can not swap. */
3777 pinfo = ip->insn_mo->pinfo;
3778 if ((pinfo & INSN_READ_COND_CODE)
3779 && (prev_pinfo & INSN_WRITE_COND_CODE))
3781 if ((pinfo & INSN_WRITE_COND_CODE)
3782 && (prev_pinfo & INSN_READ_COND_CODE))
3785 /* If the previous instruction uses the PC, we can not swap. */
3786 prev_pinfo2 = history[0].insn_mo->pinfo2;
3787 if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC))
3789 if (mips_opts.micromips && (prev_pinfo2 & INSN2_READ_PC))
3792 /* If the previous instruction has an incorrect size for a fixed
3793 branch delay slot in microMIPS mode, we cannot swap. */
3794 pinfo2 = ip->insn_mo->pinfo2;
3795 if (mips_opts.micromips
3796 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
3797 && insn_length (history) != 2)
3799 if (mips_opts.micromips
3800 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
3801 && insn_length (history) != 4)
3807 /* Decide how we should add IP to the instruction stream. */
3809 static enum append_method
3810 get_append_method (struct mips_cl_insn *ip)
3812 unsigned long pinfo;
3814 /* The relaxed version of a macro sequence must be inherently
3816 if (mips_relax.sequence == 2)
3819 /* We must not dabble with instructions in a ".set norerorder" block. */
3820 if (mips_opts.noreorder)
3823 /* Otherwise, it's our responsibility to fill branch delay slots. */
3824 if (delayed_branch_p (ip))
3826 if (!branch_likely_p (ip) && can_swap_branch_p (ip))
3829 pinfo = ip->insn_mo->pinfo;
3830 if (mips_opts.mips16
3831 && ISA_SUPPORTS_MIPS16E
3832 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)))
3833 return APPEND_ADD_COMPACT;
3835 return APPEND_ADD_WITH_NOP;
3841 /* IP is a MIPS16 instruction whose opcode we have just changed.
3842 Point IP->insn_mo to the new opcode's definition. */
3845 find_altered_mips16_opcode (struct mips_cl_insn *ip)
3847 const struct mips_opcode *mo, *end;
3849 end = &mips16_opcodes[bfd_mips16_num_opcodes];
3850 for (mo = ip->insn_mo; mo < end; mo++)
3851 if ((ip->insn_opcode & mo->mask) == mo->match)
3859 /* For microMIPS macros, we need to generate a local number label
3860 as the target of branches. */
3861 #define MICROMIPS_LABEL_CHAR '\037'
3862 static unsigned long micromips_target_label;
3863 static char micromips_target_name[32];
3866 micromips_label_name (void)
3868 char *p = micromips_target_name;
3869 char symbol_name_temporary[24];
3877 l = micromips_target_label;
3878 #ifdef LOCAL_LABEL_PREFIX
3879 *p++ = LOCAL_LABEL_PREFIX;
3882 *p++ = MICROMIPS_LABEL_CHAR;
3885 symbol_name_temporary[i++] = l % 10 + '0';
3890 *p++ = symbol_name_temporary[--i];
3893 return micromips_target_name;
3897 micromips_label_expr (expressionS *label_expr)
3899 label_expr->X_op = O_symbol;
3900 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
3901 label_expr->X_add_number = 0;
3905 micromips_label_inc (void)
3907 micromips_target_label++;
3908 *micromips_target_name = '\0';
3912 micromips_add_label (void)
3916 s = colon (micromips_label_name ());
3917 micromips_label_inc ();
3918 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
3920 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
3926 /* If assembling microMIPS code, then return the microMIPS reloc
3927 corresponding to the requested one if any. Otherwise return
3928 the reloc unchanged. */
3930 static bfd_reloc_code_real_type
3931 micromips_map_reloc (bfd_reloc_code_real_type reloc)
3933 static const bfd_reloc_code_real_type relocs[][2] =
3935 /* Keep sorted incrementally by the left-hand key. */
3936 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
3937 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
3938 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
3939 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
3940 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
3941 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
3942 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
3943 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
3944 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
3945 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
3946 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
3947 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
3948 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
3949 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
3950 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
3951 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
3952 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
3953 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
3954 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
3955 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
3956 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
3957 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
3958 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
3959 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
3960 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
3961 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
3962 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
3964 bfd_reloc_code_real_type r;
3967 if (!mips_opts.micromips)
3969 for (i = 0; i < ARRAY_SIZE (relocs); i++)
3975 return relocs[i][1];
3980 /* Output an instruction. IP is the instruction information.
3981 ADDRESS_EXPR is an operand of the instruction to be used with
3982 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
3983 a macro expansion. */
3986 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
3987 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
3989 unsigned long prev_pinfo2, pinfo;
3990 bfd_boolean relaxed_branch = FALSE;
3991 enum append_method method;
3992 bfd_boolean relax32;
3995 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
3996 fix_loongson2f (ip);
3998 mips_mark_labels ();
4000 file_ase_mips16 |= mips_opts.mips16;
4001 file_ase_micromips |= mips_opts.micromips;
4003 prev_pinfo2 = history[0].insn_mo->pinfo2;
4004 pinfo = ip->insn_mo->pinfo;
4006 if (mips_opts.micromips
4008 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
4009 && micromips_insn_length (ip->insn_mo) != 2)
4010 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
4011 && micromips_insn_length (ip->insn_mo) != 4)))
4012 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
4013 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
4015 if (address_expr == NULL)
4017 else if (*reloc_type <= BFD_RELOC_UNUSED
4018 && address_expr->X_op == O_constant)
4023 switch (*reloc_type)
4026 ip->insn_opcode |= address_expr->X_add_number;
4029 case BFD_RELOC_MIPS_HIGHEST:
4030 tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48;
4031 ip->insn_opcode |= tmp & 0xffff;
4034 case BFD_RELOC_MIPS_HIGHER:
4035 tmp = (address_expr->X_add_number + 0x80008000ull) >> 32;
4036 ip->insn_opcode |= tmp & 0xffff;
4039 case BFD_RELOC_HI16_S:
4040 tmp = (address_expr->X_add_number + 0x8000) >> 16;
4041 ip->insn_opcode |= tmp & 0xffff;
4044 case BFD_RELOC_HI16:
4045 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
4048 case BFD_RELOC_UNUSED:
4049 case BFD_RELOC_LO16:
4050 case BFD_RELOC_MIPS_GOT_DISP:
4051 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
4054 case BFD_RELOC_MIPS_JMP:
4058 shift = mips_opts.micromips ? 1 : 2;
4059 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4060 as_bad (_("jump to misaligned address (0x%lx)"),
4061 (unsigned long) address_expr->X_add_number);
4062 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4068 case BFD_RELOC_MIPS16_JMP:
4069 if ((address_expr->X_add_number & 3) != 0)
4070 as_bad (_("jump to misaligned address (0x%lx)"),
4071 (unsigned long) address_expr->X_add_number);
4073 (((address_expr->X_add_number & 0x7c0000) << 3)
4074 | ((address_expr->X_add_number & 0xf800000) >> 7)
4075 | ((address_expr->X_add_number & 0x3fffc) >> 2));
4079 case BFD_RELOC_16_PCREL_S2:
4083 shift = mips_opts.micromips ? 1 : 2;
4084 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4085 as_bad (_("branch to misaligned address (0x%lx)"),
4086 (unsigned long) address_expr->X_add_number);
4087 if (!mips_relax_branch)
4089 if ((address_expr->X_add_number + (1 << (shift + 15)))
4090 & ~((1 << (shift + 16)) - 1))
4091 as_bad (_("branch address range overflow (0x%lx)"),
4092 (unsigned long) address_expr->X_add_number);
4093 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4105 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
4107 /* There are a lot of optimizations we could do that we don't.
4108 In particular, we do not, in general, reorder instructions.
4109 If you use gcc with optimization, it will reorder
4110 instructions and generally do much more optimization then we
4111 do here; repeating all that work in the assembler would only
4112 benefit hand written assembly code, and does not seem worth
4114 int nops = (mips_optimize == 0
4115 ? nops_for_insn (0, history, NULL)
4116 : nops_for_insn_or_target (0, history, ip));
4120 unsigned long old_frag_offset;
4123 old_frag = frag_now;
4124 old_frag_offset = frag_now_fix ();
4126 for (i = 0; i < nops; i++)
4127 add_fixed_insn (NOP_INSN);
4128 insert_into_history (0, nops, NOP_INSN);
4132 listing_prev_line ();
4133 /* We may be at the start of a variant frag. In case we
4134 are, make sure there is enough space for the frag
4135 after the frags created by listing_prev_line. The
4136 argument to frag_grow here must be at least as large
4137 as the argument to all other calls to frag_grow in
4138 this file. We don't have to worry about being in the
4139 middle of a variant frag, because the variants insert
4140 all needed nop instructions themselves. */
4144 mips_move_labels ();
4146 #ifndef NO_ECOFF_DEBUGGING
4147 if (ECOFF_DEBUGGING)
4148 ecoff_fix_loc (old_frag, old_frag_offset);
4152 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
4156 /* Work out how many nops in prev_nop_frag are needed by IP,
4157 ignoring hazards generated by the first prev_nop_frag_since
4159 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
4160 gas_assert (nops <= prev_nop_frag_holds);
4162 /* Enforce NOPS as a minimum. */
4163 if (nops > prev_nop_frag_required)
4164 prev_nop_frag_required = nops;
4166 if (prev_nop_frag_holds == prev_nop_frag_required)
4168 /* Settle for the current number of nops. Update the history
4169 accordingly (for the benefit of any future .set reorder code). */
4170 prev_nop_frag = NULL;
4171 insert_into_history (prev_nop_frag_since,
4172 prev_nop_frag_holds, NOP_INSN);
4176 /* Allow this instruction to replace one of the nops that was
4177 tentatively added to prev_nop_frag. */
4178 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
4179 prev_nop_frag_holds--;
4180 prev_nop_frag_since++;
4184 method = get_append_method (ip);
4185 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
4188 /* The value passed to dwarf2_emit_insn is the distance between
4189 the beginning of the current instruction and the address that
4190 should be recorded in the debug tables. This is normally the
4193 For MIPS16/microMIPS debug info we want to use ISA-encoded
4194 addresses, so we use -1 for an address higher by one than the
4197 If the instruction produced is a branch that we will swap with
4198 the preceding instruction, then we add the displacement by which
4199 the branch will be moved backwards. This is more appropriate
4200 and for MIPS16/microMIPS code also prevents a debugger from
4201 placing a breakpoint in the middle of the branch (and corrupting
4202 code if software breakpoints are used). */
4203 dwarf2_emit_insn ((HAVE_CODE_COMPRESSION ? -1 : 0) + branch_disp);
4206 relax32 = (mips_relax_branch
4207 /* Don't try branch relaxation within .set nomacro, or within
4208 .set noat if we use $at for PIC computations. If it turns
4209 out that the branch was out-of-range, we'll get an error. */
4210 && !mips_opts.warn_about_macros
4211 && (mips_opts.at || mips_pic == NO_PIC)
4212 /* Don't relax BPOSGE32/64 as they have no complementing
4214 && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP)));
4216 if (!HAVE_CODE_COMPRESSION
4219 && *reloc_type == BFD_RELOC_16_PCREL_S2
4220 && delayed_branch_p (ip))
4222 relaxed_branch = TRUE;
4223 add_relaxed_insn (ip, (relaxed_branch_length
4225 uncond_branch_p (ip) ? -1
4226 : branch_likely_p (ip) ? 1
4230 uncond_branch_p (ip),
4231 branch_likely_p (ip),
4232 pinfo & INSN_WRITE_GPR_31,
4234 address_expr->X_add_symbol,
4235 address_expr->X_add_number);
4236 *reloc_type = BFD_RELOC_UNUSED;
4238 else if (mips_opts.micromips
4240 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
4241 || *reloc_type > BFD_RELOC_UNUSED)
4242 && (delayed_branch_p (ip) || compact_branch_p (ip))
4243 /* Don't try branch relaxation when users specify
4244 16-bit/32-bit instructions. */
4245 && !forced_insn_length)
4247 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
4248 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
4249 int uncond = uncond_branch_p (ip) ? -1 : 0;
4250 int compact = compact_branch_p (ip);
4251 int al = pinfo & INSN_WRITE_GPR_31;
4254 gas_assert (address_expr != NULL);
4255 gas_assert (!mips_relax.sequence);
4257 relaxed_branch = TRUE;
4258 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
4259 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
4260 RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al,
4262 address_expr->X_add_symbol,
4263 address_expr->X_add_number);
4264 *reloc_type = BFD_RELOC_UNUSED;
4266 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
4268 /* We need to set up a variant frag. */
4269 gas_assert (address_expr != NULL);
4270 add_relaxed_insn (ip, 4, 0,
4272 (*reloc_type - BFD_RELOC_UNUSED,
4273 forced_insn_length == 2, forced_insn_length == 4,
4274 delayed_branch_p (&history[0]),
4275 history[0].mips16_absolute_jump_p),
4276 make_expr_symbol (address_expr), 0);
4278 else if (mips_opts.mips16
4280 && *reloc_type != BFD_RELOC_MIPS16_JMP)
4282 if (!delayed_branch_p (ip))
4283 /* Make sure there is enough room to swap this instruction with
4284 a following jump instruction. */
4286 add_fixed_insn (ip);
4290 if (mips_opts.mips16
4291 && mips_opts.noreorder
4292 && delayed_branch_p (&history[0]))
4293 as_warn (_("extended instruction in delay slot"));
4295 if (mips_relax.sequence)
4297 /* If we've reached the end of this frag, turn it into a variant
4298 frag and record the information for the instructions we've
4300 if (frag_room () < 4)
4301 relax_close_frag ();
4302 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
4305 if (mips_relax.sequence != 2)
4307 if (mips_macro_warning.first_insn_sizes[0] == 0)
4308 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
4309 mips_macro_warning.sizes[0] += insn_length (ip);
4310 mips_macro_warning.insns[0]++;
4312 if (mips_relax.sequence != 1)
4314 if (mips_macro_warning.first_insn_sizes[1] == 0)
4315 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
4316 mips_macro_warning.sizes[1] += insn_length (ip);
4317 mips_macro_warning.insns[1]++;
4320 if (mips_opts.mips16)
4323 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
4325 add_fixed_insn (ip);
4328 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
4330 bfd_reloc_code_real_type final_type[3];
4331 reloc_howto_type *howto0;
4332 reloc_howto_type *howto;
4335 /* Perform any necessary conversion to microMIPS relocations
4336 and find out how many relocations there actually are. */
4337 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
4338 final_type[i] = micromips_map_reloc (reloc_type[i]);
4340 /* In a compound relocation, it is the final (outermost)
4341 operator that determines the relocated field. */
4342 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
4346 /* To reproduce this failure try assembling gas/testsuites/
4347 gas/mips/mips16-intermix.s with a mips-ecoff targeted
4349 as_bad (_("Unsupported MIPS relocation number %d"),
4351 howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16);
4355 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
4356 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
4357 bfd_get_reloc_size (howto),
4359 howto0 && howto0->pc_relative,
4362 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
4363 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
4364 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
4366 /* These relocations can have an addend that won't fit in
4367 4 octets for 64bit assembly. */
4369 && ! howto->partial_inplace
4370 && (reloc_type[0] == BFD_RELOC_16
4371 || reloc_type[0] == BFD_RELOC_32
4372 || reloc_type[0] == BFD_RELOC_MIPS_JMP
4373 || reloc_type[0] == BFD_RELOC_GPREL16
4374 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
4375 || reloc_type[0] == BFD_RELOC_GPREL32
4376 || reloc_type[0] == BFD_RELOC_64
4377 || reloc_type[0] == BFD_RELOC_CTOR
4378 || reloc_type[0] == BFD_RELOC_MIPS_SUB
4379 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
4380 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
4381 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
4382 || reloc_type[0] == BFD_RELOC_MIPS_REL16
4383 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
4384 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
4385 || hi16_reloc_p (reloc_type[0])
4386 || lo16_reloc_p (reloc_type[0])))
4387 ip->fixp[0]->fx_no_overflow = 1;
4389 if (mips_relax.sequence)
4391 if (mips_relax.first_fixup == 0)
4392 mips_relax.first_fixup = ip->fixp[0];
4394 else if (reloc_needs_lo_p (*reloc_type))
4396 struct mips_hi_fixup *hi_fixup;
4398 /* Reuse the last entry if it already has a matching %lo. */
4399 hi_fixup = mips_hi_fixup_list;
4401 || !fixup_has_matching_lo_p (hi_fixup->fixp))
4403 hi_fixup = ((struct mips_hi_fixup *)
4404 xmalloc (sizeof (struct mips_hi_fixup)));
4405 hi_fixup->next = mips_hi_fixup_list;
4406 mips_hi_fixup_list = hi_fixup;
4408 hi_fixup->fixp = ip->fixp[0];
4409 hi_fixup->seg = now_seg;
4412 /* Add fixups for the second and third relocations, if given.
4413 Note that the ABI allows the second relocation to be
4414 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
4415 moment we only use RSS_UNDEF, but we could add support
4416 for the others if it ever becomes necessary. */
4417 for (i = 1; i < 3; i++)
4418 if (reloc_type[i] != BFD_RELOC_UNUSED)
4420 ip->fixp[i] = fix_new (ip->frag, ip->where,
4421 ip->fixp[0]->fx_size, NULL, 0,
4422 FALSE, final_type[i]);
4424 /* Use fx_tcbit to mark compound relocs. */
4425 ip->fixp[0]->fx_tcbit = 1;
4426 ip->fixp[i]->fx_tcbit = 1;
4431 /* Update the register mask information. */
4432 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
4433 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
4438 insert_into_history (0, 1, ip);
4441 case APPEND_ADD_WITH_NOP:
4443 struct mips_cl_insn *nop;
4445 insert_into_history (0, 1, ip);
4446 nop = get_delay_slot_nop (ip);
4447 add_fixed_insn (nop);
4448 insert_into_history (0, 1, nop);
4449 if (mips_relax.sequence)
4450 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
4454 case APPEND_ADD_COMPACT:
4455 /* Convert MIPS16 jr/jalr into a "compact" jump. */
4456 gas_assert (mips_opts.mips16);
4457 ip->insn_opcode |= 0x0080;
4458 find_altered_mips16_opcode (ip);
4460 insert_into_history (0, 1, ip);
4465 struct mips_cl_insn delay = history[0];
4466 if (mips_opts.mips16)
4468 know (delay.frag == ip->frag);
4469 move_insn (ip, delay.frag, delay.where);
4470 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
4472 else if (relaxed_branch)
4474 /* Add the delay slot instruction to the end of the
4475 current frag and shrink the fixed part of the
4476 original frag. If the branch occupies the tail of
4477 the latter, move it backwards to cover the gap. */
4478 delay.frag->fr_fix -= branch_disp;
4479 if (delay.frag == ip->frag)
4480 move_insn (ip, ip->frag, ip->where - branch_disp);
4481 add_fixed_insn (&delay);
4485 move_insn (&delay, ip->frag,
4486 ip->where - branch_disp + insn_length (ip));
4487 move_insn (ip, history[0].frag, history[0].where);
4491 insert_into_history (0, 1, &delay);
4496 /* If we have just completed an unconditional branch, clear the history. */
4497 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
4498 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
4499 mips_no_prev_insn ();
4501 /* We need to emit a label at the end of branch-likely macros. */
4502 if (emit_branch_likely_macro)
4504 emit_branch_likely_macro = FALSE;
4505 micromips_add_label ();
4508 /* We just output an insn, so the next one doesn't have a label. */
4509 mips_clear_insn_labels ();
4512 /* Forget that there was any previous instruction or label. */
4515 mips_no_prev_insn (void)
4517 prev_nop_frag = NULL;
4518 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
4519 mips_clear_insn_labels ();
4522 /* This function must be called before we emit something other than
4523 instructions. It is like mips_no_prev_insn except that it inserts
4524 any NOPS that might be needed by previous instructions. */
4527 mips_emit_delays (void)
4529 if (! mips_opts.noreorder)
4531 int nops = nops_for_insn (0, history, NULL);
4535 add_fixed_insn (NOP_INSN);
4536 mips_move_labels ();
4539 mips_no_prev_insn ();
4542 /* Start a (possibly nested) noreorder block. */
4545 start_noreorder (void)
4547 if (mips_opts.noreorder == 0)
4552 /* None of the instructions before the .set noreorder can be moved. */
4553 for (i = 0; i < ARRAY_SIZE (history); i++)
4554 history[i].fixed_p = 1;
4556 /* Insert any nops that might be needed between the .set noreorder
4557 block and the previous instructions. We will later remove any
4558 nops that turn out not to be needed. */
4559 nops = nops_for_insn (0, history, NULL);
4562 if (mips_optimize != 0)
4564 /* Record the frag which holds the nop instructions, so
4565 that we can remove them if we don't need them. */
4566 frag_grow (nops * NOP_INSN_SIZE);
4567 prev_nop_frag = frag_now;
4568 prev_nop_frag_holds = nops;
4569 prev_nop_frag_required = 0;
4570 prev_nop_frag_since = 0;
4573 for (; nops > 0; --nops)
4574 add_fixed_insn (NOP_INSN);
4576 /* Move on to a new frag, so that it is safe to simply
4577 decrease the size of prev_nop_frag. */
4578 frag_wane (frag_now);
4580 mips_move_labels ();
4582 mips_mark_labels ();
4583 mips_clear_insn_labels ();
4585 mips_opts.noreorder++;
4586 mips_any_noreorder = 1;
4589 /* End a nested noreorder block. */
4592 end_noreorder (void)
4594 mips_opts.noreorder--;
4595 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
4597 /* Commit to inserting prev_nop_frag_required nops and go back to
4598 handling nop insertion the .set reorder way. */
4599 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
4601 insert_into_history (prev_nop_frag_since,
4602 prev_nop_frag_required, NOP_INSN);
4603 prev_nop_frag = NULL;
4607 /* Set up global variables for the start of a new macro. */
4612 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
4613 memset (&mips_macro_warning.first_insn_sizes, 0,
4614 sizeof (mips_macro_warning.first_insn_sizes));
4615 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
4616 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
4617 && delayed_branch_p (&history[0]));
4618 switch (history[0].insn_mo->pinfo2
4619 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
4621 case INSN2_BRANCH_DELAY_32BIT:
4622 mips_macro_warning.delay_slot_length = 4;
4624 case INSN2_BRANCH_DELAY_16BIT:
4625 mips_macro_warning.delay_slot_length = 2;
4628 mips_macro_warning.delay_slot_length = 0;
4631 mips_macro_warning.first_frag = NULL;
4634 /* Given that a macro is longer than one instruction or of the wrong size,
4635 return the appropriate warning for it. Return null if no warning is
4636 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
4637 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
4638 and RELAX_NOMACRO. */
4641 macro_warning (relax_substateT subtype)
4643 if (subtype & RELAX_DELAY_SLOT)
4644 return _("Macro instruction expanded into multiple instructions"
4645 " in a branch delay slot");
4646 else if (subtype & RELAX_NOMACRO)
4647 return _("Macro instruction expanded into multiple instructions");
4648 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
4649 | RELAX_DELAY_SLOT_SIZE_SECOND))
4650 return ((subtype & RELAX_DELAY_SLOT_16BIT)
4651 ? _("Macro instruction expanded into a wrong size instruction"
4652 " in a 16-bit branch delay slot")
4653 : _("Macro instruction expanded into a wrong size instruction"
4654 " in a 32-bit branch delay slot"));
4659 /* Finish up a macro. Emit warnings as appropriate. */
4664 /* Relaxation warning flags. */
4665 relax_substateT subtype = 0;
4667 /* Check delay slot size requirements. */
4668 if (mips_macro_warning.delay_slot_length == 2)
4669 subtype |= RELAX_DELAY_SLOT_16BIT;
4670 if (mips_macro_warning.delay_slot_length != 0)
4672 if (mips_macro_warning.delay_slot_length
4673 != mips_macro_warning.first_insn_sizes[0])
4674 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
4675 if (mips_macro_warning.delay_slot_length
4676 != mips_macro_warning.first_insn_sizes[1])
4677 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
4680 /* Check instruction count requirements. */
4681 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
4683 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
4684 subtype |= RELAX_SECOND_LONGER;
4685 if (mips_opts.warn_about_macros)
4686 subtype |= RELAX_NOMACRO;
4687 if (mips_macro_warning.delay_slot_p)
4688 subtype |= RELAX_DELAY_SLOT;
4691 /* If both alternatives fail to fill a delay slot correctly,
4692 emit the warning now. */
4693 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
4694 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
4699 s = subtype & (RELAX_DELAY_SLOT_16BIT
4700 | RELAX_DELAY_SLOT_SIZE_FIRST
4701 | RELAX_DELAY_SLOT_SIZE_SECOND);
4702 msg = macro_warning (s);
4704 as_warn ("%s", msg);
4708 /* If both implementations are longer than 1 instruction, then emit the
4710 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
4715 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
4716 msg = macro_warning (s);
4718 as_warn ("%s", msg);
4722 /* If any flags still set, then one implementation might need a warning
4723 and the other either will need one of a different kind or none at all.
4724 Pass any remaining flags over to relaxation. */
4725 if (mips_macro_warning.first_frag != NULL)
4726 mips_macro_warning.first_frag->fr_subtype |= subtype;
4729 /* Instruction operand formats used in macros that vary between
4730 standard MIPS and microMIPS code. */
4732 static const char * const brk_fmt[2] = { "c", "mF" };
4733 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
4734 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
4735 static const char * const lui_fmt[2] = { "t,u", "s,u" };
4736 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
4737 static const char * const mfhl_fmt[2] = { "d", "mj" };
4738 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
4739 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
4741 #define BRK_FMT (brk_fmt[mips_opts.micromips])
4742 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
4743 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
4744 #define LUI_FMT (lui_fmt[mips_opts.micromips])
4745 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
4746 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips])
4747 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
4748 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
4750 /* Read a macro's relocation codes from *ARGS and store them in *R.
4751 The first argument in *ARGS will be either the code for a single
4752 relocation or -1 followed by the three codes that make up a
4753 composite relocation. */
4756 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
4760 next = va_arg (*args, int);
4762 r[0] = (bfd_reloc_code_real_type) next;
4764 for (i = 0; i < 3; i++)
4765 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
4768 /* Build an instruction created by a macro expansion. This is passed
4769 a pointer to the count of instructions created so far, an
4770 expression, the name of the instruction to build, an operand format
4771 string, and corresponding arguments. */
4774 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
4776 const struct mips_opcode *mo = NULL;
4777 bfd_reloc_code_real_type r[3];
4778 const struct mips_opcode *amo;
4779 struct hash_control *hash;
4780 struct mips_cl_insn insn;
4783 va_start (args, fmt);
4785 if (mips_opts.mips16)
4787 mips16_macro_build (ep, name, fmt, &args);
4792 r[0] = BFD_RELOC_UNUSED;
4793 r[1] = BFD_RELOC_UNUSED;
4794 r[2] = BFD_RELOC_UNUSED;
4795 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
4796 amo = (struct mips_opcode *) hash_find (hash, name);
4798 gas_assert (strcmp (name, amo->name) == 0);
4802 /* Search until we get a match for NAME. It is assumed here that
4803 macros will never generate MDMX, MIPS-3D, or MT instructions.
4804 We try to match an instruction that fulfils the branch delay
4805 slot instruction length requirement (if any) of the previous
4806 instruction. While doing this we record the first instruction
4807 seen that matches all the other conditions and use it anyway
4808 if the requirement cannot be met; we will issue an appropriate
4809 warning later on. */
4810 if (strcmp (fmt, amo->args) == 0
4811 && amo->pinfo != INSN_MACRO
4812 && is_opcode_valid (amo)
4813 && is_size_valid (amo))
4815 if (is_delay_slot_valid (amo))
4825 gas_assert (amo->name);
4827 while (strcmp (name, amo->name) == 0);
4830 create_insn (&insn, mo);
4848 INSERT_OPERAND (mips_opts.micromips,
4849 EXTLSB, insn, va_arg (args, int));
4854 /* Note that in the macro case, these arguments are already
4855 in MSB form. (When handling the instruction in the
4856 non-macro case, these arguments are sizes from which
4857 MSB values must be calculated.) */
4858 INSERT_OPERAND (mips_opts.micromips,
4859 INSMSB, insn, va_arg (args, int));
4865 /* Note that in the macro case, these arguments are already
4866 in MSBD form. (When handling the instruction in the
4867 non-macro case, these arguments are sizes from which
4868 MSBD values must be calculated.) */
4869 INSERT_OPERAND (mips_opts.micromips,
4870 EXTMSBD, insn, va_arg (args, int));
4874 gas_assert (!mips_opts.micromips);
4875 INSERT_OPERAND (0, SEQI, insn, va_arg (args, int));
4884 gas_assert (!mips_opts.micromips);
4885 INSERT_OPERAND (0, BP, insn, va_arg (args, int));
4889 gas_assert (mips_opts.micromips);
4893 INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int));
4897 gas_assert (!mips_opts.micromips);
4898 INSERT_OPERAND (0, CODE, insn, va_arg (args, int));
4902 gas_assert (!mips_opts.micromips);
4904 INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int));
4908 if (mips_opts.micromips)
4909 INSERT_OPERAND (1, RS, insn, va_arg (args, int));
4911 INSERT_OPERAND (0, RD, insn, va_arg (args, int));
4915 gas_assert (!mips_opts.micromips);
4917 INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int));
4921 gas_assert (!mips_opts.micromips);
4923 int tmp = va_arg (args, int);
4925 INSERT_OPERAND (0, RT, insn, tmp);
4926 INSERT_OPERAND (0, RD, insn, tmp);
4932 gas_assert (!mips_opts.micromips);
4933 INSERT_OPERAND (0, FS, insn, va_arg (args, int));
4940 INSERT_OPERAND (mips_opts.micromips,
4941 SHAMT, insn, va_arg (args, int));
4945 gas_assert (!mips_opts.micromips);
4946 INSERT_OPERAND (0, FD, insn, va_arg (args, int));
4950 gas_assert (!mips_opts.micromips);
4951 INSERT_OPERAND (0, CODE20, insn, va_arg (args, int));
4955 gas_assert (!mips_opts.micromips);
4956 INSERT_OPERAND (0, CODE19, insn, va_arg (args, int));
4960 gas_assert (!mips_opts.micromips);
4961 INSERT_OPERAND (0, CODE2, insn, va_arg (args, int));
4968 INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int));
4973 macro_read_relocs (&args, r);
4974 gas_assert (*r == BFD_RELOC_GPREL16
4975 || *r == BFD_RELOC_MIPS_HIGHER
4976 || *r == BFD_RELOC_HI16_S
4977 || *r == BFD_RELOC_LO16
4978 || *r == BFD_RELOC_MIPS_GOT_OFST);
4982 macro_read_relocs (&args, r);
4986 macro_read_relocs (&args, r);
4987 gas_assert (ep != NULL
4988 && (ep->X_op == O_constant
4989 || (ep->X_op == O_symbol
4990 && (*r == BFD_RELOC_MIPS_HIGHEST
4991 || *r == BFD_RELOC_HI16_S
4992 || *r == BFD_RELOC_HI16
4993 || *r == BFD_RELOC_GPREL16
4994 || *r == BFD_RELOC_MIPS_GOT_HI16
4995 || *r == BFD_RELOC_MIPS_CALL_HI16))));
4999 gas_assert (ep != NULL);
5002 * This allows macro() to pass an immediate expression for
5003 * creating short branches without creating a symbol.
5005 * We don't allow branch relaxation for these branches, as
5006 * they should only appear in ".set nomacro" anyway.
5008 if (ep->X_op == O_constant)
5010 /* For microMIPS we always use relocations for branches.
5011 So we should not resolve immediate values. */
5012 gas_assert (!mips_opts.micromips);
5014 if ((ep->X_add_number & 3) != 0)
5015 as_bad (_("branch to misaligned address (0x%lx)"),
5016 (unsigned long) ep->X_add_number);
5017 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
5018 as_bad (_("branch address range overflow (0x%lx)"),
5019 (unsigned long) ep->X_add_number);
5020 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
5024 *r = BFD_RELOC_16_PCREL_S2;
5028 gas_assert (ep != NULL);
5029 *r = BFD_RELOC_MIPS_JMP;
5033 gas_assert (!mips_opts.micromips);
5034 INSERT_OPERAND (0, COPZ, insn, va_arg (args, unsigned long));
5038 INSERT_OPERAND (mips_opts.micromips,
5039 CACHE, insn, va_arg (args, unsigned long));
5043 gas_assert (mips_opts.micromips);
5044 INSERT_OPERAND (1, TRAP, insn, va_arg (args, int));
5048 gas_assert (mips_opts.micromips);
5049 INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int));
5053 INSERT_OPERAND (mips_opts.micromips,
5054 3BITPOS, insn, va_arg (args, unsigned int));
5058 INSERT_OPERAND (mips_opts.micromips,
5059 OFFSET12, insn, va_arg (args, unsigned long));
5063 gas_assert (mips_opts.micromips);
5064 INSERT_OPERAND (1, BCC, insn, va_arg (args, int));
5067 case 'm': /* Opcode extension character. */
5068 gas_assert (mips_opts.micromips);
5072 INSERT_OPERAND (1, MJ, insn, va_arg (args, int));
5076 INSERT_OPERAND (1, MP, insn, va_arg (args, int));
5080 INSERT_OPERAND (1, IMMF, insn, va_arg (args, int));
5094 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5096 append_insn (&insn, ep, r, TRUE);
5100 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
5103 struct mips_opcode *mo;
5104 struct mips_cl_insn insn;
5105 bfd_reloc_code_real_type r[3]
5106 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
5108 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
5110 gas_assert (strcmp (name, mo->name) == 0);
5112 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
5115 gas_assert (mo->name);
5116 gas_assert (strcmp (name, mo->name) == 0);
5119 create_insn (&insn, mo);
5137 MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int));
5142 MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int));
5146 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int));
5150 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int));
5160 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int));
5167 regno = va_arg (*args, int);
5168 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
5169 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
5190 gas_assert (ep != NULL);
5192 if (ep->X_op != O_constant)
5193 *r = (int) BFD_RELOC_UNUSED + c;
5196 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
5197 FALSE, &insn.insn_opcode, &insn.use_extend,
5200 *r = BFD_RELOC_UNUSED;
5206 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int));
5213 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5215 append_insn (&insn, ep, r, TRUE);
5219 * Sign-extend 32-bit mode constants that have bit 31 set and all
5220 * higher bits unset.
5223 normalize_constant_expr (expressionS *ex)
5225 if (ex->X_op == O_constant
5226 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5227 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5232 * Sign-extend 32-bit mode address offsets that have bit 31 set and
5233 * all higher bits unset.
5236 normalize_address_expr (expressionS *ex)
5238 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
5239 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
5240 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5241 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5246 * Generate a "jalr" instruction with a relocation hint to the called
5247 * function. This occurs in NewABI PIC code.
5250 macro_build_jalr (expressionS *ep, int cprestore)
5252 static const bfd_reloc_code_real_type jalr_relocs[2]
5253 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
5254 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
5258 if (MIPS_JALR_HINT_P (ep))
5263 if (!mips_opts.micromips)
5264 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
5267 jalr = mips_opts.noreorder && !cprestore ? "jalr" : "jalrs";
5268 if (MIPS_JALR_HINT_P (ep))
5269 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
5271 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
5273 if (MIPS_JALR_HINT_P (ep))
5274 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
5278 * Generate a "lui" instruction.
5281 macro_build_lui (expressionS *ep, int regnum)
5283 gas_assert (! mips_opts.mips16);
5285 if (ep->X_op != O_constant)
5287 gas_assert (ep->X_op == O_symbol);
5288 /* _gp_disp is a special case, used from s_cpload.
5289 __gnu_local_gp is used if mips_no_shared. */
5290 gas_assert (mips_pic == NO_PIC
5292 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
5293 || (! mips_in_shared
5294 && strcmp (S_GET_NAME (ep->X_add_symbol),
5295 "__gnu_local_gp") == 0));
5298 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
5301 /* Generate a sequence of instructions to do a load or store from a constant
5302 offset off of a base register (breg) into/from a target register (treg),
5303 using AT if necessary. */
5305 macro_build_ldst_constoffset (expressionS *ep, const char *op,
5306 int treg, int breg, int dbl)
5308 gas_assert (ep->X_op == O_constant);
5310 /* Sign-extending 32-bit constants makes their handling easier. */
5312 normalize_constant_expr (ep);
5314 /* Right now, this routine can only handle signed 32-bit constants. */
5315 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
5316 as_warn (_("operand overflow"));
5318 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
5320 /* Signed 16-bit offset will fit in the op. Easy! */
5321 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
5325 /* 32-bit offset, need multiple instructions and AT, like:
5326 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
5327 addu $tempreg,$tempreg,$breg
5328 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
5329 to handle the complete offset. */
5330 macro_build_lui (ep, AT);
5331 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
5332 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
5335 as_bad (_("Macro used $at after \".set noat\""));
5340 * Generates code to set the $at register to true (one)
5341 * if reg is less than the immediate expression.
5344 set_at (int reg, int unsignedp)
5346 if (imm_expr.X_op == O_constant
5347 && imm_expr.X_add_number >= -0x8000
5348 && imm_expr.X_add_number < 0x8000)
5349 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
5350 AT, reg, BFD_RELOC_LO16);
5353 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5354 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
5358 /* Warn if an expression is not a constant. */
5361 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
5363 if (ex->X_op == O_big)
5364 as_bad (_("unsupported large constant"));
5365 else if (ex->X_op != O_constant)
5366 as_bad (_("Instruction %s requires absolute expression"),
5369 if (HAVE_32BIT_GPRS)
5370 normalize_constant_expr (ex);
5373 /* Count the leading zeroes by performing a binary chop. This is a
5374 bulky bit of source, but performance is a LOT better for the
5375 majority of values than a simple loop to count the bits:
5376 for (lcnt = 0; (lcnt < 32); lcnt++)
5377 if ((v) & (1 << (31 - lcnt)))
5379 However it is not code size friendly, and the gain will drop a bit
5380 on certain cached systems.
5382 #define COUNT_TOP_ZEROES(v) \
5383 (((v) & ~0xffff) == 0 \
5384 ? ((v) & ~0xff) == 0 \
5385 ? ((v) & ~0xf) == 0 \
5386 ? ((v) & ~0x3) == 0 \
5387 ? ((v) & ~0x1) == 0 \
5392 : ((v) & ~0x7) == 0 \
5395 : ((v) & ~0x3f) == 0 \
5396 ? ((v) & ~0x1f) == 0 \
5399 : ((v) & ~0x7f) == 0 \
5402 : ((v) & ~0xfff) == 0 \
5403 ? ((v) & ~0x3ff) == 0 \
5404 ? ((v) & ~0x1ff) == 0 \
5407 : ((v) & ~0x7ff) == 0 \
5410 : ((v) & ~0x3fff) == 0 \
5411 ? ((v) & ~0x1fff) == 0 \
5414 : ((v) & ~0x7fff) == 0 \
5417 : ((v) & ~0xffffff) == 0 \
5418 ? ((v) & ~0xfffff) == 0 \
5419 ? ((v) & ~0x3ffff) == 0 \
5420 ? ((v) & ~0x1ffff) == 0 \
5423 : ((v) & ~0x7ffff) == 0 \
5426 : ((v) & ~0x3fffff) == 0 \
5427 ? ((v) & ~0x1fffff) == 0 \
5430 : ((v) & ~0x7fffff) == 0 \
5433 : ((v) & ~0xfffffff) == 0 \
5434 ? ((v) & ~0x3ffffff) == 0 \
5435 ? ((v) & ~0x1ffffff) == 0 \
5438 : ((v) & ~0x7ffffff) == 0 \
5441 : ((v) & ~0x3fffffff) == 0 \
5442 ? ((v) & ~0x1fffffff) == 0 \
5445 : ((v) & ~0x7fffffff) == 0 \
5450 * This routine generates the least number of instructions necessary to load
5451 * an absolute expression value into a register.
5454 load_register (int reg, expressionS *ep, int dbl)
5457 expressionS hi32, lo32;
5459 if (ep->X_op != O_big)
5461 gas_assert (ep->X_op == O_constant);
5463 /* Sign-extending 32-bit constants makes their handling easier. */
5465 normalize_constant_expr (ep);
5467 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
5469 /* We can handle 16 bit signed values with an addiu to
5470 $zero. No need to ever use daddiu here, since $zero and
5471 the result are always correct in 32 bit mode. */
5472 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5475 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
5477 /* We can handle 16 bit unsigned values with an ori to
5479 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
5482 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
5484 /* 32 bit values require an lui. */
5485 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5486 if ((ep->X_add_number & 0xffff) != 0)
5487 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
5492 /* The value is larger than 32 bits. */
5494 if (!dbl || HAVE_32BIT_GPRS)
5498 sprintf_vma (value, ep->X_add_number);
5499 as_bad (_("Number (0x%s) larger than 32 bits"), value);
5500 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5504 if (ep->X_op != O_big)
5507 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
5508 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
5509 hi32.X_add_number &= 0xffffffff;
5511 lo32.X_add_number &= 0xffffffff;
5515 gas_assert (ep->X_add_number > 2);
5516 if (ep->X_add_number == 3)
5517 generic_bignum[3] = 0;
5518 else if (ep->X_add_number > 4)
5519 as_bad (_("Number larger than 64 bits"));
5520 lo32.X_op = O_constant;
5521 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
5522 hi32.X_op = O_constant;
5523 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
5526 if (hi32.X_add_number == 0)
5531 unsigned long hi, lo;
5533 if (hi32.X_add_number == (offsetT) 0xffffffff)
5535 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
5537 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5540 if (lo32.X_add_number & 0x80000000)
5542 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5543 if (lo32.X_add_number & 0xffff)
5544 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
5549 /* Check for 16bit shifted constant. We know that hi32 is
5550 non-zero, so start the mask on the first bit of the hi32
5555 unsigned long himask, lomask;
5559 himask = 0xffff >> (32 - shift);
5560 lomask = (0xffff << shift) & 0xffffffff;
5564 himask = 0xffff << (shift - 32);
5567 if ((hi32.X_add_number & ~(offsetT) himask) == 0
5568 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
5572 tmp.X_op = O_constant;
5574 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
5575 | (lo32.X_add_number >> shift));
5577 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
5578 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
5579 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
5580 reg, reg, (shift >= 32) ? shift - 32 : shift);
5585 while (shift <= (64 - 16));
5587 /* Find the bit number of the lowest one bit, and store the
5588 shifted value in hi/lo. */
5589 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
5590 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
5594 while ((lo & 1) == 0)
5599 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
5605 while ((hi & 1) == 0)
5614 /* Optimize if the shifted value is a (power of 2) - 1. */
5615 if ((hi == 0 && ((lo + 1) & lo) == 0)
5616 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
5618 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
5623 /* This instruction will set the register to be all
5625 tmp.X_op = O_constant;
5626 tmp.X_add_number = (offsetT) -1;
5627 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5631 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
5632 reg, reg, (bit >= 32) ? bit - 32 : bit);
5634 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
5635 reg, reg, (shift >= 32) ? shift - 32 : shift);
5640 /* Sign extend hi32 before calling load_register, because we can
5641 generally get better code when we load a sign extended value. */
5642 if ((hi32.X_add_number & 0x80000000) != 0)
5643 hi32.X_add_number |= ~(offsetT) 0xffffffff;
5644 load_register (reg, &hi32, 0);
5647 if ((lo32.X_add_number & 0xffff0000) == 0)
5651 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
5659 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
5661 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5662 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
5668 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
5672 mid16.X_add_number >>= 16;
5673 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
5674 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5677 if ((lo32.X_add_number & 0xffff) != 0)
5678 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
5682 load_delay_nop (void)
5684 if (!gpr_interlocks)
5685 macro_build (NULL, "nop", "");
5688 /* Load an address into a register. */
5691 load_address (int reg, expressionS *ep, int *used_at)
5693 if (ep->X_op != O_constant
5694 && ep->X_op != O_symbol)
5696 as_bad (_("expression too complex"));
5697 ep->X_op = O_constant;
5700 if (ep->X_op == O_constant)
5702 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
5706 if (mips_pic == NO_PIC)
5708 /* If this is a reference to a GP relative symbol, we want
5709 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
5711 lui $reg,<sym> (BFD_RELOC_HI16_S)
5712 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5713 If we have an addend, we always use the latter form.
5715 With 64bit address space and a usable $at we want
5716 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5717 lui $at,<sym> (BFD_RELOC_HI16_S)
5718 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5719 daddiu $at,<sym> (BFD_RELOC_LO16)
5723 If $at is already in use, we use a path which is suboptimal
5724 on superscalar processors.
5725 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5726 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5728 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
5730 daddiu $reg,<sym> (BFD_RELOC_LO16)
5732 For GP relative symbols in 64bit address space we can use
5733 the same sequence as in 32bit address space. */
5734 if (HAVE_64BIT_SYMBOLS)
5736 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
5737 && !nopic_need_relax (ep->X_add_symbol, 1))
5739 relax_start (ep->X_add_symbol);
5740 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
5741 mips_gp_register, BFD_RELOC_GPREL16);
5745 if (*used_at == 0 && mips_opts.at)
5747 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
5748 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
5749 macro_build (ep, "daddiu", "t,r,j", reg, reg,
5750 BFD_RELOC_MIPS_HIGHER);
5751 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
5752 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
5753 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
5758 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
5759 macro_build (ep, "daddiu", "t,r,j", reg, reg,
5760 BFD_RELOC_MIPS_HIGHER);
5761 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5762 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
5763 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5764 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
5767 if (mips_relax.sequence)
5772 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
5773 && !nopic_need_relax (ep->X_add_symbol, 1))
5775 relax_start (ep->X_add_symbol);
5776 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
5777 mips_gp_register, BFD_RELOC_GPREL16);
5780 macro_build_lui (ep, reg);
5781 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
5782 reg, reg, BFD_RELOC_LO16);
5783 if (mips_relax.sequence)
5787 else if (!mips_big_got)
5791 /* If this is a reference to an external symbol, we want
5792 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5794 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5796 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5797 If there is a constant, it must be added in after.
5799 If we have NewABI, we want
5800 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5801 unless we're referencing a global symbol with a non-zero
5802 offset, in which case cst must be added separately. */
5805 if (ep->X_add_number)
5807 ex.X_add_number = ep->X_add_number;
5808 ep->X_add_number = 0;
5809 relax_start (ep->X_add_symbol);
5810 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5811 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5812 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5813 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5814 ex.X_op = O_constant;
5815 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
5816 reg, reg, BFD_RELOC_LO16);
5817 ep->X_add_number = ex.X_add_number;
5820 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5821 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5822 if (mips_relax.sequence)
5827 ex.X_add_number = ep->X_add_number;
5828 ep->X_add_number = 0;
5829 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5830 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5832 relax_start (ep->X_add_symbol);
5834 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5838 if (ex.X_add_number != 0)
5840 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5841 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5842 ex.X_op = O_constant;
5843 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
5844 reg, reg, BFD_RELOC_LO16);
5848 else if (mips_big_got)
5852 /* This is the large GOT case. If this is a reference to an
5853 external symbol, we want
5854 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5856 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
5858 Otherwise, for a reference to a local symbol in old ABI, we want
5859 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5861 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5862 If there is a constant, it must be added in after.
5864 In the NewABI, for local symbols, with or without offsets, we want:
5865 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5866 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5870 ex.X_add_number = ep->X_add_number;
5871 ep->X_add_number = 0;
5872 relax_start (ep->X_add_symbol);
5873 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
5874 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5875 reg, reg, mips_gp_register);
5876 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
5877 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
5878 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5879 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5880 else if (ex.X_add_number)
5882 ex.X_op = O_constant;
5883 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5887 ep->X_add_number = ex.X_add_number;
5889 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5890 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
5891 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5892 BFD_RELOC_MIPS_GOT_OFST);
5897 ex.X_add_number = ep->X_add_number;
5898 ep->X_add_number = 0;
5899 relax_start (ep->X_add_symbol);
5900 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
5901 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5902 reg, reg, mips_gp_register);
5903 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
5904 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
5906 if (reg_needs_delay (mips_gp_register))
5908 /* We need a nop before loading from $gp. This special
5909 check is required because the lui which starts the main
5910 instruction stream does not refer to $gp, and so will not
5911 insert the nop which may be required. */
5912 macro_build (NULL, "nop", "");
5914 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5915 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5917 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5921 if (ex.X_add_number != 0)
5923 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5924 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5925 ex.X_op = O_constant;
5926 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5934 if (!mips_opts.at && *used_at == 1)
5935 as_bad (_("Macro used $at after \".set noat\""));
5938 /* Move the contents of register SOURCE into register DEST. */
5941 move_register (int dest, int source)
5943 /* Prefer to use a 16-bit microMIPS instruction unless the previous
5944 instruction specifically requires a 32-bit one. */
5945 if (mips_opts.micromips
5946 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
5947 macro_build (NULL, "move", "mp,mj", dest, source);
5949 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
5953 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
5954 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
5955 The two alternatives are:
5957 Global symbol Local sybmol
5958 ------------- ------------
5959 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
5961 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
5963 load_got_offset emits the first instruction and add_got_offset
5964 emits the second for a 16-bit offset or add_got_offset_hilo emits
5965 a sequence to add a 32-bit offset using a scratch register. */
5968 load_got_offset (int dest, expressionS *local)
5973 global.X_add_number = 0;
5975 relax_start (local->X_add_symbol);
5976 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
5977 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5979 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
5980 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5985 add_got_offset (int dest, expressionS *local)
5989 global.X_op = O_constant;
5990 global.X_op_symbol = NULL;
5991 global.X_add_symbol = NULL;
5992 global.X_add_number = local->X_add_number;
5994 relax_start (local->X_add_symbol);
5995 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
5996 dest, dest, BFD_RELOC_LO16);
5998 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
6003 add_got_offset_hilo (int dest, expressionS *local, int tmp)
6006 int hold_mips_optimize;
6008 global.X_op = O_constant;
6009 global.X_op_symbol = NULL;
6010 global.X_add_symbol = NULL;
6011 global.X_add_number = local->X_add_number;
6013 relax_start (local->X_add_symbol);
6014 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
6016 /* Set mips_optimize around the lui instruction to avoid
6017 inserting an unnecessary nop after the lw. */
6018 hold_mips_optimize = mips_optimize;
6020 macro_build_lui (&global, tmp);
6021 mips_optimize = hold_mips_optimize;
6022 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
6025 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
6028 /* Emit a sequence of instructions to emulate a branch likely operation.
6029 BR is an ordinary branch corresponding to one to be emulated. BRNEG
6030 is its complementing branch with the original condition negated.
6031 CALL is set if the original branch specified the link operation.
6032 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
6034 Code like this is produced in the noreorder mode:
6039 delay slot (executed only if branch taken)
6047 delay slot (executed only if branch taken)
6050 In the reorder mode the delay slot would be filled with a nop anyway,
6051 so code produced is simply:
6056 This function is used when producing code for the microMIPS ASE that
6057 does not implement branch likely instructions in hardware. */
6060 macro_build_branch_likely (const char *br, const char *brneg,
6061 int call, expressionS *ep, const char *fmt,
6062 unsigned int sreg, unsigned int treg)
6064 int noreorder = mips_opts.noreorder;
6067 gas_assert (mips_opts.micromips);
6071 micromips_label_expr (&expr1);
6072 macro_build (&expr1, brneg, fmt, sreg, treg);
6073 macro_build (NULL, "nop", "");
6074 macro_build (ep, call ? "bal" : "b", "p");
6076 /* Set to true so that append_insn adds a label. */
6077 emit_branch_likely_macro = TRUE;
6081 macro_build (ep, br, fmt, sreg, treg);
6082 macro_build (NULL, "nop", "");
6087 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
6088 the condition code tested. EP specifies the branch target. */
6091 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
6118 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
6121 /* Emit a two-argument branch macro specified by TYPE, using SREG as
6122 the register tested. EP specifies the branch target. */
6125 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
6127 const char *brneg = NULL;
6137 br = mips_opts.micromips ? "bgez" : "bgezl";
6141 gas_assert (mips_opts.micromips);
6150 br = mips_opts.micromips ? "bgtz" : "bgtzl";
6157 br = mips_opts.micromips ? "blez" : "blezl";
6164 br = mips_opts.micromips ? "bltz" : "bltzl";
6168 gas_assert (mips_opts.micromips);
6176 if (mips_opts.micromips && brneg)
6177 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
6179 macro_build (ep, br, "s,p", sreg);
6182 /* Emit a three-argument branch macro specified by TYPE, using SREG and
6183 TREG as the registers tested. EP specifies the branch target. */
6186 macro_build_branch_rsrt (int type, expressionS *ep,
6187 unsigned int sreg, unsigned int treg)
6189 const char *brneg = NULL;
6201 br = mips_opts.micromips ? "beq" : "beql";
6210 br = mips_opts.micromips ? "bne" : "bnel";
6216 if (mips_opts.micromips && brneg)
6217 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
6219 macro_build (ep, br, "s,t,p", sreg, treg);
6224 * This routine implements the seemingly endless macro or synthesized
6225 * instructions and addressing modes in the mips assembly language. Many
6226 * of these macros are simple and are similar to each other. These could
6227 * probably be handled by some kind of table or grammar approach instead of
6228 * this verbose method. Others are not simple macros but are more like
6229 * optimizing code generation.
6230 * One interesting optimization is when several store macros appear
6231 * consecutively that would load AT with the upper half of the same address.
6232 * The ensuing load upper instructions are ommited. This implies some kind
6233 * of global optimization. We currently only optimize within a single macro.
6234 * For many of the load and store macros if the address is specified as a
6235 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
6236 * first load register 'at' with zero and use it as the base register. The
6237 * mips assembler simply uses register $zero. Just one tiny optimization
6241 macro (struct mips_cl_insn *ip)
6243 unsigned int treg, sreg, dreg, breg;
6244 unsigned int tempreg;
6247 expressionS label_expr;
6265 bfd_reloc_code_real_type r;
6266 int hold_mips_optimize;
6268 gas_assert (! mips_opts.mips16);
6270 treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
6271 dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
6272 sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
6273 mask = ip->insn_mo->mask;
6275 label_expr.X_op = O_constant;
6276 label_expr.X_op_symbol = NULL;
6277 label_expr.X_add_symbol = NULL;
6278 label_expr.X_add_number = 0;
6280 expr1.X_op = O_constant;
6281 expr1.X_op_symbol = NULL;
6282 expr1.X_add_symbol = NULL;
6283 expr1.X_add_number = 1;
6298 if (mips_opts.micromips)
6299 micromips_label_expr (&label_expr);
6301 label_expr.X_add_number = 8;
6302 macro_build (&label_expr, "bgez", "s,p", sreg);
6304 macro_build (NULL, "nop", "");
6306 move_register (dreg, sreg);
6307 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
6308 if (mips_opts.micromips)
6309 micromips_add_label ();
6326 if (!mips_opts.micromips)
6328 if (imm_expr.X_op == O_constant
6329 && imm_expr.X_add_number >= -0x200
6330 && imm_expr.X_add_number < 0x200)
6332 macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number);
6341 if (imm_expr.X_op == O_constant
6342 && imm_expr.X_add_number >= -0x8000
6343 && imm_expr.X_add_number < 0x8000)
6345 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
6350 load_register (AT, &imm_expr, dbl);
6351 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6370 if (imm_expr.X_op == O_constant
6371 && imm_expr.X_add_number >= 0
6372 && imm_expr.X_add_number < 0x10000)
6374 if (mask != M_NOR_I)
6375 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
6378 macro_build (&imm_expr, "ori", "t,r,i",
6379 treg, sreg, BFD_RELOC_LO16);
6380 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
6386 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
6387 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6391 switch (imm_expr.X_add_number)
6394 macro_build (NULL, "nop", "");
6397 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
6400 macro_build (NULL, "balign", "t,s,2", treg, sreg,
6401 (int) imm_expr.X_add_number);
6410 gas_assert (mips_opts.micromips);
6411 macro_build_branch_ccl (mask, &offset_expr,
6412 EXTRACT_OPERAND (1, BCC, *ip));
6419 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6425 load_register (treg, &imm_expr, HAVE_64BIT_GPRS);
6430 macro_build_branch_rsrt (mask, &offset_expr, sreg, treg);
6437 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg);
6439 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg);
6443 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
6444 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6445 &offset_expr, AT, ZERO);
6455 macro_build_branch_rs (mask, &offset_expr, sreg);
6461 /* Check for > max integer. */
6462 maxnum = 0x7fffffff;
6463 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6470 if (imm_expr.X_op == O_constant
6471 && imm_expr.X_add_number >= maxnum
6472 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6475 /* Result is always false. */
6477 macro_build (NULL, "nop", "");
6479 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
6482 if (imm_expr.X_op != O_constant)
6483 as_bad (_("Unsupported large constant"));
6484 ++imm_expr.X_add_number;
6488 if (mask == M_BGEL_I)
6490 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6492 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
6493 &offset_expr, sreg);
6496 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6498 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
6499 &offset_expr, sreg);
6502 maxnum = 0x7fffffff;
6503 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6510 maxnum = - maxnum - 1;
6511 if (imm_expr.X_op == O_constant
6512 && imm_expr.X_add_number <= maxnum
6513 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6516 /* result is always true */
6517 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
6518 macro_build (&offset_expr, "b", "p");
6523 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6524 &offset_expr, AT, ZERO);
6533 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6534 &offset_expr, ZERO, treg);
6538 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
6539 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6540 &offset_expr, AT, ZERO);
6549 && imm_expr.X_op == O_constant
6550 && imm_expr.X_add_number == -1))
6552 if (imm_expr.X_op != O_constant)
6553 as_bad (_("Unsupported large constant"));
6554 ++imm_expr.X_add_number;
6558 if (mask == M_BGEUL_I)
6560 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6562 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6563 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6564 &offset_expr, sreg, ZERO);
6569 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6570 &offset_expr, AT, ZERO);
6578 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg);
6580 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg);
6584 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
6585 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6586 &offset_expr, AT, ZERO);
6594 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6595 &offset_expr, sreg, ZERO);
6601 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
6602 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6603 &offset_expr, AT, ZERO);
6611 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
6613 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg);
6617 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
6618 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6619 &offset_expr, AT, ZERO);
6626 maxnum = 0x7fffffff;
6627 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6634 if (imm_expr.X_op == O_constant
6635 && imm_expr.X_add_number >= maxnum
6636 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6638 if (imm_expr.X_op != O_constant)
6639 as_bad (_("Unsupported large constant"));
6640 ++imm_expr.X_add_number;
6644 if (mask == M_BLTL_I)
6646 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6647 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
6648 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6649 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
6654 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6655 &offset_expr, AT, ZERO);
6663 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6664 &offset_expr, sreg, ZERO);
6670 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
6671 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6672 &offset_expr, AT, ZERO);
6681 && imm_expr.X_op == O_constant
6682 && imm_expr.X_add_number == -1))
6684 if (imm_expr.X_op != O_constant)
6685 as_bad (_("Unsupported large constant"));
6686 ++imm_expr.X_add_number;
6690 if (mask == M_BLTUL_I)
6692 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6694 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6695 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6696 &offset_expr, sreg, ZERO);
6701 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6702 &offset_expr, AT, ZERO);
6710 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
6712 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg);
6716 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
6717 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6718 &offset_expr, AT, ZERO);
6728 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6729 &offset_expr, ZERO, treg);
6733 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
6734 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6735 &offset_expr, AT, ZERO);
6741 /* Use unsigned arithmetic. */
6745 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
6747 as_bad (_("Unsupported large constant"));
6752 pos = imm_expr.X_add_number;
6753 size = imm2_expr.X_add_number;
6758 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
6761 if (size == 0 || size > 64 || (pos + size - 1) > 63)
6763 as_bad (_("Improper extract size (%lu, position %lu)"),
6764 (unsigned long) size, (unsigned long) pos);
6768 if (size <= 32 && pos < 32)
6773 else if (size <= 32)
6783 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
6790 /* Use unsigned arithmetic. */
6794 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
6796 as_bad (_("Unsupported large constant"));
6801 pos = imm_expr.X_add_number;
6802 size = imm2_expr.X_add_number;
6807 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
6810 if (size == 0 || size > 64 || (pos + size - 1) > 63)
6812 as_bad (_("Improper insert size (%lu, position %lu)"),
6813 (unsigned long) size, (unsigned long) pos);
6817 if (pos < 32 && (pos + size - 1) < 32)
6832 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
6833 (int) (pos + size - 1));
6849 as_warn (_("Divide by zero."));
6851 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
6853 macro_build (NULL, "break", BRK_FMT, 7);
6860 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
6861 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
6865 if (mips_opts.micromips)
6866 micromips_label_expr (&label_expr);
6868 label_expr.X_add_number = 8;
6869 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
6870 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
6871 macro_build (NULL, "break", BRK_FMT, 7);
6872 if (mips_opts.micromips)
6873 micromips_add_label ();
6875 expr1.X_add_number = -1;
6877 load_register (AT, &expr1, dbl);
6878 if (mips_opts.micromips)
6879 micromips_label_expr (&label_expr);
6881 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
6882 macro_build (&label_expr, "bne", "s,t,p", treg, AT);
6885 expr1.X_add_number = 1;
6886 load_register (AT, &expr1, dbl);
6887 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
6891 expr1.X_add_number = 0x80000000;
6892 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
6896 macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6);
6897 /* We want to close the noreorder block as soon as possible, so
6898 that later insns are available for delay slot filling. */
6903 if (mips_opts.micromips)
6904 micromips_label_expr (&label_expr);
6906 label_expr.X_add_number = 8;
6907 macro_build (&label_expr, "bne", "s,t,p", sreg, AT);
6908 macro_build (NULL, "nop", "");
6910 /* We want to close the noreorder block as soon as possible, so
6911 that later insns are available for delay slot filling. */
6914 macro_build (NULL, "break", BRK_FMT, 6);
6916 if (mips_opts.micromips)
6917 micromips_add_label ();
6918 macro_build (NULL, s, MFHL_FMT, dreg);
6957 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6959 as_warn (_("Divide by zero."));
6961 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
6963 macro_build (NULL, "break", BRK_FMT, 7);
6966 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6968 if (strcmp (s2, "mflo") == 0)
6969 move_register (dreg, sreg);
6971 move_register (dreg, ZERO);
6974 if (imm_expr.X_op == O_constant
6975 && imm_expr.X_add_number == -1
6976 && s[strlen (s) - 1] != 'u')
6978 if (strcmp (s2, "mflo") == 0)
6980 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
6983 move_register (dreg, ZERO);
6988 load_register (AT, &imm_expr, dbl);
6989 macro_build (NULL, s, "z,s,t", sreg, AT);
6990 macro_build (NULL, s2, MFHL_FMT, dreg);
7012 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
7013 macro_build (NULL, s, "z,s,t", sreg, treg);
7014 /* We want to close the noreorder block as soon as possible, so
7015 that later insns are available for delay slot filling. */
7020 if (mips_opts.micromips)
7021 micromips_label_expr (&label_expr);
7023 label_expr.X_add_number = 8;
7024 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
7025 macro_build (NULL, s, "z,s,t", sreg, treg);
7027 /* We want to close the noreorder block as soon as possible, so
7028 that later insns are available for delay slot filling. */
7030 macro_build (NULL, "break", BRK_FMT, 7);
7031 if (mips_opts.micromips)
7032 micromips_add_label ();
7034 macro_build (NULL, s2, MFHL_FMT, dreg);
7046 /* Load the address of a symbol into a register. If breg is not
7047 zero, we then add a base register to it. */
7049 if (dbl && HAVE_32BIT_GPRS)
7050 as_warn (_("dla used to load 32-bit register"));
7052 if (!dbl && HAVE_64BIT_OBJECTS)
7053 as_warn (_("la used to load 64-bit address"));
7055 if (offset_expr.X_op == O_constant
7056 && offset_expr.X_add_number >= -0x8000
7057 && offset_expr.X_add_number < 0x8000)
7059 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
7060 "t,r,j", treg, sreg, BFD_RELOC_LO16);
7064 if (mips_opts.at && (treg == breg))
7074 if (offset_expr.X_op != O_symbol
7075 && offset_expr.X_op != O_constant)
7077 as_bad (_("Expression too complex"));
7078 offset_expr.X_op = O_constant;
7081 if (offset_expr.X_op == O_constant)
7082 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
7083 else if (mips_pic == NO_PIC)
7085 /* If this is a reference to a GP relative symbol, we want
7086 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
7088 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
7089 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7090 If we have a constant, we need two instructions anyhow,
7091 so we may as well always use the latter form.
7093 With 64bit address space and a usable $at we want
7094 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7095 lui $at,<sym> (BFD_RELOC_HI16_S)
7096 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7097 daddiu $at,<sym> (BFD_RELOC_LO16)
7099 daddu $tempreg,$tempreg,$at
7101 If $at is already in use, we use a path which is suboptimal
7102 on superscalar processors.
7103 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7104 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7106 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
7108 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
7110 For GP relative symbols in 64bit address space we can use
7111 the same sequence as in 32bit address space. */
7112 if (HAVE_64BIT_SYMBOLS)
7114 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7115 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7117 relax_start (offset_expr.X_add_symbol);
7118 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7119 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7123 if (used_at == 0 && mips_opts.at)
7125 macro_build (&offset_expr, "lui", LUI_FMT,
7126 tempreg, BFD_RELOC_MIPS_HIGHEST);
7127 macro_build (&offset_expr, "lui", LUI_FMT,
7128 AT, BFD_RELOC_HI16_S);
7129 macro_build (&offset_expr, "daddiu", "t,r,j",
7130 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7131 macro_build (&offset_expr, "daddiu", "t,r,j",
7132 AT, AT, BFD_RELOC_LO16);
7133 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
7134 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
7139 macro_build (&offset_expr, "lui", LUI_FMT,
7140 tempreg, BFD_RELOC_MIPS_HIGHEST);
7141 macro_build (&offset_expr, "daddiu", "t,r,j",
7142 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7143 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7144 macro_build (&offset_expr, "daddiu", "t,r,j",
7145 tempreg, tempreg, BFD_RELOC_HI16_S);
7146 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7147 macro_build (&offset_expr, "daddiu", "t,r,j",
7148 tempreg, tempreg, BFD_RELOC_LO16);
7151 if (mips_relax.sequence)
7156 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7157 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7159 relax_start (offset_expr.X_add_symbol);
7160 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7161 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7164 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
7165 as_bad (_("Offset too large"));
7166 macro_build_lui (&offset_expr, tempreg);
7167 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7168 tempreg, tempreg, BFD_RELOC_LO16);
7169 if (mips_relax.sequence)
7173 else if (!mips_big_got && !HAVE_NEWABI)
7175 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7177 /* If this is a reference to an external symbol, and there
7178 is no constant, we want
7179 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7180 or for lca or if tempreg is PIC_CALL_REG
7181 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7182 For a local symbol, we want
7183 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7185 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7187 If we have a small constant, and this is a reference to
7188 an external symbol, we want
7189 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7191 addiu $tempreg,$tempreg,<constant>
7192 For a local symbol, we want the same instruction
7193 sequence, but we output a BFD_RELOC_LO16 reloc on the
7196 If we have a large constant, and this is a reference to
7197 an external symbol, we want
7198 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7199 lui $at,<hiconstant>
7200 addiu $at,$at,<loconstant>
7201 addu $tempreg,$tempreg,$at
7202 For a local symbol, we want the same instruction
7203 sequence, but we output a BFD_RELOC_LO16 reloc on the
7207 if (offset_expr.X_add_number == 0)
7209 if (mips_pic == SVR4_PIC
7211 && (call || tempreg == PIC_CALL_REG))
7212 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
7214 relax_start (offset_expr.X_add_symbol);
7215 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7216 lw_reloc_type, mips_gp_register);
7219 /* We're going to put in an addu instruction using
7220 tempreg, so we may as well insert the nop right
7225 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7226 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
7228 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7229 tempreg, tempreg, BFD_RELOC_LO16);
7231 /* FIXME: If breg == 0, and the next instruction uses
7232 $tempreg, then if this variant case is used an extra
7233 nop will be generated. */
7235 else if (offset_expr.X_add_number >= -0x8000
7236 && offset_expr.X_add_number < 0x8000)
7238 load_got_offset (tempreg, &offset_expr);
7240 add_got_offset (tempreg, &offset_expr);
7244 expr1.X_add_number = offset_expr.X_add_number;
7245 offset_expr.X_add_number =
7246 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
7247 load_got_offset (tempreg, &offset_expr);
7248 offset_expr.X_add_number = expr1.X_add_number;
7249 /* If we are going to add in a base register, and the
7250 target register and the base register are the same,
7251 then we are using AT as a temporary register. Since
7252 we want to load the constant into AT, we add our
7253 current AT (from the global offset table) and the
7254 register into the register now, and pretend we were
7255 not using a base register. */
7259 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7264 add_got_offset_hilo (tempreg, &offset_expr, AT);
7268 else if (!mips_big_got && HAVE_NEWABI)
7270 int add_breg_early = 0;
7272 /* If this is a reference to an external, and there is no
7273 constant, or local symbol (*), with or without a
7275 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7276 or for lca or if tempreg is PIC_CALL_REG
7277 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7279 If we have a small constant, and this is a reference to
7280 an external symbol, we want
7281 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7282 addiu $tempreg,$tempreg,<constant>
7284 If we have a large constant, and this is a reference to
7285 an external symbol, we want
7286 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7287 lui $at,<hiconstant>
7288 addiu $at,$at,<loconstant>
7289 addu $tempreg,$tempreg,$at
7291 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
7292 local symbols, even though it introduces an additional
7295 if (offset_expr.X_add_number)
7297 expr1.X_add_number = offset_expr.X_add_number;
7298 offset_expr.X_add_number = 0;
7300 relax_start (offset_expr.X_add_symbol);
7301 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7302 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7304 if (expr1.X_add_number >= -0x8000
7305 && expr1.X_add_number < 0x8000)
7307 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7308 tempreg, tempreg, BFD_RELOC_LO16);
7310 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
7312 /* If we are going to add in a base register, and the
7313 target register and the base register are the same,
7314 then we are using AT as a temporary register. Since
7315 we want to load the constant into AT, we add our
7316 current AT (from the global offset table) and the
7317 register into the register now, and pretend we were
7318 not using a base register. */
7323 gas_assert (tempreg == AT);
7324 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7330 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7331 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7337 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7340 offset_expr.X_add_number = expr1.X_add_number;
7342 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7343 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7346 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7347 treg, tempreg, breg);
7353 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
7355 relax_start (offset_expr.X_add_symbol);
7356 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7357 BFD_RELOC_MIPS_CALL16, mips_gp_register);
7359 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7360 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7365 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7366 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7369 else if (mips_big_got && !HAVE_NEWABI)
7372 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
7373 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
7374 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7376 /* This is the large GOT case. If this is a reference to an
7377 external symbol, and there is no constant, we want
7378 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7379 addu $tempreg,$tempreg,$gp
7380 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7381 or for lca or if tempreg is PIC_CALL_REG
7382 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7383 addu $tempreg,$tempreg,$gp
7384 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7385 For a local symbol, we want
7386 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7388 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7390 If we have a small constant, and this is a reference to
7391 an external symbol, we want
7392 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7393 addu $tempreg,$tempreg,$gp
7394 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7396 addiu $tempreg,$tempreg,<constant>
7397 For a local symbol, we want
7398 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7400 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
7402 If we have a large constant, and this is a reference to
7403 an external symbol, we want
7404 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7405 addu $tempreg,$tempreg,$gp
7406 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7407 lui $at,<hiconstant>
7408 addiu $at,$at,<loconstant>
7409 addu $tempreg,$tempreg,$at
7410 For a local symbol, we want
7411 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7412 lui $at,<hiconstant>
7413 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
7414 addu $tempreg,$tempreg,$at
7417 expr1.X_add_number = offset_expr.X_add_number;
7418 offset_expr.X_add_number = 0;
7419 relax_start (offset_expr.X_add_symbol);
7420 gpdelay = reg_needs_delay (mips_gp_register);
7421 if (expr1.X_add_number == 0 && breg == 0
7422 && (call || tempreg == PIC_CALL_REG))
7424 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
7425 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
7427 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
7428 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7429 tempreg, tempreg, mips_gp_register);
7430 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7431 tempreg, lw_reloc_type, tempreg);
7432 if (expr1.X_add_number == 0)
7436 /* We're going to put in an addu instruction using
7437 tempreg, so we may as well insert the nop right
7442 else if (expr1.X_add_number >= -0x8000
7443 && expr1.X_add_number < 0x8000)
7446 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7447 tempreg, tempreg, BFD_RELOC_LO16);
7451 /* If we are going to add in a base register, and the
7452 target register and the base register are the same,
7453 then we are using AT as a temporary register. Since
7454 we want to load the constant into AT, we add our
7455 current AT (from the global offset table) and the
7456 register into the register now, and pretend we were
7457 not using a base register. */
7462 gas_assert (tempreg == AT);
7464 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7469 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7470 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
7474 offset_expr.X_add_number =
7475 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000;
7480 /* This is needed because this instruction uses $gp, but
7481 the first instruction on the main stream does not. */
7482 macro_build (NULL, "nop", "");
7485 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7486 local_reloc_type, mips_gp_register);
7487 if (expr1.X_add_number >= -0x8000
7488 && expr1.X_add_number < 0x8000)
7491 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7492 tempreg, tempreg, BFD_RELOC_LO16);
7493 /* FIXME: If add_number is 0, and there was no base
7494 register, the external symbol case ended with a load,
7495 so if the symbol turns out to not be external, and
7496 the next instruction uses tempreg, an unnecessary nop
7497 will be inserted. */
7503 /* We must add in the base register now, as in the
7504 external symbol case. */
7505 gas_assert (tempreg == AT);
7507 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7510 /* We set breg to 0 because we have arranged to add
7511 it in in both cases. */
7515 macro_build_lui (&expr1, AT);
7516 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7517 AT, AT, BFD_RELOC_LO16);
7518 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7519 tempreg, tempreg, AT);
7524 else if (mips_big_got && HAVE_NEWABI)
7526 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
7527 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
7528 int add_breg_early = 0;
7530 /* This is the large GOT case. If this is a reference to an
7531 external symbol, and there is no constant, we want
7532 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7533 add $tempreg,$tempreg,$gp
7534 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7535 or for lca or if tempreg is PIC_CALL_REG
7536 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7537 add $tempreg,$tempreg,$gp
7538 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7540 If we have a small constant, and this is a reference to
7541 an external symbol, we want
7542 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7543 add $tempreg,$tempreg,$gp
7544 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7545 addi $tempreg,$tempreg,<constant>
7547 If we have a large constant, and this is a reference to
7548 an external symbol, we want
7549 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7550 addu $tempreg,$tempreg,$gp
7551 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7552 lui $at,<hiconstant>
7553 addi $at,$at,<loconstant>
7554 add $tempreg,$tempreg,$at
7556 If we have NewABI, and we know it's a local symbol, we want
7557 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7558 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
7559 otherwise we have to resort to GOT_HI16/GOT_LO16. */
7561 relax_start (offset_expr.X_add_symbol);
7563 expr1.X_add_number = offset_expr.X_add_number;
7564 offset_expr.X_add_number = 0;
7566 if (expr1.X_add_number == 0 && breg == 0
7567 && (call || tempreg == PIC_CALL_REG))
7569 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
7570 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
7572 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
7573 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7574 tempreg, tempreg, mips_gp_register);
7575 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7576 tempreg, lw_reloc_type, tempreg);
7578 if (expr1.X_add_number == 0)
7580 else if (expr1.X_add_number >= -0x8000
7581 && expr1.X_add_number < 0x8000)
7583 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7584 tempreg, tempreg, BFD_RELOC_LO16);
7586 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
7588 /* If we are going to add in a base register, and the
7589 target register and the base register are the same,
7590 then we are using AT as a temporary register. Since
7591 we want to load the constant into AT, we add our
7592 current AT (from the global offset table) and the
7593 register into the register now, and pretend we were
7594 not using a base register. */
7599 gas_assert (tempreg == AT);
7600 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7606 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7607 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
7612 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7615 offset_expr.X_add_number = expr1.X_add_number;
7616 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7617 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
7618 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
7619 tempreg, BFD_RELOC_MIPS_GOT_OFST);
7622 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7623 treg, tempreg, breg);
7633 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
7637 gas_assert (!mips_opts.micromips);
7639 unsigned long temp = (treg << 16) | (0x01);
7640 macro_build (NULL, "c2", "C", temp);
7645 gas_assert (!mips_opts.micromips);
7647 unsigned long temp = (0x02);
7648 macro_build (NULL, "c2", "C", temp);
7653 gas_assert (!mips_opts.micromips);
7655 unsigned long temp = (treg << 16) | (0x02);
7656 macro_build (NULL, "c2", "C", temp);
7661 gas_assert (!mips_opts.micromips);
7662 macro_build (NULL, "c2", "C", 3);
7666 gas_assert (!mips_opts.micromips);
7668 unsigned long temp = (treg << 16) | 0x03;
7669 macro_build (NULL, "c2", "C", temp);
7674 /* The j instruction may not be used in PIC code, since it
7675 requires an absolute address. We convert it to a b
7677 if (mips_pic == NO_PIC)
7678 macro_build (&offset_expr, "j", "a");
7680 macro_build (&offset_expr, "b", "p");
7683 /* The jal instructions must be handled as macros because when
7684 generating PIC code they expand to multi-instruction
7685 sequences. Normally they are simple instructions. */
7690 gas_assert (mips_opts.micromips);
7698 if (mips_pic == NO_PIC)
7700 s = jals ? "jalrs" : "jalr";
7701 if (mips_opts.micromips && dreg == RA)
7702 macro_build (NULL, s, "mj", sreg);
7704 macro_build (NULL, s, JALR_FMT, dreg, sreg);
7708 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
7709 && mips_cprestore_offset >= 0);
7711 if (sreg != PIC_CALL_REG)
7712 as_warn (_("MIPS PIC call to register other than $25"));
7714 s = (mips_opts.micromips && (!mips_opts.noreorder || cprestore)
7715 ? "jalrs" : "jalr");
7716 if (mips_opts.micromips && dreg == RA)
7717 macro_build (NULL, s, "mj", sreg);
7719 macro_build (NULL, s, JALR_FMT, dreg, sreg);
7720 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
7722 if (mips_cprestore_offset < 0)
7723 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7726 if (!mips_frame_reg_valid)
7728 as_warn (_("No .frame pseudo-op used in PIC code"));
7729 /* Quiet this warning. */
7730 mips_frame_reg_valid = 1;
7732 if (!mips_cprestore_valid)
7734 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7735 /* Quiet this warning. */
7736 mips_cprestore_valid = 1;
7738 if (mips_opts.noreorder)
7739 macro_build (NULL, "nop", "");
7740 expr1.X_add_number = mips_cprestore_offset;
7741 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
7744 HAVE_64BIT_ADDRESSES);
7752 gas_assert (mips_opts.micromips);
7756 if (mips_pic == NO_PIC)
7757 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
7758 else if (mips_pic == SVR4_PIC)
7760 /* If this is a reference to an external symbol, and we are
7761 using a small GOT, we want
7762 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7766 lw $gp,cprestore($sp)
7767 The cprestore value is set using the .cprestore
7768 pseudo-op. If we are using a big GOT, we want
7769 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7771 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
7775 lw $gp,cprestore($sp)
7776 If the symbol is not external, we want
7777 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7779 addiu $25,$25,<sym> (BFD_RELOC_LO16)
7782 lw $gp,cprestore($sp)
7784 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
7785 sequences above, minus nops, unless the symbol is local,
7786 which enables us to use GOT_PAGE/GOT_OFST (big got) or
7792 relax_start (offset_expr.X_add_symbol);
7793 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7794 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
7797 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7798 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
7804 relax_start (offset_expr.X_add_symbol);
7805 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
7806 BFD_RELOC_MIPS_CALL_HI16);
7807 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
7808 PIC_CALL_REG, mips_gp_register);
7809 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7810 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
7813 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7814 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
7816 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7817 PIC_CALL_REG, PIC_CALL_REG,
7818 BFD_RELOC_MIPS_GOT_OFST);
7822 macro_build_jalr (&offset_expr, 0);
7826 relax_start (offset_expr.X_add_symbol);
7829 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7830 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
7839 gpdelay = reg_needs_delay (mips_gp_register);
7840 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
7841 BFD_RELOC_MIPS_CALL_HI16);
7842 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
7843 PIC_CALL_REG, mips_gp_register);
7844 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7845 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
7850 macro_build (NULL, "nop", "");
7852 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7853 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
7856 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7857 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
7859 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
7861 if (mips_cprestore_offset < 0)
7862 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7865 if (!mips_frame_reg_valid)
7867 as_warn (_("No .frame pseudo-op used in PIC code"));
7868 /* Quiet this warning. */
7869 mips_frame_reg_valid = 1;
7871 if (!mips_cprestore_valid)
7873 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7874 /* Quiet this warning. */
7875 mips_cprestore_valid = 1;
7877 if (mips_opts.noreorder)
7878 macro_build (NULL, "nop", "");
7879 expr1.X_add_number = mips_cprestore_offset;
7880 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
7883 HAVE_64BIT_ADDRESSES);
7887 else if (mips_pic == VXWORKS_PIC)
7888 as_bad (_("Non-PIC jump used in PIC library"));
7898 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
7906 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
7937 gas_assert (!mips_opts.micromips);
7940 /* Itbl support may require additional care here. */
7947 /* Itbl support may require additional care here. */
7955 off12 = mips_opts.micromips;
7956 /* Itbl support may require additional care here. */
7961 gas_assert (!mips_opts.micromips);
7964 /* Itbl support may require additional care here. */
7972 off12 = mips_opts.micromips;
7979 off12 = mips_opts.micromips;
7985 /* Itbl support may require additional care here. */
7993 off12 = mips_opts.micromips;
7994 /* Itbl support may require additional care here. */
8001 /* Itbl support may require additional care here. */
8009 off12 = mips_opts.micromips;
8016 off12 = mips_opts.micromips;
8023 off12 = mips_opts.micromips;
8030 off12 = mips_opts.micromips;
8037 off12 = mips_opts.micromips;
8042 gas_assert (mips_opts.micromips);
8051 gas_assert (mips_opts.micromips);
8060 gas_assert (mips_opts.micromips);
8068 gas_assert (mips_opts.micromips);
8075 if (breg == treg + lp)
8078 tempreg = treg + lp;
8098 gas_assert (!mips_opts.micromips);
8101 /* Itbl support may require additional care here. */
8108 /* Itbl support may require additional care here. */
8116 off12 = mips_opts.micromips;
8117 /* Itbl support may require additional care here. */
8122 gas_assert (!mips_opts.micromips);
8125 /* Itbl support may require additional care here. */
8133 off12 = mips_opts.micromips;
8140 off12 = mips_opts.micromips;
8147 off12 = mips_opts.micromips;
8154 off12 = mips_opts.micromips;
8160 fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)";
8161 off12 = mips_opts.micromips;
8167 fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)";
8168 off12 = mips_opts.micromips;
8175 /* Itbl support may require additional care here. */
8182 off12 = mips_opts.micromips;
8183 /* Itbl support may require additional care here. */
8188 gas_assert (!mips_opts.micromips);
8191 /* Itbl support may require additional care here. */
8199 off12 = mips_opts.micromips;
8206 off12 = mips_opts.micromips;
8211 gas_assert (mips_opts.micromips);
8219 gas_assert (mips_opts.micromips);
8227 gas_assert (mips_opts.micromips);
8235 gas_assert (mips_opts.micromips);
8245 && NO_ISA_COP (mips_opts.arch)
8246 && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0)
8248 as_bad (_("Opcode not supported on this processor: %s"),
8249 mips_cpu_info_from_arch (mips_opts.arch)->name);
8253 if (offset_expr.X_op != O_constant
8254 && offset_expr.X_op != O_symbol)
8256 as_bad (_("Expression too complex"));
8257 offset_expr.X_op = O_constant;
8260 if (HAVE_32BIT_ADDRESSES
8261 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
8265 sprintf_vma (value, offset_expr.X_add_number);
8266 as_bad (_("Number (0x%s) larger than 32 bits"), value);
8269 /* A constant expression in PIC code can be handled just as it
8270 is in non PIC code. */
8271 if (offset_expr.X_op == O_constant)
8275 expr1.X_add_number = offset_expr.X_add_number;
8276 normalize_address_expr (&expr1);
8277 if (!off12 && !IS_SEXT_16BIT_NUM (expr1.X_add_number))
8279 expr1.X_add_number = ((expr1.X_add_number + 0x8000)
8280 & ~(bfd_vma) 0xffff);
8283 else if (off12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number))
8285 expr1.X_add_number = ((expr1.X_add_number + 0x800)
8286 & ~(bfd_vma) 0xfff);
8291 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
8293 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8294 tempreg, tempreg, breg);
8298 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg);
8300 macro_build (NULL, s, fmt,
8301 treg, (unsigned long) offset_expr.X_add_number, breg);
8305 /* A 12-bit offset field is too narrow to be used for a low-part
8306 relocation, so load the whole address into the auxillary
8307 register. In the case of "A(b)" addresses, we first load
8308 absolute address "A" into the register and then add base
8309 register "b". In the case of "o(b)" addresses, we simply
8310 need to add 16-bit offset "o" to base register "b", and
8311 offset_reloc already contains the relocations associated
8315 load_address (tempreg, &offset_expr, &used_at);
8317 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8318 tempreg, tempreg, breg);
8321 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8323 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
8324 expr1.X_add_number = 0;
8325 macro_build (NULL, s, fmt,
8326 treg, (unsigned long) expr1.X_add_number, tempreg);
8328 else if (mips_pic == NO_PIC)
8330 /* If this is a reference to a GP relative symbol, and there
8331 is no base register, we want
8332 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8333 Otherwise, if there is no base register, we want
8334 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8335 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8336 If we have a constant, we need two instructions anyhow,
8337 so we always use the latter form.
8339 If we have a base register, and this is a reference to a
8340 GP relative symbol, we want
8341 addu $tempreg,$breg,$gp
8342 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
8344 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8345 addu $tempreg,$tempreg,$breg
8346 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8347 With a constant we always use the latter case.
8349 With 64bit address space and no base register and $at usable,
8351 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8352 lui $at,<sym> (BFD_RELOC_HI16_S)
8353 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8356 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8357 If we have a base register, we want
8358 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8359 lui $at,<sym> (BFD_RELOC_HI16_S)
8360 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8364 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8366 Without $at we can't generate the optimal path for superscalar
8367 processors here since this would require two temporary registers.
8368 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8369 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8371 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8373 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8374 If we have a base register, we want
8375 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8376 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8378 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8380 daddu $tempreg,$tempreg,$breg
8381 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8383 For GP relative symbols in 64bit address space we can use
8384 the same sequence as in 32bit address space. */
8385 if (HAVE_64BIT_SYMBOLS)
8387 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8388 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8390 relax_start (offset_expr.X_add_symbol);
8393 macro_build (&offset_expr, s, fmt, treg,
8394 BFD_RELOC_GPREL16, mips_gp_register);
8398 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8399 tempreg, breg, mips_gp_register);
8400 macro_build (&offset_expr, s, fmt, treg,
8401 BFD_RELOC_GPREL16, tempreg);
8406 if (used_at == 0 && mips_opts.at)
8408 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8409 BFD_RELOC_MIPS_HIGHEST);
8410 macro_build (&offset_expr, "lui", LUI_FMT, AT,
8412 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8413 tempreg, BFD_RELOC_MIPS_HIGHER);
8415 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
8416 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
8417 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
8418 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
8424 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8425 BFD_RELOC_MIPS_HIGHEST);
8426 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8427 tempreg, BFD_RELOC_MIPS_HIGHER);
8428 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
8429 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8430 tempreg, BFD_RELOC_HI16_S);
8431 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
8433 macro_build (NULL, "daddu", "d,v,t",
8434 tempreg, tempreg, breg);
8435 macro_build (&offset_expr, s, fmt, treg,
8436 BFD_RELOC_LO16, tempreg);
8439 if (mips_relax.sequence)
8446 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8447 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8449 relax_start (offset_expr.X_add_symbol);
8450 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
8454 macro_build_lui (&offset_expr, tempreg);
8455 macro_build (&offset_expr, s, fmt, treg,
8456 BFD_RELOC_LO16, tempreg);
8457 if (mips_relax.sequence)
8462 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8463 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8465 relax_start (offset_expr.X_add_symbol);
8466 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8467 tempreg, breg, mips_gp_register);
8468 macro_build (&offset_expr, s, fmt, treg,
8469 BFD_RELOC_GPREL16, tempreg);
8472 macro_build_lui (&offset_expr, tempreg);
8473 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8474 tempreg, tempreg, breg);
8475 macro_build (&offset_expr, s, fmt, treg,
8476 BFD_RELOC_LO16, tempreg);
8477 if (mips_relax.sequence)
8481 else if (!mips_big_got)
8483 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
8485 /* If this is a reference to an external symbol, we want
8486 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8488 <op> $treg,0($tempreg)
8490 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8492 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8493 <op> $treg,0($tempreg)
8496 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8497 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
8499 If there is a base register, we add it to $tempreg before
8500 the <op>. If there is a constant, we stick it in the
8501 <op> instruction. We don't handle constants larger than
8502 16 bits, because we have no way to load the upper 16 bits
8503 (actually, we could handle them for the subset of cases
8504 in which we are not using $at). */
8505 gas_assert (offset_expr.X_op == O_symbol);
8508 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8509 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8511 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8512 tempreg, tempreg, breg);
8513 macro_build (&offset_expr, s, fmt, treg,
8514 BFD_RELOC_MIPS_GOT_OFST, tempreg);
8517 expr1.X_add_number = offset_expr.X_add_number;
8518 offset_expr.X_add_number = 0;
8519 if (expr1.X_add_number < -0x8000
8520 || expr1.X_add_number >= 0x8000)
8521 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8522 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8523 lw_reloc_type, mips_gp_register);
8525 relax_start (offset_expr.X_add_symbol);
8527 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
8528 tempreg, BFD_RELOC_LO16);
8531 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8532 tempreg, tempreg, breg);
8533 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8535 else if (mips_big_got && !HAVE_NEWABI)
8539 /* If this is a reference to an external symbol, we want
8540 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8541 addu $tempreg,$tempreg,$gp
8542 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8543 <op> $treg,0($tempreg)
8545 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8547 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8548 <op> $treg,0($tempreg)
8549 If there is a base register, we add it to $tempreg before
8550 the <op>. If there is a constant, we stick it in the
8551 <op> instruction. We don't handle constants larger than
8552 16 bits, because we have no way to load the upper 16 bits
8553 (actually, we could handle them for the subset of cases
8554 in which we are not using $at). */
8555 gas_assert (offset_expr.X_op == O_symbol);
8556 expr1.X_add_number = offset_expr.X_add_number;
8557 offset_expr.X_add_number = 0;
8558 if (expr1.X_add_number < -0x8000
8559 || expr1.X_add_number >= 0x8000)
8560 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8561 gpdelay = reg_needs_delay (mips_gp_register);
8562 relax_start (offset_expr.X_add_symbol);
8563 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8564 BFD_RELOC_MIPS_GOT_HI16);
8565 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
8567 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8568 BFD_RELOC_MIPS_GOT_LO16, tempreg);
8571 macro_build (NULL, "nop", "");
8572 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8573 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8575 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
8576 tempreg, BFD_RELOC_LO16);
8580 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8581 tempreg, tempreg, breg);
8582 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8584 else if (mips_big_got && HAVE_NEWABI)
8586 /* If this is a reference to an external symbol, we want
8587 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8588 add $tempreg,$tempreg,$gp
8589 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8590 <op> $treg,<ofst>($tempreg)
8591 Otherwise, for local symbols, we want:
8592 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8593 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
8594 gas_assert (offset_expr.X_op == O_symbol);
8595 expr1.X_add_number = offset_expr.X_add_number;
8596 offset_expr.X_add_number = 0;
8597 if (expr1.X_add_number < -0x8000
8598 || expr1.X_add_number >= 0x8000)
8599 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8600 relax_start (offset_expr.X_add_symbol);
8601 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8602 BFD_RELOC_MIPS_GOT_HI16);
8603 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
8605 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8606 BFD_RELOC_MIPS_GOT_LO16, tempreg);
8608 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8609 tempreg, tempreg, breg);
8610 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8613 offset_expr.X_add_number = expr1.X_add_number;
8614 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8615 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8617 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8618 tempreg, tempreg, breg);
8619 macro_build (&offset_expr, s, fmt, treg,
8620 BFD_RELOC_MIPS_GOT_OFST, tempreg);
8630 load_register (treg, &imm_expr, 0);
8634 load_register (treg, &imm_expr, 1);
8638 if (imm_expr.X_op == O_constant)
8641 load_register (AT, &imm_expr, 0);
8642 macro_build (NULL, "mtc1", "t,G", AT, treg);
8647 gas_assert (offset_expr.X_op == O_symbol
8648 && strcmp (segment_name (S_GET_SEGMENT
8649 (offset_expr.X_add_symbol)),
8651 && offset_expr.X_add_number == 0);
8652 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
8653 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
8658 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
8659 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
8660 order 32 bits of the value and the low order 32 bits are either
8661 zero or in OFFSET_EXPR. */
8662 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
8664 if (HAVE_64BIT_GPRS)
8665 load_register (treg, &imm_expr, 1);
8670 if (target_big_endian)
8682 load_register (hreg, &imm_expr, 0);
8685 if (offset_expr.X_op == O_absent)
8686 move_register (lreg, 0);
8689 gas_assert (offset_expr.X_op == O_constant);
8690 load_register (lreg, &offset_expr, 0);
8697 /* We know that sym is in the .rdata section. First we get the
8698 upper 16 bits of the address. */
8699 if (mips_pic == NO_PIC)
8701 macro_build_lui (&offset_expr, AT);
8706 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
8707 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8711 /* Now we load the register(s). */
8712 if (HAVE_64BIT_GPRS)
8715 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8720 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8723 /* FIXME: How in the world do we deal with the possible
8725 offset_expr.X_add_number += 4;
8726 macro_build (&offset_expr, "lw", "t,o(b)",
8727 treg + 1, BFD_RELOC_LO16, AT);
8733 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
8734 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
8735 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
8736 the value and the low order 32 bits are either zero or in
8738 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
8741 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
8742 if (HAVE_64BIT_FPRS)
8744 gas_assert (HAVE_64BIT_GPRS);
8745 macro_build (NULL, "dmtc1", "t,S", AT, treg);
8749 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
8750 if (offset_expr.X_op == O_absent)
8751 macro_build (NULL, "mtc1", "t,G", 0, treg);
8754 gas_assert (offset_expr.X_op == O_constant);
8755 load_register (AT, &offset_expr, 0);
8756 macro_build (NULL, "mtc1", "t,G", AT, treg);
8762 gas_assert (offset_expr.X_op == O_symbol
8763 && offset_expr.X_add_number == 0);
8764 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
8765 if (strcmp (s, ".lit8") == 0)
8767 if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips)
8769 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
8770 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
8773 breg = mips_gp_register;
8774 r = BFD_RELOC_MIPS_LITERAL;
8779 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
8781 if (mips_pic != NO_PIC)
8782 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
8783 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8786 /* FIXME: This won't work for a 64 bit address. */
8787 macro_build_lui (&offset_expr, AT);
8790 if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips)
8792 macro_build (&offset_expr, "ldc1", "T,o(b)",
8793 treg, BFD_RELOC_LO16, AT);
8802 /* Even on a big endian machine $fn comes before $fn+1. We have
8803 to adjust when loading from memory. */
8806 gas_assert (!mips_opts.micromips);
8807 gas_assert (mips_opts.isa == ISA_MIPS1);
8808 macro_build (&offset_expr, "lwc1", "T,o(b)",
8809 target_big_endian ? treg + 1 : treg, r, breg);
8810 /* FIXME: A possible overflow which I don't know how to deal
8812 offset_expr.X_add_number += 4;
8813 macro_build (&offset_expr, "lwc1", "T,o(b)",
8814 target_big_endian ? treg : treg + 1, r, breg);
8818 gas_assert (!mips_opts.micromips);
8819 gas_assert (mips_opts.isa == ISA_MIPS1);
8820 /* Even on a big endian machine $fn comes before $fn+1. We have
8821 to adjust when storing to memory. */
8822 macro_build (&offset_expr, "swc1", "T,o(b)",
8823 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
8824 offset_expr.X_add_number += 4;
8825 macro_build (&offset_expr, "swc1", "T,o(b)",
8826 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
8830 gas_assert (!mips_opts.micromips);
8832 * The MIPS assembler seems to check for X_add_number not
8833 * being double aligned and generating:
8836 * addiu at,at,%lo(foo+1)
8839 * But, the resulting address is the same after relocation so why
8840 * generate the extra instruction?
8842 /* Itbl support may require additional care here. */
8845 if (mips_opts.isa != ISA_MIPS1)
8854 gas_assert (!mips_opts.micromips);
8855 /* Itbl support may require additional care here. */
8858 if (mips_opts.isa != ISA_MIPS1)
8868 if (HAVE_64BIT_GPRS)
8878 if (HAVE_64BIT_GPRS)
8886 if (offset_expr.X_op != O_symbol
8887 && offset_expr.X_op != O_constant)
8889 as_bad (_("Expression too complex"));
8890 offset_expr.X_op = O_constant;
8893 if (HAVE_32BIT_ADDRESSES
8894 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
8898 sprintf_vma (value, offset_expr.X_add_number);
8899 as_bad (_("Number (0x%s) larger than 32 bits"), value);
8902 /* Even on a big endian machine $fn comes before $fn+1. We have
8903 to adjust when loading from memory. We set coproc if we must
8904 load $fn+1 first. */
8905 /* Itbl support may require additional care here. */
8906 if (!target_big_endian)
8909 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
8911 /* If this is a reference to a GP relative symbol, we want
8912 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8913 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
8914 If we have a base register, we use this
8916 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
8917 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
8918 If this is not a GP relative symbol, we want
8919 lui $at,<sym> (BFD_RELOC_HI16_S)
8920 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
8921 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
8922 If there is a base register, we add it to $at after the
8923 lui instruction. If there is a constant, we always use
8925 if (offset_expr.X_op == O_symbol
8926 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8927 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8929 relax_start (offset_expr.X_add_symbol);
8932 tempreg = mips_gp_register;
8936 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8937 AT, breg, mips_gp_register);
8942 /* Itbl support may require additional care here. */
8943 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
8944 BFD_RELOC_GPREL16, tempreg);
8945 offset_expr.X_add_number += 4;
8947 /* Set mips_optimize to 2 to avoid inserting an
8949 hold_mips_optimize = mips_optimize;
8951 /* Itbl support may require additional care here. */
8952 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
8953 BFD_RELOC_GPREL16, tempreg);
8954 mips_optimize = hold_mips_optimize;
8958 offset_expr.X_add_number -= 4;
8961 macro_build_lui (&offset_expr, AT);
8963 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
8964 /* Itbl support may require additional care here. */
8965 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
8966 BFD_RELOC_LO16, AT);
8967 /* FIXME: How do we handle overflow here? */
8968 offset_expr.X_add_number += 4;
8969 /* Itbl support may require additional care here. */
8970 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
8971 BFD_RELOC_LO16, AT);
8972 if (mips_relax.sequence)
8975 else if (!mips_big_got)
8977 /* If this is a reference to an external symbol, we want
8978 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8983 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8985 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
8986 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
8987 If there is a base register we add it to $at before the
8988 lwc1 instructions. If there is a constant we include it
8989 in the lwc1 instructions. */
8991 expr1.X_add_number = offset_expr.X_add_number;
8992 if (expr1.X_add_number < -0x8000
8993 || expr1.X_add_number >= 0x8000 - 4)
8994 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8995 load_got_offset (AT, &offset_expr);
8998 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9000 /* Set mips_optimize to 2 to avoid inserting an undesired
9002 hold_mips_optimize = mips_optimize;
9005 /* Itbl support may require additional care here. */
9006 relax_start (offset_expr.X_add_symbol);
9007 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9008 BFD_RELOC_LO16, AT);
9009 expr1.X_add_number += 4;
9010 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9011 BFD_RELOC_LO16, AT);
9013 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9014 BFD_RELOC_LO16, AT);
9015 offset_expr.X_add_number += 4;
9016 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9017 BFD_RELOC_LO16, AT);
9020 mips_optimize = hold_mips_optimize;
9022 else if (mips_big_got)
9026 /* If this is a reference to an external symbol, we want
9027 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9029 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
9034 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9036 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9037 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9038 If there is a base register we add it to $at before the
9039 lwc1 instructions. If there is a constant we include it
9040 in the lwc1 instructions. */
9042 expr1.X_add_number = offset_expr.X_add_number;
9043 offset_expr.X_add_number = 0;
9044 if (expr1.X_add_number < -0x8000
9045 || expr1.X_add_number >= 0x8000 - 4)
9046 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9047 gpdelay = reg_needs_delay (mips_gp_register);
9048 relax_start (offset_expr.X_add_symbol);
9049 macro_build (&offset_expr, "lui", LUI_FMT,
9050 AT, BFD_RELOC_MIPS_GOT_HI16);
9051 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9052 AT, AT, mips_gp_register);
9053 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9054 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
9057 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9058 /* Itbl support may require additional care here. */
9059 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9060 BFD_RELOC_LO16, AT);
9061 expr1.X_add_number += 4;
9063 /* Set mips_optimize to 2 to avoid inserting an undesired
9065 hold_mips_optimize = mips_optimize;
9067 /* Itbl support may require additional care here. */
9068 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9069 BFD_RELOC_LO16, AT);
9070 mips_optimize = hold_mips_optimize;
9071 expr1.X_add_number -= 4;
9074 offset_expr.X_add_number = expr1.X_add_number;
9076 macro_build (NULL, "nop", "");
9077 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
9078 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9081 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9082 /* Itbl support may require additional care here. */
9083 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9084 BFD_RELOC_LO16, AT);
9085 offset_expr.X_add_number += 4;
9087 /* Set mips_optimize to 2 to avoid inserting an undesired
9089 hold_mips_optimize = mips_optimize;
9091 /* Itbl support may require additional care here. */
9092 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9093 BFD_RELOC_LO16, AT);
9094 mips_optimize = hold_mips_optimize;
9103 s = HAVE_64BIT_GPRS ? "ld" : "lw";
9106 s = HAVE_64BIT_GPRS ? "sd" : "sw";
9108 macro_build (&offset_expr, s, "t,o(b)", treg,
9109 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
9111 if (!HAVE_64BIT_GPRS)
9113 offset_expr.X_add_number += 4;
9114 macro_build (&offset_expr, s, "t,o(b)", treg + 1,
9115 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
9120 /* New code added to support COPZ instructions.
9121 This code builds table entries out of the macros in mip_opcodes.
9122 R4000 uses interlocks to handle coproc delays.
9123 Other chips (like the R3000) require nops to be inserted for delays.
9125 FIXME: Currently, we require that the user handle delays.
9126 In order to fill delay slots for non-interlocked chips,
9127 we must have a way to specify delays based on the coprocessor.
9128 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
9129 What are the side-effects of the cop instruction?
9130 What cache support might we have and what are its effects?
9131 Both coprocessor & memory require delays. how long???
9132 What registers are read/set/modified?
9134 If an itbl is provided to interpret cop instructions,
9135 this knowledge can be encoded in the itbl spec. */
9149 gas_assert (!mips_opts.micromips);
9150 if (NO_ISA_COP (mips_opts.arch)
9151 && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0)
9153 as_bad (_("opcode not supported on this processor: %s"),
9154 mips_cpu_info_from_arch (mips_opts.arch)->name);
9158 /* For now we just do C (same as Cz). The parameter will be
9159 stored in insn_opcode by mips_ip. */
9160 macro_build (NULL, s, "C", ip->insn_opcode);
9164 move_register (dreg, sreg);
9170 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
9171 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9177 /* The MIPS assembler some times generates shifts and adds. I'm
9178 not trying to be that fancy. GCC should do this for us
9181 load_register (AT, &imm_expr, dbl);
9182 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
9183 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9199 load_register (AT, &imm_expr, dbl);
9200 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
9201 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9202 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA);
9203 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9205 macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6);
9208 if (mips_opts.micromips)
9209 micromips_label_expr (&label_expr);
9211 label_expr.X_add_number = 8;
9212 macro_build (&label_expr, "beq", "s,t,p", dreg, AT);
9213 macro_build (NULL, "nop", "");
9214 macro_build (NULL, "break", BRK_FMT, 6);
9215 if (mips_opts.micromips)
9216 micromips_add_label ();
9219 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9235 load_register (AT, &imm_expr, dbl);
9236 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
9237 sreg, imm ? AT : treg);
9238 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9239 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9241 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
9244 if (mips_opts.micromips)
9245 micromips_label_expr (&label_expr);
9247 label_expr.X_add_number = 8;
9248 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
9249 macro_build (NULL, "nop", "");
9250 macro_build (NULL, "break", BRK_FMT, 6);
9251 if (mips_opts.micromips)
9252 micromips_add_label ();
9258 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9269 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
9270 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
9274 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9275 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
9276 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
9277 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9281 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9292 macro_build (NULL, "negu", "d,w", tempreg, treg);
9293 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
9297 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
9298 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
9299 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
9300 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9309 if (imm_expr.X_op != O_constant)
9310 as_bad (_("Improper rotate count"));
9311 rot = imm_expr.X_add_number & 0x3f;
9312 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9314 rot = (64 - rot) & 0x3f;
9316 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
9318 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
9323 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
9326 l = (rot < 0x20) ? "dsll" : "dsll32";
9327 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
9330 macro_build (NULL, l, SHFT_FMT, AT, sreg, rot);
9331 macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9332 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9340 if (imm_expr.X_op != O_constant)
9341 as_bad (_("Improper rotate count"));
9342 rot = imm_expr.X_add_number & 0x1f;
9343 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9345 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f);
9350 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
9354 macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot);
9355 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9356 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9361 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9363 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
9367 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9368 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
9369 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
9370 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9374 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9376 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
9380 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
9381 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
9382 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
9383 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9392 if (imm_expr.X_op != O_constant)
9393 as_bad (_("Improper rotate count"));
9394 rot = imm_expr.X_add_number & 0x3f;
9395 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9398 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
9400 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
9405 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
9408 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
9409 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
9412 macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot);
9413 macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9414 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9422 if (imm_expr.X_op != O_constant)
9423 as_bad (_("Improper rotate count"));
9424 rot = imm_expr.X_add_number & 0x1f;
9425 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9427 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot);
9432 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
9436 macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot);
9437 macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9438 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9444 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
9446 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9449 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
9450 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
9455 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9457 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9462 as_warn (_("Instruction %s: result is always false"),
9464 move_register (dreg, 0);
9467 if (CPU_HAS_SEQ (mips_opts.arch)
9468 && -512 <= imm_expr.X_add_number
9469 && imm_expr.X_add_number < 512)
9471 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
9472 (int) imm_expr.X_add_number);
9475 if (imm_expr.X_op == O_constant
9476 && imm_expr.X_add_number >= 0
9477 && imm_expr.X_add_number < 0x10000)
9479 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
9481 else if (imm_expr.X_op == O_constant
9482 && imm_expr.X_add_number > -0x8000
9483 && imm_expr.X_add_number < 0)
9485 imm_expr.X_add_number = -imm_expr.X_add_number;
9486 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
9487 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9489 else if (CPU_HAS_SEQ (mips_opts.arch))
9492 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9493 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
9498 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9499 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
9502 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
9505 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
9511 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
9512 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9515 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
9517 if (imm_expr.X_op == O_constant
9518 && imm_expr.X_add_number >= -0x8000
9519 && imm_expr.X_add_number < 0x8000)
9521 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
9522 dreg, sreg, BFD_RELOC_LO16);
9526 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9527 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
9531 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9534 case M_SGT: /* sreg > treg <==> treg < sreg */
9540 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
9543 case M_SGT_I: /* sreg > I <==> I < sreg */
9550 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9551 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
9554 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
9560 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
9561 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9564 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
9571 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9572 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
9573 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9577 if (imm_expr.X_op == O_constant
9578 && imm_expr.X_add_number >= -0x8000
9579 && imm_expr.X_add_number < 0x8000)
9581 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9585 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9586 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
9590 if (imm_expr.X_op == O_constant
9591 && imm_expr.X_add_number >= -0x8000
9592 && imm_expr.X_add_number < 0x8000)
9594 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
9599 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9600 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
9605 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
9607 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
9610 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
9611 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
9616 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9618 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
9623 as_warn (_("Instruction %s: result is always true"),
9625 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
9626 dreg, 0, BFD_RELOC_LO16);
9629 if (CPU_HAS_SEQ (mips_opts.arch)
9630 && -512 <= imm_expr.X_add_number
9631 && imm_expr.X_add_number < 512)
9633 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
9634 (int) imm_expr.X_add_number);
9637 if (imm_expr.X_op == O_constant
9638 && imm_expr.X_add_number >= 0
9639 && imm_expr.X_add_number < 0x10000)
9641 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
9643 else if (imm_expr.X_op == O_constant
9644 && imm_expr.X_add_number > -0x8000
9645 && imm_expr.X_add_number < 0)
9647 imm_expr.X_add_number = -imm_expr.X_add_number;
9648 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
9649 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9651 else if (CPU_HAS_SEQ (mips_opts.arch))
9654 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9655 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
9660 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9661 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
9664 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
9679 if (!mips_opts.micromips)
9681 if (imm_expr.X_op == O_constant
9682 && imm_expr.X_add_number > -0x200
9683 && imm_expr.X_add_number <= 0x200)
9685 macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number);
9694 if (imm_expr.X_op == O_constant
9695 && imm_expr.X_add_number > -0x8000
9696 && imm_expr.X_add_number <= 0x8000)
9698 imm_expr.X_add_number = -imm_expr.X_add_number;
9699 macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9704 load_register (AT, &imm_expr, dbl);
9705 macro_build (NULL, s2, "d,v,t", dreg, sreg, AT);
9727 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9728 macro_build (NULL, s, "s,t", sreg, AT);
9733 gas_assert (!mips_opts.micromips);
9734 gas_assert (mips_opts.isa == ISA_MIPS1);
9736 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
9737 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
9740 * Is the double cfc1 instruction a bug in the mips assembler;
9741 * or is there a reason for it?
9744 macro_build (NULL, "cfc1", "t,G", treg, RA);
9745 macro_build (NULL, "cfc1", "t,G", treg, RA);
9746 macro_build (NULL, "nop", "");
9747 expr1.X_add_number = 3;
9748 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
9749 expr1.X_add_number = 2;
9750 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
9751 macro_build (NULL, "ctc1", "t,G", AT, RA);
9752 macro_build (NULL, "nop", "");
9753 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
9755 macro_build (NULL, "ctc1", "t,G", treg, RA);
9756 macro_build (NULL, "nop", "");
9779 off12 = mips_opts.micromips;
9787 off12 = mips_opts.micromips;
9803 off12 = mips_opts.micromips;
9812 off12 = mips_opts.micromips;
9817 if (!ab && offset_expr.X_add_number >= 0x8000 - off)
9818 as_bad (_("Operand overflow"));
9821 expr1.X_add_number = 0;
9826 load_address (tempreg, ep, &used_at);
9828 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9829 tempreg, tempreg, breg);
9835 && (offset_expr.X_op != O_constant
9836 || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number)
9837 || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number + off)))
9841 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg,
9842 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
9847 else if (!ust && treg == breg)
9858 if (!target_big_endian)
9859 ep->X_add_number += off;
9861 macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
9863 macro_build (NULL, s, "t,~(b)",
9864 tempreg, (unsigned long) ep->X_add_number, breg);
9866 if (!target_big_endian)
9867 ep->X_add_number -= off;
9869 ep->X_add_number += off;
9871 macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
9873 macro_build (NULL, s2, "t,~(b)",
9874 tempreg, (unsigned long) ep->X_add_number, breg);
9876 /* If necessary, move the result in tempreg to the final destination. */
9877 if (!ust && treg != tempreg)
9879 /* Protect second load's delay slot. */
9881 move_register (treg, tempreg);
9887 if (target_big_endian == ust)
9888 ep->X_add_number += off;
9889 tempreg = ust || ab ? treg : AT;
9890 macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
9892 /* For halfword transfers we need a temporary register to shuffle
9893 bytes. Unfortunately for M_USH_A we have none available before
9894 the next store as AT holds the base address. We deal with this
9895 case by clobbering TREG and then restoring it as with ULH. */
9896 tempreg = ust == ab ? treg : AT;
9898 macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8);
9900 if (target_big_endian == ust)
9901 ep->X_add_number -= off;
9903 ep->X_add_number += off;
9904 macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
9906 /* For M_USH_A re-retrieve the LSB. */
9909 if (target_big_endian)
9910 ep->X_add_number += off;
9912 ep->X_add_number -= off;
9913 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
9915 /* For ULH and M_USH_A OR the LSB in. */
9918 tempreg = !ab ? AT : treg;
9919 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
9920 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
9925 /* FIXME: Check if this is one of the itbl macros, since they
9926 are added dynamically. */
9927 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
9930 if (!mips_opts.at && used_at)
9931 as_bad (_("Macro used $at after \".set noat\""));
9934 /* Implement macros in mips16 mode. */
9937 mips16_macro (struct mips_cl_insn *ip)
9940 int xreg, yreg, zreg, tmp;
9943 const char *s, *s2, *s3;
9945 mask = ip->insn_mo->mask;
9947 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
9948 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
9949 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
9951 expr1.X_op = O_constant;
9952 expr1.X_op_symbol = NULL;
9953 expr1.X_add_symbol = NULL;
9954 expr1.X_add_number = 1;
9974 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
9975 expr1.X_add_number = 2;
9976 macro_build (&expr1, "bnez", "x,p", yreg);
9977 macro_build (NULL, "break", "6", 7);
9979 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
9980 since that causes an overflow. We should do that as well,
9981 but I don't see how to do the comparisons without a temporary
9984 macro_build (NULL, s, "x", zreg);
10003 start_noreorder ();
10004 macro_build (NULL, s, "0,x,y", xreg, yreg);
10005 expr1.X_add_number = 2;
10006 macro_build (&expr1, "bnez", "x,p", yreg);
10007 macro_build (NULL, "break", "6", 7);
10009 macro_build (NULL, s2, "x", zreg);
10015 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
10016 macro_build (NULL, "mflo", "x", zreg);
10024 if (imm_expr.X_op != O_constant)
10025 as_bad (_("Unsupported large constant"));
10026 imm_expr.X_add_number = -imm_expr.X_add_number;
10027 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
10031 if (imm_expr.X_op != O_constant)
10032 as_bad (_("Unsupported large constant"));
10033 imm_expr.X_add_number = -imm_expr.X_add_number;
10034 macro_build (&imm_expr, "addiu", "x,k", xreg);
10038 if (imm_expr.X_op != O_constant)
10039 as_bad (_("Unsupported large constant"));
10040 imm_expr.X_add_number = -imm_expr.X_add_number;
10041 macro_build (&imm_expr, "daddiu", "y,j", yreg);
10063 goto do_reverse_branch;
10067 goto do_reverse_branch;
10079 goto do_reverse_branch;
10090 macro_build (NULL, s, "x,y", xreg, yreg);
10091 macro_build (&offset_expr, s2, "p");
10118 goto do_addone_branch_i;
10123 goto do_addone_branch_i;
10138 goto do_addone_branch_i;
10144 do_addone_branch_i:
10145 if (imm_expr.X_op != O_constant)
10146 as_bad (_("Unsupported large constant"));
10147 ++imm_expr.X_add_number;
10150 macro_build (&imm_expr, s, s3, xreg);
10151 macro_build (&offset_expr, s2, "p");
10155 expr1.X_add_number = 0;
10156 macro_build (&expr1, "slti", "x,8", yreg);
10158 move_register (xreg, yreg);
10159 expr1.X_add_number = 2;
10160 macro_build (&expr1, "bteqz", "p");
10161 macro_build (NULL, "neg", "x,w", xreg, xreg);
10165 /* For consistency checking, verify that all bits are specified either
10166 by the match/mask part of the instruction definition, or by the
10169 validate_mips_insn (const struct mips_opcode *opc)
10171 const char *p = opc->args;
10173 unsigned long used_bits = opc->mask;
10175 if ((used_bits & opc->match) != opc->match)
10177 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
10178 opc->name, opc->args);
10181 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
10191 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
10192 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
10193 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
10194 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
10195 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10196 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10197 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10198 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
10199 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10200 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10201 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10202 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10203 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10205 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10206 case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
10207 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10208 case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10209 case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10210 case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10211 case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10212 case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
10213 case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10214 case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10215 case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break;
10216 case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break;
10217 case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break;
10218 case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break;
10219 case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break;
10222 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
10223 c, opc->name, opc->args);
10227 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10228 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10230 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
10231 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
10232 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10233 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10235 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10236 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10238 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
10239 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10241 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
10242 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
10243 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
10244 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
10245 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10246 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
10247 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10248 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10249 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10250 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10251 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10252 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10253 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10254 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
10255 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10256 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
10257 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10259 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
10260 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10261 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10262 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
10264 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10265 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10266 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
10267 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10268 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10269 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10270 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10271 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10272 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10275 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
10276 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
10277 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10278 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
10279 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
10282 case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10283 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
10284 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
10285 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
10286 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
10287 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10288 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
10289 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
10290 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
10291 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
10292 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
10293 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
10294 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
10295 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
10296 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
10297 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
10298 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
10299 case '\\': USE_BITS (OP_MASK_3BITPOS, OP_SH_3BITPOS); break;
10300 case '~': USE_BITS (OP_MASK_OFFSET12, OP_SH_OFFSET12); break;
10301 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10303 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
10304 c, opc->name, opc->args);
10308 if (used_bits != 0xffffffff)
10310 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
10311 ~used_bits & 0xffffffff, opc->name, opc->args);
10317 /* For consistency checking, verify that the length implied matches the
10318 major opcode and that all bits are specified either by the match/mask
10319 part of the instruction definition, or by the operand list. */
10322 validate_micromips_insn (const struct mips_opcode *opc)
10324 unsigned long match = opc->match;
10325 unsigned long mask = opc->mask;
10326 const char *p = opc->args;
10327 unsigned long insn_bits;
10328 unsigned long used_bits;
10329 unsigned long major;
10330 unsigned int length;
10334 if ((mask & match) != match)
10336 as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"),
10337 opc->name, opc->args);
10340 length = micromips_insn_length (opc);
10341 if (length != 2 && length != 4)
10343 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
10344 "%s %s"), length, opc->name, opc->args);
10347 major = match >> (10 + 8 * (length - 2));
10348 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
10349 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
10351 as_bad (_("Internal error: bad microMIPS opcode "
10352 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
10356 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
10357 insn_bits = 1 << 4 * length;
10358 insn_bits <<= 4 * length;
10361 #define USE_BITS(field) \
10362 (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field)
10373 case 'A': USE_BITS (EXTLSB); break;
10374 case 'B': USE_BITS (INSMSB); break;
10375 case 'C': USE_BITS (EXTMSBD); break;
10376 case 'D': USE_BITS (RS); USE_BITS (SEL); break;
10377 case 'E': USE_BITS (EXTLSB); break;
10378 case 'F': USE_BITS (INSMSB); break;
10379 case 'G': USE_BITS (EXTMSBD); break;
10380 case 'H': USE_BITS (EXTMSBD); break;
10382 as_bad (_("Internal error: bad mips opcode "
10383 "(unknown extension operand type `%c%c'): %s %s"),
10384 e, c, opc->name, opc->args);
10392 case 'A': USE_BITS (IMMA); break;
10393 case 'B': USE_BITS (IMMB); break;
10394 case 'C': USE_BITS (IMMC); break;
10395 case 'D': USE_BITS (IMMD); break;
10396 case 'E': USE_BITS (IMME); break;
10397 case 'F': USE_BITS (IMMF); break;
10398 case 'G': USE_BITS (IMMG); break;
10399 case 'H': USE_BITS (IMMH); break;
10400 case 'I': USE_BITS (IMMI); break;
10401 case 'J': USE_BITS (IMMJ); break;
10402 case 'L': USE_BITS (IMML); break;
10403 case 'M': USE_BITS (IMMM); break;
10404 case 'N': USE_BITS (IMMN); break;
10405 case 'O': USE_BITS (IMMO); break;
10406 case 'P': USE_BITS (IMMP); break;
10407 case 'Q': USE_BITS (IMMQ); break;
10408 case 'U': USE_BITS (IMMU); break;
10409 case 'W': USE_BITS (IMMW); break;
10410 case 'X': USE_BITS (IMMX); break;
10411 case 'Y': USE_BITS (IMMY); break;
10414 case 'b': USE_BITS (MB); break;
10415 case 'c': USE_BITS (MC); break;
10416 case 'd': USE_BITS (MD); break;
10417 case 'e': USE_BITS (ME); break;
10418 case 'f': USE_BITS (MF); break;
10419 case 'g': USE_BITS (MG); break;
10420 case 'h': USE_BITS (MH); break;
10421 case 'i': USE_BITS (MI); break;
10422 case 'j': USE_BITS (MJ); break;
10423 case 'l': USE_BITS (ML); break;
10424 case 'm': USE_BITS (MM); break;
10425 case 'n': USE_BITS (MN); break;
10426 case 'p': USE_BITS (MP); break;
10427 case 'q': USE_BITS (MQ); break;
10435 as_bad (_("Internal error: bad mips opcode "
10436 "(unknown extension operand type `%c%c'): %s %s"),
10437 e, c, opc->name, opc->args);
10441 case '.': USE_BITS (OFFSET10); break;
10442 case '1': USE_BITS (STYPE); break;
10443 case '<': USE_BITS (SHAMT); break;
10444 case '>': USE_BITS (SHAMT); break;
10445 case 'B': USE_BITS (CODE10); break;
10446 case 'C': USE_BITS (COPZ); break;
10447 case 'D': USE_BITS (FD); break;
10448 case 'E': USE_BITS (RT); break;
10449 case 'G': USE_BITS (RS); break;
10450 case 'H': USE_BITS (SEL); break;
10451 case 'K': USE_BITS (RS); break;
10452 case 'M': USE_BITS (CCC); break;
10453 case 'N': USE_BITS (BCC); break;
10454 case 'R': USE_BITS (FR); break;
10455 case 'S': USE_BITS (FS); break;
10456 case 'T': USE_BITS (FT); break;
10457 case 'V': USE_BITS (FS); break;
10458 case '\\': USE_BITS (3BITPOS); break;
10459 case 'a': USE_BITS (TARGET); break;
10460 case 'b': USE_BITS (RS); break;
10461 case 'c': USE_BITS (CODE); break;
10462 case 'd': USE_BITS (RD); break;
10463 case 'h': USE_BITS (PREFX); break;
10464 case 'i': USE_BITS (IMMEDIATE); break;
10465 case 'j': USE_BITS (DELTA); break;
10466 case 'k': USE_BITS (CACHE); break;
10467 case 'n': USE_BITS (RT); break;
10468 case 'o': USE_BITS (DELTA); break;
10469 case 'p': USE_BITS (DELTA); break;
10470 case 'q': USE_BITS (CODE2); break;
10471 case 'r': USE_BITS (RS); break;
10472 case 's': USE_BITS (RS); break;
10473 case 't': USE_BITS (RT); break;
10474 case 'u': USE_BITS (IMMEDIATE); break;
10475 case 'v': USE_BITS (RS); break;
10476 case 'w': USE_BITS (RT); break;
10477 case 'y': USE_BITS (RS3); break;
10479 case '|': USE_BITS (TRAP); break;
10480 case '~': USE_BITS (OFFSET12); break;
10482 as_bad (_("Internal error: bad microMIPS opcode "
10483 "(unknown operand type `%c'): %s %s"),
10484 c, opc->name, opc->args);
10488 if (used_bits != insn_bits)
10490 if (~used_bits & insn_bits)
10491 as_bad (_("Internal error: bad microMIPS opcode "
10492 "(bits 0x%lx undefined): %s %s"),
10493 ~used_bits & insn_bits, opc->name, opc->args);
10494 if (used_bits & ~insn_bits)
10495 as_bad (_("Internal error: bad microMIPS opcode "
10496 "(bits 0x%lx defined): %s %s"),
10497 used_bits & ~insn_bits, opc->name, opc->args);
10503 /* UDI immediates. */
10504 struct mips_immed {
10506 unsigned int shift;
10507 unsigned long mask;
10511 static const struct mips_immed mips_immed[] = {
10512 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
10513 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
10514 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
10515 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
10519 /* Check whether an odd floating-point register is allowed. */
10521 mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
10523 const char *s = insn->name;
10525 if (insn->pinfo == INSN_MACRO)
10526 /* Let a macro pass, we'll catch it later when it is expanded. */
10529 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa))
10531 /* Allow odd registers for single-precision ops. */
10532 switch (insn->pinfo & (FP_S | FP_D))
10536 return 1; /* both single precision - ok */
10538 return 0; /* both double precision - fail */
10543 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
10544 s = strchr (insn->name, '.');
10546 s = s != NULL ? strchr (s + 1, '.') : NULL;
10547 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
10550 /* Single-precision coprocessor loads and moves are OK too. */
10551 if ((insn->pinfo & FP_S)
10552 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
10553 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
10559 /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
10560 taking bits from BIT up. */
10562 expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit)
10564 return (ep->X_op == O_constant
10565 && (ep->X_add_number & ((1 << bit) - 1)) == 0
10566 && ep->X_add_number >= min << bit
10567 && ep->X_add_number < max << bit);
10570 /* This routine assembles an instruction into its binary format. As a
10571 side effect, it sets one of the global variables imm_reloc or
10572 offset_reloc to the type of relocation to do if one of the operands
10573 is an address expression. */
10576 mips_ip (char *str, struct mips_cl_insn *ip)
10578 bfd_boolean wrong_delay_slot_insns = FALSE;
10579 bfd_boolean need_delay_slot_ok = TRUE;
10580 struct mips_opcode *firstinsn = NULL;
10581 const struct mips_opcode *past;
10582 struct hash_control *hash;
10586 struct mips_opcode *insn;
10588 unsigned int regno;
10589 unsigned int lastregno;
10590 unsigned int destregno = 0;
10591 unsigned int lastpos = 0;
10592 unsigned int limlo, limhi;
10594 offsetT min_range, max_range;
10598 unsigned int rtype;
10604 if (mips_opts.micromips)
10606 hash = micromips_op_hash;
10607 past = µmips_opcodes[bfd_micromips_num_opcodes];
10612 past = &mips_opcodes[NUMOPCODES];
10614 forced_insn_length = 0;
10617 /* We first try to match an instruction up to a space or to the end. */
10618 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
10621 /* Make a copy of the instruction so that we can fiddle with it. */
10622 name = alloca (end + 1);
10623 memcpy (name, str, end);
10628 insn = (struct mips_opcode *) hash_find (hash, name);
10630 if (insn != NULL || !mips_opts.micromips)
10632 if (forced_insn_length)
10635 /* See if there's an instruction size override suffix,
10636 either `16' or `32', at the end of the mnemonic proper,
10637 that defines the operation, i.e. before the first `.'
10638 character if any. Strip it and retry. */
10639 dot = strchr (name, '.');
10640 opend = dot != NULL ? dot - name : end;
10643 if (name[opend - 2] == '1' && name[opend - 1] == '6')
10644 forced_insn_length = 2;
10645 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
10646 forced_insn_length = 4;
10649 memcpy (name + opend - 2, name + opend, end - opend + 1);
10653 insn_error = _("Unrecognized opcode");
10657 /* For microMIPS instructions placed in a fixed-length branch delay slot
10658 we make up to two passes over the relevant fragment of the opcode
10659 table. First we try instructions that meet the delay slot's length
10660 requirement. If none matched, then we retry with the remaining ones
10661 and if one matches, then we use it and then issue an appropriate
10662 warning later on. */
10663 argsStart = s = str + end;
10666 bfd_boolean delay_slot_ok;
10667 bfd_boolean size_ok;
10670 gas_assert (strcmp (insn->name, name) == 0);
10672 ok = is_opcode_valid (insn);
10673 size_ok = is_size_valid (insn);
10674 delay_slot_ok = is_delay_slot_valid (insn);
10675 if (!delay_slot_ok && !wrong_delay_slot_insns)
10678 wrong_delay_slot_insns = TRUE;
10680 if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok)
10682 static char buf[256];
10684 if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0)
10689 if (wrong_delay_slot_insns && need_delay_slot_ok)
10691 gas_assert (firstinsn);
10692 need_delay_slot_ok = FALSE;
10702 sprintf (buf, _("opcode not supported on this processor: %s (%s)"),
10703 mips_cpu_info_from_arch (mips_opts.arch)->name,
10704 mips_cpu_info_from_isa (mips_opts.isa)->name);
10706 sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"),
10707 8 * forced_insn_length);
10713 create_insn (ip, insn);
10716 lastregno = 0xffffffff;
10717 for (args = insn->args;; ++args)
10721 s += strspn (s, " \t");
10725 case '\0': /* end of args */
10730 case '2': /* DSP 2-bit unsigned immediate in bit 11. */
10731 gas_assert (!mips_opts.micromips);
10732 my_getExpression (&imm_expr, s);
10733 check_absolute_expr (ip, &imm_expr);
10734 if ((unsigned long) imm_expr.X_add_number != 1
10735 && (unsigned long) imm_expr.X_add_number != 3)
10737 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
10738 (unsigned long) imm_expr.X_add_number);
10740 INSERT_OPERAND (0, BP, *ip, imm_expr.X_add_number);
10741 imm_expr.X_op = O_absent;
10745 case '3': /* DSP 3-bit unsigned immediate in bit 21. */
10746 gas_assert (!mips_opts.micromips);
10747 my_getExpression (&imm_expr, s);
10748 check_absolute_expr (ip, &imm_expr);
10749 if (imm_expr.X_add_number & ~OP_MASK_SA3)
10751 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10752 OP_MASK_SA3, (unsigned long) imm_expr.X_add_number);
10754 INSERT_OPERAND (0, SA3, *ip, imm_expr.X_add_number);
10755 imm_expr.X_op = O_absent;
10759 case '4': /* DSP 4-bit unsigned immediate in bit 21. */
10760 gas_assert (!mips_opts.micromips);
10761 my_getExpression (&imm_expr, s);
10762 check_absolute_expr (ip, &imm_expr);
10763 if (imm_expr.X_add_number & ~OP_MASK_SA4)
10765 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10766 OP_MASK_SA4, (unsigned long) imm_expr.X_add_number);
10768 INSERT_OPERAND (0, SA4, *ip, imm_expr.X_add_number);
10769 imm_expr.X_op = O_absent;
10773 case '5': /* DSP 8-bit unsigned immediate in bit 16. */
10774 gas_assert (!mips_opts.micromips);
10775 my_getExpression (&imm_expr, s);
10776 check_absolute_expr (ip, &imm_expr);
10777 if (imm_expr.X_add_number & ~OP_MASK_IMM8)
10779 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10780 OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number);
10782 INSERT_OPERAND (0, IMM8, *ip, imm_expr.X_add_number);
10783 imm_expr.X_op = O_absent;
10787 case '6': /* DSP 5-bit unsigned immediate in bit 21. */
10788 gas_assert (!mips_opts.micromips);
10789 my_getExpression (&imm_expr, s);
10790 check_absolute_expr (ip, &imm_expr);
10791 if (imm_expr.X_add_number & ~OP_MASK_RS)
10793 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10794 OP_MASK_RS, (unsigned long) imm_expr.X_add_number);
10796 INSERT_OPERAND (0, RS, *ip, imm_expr.X_add_number);
10797 imm_expr.X_op = O_absent;
10801 case '7': /* Four DSP accumulators in bits 11,12. */
10802 gas_assert (!mips_opts.micromips);
10803 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
10804 s[3] >= '0' && s[3] <= '3')
10806 regno = s[3] - '0';
10808 INSERT_OPERAND (0, DSPACC, *ip, regno);
10812 as_bad (_("Invalid dsp acc register"));
10815 case '8': /* DSP 6-bit unsigned immediate in bit 11. */
10816 gas_assert (!mips_opts.micromips);
10817 my_getExpression (&imm_expr, s);
10818 check_absolute_expr (ip, &imm_expr);
10819 if (imm_expr.X_add_number & ~OP_MASK_WRDSP)
10821 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10823 (unsigned long) imm_expr.X_add_number);
10825 INSERT_OPERAND (0, WRDSP, *ip, imm_expr.X_add_number);
10826 imm_expr.X_op = O_absent;
10830 case '9': /* Four DSP accumulators in bits 21,22. */
10831 gas_assert (!mips_opts.micromips);
10832 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
10833 s[3] >= '0' && s[3] <= '3')
10835 regno = s[3] - '0';
10837 INSERT_OPERAND (0, DSPACC_S, *ip, regno);
10841 as_bad (_("Invalid dsp acc register"));
10844 case '0': /* DSP 6-bit signed immediate in bit 20. */
10845 gas_assert (!mips_opts.micromips);
10846 my_getExpression (&imm_expr, s);
10847 check_absolute_expr (ip, &imm_expr);
10848 min_range = -((OP_MASK_DSPSFT + 1) >> 1);
10849 max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1;
10850 if (imm_expr.X_add_number < min_range ||
10851 imm_expr.X_add_number > max_range)
10853 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10854 (long) min_range, (long) max_range,
10855 (long) imm_expr.X_add_number);
10857 INSERT_OPERAND (0, DSPSFT, *ip, imm_expr.X_add_number);
10858 imm_expr.X_op = O_absent;
10862 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
10863 gas_assert (!mips_opts.micromips);
10864 my_getExpression (&imm_expr, s);
10865 check_absolute_expr (ip, &imm_expr);
10866 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
10868 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10870 (unsigned long) imm_expr.X_add_number);
10872 INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number);
10873 imm_expr.X_op = O_absent;
10877 case ':': /* DSP 7-bit signed immediate in bit 19. */
10878 gas_assert (!mips_opts.micromips);
10879 my_getExpression (&imm_expr, s);
10880 check_absolute_expr (ip, &imm_expr);
10881 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
10882 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
10883 if (imm_expr.X_add_number < min_range ||
10884 imm_expr.X_add_number > max_range)
10886 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10887 (long) min_range, (long) max_range,
10888 (long) imm_expr.X_add_number);
10890 INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number);
10891 imm_expr.X_op = O_absent;
10895 case '@': /* DSP 10-bit signed immediate in bit 16. */
10896 gas_assert (!mips_opts.micromips);
10897 my_getExpression (&imm_expr, s);
10898 check_absolute_expr (ip, &imm_expr);
10899 min_range = -((OP_MASK_IMM10 + 1) >> 1);
10900 max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1;
10901 if (imm_expr.X_add_number < min_range ||
10902 imm_expr.X_add_number > max_range)
10904 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10905 (long) min_range, (long) max_range,
10906 (long) imm_expr.X_add_number);
10908 INSERT_OPERAND (0, IMM10, *ip, imm_expr.X_add_number);
10909 imm_expr.X_op = O_absent;
10913 case '!': /* MT usermode flag bit. */
10914 gas_assert (!mips_opts.micromips);
10915 my_getExpression (&imm_expr, s);
10916 check_absolute_expr (ip, &imm_expr);
10917 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
10918 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
10919 (unsigned long) imm_expr.X_add_number);
10920 INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number);
10921 imm_expr.X_op = O_absent;
10925 case '$': /* MT load high flag bit. */
10926 gas_assert (!mips_opts.micromips);
10927 my_getExpression (&imm_expr, s);
10928 check_absolute_expr (ip, &imm_expr);
10929 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
10930 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
10931 (unsigned long) imm_expr.X_add_number);
10932 INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number);
10933 imm_expr.X_op = O_absent;
10937 case '*': /* Four DSP accumulators in bits 18,19. */
10938 gas_assert (!mips_opts.micromips);
10939 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
10940 s[3] >= '0' && s[3] <= '3')
10942 regno = s[3] - '0';
10944 INSERT_OPERAND (0, MTACC_T, *ip, regno);
10948 as_bad (_("Invalid dsp/smartmips acc register"));
10951 case '&': /* Four DSP accumulators in bits 13,14. */
10952 gas_assert (!mips_opts.micromips);
10953 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
10954 s[3] >= '0' && s[3] <= '3')
10956 regno = s[3] - '0';
10958 INSERT_OPERAND (0, MTACC_D, *ip, regno);
10962 as_bad (_("Invalid dsp/smartmips acc register"));
10965 case '\\': /* 3-bit bit position. */
10967 unsigned long mask = (!mips_opts.micromips
10969 : MICROMIPSOP_MASK_3BITPOS);
10971 my_getExpression (&imm_expr, s);
10972 check_absolute_expr (ip, &imm_expr);
10973 if ((unsigned long) imm_expr.X_add_number > mask)
10974 as_warn (_("Bit position for %s not in range 0..%lu (%lu)"),
10976 mask, (unsigned long) imm_expr.X_add_number);
10977 INSERT_OPERAND (mips_opts.micromips,
10978 3BITPOS, *ip, imm_expr.X_add_number);
10979 imm_expr.X_op = O_absent;
10993 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
10997 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
11001 gas_assert (!mips_opts.micromips);
11002 INSERT_OPERAND (0, FT, *ip, lastregno);
11006 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
11012 /* Handle optional base register.
11013 Either the base register is omitted or
11014 we must have a left paren. */
11015 /* This is dependent on the next operand specifier
11016 is a base register specification. */
11017 gas_assert (args[1] == 'b'
11018 || (mips_opts.micromips
11020 && (args[2] == 'l' || args[2] == 'n'
11021 || args[2] == 's' || args[2] == 'a')));
11022 if (*s == '\0' && args[1] == 'b')
11024 /* Fall through. */
11026 case ')': /* These must match exactly. */
11031 case '[': /* These must match exactly. */
11033 gas_assert (!mips_opts.micromips);
11038 case '+': /* Opcode extension character. */
11041 case '1': /* UDI immediates. */
11045 gas_assert (!mips_opts.micromips);
11047 const struct mips_immed *imm = mips_immed;
11049 while (imm->type && imm->type != *args)
11053 my_getExpression (&imm_expr, s);
11054 check_absolute_expr (ip, &imm_expr);
11055 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
11057 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
11058 imm->desc ? imm->desc : ip->insn_mo->name,
11059 (unsigned long) imm_expr.X_add_number,
11060 (unsigned long) imm_expr.X_add_number);
11061 imm_expr.X_add_number &= imm->mask;
11063 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
11065 imm_expr.X_op = O_absent;
11070 case 'A': /* ins/ext position, becomes LSB. */
11079 my_getExpression (&imm_expr, s);
11080 check_absolute_expr (ip, &imm_expr);
11081 if ((unsigned long) imm_expr.X_add_number < limlo
11082 || (unsigned long) imm_expr.X_add_number > limhi)
11084 as_bad (_("Improper position (%lu)"),
11085 (unsigned long) imm_expr.X_add_number);
11086 imm_expr.X_add_number = limlo;
11088 lastpos = imm_expr.X_add_number;
11089 INSERT_OPERAND (mips_opts.micromips,
11090 EXTLSB, *ip, imm_expr.X_add_number);
11091 imm_expr.X_op = O_absent;
11095 case 'B': /* ins size, becomes MSB. */
11104 my_getExpression (&imm_expr, s);
11105 check_absolute_expr (ip, &imm_expr);
11106 /* Check for negative input so that small negative numbers
11107 will not succeed incorrectly. The checks against
11108 (pos+size) transitively check "size" itself,
11109 assuming that "pos" is reasonable. */
11110 if ((long) imm_expr.X_add_number < 0
11111 || ((unsigned long) imm_expr.X_add_number
11113 || ((unsigned long) imm_expr.X_add_number
11114 + lastpos) > limhi)
11116 as_bad (_("Improper insert size (%lu, position %lu)"),
11117 (unsigned long) imm_expr.X_add_number,
11118 (unsigned long) lastpos);
11119 imm_expr.X_add_number = limlo - lastpos;
11121 INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip,
11122 lastpos + imm_expr.X_add_number - 1);
11123 imm_expr.X_op = O_absent;
11127 case 'C': /* ext size, becomes MSBD. */
11140 my_getExpression (&imm_expr, s);
11141 check_absolute_expr (ip, &imm_expr);
11142 /* Check for negative input so that small negative numbers
11143 will not succeed incorrectly. The checks against
11144 (pos+size) transitively check "size" itself,
11145 assuming that "pos" is reasonable. */
11146 if ((long) imm_expr.X_add_number < 0
11147 || ((unsigned long) imm_expr.X_add_number
11149 || ((unsigned long) imm_expr.X_add_number
11150 + lastpos) > limhi)
11152 as_bad (_("Improper extract size (%lu, position %lu)"),
11153 (unsigned long) imm_expr.X_add_number,
11154 (unsigned long) lastpos);
11155 imm_expr.X_add_number = limlo - lastpos;
11157 INSERT_OPERAND (mips_opts.micromips,
11158 EXTMSBD, *ip, imm_expr.X_add_number - 1);
11159 imm_expr.X_op = O_absent;
11164 /* +D is for disassembly only; never match. */
11168 /* "+I" is like "I", except that imm2_expr is used. */
11169 my_getExpression (&imm2_expr, s);
11170 if (imm2_expr.X_op != O_big
11171 && imm2_expr.X_op != O_constant)
11172 insn_error = _("absolute expression required");
11173 if (HAVE_32BIT_GPRS)
11174 normalize_constant_expr (&imm2_expr);
11178 case 'T': /* Coprocessor register. */
11179 gas_assert (!mips_opts.micromips);
11180 /* +T is for disassembly only; never match. */
11183 case 't': /* Coprocessor register number. */
11184 gas_assert (!mips_opts.micromips);
11185 if (s[0] == '$' && ISDIGIT (s[1]))
11195 while (ISDIGIT (*s));
11197 as_bad (_("Invalid register number (%d)"), regno);
11200 INSERT_OPERAND (0, RT, *ip, regno);
11205 as_bad (_("Invalid coprocessor 0 register number"));
11209 /* bbit[01] and bbit[01]32 bit index. Give error if index
11210 is not in the valid range. */
11211 gas_assert (!mips_opts.micromips);
11212 my_getExpression (&imm_expr, s);
11213 check_absolute_expr (ip, &imm_expr);
11214 if ((unsigned) imm_expr.X_add_number > 31)
11216 as_bad (_("Improper bit index (%lu)"),
11217 (unsigned long) imm_expr.X_add_number);
11218 imm_expr.X_add_number = 0;
11220 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number);
11221 imm_expr.X_op = O_absent;
11226 /* bbit[01] bit index when bbit is used but we generate
11227 bbit[01]32 because the index is over 32. Move to the
11228 next candidate if index is not in the valid range. */
11229 gas_assert (!mips_opts.micromips);
11230 my_getExpression (&imm_expr, s);
11231 check_absolute_expr (ip, &imm_expr);
11232 if ((unsigned) imm_expr.X_add_number < 32
11233 || (unsigned) imm_expr.X_add_number > 63)
11235 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32);
11236 imm_expr.X_op = O_absent;
11241 /* cins, cins32, exts and exts32 position field. Give error
11242 if it's not in the valid range. */
11243 gas_assert (!mips_opts.micromips);
11244 my_getExpression (&imm_expr, s);
11245 check_absolute_expr (ip, &imm_expr);
11246 if ((unsigned) imm_expr.X_add_number > 31)
11248 as_bad (_("Improper position (%lu)"),
11249 (unsigned long) imm_expr.X_add_number);
11250 imm_expr.X_add_number = 0;
11252 /* Make the pos explicit to simplify +S. */
11253 lastpos = imm_expr.X_add_number + 32;
11254 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number);
11255 imm_expr.X_op = O_absent;
11260 /* cins, cins32, exts and exts32 position field. Move to
11261 the next candidate if it's not in the valid range. */
11262 gas_assert (!mips_opts.micromips);
11263 my_getExpression (&imm_expr, s);
11264 check_absolute_expr (ip, &imm_expr);
11265 if ((unsigned) imm_expr.X_add_number < 32
11266 || (unsigned) imm_expr.X_add_number > 63)
11268 lastpos = imm_expr.X_add_number;
11269 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32);
11270 imm_expr.X_op = O_absent;
11275 /* cins and exts length-minus-one field. */
11276 gas_assert (!mips_opts.micromips);
11277 my_getExpression (&imm_expr, s);
11278 check_absolute_expr (ip, &imm_expr);
11279 if ((unsigned long) imm_expr.X_add_number > 31)
11281 as_bad (_("Improper size (%lu)"),
11282 (unsigned long) imm_expr.X_add_number);
11283 imm_expr.X_add_number = 0;
11285 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11286 imm_expr.X_op = O_absent;
11291 /* cins32/exts32 and cins/exts aliasing cint32/exts32
11292 length-minus-one field. */
11293 gas_assert (!mips_opts.micromips);
11294 my_getExpression (&imm_expr, s);
11295 check_absolute_expr (ip, &imm_expr);
11296 if ((long) imm_expr.X_add_number < 0
11297 || (unsigned long) imm_expr.X_add_number + lastpos > 63)
11299 as_bad (_("Improper size (%lu)"),
11300 (unsigned long) imm_expr.X_add_number);
11301 imm_expr.X_add_number = 0;
11303 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11304 imm_expr.X_op = O_absent;
11309 /* seqi/snei immediate field. */
11310 gas_assert (!mips_opts.micromips);
11311 my_getExpression (&imm_expr, s);
11312 check_absolute_expr (ip, &imm_expr);
11313 if ((long) imm_expr.X_add_number < -512
11314 || (long) imm_expr.X_add_number >= 512)
11316 as_bad (_("Improper immediate (%ld)"),
11317 (long) imm_expr.X_add_number);
11318 imm_expr.X_add_number = 0;
11320 INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number);
11321 imm_expr.X_op = O_absent;
11325 case 'a': /* 8-bit signed offset in bit 6 */
11326 gas_assert (!mips_opts.micromips);
11327 my_getExpression (&imm_expr, s);
11328 check_absolute_expr (ip, &imm_expr);
11329 min_range = -((OP_MASK_OFFSET_A + 1) >> 1);
11330 max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1;
11331 if (imm_expr.X_add_number < min_range
11332 || imm_expr.X_add_number > max_range)
11334 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11335 (long) min_range, (long) max_range,
11336 (long) imm_expr.X_add_number);
11338 INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number);
11339 imm_expr.X_op = O_absent;
11343 case 'b': /* 8-bit signed offset in bit 3 */
11344 gas_assert (!mips_opts.micromips);
11345 my_getExpression (&imm_expr, s);
11346 check_absolute_expr (ip, &imm_expr);
11347 min_range = -((OP_MASK_OFFSET_B + 1) >> 1);
11348 max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1;
11349 if (imm_expr.X_add_number < min_range
11350 || imm_expr.X_add_number > max_range)
11352 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11353 (long) min_range, (long) max_range,
11354 (long) imm_expr.X_add_number);
11356 INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number);
11357 imm_expr.X_op = O_absent;
11361 case 'c': /* 9-bit signed offset in bit 6 */
11362 gas_assert (!mips_opts.micromips);
11363 my_getExpression (&imm_expr, s);
11364 check_absolute_expr (ip, &imm_expr);
11365 min_range = -((OP_MASK_OFFSET_C + 1) >> 1);
11366 max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1;
11367 /* We check the offset range before adjusted. */
11370 if (imm_expr.X_add_number < min_range
11371 || imm_expr.X_add_number > max_range)
11373 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11374 (long) min_range, (long) max_range,
11375 (long) imm_expr.X_add_number);
11377 if (imm_expr.X_add_number & 0xf)
11379 as_bad (_("Offset not 16 bytes alignment (%ld)"),
11380 (long) imm_expr.X_add_number);
11382 /* Right shift 4 bits to adjust the offset operand. */
11383 INSERT_OPERAND (0, OFFSET_C, *ip,
11384 imm_expr.X_add_number >> 4);
11385 imm_expr.X_op = O_absent;
11390 gas_assert (!mips_opts.micromips);
11391 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
11393 if (regno == AT && mips_opts.at)
11395 if (mips_opts.at == ATREG)
11396 as_warn (_("used $at without \".set noat\""));
11398 as_warn (_("used $%u with \".set at=$%u\""),
11399 regno, mips_opts.at);
11401 INSERT_OPERAND (0, RZ, *ip, regno);
11405 gas_assert (!mips_opts.micromips);
11406 if (!reg_lookup (&s, RTYPE_FPU, ®no))
11408 INSERT_OPERAND (0, FZ, *ip, regno);
11412 as_bad (_("Internal error: bad %s opcode "
11413 "(unknown extension operand type `+%c'): %s %s"),
11414 mips_opts.micromips ? "microMIPS" : "MIPS",
11415 *args, insn->name, insn->args);
11416 /* Further processing is fruitless. */
11421 case '.': /* 10-bit offset. */
11422 gas_assert (mips_opts.micromips);
11423 case '~': /* 12-bit offset. */
11425 int shift = *args == '.' ? 9 : 11;
11428 /* Check whether there is only a single bracketed expression
11429 left. If so, it must be the base register and the
11430 constant must be zero. */
11431 if (*s == '(' && strchr (s + 1, '(') == 0)
11434 /* If this value won't fit into the offset, then go find
11435 a macro that will generate a 16- or 32-bit offset code
11437 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
11438 if ((i == 0 && (imm_expr.X_op != O_constant
11439 || imm_expr.X_add_number >= 1 << shift
11440 || imm_expr.X_add_number < -1 << shift))
11443 imm_expr.X_op = O_absent;
11447 INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number);
11449 INSERT_OPERAND (mips_opts.micromips,
11450 OFFSET12, *ip, imm_expr.X_add_number);
11451 imm_expr.X_op = O_absent;
11456 case '<': /* must be at least one digit */
11458 * According to the manual, if the shift amount is greater
11459 * than 31 or less than 0, then the shift amount should be
11460 * mod 32. In reality the mips assembler issues an error.
11461 * We issue a warning and mask out all but the low 5 bits.
11463 my_getExpression (&imm_expr, s);
11464 check_absolute_expr (ip, &imm_expr);
11465 if ((unsigned long) imm_expr.X_add_number > 31)
11466 as_warn (_("Improper shift amount (%lu)"),
11467 (unsigned long) imm_expr.X_add_number);
11468 INSERT_OPERAND (mips_opts.micromips,
11469 SHAMT, *ip, imm_expr.X_add_number);
11470 imm_expr.X_op = O_absent;
11474 case '>': /* shift amount minus 32 */
11475 my_getExpression (&imm_expr, s);
11476 check_absolute_expr (ip, &imm_expr);
11477 if ((unsigned long) imm_expr.X_add_number < 32
11478 || (unsigned long) imm_expr.X_add_number > 63)
11480 INSERT_OPERAND (mips_opts.micromips,
11481 SHAMT, *ip, imm_expr.X_add_number - 32);
11482 imm_expr.X_op = O_absent;
11486 case 'k': /* CACHE code. */
11487 case 'h': /* PREFX code. */
11488 case '1': /* SYNC type. */
11489 my_getExpression (&imm_expr, s);
11490 check_absolute_expr (ip, &imm_expr);
11491 if ((unsigned long) imm_expr.X_add_number > 31)
11492 as_warn (_("Invalid value for `%s' (%lu)"),
11494 (unsigned long) imm_expr.X_add_number);
11498 if (mips_fix_cn63xxp1
11499 && !mips_opts.micromips
11500 && strcmp ("pref", insn->name) == 0)
11501 switch (imm_expr.X_add_number)
11510 case 31: /* These are ok. */
11513 default: /* The rest must be changed to 28. */
11514 imm_expr.X_add_number = 28;
11517 INSERT_OPERAND (mips_opts.micromips,
11518 CACHE, *ip, imm_expr.X_add_number);
11521 INSERT_OPERAND (mips_opts.micromips,
11522 PREFX, *ip, imm_expr.X_add_number);
11525 INSERT_OPERAND (mips_opts.micromips,
11526 STYPE, *ip, imm_expr.X_add_number);
11529 imm_expr.X_op = O_absent;
11533 case 'c': /* BREAK code. */
11535 unsigned long mask = (mips_opts.micromips
11536 ? MICROMIPSOP_MASK_CODE
11539 my_getExpression (&imm_expr, s);
11540 check_absolute_expr (ip, &imm_expr);
11541 if ((unsigned long) imm_expr.X_add_number > mask)
11542 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11544 mask, (unsigned long) imm_expr.X_add_number);
11545 INSERT_OPERAND (mips_opts.micromips,
11546 CODE, *ip, imm_expr.X_add_number);
11547 imm_expr.X_op = O_absent;
11552 case 'q': /* Lower BREAK code. */
11554 unsigned long mask = (mips_opts.micromips
11555 ? MICROMIPSOP_MASK_CODE2
11558 my_getExpression (&imm_expr, s);
11559 check_absolute_expr (ip, &imm_expr);
11560 if ((unsigned long) imm_expr.X_add_number > mask)
11561 as_warn (_("Lower code for %s not in range 0..%lu (%lu)"),
11563 mask, (unsigned long) imm_expr.X_add_number);
11564 INSERT_OPERAND (mips_opts.micromips,
11565 CODE2, *ip, imm_expr.X_add_number);
11566 imm_expr.X_op = O_absent;
11571 case 'B': /* 20- or 10-bit syscall/break/wait code. */
11573 unsigned long mask = (mips_opts.micromips
11574 ? MICROMIPSOP_MASK_CODE10
11577 my_getExpression (&imm_expr, s);
11578 check_absolute_expr (ip, &imm_expr);
11579 if ((unsigned long) imm_expr.X_add_number > mask)
11580 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11582 mask, (unsigned long) imm_expr.X_add_number);
11583 if (mips_opts.micromips)
11584 INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number);
11586 INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number);
11587 imm_expr.X_op = O_absent;
11592 case 'C': /* 25- or 23-bit coprocessor code. */
11594 unsigned long mask = (mips_opts.micromips
11595 ? MICROMIPSOP_MASK_COPZ
11598 my_getExpression (&imm_expr, s);
11599 check_absolute_expr (ip, &imm_expr);
11600 if ((unsigned long) imm_expr.X_add_number > mask)
11601 as_warn (_("Coproccesor code > %u bits (%lu)"),
11602 mips_opts.micromips ? 23U : 25U,
11603 (unsigned long) imm_expr.X_add_number);
11604 INSERT_OPERAND (mips_opts.micromips,
11605 COPZ, *ip, imm_expr.X_add_number);
11606 imm_expr.X_op = O_absent;
11611 case 'J': /* 19-bit WAIT code. */
11612 gas_assert (!mips_opts.micromips);
11613 my_getExpression (&imm_expr, s);
11614 check_absolute_expr (ip, &imm_expr);
11615 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
11617 as_warn (_("Illegal 19-bit code (%lu)"),
11618 (unsigned long) imm_expr.X_add_number);
11619 imm_expr.X_add_number &= OP_MASK_CODE19;
11621 INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number);
11622 imm_expr.X_op = O_absent;
11626 case 'P': /* Performance register. */
11627 gas_assert (!mips_opts.micromips);
11628 my_getExpression (&imm_expr, s);
11629 check_absolute_expr (ip, &imm_expr);
11630 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
11631 as_warn (_("Invalid performance register (%lu)"),
11632 (unsigned long) imm_expr.X_add_number);
11633 INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number);
11634 imm_expr.X_op = O_absent;
11638 case 'G': /* Coprocessor destination register. */
11640 unsigned long opcode = ip->insn_opcode;
11641 unsigned long mask;
11642 unsigned int types;
11645 if (mips_opts.micromips)
11647 mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT)
11648 | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)
11649 | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL));
11653 case 0x000000fc: /* mfc0 */
11654 case 0x000002fc: /* mtc0 */
11655 case 0x580000fc: /* dmfc0 */
11656 case 0x580002fc: /* dmtc0 */
11666 opcode = (opcode >> OP_SH_OP) & OP_MASK_OP;
11667 cop0 = opcode == OP_OP_COP0;
11669 types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP);
11670 ok = reg_lookup (&s, types, ®no);
11671 if (mips_opts.micromips)
11672 INSERT_OPERAND (1, RS, *ip, regno);
11674 INSERT_OPERAND (0, RD, *ip, regno);
11683 case 'y': /* ALNV.PS source register. */
11684 gas_assert (mips_opts.micromips);
11686 case 'x': /* Ignore register name. */
11687 case 'U': /* Destination register (CLO/CLZ). */
11688 case 'g': /* Coprocessor destination register. */
11689 gas_assert (!mips_opts.micromips);
11690 case 'b': /* Base register. */
11691 case 'd': /* Destination register. */
11692 case 's': /* Source register. */
11693 case 't': /* Target register. */
11694 case 'r': /* Both target and source. */
11695 case 'v': /* Both dest and source. */
11696 case 'w': /* Both dest and target. */
11697 case 'E': /* Coprocessor target register. */
11698 case 'K': /* RDHWR destination register. */
11699 case 'z': /* Must be zero register. */
11702 if (*args == 'E' || *args == 'K')
11703 ok = reg_lookup (&s, RTYPE_NUM, ®no);
11706 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
11707 if (regno == AT && mips_opts.at)
11709 if (mips_opts.at == ATREG)
11710 as_warn (_("Used $at without \".set noat\""));
11712 as_warn (_("Used $%u with \".set at=$%u\""),
11713 regno, mips_opts.at);
11723 if (c == 'r' || c == 'v' || c == 'w')
11730 /* 'z' only matches $0. */
11731 if (c == 'z' && regno != 0)
11734 if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
11736 if (regno == lastregno)
11739 = _("Source and destination must be different");
11742 if (regno == 31 && lastregno == 0xffffffff)
11745 = _("A destination register must be supplied");
11749 /* Now that we have assembled one operand, we use the args
11750 string to figure out where it goes in the instruction. */
11757 INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno);
11761 if (mips_opts.micromips)
11762 INSERT_OPERAND (1, RS, *ip, regno);
11764 INSERT_OPERAND (0, RD, *ip, regno);
11769 INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno);
11773 gas_assert (!mips_opts.micromips);
11774 INSERT_OPERAND (0, RD, *ip, regno);
11775 INSERT_OPERAND (0, RT, *ip, regno);
11781 INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno);
11785 gas_assert (mips_opts.micromips);
11786 INSERT_OPERAND (1, RS3, *ip, regno);
11790 /* This case exists because on the r3000 trunc
11791 expands into a macro which requires a gp
11792 register. On the r6000 or r4000 it is
11793 assembled into a single instruction which
11794 ignores the register. Thus the insn version
11795 is MIPS_ISA2 and uses 'x', and the macro
11796 version is MIPS_ISA1 and uses 't'. */
11800 /* This case is for the div instruction, which
11801 acts differently if the destination argument
11802 is $0. This only matches $0, and is checked
11803 outside the switch. */
11813 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
11817 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
11822 case 'O': /* MDMX alignment immediate constant. */
11823 gas_assert (!mips_opts.micromips);
11824 my_getExpression (&imm_expr, s);
11825 check_absolute_expr (ip, &imm_expr);
11826 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
11827 as_warn (_("Improper align amount (%ld), using low bits"),
11828 (long) imm_expr.X_add_number);
11829 INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number);
11830 imm_expr.X_op = O_absent;
11834 case 'Q': /* MDMX vector, element sel, or const. */
11837 /* MDMX Immediate. */
11838 gas_assert (!mips_opts.micromips);
11839 my_getExpression (&imm_expr, s);
11840 check_absolute_expr (ip, &imm_expr);
11841 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
11842 as_warn (_("Invalid MDMX Immediate (%ld)"),
11843 (long) imm_expr.X_add_number);
11844 INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number);
11845 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
11846 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
11848 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
11849 imm_expr.X_op = O_absent;
11853 /* Not MDMX Immediate. Fall through. */
11854 case 'X': /* MDMX destination register. */
11855 case 'Y': /* MDMX source register. */
11856 case 'Z': /* MDMX target register. */
11859 gas_assert (!mips_opts.micromips);
11860 case 'D': /* Floating point destination register. */
11861 case 'S': /* Floating point source register. */
11862 case 'T': /* Floating point target register. */
11863 case 'R': /* Floating point source register. */
11867 || (mips_opts.ase_mdmx
11868 && (ip->insn_mo->pinfo & FP_D)
11869 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
11870 | INSN_COPROC_MEMORY_DELAY
11871 | INSN_LOAD_COPROC_DELAY
11872 | INSN_LOAD_MEMORY_DELAY
11873 | INSN_STORE_MEMORY))))
11874 rtype |= RTYPE_VEC;
11876 if (reg_lookup (&s, rtype, ®no))
11878 if ((regno & 1) != 0
11880 && !mips_oddfpreg_ok (ip->insn_mo, argnum))
11881 as_warn (_("Float register should be even, was %d"),
11889 if (c == 'V' || c == 'W')
11900 INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno);
11906 INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno);
11910 /* This is like 'Z', but also needs to fix the MDMX
11911 vector/scalar select bits. Note that the
11912 scalar immediate case is handled above. */
11915 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
11916 int max_el = (is_qh ? 3 : 7);
11918 my_getExpression(&imm_expr, s);
11919 check_absolute_expr (ip, &imm_expr);
11921 if (imm_expr.X_add_number > max_el)
11922 as_bad (_("Bad element selector %ld"),
11923 (long) imm_expr.X_add_number);
11924 imm_expr.X_add_number &= max_el;
11925 ip->insn_opcode |= (imm_expr.X_add_number
11928 imm_expr.X_op = O_absent;
11930 as_warn (_("Expecting ']' found '%s'"), s);
11936 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
11937 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
11940 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
11943 /* Fall through. */
11947 INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno);
11951 INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno);
11961 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
11965 INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno);
11971 my_getExpression (&imm_expr, s);
11972 if (imm_expr.X_op != O_big
11973 && imm_expr.X_op != O_constant)
11974 insn_error = _("absolute expression required");
11975 if (HAVE_32BIT_GPRS)
11976 normalize_constant_expr (&imm_expr);
11981 my_getExpression (&offset_expr, s);
11982 normalize_address_expr (&offset_expr);
11983 *imm_reloc = BFD_RELOC_32;
11996 unsigned char temp[8];
11998 unsigned int length;
12003 /* These only appear as the last operand in an
12004 instruction, and every instruction that accepts
12005 them in any variant accepts them in all variants.
12006 This means we don't have to worry about backing out
12007 any changes if the instruction does not match.
12009 The difference between them is the size of the
12010 floating point constant and where it goes. For 'F'
12011 and 'L' the constant is 64 bits; for 'f' and 'l' it
12012 is 32 bits. Where the constant is placed is based
12013 on how the MIPS assembler does things:
12016 f -- immediate value
12019 The .lit4 and .lit8 sections are only used if
12020 permitted by the -G argument.
12022 The code below needs to know whether the target register
12023 is 32 or 64 bits wide. It relies on the fact 'f' and
12024 'F' are used with GPR-based instructions and 'l' and
12025 'L' are used with FPR-based instructions. */
12027 f64 = *args == 'F' || *args == 'L';
12028 using_gprs = *args == 'F' || *args == 'f';
12030 save_in = input_line_pointer;
12031 input_line_pointer = s;
12032 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
12034 s = input_line_pointer;
12035 input_line_pointer = save_in;
12036 if (err != NULL && *err != '\0')
12038 as_bad (_("Bad floating point constant: %s"), err);
12039 memset (temp, '\0', sizeof temp);
12040 length = f64 ? 8 : 4;
12043 gas_assert (length == (unsigned) (f64 ? 8 : 4));
12047 && (g_switch_value < 4
12048 || (temp[0] == 0 && temp[1] == 0)
12049 || (temp[2] == 0 && temp[3] == 0))))
12051 imm_expr.X_op = O_constant;
12052 if (!target_big_endian)
12053 imm_expr.X_add_number = bfd_getl32 (temp);
12055 imm_expr.X_add_number = bfd_getb32 (temp);
12057 else if (length > 4
12058 && !mips_disable_float_construction
12059 /* Constants can only be constructed in GPRs and
12060 copied to FPRs if the GPRs are at least as wide
12061 as the FPRs. Force the constant into memory if
12062 we are using 64-bit FPRs but the GPRs are only
12065 || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
12066 && ((temp[0] == 0 && temp[1] == 0)
12067 || (temp[2] == 0 && temp[3] == 0))
12068 && ((temp[4] == 0 && temp[5] == 0)
12069 || (temp[6] == 0 && temp[7] == 0)))
12071 /* The value is simple enough to load with a couple of
12072 instructions. If using 32-bit registers, set
12073 imm_expr to the high order 32 bits and offset_expr to
12074 the low order 32 bits. Otherwise, set imm_expr to
12075 the entire 64 bit constant. */
12076 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
12078 imm_expr.X_op = O_constant;
12079 offset_expr.X_op = O_constant;
12080 if (!target_big_endian)
12082 imm_expr.X_add_number = bfd_getl32 (temp + 4);
12083 offset_expr.X_add_number = bfd_getl32 (temp);
12087 imm_expr.X_add_number = bfd_getb32 (temp);
12088 offset_expr.X_add_number = bfd_getb32 (temp + 4);
12090 if (offset_expr.X_add_number == 0)
12091 offset_expr.X_op = O_absent;
12093 else if (sizeof (imm_expr.X_add_number) > 4)
12095 imm_expr.X_op = O_constant;
12096 if (!target_big_endian)
12097 imm_expr.X_add_number = bfd_getl64 (temp);
12099 imm_expr.X_add_number = bfd_getb64 (temp);
12103 imm_expr.X_op = O_big;
12104 imm_expr.X_add_number = 4;
12105 if (!target_big_endian)
12107 generic_bignum[0] = bfd_getl16 (temp);
12108 generic_bignum[1] = bfd_getl16 (temp + 2);
12109 generic_bignum[2] = bfd_getl16 (temp + 4);
12110 generic_bignum[3] = bfd_getl16 (temp + 6);
12114 generic_bignum[0] = bfd_getb16 (temp + 6);
12115 generic_bignum[1] = bfd_getb16 (temp + 4);
12116 generic_bignum[2] = bfd_getb16 (temp + 2);
12117 generic_bignum[3] = bfd_getb16 (temp);
12123 const char *newname;
12126 /* Switch to the right section. */
12128 subseg = now_subseg;
12131 default: /* unused default case avoids warnings. */
12133 newname = RDATA_SECTION_NAME;
12134 if (g_switch_value >= 8)
12138 newname = RDATA_SECTION_NAME;
12141 gas_assert (g_switch_value >= 4);
12145 new_seg = subseg_new (newname, (subsegT) 0);
12147 bfd_set_section_flags (stdoutput, new_seg,
12152 frag_align (*args == 'l' ? 2 : 3, 0, 0);
12153 if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0)
12154 record_alignment (new_seg, 4);
12156 record_alignment (new_seg, *args == 'l' ? 2 : 3);
12157 if (seg == now_seg)
12158 as_bad (_("Can't use floating point insn in this section"));
12160 /* Set the argument to the current address in the
12162 offset_expr.X_op = O_symbol;
12163 offset_expr.X_add_symbol = symbol_temp_new_now ();
12164 offset_expr.X_add_number = 0;
12166 /* Put the floating point number into the section. */
12167 p = frag_more ((int) length);
12168 memcpy (p, temp, length);
12170 /* Switch back to the original section. */
12171 subseg_set (seg, subseg);
12176 case 'i': /* 16-bit unsigned immediate. */
12177 case 'j': /* 16-bit signed immediate. */
12178 *imm_reloc = BFD_RELOC_LO16;
12179 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
12182 offsetT minval, maxval;
12184 more = (insn + 1 < past
12185 && strcmp (insn->name, insn[1].name) == 0);
12187 /* If the expression was written as an unsigned number,
12188 only treat it as signed if there are no more
12192 && sizeof (imm_expr.X_add_number) <= 4
12193 && imm_expr.X_op == O_constant
12194 && imm_expr.X_add_number < 0
12195 && imm_expr.X_unsigned
12196 && HAVE_64BIT_GPRS)
12199 /* For compatibility with older assemblers, we accept
12200 0x8000-0xffff as signed 16-bit numbers when only
12201 signed numbers are allowed. */
12203 minval = 0, maxval = 0xffff;
12205 minval = -0x8000, maxval = 0x7fff;
12207 minval = -0x8000, maxval = 0xffff;
12209 if (imm_expr.X_op != O_constant
12210 || imm_expr.X_add_number < minval
12211 || imm_expr.X_add_number > maxval)
12215 if (imm_expr.X_op == O_constant
12216 || imm_expr.X_op == O_big)
12217 as_bad (_("Expression out of range"));
12223 case 'o': /* 16-bit offset. */
12224 offset_reloc[0] = BFD_RELOC_LO16;
12225 offset_reloc[1] = BFD_RELOC_UNUSED;
12226 offset_reloc[2] = BFD_RELOC_UNUSED;
12228 /* Check whether there is only a single bracketed expression
12229 left. If so, it must be the base register and the
12230 constant must be zero. */
12231 if (*s == '(' && strchr (s + 1, '(') == 0)
12233 offset_expr.X_op = O_constant;
12234 offset_expr.X_add_number = 0;
12238 /* If this value won't fit into a 16 bit offset, then go
12239 find a macro that will generate the 32 bit offset
12241 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
12242 && (offset_expr.X_op != O_constant
12243 || offset_expr.X_add_number >= 0x8000
12244 || offset_expr.X_add_number < -0x8000))
12250 case 'p': /* PC-relative offset. */
12251 *offset_reloc = BFD_RELOC_16_PCREL_S2;
12252 my_getExpression (&offset_expr, s);
12256 case 'u': /* Upper 16 bits. */
12257 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
12258 && imm_expr.X_op == O_constant
12259 && (imm_expr.X_add_number < 0
12260 || imm_expr.X_add_number >= 0x10000))
12261 as_bad (_("lui expression (%lu) not in range 0..65535"),
12262 (unsigned long) imm_expr.X_add_number);
12266 case 'a': /* 26-bit address. */
12267 *offset_reloc = BFD_RELOC_MIPS_JMP;
12268 my_getExpression (&offset_expr, s);
12272 case 'N': /* 3-bit branch condition code. */
12273 case 'M': /* 3-bit compare condition code. */
12275 if (ip->insn_mo->pinfo & (FP_D | FP_S))
12276 rtype |= RTYPE_FCC;
12277 if (!reg_lookup (&s, rtype, ®no))
12279 if ((strcmp (str + strlen (str) - 3, ".ps") == 0
12280 || strcmp (str + strlen (str) - 5, "any2f") == 0
12281 || strcmp (str + strlen (str) - 5, "any2t") == 0)
12282 && (regno & 1) != 0)
12283 as_warn (_("Condition code register should be even for %s, "
12286 if ((strcmp (str + strlen (str) - 5, "any4f") == 0
12287 || strcmp (str + strlen (str) - 5, "any4t") == 0)
12288 && (regno & 3) != 0)
12289 as_warn (_("Condition code register should be 0 or 4 for %s, "
12293 INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno);
12295 INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno);
12299 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
12310 while (ISDIGIT (*s));
12313 c = 8; /* Invalid sel value. */
12316 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
12317 INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c);
12321 gas_assert (!mips_opts.micromips);
12322 /* Must be at least one digit. */
12323 my_getExpression (&imm_expr, s);
12324 check_absolute_expr (ip, &imm_expr);
12326 if ((unsigned long) imm_expr.X_add_number
12327 > (unsigned long) OP_MASK_VECBYTE)
12329 as_bad (_("bad byte vector index (%ld)"),
12330 (long) imm_expr.X_add_number);
12331 imm_expr.X_add_number = 0;
12334 INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number);
12335 imm_expr.X_op = O_absent;
12340 gas_assert (!mips_opts.micromips);
12341 my_getExpression (&imm_expr, s);
12342 check_absolute_expr (ip, &imm_expr);
12344 if ((unsigned long) imm_expr.X_add_number
12345 > (unsigned long) OP_MASK_VECALIGN)
12347 as_bad (_("bad byte vector index (%ld)"),
12348 (long) imm_expr.X_add_number);
12349 imm_expr.X_add_number = 0;
12352 INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number);
12353 imm_expr.X_op = O_absent;
12357 case 'm': /* Opcode extension character. */
12358 gas_assert (mips_opts.micromips);
12363 if (strncmp (s, "$pc", 3) == 0)
12391 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
12392 if (regno == AT && mips_opts.at)
12394 if (mips_opts.at == ATREG)
12395 as_warn (_("Used $at without \".set noat\""));
12397 as_warn (_("Used $%u with \".set at=$%u\""),
12398 regno, mips_opts.at);
12404 gas_assert (args[1] == ',');
12410 gas_assert (args[1] == ',');
12412 continue; /* Nothing to do. */
12418 if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4))
12420 if (regno == lastregno)
12423 = _("Source and destination must be different");
12426 if (regno == 31 && lastregno == 0xffffffff)
12429 = _("A destination register must be supplied");
12440 gas_assert (args[1] == ',');
12447 gas_assert (args[1] == ',');
12450 continue; /* Nothing to do. */
12454 /* Make sure regno is the same as lastregno. */
12455 if (c == 't' && regno != lastregno)
12458 /* Make sure regno is the same as destregno. */
12459 if (c == 'x' && regno != destregno)
12462 /* We need to save regno, before regno maps to the
12463 microMIPS register encoding. */
12473 regno = ILLEGAL_REG;
12477 regno = mips32_to_micromips_reg_b_map[regno];
12481 regno = mips32_to_micromips_reg_c_map[regno];
12485 regno = mips32_to_micromips_reg_d_map[regno];
12489 regno = mips32_to_micromips_reg_e_map[regno];
12493 regno = mips32_to_micromips_reg_f_map[regno];
12497 regno = mips32_to_micromips_reg_g_map[regno];
12501 regno = mips32_to_micromips_reg_h_map[regno];
12505 switch (EXTRACT_OPERAND (1, MI, *ip))
12510 else if (regno == 22)
12512 else if (regno == 5)
12514 else if (regno == 6)
12516 else if (regno == 7)
12519 regno = ILLEGAL_REG;
12525 else if (regno == 7)
12528 regno = ILLEGAL_REG;
12535 regno = ILLEGAL_REG;
12539 regno = ILLEGAL_REG;
12545 regno = mips32_to_micromips_reg_l_map[regno];
12549 regno = mips32_to_micromips_reg_m_map[regno];
12553 regno = mips32_to_micromips_reg_n_map[regno];
12557 regno = mips32_to_micromips_reg_q_map[regno];
12562 regno = ILLEGAL_REG;
12567 regno = ILLEGAL_REG;
12572 regno = ILLEGAL_REG;
12575 case 'j': /* Do nothing. */
12585 if (regno == ILLEGAL_REG)
12591 INSERT_OPERAND (1, MB, *ip, regno);
12595 INSERT_OPERAND (1, MC, *ip, regno);
12599 INSERT_OPERAND (1, MD, *ip, regno);
12603 INSERT_OPERAND (1, ME, *ip, regno);
12607 INSERT_OPERAND (1, MF, *ip, regno);
12611 INSERT_OPERAND (1, MG, *ip, regno);
12615 INSERT_OPERAND (1, MH, *ip, regno);
12619 INSERT_OPERAND (1, MI, *ip, regno);
12623 INSERT_OPERAND (1, MJ, *ip, regno);
12627 INSERT_OPERAND (1, ML, *ip, regno);
12631 INSERT_OPERAND (1, MM, *ip, regno);
12635 INSERT_OPERAND (1, MN, *ip, regno);
12639 INSERT_OPERAND (1, MP, *ip, regno);
12643 INSERT_OPERAND (1, MQ, *ip, regno);
12646 case 'a': /* Do nothing. */
12647 case 's': /* Do nothing. */
12648 case 't': /* Do nothing. */
12649 case 'x': /* Do nothing. */
12650 case 'y': /* Do nothing. */
12651 case 'z': /* Do nothing. */
12661 bfd_reloc_code_real_type r[3];
12665 /* Check whether there is only a single bracketed
12666 expression left. If so, it must be the base register
12667 and the constant must be zero. */
12668 if (*s == '(' && strchr (s + 1, '(') == 0)
12670 INSERT_OPERAND (1, IMMA, *ip, 0);
12674 if (my_getSmallExpression (&ep, r, s) > 0
12675 || !expr_const_in_range (&ep, -64, 64, 2))
12678 imm = ep.X_add_number >> 2;
12679 INSERT_OPERAND (1, IMMA, *ip, imm);
12686 bfd_reloc_code_real_type r[3];
12690 if (my_getSmallExpression (&ep, r, s) > 0
12691 || ep.X_op != O_constant)
12694 for (imm = 0; imm < 8; imm++)
12695 if (micromips_imm_b_map[imm] == ep.X_add_number)
12700 INSERT_OPERAND (1, IMMB, *ip, imm);
12707 bfd_reloc_code_real_type r[3];
12711 if (my_getSmallExpression (&ep, r, s) > 0
12712 || ep.X_op != O_constant)
12715 for (imm = 0; imm < 16; imm++)
12716 if (micromips_imm_c_map[imm] == ep.X_add_number)
12721 INSERT_OPERAND (1, IMMC, *ip, imm);
12726 case 'D': /* pc relative offset */
12727 case 'E': /* pc relative offset */
12728 my_getExpression (&offset_expr, s);
12729 if (offset_expr.X_op == O_register)
12732 if (!forced_insn_length)
12733 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
12735 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
12737 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
12743 bfd_reloc_code_real_type r[3];
12747 if (my_getSmallExpression (&ep, r, s) > 0
12748 || !expr_const_in_range (&ep, 0, 16, 0))
12751 imm = ep.X_add_number;
12752 INSERT_OPERAND (1, IMMF, *ip, imm);
12759 bfd_reloc_code_real_type r[3];
12763 /* Check whether there is only a single bracketed
12764 expression left. If so, it must be the base register
12765 and the constant must be zero. */
12766 if (*s == '(' && strchr (s + 1, '(') == 0)
12768 INSERT_OPERAND (1, IMMG, *ip, 0);
12772 if (my_getSmallExpression (&ep, r, s) > 0
12773 || !expr_const_in_range (&ep, -1, 15, 0))
12776 imm = ep.X_add_number & 15;
12777 INSERT_OPERAND (1, IMMG, *ip, imm);
12784 bfd_reloc_code_real_type r[3];
12788 /* Check whether there is only a single bracketed
12789 expression left. If so, it must be the base register
12790 and the constant must be zero. */
12791 if (*s == '(' && strchr (s + 1, '(') == 0)
12793 INSERT_OPERAND (1, IMMH, *ip, 0);
12797 if (my_getSmallExpression (&ep, r, s) > 0
12798 || !expr_const_in_range (&ep, 0, 16, 1))
12801 imm = ep.X_add_number >> 1;
12802 INSERT_OPERAND (1, IMMH, *ip, imm);
12809 bfd_reloc_code_real_type r[3];
12813 if (my_getSmallExpression (&ep, r, s) > 0
12814 || !expr_const_in_range (&ep, -1, 127, 0))
12817 imm = ep.X_add_number & 127;
12818 INSERT_OPERAND (1, IMMI, *ip, imm);
12825 bfd_reloc_code_real_type r[3];
12829 /* Check whether there is only a single bracketed
12830 expression left. If so, it must be the base register
12831 and the constant must be zero. */
12832 if (*s == '(' && strchr (s + 1, '(') == 0)
12834 INSERT_OPERAND (1, IMMJ, *ip, 0);
12838 if (my_getSmallExpression (&ep, r, s) > 0
12839 || !expr_const_in_range (&ep, 0, 16, 2))
12842 imm = ep.X_add_number >> 2;
12843 INSERT_OPERAND (1, IMMJ, *ip, imm);
12850 bfd_reloc_code_real_type r[3];
12854 /* Check whether there is only a single bracketed
12855 expression left. If so, it must be the base register
12856 and the constant must be zero. */
12857 if (*s == '(' && strchr (s + 1, '(') == 0)
12859 INSERT_OPERAND (1, IMML, *ip, 0);
12863 if (my_getSmallExpression (&ep, r, s) > 0
12864 || !expr_const_in_range (&ep, 0, 16, 0))
12867 imm = ep.X_add_number;
12868 INSERT_OPERAND (1, IMML, *ip, imm);
12875 bfd_reloc_code_real_type r[3];
12879 if (my_getSmallExpression (&ep, r, s) > 0
12880 || !expr_const_in_range (&ep, 1, 9, 0))
12883 imm = ep.X_add_number & 7;
12884 INSERT_OPERAND (1, IMMM, *ip, imm);
12889 case 'N': /* Register list for lwm and swm. */
12891 /* A comma-separated list of registers and/or
12892 dash-separated contiguous ranges including
12893 both ra and a set of one or more registers
12894 starting at s0 up to s3 which have to be
12901 and any permutations of these. */
12902 unsigned int reglist;
12905 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
12908 if ((reglist & 0xfff1ffff) != 0x80010000)
12911 reglist = (reglist >> 17) & 7;
12913 if ((reglist & -reglist) != reglist)
12916 imm = ffs (reglist) - 1;
12917 INSERT_OPERAND (1, IMMN, *ip, imm);
12921 case 'O': /* sdbbp 4-bit code. */
12923 bfd_reloc_code_real_type r[3];
12927 if (my_getSmallExpression (&ep, r, s) > 0
12928 || !expr_const_in_range (&ep, 0, 16, 0))
12931 imm = ep.X_add_number;
12932 INSERT_OPERAND (1, IMMO, *ip, imm);
12939 bfd_reloc_code_real_type r[3];
12943 if (my_getSmallExpression (&ep, r, s) > 0
12944 || !expr_const_in_range (&ep, 0, 32, 2))
12947 imm = ep.X_add_number >> 2;
12948 INSERT_OPERAND (1, IMMP, *ip, imm);
12955 bfd_reloc_code_real_type r[3];
12959 if (my_getSmallExpression (&ep, r, s) > 0
12960 || !expr_const_in_range (&ep, -0x400000, 0x400000, 2))
12963 imm = ep.X_add_number >> 2;
12964 INSERT_OPERAND (1, IMMQ, *ip, imm);
12971 bfd_reloc_code_real_type r[3];
12975 /* Check whether there is only a single bracketed
12976 expression left. If so, it must be the base register
12977 and the constant must be zero. */
12978 if (*s == '(' && strchr (s + 1, '(') == 0)
12980 INSERT_OPERAND (1, IMMU, *ip, 0);
12984 if (my_getSmallExpression (&ep, r, s) > 0
12985 || !expr_const_in_range (&ep, 0, 32, 2))
12988 imm = ep.X_add_number >> 2;
12989 INSERT_OPERAND (1, IMMU, *ip, imm);
12996 bfd_reloc_code_real_type r[3];
13000 if (my_getSmallExpression (&ep, r, s) > 0
13001 || !expr_const_in_range (&ep, 0, 64, 2))
13004 imm = ep.X_add_number >> 2;
13005 INSERT_OPERAND (1, IMMW, *ip, imm);
13012 bfd_reloc_code_real_type r[3];
13016 if (my_getSmallExpression (&ep, r, s) > 0
13017 || !expr_const_in_range (&ep, -8, 8, 0))
13020 imm = ep.X_add_number;
13021 INSERT_OPERAND (1, IMMX, *ip, imm);
13028 bfd_reloc_code_real_type r[3];
13032 if (my_getSmallExpression (&ep, r, s) > 0
13033 || expr_const_in_range (&ep, -2, 2, 2)
13034 || !expr_const_in_range (&ep, -258, 258, 2))
13037 imm = ep.X_add_number >> 2;
13038 imm = ((imm >> 1) & ~0xff) | (imm & 0xff);
13039 INSERT_OPERAND (1, IMMY, *ip, imm);
13046 bfd_reloc_code_real_type r[3];
13049 if (my_getSmallExpression (&ep, r, s) > 0
13050 || !expr_const_in_range (&ep, 0, 1, 0))
13057 as_bad (_("Internal error: bad microMIPS opcode "
13058 "(unknown extension operand type `m%c'): %s %s"),
13059 *args, insn->name, insn->args);
13060 /* Further processing is fruitless. */
13065 case 'n': /* Register list for 32-bit lwm and swm. */
13066 gas_assert (mips_opts.micromips);
13068 /* A comma-separated list of registers and/or
13069 dash-separated contiguous ranges including
13070 at least one of ra and a set of one or more
13071 registers starting at s0 up to s7 and then
13072 s8 which have to be consecutive, e.g.:
13080 and any permutations of these. */
13081 unsigned int reglist;
13085 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
13088 if ((reglist & 0x3f00ffff) != 0)
13091 ra = (reglist >> 27) & 0x10;
13092 reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
13094 if ((reglist & -reglist) != reglist)
13097 imm = (ffs (reglist) - 1) | ra;
13098 INSERT_OPERAND (1, RT, *ip, imm);
13099 imm_expr.X_op = O_absent;
13103 case '|': /* 4-bit trap code. */
13104 gas_assert (mips_opts.micromips);
13105 my_getExpression (&imm_expr, s);
13106 check_absolute_expr (ip, &imm_expr);
13107 if ((unsigned long) imm_expr.X_add_number
13108 > MICROMIPSOP_MASK_TRAP)
13109 as_bad (_("Trap code (%lu) for %s not in 0..15 range"),
13110 (unsigned long) imm_expr.X_add_number,
13111 ip->insn_mo->name);
13112 INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number);
13113 imm_expr.X_op = O_absent;
13118 as_bad (_("Bad char = '%c'\n"), *args);
13123 /* Args don't match. */
13125 insn_error = _("Illegal operands");
13126 if (insn + 1 < past && !strcmp (insn->name, insn[1].name))
13131 else if (wrong_delay_slot_insns && need_delay_slot_ok)
13133 gas_assert (firstinsn);
13134 need_delay_slot_ok = FALSE;
13143 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
13145 /* This routine assembles an instruction into its binary format when
13146 assembling for the mips16. As a side effect, it sets one of the
13147 global variables imm_reloc or offset_reloc to the type of relocation
13148 to do if one of the operands is an address expression. It also sets
13149 forced_insn_length to the resulting instruction size in bytes if the
13150 user explicitly requested a small or extended instruction. */
13153 mips16_ip (char *str, struct mips_cl_insn *ip)
13157 struct mips_opcode *insn;
13159 unsigned int regno;
13160 unsigned int lastregno = 0;
13166 forced_insn_length = 0;
13168 for (s = str; ISLOWER (*s); ++s)
13180 if (s[1] == 't' && s[2] == ' ')
13183 forced_insn_length = 2;
13187 else if (s[1] == 'e' && s[2] == ' ')
13190 forced_insn_length = 4;
13194 /* Fall through. */
13196 insn_error = _("unknown opcode");
13200 if (mips_opts.noautoextend && !forced_insn_length)
13201 forced_insn_length = 2;
13203 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
13205 insn_error = _("unrecognized opcode");
13214 gas_assert (strcmp (insn->name, str) == 0);
13216 ok = is_opcode_valid_16 (insn);
13219 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
13220 && strcmp (insn->name, insn[1].name) == 0)
13229 static char buf[100];
13231 _("opcode not supported on this processor: %s (%s)"),
13232 mips_cpu_info_from_arch (mips_opts.arch)->name,
13233 mips_cpu_info_from_isa (mips_opts.isa)->name);
13240 create_insn (ip, insn);
13241 imm_expr.X_op = O_absent;
13242 imm_reloc[0] = BFD_RELOC_UNUSED;
13243 imm_reloc[1] = BFD_RELOC_UNUSED;
13244 imm_reloc[2] = BFD_RELOC_UNUSED;
13245 imm2_expr.X_op = O_absent;
13246 offset_expr.X_op = O_absent;
13247 offset_reloc[0] = BFD_RELOC_UNUSED;
13248 offset_reloc[1] = BFD_RELOC_UNUSED;
13249 offset_reloc[2] = BFD_RELOC_UNUSED;
13250 for (args = insn->args; 1; ++args)
13257 /* In this switch statement we call break if we did not find
13258 a match, continue if we did find a match, or return if we
13267 /* Stuff the immediate value in now, if we can. */
13268 if (imm_expr.X_op == O_constant
13269 && *imm_reloc > BFD_RELOC_UNUSED
13270 && *imm_reloc != BFD_RELOC_MIPS16_GOT16
13271 && *imm_reloc != BFD_RELOC_MIPS16_CALL16
13272 && insn->pinfo != INSN_MACRO)
13276 switch (*offset_reloc)
13278 case BFD_RELOC_MIPS16_HI16_S:
13279 tmp = (imm_expr.X_add_number + 0x8000) >> 16;
13282 case BFD_RELOC_MIPS16_HI16:
13283 tmp = imm_expr.X_add_number >> 16;
13286 case BFD_RELOC_MIPS16_LO16:
13287 tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff)
13291 case BFD_RELOC_UNUSED:
13292 tmp = imm_expr.X_add_number;
13298 *offset_reloc = BFD_RELOC_UNUSED;
13300 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
13301 tmp, TRUE, forced_insn_length == 2,
13302 forced_insn_length == 4, &ip->insn_opcode,
13303 &ip->use_extend, &ip->extend);
13304 imm_expr.X_op = O_absent;
13305 *imm_reloc = BFD_RELOC_UNUSED;
13319 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13322 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13338 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13340 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13344 /* Fall through. */
13355 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
13357 if (c == 'v' || c == 'w')
13360 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13362 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13373 if (c == 'v' || c == 'w')
13375 regno = mips16_to_32_reg_map[lastregno];
13389 regno = mips32_to_16_reg_map[regno];
13394 regno = ILLEGAL_REG;
13399 regno = ILLEGAL_REG;
13404 regno = ILLEGAL_REG;
13409 if (regno == AT && mips_opts.at)
13411 if (mips_opts.at == ATREG)
13412 as_warn (_("used $at without \".set noat\""));
13414 as_warn (_("used $%u with \".set at=$%u\""),
13415 regno, mips_opts.at);
13423 if (regno == ILLEGAL_REG)
13430 MIPS16_INSERT_OPERAND (RX, *ip, regno);
13434 MIPS16_INSERT_OPERAND (RY, *ip, regno);
13437 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
13440 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
13446 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
13449 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
13450 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
13460 if (strncmp (s, "$pc", 3) == 0)
13477 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
13480 if (imm_expr.X_op != O_constant)
13482 forced_insn_length = 4;
13483 ip->use_extend = TRUE;
13488 /* We need to relax this instruction. */
13489 *offset_reloc = *imm_reloc;
13490 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13495 *imm_reloc = BFD_RELOC_UNUSED;
13496 /* Fall through. */
13503 my_getExpression (&imm_expr, s);
13504 if (imm_expr.X_op == O_register)
13506 /* What we thought was an expression turned out to
13509 if (s[0] == '(' && args[1] == '(')
13511 /* It looks like the expression was omitted
13512 before a register indirection, which means
13513 that the expression is implicitly zero. We
13514 still set up imm_expr, so that we handle
13515 explicit extensions correctly. */
13516 imm_expr.X_op = O_constant;
13517 imm_expr.X_add_number = 0;
13518 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13525 /* We need to relax this instruction. */
13526 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13535 /* We use offset_reloc rather than imm_reloc for the PC
13536 relative operands. This lets macros with both
13537 immediate and address operands work correctly. */
13538 my_getExpression (&offset_expr, s);
13540 if (offset_expr.X_op == O_register)
13543 /* We need to relax this instruction. */
13544 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
13548 case '6': /* break code */
13549 my_getExpression (&imm_expr, s);
13550 check_absolute_expr (ip, &imm_expr);
13551 if ((unsigned long) imm_expr.X_add_number > 63)
13552 as_warn (_("Invalid value for `%s' (%lu)"),
13554 (unsigned long) imm_expr.X_add_number);
13555 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
13556 imm_expr.X_op = O_absent;
13560 case 'a': /* 26 bit address */
13561 my_getExpression (&offset_expr, s);
13563 *offset_reloc = BFD_RELOC_MIPS16_JMP;
13564 ip->insn_opcode <<= 16;
13567 case 'l': /* register list for entry macro */
13568 case 'L': /* register list for exit macro */
13578 unsigned int freg, reg1, reg2;
13580 while (*s == ' ' || *s == ',')
13582 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
13584 else if (reg_lookup (&s, RTYPE_FPU, ®1))
13588 as_bad (_("can't parse register list"));
13598 if (!reg_lookup (&s, freg ? RTYPE_FPU
13599 : (RTYPE_GP | RTYPE_NUM), ®2))
13601 as_bad (_("invalid register list"));
13605 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
13607 mask &= ~ (7 << 3);
13610 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
13612 mask &= ~ (7 << 3);
13615 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
13616 mask |= (reg2 - 3) << 3;
13617 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
13618 mask |= (reg2 - 15) << 1;
13619 else if (reg1 == RA && reg2 == RA)
13623 as_bad (_("invalid register list"));
13627 /* The mask is filled in in the opcode table for the
13628 benefit of the disassembler. We remove it before
13629 applying the actual mask. */
13630 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
13631 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
13635 case 'm': /* Register list for save insn. */
13636 case 'M': /* Register list for restore insn. */
13639 int framesz = 0, seen_framesz = 0;
13640 int nargs = 0, statics = 0, sregs = 0;
13644 unsigned int reg1, reg2;
13646 SKIP_SPACE_TABS (s);
13649 SKIP_SPACE_TABS (s);
13651 my_getExpression (&imm_expr, s);
13652 if (imm_expr.X_op == O_constant)
13654 /* Handle the frame size. */
13657 as_bad (_("more than one frame size in list"));
13661 framesz = imm_expr.X_add_number;
13662 imm_expr.X_op = O_absent;
13667 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
13669 as_bad (_("can't parse register list"));
13681 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2)
13684 as_bad (_("can't parse register list"));
13689 while (reg1 <= reg2)
13691 if (reg1 >= 4 && reg1 <= 7)
13695 nargs |= 1 << (reg1 - 4);
13697 /* statics $a0-$a3 */
13698 statics |= 1 << (reg1 - 4);
13700 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
13703 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
13705 else if (reg1 == 31)
13707 /* Add $ra to insn. */
13712 as_bad (_("unexpected register in list"));
13720 /* Encode args/statics combination. */
13721 if (nargs & statics)
13722 as_bad (_("arg/static registers overlap"));
13723 else if (nargs == 0xf)
13724 /* All $a0-$a3 are args. */
13725 opcode |= MIPS16_ALL_ARGS << 16;
13726 else if (statics == 0xf)
13727 /* All $a0-$a3 are statics. */
13728 opcode |= MIPS16_ALL_STATICS << 16;
13731 int narg = 0, nstat = 0;
13733 /* Count arg registers. */
13734 while (nargs & 0x1)
13740 as_bad (_("invalid arg register list"));
13742 /* Count static registers. */
13743 while (statics & 0x8)
13745 statics = (statics << 1) & 0xf;
13749 as_bad (_("invalid static register list"));
13751 /* Encode args/statics. */
13752 opcode |= ((narg << 2) | nstat) << 16;
13755 /* Encode $s0/$s1. */
13756 if (sregs & (1 << 0)) /* $s0 */
13758 if (sregs & (1 << 1)) /* $s1 */
13764 /* Count regs $s2-$s8. */
13772 as_bad (_("invalid static register list"));
13773 /* Encode $s2-$s8. */
13774 opcode |= nsreg << 24;
13777 /* Encode frame size. */
13779 as_bad (_("missing frame size"));
13780 else if ((framesz & 7) != 0 || framesz < 0
13781 || framesz > 0xff * 8)
13782 as_bad (_("invalid frame size"));
13783 else if (framesz != 128 || (opcode >> 16) != 0)
13786 opcode |= (((framesz & 0xf0) << 16)
13787 | (framesz & 0x0f));
13790 /* Finally build the instruction. */
13791 if ((opcode >> 16) != 0 || framesz == 0)
13793 ip->use_extend = TRUE;
13794 ip->extend = opcode >> 16;
13796 ip->insn_opcode |= opcode & 0x7f;
13800 case 'e': /* extend code */
13801 my_getExpression (&imm_expr, s);
13802 check_absolute_expr (ip, &imm_expr);
13803 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
13805 as_warn (_("Invalid value for `%s' (%lu)"),
13807 (unsigned long) imm_expr.X_add_number);
13808 imm_expr.X_add_number &= 0x7ff;
13810 ip->insn_opcode |= imm_expr.X_add_number;
13811 imm_expr.X_op = O_absent;
13821 /* Args don't match. */
13822 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
13823 strcmp (insn->name, insn[1].name) == 0)
13830 insn_error = _("illegal operands");
13836 /* This structure holds information we know about a mips16 immediate
13839 struct mips16_immed_operand
13841 /* The type code used in the argument string in the opcode table. */
13843 /* The number of bits in the short form of the opcode. */
13845 /* The number of bits in the extended form of the opcode. */
13847 /* The amount by which the short form is shifted when it is used;
13848 for example, the sw instruction has a shift count of 2. */
13850 /* The amount by which the short form is shifted when it is stored
13851 into the instruction code. */
13853 /* Non-zero if the short form is unsigned. */
13855 /* Non-zero if the extended form is unsigned. */
13857 /* Non-zero if the value is PC relative. */
13861 /* The mips16 immediate operand types. */
13863 static const struct mips16_immed_operand mips16_immed_operands[] =
13865 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
13866 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
13867 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
13868 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
13869 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
13870 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
13871 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
13872 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
13873 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
13874 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
13875 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
13876 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
13877 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
13878 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
13879 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
13880 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
13881 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
13882 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
13883 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
13884 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
13885 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
13888 #define MIPS16_NUM_IMMED \
13889 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
13891 /* Handle a mips16 instruction with an immediate value. This or's the
13892 small immediate value into *INSN. It sets *USE_EXTEND to indicate
13893 whether an extended value is needed; if one is needed, it sets
13894 *EXTEND to the value. The argument type is TYPE. The value is VAL.
13895 If SMALL is true, an unextended opcode was explicitly requested.
13896 If EXT is true, an extended opcode was explicitly requested. If
13897 WARN is true, warn if EXT does not match reality. */
13900 mips16_immed (char *file, unsigned int line, int type, offsetT val,
13901 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
13902 unsigned long *insn, bfd_boolean *use_extend,
13903 unsigned short *extend)
13905 const struct mips16_immed_operand *op;
13906 int mintiny, maxtiny;
13907 bfd_boolean needext;
13909 op = mips16_immed_operands;
13910 while (op->type != type)
13913 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
13918 if (type == '<' || type == '>' || type == '[' || type == ']')
13921 maxtiny = 1 << op->nbits;
13926 maxtiny = (1 << op->nbits) - 1;
13931 mintiny = - (1 << (op->nbits - 1));
13932 maxtiny = (1 << (op->nbits - 1)) - 1;
13935 /* Branch offsets have an implicit 0 in the lowest bit. */
13936 if (type == 'p' || type == 'q')
13939 if ((val & ((1 << op->shift) - 1)) != 0
13940 || val < (mintiny << op->shift)
13941 || val > (maxtiny << op->shift))
13946 if (warn && ext && ! needext)
13947 as_warn_where (file, line,
13948 _("extended operand requested but not required"));
13949 if (small && needext)
13950 as_bad_where (file, line, _("invalid unextended operand value"));
13952 if (small || (! ext && ! needext))
13956 *use_extend = FALSE;
13957 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
13958 insnval <<= op->op_shift;
13963 long minext, maxext;
13969 maxext = (1 << op->extbits) - 1;
13973 minext = - (1 << (op->extbits - 1));
13974 maxext = (1 << (op->extbits - 1)) - 1;
13976 if (val < minext || val > maxext)
13977 as_bad_where (file, line,
13978 _("operand value out of range for instruction"));
13980 *use_extend = TRUE;
13981 if (op->extbits == 16)
13983 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
13986 else if (op->extbits == 15)
13988 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
13993 extval = ((val & 0x1f) << 6) | (val & 0x20);
13997 *extend = (unsigned short) extval;
14002 struct percent_op_match
14005 bfd_reloc_code_real_type reloc;
14008 static const struct percent_op_match mips_percent_op[] =
14010 {"%lo", BFD_RELOC_LO16},
14012 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
14013 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
14014 {"%call16", BFD_RELOC_MIPS_CALL16},
14015 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
14016 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
14017 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
14018 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
14019 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
14020 {"%got", BFD_RELOC_MIPS_GOT16},
14021 {"%gp_rel", BFD_RELOC_GPREL16},
14022 {"%half", BFD_RELOC_16},
14023 {"%highest", BFD_RELOC_MIPS_HIGHEST},
14024 {"%higher", BFD_RELOC_MIPS_HIGHER},
14025 {"%neg", BFD_RELOC_MIPS_SUB},
14026 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
14027 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
14028 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
14029 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
14030 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
14031 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
14032 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
14034 {"%hi", BFD_RELOC_HI16_S}
14037 static const struct percent_op_match mips16_percent_op[] =
14039 {"%lo", BFD_RELOC_MIPS16_LO16},
14040 {"%gprel", BFD_RELOC_MIPS16_GPREL},
14041 {"%got", BFD_RELOC_MIPS16_GOT16},
14042 {"%call16", BFD_RELOC_MIPS16_CALL16},
14043 {"%hi", BFD_RELOC_MIPS16_HI16_S}
14047 /* Return true if *STR points to a relocation operator. When returning true,
14048 move *STR over the operator and store its relocation code in *RELOC.
14049 Leave both *STR and *RELOC alone when returning false. */
14052 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
14054 const struct percent_op_match *percent_op;
14057 if (mips_opts.mips16)
14059 percent_op = mips16_percent_op;
14060 limit = ARRAY_SIZE (mips16_percent_op);
14064 percent_op = mips_percent_op;
14065 limit = ARRAY_SIZE (mips_percent_op);
14068 for (i = 0; i < limit; i++)
14069 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
14071 int len = strlen (percent_op[i].str);
14073 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
14076 *str += strlen (percent_op[i].str);
14077 *reloc = percent_op[i].reloc;
14079 /* Check whether the output BFD supports this relocation.
14080 If not, issue an error and fall back on something safe. */
14081 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
14083 as_bad (_("relocation %s isn't supported by the current ABI"),
14084 percent_op[i].str);
14085 *reloc = BFD_RELOC_UNUSED;
14093 /* Parse string STR as a 16-bit relocatable operand. Store the
14094 expression in *EP and the relocations in the array starting
14095 at RELOC. Return the number of relocation operators used.
14097 On exit, EXPR_END points to the first character after the expression. */
14100 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
14103 bfd_reloc_code_real_type reversed_reloc[3];
14104 size_t reloc_index, i;
14105 int crux_depth, str_depth;
14108 /* Search for the start of the main expression, recoding relocations
14109 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14110 of the main expression and with CRUX_DEPTH containing the number
14111 of open brackets at that point. */
14118 crux_depth = str_depth;
14120 /* Skip over whitespace and brackets, keeping count of the number
14122 while (*str == ' ' || *str == '\t' || *str == '(')
14127 && reloc_index < (HAVE_NEWABI ? 3 : 1)
14128 && parse_relocation (&str, &reversed_reloc[reloc_index]));
14130 my_getExpression (ep, crux);
14133 /* Match every open bracket. */
14134 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
14138 if (crux_depth > 0)
14139 as_bad (_("unclosed '('"));
14143 if (reloc_index != 0)
14145 prev_reloc_op_frag = frag_now;
14146 for (i = 0; i < reloc_index; i++)
14147 reloc[i] = reversed_reloc[reloc_index - 1 - i];
14150 return reloc_index;
14154 my_getExpression (expressionS *ep, char *str)
14158 save_in = input_line_pointer;
14159 input_line_pointer = str;
14161 expr_end = input_line_pointer;
14162 input_line_pointer = save_in;
14166 md_atof (int type, char *litP, int *sizeP)
14168 return ieee_md_atof (type, litP, sizeP, target_big_endian);
14172 md_number_to_chars (char *buf, valueT val, int n)
14174 if (target_big_endian)
14175 number_to_chars_bigendian (buf, val, n);
14177 number_to_chars_littleendian (buf, val, n);
14181 static int support_64bit_objects(void)
14183 const char **list, **l;
14186 list = bfd_target_list ();
14187 for (l = list; *l != NULL; l++)
14188 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
14189 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
14191 yes = (*l != NULL);
14195 #endif /* OBJ_ELF */
14197 const char *md_shortopts = "O::g::G:";
14201 OPTION_MARCH = OPTION_MD_BASE,
14223 OPTION_NO_SMARTMIPS,
14227 OPTION_NO_MICROMIPS,
14230 OPTION_COMPAT_ARCH_BASE,
14239 OPTION_M7000_HILO_FIX,
14240 OPTION_MNO_7000_HILO_FIX,
14243 OPTION_FIX_LOONGSON2F_JUMP,
14244 OPTION_NO_FIX_LOONGSON2F_JUMP,
14245 OPTION_FIX_LOONGSON2F_NOP,
14246 OPTION_NO_FIX_LOONGSON2F_NOP,
14248 OPTION_NO_FIX_VR4120,
14250 OPTION_NO_FIX_VR4130,
14251 OPTION_FIX_CN63XXP1,
14252 OPTION_NO_FIX_CN63XXP1,
14259 OPTION_CONSTRUCT_FLOATS,
14260 OPTION_NO_CONSTRUCT_FLOATS,
14263 OPTION_RELAX_BRANCH,
14264 OPTION_NO_RELAX_BRANCH,
14271 OPTION_SINGLE_FLOAT,
14272 OPTION_DOUBLE_FLOAT,
14275 OPTION_CALL_SHARED,
14276 OPTION_CALL_NONPIC,
14286 OPTION_MVXWORKS_PIC,
14287 #endif /* OBJ_ELF */
14291 struct option md_longopts[] =
14293 /* Options which specify architecture. */
14294 {"march", required_argument, NULL, OPTION_MARCH},
14295 {"mtune", required_argument, NULL, OPTION_MTUNE},
14296 {"mips0", no_argument, NULL, OPTION_MIPS1},
14297 {"mips1", no_argument, NULL, OPTION_MIPS1},
14298 {"mips2", no_argument, NULL, OPTION_MIPS2},
14299 {"mips3", no_argument, NULL, OPTION_MIPS3},
14300 {"mips4", no_argument, NULL, OPTION_MIPS4},
14301 {"mips5", no_argument, NULL, OPTION_MIPS5},
14302 {"mips32", no_argument, NULL, OPTION_MIPS32},
14303 {"mips64", no_argument, NULL, OPTION_MIPS64},
14304 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
14305 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
14307 /* Options which specify Application Specific Extensions (ASEs). */
14308 {"mips16", no_argument, NULL, OPTION_MIPS16},
14309 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
14310 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
14311 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
14312 {"mdmx", no_argument, NULL, OPTION_MDMX},
14313 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
14314 {"mdsp", no_argument, NULL, OPTION_DSP},
14315 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
14316 {"mmt", no_argument, NULL, OPTION_MT},
14317 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
14318 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
14319 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
14320 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
14321 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
14322 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
14323 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
14324 {"mmcu", no_argument, NULL, OPTION_MCU},
14325 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
14327 /* Old-style architecture options. Don't add more of these. */
14328 {"m4650", no_argument, NULL, OPTION_M4650},
14329 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
14330 {"m4010", no_argument, NULL, OPTION_M4010},
14331 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
14332 {"m4100", no_argument, NULL, OPTION_M4100},
14333 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
14334 {"m3900", no_argument, NULL, OPTION_M3900},
14335 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
14337 /* Options which enable bug fixes. */
14338 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
14339 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
14340 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
14341 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
14342 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
14343 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
14344 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
14345 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
14346 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
14347 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
14348 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
14349 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
14350 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
14351 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
14352 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
14354 /* Miscellaneous options. */
14355 {"trap", no_argument, NULL, OPTION_TRAP},
14356 {"no-break", no_argument, NULL, OPTION_TRAP},
14357 {"break", no_argument, NULL, OPTION_BREAK},
14358 {"no-trap", no_argument, NULL, OPTION_BREAK},
14359 {"EB", no_argument, NULL, OPTION_EB},
14360 {"EL", no_argument, NULL, OPTION_EL},
14361 {"mfp32", no_argument, NULL, OPTION_FP32},
14362 {"mgp32", no_argument, NULL, OPTION_GP32},
14363 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
14364 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
14365 {"mfp64", no_argument, NULL, OPTION_FP64},
14366 {"mgp64", no_argument, NULL, OPTION_GP64},
14367 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
14368 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
14369 {"mshared", no_argument, NULL, OPTION_MSHARED},
14370 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
14371 {"msym32", no_argument, NULL, OPTION_MSYM32},
14372 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
14373 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
14374 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
14375 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
14376 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
14378 /* Strictly speaking this next option is ELF specific,
14379 but we allow it for other ports as well in order to
14380 make testing easier. */
14381 {"32", no_argument, NULL, OPTION_32},
14383 /* ELF-specific options. */
14385 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
14386 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
14387 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
14388 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
14389 {"xgot", no_argument, NULL, OPTION_XGOT},
14390 {"mabi", required_argument, NULL, OPTION_MABI},
14391 {"n32", no_argument, NULL, OPTION_N32},
14392 {"64", no_argument, NULL, OPTION_64},
14393 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
14394 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
14395 {"mpdr", no_argument, NULL, OPTION_PDR},
14396 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
14397 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
14398 #endif /* OBJ_ELF */
14400 {NULL, no_argument, NULL, 0}
14402 size_t md_longopts_size = sizeof (md_longopts);
14404 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14405 NEW_VALUE. Warn if another value was already specified. Note:
14406 we have to defer parsing the -march and -mtune arguments in order
14407 to handle 'from-abi' correctly, since the ABI might be specified
14408 in a later argument. */
14411 mips_set_option_string (const char **string_ptr, const char *new_value)
14413 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
14414 as_warn (_("A different %s was already specified, is now %s"),
14415 string_ptr == &mips_arch_string ? "-march" : "-mtune",
14418 *string_ptr = new_value;
14422 md_parse_option (int c, char *arg)
14426 case OPTION_CONSTRUCT_FLOATS:
14427 mips_disable_float_construction = 0;
14430 case OPTION_NO_CONSTRUCT_FLOATS:
14431 mips_disable_float_construction = 1;
14443 target_big_endian = 1;
14447 target_big_endian = 0;
14453 else if (arg[0] == '0')
14455 else if (arg[0] == '1')
14465 mips_debug = atoi (arg);
14469 file_mips_isa = ISA_MIPS1;
14473 file_mips_isa = ISA_MIPS2;
14477 file_mips_isa = ISA_MIPS3;
14481 file_mips_isa = ISA_MIPS4;
14485 file_mips_isa = ISA_MIPS5;
14488 case OPTION_MIPS32:
14489 file_mips_isa = ISA_MIPS32;
14492 case OPTION_MIPS32R2:
14493 file_mips_isa = ISA_MIPS32R2;
14496 case OPTION_MIPS64R2:
14497 file_mips_isa = ISA_MIPS64R2;
14500 case OPTION_MIPS64:
14501 file_mips_isa = ISA_MIPS64;
14505 mips_set_option_string (&mips_tune_string, arg);
14509 mips_set_option_string (&mips_arch_string, arg);
14513 mips_set_option_string (&mips_arch_string, "4650");
14514 mips_set_option_string (&mips_tune_string, "4650");
14517 case OPTION_NO_M4650:
14521 mips_set_option_string (&mips_arch_string, "4010");
14522 mips_set_option_string (&mips_tune_string, "4010");
14525 case OPTION_NO_M4010:
14529 mips_set_option_string (&mips_arch_string, "4100");
14530 mips_set_option_string (&mips_tune_string, "4100");
14533 case OPTION_NO_M4100:
14537 mips_set_option_string (&mips_arch_string, "3900");
14538 mips_set_option_string (&mips_tune_string, "3900");
14541 case OPTION_NO_M3900:
14545 mips_opts.ase_mdmx = 1;
14548 case OPTION_NO_MDMX:
14549 mips_opts.ase_mdmx = 0;
14553 mips_opts.ase_dsp = 1;
14554 mips_opts.ase_dspr2 = 0;
14557 case OPTION_NO_DSP:
14558 mips_opts.ase_dsp = 0;
14559 mips_opts.ase_dspr2 = 0;
14563 mips_opts.ase_dspr2 = 1;
14564 mips_opts.ase_dsp = 1;
14567 case OPTION_NO_DSPR2:
14568 mips_opts.ase_dspr2 = 0;
14569 mips_opts.ase_dsp = 0;
14573 mips_opts.ase_mt = 1;
14577 mips_opts.ase_mt = 0;
14581 mips_opts.ase_mcu = 1;
14584 case OPTION_NO_MCU:
14585 mips_opts.ase_mcu = 0;
14588 case OPTION_MICROMIPS:
14589 if (mips_opts.mips16 == 1)
14591 as_bad (_("-mmicromips cannot be used with -mips16"));
14594 mips_opts.micromips = 1;
14595 mips_no_prev_insn ();
14598 case OPTION_NO_MICROMIPS:
14599 mips_opts.micromips = 0;
14600 mips_no_prev_insn ();
14603 case OPTION_MIPS16:
14604 if (mips_opts.micromips == 1)
14606 as_bad (_("-mips16 cannot be used with -micromips"));
14609 mips_opts.mips16 = 1;
14610 mips_no_prev_insn ();
14613 case OPTION_NO_MIPS16:
14614 mips_opts.mips16 = 0;
14615 mips_no_prev_insn ();
14618 case OPTION_MIPS3D:
14619 mips_opts.ase_mips3d = 1;
14622 case OPTION_NO_MIPS3D:
14623 mips_opts.ase_mips3d = 0;
14626 case OPTION_SMARTMIPS:
14627 mips_opts.ase_smartmips = 1;
14630 case OPTION_NO_SMARTMIPS:
14631 mips_opts.ase_smartmips = 0;
14634 case OPTION_FIX_24K:
14638 case OPTION_NO_FIX_24K:
14642 case OPTION_FIX_LOONGSON2F_JUMP:
14643 mips_fix_loongson2f_jump = TRUE;
14646 case OPTION_NO_FIX_LOONGSON2F_JUMP:
14647 mips_fix_loongson2f_jump = FALSE;
14650 case OPTION_FIX_LOONGSON2F_NOP:
14651 mips_fix_loongson2f_nop = TRUE;
14654 case OPTION_NO_FIX_LOONGSON2F_NOP:
14655 mips_fix_loongson2f_nop = FALSE;
14658 case OPTION_FIX_VR4120:
14659 mips_fix_vr4120 = 1;
14662 case OPTION_NO_FIX_VR4120:
14663 mips_fix_vr4120 = 0;
14666 case OPTION_FIX_VR4130:
14667 mips_fix_vr4130 = 1;
14670 case OPTION_NO_FIX_VR4130:
14671 mips_fix_vr4130 = 0;
14674 case OPTION_FIX_CN63XXP1:
14675 mips_fix_cn63xxp1 = TRUE;
14678 case OPTION_NO_FIX_CN63XXP1:
14679 mips_fix_cn63xxp1 = FALSE;
14682 case OPTION_RELAX_BRANCH:
14683 mips_relax_branch = 1;
14686 case OPTION_NO_RELAX_BRANCH:
14687 mips_relax_branch = 0;
14690 case OPTION_MSHARED:
14691 mips_in_shared = TRUE;
14694 case OPTION_MNO_SHARED:
14695 mips_in_shared = FALSE;
14698 case OPTION_MSYM32:
14699 mips_opts.sym32 = TRUE;
14702 case OPTION_MNO_SYM32:
14703 mips_opts.sym32 = FALSE;
14707 /* When generating ELF code, we permit -KPIC and -call_shared to
14708 select SVR4_PIC, and -non_shared to select no PIC. This is
14709 intended to be compatible with Irix 5. */
14710 case OPTION_CALL_SHARED:
14713 as_bad (_("-call_shared is supported only for ELF format"));
14716 mips_pic = SVR4_PIC;
14717 mips_abicalls = TRUE;
14720 case OPTION_CALL_NONPIC:
14723 as_bad (_("-call_nonpic is supported only for ELF format"));
14727 mips_abicalls = TRUE;
14730 case OPTION_NON_SHARED:
14733 as_bad (_("-non_shared is supported only for ELF format"));
14737 mips_abicalls = FALSE;
14740 /* The -xgot option tells the assembler to use 32 bit offsets
14741 when accessing the got in SVR4_PIC mode. It is for Irix
14746 #endif /* OBJ_ELF */
14749 g_switch_value = atoi (arg);
14753 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14757 mips_abi = O32_ABI;
14758 /* We silently ignore -32 for non-ELF targets. This greatly
14759 simplifies the construction of the MIPS GAS test cases. */
14766 as_bad (_("-n32 is supported for ELF format only"));
14769 mips_abi = N32_ABI;
14775 as_bad (_("-64 is supported for ELF format only"));
14778 mips_abi = N64_ABI;
14779 if (!support_64bit_objects())
14780 as_fatal (_("No compiled in support for 64 bit object file format"));
14782 #endif /* OBJ_ELF */
14785 file_mips_gp32 = 1;
14789 file_mips_gp32 = 0;
14793 file_mips_fp32 = 1;
14797 file_mips_fp32 = 0;
14800 case OPTION_SINGLE_FLOAT:
14801 file_mips_single_float = 1;
14804 case OPTION_DOUBLE_FLOAT:
14805 file_mips_single_float = 0;
14808 case OPTION_SOFT_FLOAT:
14809 file_mips_soft_float = 1;
14812 case OPTION_HARD_FLOAT:
14813 file_mips_soft_float = 0;
14820 as_bad (_("-mabi is supported for ELF format only"));
14823 if (strcmp (arg, "32") == 0)
14824 mips_abi = O32_ABI;
14825 else if (strcmp (arg, "o64") == 0)
14826 mips_abi = O64_ABI;
14827 else if (strcmp (arg, "n32") == 0)
14828 mips_abi = N32_ABI;
14829 else if (strcmp (arg, "64") == 0)
14831 mips_abi = N64_ABI;
14832 if (! support_64bit_objects())
14833 as_fatal (_("No compiled in support for 64 bit object file "
14836 else if (strcmp (arg, "eabi") == 0)
14837 mips_abi = EABI_ABI;
14840 as_fatal (_("invalid abi -mabi=%s"), arg);
14844 #endif /* OBJ_ELF */
14846 case OPTION_M7000_HILO_FIX:
14847 mips_7000_hilo_fix = TRUE;
14850 case OPTION_MNO_7000_HILO_FIX:
14851 mips_7000_hilo_fix = FALSE;
14855 case OPTION_MDEBUG:
14856 mips_flag_mdebug = TRUE;
14859 case OPTION_NO_MDEBUG:
14860 mips_flag_mdebug = FALSE;
14864 mips_flag_pdr = TRUE;
14867 case OPTION_NO_PDR:
14868 mips_flag_pdr = FALSE;
14871 case OPTION_MVXWORKS_PIC:
14872 mips_pic = VXWORKS_PIC;
14874 #endif /* OBJ_ELF */
14880 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
14885 /* Set up globals to generate code for the ISA or processor
14886 described by INFO. */
14889 mips_set_architecture (const struct mips_cpu_info *info)
14893 file_mips_arch = info->cpu;
14894 mips_opts.arch = info->cpu;
14895 mips_opts.isa = info->isa;
14900 /* Likewise for tuning. */
14903 mips_set_tune (const struct mips_cpu_info *info)
14906 mips_tune = info->cpu;
14911 mips_after_parse_args (void)
14913 const struct mips_cpu_info *arch_info = 0;
14914 const struct mips_cpu_info *tune_info = 0;
14916 /* GP relative stuff not working for PE */
14917 if (strncmp (TARGET_OS, "pe", 2) == 0)
14919 if (g_switch_seen && g_switch_value != 0)
14920 as_bad (_("-G not supported in this configuration."));
14921 g_switch_value = 0;
14924 if (mips_abi == NO_ABI)
14925 mips_abi = MIPS_DEFAULT_ABI;
14927 /* The following code determines the architecture and register size.
14928 Similar code was added to GCC 3.3 (see override_options() in
14929 config/mips/mips.c). The GAS and GCC code should be kept in sync
14930 as much as possible. */
14932 if (mips_arch_string != 0)
14933 arch_info = mips_parse_cpu ("-march", mips_arch_string);
14935 if (file_mips_isa != ISA_UNKNOWN)
14937 /* Handle -mipsN. At this point, file_mips_isa contains the
14938 ISA level specified by -mipsN, while arch_info->isa contains
14939 the -march selection (if any). */
14940 if (arch_info != 0)
14942 /* -march takes precedence over -mipsN, since it is more descriptive.
14943 There's no harm in specifying both as long as the ISA levels
14945 if (file_mips_isa != arch_info->isa)
14946 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
14947 mips_cpu_info_from_isa (file_mips_isa)->name,
14948 mips_cpu_info_from_isa (arch_info->isa)->name);
14951 arch_info = mips_cpu_info_from_isa (file_mips_isa);
14954 if (arch_info == 0)
14955 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
14957 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
14958 as_bad (_("-march=%s is not compatible with the selected ABI"),
14961 mips_set_architecture (arch_info);
14963 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
14964 if (mips_tune_string != 0)
14965 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
14967 if (tune_info == 0)
14968 mips_set_tune (arch_info);
14970 mips_set_tune (tune_info);
14972 if (file_mips_gp32 >= 0)
14974 /* The user specified the size of the integer registers. Make sure
14975 it agrees with the ABI and ISA. */
14976 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
14977 as_bad (_("-mgp64 used with a 32-bit processor"));
14978 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
14979 as_bad (_("-mgp32 used with a 64-bit ABI"));
14980 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
14981 as_bad (_("-mgp64 used with a 32-bit ABI"));
14985 /* Infer the integer register size from the ABI and processor.
14986 Restrict ourselves to 32-bit registers if that's all the
14987 processor has, or if the ABI cannot handle 64-bit registers. */
14988 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
14989 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
14992 switch (file_mips_fp32)
14996 /* No user specified float register size.
14997 ??? GAS treats single-float processors as though they had 64-bit
14998 float registers (although it complains when double-precision
14999 instructions are used). As things stand, saying they have 32-bit
15000 registers would lead to spurious "register must be even" messages.
15001 So here we assume float registers are never smaller than the
15003 if (file_mips_gp32 == 0)
15004 /* 64-bit integer registers implies 64-bit float registers. */
15005 file_mips_fp32 = 0;
15006 else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
15007 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
15008 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
15009 file_mips_fp32 = 0;
15011 /* 32-bit float registers. */
15012 file_mips_fp32 = 1;
15015 /* The user specified the size of the float registers. Check if it
15016 agrees with the ABI and ISA. */
15018 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
15019 as_bad (_("-mfp64 used with a 32-bit fpu"));
15020 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
15021 && !ISA_HAS_MXHC1 (mips_opts.isa))
15022 as_warn (_("-mfp64 used with a 32-bit ABI"));
15025 if (ABI_NEEDS_64BIT_REGS (mips_abi))
15026 as_warn (_("-mfp32 used with a 64-bit ABI"));
15030 /* End of GCC-shared inference code. */
15032 /* This flag is set when we have a 64-bit capable CPU but use only
15033 32-bit wide registers. Note that EABI does not use it. */
15034 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
15035 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
15036 || mips_abi == O32_ABI))
15037 mips_32bitmode = 1;
15039 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
15040 as_bad (_("trap exception not supported at ISA 1"));
15042 /* If the selected architecture includes support for ASEs, enable
15043 generation of code for them. */
15044 if (mips_opts.mips16 == -1)
15045 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
15046 if (mips_opts.micromips == -1)
15047 mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0;
15048 if (mips_opts.ase_mips3d == -1)
15049 mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
15050 && file_mips_fp32 == 0) ? 1 : 0;
15051 if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
15052 as_bad (_("-mfp32 used with -mips3d"));
15054 if (mips_opts.ase_mdmx == -1)
15055 mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
15056 && file_mips_fp32 == 0) ? 1 : 0;
15057 if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
15058 as_bad (_("-mfp32 used with -mdmx"));
15060 if (mips_opts.ase_smartmips == -1)
15061 mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
15062 if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
15063 as_warn (_("%s ISA does not support SmartMIPS"),
15064 mips_cpu_info_from_isa (mips_opts.isa)->name);
15066 if (mips_opts.ase_dsp == -1)
15067 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
15068 if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
15069 as_warn (_("%s ISA does not support DSP ASE"),
15070 mips_cpu_info_from_isa (mips_opts.isa)->name);
15072 if (mips_opts.ase_dspr2 == -1)
15074 mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
15075 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
15077 if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
15078 as_warn (_("%s ISA does not support DSP R2 ASE"),
15079 mips_cpu_info_from_isa (mips_opts.isa)->name);
15081 if (mips_opts.ase_mt == -1)
15082 mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
15083 if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
15084 as_warn (_("%s ISA does not support MT ASE"),
15085 mips_cpu_info_from_isa (mips_opts.isa)->name);
15087 if (mips_opts.ase_mcu == -1)
15088 mips_opts.ase_mcu = (arch_info->flags & MIPS_CPU_ASE_MCU) ? 1 : 0;
15089 if (mips_opts.ase_mcu && !ISA_SUPPORTS_MCU_ASE)
15090 as_warn (_("%s ISA does not support MCU ASE"),
15091 mips_cpu_info_from_isa (mips_opts.isa)->name);
15093 file_mips_isa = mips_opts.isa;
15094 file_ase_mips3d = mips_opts.ase_mips3d;
15095 file_ase_mdmx = mips_opts.ase_mdmx;
15096 file_ase_smartmips = mips_opts.ase_smartmips;
15097 file_ase_dsp = mips_opts.ase_dsp;
15098 file_ase_dspr2 = mips_opts.ase_dspr2;
15099 file_ase_mt = mips_opts.ase_mt;
15100 mips_opts.gp32 = file_mips_gp32;
15101 mips_opts.fp32 = file_mips_fp32;
15102 mips_opts.soft_float = file_mips_soft_float;
15103 mips_opts.single_float = file_mips_single_float;
15105 if (mips_flag_mdebug < 0)
15107 #ifdef OBJ_MAYBE_ECOFF
15108 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
15109 mips_flag_mdebug = 1;
15111 #endif /* OBJ_MAYBE_ECOFF */
15112 mips_flag_mdebug = 0;
15117 mips_init_after_args (void)
15119 /* initialize opcodes */
15120 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
15121 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
15125 md_pcrel_from (fixS *fixP)
15127 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
15128 switch (fixP->fx_r_type)
15130 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15131 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15132 /* Return the address of the delay slot. */
15135 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15136 case BFD_RELOC_MICROMIPS_JMP:
15137 case BFD_RELOC_16_PCREL_S2:
15138 case BFD_RELOC_MIPS_JMP:
15139 /* Return the address of the delay slot. */
15143 /* We have no relocation type for PC relative MIPS16 instructions. */
15144 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
15145 as_bad_where (fixP->fx_file, fixP->fx_line,
15146 _("PC relative MIPS16 instruction references a different section"));
15151 /* This is called before the symbol table is processed. In order to
15152 work with gcc when using mips-tfile, we must keep all local labels.
15153 However, in other cases, we want to discard them. If we were
15154 called with -g, but we didn't see any debugging information, it may
15155 mean that gcc is smuggling debugging information through to
15156 mips-tfile, in which case we must generate all local labels. */
15159 mips_frob_file_before_adjust (void)
15161 #ifndef NO_ECOFF_DEBUGGING
15162 if (ECOFF_DEBUGGING
15164 && ! ecoff_debugging_seen)
15165 flag_keep_locals = 1;
15169 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15170 the corresponding LO16 reloc. This is called before md_apply_fix and
15171 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15172 relocation operators.
15174 For our purposes, a %lo() expression matches a %got() or %hi()
15177 (a) it refers to the same symbol; and
15178 (b) the offset applied in the %lo() expression is no lower than
15179 the offset applied in the %got() or %hi().
15181 (b) allows us to cope with code like:
15184 lh $4,%lo(foo+2)($4)
15186 ...which is legal on RELA targets, and has a well-defined behaviour
15187 if the user knows that adding 2 to "foo" will not induce a carry to
15190 When several %lo()s match a particular %got() or %hi(), we use the
15191 following rules to distinguish them:
15193 (1) %lo()s with smaller offsets are a better match than %lo()s with
15196 (2) %lo()s with no matching %got() or %hi() are better than those
15197 that already have a matching %got() or %hi().
15199 (3) later %lo()s are better than earlier %lo()s.
15201 These rules are applied in order.
15203 (1) means, among other things, that %lo()s with identical offsets are
15204 chosen if they exist.
15206 (2) means that we won't associate several high-part relocations with
15207 the same low-part relocation unless there's no alternative. Having
15208 several high parts for the same low part is a GNU extension; this rule
15209 allows careful users to avoid it.
15211 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15212 with the last high-part relocation being at the front of the list.
15213 It therefore makes sense to choose the last matching low-part
15214 relocation, all other things being equal. It's also easier
15215 to code that way. */
15218 mips_frob_file (void)
15220 struct mips_hi_fixup *l;
15221 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
15223 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
15225 segment_info_type *seginfo;
15226 bfd_boolean matched_lo_p;
15227 fixS **hi_pos, **lo_pos, **pos;
15229 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
15231 /* If a GOT16 relocation turns out to be against a global symbol,
15232 there isn't supposed to be a matching LO. */
15233 if (got16_reloc_p (l->fixp->fx_r_type)
15234 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
15237 /* Check quickly whether the next fixup happens to be a matching %lo. */
15238 if (fixup_has_matching_lo_p (l->fixp))
15241 seginfo = seg_info (l->seg);
15243 /* Set HI_POS to the position of this relocation in the chain.
15244 Set LO_POS to the position of the chosen low-part relocation.
15245 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15246 relocation that matches an immediately-preceding high-part
15250 matched_lo_p = FALSE;
15251 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
15253 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
15255 if (*pos == l->fixp)
15258 if ((*pos)->fx_r_type == looking_for_rtype
15259 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
15260 && (*pos)->fx_offset >= l->fixp->fx_offset
15262 || (*pos)->fx_offset < (*lo_pos)->fx_offset
15264 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
15267 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
15268 && fixup_has_matching_lo_p (*pos));
15271 /* If we found a match, remove the high-part relocation from its
15272 current position and insert it before the low-part relocation.
15273 Make the offsets match so that fixup_has_matching_lo_p()
15276 We don't warn about unmatched high-part relocations since some
15277 versions of gcc have been known to emit dead "lui ...%hi(...)"
15279 if (lo_pos != NULL)
15281 l->fixp->fx_offset = (*lo_pos)->fx_offset;
15282 if (l->fixp->fx_next != *lo_pos)
15284 *hi_pos = l->fixp->fx_next;
15285 l->fixp->fx_next = *lo_pos;
15292 /* We may have combined relocations without symbols in the N32/N64 ABI.
15293 We have to prevent gas from dropping them. */
15296 mips_force_relocation (fixS *fixp)
15298 if (generic_force_reloc (fixp))
15301 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15302 so that the linker relaxation can update targets. */
15303 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15304 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15305 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
15309 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
15310 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
15311 || hi16_reloc_p (fixp->fx_r_type)
15312 || lo16_reloc_p (fixp->fx_r_type)))
15318 /* Apply a fixup to the object file. */
15321 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
15325 reloc_howto_type *howto;
15327 /* We ignore generic BFD relocations we don't know about. */
15328 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
15332 gas_assert (fixP->fx_size == 2
15333 || fixP->fx_size == 4
15334 || fixP->fx_r_type == BFD_RELOC_16
15335 || fixP->fx_r_type == BFD_RELOC_64
15336 || fixP->fx_r_type == BFD_RELOC_CTOR
15337 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
15338 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
15339 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
15340 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
15341 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
15343 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
15345 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
15346 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15347 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15348 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1);
15350 /* Don't treat parts of a composite relocation as done. There are two
15353 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15354 should nevertheless be emitted if the first part is.
15356 (2) In normal usage, composite relocations are never assembly-time
15357 constants. The easiest way of dealing with the pathological
15358 exceptions is to generate a relocation against STN_UNDEF and
15359 leave everything up to the linker. */
15360 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
15363 switch (fixP->fx_r_type)
15365 case BFD_RELOC_MIPS_TLS_GD:
15366 case BFD_RELOC_MIPS_TLS_LDM:
15367 case BFD_RELOC_MIPS_TLS_DTPREL32:
15368 case BFD_RELOC_MIPS_TLS_DTPREL64:
15369 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
15370 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
15371 case BFD_RELOC_MIPS_TLS_GOTTPREL:
15372 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
15373 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
15374 case BFD_RELOC_MICROMIPS_TLS_GD:
15375 case BFD_RELOC_MICROMIPS_TLS_LDM:
15376 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
15377 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
15378 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
15379 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
15380 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
15381 S_SET_THREAD_LOCAL (fixP->fx_addsy);
15384 case BFD_RELOC_MIPS_JMP:
15385 case BFD_RELOC_MIPS_SHIFT5:
15386 case BFD_RELOC_MIPS_SHIFT6:
15387 case BFD_RELOC_MIPS_GOT_DISP:
15388 case BFD_RELOC_MIPS_GOT_PAGE:
15389 case BFD_RELOC_MIPS_GOT_OFST:
15390 case BFD_RELOC_MIPS_SUB:
15391 case BFD_RELOC_MIPS_INSERT_A:
15392 case BFD_RELOC_MIPS_INSERT_B:
15393 case BFD_RELOC_MIPS_DELETE:
15394 case BFD_RELOC_MIPS_HIGHEST:
15395 case BFD_RELOC_MIPS_HIGHER:
15396 case BFD_RELOC_MIPS_SCN_DISP:
15397 case BFD_RELOC_MIPS_REL16:
15398 case BFD_RELOC_MIPS_RELGOT:
15399 case BFD_RELOC_MIPS_JALR:
15400 case BFD_RELOC_HI16:
15401 case BFD_RELOC_HI16_S:
15402 case BFD_RELOC_GPREL16:
15403 case BFD_RELOC_MIPS_LITERAL:
15404 case BFD_RELOC_MIPS_CALL16:
15405 case BFD_RELOC_MIPS_GOT16:
15406 case BFD_RELOC_GPREL32:
15407 case BFD_RELOC_MIPS_GOT_HI16:
15408 case BFD_RELOC_MIPS_GOT_LO16:
15409 case BFD_RELOC_MIPS_CALL_HI16:
15410 case BFD_RELOC_MIPS_CALL_LO16:
15411 case BFD_RELOC_MIPS16_GPREL:
15412 case BFD_RELOC_MIPS16_GOT16:
15413 case BFD_RELOC_MIPS16_CALL16:
15414 case BFD_RELOC_MIPS16_HI16:
15415 case BFD_RELOC_MIPS16_HI16_S:
15416 case BFD_RELOC_MIPS16_JMP:
15417 case BFD_RELOC_MICROMIPS_JMP:
15418 case BFD_RELOC_MICROMIPS_GOT_DISP:
15419 case BFD_RELOC_MICROMIPS_GOT_PAGE:
15420 case BFD_RELOC_MICROMIPS_GOT_OFST:
15421 case BFD_RELOC_MICROMIPS_SUB:
15422 case BFD_RELOC_MICROMIPS_HIGHEST:
15423 case BFD_RELOC_MICROMIPS_HIGHER:
15424 case BFD_RELOC_MICROMIPS_SCN_DISP:
15425 case BFD_RELOC_MICROMIPS_JALR:
15426 case BFD_RELOC_MICROMIPS_HI16:
15427 case BFD_RELOC_MICROMIPS_HI16_S:
15428 case BFD_RELOC_MICROMIPS_GPREL16:
15429 case BFD_RELOC_MICROMIPS_LITERAL:
15430 case BFD_RELOC_MICROMIPS_CALL16:
15431 case BFD_RELOC_MICROMIPS_GOT16:
15432 case BFD_RELOC_MICROMIPS_GOT_HI16:
15433 case BFD_RELOC_MICROMIPS_GOT_LO16:
15434 case BFD_RELOC_MICROMIPS_CALL_HI16:
15435 case BFD_RELOC_MICROMIPS_CALL_LO16:
15436 /* Nothing needed to do. The value comes from the reloc entry. */
15440 /* This is handled like BFD_RELOC_32, but we output a sign
15441 extended value if we are only 32 bits. */
15444 if (8 <= sizeof (valueT))
15445 md_number_to_chars ((char *) buf, *valP, 8);
15450 if ((*valP & 0x80000000) != 0)
15454 md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)),
15456 md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)),
15462 case BFD_RELOC_RVA:
15465 /* If we are deleting this reloc entry, we must fill in the
15466 value now. This can happen if we have a .word which is not
15467 resolved when it appears but is later defined. */
15469 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
15472 case BFD_RELOC_LO16:
15473 case BFD_RELOC_MIPS16_LO16:
15474 case BFD_RELOC_MICROMIPS_LO16:
15475 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
15476 may be safe to remove, but if so it's not obvious. */
15477 /* When handling an embedded PIC switch statement, we can wind
15478 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
15481 if (*valP + 0x8000 > 0xffff)
15482 as_bad_where (fixP->fx_file, fixP->fx_line,
15483 _("relocation overflow"));
15484 /* 32-bit microMIPS instructions are divided into two halfwords.
15485 Relocations always refer to the second halfword, regardless
15487 if (target_big_endian || fixP->fx_r_type == BFD_RELOC_MICROMIPS_LO16)
15489 md_number_to_chars ((char *) buf, *valP, 2);
15493 case BFD_RELOC_16_PCREL_S2:
15494 if ((*valP & 0x3) != 0)
15495 as_bad_where (fixP->fx_file, fixP->fx_line,
15496 _("Branch to misaligned address (%lx)"), (long) *valP);
15498 /* We need to save the bits in the instruction since fixup_segment()
15499 might be deleting the relocation entry (i.e., a branch within
15500 the current segment). */
15501 if (! fixP->fx_done)
15504 /* Update old instruction data. */
15505 if (target_big_endian)
15506 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
15508 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
15510 if (*valP + 0x20000 <= 0x3ffff)
15512 insn |= (*valP >> 2) & 0xffff;
15513 md_number_to_chars ((char *) buf, insn, 4);
15515 else if (mips_pic == NO_PIC
15517 && fixP->fx_frag->fr_address >= text_section->vma
15518 && (fixP->fx_frag->fr_address
15519 < text_section->vma + bfd_get_section_size (text_section))
15520 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
15521 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
15522 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
15524 /* The branch offset is too large. If this is an
15525 unconditional branch, and we are not generating PIC code,
15526 we can convert it to an absolute jump instruction. */
15527 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
15528 insn = 0x0c000000; /* jal */
15530 insn = 0x08000000; /* j */
15531 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
15533 fixP->fx_addsy = section_symbol (text_section);
15534 *valP += md_pcrel_from (fixP);
15535 md_number_to_chars ((char *) buf, insn, 4);
15539 /* If we got here, we have branch-relaxation disabled,
15540 and there's nothing we can do to fix this instruction
15541 without turning it into a longer sequence. */
15542 as_bad_where (fixP->fx_file, fixP->fx_line,
15543 _("Branch out of range"));
15547 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15548 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15549 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15550 /* We adjust the offset back to even. */
15551 if ((*valP & 0x1) != 0)
15554 if (! fixP->fx_done)
15557 /* Should never visit here, because we keep the relocation. */
15561 case BFD_RELOC_VTABLE_INHERIT:
15564 && !S_IS_DEFINED (fixP->fx_addsy)
15565 && !S_IS_WEAK (fixP->fx_addsy))
15566 S_SET_WEAK (fixP->fx_addsy);
15569 case BFD_RELOC_VTABLE_ENTRY:
15577 /* Remember value for tc_gen_reloc. */
15578 fixP->fx_addnumber = *valP;
15588 name = input_line_pointer;
15589 c = get_symbol_end ();
15590 p = (symbolS *) symbol_find_or_make (name);
15591 *input_line_pointer = c;
15595 /* Align the current frag to a given power of two. If a particular
15596 fill byte should be used, FILL points to an integer that contains
15597 that byte, otherwise FILL is null.
15599 The MIPS assembler also automatically adjusts any preceding
15603 mips_align (int to, int *fill, symbolS *label)
15605 mips_emit_delays ();
15606 mips_record_compressed_mode ();
15607 if (fill == NULL && subseg_text_p (now_seg))
15608 frag_align_code (to, 0);
15610 frag_align (to, fill ? *fill : 0, 0);
15611 record_alignment (now_seg, to);
15614 gas_assert (S_GET_SEGMENT (label) == now_seg);
15615 symbol_set_frag (label, frag_now);
15616 S_SET_VALUE (label, (valueT) frag_now_fix ());
15620 /* Align to a given power of two. .align 0 turns off the automatic
15621 alignment used by the data creating pseudo-ops. */
15624 s_align (int x ATTRIBUTE_UNUSED)
15626 int temp, fill_value, *fill_ptr;
15627 long max_alignment = 28;
15629 /* o Note that the assembler pulls down any immediately preceding label
15630 to the aligned address.
15631 o It's not documented but auto alignment is reinstated by
15632 a .align pseudo instruction.
15633 o Note also that after auto alignment is turned off the mips assembler
15634 issues an error on attempt to assemble an improperly aligned data item.
15637 temp = get_absolute_expression ();
15638 if (temp > max_alignment)
15639 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
15642 as_warn (_("Alignment negative: 0 assumed."));
15645 if (*input_line_pointer == ',')
15647 ++input_line_pointer;
15648 fill_value = get_absolute_expression ();
15649 fill_ptr = &fill_value;
15655 segment_info_type *si = seg_info (now_seg);
15656 struct insn_label_list *l = si->label_list;
15657 /* Auto alignment should be switched on by next section change. */
15659 mips_align (temp, fill_ptr, l != NULL ? l->label : NULL);
15666 demand_empty_rest_of_line ();
15670 s_change_sec (int sec)
15675 /* The ELF backend needs to know that we are changing sections, so
15676 that .previous works correctly. We could do something like check
15677 for an obj_section_change_hook macro, but that might be confusing
15678 as it would not be appropriate to use it in the section changing
15679 functions in read.c, since obj-elf.c intercepts those. FIXME:
15680 This should be cleaner, somehow. */
15682 obj_elf_section_change_hook ();
15685 mips_emit_delays ();
15696 subseg_set (bss_section, (subsegT) get_absolute_expression ());
15697 demand_empty_rest_of_line ();
15701 seg = subseg_new (RDATA_SECTION_NAME,
15702 (subsegT) get_absolute_expression ());
15705 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
15706 | SEC_READONLY | SEC_RELOC
15708 if (strncmp (TARGET_OS, "elf", 3) != 0)
15709 record_alignment (seg, 4);
15711 demand_empty_rest_of_line ();
15715 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
15718 bfd_set_section_flags (stdoutput, seg,
15719 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
15720 if (strncmp (TARGET_OS, "elf", 3) != 0)
15721 record_alignment (seg, 4);
15723 demand_empty_rest_of_line ();
15727 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
15730 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
15731 if (strncmp (TARGET_OS, "elf", 3) != 0)
15732 record_alignment (seg, 4);
15734 demand_empty_rest_of_line ();
15742 s_change_section (int ignore ATTRIBUTE_UNUSED)
15745 char *section_name;
15750 int section_entry_size;
15751 int section_alignment;
15756 section_name = input_line_pointer;
15757 c = get_symbol_end ();
15759 next_c = *(input_line_pointer + 1);
15761 /* Do we have .section Name<,"flags">? */
15762 if (c != ',' || (c == ',' && next_c == '"'))
15764 /* just after name is now '\0'. */
15765 *input_line_pointer = c;
15766 input_line_pointer = section_name;
15767 obj_elf_section (ignore);
15770 input_line_pointer++;
15772 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
15774 section_type = get_absolute_expression ();
15777 if (*input_line_pointer++ == ',')
15778 section_flag = get_absolute_expression ();
15781 if (*input_line_pointer++ == ',')
15782 section_entry_size = get_absolute_expression ();
15784 section_entry_size = 0;
15785 if (*input_line_pointer++ == ',')
15786 section_alignment = get_absolute_expression ();
15788 section_alignment = 0;
15789 /* FIXME: really ignore? */
15790 (void) section_alignment;
15792 section_name = xstrdup (section_name);
15794 /* When using the generic form of .section (as implemented by obj-elf.c),
15795 there's no way to set the section type to SHT_MIPS_DWARF. Users have
15796 traditionally had to fall back on the more common @progbits instead.
15798 There's nothing really harmful in this, since bfd will correct
15799 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
15800 means that, for backwards compatibility, the special_section entries
15801 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
15803 Even so, we shouldn't force users of the MIPS .section syntax to
15804 incorrectly label the sections as SHT_PROGBITS. The best compromise
15805 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
15806 generic type-checking code. */
15807 if (section_type == SHT_MIPS_DWARF)
15808 section_type = SHT_PROGBITS;
15810 obj_elf_change_section (section_name, section_type, section_flag,
15811 section_entry_size, 0, 0, 0);
15813 if (now_seg->name != section_name)
15814 free (section_name);
15815 #endif /* OBJ_ELF */
15819 mips_enable_auto_align (void)
15825 s_cons (int log_size)
15827 segment_info_type *si = seg_info (now_seg);
15828 struct insn_label_list *l = si->label_list;
15831 label = l != NULL ? l->label : NULL;
15832 mips_emit_delays ();
15833 if (log_size > 0 && auto_align)
15834 mips_align (log_size, 0, label);
15835 cons (1 << log_size);
15836 mips_clear_insn_labels ();
15840 s_float_cons (int type)
15842 segment_info_type *si = seg_info (now_seg);
15843 struct insn_label_list *l = si->label_list;
15846 label = l != NULL ? l->label : NULL;
15848 mips_emit_delays ();
15853 mips_align (3, 0, label);
15855 mips_align (2, 0, label);
15859 mips_clear_insn_labels ();
15862 /* Handle .globl. We need to override it because on Irix 5 you are
15865 where foo is an undefined symbol, to mean that foo should be
15866 considered to be the address of a function. */
15869 s_mips_globl (int x ATTRIBUTE_UNUSED)
15878 name = input_line_pointer;
15879 c = get_symbol_end ();
15880 symbolP = symbol_find_or_make (name);
15881 S_SET_EXTERNAL (symbolP);
15883 *input_line_pointer = c;
15884 SKIP_WHITESPACE ();
15886 /* On Irix 5, every global symbol that is not explicitly labelled as
15887 being a function is apparently labelled as being an object. */
15890 if (!is_end_of_line[(unsigned char) *input_line_pointer]
15891 && (*input_line_pointer != ','))
15896 secname = input_line_pointer;
15897 c = get_symbol_end ();
15898 sec = bfd_get_section_by_name (stdoutput, secname);
15900 as_bad (_("%s: no such section"), secname);
15901 *input_line_pointer = c;
15903 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
15904 flag = BSF_FUNCTION;
15907 symbol_get_bfdsym (symbolP)->flags |= flag;
15909 c = *input_line_pointer;
15912 input_line_pointer++;
15913 SKIP_WHITESPACE ();
15914 if (is_end_of_line[(unsigned char) *input_line_pointer])
15920 demand_empty_rest_of_line ();
15924 s_option (int x ATTRIBUTE_UNUSED)
15929 opt = input_line_pointer;
15930 c = get_symbol_end ();
15934 /* FIXME: What does this mean? */
15936 else if (strncmp (opt, "pic", 3) == 0)
15940 i = atoi (opt + 3);
15945 mips_pic = SVR4_PIC;
15946 mips_abicalls = TRUE;
15949 as_bad (_(".option pic%d not supported"), i);
15951 if (mips_pic == SVR4_PIC)
15953 if (g_switch_seen && g_switch_value != 0)
15954 as_warn (_("-G may not be used with SVR4 PIC code"));
15955 g_switch_value = 0;
15956 bfd_set_gp_size (stdoutput, 0);
15960 as_warn (_("Unrecognized option \"%s\""), opt);
15962 *input_line_pointer = c;
15963 demand_empty_rest_of_line ();
15966 /* This structure is used to hold a stack of .set values. */
15968 struct mips_option_stack
15970 struct mips_option_stack *next;
15971 struct mips_set_options options;
15974 static struct mips_option_stack *mips_opts_stack;
15976 /* Handle the .set pseudo-op. */
15979 s_mipsset (int x ATTRIBUTE_UNUSED)
15981 char *name = input_line_pointer, ch;
15983 while (!is_end_of_line[(unsigned char) *input_line_pointer])
15984 ++input_line_pointer;
15985 ch = *input_line_pointer;
15986 *input_line_pointer = '\0';
15988 if (strcmp (name, "reorder") == 0)
15990 if (mips_opts.noreorder)
15993 else if (strcmp (name, "noreorder") == 0)
15995 if (!mips_opts.noreorder)
15996 start_noreorder ();
15998 else if (strncmp (name, "at=", 3) == 0)
16000 char *s = name + 3;
16002 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
16003 as_bad (_("Unrecognized register name `%s'"), s);
16005 else if (strcmp (name, "at") == 0)
16007 mips_opts.at = ATREG;
16009 else if (strcmp (name, "noat") == 0)
16011 mips_opts.at = ZERO;
16013 else if (strcmp (name, "macro") == 0)
16015 mips_opts.warn_about_macros = 0;
16017 else if (strcmp (name, "nomacro") == 0)
16019 if (mips_opts.noreorder == 0)
16020 as_bad (_("`noreorder' must be set before `nomacro'"));
16021 mips_opts.warn_about_macros = 1;
16023 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
16025 mips_opts.nomove = 0;
16027 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
16029 mips_opts.nomove = 1;
16031 else if (strcmp (name, "bopt") == 0)
16033 mips_opts.nobopt = 0;
16035 else if (strcmp (name, "nobopt") == 0)
16037 mips_opts.nobopt = 1;
16039 else if (strcmp (name, "gp=default") == 0)
16040 mips_opts.gp32 = file_mips_gp32;
16041 else if (strcmp (name, "gp=32") == 0)
16042 mips_opts.gp32 = 1;
16043 else if (strcmp (name, "gp=64") == 0)
16045 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
16046 as_warn (_("%s isa does not support 64-bit registers"),
16047 mips_cpu_info_from_isa (mips_opts.isa)->name);
16048 mips_opts.gp32 = 0;
16050 else if (strcmp (name, "fp=default") == 0)
16051 mips_opts.fp32 = file_mips_fp32;
16052 else if (strcmp (name, "fp=32") == 0)
16053 mips_opts.fp32 = 1;
16054 else if (strcmp (name, "fp=64") == 0)
16056 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
16057 as_warn (_("%s isa does not support 64-bit floating point registers"),
16058 mips_cpu_info_from_isa (mips_opts.isa)->name);
16059 mips_opts.fp32 = 0;
16061 else if (strcmp (name, "softfloat") == 0)
16062 mips_opts.soft_float = 1;
16063 else if (strcmp (name, "hardfloat") == 0)
16064 mips_opts.soft_float = 0;
16065 else if (strcmp (name, "singlefloat") == 0)
16066 mips_opts.single_float = 1;
16067 else if (strcmp (name, "doublefloat") == 0)
16068 mips_opts.single_float = 0;
16069 else if (strcmp (name, "mips16") == 0
16070 || strcmp (name, "MIPS-16") == 0)
16072 if (mips_opts.micromips == 1)
16073 as_fatal (_("`mips16' cannot be used with `micromips'"));
16074 mips_opts.mips16 = 1;
16076 else if (strcmp (name, "nomips16") == 0
16077 || strcmp (name, "noMIPS-16") == 0)
16078 mips_opts.mips16 = 0;
16079 else if (strcmp (name, "micromips") == 0)
16081 if (mips_opts.mips16 == 1)
16082 as_fatal (_("`micromips' cannot be used with `mips16'"));
16083 mips_opts.micromips = 1;
16085 else if (strcmp (name, "nomicromips") == 0)
16086 mips_opts.micromips = 0;
16087 else if (strcmp (name, "smartmips") == 0)
16089 if (!ISA_SUPPORTS_SMARTMIPS)
16090 as_warn (_("%s ISA does not support SmartMIPS ASE"),
16091 mips_cpu_info_from_isa (mips_opts.isa)->name);
16092 mips_opts.ase_smartmips = 1;
16094 else if (strcmp (name, "nosmartmips") == 0)
16095 mips_opts.ase_smartmips = 0;
16096 else if (strcmp (name, "mips3d") == 0)
16097 mips_opts.ase_mips3d = 1;
16098 else if (strcmp (name, "nomips3d") == 0)
16099 mips_opts.ase_mips3d = 0;
16100 else if (strcmp (name, "mdmx") == 0)
16101 mips_opts.ase_mdmx = 1;
16102 else if (strcmp (name, "nomdmx") == 0)
16103 mips_opts.ase_mdmx = 0;
16104 else if (strcmp (name, "dsp") == 0)
16106 if (!ISA_SUPPORTS_DSP_ASE)
16107 as_warn (_("%s ISA does not support DSP ASE"),
16108 mips_cpu_info_from_isa (mips_opts.isa)->name);
16109 mips_opts.ase_dsp = 1;
16110 mips_opts.ase_dspr2 = 0;
16112 else if (strcmp (name, "nodsp") == 0)
16114 mips_opts.ase_dsp = 0;
16115 mips_opts.ase_dspr2 = 0;
16117 else if (strcmp (name, "dspr2") == 0)
16119 if (!ISA_SUPPORTS_DSPR2_ASE)
16120 as_warn (_("%s ISA does not support DSP R2 ASE"),
16121 mips_cpu_info_from_isa (mips_opts.isa)->name);
16122 mips_opts.ase_dspr2 = 1;
16123 mips_opts.ase_dsp = 1;
16125 else if (strcmp (name, "nodspr2") == 0)
16127 mips_opts.ase_dspr2 = 0;
16128 mips_opts.ase_dsp = 0;
16130 else if (strcmp (name, "mt") == 0)
16132 if (!ISA_SUPPORTS_MT_ASE)
16133 as_warn (_("%s ISA does not support MT ASE"),
16134 mips_cpu_info_from_isa (mips_opts.isa)->name);
16135 mips_opts.ase_mt = 1;
16137 else if (strcmp (name, "nomt") == 0)
16138 mips_opts.ase_mt = 0;
16139 else if (strcmp (name, "mcu") == 0)
16140 mips_opts.ase_mcu = 1;
16141 else if (strcmp (name, "nomcu") == 0)
16142 mips_opts.ase_mcu = 0;
16143 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
16147 /* Permit the user to change the ISA and architecture on the fly.
16148 Needless to say, misuse can cause serious problems. */
16149 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
16152 mips_opts.isa = file_mips_isa;
16153 mips_opts.arch = file_mips_arch;
16155 else if (strncmp (name, "arch=", 5) == 0)
16157 const struct mips_cpu_info *p;
16159 p = mips_parse_cpu("internal use", name + 5);
16161 as_bad (_("unknown architecture %s"), name + 5);
16164 mips_opts.arch = p->cpu;
16165 mips_opts.isa = p->isa;
16168 else if (strncmp (name, "mips", 4) == 0)
16170 const struct mips_cpu_info *p;
16172 p = mips_parse_cpu("internal use", name);
16174 as_bad (_("unknown ISA level %s"), name + 4);
16177 mips_opts.arch = p->cpu;
16178 mips_opts.isa = p->isa;
16182 as_bad (_("unknown ISA or architecture %s"), name);
16184 switch (mips_opts.isa)
16192 mips_opts.gp32 = 1;
16193 mips_opts.fp32 = 1;
16200 mips_opts.gp32 = 0;
16201 mips_opts.fp32 = 0;
16204 as_bad (_("unknown ISA level %s"), name + 4);
16209 mips_opts.gp32 = file_mips_gp32;
16210 mips_opts.fp32 = file_mips_fp32;
16213 else if (strcmp (name, "autoextend") == 0)
16214 mips_opts.noautoextend = 0;
16215 else if (strcmp (name, "noautoextend") == 0)
16216 mips_opts.noautoextend = 1;
16217 else if (strcmp (name, "push") == 0)
16219 struct mips_option_stack *s;
16221 s = (struct mips_option_stack *) xmalloc (sizeof *s);
16222 s->next = mips_opts_stack;
16223 s->options = mips_opts;
16224 mips_opts_stack = s;
16226 else if (strcmp (name, "pop") == 0)
16228 struct mips_option_stack *s;
16230 s = mips_opts_stack;
16232 as_bad (_(".set pop with no .set push"));
16235 /* If we're changing the reorder mode we need to handle
16236 delay slots correctly. */
16237 if (s->options.noreorder && ! mips_opts.noreorder)
16238 start_noreorder ();
16239 else if (! s->options.noreorder && mips_opts.noreorder)
16242 mips_opts = s->options;
16243 mips_opts_stack = s->next;
16247 else if (strcmp (name, "sym32") == 0)
16248 mips_opts.sym32 = TRUE;
16249 else if (strcmp (name, "nosym32") == 0)
16250 mips_opts.sym32 = FALSE;
16251 else if (strchr (name, ','))
16253 /* Generic ".set" directive; use the generic handler. */
16254 *input_line_pointer = ch;
16255 input_line_pointer = name;
16261 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
16263 *input_line_pointer = ch;
16264 demand_empty_rest_of_line ();
16267 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16268 .option pic2. It means to generate SVR4 PIC calls. */
16271 s_abicalls (int ignore ATTRIBUTE_UNUSED)
16273 mips_pic = SVR4_PIC;
16274 mips_abicalls = TRUE;
16276 if (g_switch_seen && g_switch_value != 0)
16277 as_warn (_("-G may not be used with SVR4 PIC code"));
16278 g_switch_value = 0;
16280 bfd_set_gp_size (stdoutput, 0);
16281 demand_empty_rest_of_line ();
16284 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16285 PIC code. It sets the $gp register for the function based on the
16286 function address, which is in the register named in the argument.
16287 This uses a relocation against _gp_disp, which is handled specially
16288 by the linker. The result is:
16289 lui $gp,%hi(_gp_disp)
16290 addiu $gp,$gp,%lo(_gp_disp)
16291 addu $gp,$gp,.cpload argument
16292 The .cpload argument is normally $25 == $t9.
16294 The -mno-shared option changes this to:
16295 lui $gp,%hi(__gnu_local_gp)
16296 addiu $gp,$gp,%lo(__gnu_local_gp)
16297 and the argument is ignored. This saves an instruction, but the
16298 resulting code is not position independent; it uses an absolute
16299 address for __gnu_local_gp. Thus code assembled with -mno-shared
16300 can go into an ordinary executable, but not into a shared library. */
16303 s_cpload (int ignore ATTRIBUTE_UNUSED)
16309 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16310 .cpload is ignored. */
16311 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16317 /* .cpload should be in a .set noreorder section. */
16318 if (mips_opts.noreorder == 0)
16319 as_warn (_(".cpload not in noreorder section"));
16321 reg = tc_get_register (0);
16323 /* If we need to produce a 64-bit address, we are better off using
16324 the default instruction sequence. */
16325 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
16327 ex.X_op = O_symbol;
16328 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
16330 ex.X_op_symbol = NULL;
16331 ex.X_add_number = 0;
16333 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16334 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16337 macro_build_lui (&ex, mips_gp_register);
16338 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16339 mips_gp_register, BFD_RELOC_LO16);
16341 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
16342 mips_gp_register, reg);
16345 demand_empty_rest_of_line ();
16348 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16349 .cpsetup $reg1, offset|$reg2, label
16351 If offset is given, this results in:
16352 sd $gp, offset($sp)
16353 lui $gp, %hi(%neg(%gp_rel(label)))
16354 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16355 daddu $gp, $gp, $reg1
16357 If $reg2 is given, this results in:
16358 daddu $reg2, $gp, $0
16359 lui $gp, %hi(%neg(%gp_rel(label)))
16360 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16361 daddu $gp, $gp, $reg1
16362 $reg1 is normally $25 == $t9.
16364 The -mno-shared option replaces the last three instructions with
16366 addiu $gp,$gp,%lo(_gp) */
16369 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
16371 expressionS ex_off;
16372 expressionS ex_sym;
16375 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16376 We also need NewABI support. */
16377 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16383 reg1 = tc_get_register (0);
16384 SKIP_WHITESPACE ();
16385 if (*input_line_pointer != ',')
16387 as_bad (_("missing argument separator ',' for .cpsetup"));
16391 ++input_line_pointer;
16392 SKIP_WHITESPACE ();
16393 if (*input_line_pointer == '$')
16395 mips_cpreturn_register = tc_get_register (0);
16396 mips_cpreturn_offset = -1;
16400 mips_cpreturn_offset = get_absolute_expression ();
16401 mips_cpreturn_register = -1;
16403 SKIP_WHITESPACE ();
16404 if (*input_line_pointer != ',')
16406 as_bad (_("missing argument separator ',' for .cpsetup"));
16410 ++input_line_pointer;
16411 SKIP_WHITESPACE ();
16412 expression (&ex_sym);
16415 if (mips_cpreturn_register == -1)
16417 ex_off.X_op = O_constant;
16418 ex_off.X_add_symbol = NULL;
16419 ex_off.X_op_symbol = NULL;
16420 ex_off.X_add_number = mips_cpreturn_offset;
16422 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
16423 BFD_RELOC_LO16, SP);
16426 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
16427 mips_gp_register, 0);
16429 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
16431 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
16432 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
16435 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
16436 mips_gp_register, -1, BFD_RELOC_GPREL16,
16437 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
16439 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
16440 mips_gp_register, reg1);
16446 ex.X_op = O_symbol;
16447 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
16448 ex.X_op_symbol = NULL;
16449 ex.X_add_number = 0;
16451 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16452 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16454 macro_build_lui (&ex, mips_gp_register);
16455 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16456 mips_gp_register, BFD_RELOC_LO16);
16461 demand_empty_rest_of_line ();
16465 s_cplocal (int ignore ATTRIBUTE_UNUSED)
16467 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16468 .cplocal is ignored. */
16469 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16475 mips_gp_register = tc_get_register (0);
16476 demand_empty_rest_of_line ();
16479 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16480 offset from $sp. The offset is remembered, and after making a PIC
16481 call $gp is restored from that location. */
16484 s_cprestore (int ignore ATTRIBUTE_UNUSED)
16488 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16489 .cprestore is ignored. */
16490 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16496 mips_cprestore_offset = get_absolute_expression ();
16497 mips_cprestore_valid = 1;
16499 ex.X_op = O_constant;
16500 ex.X_add_symbol = NULL;
16501 ex.X_op_symbol = NULL;
16502 ex.X_add_number = mips_cprestore_offset;
16505 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
16506 SP, HAVE_64BIT_ADDRESSES);
16509 demand_empty_rest_of_line ();
16512 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16513 was given in the preceding .cpsetup, it results in:
16514 ld $gp, offset($sp)
16516 If a register $reg2 was given there, it results in:
16517 daddu $gp, $reg2, $0 */
16520 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
16524 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16525 We also need NewABI support. */
16526 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16533 if (mips_cpreturn_register == -1)
16535 ex.X_op = O_constant;
16536 ex.X_add_symbol = NULL;
16537 ex.X_op_symbol = NULL;
16538 ex.X_add_number = mips_cpreturn_offset;
16540 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
16543 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
16544 mips_cpreturn_register, 0);
16547 demand_empty_rest_of_line ();
16550 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
16551 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
16552 use in DWARF debug information. */
16555 s_dtprel_internal (size_t bytes)
16562 if (ex.X_op != O_symbol)
16564 as_bad (_("Unsupported use of %s"), (bytes == 8
16567 ignore_rest_of_line ();
16570 p = frag_more (bytes);
16571 md_number_to_chars (p, 0, bytes);
16572 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
16574 ? BFD_RELOC_MIPS_TLS_DTPREL64
16575 : BFD_RELOC_MIPS_TLS_DTPREL32));
16577 demand_empty_rest_of_line ();
16580 /* Handle .dtprelword. */
16583 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
16585 s_dtprel_internal (4);
16588 /* Handle .dtpreldword. */
16591 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
16593 s_dtprel_internal (8);
16596 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16597 code. It sets the offset to use in gp_rel relocations. */
16600 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
16602 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16603 We also need NewABI support. */
16604 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16610 mips_gprel_offset = get_absolute_expression ();
16612 demand_empty_rest_of_line ();
16615 /* Handle the .gpword pseudo-op. This is used when generating PIC
16616 code. It generates a 32 bit GP relative reloc. */
16619 s_gpword (int ignore ATTRIBUTE_UNUSED)
16621 segment_info_type *si;
16622 struct insn_label_list *l;
16627 /* When not generating PIC code, this is treated as .word. */
16628 if (mips_pic != SVR4_PIC)
16634 si = seg_info (now_seg);
16635 l = si->label_list;
16636 label = l != NULL ? l->label : NULL;
16637 mips_emit_delays ();
16639 mips_align (2, 0, label);
16642 mips_clear_insn_labels ();
16644 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16646 as_bad (_("Unsupported use of .gpword"));
16647 ignore_rest_of_line ();
16651 md_number_to_chars (p, 0, 4);
16652 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16653 BFD_RELOC_GPREL32);
16655 demand_empty_rest_of_line ();
16659 s_gpdword (int ignore ATTRIBUTE_UNUSED)
16661 segment_info_type *si;
16662 struct insn_label_list *l;
16667 /* When not generating PIC code, this is treated as .dword. */
16668 if (mips_pic != SVR4_PIC)
16674 si = seg_info (now_seg);
16675 l = si->label_list;
16676 label = l != NULL ? l->label : NULL;
16677 mips_emit_delays ();
16679 mips_align (3, 0, label);
16682 mips_clear_insn_labels ();
16684 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16686 as_bad (_("Unsupported use of .gpdword"));
16687 ignore_rest_of_line ();
16691 md_number_to_chars (p, 0, 8);
16692 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16693 BFD_RELOC_GPREL32)->fx_tcbit = 1;
16695 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
16696 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
16697 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
16699 demand_empty_rest_of_line ();
16702 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
16703 tables in SVR4 PIC code. */
16706 s_cpadd (int ignore ATTRIBUTE_UNUSED)
16710 /* This is ignored when not generating SVR4 PIC code. */
16711 if (mips_pic != SVR4_PIC)
16717 /* Add $gp to the register named as an argument. */
16719 reg = tc_get_register (0);
16720 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
16723 demand_empty_rest_of_line ();
16726 /* Handle the .insn pseudo-op. This marks instruction labels in
16727 mips16/micromips mode. This permits the linker to handle them specially,
16728 such as generating jalx instructions when needed. We also make
16729 them odd for the duration of the assembly, in order to generate the
16730 right sort of code. We will make them even in the adjust_symtab
16731 routine, while leaving them marked. This is convenient for the
16732 debugger and the disassembler. The linker knows to make them odd
16736 s_insn (int ignore ATTRIBUTE_UNUSED)
16738 mips_mark_labels ();
16740 demand_empty_rest_of_line ();
16743 /* Handle a .stabn directive. We need these in order to mark a label
16744 as being a mips16 text label correctly. Sometimes the compiler
16745 will emit a label, followed by a .stabn, and then switch sections.
16746 If the label and .stabn are in mips16 mode, then the label is
16747 really a mips16 text label. */
16750 s_mips_stab (int type)
16753 mips_mark_labels ();
16758 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
16761 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
16768 name = input_line_pointer;
16769 c = get_symbol_end ();
16770 symbolP = symbol_find_or_make (name);
16771 S_SET_WEAK (symbolP);
16772 *input_line_pointer = c;
16774 SKIP_WHITESPACE ();
16776 if (! is_end_of_line[(unsigned char) *input_line_pointer])
16778 if (S_IS_DEFINED (symbolP))
16780 as_bad (_("ignoring attempt to redefine symbol %s"),
16781 S_GET_NAME (symbolP));
16782 ignore_rest_of_line ();
16786 if (*input_line_pointer == ',')
16788 ++input_line_pointer;
16789 SKIP_WHITESPACE ();
16793 if (exp.X_op != O_symbol)
16795 as_bad (_("bad .weakext directive"));
16796 ignore_rest_of_line ();
16799 symbol_set_value_expression (symbolP, &exp);
16802 demand_empty_rest_of_line ();
16805 /* Parse a register string into a number. Called from the ECOFF code
16806 to parse .frame. The argument is non-zero if this is the frame
16807 register, so that we can record it in mips_frame_reg. */
16810 tc_get_register (int frame)
16814 SKIP_WHITESPACE ();
16815 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
16819 mips_frame_reg = reg != 0 ? reg : SP;
16820 mips_frame_reg_valid = 1;
16821 mips_cprestore_valid = 0;
16827 md_section_align (asection *seg, valueT addr)
16829 int align = bfd_get_section_alignment (stdoutput, seg);
16833 /* We don't need to align ELF sections to the full alignment.
16834 However, Irix 5 may prefer that we align them at least to a 16
16835 byte boundary. We don't bother to align the sections if we
16836 are targeted for an embedded system. */
16837 if (strncmp (TARGET_OS, "elf", 3) == 0)
16843 return ((addr + (1 << align) - 1) & (-1 << align));
16846 /* Utility routine, called from above as well. If called while the
16847 input file is still being read, it's only an approximation. (For
16848 example, a symbol may later become defined which appeared to be
16849 undefined earlier.) */
16852 nopic_need_relax (symbolS *sym, int before_relaxing)
16857 if (g_switch_value > 0)
16859 const char *symname;
16862 /* Find out whether this symbol can be referenced off the $gp
16863 register. It can be if it is smaller than the -G size or if
16864 it is in the .sdata or .sbss section. Certain symbols can
16865 not be referenced off the $gp, although it appears as though
16867 symname = S_GET_NAME (sym);
16868 if (symname != (const char *) NULL
16869 && (strcmp (symname, "eprol") == 0
16870 || strcmp (symname, "etext") == 0
16871 || strcmp (symname, "_gp") == 0
16872 || strcmp (symname, "edata") == 0
16873 || strcmp (symname, "_fbss") == 0
16874 || strcmp (symname, "_fdata") == 0
16875 || strcmp (symname, "_ftext") == 0
16876 || strcmp (symname, "end") == 0
16877 || strcmp (symname, "_gp_disp") == 0))
16879 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
16881 #ifndef NO_ECOFF_DEBUGGING
16882 || (symbol_get_obj (sym)->ecoff_extern_size != 0
16883 && (symbol_get_obj (sym)->ecoff_extern_size
16884 <= g_switch_value))
16886 /* We must defer this decision until after the whole
16887 file has been read, since there might be a .extern
16888 after the first use of this symbol. */
16889 || (before_relaxing
16890 #ifndef NO_ECOFF_DEBUGGING
16891 && symbol_get_obj (sym)->ecoff_extern_size == 0
16893 && S_GET_VALUE (sym) == 0)
16894 || (S_GET_VALUE (sym) != 0
16895 && S_GET_VALUE (sym) <= g_switch_value)))
16899 const char *segname;
16901 segname = segment_name (S_GET_SEGMENT (sym));
16902 gas_assert (strcmp (segname, ".lit8") != 0
16903 && strcmp (segname, ".lit4") != 0);
16904 change = (strcmp (segname, ".sdata") != 0
16905 && strcmp (segname, ".sbss") != 0
16906 && strncmp (segname, ".sdata.", 7) != 0
16907 && strncmp (segname, ".sbss.", 6) != 0
16908 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
16909 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
16914 /* We are not optimizing for the $gp register. */
16919 /* Return true if the given symbol should be considered local for SVR4 PIC. */
16922 pic_need_relax (symbolS *sym, asection *segtype)
16926 /* Handle the case of a symbol equated to another symbol. */
16927 while (symbol_equated_reloc_p (sym))
16931 /* It's possible to get a loop here in a badly written program. */
16932 n = symbol_get_value_expression (sym)->X_add_symbol;
16938 if (symbol_section_p (sym))
16941 symsec = S_GET_SEGMENT (sym);
16943 /* This must duplicate the test in adjust_reloc_syms. */
16944 return (symsec != &bfd_und_section
16945 && symsec != &bfd_abs_section
16946 && !bfd_is_com_section (symsec)
16947 && !s_is_linkonce (sym, segtype)
16949 /* A global or weak symbol is treated as external. */
16950 && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
16956 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
16957 extended opcode. SEC is the section the frag is in. */
16960 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
16963 const struct mips16_immed_operand *op;
16965 int mintiny, maxtiny;
16969 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
16971 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
16974 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
16975 op = mips16_immed_operands;
16976 while (op->type != type)
16979 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
16984 if (type == '<' || type == '>' || type == '[' || type == ']')
16987 maxtiny = 1 << op->nbits;
16992 maxtiny = (1 << op->nbits) - 1;
16997 mintiny = - (1 << (op->nbits - 1));
16998 maxtiny = (1 << (op->nbits - 1)) - 1;
17001 sym_frag = symbol_get_frag (fragp->fr_symbol);
17002 val = S_GET_VALUE (fragp->fr_symbol);
17003 symsec = S_GET_SEGMENT (fragp->fr_symbol);
17009 /* We won't have the section when we are called from
17010 mips_relax_frag. However, we will always have been called
17011 from md_estimate_size_before_relax first. If this is a
17012 branch to a different section, we mark it as such. If SEC is
17013 NULL, and the frag is not marked, then it must be a branch to
17014 the same section. */
17017 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
17022 /* Must have been called from md_estimate_size_before_relax. */
17025 fragp->fr_subtype =
17026 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17028 /* FIXME: We should support this, and let the linker
17029 catch branches and loads that are out of range. */
17030 as_bad_where (fragp->fr_file, fragp->fr_line,
17031 _("unsupported PC relative reference to different section"));
17035 if (fragp != sym_frag && sym_frag->fr_address == 0)
17036 /* Assume non-extended on the first relaxation pass.
17037 The address we have calculated will be bogus if this is
17038 a forward branch to another frag, as the forward frag
17039 will have fr_address == 0. */
17043 /* In this case, we know for sure that the symbol fragment is in
17044 the same section. If the relax_marker of the symbol fragment
17045 differs from the relax_marker of this fragment, we have not
17046 yet adjusted the symbol fragment fr_address. We want to add
17047 in STRETCH in order to get a better estimate of the address.
17048 This particularly matters because of the shift bits. */
17050 && sym_frag->relax_marker != fragp->relax_marker)
17054 /* Adjust stretch for any alignment frag. Note that if have
17055 been expanding the earlier code, the symbol may be
17056 defined in what appears to be an earlier frag. FIXME:
17057 This doesn't handle the fr_subtype field, which specifies
17058 a maximum number of bytes to skip when doing an
17060 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
17062 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
17065 stretch = - ((- stretch)
17066 & ~ ((1 << (int) f->fr_offset) - 1));
17068 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
17077 addr = fragp->fr_address + fragp->fr_fix;
17079 /* The base address rules are complicated. The base address of
17080 a branch is the following instruction. The base address of a
17081 PC relative load or add is the instruction itself, but if it
17082 is in a delay slot (in which case it can not be extended) use
17083 the address of the instruction whose delay slot it is in. */
17084 if (type == 'p' || type == 'q')
17088 /* If we are currently assuming that this frag should be
17089 extended, then, the current address is two bytes
17091 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17094 /* Ignore the low bit in the target, since it will be set
17095 for a text label. */
17096 if ((val & 1) != 0)
17099 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17101 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17104 val -= addr & ~ ((1 << op->shift) - 1);
17106 /* Branch offsets have an implicit 0 in the lowest bit. */
17107 if (type == 'p' || type == 'q')
17110 /* If any of the shifted bits are set, we must use an extended
17111 opcode. If the address depends on the size of this
17112 instruction, this can lead to a loop, so we arrange to always
17113 use an extended opcode. We only check this when we are in
17114 the main relaxation loop, when SEC is NULL. */
17115 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
17117 fragp->fr_subtype =
17118 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17122 /* If we are about to mark a frag as extended because the value
17123 is precisely maxtiny + 1, then there is a chance of an
17124 infinite loop as in the following code:
17129 In this case when the la is extended, foo is 0x3fc bytes
17130 away, so the la can be shrunk, but then foo is 0x400 away, so
17131 the la must be extended. To avoid this loop, we mark the
17132 frag as extended if it was small, and is about to become
17133 extended with a value of maxtiny + 1. */
17134 if (val == ((maxtiny + 1) << op->shift)
17135 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
17138 fragp->fr_subtype =
17139 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17143 else if (symsec != absolute_section && sec != NULL)
17144 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
17146 if ((val & ((1 << op->shift) - 1)) != 0
17147 || val < (mintiny << op->shift)
17148 || val > (maxtiny << op->shift))
17154 /* Compute the length of a branch sequence, and adjust the
17155 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17156 worst-case length is computed, with UPDATE being used to indicate
17157 whether an unconditional (-1), branch-likely (+1) or regular (0)
17158 branch is to be computed. */
17160 relaxed_branch_length (fragS *fragp, asection *sec, int update)
17162 bfd_boolean toofar;
17166 && S_IS_DEFINED (fragp->fr_symbol)
17167 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17172 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17174 addr = fragp->fr_address + fragp->fr_fix + 4;
17178 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
17181 /* If the symbol is not defined or it's in a different segment,
17182 assume the user knows what's going on and emit a short
17188 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17190 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
17191 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
17192 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
17193 RELAX_BRANCH_LINK (fragp->fr_subtype),
17199 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
17202 if (mips_pic != NO_PIC)
17204 /* Additional space for PIC loading of target address. */
17206 if (mips_opts.isa == ISA_MIPS1)
17207 /* Additional space for $at-stabilizing nop. */
17211 /* If branch is conditional. */
17212 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
17219 /* Compute the length of a branch sequence, and adjust the
17220 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17221 worst-case length is computed, with UPDATE being used to indicate
17222 whether an unconditional (-1), or regular (0) branch is to be
17226 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
17228 bfd_boolean toofar;
17232 && S_IS_DEFINED (fragp->fr_symbol)
17233 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17238 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17239 /* Ignore the low bit in the target, since it will be set
17240 for a text label. */
17241 if ((val & 1) != 0)
17244 addr = fragp->fr_address + fragp->fr_fix + 4;
17248 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
17251 /* If the symbol is not defined or it's in a different segment,
17252 assume the user knows what's going on and emit a short
17258 if (fragp && update
17259 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17260 fragp->fr_subtype = (toofar
17261 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
17262 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
17267 bfd_boolean compact_known = fragp != NULL;
17268 bfd_boolean compact = FALSE;
17269 bfd_boolean uncond;
17272 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17274 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
17276 uncond = update < 0;
17278 /* If label is out of range, we turn branch <br>:
17280 <br> label # 4 bytes
17286 nop # 2 bytes if compact && !PIC
17289 if (mips_pic == NO_PIC && (!compact_known || compact))
17292 /* If assembling PIC code, we further turn:
17298 lw/ld at, %got(label)(gp) # 4 bytes
17299 d/addiu at, %lo(label) # 4 bytes
17302 if (mips_pic != NO_PIC)
17305 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17307 <brneg> 0f # 4 bytes
17308 nop # 2 bytes if !compact
17311 length += (compact_known && compact) ? 4 : 6;
17317 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17318 bit accordingly. */
17321 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
17323 bfd_boolean toofar;
17326 && S_IS_DEFINED (fragp->fr_symbol)
17327 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17333 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17334 /* Ignore the low bit in the target, since it will be set
17335 for a text label. */
17336 if ((val & 1) != 0)
17339 /* Assume this is a 2-byte branch. */
17340 addr = fragp->fr_address + fragp->fr_fix + 2;
17342 /* We try to avoid the infinite loop by not adding 2 more bytes for
17347 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17349 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
17350 else if (type == 'E')
17351 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
17356 /* If the symbol is not defined or it's in a different segment,
17357 we emit a normal 32-bit branch. */
17360 if (fragp && update
17361 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17363 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
17364 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
17372 /* Estimate the size of a frag before relaxing. Unless this is the
17373 mips16, we are not really relaxing here, and the final size is
17374 encoded in the subtype information. For the mips16, we have to
17375 decide whether we are using an extended opcode or not. */
17378 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
17382 if (RELAX_BRANCH_P (fragp->fr_subtype))
17385 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
17387 return fragp->fr_var;
17390 if (RELAX_MIPS16_P (fragp->fr_subtype))
17391 /* We don't want to modify the EXTENDED bit here; it might get us
17392 into infinite loops. We change it only in mips_relax_frag(). */
17393 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
17395 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17399 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17400 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
17401 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17402 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
17403 fragp->fr_var = length;
17408 if (mips_pic == NO_PIC)
17409 change = nopic_need_relax (fragp->fr_symbol, 0);
17410 else if (mips_pic == SVR4_PIC)
17411 change = pic_need_relax (fragp->fr_symbol, segtype);
17412 else if (mips_pic == VXWORKS_PIC)
17413 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17420 fragp->fr_subtype |= RELAX_USE_SECOND;
17421 return -RELAX_FIRST (fragp->fr_subtype);
17424 return -RELAX_SECOND (fragp->fr_subtype);
17427 /* This is called to see whether a reloc against a defined symbol
17428 should be converted into a reloc against a section. */
17431 mips_fix_adjustable (fixS *fixp)
17433 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
17434 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17437 if (fixp->fx_addsy == NULL)
17440 /* If symbol SYM is in a mergeable section, relocations of the form
17441 SYM + 0 can usually be made section-relative. The mergeable data
17442 is then identified by the section offset rather than by the symbol.
17444 However, if we're generating REL LO16 relocations, the offset is split
17445 between the LO16 and parterning high part relocation. The linker will
17446 need to recalculate the complete offset in order to correctly identify
17449 The linker has traditionally not looked for the parterning high part
17450 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17451 placed anywhere. Rather than break backwards compatibility by changing
17452 this, it seems better not to force the issue, and instead keep the
17453 original symbol. This will work with either linker behavior. */
17454 if ((lo16_reloc_p (fixp->fx_r_type)
17455 || reloc_needs_lo_p (fixp->fx_r_type))
17456 && HAVE_IN_PLACE_ADDENDS
17457 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
17460 /* There is no place to store an in-place offset for JALR relocations.
17461 Likewise an in-range offset of PC-relative relocations may overflow
17462 the in-place relocatable field if recalculated against the start
17463 address of the symbol's containing section. */
17464 if (HAVE_IN_PLACE_ADDENDS
17465 && (fixp->fx_pcrel || jalr_reloc_p (fixp->fx_r_type)))
17469 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17470 to a floating-point stub. The same is true for non-R_MIPS16_26
17471 relocations against MIPS16 functions; in this case, the stub becomes
17472 the function's canonical address.
17474 Floating-point stubs are stored in unique .mips16.call.* or
17475 .mips16.fn.* sections. If a stub T for function F is in section S,
17476 the first relocation in section S must be against F; this is how the
17477 linker determines the target function. All relocations that might
17478 resolve to T must also be against F. We therefore have the following
17479 restrictions, which are given in an intentionally-redundant way:
17481 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17484 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17485 if that stub might be used.
17487 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17490 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17491 that stub might be used.
17493 There is a further restriction:
17495 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17496 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17497 targets with in-place addends; the relocation field cannot
17498 encode the low bit.
17500 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17501 against a MIPS16 symbol. We deal with (5) by by not reducing any
17502 such relocations on REL targets.
17504 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17505 relocation against some symbol R, no relocation against R may be
17506 reduced. (Note that this deals with (2) as well as (1) because
17507 relocations against global symbols will never be reduced on ELF
17508 targets.) This approach is a little simpler than trying to detect
17509 stub sections, and gives the "all or nothing" per-symbol consistency
17510 that we have for MIPS16 symbols. */
17512 && fixp->fx_subsy == NULL
17513 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
17514 || *symbol_get_tc (fixp->fx_addsy)
17515 || (HAVE_IN_PLACE_ADDENDS
17516 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
17517 && jmp_reloc_p (fixp->fx_r_type))))
17524 /* Translate internal representation of relocation info to BFD target
17528 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
17530 static arelent *retval[4];
17532 bfd_reloc_code_real_type code;
17534 memset (retval, 0, sizeof(retval));
17535 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
17536 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
17537 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
17538 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
17540 if (fixp->fx_pcrel)
17542 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
17543 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
17544 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
17545 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1);
17547 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17548 Relocations want only the symbol offset. */
17549 reloc->addend = fixp->fx_addnumber + reloc->address;
17552 /* A gruesome hack which is a result of the gruesome gas
17553 reloc handling. What's worse, for COFF (as opposed to
17554 ECOFF), we might need yet another copy of reloc->address.
17555 See bfd_install_relocation. */
17556 reloc->addend += reloc->address;
17560 reloc->addend = fixp->fx_addnumber;
17562 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17563 entry to be used in the relocation's section offset. */
17564 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17566 reloc->address = reloc->addend;
17570 code = fixp->fx_r_type;
17572 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
17573 if (reloc->howto == NULL)
17575 as_bad_where (fixp->fx_file, fixp->fx_line,
17576 _("Can not represent %s relocation in this object file format"),
17577 bfd_get_reloc_code_name (code));
17584 /* Relax a machine dependent frag. This returns the amount by which
17585 the current size of the frag should change. */
17588 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
17590 if (RELAX_BRANCH_P (fragp->fr_subtype))
17592 offsetT old_var = fragp->fr_var;
17594 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
17596 return fragp->fr_var - old_var;
17599 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17601 offsetT old_var = fragp->fr_var;
17602 offsetT new_var = 4;
17604 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17605 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
17606 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17607 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
17608 fragp->fr_var = new_var;
17610 return new_var - old_var;
17613 if (! RELAX_MIPS16_P (fragp->fr_subtype))
17616 if (mips16_extended_frag (fragp, NULL, stretch))
17618 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17620 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
17625 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17627 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
17634 /* Convert a machine dependent frag. */
17637 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
17639 if (RELAX_BRANCH_P (fragp->fr_subtype))
17642 unsigned long insn;
17646 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
17648 if (target_big_endian)
17649 insn = bfd_getb32 (buf);
17651 insn = bfd_getl32 (buf);
17653 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17655 /* We generate a fixup instead of applying it right now
17656 because, if there are linker relaxations, we're going to
17657 need the relocations. */
17658 exp.X_op = O_symbol;
17659 exp.X_add_symbol = fragp->fr_symbol;
17660 exp.X_add_number = fragp->fr_offset;
17662 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
17663 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2);
17664 fixp->fx_file = fragp->fr_file;
17665 fixp->fx_line = fragp->fr_line;
17667 md_number_to_chars ((char *) buf, insn, 4);
17674 as_warn_where (fragp->fr_file, fragp->fr_line,
17675 _("Relaxed out-of-range branch into a jump"));
17677 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
17680 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17682 /* Reverse the branch. */
17683 switch ((insn >> 28) & 0xf)
17686 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
17687 have the condition reversed by tweaking a single
17688 bit, and their opcodes all have 0x4???????. */
17689 gas_assert ((insn & 0xf1000000) == 0x41000000);
17690 insn ^= 0x00010000;
17694 /* bltz 0x04000000 bgez 0x04010000
17695 bltzal 0x04100000 bgezal 0x04110000 */
17696 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
17697 insn ^= 0x00010000;
17701 /* beq 0x10000000 bne 0x14000000
17702 blez 0x18000000 bgtz 0x1c000000 */
17703 insn ^= 0x04000000;
17711 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
17713 /* Clear the and-link bit. */
17714 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
17716 /* bltzal 0x04100000 bgezal 0x04110000
17717 bltzall 0x04120000 bgezall 0x04130000 */
17718 insn &= ~0x00100000;
17721 /* Branch over the branch (if the branch was likely) or the
17722 full jump (not likely case). Compute the offset from the
17723 current instruction to branch to. */
17724 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17728 /* How many bytes in instructions we've already emitted? */
17729 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
17730 /* How many bytes in instructions from here to the end? */
17731 i = fragp->fr_var - i;
17733 /* Convert to instruction count. */
17735 /* Branch counts from the next instruction. */
17738 /* Branch over the jump. */
17739 md_number_to_chars ((char *) buf, insn, 4);
17743 md_number_to_chars ((char *) buf, 0, 4);
17746 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17748 /* beql $0, $0, 2f */
17750 /* Compute the PC offset from the current instruction to
17751 the end of the variable frag. */
17752 /* How many bytes in instructions we've already emitted? */
17753 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
17754 /* How many bytes in instructions from here to the end? */
17755 i = fragp->fr_var - i;
17756 /* Convert to instruction count. */
17758 /* Don't decrement i, because we want to branch over the
17762 md_number_to_chars ((char *) buf, insn, 4);
17765 md_number_to_chars ((char *) buf, 0, 4);
17770 if (mips_pic == NO_PIC)
17773 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
17774 ? 0x0c000000 : 0x08000000);
17775 exp.X_op = O_symbol;
17776 exp.X_add_symbol = fragp->fr_symbol;
17777 exp.X_add_number = fragp->fr_offset;
17779 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
17780 4, &exp, FALSE, BFD_RELOC_MIPS_JMP);
17781 fixp->fx_file = fragp->fr_file;
17782 fixp->fx_line = fragp->fr_line;
17784 md_number_to_chars ((char *) buf, insn, 4);
17789 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
17791 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
17792 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
17793 insn |= at << OP_SH_RT;
17794 exp.X_op = O_symbol;
17795 exp.X_add_symbol = fragp->fr_symbol;
17796 exp.X_add_number = fragp->fr_offset;
17798 if (fragp->fr_offset)
17800 exp.X_add_symbol = make_expr_symbol (&exp);
17801 exp.X_add_number = 0;
17804 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
17805 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16);
17806 fixp->fx_file = fragp->fr_file;
17807 fixp->fx_line = fragp->fr_line;
17809 md_number_to_chars ((char *) buf, insn, 4);
17812 if (mips_opts.isa == ISA_MIPS1)
17815 md_number_to_chars ((char *) buf, 0, 4);
17819 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
17820 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
17821 insn |= at << OP_SH_RS | at << OP_SH_RT;
17823 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
17824 4, &exp, FALSE, BFD_RELOC_LO16);
17825 fixp->fx_file = fragp->fr_file;
17826 fixp->fx_line = fragp->fr_line;
17828 md_number_to_chars ((char *) buf, insn, 4);
17832 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
17836 insn |= at << OP_SH_RS;
17838 md_number_to_chars ((char *) buf, insn, 4);
17843 gas_assert (buf == (bfd_byte *)fragp->fr_literal
17844 + fragp->fr_fix + fragp->fr_var);
17846 fragp->fr_fix += fragp->fr_var;
17851 /* Relax microMIPS branches. */
17852 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17854 bfd_byte *buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
17855 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17856 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
17857 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17858 bfd_boolean short_ds;
17859 unsigned long insn;
17863 exp.X_op = O_symbol;
17864 exp.X_add_symbol = fragp->fr_symbol;
17865 exp.X_add_number = fragp->fr_offset;
17867 fragp->fr_fix += fragp->fr_var;
17869 /* Handle 16-bit branches that fit or are forced to fit. */
17870 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17872 /* We generate a fixup instead of applying it right now,
17873 because if there is linker relaxation, we're going to
17874 need the relocations. */
17876 fixp = fix_new_exp (fragp,
17877 buf - (bfd_byte *) fragp->fr_literal,
17879 BFD_RELOC_MICROMIPS_10_PCREL_S1);
17880 else if (type == 'E')
17881 fixp = fix_new_exp (fragp,
17882 buf - (bfd_byte *) fragp->fr_literal,
17884 BFD_RELOC_MICROMIPS_7_PCREL_S1);
17888 fixp->fx_file = fragp->fr_file;
17889 fixp->fx_line = fragp->fr_line;
17891 /* These relocations can have an addend that won't fit in
17893 fixp->fx_no_overflow = 1;
17898 /* Handle 32-bit branches that fit or are forced to fit. */
17899 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
17900 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17902 /* We generate a fixup instead of applying it right now,
17903 because if there is linker relaxation, we're going to
17904 need the relocations. */
17905 fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal,
17906 4, &exp, TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1);
17907 fixp->fx_file = fragp->fr_file;
17908 fixp->fx_line = fragp->fr_line;
17914 /* Relax 16-bit branches to 32-bit branches. */
17917 if (target_big_endian)
17918 insn = bfd_getb16 (buf);
17920 insn = bfd_getl16 (buf);
17922 if ((insn & 0xfc00) == 0xcc00) /* b16 */
17923 insn = 0x94000000; /* beq */
17924 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
17926 unsigned long regno;
17928 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
17929 regno = micromips_to_32_reg_d_map [regno];
17930 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
17931 insn |= regno << MICROMIPSOP_SH_RS;
17936 /* Nothing else to do, just write it out. */
17937 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
17938 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17940 md_number_to_chars ((char *) buf, insn >> 16, 2);
17942 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
17945 gas_assert (buf == ((bfd_byte *) fragp->fr_literal
17952 unsigned long next;
17954 if (target_big_endian)
17956 insn = bfd_getb16 (buf);
17957 next = bfd_getb16 (buf + 2);
17961 insn = bfd_getl16 (buf);
17962 next = bfd_getl16 (buf + 2);
17964 insn = (insn << 16) | next;
17967 /* Relax 32-bit branches to a sequence of instructions. */
17968 as_warn_where (fragp->fr_file, fragp->fr_line,
17969 _("Relaxed out-of-range branch into a jump"));
17971 /* Set the short-delay-slot bit. */
17972 short_ds = al && (insn & 0x02000000) != 0;
17974 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
17978 /* Reverse the branch. */
17979 if ((insn & 0xfc000000) == 0x94000000 /* beq */
17980 || (insn & 0xfc000000) == 0xb4000000) /* bne */
17981 insn ^= 0x20000000;
17982 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
17983 || (insn & 0xffe00000) == 0x40400000 /* bgez */
17984 || (insn & 0xffe00000) == 0x40800000 /* blez */
17985 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
17986 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
17987 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
17988 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
17989 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
17990 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
17991 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
17992 insn ^= 0x00400000;
17993 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
17994 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
17995 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
17996 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
17997 insn ^= 0x00200000;
18003 /* Clear the and-link and short-delay-slot bits. */
18004 gas_assert ((insn & 0xfda00000) == 0x40200000);
18006 /* bltzal 0x40200000 bgezal 0x40600000 */
18007 /* bltzals 0x42200000 bgezals 0x42600000 */
18008 insn &= ~0x02200000;
18011 /* Make a label at the end for use with the branch. */
18012 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
18013 micromips_label_inc ();
18014 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
18016 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
18020 fixp = fix_new (fragp, buf - (bfd_byte *) fragp->fr_literal,
18021 4, l, 0, TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1);
18022 fixp->fx_file = fragp->fr_file;
18023 fixp->fx_line = fragp->fr_line;
18025 /* Branch over the jump. */
18026 md_number_to_chars ((char *) buf, insn >> 16, 2);
18028 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
18035 md_number_to_chars ((char *) buf, insn, 2);
18040 if (mips_pic == NO_PIC)
18042 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
18044 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18045 insn = al ? jal : 0xd4000000;
18047 fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal,
18048 4, &exp, FALSE, BFD_RELOC_MICROMIPS_JMP);
18049 fixp->fx_file = fragp->fr_file;
18050 fixp->fx_line = fragp->fr_line;
18052 md_number_to_chars ((char *) buf, insn >> 16, 2);
18054 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
18061 md_number_to_chars ((char *) buf, insn, 2);
18067 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
18068 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
18069 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
18071 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18072 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
18073 insn |= at << MICROMIPSOP_SH_RT;
18075 if (exp.X_add_number)
18077 exp.X_add_symbol = make_expr_symbol (&exp);
18078 exp.X_add_number = 0;
18081 fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal,
18082 4, &exp, FALSE, BFD_RELOC_MICROMIPS_GOT16);
18083 fixp->fx_file = fragp->fr_file;
18084 fixp->fx_line = fragp->fr_line;
18086 md_number_to_chars ((char *) buf, insn >> 16, 2);
18088 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
18091 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18092 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
18093 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
18095 fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal,
18096 4, &exp, FALSE, BFD_RELOC_MICROMIPS_LO16);
18097 fixp->fx_file = fragp->fr_file;
18098 fixp->fx_line = fragp->fr_line;
18100 md_number_to_chars ((char *) buf, insn >> 16, 2);
18102 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
18105 /* jr/jrc/jalr/jalrs $at */
18106 insn = al ? jalr : jr;
18107 insn |= at << MICROMIPSOP_SH_MJ;
18109 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
18113 gas_assert (buf == (bfd_byte *) fragp->fr_literal + fragp->fr_fix);
18117 if (RELAX_MIPS16_P (fragp->fr_subtype))
18120 const struct mips16_immed_operand *op;
18121 bfd_boolean small, ext;
18124 unsigned long insn;
18125 bfd_boolean use_extend;
18126 unsigned short extend;
18128 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
18129 op = mips16_immed_operands;
18130 while (op->type != type)
18133 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18144 val = resolve_symbol_value (fragp->fr_symbol);
18149 addr = fragp->fr_address + fragp->fr_fix;
18151 /* The rules for the base address of a PC relative reloc are
18152 complicated; see mips16_extended_frag. */
18153 if (type == 'p' || type == 'q')
18158 /* Ignore the low bit in the target, since it will be
18159 set for a text label. */
18160 if ((val & 1) != 0)
18163 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
18165 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
18168 addr &= ~ (addressT) ((1 << op->shift) - 1);
18171 /* Make sure the section winds up with the alignment we have
18174 record_alignment (asec, op->shift);
18178 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
18179 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
18180 as_warn_where (fragp->fr_file, fragp->fr_line,
18181 _("extended instruction in delay slot"));
18183 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
18185 if (target_big_endian)
18186 insn = bfd_getb16 (buf);
18188 insn = bfd_getl16 (buf);
18190 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
18191 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
18192 small, ext, &insn, &use_extend, &extend);
18196 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
18197 fragp->fr_fix += 2;
18201 md_number_to_chars ((char *) buf, insn, 2);
18202 fragp->fr_fix += 2;
18207 relax_substateT subtype = fragp->fr_subtype;
18208 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
18209 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
18213 first = RELAX_FIRST (subtype);
18214 second = RELAX_SECOND (subtype);
18215 fixp = (fixS *) fragp->fr_opcode;
18217 /* If the delay slot chosen does not match the size of the instruction,
18218 then emit a warning. */
18219 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
18220 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
18225 s = subtype & (RELAX_DELAY_SLOT_16BIT
18226 | RELAX_DELAY_SLOT_SIZE_FIRST
18227 | RELAX_DELAY_SLOT_SIZE_SECOND);
18228 msg = macro_warning (s);
18230 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18234 /* Possibly emit a warning if we've chosen the longer option. */
18235 if (use_second == second_longer)
18241 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
18242 msg = macro_warning (s);
18244 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18248 /* Go through all the fixups for the first sequence. Disable them
18249 (by marking them as done) if we're going to use the second
18250 sequence instead. */
18252 && fixp->fx_frag == fragp
18253 && fixp->fx_where < fragp->fr_fix - second)
18255 if (subtype & RELAX_USE_SECOND)
18257 fixp = fixp->fx_next;
18260 /* Go through the fixups for the second sequence. Disable them if
18261 we're going to use the first sequence, otherwise adjust their
18262 addresses to account for the relaxation. */
18263 while (fixp && fixp->fx_frag == fragp)
18265 if (subtype & RELAX_USE_SECOND)
18266 fixp->fx_where -= first;
18269 fixp = fixp->fx_next;
18272 /* Now modify the frag contents. */
18273 if (subtype & RELAX_USE_SECOND)
18277 start = fragp->fr_literal + fragp->fr_fix - first - second;
18278 memmove (start, start + first, second);
18279 fragp->fr_fix -= first;
18282 fragp->fr_fix -= second;
18288 /* This function is called after the relocs have been generated.
18289 We've been storing mips16 text labels as odd. Here we convert them
18290 back to even for the convenience of the debugger. */
18293 mips_frob_file_after_relocs (void)
18296 unsigned int count, i;
18301 syms = bfd_get_outsymbols (stdoutput);
18302 count = bfd_get_symcount (stdoutput);
18303 for (i = 0; i < count; i++, syms++)
18304 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
18305 && ((*syms)->value & 1) != 0)
18307 (*syms)->value &= ~1;
18308 /* If the symbol has an odd size, it was probably computed
18309 incorrectly, so adjust that as well. */
18310 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
18311 ++elf_symbol (*syms)->internal_elf_sym.st_size;
18317 /* This function is called whenever a label is defined, including fake
18318 labels instantiated off the dot special symbol. It is used when
18319 handling branch delays; if a branch has a label, we assume we cannot
18320 move it. This also bumps the value of the symbol by 1 in compressed
18324 mips_record_label (symbolS *sym)
18326 segment_info_type *si = seg_info (now_seg);
18327 struct insn_label_list *l;
18329 if (free_insn_labels == NULL)
18330 l = (struct insn_label_list *) xmalloc (sizeof *l);
18333 l = free_insn_labels;
18334 free_insn_labels = l->next;
18338 l->next = si->label_list;
18339 si->label_list = l;
18342 /* This function is called as tc_frob_label() whenever a label is defined
18343 and adds a DWARF-2 record we only want for true labels. */
18346 mips_define_label (symbolS *sym)
18348 mips_record_label (sym);
18350 dwarf2_emit_label (sym);
18354 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
18356 /* Some special processing for a MIPS ELF file. */
18359 mips_elf_final_processing (void)
18361 /* Write out the register information. */
18362 if (mips_abi != N64_ABI)
18366 s.ri_gprmask = mips_gprmask;
18367 s.ri_cprmask[0] = mips_cprmask[0];
18368 s.ri_cprmask[1] = mips_cprmask[1];
18369 s.ri_cprmask[2] = mips_cprmask[2];
18370 s.ri_cprmask[3] = mips_cprmask[3];
18371 /* The gp_value field is set by the MIPS ELF backend. */
18373 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
18374 ((Elf32_External_RegInfo *)
18375 mips_regmask_frag));
18379 Elf64_Internal_RegInfo s;
18381 s.ri_gprmask = mips_gprmask;
18383 s.ri_cprmask[0] = mips_cprmask[0];
18384 s.ri_cprmask[1] = mips_cprmask[1];
18385 s.ri_cprmask[2] = mips_cprmask[2];
18386 s.ri_cprmask[3] = mips_cprmask[3];
18387 /* The gp_value field is set by the MIPS ELF backend. */
18389 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
18390 ((Elf64_External_RegInfo *)
18391 mips_regmask_frag));
18394 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18395 sort of BFD interface for this. */
18396 if (mips_any_noreorder)
18397 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
18398 if (mips_pic != NO_PIC)
18400 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
18401 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18404 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18406 /* Set MIPS ELF flags for ASEs. */
18407 /* We may need to define a new flag for DSP ASE, and set this flag when
18408 file_ase_dsp is true. */
18409 /* Same for DSP R2. */
18410 /* We may need to define a new flag for MT ASE, and set this flag when
18411 file_ase_mt is true. */
18412 if (file_ase_mips16)
18413 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
18414 if (file_ase_micromips)
18415 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
18416 #if 0 /* XXX FIXME */
18417 if (file_ase_mips3d)
18418 elf_elfheader (stdoutput)->e_flags |= ???;
18421 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
18423 /* Set the MIPS ELF ABI flags. */
18424 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
18425 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
18426 else if (mips_abi == O64_ABI)
18427 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
18428 else if (mips_abi == EABI_ABI)
18430 if (!file_mips_gp32)
18431 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
18433 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
18435 else if (mips_abi == N32_ABI)
18436 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
18438 /* Nothing to do for N64_ABI. */
18440 if (mips_32bitmode)
18441 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
18443 #if 0 /* XXX FIXME */
18444 /* 32 bit code with 64 bit FP registers. */
18445 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
18446 elf_elfheader (stdoutput)->e_flags |= ???;
18450 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
18452 typedef struct proc {
18454 symbolS *func_end_sym;
18455 unsigned long reg_mask;
18456 unsigned long reg_offset;
18457 unsigned long fpreg_mask;
18458 unsigned long fpreg_offset;
18459 unsigned long frame_offset;
18460 unsigned long frame_reg;
18461 unsigned long pc_reg;
18464 static procS cur_proc;
18465 static procS *cur_proc_ptr;
18466 static int numprocs;
18468 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18469 as "2", and a normal nop as "0". */
18471 #define NOP_OPCODE_MIPS 0
18472 #define NOP_OPCODE_MIPS16 1
18473 #define NOP_OPCODE_MICROMIPS 2
18476 mips_nop_opcode (void)
18478 if (seg_info (now_seg)->tc_segment_info_data.micromips)
18479 return NOP_OPCODE_MICROMIPS;
18480 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
18481 return NOP_OPCODE_MIPS16;
18483 return NOP_OPCODE_MIPS;
18486 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18487 32-bit microMIPS NOPs here (if applicable). */
18490 mips_handle_align (fragS *fragp)
18494 int bytes, size, excess;
18497 if (fragp->fr_type != rs_align_code)
18500 p = fragp->fr_literal + fragp->fr_fix;
18502 switch (nop_opcode)
18504 case NOP_OPCODE_MICROMIPS:
18505 opcode = micromips_nop32_insn.insn_opcode;
18508 case NOP_OPCODE_MIPS16:
18509 opcode = mips16_nop_insn.insn_opcode;
18512 case NOP_OPCODE_MIPS:
18514 opcode = nop_insn.insn_opcode;
18519 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
18520 excess = bytes % size;
18522 /* Handle the leading part if we're not inserting a whole number of
18523 instructions, and make it the end of the fixed part of the frag.
18524 Try to fit in a short microMIPS NOP if applicable and possible,
18525 and use zeroes otherwise. */
18526 gas_assert (excess < 4);
18527 fragp->fr_fix += excess;
18532 /* Fall through. */
18534 if (nop_opcode == NOP_OPCODE_MICROMIPS)
18536 md_number_to_chars (p, micromips_nop16_insn.insn_opcode, 2);
18541 /* Fall through. */
18544 /* Fall through. */
18549 md_number_to_chars (p, opcode, size);
18550 fragp->fr_var = size;
18554 md_obj_begin (void)
18561 /* Check for premature end, nesting errors, etc. */
18563 as_warn (_("missing .end at end of assembly"));
18572 if (*input_line_pointer == '-')
18574 ++input_line_pointer;
18577 if (!ISDIGIT (*input_line_pointer))
18578 as_bad (_("expected simple number"));
18579 if (input_line_pointer[0] == '0')
18581 if (input_line_pointer[1] == 'x')
18583 input_line_pointer += 2;
18584 while (ISXDIGIT (*input_line_pointer))
18587 val |= hex_value (*input_line_pointer++);
18589 return negative ? -val : val;
18593 ++input_line_pointer;
18594 while (ISDIGIT (*input_line_pointer))
18597 val |= *input_line_pointer++ - '0';
18599 return negative ? -val : val;
18602 if (!ISDIGIT (*input_line_pointer))
18604 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18605 *input_line_pointer, *input_line_pointer);
18606 as_warn (_("invalid number"));
18609 while (ISDIGIT (*input_line_pointer))
18612 val += *input_line_pointer++ - '0';
18614 return negative ? -val : val;
18617 /* The .file directive; just like the usual .file directive, but there
18618 is an initial number which is the ECOFF file index. In the non-ECOFF
18619 case .file implies DWARF-2. */
18622 s_mips_file (int x ATTRIBUTE_UNUSED)
18624 static int first_file_directive = 0;
18626 if (ECOFF_DEBUGGING)
18635 filename = dwarf2_directive_file (0);
18637 /* Versions of GCC up to 3.1 start files with a ".file"
18638 directive even for stabs output. Make sure that this
18639 ".file" is handled. Note that you need a version of GCC
18640 after 3.1 in order to support DWARF-2 on MIPS. */
18641 if (filename != NULL && ! first_file_directive)
18643 (void) new_logical_line (filename, -1);
18644 s_app_file_string (filename, 0);
18646 first_file_directive = 1;
18650 /* The .loc directive, implying DWARF-2. */
18653 s_mips_loc (int x ATTRIBUTE_UNUSED)
18655 if (!ECOFF_DEBUGGING)
18656 dwarf2_directive_loc (0);
18659 /* The .end directive. */
18662 s_mips_end (int x ATTRIBUTE_UNUSED)
18666 /* Following functions need their own .frame and .cprestore directives. */
18667 mips_frame_reg_valid = 0;
18668 mips_cprestore_valid = 0;
18670 if (!is_end_of_line[(unsigned char) *input_line_pointer])
18673 demand_empty_rest_of_line ();
18678 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
18679 as_warn (_(".end not in text section"));
18683 as_warn (_(".end directive without a preceding .ent directive."));
18684 demand_empty_rest_of_line ();
18690 gas_assert (S_GET_NAME (p));
18691 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
18692 as_warn (_(".end symbol does not match .ent symbol."));
18694 if (debug_type == DEBUG_STABS)
18695 stabs_generate_asm_endfunc (S_GET_NAME (p),
18699 as_warn (_(".end directive missing or unknown symbol"));
18702 /* Create an expression to calculate the size of the function. */
18703 if (p && cur_proc_ptr)
18705 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
18706 expressionS *exp = xmalloc (sizeof (expressionS));
18709 exp->X_op = O_subtract;
18710 exp->X_add_symbol = symbol_temp_new_now ();
18711 exp->X_op_symbol = p;
18712 exp->X_add_number = 0;
18714 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
18717 /* Generate a .pdr section. */
18718 if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr)
18720 segT saved_seg = now_seg;
18721 subsegT saved_subseg = now_subseg;
18725 #ifdef md_flush_pending_output
18726 md_flush_pending_output ();
18729 gas_assert (pdr_seg);
18730 subseg_set (pdr_seg, 0);
18732 /* Write the symbol. */
18733 exp.X_op = O_symbol;
18734 exp.X_add_symbol = p;
18735 exp.X_add_number = 0;
18736 emit_expr (&exp, 4);
18738 fragp = frag_more (7 * 4);
18740 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
18741 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
18742 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
18743 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
18744 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
18745 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
18746 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
18748 subseg_set (saved_seg, saved_subseg);
18750 #endif /* OBJ_ELF */
18752 cur_proc_ptr = NULL;
18755 /* The .aent and .ent directives. */
18758 s_mips_ent (int aent)
18762 symbolP = get_symbol ();
18763 if (*input_line_pointer == ',')
18764 ++input_line_pointer;
18765 SKIP_WHITESPACE ();
18766 if (ISDIGIT (*input_line_pointer)
18767 || *input_line_pointer == '-')
18770 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
18771 as_warn (_(".ent or .aent not in text section."));
18773 if (!aent && cur_proc_ptr)
18774 as_warn (_("missing .end"));
18778 /* This function needs its own .frame and .cprestore directives. */
18779 mips_frame_reg_valid = 0;
18780 mips_cprestore_valid = 0;
18782 cur_proc_ptr = &cur_proc;
18783 memset (cur_proc_ptr, '\0', sizeof (procS));
18785 cur_proc_ptr->func_sym = symbolP;
18789 if (debug_type == DEBUG_STABS)
18790 stabs_generate_asm_func (S_GET_NAME (symbolP),
18791 S_GET_NAME (symbolP));
18794 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
18796 demand_empty_rest_of_line ();
18799 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
18800 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
18801 s_mips_frame is used so that we can set the PDR information correctly.
18802 We can't use the ecoff routines because they make reference to the ecoff
18803 symbol table (in the mdebug section). */
18806 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
18809 if (IS_ELF && !ECOFF_DEBUGGING)
18813 if (cur_proc_ptr == (procS *) NULL)
18815 as_warn (_(".frame outside of .ent"));
18816 demand_empty_rest_of_line ();
18820 cur_proc_ptr->frame_reg = tc_get_register (1);
18822 SKIP_WHITESPACE ();
18823 if (*input_line_pointer++ != ','
18824 || get_absolute_expression_and_terminator (&val) != ',')
18826 as_warn (_("Bad .frame directive"));
18827 --input_line_pointer;
18828 demand_empty_rest_of_line ();
18832 cur_proc_ptr->frame_offset = val;
18833 cur_proc_ptr->pc_reg = tc_get_register (0);
18835 demand_empty_rest_of_line ();
18838 #endif /* OBJ_ELF */
18842 /* The .fmask and .mask directives. If the mdebug section is present
18843 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
18844 embedded targets, s_mips_mask is used so that we can set the PDR
18845 information correctly. We can't use the ecoff routines because they
18846 make reference to the ecoff symbol table (in the mdebug section). */
18849 s_mips_mask (int reg_type)
18852 if (IS_ELF && !ECOFF_DEBUGGING)
18856 if (cur_proc_ptr == (procS *) NULL)
18858 as_warn (_(".mask/.fmask outside of .ent"));
18859 demand_empty_rest_of_line ();
18863 if (get_absolute_expression_and_terminator (&mask) != ',')
18865 as_warn (_("Bad .mask/.fmask directive"));
18866 --input_line_pointer;
18867 demand_empty_rest_of_line ();
18871 off = get_absolute_expression ();
18873 if (reg_type == 'F')
18875 cur_proc_ptr->fpreg_mask = mask;
18876 cur_proc_ptr->fpreg_offset = off;
18880 cur_proc_ptr->reg_mask = mask;
18881 cur_proc_ptr->reg_offset = off;
18884 demand_empty_rest_of_line ();
18887 #endif /* OBJ_ELF */
18888 s_ignore (reg_type);
18891 /* A table describing all the processors gas knows about. Names are
18892 matched in the order listed.
18894 To ease comparison, please keep this table in the same order as
18895 gcc's mips_cpu_info_table[]. */
18896 static const struct mips_cpu_info mips_cpu_info_table[] =
18898 /* Entries for generic ISAs */
18899 { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 },
18900 { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 },
18901 { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 },
18902 { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 },
18903 { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 },
18904 { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 },
18905 { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 },
18906 { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
18907 { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
18910 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
18911 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
18912 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
18915 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
18918 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
18919 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
18920 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
18921 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
18922 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
18923 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
18924 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
18925 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
18926 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
18927 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
18928 { "orion", 0, ISA_MIPS3, CPU_R4600 },
18929 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
18930 /* ST Microelectronics Loongson 2E and 2F cores */
18931 { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E },
18932 { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F },
18935 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
18936 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
18937 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
18938 { "r14000", 0, ISA_MIPS4, CPU_R14000 },
18939 { "r16000", 0, ISA_MIPS4, CPU_R16000 },
18940 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
18941 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
18942 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
18943 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
18944 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
18945 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
18946 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
18947 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
18948 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
18949 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
18952 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
18953 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
18954 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
18955 { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
18957 /* MIPS 32 Release 2 */
18958 { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18959 { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18960 { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18961 { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
18962 { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18963 { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18964 { "m14k", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
18965 { "m14kc", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
18966 { "m14ke", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU,
18967 ISA_MIPS32R2, CPU_MIPS32R2 },
18968 { "m14kec", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU,
18969 ISA_MIPS32R2, CPU_MIPS32R2 },
18970 { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18971 { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18972 { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18973 { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18974 /* Deprecated forms of the above. */
18975 { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18976 { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18977 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
18978 { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18979 { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18980 { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18981 { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18982 /* Deprecated forms of the above. */
18983 { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18984 { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18985 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
18986 { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18987 ISA_MIPS32R2, CPU_MIPS32R2 },
18988 { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18989 ISA_MIPS32R2, CPU_MIPS32R2 },
18990 { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18991 ISA_MIPS32R2, CPU_MIPS32R2 },
18992 { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18993 ISA_MIPS32R2, CPU_MIPS32R2 },
18994 /* Deprecated forms of the above. */
18995 { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18996 ISA_MIPS32R2, CPU_MIPS32R2 },
18997 { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18998 ISA_MIPS32R2, CPU_MIPS32R2 },
18999 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19000 { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19001 ISA_MIPS32R2, CPU_MIPS32R2 },
19002 { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19003 ISA_MIPS32R2, CPU_MIPS32R2 },
19004 { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19005 ISA_MIPS32R2, CPU_MIPS32R2 },
19006 { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19007 ISA_MIPS32R2, CPU_MIPS32R2 },
19008 { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19009 ISA_MIPS32R2, CPU_MIPS32R2 },
19010 /* Deprecated forms of the above. */
19011 { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19012 ISA_MIPS32R2, CPU_MIPS32R2 },
19013 { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19014 ISA_MIPS32R2, CPU_MIPS32R2 },
19015 /* 1004K cores are multiprocessor versions of the 34K. */
19016 { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19017 ISA_MIPS32R2, CPU_MIPS32R2 },
19018 { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19019 ISA_MIPS32R2, CPU_MIPS32R2 },
19020 { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19021 ISA_MIPS32R2, CPU_MIPS32R2 },
19022 { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19023 ISA_MIPS32R2, CPU_MIPS32R2 },
19026 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
19027 { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
19028 { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19029 { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19031 /* Broadcom SB-1 CPU core */
19032 { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
19033 ISA_MIPS64, CPU_SB1 },
19034 /* Broadcom SB-1A CPU core */
19035 { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
19036 ISA_MIPS64, CPU_SB1 },
19038 { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A },
19040 /* MIPS 64 Release 2 */
19042 /* Cavium Networks Octeon CPU core */
19043 { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
19046 { "xlr", 0, ISA_MIPS64, CPU_XLR },
19053 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19054 with a final "000" replaced by "k". Ignore case.
19056 Note: this function is shared between GCC and GAS. */
19059 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
19061 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
19062 given++, canonical++;
19064 return ((*given == 0 && *canonical == 0)
19065 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
19069 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19070 CPU name. We've traditionally allowed a lot of variation here.
19072 Note: this function is shared between GCC and GAS. */
19075 mips_matching_cpu_name_p (const char *canonical, const char *given)
19077 /* First see if the name matches exactly, or with a final "000"
19078 turned into "k". */
19079 if (mips_strict_matching_cpu_name_p (canonical, given))
19082 /* If not, try comparing based on numerical designation alone.
19083 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19084 if (TOLOWER (*given) == 'r')
19086 if (!ISDIGIT (*given))
19089 /* Skip over some well-known prefixes in the canonical name,
19090 hoping to find a number there too. */
19091 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
19093 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
19095 else if (TOLOWER (canonical[0]) == 'r')
19098 return mips_strict_matching_cpu_name_p (canonical, given);
19102 /* Parse an option that takes the name of a processor as its argument.
19103 OPTION is the name of the option and CPU_STRING is the argument.
19104 Return the corresponding processor enumeration if the CPU_STRING is
19105 recognized, otherwise report an error and return null.
19107 A similar function exists in GCC. */
19109 static const struct mips_cpu_info *
19110 mips_parse_cpu (const char *option, const char *cpu_string)
19112 const struct mips_cpu_info *p;
19114 /* 'from-abi' selects the most compatible architecture for the given
19115 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19116 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19117 version. Look first at the -mgp options, if given, otherwise base
19118 the choice on MIPS_DEFAULT_64BIT.
19120 Treat NO_ABI like the EABIs. One reason to do this is that the
19121 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19122 architecture. This code picks MIPS I for 'mips' and MIPS III for
19123 'mips64', just as we did in the days before 'from-abi'. */
19124 if (strcasecmp (cpu_string, "from-abi") == 0)
19126 if (ABI_NEEDS_32BIT_REGS (mips_abi))
19127 return mips_cpu_info_from_isa (ISA_MIPS1);
19129 if (ABI_NEEDS_64BIT_REGS (mips_abi))
19130 return mips_cpu_info_from_isa (ISA_MIPS3);
19132 if (file_mips_gp32 >= 0)
19133 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
19135 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19140 /* 'default' has traditionally been a no-op. Probably not very useful. */
19141 if (strcasecmp (cpu_string, "default") == 0)
19144 for (p = mips_cpu_info_table; p->name != 0; p++)
19145 if (mips_matching_cpu_name_p (p->name, cpu_string))
19148 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
19152 /* Return the canonical processor information for ISA (a member of the
19153 ISA_MIPS* enumeration). */
19155 static const struct mips_cpu_info *
19156 mips_cpu_info_from_isa (int isa)
19160 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19161 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
19162 && isa == mips_cpu_info_table[i].isa)
19163 return (&mips_cpu_info_table[i]);
19168 static const struct mips_cpu_info *
19169 mips_cpu_info_from_arch (int arch)
19173 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19174 if (arch == mips_cpu_info_table[i].cpu)
19175 return (&mips_cpu_info_table[i]);
19181 show (FILE *stream, const char *string, int *col_p, int *first_p)
19185 fprintf (stream, "%24s", "");
19190 fprintf (stream, ", ");
19194 if (*col_p + strlen (string) > 72)
19196 fprintf (stream, "\n%24s", "");
19200 fprintf (stream, "%s", string);
19201 *col_p += strlen (string);
19207 md_show_usage (FILE *stream)
19212 fprintf (stream, _("\
19214 -EB generate big endian output\n\
19215 -EL generate little endian output\n\
19216 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19217 -G NUM allow referencing objects up to NUM bytes\n\
19218 implicitly with the gp register [default 8]\n"));
19219 fprintf (stream, _("\
19220 -mips1 generate MIPS ISA I instructions\n\
19221 -mips2 generate MIPS ISA II instructions\n\
19222 -mips3 generate MIPS ISA III instructions\n\
19223 -mips4 generate MIPS ISA IV instructions\n\
19224 -mips5 generate MIPS ISA V instructions\n\
19225 -mips32 generate MIPS32 ISA instructions\n\
19226 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19227 -mips64 generate MIPS64 ISA instructions\n\
19228 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19229 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19233 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19234 show (stream, mips_cpu_info_table[i].name, &column, &first);
19235 show (stream, "from-abi", &column, &first);
19236 fputc ('\n', stream);
19238 fprintf (stream, _("\
19239 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19240 -no-mCPU don't generate code specific to CPU.\n\
19241 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19245 show (stream, "3900", &column, &first);
19246 show (stream, "4010", &column, &first);
19247 show (stream, "4100", &column, &first);
19248 show (stream, "4650", &column, &first);
19249 fputc ('\n', stream);
19251 fprintf (stream, _("\
19252 -mips16 generate mips16 instructions\n\
19253 -no-mips16 do not generate mips16 instructions\n"));
19254 fprintf (stream, _("\
19255 -mmicromips generate microMIPS instructions\n\
19256 -mno-micromips do not generate microMIPS instructions\n"));
19257 fprintf (stream, _("\
19258 -msmartmips generate smartmips instructions\n\
19259 -mno-smartmips do not generate smartmips instructions\n"));
19260 fprintf (stream, _("\
19261 -mdsp generate DSP instructions\n\
19262 -mno-dsp do not generate DSP instructions\n"));
19263 fprintf (stream, _("\
19264 -mdspr2 generate DSP R2 instructions\n\
19265 -mno-dspr2 do not generate DSP R2 instructions\n"));
19266 fprintf (stream, _("\
19267 -mmt generate MT instructions\n\
19268 -mno-mt do not generate MT instructions\n"));
19269 fprintf (stream, _("\
19270 -mmcu generate MCU instructions\n\
19271 -mno-mcu do not generate MCU instructions\n"));
19272 fprintf (stream, _("\
19273 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19274 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19275 -mfix-vr4120 work around certain VR4120 errata\n\
19276 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19277 -mfix-24k insert a nop after ERET and DERET instructions\n\
19278 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19279 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19280 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19281 -msym32 assume all symbols have 32-bit values\n\
19282 -O0 remove unneeded NOPs, do not swap branches\n\
19283 -O remove unneeded NOPs and swap branches\n\
19284 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19285 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19286 fprintf (stream, _("\
19287 -mhard-float allow floating-point instructions\n\
19288 -msoft-float do not allow floating-point instructions\n\
19289 -msingle-float only allow 32-bit floating-point operations\n\
19290 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19291 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
19294 fprintf (stream, _("\
19295 -KPIC, -call_shared generate SVR4 position independent code\n\
19296 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19297 -mvxworks-pic generate VxWorks position independent code\n\
19298 -non_shared do not generate code that can operate with DSOs\n\
19299 -xgot assume a 32 bit GOT\n\
19300 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19301 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19302 position dependent (non shared) code\n\
19303 -mabi=ABI create ABI conformant object file for:\n"));
19307 show (stream, "32", &column, &first);
19308 show (stream, "o64", &column, &first);
19309 show (stream, "n32", &column, &first);
19310 show (stream, "64", &column, &first);
19311 show (stream, "eabi", &column, &first);
19313 fputc ('\n', stream);
19315 fprintf (stream, _("\
19316 -32 create o32 ABI object file (default)\n\
19317 -n32 create n32 ABI object file\n\
19318 -64 create 64 ABI object file\n"));
19324 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
19326 if (HAVE_64BIT_SYMBOLS)
19327 return dwarf2_format_64bit_irix;
19329 return dwarf2_format_32bit;
19334 mips_dwarf2_addr_size (void)
19336 if (HAVE_64BIT_OBJECTS)
19342 /* Standard calling conventions leave the CFA at SP on entry. */
19344 mips_cfi_frame_initial_instructions (void)
19346 cfi_add_CFA_def_cfa_register (SP);
19350 tc_mips_regname_to_dw2regnum (char *regname)
19352 unsigned int regnum = -1;
19355 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))