1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR; }
51 #undef OBJ_PROCESS_STAB
58 #undef obj_frob_file_after_relocs
59 #undef obj_frob_symbol
61 #undef obj_sec_sym_ok_for_reloc
62 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
65 /* Fix any of them that we actually care about. */
67 #define OUTPUT_FLAVOR mips_output_flavor()
74 #ifndef ECOFF_DEBUGGING
75 #define NO_ECOFF_DEBUGGING
76 #define ECOFF_DEBUGGING 0
81 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
82 static char *mips_regmask_frag;
87 #define PIC_CALL_REG 25
95 #define ILLEGAL_REG (32)
97 /* Allow override of standard little-endian ECOFF format. */
99 #ifndef ECOFF_LITTLE_FORMAT
100 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
103 extern int target_big_endian;
105 /* The name of the readonly data section. */
106 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
108 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
110 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
112 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
116 /* The ABI to use. */
127 /* MIPS ABI we are using for this output file. */
128 static enum mips_abi_level file_mips_abi = NO_ABI;
130 /* This is the set of options which may be modified by the .set
131 pseudo-op. We use a struct so that .set push and .set pop are more
134 struct mips_set_options
136 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
137 if it has not been initialized. Changed by `.set mipsN', and the
138 -mipsN command line option, and the default CPU. */
140 /* Enabled Application Specific Extensions (ASEs). These are set to -1
141 if they have not been initialized. Changed by `.set <asename>', by
142 command line options, and based on the default architecture. */
145 /* Whether we are assembling for the mips16 processor. 0 if we are
146 not, 1 if we are, and -1 if the value has not been initialized.
147 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
148 -nomips16 command line options, and the default CPU. */
150 /* Non-zero if we should not reorder instructions. Changed by `.set
151 reorder' and `.set noreorder'. */
153 /* Non-zero if we should not permit the $at ($1) register to be used
154 in instructions. Changed by `.set at' and `.set noat'. */
156 /* Non-zero if we should warn when a macro instruction expands into
157 more than one machine instruction. Changed by `.set nomacro' and
159 int warn_about_macros;
160 /* Non-zero if we should not move instructions. Changed by `.set
161 move', `.set volatile', `.set nomove', and `.set novolatile'. */
163 /* Non-zero if we should not optimize branches by moving the target
164 of the branch into the delay slot. Actually, we don't perform
165 this optimization anyhow. Changed by `.set bopt' and `.set
168 /* Non-zero if we should not autoextend mips16 instructions.
169 Changed by `.set autoextend' and `.set noautoextend'. */
171 /* Restrict general purpose registers and floating point registers
172 to 32 bit. This is initially determined when -mgp32 or -mfp32
173 is passed but can changed if the assembler code uses .set mipsN. */
176 /* The ABI currently in use. This is changed by .set mipsN to loosen
177 restrictions and doesn't affect the whole file. */
178 enum mips_abi_level abi;
181 /* True if -mgp32 was passed. */
182 static int file_mips_gp32 = -1;
184 /* True if -mfp32 was passed. */
185 static int file_mips_fp32 = -1;
187 /* This is the struct we use to hold the current set of options. Note
188 that we must set the isa field to ISA_UNKNOWN and the mips16 field to
189 -1 to indicate that they have not been initialized. */
191 static struct mips_set_options mips_opts =
193 ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, NO_ABI
196 /* These variables are filled in with the masks of registers used.
197 The object format code reads them and puts them in the appropriate
199 unsigned long mips_gprmask;
200 unsigned long mips_cprmask[4];
202 /* MIPS ISA we are using for this output file. */
203 static int file_mips_isa = ISA_UNKNOWN;
205 /* True if -mips3d was passed or implied by arguments passed on the
206 command line (e.g., by -march). */
207 static int file_ase_mips3d;
209 /* True if -mdmx was passed or implied by arguments passed on the
210 command line (e.g., by -march). */
211 static int file_ase_mdmx;
213 /* The argument of the -mcpu= flag. Historical for code generation. */
214 static int mips_cpu = CPU_UNKNOWN;
216 /* The argument of the -march= flag. The architecture we are assembling. */
217 static int mips_arch = CPU_UNKNOWN;
219 /* The argument of the -mtune= flag. The architecture for which we
221 static int mips_tune = CPU_UNKNOWN;
223 /* Whether we should mark the file EABI64 or EABI32. */
224 static int mips_eabi64 = 0;
226 /* If they asked for mips1 or mips2 and a cpu that is
227 mips3 or greater, then mark the object file 32BITMODE. */
228 static int mips_32bitmode = 0;
230 /* Some ISA's have delay slots for instructions which read or write
231 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
232 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
233 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
234 delay slot in this ISA. The uses of this macro assume that any
235 ISA that has delay slots for one of these, has them for all. They
236 also assume that ISAs which don't have delays for these insns, don't
237 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
238 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
240 || (ISA) == ISA_MIPS2 \
241 || (ISA) == ISA_MIPS3 \
244 /* Return true if ISA supports 64 bit gp register instructions. */
245 #define ISA_HAS_64BIT_REGS(ISA) ( \
247 || (ISA) == ISA_MIPS4 \
248 || (ISA) == ISA_MIPS5 \
249 || (ISA) == ISA_MIPS64 \
252 #define HAVE_32BIT_GPRS \
254 || mips_opts.abi == O32_ABI \
255 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
257 #define HAVE_32BIT_FPRS \
259 || mips_opts.abi == O32_ABI \
260 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
262 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
263 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
265 #define HAVE_NEWABI (mips_opts.abi == N32_ABI || mips_opts.abi == N64_ABI)
267 #define HAVE_64BIT_OBJECTS (mips_opts.abi == N64_ABI)
269 /* We can only have 64bit addresses if the object file format
271 #define HAVE_32BIT_ADDRESSES \
273 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
274 || ! HAVE_64BIT_OBJECTS) \
275 && mips_pic != EMBEDDED_PIC))
277 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
279 /* Return true if the given CPU supports the MIPS3D ASE. */
280 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
283 /* Return true if the given CPU supports the MDMX ASE. */
284 #define CPU_HAS_MDMX(cpu) (0 \
287 /* Whether the processor uses hardware interlocks to protect
288 reads from the HI and LO registers, and thus does not
289 require nops to be inserted. */
291 #define hilo_interlocks (mips_arch == CPU_R4010 \
292 || mips_arch == CPU_SB1 \
295 /* Whether the processor uses hardware interlocks to protect reads
296 from the GPRs, and thus does not require nops to be inserted. */
297 #define gpr_interlocks \
298 (mips_opts.isa != ISA_MIPS1 \
299 || mips_arch == CPU_R3900)
301 /* As with other "interlocks" this is used by hardware that has FP
302 (co-processor) interlocks. */
303 /* Itbl support may require additional care here. */
304 #define cop_interlocks (mips_arch == CPU_R4300 \
305 || mips_arch == CPU_SB1 \
308 /* Is this a mfhi or mflo instruction? */
309 #define MF_HILO_INSN(PINFO) \
310 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
312 /* MIPS PIC level. */
316 /* Do not generate PIC code. */
319 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
320 not sure what it is supposed to do. */
323 /* Generate PIC code as in the SVR4 MIPS ABI. */
326 /* Generate PIC code without using a global offset table: the data
327 segment has a maximum size of 64K, all data references are off
328 the $gp register, and all text references are PC relative. This
329 is used on some embedded systems. */
333 static enum mips_pic_level mips_pic;
335 /* Warn about all NOPS that the assembler generates. */
336 static int warn_nops = 0;
338 /* 1 if we should generate 32 bit offsets from the $gp register in
339 SVR4_PIC mode. Currently has no meaning in other modes. */
340 static int mips_big_got = 0;
342 /* 1 if trap instructions should used for overflow rather than break
344 static int mips_trap = 0;
346 /* 1 if double width floating point constants should not be constructed
347 by assembling two single width halves into two single width floating
348 point registers which just happen to alias the double width destination
349 register. On some architectures this aliasing can be disabled by a bit
350 in the status register, and the setting of this bit cannot be determined
351 automatically at assemble time. */
352 static int mips_disable_float_construction;
354 /* Non-zero if any .set noreorder directives were used. */
356 static int mips_any_noreorder;
358 /* Non-zero if nops should be inserted when the register referenced in
359 an mfhi/mflo instruction is read in the next two instructions. */
360 static int mips_7000_hilo_fix;
362 /* The size of the small data section. */
363 static unsigned int g_switch_value = 8;
364 /* Whether the -G option was used. */
365 static int g_switch_seen = 0;
370 /* If we can determine in advance that GP optimization won't be
371 possible, we can skip the relaxation stuff that tries to produce
372 GP-relative references. This makes delay slot optimization work
375 This function can only provide a guess, but it seems to work for
376 gcc output. It needs to guess right for gcc, otherwise gcc
377 will put what it thinks is a GP-relative instruction in a branch
380 I don't know if a fix is needed for the SVR4_PIC mode. I've only
381 fixed it for the non-PIC mode. KR 95/04/07 */
382 static int nopic_need_relax PARAMS ((symbolS *, int));
384 /* handle of the OPCODE hash table */
385 static struct hash_control *op_hash = NULL;
387 /* The opcode hash table we use for the mips16. */
388 static struct hash_control *mips16_op_hash = NULL;
390 /* This array holds the chars that always start a comment. If the
391 pre-processor is disabled, these aren't very useful */
392 const char comment_chars[] = "#";
394 /* This array holds the chars that only start a comment at the beginning of
395 a line. If the line seems to have the form '# 123 filename'
396 .line and .file directives will appear in the pre-processed output */
397 /* Note that input_file.c hand checks for '#' at the beginning of the
398 first line of the input file. This is because the compiler outputs
399 #NO_APP at the beginning of its output. */
400 /* Also note that C style comments are always supported. */
401 const char line_comment_chars[] = "#";
403 /* This array holds machine specific line separator characters. */
404 const char line_separator_chars[] = ";";
406 /* Chars that can be used to separate mant from exp in floating point nums */
407 const char EXP_CHARS[] = "eE";
409 /* Chars that mean this number is a floating point constant */
412 const char FLT_CHARS[] = "rRsSfFdDxXpP";
414 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
415 changed in read.c . Ideally it shouldn't have to know about it at all,
416 but nothing is ideal around here.
419 static char *insn_error;
421 static int auto_align = 1;
423 /* When outputting SVR4 PIC code, the assembler needs to know the
424 offset in the stack frame from which to restore the $gp register.
425 This is set by the .cprestore pseudo-op, and saved in this
427 static offsetT mips_cprestore_offset = -1;
429 /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some
430 more optimizations, it can use a register value instead of a memory-saved
431 offset and even an other register than $gp as global pointer. */
432 static offsetT mips_cpreturn_offset = -1;
433 static int mips_cpreturn_register = -1;
434 static int mips_gp_register = GP;
435 static int mips_gprel_offset = 0;
437 /* Whether mips_cprestore_offset has been set in the current function
438 (or whether it has already been warned about, if not). */
439 static int mips_cprestore_valid = 0;
441 /* This is the register which holds the stack frame, as set by the
442 .frame pseudo-op. This is needed to implement .cprestore. */
443 static int mips_frame_reg = SP;
445 /* Whether mips_frame_reg has been set in the current function
446 (or whether it has already been warned about, if not). */
447 static int mips_frame_reg_valid = 0;
449 /* To output NOP instructions correctly, we need to keep information
450 about the previous two instructions. */
452 /* Whether we are optimizing. The default value of 2 means to remove
453 unneeded NOPs and swap branch instructions when possible. A value
454 of 1 means to not swap branches. A value of 0 means to always
456 static int mips_optimize = 2;
458 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
459 equivalent to seeing no -g option at all. */
460 static int mips_debug = 0;
462 /* The previous instruction. */
463 static struct mips_cl_insn prev_insn;
465 /* The instruction before prev_insn. */
466 static struct mips_cl_insn prev_prev_insn;
468 /* If we don't want information for prev_insn or prev_prev_insn, we
469 point the insn_mo field at this dummy integer. */
470 static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 };
472 /* Non-zero if prev_insn is valid. */
473 static int prev_insn_valid;
475 /* The frag for the previous instruction. */
476 static struct frag *prev_insn_frag;
478 /* The offset into prev_insn_frag for the previous instruction. */
479 static long prev_insn_where;
481 /* The reloc type for the previous instruction, if any. */
482 static bfd_reloc_code_real_type prev_insn_reloc_type[3];
484 /* The reloc for the previous instruction, if any. */
485 static fixS *prev_insn_fixp[3];
487 /* Non-zero if the previous instruction was in a delay slot. */
488 static int prev_insn_is_delay_slot;
490 /* Non-zero if the previous instruction was in a .set noreorder. */
491 static int prev_insn_unreordered;
493 /* Non-zero if the previous instruction uses an extend opcode (if
495 static int prev_insn_extended;
497 /* Non-zero if the previous previous instruction was in a .set
499 static int prev_prev_insn_unreordered;
501 /* If this is set, it points to a frag holding nop instructions which
502 were inserted before the start of a noreorder section. If those
503 nops turn out to be unnecessary, the size of the frag can be
505 static fragS *prev_nop_frag;
507 /* The number of nop instructions we created in prev_nop_frag. */
508 static int prev_nop_frag_holds;
510 /* The number of nop instructions that we know we need in
512 static int prev_nop_frag_required;
514 /* The number of instructions we've seen since prev_nop_frag. */
515 static int prev_nop_frag_since;
517 /* For ECOFF and ELF, relocations against symbols are done in two
518 parts, with a HI relocation and a LO relocation. Each relocation
519 has only 16 bits of space to store an addend. This means that in
520 order for the linker to handle carries correctly, it must be able
521 to locate both the HI and the LO relocation. This means that the
522 relocations must appear in order in the relocation table.
524 In order to implement this, we keep track of each unmatched HI
525 relocation. We then sort them so that they immediately precede the
526 corresponding LO relocation. */
531 struct mips_hi_fixup *next;
534 /* The section this fixup is in. */
538 /* The list of unmatched HI relocs. */
540 static struct mips_hi_fixup *mips_hi_fixup_list;
542 /* Map normal MIPS register numbers to mips16 register numbers. */
544 #define X ILLEGAL_REG
545 static const int mips32_to_16_reg_map[] =
547 X, X, 2, 3, 4, 5, 6, 7,
548 X, X, X, X, X, X, X, X,
549 0, 1, X, X, X, X, X, X,
550 X, X, X, X, X, X, X, X
554 /* Map mips16 register numbers to normal MIPS register numbers. */
556 static const unsigned int mips16_to_32_reg_map[] =
558 16, 17, 2, 3, 4, 5, 6, 7
561 /* Since the MIPS does not have multiple forms of PC relative
562 instructions, we do not have to do relaxing as is done on other
563 platforms. However, we do have to handle GP relative addressing
564 correctly, which turns out to be a similar problem.
566 Every macro that refers to a symbol can occur in (at least) two
567 forms, one with GP relative addressing and one without. For
568 example, loading a global variable into a register generally uses
569 a macro instruction like this:
571 If i can be addressed off the GP register (this is true if it is in
572 the .sbss or .sdata section, or if it is known to be smaller than
573 the -G argument) this will generate the following instruction:
575 This instruction will use a GPREL reloc. If i can not be addressed
576 off the GP register, the following instruction sequence will be used:
579 In this case the first instruction will have a HI16 reloc, and the
580 second reloc will have a LO16 reloc. Both relocs will be against
583 The issue here is that we may not know whether i is GP addressable
584 until after we see the instruction that uses it. Therefore, we
585 want to be able to choose the final instruction sequence only at
586 the end of the assembly. This is similar to the way other
587 platforms choose the size of a PC relative instruction only at the
590 When generating position independent code we do not use GP
591 addressing in quite the same way, but the issue still arises as
592 external symbols and local symbols must be handled differently.
594 We handle these issues by actually generating both possible
595 instruction sequences. The longer one is put in a frag_var with
596 type rs_machine_dependent. We encode what to do with the frag in
597 the subtype field. We encode (1) the number of existing bytes to
598 replace, (2) the number of new bytes to use, (3) the offset from
599 the start of the existing bytes to the first reloc we must generate
600 (that is, the offset is applied from the start of the existing
601 bytes after they are replaced by the new bytes, if any), (4) the
602 offset from the start of the existing bytes to the second reloc,
603 (5) whether a third reloc is needed (the third reloc is always four
604 bytes after the second reloc), and (6) whether to warn if this
605 variant is used (this is sometimes needed if .set nomacro or .set
606 noat is in effect). All these numbers are reasonably small.
608 Generating two instruction sequences must be handled carefully to
609 ensure that delay slots are handled correctly. Fortunately, there
610 are a limited number of cases. When the second instruction
611 sequence is generated, append_insn is directed to maintain the
612 existing delay slot information, so it continues to apply to any
613 code after the second instruction sequence. This means that the
614 second instruction sequence must not impose any requirements not
615 required by the first instruction sequence.
617 These variant frags are then handled in functions called by the
618 machine independent code. md_estimate_size_before_relax returns
619 the final size of the frag. md_convert_frag sets up the final form
620 of the frag. tc_gen_reloc adjust the first reloc and adds a second
622 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
626 | (((reloc1) + 64) << 9) \
627 | (((reloc2) + 64) << 2) \
628 | ((reloc3) ? (1 << 1) : 0) \
630 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
631 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
632 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
633 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
634 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
635 #define RELAX_WARN(i) ((i) & 1)
637 /* For mips16 code, we use an entirely different form of relaxation.
638 mips16 supports two versions of most instructions which take
639 immediate values: a small one which takes some small value, and a
640 larger one which takes a 16 bit value. Since branches also follow
641 this pattern, relaxing these values is required.
643 We can assemble both mips16 and normal MIPS code in a single
644 object. Therefore, we need to support this type of relaxation at
645 the same time that we support the relaxation described above. We
646 use the high bit of the subtype field to distinguish these cases.
648 The information we store for this type of relaxation is the
649 argument code found in the opcode file for this relocation, whether
650 the user explicitly requested a small or extended form, and whether
651 the relocation is in a jump or jal delay slot. That tells us the
652 size of the value, and how it should be stored. We also store
653 whether the fragment is considered to be extended or not. We also
654 store whether this is known to be a branch to a different section,
655 whether we have tried to relax this frag yet, and whether we have
656 ever extended a PC relative fragment because of a shift count. */
657 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
660 | ((small) ? 0x100 : 0) \
661 | ((ext) ? 0x200 : 0) \
662 | ((dslot) ? 0x400 : 0) \
663 | ((jal_dslot) ? 0x800 : 0))
664 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
665 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
666 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
667 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
668 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
669 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
670 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
671 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
672 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
673 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
674 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
675 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
677 /* Prototypes for static functions. */
680 #define internalError() \
681 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
683 #define internalError() as_fatal (_("MIPS internal Error"));
686 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
688 static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip,
689 unsigned int reg, enum mips_regclass class));
690 static int reg_needs_delay PARAMS ((unsigned int));
691 static void mips16_mark_labels PARAMS ((void));
692 static void append_insn PARAMS ((char *place,
693 struct mips_cl_insn * ip,
695 bfd_reloc_code_real_type *r,
697 static void mips_no_prev_insn PARAMS ((int));
698 static void mips_emit_delays PARAMS ((boolean));
700 static void macro_build PARAMS ((char *place, int *counter, expressionS * ep,
701 const char *name, const char *fmt,
704 static void macro_build ();
706 static void mips16_macro_build PARAMS ((char *, int *, expressionS *,
707 const char *, const char *,
709 static void macro_build_jalr PARAMS ((int, expressionS *));
710 static void macro_build_lui PARAMS ((char *place, int *counter,
711 expressionS * ep, int regnum));
712 static void set_at PARAMS ((int *counter, int reg, int unsignedp));
713 static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip,
715 static void load_register PARAMS ((int *, int, expressionS *, int));
716 static void load_address PARAMS ((int *, int, expressionS *, int *));
717 static void move_register PARAMS ((int *, int, int));
718 static void macro PARAMS ((struct mips_cl_insn * ip));
719 static void mips16_macro PARAMS ((struct mips_cl_insn * ip));
720 #ifdef LOSING_COMPILER
721 static void macro2 PARAMS ((struct mips_cl_insn * ip));
723 static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip));
724 static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip));
725 static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean,
726 boolean, boolean, unsigned long *,
727 boolean *, unsigned short *));
728 static int my_getPercentOp PARAMS ((char **, unsigned int *, int *));
729 static int my_getSmallParser PARAMS ((char **, unsigned int *, int *));
730 static int my_getSmallExpression PARAMS ((expressionS *, char *));
731 static void my_getExpression PARAMS ((expressionS *, char *));
733 static int support_64bit_objects PARAMS((void));
735 static symbolS *get_symbol PARAMS ((void));
736 static void mips_align PARAMS ((int to, int fill, symbolS *label));
737 static void s_align PARAMS ((int));
738 static void s_change_sec PARAMS ((int));
739 static void s_cons PARAMS ((int));
740 static void s_float_cons PARAMS ((int));
741 static void s_mips_globl PARAMS ((int));
742 static void s_option PARAMS ((int));
743 static void s_mipsset PARAMS ((int));
744 static void s_abicalls PARAMS ((int));
745 static void s_cpload PARAMS ((int));
746 static void s_cpsetup PARAMS ((int));
747 static void s_cplocal PARAMS ((int));
748 static void s_cprestore PARAMS ((int));
749 static void s_cpreturn PARAMS ((int));
750 static void s_gpvalue PARAMS ((int));
751 static void s_gpword PARAMS ((int));
752 static void s_cpadd PARAMS ((int));
753 static void s_insn PARAMS ((int));
754 static void md_obj_begin PARAMS ((void));
755 static void md_obj_end PARAMS ((void));
756 static long get_number PARAMS ((void));
757 static void s_mips_ent PARAMS ((int));
758 static void s_mips_end PARAMS ((int));
759 static void s_mips_frame PARAMS ((int));
760 static void s_mips_mask PARAMS ((int));
761 static void s_mips_stab PARAMS ((int));
762 static void s_mips_weakext PARAMS ((int));
763 static void s_file PARAMS ((int));
764 static int mips16_extended_frag PARAMS ((fragS *, asection *, long));
765 static const char *mips_isa_to_str PARAMS ((int));
766 static const char *mips_cpu_to_str PARAMS ((int));
767 static int validate_mips_insn PARAMS ((const struct mips_opcode *));
768 static void show PARAMS ((FILE *, char *, int *, int *));
770 static int mips_need_elf_addend_fixup PARAMS ((fixS *));
773 /* Return values of my_getSmallExpression(). */
780 /* Direct relocation creation by %percent_op(). */
799 /* Table and functions used to map between CPU/ISA names, and
800 ISA levels, and CPU numbers. */
804 const char *name; /* CPU or ISA name. */
805 int is_isa; /* Is this an ISA? (If 0, a CPU.) */
806 int isa; /* ISA level. */
807 int cpu; /* CPU number (default CPU if ISA). */
810 static const struct mips_cpu_info *mips_cpu_info_from_name PARAMS ((const char *));
811 static const struct mips_cpu_info *mips_cpu_info_from_isa PARAMS ((int));
812 static const struct mips_cpu_info *mips_cpu_info_from_cpu PARAMS ((int));
816 The following pseudo-ops from the Kane and Heinrich MIPS book
817 should be defined here, but are currently unsupported: .alias,
818 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
820 The following pseudo-ops from the Kane and Heinrich MIPS book are
821 specific to the type of debugging information being generated, and
822 should be defined by the object format: .aent, .begin, .bend,
823 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
826 The following pseudo-ops from the Kane and Heinrich MIPS book are
827 not MIPS CPU specific, but are also not specific to the object file
828 format. This file is probably the best place to define them, but
829 they are not currently supported: .asm0, .endr, .lab, .repeat,
832 static const pseudo_typeS mips_pseudo_table[] =
834 /* MIPS specific pseudo-ops. */
835 {"option", s_option, 0},
836 {"set", s_mipsset, 0},
837 {"rdata", s_change_sec, 'r'},
838 {"sdata", s_change_sec, 's'},
839 {"livereg", s_ignore, 0},
840 {"abicalls", s_abicalls, 0},
841 {"cpload", s_cpload, 0},
842 {"cpsetup", s_cpsetup, 0},
843 {"cplocal", s_cplocal, 0},
844 {"cprestore", s_cprestore, 0},
845 {"cpreturn", s_cpreturn, 0},
846 {"gpvalue", s_gpvalue, 0},
847 {"gpword", s_gpword, 0},
848 {"cpadd", s_cpadd, 0},
851 /* Relatively generic pseudo-ops that happen to be used on MIPS
853 {"asciiz", stringer, 1},
854 {"bss", s_change_sec, 'b'},
857 {"dword", s_cons, 3},
858 {"weakext", s_mips_weakext, 0},
860 /* These pseudo-ops are defined in read.c, but must be overridden
861 here for one reason or another. */
862 {"align", s_align, 0},
864 {"data", s_change_sec, 'd'},
865 {"double", s_float_cons, 'd'},
866 {"float", s_float_cons, 'f'},
867 {"globl", s_mips_globl, 0},
868 {"global", s_mips_globl, 0},
869 {"hword", s_cons, 1},
874 {"short", s_cons, 1},
875 {"single", s_float_cons, 'f'},
876 {"stabn", s_mips_stab, 'n'},
877 {"text", s_change_sec, 't'},
880 #ifdef MIPS_STABS_ELF
881 { "extern", ecoff_directive_extern, 0},
887 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
889 /* These pseudo-ops should be defined by the object file format.
890 However, a.out doesn't support them, so we have versions here. */
891 {"aent", s_mips_ent, 1},
892 {"bgnb", s_ignore, 0},
893 {"end", s_mips_end, 0},
894 {"endb", s_ignore, 0},
895 {"ent", s_mips_ent, 0},
897 {"fmask", s_mips_mask, 'F'},
898 {"frame", s_mips_frame, 0},
899 {"loc", s_ignore, 0},
900 {"mask", s_mips_mask, 'R'},
901 {"verstamp", s_ignore, 0},
905 extern void pop_insert PARAMS ((const pseudo_typeS *));
910 pop_insert (mips_pseudo_table);
911 if (! ECOFF_DEBUGGING)
912 pop_insert (mips_nonecoff_pseudo_table);
915 /* Symbols labelling the current insn. */
917 struct insn_label_list
919 struct insn_label_list *next;
923 static struct insn_label_list *insn_labels;
924 static struct insn_label_list *free_insn_labels;
926 static void mips_clear_insn_labels PARAMS ((void));
929 mips_clear_insn_labels ()
931 register struct insn_label_list **pl;
933 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
939 static char *expr_end;
941 /* Expressions which appear in instructions. These are set by
944 static expressionS imm_expr;
945 static expressionS offset_expr;
947 /* Relocs associated with imm_expr and offset_expr. */
949 static bfd_reloc_code_real_type imm_reloc[3]
950 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
951 static bfd_reloc_code_real_type offset_reloc[3]
952 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
954 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
956 static boolean imm_unmatched_hi;
958 /* These are set by mips16_ip if an explicit extension is used. */
960 static boolean mips16_small, mips16_ext;
962 #ifdef MIPS_STABS_ELF
963 /* The pdr segment for per procedure frame/regmask info */
969 mips_isa_to_str (isa)
972 const struct mips_cpu_info *ci;
975 ci = mips_cpu_info_from_isa (isa);
979 sprintf (s, "ISA#%d", isa);
984 mips_cpu_to_str (cpu)
987 const struct mips_cpu_info *ci;
990 ci = mips_cpu_info_from_cpu (cpu);
994 sprintf (s, "CPU#%d", cpu);
998 /* The default target format to use. */
1001 mips_target_format ()
1003 switch (OUTPUT_FLAVOR)
1005 case bfd_target_aout_flavour:
1006 return target_big_endian ? "a.out-mips-big" : "a.out-mips-little";
1007 case bfd_target_ecoff_flavour:
1008 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1009 case bfd_target_coff_flavour:
1011 case bfd_target_elf_flavour:
1013 /* This is traditional mips */
1014 return (target_big_endian
1015 ? (HAVE_64BIT_OBJECTS ? "elf64-tradbigmips"
1016 : "elf32-tradbigmips")
1017 : (HAVE_64BIT_OBJECTS ? "elf64-tradlittlemips"
1018 : "elf32-tradlittlemips"));
1020 return (target_big_endian
1021 ? (HAVE_64BIT_OBJECTS ? "elf64-bigmips" : "elf32-bigmips")
1022 : (HAVE_64BIT_OBJECTS ? "elf64-littlemips"
1023 : "elf32-littlemips"));
1031 /* This function is called once, at assembler startup time. It should
1032 set up all the tables, etc. that the MD part of the assembler will need. */
1037 register const char *retval = NULL;
1042 int mips_isa_from_cpu;
1043 int target_cpu_had_mips16 = 0;
1044 const struct mips_cpu_info *ci;
1046 /* GP relative stuff not working for PE */
1047 if (strncmp (TARGET_OS, "pe", 2) == 0
1048 && g_switch_value != 0)
1051 as_bad (_("-G not supported in this configuration."));
1056 if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0)
1058 a = xmalloc (sizeof TARGET_CPU);
1059 strcpy (a, TARGET_CPU);
1060 a[(sizeof TARGET_CPU) - 3] = '\0';
1064 if (strncmp (cpu, "mips16", sizeof "mips16" - 1) == 0)
1066 target_cpu_had_mips16 = 1;
1067 cpu += sizeof "mips16" - 1;
1070 if (mips_opts.mips16 < 0)
1071 mips_opts.mips16 = target_cpu_had_mips16;
1073 /* Backward compatibility for historic -mcpu= option. Check for
1074 incompatible options, warn if -mcpu is used. */
1075 if (mips_cpu != CPU_UNKNOWN
1076 && mips_arch != CPU_UNKNOWN
1077 && mips_cpu != mips_arch)
1079 as_fatal (_("The -mcpu option can't be used together with -march. "
1080 "Use -mtune instead of -mcpu."));
1083 if (mips_cpu != CPU_UNKNOWN
1084 && mips_tune != CPU_UNKNOWN
1085 && mips_cpu != mips_tune)
1087 as_fatal (_("The -mcpu option can't be used together with -mtune. "
1088 "Use -march instead of -mcpu."));
1092 /* For backward compatibility, let -mipsN set various defaults. */
1093 /* This code should go away, to be replaced with something rather more
1094 draconian. Until GCC 3.1 has been released for some reasonable
1095 amount of time, however, we need to support this. */
1096 if (mips_opts.isa != ISA_UNKNOWN)
1098 /* Translate -mipsN to the appropriate settings of file_mips_gp32
1099 and file_mips_fp32. Tag binaries as using the mipsN ISA. */
1100 if (file_mips_gp32 < 0)
1102 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
1107 if (file_mips_fp32 < 0)
1109 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
1115 ci = mips_cpu_info_from_isa (mips_opts.isa);
1116 assert (ci != NULL);
1117 /* -mipsN has higher priority than -mcpu but lower than -march. */
1118 if (mips_arch == CPU_UNKNOWN)
1119 mips_arch = ci->cpu;
1121 /* Default mips_abi. */
1122 if (mips_opts.abi == NO_ABI)
1124 if (mips_opts.isa == ISA_MIPS1 || mips_opts.isa == ISA_MIPS2)
1125 mips_opts.abi = O32_ABI;
1126 else if (mips_opts.isa == ISA_MIPS3 || mips_opts.isa == ISA_MIPS4)
1127 mips_opts.abi = O64_ABI;
1131 if (mips_arch == CPU_UNKNOWN && mips_cpu != CPU_UNKNOWN)
1133 ci = mips_cpu_info_from_cpu (mips_cpu);
1134 assert (ci != NULL);
1135 mips_arch = ci->cpu;
1136 as_warn (_("The -mcpu option is deprecated. Please use -march and "
1137 "-mtune instead."));
1140 /* Set tune from -mcpu, not from -mipsN. */
1141 if (mips_tune == CPU_UNKNOWN && mips_cpu != CPU_UNKNOWN)
1143 ci = mips_cpu_info_from_cpu (mips_cpu);
1144 assert (ci != NULL);
1145 mips_tune = ci->cpu;
1148 /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was
1149 specified on the command line, or some other value if one was.
1150 Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on
1151 the command line, or will be set otherwise if one was. */
1153 if (mips_arch != CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN)
1154 /* Handled above. */;
1156 if (mips_arch == CPU_UNKNOWN && mips_cpu != CPU_UNKNOWN)
1158 ci = mips_cpu_info_from_cpu (mips_cpu);
1159 assert (ci != NULL);
1160 mips_arch = ci->cpu;
1161 as_warn (_("The -mcpu option is deprecated. Please use -march and "
1162 "-mtune instead."));
1165 /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was
1166 specified on the command line, or some other value if one was.
1167 Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on
1168 the command line, or will be set otherwise if one was. */
1170 if (mips_arch != CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN)
1172 /* We have to check if the isa is the default isa of arch. Otherwise
1173 we'll get invalid object file headers. */
1174 ci = mips_cpu_info_from_cpu (mips_arch);
1175 assert (ci != NULL);
1176 if (mips_opts.isa != ci->isa)
1178 /* This really should be an error instead of a warning, but old
1179 compilers only have -mcpu which sets both arch and tune. For
1180 now, we discard arch and preserve tune. */
1181 as_warn (_("The -march option is incompatible to -mipsN and "
1182 "therefore ignored."));
1183 if (mips_tune == CPU_UNKNOWN)
1184 mips_tune = mips_arch;
1185 ci = mips_cpu_info_from_isa (mips_opts.isa);
1186 assert (ci != NULL);
1187 mips_arch = ci->cpu;
1191 else if (mips_arch != CPU_UNKNOWN && mips_opts.isa == ISA_UNKNOWN)
1193 /* We have ARCH, we need ISA. */
1194 ci = mips_cpu_info_from_cpu (mips_arch);
1195 assert (ci != NULL);
1196 mips_opts.isa = ci->isa;
1198 else if (mips_arch == CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN)
1200 /* We have ISA, we need default ARCH. */
1201 ci = mips_cpu_info_from_isa (mips_opts.isa);
1202 assert (ci != NULL);
1203 mips_arch = ci->cpu;
1207 /* We need to set both ISA and ARCH from target cpu. */
1208 ci = mips_cpu_info_from_name (cpu);
1210 ci = mips_cpu_info_from_cpu (CPU_R3000);
1211 assert (ci != NULL);
1212 mips_opts.isa = ci->isa;
1213 mips_arch = ci->cpu;
1216 if (mips_tune == CPU_UNKNOWN)
1217 mips_tune = mips_arch;
1219 ci = mips_cpu_info_from_cpu (mips_arch);
1220 assert (ci != NULL);
1221 mips_isa_from_cpu = ci->isa;
1223 /* End of TARGET_CPU processing, get rid of malloced memory
1232 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
1233 as_bad (_("trap exception not supported at ISA 1"));
1235 /* Set the EABI kind based on the ISA before the user gets
1236 to change the ISA with directives. This isn't really
1237 the best, but then neither is basing the abi on the isa. */
1238 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
1239 && mips_opts.abi == EABI_ABI)
1242 /* If they asked for mips1 or mips2 and a cpu that is
1243 mips3 or greater, then mark the object file 32BITMODE. */
1244 if (mips_isa_from_cpu != ISA_UNKNOWN
1245 && ! ISA_HAS_64BIT_REGS (mips_opts.isa)
1246 && ISA_HAS_64BIT_REGS (mips_isa_from_cpu))
1249 /* If the selected architecture includes support for ASEs, enable
1250 generation of code for them. */
1251 if (mips_opts.ase_mips3d == -1 && CPU_HAS_MIPS3D (mips_arch))
1252 mips_opts.ase_mips3d = 1;
1253 if (mips_opts.ase_mdmx == -1 && CPU_HAS_MDMX (mips_arch))
1254 mips_opts.ase_mdmx = 1;
1256 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_arch))
1257 as_warn (_("Could not set architecture and machine"));
1259 if (file_mips_gp32 < 0)
1261 if (file_mips_fp32 < 0)
1264 file_mips_isa = mips_opts.isa;
1265 file_mips_abi = mips_opts.abi;
1266 file_ase_mips3d = mips_opts.ase_mips3d;
1267 file_ase_mdmx = mips_opts.ase_mdmx;
1268 mips_opts.gp32 = file_mips_gp32;
1269 mips_opts.fp32 = file_mips_fp32;
1274 op_hash = hash_new ();
1276 for (i = 0; i < NUMOPCODES;)
1278 const char *name = mips_opcodes[i].name;
1280 retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]);
1283 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1284 mips_opcodes[i].name, retval);
1285 /* Probably a memory allocation problem? Give up now. */
1286 as_fatal (_("Broken assembler. No assembly attempted."));
1290 if (mips_opcodes[i].pinfo != INSN_MACRO)
1292 if (!validate_mips_insn (&mips_opcodes[i]))
1297 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1300 mips16_op_hash = hash_new ();
1303 while (i < bfd_mips16_num_opcodes)
1305 const char *name = mips16_opcodes[i].name;
1307 retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]);
1309 as_fatal (_("internal: can't hash `%s': %s"),
1310 mips16_opcodes[i].name, retval);
1313 if (mips16_opcodes[i].pinfo != INSN_MACRO
1314 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1315 != mips16_opcodes[i].match))
1317 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1318 mips16_opcodes[i].name, mips16_opcodes[i].args);
1323 while (i < bfd_mips16_num_opcodes
1324 && strcmp (mips16_opcodes[i].name, name) == 0);
1328 as_fatal (_("Broken assembler. No assembly attempted."));
1330 /* We add all the general register names to the symbol table. This
1331 helps us detect invalid uses of them. */
1332 for (i = 0; i < 32; i++)
1336 sprintf (buf, "$%d", i);
1337 symbol_table_insert (symbol_new (buf, reg_section, i,
1338 &zero_address_frag));
1340 symbol_table_insert (symbol_new ("$ra", reg_section, RA,
1341 &zero_address_frag));
1342 symbol_table_insert (symbol_new ("$fp", reg_section, FP,
1343 &zero_address_frag));
1344 symbol_table_insert (symbol_new ("$sp", reg_section, SP,
1345 &zero_address_frag));
1346 symbol_table_insert (symbol_new ("$gp", reg_section, GP,
1347 &zero_address_frag));
1348 symbol_table_insert (symbol_new ("$at", reg_section, AT,
1349 &zero_address_frag));
1350 symbol_table_insert (symbol_new ("$kt0", reg_section, KT0,
1351 &zero_address_frag));
1352 symbol_table_insert (symbol_new ("$kt1", reg_section, KT1,
1353 &zero_address_frag));
1354 symbol_table_insert (symbol_new ("$pc", reg_section, -1,
1355 &zero_address_frag));
1357 mips_no_prev_insn (false);
1360 mips_cprmask[0] = 0;
1361 mips_cprmask[1] = 0;
1362 mips_cprmask[2] = 0;
1363 mips_cprmask[3] = 0;
1365 /* set the default alignment for the text section (2**2) */
1366 record_alignment (text_section, 2);
1368 if (USE_GLOBAL_POINTER_OPT)
1369 bfd_set_gp_size (stdoutput, g_switch_value);
1371 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1373 /* On a native system, sections must be aligned to 16 byte
1374 boundaries. When configured for an embedded ELF target, we
1376 if (strcmp (TARGET_OS, "elf") != 0)
1378 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
1379 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
1380 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
1383 /* Create a .reginfo section for register masks and a .mdebug
1384 section for debugging information. */
1392 subseg = now_subseg;
1394 /* The ABI says this section should be loaded so that the
1395 running program can access it. However, we don't load it
1396 if we are configured for an embedded target */
1397 flags = SEC_READONLY | SEC_DATA;
1398 if (strcmp (TARGET_OS, "elf") != 0)
1399 flags |= SEC_ALLOC | SEC_LOAD;
1401 if (file_mips_abi != N64_ABI)
1403 sec = subseg_new (".reginfo", (subsegT) 0);
1405 bfd_set_section_flags (stdoutput, sec, flags);
1406 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
1409 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
1414 /* The 64-bit ABI uses a .MIPS.options section rather than
1415 .reginfo section. */
1416 sec = subseg_new (".MIPS.options", (subsegT) 0);
1417 bfd_set_section_flags (stdoutput, sec, flags);
1418 bfd_set_section_alignment (stdoutput, sec, 3);
1421 /* Set up the option header. */
1423 Elf_Internal_Options opthdr;
1426 opthdr.kind = ODK_REGINFO;
1427 opthdr.size = (sizeof (Elf_External_Options)
1428 + sizeof (Elf64_External_RegInfo));
1431 f = frag_more (sizeof (Elf_External_Options));
1432 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
1433 (Elf_External_Options *) f);
1435 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
1440 if (ECOFF_DEBUGGING)
1442 sec = subseg_new (".mdebug", (subsegT) 0);
1443 (void) bfd_set_section_flags (stdoutput, sec,
1444 SEC_HAS_CONTENTS | SEC_READONLY);
1445 (void) bfd_set_section_alignment (stdoutput, sec, 2);
1448 #ifdef MIPS_STABS_ELF
1449 pdr_seg = subseg_new (".pdr", (subsegT) 0);
1450 (void) bfd_set_section_flags (stdoutput, pdr_seg,
1451 SEC_READONLY | SEC_RELOC | SEC_DEBUGGING);
1452 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
1455 subseg_set (seg, subseg);
1459 if (! ECOFF_DEBUGGING)
1466 if (! ECOFF_DEBUGGING)
1474 struct mips_cl_insn insn;
1475 bfd_reloc_code_real_type unused_reloc[3]
1476 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1478 imm_expr.X_op = O_absent;
1479 imm_unmatched_hi = false;
1480 offset_expr.X_op = O_absent;
1481 imm_reloc[0] = BFD_RELOC_UNUSED;
1482 imm_reloc[1] = BFD_RELOC_UNUSED;
1483 imm_reloc[2] = BFD_RELOC_UNUSED;
1484 offset_reloc[0] = BFD_RELOC_UNUSED;
1485 offset_reloc[1] = BFD_RELOC_UNUSED;
1486 offset_reloc[2] = BFD_RELOC_UNUSED;
1488 if (mips_opts.mips16)
1489 mips16_ip (str, &insn);
1492 mips_ip (str, &insn);
1493 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1494 str, insn.insn_opcode));
1499 as_bad ("%s `%s'", insn_error, str);
1503 if (insn.insn_mo->pinfo == INSN_MACRO)
1505 if (mips_opts.mips16)
1506 mips16_macro (&insn);
1512 if (imm_expr.X_op != O_absent)
1513 append_insn (NULL, &insn, &imm_expr, imm_reloc, imm_unmatched_hi);
1514 else if (offset_expr.X_op != O_absent)
1515 append_insn (NULL, &insn, &offset_expr, offset_reloc, false);
1517 append_insn (NULL, &insn, NULL, unused_reloc, false);
1521 /* See whether instruction IP reads register REG. CLASS is the type
1525 insn_uses_reg (ip, reg, class)
1526 struct mips_cl_insn *ip;
1528 enum mips_regclass class;
1530 if (class == MIPS16_REG)
1532 assert (mips_opts.mips16);
1533 reg = mips16_to_32_reg_map[reg];
1534 class = MIPS_GR_REG;
1537 /* Don't report on general register 0, since it never changes. */
1538 if (class == MIPS_GR_REG && reg == 0)
1541 if (class == MIPS_FP_REG)
1543 assert (! mips_opts.mips16);
1544 /* If we are called with either $f0 or $f1, we must check $f0.
1545 This is not optimal, because it will introduce an unnecessary
1546 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1547 need to distinguish reading both $f0 and $f1 or just one of
1548 them. Note that we don't have to check the other way,
1549 because there is no instruction that sets both $f0 and $f1
1550 and requires a delay. */
1551 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
1552 && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1)
1553 == (reg &~ (unsigned) 1)))
1555 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
1556 && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1)
1557 == (reg &~ (unsigned) 1)))
1560 else if (! mips_opts.mips16)
1562 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
1563 && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg)
1565 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
1566 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg)
1571 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
1572 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX)
1573 & MIPS16OP_MASK_RX)]
1576 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
1577 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY)
1578 & MIPS16OP_MASK_RY)]
1581 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
1582 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
1583 & MIPS16OP_MASK_MOVE32Z)]
1586 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
1588 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
1590 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
1592 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
1593 && ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
1594 & MIPS16OP_MASK_REGR32) == reg)
1601 /* This function returns true if modifying a register requires a
1605 reg_needs_delay (reg)
1608 unsigned long prev_pinfo;
1610 prev_pinfo = prev_insn.insn_mo->pinfo;
1611 if (! mips_opts.noreorder
1612 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1613 && ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1614 || (! gpr_interlocks
1615 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
1617 /* A load from a coprocessor or from memory. All load
1618 delays delay the use of general register rt for one
1619 instruction on the r3000. The r6000 and r4000 use
1621 /* Itbl support may require additional care here. */
1622 know (prev_pinfo & INSN_WRITE_GPR_T);
1623 if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT))
1630 /* Mark instruction labels in mips16 mode. This permits the linker to
1631 handle them specially, such as generating jalx instructions when
1632 needed. We also make them odd for the duration of the assembly, in
1633 order to generate the right sort of code. We will make them even
1634 in the adjust_symtab routine, while leaving them marked. This is
1635 convenient for the debugger and the disassembler. The linker knows
1636 to make them odd again. */
1639 mips16_mark_labels ()
1641 if (mips_opts.mips16)
1643 struct insn_label_list *l;
1646 for (l = insn_labels; l != NULL; l = l->next)
1649 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1650 S_SET_OTHER (l->label, STO_MIPS16);
1652 val = S_GET_VALUE (l->label);
1654 S_SET_VALUE (l->label, val + 1);
1659 /* Output an instruction. PLACE is where to put the instruction; if
1660 it is NULL, this uses frag_more to get room. IP is the instruction
1661 information. ADDRESS_EXPR is an operand of the instruction to be
1662 used with RELOC_TYPE. */
1665 append_insn (place, ip, address_expr, reloc_type, unmatched_hi)
1667 struct mips_cl_insn *ip;
1668 expressionS *address_expr;
1669 bfd_reloc_code_real_type *reloc_type;
1670 boolean unmatched_hi;
1672 register unsigned long prev_pinfo, pinfo;
1677 /* Mark instruction labels in mips16 mode. */
1678 mips16_mark_labels ();
1680 prev_pinfo = prev_insn.insn_mo->pinfo;
1681 pinfo = ip->insn_mo->pinfo;
1683 if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL))
1687 /* If the previous insn required any delay slots, see if we need
1688 to insert a NOP or two. There are eight kinds of possible
1689 hazards, of which an instruction can have at most one type.
1690 (1) a load from memory delay
1691 (2) a load from a coprocessor delay
1692 (3) an unconditional branch delay
1693 (4) a conditional branch delay
1694 (5) a move to coprocessor register delay
1695 (6) a load coprocessor register from memory delay
1696 (7) a coprocessor condition code delay
1697 (8) a HI/LO special register delay
1699 There are a lot of optimizations we could do that we don't.
1700 In particular, we do not, in general, reorder instructions.
1701 If you use gcc with optimization, it will reorder
1702 instructions and generally do much more optimization then we
1703 do here; repeating all that work in the assembler would only
1704 benefit hand written assembly code, and does not seem worth
1707 /* This is how a NOP is emitted. */
1708 #define emit_nop() \
1710 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1711 : md_number_to_chars (frag_more (4), 0, 4))
1713 /* The previous insn might require a delay slot, depending upon
1714 the contents of the current insn. */
1715 if (! mips_opts.mips16
1716 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1717 && (((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1718 && ! cop_interlocks)
1719 || (! gpr_interlocks
1720 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
1722 /* A load from a coprocessor or from memory. All load
1723 delays delay the use of general register rt for one
1724 instruction on the r3000. The r6000 and r4000 use
1726 /* Itbl support may require additional care here. */
1727 know (prev_pinfo & INSN_WRITE_GPR_T);
1728 if (mips_optimize == 0
1729 || insn_uses_reg (ip,
1730 ((prev_insn.insn_opcode >> OP_SH_RT)
1735 else if (! mips_opts.mips16
1736 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1737 && (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
1738 && ! cop_interlocks)
1739 || (mips_opts.isa == ISA_MIPS1
1740 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))))
1742 /* A generic coprocessor delay. The previous instruction
1743 modified a coprocessor general or control register. If
1744 it modified a control register, we need to avoid any
1745 coprocessor instruction (this is probably not always
1746 required, but it sometimes is). If it modified a general
1747 register, we avoid using that register.
1749 On the r6000 and r4000 loading a coprocessor register
1750 from memory is interlocked, and does not require a delay.
1752 This case is not handled very well. There is no special
1753 knowledge of CP0 handling, and the coprocessors other
1754 than the floating point unit are not distinguished at
1756 /* Itbl support may require additional care here. FIXME!
1757 Need to modify this to include knowledge about
1758 user specified delays! */
1759 if (prev_pinfo & INSN_WRITE_FPR_T)
1761 if (mips_optimize == 0
1762 || insn_uses_reg (ip,
1763 ((prev_insn.insn_opcode >> OP_SH_FT)
1768 else if (prev_pinfo & INSN_WRITE_FPR_S)
1770 if (mips_optimize == 0
1771 || insn_uses_reg (ip,
1772 ((prev_insn.insn_opcode >> OP_SH_FS)
1779 /* We don't know exactly what the previous instruction
1780 does. If the current instruction uses a coprocessor
1781 register, we must insert a NOP. If previous
1782 instruction may set the condition codes, and the
1783 current instruction uses them, we must insert two
1785 /* Itbl support may require additional care here. */
1786 if (mips_optimize == 0
1787 || ((prev_pinfo & INSN_WRITE_COND_CODE)
1788 && (pinfo & INSN_READ_COND_CODE)))
1790 else if (pinfo & INSN_COP)
1794 else if (! mips_opts.mips16
1795 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1796 && (prev_pinfo & INSN_WRITE_COND_CODE)
1797 && ! cop_interlocks)
1799 /* The previous instruction sets the coprocessor condition
1800 codes, but does not require a general coprocessor delay
1801 (this means it is a floating point comparison
1802 instruction). If this instruction uses the condition
1803 codes, we need to insert a single NOP. */
1804 /* Itbl support may require additional care here. */
1805 if (mips_optimize == 0
1806 || (pinfo & INSN_READ_COND_CODE))
1810 /* If we're fixing up mfhi/mflo for the r7000 and the
1811 previous insn was an mfhi/mflo and the current insn
1812 reads the register that the mfhi/mflo wrote to, then
1815 else if (mips_7000_hilo_fix
1816 && MF_HILO_INSN (prev_pinfo)
1817 && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD)
1824 /* If we're fixing up mfhi/mflo for the r7000 and the
1825 2nd previous insn was an mfhi/mflo and the current insn
1826 reads the register that the mfhi/mflo wrote to, then
1829 else if (mips_7000_hilo_fix
1830 && MF_HILO_INSN (prev_prev_insn.insn_opcode)
1831 && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD)
1839 else if (prev_pinfo & INSN_READ_LO)
1841 /* The previous instruction reads the LO register; if the
1842 current instruction writes to the LO register, we must
1843 insert two NOPS. Some newer processors have interlocks.
1844 Also the tx39's multiply instructions can be exectuted
1845 immediatly after a read from HI/LO (without the delay),
1846 though the tx39's divide insns still do require the
1848 if (! (hilo_interlocks
1849 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
1850 && (mips_optimize == 0
1851 || (pinfo & INSN_WRITE_LO)))
1853 /* Most mips16 branch insns don't have a delay slot.
1854 If a read from LO is immediately followed by a branch
1855 to a write to LO we have a read followed by a write
1856 less than 2 insns away. We assume the target of
1857 a branch might be a write to LO, and insert a nop
1858 between a read and an immediately following branch. */
1859 else if (mips_opts.mips16
1860 && (mips_optimize == 0
1861 || (pinfo & MIPS16_INSN_BRANCH)))
1864 else if (prev_insn.insn_mo->pinfo & INSN_READ_HI)
1866 /* The previous instruction reads the HI register; if the
1867 current instruction writes to the HI register, we must
1868 insert a NOP. Some newer processors have interlocks.
1869 Also the note tx39's multiply above. */
1870 if (! (hilo_interlocks
1871 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
1872 && (mips_optimize == 0
1873 || (pinfo & INSN_WRITE_HI)))
1875 /* Most mips16 branch insns don't have a delay slot.
1876 If a read from HI is immediately followed by a branch
1877 to a write to HI we have a read followed by a write
1878 less than 2 insns away. We assume the target of
1879 a branch might be a write to HI, and insert a nop
1880 between a read and an immediately following branch. */
1881 else if (mips_opts.mips16
1882 && (mips_optimize == 0
1883 || (pinfo & MIPS16_INSN_BRANCH)))
1887 /* If the previous instruction was in a noreorder section, then
1888 we don't want to insert the nop after all. */
1889 /* Itbl support may require additional care here. */
1890 if (prev_insn_unreordered)
1893 /* There are two cases which require two intervening
1894 instructions: 1) setting the condition codes using a move to
1895 coprocessor instruction which requires a general coprocessor
1896 delay and then reading the condition codes 2) reading the HI
1897 or LO register and then writing to it (except on processors
1898 which have interlocks). If we are not already emitting a NOP
1899 instruction, we must check for these cases compared to the
1900 instruction previous to the previous instruction. */
1901 if ((! mips_opts.mips16
1902 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1903 && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
1904 && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
1905 && (pinfo & INSN_READ_COND_CODE)
1906 && ! cop_interlocks)
1907 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
1908 && (pinfo & INSN_WRITE_LO)
1909 && ! (hilo_interlocks
1910 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))))
1911 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
1912 && (pinfo & INSN_WRITE_HI)
1913 && ! (hilo_interlocks
1914 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))))
1919 if (prev_prev_insn_unreordered)
1922 if (prev_prev_nop && nops == 0)
1925 /* If we are being given a nop instruction, don't bother with
1926 one of the nops we would otherwise output. This will only
1927 happen when a nop instruction is used with mips_optimize set
1930 && ! mips_opts.noreorder
1931 && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0))
1934 /* Now emit the right number of NOP instructions. */
1935 if (nops > 0 && ! mips_opts.noreorder)
1938 unsigned long old_frag_offset;
1940 struct insn_label_list *l;
1942 old_frag = frag_now;
1943 old_frag_offset = frag_now_fix ();
1945 for (i = 0; i < nops; i++)
1950 listing_prev_line ();
1951 /* We may be at the start of a variant frag. In case we
1952 are, make sure there is enough space for the frag
1953 after the frags created by listing_prev_line. The
1954 argument to frag_grow here must be at least as large
1955 as the argument to all other calls to frag_grow in
1956 this file. We don't have to worry about being in the
1957 middle of a variant frag, because the variants insert
1958 all needed nop instructions themselves. */
1962 for (l = insn_labels; l != NULL; l = l->next)
1966 assert (S_GET_SEGMENT (l->label) == now_seg);
1967 symbol_set_frag (l->label, frag_now);
1968 val = (valueT) frag_now_fix ();
1969 /* mips16 text labels are stored as odd. */
1970 if (mips_opts.mips16)
1972 S_SET_VALUE (l->label, val);
1975 #ifndef NO_ECOFF_DEBUGGING
1976 if (ECOFF_DEBUGGING)
1977 ecoff_fix_loc (old_frag, old_frag_offset);
1980 else if (prev_nop_frag != NULL)
1982 /* We have a frag holding nops we may be able to remove. If
1983 we don't need any nops, we can decrease the size of
1984 prev_nop_frag by the size of one instruction. If we do
1985 need some nops, we count them in prev_nops_required. */
1986 if (prev_nop_frag_since == 0)
1990 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1991 --prev_nop_frag_holds;
1994 prev_nop_frag_required += nops;
1998 if (prev_prev_nop == 0)
2000 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
2001 --prev_nop_frag_holds;
2004 ++prev_nop_frag_required;
2007 if (prev_nop_frag_holds <= prev_nop_frag_required)
2008 prev_nop_frag = NULL;
2010 ++prev_nop_frag_since;
2012 /* Sanity check: by the time we reach the second instruction
2013 after prev_nop_frag, we should have used up all the nops
2014 one way or another. */
2015 assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL);
2019 if (*reloc_type > BFD_RELOC_UNUSED)
2021 /* We need to set up a variant frag. */
2022 assert (mips_opts.mips16 && address_expr != NULL);
2023 f = frag_var (rs_machine_dependent, 4, 0,
2024 RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED,
2025 mips16_small, mips16_ext,
2027 & INSN_UNCOND_BRANCH_DELAY),
2028 (*prev_insn_reloc_type
2029 == BFD_RELOC_MIPS16_JMP)),
2030 make_expr_symbol (address_expr), 0, NULL);
2032 else if (place != NULL)
2034 else if (mips_opts.mips16
2036 && *reloc_type != BFD_RELOC_MIPS16_JMP)
2038 /* Make sure there is enough room to swap this instruction with
2039 a following jump instruction. */
2045 if (mips_opts.mips16
2046 && mips_opts.noreorder
2047 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2048 as_warn (_("extended instruction in delay slot"));
2053 fixp[0] = fixp[1] = fixp[2] = NULL;
2054 if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED)
2056 if (address_expr->X_op == O_constant)
2060 switch (*reloc_type)
2063 ip->insn_opcode |= address_expr->X_add_number;
2066 case BFD_RELOC_MIPS_HIGHEST:
2067 tmp = (address_expr->X_add_number + 0x800080008000) >> 16;
2069 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2072 case BFD_RELOC_MIPS_HIGHER:
2073 tmp = (address_expr->X_add_number + 0x80008000) >> 16;
2074 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2077 case BFD_RELOC_HI16_S:
2078 ip->insn_opcode |= ((address_expr->X_add_number + 0x8000)
2082 case BFD_RELOC_HI16:
2083 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
2086 case BFD_RELOC_LO16:
2087 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
2090 case BFD_RELOC_MIPS_JMP:
2091 if ((address_expr->X_add_number & 3) != 0)
2092 as_bad (_("jump to misaligned address (0x%lx)"),
2093 (unsigned long) address_expr->X_add_number);
2094 if (address_expr->X_add_number & ~0xfffffff
2095 || address_expr->X_add_number > 0x7fffffc)
2096 as_bad (_("jump address range overflow (0x%lx)"),
2097 (unsigned long) address_expr->X_add_number);
2098 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
2101 case BFD_RELOC_MIPS16_JMP:
2102 if ((address_expr->X_add_number & 3) != 0)
2103 as_bad (_("jump to misaligned address (0x%lx)"),
2104 (unsigned long) address_expr->X_add_number);
2105 if (address_expr->X_add_number & ~0xfffffff
2106 || address_expr->X_add_number > 0x7fffffc)
2107 as_bad (_("jump address range overflow (0x%lx)"),
2108 (unsigned long) address_expr->X_add_number);
2110 (((address_expr->X_add_number & 0x7c0000) << 3)
2111 | ((address_expr->X_add_number & 0xf800000) >> 7)
2112 | ((address_expr->X_add_number & 0x3fffc) >> 2));
2115 case BFD_RELOC_16_PCREL:
2116 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
2119 case BFD_RELOC_16_PCREL_S2:
2129 /* Don't generate a reloc if we are writing into a variant frag. */
2132 fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal, 4,
2134 (*reloc_type == BFD_RELOC_16_PCREL
2135 || *reloc_type == BFD_RELOC_16_PCREL_S2),
2138 /* These relocations can have an addend that won't fit in
2139 4 octets for 64bit assembly. */
2140 if (HAVE_64BIT_GPRS &&
2141 (*reloc_type == BFD_RELOC_16
2142 || *reloc_type == BFD_RELOC_32
2143 || *reloc_type == BFD_RELOC_MIPS_JMP
2144 || *reloc_type == BFD_RELOC_HI16_S
2145 || *reloc_type == BFD_RELOC_LO16
2146 || *reloc_type == BFD_RELOC_GPREL16
2147 || *reloc_type == BFD_RELOC_MIPS_LITERAL
2148 || *reloc_type == BFD_RELOC_GPREL32
2149 || *reloc_type == BFD_RELOC_64
2150 || *reloc_type == BFD_RELOC_CTOR
2151 || *reloc_type == BFD_RELOC_MIPS_SUB
2152 || *reloc_type == BFD_RELOC_MIPS_HIGHEST
2153 || *reloc_type == BFD_RELOC_MIPS_HIGHER
2154 || *reloc_type == BFD_RELOC_MIPS_SCN_DISP
2155 || *reloc_type == BFD_RELOC_MIPS_REL16
2156 || *reloc_type == BFD_RELOC_MIPS_RELGOT))
2157 fixp[0]->fx_no_overflow = 1;
2161 struct mips_hi_fixup *hi_fixup;
2163 assert (*reloc_type == BFD_RELOC_HI16_S);
2164 hi_fixup = ((struct mips_hi_fixup *)
2165 xmalloc (sizeof (struct mips_hi_fixup)));
2166 hi_fixup->fixp = fixp[0];
2167 hi_fixup->seg = now_seg;
2168 hi_fixup->next = mips_hi_fixup_list;
2169 mips_hi_fixup_list = hi_fixup;
2172 if (reloc_type[1] != BFD_RELOC_UNUSED)
2174 /* FIXME: This symbol can be one of
2175 RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */
2176 address_expr->X_op = O_absent;
2177 address_expr->X_add_symbol = 0;
2178 address_expr->X_add_number = 0;
2180 fixp[1] = fix_new_exp (frag_now, f - frag_now->fr_literal,
2181 4, address_expr, false,
2184 /* These relocations can have an addend that won't fit in
2185 4 octets for 64bit assembly. */
2186 if (HAVE_64BIT_GPRS &&
2187 (*reloc_type == BFD_RELOC_16
2188 || *reloc_type == BFD_RELOC_32
2189 || *reloc_type == BFD_RELOC_MIPS_JMP
2190 || *reloc_type == BFD_RELOC_HI16_S
2191 || *reloc_type == BFD_RELOC_LO16
2192 || *reloc_type == BFD_RELOC_GPREL16
2193 || *reloc_type == BFD_RELOC_MIPS_LITERAL
2194 || *reloc_type == BFD_RELOC_GPREL32
2195 || *reloc_type == BFD_RELOC_64
2196 || *reloc_type == BFD_RELOC_CTOR
2197 || *reloc_type == BFD_RELOC_MIPS_SUB
2198 || *reloc_type == BFD_RELOC_MIPS_HIGHEST
2199 || *reloc_type == BFD_RELOC_MIPS_HIGHER
2200 || *reloc_type == BFD_RELOC_MIPS_SCN_DISP
2201 || *reloc_type == BFD_RELOC_MIPS_REL16
2202 || *reloc_type == BFD_RELOC_MIPS_RELGOT))
2203 fixp[1]->fx_no_overflow = 1;
2205 if (reloc_type[2] != BFD_RELOC_UNUSED)
2207 address_expr->X_op = O_absent;
2208 address_expr->X_add_symbol = 0;
2209 address_expr->X_add_number = 0;
2211 fixp[2] = fix_new_exp (frag_now,
2212 f - frag_now->fr_literal, 4,
2213 address_expr, false,
2216 /* These relocations can have an addend that won't fit in
2217 4 octets for 64bit assembly. */
2218 if (HAVE_64BIT_GPRS &&
2219 (*reloc_type == BFD_RELOC_16
2220 || *reloc_type == BFD_RELOC_32
2221 || *reloc_type == BFD_RELOC_MIPS_JMP
2222 || *reloc_type == BFD_RELOC_HI16_S
2223 || *reloc_type == BFD_RELOC_LO16
2224 || *reloc_type == BFD_RELOC_GPREL16
2225 || *reloc_type == BFD_RELOC_MIPS_LITERAL
2226 || *reloc_type == BFD_RELOC_GPREL32
2227 || *reloc_type == BFD_RELOC_64
2228 || *reloc_type == BFD_RELOC_CTOR
2229 || *reloc_type == BFD_RELOC_MIPS_SUB
2230 || *reloc_type == BFD_RELOC_MIPS_HIGHEST
2231 || *reloc_type == BFD_RELOC_MIPS_HIGHER
2232 || *reloc_type == BFD_RELOC_MIPS_SCN_DISP
2233 || *reloc_type == BFD_RELOC_MIPS_REL16
2234 || *reloc_type == BFD_RELOC_MIPS_RELGOT))
2235 fixp[2]->fx_no_overflow = 1;
2242 if (! mips_opts.mips16)
2243 md_number_to_chars (f, ip->insn_opcode, 4);
2244 else if (*reloc_type == BFD_RELOC_MIPS16_JMP)
2246 md_number_to_chars (f, ip->insn_opcode >> 16, 2);
2247 md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2);
2253 md_number_to_chars (f, 0xf000 | ip->extend, 2);
2256 md_number_to_chars (f, ip->insn_opcode, 2);
2259 /* Update the register mask information. */
2260 if (! mips_opts.mips16)
2262 if (pinfo & INSN_WRITE_GPR_D)
2263 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD);
2264 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
2265 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT);
2266 if (pinfo & INSN_READ_GPR_S)
2267 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS);
2268 if (pinfo & INSN_WRITE_GPR_31)
2269 mips_gprmask |= 1 << RA;
2270 if (pinfo & INSN_WRITE_FPR_D)
2271 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD);
2272 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
2273 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS);
2274 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
2275 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT);
2276 if ((pinfo & INSN_READ_FPR_R) != 0)
2277 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR);
2278 if (pinfo & INSN_COP)
2280 /* We don't keep enough information to sort these cases out.
2281 The itbl support does keep this information however, although
2282 we currently don't support itbl fprmats as part of the cop
2283 instruction. May want to add this support in the future. */
2285 /* Never set the bit for $0, which is always zero. */
2286 mips_gprmask &= ~1 << 0;
2290 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
2291 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX)
2292 & MIPS16OP_MASK_RX);
2293 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
2294 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY)
2295 & MIPS16OP_MASK_RY);
2296 if (pinfo & MIPS16_INSN_WRITE_Z)
2297 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ)
2298 & MIPS16OP_MASK_RZ);
2299 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
2300 mips_gprmask |= 1 << TREG;
2301 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
2302 mips_gprmask |= 1 << SP;
2303 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
2304 mips_gprmask |= 1 << RA;
2305 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2306 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2307 if (pinfo & MIPS16_INSN_READ_Z)
2308 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
2309 & MIPS16OP_MASK_MOVE32Z);
2310 if (pinfo & MIPS16_INSN_READ_GPR_X)
2311 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
2312 & MIPS16OP_MASK_REGR32);
2315 if (place == NULL && ! mips_opts.noreorder)
2317 /* Filling the branch delay slot is more complex. We try to
2318 switch the branch with the previous instruction, which we can
2319 do if the previous instruction does not set up a condition
2320 that the branch tests and if the branch is not itself the
2321 target of any branch. */
2322 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
2323 || (pinfo & INSN_COND_BRANCH_DELAY))
2325 if (mips_optimize < 2
2326 /* If we have seen .set volatile or .set nomove, don't
2328 || mips_opts.nomove != 0
2329 /* If we had to emit any NOP instructions, then we
2330 already know we can not swap. */
2332 /* If we don't even know the previous insn, we can not
2334 || ! prev_insn_valid
2335 /* If the previous insn is already in a branch delay
2336 slot, then we can not swap. */
2337 || prev_insn_is_delay_slot
2338 /* If the previous previous insn was in a .set
2339 noreorder, we can't swap. Actually, the MIPS
2340 assembler will swap in this situation. However, gcc
2341 configured -with-gnu-as will generate code like
2347 in which we can not swap the bne and INSN. If gcc is
2348 not configured -with-gnu-as, it does not output the
2349 .set pseudo-ops. We don't have to check
2350 prev_insn_unreordered, because prev_insn_valid will
2351 be 0 in that case. We don't want to use
2352 prev_prev_insn_valid, because we do want to be able
2353 to swap at the start of a function. */
2354 || prev_prev_insn_unreordered
2355 /* If the branch is itself the target of a branch, we
2356 can not swap. We cheat on this; all we check for is
2357 whether there is a label on this instruction. If
2358 there are any branches to anything other than a
2359 label, users must use .set noreorder. */
2360 || insn_labels != NULL
2361 /* If the previous instruction is in a variant frag, we
2362 can not do the swap. This does not apply to the
2363 mips16, which uses variant frags for different
2365 || (! mips_opts.mips16
2366 && prev_insn_frag->fr_type == rs_machine_dependent)
2367 /* If the branch reads the condition codes, we don't
2368 even try to swap, because in the sequence
2373 we can not swap, and I don't feel like handling that
2375 || (! mips_opts.mips16
2376 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2377 && (pinfo & INSN_READ_COND_CODE))
2378 /* We can not swap with an instruction that requires a
2379 delay slot, becase the target of the branch might
2380 interfere with that instruction. */
2381 || (! mips_opts.mips16
2382 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2384 /* Itbl support may require additional care here. */
2385 & (INSN_LOAD_COPROC_DELAY
2386 | INSN_COPROC_MOVE_DELAY
2387 | INSN_WRITE_COND_CODE)))
2388 || (! (hilo_interlocks
2389 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
2393 || (! mips_opts.mips16
2395 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))
2396 || (! mips_opts.mips16
2397 && mips_opts.isa == ISA_MIPS1
2398 /* Itbl support may require additional care here. */
2399 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))
2400 /* We can not swap with a branch instruction. */
2402 & (INSN_UNCOND_BRANCH_DELAY
2403 | INSN_COND_BRANCH_DELAY
2404 | INSN_COND_BRANCH_LIKELY))
2405 /* We do not swap with a trap instruction, since it
2406 complicates trap handlers to have the trap
2407 instruction be in a delay slot. */
2408 || (prev_pinfo & INSN_TRAP)
2409 /* If the branch reads a register that the previous
2410 instruction sets, we can not swap. */
2411 || (! mips_opts.mips16
2412 && (prev_pinfo & INSN_WRITE_GPR_T)
2413 && insn_uses_reg (ip,
2414 ((prev_insn.insn_opcode >> OP_SH_RT)
2417 || (! mips_opts.mips16
2418 && (prev_pinfo & INSN_WRITE_GPR_D)
2419 && insn_uses_reg (ip,
2420 ((prev_insn.insn_opcode >> OP_SH_RD)
2423 || (mips_opts.mips16
2424 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
2425 && insn_uses_reg (ip,
2426 ((prev_insn.insn_opcode
2428 & MIPS16OP_MASK_RX),
2430 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
2431 && insn_uses_reg (ip,
2432 ((prev_insn.insn_opcode
2434 & MIPS16OP_MASK_RY),
2436 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
2437 && insn_uses_reg (ip,
2438 ((prev_insn.insn_opcode
2440 & MIPS16OP_MASK_RZ),
2442 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
2443 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
2444 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
2445 && insn_uses_reg (ip, RA, MIPS_GR_REG))
2446 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2447 && insn_uses_reg (ip,
2448 MIPS16OP_EXTRACT_REG32R (prev_insn.
2451 /* If the branch writes a register that the previous
2452 instruction sets, we can not swap (we know that
2453 branches write only to RD or to $31). */
2454 || (! mips_opts.mips16
2455 && (prev_pinfo & INSN_WRITE_GPR_T)
2456 && (((pinfo & INSN_WRITE_GPR_D)
2457 && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)
2458 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2459 || ((pinfo & INSN_WRITE_GPR_31)
2460 && (((prev_insn.insn_opcode >> OP_SH_RT)
2463 || (! mips_opts.mips16
2464 && (prev_pinfo & INSN_WRITE_GPR_D)
2465 && (((pinfo & INSN_WRITE_GPR_D)
2466 && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD)
2467 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2468 || ((pinfo & INSN_WRITE_GPR_31)
2469 && (((prev_insn.insn_opcode >> OP_SH_RD)
2472 || (mips_opts.mips16
2473 && (pinfo & MIPS16_INSN_WRITE_31)
2474 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
2475 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2476 && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode)
2478 /* If the branch writes a register that the previous
2479 instruction reads, we can not swap (we know that
2480 branches only write to RD or to $31). */
2481 || (! mips_opts.mips16
2482 && (pinfo & INSN_WRITE_GPR_D)
2483 && insn_uses_reg (&prev_insn,
2484 ((ip->insn_opcode >> OP_SH_RD)
2487 || (! mips_opts.mips16
2488 && (pinfo & INSN_WRITE_GPR_31)
2489 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2490 || (mips_opts.mips16
2491 && (pinfo & MIPS16_INSN_WRITE_31)
2492 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2493 /* If we are generating embedded PIC code, the branch
2494 might be expanded into a sequence which uses $at, so
2495 we can't swap with an instruction which reads it. */
2496 || (mips_pic == EMBEDDED_PIC
2497 && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG))
2498 /* If the previous previous instruction has a load
2499 delay, and sets a register that the branch reads, we
2501 || (! mips_opts.mips16
2502 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2503 /* Itbl support may require additional care here. */
2504 && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
2505 || (! gpr_interlocks
2506 && (prev_prev_insn.insn_mo->pinfo
2507 & INSN_LOAD_MEMORY_DELAY)))
2508 && insn_uses_reg (ip,
2509 ((prev_prev_insn.insn_opcode >> OP_SH_RT)
2512 /* If one instruction sets a condition code and the
2513 other one uses a condition code, we can not swap. */
2514 || ((pinfo & INSN_READ_COND_CODE)
2515 && (prev_pinfo & INSN_WRITE_COND_CODE))
2516 || ((pinfo & INSN_WRITE_COND_CODE)
2517 && (prev_pinfo & INSN_READ_COND_CODE))
2518 /* If the previous instruction uses the PC, we can not
2520 || (mips_opts.mips16
2521 && (prev_pinfo & MIPS16_INSN_READ_PC))
2522 /* If the previous instruction was extended, we can not
2524 || (mips_opts.mips16 && prev_insn_extended)
2525 /* If the previous instruction had a fixup in mips16
2526 mode, we can not swap. This normally means that the
2527 previous instruction was a 4 byte branch anyhow. */
2528 || (mips_opts.mips16 && prev_insn_fixp[0])
2529 /* If the previous instruction is a sync, sync.l, or
2530 sync.p, we can not swap. */
2531 || (prev_pinfo & INSN_SYNC))
2533 /* We could do even better for unconditional branches to
2534 portions of this object file; we could pick up the
2535 instruction at the destination, put it in the delay
2536 slot, and bump the destination address. */
2538 /* Update the previous insn information. */
2539 prev_prev_insn = *ip;
2540 prev_insn.insn_mo = &dummy_opcode;
2544 /* It looks like we can actually do the swap. */
2545 if (! mips_opts.mips16)
2550 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2551 memcpy (temp, prev_f, 4);
2552 memcpy (prev_f, f, 4);
2553 memcpy (f, temp, 4);
2554 if (prev_insn_fixp[0])
2556 prev_insn_fixp[0]->fx_frag = frag_now;
2557 prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal;
2559 if (prev_insn_fixp[1])
2561 prev_insn_fixp[1]->fx_frag = frag_now;
2562 prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal;
2564 if (prev_insn_fixp[2])
2566 prev_insn_fixp[2]->fx_frag = frag_now;
2567 prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal;
2571 fixp[0]->fx_frag = prev_insn_frag;
2572 fixp[0]->fx_where = prev_insn_where;
2576 fixp[1]->fx_frag = prev_insn_frag;
2577 fixp[1]->fx_where = prev_insn_where;
2581 fixp[2]->fx_frag = prev_insn_frag;
2582 fixp[2]->fx_where = prev_insn_where;
2590 assert (prev_insn_fixp[0] == NULL);
2591 assert (prev_insn_fixp[1] == NULL);
2592 assert (prev_insn_fixp[2] == NULL);
2593 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2594 memcpy (temp, prev_f, 2);
2595 memcpy (prev_f, f, 2);
2596 if (*reloc_type != BFD_RELOC_MIPS16_JMP)
2598 assert (*reloc_type == BFD_RELOC_UNUSED);
2599 memcpy (f, temp, 2);
2603 memcpy (f, f + 2, 2);
2604 memcpy (f + 2, temp, 2);
2608 fixp[0]->fx_frag = prev_insn_frag;
2609 fixp[0]->fx_where = prev_insn_where;
2613 fixp[1]->fx_frag = prev_insn_frag;
2614 fixp[1]->fx_where = prev_insn_where;
2618 fixp[2]->fx_frag = prev_insn_frag;
2619 fixp[2]->fx_where = prev_insn_where;
2623 /* Update the previous insn information; leave prev_insn
2625 prev_prev_insn = *ip;
2627 prev_insn_is_delay_slot = 1;
2629 /* If that was an unconditional branch, forget the previous
2630 insn information. */
2631 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
2633 prev_prev_insn.insn_mo = &dummy_opcode;
2634 prev_insn.insn_mo = &dummy_opcode;
2637 prev_insn_fixp[0] = NULL;
2638 prev_insn_fixp[1] = NULL;
2639 prev_insn_fixp[2] = NULL;
2640 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2641 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2642 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2643 prev_insn_extended = 0;
2645 else if (pinfo & INSN_COND_BRANCH_LIKELY)
2647 /* We don't yet optimize a branch likely. What we should do
2648 is look at the target, copy the instruction found there
2649 into the delay slot, and increment the branch to jump to
2650 the next instruction. */
2652 /* Update the previous insn information. */
2653 prev_prev_insn = *ip;
2654 prev_insn.insn_mo = &dummy_opcode;
2655 prev_insn_fixp[0] = NULL;
2656 prev_insn_fixp[1] = NULL;
2657 prev_insn_fixp[2] = NULL;
2658 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2659 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2660 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2661 prev_insn_extended = 0;
2665 /* Update the previous insn information. */
2667 prev_prev_insn.insn_mo = &dummy_opcode;
2669 prev_prev_insn = prev_insn;
2672 /* Any time we see a branch, we always fill the delay slot
2673 immediately; since this insn is not a branch, we know it
2674 is not in a delay slot. */
2675 prev_insn_is_delay_slot = 0;
2677 prev_insn_fixp[0] = fixp[0];
2678 prev_insn_fixp[1] = fixp[1];
2679 prev_insn_fixp[2] = fixp[2];
2680 prev_insn_reloc_type[0] = reloc_type[0];
2681 prev_insn_reloc_type[1] = reloc_type[1];
2682 prev_insn_reloc_type[2] = reloc_type[2];
2683 if (mips_opts.mips16)
2684 prev_insn_extended = (ip->use_extend
2685 || *reloc_type > BFD_RELOC_UNUSED);
2688 prev_prev_insn_unreordered = prev_insn_unreordered;
2689 prev_insn_unreordered = 0;
2690 prev_insn_frag = frag_now;
2691 prev_insn_where = f - frag_now->fr_literal;
2692 prev_insn_valid = 1;
2694 else if (place == NULL)
2696 /* We need to record a bit of information even when we are not
2697 reordering, in order to determine the base address for mips16
2698 PC relative relocs. */
2699 prev_prev_insn = prev_insn;
2701 prev_insn_reloc_type[0] = reloc_type[0];
2702 prev_insn_reloc_type[1] = reloc_type[1];
2703 prev_insn_reloc_type[2] = reloc_type[2];
2704 prev_prev_insn_unreordered = prev_insn_unreordered;
2705 prev_insn_unreordered = 1;
2708 /* We just output an insn, so the next one doesn't have a label. */
2709 mips_clear_insn_labels ();
2711 /* We must ensure that a fixup associated with an unmatched %hi
2712 reloc does not become a variant frag. Otherwise, the
2713 rearrangement of %hi relocs in frob_file may confuse
2717 frag_wane (frag_now);
2722 /* This function forgets that there was any previous instruction or
2723 label. If PRESERVE is non-zero, it remembers enough information to
2724 know whether nops are needed before a noreorder section. */
2727 mips_no_prev_insn (preserve)
2732 prev_insn.insn_mo = &dummy_opcode;
2733 prev_prev_insn.insn_mo = &dummy_opcode;
2734 prev_nop_frag = NULL;
2735 prev_nop_frag_holds = 0;
2736 prev_nop_frag_required = 0;
2737 prev_nop_frag_since = 0;
2739 prev_insn_valid = 0;
2740 prev_insn_is_delay_slot = 0;
2741 prev_insn_unreordered = 0;
2742 prev_insn_extended = 0;
2743 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2744 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2745 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2746 prev_prev_insn_unreordered = 0;
2747 mips_clear_insn_labels ();
2750 /* This function must be called whenever we turn on noreorder or emit
2751 something other than instructions. It inserts any NOPS which might
2752 be needed by the previous instruction, and clears the information
2753 kept for the previous instructions. The INSNS parameter is true if
2754 instructions are to follow. */
2757 mips_emit_delays (insns)
2760 if (! mips_opts.noreorder)
2765 if ((! mips_opts.mips16
2766 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2767 && (! cop_interlocks
2768 && (prev_insn.insn_mo->pinfo
2769 & (INSN_LOAD_COPROC_DELAY
2770 | INSN_COPROC_MOVE_DELAY
2771 | INSN_WRITE_COND_CODE))))
2772 || (! hilo_interlocks
2773 && (prev_insn.insn_mo->pinfo
2776 || (! mips_opts.mips16
2778 && (prev_insn.insn_mo->pinfo
2779 & INSN_LOAD_MEMORY_DELAY))
2780 || (! mips_opts.mips16
2781 && mips_opts.isa == ISA_MIPS1
2782 && (prev_insn.insn_mo->pinfo
2783 & INSN_COPROC_MEMORY_DELAY)))
2785 /* Itbl support may require additional care here. */
2787 if ((! mips_opts.mips16
2788 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2789 && (! cop_interlocks
2790 && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
2791 || (! hilo_interlocks
2792 && ((prev_insn.insn_mo->pinfo & INSN_READ_HI)
2793 || (prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2796 if (prev_insn_unreordered)
2799 else if ((! mips_opts.mips16
2800 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2801 && (! cop_interlocks
2802 && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
2803 || (! hilo_interlocks
2804 && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
2805 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2807 /* Itbl support may require additional care here. */
2808 if (! prev_prev_insn_unreordered)
2814 struct insn_label_list *l;
2818 /* Record the frag which holds the nop instructions, so
2819 that we can remove them if we don't need them. */
2820 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
2821 prev_nop_frag = frag_now;
2822 prev_nop_frag_holds = nops;
2823 prev_nop_frag_required = 0;
2824 prev_nop_frag_since = 0;
2827 for (; nops > 0; --nops)
2832 /* Move on to a new frag, so that it is safe to simply
2833 decrease the size of prev_nop_frag. */
2834 frag_wane (frag_now);
2838 for (l = insn_labels; l != NULL; l = l->next)
2842 assert (S_GET_SEGMENT (l->label) == now_seg);
2843 symbol_set_frag (l->label, frag_now);
2844 val = (valueT) frag_now_fix ();
2845 /* mips16 text labels are stored as odd. */
2846 if (mips_opts.mips16)
2848 S_SET_VALUE (l->label, val);
2853 /* Mark instruction labels in mips16 mode. */
2855 mips16_mark_labels ();
2857 mips_no_prev_insn (insns);
2860 /* Build an instruction created by a macro expansion. This is passed
2861 a pointer to the count of instructions created so far, an
2862 expression, the name of the instruction to build, an operand format
2863 string, and corresponding arguments. */
2867 macro_build (char *place,
2875 macro_build (place, counter, ep, name, fmt, va_alist)
2884 struct mips_cl_insn insn;
2885 bfd_reloc_code_real_type r[3];
2889 va_start (args, fmt);
2895 * If the macro is about to expand into a second instruction,
2896 * print a warning if needed. We need to pass ip as a parameter
2897 * to generate a better warning message here...
2899 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
2900 as_warn (_("Macro instruction expanded into multiple instructions"));
2903 * If the macro is about to expand into a second instruction,
2904 * and it is in a delay slot, print a warning.
2908 && mips_opts.noreorder
2909 && (prev_prev_insn.insn_mo->pinfo
2910 & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY
2911 | INSN_COND_BRANCH_LIKELY)) != 0)
2912 as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot"));
2915 ++*counter; /* bump instruction counter */
2917 if (mips_opts.mips16)
2919 mips16_macro_build (place, counter, ep, name, fmt, args);
2924 r[0] = BFD_RELOC_UNUSED;
2925 r[1] = BFD_RELOC_UNUSED;
2926 r[2] = BFD_RELOC_UNUSED;
2927 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
2928 assert (insn.insn_mo);
2929 assert (strcmp (name, insn.insn_mo->name) == 0);
2931 /* Search until we get a match for NAME. */
2934 /* It is assumed here that macros will never generate
2935 MDMX or MIPS-3D instructions. */
2936 if (strcmp (fmt, insn.insn_mo->args) == 0
2937 && insn.insn_mo->pinfo != INSN_MACRO
2938 && OPCODE_IS_MEMBER (insn.insn_mo, mips_opts.isa, mips_arch)
2939 && (mips_arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
2943 assert (insn.insn_mo->name);
2944 assert (strcmp (name, insn.insn_mo->name) == 0);
2947 insn.insn_opcode = insn.insn_mo->match;
2963 insn.insn_opcode |= va_arg (args, int) << OP_SH_RT;
2967 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE;
2972 insn.insn_opcode |= va_arg (args, int) << OP_SH_FT;
2977 insn.insn_opcode |= va_arg (args, int) << OP_SH_RD;
2982 int tmp = va_arg (args, int);
2984 insn.insn_opcode |= tmp << OP_SH_RT;
2985 insn.insn_opcode |= tmp << OP_SH_RD;
2991 insn.insn_opcode |= va_arg (args, int) << OP_SH_FS;
2998 insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT;
3002 insn.insn_opcode |= va_arg (args, int) << OP_SH_FD;
3006 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20;
3010 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19;
3014 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2;
3021 insn.insn_opcode |= va_arg (args, int) << OP_SH_RS;
3027 *r = (bfd_reloc_code_real_type) va_arg (args, int);
3028 assert (*r == BFD_RELOC_GPREL16
3029 || *r == BFD_RELOC_MIPS_LITERAL
3030 || *r == BFD_RELOC_MIPS_HIGHER
3031 || *r == BFD_RELOC_HI16_S
3032 || *r == BFD_RELOC_LO16
3033 || *r == BFD_RELOC_MIPS_GOT16
3034 || *r == BFD_RELOC_MIPS_CALL16
3035 || *r == BFD_RELOC_MIPS_GOT_DISP
3036 || *r == BFD_RELOC_MIPS_GOT_PAGE
3037 || *r == BFD_RELOC_MIPS_GOT_OFST
3038 || *r == BFD_RELOC_MIPS_GOT_LO16
3039 || *r == BFD_RELOC_MIPS_CALL_LO16
3040 || (ep->X_op == O_subtract
3041 && *r == BFD_RELOC_PCREL_LO16));
3045 *r = (bfd_reloc_code_real_type) va_arg (args, int);
3047 && (ep->X_op == O_constant
3048 || (ep->X_op == O_symbol
3049 && (*r == BFD_RELOC_MIPS_HIGHEST
3050 || *r == BFD_RELOC_HI16_S
3051 || *r == BFD_RELOC_HI16
3052 || *r == BFD_RELOC_GPREL16
3053 || *r == BFD_RELOC_MIPS_GOT_HI16
3054 || *r == BFD_RELOC_MIPS_CALL_HI16))
3055 || (ep->X_op == O_subtract
3056 && *r == BFD_RELOC_PCREL_HI16_S)));
3060 assert (ep != NULL);
3062 * This allows macro() to pass an immediate expression for
3063 * creating short branches without creating a symbol.
3064 * Note that the expression still might come from the assembly
3065 * input, in which case the value is not checked for range nor
3066 * is a relocation entry generated (yuck).
3068 if (ep->X_op == O_constant)
3070 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
3074 if (mips_pic == EMBEDDED_PIC)
3075 *r = BFD_RELOC_16_PCREL_S2;
3077 *r = BFD_RELOC_16_PCREL;
3081 assert (ep != NULL);
3082 *r = BFD_RELOC_MIPS_JMP;
3086 insn.insn_opcode |= va_arg (args, unsigned long);
3095 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3097 append_insn (place, &insn, ep, r, false);
3101 mips16_macro_build (place, counter, ep, name, fmt, args)
3103 int *counter ATTRIBUTE_UNUSED;
3109 struct mips_cl_insn insn;
3110 bfd_reloc_code_real_type r[3]
3111 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3113 insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
3114 assert (insn.insn_mo);
3115 assert (strcmp (name, insn.insn_mo->name) == 0);
3117 while (strcmp (fmt, insn.insn_mo->args) != 0
3118 || insn.insn_mo->pinfo == INSN_MACRO)
3121 assert (insn.insn_mo->name);
3122 assert (strcmp (name, insn.insn_mo->name) == 0);
3125 insn.insn_opcode = insn.insn_mo->match;
3126 insn.use_extend = false;
3145 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY;
3150 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX;
3154 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ;
3158 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z;
3168 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32;
3175 regno = va_arg (args, int);
3176 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
3177 insn.insn_opcode |= regno << MIPS16OP_SH_REG32R;
3198 assert (ep != NULL);
3200 if (ep->X_op != O_constant)
3201 *r = (int) BFD_RELOC_UNUSED + c;
3204 mips16_immed (NULL, 0, c, ep->X_add_number, false, false,
3205 false, &insn.insn_opcode, &insn.use_extend,
3208 *r = BFD_RELOC_UNUSED;
3214 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6;
3221 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3223 append_insn (place, &insn, ep, r, false);
3227 * Generate a "jalr" instruction with a relocation hint to the called
3228 * function. This occurs in NewABI PIC code.
3231 macro_build_jalr (icnt, ep)
3237 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", "d,s",
3240 fix_new_exp (frag_now, 0, 0, ep, false, BFD_RELOC_MIPS_JALR);
3244 * Generate a "lui" instruction.
3247 macro_build_lui (place, counter, ep, regnum)
3253 expressionS high_expr;
3254 struct mips_cl_insn insn;
3255 bfd_reloc_code_real_type r[3]
3256 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3257 CONST char *name = "lui";
3258 CONST char *fmt = "t,u";
3260 assert (! mips_opts.mips16);
3266 high_expr.X_op = O_constant;
3267 high_expr.X_add_number = ep->X_add_number;
3270 if (high_expr.X_op == O_constant)
3272 /* we can compute the instruction now without a relocation entry */
3273 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
3275 *r = BFD_RELOC_UNUSED;
3277 else if (! HAVE_NEWABI)
3279 assert (ep->X_op == O_symbol);
3280 /* _gp_disp is a special case, used from s_cpload. */
3281 assert (mips_pic == NO_PIC
3282 || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0);
3283 *r = BFD_RELOC_HI16_S;
3287 * If the macro is about to expand into a second instruction,
3288 * print a warning if needed. We need to pass ip as a parameter
3289 * to generate a better warning message here...
3291 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
3292 as_warn (_("Macro instruction expanded into multiple instructions"));
3295 ++*counter; /* bump instruction counter */
3297 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
3298 assert (insn.insn_mo);
3299 assert (strcmp (name, insn.insn_mo->name) == 0);
3300 assert (strcmp (fmt, insn.insn_mo->args) == 0);
3302 insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT);
3303 if (*r == BFD_RELOC_UNUSED)
3305 insn.insn_opcode |= high_expr.X_add_number;
3306 append_insn (place, &insn, NULL, r, false);
3309 append_insn (place, &insn, &high_expr, r, false);
3313 * Generates code to set the $at register to true (one)
3314 * if reg is less than the immediate expression.
3317 set_at (counter, reg, unsignedp)
3322 if (imm_expr.X_op == O_constant
3323 && imm_expr.X_add_number >= -0x8000
3324 && imm_expr.X_add_number < 0x8000)
3325 macro_build ((char *) NULL, counter, &imm_expr,
3326 unsignedp ? "sltiu" : "slti",
3327 "t,r,j", AT, reg, (int) BFD_RELOC_LO16);
3330 load_register (counter, AT, &imm_expr, HAVE_64BIT_GPRS);
3331 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3332 unsignedp ? "sltu" : "slt",
3333 "d,v,t", AT, reg, AT);
3337 /* Warn if an expression is not a constant. */
3340 check_absolute_expr (ip, ex)
3341 struct mips_cl_insn *ip;
3344 if (ex->X_op == O_big)
3345 as_bad (_("unsupported large constant"));
3346 else if (ex->X_op != O_constant)
3347 as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name);
3350 /* Count the leading zeroes by performing a binary chop. This is a
3351 bulky bit of source, but performance is a LOT better for the
3352 majority of values than a simple loop to count the bits:
3353 for (lcnt = 0; (lcnt < 32); lcnt++)
3354 if ((v) & (1 << (31 - lcnt)))
3356 However it is not code size friendly, and the gain will drop a bit
3357 on certain cached systems.
3359 #define COUNT_TOP_ZEROES(v) \
3360 (((v) & ~0xffff) == 0 \
3361 ? ((v) & ~0xff) == 0 \
3362 ? ((v) & ~0xf) == 0 \
3363 ? ((v) & ~0x3) == 0 \
3364 ? ((v) & ~0x1) == 0 \
3369 : ((v) & ~0x7) == 0 \
3372 : ((v) & ~0x3f) == 0 \
3373 ? ((v) & ~0x1f) == 0 \
3376 : ((v) & ~0x7f) == 0 \
3379 : ((v) & ~0xfff) == 0 \
3380 ? ((v) & ~0x3ff) == 0 \
3381 ? ((v) & ~0x1ff) == 0 \
3384 : ((v) & ~0x7ff) == 0 \
3387 : ((v) & ~0x3fff) == 0 \
3388 ? ((v) & ~0x1fff) == 0 \
3391 : ((v) & ~0x7fff) == 0 \
3394 : ((v) & ~0xffffff) == 0 \
3395 ? ((v) & ~0xfffff) == 0 \
3396 ? ((v) & ~0x3ffff) == 0 \
3397 ? ((v) & ~0x1ffff) == 0 \
3400 : ((v) & ~0x7ffff) == 0 \
3403 : ((v) & ~0x3fffff) == 0 \
3404 ? ((v) & ~0x1fffff) == 0 \
3407 : ((v) & ~0x7fffff) == 0 \
3410 : ((v) & ~0xfffffff) == 0 \
3411 ? ((v) & ~0x3ffffff) == 0 \
3412 ? ((v) & ~0x1ffffff) == 0 \
3415 : ((v) & ~0x7ffffff) == 0 \
3418 : ((v) & ~0x3fffffff) == 0 \
3419 ? ((v) & ~0x1fffffff) == 0 \
3422 : ((v) & ~0x7fffffff) == 0 \
3426 /* Is the given value a sign-extended 32-bit value? */
3427 #define IS_SEXT_32BIT_NUM(x) \
3428 (((x) &~ (offsetT) 0x7fffffff) == 0 \
3429 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
3432 * This routine generates the least number of instructions neccessary to load
3433 * an absolute expression value into a register.
3436 load_register (counter, reg, ep, dbl)
3443 expressionS hi32, lo32;
3445 if (ep->X_op != O_big)
3447 assert (ep->X_op == O_constant);
3448 if (ep->X_add_number < 0x8000
3449 && (ep->X_add_number >= 0
3450 || (ep->X_add_number >= -0x8000
3453 || sizeof (ep->X_add_number) > 4))))
3455 /* We can handle 16 bit signed values with an addiu to
3456 $zero. No need to ever use daddiu here, since $zero and
3457 the result are always correct in 32 bit mode. */
3458 macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3459 (int) BFD_RELOC_LO16);
3462 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
3464 /* We can handle 16 bit unsigned values with an ori to
3466 macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0,
3467 (int) BFD_RELOC_LO16);
3470 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)
3473 || sizeof (ep->X_add_number) > 4
3474 || (ep->X_add_number & 0x80000000) == 0))
3475 || ((HAVE_32BIT_GPRS || ! dbl)
3476 && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0)
3479 && ((ep->X_add_number &~ (offsetT) 0xffffffff)
3480 == ~ (offsetT) 0xffffffff)))
3482 /* 32 bit values require an lui. */
3483 macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg,
3484 (int) BFD_RELOC_HI16);
3485 if ((ep->X_add_number & 0xffff) != 0)
3486 macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg,
3487 (int) BFD_RELOC_LO16);
3492 /* The value is larger than 32 bits. */
3494 if (HAVE_32BIT_GPRS)
3496 as_bad (_("Number (0x%lx) larger than 32 bits"),
3497 (unsigned long) ep->X_add_number);
3498 macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3499 (int) BFD_RELOC_LO16);
3503 if (ep->X_op != O_big)
3506 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3507 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3508 hi32.X_add_number &= 0xffffffff;
3510 lo32.X_add_number &= 0xffffffff;
3514 assert (ep->X_add_number > 2);
3515 if (ep->X_add_number == 3)
3516 generic_bignum[3] = 0;
3517 else if (ep->X_add_number > 4)
3518 as_bad (_("Number larger than 64 bits"));
3519 lo32.X_op = O_constant;
3520 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
3521 hi32.X_op = O_constant;
3522 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
3525 if (hi32.X_add_number == 0)
3530 unsigned long hi, lo;
3532 if (hi32.X_add_number == (offsetT) 0xffffffff)
3534 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
3536 macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j",
3537 reg, 0, (int) BFD_RELOC_LO16);
3540 if (lo32.X_add_number & 0x80000000)
3542 macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg,
3543 (int) BFD_RELOC_HI16);
3544 if (lo32.X_add_number & 0xffff)
3545 macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i",
3546 reg, reg, (int) BFD_RELOC_LO16);
3551 /* Check for 16bit shifted constant. We know that hi32 is
3552 non-zero, so start the mask on the first bit of the hi32
3557 unsigned long himask, lomask;
3561 himask = 0xffff >> (32 - shift);
3562 lomask = (0xffff << shift) & 0xffffffff;
3566 himask = 0xffff << (shift - 32);
3569 if ((hi32.X_add_number & ~(offsetT) himask) == 0
3570 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
3574 tmp.X_op = O_constant;
3576 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
3577 | (lo32.X_add_number >> shift));
3579 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
3580 macro_build ((char *) NULL, counter, &tmp,
3581 "ori", "t,r,i", reg, 0,
3582 (int) BFD_RELOC_LO16);
3583 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3584 (shift >= 32) ? "dsll32" : "dsll",
3586 (shift >= 32) ? shift - 32 : shift);
3591 while (shift <= (64 - 16));
3593 /* Find the bit number of the lowest one bit, and store the
3594 shifted value in hi/lo. */
3595 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
3596 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
3600 while ((lo & 1) == 0)
3605 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
3611 while ((hi & 1) == 0)
3620 /* Optimize if the shifted value is a (power of 2) - 1. */
3621 if ((hi == 0 && ((lo + 1) & lo) == 0)
3622 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
3624 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
3629 /* This instruction will set the register to be all
3631 tmp.X_op = O_constant;
3632 tmp.X_add_number = (offsetT) -1;
3633 macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j",
3634 reg, 0, (int) BFD_RELOC_LO16);
3638 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3639 (bit >= 32) ? "dsll32" : "dsll",
3641 (bit >= 32) ? bit - 32 : bit);
3643 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3644 (shift >= 32) ? "dsrl32" : "dsrl",
3646 (shift >= 32) ? shift - 32 : shift);
3651 /* Sign extend hi32 before calling load_register, because we can
3652 generally get better code when we load a sign extended value. */
3653 if ((hi32.X_add_number & 0x80000000) != 0)
3654 hi32.X_add_number |= ~(offsetT) 0xffffffff;
3655 load_register (counter, reg, &hi32, 0);
3658 if ((lo32.X_add_number & 0xffff0000) == 0)
3662 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3663 "dsll32", "d,w,<", reg, freg, 0);
3671 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
3673 macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg,
3674 (int) BFD_RELOC_HI16);
3675 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3676 "dsrl32", "d,w,<", reg, reg, 0);
3682 macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll",
3683 "d,w,<", reg, freg, 16);
3687 mid16.X_add_number >>= 16;
3688 macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg,
3689 freg, (int) BFD_RELOC_LO16);
3690 macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll",
3691 "d,w,<", reg, reg, 16);
3694 if ((lo32.X_add_number & 0xffff) != 0)
3695 macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg,
3696 (int) BFD_RELOC_LO16);
3699 /* Load an address into a register. */
3702 load_address (counter, reg, ep, used_at)
3710 if (ep->X_op != O_constant
3711 && ep->X_op != O_symbol)
3713 as_bad (_("expression too complex"));
3714 ep->X_op = O_constant;
3717 if (ep->X_op == O_constant)
3719 load_register (counter, reg, ep, HAVE_64BIT_ADDRESSES);
3723 if (mips_pic == NO_PIC)
3725 /* If this is a reference to a GP relative symbol, we want
3726 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3728 lui $reg,<sym> (BFD_RELOC_HI16_S)
3729 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3730 If we have an addend, we always use the latter form.
3732 With 64bit address space and a usable $at we want
3733 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3734 lui $at,<sym> (BFD_RELOC_HI16_S)
3735 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3736 daddiu $at,<sym> (BFD_RELOC_LO16)
3740 If $at is already in use, we use an path which is suboptimal
3741 on superscalar processors.
3742 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3743 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3745 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3747 daddiu $reg,<sym> (BFD_RELOC_LO16)
3749 if (HAVE_64BIT_ADDRESSES)
3751 /* We don't do GP optimization for now because RELAX_ENCODE can't
3752 hold the data for such large chunks. */
3756 macro_build (p, counter, ep, "lui", "t,u",
3757 reg, (int) BFD_RELOC_MIPS_HIGHEST);
3758 macro_build (p, counter, ep, "lui", "t,u",
3759 AT, (int) BFD_RELOC_HI16_S);
3760 macro_build (p, counter, ep, "daddiu", "t,r,j",
3761 reg, reg, (int) BFD_RELOC_MIPS_HIGHER);
3762 macro_build (p, counter, ep, "daddiu", "t,r,j",
3763 AT, AT, (int) BFD_RELOC_LO16);
3764 macro_build (p, counter, (expressionS *) NULL, "dsll32",
3765 "d,w,<", reg, reg, 0);
3766 macro_build (p, counter, (expressionS *) NULL, "dadd",
3767 "d,v,t", reg, reg, AT);
3772 macro_build (p, counter, ep, "lui", "t,u",
3773 reg, (int) BFD_RELOC_MIPS_HIGHEST);
3774 macro_build (p, counter, ep, "daddiu", "t,r,j",
3775 reg, reg, (int) BFD_RELOC_MIPS_HIGHER);
3776 macro_build (p, counter, (expressionS *) NULL, "dsll",
3777 "d,w,<", reg, reg, 16);
3778 macro_build (p, counter, ep, "daddiu", "t,r,j",
3779 reg, reg, (int) BFD_RELOC_HI16_S);
3780 macro_build (p, counter, (expressionS *) NULL, "dsll",
3781 "d,w,<", reg, reg, 16);
3782 macro_build (p, counter, ep, "daddiu", "t,r,j",
3783 reg, reg, (int) BFD_RELOC_LO16);
3788 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
3789 && ! nopic_need_relax (ep->X_add_symbol, 1))
3792 macro_build ((char *) NULL, counter, ep,
3793 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j",
3794 reg, mips_gp_register, (int) BFD_RELOC_GPREL16);
3795 p = frag_var (rs_machine_dependent, 8, 0,
3796 RELAX_ENCODE (4, 8, 0, 4, 0,
3797 mips_opts.warn_about_macros),
3798 ep->X_add_symbol, 0, NULL);
3800 macro_build_lui (p, counter, ep, reg);
3803 macro_build (p, counter, ep,
3804 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3805 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3808 else if (mips_pic == SVR4_PIC && ! mips_big_got)
3812 /* If this is a reference to an external symbol, we want
3813 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3815 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3817 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3818 If there is a constant, it must be added in after. */
3819 ex.X_add_number = ep->X_add_number;
3820 ep->X_add_number = 0;
3822 macro_build ((char *) NULL, counter, ep,
3823 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)",
3824 reg, (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
3825 macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", "");
3826 p = frag_var (rs_machine_dependent, 4, 0,
3827 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros),
3828 ep->X_add_symbol, (offsetT) 0, (char *) NULL);
3829 macro_build (p, counter, ep,
3830 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3831 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3832 if (ex.X_add_number != 0)
3834 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3835 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3836 ex.X_op = O_constant;
3837 macro_build ((char *) NULL, counter, &ex,
3838 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3839 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3842 else if (mips_pic == SVR4_PIC)
3847 /* This is the large GOT case. If this is a reference to an
3848 external symbol, we want
3849 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3851 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3852 Otherwise, for a reference to a local symbol, we want
3853 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3855 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3856 If we have NewABI, we want
3857 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3858 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3859 If there is a constant, it must be added in after. */
3860 ex.X_add_number = ep->X_add_number;
3861 ep->X_add_number = 0;
3864 macro_build ((char *) NULL, counter, ep,
3865 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg,
3866 (int) BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
3867 macro_build (p, counter, ep,
3868 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j",
3869 reg, reg, (int) BFD_RELOC_MIPS_GOT_OFST);
3873 if (reg_needs_delay (mips_gp_register))
3878 macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg,
3879 (int) BFD_RELOC_MIPS_GOT_HI16);
3880 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3881 HAVE_32BIT_ADDRESSES ? "addu" : "daddu", "d,v,t", reg,
3882 reg, mips_gp_register);
3883 macro_build ((char *) NULL, counter, ep,
3884 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
3885 "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg);
3886 p = frag_var (rs_machine_dependent, 12 + off, 0,
3887 RELAX_ENCODE (12, 12 + off, off, 8 + off, 0,
3888 mips_opts.warn_about_macros),
3889 ep->X_add_symbol, 0, NULL);
3892 /* We need a nop before loading from $gp. This special
3893 check is required because the lui which starts the main
3894 instruction stream does not refer to $gp, and so will not
3895 insert the nop which may be required. */
3896 macro_build (p, counter, (expressionS *) NULL, "nop", "");
3899 macro_build (p, counter, ep,
3900 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg,
3901 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
3903 macro_build (p, counter, (expressionS *) NULL, "nop", "");
3905 macro_build (p, counter, ep,
3906 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3907 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3910 if (ex.X_add_number != 0)
3912 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3913 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3914 ex.X_op = O_constant;
3915 macro_build ((char *) NULL, counter, &ex,
3916 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3917 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3920 else if (mips_pic == EMBEDDED_PIC)
3923 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3925 macro_build ((char *) NULL, counter, ep,
3926 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3927 "t,r,j", reg, mips_gp_register, (int) BFD_RELOC_GPREL16);
3933 /* Move the contents of register SOURCE into register DEST. */
3936 move_register (counter, dest, source)
3941 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3942 HAVE_32BIT_GPRS ? "addu" : "daddu",
3943 "d,v,t", dest, source, 0);
3948 * This routine implements the seemingly endless macro or synthesized
3949 * instructions and addressing modes in the mips assembly language. Many
3950 * of these macros are simple and are similar to each other. These could
3951 * probably be handled by some kind of table or grammer aproach instead of
3952 * this verbose method. Others are not simple macros but are more like
3953 * optimizing code generation.
3954 * One interesting optimization is when several store macros appear
3955 * consecutivly that would load AT with the upper half of the same address.
3956 * The ensuing load upper instructions are ommited. This implies some kind
3957 * of global optimization. We currently only optimize within a single macro.
3958 * For many of the load and store macros if the address is specified as a
3959 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3960 * first load register 'at' with zero and use it as the base register. The
3961 * mips assembler simply uses register $zero. Just one tiny optimization
3966 struct mips_cl_insn *ip;
3968 register int treg, sreg, dreg, breg;
3984 bfd_reloc_code_real_type r;
3985 int hold_mips_optimize;
3987 assert (! mips_opts.mips16);
3989 treg = (ip->insn_opcode >> 16) & 0x1f;
3990 dreg = (ip->insn_opcode >> 11) & 0x1f;
3991 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
3992 mask = ip->insn_mo->mask;
3994 expr1.X_op = O_constant;
3995 expr1.X_op_symbol = NULL;
3996 expr1.X_add_symbol = NULL;
3997 expr1.X_add_number = 1;
4009 mips_emit_delays (true);
4010 ++mips_opts.noreorder;
4011 mips_any_noreorder = 1;
4013 expr1.X_add_number = 8;
4014 macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg);
4016 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
4019 move_register (&icnt, dreg, sreg);
4020 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4021 dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
4023 --mips_opts.noreorder;
4044 if (imm_expr.X_op == O_constant
4045 && imm_expr.X_add_number >= -0x8000
4046 && imm_expr.X_add_number < 0x8000)
4048 macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg,
4049 (int) BFD_RELOC_LO16);
4052 load_register (&icnt, AT, &imm_expr, dbl);
4053 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t",
4073 if (imm_expr.X_op == O_constant
4074 && imm_expr.X_add_number >= 0
4075 && imm_expr.X_add_number < 0x10000)
4077 if (mask != M_NOR_I)
4078 macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg,
4079 sreg, (int) BFD_RELOC_LO16);
4082 macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i",
4083 treg, sreg, (int) BFD_RELOC_LO16);
4084 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nor",
4085 "d,v,t", treg, treg, 0);
4090 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
4091 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t",
4109 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4111 macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg,
4115 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
4116 macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT);
4124 macro_build ((char *) NULL, &icnt, &offset_expr,
4125 likely ? "bgezl" : "bgez", "s,p", sreg);
4130 macro_build ((char *) NULL, &icnt, &offset_expr,
4131 likely ? "blezl" : "blez", "s,p", treg);
4134 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4136 macro_build ((char *) NULL, &icnt, &offset_expr,
4137 likely ? "beql" : "beq", "s,t,p", AT, 0);
4143 /* check for > max integer */
4144 maxnum = 0x7fffffff;
4145 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4152 if (imm_expr.X_op == O_constant
4153 && imm_expr.X_add_number >= maxnum
4154 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4157 /* result is always false */
4161 as_warn (_("Branch %s is always false (nop)"),
4163 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop",
4169 as_warn (_("Branch likely %s is always false"),
4171 macro_build ((char *) NULL, &icnt, &offset_expr, "bnel",
4176 if (imm_expr.X_op != O_constant)
4177 as_bad (_("Unsupported large constant"));
4178 ++imm_expr.X_add_number;
4182 if (mask == M_BGEL_I)
4184 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4186 macro_build ((char *) NULL, &icnt, &offset_expr,
4187 likely ? "bgezl" : "bgez", "s,p", sreg);
4190 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4192 macro_build ((char *) NULL, &icnt, &offset_expr,
4193 likely ? "bgtzl" : "bgtz", "s,p", sreg);
4196 maxnum = 0x7fffffff;
4197 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4204 maxnum = - maxnum - 1;
4205 if (imm_expr.X_op == O_constant
4206 && imm_expr.X_add_number <= maxnum
4207 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4210 /* result is always true */
4211 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
4212 macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p");
4215 set_at (&icnt, sreg, 0);
4216 macro_build ((char *) NULL, &icnt, &offset_expr,
4217 likely ? "beql" : "beq", "s,t,p", AT, 0);
4227 macro_build ((char *) NULL, &icnt, &offset_expr,
4228 likely ? "beql" : "beq", "s,t,p", 0, treg);
4231 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4232 "d,v,t", AT, sreg, treg);
4233 macro_build ((char *) NULL, &icnt, &offset_expr,
4234 likely ? "beql" : "beq", "s,t,p", AT, 0);
4242 && imm_expr.X_op == O_constant
4243 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4245 if (imm_expr.X_op != O_constant)
4246 as_bad (_("Unsupported large constant"));
4247 ++imm_expr.X_add_number;
4251 if (mask == M_BGEUL_I)
4253 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4255 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4257 macro_build ((char *) NULL, &icnt, &offset_expr,
4258 likely ? "bnel" : "bne", "s,t,p", sreg, 0);
4261 set_at (&icnt, sreg, 1);
4262 macro_build ((char *) NULL, &icnt, &offset_expr,
4263 likely ? "beql" : "beq", "s,t,p", AT, 0);
4271 macro_build ((char *) NULL, &icnt, &offset_expr,
4272 likely ? "bgtzl" : "bgtz", "s,p", sreg);
4277 macro_build ((char *) NULL, &icnt, &offset_expr,
4278 likely ? "bltzl" : "bltz", "s,p", treg);
4281 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4283 macro_build ((char *) NULL, &icnt, &offset_expr,
4284 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4292 macro_build ((char *) NULL, &icnt, &offset_expr,
4293 likely ? "bnel" : "bne", "s,t,p", sreg, 0);
4298 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4299 "d,v,t", AT, treg, sreg);
4300 macro_build ((char *) NULL, &icnt, &offset_expr,
4301 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4309 macro_build ((char *) NULL, &icnt, &offset_expr,
4310 likely ? "blezl" : "blez", "s,p", sreg);
4315 macro_build ((char *) NULL, &icnt, &offset_expr,
4316 likely ? "bgezl" : "bgez", "s,p", treg);
4319 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4321 macro_build ((char *) NULL, &icnt, &offset_expr,
4322 likely ? "beql" : "beq", "s,t,p", AT, 0);
4328 maxnum = 0x7fffffff;
4329 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4336 if (imm_expr.X_op == O_constant
4337 && imm_expr.X_add_number >= maxnum
4338 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4340 if (imm_expr.X_op != O_constant)
4341 as_bad (_("Unsupported large constant"));
4342 ++imm_expr.X_add_number;
4346 if (mask == M_BLTL_I)
4348 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4350 macro_build ((char *) NULL, &icnt, &offset_expr,
4351 likely ? "bltzl" : "bltz", "s,p", sreg);
4354 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4356 macro_build ((char *) NULL, &icnt, &offset_expr,
4357 likely ? "blezl" : "blez", "s,p", sreg);
4360 set_at (&icnt, sreg, 0);
4361 macro_build ((char *) NULL, &icnt, &offset_expr,
4362 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4370 macro_build ((char *) NULL, &icnt, &offset_expr,
4371 likely ? "beql" : "beq", "s,t,p", sreg, 0);
4376 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4377 "d,v,t", AT, treg, sreg);
4378 macro_build ((char *) NULL, &icnt, &offset_expr,
4379 likely ? "beql" : "beq", "s,t,p", AT, 0);
4387 && imm_expr.X_op == O_constant
4388 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4390 if (imm_expr.X_op != O_constant)
4391 as_bad (_("Unsupported large constant"));
4392 ++imm_expr.X_add_number;
4396 if (mask == M_BLTUL_I)
4398 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4400 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4402 macro_build ((char *) NULL, &icnt, &offset_expr,
4403 likely ? "beql" : "beq",
4407 set_at (&icnt, sreg, 1);
4408 macro_build ((char *) NULL, &icnt, &offset_expr,
4409 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4417 macro_build ((char *) NULL, &icnt, &offset_expr,
4418 likely ? "bltzl" : "bltz", "s,p", sreg);
4423 macro_build ((char *) NULL, &icnt, &offset_expr,
4424 likely ? "bgtzl" : "bgtz", "s,p", treg);
4427 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4429 macro_build ((char *) NULL, &icnt, &offset_expr,
4430 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4440 macro_build ((char *) NULL, &icnt, &offset_expr,
4441 likely ? "bnel" : "bne", "s,t,p", 0, treg);
4444 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4447 macro_build ((char *) NULL, &icnt, &offset_expr,
4448 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4463 as_warn (_("Divide by zero."));
4465 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4468 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4473 mips_emit_delays (true);
4474 ++mips_opts.noreorder;
4475 mips_any_noreorder = 1;
4478 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4480 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4481 dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4485 expr1.X_add_number = 8;
4486 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4487 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4488 dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4489 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4492 expr1.X_add_number = -1;
4493 macro_build ((char *) NULL, &icnt, &expr1,
4494 dbl ? "daddiu" : "addiu",
4495 "t,r,j", AT, 0, (int) BFD_RELOC_LO16);
4496 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
4497 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT);
4500 expr1.X_add_number = 1;
4501 macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0,
4502 (int) BFD_RELOC_LO16);
4503 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsll32",
4504 "d,w,<", AT, AT, 31);
4508 expr1.X_add_number = 0x80000000;
4509 macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT,
4510 (int) BFD_RELOC_HI16);
4514 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4516 /* We want to close the noreorder block as soon as possible, so
4517 that later insns are available for delay slot filling. */
4518 --mips_opts.noreorder;
4522 expr1.X_add_number = 8;
4523 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT);
4524 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
4527 /* We want to close the noreorder block as soon as possible, so
4528 that later insns are available for delay slot filling. */
4529 --mips_opts.noreorder;
4531 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4534 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d", dreg);
4573 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4575 as_warn (_("Divide by zero."));
4577 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4580 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4584 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4586 if (strcmp (s2, "mflo") == 0)
4587 move_register (&icnt, dreg, sreg);
4589 move_register (&icnt, dreg, 0);
4592 if (imm_expr.X_op == O_constant
4593 && imm_expr.X_add_number == -1
4594 && s[strlen (s) - 1] != 'u')
4596 if (strcmp (s2, "mflo") == 0)
4598 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4599 dbl ? "dneg" : "neg", "d,w", dreg, sreg);
4602 move_register (&icnt, dreg, 0);
4606 load_register (&icnt, AT, &imm_expr, dbl);
4607 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4609 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg);
4628 mips_emit_delays (true);
4629 ++mips_opts.noreorder;
4630 mips_any_noreorder = 1;
4633 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4635 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4637 /* We want to close the noreorder block as soon as possible, so
4638 that later insns are available for delay slot filling. */
4639 --mips_opts.noreorder;
4643 expr1.X_add_number = 8;
4644 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4645 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4648 /* We want to close the noreorder block as soon as possible, so
4649 that later insns are available for delay slot filling. */
4650 --mips_opts.noreorder;
4651 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4654 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg);
4660 /* Load the address of a symbol into a register. If breg is not
4661 zero, we then add a base register to it. */
4663 if (dbl && HAVE_32BIT_GPRS)
4664 as_warn (_("dla used to load 32-bit register"));
4666 if (! dbl && HAVE_64BIT_OBJECTS)
4667 as_warn (_("la used to load 64-bit address"));
4680 /* When generating embedded PIC code, we permit expressions of
4683 la $treg,foo-bar($breg)
4684 where bar is an address in the current section. These are used
4685 when getting the addresses of functions. We don't permit
4686 X_add_number to be non-zero, because if the symbol is
4687 external the relaxing code needs to know that any addend is
4688 purely the offset to X_op_symbol. */
4689 if (mips_pic == EMBEDDED_PIC
4690 && offset_expr.X_op == O_subtract
4691 && (symbol_constant_p (offset_expr.X_op_symbol)
4692 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
4693 : (symbol_equated_p (offset_expr.X_op_symbol)
4695 (symbol_get_value_expression (offset_expr.X_op_symbol)
4698 && (offset_expr.X_add_number == 0
4699 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
4705 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4706 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
4710 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4711 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
4712 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4713 (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu",
4714 "d,v,t", tempreg, tempreg, breg);
4716 macro_build ((char *) NULL, &icnt, &offset_expr,
4717 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4718 "t,r,j", treg, tempreg, (int) BFD_RELOC_PCREL_LO16);
4724 if (offset_expr.X_op != O_symbol
4725 && offset_expr.X_op != O_constant)
4727 as_bad (_("expression too complex"));
4728 offset_expr.X_op = O_constant;
4731 if (offset_expr.X_op == O_constant)
4732 load_register (&icnt, tempreg, &offset_expr,
4733 ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
4734 ? (dbl || HAVE_64BIT_ADDRESSES)
4735 : HAVE_64BIT_ADDRESSES));
4736 else if (mips_pic == NO_PIC)
4738 /* If this is a reference to a GP relative symbol, we want
4739 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4741 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4742 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4743 If we have a constant, we need two instructions anyhow,
4744 so we may as well always use the latter form.
4746 With 64bit address space and a usable $at we want
4747 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4748 lui $at,<sym> (BFD_RELOC_HI16_S)
4749 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4750 daddiu $at,<sym> (BFD_RELOC_LO16)
4752 dadd $tempreg,$tempreg,$at
4754 If $at is already in use, we use an path which is suboptimal
4755 on superscalar processors.
4756 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4757 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4759 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4761 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4764 if (HAVE_64BIT_ADDRESSES)
4766 /* We don't do GP optimization for now because RELAX_ENCODE can't
4767 hold the data for such large chunks. */
4771 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4772 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
4773 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4774 AT, (int) BFD_RELOC_HI16_S);
4775 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4776 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
4777 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4778 AT, AT, (int) BFD_RELOC_LO16);
4779 macro_build (p, &icnt, (expressionS *) NULL, "dsll32",
4780 "d,w,<", tempreg, tempreg, 0);
4781 macro_build (p, &icnt, (expressionS *) NULL, "dadd", "d,v,t",
4782 tempreg, tempreg, AT);
4787 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4788 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
4789 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4790 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
4791 macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<",
4792 tempreg, tempreg, 16);
4793 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4794 tempreg, tempreg, (int) BFD_RELOC_HI16_S);
4795 macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<",
4796 tempreg, tempreg, 16);
4797 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4798 tempreg, tempreg, (int) BFD_RELOC_LO16);
4803 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
4804 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
4807 macro_build ((char *) NULL, &icnt, &offset_expr, "addiu",
4808 "t,r,j", tempreg, mips_gp_register,
4809 (int) BFD_RELOC_GPREL16);
4810 p = frag_var (rs_machine_dependent, 8, 0,
4811 RELAX_ENCODE (4, 8, 0, 4, 0,
4812 mips_opts.warn_about_macros),
4813 offset_expr.X_add_symbol, 0, NULL);
4815 macro_build_lui (p, &icnt, &offset_expr, tempreg);
4818 macro_build (p, &icnt, &offset_expr, "addiu",
4819 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4822 else if (mips_pic == SVR4_PIC && ! mips_big_got)
4824 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
4826 /* If this is a reference to an external symbol, and there
4827 is no constant, we want
4828 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4829 or if tempreg is PIC_CALL_REG
4830 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4831 For a local symbol, we want
4832 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4834 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4836 If we have a small constant, and this is a reference to
4837 an external symbol, we want
4838 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4840 addiu $tempreg,$tempreg,<constant>
4841 For a local symbol, we want the same instruction
4842 sequence, but we output a BFD_RELOC_LO16 reloc on the
4845 If we have a large constant, and this is a reference to
4846 an external symbol, we want
4847 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4848 lui $at,<hiconstant>
4849 addiu $at,$at,<loconstant>
4850 addu $tempreg,$tempreg,$at
4851 For a local symbol, we want the same instruction
4852 sequence, but we output a BFD_RELOC_LO16 reloc on the
4853 addiu instruction. */
4854 expr1.X_add_number = offset_expr.X_add_number;
4855 offset_expr.X_add_number = 0;
4857 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
4858 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
4859 macro_build ((char *) NULL, &icnt, &offset_expr,
4860 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
4861 "t,o(b)", tempreg, lw_reloc_type, mips_gp_register);
4862 if (expr1.X_add_number == 0)
4871 /* We're going to put in an addu instruction using
4872 tempreg, so we may as well insert the nop right
4874 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4878 p = frag_var (rs_machine_dependent, 8 - off, 0,
4879 RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0,
4881 ? mips_opts.warn_about_macros
4883 offset_expr.X_add_symbol, 0, NULL);
4886 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
4889 macro_build (p, &icnt, &expr1,
4890 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4891 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4892 /* FIXME: If breg == 0, and the next instruction uses
4893 $tempreg, then if this variant case is used an extra
4894 nop will be generated. */
4896 else if (expr1.X_add_number >= -0x8000
4897 && expr1.X_add_number < 0x8000)
4899 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4901 macro_build ((char *) NULL, &icnt, &expr1,
4902 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4903 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4904 frag_var (rs_machine_dependent, 0, 0,
4905 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4906 offset_expr.X_add_symbol, 0, NULL);
4912 /* If we are going to add in a base register, and the
4913 target register and the base register are the same,
4914 then we are using AT as a temporary register. Since
4915 we want to load the constant into AT, we add our
4916 current AT (from the global offset table) and the
4917 register into the register now, and pretend we were
4918 not using a base register. */
4923 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4925 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4926 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4927 "d,v,t", treg, AT, breg);
4933 /* Set mips_optimize around the lui instruction to avoid
4934 inserting an unnecessary nop after the lw. */
4935 hold_mips_optimize = mips_optimize;
4937 macro_build_lui (NULL, &icnt, &expr1, AT);
4938 mips_optimize = hold_mips_optimize;
4940 macro_build ((char *) NULL, &icnt, &expr1,
4941 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4942 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
4943 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4944 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4945 "d,v,t", tempreg, tempreg, AT);
4946 frag_var (rs_machine_dependent, 0, 0,
4947 RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0),
4948 offset_expr.X_add_symbol, 0, NULL);
4952 else if (mips_pic == SVR4_PIC)
4956 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
4957 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
4959 /* This is the large GOT case. If this is a reference to an
4960 external symbol, and there is no constant, we want
4961 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4962 addu $tempreg,$tempreg,$gp
4963 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4964 or if tempreg is PIC_CALL_REG
4965 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4966 addu $tempreg,$tempreg,$gp
4967 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
4968 For a local symbol, we want
4969 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4971 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4973 If we have a small constant, and this is a reference to
4974 an external symbol, we want
4975 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4976 addu $tempreg,$tempreg,$gp
4977 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4979 addiu $tempreg,$tempreg,<constant>
4980 For a local symbol, we want
4981 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4983 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4985 If we have a large constant, and this is a reference to
4986 an external symbol, we want
4987 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4988 addu $tempreg,$tempreg,$gp
4989 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4990 lui $at,<hiconstant>
4991 addiu $at,$at,<loconstant>
4992 addu $tempreg,$tempreg,$at
4993 For a local symbol, we want
4994 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4995 lui $at,<hiconstant>
4996 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4997 addu $tempreg,$tempreg,$at
4999 For NewABI, we want for data addresses
5000 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5001 If tempreg is PIC_CALL_REG pointing to a external symbol, we want
5002 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5006 int reloc_type = (tempreg == PIC_CALL_REG
5007 ? BFD_RELOC_MIPS_CALL16
5008 : BFD_RELOC_MIPS_GOT_DISP);
5010 macro_build ((char *) NULL, &icnt, &offset_expr,
5011 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5012 "t,o(b)", tempreg, reloc_type, mips_gp_register);
5015 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5016 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5017 "d,v,t", treg, tempreg, breg);
5024 expr1.X_add_number = offset_expr.X_add_number;
5025 offset_expr.X_add_number = 0;
5027 if (reg_needs_delay (mips_gp_register))
5031 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
5033 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5034 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5036 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
5037 tempreg, lui_reloc_type);
5038 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5039 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5040 "d,v,t", tempreg, tempreg, mips_gp_register);
5041 macro_build ((char *) NULL, &icnt, &offset_expr,
5042 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5043 "t,o(b)", tempreg, lw_reloc_type, tempreg);
5044 if (expr1.X_add_number == 0)
5052 /* We're going to put in an addu instruction using
5053 tempreg, so we may as well insert the nop right
5055 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5060 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5061 RELAX_ENCODE (12 + off, 12 + gpdel, gpdel,
5064 ? mips_opts.warn_about_macros
5066 offset_expr.X_add_symbol, 0, NULL);
5068 else if (expr1.X_add_number >= -0x8000
5069 && expr1.X_add_number < 0x8000)
5071 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5073 macro_build ((char *) NULL, &icnt, &expr1,
5074 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5075 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5077 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5078 RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0,
5080 ? mips_opts.warn_about_macros
5082 offset_expr.X_add_symbol, 0, NULL);
5088 /* If we are going to add in a base register, and the
5089 target register and the base register are the same,
5090 then we are using AT as a temporary register. Since
5091 we want to load the constant into AT, we add our
5092 current AT (from the global offset table) and the
5093 register into the register now, and pretend we were
5094 not using a base register. */
5102 assert (tempreg == AT);
5103 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5105 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5106 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5107 "d,v,t", treg, AT, breg);
5112 /* Set mips_optimize around the lui instruction to avoid
5113 inserting an unnecessary nop after the lw. */
5114 hold_mips_optimize = mips_optimize;
5116 macro_build_lui (NULL, &icnt, &expr1, AT);
5117 mips_optimize = hold_mips_optimize;
5119 macro_build ((char *) NULL, &icnt, &expr1,
5120 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5121 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
5122 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5123 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5124 "d,v,t", dreg, dreg, AT);
5126 p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0,
5127 RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel,
5130 ? mips_opts.warn_about_macros
5132 offset_expr.X_add_symbol, 0, NULL);
5139 /* This is needed because this instruction uses $gp, but
5140 the first instruction on the main stream does not. */
5141 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5144 macro_build (p, &icnt, &offset_expr,
5145 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5146 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16,
5149 if (expr1.X_add_number >= -0x8000
5150 && expr1.X_add_number < 0x8000)
5152 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5154 macro_build (p, &icnt, &expr1,
5155 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5156 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5157 /* FIXME: If add_number is 0, and there was no base
5158 register, the external symbol case ended with a load,
5159 so if the symbol turns out to not be external, and
5160 the next instruction uses tempreg, an unnecessary nop
5161 will be inserted. */
5167 /* We must add in the base register now, as in the
5168 external symbol case. */
5169 assert (tempreg == AT);
5170 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5172 macro_build (p, &icnt, (expressionS *) NULL,
5173 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5174 "d,v,t", treg, AT, breg);
5177 /* We set breg to 0 because we have arranged to add
5178 it in in both cases. */
5182 macro_build_lui (p, &icnt, &expr1, AT);
5184 macro_build (p, &icnt, &expr1,
5185 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5186 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
5188 macro_build (p, &icnt, (expressionS *) NULL,
5189 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5190 "d,v,t", tempreg, tempreg, AT);
5194 else if (mips_pic == EMBEDDED_PIC)
5197 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5199 macro_build ((char *) NULL, &icnt, &offset_expr,
5200 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j",
5201 tempreg, mips_gp_register, (int) BFD_RELOC_GPREL16);
5210 if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
5211 s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu";
5213 s = HAVE_64BIT_ADDRESSES ? "daddu" : "addu";
5215 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s,
5216 "d,v,t", treg, tempreg, breg);
5225 /* The j instruction may not be used in PIC code, since it
5226 requires an absolute address. We convert it to a b
5228 if (mips_pic == NO_PIC)
5229 macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a");
5231 macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p");
5234 /* The jal instructions must be handled as macros because when
5235 generating PIC code they expand to multi-instruction
5236 sequences. Normally they are simple instructions. */
5241 if (mips_pic == NO_PIC
5242 || mips_pic == EMBEDDED_PIC)
5243 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr",
5245 else if (mips_pic == SVR4_PIC)
5247 if (sreg != PIC_CALL_REG)
5248 as_warn (_("MIPS PIC call to register other than $25"));
5250 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr",
5254 if (mips_cprestore_offset < 0)
5255 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5258 if (! mips_frame_reg_valid)
5260 as_warn (_("No .frame pseudo-op used in PIC code"));
5261 /* Quiet this warning. */
5262 mips_frame_reg_valid = 1;
5264 if (! mips_cprestore_valid)
5266 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5267 /* Quiet this warning. */
5268 mips_cprestore_valid = 1;
5270 expr1.X_add_number = mips_cprestore_offset;
5271 macro_build ((char *) NULL, &icnt, &expr1,
5272 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)",
5273 mips_gp_register, (int) BFD_RELOC_LO16,
5284 if (mips_pic == NO_PIC)
5285 macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a");
5286 else if (mips_pic == SVR4_PIC)
5290 /* If this is a reference to an external symbol, and we are
5291 using a small GOT, we want
5292 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5296 lw $gp,cprestore($sp)
5297 The cprestore value is set using the .cprestore
5298 pseudo-op. If we are using a big GOT, we want
5299 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5301 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5305 lw $gp,cprestore($sp)
5306 If the symbol is not external, we want
5307 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5309 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5312 lw $gp,cprestore($sp)
5314 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5315 jalr $ra,$25 (BFD_RELOC_MIPS_JALR)
5319 macro_build ((char *) NULL, &icnt, &offset_expr,
5320 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5321 "t,o(b)", PIC_CALL_REG,
5322 (int) BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5323 macro_build_jalr (icnt, &offset_expr);
5330 macro_build ((char *) NULL, &icnt, &offset_expr,
5331 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5332 "t,o(b)", PIC_CALL_REG,
5333 (int) BFD_RELOC_MIPS_CALL16, mips_gp_register);
5334 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5336 p = frag_var (rs_machine_dependent, 4, 0,
5337 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5338 offset_expr.X_add_symbol, 0, NULL);
5344 if (reg_needs_delay (mips_gp_register))
5348 macro_build ((char *) NULL, &icnt, &offset_expr, "lui",
5349 "t,u", PIC_CALL_REG,
5350 (int) BFD_RELOC_MIPS_CALL_HI16);
5351 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5352 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5353 "d,v,t", PIC_CALL_REG, PIC_CALL_REG,
5355 macro_build ((char *) NULL, &icnt, &offset_expr,
5356 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5357 "t,o(b)", PIC_CALL_REG,
5358 (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
5359 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5361 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5362 RELAX_ENCODE (16, 12 + gpdel, gpdel,
5364 offset_expr.X_add_symbol, 0, NULL);
5367 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5370 macro_build (p, &icnt, &offset_expr,
5371 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5372 "t,o(b)", PIC_CALL_REG,
5373 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
5375 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5378 macro_build (p, &icnt, &offset_expr,
5379 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5380 "t,r,j", PIC_CALL_REG, PIC_CALL_REG,
5381 (int) BFD_RELOC_LO16);
5382 macro_build_jalr (icnt, &offset_expr);
5384 if (mips_cprestore_offset < 0)
5385 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5388 if (! mips_frame_reg_valid)
5390 as_warn (_("No .frame pseudo-op used in PIC code"));
5391 /* Quiet this warning. */
5392 mips_frame_reg_valid = 1;
5394 if (! mips_cprestore_valid)
5396 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5397 /* Quiet this warning. */
5398 mips_cprestore_valid = 1;
5400 if (mips_opts.noreorder)
5401 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5403 expr1.X_add_number = mips_cprestore_offset;
5404 macro_build ((char *) NULL, &icnt, &expr1,
5405 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)",
5406 mips_gp_register, (int) BFD_RELOC_LO16,
5411 else if (mips_pic == EMBEDDED_PIC)
5413 macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p");
5414 /* The linker may expand the call to a longer sequence which
5415 uses $at, so we must break rather than return. */
5440 /* Itbl support may require additional care here. */
5445 /* Itbl support may require additional care here. */
5450 /* Itbl support may require additional care here. */
5455 /* Itbl support may require additional care here. */
5467 if (mips_arch == CPU_R4650)
5469 as_bad (_("opcode not supported on this processor"));
5473 /* Itbl support may require additional care here. */
5478 /* Itbl support may require additional care here. */
5483 /* Itbl support may require additional care here. */
5503 if (breg == treg || coproc || lr)
5525 /* Itbl support may require additional care here. */
5530 /* Itbl support may require additional care here. */
5535 /* Itbl support may require additional care here. */
5540 /* Itbl support may require additional care here. */
5556 if (mips_arch == CPU_R4650)
5558 as_bad (_("opcode not supported on this processor"));
5563 /* Itbl support may require additional care here. */
5567 /* Itbl support may require additional care here. */
5572 /* Itbl support may require additional care here. */
5584 /* Itbl support may require additional care here. */
5585 if (mask == M_LWC1_AB
5586 || mask == M_SWC1_AB
5587 || mask == M_LDC1_AB
5588 || mask == M_SDC1_AB
5597 /* For embedded PIC, we allow loads where the offset is calculated
5598 by subtracting a symbol in the current segment from an unknown
5599 symbol, relative to a base register, e.g.:
5600 <op> $treg, <sym>-<localsym>($breg)
5601 This is used by the compiler for switch statements. */
5602 if (mips_pic == EMBEDDED_PIC
5603 && offset_expr.X_op == O_subtract
5604 && (symbol_constant_p (offset_expr.X_op_symbol)
5605 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
5606 : (symbol_equated_p (offset_expr.X_op_symbol)
5608 (symbol_get_value_expression (offset_expr.X_op_symbol)
5612 && (offset_expr.X_add_number == 0
5613 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
5615 /* For this case, we output the instructions:
5616 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5617 addiu $tempreg,$tempreg,$breg
5618 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5619 If the relocation would fit entirely in 16 bits, it would be
5621 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5622 instead, but that seems quite difficult. */
5623 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
5624 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
5625 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5626 ((bfd_arch_bits_per_address (stdoutput) == 32
5627 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
5628 ? "addu" : "daddu"),
5629 "d,v,t", tempreg, tempreg, breg);
5630 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, treg,
5631 (int) BFD_RELOC_PCREL_LO16, tempreg);
5637 if (offset_expr.X_op != O_constant
5638 && offset_expr.X_op != O_symbol)
5640 as_bad (_("expression too complex"));
5641 offset_expr.X_op = O_constant;
5644 /* A constant expression in PIC code can be handled just as it
5645 is in non PIC code. */
5646 if (mips_pic == NO_PIC
5647 || offset_expr.X_op == O_constant)
5651 /* If this is a reference to a GP relative symbol, and there
5652 is no base register, we want
5653 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5654 Otherwise, if there is no base register, we want
5655 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5656 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5657 If we have a constant, we need two instructions anyhow,
5658 so we always use the latter form.
5660 If we have a base register, and this is a reference to a
5661 GP relative symbol, we want
5662 addu $tempreg,$breg,$gp
5663 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5665 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5666 addu $tempreg,$tempreg,$breg
5667 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5668 With a constant we always use the latter case.
5670 With 64bit address space and no base register and $at usable,
5672 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5673 lui $at,<sym> (BFD_RELOC_HI16_S)
5674 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5677 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5678 If we have a base register, we want
5679 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5680 lui $at,<sym> (BFD_RELOC_HI16_S)
5681 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5685 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5687 Without $at we can't generate the optimal path for superscalar
5688 processors here since this would require two temporary registers.
5689 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5690 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5692 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5694 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5695 If we have a base register, we want
5696 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5697 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5699 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5701 daddu $tempreg,$tempreg,$breg
5702 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5704 If we have 64-bit addresses, as an optimization, for
5705 addresses which are 32-bit constants (e.g. kseg0/kseg1
5706 addresses) we fall back to the 32-bit address generation
5707 mechanism since it is more efficient. This code should
5708 probably attempt to generate 64-bit constants more
5709 efficiently in general.
5711 if (HAVE_64BIT_ADDRESSES
5712 && !(offset_expr.X_op == O_constant
5713 && IS_SEXT_32BIT_NUM (offset_expr.X_add_number)))
5717 /* We don't do GP optimization for now because RELAX_ENCODE can't
5718 hold the data for such large chunks. */
5722 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5723 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
5724 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5725 AT, (int) BFD_RELOC_HI16_S);
5726 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5727 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
5729 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
5730 "d,v,t", AT, AT, breg);
5731 macro_build (p, &icnt, (expressionS *) NULL, "dsll32",
5732 "d,w,<", tempreg, tempreg, 0);
5733 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
5734 "d,v,t", tempreg, tempreg, AT);
5735 macro_build (p, &icnt, &offset_expr, s,
5736 fmt, treg, (int) BFD_RELOC_LO16, tempreg);
5741 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5742 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
5743 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5744 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
5745 macro_build (p, &icnt, (expressionS *) NULL, "dsll",
5746 "d,w,<", tempreg, tempreg, 16);
5747 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5748 tempreg, tempreg, (int) BFD_RELOC_HI16_S);
5749 macro_build (p, &icnt, (expressionS *) NULL, "dsll",
5750 "d,w,<", tempreg, tempreg, 16);
5752 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
5753 "d,v,t", tempreg, tempreg, breg);
5754 macro_build (p, &icnt, &offset_expr, s,
5755 fmt, treg, (int) BFD_RELOC_LO16, tempreg);
5763 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
5764 || nopic_need_relax (offset_expr.X_add_symbol, 1))
5769 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5770 treg, (int) BFD_RELOC_GPREL16,
5772 p = frag_var (rs_machine_dependent, 8, 0,
5773 RELAX_ENCODE (4, 8, 0, 4, 0,
5774 (mips_opts.warn_about_macros
5776 && mips_opts.noat))),
5777 offset_expr.X_add_symbol, 0, NULL);
5780 macro_build_lui (p, &icnt, &offset_expr, tempreg);
5783 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
5784 (int) BFD_RELOC_LO16, tempreg);
5788 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
5789 || nopic_need_relax (offset_expr.X_add_symbol, 1))
5794 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5795 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5796 "d,v,t", tempreg, breg, mips_gp_register);
5797 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5798 treg, (int) BFD_RELOC_GPREL16, tempreg);
5799 p = frag_var (rs_machine_dependent, 12, 0,
5800 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5801 offset_expr.X_add_symbol, 0, NULL);
5803 macro_build_lui (p, &icnt, &offset_expr, tempreg);
5806 macro_build (p, &icnt, (expressionS *) NULL,
5807 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5808 "d,v,t", tempreg, tempreg, breg);
5811 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
5812 (int) BFD_RELOC_LO16, tempreg);
5815 else if (mips_pic == SVR4_PIC && ! mips_big_got)
5819 /* If this is a reference to an external symbol, we want
5820 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5822 <op> $treg,0($tempreg)
5824 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5826 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5827 <op> $treg,0($tempreg)
5828 If there is a base register, we add it to $tempreg before
5829 the <op>. If there is a constant, we stick it in the
5830 <op> instruction. We don't handle constants larger than
5831 16 bits, because we have no way to load the upper 16 bits
5832 (actually, we could handle them for the subset of cases
5833 in which we are not using $at). */
5834 assert (offset_expr.X_op == O_symbol);
5835 expr1.X_add_number = offset_expr.X_add_number;
5836 offset_expr.X_add_number = 0;
5837 if (expr1.X_add_number < -0x8000
5838 || expr1.X_add_number >= 0x8000)
5839 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5841 macro_build ((char *) NULL, &icnt, &offset_expr,
5842 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", tempreg,
5843 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
5844 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
5845 p = frag_var (rs_machine_dependent, 4, 0,
5846 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5847 offset_expr.X_add_symbol, 0, NULL);
5848 macro_build (p, &icnt, &offset_expr,
5849 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5850 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5852 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5853 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5854 "d,v,t", tempreg, tempreg, breg);
5855 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
5856 (int) BFD_RELOC_LO16, tempreg);
5858 else if (mips_pic == SVR4_PIC)
5863 /* If this is a reference to an external symbol, we want
5864 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5865 addu $tempreg,$tempreg,$gp
5866 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5867 <op> $treg,0($tempreg)
5869 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5871 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5872 <op> $treg,0($tempreg)
5873 If there is a base register, we add it to $tempreg before
5874 the <op>. If there is a constant, we stick it in the
5875 <op> instruction. We don't handle constants larger than
5876 16 bits, because we have no way to load the upper 16 bits
5877 (actually, we could handle them for the subset of cases
5878 in which we are not using $at).
5881 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5882 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5883 <op> $treg,0($tempreg)
5885 assert (offset_expr.X_op == O_symbol);
5886 expr1.X_add_number = offset_expr.X_add_number;
5887 offset_expr.X_add_number = 0;
5888 if (expr1.X_add_number < -0x8000
5889 || expr1.X_add_number >= 0x8000)
5890 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5893 macro_build ((char *) NULL, &icnt, &offset_expr,
5894 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5895 "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_PAGE,
5897 macro_build ((char *) NULL, &icnt, &offset_expr,
5898 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5899 "t,r,j", tempreg, tempreg,
5900 BFD_RELOC_MIPS_GOT_OFST);
5902 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5903 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5904 "d,v,t", tempreg, tempreg, breg);
5905 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
5906 (int) BFD_RELOC_LO16, tempreg);
5913 if (reg_needs_delay (mips_gp_register))
5918 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
5919 tempreg, (int) BFD_RELOC_MIPS_GOT_HI16);
5920 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5921 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5922 "d,v,t", tempreg, tempreg, mips_gp_register);
5923 macro_build ((char *) NULL, &icnt, &offset_expr,
5924 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5925 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16,
5927 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5928 RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0),
5929 offset_expr.X_add_symbol, 0, NULL);
5932 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5935 macro_build (p, &icnt, &offset_expr,
5936 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5937 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16,
5940 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5942 macro_build (p, &icnt, &offset_expr,
5943 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5944 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5946 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5947 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5948 "d,v,t", tempreg, tempreg, breg);
5949 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
5950 (int) BFD_RELOC_LO16, tempreg);
5952 else if (mips_pic == EMBEDDED_PIC)
5954 /* If there is no base register, we want
5955 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5956 If there is a base register, we want
5957 addu $tempreg,$breg,$gp
5958 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5960 assert (offset_expr.X_op == O_symbol);
5963 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5964 treg, (int) BFD_RELOC_GPREL16, mips_gp_register);
5969 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5970 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5971 "d,v,t", tempreg, breg, mips_gp_register);
5972 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5973 treg, (int) BFD_RELOC_GPREL16, tempreg);
5986 load_register (&icnt, treg, &imm_expr, 0);
5990 load_register (&icnt, treg, &imm_expr, 1);
5994 if (imm_expr.X_op == O_constant)
5996 load_register (&icnt, AT, &imm_expr, 0);
5997 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5998 "mtc1", "t,G", AT, treg);
6003 assert (offset_expr.X_op == O_symbol
6004 && strcmp (segment_name (S_GET_SEGMENT
6005 (offset_expr.X_add_symbol)),
6007 && offset_expr.X_add_number == 0);
6008 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
6009 treg, (int) BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6014 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6015 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6016 order 32 bits of the value and the low order 32 bits are either
6017 zero or in OFFSET_EXPR. */
6018 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6020 if (HAVE_64BIT_GPRS)
6021 load_register (&icnt, treg, &imm_expr, 1);
6026 if (target_big_endian)
6038 load_register (&icnt, hreg, &imm_expr, 0);
6041 if (offset_expr.X_op == O_absent)
6042 move_register (&icnt, lreg, 0);
6045 assert (offset_expr.X_op == O_constant);
6046 load_register (&icnt, lreg, &offset_expr, 0);
6053 /* We know that sym is in the .rdata section. First we get the
6054 upper 16 bits of the address. */
6055 if (mips_pic == NO_PIC)
6057 macro_build_lui (NULL, &icnt, &offset_expr, AT);
6059 else if (mips_pic == SVR4_PIC)
6061 macro_build ((char *) NULL, &icnt, &offset_expr,
6062 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6063 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
6066 else if (mips_pic == EMBEDDED_PIC)
6068 /* For embedded PIC we pick up the entire address off $gp in
6069 a single instruction. */
6070 macro_build ((char *) NULL, &icnt, &offset_expr,
6071 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j", AT,
6072 mips_gp_register, (int) BFD_RELOC_GPREL16);
6073 offset_expr.X_op = O_constant;
6074 offset_expr.X_add_number = 0;
6079 /* Now we load the register(s). */
6080 if (HAVE_64BIT_GPRS)
6081 macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)",
6082 treg, (int) BFD_RELOC_LO16, AT);
6085 macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)",
6086 treg, (int) BFD_RELOC_LO16, AT);
6089 /* FIXME: How in the world do we deal with the possible
6091 offset_expr.X_add_number += 4;
6092 macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)",
6093 treg + 1, (int) BFD_RELOC_LO16, AT);
6097 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6098 does not become a variant frag. */
6099 frag_wane (frag_now);
6105 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6106 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6107 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6108 the value and the low order 32 bits are either zero or in
6110 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6112 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS);
6113 if (HAVE_64BIT_FPRS)
6115 assert (HAVE_64BIT_GPRS);
6116 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6117 "dmtc1", "t,S", AT, treg);
6121 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6122 "mtc1", "t,G", AT, treg + 1);
6123 if (offset_expr.X_op == O_absent)
6124 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6125 "mtc1", "t,G", 0, treg);
6128 assert (offset_expr.X_op == O_constant);
6129 load_register (&icnt, AT, &offset_expr, 0);
6130 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6131 "mtc1", "t,G", AT, treg);
6137 assert (offset_expr.X_op == O_symbol
6138 && offset_expr.X_add_number == 0);
6139 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
6140 if (strcmp (s, ".lit8") == 0)
6142 if (mips_opts.isa != ISA_MIPS1)
6144 macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
6145 "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL,
6149 breg = mips_gp_register;
6150 r = BFD_RELOC_MIPS_LITERAL;
6155 assert (strcmp (s, RDATA_SECTION_NAME) == 0);
6156 if (mips_pic == SVR4_PIC)
6157 macro_build ((char *) NULL, &icnt, &offset_expr,
6158 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6159 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
6163 /* FIXME: This won't work for a 64 bit address. */
6164 macro_build_lui (NULL, &icnt, &offset_expr, AT);
6167 if (mips_opts.isa != ISA_MIPS1)
6169 macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
6170 "T,o(b)", treg, (int) BFD_RELOC_LO16, AT);
6172 /* To avoid confusion in tc_gen_reloc, we must ensure
6173 that this does not become a variant frag. */
6174 frag_wane (frag_now);
6185 if (mips_arch == CPU_R4650)
6187 as_bad (_("opcode not supported on this processor"));
6190 /* Even on a big endian machine $fn comes before $fn+1. We have
6191 to adjust when loading from memory. */
6194 assert (mips_opts.isa == ISA_MIPS1);
6195 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
6196 target_big_endian ? treg + 1 : treg,
6198 /* FIXME: A possible overflow which I don't know how to deal
6200 offset_expr.X_add_number += 4;
6201 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
6202 target_big_endian ? treg : treg + 1,
6205 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6206 does not become a variant frag. */
6207 frag_wane (frag_now);
6216 * The MIPS assembler seems to check for X_add_number not
6217 * being double aligned and generating:
6220 * addiu at,at,%lo(foo+1)
6223 * But, the resulting address is the same after relocation so why
6224 * generate the extra instruction?
6226 if (mips_arch == CPU_R4650)
6228 as_bad (_("opcode not supported on this processor"));
6231 /* Itbl support may require additional care here. */
6233 if (mips_opts.isa != ISA_MIPS1)
6244 if (mips_arch == CPU_R4650)
6246 as_bad (_("opcode not supported on this processor"));
6250 if (mips_opts.isa != ISA_MIPS1)
6258 /* Itbl support may require additional care here. */
6263 if (HAVE_64BIT_GPRS)
6274 if (HAVE_64BIT_GPRS)
6284 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6285 loads for the case of doing a pair of loads to simulate an 'ld'.
6286 This is not currently done by the compiler, and assembly coders
6287 writing embedded-pic code can cope. */
6289 if (offset_expr.X_op != O_symbol
6290 && offset_expr.X_op != O_constant)
6292 as_bad (_("expression too complex"));
6293 offset_expr.X_op = O_constant;
6296 /* Even on a big endian machine $fn comes before $fn+1. We have
6297 to adjust when loading from memory. We set coproc if we must
6298 load $fn+1 first. */
6299 /* Itbl support may require additional care here. */
6300 if (! target_big_endian)
6303 if (mips_pic == NO_PIC
6304 || offset_expr.X_op == O_constant)
6308 /* If this is a reference to a GP relative symbol, we want
6309 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6310 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6311 If we have a base register, we use this
6313 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6314 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6315 If this is not a GP relative symbol, we want
6316 lui $at,<sym> (BFD_RELOC_HI16_S)
6317 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6318 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6319 If there is a base register, we add it to $at after the
6320 lui instruction. If there is a constant, we always use
6322 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6323 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6335 tempreg = mips_gp_register;
6342 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6343 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6344 "d,v,t", AT, breg, mips_gp_register);
6350 /* Itbl support may require additional care here. */
6351 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6352 coproc ? treg + 1 : treg,
6353 (int) BFD_RELOC_GPREL16, tempreg);
6354 offset_expr.X_add_number += 4;
6356 /* Set mips_optimize to 2 to avoid inserting an
6358 hold_mips_optimize = mips_optimize;
6360 /* Itbl support may require additional care here. */
6361 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6362 coproc ? treg : treg + 1,
6363 (int) BFD_RELOC_GPREL16, tempreg);
6364 mips_optimize = hold_mips_optimize;
6366 p = frag_var (rs_machine_dependent, 12 + off, 0,
6367 RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1,
6368 used_at && mips_opts.noat),
6369 offset_expr.X_add_symbol, 0, NULL);
6371 /* We just generated two relocs. When tc_gen_reloc
6372 handles this case, it will skip the first reloc and
6373 handle the second. The second reloc already has an
6374 extra addend of 4, which we added above. We must
6375 subtract it out, and then subtract another 4 to make
6376 the first reloc come out right. The second reloc
6377 will come out right because we are going to add 4 to
6378 offset_expr when we build its instruction below.
6380 If we have a symbol, then we don't want to include
6381 the offset, because it will wind up being included
6382 when we generate the reloc. */
6384 if (offset_expr.X_op == O_constant)
6385 offset_expr.X_add_number -= 8;
6388 offset_expr.X_add_number = -4;
6389 offset_expr.X_op = O_constant;
6392 macro_build_lui (p, &icnt, &offset_expr, AT);
6397 macro_build (p, &icnt, (expressionS *) NULL,
6398 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6399 "d,v,t", AT, breg, AT);
6403 /* Itbl support may require additional care here. */
6404 macro_build (p, &icnt, &offset_expr, s, fmt,
6405 coproc ? treg + 1 : treg,
6406 (int) BFD_RELOC_LO16, AT);
6409 /* FIXME: How do we handle overflow here? */
6410 offset_expr.X_add_number += 4;
6411 /* Itbl support may require additional care here. */
6412 macro_build (p, &icnt, &offset_expr, s, fmt,
6413 coproc ? treg : treg + 1,
6414 (int) BFD_RELOC_LO16, AT);
6416 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6420 /* If this is a reference to an external symbol, we want
6421 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6426 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6428 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6429 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6430 If there is a base register we add it to $at before the
6431 lwc1 instructions. If there is a constant we include it
6432 in the lwc1 instructions. */
6434 expr1.X_add_number = offset_expr.X_add_number;
6435 offset_expr.X_add_number = 0;
6436 if (expr1.X_add_number < -0x8000
6437 || expr1.X_add_number >= 0x8000 - 4)
6438 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6443 frag_grow (24 + off);
6444 macro_build ((char *) NULL, &icnt, &offset_expr,
6445 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", AT,
6446 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
6447 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
6449 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6450 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6451 "d,v,t", AT, breg, AT);
6452 /* Itbl support may require additional care here. */
6453 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6454 coproc ? treg + 1 : treg,
6455 (int) BFD_RELOC_LO16, AT);
6456 expr1.X_add_number += 4;
6458 /* Set mips_optimize to 2 to avoid inserting an undesired
6460 hold_mips_optimize = mips_optimize;
6462 /* Itbl support may require additional care here. */
6463 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6464 coproc ? treg : treg + 1,
6465 (int) BFD_RELOC_LO16, AT);
6466 mips_optimize = hold_mips_optimize;
6468 (void) frag_var (rs_machine_dependent, 0, 0,
6469 RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0),
6470 offset_expr.X_add_symbol, 0, NULL);
6472 else if (mips_pic == SVR4_PIC)
6477 /* If this is a reference to an external symbol, we want
6478 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6480 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6485 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6487 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6488 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6489 If there is a base register we add it to $at before the
6490 lwc1 instructions. If there is a constant we include it
6491 in the lwc1 instructions. */
6493 expr1.X_add_number = offset_expr.X_add_number;
6494 offset_expr.X_add_number = 0;
6495 if (expr1.X_add_number < -0x8000
6496 || expr1.X_add_number >= 0x8000 - 4)
6497 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6498 if (reg_needs_delay (mips_gp_register))
6507 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
6508 AT, (int) BFD_RELOC_MIPS_GOT_HI16);
6509 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6510 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6511 "d,v,t", AT, AT, mips_gp_register);
6512 macro_build ((char *) NULL, &icnt, &offset_expr,
6513 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6514 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT);
6515 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
6517 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6518 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6519 "d,v,t", AT, breg, AT);
6520 /* Itbl support may require additional care here. */
6521 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6522 coproc ? treg + 1 : treg,
6523 (int) BFD_RELOC_LO16, AT);
6524 expr1.X_add_number += 4;
6526 /* Set mips_optimize to 2 to avoid inserting an undesired
6528 hold_mips_optimize = mips_optimize;
6530 /* Itbl support may require additional care here. */
6531 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6532 coproc ? treg : treg + 1,
6533 (int) BFD_RELOC_LO16, AT);
6534 mips_optimize = hold_mips_optimize;
6535 expr1.X_add_number -= 4;
6537 p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0,
6538 RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel,
6539 8 + gpdel + off, 1, 0),
6540 offset_expr.X_add_symbol, 0, NULL);
6543 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
6546 macro_build (p, &icnt, &offset_expr,
6547 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6548 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
6551 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
6555 macro_build (p, &icnt, (expressionS *) NULL,
6556 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6557 "d,v,t", AT, breg, AT);
6560 /* Itbl support may require additional care here. */
6561 macro_build (p, &icnt, &expr1, s, fmt,
6562 coproc ? treg + 1 : treg,
6563 (int) BFD_RELOC_LO16, AT);
6565 expr1.X_add_number += 4;
6567 /* Set mips_optimize to 2 to avoid inserting an undesired
6569 hold_mips_optimize = mips_optimize;
6571 /* Itbl support may require additional care here. */
6572 macro_build (p, &icnt, &expr1, s, fmt,
6573 coproc ? treg : treg + 1,
6574 (int) BFD_RELOC_LO16, AT);
6575 mips_optimize = hold_mips_optimize;
6577 else if (mips_pic == EMBEDDED_PIC)
6579 /* If there is no base register, we use
6580 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6581 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6582 If we have a base register, we use
6584 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6585 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6589 tempreg = mips_gp_register;
6594 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6595 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6596 "d,v,t", AT, breg, mips_gp_register);
6601 /* Itbl support may require additional care here. */
6602 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6603 coproc ? treg + 1 : treg,
6604 (int) BFD_RELOC_GPREL16, tempreg);
6605 offset_expr.X_add_number += 4;
6606 /* Itbl support may require additional care here. */
6607 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6608 coproc ? treg : treg + 1,
6609 (int) BFD_RELOC_GPREL16, tempreg);
6625 assert (HAVE_32BIT_ADDRESSES);
6626 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
6627 (int) BFD_RELOC_LO16, breg);
6628 offset_expr.X_add_number += 4;
6629 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1,
6630 (int) BFD_RELOC_LO16, breg);
6633 /* New code added to support COPZ instructions.
6634 This code builds table entries out of the macros in mip_opcodes.
6635 R4000 uses interlocks to handle coproc delays.
6636 Other chips (like the R3000) require nops to be inserted for delays.
6638 FIXME: Currently, we require that the user handle delays.
6639 In order to fill delay slots for non-interlocked chips,
6640 we must have a way to specify delays based on the coprocessor.
6641 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6642 What are the side-effects of the cop instruction?
6643 What cache support might we have and what are its effects?
6644 Both coprocessor & memory require delays. how long???
6645 What registers are read/set/modified?
6647 If an itbl is provided to interpret cop instructions,
6648 this knowledge can be encoded in the itbl spec. */
6662 /* For now we just do C (same as Cz). The parameter will be
6663 stored in insn_opcode by mips_ip. */
6664 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "C",
6669 move_register (&icnt, dreg, sreg);
6672 #ifdef LOSING_COMPILER
6674 /* Try and see if this is a new itbl instruction.
6675 This code builds table entries out of the macros in mip_opcodes.
6676 FIXME: For now we just assemble the expression and pass it's
6677 value along as a 32-bit immediate.
6678 We may want to have the assembler assemble this value,
6679 so that we gain the assembler's knowledge of delay slots,
6681 Would it be more efficient to use mask (id) here? */
6682 if (itbl_have_entries
6683 && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
6685 s = ip->insn_mo->name;
6687 coproc = ITBL_DECODE_PNUM (immed_expr);;
6688 macro_build ((char *) NULL, &icnt, &immed_expr, s, "C");
6695 as_warn (_("Macro used $at after \".set noat\""));
6700 struct mips_cl_insn *ip;
6702 register int treg, sreg, dreg, breg;
6718 bfd_reloc_code_real_type r;
6721 treg = (ip->insn_opcode >> 16) & 0x1f;
6722 dreg = (ip->insn_opcode >> 11) & 0x1f;
6723 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
6724 mask = ip->insn_mo->mask;
6726 expr1.X_op = O_constant;
6727 expr1.X_op_symbol = NULL;
6728 expr1.X_add_symbol = NULL;
6729 expr1.X_add_number = 1;
6733 #endif /* LOSING_COMPILER */
6738 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6739 dbl ? "dmultu" : "multu", "s,t", sreg, treg);
6740 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6747 /* The MIPS assembler some times generates shifts and adds. I'm
6748 not trying to be that fancy. GCC should do this for us
6750 load_register (&icnt, AT, &imm_expr, dbl);
6751 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6752 dbl ? "dmult" : "mult", "s,t", sreg, AT);
6753 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6767 mips_emit_delays (true);
6768 ++mips_opts.noreorder;
6769 mips_any_noreorder = 1;
6771 load_register (&icnt, AT, &imm_expr, dbl);
6772 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6773 dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
6774 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6776 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6777 dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
6778 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d",
6781 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne", "s,t",
6785 expr1.X_add_number = 8;
6786 macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg,
6788 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
6790 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
6793 --mips_opts.noreorder;
6794 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", dreg);
6807 mips_emit_delays (true);
6808 ++mips_opts.noreorder;
6809 mips_any_noreorder = 1;
6811 load_register (&icnt, AT, &imm_expr, dbl);
6812 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6813 dbl ? "dmultu" : "multu",
6814 "s,t", sreg, imm ? AT : treg);
6815 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d",
6817 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6820 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne", "s,t",
6824 expr1.X_add_number = 8;
6825 macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0);
6826 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
6828 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
6831 --mips_opts.noreorder;
6835 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
6836 "d,v,t", AT, 0, treg);
6837 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
6838 "d,t,s", AT, sreg, AT);
6839 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
6840 "d,t,s", dreg, sreg, treg);
6841 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6842 "d,v,t", dreg, dreg, AT);
6846 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
6847 "d,v,t", AT, 0, treg);
6848 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv",
6849 "d,t,s", AT, sreg, AT);
6850 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv",
6851 "d,t,s", dreg, sreg, treg);
6852 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6853 "d,v,t", dreg, dreg, AT);
6861 if (imm_expr.X_op != O_constant)
6862 as_bad (_("rotate count too large"));
6863 rot = imm_expr.X_add_number & 0x3f;
6866 l = (rot < 0x20) ? "dsll" : "dsll32";
6867 r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
6869 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
6870 "d,w,<", AT, sreg, rot);
6871 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
6872 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6873 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6874 "d,v,t", dreg, dreg, AT);
6882 if (imm_expr.X_op != O_constant)
6883 as_bad (_("rotate count too large"));
6884 rot = imm_expr.X_add_number & 0x1f;
6887 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
6888 "d,w,<", AT, sreg, rot);
6889 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
6890 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6891 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6892 "d,v,t", dreg, dreg, AT);
6897 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
6898 "d,v,t", AT, 0, treg);
6899 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
6900 "d,t,s", AT, sreg, AT);
6901 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
6902 "d,t,s", dreg, sreg, treg);
6903 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6904 "d,v,t", dreg, dreg, AT);
6908 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
6909 "d,v,t", AT, 0, treg);
6910 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv",
6911 "d,t,s", AT, sreg, AT);
6912 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv",
6913 "d,t,s", dreg, sreg, treg);
6914 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6915 "d,v,t", dreg, dreg, AT);
6923 if (imm_expr.X_op != O_constant)
6924 as_bad (_("rotate count too large"));
6925 rot = imm_expr.X_add_number & 0x3f;
6928 r = (rot < 0x20) ? "dsrl" : "dsrl32";
6929 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
6931 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
6932 "d,w,<", AT, sreg, rot);
6933 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
6934 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6935 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6936 "d,v,t", dreg, dreg, AT);
6944 if (imm_expr.X_op != O_constant)
6945 as_bad (_("rotate count too large"));
6946 rot = imm_expr.X_add_number & 0x1f;
6949 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
6950 "d,w,<", AT, sreg, rot);
6951 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
6952 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6953 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6954 "d,v,t", dreg, dreg, AT);
6959 if (mips_arch == CPU_R4650)
6961 as_bad (_("opcode not supported on this processor"));
6964 assert (mips_opts.isa == ISA_MIPS1);
6965 /* Even on a big endian machine $fn comes before $fn+1. We have
6966 to adjust when storing to memory. */
6967 macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
6968 target_big_endian ? treg + 1 : treg,
6969 (int) BFD_RELOC_LO16, breg);
6970 offset_expr.X_add_number += 4;
6971 macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
6972 target_big_endian ? treg : treg + 1,
6973 (int) BFD_RELOC_LO16, breg);
6978 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6979 treg, (int) BFD_RELOC_LO16);
6981 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6982 sreg, (int) BFD_RELOC_LO16);
6985 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
6986 "d,v,t", dreg, sreg, treg);
6987 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6988 dreg, (int) BFD_RELOC_LO16);
6993 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6995 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6996 sreg, (int) BFD_RELOC_LO16);
7001 as_warn (_("Instruction %s: result is always false"),
7003 move_register (&icnt, dreg, 0);
7006 if (imm_expr.X_op == O_constant
7007 && imm_expr.X_add_number >= 0
7008 && imm_expr.X_add_number < 0x10000)
7010 macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg,
7011 sreg, (int) BFD_RELOC_LO16);
7014 else if (imm_expr.X_op == O_constant
7015 && imm_expr.X_add_number > -0x8000
7016 && imm_expr.X_add_number < 0)
7018 imm_expr.X_add_number = -imm_expr.X_add_number;
7019 macro_build ((char *) NULL, &icnt, &imm_expr,
7020 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7021 "t,r,j", dreg, sreg,
7022 (int) BFD_RELOC_LO16);
7027 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7028 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
7029 "d,v,t", dreg, sreg, AT);
7032 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg,
7033 (int) BFD_RELOC_LO16);
7038 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
7044 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
7046 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7047 (int) BFD_RELOC_LO16);
7050 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
7052 if (imm_expr.X_op == O_constant
7053 && imm_expr.X_add_number >= -0x8000
7054 && imm_expr.X_add_number < 0x8000)
7056 macro_build ((char *) NULL, &icnt, &imm_expr,
7057 mask == M_SGE_I ? "slti" : "sltiu",
7058 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
7063 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7064 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7065 mask == M_SGE_I ? "slt" : "sltu", "d,v,t", dreg, sreg,
7069 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7070 (int) BFD_RELOC_LO16);
7075 case M_SGT: /* sreg > treg <==> treg < sreg */
7081 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
7085 case M_SGT_I: /* sreg > I <==> I < sreg */
7091 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7092 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
7096 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7102 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
7104 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7105 (int) BFD_RELOC_LO16);
7108 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7114 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7115 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
7117 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7118 (int) BFD_RELOC_LO16);
7122 if (imm_expr.X_op == O_constant
7123 && imm_expr.X_add_number >= -0x8000
7124 && imm_expr.X_add_number < 0x8000)
7126 macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j",
7127 dreg, sreg, (int) BFD_RELOC_LO16);
7130 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7131 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
7136 if (imm_expr.X_op == O_constant
7137 && imm_expr.X_add_number >= -0x8000
7138 && imm_expr.X_add_number < 0x8000)
7140 macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j",
7141 dreg, sreg, (int) BFD_RELOC_LO16);
7144 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7145 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
7146 "d,v,t", dreg, sreg, AT);
7151 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
7152 "d,v,t", dreg, 0, treg);
7154 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
7155 "d,v,t", dreg, 0, sreg);
7158 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
7159 "d,v,t", dreg, sreg, treg);
7160 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
7161 "d,v,t", dreg, 0, dreg);
7166 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7168 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
7169 "d,v,t", dreg, 0, sreg);
7174 as_warn (_("Instruction %s: result is always true"),
7176 macro_build ((char *) NULL, &icnt, &expr1,
7177 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7178 "t,r,j", dreg, 0, (int) BFD_RELOC_LO16);
7181 if (imm_expr.X_op == O_constant
7182 && imm_expr.X_add_number >= 0
7183 && imm_expr.X_add_number < 0x10000)
7185 macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i",
7186 dreg, sreg, (int) BFD_RELOC_LO16);
7189 else if (imm_expr.X_op == O_constant
7190 && imm_expr.X_add_number > -0x8000
7191 && imm_expr.X_add_number < 0)
7193 imm_expr.X_add_number = -imm_expr.X_add_number;
7194 macro_build ((char *) NULL, &icnt, &imm_expr,
7195 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7196 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
7201 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7202 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
7203 "d,v,t", dreg, sreg, AT);
7206 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
7207 "d,v,t", dreg, 0, dreg);
7215 if (imm_expr.X_op == O_constant
7216 && imm_expr.X_add_number > -0x8000
7217 && imm_expr.X_add_number <= 0x8000)
7219 imm_expr.X_add_number = -imm_expr.X_add_number;
7220 macro_build ((char *) NULL, &icnt, &imm_expr,
7221 dbl ? "daddi" : "addi",
7222 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
7225 load_register (&icnt, AT, &imm_expr, dbl);
7226 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7227 dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
7233 if (imm_expr.X_op == O_constant
7234 && imm_expr.X_add_number > -0x8000
7235 && imm_expr.X_add_number <= 0x8000)
7237 imm_expr.X_add_number = -imm_expr.X_add_number;
7238 macro_build ((char *) NULL, &icnt, &imm_expr,
7239 dbl ? "daddiu" : "addiu",
7240 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
7243 load_register (&icnt, AT, &imm_expr, dbl);
7244 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7245 dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
7266 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7267 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "s,t", sreg,
7273 assert (mips_opts.isa == ISA_MIPS1);
7274 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
7275 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
7278 * Is the double cfc1 instruction a bug in the mips assembler;
7279 * or is there a reason for it?
7281 mips_emit_delays (true);
7282 ++mips_opts.noreorder;
7283 mips_any_noreorder = 1;
7284 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G",
7286 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G",
7288 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7289 expr1.X_add_number = 3;
7290 macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg,
7291 (int) BFD_RELOC_LO16);
7292 expr1.X_add_number = 2;
7293 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT,
7294 (int) BFD_RELOC_LO16);
7295 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G",
7297 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7298 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7299 mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg);
7300 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G",
7302 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7303 --mips_opts.noreorder;
7312 if (offset_expr.X_add_number >= 0x7fff)
7313 as_bad (_("operand overflow"));
7314 /* avoid load delay */
7315 if (! target_big_endian)
7316 ++offset_expr.X_add_number;
7317 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7318 (int) BFD_RELOC_LO16, breg);
7319 if (! target_big_endian)
7320 --offset_expr.X_add_number;
7322 ++offset_expr.X_add_number;
7323 macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT,
7324 (int) BFD_RELOC_LO16, breg);
7325 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7327 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7341 if (offset_expr.X_add_number >= 0x8000 - off)
7342 as_bad (_("operand overflow"));
7343 if (! target_big_endian)
7344 offset_expr.X_add_number += off;
7345 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7346 (int) BFD_RELOC_LO16, breg);
7347 if (! target_big_endian)
7348 offset_expr.X_add_number -= off;
7350 offset_expr.X_add_number += off;
7351 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
7352 (int) BFD_RELOC_LO16, breg);
7366 load_address (&icnt, AT, &offset_expr, &used_at);
7368 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7369 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7370 "d,v,t", AT, AT, breg);
7371 if (! target_big_endian)
7372 expr1.X_add_number = off;
7374 expr1.X_add_number = 0;
7375 macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg,
7376 (int) BFD_RELOC_LO16, AT);
7377 if (! target_big_endian)
7378 expr1.X_add_number = 0;
7380 expr1.X_add_number = off;
7381 macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7382 (int) BFD_RELOC_LO16, AT);
7388 load_address (&icnt, AT, &offset_expr, &used_at);
7390 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7391 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7392 "d,v,t", AT, AT, breg);
7393 if (target_big_endian)
7394 expr1.X_add_number = 0;
7395 macro_build ((char *) NULL, &icnt, &expr1,
7396 mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg,
7397 (int) BFD_RELOC_LO16, AT);
7398 if (target_big_endian)
7399 expr1.X_add_number = 1;
7401 expr1.X_add_number = 0;
7402 macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
7403 (int) BFD_RELOC_LO16, AT);
7404 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7406 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7411 if (offset_expr.X_add_number >= 0x7fff)
7412 as_bad (_("operand overflow"));
7413 if (target_big_endian)
7414 ++offset_expr.X_add_number;
7415 macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg,
7416 (int) BFD_RELOC_LO16, breg);
7417 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
7419 if (target_big_endian)
7420 --offset_expr.X_add_number;
7422 ++offset_expr.X_add_number;
7423 macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT,
7424 (int) BFD_RELOC_LO16, breg);
7437 if (offset_expr.X_add_number >= 0x8000 - off)
7438 as_bad (_("operand overflow"));
7439 if (! target_big_endian)
7440 offset_expr.X_add_number += off;
7441 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7442 (int) BFD_RELOC_LO16, breg);
7443 if (! target_big_endian)
7444 offset_expr.X_add_number -= off;
7446 offset_expr.X_add_number += off;
7447 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
7448 (int) BFD_RELOC_LO16, breg);
7462 load_address (&icnt, AT, &offset_expr, &used_at);
7464 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7465 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7466 "d,v,t", AT, AT, breg);
7467 if (! target_big_endian)
7468 expr1.X_add_number = off;
7470 expr1.X_add_number = 0;
7471 macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg,
7472 (int) BFD_RELOC_LO16, AT);
7473 if (! target_big_endian)
7474 expr1.X_add_number = 0;
7476 expr1.X_add_number = off;
7477 macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7478 (int) BFD_RELOC_LO16, AT);
7483 load_address (&icnt, AT, &offset_expr, &used_at);
7485 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7486 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7487 "d,v,t", AT, AT, breg);
7488 if (! target_big_endian)
7489 expr1.X_add_number = 0;
7490 macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7491 (int) BFD_RELOC_LO16, AT);
7492 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
7494 if (! target_big_endian)
7495 expr1.X_add_number = 1;
7497 expr1.X_add_number = 0;
7498 macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7499 (int) BFD_RELOC_LO16, AT);
7500 if (! target_big_endian)
7501 expr1.X_add_number = 0;
7503 expr1.X_add_number = 1;
7504 macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
7505 (int) BFD_RELOC_LO16, AT);
7506 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7508 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7513 /* FIXME: Check if this is one of the itbl macros, since they
7514 are added dynamically. */
7515 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
7519 as_warn (_("Macro used $at after \".set noat\""));
7522 /* Implement macros in mips16 mode. */
7526 struct mips_cl_insn *ip;
7529 int xreg, yreg, zreg, tmp;
7533 const char *s, *s2, *s3;
7535 mask = ip->insn_mo->mask;
7537 xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
7538 yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY;
7539 zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
7543 expr1.X_op = O_constant;
7544 expr1.X_op_symbol = NULL;
7545 expr1.X_add_symbol = NULL;
7546 expr1.X_add_number = 1;
7565 mips_emit_delays (true);
7566 ++mips_opts.noreorder;
7567 mips_any_noreorder = 1;
7568 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7569 dbl ? "ddiv" : "div",
7570 "0,x,y", xreg, yreg);
7571 expr1.X_add_number = 2;
7572 macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg);
7573 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", "6",
7576 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7577 since that causes an overflow. We should do that as well,
7578 but I don't see how to do the comparisons without a temporary
7580 --mips_opts.noreorder;
7581 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x", zreg);
7600 mips_emit_delays (true);
7601 ++mips_opts.noreorder;
7602 mips_any_noreorder = 1;
7603 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "0,x,y",
7605 expr1.X_add_number = 2;
7606 macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg);
7607 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
7609 --mips_opts.noreorder;
7610 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "x", zreg);
7616 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7617 dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
7618 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "x",
7627 if (imm_expr.X_op != O_constant)
7628 as_bad (_("Unsupported large constant"));
7629 imm_expr.X_add_number = -imm_expr.X_add_number;
7630 macro_build ((char *) NULL, &icnt, &imm_expr,
7631 dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
7635 if (imm_expr.X_op != O_constant)
7636 as_bad (_("Unsupported large constant"));
7637 imm_expr.X_add_number = -imm_expr.X_add_number;
7638 macro_build ((char *) NULL, &icnt, &imm_expr, "addiu",
7643 if (imm_expr.X_op != O_constant)
7644 as_bad (_("Unsupported large constant"));
7645 imm_expr.X_add_number = -imm_expr.X_add_number;
7646 macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu",
7669 goto do_reverse_branch;
7673 goto do_reverse_branch;
7685 goto do_reverse_branch;
7696 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y",
7698 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p");
7725 goto do_addone_branch_i;
7730 goto do_addone_branch_i;
7745 goto do_addone_branch_i;
7752 if (imm_expr.X_op != O_constant)
7753 as_bad (_("Unsupported large constant"));
7754 ++imm_expr.X_add_number;
7757 macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg);
7758 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p");
7762 expr1.X_add_number = 0;
7763 macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg);
7765 move_register (&icnt, xreg, yreg);
7766 expr1.X_add_number = 2;
7767 macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p");
7768 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7769 "neg", "x,w", xreg, xreg);
7773 /* For consistency checking, verify that all bits are specified either
7774 by the match/mask part of the instruction definition, or by the
7777 validate_mips_insn (opc)
7778 const struct mips_opcode *opc;
7780 const char *p = opc->args;
7782 unsigned long used_bits = opc->mask;
7784 if ((used_bits & opc->match) != opc->match)
7786 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7787 opc->name, opc->args);
7790 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7797 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7798 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7800 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
7801 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
7802 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
7803 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7805 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7806 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
7808 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
7810 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
7811 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
7812 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
7813 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
7814 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7815 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
7816 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7817 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7818 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7819 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7820 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
7821 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7822 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7823 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
7824 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7825 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
7826 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7828 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
7829 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
7830 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7831 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
7833 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7834 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7835 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
7836 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7837 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7838 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7839 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
7840 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7841 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7844 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
7845 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
7846 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7848 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7849 c, opc->name, opc->args);
7853 if (used_bits != 0xffffffff)
7855 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7856 ~used_bits & 0xffffffff, opc->name, opc->args);
7862 /* This routine assembles an instruction into its binary format. As a
7863 side effect, it sets one of the global variables imm_reloc or
7864 offset_reloc to the type of relocation to do if one of the operands
7865 is an address expression. */
7870 struct mips_cl_insn *ip;
7875 struct mips_opcode *insn;
7878 unsigned int lastregno = 0;
7884 /* If the instruction contains a '.', we first try to match an instruction
7885 including the '.'. Then we try again without the '.'. */
7887 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
7890 /* If we stopped on whitespace, then replace the whitespace with null for
7891 the call to hash_find. Save the character we replaced just in case we
7892 have to re-parse the instruction. */
7899 insn = (struct mips_opcode *) hash_find (op_hash, str);
7901 /* If we didn't find the instruction in the opcode table, try again, but
7902 this time with just the instruction up to, but not including the
7906 /* Restore the character we overwrite above (if any). */
7910 /* Scan up to the first '.' or whitespace. */
7912 *s != '\0' && *s != '.' && !ISSPACE (*s);
7916 /* If we did not find a '.', then we can quit now. */
7919 insn_error = "unrecognized opcode";
7923 /* Lookup the instruction in the hash table. */
7925 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
7927 insn_error = "unrecognized opcode";
7937 assert (strcmp (insn->name, str) == 0);
7939 if (OPCODE_IS_MEMBER (insn,
7941 | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
7942 | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
7948 if (insn->pinfo != INSN_MACRO)
7950 if (mips_arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)
7956 if (insn + 1 < &mips_opcodes[NUMOPCODES]
7957 && strcmp (insn->name, insn[1].name) == 0)
7966 static char buf[100];
7968 _("opcode not supported on this processor: %s (%s)"),
7969 mips_cpu_to_str (mips_arch),
7970 mips_isa_to_str (mips_opts.isa));
7981 ip->insn_opcode = insn->match;
7983 for (args = insn->args;; ++args)
7987 s += strspn (s, " \t");
7991 case '\0': /* end of args */
8004 ip->insn_opcode |= lastregno << OP_SH_RS;
8008 ip->insn_opcode |= lastregno << OP_SH_RT;
8012 ip->insn_opcode |= lastregno << OP_SH_FT;
8016 ip->insn_opcode |= lastregno << OP_SH_FS;
8022 /* Handle optional base register.
8023 Either the base register is omitted or
8024 we must have a left paren. */
8025 /* This is dependent on the next operand specifier
8026 is a base register specification. */
8027 assert (args[1] == 'b' || args[1] == '5'
8028 || args[1] == '-' || args[1] == '4');
8032 case ')': /* these must match exactly */
8037 case '<': /* must be at least one digit */
8039 * According to the manual, if the shift amount is greater
8040 * than 31 or less than 0, then the shift amount should be
8041 * mod 32. In reality the mips assembler issues an error.
8042 * We issue a warning and mask out all but the low 5 bits.
8044 my_getExpression (&imm_expr, s);
8045 check_absolute_expr (ip, &imm_expr);
8046 if ((unsigned long) imm_expr.X_add_number > 31)
8048 as_warn (_("Improper shift amount (%ld)"),
8049 (long) imm_expr.X_add_number);
8050 imm_expr.X_add_number &= OP_MASK_SHAMT;
8052 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT;
8053 imm_expr.X_op = O_absent;
8057 case '>': /* shift amount minus 32 */
8058 my_getExpression (&imm_expr, s);
8059 check_absolute_expr (ip, &imm_expr);
8060 if ((unsigned long) imm_expr.X_add_number < 32
8061 || (unsigned long) imm_expr.X_add_number > 63)
8063 ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT;
8064 imm_expr.X_op = O_absent;
8068 case 'k': /* cache code */
8069 case 'h': /* prefx code */
8070 my_getExpression (&imm_expr, s);
8071 check_absolute_expr (ip, &imm_expr);
8072 if ((unsigned long) imm_expr.X_add_number > 31)
8074 as_warn (_("Invalid value for `%s' (%lu)"),
8076 (unsigned long) imm_expr.X_add_number);
8077 imm_expr.X_add_number &= 0x1f;
8080 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE;
8082 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX;
8083 imm_expr.X_op = O_absent;
8087 case 'c': /* break code */
8088 my_getExpression (&imm_expr, s);
8089 check_absolute_expr (ip, &imm_expr);
8090 if ((unsigned) imm_expr.X_add_number > 1023)
8092 as_warn (_("Illegal break code (%ld)"),
8093 (long) imm_expr.X_add_number);
8094 imm_expr.X_add_number &= OP_MASK_CODE;
8096 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE;
8097 imm_expr.X_op = O_absent;
8101 case 'q': /* lower break code */
8102 my_getExpression (&imm_expr, s);
8103 check_absolute_expr (ip, &imm_expr);
8104 if ((unsigned) imm_expr.X_add_number > 1023)
8106 as_warn (_("Illegal lower break code (%ld)"),
8107 (long) imm_expr.X_add_number);
8108 imm_expr.X_add_number &= OP_MASK_CODE2;
8110 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2;
8111 imm_expr.X_op = O_absent;
8115 case 'B': /* 20-bit syscall/break code. */
8116 my_getExpression (&imm_expr, s);
8117 check_absolute_expr (ip, &imm_expr);
8118 if ((unsigned) imm_expr.X_add_number > OP_MASK_CODE20)
8119 as_warn (_("Illegal 20-bit code (%ld)"),
8120 (long) imm_expr.X_add_number);
8121 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20;
8122 imm_expr.X_op = O_absent;
8126 case 'C': /* Coprocessor code */
8127 my_getExpression (&imm_expr, s);
8128 check_absolute_expr (ip, &imm_expr);
8129 if ((unsigned long) imm_expr.X_add_number >= (1 << 25))
8131 as_warn (_("Coproccesor code > 25 bits (%ld)"),
8132 (long) imm_expr.X_add_number);
8133 imm_expr.X_add_number &= ((1 << 25) - 1);
8135 ip->insn_opcode |= imm_expr.X_add_number;
8136 imm_expr.X_op = O_absent;
8140 case 'J': /* 19-bit wait code. */
8141 my_getExpression (&imm_expr, s);
8142 check_absolute_expr (ip, &imm_expr);
8143 if ((unsigned) imm_expr.X_add_number > OP_MASK_CODE19)
8144 as_warn (_("Illegal 19-bit code (%ld)"),
8145 (long) imm_expr.X_add_number);
8146 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19;
8147 imm_expr.X_op = O_absent;
8151 case 'P': /* Performance register */
8152 my_getExpression (&imm_expr, s);
8153 check_absolute_expr (ip, &imm_expr);
8154 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
8156 as_warn (_("Invalid performance register (%ld)"),
8157 (long) imm_expr.X_add_number);
8158 imm_expr.X_add_number &= OP_MASK_PERFREG;
8160 ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG);
8161 imm_expr.X_op = O_absent;
8165 case 'b': /* base register */
8166 case 'd': /* destination register */
8167 case 's': /* source register */
8168 case 't': /* target register */
8169 case 'r': /* both target and source */
8170 case 'v': /* both dest and source */
8171 case 'w': /* both dest and target */
8172 case 'E': /* coprocessor target register */
8173 case 'G': /* coprocessor destination register */
8174 case 'x': /* ignore register name */
8175 case 'z': /* must be zero register */
8176 case 'U': /* destination register (clo/clz). */
8191 while (ISDIGIT (*s));
8193 as_bad (_("Invalid register number (%d)"), regno);
8195 else if (*args == 'E' || *args == 'G')
8199 if (s[1] == 'r' && s[2] == 'a')
8204 else if (s[1] == 'f' && s[2] == 'p')
8209 else if (s[1] == 's' && s[2] == 'p')
8214 else if (s[1] == 'g' && s[2] == 'p')
8219 else if (s[1] == 'a' && s[2] == 't')
8224 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
8229 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
8234 else if (itbl_have_entries)
8239 p = s + 1; /* advance past '$' */
8240 n = itbl_get_field (&p); /* n is name */
8242 /* See if this is a register defined in an
8244 if (itbl_get_reg_val (n, &r))
8246 /* Get_field advances to the start of
8247 the next field, so we need to back
8248 rack to the end of the last field. */
8252 s = strchr (s, '\0');
8265 as_warn (_("Used $at without \".set noat\""));
8271 if (c == 'r' || c == 'v' || c == 'w')
8278 /* 'z' only matches $0. */
8279 if (c == 'z' && regno != 0)
8282 /* Now that we have assembled one operand, we use the args string
8283 * to figure out where it goes in the instruction. */
8290 ip->insn_opcode |= regno << OP_SH_RS;
8294 ip->insn_opcode |= regno << OP_SH_RD;
8297 ip->insn_opcode |= regno << OP_SH_RD;
8298 ip->insn_opcode |= regno << OP_SH_RT;
8303 ip->insn_opcode |= regno << OP_SH_RT;
8306 /* This case exists because on the r3000 trunc
8307 expands into a macro which requires a gp
8308 register. On the r6000 or r4000 it is
8309 assembled into a single instruction which
8310 ignores the register. Thus the insn version
8311 is MIPS_ISA2 and uses 'x', and the macro
8312 version is MIPS_ISA1 and uses 't'. */
8315 /* This case is for the div instruction, which
8316 acts differently if the destination argument
8317 is $0. This only matches $0, and is checked
8318 outside the switch. */
8321 /* Itbl operand; not yet implemented. FIXME ?? */
8323 /* What about all other operands like 'i', which
8324 can be specified in the opcode table? */
8334 ip->insn_opcode |= lastregno << OP_SH_RS;
8337 ip->insn_opcode |= lastregno << OP_SH_RT;
8342 case 'O': /* MDMX alignment immediate constant. */
8343 my_getExpression (&imm_expr, s);
8344 check_absolute_expr (ip, &imm_expr);
8345 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
8347 as_warn ("Improper align amount (%ld), using low bits",
8348 (long) imm_expr.X_add_number);
8349 imm_expr.X_add_number &= OP_MASK_ALN;
8351 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN;
8352 imm_expr.X_op = O_absent;
8356 case 'Q': /* MDMX vector, element sel, or const. */
8359 /* MDMX Immediate. */
8360 my_getExpression (&imm_expr, s);
8361 check_absolute_expr (ip, &imm_expr);
8362 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
8364 as_warn (_("Invalid MDMX Immediate (%ld)"),
8365 (long) imm_expr.X_add_number);
8366 imm_expr.X_add_number &= OP_MASK_FT;
8368 imm_expr.X_add_number &= OP_MASK_FT;
8369 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8370 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
8372 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
8373 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT;
8374 imm_expr.X_op = O_absent;
8378 /* Not MDMX Immediate. Fall through. */
8379 case 'X': /* MDMX destination register. */
8380 case 'Y': /* MDMX source register. */
8381 case 'Z': /* MDMX target register. */
8383 case 'D': /* floating point destination register */
8384 case 'S': /* floating point source register */
8385 case 'T': /* floating point target register */
8386 case 'R': /* floating point source register */
8390 /* Accept $fN for FP and MDMX register numbers, and in
8391 addition accept $vN for MDMX register numbers. */
8392 if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2]))
8393 || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v'
8404 while (ISDIGIT (*s));
8407 as_bad (_("Invalid float register number (%d)"), regno);
8409 if ((regno & 1) != 0
8411 && ! (strcmp (str, "mtc1") == 0
8412 || strcmp (str, "mfc1") == 0
8413 || strcmp (str, "lwc1") == 0
8414 || strcmp (str, "swc1") == 0
8415 || strcmp (str, "l.s") == 0
8416 || strcmp (str, "s.s") == 0))
8417 as_warn (_("Float register should be even, was %d"),
8425 if (c == 'V' || c == 'W')
8436 ip->insn_opcode |= regno << OP_SH_FD;
8441 ip->insn_opcode |= regno << OP_SH_FS;
8444 /* This is like 'Z', but also needs to fix the MDMX
8445 vector/scalar select bits. Note that the
8446 scalar immediate case is handled above. */
8449 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
8450 int max_el = (is_qh ? 3 : 7);
8452 my_getExpression(&imm_expr, s);
8453 check_absolute_expr (ip, &imm_expr);
8455 if (imm_expr.X_add_number > max_el)
8456 as_bad(_("Bad element selector %ld"),
8457 (long) imm_expr.X_add_number);
8458 imm_expr.X_add_number &= max_el;
8459 ip->insn_opcode |= (imm_expr.X_add_number
8463 as_warn(_("Expecting ']' found '%s'"), s);
8469 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8470 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
8473 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
8480 ip->insn_opcode |= regno << OP_SH_FT;
8483 ip->insn_opcode |= regno << OP_SH_FR;
8493 ip->insn_opcode |= lastregno << OP_SH_FS;
8496 ip->insn_opcode |= lastregno << OP_SH_FT;
8502 my_getExpression (&imm_expr, s);
8503 if (imm_expr.X_op != O_big
8504 && imm_expr.X_op != O_constant)
8505 insn_error = _("absolute expression required");
8510 my_getExpression (&offset_expr, s);
8511 *imm_reloc = BFD_RELOC_32;
8524 unsigned char temp[8];
8526 unsigned int length;
8531 /* These only appear as the last operand in an
8532 instruction, and every instruction that accepts
8533 them in any variant accepts them in all variants.
8534 This means we don't have to worry about backing out
8535 any changes if the instruction does not match.
8537 The difference between them is the size of the
8538 floating point constant and where it goes. For 'F'
8539 and 'L' the constant is 64 bits; for 'f' and 'l' it
8540 is 32 bits. Where the constant is placed is based
8541 on how the MIPS assembler does things:
8544 f -- immediate value
8547 The .lit4 and .lit8 sections are only used if
8548 permitted by the -G argument.
8550 When generating embedded PIC code, we use the
8551 .lit8 section but not the .lit4 section (we can do
8552 .lit4 inline easily; we need to put .lit8
8553 somewhere in the data segment, and using .lit8
8554 permits the linker to eventually combine identical
8557 The code below needs to know whether the target register
8558 is 32 or 64 bits wide. It relies on the fact 'f' and
8559 'F' are used with GPR-based instructions and 'l' and
8560 'L' are used with FPR-based instructions. */
8562 f64 = *args == 'F' || *args == 'L';
8563 using_gprs = *args == 'F' || *args == 'f';
8565 save_in = input_line_pointer;
8566 input_line_pointer = s;
8567 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
8569 s = input_line_pointer;
8570 input_line_pointer = save_in;
8571 if (err != NULL && *err != '\0')
8573 as_bad (_("Bad floating point constant: %s"), err);
8574 memset (temp, '\0', sizeof temp);
8575 length = f64 ? 8 : 4;
8578 assert (length == (unsigned) (f64 ? 8 : 4));
8582 && (! USE_GLOBAL_POINTER_OPT
8583 || mips_pic == EMBEDDED_PIC
8584 || g_switch_value < 4
8585 || (temp[0] == 0 && temp[1] == 0)
8586 || (temp[2] == 0 && temp[3] == 0))))
8588 imm_expr.X_op = O_constant;
8589 if (! target_big_endian)
8590 imm_expr.X_add_number = bfd_getl32 (temp);
8592 imm_expr.X_add_number = bfd_getb32 (temp);
8595 && ! mips_disable_float_construction
8596 /* Constants can only be constructed in GPRs and
8597 copied to FPRs if the GPRs are at least as wide
8598 as the FPRs. Force the constant into memory if
8599 we are using 64-bit FPRs but the GPRs are only
8602 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
8603 && ((temp[0] == 0 && temp[1] == 0)
8604 || (temp[2] == 0 && temp[3] == 0))
8605 && ((temp[4] == 0 && temp[5] == 0)
8606 || (temp[6] == 0 && temp[7] == 0)))
8608 /* The value is simple enough to load with a couple of
8609 instructions. If using 32-bit registers, set
8610 imm_expr to the high order 32 bits and offset_expr to
8611 the low order 32 bits. Otherwise, set imm_expr to
8612 the entire 64 bit constant. */
8613 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
8615 imm_expr.X_op = O_constant;
8616 offset_expr.X_op = O_constant;
8617 if (! target_big_endian)
8619 imm_expr.X_add_number = bfd_getl32 (temp + 4);
8620 offset_expr.X_add_number = bfd_getl32 (temp);
8624 imm_expr.X_add_number = bfd_getb32 (temp);
8625 offset_expr.X_add_number = bfd_getb32 (temp + 4);
8627 if (offset_expr.X_add_number == 0)
8628 offset_expr.X_op = O_absent;
8630 else if (sizeof (imm_expr.X_add_number) > 4)
8632 imm_expr.X_op = O_constant;
8633 if (! target_big_endian)
8634 imm_expr.X_add_number = bfd_getl64 (temp);
8636 imm_expr.X_add_number = bfd_getb64 (temp);
8640 imm_expr.X_op = O_big;
8641 imm_expr.X_add_number = 4;
8642 if (! target_big_endian)
8644 generic_bignum[0] = bfd_getl16 (temp);
8645 generic_bignum[1] = bfd_getl16 (temp + 2);
8646 generic_bignum[2] = bfd_getl16 (temp + 4);
8647 generic_bignum[3] = bfd_getl16 (temp + 6);
8651 generic_bignum[0] = bfd_getb16 (temp + 6);
8652 generic_bignum[1] = bfd_getb16 (temp + 4);
8653 generic_bignum[2] = bfd_getb16 (temp + 2);
8654 generic_bignum[3] = bfd_getb16 (temp);
8660 const char *newname;
8663 /* Switch to the right section. */
8665 subseg = now_subseg;
8668 default: /* unused default case avoids warnings. */
8670 newname = RDATA_SECTION_NAME;
8671 if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8)
8672 || mips_pic == EMBEDDED_PIC)
8676 if (mips_pic == EMBEDDED_PIC)
8679 newname = RDATA_SECTION_NAME;
8682 assert (!USE_GLOBAL_POINTER_OPT
8683 || g_switch_value >= 4);
8687 new_seg = subseg_new (newname, (subsegT) 0);
8688 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
8689 bfd_set_section_flags (stdoutput, new_seg,
8694 frag_align (*args == 'l' ? 2 : 3, 0, 0);
8695 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
8696 && strcmp (TARGET_OS, "elf") != 0)
8697 record_alignment (new_seg, 4);
8699 record_alignment (new_seg, *args == 'l' ? 2 : 3);
8701 as_bad (_("Can't use floating point insn in this section"));
8703 /* Set the argument to the current address in the
8705 offset_expr.X_op = O_symbol;
8706 offset_expr.X_add_symbol =
8707 symbol_new ("L0\001", now_seg,
8708 (valueT) frag_now_fix (), frag_now);
8709 offset_expr.X_add_number = 0;
8711 /* Put the floating point number into the section. */
8712 p = frag_more ((int) length);
8713 memcpy (p, temp, length);
8715 /* Switch back to the original section. */
8716 subseg_set (seg, subseg);
8721 case 'i': /* 16 bit unsigned immediate */
8722 case 'j': /* 16 bit signed immediate */
8723 *imm_reloc = BFD_RELOC_LO16;
8724 c = my_getSmallExpression (&imm_expr, s);
8729 if (imm_expr.X_op == O_constant)
8730 imm_expr.X_add_number =
8731 (imm_expr.X_add_number >> 16) & 0xffff;
8733 else if (c == S_EX_HIGHEST)
8734 *imm_reloc = BFD_RELOC_MIPS_HIGHEST;
8735 else if (c == S_EX_HIGHER)
8736 *imm_reloc = BFD_RELOC_MIPS_HIGHER;
8737 else if (c == S_EX_GP_REL)
8739 /* This occurs in NewABI only. */
8740 c = my_getSmallExpression (&imm_expr, s);
8742 as_bad (_("bad composition of relocations"));
8745 c = my_getSmallExpression (&imm_expr, s);
8747 as_bad (_("bad composition of relocations"));
8750 imm_reloc[0] = BFD_RELOC_GPREL16;
8751 imm_reloc[1] = BFD_RELOC_MIPS_SUB;
8752 imm_reloc[2] = BFD_RELOC_LO16;
8757 else if (c == S_EX_HI)
8759 *imm_reloc = BFD_RELOC_HI16_S;
8760 imm_unmatched_hi = true;
8763 *imm_reloc = BFD_RELOC_HI16;
8765 else if (imm_expr.X_op == O_constant)
8766 imm_expr.X_add_number &= 0xffff;
8770 if ((c == S_EX_NONE && imm_expr.X_op != O_constant)
8771 || ((imm_expr.X_add_number < 0
8772 || imm_expr.X_add_number >= 0x10000)
8773 && imm_expr.X_op == O_constant))
8775 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
8776 !strcmp (insn->name, insn[1].name))
8778 if (imm_expr.X_op == O_constant
8779 || imm_expr.X_op == O_big)
8780 as_bad (_("16 bit expression not in range 0..65535"));
8788 /* The upper bound should be 0x8000, but
8789 unfortunately the MIPS assembler accepts numbers
8790 from 0x8000 to 0xffff and sign extends them, and
8791 we want to be compatible. We only permit this
8792 extended range for an instruction which does not
8793 provide any further alternates, since those
8794 alternates may handle other cases. People should
8795 use the numbers they mean, rather than relying on
8796 a mysterious sign extension. */
8797 more = (insn + 1 < &mips_opcodes[NUMOPCODES] &&
8798 strcmp (insn->name, insn[1].name) == 0);
8803 if ((c == S_EX_NONE && imm_expr.X_op != O_constant)
8804 || ((imm_expr.X_add_number < -0x8000
8805 || imm_expr.X_add_number >= max)
8806 && imm_expr.X_op == O_constant)
8808 && imm_expr.X_add_number < 0
8810 && imm_expr.X_unsigned
8811 && sizeof (imm_expr.X_add_number) <= 4))
8815 if (imm_expr.X_op == O_constant
8816 || imm_expr.X_op == O_big)
8817 as_bad (_("16 bit expression not in range -32768..32767"));
8823 case 'o': /* 16 bit offset */
8824 c = my_getSmallExpression (&offset_expr, s);
8826 /* If this value won't fit into a 16 bit offset, then go
8827 find a macro that will generate the 32 bit offset
8830 && (offset_expr.X_op != O_constant
8831 || offset_expr.X_add_number >= 0x8000
8832 || offset_expr.X_add_number < -0x8000))
8837 if (offset_expr.X_op != O_constant)
8839 offset_expr.X_add_number =
8840 (offset_expr.X_add_number >> 16) & 0xffff;
8842 *offset_reloc = BFD_RELOC_LO16;
8846 case 'p': /* pc relative offset */
8847 if (mips_pic == EMBEDDED_PIC)
8848 *offset_reloc = BFD_RELOC_16_PCREL_S2;
8850 *offset_reloc = BFD_RELOC_16_PCREL;
8851 my_getExpression (&offset_expr, s);
8855 case 'u': /* upper 16 bits */
8856 c = my_getSmallExpression (&imm_expr, s);
8857 *imm_reloc = BFD_RELOC_LO16;
8862 if (imm_expr.X_op == O_constant)
8863 imm_expr.X_add_number =
8864 (imm_expr.X_add_number >> 16) & 0xffff;
8865 else if (c == S_EX_HI)
8867 *imm_reloc = BFD_RELOC_HI16_S;
8868 imm_unmatched_hi = true;
8871 else if (c == S_EX_HIGHEST)
8872 *imm_reloc = BFD_RELOC_MIPS_HIGHEST;
8873 else if (c == S_EX_GP_REL)
8875 /* This occurs in NewABI only. */
8876 c = my_getSmallExpression (&imm_expr, s);
8878 as_bad (_("bad composition of relocations"));
8881 c = my_getSmallExpression (&imm_expr, s);
8883 as_bad (_("bad composition of relocations"));
8886 imm_reloc[0] = BFD_RELOC_GPREL16;
8887 imm_reloc[1] = BFD_RELOC_MIPS_SUB;
8888 imm_reloc[2] = BFD_RELOC_HI16_S;
8894 *imm_reloc = BFD_RELOC_HI16;
8896 else if (imm_expr.X_op == O_constant)
8897 imm_expr.X_add_number &= 0xffff;
8899 if (imm_expr.X_op == O_constant
8900 && (imm_expr.X_add_number < 0
8901 || imm_expr.X_add_number >= 0x10000))
8902 as_bad (_("lui expression not in range 0..65535"));
8906 case 'a': /* 26 bit address */
8907 my_getExpression (&offset_expr, s);
8909 *offset_reloc = BFD_RELOC_MIPS_JMP;
8912 case 'N': /* 3 bit branch condition code */
8913 case 'M': /* 3 bit compare condition code */
8914 if (strncmp (s, "$fcc", 4) != 0)
8924 while (ISDIGIT (*s));
8926 as_bad (_("invalid condition code register $fcc%d"), regno);
8928 ip->insn_opcode |= regno << OP_SH_BCC;
8930 ip->insn_opcode |= regno << OP_SH_CCC;
8934 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
8945 while (ISDIGIT (*s));
8948 c = 8; /* Invalid sel value. */
8951 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
8952 ip->insn_opcode |= c;
8956 as_bad (_("bad char = '%c'\n"), *args);
8961 /* Args don't match. */
8962 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
8963 !strcmp (insn->name, insn[1].name))
8967 insn_error = _("illegal operands");
8972 insn_error = _("illegal operands");
8977 /* This routine assembles an instruction into its binary format when
8978 assembling for the mips16. As a side effect, it sets one of the
8979 global variables imm_reloc or offset_reloc to the type of
8980 relocation to do if one of the operands is an address expression.
8981 It also sets mips16_small and mips16_ext if the user explicitly
8982 requested a small or extended instruction. */
8987 struct mips_cl_insn *ip;
8991 struct mips_opcode *insn;
8994 unsigned int lastregno = 0;
8999 mips16_small = false;
9002 for (s = str; ISLOWER (*s); ++s)
9014 if (s[1] == 't' && s[2] == ' ')
9017 mips16_small = true;
9021 else if (s[1] == 'e' && s[2] == ' ')
9030 insn_error = _("unknown opcode");
9034 if (mips_opts.noautoextend && ! mips16_ext)
9035 mips16_small = true;
9037 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
9039 insn_error = _("unrecognized opcode");
9046 assert (strcmp (insn->name, str) == 0);
9049 ip->insn_opcode = insn->match;
9050 ip->use_extend = false;
9051 imm_expr.X_op = O_absent;
9052 imm_reloc[0] = BFD_RELOC_UNUSED;
9053 imm_reloc[1] = BFD_RELOC_UNUSED;
9054 imm_reloc[2] = BFD_RELOC_UNUSED;
9055 offset_expr.X_op = O_absent;
9056 offset_reloc[0] = BFD_RELOC_UNUSED;
9057 offset_reloc[1] = BFD_RELOC_UNUSED;
9058 offset_reloc[2] = BFD_RELOC_UNUSED;
9059 for (args = insn->args; 1; ++args)
9066 /* In this switch statement we call break if we did not find
9067 a match, continue if we did find a match, or return if we
9076 /* Stuff the immediate value in now, if we can. */
9077 if (imm_expr.X_op == O_constant
9078 && *imm_reloc > BFD_RELOC_UNUSED
9079 && insn->pinfo != INSN_MACRO)
9081 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
9082 imm_expr.X_add_number, true, mips16_small,
9083 mips16_ext, &ip->insn_opcode,
9084 &ip->use_extend, &ip->extend);
9085 imm_expr.X_op = O_absent;
9086 *imm_reloc = BFD_RELOC_UNUSED;
9100 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9103 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9119 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9121 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9148 while (ISDIGIT (*s));
9151 as_bad (_("invalid register number (%d)"), regno);
9157 if (s[1] == 'r' && s[2] == 'a')
9162 else if (s[1] == 'f' && s[2] == 'p')
9167 else if (s[1] == 's' && s[2] == 'p')
9172 else if (s[1] == 'g' && s[2] == 'p')
9177 else if (s[1] == 'a' && s[2] == 't')
9182 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
9187 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
9200 if (c == 'v' || c == 'w')
9202 regno = mips16_to_32_reg_map[lastregno];
9216 regno = mips32_to_16_reg_map[regno];
9221 regno = ILLEGAL_REG;
9226 regno = ILLEGAL_REG;
9231 regno = ILLEGAL_REG;
9236 if (regno == AT && ! mips_opts.noat)
9237 as_warn (_("used $at without \".set noat\""));
9244 if (regno == ILLEGAL_REG)
9251 ip->insn_opcode |= regno << MIPS16OP_SH_RX;
9255 ip->insn_opcode |= regno << MIPS16OP_SH_RY;
9258 ip->insn_opcode |= regno << MIPS16OP_SH_RZ;
9261 ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z;
9267 ip->insn_opcode |= regno << MIPS16OP_SH_REGR32;
9270 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
9271 ip->insn_opcode |= regno << MIPS16OP_SH_REG32R;
9281 if (strncmp (s, "$pc", 3) == 0)
9305 && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0)
9307 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9308 and generate the appropriate reloc. If the text
9309 inside %gprel is not a symbol name with an
9310 optional offset, then we generate a normal reloc
9311 and will probably fail later. */
9312 my_getExpression (&imm_expr, s + sizeof "%gprel" - 1);
9313 if (imm_expr.X_op == O_symbol)
9316 *imm_reloc = BFD_RELOC_MIPS16_GPREL;
9318 ip->use_extend = true;
9325 /* Just pick up a normal expression. */
9326 my_getExpression (&imm_expr, s);
9329 if (imm_expr.X_op == O_register)
9331 /* What we thought was an expression turned out to
9334 if (s[0] == '(' && args[1] == '(')
9336 /* It looks like the expression was omitted
9337 before a register indirection, which means
9338 that the expression is implicitly zero. We
9339 still set up imm_expr, so that we handle
9340 explicit extensions correctly. */
9341 imm_expr.X_op = O_constant;
9342 imm_expr.X_add_number = 0;
9343 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9350 /* We need to relax this instruction. */
9351 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9360 /* We use offset_reloc rather than imm_reloc for the PC
9361 relative operands. This lets macros with both
9362 immediate and address operands work correctly. */
9363 my_getExpression (&offset_expr, s);
9365 if (offset_expr.X_op == O_register)
9368 /* We need to relax this instruction. */
9369 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
9373 case '6': /* break code */
9374 my_getExpression (&imm_expr, s);
9375 check_absolute_expr (ip, &imm_expr);
9376 if ((unsigned long) imm_expr.X_add_number > 63)
9378 as_warn (_("Invalid value for `%s' (%lu)"),
9380 (unsigned long) imm_expr.X_add_number);
9381 imm_expr.X_add_number &= 0x3f;
9383 ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6;
9384 imm_expr.X_op = O_absent;
9388 case 'a': /* 26 bit address */
9389 my_getExpression (&offset_expr, s);
9391 *offset_reloc = BFD_RELOC_MIPS16_JMP;
9392 ip->insn_opcode <<= 16;
9395 case 'l': /* register list for entry macro */
9396 case 'L': /* register list for exit macro */
9406 int freg, reg1, reg2;
9408 while (*s == ' ' || *s == ',')
9412 as_bad (_("can't parse register list"));
9424 while (ISDIGIT (*s))
9446 as_bad (_("invalid register list"));
9451 while (ISDIGIT (*s))
9458 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
9463 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
9468 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
9469 mask |= (reg2 - 3) << 3;
9470 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
9471 mask |= (reg2 - 15) << 1;
9472 else if (reg1 == RA && reg2 == RA)
9476 as_bad (_("invalid register list"));
9480 /* The mask is filled in in the opcode table for the
9481 benefit of the disassembler. We remove it before
9482 applying the actual mask. */
9483 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
9484 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
9488 case 'e': /* extend code */
9489 my_getExpression (&imm_expr, s);
9490 check_absolute_expr (ip, &imm_expr);
9491 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
9493 as_warn (_("Invalid value for `%s' (%lu)"),
9495 (unsigned long) imm_expr.X_add_number);
9496 imm_expr.X_add_number &= 0x7ff;
9498 ip->insn_opcode |= imm_expr.X_add_number;
9499 imm_expr.X_op = O_absent;
9509 /* Args don't match. */
9510 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
9511 strcmp (insn->name, insn[1].name) == 0)
9518 insn_error = _("illegal operands");
9524 /* This structure holds information we know about a mips16 immediate
9527 struct mips16_immed_operand
9529 /* The type code used in the argument string in the opcode table. */
9531 /* The number of bits in the short form of the opcode. */
9533 /* The number of bits in the extended form of the opcode. */
9535 /* The amount by which the short form is shifted when it is used;
9536 for example, the sw instruction has a shift count of 2. */
9538 /* The amount by which the short form is shifted when it is stored
9539 into the instruction code. */
9541 /* Non-zero if the short form is unsigned. */
9543 /* Non-zero if the extended form is unsigned. */
9545 /* Non-zero if the value is PC relative. */
9549 /* The mips16 immediate operand types. */
9551 static const struct mips16_immed_operand mips16_immed_operands[] =
9553 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9554 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9555 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9556 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9557 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
9558 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
9559 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
9560 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
9561 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
9562 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
9563 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
9564 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
9565 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
9566 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
9567 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
9568 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
9569 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9570 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9571 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
9572 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
9573 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
9576 #define MIPS16_NUM_IMMED \
9577 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9579 /* Handle a mips16 instruction with an immediate value. This or's the
9580 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9581 whether an extended value is needed; if one is needed, it sets
9582 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9583 If SMALL is true, an unextended opcode was explicitly requested.
9584 If EXT is true, an extended opcode was explicitly requested. If
9585 WARN is true, warn if EXT does not match reality. */
9588 mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend,
9597 unsigned long *insn;
9598 boolean *use_extend;
9599 unsigned short *extend;
9601 register const struct mips16_immed_operand *op;
9602 int mintiny, maxtiny;
9605 op = mips16_immed_operands;
9606 while (op->type != type)
9609 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
9614 if (type == '<' || type == '>' || type == '[' || type == ']')
9617 maxtiny = 1 << op->nbits;
9622 maxtiny = (1 << op->nbits) - 1;
9627 mintiny = - (1 << (op->nbits - 1));
9628 maxtiny = (1 << (op->nbits - 1)) - 1;
9631 /* Branch offsets have an implicit 0 in the lowest bit. */
9632 if (type == 'p' || type == 'q')
9635 if ((val & ((1 << op->shift) - 1)) != 0
9636 || val < (mintiny << op->shift)
9637 || val > (maxtiny << op->shift))
9642 if (warn && ext && ! needext)
9643 as_warn_where (file, line,
9644 _("extended operand requested but not required"));
9645 if (small && needext)
9646 as_bad_where (file, line, _("invalid unextended operand value"));
9648 if (small || (! ext && ! needext))
9652 *use_extend = false;
9653 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
9654 insnval <<= op->op_shift;
9659 long minext, maxext;
9665 maxext = (1 << op->extbits) - 1;
9669 minext = - (1 << (op->extbits - 1));
9670 maxext = (1 << (op->extbits - 1)) - 1;
9672 if (val < minext || val > maxext)
9673 as_bad_where (file, line,
9674 _("operand value out of range for instruction"));
9677 if (op->extbits == 16)
9679 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
9682 else if (op->extbits == 15)
9684 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
9689 extval = ((val & 0x1f) << 6) | (val & 0x20);
9693 *extend = (unsigned short) extval;
9698 static struct percent_op_match
9701 const enum small_ex_type type;
9706 {"%call_hi", S_EX_CALL_HI},
9707 {"%call_lo", S_EX_CALL_LO},
9708 {"%call16", S_EX_CALL16},
9709 {"%got_disp", S_EX_GOT_DISP},
9710 {"%got_page", S_EX_GOT_PAGE},
9711 {"%got_ofst", S_EX_GOT_OFST},
9712 {"%got_hi", S_EX_GOT_HI},
9713 {"%got_lo", S_EX_GOT_LO},
9715 {"%gp_rel", S_EX_GP_REL},
9716 {"%half", S_EX_HALF},
9717 {"%highest", S_EX_HIGHEST},
9718 {"%higher", S_EX_HIGHER},
9724 /* Parse small expression input. STR gets adjusted to eat up whitespace.
9725 It detects valid "%percent_op(...)" and "($reg)" strings. Percent_op's
9726 can be nested, this is handled by blanking the innermost, parsing the
9727 rest by subsequent calls. */
9730 my_getSmallParser (str, len, nestlevel)
9736 *str += strspn (*str, " \t");
9737 /* Check for expression in parentheses. */
9740 char *b = *str + 1 + strspn (*str + 1, " \t");
9743 /* Check for base register. */
9747 && (e = b + strcspn (b, ") \t"))
9748 && e - b > 1 && e - b < 4)
9751 && ((b[1] == 'f' && b[2] == 'p')
9752 || (b[1] == 's' && b[2] == 'p')
9753 || (b[1] == 'g' && b[2] == 'p')
9754 || (b[1] == 'a' && b[2] == 't')
9756 && ISDIGIT (b[2]))))
9757 || (ISDIGIT (b[1])))
9759 *len = strcspn (*str, ")") + 1;
9760 return S_EX_REGISTER;
9764 /* Check for percent_op (in parentheses). */
9765 else if (b[0] == '%')
9768 return my_getPercentOp (str, len, nestlevel);
9771 /* Some other expression in the parentheses, which can contain
9772 parentheses itself. Attempt to find the matching one. */
9778 for (s = *str + 1; *s && pcnt; s++, (*len)++)
9787 /* Check for percent_op (outside of parentheses). */
9788 else if (*str[0] == '%')
9789 return my_getPercentOp (str, len, nestlevel);
9791 /* Any other expression. */
9796 my_getPercentOp (str, len, nestlevel)
9801 char *tmp = *str + 1;
9804 while (ISALPHA (*tmp) || *tmp == '_')
9806 *tmp = TOLOWER (*tmp);
9809 while (i < (sizeof (percent_op) / sizeof (struct percent_op_match)))
9811 if (strncmp (*str, percent_op[i].str, strlen (percent_op[i].str)))
9815 int type = percent_op[i].type;
9817 /* Only %hi and %lo are allowed for OldABI. */
9818 if (! HAVE_NEWABI && type != S_EX_HI && type != S_EX_LO)
9821 *len = strlen (percent_op[i].str);
9830 my_getSmallExpression (ep, str)
9834 static char *oldstr = NULL;
9840 /* Don't update oldstr if the last call had nested percent_op's. We need
9841 it to parse the outer ones later. */
9848 c = my_getSmallParser (&str, &len, &nestlevel);
9849 if (c != S_EX_NONE && c != S_EX_REGISTER)
9852 while (c != S_EX_NONE && c != S_EX_REGISTER);
9856 /* A percent_op was encountered. Don't try to get an expression if
9857 it is already blanked out. */
9858 if (*(str + strspn (str + 1, " )")) != ')')
9862 /* Let my_getExpression() stop at the closing parenthesis. */
9863 save = *(str + len);
9864 *(str + len) = '\0';
9865 my_getExpression (ep, str);
9866 *(str + len) = save;
9870 /* Blank out including the % sign and the proper matching
9873 char *s = strrchr (oldstr, '%');
9876 for (end = strchr (s, '(') + 1; *end && pcnt; end++)
9880 else if (*end == ')')
9884 memset (s, ' ', end - s);
9888 expr_end = str + len;
9892 else if (c == S_EX_NONE)
9894 my_getExpression (ep, str);
9896 else if (c == S_EX_REGISTER)
9898 ep->X_op = O_constant;
9900 ep->X_add_symbol = NULL;
9901 ep->X_op_symbol = NULL;
9902 ep->X_add_number = 0;
9906 as_fatal (_("internal error"));
9910 /* All percent_op's have been handled. */
9917 my_getExpression (ep, str)
9924 save_in = input_line_pointer;
9925 input_line_pointer = str;
9927 expr_end = input_line_pointer;
9928 input_line_pointer = save_in;
9930 /* If we are in mips16 mode, and this is an expression based on `.',
9931 then we bump the value of the symbol by 1 since that is how other
9932 text symbols are handled. We don't bother to handle complex
9933 expressions, just `.' plus or minus a constant. */
9934 if (mips_opts.mips16
9935 && ep->X_op == O_symbol
9936 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
9937 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg
9938 && symbol_get_frag (ep->X_add_symbol) == frag_now
9939 && symbol_constant_p (ep->X_add_symbol)
9940 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
9941 S_SET_VALUE (ep->X_add_symbol, val + 1);
9944 /* Turn a string in input_line_pointer into a floating point constant
9945 of type TYPE, and store the appropriate bytes in *LITP. The number
9946 of LITTLENUMS emitted is stored in *SIZEP. An error message is
9947 returned, or NULL on OK. */
9950 md_atof (type, litP, sizeP)
9956 LITTLENUM_TYPE words[4];
9972 return _("bad call to md_atof");
9975 t = atof_ieee (input_line_pointer, type, words);
9977 input_line_pointer = t;
9981 if (! target_big_endian)
9983 for (i = prec - 1; i >= 0; i--)
9985 md_number_to_chars (litP, (valueT) words[i], 2);
9991 for (i = 0; i < prec; i++)
9993 md_number_to_chars (litP, (valueT) words[i], 2);
10002 md_number_to_chars (buf, val, n)
10007 if (target_big_endian)
10008 number_to_chars_bigendian (buf, val, n);
10010 number_to_chars_littleendian (buf, val, n);
10014 static int support_64bit_objects(void)
10016 const char **list, **l;
10018 list = bfd_target_list ();
10019 for (l = list; *l != NULL; l++)
10021 /* This is traditional mips */
10022 if (strcmp (*l, "elf64-tradbigmips") == 0
10023 || strcmp (*l, "elf64-tradlittlemips") == 0)
10025 if (strcmp (*l, "elf64-bigmips") == 0
10026 || strcmp (*l, "elf64-littlemips") == 0)
10030 return (*l != NULL);
10032 #endif /* OBJ_ELF */
10034 CONST char *md_shortopts = "nO::g::G:";
10036 struct option md_longopts[] =
10038 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
10039 {"mips0", no_argument, NULL, OPTION_MIPS1},
10040 {"mips1", no_argument, NULL, OPTION_MIPS1},
10041 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
10042 {"mips2", no_argument, NULL, OPTION_MIPS2},
10043 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
10044 {"mips3", no_argument, NULL, OPTION_MIPS3},
10045 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
10046 {"mips4", no_argument, NULL, OPTION_MIPS4},
10047 #define OPTION_MIPS5 (OPTION_MD_BASE + 5)
10048 {"mips5", no_argument, NULL, OPTION_MIPS5},
10049 #define OPTION_MIPS32 (OPTION_MD_BASE + 6)
10050 {"mips32", no_argument, NULL, OPTION_MIPS32},
10051 #define OPTION_MIPS64 (OPTION_MD_BASE + 7)
10052 {"mips64", no_argument, NULL, OPTION_MIPS64},
10053 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 8)
10054 {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC},
10055 #define OPTION_TRAP (OPTION_MD_BASE + 9)
10056 {"trap", no_argument, NULL, OPTION_TRAP},
10057 {"no-break", no_argument, NULL, OPTION_TRAP},
10058 #define OPTION_BREAK (OPTION_MD_BASE + 10)
10059 {"break", no_argument, NULL, OPTION_BREAK},
10060 {"no-trap", no_argument, NULL, OPTION_BREAK},
10061 #define OPTION_EB (OPTION_MD_BASE + 11)
10062 {"EB", no_argument, NULL, OPTION_EB},
10063 #define OPTION_EL (OPTION_MD_BASE + 12)
10064 {"EL", no_argument, NULL, OPTION_EL},
10065 #define OPTION_MIPS16 (OPTION_MD_BASE + 13)
10066 {"mips16", no_argument, NULL, OPTION_MIPS16},
10067 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 14)
10068 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
10069 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 15)
10070 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
10071 #define OPTION_MNO_7000_HILO_FIX (OPTION_MD_BASE + 16)
10072 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10073 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10074 #define OPTION_FP32 (OPTION_MD_BASE + 17)
10075 {"mfp32", no_argument, NULL, OPTION_FP32},
10076 #define OPTION_GP32 (OPTION_MD_BASE + 18)
10077 {"mgp32", no_argument, NULL, OPTION_GP32},
10078 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 19)
10079 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
10080 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 20)
10081 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
10082 #define OPTION_MARCH (OPTION_MD_BASE + 21)
10083 {"march", required_argument, NULL, OPTION_MARCH},
10084 #define OPTION_MTUNE (OPTION_MD_BASE + 22)
10085 {"mtune", required_argument, NULL, OPTION_MTUNE},
10086 #define OPTION_MCPU (OPTION_MD_BASE + 23)
10087 {"mcpu", required_argument, NULL, OPTION_MCPU},
10088 #define OPTION_M4650 (OPTION_MD_BASE + 24)
10089 {"m4650", no_argument, NULL, OPTION_M4650},
10090 #define OPTION_NO_M4650 (OPTION_MD_BASE + 25)
10091 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
10092 #define OPTION_M4010 (OPTION_MD_BASE + 26)
10093 {"m4010", no_argument, NULL, OPTION_M4010},
10094 #define OPTION_NO_M4010 (OPTION_MD_BASE + 27)
10095 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
10096 #define OPTION_M4100 (OPTION_MD_BASE + 28)
10097 {"m4100", no_argument, NULL, OPTION_M4100},
10098 #define OPTION_NO_M4100 (OPTION_MD_BASE + 29)
10099 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
10100 #define OPTION_M3900 (OPTION_MD_BASE + 30)
10101 {"m3900", no_argument, NULL, OPTION_M3900},
10102 #define OPTION_NO_M3900 (OPTION_MD_BASE + 31)
10103 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
10104 #define OPTION_GP64 (OPTION_MD_BASE + 32)
10105 {"mgp64", no_argument, NULL, OPTION_GP64},
10106 #define OPTION_MIPS3D (OPTION_MD_BASE + 33)
10107 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
10108 #define OPTION_NO_MIPS3D (OPTION_MD_BASE + 34)
10109 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
10110 #define OPTION_MDMX (OPTION_MD_BASE + 35)
10111 {"mdmx", no_argument, NULL, OPTION_MDMX},
10112 #define OPTION_NO_MDMX (OPTION_MD_BASE + 36)
10113 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
10115 #define OPTION_ELF_BASE (OPTION_MD_BASE + 37)
10116 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10117 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
10118 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
10119 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10120 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
10121 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10122 {"xgot", no_argument, NULL, OPTION_XGOT},
10123 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10124 {"mabi", required_argument, NULL, OPTION_MABI},
10125 #define OPTION_32 (OPTION_ELF_BASE + 4)
10126 {"32", no_argument, NULL, OPTION_32},
10127 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10128 {"n32", no_argument, NULL, OPTION_N32},
10129 #define OPTION_64 (OPTION_ELF_BASE + 6)
10130 {"64", no_argument, NULL, OPTION_64},
10131 #endif /* OBJ_ELF */
10132 {NULL, no_argument, NULL, 0}
10134 size_t md_longopts_size = sizeof (md_longopts);
10137 md_parse_option (c, arg)
10143 case OPTION_CONSTRUCT_FLOATS:
10144 mips_disable_float_construction = 0;
10147 case OPTION_NO_CONSTRUCT_FLOATS:
10148 mips_disable_float_construction = 1;
10160 target_big_endian = 1;
10164 target_big_endian = 0;
10172 if (arg && arg[1] == '0')
10182 mips_debug = atoi (arg);
10183 /* When the MIPS assembler sees -g or -g2, it does not do
10184 optimizations which limit full symbolic debugging. We take
10185 that to be equivalent to -O0. */
10186 if (mips_debug == 2)
10191 mips_opts.isa = ISA_MIPS1;
10195 mips_opts.isa = ISA_MIPS2;
10199 mips_opts.isa = ISA_MIPS3;
10203 mips_opts.isa = ISA_MIPS4;
10207 mips_opts.isa = ISA_MIPS5;
10210 case OPTION_MIPS32:
10211 mips_opts.isa = ISA_MIPS32;
10214 case OPTION_MIPS64:
10215 mips_opts.isa = ISA_MIPS64;
10222 int cpu = CPU_UNKNOWN;
10224 /* Identify the processor type. */
10225 if (strcasecmp (arg, "default") != 0)
10227 const struct mips_cpu_info *ci;
10229 ci = mips_cpu_info_from_name (arg);
10230 if (ci == NULL || ci->is_isa)
10235 as_fatal (_("invalid architecture -mtune=%s"), arg);
10238 as_fatal (_("invalid architecture -march=%s"), arg);
10241 as_fatal (_("invalid architecture -mcpu=%s"), arg);
10252 if (mips_tune != CPU_UNKNOWN && mips_tune != cpu)
10253 as_warn (_("A different -mtune= was already specified, is now "
10254 "-mtune=%s"), arg);
10258 if (mips_arch != CPU_UNKNOWN && mips_arch != cpu)
10259 as_warn (_("A different -march= was already specified, is now "
10260 "-march=%s"), arg);
10264 if (mips_cpu != CPU_UNKNOWN && mips_cpu != cpu)
10265 as_warn (_("A different -mcpu= was already specified, is now "
10273 if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R4650)
10274 || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R4650))
10275 as_warn (_("A different -march= or -mtune= was already specified, "
10277 mips_arch = CPU_R4650;
10278 mips_tune = CPU_R4650;
10281 case OPTION_NO_M4650:
10285 if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R4010)
10286 || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R4010))
10287 as_warn (_("A different -march= or -mtune= was already specified, "
10289 mips_arch = CPU_R4010;
10290 mips_tune = CPU_R4010;
10293 case OPTION_NO_M4010:
10297 if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_VR4100)
10298 || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_VR4100))
10299 as_warn (_("A different -march= or -mtune= was already specified, "
10301 mips_arch = CPU_VR4100;
10302 mips_tune = CPU_VR4100;
10305 case OPTION_NO_M4100:
10309 if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R3900)
10310 || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R3900))
10311 as_warn (_("A different -march= or -mtune= was already specified, "
10313 mips_arch = CPU_R3900;
10314 mips_tune = CPU_R3900;
10317 case OPTION_NO_M3900:
10321 mips_opts.ase_mdmx = 1;
10324 case OPTION_NO_MDMX:
10325 mips_opts.ase_mdmx = 0;
10328 case OPTION_MIPS16:
10329 mips_opts.mips16 = 1;
10330 mips_no_prev_insn (false);
10333 case OPTION_NO_MIPS16:
10334 mips_opts.mips16 = 0;
10335 mips_no_prev_insn (false);
10338 case OPTION_MIPS3D:
10339 mips_opts.ase_mips3d = 1;
10342 case OPTION_NO_MIPS3D:
10343 mips_opts.ase_mips3d = 0;
10346 case OPTION_MEMBEDDED_PIC:
10347 mips_pic = EMBEDDED_PIC;
10348 if (USE_GLOBAL_POINTER_OPT && g_switch_seen)
10350 as_bad (_("-G may not be used with embedded PIC code"));
10353 g_switch_value = 0x7fffffff;
10357 /* When generating ELF code, we permit -KPIC and -call_shared to
10358 select SVR4_PIC, and -non_shared to select no PIC. This is
10359 intended to be compatible with Irix 5. */
10360 case OPTION_CALL_SHARED:
10361 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10363 as_bad (_("-call_shared is supported only for ELF format"));
10366 mips_pic = SVR4_PIC;
10367 if (g_switch_seen && g_switch_value != 0)
10369 as_bad (_("-G may not be used with SVR4 PIC code"));
10372 g_switch_value = 0;
10375 case OPTION_NON_SHARED:
10376 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10378 as_bad (_("-non_shared is supported only for ELF format"));
10384 /* The -xgot option tells the assembler to use 32 offsets when
10385 accessing the got in SVR4_PIC mode. It is for Irix
10390 #endif /* OBJ_ELF */
10393 if (! USE_GLOBAL_POINTER_OPT)
10395 as_bad (_("-G is not supported for this configuration"));
10398 else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC)
10400 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
10404 g_switch_value = atoi (arg);
10409 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10412 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10414 as_bad (_("-32 is supported for ELF format only"));
10417 mips_opts.abi = O32_ABI;
10421 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10423 as_bad (_("-n32 is supported for ELF format only"));
10426 mips_opts.abi = N32_ABI;
10430 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10432 as_bad (_("-64 is supported for ELF format only"));
10435 mips_opts.abi = N64_ABI;
10436 if (! support_64bit_objects())
10437 as_fatal (_("No compiled in support for 64 bit object file format"));
10439 #endif /* OBJ_ELF */
10442 file_mips_gp32 = 1;
10443 if (mips_opts.abi != O32_ABI)
10444 mips_opts.abi = NO_ABI;
10448 file_mips_gp32 = 0;
10449 if (mips_opts.abi == O32_ABI)
10450 mips_opts.abi = NO_ABI;
10454 file_mips_fp32 = 1;
10455 if (mips_opts.abi != O32_ABI)
10456 mips_opts.abi = NO_ABI;
10461 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10463 as_bad (_("-mabi is supported for ELF format only"));
10466 if (strcmp (arg, "32") == 0)
10467 mips_opts.abi = O32_ABI;
10468 else if (strcmp (arg, "o64") == 0)
10469 mips_opts.abi = O64_ABI;
10470 else if (strcmp (arg, "n32") == 0)
10471 mips_opts.abi = N32_ABI;
10472 else if (strcmp (arg, "64") == 0)
10474 mips_opts.abi = N64_ABI;
10475 if (! support_64bit_objects())
10476 as_fatal (_("No compiled in support for 64 bit object file "
10479 else if (strcmp (arg, "eabi") == 0)
10480 mips_opts.abi = EABI_ABI;
10483 as_fatal (_("invalid abi -mabi=%s"), arg);
10487 #endif /* OBJ_ELF */
10489 case OPTION_M7000_HILO_FIX:
10490 mips_7000_hilo_fix = true;
10493 case OPTION_MNO_7000_HILO_FIX:
10494 mips_7000_hilo_fix = false;
10505 show (stream, string, col_p, first_p)
10513 fprintf (stream, "%24s", "");
10518 fprintf (stream, ", ");
10522 if (*col_p + strlen (string) > 72)
10524 fprintf (stream, "\n%24s", "");
10528 fprintf (stream, "%s", string);
10529 *col_p += strlen (string);
10535 md_show_usage (stream)
10540 fprintf (stream, _("\
10542 -membedded-pic generate embedded position independent code\n\
10543 -EB generate big endian output\n\
10544 -EL generate little endian output\n\
10545 -g, -g2 do not remove unneeded NOPs or swap branches\n\
10546 -G NUM allow referencing objects up to NUM bytes\n\
10547 implicitly with the gp register [default 8]\n"));
10548 fprintf (stream, _("\
10549 -mips1 generate MIPS ISA I instructions\n\
10550 -mips2 generate MIPS ISA II instructions\n\
10551 -mips3 generate MIPS ISA III instructions\n\
10552 -mips4 generate MIPS ISA IV instructions\n\
10553 -mips5 generate MIPS ISA V instructions\n\
10554 -mips32 generate MIPS32 ISA instructions\n\
10555 -mips64 generate MIPS64 ISA instructions\n\
10556 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
10560 show (stream, "2000", &column, &first);
10561 show (stream, "3000", &column, &first);
10562 show (stream, "3900", &column, &first);
10563 show (stream, "4000", &column, &first);
10564 show (stream, "4010", &column, &first);
10565 show (stream, "4100", &column, &first);
10566 show (stream, "4111", &column, &first);
10567 show (stream, "4300", &column, &first);
10568 show (stream, "4400", &column, &first);
10569 show (stream, "4600", &column, &first);
10570 show (stream, "4650", &column, &first);
10571 show (stream, "5000", &column, &first);
10572 show (stream, "5200", &column, &first);
10573 show (stream, "5230", &column, &first);
10574 show (stream, "5231", &column, &first);
10575 show (stream, "5261", &column, &first);
10576 show (stream, "5721", &column, &first);
10577 show (stream, "6000", &column, &first);
10578 show (stream, "8000", &column, &first);
10579 show (stream, "10000", &column, &first);
10580 show (stream, "12000", &column, &first);
10581 show (stream, "sb1", &column, &first);
10582 fputc ('\n', stream);
10584 fprintf (stream, _("\
10585 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
10586 -no-mCPU don't generate code specific to CPU.\n\
10587 For -mCPU and -no-mCPU, CPU must be one of:\n"));
10591 show (stream, "3900", &column, &first);
10592 show (stream, "4010", &column, &first);
10593 show (stream, "4100", &column, &first);
10594 show (stream, "4650", &column, &first);
10595 fputc ('\n', stream);
10597 fprintf (stream, _("\
10598 -mips16 generate mips16 instructions\n\
10599 -no-mips16 do not generate mips16 instructions\n"));
10600 fprintf (stream, _("\
10601 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
10602 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
10603 -O0 remove unneeded NOPs, do not swap branches\n\
10604 -O remove unneeded NOPs and swap branches\n\
10605 -n warn about NOPs generated from macros\n\
10606 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
10607 --trap, --no-break trap exception on div by 0 and mult overflow\n\
10608 --break, --no-trap break exception on div by 0 and mult overflow\n"));
10610 fprintf (stream, _("\
10611 -KPIC, -call_shared generate SVR4 position independent code\n\
10612 -non_shared do not generate position independent code\n\
10613 -xgot assume a 32 bit GOT\n\
10614 -mabi=ABI create ABI conformant object file for:\n"));
10618 show (stream, "32", &column, &first);
10619 show (stream, "o64", &column, &first);
10620 show (stream, "n32", &column, &first);
10621 show (stream, "64", &column, &first);
10622 show (stream, "eabi", &column, &first);
10624 fputc ('\n', stream);
10626 fprintf (stream, _("\
10627 -32 create o32 ABI object file (default)\n\
10628 -n32 create n32 ABI object file\n\
10629 -64 create 64 ABI object file\n"));
10634 mips_init_after_args ()
10636 /* initialize opcodes */
10637 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
10638 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
10642 md_pcrel_from (fixP)
10645 if (OUTPUT_FLAVOR != bfd_target_aout_flavour
10646 && fixP->fx_addsy != (symbolS *) NULL
10647 && ! S_IS_DEFINED (fixP->fx_addsy))
10649 /* This makes a branch to an undefined symbol be a branch to the
10650 current location. */
10651 if (mips_pic == EMBEDDED_PIC)
10657 /* Return the address of the delay slot. */
10658 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10661 /* This is called before the symbol table is processed. In order to
10662 work with gcc when using mips-tfile, we must keep all local labels.
10663 However, in other cases, we want to discard them. If we were
10664 called with -g, but we didn't see any debugging information, it may
10665 mean that gcc is smuggling debugging information through to
10666 mips-tfile, in which case we must generate all local labels. */
10669 mips_frob_file_before_adjust ()
10671 #ifndef NO_ECOFF_DEBUGGING
10672 if (ECOFF_DEBUGGING
10674 && ! ecoff_debugging_seen)
10675 flag_keep_locals = 1;
10679 /* Sort any unmatched HI16_S relocs so that they immediately precede
10680 the corresponding LO reloc. This is called before md_apply_fix3 and
10681 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10682 explicit use of the %hi modifier. */
10687 struct mips_hi_fixup *l;
10689 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
10691 segment_info_type *seginfo;
10694 assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S);
10696 /* Check quickly whether the next fixup happens to be a matching
10698 if (l->fixp->fx_next != NULL
10699 && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16
10700 && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
10701 && l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
10704 /* Look through the fixups for this segment for a matching %lo.
10705 When we find one, move the %hi just in front of it. We do
10706 this in two passes. In the first pass, we try to find a
10707 unique %lo. In the second pass, we permit multiple %hi
10708 relocs for a single %lo (this is a GNU extension). */
10709 seginfo = seg_info (l->seg);
10710 for (pass = 0; pass < 2; pass++)
10715 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
10717 /* Check whether this is a %lo fixup which matches l->fixp. */
10718 if (f->fx_r_type == BFD_RELOC_LO16
10719 && f->fx_addsy == l->fixp->fx_addsy
10720 && f->fx_offset == l->fixp->fx_offset
10723 || prev->fx_r_type != BFD_RELOC_HI16_S
10724 || prev->fx_addsy != f->fx_addsy
10725 || prev->fx_offset != f->fx_offset))
10729 /* Move l->fixp before f. */
10730 for (pf = &seginfo->fix_root;
10732 pf = &(*pf)->fx_next)
10733 assert (*pf != NULL);
10735 *pf = l->fixp->fx_next;
10737 l->fixp->fx_next = f;
10739 seginfo->fix_root = l->fixp;
10741 prev->fx_next = l->fixp;
10752 #if 0 /* GCC code motion plus incomplete dead code elimination
10753 can leave a %hi without a %lo. */
10755 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
10756 _("Unmatched %%hi reloc"));
10762 /* When generating embedded PIC code we need to use a special
10763 relocation to represent the difference of two symbols in the .text
10764 section (switch tables use a difference of this sort). See
10765 include/coff/mips.h for details. This macro checks whether this
10766 fixup requires the special reloc. */
10767 #define SWITCH_TABLE(fixp) \
10768 ((fixp)->fx_r_type == BFD_RELOC_32 \
10769 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
10770 && (fixp)->fx_addsy != NULL \
10771 && (fixp)->fx_subsy != NULL \
10772 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
10773 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
10775 /* When generating embedded PIC code we must keep all PC relative
10776 relocations, in case the linker has to relax a call. We also need
10777 to keep relocations for switch table entries.
10779 We may have combined relocations without symbols in the N32/N64 ABI.
10780 We have to prevent gas from dropping them. */
10783 mips_force_relocation (fixp)
10786 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
10787 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10791 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
10792 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
10793 || fixp->fx_r_type == BFD_RELOC_HI16_S
10794 || fixp->fx_r_type == BFD_RELOC_LO16))
10797 return (mips_pic == EMBEDDED_PIC
10799 || SWITCH_TABLE (fixp)
10800 || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S
10801 || fixp->fx_r_type == BFD_RELOC_PCREL_LO16));
10806 mips_need_elf_addend_fixup (fixP)
10809 if (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16)
10811 if (mips_pic == EMBEDDED_PIC
10812 && S_IS_WEAK (fixP->fx_addsy))
10814 if (mips_pic != EMBEDDED_PIC
10815 && (S_IS_WEAK (fixP->fx_addsy)
10816 || S_IS_EXTERN (fixP->fx_addsy))
10817 && !S_IS_COMMON (fixP->fx_addsy))
10819 if (symbol_used_in_reloc_p (fixP->fx_addsy)
10820 && (((bfd_get_section_flags (stdoutput,
10821 S_GET_SEGMENT (fixP->fx_addsy))
10822 & SEC_LINK_ONCE) != 0)
10823 || !strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)),
10825 sizeof (".gnu.linkonce") - 1)))
10831 /* Apply a fixup to the object file. */
10834 md_apply_fix3 (fixP, valP, seg)
10837 segT seg ATTRIBUTE_UNUSED;
10843 assert (fixP->fx_size == 4
10844 || fixP->fx_r_type == BFD_RELOC_16
10845 || fixP->fx_r_type == BFD_RELOC_32
10846 || fixP->fx_r_type == BFD_RELOC_MIPS_JMP
10847 || fixP->fx_r_type == BFD_RELOC_HI16_S
10848 || fixP->fx_r_type == BFD_RELOC_LO16
10849 || fixP->fx_r_type == BFD_RELOC_GPREL16
10850 || fixP->fx_r_type == BFD_RELOC_MIPS_LITERAL
10851 || fixP->fx_r_type == BFD_RELOC_GPREL32
10852 || fixP->fx_r_type == BFD_RELOC_64
10853 || fixP->fx_r_type == BFD_RELOC_CTOR
10854 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
10855 || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHEST
10856 || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHER
10857 || fixP->fx_r_type == BFD_RELOC_MIPS_SCN_DISP
10858 || fixP->fx_r_type == BFD_RELOC_MIPS_REL16
10859 || fixP->fx_r_type == BFD_RELOC_MIPS_RELGOT
10860 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
10861 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
10862 || fixP->fx_r_type == BFD_RELOC_MIPS_JALR);
10866 /* If we aren't adjusting this fixup to be against the section
10867 symbol, we need to adjust the value. */
10869 if (fixP->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour)
10871 if (mips_need_elf_addend_fixup (fixP))
10873 valueT symval = S_GET_VALUE (fixP->fx_addsy);
10876 if (value != 0 && ! fixP->fx_pcrel)
10878 /* In this case, the bfd_install_relocation routine will
10879 incorrectly add the symbol value back in. We just want
10880 the addend to appear in the object file. */
10883 /* Make sure the addend is still non-zero. If it became zero
10884 after the last operation, set it to a spurious value and
10885 subtract the same value from the object file's contents. */
10890 /* The in-place addends for LO16 relocations are signed;
10891 leave the matching HI16 in-place addends as zero. */
10892 if (fixP->fx_r_type != BFD_RELOC_HI16_S)
10894 reloc_howto_type *howto;
10895 bfd_vma contents, mask, field;
10897 howto = bfd_reloc_type_lookup (stdoutput,
10900 contents = bfd_get_bits (fixP->fx_frag->fr_literal
10903 target_big_endian);
10905 /* MASK has bits set where the relocation should go.
10906 FIELD is -value, shifted into the appropriate place
10907 for this relocation. */
10908 mask = 1 << (howto->bitsize - 1);
10909 mask = (((mask - 1) << 1) | 1) << howto->bitpos;
10910 field = (-value >> howto->rightshift) << howto->bitpos;
10912 bfd_put_bits ((field & mask) | (contents & ~mask),
10913 fixP->fx_frag->fr_literal + fixP->fx_where,
10915 target_big_endian);
10921 /* This code was generated using trial and error and so is
10922 fragile and not trustworthy. If you change it, you should
10923 rerun the elf-rel, elf-rel2, and empic testcases and ensure
10924 they still pass. */
10925 if (fixP->fx_pcrel || fixP->fx_subsy != NULL)
10927 value += fixP->fx_frag->fr_address + fixP->fx_where;
10929 /* BFD's REL handling, for MIPS, is _very_ weird.
10930 This gives the right results, but it can't possibly
10931 be the way things are supposed to work. */
10932 if ((fixP->fx_r_type != BFD_RELOC_16_PCREL
10933 && fixP->fx_r_type != BFD_RELOC_16_PCREL_S2)
10934 || S_GET_SEGMENT (fixP->fx_addsy) != undefined_section)
10935 value += fixP->fx_frag->fr_address + fixP->fx_where;
10940 fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc. */
10942 if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel)
10945 switch (fixP->fx_r_type)
10947 case BFD_RELOC_MIPS_JMP:
10948 case BFD_RELOC_MIPS_SHIFT5:
10949 case BFD_RELOC_MIPS_SHIFT6:
10950 case BFD_RELOC_MIPS_GOT_DISP:
10951 case BFD_RELOC_MIPS_GOT_PAGE:
10952 case BFD_RELOC_MIPS_GOT_OFST:
10953 case BFD_RELOC_MIPS_SUB:
10954 case BFD_RELOC_MIPS_INSERT_A:
10955 case BFD_RELOC_MIPS_INSERT_B:
10956 case BFD_RELOC_MIPS_DELETE:
10957 case BFD_RELOC_MIPS_HIGHEST:
10958 case BFD_RELOC_MIPS_HIGHER:
10959 case BFD_RELOC_MIPS_SCN_DISP:
10960 case BFD_RELOC_MIPS_REL16:
10961 case BFD_RELOC_MIPS_RELGOT:
10962 case BFD_RELOC_MIPS_JALR:
10963 case BFD_RELOC_HI16:
10964 case BFD_RELOC_HI16_S:
10965 case BFD_RELOC_GPREL16:
10966 case BFD_RELOC_MIPS_LITERAL:
10967 case BFD_RELOC_MIPS_CALL16:
10968 case BFD_RELOC_MIPS_GOT16:
10969 case BFD_RELOC_GPREL32:
10970 case BFD_RELOC_MIPS_GOT_HI16:
10971 case BFD_RELOC_MIPS_GOT_LO16:
10972 case BFD_RELOC_MIPS_CALL_HI16:
10973 case BFD_RELOC_MIPS_CALL_LO16:
10974 case BFD_RELOC_MIPS16_GPREL:
10975 if (fixP->fx_pcrel)
10976 as_bad_where (fixP->fx_file, fixP->fx_line,
10977 _("Invalid PC relative reloc"));
10978 /* Nothing needed to do. The value comes from the reloc entry */
10981 case BFD_RELOC_MIPS16_JMP:
10982 /* We currently always generate a reloc against a symbol, which
10983 means that we don't want an addend even if the symbol is
10985 fixP->fx_addnumber = 0;
10988 case BFD_RELOC_PCREL_HI16_S:
10989 /* The addend for this is tricky if it is internal, so we just
10990 do everything here rather than in bfd_install_relocation. */
10991 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
10996 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
10998 /* For an external symbol adjust by the address to make it
10999 pcrel_offset. We use the address of the RELLO reloc
11000 which follows this one. */
11001 value += (fixP->fx_next->fx_frag->fr_address
11002 + fixP->fx_next->fx_where);
11004 value = ((value + 0x8000) >> 16) & 0xffff;
11005 buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where;
11006 if (target_big_endian)
11008 md_number_to_chars ((char *) buf, value, 2);
11011 case BFD_RELOC_PCREL_LO16:
11012 /* The addend for this is tricky if it is internal, so we just
11013 do everything here rather than in bfd_install_relocation. */
11014 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
11019 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
11020 value += fixP->fx_frag->fr_address + fixP->fx_where;
11021 buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where;
11022 if (target_big_endian)
11024 md_number_to_chars ((char *) buf, value, 2);
11028 /* This is handled like BFD_RELOC_32, but we output a sign
11029 extended value if we are only 32 bits. */
11031 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
11033 if (8 <= sizeof (valueT))
11034 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
11041 w1 = w2 = fixP->fx_where;
11042 if (target_big_endian)
11046 md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4);
11047 if ((value & 0x80000000) != 0)
11051 md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4);
11056 case BFD_RELOC_RVA:
11058 /* If we are deleting this reloc entry, we must fill in the
11059 value now. This can happen if we have a .word which is not
11060 resolved when it appears but is later defined. We also need
11061 to fill in the value if this is an embedded PIC switch table
11064 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
11065 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
11070 /* If we are deleting this reloc entry, we must fill in the
11072 assert (fixP->fx_size == 2);
11074 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
11078 case BFD_RELOC_LO16:
11079 /* When handling an embedded PIC switch statement, we can wind
11080 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11083 if (value + 0x8000 > 0xffff)
11084 as_bad_where (fixP->fx_file, fixP->fx_line,
11085 _("relocation overflow"));
11086 buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where;
11087 if (target_big_endian)
11089 md_number_to_chars ((char *) buf, value, 2);
11093 case BFD_RELOC_16_PCREL_S2:
11094 if ((value & 0x3) != 0)
11095 as_bad_where (fixP->fx_file, fixP->fx_line,
11096 _("Branch to odd address (%lx)"), (long) value);
11098 /* Fall through. */
11100 case BFD_RELOC_16_PCREL:
11102 * We need to save the bits in the instruction since fixup_segment()
11103 * might be deleting the relocation entry (i.e., a branch within
11104 * the current segment).
11106 if (!fixP->fx_done && value != 0)
11108 /* If 'value' is zero, the remaining reloc code won't actually
11109 do the store, so it must be done here. This is probably
11110 a bug somewhere. */
11112 && (fixP->fx_r_type != BFD_RELOC_16_PCREL_S2
11113 || fixP->fx_addsy == NULL /* ??? */
11114 || ! S_IS_DEFINED (fixP->fx_addsy)))
11115 value -= fixP->fx_frag->fr_address + fixP->fx_where;
11117 value = (offsetT) value >> 2;
11119 /* update old instruction data */
11120 buf = (bfd_byte *) (fixP->fx_where + fixP->fx_frag->fr_literal);
11121 if (target_big_endian)
11122 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
11124 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
11126 if (value + 0x8000 <= 0xffff)
11127 insn |= value & 0xffff;
11130 /* The branch offset is too large. If this is an
11131 unconditional branch, and we are not generating PIC code,
11132 we can convert it to an absolute jump instruction. */
11133 if (mips_pic == NO_PIC
11135 && fixP->fx_frag->fr_address >= text_section->vma
11136 && (fixP->fx_frag->fr_address
11137 < text_section->vma + text_section->_raw_size)
11138 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
11139 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
11140 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
11142 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
11143 insn = 0x0c000000; /* jal */
11145 insn = 0x08000000; /* j */
11146 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
11148 fixP->fx_addsy = section_symbol (text_section);
11149 fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP);
11153 /* FIXME. It would be possible in principle to handle
11154 conditional branches which overflow. They could be
11155 transformed into a branch around a jump. This would
11156 require setting up variant frags for each different
11157 branch type. The native MIPS assembler attempts to
11158 handle these cases, but it appears to do it
11160 as_bad_where (fixP->fx_file, fixP->fx_line,
11161 _("Branch out of range"));
11165 md_number_to_chars ((char *) buf, (valueT) insn, 4);
11168 case BFD_RELOC_VTABLE_INHERIT:
11171 && !S_IS_DEFINED (fixP->fx_addsy)
11172 && !S_IS_WEAK (fixP->fx_addsy))
11173 S_SET_WEAK (fixP->fx_addsy);
11176 case BFD_RELOC_VTABLE_ENTRY:
11190 const struct mips_opcode *p;
11191 int treg, sreg, dreg, shamt;
11196 for (i = 0; i < NUMOPCODES; ++i)
11198 p = &mips_opcodes[i];
11199 if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO))
11201 printf ("%08lx %s\t", oc, p->name);
11202 treg = (oc >> 16) & 0x1f;
11203 sreg = (oc >> 21) & 0x1f;
11204 dreg = (oc >> 11) & 0x1f;
11205 shamt = (oc >> 6) & 0x1f;
11207 for (args = p->args;; ++args)
11218 printf ("%c", *args);
11222 assert (treg == sreg);
11223 printf ("$%d,$%d", treg, sreg);
11228 printf ("$%d", dreg);
11233 printf ("$%d", treg);
11237 printf ("0x%x", treg);
11242 printf ("$%d", sreg);
11246 printf ("0x%08lx", oc & 0x1ffffff);
11253 printf ("%d", imm);
11258 printf ("$%d", shamt);
11269 printf (_("%08lx UNDEFINED\n"), oc);
11280 name = input_line_pointer;
11281 c = get_symbol_end ();
11282 p = (symbolS *) symbol_find_or_make (name);
11283 *input_line_pointer = c;
11287 /* Align the current frag to a given power of two. The MIPS assembler
11288 also automatically adjusts any preceding label. */
11291 mips_align (to, fill, label)
11296 mips_emit_delays (false);
11297 frag_align (to, fill, 0);
11298 record_alignment (now_seg, to);
11301 assert (S_GET_SEGMENT (label) == now_seg);
11302 symbol_set_frag (label, frag_now);
11303 S_SET_VALUE (label, (valueT) frag_now_fix ());
11307 /* Align to a given power of two. .align 0 turns off the automatic
11308 alignment used by the data creating pseudo-ops. */
11312 int x ATTRIBUTE_UNUSED;
11315 register long temp_fill;
11316 long max_alignment = 15;
11320 o Note that the assembler pulls down any immediately preceeding label
11321 to the aligned address.
11322 o It's not documented but auto alignment is reinstated by
11323 a .align pseudo instruction.
11324 o Note also that after auto alignment is turned off the mips assembler
11325 issues an error on attempt to assemble an improperly aligned data item.
11330 temp = get_absolute_expression ();
11331 if (temp > max_alignment)
11332 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
11335 as_warn (_("Alignment negative: 0 assumed."));
11338 if (*input_line_pointer == ',')
11340 ++input_line_pointer;
11341 temp_fill = get_absolute_expression ();
11348 mips_align (temp, (int) temp_fill,
11349 insn_labels != NULL ? insn_labels->label : NULL);
11356 demand_empty_rest_of_line ();
11360 mips_flush_pending_output ()
11362 mips_emit_delays (false);
11363 mips_clear_insn_labels ();
11372 /* When generating embedded PIC code, we only use the .text, .lit8,
11373 .sdata and .sbss sections. We change the .data and .rdata
11374 pseudo-ops to use .sdata. */
11375 if (mips_pic == EMBEDDED_PIC
11376 && (sec == 'd' || sec == 'r'))
11380 /* The ELF backend needs to know that we are changing sections, so
11381 that .previous works correctly. We could do something like check
11382 for an obj_section_change_hook macro, but that might be confusing
11383 as it would not be appropriate to use it in the section changing
11384 functions in read.c, since obj-elf.c intercepts those. FIXME:
11385 This should be cleaner, somehow. */
11386 obj_elf_section_change_hook ();
11389 mips_emit_delays (false);
11399 subseg_set (bss_section, (subsegT) get_absolute_expression ());
11400 demand_empty_rest_of_line ();
11404 if (USE_GLOBAL_POINTER_OPT)
11406 seg = subseg_new (RDATA_SECTION_NAME,
11407 (subsegT) get_absolute_expression ());
11408 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11410 bfd_set_section_flags (stdoutput, seg,
11416 if (strcmp (TARGET_OS, "elf") != 0)
11417 record_alignment (seg, 4);
11419 demand_empty_rest_of_line ();
11423 as_bad (_("No read only data section in this object file format"));
11424 demand_empty_rest_of_line ();
11430 if (USE_GLOBAL_POINTER_OPT)
11432 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
11433 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11435 bfd_set_section_flags (stdoutput, seg,
11436 SEC_ALLOC | SEC_LOAD | SEC_RELOC
11438 if (strcmp (TARGET_OS, "elf") != 0)
11439 record_alignment (seg, 4);
11441 demand_empty_rest_of_line ();
11446 as_bad (_("Global pointers not supported; recompile -G 0"));
11447 demand_empty_rest_of_line ();
11456 mips_enable_auto_align ()
11467 label = insn_labels != NULL ? insn_labels->label : NULL;
11468 mips_emit_delays (false);
11469 if (log_size > 0 && auto_align)
11470 mips_align (log_size, 0, label);
11471 mips_clear_insn_labels ();
11472 cons (1 << log_size);
11476 s_float_cons (type)
11481 label = insn_labels != NULL ? insn_labels->label : NULL;
11483 mips_emit_delays (false);
11488 mips_align (3, 0, label);
11490 mips_align (2, 0, label);
11493 mips_clear_insn_labels ();
11498 /* Handle .globl. We need to override it because on Irix 5 you are
11501 where foo is an undefined symbol, to mean that foo should be
11502 considered to be the address of a function. */
11506 int x ATTRIBUTE_UNUSED;
11513 name = input_line_pointer;
11514 c = get_symbol_end ();
11515 symbolP = symbol_find_or_make (name);
11516 *input_line_pointer = c;
11517 SKIP_WHITESPACE ();
11519 /* On Irix 5, every global symbol that is not explicitly labelled as
11520 being a function is apparently labelled as being an object. */
11523 if (! is_end_of_line[(unsigned char) *input_line_pointer])
11528 secname = input_line_pointer;
11529 c = get_symbol_end ();
11530 sec = bfd_get_section_by_name (stdoutput, secname);
11532 as_bad (_("%s: no such section"), secname);
11533 *input_line_pointer = c;
11535 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
11536 flag = BSF_FUNCTION;
11539 symbol_get_bfdsym (symbolP)->flags |= flag;
11541 S_SET_EXTERNAL (symbolP);
11542 demand_empty_rest_of_line ();
11547 int x ATTRIBUTE_UNUSED;
11552 opt = input_line_pointer;
11553 c = get_symbol_end ();
11557 /* FIXME: What does this mean? */
11559 else if (strncmp (opt, "pic", 3) == 0)
11563 i = atoi (opt + 3);
11567 mips_pic = SVR4_PIC;
11569 as_bad (_(".option pic%d not supported"), i);
11571 if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC)
11573 if (g_switch_seen && g_switch_value != 0)
11574 as_warn (_("-G may not be used with SVR4 PIC code"));
11575 g_switch_value = 0;
11576 bfd_set_gp_size (stdoutput, 0);
11580 as_warn (_("Unrecognized option \"%s\""), opt);
11582 *input_line_pointer = c;
11583 demand_empty_rest_of_line ();
11586 /* This structure is used to hold a stack of .set values. */
11588 struct mips_option_stack
11590 struct mips_option_stack *next;
11591 struct mips_set_options options;
11594 static struct mips_option_stack *mips_opts_stack;
11596 /* Handle the .set pseudo-op. */
11600 int x ATTRIBUTE_UNUSED;
11602 char *name = input_line_pointer, ch;
11604 while (!is_end_of_line[(unsigned char) *input_line_pointer])
11605 ++input_line_pointer;
11606 ch = *input_line_pointer;
11607 *input_line_pointer = '\0';
11609 if (strcmp (name, "reorder") == 0)
11611 if (mips_opts.noreorder && prev_nop_frag != NULL)
11613 /* If we still have pending nops, we can discard them. The
11614 usual nop handling will insert any that are still
11616 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11617 * (mips_opts.mips16 ? 2 : 4));
11618 prev_nop_frag = NULL;
11620 mips_opts.noreorder = 0;
11622 else if (strcmp (name, "noreorder") == 0)
11624 mips_emit_delays (true);
11625 mips_opts.noreorder = 1;
11626 mips_any_noreorder = 1;
11628 else if (strcmp (name, "at") == 0)
11630 mips_opts.noat = 0;
11632 else if (strcmp (name, "noat") == 0)
11634 mips_opts.noat = 1;
11636 else if (strcmp (name, "macro") == 0)
11638 mips_opts.warn_about_macros = 0;
11640 else if (strcmp (name, "nomacro") == 0)
11642 if (mips_opts.noreorder == 0)
11643 as_bad (_("`noreorder' must be set before `nomacro'"));
11644 mips_opts.warn_about_macros = 1;
11646 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
11648 mips_opts.nomove = 0;
11650 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
11652 mips_opts.nomove = 1;
11654 else if (strcmp (name, "bopt") == 0)
11656 mips_opts.nobopt = 0;
11658 else if (strcmp (name, "nobopt") == 0)
11660 mips_opts.nobopt = 1;
11662 else if (strcmp (name, "mdmx") == 0)
11663 mips_opts.ase_mdmx = 1;
11664 else if (strcmp (name, "nomdmx") == 0)
11665 mips_opts.ase_mdmx = 0;
11666 else if (strcmp (name, "mips16") == 0
11667 || strcmp (name, "MIPS-16") == 0)
11668 mips_opts.mips16 = 1;
11669 else if (strcmp (name, "nomips16") == 0
11670 || strcmp (name, "noMIPS-16") == 0)
11671 mips_opts.mips16 = 0;
11672 else if (strcmp (name, "mips3d") == 0)
11673 mips_opts.ase_mips3d = 1;
11674 else if (strcmp (name, "nomips3d") == 0)
11675 mips_opts.ase_mips3d = 0;
11676 else if (strncmp (name, "mips", 4) == 0)
11680 /* Permit the user to change the ISA on the fly. Needless to
11681 say, misuse can cause serious problems. */
11682 isa = atoi (name + 4);
11686 mips_opts.gp32 = file_mips_gp32;
11687 mips_opts.fp32 = file_mips_fp32;
11688 mips_opts.abi = file_mips_abi;
11693 mips_opts.gp32 = 1;
11694 mips_opts.fp32 = 1;
11700 /* Loosen ABI register width restriction. */
11701 if (mips_opts.abi == O32_ABI)
11702 mips_opts.abi = NO_ABI;
11703 mips_opts.gp32 = 0;
11704 mips_opts.fp32 = 0;
11707 as_bad (_("unknown ISA level %s"), name + 4);
11713 case 0: mips_opts.isa = file_mips_isa; break;
11714 case 1: mips_opts.isa = ISA_MIPS1; break;
11715 case 2: mips_opts.isa = ISA_MIPS2; break;
11716 case 3: mips_opts.isa = ISA_MIPS3; break;
11717 case 4: mips_opts.isa = ISA_MIPS4; break;
11718 case 5: mips_opts.isa = ISA_MIPS5; break;
11719 case 32: mips_opts.isa = ISA_MIPS32; break;
11720 case 64: mips_opts.isa = ISA_MIPS64; break;
11721 default: as_bad (_("unknown ISA level %s"), name + 4); break;
11724 else if (strcmp (name, "autoextend") == 0)
11725 mips_opts.noautoextend = 0;
11726 else if (strcmp (name, "noautoextend") == 0)
11727 mips_opts.noautoextend = 1;
11728 else if (strcmp (name, "push") == 0)
11730 struct mips_option_stack *s;
11732 s = (struct mips_option_stack *) xmalloc (sizeof *s);
11733 s->next = mips_opts_stack;
11734 s->options = mips_opts;
11735 mips_opts_stack = s;
11737 else if (strcmp (name, "pop") == 0)
11739 struct mips_option_stack *s;
11741 s = mips_opts_stack;
11743 as_bad (_(".set pop with no .set push"));
11746 /* If we're changing the reorder mode we need to handle
11747 delay slots correctly. */
11748 if (s->options.noreorder && ! mips_opts.noreorder)
11749 mips_emit_delays (true);
11750 else if (! s->options.noreorder && mips_opts.noreorder)
11752 if (prev_nop_frag != NULL)
11754 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11755 * (mips_opts.mips16 ? 2 : 4));
11756 prev_nop_frag = NULL;
11760 mips_opts = s->options;
11761 mips_opts_stack = s->next;
11767 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
11769 *input_line_pointer = ch;
11770 demand_empty_rest_of_line ();
11773 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11774 .option pic2. It means to generate SVR4 PIC calls. */
11777 s_abicalls (ignore)
11778 int ignore ATTRIBUTE_UNUSED;
11780 mips_pic = SVR4_PIC;
11781 if (USE_GLOBAL_POINTER_OPT)
11783 if (g_switch_seen && g_switch_value != 0)
11784 as_warn (_("-G may not be used with SVR4 PIC code"));
11785 g_switch_value = 0;
11787 bfd_set_gp_size (stdoutput, 0);
11788 demand_empty_rest_of_line ();
11791 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11792 PIC code. It sets the $gp register for the function based on the
11793 function address, which is in the register named in the argument.
11794 This uses a relocation against _gp_disp, which is handled specially
11795 by the linker. The result is:
11796 lui $gp,%hi(_gp_disp)
11797 addiu $gp,$gp,%lo(_gp_disp)
11798 addu $gp,$gp,.cpload argument
11799 The .cpload argument is normally $25 == $t9. */
11803 int ignore ATTRIBUTE_UNUSED;
11808 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11809 .cpload is ignored. */
11810 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
11816 /* .cpload should be in a .set noreorder section. */
11817 if (mips_opts.noreorder == 0)
11818 as_warn (_(".cpload not in noreorder section"));
11820 ex.X_op = O_symbol;
11821 ex.X_add_symbol = symbol_find_or_make ("_gp_disp");
11822 ex.X_op_symbol = NULL;
11823 ex.X_add_number = 0;
11825 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11826 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
11828 macro_build_lui (NULL, &icnt, &ex, mips_gp_register);
11829 macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j",
11830 mips_gp_register, mips_gp_register, (int) BFD_RELOC_LO16);
11832 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t",
11833 mips_gp_register, mips_gp_register, tc_get_register (0));
11835 demand_empty_rest_of_line ();
11838 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11839 .cpsetup $reg1, offset|$reg2, label
11841 If offset is given, this results in:
11842 sd $gp, offset($sp)
11843 lui $gp, %hi(%neg(%gp_rel(label)))
11844 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11845 daddu $gp, $gp, $reg1
11847 If $reg2 is given, this results in:
11848 daddu $reg2, $gp, $0
11849 lui $gp, %hi(%neg(%gp_rel(label)))
11850 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11851 daddu $gp, $gp, $reg1
11852 $reg1 is normally $25 == $t9. */
11855 int ignore ATTRIBUTE_UNUSED;
11857 expressionS ex_off;
11858 expressionS ex_sym;
11863 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
11864 We also need NewABI support. */
11865 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11871 reg1 = tc_get_register (0);
11872 SKIP_WHITESPACE ();
11873 if (*input_line_pointer != ',')
11875 as_bad (_("missing argument separator ',' for .cpsetup"));
11879 input_line_pointer++;
11880 SKIP_WHITESPACE ();
11881 if (*input_line_pointer == '$')
11882 mips_cpreturn_register = tc_get_register (0);
11884 mips_cpreturn_offset = get_absolute_expression ();
11885 SKIP_WHITESPACE ();
11886 if (*input_line_pointer != ',')
11888 as_bad (_("missing argument separator ',' for .cpsetup"));
11892 ++input_line_pointer;
11893 SKIP_WHITESPACE ();
11894 sym = input_line_pointer;
11895 while (ISALNUM (*input_line_pointer))
11896 ++input_line_pointer;
11897 *input_line_pointer = 0;
11899 ex_sym.X_op = O_symbol;
11900 ex_sym.X_add_symbol = symbol_find_or_make (sym);
11901 ex_sym.X_op_symbol = NULL;
11902 ex_sym.X_add_number = 0;
11904 if (mips_cpreturn_register == -1)
11906 ex_off.X_op = O_constant;
11907 ex_off.X_add_symbol = NULL;
11908 ex_off.X_op_symbol = NULL;
11909 ex_off.X_add_number = mips_cpreturn_offset;
11911 macro_build ((char *) NULL, &icnt, &ex_off, "sd", "t,o(b)",
11912 mips_gp_register, (int) BFD_RELOC_LO16, SP);
11915 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu",
11916 "d,v,t", mips_cpreturn_register, mips_gp_register, 0);
11918 macro_build ((char *) NULL, &icnt, &ex_sym, "lui", "t,u", mips_gp_register,
11919 (int) BFD_RELOC_GPREL16);
11920 fix_new (frag_now, prev_insn_where, 0, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
11921 fix_new (frag_now, prev_insn_where, 0, NULL, 0, 0, BFD_RELOC_HI16_S);
11922 macro_build ((char *) NULL, &icnt, &ex_sym, "addiu", "t,r,j",
11923 mips_gp_register, mips_gp_register, (int) BFD_RELOC_GPREL16);
11924 fix_new (frag_now, prev_insn_where, 0, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
11925 fix_new (frag_now, prev_insn_where, 0, NULL, 0, 0, BFD_RELOC_LO16);
11926 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
11927 HAVE_64BIT_ADDRESSES ? "daddu" : "addu", "d,v,t",
11928 mips_gp_register, mips_gp_register, reg1);
11930 demand_empty_rest_of_line ();
11935 int ignore ATTRIBUTE_UNUSED;
11937 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11938 .cplocal is ignored. */
11939 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11945 mips_gp_register = tc_get_register (0);
11948 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11949 offset from $sp. The offset is remembered, and after making a PIC
11950 call $gp is restored from that location. */
11953 s_cprestore (ignore)
11954 int ignore ATTRIBUTE_UNUSED;
11959 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11960 .cprestore is ignored. */
11961 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
11967 mips_cprestore_offset = get_absolute_expression ();
11968 mips_cprestore_valid = 1;
11970 ex.X_op = O_constant;
11971 ex.X_add_symbol = NULL;
11972 ex.X_op_symbol = NULL;
11973 ex.X_add_number = mips_cprestore_offset;
11975 macro_build ((char *) NULL, &icnt, &ex, HAVE_32BIT_ADDRESSES ? "sw" : "sd",
11976 "t,o(b)", mips_gp_register, (int) BFD_RELOC_LO16, SP);
11978 demand_empty_rest_of_line ();
11981 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
11982 was given in the preceeding .gpsetup, it results in:
11983 ld $gp, offset($sp)
11985 If a register $reg2 was given there, it results in:
11986 daddiu $gp, $gp, $reg2
11989 s_cpreturn (ignore)
11990 int ignore ATTRIBUTE_UNUSED;
11995 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
11996 We also need NewABI support. */
11997 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12003 if (mips_cpreturn_register == -1)
12005 ex.X_op = O_constant;
12006 ex.X_add_symbol = NULL;
12007 ex.X_op_symbol = NULL;
12008 ex.X_add_number = mips_cpreturn_offset;
12010 macro_build ((char *) NULL, &icnt, &ex, "ld", "t,o(b)",
12011 mips_gp_register, (int) BFD_RELOC_LO16, SP);
12014 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu",
12015 "d,v,t", mips_gp_register, mips_cpreturn_register, 0);
12017 demand_empty_rest_of_line ();
12020 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12021 code. It sets the offset to use in gp_rel relocations. */
12025 int ignore ATTRIBUTE_UNUSED;
12027 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12028 We also need NewABI support. */
12029 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12035 mips_gprel_offset = get_absolute_expression ();
12037 demand_empty_rest_of_line ();
12040 /* Handle the .gpword pseudo-op. This is used when generating PIC
12041 code. It generates a 32 bit GP relative reloc. */
12045 int ignore ATTRIBUTE_UNUSED;
12051 /* When not generating PIC code, this is treated as .word. */
12052 if (mips_pic != SVR4_PIC)
12058 label = insn_labels != NULL ? insn_labels->label : NULL;
12059 mips_emit_delays (true);
12061 mips_align (2, 0, label);
12062 mips_clear_insn_labels ();
12066 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12068 as_bad (_("Unsupported use of .gpword"));
12069 ignore_rest_of_line ();
12073 md_number_to_chars (p, (valueT) 0, 4);
12074 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, false,
12075 BFD_RELOC_GPREL32);
12077 demand_empty_rest_of_line ();
12080 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12081 tables in SVR4 PIC code. */
12085 int ignore ATTRIBUTE_UNUSED;
12090 /* This is ignored when not generating SVR4 PIC code or if this is NewABI
12092 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12098 /* Add $gp to the register named as an argument. */
12099 reg = tc_get_register (0);
12100 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
12101 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
12102 "d,v,t", reg, reg, mips_gp_register);
12104 demand_empty_rest_of_line ();
12107 /* Handle the .insn pseudo-op. This marks instruction labels in
12108 mips16 mode. This permits the linker to handle them specially,
12109 such as generating jalx instructions when needed. We also make
12110 them odd for the duration of the assembly, in order to generate the
12111 right sort of code. We will make them even in the adjust_symtab
12112 routine, while leaving them marked. This is convenient for the
12113 debugger and the disassembler. The linker knows to make them odd
12118 int ignore ATTRIBUTE_UNUSED;
12120 mips16_mark_labels ();
12122 demand_empty_rest_of_line ();
12125 /* Handle a .stabn directive. We need these in order to mark a label
12126 as being a mips16 text label correctly. Sometimes the compiler
12127 will emit a label, followed by a .stabn, and then switch sections.
12128 If the label and .stabn are in mips16 mode, then the label is
12129 really a mips16 text label. */
12136 mips16_mark_labels ();
12141 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12145 s_mips_weakext (ignore)
12146 int ignore ATTRIBUTE_UNUSED;
12153 name = input_line_pointer;
12154 c = get_symbol_end ();
12155 symbolP = symbol_find_or_make (name);
12156 S_SET_WEAK (symbolP);
12157 *input_line_pointer = c;
12159 SKIP_WHITESPACE ();
12161 if (! is_end_of_line[(unsigned char) *input_line_pointer])
12163 if (S_IS_DEFINED (symbolP))
12165 as_bad ("ignoring attempt to redefine symbol %s",
12166 S_GET_NAME (symbolP));
12167 ignore_rest_of_line ();
12171 if (*input_line_pointer == ',')
12173 ++input_line_pointer;
12174 SKIP_WHITESPACE ();
12178 if (exp.X_op != O_symbol)
12180 as_bad ("bad .weakext directive");
12181 ignore_rest_of_line ();
12184 symbol_set_value_expression (symbolP, &exp);
12187 demand_empty_rest_of_line ();
12190 /* Parse a register string into a number. Called from the ECOFF code
12191 to parse .frame. The argument is non-zero if this is the frame
12192 register, so that we can record it in mips_frame_reg. */
12195 tc_get_register (frame)
12200 SKIP_WHITESPACE ();
12201 if (*input_line_pointer++ != '$')
12203 as_warn (_("expected `$'"));
12206 else if (ISDIGIT (*input_line_pointer))
12208 reg = get_absolute_expression ();
12209 if (reg < 0 || reg >= 32)
12211 as_warn (_("Bad register number"));
12217 if (strncmp (input_line_pointer, "ra", 2) == 0)
12219 else if (strncmp (input_line_pointer, "fp", 2) == 0)
12221 else if (strncmp (input_line_pointer, "sp", 2) == 0)
12223 else if (strncmp (input_line_pointer, "gp", 2) == 0)
12225 else if (strncmp (input_line_pointer, "at", 2) == 0)
12229 as_warn (_("Unrecognized register name"));
12232 input_line_pointer += 2;
12236 mips_frame_reg = reg != 0 ? reg : SP;
12237 mips_frame_reg_valid = 1;
12238 mips_cprestore_valid = 0;
12244 md_section_align (seg, addr)
12248 int align = bfd_get_section_alignment (stdoutput, seg);
12251 /* We don't need to align ELF sections to the full alignment.
12252 However, Irix 5 may prefer that we align them at least to a 16
12253 byte boundary. We don't bother to align the sections if we are
12254 targeted for an embedded system. */
12255 if (strcmp (TARGET_OS, "elf") == 0)
12261 return ((addr + (1 << align) - 1) & (-1 << align));
12264 /* Utility routine, called from above as well. If called while the
12265 input file is still being read, it's only an approximation. (For
12266 example, a symbol may later become defined which appeared to be
12267 undefined earlier.) */
12270 nopic_need_relax (sym, before_relaxing)
12272 int before_relaxing;
12277 if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0)
12279 const char *symname;
12282 /* Find out whether this symbol can be referenced off the $gp
12283 register. It can be if it is smaller than the -G size or if
12284 it is in the .sdata or .sbss section. Certain symbols can
12285 not be referenced off the $gp, although it appears as though
12287 symname = S_GET_NAME (sym);
12288 if (symname != (const char *) NULL
12289 && (strcmp (symname, "eprol") == 0
12290 || strcmp (symname, "etext") == 0
12291 || strcmp (symname, "_gp") == 0
12292 || strcmp (symname, "edata") == 0
12293 || strcmp (symname, "_fbss") == 0
12294 || strcmp (symname, "_fdata") == 0
12295 || strcmp (symname, "_ftext") == 0
12296 || strcmp (symname, "end") == 0
12297 || strcmp (symname, "_gp_disp") == 0))
12299 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
12301 #ifndef NO_ECOFF_DEBUGGING
12302 || (symbol_get_obj (sym)->ecoff_extern_size != 0
12303 && (symbol_get_obj (sym)->ecoff_extern_size
12304 <= g_switch_value))
12306 /* We must defer this decision until after the whole
12307 file has been read, since there might be a .extern
12308 after the first use of this symbol. */
12309 || (before_relaxing
12310 #ifndef NO_ECOFF_DEBUGGING
12311 && symbol_get_obj (sym)->ecoff_extern_size == 0
12313 && S_GET_VALUE (sym) == 0)
12314 || (S_GET_VALUE (sym) != 0
12315 && S_GET_VALUE (sym) <= g_switch_value)))
12319 const char *segname;
12321 segname = segment_name (S_GET_SEGMENT (sym));
12322 assert (strcmp (segname, ".lit8") != 0
12323 && strcmp (segname, ".lit4") != 0);
12324 change = (strcmp (segname, ".sdata") != 0
12325 && strcmp (segname, ".sbss") != 0
12326 && strncmp (segname, ".sdata.", 7) != 0
12327 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
12332 /* We are not optimizing for the $gp register. */
12336 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12337 extended opcode. SEC is the section the frag is in. */
12340 mips16_extended_frag (fragp, sec, stretch)
12346 register const struct mips16_immed_operand *op;
12348 int mintiny, maxtiny;
12352 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
12354 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
12357 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
12358 op = mips16_immed_operands;
12359 while (op->type != type)
12362 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
12367 if (type == '<' || type == '>' || type == '[' || type == ']')
12370 maxtiny = 1 << op->nbits;
12375 maxtiny = (1 << op->nbits) - 1;
12380 mintiny = - (1 << (op->nbits - 1));
12381 maxtiny = (1 << (op->nbits - 1)) - 1;
12384 sym_frag = symbol_get_frag (fragp->fr_symbol);
12385 val = S_GET_VALUE (fragp->fr_symbol);
12386 symsec = S_GET_SEGMENT (fragp->fr_symbol);
12392 /* We won't have the section when we are called from
12393 mips_relax_frag. However, we will always have been called
12394 from md_estimate_size_before_relax first. If this is a
12395 branch to a different section, we mark it as such. If SEC is
12396 NULL, and the frag is not marked, then it must be a branch to
12397 the same section. */
12400 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
12405 /* Must have been called from md_estimate_size_before_relax. */
12408 fragp->fr_subtype =
12409 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12411 /* FIXME: We should support this, and let the linker
12412 catch branches and loads that are out of range. */
12413 as_bad_where (fragp->fr_file, fragp->fr_line,
12414 _("unsupported PC relative reference to different section"));
12418 if (fragp != sym_frag && sym_frag->fr_address == 0)
12419 /* Assume non-extended on the first relaxation pass.
12420 The address we have calculated will be bogus if this is
12421 a forward branch to another frag, as the forward frag
12422 will have fr_address == 0. */
12426 /* In this case, we know for sure that the symbol fragment is in
12427 the same section. If the relax_marker of the symbol fragment
12428 differs from the relax_marker of this fragment, we have not
12429 yet adjusted the symbol fragment fr_address. We want to add
12430 in STRETCH in order to get a better estimate of the address.
12431 This particularly matters because of the shift bits. */
12433 && sym_frag->relax_marker != fragp->relax_marker)
12437 /* Adjust stretch for any alignment frag. Note that if have
12438 been expanding the earlier code, the symbol may be
12439 defined in what appears to be an earlier frag. FIXME:
12440 This doesn't handle the fr_subtype field, which specifies
12441 a maximum number of bytes to skip when doing an
12443 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
12445 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
12448 stretch = - ((- stretch)
12449 & ~ ((1 << (int) f->fr_offset) - 1));
12451 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
12460 addr = fragp->fr_address + fragp->fr_fix;
12462 /* The base address rules are complicated. The base address of
12463 a branch is the following instruction. The base address of a
12464 PC relative load or add is the instruction itself, but if it
12465 is in a delay slot (in which case it can not be extended) use
12466 the address of the instruction whose delay slot it is in. */
12467 if (type == 'p' || type == 'q')
12471 /* If we are currently assuming that this frag should be
12472 extended, then, the current address is two bytes
12474 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12477 /* Ignore the low bit in the target, since it will be set
12478 for a text label. */
12479 if ((val & 1) != 0)
12482 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
12484 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
12487 val -= addr & ~ ((1 << op->shift) - 1);
12489 /* Branch offsets have an implicit 0 in the lowest bit. */
12490 if (type == 'p' || type == 'q')
12493 /* If any of the shifted bits are set, we must use an extended
12494 opcode. If the address depends on the size of this
12495 instruction, this can lead to a loop, so we arrange to always
12496 use an extended opcode. We only check this when we are in
12497 the main relaxation loop, when SEC is NULL. */
12498 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
12500 fragp->fr_subtype =
12501 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12505 /* If we are about to mark a frag as extended because the value
12506 is precisely maxtiny + 1, then there is a chance of an
12507 infinite loop as in the following code:
12512 In this case when the la is extended, foo is 0x3fc bytes
12513 away, so the la can be shrunk, but then foo is 0x400 away, so
12514 the la must be extended. To avoid this loop, we mark the
12515 frag as extended if it was small, and is about to become
12516 extended with a value of maxtiny + 1. */
12517 if (val == ((maxtiny + 1) << op->shift)
12518 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
12521 fragp->fr_subtype =
12522 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12526 else if (symsec != absolute_section && sec != NULL)
12527 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
12529 if ((val & ((1 << op->shift) - 1)) != 0
12530 || val < (mintiny << op->shift)
12531 || val > (maxtiny << op->shift))
12537 /* Estimate the size of a frag before relaxing. Unless this is the
12538 mips16, we are not really relaxing here, and the final size is
12539 encoded in the subtype information. For the mips16, we have to
12540 decide whether we are using an extended opcode or not. */
12543 md_estimate_size_before_relax (fragp, segtype)
12548 boolean linkonce = false;
12550 if (RELAX_MIPS16_P (fragp->fr_subtype))
12551 /* We don't want to modify the EXTENDED bit here; it might get us
12552 into infinite loops. We change it only in mips_relax_frag(). */
12553 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
12555 if (mips_pic == NO_PIC)
12557 change = nopic_need_relax (fragp->fr_symbol, 0);
12559 else if (mips_pic == SVR4_PIC)
12564 sym = fragp->fr_symbol;
12566 /* Handle the case of a symbol equated to another symbol. */
12567 while (symbol_equated_reloc_p (sym))
12571 /* It's possible to get a loop here in a badly written
12573 n = symbol_get_value_expression (sym)->X_add_symbol;
12579 symsec = S_GET_SEGMENT (sym);
12581 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12582 if (symsec != segtype && ! S_IS_LOCAL (sym))
12584 if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE)
12588 /* The GNU toolchain uses an extension for ELF: a section
12589 beginning with the magic string .gnu.linkonce is a linkonce
12591 if (strncmp (segment_name (symsec), ".gnu.linkonce",
12592 sizeof ".gnu.linkonce" - 1) == 0)
12596 /* This must duplicate the test in adjust_reloc_syms. */
12597 change = (symsec != &bfd_und_section
12598 && symsec != &bfd_abs_section
12599 && ! bfd_is_com_section (symsec)
12602 /* A global or weak symbol is treated as external. */
12603 && (OUTPUT_FLAVOR != bfd_target_elf_flavour
12604 || (! S_IS_WEAK (sym)
12605 && (! S_IS_EXTERN (sym) || mips_pic == EMBEDDED_PIC)))
12614 /* Record the offset to the first reloc in the fr_opcode field.
12615 This lets md_convert_frag and tc_gen_reloc know that the code
12616 must be expanded. */
12617 fragp->fr_opcode = (fragp->fr_literal
12619 - RELAX_OLD (fragp->fr_subtype)
12620 + RELAX_RELOC1 (fragp->fr_subtype));
12621 /* FIXME: This really needs as_warn_where. */
12622 if (RELAX_WARN (fragp->fr_subtype))
12623 as_warn (_("AT used after \".set noat\" or macro used after "
12624 "\".set nomacro\""));
12626 return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype);
12632 /* This is called to see whether a reloc against a defined symbol
12633 should be converted into a reloc against a section. Don't adjust
12634 MIPS16 jump relocations, so we don't have to worry about the format
12635 of the offset in the .o file. Don't adjust relocations against
12636 mips16 symbols, so that the linker can find them if it needs to set
12640 mips_fix_adjustable (fixp)
12644 /* Prevent all adjustments to global symbols. */
12645 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
12646 && mips_pic != EMBEDDED_PIC
12647 && (S_IS_EXTERN (fixp->fx_addsy) || S_IS_WEAK (fixp->fx_addsy)))
12650 if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
12652 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12653 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12655 if (fixp->fx_addsy == NULL)
12658 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
12659 && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
12660 && fixp->fx_subsy == NULL)
12666 /* Translate internal representation of relocation info to BFD target
12670 tc_gen_reloc (section, fixp)
12671 asection *section ATTRIBUTE_UNUSED;
12674 static arelent *retval[4];
12676 bfd_reloc_code_real_type code;
12678 reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent));
12681 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
12682 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
12683 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
12685 if (mips_pic == EMBEDDED_PIC
12686 && SWITCH_TABLE (fixp))
12688 /* For a switch table entry we use a special reloc. The addend
12689 is actually the difference between the reloc address and the
12691 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
12692 if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour)
12693 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
12694 fixp->fx_r_type = BFD_RELOC_GPREL32;
12696 else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16)
12698 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
12699 reloc->addend = fixp->fx_addnumber;
12702 /* We use a special addend for an internal RELLO reloc. */
12703 if (symbol_section_p (fixp->fx_addsy))
12704 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
12706 reloc->addend = fixp->fx_addnumber + reloc->address;
12709 else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
12711 assert (fixp->fx_next != NULL
12712 && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16);
12714 /* The reloc is relative to the RELLO; adjust the addend
12716 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
12717 reloc->addend = fixp->fx_next->fx_addnumber;
12720 /* We use a special addend for an internal RELHI reloc. */
12721 if (symbol_section_p (fixp->fx_addsy))
12722 reloc->addend = (fixp->fx_next->fx_frag->fr_address
12723 + fixp->fx_next->fx_where
12724 - S_GET_VALUE (fixp->fx_subsy));
12726 reloc->addend = (fixp->fx_addnumber
12727 + fixp->fx_next->fx_frag->fr_address
12728 + fixp->fx_next->fx_where);
12731 else if (fixp->fx_pcrel == 0 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
12732 reloc->addend = fixp->fx_addnumber;
12735 if (OUTPUT_FLAVOR != bfd_target_aout_flavour)
12736 /* A gruesome hack which is a result of the gruesome gas reloc
12738 reloc->addend = reloc->address;
12740 reloc->addend = -reloc->address;
12743 /* If this is a variant frag, we may need to adjust the existing
12744 reloc and generate a new one. */
12745 if (fixp->fx_frag->fr_opcode != NULL
12746 && (fixp->fx_r_type == BFD_RELOC_GPREL16
12747 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
12748 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16
12749 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
12750 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16
12751 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
12752 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)
12757 assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype));
12759 /* If this is not the last reloc in this frag, then we have two
12760 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
12761 CALL_HI16/CALL_LO16, both of which are being replaced. Let
12762 the second one handle all of them. */
12763 if (fixp->fx_next != NULL
12764 && fixp->fx_frag == fixp->fx_next->fx_frag)
12766 assert ((fixp->fx_r_type == BFD_RELOC_GPREL16
12767 && fixp->fx_next->fx_r_type == BFD_RELOC_GPREL16)
12768 || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
12769 && (fixp->fx_next->fx_r_type
12770 == BFD_RELOC_MIPS_GOT_LO16))
12771 || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
12772 && (fixp->fx_next->fx_r_type
12773 == BFD_RELOC_MIPS_CALL_LO16)));
12778 fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal;
12779 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
12780 reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent));
12782 reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
12783 *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
12784 reloc2->address = (reloc->address
12785 + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype)
12786 - RELAX_RELOC1 (fixp->fx_frag->fr_subtype)));
12787 reloc2->addend = fixp->fx_addnumber;
12788 reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16);
12789 assert (reloc2->howto != NULL);
12791 if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype))
12795 reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent));
12798 reloc3->address += 4;
12801 if (mips_pic == NO_PIC)
12803 assert (fixp->fx_r_type == BFD_RELOC_GPREL16);
12804 fixp->fx_r_type = BFD_RELOC_HI16_S;
12806 else if (mips_pic == SVR4_PIC)
12808 switch (fixp->fx_r_type)
12812 case BFD_RELOC_MIPS_GOT16:
12814 case BFD_RELOC_MIPS_CALL16:
12815 case BFD_RELOC_MIPS_GOT_LO16:
12816 case BFD_RELOC_MIPS_CALL_LO16:
12817 fixp->fx_r_type = BFD_RELOC_MIPS_GOT16;
12825 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
12826 entry to be used in the relocation's section offset. */
12827 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12829 reloc->address = reloc->addend;
12833 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
12834 fixup_segment converted a non-PC relative reloc into a PC
12835 relative reloc. In such a case, we need to convert the reloc
12837 code = fixp->fx_r_type;
12838 if (fixp->fx_pcrel)
12843 code = BFD_RELOC_8_PCREL;
12846 code = BFD_RELOC_16_PCREL;
12849 code = BFD_RELOC_32_PCREL;
12852 code = BFD_RELOC_64_PCREL;
12854 case BFD_RELOC_8_PCREL:
12855 case BFD_RELOC_16_PCREL:
12856 case BFD_RELOC_32_PCREL:
12857 case BFD_RELOC_64_PCREL:
12858 case BFD_RELOC_16_PCREL_S2:
12859 case BFD_RELOC_PCREL_HI16_S:
12860 case BFD_RELOC_PCREL_LO16:
12863 as_bad_where (fixp->fx_file, fixp->fx_line,
12864 _("Cannot make %s relocation PC relative"),
12865 bfd_get_reloc_code_name (code));
12870 /* md_apply_fix3 has a double-subtraction hack to get
12871 bfd_install_relocation to behave nicely. GPREL relocations are
12872 handled correctly without this hack, so undo it here. We can't
12873 stop md_apply_fix3 from subtracting twice in the first place since
12874 the fake addend is required for variant frags above. */
12875 if (fixp->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour
12876 && code == BFD_RELOC_GPREL16
12877 && reloc->addend != 0
12878 && mips_need_elf_addend_fixup (fixp))
12879 reloc->addend += S_GET_VALUE (fixp->fx_addsy);
12882 /* To support a PC relative reloc when generating embedded PIC code
12883 for ECOFF, we use a Cygnus extension. We check for that here to
12884 make sure that we don't let such a reloc escape normally. */
12885 if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
12886 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
12887 && code == BFD_RELOC_16_PCREL_S2
12888 && mips_pic != EMBEDDED_PIC)
12889 reloc->howto = NULL;
12891 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
12893 if (reloc->howto == NULL)
12895 as_bad_where (fixp->fx_file, fixp->fx_line,
12896 _("Can not represent %s relocation in this object file format"),
12897 bfd_get_reloc_code_name (code));
12904 /* Relax a machine dependent frag. This returns the amount by which
12905 the current size of the frag should change. */
12908 mips_relax_frag (fragp, stretch)
12912 if (! RELAX_MIPS16_P (fragp->fr_subtype))
12915 if (mips16_extended_frag (fragp, NULL, stretch))
12917 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12919 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
12924 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12926 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
12933 /* Convert a machine dependent frag. */
12936 md_convert_frag (abfd, asec, fragp)
12937 bfd *abfd ATTRIBUTE_UNUSED;
12944 if (RELAX_MIPS16_P (fragp->fr_subtype))
12947 register const struct mips16_immed_operand *op;
12948 boolean small, ext;
12951 unsigned long insn;
12952 boolean use_extend;
12953 unsigned short extend;
12955 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
12956 op = mips16_immed_operands;
12957 while (op->type != type)
12960 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12971 resolve_symbol_value (fragp->fr_symbol);
12972 val = S_GET_VALUE (fragp->fr_symbol);
12977 addr = fragp->fr_address + fragp->fr_fix;
12979 /* The rules for the base address of a PC relative reloc are
12980 complicated; see mips16_extended_frag. */
12981 if (type == 'p' || type == 'q')
12986 /* Ignore the low bit in the target, since it will be
12987 set for a text label. */
12988 if ((val & 1) != 0)
12991 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
12993 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
12996 addr &= ~ (addressT) ((1 << op->shift) - 1);
12999 /* Make sure the section winds up with the alignment we have
13002 record_alignment (asec, op->shift);
13006 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
13007 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
13008 as_warn_where (fragp->fr_file, fragp->fr_line,
13009 _("extended instruction in delay slot"));
13011 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
13013 if (target_big_endian)
13014 insn = bfd_getb16 (buf);
13016 insn = bfd_getl16 (buf);
13018 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
13019 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
13020 small, ext, &insn, &use_extend, &extend);
13024 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
13025 fragp->fr_fix += 2;
13029 md_number_to_chars ((char *) buf, insn, 2);
13030 fragp->fr_fix += 2;
13035 if (fragp->fr_opcode == NULL)
13038 old = RELAX_OLD (fragp->fr_subtype);
13039 new = RELAX_NEW (fragp->fr_subtype);
13040 fixptr = fragp->fr_literal + fragp->fr_fix;
13043 memcpy (fixptr - old, fixptr, new);
13045 fragp->fr_fix += new - old;
13051 /* This function is called after the relocs have been generated.
13052 We've been storing mips16 text labels as odd. Here we convert them
13053 back to even for the convenience of the debugger. */
13056 mips_frob_file_after_relocs ()
13059 unsigned int count, i;
13061 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
13064 syms = bfd_get_outsymbols (stdoutput);
13065 count = bfd_get_symcount (stdoutput);
13066 for (i = 0; i < count; i++, syms++)
13068 if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16
13069 && ((*syms)->value & 1) != 0)
13071 (*syms)->value &= ~1;
13072 /* If the symbol has an odd size, it was probably computed
13073 incorrectly, so adjust that as well. */
13074 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
13075 ++elf_symbol (*syms)->internal_elf_sym.st_size;
13082 /* This function is called whenever a label is defined. It is used
13083 when handling branch delays; if a branch has a label, we assume we
13084 can not move it. */
13087 mips_define_label (sym)
13090 struct insn_label_list *l;
13092 if (free_insn_labels == NULL)
13093 l = (struct insn_label_list *) xmalloc (sizeof *l);
13096 l = free_insn_labels;
13097 free_insn_labels = l->next;
13101 l->next = insn_labels;
13105 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13107 /* Some special processing for a MIPS ELF file. */
13110 mips_elf_final_processing ()
13112 /* Write out the register information. */
13113 if (file_mips_abi != N64_ABI)
13117 s.ri_gprmask = mips_gprmask;
13118 s.ri_cprmask[0] = mips_cprmask[0];
13119 s.ri_cprmask[1] = mips_cprmask[1];
13120 s.ri_cprmask[2] = mips_cprmask[2];
13121 s.ri_cprmask[3] = mips_cprmask[3];
13122 /* The gp_value field is set by the MIPS ELF backend. */
13124 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
13125 ((Elf32_External_RegInfo *)
13126 mips_regmask_frag));
13130 Elf64_Internal_RegInfo s;
13132 s.ri_gprmask = mips_gprmask;
13134 s.ri_cprmask[0] = mips_cprmask[0];
13135 s.ri_cprmask[1] = mips_cprmask[1];
13136 s.ri_cprmask[2] = mips_cprmask[2];
13137 s.ri_cprmask[3] = mips_cprmask[3];
13138 /* The gp_value field is set by the MIPS ELF backend. */
13140 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
13141 ((Elf64_External_RegInfo *)
13142 mips_regmask_frag));
13145 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13146 sort of BFD interface for this. */
13147 if (mips_any_noreorder)
13148 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
13149 if (mips_pic != NO_PIC)
13150 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
13152 /* Set MIPS ELF flags for ASEs. */
13153 #if 0 /* XXX FIXME */
13154 if (file_ase_mips3d)
13155 elf_elfheader (stdoutput)->e_flags |= ???;
13158 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
13160 /* Set the MIPS ELF ABI flags. */
13161 if (file_mips_abi == NO_ABI)
13163 else if (file_mips_abi == O32_ABI)
13164 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
13165 else if (file_mips_abi == O64_ABI)
13166 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
13167 else if (file_mips_abi == EABI_ABI)
13170 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
13172 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
13174 else if (file_mips_abi == N32_ABI)
13175 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
13177 /* Nothing to do for N64_ABI. */
13179 if (mips_32bitmode)
13180 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
13183 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13185 typedef struct proc {
13187 unsigned long reg_mask;
13188 unsigned long reg_offset;
13189 unsigned long fpreg_mask;
13190 unsigned long fpreg_offset;
13191 unsigned long frame_offset;
13192 unsigned long frame_reg;
13193 unsigned long pc_reg;
13196 static procS cur_proc;
13197 static procS *cur_proc_ptr;
13198 static int numprocs;
13200 /* Fill in an rs_align_code fragment. */
13203 mips_handle_align (fragp)
13206 if (fragp->fr_type != rs_align_code)
13209 if (mips_opts.mips16)
13211 static const unsigned char be_nop[] = { 0x65, 0x00 };
13212 static const unsigned char le_nop[] = { 0x00, 0x65 };
13217 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
13218 p = fragp->fr_literal + fragp->fr_fix;
13226 memcpy (p, (target_big_endian ? be_nop : le_nop), 2);
13230 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13241 /* check for premature end, nesting errors, etc */
13243 as_warn (_("missing .end at end of assembly"));
13252 if (*input_line_pointer == '-')
13254 ++input_line_pointer;
13257 if (!ISDIGIT (*input_line_pointer))
13258 as_bad (_("expected simple number"));
13259 if (input_line_pointer[0] == '0')
13261 if (input_line_pointer[1] == 'x')
13263 input_line_pointer += 2;
13264 while (ISXDIGIT (*input_line_pointer))
13267 val |= hex_value (*input_line_pointer++);
13269 return negative ? -val : val;
13273 ++input_line_pointer;
13274 while (ISDIGIT (*input_line_pointer))
13277 val |= *input_line_pointer++ - '0';
13279 return negative ? -val : val;
13282 if (!ISDIGIT (*input_line_pointer))
13284 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13285 *input_line_pointer, *input_line_pointer);
13286 as_warn (_("invalid number"));
13289 while (ISDIGIT (*input_line_pointer))
13292 val += *input_line_pointer++ - '0';
13294 return negative ? -val : val;
13297 /* The .file directive; just like the usual .file directive, but there
13298 is an initial number which is the ECOFF file index. */
13302 int x ATTRIBUTE_UNUSED;
13308 /* The .end directive. */
13312 int x ATTRIBUTE_UNUSED;
13317 /* Following functions need their own .frame and .cprestore directives. */
13318 mips_frame_reg_valid = 0;
13319 mips_cprestore_valid = 0;
13321 if (!is_end_of_line[(unsigned char) *input_line_pointer])
13324 demand_empty_rest_of_line ();
13329 #ifdef BFD_ASSEMBLER
13330 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
13335 if (now_seg != data_section && now_seg != bss_section)
13342 as_warn (_(".end not in text section"));
13346 as_warn (_(".end directive without a preceding .ent directive."));
13347 demand_empty_rest_of_line ();
13353 assert (S_GET_NAME (p));
13354 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym)))
13355 as_warn (_(".end symbol does not match .ent symbol."));
13358 as_warn (_(".end directive missing or unknown symbol"));
13360 #ifdef MIPS_STABS_ELF
13362 segT saved_seg = now_seg;
13363 subsegT saved_subseg = now_subseg;
13368 dot = frag_now_fix ();
13370 #ifdef md_flush_pending_output
13371 md_flush_pending_output ();
13375 subseg_set (pdr_seg, 0);
13377 /* Write the symbol. */
13378 exp.X_op = O_symbol;
13379 exp.X_add_symbol = p;
13380 exp.X_add_number = 0;
13381 emit_expr (&exp, 4);
13383 fragp = frag_more (7 * 4);
13385 md_number_to_chars (fragp, (valueT) cur_proc_ptr->reg_mask, 4);
13386 md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4);
13387 md_number_to_chars (fragp + 8, (valueT) cur_proc_ptr->fpreg_mask, 4);
13388 md_number_to_chars (fragp + 12, (valueT) cur_proc_ptr->fpreg_offset, 4);
13389 md_number_to_chars (fragp + 16, (valueT) cur_proc_ptr->frame_offset, 4);
13390 md_number_to_chars (fragp + 20, (valueT) cur_proc_ptr->frame_reg, 4);
13391 md_number_to_chars (fragp + 24, (valueT) cur_proc_ptr->pc_reg, 4);
13393 subseg_set (saved_seg, saved_subseg);
13395 #endif /* MIPS_STABS_ELF */
13397 cur_proc_ptr = NULL;
13400 /* The .aent and .ent directives. */
13409 symbolP = get_symbol ();
13410 if (*input_line_pointer == ',')
13411 ++input_line_pointer;
13412 SKIP_WHITESPACE ();
13413 if (ISDIGIT (*input_line_pointer)
13414 || *input_line_pointer == '-')
13417 #ifdef BFD_ASSEMBLER
13418 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
13423 if (now_seg != data_section && now_seg != bss_section)
13430 as_warn (_(".ent or .aent not in text section."));
13432 if (!aent && cur_proc_ptr)
13433 as_warn (_("missing .end"));
13437 /* This function needs its own .frame and .cprestore directives. */
13438 mips_frame_reg_valid = 0;
13439 mips_cprestore_valid = 0;
13441 cur_proc_ptr = &cur_proc;
13442 memset (cur_proc_ptr, '\0', sizeof (procS));
13444 cur_proc_ptr->isym = symbolP;
13446 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
13451 demand_empty_rest_of_line ();
13454 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13455 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13456 s_mips_frame is used so that we can set the PDR information correctly.
13457 We can't use the ecoff routines because they make reference to the ecoff
13458 symbol table (in the mdebug section). */
13461 s_mips_frame (ignore)
13462 int ignore ATTRIBUTE_UNUSED;
13464 #ifdef MIPS_STABS_ELF
13468 if (cur_proc_ptr == (procS *) NULL)
13470 as_warn (_(".frame outside of .ent"));
13471 demand_empty_rest_of_line ();
13475 cur_proc_ptr->frame_reg = tc_get_register (1);
13477 SKIP_WHITESPACE ();
13478 if (*input_line_pointer++ != ','
13479 || get_absolute_expression_and_terminator (&val) != ',')
13481 as_warn (_("Bad .frame directive"));
13482 --input_line_pointer;
13483 demand_empty_rest_of_line ();
13487 cur_proc_ptr->frame_offset = val;
13488 cur_proc_ptr->pc_reg = tc_get_register (0);
13490 demand_empty_rest_of_line ();
13493 #endif /* MIPS_STABS_ELF */
13496 /* The .fmask and .mask directives. If the mdebug section is present
13497 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13498 embedded targets, s_mips_mask is used so that we can set the PDR
13499 information correctly. We can't use the ecoff routines because they
13500 make reference to the ecoff symbol table (in the mdebug section). */
13503 s_mips_mask (reg_type)
13506 #ifdef MIPS_STABS_ELF
13509 if (cur_proc_ptr == (procS *) NULL)
13511 as_warn (_(".mask/.fmask outside of .ent"));
13512 demand_empty_rest_of_line ();
13516 if (get_absolute_expression_and_terminator (&mask) != ',')
13518 as_warn (_("Bad .mask/.fmask directive"));
13519 --input_line_pointer;
13520 demand_empty_rest_of_line ();
13524 off = get_absolute_expression ();
13526 if (reg_type == 'F')
13528 cur_proc_ptr->fpreg_mask = mask;
13529 cur_proc_ptr->fpreg_offset = off;
13533 cur_proc_ptr->reg_mask = mask;
13534 cur_proc_ptr->reg_offset = off;
13537 demand_empty_rest_of_line ();
13539 s_ignore (reg_type);
13540 #endif /* MIPS_STABS_ELF */
13543 /* The .loc directive. */
13554 assert (now_seg == text_section);
13556 lineno = get_number ();
13557 addroff = frag_now_fix ();
13559 symbolP = symbol_new ("", N_SLINE, addroff, frag_now);
13560 S_SET_TYPE (symbolP, N_SLINE);
13561 S_SET_OTHER (symbolP, 0);
13562 S_SET_DESC (symbolP, lineno);
13563 symbolP->sy_segment = now_seg;
13567 /* CPU name/ISA/number mapping table.
13569 Entries are grouped by type. The first matching CPU or ISA entry
13570 gets chosen by CPU or ISA, so it should be the 'canonical' name
13571 for that type. Entries after that within the type are sorted
13574 Case is ignored in comparison, so put the canonical entry in the
13575 appropriate case but everything else in lower case to ease eye pain. */
13576 static const struct mips_cpu_info mips_cpu_info_table[] =
13579 { "MIPS1", 1, ISA_MIPS1, CPU_R3000, },
13580 { "mips", 1, ISA_MIPS1, CPU_R3000, },
13583 { "MIPS2", 1, ISA_MIPS2, CPU_R6000, },
13586 { "MIPS3", 1, ISA_MIPS3, CPU_R4000, },
13589 { "MIPS4", 1, ISA_MIPS4, CPU_R8000, },
13592 { "MIPS5", 1, ISA_MIPS5, CPU_MIPS5, },
13593 { "Generic-MIPS5", 0, ISA_MIPS5, CPU_MIPS5, },
13596 { "MIPS32", 1, ISA_MIPS32, CPU_MIPS32, },
13597 { "mipsisa32", 0, ISA_MIPS32, CPU_MIPS32, },
13598 { "Generic-MIPS32", 0, ISA_MIPS32, CPU_MIPS32, },
13599 { "4kc", 0, ISA_MIPS32, CPU_MIPS32, },
13600 { "4km", 0, ISA_MIPS32, CPU_MIPS32, },
13601 { "4kp", 0, ISA_MIPS32, CPU_MIPS32, },
13603 /* For historical reasons. */
13604 { "MIPS64", 1, ISA_MIPS3, CPU_R4000, },
13607 { "mipsisa64", 1, ISA_MIPS64, CPU_MIPS64, },
13608 { "Generic-MIPS64", 0, ISA_MIPS64, CPU_MIPS64, },
13609 { "5kc", 0, ISA_MIPS64, CPU_MIPS64, },
13610 { "20kc", 0, ISA_MIPS64, CPU_MIPS64, },
13613 { "R2000", 0, ISA_MIPS1, CPU_R2000, },
13614 { "2000", 0, ISA_MIPS1, CPU_R2000, },
13615 { "2k", 0, ISA_MIPS1, CPU_R2000, },
13616 { "r2k", 0, ISA_MIPS1, CPU_R2000, },
13619 { "R3000", 0, ISA_MIPS1, CPU_R3000, },
13620 { "3000", 0, ISA_MIPS1, CPU_R3000, },
13621 { "3k", 0, ISA_MIPS1, CPU_R3000, },
13622 { "r3k", 0, ISA_MIPS1, CPU_R3000, },
13625 { "R3900", 0, ISA_MIPS1, CPU_R3900, },
13626 { "3900", 0, ISA_MIPS1, CPU_R3900, },
13627 { "mipstx39", 0, ISA_MIPS1, CPU_R3900, },
13630 { "R4000", 0, ISA_MIPS3, CPU_R4000, },
13631 { "4000", 0, ISA_MIPS3, CPU_R4000, },
13632 { "4k", 0, ISA_MIPS3, CPU_R4000, }, /* beware */
13633 { "r4k", 0, ISA_MIPS3, CPU_R4000, },
13636 { "R4010", 0, ISA_MIPS2, CPU_R4010, },
13637 { "4010", 0, ISA_MIPS2, CPU_R4010, },
13640 { "R4400", 0, ISA_MIPS3, CPU_R4400, },
13641 { "4400", 0, ISA_MIPS3, CPU_R4400, },
13644 { "R4600", 0, ISA_MIPS3, CPU_R4600, },
13645 { "4600", 0, ISA_MIPS3, CPU_R4600, },
13646 { "mips64orion", 0, ISA_MIPS3, CPU_R4600, },
13647 { "orion", 0, ISA_MIPS3, CPU_R4600, },
13650 { "R4650", 0, ISA_MIPS3, CPU_R4650, },
13651 { "4650", 0, ISA_MIPS3, CPU_R4650, },
13654 { "R6000", 0, ISA_MIPS2, CPU_R6000, },
13655 { "6000", 0, ISA_MIPS2, CPU_R6000, },
13656 { "6k", 0, ISA_MIPS2, CPU_R6000, },
13657 { "r6k", 0, ISA_MIPS2, CPU_R6000, },
13660 { "R8000", 0, ISA_MIPS4, CPU_R8000, },
13661 { "8000", 0, ISA_MIPS4, CPU_R8000, },
13662 { "8k", 0, ISA_MIPS4, CPU_R8000, },
13663 { "r8k", 0, ISA_MIPS4, CPU_R8000, },
13666 { "R10000", 0, ISA_MIPS4, CPU_R10000, },
13667 { "10000", 0, ISA_MIPS4, CPU_R10000, },
13668 { "10k", 0, ISA_MIPS4, CPU_R10000, },
13669 { "r10k", 0, ISA_MIPS4, CPU_R10000, },
13672 { "R12000", 0, ISA_MIPS4, CPU_R12000, },
13673 { "12000", 0, ISA_MIPS4, CPU_R12000, },
13674 { "12k", 0, ISA_MIPS4, CPU_R12000, },
13675 { "r12k", 0, ISA_MIPS4, CPU_R12000, },
13678 { "VR4100", 0, ISA_MIPS3, CPU_VR4100, },
13679 { "4100", 0, ISA_MIPS3, CPU_VR4100, },
13680 { "mips64vr4100", 0, ISA_MIPS3, CPU_VR4100, },
13681 { "r4100", 0, ISA_MIPS3, CPU_VR4100, },
13684 { "VR4111", 0, ISA_MIPS3, CPU_R4111, },
13685 { "4111", 0, ISA_MIPS3, CPU_R4111, },
13686 { "mips64vr4111", 0, ISA_MIPS3, CPU_R4111, },
13687 { "r4111", 0, ISA_MIPS3, CPU_R4111, },
13690 { "VR4300", 0, ISA_MIPS3, CPU_R4300, },
13691 { "4300", 0, ISA_MIPS3, CPU_R4300, },
13692 { "mips64vr4300", 0, ISA_MIPS3, CPU_R4300, },
13693 { "r4300", 0, ISA_MIPS3, CPU_R4300, },
13696 { "VR5000", 0, ISA_MIPS4, CPU_R5000, },
13697 { "5000", 0, ISA_MIPS4, CPU_R5000, },
13698 { "5k", 0, ISA_MIPS4, CPU_R5000, },
13699 { "mips64vr5000", 0, ISA_MIPS4, CPU_R5000, },
13700 { "r5000", 0, ISA_MIPS4, CPU_R5000, },
13701 { "r5200", 0, ISA_MIPS4, CPU_R5000, },
13702 { "rm5200", 0, ISA_MIPS4, CPU_R5000, },
13703 { "r5230", 0, ISA_MIPS4, CPU_R5000, },
13704 { "rm5230", 0, ISA_MIPS4, CPU_R5000, },
13705 { "r5231", 0, ISA_MIPS4, CPU_R5000, },
13706 { "rm5231", 0, ISA_MIPS4, CPU_R5000, },
13707 { "r5261", 0, ISA_MIPS4, CPU_R5000, },
13708 { "rm5261", 0, ISA_MIPS4, CPU_R5000, },
13709 { "r5721", 0, ISA_MIPS4, CPU_R5000, },
13710 { "rm5721", 0, ISA_MIPS4, CPU_R5000, },
13711 { "r5k", 0, ISA_MIPS4, CPU_R5000, },
13712 { "r7000", 0, ISA_MIPS4, CPU_R5000, },
13714 /* Broadcom SB-1 CPU */
13715 { "SB-1", 0, ISA_MIPS64, CPU_SB1, },
13716 { "sb-1250", 0, ISA_MIPS64, CPU_SB1, },
13717 { "sb1", 0, ISA_MIPS64, CPU_SB1, },
13718 { "sb1250", 0, ISA_MIPS64, CPU_SB1, },
13721 { NULL, 0, 0, 0, },
13724 static const struct mips_cpu_info *
13725 mips_cpu_info_from_name (name)
13730 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
13731 if (strcasecmp (name, mips_cpu_info_table[i].name) == 0)
13732 return (&mips_cpu_info_table[i]);
13737 static const struct mips_cpu_info *
13738 mips_cpu_info_from_isa (isa)
13743 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
13744 if (mips_cpu_info_table[i].is_isa
13745 && isa == mips_cpu_info_table[i].isa)
13746 return (&mips_cpu_info_table[i]);
13751 static const struct mips_cpu_info *
13752 mips_cpu_info_from_cpu (cpu)
13757 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
13758 if (!mips_cpu_info_table[i].is_isa
13759 && cpu == mips_cpu_info_table[i].cpu)
13760 return (&mips_cpu_info_table[i]);