1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 /* Allow override of standard little-endian ECOFF format. */
107 #ifndef ECOFF_LITTLE_FORMAT
108 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
111 extern int target_big_endian;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
116 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
124 /* The ABI to use. */
135 /* MIPS ABI we are using for this output file. */
136 static enum mips_abi_level mips_abi = NO_ABI;
138 /* Whether or not we have code that can call pic code. */
139 int mips_abicalls = FALSE;
141 /* This is the set of options which may be modified by the .set
142 pseudo-op. We use a struct so that .set push and .set pop are more
145 struct mips_set_options
147 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
148 if it has not been initialized. Changed by `.set mipsN', and the
149 -mipsN command line option, and the default CPU. */
151 /* Enabled Application Specific Extensions (ASEs). These are set to -1
152 if they have not been initialized. Changed by `.set <asename>', by
153 command line options, and based on the default architecture. */
156 /* Whether we are assembling for the mips16 processor. 0 if we are
157 not, 1 if we are, and -1 if the value has not been initialized.
158 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
159 -nomips16 command line options, and the default CPU. */
161 /* Non-zero if we should not reorder instructions. Changed by `.set
162 reorder' and `.set noreorder'. */
164 /* Non-zero if we should not permit the $at ($1) register to be used
165 in instructions. Changed by `.set at' and `.set noat'. */
167 /* Non-zero if we should warn when a macro instruction expands into
168 more than one machine instruction. Changed by `.set nomacro' and
170 int warn_about_macros;
171 /* Non-zero if we should not move instructions. Changed by `.set
172 move', `.set volatile', `.set nomove', and `.set novolatile'. */
174 /* Non-zero if we should not optimize branches by moving the target
175 of the branch into the delay slot. Actually, we don't perform
176 this optimization anyhow. Changed by `.set bopt' and `.set
179 /* Non-zero if we should not autoextend mips16 instructions.
180 Changed by `.set autoextend' and `.set noautoextend'. */
182 /* Restrict general purpose registers and floating point registers
183 to 32 bit. This is initially determined when -mgp32 or -mfp32
184 is passed but can changed if the assembler code uses .set mipsN. */
187 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
188 command line option, and the default CPU. */
192 /* True if -mgp32 was passed. */
193 static int file_mips_gp32 = -1;
195 /* True if -mfp32 was passed. */
196 static int file_mips_fp32 = -1;
198 /* This is the struct we use to hold the current set of options. Note
199 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
200 -1 to indicate that they have not been initialized. */
202 static struct mips_set_options mips_opts =
204 ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
207 /* These variables are filled in with the masks of registers used.
208 The object format code reads them and puts them in the appropriate
210 unsigned long mips_gprmask;
211 unsigned long mips_cprmask[4];
213 /* MIPS ISA we are using for this output file. */
214 static int file_mips_isa = ISA_UNKNOWN;
216 /* True if -mips16 was passed or implied by arguments passed on the
217 command line (e.g., by -march). */
218 static int file_ase_mips16;
220 /* True if -mips3d was passed or implied by arguments passed on the
221 command line (e.g., by -march). */
222 static int file_ase_mips3d;
224 /* True if -mdmx was passed or implied by arguments passed on the
225 command line (e.g., by -march). */
226 static int file_ase_mdmx;
228 /* The argument of the -march= flag. The architecture we are assembling. */
229 static int file_mips_arch = CPU_UNKNOWN;
230 static const char *mips_arch_string;
232 /* The argument of the -mtune= flag. The architecture for which we
234 static int mips_tune = CPU_UNKNOWN;
235 static const char *mips_tune_string;
237 /* True when generating 32-bit code for a 64-bit processor. */
238 static int mips_32bitmode = 0;
240 /* True if the given ABI requires 32-bit registers. */
241 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
243 /* Likewise 64-bit registers. */
244 #define ABI_NEEDS_64BIT_REGS(ABI) \
246 || (ABI) == N64_ABI \
249 /* Return true if ISA supports 64 bit gp register instructions. */
250 #define ISA_HAS_64BIT_REGS(ISA) ( \
252 || (ISA) == ISA_MIPS4 \
253 || (ISA) == ISA_MIPS5 \
254 || (ISA) == ISA_MIPS64 \
255 || (ISA) == ISA_MIPS64R2 \
258 /* Return true if ISA supports 64-bit right rotate (dror et al.)
260 #define ISA_HAS_DROR(ISA) ( \
261 (ISA) == ISA_MIPS64R2 \
264 /* Return true if ISA supports 32-bit right rotate (ror et al.)
266 #define ISA_HAS_ROR(ISA) ( \
267 (ISA) == ISA_MIPS32R2 \
268 || (ISA) == ISA_MIPS64R2 \
271 #define HAVE_32BIT_GPRS \
272 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
274 #define HAVE_32BIT_FPRS \
275 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
277 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
278 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
280 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
282 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
284 /* We can only have 64bit addresses if the object file format
286 #define HAVE_32BIT_ADDRESSES \
288 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
289 || ! HAVE_64BIT_OBJECTS) \
290 && mips_pic != EMBEDDED_PIC))
292 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
294 /* Addresses are loaded in different ways, depending on the address size
295 in use. The n32 ABI Documentation also mandates the use of additions
296 with overflow checking, but existing implementations don't follow it. */
297 #define ADDRESS_ADD_INSN \
298 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
300 #define ADDRESS_ADDI_INSN \
301 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
303 #define ADDRESS_LOAD_INSN \
304 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
306 #define ADDRESS_STORE_INSN \
307 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
309 /* Return true if the given CPU supports the MIPS16 ASE. */
310 #define CPU_HAS_MIPS16(cpu) \
311 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
312 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
314 /* Return true if the given CPU supports the MIPS3D ASE. */
315 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
318 /* Return true if the given CPU supports the MDMX ASE. */
319 #define CPU_HAS_MDMX(cpu) (FALSE \
322 /* True if CPU has a dror instruction. */
323 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
325 /* True if CPU has a ror instruction. */
326 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
328 /* Whether the processor uses hardware interlocks to protect
329 reads from the HI and LO registers, and thus does not
330 require nops to be inserted. */
332 #define hilo_interlocks (mips_opts.arch == CPU_R4010 \
333 || mips_opts.arch == CPU_VR5500 \
334 || mips_opts.arch == CPU_RM7000 \
335 || mips_opts.arch == CPU_SB1 \
338 /* Whether the processor uses hardware interlocks to protect reads
339 from the GPRs after they are loaded from memory, and thus does not
340 require nops to be inserted. This applies to instructions marked
341 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
343 #define gpr_interlocks \
344 (mips_opts.isa != ISA_MIPS1 \
345 || mips_opts.arch == CPU_VR5400 \
346 || mips_opts.arch == CPU_VR5500 \
347 || mips_opts.arch == CPU_R3900)
349 /* Whether the processor uses hardware interlocks to avoid delays
350 required by coprocessor instructions, and thus does not require
351 nops to be inserted. This applies to instructions marked
352 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
353 between instructions marked INSN_WRITE_COND_CODE and ones marked
354 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
355 levels I, II, and III. */
356 /* Itbl support may require additional care here. */
357 #define cop_interlocks \
358 ((mips_opts.isa != ISA_MIPS1 \
359 && mips_opts.isa != ISA_MIPS2 \
360 && mips_opts.isa != ISA_MIPS3) \
361 || mips_opts.arch == CPU_R4300 \
362 || mips_opts.arch == CPU_VR5400 \
363 || mips_opts.arch == CPU_VR5500 \
364 || mips_opts.arch == CPU_SB1 \
367 /* Whether the processor uses hardware interlocks to protect reads
368 from coprocessor registers after they are loaded from memory, and
369 thus does not require nops to be inserted. This applies to
370 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
371 requires at MIPS ISA level I. */
372 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
374 /* Is this a mfhi or mflo instruction? */
375 #define MF_HILO_INSN(PINFO) \
376 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
378 /* MIPS PIC level. */
380 enum mips_pic_level mips_pic;
382 /* 1 if we should generate 32 bit offsets from the $gp register in
383 SVR4_PIC mode. Currently has no meaning in other modes. */
384 static int mips_big_got = 0;
386 /* 1 if trap instructions should used for overflow rather than break
388 static int mips_trap = 0;
390 /* 1 if double width floating point constants should not be constructed
391 by assembling two single width halves into two single width floating
392 point registers which just happen to alias the double width destination
393 register. On some architectures this aliasing can be disabled by a bit
394 in the status register, and the setting of this bit cannot be determined
395 automatically at assemble time. */
396 static int mips_disable_float_construction;
398 /* Non-zero if any .set noreorder directives were used. */
400 static int mips_any_noreorder;
402 /* Non-zero if nops should be inserted when the register referenced in
403 an mfhi/mflo instruction is read in the next two instructions. */
404 static int mips_7000_hilo_fix;
406 /* The size of the small data section. */
407 static unsigned int g_switch_value = 8;
408 /* Whether the -G option was used. */
409 static int g_switch_seen = 0;
414 /* If we can determine in advance that GP optimization won't be
415 possible, we can skip the relaxation stuff that tries to produce
416 GP-relative references. This makes delay slot optimization work
419 This function can only provide a guess, but it seems to work for
420 gcc output. It needs to guess right for gcc, otherwise gcc
421 will put what it thinks is a GP-relative instruction in a branch
424 I don't know if a fix is needed for the SVR4_PIC mode. I've only
425 fixed it for the non-PIC mode. KR 95/04/07 */
426 static int nopic_need_relax (symbolS *, int);
428 /* handle of the OPCODE hash table */
429 static struct hash_control *op_hash = NULL;
431 /* The opcode hash table we use for the mips16. */
432 static struct hash_control *mips16_op_hash = NULL;
434 /* This array holds the chars that always start a comment. If the
435 pre-processor is disabled, these aren't very useful */
436 const char comment_chars[] = "#";
438 /* This array holds the chars that only start a comment at the beginning of
439 a line. If the line seems to have the form '# 123 filename'
440 .line and .file directives will appear in the pre-processed output */
441 /* Note that input_file.c hand checks for '#' at the beginning of the
442 first line of the input file. This is because the compiler outputs
443 #NO_APP at the beginning of its output. */
444 /* Also note that C style comments are always supported. */
445 const char line_comment_chars[] = "#";
447 /* This array holds machine specific line separator characters. */
448 const char line_separator_chars[] = ";";
450 /* Chars that can be used to separate mant from exp in floating point nums */
451 const char EXP_CHARS[] = "eE";
453 /* Chars that mean this number is a floating point constant */
456 const char FLT_CHARS[] = "rRsSfFdDxXpP";
458 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
459 changed in read.c . Ideally it shouldn't have to know about it at all,
460 but nothing is ideal around here.
463 static char *insn_error;
465 static int auto_align = 1;
467 /* When outputting SVR4 PIC code, the assembler needs to know the
468 offset in the stack frame from which to restore the $gp register.
469 This is set by the .cprestore pseudo-op, and saved in this
471 static offsetT mips_cprestore_offset = -1;
473 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
474 more optimizations, it can use a register value instead of a memory-saved
475 offset and even an other register than $gp as global pointer. */
476 static offsetT mips_cpreturn_offset = -1;
477 static int mips_cpreturn_register = -1;
478 static int mips_gp_register = GP;
479 static int mips_gprel_offset = 0;
481 /* Whether mips_cprestore_offset has been set in the current function
482 (or whether it has already been warned about, if not). */
483 static int mips_cprestore_valid = 0;
485 /* This is the register which holds the stack frame, as set by the
486 .frame pseudo-op. This is needed to implement .cprestore. */
487 static int mips_frame_reg = SP;
489 /* Whether mips_frame_reg has been set in the current function
490 (or whether it has already been warned about, if not). */
491 static int mips_frame_reg_valid = 0;
493 /* To output NOP instructions correctly, we need to keep information
494 about the previous two instructions. */
496 /* Whether we are optimizing. The default value of 2 means to remove
497 unneeded NOPs and swap branch instructions when possible. A value
498 of 1 means to not swap branches. A value of 0 means to always
500 static int mips_optimize = 2;
502 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
503 equivalent to seeing no -g option at all. */
504 static int mips_debug = 0;
506 /* The previous instruction. */
507 static struct mips_cl_insn prev_insn;
509 /* The instruction before prev_insn. */
510 static struct mips_cl_insn prev_prev_insn;
512 /* If we don't want information for prev_insn or prev_prev_insn, we
513 point the insn_mo field at this dummy integer. */
514 static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 };
516 /* Non-zero if prev_insn is valid. */
517 static int prev_insn_valid;
519 /* The frag for the previous instruction. */
520 static struct frag *prev_insn_frag;
522 /* The offset into prev_insn_frag for the previous instruction. */
523 static long prev_insn_where;
525 /* The reloc type for the previous instruction, if any. */
526 static bfd_reloc_code_real_type prev_insn_reloc_type[3];
528 /* The reloc for the previous instruction, if any. */
529 static fixS *prev_insn_fixp[3];
531 /* Non-zero if the previous instruction was in a delay slot. */
532 static int prev_insn_is_delay_slot;
534 /* Non-zero if the previous instruction was in a .set noreorder. */
535 static int prev_insn_unreordered;
537 /* Non-zero if the previous instruction uses an extend opcode (if
539 static int prev_insn_extended;
541 /* Non-zero if the previous previous instruction was in a .set
543 static int prev_prev_insn_unreordered;
545 /* If this is set, it points to a frag holding nop instructions which
546 were inserted before the start of a noreorder section. If those
547 nops turn out to be unnecessary, the size of the frag can be
549 static fragS *prev_nop_frag;
551 /* The number of nop instructions we created in prev_nop_frag. */
552 static int prev_nop_frag_holds;
554 /* The number of nop instructions that we know we need in
556 static int prev_nop_frag_required;
558 /* The number of instructions we've seen since prev_nop_frag. */
559 static int prev_nop_frag_since;
561 /* For ECOFF and ELF, relocations against symbols are done in two
562 parts, with a HI relocation and a LO relocation. Each relocation
563 has only 16 bits of space to store an addend. This means that in
564 order for the linker to handle carries correctly, it must be able
565 to locate both the HI and the LO relocation. This means that the
566 relocations must appear in order in the relocation table.
568 In order to implement this, we keep track of each unmatched HI
569 relocation. We then sort them so that they immediately precede the
570 corresponding LO relocation. */
575 struct mips_hi_fixup *next;
578 /* The section this fixup is in. */
582 /* The list of unmatched HI relocs. */
584 static struct mips_hi_fixup *mips_hi_fixup_list;
586 /* The frag containing the last explicit relocation operator.
587 Null if explicit relocations have not been used. */
589 static fragS *prev_reloc_op_frag;
591 /* Map normal MIPS register numbers to mips16 register numbers. */
593 #define X ILLEGAL_REG
594 static const int mips32_to_16_reg_map[] =
596 X, X, 2, 3, 4, 5, 6, 7,
597 X, X, X, X, X, X, X, X,
598 0, 1, X, X, X, X, X, X,
599 X, X, X, X, X, X, X, X
603 /* Map mips16 register numbers to normal MIPS register numbers. */
605 static const unsigned int mips16_to_32_reg_map[] =
607 16, 17, 2, 3, 4, 5, 6, 7
610 static int mips_fix_4122_bugs;
612 /* We don't relax branches by default, since this causes us to expand
613 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
614 fail to compute the offset before expanding the macro to the most
615 efficient expansion. */
617 static int mips_relax_branch;
619 /* The expansion of many macros depends on the type of symbol that
620 they refer to. For example, when generating position-dependent code,
621 a macro that refers to a symbol may have two different expansions,
622 one which uses GP-relative addresses and one which uses absolute
623 addresses. When generating SVR4-style PIC, a macro may have
624 different expansions for local and global symbols.
626 We handle these situations by generating both sequences and putting
627 them in variant frags. In position-dependent code, the first sequence
628 will be the GP-relative one and the second sequence will be the
629 absolute one. In SVR4 PIC, the first sequence will be for global
630 symbols and the second will be for local symbols.
632 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
633 SECOND are the lengths of the two sequences in bytes. These fields
634 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
635 the subtype has the following flags:
638 Set if it has been decided that we should use the second
639 sequence instead of the first.
642 Set in the first variant frag if the macro's second implementation
643 is longer than its first. This refers to the macro as a whole,
644 not an individual relaxation.
647 Set in the first variant frag if the macro appeared in a .set nomacro
648 block and if one alternative requires a warning but the other does not.
651 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
654 The frag's "opcode" points to the first fixup for relaxable code.
656 Relaxable macros are generated using a sequence such as:
658 relax_start (SYMBOL);
659 ... generate first expansion ...
661 ... generate second expansion ...
664 The code and fixups for the unwanted alternative are discarded
665 by md_convert_frag. */
666 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
668 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
669 #define RELAX_SECOND(X) ((X) & 0xff)
670 #define RELAX_USE_SECOND 0x10000
671 #define RELAX_SECOND_LONGER 0x20000
672 #define RELAX_NOMACRO 0x40000
673 #define RELAX_DELAY_SLOT 0x80000
675 /* Branch without likely bit. If label is out of range, we turn:
677 beq reg1, reg2, label
687 with the following opcode replacements:
694 bltzal <-> bgezal (with jal label instead of j label)
696 Even though keeping the delay slot instruction in the delay slot of
697 the branch would be more efficient, it would be very tricky to do
698 correctly, because we'd have to introduce a variable frag *after*
699 the delay slot instruction, and expand that instead. Let's do it
700 the easy way for now, even if the branch-not-taken case now costs
701 one additional instruction. Out-of-range branches are not supposed
702 to be common, anyway.
704 Branch likely. If label is out of range, we turn:
706 beql reg1, reg2, label
707 delay slot (annulled if branch not taken)
716 delay slot (executed only if branch taken)
719 It would be possible to generate a shorter sequence by losing the
720 likely bit, generating something like:
725 delay slot (executed only if branch taken)
737 bltzall -> bgezal (with jal label instead of j label)
738 bgezall -> bltzal (ditto)
741 but it's not clear that it would actually improve performance. */
742 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
745 | ((toofar) ? 1 : 0) \
747 | ((likely) ? 4 : 0) \
748 | ((uncond) ? 8 : 0)))
749 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
750 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
751 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
752 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
753 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
755 /* For mips16 code, we use an entirely different form of relaxation.
756 mips16 supports two versions of most instructions which take
757 immediate values: a small one which takes some small value, and a
758 larger one which takes a 16 bit value. Since branches also follow
759 this pattern, relaxing these values is required.
761 We can assemble both mips16 and normal MIPS code in a single
762 object. Therefore, we need to support this type of relaxation at
763 the same time that we support the relaxation described above. We
764 use the high bit of the subtype field to distinguish these cases.
766 The information we store for this type of relaxation is the
767 argument code found in the opcode file for this relocation, whether
768 the user explicitly requested a small or extended form, and whether
769 the relocation is in a jump or jal delay slot. That tells us the
770 size of the value, and how it should be stored. We also store
771 whether the fragment is considered to be extended or not. We also
772 store whether this is known to be a branch to a different section,
773 whether we have tried to relax this frag yet, and whether we have
774 ever extended a PC relative fragment because of a shift count. */
775 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
778 | ((small) ? 0x100 : 0) \
779 | ((ext) ? 0x200 : 0) \
780 | ((dslot) ? 0x400 : 0) \
781 | ((jal_dslot) ? 0x800 : 0))
782 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
783 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
784 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
785 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
786 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
787 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
788 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
789 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
790 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
791 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
792 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
793 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
795 /* Is the given value a sign-extended 32-bit value? */
796 #define IS_SEXT_32BIT_NUM(x) \
797 (((x) &~ (offsetT) 0x7fffffff) == 0 \
798 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
800 /* Is the given value a sign-extended 16-bit value? */
801 #define IS_SEXT_16BIT_NUM(x) \
802 (((x) &~ (offsetT) 0x7fff) == 0 \
803 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
806 /* Global variables used when generating relaxable macros. See the
807 comment above RELAX_ENCODE for more details about how relaxation
810 /* 0 if we're not emitting a relaxable macro.
811 1 if we're emitting the first of the two relaxation alternatives.
812 2 if we're emitting the second alternative. */
815 /* The first relaxable fixup in the current frag. (In other words,
816 the first fixup that refers to relaxable code.) */
819 /* sizes[0] says how many bytes of the first alternative are stored in
820 the current frag. Likewise sizes[1] for the second alternative. */
821 unsigned int sizes[2];
823 /* The symbol on which the choice of sequence depends. */
827 /* Global variables used to decide whether a macro needs a warning. */
829 /* True if the macro is in a branch delay slot. */
830 bfd_boolean delay_slot_p;
832 /* For relaxable macros, sizes[0] is the length of the first alternative
833 in bytes and sizes[1] is the length of the second alternative.
834 For non-relaxable macros, both elements give the length of the
836 unsigned int sizes[2];
838 /* The first variant frag for this macro. */
840 } mips_macro_warning;
842 /* Prototypes for static functions. */
844 #define internalError() \
845 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
847 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
849 static void append_insn
850 (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r);
851 static void mips_no_prev_insn (int);
852 static void mips16_macro_build
853 (expressionS *, const char *, const char *, va_list);
854 static void load_register (int, expressionS *, int);
855 static void macro_start (void);
856 static void macro_end (void);
857 static void macro (struct mips_cl_insn * ip);
858 static void mips16_macro (struct mips_cl_insn * ip);
859 #ifdef LOSING_COMPILER
860 static void macro2 (struct mips_cl_insn * ip);
862 static void mips_ip (char *str, struct mips_cl_insn * ip);
863 static void mips16_ip (char *str, struct mips_cl_insn * ip);
864 static void mips16_immed
865 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
866 unsigned long *, bfd_boolean *, unsigned short *);
867 static size_t my_getSmallExpression
868 (expressionS *, bfd_reloc_code_real_type *, char *);
869 static void my_getExpression (expressionS *, char *);
870 static void s_align (int);
871 static void s_change_sec (int);
872 static void s_change_section (int);
873 static void s_cons (int);
874 static void s_float_cons (int);
875 static void s_mips_globl (int);
876 static void s_option (int);
877 static void s_mipsset (int);
878 static void s_abicalls (int);
879 static void s_cpload (int);
880 static void s_cpsetup (int);
881 static void s_cplocal (int);
882 static void s_cprestore (int);
883 static void s_cpreturn (int);
884 static void s_gpvalue (int);
885 static void s_gpword (int);
886 static void s_gpdword (int);
887 static void s_cpadd (int);
888 static void s_insn (int);
889 static void md_obj_begin (void);
890 static void md_obj_end (void);
891 static void s_mips_ent (int);
892 static void s_mips_end (int);
893 static void s_mips_frame (int);
894 static void s_mips_mask (int reg_type);
895 static void s_mips_stab (int);
896 static void s_mips_weakext (int);
897 static void s_mips_file (int);
898 static void s_mips_loc (int);
899 static bfd_boolean pic_need_relax (symbolS *, asection *);
900 static int relaxed_branch_length (fragS *, asection *, int);
901 static int validate_mips_insn (const struct mips_opcode *);
903 /* Table and functions used to map between CPU/ISA names, and
904 ISA levels, and CPU numbers. */
908 const char *name; /* CPU or ISA name. */
909 int is_isa; /* Is this an ISA? (If 0, a CPU.) */
910 int isa; /* ISA level. */
911 int cpu; /* CPU number (default CPU if ISA). */
914 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
915 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
916 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
920 The following pseudo-ops from the Kane and Heinrich MIPS book
921 should be defined here, but are currently unsupported: .alias,
922 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
924 The following pseudo-ops from the Kane and Heinrich MIPS book are
925 specific to the type of debugging information being generated, and
926 should be defined by the object format: .aent, .begin, .bend,
927 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
930 The following pseudo-ops from the Kane and Heinrich MIPS book are
931 not MIPS CPU specific, but are also not specific to the object file
932 format. This file is probably the best place to define them, but
933 they are not currently supported: .asm0, .endr, .lab, .repeat,
936 static const pseudo_typeS mips_pseudo_table[] =
938 /* MIPS specific pseudo-ops. */
939 {"option", s_option, 0},
940 {"set", s_mipsset, 0},
941 {"rdata", s_change_sec, 'r'},
942 {"sdata", s_change_sec, 's'},
943 {"livereg", s_ignore, 0},
944 {"abicalls", s_abicalls, 0},
945 {"cpload", s_cpload, 0},
946 {"cpsetup", s_cpsetup, 0},
947 {"cplocal", s_cplocal, 0},
948 {"cprestore", s_cprestore, 0},
949 {"cpreturn", s_cpreturn, 0},
950 {"gpvalue", s_gpvalue, 0},
951 {"gpword", s_gpword, 0},
952 {"gpdword", s_gpdword, 0},
953 {"cpadd", s_cpadd, 0},
956 /* Relatively generic pseudo-ops that happen to be used on MIPS
958 {"asciiz", stringer, 1},
959 {"bss", s_change_sec, 'b'},
962 {"dword", s_cons, 3},
963 {"weakext", s_mips_weakext, 0},
965 /* These pseudo-ops are defined in read.c, but must be overridden
966 here for one reason or another. */
967 {"align", s_align, 0},
969 {"data", s_change_sec, 'd'},
970 {"double", s_float_cons, 'd'},
971 {"float", s_float_cons, 'f'},
972 {"globl", s_mips_globl, 0},
973 {"global", s_mips_globl, 0},
974 {"hword", s_cons, 1},
979 {"section", s_change_section, 0},
980 {"short", s_cons, 1},
981 {"single", s_float_cons, 'f'},
982 {"stabn", s_mips_stab, 'n'},
983 {"text", s_change_sec, 't'},
986 { "extern", ecoff_directive_extern, 0},
991 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
993 /* These pseudo-ops should be defined by the object file format.
994 However, a.out doesn't support them, so we have versions here. */
995 {"aent", s_mips_ent, 1},
996 {"bgnb", s_ignore, 0},
997 {"end", s_mips_end, 0},
998 {"endb", s_ignore, 0},
999 {"ent", s_mips_ent, 0},
1000 {"file", s_mips_file, 0},
1001 {"fmask", s_mips_mask, 'F'},
1002 {"frame", s_mips_frame, 0},
1003 {"loc", s_mips_loc, 0},
1004 {"mask", s_mips_mask, 'R'},
1005 {"verstamp", s_ignore, 0},
1009 extern void pop_insert (const pseudo_typeS *);
1012 mips_pop_insert (void)
1014 pop_insert (mips_pseudo_table);
1015 if (! ECOFF_DEBUGGING)
1016 pop_insert (mips_nonecoff_pseudo_table);
1019 /* Symbols labelling the current insn. */
1021 struct insn_label_list
1023 struct insn_label_list *next;
1027 static struct insn_label_list *insn_labels;
1028 static struct insn_label_list *free_insn_labels;
1030 static void mips_clear_insn_labels (void);
1033 mips_clear_insn_labels (void)
1035 register struct insn_label_list **pl;
1037 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1043 static char *expr_end;
1045 /* Expressions which appear in instructions. These are set by
1048 static expressionS imm_expr;
1049 static expressionS imm2_expr;
1050 static expressionS offset_expr;
1052 /* Relocs associated with imm_expr and offset_expr. */
1054 static bfd_reloc_code_real_type imm_reloc[3]
1055 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1056 static bfd_reloc_code_real_type offset_reloc[3]
1057 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1059 /* These are set by mips16_ip if an explicit extension is used. */
1061 static bfd_boolean mips16_small, mips16_ext;
1064 /* The pdr segment for per procedure frame/regmask info. Not used for
1067 static segT pdr_seg;
1070 /* The default target format to use. */
1073 mips_target_format (void)
1075 switch (OUTPUT_FLAVOR)
1077 case bfd_target_aout_flavour:
1078 return target_big_endian ? "a.out-mips-big" : "a.out-mips-little";
1079 case bfd_target_ecoff_flavour:
1080 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1081 case bfd_target_coff_flavour:
1083 case bfd_target_elf_flavour:
1085 /* This is traditional mips. */
1086 return (target_big_endian
1087 ? (HAVE_64BIT_OBJECTS
1088 ? "elf64-tradbigmips"
1090 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1091 : (HAVE_64BIT_OBJECTS
1092 ? "elf64-tradlittlemips"
1094 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1096 return (target_big_endian
1097 ? (HAVE_64BIT_OBJECTS
1100 ? "elf32-nbigmips" : "elf32-bigmips"))
1101 : (HAVE_64BIT_OBJECTS
1102 ? "elf64-littlemips"
1104 ? "elf32-nlittlemips" : "elf32-littlemips")));
1112 /* This function is called once, at assembler startup time. It should
1113 set up all the tables, etc. that the MD part of the assembler will need. */
1118 register const char *retval = NULL;
1122 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
1123 as_warn (_("Could not set architecture and machine"));
1125 op_hash = hash_new ();
1127 for (i = 0; i < NUMOPCODES;)
1129 const char *name = mips_opcodes[i].name;
1131 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
1134 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1135 mips_opcodes[i].name, retval);
1136 /* Probably a memory allocation problem? Give up now. */
1137 as_fatal (_("Broken assembler. No assembly attempted."));
1141 if (mips_opcodes[i].pinfo != INSN_MACRO)
1143 if (!validate_mips_insn (&mips_opcodes[i]))
1148 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1151 mips16_op_hash = hash_new ();
1154 while (i < bfd_mips16_num_opcodes)
1156 const char *name = mips16_opcodes[i].name;
1158 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
1160 as_fatal (_("internal: can't hash `%s': %s"),
1161 mips16_opcodes[i].name, retval);
1164 if (mips16_opcodes[i].pinfo != INSN_MACRO
1165 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1166 != mips16_opcodes[i].match))
1168 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1169 mips16_opcodes[i].name, mips16_opcodes[i].args);
1174 while (i < bfd_mips16_num_opcodes
1175 && strcmp (mips16_opcodes[i].name, name) == 0);
1179 as_fatal (_("Broken assembler. No assembly attempted."));
1181 /* We add all the general register names to the symbol table. This
1182 helps us detect invalid uses of them. */
1183 for (i = 0; i < 32; i++)
1187 sprintf (buf, "$%d", i);
1188 symbol_table_insert (symbol_new (buf, reg_section, i,
1189 &zero_address_frag));
1191 symbol_table_insert (symbol_new ("$ra", reg_section, RA,
1192 &zero_address_frag));
1193 symbol_table_insert (symbol_new ("$fp", reg_section, FP,
1194 &zero_address_frag));
1195 symbol_table_insert (symbol_new ("$sp", reg_section, SP,
1196 &zero_address_frag));
1197 symbol_table_insert (symbol_new ("$gp", reg_section, GP,
1198 &zero_address_frag));
1199 symbol_table_insert (symbol_new ("$at", reg_section, AT,
1200 &zero_address_frag));
1201 symbol_table_insert (symbol_new ("$kt0", reg_section, KT0,
1202 &zero_address_frag));
1203 symbol_table_insert (symbol_new ("$kt1", reg_section, KT1,
1204 &zero_address_frag));
1205 symbol_table_insert (symbol_new ("$zero", reg_section, ZERO,
1206 &zero_address_frag));
1207 symbol_table_insert (symbol_new ("$pc", reg_section, -1,
1208 &zero_address_frag));
1210 /* If we don't add these register names to the symbol table, they
1211 may end up being added as regular symbols by operand(), and then
1212 make it to the object file as undefined in case they're not
1213 regarded as local symbols. They're local in o32, since `$' is a
1214 local symbol prefix, but not in n32 or n64. */
1215 for (i = 0; i < 8; i++)
1219 sprintf (buf, "$fcc%i", i);
1220 symbol_table_insert (symbol_new (buf, reg_section, -1,
1221 &zero_address_frag));
1224 mips_no_prev_insn (FALSE);
1227 mips_cprmask[0] = 0;
1228 mips_cprmask[1] = 0;
1229 mips_cprmask[2] = 0;
1230 mips_cprmask[3] = 0;
1232 /* set the default alignment for the text section (2**2) */
1233 record_alignment (text_section, 2);
1235 if (USE_GLOBAL_POINTER_OPT)
1236 bfd_set_gp_size (stdoutput, g_switch_value);
1238 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1240 /* On a native system, sections must be aligned to 16 byte
1241 boundaries. When configured for an embedded ELF target, we
1243 if (strcmp (TARGET_OS, "elf") != 0)
1245 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
1246 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
1247 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
1250 /* Create a .reginfo section for register masks and a .mdebug
1251 section for debugging information. */
1259 subseg = now_subseg;
1261 /* The ABI says this section should be loaded so that the
1262 running program can access it. However, we don't load it
1263 if we are configured for an embedded target */
1264 flags = SEC_READONLY | SEC_DATA;
1265 if (strcmp (TARGET_OS, "elf") != 0)
1266 flags |= SEC_ALLOC | SEC_LOAD;
1268 if (mips_abi != N64_ABI)
1270 sec = subseg_new (".reginfo", (subsegT) 0);
1272 bfd_set_section_flags (stdoutput, sec, flags);
1273 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
1276 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
1281 /* The 64-bit ABI uses a .MIPS.options section rather than
1282 .reginfo section. */
1283 sec = subseg_new (".MIPS.options", (subsegT) 0);
1284 bfd_set_section_flags (stdoutput, sec, flags);
1285 bfd_set_section_alignment (stdoutput, sec, 3);
1288 /* Set up the option header. */
1290 Elf_Internal_Options opthdr;
1293 opthdr.kind = ODK_REGINFO;
1294 opthdr.size = (sizeof (Elf_External_Options)
1295 + sizeof (Elf64_External_RegInfo));
1298 f = frag_more (sizeof (Elf_External_Options));
1299 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
1300 (Elf_External_Options *) f);
1302 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
1307 if (ECOFF_DEBUGGING)
1309 sec = subseg_new (".mdebug", (subsegT) 0);
1310 (void) bfd_set_section_flags (stdoutput, sec,
1311 SEC_HAS_CONTENTS | SEC_READONLY);
1312 (void) bfd_set_section_alignment (stdoutput, sec, 2);
1315 else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr)
1317 pdr_seg = subseg_new (".pdr", (subsegT) 0);
1318 (void) bfd_set_section_flags (stdoutput, pdr_seg,
1319 SEC_READONLY | SEC_RELOC
1321 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
1325 subseg_set (seg, subseg);
1329 if (! ECOFF_DEBUGGING)
1336 if (! ECOFF_DEBUGGING)
1341 md_assemble (char *str)
1343 struct mips_cl_insn insn;
1344 bfd_reloc_code_real_type unused_reloc[3]
1345 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1347 imm_expr.X_op = O_absent;
1348 imm2_expr.X_op = O_absent;
1349 offset_expr.X_op = O_absent;
1350 imm_reloc[0] = BFD_RELOC_UNUSED;
1351 imm_reloc[1] = BFD_RELOC_UNUSED;
1352 imm_reloc[2] = BFD_RELOC_UNUSED;
1353 offset_reloc[0] = BFD_RELOC_UNUSED;
1354 offset_reloc[1] = BFD_RELOC_UNUSED;
1355 offset_reloc[2] = BFD_RELOC_UNUSED;
1357 if (mips_opts.mips16)
1358 mips16_ip (str, &insn);
1361 mips_ip (str, &insn);
1362 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1363 str, insn.insn_opcode));
1368 as_bad ("%s `%s'", insn_error, str);
1372 if (insn.insn_mo->pinfo == INSN_MACRO)
1375 if (mips_opts.mips16)
1376 mips16_macro (&insn);
1383 if (imm_expr.X_op != O_absent)
1384 append_insn (&insn, &imm_expr, imm_reloc);
1385 else if (offset_expr.X_op != O_absent)
1386 append_insn (&insn, &offset_expr, offset_reloc);
1388 append_insn (&insn, NULL, unused_reloc);
1392 /* Return true if the given relocation might need a matching %lo().
1393 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1394 applied to local symbols. */
1396 static inline bfd_boolean
1397 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
1399 return (reloc == BFD_RELOC_HI16_S
1400 || reloc == BFD_RELOC_MIPS_GOT16);
1403 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1406 static inline bfd_boolean
1407 fixup_has_matching_lo_p (fixS *fixp)
1409 return (fixp->fx_next != NULL
1410 && fixp->fx_next->fx_r_type == BFD_RELOC_LO16
1411 && fixp->fx_addsy == fixp->fx_next->fx_addsy
1412 && fixp->fx_offset == fixp->fx_next->fx_offset);
1415 /* See whether instruction IP reads register REG. CLASS is the type
1419 insn_uses_reg (struct mips_cl_insn *ip, unsigned int reg,
1420 enum mips_regclass class)
1422 if (class == MIPS16_REG)
1424 assert (mips_opts.mips16);
1425 reg = mips16_to_32_reg_map[reg];
1426 class = MIPS_GR_REG;
1429 /* Don't report on general register ZERO, since it never changes. */
1430 if (class == MIPS_GR_REG && reg == ZERO)
1433 if (class == MIPS_FP_REG)
1435 assert (! mips_opts.mips16);
1436 /* If we are called with either $f0 or $f1, we must check $f0.
1437 This is not optimal, because it will introduce an unnecessary
1438 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1439 need to distinguish reading both $f0 and $f1 or just one of
1440 them. Note that we don't have to check the other way,
1441 because there is no instruction that sets both $f0 and $f1
1442 and requires a delay. */
1443 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
1444 && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1)
1445 == (reg &~ (unsigned) 1)))
1447 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
1448 && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1)
1449 == (reg &~ (unsigned) 1)))
1452 else if (! mips_opts.mips16)
1454 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
1455 && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg)
1457 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
1458 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg)
1463 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
1464 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX)
1465 & MIPS16OP_MASK_RX)]
1468 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
1469 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY)
1470 & MIPS16OP_MASK_RY)]
1473 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
1474 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
1475 & MIPS16OP_MASK_MOVE32Z)]
1478 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
1480 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
1482 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
1484 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
1485 && ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
1486 & MIPS16OP_MASK_REGR32) == reg)
1493 /* This function returns true if modifying a register requires a
1497 reg_needs_delay (unsigned int reg)
1499 unsigned long prev_pinfo;
1501 prev_pinfo = prev_insn.insn_mo->pinfo;
1502 if (! mips_opts.noreorder
1503 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
1504 && ! gpr_interlocks)
1505 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1506 && ! cop_interlocks)))
1508 /* A load from a coprocessor or from memory. All load delays
1509 delay the use of general register rt for one instruction. */
1510 /* Itbl support may require additional care here. */
1511 know (prev_pinfo & INSN_WRITE_GPR_T);
1512 if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT))
1519 /* Mark instruction labels in mips16 mode. This permits the linker to
1520 handle them specially, such as generating jalx instructions when
1521 needed. We also make them odd for the duration of the assembly, in
1522 order to generate the right sort of code. We will make them even
1523 in the adjust_symtab routine, while leaving them marked. This is
1524 convenient for the debugger and the disassembler. The linker knows
1525 to make them odd again. */
1528 mips16_mark_labels (void)
1530 if (mips_opts.mips16)
1532 struct insn_label_list *l;
1535 for (l = insn_labels; l != NULL; l = l->next)
1538 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1539 S_SET_OTHER (l->label, STO_MIPS16);
1541 val = S_GET_VALUE (l->label);
1543 S_SET_VALUE (l->label, val + 1);
1548 /* End the current frag. Make it a variant frag and record the
1552 relax_close_frag (void)
1554 mips_macro_warning.first_frag = frag_now;
1555 frag_var (rs_machine_dependent, 0, 0,
1556 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
1557 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
1559 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
1560 mips_relax.first_fixup = 0;
1563 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
1564 See the comment above RELAX_ENCODE for more details. */
1567 relax_start (symbolS *symbol)
1569 assert (mips_relax.sequence == 0);
1570 mips_relax.sequence = 1;
1571 mips_relax.symbol = symbol;
1574 /* Start generating the second version of a relaxable sequence.
1575 See the comment above RELAX_ENCODE for more details. */
1580 assert (mips_relax.sequence == 1);
1581 mips_relax.sequence = 2;
1584 /* End the current relaxable sequence. */
1589 assert (mips_relax.sequence == 2);
1590 relax_close_frag ();
1591 mips_relax.sequence = 0;
1594 /* Output an instruction. IP is the instruction information.
1595 ADDRESS_EXPR is an operand of the instruction to be used with
1599 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
1600 bfd_reloc_code_real_type *reloc_type)
1602 register unsigned long prev_pinfo, pinfo;
1606 relax_stateT prev_insn_frag_type = 0;
1607 bfd_boolean relaxed_branch = FALSE;
1608 bfd_boolean force_new_frag = FALSE;
1610 /* Mark instruction labels in mips16 mode. */
1611 mips16_mark_labels ();
1613 prev_pinfo = prev_insn.insn_mo->pinfo;
1614 pinfo = ip->insn_mo->pinfo;
1616 if (mips_relax.sequence != 2
1617 && (!mips_opts.noreorder || prev_nop_frag != NULL))
1621 /* If the previous insn required any delay slots, see if we need
1622 to insert a NOP or two. There are eight kinds of possible
1623 hazards, of which an instruction can have at most one type.
1624 (1) a load from memory delay
1625 (2) a load from a coprocessor delay
1626 (3) an unconditional branch delay
1627 (4) a conditional branch delay
1628 (5) a move to coprocessor register delay
1629 (6) a load coprocessor register from memory delay
1630 (7) a coprocessor condition code delay
1631 (8) a HI/LO special register delay
1633 There are a lot of optimizations we could do that we don't.
1634 In particular, we do not, in general, reorder instructions.
1635 If you use gcc with optimization, it will reorder
1636 instructions and generally do much more optimization then we
1637 do here; repeating all that work in the assembler would only
1638 benefit hand written assembly code, and does not seem worth
1641 /* This is how a NOP is emitted. */
1642 #define emit_nop() \
1644 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1645 : md_number_to_chars (frag_more (4), 0, 4))
1647 /* The previous insn might require a delay slot, depending upon
1648 the contents of the current insn. */
1649 if (! mips_opts.mips16
1650 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
1651 && ! gpr_interlocks)
1652 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1653 && ! cop_interlocks)))
1655 /* A load from a coprocessor or from memory. All load
1656 delays delay the use of general register rt for one
1658 /* Itbl support may require additional care here. */
1659 know (prev_pinfo & INSN_WRITE_GPR_T);
1660 if (mips_optimize == 0
1661 || insn_uses_reg (ip,
1662 ((prev_insn.insn_opcode >> OP_SH_RT)
1667 else if (! mips_opts.mips16
1668 && (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
1669 && ! cop_interlocks)
1670 || ((prev_pinfo & INSN_COPROC_MEMORY_DELAY)
1671 && ! cop_mem_interlocks)))
1673 /* A generic coprocessor delay. The previous instruction
1674 modified a coprocessor general or control register. If
1675 it modified a control register, we need to avoid any
1676 coprocessor instruction (this is probably not always
1677 required, but it sometimes is). If it modified a general
1678 register, we avoid using that register.
1680 This case is not handled very well. There is no special
1681 knowledge of CP0 handling, and the coprocessors other
1682 than the floating point unit are not distinguished at
1684 /* Itbl support may require additional care here. FIXME!
1685 Need to modify this to include knowledge about
1686 user specified delays! */
1687 if (prev_pinfo & INSN_WRITE_FPR_T)
1689 if (mips_optimize == 0
1690 || insn_uses_reg (ip,
1691 ((prev_insn.insn_opcode >> OP_SH_FT)
1696 else if (prev_pinfo & INSN_WRITE_FPR_S)
1698 if (mips_optimize == 0
1699 || insn_uses_reg (ip,
1700 ((prev_insn.insn_opcode >> OP_SH_FS)
1707 /* We don't know exactly what the previous instruction
1708 does. If the current instruction uses a coprocessor
1709 register, we must insert a NOP. If previous
1710 instruction may set the condition codes, and the
1711 current instruction uses them, we must insert two
1713 /* Itbl support may require additional care here. */
1714 if (mips_optimize == 0
1715 || ((prev_pinfo & INSN_WRITE_COND_CODE)
1716 && (pinfo & INSN_READ_COND_CODE)))
1718 else if (pinfo & INSN_COP)
1722 else if (! mips_opts.mips16
1723 && (prev_pinfo & INSN_WRITE_COND_CODE)
1724 && ! cop_interlocks)
1726 /* The previous instruction sets the coprocessor condition
1727 codes, but does not require a general coprocessor delay
1728 (this means it is a floating point comparison
1729 instruction). If this instruction uses the condition
1730 codes, we need to insert a single NOP. */
1731 /* Itbl support may require additional care here. */
1732 if (mips_optimize == 0
1733 || (pinfo & INSN_READ_COND_CODE))
1737 /* If we're fixing up mfhi/mflo for the r7000 and the
1738 previous insn was an mfhi/mflo and the current insn
1739 reads the register that the mfhi/mflo wrote to, then
1742 else if (mips_7000_hilo_fix
1743 && MF_HILO_INSN (prev_pinfo)
1744 && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD)
1751 /* If we're fixing up mfhi/mflo for the r7000 and the
1752 2nd previous insn was an mfhi/mflo and the current insn
1753 reads the register that the mfhi/mflo wrote to, then
1756 else if (mips_7000_hilo_fix
1757 && MF_HILO_INSN (prev_prev_insn.insn_opcode)
1758 && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD)
1766 else if (prev_pinfo & INSN_READ_LO)
1768 /* The previous instruction reads the LO register; if the
1769 current instruction writes to the LO register, we must
1770 insert two NOPS. Some newer processors have interlocks.
1771 Also the tx39's multiply instructions can be executed
1772 immediately after a read from HI/LO (without the delay),
1773 though the tx39's divide insns still do require the
1775 if (! (hilo_interlocks
1776 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
1777 && (mips_optimize == 0
1778 || (pinfo & INSN_WRITE_LO)))
1780 /* Most mips16 branch insns don't have a delay slot.
1781 If a read from LO is immediately followed by a branch
1782 to a write to LO we have a read followed by a write
1783 less than 2 insns away. We assume the target of
1784 a branch might be a write to LO, and insert a nop
1785 between a read and an immediately following branch. */
1786 else if (mips_opts.mips16
1787 && (mips_optimize == 0
1788 || (pinfo & MIPS16_INSN_BRANCH)))
1791 else if (prev_insn.insn_mo->pinfo & INSN_READ_HI)
1793 /* The previous instruction reads the HI register; if the
1794 current instruction writes to the HI register, we must
1795 insert a NOP. Some newer processors have interlocks.
1796 Also the note tx39's multiply above. */
1797 if (! (hilo_interlocks
1798 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
1799 && (mips_optimize == 0
1800 || (pinfo & INSN_WRITE_HI)))
1802 /* Most mips16 branch insns don't have a delay slot.
1803 If a read from HI is immediately followed by a branch
1804 to a write to HI we have a read followed by a write
1805 less than 2 insns away. We assume the target of
1806 a branch might be a write to HI, and insert a nop
1807 between a read and an immediately following branch. */
1808 else if (mips_opts.mips16
1809 && (mips_optimize == 0
1810 || (pinfo & MIPS16_INSN_BRANCH)))
1814 /* If the previous instruction was in a noreorder section, then
1815 we don't want to insert the nop after all. */
1816 /* Itbl support may require additional care here. */
1817 if (prev_insn_unreordered)
1820 /* There are two cases which require two intervening
1821 instructions: 1) setting the condition codes using a move to
1822 coprocessor instruction which requires a general coprocessor
1823 delay and then reading the condition codes 2) reading the HI
1824 or LO register and then writing to it (except on processors
1825 which have interlocks). If we are not already emitting a NOP
1826 instruction, we must check for these cases compared to the
1827 instruction previous to the previous instruction. */
1828 if ((! mips_opts.mips16
1829 && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
1830 && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
1831 && (pinfo & INSN_READ_COND_CODE)
1832 && ! cop_interlocks)
1833 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
1834 && (pinfo & INSN_WRITE_LO)
1835 && ! (hilo_interlocks
1836 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))))
1837 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
1838 && (pinfo & INSN_WRITE_HI)
1839 && ! (hilo_interlocks
1840 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))))
1845 if (prev_prev_insn_unreordered)
1848 if (prev_prev_nop && nops == 0)
1851 if (mips_fix_4122_bugs && prev_insn.insn_mo->name)
1853 /* We're out of bits in pinfo, so we must resort to string
1854 ops here. Shortcuts are selected based on opcodes being
1855 limited to the VR4122 instruction set. */
1857 const char *pn = prev_insn.insn_mo->name;
1858 const char *tn = ip->insn_mo->name;
1859 if (strncmp(pn, "macc", 4) == 0
1860 || strncmp(pn, "dmacc", 5) == 0)
1862 /* Errata 21 - [D]DIV[U] after [D]MACC */
1863 if (strstr (tn, "div"))
1868 /* Errata 23 - Continuous DMULT[U]/DMACC instructions */
1869 if (pn[0] == 'd' /* dmacc */
1870 && (strncmp(tn, "dmult", 5) == 0
1871 || strncmp(tn, "dmacc", 5) == 0))
1876 /* Errata 24 - MT{LO,HI} after [D]MACC */
1877 if (strcmp (tn, "mtlo") == 0
1878 || strcmp (tn, "mthi") == 0)
1884 else if (strncmp(pn, "dmult", 5) == 0
1885 && (strncmp(tn, "dmult", 5) == 0
1886 || strncmp(tn, "dmacc", 5) == 0))
1888 /* Here is the rest of errata 23. */
1891 if (nops < min_nops)
1895 /* If we are being given a nop instruction, don't bother with
1896 one of the nops we would otherwise output. This will only
1897 happen when a nop instruction is used with mips_optimize set
1900 && ! mips_opts.noreorder
1901 && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0))
1904 /* Now emit the right number of NOP instructions. */
1905 if (nops > 0 && ! mips_opts.noreorder)
1908 unsigned long old_frag_offset;
1910 struct insn_label_list *l;
1912 old_frag = frag_now;
1913 old_frag_offset = frag_now_fix ();
1915 for (i = 0; i < nops; i++)
1920 listing_prev_line ();
1921 /* We may be at the start of a variant frag. In case we
1922 are, make sure there is enough space for the frag
1923 after the frags created by listing_prev_line. The
1924 argument to frag_grow here must be at least as large
1925 as the argument to all other calls to frag_grow in
1926 this file. We don't have to worry about being in the
1927 middle of a variant frag, because the variants insert
1928 all needed nop instructions themselves. */
1932 for (l = insn_labels; l != NULL; l = l->next)
1936 assert (S_GET_SEGMENT (l->label) == now_seg);
1937 symbol_set_frag (l->label, frag_now);
1938 val = (valueT) frag_now_fix ();
1939 /* mips16 text labels are stored as odd. */
1940 if (mips_opts.mips16)
1942 S_SET_VALUE (l->label, val);
1945 #ifndef NO_ECOFF_DEBUGGING
1946 if (ECOFF_DEBUGGING)
1947 ecoff_fix_loc (old_frag, old_frag_offset);
1950 else if (prev_nop_frag != NULL)
1952 /* We have a frag holding nops we may be able to remove. If
1953 we don't need any nops, we can decrease the size of
1954 prev_nop_frag by the size of one instruction. If we do
1955 need some nops, we count them in prev_nops_required. */
1956 if (prev_nop_frag_since == 0)
1960 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1961 --prev_nop_frag_holds;
1964 prev_nop_frag_required += nops;
1968 if (prev_prev_nop == 0)
1970 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1971 --prev_nop_frag_holds;
1974 ++prev_nop_frag_required;
1977 if (prev_nop_frag_holds <= prev_nop_frag_required)
1978 prev_nop_frag = NULL;
1980 ++prev_nop_frag_since;
1982 /* Sanity check: by the time we reach the second instruction
1983 after prev_nop_frag, we should have used up all the nops
1984 one way or another. */
1985 assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL);
1989 /* Record the frag type before frag_var. */
1991 prev_insn_frag_type = prev_insn_frag->fr_type;
1994 && *reloc_type == BFD_RELOC_16_PCREL_S2
1995 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
1996 || pinfo & INSN_COND_BRANCH_LIKELY)
1997 && mips_relax_branch
1998 /* Don't try branch relaxation within .set nomacro, or within
1999 .set noat if we use $at for PIC computations. If it turns
2000 out that the branch was out-of-range, we'll get an error. */
2001 && !mips_opts.warn_about_macros
2002 && !(mips_opts.noat && mips_pic != NO_PIC)
2003 && !mips_opts.mips16)
2005 relaxed_branch = TRUE;
2006 f = frag_var (rs_machine_dependent,
2007 relaxed_branch_length
2009 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
2010 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4,
2012 (pinfo & INSN_UNCOND_BRANCH_DELAY,
2013 pinfo & INSN_COND_BRANCH_LIKELY,
2014 pinfo & INSN_WRITE_GPR_31,
2016 address_expr->X_add_symbol,
2017 address_expr->X_add_number,
2019 *reloc_type = BFD_RELOC_UNUSED;
2021 else if (*reloc_type > BFD_RELOC_UNUSED)
2023 /* We need to set up a variant frag. */
2024 assert (mips_opts.mips16 && address_expr != NULL);
2025 f = frag_var (rs_machine_dependent, 4, 0,
2026 RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED,
2027 mips16_small, mips16_ext,
2029 & INSN_UNCOND_BRANCH_DELAY),
2030 (*prev_insn_reloc_type
2031 == BFD_RELOC_MIPS16_JMP)),
2032 make_expr_symbol (address_expr), 0, NULL);
2034 else if (mips_opts.mips16
2036 && *reloc_type != BFD_RELOC_MIPS16_JMP)
2038 /* Make sure there is enough room to swap this instruction with
2039 a following jump instruction. */
2045 if (mips_opts.mips16
2046 && mips_opts.noreorder
2047 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2048 as_warn (_("extended instruction in delay slot"));
2050 if (mips_relax.sequence)
2052 /* If we've reached the end of this frag, turn it into a variant
2053 frag and record the information for the instructions we've
2055 if (frag_room () < 4)
2056 relax_close_frag ();
2057 mips_relax.sizes[mips_relax.sequence - 1] += 4;
2060 if (mips_relax.sequence != 2)
2061 mips_macro_warning.sizes[0] += 4;
2062 if (mips_relax.sequence != 1)
2063 mips_macro_warning.sizes[1] += 4;
2068 fixp[0] = fixp[1] = fixp[2] = NULL;
2069 if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED)
2071 if (address_expr->X_op == O_constant)
2075 switch (*reloc_type)
2078 ip->insn_opcode |= address_expr->X_add_number;
2081 case BFD_RELOC_MIPS_HIGHEST:
2082 tmp = (address_expr->X_add_number
2083 + ((valueT) 0x8000 << 32) + 0x80008000) >> 16;
2085 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2088 case BFD_RELOC_MIPS_HIGHER:
2089 tmp = (address_expr->X_add_number + 0x80008000) >> 16;
2090 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2093 case BFD_RELOC_HI16_S:
2094 ip->insn_opcode |= ((address_expr->X_add_number + 0x8000)
2098 case BFD_RELOC_HI16:
2099 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
2102 case BFD_RELOC_LO16:
2103 case BFD_RELOC_MIPS_GOT_DISP:
2104 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
2107 case BFD_RELOC_MIPS_JMP:
2108 if ((address_expr->X_add_number & 3) != 0)
2109 as_bad (_("jump to misaligned address (0x%lx)"),
2110 (unsigned long) address_expr->X_add_number);
2111 if (address_expr->X_add_number & ~0xfffffff)
2112 as_bad (_("jump address range overflow (0x%lx)"),
2113 (unsigned long) address_expr->X_add_number);
2114 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
2117 case BFD_RELOC_MIPS16_JMP:
2118 if ((address_expr->X_add_number & 3) != 0)
2119 as_bad (_("jump to misaligned address (0x%lx)"),
2120 (unsigned long) address_expr->X_add_number);
2121 if (address_expr->X_add_number & ~0xfffffff)
2122 as_bad (_("jump address range overflow (0x%lx)"),
2123 (unsigned long) address_expr->X_add_number);
2125 (((address_expr->X_add_number & 0x7c0000) << 3)
2126 | ((address_expr->X_add_number & 0xf800000) >> 7)
2127 | ((address_expr->X_add_number & 0x3fffc) >> 2));
2130 case BFD_RELOC_16_PCREL_S2:
2140 reloc_howto_type *howto;
2143 /* In a compound relocation, it is the final (outermost)
2144 operator that determines the relocated field. */
2145 for (i = 1; i < 3; i++)
2146 if (reloc_type[i] == BFD_RELOC_UNUSED)
2149 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
2150 fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal,
2151 bfd_get_reloc_size(howto),
2153 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
2156 /* These relocations can have an addend that won't fit in
2157 4 octets for 64bit assembly. */
2159 && ! howto->partial_inplace
2160 && (reloc_type[0] == BFD_RELOC_16
2161 || reloc_type[0] == BFD_RELOC_32
2162 || reloc_type[0] == BFD_RELOC_MIPS_JMP
2163 || reloc_type[0] == BFD_RELOC_HI16_S
2164 || reloc_type[0] == BFD_RELOC_LO16
2165 || reloc_type[0] == BFD_RELOC_GPREL16
2166 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
2167 || reloc_type[0] == BFD_RELOC_GPREL32
2168 || reloc_type[0] == BFD_RELOC_64
2169 || reloc_type[0] == BFD_RELOC_CTOR
2170 || reloc_type[0] == BFD_RELOC_MIPS_SUB
2171 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
2172 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
2173 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
2174 || reloc_type[0] == BFD_RELOC_MIPS_REL16
2175 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT))
2176 fixp[0]->fx_no_overflow = 1;
2178 if (mips_relax.sequence)
2180 if (mips_relax.first_fixup == 0)
2181 mips_relax.first_fixup = fixp[0];
2183 else if (reloc_needs_lo_p (*reloc_type))
2185 struct mips_hi_fixup *hi_fixup;
2187 /* Reuse the last entry if it already has a matching %lo. */
2188 hi_fixup = mips_hi_fixup_list;
2190 || !fixup_has_matching_lo_p (hi_fixup->fixp))
2192 hi_fixup = ((struct mips_hi_fixup *)
2193 xmalloc (sizeof (struct mips_hi_fixup)));
2194 hi_fixup->next = mips_hi_fixup_list;
2195 mips_hi_fixup_list = hi_fixup;
2197 hi_fixup->fixp = fixp[0];
2198 hi_fixup->seg = now_seg;
2201 /* Add fixups for the second and third relocations, if given.
2202 Note that the ABI allows the second relocation to be
2203 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2204 moment we only use RSS_UNDEF, but we could add support
2205 for the others if it ever becomes necessary. */
2206 for (i = 1; i < 3; i++)
2207 if (reloc_type[i] != BFD_RELOC_UNUSED)
2209 address_expr->X_op = O_absent;
2210 address_expr->X_add_symbol = 0;
2211 address_expr->X_add_number = 0;
2213 fixp[i] = fix_new_exp (frag_now, fixp[0]->fx_where,
2214 fixp[0]->fx_size, address_expr,
2215 FALSE, reloc_type[i]);
2220 if (! mips_opts.mips16)
2222 md_number_to_chars (f, ip->insn_opcode, 4);
2224 dwarf2_emit_insn (4);
2227 else if (*reloc_type == BFD_RELOC_MIPS16_JMP)
2229 md_number_to_chars (f, ip->insn_opcode >> 16, 2);
2230 md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2);
2232 dwarf2_emit_insn (4);
2239 md_number_to_chars (f, 0xf000 | ip->extend, 2);
2242 md_number_to_chars (f, ip->insn_opcode, 2);
2244 dwarf2_emit_insn (ip->use_extend ? 4 : 2);
2248 /* Update the register mask information. */
2249 if (! mips_opts.mips16)
2251 if (pinfo & INSN_WRITE_GPR_D)
2252 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD);
2253 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
2254 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT);
2255 if (pinfo & INSN_READ_GPR_S)
2256 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS);
2257 if (pinfo & INSN_WRITE_GPR_31)
2258 mips_gprmask |= 1 << RA;
2259 if (pinfo & INSN_WRITE_FPR_D)
2260 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD);
2261 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
2262 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS);
2263 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
2264 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT);
2265 if ((pinfo & INSN_READ_FPR_R) != 0)
2266 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR);
2267 if (pinfo & INSN_COP)
2269 /* We don't keep enough information to sort these cases out.
2270 The itbl support does keep this information however, although
2271 we currently don't support itbl fprmats as part of the cop
2272 instruction. May want to add this support in the future. */
2274 /* Never set the bit for $0, which is always zero. */
2275 mips_gprmask &= ~1 << 0;
2279 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
2280 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX)
2281 & MIPS16OP_MASK_RX);
2282 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
2283 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY)
2284 & MIPS16OP_MASK_RY);
2285 if (pinfo & MIPS16_INSN_WRITE_Z)
2286 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ)
2287 & MIPS16OP_MASK_RZ);
2288 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
2289 mips_gprmask |= 1 << TREG;
2290 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
2291 mips_gprmask |= 1 << SP;
2292 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
2293 mips_gprmask |= 1 << RA;
2294 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2295 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2296 if (pinfo & MIPS16_INSN_READ_Z)
2297 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
2298 & MIPS16OP_MASK_MOVE32Z);
2299 if (pinfo & MIPS16_INSN_READ_GPR_X)
2300 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
2301 & MIPS16OP_MASK_REGR32);
2304 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
2306 /* Filling the branch delay slot is more complex. We try to
2307 switch the branch with the previous instruction, which we can
2308 do if the previous instruction does not set up a condition
2309 that the branch tests and if the branch is not itself the
2310 target of any branch. */
2311 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
2312 || (pinfo & INSN_COND_BRANCH_DELAY))
2314 if (mips_optimize < 2
2315 /* If we have seen .set volatile or .set nomove, don't
2317 || mips_opts.nomove != 0
2318 /* If we had to emit any NOP instructions, then we
2319 already know we can not swap. */
2321 /* If we don't even know the previous insn, we can not
2323 || ! prev_insn_valid
2324 /* If the previous insn is already in a branch delay
2325 slot, then we can not swap. */
2326 || prev_insn_is_delay_slot
2327 /* If the previous previous insn was in a .set
2328 noreorder, we can't swap. Actually, the MIPS
2329 assembler will swap in this situation. However, gcc
2330 configured -with-gnu-as will generate code like
2336 in which we can not swap the bne and INSN. If gcc is
2337 not configured -with-gnu-as, it does not output the
2338 .set pseudo-ops. We don't have to check
2339 prev_insn_unreordered, because prev_insn_valid will
2340 be 0 in that case. We don't want to use
2341 prev_prev_insn_valid, because we do want to be able
2342 to swap at the start of a function. */
2343 || prev_prev_insn_unreordered
2344 /* If the branch is itself the target of a branch, we
2345 can not swap. We cheat on this; all we check for is
2346 whether there is a label on this instruction. If
2347 there are any branches to anything other than a
2348 label, users must use .set noreorder. */
2349 || insn_labels != NULL
2350 /* If the previous instruction is in a variant frag
2351 other than this branch's one, we cannot do the swap.
2352 This does not apply to the mips16, which uses variant
2353 frags for different purposes. */
2354 || (! mips_opts.mips16
2355 && prev_insn_frag_type == rs_machine_dependent)
2356 /* If the branch reads the condition codes, we don't
2357 even try to swap, because in the sequence
2362 we can not swap, and I don't feel like handling that
2364 || (! mips_opts.mips16
2365 && (pinfo & INSN_READ_COND_CODE)
2366 && ! cop_interlocks)
2367 /* We can not swap with an instruction that requires a
2368 delay slot, because the target of the branch might
2369 interfere with that instruction. */
2370 || (! mips_opts.mips16
2372 /* Itbl support may require additional care here. */
2373 & (INSN_LOAD_COPROC_DELAY
2374 | INSN_COPROC_MOVE_DELAY
2375 | INSN_WRITE_COND_CODE))
2376 && ! cop_interlocks)
2377 || (! (hilo_interlocks
2378 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
2382 || (! mips_opts.mips16
2383 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2384 && ! gpr_interlocks)
2385 || (! mips_opts.mips16
2386 /* Itbl support may require additional care here. */
2387 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)
2388 && ! cop_mem_interlocks)
2389 /* We can not swap with a branch instruction. */
2391 & (INSN_UNCOND_BRANCH_DELAY
2392 | INSN_COND_BRANCH_DELAY
2393 | INSN_COND_BRANCH_LIKELY))
2394 /* We do not swap with a trap instruction, since it
2395 complicates trap handlers to have the trap
2396 instruction be in a delay slot. */
2397 || (prev_pinfo & INSN_TRAP)
2398 /* If the branch reads a register that the previous
2399 instruction sets, we can not swap. */
2400 || (! mips_opts.mips16
2401 && (prev_pinfo & INSN_WRITE_GPR_T)
2402 && insn_uses_reg (ip,
2403 ((prev_insn.insn_opcode >> OP_SH_RT)
2406 || (! mips_opts.mips16
2407 && (prev_pinfo & INSN_WRITE_GPR_D)
2408 && insn_uses_reg (ip,
2409 ((prev_insn.insn_opcode >> OP_SH_RD)
2412 || (mips_opts.mips16
2413 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
2414 && insn_uses_reg (ip,
2415 ((prev_insn.insn_opcode
2417 & MIPS16OP_MASK_RX),
2419 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
2420 && insn_uses_reg (ip,
2421 ((prev_insn.insn_opcode
2423 & MIPS16OP_MASK_RY),
2425 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
2426 && insn_uses_reg (ip,
2427 ((prev_insn.insn_opcode
2429 & MIPS16OP_MASK_RZ),
2431 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
2432 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
2433 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
2434 && insn_uses_reg (ip, RA, MIPS_GR_REG))
2435 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2436 && insn_uses_reg (ip,
2437 MIPS16OP_EXTRACT_REG32R (prev_insn.
2440 /* If the branch writes a register that the previous
2441 instruction sets, we can not swap (we know that
2442 branches write only to RD or to $31). */
2443 || (! mips_opts.mips16
2444 && (prev_pinfo & INSN_WRITE_GPR_T)
2445 && (((pinfo & INSN_WRITE_GPR_D)
2446 && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)
2447 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2448 || ((pinfo & INSN_WRITE_GPR_31)
2449 && (((prev_insn.insn_opcode >> OP_SH_RT)
2452 || (! mips_opts.mips16
2453 && (prev_pinfo & INSN_WRITE_GPR_D)
2454 && (((pinfo & INSN_WRITE_GPR_D)
2455 && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD)
2456 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2457 || ((pinfo & INSN_WRITE_GPR_31)
2458 && (((prev_insn.insn_opcode >> OP_SH_RD)
2461 || (mips_opts.mips16
2462 && (pinfo & MIPS16_INSN_WRITE_31)
2463 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
2464 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2465 && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode)
2467 /* If the branch writes a register that the previous
2468 instruction reads, we can not swap (we know that
2469 branches only write to RD or to $31). */
2470 || (! mips_opts.mips16
2471 && (pinfo & INSN_WRITE_GPR_D)
2472 && insn_uses_reg (&prev_insn,
2473 ((ip->insn_opcode >> OP_SH_RD)
2476 || (! mips_opts.mips16
2477 && (pinfo & INSN_WRITE_GPR_31)
2478 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2479 || (mips_opts.mips16
2480 && (pinfo & MIPS16_INSN_WRITE_31)
2481 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2482 /* If we are generating embedded PIC code, the branch
2483 might be expanded into a sequence which uses $at, so
2484 we can't swap with an instruction which reads it. */
2485 || (mips_pic == EMBEDDED_PIC
2486 && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG))
2487 /* If the previous previous instruction has a load
2488 delay, and sets a register that the branch reads, we
2490 || (! mips_opts.mips16
2491 /* Itbl support may require additional care here. */
2492 && (((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
2493 && ! cop_interlocks)
2494 || ((prev_prev_insn.insn_mo->pinfo
2495 & INSN_LOAD_MEMORY_DELAY)
2496 && ! gpr_interlocks))
2497 && insn_uses_reg (ip,
2498 ((prev_prev_insn.insn_opcode >> OP_SH_RT)
2501 /* If one instruction sets a condition code and the
2502 other one uses a condition code, we can not swap. */
2503 || ((pinfo & INSN_READ_COND_CODE)
2504 && (prev_pinfo & INSN_WRITE_COND_CODE))
2505 || ((pinfo & INSN_WRITE_COND_CODE)
2506 && (prev_pinfo & INSN_READ_COND_CODE))
2507 /* If the previous instruction uses the PC, we can not
2509 || (mips_opts.mips16
2510 && (prev_pinfo & MIPS16_INSN_READ_PC))
2511 /* If the previous instruction was extended, we can not
2513 || (mips_opts.mips16 && prev_insn_extended)
2514 /* If the previous instruction had a fixup in mips16
2515 mode, we can not swap. This normally means that the
2516 previous instruction was a 4 byte branch anyhow. */
2517 || (mips_opts.mips16 && prev_insn_fixp[0])
2518 /* If the previous instruction is a sync, sync.l, or
2519 sync.p, we can not swap. */
2520 || (prev_pinfo & INSN_SYNC))
2522 /* We could do even better for unconditional branches to
2523 portions of this object file; we could pick up the
2524 instruction at the destination, put it in the delay
2525 slot, and bump the destination address. */
2527 /* Update the previous insn information. */
2528 prev_prev_insn = *ip;
2529 prev_insn.insn_mo = &dummy_opcode;
2533 /* It looks like we can actually do the swap. */
2534 if (! mips_opts.mips16)
2539 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2540 if (!relaxed_branch)
2542 /* If this is not a relaxed branch, then just
2543 swap the instructions. */
2544 memcpy (temp, prev_f, 4);
2545 memcpy (prev_f, f, 4);
2546 memcpy (f, temp, 4);
2550 /* If this is a relaxed branch, then we move the
2551 instruction to be placed in the delay slot to
2552 the current frag, shrinking the fixed part of
2553 the originating frag. If the branch occupies
2554 the tail of the latter, we move it backwards,
2555 into the space freed by the moved instruction. */
2557 memcpy (f, prev_f, 4);
2558 prev_insn_frag->fr_fix -= 4;
2559 if (prev_insn_frag->fr_type == rs_machine_dependent)
2560 memmove (prev_f, prev_f + 4, prev_insn_frag->fr_var);
2563 if (prev_insn_fixp[0])
2565 prev_insn_fixp[0]->fx_frag = frag_now;
2566 prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal;
2568 if (prev_insn_fixp[1])
2570 prev_insn_fixp[1]->fx_frag = frag_now;
2571 prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal;
2573 if (prev_insn_fixp[2])
2575 prev_insn_fixp[2]->fx_frag = frag_now;
2576 prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal;
2578 if (prev_insn_fixp[0] && HAVE_NEWABI
2579 && prev_insn_frag != frag_now
2580 && (prev_insn_fixp[0]->fx_r_type
2581 == BFD_RELOC_MIPS_GOT_DISP
2582 || (prev_insn_fixp[0]->fx_r_type
2583 == BFD_RELOC_MIPS_CALL16)))
2585 /* To avoid confusion in tc_gen_reloc, we must
2586 ensure that this does not become a variant
2588 force_new_frag = TRUE;
2591 if (!relaxed_branch)
2595 fixp[0]->fx_frag = prev_insn_frag;
2596 fixp[0]->fx_where = prev_insn_where;
2600 fixp[1]->fx_frag = prev_insn_frag;
2601 fixp[1]->fx_where = prev_insn_where;
2605 fixp[2]->fx_frag = prev_insn_frag;
2606 fixp[2]->fx_where = prev_insn_where;
2609 else if (prev_insn_frag->fr_type == rs_machine_dependent)
2612 fixp[0]->fx_where -= 4;
2614 fixp[1]->fx_where -= 4;
2616 fixp[2]->fx_where -= 4;
2624 assert (prev_insn_fixp[0] == NULL);
2625 assert (prev_insn_fixp[1] == NULL);
2626 assert (prev_insn_fixp[2] == NULL);
2627 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2628 memcpy (temp, prev_f, 2);
2629 memcpy (prev_f, f, 2);
2630 if (*reloc_type != BFD_RELOC_MIPS16_JMP)
2632 assert (*reloc_type == BFD_RELOC_UNUSED);
2633 memcpy (f, temp, 2);
2637 memcpy (f, f + 2, 2);
2638 memcpy (f + 2, temp, 2);
2642 fixp[0]->fx_frag = prev_insn_frag;
2643 fixp[0]->fx_where = prev_insn_where;
2647 fixp[1]->fx_frag = prev_insn_frag;
2648 fixp[1]->fx_where = prev_insn_where;
2652 fixp[2]->fx_frag = prev_insn_frag;
2653 fixp[2]->fx_where = prev_insn_where;
2657 /* Update the previous insn information; leave prev_insn
2659 prev_prev_insn = *ip;
2661 prev_insn_is_delay_slot = 1;
2663 /* If that was an unconditional branch, forget the previous
2664 insn information. */
2665 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
2667 prev_prev_insn.insn_mo = &dummy_opcode;
2668 prev_insn.insn_mo = &dummy_opcode;
2671 prev_insn_fixp[0] = NULL;
2672 prev_insn_fixp[1] = NULL;
2673 prev_insn_fixp[2] = NULL;
2674 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2675 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2676 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2677 prev_insn_extended = 0;
2679 else if (pinfo & INSN_COND_BRANCH_LIKELY)
2681 /* We don't yet optimize a branch likely. What we should do
2682 is look at the target, copy the instruction found there
2683 into the delay slot, and increment the branch to jump to
2684 the next instruction. */
2686 /* Update the previous insn information. */
2687 prev_prev_insn = *ip;
2688 prev_insn.insn_mo = &dummy_opcode;
2689 prev_insn_fixp[0] = NULL;
2690 prev_insn_fixp[1] = NULL;
2691 prev_insn_fixp[2] = NULL;
2692 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2693 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2694 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2695 prev_insn_extended = 0;
2699 /* Update the previous insn information. */
2701 prev_prev_insn.insn_mo = &dummy_opcode;
2703 prev_prev_insn = prev_insn;
2706 /* Any time we see a branch, we always fill the delay slot
2707 immediately; since this insn is not a branch, we know it
2708 is not in a delay slot. */
2709 prev_insn_is_delay_slot = 0;
2711 prev_insn_fixp[0] = fixp[0];
2712 prev_insn_fixp[1] = fixp[1];
2713 prev_insn_fixp[2] = fixp[2];
2714 prev_insn_reloc_type[0] = reloc_type[0];
2715 prev_insn_reloc_type[1] = reloc_type[1];
2716 prev_insn_reloc_type[2] = reloc_type[2];
2717 if (mips_opts.mips16)
2718 prev_insn_extended = (ip->use_extend
2719 || *reloc_type > BFD_RELOC_UNUSED);
2722 prev_prev_insn_unreordered = prev_insn_unreordered;
2723 prev_insn_unreordered = 0;
2724 prev_insn_frag = frag_now;
2725 prev_insn_where = f - frag_now->fr_literal;
2726 prev_insn_valid = 1;
2728 else if (mips_relax.sequence != 2)
2730 /* We need to record a bit of information even when we are not
2731 reordering, in order to determine the base address for mips16
2732 PC relative relocs. */
2733 prev_prev_insn = prev_insn;
2735 prev_insn_reloc_type[0] = reloc_type[0];
2736 prev_insn_reloc_type[1] = reloc_type[1];
2737 prev_insn_reloc_type[2] = reloc_type[2];
2738 prev_prev_insn_unreordered = prev_insn_unreordered;
2739 prev_insn_unreordered = 1;
2742 /* We just output an insn, so the next one doesn't have a label. */
2743 mips_clear_insn_labels ();
2746 /* This function forgets that there was any previous instruction or
2747 label. If PRESERVE is non-zero, it remembers enough information to
2748 know whether nops are needed before a noreorder section. */
2751 mips_no_prev_insn (int preserve)
2755 prev_insn.insn_mo = &dummy_opcode;
2756 prev_prev_insn.insn_mo = &dummy_opcode;
2757 prev_nop_frag = NULL;
2758 prev_nop_frag_holds = 0;
2759 prev_nop_frag_required = 0;
2760 prev_nop_frag_since = 0;
2762 prev_insn_valid = 0;
2763 prev_insn_is_delay_slot = 0;
2764 prev_insn_unreordered = 0;
2765 prev_insn_extended = 0;
2766 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2767 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2768 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2769 prev_prev_insn_unreordered = 0;
2770 mips_clear_insn_labels ();
2773 /* This function must be called whenever we turn on noreorder or emit
2774 something other than instructions. It inserts any NOPS which might
2775 be needed by the previous instruction, and clears the information
2776 kept for the previous instructions. The INSNS parameter is true if
2777 instructions are to follow. */
2780 mips_emit_delays (bfd_boolean insns)
2782 if (! mips_opts.noreorder)
2787 if ((! mips_opts.mips16
2788 && ((prev_insn.insn_mo->pinfo
2789 & (INSN_LOAD_COPROC_DELAY
2790 | INSN_COPROC_MOVE_DELAY
2791 | INSN_WRITE_COND_CODE))
2792 && ! cop_interlocks))
2793 || (! hilo_interlocks
2794 && (prev_insn.insn_mo->pinfo
2797 || (! mips_opts.mips16
2798 && (prev_insn.insn_mo->pinfo & INSN_LOAD_MEMORY_DELAY)
2799 && ! gpr_interlocks)
2800 || (! mips_opts.mips16
2801 && (prev_insn.insn_mo->pinfo & INSN_COPROC_MEMORY_DELAY)
2802 && ! cop_mem_interlocks))
2804 /* Itbl support may require additional care here. */
2806 if ((! mips_opts.mips16
2807 && ((prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
2808 && ! cop_interlocks))
2809 || (! hilo_interlocks
2810 && ((prev_insn.insn_mo->pinfo & INSN_READ_HI)
2811 || (prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2814 if (prev_insn_unreordered)
2817 else if ((! mips_opts.mips16
2818 && ((prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
2819 && ! cop_interlocks))
2820 || (! hilo_interlocks
2821 && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
2822 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2824 /* Itbl support may require additional care here. */
2825 if (! prev_prev_insn_unreordered)
2829 if (mips_fix_4122_bugs && prev_insn.insn_mo->name)
2832 const char *pn = prev_insn.insn_mo->name;
2833 if (strncmp(pn, "macc", 4) == 0
2834 || strncmp(pn, "dmacc", 5) == 0
2835 || strncmp(pn, "dmult", 5) == 0)
2839 if (nops < min_nops)
2845 struct insn_label_list *l;
2849 /* Record the frag which holds the nop instructions, so
2850 that we can remove them if we don't need them. */
2851 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
2852 prev_nop_frag = frag_now;
2853 prev_nop_frag_holds = nops;
2854 prev_nop_frag_required = 0;
2855 prev_nop_frag_since = 0;
2858 for (; nops > 0; --nops)
2863 /* Move on to a new frag, so that it is safe to simply
2864 decrease the size of prev_nop_frag. */
2865 frag_wane (frag_now);
2869 for (l = insn_labels; l != NULL; l = l->next)
2873 assert (S_GET_SEGMENT (l->label) == now_seg);
2874 symbol_set_frag (l->label, frag_now);
2875 val = (valueT) frag_now_fix ();
2876 /* mips16 text labels are stored as odd. */
2877 if (mips_opts.mips16)
2879 S_SET_VALUE (l->label, val);
2884 /* Mark instruction labels in mips16 mode. */
2886 mips16_mark_labels ();
2888 mips_no_prev_insn (insns);
2891 /* Set up global variables for the start of a new macro. */
2896 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
2897 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
2898 && (prev_insn.insn_mo->pinfo
2899 & (INSN_UNCOND_BRANCH_DELAY
2900 | INSN_COND_BRANCH_DELAY
2901 | INSN_COND_BRANCH_LIKELY)) != 0);
2904 /* Given that a macro is longer than 4 bytes, return the appropriate warning
2905 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
2906 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
2909 macro_warning (relax_substateT subtype)
2911 if (subtype & RELAX_DELAY_SLOT)
2912 return _("Macro instruction expanded into multiple instructions"
2913 " in a branch delay slot");
2914 else if (subtype & RELAX_NOMACRO)
2915 return _("Macro instruction expanded into multiple instructions");
2920 /* Finish up a macro. Emit warnings as appropriate. */
2925 if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4)
2927 relax_substateT subtype;
2929 /* Set up the relaxation warning flags. */
2931 if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0])
2932 subtype |= RELAX_SECOND_LONGER;
2933 if (mips_opts.warn_about_macros)
2934 subtype |= RELAX_NOMACRO;
2935 if (mips_macro_warning.delay_slot_p)
2936 subtype |= RELAX_DELAY_SLOT;
2938 if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4)
2940 /* Either the macro has a single implementation or both
2941 implementations are longer than 4 bytes. Emit the
2943 const char *msg = macro_warning (subtype);
2949 /* One implementation might need a warning but the other
2950 definitely doesn't. */
2951 mips_macro_warning.first_frag->fr_subtype |= subtype;
2956 /* Build an instruction created by a macro expansion. This is passed
2957 a pointer to the count of instructions created so far, an
2958 expression, the name of the instruction to build, an operand format
2959 string, and corresponding arguments. */
2962 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
2964 struct mips_cl_insn insn;
2965 bfd_reloc_code_real_type r[3];
2968 va_start (args, fmt);
2970 if (mips_opts.mips16)
2972 mips16_macro_build (ep, name, fmt, args);
2977 r[0] = BFD_RELOC_UNUSED;
2978 r[1] = BFD_RELOC_UNUSED;
2979 r[2] = BFD_RELOC_UNUSED;
2980 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
2981 assert (insn.insn_mo);
2982 assert (strcmp (name, insn.insn_mo->name) == 0);
2984 /* Search until we get a match for NAME. */
2987 /* It is assumed here that macros will never generate
2988 MDMX or MIPS-3D instructions. */
2989 if (strcmp (fmt, insn.insn_mo->args) == 0
2990 && insn.insn_mo->pinfo != INSN_MACRO
2991 && OPCODE_IS_MEMBER (insn.insn_mo,
2993 | (file_ase_mips16 ? INSN_MIPS16 : 0)),
2995 && (mips_opts.arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
2999 assert (insn.insn_mo->name);
3000 assert (strcmp (name, insn.insn_mo->name) == 0);
3003 insn.insn_opcode = insn.insn_mo->match;
3021 insn.insn_opcode |= (va_arg (args, int)
3022 & OP_MASK_SHAMT) << OP_SH_SHAMT;
3027 /* Note that in the macro case, these arguments are already
3028 in MSB form. (When handling the instruction in the
3029 non-macro case, these arguments are sizes from which
3030 MSB values must be calculated.) */
3031 insn.insn_opcode |= (va_arg (args, int)
3032 & OP_MASK_INSMSB) << OP_SH_INSMSB;
3038 /* Note that in the macro case, these arguments are already
3039 in MSBD form. (When handling the instruction in the
3040 non-macro case, these arguments are sizes from which
3041 MSBD values must be calculated.) */
3042 insn.insn_opcode |= (va_arg (args, int)
3043 & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD;
3054 insn.insn_opcode |= va_arg (args, int) << OP_SH_RT;
3058 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE;
3063 insn.insn_opcode |= va_arg (args, int) << OP_SH_FT;
3069 insn.insn_opcode |= va_arg (args, int) << OP_SH_RD;
3074 int tmp = va_arg (args, int);
3076 insn.insn_opcode |= tmp << OP_SH_RT;
3077 insn.insn_opcode |= tmp << OP_SH_RD;
3083 insn.insn_opcode |= va_arg (args, int) << OP_SH_FS;
3090 insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT;
3094 insn.insn_opcode |= va_arg (args, int) << OP_SH_FD;
3098 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20;
3102 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19;
3106 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2;
3113 insn.insn_opcode |= va_arg (args, int) << OP_SH_RS;
3119 *r = (bfd_reloc_code_real_type) va_arg (args, int);
3120 assert (*r == BFD_RELOC_GPREL16
3121 || *r == BFD_RELOC_MIPS_LITERAL
3122 || *r == BFD_RELOC_MIPS_HIGHER
3123 || *r == BFD_RELOC_HI16_S
3124 || *r == BFD_RELOC_LO16
3125 || *r == BFD_RELOC_MIPS_GOT16
3126 || *r == BFD_RELOC_MIPS_CALL16
3127 || *r == BFD_RELOC_MIPS_GOT_DISP
3128 || *r == BFD_RELOC_MIPS_GOT_PAGE
3129 || *r == BFD_RELOC_MIPS_GOT_OFST
3130 || *r == BFD_RELOC_MIPS_GOT_LO16
3131 || *r == BFD_RELOC_MIPS_CALL_LO16
3132 || (ep->X_op == O_subtract
3133 && *r == BFD_RELOC_PCREL_LO16));
3137 *r = (bfd_reloc_code_real_type) va_arg (args, int);
3139 && (ep->X_op == O_constant
3140 || (ep->X_op == O_symbol
3141 && (*r == BFD_RELOC_MIPS_HIGHEST
3142 || *r == BFD_RELOC_HI16_S
3143 || *r == BFD_RELOC_HI16
3144 || *r == BFD_RELOC_GPREL16
3145 || *r == BFD_RELOC_MIPS_GOT_HI16
3146 || *r == BFD_RELOC_MIPS_CALL_HI16))
3147 || (ep->X_op == O_subtract
3148 && *r == BFD_RELOC_PCREL_HI16_S)));
3152 assert (ep != NULL);
3154 * This allows macro() to pass an immediate expression for
3155 * creating short branches without creating a symbol.
3156 * Note that the expression still might come from the assembly
3157 * input, in which case the value is not checked for range nor
3158 * is a relocation entry generated (yuck).
3160 if (ep->X_op == O_constant)
3162 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
3166 *r = BFD_RELOC_16_PCREL_S2;
3170 assert (ep != NULL);
3171 *r = BFD_RELOC_MIPS_JMP;
3175 insn.insn_opcode |= va_arg (args, unsigned long);
3184 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3186 append_insn (&insn, ep, r);
3190 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
3193 struct mips_cl_insn insn;
3194 bfd_reloc_code_real_type r[3]
3195 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3197 insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
3198 assert (insn.insn_mo);
3199 assert (strcmp (name, insn.insn_mo->name) == 0);
3201 while (strcmp (fmt, insn.insn_mo->args) != 0
3202 || insn.insn_mo->pinfo == INSN_MACRO)
3205 assert (insn.insn_mo->name);
3206 assert (strcmp (name, insn.insn_mo->name) == 0);
3209 insn.insn_opcode = insn.insn_mo->match;
3210 insn.use_extend = FALSE;
3229 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY;
3234 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX;
3238 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ;
3242 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z;
3252 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32;
3259 regno = va_arg (args, int);
3260 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
3261 insn.insn_opcode |= regno << MIPS16OP_SH_REG32R;
3282 assert (ep != NULL);
3284 if (ep->X_op != O_constant)
3285 *r = (int) BFD_RELOC_UNUSED + c;
3288 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
3289 FALSE, &insn.insn_opcode, &insn.use_extend,
3292 *r = BFD_RELOC_UNUSED;
3298 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6;
3305 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3307 append_insn (&insn, ep, r);
3311 * Generate a "jalr" instruction with a relocation hint to the called
3312 * function. This occurs in NewABI PIC code.
3315 macro_build_jalr (expressionS *ep)
3324 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
3326 fix_new_exp (frag_now, f - frag_now->fr_literal,
3327 4, ep, FALSE, BFD_RELOC_MIPS_JALR);
3331 * Generate a "lui" instruction.
3334 macro_build_lui (expressionS *ep, int regnum)
3336 expressionS high_expr;
3337 struct mips_cl_insn insn;
3338 bfd_reloc_code_real_type r[3]
3339 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3340 const char *name = "lui";
3341 const char *fmt = "t,u";
3343 assert (! mips_opts.mips16);
3347 if (high_expr.X_op == O_constant)
3349 /* we can compute the instruction now without a relocation entry */
3350 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
3352 *r = BFD_RELOC_UNUSED;
3356 assert (ep->X_op == O_symbol);
3357 /* _gp_disp is a special case, used from s_cpload. */
3358 assert (mips_pic == NO_PIC
3360 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0));
3361 *r = BFD_RELOC_HI16_S;
3364 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
3365 assert (insn.insn_mo);
3366 assert (strcmp (name, insn.insn_mo->name) == 0);
3367 assert (strcmp (fmt, insn.insn_mo->args) == 0);
3369 insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT);
3370 if (*r == BFD_RELOC_UNUSED)
3372 insn.insn_opcode |= high_expr.X_add_number;
3373 append_insn (&insn, NULL, r);
3376 append_insn (&insn, &high_expr, r);
3379 /* Generate a sequence of instructions to do a load or store from a constant
3380 offset off of a base register (breg) into/from a target register (treg),
3381 using AT if necessary. */
3383 macro_build_ldst_constoffset (expressionS *ep, const char *op,
3384 int treg, int breg, int dbl)
3386 assert (ep->X_op == O_constant);
3388 /* Sign-extending 32-bit constants makes their handling easier. */
3389 if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff))
3390 == ~((bfd_vma) 0x7fffffff)))
3392 if (ep->X_add_number & ~((bfd_vma) 0xffffffff))
3393 as_bad (_("constant too large"));
3395 ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000)
3399 /* Right now, this routine can only handle signed 32-bit constants. */
3400 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
3401 as_warn (_("operand overflow"));
3403 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
3405 /* Signed 16-bit offset will fit in the op. Easy! */
3406 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
3410 /* 32-bit offset, need multiple instructions and AT, like:
3411 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3412 addu $tempreg,$tempreg,$breg
3413 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3414 to handle the complete offset. */
3415 macro_build_lui (ep, AT);
3416 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
3417 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
3420 as_warn (_("Macro used $at after \".set noat\""));
3425 * Generates code to set the $at register to true (one)
3426 * if reg is less than the immediate expression.
3429 set_at (int reg, int unsignedp)
3431 if (imm_expr.X_op == O_constant
3432 && imm_expr.X_add_number >= -0x8000
3433 && imm_expr.X_add_number < 0x8000)
3434 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
3435 AT, reg, BFD_RELOC_LO16);
3438 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
3439 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
3444 normalize_constant_expr (expressionS *ex)
3446 if (ex->X_op == O_constant && HAVE_32BIT_GPRS)
3447 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
3451 /* Warn if an expression is not a constant. */
3454 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
3456 if (ex->X_op == O_big)
3457 as_bad (_("unsupported large constant"));
3458 else if (ex->X_op != O_constant)
3459 as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name);
3461 normalize_constant_expr (ex);
3464 /* Count the leading zeroes by performing a binary chop. This is a
3465 bulky bit of source, but performance is a LOT better for the
3466 majority of values than a simple loop to count the bits:
3467 for (lcnt = 0; (lcnt < 32); lcnt++)
3468 if ((v) & (1 << (31 - lcnt)))
3470 However it is not code size friendly, and the gain will drop a bit
3471 on certain cached systems.
3473 #define COUNT_TOP_ZEROES(v) \
3474 (((v) & ~0xffff) == 0 \
3475 ? ((v) & ~0xff) == 0 \
3476 ? ((v) & ~0xf) == 0 \
3477 ? ((v) & ~0x3) == 0 \
3478 ? ((v) & ~0x1) == 0 \
3483 : ((v) & ~0x7) == 0 \
3486 : ((v) & ~0x3f) == 0 \
3487 ? ((v) & ~0x1f) == 0 \
3490 : ((v) & ~0x7f) == 0 \
3493 : ((v) & ~0xfff) == 0 \
3494 ? ((v) & ~0x3ff) == 0 \
3495 ? ((v) & ~0x1ff) == 0 \
3498 : ((v) & ~0x7ff) == 0 \
3501 : ((v) & ~0x3fff) == 0 \
3502 ? ((v) & ~0x1fff) == 0 \
3505 : ((v) & ~0x7fff) == 0 \
3508 : ((v) & ~0xffffff) == 0 \
3509 ? ((v) & ~0xfffff) == 0 \
3510 ? ((v) & ~0x3ffff) == 0 \
3511 ? ((v) & ~0x1ffff) == 0 \
3514 : ((v) & ~0x7ffff) == 0 \
3517 : ((v) & ~0x3fffff) == 0 \
3518 ? ((v) & ~0x1fffff) == 0 \
3521 : ((v) & ~0x7fffff) == 0 \
3524 : ((v) & ~0xfffffff) == 0 \
3525 ? ((v) & ~0x3ffffff) == 0 \
3526 ? ((v) & ~0x1ffffff) == 0 \
3529 : ((v) & ~0x7ffffff) == 0 \
3532 : ((v) & ~0x3fffffff) == 0 \
3533 ? ((v) & ~0x1fffffff) == 0 \
3536 : ((v) & ~0x7fffffff) == 0 \
3541 * This routine generates the least number of instructions necessary to load
3542 * an absolute expression value into a register.
3545 load_register (int reg, expressionS *ep, int dbl)
3548 expressionS hi32, lo32;
3550 if (ep->X_op != O_big)
3552 assert (ep->X_op == O_constant);
3554 /* Sign-extending 32-bit constants makes their handling easier. */
3555 if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff))
3556 == ~((bfd_vma) 0x7fffffff)))
3558 if (ep->X_add_number & ~((bfd_vma) 0xffffffff))
3559 as_bad (_("constant too large"));
3561 ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000)
3565 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
3567 /* We can handle 16 bit signed values with an addiu to
3568 $zero. No need to ever use daddiu here, since $zero and
3569 the result are always correct in 32 bit mode. */
3570 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3573 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
3575 /* We can handle 16 bit unsigned values with an ori to
3577 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
3580 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
3582 /* 32 bit values require an lui. */
3583 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16);
3584 if ((ep->X_add_number & 0xffff) != 0)
3585 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
3590 /* The value is larger than 32 bits. */
3592 if (HAVE_32BIT_GPRS)
3594 as_bad (_("Number (0x%lx) larger than 32 bits"),
3595 (unsigned long) ep->X_add_number);
3596 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3600 if (ep->X_op != O_big)
3603 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3604 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3605 hi32.X_add_number &= 0xffffffff;
3607 lo32.X_add_number &= 0xffffffff;
3611 assert (ep->X_add_number > 2);
3612 if (ep->X_add_number == 3)
3613 generic_bignum[3] = 0;
3614 else if (ep->X_add_number > 4)
3615 as_bad (_("Number larger than 64 bits"));
3616 lo32.X_op = O_constant;
3617 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
3618 hi32.X_op = O_constant;
3619 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
3622 if (hi32.X_add_number == 0)
3627 unsigned long hi, lo;
3629 if (hi32.X_add_number == (offsetT) 0xffffffff)
3631 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
3633 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3636 if (lo32.X_add_number & 0x80000000)
3638 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
3639 if (lo32.X_add_number & 0xffff)
3640 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
3645 /* Check for 16bit shifted constant. We know that hi32 is
3646 non-zero, so start the mask on the first bit of the hi32
3651 unsigned long himask, lomask;
3655 himask = 0xffff >> (32 - shift);
3656 lomask = (0xffff << shift) & 0xffffffff;
3660 himask = 0xffff << (shift - 32);
3663 if ((hi32.X_add_number & ~(offsetT) himask) == 0
3664 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
3668 tmp.X_op = O_constant;
3670 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
3671 | (lo32.X_add_number >> shift));
3673 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
3674 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
3675 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<",
3676 reg, reg, (shift >= 32) ? shift - 32 : shift);
3681 while (shift <= (64 - 16));
3683 /* Find the bit number of the lowest one bit, and store the
3684 shifted value in hi/lo. */
3685 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
3686 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
3690 while ((lo & 1) == 0)
3695 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
3701 while ((hi & 1) == 0)
3710 /* Optimize if the shifted value is a (power of 2) - 1. */
3711 if ((hi == 0 && ((lo + 1) & lo) == 0)
3712 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
3714 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
3719 /* This instruction will set the register to be all
3721 tmp.X_op = O_constant;
3722 tmp.X_add_number = (offsetT) -1;
3723 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3727 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<",
3728 reg, reg, (bit >= 32) ? bit - 32 : bit);
3730 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<",
3731 reg, reg, (shift >= 32) ? shift - 32 : shift);
3736 /* Sign extend hi32 before calling load_register, because we can
3737 generally get better code when we load a sign extended value. */
3738 if ((hi32.X_add_number & 0x80000000) != 0)
3739 hi32.X_add_number |= ~(offsetT) 0xffffffff;
3740 load_register (reg, &hi32, 0);
3743 if ((lo32.X_add_number & 0xffff0000) == 0)
3747 macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0);
3755 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
3757 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
3758 macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0);
3764 macro_build (NULL, "dsll", "d,w,<", reg, freg, 16);
3768 mid16.X_add_number >>= 16;
3769 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
3770 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
3773 if ((lo32.X_add_number & 0xffff) != 0)
3774 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
3777 /* Load an address into a register. */
3780 load_address (int reg, expressionS *ep, int *used_at)
3782 if (ep->X_op != O_constant
3783 && ep->X_op != O_symbol)
3785 as_bad (_("expression too complex"));
3786 ep->X_op = O_constant;
3789 if (ep->X_op == O_constant)
3791 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
3795 if (mips_pic == NO_PIC)
3797 /* If this is a reference to a GP relative symbol, we want
3798 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3800 lui $reg,<sym> (BFD_RELOC_HI16_S)
3801 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3802 If we have an addend, we always use the latter form.
3804 With 64bit address space and a usable $at we want
3805 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3806 lui $at,<sym> (BFD_RELOC_HI16_S)
3807 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3808 daddiu $at,<sym> (BFD_RELOC_LO16)
3812 If $at is already in use, we use a path which is suboptimal
3813 on superscalar processors.
3814 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3815 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3817 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3819 daddiu $reg,<sym> (BFD_RELOC_LO16)
3821 if (HAVE_64BIT_ADDRESSES)
3823 /* We don't do GP optimization for now because RELAX_ENCODE can't
3824 hold the data for such large chunks. */
3826 if (*used_at == 0 && ! mips_opts.noat)
3828 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
3829 macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S);
3830 macro_build (ep, "daddiu", "t,r,j", reg, reg,
3831 BFD_RELOC_MIPS_HIGHER);
3832 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
3833 macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0);
3834 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
3839 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
3840 macro_build (ep, "daddiu", "t,r,j", reg, reg,
3841 BFD_RELOC_MIPS_HIGHER);
3842 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
3843 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
3844 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
3845 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
3850 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
3851 && ! nopic_need_relax (ep->X_add_symbol, 1))
3853 relax_start (ep->X_add_symbol);
3854 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
3855 mips_gp_register, BFD_RELOC_GPREL16);
3858 macro_build_lui (ep, reg);
3859 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
3860 reg, reg, BFD_RELOC_LO16);
3861 if (mips_relax.sequence)
3865 else if (mips_pic == SVR4_PIC && ! mips_big_got)
3869 /* If this is a reference to an external symbol, we want
3870 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3872 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3874 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3875 If there is a constant, it must be added in after.
3877 If we have NewABI, we want
3878 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3879 unless we're referencing a global symbol with a non-zero
3880 offset, in which case cst must be added separately. */
3883 if (ep->X_add_number)
3885 ex.X_add_number = ep->X_add_number;
3886 ep->X_add_number = 0;
3887 relax_start (ep->X_add_symbol);
3888 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3889 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
3890 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3891 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3892 ex.X_op = O_constant;
3893 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
3894 reg, reg, BFD_RELOC_LO16);
3895 ep->X_add_number = ex.X_add_number;
3898 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3899 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
3900 if (mips_relax.sequence)
3905 ex.X_add_number = ep->X_add_number;
3906 ep->X_add_number = 0;
3907 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3908 BFD_RELOC_MIPS_GOT16, mips_gp_register);
3909 macro_build (NULL, "nop", "");
3910 relax_start (ep->X_add_symbol);
3912 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3916 if (ex.X_add_number != 0)
3918 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3919 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3920 ex.X_op = O_constant;
3921 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
3922 reg, reg, BFD_RELOC_LO16);
3926 else if (mips_pic == SVR4_PIC)
3930 /* This is the large GOT case. If this is a reference to an
3931 external symbol, we want
3932 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3934 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3936 Otherwise, for a reference to a local symbol in old ABI, we want
3937 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3939 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3940 If there is a constant, it must be added in after.
3942 In the NewABI, for local symbols, with or without offsets, we want:
3943 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3944 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3948 ex.X_add_number = ep->X_add_number;
3949 ep->X_add_number = 0;
3950 relax_start (ep->X_add_symbol);
3951 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
3952 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
3953 reg, reg, mips_gp_register);
3954 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
3955 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
3956 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3957 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3958 else if (ex.X_add_number)
3960 ex.X_op = O_constant;
3961 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3965 ep->X_add_number = ex.X_add_number;
3967 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3968 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
3969 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3970 BFD_RELOC_MIPS_GOT_OFST);
3975 ex.X_add_number = ep->X_add_number;
3976 ep->X_add_number = 0;
3977 relax_start (ep->X_add_symbol);
3978 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
3979 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
3980 reg, reg, mips_gp_register);
3981 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
3982 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
3984 if (reg_needs_delay (mips_gp_register))
3986 /* We need a nop before loading from $gp. This special
3987 check is required because the lui which starts the main
3988 instruction stream does not refer to $gp, and so will not
3989 insert the nop which may be required. */
3990 macro_build (NULL, "nop", "");
3992 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3993 BFD_RELOC_MIPS_GOT16, mips_gp_register);
3994 macro_build (NULL, "nop", "");
3995 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3999 if (ex.X_add_number != 0)
4001 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4002 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4003 ex.X_op = O_constant;
4004 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4009 else if (mips_pic == EMBEDDED_PIC)
4012 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4014 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
4015 reg, mips_gp_register, BFD_RELOC_GPREL16);
4021 /* Move the contents of register SOURCE into register DEST. */
4024 move_register (int dest, int source)
4026 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
4030 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4031 LOCAL is the sum of a symbol and a 16-bit displacement. The two
4034 Global symbol Local sybmol
4035 ------------- ------------
4036 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4038 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4040 load_got_offset emits the first instruction and add_got_offset
4041 emits the second. */
4044 load_got_offset (int dest, expressionS *local)
4049 global.X_add_number = 0;
4051 relax_start (local->X_add_symbol);
4052 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4053 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4055 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4056 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4061 add_got_offset (int dest, expressionS *local)
4065 global.X_op = O_constant;
4066 global.X_op_symbol = NULL;
4067 global.X_add_symbol = NULL;
4068 global.X_add_number = local->X_add_number;
4070 relax_start (local->X_add_symbol);
4071 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
4072 dest, dest, BFD_RELOC_LO16);
4074 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
4080 * This routine implements the seemingly endless macro or synthesized
4081 * instructions and addressing modes in the mips assembly language. Many
4082 * of these macros are simple and are similar to each other. These could
4083 * probably be handled by some kind of table or grammar approach instead of
4084 * this verbose method. Others are not simple macros but are more like
4085 * optimizing code generation.
4086 * One interesting optimization is when several store macros appear
4087 * consecutively that would load AT with the upper half of the same address.
4088 * The ensuing load upper instructions are ommited. This implies some kind
4089 * of global optimization. We currently only optimize within a single macro.
4090 * For many of the load and store macros if the address is specified as a
4091 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4092 * first load register 'at' with zero and use it as the base register. The
4093 * mips assembler simply uses register $zero. Just one tiny optimization
4097 macro (struct mips_cl_insn *ip)
4099 register int treg, sreg, dreg, breg;
4115 bfd_reloc_code_real_type r;
4116 int hold_mips_optimize;
4118 assert (! mips_opts.mips16);
4120 treg = (ip->insn_opcode >> 16) & 0x1f;
4121 dreg = (ip->insn_opcode >> 11) & 0x1f;
4122 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
4123 mask = ip->insn_mo->mask;
4125 expr1.X_op = O_constant;
4126 expr1.X_op_symbol = NULL;
4127 expr1.X_add_symbol = NULL;
4128 expr1.X_add_number = 1;
4140 mips_emit_delays (TRUE);
4141 ++mips_opts.noreorder;
4142 mips_any_noreorder = 1;
4144 expr1.X_add_number = 8;
4145 macro_build (&expr1, "bgez", "s,p", sreg);
4147 macro_build (NULL, "nop", "", 0);
4149 move_register (dreg, sreg);
4150 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
4152 --mips_opts.noreorder;
4173 if (imm_expr.X_op == O_constant
4174 && imm_expr.X_add_number >= -0x8000
4175 && imm_expr.X_add_number < 0x8000)
4177 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
4180 load_register (AT, &imm_expr, dbl);
4181 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4200 if (imm_expr.X_op == O_constant
4201 && imm_expr.X_add_number >= 0
4202 && imm_expr.X_add_number < 0x10000)
4204 if (mask != M_NOR_I)
4205 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
4208 macro_build (&imm_expr, "ori", "t,r,i",
4209 treg, sreg, BFD_RELOC_LO16);
4210 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
4215 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4216 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4233 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4235 macro_build (&offset_expr, s, "s,t,p", sreg, 0);
4238 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4239 macro_build (&offset_expr, s, "s,t,p", sreg, AT);
4247 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
4252 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg);
4255 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
4256 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4262 /* check for > max integer */
4263 maxnum = 0x7fffffff;
4264 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4271 if (imm_expr.X_op == O_constant
4272 && imm_expr.X_add_number >= maxnum
4273 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4276 /* result is always false */
4278 macro_build (NULL, "nop", "", 0);
4280 macro_build (&offset_expr, "bnel", "s,t,p", 0, 0);
4283 if (imm_expr.X_op != O_constant)
4284 as_bad (_("Unsupported large constant"));
4285 ++imm_expr.X_add_number;
4289 if (mask == M_BGEL_I)
4291 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4293 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
4296 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4298 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
4301 maxnum = 0x7fffffff;
4302 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4309 maxnum = - maxnum - 1;
4310 if (imm_expr.X_op == O_constant
4311 && imm_expr.X_add_number <= maxnum
4312 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4315 /* result is always true */
4316 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
4317 macro_build (&offset_expr, "b", "p");
4321 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4331 macro_build (&offset_expr, likely ? "beql" : "beq",
4335 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
4336 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4344 && imm_expr.X_op == O_constant
4345 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4347 if (imm_expr.X_op != O_constant)
4348 as_bad (_("Unsupported large constant"));
4349 ++imm_expr.X_add_number;
4353 if (mask == M_BGEUL_I)
4355 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4357 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4359 macro_build (&offset_expr, likely ? "bnel" : "bne",
4364 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4372 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
4377 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg);
4380 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
4381 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4389 macro_build (&offset_expr, likely ? "bnel" : "bne",
4395 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
4396 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4404 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
4409 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg);
4412 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
4413 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4419 maxnum = 0x7fffffff;
4420 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4427 if (imm_expr.X_op == O_constant
4428 && imm_expr.X_add_number >= maxnum
4429 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4431 if (imm_expr.X_op != O_constant)
4432 as_bad (_("Unsupported large constant"));
4433 ++imm_expr.X_add_number;
4437 if (mask == M_BLTL_I)
4439 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4441 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
4444 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4446 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
4450 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4458 macro_build (&offset_expr, likely ? "beql" : "beq",
4464 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
4465 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4473 && imm_expr.X_op == O_constant
4474 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4476 if (imm_expr.X_op != O_constant)
4477 as_bad (_("Unsupported large constant"));
4478 ++imm_expr.X_add_number;
4482 if (mask == M_BLTUL_I)
4484 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4486 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4488 macro_build (&offset_expr, likely ? "beql" : "beq",
4493 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4501 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
4506 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg);
4509 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
4510 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4520 macro_build (&offset_expr, likely ? "bnel" : "bne",
4524 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
4525 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4533 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
4535 as_bad (_("Unsupported large constant"));
4540 pos = (unsigned long) imm_expr.X_add_number;
4541 size = (unsigned long) imm2_expr.X_add_number;
4546 as_bad (_("Improper position (%lu)"), pos);
4549 if (size == 0 || size > 64
4550 || (pos + size - 1) > 63)
4552 as_bad (_("Improper extract size (%lu, position %lu)"),
4557 if (size <= 32 && pos < 32)
4562 else if (size <= 32)
4572 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1);
4581 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
4583 as_bad (_("Unsupported large constant"));
4588 pos = (unsigned long) imm_expr.X_add_number;
4589 size = (unsigned long) imm2_expr.X_add_number;
4594 as_bad (_("Improper position (%lu)"), pos);
4597 if (size == 0 || size > 64
4598 || (pos + size - 1) > 63)
4600 as_bad (_("Improper insert size (%lu, position %lu)"),
4605 if (pos < 32 && (pos + size - 1) < 32)
4620 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos,
4637 as_warn (_("Divide by zero."));
4639 macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
4641 macro_build (NULL, "break", "c", 7);
4645 mips_emit_delays (TRUE);
4646 ++mips_opts.noreorder;
4647 mips_any_noreorder = 1;
4650 macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
4651 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4655 expr1.X_add_number = 8;
4656 macro_build (&expr1, "bne", "s,t,p", treg, 0);
4657 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4658 macro_build (NULL, "break", "c", 7);
4660 expr1.X_add_number = -1;
4661 macro_build (&expr1, dbl ? "daddiu" : "addiu", "t,r,j", AT, 0,
4663 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
4664 macro_build (&expr1, "bne", "s,t,p", treg, AT);
4667 expr1.X_add_number = 1;
4668 macro_build (&expr1, "daddiu", "t,r,j", AT, 0, BFD_RELOC_LO16);
4669 macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31);
4673 expr1.X_add_number = 0x80000000;
4674 macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16);
4678 macro_build (NULL, "teq", "s,t,q", sreg, AT, 6);
4679 /* We want to close the noreorder block as soon as possible, so
4680 that later insns are available for delay slot filling. */
4681 --mips_opts.noreorder;
4685 expr1.X_add_number = 8;
4686 macro_build (&expr1, "bne", "s,t,p", sreg, AT);
4687 macro_build (NULL, "nop", "", 0);
4689 /* We want to close the noreorder block as soon as possible, so
4690 that later insns are available for delay slot filling. */
4691 --mips_opts.noreorder;
4693 macro_build (NULL, "break", "c", 6);
4695 macro_build (NULL, s, "d", dreg);
4734 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4736 as_warn (_("Divide by zero."));
4738 macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
4740 macro_build (NULL, "break", "c", 7);
4743 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4745 if (strcmp (s2, "mflo") == 0)
4746 move_register (dreg, sreg);
4748 move_register (dreg, 0);
4751 if (imm_expr.X_op == O_constant
4752 && imm_expr.X_add_number == -1
4753 && s[strlen (s) - 1] != 'u')
4755 if (strcmp (s2, "mflo") == 0)
4757 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
4760 move_register (dreg, 0);
4764 load_register (AT, &imm_expr, dbl);
4765 macro_build (NULL, s, "z,s,t", sreg, AT);
4766 macro_build (NULL, s2, "d", dreg);
4785 mips_emit_delays (TRUE);
4786 ++mips_opts.noreorder;
4787 mips_any_noreorder = 1;
4790 macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
4791 macro_build (NULL, s, "z,s,t", sreg, treg);
4792 /* We want to close the noreorder block as soon as possible, so
4793 that later insns are available for delay slot filling. */
4794 --mips_opts.noreorder;
4798 expr1.X_add_number = 8;
4799 macro_build (&expr1, "bne", "s,t,p", treg, 0);
4800 macro_build (NULL, s, "z,s,t", sreg, treg);
4802 /* We want to close the noreorder block as soon as possible, so
4803 that later insns are available for delay slot filling. */
4804 --mips_opts.noreorder;
4805 macro_build (NULL, "break", "c", 7);
4807 macro_build (NULL, s2, "d", dreg);
4819 /* Load the address of a symbol into a register. If breg is not
4820 zero, we then add a base register to it. */
4822 if (dbl && HAVE_32BIT_GPRS)
4823 as_warn (_("dla used to load 32-bit register"));
4825 if (! dbl && HAVE_64BIT_OBJECTS)
4826 as_warn (_("la used to load 64-bit address"));
4828 if (offset_expr.X_op == O_constant
4829 && offset_expr.X_add_number >= -0x8000
4830 && offset_expr.X_add_number < 0x8000)
4832 macro_build (&offset_expr,
4833 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4834 "t,r,j", treg, sreg, BFD_RELOC_LO16);
4849 /* When generating embedded PIC code, we permit expressions of
4852 la $treg,foo-bar($breg)
4853 where bar is an address in the current section. These are used
4854 when getting the addresses of functions. We don't permit
4855 X_add_number to be non-zero, because if the symbol is
4856 external the relaxing code needs to know that any addend is
4857 purely the offset to X_op_symbol. */
4858 if (mips_pic == EMBEDDED_PIC
4859 && offset_expr.X_op == O_subtract
4860 && (symbol_constant_p (offset_expr.X_op_symbol)
4861 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
4862 : (symbol_equated_p (offset_expr.X_op_symbol)
4864 (symbol_get_value_expression (offset_expr.X_op_symbol)
4867 && (offset_expr.X_add_number == 0
4868 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
4874 macro_build (&offset_expr, "lui", "t,u",
4875 tempreg, BFD_RELOC_PCREL_HI16_S);
4879 macro_build (&offset_expr, "lui", "t,u",
4880 tempreg, BFD_RELOC_PCREL_HI16_S);
4882 (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu",
4883 "d,v,t", tempreg, tempreg, breg);
4885 macro_build (&offset_expr,
4886 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4887 "t,r,j", treg, tempreg, BFD_RELOC_PCREL_LO16);
4893 if (offset_expr.X_op != O_symbol
4894 && offset_expr.X_op != O_constant)
4896 as_bad (_("expression too complex"));
4897 offset_expr.X_op = O_constant;
4900 if (offset_expr.X_op == O_constant)
4901 load_register (tempreg, &offset_expr,
4902 ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
4903 ? (dbl || HAVE_64BIT_ADDRESSES)
4904 : HAVE_64BIT_ADDRESSES));
4905 else if (mips_pic == NO_PIC)
4907 /* If this is a reference to a GP relative symbol, we want
4908 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4910 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4911 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4912 If we have a constant, we need two instructions anyhow,
4913 so we may as well always use the latter form.
4915 With 64bit address space and a usable $at we want
4916 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4917 lui $at,<sym> (BFD_RELOC_HI16_S)
4918 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4919 daddiu $at,<sym> (BFD_RELOC_LO16)
4921 daddu $tempreg,$tempreg,$at
4923 If $at is already in use, we use a path which is suboptimal
4924 on superscalar processors.
4925 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4926 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4928 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4930 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4932 if (HAVE_64BIT_ADDRESSES)
4934 /* We don't do GP optimization for now because RELAX_ENCODE can't
4935 hold the data for such large chunks. */
4937 if (used_at == 0 && ! mips_opts.noat)
4939 macro_build (&offset_expr, "lui", "t,u",
4940 tempreg, BFD_RELOC_MIPS_HIGHEST);
4941 macro_build (&offset_expr, "lui", "t,u",
4942 AT, BFD_RELOC_HI16_S);
4943 macro_build (&offset_expr, "daddiu", "t,r,j",
4944 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
4945 macro_build (&offset_expr, "daddiu", "t,r,j",
4946 AT, AT, BFD_RELOC_LO16);
4947 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
4948 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
4953 macro_build (&offset_expr, "lui", "t,u",
4954 tempreg, BFD_RELOC_MIPS_HIGHEST);
4955 macro_build (&offset_expr, "daddiu", "t,r,j",
4956 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
4957 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
4958 macro_build (&offset_expr, "daddiu", "t,r,j",
4959 tempreg, tempreg, BFD_RELOC_HI16_S);
4960 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
4961 macro_build (&offset_expr, "daddiu", "t,r,j",
4962 tempreg, tempreg, BFD_RELOC_LO16);
4967 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
4968 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
4970 relax_start (offset_expr.X_add_symbol);
4971 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
4972 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
4975 macro_build_lui (&offset_expr, tempreg);
4976 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
4977 tempreg, tempreg, BFD_RELOC_LO16);
4978 if (mips_relax.sequence)
4982 else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI)
4984 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
4986 /* If this is a reference to an external symbol, and there
4987 is no constant, we want
4988 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4989 or for lca or if tempreg is PIC_CALL_REG
4990 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4991 For a local symbol, we want
4992 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4994 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4996 If we have a small constant, and this is a reference to
4997 an external symbol, we want
4998 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5000 addiu $tempreg,$tempreg,<constant>
5001 For a local symbol, we want the same instruction
5002 sequence, but we output a BFD_RELOC_LO16 reloc on the
5005 If we have a large constant, and this is a reference to
5006 an external symbol, we want
5007 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5008 lui $at,<hiconstant>
5009 addiu $at,$at,<loconstant>
5010 addu $tempreg,$tempreg,$at
5011 For a local symbol, we want the same instruction
5012 sequence, but we output a BFD_RELOC_LO16 reloc on the
5016 if (offset_expr.X_add_number == 0)
5018 if (breg == 0 && (call || tempreg == PIC_CALL_REG))
5019 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
5021 relax_start (offset_expr.X_add_symbol);
5022 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5023 lw_reloc_type, mips_gp_register);
5026 /* We're going to put in an addu instruction using
5027 tempreg, so we may as well insert the nop right
5029 macro_build (NULL, "nop", "");
5032 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5033 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
5034 macro_build (NULL, "nop", "");
5035 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5036 tempreg, tempreg, BFD_RELOC_LO16);
5038 /* FIXME: If breg == 0, and the next instruction uses
5039 $tempreg, then if this variant case is used an extra
5040 nop will be generated. */
5042 else if (offset_expr.X_add_number >= -0x8000
5043 && offset_expr.X_add_number < 0x8000)
5045 load_got_offset (tempreg, &offset_expr);
5046 macro_build (NULL, "nop", "");
5047 add_got_offset (tempreg, &offset_expr);
5051 expr1.X_add_number = offset_expr.X_add_number;
5052 offset_expr.X_add_number =
5053 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
5054 load_got_offset (tempreg, &offset_expr);
5055 /* If we are going to add in a base register, and the
5056 target register and the base register are the same,
5057 then we are using AT as a temporary register. Since
5058 we want to load the constant into AT, we add our
5059 current AT (from the global offset table) and the
5060 register into the register now, and pretend we were
5061 not using a base register. */
5064 macro_build (NULL, "nop", "");
5065 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5071 /* Set mips_optimize around the lui instruction to avoid
5072 inserting an unnecessary nop after the lw. */
5073 hold_mips_optimize = mips_optimize;
5075 macro_build_lui (&expr1, AT);
5076 mips_optimize = hold_mips_optimize;
5078 add_got_offset (AT, &offset_expr);
5079 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5080 tempreg, tempreg, AT);
5084 else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI)
5086 int add_breg_early = 0;
5088 /* If this is a reference to an external, and there is no
5089 constant, or local symbol (*), with or without a
5091 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5092 or for lca or if tempreg is PIC_CALL_REG
5093 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5095 If we have a small constant, and this is a reference to
5096 an external symbol, we want
5097 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5098 addiu $tempreg,$tempreg,<constant>
5100 If we have a large constant, and this is a reference to
5101 an external symbol, we want
5102 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5103 lui $at,<hiconstant>
5104 addiu $at,$at,<loconstant>
5105 addu $tempreg,$tempreg,$at
5107 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5108 local symbols, even though it introduces an additional
5111 if (offset_expr.X_add_number)
5113 expr1.X_add_number = offset_expr.X_add_number;
5114 offset_expr.X_add_number = 0;
5116 relax_start (offset_expr.X_add_symbol);
5117 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5118 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5120 if (expr1.X_add_number >= -0x8000
5121 && expr1.X_add_number < 0x8000)
5123 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5124 tempreg, tempreg, BFD_RELOC_LO16);
5126 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
5130 /* If we are going to add in a base register, and the
5131 target register and the base register are the same,
5132 then we are using AT as a temporary register. Since
5133 we want to load the constant into AT, we add our
5134 current AT (from the global offset table) and the
5135 register into the register now, and pretend we were
5136 not using a base register. */
5141 assert (tempreg == AT);
5142 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5148 macro_build_lui (&expr1, AT);
5149 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5150 AT, AT, BFD_RELOC_LO16);
5151 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5157 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5160 offset_expr.X_add_number = expr1.X_add_number;
5162 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5163 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5166 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5167 treg, tempreg, breg);
5173 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
5175 relax_start (offset_expr.X_add_symbol);
5176 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5177 BFD_RELOC_MIPS_CALL16, mips_gp_register);
5179 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5180 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5185 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5186 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5189 else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
5192 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5193 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5194 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5196 /* This is the large GOT case. If this is a reference to an
5197 external symbol, and there is no constant, we want
5198 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5199 addu $tempreg,$tempreg,$gp
5200 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5201 or for lca or if tempreg is PIC_CALL_REG
5202 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5203 addu $tempreg,$tempreg,$gp
5204 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5205 For a local symbol, we want
5206 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5208 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5210 If we have a small constant, and this is a reference to
5211 an external symbol, we want
5212 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5213 addu $tempreg,$tempreg,$gp
5214 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5216 addiu $tempreg,$tempreg,<constant>
5217 For a local symbol, we want
5218 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5220 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5222 If we have a large constant, and this is a reference to
5223 an external symbol, we want
5224 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5225 addu $tempreg,$tempreg,$gp
5226 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5227 lui $at,<hiconstant>
5228 addiu $at,$at,<loconstant>
5229 addu $tempreg,$tempreg,$at
5230 For a local symbol, we want
5231 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5232 lui $at,<hiconstant>
5233 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5234 addu $tempreg,$tempreg,$at
5237 expr1.X_add_number = offset_expr.X_add_number;
5238 offset_expr.X_add_number = 0;
5239 relax_start (offset_expr.X_add_symbol);
5240 gpdelay = reg_needs_delay (mips_gp_register);
5241 if (expr1.X_add_number == 0 && breg == 0
5242 && (call || tempreg == PIC_CALL_REG))
5244 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5245 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5247 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
5248 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5249 tempreg, tempreg, mips_gp_register);
5250 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5251 tempreg, lw_reloc_type, tempreg);
5252 if (expr1.X_add_number == 0)
5256 /* We're going to put in an addu instruction using
5257 tempreg, so we may as well insert the nop right
5259 macro_build (NULL, "nop", "");
5262 else if (expr1.X_add_number >= -0x8000
5263 && expr1.X_add_number < 0x8000)
5265 macro_build (NULL, "nop", "");
5266 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5267 tempreg, tempreg, BFD_RELOC_LO16);
5273 /* If we are going to add in a base register, and the
5274 target register and the base register are the same,
5275 then we are using AT as a temporary register. Since
5276 we want to load the constant into AT, we add our
5277 current AT (from the global offset table) and the
5278 register into the register now, and pretend we were
5279 not using a base register. */
5284 assert (tempreg == AT);
5285 macro_build (NULL, "nop", "");
5286 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5291 /* Set mips_optimize around the lui instruction to avoid
5292 inserting an unnecessary nop after the lw. */
5293 hold_mips_optimize = mips_optimize;
5295 macro_build_lui (&expr1, AT);
5296 mips_optimize = hold_mips_optimize;
5298 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5299 AT, AT, BFD_RELOC_LO16);
5300 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
5304 offset_expr.X_add_number =
5305 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000;
5310 /* This is needed because this instruction uses $gp, but
5311 the first instruction on the main stream does not. */
5312 macro_build (NULL, "nop", "");
5315 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5316 local_reloc_type, mips_gp_register);
5317 if (expr1.X_add_number >= -0x8000
5318 && expr1.X_add_number < 0x8000)
5320 macro_build (NULL, "nop", "");
5321 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5322 tempreg, tempreg, BFD_RELOC_LO16);
5323 /* FIXME: If add_number is 0, and there was no base
5324 register, the external symbol case ended with a load,
5325 so if the symbol turns out to not be external, and
5326 the next instruction uses tempreg, an unnecessary nop
5327 will be inserted. */
5333 /* We must add in the base register now, as in the
5334 external symbol case. */
5335 assert (tempreg == AT);
5336 macro_build (NULL, "nop", "");
5337 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5340 /* We set breg to 0 because we have arranged to add
5341 it in in both cases. */
5345 macro_build_lui (&expr1, AT);
5346 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5347 AT, AT, BFD_RELOC_LO16);
5348 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5349 tempreg, tempreg, AT);
5353 else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
5355 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5356 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5357 int add_breg_early = 0;
5359 /* This is the large GOT case. If this is a reference to an
5360 external symbol, and there is no constant, we want
5361 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5362 add $tempreg,$tempreg,$gp
5363 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5364 or for lca or if tempreg is PIC_CALL_REG
5365 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5366 add $tempreg,$tempreg,$gp
5367 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5369 If we have a small constant, and this is a reference to
5370 an external symbol, we want
5371 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5372 add $tempreg,$tempreg,$gp
5373 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5374 addi $tempreg,$tempreg,<constant>
5376 If we have a large constant, and this is a reference to
5377 an external symbol, we want
5378 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5379 addu $tempreg,$tempreg,$gp
5380 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5381 lui $at,<hiconstant>
5382 addi $at,$at,<loconstant>
5383 add $tempreg,$tempreg,$at
5385 If we have NewABI, and we know it's a local symbol, we want
5386 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5387 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5388 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5390 relax_start (offset_expr.X_add_symbol);
5392 expr1.X_add_number = offset_expr.X_add_number;
5393 offset_expr.X_add_number = 0;
5395 if (expr1.X_add_number == 0 && breg == 0
5396 && (call || tempreg == PIC_CALL_REG))
5398 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5399 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5401 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
5402 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5403 tempreg, tempreg, mips_gp_register);
5404 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5405 tempreg, lw_reloc_type, tempreg);
5407 if (expr1.X_add_number == 0)
5409 else if (expr1.X_add_number >= -0x8000
5410 && expr1.X_add_number < 0x8000)
5412 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5413 tempreg, tempreg, BFD_RELOC_LO16);
5415 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
5419 /* If we are going to add in a base register, and the
5420 target register and the base register are the same,
5421 then we are using AT as a temporary register. Since
5422 we want to load the constant into AT, we add our
5423 current AT (from the global offset table) and the
5424 register into the register now, and pretend we were
5425 not using a base register. */
5430 assert (tempreg == AT);
5431 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5437 /* Set mips_optimize around the lui instruction to avoid
5438 inserting an unnecessary nop after the lw. */
5439 macro_build_lui (&expr1, AT);
5440 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5441 AT, AT, BFD_RELOC_LO16);
5442 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
5447 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5450 offset_expr.X_add_number = expr1.X_add_number;
5451 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5452 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
5453 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
5454 tempreg, BFD_RELOC_MIPS_GOT_OFST);
5457 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5458 treg, tempreg, breg);
5464 else if (mips_pic == EMBEDDED_PIC)
5467 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5469 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
5470 mips_gp_register, BFD_RELOC_GPREL16);
5479 if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
5480 s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu";
5482 s = ADDRESS_ADD_INSN;
5484 macro_build (NULL, s, "d,v,t", treg, tempreg, breg);
5493 /* The j instruction may not be used in PIC code, since it
5494 requires an absolute address. We convert it to a b
5496 if (mips_pic == NO_PIC)
5497 macro_build (&offset_expr, "j", "a");
5499 macro_build (&offset_expr, "b", "p");
5502 /* The jal instructions must be handled as macros because when
5503 generating PIC code they expand to multi-instruction
5504 sequences. Normally they are simple instructions. */
5509 if (mips_pic == NO_PIC
5510 || mips_pic == EMBEDDED_PIC)
5511 macro_build (NULL, "jalr", "d,s", dreg, sreg);
5512 else if (mips_pic == SVR4_PIC)
5514 if (sreg != PIC_CALL_REG)
5515 as_warn (_("MIPS PIC call to register other than $25"));
5517 macro_build (NULL, "jalr", "d,s", dreg, sreg);
5520 if (mips_cprestore_offset < 0)
5521 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5524 if (! mips_frame_reg_valid)
5526 as_warn (_("No .frame pseudo-op used in PIC code"));
5527 /* Quiet this warning. */
5528 mips_frame_reg_valid = 1;
5530 if (! mips_cprestore_valid)
5532 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5533 /* Quiet this warning. */
5534 mips_cprestore_valid = 1;
5536 expr1.X_add_number = mips_cprestore_offset;
5537 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
5540 HAVE_64BIT_ADDRESSES);
5550 if (mips_pic == NO_PIC)
5551 macro_build (&offset_expr, "jal", "a");
5552 else if (mips_pic == SVR4_PIC)
5554 /* If this is a reference to an external symbol, and we are
5555 using a small GOT, we want
5556 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5560 lw $gp,cprestore($sp)
5561 The cprestore value is set using the .cprestore
5562 pseudo-op. If we are using a big GOT, we want
5563 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5565 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5569 lw $gp,cprestore($sp)
5570 If the symbol is not external, we want
5571 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5573 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5576 lw $gp,cprestore($sp)
5578 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5579 sequences above, minus nops, unless the symbol is local,
5580 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5586 relax_start (offset_expr.X_add_symbol);
5587 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5588 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
5591 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5592 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
5598 relax_start (offset_expr.X_add_symbol);
5599 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
5600 BFD_RELOC_MIPS_CALL_HI16);
5601 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
5602 PIC_CALL_REG, mips_gp_register);
5603 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5604 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
5607 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5608 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
5610 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5611 PIC_CALL_REG, PIC_CALL_REG,
5612 BFD_RELOC_MIPS_GOT_OFST);
5616 macro_build_jalr (&offset_expr);
5620 relax_start (offset_expr.X_add_symbol);
5623 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5624 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
5626 macro_build (NULL, "nop", "");
5633 gpdelay = reg_needs_delay (mips_gp_register);
5634 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
5635 BFD_RELOC_MIPS_CALL_HI16);
5636 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
5637 PIC_CALL_REG, mips_gp_register);
5638 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5639 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
5641 macro_build (NULL, "nop", "");
5644 macro_build (NULL, "nop", "");
5646 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5647 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
5649 macro_build (NULL, "nop", "");
5650 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5651 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
5653 macro_build_jalr (&offset_expr);
5655 if (mips_cprestore_offset < 0)
5656 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5659 if (! mips_frame_reg_valid)
5661 as_warn (_("No .frame pseudo-op used in PIC code"));
5662 /* Quiet this warning. */
5663 mips_frame_reg_valid = 1;
5665 if (! mips_cprestore_valid)
5667 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5668 /* Quiet this warning. */
5669 mips_cprestore_valid = 1;
5671 if (mips_opts.noreorder)
5672 macro_build (NULL, "nop", "");
5673 expr1.X_add_number = mips_cprestore_offset;
5674 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
5677 HAVE_64BIT_ADDRESSES);
5681 else if (mips_pic == EMBEDDED_PIC)
5683 macro_build (&offset_expr, "bal", "p");
5684 /* The linker may expand the call to a longer sequence which
5685 uses $at, so we must break rather than return. */
5710 /* Itbl support may require additional care here. */
5715 /* Itbl support may require additional care here. */
5720 /* Itbl support may require additional care here. */
5725 /* Itbl support may require additional care here. */
5737 if (mips_opts.arch == CPU_R4650)
5739 as_bad (_("opcode not supported on this processor"));
5743 /* Itbl support may require additional care here. */
5748 /* Itbl support may require additional care here. */
5753 /* Itbl support may require additional care here. */
5773 if (breg == treg || coproc || lr)
5795 /* Itbl support may require additional care here. */
5800 /* Itbl support may require additional care here. */
5805 /* Itbl support may require additional care here. */
5810 /* Itbl support may require additional care here. */
5826 if (mips_opts.arch == CPU_R4650)
5828 as_bad (_("opcode not supported on this processor"));
5833 /* Itbl support may require additional care here. */
5837 /* Itbl support may require additional care here. */
5842 /* Itbl support may require additional care here. */
5854 /* Itbl support may require additional care here. */
5855 if (mask == M_LWC1_AB
5856 || mask == M_SWC1_AB
5857 || mask == M_LDC1_AB
5858 || mask == M_SDC1_AB
5867 /* Sign-extending 32-bit constants makes their handling easier.
5868 The HAVE_64BIT_GPRS... part is due to the linux kernel hack
5870 if ((! HAVE_64BIT_ADDRESSES
5871 && (! HAVE_64BIT_GPRS && offset_expr.X_op == O_constant))
5872 && (offset_expr.X_op == O_constant)
5873 && ! ((offset_expr.X_add_number & ~((bfd_vma) 0x7fffffff))
5874 == ~((bfd_vma) 0x7fffffff)))
5876 if (offset_expr.X_add_number & ~((bfd_vma) 0xffffffff))
5877 as_bad (_("constant too large"));
5879 offset_expr.X_add_number = (((offset_expr.X_add_number & 0xffffffff)
5880 ^ 0x80000000) - 0x80000000);
5883 /* For embedded PIC, we allow loads where the offset is calculated
5884 by subtracting a symbol in the current segment from an unknown
5885 symbol, relative to a base register, e.g.:
5886 <op> $treg, <sym>-<localsym>($breg)
5887 This is used by the compiler for switch statements. */
5888 if (mips_pic == EMBEDDED_PIC
5889 && offset_expr.X_op == O_subtract
5890 && (symbol_constant_p (offset_expr.X_op_symbol)
5891 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
5892 : (symbol_equated_p (offset_expr.X_op_symbol)
5894 (symbol_get_value_expression (offset_expr.X_op_symbol)
5898 && (offset_expr.X_add_number == 0
5899 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
5901 /* For this case, we output the instructions:
5902 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5903 addiu $tempreg,$tempreg,$breg
5904 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5905 If the relocation would fit entirely in 16 bits, it would be
5907 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5908 instead, but that seems quite difficult. */
5909 macro_build (&offset_expr, "lui", "t,u", tempreg,
5910 BFD_RELOC_PCREL_HI16_S);
5912 ((bfd_arch_bits_per_address (stdoutput) == 32
5913 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
5914 ? "addu" : "daddu"),
5915 "d,v,t", tempreg, tempreg, breg);
5916 macro_build (&offset_expr, s, fmt, treg,
5917 BFD_RELOC_PCREL_LO16, tempreg);
5923 if (offset_expr.X_op != O_constant
5924 && offset_expr.X_op != O_symbol)
5926 as_bad (_("expression too complex"));
5927 offset_expr.X_op = O_constant;
5930 /* A constant expression in PIC code can be handled just as it
5931 is in non PIC code. */
5932 if (mips_pic == NO_PIC
5933 || offset_expr.X_op == O_constant)
5935 /* If this is a reference to a GP relative symbol, and there
5936 is no base register, we want
5937 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5938 Otherwise, if there is no base register, we want
5939 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5940 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5941 If we have a constant, we need two instructions anyhow,
5942 so we always use the latter form.
5944 If we have a base register, and this is a reference to a
5945 GP relative symbol, we want
5946 addu $tempreg,$breg,$gp
5947 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5949 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5950 addu $tempreg,$tempreg,$breg
5951 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5952 With a constant we always use the latter case.
5954 With 64bit address space and no base register and $at usable,
5956 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5957 lui $at,<sym> (BFD_RELOC_HI16_S)
5958 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5961 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5962 If we have a base register, we want
5963 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5964 lui $at,<sym> (BFD_RELOC_HI16_S)
5965 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5969 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5971 Without $at we can't generate the optimal path for superscalar
5972 processors here since this would require two temporary registers.
5973 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5974 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5976 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5978 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5979 If we have a base register, we want
5980 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5981 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5983 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5985 daddu $tempreg,$tempreg,$breg
5986 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5988 If we have 64-bit addresses, as an optimization, for
5989 addresses which are 32-bit constants (e.g. kseg0/kseg1
5990 addresses) we fall back to the 32-bit address generation
5991 mechanism since it is more efficient. Note that due to
5992 the signed offset used by memory operations, the 32-bit
5993 range is shifted down by 32768 here. This code should
5994 probably attempt to generate 64-bit constants more
5995 efficiently in general.
5997 As an extension for architectures with 64-bit registers,
5998 we don't truncate 64-bit addresses given as literal
5999 constants down to 32 bits, to support existing practice
6000 in the mips64 Linux (the kernel), that compiles source
6001 files with -mabi=64, assembling them as o32 or n32 (with
6002 -Wa,-32 or -Wa,-n32). This is not beautiful, but since
6003 the whole kernel is loaded into a memory region that is
6004 addressable with sign-extended 32-bit addresses, it is
6005 wasteful to compute the upper 32 bits of every
6006 non-literal address, that takes more space and time.
6007 Some day this should probably be implemented as an
6008 assembler option, such that the kernel doesn't have to
6009 use such ugly hacks, even though it will still have to
6010 end up converting the binary to ELF32 for a number of
6011 platforms whose boot loaders don't support ELF64
6013 if ((HAVE_64BIT_ADDRESSES
6014 && ! (offset_expr.X_op == O_constant
6015 && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
6017 && offset_expr.X_op == O_constant
6018 && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
6020 /* We don't do GP optimization for now because RELAX_ENCODE can't
6021 hold the data for such large chunks. */
6023 if (used_at == 0 && ! mips_opts.noat)
6025 macro_build (&offset_expr, "lui", "t,u", tempreg,
6026 BFD_RELOC_MIPS_HIGHEST);
6027 macro_build (&offset_expr, "lui", "t,u", AT,
6029 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6030 tempreg, BFD_RELOC_MIPS_HIGHER);
6032 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
6033 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
6034 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
6035 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
6041 macro_build (&offset_expr, "lui", "t,u", tempreg,
6042 BFD_RELOC_MIPS_HIGHEST);
6043 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6044 tempreg, BFD_RELOC_MIPS_HIGHER);
6045 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6046 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6047 tempreg, BFD_RELOC_HI16_S);
6048 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6050 macro_build (NULL, "daddu", "d,v,t",
6051 tempreg, tempreg, breg);
6052 macro_build (&offset_expr, s, fmt, treg,
6053 BFD_RELOC_LO16, tempreg);
6059 if (offset_expr.X_op == O_constant
6060 && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))
6061 as_bad (_("load/store address overflow (max 32 bits)"));
6065 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6066 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
6068 relax_start (offset_expr.X_add_symbol);
6069 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
6074 macro_build_lui (&offset_expr, tempreg);
6075 macro_build (&offset_expr, s, fmt, treg,
6076 BFD_RELOC_LO16, tempreg);
6077 if (mips_relax.sequence)
6082 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6083 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
6085 relax_start (offset_expr.X_add_symbol);
6086 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6087 tempreg, breg, mips_gp_register);
6088 macro_build (&offset_expr, s, fmt, treg,
6089 BFD_RELOC_GPREL16, tempreg);
6092 macro_build_lui (&offset_expr, tempreg);
6093 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6094 tempreg, tempreg, breg);
6095 macro_build (&offset_expr, s, fmt, treg,
6096 BFD_RELOC_LO16, tempreg);
6097 if (mips_relax.sequence)
6101 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6103 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6105 /* If this is a reference to an external symbol, we want
6106 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6108 <op> $treg,0($tempreg)
6110 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6112 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6113 <op> $treg,0($tempreg)
6116 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6117 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6119 If there is a base register, we add it to $tempreg before
6120 the <op>. If there is a constant, we stick it in the
6121 <op> instruction. We don't handle constants larger than
6122 16 bits, because we have no way to load the upper 16 bits
6123 (actually, we could handle them for the subset of cases
6124 in which we are not using $at). */
6125 assert (offset_expr.X_op == O_symbol);
6128 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6129 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6131 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6132 tempreg, tempreg, breg);
6133 macro_build (&offset_expr, s, fmt, treg,
6134 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6141 expr1.X_add_number = offset_expr.X_add_number;
6142 offset_expr.X_add_number = 0;
6143 if (expr1.X_add_number < -0x8000
6144 || expr1.X_add_number >= 0x8000)
6145 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6146 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6147 lw_reloc_type, mips_gp_register);
6148 macro_build (NULL, "nop", "");
6149 relax_start (offset_expr.X_add_symbol);
6151 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6152 tempreg, BFD_RELOC_LO16);
6155 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6156 tempreg, tempreg, breg);
6157 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6159 else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
6163 /* If this is a reference to an external symbol, we want
6164 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6165 addu $tempreg,$tempreg,$gp
6166 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6167 <op> $treg,0($tempreg)
6169 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6171 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6172 <op> $treg,0($tempreg)
6173 If there is a base register, we add it to $tempreg before
6174 the <op>. If there is a constant, we stick it in the
6175 <op> instruction. We don't handle constants larger than
6176 16 bits, because we have no way to load the upper 16 bits
6177 (actually, we could handle them for the subset of cases
6178 in which we are not using $at). */
6179 assert (offset_expr.X_op == O_symbol);
6180 expr1.X_add_number = offset_expr.X_add_number;
6181 offset_expr.X_add_number = 0;
6182 if (expr1.X_add_number < -0x8000
6183 || expr1.X_add_number >= 0x8000)
6184 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6185 gpdelay = reg_needs_delay (mips_gp_register);
6186 relax_start (offset_expr.X_add_symbol);
6187 macro_build (&offset_expr, "lui", "t,u", tempreg,
6188 BFD_RELOC_MIPS_GOT_HI16);
6189 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
6191 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6192 BFD_RELOC_MIPS_GOT_LO16, tempreg);
6195 macro_build (NULL, "nop", "");
6196 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6197 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6198 macro_build (NULL, "nop", "");
6199 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6200 tempreg, BFD_RELOC_LO16);
6204 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6205 tempreg, tempreg, breg);
6206 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6208 else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
6210 /* If this is a reference to an external symbol, we want
6211 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6212 add $tempreg,$tempreg,$gp
6213 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6214 <op> $treg,<ofst>($tempreg)
6215 Otherwise, for local symbols, we want:
6216 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6217 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6218 assert (offset_expr.X_op == O_symbol);
6219 expr1.X_add_number = offset_expr.X_add_number;
6220 offset_expr.X_add_number = 0;
6221 if (expr1.X_add_number < -0x8000
6222 || expr1.X_add_number >= 0x8000)
6223 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6224 relax_start (offset_expr.X_add_symbol);
6225 macro_build (&offset_expr, "lui", "t,u", tempreg,
6226 BFD_RELOC_MIPS_GOT_HI16);
6227 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
6229 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6230 BFD_RELOC_MIPS_GOT_LO16, tempreg);
6232 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6233 tempreg, tempreg, breg);
6234 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6237 offset_expr.X_add_number = expr1.X_add_number;
6238 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6239 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6241 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6242 tempreg, tempreg, breg);
6243 macro_build (&offset_expr, s, fmt, treg,
6244 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6247 else if (mips_pic == EMBEDDED_PIC)
6249 /* If there is no base register, we want
6250 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6251 If there is a base register, we want
6252 addu $tempreg,$breg,$gp
6253 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6255 assert (offset_expr.X_op == O_symbol);
6258 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
6264 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6265 tempreg, breg, mips_gp_register);
6266 macro_build (&offset_expr, s, fmt, treg,
6267 BFD_RELOC_GPREL16, tempreg);
6280 load_register (treg, &imm_expr, 0);
6284 load_register (treg, &imm_expr, 1);
6288 if (imm_expr.X_op == O_constant)
6290 load_register (AT, &imm_expr, 0);
6291 macro_build (NULL, "mtc1", "t,G", AT, treg);
6296 assert (offset_expr.X_op == O_symbol
6297 && strcmp (segment_name (S_GET_SEGMENT
6298 (offset_expr.X_add_symbol)),
6300 && offset_expr.X_add_number == 0);
6301 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
6302 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6307 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6308 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6309 order 32 bits of the value and the low order 32 bits are either
6310 zero or in OFFSET_EXPR. */
6311 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6313 if (HAVE_64BIT_GPRS)
6314 load_register (treg, &imm_expr, 1);
6319 if (target_big_endian)
6331 load_register (hreg, &imm_expr, 0);
6334 if (offset_expr.X_op == O_absent)
6335 move_register (lreg, 0);
6338 assert (offset_expr.X_op == O_constant);
6339 load_register (lreg, &offset_expr, 0);
6346 /* We know that sym is in the .rdata section. First we get the
6347 upper 16 bits of the address. */
6348 if (mips_pic == NO_PIC)
6350 macro_build_lui (&offset_expr, AT);
6352 else if (mips_pic == SVR4_PIC)
6354 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6355 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6357 else if (mips_pic == EMBEDDED_PIC)
6359 /* For embedded PIC we pick up the entire address off $gp in
6360 a single instruction. */
6361 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT,
6362 mips_gp_register, BFD_RELOC_GPREL16);
6363 offset_expr.X_op = O_constant;
6364 offset_expr.X_add_number = 0;
6369 /* Now we load the register(s). */
6370 if (HAVE_64BIT_GPRS)
6371 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
6374 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
6377 /* FIXME: How in the world do we deal with the possible
6379 offset_expr.X_add_number += 4;
6380 macro_build (&offset_expr, "lw", "t,o(b)",
6381 treg + 1, BFD_RELOC_LO16, AT);
6387 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6388 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6389 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6390 the value and the low order 32 bits are either zero or in
6392 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6394 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
6395 if (HAVE_64BIT_FPRS)
6397 assert (HAVE_64BIT_GPRS);
6398 macro_build (NULL, "dmtc1", "t,S", AT, treg);
6402 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
6403 if (offset_expr.X_op == O_absent)
6404 macro_build (NULL, "mtc1", "t,G", 0, treg);
6407 assert (offset_expr.X_op == O_constant);
6408 load_register (AT, &offset_expr, 0);
6409 macro_build (NULL, "mtc1", "t,G", AT, treg);
6415 assert (offset_expr.X_op == O_symbol
6416 && offset_expr.X_add_number == 0);
6417 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
6418 if (strcmp (s, ".lit8") == 0)
6420 if (mips_opts.isa != ISA_MIPS1)
6422 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
6423 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6426 breg = mips_gp_register;
6427 r = BFD_RELOC_MIPS_LITERAL;
6432 assert (strcmp (s, RDATA_SECTION_NAME) == 0);
6433 if (mips_pic == SVR4_PIC)
6434 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6435 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6438 /* FIXME: This won't work for a 64 bit address. */
6439 macro_build_lui (&offset_expr, AT);
6442 if (mips_opts.isa != ISA_MIPS1)
6444 macro_build (&offset_expr, "ldc1", "T,o(b)",
6445 treg, BFD_RELOC_LO16, AT);
6454 if (mips_opts.arch == CPU_R4650)
6456 as_bad (_("opcode not supported on this processor"));
6459 /* Even on a big endian machine $fn comes before $fn+1. We have
6460 to adjust when loading from memory. */
6463 assert (mips_opts.isa == ISA_MIPS1);
6464 macro_build (&offset_expr, "lwc1", "T,o(b)",
6465 target_big_endian ? treg + 1 : treg, r, breg);
6466 /* FIXME: A possible overflow which I don't know how to deal
6468 offset_expr.X_add_number += 4;
6469 macro_build (&offset_expr, "lwc1", "T,o(b)",
6470 target_big_endian ? treg : treg + 1, r, breg);
6478 * The MIPS assembler seems to check for X_add_number not
6479 * being double aligned and generating:
6482 * addiu at,at,%lo(foo+1)
6485 * But, the resulting address is the same after relocation so why
6486 * generate the extra instruction?
6488 if (mips_opts.arch == CPU_R4650)
6490 as_bad (_("opcode not supported on this processor"));
6493 /* Itbl support may require additional care here. */
6495 if (mips_opts.isa != ISA_MIPS1)
6506 if (mips_opts.arch == CPU_R4650)
6508 as_bad (_("opcode not supported on this processor"));
6512 if (mips_opts.isa != ISA_MIPS1)
6520 /* Itbl support may require additional care here. */
6525 if (HAVE_64BIT_GPRS)
6536 if (HAVE_64BIT_GPRS)
6546 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6547 loads for the case of doing a pair of loads to simulate an 'ld'.
6548 This is not currently done by the compiler, and assembly coders
6549 writing embedded-pic code can cope. */
6551 if (offset_expr.X_op != O_symbol
6552 && offset_expr.X_op != O_constant)
6554 as_bad (_("expression too complex"));
6555 offset_expr.X_op = O_constant;
6558 /* Even on a big endian machine $fn comes before $fn+1. We have
6559 to adjust when loading from memory. We set coproc if we must
6560 load $fn+1 first. */
6561 /* Itbl support may require additional care here. */
6562 if (! target_big_endian)
6565 if (mips_pic == NO_PIC
6566 || offset_expr.X_op == O_constant)
6568 /* If this is a reference to a GP relative symbol, we want
6569 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6570 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6571 If we have a base register, we use this
6573 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6574 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6575 If this is not a GP relative symbol, we want
6576 lui $at,<sym> (BFD_RELOC_HI16_S)
6577 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6578 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6579 If there is a base register, we add it to $at after the
6580 lui instruction. If there is a constant, we always use
6582 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6583 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6587 relax_start (offset_expr.X_add_symbol);
6590 tempreg = mips_gp_register;
6595 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6596 AT, breg, mips_gp_register);
6601 /* Itbl support may require additional care here. */
6602 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6603 BFD_RELOC_GPREL16, tempreg);
6604 offset_expr.X_add_number += 4;
6606 /* Set mips_optimize to 2 to avoid inserting an
6608 hold_mips_optimize = mips_optimize;
6610 /* Itbl support may require additional care here. */
6611 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6612 BFD_RELOC_GPREL16, tempreg);
6613 mips_optimize = hold_mips_optimize;
6617 /* We just generated two relocs. When tc_gen_reloc
6618 handles this case, it will skip the first reloc and
6619 handle the second. The second reloc already has an
6620 extra addend of 4, which we added above. We must
6621 subtract it out, and then subtract another 4 to make
6622 the first reloc come out right. The second reloc
6623 will come out right because we are going to add 4 to
6624 offset_expr when we build its instruction below.
6626 If we have a symbol, then we don't want to include
6627 the offset, because it will wind up being included
6628 when we generate the reloc. */
6630 if (offset_expr.X_op == O_constant)
6631 offset_expr.X_add_number -= 8;
6634 offset_expr.X_add_number = -4;
6635 offset_expr.X_op = O_constant;
6638 macro_build_lui (&offset_expr, AT);
6640 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6641 /* Itbl support may require additional care here. */
6642 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6643 BFD_RELOC_LO16, AT);
6644 /* FIXME: How do we handle overflow here? */
6645 offset_expr.X_add_number += 4;
6646 /* Itbl support may require additional care here. */
6647 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6648 BFD_RELOC_LO16, AT);
6649 if (mips_relax.sequence)
6652 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6654 /* If this is a reference to an external symbol, we want
6655 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6660 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6662 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6663 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6664 If there is a base register we add it to $at before the
6665 lwc1 instructions. If there is a constant we include it
6666 in the lwc1 instructions. */
6668 expr1.X_add_number = offset_expr.X_add_number;
6669 if (expr1.X_add_number < -0x8000
6670 || expr1.X_add_number >= 0x8000 - 4)
6671 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6672 load_got_offset (AT, &offset_expr);
6673 macro_build (NULL, "nop", "");
6675 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6677 /* Set mips_optimize to 2 to avoid inserting an undesired
6679 hold_mips_optimize = mips_optimize;
6682 /* Itbl support may require additional care here. */
6683 relax_start (offset_expr.X_add_symbol);
6684 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
6685 BFD_RELOC_LO16, AT);
6686 expr1.X_add_number += 4;
6687 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
6688 BFD_RELOC_LO16, AT);
6690 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6691 BFD_RELOC_LO16, AT);
6692 offset_expr.X_add_number += 4;
6693 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6694 BFD_RELOC_LO16, AT);
6697 mips_optimize = hold_mips_optimize;
6699 else if (mips_pic == SVR4_PIC)
6703 /* If this is a reference to an external symbol, we want
6704 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6706 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6711 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6713 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6714 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6715 If there is a base register we add it to $at before the
6716 lwc1 instructions. If there is a constant we include it
6717 in the lwc1 instructions. */
6719 expr1.X_add_number = offset_expr.X_add_number;
6720 offset_expr.X_add_number = 0;
6721 if (expr1.X_add_number < -0x8000
6722 || expr1.X_add_number >= 0x8000 - 4)
6723 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6724 gpdelay = reg_needs_delay (mips_gp_register);
6725 relax_start (offset_expr.X_add_symbol);
6726 macro_build (&offset_expr, "lui", "t,u",
6727 AT, BFD_RELOC_MIPS_GOT_HI16);
6728 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6729 AT, AT, mips_gp_register);
6730 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6731 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
6732 macro_build (NULL, "nop", "");
6734 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6735 /* Itbl support may require additional care here. */
6736 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
6737 BFD_RELOC_LO16, AT);
6738 expr1.X_add_number += 4;
6740 /* Set mips_optimize to 2 to avoid inserting an undesired
6742 hold_mips_optimize = mips_optimize;
6744 /* Itbl support may require additional care here. */
6745 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
6746 BFD_RELOC_LO16, AT);
6747 mips_optimize = hold_mips_optimize;
6748 expr1.X_add_number -= 4;
6751 offset_expr.X_add_number = expr1.X_add_number;
6753 macro_build (NULL, "nop", "");
6754 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6755 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6756 macro_build (NULL, "nop", "");
6758 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6759 /* Itbl support may require additional care here. */
6760 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6761 BFD_RELOC_LO16, AT);
6762 offset_expr.X_add_number += 4;
6764 /* Set mips_optimize to 2 to avoid inserting an undesired
6766 hold_mips_optimize = mips_optimize;
6768 /* Itbl support may require additional care here. */
6769 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6770 BFD_RELOC_LO16, AT);
6771 mips_optimize = hold_mips_optimize;
6774 else if (mips_pic == EMBEDDED_PIC)
6776 /* If there is no base register, we use
6777 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6778 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6779 If we have a base register, we use
6781 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6782 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6786 tempreg = mips_gp_register;
6791 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6792 AT, breg, mips_gp_register);
6797 /* Itbl support may require additional care here. */
6798 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6799 BFD_RELOC_GPREL16, tempreg);
6800 offset_expr.X_add_number += 4;
6801 /* Itbl support may require additional care here. */
6802 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6803 BFD_RELOC_GPREL16, tempreg);
6819 assert (HAVE_32BIT_ADDRESSES);
6820 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
6821 offset_expr.X_add_number += 4;
6822 macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg);
6825 /* New code added to support COPZ instructions.
6826 This code builds table entries out of the macros in mip_opcodes.
6827 R4000 uses interlocks to handle coproc delays.
6828 Other chips (like the R3000) require nops to be inserted for delays.
6830 FIXME: Currently, we require that the user handle delays.
6831 In order to fill delay slots for non-interlocked chips,
6832 we must have a way to specify delays based on the coprocessor.
6833 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6834 What are the side-effects of the cop instruction?
6835 What cache support might we have and what are its effects?
6836 Both coprocessor & memory require delays. how long???
6837 What registers are read/set/modified?
6839 If an itbl is provided to interpret cop instructions,
6840 this knowledge can be encoded in the itbl spec. */
6854 /* For now we just do C (same as Cz). The parameter will be
6855 stored in insn_opcode by mips_ip. */
6856 macro_build (NULL, s, "C", ip->insn_opcode);
6860 move_register (dreg, sreg);
6863 #ifdef LOSING_COMPILER
6865 /* Try and see if this is a new itbl instruction.
6866 This code builds table entries out of the macros in mip_opcodes.
6867 FIXME: For now we just assemble the expression and pass it's
6868 value along as a 32-bit immediate.
6869 We may want to have the assembler assemble this value,
6870 so that we gain the assembler's knowledge of delay slots,
6872 Would it be more efficient to use mask (id) here? */
6873 if (itbl_have_entries
6874 && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
6876 s = ip->insn_mo->name;
6878 coproc = ITBL_DECODE_PNUM (immed_expr);;
6879 macro_build (&immed_expr, s, "C");
6886 as_warn (_("Macro used $at after \".set noat\""));
6890 macro2 (struct mips_cl_insn *ip)
6892 register int treg, sreg, dreg, breg;
6907 bfd_reloc_code_real_type r;
6909 treg = (ip->insn_opcode >> 16) & 0x1f;
6910 dreg = (ip->insn_opcode >> 11) & 0x1f;
6911 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
6912 mask = ip->insn_mo->mask;
6914 expr1.X_op = O_constant;
6915 expr1.X_op_symbol = NULL;
6916 expr1.X_add_symbol = NULL;
6917 expr1.X_add_number = 1;
6921 #endif /* LOSING_COMPILER */
6926 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
6927 macro_build (NULL, "mflo", "d", dreg);
6933 /* The MIPS assembler some times generates shifts and adds. I'm
6934 not trying to be that fancy. GCC should do this for us
6936 load_register (AT, &imm_expr, dbl);
6937 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
6938 macro_build (NULL, "mflo", "d", dreg);
6951 mips_emit_delays (TRUE);
6952 ++mips_opts.noreorder;
6953 mips_any_noreorder = 1;
6955 load_register (AT, &imm_expr, dbl);
6956 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
6957 macro_build (NULL, "mflo", "d", dreg);
6958 macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
6959 macro_build (NULL, "mfhi", "d", AT);
6961 macro_build (NULL, "tne", "s,t,q", dreg, AT, 6);
6964 expr1.X_add_number = 8;
6965 macro_build (&expr1, "beq", "s,t,p", dreg, AT);
6966 macro_build (NULL, "nop", "", 0);
6967 macro_build (NULL, "break", "c", 6);
6969 --mips_opts.noreorder;
6970 macro_build (NULL, "mflo", "d", dreg);
6983 mips_emit_delays (TRUE);
6984 ++mips_opts.noreorder;
6985 mips_any_noreorder = 1;
6987 load_register (AT, &imm_expr, dbl);
6988 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
6989 sreg, imm ? AT : treg);
6990 macro_build (NULL, "mfhi", "d", AT);
6991 macro_build (NULL, "mflo", "d", dreg);
6993 macro_build (NULL, "tne", "s,t,q", AT, 0, 6);
6996 expr1.X_add_number = 8;
6997 macro_build (&expr1, "beq", "s,t,p", AT, 0);
6998 macro_build (NULL, "nop", "", 0);
6999 macro_build (NULL, "break", "c", 6);
7001 --mips_opts.noreorder;
7005 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7017 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
7018 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
7023 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
7024 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
7025 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
7026 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7030 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7042 macro_build (NULL, "negu", "d,w", tempreg, treg);
7043 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
7048 macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
7049 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
7050 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
7051 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7059 if (imm_expr.X_op != O_constant)
7060 as_bad (_("Improper rotate count"));
7061 rot = imm_expr.X_add_number & 0x3f;
7062 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7064 rot = (64 - rot) & 0x3f;
7066 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7068 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7073 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7076 l = (rot < 0x20) ? "dsll" : "dsll32";
7077 r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
7079 macro_build (NULL, l, "d,w,<", AT, sreg, rot);
7080 macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7081 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7089 if (imm_expr.X_op != O_constant)
7090 as_bad (_("Improper rotate count"));
7091 rot = imm_expr.X_add_number & 0x1f;
7092 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7094 macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f);
7099 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7102 macro_build (NULL, "sll", "d,w,<", AT, sreg, rot);
7103 macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7104 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7109 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7111 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
7114 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
7115 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
7116 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
7117 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7121 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7123 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
7126 macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
7127 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
7128 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
7129 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7137 if (imm_expr.X_op != O_constant)
7138 as_bad (_("Improper rotate count"));
7139 rot = imm_expr.X_add_number & 0x3f;
7140 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7143 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7145 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7150 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7153 r = (rot < 0x20) ? "dsrl" : "dsrl32";
7154 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7156 macro_build (NULL, r, "d,w,<", AT, sreg, rot);
7157 macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7158 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7166 if (imm_expr.X_op != O_constant)
7167 as_bad (_("Improper rotate count"));
7168 rot = imm_expr.X_add_number & 0x1f;
7169 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7171 macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot);
7176 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7179 macro_build (NULL, "srl", "d,w,<", AT, sreg, rot);
7180 macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7181 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7186 if (mips_opts.arch == CPU_R4650)
7188 as_bad (_("opcode not supported on this processor"));
7191 assert (mips_opts.isa == ISA_MIPS1);
7192 /* Even on a big endian machine $fn comes before $fn+1. We have
7193 to adjust when storing to memory. */
7194 macro_build (&offset_expr, "swc1", "T,o(b)",
7195 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
7196 offset_expr.X_add_number += 4;
7197 macro_build (&offset_expr, "swc1", "T,o(b)",
7198 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
7203 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
7205 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7208 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7209 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7214 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7216 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7221 as_warn (_("Instruction %s: result is always false"),
7223 move_register (dreg, 0);
7226 if (imm_expr.X_op == O_constant
7227 && imm_expr.X_add_number >= 0
7228 && imm_expr.X_add_number < 0x10000)
7230 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7233 else if (imm_expr.X_op == O_constant
7234 && imm_expr.X_add_number > -0x8000
7235 && imm_expr.X_add_number < 0)
7237 imm_expr.X_add_number = -imm_expr.X_add_number;
7238 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7239 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7244 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7245 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7248 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7253 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
7259 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
7260 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7263 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
7265 if (imm_expr.X_op == O_constant
7266 && imm_expr.X_add_number >= -0x8000
7267 && imm_expr.X_add_number < 0x8000)
7269 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
7270 dreg, sreg, BFD_RELOC_LO16);
7275 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7276 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
7280 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7285 case M_SGT: /* sreg > treg <==> treg < sreg */
7291 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7294 case M_SGT_I: /* sreg > I <==> I < sreg */
7300 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7301 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7304 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7310 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7311 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7314 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7320 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7321 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7322 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7326 if (imm_expr.X_op == O_constant
7327 && imm_expr.X_add_number >= -0x8000
7328 && imm_expr.X_add_number < 0x8000)
7330 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7333 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7334 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
7338 if (imm_expr.X_op == O_constant
7339 && imm_expr.X_add_number >= -0x8000
7340 && imm_expr.X_add_number < 0x8000)
7342 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
7346 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7347 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
7352 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
7354 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
7357 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7358 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
7363 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7365 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
7370 as_warn (_("Instruction %s: result is always true"),
7372 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
7373 dreg, 0, BFD_RELOC_LO16);
7376 if (imm_expr.X_op == O_constant
7377 && imm_expr.X_add_number >= 0
7378 && imm_expr.X_add_number < 0x10000)
7380 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7383 else if (imm_expr.X_op == O_constant
7384 && imm_expr.X_add_number > -0x8000
7385 && imm_expr.X_add_number < 0)
7387 imm_expr.X_add_number = -imm_expr.X_add_number;
7388 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7389 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7394 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7395 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7398 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
7406 if (imm_expr.X_op == O_constant
7407 && imm_expr.X_add_number > -0x8000
7408 && imm_expr.X_add_number <= 0x8000)
7410 imm_expr.X_add_number = -imm_expr.X_add_number;
7411 macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j",
7412 dreg, sreg, BFD_RELOC_LO16);
7415 load_register (AT, &imm_expr, dbl);
7416 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
7422 if (imm_expr.X_op == O_constant
7423 && imm_expr.X_add_number > -0x8000
7424 && imm_expr.X_add_number <= 0x8000)
7426 imm_expr.X_add_number = -imm_expr.X_add_number;
7427 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j",
7428 dreg, sreg, BFD_RELOC_LO16);
7431 load_register (AT, &imm_expr, dbl);
7432 macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
7453 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7454 macro_build (NULL, s, "s,t", sreg, AT);
7459 assert (mips_opts.isa == ISA_MIPS1);
7460 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
7461 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
7464 * Is the double cfc1 instruction a bug in the mips assembler;
7465 * or is there a reason for it?
7467 mips_emit_delays (TRUE);
7468 ++mips_opts.noreorder;
7469 mips_any_noreorder = 1;
7470 macro_build (NULL, "cfc1", "t,G", treg, RA);
7471 macro_build (NULL, "cfc1", "t,G", treg, RA);
7472 macro_build (NULL, "nop", "");
7473 expr1.X_add_number = 3;
7474 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
7475 expr1.X_add_number = 2;
7476 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
7477 macro_build (NULL, "ctc1", "t,G", AT, RA);
7478 macro_build (NULL, "nop", "");
7479 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
7481 macro_build (NULL, "ctc1", "t,G", treg, RA);
7482 macro_build (NULL, "nop", "");
7483 --mips_opts.noreorder;
7492 if (offset_expr.X_add_number >= 0x7fff)
7493 as_bad (_("operand overflow"));
7494 if (! target_big_endian)
7495 ++offset_expr.X_add_number;
7496 macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg);
7497 if (! target_big_endian)
7498 --offset_expr.X_add_number;
7500 ++offset_expr.X_add_number;
7501 macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg);
7502 macro_build (NULL, "sll", "d,w,<", AT, AT, 8);
7503 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
7516 if (offset_expr.X_add_number >= 0x8000 - off)
7517 as_bad (_("operand overflow"));
7522 if (! target_big_endian)
7523 offset_expr.X_add_number += off;
7524 macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
7525 if (! target_big_endian)
7526 offset_expr.X_add_number -= off;
7528 offset_expr.X_add_number += off;
7529 macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
7531 /* If necessary, move the result in tempreg the final destination. */
7532 if (treg == tempreg)
7534 /* Protect second load's delay slot. */
7535 if (!gpr_interlocks)
7536 macro_build (NULL, "nop", "");
7537 move_register (treg, tempreg);
7551 load_address (AT, &offset_expr, &used_at);
7553 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7554 if (! target_big_endian)
7555 expr1.X_add_number = off;
7557 expr1.X_add_number = 0;
7558 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7559 if (! target_big_endian)
7560 expr1.X_add_number = 0;
7562 expr1.X_add_number = off;
7563 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7569 load_address (AT, &offset_expr, &used_at);
7571 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7572 if (target_big_endian)
7573 expr1.X_add_number = 0;
7574 macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
7575 treg, BFD_RELOC_LO16, AT);
7576 if (target_big_endian)
7577 expr1.X_add_number = 1;
7579 expr1.X_add_number = 0;
7580 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
7581 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
7582 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
7586 if (offset_expr.X_add_number >= 0x7fff)
7587 as_bad (_("operand overflow"));
7588 if (target_big_endian)
7589 ++offset_expr.X_add_number;
7590 macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg);
7591 macro_build (NULL, "srl", "d,w,<", AT, treg, 8);
7592 if (target_big_endian)
7593 --offset_expr.X_add_number;
7595 ++offset_expr.X_add_number;
7596 macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg);
7609 if (offset_expr.X_add_number >= 0x8000 - off)
7610 as_bad (_("operand overflow"));
7611 if (! target_big_endian)
7612 offset_expr.X_add_number += off;
7613 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
7614 if (! target_big_endian)
7615 offset_expr.X_add_number -= off;
7617 offset_expr.X_add_number += off;
7618 macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg);
7632 load_address (AT, &offset_expr, &used_at);
7634 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7635 if (! target_big_endian)
7636 expr1.X_add_number = off;
7638 expr1.X_add_number = 0;
7639 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7640 if (! target_big_endian)
7641 expr1.X_add_number = 0;
7643 expr1.X_add_number = off;
7644 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7649 load_address (AT, &offset_expr, &used_at);
7651 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7652 if (! target_big_endian)
7653 expr1.X_add_number = 0;
7654 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7655 macro_build (NULL, "srl", "d,w,<", treg, treg, 8);
7656 if (! target_big_endian)
7657 expr1.X_add_number = 1;
7659 expr1.X_add_number = 0;
7660 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7661 if (! target_big_endian)
7662 expr1.X_add_number = 0;
7664 expr1.X_add_number = 1;
7665 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
7666 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
7667 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
7671 /* FIXME: Check if this is one of the itbl macros, since they
7672 are added dynamically. */
7673 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
7677 as_warn (_("Macro used $at after \".set noat\""));
7680 /* Implement macros in mips16 mode. */
7683 mips16_macro (struct mips_cl_insn *ip)
7686 int xreg, yreg, zreg, tmp;
7689 const char *s, *s2, *s3;
7691 mask = ip->insn_mo->mask;
7693 xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
7694 yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY;
7695 zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
7697 expr1.X_op = O_constant;
7698 expr1.X_op_symbol = NULL;
7699 expr1.X_add_symbol = NULL;
7700 expr1.X_add_number = 1;
7719 mips_emit_delays (TRUE);
7720 ++mips_opts.noreorder;
7721 mips_any_noreorder = 1;
7722 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
7723 expr1.X_add_number = 2;
7724 macro_build (&expr1, "bnez", "x,p", yreg);
7725 macro_build (NULL, "break", "6", 7);
7727 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7728 since that causes an overflow. We should do that as well,
7729 but I don't see how to do the comparisons without a temporary
7731 --mips_opts.noreorder;
7732 macro_build (NULL, s, "x", zreg);
7751 mips_emit_delays (TRUE);
7752 ++mips_opts.noreorder;
7753 mips_any_noreorder = 1;
7754 macro_build (NULL, s, "0,x,y", xreg, yreg);
7755 expr1.X_add_number = 2;
7756 macro_build (&expr1, "bnez", "x,p", yreg);
7757 macro_build (NULL, "break", "6", 7);
7758 --mips_opts.noreorder;
7759 macro_build (NULL, s2, "x", zreg);
7765 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
7766 macro_build (NULL, "mflo", "x", zreg);
7774 if (imm_expr.X_op != O_constant)
7775 as_bad (_("Unsupported large constant"));
7776 imm_expr.X_add_number = -imm_expr.X_add_number;
7777 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
7781 if (imm_expr.X_op != O_constant)
7782 as_bad (_("Unsupported large constant"));
7783 imm_expr.X_add_number = -imm_expr.X_add_number;
7784 macro_build (&imm_expr, "addiu", "x,k", xreg);
7788 if (imm_expr.X_op != O_constant)
7789 as_bad (_("Unsupported large constant"));
7790 imm_expr.X_add_number = -imm_expr.X_add_number;
7791 macro_build (&imm_expr, "daddiu", "y,j", yreg);
7813 goto do_reverse_branch;
7817 goto do_reverse_branch;
7829 goto do_reverse_branch;
7840 macro_build (NULL, s, "x,y", xreg, yreg);
7841 macro_build (&offset_expr, s2, "p");
7868 goto do_addone_branch_i;
7873 goto do_addone_branch_i;
7888 goto do_addone_branch_i;
7895 if (imm_expr.X_op != O_constant)
7896 as_bad (_("Unsupported large constant"));
7897 ++imm_expr.X_add_number;
7900 macro_build (&imm_expr, s, s3, xreg);
7901 macro_build (&offset_expr, s2, "p");
7905 expr1.X_add_number = 0;
7906 macro_build (&expr1, "slti", "x,8", yreg);
7908 move_register (xreg, yreg);
7909 expr1.X_add_number = 2;
7910 macro_build (&expr1, "bteqz", "p");
7911 macro_build (NULL, "neg", "x,w", xreg, xreg);
7915 /* For consistency checking, verify that all bits are specified either
7916 by the match/mask part of the instruction definition, or by the
7919 validate_mips_insn (const struct mips_opcode *opc)
7921 const char *p = opc->args;
7923 unsigned long used_bits = opc->mask;
7925 if ((used_bits & opc->match) != opc->match)
7927 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7928 opc->name, opc->args);
7931 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7941 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7942 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
7943 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
7944 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
7945 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
7946 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7947 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
7948 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
7949 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
7952 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
7953 c, opc->name, opc->args);
7957 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7958 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7960 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
7961 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
7962 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
7963 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7965 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7966 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
7968 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
7969 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7971 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
7972 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
7973 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
7974 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
7975 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7976 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
7977 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7978 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7979 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7980 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7981 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
7982 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7983 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7984 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
7985 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7986 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
7987 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7989 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
7990 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
7991 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7992 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
7994 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7995 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7996 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
7997 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7998 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7999 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8000 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8001 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8002 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8005 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
8006 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
8007 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8008 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
8009 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
8013 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8014 c, opc->name, opc->args);
8018 if (used_bits != 0xffffffff)
8020 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8021 ~used_bits & 0xffffffff, opc->name, opc->args);
8027 /* This routine assembles an instruction into its binary format. As a
8028 side effect, it sets one of the global variables imm_reloc or
8029 offset_reloc to the type of relocation to do if one of the operands
8030 is an address expression. */
8033 mips_ip (char *str, struct mips_cl_insn *ip)
8038 struct mips_opcode *insn;
8041 unsigned int lastregno = 0;
8042 unsigned int lastpos = 0;
8043 unsigned int limlo, limhi;
8049 /* If the instruction contains a '.', we first try to match an instruction
8050 including the '.'. Then we try again without the '.'. */
8052 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
8055 /* If we stopped on whitespace, then replace the whitespace with null for
8056 the call to hash_find. Save the character we replaced just in case we
8057 have to re-parse the instruction. */
8064 insn = (struct mips_opcode *) hash_find (op_hash, str);
8066 /* If we didn't find the instruction in the opcode table, try again, but
8067 this time with just the instruction up to, but not including the
8071 /* Restore the character we overwrite above (if any). */
8075 /* Scan up to the first '.' or whitespace. */
8077 *s != '\0' && *s != '.' && !ISSPACE (*s);
8081 /* If we did not find a '.', then we can quit now. */
8084 insn_error = "unrecognized opcode";
8088 /* Lookup the instruction in the hash table. */
8090 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
8092 insn_error = "unrecognized opcode";
8102 assert (strcmp (insn->name, str) == 0);
8104 if (OPCODE_IS_MEMBER (insn,
8106 | (file_ase_mips16 ? INSN_MIPS16 : 0)
8107 | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
8108 | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
8114 if (insn->pinfo != INSN_MACRO)
8116 if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)
8122 if (insn + 1 < &mips_opcodes[NUMOPCODES]
8123 && strcmp (insn->name, insn[1].name) == 0)
8132 static char buf[100];
8134 _("opcode not supported on this processor: %s (%s)"),
8135 mips_cpu_info_from_arch (mips_opts.arch)->name,
8136 mips_cpu_info_from_isa (mips_opts.isa)->name);
8146 ip->insn_opcode = insn->match;
8148 for (args = insn->args;; ++args)
8152 s += strspn (s, " \t");
8156 case '\0': /* end of args */
8169 ip->insn_opcode |= lastregno << OP_SH_RS;
8173 ip->insn_opcode |= lastregno << OP_SH_RT;
8177 ip->insn_opcode |= lastregno << OP_SH_FT;
8181 ip->insn_opcode |= lastregno << OP_SH_FS;
8187 /* Handle optional base register.
8188 Either the base register is omitted or
8189 we must have a left paren. */
8190 /* This is dependent on the next operand specifier
8191 is a base register specification. */
8192 assert (args[1] == 'b' || args[1] == '5'
8193 || args[1] == '-' || args[1] == '4');
8197 case ')': /* these must match exactly */
8204 case '+': /* Opcode extension character. */
8207 case 'A': /* ins/ext position, becomes LSB. */
8216 my_getExpression (&imm_expr, s);
8217 check_absolute_expr (ip, &imm_expr);
8218 if ((unsigned long) imm_expr.X_add_number < limlo
8219 || (unsigned long) imm_expr.X_add_number > limhi)
8221 as_bad (_("Improper position (%lu)"),
8222 (unsigned long) imm_expr.X_add_number);
8223 imm_expr.X_add_number = limlo;
8225 lastpos = imm_expr.X_add_number;
8226 ip->insn_opcode |= (imm_expr.X_add_number
8227 & OP_MASK_SHAMT) << OP_SH_SHAMT;
8228 imm_expr.X_op = O_absent;
8232 case 'B': /* ins size, becomes MSB. */
8241 my_getExpression (&imm_expr, s);
8242 check_absolute_expr (ip, &imm_expr);
8243 /* Check for negative input so that small negative numbers
8244 will not succeed incorrectly. The checks against
8245 (pos+size) transitively check "size" itself,
8246 assuming that "pos" is reasonable. */
8247 if ((long) imm_expr.X_add_number < 0
8248 || ((unsigned long) imm_expr.X_add_number
8250 || ((unsigned long) imm_expr.X_add_number
8253 as_bad (_("Improper insert size (%lu, position %lu)"),
8254 (unsigned long) imm_expr.X_add_number,
8255 (unsigned long) lastpos);
8256 imm_expr.X_add_number = limlo - lastpos;
8258 ip->insn_opcode |= ((lastpos + imm_expr.X_add_number - 1)
8259 & OP_MASK_INSMSB) << OP_SH_INSMSB;
8260 imm_expr.X_op = O_absent;
8264 case 'C': /* ext size, becomes MSBD. */
8277 my_getExpression (&imm_expr, s);
8278 check_absolute_expr (ip, &imm_expr);
8279 /* Check for negative input so that small negative numbers
8280 will not succeed incorrectly. The checks against
8281 (pos+size) transitively check "size" itself,
8282 assuming that "pos" is reasonable. */
8283 if ((long) imm_expr.X_add_number < 0
8284 || ((unsigned long) imm_expr.X_add_number
8286 || ((unsigned long) imm_expr.X_add_number
8289 as_bad (_("Improper extract size (%lu, position %lu)"),
8290 (unsigned long) imm_expr.X_add_number,
8291 (unsigned long) lastpos);
8292 imm_expr.X_add_number = limlo - lastpos;
8294 ip->insn_opcode |= ((imm_expr.X_add_number - 1)
8295 & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD;
8296 imm_expr.X_op = O_absent;
8301 /* +D is for disassembly only; never match. */
8305 /* "+I" is like "I", except that imm2_expr is used. */
8306 my_getExpression (&imm2_expr, s);
8307 if (imm2_expr.X_op != O_big
8308 && imm2_expr.X_op != O_constant)
8309 insn_error = _("absolute expression required");
8310 normalize_constant_expr (&imm2_expr);
8315 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8316 *args, insn->name, insn->args);
8317 /* Further processing is fruitless. */
8322 case '<': /* must be at least one digit */
8324 * According to the manual, if the shift amount is greater
8325 * than 31 or less than 0, then the shift amount should be
8326 * mod 32. In reality the mips assembler issues an error.
8327 * We issue a warning and mask out all but the low 5 bits.
8329 my_getExpression (&imm_expr, s);
8330 check_absolute_expr (ip, &imm_expr);
8331 if ((unsigned long) imm_expr.X_add_number > 31)
8333 as_warn (_("Improper shift amount (%lu)"),
8334 (unsigned long) imm_expr.X_add_number);
8335 imm_expr.X_add_number &= OP_MASK_SHAMT;
8337 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT;
8338 imm_expr.X_op = O_absent;
8342 case '>': /* shift amount minus 32 */
8343 my_getExpression (&imm_expr, s);
8344 check_absolute_expr (ip, &imm_expr);
8345 if ((unsigned long) imm_expr.X_add_number < 32
8346 || (unsigned long) imm_expr.X_add_number > 63)
8348 ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT;
8349 imm_expr.X_op = O_absent;
8353 case 'k': /* cache code */
8354 case 'h': /* prefx code */
8355 my_getExpression (&imm_expr, s);
8356 check_absolute_expr (ip, &imm_expr);
8357 if ((unsigned long) imm_expr.X_add_number > 31)
8359 as_warn (_("Invalid value for `%s' (%lu)"),
8361 (unsigned long) imm_expr.X_add_number);
8362 imm_expr.X_add_number &= 0x1f;
8365 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE;
8367 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX;
8368 imm_expr.X_op = O_absent;
8372 case 'c': /* break code */
8373 my_getExpression (&imm_expr, s);
8374 check_absolute_expr (ip, &imm_expr);
8375 if ((unsigned long) imm_expr.X_add_number > 1023)
8377 as_warn (_("Illegal break code (%lu)"),
8378 (unsigned long) imm_expr.X_add_number);
8379 imm_expr.X_add_number &= OP_MASK_CODE;
8381 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE;
8382 imm_expr.X_op = O_absent;
8386 case 'q': /* lower break code */
8387 my_getExpression (&imm_expr, s);
8388 check_absolute_expr (ip, &imm_expr);
8389 if ((unsigned long) imm_expr.X_add_number > 1023)
8391 as_warn (_("Illegal lower break code (%lu)"),
8392 (unsigned long) imm_expr.X_add_number);
8393 imm_expr.X_add_number &= OP_MASK_CODE2;
8395 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2;
8396 imm_expr.X_op = O_absent;
8400 case 'B': /* 20-bit syscall/break code. */
8401 my_getExpression (&imm_expr, s);
8402 check_absolute_expr (ip, &imm_expr);
8403 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
8404 as_warn (_("Illegal 20-bit code (%lu)"),
8405 (unsigned long) imm_expr.X_add_number);
8406 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20;
8407 imm_expr.X_op = O_absent;
8411 case 'C': /* Coprocessor code */
8412 my_getExpression (&imm_expr, s);
8413 check_absolute_expr (ip, &imm_expr);
8414 if ((unsigned long) imm_expr.X_add_number >= (1 << 25))
8416 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8417 (unsigned long) imm_expr.X_add_number);
8418 imm_expr.X_add_number &= ((1 << 25) - 1);
8420 ip->insn_opcode |= imm_expr.X_add_number;
8421 imm_expr.X_op = O_absent;
8425 case 'J': /* 19-bit wait code. */
8426 my_getExpression (&imm_expr, s);
8427 check_absolute_expr (ip, &imm_expr);
8428 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
8429 as_warn (_("Illegal 19-bit code (%lu)"),
8430 (unsigned long) imm_expr.X_add_number);
8431 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19;
8432 imm_expr.X_op = O_absent;
8436 case 'P': /* Performance register */
8437 my_getExpression (&imm_expr, s);
8438 check_absolute_expr (ip, &imm_expr);
8439 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
8441 as_warn (_("Invalid performance register (%lu)"),
8442 (unsigned long) imm_expr.X_add_number);
8443 imm_expr.X_add_number &= OP_MASK_PERFREG;
8445 ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG);
8446 imm_expr.X_op = O_absent;
8450 case 'b': /* base register */
8451 case 'd': /* destination register */
8452 case 's': /* source register */
8453 case 't': /* target register */
8454 case 'r': /* both target and source */
8455 case 'v': /* both dest and source */
8456 case 'w': /* both dest and target */
8457 case 'E': /* coprocessor target register */
8458 case 'G': /* coprocessor destination register */
8459 case 'K': /* 'rdhwr' destination register */
8460 case 'x': /* ignore register name */
8461 case 'z': /* must be zero register */
8462 case 'U': /* destination register (clo/clz). */
8477 while (ISDIGIT (*s));
8479 as_bad (_("Invalid register number (%d)"), regno);
8481 else if (*args == 'E' || *args == 'G' || *args == 'K')
8485 if (s[1] == 'r' && s[2] == 'a')
8490 else if (s[1] == 'f' && s[2] == 'p')
8495 else if (s[1] == 's' && s[2] == 'p')
8500 else if (s[1] == 'g' && s[2] == 'p')
8505 else if (s[1] == 'a' && s[2] == 't')
8510 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
8515 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
8520 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
8525 else if (itbl_have_entries)
8530 p = s + 1; /* advance past '$' */
8531 n = itbl_get_field (&p); /* n is name */
8533 /* See if this is a register defined in an
8535 if (itbl_get_reg_val (n, &r))
8537 /* Get_field advances to the start of
8538 the next field, so we need to back
8539 rack to the end of the last field. */
8543 s = strchr (s, '\0');
8557 as_warn (_("Used $at without \".set noat\""));
8563 if (c == 'r' || c == 'v' || c == 'w')
8570 /* 'z' only matches $0. */
8571 if (c == 'z' && regno != 0)
8574 /* Now that we have assembled one operand, we use the args string
8575 * to figure out where it goes in the instruction. */
8582 ip->insn_opcode |= regno << OP_SH_RS;
8587 ip->insn_opcode |= regno << OP_SH_RD;
8590 ip->insn_opcode |= regno << OP_SH_RD;
8591 ip->insn_opcode |= regno << OP_SH_RT;
8596 ip->insn_opcode |= regno << OP_SH_RT;
8599 /* This case exists because on the r3000 trunc
8600 expands into a macro which requires a gp
8601 register. On the r6000 or r4000 it is
8602 assembled into a single instruction which
8603 ignores the register. Thus the insn version
8604 is MIPS_ISA2 and uses 'x', and the macro
8605 version is MIPS_ISA1 and uses 't'. */
8608 /* This case is for the div instruction, which
8609 acts differently if the destination argument
8610 is $0. This only matches $0, and is checked
8611 outside the switch. */
8614 /* Itbl operand; not yet implemented. FIXME ?? */
8616 /* What about all other operands like 'i', which
8617 can be specified in the opcode table? */
8627 ip->insn_opcode |= lastregno << OP_SH_RS;
8630 ip->insn_opcode |= lastregno << OP_SH_RT;
8635 case 'O': /* MDMX alignment immediate constant. */
8636 my_getExpression (&imm_expr, s);
8637 check_absolute_expr (ip, &imm_expr);
8638 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
8640 as_warn ("Improper align amount (%ld), using low bits",
8641 (long) imm_expr.X_add_number);
8642 imm_expr.X_add_number &= OP_MASK_ALN;
8644 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN;
8645 imm_expr.X_op = O_absent;
8649 case 'Q': /* MDMX vector, element sel, or const. */
8652 /* MDMX Immediate. */
8653 my_getExpression (&imm_expr, s);
8654 check_absolute_expr (ip, &imm_expr);
8655 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
8657 as_warn (_("Invalid MDMX Immediate (%ld)"),
8658 (long) imm_expr.X_add_number);
8659 imm_expr.X_add_number &= OP_MASK_FT;
8661 imm_expr.X_add_number &= OP_MASK_FT;
8662 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8663 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
8665 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
8666 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT;
8667 imm_expr.X_op = O_absent;
8671 /* Not MDMX Immediate. Fall through. */
8672 case 'X': /* MDMX destination register. */
8673 case 'Y': /* MDMX source register. */
8674 case 'Z': /* MDMX target register. */
8676 case 'D': /* floating point destination register */
8677 case 'S': /* floating point source register */
8678 case 'T': /* floating point target register */
8679 case 'R': /* floating point source register */
8683 /* Accept $fN for FP and MDMX register numbers, and in
8684 addition accept $vN for MDMX register numbers. */
8685 if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2]))
8686 || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v'
8697 while (ISDIGIT (*s));
8700 as_bad (_("Invalid float register number (%d)"), regno);
8702 if ((regno & 1) != 0
8704 && ! (strcmp (str, "mtc1") == 0
8705 || strcmp (str, "mfc1") == 0
8706 || strcmp (str, "lwc1") == 0
8707 || strcmp (str, "swc1") == 0
8708 || strcmp (str, "l.s") == 0
8709 || strcmp (str, "s.s") == 0))
8710 as_warn (_("Float register should be even, was %d"),
8718 if (c == 'V' || c == 'W')
8729 ip->insn_opcode |= regno << OP_SH_FD;
8734 ip->insn_opcode |= regno << OP_SH_FS;
8737 /* This is like 'Z', but also needs to fix the MDMX
8738 vector/scalar select bits. Note that the
8739 scalar immediate case is handled above. */
8742 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
8743 int max_el = (is_qh ? 3 : 7);
8745 my_getExpression(&imm_expr, s);
8746 check_absolute_expr (ip, &imm_expr);
8748 if (imm_expr.X_add_number > max_el)
8749 as_bad(_("Bad element selector %ld"),
8750 (long) imm_expr.X_add_number);
8751 imm_expr.X_add_number &= max_el;
8752 ip->insn_opcode |= (imm_expr.X_add_number
8756 as_warn(_("Expecting ']' found '%s'"), s);
8762 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8763 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
8766 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
8773 ip->insn_opcode |= regno << OP_SH_FT;
8776 ip->insn_opcode |= regno << OP_SH_FR;
8786 ip->insn_opcode |= lastregno << OP_SH_FS;
8789 ip->insn_opcode |= lastregno << OP_SH_FT;
8795 my_getExpression (&imm_expr, s);
8796 if (imm_expr.X_op != O_big
8797 && imm_expr.X_op != O_constant)
8798 insn_error = _("absolute expression required");
8799 normalize_constant_expr (&imm_expr);
8804 my_getExpression (&offset_expr, s);
8805 *imm_reloc = BFD_RELOC_32;
8818 unsigned char temp[8];
8820 unsigned int length;
8825 /* These only appear as the last operand in an
8826 instruction, and every instruction that accepts
8827 them in any variant accepts them in all variants.
8828 This means we don't have to worry about backing out
8829 any changes if the instruction does not match.
8831 The difference between them is the size of the
8832 floating point constant and where it goes. For 'F'
8833 and 'L' the constant is 64 bits; for 'f' and 'l' it
8834 is 32 bits. Where the constant is placed is based
8835 on how the MIPS assembler does things:
8838 f -- immediate value
8841 The .lit4 and .lit8 sections are only used if
8842 permitted by the -G argument.
8844 When generating embedded PIC code, we use the
8845 .lit8 section but not the .lit4 section (we can do
8846 .lit4 inline easily; we need to put .lit8
8847 somewhere in the data segment, and using .lit8
8848 permits the linker to eventually combine identical
8851 The code below needs to know whether the target register
8852 is 32 or 64 bits wide. It relies on the fact 'f' and
8853 'F' are used with GPR-based instructions and 'l' and
8854 'L' are used with FPR-based instructions. */
8856 f64 = *args == 'F' || *args == 'L';
8857 using_gprs = *args == 'F' || *args == 'f';
8859 save_in = input_line_pointer;
8860 input_line_pointer = s;
8861 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
8863 s = input_line_pointer;
8864 input_line_pointer = save_in;
8865 if (err != NULL && *err != '\0')
8867 as_bad (_("Bad floating point constant: %s"), err);
8868 memset (temp, '\0', sizeof temp);
8869 length = f64 ? 8 : 4;
8872 assert (length == (unsigned) (f64 ? 8 : 4));
8876 && (! USE_GLOBAL_POINTER_OPT
8877 || mips_pic == EMBEDDED_PIC
8878 || g_switch_value < 4
8879 || (temp[0] == 0 && temp[1] == 0)
8880 || (temp[2] == 0 && temp[3] == 0))))
8882 imm_expr.X_op = O_constant;
8883 if (! target_big_endian)
8884 imm_expr.X_add_number = bfd_getl32 (temp);
8886 imm_expr.X_add_number = bfd_getb32 (temp);
8889 && ! mips_disable_float_construction
8890 /* Constants can only be constructed in GPRs and
8891 copied to FPRs if the GPRs are at least as wide
8892 as the FPRs. Force the constant into memory if
8893 we are using 64-bit FPRs but the GPRs are only
8896 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
8897 && ((temp[0] == 0 && temp[1] == 0)
8898 || (temp[2] == 0 && temp[3] == 0))
8899 && ((temp[4] == 0 && temp[5] == 0)
8900 || (temp[6] == 0 && temp[7] == 0)))
8902 /* The value is simple enough to load with a couple of
8903 instructions. If using 32-bit registers, set
8904 imm_expr to the high order 32 bits and offset_expr to
8905 the low order 32 bits. Otherwise, set imm_expr to
8906 the entire 64 bit constant. */
8907 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
8909 imm_expr.X_op = O_constant;
8910 offset_expr.X_op = O_constant;
8911 if (! target_big_endian)
8913 imm_expr.X_add_number = bfd_getl32 (temp + 4);
8914 offset_expr.X_add_number = bfd_getl32 (temp);
8918 imm_expr.X_add_number = bfd_getb32 (temp);
8919 offset_expr.X_add_number = bfd_getb32 (temp + 4);
8921 if (offset_expr.X_add_number == 0)
8922 offset_expr.X_op = O_absent;
8924 else if (sizeof (imm_expr.X_add_number) > 4)
8926 imm_expr.X_op = O_constant;
8927 if (! target_big_endian)
8928 imm_expr.X_add_number = bfd_getl64 (temp);
8930 imm_expr.X_add_number = bfd_getb64 (temp);
8934 imm_expr.X_op = O_big;
8935 imm_expr.X_add_number = 4;
8936 if (! target_big_endian)
8938 generic_bignum[0] = bfd_getl16 (temp);
8939 generic_bignum[1] = bfd_getl16 (temp + 2);
8940 generic_bignum[2] = bfd_getl16 (temp + 4);
8941 generic_bignum[3] = bfd_getl16 (temp + 6);
8945 generic_bignum[0] = bfd_getb16 (temp + 6);
8946 generic_bignum[1] = bfd_getb16 (temp + 4);
8947 generic_bignum[2] = bfd_getb16 (temp + 2);
8948 generic_bignum[3] = bfd_getb16 (temp);
8954 const char *newname;
8957 /* Switch to the right section. */
8959 subseg = now_subseg;
8962 default: /* unused default case avoids warnings. */
8964 newname = RDATA_SECTION_NAME;
8965 if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8)
8966 || mips_pic == EMBEDDED_PIC)
8970 if (mips_pic == EMBEDDED_PIC)
8973 newname = RDATA_SECTION_NAME;
8976 assert (!USE_GLOBAL_POINTER_OPT
8977 || g_switch_value >= 4);
8981 new_seg = subseg_new (newname, (subsegT) 0);
8982 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
8983 bfd_set_section_flags (stdoutput, new_seg,
8988 frag_align (*args == 'l' ? 2 : 3, 0, 0);
8989 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
8990 && strcmp (TARGET_OS, "elf") != 0)
8991 record_alignment (new_seg, 4);
8993 record_alignment (new_seg, *args == 'l' ? 2 : 3);
8995 as_bad (_("Can't use floating point insn in this section"));
8997 /* Set the argument to the current address in the
8999 offset_expr.X_op = O_symbol;
9000 offset_expr.X_add_symbol =
9001 symbol_new ("L0\001", now_seg,
9002 (valueT) frag_now_fix (), frag_now);
9003 offset_expr.X_add_number = 0;
9005 /* Put the floating point number into the section. */
9006 p = frag_more ((int) length);
9007 memcpy (p, temp, length);
9009 /* Switch back to the original section. */
9010 subseg_set (seg, subseg);
9015 case 'i': /* 16 bit unsigned immediate */
9016 case 'j': /* 16 bit signed immediate */
9017 *imm_reloc = BFD_RELOC_LO16;
9018 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
9021 offsetT minval, maxval;
9023 more = (insn + 1 < &mips_opcodes[NUMOPCODES]
9024 && strcmp (insn->name, insn[1].name) == 0);
9026 /* If the expression was written as an unsigned number,
9027 only treat it as signed if there are no more
9031 && sizeof (imm_expr.X_add_number) <= 4
9032 && imm_expr.X_op == O_constant
9033 && imm_expr.X_add_number < 0
9034 && imm_expr.X_unsigned
9038 /* For compatibility with older assemblers, we accept
9039 0x8000-0xffff as signed 16-bit numbers when only
9040 signed numbers are allowed. */
9042 minval = 0, maxval = 0xffff;
9044 minval = -0x8000, maxval = 0x7fff;
9046 minval = -0x8000, maxval = 0xffff;
9048 if (imm_expr.X_op != O_constant
9049 || imm_expr.X_add_number < minval
9050 || imm_expr.X_add_number > maxval)
9054 if (imm_expr.X_op == O_constant
9055 || imm_expr.X_op == O_big)
9056 as_bad (_("expression out of range"));
9062 case 'o': /* 16 bit offset */
9063 /* Check whether there is only a single bracketed expression
9064 left. If so, it must be the base register and the
9065 constant must be zero. */
9066 if (*s == '(' && strchr (s + 1, '(') == 0)
9068 offset_expr.X_op = O_constant;
9069 offset_expr.X_add_number = 0;
9073 /* If this value won't fit into a 16 bit offset, then go
9074 find a macro that will generate the 32 bit offset
9076 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
9077 && (offset_expr.X_op != O_constant
9078 || offset_expr.X_add_number >= 0x8000
9079 || offset_expr.X_add_number < -0x8000))
9085 case 'p': /* pc relative offset */
9086 *offset_reloc = BFD_RELOC_16_PCREL_S2;
9087 my_getExpression (&offset_expr, s);
9091 case 'u': /* upper 16 bits */
9092 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
9093 && imm_expr.X_op == O_constant
9094 && (imm_expr.X_add_number < 0
9095 || imm_expr.X_add_number >= 0x10000))
9096 as_bad (_("lui expression not in range 0..65535"));
9100 case 'a': /* 26 bit address */
9101 my_getExpression (&offset_expr, s);
9103 *offset_reloc = BFD_RELOC_MIPS_JMP;
9106 case 'N': /* 3 bit branch condition code */
9107 case 'M': /* 3 bit compare condition code */
9108 if (strncmp (s, "$fcc", 4) != 0)
9118 while (ISDIGIT (*s));
9120 as_bad (_("Invalid condition code register $fcc%d"), regno);
9121 if ((strcmp(str + strlen(str) - 3, ".ps") == 0
9122 || strcmp(str + strlen(str) - 5, "any2f") == 0
9123 || strcmp(str + strlen(str) - 5, "any2t") == 0)
9124 && (regno & 1) != 0)
9125 as_warn(_("Condition code register should be even for %s, was %d"),
9127 if ((strcmp(str + strlen(str) - 5, "any4f") == 0
9128 || strcmp(str + strlen(str) - 5, "any4t") == 0)
9129 && (regno & 3) != 0)
9130 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
9133 ip->insn_opcode |= regno << OP_SH_BCC;
9135 ip->insn_opcode |= regno << OP_SH_CCC;
9139 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
9150 while (ISDIGIT (*s));
9153 c = 8; /* Invalid sel value. */
9156 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9157 ip->insn_opcode |= c;
9161 /* Must be at least one digit. */
9162 my_getExpression (&imm_expr, s);
9163 check_absolute_expr (ip, &imm_expr);
9165 if ((unsigned long) imm_expr.X_add_number
9166 > (unsigned long) OP_MASK_VECBYTE)
9168 as_bad (_("bad byte vector index (%ld)"),
9169 (long) imm_expr.X_add_number);
9170 imm_expr.X_add_number = 0;
9173 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE;
9174 imm_expr.X_op = O_absent;
9179 my_getExpression (&imm_expr, s);
9180 check_absolute_expr (ip, &imm_expr);
9182 if ((unsigned long) imm_expr.X_add_number
9183 > (unsigned long) OP_MASK_VECALIGN)
9185 as_bad (_("bad byte vector index (%ld)"),
9186 (long) imm_expr.X_add_number);
9187 imm_expr.X_add_number = 0;
9190 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN;
9191 imm_expr.X_op = O_absent;
9196 as_bad (_("bad char = '%c'\n"), *args);
9201 /* Args don't match. */
9202 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
9203 !strcmp (insn->name, insn[1].name))
9207 insn_error = _("illegal operands");
9212 insn_error = _("illegal operands");
9217 /* This routine assembles an instruction into its binary format when
9218 assembling for the mips16. As a side effect, it sets one of the
9219 global variables imm_reloc or offset_reloc to the type of
9220 relocation to do if one of the operands is an address expression.
9221 It also sets mips16_small and mips16_ext if the user explicitly
9222 requested a small or extended instruction. */
9225 mips16_ip (char *str, struct mips_cl_insn *ip)
9229 struct mips_opcode *insn;
9232 unsigned int lastregno = 0;
9237 mips16_small = FALSE;
9240 for (s = str; ISLOWER (*s); ++s)
9252 if (s[1] == 't' && s[2] == ' ')
9255 mips16_small = TRUE;
9259 else if (s[1] == 'e' && s[2] == ' ')
9268 insn_error = _("unknown opcode");
9272 if (mips_opts.noautoextend && ! mips16_ext)
9273 mips16_small = TRUE;
9275 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
9277 insn_error = _("unrecognized opcode");
9284 assert (strcmp (insn->name, str) == 0);
9287 ip->insn_opcode = insn->match;
9288 ip->use_extend = FALSE;
9289 imm_expr.X_op = O_absent;
9290 imm_reloc[0] = BFD_RELOC_UNUSED;
9291 imm_reloc[1] = BFD_RELOC_UNUSED;
9292 imm_reloc[2] = BFD_RELOC_UNUSED;
9293 imm2_expr.X_op = O_absent;
9294 offset_expr.X_op = O_absent;
9295 offset_reloc[0] = BFD_RELOC_UNUSED;
9296 offset_reloc[1] = BFD_RELOC_UNUSED;
9297 offset_reloc[2] = BFD_RELOC_UNUSED;
9298 for (args = insn->args; 1; ++args)
9305 /* In this switch statement we call break if we did not find
9306 a match, continue if we did find a match, or return if we
9315 /* Stuff the immediate value in now, if we can. */
9316 if (imm_expr.X_op == O_constant
9317 && *imm_reloc > BFD_RELOC_UNUSED
9318 && insn->pinfo != INSN_MACRO)
9320 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
9321 imm_expr.X_add_number, TRUE, mips16_small,
9322 mips16_ext, &ip->insn_opcode,
9323 &ip->use_extend, &ip->extend);
9324 imm_expr.X_op = O_absent;
9325 *imm_reloc = BFD_RELOC_UNUSED;
9339 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9342 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9358 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9360 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9387 while (ISDIGIT (*s));
9390 as_bad (_("invalid register number (%d)"), regno);
9396 if (s[1] == 'r' && s[2] == 'a')
9401 else if (s[1] == 'f' && s[2] == 'p')
9406 else if (s[1] == 's' && s[2] == 'p')
9411 else if (s[1] == 'g' && s[2] == 'p')
9416 else if (s[1] == 'a' && s[2] == 't')
9421 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
9426 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
9431 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
9444 if (c == 'v' || c == 'w')
9446 regno = mips16_to_32_reg_map[lastregno];
9460 regno = mips32_to_16_reg_map[regno];
9465 regno = ILLEGAL_REG;
9470 regno = ILLEGAL_REG;
9475 regno = ILLEGAL_REG;
9480 if (regno == AT && ! mips_opts.noat)
9481 as_warn (_("used $at without \".set noat\""));
9488 if (regno == ILLEGAL_REG)
9495 ip->insn_opcode |= regno << MIPS16OP_SH_RX;
9499 ip->insn_opcode |= regno << MIPS16OP_SH_RY;
9502 ip->insn_opcode |= regno << MIPS16OP_SH_RZ;
9505 ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z;
9511 ip->insn_opcode |= regno << MIPS16OP_SH_REGR32;
9514 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
9515 ip->insn_opcode |= regno << MIPS16OP_SH_REG32R;
9525 if (strncmp (s, "$pc", 3) == 0)
9549 && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0)
9551 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9552 and generate the appropriate reloc. If the text
9553 inside %gprel is not a symbol name with an
9554 optional offset, then we generate a normal reloc
9555 and will probably fail later. */
9556 my_getExpression (&imm_expr, s + sizeof "%gprel" - 1);
9557 if (imm_expr.X_op == O_symbol)
9560 *imm_reloc = BFD_RELOC_MIPS16_GPREL;
9562 ip->use_extend = TRUE;
9569 /* Just pick up a normal expression. */
9570 my_getExpression (&imm_expr, s);
9573 if (imm_expr.X_op == O_register)
9575 /* What we thought was an expression turned out to
9578 if (s[0] == '(' && args[1] == '(')
9580 /* It looks like the expression was omitted
9581 before a register indirection, which means
9582 that the expression is implicitly zero. We
9583 still set up imm_expr, so that we handle
9584 explicit extensions correctly. */
9585 imm_expr.X_op = O_constant;
9586 imm_expr.X_add_number = 0;
9587 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9594 /* We need to relax this instruction. */
9595 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9604 /* We use offset_reloc rather than imm_reloc for the PC
9605 relative operands. This lets macros with both
9606 immediate and address operands work correctly. */
9607 my_getExpression (&offset_expr, s);
9609 if (offset_expr.X_op == O_register)
9612 /* We need to relax this instruction. */
9613 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
9617 case '6': /* break code */
9618 my_getExpression (&imm_expr, s);
9619 check_absolute_expr (ip, &imm_expr);
9620 if ((unsigned long) imm_expr.X_add_number > 63)
9622 as_warn (_("Invalid value for `%s' (%lu)"),
9624 (unsigned long) imm_expr.X_add_number);
9625 imm_expr.X_add_number &= 0x3f;
9627 ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6;
9628 imm_expr.X_op = O_absent;
9632 case 'a': /* 26 bit address */
9633 my_getExpression (&offset_expr, s);
9635 *offset_reloc = BFD_RELOC_MIPS16_JMP;
9636 ip->insn_opcode <<= 16;
9639 case 'l': /* register list for entry macro */
9640 case 'L': /* register list for exit macro */
9650 int freg, reg1, reg2;
9652 while (*s == ' ' || *s == ',')
9656 as_bad (_("can't parse register list"));
9668 while (ISDIGIT (*s))
9690 as_bad (_("invalid register list"));
9695 while (ISDIGIT (*s))
9702 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
9707 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
9712 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
9713 mask |= (reg2 - 3) << 3;
9714 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
9715 mask |= (reg2 - 15) << 1;
9716 else if (reg1 == RA && reg2 == RA)
9720 as_bad (_("invalid register list"));
9724 /* The mask is filled in in the opcode table for the
9725 benefit of the disassembler. We remove it before
9726 applying the actual mask. */
9727 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
9728 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
9732 case 'e': /* extend code */
9733 my_getExpression (&imm_expr, s);
9734 check_absolute_expr (ip, &imm_expr);
9735 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
9737 as_warn (_("Invalid value for `%s' (%lu)"),
9739 (unsigned long) imm_expr.X_add_number);
9740 imm_expr.X_add_number &= 0x7ff;
9742 ip->insn_opcode |= imm_expr.X_add_number;
9743 imm_expr.X_op = O_absent;
9753 /* Args don't match. */
9754 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
9755 strcmp (insn->name, insn[1].name) == 0)
9762 insn_error = _("illegal operands");
9768 /* This structure holds information we know about a mips16 immediate
9771 struct mips16_immed_operand
9773 /* The type code used in the argument string in the opcode table. */
9775 /* The number of bits in the short form of the opcode. */
9777 /* The number of bits in the extended form of the opcode. */
9779 /* The amount by which the short form is shifted when it is used;
9780 for example, the sw instruction has a shift count of 2. */
9782 /* The amount by which the short form is shifted when it is stored
9783 into the instruction code. */
9785 /* Non-zero if the short form is unsigned. */
9787 /* Non-zero if the extended form is unsigned. */
9789 /* Non-zero if the value is PC relative. */
9793 /* The mips16 immediate operand types. */
9795 static const struct mips16_immed_operand mips16_immed_operands[] =
9797 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9798 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9799 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9800 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9801 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
9802 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
9803 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
9804 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
9805 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
9806 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
9807 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
9808 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
9809 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
9810 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
9811 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
9812 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
9813 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9814 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9815 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
9816 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
9817 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
9820 #define MIPS16_NUM_IMMED \
9821 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9823 /* Handle a mips16 instruction with an immediate value. This or's the
9824 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9825 whether an extended value is needed; if one is needed, it sets
9826 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9827 If SMALL is true, an unextended opcode was explicitly requested.
9828 If EXT is true, an extended opcode was explicitly requested. If
9829 WARN is true, warn if EXT does not match reality. */
9832 mips16_immed (char *file, unsigned int line, int type, offsetT val,
9833 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
9834 unsigned long *insn, bfd_boolean *use_extend,
9835 unsigned short *extend)
9837 register const struct mips16_immed_operand *op;
9838 int mintiny, maxtiny;
9839 bfd_boolean needext;
9841 op = mips16_immed_operands;
9842 while (op->type != type)
9845 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
9850 if (type == '<' || type == '>' || type == '[' || type == ']')
9853 maxtiny = 1 << op->nbits;
9858 maxtiny = (1 << op->nbits) - 1;
9863 mintiny = - (1 << (op->nbits - 1));
9864 maxtiny = (1 << (op->nbits - 1)) - 1;
9867 /* Branch offsets have an implicit 0 in the lowest bit. */
9868 if (type == 'p' || type == 'q')
9871 if ((val & ((1 << op->shift) - 1)) != 0
9872 || val < (mintiny << op->shift)
9873 || val > (maxtiny << op->shift))
9878 if (warn && ext && ! needext)
9879 as_warn_where (file, line,
9880 _("extended operand requested but not required"));
9881 if (small && needext)
9882 as_bad_where (file, line, _("invalid unextended operand value"));
9884 if (small || (! ext && ! needext))
9888 *use_extend = FALSE;
9889 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
9890 insnval <<= op->op_shift;
9895 long minext, maxext;
9901 maxext = (1 << op->extbits) - 1;
9905 minext = - (1 << (op->extbits - 1));
9906 maxext = (1 << (op->extbits - 1)) - 1;
9908 if (val < minext || val > maxext)
9909 as_bad_where (file, line,
9910 _("operand value out of range for instruction"));
9913 if (op->extbits == 16)
9915 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
9918 else if (op->extbits == 15)
9920 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
9925 extval = ((val & 0x1f) << 6) | (val & 0x20);
9929 *extend = (unsigned short) extval;
9934 static const struct percent_op_match
9937 bfd_reloc_code_real_type reloc;
9940 {"%lo", BFD_RELOC_LO16},
9942 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
9943 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
9944 {"%call16", BFD_RELOC_MIPS_CALL16},
9945 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
9946 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
9947 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
9948 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
9949 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
9950 {"%got", BFD_RELOC_MIPS_GOT16},
9951 {"%gp_rel", BFD_RELOC_GPREL16},
9952 {"%half", BFD_RELOC_16},
9953 {"%highest", BFD_RELOC_MIPS_HIGHEST},
9954 {"%higher", BFD_RELOC_MIPS_HIGHER},
9955 {"%neg", BFD_RELOC_MIPS_SUB},
9957 {"%hi", BFD_RELOC_HI16_S}
9961 /* Return true if *STR points to a relocation operator. When returning true,
9962 move *STR over the operator and store its relocation code in *RELOC.
9963 Leave both *STR and *RELOC alone when returning false. */
9966 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
9970 for (i = 0; i < ARRAY_SIZE (percent_op); i++)
9971 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
9973 *str += strlen (percent_op[i].str);
9974 *reloc = percent_op[i].reloc;
9976 /* Check whether the output BFD supports this relocation.
9977 If not, issue an error and fall back on something safe. */
9978 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
9980 as_bad ("relocation %s isn't supported by the current ABI",
9982 *reloc = BFD_RELOC_LO16;
9990 /* Parse string STR as a 16-bit relocatable operand. Store the
9991 expression in *EP and the relocations in the array starting
9992 at RELOC. Return the number of relocation operators used.
9994 On exit, EXPR_END points to the first character after the expression.
9995 If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16. */
9998 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
10001 bfd_reloc_code_real_type reversed_reloc[3];
10002 size_t reloc_index, i;
10003 int crux_depth, str_depth;
10006 /* Search for the start of the main expression, recoding relocations
10007 in REVERSED_RELOC. End the loop with CRUX pointing to the start
10008 of the main expression and with CRUX_DEPTH containing the number
10009 of open brackets at that point. */
10016 crux_depth = str_depth;
10018 /* Skip over whitespace and brackets, keeping count of the number
10020 while (*str == ' ' || *str == '\t' || *str == '(')
10025 && reloc_index < (HAVE_NEWABI ? 3 : 1)
10026 && parse_relocation (&str, &reversed_reloc[reloc_index]));
10028 my_getExpression (ep, crux);
10031 /* Match every open bracket. */
10032 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
10036 if (crux_depth > 0)
10037 as_bad ("unclosed '('");
10041 if (reloc_index == 0)
10042 reloc[0] = BFD_RELOC_LO16;
10045 prev_reloc_op_frag = frag_now;
10046 for (i = 0; i < reloc_index; i++)
10047 reloc[i] = reversed_reloc[reloc_index - 1 - i];
10050 return reloc_index;
10054 my_getExpression (expressionS *ep, char *str)
10059 save_in = input_line_pointer;
10060 input_line_pointer = str;
10062 expr_end = input_line_pointer;
10063 input_line_pointer = save_in;
10065 /* If we are in mips16 mode, and this is an expression based on `.',
10066 then we bump the value of the symbol by 1 since that is how other
10067 text symbols are handled. We don't bother to handle complex
10068 expressions, just `.' plus or minus a constant. */
10069 if (mips_opts.mips16
10070 && ep->X_op == O_symbol
10071 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
10072 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg
10073 && symbol_get_frag (ep->X_add_symbol) == frag_now
10074 && symbol_constant_p (ep->X_add_symbol)
10075 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
10076 S_SET_VALUE (ep->X_add_symbol, val + 1);
10079 /* Turn a string in input_line_pointer into a floating point constant
10080 of type TYPE, and store the appropriate bytes in *LITP. The number
10081 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10082 returned, or NULL on OK. */
10085 md_atof (int type, char *litP, int *sizeP)
10088 LITTLENUM_TYPE words[4];
10104 return _("bad call to md_atof");
10107 t = atof_ieee (input_line_pointer, type, words);
10109 input_line_pointer = t;
10113 if (! target_big_endian)
10115 for (i = prec - 1; i >= 0; i--)
10117 md_number_to_chars (litP, words[i], 2);
10123 for (i = 0; i < prec; i++)
10125 md_number_to_chars (litP, words[i], 2);
10134 md_number_to_chars (char *buf, valueT val, int n)
10136 if (target_big_endian)
10137 number_to_chars_bigendian (buf, val, n);
10139 number_to_chars_littleendian (buf, val, n);
10143 static int support_64bit_objects(void)
10145 const char **list, **l;
10148 list = bfd_target_list ();
10149 for (l = list; *l != NULL; l++)
10151 /* This is traditional mips */
10152 if (strcmp (*l, "elf64-tradbigmips") == 0
10153 || strcmp (*l, "elf64-tradlittlemips") == 0)
10155 if (strcmp (*l, "elf64-bigmips") == 0
10156 || strcmp (*l, "elf64-littlemips") == 0)
10159 yes = (*l != NULL);
10163 #endif /* OBJ_ELF */
10165 const char *md_shortopts = "O::g::G:";
10167 struct option md_longopts[] =
10169 /* Options which specify architecture. */
10170 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10171 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10172 {"march", required_argument, NULL, OPTION_MARCH},
10173 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10174 {"mtune", required_argument, NULL, OPTION_MTUNE},
10175 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10176 {"mips0", no_argument, NULL, OPTION_MIPS1},
10177 {"mips1", no_argument, NULL, OPTION_MIPS1},
10178 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10179 {"mips2", no_argument, NULL, OPTION_MIPS2},
10180 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10181 {"mips3", no_argument, NULL, OPTION_MIPS3},
10182 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10183 {"mips4", no_argument, NULL, OPTION_MIPS4},
10184 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10185 {"mips5", no_argument, NULL, OPTION_MIPS5},
10186 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10187 {"mips32", no_argument, NULL, OPTION_MIPS32},
10188 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10189 {"mips64", no_argument, NULL, OPTION_MIPS64},
10190 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10191 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
10192 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10193 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
10195 /* Options which specify Application Specific Extensions (ASEs). */
10196 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10197 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10198 {"mips16", no_argument, NULL, OPTION_MIPS16},
10199 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10200 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
10201 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10202 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
10203 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10204 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
10205 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10206 {"mdmx", no_argument, NULL, OPTION_MDMX},
10207 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10208 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
10210 /* Old-style architecture options. Don't add more of these. */
10211 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
10212 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10213 {"m4650", no_argument, NULL, OPTION_M4650},
10214 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10215 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
10216 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10217 {"m4010", no_argument, NULL, OPTION_M4010},
10218 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10219 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
10220 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10221 {"m4100", no_argument, NULL, OPTION_M4100},
10222 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10223 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
10224 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10225 {"m3900", no_argument, NULL, OPTION_M3900},
10226 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10227 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
10229 /* Options which enable bug fixes. */
10230 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10231 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10232 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
10233 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10234 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10235 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10236 #define OPTION_FIX_VR4122 (OPTION_FIX_BASE + 2)
10237 #define OPTION_NO_FIX_VR4122 (OPTION_FIX_BASE + 3)
10238 {"mfix-vr4122-bugs", no_argument, NULL, OPTION_FIX_VR4122},
10239 {"no-mfix-vr4122-bugs", no_argument, NULL, OPTION_NO_FIX_VR4122},
10241 /* Miscellaneous options. */
10242 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
10243 #define OPTION_MEMBEDDED_PIC (OPTION_MISC_BASE + 0)
10244 {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC},
10245 #define OPTION_TRAP (OPTION_MISC_BASE + 1)
10246 {"trap", no_argument, NULL, OPTION_TRAP},
10247 {"no-break", no_argument, NULL, OPTION_TRAP},
10248 #define OPTION_BREAK (OPTION_MISC_BASE + 2)
10249 {"break", no_argument, NULL, OPTION_BREAK},
10250 {"no-trap", no_argument, NULL, OPTION_BREAK},
10251 #define OPTION_EB (OPTION_MISC_BASE + 3)
10252 {"EB", no_argument, NULL, OPTION_EB},
10253 #define OPTION_EL (OPTION_MISC_BASE + 4)
10254 {"EL", no_argument, NULL, OPTION_EL},
10255 #define OPTION_FP32 (OPTION_MISC_BASE + 5)
10256 {"mfp32", no_argument, NULL, OPTION_FP32},
10257 #define OPTION_GP32 (OPTION_MISC_BASE + 6)
10258 {"mgp32", no_argument, NULL, OPTION_GP32},
10259 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10260 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
10261 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 8)
10262 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
10263 #define OPTION_FP64 (OPTION_MISC_BASE + 9)
10264 {"mfp64", no_argument, NULL, OPTION_FP64},
10265 #define OPTION_GP64 (OPTION_MISC_BASE + 10)
10266 {"mgp64", no_argument, NULL, OPTION_GP64},
10267 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10268 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 12)
10269 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
10270 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
10272 /* ELF-specific options. */
10274 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 13)
10275 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10276 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
10277 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
10278 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10279 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
10280 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10281 {"xgot", no_argument, NULL, OPTION_XGOT},
10282 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10283 {"mabi", required_argument, NULL, OPTION_MABI},
10284 #define OPTION_32 (OPTION_ELF_BASE + 4)
10285 {"32", no_argument, NULL, OPTION_32},
10286 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10287 {"n32", no_argument, NULL, OPTION_N32},
10288 #define OPTION_64 (OPTION_ELF_BASE + 6)
10289 {"64", no_argument, NULL, OPTION_64},
10290 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10291 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
10292 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10293 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
10294 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10295 {"mpdr", no_argument, NULL, OPTION_PDR},
10296 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10297 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
10298 #endif /* OBJ_ELF */
10300 {NULL, no_argument, NULL, 0}
10302 size_t md_longopts_size = sizeof (md_longopts);
10304 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10305 NEW_VALUE. Warn if another value was already specified. Note:
10306 we have to defer parsing the -march and -mtune arguments in order
10307 to handle 'from-abi' correctly, since the ABI might be specified
10308 in a later argument. */
10311 mips_set_option_string (const char **string_ptr, const char *new_value)
10313 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
10314 as_warn (_("A different %s was already specified, is now %s"),
10315 string_ptr == &mips_arch_string ? "-march" : "-mtune",
10318 *string_ptr = new_value;
10322 md_parse_option (int c, char *arg)
10326 case OPTION_CONSTRUCT_FLOATS:
10327 mips_disable_float_construction = 0;
10330 case OPTION_NO_CONSTRUCT_FLOATS:
10331 mips_disable_float_construction = 1;
10343 target_big_endian = 1;
10347 target_big_endian = 0;
10351 if (arg && arg[1] == '0')
10361 mips_debug = atoi (arg);
10362 /* When the MIPS assembler sees -g or -g2, it does not do
10363 optimizations which limit full symbolic debugging. We take
10364 that to be equivalent to -O0. */
10365 if (mips_debug == 2)
10370 file_mips_isa = ISA_MIPS1;
10374 file_mips_isa = ISA_MIPS2;
10378 file_mips_isa = ISA_MIPS3;
10382 file_mips_isa = ISA_MIPS4;
10386 file_mips_isa = ISA_MIPS5;
10389 case OPTION_MIPS32:
10390 file_mips_isa = ISA_MIPS32;
10393 case OPTION_MIPS32R2:
10394 file_mips_isa = ISA_MIPS32R2;
10397 case OPTION_MIPS64R2:
10398 file_mips_isa = ISA_MIPS64R2;
10401 case OPTION_MIPS64:
10402 file_mips_isa = ISA_MIPS64;
10406 mips_set_option_string (&mips_tune_string, arg);
10410 mips_set_option_string (&mips_arch_string, arg);
10414 mips_set_option_string (&mips_arch_string, "4650");
10415 mips_set_option_string (&mips_tune_string, "4650");
10418 case OPTION_NO_M4650:
10422 mips_set_option_string (&mips_arch_string, "4010");
10423 mips_set_option_string (&mips_tune_string, "4010");
10426 case OPTION_NO_M4010:
10430 mips_set_option_string (&mips_arch_string, "4100");
10431 mips_set_option_string (&mips_tune_string, "4100");
10434 case OPTION_NO_M4100:
10438 mips_set_option_string (&mips_arch_string, "3900");
10439 mips_set_option_string (&mips_tune_string, "3900");
10442 case OPTION_NO_M3900:
10446 mips_opts.ase_mdmx = 1;
10449 case OPTION_NO_MDMX:
10450 mips_opts.ase_mdmx = 0;
10453 case OPTION_MIPS16:
10454 mips_opts.mips16 = 1;
10455 mips_no_prev_insn (FALSE);
10458 case OPTION_NO_MIPS16:
10459 mips_opts.mips16 = 0;
10460 mips_no_prev_insn (FALSE);
10463 case OPTION_MIPS3D:
10464 mips_opts.ase_mips3d = 1;
10467 case OPTION_NO_MIPS3D:
10468 mips_opts.ase_mips3d = 0;
10471 case OPTION_MEMBEDDED_PIC:
10472 mips_pic = EMBEDDED_PIC;
10473 if (USE_GLOBAL_POINTER_OPT && g_switch_seen)
10475 as_bad (_("-G may not be used with embedded PIC code"));
10478 g_switch_value = 0x7fffffff;
10481 case OPTION_FIX_VR4122:
10482 mips_fix_4122_bugs = 1;
10485 case OPTION_NO_FIX_VR4122:
10486 mips_fix_4122_bugs = 0;
10489 case OPTION_RELAX_BRANCH:
10490 mips_relax_branch = 1;
10493 case OPTION_NO_RELAX_BRANCH:
10494 mips_relax_branch = 0;
10498 /* When generating ELF code, we permit -KPIC and -call_shared to
10499 select SVR4_PIC, and -non_shared to select no PIC. This is
10500 intended to be compatible with Irix 5. */
10501 case OPTION_CALL_SHARED:
10502 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10504 as_bad (_("-call_shared is supported only for ELF format"));
10507 mips_pic = SVR4_PIC;
10508 mips_abicalls = TRUE;
10509 if (g_switch_seen && g_switch_value != 0)
10511 as_bad (_("-G may not be used with SVR4 PIC code"));
10514 g_switch_value = 0;
10517 case OPTION_NON_SHARED:
10518 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10520 as_bad (_("-non_shared is supported only for ELF format"));
10524 mips_abicalls = FALSE;
10527 /* The -xgot option tells the assembler to use 32 offsets when
10528 accessing the got in SVR4_PIC mode. It is for Irix
10533 #endif /* OBJ_ELF */
10536 if (! USE_GLOBAL_POINTER_OPT)
10538 as_bad (_("-G is not supported for this configuration"));
10541 else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC)
10543 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
10547 g_switch_value = atoi (arg);
10552 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10555 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10557 as_bad (_("-32 is supported for ELF format only"));
10560 mips_abi = O32_ABI;
10564 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10566 as_bad (_("-n32 is supported for ELF format only"));
10569 mips_abi = N32_ABI;
10573 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10575 as_bad (_("-64 is supported for ELF format only"));
10578 mips_abi = N64_ABI;
10579 if (! support_64bit_objects())
10580 as_fatal (_("No compiled in support for 64 bit object file format"));
10582 #endif /* OBJ_ELF */
10585 file_mips_gp32 = 1;
10589 file_mips_gp32 = 0;
10593 file_mips_fp32 = 1;
10597 file_mips_fp32 = 0;
10602 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10604 as_bad (_("-mabi is supported for ELF format only"));
10607 if (strcmp (arg, "32") == 0)
10608 mips_abi = O32_ABI;
10609 else if (strcmp (arg, "o64") == 0)
10610 mips_abi = O64_ABI;
10611 else if (strcmp (arg, "n32") == 0)
10612 mips_abi = N32_ABI;
10613 else if (strcmp (arg, "64") == 0)
10615 mips_abi = N64_ABI;
10616 if (! support_64bit_objects())
10617 as_fatal (_("No compiled in support for 64 bit object file "
10620 else if (strcmp (arg, "eabi") == 0)
10621 mips_abi = EABI_ABI;
10624 as_fatal (_("invalid abi -mabi=%s"), arg);
10628 #endif /* OBJ_ELF */
10630 case OPTION_M7000_HILO_FIX:
10631 mips_7000_hilo_fix = TRUE;
10634 case OPTION_MNO_7000_HILO_FIX:
10635 mips_7000_hilo_fix = FALSE;
10639 case OPTION_MDEBUG:
10640 mips_flag_mdebug = TRUE;
10643 case OPTION_NO_MDEBUG:
10644 mips_flag_mdebug = FALSE;
10648 mips_flag_pdr = TRUE;
10651 case OPTION_NO_PDR:
10652 mips_flag_pdr = FALSE;
10654 #endif /* OBJ_ELF */
10663 /* Set up globals to generate code for the ISA or processor
10664 described by INFO. */
10667 mips_set_architecture (const struct mips_cpu_info *info)
10671 file_mips_arch = info->cpu;
10672 mips_opts.arch = info->cpu;
10673 mips_opts.isa = info->isa;
10678 /* Likewise for tuning. */
10681 mips_set_tune (const struct mips_cpu_info *info)
10684 mips_tune = info->cpu;
10689 mips_after_parse_args (void)
10691 const struct mips_cpu_info *arch_info = 0;
10692 const struct mips_cpu_info *tune_info = 0;
10694 /* GP relative stuff not working for PE */
10695 if (strncmp (TARGET_OS, "pe", 2) == 0
10696 && g_switch_value != 0)
10699 as_bad (_("-G not supported in this configuration."));
10700 g_switch_value = 0;
10703 if (mips_abi == NO_ABI)
10704 mips_abi = MIPS_DEFAULT_ABI;
10706 /* The following code determines the architecture and register size.
10707 Similar code was added to GCC 3.3 (see override_options() in
10708 config/mips/mips.c). The GAS and GCC code should be kept in sync
10709 as much as possible. */
10711 if (mips_arch_string != 0)
10712 arch_info = mips_parse_cpu ("-march", mips_arch_string);
10714 if (file_mips_isa != ISA_UNKNOWN)
10716 /* Handle -mipsN. At this point, file_mips_isa contains the
10717 ISA level specified by -mipsN, while arch_info->isa contains
10718 the -march selection (if any). */
10719 if (arch_info != 0)
10721 /* -march takes precedence over -mipsN, since it is more descriptive.
10722 There's no harm in specifying both as long as the ISA levels
10724 if (file_mips_isa != arch_info->isa)
10725 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10726 mips_cpu_info_from_isa (file_mips_isa)->name,
10727 mips_cpu_info_from_isa (arch_info->isa)->name);
10730 arch_info = mips_cpu_info_from_isa (file_mips_isa);
10733 if (arch_info == 0)
10734 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
10736 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
10737 as_bad ("-march=%s is not compatible with the selected ABI",
10740 mips_set_architecture (arch_info);
10742 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
10743 if (mips_tune_string != 0)
10744 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
10746 if (tune_info == 0)
10747 mips_set_tune (arch_info);
10749 mips_set_tune (tune_info);
10751 if (file_mips_gp32 >= 0)
10753 /* The user specified the size of the integer registers. Make sure
10754 it agrees with the ABI and ISA. */
10755 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
10756 as_bad (_("-mgp64 used with a 32-bit processor"));
10757 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
10758 as_bad (_("-mgp32 used with a 64-bit ABI"));
10759 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
10760 as_bad (_("-mgp64 used with a 32-bit ABI"));
10764 /* Infer the integer register size from the ABI and processor.
10765 Restrict ourselves to 32-bit registers if that's all the
10766 processor has, or if the ABI cannot handle 64-bit registers. */
10767 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
10768 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
10771 /* ??? GAS treats single-float processors as though they had 64-bit
10772 float registers (although it complains when double-precision
10773 instructions are used). As things stand, saying they have 32-bit
10774 registers would lead to spurious "register must be even" messages.
10775 So here we assume float registers are always the same size as
10776 integer ones, unless the user says otherwise. */
10777 if (file_mips_fp32 < 0)
10778 file_mips_fp32 = file_mips_gp32;
10780 /* End of GCC-shared inference code. */
10782 /* This flag is set when we have a 64-bit capable CPU but use only
10783 32-bit wide registers. Note that EABI does not use it. */
10784 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
10785 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
10786 || mips_abi == O32_ABI))
10787 mips_32bitmode = 1;
10789 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
10790 as_bad (_("trap exception not supported at ISA 1"));
10792 /* If the selected architecture includes support for ASEs, enable
10793 generation of code for them. */
10794 if (mips_opts.mips16 == -1)
10795 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
10796 if (mips_opts.ase_mips3d == -1)
10797 mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0;
10798 if (mips_opts.ase_mdmx == -1)
10799 mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0;
10801 file_mips_isa = mips_opts.isa;
10802 file_ase_mips16 = mips_opts.mips16;
10803 file_ase_mips3d = mips_opts.ase_mips3d;
10804 file_ase_mdmx = mips_opts.ase_mdmx;
10805 mips_opts.gp32 = file_mips_gp32;
10806 mips_opts.fp32 = file_mips_fp32;
10808 if (mips_flag_mdebug < 0)
10810 #ifdef OBJ_MAYBE_ECOFF
10811 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
10812 mips_flag_mdebug = 1;
10814 #endif /* OBJ_MAYBE_ECOFF */
10815 mips_flag_mdebug = 0;
10820 mips_init_after_args (void)
10822 /* initialize opcodes */
10823 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
10824 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
10828 md_pcrel_from (fixS *fixP)
10830 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
10831 switch (fixP->fx_r_type)
10833 case BFD_RELOC_16_PCREL_S2:
10834 case BFD_RELOC_MIPS_JMP:
10835 /* Return the address of the delay slot. */
10842 /* This is called before the symbol table is processed. In order to
10843 work with gcc when using mips-tfile, we must keep all local labels.
10844 However, in other cases, we want to discard them. If we were
10845 called with -g, but we didn't see any debugging information, it may
10846 mean that gcc is smuggling debugging information through to
10847 mips-tfile, in which case we must generate all local labels. */
10850 mips_frob_file_before_adjust (void)
10852 #ifndef NO_ECOFF_DEBUGGING
10853 if (ECOFF_DEBUGGING
10855 && ! ecoff_debugging_seen)
10856 flag_keep_locals = 1;
10860 /* Sort any unmatched HI16_S relocs so that they immediately precede
10861 the corresponding LO reloc. This is called before md_apply_fix3 and
10862 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10863 explicit use of the %hi modifier. */
10866 mips_frob_file (void)
10868 struct mips_hi_fixup *l;
10870 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
10872 segment_info_type *seginfo;
10875 assert (reloc_needs_lo_p (l->fixp->fx_r_type));
10877 /* If a GOT16 relocation turns out to be against a global symbol,
10878 there isn't supposed to be a matching LO. */
10879 if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
10880 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
10883 /* Check quickly whether the next fixup happens to be a matching %lo. */
10884 if (fixup_has_matching_lo_p (l->fixp))
10887 /* Look through the fixups for this segment for a matching %lo.
10888 When we find one, move the %hi just in front of it. We do
10889 this in two passes. In the first pass, we try to find a
10890 unique %lo. In the second pass, we permit multiple %hi
10891 relocs for a single %lo (this is a GNU extension). */
10892 seginfo = seg_info (l->seg);
10893 for (pass = 0; pass < 2; pass++)
10898 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
10900 /* Check whether this is a %lo fixup which matches l->fixp. */
10901 if (f->fx_r_type == BFD_RELOC_LO16
10902 && f->fx_addsy == l->fixp->fx_addsy
10903 && f->fx_offset == l->fixp->fx_offset
10906 || !reloc_needs_lo_p (prev->fx_r_type)
10907 || !fixup_has_matching_lo_p (prev)))
10911 /* Move l->fixp before f. */
10912 for (pf = &seginfo->fix_root;
10914 pf = &(*pf)->fx_next)
10915 assert (*pf != NULL);
10917 *pf = l->fixp->fx_next;
10919 l->fixp->fx_next = f;
10921 seginfo->fix_root = l->fixp;
10923 prev->fx_next = l->fixp;
10934 #if 0 /* GCC code motion plus incomplete dead code elimination
10935 can leave a %hi without a %lo. */
10937 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
10938 _("Unmatched %%hi reloc"));
10944 /* When generating embedded PIC code we need to use a special
10945 relocation to represent the difference of two symbols in the .text
10946 section (switch tables use a difference of this sort). See
10947 include/coff/mips.h for details. This macro checks whether this
10948 fixup requires the special reloc. */
10949 #define SWITCH_TABLE(fixp) \
10950 ((fixp)->fx_r_type == BFD_RELOC_32 \
10951 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
10952 && (fixp)->fx_addsy != NULL \
10953 && (fixp)->fx_subsy != NULL \
10954 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
10955 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
10957 /* When generating embedded PIC code we must keep all PC relative
10958 relocations, in case the linker has to relax a call. We also need
10959 to keep relocations for switch table entries.
10961 We may have combined relocations without symbols in the N32/N64 ABI.
10962 We have to prevent gas from dropping them. */
10965 mips_force_relocation (fixS *fixp)
10967 if (generic_force_reloc (fixp))
10971 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
10972 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
10973 || fixp->fx_r_type == BFD_RELOC_HI16_S
10974 || fixp->fx_r_type == BFD_RELOC_LO16))
10977 return (mips_pic == EMBEDDED_PIC
10979 || SWITCH_TABLE (fixp)
10980 || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S
10981 || fixp->fx_r_type == BFD_RELOC_PCREL_LO16));
10984 /* This hook is called before a fix is simplified. We don't really
10985 decide whether to skip a fix here. Rather, we turn global symbols
10986 used as branch targets into local symbols, such that they undergo
10987 simplification. We can only do this if the symbol is defined and
10988 it is in the same section as the branch. If this doesn't hold, we
10989 emit a better error message than just saying the relocation is not
10990 valid for the selected object format.
10992 FIXP is the fix-up we're going to try to simplify, SEG is the
10993 segment in which the fix up occurs. The return value should be
10994 non-zero to indicate the fix-up is valid for further
10995 simplifications. */
10998 mips_validate_fix (struct fix *fixP, asection *seg)
11000 /* There's a lot of discussion on whether it should be possible to
11001 use R_MIPS_PC16 to represent branch relocations. The outcome
11002 seems to be that it can, but gas/bfd are very broken in creating
11003 RELA relocations for this, so for now we only accept branches to
11004 symbols in the same section. Anything else is of dubious value,
11005 since there's no guarantee that at link time the symbol would be
11006 in range. Even for branches to local symbols this is arguably
11007 wrong, since it we assume the symbol is not going to be
11008 overridden, which should be possible per ELF library semantics,
11009 but then, there isn't a dynamic relocation that could be used to
11010 this effect, and the target would likely be out of range as well.
11012 Unfortunately, it seems that there is too much code out there
11013 that relies on branches to symbols that are global to be resolved
11014 as if they were local, like the IRIX tools do, so we do it as
11015 well, but with a warning so that people are reminded to fix their
11016 code. If we ever get back to using R_MIPS_PC16 for branch
11017 targets, this entire block should go away (and probably the
11018 whole function). */
11020 if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
11021 && (((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
11022 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
11023 && mips_pic != EMBEDDED_PIC)
11024 || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL)
11027 if (! S_IS_DEFINED (fixP->fx_addsy))
11029 as_bad_where (fixP->fx_file, fixP->fx_line,
11030 _("Cannot branch to undefined symbol."));
11031 /* Avoid any further errors about this fixup. */
11034 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
11036 as_bad_where (fixP->fx_file, fixP->fx_line,
11037 _("Cannot branch to symbol in another section."));
11040 else if (S_IS_EXTERNAL (fixP->fx_addsy))
11042 symbolS *sym = fixP->fx_addsy;
11044 if (mips_pic == SVR4_PIC)
11045 as_warn_where (fixP->fx_file, fixP->fx_line,
11046 _("Pretending global symbol used as branch target is local."));
11048 fixP->fx_addsy = symbol_create (S_GET_NAME (sym),
11049 S_GET_SEGMENT (sym),
11051 symbol_get_frag (sym));
11052 copy_symbol_attributes (fixP->fx_addsy, sym);
11053 S_CLEAR_EXTERNAL (fixP->fx_addsy);
11054 assert (symbol_resolved_p (sym));
11055 symbol_mark_resolved (fixP->fx_addsy);
11062 /* Apply a fixup to the object file. */
11065 md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
11069 static int previous_fx_r_type = 0;
11070 reloc_howto_type *howto;
11072 /* We ignore generic BFD relocations we don't know about. */
11073 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
11077 assert (fixP->fx_size == 4
11078 || fixP->fx_r_type == BFD_RELOC_16
11079 || fixP->fx_r_type == BFD_RELOC_64
11080 || fixP->fx_r_type == BFD_RELOC_CTOR
11081 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
11082 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
11083 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY);
11085 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
11087 /* We are not done if this is a composite relocation to set up gp. */
11088 if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel
11089 && !(fixP->fx_r_type == BFD_RELOC_MIPS_SUB
11090 || (fixP->fx_r_type == BFD_RELOC_64
11091 && (previous_fx_r_type == BFD_RELOC_GPREL32
11092 || previous_fx_r_type == BFD_RELOC_GPREL16))
11093 || (previous_fx_r_type == BFD_RELOC_MIPS_SUB
11094 && (fixP->fx_r_type == BFD_RELOC_HI16_S
11095 || fixP->fx_r_type == BFD_RELOC_LO16))))
11097 previous_fx_r_type = fixP->fx_r_type;
11099 switch (fixP->fx_r_type)
11101 case BFD_RELOC_MIPS_JMP:
11102 case BFD_RELOC_MIPS_SHIFT5:
11103 case BFD_RELOC_MIPS_SHIFT6:
11104 case BFD_RELOC_MIPS_GOT_DISP:
11105 case BFD_RELOC_MIPS_GOT_PAGE:
11106 case BFD_RELOC_MIPS_GOT_OFST:
11107 case BFD_RELOC_MIPS_SUB:
11108 case BFD_RELOC_MIPS_INSERT_A:
11109 case BFD_RELOC_MIPS_INSERT_B:
11110 case BFD_RELOC_MIPS_DELETE:
11111 case BFD_RELOC_MIPS_HIGHEST:
11112 case BFD_RELOC_MIPS_HIGHER:
11113 case BFD_RELOC_MIPS_SCN_DISP:
11114 case BFD_RELOC_MIPS_REL16:
11115 case BFD_RELOC_MIPS_RELGOT:
11116 case BFD_RELOC_MIPS_JALR:
11117 case BFD_RELOC_HI16:
11118 case BFD_RELOC_HI16_S:
11119 case BFD_RELOC_GPREL16:
11120 case BFD_RELOC_MIPS_LITERAL:
11121 case BFD_RELOC_MIPS_CALL16:
11122 case BFD_RELOC_MIPS_GOT16:
11123 case BFD_RELOC_GPREL32:
11124 case BFD_RELOC_MIPS_GOT_HI16:
11125 case BFD_RELOC_MIPS_GOT_LO16:
11126 case BFD_RELOC_MIPS_CALL_HI16:
11127 case BFD_RELOC_MIPS_CALL_LO16:
11128 case BFD_RELOC_MIPS16_GPREL:
11129 if (fixP->fx_pcrel)
11130 as_bad_where (fixP->fx_file, fixP->fx_line,
11131 _("Invalid PC relative reloc"));
11132 /* Nothing needed to do. The value comes from the reloc entry */
11135 case BFD_RELOC_MIPS16_JMP:
11136 /* We currently always generate a reloc against a symbol, which
11137 means that we don't want an addend even if the symbol is
11142 case BFD_RELOC_PCREL_HI16_S:
11143 /* The addend for this is tricky if it is internal, so we just
11144 do everything here rather than in bfd_install_relocation. */
11145 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done)
11148 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
11150 /* For an external symbol adjust by the address to make it
11151 pcrel_offset. We use the address of the RELLO reloc
11152 which follows this one. */
11153 *valP += (fixP->fx_next->fx_frag->fr_address
11154 + fixP->fx_next->fx_where);
11156 *valP = ((*valP + 0x8000) >> 16) & 0xffff;
11157 if (target_big_endian)
11159 md_number_to_chars (buf, *valP, 2);
11162 case BFD_RELOC_PCREL_LO16:
11163 /* The addend for this is tricky if it is internal, so we just
11164 do everything here rather than in bfd_install_relocation. */
11165 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done)
11168 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
11169 *valP += fixP->fx_frag->fr_address + fixP->fx_where;
11170 if (target_big_endian)
11172 md_number_to_chars (buf, *valP, 2);
11176 /* This is handled like BFD_RELOC_32, but we output a sign
11177 extended value if we are only 32 bits. */
11179 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
11181 if (8 <= sizeof (valueT))
11182 md_number_to_chars (buf, *valP, 8);
11187 if ((*valP & 0x80000000) != 0)
11191 md_number_to_chars ((char *)(buf + target_big_endian ? 4 : 0),
11193 md_number_to_chars ((char *)(buf + target_big_endian ? 0 : 4),
11199 case BFD_RELOC_RVA:
11201 /* If we are deleting this reloc entry, we must fill in the
11202 value now. This can happen if we have a .word which is not
11203 resolved when it appears but is later defined. We also need
11204 to fill in the value if this is an embedded PIC switch table
11207 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
11208 md_number_to_chars (buf, *valP, 4);
11212 /* If we are deleting this reloc entry, we must fill in the
11214 assert (fixP->fx_size == 2);
11216 md_number_to_chars (buf, *valP, 2);
11219 case BFD_RELOC_LO16:
11220 /* When handling an embedded PIC switch statement, we can wind
11221 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11224 if (*valP + 0x8000 > 0xffff)
11225 as_bad_where (fixP->fx_file, fixP->fx_line,
11226 _("relocation overflow"));
11227 if (target_big_endian)
11229 md_number_to_chars (buf, *valP, 2);
11233 case BFD_RELOC_16_PCREL_S2:
11234 if ((*valP & 0x3) != 0)
11235 as_bad_where (fixP->fx_file, fixP->fx_line,
11236 _("Branch to odd address (%lx)"), (long) *valP);
11239 * We need to save the bits in the instruction since fixup_segment()
11240 * might be deleting the relocation entry (i.e., a branch within
11241 * the current segment).
11243 if (! fixP->fx_done)
11246 /* update old instruction data */
11247 if (target_big_endian)
11248 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
11250 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
11252 if (*valP + 0x20000 <= 0x3ffff)
11254 insn |= (*valP >> 2) & 0xffff;
11255 md_number_to_chars (buf, insn, 4);
11257 else if (mips_pic == NO_PIC
11259 && fixP->fx_frag->fr_address >= text_section->vma
11260 && (fixP->fx_frag->fr_address
11261 < text_section->vma + text_section->_raw_size)
11262 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
11263 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
11264 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
11266 /* The branch offset is too large. If this is an
11267 unconditional branch, and we are not generating PIC code,
11268 we can convert it to an absolute jump instruction. */
11269 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
11270 insn = 0x0c000000; /* jal */
11272 insn = 0x08000000; /* j */
11273 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
11275 fixP->fx_addsy = section_symbol (text_section);
11276 *valP += md_pcrel_from (fixP);
11277 md_number_to_chars (buf, insn, 4);
11281 /* If we got here, we have branch-relaxation disabled,
11282 and there's nothing we can do to fix this instruction
11283 without turning it into a longer sequence. */
11284 as_bad_where (fixP->fx_file, fixP->fx_line,
11285 _("Branch out of range"));
11289 case BFD_RELOC_VTABLE_INHERIT:
11292 && !S_IS_DEFINED (fixP->fx_addsy)
11293 && !S_IS_WEAK (fixP->fx_addsy))
11294 S_SET_WEAK (fixP->fx_addsy);
11297 case BFD_RELOC_VTABLE_ENTRY:
11305 /* Remember value for tc_gen_reloc. */
11306 fixP->fx_addnumber = *valP;
11311 printInsn (unsigned long oc)
11313 const struct mips_opcode *p;
11314 int treg, sreg, dreg, shamt;
11319 for (i = 0; i < NUMOPCODES; ++i)
11321 p = &mips_opcodes[i];
11322 if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO))
11324 printf ("%08lx %s\t", oc, p->name);
11325 treg = (oc >> 16) & 0x1f;
11326 sreg = (oc >> 21) & 0x1f;
11327 dreg = (oc >> 11) & 0x1f;
11328 shamt = (oc >> 6) & 0x1f;
11330 for (args = p->args;; ++args)
11341 printf ("%c", *args);
11345 assert (treg == sreg);
11346 printf ("$%d,$%d", treg, sreg);
11351 printf ("$%d", dreg);
11356 printf ("$%d", treg);
11360 printf ("0x%x", treg);
11365 printf ("$%d", sreg);
11369 printf ("0x%08lx", oc & 0x1ffffff);
11376 printf ("%d", imm);
11381 printf ("$%d", shamt);
11392 printf (_("%08lx UNDEFINED\n"), oc);
11403 name = input_line_pointer;
11404 c = get_symbol_end ();
11405 p = (symbolS *) symbol_find_or_make (name);
11406 *input_line_pointer = c;
11410 /* Align the current frag to a given power of two. The MIPS assembler
11411 also automatically adjusts any preceding label. */
11414 mips_align (int to, int fill, symbolS *label)
11416 mips_emit_delays (FALSE);
11417 frag_align (to, fill, 0);
11418 record_alignment (now_seg, to);
11421 assert (S_GET_SEGMENT (label) == now_seg);
11422 symbol_set_frag (label, frag_now);
11423 S_SET_VALUE (label, (valueT) frag_now_fix ());
11427 /* Align to a given power of two. .align 0 turns off the automatic
11428 alignment used by the data creating pseudo-ops. */
11431 s_align (int x ATTRIBUTE_UNUSED)
11434 register long temp_fill;
11435 long max_alignment = 15;
11439 o Note that the assembler pulls down any immediately preceding label
11440 to the aligned address.
11441 o It's not documented but auto alignment is reinstated by
11442 a .align pseudo instruction.
11443 o Note also that after auto alignment is turned off the mips assembler
11444 issues an error on attempt to assemble an improperly aligned data item.
11449 temp = get_absolute_expression ();
11450 if (temp > max_alignment)
11451 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
11454 as_warn (_("Alignment negative: 0 assumed."));
11457 if (*input_line_pointer == ',')
11459 ++input_line_pointer;
11460 temp_fill = get_absolute_expression ();
11467 mips_align (temp, (int) temp_fill,
11468 insn_labels != NULL ? insn_labels->label : NULL);
11475 demand_empty_rest_of_line ();
11479 mips_flush_pending_output (void)
11481 mips_emit_delays (FALSE);
11482 mips_clear_insn_labels ();
11486 s_change_sec (int sec)
11490 /* When generating embedded PIC code, we only use the .text, .lit8,
11491 .sdata and .sbss sections. We change the .data and .rdata
11492 pseudo-ops to use .sdata. */
11493 if (mips_pic == EMBEDDED_PIC
11494 && (sec == 'd' || sec == 'r'))
11498 /* The ELF backend needs to know that we are changing sections, so
11499 that .previous works correctly. We could do something like check
11500 for an obj_section_change_hook macro, but that might be confusing
11501 as it would not be appropriate to use it in the section changing
11502 functions in read.c, since obj-elf.c intercepts those. FIXME:
11503 This should be cleaner, somehow. */
11504 obj_elf_section_change_hook ();
11507 mips_emit_delays (FALSE);
11517 subseg_set (bss_section, (subsegT) get_absolute_expression ());
11518 demand_empty_rest_of_line ();
11522 if (USE_GLOBAL_POINTER_OPT)
11524 seg = subseg_new (RDATA_SECTION_NAME,
11525 (subsegT) get_absolute_expression ());
11526 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11528 bfd_set_section_flags (stdoutput, seg,
11534 if (strcmp (TARGET_OS, "elf") != 0)
11535 record_alignment (seg, 4);
11537 demand_empty_rest_of_line ();
11541 as_bad (_("No read only data section in this object file format"));
11542 demand_empty_rest_of_line ();
11548 if (USE_GLOBAL_POINTER_OPT)
11550 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
11551 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11553 bfd_set_section_flags (stdoutput, seg,
11554 SEC_ALLOC | SEC_LOAD | SEC_RELOC
11556 if (strcmp (TARGET_OS, "elf") != 0)
11557 record_alignment (seg, 4);
11559 demand_empty_rest_of_line ();
11564 as_bad (_("Global pointers not supported; recompile -G 0"));
11565 demand_empty_rest_of_line ();
11574 s_change_section (int ignore ATTRIBUTE_UNUSED)
11577 char *section_name;
11582 int section_entry_size;
11583 int section_alignment;
11585 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
11588 section_name = input_line_pointer;
11589 c = get_symbol_end ();
11591 next_c = *(input_line_pointer + 1);
11593 /* Do we have .section Name<,"flags">? */
11594 if (c != ',' || (c == ',' && next_c == '"'))
11596 /* just after name is now '\0'. */
11597 *input_line_pointer = c;
11598 input_line_pointer = section_name;
11599 obj_elf_section (ignore);
11602 input_line_pointer++;
11604 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11606 section_type = get_absolute_expression ();
11609 if (*input_line_pointer++ == ',')
11610 section_flag = get_absolute_expression ();
11613 if (*input_line_pointer++ == ',')
11614 section_entry_size = get_absolute_expression ();
11616 section_entry_size = 0;
11617 if (*input_line_pointer++ == ',')
11618 section_alignment = get_absolute_expression ();
11620 section_alignment = 0;
11622 section_name = xstrdup (section_name);
11624 /* When using the generic form of .section (as implemented by obj-elf.c),
11625 there's no way to set the section type to SHT_MIPS_DWARF. Users have
11626 traditionally had to fall back on the more common @progbits instead.
11628 There's nothing really harmful in this, since bfd will correct
11629 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
11630 means that, for backwards compatibiltiy, the special_section entries
11631 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
11633 Even so, we shouldn't force users of the MIPS .section syntax to
11634 incorrectly label the sections as SHT_PROGBITS. The best compromise
11635 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
11636 generic type-checking code. */
11637 if (section_type == SHT_MIPS_DWARF)
11638 section_type = SHT_PROGBITS;
11640 obj_elf_change_section (section_name, section_type, section_flag,
11641 section_entry_size, 0, 0, 0);
11643 if (now_seg->name != section_name)
11644 free (section_name);
11645 #endif /* OBJ_ELF */
11649 mips_enable_auto_align (void)
11655 s_cons (int log_size)
11659 label = insn_labels != NULL ? insn_labels->label : NULL;
11660 mips_emit_delays (FALSE);
11661 if (log_size > 0 && auto_align)
11662 mips_align (log_size, 0, label);
11663 mips_clear_insn_labels ();
11664 cons (1 << log_size);
11668 s_float_cons (int type)
11672 label = insn_labels != NULL ? insn_labels->label : NULL;
11674 mips_emit_delays (FALSE);
11679 mips_align (3, 0, label);
11681 mips_align (2, 0, label);
11684 mips_clear_insn_labels ();
11689 /* Handle .globl. We need to override it because on Irix 5 you are
11692 where foo is an undefined symbol, to mean that foo should be
11693 considered to be the address of a function. */
11696 s_mips_globl (int x ATTRIBUTE_UNUSED)
11703 name = input_line_pointer;
11704 c = get_symbol_end ();
11705 symbolP = symbol_find_or_make (name);
11706 *input_line_pointer = c;
11707 SKIP_WHITESPACE ();
11709 /* On Irix 5, every global symbol that is not explicitly labelled as
11710 being a function is apparently labelled as being an object. */
11713 if (! is_end_of_line[(unsigned char) *input_line_pointer])
11718 secname = input_line_pointer;
11719 c = get_symbol_end ();
11720 sec = bfd_get_section_by_name (stdoutput, secname);
11722 as_bad (_("%s: no such section"), secname);
11723 *input_line_pointer = c;
11725 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
11726 flag = BSF_FUNCTION;
11729 symbol_get_bfdsym (symbolP)->flags |= flag;
11731 S_SET_EXTERNAL (symbolP);
11732 demand_empty_rest_of_line ();
11736 s_option (int x ATTRIBUTE_UNUSED)
11741 opt = input_line_pointer;
11742 c = get_symbol_end ();
11746 /* FIXME: What does this mean? */
11748 else if (strncmp (opt, "pic", 3) == 0)
11752 i = atoi (opt + 3);
11757 mips_pic = SVR4_PIC;
11758 mips_abicalls = TRUE;
11761 as_bad (_(".option pic%d not supported"), i);
11763 if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC)
11765 if (g_switch_seen && g_switch_value != 0)
11766 as_warn (_("-G may not be used with SVR4 PIC code"));
11767 g_switch_value = 0;
11768 bfd_set_gp_size (stdoutput, 0);
11772 as_warn (_("Unrecognized option \"%s\""), opt);
11774 *input_line_pointer = c;
11775 demand_empty_rest_of_line ();
11778 /* This structure is used to hold a stack of .set values. */
11780 struct mips_option_stack
11782 struct mips_option_stack *next;
11783 struct mips_set_options options;
11786 static struct mips_option_stack *mips_opts_stack;
11788 /* Handle the .set pseudo-op. */
11791 s_mipsset (int x ATTRIBUTE_UNUSED)
11793 char *name = input_line_pointer, ch;
11795 while (!is_end_of_line[(unsigned char) *input_line_pointer])
11796 ++input_line_pointer;
11797 ch = *input_line_pointer;
11798 *input_line_pointer = '\0';
11800 if (strcmp (name, "reorder") == 0)
11802 if (mips_opts.noreorder && prev_nop_frag != NULL)
11804 /* If we still have pending nops, we can discard them. The
11805 usual nop handling will insert any that are still
11807 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11808 * (mips_opts.mips16 ? 2 : 4));
11809 prev_nop_frag = NULL;
11811 mips_opts.noreorder = 0;
11813 else if (strcmp (name, "noreorder") == 0)
11815 mips_emit_delays (TRUE);
11816 mips_opts.noreorder = 1;
11817 mips_any_noreorder = 1;
11819 else if (strcmp (name, "at") == 0)
11821 mips_opts.noat = 0;
11823 else if (strcmp (name, "noat") == 0)
11825 mips_opts.noat = 1;
11827 else if (strcmp (name, "macro") == 0)
11829 mips_opts.warn_about_macros = 0;
11831 else if (strcmp (name, "nomacro") == 0)
11833 if (mips_opts.noreorder == 0)
11834 as_bad (_("`noreorder' must be set before `nomacro'"));
11835 mips_opts.warn_about_macros = 1;
11837 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
11839 mips_opts.nomove = 0;
11841 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
11843 mips_opts.nomove = 1;
11845 else if (strcmp (name, "bopt") == 0)
11847 mips_opts.nobopt = 0;
11849 else if (strcmp (name, "nobopt") == 0)
11851 mips_opts.nobopt = 1;
11853 else if (strcmp (name, "mips16") == 0
11854 || strcmp (name, "MIPS-16") == 0)
11855 mips_opts.mips16 = 1;
11856 else if (strcmp (name, "nomips16") == 0
11857 || strcmp (name, "noMIPS-16") == 0)
11858 mips_opts.mips16 = 0;
11859 else if (strcmp (name, "mips3d") == 0)
11860 mips_opts.ase_mips3d = 1;
11861 else if (strcmp (name, "nomips3d") == 0)
11862 mips_opts.ase_mips3d = 0;
11863 else if (strcmp (name, "mdmx") == 0)
11864 mips_opts.ase_mdmx = 1;
11865 else if (strcmp (name, "nomdmx") == 0)
11866 mips_opts.ase_mdmx = 0;
11867 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
11871 /* Permit the user to change the ISA and architecture on the fly.
11872 Needless to say, misuse can cause serious problems. */
11873 if (strcmp (name, "mips0") == 0)
11876 mips_opts.isa = file_mips_isa;
11878 else if (strcmp (name, "mips1") == 0)
11879 mips_opts.isa = ISA_MIPS1;
11880 else if (strcmp (name, "mips2") == 0)
11881 mips_opts.isa = ISA_MIPS2;
11882 else if (strcmp (name, "mips3") == 0)
11883 mips_opts.isa = ISA_MIPS3;
11884 else if (strcmp (name, "mips4") == 0)
11885 mips_opts.isa = ISA_MIPS4;
11886 else if (strcmp (name, "mips5") == 0)
11887 mips_opts.isa = ISA_MIPS5;
11888 else if (strcmp (name, "mips32") == 0)
11889 mips_opts.isa = ISA_MIPS32;
11890 else if (strcmp (name, "mips32r2") == 0)
11891 mips_opts.isa = ISA_MIPS32R2;
11892 else if (strcmp (name, "mips64") == 0)
11893 mips_opts.isa = ISA_MIPS64;
11894 else if (strcmp (name, "mips64r2") == 0)
11895 mips_opts.isa = ISA_MIPS64R2;
11896 else if (strcmp (name, "arch=default") == 0)
11899 mips_opts.arch = file_mips_arch;
11900 mips_opts.isa = file_mips_isa;
11902 else if (strncmp (name, "arch=", 5) == 0)
11904 const struct mips_cpu_info *p;
11906 p = mips_parse_cpu("internal use", name + 5);
11908 as_bad (_("unknown architecture %s"), name + 5);
11911 mips_opts.arch = p->cpu;
11912 mips_opts.isa = p->isa;
11916 as_bad (_("unknown ISA level %s"), name + 4);
11918 switch (mips_opts.isa)
11926 mips_opts.gp32 = 1;
11927 mips_opts.fp32 = 1;
11934 mips_opts.gp32 = 0;
11935 mips_opts.fp32 = 0;
11938 as_bad (_("unknown ISA level %s"), name + 4);
11943 mips_opts.gp32 = file_mips_gp32;
11944 mips_opts.fp32 = file_mips_fp32;
11947 else if (strcmp (name, "autoextend") == 0)
11948 mips_opts.noautoextend = 0;
11949 else if (strcmp (name, "noautoextend") == 0)
11950 mips_opts.noautoextend = 1;
11951 else if (strcmp (name, "push") == 0)
11953 struct mips_option_stack *s;
11955 s = (struct mips_option_stack *) xmalloc (sizeof *s);
11956 s->next = mips_opts_stack;
11957 s->options = mips_opts;
11958 mips_opts_stack = s;
11960 else if (strcmp (name, "pop") == 0)
11962 struct mips_option_stack *s;
11964 s = mips_opts_stack;
11966 as_bad (_(".set pop with no .set push"));
11969 /* If we're changing the reorder mode we need to handle
11970 delay slots correctly. */
11971 if (s->options.noreorder && ! mips_opts.noreorder)
11972 mips_emit_delays (TRUE);
11973 else if (! s->options.noreorder && mips_opts.noreorder)
11975 if (prev_nop_frag != NULL)
11977 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11978 * (mips_opts.mips16 ? 2 : 4));
11979 prev_nop_frag = NULL;
11983 mips_opts = s->options;
11984 mips_opts_stack = s->next;
11990 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
11992 *input_line_pointer = ch;
11993 demand_empty_rest_of_line ();
11996 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11997 .option pic2. It means to generate SVR4 PIC calls. */
12000 s_abicalls (int ignore ATTRIBUTE_UNUSED)
12002 mips_pic = SVR4_PIC;
12003 mips_abicalls = TRUE;
12004 if (USE_GLOBAL_POINTER_OPT)
12006 if (g_switch_seen && g_switch_value != 0)
12007 as_warn (_("-G may not be used with SVR4 PIC code"));
12008 g_switch_value = 0;
12010 bfd_set_gp_size (stdoutput, 0);
12011 demand_empty_rest_of_line ();
12014 /* Handle the .cpload pseudo-op. This is used when generating SVR4
12015 PIC code. It sets the $gp register for the function based on the
12016 function address, which is in the register named in the argument.
12017 This uses a relocation against _gp_disp, which is handled specially
12018 by the linker. The result is:
12019 lui $gp,%hi(_gp_disp)
12020 addiu $gp,$gp,%lo(_gp_disp)
12021 addu $gp,$gp,.cpload argument
12022 The .cpload argument is normally $25 == $t9. */
12025 s_cpload (int ignore ATTRIBUTE_UNUSED)
12029 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12030 .cpload is ignored. */
12031 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12037 /* .cpload should be in a .set noreorder section. */
12038 if (mips_opts.noreorder == 0)
12039 as_warn (_(".cpload not in noreorder section"));
12041 ex.X_op = O_symbol;
12042 ex.X_add_symbol = symbol_find_or_make ("_gp_disp");
12043 ex.X_op_symbol = NULL;
12044 ex.X_add_number = 0;
12046 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12047 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
12050 macro_build_lui (&ex, mips_gp_register);
12051 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
12052 mips_gp_register, BFD_RELOC_LO16);
12053 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
12054 mips_gp_register, tc_get_register (0));
12057 demand_empty_rest_of_line ();
12060 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12061 .cpsetup $reg1, offset|$reg2, label
12063 If offset is given, this results in:
12064 sd $gp, offset($sp)
12065 lui $gp, %hi(%neg(%gp_rel(label)))
12066 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12067 daddu $gp, $gp, $reg1
12069 If $reg2 is given, this results in:
12070 daddu $reg2, $gp, $0
12071 lui $gp, %hi(%neg(%gp_rel(label)))
12072 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12073 daddu $gp, $gp, $reg1
12074 $reg1 is normally $25 == $t9. */
12076 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
12078 expressionS ex_off;
12079 expressionS ex_sym;
12083 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12084 We also need NewABI support. */
12085 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12091 reg1 = tc_get_register (0);
12092 SKIP_WHITESPACE ();
12093 if (*input_line_pointer != ',')
12095 as_bad (_("missing argument separator ',' for .cpsetup"));
12099 ++input_line_pointer;
12100 SKIP_WHITESPACE ();
12101 if (*input_line_pointer == '$')
12103 mips_cpreturn_register = tc_get_register (0);
12104 mips_cpreturn_offset = -1;
12108 mips_cpreturn_offset = get_absolute_expression ();
12109 mips_cpreturn_register = -1;
12111 SKIP_WHITESPACE ();
12112 if (*input_line_pointer != ',')
12114 as_bad (_("missing argument separator ',' for .cpsetup"));
12118 ++input_line_pointer;
12119 SKIP_WHITESPACE ();
12120 expression (&ex_sym);
12123 if (mips_cpreturn_register == -1)
12125 ex_off.X_op = O_constant;
12126 ex_off.X_add_symbol = NULL;
12127 ex_off.X_op_symbol = NULL;
12128 ex_off.X_add_number = mips_cpreturn_offset;
12130 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
12131 BFD_RELOC_LO16, SP);
12134 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
12135 mips_gp_register, 0);
12137 /* Ensure there's room for the next two instructions, so that `f'
12138 doesn't end up with an address in the wrong frag. */
12141 macro_build (&ex_sym, "lui", "t,u", mips_gp_register, BFD_RELOC_GPREL16);
12142 fix_new (frag_now, f - frag_now->fr_literal,
12143 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
12144 fix_new (frag_now, f - frag_now->fr_literal,
12145 4, NULL, 0, 0, BFD_RELOC_HI16_S);
12148 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
12149 mips_gp_register, BFD_RELOC_GPREL16);
12150 fix_new (frag_now, f - frag_now->fr_literal,
12151 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
12152 fix_new (frag_now, f - frag_now->fr_literal,
12153 4, NULL, 0, 0, BFD_RELOC_LO16);
12155 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
12156 mips_gp_register, reg1);
12159 demand_empty_rest_of_line ();
12163 s_cplocal (int ignore ATTRIBUTE_UNUSED)
12165 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12166 .cplocal is ignored. */
12167 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12173 mips_gp_register = tc_get_register (0);
12174 demand_empty_rest_of_line ();
12177 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12178 offset from $sp. The offset is remembered, and after making a PIC
12179 call $gp is restored from that location. */
12182 s_cprestore (int ignore ATTRIBUTE_UNUSED)
12186 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12187 .cprestore is ignored. */
12188 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12194 mips_cprestore_offset = get_absolute_expression ();
12195 mips_cprestore_valid = 1;
12197 ex.X_op = O_constant;
12198 ex.X_add_symbol = NULL;
12199 ex.X_op_symbol = NULL;
12200 ex.X_add_number = mips_cprestore_offset;
12203 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
12204 SP, HAVE_64BIT_ADDRESSES);
12207 demand_empty_rest_of_line ();
12210 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12211 was given in the preceding .cpsetup, it results in:
12212 ld $gp, offset($sp)
12214 If a register $reg2 was given there, it results in:
12215 daddu $gp, $reg2, $0
12218 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
12222 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12223 We also need NewABI support. */
12224 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12231 if (mips_cpreturn_register == -1)
12233 ex.X_op = O_constant;
12234 ex.X_add_symbol = NULL;
12235 ex.X_op_symbol = NULL;
12236 ex.X_add_number = mips_cpreturn_offset;
12238 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
12241 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
12242 mips_cpreturn_register, 0);
12245 demand_empty_rest_of_line ();
12248 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12249 code. It sets the offset to use in gp_rel relocations. */
12252 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
12254 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12255 We also need NewABI support. */
12256 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12262 mips_gprel_offset = get_absolute_expression ();
12264 demand_empty_rest_of_line ();
12267 /* Handle the .gpword pseudo-op. This is used when generating PIC
12268 code. It generates a 32 bit GP relative reloc. */
12271 s_gpword (int ignore ATTRIBUTE_UNUSED)
12277 /* When not generating PIC code, this is treated as .word. */
12278 if (mips_pic != SVR4_PIC)
12284 label = insn_labels != NULL ? insn_labels->label : NULL;
12285 mips_emit_delays (TRUE);
12287 mips_align (2, 0, label);
12288 mips_clear_insn_labels ();
12292 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12294 as_bad (_("Unsupported use of .gpword"));
12295 ignore_rest_of_line ();
12299 md_number_to_chars (p, 0, 4);
12300 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
12301 BFD_RELOC_GPREL32);
12303 demand_empty_rest_of_line ();
12307 s_gpdword (int ignore ATTRIBUTE_UNUSED)
12313 /* When not generating PIC code, this is treated as .dword. */
12314 if (mips_pic != SVR4_PIC)
12320 label = insn_labels != NULL ? insn_labels->label : NULL;
12321 mips_emit_delays (TRUE);
12323 mips_align (3, 0, label);
12324 mips_clear_insn_labels ();
12328 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12330 as_bad (_("Unsupported use of .gpdword"));
12331 ignore_rest_of_line ();
12335 md_number_to_chars (p, 0, 8);
12336 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
12337 BFD_RELOC_GPREL32);
12339 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12340 ex.X_op = O_absent;
12341 ex.X_add_symbol = 0;
12342 ex.X_add_number = 0;
12343 fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &ex, FALSE,
12346 demand_empty_rest_of_line ();
12349 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12350 tables in SVR4 PIC code. */
12353 s_cpadd (int ignore ATTRIBUTE_UNUSED)
12357 /* This is ignored when not generating SVR4 PIC code. */
12358 if (mips_pic != SVR4_PIC)
12364 /* Add $gp to the register named as an argument. */
12366 reg = tc_get_register (0);
12367 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
12370 demand_empty_rest_of_line ();
12373 /* Handle the .insn pseudo-op. This marks instruction labels in
12374 mips16 mode. This permits the linker to handle them specially,
12375 such as generating jalx instructions when needed. We also make
12376 them odd for the duration of the assembly, in order to generate the
12377 right sort of code. We will make them even in the adjust_symtab
12378 routine, while leaving them marked. This is convenient for the
12379 debugger and the disassembler. The linker knows to make them odd
12383 s_insn (int ignore ATTRIBUTE_UNUSED)
12385 mips16_mark_labels ();
12387 demand_empty_rest_of_line ();
12390 /* Handle a .stabn directive. We need these in order to mark a label
12391 as being a mips16 text label correctly. Sometimes the compiler
12392 will emit a label, followed by a .stabn, and then switch sections.
12393 If the label and .stabn are in mips16 mode, then the label is
12394 really a mips16 text label. */
12397 s_mips_stab (int type)
12400 mips16_mark_labels ();
12405 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12409 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
12416 name = input_line_pointer;
12417 c = get_symbol_end ();
12418 symbolP = symbol_find_or_make (name);
12419 S_SET_WEAK (symbolP);
12420 *input_line_pointer = c;
12422 SKIP_WHITESPACE ();
12424 if (! is_end_of_line[(unsigned char) *input_line_pointer])
12426 if (S_IS_DEFINED (symbolP))
12428 as_bad ("ignoring attempt to redefine symbol %s",
12429 S_GET_NAME (symbolP));
12430 ignore_rest_of_line ();
12434 if (*input_line_pointer == ',')
12436 ++input_line_pointer;
12437 SKIP_WHITESPACE ();
12441 if (exp.X_op != O_symbol)
12443 as_bad ("bad .weakext directive");
12444 ignore_rest_of_line ();
12447 symbol_set_value_expression (symbolP, &exp);
12450 demand_empty_rest_of_line ();
12453 /* Parse a register string into a number. Called from the ECOFF code
12454 to parse .frame. The argument is non-zero if this is the frame
12455 register, so that we can record it in mips_frame_reg. */
12458 tc_get_register (int frame)
12462 SKIP_WHITESPACE ();
12463 if (*input_line_pointer++ != '$')
12465 as_warn (_("expected `$'"));
12468 else if (ISDIGIT (*input_line_pointer))
12470 reg = get_absolute_expression ();
12471 if (reg < 0 || reg >= 32)
12473 as_warn (_("Bad register number"));
12479 if (strncmp (input_line_pointer, "ra", 2) == 0)
12482 input_line_pointer += 2;
12484 else if (strncmp (input_line_pointer, "fp", 2) == 0)
12487 input_line_pointer += 2;
12489 else if (strncmp (input_line_pointer, "sp", 2) == 0)
12492 input_line_pointer += 2;
12494 else if (strncmp (input_line_pointer, "gp", 2) == 0)
12497 input_line_pointer += 2;
12499 else if (strncmp (input_line_pointer, "at", 2) == 0)
12502 input_line_pointer += 2;
12504 else if (strncmp (input_line_pointer, "kt0", 3) == 0)
12507 input_line_pointer += 3;
12509 else if (strncmp (input_line_pointer, "kt1", 3) == 0)
12512 input_line_pointer += 3;
12514 else if (strncmp (input_line_pointer, "zero", 4) == 0)
12517 input_line_pointer += 4;
12521 as_warn (_("Unrecognized register name"));
12523 while (ISALNUM(*input_line_pointer))
12524 input_line_pointer++;
12529 mips_frame_reg = reg != 0 ? reg : SP;
12530 mips_frame_reg_valid = 1;
12531 mips_cprestore_valid = 0;
12537 md_section_align (asection *seg, valueT addr)
12539 int align = bfd_get_section_alignment (stdoutput, seg);
12542 /* We don't need to align ELF sections to the full alignment.
12543 However, Irix 5 may prefer that we align them at least to a 16
12544 byte boundary. We don't bother to align the sections if we are
12545 targeted for an embedded system. */
12546 if (strcmp (TARGET_OS, "elf") == 0)
12552 return ((addr + (1 << align) - 1) & (-1 << align));
12555 /* Utility routine, called from above as well. If called while the
12556 input file is still being read, it's only an approximation. (For
12557 example, a symbol may later become defined which appeared to be
12558 undefined earlier.) */
12561 nopic_need_relax (symbolS *sym, int before_relaxing)
12566 if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0)
12568 const char *symname;
12571 /* Find out whether this symbol can be referenced off the $gp
12572 register. It can be if it is smaller than the -G size or if
12573 it is in the .sdata or .sbss section. Certain symbols can
12574 not be referenced off the $gp, although it appears as though
12576 symname = S_GET_NAME (sym);
12577 if (symname != (const char *) NULL
12578 && (strcmp (symname, "eprol") == 0
12579 || strcmp (symname, "etext") == 0
12580 || strcmp (symname, "_gp") == 0
12581 || strcmp (symname, "edata") == 0
12582 || strcmp (symname, "_fbss") == 0
12583 || strcmp (symname, "_fdata") == 0
12584 || strcmp (symname, "_ftext") == 0
12585 || strcmp (symname, "end") == 0
12586 || strcmp (symname, "_gp_disp") == 0))
12588 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
12590 #ifndef NO_ECOFF_DEBUGGING
12591 || (symbol_get_obj (sym)->ecoff_extern_size != 0
12592 && (symbol_get_obj (sym)->ecoff_extern_size
12593 <= g_switch_value))
12595 /* We must defer this decision until after the whole
12596 file has been read, since there might be a .extern
12597 after the first use of this symbol. */
12598 || (before_relaxing
12599 #ifndef NO_ECOFF_DEBUGGING
12600 && symbol_get_obj (sym)->ecoff_extern_size == 0
12602 && S_GET_VALUE (sym) == 0)
12603 || (S_GET_VALUE (sym) != 0
12604 && S_GET_VALUE (sym) <= g_switch_value)))
12608 const char *segname;
12610 segname = segment_name (S_GET_SEGMENT (sym));
12611 assert (strcmp (segname, ".lit8") != 0
12612 && strcmp (segname, ".lit4") != 0);
12613 change = (strcmp (segname, ".sdata") != 0
12614 && strcmp (segname, ".sbss") != 0
12615 && strncmp (segname, ".sdata.", 7) != 0
12616 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
12621 /* We are not optimizing for the $gp register. */
12626 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12629 pic_need_relax (symbolS *sym, asection *segtype)
12632 bfd_boolean linkonce;
12634 /* Handle the case of a symbol equated to another symbol. */
12635 while (symbol_equated_reloc_p (sym))
12639 /* It's possible to get a loop here in a badly written
12641 n = symbol_get_value_expression (sym)->X_add_symbol;
12647 symsec = S_GET_SEGMENT (sym);
12649 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12651 if (symsec != segtype && ! S_IS_LOCAL (sym))
12653 if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE)
12657 /* The GNU toolchain uses an extension for ELF: a section
12658 beginning with the magic string .gnu.linkonce is a linkonce
12660 if (strncmp (segment_name (symsec), ".gnu.linkonce",
12661 sizeof ".gnu.linkonce" - 1) == 0)
12665 /* This must duplicate the test in adjust_reloc_syms. */
12666 return (symsec != &bfd_und_section
12667 && symsec != &bfd_abs_section
12668 && ! bfd_is_com_section (symsec)
12671 /* A global or weak symbol is treated as external. */
12672 && (OUTPUT_FLAVOR != bfd_target_elf_flavour
12673 || (! S_IS_WEAK (sym)
12674 && (! S_IS_EXTERNAL (sym)
12675 || mips_pic == EMBEDDED_PIC)))
12681 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12682 extended opcode. SEC is the section the frag is in. */
12685 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
12688 register const struct mips16_immed_operand *op;
12690 int mintiny, maxtiny;
12694 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
12696 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
12699 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
12700 op = mips16_immed_operands;
12701 while (op->type != type)
12704 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
12709 if (type == '<' || type == '>' || type == '[' || type == ']')
12712 maxtiny = 1 << op->nbits;
12717 maxtiny = (1 << op->nbits) - 1;
12722 mintiny = - (1 << (op->nbits - 1));
12723 maxtiny = (1 << (op->nbits - 1)) - 1;
12726 sym_frag = symbol_get_frag (fragp->fr_symbol);
12727 val = S_GET_VALUE (fragp->fr_symbol);
12728 symsec = S_GET_SEGMENT (fragp->fr_symbol);
12734 /* We won't have the section when we are called from
12735 mips_relax_frag. However, we will always have been called
12736 from md_estimate_size_before_relax first. If this is a
12737 branch to a different section, we mark it as such. If SEC is
12738 NULL, and the frag is not marked, then it must be a branch to
12739 the same section. */
12742 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
12747 /* Must have been called from md_estimate_size_before_relax. */
12750 fragp->fr_subtype =
12751 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12753 /* FIXME: We should support this, and let the linker
12754 catch branches and loads that are out of range. */
12755 as_bad_where (fragp->fr_file, fragp->fr_line,
12756 _("unsupported PC relative reference to different section"));
12760 if (fragp != sym_frag && sym_frag->fr_address == 0)
12761 /* Assume non-extended on the first relaxation pass.
12762 The address we have calculated will be bogus if this is
12763 a forward branch to another frag, as the forward frag
12764 will have fr_address == 0. */
12768 /* In this case, we know for sure that the symbol fragment is in
12769 the same section. If the relax_marker of the symbol fragment
12770 differs from the relax_marker of this fragment, we have not
12771 yet adjusted the symbol fragment fr_address. We want to add
12772 in STRETCH in order to get a better estimate of the address.
12773 This particularly matters because of the shift bits. */
12775 && sym_frag->relax_marker != fragp->relax_marker)
12779 /* Adjust stretch for any alignment frag. Note that if have
12780 been expanding the earlier code, the symbol may be
12781 defined in what appears to be an earlier frag. FIXME:
12782 This doesn't handle the fr_subtype field, which specifies
12783 a maximum number of bytes to skip when doing an
12785 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
12787 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
12790 stretch = - ((- stretch)
12791 & ~ ((1 << (int) f->fr_offset) - 1));
12793 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
12802 addr = fragp->fr_address + fragp->fr_fix;
12804 /* The base address rules are complicated. The base address of
12805 a branch is the following instruction. The base address of a
12806 PC relative load or add is the instruction itself, but if it
12807 is in a delay slot (in which case it can not be extended) use
12808 the address of the instruction whose delay slot it is in. */
12809 if (type == 'p' || type == 'q')
12813 /* If we are currently assuming that this frag should be
12814 extended, then, the current address is two bytes
12816 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12819 /* Ignore the low bit in the target, since it will be set
12820 for a text label. */
12821 if ((val & 1) != 0)
12824 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
12826 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
12829 val -= addr & ~ ((1 << op->shift) - 1);
12831 /* Branch offsets have an implicit 0 in the lowest bit. */
12832 if (type == 'p' || type == 'q')
12835 /* If any of the shifted bits are set, we must use an extended
12836 opcode. If the address depends on the size of this
12837 instruction, this can lead to a loop, so we arrange to always
12838 use an extended opcode. We only check this when we are in
12839 the main relaxation loop, when SEC is NULL. */
12840 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
12842 fragp->fr_subtype =
12843 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12847 /* If we are about to mark a frag as extended because the value
12848 is precisely maxtiny + 1, then there is a chance of an
12849 infinite loop as in the following code:
12854 In this case when the la is extended, foo is 0x3fc bytes
12855 away, so the la can be shrunk, but then foo is 0x400 away, so
12856 the la must be extended. To avoid this loop, we mark the
12857 frag as extended if it was small, and is about to become
12858 extended with a value of maxtiny + 1. */
12859 if (val == ((maxtiny + 1) << op->shift)
12860 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
12863 fragp->fr_subtype =
12864 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12868 else if (symsec != absolute_section && sec != NULL)
12869 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
12871 if ((val & ((1 << op->shift) - 1)) != 0
12872 || val < (mintiny << op->shift)
12873 || val > (maxtiny << op->shift))
12879 /* Compute the length of a branch sequence, and adjust the
12880 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12881 worst-case length is computed, with UPDATE being used to indicate
12882 whether an unconditional (-1), branch-likely (+1) or regular (0)
12883 branch is to be computed. */
12885 relaxed_branch_length (fragS *fragp, asection *sec, int update)
12887 bfd_boolean toofar;
12891 && S_IS_DEFINED (fragp->fr_symbol)
12892 && sec == S_GET_SEGMENT (fragp->fr_symbol))
12897 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
12899 addr = fragp->fr_address + fragp->fr_fix + 4;
12903 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
12906 /* If the symbol is not defined or it's in a different segment,
12907 assume the user knows what's going on and emit a short
12913 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
12915 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype),
12916 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
12917 RELAX_BRANCH_LINK (fragp->fr_subtype),
12923 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
12926 if (mips_pic != NO_PIC)
12928 /* Additional space for PIC loading of target address. */
12930 if (mips_opts.isa == ISA_MIPS1)
12931 /* Additional space for $at-stabilizing nop. */
12935 /* If branch is conditional. */
12936 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
12943 /* Estimate the size of a frag before relaxing. Unless this is the
12944 mips16, we are not really relaxing here, and the final size is
12945 encoded in the subtype information. For the mips16, we have to
12946 decide whether we are using an extended opcode or not. */
12949 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
12953 if (RELAX_BRANCH_P (fragp->fr_subtype))
12956 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
12958 return fragp->fr_var;
12961 if (RELAX_MIPS16_P (fragp->fr_subtype))
12962 /* We don't want to modify the EXTENDED bit here; it might get us
12963 into infinite loops. We change it only in mips_relax_frag(). */
12964 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
12966 if (mips_pic == NO_PIC)
12967 change = nopic_need_relax (fragp->fr_symbol, 0);
12968 else if (mips_pic == SVR4_PIC)
12969 change = pic_need_relax (fragp->fr_symbol, segtype);
12975 fragp->fr_subtype |= RELAX_USE_SECOND;
12976 return -RELAX_FIRST (fragp->fr_subtype);
12979 return -RELAX_SECOND (fragp->fr_subtype);
12982 /* This is called to see whether a reloc against a defined symbol
12983 should be converted into a reloc against a section. Don't adjust
12984 MIPS16 jump relocations, so we don't have to worry about the format
12985 of the offset in the .o file. Don't adjust relocations against
12986 mips16 symbols, so that the linker can find them if it needs to set
12990 mips_fix_adjustable (fixS *fixp)
12992 if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
12995 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12996 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12999 if (fixp->fx_addsy == NULL)
13003 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
13004 && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
13005 && fixp->fx_subsy == NULL)
13012 /* Translate internal representation of relocation info to BFD target
13016 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
13018 static arelent *retval[4];
13020 bfd_reloc_code_real_type code;
13022 memset (retval, 0, sizeof(retval));
13023 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
13024 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
13025 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
13026 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
13028 if (mips_pic == EMBEDDED_PIC
13029 && SWITCH_TABLE (fixp))
13031 /* For a switch table entry we use a special reloc. The addend
13032 is actually the difference between the reloc address and the
13034 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
13035 if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour)
13036 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
13037 fixp->fx_r_type = BFD_RELOC_GPREL32;
13039 else if (fixp->fx_pcrel)
13041 bfd_vma pcrel_address;
13043 /* Set PCREL_ADDRESS to this relocation's "PC". The PC for high
13044 high-part relocs is the address of the low-part reloc. */
13045 if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
13047 assert (fixp->fx_next != NULL
13048 && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16);
13049 pcrel_address = (fixp->fx_next->fx_where
13050 + fixp->fx_next->fx_frag->fr_address);
13053 pcrel_address = reloc->address;
13055 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
13057 /* At this point, fx_addnumber is "symbol offset - pcrel_address".
13058 Relocations want only the symbol offset. */
13059 reloc->addend = fixp->fx_addnumber + pcrel_address;
13061 else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16
13062 || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
13064 /* We use a special addend for an internal RELLO or RELHI reloc. */
13065 if (symbol_section_p (fixp->fx_addsy))
13066 reloc->addend = pcrel_address - S_GET_VALUE (fixp->fx_subsy);
13068 reloc->addend = fixp->fx_addnumber + pcrel_address;
13072 if (OUTPUT_FLAVOR != bfd_target_aout_flavour)
13073 /* A gruesome hack which is a result of the gruesome gas reloc
13075 reloc->addend = pcrel_address;
13077 reloc->addend = -pcrel_address;
13081 reloc->addend = fixp->fx_addnumber;
13083 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
13084 entry to be used in the relocation's section offset. */
13085 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
13087 reloc->address = reloc->addend;
13091 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
13092 fixup_segment converted a non-PC relative reloc into a PC
13093 relative reloc. In such a case, we need to convert the reloc
13095 code = fixp->fx_r_type;
13096 if (fixp->fx_pcrel)
13101 code = BFD_RELOC_8_PCREL;
13104 code = BFD_RELOC_16_PCREL;
13107 code = BFD_RELOC_32_PCREL;
13110 code = BFD_RELOC_64_PCREL;
13112 case BFD_RELOC_8_PCREL:
13113 case BFD_RELOC_16_PCREL:
13114 case BFD_RELOC_32_PCREL:
13115 case BFD_RELOC_64_PCREL:
13116 case BFD_RELOC_16_PCREL_S2:
13117 case BFD_RELOC_PCREL_HI16_S:
13118 case BFD_RELOC_PCREL_LO16:
13121 as_bad_where (fixp->fx_file, fixp->fx_line,
13122 _("Cannot make %s relocation PC relative"),
13123 bfd_get_reloc_code_name (code));
13127 /* To support a PC relative reloc when generating embedded PIC code
13128 for ECOFF, we use a Cygnus extension. We check for that here to
13129 make sure that we don't let such a reloc escape normally. */
13130 if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
13131 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
13132 && code == BFD_RELOC_16_PCREL_S2
13133 && mips_pic != EMBEDDED_PIC)
13134 reloc->howto = NULL;
13136 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
13138 if (reloc->howto == NULL)
13140 as_bad_where (fixp->fx_file, fixp->fx_line,
13141 _("Can not represent %s relocation in this object file format"),
13142 bfd_get_reloc_code_name (code));
13149 /* Relax a machine dependent frag. This returns the amount by which
13150 the current size of the frag should change. */
13153 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
13155 if (RELAX_BRANCH_P (fragp->fr_subtype))
13157 offsetT old_var = fragp->fr_var;
13159 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
13161 return fragp->fr_var - old_var;
13164 if (! RELAX_MIPS16_P (fragp->fr_subtype))
13167 if (mips16_extended_frag (fragp, NULL, stretch))
13169 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13171 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
13176 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13178 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
13185 /* Convert a machine dependent frag. */
13188 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
13190 if (RELAX_BRANCH_P (fragp->fr_subtype))
13193 unsigned long insn;
13197 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
13199 if (target_big_endian)
13200 insn = bfd_getb32 (buf);
13202 insn = bfd_getl32 (buf);
13204 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
13206 /* We generate a fixup instead of applying it right now
13207 because, if there are linker relaxations, we're going to
13208 need the relocations. */
13209 exp.X_op = O_symbol;
13210 exp.X_add_symbol = fragp->fr_symbol;
13211 exp.X_add_number = fragp->fr_offset;
13213 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13215 BFD_RELOC_16_PCREL_S2);
13216 fixp->fx_file = fragp->fr_file;
13217 fixp->fx_line = fragp->fr_line;
13219 md_number_to_chars (buf, insn, 4);
13226 as_warn_where (fragp->fr_file, fragp->fr_line,
13227 _("relaxed out-of-range branch into a jump"));
13229 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
13232 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13234 /* Reverse the branch. */
13235 switch ((insn >> 28) & 0xf)
13238 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
13239 have the condition reversed by tweaking a single
13240 bit, and their opcodes all have 0x4???????. */
13241 assert ((insn & 0xf1000000) == 0x41000000);
13242 insn ^= 0x00010000;
13246 /* bltz 0x04000000 bgez 0x04010000
13247 bltzal 0x04100000 bgezal 0x04110000 */
13248 assert ((insn & 0xfc0e0000) == 0x04000000);
13249 insn ^= 0x00010000;
13253 /* beq 0x10000000 bne 0x14000000
13254 blez 0x18000000 bgtz 0x1c000000 */
13255 insn ^= 0x04000000;
13263 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13265 /* Clear the and-link bit. */
13266 assert ((insn & 0xfc1c0000) == 0x04100000);
13268 /* bltzal 0x04100000 bgezal 0x04110000
13269 bltzall 0x04120000 bgezall 0x04130000 */
13270 insn &= ~0x00100000;
13273 /* Branch over the branch (if the branch was likely) or the
13274 full jump (not likely case). Compute the offset from the
13275 current instruction to branch to. */
13276 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13280 /* How many bytes in instructions we've already emitted? */
13281 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
13282 /* How many bytes in instructions from here to the end? */
13283 i = fragp->fr_var - i;
13285 /* Convert to instruction count. */
13287 /* Branch counts from the next instruction. */
13290 /* Branch over the jump. */
13291 md_number_to_chars (buf, insn, 4);
13295 md_number_to_chars (buf, 0, 4);
13298 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13300 /* beql $0, $0, 2f */
13302 /* Compute the PC offset from the current instruction to
13303 the end of the variable frag. */
13304 /* How many bytes in instructions we've already emitted? */
13305 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
13306 /* How many bytes in instructions from here to the end? */
13307 i = fragp->fr_var - i;
13308 /* Convert to instruction count. */
13310 /* Don't decrement i, because we want to branch over the
13314 md_number_to_chars (buf, insn, 4);
13317 md_number_to_chars (buf, 0, 4);
13322 if (mips_pic == NO_PIC)
13325 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
13326 ? 0x0c000000 : 0x08000000);
13327 exp.X_op = O_symbol;
13328 exp.X_add_symbol = fragp->fr_symbol;
13329 exp.X_add_number = fragp->fr_offset;
13331 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13332 4, &exp, 0, BFD_RELOC_MIPS_JMP);
13333 fixp->fx_file = fragp->fr_file;
13334 fixp->fx_line = fragp->fr_line;
13336 md_number_to_chars (buf, insn, 4);
13341 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13342 insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000;
13343 exp.X_op = O_symbol;
13344 exp.X_add_symbol = fragp->fr_symbol;
13345 exp.X_add_number = fragp->fr_offset;
13347 if (fragp->fr_offset)
13349 exp.X_add_symbol = make_expr_symbol (&exp);
13350 exp.X_add_number = 0;
13353 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13354 4, &exp, 0, BFD_RELOC_MIPS_GOT16);
13355 fixp->fx_file = fragp->fr_file;
13356 fixp->fx_line = fragp->fr_line;
13358 md_number_to_chars (buf, insn, 4);
13361 if (mips_opts.isa == ISA_MIPS1)
13364 md_number_to_chars (buf, 0, 4);
13368 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13369 insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000;
13371 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13372 4, &exp, 0, BFD_RELOC_LO16);
13373 fixp->fx_file = fragp->fr_file;
13374 fixp->fx_line = fragp->fr_line;
13376 md_number_to_chars (buf, insn, 4);
13380 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13385 md_number_to_chars (buf, insn, 4);
13390 assert (buf == (bfd_byte *)fragp->fr_literal
13391 + fragp->fr_fix + fragp->fr_var);
13393 fragp->fr_fix += fragp->fr_var;
13398 if (RELAX_MIPS16_P (fragp->fr_subtype))
13401 register const struct mips16_immed_operand *op;
13402 bfd_boolean small, ext;
13405 unsigned long insn;
13406 bfd_boolean use_extend;
13407 unsigned short extend;
13409 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
13410 op = mips16_immed_operands;
13411 while (op->type != type)
13414 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13425 resolve_symbol_value (fragp->fr_symbol);
13426 val = S_GET_VALUE (fragp->fr_symbol);
13431 addr = fragp->fr_address + fragp->fr_fix;
13433 /* The rules for the base address of a PC relative reloc are
13434 complicated; see mips16_extended_frag. */
13435 if (type == 'p' || type == 'q')
13440 /* Ignore the low bit in the target, since it will be
13441 set for a text label. */
13442 if ((val & 1) != 0)
13445 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
13447 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
13450 addr &= ~ (addressT) ((1 << op->shift) - 1);
13453 /* Make sure the section winds up with the alignment we have
13456 record_alignment (asec, op->shift);
13460 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
13461 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
13462 as_warn_where (fragp->fr_file, fragp->fr_line,
13463 _("extended instruction in delay slot"));
13465 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
13467 if (target_big_endian)
13468 insn = bfd_getb16 (buf);
13470 insn = bfd_getl16 (buf);
13472 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
13473 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
13474 small, ext, &insn, &use_extend, &extend);
13478 md_number_to_chars (buf, 0xf000 | extend, 2);
13479 fragp->fr_fix += 2;
13483 md_number_to_chars (buf, insn, 2);
13484 fragp->fr_fix += 2;
13492 first = RELAX_FIRST (fragp->fr_subtype);
13493 second = RELAX_SECOND (fragp->fr_subtype);
13494 fixp = (fixS *) fragp->fr_opcode;
13496 /* Possibly emit a warning if we've chosen the longer option. */
13497 if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0)
13498 == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0))
13500 const char *msg = macro_warning (fragp->fr_subtype);
13502 as_warn_where (fragp->fr_file, fragp->fr_line, msg);
13505 /* Go through all the fixups for the first sequence. Disable them
13506 (by marking them as done) if we're going to use the second
13507 sequence instead. */
13509 && fixp->fx_frag == fragp
13510 && fixp->fx_where < fragp->fr_fix - second)
13512 if (fragp->fr_subtype & RELAX_USE_SECOND)
13514 fixp = fixp->fx_next;
13517 /* Go through the fixups for the second sequence. Disable them if
13518 we're going to use the first sequence, otherwise adjust their
13519 addresses to account for the relaxation. */
13520 while (fixp && fixp->fx_frag == fragp)
13522 if (fragp->fr_subtype & RELAX_USE_SECOND)
13523 fixp->fx_where -= first;
13526 fixp = fixp->fx_next;
13529 /* Now modify the frag contents. */
13530 if (fragp->fr_subtype & RELAX_USE_SECOND)
13534 start = fragp->fr_literal + fragp->fr_fix - first - second;
13535 memmove (start, start + first, second);
13536 fragp->fr_fix -= first;
13539 fragp->fr_fix -= second;
13545 /* This function is called after the relocs have been generated.
13546 We've been storing mips16 text labels as odd. Here we convert them
13547 back to even for the convenience of the debugger. */
13550 mips_frob_file_after_relocs (void)
13553 unsigned int count, i;
13555 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
13558 syms = bfd_get_outsymbols (stdoutput);
13559 count = bfd_get_symcount (stdoutput);
13560 for (i = 0; i < count; i++, syms++)
13562 if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16
13563 && ((*syms)->value & 1) != 0)
13565 (*syms)->value &= ~1;
13566 /* If the symbol has an odd size, it was probably computed
13567 incorrectly, so adjust that as well. */
13568 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
13569 ++elf_symbol (*syms)->internal_elf_sym.st_size;
13576 /* This function is called whenever a label is defined. It is used
13577 when handling branch delays; if a branch has a label, we assume we
13578 can not move it. */
13581 mips_define_label (symbolS *sym)
13583 struct insn_label_list *l;
13585 if (free_insn_labels == NULL)
13586 l = (struct insn_label_list *) xmalloc (sizeof *l);
13589 l = free_insn_labels;
13590 free_insn_labels = l->next;
13594 l->next = insn_labels;
13598 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13600 /* Some special processing for a MIPS ELF file. */
13603 mips_elf_final_processing (void)
13605 /* Write out the register information. */
13606 if (mips_abi != N64_ABI)
13610 s.ri_gprmask = mips_gprmask;
13611 s.ri_cprmask[0] = mips_cprmask[0];
13612 s.ri_cprmask[1] = mips_cprmask[1];
13613 s.ri_cprmask[2] = mips_cprmask[2];
13614 s.ri_cprmask[3] = mips_cprmask[3];
13615 /* The gp_value field is set by the MIPS ELF backend. */
13617 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
13618 ((Elf32_External_RegInfo *)
13619 mips_regmask_frag));
13623 Elf64_Internal_RegInfo s;
13625 s.ri_gprmask = mips_gprmask;
13627 s.ri_cprmask[0] = mips_cprmask[0];
13628 s.ri_cprmask[1] = mips_cprmask[1];
13629 s.ri_cprmask[2] = mips_cprmask[2];
13630 s.ri_cprmask[3] = mips_cprmask[3];
13631 /* The gp_value field is set by the MIPS ELF backend. */
13633 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
13634 ((Elf64_External_RegInfo *)
13635 mips_regmask_frag));
13638 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13639 sort of BFD interface for this. */
13640 if (mips_any_noreorder)
13641 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
13642 if (mips_pic != NO_PIC)
13644 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
13645 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
13648 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
13650 /* Set MIPS ELF flags for ASEs. */
13651 if (file_ase_mips16)
13652 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
13653 #if 0 /* XXX FIXME */
13654 if (file_ase_mips3d)
13655 elf_elfheader (stdoutput)->e_flags |= ???;
13658 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
13660 /* Set the MIPS ELF ABI flags. */
13661 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
13662 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
13663 else if (mips_abi == O64_ABI)
13664 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
13665 else if (mips_abi == EABI_ABI)
13667 if (!file_mips_gp32)
13668 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
13670 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
13672 else if (mips_abi == N32_ABI)
13673 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
13675 /* Nothing to do for N64_ABI. */
13677 if (mips_32bitmode)
13678 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
13681 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13683 typedef struct proc {
13685 unsigned long reg_mask;
13686 unsigned long reg_offset;
13687 unsigned long fpreg_mask;
13688 unsigned long fpreg_offset;
13689 unsigned long frame_offset;
13690 unsigned long frame_reg;
13691 unsigned long pc_reg;
13694 static procS cur_proc;
13695 static procS *cur_proc_ptr;
13696 static int numprocs;
13698 /* Fill in an rs_align_code fragment. */
13701 mips_handle_align (fragS *fragp)
13703 if (fragp->fr_type != rs_align_code)
13706 if (mips_opts.mips16)
13708 static const unsigned char be_nop[] = { 0x65, 0x00 };
13709 static const unsigned char le_nop[] = { 0x00, 0x65 };
13714 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
13715 p = fragp->fr_literal + fragp->fr_fix;
13723 memcpy (p, (target_big_endian ? be_nop : le_nop), 2);
13727 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13731 md_obj_begin (void)
13738 /* check for premature end, nesting errors, etc */
13740 as_warn (_("missing .end at end of assembly"));
13749 if (*input_line_pointer == '-')
13751 ++input_line_pointer;
13754 if (!ISDIGIT (*input_line_pointer))
13755 as_bad (_("expected simple number"));
13756 if (input_line_pointer[0] == '0')
13758 if (input_line_pointer[1] == 'x')
13760 input_line_pointer += 2;
13761 while (ISXDIGIT (*input_line_pointer))
13764 val |= hex_value (*input_line_pointer++);
13766 return negative ? -val : val;
13770 ++input_line_pointer;
13771 while (ISDIGIT (*input_line_pointer))
13774 val |= *input_line_pointer++ - '0';
13776 return negative ? -val : val;
13779 if (!ISDIGIT (*input_line_pointer))
13781 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13782 *input_line_pointer, *input_line_pointer);
13783 as_warn (_("invalid number"));
13786 while (ISDIGIT (*input_line_pointer))
13789 val += *input_line_pointer++ - '0';
13791 return negative ? -val : val;
13794 /* The .file directive; just like the usual .file directive, but there
13795 is an initial number which is the ECOFF file index. In the non-ECOFF
13796 case .file implies DWARF-2. */
13799 s_mips_file (int x ATTRIBUTE_UNUSED)
13801 static int first_file_directive = 0;
13803 if (ECOFF_DEBUGGING)
13812 filename = dwarf2_directive_file (0);
13814 /* Versions of GCC up to 3.1 start files with a ".file"
13815 directive even for stabs output. Make sure that this
13816 ".file" is handled. Note that you need a version of GCC
13817 after 3.1 in order to support DWARF-2 on MIPS. */
13818 if (filename != NULL && ! first_file_directive)
13820 (void) new_logical_line (filename, -1);
13821 s_app_file_string (filename);
13823 first_file_directive = 1;
13827 /* The .loc directive, implying DWARF-2. */
13830 s_mips_loc (int x ATTRIBUTE_UNUSED)
13832 if (!ECOFF_DEBUGGING)
13833 dwarf2_directive_loc (0);
13836 /* The .end directive. */
13839 s_mips_end (int x ATTRIBUTE_UNUSED)
13843 /* Following functions need their own .frame and .cprestore directives. */
13844 mips_frame_reg_valid = 0;
13845 mips_cprestore_valid = 0;
13847 if (!is_end_of_line[(unsigned char) *input_line_pointer])
13850 demand_empty_rest_of_line ();
13855 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
13856 as_warn (_(".end not in text section"));
13860 as_warn (_(".end directive without a preceding .ent directive."));
13861 demand_empty_rest_of_line ();
13867 assert (S_GET_NAME (p));
13868 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym)))
13869 as_warn (_(".end symbol does not match .ent symbol."));
13871 if (debug_type == DEBUG_STABS)
13872 stabs_generate_asm_endfunc (S_GET_NAME (p),
13876 as_warn (_(".end directive missing or unknown symbol"));
13879 /* Generate a .pdr section. */
13880 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING
13883 segT saved_seg = now_seg;
13884 subsegT saved_subseg = now_subseg;
13889 dot = frag_now_fix ();
13891 #ifdef md_flush_pending_output
13892 md_flush_pending_output ();
13896 subseg_set (pdr_seg, 0);
13898 /* Write the symbol. */
13899 exp.X_op = O_symbol;
13900 exp.X_add_symbol = p;
13901 exp.X_add_number = 0;
13902 emit_expr (&exp, 4);
13904 fragp = frag_more (7 * 4);
13906 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
13907 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
13908 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
13909 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
13910 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
13911 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
13912 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
13914 subseg_set (saved_seg, saved_subseg);
13916 #endif /* OBJ_ELF */
13918 cur_proc_ptr = NULL;
13921 /* The .aent and .ent directives. */
13924 s_mips_ent (int aent)
13928 symbolP = get_symbol ();
13929 if (*input_line_pointer == ',')
13930 ++input_line_pointer;
13931 SKIP_WHITESPACE ();
13932 if (ISDIGIT (*input_line_pointer)
13933 || *input_line_pointer == '-')
13936 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
13937 as_warn (_(".ent or .aent not in text section."));
13939 if (!aent && cur_proc_ptr)
13940 as_warn (_("missing .end"));
13944 /* This function needs its own .frame and .cprestore directives. */
13945 mips_frame_reg_valid = 0;
13946 mips_cprestore_valid = 0;
13948 cur_proc_ptr = &cur_proc;
13949 memset (cur_proc_ptr, '\0', sizeof (procS));
13951 cur_proc_ptr->isym = symbolP;
13953 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
13957 if (debug_type == DEBUG_STABS)
13958 stabs_generate_asm_func (S_GET_NAME (symbolP),
13959 S_GET_NAME (symbolP));
13962 demand_empty_rest_of_line ();
13965 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13966 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13967 s_mips_frame is used so that we can set the PDR information correctly.
13968 We can't use the ecoff routines because they make reference to the ecoff
13969 symbol table (in the mdebug section). */
13972 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
13975 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
13979 if (cur_proc_ptr == (procS *) NULL)
13981 as_warn (_(".frame outside of .ent"));
13982 demand_empty_rest_of_line ();
13986 cur_proc_ptr->frame_reg = tc_get_register (1);
13988 SKIP_WHITESPACE ();
13989 if (*input_line_pointer++ != ','
13990 || get_absolute_expression_and_terminator (&val) != ',')
13992 as_warn (_("Bad .frame directive"));
13993 --input_line_pointer;
13994 demand_empty_rest_of_line ();
13998 cur_proc_ptr->frame_offset = val;
13999 cur_proc_ptr->pc_reg = tc_get_register (0);
14001 demand_empty_rest_of_line ();
14004 #endif /* OBJ_ELF */
14008 /* The .fmask and .mask directives. If the mdebug section is present
14009 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
14010 embedded targets, s_mips_mask is used so that we can set the PDR
14011 information correctly. We can't use the ecoff routines because they
14012 make reference to the ecoff symbol table (in the mdebug section). */
14015 s_mips_mask (int reg_type)
14018 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
14022 if (cur_proc_ptr == (procS *) NULL)
14024 as_warn (_(".mask/.fmask outside of .ent"));
14025 demand_empty_rest_of_line ();
14029 if (get_absolute_expression_and_terminator (&mask) != ',')
14031 as_warn (_("Bad .mask/.fmask directive"));
14032 --input_line_pointer;
14033 demand_empty_rest_of_line ();
14037 off = get_absolute_expression ();
14039 if (reg_type == 'F')
14041 cur_proc_ptr->fpreg_mask = mask;
14042 cur_proc_ptr->fpreg_offset = off;
14046 cur_proc_ptr->reg_mask = mask;
14047 cur_proc_ptr->reg_offset = off;
14050 demand_empty_rest_of_line ();
14053 #endif /* OBJ_ELF */
14054 s_ignore (reg_type);
14057 /* The .loc directive. */
14067 assert (now_seg == text_section);
14069 lineno = get_number ();
14070 addroff = frag_now_fix ();
14072 symbolP = symbol_new ("", N_SLINE, addroff, frag_now);
14073 S_SET_TYPE (symbolP, N_SLINE);
14074 S_SET_OTHER (symbolP, 0);
14075 S_SET_DESC (symbolP, lineno);
14076 symbolP->sy_segment = now_seg;
14080 /* A table describing all the processors gas knows about. Names are
14081 matched in the order listed.
14083 To ease comparison, please keep this table in the same order as
14084 gcc's mips_cpu_info_table[]. */
14085 static const struct mips_cpu_info mips_cpu_info_table[] =
14087 /* Entries for generic ISAs */
14088 { "mips1", 1, ISA_MIPS1, CPU_R3000 },
14089 { "mips2", 1, ISA_MIPS2, CPU_R6000 },
14090 { "mips3", 1, ISA_MIPS3, CPU_R4000 },
14091 { "mips4", 1, ISA_MIPS4, CPU_R8000 },
14092 { "mips5", 1, ISA_MIPS5, CPU_MIPS5 },
14093 { "mips32", 1, ISA_MIPS32, CPU_MIPS32 },
14094 { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 },
14095 { "mips64", 1, ISA_MIPS64, CPU_MIPS64 },
14096 { "mips64r2", 1, ISA_MIPS64R2, CPU_MIPS64R2 },
14099 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
14100 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
14101 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
14104 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
14107 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
14108 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
14109 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
14110 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
14111 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
14112 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
14113 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
14114 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
14115 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
14116 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
14117 { "orion", 0, ISA_MIPS3, CPU_R4600 },
14118 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
14121 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
14122 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
14123 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
14124 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
14125 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
14126 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
14127 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
14128 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
14129 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
14130 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
14131 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
14132 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
14133 { "rm9000", 0, ISA_MIPS4, CPU_RM7000 },
14136 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
14137 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
14138 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
14141 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
14142 { "20kc", 0, ISA_MIPS64, CPU_MIPS64 },
14144 /* Broadcom SB-1 CPU core */
14145 { "sb1", 0, ISA_MIPS64, CPU_SB1 },
14152 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14153 with a final "000" replaced by "k". Ignore case.
14155 Note: this function is shared between GCC and GAS. */
14158 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
14160 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
14161 given++, canonical++;
14163 return ((*given == 0 && *canonical == 0)
14164 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
14168 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14169 CPU name. We've traditionally allowed a lot of variation here.
14171 Note: this function is shared between GCC and GAS. */
14174 mips_matching_cpu_name_p (const char *canonical, const char *given)
14176 /* First see if the name matches exactly, or with a final "000"
14177 turned into "k". */
14178 if (mips_strict_matching_cpu_name_p (canonical, given))
14181 /* If not, try comparing based on numerical designation alone.
14182 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14183 if (TOLOWER (*given) == 'r')
14185 if (!ISDIGIT (*given))
14188 /* Skip over some well-known prefixes in the canonical name,
14189 hoping to find a number there too. */
14190 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
14192 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
14194 else if (TOLOWER (canonical[0]) == 'r')
14197 return mips_strict_matching_cpu_name_p (canonical, given);
14201 /* Parse an option that takes the name of a processor as its argument.
14202 OPTION is the name of the option and CPU_STRING is the argument.
14203 Return the corresponding processor enumeration if the CPU_STRING is
14204 recognized, otherwise report an error and return null.
14206 A similar function exists in GCC. */
14208 static const struct mips_cpu_info *
14209 mips_parse_cpu (const char *option, const char *cpu_string)
14211 const struct mips_cpu_info *p;
14213 /* 'from-abi' selects the most compatible architecture for the given
14214 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14215 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14216 version. Look first at the -mgp options, if given, otherwise base
14217 the choice on MIPS_DEFAULT_64BIT.
14219 Treat NO_ABI like the EABIs. One reason to do this is that the
14220 plain 'mips' and 'mips64' configs have 'from-abi' as their default
14221 architecture. This code picks MIPS I for 'mips' and MIPS III for
14222 'mips64', just as we did in the days before 'from-abi'. */
14223 if (strcasecmp (cpu_string, "from-abi") == 0)
14225 if (ABI_NEEDS_32BIT_REGS (mips_abi))
14226 return mips_cpu_info_from_isa (ISA_MIPS1);
14228 if (ABI_NEEDS_64BIT_REGS (mips_abi))
14229 return mips_cpu_info_from_isa (ISA_MIPS3);
14231 if (file_mips_gp32 >= 0)
14232 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
14234 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
14239 /* 'default' has traditionally been a no-op. Probably not very useful. */
14240 if (strcasecmp (cpu_string, "default") == 0)
14243 for (p = mips_cpu_info_table; p->name != 0; p++)
14244 if (mips_matching_cpu_name_p (p->name, cpu_string))
14247 as_bad ("Bad value (%s) for %s", cpu_string, option);
14251 /* Return the canonical processor information for ISA (a member of the
14252 ISA_MIPS* enumeration). */
14254 static const struct mips_cpu_info *
14255 mips_cpu_info_from_isa (int isa)
14259 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14260 if (mips_cpu_info_table[i].is_isa
14261 && isa == mips_cpu_info_table[i].isa)
14262 return (&mips_cpu_info_table[i]);
14267 static const struct mips_cpu_info *
14268 mips_cpu_info_from_arch (int arch)
14272 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14273 if (arch == mips_cpu_info_table[i].cpu)
14274 return (&mips_cpu_info_table[i]);
14280 show (FILE *stream, const char *string, int *col_p, int *first_p)
14284 fprintf (stream, "%24s", "");
14289 fprintf (stream, ", ");
14293 if (*col_p + strlen (string) > 72)
14295 fprintf (stream, "\n%24s", "");
14299 fprintf (stream, "%s", string);
14300 *col_p += strlen (string);
14306 md_show_usage (FILE *stream)
14311 fprintf (stream, _("\
14313 -membedded-pic generate embedded position independent code\n\
14314 -EB generate big endian output\n\
14315 -EL generate little endian output\n\
14316 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14317 -G NUM allow referencing objects up to NUM bytes\n\
14318 implicitly with the gp register [default 8]\n"));
14319 fprintf (stream, _("\
14320 -mips1 generate MIPS ISA I instructions\n\
14321 -mips2 generate MIPS ISA II instructions\n\
14322 -mips3 generate MIPS ISA III instructions\n\
14323 -mips4 generate MIPS ISA IV instructions\n\
14324 -mips5 generate MIPS ISA V instructions\n\
14325 -mips32 generate MIPS32 ISA instructions\n\
14326 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14327 -mips64 generate MIPS64 ISA instructions\n\
14328 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
14329 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14333 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14334 show (stream, mips_cpu_info_table[i].name, &column, &first);
14335 show (stream, "from-abi", &column, &first);
14336 fputc ('\n', stream);
14338 fprintf (stream, _("\
14339 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14340 -no-mCPU don't generate code specific to CPU.\n\
14341 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14345 show (stream, "3900", &column, &first);
14346 show (stream, "4010", &column, &first);
14347 show (stream, "4100", &column, &first);
14348 show (stream, "4650", &column, &first);
14349 fputc ('\n', stream);
14351 fprintf (stream, _("\
14352 -mips16 generate mips16 instructions\n\
14353 -no-mips16 do not generate mips16 instructions\n"));
14354 fprintf (stream, _("\
14355 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14356 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14357 -O0 remove unneeded NOPs, do not swap branches\n\
14358 -O remove unneeded NOPs and swap branches\n\
14359 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14360 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14361 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14363 fprintf (stream, _("\
14364 -KPIC, -call_shared generate SVR4 position independent code\n\
14365 -non_shared do not generate position independent code\n\
14366 -xgot assume a 32 bit GOT\n\
14367 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14368 -mabi=ABI create ABI conformant object file for:\n"));
14372 show (stream, "32", &column, &first);
14373 show (stream, "o64", &column, &first);
14374 show (stream, "n32", &column, &first);
14375 show (stream, "64", &column, &first);
14376 show (stream, "eabi", &column, &first);
14378 fputc ('\n', stream);
14380 fprintf (stream, _("\
14381 -32 create o32 ABI object file (default)\n\
14382 -n32 create n32 ABI object file\n\
14383 -64 create 64 ABI object file\n"));
14388 mips_dwarf2_format (void)
14390 if (mips_abi == N64_ABI)
14393 return dwarf2_format_64bit_irix;
14395 return dwarf2_format_64bit;
14399 return dwarf2_format_32bit;