1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
29 #include "safe-ctype.h"
31 #include "opcode/mips.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
37 #define DBG(x) printf x
43 /* Clean up namespace so we can include obj-elf.h too. */
44 static int mips_output_flavor (void);
45 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
46 #undef OBJ_PROCESS_STAB
53 #undef obj_frob_file_after_relocs
54 #undef obj_frob_symbol
56 #undef obj_sec_sym_ok_for_reloc
57 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
60 /* Fix any of them that we actually care about. */
62 #define OUTPUT_FLAVOR mips_output_flavor()
69 #ifndef ECOFF_DEBUGGING
70 #define NO_ECOFF_DEBUGGING
71 #define ECOFF_DEBUGGING 0
74 int mips_flag_mdebug = -1;
76 /* Control generation of .pdr sections. Off by default on IRIX: the native
77 linker doesn't know about and discards them, but relocations against them
78 remain, leading to rld crashes. */
80 int mips_flag_pdr = FALSE;
82 int mips_flag_pdr = TRUE;
87 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
88 static char *mips_regmask_frag;
94 #define PIC_CALL_REG 25
102 #define ILLEGAL_REG (32)
104 #define AT mips_opts.at
106 /* Allow override of standard little-endian ECOFF format. */
108 #ifndef ECOFF_LITTLE_FORMAT
109 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
112 extern int target_big_endian;
114 /* The name of the readonly data section. */
115 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
117 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
119 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
123 /* Information about an instruction, including its format, operands
127 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
128 const struct mips_opcode *insn_mo;
130 /* True if this is a mips16 instruction and if we want the extended
132 bfd_boolean use_extend;
134 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
135 unsigned short extend;
137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
138 a copy of INSN_MO->match with the operands filled in. */
139 unsigned long insn_opcode;
141 /* The frag that contains the instruction. */
144 /* The offset into FRAG of the first instruction byte. */
147 /* The relocs associated with the instruction, if any. */
150 /* True if this entry cannot be moved from its current position. */
151 unsigned int fixed_p : 1;
153 /* True if this instruction occurred in a .set noreorder block. */
154 unsigned int noreorder_p : 1;
156 /* True for mips16 instructions that jump to an absolute address. */
157 unsigned int mips16_absolute_jump_p : 1;
160 /* The ABI to use. */
171 /* MIPS ABI we are using for this output file. */
172 static enum mips_abi_level mips_abi = NO_ABI;
174 /* Whether or not we have code that can call pic code. */
175 int mips_abicalls = FALSE;
177 /* Whether or not we have code which can be put into a shared
179 static bfd_boolean mips_in_shared = TRUE;
181 /* This is the set of options which may be modified by the .set
182 pseudo-op. We use a struct so that .set push and .set pop are more
185 struct mips_set_options
187 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
188 if it has not been initialized. Changed by `.set mipsN', and the
189 -mipsN command line option, and the default CPU. */
191 /* Enabled Application Specific Extensions (ASEs). These are set to -1
192 if they have not been initialized. Changed by `.set <asename>', by
193 command line options, and based on the default architecture. */
200 /* Whether we are assembling for the mips16 processor. 0 if we are
201 not, 1 if we are, and -1 if the value has not been initialized.
202 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
203 -nomips16 command line options, and the default CPU. */
205 /* Non-zero if we should not reorder instructions. Changed by `.set
206 reorder' and `.set noreorder'. */
208 /* Non-zero if we should not permit the register designated "assembler
209 temporary" to be used in instructions. The value is the register
210 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
211 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
213 /* Non-zero if we should warn when a macro instruction expands into
214 more than one machine instruction. Changed by `.set nomacro' and
216 int warn_about_macros;
217 /* Non-zero if we should not move instructions. Changed by `.set
218 move', `.set volatile', `.set nomove', and `.set novolatile'. */
220 /* Non-zero if we should not optimize branches by moving the target
221 of the branch into the delay slot. Actually, we don't perform
222 this optimization anyhow. Changed by `.set bopt' and `.set
225 /* Non-zero if we should not autoextend mips16 instructions.
226 Changed by `.set autoextend' and `.set noautoextend'. */
228 /* Restrict general purpose registers and floating point registers
229 to 32 bit. This is initially determined when -mgp32 or -mfp32
230 is passed but can changed if the assembler code uses .set mipsN. */
233 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
234 command line option, and the default CPU. */
236 /* True if ".set sym32" is in effect. */
238 /* True if floating-point operations are not allowed. Changed by .set
239 softfloat or .set hardfloat, by command line options -msoft-float or
240 -mhard-float. The default is false. */
241 bfd_boolean soft_float;
243 /* True if only single-precision floating-point operations are allowed.
244 Changed by .set singlefloat or .set doublefloat, command-line options
245 -msingle-float or -mdouble-float. The default is false. */
246 bfd_boolean single_float;
249 /* This is the struct we use to hold the current set of options. Note
250 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
251 -1 to indicate that they have not been initialized. */
253 /* True if -mgp32 was passed. */
254 static int file_mips_gp32 = -1;
256 /* True if -mfp32 was passed. */
257 static int file_mips_fp32 = -1;
259 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
260 static int file_mips_soft_float = 0;
262 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
263 static int file_mips_single_float = 0;
265 static struct mips_set_options mips_opts =
267 /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
268 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
269 /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG,
270 /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
271 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN,
272 /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE
275 /* These variables are filled in with the masks of registers used.
276 The object format code reads them and puts them in the appropriate
278 unsigned long mips_gprmask;
279 unsigned long mips_cprmask[4];
281 /* MIPS ISA we are using for this output file. */
282 static int file_mips_isa = ISA_UNKNOWN;
284 /* True if -mips16 was passed or implied by arguments passed on the
285 command line (e.g., by -march). */
286 static int file_ase_mips16;
288 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
289 || mips_opts.isa == ISA_MIPS32R2 \
290 || mips_opts.isa == ISA_MIPS64 \
291 || mips_opts.isa == ISA_MIPS64R2)
293 /* True if -mips3d was passed or implied by arguments passed on the
294 command line (e.g., by -march). */
295 static int file_ase_mips3d;
297 /* True if -mdmx was passed or implied by arguments passed on the
298 command line (e.g., by -march). */
299 static int file_ase_mdmx;
301 /* True if -msmartmips was passed or implied by arguments passed on the
302 command line (e.g., by -march). */
303 static int file_ase_smartmips;
305 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
306 || mips_opts.isa == ISA_MIPS32R2)
308 /* True if -mdsp was passed or implied by arguments passed on the
309 command line (e.g., by -march). */
310 static int file_ase_dsp;
312 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
313 || mips_opts.isa == ISA_MIPS64R2)
315 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
317 /* True if -mdspr2 was passed or implied by arguments passed on the
318 command line (e.g., by -march). */
319 static int file_ase_dspr2;
321 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
322 || mips_opts.isa == ISA_MIPS64R2)
324 /* True if -mmt was passed or implied by arguments passed on the
325 command line (e.g., by -march). */
326 static int file_ase_mt;
328 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
329 || mips_opts.isa == ISA_MIPS64R2)
331 /* The argument of the -march= flag. The architecture we are assembling. */
332 static int file_mips_arch = CPU_UNKNOWN;
333 static const char *mips_arch_string;
335 /* The argument of the -mtune= flag. The architecture for which we
337 static int mips_tune = CPU_UNKNOWN;
338 static const char *mips_tune_string;
340 /* True when generating 32-bit code for a 64-bit processor. */
341 static int mips_32bitmode = 0;
343 /* True if the given ABI requires 32-bit registers. */
344 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
346 /* Likewise 64-bit registers. */
347 #define ABI_NEEDS_64BIT_REGS(ABI) \
349 || (ABI) == N64_ABI \
352 /* Return true if ISA supports 64 bit wide gp registers. */
353 #define ISA_HAS_64BIT_REGS(ISA) \
354 ((ISA) == ISA_MIPS3 \
355 || (ISA) == ISA_MIPS4 \
356 || (ISA) == ISA_MIPS5 \
357 || (ISA) == ISA_MIPS64 \
358 || (ISA) == ISA_MIPS64R2)
360 /* Return true if ISA supports 64 bit wide float registers. */
361 #define ISA_HAS_64BIT_FPRS(ISA) \
362 ((ISA) == ISA_MIPS3 \
363 || (ISA) == ISA_MIPS4 \
364 || (ISA) == ISA_MIPS5 \
365 || (ISA) == ISA_MIPS32R2 \
366 || (ISA) == ISA_MIPS64 \
367 || (ISA) == ISA_MIPS64R2)
369 /* Return true if ISA supports 64-bit right rotate (dror et al.)
371 #define ISA_HAS_DROR(ISA) \
372 ((ISA) == ISA_MIPS64R2)
374 /* Return true if ISA supports 32-bit right rotate (ror et al.)
376 #define ISA_HAS_ROR(ISA) \
377 ((ISA) == ISA_MIPS32R2 \
378 || (ISA) == ISA_MIPS64R2 \
379 || mips_opts.ase_smartmips)
381 /* Return true if ISA supports single-precision floats in odd registers. */
382 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
383 ((ISA) == ISA_MIPS32 \
384 || (ISA) == ISA_MIPS32R2 \
385 || (ISA) == ISA_MIPS64 \
386 || (ISA) == ISA_MIPS64R2)
388 /* Return true if ISA supports move to/from high part of a 64-bit
389 floating-point register. */
390 #define ISA_HAS_MXHC1(ISA) \
391 ((ISA) == ISA_MIPS32R2 \
392 || (ISA) == ISA_MIPS64R2)
394 #define HAVE_32BIT_GPRS \
395 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
397 #define HAVE_32BIT_FPRS \
398 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
400 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
401 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
403 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
405 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
407 /* True if relocations are stored in-place. */
408 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
410 /* The ABI-derived address size. */
411 #define HAVE_64BIT_ADDRESSES \
412 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
413 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
415 /* The size of symbolic constants (i.e., expressions of the form
416 "SYMBOL" or "SYMBOL + OFFSET"). */
417 #define HAVE_32BIT_SYMBOLS \
418 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
419 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
421 /* Addresses are loaded in different ways, depending on the address size
422 in use. The n32 ABI Documentation also mandates the use of additions
423 with overflow checking, but existing implementations don't follow it. */
424 #define ADDRESS_ADD_INSN \
425 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
427 #define ADDRESS_ADDI_INSN \
428 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
430 #define ADDRESS_LOAD_INSN \
431 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
433 #define ADDRESS_STORE_INSN \
434 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
436 /* Return true if the given CPU supports the MIPS16 ASE. */
437 #define CPU_HAS_MIPS16(cpu) \
438 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
439 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
441 /* True if CPU has a dror instruction. */
442 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
444 /* True if CPU has a ror instruction. */
445 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
447 /* True if CPU has seq/sne and seqi/snei instructions. */
448 #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON)
450 /* True if CPU does not implement the all the coprocessor insns. For these
451 CPUs only those COP insns are accepted that are explicitly marked to be
452 available on the CPU. ISA membership for COP insns is ignored. */
453 #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON)
455 /* True if mflo and mfhi can be immediately followed by instructions
456 which write to the HI and LO registers.
458 According to MIPS specifications, MIPS ISAs I, II, and III need
459 (at least) two instructions between the reads of HI/LO and
460 instructions which write them, and later ISAs do not. Contradicting
461 the MIPS specifications, some MIPS IV processor user manuals (e.g.
462 the UM for the NEC Vr5000) document needing the instructions between
463 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
464 MIPS64 and later ISAs to have the interlocks, plus any specific
465 earlier-ISA CPUs for which CPU documentation declares that the
466 instructions are really interlocked. */
467 #define hilo_interlocks \
468 (mips_opts.isa == ISA_MIPS32 \
469 || mips_opts.isa == ISA_MIPS32R2 \
470 || mips_opts.isa == ISA_MIPS64 \
471 || mips_opts.isa == ISA_MIPS64R2 \
472 || mips_opts.arch == CPU_R4010 \
473 || mips_opts.arch == CPU_R10000 \
474 || mips_opts.arch == CPU_R12000 \
475 || mips_opts.arch == CPU_R14000 \
476 || mips_opts.arch == CPU_R16000 \
477 || mips_opts.arch == CPU_RM7000 \
478 || mips_opts.arch == CPU_VR5500 \
481 /* Whether the processor uses hardware interlocks to protect reads
482 from the GPRs after they are loaded from memory, and thus does not
483 require nops to be inserted. This applies to instructions marked
484 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
486 #define gpr_interlocks \
487 (mips_opts.isa != ISA_MIPS1 \
488 || mips_opts.arch == CPU_R3900)
490 /* Whether the processor uses hardware interlocks to avoid delays
491 required by coprocessor instructions, and thus does not require
492 nops to be inserted. This applies to instructions marked
493 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
494 between instructions marked INSN_WRITE_COND_CODE and ones marked
495 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
496 levels I, II, and III. */
497 /* Itbl support may require additional care here. */
498 #define cop_interlocks \
499 ((mips_opts.isa != ISA_MIPS1 \
500 && mips_opts.isa != ISA_MIPS2 \
501 && mips_opts.isa != ISA_MIPS3) \
502 || mips_opts.arch == CPU_R4300 \
505 /* Whether the processor uses hardware interlocks to protect reads
506 from coprocessor registers after they are loaded from memory, and
507 thus does not require nops to be inserted. This applies to
508 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
509 requires at MIPS ISA level I. */
510 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
512 /* Is this a mfhi or mflo instruction? */
513 #define MF_HILO_INSN(PINFO) \
514 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
516 /* Returns true for a (non floating-point) coprocessor instruction. Reading
517 or writing the condition code is only possible on the coprocessors and
518 these insns are not marked with INSN_COP. Thus for these insns use the
519 condition-code flags. */
520 #define COP_INSN(PINFO) \
521 (PINFO != INSN_MACRO \
522 && ((PINFO) & (FP_S | FP_D)) == 0 \
523 && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
525 /* MIPS PIC level. */
527 enum mips_pic_level mips_pic;
529 /* 1 if we should generate 32 bit offsets from the $gp register in
530 SVR4_PIC mode. Currently has no meaning in other modes. */
531 static int mips_big_got = 0;
533 /* 1 if trap instructions should used for overflow rather than break
535 static int mips_trap = 0;
537 /* 1 if double width floating point constants should not be constructed
538 by assembling two single width halves into two single width floating
539 point registers which just happen to alias the double width destination
540 register. On some architectures this aliasing can be disabled by a bit
541 in the status register, and the setting of this bit cannot be determined
542 automatically at assemble time. */
543 static int mips_disable_float_construction;
545 /* Non-zero if any .set noreorder directives were used. */
547 static int mips_any_noreorder;
549 /* Non-zero if nops should be inserted when the register referenced in
550 an mfhi/mflo instruction is read in the next two instructions. */
551 static int mips_7000_hilo_fix;
553 /* The size of objects in the small data section. */
554 static unsigned int g_switch_value = 8;
555 /* Whether the -G option was used. */
556 static int g_switch_seen = 0;
561 /* If we can determine in advance that GP optimization won't be
562 possible, we can skip the relaxation stuff that tries to produce
563 GP-relative references. This makes delay slot optimization work
566 This function can only provide a guess, but it seems to work for
567 gcc output. It needs to guess right for gcc, otherwise gcc
568 will put what it thinks is a GP-relative instruction in a branch
571 I don't know if a fix is needed for the SVR4_PIC mode. I've only
572 fixed it for the non-PIC mode. KR 95/04/07 */
573 static int nopic_need_relax (symbolS *, int);
575 /* handle of the OPCODE hash table */
576 static struct hash_control *op_hash = NULL;
578 /* The opcode hash table we use for the mips16. */
579 static struct hash_control *mips16_op_hash = NULL;
581 /* This array holds the chars that always start a comment. If the
582 pre-processor is disabled, these aren't very useful */
583 const char comment_chars[] = "#";
585 /* This array holds the chars that only start a comment at the beginning of
586 a line. If the line seems to have the form '# 123 filename'
587 .line and .file directives will appear in the pre-processed output */
588 /* Note that input_file.c hand checks for '#' at the beginning of the
589 first line of the input file. This is because the compiler outputs
590 #NO_APP at the beginning of its output. */
591 /* Also note that C style comments are always supported. */
592 const char line_comment_chars[] = "#";
594 /* This array holds machine specific line separator characters. */
595 const char line_separator_chars[] = ";";
597 /* Chars that can be used to separate mant from exp in floating point nums */
598 const char EXP_CHARS[] = "eE";
600 /* Chars that mean this number is a floating point constant */
603 const char FLT_CHARS[] = "rRsSfFdDxXpP";
605 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
606 changed in read.c . Ideally it shouldn't have to know about it at all,
607 but nothing is ideal around here.
610 static char *insn_error;
612 static int auto_align = 1;
614 /* When outputting SVR4 PIC code, the assembler needs to know the
615 offset in the stack frame from which to restore the $gp register.
616 This is set by the .cprestore pseudo-op, and saved in this
618 static offsetT mips_cprestore_offset = -1;
620 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
621 more optimizations, it can use a register value instead of a memory-saved
622 offset and even an other register than $gp as global pointer. */
623 static offsetT mips_cpreturn_offset = -1;
624 static int mips_cpreturn_register = -1;
625 static int mips_gp_register = GP;
626 static int mips_gprel_offset = 0;
628 /* Whether mips_cprestore_offset has been set in the current function
629 (or whether it has already been warned about, if not). */
630 static int mips_cprestore_valid = 0;
632 /* This is the register which holds the stack frame, as set by the
633 .frame pseudo-op. This is needed to implement .cprestore. */
634 static int mips_frame_reg = SP;
636 /* Whether mips_frame_reg has been set in the current function
637 (or whether it has already been warned about, if not). */
638 static int mips_frame_reg_valid = 0;
640 /* To output NOP instructions correctly, we need to keep information
641 about the previous two instructions. */
643 /* Whether we are optimizing. The default value of 2 means to remove
644 unneeded NOPs and swap branch instructions when possible. A value
645 of 1 means to not swap branches. A value of 0 means to always
647 static int mips_optimize = 2;
649 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
650 equivalent to seeing no -g option at all. */
651 static int mips_debug = 0;
653 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
654 #define MAX_VR4130_NOPS 4
656 /* The maximum number of NOPs needed to fill delay slots. */
657 #define MAX_DELAY_NOPS 2
659 /* The maximum number of NOPs needed for any purpose. */
662 /* A list of previous instructions, with index 0 being the most recent.
663 We need to look back MAX_NOPS instructions when filling delay slots
664 or working around processor errata. We need to look back one
665 instruction further if we're thinking about using history[0] to
666 fill a branch delay slot. */
667 static struct mips_cl_insn history[1 + MAX_NOPS];
669 /* Nop instructions used by emit_nop. */
670 static struct mips_cl_insn nop_insn, mips16_nop_insn;
672 /* The appropriate nop for the current mode. */
673 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
675 /* If this is set, it points to a frag holding nop instructions which
676 were inserted before the start of a noreorder section. If those
677 nops turn out to be unnecessary, the size of the frag can be
679 static fragS *prev_nop_frag;
681 /* The number of nop instructions we created in prev_nop_frag. */
682 static int prev_nop_frag_holds;
684 /* The number of nop instructions that we know we need in
686 static int prev_nop_frag_required;
688 /* The number of instructions we've seen since prev_nop_frag. */
689 static int prev_nop_frag_since;
691 /* For ECOFF and ELF, relocations against symbols are done in two
692 parts, with a HI relocation and a LO relocation. Each relocation
693 has only 16 bits of space to store an addend. This means that in
694 order for the linker to handle carries correctly, it must be able
695 to locate both the HI and the LO relocation. This means that the
696 relocations must appear in order in the relocation table.
698 In order to implement this, we keep track of each unmatched HI
699 relocation. We then sort them so that they immediately precede the
700 corresponding LO relocation. */
705 struct mips_hi_fixup *next;
708 /* The section this fixup is in. */
712 /* The list of unmatched HI relocs. */
714 static struct mips_hi_fixup *mips_hi_fixup_list;
716 /* The frag containing the last explicit relocation operator.
717 Null if explicit relocations have not been used. */
719 static fragS *prev_reloc_op_frag;
721 /* Map normal MIPS register numbers to mips16 register numbers. */
723 #define X ILLEGAL_REG
724 static const int mips32_to_16_reg_map[] =
726 X, X, 2, 3, 4, 5, 6, 7,
727 X, X, X, X, X, X, X, X,
728 0, 1, X, X, X, X, X, X,
729 X, X, X, X, X, X, X, X
733 /* Map mips16 register numbers to normal MIPS register numbers. */
735 static const unsigned int mips16_to_32_reg_map[] =
737 16, 17, 2, 3, 4, 5, 6, 7
740 /* Classifies the kind of instructions we're interested in when
741 implementing -mfix-vr4120. */
742 enum fix_vr4120_class {
749 NUM_FIX_VR4120_CLASSES
752 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
753 there must be at least one other instruction between an instruction
754 of type X and an instruction of type Y. */
755 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
757 /* True if -mfix-vr4120 is in force. */
758 static int mips_fix_vr4120;
760 /* ...likewise -mfix-vr4130. */
761 static int mips_fix_vr4130;
763 /* ...likewise -mfix-24k. */
764 static int mips_fix_24k;
766 /* We don't relax branches by default, since this causes us to expand
767 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
768 fail to compute the offset before expanding the macro to the most
769 efficient expansion. */
771 static int mips_relax_branch;
773 /* The expansion of many macros depends on the type of symbol that
774 they refer to. For example, when generating position-dependent code,
775 a macro that refers to a symbol may have two different expansions,
776 one which uses GP-relative addresses and one which uses absolute
777 addresses. When generating SVR4-style PIC, a macro may have
778 different expansions for local and global symbols.
780 We handle these situations by generating both sequences and putting
781 them in variant frags. In position-dependent code, the first sequence
782 will be the GP-relative one and the second sequence will be the
783 absolute one. In SVR4 PIC, the first sequence will be for global
784 symbols and the second will be for local symbols.
786 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
787 SECOND are the lengths of the two sequences in bytes. These fields
788 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
789 the subtype has the following flags:
792 Set if it has been decided that we should use the second
793 sequence instead of the first.
796 Set in the first variant frag if the macro's second implementation
797 is longer than its first. This refers to the macro as a whole,
798 not an individual relaxation.
801 Set in the first variant frag if the macro appeared in a .set nomacro
802 block and if one alternative requires a warning but the other does not.
805 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
808 The frag's "opcode" points to the first fixup for relaxable code.
810 Relaxable macros are generated using a sequence such as:
812 relax_start (SYMBOL);
813 ... generate first expansion ...
815 ... generate second expansion ...
818 The code and fixups for the unwanted alternative are discarded
819 by md_convert_frag. */
820 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
822 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
823 #define RELAX_SECOND(X) ((X) & 0xff)
824 #define RELAX_USE_SECOND 0x10000
825 #define RELAX_SECOND_LONGER 0x20000
826 #define RELAX_NOMACRO 0x40000
827 #define RELAX_DELAY_SLOT 0x80000
829 /* Branch without likely bit. If label is out of range, we turn:
831 beq reg1, reg2, label
841 with the following opcode replacements:
848 bltzal <-> bgezal (with jal label instead of j label)
850 Even though keeping the delay slot instruction in the delay slot of
851 the branch would be more efficient, it would be very tricky to do
852 correctly, because we'd have to introduce a variable frag *after*
853 the delay slot instruction, and expand that instead. Let's do it
854 the easy way for now, even if the branch-not-taken case now costs
855 one additional instruction. Out-of-range branches are not supposed
856 to be common, anyway.
858 Branch likely. If label is out of range, we turn:
860 beql reg1, reg2, label
861 delay slot (annulled if branch not taken)
870 delay slot (executed only if branch taken)
873 It would be possible to generate a shorter sequence by losing the
874 likely bit, generating something like:
879 delay slot (executed only if branch taken)
891 bltzall -> bgezal (with jal label instead of j label)
892 bgezall -> bltzal (ditto)
895 but it's not clear that it would actually improve performance. */
896 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
899 | ((toofar) ? 1 : 0) \
901 | ((likely) ? 4 : 0) \
902 | ((uncond) ? 8 : 0)))
903 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
904 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
905 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
906 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
907 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
909 /* For mips16 code, we use an entirely different form of relaxation.
910 mips16 supports two versions of most instructions which take
911 immediate values: a small one which takes some small value, and a
912 larger one which takes a 16 bit value. Since branches also follow
913 this pattern, relaxing these values is required.
915 We can assemble both mips16 and normal MIPS code in a single
916 object. Therefore, we need to support this type of relaxation at
917 the same time that we support the relaxation described above. We
918 use the high bit of the subtype field to distinguish these cases.
920 The information we store for this type of relaxation is the
921 argument code found in the opcode file for this relocation, whether
922 the user explicitly requested a small or extended form, and whether
923 the relocation is in a jump or jal delay slot. That tells us the
924 size of the value, and how it should be stored. We also store
925 whether the fragment is considered to be extended or not. We also
926 store whether this is known to be a branch to a different section,
927 whether we have tried to relax this frag yet, and whether we have
928 ever extended a PC relative fragment because of a shift count. */
929 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
932 | ((small) ? 0x100 : 0) \
933 | ((ext) ? 0x200 : 0) \
934 | ((dslot) ? 0x400 : 0) \
935 | ((jal_dslot) ? 0x800 : 0))
936 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
937 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
938 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
939 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
940 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
941 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
942 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
943 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
944 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
945 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
946 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
947 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
949 /* Is the given value a sign-extended 32-bit value? */
950 #define IS_SEXT_32BIT_NUM(x) \
951 (((x) &~ (offsetT) 0x7fffffff) == 0 \
952 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
954 /* Is the given value a sign-extended 16-bit value? */
955 #define IS_SEXT_16BIT_NUM(x) \
956 (((x) &~ (offsetT) 0x7fff) == 0 \
957 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
959 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
960 #define IS_ZEXT_32BIT_NUM(x) \
961 (((x) &~ (offsetT) 0xffffffff) == 0 \
962 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
964 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
965 VALUE << SHIFT. VALUE is evaluated exactly once. */
966 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
967 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
968 | (((VALUE) & (MASK)) << (SHIFT)))
970 /* Extract bits MASK << SHIFT from STRUCT and shift them right
972 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
973 (((STRUCT) >> (SHIFT)) & (MASK))
975 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
976 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
978 include/opcode/mips.h specifies operand fields using the macros
979 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
980 with "MIPS16OP" instead of "OP". */
981 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
982 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
983 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
984 INSERT_BITS ((INSN).insn_opcode, VALUE, \
985 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
987 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
988 #define EXTRACT_OPERAND(FIELD, INSN) \
989 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
990 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
991 EXTRACT_BITS ((INSN).insn_opcode, \
992 MIPS16OP_MASK_##FIELD, \
995 /* Global variables used when generating relaxable macros. See the
996 comment above RELAX_ENCODE for more details about how relaxation
999 /* 0 if we're not emitting a relaxable macro.
1000 1 if we're emitting the first of the two relaxation alternatives.
1001 2 if we're emitting the second alternative. */
1004 /* The first relaxable fixup in the current frag. (In other words,
1005 the first fixup that refers to relaxable code.) */
1008 /* sizes[0] says how many bytes of the first alternative are stored in
1009 the current frag. Likewise sizes[1] for the second alternative. */
1010 unsigned int sizes[2];
1012 /* The symbol on which the choice of sequence depends. */
1016 /* Global variables used to decide whether a macro needs a warning. */
1018 /* True if the macro is in a branch delay slot. */
1019 bfd_boolean delay_slot_p;
1021 /* For relaxable macros, sizes[0] is the length of the first alternative
1022 in bytes and sizes[1] is the length of the second alternative.
1023 For non-relaxable macros, both elements give the length of the
1025 unsigned int sizes[2];
1027 /* The first variant frag for this macro. */
1029 } mips_macro_warning;
1031 /* Prototypes for static functions. */
1033 #define internalError() \
1034 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1036 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1038 static void append_insn
1039 (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r);
1040 static void mips_no_prev_insn (void);
1041 static void mips16_macro_build
1042 (expressionS *, const char *, const char *, va_list);
1043 static void load_register (int, expressionS *, int);
1044 static void macro_start (void);
1045 static void macro_end (void);
1046 static void macro (struct mips_cl_insn * ip);
1047 static void mips16_macro (struct mips_cl_insn * ip);
1048 #ifdef LOSING_COMPILER
1049 static void macro2 (struct mips_cl_insn * ip);
1051 static void mips_ip (char *str, struct mips_cl_insn * ip);
1052 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1053 static void mips16_immed
1054 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
1055 unsigned long *, bfd_boolean *, unsigned short *);
1056 static size_t my_getSmallExpression
1057 (expressionS *, bfd_reloc_code_real_type *, char *);
1058 static void my_getExpression (expressionS *, char *);
1059 static void s_align (int);
1060 static void s_change_sec (int);
1061 static void s_change_section (int);
1062 static void s_cons (int);
1063 static void s_float_cons (int);
1064 static void s_mips_globl (int);
1065 static void s_option (int);
1066 static void s_mipsset (int);
1067 static void s_abicalls (int);
1068 static void s_cpload (int);
1069 static void s_cpsetup (int);
1070 static void s_cplocal (int);
1071 static void s_cprestore (int);
1072 static void s_cpreturn (int);
1073 static void s_dtprelword (int);
1074 static void s_dtpreldword (int);
1075 static void s_gpvalue (int);
1076 static void s_gpword (int);
1077 static void s_gpdword (int);
1078 static void s_cpadd (int);
1079 static void s_insn (int);
1080 static void md_obj_begin (void);
1081 static void md_obj_end (void);
1082 static void s_mips_ent (int);
1083 static void s_mips_end (int);
1084 static void s_mips_frame (int);
1085 static void s_mips_mask (int reg_type);
1086 static void s_mips_stab (int);
1087 static void s_mips_weakext (int);
1088 static void s_mips_file (int);
1089 static void s_mips_loc (int);
1090 static bfd_boolean pic_need_relax (symbolS *, asection *);
1091 static int relaxed_branch_length (fragS *, asection *, int);
1092 static int validate_mips_insn (const struct mips_opcode *);
1094 /* Table and functions used to map between CPU/ISA names, and
1095 ISA levels, and CPU numbers. */
1097 struct mips_cpu_info
1099 const char *name; /* CPU or ISA name. */
1100 int flags; /* ASEs available, or ISA flag. */
1101 int isa; /* ISA level. */
1102 int cpu; /* CPU number (default CPU if ISA). */
1105 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1106 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1107 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1108 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1109 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1110 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1111 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1113 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1114 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1115 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1119 The following pseudo-ops from the Kane and Heinrich MIPS book
1120 should be defined here, but are currently unsupported: .alias,
1121 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1123 The following pseudo-ops from the Kane and Heinrich MIPS book are
1124 specific to the type of debugging information being generated, and
1125 should be defined by the object format: .aent, .begin, .bend,
1126 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1129 The following pseudo-ops from the Kane and Heinrich MIPS book are
1130 not MIPS CPU specific, but are also not specific to the object file
1131 format. This file is probably the best place to define them, but
1132 they are not currently supported: .asm0, .endr, .lab, .struct. */
1134 static const pseudo_typeS mips_pseudo_table[] =
1136 /* MIPS specific pseudo-ops. */
1137 {"option", s_option, 0},
1138 {"set", s_mipsset, 0},
1139 {"rdata", s_change_sec, 'r'},
1140 {"sdata", s_change_sec, 's'},
1141 {"livereg", s_ignore, 0},
1142 {"abicalls", s_abicalls, 0},
1143 {"cpload", s_cpload, 0},
1144 {"cpsetup", s_cpsetup, 0},
1145 {"cplocal", s_cplocal, 0},
1146 {"cprestore", s_cprestore, 0},
1147 {"cpreturn", s_cpreturn, 0},
1148 {"dtprelword", s_dtprelword, 0},
1149 {"dtpreldword", s_dtpreldword, 0},
1150 {"gpvalue", s_gpvalue, 0},
1151 {"gpword", s_gpword, 0},
1152 {"gpdword", s_gpdword, 0},
1153 {"cpadd", s_cpadd, 0},
1154 {"insn", s_insn, 0},
1156 /* Relatively generic pseudo-ops that happen to be used on MIPS
1158 {"asciiz", stringer, 8 + 1},
1159 {"bss", s_change_sec, 'b'},
1161 {"half", s_cons, 1},
1162 {"dword", s_cons, 3},
1163 {"weakext", s_mips_weakext, 0},
1164 {"origin", s_org, 0},
1165 {"repeat", s_rept, 0},
1167 /* These pseudo-ops are defined in read.c, but must be overridden
1168 here for one reason or another. */
1169 {"align", s_align, 0},
1170 {"byte", s_cons, 0},
1171 {"data", s_change_sec, 'd'},
1172 {"double", s_float_cons, 'd'},
1173 {"float", s_float_cons, 'f'},
1174 {"globl", s_mips_globl, 0},
1175 {"global", s_mips_globl, 0},
1176 {"hword", s_cons, 1},
1178 {"long", s_cons, 2},
1179 {"octa", s_cons, 4},
1180 {"quad", s_cons, 3},
1181 {"section", s_change_section, 0},
1182 {"short", s_cons, 1},
1183 {"single", s_float_cons, 'f'},
1184 {"stabn", s_mips_stab, 'n'},
1185 {"text", s_change_sec, 't'},
1186 {"word", s_cons, 2},
1188 { "extern", ecoff_directive_extern, 0},
1193 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1195 /* These pseudo-ops should be defined by the object file format.
1196 However, a.out doesn't support them, so we have versions here. */
1197 {"aent", s_mips_ent, 1},
1198 {"bgnb", s_ignore, 0},
1199 {"end", s_mips_end, 0},
1200 {"endb", s_ignore, 0},
1201 {"ent", s_mips_ent, 0},
1202 {"file", s_mips_file, 0},
1203 {"fmask", s_mips_mask, 'F'},
1204 {"frame", s_mips_frame, 0},
1205 {"loc", s_mips_loc, 0},
1206 {"mask", s_mips_mask, 'R'},
1207 {"verstamp", s_ignore, 0},
1211 extern void pop_insert (const pseudo_typeS *);
1214 mips_pop_insert (void)
1216 pop_insert (mips_pseudo_table);
1217 if (! ECOFF_DEBUGGING)
1218 pop_insert (mips_nonecoff_pseudo_table);
1221 /* Symbols labelling the current insn. */
1223 struct insn_label_list
1225 struct insn_label_list *next;
1229 static struct insn_label_list *free_insn_labels;
1230 #define label_list tc_segment_info_data.labels
1232 static void mips_clear_insn_labels (void);
1235 mips_clear_insn_labels (void)
1237 register struct insn_label_list **pl;
1238 segment_info_type *si;
1242 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1245 si = seg_info (now_seg);
1246 *pl = si->label_list;
1247 si->label_list = NULL;
1252 static char *expr_end;
1254 /* Expressions which appear in instructions. These are set by
1257 static expressionS imm_expr;
1258 static expressionS imm2_expr;
1259 static expressionS offset_expr;
1261 /* Relocs associated with imm_expr and offset_expr. */
1263 static bfd_reloc_code_real_type imm_reloc[3]
1264 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1265 static bfd_reloc_code_real_type offset_reloc[3]
1266 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1268 /* These are set by mips16_ip if an explicit extension is used. */
1270 static bfd_boolean mips16_small, mips16_ext;
1273 /* The pdr segment for per procedure frame/regmask info. Not used for
1276 static segT pdr_seg;
1279 /* The default target format to use. */
1282 mips_target_format (void)
1284 switch (OUTPUT_FLAVOR)
1286 case bfd_target_ecoff_flavour:
1287 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1288 case bfd_target_coff_flavour:
1290 case bfd_target_elf_flavour:
1292 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1293 return (target_big_endian
1294 ? "elf32-bigmips-vxworks"
1295 : "elf32-littlemips-vxworks");
1298 /* This is traditional mips. */
1299 return (target_big_endian
1300 ? (HAVE_64BIT_OBJECTS
1301 ? "elf64-tradbigmips"
1303 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1304 : (HAVE_64BIT_OBJECTS
1305 ? "elf64-tradlittlemips"
1307 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1309 return (target_big_endian
1310 ? (HAVE_64BIT_OBJECTS
1313 ? "elf32-nbigmips" : "elf32-bigmips"))
1314 : (HAVE_64BIT_OBJECTS
1315 ? "elf64-littlemips"
1317 ? "elf32-nlittlemips" : "elf32-littlemips")));
1325 /* Return the length of instruction INSN. */
1327 static inline unsigned int
1328 insn_length (const struct mips_cl_insn *insn)
1330 if (!mips_opts.mips16)
1332 return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2;
1335 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1338 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1343 insn->use_extend = FALSE;
1345 insn->insn_opcode = mo->match;
1348 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1349 insn->fixp[i] = NULL;
1350 insn->fixed_p = (mips_opts.noreorder > 0);
1351 insn->noreorder_p = (mips_opts.noreorder > 0);
1352 insn->mips16_absolute_jump_p = 0;
1355 /* Record the current MIPS16 mode in now_seg. */
1358 mips_record_mips16_mode (void)
1360 segment_info_type *si;
1362 si = seg_info (now_seg);
1363 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
1364 si->tc_segment_info_data.mips16 = mips_opts.mips16;
1367 /* Install INSN at the location specified by its "frag" and "where" fields. */
1370 install_insn (const struct mips_cl_insn *insn)
1372 char *f = insn->frag->fr_literal + insn->where;
1373 if (!mips_opts.mips16)
1374 md_number_to_chars (f, insn->insn_opcode, 4);
1375 else if (insn->mips16_absolute_jump_p)
1377 md_number_to_chars (f, insn->insn_opcode >> 16, 2);
1378 md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2);
1382 if (insn->use_extend)
1384 md_number_to_chars (f, 0xf000 | insn->extend, 2);
1387 md_number_to_chars (f, insn->insn_opcode, 2);
1389 mips_record_mips16_mode ();
1392 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1393 and install the opcode in the new location. */
1396 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
1401 insn->where = where;
1402 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1403 if (insn->fixp[i] != NULL)
1405 insn->fixp[i]->fx_frag = frag;
1406 insn->fixp[i]->fx_where = where;
1408 install_insn (insn);
1411 /* Add INSN to the end of the output. */
1414 add_fixed_insn (struct mips_cl_insn *insn)
1416 char *f = frag_more (insn_length (insn));
1417 move_insn (insn, frag_now, f - frag_now->fr_literal);
1420 /* Start a variant frag and move INSN to the start of the variant part,
1421 marking it as fixed. The other arguments are as for frag_var. */
1424 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
1425 relax_substateT subtype, symbolS *symbol, offsetT offset)
1427 frag_grow (max_chars);
1428 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
1430 frag_var (rs_machine_dependent, max_chars, var,
1431 subtype, symbol, offset, NULL);
1434 /* Insert N copies of INSN into the history buffer, starting at
1435 position FIRST. Neither FIRST nor N need to be clipped. */
1438 insert_into_history (unsigned int first, unsigned int n,
1439 const struct mips_cl_insn *insn)
1441 if (mips_relax.sequence != 2)
1445 for (i = ARRAY_SIZE (history); i-- > first;)
1447 history[i] = history[i - n];
1453 /* Emit a nop instruction, recording it in the history buffer. */
1458 add_fixed_insn (NOP_INSN);
1459 insert_into_history (0, 1, NOP_INSN);
1462 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1463 the idea is to make it obvious at a glance that each errata is
1467 init_vr4120_conflicts (void)
1469 #define CONFLICT(FIRST, SECOND) \
1470 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1472 /* Errata 21 - [D]DIV[U] after [D]MACC */
1473 CONFLICT (MACC, DIV);
1474 CONFLICT (DMACC, DIV);
1476 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1477 CONFLICT (DMULT, DMULT);
1478 CONFLICT (DMULT, DMACC);
1479 CONFLICT (DMACC, DMULT);
1480 CONFLICT (DMACC, DMACC);
1482 /* Errata 24 - MT{LO,HI} after [D]MACC */
1483 CONFLICT (MACC, MTHILO);
1484 CONFLICT (DMACC, MTHILO);
1486 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1487 instruction is executed immediately after a MACC or DMACC
1488 instruction, the result of [either instruction] is incorrect." */
1489 CONFLICT (MACC, MULT);
1490 CONFLICT (MACC, DMULT);
1491 CONFLICT (DMACC, MULT);
1492 CONFLICT (DMACC, DMULT);
1494 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1495 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1496 DDIV or DDIVU instruction, the result of the MACC or
1497 DMACC instruction is incorrect.". */
1498 CONFLICT (DMULT, MACC);
1499 CONFLICT (DMULT, DMACC);
1500 CONFLICT (DIV, MACC);
1501 CONFLICT (DIV, DMACC);
1511 #define RTYPE_MASK 0x1ff00
1512 #define RTYPE_NUM 0x00100
1513 #define RTYPE_FPU 0x00200
1514 #define RTYPE_FCC 0x00400
1515 #define RTYPE_VEC 0x00800
1516 #define RTYPE_GP 0x01000
1517 #define RTYPE_CP0 0x02000
1518 #define RTYPE_PC 0x04000
1519 #define RTYPE_ACC 0x08000
1520 #define RTYPE_CCC 0x10000
1521 #define RNUM_MASK 0x000ff
1522 #define RWARN 0x80000
1524 #define GENERIC_REGISTER_NUMBERS \
1525 {"$0", RTYPE_NUM | 0}, \
1526 {"$1", RTYPE_NUM | 1}, \
1527 {"$2", RTYPE_NUM | 2}, \
1528 {"$3", RTYPE_NUM | 3}, \
1529 {"$4", RTYPE_NUM | 4}, \
1530 {"$5", RTYPE_NUM | 5}, \
1531 {"$6", RTYPE_NUM | 6}, \
1532 {"$7", RTYPE_NUM | 7}, \
1533 {"$8", RTYPE_NUM | 8}, \
1534 {"$9", RTYPE_NUM | 9}, \
1535 {"$10", RTYPE_NUM | 10}, \
1536 {"$11", RTYPE_NUM | 11}, \
1537 {"$12", RTYPE_NUM | 12}, \
1538 {"$13", RTYPE_NUM | 13}, \
1539 {"$14", RTYPE_NUM | 14}, \
1540 {"$15", RTYPE_NUM | 15}, \
1541 {"$16", RTYPE_NUM | 16}, \
1542 {"$17", RTYPE_NUM | 17}, \
1543 {"$18", RTYPE_NUM | 18}, \
1544 {"$19", RTYPE_NUM | 19}, \
1545 {"$20", RTYPE_NUM | 20}, \
1546 {"$21", RTYPE_NUM | 21}, \
1547 {"$22", RTYPE_NUM | 22}, \
1548 {"$23", RTYPE_NUM | 23}, \
1549 {"$24", RTYPE_NUM | 24}, \
1550 {"$25", RTYPE_NUM | 25}, \
1551 {"$26", RTYPE_NUM | 26}, \
1552 {"$27", RTYPE_NUM | 27}, \
1553 {"$28", RTYPE_NUM | 28}, \
1554 {"$29", RTYPE_NUM | 29}, \
1555 {"$30", RTYPE_NUM | 30}, \
1556 {"$31", RTYPE_NUM | 31}
1558 #define FPU_REGISTER_NAMES \
1559 {"$f0", RTYPE_FPU | 0}, \
1560 {"$f1", RTYPE_FPU | 1}, \
1561 {"$f2", RTYPE_FPU | 2}, \
1562 {"$f3", RTYPE_FPU | 3}, \
1563 {"$f4", RTYPE_FPU | 4}, \
1564 {"$f5", RTYPE_FPU | 5}, \
1565 {"$f6", RTYPE_FPU | 6}, \
1566 {"$f7", RTYPE_FPU | 7}, \
1567 {"$f8", RTYPE_FPU | 8}, \
1568 {"$f9", RTYPE_FPU | 9}, \
1569 {"$f10", RTYPE_FPU | 10}, \
1570 {"$f11", RTYPE_FPU | 11}, \
1571 {"$f12", RTYPE_FPU | 12}, \
1572 {"$f13", RTYPE_FPU | 13}, \
1573 {"$f14", RTYPE_FPU | 14}, \
1574 {"$f15", RTYPE_FPU | 15}, \
1575 {"$f16", RTYPE_FPU | 16}, \
1576 {"$f17", RTYPE_FPU | 17}, \
1577 {"$f18", RTYPE_FPU | 18}, \
1578 {"$f19", RTYPE_FPU | 19}, \
1579 {"$f20", RTYPE_FPU | 20}, \
1580 {"$f21", RTYPE_FPU | 21}, \
1581 {"$f22", RTYPE_FPU | 22}, \
1582 {"$f23", RTYPE_FPU | 23}, \
1583 {"$f24", RTYPE_FPU | 24}, \
1584 {"$f25", RTYPE_FPU | 25}, \
1585 {"$f26", RTYPE_FPU | 26}, \
1586 {"$f27", RTYPE_FPU | 27}, \
1587 {"$f28", RTYPE_FPU | 28}, \
1588 {"$f29", RTYPE_FPU | 29}, \
1589 {"$f30", RTYPE_FPU | 30}, \
1590 {"$f31", RTYPE_FPU | 31}
1592 #define FPU_CONDITION_CODE_NAMES \
1593 {"$fcc0", RTYPE_FCC | 0}, \
1594 {"$fcc1", RTYPE_FCC | 1}, \
1595 {"$fcc2", RTYPE_FCC | 2}, \
1596 {"$fcc3", RTYPE_FCC | 3}, \
1597 {"$fcc4", RTYPE_FCC | 4}, \
1598 {"$fcc5", RTYPE_FCC | 5}, \
1599 {"$fcc6", RTYPE_FCC | 6}, \
1600 {"$fcc7", RTYPE_FCC | 7}
1602 #define COPROC_CONDITION_CODE_NAMES \
1603 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1604 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1605 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1606 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1607 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1608 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1609 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1610 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1612 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1613 {"$a4", RTYPE_GP | 8}, \
1614 {"$a5", RTYPE_GP | 9}, \
1615 {"$a6", RTYPE_GP | 10}, \
1616 {"$a7", RTYPE_GP | 11}, \
1617 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1618 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1619 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1620 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1621 {"$t0", RTYPE_GP | 12}, \
1622 {"$t1", RTYPE_GP | 13}, \
1623 {"$t2", RTYPE_GP | 14}, \
1624 {"$t3", RTYPE_GP | 15}
1626 #define O32_SYMBOLIC_REGISTER_NAMES \
1627 {"$t0", RTYPE_GP | 8}, \
1628 {"$t1", RTYPE_GP | 9}, \
1629 {"$t2", RTYPE_GP | 10}, \
1630 {"$t3", RTYPE_GP | 11}, \
1631 {"$t4", RTYPE_GP | 12}, \
1632 {"$t5", RTYPE_GP | 13}, \
1633 {"$t6", RTYPE_GP | 14}, \
1634 {"$t7", RTYPE_GP | 15}, \
1635 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1636 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1637 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1638 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1640 /* Remaining symbolic register names */
1641 #define SYMBOLIC_REGISTER_NAMES \
1642 {"$zero", RTYPE_GP | 0}, \
1643 {"$at", RTYPE_GP | 1}, \
1644 {"$AT", RTYPE_GP | 1}, \
1645 {"$v0", RTYPE_GP | 2}, \
1646 {"$v1", RTYPE_GP | 3}, \
1647 {"$a0", RTYPE_GP | 4}, \
1648 {"$a1", RTYPE_GP | 5}, \
1649 {"$a2", RTYPE_GP | 6}, \
1650 {"$a3", RTYPE_GP | 7}, \
1651 {"$s0", RTYPE_GP | 16}, \
1652 {"$s1", RTYPE_GP | 17}, \
1653 {"$s2", RTYPE_GP | 18}, \
1654 {"$s3", RTYPE_GP | 19}, \
1655 {"$s4", RTYPE_GP | 20}, \
1656 {"$s5", RTYPE_GP | 21}, \
1657 {"$s6", RTYPE_GP | 22}, \
1658 {"$s7", RTYPE_GP | 23}, \
1659 {"$t8", RTYPE_GP | 24}, \
1660 {"$t9", RTYPE_GP | 25}, \
1661 {"$k0", RTYPE_GP | 26}, \
1662 {"$kt0", RTYPE_GP | 26}, \
1663 {"$k1", RTYPE_GP | 27}, \
1664 {"$kt1", RTYPE_GP | 27}, \
1665 {"$gp", RTYPE_GP | 28}, \
1666 {"$sp", RTYPE_GP | 29}, \
1667 {"$s8", RTYPE_GP | 30}, \
1668 {"$fp", RTYPE_GP | 30}, \
1669 {"$ra", RTYPE_GP | 31}
1671 #define MIPS16_SPECIAL_REGISTER_NAMES \
1672 {"$pc", RTYPE_PC | 0}
1674 #define MDMX_VECTOR_REGISTER_NAMES \
1675 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
1676 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
1677 {"$v2", RTYPE_VEC | 2}, \
1678 {"$v3", RTYPE_VEC | 3}, \
1679 {"$v4", RTYPE_VEC | 4}, \
1680 {"$v5", RTYPE_VEC | 5}, \
1681 {"$v6", RTYPE_VEC | 6}, \
1682 {"$v7", RTYPE_VEC | 7}, \
1683 {"$v8", RTYPE_VEC | 8}, \
1684 {"$v9", RTYPE_VEC | 9}, \
1685 {"$v10", RTYPE_VEC | 10}, \
1686 {"$v11", RTYPE_VEC | 11}, \
1687 {"$v12", RTYPE_VEC | 12}, \
1688 {"$v13", RTYPE_VEC | 13}, \
1689 {"$v14", RTYPE_VEC | 14}, \
1690 {"$v15", RTYPE_VEC | 15}, \
1691 {"$v16", RTYPE_VEC | 16}, \
1692 {"$v17", RTYPE_VEC | 17}, \
1693 {"$v18", RTYPE_VEC | 18}, \
1694 {"$v19", RTYPE_VEC | 19}, \
1695 {"$v20", RTYPE_VEC | 20}, \
1696 {"$v21", RTYPE_VEC | 21}, \
1697 {"$v22", RTYPE_VEC | 22}, \
1698 {"$v23", RTYPE_VEC | 23}, \
1699 {"$v24", RTYPE_VEC | 24}, \
1700 {"$v25", RTYPE_VEC | 25}, \
1701 {"$v26", RTYPE_VEC | 26}, \
1702 {"$v27", RTYPE_VEC | 27}, \
1703 {"$v28", RTYPE_VEC | 28}, \
1704 {"$v29", RTYPE_VEC | 29}, \
1705 {"$v30", RTYPE_VEC | 30}, \
1706 {"$v31", RTYPE_VEC | 31}
1708 #define MIPS_DSP_ACCUMULATOR_NAMES \
1709 {"$ac0", RTYPE_ACC | 0}, \
1710 {"$ac1", RTYPE_ACC | 1}, \
1711 {"$ac2", RTYPE_ACC | 2}, \
1712 {"$ac3", RTYPE_ACC | 3}
1714 static const struct regname reg_names[] = {
1715 GENERIC_REGISTER_NUMBERS,
1717 FPU_CONDITION_CODE_NAMES,
1718 COPROC_CONDITION_CODE_NAMES,
1720 /* The $txx registers depends on the abi,
1721 these will be added later into the symbol table from
1722 one of the tables below once mips_abi is set after
1723 parsing of arguments from the command line. */
1724 SYMBOLIC_REGISTER_NAMES,
1726 MIPS16_SPECIAL_REGISTER_NAMES,
1727 MDMX_VECTOR_REGISTER_NAMES,
1728 MIPS_DSP_ACCUMULATOR_NAMES,
1732 static const struct regname reg_names_o32[] = {
1733 O32_SYMBOLIC_REGISTER_NAMES,
1737 static const struct regname reg_names_n32n64[] = {
1738 N32N64_SYMBOLIC_REGISTER_NAMES,
1743 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
1750 /* Find end of name. */
1752 if (is_name_beginner (*e))
1754 while (is_part_of_name (*e))
1757 /* Terminate name. */
1761 /* Look for a register symbol. */
1762 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
1764 int r = S_GET_VALUE (symbolP);
1766 reg = r & RNUM_MASK;
1767 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
1768 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
1769 reg = (r & RNUM_MASK) - 2;
1771 /* Else see if this is a register defined in an itbl entry. */
1772 else if ((types & RTYPE_GP) && itbl_have_entries)
1779 if (itbl_get_reg_val (n, &r))
1780 reg = r & RNUM_MASK;
1783 /* Advance to next token if a register was recognised. */
1786 else if (types & RWARN)
1787 as_warn ("Unrecognized register name `%s'", *s);
1795 #define INSN_ERET 0x42000018
1796 #define INSN_DERET 0x4200001f
1798 /* Implement the ERET/DERET Errata for MIPS 24k.
1800 If an ERET/DERET is encountered in a noreorder block,
1801 warn if the ERET/DERET is followed by a branch instruction.
1802 Also warn if the ERET/DERET is the last instruction in the
1805 IF an ERET/DERET is in a reorder block and is followed by a
1806 branch instruction, insert a nop. */
1809 check_for_24k_errata (struct mips_cl_insn *insn, int eret_ndx)
1811 bfd_boolean next_insn_is_branch = FALSE;
1813 /* eret_ndx will be -1 for the last instruction in a section
1814 and the ERET/DERET will be in insn, not history. */
1817 && (insn->insn_opcode == INSN_ERET
1818 || insn->insn_opcode == INSN_DERET)
1819 && insn->noreorder_p)
1821 as_warn (_("ERET and DERET must be followed by a NOP on the 24K."));
1825 if (history[eret_ndx].insn_opcode != INSN_ERET
1826 && history[eret_ndx].insn_opcode != INSN_DERET)
1831 if (history[eret_ndx].noreorder_p)
1832 as_warn (_("ERET and DERET must be followed by a NOP on the 24K."));
1836 next_insn_is_branch = ((insn->insn_opcode == INSN_ERET)
1837 || (insn->insn_opcode == INSN_DERET)
1838 || (insn->insn_mo->pinfo
1839 & (INSN_UNCOND_BRANCH_DELAY
1840 | INSN_COND_BRANCH_DELAY
1841 | INSN_COND_BRANCH_LIKELY)));
1843 if (next_insn_is_branch && history[eret_ndx].noreorder_p)
1845 as_warn (_("ERET and DERET must be followed by a NOP on the 24K."));
1849 /* Emit nop if the next instruction is a branch. */
1850 if (next_insn_is_branch)
1852 long nop_where, br_where;
1853 struct frag *nop_frag, *br_frag;
1854 struct mips_cl_insn br_insn, nop_insn;
1858 nop_insn = history[eret_ndx - 1];
1859 nop_frag = history[eret_ndx - 1].frag;
1860 nop_where = history[eret_ndx - 1].where;
1862 br_insn = history[eret_ndx];
1863 br_frag = history[eret_ndx].frag;
1864 br_where = history[eret_ndx].where;
1866 move_insn (&nop_insn, br_frag, br_where);
1867 move_insn (&br_insn, nop_frag, nop_where);
1869 history[eret_ndx-1] = br_insn;
1870 history[eret_ndx] = nop_insn;
1874 /* Return TRUE if opcode MO is valid on the currently selected ISA and
1875 architecture. If EXPANSIONP is TRUE then this check is done while
1876 expanding a macro. Use is_opcode_valid_16 for MIPS16 opcodes. */
1879 is_opcode_valid (const struct mips_opcode *mo, bfd_boolean expansionp)
1881 int isa = mips_opts.isa;
1884 if (mips_opts.ase_mdmx)
1886 if (mips_opts.ase_dsp)
1888 if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
1890 if (mips_opts.ase_dspr2)
1892 if (mips_opts.ase_mt)
1894 if (mips_opts.ase_mips3d)
1896 if (mips_opts.ase_smartmips)
1897 isa |= INSN_SMARTMIPS;
1899 /* For user code we don't check for mips_opts.mips16 since we want
1900 to allow jalx if -mips16 was specified on the command line. */
1901 if (expansionp ? mips_opts.mips16 : file_ase_mips16)
1904 /* Don't accept instructions based on the ISA if the CPU does not implement
1905 all the coprocessor insns. */
1906 if (NO_ISA_COP (mips_opts.arch)
1907 && COP_INSN (mo->pinfo))
1910 if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch))
1913 /* Check whether the instruction or macro requires single-precision or
1914 double-precision floating-point support. Note that this information is
1915 stored differently in the opcode table for insns and macros. */
1916 if (mo->pinfo == INSN_MACRO)
1918 fp_s = mo->pinfo2 & INSN2_M_FP_S;
1919 fp_d = mo->pinfo2 & INSN2_M_FP_D;
1923 fp_s = mo->pinfo & FP_S;
1924 fp_d = mo->pinfo & FP_D;
1927 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
1930 if (fp_s && mips_opts.soft_float)
1936 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
1937 selected ISA and architecture. */
1940 is_opcode_valid_16 (const struct mips_opcode *mo)
1942 return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE;
1945 /* This function is called once, at assembler startup time. It should set up
1946 all the tables, etc. that the MD part of the assembler will need. */
1951 const char *retval = NULL;
1955 if (mips_pic != NO_PIC)
1957 if (g_switch_seen && g_switch_value != 0)
1958 as_bad (_("-G may not be used in position-independent code"));
1962 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
1963 as_warn (_("Could not set architecture and machine"));
1965 op_hash = hash_new ();
1967 for (i = 0; i < NUMOPCODES;)
1969 const char *name = mips_opcodes[i].name;
1971 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
1974 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1975 mips_opcodes[i].name, retval);
1976 /* Probably a memory allocation problem? Give up now. */
1977 as_fatal (_("Broken assembler. No assembly attempted."));
1981 if (mips_opcodes[i].pinfo != INSN_MACRO)
1983 if (!validate_mips_insn (&mips_opcodes[i]))
1985 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
1987 create_insn (&nop_insn, mips_opcodes + i);
1988 nop_insn.fixed_p = 1;
1993 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1996 mips16_op_hash = hash_new ();
1999 while (i < bfd_mips16_num_opcodes)
2001 const char *name = mips16_opcodes[i].name;
2003 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
2005 as_fatal (_("internal: can't hash `%s': %s"),
2006 mips16_opcodes[i].name, retval);
2009 if (mips16_opcodes[i].pinfo != INSN_MACRO
2010 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
2011 != mips16_opcodes[i].match))
2013 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
2014 mips16_opcodes[i].name, mips16_opcodes[i].args);
2017 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2019 create_insn (&mips16_nop_insn, mips16_opcodes + i);
2020 mips16_nop_insn.fixed_p = 1;
2024 while (i < bfd_mips16_num_opcodes
2025 && strcmp (mips16_opcodes[i].name, name) == 0);
2029 as_fatal (_("Broken assembler. No assembly attempted."));
2031 /* We add all the general register names to the symbol table. This
2032 helps us detect invalid uses of them. */
2033 for (i = 0; reg_names[i].name; i++)
2034 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
2035 reg_names[i].num, /* & RNUM_MASK, */
2036 &zero_address_frag));
2038 for (i = 0; reg_names_n32n64[i].name; i++)
2039 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
2040 reg_names_n32n64[i].num, /* & RNUM_MASK, */
2041 &zero_address_frag));
2043 for (i = 0; reg_names_o32[i].name; i++)
2044 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
2045 reg_names_o32[i].num, /* & RNUM_MASK, */
2046 &zero_address_frag));
2048 mips_no_prev_insn ();
2051 mips_cprmask[0] = 0;
2052 mips_cprmask[1] = 0;
2053 mips_cprmask[2] = 0;
2054 mips_cprmask[3] = 0;
2056 /* set the default alignment for the text section (2**2) */
2057 record_alignment (text_section, 2);
2059 bfd_set_gp_size (stdoutput, g_switch_value);
2064 /* On a native system other than VxWorks, sections must be aligned
2065 to 16 byte boundaries. When configured for an embedded ELF
2066 target, we don't bother. */
2067 if (strncmp (TARGET_OS, "elf", 3) != 0
2068 && strncmp (TARGET_OS, "vxworks", 7) != 0)
2070 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
2071 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
2072 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
2075 /* Create a .reginfo section for register masks and a .mdebug
2076 section for debugging information. */
2084 subseg = now_subseg;
2086 /* The ABI says this section should be loaded so that the
2087 running program can access it. However, we don't load it
2088 if we are configured for an embedded target */
2089 flags = SEC_READONLY | SEC_DATA;
2090 if (strncmp (TARGET_OS, "elf", 3) != 0)
2091 flags |= SEC_ALLOC | SEC_LOAD;
2093 if (mips_abi != N64_ABI)
2095 sec = subseg_new (".reginfo", (subsegT) 0);
2097 bfd_set_section_flags (stdoutput, sec, flags);
2098 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
2100 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
2104 /* The 64-bit ABI uses a .MIPS.options section rather than
2105 .reginfo section. */
2106 sec = subseg_new (".MIPS.options", (subsegT) 0);
2107 bfd_set_section_flags (stdoutput, sec, flags);
2108 bfd_set_section_alignment (stdoutput, sec, 3);
2110 /* Set up the option header. */
2112 Elf_Internal_Options opthdr;
2115 opthdr.kind = ODK_REGINFO;
2116 opthdr.size = (sizeof (Elf_External_Options)
2117 + sizeof (Elf64_External_RegInfo));
2120 f = frag_more (sizeof (Elf_External_Options));
2121 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2122 (Elf_External_Options *) f);
2124 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2128 if (ECOFF_DEBUGGING)
2130 sec = subseg_new (".mdebug", (subsegT) 0);
2131 (void) bfd_set_section_flags (stdoutput, sec,
2132 SEC_HAS_CONTENTS | SEC_READONLY);
2133 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2135 else if (mips_flag_pdr)
2137 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2138 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2139 SEC_READONLY | SEC_RELOC
2141 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2144 subseg_set (seg, subseg);
2147 #endif /* OBJ_ELF */
2149 if (! ECOFF_DEBUGGING)
2152 if (mips_fix_vr4120)
2153 init_vr4120_conflicts ();
2160 check_for_24k_errata ((struct mips_cl_insn *) &history[0], -1);
2162 if (! ECOFF_DEBUGGING)
2167 md_assemble (char *str)
2169 struct mips_cl_insn insn;
2170 bfd_reloc_code_real_type unused_reloc[3]
2171 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2173 imm_expr.X_op = O_absent;
2174 imm2_expr.X_op = O_absent;
2175 offset_expr.X_op = O_absent;
2176 imm_reloc[0] = BFD_RELOC_UNUSED;
2177 imm_reloc[1] = BFD_RELOC_UNUSED;
2178 imm_reloc[2] = BFD_RELOC_UNUSED;
2179 offset_reloc[0] = BFD_RELOC_UNUSED;
2180 offset_reloc[1] = BFD_RELOC_UNUSED;
2181 offset_reloc[2] = BFD_RELOC_UNUSED;
2183 if (mips_opts.mips16)
2184 mips16_ip (str, &insn);
2187 mips_ip (str, &insn);
2188 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2189 str, insn.insn_opcode));
2194 as_bad ("%s `%s'", insn_error, str);
2198 if (insn.insn_mo->pinfo == INSN_MACRO)
2201 if (mips_opts.mips16)
2202 mips16_macro (&insn);
2209 if (imm_expr.X_op != O_absent)
2210 append_insn (&insn, &imm_expr, imm_reloc);
2211 else if (offset_expr.X_op != O_absent)
2212 append_insn (&insn, &offset_expr, offset_reloc);
2214 append_insn (&insn, NULL, unused_reloc);
2218 /* Convenience functions for abstracting away the differences between
2219 MIPS16 and non-MIPS16 relocations. */
2221 static inline bfd_boolean
2222 mips16_reloc_p (bfd_reloc_code_real_type reloc)
2226 case BFD_RELOC_MIPS16_JMP:
2227 case BFD_RELOC_MIPS16_GPREL:
2228 case BFD_RELOC_MIPS16_GOT16:
2229 case BFD_RELOC_MIPS16_CALL16:
2230 case BFD_RELOC_MIPS16_HI16_S:
2231 case BFD_RELOC_MIPS16_HI16:
2232 case BFD_RELOC_MIPS16_LO16:
2240 static inline bfd_boolean
2241 got16_reloc_p (bfd_reloc_code_real_type reloc)
2243 return reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16;
2246 static inline bfd_boolean
2247 hi16_reloc_p (bfd_reloc_code_real_type reloc)
2249 return reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S;
2252 static inline bfd_boolean
2253 lo16_reloc_p (bfd_reloc_code_real_type reloc)
2255 return reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16;
2258 /* Return true if the given relocation might need a matching %lo().
2259 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2260 need a matching %lo() when applied to local symbols. */
2262 static inline bfd_boolean
2263 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
2265 return (HAVE_IN_PLACE_ADDENDS
2266 && (hi16_reloc_p (reloc)
2267 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2268 all GOT16 relocations evaluate to "G". */
2269 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
2272 /* Return the type of %lo() reloc needed by RELOC, given that
2273 reloc_needs_lo_p. */
2275 static inline bfd_reloc_code_real_type
2276 matching_lo_reloc (bfd_reloc_code_real_type reloc)
2278 return mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 : BFD_RELOC_LO16;
2281 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2284 static inline bfd_boolean
2285 fixup_has_matching_lo_p (fixS *fixp)
2287 return (fixp->fx_next != NULL
2288 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
2289 && fixp->fx_addsy == fixp->fx_next->fx_addsy
2290 && fixp->fx_offset == fixp->fx_next->fx_offset);
2293 /* See whether instruction IP reads register REG. CLASS is the type
2297 insn_uses_reg (const struct mips_cl_insn *ip, unsigned int reg,
2298 enum mips_regclass class)
2300 if (class == MIPS16_REG)
2302 assert (mips_opts.mips16);
2303 reg = mips16_to_32_reg_map[reg];
2304 class = MIPS_GR_REG;
2307 /* Don't report on general register ZERO, since it never changes. */
2308 if (class == MIPS_GR_REG && reg == ZERO)
2311 if (class == MIPS_FP_REG)
2313 assert (! mips_opts.mips16);
2314 /* If we are called with either $f0 or $f1, we must check $f0.
2315 This is not optimal, because it will introduce an unnecessary
2316 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
2317 need to distinguish reading both $f0 and $f1 or just one of
2318 them. Note that we don't have to check the other way,
2319 because there is no instruction that sets both $f0 and $f1
2320 and requires a delay. */
2321 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
2322 && ((EXTRACT_OPERAND (FS, *ip) & ~(unsigned) 1)
2323 == (reg &~ (unsigned) 1)))
2325 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
2326 && ((EXTRACT_OPERAND (FT, *ip) & ~(unsigned) 1)
2327 == (reg &~ (unsigned) 1)))
2330 else if (! mips_opts.mips16)
2332 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
2333 && EXTRACT_OPERAND (RS, *ip) == reg)
2335 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
2336 && EXTRACT_OPERAND (RT, *ip) == reg)
2341 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
2342 && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)] == reg)
2344 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
2345 && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)] == reg)
2347 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
2348 && (mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]
2351 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
2353 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
2355 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
2357 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
2358 && MIPS16_EXTRACT_OPERAND (REGR32, *ip) == reg)
2365 /* This function returns true if modifying a register requires a
2369 reg_needs_delay (unsigned int reg)
2371 unsigned long prev_pinfo;
2373 prev_pinfo = history[0].insn_mo->pinfo;
2374 if (! mips_opts.noreorder
2375 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2376 && ! gpr_interlocks)
2377 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
2378 && ! cop_interlocks)))
2380 /* A load from a coprocessor or from memory. All load delays
2381 delay the use of general register rt for one instruction. */
2382 /* Itbl support may require additional care here. */
2383 know (prev_pinfo & INSN_WRITE_GPR_T);
2384 if (reg == EXTRACT_OPERAND (RT, history[0]))
2391 /* Move all labels in insn_labels to the current insertion point. */
2394 mips_move_labels (void)
2396 segment_info_type *si = seg_info (now_seg);
2397 struct insn_label_list *l;
2400 for (l = si->label_list; l != NULL; l = l->next)
2402 assert (S_GET_SEGMENT (l->label) == now_seg);
2403 symbol_set_frag (l->label, frag_now);
2404 val = (valueT) frag_now_fix ();
2405 /* mips16 text labels are stored as odd. */
2406 if (mips_opts.mips16)
2408 S_SET_VALUE (l->label, val);
2413 s_is_linkonce (symbolS *sym, segT from_seg)
2415 bfd_boolean linkonce = FALSE;
2416 segT symseg = S_GET_SEGMENT (sym);
2418 if (symseg != from_seg && !S_IS_LOCAL (sym))
2420 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
2423 /* The GNU toolchain uses an extension for ELF: a section
2424 beginning with the magic string .gnu.linkonce is a
2425 linkonce section. */
2426 if (strncmp (segment_name (symseg), ".gnu.linkonce",
2427 sizeof ".gnu.linkonce" - 1) == 0)
2434 /* Mark instruction labels in mips16 mode. This permits the linker to
2435 handle them specially, such as generating jalx instructions when
2436 needed. We also make them odd for the duration of the assembly, in
2437 order to generate the right sort of code. We will make them even
2438 in the adjust_symtab routine, while leaving them marked. This is
2439 convenient for the debugger and the disassembler. The linker knows
2440 to make them odd again. */
2443 mips16_mark_labels (void)
2445 segment_info_type *si = seg_info (now_seg);
2446 struct insn_label_list *l;
2448 if (!mips_opts.mips16)
2451 for (l = si->label_list; l != NULL; l = l->next)
2453 symbolS *label = l->label;
2455 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2457 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
2459 if ((S_GET_VALUE (label) & 1) == 0
2460 /* Don't adjust the address if the label is global or weak, or
2461 in a link-once section, since we'll be emitting symbol reloc
2462 references to it which will be patched up by the linker, and
2463 the final value of the symbol may or may not be MIPS16. */
2464 && ! S_IS_WEAK (label)
2465 && ! S_IS_EXTERNAL (label)
2466 && ! s_is_linkonce (label, now_seg))
2467 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
2471 /* End the current frag. Make it a variant frag and record the
2475 relax_close_frag (void)
2477 mips_macro_warning.first_frag = frag_now;
2478 frag_var (rs_machine_dependent, 0, 0,
2479 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
2480 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
2482 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
2483 mips_relax.first_fixup = 0;
2486 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2487 See the comment above RELAX_ENCODE for more details. */
2490 relax_start (symbolS *symbol)
2492 assert (mips_relax.sequence == 0);
2493 mips_relax.sequence = 1;
2494 mips_relax.symbol = symbol;
2497 /* Start generating the second version of a relaxable sequence.
2498 See the comment above RELAX_ENCODE for more details. */
2503 assert (mips_relax.sequence == 1);
2504 mips_relax.sequence = 2;
2507 /* End the current relaxable sequence. */
2512 assert (mips_relax.sequence == 2);
2513 relax_close_frag ();
2514 mips_relax.sequence = 0;
2517 /* Classify an instruction according to the FIX_VR4120_* enumeration.
2518 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
2519 by VR4120 errata. */
2522 classify_vr4120_insn (const char *name)
2524 if (strncmp (name, "macc", 4) == 0)
2525 return FIX_VR4120_MACC;
2526 if (strncmp (name, "dmacc", 5) == 0)
2527 return FIX_VR4120_DMACC;
2528 if (strncmp (name, "mult", 4) == 0)
2529 return FIX_VR4120_MULT;
2530 if (strncmp (name, "dmult", 5) == 0)
2531 return FIX_VR4120_DMULT;
2532 if (strstr (name, "div"))
2533 return FIX_VR4120_DIV;
2534 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
2535 return FIX_VR4120_MTHILO;
2536 return NUM_FIX_VR4120_CLASSES;
2539 /* Return the number of instructions that must separate INSN1 and INSN2,
2540 where INSN1 is the earlier instruction. Return the worst-case value
2541 for any INSN2 if INSN2 is null. */
2544 insns_between (const struct mips_cl_insn *insn1,
2545 const struct mips_cl_insn *insn2)
2547 unsigned long pinfo1, pinfo2;
2549 /* This function needs to know which pinfo flags are set for INSN2
2550 and which registers INSN2 uses. The former is stored in PINFO2 and
2551 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
2552 will have every flag set and INSN2_USES_REG will always return true. */
2553 pinfo1 = insn1->insn_mo->pinfo;
2554 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
2556 #define INSN2_USES_REG(REG, CLASS) \
2557 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
2559 /* For most targets, write-after-read dependencies on the HI and LO
2560 registers must be separated by at least two instructions. */
2561 if (!hilo_interlocks)
2563 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
2565 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
2569 /* If we're working around r7000 errata, there must be two instructions
2570 between an mfhi or mflo and any instruction that uses the result. */
2571 if (mips_7000_hilo_fix
2572 && MF_HILO_INSN (pinfo1)
2573 && INSN2_USES_REG (EXTRACT_OPERAND (RD, *insn1), MIPS_GR_REG))
2576 /* If working around VR4120 errata, check for combinations that need
2577 a single intervening instruction. */
2578 if (mips_fix_vr4120)
2580 unsigned int class1, class2;
2582 class1 = classify_vr4120_insn (insn1->insn_mo->name);
2583 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
2587 class2 = classify_vr4120_insn (insn2->insn_mo->name);
2588 if (vr4120_conflicts[class1] & (1 << class2))
2593 if (!mips_opts.mips16)
2595 /* Check for GPR or coprocessor load delays. All such delays
2596 are on the RT register. */
2597 /* Itbl support may require additional care here. */
2598 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
2599 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
2601 know (pinfo1 & INSN_WRITE_GPR_T);
2602 if (INSN2_USES_REG (EXTRACT_OPERAND (RT, *insn1), MIPS_GR_REG))
2606 /* Check for generic coprocessor hazards.
2608 This case is not handled very well. There is no special
2609 knowledge of CP0 handling, and the coprocessors other than
2610 the floating point unit are not distinguished at all. */
2611 /* Itbl support may require additional care here. FIXME!
2612 Need to modify this to include knowledge about
2613 user specified delays! */
2614 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
2615 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
2617 /* Handle cases where INSN1 writes to a known general coprocessor
2618 register. There must be a one instruction delay before INSN2
2619 if INSN2 reads that register, otherwise no delay is needed. */
2620 if (pinfo1 & INSN_WRITE_FPR_T)
2622 if (INSN2_USES_REG (EXTRACT_OPERAND (FT, *insn1), MIPS_FP_REG))
2625 else if (pinfo1 & INSN_WRITE_FPR_S)
2627 if (INSN2_USES_REG (EXTRACT_OPERAND (FS, *insn1), MIPS_FP_REG))
2632 /* Read-after-write dependencies on the control registers
2633 require a two-instruction gap. */
2634 if ((pinfo1 & INSN_WRITE_COND_CODE)
2635 && (pinfo2 & INSN_READ_COND_CODE))
2638 /* We don't know exactly what INSN1 does. If INSN2 is
2639 also a coprocessor instruction, assume there must be
2640 a one instruction gap. */
2641 if (pinfo2 & INSN_COP)
2646 /* Check for read-after-write dependencies on the coprocessor
2647 control registers in cases where INSN1 does not need a general
2648 coprocessor delay. This means that INSN1 is a floating point
2649 comparison instruction. */
2650 /* Itbl support may require additional care here. */
2651 else if (!cop_interlocks
2652 && (pinfo1 & INSN_WRITE_COND_CODE)
2653 && (pinfo2 & INSN_READ_COND_CODE))
2657 #undef INSN2_USES_REG
2662 /* Return the number of nops that would be needed to work around the
2663 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2664 the MAX_VR4130_NOPS instructions described by HISTORY. */
2667 nops_for_vr4130 (const struct mips_cl_insn *history,
2668 const struct mips_cl_insn *insn)
2672 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2673 are not affected by the errata. */
2675 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
2676 || strcmp (insn->insn_mo->name, "mtlo") == 0
2677 || strcmp (insn->insn_mo->name, "mthi") == 0))
2680 /* Search for the first MFLO or MFHI. */
2681 for (i = 0; i < MAX_VR4130_NOPS; i++)
2682 if (MF_HILO_INSN (history[i].insn_mo->pinfo))
2684 /* Extract the destination register. */
2685 if (mips_opts.mips16)
2686 reg = mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, history[i])];
2688 reg = EXTRACT_OPERAND (RD, history[i]);
2690 /* No nops are needed if INSN reads that register. */
2691 if (insn != NULL && insn_uses_reg (insn, reg, MIPS_GR_REG))
2694 /* ...or if any of the intervening instructions do. */
2695 for (j = 0; j < i; j++)
2696 if (insn_uses_reg (&history[j], reg, MIPS_GR_REG))
2699 return MAX_VR4130_NOPS - i;
2704 /* Return the number of nops that would be needed if instruction INSN
2705 immediately followed the MAX_NOPS instructions given by HISTORY,
2706 where HISTORY[0] is the most recent instruction. If INSN is null,
2707 return the worse-case number of nops for any instruction. */
2710 nops_for_insn (const struct mips_cl_insn *history,
2711 const struct mips_cl_insn *insn)
2713 int i, nops, tmp_nops;
2716 for (i = 0; i < MAX_DELAY_NOPS; i++)
2718 tmp_nops = insns_between (history + i, insn) - i;
2719 if (tmp_nops > nops)
2723 if (mips_fix_vr4130)
2725 tmp_nops = nops_for_vr4130 (history, insn);
2726 if (tmp_nops > nops)
2733 /* The variable arguments provide NUM_INSNS extra instructions that
2734 might be added to HISTORY. Return the largest number of nops that
2735 would be needed after the extended sequence. */
2738 nops_for_sequence (int num_insns, const struct mips_cl_insn *history, ...)
2741 struct mips_cl_insn buffer[MAX_NOPS];
2742 struct mips_cl_insn *cursor;
2745 va_start (args, history);
2746 cursor = buffer + num_insns;
2747 memcpy (cursor, history, (MAX_NOPS - num_insns) * sizeof (*cursor));
2748 while (cursor > buffer)
2749 *--cursor = *va_arg (args, const struct mips_cl_insn *);
2751 nops = nops_for_insn (buffer, NULL);
2756 /* Like nops_for_insn, but if INSN is a branch, take into account the
2757 worst-case delay for the branch target. */
2760 nops_for_insn_or_target (const struct mips_cl_insn *history,
2761 const struct mips_cl_insn *insn)
2765 nops = nops_for_insn (history, insn);
2766 if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
2767 | INSN_COND_BRANCH_DELAY
2768 | INSN_COND_BRANCH_LIKELY))
2770 tmp_nops = nops_for_sequence (2, history, insn, NOP_INSN);
2771 if (tmp_nops > nops)
2774 else if (mips_opts.mips16 && (insn->insn_mo->pinfo & MIPS16_INSN_BRANCH))
2776 tmp_nops = nops_for_sequence (1, history, insn);
2777 if (tmp_nops > nops)
2783 /* Output an instruction. IP is the instruction information.
2784 ADDRESS_EXPR is an operand of the instruction to be used with
2788 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
2789 bfd_reloc_code_real_type *reloc_type)
2791 unsigned long prev_pinfo, pinfo;
2793 relax_stateT prev_insn_frag_type = 0;
2794 bfd_boolean relaxed_branch = FALSE;
2795 segment_info_type *si = seg_info (now_seg);
2797 /* Mark instruction labels in mips16 mode. */
2798 mips16_mark_labels ();
2800 prev_pinfo = history[0].insn_mo->pinfo;
2801 pinfo = ip->insn_mo->pinfo;
2803 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
2805 /* There are a lot of optimizations we could do that we don't.
2806 In particular, we do not, in general, reorder instructions.
2807 If you use gcc with optimization, it will reorder
2808 instructions and generally do much more optimization then we
2809 do here; repeating all that work in the assembler would only
2810 benefit hand written assembly code, and does not seem worth
2812 int nops = (mips_optimize == 0
2813 ? nops_for_insn (history, NULL)
2814 : nops_for_insn_or_target (history, ip));
2818 unsigned long old_frag_offset;
2821 old_frag = frag_now;
2822 old_frag_offset = frag_now_fix ();
2824 for (i = 0; i < nops; i++)
2829 listing_prev_line ();
2830 /* We may be at the start of a variant frag. In case we
2831 are, make sure there is enough space for the frag
2832 after the frags created by listing_prev_line. The
2833 argument to frag_grow here must be at least as large
2834 as the argument to all other calls to frag_grow in
2835 this file. We don't have to worry about being in the
2836 middle of a variant frag, because the variants insert
2837 all needed nop instructions themselves. */
2841 mips_move_labels ();
2843 #ifndef NO_ECOFF_DEBUGGING
2844 if (ECOFF_DEBUGGING)
2845 ecoff_fix_loc (old_frag, old_frag_offset);
2849 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
2851 /* Work out how many nops in prev_nop_frag are needed by IP. */
2852 int nops = nops_for_insn_or_target (history, ip);
2853 assert (nops <= prev_nop_frag_holds);
2855 /* Enforce NOPS as a minimum. */
2856 if (nops > prev_nop_frag_required)
2857 prev_nop_frag_required = nops;
2859 if (prev_nop_frag_holds == prev_nop_frag_required)
2861 /* Settle for the current number of nops. Update the history
2862 accordingly (for the benefit of any future .set reorder code). */
2863 prev_nop_frag = NULL;
2864 insert_into_history (prev_nop_frag_since,
2865 prev_nop_frag_holds, NOP_INSN);
2869 /* Allow this instruction to replace one of the nops that was
2870 tentatively added to prev_nop_frag. */
2871 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
2872 prev_nop_frag_holds--;
2873 prev_nop_frag_since++;
2878 /* The value passed to dwarf2_emit_insn is the distance between
2879 the beginning of the current instruction and the address that
2880 should be recorded in the debug tables. For MIPS16 debug info
2881 we want to use ISA-encoded addresses, so we pass -1 for an
2882 address higher by one than the current. */
2883 dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0);
2886 /* Record the frag type before frag_var. */
2887 if (history[0].frag)
2888 prev_insn_frag_type = history[0].frag->fr_type;
2891 && *reloc_type == BFD_RELOC_16_PCREL_S2
2892 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
2893 || pinfo & INSN_COND_BRANCH_LIKELY)
2894 && mips_relax_branch
2895 /* Don't try branch relaxation within .set nomacro, or within
2896 .set noat if we use $at for PIC computations. If it turns
2897 out that the branch was out-of-range, we'll get an error. */
2898 && !mips_opts.warn_about_macros
2899 && (mips_opts.at || mips_pic == NO_PIC)
2900 && !mips_opts.mips16)
2902 relaxed_branch = TRUE;
2903 add_relaxed_insn (ip, (relaxed_branch_length
2905 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
2906 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1
2909 (pinfo & INSN_UNCOND_BRANCH_DELAY,
2910 pinfo & INSN_COND_BRANCH_LIKELY,
2911 pinfo & INSN_WRITE_GPR_31,
2913 address_expr->X_add_symbol,
2914 address_expr->X_add_number);
2915 *reloc_type = BFD_RELOC_UNUSED;
2917 else if (*reloc_type > BFD_RELOC_UNUSED)
2919 /* We need to set up a variant frag. */
2920 assert (mips_opts.mips16 && address_expr != NULL);
2921 add_relaxed_insn (ip, 4, 0,
2923 (*reloc_type - BFD_RELOC_UNUSED,
2924 mips16_small, mips16_ext,
2925 prev_pinfo & INSN_UNCOND_BRANCH_DELAY,
2926 history[0].mips16_absolute_jump_p),
2927 make_expr_symbol (address_expr), 0);
2929 else if (mips_opts.mips16
2931 && *reloc_type != BFD_RELOC_MIPS16_JMP)
2933 if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0)
2934 /* Make sure there is enough room to swap this instruction with
2935 a following jump instruction. */
2937 add_fixed_insn (ip);
2941 if (mips_opts.mips16
2942 && mips_opts.noreorder
2943 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2944 as_warn (_("extended instruction in delay slot"));
2946 if (mips_relax.sequence)
2948 /* If we've reached the end of this frag, turn it into a variant
2949 frag and record the information for the instructions we've
2951 if (frag_room () < 4)
2952 relax_close_frag ();
2953 mips_relax.sizes[mips_relax.sequence - 1] += 4;
2956 if (mips_relax.sequence != 2)
2957 mips_macro_warning.sizes[0] += 4;
2958 if (mips_relax.sequence != 1)
2959 mips_macro_warning.sizes[1] += 4;
2961 if (mips_opts.mips16)
2964 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
2966 add_fixed_insn (ip);
2969 if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED)
2971 if (address_expr->X_op == O_constant)
2975 switch (*reloc_type)
2978 ip->insn_opcode |= address_expr->X_add_number;
2981 case BFD_RELOC_MIPS_HIGHEST:
2982 tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48;
2983 ip->insn_opcode |= tmp & 0xffff;
2986 case BFD_RELOC_MIPS_HIGHER:
2987 tmp = (address_expr->X_add_number + 0x80008000ull) >> 32;
2988 ip->insn_opcode |= tmp & 0xffff;
2991 case BFD_RELOC_HI16_S:
2992 tmp = (address_expr->X_add_number + 0x8000) >> 16;
2993 ip->insn_opcode |= tmp & 0xffff;
2996 case BFD_RELOC_HI16:
2997 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
3000 case BFD_RELOC_UNUSED:
3001 case BFD_RELOC_LO16:
3002 case BFD_RELOC_MIPS_GOT_DISP:
3003 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
3006 case BFD_RELOC_MIPS_JMP:
3007 if ((address_expr->X_add_number & 3) != 0)
3008 as_bad (_("jump to misaligned address (0x%lx)"),
3009 (unsigned long) address_expr->X_add_number);
3010 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
3013 case BFD_RELOC_MIPS16_JMP:
3014 if ((address_expr->X_add_number & 3) != 0)
3015 as_bad (_("jump to misaligned address (0x%lx)"),
3016 (unsigned long) address_expr->X_add_number);
3018 (((address_expr->X_add_number & 0x7c0000) << 3)
3019 | ((address_expr->X_add_number & 0xf800000) >> 7)
3020 | ((address_expr->X_add_number & 0x3fffc) >> 2));
3023 case BFD_RELOC_16_PCREL_S2:
3024 if ((address_expr->X_add_number & 3) != 0)
3025 as_bad (_("branch to misaligned address (0x%lx)"),
3026 (unsigned long) address_expr->X_add_number);
3027 if (mips_relax_branch)
3029 if ((address_expr->X_add_number + 0x20000) & ~0x3ffff)
3030 as_bad (_("branch address range overflow (0x%lx)"),
3031 (unsigned long) address_expr->X_add_number);
3032 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff;
3039 else if (*reloc_type < BFD_RELOC_UNUSED)
3042 reloc_howto_type *howto;
3045 /* In a compound relocation, it is the final (outermost)
3046 operator that determines the relocated field. */
3047 for (i = 1; i < 3; i++)
3048 if (reloc_type[i] == BFD_RELOC_UNUSED)
3051 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
3054 /* To reproduce this failure try assembling gas/testsuites/
3055 gas/mips/mips16-intermix.s with a mips-ecoff targeted
3057 as_bad (_("Unsupported MIPS relocation number %d"), reloc_type[i - 1]);
3058 howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16);
3061 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
3062 bfd_get_reloc_size (howto),
3064 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
3067 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
3068 if (reloc_type[0] == BFD_RELOC_MIPS16_JMP
3069 && ip->fixp[0]->fx_addsy)
3070 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
3072 /* These relocations can have an addend that won't fit in
3073 4 octets for 64bit assembly. */
3075 && ! howto->partial_inplace
3076 && (reloc_type[0] == BFD_RELOC_16
3077 || reloc_type[0] == BFD_RELOC_32
3078 || reloc_type[0] == BFD_RELOC_MIPS_JMP
3079 || reloc_type[0] == BFD_RELOC_GPREL16
3080 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
3081 || reloc_type[0] == BFD_RELOC_GPREL32
3082 || reloc_type[0] == BFD_RELOC_64
3083 || reloc_type[0] == BFD_RELOC_CTOR
3084 || reloc_type[0] == BFD_RELOC_MIPS_SUB
3085 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
3086 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
3087 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
3088 || reloc_type[0] == BFD_RELOC_MIPS_REL16
3089 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
3090 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
3091 || hi16_reloc_p (reloc_type[0])
3092 || lo16_reloc_p (reloc_type[0])))
3093 ip->fixp[0]->fx_no_overflow = 1;
3095 if (mips_relax.sequence)
3097 if (mips_relax.first_fixup == 0)
3098 mips_relax.first_fixup = ip->fixp[0];
3100 else if (reloc_needs_lo_p (*reloc_type))
3102 struct mips_hi_fixup *hi_fixup;
3104 /* Reuse the last entry if it already has a matching %lo. */
3105 hi_fixup = mips_hi_fixup_list;
3107 || !fixup_has_matching_lo_p (hi_fixup->fixp))
3109 hi_fixup = ((struct mips_hi_fixup *)
3110 xmalloc (sizeof (struct mips_hi_fixup)));
3111 hi_fixup->next = mips_hi_fixup_list;
3112 mips_hi_fixup_list = hi_fixup;
3114 hi_fixup->fixp = ip->fixp[0];
3115 hi_fixup->seg = now_seg;
3118 /* Add fixups for the second and third relocations, if given.
3119 Note that the ABI allows the second relocation to be
3120 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
3121 moment we only use RSS_UNDEF, but we could add support
3122 for the others if it ever becomes necessary. */
3123 for (i = 1; i < 3; i++)
3124 if (reloc_type[i] != BFD_RELOC_UNUSED)
3126 ip->fixp[i] = fix_new (ip->frag, ip->where,
3127 ip->fixp[0]->fx_size, NULL, 0,
3128 FALSE, reloc_type[i]);
3130 /* Use fx_tcbit to mark compound relocs. */
3131 ip->fixp[0]->fx_tcbit = 1;
3132 ip->fixp[i]->fx_tcbit = 1;
3138 /* Update the register mask information. */
3139 if (! mips_opts.mips16)
3141 if (pinfo & INSN_WRITE_GPR_D)
3142 mips_gprmask |= 1 << EXTRACT_OPERAND (RD, *ip);
3143 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
3144 mips_gprmask |= 1 << EXTRACT_OPERAND (RT, *ip);
3145 if (pinfo & INSN_READ_GPR_S)
3146 mips_gprmask |= 1 << EXTRACT_OPERAND (RS, *ip);
3147 if (pinfo & INSN_WRITE_GPR_31)
3148 mips_gprmask |= 1 << RA;
3149 if (pinfo & INSN_WRITE_FPR_D)
3150 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FD, *ip);
3151 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
3152 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FS, *ip);
3153 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
3154 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FT, *ip);
3155 if ((pinfo & INSN_READ_FPR_R) != 0)
3156 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FR, *ip);
3157 if (pinfo & INSN_COP)
3159 /* We don't keep enough information to sort these cases out.
3160 The itbl support does keep this information however, although
3161 we currently don't support itbl fprmats as part of the cop
3162 instruction. May want to add this support in the future. */
3164 /* Never set the bit for $0, which is always zero. */
3165 mips_gprmask &= ~1 << 0;
3169 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
3170 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RX, *ip);
3171 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
3172 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RY, *ip);
3173 if (pinfo & MIPS16_INSN_WRITE_Z)
3174 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RZ, *ip);
3175 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
3176 mips_gprmask |= 1 << TREG;
3177 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
3178 mips_gprmask |= 1 << SP;
3179 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
3180 mips_gprmask |= 1 << RA;
3181 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
3182 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
3183 if (pinfo & MIPS16_INSN_READ_Z)
3184 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip);
3185 if (pinfo & MIPS16_INSN_READ_GPR_X)
3186 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
3189 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
3191 /* Filling the branch delay slot is more complex. We try to
3192 switch the branch with the previous instruction, which we can
3193 do if the previous instruction does not set up a condition
3194 that the branch tests and if the branch is not itself the
3195 target of any branch. */
3196 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
3197 || (pinfo & INSN_COND_BRANCH_DELAY))
3199 if (mips_optimize < 2
3200 /* If we have seen .set volatile or .set nomove, don't
3202 || mips_opts.nomove != 0
3203 /* We can't swap if the previous instruction's position
3205 || history[0].fixed_p
3206 /* If the previous previous insn was in a .set
3207 noreorder, we can't swap. Actually, the MIPS
3208 assembler will swap in this situation. However, gcc
3209 configured -with-gnu-as will generate code like
3215 in which we can not swap the bne and INSN. If gcc is
3216 not configured -with-gnu-as, it does not output the
3218 || history[1].noreorder_p
3219 /* If the branch is itself the target of a branch, we
3220 can not swap. We cheat on this; all we check for is
3221 whether there is a label on this instruction. If
3222 there are any branches to anything other than a
3223 label, users must use .set noreorder. */
3224 || si->label_list != NULL
3225 /* If the previous instruction is in a variant frag
3226 other than this branch's one, we cannot do the swap.
3227 This does not apply to the mips16, which uses variant
3228 frags for different purposes. */
3229 || (! mips_opts.mips16
3230 && prev_insn_frag_type == rs_machine_dependent)
3231 /* Check for conflicts between the branch and the instructions
3232 before the candidate delay slot. */
3233 || nops_for_insn (history + 1, ip) > 0
3234 /* Check for conflicts between the swapped sequence and the
3235 target of the branch. */
3236 || nops_for_sequence (2, history + 1, ip, history) > 0
3237 /* We do not swap with a trap instruction, since it
3238 complicates trap handlers to have the trap
3239 instruction be in a delay slot. */
3240 || (prev_pinfo & INSN_TRAP)
3241 /* If the branch reads a register that the previous
3242 instruction sets, we can not swap. */
3243 || (! mips_opts.mips16
3244 && (prev_pinfo & INSN_WRITE_GPR_T)
3245 && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]),
3247 || (! mips_opts.mips16
3248 && (prev_pinfo & INSN_WRITE_GPR_D)
3249 && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]),
3251 || (mips_opts.mips16
3252 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
3254 (ip, MIPS16_EXTRACT_OPERAND (RX, history[0]),
3256 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
3258 (ip, MIPS16_EXTRACT_OPERAND (RY, history[0]),
3260 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
3262 (ip, MIPS16_EXTRACT_OPERAND (RZ, history[0]),
3264 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
3265 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
3266 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
3267 && insn_uses_reg (ip, RA, MIPS_GR_REG))
3268 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
3269 && insn_uses_reg (ip,
3270 MIPS16OP_EXTRACT_REG32R
3271 (history[0].insn_opcode),
3273 /* If the branch writes a register that the previous
3274 instruction sets, we can not swap (we know that
3275 branches write only to RD or to $31). */
3276 || (! mips_opts.mips16
3277 && (prev_pinfo & INSN_WRITE_GPR_T)
3278 && (((pinfo & INSN_WRITE_GPR_D)
3279 && (EXTRACT_OPERAND (RT, history[0])
3280 == EXTRACT_OPERAND (RD, *ip)))
3281 || ((pinfo & INSN_WRITE_GPR_31)
3282 && EXTRACT_OPERAND (RT, history[0]) == RA)))
3283 || (! mips_opts.mips16
3284 && (prev_pinfo & INSN_WRITE_GPR_D)
3285 && (((pinfo & INSN_WRITE_GPR_D)
3286 && (EXTRACT_OPERAND (RD, history[0])
3287 == EXTRACT_OPERAND (RD, *ip)))
3288 || ((pinfo & INSN_WRITE_GPR_31)
3289 && EXTRACT_OPERAND (RD, history[0]) == RA)))
3290 || (mips_opts.mips16
3291 && (pinfo & MIPS16_INSN_WRITE_31)
3292 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
3293 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
3294 && (MIPS16OP_EXTRACT_REG32R (history[0].insn_opcode)
3296 /* If the branch writes a register that the previous
3297 instruction reads, we can not swap (we know that
3298 branches only write to RD or to $31). */
3299 || (! mips_opts.mips16
3300 && (pinfo & INSN_WRITE_GPR_D)
3301 && insn_uses_reg (&history[0],
3302 EXTRACT_OPERAND (RD, *ip),
3304 || (! mips_opts.mips16
3305 && (pinfo & INSN_WRITE_GPR_31)
3306 && insn_uses_reg (&history[0], RA, MIPS_GR_REG))
3307 || (mips_opts.mips16
3308 && (pinfo & MIPS16_INSN_WRITE_31)
3309 && insn_uses_reg (&history[0], RA, MIPS_GR_REG))
3310 /* If one instruction sets a condition code and the
3311 other one uses a condition code, we can not swap. */
3312 || ((pinfo & INSN_READ_COND_CODE)
3313 && (prev_pinfo & INSN_WRITE_COND_CODE))
3314 || ((pinfo & INSN_WRITE_COND_CODE)
3315 && (prev_pinfo & INSN_READ_COND_CODE))
3316 /* If the previous instruction uses the PC, we can not
3318 || (mips_opts.mips16
3319 && (prev_pinfo & MIPS16_INSN_READ_PC))
3320 /* If the previous instruction had a fixup in mips16
3321 mode, we can not swap. This normally means that the
3322 previous instruction was a 4 byte branch anyhow. */
3323 || (mips_opts.mips16 && history[0].fixp[0])
3324 /* If the previous instruction is a sync, sync.l, or
3325 sync.p, we can not swap. */
3326 || (prev_pinfo & INSN_SYNC)
3327 /* If the previous instruction is an ERET or
3328 DERET, avoid the swap. */
3329 || (history[0].insn_opcode == INSN_ERET)
3330 || (history[0].insn_opcode == INSN_DERET))
3332 if (mips_opts.mips16
3333 && (pinfo & INSN_UNCOND_BRANCH_DELAY)
3334 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))
3335 && ISA_SUPPORTS_MIPS16E)
3337 /* Convert MIPS16 jr/jalr into a "compact" jump. */
3338 ip->insn_opcode |= 0x0080;
3340 insert_into_history (0, 1, ip);
3344 /* We could do even better for unconditional branches to
3345 portions of this object file; we could pick up the
3346 instruction at the destination, put it in the delay
3347 slot, and bump the destination address. */
3348 insert_into_history (0, 1, ip);
3354 if (mips_relax.sequence)
3355 mips_relax.sizes[mips_relax.sequence - 1] += 4;
3359 /* It looks like we can actually do the swap. */
3360 struct mips_cl_insn delay = history[0];
3361 if (mips_opts.mips16)
3363 know (delay.frag == ip->frag);
3364 move_insn (ip, delay.frag, delay.where);
3365 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
3367 else if (relaxed_branch)
3369 /* Add the delay slot instruction to the end of the
3370 current frag and shrink the fixed part of the
3371 original frag. If the branch occupies the tail of
3372 the latter, move it backwards to cover the gap. */
3373 delay.frag->fr_fix -= 4;
3374 if (delay.frag == ip->frag)
3375 move_insn (ip, ip->frag, ip->where - 4);
3376 add_fixed_insn (&delay);
3380 move_insn (&delay, ip->frag, ip->where);
3381 move_insn (ip, history[0].frag, history[0].where);
3385 insert_into_history (0, 1, &delay);
3388 /* If that was an unconditional branch, forget the previous
3389 insn information. */
3390 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
3392 /* Check for eret/deret before clearing history. */
3394 check_for_24k_errata (
3395 (struct mips_cl_insn *) &history[hndx_24k],
3397 mips_no_prev_insn ();
3400 else if (pinfo & INSN_COND_BRANCH_LIKELY)
3402 /* We don't yet optimize a branch likely. What we should do
3403 is look at the target, copy the instruction found there
3404 into the delay slot, and increment the branch to jump to
3405 the next instruction. */
3406 insert_into_history (0, 1, ip);
3412 insert_into_history (0, 1, ip);
3415 insert_into_history (0, 1, ip);
3418 check_for_24k_errata ((struct mips_cl_insn *) &history[hndx_24k],
3421 /* We just output an insn, so the next one doesn't have a label. */
3422 mips_clear_insn_labels ();
3425 /* Forget that there was any previous instruction or label. */
3428 mips_no_prev_insn (void)
3430 prev_nop_frag = NULL;
3431 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
3432 mips_clear_insn_labels ();
3435 /* This function must be called before we emit something other than
3436 instructions. It is like mips_no_prev_insn except that it inserts
3437 any NOPS that might be needed by previous instructions. */
3440 mips_emit_delays (void)
3442 if (! mips_opts.noreorder)
3444 int nops = nops_for_insn (history, NULL);
3448 add_fixed_insn (NOP_INSN);
3449 mips_move_labels ();
3452 mips_no_prev_insn ();
3455 /* Start a (possibly nested) noreorder block. */
3458 start_noreorder (void)
3460 if (mips_opts.noreorder == 0)
3465 /* None of the instructions before the .set noreorder can be moved. */
3466 for (i = 0; i < ARRAY_SIZE (history); i++)
3467 history[i].fixed_p = 1;
3469 /* Insert any nops that might be needed between the .set noreorder
3470 block and the previous instructions. We will later remove any
3471 nops that turn out not to be needed. */
3472 nops = nops_for_insn (history, NULL);
3475 if (mips_optimize != 0)
3477 /* Record the frag which holds the nop instructions, so
3478 that we can remove them if we don't need them. */
3479 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
3480 prev_nop_frag = frag_now;
3481 prev_nop_frag_holds = nops;
3482 prev_nop_frag_required = 0;
3483 prev_nop_frag_since = 0;
3486 for (; nops > 0; --nops)
3487 add_fixed_insn (NOP_INSN);
3489 /* Move on to a new frag, so that it is safe to simply
3490 decrease the size of prev_nop_frag. */
3491 frag_wane (frag_now);
3493 mips_move_labels ();
3495 mips16_mark_labels ();
3496 mips_clear_insn_labels ();
3498 mips_opts.noreorder++;
3499 mips_any_noreorder = 1;
3502 /* End a nested noreorder block. */
3505 end_noreorder (void)
3508 check_for_24k_errata (NULL, 0);
3510 mips_opts.noreorder--;
3511 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
3513 /* Commit to inserting prev_nop_frag_required nops and go back to
3514 handling nop insertion the .set reorder way. */
3515 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
3516 * (mips_opts.mips16 ? 2 : 4));
3517 insert_into_history (prev_nop_frag_since,
3518 prev_nop_frag_required, NOP_INSN);
3519 prev_nop_frag = NULL;
3523 /* Set up global variables for the start of a new macro. */
3528 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
3529 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
3530 && (history[0].insn_mo->pinfo
3531 & (INSN_UNCOND_BRANCH_DELAY
3532 | INSN_COND_BRANCH_DELAY
3533 | INSN_COND_BRANCH_LIKELY)) != 0);
3536 /* Given that a macro is longer than 4 bytes, return the appropriate warning
3537 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
3538 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
3541 macro_warning (relax_substateT subtype)
3543 if (subtype & RELAX_DELAY_SLOT)
3544 return _("Macro instruction expanded into multiple instructions"
3545 " in a branch delay slot");
3546 else if (subtype & RELAX_NOMACRO)
3547 return _("Macro instruction expanded into multiple instructions");
3552 /* Finish up a macro. Emit warnings as appropriate. */
3557 if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4)
3559 relax_substateT subtype;
3561 /* Set up the relaxation warning flags. */
3563 if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0])
3564 subtype |= RELAX_SECOND_LONGER;
3565 if (mips_opts.warn_about_macros)
3566 subtype |= RELAX_NOMACRO;
3567 if (mips_macro_warning.delay_slot_p)
3568 subtype |= RELAX_DELAY_SLOT;
3570 if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4)
3572 /* Either the macro has a single implementation or both
3573 implementations are longer than 4 bytes. Emit the
3575 const char *msg = macro_warning (subtype);
3577 as_warn ("%s", msg);
3581 /* One implementation might need a warning but the other
3582 definitely doesn't. */
3583 mips_macro_warning.first_frag->fr_subtype |= subtype;
3588 /* Read a macro's relocation codes from *ARGS and store them in *R.
3589 The first argument in *ARGS will be either the code for a single
3590 relocation or -1 followed by the three codes that make up a
3591 composite relocation. */
3594 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
3598 next = va_arg (*args, int);
3600 r[0] = (bfd_reloc_code_real_type) next;
3602 for (i = 0; i < 3; i++)
3603 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
3606 /* Build an instruction created by a macro expansion. This is passed
3607 a pointer to the count of instructions created so far, an
3608 expression, the name of the instruction to build, an operand format
3609 string, and corresponding arguments. */
3612 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
3614 const struct mips_opcode *mo;
3615 struct mips_cl_insn insn;
3616 bfd_reloc_code_real_type r[3];
3619 va_start (args, fmt);
3621 if (mips_opts.mips16)
3623 mips16_macro_build (ep, name, fmt, args);
3628 r[0] = BFD_RELOC_UNUSED;
3629 r[1] = BFD_RELOC_UNUSED;
3630 r[2] = BFD_RELOC_UNUSED;
3631 mo = (struct mips_opcode *) hash_find (op_hash, name);
3633 assert (strcmp (name, mo->name) == 0);
3637 /* Search until we get a match for NAME. It is assumed here that
3638 macros will never generate MDMX, MIPS-3D, or MT instructions. */
3639 if (strcmp (fmt, mo->args) == 0
3640 && mo->pinfo != INSN_MACRO
3641 && is_opcode_valid (mo, TRUE))
3646 assert (strcmp (name, mo->name) == 0);
3649 create_insn (&insn, mo);
3667 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
3672 /* Note that in the macro case, these arguments are already
3673 in MSB form. (When handling the instruction in the
3674 non-macro case, these arguments are sizes from which
3675 MSB values must be calculated.) */
3676 INSERT_OPERAND (INSMSB, insn, va_arg (args, int));
3682 /* Note that in the macro case, these arguments are already
3683 in MSBD form. (When handling the instruction in the
3684 non-macro case, these arguments are sizes from which
3685 MSBD values must be calculated.) */
3686 INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int));
3690 INSERT_OPERAND (SEQI, insn, va_arg (args, int));
3699 INSERT_OPERAND (BP, insn, va_arg (args, int));
3705 INSERT_OPERAND (RT, insn, va_arg (args, int));
3709 INSERT_OPERAND (CODE, insn, va_arg (args, int));
3714 INSERT_OPERAND (FT, insn, va_arg (args, int));
3720 INSERT_OPERAND (RD, insn, va_arg (args, int));
3725 int tmp = va_arg (args, int);
3727 INSERT_OPERAND (RT, insn, tmp);
3728 INSERT_OPERAND (RD, insn, tmp);
3734 INSERT_OPERAND (FS, insn, va_arg (args, int));
3741 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
3745 INSERT_OPERAND (FD, insn, va_arg (args, int));
3749 INSERT_OPERAND (CODE20, insn, va_arg (args, int));
3753 INSERT_OPERAND (CODE19, insn, va_arg (args, int));
3757 INSERT_OPERAND (CODE2, insn, va_arg (args, int));
3764 INSERT_OPERAND (RS, insn, va_arg (args, int));
3770 macro_read_relocs (&args, r);
3771 assert (*r == BFD_RELOC_GPREL16
3772 || *r == BFD_RELOC_MIPS_LITERAL
3773 || *r == BFD_RELOC_MIPS_HIGHER
3774 || *r == BFD_RELOC_HI16_S
3775 || *r == BFD_RELOC_LO16
3776 || *r == BFD_RELOC_MIPS_GOT16
3777 || *r == BFD_RELOC_MIPS_CALL16
3778 || *r == BFD_RELOC_MIPS_GOT_DISP
3779 || *r == BFD_RELOC_MIPS_GOT_PAGE
3780 || *r == BFD_RELOC_MIPS_GOT_OFST
3781 || *r == BFD_RELOC_MIPS_GOT_LO16
3782 || *r == BFD_RELOC_MIPS_CALL_LO16);
3786 macro_read_relocs (&args, r);
3788 && (ep->X_op == O_constant
3789 || (ep->X_op == O_symbol
3790 && (*r == BFD_RELOC_MIPS_HIGHEST
3791 || *r == BFD_RELOC_HI16_S
3792 || *r == BFD_RELOC_HI16
3793 || *r == BFD_RELOC_GPREL16
3794 || *r == BFD_RELOC_MIPS_GOT_HI16
3795 || *r == BFD_RELOC_MIPS_CALL_HI16))));
3799 assert (ep != NULL);
3802 * This allows macro() to pass an immediate expression for
3803 * creating short branches without creating a symbol.
3805 * We don't allow branch relaxation for these branches, as
3806 * they should only appear in ".set nomacro" anyway.
3808 if (ep->X_op == O_constant)
3810 if ((ep->X_add_number & 3) != 0)
3811 as_bad (_("branch to misaligned address (0x%lx)"),
3812 (unsigned long) ep->X_add_number);
3813 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
3814 as_bad (_("branch address range overflow (0x%lx)"),
3815 (unsigned long) ep->X_add_number);
3816 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
3820 *r = BFD_RELOC_16_PCREL_S2;
3824 assert (ep != NULL);
3825 *r = BFD_RELOC_MIPS_JMP;
3829 INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long));
3833 INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long));
3842 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3844 append_insn (&insn, ep, r);
3848 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
3851 struct mips_opcode *mo;
3852 struct mips_cl_insn insn;
3853 bfd_reloc_code_real_type r[3]
3854 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3856 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
3858 assert (strcmp (name, mo->name) == 0);
3860 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
3864 assert (strcmp (name, mo->name) == 0);
3867 create_insn (&insn, mo);
3885 MIPS16_INSERT_OPERAND (RY, insn, va_arg (args, int));
3890 MIPS16_INSERT_OPERAND (RX, insn, va_arg (args, int));
3894 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (args, int));
3898 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (args, int));
3908 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (args, int));
3915 regno = va_arg (args, int);
3916 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
3917 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
3938 assert (ep != NULL);
3940 if (ep->X_op != O_constant)
3941 *r = (int) BFD_RELOC_UNUSED + c;
3944 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
3945 FALSE, &insn.insn_opcode, &insn.use_extend,
3948 *r = BFD_RELOC_UNUSED;
3954 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (args, int));
3961 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3963 append_insn (&insn, ep, r);
3967 * Sign-extend 32-bit mode constants that have bit 31 set and all
3968 * higher bits unset.
3971 normalize_constant_expr (expressionS *ex)
3973 if (ex->X_op == O_constant
3974 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
3975 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
3980 * Sign-extend 32-bit mode address offsets that have bit 31 set and
3981 * all higher bits unset.
3984 normalize_address_expr (expressionS *ex)
3986 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
3987 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
3988 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
3989 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
3994 * Generate a "jalr" instruction with a relocation hint to the called
3995 * function. This occurs in NewABI PIC code.
3998 macro_build_jalr (expressionS *ep)
4007 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
4009 fix_new_exp (frag_now, f - frag_now->fr_literal,
4010 4, ep, FALSE, BFD_RELOC_MIPS_JALR);
4014 * Generate a "lui" instruction.
4017 macro_build_lui (expressionS *ep, int regnum)
4019 expressionS high_expr;
4020 const struct mips_opcode *mo;
4021 struct mips_cl_insn insn;
4022 bfd_reloc_code_real_type r[3]
4023 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
4024 const char *name = "lui";
4025 const char *fmt = "t,u";
4027 assert (! mips_opts.mips16);
4031 if (high_expr.X_op == O_constant)
4033 /* We can compute the instruction now without a relocation entry. */
4034 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
4036 *r = BFD_RELOC_UNUSED;
4040 assert (ep->X_op == O_symbol);
4041 /* _gp_disp is a special case, used from s_cpload.
4042 __gnu_local_gp is used if mips_no_shared. */
4043 assert (mips_pic == NO_PIC
4045 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
4046 || (! mips_in_shared
4047 && strcmp (S_GET_NAME (ep->X_add_symbol),
4048 "__gnu_local_gp") == 0));
4049 *r = BFD_RELOC_HI16_S;
4052 mo = hash_find (op_hash, name);
4053 assert (strcmp (name, mo->name) == 0);
4054 assert (strcmp (fmt, mo->args) == 0);
4055 create_insn (&insn, mo);
4057 insn.insn_opcode = insn.insn_mo->match;
4058 INSERT_OPERAND (RT, insn, regnum);
4059 if (*r == BFD_RELOC_UNUSED)
4061 insn.insn_opcode |= high_expr.X_add_number;
4062 append_insn (&insn, NULL, r);
4065 append_insn (&insn, &high_expr, r);
4068 /* Generate a sequence of instructions to do a load or store from a constant
4069 offset off of a base register (breg) into/from a target register (treg),
4070 using AT if necessary. */
4072 macro_build_ldst_constoffset (expressionS *ep, const char *op,
4073 int treg, int breg, int dbl)
4075 assert (ep->X_op == O_constant);
4077 /* Sign-extending 32-bit constants makes their handling easier. */
4079 normalize_constant_expr (ep);
4081 /* Right now, this routine can only handle signed 32-bit constants. */
4082 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
4083 as_warn (_("operand overflow"));
4085 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
4087 /* Signed 16-bit offset will fit in the op. Easy! */
4088 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
4092 /* 32-bit offset, need multiple instructions and AT, like:
4093 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
4094 addu $tempreg,$tempreg,$breg
4095 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
4096 to handle the complete offset. */
4097 macro_build_lui (ep, AT);
4098 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
4099 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
4102 as_bad (_("Macro used $at after \".set noat\""));
4107 * Generates code to set the $at register to true (one)
4108 * if reg is less than the immediate expression.
4111 set_at (int reg, int unsignedp)
4113 if (imm_expr.X_op == O_constant
4114 && imm_expr.X_add_number >= -0x8000
4115 && imm_expr.X_add_number < 0x8000)
4116 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
4117 AT, reg, BFD_RELOC_LO16);
4120 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4121 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
4125 /* Warn if an expression is not a constant. */
4128 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
4130 if (ex->X_op == O_big)
4131 as_bad (_("unsupported large constant"));
4132 else if (ex->X_op != O_constant)
4133 as_bad (_("Instruction %s requires absolute expression"),
4136 if (HAVE_32BIT_GPRS)
4137 normalize_constant_expr (ex);
4140 /* Count the leading zeroes by performing a binary chop. This is a
4141 bulky bit of source, but performance is a LOT better for the
4142 majority of values than a simple loop to count the bits:
4143 for (lcnt = 0; (lcnt < 32); lcnt++)
4144 if ((v) & (1 << (31 - lcnt)))
4146 However it is not code size friendly, and the gain will drop a bit
4147 on certain cached systems.
4149 #define COUNT_TOP_ZEROES(v) \
4150 (((v) & ~0xffff) == 0 \
4151 ? ((v) & ~0xff) == 0 \
4152 ? ((v) & ~0xf) == 0 \
4153 ? ((v) & ~0x3) == 0 \
4154 ? ((v) & ~0x1) == 0 \
4159 : ((v) & ~0x7) == 0 \
4162 : ((v) & ~0x3f) == 0 \
4163 ? ((v) & ~0x1f) == 0 \
4166 : ((v) & ~0x7f) == 0 \
4169 : ((v) & ~0xfff) == 0 \
4170 ? ((v) & ~0x3ff) == 0 \
4171 ? ((v) & ~0x1ff) == 0 \
4174 : ((v) & ~0x7ff) == 0 \
4177 : ((v) & ~0x3fff) == 0 \
4178 ? ((v) & ~0x1fff) == 0 \
4181 : ((v) & ~0x7fff) == 0 \
4184 : ((v) & ~0xffffff) == 0 \
4185 ? ((v) & ~0xfffff) == 0 \
4186 ? ((v) & ~0x3ffff) == 0 \
4187 ? ((v) & ~0x1ffff) == 0 \
4190 : ((v) & ~0x7ffff) == 0 \
4193 : ((v) & ~0x3fffff) == 0 \
4194 ? ((v) & ~0x1fffff) == 0 \
4197 : ((v) & ~0x7fffff) == 0 \
4200 : ((v) & ~0xfffffff) == 0 \
4201 ? ((v) & ~0x3ffffff) == 0 \
4202 ? ((v) & ~0x1ffffff) == 0 \
4205 : ((v) & ~0x7ffffff) == 0 \
4208 : ((v) & ~0x3fffffff) == 0 \
4209 ? ((v) & ~0x1fffffff) == 0 \
4212 : ((v) & ~0x7fffffff) == 0 \
4217 * This routine generates the least number of instructions necessary to load
4218 * an absolute expression value into a register.
4221 load_register (int reg, expressionS *ep, int dbl)
4224 expressionS hi32, lo32;
4226 if (ep->X_op != O_big)
4228 assert (ep->X_op == O_constant);
4230 /* Sign-extending 32-bit constants makes their handling easier. */
4232 normalize_constant_expr (ep);
4234 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
4236 /* We can handle 16 bit signed values with an addiu to
4237 $zero. No need to ever use daddiu here, since $zero and
4238 the result are always correct in 32 bit mode. */
4239 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4242 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
4244 /* We can handle 16 bit unsigned values with an ori to
4246 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
4249 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
4251 /* 32 bit values require an lui. */
4252 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16);
4253 if ((ep->X_add_number & 0xffff) != 0)
4254 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
4259 /* The value is larger than 32 bits. */
4261 if (!dbl || HAVE_32BIT_GPRS)
4265 sprintf_vma (value, ep->X_add_number);
4266 as_bad (_("Number (0x%s) larger than 32 bits"), value);
4267 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4271 if (ep->X_op != O_big)
4274 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
4275 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
4276 hi32.X_add_number &= 0xffffffff;
4278 lo32.X_add_number &= 0xffffffff;
4282 assert (ep->X_add_number > 2);
4283 if (ep->X_add_number == 3)
4284 generic_bignum[3] = 0;
4285 else if (ep->X_add_number > 4)
4286 as_bad (_("Number larger than 64 bits"));
4287 lo32.X_op = O_constant;
4288 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
4289 hi32.X_op = O_constant;
4290 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
4293 if (hi32.X_add_number == 0)
4298 unsigned long hi, lo;
4300 if (hi32.X_add_number == (offsetT) 0xffffffff)
4302 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
4304 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4307 if (lo32.X_add_number & 0x80000000)
4309 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
4310 if (lo32.X_add_number & 0xffff)
4311 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
4316 /* Check for 16bit shifted constant. We know that hi32 is
4317 non-zero, so start the mask on the first bit of the hi32
4322 unsigned long himask, lomask;
4326 himask = 0xffff >> (32 - shift);
4327 lomask = (0xffff << shift) & 0xffffffff;
4331 himask = 0xffff << (shift - 32);
4334 if ((hi32.X_add_number & ~(offsetT) himask) == 0
4335 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
4339 tmp.X_op = O_constant;
4341 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
4342 | (lo32.X_add_number >> shift));
4344 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
4345 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
4346 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<",
4347 reg, reg, (shift >= 32) ? shift - 32 : shift);
4352 while (shift <= (64 - 16));
4354 /* Find the bit number of the lowest one bit, and store the
4355 shifted value in hi/lo. */
4356 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
4357 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
4361 while ((lo & 1) == 0)
4366 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
4372 while ((hi & 1) == 0)
4381 /* Optimize if the shifted value is a (power of 2) - 1. */
4382 if ((hi == 0 && ((lo + 1) & lo) == 0)
4383 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
4385 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
4390 /* This instruction will set the register to be all
4392 tmp.X_op = O_constant;
4393 tmp.X_add_number = (offsetT) -1;
4394 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4398 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<",
4399 reg, reg, (bit >= 32) ? bit - 32 : bit);
4401 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<",
4402 reg, reg, (shift >= 32) ? shift - 32 : shift);
4407 /* Sign extend hi32 before calling load_register, because we can
4408 generally get better code when we load a sign extended value. */
4409 if ((hi32.X_add_number & 0x80000000) != 0)
4410 hi32.X_add_number |= ~(offsetT) 0xffffffff;
4411 load_register (reg, &hi32, 0);
4414 if ((lo32.X_add_number & 0xffff0000) == 0)
4418 macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0);
4426 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
4428 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
4429 macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0);
4435 macro_build (NULL, "dsll", "d,w,<", reg, freg, 16);
4439 mid16.X_add_number >>= 16;
4440 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
4441 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4444 if ((lo32.X_add_number & 0xffff) != 0)
4445 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
4449 load_delay_nop (void)
4451 if (!gpr_interlocks)
4452 macro_build (NULL, "nop", "");
4455 /* Load an address into a register. */
4458 load_address (int reg, expressionS *ep, int *used_at)
4460 if (ep->X_op != O_constant
4461 && ep->X_op != O_symbol)
4463 as_bad (_("expression too complex"));
4464 ep->X_op = O_constant;
4467 if (ep->X_op == O_constant)
4469 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
4473 if (mips_pic == NO_PIC)
4475 /* If this is a reference to a GP relative symbol, we want
4476 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4478 lui $reg,<sym> (BFD_RELOC_HI16_S)
4479 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4480 If we have an addend, we always use the latter form.
4482 With 64bit address space and a usable $at we want
4483 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4484 lui $at,<sym> (BFD_RELOC_HI16_S)
4485 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4486 daddiu $at,<sym> (BFD_RELOC_LO16)
4490 If $at is already in use, we use a path which is suboptimal
4491 on superscalar processors.
4492 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4493 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4495 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
4497 daddiu $reg,<sym> (BFD_RELOC_LO16)
4499 For GP relative symbols in 64bit address space we can use
4500 the same sequence as in 32bit address space. */
4501 if (HAVE_64BIT_SYMBOLS)
4503 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
4504 && !nopic_need_relax (ep->X_add_symbol, 1))
4506 relax_start (ep->X_add_symbol);
4507 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4508 mips_gp_register, BFD_RELOC_GPREL16);
4512 if (*used_at == 0 && mips_opts.at)
4514 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
4515 macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S);
4516 macro_build (ep, "daddiu", "t,r,j", reg, reg,
4517 BFD_RELOC_MIPS_HIGHER);
4518 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
4519 macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0);
4520 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
4525 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
4526 macro_build (ep, "daddiu", "t,r,j", reg, reg,
4527 BFD_RELOC_MIPS_HIGHER);
4528 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4529 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
4530 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4531 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
4534 if (mips_relax.sequence)
4539 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
4540 && !nopic_need_relax (ep->X_add_symbol, 1))
4542 relax_start (ep->X_add_symbol);
4543 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4544 mips_gp_register, BFD_RELOC_GPREL16);
4547 macro_build_lui (ep, reg);
4548 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
4549 reg, reg, BFD_RELOC_LO16);
4550 if (mips_relax.sequence)
4554 else if (!mips_big_got)
4558 /* If this is a reference to an external symbol, we want
4559 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4561 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4563 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4564 If there is a constant, it must be added in after.
4566 If we have NewABI, we want
4567 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4568 unless we're referencing a global symbol with a non-zero
4569 offset, in which case cst must be added separately. */
4572 if (ep->X_add_number)
4574 ex.X_add_number = ep->X_add_number;
4575 ep->X_add_number = 0;
4576 relax_start (ep->X_add_symbol);
4577 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4578 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4579 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4580 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4581 ex.X_op = O_constant;
4582 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
4583 reg, reg, BFD_RELOC_LO16);
4584 ep->X_add_number = ex.X_add_number;
4587 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4588 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4589 if (mips_relax.sequence)
4594 ex.X_add_number = ep->X_add_number;
4595 ep->X_add_number = 0;
4596 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4597 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4599 relax_start (ep->X_add_symbol);
4601 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4605 if (ex.X_add_number != 0)
4607 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4608 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4609 ex.X_op = O_constant;
4610 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
4611 reg, reg, BFD_RELOC_LO16);
4615 else if (mips_big_got)
4619 /* This is the large GOT case. If this is a reference to an
4620 external symbol, we want
4621 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4623 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
4625 Otherwise, for a reference to a local symbol in old ABI, we want
4626 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4628 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4629 If there is a constant, it must be added in after.
4631 In the NewABI, for local symbols, with or without offsets, we want:
4632 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4633 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4637 ex.X_add_number = ep->X_add_number;
4638 ep->X_add_number = 0;
4639 relax_start (ep->X_add_symbol);
4640 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4641 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4642 reg, reg, mips_gp_register);
4643 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4644 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4645 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4646 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4647 else if (ex.X_add_number)
4649 ex.X_op = O_constant;
4650 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4654 ep->X_add_number = ex.X_add_number;
4656 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4657 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
4658 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4659 BFD_RELOC_MIPS_GOT_OFST);
4664 ex.X_add_number = ep->X_add_number;
4665 ep->X_add_number = 0;
4666 relax_start (ep->X_add_symbol);
4667 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4668 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4669 reg, reg, mips_gp_register);
4670 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4671 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4673 if (reg_needs_delay (mips_gp_register))
4675 /* We need a nop before loading from $gp. This special
4676 check is required because the lui which starts the main
4677 instruction stream does not refer to $gp, and so will not
4678 insert the nop which may be required. */
4679 macro_build (NULL, "nop", "");
4681 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4682 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4684 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4688 if (ex.X_add_number != 0)
4690 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4691 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4692 ex.X_op = O_constant;
4693 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4701 if (!mips_opts.at && *used_at == 1)
4702 as_bad (_("Macro used $at after \".set noat\""));
4705 /* Move the contents of register SOURCE into register DEST. */
4708 move_register (int dest, int source)
4710 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
4714 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4715 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4716 The two alternatives are:
4718 Global symbol Local sybmol
4719 ------------- ------------
4720 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4722 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4724 load_got_offset emits the first instruction and add_got_offset
4725 emits the second for a 16-bit offset or add_got_offset_hilo emits
4726 a sequence to add a 32-bit offset using a scratch register. */
4729 load_got_offset (int dest, expressionS *local)
4734 global.X_add_number = 0;
4736 relax_start (local->X_add_symbol);
4737 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4738 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4740 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4741 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4746 add_got_offset (int dest, expressionS *local)
4750 global.X_op = O_constant;
4751 global.X_op_symbol = NULL;
4752 global.X_add_symbol = NULL;
4753 global.X_add_number = local->X_add_number;
4755 relax_start (local->X_add_symbol);
4756 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
4757 dest, dest, BFD_RELOC_LO16);
4759 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
4764 add_got_offset_hilo (int dest, expressionS *local, int tmp)
4767 int hold_mips_optimize;
4769 global.X_op = O_constant;
4770 global.X_op_symbol = NULL;
4771 global.X_add_symbol = NULL;
4772 global.X_add_number = local->X_add_number;
4774 relax_start (local->X_add_symbol);
4775 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
4777 /* Set mips_optimize around the lui instruction to avoid
4778 inserting an unnecessary nop after the lw. */
4779 hold_mips_optimize = mips_optimize;
4781 macro_build_lui (&global, tmp);
4782 mips_optimize = hold_mips_optimize;
4783 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
4786 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
4791 * This routine implements the seemingly endless macro or synthesized
4792 * instructions and addressing modes in the mips assembly language. Many
4793 * of these macros are simple and are similar to each other. These could
4794 * probably be handled by some kind of table or grammar approach instead of
4795 * this verbose method. Others are not simple macros but are more like
4796 * optimizing code generation.
4797 * One interesting optimization is when several store macros appear
4798 * consecutively that would load AT with the upper half of the same address.
4799 * The ensuing load upper instructions are ommited. This implies some kind
4800 * of global optimization. We currently only optimize within a single macro.
4801 * For many of the load and store macros if the address is specified as a
4802 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4803 * first load register 'at' with zero and use it as the base register. The
4804 * mips assembler simply uses register $zero. Just one tiny optimization
4808 macro (struct mips_cl_insn *ip)
4810 unsigned int treg, sreg, dreg, breg;
4811 unsigned int tempreg;
4826 bfd_reloc_code_real_type r;
4827 int hold_mips_optimize;
4829 assert (! mips_opts.mips16);
4831 treg = (ip->insn_opcode >> 16) & 0x1f;
4832 dreg = (ip->insn_opcode >> 11) & 0x1f;
4833 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
4834 mask = ip->insn_mo->mask;
4836 expr1.X_op = O_constant;
4837 expr1.X_op_symbol = NULL;
4838 expr1.X_add_symbol = NULL;
4839 expr1.X_add_number = 1;
4853 expr1.X_add_number = 8;
4854 macro_build (&expr1, "bgez", "s,p", sreg);
4856 macro_build (NULL, "nop", "", 0);
4858 move_register (dreg, sreg);
4859 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
4882 if (imm_expr.X_op == O_constant
4883 && imm_expr.X_add_number >= -0x8000
4884 && imm_expr.X_add_number < 0x8000)
4886 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
4890 load_register (AT, &imm_expr, dbl);
4891 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4910 if (imm_expr.X_op == O_constant
4911 && imm_expr.X_add_number >= 0
4912 && imm_expr.X_add_number < 0x10000)
4914 if (mask != M_NOR_I)
4915 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
4918 macro_build (&imm_expr, "ori", "t,r,i",
4919 treg, sreg, BFD_RELOC_LO16);
4920 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
4926 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4927 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4931 switch (imm_expr.X_add_number)
4934 macro_build (NULL, "nop", "");
4937 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
4940 macro_build (NULL, "balign", "t,s,2", treg, sreg,
4941 (int)imm_expr.X_add_number);
4960 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4962 macro_build (&offset_expr, s, "s,t,p", sreg, 0);
4966 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4967 macro_build (&offset_expr, s, "s,t,p", sreg, AT);
4975 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
4980 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg);
4984 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
4985 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4991 /* check for > max integer */
4992 maxnum = 0x7fffffff;
4993 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5000 if (imm_expr.X_op == O_constant
5001 && imm_expr.X_add_number >= maxnum
5002 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5005 /* result is always false */
5007 macro_build (NULL, "nop", "", 0);
5009 macro_build (&offset_expr, "bnel", "s,t,p", 0, 0);
5012 if (imm_expr.X_op != O_constant)
5013 as_bad (_("Unsupported large constant"));
5014 ++imm_expr.X_add_number;
5018 if (mask == M_BGEL_I)
5020 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5022 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
5025 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5027 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
5030 maxnum = 0x7fffffff;
5031 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5038 maxnum = - maxnum - 1;
5039 if (imm_expr.X_op == O_constant
5040 && imm_expr.X_add_number <= maxnum
5041 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5044 /* result is always true */
5045 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
5046 macro_build (&offset_expr, "b", "p");
5051 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
5061 macro_build (&offset_expr, likely ? "beql" : "beq",
5066 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
5067 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
5075 && imm_expr.X_op == O_constant
5076 && imm_expr.X_add_number == (offsetT) 0xffffffff))
5078 if (imm_expr.X_op != O_constant)
5079 as_bad (_("Unsupported large constant"));
5080 ++imm_expr.X_add_number;
5084 if (mask == M_BGEUL_I)
5086 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5088 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5090 macro_build (&offset_expr, likely ? "bnel" : "bne",
5096 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
5104 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
5109 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg);
5113 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
5114 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
5122 macro_build (&offset_expr, likely ? "bnel" : "bne",
5129 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
5130 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
5138 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
5143 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg);
5147 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
5148 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
5154 maxnum = 0x7fffffff;
5155 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5162 if (imm_expr.X_op == O_constant
5163 && imm_expr.X_add_number >= maxnum
5164 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5166 if (imm_expr.X_op != O_constant)
5167 as_bad (_("Unsupported large constant"));
5168 ++imm_expr.X_add_number;
5172 if (mask == M_BLTL_I)
5174 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5176 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
5179 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5181 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
5186 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
5194 macro_build (&offset_expr, likely ? "beql" : "beq",
5201 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
5202 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
5210 && imm_expr.X_op == O_constant
5211 && imm_expr.X_add_number == (offsetT) 0xffffffff))
5213 if (imm_expr.X_op != O_constant)
5214 as_bad (_("Unsupported large constant"));
5215 ++imm_expr.X_add_number;
5219 if (mask == M_BLTUL_I)
5221 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5223 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5225 macro_build (&offset_expr, likely ? "beql" : "beq",
5231 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
5239 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
5244 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg);
5248 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
5249 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
5259 macro_build (&offset_expr, likely ? "bnel" : "bne",
5264 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
5265 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
5273 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5275 as_bad (_("Unsupported large constant"));
5280 pos = (unsigned long) imm_expr.X_add_number;
5281 size = (unsigned long) imm2_expr.X_add_number;
5286 as_bad (_("Improper position (%lu)"), pos);
5289 if (size == 0 || size > 64
5290 || (pos + size - 1) > 63)
5292 as_bad (_("Improper extract size (%lu, position %lu)"),
5297 if (size <= 32 && pos < 32)
5302 else if (size <= 32)
5312 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1);
5321 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5323 as_bad (_("Unsupported large constant"));
5328 pos = (unsigned long) imm_expr.X_add_number;
5329 size = (unsigned long) imm2_expr.X_add_number;
5334 as_bad (_("Improper position (%lu)"), pos);
5337 if (size == 0 || size > 64
5338 || (pos + size - 1) > 63)
5340 as_bad (_("Improper insert size (%lu, position %lu)"),
5345 if (pos < 32 && (pos + size - 1) < 32)
5360 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
5361 (int) (pos + size - 1));
5377 as_warn (_("Divide by zero."));
5379 macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
5381 macro_build (NULL, "break", "c", 7);
5388 macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
5389 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
5393 expr1.X_add_number = 8;
5394 macro_build (&expr1, "bne", "s,t,p", treg, 0);
5395 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
5396 macro_build (NULL, "break", "c", 7);
5398 expr1.X_add_number = -1;
5400 load_register (AT, &expr1, dbl);
5401 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
5402 macro_build (&expr1, "bne", "s,t,p", treg, AT);
5405 expr1.X_add_number = 1;
5406 load_register (AT, &expr1, dbl);
5407 macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31);
5411 expr1.X_add_number = 0x80000000;
5412 macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16);
5416 macro_build (NULL, "teq", "s,t,q", sreg, AT, 6);
5417 /* We want to close the noreorder block as soon as possible, so
5418 that later insns are available for delay slot filling. */
5423 expr1.X_add_number = 8;
5424 macro_build (&expr1, "bne", "s,t,p", sreg, AT);
5425 macro_build (NULL, "nop", "", 0);
5427 /* We want to close the noreorder block as soon as possible, so
5428 that later insns are available for delay slot filling. */
5431 macro_build (NULL, "break", "c", 6);
5433 macro_build (NULL, s, "d", dreg);
5472 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5474 as_warn (_("Divide by zero."));
5476 macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
5478 macro_build (NULL, "break", "c", 7);
5481 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5483 if (strcmp (s2, "mflo") == 0)
5484 move_register (dreg, sreg);
5486 move_register (dreg, 0);
5489 if (imm_expr.X_op == O_constant
5490 && imm_expr.X_add_number == -1
5491 && s[strlen (s) - 1] != 'u')
5493 if (strcmp (s2, "mflo") == 0)
5495 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
5498 move_register (dreg, 0);
5503 load_register (AT, &imm_expr, dbl);
5504 macro_build (NULL, s, "z,s,t", sreg, AT);
5505 macro_build (NULL, s2, "d", dreg);
5527 macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
5528 macro_build (NULL, s, "z,s,t", sreg, treg);
5529 /* We want to close the noreorder block as soon as possible, so
5530 that later insns are available for delay slot filling. */
5535 expr1.X_add_number = 8;
5536 macro_build (&expr1, "bne", "s,t,p", treg, 0);
5537 macro_build (NULL, s, "z,s,t", sreg, treg);
5539 /* We want to close the noreorder block as soon as possible, so
5540 that later insns are available for delay slot filling. */
5542 macro_build (NULL, "break", "c", 7);
5544 macro_build (NULL, s2, "d", dreg);
5556 /* Load the address of a symbol into a register. If breg is not
5557 zero, we then add a base register to it. */
5559 if (dbl && HAVE_32BIT_GPRS)
5560 as_warn (_("dla used to load 32-bit register"));
5562 if (! dbl && HAVE_64BIT_OBJECTS)
5563 as_warn (_("la used to load 64-bit address"));
5565 if (offset_expr.X_op == O_constant
5566 && offset_expr.X_add_number >= -0x8000
5567 && offset_expr.X_add_number < 0x8000)
5569 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
5570 "t,r,j", treg, sreg, BFD_RELOC_LO16);
5574 if (mips_opts.at && (treg == breg))
5584 if (offset_expr.X_op != O_symbol
5585 && offset_expr.X_op != O_constant)
5587 as_bad (_("expression too complex"));
5588 offset_expr.X_op = O_constant;
5591 if (offset_expr.X_op == O_constant)
5592 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
5593 else if (mips_pic == NO_PIC)
5595 /* If this is a reference to a GP relative symbol, we want
5596 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5598 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5599 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5600 If we have a constant, we need two instructions anyhow,
5601 so we may as well always use the latter form.
5603 With 64bit address space and a usable $at we want
5604 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5605 lui $at,<sym> (BFD_RELOC_HI16_S)
5606 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5607 daddiu $at,<sym> (BFD_RELOC_LO16)
5609 daddu $tempreg,$tempreg,$at
5611 If $at is already in use, we use a path which is suboptimal
5612 on superscalar processors.
5613 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5614 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5616 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5618 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
5620 For GP relative symbols in 64bit address space we can use
5621 the same sequence as in 32bit address space. */
5622 if (HAVE_64BIT_SYMBOLS)
5624 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5625 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5627 relax_start (offset_expr.X_add_symbol);
5628 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5629 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5633 if (used_at == 0 && mips_opts.at)
5635 macro_build (&offset_expr, "lui", "t,u",
5636 tempreg, BFD_RELOC_MIPS_HIGHEST);
5637 macro_build (&offset_expr, "lui", "t,u",
5638 AT, BFD_RELOC_HI16_S);
5639 macro_build (&offset_expr, "daddiu", "t,r,j",
5640 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5641 macro_build (&offset_expr, "daddiu", "t,r,j",
5642 AT, AT, BFD_RELOC_LO16);
5643 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
5644 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
5649 macro_build (&offset_expr, "lui", "t,u",
5650 tempreg, BFD_RELOC_MIPS_HIGHEST);
5651 macro_build (&offset_expr, "daddiu", "t,r,j",
5652 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5653 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5654 macro_build (&offset_expr, "daddiu", "t,r,j",
5655 tempreg, tempreg, BFD_RELOC_HI16_S);
5656 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5657 macro_build (&offset_expr, "daddiu", "t,r,j",
5658 tempreg, tempreg, BFD_RELOC_LO16);
5661 if (mips_relax.sequence)
5666 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5667 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5669 relax_start (offset_expr.X_add_symbol);
5670 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5671 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5674 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
5675 as_bad (_("offset too large"));
5676 macro_build_lui (&offset_expr, tempreg);
5677 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5678 tempreg, tempreg, BFD_RELOC_LO16);
5679 if (mips_relax.sequence)
5683 else if (!mips_big_got && !HAVE_NEWABI)
5685 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5687 /* If this is a reference to an external symbol, and there
5688 is no constant, we want
5689 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5690 or for lca or if tempreg is PIC_CALL_REG
5691 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5692 For a local symbol, we want
5693 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5695 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5697 If we have a small constant, and this is a reference to
5698 an external symbol, we want
5699 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5701 addiu $tempreg,$tempreg,<constant>
5702 For a local symbol, we want the same instruction
5703 sequence, but we output a BFD_RELOC_LO16 reloc on the
5706 If we have a large constant, and this is a reference to
5707 an external symbol, we want
5708 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5709 lui $at,<hiconstant>
5710 addiu $at,$at,<loconstant>
5711 addu $tempreg,$tempreg,$at
5712 For a local symbol, we want the same instruction
5713 sequence, but we output a BFD_RELOC_LO16 reloc on the
5717 if (offset_expr.X_add_number == 0)
5719 if (mips_pic == SVR4_PIC
5721 && (call || tempreg == PIC_CALL_REG))
5722 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
5724 relax_start (offset_expr.X_add_symbol);
5725 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5726 lw_reloc_type, mips_gp_register);
5729 /* We're going to put in an addu instruction using
5730 tempreg, so we may as well insert the nop right
5735 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5736 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
5738 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5739 tempreg, tempreg, BFD_RELOC_LO16);
5741 /* FIXME: If breg == 0, and the next instruction uses
5742 $tempreg, then if this variant case is used an extra
5743 nop will be generated. */
5745 else if (offset_expr.X_add_number >= -0x8000
5746 && offset_expr.X_add_number < 0x8000)
5748 load_got_offset (tempreg, &offset_expr);
5750 add_got_offset (tempreg, &offset_expr);
5754 expr1.X_add_number = offset_expr.X_add_number;
5755 offset_expr.X_add_number =
5756 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
5757 load_got_offset (tempreg, &offset_expr);
5758 offset_expr.X_add_number = expr1.X_add_number;
5759 /* If we are going to add in a base register, and the
5760 target register and the base register are the same,
5761 then we are using AT as a temporary register. Since
5762 we want to load the constant into AT, we add our
5763 current AT (from the global offset table) and the
5764 register into the register now, and pretend we were
5765 not using a base register. */
5769 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5774 add_got_offset_hilo (tempreg, &offset_expr, AT);
5778 else if (!mips_big_got && HAVE_NEWABI)
5780 int add_breg_early = 0;
5782 /* If this is a reference to an external, and there is no
5783 constant, or local symbol (*), with or without a
5785 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5786 or for lca or if tempreg is PIC_CALL_REG
5787 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5789 If we have a small constant, and this is a reference to
5790 an external symbol, we want
5791 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5792 addiu $tempreg,$tempreg,<constant>
5794 If we have a large constant, and this is a reference to
5795 an external symbol, we want
5796 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5797 lui $at,<hiconstant>
5798 addiu $at,$at,<loconstant>
5799 addu $tempreg,$tempreg,$at
5801 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5802 local symbols, even though it introduces an additional
5805 if (offset_expr.X_add_number)
5807 expr1.X_add_number = offset_expr.X_add_number;
5808 offset_expr.X_add_number = 0;
5810 relax_start (offset_expr.X_add_symbol);
5811 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5812 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5814 if (expr1.X_add_number >= -0x8000
5815 && expr1.X_add_number < 0x8000)
5817 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5818 tempreg, tempreg, BFD_RELOC_LO16);
5820 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
5824 /* If we are going to add in a base register, and the
5825 target register and the base register are the same,
5826 then we are using AT as a temporary register. Since
5827 we want to load the constant into AT, we add our
5828 current AT (from the global offset table) and the
5829 register into the register now, and pretend we were
5830 not using a base register. */
5835 assert (tempreg == AT);
5836 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5842 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5843 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5849 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5852 offset_expr.X_add_number = expr1.X_add_number;
5854 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5855 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5858 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5859 treg, tempreg, breg);
5865 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
5867 relax_start (offset_expr.X_add_symbol);
5868 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5869 BFD_RELOC_MIPS_CALL16, mips_gp_register);
5871 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5872 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5877 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5878 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5881 else if (mips_big_got && !HAVE_NEWABI)
5884 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5885 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5886 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5888 /* This is the large GOT case. If this is a reference to an
5889 external symbol, and there is no constant, we want
5890 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5891 addu $tempreg,$tempreg,$gp
5892 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5893 or for lca or if tempreg is PIC_CALL_REG
5894 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5895 addu $tempreg,$tempreg,$gp
5896 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5897 For a local symbol, we want
5898 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5900 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5902 If we have a small constant, and this is a reference to
5903 an external symbol, we want
5904 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5905 addu $tempreg,$tempreg,$gp
5906 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5908 addiu $tempreg,$tempreg,<constant>
5909 For a local symbol, we want
5910 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5912 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5914 If we have a large constant, and this is a reference to
5915 an external symbol, we want
5916 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5917 addu $tempreg,$tempreg,$gp
5918 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5919 lui $at,<hiconstant>
5920 addiu $at,$at,<loconstant>
5921 addu $tempreg,$tempreg,$at
5922 For a local symbol, we want
5923 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5924 lui $at,<hiconstant>
5925 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5926 addu $tempreg,$tempreg,$at
5929 expr1.X_add_number = offset_expr.X_add_number;
5930 offset_expr.X_add_number = 0;
5931 relax_start (offset_expr.X_add_symbol);
5932 gpdelay = reg_needs_delay (mips_gp_register);
5933 if (expr1.X_add_number == 0 && breg == 0
5934 && (call || tempreg == PIC_CALL_REG))
5936 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5937 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5939 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
5940 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5941 tempreg, tempreg, mips_gp_register);
5942 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5943 tempreg, lw_reloc_type, tempreg);
5944 if (expr1.X_add_number == 0)
5948 /* We're going to put in an addu instruction using
5949 tempreg, so we may as well insert the nop right
5954 else if (expr1.X_add_number >= -0x8000
5955 && expr1.X_add_number < 0x8000)
5958 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5959 tempreg, tempreg, BFD_RELOC_LO16);
5965 /* If we are going to add in a base register, and the
5966 target register and the base register are the same,
5967 then we are using AT as a temporary register. Since
5968 we want to load the constant into AT, we add our
5969 current AT (from the global offset table) and the
5970 register into the register now, and pretend we were
5971 not using a base register. */
5976 assert (tempreg == AT);
5978 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5983 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5984 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
5988 offset_expr.X_add_number =
5989 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000;
5994 /* This is needed because this instruction uses $gp, but
5995 the first instruction on the main stream does not. */
5996 macro_build (NULL, "nop", "");
5999 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6000 local_reloc_type, mips_gp_register);
6001 if (expr1.X_add_number >= -0x8000
6002 && expr1.X_add_number < 0x8000)
6005 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6006 tempreg, tempreg, BFD_RELOC_LO16);
6007 /* FIXME: If add_number is 0, and there was no base
6008 register, the external symbol case ended with a load,
6009 so if the symbol turns out to not be external, and
6010 the next instruction uses tempreg, an unnecessary nop
6011 will be inserted. */
6017 /* We must add in the base register now, as in the
6018 external symbol case. */
6019 assert (tempreg == AT);
6021 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6024 /* We set breg to 0 because we have arranged to add
6025 it in in both cases. */
6029 macro_build_lui (&expr1, AT);
6030 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6031 AT, AT, BFD_RELOC_LO16);
6032 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6033 tempreg, tempreg, AT);
6038 else if (mips_big_got && HAVE_NEWABI)
6040 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
6041 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
6042 int add_breg_early = 0;
6044 /* This is the large GOT case. If this is a reference to an
6045 external symbol, and there is no constant, we want
6046 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6047 add $tempreg,$tempreg,$gp
6048 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6049 or for lca or if tempreg is PIC_CALL_REG
6050 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6051 add $tempreg,$tempreg,$gp
6052 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
6054 If we have a small constant, and this is a reference to
6055 an external symbol, we want
6056 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6057 add $tempreg,$tempreg,$gp
6058 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6059 addi $tempreg,$tempreg,<constant>
6061 If we have a large constant, and this is a reference to
6062 an external symbol, we want
6063 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6064 addu $tempreg,$tempreg,$gp
6065 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6066 lui $at,<hiconstant>
6067 addi $at,$at,<loconstant>
6068 add $tempreg,$tempreg,$at
6070 If we have NewABI, and we know it's a local symbol, we want
6071 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6072 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6073 otherwise we have to resort to GOT_HI16/GOT_LO16. */
6075 relax_start (offset_expr.X_add_symbol);
6077 expr1.X_add_number = offset_expr.X_add_number;
6078 offset_expr.X_add_number = 0;
6080 if (expr1.X_add_number == 0 && breg == 0
6081 && (call || tempreg == PIC_CALL_REG))
6083 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
6084 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
6086 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
6087 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6088 tempreg, tempreg, mips_gp_register);
6089 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6090 tempreg, lw_reloc_type, tempreg);
6092 if (expr1.X_add_number == 0)
6094 else if (expr1.X_add_number >= -0x8000
6095 && expr1.X_add_number < 0x8000)
6097 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
6098 tempreg, tempreg, BFD_RELOC_LO16);
6100 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
6104 /* If we are going to add in a base register, and the
6105 target register and the base register are the same,
6106 then we are using AT as a temporary register. Since
6107 we want to load the constant into AT, we add our
6108 current AT (from the global offset table) and the
6109 register into the register now, and pretend we were
6110 not using a base register. */
6115 assert (tempreg == AT);
6116 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6122 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
6123 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
6128 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
6131 offset_expr.X_add_number = expr1.X_add_number;
6132 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6133 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6134 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6135 tempreg, BFD_RELOC_MIPS_GOT_OFST);
6138 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6139 treg, tempreg, breg);
6149 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
6154 unsigned long temp = (treg << 16) | (0x01);
6155 macro_build (NULL, "c2", "C", temp);
6157 /* AT is not used, just return */
6162 unsigned long temp = (0x02);
6163 macro_build (NULL, "c2", "C", temp);
6165 /* AT is not used, just return */
6170 unsigned long temp = (treg << 16) | (0x02);
6171 macro_build (NULL, "c2", "C", temp);
6173 /* AT is not used, just return */
6177 macro_build (NULL, "c2", "C", 3);
6178 /* AT is not used, just return */
6183 unsigned long temp = (treg << 16) | 0x03;
6184 macro_build (NULL, "c2", "C", temp);
6186 /* AT is not used, just return */
6190 /* The j instruction may not be used in PIC code, since it
6191 requires an absolute address. We convert it to a b
6193 if (mips_pic == NO_PIC)
6194 macro_build (&offset_expr, "j", "a");
6196 macro_build (&offset_expr, "b", "p");
6199 /* The jal instructions must be handled as macros because when
6200 generating PIC code they expand to multi-instruction
6201 sequences. Normally they are simple instructions. */
6206 if (mips_pic == NO_PIC)
6207 macro_build (NULL, "jalr", "d,s", dreg, sreg);
6210 if (sreg != PIC_CALL_REG)
6211 as_warn (_("MIPS PIC call to register other than $25"));
6213 macro_build (NULL, "jalr", "d,s", dreg, sreg);
6214 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
6216 if (mips_cprestore_offset < 0)
6217 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6220 if (! mips_frame_reg_valid)
6222 as_warn (_("No .frame pseudo-op used in PIC code"));
6223 /* Quiet this warning. */
6224 mips_frame_reg_valid = 1;
6226 if (! mips_cprestore_valid)
6228 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6229 /* Quiet this warning. */
6230 mips_cprestore_valid = 1;
6232 expr1.X_add_number = mips_cprestore_offset;
6233 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
6236 HAVE_64BIT_ADDRESSES);
6244 if (mips_pic == NO_PIC)
6245 macro_build (&offset_expr, "jal", "a");
6246 else if (mips_pic == SVR4_PIC)
6248 /* If this is a reference to an external symbol, and we are
6249 using a small GOT, we want
6250 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
6254 lw $gp,cprestore($sp)
6255 The cprestore value is set using the .cprestore
6256 pseudo-op. If we are using a big GOT, we want
6257 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6259 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
6263 lw $gp,cprestore($sp)
6264 If the symbol is not external, we want
6265 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6267 addiu $25,$25,<sym> (BFD_RELOC_LO16)
6270 lw $gp,cprestore($sp)
6272 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
6273 sequences above, minus nops, unless the symbol is local,
6274 which enables us to use GOT_PAGE/GOT_OFST (big got) or
6280 relax_start (offset_expr.X_add_symbol);
6281 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6282 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
6285 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6286 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
6292 relax_start (offset_expr.X_add_symbol);
6293 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
6294 BFD_RELOC_MIPS_CALL_HI16);
6295 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
6296 PIC_CALL_REG, mips_gp_register);
6297 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6298 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
6301 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6302 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
6304 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6305 PIC_CALL_REG, PIC_CALL_REG,
6306 BFD_RELOC_MIPS_GOT_OFST);
6310 macro_build_jalr (&offset_expr);
6314 relax_start (offset_expr.X_add_symbol);
6317 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6318 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
6327 gpdelay = reg_needs_delay (mips_gp_register);
6328 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
6329 BFD_RELOC_MIPS_CALL_HI16);
6330 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
6331 PIC_CALL_REG, mips_gp_register);
6332 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6333 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
6338 macro_build (NULL, "nop", "");
6340 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6341 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
6344 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6345 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
6347 macro_build_jalr (&offset_expr);
6349 if (mips_cprestore_offset < 0)
6350 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6353 if (! mips_frame_reg_valid)
6355 as_warn (_("No .frame pseudo-op used in PIC code"));
6356 /* Quiet this warning. */
6357 mips_frame_reg_valid = 1;
6359 if (! mips_cprestore_valid)
6361 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6362 /* Quiet this warning. */
6363 mips_cprestore_valid = 1;
6365 if (mips_opts.noreorder)
6366 macro_build (NULL, "nop", "");
6367 expr1.X_add_number = mips_cprestore_offset;
6368 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
6371 HAVE_64BIT_ADDRESSES);
6375 else if (mips_pic == VXWORKS_PIC)
6376 as_bad (_("Non-PIC jump used in PIC library"));
6399 /* Itbl support may require additional care here. */
6404 /* Itbl support may require additional care here. */
6409 /* Itbl support may require additional care here. */
6414 /* Itbl support may require additional care here. */
6427 /* Itbl support may require additional care here. */
6432 /* Itbl support may require additional care here. */
6437 /* Itbl support may require additional care here. */
6457 if (breg == treg || coproc || lr)
6478 /* Itbl support may require additional care here. */
6483 /* Itbl support may require additional care here. */
6488 /* Itbl support may require additional care here. */
6493 /* Itbl support may require additional care here. */
6514 /* Itbl support may require additional care here. */
6518 /* Itbl support may require additional care here. */
6523 /* Itbl support may require additional care here. */
6536 && NO_ISA_COP (mips_opts.arch)
6537 && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0)
6539 as_bad (_("opcode not supported on this processor: %s"),
6540 mips_cpu_info_from_arch (mips_opts.arch)->name);
6544 /* Itbl support may require additional care here. */
6545 if (mask == M_LWC1_AB
6546 || mask == M_SWC1_AB
6547 || mask == M_LDC1_AB
6548 || mask == M_SDC1_AB
6552 else if (mask == M_CACHE_AB)
6559 if (offset_expr.X_op != O_constant
6560 && offset_expr.X_op != O_symbol)
6562 as_bad (_("expression too complex"));
6563 offset_expr.X_op = O_constant;
6566 if (HAVE_32BIT_ADDRESSES
6567 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
6571 sprintf_vma (value, offset_expr.X_add_number);
6572 as_bad (_("Number (0x%s) larger than 32 bits"), value);
6575 /* A constant expression in PIC code can be handled just as it
6576 is in non PIC code. */
6577 if (offset_expr.X_op == O_constant)
6579 expr1.X_add_number = ((offset_expr.X_add_number + 0x8000)
6580 & ~(bfd_vma) 0xffff);
6581 normalize_address_expr (&expr1);
6582 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
6584 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6585 tempreg, tempreg, breg);
6586 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6588 else if (mips_pic == NO_PIC)
6590 /* If this is a reference to a GP relative symbol, and there
6591 is no base register, we want
6592 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6593 Otherwise, if there is no base register, we want
6594 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6595 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6596 If we have a constant, we need two instructions anyhow,
6597 so we always use the latter form.
6599 If we have a base register, and this is a reference to a
6600 GP relative symbol, we want
6601 addu $tempreg,$breg,$gp
6602 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6604 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6605 addu $tempreg,$tempreg,$breg
6606 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6607 With a constant we always use the latter case.
6609 With 64bit address space and no base register and $at usable,
6611 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6612 lui $at,<sym> (BFD_RELOC_HI16_S)
6613 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6616 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6617 If we have a base register, we want
6618 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6619 lui $at,<sym> (BFD_RELOC_HI16_S)
6620 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6624 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6626 Without $at we can't generate the optimal path for superscalar
6627 processors here since this would require two temporary registers.
6628 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6629 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6631 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6633 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6634 If we have a base register, we want
6635 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6636 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6638 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6640 daddu $tempreg,$tempreg,$breg
6641 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6643 For GP relative symbols in 64bit address space we can use
6644 the same sequence as in 32bit address space. */
6645 if (HAVE_64BIT_SYMBOLS)
6647 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6648 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6650 relax_start (offset_expr.X_add_symbol);
6653 macro_build (&offset_expr, s, fmt, treg,
6654 BFD_RELOC_GPREL16, mips_gp_register);
6658 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6659 tempreg, breg, mips_gp_register);
6660 macro_build (&offset_expr, s, fmt, treg,
6661 BFD_RELOC_GPREL16, tempreg);
6666 if (used_at == 0 && mips_opts.at)
6668 macro_build (&offset_expr, "lui", "t,u", tempreg,
6669 BFD_RELOC_MIPS_HIGHEST);
6670 macro_build (&offset_expr, "lui", "t,u", AT,
6672 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6673 tempreg, BFD_RELOC_MIPS_HIGHER);
6675 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
6676 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
6677 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
6678 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
6684 macro_build (&offset_expr, "lui", "t,u", tempreg,
6685 BFD_RELOC_MIPS_HIGHEST);
6686 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6687 tempreg, BFD_RELOC_MIPS_HIGHER);
6688 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6689 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6690 tempreg, BFD_RELOC_HI16_S);
6691 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6693 macro_build (NULL, "daddu", "d,v,t",
6694 tempreg, tempreg, breg);
6695 macro_build (&offset_expr, s, fmt, treg,
6696 BFD_RELOC_LO16, tempreg);
6699 if (mips_relax.sequence)
6706 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6707 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6709 relax_start (offset_expr.X_add_symbol);
6710 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
6714 macro_build_lui (&offset_expr, tempreg);
6715 macro_build (&offset_expr, s, fmt, treg,
6716 BFD_RELOC_LO16, tempreg);
6717 if (mips_relax.sequence)
6722 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6723 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6725 relax_start (offset_expr.X_add_symbol);
6726 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6727 tempreg, breg, mips_gp_register);
6728 macro_build (&offset_expr, s, fmt, treg,
6729 BFD_RELOC_GPREL16, tempreg);
6732 macro_build_lui (&offset_expr, tempreg);
6733 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6734 tempreg, tempreg, breg);
6735 macro_build (&offset_expr, s, fmt, treg,
6736 BFD_RELOC_LO16, tempreg);
6737 if (mips_relax.sequence)
6741 else if (!mips_big_got)
6743 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6745 /* If this is a reference to an external symbol, we want
6746 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6748 <op> $treg,0($tempreg)
6750 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6752 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6753 <op> $treg,0($tempreg)
6756 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6757 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6759 If there is a base register, we add it to $tempreg before
6760 the <op>. If there is a constant, we stick it in the
6761 <op> instruction. We don't handle constants larger than
6762 16 bits, because we have no way to load the upper 16 bits
6763 (actually, we could handle them for the subset of cases
6764 in which we are not using $at). */
6765 assert (offset_expr.X_op == O_symbol);
6768 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6769 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6771 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6772 tempreg, tempreg, breg);
6773 macro_build (&offset_expr, s, fmt, treg,
6774 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6777 expr1.X_add_number = offset_expr.X_add_number;
6778 offset_expr.X_add_number = 0;
6779 if (expr1.X_add_number < -0x8000
6780 || expr1.X_add_number >= 0x8000)
6781 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6782 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6783 lw_reloc_type, mips_gp_register);
6785 relax_start (offset_expr.X_add_symbol);
6787 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6788 tempreg, BFD_RELOC_LO16);
6791 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6792 tempreg, tempreg, breg);
6793 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6795 else if (mips_big_got && !HAVE_NEWABI)
6799 /* If this is a reference to an external symbol, we want
6800 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6801 addu $tempreg,$tempreg,$gp
6802 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6803 <op> $treg,0($tempreg)
6805 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6807 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6808 <op> $treg,0($tempreg)
6809 If there is a base register, we add it to $tempreg before
6810 the <op>. If there is a constant, we stick it in the
6811 <op> instruction. We don't handle constants larger than
6812 16 bits, because we have no way to load the upper 16 bits
6813 (actually, we could handle them for the subset of cases
6814 in which we are not using $at). */
6815 assert (offset_expr.X_op == O_symbol);
6816 expr1.X_add_number = offset_expr.X_add_number;
6817 offset_expr.X_add_number = 0;
6818 if (expr1.X_add_number < -0x8000
6819 || expr1.X_add_number >= 0x8000)
6820 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6821 gpdelay = reg_needs_delay (mips_gp_register);
6822 relax_start (offset_expr.X_add_symbol);
6823 macro_build (&offset_expr, "lui", "t,u", tempreg,
6824 BFD_RELOC_MIPS_GOT_HI16);
6825 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
6827 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6828 BFD_RELOC_MIPS_GOT_LO16, tempreg);
6831 macro_build (NULL, "nop", "");
6832 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6833 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6835 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6836 tempreg, BFD_RELOC_LO16);
6840 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6841 tempreg, tempreg, breg);
6842 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6844 else if (mips_big_got && HAVE_NEWABI)
6846 /* If this is a reference to an external symbol, we want
6847 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6848 add $tempreg,$tempreg,$gp
6849 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6850 <op> $treg,<ofst>($tempreg)
6851 Otherwise, for local symbols, we want:
6852 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6853 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6854 assert (offset_expr.X_op == O_symbol);
6855 expr1.X_add_number = offset_expr.X_add_number;
6856 offset_expr.X_add_number = 0;
6857 if (expr1.X_add_number < -0x8000
6858 || expr1.X_add_number >= 0x8000)
6859 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6860 relax_start (offset_expr.X_add_symbol);
6861 macro_build (&offset_expr, "lui", "t,u", tempreg,
6862 BFD_RELOC_MIPS_GOT_HI16);
6863 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
6865 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6866 BFD_RELOC_MIPS_GOT_LO16, tempreg);
6868 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6869 tempreg, tempreg, breg);
6870 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6873 offset_expr.X_add_number = expr1.X_add_number;
6874 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6875 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6877 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6878 tempreg, tempreg, breg);
6879 macro_build (&offset_expr, s, fmt, treg,
6880 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6890 load_register (treg, &imm_expr, 0);
6894 load_register (treg, &imm_expr, 1);
6898 if (imm_expr.X_op == O_constant)
6901 load_register (AT, &imm_expr, 0);
6902 macro_build (NULL, "mtc1", "t,G", AT, treg);
6907 assert (offset_expr.X_op == O_symbol
6908 && strcmp (segment_name (S_GET_SEGMENT
6909 (offset_expr.X_add_symbol)),
6911 && offset_expr.X_add_number == 0);
6912 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
6913 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6918 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6919 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6920 order 32 bits of the value and the low order 32 bits are either
6921 zero or in OFFSET_EXPR. */
6922 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6924 if (HAVE_64BIT_GPRS)
6925 load_register (treg, &imm_expr, 1);
6930 if (target_big_endian)
6942 load_register (hreg, &imm_expr, 0);
6945 if (offset_expr.X_op == O_absent)
6946 move_register (lreg, 0);
6949 assert (offset_expr.X_op == O_constant);
6950 load_register (lreg, &offset_expr, 0);
6957 /* We know that sym is in the .rdata section. First we get the
6958 upper 16 bits of the address. */
6959 if (mips_pic == NO_PIC)
6961 macro_build_lui (&offset_expr, AT);
6966 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6967 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6971 /* Now we load the register(s). */
6972 if (HAVE_64BIT_GPRS)
6975 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
6980 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
6983 /* FIXME: How in the world do we deal with the possible
6985 offset_expr.X_add_number += 4;
6986 macro_build (&offset_expr, "lw", "t,o(b)",
6987 treg + 1, BFD_RELOC_LO16, AT);
6993 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6994 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6995 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6996 the value and the low order 32 bits are either zero or in
6998 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
7001 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
7002 if (HAVE_64BIT_FPRS)
7004 assert (HAVE_64BIT_GPRS);
7005 macro_build (NULL, "dmtc1", "t,S", AT, treg);
7009 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
7010 if (offset_expr.X_op == O_absent)
7011 macro_build (NULL, "mtc1", "t,G", 0, treg);
7014 assert (offset_expr.X_op == O_constant);
7015 load_register (AT, &offset_expr, 0);
7016 macro_build (NULL, "mtc1", "t,G", AT, treg);
7022 assert (offset_expr.X_op == O_symbol
7023 && offset_expr.X_add_number == 0);
7024 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
7025 if (strcmp (s, ".lit8") == 0)
7027 if (mips_opts.isa != ISA_MIPS1)
7029 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
7030 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
7033 breg = mips_gp_register;
7034 r = BFD_RELOC_MIPS_LITERAL;
7039 assert (strcmp (s, RDATA_SECTION_NAME) == 0);
7041 if (mips_pic != NO_PIC)
7042 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7043 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7046 /* FIXME: This won't work for a 64 bit address. */
7047 macro_build_lui (&offset_expr, AT);
7050 if (mips_opts.isa != ISA_MIPS1)
7052 macro_build (&offset_expr, "ldc1", "T,o(b)",
7053 treg, BFD_RELOC_LO16, AT);
7062 /* Even on a big endian machine $fn comes before $fn+1. We have
7063 to adjust when loading from memory. */
7066 assert (mips_opts.isa == ISA_MIPS1);
7067 macro_build (&offset_expr, "lwc1", "T,o(b)",
7068 target_big_endian ? treg + 1 : treg, r, breg);
7069 /* FIXME: A possible overflow which I don't know how to deal
7071 offset_expr.X_add_number += 4;
7072 macro_build (&offset_expr, "lwc1", "T,o(b)",
7073 target_big_endian ? treg : treg + 1, r, breg);
7078 * The MIPS assembler seems to check for X_add_number not
7079 * being double aligned and generating:
7082 * addiu at,at,%lo(foo+1)
7085 * But, the resulting address is the same after relocation so why
7086 * generate the extra instruction?
7088 /* Itbl support may require additional care here. */
7090 if (mips_opts.isa != ISA_MIPS1)
7101 if (mips_opts.isa != ISA_MIPS1)
7109 /* Itbl support may require additional care here. */
7114 if (HAVE_64BIT_GPRS)
7125 if (HAVE_64BIT_GPRS)
7135 if (offset_expr.X_op != O_symbol
7136 && offset_expr.X_op != O_constant)
7138 as_bad (_("expression too complex"));
7139 offset_expr.X_op = O_constant;
7142 if (HAVE_32BIT_ADDRESSES
7143 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
7147 sprintf_vma (value, offset_expr.X_add_number);
7148 as_bad (_("Number (0x%s) larger than 32 bits"), value);
7151 /* Even on a big endian machine $fn comes before $fn+1. We have
7152 to adjust when loading from memory. We set coproc if we must
7153 load $fn+1 first. */
7154 /* Itbl support may require additional care here. */
7155 if (! target_big_endian)
7158 if (mips_pic == NO_PIC
7159 || offset_expr.X_op == O_constant)
7161 /* If this is a reference to a GP relative symbol, we want
7162 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
7163 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
7164 If we have a base register, we use this
7166 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
7167 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
7168 If this is not a GP relative symbol, we want
7169 lui $at,<sym> (BFD_RELOC_HI16_S)
7170 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7171 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7172 If there is a base register, we add it to $at after the
7173 lui instruction. If there is a constant, we always use
7175 if (offset_expr.X_op == O_symbol
7176 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7177 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7179 relax_start (offset_expr.X_add_symbol);
7182 tempreg = mips_gp_register;
7186 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7187 AT, breg, mips_gp_register);
7192 /* Itbl support may require additional care here. */
7193 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7194 BFD_RELOC_GPREL16, tempreg);
7195 offset_expr.X_add_number += 4;
7197 /* Set mips_optimize to 2 to avoid inserting an
7199 hold_mips_optimize = mips_optimize;
7201 /* Itbl support may require additional care here. */
7202 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7203 BFD_RELOC_GPREL16, tempreg);
7204 mips_optimize = hold_mips_optimize;
7208 /* We just generated two relocs. When tc_gen_reloc
7209 handles this case, it will skip the first reloc and
7210 handle the second. The second reloc already has an
7211 extra addend of 4, which we added above. We must
7212 subtract it out, and then subtract another 4 to make
7213 the first reloc come out right. The second reloc
7214 will come out right because we are going to add 4 to
7215 offset_expr when we build its instruction below.
7217 If we have a symbol, then we don't want to include
7218 the offset, because it will wind up being included
7219 when we generate the reloc. */
7221 if (offset_expr.X_op == O_constant)
7222 offset_expr.X_add_number -= 8;
7225 offset_expr.X_add_number = -4;
7226 offset_expr.X_op = O_constant;
7230 macro_build_lui (&offset_expr, AT);
7232 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7233 /* Itbl support may require additional care here. */
7234 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7235 BFD_RELOC_LO16, AT);
7236 /* FIXME: How do we handle overflow here? */
7237 offset_expr.X_add_number += 4;
7238 /* Itbl support may require additional care here. */
7239 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7240 BFD_RELOC_LO16, AT);
7241 if (mips_relax.sequence)
7244 else if (!mips_big_got)
7246 /* If this is a reference to an external symbol, we want
7247 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7252 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7254 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7255 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7256 If there is a base register we add it to $at before the
7257 lwc1 instructions. If there is a constant we include it
7258 in the lwc1 instructions. */
7260 expr1.X_add_number = offset_expr.X_add_number;
7261 if (expr1.X_add_number < -0x8000
7262 || expr1.X_add_number >= 0x8000 - 4)
7263 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7264 load_got_offset (AT, &offset_expr);
7267 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7269 /* Set mips_optimize to 2 to avoid inserting an undesired
7271 hold_mips_optimize = mips_optimize;
7274 /* Itbl support may require additional care here. */
7275 relax_start (offset_expr.X_add_symbol);
7276 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
7277 BFD_RELOC_LO16, AT);
7278 expr1.X_add_number += 4;
7279 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
7280 BFD_RELOC_LO16, AT);
7282 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7283 BFD_RELOC_LO16, AT);
7284 offset_expr.X_add_number += 4;
7285 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7286 BFD_RELOC_LO16, AT);
7289 mips_optimize = hold_mips_optimize;
7291 else if (mips_big_got)
7295 /* If this is a reference to an external symbol, we want
7296 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7298 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
7303 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7305 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7306 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7307 If there is a base register we add it to $at before the
7308 lwc1 instructions. If there is a constant we include it
7309 in the lwc1 instructions. */
7311 expr1.X_add_number = offset_expr.X_add_number;
7312 offset_expr.X_add_number = 0;
7313 if (expr1.X_add_number < -0x8000
7314 || expr1.X_add_number >= 0x8000 - 4)
7315 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7316 gpdelay = reg_needs_delay (mips_gp_register);
7317 relax_start (offset_expr.X_add_symbol);
7318 macro_build (&offset_expr, "lui", "t,u",
7319 AT, BFD_RELOC_MIPS_GOT_HI16);
7320 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7321 AT, AT, mips_gp_register);
7322 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7323 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
7326 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7327 /* Itbl support may require additional care here. */
7328 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
7329 BFD_RELOC_LO16, AT);
7330 expr1.X_add_number += 4;
7332 /* Set mips_optimize to 2 to avoid inserting an undesired
7334 hold_mips_optimize = mips_optimize;
7336 /* Itbl support may require additional care here. */
7337 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
7338 BFD_RELOC_LO16, AT);
7339 mips_optimize = hold_mips_optimize;
7340 expr1.X_add_number -= 4;
7343 offset_expr.X_add_number = expr1.X_add_number;
7345 macro_build (NULL, "nop", "");
7346 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7347 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7350 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7351 /* Itbl support may require additional care here. */
7352 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7353 BFD_RELOC_LO16, AT);
7354 offset_expr.X_add_number += 4;
7356 /* Set mips_optimize to 2 to avoid inserting an undesired
7358 hold_mips_optimize = mips_optimize;
7360 /* Itbl support may require additional care here. */
7361 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7362 BFD_RELOC_LO16, AT);
7363 mips_optimize = hold_mips_optimize;
7377 assert (HAVE_32BIT_ADDRESSES);
7378 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
7379 offset_expr.X_add_number += 4;
7380 macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg);
7383 /* New code added to support COPZ instructions.
7384 This code builds table entries out of the macros in mip_opcodes.
7385 R4000 uses interlocks to handle coproc delays.
7386 Other chips (like the R3000) require nops to be inserted for delays.
7388 FIXME: Currently, we require that the user handle delays.
7389 In order to fill delay slots for non-interlocked chips,
7390 we must have a way to specify delays based on the coprocessor.
7391 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7392 What are the side-effects of the cop instruction?
7393 What cache support might we have and what are its effects?
7394 Both coprocessor & memory require delays. how long???
7395 What registers are read/set/modified?
7397 If an itbl is provided to interpret cop instructions,
7398 this knowledge can be encoded in the itbl spec. */
7412 if (NO_ISA_COP (mips_opts.arch)
7413 && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0)
7415 as_bad (_("opcode not supported on this processor: %s"),
7416 mips_cpu_info_from_arch (mips_opts.arch)->name);
7420 /* For now we just do C (same as Cz). The parameter will be
7421 stored in insn_opcode by mips_ip. */
7422 macro_build (NULL, s, "C", ip->insn_opcode);
7426 move_register (dreg, sreg);
7429 #ifdef LOSING_COMPILER
7431 /* Try and see if this is a new itbl instruction.
7432 This code builds table entries out of the macros in mip_opcodes.
7433 FIXME: For now we just assemble the expression and pass it's
7434 value along as a 32-bit immediate.
7435 We may want to have the assembler assemble this value,
7436 so that we gain the assembler's knowledge of delay slots,
7438 Would it be more efficient to use mask (id) here? */
7439 if (itbl_have_entries
7440 && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
7442 s = ip->insn_mo->name;
7444 coproc = ITBL_DECODE_PNUM (immed_expr);;
7445 macro_build (&immed_expr, s, "C");
7451 if (!mips_opts.at && used_at)
7452 as_bad (_("Macro used $at after \".set noat\""));
7456 macro2 (struct mips_cl_insn *ip)
7458 unsigned int treg, sreg, dreg, breg;
7459 unsigned int tempreg;
7473 bfd_reloc_code_real_type r;
7475 treg = (ip->insn_opcode >> 16) & 0x1f;
7476 dreg = (ip->insn_opcode >> 11) & 0x1f;
7477 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
7478 mask = ip->insn_mo->mask;
7480 expr1.X_op = O_constant;
7481 expr1.X_op_symbol = NULL;
7482 expr1.X_add_symbol = NULL;
7483 expr1.X_add_number = 1;
7487 #endif /* LOSING_COMPILER */
7492 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
7493 macro_build (NULL, "mflo", "d", dreg);
7499 /* The MIPS assembler some times generates shifts and adds. I'm
7500 not trying to be that fancy. GCC should do this for us
7503 load_register (AT, &imm_expr, dbl);
7504 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
7505 macro_build (NULL, "mflo", "d", dreg);
7521 load_register (AT, &imm_expr, dbl);
7522 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
7523 macro_build (NULL, "mflo", "d", dreg);
7524 macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
7525 macro_build (NULL, "mfhi", "d", AT);
7527 macro_build (NULL, "tne", "s,t,q", dreg, AT, 6);
7530 expr1.X_add_number = 8;
7531 macro_build (&expr1, "beq", "s,t,p", dreg, AT);
7532 macro_build (NULL, "nop", "", 0);
7533 macro_build (NULL, "break", "c", 6);
7536 macro_build (NULL, "mflo", "d", dreg);
7552 load_register (AT, &imm_expr, dbl);
7553 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
7554 sreg, imm ? AT : treg);
7555 macro_build (NULL, "mfhi", "d", AT);
7556 macro_build (NULL, "mflo", "d", dreg);
7558 macro_build (NULL, "tne", "s,t,q", AT, 0, 6);
7561 expr1.X_add_number = 8;
7562 macro_build (&expr1, "beq", "s,t,p", AT, 0);
7563 macro_build (NULL, "nop", "", 0);
7564 macro_build (NULL, "break", "c", 6);
7570 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7581 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
7582 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
7586 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
7587 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
7588 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
7589 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7593 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7604 macro_build (NULL, "negu", "d,w", tempreg, treg);
7605 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
7609 macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
7610 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
7611 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
7612 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7620 if (imm_expr.X_op != O_constant)
7621 as_bad (_("Improper rotate count"));
7622 rot = imm_expr.X_add_number & 0x3f;
7623 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7625 rot = (64 - rot) & 0x3f;
7627 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7629 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7634 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7637 l = (rot < 0x20) ? "dsll" : "dsll32";
7638 r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
7641 macro_build (NULL, l, "d,w,<", AT, sreg, rot);
7642 macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7643 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7651 if (imm_expr.X_op != O_constant)
7652 as_bad (_("Improper rotate count"));
7653 rot = imm_expr.X_add_number & 0x1f;
7654 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7656 macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f);
7661 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7665 macro_build (NULL, "sll", "d,w,<", AT, sreg, rot);
7666 macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7667 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7672 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7674 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
7678 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
7679 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
7680 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
7681 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7685 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7687 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
7691 macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
7692 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
7693 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
7694 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7702 if (imm_expr.X_op != O_constant)
7703 as_bad (_("Improper rotate count"));
7704 rot = imm_expr.X_add_number & 0x3f;
7705 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7708 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7710 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7715 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7718 r = (rot < 0x20) ? "dsrl" : "dsrl32";
7719 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7722 macro_build (NULL, r, "d,w,<", AT, sreg, rot);
7723 macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7724 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7732 if (imm_expr.X_op != O_constant)
7733 as_bad (_("Improper rotate count"));
7734 rot = imm_expr.X_add_number & 0x1f;
7735 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7737 macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot);
7742 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7746 macro_build (NULL, "srl", "d,w,<", AT, sreg, rot);
7747 macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7748 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7753 assert (mips_opts.isa == ISA_MIPS1);
7754 /* Even on a big endian machine $fn comes before $fn+1. We have
7755 to adjust when storing to memory. */
7756 macro_build (&offset_expr, "swc1", "T,o(b)",
7757 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
7758 offset_expr.X_add_number += 4;
7759 macro_build (&offset_expr, "swc1", "T,o(b)",
7760 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
7765 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
7767 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7770 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7771 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7776 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7778 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7783 as_warn (_("Instruction %s: result is always false"),
7785 move_register (dreg, 0);
7788 if (CPU_HAS_SEQ (mips_opts.arch)
7789 && -512 <= imm_expr.X_add_number
7790 && imm_expr.X_add_number < 512)
7792 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
7793 (int) imm_expr.X_add_number);
7796 if (imm_expr.X_op == O_constant
7797 && imm_expr.X_add_number >= 0
7798 && imm_expr.X_add_number < 0x10000)
7800 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7802 else if (imm_expr.X_op == O_constant
7803 && imm_expr.X_add_number > -0x8000
7804 && imm_expr.X_add_number < 0)
7806 imm_expr.X_add_number = -imm_expr.X_add_number;
7807 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7808 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7810 else if (CPU_HAS_SEQ (mips_opts.arch))
7813 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7814 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
7819 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7820 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7823 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7826 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
7832 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
7833 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7836 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
7838 if (imm_expr.X_op == O_constant
7839 && imm_expr.X_add_number >= -0x8000
7840 && imm_expr.X_add_number < 0x8000)
7842 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
7843 dreg, sreg, BFD_RELOC_LO16);
7847 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7848 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
7852 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7855 case M_SGT: /* sreg > treg <==> treg < sreg */
7861 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7864 case M_SGT_I: /* sreg > I <==> I < sreg */
7871 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7872 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7875 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7881 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7882 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7885 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7892 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7893 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7894 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7898 if (imm_expr.X_op == O_constant
7899 && imm_expr.X_add_number >= -0x8000
7900 && imm_expr.X_add_number < 0x8000)
7902 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7906 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7907 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
7911 if (imm_expr.X_op == O_constant
7912 && imm_expr.X_add_number >= -0x8000
7913 && imm_expr.X_add_number < 0x8000)
7915 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
7920 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7921 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
7926 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
7928 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
7931 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7932 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
7937 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7939 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
7944 as_warn (_("Instruction %s: result is always true"),
7946 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
7947 dreg, 0, BFD_RELOC_LO16);
7950 if (CPU_HAS_SEQ (mips_opts.arch)
7951 && -512 <= imm_expr.X_add_number
7952 && imm_expr.X_add_number < 512)
7954 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
7955 (int) imm_expr.X_add_number);
7958 if (imm_expr.X_op == O_constant
7959 && imm_expr.X_add_number >= 0
7960 && imm_expr.X_add_number < 0x10000)
7962 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7964 else if (imm_expr.X_op == O_constant
7965 && imm_expr.X_add_number > -0x8000
7966 && imm_expr.X_add_number < 0)
7968 imm_expr.X_add_number = -imm_expr.X_add_number;
7969 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7970 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7972 else if (CPU_HAS_SEQ (mips_opts.arch))
7975 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7976 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
7981 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7982 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7985 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
7991 if (imm_expr.X_op == O_constant
7992 && imm_expr.X_add_number > -0x8000
7993 && imm_expr.X_add_number <= 0x8000)
7995 imm_expr.X_add_number = -imm_expr.X_add_number;
7996 macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j",
7997 dreg, sreg, BFD_RELOC_LO16);
8001 load_register (AT, &imm_expr, dbl);
8002 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
8008 if (imm_expr.X_op == O_constant
8009 && imm_expr.X_add_number > -0x8000
8010 && imm_expr.X_add_number <= 0x8000)
8012 imm_expr.X_add_number = -imm_expr.X_add_number;
8013 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j",
8014 dreg, sreg, BFD_RELOC_LO16);
8018 load_register (AT, &imm_expr, dbl);
8019 macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
8041 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8042 macro_build (NULL, s, "s,t", sreg, AT);
8047 assert (mips_opts.isa == ISA_MIPS1);
8049 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
8050 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
8053 * Is the double cfc1 instruction a bug in the mips assembler;
8054 * or is there a reason for it?
8057 macro_build (NULL, "cfc1", "t,G", treg, RA);
8058 macro_build (NULL, "cfc1", "t,G", treg, RA);
8059 macro_build (NULL, "nop", "");
8060 expr1.X_add_number = 3;
8061 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
8062 expr1.X_add_number = 2;
8063 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
8064 macro_build (NULL, "ctc1", "t,G", AT, RA);
8065 macro_build (NULL, "nop", "");
8066 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
8068 macro_build (NULL, "ctc1", "t,G", treg, RA);
8069 macro_build (NULL, "nop", "");
8080 if (offset_expr.X_add_number >= 0x7fff)
8081 as_bad (_("operand overflow"));
8082 if (! target_big_endian)
8083 ++offset_expr.X_add_number;
8084 macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg);
8085 if (! target_big_endian)
8086 --offset_expr.X_add_number;
8088 ++offset_expr.X_add_number;
8089 macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg);
8090 macro_build (NULL, "sll", "d,w,<", AT, AT, 8);
8091 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8104 if (offset_expr.X_add_number >= 0x8000 - off)
8105 as_bad (_("operand overflow"));
8113 if (! target_big_endian)
8114 offset_expr.X_add_number += off;
8115 macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
8116 if (! target_big_endian)
8117 offset_expr.X_add_number -= off;
8119 offset_expr.X_add_number += off;
8120 macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
8122 /* If necessary, move the result in tempreg the final destination. */
8123 if (treg == tempreg)
8125 /* Protect second load's delay slot. */
8127 move_register (treg, tempreg);
8141 load_address (AT, &offset_expr, &used_at);
8143 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8144 if (! target_big_endian)
8145 expr1.X_add_number = off;
8147 expr1.X_add_number = 0;
8148 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8149 if (! target_big_endian)
8150 expr1.X_add_number = 0;
8152 expr1.X_add_number = off;
8153 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8159 load_address (AT, &offset_expr, &used_at);
8161 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8162 if (target_big_endian)
8163 expr1.X_add_number = 0;
8164 macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
8165 treg, BFD_RELOC_LO16, AT);
8166 if (target_big_endian)
8167 expr1.X_add_number = 1;
8169 expr1.X_add_number = 0;
8170 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
8171 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
8172 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8177 if (offset_expr.X_add_number >= 0x7fff)
8178 as_bad (_("operand overflow"));
8179 if (target_big_endian)
8180 ++offset_expr.X_add_number;
8181 macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg);
8182 macro_build (NULL, "srl", "d,w,<", AT, treg, 8);
8183 if (target_big_endian)
8184 --offset_expr.X_add_number;
8186 ++offset_expr.X_add_number;
8187 macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg);
8200 if (offset_expr.X_add_number >= 0x8000 - off)
8201 as_bad (_("operand overflow"));
8202 if (! target_big_endian)
8203 offset_expr.X_add_number += off;
8204 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8205 if (! target_big_endian)
8206 offset_expr.X_add_number -= off;
8208 offset_expr.X_add_number += off;
8209 macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8223 load_address (AT, &offset_expr, &used_at);
8225 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8226 if (! target_big_endian)
8227 expr1.X_add_number = off;
8229 expr1.X_add_number = 0;
8230 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8231 if (! target_big_endian)
8232 expr1.X_add_number = 0;
8234 expr1.X_add_number = off;
8235 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8240 load_address (AT, &offset_expr, &used_at);
8242 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8243 if (! target_big_endian)
8244 expr1.X_add_number = 0;
8245 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8246 macro_build (NULL, "srl", "d,w,<", treg, treg, 8);
8247 if (! target_big_endian)
8248 expr1.X_add_number = 1;
8250 expr1.X_add_number = 0;
8251 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8252 if (! target_big_endian)
8253 expr1.X_add_number = 0;
8255 expr1.X_add_number = 1;
8256 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
8257 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
8258 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8262 /* FIXME: Check if this is one of the itbl macros, since they
8263 are added dynamically. */
8264 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
8267 if (!mips_opts.at && used_at)
8268 as_bad (_("Macro used $at after \".set noat\""));
8271 /* Implement macros in mips16 mode. */
8274 mips16_macro (struct mips_cl_insn *ip)
8277 int xreg, yreg, zreg, tmp;
8280 const char *s, *s2, *s3;
8282 mask = ip->insn_mo->mask;
8284 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
8285 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
8286 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
8288 expr1.X_op = O_constant;
8289 expr1.X_op_symbol = NULL;
8290 expr1.X_add_symbol = NULL;
8291 expr1.X_add_number = 1;
8311 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
8312 expr1.X_add_number = 2;
8313 macro_build (&expr1, "bnez", "x,p", yreg);
8314 macro_build (NULL, "break", "6", 7);
8316 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
8317 since that causes an overflow. We should do that as well,
8318 but I don't see how to do the comparisons without a temporary
8321 macro_build (NULL, s, "x", zreg);
8341 macro_build (NULL, s, "0,x,y", xreg, yreg);
8342 expr1.X_add_number = 2;
8343 macro_build (&expr1, "bnez", "x,p", yreg);
8344 macro_build (NULL, "break", "6", 7);
8346 macro_build (NULL, s2, "x", zreg);
8352 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
8353 macro_build (NULL, "mflo", "x", zreg);
8361 if (imm_expr.X_op != O_constant)
8362 as_bad (_("Unsupported large constant"));
8363 imm_expr.X_add_number = -imm_expr.X_add_number;
8364 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
8368 if (imm_expr.X_op != O_constant)
8369 as_bad (_("Unsupported large constant"));
8370 imm_expr.X_add_number = -imm_expr.X_add_number;
8371 macro_build (&imm_expr, "addiu", "x,k", xreg);
8375 if (imm_expr.X_op != O_constant)
8376 as_bad (_("Unsupported large constant"));
8377 imm_expr.X_add_number = -imm_expr.X_add_number;
8378 macro_build (&imm_expr, "daddiu", "y,j", yreg);
8400 goto do_reverse_branch;
8404 goto do_reverse_branch;
8416 goto do_reverse_branch;
8427 macro_build (NULL, s, "x,y", xreg, yreg);
8428 macro_build (&offset_expr, s2, "p");
8455 goto do_addone_branch_i;
8460 goto do_addone_branch_i;
8475 goto do_addone_branch_i;
8482 if (imm_expr.X_op != O_constant)
8483 as_bad (_("Unsupported large constant"));
8484 ++imm_expr.X_add_number;
8487 macro_build (&imm_expr, s, s3, xreg);
8488 macro_build (&offset_expr, s2, "p");
8492 expr1.X_add_number = 0;
8493 macro_build (&expr1, "slti", "x,8", yreg);
8495 move_register (xreg, yreg);
8496 expr1.X_add_number = 2;
8497 macro_build (&expr1, "bteqz", "p");
8498 macro_build (NULL, "neg", "x,w", xreg, xreg);
8502 /* For consistency checking, verify that all bits are specified either
8503 by the match/mask part of the instruction definition, or by the
8506 validate_mips_insn (const struct mips_opcode *opc)
8508 const char *p = opc->args;
8510 unsigned long used_bits = opc->mask;
8512 if ((used_bits & opc->match) != opc->match)
8514 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8515 opc->name, opc->args);
8518 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8528 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
8529 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
8530 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
8531 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
8532 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8533 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8534 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8535 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
8536 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8537 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8538 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8539 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8540 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8542 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8543 case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
8544 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8545 case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
8546 case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
8547 case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
8548 case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
8549 case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
8550 case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
8551 case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
8554 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8555 c, opc->name, opc->args);
8559 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8560 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8562 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
8563 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
8564 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8565 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8567 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8568 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8570 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
8571 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8573 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
8574 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
8575 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
8576 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
8577 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8578 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
8579 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8580 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8581 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8582 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8583 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8584 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8585 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8586 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
8587 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8588 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
8589 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8591 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
8592 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8593 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8594 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
8596 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8597 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8598 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
8599 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8600 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8601 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8602 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8603 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8604 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8607 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
8608 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
8609 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8610 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
8611 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
8614 case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8615 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
8616 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
8617 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
8618 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
8619 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8620 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
8621 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
8622 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
8623 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
8624 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
8625 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
8626 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
8627 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
8628 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
8629 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
8630 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
8631 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8633 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8634 c, opc->name, opc->args);
8638 if (used_bits != 0xffffffff)
8640 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8641 ~used_bits & 0xffffffff, opc->name, opc->args);
8647 /* UDI immediates. */
8655 static const struct mips_immed mips_immed[] = {
8656 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
8657 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
8658 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
8659 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
8663 /* Check whether an odd floating-point register is allowed. */
8665 mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
8667 const char *s = insn->name;
8669 if (insn->pinfo == INSN_MACRO)
8670 /* Let a macro pass, we'll catch it later when it is expanded. */
8673 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa))
8675 /* Allow odd registers for single-precision ops. */
8676 switch (insn->pinfo & (FP_S | FP_D))
8680 return 1; /* both single precision - ok */
8682 return 0; /* both double precision - fail */
8687 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
8688 s = strchr (insn->name, '.');
8690 s = s != NULL ? strchr (s + 1, '.') : NULL;
8691 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
8694 /* Single-precision coprocessor loads and moves are OK too. */
8695 if ((insn->pinfo & FP_S)
8696 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
8697 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
8703 /* This routine assembles an instruction into its binary format. As a
8704 side effect, it sets one of the global variables imm_reloc or
8705 offset_reloc to the type of relocation to do if one of the operands
8706 is an address expression. */
8709 mips_ip (char *str, struct mips_cl_insn *ip)
8714 struct mips_opcode *insn;
8717 unsigned int lastregno = 0;
8718 unsigned int lastpos = 0;
8719 unsigned int limlo, limhi;
8722 offsetT min_range, max_range;
8728 /* If the instruction contains a '.', we first try to match an instruction
8729 including the '.'. Then we try again without the '.'. */
8731 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
8734 /* If we stopped on whitespace, then replace the whitespace with null for
8735 the call to hash_find. Save the character we replaced just in case we
8736 have to re-parse the instruction. */
8743 insn = (struct mips_opcode *) hash_find (op_hash, str);
8745 /* If we didn't find the instruction in the opcode table, try again, but
8746 this time with just the instruction up to, but not including the
8750 /* Restore the character we overwrite above (if any). */
8754 /* Scan up to the first '.' or whitespace. */
8756 *s != '\0' && *s != '.' && !ISSPACE (*s);
8760 /* If we did not find a '.', then we can quit now. */
8763 insn_error = "unrecognized opcode";
8767 /* Lookup the instruction in the hash table. */
8769 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
8771 insn_error = "unrecognized opcode";
8781 assert (strcmp (insn->name, str) == 0);
8783 ok = is_opcode_valid (insn, FALSE);
8786 if (insn + 1 < &mips_opcodes[NUMOPCODES]
8787 && strcmp (insn->name, insn[1].name) == 0)
8796 static char buf[100];
8798 _("opcode not supported on this processor: %s (%s)"),
8799 mips_cpu_info_from_arch (mips_opts.arch)->name,
8800 mips_cpu_info_from_isa (mips_opts.isa)->name);
8809 create_insn (ip, insn);
8812 lastregno = 0xffffffff;
8813 for (args = insn->args;; ++args)
8817 s += strspn (s, " \t");
8821 case '\0': /* end of args */
8826 case '2': /* dsp 2-bit unsigned immediate in bit 11 */
8827 my_getExpression (&imm_expr, s);
8828 check_absolute_expr (ip, &imm_expr);
8829 if ((unsigned long) imm_expr.X_add_number != 1
8830 && (unsigned long) imm_expr.X_add_number != 3)
8832 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
8833 (unsigned long) imm_expr.X_add_number);
8835 INSERT_OPERAND (BP, *ip, imm_expr.X_add_number);
8836 imm_expr.X_op = O_absent;
8840 case '3': /* dsp 3-bit unsigned immediate in bit 21 */
8841 my_getExpression (&imm_expr, s);
8842 check_absolute_expr (ip, &imm_expr);
8843 if (imm_expr.X_add_number & ~OP_MASK_SA3)
8845 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8846 OP_MASK_SA3, (unsigned long) imm_expr.X_add_number);
8848 INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number);
8849 imm_expr.X_op = O_absent;
8853 case '4': /* dsp 4-bit unsigned immediate in bit 21 */
8854 my_getExpression (&imm_expr, s);
8855 check_absolute_expr (ip, &imm_expr);
8856 if (imm_expr.X_add_number & ~OP_MASK_SA4)
8858 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8859 OP_MASK_SA4, (unsigned long) imm_expr.X_add_number);
8861 INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number);
8862 imm_expr.X_op = O_absent;
8866 case '5': /* dsp 8-bit unsigned immediate in bit 16 */
8867 my_getExpression (&imm_expr, s);
8868 check_absolute_expr (ip, &imm_expr);
8869 if (imm_expr.X_add_number & ~OP_MASK_IMM8)
8871 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8872 OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number);
8874 INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number);
8875 imm_expr.X_op = O_absent;
8879 case '6': /* dsp 5-bit unsigned immediate in bit 21 */
8880 my_getExpression (&imm_expr, s);
8881 check_absolute_expr (ip, &imm_expr);
8882 if (imm_expr.X_add_number & ~OP_MASK_RS)
8884 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8885 OP_MASK_RS, (unsigned long) imm_expr.X_add_number);
8887 INSERT_OPERAND (RS, *ip, imm_expr.X_add_number);
8888 imm_expr.X_op = O_absent;
8892 case '7': /* four dsp accumulators in bits 11,12 */
8893 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8894 s[3] >= '0' && s[3] <= '3')
8898 INSERT_OPERAND (DSPACC, *ip, regno);
8902 as_bad (_("Invalid dsp acc register"));
8905 case '8': /* dsp 6-bit unsigned immediate in bit 11 */
8906 my_getExpression (&imm_expr, s);
8907 check_absolute_expr (ip, &imm_expr);
8908 if (imm_expr.X_add_number & ~OP_MASK_WRDSP)
8910 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8912 (unsigned long) imm_expr.X_add_number);
8914 INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number);
8915 imm_expr.X_op = O_absent;
8919 case '9': /* four dsp accumulators in bits 21,22 */
8920 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8921 s[3] >= '0' && s[3] <= '3')
8925 INSERT_OPERAND (DSPACC_S, *ip, regno);
8929 as_bad (_("Invalid dsp acc register"));
8932 case '0': /* dsp 6-bit signed immediate in bit 20 */
8933 my_getExpression (&imm_expr, s);
8934 check_absolute_expr (ip, &imm_expr);
8935 min_range = -((OP_MASK_DSPSFT + 1) >> 1);
8936 max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1;
8937 if (imm_expr.X_add_number < min_range ||
8938 imm_expr.X_add_number > max_range)
8940 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8941 (long) min_range, (long) max_range,
8942 (long) imm_expr.X_add_number);
8944 INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number);
8945 imm_expr.X_op = O_absent;
8949 case '\'': /* dsp 6-bit unsigned immediate in bit 16 */
8950 my_getExpression (&imm_expr, s);
8951 check_absolute_expr (ip, &imm_expr);
8952 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
8954 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8956 (unsigned long) imm_expr.X_add_number);
8958 INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number);
8959 imm_expr.X_op = O_absent;
8963 case ':': /* dsp 7-bit signed immediate in bit 19 */
8964 my_getExpression (&imm_expr, s);
8965 check_absolute_expr (ip, &imm_expr);
8966 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
8967 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
8968 if (imm_expr.X_add_number < min_range ||
8969 imm_expr.X_add_number > max_range)
8971 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8972 (long) min_range, (long) max_range,
8973 (long) imm_expr.X_add_number);
8975 INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number);
8976 imm_expr.X_op = O_absent;
8980 case '@': /* dsp 10-bit signed immediate in bit 16 */
8981 my_getExpression (&imm_expr, s);
8982 check_absolute_expr (ip, &imm_expr);
8983 min_range = -((OP_MASK_IMM10 + 1) >> 1);
8984 max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1;
8985 if (imm_expr.X_add_number < min_range ||
8986 imm_expr.X_add_number > max_range)
8988 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8989 (long) min_range, (long) max_range,
8990 (long) imm_expr.X_add_number);
8992 INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number);
8993 imm_expr.X_op = O_absent;
8997 case '!': /* MT usermode flag bit. */
8998 my_getExpression (&imm_expr, s);
8999 check_absolute_expr (ip, &imm_expr);
9000 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
9001 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
9002 (unsigned long) imm_expr.X_add_number);
9003 INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number);
9004 imm_expr.X_op = O_absent;
9008 case '$': /* MT load high flag bit. */
9009 my_getExpression (&imm_expr, s);
9010 check_absolute_expr (ip, &imm_expr);
9011 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
9012 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
9013 (unsigned long) imm_expr.X_add_number);
9014 INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number);
9015 imm_expr.X_op = O_absent;
9019 case '*': /* four dsp accumulators in bits 18,19 */
9020 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9021 s[3] >= '0' && s[3] <= '3')
9025 INSERT_OPERAND (MTACC_T, *ip, regno);
9029 as_bad (_("Invalid dsp/smartmips acc register"));
9032 case '&': /* four dsp accumulators in bits 13,14 */
9033 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9034 s[3] >= '0' && s[3] <= '3')
9038 INSERT_OPERAND (MTACC_D, *ip, regno);
9042 as_bad (_("Invalid dsp/smartmips acc register"));
9054 INSERT_OPERAND (RS, *ip, lastregno);
9058 INSERT_OPERAND (RT, *ip, lastregno);
9062 INSERT_OPERAND (FT, *ip, lastregno);
9066 INSERT_OPERAND (FS, *ip, lastregno);
9072 /* Handle optional base register.
9073 Either the base register is omitted or
9074 we must have a left paren. */
9075 /* This is dependent on the next operand specifier
9076 is a base register specification. */
9077 assert (args[1] == 'b' || args[1] == '5'
9078 || args[1] == '-' || args[1] == '4');
9082 case ')': /* these must match exactly */
9089 case '+': /* Opcode extension character. */
9092 case '1': /* UDI immediates. */
9097 const struct mips_immed *imm = mips_immed;
9099 while (imm->type && imm->type != *args)
9103 my_getExpression (&imm_expr, s);
9104 check_absolute_expr (ip, &imm_expr);
9105 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
9107 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
9108 imm->desc ? imm->desc : ip->insn_mo->name,
9109 (unsigned long) imm_expr.X_add_number,
9110 (unsigned long) imm_expr.X_add_number);
9111 imm_expr.X_add_number &= imm->mask;
9113 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
9115 imm_expr.X_op = O_absent;
9120 case 'A': /* ins/ext position, becomes LSB. */
9129 my_getExpression (&imm_expr, s);
9130 check_absolute_expr (ip, &imm_expr);
9131 if ((unsigned long) imm_expr.X_add_number < limlo
9132 || (unsigned long) imm_expr.X_add_number > limhi)
9134 as_bad (_("Improper position (%lu)"),
9135 (unsigned long) imm_expr.X_add_number);
9136 imm_expr.X_add_number = limlo;
9138 lastpos = imm_expr.X_add_number;
9139 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9140 imm_expr.X_op = O_absent;
9144 case 'B': /* ins size, becomes MSB. */
9153 my_getExpression (&imm_expr, s);
9154 check_absolute_expr (ip, &imm_expr);
9155 /* Check for negative input so that small negative numbers
9156 will not succeed incorrectly. The checks against
9157 (pos+size) transitively check "size" itself,
9158 assuming that "pos" is reasonable. */
9159 if ((long) imm_expr.X_add_number < 0
9160 || ((unsigned long) imm_expr.X_add_number
9162 || ((unsigned long) imm_expr.X_add_number
9165 as_bad (_("Improper insert size (%lu, position %lu)"),
9166 (unsigned long) imm_expr.X_add_number,
9167 (unsigned long) lastpos);
9168 imm_expr.X_add_number = limlo - lastpos;
9170 INSERT_OPERAND (INSMSB, *ip,
9171 lastpos + imm_expr.X_add_number - 1);
9172 imm_expr.X_op = O_absent;
9176 case 'C': /* ext size, becomes MSBD. */
9189 my_getExpression (&imm_expr, s);
9190 check_absolute_expr (ip, &imm_expr);
9191 /* Check for negative input so that small negative numbers
9192 will not succeed incorrectly. The checks against
9193 (pos+size) transitively check "size" itself,
9194 assuming that "pos" is reasonable. */
9195 if ((long) imm_expr.X_add_number < 0
9196 || ((unsigned long) imm_expr.X_add_number
9198 || ((unsigned long) imm_expr.X_add_number
9201 as_bad (_("Improper extract size (%lu, position %lu)"),
9202 (unsigned long) imm_expr.X_add_number,
9203 (unsigned long) lastpos);
9204 imm_expr.X_add_number = limlo - lastpos;
9206 INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1);
9207 imm_expr.X_op = O_absent;
9212 /* +D is for disassembly only; never match. */
9216 /* "+I" is like "I", except that imm2_expr is used. */
9217 my_getExpression (&imm2_expr, s);
9218 if (imm2_expr.X_op != O_big
9219 && imm2_expr.X_op != O_constant)
9220 insn_error = _("absolute expression required");
9221 if (HAVE_32BIT_GPRS)
9222 normalize_constant_expr (&imm2_expr);
9226 case 'T': /* Coprocessor register. */
9227 /* +T is for disassembly only; never match. */
9230 case 't': /* Coprocessor register number. */
9231 if (s[0] == '$' && ISDIGIT (s[1]))
9241 while (ISDIGIT (*s));
9243 as_bad (_("Invalid register number (%d)"), regno);
9246 INSERT_OPERAND (RT, *ip, regno);
9251 as_bad (_("Invalid coprocessor 0 register number"));
9255 /* bbit[01] and bbit[01]32 bit index. Give error if index
9256 is not in the valid range. */
9257 my_getExpression (&imm_expr, s);
9258 check_absolute_expr (ip, &imm_expr);
9259 if ((unsigned) imm_expr.X_add_number > 31)
9261 as_bad (_("Improper bit index (%lu)"),
9262 (unsigned long) imm_expr.X_add_number);
9263 imm_expr.X_add_number = 0;
9265 INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number);
9266 imm_expr.X_op = O_absent;
9271 /* bbit[01] bit index when bbit is used but we generate
9272 bbit[01]32 because the index is over 32. Move to the
9273 next candidate if index is not in the valid range. */
9274 my_getExpression (&imm_expr, s);
9275 check_absolute_expr (ip, &imm_expr);
9276 if ((unsigned) imm_expr.X_add_number < 32
9277 || (unsigned) imm_expr.X_add_number > 63)
9279 INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number - 32);
9280 imm_expr.X_op = O_absent;
9285 /* cins, cins32, exts and exts32 position field. Give error
9286 if it's not in the valid range. */
9287 my_getExpression (&imm_expr, s);
9288 check_absolute_expr (ip, &imm_expr);
9289 if ((unsigned) imm_expr.X_add_number > 31)
9291 as_bad (_("Improper position (%lu)"),
9292 (unsigned long) imm_expr.X_add_number);
9293 imm_expr.X_add_number = 0;
9295 /* Make the pos explicit to simplify +S. */
9296 lastpos = imm_expr.X_add_number + 32;
9297 INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number);
9298 imm_expr.X_op = O_absent;
9303 /* cins, cins32, exts and exts32 position field. Move to
9304 the next candidate if it's not in the valid range. */
9305 my_getExpression (&imm_expr, s);
9306 check_absolute_expr (ip, &imm_expr);
9307 if ((unsigned) imm_expr.X_add_number < 32
9308 || (unsigned) imm_expr.X_add_number > 63)
9310 lastpos = imm_expr.X_add_number;
9311 INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number - 32);
9312 imm_expr.X_op = O_absent;
9317 /* cins and exts length-minus-one field. */
9318 my_getExpression (&imm_expr, s);
9319 check_absolute_expr (ip, &imm_expr);
9320 if ((unsigned long) imm_expr.X_add_number > 31)
9322 as_bad (_("Improper size (%lu)"),
9323 (unsigned long) imm_expr.X_add_number);
9324 imm_expr.X_add_number = 0;
9326 INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number);
9327 imm_expr.X_op = O_absent;
9332 /* cins32/exts32 and cins/exts aliasing cint32/exts32
9333 length-minus-one field. */
9334 my_getExpression (&imm_expr, s);
9335 check_absolute_expr (ip, &imm_expr);
9336 if ((long) imm_expr.X_add_number < 0
9337 || (unsigned long) imm_expr.X_add_number + lastpos > 63)
9339 as_bad (_("Improper size (%lu)"),
9340 (unsigned long) imm_expr.X_add_number);
9341 imm_expr.X_add_number = 0;
9343 INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number);
9344 imm_expr.X_op = O_absent;
9349 /* seqi/snei immediate field. */
9350 my_getExpression (&imm_expr, s);
9351 check_absolute_expr (ip, &imm_expr);
9352 if ((long) imm_expr.X_add_number < -512
9353 || (long) imm_expr.X_add_number >= 512)
9355 as_bad (_("Improper immediate (%ld)"),
9356 (long) imm_expr.X_add_number);
9357 imm_expr.X_add_number = 0;
9359 INSERT_OPERAND (SEQI, *ip, imm_expr.X_add_number);
9360 imm_expr.X_op = O_absent;
9365 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
9366 *args, insn->name, insn->args);
9367 /* Further processing is fruitless. */
9372 case '<': /* must be at least one digit */
9374 * According to the manual, if the shift amount is greater
9375 * than 31 or less than 0, then the shift amount should be
9376 * mod 32. In reality the mips assembler issues an error.
9377 * We issue a warning and mask out all but the low 5 bits.
9379 my_getExpression (&imm_expr, s);
9380 check_absolute_expr (ip, &imm_expr);
9381 if ((unsigned long) imm_expr.X_add_number > 31)
9382 as_warn (_("Improper shift amount (%lu)"),
9383 (unsigned long) imm_expr.X_add_number);
9384 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9385 imm_expr.X_op = O_absent;
9389 case '>': /* shift amount minus 32 */
9390 my_getExpression (&imm_expr, s);
9391 check_absolute_expr (ip, &imm_expr);
9392 if ((unsigned long) imm_expr.X_add_number < 32
9393 || (unsigned long) imm_expr.X_add_number > 63)
9395 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32);
9396 imm_expr.X_op = O_absent;
9400 case 'k': /* cache code */
9401 case 'h': /* prefx code */
9402 case '1': /* sync type */
9403 my_getExpression (&imm_expr, s);
9404 check_absolute_expr (ip, &imm_expr);
9405 if ((unsigned long) imm_expr.X_add_number > 31)
9406 as_warn (_("Invalid value for `%s' (%lu)"),
9408 (unsigned long) imm_expr.X_add_number);
9410 INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number);
9411 else if (*args == 'h')
9412 INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number);
9414 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9415 imm_expr.X_op = O_absent;
9419 case 'c': /* break code */
9420 my_getExpression (&imm_expr, s);
9421 check_absolute_expr (ip, &imm_expr);
9422 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE)
9423 as_warn (_("Code for %s not in range 0..1023 (%lu)"),
9425 (unsigned long) imm_expr.X_add_number);
9426 INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number);
9427 imm_expr.X_op = O_absent;
9431 case 'q': /* lower break code */
9432 my_getExpression (&imm_expr, s);
9433 check_absolute_expr (ip, &imm_expr);
9434 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2)
9435 as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
9437 (unsigned long) imm_expr.X_add_number);
9438 INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number);
9439 imm_expr.X_op = O_absent;
9443 case 'B': /* 20-bit syscall/break code. */
9444 my_getExpression (&imm_expr, s);
9445 check_absolute_expr (ip, &imm_expr);
9446 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
9447 as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
9449 (unsigned long) imm_expr.X_add_number);
9450 INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number);
9451 imm_expr.X_op = O_absent;
9455 case 'C': /* Coprocessor code */
9456 my_getExpression (&imm_expr, s);
9457 check_absolute_expr (ip, &imm_expr);
9458 if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ)
9460 as_warn (_("Coproccesor code > 25 bits (%lu)"),
9461 (unsigned long) imm_expr.X_add_number);
9462 imm_expr.X_add_number &= OP_MASK_COPZ;
9464 INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number);
9465 imm_expr.X_op = O_absent;
9469 case 'J': /* 19-bit wait code. */
9470 my_getExpression (&imm_expr, s);
9471 check_absolute_expr (ip, &imm_expr);
9472 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
9474 as_warn (_("Illegal 19-bit code (%lu)"),
9475 (unsigned long) imm_expr.X_add_number);
9476 imm_expr.X_add_number &= OP_MASK_CODE19;
9478 INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number);
9479 imm_expr.X_op = O_absent;
9483 case 'P': /* Performance register. */
9484 my_getExpression (&imm_expr, s);
9485 check_absolute_expr (ip, &imm_expr);
9486 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
9487 as_warn (_("Invalid performance register (%lu)"),
9488 (unsigned long) imm_expr.X_add_number);
9489 INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number);
9490 imm_expr.X_op = O_absent;
9494 case 'G': /* Coprocessor destination register. */
9495 if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0)
9496 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, ®no);
9498 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
9499 INSERT_OPERAND (RD, *ip, regno);
9508 case 'b': /* base register */
9509 case 'd': /* destination register */
9510 case 's': /* source register */
9511 case 't': /* target register */
9512 case 'r': /* both target and source */
9513 case 'v': /* both dest and source */
9514 case 'w': /* both dest and target */
9515 case 'E': /* coprocessor target register */
9516 case 'K': /* 'rdhwr' destination register */
9517 case 'x': /* ignore register name */
9518 case 'z': /* must be zero register */
9519 case 'U': /* destination register (clo/clz). */
9520 case 'g': /* coprocessor destination register */
9522 if (*args == 'E' || *args == 'K')
9523 ok = reg_lookup (&s, RTYPE_NUM, ®no);
9526 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
9527 if (regno == AT && mips_opts.at)
9529 if (mips_opts.at == ATREG)
9530 as_warn (_("used $at without \".set noat\""));
9532 as_warn (_("used $%u with \".set at=$%u\""),
9533 regno, mips_opts.at);
9543 if (c == 'r' || c == 'v' || c == 'w')
9550 /* 'z' only matches $0. */
9551 if (c == 'z' && regno != 0)
9554 if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
9556 if (regno == lastregno)
9558 insn_error = _("source and destination must be different");
9561 if (regno == 31 && lastregno == 0xffffffff)
9563 insn_error = _("a destination register must be supplied");
9567 /* Now that we have assembled one operand, we use the args string
9568 * to figure out where it goes in the instruction. */
9575 INSERT_OPERAND (RS, *ip, regno);
9581 INSERT_OPERAND (RD, *ip, regno);
9584 INSERT_OPERAND (RD, *ip, regno);
9585 INSERT_OPERAND (RT, *ip, regno);
9590 INSERT_OPERAND (RT, *ip, regno);
9593 /* This case exists because on the r3000 trunc
9594 expands into a macro which requires a gp
9595 register. On the r6000 or r4000 it is
9596 assembled into a single instruction which
9597 ignores the register. Thus the insn version
9598 is MIPS_ISA2 and uses 'x', and the macro
9599 version is MIPS_ISA1 and uses 't'. */
9602 /* This case is for the div instruction, which
9603 acts differently if the destination argument
9604 is $0. This only matches $0, and is checked
9605 outside the switch. */
9608 /* Itbl operand; not yet implemented. FIXME ?? */
9610 /* What about all other operands like 'i', which
9611 can be specified in the opcode table? */
9620 INSERT_OPERAND (RS, *ip, lastregno);
9623 INSERT_OPERAND (RT, *ip, lastregno);
9628 case 'O': /* MDMX alignment immediate constant. */
9629 my_getExpression (&imm_expr, s);
9630 check_absolute_expr (ip, &imm_expr);
9631 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
9632 as_warn ("Improper align amount (%ld), using low bits",
9633 (long) imm_expr.X_add_number);
9634 INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number);
9635 imm_expr.X_op = O_absent;
9639 case 'Q': /* MDMX vector, element sel, or const. */
9642 /* MDMX Immediate. */
9643 my_getExpression (&imm_expr, s);
9644 check_absolute_expr (ip, &imm_expr);
9645 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
9646 as_warn (_("Invalid MDMX Immediate (%ld)"),
9647 (long) imm_expr.X_add_number);
9648 INSERT_OPERAND (FT, *ip, imm_expr.X_add_number);
9649 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
9650 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
9652 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
9653 imm_expr.X_op = O_absent;
9657 /* Not MDMX Immediate. Fall through. */
9658 case 'X': /* MDMX destination register. */
9659 case 'Y': /* MDMX source register. */
9660 case 'Z': /* MDMX target register. */
9662 case 'D': /* floating point destination register */
9663 case 'S': /* floating point source register */
9664 case 'T': /* floating point target register */
9665 case 'R': /* floating point source register */
9670 || (mips_opts.ase_mdmx
9671 && (ip->insn_mo->pinfo & FP_D)
9672 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
9673 | INSN_COPROC_MEMORY_DELAY
9674 | INSN_LOAD_COPROC_DELAY
9675 | INSN_LOAD_MEMORY_DELAY
9676 | INSN_STORE_MEMORY))))
9679 if (reg_lookup (&s, rtype, ®no))
9681 if ((regno & 1) != 0
9683 && ! mips_oddfpreg_ok (ip->insn_mo, argnum))
9684 as_warn (_("Float register should be even, was %d"),
9692 if (c == 'V' || c == 'W')
9703 INSERT_OPERAND (FD, *ip, regno);
9708 INSERT_OPERAND (FS, *ip, regno);
9711 /* This is like 'Z', but also needs to fix the MDMX
9712 vector/scalar select bits. Note that the
9713 scalar immediate case is handled above. */
9716 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
9717 int max_el = (is_qh ? 3 : 7);
9719 my_getExpression(&imm_expr, s);
9720 check_absolute_expr (ip, &imm_expr);
9722 if (imm_expr.X_add_number > max_el)
9723 as_bad(_("Bad element selector %ld"),
9724 (long) imm_expr.X_add_number);
9725 imm_expr.X_add_number &= max_el;
9726 ip->insn_opcode |= (imm_expr.X_add_number
9729 imm_expr.X_op = O_absent;
9731 as_warn(_("Expecting ']' found '%s'"), s);
9737 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
9738 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
9741 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
9748 INSERT_OPERAND (FT, *ip, regno);
9751 INSERT_OPERAND (FR, *ip, regno);
9761 INSERT_OPERAND (FS, *ip, lastregno);
9764 INSERT_OPERAND (FT, *ip, lastregno);
9770 my_getExpression (&imm_expr, s);
9771 if (imm_expr.X_op != O_big
9772 && imm_expr.X_op != O_constant)
9773 insn_error = _("absolute expression required");
9774 if (HAVE_32BIT_GPRS)
9775 normalize_constant_expr (&imm_expr);
9780 my_getExpression (&offset_expr, s);
9781 normalize_address_expr (&offset_expr);
9782 *imm_reloc = BFD_RELOC_32;
9795 unsigned char temp[8];
9797 unsigned int length;
9802 /* These only appear as the last operand in an
9803 instruction, and every instruction that accepts
9804 them in any variant accepts them in all variants.
9805 This means we don't have to worry about backing out
9806 any changes if the instruction does not match.
9808 The difference between them is the size of the
9809 floating point constant and where it goes. For 'F'
9810 and 'L' the constant is 64 bits; for 'f' and 'l' it
9811 is 32 bits. Where the constant is placed is based
9812 on how the MIPS assembler does things:
9815 f -- immediate value
9818 The .lit4 and .lit8 sections are only used if
9819 permitted by the -G argument.
9821 The code below needs to know whether the target register
9822 is 32 or 64 bits wide. It relies on the fact 'f' and
9823 'F' are used with GPR-based instructions and 'l' and
9824 'L' are used with FPR-based instructions. */
9826 f64 = *args == 'F' || *args == 'L';
9827 using_gprs = *args == 'F' || *args == 'f';
9829 save_in = input_line_pointer;
9830 input_line_pointer = s;
9831 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
9833 s = input_line_pointer;
9834 input_line_pointer = save_in;
9835 if (err != NULL && *err != '\0')
9837 as_bad (_("Bad floating point constant: %s"), err);
9838 memset (temp, '\0', sizeof temp);
9839 length = f64 ? 8 : 4;
9842 assert (length == (unsigned) (f64 ? 8 : 4));
9846 && (g_switch_value < 4
9847 || (temp[0] == 0 && temp[1] == 0)
9848 || (temp[2] == 0 && temp[3] == 0))))
9850 imm_expr.X_op = O_constant;
9851 if (! target_big_endian)
9852 imm_expr.X_add_number = bfd_getl32 (temp);
9854 imm_expr.X_add_number = bfd_getb32 (temp);
9857 && ! mips_disable_float_construction
9858 /* Constants can only be constructed in GPRs and
9859 copied to FPRs if the GPRs are at least as wide
9860 as the FPRs. Force the constant into memory if
9861 we are using 64-bit FPRs but the GPRs are only
9864 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
9865 && ((temp[0] == 0 && temp[1] == 0)
9866 || (temp[2] == 0 && temp[3] == 0))
9867 && ((temp[4] == 0 && temp[5] == 0)
9868 || (temp[6] == 0 && temp[7] == 0)))
9870 /* The value is simple enough to load with a couple of
9871 instructions. If using 32-bit registers, set
9872 imm_expr to the high order 32 bits and offset_expr to
9873 the low order 32 bits. Otherwise, set imm_expr to
9874 the entire 64 bit constant. */
9875 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
9877 imm_expr.X_op = O_constant;
9878 offset_expr.X_op = O_constant;
9879 if (! target_big_endian)
9881 imm_expr.X_add_number = bfd_getl32 (temp + 4);
9882 offset_expr.X_add_number = bfd_getl32 (temp);
9886 imm_expr.X_add_number = bfd_getb32 (temp);
9887 offset_expr.X_add_number = bfd_getb32 (temp + 4);
9889 if (offset_expr.X_add_number == 0)
9890 offset_expr.X_op = O_absent;
9892 else if (sizeof (imm_expr.X_add_number) > 4)
9894 imm_expr.X_op = O_constant;
9895 if (! target_big_endian)
9896 imm_expr.X_add_number = bfd_getl64 (temp);
9898 imm_expr.X_add_number = bfd_getb64 (temp);
9902 imm_expr.X_op = O_big;
9903 imm_expr.X_add_number = 4;
9904 if (! target_big_endian)
9906 generic_bignum[0] = bfd_getl16 (temp);
9907 generic_bignum[1] = bfd_getl16 (temp + 2);
9908 generic_bignum[2] = bfd_getl16 (temp + 4);
9909 generic_bignum[3] = bfd_getl16 (temp + 6);
9913 generic_bignum[0] = bfd_getb16 (temp + 6);
9914 generic_bignum[1] = bfd_getb16 (temp + 4);
9915 generic_bignum[2] = bfd_getb16 (temp + 2);
9916 generic_bignum[3] = bfd_getb16 (temp);
9922 const char *newname;
9925 /* Switch to the right section. */
9927 subseg = now_subseg;
9930 default: /* unused default case avoids warnings. */
9932 newname = RDATA_SECTION_NAME;
9933 if (g_switch_value >= 8)
9937 newname = RDATA_SECTION_NAME;
9940 assert (g_switch_value >= 4);
9944 new_seg = subseg_new (newname, (subsegT) 0);
9946 bfd_set_section_flags (stdoutput, new_seg,
9951 frag_align (*args == 'l' ? 2 : 3, 0, 0);
9952 if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0)
9953 record_alignment (new_seg, 4);
9955 record_alignment (new_seg, *args == 'l' ? 2 : 3);
9957 as_bad (_("Can't use floating point insn in this section"));
9959 /* Set the argument to the current address in the
9961 offset_expr.X_op = O_symbol;
9962 offset_expr.X_add_symbol =
9963 symbol_new ("L0\001", now_seg,
9964 (valueT) frag_now_fix (), frag_now);
9965 offset_expr.X_add_number = 0;
9967 /* Put the floating point number into the section. */
9968 p = frag_more ((int) length);
9969 memcpy (p, temp, length);
9971 /* Switch back to the original section. */
9972 subseg_set (seg, subseg);
9977 case 'i': /* 16 bit unsigned immediate */
9978 case 'j': /* 16 bit signed immediate */
9979 *imm_reloc = BFD_RELOC_LO16;
9980 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
9983 offsetT minval, maxval;
9985 more = (insn + 1 < &mips_opcodes[NUMOPCODES]
9986 && strcmp (insn->name, insn[1].name) == 0);
9988 /* If the expression was written as an unsigned number,
9989 only treat it as signed if there are no more
9993 && sizeof (imm_expr.X_add_number) <= 4
9994 && imm_expr.X_op == O_constant
9995 && imm_expr.X_add_number < 0
9996 && imm_expr.X_unsigned
10000 /* For compatibility with older assemblers, we accept
10001 0x8000-0xffff as signed 16-bit numbers when only
10002 signed numbers are allowed. */
10004 minval = 0, maxval = 0xffff;
10006 minval = -0x8000, maxval = 0x7fff;
10008 minval = -0x8000, maxval = 0xffff;
10010 if (imm_expr.X_op != O_constant
10011 || imm_expr.X_add_number < minval
10012 || imm_expr.X_add_number > maxval)
10016 if (imm_expr.X_op == O_constant
10017 || imm_expr.X_op == O_big)
10018 as_bad (_("expression out of range"));
10024 case 'o': /* 16 bit offset */
10025 /* Check whether there is only a single bracketed expression
10026 left. If so, it must be the base register and the
10027 constant must be zero. */
10028 if (*s == '(' && strchr (s + 1, '(') == 0)
10030 offset_expr.X_op = O_constant;
10031 offset_expr.X_add_number = 0;
10035 /* If this value won't fit into a 16 bit offset, then go
10036 find a macro that will generate the 32 bit offset
10038 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
10039 && (offset_expr.X_op != O_constant
10040 || offset_expr.X_add_number >= 0x8000
10041 || offset_expr.X_add_number < -0x8000))
10047 case 'p': /* pc relative offset */
10048 *offset_reloc = BFD_RELOC_16_PCREL_S2;
10049 my_getExpression (&offset_expr, s);
10053 case 'u': /* upper 16 bits */
10054 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
10055 && imm_expr.X_op == O_constant
10056 && (imm_expr.X_add_number < 0
10057 || imm_expr.X_add_number >= 0x10000))
10058 as_bad (_("lui expression not in range 0..65535"));
10062 case 'a': /* 26 bit address */
10063 my_getExpression (&offset_expr, s);
10065 *offset_reloc = BFD_RELOC_MIPS_JMP;
10068 case 'N': /* 3 bit branch condition code */
10069 case 'M': /* 3 bit compare condition code */
10071 if (ip->insn_mo->pinfo & (FP_D| FP_S))
10072 rtype |= RTYPE_FCC;
10073 if (!reg_lookup (&s, rtype, ®no))
10075 if ((strcmp(str + strlen(str) - 3, ".ps") == 0
10076 || strcmp(str + strlen(str) - 5, "any2f") == 0
10077 || strcmp(str + strlen(str) - 5, "any2t") == 0)
10078 && (regno & 1) != 0)
10079 as_warn(_("Condition code register should be even for %s, was %d"),
10081 if ((strcmp(str + strlen(str) - 5, "any4f") == 0
10082 || strcmp(str + strlen(str) - 5, "any4t") == 0)
10083 && (regno & 3) != 0)
10084 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
10087 INSERT_OPERAND (BCC, *ip, regno);
10089 INSERT_OPERAND (CCC, *ip, regno);
10093 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
10104 while (ISDIGIT (*s));
10107 c = 8; /* Invalid sel value. */
10110 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
10111 ip->insn_opcode |= c;
10115 /* Must be at least one digit. */
10116 my_getExpression (&imm_expr, s);
10117 check_absolute_expr (ip, &imm_expr);
10119 if ((unsigned long) imm_expr.X_add_number
10120 > (unsigned long) OP_MASK_VECBYTE)
10122 as_bad (_("bad byte vector index (%ld)"),
10123 (long) imm_expr.X_add_number);
10124 imm_expr.X_add_number = 0;
10127 INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number);
10128 imm_expr.X_op = O_absent;
10133 my_getExpression (&imm_expr, s);
10134 check_absolute_expr (ip, &imm_expr);
10136 if ((unsigned long) imm_expr.X_add_number
10137 > (unsigned long) OP_MASK_VECALIGN)
10139 as_bad (_("bad byte vector index (%ld)"),
10140 (long) imm_expr.X_add_number);
10141 imm_expr.X_add_number = 0;
10144 INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number);
10145 imm_expr.X_op = O_absent;
10150 as_bad (_("bad char = '%c'\n"), *args);
10155 /* Args don't match. */
10156 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
10157 !strcmp (insn->name, insn[1].name))
10161 insn_error = _("illegal operands");
10165 *(--argsStart) = save_c;
10166 insn_error = _("illegal operands");
10171 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
10173 /* This routine assembles an instruction into its binary format when
10174 assembling for the mips16. As a side effect, it sets one of the
10175 global variables imm_reloc or offset_reloc to the type of
10176 relocation to do if one of the operands is an address expression.
10177 It also sets mips16_small and mips16_ext if the user explicitly
10178 requested a small or extended instruction. */
10181 mips16_ip (char *str, struct mips_cl_insn *ip)
10185 struct mips_opcode *insn;
10187 unsigned int regno;
10188 unsigned int lastregno = 0;
10194 mips16_small = FALSE;
10195 mips16_ext = FALSE;
10197 for (s = str; ISLOWER (*s); ++s)
10209 if (s[1] == 't' && s[2] == ' ')
10212 mips16_small = TRUE;
10216 else if (s[1] == 'e' && s[2] == ' ')
10223 /* Fall through. */
10225 insn_error = _("unknown opcode");
10229 if (mips_opts.noautoextend && ! mips16_ext)
10230 mips16_small = TRUE;
10232 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
10234 insn_error = _("unrecognized opcode");
10243 assert (strcmp (insn->name, str) == 0);
10245 ok = is_opcode_valid_16 (insn);
10248 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
10249 && strcmp (insn->name, insn[1].name) == 0)
10258 static char buf[100];
10260 _("opcode not supported on this processor: %s (%s)"),
10261 mips_cpu_info_from_arch (mips_opts.arch)->name,
10262 mips_cpu_info_from_isa (mips_opts.isa)->name);
10269 create_insn (ip, insn);
10270 imm_expr.X_op = O_absent;
10271 imm_reloc[0] = BFD_RELOC_UNUSED;
10272 imm_reloc[1] = BFD_RELOC_UNUSED;
10273 imm_reloc[2] = BFD_RELOC_UNUSED;
10274 imm2_expr.X_op = O_absent;
10275 offset_expr.X_op = O_absent;
10276 offset_reloc[0] = BFD_RELOC_UNUSED;
10277 offset_reloc[1] = BFD_RELOC_UNUSED;
10278 offset_reloc[2] = BFD_RELOC_UNUSED;
10279 for (args = insn->args; 1; ++args)
10286 /* In this switch statement we call break if we did not find
10287 a match, continue if we did find a match, or return if we
10296 /* Stuff the immediate value in now, if we can. */
10297 if (imm_expr.X_op == O_constant
10298 && *imm_reloc > BFD_RELOC_UNUSED
10299 && *imm_reloc != BFD_RELOC_MIPS16_GOT16
10300 && *imm_reloc != BFD_RELOC_MIPS16_CALL16
10301 && insn->pinfo != INSN_MACRO)
10305 switch (*offset_reloc)
10307 case BFD_RELOC_MIPS16_HI16_S:
10308 tmp = (imm_expr.X_add_number + 0x8000) >> 16;
10311 case BFD_RELOC_MIPS16_HI16:
10312 tmp = imm_expr.X_add_number >> 16;
10315 case BFD_RELOC_MIPS16_LO16:
10316 tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff)
10320 case BFD_RELOC_UNUSED:
10321 tmp = imm_expr.X_add_number;
10327 *offset_reloc = BFD_RELOC_UNUSED;
10329 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
10330 tmp, TRUE, mips16_small,
10331 mips16_ext, &ip->insn_opcode,
10332 &ip->use_extend, &ip->extend);
10333 imm_expr.X_op = O_absent;
10334 *imm_reloc = BFD_RELOC_UNUSED;
10348 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10351 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10367 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10369 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10373 /* Fall through. */
10384 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
10386 if (c == 'v' || c == 'w')
10389 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10391 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10402 if (c == 'v' || c == 'w')
10404 regno = mips16_to_32_reg_map[lastregno];
10418 regno = mips32_to_16_reg_map[regno];
10423 regno = ILLEGAL_REG;
10428 regno = ILLEGAL_REG;
10433 regno = ILLEGAL_REG;
10438 if (regno == AT && mips_opts.at)
10440 if (mips_opts.at == ATREG)
10441 as_warn (_("used $at without \".set noat\""));
10443 as_warn (_("used $%u with \".set at=$%u\""),
10444 regno, mips_opts.at);
10452 if (regno == ILLEGAL_REG)
10459 MIPS16_INSERT_OPERAND (RX, *ip, regno);
10463 MIPS16_INSERT_OPERAND (RY, *ip, regno);
10466 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
10469 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
10475 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
10478 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
10479 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
10489 if (strncmp (s, "$pc", 3) == 0)
10506 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
10509 if (imm_expr.X_op != O_constant)
10512 ip->use_extend = TRUE;
10517 /* We need to relax this instruction. */
10518 *offset_reloc = *imm_reloc;
10519 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10524 *imm_reloc = BFD_RELOC_UNUSED;
10525 /* Fall through. */
10532 my_getExpression (&imm_expr, s);
10533 if (imm_expr.X_op == O_register)
10535 /* What we thought was an expression turned out to
10538 if (s[0] == '(' && args[1] == '(')
10540 /* It looks like the expression was omitted
10541 before a register indirection, which means
10542 that the expression is implicitly zero. We
10543 still set up imm_expr, so that we handle
10544 explicit extensions correctly. */
10545 imm_expr.X_op = O_constant;
10546 imm_expr.X_add_number = 0;
10547 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10554 /* We need to relax this instruction. */
10555 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10564 /* We use offset_reloc rather than imm_reloc for the PC
10565 relative operands. This lets macros with both
10566 immediate and address operands work correctly. */
10567 my_getExpression (&offset_expr, s);
10569 if (offset_expr.X_op == O_register)
10572 /* We need to relax this instruction. */
10573 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
10577 case '6': /* break code */
10578 my_getExpression (&imm_expr, s);
10579 check_absolute_expr (ip, &imm_expr);
10580 if ((unsigned long) imm_expr.X_add_number > 63)
10581 as_warn (_("Invalid value for `%s' (%lu)"),
10583 (unsigned long) imm_expr.X_add_number);
10584 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
10585 imm_expr.X_op = O_absent;
10589 case 'a': /* 26 bit address */
10590 my_getExpression (&offset_expr, s);
10592 *offset_reloc = BFD_RELOC_MIPS16_JMP;
10593 ip->insn_opcode <<= 16;
10596 case 'l': /* register list for entry macro */
10597 case 'L': /* register list for exit macro */
10607 unsigned int freg, reg1, reg2;
10609 while (*s == ' ' || *s == ',')
10611 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
10613 else if (reg_lookup (&s, RTYPE_FPU, ®1))
10617 as_bad (_("can't parse register list"));
10627 if (!reg_lookup (&s, freg ? RTYPE_FPU
10628 : (RTYPE_GP | RTYPE_NUM), ®2))
10630 as_bad (_("invalid register list"));
10634 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
10636 mask &= ~ (7 << 3);
10639 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
10641 mask &= ~ (7 << 3);
10644 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
10645 mask |= (reg2 - 3) << 3;
10646 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
10647 mask |= (reg2 - 15) << 1;
10648 else if (reg1 == RA && reg2 == RA)
10652 as_bad (_("invalid register list"));
10656 /* The mask is filled in in the opcode table for the
10657 benefit of the disassembler. We remove it before
10658 applying the actual mask. */
10659 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
10660 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
10664 case 'm': /* Register list for save insn. */
10665 case 'M': /* Register list for restore insn. */
10668 int framesz = 0, seen_framesz = 0;
10669 int args = 0, statics = 0, sregs = 0;
10673 unsigned int reg1, reg2;
10675 SKIP_SPACE_TABS (s);
10678 SKIP_SPACE_TABS (s);
10680 my_getExpression (&imm_expr, s);
10681 if (imm_expr.X_op == O_constant)
10683 /* Handle the frame size. */
10686 as_bad (_("more than one frame size in list"));
10690 framesz = imm_expr.X_add_number;
10691 imm_expr.X_op = O_absent;
10696 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
10698 as_bad (_("can't parse register list"));
10710 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2)
10713 as_bad (_("can't parse register list"));
10718 while (reg1 <= reg2)
10720 if (reg1 >= 4 && reg1 <= 7)
10724 args |= 1 << (reg1 - 4);
10726 /* statics $a0-$a3 */
10727 statics |= 1 << (reg1 - 4);
10729 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
10732 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
10734 else if (reg1 == 31)
10736 /* Add $ra to insn. */
10741 as_bad (_("unexpected register in list"));
10749 /* Encode args/statics combination. */
10750 if (args & statics)
10751 as_bad (_("arg/static registers overlap"));
10752 else if (args == 0xf)
10753 /* All $a0-$a3 are args. */
10754 opcode |= MIPS16_ALL_ARGS << 16;
10755 else if (statics == 0xf)
10756 /* All $a0-$a3 are statics. */
10757 opcode |= MIPS16_ALL_STATICS << 16;
10760 int narg = 0, nstat = 0;
10762 /* Count arg registers. */
10769 as_bad (_("invalid arg register list"));
10771 /* Count static registers. */
10772 while (statics & 0x8)
10774 statics = (statics << 1) & 0xf;
10778 as_bad (_("invalid static register list"));
10780 /* Encode args/statics. */
10781 opcode |= ((narg << 2) | nstat) << 16;
10784 /* Encode $s0/$s1. */
10785 if (sregs & (1 << 0)) /* $s0 */
10787 if (sregs & (1 << 1)) /* $s1 */
10793 /* Count regs $s2-$s8. */
10801 as_bad (_("invalid static register list"));
10802 /* Encode $s2-$s8. */
10803 opcode |= nsreg << 24;
10806 /* Encode frame size. */
10808 as_bad (_("missing frame size"));
10809 else if ((framesz & 7) != 0 || framesz < 0
10810 || framesz > 0xff * 8)
10811 as_bad (_("invalid frame size"));
10812 else if (framesz != 128 || (opcode >> 16) != 0)
10815 opcode |= (((framesz & 0xf0) << 16)
10816 | (framesz & 0x0f));
10819 /* Finally build the instruction. */
10820 if ((opcode >> 16) != 0 || framesz == 0)
10822 ip->use_extend = TRUE;
10823 ip->extend = opcode >> 16;
10825 ip->insn_opcode |= opcode & 0x7f;
10829 case 'e': /* extend code */
10830 my_getExpression (&imm_expr, s);
10831 check_absolute_expr (ip, &imm_expr);
10832 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
10834 as_warn (_("Invalid value for `%s' (%lu)"),
10836 (unsigned long) imm_expr.X_add_number);
10837 imm_expr.X_add_number &= 0x7ff;
10839 ip->insn_opcode |= imm_expr.X_add_number;
10840 imm_expr.X_op = O_absent;
10850 /* Args don't match. */
10851 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
10852 strcmp (insn->name, insn[1].name) == 0)
10859 insn_error = _("illegal operands");
10865 /* This structure holds information we know about a mips16 immediate
10868 struct mips16_immed_operand
10870 /* The type code used in the argument string in the opcode table. */
10872 /* The number of bits in the short form of the opcode. */
10874 /* The number of bits in the extended form of the opcode. */
10876 /* The amount by which the short form is shifted when it is used;
10877 for example, the sw instruction has a shift count of 2. */
10879 /* The amount by which the short form is shifted when it is stored
10880 into the instruction code. */
10882 /* Non-zero if the short form is unsigned. */
10884 /* Non-zero if the extended form is unsigned. */
10886 /* Non-zero if the value is PC relative. */
10890 /* The mips16 immediate operand types. */
10892 static const struct mips16_immed_operand mips16_immed_operands[] =
10894 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
10895 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
10896 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
10897 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
10898 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
10899 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
10900 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
10901 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
10902 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
10903 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
10904 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
10905 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
10906 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
10907 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
10908 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
10909 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
10910 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
10911 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
10912 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
10913 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
10914 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
10917 #define MIPS16_NUM_IMMED \
10918 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
10920 /* Handle a mips16 instruction with an immediate value. This or's the
10921 small immediate value into *INSN. It sets *USE_EXTEND to indicate
10922 whether an extended value is needed; if one is needed, it sets
10923 *EXTEND to the value. The argument type is TYPE. The value is VAL.
10924 If SMALL is true, an unextended opcode was explicitly requested.
10925 If EXT is true, an extended opcode was explicitly requested. If
10926 WARN is true, warn if EXT does not match reality. */
10929 mips16_immed (char *file, unsigned int line, int type, offsetT val,
10930 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
10931 unsigned long *insn, bfd_boolean *use_extend,
10932 unsigned short *extend)
10934 const struct mips16_immed_operand *op;
10935 int mintiny, maxtiny;
10936 bfd_boolean needext;
10938 op = mips16_immed_operands;
10939 while (op->type != type)
10942 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
10947 if (type == '<' || type == '>' || type == '[' || type == ']')
10950 maxtiny = 1 << op->nbits;
10955 maxtiny = (1 << op->nbits) - 1;
10960 mintiny = - (1 << (op->nbits - 1));
10961 maxtiny = (1 << (op->nbits - 1)) - 1;
10964 /* Branch offsets have an implicit 0 in the lowest bit. */
10965 if (type == 'p' || type == 'q')
10968 if ((val & ((1 << op->shift) - 1)) != 0
10969 || val < (mintiny << op->shift)
10970 || val > (maxtiny << op->shift))
10975 if (warn && ext && ! needext)
10976 as_warn_where (file, line,
10977 _("extended operand requested but not required"));
10978 if (small && needext)
10979 as_bad_where (file, line, _("invalid unextended operand value"));
10981 if (small || (! ext && ! needext))
10985 *use_extend = FALSE;
10986 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
10987 insnval <<= op->op_shift;
10992 long minext, maxext;
10998 maxext = (1 << op->extbits) - 1;
11002 minext = - (1 << (op->extbits - 1));
11003 maxext = (1 << (op->extbits - 1)) - 1;
11005 if (val < minext || val > maxext)
11006 as_bad_where (file, line,
11007 _("operand value out of range for instruction"));
11009 *use_extend = TRUE;
11010 if (op->extbits == 16)
11012 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
11015 else if (op->extbits == 15)
11017 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
11022 extval = ((val & 0x1f) << 6) | (val & 0x20);
11026 *extend = (unsigned short) extval;
11031 struct percent_op_match
11034 bfd_reloc_code_real_type reloc;
11037 static const struct percent_op_match mips_percent_op[] =
11039 {"%lo", BFD_RELOC_LO16},
11041 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
11042 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
11043 {"%call16", BFD_RELOC_MIPS_CALL16},
11044 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
11045 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
11046 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
11047 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
11048 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
11049 {"%got", BFD_RELOC_MIPS_GOT16},
11050 {"%gp_rel", BFD_RELOC_GPREL16},
11051 {"%half", BFD_RELOC_16},
11052 {"%highest", BFD_RELOC_MIPS_HIGHEST},
11053 {"%higher", BFD_RELOC_MIPS_HIGHER},
11054 {"%neg", BFD_RELOC_MIPS_SUB},
11055 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
11056 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
11057 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
11058 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
11059 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
11060 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
11061 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
11063 {"%hi", BFD_RELOC_HI16_S}
11066 static const struct percent_op_match mips16_percent_op[] =
11068 {"%lo", BFD_RELOC_MIPS16_LO16},
11069 {"%gprel", BFD_RELOC_MIPS16_GPREL},
11070 {"%got", BFD_RELOC_MIPS16_GOT16},
11071 {"%call16", BFD_RELOC_MIPS16_CALL16},
11072 {"%hi", BFD_RELOC_MIPS16_HI16_S}
11076 /* Return true if *STR points to a relocation operator. When returning true,
11077 move *STR over the operator and store its relocation code in *RELOC.
11078 Leave both *STR and *RELOC alone when returning false. */
11081 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
11083 const struct percent_op_match *percent_op;
11086 if (mips_opts.mips16)
11088 percent_op = mips16_percent_op;
11089 limit = ARRAY_SIZE (mips16_percent_op);
11093 percent_op = mips_percent_op;
11094 limit = ARRAY_SIZE (mips_percent_op);
11097 for (i = 0; i < limit; i++)
11098 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
11100 int len = strlen (percent_op[i].str);
11102 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
11105 *str += strlen (percent_op[i].str);
11106 *reloc = percent_op[i].reloc;
11108 /* Check whether the output BFD supports this relocation.
11109 If not, issue an error and fall back on something safe. */
11110 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
11112 as_bad ("relocation %s isn't supported by the current ABI",
11113 percent_op[i].str);
11114 *reloc = BFD_RELOC_UNUSED;
11122 /* Parse string STR as a 16-bit relocatable operand. Store the
11123 expression in *EP and the relocations in the array starting
11124 at RELOC. Return the number of relocation operators used.
11126 On exit, EXPR_END points to the first character after the expression. */
11129 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
11132 bfd_reloc_code_real_type reversed_reloc[3];
11133 size_t reloc_index, i;
11134 int crux_depth, str_depth;
11137 /* Search for the start of the main expression, recoding relocations
11138 in REVERSED_RELOC. End the loop with CRUX pointing to the start
11139 of the main expression and with CRUX_DEPTH containing the number
11140 of open brackets at that point. */
11147 crux_depth = str_depth;
11149 /* Skip over whitespace and brackets, keeping count of the number
11151 while (*str == ' ' || *str == '\t' || *str == '(')
11156 && reloc_index < (HAVE_NEWABI ? 3 : 1)
11157 && parse_relocation (&str, &reversed_reloc[reloc_index]));
11159 my_getExpression (ep, crux);
11162 /* Match every open bracket. */
11163 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
11167 if (crux_depth > 0)
11168 as_bad ("unclosed '('");
11172 if (reloc_index != 0)
11174 prev_reloc_op_frag = frag_now;
11175 for (i = 0; i < reloc_index; i++)
11176 reloc[i] = reversed_reloc[reloc_index - 1 - i];
11179 return reloc_index;
11183 my_getExpression (expressionS *ep, char *str)
11188 save_in = input_line_pointer;
11189 input_line_pointer = str;
11191 expr_end = input_line_pointer;
11192 input_line_pointer = save_in;
11194 /* If we are in mips16 mode, and this is an expression based on `.',
11195 then we bump the value of the symbol by 1 since that is how other
11196 text symbols are handled. We don't bother to handle complex
11197 expressions, just `.' plus or minus a constant. */
11198 if (mips_opts.mips16
11199 && ep->X_op == O_symbol
11200 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
11201 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg
11202 && symbol_get_frag (ep->X_add_symbol) == frag_now
11203 && symbol_constant_p (ep->X_add_symbol)
11204 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
11205 S_SET_VALUE (ep->X_add_symbol, val + 1);
11209 md_atof (int type, char *litP, int *sizeP)
11211 return ieee_md_atof (type, litP, sizeP, target_big_endian);
11215 md_number_to_chars (char *buf, valueT val, int n)
11217 if (target_big_endian)
11218 number_to_chars_bigendian (buf, val, n);
11220 number_to_chars_littleendian (buf, val, n);
11224 static int support_64bit_objects(void)
11226 const char **list, **l;
11229 list = bfd_target_list ();
11230 for (l = list; *l != NULL; l++)
11232 /* This is traditional mips */
11233 if (strcmp (*l, "elf64-tradbigmips") == 0
11234 || strcmp (*l, "elf64-tradlittlemips") == 0)
11236 if (strcmp (*l, "elf64-bigmips") == 0
11237 || strcmp (*l, "elf64-littlemips") == 0)
11240 yes = (*l != NULL);
11244 #endif /* OBJ_ELF */
11246 const char *md_shortopts = "O::g::G:";
11250 OPTION_MARCH = OPTION_MD_BASE,
11272 OPTION_NO_SMARTMIPS,
11275 OPTION_COMPAT_ARCH_BASE,
11284 OPTION_M7000_HILO_FIX,
11285 OPTION_MNO_7000_HILO_FIX,
11289 OPTION_NO_FIX_VR4120,
11291 OPTION_NO_FIX_VR4130,
11298 OPTION_CONSTRUCT_FLOATS,
11299 OPTION_NO_CONSTRUCT_FLOATS,
11302 OPTION_RELAX_BRANCH,
11303 OPTION_NO_RELAX_BRANCH,
11310 OPTION_SINGLE_FLOAT,
11311 OPTION_DOUBLE_FLOAT,
11314 OPTION_CALL_SHARED,
11315 OPTION_CALL_NONPIC,
11325 OPTION_MVXWORKS_PIC,
11326 #endif /* OBJ_ELF */
11330 struct option md_longopts[] =
11332 /* Options which specify architecture. */
11333 {"march", required_argument, NULL, OPTION_MARCH},
11334 {"mtune", required_argument, NULL, OPTION_MTUNE},
11335 {"mips0", no_argument, NULL, OPTION_MIPS1},
11336 {"mips1", no_argument, NULL, OPTION_MIPS1},
11337 {"mips2", no_argument, NULL, OPTION_MIPS2},
11338 {"mips3", no_argument, NULL, OPTION_MIPS3},
11339 {"mips4", no_argument, NULL, OPTION_MIPS4},
11340 {"mips5", no_argument, NULL, OPTION_MIPS5},
11341 {"mips32", no_argument, NULL, OPTION_MIPS32},
11342 {"mips64", no_argument, NULL, OPTION_MIPS64},
11343 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
11344 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
11346 /* Options which specify Application Specific Extensions (ASEs). */
11347 {"mips16", no_argument, NULL, OPTION_MIPS16},
11348 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
11349 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
11350 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
11351 {"mdmx", no_argument, NULL, OPTION_MDMX},
11352 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
11353 {"mdsp", no_argument, NULL, OPTION_DSP},
11354 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
11355 {"mmt", no_argument, NULL, OPTION_MT},
11356 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
11357 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
11358 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
11359 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
11360 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
11362 /* Old-style architecture options. Don't add more of these. */
11363 {"m4650", no_argument, NULL, OPTION_M4650},
11364 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
11365 {"m4010", no_argument, NULL, OPTION_M4010},
11366 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
11367 {"m4100", no_argument, NULL, OPTION_M4100},
11368 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
11369 {"m3900", no_argument, NULL, OPTION_M3900},
11370 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
11372 /* Options which enable bug fixes. */
11373 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
11374 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
11375 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
11376 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
11377 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
11378 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
11379 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
11380 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
11381 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
11383 /* Miscellaneous options. */
11384 {"trap", no_argument, NULL, OPTION_TRAP},
11385 {"no-break", no_argument, NULL, OPTION_TRAP},
11386 {"break", no_argument, NULL, OPTION_BREAK},
11387 {"no-trap", no_argument, NULL, OPTION_BREAK},
11388 {"EB", no_argument, NULL, OPTION_EB},
11389 {"EL", no_argument, NULL, OPTION_EL},
11390 {"mfp32", no_argument, NULL, OPTION_FP32},
11391 {"mgp32", no_argument, NULL, OPTION_GP32},
11392 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
11393 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
11394 {"mfp64", no_argument, NULL, OPTION_FP64},
11395 {"mgp64", no_argument, NULL, OPTION_GP64},
11396 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
11397 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
11398 {"mshared", no_argument, NULL, OPTION_MSHARED},
11399 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
11400 {"msym32", no_argument, NULL, OPTION_MSYM32},
11401 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
11402 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
11403 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
11404 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
11405 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
11407 /* Strictly speaking this next option is ELF specific,
11408 but we allow it for other ports as well in order to
11409 make testing easier. */
11410 {"32", no_argument, NULL, OPTION_32},
11412 /* ELF-specific options. */
11414 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
11415 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
11416 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
11417 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
11418 {"xgot", no_argument, NULL, OPTION_XGOT},
11419 {"mabi", required_argument, NULL, OPTION_MABI},
11420 {"n32", no_argument, NULL, OPTION_N32},
11421 {"64", no_argument, NULL, OPTION_64},
11422 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
11423 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
11424 {"mpdr", no_argument, NULL, OPTION_PDR},
11425 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
11426 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
11427 #endif /* OBJ_ELF */
11429 {NULL, no_argument, NULL, 0}
11431 size_t md_longopts_size = sizeof (md_longopts);
11433 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
11434 NEW_VALUE. Warn if another value was already specified. Note:
11435 we have to defer parsing the -march and -mtune arguments in order
11436 to handle 'from-abi' correctly, since the ABI might be specified
11437 in a later argument. */
11440 mips_set_option_string (const char **string_ptr, const char *new_value)
11442 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
11443 as_warn (_("A different %s was already specified, is now %s"),
11444 string_ptr == &mips_arch_string ? "-march" : "-mtune",
11447 *string_ptr = new_value;
11451 md_parse_option (int c, char *arg)
11455 case OPTION_CONSTRUCT_FLOATS:
11456 mips_disable_float_construction = 0;
11459 case OPTION_NO_CONSTRUCT_FLOATS:
11460 mips_disable_float_construction = 1;
11472 target_big_endian = 1;
11476 target_big_endian = 0;
11482 else if (arg[0] == '0')
11484 else if (arg[0] == '1')
11494 mips_debug = atoi (arg);
11498 file_mips_isa = ISA_MIPS1;
11502 file_mips_isa = ISA_MIPS2;
11506 file_mips_isa = ISA_MIPS3;
11510 file_mips_isa = ISA_MIPS4;
11514 file_mips_isa = ISA_MIPS5;
11517 case OPTION_MIPS32:
11518 file_mips_isa = ISA_MIPS32;
11521 case OPTION_MIPS32R2:
11522 file_mips_isa = ISA_MIPS32R2;
11525 case OPTION_MIPS64R2:
11526 file_mips_isa = ISA_MIPS64R2;
11529 case OPTION_MIPS64:
11530 file_mips_isa = ISA_MIPS64;
11534 mips_set_option_string (&mips_tune_string, arg);
11538 mips_set_option_string (&mips_arch_string, arg);
11542 mips_set_option_string (&mips_arch_string, "4650");
11543 mips_set_option_string (&mips_tune_string, "4650");
11546 case OPTION_NO_M4650:
11550 mips_set_option_string (&mips_arch_string, "4010");
11551 mips_set_option_string (&mips_tune_string, "4010");
11554 case OPTION_NO_M4010:
11558 mips_set_option_string (&mips_arch_string, "4100");
11559 mips_set_option_string (&mips_tune_string, "4100");
11562 case OPTION_NO_M4100:
11566 mips_set_option_string (&mips_arch_string, "3900");
11567 mips_set_option_string (&mips_tune_string, "3900");
11570 case OPTION_NO_M3900:
11574 mips_opts.ase_mdmx = 1;
11577 case OPTION_NO_MDMX:
11578 mips_opts.ase_mdmx = 0;
11582 mips_opts.ase_dsp = 1;
11583 mips_opts.ase_dspr2 = 0;
11586 case OPTION_NO_DSP:
11587 mips_opts.ase_dsp = 0;
11588 mips_opts.ase_dspr2 = 0;
11592 mips_opts.ase_dspr2 = 1;
11593 mips_opts.ase_dsp = 1;
11596 case OPTION_NO_DSPR2:
11597 mips_opts.ase_dspr2 = 0;
11598 mips_opts.ase_dsp = 0;
11602 mips_opts.ase_mt = 1;
11606 mips_opts.ase_mt = 0;
11609 case OPTION_MIPS16:
11610 mips_opts.mips16 = 1;
11611 mips_no_prev_insn ();
11614 case OPTION_NO_MIPS16:
11615 mips_opts.mips16 = 0;
11616 mips_no_prev_insn ();
11619 case OPTION_MIPS3D:
11620 mips_opts.ase_mips3d = 1;
11623 case OPTION_NO_MIPS3D:
11624 mips_opts.ase_mips3d = 0;
11627 case OPTION_SMARTMIPS:
11628 mips_opts.ase_smartmips = 1;
11631 case OPTION_NO_SMARTMIPS:
11632 mips_opts.ase_smartmips = 0;
11635 case OPTION_FIX_24K:
11639 case OPTION_NO_FIX_24K:
11643 case OPTION_FIX_VR4120:
11644 mips_fix_vr4120 = 1;
11647 case OPTION_NO_FIX_VR4120:
11648 mips_fix_vr4120 = 0;
11651 case OPTION_FIX_VR4130:
11652 mips_fix_vr4130 = 1;
11655 case OPTION_NO_FIX_VR4130:
11656 mips_fix_vr4130 = 0;
11659 case OPTION_RELAX_BRANCH:
11660 mips_relax_branch = 1;
11663 case OPTION_NO_RELAX_BRANCH:
11664 mips_relax_branch = 0;
11667 case OPTION_MSHARED:
11668 mips_in_shared = TRUE;
11671 case OPTION_MNO_SHARED:
11672 mips_in_shared = FALSE;
11675 case OPTION_MSYM32:
11676 mips_opts.sym32 = TRUE;
11679 case OPTION_MNO_SYM32:
11680 mips_opts.sym32 = FALSE;
11684 /* When generating ELF code, we permit -KPIC and -call_shared to
11685 select SVR4_PIC, and -non_shared to select no PIC. This is
11686 intended to be compatible with Irix 5. */
11687 case OPTION_CALL_SHARED:
11690 as_bad (_("-call_shared is supported only for ELF format"));
11693 mips_pic = SVR4_PIC;
11694 mips_abicalls = TRUE;
11697 case OPTION_CALL_NONPIC:
11700 as_bad (_("-call_nonpic is supported only for ELF format"));
11704 mips_abicalls = TRUE;
11707 case OPTION_NON_SHARED:
11710 as_bad (_("-non_shared is supported only for ELF format"));
11714 mips_abicalls = FALSE;
11717 /* The -xgot option tells the assembler to use 32 bit offsets
11718 when accessing the got in SVR4_PIC mode. It is for Irix
11723 #endif /* OBJ_ELF */
11726 g_switch_value = atoi (arg);
11730 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
11734 mips_abi = O32_ABI;
11735 /* We silently ignore -32 for non-ELF targets. This greatly
11736 simplifies the construction of the MIPS GAS test cases. */
11743 as_bad (_("-n32 is supported for ELF format only"));
11746 mips_abi = N32_ABI;
11752 as_bad (_("-64 is supported for ELF format only"));
11755 mips_abi = N64_ABI;
11756 if (!support_64bit_objects())
11757 as_fatal (_("No compiled in support for 64 bit object file format"));
11759 #endif /* OBJ_ELF */
11762 file_mips_gp32 = 1;
11766 file_mips_gp32 = 0;
11770 file_mips_fp32 = 1;
11774 file_mips_fp32 = 0;
11777 case OPTION_SINGLE_FLOAT:
11778 file_mips_single_float = 1;
11781 case OPTION_DOUBLE_FLOAT:
11782 file_mips_single_float = 0;
11785 case OPTION_SOFT_FLOAT:
11786 file_mips_soft_float = 1;
11789 case OPTION_HARD_FLOAT:
11790 file_mips_soft_float = 0;
11797 as_bad (_("-mabi is supported for ELF format only"));
11800 if (strcmp (arg, "32") == 0)
11801 mips_abi = O32_ABI;
11802 else if (strcmp (arg, "o64") == 0)
11803 mips_abi = O64_ABI;
11804 else if (strcmp (arg, "n32") == 0)
11805 mips_abi = N32_ABI;
11806 else if (strcmp (arg, "64") == 0)
11808 mips_abi = N64_ABI;
11809 if (! support_64bit_objects())
11810 as_fatal (_("No compiled in support for 64 bit object file "
11813 else if (strcmp (arg, "eabi") == 0)
11814 mips_abi = EABI_ABI;
11817 as_fatal (_("invalid abi -mabi=%s"), arg);
11821 #endif /* OBJ_ELF */
11823 case OPTION_M7000_HILO_FIX:
11824 mips_7000_hilo_fix = TRUE;
11827 case OPTION_MNO_7000_HILO_FIX:
11828 mips_7000_hilo_fix = FALSE;
11832 case OPTION_MDEBUG:
11833 mips_flag_mdebug = TRUE;
11836 case OPTION_NO_MDEBUG:
11837 mips_flag_mdebug = FALSE;
11841 mips_flag_pdr = TRUE;
11844 case OPTION_NO_PDR:
11845 mips_flag_pdr = FALSE;
11848 case OPTION_MVXWORKS_PIC:
11849 mips_pic = VXWORKS_PIC;
11851 #endif /* OBJ_ELF */
11860 /* Set up globals to generate code for the ISA or processor
11861 described by INFO. */
11864 mips_set_architecture (const struct mips_cpu_info *info)
11868 file_mips_arch = info->cpu;
11869 mips_opts.arch = info->cpu;
11870 mips_opts.isa = info->isa;
11875 /* Likewise for tuning. */
11878 mips_set_tune (const struct mips_cpu_info *info)
11881 mips_tune = info->cpu;
11886 mips_after_parse_args (void)
11888 const struct mips_cpu_info *arch_info = 0;
11889 const struct mips_cpu_info *tune_info = 0;
11891 /* GP relative stuff not working for PE */
11892 if (strncmp (TARGET_OS, "pe", 2) == 0)
11894 if (g_switch_seen && g_switch_value != 0)
11895 as_bad (_("-G not supported in this configuration."));
11896 g_switch_value = 0;
11899 if (mips_abi == NO_ABI)
11900 mips_abi = MIPS_DEFAULT_ABI;
11902 /* The following code determines the architecture and register size.
11903 Similar code was added to GCC 3.3 (see override_options() in
11904 config/mips/mips.c). The GAS and GCC code should be kept in sync
11905 as much as possible. */
11907 if (mips_arch_string != 0)
11908 arch_info = mips_parse_cpu ("-march", mips_arch_string);
11910 if (file_mips_isa != ISA_UNKNOWN)
11912 /* Handle -mipsN. At this point, file_mips_isa contains the
11913 ISA level specified by -mipsN, while arch_info->isa contains
11914 the -march selection (if any). */
11915 if (arch_info != 0)
11917 /* -march takes precedence over -mipsN, since it is more descriptive.
11918 There's no harm in specifying both as long as the ISA levels
11920 if (file_mips_isa != arch_info->isa)
11921 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
11922 mips_cpu_info_from_isa (file_mips_isa)->name,
11923 mips_cpu_info_from_isa (arch_info->isa)->name);
11926 arch_info = mips_cpu_info_from_isa (file_mips_isa);
11929 if (arch_info == 0)
11930 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
11932 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
11933 as_bad ("-march=%s is not compatible with the selected ABI",
11936 mips_set_architecture (arch_info);
11938 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
11939 if (mips_tune_string != 0)
11940 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
11942 if (tune_info == 0)
11943 mips_set_tune (arch_info);
11945 mips_set_tune (tune_info);
11947 if (file_mips_gp32 >= 0)
11949 /* The user specified the size of the integer registers. Make sure
11950 it agrees with the ABI and ISA. */
11951 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
11952 as_bad (_("-mgp64 used with a 32-bit processor"));
11953 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
11954 as_bad (_("-mgp32 used with a 64-bit ABI"));
11955 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
11956 as_bad (_("-mgp64 used with a 32-bit ABI"));
11960 /* Infer the integer register size from the ABI and processor.
11961 Restrict ourselves to 32-bit registers if that's all the
11962 processor has, or if the ABI cannot handle 64-bit registers. */
11963 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
11964 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
11967 switch (file_mips_fp32)
11971 /* No user specified float register size.
11972 ??? GAS treats single-float processors as though they had 64-bit
11973 float registers (although it complains when double-precision
11974 instructions are used). As things stand, saying they have 32-bit
11975 registers would lead to spurious "register must be even" messages.
11976 So here we assume float registers are never smaller than the
11978 if (file_mips_gp32 == 0)
11979 /* 64-bit integer registers implies 64-bit float registers. */
11980 file_mips_fp32 = 0;
11981 else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
11982 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
11983 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
11984 file_mips_fp32 = 0;
11986 /* 32-bit float registers. */
11987 file_mips_fp32 = 1;
11990 /* The user specified the size of the float registers. Check if it
11991 agrees with the ABI and ISA. */
11993 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
11994 as_bad (_("-mfp64 used with a 32-bit fpu"));
11995 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
11996 && !ISA_HAS_MXHC1 (mips_opts.isa))
11997 as_warn (_("-mfp64 used with a 32-bit ABI"));
12000 if (ABI_NEEDS_64BIT_REGS (mips_abi))
12001 as_warn (_("-mfp32 used with a 64-bit ABI"));
12005 /* End of GCC-shared inference code. */
12007 /* This flag is set when we have a 64-bit capable CPU but use only
12008 32-bit wide registers. Note that EABI does not use it. */
12009 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
12010 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
12011 || mips_abi == O32_ABI))
12012 mips_32bitmode = 1;
12014 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
12015 as_bad (_("trap exception not supported at ISA 1"));
12017 /* If the selected architecture includes support for ASEs, enable
12018 generation of code for them. */
12019 if (mips_opts.mips16 == -1)
12020 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
12021 if (mips_opts.ase_mips3d == -1)
12022 mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
12023 && file_mips_fp32 == 0) ? 1 : 0;
12024 if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
12025 as_bad (_("-mfp32 used with -mips3d"));
12027 if (mips_opts.ase_mdmx == -1)
12028 mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
12029 && file_mips_fp32 == 0) ? 1 : 0;
12030 if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
12031 as_bad (_("-mfp32 used with -mdmx"));
12033 if (mips_opts.ase_smartmips == -1)
12034 mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
12035 if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
12036 as_warn ("%s ISA does not support SmartMIPS",
12037 mips_cpu_info_from_isa (mips_opts.isa)->name);
12039 if (mips_opts.ase_dsp == -1)
12040 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
12041 if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
12042 as_warn ("%s ISA does not support DSP ASE",
12043 mips_cpu_info_from_isa (mips_opts.isa)->name);
12045 if (mips_opts.ase_dspr2 == -1)
12047 mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
12048 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
12050 if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
12051 as_warn ("%s ISA does not support DSP R2 ASE",
12052 mips_cpu_info_from_isa (mips_opts.isa)->name);
12054 if (mips_opts.ase_mt == -1)
12055 mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
12056 if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
12057 as_warn ("%s ISA does not support MT ASE",
12058 mips_cpu_info_from_isa (mips_opts.isa)->name);
12060 file_mips_isa = mips_opts.isa;
12061 file_ase_mips16 = mips_opts.mips16;
12062 file_ase_mips3d = mips_opts.ase_mips3d;
12063 file_ase_mdmx = mips_opts.ase_mdmx;
12064 file_ase_smartmips = mips_opts.ase_smartmips;
12065 file_ase_dsp = mips_opts.ase_dsp;
12066 file_ase_dspr2 = mips_opts.ase_dspr2;
12067 file_ase_mt = mips_opts.ase_mt;
12068 mips_opts.gp32 = file_mips_gp32;
12069 mips_opts.fp32 = file_mips_fp32;
12070 mips_opts.soft_float = file_mips_soft_float;
12071 mips_opts.single_float = file_mips_single_float;
12073 if (mips_flag_mdebug < 0)
12075 #ifdef OBJ_MAYBE_ECOFF
12076 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
12077 mips_flag_mdebug = 1;
12079 #endif /* OBJ_MAYBE_ECOFF */
12080 mips_flag_mdebug = 0;
12085 mips_init_after_args (void)
12087 /* initialize opcodes */
12088 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
12089 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
12093 md_pcrel_from (fixS *fixP)
12095 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
12096 switch (fixP->fx_r_type)
12098 case BFD_RELOC_16_PCREL_S2:
12099 case BFD_RELOC_MIPS_JMP:
12100 /* Return the address of the delay slot. */
12103 /* We have no relocation type for PC relative MIPS16 instructions. */
12104 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
12105 as_bad_where (fixP->fx_file, fixP->fx_line,
12106 _("PC relative MIPS16 instruction references a different section"));
12111 /* This is called before the symbol table is processed. In order to
12112 work with gcc when using mips-tfile, we must keep all local labels.
12113 However, in other cases, we want to discard them. If we were
12114 called with -g, but we didn't see any debugging information, it may
12115 mean that gcc is smuggling debugging information through to
12116 mips-tfile, in which case we must generate all local labels. */
12119 mips_frob_file_before_adjust (void)
12121 #ifndef NO_ECOFF_DEBUGGING
12122 if (ECOFF_DEBUGGING
12124 && ! ecoff_debugging_seen)
12125 flag_keep_locals = 1;
12129 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
12130 the corresponding LO16 reloc. This is called before md_apply_fix and
12131 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
12132 relocation operators.
12134 For our purposes, a %lo() expression matches a %got() or %hi()
12137 (a) it refers to the same symbol; and
12138 (b) the offset applied in the %lo() expression is no lower than
12139 the offset applied in the %got() or %hi().
12141 (b) allows us to cope with code like:
12144 lh $4,%lo(foo+2)($4)
12146 ...which is legal on RELA targets, and has a well-defined behaviour
12147 if the user knows that adding 2 to "foo" will not induce a carry to
12150 When several %lo()s match a particular %got() or %hi(), we use the
12151 following rules to distinguish them:
12153 (1) %lo()s with smaller offsets are a better match than %lo()s with
12156 (2) %lo()s with no matching %got() or %hi() are better than those
12157 that already have a matching %got() or %hi().
12159 (3) later %lo()s are better than earlier %lo()s.
12161 These rules are applied in order.
12163 (1) means, among other things, that %lo()s with identical offsets are
12164 chosen if they exist.
12166 (2) means that we won't associate several high-part relocations with
12167 the same low-part relocation unless there's no alternative. Having
12168 several high parts for the same low part is a GNU extension; this rule
12169 allows careful users to avoid it.
12171 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
12172 with the last high-part relocation being at the front of the list.
12173 It therefore makes sense to choose the last matching low-part
12174 relocation, all other things being equal. It's also easier
12175 to code that way. */
12178 mips_frob_file (void)
12180 struct mips_hi_fixup *l;
12181 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
12183 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
12185 segment_info_type *seginfo;
12186 bfd_boolean matched_lo_p;
12187 fixS **hi_pos, **lo_pos, **pos;
12189 assert (reloc_needs_lo_p (l->fixp->fx_r_type));
12191 /* If a GOT16 relocation turns out to be against a global symbol,
12192 there isn't supposed to be a matching LO. */
12193 if (got16_reloc_p (l->fixp->fx_r_type)
12194 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
12197 /* Check quickly whether the next fixup happens to be a matching %lo. */
12198 if (fixup_has_matching_lo_p (l->fixp))
12201 seginfo = seg_info (l->seg);
12203 /* Set HI_POS to the position of this relocation in the chain.
12204 Set LO_POS to the position of the chosen low-part relocation.
12205 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
12206 relocation that matches an immediately-preceding high-part
12210 matched_lo_p = FALSE;
12211 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
12213 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
12215 if (*pos == l->fixp)
12218 if ((*pos)->fx_r_type == looking_for_rtype
12219 && (*pos)->fx_addsy == l->fixp->fx_addsy
12220 && (*pos)->fx_offset >= l->fixp->fx_offset
12222 || (*pos)->fx_offset < (*lo_pos)->fx_offset
12224 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
12227 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
12228 && fixup_has_matching_lo_p (*pos));
12231 /* If we found a match, remove the high-part relocation from its
12232 current position and insert it before the low-part relocation.
12233 Make the offsets match so that fixup_has_matching_lo_p()
12236 We don't warn about unmatched high-part relocations since some
12237 versions of gcc have been known to emit dead "lui ...%hi(...)"
12239 if (lo_pos != NULL)
12241 l->fixp->fx_offset = (*lo_pos)->fx_offset;
12242 if (l->fixp->fx_next != *lo_pos)
12244 *hi_pos = l->fixp->fx_next;
12245 l->fixp->fx_next = *lo_pos;
12252 /* We may have combined relocations without symbols in the N32/N64 ABI.
12253 We have to prevent gas from dropping them. */
12256 mips_force_relocation (fixS *fixp)
12258 if (generic_force_reloc (fixp))
12262 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
12263 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
12264 || hi16_reloc_p (fixp->fx_r_type)
12265 || lo16_reloc_p (fixp->fx_r_type)))
12271 /* Apply a fixup to the object file. */
12274 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
12278 reloc_howto_type *howto;
12280 /* We ignore generic BFD relocations we don't know about. */
12281 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
12285 assert (fixP->fx_size == 4
12286 || fixP->fx_r_type == BFD_RELOC_16
12287 || fixP->fx_r_type == BFD_RELOC_64
12288 || fixP->fx_r_type == BFD_RELOC_CTOR
12289 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
12290 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12291 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
12292 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
12294 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
12296 assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2);
12298 /* Don't treat parts of a composite relocation as done. There are two
12301 (1) The second and third parts will be against 0 (RSS_UNDEF) but
12302 should nevertheless be emitted if the first part is.
12304 (2) In normal usage, composite relocations are never assembly-time
12305 constants. The easiest way of dealing with the pathological
12306 exceptions is to generate a relocation against STN_UNDEF and
12307 leave everything up to the linker. */
12308 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
12311 switch (fixP->fx_r_type)
12313 case BFD_RELOC_MIPS_TLS_GD:
12314 case BFD_RELOC_MIPS_TLS_LDM:
12315 case BFD_RELOC_MIPS_TLS_DTPREL32:
12316 case BFD_RELOC_MIPS_TLS_DTPREL64:
12317 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
12318 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
12319 case BFD_RELOC_MIPS_TLS_GOTTPREL:
12320 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
12321 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
12322 S_SET_THREAD_LOCAL (fixP->fx_addsy);
12325 case BFD_RELOC_MIPS_JMP:
12326 case BFD_RELOC_MIPS_SHIFT5:
12327 case BFD_RELOC_MIPS_SHIFT6:
12328 case BFD_RELOC_MIPS_GOT_DISP:
12329 case BFD_RELOC_MIPS_GOT_PAGE:
12330 case BFD_RELOC_MIPS_GOT_OFST:
12331 case BFD_RELOC_MIPS_SUB:
12332 case BFD_RELOC_MIPS_INSERT_A:
12333 case BFD_RELOC_MIPS_INSERT_B:
12334 case BFD_RELOC_MIPS_DELETE:
12335 case BFD_RELOC_MIPS_HIGHEST:
12336 case BFD_RELOC_MIPS_HIGHER:
12337 case BFD_RELOC_MIPS_SCN_DISP:
12338 case BFD_RELOC_MIPS_REL16:
12339 case BFD_RELOC_MIPS_RELGOT:
12340 case BFD_RELOC_MIPS_JALR:
12341 case BFD_RELOC_HI16:
12342 case BFD_RELOC_HI16_S:
12343 case BFD_RELOC_GPREL16:
12344 case BFD_RELOC_MIPS_LITERAL:
12345 case BFD_RELOC_MIPS_CALL16:
12346 case BFD_RELOC_MIPS_GOT16:
12347 case BFD_RELOC_GPREL32:
12348 case BFD_RELOC_MIPS_GOT_HI16:
12349 case BFD_RELOC_MIPS_GOT_LO16:
12350 case BFD_RELOC_MIPS_CALL_HI16:
12351 case BFD_RELOC_MIPS_CALL_LO16:
12352 case BFD_RELOC_MIPS16_GPREL:
12353 case BFD_RELOC_MIPS16_GOT16:
12354 case BFD_RELOC_MIPS16_CALL16:
12355 case BFD_RELOC_MIPS16_HI16:
12356 case BFD_RELOC_MIPS16_HI16_S:
12357 case BFD_RELOC_MIPS16_JMP:
12358 /* Nothing needed to do. The value comes from the reloc entry. */
12362 /* This is handled like BFD_RELOC_32, but we output a sign
12363 extended value if we are only 32 bits. */
12366 if (8 <= sizeof (valueT))
12367 md_number_to_chars ((char *) buf, *valP, 8);
12372 if ((*valP & 0x80000000) != 0)
12376 md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)),
12378 md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)),
12384 case BFD_RELOC_RVA:
12387 /* If we are deleting this reloc entry, we must fill in the
12388 value now. This can happen if we have a .word which is not
12389 resolved when it appears but is later defined. */
12391 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
12394 case BFD_RELOC_LO16:
12395 case BFD_RELOC_MIPS16_LO16:
12396 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
12397 may be safe to remove, but if so it's not obvious. */
12398 /* When handling an embedded PIC switch statement, we can wind
12399 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
12402 if (*valP + 0x8000 > 0xffff)
12403 as_bad_where (fixP->fx_file, fixP->fx_line,
12404 _("relocation overflow"));
12405 if (target_big_endian)
12407 md_number_to_chars ((char *) buf, *valP, 2);
12411 case BFD_RELOC_16_PCREL_S2:
12412 if ((*valP & 0x3) != 0)
12413 as_bad_where (fixP->fx_file, fixP->fx_line,
12414 _("Branch to misaligned address (%lx)"), (long) *valP);
12416 /* We need to save the bits in the instruction since fixup_segment()
12417 might be deleting the relocation entry (i.e., a branch within
12418 the current segment). */
12419 if (! fixP->fx_done)
12422 /* Update old instruction data. */
12423 if (target_big_endian)
12424 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
12426 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
12428 if (*valP + 0x20000 <= 0x3ffff)
12430 insn |= (*valP >> 2) & 0xffff;
12431 md_number_to_chars ((char *) buf, insn, 4);
12433 else if (mips_pic == NO_PIC
12435 && fixP->fx_frag->fr_address >= text_section->vma
12436 && (fixP->fx_frag->fr_address
12437 < text_section->vma + bfd_get_section_size (text_section))
12438 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
12439 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
12440 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
12442 /* The branch offset is too large. If this is an
12443 unconditional branch, and we are not generating PIC code,
12444 we can convert it to an absolute jump instruction. */
12445 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
12446 insn = 0x0c000000; /* jal */
12448 insn = 0x08000000; /* j */
12449 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
12451 fixP->fx_addsy = section_symbol (text_section);
12452 *valP += md_pcrel_from (fixP);
12453 md_number_to_chars ((char *) buf, insn, 4);
12457 /* If we got here, we have branch-relaxation disabled,
12458 and there's nothing we can do to fix this instruction
12459 without turning it into a longer sequence. */
12460 as_bad_where (fixP->fx_file, fixP->fx_line,
12461 _("Branch out of range"));
12465 case BFD_RELOC_VTABLE_INHERIT:
12468 && !S_IS_DEFINED (fixP->fx_addsy)
12469 && !S_IS_WEAK (fixP->fx_addsy))
12470 S_SET_WEAK (fixP->fx_addsy);
12473 case BFD_RELOC_VTABLE_ENTRY:
12481 /* Remember value for tc_gen_reloc. */
12482 fixP->fx_addnumber = *valP;
12492 name = input_line_pointer;
12493 c = get_symbol_end ();
12494 p = (symbolS *) symbol_find_or_make (name);
12495 *input_line_pointer = c;
12499 /* Align the current frag to a given power of two. If a particular
12500 fill byte should be used, FILL points to an integer that contains
12501 that byte, otherwise FILL is null.
12503 The MIPS assembler also automatically adjusts any preceding
12507 mips_align (int to, int *fill, symbolS *label)
12509 mips_emit_delays ();
12510 mips_record_mips16_mode ();
12511 if (fill == NULL && subseg_text_p (now_seg))
12512 frag_align_code (to, 0);
12514 frag_align (to, fill ? *fill : 0, 0);
12515 record_alignment (now_seg, to);
12518 assert (S_GET_SEGMENT (label) == now_seg);
12519 symbol_set_frag (label, frag_now);
12520 S_SET_VALUE (label, (valueT) frag_now_fix ());
12524 /* Align to a given power of two. .align 0 turns off the automatic
12525 alignment used by the data creating pseudo-ops. */
12528 s_align (int x ATTRIBUTE_UNUSED)
12530 int temp, fill_value, *fill_ptr;
12531 long max_alignment = 28;
12533 /* o Note that the assembler pulls down any immediately preceding label
12534 to the aligned address.
12535 o It's not documented but auto alignment is reinstated by
12536 a .align pseudo instruction.
12537 o Note also that after auto alignment is turned off the mips assembler
12538 issues an error on attempt to assemble an improperly aligned data item.
12541 temp = get_absolute_expression ();
12542 if (temp > max_alignment)
12543 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
12546 as_warn (_("Alignment negative: 0 assumed."));
12549 if (*input_line_pointer == ',')
12551 ++input_line_pointer;
12552 fill_value = get_absolute_expression ();
12553 fill_ptr = &fill_value;
12559 segment_info_type *si = seg_info (now_seg);
12560 struct insn_label_list *l = si->label_list;
12561 /* Auto alignment should be switched on by next section change. */
12563 mips_align (temp, fill_ptr, l != NULL ? l->label : NULL);
12570 demand_empty_rest_of_line ();
12574 s_change_sec (int sec)
12579 /* The ELF backend needs to know that we are changing sections, so
12580 that .previous works correctly. We could do something like check
12581 for an obj_section_change_hook macro, but that might be confusing
12582 as it would not be appropriate to use it in the section changing
12583 functions in read.c, since obj-elf.c intercepts those. FIXME:
12584 This should be cleaner, somehow. */
12586 obj_elf_section_change_hook ();
12589 mips_emit_delays ();
12592 check_for_24k_errata ((struct mips_cl_insn *) &history[0], -1);
12603 subseg_set (bss_section, (subsegT) get_absolute_expression ());
12604 demand_empty_rest_of_line ();
12608 seg = subseg_new (RDATA_SECTION_NAME,
12609 (subsegT) get_absolute_expression ());
12612 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
12613 | SEC_READONLY | SEC_RELOC
12615 if (strncmp (TARGET_OS, "elf", 3) != 0)
12616 record_alignment (seg, 4);
12618 demand_empty_rest_of_line ();
12622 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
12625 bfd_set_section_flags (stdoutput, seg,
12626 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
12627 if (strncmp (TARGET_OS, "elf", 3) != 0)
12628 record_alignment (seg, 4);
12630 demand_empty_rest_of_line ();
12638 s_change_section (int ignore ATTRIBUTE_UNUSED)
12641 char *section_name;
12646 int section_entry_size;
12647 int section_alignment;
12653 check_for_24k_errata ((struct mips_cl_insn *) &history[0], -1);
12655 section_name = input_line_pointer;
12656 c = get_symbol_end ();
12658 next_c = *(input_line_pointer + 1);
12660 /* Do we have .section Name<,"flags">? */
12661 if (c != ',' || (c == ',' && next_c == '"'))
12663 /* just after name is now '\0'. */
12664 *input_line_pointer = c;
12665 input_line_pointer = section_name;
12666 obj_elf_section (ignore);
12669 input_line_pointer++;
12671 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
12673 section_type = get_absolute_expression ();
12676 if (*input_line_pointer++ == ',')
12677 section_flag = get_absolute_expression ();
12680 if (*input_line_pointer++ == ',')
12681 section_entry_size = get_absolute_expression ();
12683 section_entry_size = 0;
12684 if (*input_line_pointer++ == ',')
12685 section_alignment = get_absolute_expression ();
12687 section_alignment = 0;
12689 section_name = xstrdup (section_name);
12691 /* When using the generic form of .section (as implemented by obj-elf.c),
12692 there's no way to set the section type to SHT_MIPS_DWARF. Users have
12693 traditionally had to fall back on the more common @progbits instead.
12695 There's nothing really harmful in this, since bfd will correct
12696 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
12697 means that, for backwards compatibility, the special_section entries
12698 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
12700 Even so, we shouldn't force users of the MIPS .section syntax to
12701 incorrectly label the sections as SHT_PROGBITS. The best compromise
12702 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
12703 generic type-checking code. */
12704 if (section_type == SHT_MIPS_DWARF)
12705 section_type = SHT_PROGBITS;
12707 obj_elf_change_section (section_name, section_type, section_flag,
12708 section_entry_size, 0, 0, 0);
12710 if (now_seg->name != section_name)
12711 free (section_name);
12712 #endif /* OBJ_ELF */
12716 mips_enable_auto_align (void)
12722 s_cons (int log_size)
12724 segment_info_type *si = seg_info (now_seg);
12725 struct insn_label_list *l = si->label_list;
12728 label = l != NULL ? l->label : NULL;
12729 mips_emit_delays ();
12730 if (log_size > 0 && auto_align)
12731 mips_align (log_size, 0, label);
12732 mips_clear_insn_labels ();
12733 cons (1 << log_size);
12737 s_float_cons (int type)
12739 segment_info_type *si = seg_info (now_seg);
12740 struct insn_label_list *l = si->label_list;
12743 label = l != NULL ? l->label : NULL;
12745 mips_emit_delays ();
12750 mips_align (3, 0, label);
12752 mips_align (2, 0, label);
12755 mips_clear_insn_labels ();
12760 /* Handle .globl. We need to override it because on Irix 5 you are
12763 where foo is an undefined symbol, to mean that foo should be
12764 considered to be the address of a function. */
12767 s_mips_globl (int x ATTRIBUTE_UNUSED)
12776 name = input_line_pointer;
12777 c = get_symbol_end ();
12778 symbolP = symbol_find_or_make (name);
12779 S_SET_EXTERNAL (symbolP);
12781 *input_line_pointer = c;
12782 SKIP_WHITESPACE ();
12784 /* On Irix 5, every global symbol that is not explicitly labelled as
12785 being a function is apparently labelled as being an object. */
12788 if (!is_end_of_line[(unsigned char) *input_line_pointer]
12789 && (*input_line_pointer != ','))
12794 secname = input_line_pointer;
12795 c = get_symbol_end ();
12796 sec = bfd_get_section_by_name (stdoutput, secname);
12798 as_bad (_("%s: no such section"), secname);
12799 *input_line_pointer = c;
12801 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
12802 flag = BSF_FUNCTION;
12805 symbol_get_bfdsym (symbolP)->flags |= flag;
12807 c = *input_line_pointer;
12810 input_line_pointer++;
12811 SKIP_WHITESPACE ();
12812 if (is_end_of_line[(unsigned char) *input_line_pointer])
12818 demand_empty_rest_of_line ();
12822 s_option (int x ATTRIBUTE_UNUSED)
12827 opt = input_line_pointer;
12828 c = get_symbol_end ();
12832 /* FIXME: What does this mean? */
12834 else if (strncmp (opt, "pic", 3) == 0)
12838 i = atoi (opt + 3);
12843 mips_pic = SVR4_PIC;
12844 mips_abicalls = TRUE;
12847 as_bad (_(".option pic%d not supported"), i);
12849 if (mips_pic == SVR4_PIC)
12851 if (g_switch_seen && g_switch_value != 0)
12852 as_warn (_("-G may not be used with SVR4 PIC code"));
12853 g_switch_value = 0;
12854 bfd_set_gp_size (stdoutput, 0);
12858 as_warn (_("Unrecognized option \"%s\""), opt);
12860 *input_line_pointer = c;
12861 demand_empty_rest_of_line ();
12864 /* This structure is used to hold a stack of .set values. */
12866 struct mips_option_stack
12868 struct mips_option_stack *next;
12869 struct mips_set_options options;
12872 static struct mips_option_stack *mips_opts_stack;
12874 /* Handle the .set pseudo-op. */
12877 s_mipsset (int x ATTRIBUTE_UNUSED)
12879 char *name = input_line_pointer, ch;
12881 while (!is_end_of_line[(unsigned char) *input_line_pointer])
12882 ++input_line_pointer;
12883 ch = *input_line_pointer;
12884 *input_line_pointer = '\0';
12886 if (strcmp (name, "reorder") == 0)
12888 if (mips_opts.noreorder)
12891 else if (strcmp (name, "noreorder") == 0)
12893 if (!mips_opts.noreorder)
12894 start_noreorder ();
12896 else if (strncmp (name, "at=", 3) == 0)
12898 char *s = name + 3;
12900 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
12901 as_bad (_("Unrecognized register name `%s'"), s);
12903 else if (strcmp (name, "at") == 0)
12905 mips_opts.at = ATREG;
12907 else if (strcmp (name, "noat") == 0)
12909 mips_opts.at = ZERO;
12911 else if (strcmp (name, "macro") == 0)
12913 mips_opts.warn_about_macros = 0;
12915 else if (strcmp (name, "nomacro") == 0)
12917 if (mips_opts.noreorder == 0)
12918 as_bad (_("`noreorder' must be set before `nomacro'"));
12919 mips_opts.warn_about_macros = 1;
12921 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
12923 mips_opts.nomove = 0;
12925 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
12927 mips_opts.nomove = 1;
12929 else if (strcmp (name, "bopt") == 0)
12931 mips_opts.nobopt = 0;
12933 else if (strcmp (name, "nobopt") == 0)
12935 mips_opts.nobopt = 1;
12937 else if (strcmp (name, "gp=default") == 0)
12938 mips_opts.gp32 = file_mips_gp32;
12939 else if (strcmp (name, "gp=32") == 0)
12940 mips_opts.gp32 = 1;
12941 else if (strcmp (name, "gp=64") == 0)
12943 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
12944 as_warn ("%s isa does not support 64-bit registers",
12945 mips_cpu_info_from_isa (mips_opts.isa)->name);
12946 mips_opts.gp32 = 0;
12948 else if (strcmp (name, "fp=default") == 0)
12949 mips_opts.fp32 = file_mips_fp32;
12950 else if (strcmp (name, "fp=32") == 0)
12951 mips_opts.fp32 = 1;
12952 else if (strcmp (name, "fp=64") == 0)
12954 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
12955 as_warn ("%s isa does not support 64-bit floating point registers",
12956 mips_cpu_info_from_isa (mips_opts.isa)->name);
12957 mips_opts.fp32 = 0;
12959 else if (strcmp (name, "softfloat") == 0)
12960 mips_opts.soft_float = 1;
12961 else if (strcmp (name, "hardfloat") == 0)
12962 mips_opts.soft_float = 0;
12963 else if (strcmp (name, "singlefloat") == 0)
12964 mips_opts.single_float = 1;
12965 else if (strcmp (name, "doublefloat") == 0)
12966 mips_opts.single_float = 0;
12967 else if (strcmp (name, "mips16") == 0
12968 || strcmp (name, "MIPS-16") == 0)
12969 mips_opts.mips16 = 1;
12970 else if (strcmp (name, "nomips16") == 0
12971 || strcmp (name, "noMIPS-16") == 0)
12972 mips_opts.mips16 = 0;
12973 else if (strcmp (name, "smartmips") == 0)
12975 if (!ISA_SUPPORTS_SMARTMIPS)
12976 as_warn ("%s ISA does not support SmartMIPS ASE",
12977 mips_cpu_info_from_isa (mips_opts.isa)->name);
12978 mips_opts.ase_smartmips = 1;
12980 else if (strcmp (name, "nosmartmips") == 0)
12981 mips_opts.ase_smartmips = 0;
12982 else if (strcmp (name, "mips3d") == 0)
12983 mips_opts.ase_mips3d = 1;
12984 else if (strcmp (name, "nomips3d") == 0)
12985 mips_opts.ase_mips3d = 0;
12986 else if (strcmp (name, "mdmx") == 0)
12987 mips_opts.ase_mdmx = 1;
12988 else if (strcmp (name, "nomdmx") == 0)
12989 mips_opts.ase_mdmx = 0;
12990 else if (strcmp (name, "dsp") == 0)
12992 if (!ISA_SUPPORTS_DSP_ASE)
12993 as_warn ("%s ISA does not support DSP ASE",
12994 mips_cpu_info_from_isa (mips_opts.isa)->name);
12995 mips_opts.ase_dsp = 1;
12996 mips_opts.ase_dspr2 = 0;
12998 else if (strcmp (name, "nodsp") == 0)
13000 mips_opts.ase_dsp = 0;
13001 mips_opts.ase_dspr2 = 0;
13003 else if (strcmp (name, "dspr2") == 0)
13005 if (!ISA_SUPPORTS_DSPR2_ASE)
13006 as_warn ("%s ISA does not support DSP R2 ASE",
13007 mips_cpu_info_from_isa (mips_opts.isa)->name);
13008 mips_opts.ase_dspr2 = 1;
13009 mips_opts.ase_dsp = 1;
13011 else if (strcmp (name, "nodspr2") == 0)
13013 mips_opts.ase_dspr2 = 0;
13014 mips_opts.ase_dsp = 0;
13016 else if (strcmp (name, "mt") == 0)
13018 if (!ISA_SUPPORTS_MT_ASE)
13019 as_warn ("%s ISA does not support MT ASE",
13020 mips_cpu_info_from_isa (mips_opts.isa)->name);
13021 mips_opts.ase_mt = 1;
13023 else if (strcmp (name, "nomt") == 0)
13024 mips_opts.ase_mt = 0;
13025 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
13029 /* Permit the user to change the ISA and architecture on the fly.
13030 Needless to say, misuse can cause serious problems. */
13031 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
13034 mips_opts.isa = file_mips_isa;
13035 mips_opts.arch = file_mips_arch;
13037 else if (strncmp (name, "arch=", 5) == 0)
13039 const struct mips_cpu_info *p;
13041 p = mips_parse_cpu("internal use", name + 5);
13043 as_bad (_("unknown architecture %s"), name + 5);
13046 mips_opts.arch = p->cpu;
13047 mips_opts.isa = p->isa;
13050 else if (strncmp (name, "mips", 4) == 0)
13052 const struct mips_cpu_info *p;
13054 p = mips_parse_cpu("internal use", name);
13056 as_bad (_("unknown ISA level %s"), name + 4);
13059 mips_opts.arch = p->cpu;
13060 mips_opts.isa = p->isa;
13064 as_bad (_("unknown ISA or architecture %s"), name);
13066 switch (mips_opts.isa)
13074 mips_opts.gp32 = 1;
13075 mips_opts.fp32 = 1;
13082 mips_opts.gp32 = 0;
13083 mips_opts.fp32 = 0;
13086 as_bad (_("unknown ISA level %s"), name + 4);
13091 mips_opts.gp32 = file_mips_gp32;
13092 mips_opts.fp32 = file_mips_fp32;
13095 else if (strcmp (name, "autoextend") == 0)
13096 mips_opts.noautoextend = 0;
13097 else if (strcmp (name, "noautoextend") == 0)
13098 mips_opts.noautoextend = 1;
13099 else if (strcmp (name, "push") == 0)
13101 struct mips_option_stack *s;
13103 s = (struct mips_option_stack *) xmalloc (sizeof *s);
13104 s->next = mips_opts_stack;
13105 s->options = mips_opts;
13106 mips_opts_stack = s;
13108 else if (strcmp (name, "pop") == 0)
13110 struct mips_option_stack *s;
13112 s = mips_opts_stack;
13114 as_bad (_(".set pop with no .set push"));
13117 /* If we're changing the reorder mode we need to handle
13118 delay slots correctly. */
13119 if (s->options.noreorder && ! mips_opts.noreorder)
13120 start_noreorder ();
13121 else if (! s->options.noreorder && mips_opts.noreorder)
13124 mips_opts = s->options;
13125 mips_opts_stack = s->next;
13129 else if (strcmp (name, "sym32") == 0)
13130 mips_opts.sym32 = TRUE;
13131 else if (strcmp (name, "nosym32") == 0)
13132 mips_opts.sym32 = FALSE;
13133 else if (strchr (name, ','))
13135 /* Generic ".set" directive; use the generic handler. */
13136 *input_line_pointer = ch;
13137 input_line_pointer = name;
13143 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
13145 *input_line_pointer = ch;
13146 demand_empty_rest_of_line ();
13149 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
13150 .option pic2. It means to generate SVR4 PIC calls. */
13153 s_abicalls (int ignore ATTRIBUTE_UNUSED)
13155 mips_pic = SVR4_PIC;
13156 mips_abicalls = TRUE;
13158 if (g_switch_seen && g_switch_value != 0)
13159 as_warn (_("-G may not be used with SVR4 PIC code"));
13160 g_switch_value = 0;
13162 bfd_set_gp_size (stdoutput, 0);
13163 demand_empty_rest_of_line ();
13166 /* Handle the .cpload pseudo-op. This is used when generating SVR4
13167 PIC code. It sets the $gp register for the function based on the
13168 function address, which is in the register named in the argument.
13169 This uses a relocation against _gp_disp, which is handled specially
13170 by the linker. The result is:
13171 lui $gp,%hi(_gp_disp)
13172 addiu $gp,$gp,%lo(_gp_disp)
13173 addu $gp,$gp,.cpload argument
13174 The .cpload argument is normally $25 == $t9.
13176 The -mno-shared option changes this to:
13177 lui $gp,%hi(__gnu_local_gp)
13178 addiu $gp,$gp,%lo(__gnu_local_gp)
13179 and the argument is ignored. This saves an instruction, but the
13180 resulting code is not position independent; it uses an absolute
13181 address for __gnu_local_gp. Thus code assembled with -mno-shared
13182 can go into an ordinary executable, but not into a shared library. */
13185 s_cpload (int ignore ATTRIBUTE_UNUSED)
13191 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13192 .cpload is ignored. */
13193 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
13199 /* .cpload should be in a .set noreorder section. */
13200 if (mips_opts.noreorder == 0)
13201 as_warn (_(".cpload not in noreorder section"));
13203 reg = tc_get_register (0);
13205 /* If we need to produce a 64-bit address, we are better off using
13206 the default instruction sequence. */
13207 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
13209 ex.X_op = O_symbol;
13210 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
13212 ex.X_op_symbol = NULL;
13213 ex.X_add_number = 0;
13215 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13216 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
13219 macro_build_lui (&ex, mips_gp_register);
13220 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
13221 mips_gp_register, BFD_RELOC_LO16);
13223 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
13224 mips_gp_register, reg);
13227 demand_empty_rest_of_line ();
13230 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
13231 .cpsetup $reg1, offset|$reg2, label
13233 If offset is given, this results in:
13234 sd $gp, offset($sp)
13235 lui $gp, %hi(%neg(%gp_rel(label)))
13236 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13237 daddu $gp, $gp, $reg1
13239 If $reg2 is given, this results in:
13240 daddu $reg2, $gp, $0
13241 lui $gp, %hi(%neg(%gp_rel(label)))
13242 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13243 daddu $gp, $gp, $reg1
13244 $reg1 is normally $25 == $t9.
13246 The -mno-shared option replaces the last three instructions with
13248 addiu $gp,$gp,%lo(_gp) */
13251 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
13253 expressionS ex_off;
13254 expressionS ex_sym;
13257 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
13258 We also need NewABI support. */
13259 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13265 reg1 = tc_get_register (0);
13266 SKIP_WHITESPACE ();
13267 if (*input_line_pointer != ',')
13269 as_bad (_("missing argument separator ',' for .cpsetup"));
13273 ++input_line_pointer;
13274 SKIP_WHITESPACE ();
13275 if (*input_line_pointer == '$')
13277 mips_cpreturn_register = tc_get_register (0);
13278 mips_cpreturn_offset = -1;
13282 mips_cpreturn_offset = get_absolute_expression ();
13283 mips_cpreturn_register = -1;
13285 SKIP_WHITESPACE ();
13286 if (*input_line_pointer != ',')
13288 as_bad (_("missing argument separator ',' for .cpsetup"));
13292 ++input_line_pointer;
13293 SKIP_WHITESPACE ();
13294 expression (&ex_sym);
13297 if (mips_cpreturn_register == -1)
13299 ex_off.X_op = O_constant;
13300 ex_off.X_add_symbol = NULL;
13301 ex_off.X_op_symbol = NULL;
13302 ex_off.X_add_number = mips_cpreturn_offset;
13304 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
13305 BFD_RELOC_LO16, SP);
13308 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
13309 mips_gp_register, 0);
13311 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
13313 macro_build (&ex_sym, "lui", "t,u", mips_gp_register,
13314 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
13317 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
13318 mips_gp_register, -1, BFD_RELOC_GPREL16,
13319 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
13321 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
13322 mips_gp_register, reg1);
13328 ex.X_op = O_symbol;
13329 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
13330 ex.X_op_symbol = NULL;
13331 ex.X_add_number = 0;
13333 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13334 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
13336 macro_build_lui (&ex, mips_gp_register);
13337 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
13338 mips_gp_register, BFD_RELOC_LO16);
13343 demand_empty_rest_of_line ();
13347 s_cplocal (int ignore ATTRIBUTE_UNUSED)
13349 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
13350 .cplocal is ignored. */
13351 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13357 mips_gp_register = tc_get_register (0);
13358 demand_empty_rest_of_line ();
13361 /* Handle the .cprestore pseudo-op. This stores $gp into a given
13362 offset from $sp. The offset is remembered, and after making a PIC
13363 call $gp is restored from that location. */
13366 s_cprestore (int ignore ATTRIBUTE_UNUSED)
13370 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13371 .cprestore is ignored. */
13372 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
13378 mips_cprestore_offset = get_absolute_expression ();
13379 mips_cprestore_valid = 1;
13381 ex.X_op = O_constant;
13382 ex.X_add_symbol = NULL;
13383 ex.X_op_symbol = NULL;
13384 ex.X_add_number = mips_cprestore_offset;
13387 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
13388 SP, HAVE_64BIT_ADDRESSES);
13391 demand_empty_rest_of_line ();
13394 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
13395 was given in the preceding .cpsetup, it results in:
13396 ld $gp, offset($sp)
13398 If a register $reg2 was given there, it results in:
13399 daddu $gp, $reg2, $0 */
13402 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
13406 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
13407 We also need NewABI support. */
13408 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13415 if (mips_cpreturn_register == -1)
13417 ex.X_op = O_constant;
13418 ex.X_add_symbol = NULL;
13419 ex.X_op_symbol = NULL;
13420 ex.X_add_number = mips_cpreturn_offset;
13422 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
13425 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
13426 mips_cpreturn_register, 0);
13429 demand_empty_rest_of_line ();
13432 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
13433 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
13434 use in DWARF debug information. */
13437 s_dtprel_internal (size_t bytes)
13444 if (ex.X_op != O_symbol)
13446 as_bad (_("Unsupported use of %s"), (bytes == 8
13449 ignore_rest_of_line ();
13452 p = frag_more (bytes);
13453 md_number_to_chars (p, 0, bytes);
13454 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
13456 ? BFD_RELOC_MIPS_TLS_DTPREL64
13457 : BFD_RELOC_MIPS_TLS_DTPREL32));
13459 demand_empty_rest_of_line ();
13462 /* Handle .dtprelword. */
13465 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
13467 s_dtprel_internal (4);
13470 /* Handle .dtpreldword. */
13473 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
13475 s_dtprel_internal (8);
13478 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
13479 code. It sets the offset to use in gp_rel relocations. */
13482 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
13484 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
13485 We also need NewABI support. */
13486 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13492 mips_gprel_offset = get_absolute_expression ();
13494 demand_empty_rest_of_line ();
13497 /* Handle the .gpword pseudo-op. This is used when generating PIC
13498 code. It generates a 32 bit GP relative reloc. */
13501 s_gpword (int ignore ATTRIBUTE_UNUSED)
13503 segment_info_type *si;
13504 struct insn_label_list *l;
13509 /* When not generating PIC code, this is treated as .word. */
13510 if (mips_pic != SVR4_PIC)
13516 si = seg_info (now_seg);
13517 l = si->label_list;
13518 label = l != NULL ? l->label : NULL;
13519 mips_emit_delays ();
13521 mips_align (2, 0, label);
13522 mips_clear_insn_labels ();
13526 if (ex.X_op != O_symbol || ex.X_add_number != 0)
13528 as_bad (_("Unsupported use of .gpword"));
13529 ignore_rest_of_line ();
13533 md_number_to_chars (p, 0, 4);
13534 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
13535 BFD_RELOC_GPREL32);
13537 demand_empty_rest_of_line ();
13541 s_gpdword (int ignore ATTRIBUTE_UNUSED)
13543 segment_info_type *si;
13544 struct insn_label_list *l;
13549 /* When not generating PIC code, this is treated as .dword. */
13550 if (mips_pic != SVR4_PIC)
13556 si = seg_info (now_seg);
13557 l = si->label_list;
13558 label = l != NULL ? l->label : NULL;
13559 mips_emit_delays ();
13561 mips_align (3, 0, label);
13562 mips_clear_insn_labels ();
13566 if (ex.X_op != O_symbol || ex.X_add_number != 0)
13568 as_bad (_("Unsupported use of .gpdword"));
13569 ignore_rest_of_line ();
13573 md_number_to_chars (p, 0, 8);
13574 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
13575 BFD_RELOC_GPREL32)->fx_tcbit = 1;
13577 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
13578 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
13579 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
13581 demand_empty_rest_of_line ();
13584 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
13585 tables in SVR4 PIC code. */
13588 s_cpadd (int ignore ATTRIBUTE_UNUSED)
13592 /* This is ignored when not generating SVR4 PIC code. */
13593 if (mips_pic != SVR4_PIC)
13599 /* Add $gp to the register named as an argument. */
13601 reg = tc_get_register (0);
13602 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
13605 demand_empty_rest_of_line ();
13608 /* Handle the .insn pseudo-op. This marks instruction labels in
13609 mips16 mode. This permits the linker to handle them specially,
13610 such as generating jalx instructions when needed. We also make
13611 them odd for the duration of the assembly, in order to generate the
13612 right sort of code. We will make them even in the adjust_symtab
13613 routine, while leaving them marked. This is convenient for the
13614 debugger and the disassembler. The linker knows to make them odd
13618 s_insn (int ignore ATTRIBUTE_UNUSED)
13620 mips16_mark_labels ();
13622 demand_empty_rest_of_line ();
13625 /* Handle a .stabn directive. We need these in order to mark a label
13626 as being a mips16 text label correctly. Sometimes the compiler
13627 will emit a label, followed by a .stabn, and then switch sections.
13628 If the label and .stabn are in mips16 mode, then the label is
13629 really a mips16 text label. */
13632 s_mips_stab (int type)
13635 mips16_mark_labels ();
13640 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
13643 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
13650 name = input_line_pointer;
13651 c = get_symbol_end ();
13652 symbolP = symbol_find_or_make (name);
13653 S_SET_WEAK (symbolP);
13654 *input_line_pointer = c;
13656 SKIP_WHITESPACE ();
13658 if (! is_end_of_line[(unsigned char) *input_line_pointer])
13660 if (S_IS_DEFINED (symbolP))
13662 as_bad ("ignoring attempt to redefine symbol %s",
13663 S_GET_NAME (symbolP));
13664 ignore_rest_of_line ();
13668 if (*input_line_pointer == ',')
13670 ++input_line_pointer;
13671 SKIP_WHITESPACE ();
13675 if (exp.X_op != O_symbol)
13677 as_bad ("bad .weakext directive");
13678 ignore_rest_of_line ();
13681 symbol_set_value_expression (symbolP, &exp);
13684 demand_empty_rest_of_line ();
13687 /* Parse a register string into a number. Called from the ECOFF code
13688 to parse .frame. The argument is non-zero if this is the frame
13689 register, so that we can record it in mips_frame_reg. */
13692 tc_get_register (int frame)
13696 SKIP_WHITESPACE ();
13697 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
13701 mips_frame_reg = reg != 0 ? reg : SP;
13702 mips_frame_reg_valid = 1;
13703 mips_cprestore_valid = 0;
13709 md_section_align (asection *seg, valueT addr)
13711 int align = bfd_get_section_alignment (stdoutput, seg);
13715 /* We don't need to align ELF sections to the full alignment.
13716 However, Irix 5 may prefer that we align them at least to a 16
13717 byte boundary. We don't bother to align the sections if we
13718 are targeted for an embedded system. */
13719 if (strncmp (TARGET_OS, "elf", 3) == 0)
13725 return ((addr + (1 << align) - 1) & (-1 << align));
13728 /* Utility routine, called from above as well. If called while the
13729 input file is still being read, it's only an approximation. (For
13730 example, a symbol may later become defined which appeared to be
13731 undefined earlier.) */
13734 nopic_need_relax (symbolS *sym, int before_relaxing)
13739 if (g_switch_value > 0)
13741 const char *symname;
13744 /* Find out whether this symbol can be referenced off the $gp
13745 register. It can be if it is smaller than the -G size or if
13746 it is in the .sdata or .sbss section. Certain symbols can
13747 not be referenced off the $gp, although it appears as though
13749 symname = S_GET_NAME (sym);
13750 if (symname != (const char *) NULL
13751 && (strcmp (symname, "eprol") == 0
13752 || strcmp (symname, "etext") == 0
13753 || strcmp (symname, "_gp") == 0
13754 || strcmp (symname, "edata") == 0
13755 || strcmp (symname, "_fbss") == 0
13756 || strcmp (symname, "_fdata") == 0
13757 || strcmp (symname, "_ftext") == 0
13758 || strcmp (symname, "end") == 0
13759 || strcmp (symname, "_gp_disp") == 0))
13761 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
13763 #ifndef NO_ECOFF_DEBUGGING
13764 || (symbol_get_obj (sym)->ecoff_extern_size != 0
13765 && (symbol_get_obj (sym)->ecoff_extern_size
13766 <= g_switch_value))
13768 /* We must defer this decision until after the whole
13769 file has been read, since there might be a .extern
13770 after the first use of this symbol. */
13771 || (before_relaxing
13772 #ifndef NO_ECOFF_DEBUGGING
13773 && symbol_get_obj (sym)->ecoff_extern_size == 0
13775 && S_GET_VALUE (sym) == 0)
13776 || (S_GET_VALUE (sym) != 0
13777 && S_GET_VALUE (sym) <= g_switch_value)))
13781 const char *segname;
13783 segname = segment_name (S_GET_SEGMENT (sym));
13784 assert (strcmp (segname, ".lit8") != 0
13785 && strcmp (segname, ".lit4") != 0);
13786 change = (strcmp (segname, ".sdata") != 0
13787 && strcmp (segname, ".sbss") != 0
13788 && strncmp (segname, ".sdata.", 7) != 0
13789 && strncmp (segname, ".sbss.", 6) != 0
13790 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
13791 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
13796 /* We are not optimizing for the $gp register. */
13801 /* Return true if the given symbol should be considered local for SVR4 PIC. */
13804 pic_need_relax (symbolS *sym, asection *segtype)
13808 /* Handle the case of a symbol equated to another symbol. */
13809 while (symbol_equated_reloc_p (sym))
13813 /* It's possible to get a loop here in a badly written program. */
13814 n = symbol_get_value_expression (sym)->X_add_symbol;
13820 if (symbol_section_p (sym))
13823 symsec = S_GET_SEGMENT (sym);
13825 /* This must duplicate the test in adjust_reloc_syms. */
13826 return (symsec != &bfd_und_section
13827 && symsec != &bfd_abs_section
13828 && !bfd_is_com_section (symsec)
13829 && !s_is_linkonce (sym, segtype)
13831 /* A global or weak symbol is treated as external. */
13832 && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
13838 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
13839 extended opcode. SEC is the section the frag is in. */
13842 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
13845 const struct mips16_immed_operand *op;
13847 int mintiny, maxtiny;
13851 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
13853 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
13856 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
13857 op = mips16_immed_operands;
13858 while (op->type != type)
13861 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
13866 if (type == '<' || type == '>' || type == '[' || type == ']')
13869 maxtiny = 1 << op->nbits;
13874 maxtiny = (1 << op->nbits) - 1;
13879 mintiny = - (1 << (op->nbits - 1));
13880 maxtiny = (1 << (op->nbits - 1)) - 1;
13883 sym_frag = symbol_get_frag (fragp->fr_symbol);
13884 val = S_GET_VALUE (fragp->fr_symbol);
13885 symsec = S_GET_SEGMENT (fragp->fr_symbol);
13891 /* We won't have the section when we are called from
13892 mips_relax_frag. However, we will always have been called
13893 from md_estimate_size_before_relax first. If this is a
13894 branch to a different section, we mark it as such. If SEC is
13895 NULL, and the frag is not marked, then it must be a branch to
13896 the same section. */
13899 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
13904 /* Must have been called from md_estimate_size_before_relax. */
13907 fragp->fr_subtype =
13908 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
13910 /* FIXME: We should support this, and let the linker
13911 catch branches and loads that are out of range. */
13912 as_bad_where (fragp->fr_file, fragp->fr_line,
13913 _("unsupported PC relative reference to different section"));
13917 if (fragp != sym_frag && sym_frag->fr_address == 0)
13918 /* Assume non-extended on the first relaxation pass.
13919 The address we have calculated will be bogus if this is
13920 a forward branch to another frag, as the forward frag
13921 will have fr_address == 0. */
13925 /* In this case, we know for sure that the symbol fragment is in
13926 the same section. If the relax_marker of the symbol fragment
13927 differs from the relax_marker of this fragment, we have not
13928 yet adjusted the symbol fragment fr_address. We want to add
13929 in STRETCH in order to get a better estimate of the address.
13930 This particularly matters because of the shift bits. */
13932 && sym_frag->relax_marker != fragp->relax_marker)
13936 /* Adjust stretch for any alignment frag. Note that if have
13937 been expanding the earlier code, the symbol may be
13938 defined in what appears to be an earlier frag. FIXME:
13939 This doesn't handle the fr_subtype field, which specifies
13940 a maximum number of bytes to skip when doing an
13942 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
13944 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
13947 stretch = - ((- stretch)
13948 & ~ ((1 << (int) f->fr_offset) - 1));
13950 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
13959 addr = fragp->fr_address + fragp->fr_fix;
13961 /* The base address rules are complicated. The base address of
13962 a branch is the following instruction. The base address of a
13963 PC relative load or add is the instruction itself, but if it
13964 is in a delay slot (in which case it can not be extended) use
13965 the address of the instruction whose delay slot it is in. */
13966 if (type == 'p' || type == 'q')
13970 /* If we are currently assuming that this frag should be
13971 extended, then, the current address is two bytes
13973 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13976 /* Ignore the low bit in the target, since it will be set
13977 for a text label. */
13978 if ((val & 1) != 0)
13981 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
13983 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
13986 val -= addr & ~ ((1 << op->shift) - 1);
13988 /* Branch offsets have an implicit 0 in the lowest bit. */
13989 if (type == 'p' || type == 'q')
13992 /* If any of the shifted bits are set, we must use an extended
13993 opcode. If the address depends on the size of this
13994 instruction, this can lead to a loop, so we arrange to always
13995 use an extended opcode. We only check this when we are in
13996 the main relaxation loop, when SEC is NULL. */
13997 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
13999 fragp->fr_subtype =
14000 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14004 /* If we are about to mark a frag as extended because the value
14005 is precisely maxtiny + 1, then there is a chance of an
14006 infinite loop as in the following code:
14011 In this case when the la is extended, foo is 0x3fc bytes
14012 away, so the la can be shrunk, but then foo is 0x400 away, so
14013 the la must be extended. To avoid this loop, we mark the
14014 frag as extended if it was small, and is about to become
14015 extended with a value of maxtiny + 1. */
14016 if (val == ((maxtiny + 1) << op->shift)
14017 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
14020 fragp->fr_subtype =
14021 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14025 else if (symsec != absolute_section && sec != NULL)
14026 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
14028 if ((val & ((1 << op->shift) - 1)) != 0
14029 || val < (mintiny << op->shift)
14030 || val > (maxtiny << op->shift))
14036 /* Compute the length of a branch sequence, and adjust the
14037 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
14038 worst-case length is computed, with UPDATE being used to indicate
14039 whether an unconditional (-1), branch-likely (+1) or regular (0)
14040 branch is to be computed. */
14042 relaxed_branch_length (fragS *fragp, asection *sec, int update)
14044 bfd_boolean toofar;
14048 && S_IS_DEFINED (fragp->fr_symbol)
14049 && sec == S_GET_SEGMENT (fragp->fr_symbol))
14054 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
14056 addr = fragp->fr_address + fragp->fr_fix + 4;
14060 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
14063 /* If the symbol is not defined or it's in a different segment,
14064 assume the user knows what's going on and emit a short
14070 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
14072 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype),
14073 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
14074 RELAX_BRANCH_LINK (fragp->fr_subtype),
14080 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
14083 if (mips_pic != NO_PIC)
14085 /* Additional space for PIC loading of target address. */
14087 if (mips_opts.isa == ISA_MIPS1)
14088 /* Additional space for $at-stabilizing nop. */
14092 /* If branch is conditional. */
14093 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
14100 /* Estimate the size of a frag before relaxing. Unless this is the
14101 mips16, we are not really relaxing here, and the final size is
14102 encoded in the subtype information. For the mips16, we have to
14103 decide whether we are using an extended opcode or not. */
14106 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
14110 if (RELAX_BRANCH_P (fragp->fr_subtype))
14113 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
14115 return fragp->fr_var;
14118 if (RELAX_MIPS16_P (fragp->fr_subtype))
14119 /* We don't want to modify the EXTENDED bit here; it might get us
14120 into infinite loops. We change it only in mips_relax_frag(). */
14121 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
14123 if (mips_pic == NO_PIC)
14124 change = nopic_need_relax (fragp->fr_symbol, 0);
14125 else if (mips_pic == SVR4_PIC)
14126 change = pic_need_relax (fragp->fr_symbol, segtype);
14127 else if (mips_pic == VXWORKS_PIC)
14128 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
14135 fragp->fr_subtype |= RELAX_USE_SECOND;
14136 return -RELAX_FIRST (fragp->fr_subtype);
14139 return -RELAX_SECOND (fragp->fr_subtype);
14142 /* This is called to see whether a reloc against a defined symbol
14143 should be converted into a reloc against a section. */
14146 mips_fix_adjustable (fixS *fixp)
14148 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
14149 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
14152 if (fixp->fx_addsy == NULL)
14155 /* If symbol SYM is in a mergeable section, relocations of the form
14156 SYM + 0 can usually be made section-relative. The mergeable data
14157 is then identified by the section offset rather than by the symbol.
14159 However, if we're generating REL LO16 relocations, the offset is split
14160 between the LO16 and parterning high part relocation. The linker will
14161 need to recalculate the complete offset in order to correctly identify
14164 The linker has traditionally not looked for the parterning high part
14165 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
14166 placed anywhere. Rather than break backwards compatibility by changing
14167 this, it seems better not to force the issue, and instead keep the
14168 original symbol. This will work with either linker behavior. */
14169 if ((lo16_reloc_p (fixp->fx_r_type)
14170 || reloc_needs_lo_p (fixp->fx_r_type))
14171 && HAVE_IN_PLACE_ADDENDS
14172 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
14176 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
14177 to a floating-point stub. The same is true for non-R_MIPS16_26
14178 relocations against MIPS16 functions; in this case, the stub becomes
14179 the function's canonical address.
14181 Floating-point stubs are stored in unique .mips16.call.* or
14182 .mips16.fn.* sections. If a stub T for function F is in section S,
14183 the first relocation in section S must be against F; this is how the
14184 linker determines the target function. All relocations that might
14185 resolve to T must also be against F. We therefore have the following
14186 restrictions, which are given in an intentionally-redundant way:
14188 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
14191 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
14192 if that stub might be used.
14194 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
14197 4. We cannot reduce a stub's relocations against MIPS16 symbols if
14198 that stub might be used.
14200 There is a further restriction:
14202 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols
14203 on targets with in-place addends; the relocation field cannot
14204 encode the low bit.
14206 For simplicity, we deal with (3)-(5) by not reducing _any_ relocation
14207 against a MIPS16 symbol.
14209 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
14210 relocation against some symbol R, no relocation against R may be
14211 reduced. (Note that this deals with (2) as well as (1) because
14212 relocations against global symbols will never be reduced on ELF
14213 targets.) This approach is a little simpler than trying to detect
14214 stub sections, and gives the "all or nothing" per-symbol consistency
14215 that we have for MIPS16 symbols. */
14217 && fixp->fx_subsy == NULL
14218 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
14219 || *symbol_get_tc (fixp->fx_addsy)))
14226 /* Translate internal representation of relocation info to BFD target
14230 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
14232 static arelent *retval[4];
14234 bfd_reloc_code_real_type code;
14236 memset (retval, 0, sizeof(retval));
14237 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
14238 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
14239 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
14240 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
14242 if (fixp->fx_pcrel)
14244 assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2);
14246 /* At this point, fx_addnumber is "symbol offset - pcrel address".
14247 Relocations want only the symbol offset. */
14248 reloc->addend = fixp->fx_addnumber + reloc->address;
14251 /* A gruesome hack which is a result of the gruesome gas
14252 reloc handling. What's worse, for COFF (as opposed to
14253 ECOFF), we might need yet another copy of reloc->address.
14254 See bfd_install_relocation. */
14255 reloc->addend += reloc->address;
14259 reloc->addend = fixp->fx_addnumber;
14261 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
14262 entry to be used in the relocation's section offset. */
14263 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
14265 reloc->address = reloc->addend;
14269 code = fixp->fx_r_type;
14271 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
14272 if (reloc->howto == NULL)
14274 as_bad_where (fixp->fx_file, fixp->fx_line,
14275 _("Can not represent %s relocation in this object file format"),
14276 bfd_get_reloc_code_name (code));
14283 /* Relax a machine dependent frag. This returns the amount by which
14284 the current size of the frag should change. */
14287 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
14289 if (RELAX_BRANCH_P (fragp->fr_subtype))
14291 offsetT old_var = fragp->fr_var;
14293 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
14295 return fragp->fr_var - old_var;
14298 if (! RELAX_MIPS16_P (fragp->fr_subtype))
14301 if (mips16_extended_frag (fragp, NULL, stretch))
14303 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14305 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
14310 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14312 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
14319 /* Convert a machine dependent frag. */
14322 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
14324 if (RELAX_BRANCH_P (fragp->fr_subtype))
14327 unsigned long insn;
14331 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
14333 if (target_big_endian)
14334 insn = bfd_getb32 (buf);
14336 insn = bfd_getl32 (buf);
14338 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
14340 /* We generate a fixup instead of applying it right now
14341 because, if there are linker relaxations, we're going to
14342 need the relocations. */
14343 exp.X_op = O_symbol;
14344 exp.X_add_symbol = fragp->fr_symbol;
14345 exp.X_add_number = fragp->fr_offset;
14347 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14348 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2);
14349 fixp->fx_file = fragp->fr_file;
14350 fixp->fx_line = fragp->fr_line;
14352 md_number_to_chars ((char *) buf, insn, 4);
14359 as_warn_where (fragp->fr_file, fragp->fr_line,
14360 _("relaxed out-of-range branch into a jump"));
14362 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
14365 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14367 /* Reverse the branch. */
14368 switch ((insn >> 28) & 0xf)
14371 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
14372 have the condition reversed by tweaking a single
14373 bit, and their opcodes all have 0x4???????. */
14374 assert ((insn & 0xf1000000) == 0x41000000);
14375 insn ^= 0x00010000;
14379 /* bltz 0x04000000 bgez 0x04010000
14380 bltzal 0x04100000 bgezal 0x04110000 */
14381 assert ((insn & 0xfc0e0000) == 0x04000000);
14382 insn ^= 0x00010000;
14386 /* beq 0x10000000 bne 0x14000000
14387 blez 0x18000000 bgtz 0x1c000000 */
14388 insn ^= 0x04000000;
14396 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
14398 /* Clear the and-link bit. */
14399 assert ((insn & 0xfc1c0000) == 0x04100000);
14401 /* bltzal 0x04100000 bgezal 0x04110000
14402 bltzall 0x04120000 bgezall 0x04130000 */
14403 insn &= ~0x00100000;
14406 /* Branch over the branch (if the branch was likely) or the
14407 full jump (not likely case). Compute the offset from the
14408 current instruction to branch to. */
14409 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14413 /* How many bytes in instructions we've already emitted? */
14414 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
14415 /* How many bytes in instructions from here to the end? */
14416 i = fragp->fr_var - i;
14418 /* Convert to instruction count. */
14420 /* Branch counts from the next instruction. */
14423 /* Branch over the jump. */
14424 md_number_to_chars ((char *) buf, insn, 4);
14428 md_number_to_chars ((char *) buf, 0, 4);
14431 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14433 /* beql $0, $0, 2f */
14435 /* Compute the PC offset from the current instruction to
14436 the end of the variable frag. */
14437 /* How many bytes in instructions we've already emitted? */
14438 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
14439 /* How many bytes in instructions from here to the end? */
14440 i = fragp->fr_var - i;
14441 /* Convert to instruction count. */
14443 /* Don't decrement i, because we want to branch over the
14447 md_number_to_chars ((char *) buf, insn, 4);
14450 md_number_to_chars ((char *) buf, 0, 4);
14455 if (mips_pic == NO_PIC)
14458 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
14459 ? 0x0c000000 : 0x08000000);
14460 exp.X_op = O_symbol;
14461 exp.X_add_symbol = fragp->fr_symbol;
14462 exp.X_add_number = fragp->fr_offset;
14464 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14465 4, &exp, FALSE, BFD_RELOC_MIPS_JMP);
14466 fixp->fx_file = fragp->fr_file;
14467 fixp->fx_line = fragp->fr_line;
14469 md_number_to_chars ((char *) buf, insn, 4);
14474 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
14475 insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000;
14476 exp.X_op = O_symbol;
14477 exp.X_add_symbol = fragp->fr_symbol;
14478 exp.X_add_number = fragp->fr_offset;
14480 if (fragp->fr_offset)
14482 exp.X_add_symbol = make_expr_symbol (&exp);
14483 exp.X_add_number = 0;
14486 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14487 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16);
14488 fixp->fx_file = fragp->fr_file;
14489 fixp->fx_line = fragp->fr_line;
14491 md_number_to_chars ((char *) buf, insn, 4);
14494 if (mips_opts.isa == ISA_MIPS1)
14497 md_number_to_chars ((char *) buf, 0, 4);
14501 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
14502 insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000;
14504 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14505 4, &exp, FALSE, BFD_RELOC_LO16);
14506 fixp->fx_file = fragp->fr_file;
14507 fixp->fx_line = fragp->fr_line;
14509 md_number_to_chars ((char *) buf, insn, 4);
14513 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
14518 md_number_to_chars ((char *) buf, insn, 4);
14523 assert (buf == (bfd_byte *)fragp->fr_literal
14524 + fragp->fr_fix + fragp->fr_var);
14526 fragp->fr_fix += fragp->fr_var;
14531 if (RELAX_MIPS16_P (fragp->fr_subtype))
14534 const struct mips16_immed_operand *op;
14535 bfd_boolean small, ext;
14538 unsigned long insn;
14539 bfd_boolean use_extend;
14540 unsigned short extend;
14542 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
14543 op = mips16_immed_operands;
14544 while (op->type != type)
14547 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14558 resolve_symbol_value (fragp->fr_symbol);
14559 val = S_GET_VALUE (fragp->fr_symbol);
14564 addr = fragp->fr_address + fragp->fr_fix;
14566 /* The rules for the base address of a PC relative reloc are
14567 complicated; see mips16_extended_frag. */
14568 if (type == 'p' || type == 'q')
14573 /* Ignore the low bit in the target, since it will be
14574 set for a text label. */
14575 if ((val & 1) != 0)
14578 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
14580 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
14583 addr &= ~ (addressT) ((1 << op->shift) - 1);
14586 /* Make sure the section winds up with the alignment we have
14589 record_alignment (asec, op->shift);
14593 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
14594 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
14595 as_warn_where (fragp->fr_file, fragp->fr_line,
14596 _("extended instruction in delay slot"));
14598 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
14600 if (target_big_endian)
14601 insn = bfd_getb16 (buf);
14603 insn = bfd_getl16 (buf);
14605 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
14606 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
14607 small, ext, &insn, &use_extend, &extend);
14611 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
14612 fragp->fr_fix += 2;
14616 md_number_to_chars ((char *) buf, insn, 2);
14617 fragp->fr_fix += 2;
14625 first = RELAX_FIRST (fragp->fr_subtype);
14626 second = RELAX_SECOND (fragp->fr_subtype);
14627 fixp = (fixS *) fragp->fr_opcode;
14629 /* Possibly emit a warning if we've chosen the longer option. */
14630 if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0)
14631 == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0))
14633 const char *msg = macro_warning (fragp->fr_subtype);
14635 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
14638 /* Go through all the fixups for the first sequence. Disable them
14639 (by marking them as done) if we're going to use the second
14640 sequence instead. */
14642 && fixp->fx_frag == fragp
14643 && fixp->fx_where < fragp->fr_fix - second)
14645 if (fragp->fr_subtype & RELAX_USE_SECOND)
14647 fixp = fixp->fx_next;
14650 /* Go through the fixups for the second sequence. Disable them if
14651 we're going to use the first sequence, otherwise adjust their
14652 addresses to account for the relaxation. */
14653 while (fixp && fixp->fx_frag == fragp)
14655 if (fragp->fr_subtype & RELAX_USE_SECOND)
14656 fixp->fx_where -= first;
14659 fixp = fixp->fx_next;
14662 /* Now modify the frag contents. */
14663 if (fragp->fr_subtype & RELAX_USE_SECOND)
14667 start = fragp->fr_literal + fragp->fr_fix - first - second;
14668 memmove (start, start + first, second);
14669 fragp->fr_fix -= first;
14672 fragp->fr_fix -= second;
14678 /* This function is called after the relocs have been generated.
14679 We've been storing mips16 text labels as odd. Here we convert them
14680 back to even for the convenience of the debugger. */
14683 mips_frob_file_after_relocs (void)
14686 unsigned int count, i;
14691 syms = bfd_get_outsymbols (stdoutput);
14692 count = bfd_get_symcount (stdoutput);
14693 for (i = 0; i < count; i++, syms++)
14695 if (ELF_ST_IS_MIPS16 (elf_symbol (*syms)->internal_elf_sym.st_other)
14696 && ((*syms)->value & 1) != 0)
14698 (*syms)->value &= ~1;
14699 /* If the symbol has an odd size, it was probably computed
14700 incorrectly, so adjust that as well. */
14701 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
14702 ++elf_symbol (*syms)->internal_elf_sym.st_size;
14709 /* This function is called whenever a label is defined. It is used
14710 when handling branch delays; if a branch has a label, we assume we
14711 can not move it. */
14714 mips_define_label (symbolS *sym)
14716 segment_info_type *si = seg_info (now_seg);
14717 struct insn_label_list *l;
14719 if (free_insn_labels == NULL)
14720 l = (struct insn_label_list *) xmalloc (sizeof *l);
14723 l = free_insn_labels;
14724 free_insn_labels = l->next;
14728 l->next = si->label_list;
14729 si->label_list = l;
14732 dwarf2_emit_label (sym);
14736 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14738 /* Some special processing for a MIPS ELF file. */
14741 mips_elf_final_processing (void)
14743 /* Write out the register information. */
14744 if (mips_abi != N64_ABI)
14748 s.ri_gprmask = mips_gprmask;
14749 s.ri_cprmask[0] = mips_cprmask[0];
14750 s.ri_cprmask[1] = mips_cprmask[1];
14751 s.ri_cprmask[2] = mips_cprmask[2];
14752 s.ri_cprmask[3] = mips_cprmask[3];
14753 /* The gp_value field is set by the MIPS ELF backend. */
14755 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
14756 ((Elf32_External_RegInfo *)
14757 mips_regmask_frag));
14761 Elf64_Internal_RegInfo s;
14763 s.ri_gprmask = mips_gprmask;
14765 s.ri_cprmask[0] = mips_cprmask[0];
14766 s.ri_cprmask[1] = mips_cprmask[1];
14767 s.ri_cprmask[2] = mips_cprmask[2];
14768 s.ri_cprmask[3] = mips_cprmask[3];
14769 /* The gp_value field is set by the MIPS ELF backend. */
14771 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
14772 ((Elf64_External_RegInfo *)
14773 mips_regmask_frag));
14776 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
14777 sort of BFD interface for this. */
14778 if (mips_any_noreorder)
14779 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
14780 if (mips_pic != NO_PIC)
14782 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
14783 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
14786 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
14788 /* Set MIPS ELF flags for ASEs. */
14789 /* We may need to define a new flag for DSP ASE, and set this flag when
14790 file_ase_dsp is true. */
14791 /* Same for DSP R2. */
14792 /* We may need to define a new flag for MT ASE, and set this flag when
14793 file_ase_mt is true. */
14794 if (file_ase_mips16)
14795 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
14796 #if 0 /* XXX FIXME */
14797 if (file_ase_mips3d)
14798 elf_elfheader (stdoutput)->e_flags |= ???;
14801 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
14803 /* Set the MIPS ELF ABI flags. */
14804 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
14805 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
14806 else if (mips_abi == O64_ABI)
14807 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
14808 else if (mips_abi == EABI_ABI)
14810 if (!file_mips_gp32)
14811 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
14813 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
14815 else if (mips_abi == N32_ABI)
14816 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
14818 /* Nothing to do for N64_ABI. */
14820 if (mips_32bitmode)
14821 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
14823 #if 0 /* XXX FIXME */
14824 /* 32 bit code with 64 bit FP registers. */
14825 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
14826 elf_elfheader (stdoutput)->e_flags |= ???;
14830 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
14832 typedef struct proc {
14834 symbolS *func_end_sym;
14835 unsigned long reg_mask;
14836 unsigned long reg_offset;
14837 unsigned long fpreg_mask;
14838 unsigned long fpreg_offset;
14839 unsigned long frame_offset;
14840 unsigned long frame_reg;
14841 unsigned long pc_reg;
14844 static procS cur_proc;
14845 static procS *cur_proc_ptr;
14846 static int numprocs;
14848 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal
14852 mips_nop_opcode (void)
14854 return seg_info (now_seg)->tc_segment_info_data.mips16;
14857 /* Fill in an rs_align_code fragment. This only needs to do something
14858 for MIPS16 code, where 0 is not a nop. */
14861 mips_handle_align (fragS *fragp)
14865 if (fragp->fr_type != rs_align_code)
14868 p = fragp->fr_literal + fragp->fr_fix;
14873 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
14879 md_number_to_chars (p, mips16_nop_insn.insn_opcode, 2);
14885 md_obj_begin (void)
14892 /* Check for premature end, nesting errors, etc. */
14894 as_warn (_("missing .end at end of assembly"));
14903 if (*input_line_pointer == '-')
14905 ++input_line_pointer;
14908 if (!ISDIGIT (*input_line_pointer))
14909 as_bad (_("expected simple number"));
14910 if (input_line_pointer[0] == '0')
14912 if (input_line_pointer[1] == 'x')
14914 input_line_pointer += 2;
14915 while (ISXDIGIT (*input_line_pointer))
14918 val |= hex_value (*input_line_pointer++);
14920 return negative ? -val : val;
14924 ++input_line_pointer;
14925 while (ISDIGIT (*input_line_pointer))
14928 val |= *input_line_pointer++ - '0';
14930 return negative ? -val : val;
14933 if (!ISDIGIT (*input_line_pointer))
14935 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
14936 *input_line_pointer, *input_line_pointer);
14937 as_warn (_("invalid number"));
14940 while (ISDIGIT (*input_line_pointer))
14943 val += *input_line_pointer++ - '0';
14945 return negative ? -val : val;
14948 /* The .file directive; just like the usual .file directive, but there
14949 is an initial number which is the ECOFF file index. In the non-ECOFF
14950 case .file implies DWARF-2. */
14953 s_mips_file (int x ATTRIBUTE_UNUSED)
14955 static int first_file_directive = 0;
14957 if (ECOFF_DEBUGGING)
14966 filename = dwarf2_directive_file (0);
14968 /* Versions of GCC up to 3.1 start files with a ".file"
14969 directive even for stabs output. Make sure that this
14970 ".file" is handled. Note that you need a version of GCC
14971 after 3.1 in order to support DWARF-2 on MIPS. */
14972 if (filename != NULL && ! first_file_directive)
14974 (void) new_logical_line (filename, -1);
14975 s_app_file_string (filename, 0);
14977 first_file_directive = 1;
14981 /* The .loc directive, implying DWARF-2. */
14984 s_mips_loc (int x ATTRIBUTE_UNUSED)
14986 if (!ECOFF_DEBUGGING)
14987 dwarf2_directive_loc (0);
14990 /* The .end directive. */
14993 s_mips_end (int x ATTRIBUTE_UNUSED)
14997 /* Following functions need their own .frame and .cprestore directives. */
14998 mips_frame_reg_valid = 0;
14999 mips_cprestore_valid = 0;
15001 if (!is_end_of_line[(unsigned char) *input_line_pointer])
15004 demand_empty_rest_of_line ();
15009 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
15010 as_warn (_(".end not in text section"));
15014 as_warn (_(".end directive without a preceding .ent directive."));
15015 demand_empty_rest_of_line ();
15021 assert (S_GET_NAME (p));
15022 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
15023 as_warn (_(".end symbol does not match .ent symbol."));
15025 if (debug_type == DEBUG_STABS)
15026 stabs_generate_asm_endfunc (S_GET_NAME (p),
15030 as_warn (_(".end directive missing or unknown symbol"));
15033 /* Create an expression to calculate the size of the function. */
15034 if (p && cur_proc_ptr)
15036 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
15037 expressionS *exp = xmalloc (sizeof (expressionS));
15040 exp->X_op = O_subtract;
15041 exp->X_add_symbol = symbol_temp_new_now ();
15042 exp->X_op_symbol = p;
15043 exp->X_add_number = 0;
15045 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
15048 /* Generate a .pdr section. */
15049 if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr)
15051 segT saved_seg = now_seg;
15052 subsegT saved_subseg = now_subseg;
15057 dot = frag_now_fix ();
15059 #ifdef md_flush_pending_output
15060 md_flush_pending_output ();
15064 subseg_set (pdr_seg, 0);
15066 /* Write the symbol. */
15067 exp.X_op = O_symbol;
15068 exp.X_add_symbol = p;
15069 exp.X_add_number = 0;
15070 emit_expr (&exp, 4);
15072 fragp = frag_more (7 * 4);
15074 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
15075 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
15076 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
15077 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
15078 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
15079 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
15080 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
15082 subseg_set (saved_seg, saved_subseg);
15084 #endif /* OBJ_ELF */
15086 cur_proc_ptr = NULL;
15089 /* The .aent and .ent directives. */
15092 s_mips_ent (int aent)
15096 symbolP = get_symbol ();
15097 if (*input_line_pointer == ',')
15098 ++input_line_pointer;
15099 SKIP_WHITESPACE ();
15100 if (ISDIGIT (*input_line_pointer)
15101 || *input_line_pointer == '-')
15104 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
15105 as_warn (_(".ent or .aent not in text section."));
15107 if (!aent && cur_proc_ptr)
15108 as_warn (_("missing .end"));
15112 /* This function needs its own .frame and .cprestore directives. */
15113 mips_frame_reg_valid = 0;
15114 mips_cprestore_valid = 0;
15116 cur_proc_ptr = &cur_proc;
15117 memset (cur_proc_ptr, '\0', sizeof (procS));
15119 cur_proc_ptr->func_sym = symbolP;
15121 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
15125 if (debug_type == DEBUG_STABS)
15126 stabs_generate_asm_func (S_GET_NAME (symbolP),
15127 S_GET_NAME (symbolP));
15130 demand_empty_rest_of_line ();
15133 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
15134 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
15135 s_mips_frame is used so that we can set the PDR information correctly.
15136 We can't use the ecoff routines because they make reference to the ecoff
15137 symbol table (in the mdebug section). */
15140 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
15143 if (IS_ELF && !ECOFF_DEBUGGING)
15147 if (cur_proc_ptr == (procS *) NULL)
15149 as_warn (_(".frame outside of .ent"));
15150 demand_empty_rest_of_line ();
15154 cur_proc_ptr->frame_reg = tc_get_register (1);
15156 SKIP_WHITESPACE ();
15157 if (*input_line_pointer++ != ','
15158 || get_absolute_expression_and_terminator (&val) != ',')
15160 as_warn (_("Bad .frame directive"));
15161 --input_line_pointer;
15162 demand_empty_rest_of_line ();
15166 cur_proc_ptr->frame_offset = val;
15167 cur_proc_ptr->pc_reg = tc_get_register (0);
15169 demand_empty_rest_of_line ();
15172 #endif /* OBJ_ELF */
15176 /* The .fmask and .mask directives. If the mdebug section is present
15177 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
15178 embedded targets, s_mips_mask is used so that we can set the PDR
15179 information correctly. We can't use the ecoff routines because they
15180 make reference to the ecoff symbol table (in the mdebug section). */
15183 s_mips_mask (int reg_type)
15186 if (IS_ELF && !ECOFF_DEBUGGING)
15190 if (cur_proc_ptr == (procS *) NULL)
15192 as_warn (_(".mask/.fmask outside of .ent"));
15193 demand_empty_rest_of_line ();
15197 if (get_absolute_expression_and_terminator (&mask) != ',')
15199 as_warn (_("Bad .mask/.fmask directive"));
15200 --input_line_pointer;
15201 demand_empty_rest_of_line ();
15205 off = get_absolute_expression ();
15207 if (reg_type == 'F')
15209 cur_proc_ptr->fpreg_mask = mask;
15210 cur_proc_ptr->fpreg_offset = off;
15214 cur_proc_ptr->reg_mask = mask;
15215 cur_proc_ptr->reg_offset = off;
15218 demand_empty_rest_of_line ();
15221 #endif /* OBJ_ELF */
15222 s_ignore (reg_type);
15225 /* A table describing all the processors gas knows about. Names are
15226 matched in the order listed.
15228 To ease comparison, please keep this table in the same order as
15229 gcc's mips_cpu_info_table[]. */
15230 static const struct mips_cpu_info mips_cpu_info_table[] =
15232 /* Entries for generic ISAs */
15233 { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 },
15234 { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 },
15235 { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 },
15236 { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 },
15237 { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 },
15238 { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 },
15239 { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 },
15240 { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
15241 { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
15244 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
15245 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
15246 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
15249 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
15252 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
15253 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
15254 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
15255 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
15256 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
15257 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
15258 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
15259 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
15260 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
15261 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
15262 { "orion", 0, ISA_MIPS3, CPU_R4600 },
15263 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
15264 /* ST Microelectronics Loongson 2E and 2F cores */
15265 { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E },
15266 { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F },
15269 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
15270 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
15271 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
15272 { "r14000", 0, ISA_MIPS4, CPU_R14000 },
15273 { "r16000", 0, ISA_MIPS4, CPU_R16000 },
15274 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
15275 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
15276 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
15277 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
15278 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
15279 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
15280 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
15281 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
15282 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
15283 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
15286 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
15287 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
15288 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
15289 { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
15291 /* MIPS 32 Release 2 */
15292 { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15293 { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15294 { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15295 { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
15296 { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15297 { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15298 { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15299 { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15300 { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15301 { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15302 /* Deprecated forms of the above. */
15303 { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15304 { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15305 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
15306 { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15307 { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15308 { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15309 { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15310 /* Deprecated forms of the above. */
15311 { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15312 { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15313 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
15314 { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15315 ISA_MIPS32R2, CPU_MIPS32R2 },
15316 { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15317 ISA_MIPS32R2, CPU_MIPS32R2 },
15318 { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15319 ISA_MIPS32R2, CPU_MIPS32R2 },
15320 { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15321 ISA_MIPS32R2, CPU_MIPS32R2 },
15322 /* Deprecated forms of the above. */
15323 { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15324 ISA_MIPS32R2, CPU_MIPS32R2 },
15325 { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15326 ISA_MIPS32R2, CPU_MIPS32R2 },
15327 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
15328 { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15329 ISA_MIPS32R2, CPU_MIPS32R2 },
15330 { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15331 ISA_MIPS32R2, CPU_MIPS32R2 },
15332 { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15333 ISA_MIPS32R2, CPU_MIPS32R2 },
15334 { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15335 ISA_MIPS32R2, CPU_MIPS32R2 },
15336 { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15337 ISA_MIPS32R2, CPU_MIPS32R2 },
15338 /* Deprecated forms of the above. */
15339 { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15340 ISA_MIPS32R2, CPU_MIPS32R2 },
15341 { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15342 ISA_MIPS32R2, CPU_MIPS32R2 },
15345 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
15346 { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
15347 { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
15348 { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
15350 /* Broadcom SB-1 CPU core */
15351 { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
15352 ISA_MIPS64, CPU_SB1 },
15353 /* Broadcom SB-1A CPU core */
15354 { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
15355 ISA_MIPS64, CPU_SB1 },
15357 /* MIPS 64 Release 2 */
15359 /* Cavium Networks Octeon CPU core */
15360 { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
15363 { "xlr", 0, ISA_MIPS64, CPU_XLR },
15370 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
15371 with a final "000" replaced by "k". Ignore case.
15373 Note: this function is shared between GCC and GAS. */
15376 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
15378 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
15379 given++, canonical++;
15381 return ((*given == 0 && *canonical == 0)
15382 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
15386 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
15387 CPU name. We've traditionally allowed a lot of variation here.
15389 Note: this function is shared between GCC and GAS. */
15392 mips_matching_cpu_name_p (const char *canonical, const char *given)
15394 /* First see if the name matches exactly, or with a final "000"
15395 turned into "k". */
15396 if (mips_strict_matching_cpu_name_p (canonical, given))
15399 /* If not, try comparing based on numerical designation alone.
15400 See if GIVEN is an unadorned number, or 'r' followed by a number. */
15401 if (TOLOWER (*given) == 'r')
15403 if (!ISDIGIT (*given))
15406 /* Skip over some well-known prefixes in the canonical name,
15407 hoping to find a number there too. */
15408 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
15410 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
15412 else if (TOLOWER (canonical[0]) == 'r')
15415 return mips_strict_matching_cpu_name_p (canonical, given);
15419 /* Parse an option that takes the name of a processor as its argument.
15420 OPTION is the name of the option and CPU_STRING is the argument.
15421 Return the corresponding processor enumeration if the CPU_STRING is
15422 recognized, otherwise report an error and return null.
15424 A similar function exists in GCC. */
15426 static const struct mips_cpu_info *
15427 mips_parse_cpu (const char *option, const char *cpu_string)
15429 const struct mips_cpu_info *p;
15431 /* 'from-abi' selects the most compatible architecture for the given
15432 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
15433 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15434 version. Look first at the -mgp options, if given, otherwise base
15435 the choice on MIPS_DEFAULT_64BIT.
15437 Treat NO_ABI like the EABIs. One reason to do this is that the
15438 plain 'mips' and 'mips64' configs have 'from-abi' as their default
15439 architecture. This code picks MIPS I for 'mips' and MIPS III for
15440 'mips64', just as we did in the days before 'from-abi'. */
15441 if (strcasecmp (cpu_string, "from-abi") == 0)
15443 if (ABI_NEEDS_32BIT_REGS (mips_abi))
15444 return mips_cpu_info_from_isa (ISA_MIPS1);
15446 if (ABI_NEEDS_64BIT_REGS (mips_abi))
15447 return mips_cpu_info_from_isa (ISA_MIPS3);
15449 if (file_mips_gp32 >= 0)
15450 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
15452 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
15457 /* 'default' has traditionally been a no-op. Probably not very useful. */
15458 if (strcasecmp (cpu_string, "default") == 0)
15461 for (p = mips_cpu_info_table; p->name != 0; p++)
15462 if (mips_matching_cpu_name_p (p->name, cpu_string))
15465 as_bad ("Bad value (%s) for %s", cpu_string, option);
15469 /* Return the canonical processor information for ISA (a member of the
15470 ISA_MIPS* enumeration). */
15472 static const struct mips_cpu_info *
15473 mips_cpu_info_from_isa (int isa)
15477 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15478 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
15479 && isa == mips_cpu_info_table[i].isa)
15480 return (&mips_cpu_info_table[i]);
15485 static const struct mips_cpu_info *
15486 mips_cpu_info_from_arch (int arch)
15490 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15491 if (arch == mips_cpu_info_table[i].cpu)
15492 return (&mips_cpu_info_table[i]);
15498 show (FILE *stream, const char *string, int *col_p, int *first_p)
15502 fprintf (stream, "%24s", "");
15507 fprintf (stream, ", ");
15511 if (*col_p + strlen (string) > 72)
15513 fprintf (stream, "\n%24s", "");
15517 fprintf (stream, "%s", string);
15518 *col_p += strlen (string);
15524 md_show_usage (FILE *stream)
15529 fprintf (stream, _("\
15531 -EB generate big endian output\n\
15532 -EL generate little endian output\n\
15533 -g, -g2 do not remove unneeded NOPs or swap branches\n\
15534 -G NUM allow referencing objects up to NUM bytes\n\
15535 implicitly with the gp register [default 8]\n"));
15536 fprintf (stream, _("\
15537 -mips1 generate MIPS ISA I instructions\n\
15538 -mips2 generate MIPS ISA II instructions\n\
15539 -mips3 generate MIPS ISA III instructions\n\
15540 -mips4 generate MIPS ISA IV instructions\n\
15541 -mips5 generate MIPS ISA V instructions\n\
15542 -mips32 generate MIPS32 ISA instructions\n\
15543 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
15544 -mips64 generate MIPS64 ISA instructions\n\
15545 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
15546 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
15550 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15551 show (stream, mips_cpu_info_table[i].name, &column, &first);
15552 show (stream, "from-abi", &column, &first);
15553 fputc ('\n', stream);
15555 fprintf (stream, _("\
15556 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
15557 -no-mCPU don't generate code specific to CPU.\n\
15558 For -mCPU and -no-mCPU, CPU must be one of:\n"));
15562 show (stream, "3900", &column, &first);
15563 show (stream, "4010", &column, &first);
15564 show (stream, "4100", &column, &first);
15565 show (stream, "4650", &column, &first);
15566 fputc ('\n', stream);
15568 fprintf (stream, _("\
15569 -mips16 generate mips16 instructions\n\
15570 -no-mips16 do not generate mips16 instructions\n"));
15571 fprintf (stream, _("\
15572 -msmartmips generate smartmips instructions\n\
15573 -mno-smartmips do not generate smartmips instructions\n"));
15574 fprintf (stream, _("\
15575 -mdsp generate DSP instructions\n\
15576 -mno-dsp do not generate DSP instructions\n"));
15577 fprintf (stream, _("\
15578 -mdspr2 generate DSP R2 instructions\n\
15579 -mno-dspr2 do not generate DSP R2 instructions\n"));
15580 fprintf (stream, _("\
15581 -mmt generate MT instructions\n\
15582 -mno-mt do not generate MT instructions\n"));
15583 fprintf (stream, _("\
15584 -mfix-vr4120 work around certain VR4120 errata\n\
15585 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
15586 -mfix-24k insert a nop after ERET and DERET instructions\n\
15587 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
15588 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
15589 -msym32 assume all symbols have 32-bit values\n\
15590 -O0 remove unneeded NOPs, do not swap branches\n\
15591 -O remove unneeded NOPs and swap branches\n\
15592 --trap, --no-break trap exception on div by 0 and mult overflow\n\
15593 --break, --no-trap break exception on div by 0 and mult overflow\n"));
15594 fprintf (stream, _("\
15595 -mhard-float allow floating-point instructions\n\
15596 -msoft-float do not allow floating-point instructions\n\
15597 -msingle-float only allow 32-bit floating-point operations\n\
15598 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
15599 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
15602 fprintf (stream, _("\
15603 -KPIC, -call_shared generate SVR4 position independent code\n\
15604 -call_nonpic generate non-PIC code that can operate with DSOs\n\
15605 -mvxworks-pic generate VxWorks position independent code\n\
15606 -non_shared do not generate code that can operate with DSOs\n\
15607 -xgot assume a 32 bit GOT\n\
15608 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
15609 -mshared, -mno-shared disable/enable .cpload optimization for\n\
15610 position dependent (non shared) code\n\
15611 -mabi=ABI create ABI conformant object file for:\n"));
15615 show (stream, "32", &column, &first);
15616 show (stream, "o64", &column, &first);
15617 show (stream, "n32", &column, &first);
15618 show (stream, "64", &column, &first);
15619 show (stream, "eabi", &column, &first);
15621 fputc ('\n', stream);
15623 fprintf (stream, _("\
15624 -32 create o32 ABI object file (default)\n\
15625 -n32 create n32 ABI object file\n\
15626 -64 create 64 ABI object file\n"));
15631 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
15633 if (HAVE_64BIT_SYMBOLS)
15636 return dwarf2_format_64bit_irix;
15638 return dwarf2_format_64bit;
15642 return dwarf2_format_32bit;
15646 mips_dwarf2_addr_size (void)
15648 if (HAVE_64BIT_OBJECTS)
15654 /* Standard calling conventions leave the CFA at SP on entry. */
15656 mips_cfi_frame_initial_instructions (void)
15658 cfi_add_CFA_def_cfa_register (SP);
15662 tc_mips_regname_to_dw2regnum (char *regname)
15664 unsigned int regnum = -1;
15667 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))