1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
38 #include "opcode/mips.h"
40 #include "dwarf2dbg.h"
43 #define DBG(x) printf x
49 /* Clean up namespace so we can include obj-elf.h too. */
50 static int mips_output_flavor PARAMS ((void));
51 static int mips_output_flavor () { return OUTPUT_FLAVOR; }
52 #undef OBJ_PROCESS_STAB
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
80 int mips_flag_mdebug = -1;
84 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
85 static char *mips_regmask_frag;
91 #define PIC_CALL_REG 25
99 #define ILLEGAL_REG (32)
101 /* Allow override of standard little-endian ECOFF format. */
103 #ifndef ECOFF_LITTLE_FORMAT
104 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
107 extern int target_big_endian;
109 /* The name of the readonly data section. */
110 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
112 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
114 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
120 /* The ABI to use. */
131 /* MIPS ABI we are using for this output file. */
132 static enum mips_abi_level mips_abi = NO_ABI;
134 /* This is the set of options which may be modified by the .set
135 pseudo-op. We use a struct so that .set push and .set pop are more
138 struct mips_set_options
140 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
141 if it has not been initialized. Changed by `.set mipsN', and the
142 -mipsN command line option, and the default CPU. */
144 /* Enabled Application Specific Extensions (ASEs). These are set to -1
145 if they have not been initialized. Changed by `.set <asename>', by
146 command line options, and based on the default architecture. */
149 /* Whether we are assembling for the mips16 processor. 0 if we are
150 not, 1 if we are, and -1 if the value has not been initialized.
151 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
152 -nomips16 command line options, and the default CPU. */
154 /* Non-zero if we should not reorder instructions. Changed by `.set
155 reorder' and `.set noreorder'. */
157 /* Non-zero if we should not permit the $at ($1) register to be used
158 in instructions. Changed by `.set at' and `.set noat'. */
160 /* Non-zero if we should warn when a macro instruction expands into
161 more than one machine instruction. Changed by `.set nomacro' and
163 int warn_about_macros;
164 /* Non-zero if we should not move instructions. Changed by `.set
165 move', `.set volatile', `.set nomove', and `.set novolatile'. */
167 /* Non-zero if we should not optimize branches by moving the target
168 of the branch into the delay slot. Actually, we don't perform
169 this optimization anyhow. Changed by `.set bopt' and `.set
172 /* Non-zero if we should not autoextend mips16 instructions.
173 Changed by `.set autoextend' and `.set noautoextend'. */
175 /* Restrict general purpose registers and floating point registers
176 to 32 bit. This is initially determined when -mgp32 or -mfp32
177 is passed but can changed if the assembler code uses .set mipsN. */
182 /* True if -mgp32 was passed. */
183 static int file_mips_gp32 = -1;
185 /* True if -mfp32 was passed. */
186 static int file_mips_fp32 = -1;
188 /* This is the struct we use to hold the current set of options. Note
189 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
190 -1 to indicate that they have not been initialized. */
192 static struct mips_set_options mips_opts =
194 ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0
197 /* These variables are filled in with the masks of registers used.
198 The object format code reads them and puts them in the appropriate
200 unsigned long mips_gprmask;
201 unsigned long mips_cprmask[4];
203 /* MIPS ISA we are using for this output file. */
204 static int file_mips_isa = ISA_UNKNOWN;
206 /* True if -mips16 was passed or implied by arguments passed on the
207 command line (e.g., by -march). */
208 static int file_ase_mips16;
210 /* True if -mips3d was passed or implied by arguments passed on the
211 command line (e.g., by -march). */
212 static int file_ase_mips3d;
214 /* True if -mdmx was passed or implied by arguments passed on the
215 command line (e.g., by -march). */
216 static int file_ase_mdmx;
218 /* The argument of the -march= flag. The architecture we are assembling. */
219 static int mips_arch = CPU_UNKNOWN;
220 static const char *mips_arch_string;
221 static const struct mips_cpu_info *mips_arch_info;
223 /* The argument of the -mtune= flag. The architecture for which we
225 static int mips_tune = CPU_UNKNOWN;
226 static const char *mips_tune_string;
227 static const struct mips_cpu_info *mips_tune_info;
229 /* True when generating 32-bit code for a 64-bit processor. */
230 static int mips_32bitmode = 0;
232 /* Some ISA's have delay slots for instructions which read or write
233 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
234 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
235 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
236 delay slot in this ISA. The uses of this macro assume that any
237 ISA that has delay slots for one of these, has them for all. They
238 also assume that ISAs which don't have delays for these insns, don't
239 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
240 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
242 || (ISA) == ISA_MIPS2 \
243 || (ISA) == ISA_MIPS3 \
246 /* True if the given ABI requires 32-bit registers. */
247 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
249 /* Likewise 64-bit registers. */
250 #define ABI_NEEDS_64BIT_REGS(ABI) \
252 || (ABI) == N64_ABI \
255 /* Return true if ISA supports 64 bit gp register instructions. */
256 #define ISA_HAS_64BIT_REGS(ISA) ( \
258 || (ISA) == ISA_MIPS4 \
259 || (ISA) == ISA_MIPS5 \
260 || (ISA) == ISA_MIPS64 \
263 #define HAVE_32BIT_GPRS \
264 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
266 #define HAVE_32BIT_FPRS \
267 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
269 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
270 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
272 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
274 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
276 /* We can only have 64bit addresses if the object file format
278 #define HAVE_32BIT_ADDRESSES \
280 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
281 || ! HAVE_64BIT_OBJECTS) \
282 && mips_pic != EMBEDDED_PIC))
284 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
286 /* Return true if the given CPU supports the MIPS16 ASE. */
287 #define CPU_HAS_MIPS16(cpu) \
288 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0)
290 /* Return true if the given CPU supports the MIPS3D ASE. */
291 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
294 /* Return true if the given CPU supports the MDMX ASE. */
295 #define CPU_HAS_MDMX(cpu) (false \
298 /* Whether the processor uses hardware interlocks to protect
299 reads from the HI and LO registers, and thus does not
300 require nops to be inserted. */
302 #define hilo_interlocks (mips_arch == CPU_R4010 \
303 || mips_arch == CPU_SB1 \
306 /* Whether the processor uses hardware interlocks to protect reads
307 from the GPRs, and thus does not require nops to be inserted. */
308 #define gpr_interlocks \
309 (mips_opts.isa != ISA_MIPS1 \
310 || mips_arch == CPU_R3900)
312 /* As with other "interlocks" this is used by hardware that has FP
313 (co-processor) interlocks. */
314 /* Itbl support may require additional care here. */
315 #define cop_interlocks (mips_arch == CPU_R4300 \
316 || mips_arch == CPU_SB1 \
319 /* Is this a mfhi or mflo instruction? */
320 #define MF_HILO_INSN(PINFO) \
321 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
323 /* MIPS PIC level. */
325 enum mips_pic_level mips_pic;
327 /* Warn about all NOPS that the assembler generates. */
328 static int warn_nops = 0;
330 /* 1 if we should generate 32 bit offsets from the $gp register in
331 SVR4_PIC mode. Currently has no meaning in other modes. */
332 static int mips_big_got = 0;
334 /* 1 if trap instructions should used for overflow rather than break
336 static int mips_trap = 0;
338 /* 1 if double width floating point constants should not be constructed
339 by assembling two single width halves into two single width floating
340 point registers which just happen to alias the double width destination
341 register. On some architectures this aliasing can be disabled by a bit
342 in the status register, and the setting of this bit cannot be determined
343 automatically at assemble time. */
344 static int mips_disable_float_construction;
346 /* Non-zero if any .set noreorder directives were used. */
348 static int mips_any_noreorder;
350 /* Non-zero if nops should be inserted when the register referenced in
351 an mfhi/mflo instruction is read in the next two instructions. */
352 static int mips_7000_hilo_fix;
354 /* The size of the small data section. */
355 static unsigned int g_switch_value = 8;
356 /* Whether the -G option was used. */
357 static int g_switch_seen = 0;
362 /* If we can determine in advance that GP optimization won't be
363 possible, we can skip the relaxation stuff that tries to produce
364 GP-relative references. This makes delay slot optimization work
367 This function can only provide a guess, but it seems to work for
368 gcc output. It needs to guess right for gcc, otherwise gcc
369 will put what it thinks is a GP-relative instruction in a branch
372 I don't know if a fix is needed for the SVR4_PIC mode. I've only
373 fixed it for the non-PIC mode. KR 95/04/07 */
374 static int nopic_need_relax PARAMS ((symbolS *, int));
376 /* handle of the OPCODE hash table */
377 static struct hash_control *op_hash = NULL;
379 /* The opcode hash table we use for the mips16. */
380 static struct hash_control *mips16_op_hash = NULL;
382 /* This array holds the chars that always start a comment. If the
383 pre-processor is disabled, these aren't very useful */
384 const char comment_chars[] = "#";
386 /* This array holds the chars that only start a comment at the beginning of
387 a line. If the line seems to have the form '# 123 filename'
388 .line and .file directives will appear in the pre-processed output */
389 /* Note that input_file.c hand checks for '#' at the beginning of the
390 first line of the input file. This is because the compiler outputs
391 #NO_APP at the beginning of its output. */
392 /* Also note that C style comments are always supported. */
393 const char line_comment_chars[] = "#";
395 /* This array holds machine specific line separator characters. */
396 const char line_separator_chars[] = ";";
398 /* Chars that can be used to separate mant from exp in floating point nums */
399 const char EXP_CHARS[] = "eE";
401 /* Chars that mean this number is a floating point constant */
404 const char FLT_CHARS[] = "rRsSfFdDxXpP";
406 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
407 changed in read.c . Ideally it shouldn't have to know about it at all,
408 but nothing is ideal around here.
411 static char *insn_error;
413 static int auto_align = 1;
415 /* When outputting SVR4 PIC code, the assembler needs to know the
416 offset in the stack frame from which to restore the $gp register.
417 This is set by the .cprestore pseudo-op, and saved in this
419 static offsetT mips_cprestore_offset = -1;
421 /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some
422 more optimizations, it can use a register value instead of a memory-saved
423 offset and even an other register than $gp as global pointer. */
424 static offsetT mips_cpreturn_offset = -1;
425 static int mips_cpreturn_register = -1;
426 static int mips_gp_register = GP;
427 static int mips_gprel_offset = 0;
429 /* Whether mips_cprestore_offset has been set in the current function
430 (or whether it has already been warned about, if not). */
431 static int mips_cprestore_valid = 0;
433 /* This is the register which holds the stack frame, as set by the
434 .frame pseudo-op. This is needed to implement .cprestore. */
435 static int mips_frame_reg = SP;
437 /* Whether mips_frame_reg has been set in the current function
438 (or whether it has already been warned about, if not). */
439 static int mips_frame_reg_valid = 0;
441 /* To output NOP instructions correctly, we need to keep information
442 about the previous two instructions. */
444 /* Whether we are optimizing. The default value of 2 means to remove
445 unneeded NOPs and swap branch instructions when possible. A value
446 of 1 means to not swap branches. A value of 0 means to always
448 static int mips_optimize = 2;
450 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
451 equivalent to seeing no -g option at all. */
452 static int mips_debug = 0;
454 /* The previous instruction. */
455 static struct mips_cl_insn prev_insn;
457 /* The instruction before prev_insn. */
458 static struct mips_cl_insn prev_prev_insn;
460 /* If we don't want information for prev_insn or prev_prev_insn, we
461 point the insn_mo field at this dummy integer. */
462 static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 };
464 /* Non-zero if prev_insn is valid. */
465 static int prev_insn_valid;
467 /* The frag for the previous instruction. */
468 static struct frag *prev_insn_frag;
470 /* The offset into prev_insn_frag for the previous instruction. */
471 static long prev_insn_where;
473 /* The reloc type for the previous instruction, if any. */
474 static bfd_reloc_code_real_type prev_insn_reloc_type[3];
476 /* The reloc for the previous instruction, if any. */
477 static fixS *prev_insn_fixp[3];
479 /* Non-zero if the previous instruction was in a delay slot. */
480 static int prev_insn_is_delay_slot;
482 /* Non-zero if the previous instruction was in a .set noreorder. */
483 static int prev_insn_unreordered;
485 /* Non-zero if the previous instruction uses an extend opcode (if
487 static int prev_insn_extended;
489 /* Non-zero if the previous previous instruction was in a .set
491 static int prev_prev_insn_unreordered;
493 /* If this is set, it points to a frag holding nop instructions which
494 were inserted before the start of a noreorder section. If those
495 nops turn out to be unnecessary, the size of the frag can be
497 static fragS *prev_nop_frag;
499 /* The number of nop instructions we created in prev_nop_frag. */
500 static int prev_nop_frag_holds;
502 /* The number of nop instructions that we know we need in
504 static int prev_nop_frag_required;
506 /* The number of instructions we've seen since prev_nop_frag. */
507 static int prev_nop_frag_since;
509 /* For ECOFF and ELF, relocations against symbols are done in two
510 parts, with a HI relocation and a LO relocation. Each relocation
511 has only 16 bits of space to store an addend. This means that in
512 order for the linker to handle carries correctly, it must be able
513 to locate both the HI and the LO relocation. This means that the
514 relocations must appear in order in the relocation table.
516 In order to implement this, we keep track of each unmatched HI
517 relocation. We then sort them so that they immediately precede the
518 corresponding LO relocation. */
523 struct mips_hi_fixup *next;
526 /* The section this fixup is in. */
530 /* The list of unmatched HI relocs. */
532 static struct mips_hi_fixup *mips_hi_fixup_list;
534 /* Map normal MIPS register numbers to mips16 register numbers. */
536 #define X ILLEGAL_REG
537 static const int mips32_to_16_reg_map[] =
539 X, X, 2, 3, 4, 5, 6, 7,
540 X, X, X, X, X, X, X, X,
541 0, 1, X, X, X, X, X, X,
542 X, X, X, X, X, X, X, X
546 /* Map mips16 register numbers to normal MIPS register numbers. */
548 static const unsigned int mips16_to_32_reg_map[] =
550 16, 17, 2, 3, 4, 5, 6, 7
553 /* Since the MIPS does not have multiple forms of PC relative
554 instructions, we do not have to do relaxing as is done on other
555 platforms. However, we do have to handle GP relative addressing
556 correctly, which turns out to be a similar problem.
558 Every macro that refers to a symbol can occur in (at least) two
559 forms, one with GP relative addressing and one without. For
560 example, loading a global variable into a register generally uses
561 a macro instruction like this:
563 If i can be addressed off the GP register (this is true if it is in
564 the .sbss or .sdata section, or if it is known to be smaller than
565 the -G argument) this will generate the following instruction:
567 This instruction will use a GPREL reloc. If i can not be addressed
568 off the GP register, the following instruction sequence will be used:
571 In this case the first instruction will have a HI16 reloc, and the
572 second reloc will have a LO16 reloc. Both relocs will be against
575 The issue here is that we may not know whether i is GP addressable
576 until after we see the instruction that uses it. Therefore, we
577 want to be able to choose the final instruction sequence only at
578 the end of the assembly. This is similar to the way other
579 platforms choose the size of a PC relative instruction only at the
582 When generating position independent code we do not use GP
583 addressing in quite the same way, but the issue still arises as
584 external symbols and local symbols must be handled differently.
586 We handle these issues by actually generating both possible
587 instruction sequences. The longer one is put in a frag_var with
588 type rs_machine_dependent. We encode what to do with the frag in
589 the subtype field. We encode (1) the number of existing bytes to
590 replace, (2) the number of new bytes to use, (3) the offset from
591 the start of the existing bytes to the first reloc we must generate
592 (that is, the offset is applied from the start of the existing
593 bytes after they are replaced by the new bytes, if any), (4) the
594 offset from the start of the existing bytes to the second reloc,
595 (5) whether a third reloc is needed (the third reloc is always four
596 bytes after the second reloc), and (6) whether to warn if this
597 variant is used (this is sometimes needed if .set nomacro or .set
598 noat is in effect). All these numbers are reasonably small.
600 Generating two instruction sequences must be handled carefully to
601 ensure that delay slots are handled correctly. Fortunately, there
602 are a limited number of cases. When the second instruction
603 sequence is generated, append_insn is directed to maintain the
604 existing delay slot information, so it continues to apply to any
605 code after the second instruction sequence. This means that the
606 second instruction sequence must not impose any requirements not
607 required by the first instruction sequence.
609 These variant frags are then handled in functions called by the
610 machine independent code. md_estimate_size_before_relax returns
611 the final size of the frag. md_convert_frag sets up the final form
612 of the frag. tc_gen_reloc adjust the first reloc and adds a second
614 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
618 | (((reloc1) + 64) << 9) \
619 | (((reloc2) + 64) << 2) \
620 | ((reloc3) ? (1 << 1) : 0) \
622 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
623 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
624 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
625 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
626 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
627 #define RELAX_WARN(i) ((i) & 1)
629 /* For mips16 code, we use an entirely different form of relaxation.
630 mips16 supports two versions of most instructions which take
631 immediate values: a small one which takes some small value, and a
632 larger one which takes a 16 bit value. Since branches also follow
633 this pattern, relaxing these values is required.
635 We can assemble both mips16 and normal MIPS code in a single
636 object. Therefore, we need to support this type of relaxation at
637 the same time that we support the relaxation described above. We
638 use the high bit of the subtype field to distinguish these cases.
640 The information we store for this type of relaxation is the
641 argument code found in the opcode file for this relocation, whether
642 the user explicitly requested a small or extended form, and whether
643 the relocation is in a jump or jal delay slot. That tells us the
644 size of the value, and how it should be stored. We also store
645 whether the fragment is considered to be extended or not. We also
646 store whether this is known to be a branch to a different section,
647 whether we have tried to relax this frag yet, and whether we have
648 ever extended a PC relative fragment because of a shift count. */
649 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
652 | ((small) ? 0x100 : 0) \
653 | ((ext) ? 0x200 : 0) \
654 | ((dslot) ? 0x400 : 0) \
655 | ((jal_dslot) ? 0x800 : 0))
656 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
657 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
658 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
659 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
660 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
661 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
662 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
663 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
664 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
665 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
666 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
667 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
669 /* Prototypes for static functions. */
672 #define internalError() \
673 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
675 #define internalError() as_fatal (_("MIPS internal Error"));
678 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
680 static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip,
681 unsigned int reg, enum mips_regclass class));
682 static int reg_needs_delay PARAMS ((unsigned int));
683 static void mips16_mark_labels PARAMS ((void));
684 static void append_insn PARAMS ((char *place,
685 struct mips_cl_insn * ip,
687 bfd_reloc_code_real_type *r,
689 static void mips_no_prev_insn PARAMS ((int));
690 static void mips_emit_delays PARAMS ((boolean));
692 static void macro_build PARAMS ((char *place, int *counter, expressionS * ep,
693 const char *name, const char *fmt,
696 static void macro_build ();
698 static void mips16_macro_build PARAMS ((char *, int *, expressionS *,
699 const char *, const char *,
701 static void macro_build_jalr PARAMS ((int, expressionS *));
702 static void macro_build_lui PARAMS ((char *place, int *counter,
703 expressionS * ep, int regnum));
704 static void set_at PARAMS ((int *counter, int reg, int unsignedp));
705 static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip,
707 static void load_register PARAMS ((int *, int, expressionS *, int));
708 static void load_address PARAMS ((int *, int, expressionS *, int *));
709 static void move_register PARAMS ((int *, int, int));
710 static void macro PARAMS ((struct mips_cl_insn * ip));
711 static void mips16_macro PARAMS ((struct mips_cl_insn * ip));
712 #ifdef LOSING_COMPILER
713 static void macro2 PARAMS ((struct mips_cl_insn * ip));
715 static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip));
716 static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip));
717 static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean,
718 boolean, boolean, unsigned long *,
719 boolean *, unsigned short *));
720 static int my_getPercentOp PARAMS ((char **, unsigned int *, int *));
721 static int my_getSmallParser PARAMS ((char **, unsigned int *, int *));
722 static int my_getSmallExpression PARAMS ((expressionS *, char *));
723 static void my_getExpression PARAMS ((expressionS *, char *));
725 static int support_64bit_objects PARAMS((void));
727 static void mips_set_option_string PARAMS ((const char **, const char *));
728 static symbolS *get_symbol PARAMS ((void));
729 static void mips_align PARAMS ((int to, int fill, symbolS *label));
730 static void s_align PARAMS ((int));
731 static void s_change_sec PARAMS ((int));
732 static void s_change_section PARAMS ((int));
733 static void s_cons PARAMS ((int));
734 static void s_float_cons PARAMS ((int));
735 static void s_mips_globl PARAMS ((int));
736 static void s_option PARAMS ((int));
737 static void s_mipsset PARAMS ((int));
738 static void s_abicalls PARAMS ((int));
739 static void s_cpload PARAMS ((int));
740 static void s_cpsetup PARAMS ((int));
741 static void s_cplocal PARAMS ((int));
742 static void s_cprestore PARAMS ((int));
743 static void s_cpreturn PARAMS ((int));
744 static void s_gpvalue PARAMS ((int));
745 static void s_gpword PARAMS ((int));
746 static void s_cpadd PARAMS ((int));
747 static void s_insn PARAMS ((int));
748 static void md_obj_begin PARAMS ((void));
749 static void md_obj_end PARAMS ((void));
750 static long get_number PARAMS ((void));
751 static void s_mips_ent PARAMS ((int));
752 static void s_mips_end PARAMS ((int));
753 static void s_mips_frame PARAMS ((int));
754 static void s_mips_mask PARAMS ((int));
755 static void s_mips_stab PARAMS ((int));
756 static void s_mips_weakext PARAMS ((int));
757 static void s_mips_file PARAMS ((int));
758 static void s_mips_loc PARAMS ((int));
759 static int mips16_extended_frag PARAMS ((fragS *, asection *, long));
760 static int validate_mips_insn PARAMS ((const struct mips_opcode *));
761 static void show PARAMS ((FILE *, const char *, int *, int *));
763 static int mips_need_elf_addend_fixup PARAMS ((fixS *));
766 /* Return values of my_getSmallExpression(). */
773 /* Direct relocation creation by %percent_op(). */
792 /* Table and functions used to map between CPU/ISA names, and
793 ISA levels, and CPU numbers. */
797 const char *name; /* CPU or ISA name. */
798 int is_isa; /* Is this an ISA? (If 0, a CPU.) */
799 int isa; /* ISA level. */
800 int cpu; /* CPU number (default CPU if ISA). */
803 static void mips_set_architecture PARAMS ((const struct mips_cpu_info *));
804 static void mips_set_tune PARAMS ((const struct mips_cpu_info *));
805 static boolean mips_strict_matching_cpu_name_p PARAMS ((const char *,
807 static boolean mips_matching_cpu_name_p PARAMS ((const char *, const char *));
808 static const struct mips_cpu_info *mips_parse_cpu PARAMS ((const char *,
810 static const struct mips_cpu_info *mips_cpu_info_from_isa PARAMS ((int));
814 The following pseudo-ops from the Kane and Heinrich MIPS book
815 should be defined here, but are currently unsupported: .alias,
816 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
818 The following pseudo-ops from the Kane and Heinrich MIPS book are
819 specific to the type of debugging information being generated, and
820 should be defined by the object format: .aent, .begin, .bend,
821 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
824 The following pseudo-ops from the Kane and Heinrich MIPS book are
825 not MIPS CPU specific, but are also not specific to the object file
826 format. This file is probably the best place to define them, but
827 they are not currently supported: .asm0, .endr, .lab, .repeat,
830 static const pseudo_typeS mips_pseudo_table[] =
832 /* MIPS specific pseudo-ops. */
833 {"option", s_option, 0},
834 {"set", s_mipsset, 0},
835 {"rdata", s_change_sec, 'r'},
836 {"sdata", s_change_sec, 's'},
837 {"livereg", s_ignore, 0},
838 {"abicalls", s_abicalls, 0},
839 {"cpload", s_cpload, 0},
840 {"cpsetup", s_cpsetup, 0},
841 {"cplocal", s_cplocal, 0},
842 {"cprestore", s_cprestore, 0},
843 {"cpreturn", s_cpreturn, 0},
844 {"gpvalue", s_gpvalue, 0},
845 {"gpword", s_gpword, 0},
846 {"cpadd", s_cpadd, 0},
849 /* Relatively generic pseudo-ops that happen to be used on MIPS
851 {"asciiz", stringer, 1},
852 {"bss", s_change_sec, 'b'},
855 {"dword", s_cons, 3},
856 {"weakext", s_mips_weakext, 0},
858 /* These pseudo-ops are defined in read.c, but must be overridden
859 here for one reason or another. */
860 {"align", s_align, 0},
862 {"data", s_change_sec, 'd'},
863 {"double", s_float_cons, 'd'},
864 {"float", s_float_cons, 'f'},
865 {"globl", s_mips_globl, 0},
866 {"global", s_mips_globl, 0},
867 {"hword", s_cons, 1},
872 {"section", s_change_section, 0},
873 {"short", s_cons, 1},
874 {"single", s_float_cons, 'f'},
875 {"stabn", s_mips_stab, 'n'},
876 {"text", s_change_sec, 't'},
879 { "extern", ecoff_directive_extern, 0},
884 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
886 /* These pseudo-ops should be defined by the object file format.
887 However, a.out doesn't support them, so we have versions here. */
888 {"aent", s_mips_ent, 1},
889 {"bgnb", s_ignore, 0},
890 {"end", s_mips_end, 0},
891 {"endb", s_ignore, 0},
892 {"ent", s_mips_ent, 0},
893 {"file", s_mips_file, 0},
894 {"fmask", s_mips_mask, 'F'},
895 {"frame", s_mips_frame, 0},
896 {"loc", s_mips_loc, 0},
897 {"mask", s_mips_mask, 'R'},
898 {"verstamp", s_ignore, 0},
902 extern void pop_insert PARAMS ((const pseudo_typeS *));
907 pop_insert (mips_pseudo_table);
908 if (! ECOFF_DEBUGGING)
909 pop_insert (mips_nonecoff_pseudo_table);
912 /* Symbols labelling the current insn. */
914 struct insn_label_list
916 struct insn_label_list *next;
920 static struct insn_label_list *insn_labels;
921 static struct insn_label_list *free_insn_labels;
923 static void mips_clear_insn_labels PARAMS ((void));
926 mips_clear_insn_labels ()
928 register struct insn_label_list **pl;
930 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
936 static char *expr_end;
938 /* Expressions which appear in instructions. These are set by
941 static expressionS imm_expr;
942 static expressionS offset_expr;
944 /* Relocs associated with imm_expr and offset_expr. */
946 static bfd_reloc_code_real_type imm_reloc[3]
947 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
948 static bfd_reloc_code_real_type offset_reloc[3]
949 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
951 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
953 static boolean imm_unmatched_hi;
955 /* These are set by mips16_ip if an explicit extension is used. */
957 static boolean mips16_small, mips16_ext;
960 /* The pdr segment for per procedure frame/regmask info. Not used for
966 /* The default target format to use. */
969 mips_target_format ()
971 switch (OUTPUT_FLAVOR)
973 case bfd_target_aout_flavour:
974 return target_big_endian ? "a.out-mips-big" : "a.out-mips-little";
975 case bfd_target_ecoff_flavour:
976 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
977 case bfd_target_coff_flavour:
979 case bfd_target_elf_flavour:
981 /* This is traditional mips. */
982 return (target_big_endian
983 ? (HAVE_64BIT_OBJECTS
984 ? "elf64-tradbigmips"
986 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
987 : (HAVE_64BIT_OBJECTS
988 ? "elf64-tradlittlemips"
990 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
992 return (target_big_endian
993 ? (HAVE_64BIT_OBJECTS
996 ? "elf32-nbigmips" : "elf32-bigmips"))
997 : (HAVE_64BIT_OBJECTS
1000 ? "elf32-nlittlemips" : "elf32-littlemips")));
1008 /* This function is called once, at assembler startup time. It should
1009 set up all the tables, etc. that the MD part of the assembler will need. */
1014 register const char *retval = NULL;
1018 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_arch))
1019 as_warn (_("Could not set architecture and machine"));
1021 op_hash = hash_new ();
1023 for (i = 0; i < NUMOPCODES;)
1025 const char *name = mips_opcodes[i].name;
1027 retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]);
1030 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1031 mips_opcodes[i].name, retval);
1032 /* Probably a memory allocation problem? Give up now. */
1033 as_fatal (_("Broken assembler. No assembly attempted."));
1037 if (mips_opcodes[i].pinfo != INSN_MACRO)
1039 if (!validate_mips_insn (&mips_opcodes[i]))
1044 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1047 mips16_op_hash = hash_new ();
1050 while (i < bfd_mips16_num_opcodes)
1052 const char *name = mips16_opcodes[i].name;
1054 retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]);
1056 as_fatal (_("internal: can't hash `%s': %s"),
1057 mips16_opcodes[i].name, retval);
1060 if (mips16_opcodes[i].pinfo != INSN_MACRO
1061 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1062 != mips16_opcodes[i].match))
1064 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1065 mips16_opcodes[i].name, mips16_opcodes[i].args);
1070 while (i < bfd_mips16_num_opcodes
1071 && strcmp (mips16_opcodes[i].name, name) == 0);
1075 as_fatal (_("Broken assembler. No assembly attempted."));
1077 /* We add all the general register names to the symbol table. This
1078 helps us detect invalid uses of them. */
1079 for (i = 0; i < 32; i++)
1083 sprintf (buf, "$%d", i);
1084 symbol_table_insert (symbol_new (buf, reg_section, i,
1085 &zero_address_frag));
1087 symbol_table_insert (symbol_new ("$ra", reg_section, RA,
1088 &zero_address_frag));
1089 symbol_table_insert (symbol_new ("$fp", reg_section, FP,
1090 &zero_address_frag));
1091 symbol_table_insert (symbol_new ("$sp", reg_section, SP,
1092 &zero_address_frag));
1093 symbol_table_insert (symbol_new ("$gp", reg_section, GP,
1094 &zero_address_frag));
1095 symbol_table_insert (symbol_new ("$at", reg_section, AT,
1096 &zero_address_frag));
1097 symbol_table_insert (symbol_new ("$kt0", reg_section, KT0,
1098 &zero_address_frag));
1099 symbol_table_insert (symbol_new ("$kt1", reg_section, KT1,
1100 &zero_address_frag));
1101 symbol_table_insert (symbol_new ("$zero", reg_section, ZERO,
1102 &zero_address_frag));
1103 symbol_table_insert (symbol_new ("$pc", reg_section, -1,
1104 &zero_address_frag));
1106 mips_no_prev_insn (false);
1109 mips_cprmask[0] = 0;
1110 mips_cprmask[1] = 0;
1111 mips_cprmask[2] = 0;
1112 mips_cprmask[3] = 0;
1114 /* set the default alignment for the text section (2**2) */
1115 record_alignment (text_section, 2);
1117 if (USE_GLOBAL_POINTER_OPT)
1118 bfd_set_gp_size (stdoutput, g_switch_value);
1120 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1122 /* On a native system, sections must be aligned to 16 byte
1123 boundaries. When configured for an embedded ELF target, we
1125 if (strcmp (TARGET_OS, "elf") != 0)
1127 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
1128 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
1129 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
1132 /* Create a .reginfo section for register masks and a .mdebug
1133 section for debugging information. */
1141 subseg = now_subseg;
1143 /* The ABI says this section should be loaded so that the
1144 running program can access it. However, we don't load it
1145 if we are configured for an embedded target */
1146 flags = SEC_READONLY | SEC_DATA;
1147 if (strcmp (TARGET_OS, "elf") != 0)
1148 flags |= SEC_ALLOC | SEC_LOAD;
1150 if (mips_abi != N64_ABI)
1152 sec = subseg_new (".reginfo", (subsegT) 0);
1154 bfd_set_section_flags (stdoutput, sec, flags);
1155 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
1158 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
1163 /* The 64-bit ABI uses a .MIPS.options section rather than
1164 .reginfo section. */
1165 sec = subseg_new (".MIPS.options", (subsegT) 0);
1166 bfd_set_section_flags (stdoutput, sec, flags);
1167 bfd_set_section_alignment (stdoutput, sec, 3);
1170 /* Set up the option header. */
1172 Elf_Internal_Options opthdr;
1175 opthdr.kind = ODK_REGINFO;
1176 opthdr.size = (sizeof (Elf_External_Options)
1177 + sizeof (Elf64_External_RegInfo));
1180 f = frag_more (sizeof (Elf_External_Options));
1181 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
1182 (Elf_External_Options *) f);
1184 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
1189 if (ECOFF_DEBUGGING)
1191 sec = subseg_new (".mdebug", (subsegT) 0);
1192 (void) bfd_set_section_flags (stdoutput, sec,
1193 SEC_HAS_CONTENTS | SEC_READONLY);
1194 (void) bfd_set_section_alignment (stdoutput, sec, 2);
1197 else if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1199 pdr_seg = subseg_new (".pdr", (subsegT) 0);
1200 (void) bfd_set_section_flags (stdoutput, pdr_seg,
1201 SEC_READONLY | SEC_RELOC
1203 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
1207 subseg_set (seg, subseg);
1211 if (! ECOFF_DEBUGGING)
1218 if (! ECOFF_DEBUGGING)
1226 struct mips_cl_insn insn;
1227 bfd_reloc_code_real_type unused_reloc[3]
1228 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1230 imm_expr.X_op = O_absent;
1231 imm_unmatched_hi = false;
1232 offset_expr.X_op = O_absent;
1233 imm_reloc[0] = BFD_RELOC_UNUSED;
1234 imm_reloc[1] = BFD_RELOC_UNUSED;
1235 imm_reloc[2] = BFD_RELOC_UNUSED;
1236 offset_reloc[0] = BFD_RELOC_UNUSED;
1237 offset_reloc[1] = BFD_RELOC_UNUSED;
1238 offset_reloc[2] = BFD_RELOC_UNUSED;
1240 if (mips_opts.mips16)
1241 mips16_ip (str, &insn);
1244 mips_ip (str, &insn);
1245 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1246 str, insn.insn_opcode));
1251 as_bad ("%s `%s'", insn_error, str);
1255 if (insn.insn_mo->pinfo == INSN_MACRO)
1257 if (mips_opts.mips16)
1258 mips16_macro (&insn);
1264 if (imm_expr.X_op != O_absent)
1265 append_insn (NULL, &insn, &imm_expr, imm_reloc, imm_unmatched_hi);
1266 else if (offset_expr.X_op != O_absent)
1267 append_insn (NULL, &insn, &offset_expr, offset_reloc, false);
1269 append_insn (NULL, &insn, NULL, unused_reloc, false);
1273 /* See whether instruction IP reads register REG. CLASS is the type
1277 insn_uses_reg (ip, reg, class)
1278 struct mips_cl_insn *ip;
1280 enum mips_regclass class;
1282 if (class == MIPS16_REG)
1284 assert (mips_opts.mips16);
1285 reg = mips16_to_32_reg_map[reg];
1286 class = MIPS_GR_REG;
1289 /* Don't report on general register ZERO, since it never changes. */
1290 if (class == MIPS_GR_REG && reg == ZERO)
1293 if (class == MIPS_FP_REG)
1295 assert (! mips_opts.mips16);
1296 /* If we are called with either $f0 or $f1, we must check $f0.
1297 This is not optimal, because it will introduce an unnecessary
1298 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1299 need to distinguish reading both $f0 and $f1 or just one of
1300 them. Note that we don't have to check the other way,
1301 because there is no instruction that sets both $f0 and $f1
1302 and requires a delay. */
1303 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
1304 && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1)
1305 == (reg &~ (unsigned) 1)))
1307 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
1308 && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1)
1309 == (reg &~ (unsigned) 1)))
1312 else if (! mips_opts.mips16)
1314 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
1315 && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg)
1317 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
1318 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg)
1323 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
1324 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX)
1325 & MIPS16OP_MASK_RX)]
1328 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
1329 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY)
1330 & MIPS16OP_MASK_RY)]
1333 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
1334 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
1335 & MIPS16OP_MASK_MOVE32Z)]
1338 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
1340 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
1342 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
1344 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
1345 && ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
1346 & MIPS16OP_MASK_REGR32) == reg)
1353 /* This function returns true if modifying a register requires a
1357 reg_needs_delay (reg)
1360 unsigned long prev_pinfo;
1362 prev_pinfo = prev_insn.insn_mo->pinfo;
1363 if (! mips_opts.noreorder
1364 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1365 && ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1366 || (! gpr_interlocks
1367 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
1369 /* A load from a coprocessor or from memory. All load
1370 delays delay the use of general register rt for one
1371 instruction on the r3000. The r6000 and r4000 use
1373 /* Itbl support may require additional care here. */
1374 know (prev_pinfo & INSN_WRITE_GPR_T);
1375 if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT))
1382 /* Mark instruction labels in mips16 mode. This permits the linker to
1383 handle them specially, such as generating jalx instructions when
1384 needed. We also make them odd for the duration of the assembly, in
1385 order to generate the right sort of code. We will make them even
1386 in the adjust_symtab routine, while leaving them marked. This is
1387 convenient for the debugger and the disassembler. The linker knows
1388 to make them odd again. */
1391 mips16_mark_labels ()
1393 if (mips_opts.mips16)
1395 struct insn_label_list *l;
1398 for (l = insn_labels; l != NULL; l = l->next)
1401 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1402 S_SET_OTHER (l->label, STO_MIPS16);
1404 val = S_GET_VALUE (l->label);
1406 S_SET_VALUE (l->label, val + 1);
1411 /* Output an instruction. PLACE is where to put the instruction; if
1412 it is NULL, this uses frag_more to get room. IP is the instruction
1413 information. ADDRESS_EXPR is an operand of the instruction to be
1414 used with RELOC_TYPE. */
1417 append_insn (place, ip, address_expr, reloc_type, unmatched_hi)
1419 struct mips_cl_insn *ip;
1420 expressionS *address_expr;
1421 bfd_reloc_code_real_type *reloc_type;
1422 boolean unmatched_hi;
1424 register unsigned long prev_pinfo, pinfo;
1429 /* Mark instruction labels in mips16 mode. */
1430 mips16_mark_labels ();
1432 prev_pinfo = prev_insn.insn_mo->pinfo;
1433 pinfo = ip->insn_mo->pinfo;
1435 if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL))
1439 /* If the previous insn required any delay slots, see if we need
1440 to insert a NOP or two. There are eight kinds of possible
1441 hazards, of which an instruction can have at most one type.
1442 (1) a load from memory delay
1443 (2) a load from a coprocessor delay
1444 (3) an unconditional branch delay
1445 (4) a conditional branch delay
1446 (5) a move to coprocessor register delay
1447 (6) a load coprocessor register from memory delay
1448 (7) a coprocessor condition code delay
1449 (8) a HI/LO special register delay
1451 There are a lot of optimizations we could do that we don't.
1452 In particular, we do not, in general, reorder instructions.
1453 If you use gcc with optimization, it will reorder
1454 instructions and generally do much more optimization then we
1455 do here; repeating all that work in the assembler would only
1456 benefit hand written assembly code, and does not seem worth
1459 /* This is how a NOP is emitted. */
1460 #define emit_nop() \
1462 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1463 : md_number_to_chars (frag_more (4), 0, 4))
1465 /* The previous insn might require a delay slot, depending upon
1466 the contents of the current insn. */
1467 if (! mips_opts.mips16
1468 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1469 && (((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1470 && ! cop_interlocks)
1471 || (! gpr_interlocks
1472 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
1474 /* A load from a coprocessor or from memory. All load
1475 delays delay the use of general register rt for one
1476 instruction on the r3000. The r6000 and r4000 use
1478 /* Itbl support may require additional care here. */
1479 know (prev_pinfo & INSN_WRITE_GPR_T);
1480 if (mips_optimize == 0
1481 || insn_uses_reg (ip,
1482 ((prev_insn.insn_opcode >> OP_SH_RT)
1487 else if (! mips_opts.mips16
1488 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1489 && (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
1490 && ! cop_interlocks)
1491 || (mips_opts.isa == ISA_MIPS1
1492 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))))
1494 /* A generic coprocessor delay. The previous instruction
1495 modified a coprocessor general or control register. If
1496 it modified a control register, we need to avoid any
1497 coprocessor instruction (this is probably not always
1498 required, but it sometimes is). If it modified a general
1499 register, we avoid using that register.
1501 On the r6000 and r4000 loading a coprocessor register
1502 from memory is interlocked, and does not require a delay.
1504 This case is not handled very well. There is no special
1505 knowledge of CP0 handling, and the coprocessors other
1506 than the floating point unit are not distinguished at
1508 /* Itbl support may require additional care here. FIXME!
1509 Need to modify this to include knowledge about
1510 user specified delays! */
1511 if (prev_pinfo & INSN_WRITE_FPR_T)
1513 if (mips_optimize == 0
1514 || insn_uses_reg (ip,
1515 ((prev_insn.insn_opcode >> OP_SH_FT)
1520 else if (prev_pinfo & INSN_WRITE_FPR_S)
1522 if (mips_optimize == 0
1523 || insn_uses_reg (ip,
1524 ((prev_insn.insn_opcode >> OP_SH_FS)
1531 /* We don't know exactly what the previous instruction
1532 does. If the current instruction uses a coprocessor
1533 register, we must insert a NOP. If previous
1534 instruction may set the condition codes, and the
1535 current instruction uses them, we must insert two
1537 /* Itbl support may require additional care here. */
1538 if (mips_optimize == 0
1539 || ((prev_pinfo & INSN_WRITE_COND_CODE)
1540 && (pinfo & INSN_READ_COND_CODE)))
1542 else if (pinfo & INSN_COP)
1546 else if (! mips_opts.mips16
1547 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1548 && (prev_pinfo & INSN_WRITE_COND_CODE)
1549 && ! cop_interlocks)
1551 /* The previous instruction sets the coprocessor condition
1552 codes, but does not require a general coprocessor delay
1553 (this means it is a floating point comparison
1554 instruction). If this instruction uses the condition
1555 codes, we need to insert a single NOP. */
1556 /* Itbl support may require additional care here. */
1557 if (mips_optimize == 0
1558 || (pinfo & INSN_READ_COND_CODE))
1562 /* If we're fixing up mfhi/mflo for the r7000 and the
1563 previous insn was an mfhi/mflo and the current insn
1564 reads the register that the mfhi/mflo wrote to, then
1567 else if (mips_7000_hilo_fix
1568 && MF_HILO_INSN (prev_pinfo)
1569 && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD)
1576 /* If we're fixing up mfhi/mflo for the r7000 and the
1577 2nd previous insn was an mfhi/mflo and the current insn
1578 reads the register that the mfhi/mflo wrote to, then
1581 else if (mips_7000_hilo_fix
1582 && MF_HILO_INSN (prev_prev_insn.insn_opcode)
1583 && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD)
1591 else if (prev_pinfo & INSN_READ_LO)
1593 /* The previous instruction reads the LO register; if the
1594 current instruction writes to the LO register, we must
1595 insert two NOPS. Some newer processors have interlocks.
1596 Also the tx39's multiply instructions can be exectuted
1597 immediatly after a read from HI/LO (without the delay),
1598 though the tx39's divide insns still do require the
1600 if (! (hilo_interlocks
1601 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
1602 && (mips_optimize == 0
1603 || (pinfo & INSN_WRITE_LO)))
1605 /* Most mips16 branch insns don't have a delay slot.
1606 If a read from LO is immediately followed by a branch
1607 to a write to LO we have a read followed by a write
1608 less than 2 insns away. We assume the target of
1609 a branch might be a write to LO, and insert a nop
1610 between a read and an immediately following branch. */
1611 else if (mips_opts.mips16
1612 && (mips_optimize == 0
1613 || (pinfo & MIPS16_INSN_BRANCH)))
1616 else if (prev_insn.insn_mo->pinfo & INSN_READ_HI)
1618 /* The previous instruction reads the HI register; if the
1619 current instruction writes to the HI register, we must
1620 insert a NOP. Some newer processors have interlocks.
1621 Also the note tx39's multiply above. */
1622 if (! (hilo_interlocks
1623 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
1624 && (mips_optimize == 0
1625 || (pinfo & INSN_WRITE_HI)))
1627 /* Most mips16 branch insns don't have a delay slot.
1628 If a read from HI is immediately followed by a branch
1629 to a write to HI we have a read followed by a write
1630 less than 2 insns away. We assume the target of
1631 a branch might be a write to HI, and insert a nop
1632 between a read and an immediately following branch. */
1633 else if (mips_opts.mips16
1634 && (mips_optimize == 0
1635 || (pinfo & MIPS16_INSN_BRANCH)))
1639 /* If the previous instruction was in a noreorder section, then
1640 we don't want to insert the nop after all. */
1641 /* Itbl support may require additional care here. */
1642 if (prev_insn_unreordered)
1645 /* There are two cases which require two intervening
1646 instructions: 1) setting the condition codes using a move to
1647 coprocessor instruction which requires a general coprocessor
1648 delay and then reading the condition codes 2) reading the HI
1649 or LO register and then writing to it (except on processors
1650 which have interlocks). If we are not already emitting a NOP
1651 instruction, we must check for these cases compared to the
1652 instruction previous to the previous instruction. */
1653 if ((! mips_opts.mips16
1654 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1655 && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
1656 && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
1657 && (pinfo & INSN_READ_COND_CODE)
1658 && ! cop_interlocks)
1659 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
1660 && (pinfo & INSN_WRITE_LO)
1661 && ! (hilo_interlocks
1662 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))))
1663 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
1664 && (pinfo & INSN_WRITE_HI)
1665 && ! (hilo_interlocks
1666 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))))
1671 if (prev_prev_insn_unreordered)
1674 if (prev_prev_nop && nops == 0)
1677 /* If we are being given a nop instruction, don't bother with
1678 one of the nops we would otherwise output. This will only
1679 happen when a nop instruction is used with mips_optimize set
1682 && ! mips_opts.noreorder
1683 && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0))
1686 /* Now emit the right number of NOP instructions. */
1687 if (nops > 0 && ! mips_opts.noreorder)
1690 unsigned long old_frag_offset;
1692 struct insn_label_list *l;
1694 old_frag = frag_now;
1695 old_frag_offset = frag_now_fix ();
1697 for (i = 0; i < nops; i++)
1702 listing_prev_line ();
1703 /* We may be at the start of a variant frag. In case we
1704 are, make sure there is enough space for the frag
1705 after the frags created by listing_prev_line. The
1706 argument to frag_grow here must be at least as large
1707 as the argument to all other calls to frag_grow in
1708 this file. We don't have to worry about being in the
1709 middle of a variant frag, because the variants insert
1710 all needed nop instructions themselves. */
1714 for (l = insn_labels; l != NULL; l = l->next)
1718 assert (S_GET_SEGMENT (l->label) == now_seg);
1719 symbol_set_frag (l->label, frag_now);
1720 val = (valueT) frag_now_fix ();
1721 /* mips16 text labels are stored as odd. */
1722 if (mips_opts.mips16)
1724 S_SET_VALUE (l->label, val);
1727 #ifndef NO_ECOFF_DEBUGGING
1728 if (ECOFF_DEBUGGING)
1729 ecoff_fix_loc (old_frag, old_frag_offset);
1732 else if (prev_nop_frag != NULL)
1734 /* We have a frag holding nops we may be able to remove. If
1735 we don't need any nops, we can decrease the size of
1736 prev_nop_frag by the size of one instruction. If we do
1737 need some nops, we count them in prev_nops_required. */
1738 if (prev_nop_frag_since == 0)
1742 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1743 --prev_nop_frag_holds;
1746 prev_nop_frag_required += nops;
1750 if (prev_prev_nop == 0)
1752 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1753 --prev_nop_frag_holds;
1756 ++prev_nop_frag_required;
1759 if (prev_nop_frag_holds <= prev_nop_frag_required)
1760 prev_nop_frag = NULL;
1762 ++prev_nop_frag_since;
1764 /* Sanity check: by the time we reach the second instruction
1765 after prev_nop_frag, we should have used up all the nops
1766 one way or another. */
1767 assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL);
1771 if (*reloc_type > BFD_RELOC_UNUSED)
1773 /* We need to set up a variant frag. */
1774 assert (mips_opts.mips16 && address_expr != NULL);
1775 f = frag_var (rs_machine_dependent, 4, 0,
1776 RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED,
1777 mips16_small, mips16_ext,
1779 & INSN_UNCOND_BRANCH_DELAY),
1780 (*prev_insn_reloc_type
1781 == BFD_RELOC_MIPS16_JMP)),
1782 make_expr_symbol (address_expr), 0, NULL);
1784 else if (place != NULL)
1786 else if (mips_opts.mips16
1788 && *reloc_type != BFD_RELOC_MIPS16_JMP)
1790 /* Make sure there is enough room to swap this instruction with
1791 a following jump instruction. */
1797 if (mips_opts.mips16
1798 && mips_opts.noreorder
1799 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1800 as_warn (_("extended instruction in delay slot"));
1805 fixp[0] = fixp[1] = fixp[2] = NULL;
1806 if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED)
1808 if (address_expr->X_op == O_constant)
1812 switch (*reloc_type)
1815 ip->insn_opcode |= address_expr->X_add_number;
1818 case BFD_RELOC_MIPS_HIGHEST:
1819 tmp = (address_expr->X_add_number + 0x800080008000) >> 16;
1821 ip->insn_opcode |= (tmp >> 16) & 0xffff;
1824 case BFD_RELOC_MIPS_HIGHER:
1825 tmp = (address_expr->X_add_number + 0x80008000) >> 16;
1826 ip->insn_opcode |= (tmp >> 16) & 0xffff;
1829 case BFD_RELOC_HI16_S:
1830 ip->insn_opcode |= ((address_expr->X_add_number + 0x8000)
1834 case BFD_RELOC_HI16:
1835 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
1838 case BFD_RELOC_LO16:
1839 case BFD_RELOC_MIPS_GOT_DISP:
1840 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
1843 case BFD_RELOC_MIPS_JMP:
1844 if ((address_expr->X_add_number & 3) != 0)
1845 as_bad (_("jump to misaligned address (0x%lx)"),
1846 (unsigned long) address_expr->X_add_number);
1847 if (address_expr->X_add_number & ~0xfffffff
1848 || address_expr->X_add_number > 0x7fffffc)
1849 as_bad (_("jump address range overflow (0x%lx)"),
1850 (unsigned long) address_expr->X_add_number);
1851 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
1854 case BFD_RELOC_MIPS16_JMP:
1855 if ((address_expr->X_add_number & 3) != 0)
1856 as_bad (_("jump to misaligned address (0x%lx)"),
1857 (unsigned long) address_expr->X_add_number);
1858 if (address_expr->X_add_number & ~0xfffffff
1859 || address_expr->X_add_number > 0x7fffffc)
1860 as_bad (_("jump address range overflow (0x%lx)"),
1861 (unsigned long) address_expr->X_add_number);
1863 (((address_expr->X_add_number & 0x7c0000) << 3)
1864 | ((address_expr->X_add_number & 0xf800000) >> 7)
1865 | ((address_expr->X_add_number & 0x3fffc) >> 2));
1868 case BFD_RELOC_16_PCREL:
1869 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
1872 case BFD_RELOC_16_PCREL_S2:
1882 /* Don't generate a reloc if we are writing into a variant frag. */
1885 fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal, 4,
1887 (*reloc_type == BFD_RELOC_16_PCREL
1888 || *reloc_type == BFD_RELOC_16_PCREL_S2),
1891 /* These relocations can have an addend that won't fit in
1892 4 octets for 64bit assembly. */
1893 if (HAVE_64BIT_GPRS &&
1894 (*reloc_type == BFD_RELOC_16
1895 || *reloc_type == BFD_RELOC_32
1896 || *reloc_type == BFD_RELOC_MIPS_JMP
1897 || *reloc_type == BFD_RELOC_HI16_S
1898 || *reloc_type == BFD_RELOC_LO16
1899 || *reloc_type == BFD_RELOC_GPREL16
1900 || *reloc_type == BFD_RELOC_MIPS_LITERAL
1901 || *reloc_type == BFD_RELOC_GPREL32
1902 || *reloc_type == BFD_RELOC_64
1903 || *reloc_type == BFD_RELOC_CTOR
1904 || *reloc_type == BFD_RELOC_MIPS_SUB
1905 || *reloc_type == BFD_RELOC_MIPS_HIGHEST
1906 || *reloc_type == BFD_RELOC_MIPS_HIGHER
1907 || *reloc_type == BFD_RELOC_MIPS_SCN_DISP
1908 || *reloc_type == BFD_RELOC_MIPS_REL16
1909 || *reloc_type == BFD_RELOC_MIPS_RELGOT))
1910 fixp[0]->fx_no_overflow = 1;
1914 struct mips_hi_fixup *hi_fixup;
1916 assert (*reloc_type == BFD_RELOC_HI16_S);
1917 hi_fixup = ((struct mips_hi_fixup *)
1918 xmalloc (sizeof (struct mips_hi_fixup)));
1919 hi_fixup->fixp = fixp[0];
1920 hi_fixup->seg = now_seg;
1921 hi_fixup->next = mips_hi_fixup_list;
1922 mips_hi_fixup_list = hi_fixup;
1925 if (reloc_type[1] != BFD_RELOC_UNUSED)
1927 /* FIXME: This symbol can be one of
1928 RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */
1929 address_expr->X_op = O_absent;
1930 address_expr->X_add_symbol = 0;
1931 address_expr->X_add_number = 0;
1933 fixp[1] = fix_new_exp (frag_now, f - frag_now->fr_literal,
1934 4, address_expr, false,
1937 /* These relocations can have an addend that won't fit in
1938 4 octets for 64bit assembly. */
1939 if (HAVE_64BIT_GPRS &&
1940 (*reloc_type == BFD_RELOC_16
1941 || *reloc_type == BFD_RELOC_32
1942 || *reloc_type == BFD_RELOC_MIPS_JMP
1943 || *reloc_type == BFD_RELOC_HI16_S
1944 || *reloc_type == BFD_RELOC_LO16
1945 || *reloc_type == BFD_RELOC_GPREL16
1946 || *reloc_type == BFD_RELOC_MIPS_LITERAL
1947 || *reloc_type == BFD_RELOC_GPREL32
1948 || *reloc_type == BFD_RELOC_64
1949 || *reloc_type == BFD_RELOC_CTOR
1950 || *reloc_type == BFD_RELOC_MIPS_SUB
1951 || *reloc_type == BFD_RELOC_MIPS_HIGHEST
1952 || *reloc_type == BFD_RELOC_MIPS_HIGHER
1953 || *reloc_type == BFD_RELOC_MIPS_SCN_DISP
1954 || *reloc_type == BFD_RELOC_MIPS_REL16
1955 || *reloc_type == BFD_RELOC_MIPS_RELGOT))
1956 fixp[1]->fx_no_overflow = 1;
1958 if (reloc_type[2] != BFD_RELOC_UNUSED)
1960 address_expr->X_op = O_absent;
1961 address_expr->X_add_symbol = 0;
1962 address_expr->X_add_number = 0;
1964 fixp[2] = fix_new_exp (frag_now,
1965 f - frag_now->fr_literal, 4,
1966 address_expr, false,
1969 /* These relocations can have an addend that won't fit in
1970 4 octets for 64bit assembly. */
1971 if (HAVE_64BIT_GPRS &&
1972 (*reloc_type == BFD_RELOC_16
1973 || *reloc_type == BFD_RELOC_32
1974 || *reloc_type == BFD_RELOC_MIPS_JMP
1975 || *reloc_type == BFD_RELOC_HI16_S
1976 || *reloc_type == BFD_RELOC_LO16
1977 || *reloc_type == BFD_RELOC_GPREL16
1978 || *reloc_type == BFD_RELOC_MIPS_LITERAL
1979 || *reloc_type == BFD_RELOC_GPREL32
1980 || *reloc_type == BFD_RELOC_64
1981 || *reloc_type == BFD_RELOC_CTOR
1982 || *reloc_type == BFD_RELOC_MIPS_SUB
1983 || *reloc_type == BFD_RELOC_MIPS_HIGHEST
1984 || *reloc_type == BFD_RELOC_MIPS_HIGHER
1985 || *reloc_type == BFD_RELOC_MIPS_SCN_DISP
1986 || *reloc_type == BFD_RELOC_MIPS_REL16
1987 || *reloc_type == BFD_RELOC_MIPS_RELGOT))
1988 fixp[2]->fx_no_overflow = 1;
1995 if (! mips_opts.mips16)
1997 md_number_to_chars (f, ip->insn_opcode, 4);
1999 dwarf2_emit_insn (4);
2002 else if (*reloc_type == BFD_RELOC_MIPS16_JMP)
2004 md_number_to_chars (f, ip->insn_opcode >> 16, 2);
2005 md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2);
2007 dwarf2_emit_insn (4);
2014 md_number_to_chars (f, 0xf000 | ip->extend, 2);
2017 md_number_to_chars (f, ip->insn_opcode, 2);
2019 dwarf2_emit_insn (ip->use_extend ? 4 : 2);
2023 /* Update the register mask information. */
2024 if (! mips_opts.mips16)
2026 if (pinfo & INSN_WRITE_GPR_D)
2027 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD);
2028 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
2029 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT);
2030 if (pinfo & INSN_READ_GPR_S)
2031 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS);
2032 if (pinfo & INSN_WRITE_GPR_31)
2033 mips_gprmask |= 1 << RA;
2034 if (pinfo & INSN_WRITE_FPR_D)
2035 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD);
2036 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
2037 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS);
2038 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
2039 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT);
2040 if ((pinfo & INSN_READ_FPR_R) != 0)
2041 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR);
2042 if (pinfo & INSN_COP)
2044 /* We don't keep enough information to sort these cases out.
2045 The itbl support does keep this information however, although
2046 we currently don't support itbl fprmats as part of the cop
2047 instruction. May want to add this support in the future. */
2049 /* Never set the bit for $0, which is always zero. */
2050 mips_gprmask &= ~1 << 0;
2054 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
2055 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX)
2056 & MIPS16OP_MASK_RX);
2057 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
2058 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY)
2059 & MIPS16OP_MASK_RY);
2060 if (pinfo & MIPS16_INSN_WRITE_Z)
2061 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ)
2062 & MIPS16OP_MASK_RZ);
2063 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
2064 mips_gprmask |= 1 << TREG;
2065 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
2066 mips_gprmask |= 1 << SP;
2067 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
2068 mips_gprmask |= 1 << RA;
2069 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2070 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2071 if (pinfo & MIPS16_INSN_READ_Z)
2072 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
2073 & MIPS16OP_MASK_MOVE32Z);
2074 if (pinfo & MIPS16_INSN_READ_GPR_X)
2075 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
2076 & MIPS16OP_MASK_REGR32);
2079 if (place == NULL && ! mips_opts.noreorder)
2081 /* Filling the branch delay slot is more complex. We try to
2082 switch the branch with the previous instruction, which we can
2083 do if the previous instruction does not set up a condition
2084 that the branch tests and if the branch is not itself the
2085 target of any branch. */
2086 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
2087 || (pinfo & INSN_COND_BRANCH_DELAY))
2089 if (mips_optimize < 2
2090 /* If we have seen .set volatile or .set nomove, don't
2092 || mips_opts.nomove != 0
2093 /* If we had to emit any NOP instructions, then we
2094 already know we can not swap. */
2096 /* If we don't even know the previous insn, we can not
2098 || ! prev_insn_valid
2099 /* If the previous insn is already in a branch delay
2100 slot, then we can not swap. */
2101 || prev_insn_is_delay_slot
2102 /* If the previous previous insn was in a .set
2103 noreorder, we can't swap. Actually, the MIPS
2104 assembler will swap in this situation. However, gcc
2105 configured -with-gnu-as will generate code like
2111 in which we can not swap the bne and INSN. If gcc is
2112 not configured -with-gnu-as, it does not output the
2113 .set pseudo-ops. We don't have to check
2114 prev_insn_unreordered, because prev_insn_valid will
2115 be 0 in that case. We don't want to use
2116 prev_prev_insn_valid, because we do want to be able
2117 to swap at the start of a function. */
2118 || prev_prev_insn_unreordered
2119 /* If the branch is itself the target of a branch, we
2120 can not swap. We cheat on this; all we check for is
2121 whether there is a label on this instruction. If
2122 there are any branches to anything other than a
2123 label, users must use .set noreorder. */
2124 || insn_labels != NULL
2125 /* If the previous instruction is in a variant frag, we
2126 can not do the swap. This does not apply to the
2127 mips16, which uses variant frags for different
2129 || (! mips_opts.mips16
2130 && prev_insn_frag->fr_type == rs_machine_dependent)
2131 /* If the branch reads the condition codes, we don't
2132 even try to swap, because in the sequence
2137 we can not swap, and I don't feel like handling that
2139 || (! mips_opts.mips16
2140 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2141 && (pinfo & INSN_READ_COND_CODE))
2142 /* We can not swap with an instruction that requires a
2143 delay slot, becase the target of the branch might
2144 interfere with that instruction. */
2145 || (! mips_opts.mips16
2146 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2148 /* Itbl support may require additional care here. */
2149 & (INSN_LOAD_COPROC_DELAY
2150 | INSN_COPROC_MOVE_DELAY
2151 | INSN_WRITE_COND_CODE)))
2152 || (! (hilo_interlocks
2153 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
2157 || (! mips_opts.mips16
2159 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))
2160 || (! mips_opts.mips16
2161 && mips_opts.isa == ISA_MIPS1
2162 /* Itbl support may require additional care here. */
2163 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))
2164 /* We can not swap with a branch instruction. */
2166 & (INSN_UNCOND_BRANCH_DELAY
2167 | INSN_COND_BRANCH_DELAY
2168 | INSN_COND_BRANCH_LIKELY))
2169 /* We do not swap with a trap instruction, since it
2170 complicates trap handlers to have the trap
2171 instruction be in a delay slot. */
2172 || (prev_pinfo & INSN_TRAP)
2173 /* If the branch reads a register that the previous
2174 instruction sets, we can not swap. */
2175 || (! mips_opts.mips16
2176 && (prev_pinfo & INSN_WRITE_GPR_T)
2177 && insn_uses_reg (ip,
2178 ((prev_insn.insn_opcode >> OP_SH_RT)
2181 || (! mips_opts.mips16
2182 && (prev_pinfo & INSN_WRITE_GPR_D)
2183 && insn_uses_reg (ip,
2184 ((prev_insn.insn_opcode >> OP_SH_RD)
2187 || (mips_opts.mips16
2188 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
2189 && insn_uses_reg (ip,
2190 ((prev_insn.insn_opcode
2192 & MIPS16OP_MASK_RX),
2194 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
2195 && insn_uses_reg (ip,
2196 ((prev_insn.insn_opcode
2198 & MIPS16OP_MASK_RY),
2200 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
2201 && insn_uses_reg (ip,
2202 ((prev_insn.insn_opcode
2204 & MIPS16OP_MASK_RZ),
2206 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
2207 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
2208 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
2209 && insn_uses_reg (ip, RA, MIPS_GR_REG))
2210 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2211 && insn_uses_reg (ip,
2212 MIPS16OP_EXTRACT_REG32R (prev_insn.
2215 /* If the branch writes a register that the previous
2216 instruction sets, we can not swap (we know that
2217 branches write only to RD or to $31). */
2218 || (! mips_opts.mips16
2219 && (prev_pinfo & INSN_WRITE_GPR_T)
2220 && (((pinfo & INSN_WRITE_GPR_D)
2221 && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)
2222 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2223 || ((pinfo & INSN_WRITE_GPR_31)
2224 && (((prev_insn.insn_opcode >> OP_SH_RT)
2227 || (! mips_opts.mips16
2228 && (prev_pinfo & INSN_WRITE_GPR_D)
2229 && (((pinfo & INSN_WRITE_GPR_D)
2230 && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD)
2231 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2232 || ((pinfo & INSN_WRITE_GPR_31)
2233 && (((prev_insn.insn_opcode >> OP_SH_RD)
2236 || (mips_opts.mips16
2237 && (pinfo & MIPS16_INSN_WRITE_31)
2238 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
2239 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2240 && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode)
2242 /* If the branch writes a register that the previous
2243 instruction reads, we can not swap (we know that
2244 branches only write to RD or to $31). */
2245 || (! mips_opts.mips16
2246 && (pinfo & INSN_WRITE_GPR_D)
2247 && insn_uses_reg (&prev_insn,
2248 ((ip->insn_opcode >> OP_SH_RD)
2251 || (! mips_opts.mips16
2252 && (pinfo & INSN_WRITE_GPR_31)
2253 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2254 || (mips_opts.mips16
2255 && (pinfo & MIPS16_INSN_WRITE_31)
2256 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2257 /* If we are generating embedded PIC code, the branch
2258 might be expanded into a sequence which uses $at, so
2259 we can't swap with an instruction which reads it. */
2260 || (mips_pic == EMBEDDED_PIC
2261 && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG))
2262 /* If the previous previous instruction has a load
2263 delay, and sets a register that the branch reads, we
2265 || (! mips_opts.mips16
2266 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2267 /* Itbl support may require additional care here. */
2268 && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
2269 || (! gpr_interlocks
2270 && (prev_prev_insn.insn_mo->pinfo
2271 & INSN_LOAD_MEMORY_DELAY)))
2272 && insn_uses_reg (ip,
2273 ((prev_prev_insn.insn_opcode >> OP_SH_RT)
2276 /* If one instruction sets a condition code and the
2277 other one uses a condition code, we can not swap. */
2278 || ((pinfo & INSN_READ_COND_CODE)
2279 && (prev_pinfo & INSN_WRITE_COND_CODE))
2280 || ((pinfo & INSN_WRITE_COND_CODE)
2281 && (prev_pinfo & INSN_READ_COND_CODE))
2282 /* If the previous instruction uses the PC, we can not
2284 || (mips_opts.mips16
2285 && (prev_pinfo & MIPS16_INSN_READ_PC))
2286 /* If the previous instruction was extended, we can not
2288 || (mips_opts.mips16 && prev_insn_extended)
2289 /* If the previous instruction had a fixup in mips16
2290 mode, we can not swap. This normally means that the
2291 previous instruction was a 4 byte branch anyhow. */
2292 || (mips_opts.mips16 && prev_insn_fixp[0])
2293 /* If the previous instruction is a sync, sync.l, or
2294 sync.p, we can not swap. */
2295 || (prev_pinfo & INSN_SYNC))
2297 /* We could do even better for unconditional branches to
2298 portions of this object file; we could pick up the
2299 instruction at the destination, put it in the delay
2300 slot, and bump the destination address. */
2302 /* Update the previous insn information. */
2303 prev_prev_insn = *ip;
2304 prev_insn.insn_mo = &dummy_opcode;
2308 /* It looks like we can actually do the swap. */
2309 if (! mips_opts.mips16)
2314 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2315 memcpy (temp, prev_f, 4);
2316 memcpy (prev_f, f, 4);
2317 memcpy (f, temp, 4);
2318 if (prev_insn_fixp[0])
2320 prev_insn_fixp[0]->fx_frag = frag_now;
2321 prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal;
2323 if (prev_insn_fixp[1])
2325 prev_insn_fixp[1]->fx_frag = frag_now;
2326 prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal;
2328 if (prev_insn_fixp[2])
2330 prev_insn_fixp[2]->fx_frag = frag_now;
2331 prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal;
2335 fixp[0]->fx_frag = prev_insn_frag;
2336 fixp[0]->fx_where = prev_insn_where;
2340 fixp[1]->fx_frag = prev_insn_frag;
2341 fixp[1]->fx_where = prev_insn_where;
2345 fixp[2]->fx_frag = prev_insn_frag;
2346 fixp[2]->fx_where = prev_insn_where;
2354 assert (prev_insn_fixp[0] == NULL);
2355 assert (prev_insn_fixp[1] == NULL);
2356 assert (prev_insn_fixp[2] == NULL);
2357 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2358 memcpy (temp, prev_f, 2);
2359 memcpy (prev_f, f, 2);
2360 if (*reloc_type != BFD_RELOC_MIPS16_JMP)
2362 assert (*reloc_type == BFD_RELOC_UNUSED);
2363 memcpy (f, temp, 2);
2367 memcpy (f, f + 2, 2);
2368 memcpy (f + 2, temp, 2);
2372 fixp[0]->fx_frag = prev_insn_frag;
2373 fixp[0]->fx_where = prev_insn_where;
2377 fixp[1]->fx_frag = prev_insn_frag;
2378 fixp[1]->fx_where = prev_insn_where;
2382 fixp[2]->fx_frag = prev_insn_frag;
2383 fixp[2]->fx_where = prev_insn_where;
2387 /* Update the previous insn information; leave prev_insn
2389 prev_prev_insn = *ip;
2391 prev_insn_is_delay_slot = 1;
2393 /* If that was an unconditional branch, forget the previous
2394 insn information. */
2395 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
2397 prev_prev_insn.insn_mo = &dummy_opcode;
2398 prev_insn.insn_mo = &dummy_opcode;
2401 prev_insn_fixp[0] = NULL;
2402 prev_insn_fixp[1] = NULL;
2403 prev_insn_fixp[2] = NULL;
2404 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2405 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2406 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2407 prev_insn_extended = 0;
2409 else if (pinfo & INSN_COND_BRANCH_LIKELY)
2411 /* We don't yet optimize a branch likely. What we should do
2412 is look at the target, copy the instruction found there
2413 into the delay slot, and increment the branch to jump to
2414 the next instruction. */
2416 /* Update the previous insn information. */
2417 prev_prev_insn = *ip;
2418 prev_insn.insn_mo = &dummy_opcode;
2419 prev_insn_fixp[0] = NULL;
2420 prev_insn_fixp[1] = NULL;
2421 prev_insn_fixp[2] = NULL;
2422 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2423 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2424 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2425 prev_insn_extended = 0;
2429 /* Update the previous insn information. */
2431 prev_prev_insn.insn_mo = &dummy_opcode;
2433 prev_prev_insn = prev_insn;
2436 /* Any time we see a branch, we always fill the delay slot
2437 immediately; since this insn is not a branch, we know it
2438 is not in a delay slot. */
2439 prev_insn_is_delay_slot = 0;
2441 prev_insn_fixp[0] = fixp[0];
2442 prev_insn_fixp[1] = fixp[1];
2443 prev_insn_fixp[2] = fixp[2];
2444 prev_insn_reloc_type[0] = reloc_type[0];
2445 prev_insn_reloc_type[1] = reloc_type[1];
2446 prev_insn_reloc_type[2] = reloc_type[2];
2447 if (mips_opts.mips16)
2448 prev_insn_extended = (ip->use_extend
2449 || *reloc_type > BFD_RELOC_UNUSED);
2452 prev_prev_insn_unreordered = prev_insn_unreordered;
2453 prev_insn_unreordered = 0;
2454 prev_insn_frag = frag_now;
2455 prev_insn_where = f - frag_now->fr_literal;
2456 prev_insn_valid = 1;
2458 else if (place == NULL)
2460 /* We need to record a bit of information even when we are not
2461 reordering, in order to determine the base address for mips16
2462 PC relative relocs. */
2463 prev_prev_insn = prev_insn;
2465 prev_insn_reloc_type[0] = reloc_type[0];
2466 prev_insn_reloc_type[1] = reloc_type[1];
2467 prev_insn_reloc_type[2] = reloc_type[2];
2468 prev_prev_insn_unreordered = prev_insn_unreordered;
2469 prev_insn_unreordered = 1;
2472 /* We just output an insn, so the next one doesn't have a label. */
2473 mips_clear_insn_labels ();
2475 /* We must ensure that a fixup associated with an unmatched %hi
2476 reloc does not become a variant frag. Otherwise, the
2477 rearrangement of %hi relocs in frob_file may confuse
2481 frag_wane (frag_now);
2486 /* This function forgets that there was any previous instruction or
2487 label. If PRESERVE is non-zero, it remembers enough information to
2488 know whether nops are needed before a noreorder section. */
2491 mips_no_prev_insn (preserve)
2496 prev_insn.insn_mo = &dummy_opcode;
2497 prev_prev_insn.insn_mo = &dummy_opcode;
2498 prev_nop_frag = NULL;
2499 prev_nop_frag_holds = 0;
2500 prev_nop_frag_required = 0;
2501 prev_nop_frag_since = 0;
2503 prev_insn_valid = 0;
2504 prev_insn_is_delay_slot = 0;
2505 prev_insn_unreordered = 0;
2506 prev_insn_extended = 0;
2507 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2508 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2509 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2510 prev_prev_insn_unreordered = 0;
2511 mips_clear_insn_labels ();
2514 /* This function must be called whenever we turn on noreorder or emit
2515 something other than instructions. It inserts any NOPS which might
2516 be needed by the previous instruction, and clears the information
2517 kept for the previous instructions. The INSNS parameter is true if
2518 instructions are to follow. */
2521 mips_emit_delays (insns)
2524 if (! mips_opts.noreorder)
2529 if ((! mips_opts.mips16
2530 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2531 && (! cop_interlocks
2532 && (prev_insn.insn_mo->pinfo
2533 & (INSN_LOAD_COPROC_DELAY
2534 | INSN_COPROC_MOVE_DELAY
2535 | INSN_WRITE_COND_CODE))))
2536 || (! hilo_interlocks
2537 && (prev_insn.insn_mo->pinfo
2540 || (! mips_opts.mips16
2542 && (prev_insn.insn_mo->pinfo
2543 & INSN_LOAD_MEMORY_DELAY))
2544 || (! mips_opts.mips16
2545 && mips_opts.isa == ISA_MIPS1
2546 && (prev_insn.insn_mo->pinfo
2547 & INSN_COPROC_MEMORY_DELAY)))
2549 /* Itbl support may require additional care here. */
2551 if ((! mips_opts.mips16
2552 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2553 && (! cop_interlocks
2554 && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
2555 || (! hilo_interlocks
2556 && ((prev_insn.insn_mo->pinfo & INSN_READ_HI)
2557 || (prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2560 if (prev_insn_unreordered)
2563 else if ((! mips_opts.mips16
2564 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2565 && (! cop_interlocks
2566 && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
2567 || (! hilo_interlocks
2568 && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
2569 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2571 /* Itbl support may require additional care here. */
2572 if (! prev_prev_insn_unreordered)
2578 struct insn_label_list *l;
2582 /* Record the frag which holds the nop instructions, so
2583 that we can remove them if we don't need them. */
2584 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
2585 prev_nop_frag = frag_now;
2586 prev_nop_frag_holds = nops;
2587 prev_nop_frag_required = 0;
2588 prev_nop_frag_since = 0;
2591 for (; nops > 0; --nops)
2596 /* Move on to a new frag, so that it is safe to simply
2597 decrease the size of prev_nop_frag. */
2598 frag_wane (frag_now);
2602 for (l = insn_labels; l != NULL; l = l->next)
2606 assert (S_GET_SEGMENT (l->label) == now_seg);
2607 symbol_set_frag (l->label, frag_now);
2608 val = (valueT) frag_now_fix ();
2609 /* mips16 text labels are stored as odd. */
2610 if (mips_opts.mips16)
2612 S_SET_VALUE (l->label, val);
2617 /* Mark instruction labels in mips16 mode. */
2619 mips16_mark_labels ();
2621 mips_no_prev_insn (insns);
2624 /* Build an instruction created by a macro expansion. This is passed
2625 a pointer to the count of instructions created so far, an
2626 expression, the name of the instruction to build, an operand format
2627 string, and corresponding arguments. */
2631 macro_build (char *place,
2639 macro_build (place, counter, ep, name, fmt, va_alist)
2648 struct mips_cl_insn insn;
2649 bfd_reloc_code_real_type r[3];
2653 va_start (args, fmt);
2659 * If the macro is about to expand into a second instruction,
2660 * print a warning if needed. We need to pass ip as a parameter
2661 * to generate a better warning message here...
2663 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
2664 as_warn (_("Macro instruction expanded into multiple instructions"));
2667 * If the macro is about to expand into a second instruction,
2668 * and it is in a delay slot, print a warning.
2672 && mips_opts.noreorder
2673 && (prev_prev_insn.insn_mo->pinfo
2674 & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY
2675 | INSN_COND_BRANCH_LIKELY)) != 0)
2676 as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot"));
2679 ++*counter; /* bump instruction counter */
2681 if (mips_opts.mips16)
2683 mips16_macro_build (place, counter, ep, name, fmt, args);
2688 r[0] = BFD_RELOC_UNUSED;
2689 r[1] = BFD_RELOC_UNUSED;
2690 r[2] = BFD_RELOC_UNUSED;
2691 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
2692 assert (insn.insn_mo);
2693 assert (strcmp (name, insn.insn_mo->name) == 0);
2695 /* Search until we get a match for NAME. */
2698 /* It is assumed here that macros will never generate
2699 MDMX or MIPS-3D instructions. */
2700 if (strcmp (fmt, insn.insn_mo->args) == 0
2701 && insn.insn_mo->pinfo != INSN_MACRO
2702 && OPCODE_IS_MEMBER (insn.insn_mo,
2704 | (mips_opts.mips16 ? INSN_MIPS16 : 0)),
2706 && (mips_arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
2710 assert (insn.insn_mo->name);
2711 assert (strcmp (name, insn.insn_mo->name) == 0);
2714 insn.insn_opcode = insn.insn_mo->match;
2730 insn.insn_opcode |= va_arg (args, int) << OP_SH_RT;
2734 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE;
2739 insn.insn_opcode |= va_arg (args, int) << OP_SH_FT;
2744 insn.insn_opcode |= va_arg (args, int) << OP_SH_RD;
2749 int tmp = va_arg (args, int);
2751 insn.insn_opcode |= tmp << OP_SH_RT;
2752 insn.insn_opcode |= tmp << OP_SH_RD;
2758 insn.insn_opcode |= va_arg (args, int) << OP_SH_FS;
2765 insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT;
2769 insn.insn_opcode |= va_arg (args, int) << OP_SH_FD;
2773 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20;
2777 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19;
2781 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2;
2788 insn.insn_opcode |= va_arg (args, int) << OP_SH_RS;
2794 *r = (bfd_reloc_code_real_type) va_arg (args, int);
2795 assert (*r == BFD_RELOC_GPREL16
2796 || *r == BFD_RELOC_MIPS_LITERAL
2797 || *r == BFD_RELOC_MIPS_HIGHER
2798 || *r == BFD_RELOC_HI16_S
2799 || *r == BFD_RELOC_LO16
2800 || *r == BFD_RELOC_MIPS_GOT16
2801 || *r == BFD_RELOC_MIPS_CALL16
2802 || *r == BFD_RELOC_MIPS_GOT_DISP
2803 || *r == BFD_RELOC_MIPS_GOT_PAGE
2804 || *r == BFD_RELOC_MIPS_GOT_OFST
2805 || *r == BFD_RELOC_MIPS_GOT_LO16
2806 || *r == BFD_RELOC_MIPS_CALL_LO16
2807 || (ep->X_op == O_subtract
2808 && *r == BFD_RELOC_PCREL_LO16));
2812 *r = (bfd_reloc_code_real_type) va_arg (args, int);
2814 && (ep->X_op == O_constant
2815 || (ep->X_op == O_symbol
2816 && (*r == BFD_RELOC_MIPS_HIGHEST
2817 || *r == BFD_RELOC_HI16_S
2818 || *r == BFD_RELOC_HI16
2819 || *r == BFD_RELOC_GPREL16
2820 || *r == BFD_RELOC_MIPS_GOT_HI16
2821 || *r == BFD_RELOC_MIPS_CALL_HI16))
2822 || (ep->X_op == O_subtract
2823 && *r == BFD_RELOC_PCREL_HI16_S)));
2827 assert (ep != NULL);
2829 * This allows macro() to pass an immediate expression for
2830 * creating short branches without creating a symbol.
2831 * Note that the expression still might come from the assembly
2832 * input, in which case the value is not checked for range nor
2833 * is a relocation entry generated (yuck).
2835 if (ep->X_op == O_constant)
2837 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
2841 if (mips_pic == EMBEDDED_PIC)
2842 *r = BFD_RELOC_16_PCREL_S2;
2844 *r = BFD_RELOC_16_PCREL;
2848 assert (ep != NULL);
2849 *r = BFD_RELOC_MIPS_JMP;
2853 insn.insn_opcode |= va_arg (args, unsigned long);
2862 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
2864 append_insn (place, &insn, ep, r, false);
2868 mips16_macro_build (place, counter, ep, name, fmt, args)
2870 int *counter ATTRIBUTE_UNUSED;
2876 struct mips_cl_insn insn;
2877 bfd_reloc_code_real_type r[3]
2878 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2880 insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
2881 assert (insn.insn_mo);
2882 assert (strcmp (name, insn.insn_mo->name) == 0);
2884 while (strcmp (fmt, insn.insn_mo->args) != 0
2885 || insn.insn_mo->pinfo == INSN_MACRO)
2888 assert (insn.insn_mo->name);
2889 assert (strcmp (name, insn.insn_mo->name) == 0);
2892 insn.insn_opcode = insn.insn_mo->match;
2893 insn.use_extend = false;
2912 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY;
2917 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX;
2921 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ;
2925 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z;
2935 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32;
2942 regno = va_arg (args, int);
2943 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
2944 insn.insn_opcode |= regno << MIPS16OP_SH_REG32R;
2965 assert (ep != NULL);
2967 if (ep->X_op != O_constant)
2968 *r = (int) BFD_RELOC_UNUSED + c;
2971 mips16_immed (NULL, 0, c, ep->X_add_number, false, false,
2972 false, &insn.insn_opcode, &insn.use_extend,
2975 *r = BFD_RELOC_UNUSED;
2981 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6;
2988 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
2990 append_insn (place, &insn, ep, r, false);
2994 * Generate a "jalr" instruction with a relocation hint to the called
2995 * function. This occurs in NewABI PIC code.
2998 macro_build_jalr (icnt, ep)
3009 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", "d,s",
3012 fix_new_exp (frag_now, f - frag_now->fr_literal,
3013 0, ep, false, BFD_RELOC_MIPS_JALR);
3017 * Generate a "lui" instruction.
3020 macro_build_lui (place, counter, ep, regnum)
3026 expressionS high_expr;
3027 struct mips_cl_insn insn;
3028 bfd_reloc_code_real_type r[3]
3029 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3030 const char *name = "lui";
3031 const char *fmt = "t,u";
3033 assert (! mips_opts.mips16);
3039 high_expr.X_op = O_constant;
3040 high_expr.X_add_number = ep->X_add_number;
3043 if (high_expr.X_op == O_constant)
3045 /* we can compute the instruction now without a relocation entry */
3046 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
3048 *r = BFD_RELOC_UNUSED;
3050 else if (! HAVE_NEWABI)
3052 assert (ep->X_op == O_symbol);
3053 /* _gp_disp is a special case, used from s_cpload. */
3054 assert (mips_pic == NO_PIC
3055 || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0);
3056 *r = BFD_RELOC_HI16_S;
3060 * If the macro is about to expand into a second instruction,
3061 * print a warning if needed. We need to pass ip as a parameter
3062 * to generate a better warning message here...
3064 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
3065 as_warn (_("Macro instruction expanded into multiple instructions"));
3068 ++*counter; /* bump instruction counter */
3070 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
3071 assert (insn.insn_mo);
3072 assert (strcmp (name, insn.insn_mo->name) == 0);
3073 assert (strcmp (fmt, insn.insn_mo->args) == 0);
3075 insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT);
3076 if (*r == BFD_RELOC_UNUSED)
3078 insn.insn_opcode |= high_expr.X_add_number;
3079 append_insn (place, &insn, NULL, r, false);
3082 append_insn (place, &insn, &high_expr, r, false);
3086 * Generates code to set the $at register to true (one)
3087 * if reg is less than the immediate expression.
3090 set_at (counter, reg, unsignedp)
3095 if (imm_expr.X_op == O_constant
3096 && imm_expr.X_add_number >= -0x8000
3097 && imm_expr.X_add_number < 0x8000)
3098 macro_build ((char *) NULL, counter, &imm_expr,
3099 unsignedp ? "sltiu" : "slti",
3100 "t,r,j", AT, reg, (int) BFD_RELOC_LO16);
3103 load_register (counter, AT, &imm_expr, HAVE_64BIT_GPRS);
3104 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3105 unsignedp ? "sltu" : "slt",
3106 "d,v,t", AT, reg, AT);
3110 /* Warn if an expression is not a constant. */
3113 check_absolute_expr (ip, ex)
3114 struct mips_cl_insn *ip;
3117 if (ex->X_op == O_big)
3118 as_bad (_("unsupported large constant"));
3119 else if (ex->X_op != O_constant)
3120 as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name);
3123 /* Count the leading zeroes by performing a binary chop. This is a
3124 bulky bit of source, but performance is a LOT better for the
3125 majority of values than a simple loop to count the bits:
3126 for (lcnt = 0; (lcnt < 32); lcnt++)
3127 if ((v) & (1 << (31 - lcnt)))
3129 However it is not code size friendly, and the gain will drop a bit
3130 on certain cached systems.
3132 #define COUNT_TOP_ZEROES(v) \
3133 (((v) & ~0xffff) == 0 \
3134 ? ((v) & ~0xff) == 0 \
3135 ? ((v) & ~0xf) == 0 \
3136 ? ((v) & ~0x3) == 0 \
3137 ? ((v) & ~0x1) == 0 \
3142 : ((v) & ~0x7) == 0 \
3145 : ((v) & ~0x3f) == 0 \
3146 ? ((v) & ~0x1f) == 0 \
3149 : ((v) & ~0x7f) == 0 \
3152 : ((v) & ~0xfff) == 0 \
3153 ? ((v) & ~0x3ff) == 0 \
3154 ? ((v) & ~0x1ff) == 0 \
3157 : ((v) & ~0x7ff) == 0 \
3160 : ((v) & ~0x3fff) == 0 \
3161 ? ((v) & ~0x1fff) == 0 \
3164 : ((v) & ~0x7fff) == 0 \
3167 : ((v) & ~0xffffff) == 0 \
3168 ? ((v) & ~0xfffff) == 0 \
3169 ? ((v) & ~0x3ffff) == 0 \
3170 ? ((v) & ~0x1ffff) == 0 \
3173 : ((v) & ~0x7ffff) == 0 \
3176 : ((v) & ~0x3fffff) == 0 \
3177 ? ((v) & ~0x1fffff) == 0 \
3180 : ((v) & ~0x7fffff) == 0 \
3183 : ((v) & ~0xfffffff) == 0 \
3184 ? ((v) & ~0x3ffffff) == 0 \
3185 ? ((v) & ~0x1ffffff) == 0 \
3188 : ((v) & ~0x7ffffff) == 0 \
3191 : ((v) & ~0x3fffffff) == 0 \
3192 ? ((v) & ~0x1fffffff) == 0 \
3195 : ((v) & ~0x7fffffff) == 0 \
3199 /* Is the given value a sign-extended 32-bit value? */
3200 #define IS_SEXT_32BIT_NUM(x) \
3201 (((x) &~ (offsetT) 0x7fffffff) == 0 \
3202 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
3205 * This routine generates the least number of instructions neccessary to load
3206 * an absolute expression value into a register.
3209 load_register (counter, reg, ep, dbl)
3216 expressionS hi32, lo32;
3218 if (ep->X_op != O_big)
3220 assert (ep->X_op == O_constant);
3221 if (ep->X_add_number < 0x8000
3222 && (ep->X_add_number >= 0
3223 || (ep->X_add_number >= -0x8000
3226 || sizeof (ep->X_add_number) > 4))))
3228 /* We can handle 16 bit signed values with an addiu to
3229 $zero. No need to ever use daddiu here, since $zero and
3230 the result are always correct in 32 bit mode. */
3231 macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3232 (int) BFD_RELOC_LO16);
3235 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
3237 /* We can handle 16 bit unsigned values with an ori to
3239 macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0,
3240 (int) BFD_RELOC_LO16);
3243 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)
3246 || sizeof (ep->X_add_number) > 4
3247 || (ep->X_add_number & 0x80000000) == 0))
3248 || ((HAVE_32BIT_GPRS || ! dbl)
3249 && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0)
3252 && ((ep->X_add_number &~ (offsetT) 0xffffffff)
3253 == ~ (offsetT) 0xffffffff)))
3255 /* 32 bit values require an lui. */
3256 macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg,
3257 (int) BFD_RELOC_HI16);
3258 if ((ep->X_add_number & 0xffff) != 0)
3259 macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg,
3260 (int) BFD_RELOC_LO16);
3265 /* The value is larger than 32 bits. */
3267 if (HAVE_32BIT_GPRS)
3269 as_bad (_("Number (0x%lx) larger than 32 bits"),
3270 (unsigned long) ep->X_add_number);
3271 macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3272 (int) BFD_RELOC_LO16);
3276 if (ep->X_op != O_big)
3279 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3280 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3281 hi32.X_add_number &= 0xffffffff;
3283 lo32.X_add_number &= 0xffffffff;
3287 assert (ep->X_add_number > 2);
3288 if (ep->X_add_number == 3)
3289 generic_bignum[3] = 0;
3290 else if (ep->X_add_number > 4)
3291 as_bad (_("Number larger than 64 bits"));
3292 lo32.X_op = O_constant;
3293 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
3294 hi32.X_op = O_constant;
3295 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
3298 if (hi32.X_add_number == 0)
3303 unsigned long hi, lo;
3305 if (hi32.X_add_number == (offsetT) 0xffffffff)
3307 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
3309 macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j",
3310 reg, 0, (int) BFD_RELOC_LO16);
3313 if (lo32.X_add_number & 0x80000000)
3315 macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg,
3316 (int) BFD_RELOC_HI16);
3317 if (lo32.X_add_number & 0xffff)
3318 macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i",
3319 reg, reg, (int) BFD_RELOC_LO16);
3324 /* Check for 16bit shifted constant. We know that hi32 is
3325 non-zero, so start the mask on the first bit of the hi32
3330 unsigned long himask, lomask;
3334 himask = 0xffff >> (32 - shift);
3335 lomask = (0xffff << shift) & 0xffffffff;
3339 himask = 0xffff << (shift - 32);
3342 if ((hi32.X_add_number & ~(offsetT) himask) == 0
3343 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
3347 tmp.X_op = O_constant;
3349 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
3350 | (lo32.X_add_number >> shift));
3352 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
3353 macro_build ((char *) NULL, counter, &tmp,
3354 "ori", "t,r,i", reg, 0,
3355 (int) BFD_RELOC_LO16);
3356 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3357 (shift >= 32) ? "dsll32" : "dsll",
3359 (shift >= 32) ? shift - 32 : shift);
3364 while (shift <= (64 - 16));
3366 /* Find the bit number of the lowest one bit, and store the
3367 shifted value in hi/lo. */
3368 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
3369 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
3373 while ((lo & 1) == 0)
3378 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
3384 while ((hi & 1) == 0)
3393 /* Optimize if the shifted value is a (power of 2) - 1. */
3394 if ((hi == 0 && ((lo + 1) & lo) == 0)
3395 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
3397 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
3402 /* This instruction will set the register to be all
3404 tmp.X_op = O_constant;
3405 tmp.X_add_number = (offsetT) -1;
3406 macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j",
3407 reg, 0, (int) BFD_RELOC_LO16);
3411 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3412 (bit >= 32) ? "dsll32" : "dsll",
3414 (bit >= 32) ? bit - 32 : bit);
3416 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3417 (shift >= 32) ? "dsrl32" : "dsrl",
3419 (shift >= 32) ? shift - 32 : shift);
3424 /* Sign extend hi32 before calling load_register, because we can
3425 generally get better code when we load a sign extended value. */
3426 if ((hi32.X_add_number & 0x80000000) != 0)
3427 hi32.X_add_number |= ~(offsetT) 0xffffffff;
3428 load_register (counter, reg, &hi32, 0);
3431 if ((lo32.X_add_number & 0xffff0000) == 0)
3435 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3436 "dsll32", "d,w,<", reg, freg, 0);
3444 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
3446 macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg,
3447 (int) BFD_RELOC_HI16);
3448 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3449 "dsrl32", "d,w,<", reg, reg, 0);
3455 macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll",
3456 "d,w,<", reg, freg, 16);
3460 mid16.X_add_number >>= 16;
3461 macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg,
3462 freg, (int) BFD_RELOC_LO16);
3463 macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll",
3464 "d,w,<", reg, reg, 16);
3467 if ((lo32.X_add_number & 0xffff) != 0)
3468 macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg,
3469 (int) BFD_RELOC_LO16);
3472 /* Load an address into a register. */
3475 load_address (counter, reg, ep, used_at)
3483 if (ep->X_op != O_constant
3484 && ep->X_op != O_symbol)
3486 as_bad (_("expression too complex"));
3487 ep->X_op = O_constant;
3490 if (ep->X_op == O_constant)
3492 load_register (counter, reg, ep, HAVE_64BIT_ADDRESSES);
3496 if (mips_pic == NO_PIC)
3498 /* If this is a reference to a GP relative symbol, we want
3499 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3501 lui $reg,<sym> (BFD_RELOC_HI16_S)
3502 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3503 If we have an addend, we always use the latter form.
3505 With 64bit address space and a usable $at we want
3506 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3507 lui $at,<sym> (BFD_RELOC_HI16_S)
3508 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3509 daddiu $at,<sym> (BFD_RELOC_LO16)
3513 If $at is already in use, we use an path which is suboptimal
3514 on superscalar processors.
3515 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3516 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3518 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3520 daddiu $reg,<sym> (BFD_RELOC_LO16)
3522 if (HAVE_64BIT_ADDRESSES)
3524 /* We don't do GP optimization for now because RELAX_ENCODE can't
3525 hold the data for such large chunks. */
3527 if (*used_at == 0 && ! mips_opts.noat)
3529 macro_build (p, counter, ep, "lui", "t,u",
3530 reg, (int) BFD_RELOC_MIPS_HIGHEST);
3531 macro_build (p, counter, ep, "lui", "t,u",
3532 AT, (int) BFD_RELOC_HI16_S);
3533 macro_build (p, counter, ep, "daddiu", "t,r,j",
3534 reg, reg, (int) BFD_RELOC_MIPS_HIGHER);
3535 macro_build (p, counter, ep, "daddiu", "t,r,j",
3536 AT, AT, (int) BFD_RELOC_LO16);
3537 macro_build (p, counter, (expressionS *) NULL, "dsll32",
3538 "d,w,<", reg, reg, 0);
3539 macro_build (p, counter, (expressionS *) NULL, "daddu",
3540 "d,v,t", reg, reg, AT);
3545 macro_build (p, counter, ep, "lui", "t,u",
3546 reg, (int) BFD_RELOC_MIPS_HIGHEST);
3547 macro_build (p, counter, ep, "daddiu", "t,r,j",
3548 reg, reg, (int) BFD_RELOC_MIPS_HIGHER);
3549 macro_build (p, counter, (expressionS *) NULL, "dsll",
3550 "d,w,<", reg, reg, 16);
3551 macro_build (p, counter, ep, "daddiu", "t,r,j",
3552 reg, reg, (int) BFD_RELOC_HI16_S);
3553 macro_build (p, counter, (expressionS *) NULL, "dsll",
3554 "d,w,<", reg, reg, 16);
3555 macro_build (p, counter, ep, "daddiu", "t,r,j",
3556 reg, reg, (int) BFD_RELOC_LO16);
3561 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
3562 && ! nopic_need_relax (ep->X_add_symbol, 1))
3565 macro_build ((char *) NULL, counter, ep,
3566 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j",
3567 reg, mips_gp_register, (int) BFD_RELOC_GPREL16);
3568 p = frag_var (rs_machine_dependent, 8, 0,
3569 RELAX_ENCODE (4, 8, 0, 4, 0,
3570 mips_opts.warn_about_macros),
3571 ep->X_add_symbol, 0, NULL);
3573 macro_build_lui (p, counter, ep, reg);
3576 macro_build (p, counter, ep,
3577 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3578 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3581 else if (mips_pic == SVR4_PIC && ! mips_big_got)
3585 /* If this is a reference to an external symbol, we want
3586 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3588 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3590 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3591 If we have NewABI, we want
3592 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3593 If there is a constant, it must be added in after. */
3594 ex.X_add_number = ep->X_add_number;
3595 ep->X_add_number = 0;
3599 macro_build ((char *) NULL, counter, ep,
3600 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg,
3601 (int) BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
3605 macro_build ((char *) NULL, counter, ep,
3606 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)",
3607 reg, (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
3608 macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", "");
3609 p = frag_var (rs_machine_dependent, 4, 0,
3610 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros),
3611 ep->X_add_symbol, (offsetT) 0, (char *) NULL);
3612 macro_build (p, counter, ep,
3613 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3614 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3617 if (ex.X_add_number != 0)
3619 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3620 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3621 ex.X_op = O_constant;
3622 macro_build ((char *) NULL, counter, &ex,
3623 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3624 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3627 else if (mips_pic == SVR4_PIC)
3632 /* This is the large GOT case. If this is a reference to an
3633 external symbol, we want
3634 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3636 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3637 Otherwise, for a reference to a local symbol, we want
3638 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3640 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3641 If we have NewABI, we want
3642 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3643 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3644 If there is a constant, it must be added in after. */
3645 ex.X_add_number = ep->X_add_number;
3646 ep->X_add_number = 0;
3649 macro_build ((char *) NULL, counter, ep,
3650 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg,
3651 (int) BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
3652 macro_build (p, counter, ep,
3653 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j",
3654 reg, reg, (int) BFD_RELOC_MIPS_GOT_OFST);
3658 if (reg_needs_delay (mips_gp_register))
3663 macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg,
3664 (int) BFD_RELOC_MIPS_GOT_HI16);
3665 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3666 HAVE_32BIT_ADDRESSES ? "addu" : "daddu", "d,v,t", reg,
3667 reg, mips_gp_register);
3668 macro_build ((char *) NULL, counter, ep,
3669 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
3670 "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg);
3671 p = frag_var (rs_machine_dependent, 12 + off, 0,
3672 RELAX_ENCODE (12, 12 + off, off, 8 + off, 0,
3673 mips_opts.warn_about_macros),
3674 ep->X_add_symbol, 0, NULL);
3677 /* We need a nop before loading from $gp. This special
3678 check is required because the lui which starts the main
3679 instruction stream does not refer to $gp, and so will not
3680 insert the nop which may be required. */
3681 macro_build (p, counter, (expressionS *) NULL, "nop", "");
3684 macro_build (p, counter, ep,
3685 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg,
3686 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
3688 macro_build (p, counter, (expressionS *) NULL, "nop", "");
3690 macro_build (p, counter, ep,
3691 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3692 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3695 if (ex.X_add_number != 0)
3697 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3698 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3699 ex.X_op = O_constant;
3700 macro_build ((char *) NULL, counter, &ex,
3701 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3702 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3705 else if (mips_pic == EMBEDDED_PIC)
3708 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3710 macro_build ((char *) NULL, counter, ep,
3711 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3712 "t,r,j", reg, mips_gp_register, (int) BFD_RELOC_GPREL16);
3718 /* Move the contents of register SOURCE into register DEST. */
3721 move_register (counter, dest, source)
3726 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3727 HAVE_32BIT_GPRS ? "addu" : "daddu",
3728 "d,v,t", dest, source, 0);
3733 * This routine implements the seemingly endless macro or synthesized
3734 * instructions and addressing modes in the mips assembly language. Many
3735 * of these macros are simple and are similar to each other. These could
3736 * probably be handled by some kind of table or grammer aproach instead of
3737 * this verbose method. Others are not simple macros but are more like
3738 * optimizing code generation.
3739 * One interesting optimization is when several store macros appear
3740 * consecutivly that would load AT with the upper half of the same address.
3741 * The ensuing load upper instructions are ommited. This implies some kind
3742 * of global optimization. We currently only optimize within a single macro.
3743 * For many of the load and store macros if the address is specified as a
3744 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3745 * first load register 'at' with zero and use it as the base register. The
3746 * mips assembler simply uses register $zero. Just one tiny optimization
3751 struct mips_cl_insn *ip;
3753 register int treg, sreg, dreg, breg;
3769 bfd_reloc_code_real_type r;
3770 int hold_mips_optimize;
3772 assert (! mips_opts.mips16);
3774 treg = (ip->insn_opcode >> 16) & 0x1f;
3775 dreg = (ip->insn_opcode >> 11) & 0x1f;
3776 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
3777 mask = ip->insn_mo->mask;
3779 expr1.X_op = O_constant;
3780 expr1.X_op_symbol = NULL;
3781 expr1.X_add_symbol = NULL;
3782 expr1.X_add_number = 1;
3794 mips_emit_delays (true);
3795 ++mips_opts.noreorder;
3796 mips_any_noreorder = 1;
3798 expr1.X_add_number = 8;
3799 macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg);
3801 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
3804 move_register (&icnt, dreg, sreg);
3805 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
3806 dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
3808 --mips_opts.noreorder;
3829 if (imm_expr.X_op == O_constant
3830 && imm_expr.X_add_number >= -0x8000
3831 && imm_expr.X_add_number < 0x8000)
3833 macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg,
3834 (int) BFD_RELOC_LO16);
3837 load_register (&icnt, AT, &imm_expr, dbl);
3838 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t",
3858 if (imm_expr.X_op == O_constant
3859 && imm_expr.X_add_number >= 0
3860 && imm_expr.X_add_number < 0x10000)
3862 if (mask != M_NOR_I)
3863 macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg,
3864 sreg, (int) BFD_RELOC_LO16);
3867 macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i",
3868 treg, sreg, (int) BFD_RELOC_LO16);
3869 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nor",
3870 "d,v,t", treg, treg, 0);
3875 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
3876 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t",
3894 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
3896 macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg,
3900 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
3901 macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT);
3909 macro_build ((char *) NULL, &icnt, &offset_expr,
3910 likely ? "bgezl" : "bgez", "s,p", sreg);
3915 macro_build ((char *) NULL, &icnt, &offset_expr,
3916 likely ? "blezl" : "blez", "s,p", treg);
3919 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
3921 macro_build ((char *) NULL, &icnt, &offset_expr,
3922 likely ? "beql" : "beq", "s,t,p", AT, 0);
3928 /* check for > max integer */
3929 maxnum = 0x7fffffff;
3930 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
3937 if (imm_expr.X_op == O_constant
3938 && imm_expr.X_add_number >= maxnum
3939 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
3942 /* result is always false */
3946 as_warn (_("Branch %s is always false (nop)"),
3948 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop",
3954 as_warn (_("Branch likely %s is always false"),
3956 macro_build ((char *) NULL, &icnt, &offset_expr, "bnel",
3961 if (imm_expr.X_op != O_constant)
3962 as_bad (_("Unsupported large constant"));
3963 ++imm_expr.X_add_number;
3967 if (mask == M_BGEL_I)
3969 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
3971 macro_build ((char *) NULL, &icnt, &offset_expr,
3972 likely ? "bgezl" : "bgez", "s,p", sreg);
3975 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
3977 macro_build ((char *) NULL, &icnt, &offset_expr,
3978 likely ? "bgtzl" : "bgtz", "s,p", sreg);
3981 maxnum = 0x7fffffff;
3982 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
3989 maxnum = - maxnum - 1;
3990 if (imm_expr.X_op == O_constant
3991 && imm_expr.X_add_number <= maxnum
3992 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
3995 /* result is always true */
3996 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
3997 macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p");
4000 set_at (&icnt, sreg, 0);
4001 macro_build ((char *) NULL, &icnt, &offset_expr,
4002 likely ? "beql" : "beq", "s,t,p", AT, 0);
4012 macro_build ((char *) NULL, &icnt, &offset_expr,
4013 likely ? "beql" : "beq", "s,t,p", 0, treg);
4016 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4017 "d,v,t", AT, sreg, treg);
4018 macro_build ((char *) NULL, &icnt, &offset_expr,
4019 likely ? "beql" : "beq", "s,t,p", AT, 0);
4027 && imm_expr.X_op == O_constant
4028 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4030 if (imm_expr.X_op != O_constant)
4031 as_bad (_("Unsupported large constant"));
4032 ++imm_expr.X_add_number;
4036 if (mask == M_BGEUL_I)
4038 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4040 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4042 macro_build ((char *) NULL, &icnt, &offset_expr,
4043 likely ? "bnel" : "bne", "s,t,p", sreg, 0);
4046 set_at (&icnt, sreg, 1);
4047 macro_build ((char *) NULL, &icnt, &offset_expr,
4048 likely ? "beql" : "beq", "s,t,p", AT, 0);
4056 macro_build ((char *) NULL, &icnt, &offset_expr,
4057 likely ? "bgtzl" : "bgtz", "s,p", sreg);
4062 macro_build ((char *) NULL, &icnt, &offset_expr,
4063 likely ? "bltzl" : "bltz", "s,p", treg);
4066 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4068 macro_build ((char *) NULL, &icnt, &offset_expr,
4069 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4077 macro_build ((char *) NULL, &icnt, &offset_expr,
4078 likely ? "bnel" : "bne", "s,t,p", sreg, 0);
4083 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4084 "d,v,t", AT, treg, sreg);
4085 macro_build ((char *) NULL, &icnt, &offset_expr,
4086 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4094 macro_build ((char *) NULL, &icnt, &offset_expr,
4095 likely ? "blezl" : "blez", "s,p", sreg);
4100 macro_build ((char *) NULL, &icnt, &offset_expr,
4101 likely ? "bgezl" : "bgez", "s,p", treg);
4104 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4106 macro_build ((char *) NULL, &icnt, &offset_expr,
4107 likely ? "beql" : "beq", "s,t,p", AT, 0);
4113 maxnum = 0x7fffffff;
4114 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4121 if (imm_expr.X_op == O_constant
4122 && imm_expr.X_add_number >= maxnum
4123 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4125 if (imm_expr.X_op != O_constant)
4126 as_bad (_("Unsupported large constant"));
4127 ++imm_expr.X_add_number;
4131 if (mask == M_BLTL_I)
4133 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4135 macro_build ((char *) NULL, &icnt, &offset_expr,
4136 likely ? "bltzl" : "bltz", "s,p", sreg);
4139 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4141 macro_build ((char *) NULL, &icnt, &offset_expr,
4142 likely ? "blezl" : "blez", "s,p", sreg);
4145 set_at (&icnt, sreg, 0);
4146 macro_build ((char *) NULL, &icnt, &offset_expr,
4147 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4155 macro_build ((char *) NULL, &icnt, &offset_expr,
4156 likely ? "beql" : "beq", "s,t,p", sreg, 0);
4161 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4162 "d,v,t", AT, treg, sreg);
4163 macro_build ((char *) NULL, &icnt, &offset_expr,
4164 likely ? "beql" : "beq", "s,t,p", AT, 0);
4172 && imm_expr.X_op == O_constant
4173 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4175 if (imm_expr.X_op != O_constant)
4176 as_bad (_("Unsupported large constant"));
4177 ++imm_expr.X_add_number;
4181 if (mask == M_BLTUL_I)
4183 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4185 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4187 macro_build ((char *) NULL, &icnt, &offset_expr,
4188 likely ? "beql" : "beq",
4192 set_at (&icnt, sreg, 1);
4193 macro_build ((char *) NULL, &icnt, &offset_expr,
4194 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4202 macro_build ((char *) NULL, &icnt, &offset_expr,
4203 likely ? "bltzl" : "bltz", "s,p", sreg);
4208 macro_build ((char *) NULL, &icnt, &offset_expr,
4209 likely ? "bgtzl" : "bgtz", "s,p", treg);
4212 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4214 macro_build ((char *) NULL, &icnt, &offset_expr,
4215 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4225 macro_build ((char *) NULL, &icnt, &offset_expr,
4226 likely ? "bnel" : "bne", "s,t,p", 0, treg);
4229 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4232 macro_build ((char *) NULL, &icnt, &offset_expr,
4233 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4248 as_warn (_("Divide by zero."));
4250 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4253 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4258 mips_emit_delays (true);
4259 ++mips_opts.noreorder;
4260 mips_any_noreorder = 1;
4263 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4264 "s,t,q", treg, 0, 7);
4265 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4266 dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4270 expr1.X_add_number = 8;
4271 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4272 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4273 dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4274 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4277 expr1.X_add_number = -1;
4278 macro_build ((char *) NULL, &icnt, &expr1,
4279 dbl ? "daddiu" : "addiu",
4280 "t,r,j", AT, 0, (int) BFD_RELOC_LO16);
4281 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
4282 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT);
4285 expr1.X_add_number = 1;
4286 macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0,
4287 (int) BFD_RELOC_LO16);
4288 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsll32",
4289 "d,w,<", AT, AT, 31);
4293 expr1.X_add_number = 0x80000000;
4294 macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT,
4295 (int) BFD_RELOC_HI16);
4299 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4300 "s,t,q", sreg, AT, 6);
4301 /* We want to close the noreorder block as soon as possible, so
4302 that later insns are available for delay slot filling. */
4303 --mips_opts.noreorder;
4307 expr1.X_add_number = 8;
4308 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT);
4309 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
4312 /* We want to close the noreorder block as soon as possible, so
4313 that later insns are available for delay slot filling. */
4314 --mips_opts.noreorder;
4316 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4319 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d", dreg);
4358 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4360 as_warn (_("Divide by zero."));
4362 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4365 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4369 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4371 if (strcmp (s2, "mflo") == 0)
4372 move_register (&icnt, dreg, sreg);
4374 move_register (&icnt, dreg, 0);
4377 if (imm_expr.X_op == O_constant
4378 && imm_expr.X_add_number == -1
4379 && s[strlen (s) - 1] != 'u')
4381 if (strcmp (s2, "mflo") == 0)
4383 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4384 dbl ? "dneg" : "neg", "d,w", dreg, sreg);
4387 move_register (&icnt, dreg, 0);
4391 load_register (&icnt, AT, &imm_expr, dbl);
4392 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4394 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg);
4413 mips_emit_delays (true);
4414 ++mips_opts.noreorder;
4415 mips_any_noreorder = 1;
4418 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4419 "s,t,q", treg, 0, 7);
4420 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4422 /* We want to close the noreorder block as soon as possible, so
4423 that later insns are available for delay slot filling. */
4424 --mips_opts.noreorder;
4428 expr1.X_add_number = 8;
4429 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4430 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4433 /* We want to close the noreorder block as soon as possible, so
4434 that later insns are available for delay slot filling. */
4435 --mips_opts.noreorder;
4436 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4439 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg);
4445 /* Load the address of a symbol into a register. If breg is not
4446 zero, we then add a base register to it. */
4448 if (dbl && HAVE_32BIT_GPRS)
4449 as_warn (_("dla used to load 32-bit register"));
4451 if (! dbl && HAVE_64BIT_OBJECTS)
4452 as_warn (_("la used to load 64-bit address"));
4454 if (offset_expr.X_op == O_constant
4455 && offset_expr.X_add_number >= -0x8000
4456 && offset_expr.X_add_number < 0x8000)
4458 macro_build ((char *) NULL, &icnt, &offset_expr,
4459 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4460 "t,r,j", treg, sreg, (int) BFD_RELOC_LO16);
4475 /* When generating embedded PIC code, we permit expressions of
4478 la $treg,foo-bar($breg)
4479 where bar is an address in the current section. These are used
4480 when getting the addresses of functions. We don't permit
4481 X_add_number to be non-zero, because if the symbol is
4482 external the relaxing code needs to know that any addend is
4483 purely the offset to X_op_symbol. */
4484 if (mips_pic == EMBEDDED_PIC
4485 && offset_expr.X_op == O_subtract
4486 && (symbol_constant_p (offset_expr.X_op_symbol)
4487 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
4488 : (symbol_equated_p (offset_expr.X_op_symbol)
4490 (symbol_get_value_expression (offset_expr.X_op_symbol)
4493 && (offset_expr.X_add_number == 0
4494 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
4500 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4501 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
4505 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4506 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
4507 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4508 (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu",
4509 "d,v,t", tempreg, tempreg, breg);
4511 macro_build ((char *) NULL, &icnt, &offset_expr,
4512 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4513 "t,r,j", treg, tempreg, (int) BFD_RELOC_PCREL_LO16);
4519 if (offset_expr.X_op != O_symbol
4520 && offset_expr.X_op != O_constant)
4522 as_bad (_("expression too complex"));
4523 offset_expr.X_op = O_constant;
4526 if (offset_expr.X_op == O_constant)
4527 load_register (&icnt, tempreg, &offset_expr,
4528 ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
4529 ? (dbl || HAVE_64BIT_ADDRESSES)
4530 : HAVE_64BIT_ADDRESSES));
4531 else if (mips_pic == NO_PIC)
4533 /* If this is a reference to a GP relative symbol, we want
4534 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4536 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4537 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4538 If we have a constant, we need two instructions anyhow,
4539 so we may as well always use the latter form.
4541 With 64bit address space and a usable $at we want
4542 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4543 lui $at,<sym> (BFD_RELOC_HI16_S)
4544 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4545 daddiu $at,<sym> (BFD_RELOC_LO16)
4547 daddu $tempreg,$tempreg,$at
4549 If $at is already in use, we use an path which is suboptimal
4550 on superscalar processors.
4551 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4552 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4554 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4556 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4559 if (HAVE_64BIT_ADDRESSES)
4561 /* We don't do GP optimization for now because RELAX_ENCODE can't
4562 hold the data for such large chunks. */
4564 if (used_at == 0 && ! mips_opts.noat)
4566 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4567 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
4568 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4569 AT, (int) BFD_RELOC_HI16_S);
4570 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4571 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
4572 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4573 AT, AT, (int) BFD_RELOC_LO16);
4574 macro_build (p, &icnt, (expressionS *) NULL, "dsll32",
4575 "d,w,<", tempreg, tempreg, 0);
4576 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
4577 "d,v,t", tempreg, tempreg, AT);
4582 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4583 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
4584 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4585 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
4586 macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<",
4587 tempreg, tempreg, 16);
4588 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4589 tempreg, tempreg, (int) BFD_RELOC_HI16_S);
4590 macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<",
4591 tempreg, tempreg, 16);
4592 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4593 tempreg, tempreg, (int) BFD_RELOC_LO16);
4598 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
4599 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
4602 macro_build ((char *) NULL, &icnt, &offset_expr, "addiu",
4603 "t,r,j", tempreg, mips_gp_register,
4604 (int) BFD_RELOC_GPREL16);
4605 p = frag_var (rs_machine_dependent, 8, 0,
4606 RELAX_ENCODE (4, 8, 0, 4, 0,
4607 mips_opts.warn_about_macros),
4608 offset_expr.X_add_symbol, 0, NULL);
4610 macro_build_lui (p, &icnt, &offset_expr, tempreg);
4613 macro_build (p, &icnt, &offset_expr, "addiu",
4614 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4617 else if (mips_pic == SVR4_PIC && ! mips_big_got)
4619 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
4621 /* If this is a reference to an external symbol, and there
4622 is no constant, we want
4623 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4624 or if tempreg is PIC_CALL_REG
4625 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4626 For a local symbol, we want
4627 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4629 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4631 If we have a small constant, and this is a reference to
4632 an external symbol, we want
4633 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4635 addiu $tempreg,$tempreg,<constant>
4636 For a local symbol, we want the same instruction
4637 sequence, but we output a BFD_RELOC_LO16 reloc on the
4640 If we have a large constant, and this is a reference to
4641 an external symbol, we want
4642 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4643 lui $at,<hiconstant>
4644 addiu $at,$at,<loconstant>
4645 addu $tempreg,$tempreg,$at
4646 For a local symbol, we want the same instruction
4647 sequence, but we output a BFD_RELOC_LO16 reloc on the
4650 For NewABI, we want for local or external data addresses
4651 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4652 For a local function symbol, we want
4653 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4655 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4658 expr1.X_add_number = offset_expr.X_add_number;
4659 offset_expr.X_add_number = 0;
4661 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
4662 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
4663 else if (HAVE_NEWABI)
4664 lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_DISP;
4665 macro_build ((char *) NULL, &icnt, &offset_expr,
4666 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
4667 "t,o(b)", tempreg, lw_reloc_type, mips_gp_register);
4668 if (expr1.X_add_number == 0)
4677 /* We're going to put in an addu instruction using
4678 tempreg, so we may as well insert the nop right
4680 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4684 p = frag_var (rs_machine_dependent, 8 - off, 0,
4685 RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0,
4687 ? mips_opts.warn_about_macros
4689 offset_expr.X_add_symbol, 0, NULL);
4692 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
4695 macro_build (p, &icnt, &expr1,
4696 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4697 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4698 /* FIXME: If breg == 0, and the next instruction uses
4699 $tempreg, then if this variant case is used an extra
4700 nop will be generated. */
4702 else if (expr1.X_add_number >= -0x8000
4703 && expr1.X_add_number < 0x8000)
4705 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4707 macro_build ((char *) NULL, &icnt, &expr1,
4708 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4709 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4710 frag_var (rs_machine_dependent, 0, 0,
4711 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4712 offset_expr.X_add_symbol, 0, NULL);
4718 /* If we are going to add in a base register, and the
4719 target register and the base register are the same,
4720 then we are using AT as a temporary register. Since
4721 we want to load the constant into AT, we add our
4722 current AT (from the global offset table) and the
4723 register into the register now, and pretend we were
4724 not using a base register. */
4729 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4731 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4732 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4733 "d,v,t", treg, AT, breg);
4739 /* Set mips_optimize around the lui instruction to avoid
4740 inserting an unnecessary nop after the lw. */
4741 hold_mips_optimize = mips_optimize;
4743 macro_build_lui (NULL, &icnt, &expr1, AT);
4744 mips_optimize = hold_mips_optimize;
4746 macro_build ((char *) NULL, &icnt, &expr1,
4747 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4748 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
4749 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4750 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4751 "d,v,t", tempreg, tempreg, AT);
4752 frag_var (rs_machine_dependent, 0, 0,
4753 RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0),
4754 offset_expr.X_add_symbol, 0, NULL);
4758 else if (mips_pic == SVR4_PIC)
4762 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
4763 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
4764 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
4766 /* This is the large GOT case. If this is a reference to an
4767 external symbol, and there is no constant, we want
4768 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4769 addu $tempreg,$tempreg,$gp
4770 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4771 or if tempreg is PIC_CALL_REG
4772 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4773 addu $tempreg,$tempreg,$gp
4774 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
4775 For a local symbol, we want
4776 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4778 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4780 If we have a small constant, and this is a reference to
4781 an external symbol, we want
4782 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4783 addu $tempreg,$tempreg,$gp
4784 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4786 addiu $tempreg,$tempreg,<constant>
4787 For a local symbol, we want
4788 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4790 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4792 If we have a large constant, and this is a reference to
4793 an external symbol, we want
4794 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4795 addu $tempreg,$tempreg,$gp
4796 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4797 lui $at,<hiconstant>
4798 addiu $at,$at,<loconstant>
4799 addu $tempreg,$tempreg,$at
4800 For a local symbol, we want
4801 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4802 lui $at,<hiconstant>
4803 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4804 addu $tempreg,$tempreg,$at
4806 For NewABI, we want for local data addresses
4807 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4810 expr1.X_add_number = offset_expr.X_add_number;
4811 offset_expr.X_add_number = 0;
4813 if (reg_needs_delay (mips_gp_register))
4817 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
4819 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
4820 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
4822 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4823 tempreg, lui_reloc_type);
4824 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4825 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4826 "d,v,t", tempreg, tempreg, mips_gp_register);
4827 macro_build ((char *) NULL, &icnt, &offset_expr,
4828 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
4829 "t,o(b)", tempreg, lw_reloc_type, tempreg);
4830 if (expr1.X_add_number == 0)
4838 /* We're going to put in an addu instruction using
4839 tempreg, so we may as well insert the nop right
4841 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4846 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
4847 RELAX_ENCODE (12 + off, 12 + gpdel, gpdel,
4850 ? mips_opts.warn_about_macros
4852 offset_expr.X_add_symbol, 0, NULL);
4854 else if (expr1.X_add_number >= -0x8000
4855 && expr1.X_add_number < 0x8000)
4857 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4859 macro_build ((char *) NULL, &icnt, &expr1,
4860 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4861 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4863 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
4864 RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0,
4866 ? mips_opts.warn_about_macros
4868 offset_expr.X_add_symbol, 0, NULL);
4874 /* If we are going to add in a base register, and the
4875 target register and the base register are the same,
4876 then we are using AT as a temporary register. Since
4877 we want to load the constant into AT, we add our
4878 current AT (from the global offset table) and the
4879 register into the register now, and pretend we were
4880 not using a base register. */
4888 assert (tempreg == AT);
4889 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4891 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4892 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4893 "d,v,t", treg, AT, breg);
4898 /* Set mips_optimize around the lui instruction to avoid
4899 inserting an unnecessary nop after the lw. */
4900 hold_mips_optimize = mips_optimize;
4902 macro_build_lui (NULL, &icnt, &expr1, AT);
4903 mips_optimize = hold_mips_optimize;
4905 macro_build ((char *) NULL, &icnt, &expr1,
4906 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4907 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
4908 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4909 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4910 "d,v,t", dreg, dreg, AT);
4912 p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0,
4913 RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel,
4916 ? mips_opts.warn_about_macros
4918 offset_expr.X_add_symbol, 0, NULL);
4925 /* This is needed because this instruction uses $gp, but
4926 the first instruction on the main stream does not. */
4927 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
4932 local_reloc_type = (int) BFD_RELOC_MIPS_GOT_DISP;
4933 macro_build (p, &icnt, &offset_expr,
4934 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
4939 if (expr1.X_add_number == 0 && HAVE_NEWABI)
4941 /* BFD_RELOC_MIPS_GOT_DISP is sufficient for newabi */
4944 if (expr1.X_add_number >= -0x8000
4945 && expr1.X_add_number < 0x8000)
4947 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
4949 macro_build (p, &icnt, &expr1,
4950 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4951 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4952 /* FIXME: If add_number is 0, and there was no base
4953 register, the external symbol case ended with a load,
4954 so if the symbol turns out to not be external, and
4955 the next instruction uses tempreg, an unnecessary nop
4956 will be inserted. */
4962 /* We must add in the base register now, as in the
4963 external symbol case. */
4964 assert (tempreg == AT);
4965 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
4967 macro_build (p, &icnt, (expressionS *) NULL,
4968 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4969 "d,v,t", treg, AT, breg);
4972 /* We set breg to 0 because we have arranged to add
4973 it in in both cases. */
4977 macro_build_lui (p, &icnt, &expr1, AT);
4979 macro_build (p, &icnt, &expr1,
4980 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4981 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
4983 macro_build (p, &icnt, (expressionS *) NULL,
4984 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4985 "d,v,t", tempreg, tempreg, AT);
4989 else if (mips_pic == EMBEDDED_PIC)
4992 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4994 macro_build ((char *) NULL, &icnt, &offset_expr,
4995 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j",
4996 tempreg, mips_gp_register, (int) BFD_RELOC_GPREL16);
5005 if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
5006 s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu";
5008 s = HAVE_64BIT_ADDRESSES ? "daddu" : "addu";
5010 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s,
5011 "d,v,t", treg, tempreg, breg);
5020 /* The j instruction may not be used in PIC code, since it
5021 requires an absolute address. We convert it to a b
5023 if (mips_pic == NO_PIC)
5024 macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a");
5026 macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p");
5029 /* The jal instructions must be handled as macros because when
5030 generating PIC code they expand to multi-instruction
5031 sequences. Normally they are simple instructions. */
5036 if (mips_pic == NO_PIC
5037 || mips_pic == EMBEDDED_PIC)
5038 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr",
5040 else if (mips_pic == SVR4_PIC)
5042 if (sreg != PIC_CALL_REG)
5043 as_warn (_("MIPS PIC call to register other than $25"));
5045 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr",
5049 if (mips_cprestore_offset < 0)
5050 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5053 if (! mips_frame_reg_valid)
5055 as_warn (_("No .frame pseudo-op used in PIC code"));
5056 /* Quiet this warning. */
5057 mips_frame_reg_valid = 1;
5059 if (! mips_cprestore_valid)
5061 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5062 /* Quiet this warning. */
5063 mips_cprestore_valid = 1;
5065 expr1.X_add_number = mips_cprestore_offset;
5066 macro_build ((char *) NULL, &icnt, &expr1,
5067 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)",
5068 mips_gp_register, (int) BFD_RELOC_LO16,
5079 if (mips_pic == NO_PIC)
5080 macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a");
5081 else if (mips_pic == SVR4_PIC)
5085 /* If this is a reference to an external symbol, and we are
5086 using a small GOT, we want
5087 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5091 lw $gp,cprestore($sp)
5092 The cprestore value is set using the .cprestore
5093 pseudo-op. If we are using a big GOT, we want
5094 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5096 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5100 lw $gp,cprestore($sp)
5101 If the symbol is not external, we want
5102 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5104 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5107 lw $gp,cprestore($sp)
5109 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5110 jalr $ra,$25 (BFD_RELOC_MIPS_JALR)
5114 macro_build ((char *) NULL, &icnt, &offset_expr,
5115 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5116 "t,o(b)", PIC_CALL_REG,
5117 (int) BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5118 macro_build_jalr (icnt, &offset_expr);
5125 macro_build ((char *) NULL, &icnt, &offset_expr,
5126 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5127 "t,o(b)", PIC_CALL_REG,
5128 (int) BFD_RELOC_MIPS_CALL16, mips_gp_register);
5129 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5131 p = frag_var (rs_machine_dependent, 4, 0,
5132 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5133 offset_expr.X_add_symbol, 0, NULL);
5139 if (reg_needs_delay (mips_gp_register))
5143 macro_build ((char *) NULL, &icnt, &offset_expr, "lui",
5144 "t,u", PIC_CALL_REG,
5145 (int) BFD_RELOC_MIPS_CALL_HI16);
5146 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5147 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5148 "d,v,t", PIC_CALL_REG, PIC_CALL_REG,
5150 macro_build ((char *) NULL, &icnt, &offset_expr,
5151 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5152 "t,o(b)", PIC_CALL_REG,
5153 (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
5154 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5156 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5157 RELAX_ENCODE (16, 12 + gpdel, gpdel,
5159 offset_expr.X_add_symbol, 0, NULL);
5162 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5165 macro_build (p, &icnt, &offset_expr,
5166 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5167 "t,o(b)", PIC_CALL_REG,
5168 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
5170 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5173 macro_build (p, &icnt, &offset_expr,
5174 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5175 "t,r,j", PIC_CALL_REG, PIC_CALL_REG,
5176 (int) BFD_RELOC_LO16);
5177 macro_build_jalr (icnt, &offset_expr);
5179 if (mips_cprestore_offset < 0)
5180 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5183 if (! mips_frame_reg_valid)
5185 as_warn (_("No .frame pseudo-op used in PIC code"));
5186 /* Quiet this warning. */
5187 mips_frame_reg_valid = 1;
5189 if (! mips_cprestore_valid)
5191 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5192 /* Quiet this warning. */
5193 mips_cprestore_valid = 1;
5195 if (mips_opts.noreorder)
5196 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5198 expr1.X_add_number = mips_cprestore_offset;
5199 macro_build ((char *) NULL, &icnt, &expr1,
5200 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)",
5201 mips_gp_register, (int) BFD_RELOC_LO16,
5206 else if (mips_pic == EMBEDDED_PIC)
5208 macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p");
5209 /* The linker may expand the call to a longer sequence which
5210 uses $at, so we must break rather than return. */
5235 /* Itbl support may require additional care here. */
5240 /* Itbl support may require additional care here. */
5245 /* Itbl support may require additional care here. */
5250 /* Itbl support may require additional care here. */
5262 if (mips_arch == CPU_R4650)
5264 as_bad (_("opcode not supported on this processor"));
5268 /* Itbl support may require additional care here. */
5273 /* Itbl support may require additional care here. */
5278 /* Itbl support may require additional care here. */
5298 if (breg == treg || coproc || lr)
5320 /* Itbl support may require additional care here. */
5325 /* Itbl support may require additional care here. */
5330 /* Itbl support may require additional care here. */
5335 /* Itbl support may require additional care here. */
5351 if (mips_arch == CPU_R4650)
5353 as_bad (_("opcode not supported on this processor"));
5358 /* Itbl support may require additional care here. */
5362 /* Itbl support may require additional care here. */
5367 /* Itbl support may require additional care here. */
5379 /* Itbl support may require additional care here. */
5380 if (mask == M_LWC1_AB
5381 || mask == M_SWC1_AB
5382 || mask == M_LDC1_AB
5383 || mask == M_SDC1_AB
5392 /* For embedded PIC, we allow loads where the offset is calculated
5393 by subtracting a symbol in the current segment from an unknown
5394 symbol, relative to a base register, e.g.:
5395 <op> $treg, <sym>-<localsym>($breg)
5396 This is used by the compiler for switch statements. */
5397 if (mips_pic == EMBEDDED_PIC
5398 && offset_expr.X_op == O_subtract
5399 && (symbol_constant_p (offset_expr.X_op_symbol)
5400 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
5401 : (symbol_equated_p (offset_expr.X_op_symbol)
5403 (symbol_get_value_expression (offset_expr.X_op_symbol)
5407 && (offset_expr.X_add_number == 0
5408 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
5410 /* For this case, we output the instructions:
5411 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5412 addiu $tempreg,$tempreg,$breg
5413 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5414 If the relocation would fit entirely in 16 bits, it would be
5416 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5417 instead, but that seems quite difficult. */
5418 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
5419 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
5420 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5421 ((bfd_arch_bits_per_address (stdoutput) == 32
5422 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
5423 ? "addu" : "daddu"),
5424 "d,v,t", tempreg, tempreg, breg);
5425 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, treg,
5426 (int) BFD_RELOC_PCREL_LO16, tempreg);
5432 if (offset_expr.X_op != O_constant
5433 && offset_expr.X_op != O_symbol)
5435 as_bad (_("expression too complex"));
5436 offset_expr.X_op = O_constant;
5439 /* A constant expression in PIC code can be handled just as it
5440 is in non PIC code. */
5441 if (mips_pic == NO_PIC
5442 || offset_expr.X_op == O_constant)
5446 /* If this is a reference to a GP relative symbol, and there
5447 is no base register, we want
5448 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5449 Otherwise, if there is no base register, we want
5450 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5451 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5452 If we have a constant, we need two instructions anyhow,
5453 so we always use the latter form.
5455 If we have a base register, and this is a reference to a
5456 GP relative symbol, we want
5457 addu $tempreg,$breg,$gp
5458 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5460 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5461 addu $tempreg,$tempreg,$breg
5462 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5463 With a constant we always use the latter case.
5465 With 64bit address space and no base register and $at usable,
5467 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5468 lui $at,<sym> (BFD_RELOC_HI16_S)
5469 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5472 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5473 If we have a base register, we want
5474 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5475 lui $at,<sym> (BFD_RELOC_HI16_S)
5476 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5480 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5482 Without $at we can't generate the optimal path for superscalar
5483 processors here since this would require two temporary registers.
5484 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5485 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5487 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5489 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5490 If we have a base register, we want
5491 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5492 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5494 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5496 daddu $tempreg,$tempreg,$breg
5497 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5499 If we have 64-bit addresses, as an optimization, for
5500 addresses which are 32-bit constants (e.g. kseg0/kseg1
5501 addresses) we fall back to the 32-bit address generation
5502 mechanism since it is more efficient. Note that due to
5503 the signed offset used by memory operations, the 32-bit
5504 range is shifted down by 32768 here. This code should
5505 probably attempt to generate 64-bit constants more
5506 efficiently in general.
5508 if (HAVE_64BIT_ADDRESSES
5509 && !(offset_expr.X_op == O_constant
5510 && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
5514 /* We don't do GP optimization for now because RELAX_ENCODE can't
5515 hold the data for such large chunks. */
5517 if (used_at == 0 && ! mips_opts.noat)
5519 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5520 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
5521 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5522 AT, (int) BFD_RELOC_HI16_S);
5523 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5524 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
5526 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
5527 "d,v,t", AT, AT, breg);
5528 macro_build (p, &icnt, (expressionS *) NULL, "dsll32",
5529 "d,w,<", tempreg, tempreg, 0);
5530 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
5531 "d,v,t", tempreg, tempreg, AT);
5532 macro_build (p, &icnt, &offset_expr, s,
5533 fmt, treg, (int) BFD_RELOC_LO16, tempreg);
5538 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5539 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
5540 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5541 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
5542 macro_build (p, &icnt, (expressionS *) NULL, "dsll",
5543 "d,w,<", tempreg, tempreg, 16);
5544 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5545 tempreg, tempreg, (int) BFD_RELOC_HI16_S);
5546 macro_build (p, &icnt, (expressionS *) NULL, "dsll",
5547 "d,w,<", tempreg, tempreg, 16);
5549 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
5550 "d,v,t", tempreg, tempreg, breg);
5551 macro_build (p, &icnt, &offset_expr, s,
5552 fmt, treg, (int) BFD_RELOC_LO16, tempreg);
5560 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
5561 || nopic_need_relax (offset_expr.X_add_symbol, 1))
5566 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5567 treg, (int) BFD_RELOC_GPREL16,
5569 p = frag_var (rs_machine_dependent, 8, 0,
5570 RELAX_ENCODE (4, 8, 0, 4, 0,
5571 (mips_opts.warn_about_macros
5573 && mips_opts.noat))),
5574 offset_expr.X_add_symbol, 0, NULL);
5577 macro_build_lui (p, &icnt, &offset_expr, tempreg);
5580 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
5581 (int) BFD_RELOC_LO16, tempreg);
5585 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
5586 || nopic_need_relax (offset_expr.X_add_symbol, 1))
5591 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5592 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5593 "d,v,t", tempreg, breg, mips_gp_register);
5594 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5595 treg, (int) BFD_RELOC_GPREL16, tempreg);
5596 p = frag_var (rs_machine_dependent, 12, 0,
5597 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5598 offset_expr.X_add_symbol, 0, NULL);
5600 macro_build_lui (p, &icnt, &offset_expr, tempreg);
5603 macro_build (p, &icnt, (expressionS *) NULL,
5604 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5605 "d,v,t", tempreg, tempreg, breg);
5608 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
5609 (int) BFD_RELOC_LO16, tempreg);
5612 else if (mips_pic == SVR4_PIC && ! mips_big_got)
5615 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5617 /* If this is a reference to an external symbol, we want
5618 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5620 <op> $treg,0($tempreg)
5622 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5624 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5625 <op> $treg,0($tempreg)
5626 If we have NewABI, we want
5627 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5628 If there is a base register, we add it to $tempreg before
5629 the <op>. If there is a constant, we stick it in the
5630 <op> instruction. We don't handle constants larger than
5631 16 bits, because we have no way to load the upper 16 bits
5632 (actually, we could handle them for the subset of cases
5633 in which we are not using $at). */
5634 assert (offset_expr.X_op == O_symbol);
5635 expr1.X_add_number = offset_expr.X_add_number;
5636 offset_expr.X_add_number = 0;
5638 lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_DISP;
5639 if (expr1.X_add_number < -0x8000
5640 || expr1.X_add_number >= 0x8000)
5641 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5643 macro_build ((char *) NULL, &icnt, &offset_expr,
5644 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", tempreg,
5645 (int) lw_reloc_type, mips_gp_register);
5646 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
5647 p = frag_var (rs_machine_dependent, 4, 0,
5648 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5649 offset_expr.X_add_symbol, 0, NULL);
5650 macro_build (p, &icnt, &offset_expr,
5651 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5652 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5654 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5655 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5656 "d,v,t", tempreg, tempreg, breg);
5657 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
5658 (int) BFD_RELOC_LO16, tempreg);
5660 else if (mips_pic == SVR4_PIC)
5665 /* If this is a reference to an external symbol, we want
5666 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5667 addu $tempreg,$tempreg,$gp
5668 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5669 <op> $treg,0($tempreg)
5671 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5673 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5674 <op> $treg,0($tempreg)
5675 If there is a base register, we add it to $tempreg before
5676 the <op>. If there is a constant, we stick it in the
5677 <op> instruction. We don't handle constants larger than
5678 16 bits, because we have no way to load the upper 16 bits
5679 (actually, we could handle them for the subset of cases
5680 in which we are not using $at).
5683 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5684 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5685 <op> $treg,0($tempreg)
5687 assert (offset_expr.X_op == O_symbol);
5688 expr1.X_add_number = offset_expr.X_add_number;
5689 offset_expr.X_add_number = 0;
5690 if (expr1.X_add_number < -0x8000
5691 || expr1.X_add_number >= 0x8000)
5692 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5695 macro_build ((char *) NULL, &icnt, &offset_expr,
5696 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5697 "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_PAGE,
5699 macro_build ((char *) NULL, &icnt, &offset_expr,
5700 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5701 "t,r,j", tempreg, tempreg,
5702 BFD_RELOC_MIPS_GOT_OFST);
5704 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5705 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5706 "d,v,t", tempreg, tempreg, breg);
5707 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
5708 (int) BFD_RELOC_LO16, tempreg);
5715 if (reg_needs_delay (mips_gp_register))
5720 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
5721 tempreg, (int) BFD_RELOC_MIPS_GOT_HI16);
5722 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5723 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5724 "d,v,t", tempreg, tempreg, mips_gp_register);
5725 macro_build ((char *) NULL, &icnt, &offset_expr,
5726 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5727 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16,
5729 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5730 RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0),
5731 offset_expr.X_add_symbol, 0, NULL);
5734 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5737 macro_build (p, &icnt, &offset_expr,
5738 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5739 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16,
5742 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5744 macro_build (p, &icnt, &offset_expr,
5745 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5746 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5748 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5749 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5750 "d,v,t", tempreg, tempreg, breg);
5751 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
5752 (int) BFD_RELOC_LO16, tempreg);
5754 else if (mips_pic == EMBEDDED_PIC)
5756 /* If there is no base register, we want
5757 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5758 If there is a base register, we want
5759 addu $tempreg,$breg,$gp
5760 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5762 assert (offset_expr.X_op == O_symbol);
5765 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5766 treg, (int) BFD_RELOC_GPREL16, mips_gp_register);
5771 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5772 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5773 "d,v,t", tempreg, breg, mips_gp_register);
5774 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5775 treg, (int) BFD_RELOC_GPREL16, tempreg);
5788 load_register (&icnt, treg, &imm_expr, 0);
5792 load_register (&icnt, treg, &imm_expr, 1);
5796 if (imm_expr.X_op == O_constant)
5798 load_register (&icnt, AT, &imm_expr, 0);
5799 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5800 "mtc1", "t,G", AT, treg);
5805 assert (offset_expr.X_op == O_symbol
5806 && strcmp (segment_name (S_GET_SEGMENT
5807 (offset_expr.X_add_symbol)),
5809 && offset_expr.X_add_number == 0);
5810 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
5811 treg, (int) BFD_RELOC_MIPS_LITERAL, mips_gp_register);
5816 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
5817 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
5818 order 32 bits of the value and the low order 32 bits are either
5819 zero or in OFFSET_EXPR. */
5820 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
5822 if (HAVE_64BIT_GPRS)
5823 load_register (&icnt, treg, &imm_expr, 1);
5828 if (target_big_endian)
5840 load_register (&icnt, hreg, &imm_expr, 0);
5843 if (offset_expr.X_op == O_absent)
5844 move_register (&icnt, lreg, 0);
5847 assert (offset_expr.X_op == O_constant);
5848 load_register (&icnt, lreg, &offset_expr, 0);
5855 /* We know that sym is in the .rdata section. First we get the
5856 upper 16 bits of the address. */
5857 if (mips_pic == NO_PIC)
5859 macro_build_lui (NULL, &icnt, &offset_expr, AT);
5861 else if (mips_pic == SVR4_PIC)
5863 macro_build ((char *) NULL, &icnt, &offset_expr,
5864 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5865 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
5868 else if (mips_pic == EMBEDDED_PIC)
5870 /* For embedded PIC we pick up the entire address off $gp in
5871 a single instruction. */
5872 macro_build ((char *) NULL, &icnt, &offset_expr,
5873 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j", AT,
5874 mips_gp_register, (int) BFD_RELOC_GPREL16);
5875 offset_expr.X_op = O_constant;
5876 offset_expr.X_add_number = 0;
5881 /* Now we load the register(s). */
5882 if (HAVE_64BIT_GPRS)
5883 macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)",
5884 treg, (int) BFD_RELOC_LO16, AT);
5887 macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)",
5888 treg, (int) BFD_RELOC_LO16, AT);
5891 /* FIXME: How in the world do we deal with the possible
5893 offset_expr.X_add_number += 4;
5894 macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)",
5895 treg + 1, (int) BFD_RELOC_LO16, AT);
5899 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5900 does not become a variant frag. */
5901 frag_wane (frag_now);
5907 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
5908 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
5909 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
5910 the value and the low order 32 bits are either zero or in
5912 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
5914 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS);
5915 if (HAVE_64BIT_FPRS)
5917 assert (HAVE_64BIT_GPRS);
5918 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5919 "dmtc1", "t,S", AT, treg);
5923 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5924 "mtc1", "t,G", AT, treg + 1);
5925 if (offset_expr.X_op == O_absent)
5926 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5927 "mtc1", "t,G", 0, treg);
5930 assert (offset_expr.X_op == O_constant);
5931 load_register (&icnt, AT, &offset_expr, 0);
5932 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5933 "mtc1", "t,G", AT, treg);
5939 assert (offset_expr.X_op == O_symbol
5940 && offset_expr.X_add_number == 0);
5941 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
5942 if (strcmp (s, ".lit8") == 0)
5944 if (mips_opts.isa != ISA_MIPS1)
5946 macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
5947 "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL,
5951 breg = mips_gp_register;
5952 r = BFD_RELOC_MIPS_LITERAL;
5957 assert (strcmp (s, RDATA_SECTION_NAME) == 0);
5958 if (mips_pic == SVR4_PIC)
5959 macro_build ((char *) NULL, &icnt, &offset_expr,
5960 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5961 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
5965 /* FIXME: This won't work for a 64 bit address. */
5966 macro_build_lui (NULL, &icnt, &offset_expr, AT);
5969 if (mips_opts.isa != ISA_MIPS1)
5971 macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
5972 "T,o(b)", treg, (int) BFD_RELOC_LO16, AT);
5974 /* To avoid confusion in tc_gen_reloc, we must ensure
5975 that this does not become a variant frag. */
5976 frag_wane (frag_now);
5987 if (mips_arch == CPU_R4650)
5989 as_bad (_("opcode not supported on this processor"));
5992 /* Even on a big endian machine $fn comes before $fn+1. We have
5993 to adjust when loading from memory. */
5996 assert (mips_opts.isa == ISA_MIPS1);
5997 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
5998 target_big_endian ? treg + 1 : treg,
6000 /* FIXME: A possible overflow which I don't know how to deal
6002 offset_expr.X_add_number += 4;
6003 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
6004 target_big_endian ? treg : treg + 1,
6007 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6008 does not become a variant frag. */
6009 frag_wane (frag_now);
6018 * The MIPS assembler seems to check for X_add_number not
6019 * being double aligned and generating:
6022 * addiu at,at,%lo(foo+1)
6025 * But, the resulting address is the same after relocation so why
6026 * generate the extra instruction?
6028 if (mips_arch == CPU_R4650)
6030 as_bad (_("opcode not supported on this processor"));
6033 /* Itbl support may require additional care here. */
6035 if (mips_opts.isa != ISA_MIPS1)
6046 if (mips_arch == CPU_R4650)
6048 as_bad (_("opcode not supported on this processor"));
6052 if (mips_opts.isa != ISA_MIPS1)
6060 /* Itbl support may require additional care here. */
6065 if (HAVE_64BIT_GPRS)
6076 if (HAVE_64BIT_GPRS)
6086 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6087 loads for the case of doing a pair of loads to simulate an 'ld'.
6088 This is not currently done by the compiler, and assembly coders
6089 writing embedded-pic code can cope. */
6091 if (offset_expr.X_op != O_symbol
6092 && offset_expr.X_op != O_constant)
6094 as_bad (_("expression too complex"));
6095 offset_expr.X_op = O_constant;
6098 /* Even on a big endian machine $fn comes before $fn+1. We have
6099 to adjust when loading from memory. We set coproc if we must
6100 load $fn+1 first. */
6101 /* Itbl support may require additional care here. */
6102 if (! target_big_endian)
6105 if (mips_pic == NO_PIC
6106 || offset_expr.X_op == O_constant)
6110 /* If this is a reference to a GP relative symbol, we want
6111 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6112 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6113 If we have a base register, we use this
6115 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6116 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6117 If this is not a GP relative symbol, we want
6118 lui $at,<sym> (BFD_RELOC_HI16_S)
6119 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6120 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6121 If there is a base register, we add it to $at after the
6122 lui instruction. If there is a constant, we always use
6124 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6125 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6137 tempreg = mips_gp_register;
6144 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6145 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6146 "d,v,t", AT, breg, mips_gp_register);
6152 /* Itbl support may require additional care here. */
6153 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6154 coproc ? treg + 1 : treg,
6155 (int) BFD_RELOC_GPREL16, tempreg);
6156 offset_expr.X_add_number += 4;
6158 /* Set mips_optimize to 2 to avoid inserting an
6160 hold_mips_optimize = mips_optimize;
6162 /* Itbl support may require additional care here. */
6163 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6164 coproc ? treg : treg + 1,
6165 (int) BFD_RELOC_GPREL16, tempreg);
6166 mips_optimize = hold_mips_optimize;
6168 p = frag_var (rs_machine_dependent, 12 + off, 0,
6169 RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1,
6170 used_at && mips_opts.noat),
6171 offset_expr.X_add_symbol, 0, NULL);
6173 /* We just generated two relocs. When tc_gen_reloc
6174 handles this case, it will skip the first reloc and
6175 handle the second. The second reloc already has an
6176 extra addend of 4, which we added above. We must
6177 subtract it out, and then subtract another 4 to make
6178 the first reloc come out right. The second reloc
6179 will come out right because we are going to add 4 to
6180 offset_expr when we build its instruction below.
6182 If we have a symbol, then we don't want to include
6183 the offset, because it will wind up being included
6184 when we generate the reloc. */
6186 if (offset_expr.X_op == O_constant)
6187 offset_expr.X_add_number -= 8;
6190 offset_expr.X_add_number = -4;
6191 offset_expr.X_op = O_constant;
6194 macro_build_lui (p, &icnt, &offset_expr, AT);
6199 macro_build (p, &icnt, (expressionS *) NULL,
6200 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6201 "d,v,t", AT, breg, AT);
6205 /* Itbl support may require additional care here. */
6206 macro_build (p, &icnt, &offset_expr, s, fmt,
6207 coproc ? treg + 1 : treg,
6208 (int) BFD_RELOC_LO16, AT);
6211 /* FIXME: How do we handle overflow here? */
6212 offset_expr.X_add_number += 4;
6213 /* Itbl support may require additional care here. */
6214 macro_build (p, &icnt, &offset_expr, s, fmt,
6215 coproc ? treg : treg + 1,
6216 (int) BFD_RELOC_LO16, AT);
6218 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6222 /* If this is a reference to an external symbol, we want
6223 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6228 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6230 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6231 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6232 If there is a base register we add it to $at before the
6233 lwc1 instructions. If there is a constant we include it
6234 in the lwc1 instructions. */
6236 expr1.X_add_number = offset_expr.X_add_number;
6237 offset_expr.X_add_number = 0;
6238 if (expr1.X_add_number < -0x8000
6239 || expr1.X_add_number >= 0x8000 - 4)
6240 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6245 frag_grow (24 + off);
6246 macro_build ((char *) NULL, &icnt, &offset_expr,
6247 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", AT,
6248 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
6249 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
6251 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6252 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6253 "d,v,t", AT, breg, AT);
6254 /* Itbl support may require additional care here. */
6255 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6256 coproc ? treg + 1 : treg,
6257 (int) BFD_RELOC_LO16, AT);
6258 expr1.X_add_number += 4;
6260 /* Set mips_optimize to 2 to avoid inserting an undesired
6262 hold_mips_optimize = mips_optimize;
6264 /* Itbl support may require additional care here. */
6265 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6266 coproc ? treg : treg + 1,
6267 (int) BFD_RELOC_LO16, AT);
6268 mips_optimize = hold_mips_optimize;
6270 (void) frag_var (rs_machine_dependent, 0, 0,
6271 RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0),
6272 offset_expr.X_add_symbol, 0, NULL);
6274 else if (mips_pic == SVR4_PIC)
6279 /* If this is a reference to an external symbol, we want
6280 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6282 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6287 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6289 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6290 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6291 If there is a base register we add it to $at before the
6292 lwc1 instructions. If there is a constant we include it
6293 in the lwc1 instructions. */
6295 expr1.X_add_number = offset_expr.X_add_number;
6296 offset_expr.X_add_number = 0;
6297 if (expr1.X_add_number < -0x8000
6298 || expr1.X_add_number >= 0x8000 - 4)
6299 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6300 if (reg_needs_delay (mips_gp_register))
6309 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
6310 AT, (int) BFD_RELOC_MIPS_GOT_HI16);
6311 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6312 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6313 "d,v,t", AT, AT, mips_gp_register);
6314 macro_build ((char *) NULL, &icnt, &offset_expr,
6315 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6316 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT);
6317 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
6319 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6320 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6321 "d,v,t", AT, breg, AT);
6322 /* Itbl support may require additional care here. */
6323 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6324 coproc ? treg + 1 : treg,
6325 (int) BFD_RELOC_LO16, AT);
6326 expr1.X_add_number += 4;
6328 /* Set mips_optimize to 2 to avoid inserting an undesired
6330 hold_mips_optimize = mips_optimize;
6332 /* Itbl support may require additional care here. */
6333 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6334 coproc ? treg : treg + 1,
6335 (int) BFD_RELOC_LO16, AT);
6336 mips_optimize = hold_mips_optimize;
6337 expr1.X_add_number -= 4;
6339 p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0,
6340 RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel,
6341 8 + gpdel + off, 1, 0),
6342 offset_expr.X_add_symbol, 0, NULL);
6345 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
6348 macro_build (p, &icnt, &offset_expr,
6349 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6350 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
6353 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
6357 macro_build (p, &icnt, (expressionS *) NULL,
6358 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6359 "d,v,t", AT, breg, AT);
6362 /* Itbl support may require additional care here. */
6363 macro_build (p, &icnt, &expr1, s, fmt,
6364 coproc ? treg + 1 : treg,
6365 (int) BFD_RELOC_LO16, AT);
6367 expr1.X_add_number += 4;
6369 /* Set mips_optimize to 2 to avoid inserting an undesired
6371 hold_mips_optimize = mips_optimize;
6373 /* Itbl support may require additional care here. */
6374 macro_build (p, &icnt, &expr1, s, fmt,
6375 coproc ? treg : treg + 1,
6376 (int) BFD_RELOC_LO16, AT);
6377 mips_optimize = hold_mips_optimize;
6379 else if (mips_pic == EMBEDDED_PIC)
6381 /* If there is no base register, we use
6382 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6383 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6384 If we have a base register, we use
6386 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6387 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6391 tempreg = mips_gp_register;
6396 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6397 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6398 "d,v,t", AT, breg, mips_gp_register);
6403 /* Itbl support may require additional care here. */
6404 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6405 coproc ? treg + 1 : treg,
6406 (int) BFD_RELOC_GPREL16, tempreg);
6407 offset_expr.X_add_number += 4;
6408 /* Itbl support may require additional care here. */
6409 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6410 coproc ? treg : treg + 1,
6411 (int) BFD_RELOC_GPREL16, tempreg);
6427 assert (HAVE_32BIT_ADDRESSES);
6428 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
6429 (int) BFD_RELOC_LO16, breg);
6430 offset_expr.X_add_number += 4;
6431 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1,
6432 (int) BFD_RELOC_LO16, breg);
6435 /* New code added to support COPZ instructions.
6436 This code builds table entries out of the macros in mip_opcodes.
6437 R4000 uses interlocks to handle coproc delays.
6438 Other chips (like the R3000) require nops to be inserted for delays.
6440 FIXME: Currently, we require that the user handle delays.
6441 In order to fill delay slots for non-interlocked chips,
6442 we must have a way to specify delays based on the coprocessor.
6443 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6444 What are the side-effects of the cop instruction?
6445 What cache support might we have and what are its effects?
6446 Both coprocessor & memory require delays. how long???
6447 What registers are read/set/modified?
6449 If an itbl is provided to interpret cop instructions,
6450 this knowledge can be encoded in the itbl spec. */
6464 /* For now we just do C (same as Cz). The parameter will be
6465 stored in insn_opcode by mips_ip. */
6466 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "C",
6471 move_register (&icnt, dreg, sreg);
6474 #ifdef LOSING_COMPILER
6476 /* Try and see if this is a new itbl instruction.
6477 This code builds table entries out of the macros in mip_opcodes.
6478 FIXME: For now we just assemble the expression and pass it's
6479 value along as a 32-bit immediate.
6480 We may want to have the assembler assemble this value,
6481 so that we gain the assembler's knowledge of delay slots,
6483 Would it be more efficient to use mask (id) here? */
6484 if (itbl_have_entries
6485 && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
6487 s = ip->insn_mo->name;
6489 coproc = ITBL_DECODE_PNUM (immed_expr);;
6490 macro_build ((char *) NULL, &icnt, &immed_expr, s, "C");
6497 as_warn (_("Macro used $at after \".set noat\""));
6502 struct mips_cl_insn *ip;
6504 register int treg, sreg, dreg, breg;
6520 bfd_reloc_code_real_type r;
6523 treg = (ip->insn_opcode >> 16) & 0x1f;
6524 dreg = (ip->insn_opcode >> 11) & 0x1f;
6525 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
6526 mask = ip->insn_mo->mask;
6528 expr1.X_op = O_constant;
6529 expr1.X_op_symbol = NULL;
6530 expr1.X_add_symbol = NULL;
6531 expr1.X_add_number = 1;
6535 #endif /* LOSING_COMPILER */
6540 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6541 dbl ? "dmultu" : "multu", "s,t", sreg, treg);
6542 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6549 /* The MIPS assembler some times generates shifts and adds. I'm
6550 not trying to be that fancy. GCC should do this for us
6552 load_register (&icnt, AT, &imm_expr, dbl);
6553 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6554 dbl ? "dmult" : "mult", "s,t", sreg, AT);
6555 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6569 mips_emit_delays (true);
6570 ++mips_opts.noreorder;
6571 mips_any_noreorder = 1;
6573 load_register (&icnt, AT, &imm_expr, dbl);
6574 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6575 dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
6576 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6578 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6579 dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
6580 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d",
6583 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne",
6584 "s,t,q", dreg, AT, 6);
6587 expr1.X_add_number = 8;
6588 macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg,
6590 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
6592 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
6595 --mips_opts.noreorder;
6596 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", dreg);
6609 mips_emit_delays (true);
6610 ++mips_opts.noreorder;
6611 mips_any_noreorder = 1;
6613 load_register (&icnt, AT, &imm_expr, dbl);
6614 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6615 dbl ? "dmultu" : "multu",
6616 "s,t", sreg, imm ? AT : treg);
6617 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d",
6619 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6622 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne",
6626 expr1.X_add_number = 8;
6627 macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0);
6628 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
6630 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
6633 --mips_opts.noreorder;
6637 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
6638 "d,v,t", AT, 0, treg);
6639 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
6640 "d,t,s", AT, sreg, AT);
6641 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
6642 "d,t,s", dreg, sreg, treg);
6643 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6644 "d,v,t", dreg, dreg, AT);
6648 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
6649 "d,v,t", AT, 0, treg);
6650 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv",
6651 "d,t,s", AT, sreg, AT);
6652 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv",
6653 "d,t,s", dreg, sreg, treg);
6654 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6655 "d,v,t", dreg, dreg, AT);
6662 if (imm_expr.X_op != O_constant)
6663 as_bad (_("rotate count too large"));
6664 rot = imm_expr.X_add_number & 0x3f;
6666 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrl",
6667 "d,w,<", dreg, sreg, 0);
6672 l = (rot < 0x20) ? "dsll" : "dsll32";
6673 r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
6675 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
6676 "d,w,<", AT, sreg, rot);
6677 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
6678 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6679 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6680 "d,v,t", dreg, dreg, AT);
6689 if (imm_expr.X_op != O_constant)
6690 as_bad (_("rotate count too large"));
6691 rot = imm_expr.X_add_number & 0x1f;
6693 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
6694 "d,w,<", dreg, sreg, 0);
6697 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
6698 "d,w,<", AT, sreg, rot);
6699 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
6700 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6701 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6702 "d,v,t", dreg, dreg, AT);
6708 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
6709 "d,v,t", AT, 0, treg);
6710 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
6711 "d,t,s", AT, sreg, AT);
6712 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
6713 "d,t,s", dreg, sreg, treg);
6714 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6715 "d,v,t", dreg, dreg, AT);
6719 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
6720 "d,v,t", AT, 0, treg);
6721 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv",
6722 "d,t,s", AT, sreg, AT);
6723 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv",
6724 "d,t,s", dreg, sreg, treg);
6725 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6726 "d,v,t", dreg, dreg, AT);
6733 if (imm_expr.X_op != O_constant)
6734 as_bad (_("rotate count too large"));
6735 rot = imm_expr.X_add_number & 0x3f;
6737 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrl",
6738 "d,w,<", dreg, sreg, 0);
6743 r = (rot < 0x20) ? "dsrl" : "dsrl32";
6744 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
6746 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
6747 "d,w,<", AT, sreg, rot);
6748 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
6749 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6750 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6751 "d,v,t", dreg, dreg, AT);
6760 if (imm_expr.X_op != O_constant)
6761 as_bad (_("rotate count too large"));
6762 rot = imm_expr.X_add_number & 0x1f;
6764 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
6765 "d,w,<", dreg, sreg, 0);
6768 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
6769 "d,w,<", AT, sreg, rot);
6770 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
6771 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6772 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6773 "d,v,t", dreg, dreg, AT);
6779 if (mips_arch == CPU_R4650)
6781 as_bad (_("opcode not supported on this processor"));
6784 assert (mips_opts.isa == ISA_MIPS1);
6785 /* Even on a big endian machine $fn comes before $fn+1. We have
6786 to adjust when storing to memory. */
6787 macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
6788 target_big_endian ? treg + 1 : treg,
6789 (int) BFD_RELOC_LO16, breg);
6790 offset_expr.X_add_number += 4;
6791 macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
6792 target_big_endian ? treg : treg + 1,
6793 (int) BFD_RELOC_LO16, breg);
6798 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6799 treg, (int) BFD_RELOC_LO16);
6801 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6802 sreg, (int) BFD_RELOC_LO16);
6805 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
6806 "d,v,t", dreg, sreg, treg);
6807 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6808 dreg, (int) BFD_RELOC_LO16);
6813 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6815 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6816 sreg, (int) BFD_RELOC_LO16);
6821 as_warn (_("Instruction %s: result is always false"),
6823 move_register (&icnt, dreg, 0);
6826 if (imm_expr.X_op == O_constant
6827 && imm_expr.X_add_number >= 0
6828 && imm_expr.X_add_number < 0x10000)
6830 macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg,
6831 sreg, (int) BFD_RELOC_LO16);
6834 else if (imm_expr.X_op == O_constant
6835 && imm_expr.X_add_number > -0x8000
6836 && imm_expr.X_add_number < 0)
6838 imm_expr.X_add_number = -imm_expr.X_add_number;
6839 macro_build ((char *) NULL, &icnt, &imm_expr,
6840 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
6841 "t,r,j", dreg, sreg,
6842 (int) BFD_RELOC_LO16);
6847 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6848 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
6849 "d,v,t", dreg, sreg, AT);
6852 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg,
6853 (int) BFD_RELOC_LO16);
6858 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
6864 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6866 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6867 (int) BFD_RELOC_LO16);
6870 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
6872 if (imm_expr.X_op == O_constant
6873 && imm_expr.X_add_number >= -0x8000
6874 && imm_expr.X_add_number < 0x8000)
6876 macro_build ((char *) NULL, &icnt, &imm_expr,
6877 mask == M_SGE_I ? "slti" : "sltiu",
6878 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
6883 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6884 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6885 mask == M_SGE_I ? "slt" : "sltu", "d,v,t", dreg, sreg,
6889 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6890 (int) BFD_RELOC_LO16);
6895 case M_SGT: /* sreg > treg <==> treg < sreg */
6901 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6905 case M_SGT_I: /* sreg > I <==> I < sreg */
6911 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6912 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6916 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6922 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6924 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6925 (int) BFD_RELOC_LO16);
6928 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6934 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6935 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6937 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6938 (int) BFD_RELOC_LO16);
6942 if (imm_expr.X_op == O_constant
6943 && imm_expr.X_add_number >= -0x8000
6944 && imm_expr.X_add_number < 0x8000)
6946 macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j",
6947 dreg, sreg, (int) BFD_RELOC_LO16);
6950 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6951 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
6956 if (imm_expr.X_op == O_constant
6957 && imm_expr.X_add_number >= -0x8000
6958 && imm_expr.X_add_number < 0x8000)
6960 macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j",
6961 dreg, sreg, (int) BFD_RELOC_LO16);
6964 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6965 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6966 "d,v,t", dreg, sreg, AT);
6971 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6972 "d,v,t", dreg, 0, treg);
6974 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6975 "d,v,t", dreg, 0, sreg);
6978 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
6979 "d,v,t", dreg, sreg, treg);
6980 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6981 "d,v,t", dreg, 0, dreg);
6986 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6988 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6989 "d,v,t", dreg, 0, sreg);
6994 as_warn (_("Instruction %s: result is always true"),
6996 macro_build ((char *) NULL, &icnt, &expr1,
6997 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
6998 "t,r,j", dreg, 0, (int) BFD_RELOC_LO16);
7001 if (imm_expr.X_op == O_constant
7002 && imm_expr.X_add_number >= 0
7003 && imm_expr.X_add_number < 0x10000)
7005 macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i",
7006 dreg, sreg, (int) BFD_RELOC_LO16);
7009 else if (imm_expr.X_op == O_constant
7010 && imm_expr.X_add_number > -0x8000
7011 && imm_expr.X_add_number < 0)
7013 imm_expr.X_add_number = -imm_expr.X_add_number;
7014 macro_build ((char *) NULL, &icnt, &imm_expr,
7015 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7016 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
7021 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7022 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
7023 "d,v,t", dreg, sreg, AT);
7026 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
7027 "d,v,t", dreg, 0, dreg);
7035 if (imm_expr.X_op == O_constant
7036 && imm_expr.X_add_number > -0x8000
7037 && imm_expr.X_add_number <= 0x8000)
7039 imm_expr.X_add_number = -imm_expr.X_add_number;
7040 macro_build ((char *) NULL, &icnt, &imm_expr,
7041 dbl ? "daddi" : "addi",
7042 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
7045 load_register (&icnt, AT, &imm_expr, dbl);
7046 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7047 dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
7053 if (imm_expr.X_op == O_constant
7054 && imm_expr.X_add_number > -0x8000
7055 && imm_expr.X_add_number <= 0x8000)
7057 imm_expr.X_add_number = -imm_expr.X_add_number;
7058 macro_build ((char *) NULL, &icnt, &imm_expr,
7059 dbl ? "daddiu" : "addiu",
7060 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
7063 load_register (&icnt, AT, &imm_expr, dbl);
7064 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7065 dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
7086 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7087 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "s,t", sreg,
7093 assert (mips_opts.isa == ISA_MIPS1);
7094 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
7095 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
7098 * Is the double cfc1 instruction a bug in the mips assembler;
7099 * or is there a reason for it?
7101 mips_emit_delays (true);
7102 ++mips_opts.noreorder;
7103 mips_any_noreorder = 1;
7104 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G",
7106 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G",
7108 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7109 expr1.X_add_number = 3;
7110 macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg,
7111 (int) BFD_RELOC_LO16);
7112 expr1.X_add_number = 2;
7113 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT,
7114 (int) BFD_RELOC_LO16);
7115 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G",
7117 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7118 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7119 mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg);
7120 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G",
7122 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7123 --mips_opts.noreorder;
7132 if (offset_expr.X_add_number >= 0x7fff)
7133 as_bad (_("operand overflow"));
7134 /* avoid load delay */
7135 if (! target_big_endian)
7136 ++offset_expr.X_add_number;
7137 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7138 (int) BFD_RELOC_LO16, breg);
7139 if (! target_big_endian)
7140 --offset_expr.X_add_number;
7142 ++offset_expr.X_add_number;
7143 macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT,
7144 (int) BFD_RELOC_LO16, breg);
7145 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7147 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7161 if (offset_expr.X_add_number >= 0x8000 - off)
7162 as_bad (_("operand overflow"));
7163 if (! target_big_endian)
7164 offset_expr.X_add_number += off;
7165 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7166 (int) BFD_RELOC_LO16, breg);
7167 if (! target_big_endian)
7168 offset_expr.X_add_number -= off;
7170 offset_expr.X_add_number += off;
7171 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
7172 (int) BFD_RELOC_LO16, breg);
7186 load_address (&icnt, AT, &offset_expr, &used_at);
7188 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7189 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7190 "d,v,t", AT, AT, breg);
7191 if (! target_big_endian)
7192 expr1.X_add_number = off;
7194 expr1.X_add_number = 0;
7195 macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg,
7196 (int) BFD_RELOC_LO16, AT);
7197 if (! target_big_endian)
7198 expr1.X_add_number = 0;
7200 expr1.X_add_number = off;
7201 macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7202 (int) BFD_RELOC_LO16, AT);
7208 load_address (&icnt, AT, &offset_expr, &used_at);
7210 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7211 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7212 "d,v,t", AT, AT, breg);
7213 if (target_big_endian)
7214 expr1.X_add_number = 0;
7215 macro_build ((char *) NULL, &icnt, &expr1,
7216 mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg,
7217 (int) BFD_RELOC_LO16, AT);
7218 if (target_big_endian)
7219 expr1.X_add_number = 1;
7221 expr1.X_add_number = 0;
7222 macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
7223 (int) BFD_RELOC_LO16, AT);
7224 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7226 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7231 if (offset_expr.X_add_number >= 0x7fff)
7232 as_bad (_("operand overflow"));
7233 if (target_big_endian)
7234 ++offset_expr.X_add_number;
7235 macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg,
7236 (int) BFD_RELOC_LO16, breg);
7237 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
7239 if (target_big_endian)
7240 --offset_expr.X_add_number;
7242 ++offset_expr.X_add_number;
7243 macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT,
7244 (int) BFD_RELOC_LO16, breg);
7257 if (offset_expr.X_add_number >= 0x8000 - off)
7258 as_bad (_("operand overflow"));
7259 if (! target_big_endian)
7260 offset_expr.X_add_number += off;
7261 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7262 (int) BFD_RELOC_LO16, breg);
7263 if (! target_big_endian)
7264 offset_expr.X_add_number -= off;
7266 offset_expr.X_add_number += off;
7267 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
7268 (int) BFD_RELOC_LO16, breg);
7282 load_address (&icnt, AT, &offset_expr, &used_at);
7284 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7285 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7286 "d,v,t", AT, AT, breg);
7287 if (! target_big_endian)
7288 expr1.X_add_number = off;
7290 expr1.X_add_number = 0;
7291 macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg,
7292 (int) BFD_RELOC_LO16, AT);
7293 if (! target_big_endian)
7294 expr1.X_add_number = 0;
7296 expr1.X_add_number = off;
7297 macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7298 (int) BFD_RELOC_LO16, AT);
7303 load_address (&icnt, AT, &offset_expr, &used_at);
7305 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7306 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7307 "d,v,t", AT, AT, breg);
7308 if (! target_big_endian)
7309 expr1.X_add_number = 0;
7310 macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7311 (int) BFD_RELOC_LO16, AT);
7312 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
7314 if (! target_big_endian)
7315 expr1.X_add_number = 1;
7317 expr1.X_add_number = 0;
7318 macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7319 (int) BFD_RELOC_LO16, AT);
7320 if (! target_big_endian)
7321 expr1.X_add_number = 0;
7323 expr1.X_add_number = 1;
7324 macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
7325 (int) BFD_RELOC_LO16, AT);
7326 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7328 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7333 /* FIXME: Check if this is one of the itbl macros, since they
7334 are added dynamically. */
7335 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
7339 as_warn (_("Macro used $at after \".set noat\""));
7342 /* Implement macros in mips16 mode. */
7346 struct mips_cl_insn *ip;
7349 int xreg, yreg, zreg, tmp;
7353 const char *s, *s2, *s3;
7355 mask = ip->insn_mo->mask;
7357 xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
7358 yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY;
7359 zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
7363 expr1.X_op = O_constant;
7364 expr1.X_op_symbol = NULL;
7365 expr1.X_add_symbol = NULL;
7366 expr1.X_add_number = 1;
7385 mips_emit_delays (true);
7386 ++mips_opts.noreorder;
7387 mips_any_noreorder = 1;
7388 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7389 dbl ? "ddiv" : "div",
7390 "0,x,y", xreg, yreg);
7391 expr1.X_add_number = 2;
7392 macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg);
7393 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", "6",
7396 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7397 since that causes an overflow. We should do that as well,
7398 but I don't see how to do the comparisons without a temporary
7400 --mips_opts.noreorder;
7401 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x", zreg);
7420 mips_emit_delays (true);
7421 ++mips_opts.noreorder;
7422 mips_any_noreorder = 1;
7423 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "0,x,y",
7425 expr1.X_add_number = 2;
7426 macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg);
7427 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
7429 --mips_opts.noreorder;
7430 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "x", zreg);
7436 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7437 dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
7438 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "x",
7447 if (imm_expr.X_op != O_constant)
7448 as_bad (_("Unsupported large constant"));
7449 imm_expr.X_add_number = -imm_expr.X_add_number;
7450 macro_build ((char *) NULL, &icnt, &imm_expr,
7451 dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
7455 if (imm_expr.X_op != O_constant)
7456 as_bad (_("Unsupported large constant"));
7457 imm_expr.X_add_number = -imm_expr.X_add_number;
7458 macro_build ((char *) NULL, &icnt, &imm_expr, "addiu",
7463 if (imm_expr.X_op != O_constant)
7464 as_bad (_("Unsupported large constant"));
7465 imm_expr.X_add_number = -imm_expr.X_add_number;
7466 macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu",
7489 goto do_reverse_branch;
7493 goto do_reverse_branch;
7505 goto do_reverse_branch;
7516 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y",
7518 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p");
7545 goto do_addone_branch_i;
7550 goto do_addone_branch_i;
7565 goto do_addone_branch_i;
7572 if (imm_expr.X_op != O_constant)
7573 as_bad (_("Unsupported large constant"));
7574 ++imm_expr.X_add_number;
7577 macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg);
7578 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p");
7582 expr1.X_add_number = 0;
7583 macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg);
7585 move_register (&icnt, xreg, yreg);
7586 expr1.X_add_number = 2;
7587 macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p");
7588 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7589 "neg", "x,w", xreg, xreg);
7593 /* For consistency checking, verify that all bits are specified either
7594 by the match/mask part of the instruction definition, or by the
7597 validate_mips_insn (opc)
7598 const struct mips_opcode *opc;
7600 const char *p = opc->args;
7602 unsigned long used_bits = opc->mask;
7604 if ((used_bits & opc->match) != opc->match)
7606 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7607 opc->name, opc->args);
7610 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7617 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7618 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7620 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
7621 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
7622 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
7623 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7625 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7626 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
7628 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
7630 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
7631 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
7632 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
7633 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
7634 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7635 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
7636 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7637 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7638 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7639 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7640 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
7641 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7642 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7643 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
7644 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7645 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
7646 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7648 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
7649 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
7650 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7651 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
7653 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7654 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7655 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
7656 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7657 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7658 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7659 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
7660 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7661 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7664 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
7665 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
7666 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7668 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7669 c, opc->name, opc->args);
7673 if (used_bits != 0xffffffff)
7675 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7676 ~used_bits & 0xffffffff, opc->name, opc->args);
7682 /* This routine assembles an instruction into its binary format. As a
7683 side effect, it sets one of the global variables imm_reloc or
7684 offset_reloc to the type of relocation to do if one of the operands
7685 is an address expression. */
7690 struct mips_cl_insn *ip;
7695 struct mips_opcode *insn;
7698 unsigned int lastregno = 0;
7704 /* If the instruction contains a '.', we first try to match an instruction
7705 including the '.'. Then we try again without the '.'. */
7707 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
7710 /* If we stopped on whitespace, then replace the whitespace with null for
7711 the call to hash_find. Save the character we replaced just in case we
7712 have to re-parse the instruction. */
7719 insn = (struct mips_opcode *) hash_find (op_hash, str);
7721 /* If we didn't find the instruction in the opcode table, try again, but
7722 this time with just the instruction up to, but not including the
7726 /* Restore the character we overwrite above (if any). */
7730 /* Scan up to the first '.' or whitespace. */
7732 *s != '\0' && *s != '.' && !ISSPACE (*s);
7736 /* If we did not find a '.', then we can quit now. */
7739 insn_error = "unrecognized opcode";
7743 /* Lookup the instruction in the hash table. */
7745 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
7747 insn_error = "unrecognized opcode";
7757 assert (strcmp (insn->name, str) == 0);
7759 if (OPCODE_IS_MEMBER (insn,
7761 | (mips_opts.mips16 ? INSN_MIPS16 : 0)
7762 | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
7763 | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
7769 if (insn->pinfo != INSN_MACRO)
7771 if (mips_arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)
7777 if (insn + 1 < &mips_opcodes[NUMOPCODES]
7778 && strcmp (insn->name, insn[1].name) == 0)
7787 static char buf[100];
7788 if (mips_arch_info->is_isa)
7790 _("opcode not supported at this ISA level (%s)"),
7791 mips_cpu_info_from_isa (mips_opts.isa)->name);
7794 _("opcode not supported on this processor: %s (%s)"),
7795 mips_arch_info->name,
7796 mips_cpu_info_from_isa (mips_opts.isa)->name);
7806 ip->insn_opcode = insn->match;
7808 for (args = insn->args;; ++args)
7812 s += strspn (s, " \t");
7816 case '\0': /* end of args */
7829 ip->insn_opcode |= lastregno << OP_SH_RS;
7833 ip->insn_opcode |= lastregno << OP_SH_RT;
7837 ip->insn_opcode |= lastregno << OP_SH_FT;
7841 ip->insn_opcode |= lastregno << OP_SH_FS;
7847 /* Handle optional base register.
7848 Either the base register is omitted or
7849 we must have a left paren. */
7850 /* This is dependent on the next operand specifier
7851 is a base register specification. */
7852 assert (args[1] == 'b' || args[1] == '5'
7853 || args[1] == '-' || args[1] == '4');
7857 case ')': /* these must match exactly */
7862 case '<': /* must be at least one digit */
7864 * According to the manual, if the shift amount is greater
7865 * than 31 or less than 0, then the shift amount should be
7866 * mod 32. In reality the mips assembler issues an error.
7867 * We issue a warning and mask out all but the low 5 bits.
7869 my_getExpression (&imm_expr, s);
7870 check_absolute_expr (ip, &imm_expr);
7871 if ((unsigned long) imm_expr.X_add_number > 31)
7873 as_warn (_("Improper shift amount (%lu)"),
7874 (unsigned long) imm_expr.X_add_number);
7875 imm_expr.X_add_number &= OP_MASK_SHAMT;
7877 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT;
7878 imm_expr.X_op = O_absent;
7882 case '>': /* shift amount minus 32 */
7883 my_getExpression (&imm_expr, s);
7884 check_absolute_expr (ip, &imm_expr);
7885 if ((unsigned long) imm_expr.X_add_number < 32
7886 || (unsigned long) imm_expr.X_add_number > 63)
7888 ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT;
7889 imm_expr.X_op = O_absent;
7893 case 'k': /* cache code */
7894 case 'h': /* prefx code */
7895 my_getExpression (&imm_expr, s);
7896 check_absolute_expr (ip, &imm_expr);
7897 if ((unsigned long) imm_expr.X_add_number > 31)
7899 as_warn (_("Invalid value for `%s' (%lu)"),
7901 (unsigned long) imm_expr.X_add_number);
7902 imm_expr.X_add_number &= 0x1f;
7905 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE;
7907 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX;
7908 imm_expr.X_op = O_absent;
7912 case 'c': /* break code */
7913 my_getExpression (&imm_expr, s);
7914 check_absolute_expr (ip, &imm_expr);
7915 if ((unsigned long) imm_expr.X_add_number > 1023)
7917 as_warn (_("Illegal break code (%lu)"),
7918 (unsigned long) imm_expr.X_add_number);
7919 imm_expr.X_add_number &= OP_MASK_CODE;
7921 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE;
7922 imm_expr.X_op = O_absent;
7926 case 'q': /* lower break code */
7927 my_getExpression (&imm_expr, s);
7928 check_absolute_expr (ip, &imm_expr);
7929 if ((unsigned long) imm_expr.X_add_number > 1023)
7931 as_warn (_("Illegal lower break code (%lu)"),
7932 (unsigned long) imm_expr.X_add_number);
7933 imm_expr.X_add_number &= OP_MASK_CODE2;
7935 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2;
7936 imm_expr.X_op = O_absent;
7940 case 'B': /* 20-bit syscall/break code. */
7941 my_getExpression (&imm_expr, s);
7942 check_absolute_expr (ip, &imm_expr);
7943 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
7944 as_warn (_("Illegal 20-bit code (%lu)"),
7945 (unsigned long) imm_expr.X_add_number);
7946 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20;
7947 imm_expr.X_op = O_absent;
7951 case 'C': /* Coprocessor code */
7952 my_getExpression (&imm_expr, s);
7953 check_absolute_expr (ip, &imm_expr);
7954 if ((unsigned long) imm_expr.X_add_number >= (1 << 25))
7956 as_warn (_("Coproccesor code > 25 bits (%lu)"),
7957 (unsigned long) imm_expr.X_add_number);
7958 imm_expr.X_add_number &= ((1 << 25) - 1);
7960 ip->insn_opcode |= imm_expr.X_add_number;
7961 imm_expr.X_op = O_absent;
7965 case 'J': /* 19-bit wait code. */
7966 my_getExpression (&imm_expr, s);
7967 check_absolute_expr (ip, &imm_expr);
7968 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
7969 as_warn (_("Illegal 19-bit code (%lu)"),
7970 (unsigned long) imm_expr.X_add_number);
7971 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19;
7972 imm_expr.X_op = O_absent;
7976 case 'P': /* Performance register */
7977 my_getExpression (&imm_expr, s);
7978 check_absolute_expr (ip, &imm_expr);
7979 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
7981 as_warn (_("Invalid performance register (%lu)"),
7982 (unsigned long) imm_expr.X_add_number);
7983 imm_expr.X_add_number &= OP_MASK_PERFREG;
7985 ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG);
7986 imm_expr.X_op = O_absent;
7990 case 'b': /* base register */
7991 case 'd': /* destination register */
7992 case 's': /* source register */
7993 case 't': /* target register */
7994 case 'r': /* both target and source */
7995 case 'v': /* both dest and source */
7996 case 'w': /* both dest and target */
7997 case 'E': /* coprocessor target register */
7998 case 'G': /* coprocessor destination register */
7999 case 'x': /* ignore register name */
8000 case 'z': /* must be zero register */
8001 case 'U': /* destination register (clo/clz). */
8016 while (ISDIGIT (*s));
8018 as_bad (_("Invalid register number (%d)"), regno);
8020 else if (*args == 'E' || *args == 'G')
8024 if (s[1] == 'r' && s[2] == 'a')
8029 else if (s[1] == 'f' && s[2] == 'p')
8034 else if (s[1] == 's' && s[2] == 'p')
8039 else if (s[1] == 'g' && s[2] == 'p')
8044 else if (s[1] == 'a' && s[2] == 't')
8049 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
8054 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
8059 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
8064 else if (itbl_have_entries)
8069 p = s + 1; /* advance past '$' */
8070 n = itbl_get_field (&p); /* n is name */
8072 /* See if this is a register defined in an
8074 if (itbl_get_reg_val (n, &r))
8076 /* Get_field advances to the start of
8077 the next field, so we need to back
8078 rack to the end of the last field. */
8082 s = strchr (s, '\0');
8095 as_warn (_("Used $at without \".set noat\""));
8101 if (c == 'r' || c == 'v' || c == 'w')
8108 /* 'z' only matches $0. */
8109 if (c == 'z' && regno != 0)
8112 /* Now that we have assembled one operand, we use the args string
8113 * to figure out where it goes in the instruction. */
8120 ip->insn_opcode |= regno << OP_SH_RS;
8124 ip->insn_opcode |= regno << OP_SH_RD;
8127 ip->insn_opcode |= regno << OP_SH_RD;
8128 ip->insn_opcode |= regno << OP_SH_RT;
8133 ip->insn_opcode |= regno << OP_SH_RT;
8136 /* This case exists because on the r3000 trunc
8137 expands into a macro which requires a gp
8138 register. On the r6000 or r4000 it is
8139 assembled into a single instruction which
8140 ignores the register. Thus the insn version
8141 is MIPS_ISA2 and uses 'x', and the macro
8142 version is MIPS_ISA1 and uses 't'. */
8145 /* This case is for the div instruction, which
8146 acts differently if the destination argument
8147 is $0. This only matches $0, and is checked
8148 outside the switch. */
8151 /* Itbl operand; not yet implemented. FIXME ?? */
8153 /* What about all other operands like 'i', which
8154 can be specified in the opcode table? */
8164 ip->insn_opcode |= lastregno << OP_SH_RS;
8167 ip->insn_opcode |= lastregno << OP_SH_RT;
8172 case 'O': /* MDMX alignment immediate constant. */
8173 my_getExpression (&imm_expr, s);
8174 check_absolute_expr (ip, &imm_expr);
8175 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
8177 as_warn ("Improper align amount (%ld), using low bits",
8178 (long) imm_expr.X_add_number);
8179 imm_expr.X_add_number &= OP_MASK_ALN;
8181 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN;
8182 imm_expr.X_op = O_absent;
8186 case 'Q': /* MDMX vector, element sel, or const. */
8189 /* MDMX Immediate. */
8190 my_getExpression (&imm_expr, s);
8191 check_absolute_expr (ip, &imm_expr);
8192 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
8194 as_warn (_("Invalid MDMX Immediate (%ld)"),
8195 (long) imm_expr.X_add_number);
8196 imm_expr.X_add_number &= OP_MASK_FT;
8198 imm_expr.X_add_number &= OP_MASK_FT;
8199 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8200 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
8202 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
8203 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT;
8204 imm_expr.X_op = O_absent;
8208 /* Not MDMX Immediate. Fall through. */
8209 case 'X': /* MDMX destination register. */
8210 case 'Y': /* MDMX source register. */
8211 case 'Z': /* MDMX target register. */
8213 case 'D': /* floating point destination register */
8214 case 'S': /* floating point source register */
8215 case 'T': /* floating point target register */
8216 case 'R': /* floating point source register */
8220 /* Accept $fN for FP and MDMX register numbers, and in
8221 addition accept $vN for MDMX register numbers. */
8222 if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2]))
8223 || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v'
8234 while (ISDIGIT (*s));
8237 as_bad (_("Invalid float register number (%d)"), regno);
8239 if ((regno & 1) != 0
8241 && ! (strcmp (str, "mtc1") == 0
8242 || strcmp (str, "mfc1") == 0
8243 || strcmp (str, "lwc1") == 0
8244 || strcmp (str, "swc1") == 0
8245 || strcmp (str, "l.s") == 0
8246 || strcmp (str, "s.s") == 0))
8247 as_warn (_("Float register should be even, was %d"),
8255 if (c == 'V' || c == 'W')
8266 ip->insn_opcode |= regno << OP_SH_FD;
8271 ip->insn_opcode |= regno << OP_SH_FS;
8274 /* This is like 'Z', but also needs to fix the MDMX
8275 vector/scalar select bits. Note that the
8276 scalar immediate case is handled above. */
8279 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
8280 int max_el = (is_qh ? 3 : 7);
8282 my_getExpression(&imm_expr, s);
8283 check_absolute_expr (ip, &imm_expr);
8285 if (imm_expr.X_add_number > max_el)
8286 as_bad(_("Bad element selector %ld"),
8287 (long) imm_expr.X_add_number);
8288 imm_expr.X_add_number &= max_el;
8289 ip->insn_opcode |= (imm_expr.X_add_number
8293 as_warn(_("Expecting ']' found '%s'"), s);
8299 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8300 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
8303 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
8310 ip->insn_opcode |= regno << OP_SH_FT;
8313 ip->insn_opcode |= regno << OP_SH_FR;
8323 ip->insn_opcode |= lastregno << OP_SH_FS;
8326 ip->insn_opcode |= lastregno << OP_SH_FT;
8332 my_getExpression (&imm_expr, s);
8333 if (imm_expr.X_op != O_big
8334 && imm_expr.X_op != O_constant)
8335 insn_error = _("absolute expression required");
8340 my_getExpression (&offset_expr, s);
8341 *imm_reloc = BFD_RELOC_32;
8354 unsigned char temp[8];
8356 unsigned int length;
8361 /* These only appear as the last operand in an
8362 instruction, and every instruction that accepts
8363 them in any variant accepts them in all variants.
8364 This means we don't have to worry about backing out
8365 any changes if the instruction does not match.
8367 The difference between them is the size of the
8368 floating point constant and where it goes. For 'F'
8369 and 'L' the constant is 64 bits; for 'f' and 'l' it
8370 is 32 bits. Where the constant is placed is based
8371 on how the MIPS assembler does things:
8374 f -- immediate value
8377 The .lit4 and .lit8 sections are only used if
8378 permitted by the -G argument.
8380 When generating embedded PIC code, we use the
8381 .lit8 section but not the .lit4 section (we can do
8382 .lit4 inline easily; we need to put .lit8
8383 somewhere in the data segment, and using .lit8
8384 permits the linker to eventually combine identical
8387 The code below needs to know whether the target register
8388 is 32 or 64 bits wide. It relies on the fact 'f' and
8389 'F' are used with GPR-based instructions and 'l' and
8390 'L' are used with FPR-based instructions. */
8392 f64 = *args == 'F' || *args == 'L';
8393 using_gprs = *args == 'F' || *args == 'f';
8395 save_in = input_line_pointer;
8396 input_line_pointer = s;
8397 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
8399 s = input_line_pointer;
8400 input_line_pointer = save_in;
8401 if (err != NULL && *err != '\0')
8403 as_bad (_("Bad floating point constant: %s"), err);
8404 memset (temp, '\0', sizeof temp);
8405 length = f64 ? 8 : 4;
8408 assert (length == (unsigned) (f64 ? 8 : 4));
8412 && (! USE_GLOBAL_POINTER_OPT
8413 || mips_pic == EMBEDDED_PIC
8414 || g_switch_value < 4
8415 || (temp[0] == 0 && temp[1] == 0)
8416 || (temp[2] == 0 && temp[3] == 0))))
8418 imm_expr.X_op = O_constant;
8419 if (! target_big_endian)
8420 imm_expr.X_add_number = bfd_getl32 (temp);
8422 imm_expr.X_add_number = bfd_getb32 (temp);
8425 && ! mips_disable_float_construction
8426 /* Constants can only be constructed in GPRs and
8427 copied to FPRs if the GPRs are at least as wide
8428 as the FPRs. Force the constant into memory if
8429 we are using 64-bit FPRs but the GPRs are only
8432 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
8433 && ((temp[0] == 0 && temp[1] == 0)
8434 || (temp[2] == 0 && temp[3] == 0))
8435 && ((temp[4] == 0 && temp[5] == 0)
8436 || (temp[6] == 0 && temp[7] == 0)))
8438 /* The value is simple enough to load with a couple of
8439 instructions. If using 32-bit registers, set
8440 imm_expr to the high order 32 bits and offset_expr to
8441 the low order 32 bits. Otherwise, set imm_expr to
8442 the entire 64 bit constant. */
8443 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
8445 imm_expr.X_op = O_constant;
8446 offset_expr.X_op = O_constant;
8447 if (! target_big_endian)
8449 imm_expr.X_add_number = bfd_getl32 (temp + 4);
8450 offset_expr.X_add_number = bfd_getl32 (temp);
8454 imm_expr.X_add_number = bfd_getb32 (temp);
8455 offset_expr.X_add_number = bfd_getb32 (temp + 4);
8457 if (offset_expr.X_add_number == 0)
8458 offset_expr.X_op = O_absent;
8460 else if (sizeof (imm_expr.X_add_number) > 4)
8462 imm_expr.X_op = O_constant;
8463 if (! target_big_endian)
8464 imm_expr.X_add_number = bfd_getl64 (temp);
8466 imm_expr.X_add_number = bfd_getb64 (temp);
8470 imm_expr.X_op = O_big;
8471 imm_expr.X_add_number = 4;
8472 if (! target_big_endian)
8474 generic_bignum[0] = bfd_getl16 (temp);
8475 generic_bignum[1] = bfd_getl16 (temp + 2);
8476 generic_bignum[2] = bfd_getl16 (temp + 4);
8477 generic_bignum[3] = bfd_getl16 (temp + 6);
8481 generic_bignum[0] = bfd_getb16 (temp + 6);
8482 generic_bignum[1] = bfd_getb16 (temp + 4);
8483 generic_bignum[2] = bfd_getb16 (temp + 2);
8484 generic_bignum[3] = bfd_getb16 (temp);
8490 const char *newname;
8493 /* Switch to the right section. */
8495 subseg = now_subseg;
8498 default: /* unused default case avoids warnings. */
8500 newname = RDATA_SECTION_NAME;
8501 if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8)
8502 || mips_pic == EMBEDDED_PIC)
8506 if (mips_pic == EMBEDDED_PIC)
8509 newname = RDATA_SECTION_NAME;
8512 assert (!USE_GLOBAL_POINTER_OPT
8513 || g_switch_value >= 4);
8517 new_seg = subseg_new (newname, (subsegT) 0);
8518 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
8519 bfd_set_section_flags (stdoutput, new_seg,
8524 frag_align (*args == 'l' ? 2 : 3, 0, 0);
8525 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
8526 && strcmp (TARGET_OS, "elf") != 0)
8527 record_alignment (new_seg, 4);
8529 record_alignment (new_seg, *args == 'l' ? 2 : 3);
8531 as_bad (_("Can't use floating point insn in this section"));
8533 /* Set the argument to the current address in the
8535 offset_expr.X_op = O_symbol;
8536 offset_expr.X_add_symbol =
8537 symbol_new ("L0\001", now_seg,
8538 (valueT) frag_now_fix (), frag_now);
8539 offset_expr.X_add_number = 0;
8541 /* Put the floating point number into the section. */
8542 p = frag_more ((int) length);
8543 memcpy (p, temp, length);
8545 /* Switch back to the original section. */
8546 subseg_set (seg, subseg);
8551 case 'i': /* 16 bit unsigned immediate */
8552 case 'j': /* 16 bit signed immediate */
8553 *imm_reloc = BFD_RELOC_LO16;
8554 c = my_getSmallExpression (&imm_expr, s);
8561 *imm_reloc = BFD_RELOC_HI16_S;
8562 imm_unmatched_hi = true;
8565 else if (c == S_EX_HIGHEST)
8566 *imm_reloc = BFD_RELOC_MIPS_HIGHEST;
8567 else if (c == S_EX_HIGHER)
8568 *imm_reloc = BFD_RELOC_MIPS_HIGHER;
8569 else if (c == S_EX_GP_REL)
8571 /* This occurs in NewABI only. */
8572 c = my_getSmallExpression (&imm_expr, s);
8574 as_bad (_("bad composition of relocations"));
8577 c = my_getSmallExpression (&imm_expr, s);
8579 as_bad (_("bad composition of relocations"));
8582 imm_reloc[0] = BFD_RELOC_GPREL16;
8583 imm_reloc[1] = BFD_RELOC_MIPS_SUB;
8584 imm_reloc[2] = BFD_RELOC_LO16;
8590 *imm_reloc = BFD_RELOC_HI16;
8592 else if (imm_expr.X_op == O_constant)
8593 imm_expr.X_add_number &= 0xffff;
8597 if ((c == S_EX_NONE && imm_expr.X_op != O_constant)
8598 || ((imm_expr.X_add_number < 0
8599 || imm_expr.X_add_number >= 0x10000)
8600 && imm_expr.X_op == O_constant))
8602 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
8603 !strcmp (insn->name, insn[1].name))
8605 if (imm_expr.X_op == O_constant
8606 || imm_expr.X_op == O_big)
8607 as_bad (_("16 bit expression not in range 0..65535"));
8615 /* The upper bound should be 0x8000, but
8616 unfortunately the MIPS assembler accepts numbers
8617 from 0x8000 to 0xffff and sign extends them, and
8618 we want to be compatible. We only permit this
8619 extended range for an instruction which does not
8620 provide any further alternates, since those
8621 alternates may handle other cases. People should
8622 use the numbers they mean, rather than relying on
8623 a mysterious sign extension. */
8624 more = (insn + 1 < &mips_opcodes[NUMOPCODES] &&
8625 strcmp (insn->name, insn[1].name) == 0);
8630 if ((c == S_EX_NONE && imm_expr.X_op != O_constant)
8631 || ((imm_expr.X_add_number < -0x8000
8632 || imm_expr.X_add_number >= max)
8633 && imm_expr.X_op == O_constant)
8635 && imm_expr.X_add_number < 0
8637 && imm_expr.X_unsigned
8638 && sizeof (imm_expr.X_add_number) <= 4))
8642 if (imm_expr.X_op == O_constant
8643 || imm_expr.X_op == O_big)
8644 as_bad (_("16 bit expression not in range -32768..32767"));
8650 case 'o': /* 16 bit offset */
8651 c = my_getSmallExpression (&offset_expr, s);
8653 /* If this value won't fit into a 16 bit offset, then go
8654 find a macro that will generate the 32 bit offset
8657 && (offset_expr.X_op != O_constant
8658 || offset_expr.X_add_number >= 0x8000
8659 || offset_expr.X_add_number < -0x8000))
8664 if (offset_expr.X_op != O_constant)
8666 offset_expr.X_add_number =
8667 (offset_expr.X_add_number >> 16) & 0xffff;
8669 *offset_reloc = BFD_RELOC_LO16;
8673 case 'p': /* pc relative offset */
8674 if (mips_pic == EMBEDDED_PIC)
8675 *offset_reloc = BFD_RELOC_16_PCREL_S2;
8677 *offset_reloc = BFD_RELOC_16_PCREL;
8678 my_getExpression (&offset_expr, s);
8682 case 'u': /* upper 16 bits */
8683 c = my_getSmallExpression (&imm_expr, s);
8684 *imm_reloc = BFD_RELOC_LO16;
8691 *imm_reloc = BFD_RELOC_HI16_S;
8692 imm_unmatched_hi = true;
8695 else if (c == S_EX_HIGHEST)
8696 *imm_reloc = BFD_RELOC_MIPS_HIGHEST;
8697 else if (c == S_EX_GP_REL)
8699 /* This occurs in NewABI only. */
8700 c = my_getSmallExpression (&imm_expr, s);
8702 as_bad (_("bad composition of relocations"));
8705 c = my_getSmallExpression (&imm_expr, s);
8707 as_bad (_("bad composition of relocations"));
8710 imm_reloc[0] = BFD_RELOC_GPREL16;
8711 imm_reloc[1] = BFD_RELOC_MIPS_SUB;
8712 imm_reloc[2] = BFD_RELOC_HI16_S;
8718 *imm_reloc = BFD_RELOC_HI16;
8720 else if (imm_expr.X_op == O_constant)
8721 imm_expr.X_add_number &= 0xffff;
8723 else if (imm_expr.X_op == O_constant
8724 && (imm_expr.X_add_number < 0
8725 || imm_expr.X_add_number >= 0x10000))
8726 as_bad (_("lui expression not in range 0..65535"));
8730 case 'a': /* 26 bit address */
8731 my_getExpression (&offset_expr, s);
8733 *offset_reloc = BFD_RELOC_MIPS_JMP;
8736 case 'N': /* 3 bit branch condition code */
8737 case 'M': /* 3 bit compare condition code */
8738 if (strncmp (s, "$fcc", 4) != 0)
8748 while (ISDIGIT (*s));
8750 as_bad (_("invalid condition code register $fcc%d"), regno);
8752 ip->insn_opcode |= regno << OP_SH_BCC;
8754 ip->insn_opcode |= regno << OP_SH_CCC;
8758 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
8769 while (ISDIGIT (*s));
8772 c = 8; /* Invalid sel value. */
8775 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
8776 ip->insn_opcode |= c;
8780 as_bad (_("bad char = '%c'\n"), *args);
8785 /* Args don't match. */
8786 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
8787 !strcmp (insn->name, insn[1].name))
8791 insn_error = _("illegal operands");
8796 insn_error = _("illegal operands");
8801 /* This routine assembles an instruction into its binary format when
8802 assembling for the mips16. As a side effect, it sets one of the
8803 global variables imm_reloc or offset_reloc to the type of
8804 relocation to do if one of the operands is an address expression.
8805 It also sets mips16_small and mips16_ext if the user explicitly
8806 requested a small or extended instruction. */
8811 struct mips_cl_insn *ip;
8815 struct mips_opcode *insn;
8818 unsigned int lastregno = 0;
8823 mips16_small = false;
8826 for (s = str; ISLOWER (*s); ++s)
8838 if (s[1] == 't' && s[2] == ' ')
8841 mips16_small = true;
8845 else if (s[1] == 'e' && s[2] == ' ')
8854 insn_error = _("unknown opcode");
8858 if (mips_opts.noautoextend && ! mips16_ext)
8859 mips16_small = true;
8861 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
8863 insn_error = _("unrecognized opcode");
8870 assert (strcmp (insn->name, str) == 0);
8873 ip->insn_opcode = insn->match;
8874 ip->use_extend = false;
8875 imm_expr.X_op = O_absent;
8876 imm_reloc[0] = BFD_RELOC_UNUSED;
8877 imm_reloc[1] = BFD_RELOC_UNUSED;
8878 imm_reloc[2] = BFD_RELOC_UNUSED;
8879 offset_expr.X_op = O_absent;
8880 offset_reloc[0] = BFD_RELOC_UNUSED;
8881 offset_reloc[1] = BFD_RELOC_UNUSED;
8882 offset_reloc[2] = BFD_RELOC_UNUSED;
8883 for (args = insn->args; 1; ++args)
8890 /* In this switch statement we call break if we did not find
8891 a match, continue if we did find a match, or return if we
8900 /* Stuff the immediate value in now, if we can. */
8901 if (imm_expr.X_op == O_constant
8902 && *imm_reloc > BFD_RELOC_UNUSED
8903 && insn->pinfo != INSN_MACRO)
8905 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
8906 imm_expr.X_add_number, true, mips16_small,
8907 mips16_ext, &ip->insn_opcode,
8908 &ip->use_extend, &ip->extend);
8909 imm_expr.X_op = O_absent;
8910 *imm_reloc = BFD_RELOC_UNUSED;
8924 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
8927 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
8943 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
8945 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
8972 while (ISDIGIT (*s));
8975 as_bad (_("invalid register number (%d)"), regno);
8981 if (s[1] == 'r' && s[2] == 'a')
8986 else if (s[1] == 'f' && s[2] == 'p')
8991 else if (s[1] == 's' && s[2] == 'p')
8996 else if (s[1] == 'g' && s[2] == 'p')
9001 else if (s[1] == 'a' && s[2] == 't')
9006 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
9011 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
9016 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
9029 if (c == 'v' || c == 'w')
9031 regno = mips16_to_32_reg_map[lastregno];
9045 regno = mips32_to_16_reg_map[regno];
9050 regno = ILLEGAL_REG;
9055 regno = ILLEGAL_REG;
9060 regno = ILLEGAL_REG;
9065 if (regno == AT && ! mips_opts.noat)
9066 as_warn (_("used $at without \".set noat\""));
9073 if (regno == ILLEGAL_REG)
9080 ip->insn_opcode |= regno << MIPS16OP_SH_RX;
9084 ip->insn_opcode |= regno << MIPS16OP_SH_RY;
9087 ip->insn_opcode |= regno << MIPS16OP_SH_RZ;
9090 ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z;
9096 ip->insn_opcode |= regno << MIPS16OP_SH_REGR32;
9099 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
9100 ip->insn_opcode |= regno << MIPS16OP_SH_REG32R;
9110 if (strncmp (s, "$pc", 3) == 0)
9134 && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0)
9136 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9137 and generate the appropriate reloc. If the text
9138 inside %gprel is not a symbol name with an
9139 optional offset, then we generate a normal reloc
9140 and will probably fail later. */
9141 my_getExpression (&imm_expr, s + sizeof "%gprel" - 1);
9142 if (imm_expr.X_op == O_symbol)
9145 *imm_reloc = BFD_RELOC_MIPS16_GPREL;
9147 ip->use_extend = true;
9154 /* Just pick up a normal expression. */
9155 my_getExpression (&imm_expr, s);
9158 if (imm_expr.X_op == O_register)
9160 /* What we thought was an expression turned out to
9163 if (s[0] == '(' && args[1] == '(')
9165 /* It looks like the expression was omitted
9166 before a register indirection, which means
9167 that the expression is implicitly zero. We
9168 still set up imm_expr, so that we handle
9169 explicit extensions correctly. */
9170 imm_expr.X_op = O_constant;
9171 imm_expr.X_add_number = 0;
9172 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9179 /* We need to relax this instruction. */
9180 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9189 /* We use offset_reloc rather than imm_reloc for the PC
9190 relative operands. This lets macros with both
9191 immediate and address operands work correctly. */
9192 my_getExpression (&offset_expr, s);
9194 if (offset_expr.X_op == O_register)
9197 /* We need to relax this instruction. */
9198 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
9202 case '6': /* break code */
9203 my_getExpression (&imm_expr, s);
9204 check_absolute_expr (ip, &imm_expr);
9205 if ((unsigned long) imm_expr.X_add_number > 63)
9207 as_warn (_("Invalid value for `%s' (%lu)"),
9209 (unsigned long) imm_expr.X_add_number);
9210 imm_expr.X_add_number &= 0x3f;
9212 ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6;
9213 imm_expr.X_op = O_absent;
9217 case 'a': /* 26 bit address */
9218 my_getExpression (&offset_expr, s);
9220 *offset_reloc = BFD_RELOC_MIPS16_JMP;
9221 ip->insn_opcode <<= 16;
9224 case 'l': /* register list for entry macro */
9225 case 'L': /* register list for exit macro */
9235 int freg, reg1, reg2;
9237 while (*s == ' ' || *s == ',')
9241 as_bad (_("can't parse register list"));
9253 while (ISDIGIT (*s))
9275 as_bad (_("invalid register list"));
9280 while (ISDIGIT (*s))
9287 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
9292 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
9297 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
9298 mask |= (reg2 - 3) << 3;
9299 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
9300 mask |= (reg2 - 15) << 1;
9301 else if (reg1 == RA && reg2 == RA)
9305 as_bad (_("invalid register list"));
9309 /* The mask is filled in in the opcode table for the
9310 benefit of the disassembler. We remove it before
9311 applying the actual mask. */
9312 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
9313 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
9317 case 'e': /* extend code */
9318 my_getExpression (&imm_expr, s);
9319 check_absolute_expr (ip, &imm_expr);
9320 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
9322 as_warn (_("Invalid value for `%s' (%lu)"),
9324 (unsigned long) imm_expr.X_add_number);
9325 imm_expr.X_add_number &= 0x7ff;
9327 ip->insn_opcode |= imm_expr.X_add_number;
9328 imm_expr.X_op = O_absent;
9338 /* Args don't match. */
9339 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
9340 strcmp (insn->name, insn[1].name) == 0)
9347 insn_error = _("illegal operands");
9353 /* This structure holds information we know about a mips16 immediate
9356 struct mips16_immed_operand
9358 /* The type code used in the argument string in the opcode table. */
9360 /* The number of bits in the short form of the opcode. */
9362 /* The number of bits in the extended form of the opcode. */
9364 /* The amount by which the short form is shifted when it is used;
9365 for example, the sw instruction has a shift count of 2. */
9367 /* The amount by which the short form is shifted when it is stored
9368 into the instruction code. */
9370 /* Non-zero if the short form is unsigned. */
9372 /* Non-zero if the extended form is unsigned. */
9374 /* Non-zero if the value is PC relative. */
9378 /* The mips16 immediate operand types. */
9380 static const struct mips16_immed_operand mips16_immed_operands[] =
9382 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9383 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9384 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9385 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9386 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
9387 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
9388 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
9389 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
9390 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
9391 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
9392 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
9393 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
9394 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
9395 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
9396 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
9397 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
9398 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9399 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9400 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
9401 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
9402 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
9405 #define MIPS16_NUM_IMMED \
9406 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9408 /* Handle a mips16 instruction with an immediate value. This or's the
9409 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9410 whether an extended value is needed; if one is needed, it sets
9411 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9412 If SMALL is true, an unextended opcode was explicitly requested.
9413 If EXT is true, an extended opcode was explicitly requested. If
9414 WARN is true, warn if EXT does not match reality. */
9417 mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend,
9426 unsigned long *insn;
9427 boolean *use_extend;
9428 unsigned short *extend;
9430 register const struct mips16_immed_operand *op;
9431 int mintiny, maxtiny;
9434 op = mips16_immed_operands;
9435 while (op->type != type)
9438 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
9443 if (type == '<' || type == '>' || type == '[' || type == ']')
9446 maxtiny = 1 << op->nbits;
9451 maxtiny = (1 << op->nbits) - 1;
9456 mintiny = - (1 << (op->nbits - 1));
9457 maxtiny = (1 << (op->nbits - 1)) - 1;
9460 /* Branch offsets have an implicit 0 in the lowest bit. */
9461 if (type == 'p' || type == 'q')
9464 if ((val & ((1 << op->shift) - 1)) != 0
9465 || val < (mintiny << op->shift)
9466 || val > (maxtiny << op->shift))
9471 if (warn && ext && ! needext)
9472 as_warn_where (file, line,
9473 _("extended operand requested but not required"));
9474 if (small && needext)
9475 as_bad_where (file, line, _("invalid unextended operand value"));
9477 if (small || (! ext && ! needext))
9481 *use_extend = false;
9482 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
9483 insnval <<= op->op_shift;
9488 long minext, maxext;
9494 maxext = (1 << op->extbits) - 1;
9498 minext = - (1 << (op->extbits - 1));
9499 maxext = (1 << (op->extbits - 1)) - 1;
9501 if (val < minext || val > maxext)
9502 as_bad_where (file, line,
9503 _("operand value out of range for instruction"));
9506 if (op->extbits == 16)
9508 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
9511 else if (op->extbits == 15)
9513 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
9518 extval = ((val & 0x1f) << 6) | (val & 0x20);
9522 *extend = (unsigned short) extval;
9527 static struct percent_op_match
9530 const enum small_ex_type type;
9535 {"%call_hi", S_EX_CALL_HI},
9536 {"%call_lo", S_EX_CALL_LO},
9537 {"%call16", S_EX_CALL16},
9538 {"%got_disp", S_EX_GOT_DISP},
9539 {"%got_page", S_EX_GOT_PAGE},
9540 {"%got_ofst", S_EX_GOT_OFST},
9541 {"%got_hi", S_EX_GOT_HI},
9542 {"%got_lo", S_EX_GOT_LO},
9544 {"%gp_rel", S_EX_GP_REL},
9545 {"%half", S_EX_HALF},
9546 {"%highest", S_EX_HIGHEST},
9547 {"%higher", S_EX_HIGHER},
9553 /* Parse small expression input. STR gets adjusted to eat up whitespace.
9554 It detects valid "%percent_op(...)" and "($reg)" strings. Percent_op's
9555 can be nested, this is handled by blanking the innermost, parsing the
9556 rest by subsequent calls. */
9559 my_getSmallParser (str, len, nestlevel)
9565 *str += strspn (*str, " \t");
9566 /* Check for expression in parentheses. */
9569 char *b = *str + 1 + strspn (*str + 1, " \t");
9572 /* Check for base register. */
9576 && (e = b + strcspn (b, ") \t"))
9577 && e - b > 1 && e - b < 4)
9580 && ((b[1] == 'f' && b[2] == 'p')
9581 || (b[1] == 's' && b[2] == 'p')
9582 || (b[1] == 'g' && b[2] == 'p')
9583 || (b[1] == 'a' && b[2] == 't')
9585 && ISDIGIT (b[2]))))
9586 || (ISDIGIT (b[1])))
9588 *len = strcspn (*str, ")") + 1;
9589 return S_EX_REGISTER;
9593 /* Check for percent_op (in parentheses). */
9594 else if (b[0] == '%')
9597 return my_getPercentOp (str, len, nestlevel);
9600 /* Some other expression in the parentheses, which can contain
9601 parentheses itself. Attempt to find the matching one. */
9607 for (s = *str + 1; *s && pcnt; s++, (*len)++)
9616 /* Check for percent_op (outside of parentheses). */
9617 else if (*str[0] == '%')
9618 return my_getPercentOp (str, len, nestlevel);
9620 /* Any other expression. */
9625 my_getPercentOp (str, len, nestlevel)
9630 char *tmp = *str + 1;
9633 while (ISALPHA (*tmp) || *tmp == '_')
9635 *tmp = TOLOWER (*tmp);
9638 while (i < (sizeof (percent_op) / sizeof (struct percent_op_match)))
9640 if (strncmp (*str, percent_op[i].str, strlen (percent_op[i].str)))
9644 int type = percent_op[i].type;
9646 /* Only %hi and %lo are allowed for OldABI. */
9647 if (! HAVE_NEWABI && type != S_EX_HI && type != S_EX_LO)
9650 *len = strlen (percent_op[i].str);
9659 my_getSmallExpression (ep, str)
9663 static char *oldstr = NULL;
9669 /* Don't update oldstr if the last call had nested percent_op's. We need
9670 it to parse the outer ones later. */
9677 c = my_getSmallParser (&str, &len, &nestlevel);
9678 if (c != S_EX_NONE && c != S_EX_REGISTER)
9681 while (c != S_EX_NONE && c != S_EX_REGISTER);
9685 /* A percent_op was encountered. Don't try to get an expression if
9686 it is already blanked out. */
9687 if (*(str + strspn (str + 1, " )")) != ')')
9691 /* Let my_getExpression() stop at the closing parenthesis. */
9692 save = *(str + len);
9693 *(str + len) = '\0';
9694 my_getExpression (ep, str);
9695 *(str + len) = save;
9699 /* Blank out including the % sign and the proper matching
9702 char *s = strrchr (oldstr, '%');
9705 for (end = strchr (s, '(') + 1; *end && pcnt; end++)
9709 else if (*end == ')')
9713 memset (s, ' ', end - s);
9717 expr_end = str + len;
9721 else if (c == S_EX_NONE)
9723 my_getExpression (ep, str);
9725 else if (c == S_EX_REGISTER)
9727 ep->X_op = O_constant;
9729 ep->X_add_symbol = NULL;
9730 ep->X_op_symbol = NULL;
9731 ep->X_add_number = 0;
9735 as_fatal (_("internal error"));
9739 /* All percent_op's have been handled. */
9746 my_getExpression (ep, str)
9753 save_in = input_line_pointer;
9754 input_line_pointer = str;
9756 expr_end = input_line_pointer;
9757 input_line_pointer = save_in;
9759 /* If we are in mips16 mode, and this is an expression based on `.',
9760 then we bump the value of the symbol by 1 since that is how other
9761 text symbols are handled. We don't bother to handle complex
9762 expressions, just `.' plus or minus a constant. */
9763 if (mips_opts.mips16
9764 && ep->X_op == O_symbol
9765 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
9766 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg
9767 && symbol_get_frag (ep->X_add_symbol) == frag_now
9768 && symbol_constant_p (ep->X_add_symbol)
9769 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
9770 S_SET_VALUE (ep->X_add_symbol, val + 1);
9773 /* Turn a string in input_line_pointer into a floating point constant
9774 of type TYPE, and store the appropriate bytes in *LITP. The number
9775 of LITTLENUMS emitted is stored in *SIZEP. An error message is
9776 returned, or NULL on OK. */
9779 md_atof (type, litP, sizeP)
9785 LITTLENUM_TYPE words[4];
9801 return _("bad call to md_atof");
9804 t = atof_ieee (input_line_pointer, type, words);
9806 input_line_pointer = t;
9810 if (! target_big_endian)
9812 for (i = prec - 1; i >= 0; i--)
9814 md_number_to_chars (litP, (valueT) words[i], 2);
9820 for (i = 0; i < prec; i++)
9822 md_number_to_chars (litP, (valueT) words[i], 2);
9831 md_number_to_chars (buf, val, n)
9836 if (target_big_endian)
9837 number_to_chars_bigendian (buf, val, n);
9839 number_to_chars_littleendian (buf, val, n);
9843 static int support_64bit_objects(void)
9845 const char **list, **l;
9847 list = bfd_target_list ();
9848 for (l = list; *l != NULL; l++)
9850 /* This is traditional mips */
9851 if (strcmp (*l, "elf64-tradbigmips") == 0
9852 || strcmp (*l, "elf64-tradlittlemips") == 0)
9854 if (strcmp (*l, "elf64-bigmips") == 0
9855 || strcmp (*l, "elf64-littlemips") == 0)
9859 return (*l != NULL);
9861 #endif /* OBJ_ELF */
9863 const char *md_shortopts = "nO::g::G:";
9865 struct option md_longopts[] =
9867 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
9868 {"mips0", no_argument, NULL, OPTION_MIPS1},
9869 {"mips1", no_argument, NULL, OPTION_MIPS1},
9870 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
9871 {"mips2", no_argument, NULL, OPTION_MIPS2},
9872 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
9873 {"mips3", no_argument, NULL, OPTION_MIPS3},
9874 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
9875 {"mips4", no_argument, NULL, OPTION_MIPS4},
9876 #define OPTION_MIPS5 (OPTION_MD_BASE + 5)
9877 {"mips5", no_argument, NULL, OPTION_MIPS5},
9878 #define OPTION_MIPS32 (OPTION_MD_BASE + 6)
9879 {"mips32", no_argument, NULL, OPTION_MIPS32},
9880 #define OPTION_MIPS64 (OPTION_MD_BASE + 7)
9881 {"mips64", no_argument, NULL, OPTION_MIPS64},
9882 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 8)
9883 {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC},
9884 #define OPTION_TRAP (OPTION_MD_BASE + 9)
9885 {"trap", no_argument, NULL, OPTION_TRAP},
9886 {"no-break", no_argument, NULL, OPTION_TRAP},
9887 #define OPTION_BREAK (OPTION_MD_BASE + 10)
9888 {"break", no_argument, NULL, OPTION_BREAK},
9889 {"no-trap", no_argument, NULL, OPTION_BREAK},
9890 #define OPTION_EB (OPTION_MD_BASE + 11)
9891 {"EB", no_argument, NULL, OPTION_EB},
9892 #define OPTION_EL (OPTION_MD_BASE + 12)
9893 {"EL", no_argument, NULL, OPTION_EL},
9894 #define OPTION_MIPS16 (OPTION_MD_BASE + 13)
9895 {"mips16", no_argument, NULL, OPTION_MIPS16},
9896 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 14)
9897 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
9898 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 15)
9899 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
9900 #define OPTION_MNO_7000_HILO_FIX (OPTION_MD_BASE + 16)
9901 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
9902 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
9903 #define OPTION_FP32 (OPTION_MD_BASE + 17)
9904 {"mfp32", no_argument, NULL, OPTION_FP32},
9905 #define OPTION_GP32 (OPTION_MD_BASE + 18)
9906 {"mgp32", no_argument, NULL, OPTION_GP32},
9907 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 19)
9908 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
9909 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 20)
9910 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
9911 #define OPTION_MARCH (OPTION_MD_BASE + 21)
9912 {"march", required_argument, NULL, OPTION_MARCH},
9913 #define OPTION_MTUNE (OPTION_MD_BASE + 22)
9914 {"mtune", required_argument, NULL, OPTION_MTUNE},
9915 #define OPTION_FP64 (OPTION_MD_BASE + 23)
9916 {"mfp64", no_argument, NULL, OPTION_FP64},
9917 #define OPTION_M4650 (OPTION_MD_BASE + 24)
9918 {"m4650", no_argument, NULL, OPTION_M4650},
9919 #define OPTION_NO_M4650 (OPTION_MD_BASE + 25)
9920 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
9921 #define OPTION_M4010 (OPTION_MD_BASE + 26)
9922 {"m4010", no_argument, NULL, OPTION_M4010},
9923 #define OPTION_NO_M4010 (OPTION_MD_BASE + 27)
9924 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
9925 #define OPTION_M4100 (OPTION_MD_BASE + 28)
9926 {"m4100", no_argument, NULL, OPTION_M4100},
9927 #define OPTION_NO_M4100 (OPTION_MD_BASE + 29)
9928 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
9929 #define OPTION_M3900 (OPTION_MD_BASE + 30)
9930 {"m3900", no_argument, NULL, OPTION_M3900},
9931 #define OPTION_NO_M3900 (OPTION_MD_BASE + 31)
9932 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
9933 #define OPTION_GP64 (OPTION_MD_BASE + 32)
9934 {"mgp64", no_argument, NULL, OPTION_GP64},
9935 #define OPTION_MIPS3D (OPTION_MD_BASE + 33)
9936 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
9937 #define OPTION_NO_MIPS3D (OPTION_MD_BASE + 34)
9938 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
9939 #define OPTION_MDMX (OPTION_MD_BASE + 35)
9940 {"mdmx", no_argument, NULL, OPTION_MDMX},
9941 #define OPTION_NO_MDMX (OPTION_MD_BASE + 36)
9942 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
9944 #define OPTION_ELF_BASE (OPTION_MD_BASE + 37)
9945 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
9946 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
9947 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
9948 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
9949 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
9950 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
9951 {"xgot", no_argument, NULL, OPTION_XGOT},
9952 #define OPTION_MABI (OPTION_ELF_BASE + 3)
9953 {"mabi", required_argument, NULL, OPTION_MABI},
9954 #define OPTION_32 (OPTION_ELF_BASE + 4)
9955 {"32", no_argument, NULL, OPTION_32},
9956 #define OPTION_N32 (OPTION_ELF_BASE + 5)
9957 {"n32", no_argument, NULL, OPTION_N32},
9958 #define OPTION_64 (OPTION_ELF_BASE + 6)
9959 {"64", no_argument, NULL, OPTION_64},
9960 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
9961 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
9962 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
9963 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
9964 #endif /* OBJ_ELF */
9965 {NULL, no_argument, NULL, 0}
9967 size_t md_longopts_size = sizeof (md_longopts);
9969 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
9970 NEW_VALUE. Warn if another value was already specified. Note:
9971 we have to defer parsing the -march and -mtune arguments in order
9972 to handle 'from-abi' correctly, since the ABI might be specified
9973 in a later argument. */
9976 mips_set_option_string (string_ptr, new_value)
9977 const char **string_ptr, *new_value;
9979 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
9980 as_warn (_("A different %s was already specified, is now %s"),
9981 string_ptr == &mips_arch_string ? "-march" : "-mtune",
9984 *string_ptr = new_value;
9988 md_parse_option (c, arg)
9994 case OPTION_CONSTRUCT_FLOATS:
9995 mips_disable_float_construction = 0;
9998 case OPTION_NO_CONSTRUCT_FLOATS:
9999 mips_disable_float_construction = 1;
10011 target_big_endian = 1;
10015 target_big_endian = 0;
10023 if (arg && arg[1] == '0')
10033 mips_debug = atoi (arg);
10034 /* When the MIPS assembler sees -g or -g2, it does not do
10035 optimizations which limit full symbolic debugging. We take
10036 that to be equivalent to -O0. */
10037 if (mips_debug == 2)
10042 file_mips_isa = ISA_MIPS1;
10046 file_mips_isa = ISA_MIPS2;
10050 file_mips_isa = ISA_MIPS3;
10054 file_mips_isa = ISA_MIPS4;
10058 file_mips_isa = ISA_MIPS5;
10061 case OPTION_MIPS32:
10062 file_mips_isa = ISA_MIPS32;
10065 case OPTION_MIPS64:
10066 file_mips_isa = ISA_MIPS64;
10070 mips_set_option_string (&mips_tune_string, arg);
10074 mips_set_option_string (&mips_arch_string, arg);
10078 mips_set_option_string (&mips_arch_string, "4650");
10079 mips_set_option_string (&mips_tune_string, "4650");
10082 case OPTION_NO_M4650:
10086 mips_set_option_string (&mips_arch_string, "4010");
10087 mips_set_option_string (&mips_tune_string, "4010");
10090 case OPTION_NO_M4010:
10094 mips_set_option_string (&mips_arch_string, "4100");
10095 mips_set_option_string (&mips_tune_string, "4100");
10098 case OPTION_NO_M4100:
10102 mips_set_option_string (&mips_arch_string, "3900");
10103 mips_set_option_string (&mips_tune_string, "3900");
10106 case OPTION_NO_M3900:
10110 mips_opts.ase_mdmx = 1;
10113 case OPTION_NO_MDMX:
10114 mips_opts.ase_mdmx = 0;
10117 case OPTION_MIPS16:
10118 mips_opts.mips16 = 1;
10119 mips_no_prev_insn (false);
10122 case OPTION_NO_MIPS16:
10123 mips_opts.mips16 = 0;
10124 mips_no_prev_insn (false);
10127 case OPTION_MIPS3D:
10128 mips_opts.ase_mips3d = 1;
10131 case OPTION_NO_MIPS3D:
10132 mips_opts.ase_mips3d = 0;
10135 case OPTION_MEMBEDDED_PIC:
10136 mips_pic = EMBEDDED_PIC;
10137 if (USE_GLOBAL_POINTER_OPT && g_switch_seen)
10139 as_bad (_("-G may not be used with embedded PIC code"));
10142 g_switch_value = 0x7fffffff;
10146 /* When generating ELF code, we permit -KPIC and -call_shared to
10147 select SVR4_PIC, and -non_shared to select no PIC. This is
10148 intended to be compatible with Irix 5. */
10149 case OPTION_CALL_SHARED:
10150 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10152 as_bad (_("-call_shared is supported only for ELF format"));
10155 mips_pic = SVR4_PIC;
10156 if (g_switch_seen && g_switch_value != 0)
10158 as_bad (_("-G may not be used with SVR4 PIC code"));
10161 g_switch_value = 0;
10164 case OPTION_NON_SHARED:
10165 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10167 as_bad (_("-non_shared is supported only for ELF format"));
10173 /* The -xgot option tells the assembler to use 32 offsets when
10174 accessing the got in SVR4_PIC mode. It is for Irix
10179 #endif /* OBJ_ELF */
10182 if (! USE_GLOBAL_POINTER_OPT)
10184 as_bad (_("-G is not supported for this configuration"));
10187 else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC)
10189 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
10193 g_switch_value = atoi (arg);
10198 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10201 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10203 as_bad (_("-32 is supported for ELF format only"));
10206 mips_abi = O32_ABI;
10210 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10212 as_bad (_("-n32 is supported for ELF format only"));
10215 mips_abi = N32_ABI;
10219 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10221 as_bad (_("-64 is supported for ELF format only"));
10224 mips_abi = N64_ABI;
10225 if (! support_64bit_objects())
10226 as_fatal (_("No compiled in support for 64 bit object file format"));
10228 #endif /* OBJ_ELF */
10231 file_mips_gp32 = 1;
10235 file_mips_gp32 = 0;
10239 file_mips_fp32 = 1;
10243 file_mips_fp32 = 0;
10248 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10250 as_bad (_("-mabi is supported for ELF format only"));
10253 if (strcmp (arg, "32") == 0)
10254 mips_abi = O32_ABI;
10255 else if (strcmp (arg, "o64") == 0)
10256 mips_abi = O64_ABI;
10257 else if (strcmp (arg, "n32") == 0)
10258 mips_abi = N32_ABI;
10259 else if (strcmp (arg, "64") == 0)
10261 mips_abi = N64_ABI;
10262 if (! support_64bit_objects())
10263 as_fatal (_("No compiled in support for 64 bit object file "
10266 else if (strcmp (arg, "eabi") == 0)
10267 mips_abi = EABI_ABI;
10270 as_fatal (_("invalid abi -mabi=%s"), arg);
10274 #endif /* OBJ_ELF */
10276 case OPTION_M7000_HILO_FIX:
10277 mips_7000_hilo_fix = true;
10280 case OPTION_MNO_7000_HILO_FIX:
10281 mips_7000_hilo_fix = false;
10285 case OPTION_MDEBUG:
10286 mips_flag_mdebug = true;
10289 case OPTION_NO_MDEBUG:
10290 mips_flag_mdebug = false;
10292 #endif /* OBJ_ELF */
10301 /* Set up globals to generate code for the ISA or processor
10302 described by INFO. */
10305 mips_set_architecture (info)
10306 const struct mips_cpu_info *info;
10310 mips_arch_info = info;
10311 mips_arch = info->cpu;
10312 mips_opts.isa = info->isa;
10317 /* Likewise for tuning. */
10320 mips_set_tune (info)
10321 const struct mips_cpu_info *info;
10325 mips_tune_info = info;
10326 mips_tune = info->cpu;
10332 mips_after_parse_args ()
10334 /* GP relative stuff not working for PE */
10335 if (strncmp (TARGET_OS, "pe", 2) == 0
10336 && g_switch_value != 0)
10339 as_bad (_("-G not supported in this configuration."));
10340 g_switch_value = 0;
10343 /* The following code determines the architecture and register size.
10344 Similar code was added to GCC 3.3 (see override_options() in
10345 config/mips/mips.c). The GAS and GCC code should be kept in sync
10346 as much as possible. */
10348 if (mips_arch_string != 0)
10349 mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string));
10351 if (mips_tune_string != 0)
10352 mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string));
10354 if (file_mips_isa != ISA_UNKNOWN)
10356 /* Handle -mipsN. At this point, file_mips_isa contains the
10357 ISA level specified by -mipsN, while mips_opts.isa contains
10358 the -march selection (if any). */
10359 if (mips_arch_info != 0)
10361 /* -march takes precedence over -mipsN, since it is more descriptive.
10362 There's no harm in specifying both as long as the ISA levels
10364 if (file_mips_isa != mips_opts.isa)
10365 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10366 mips_cpu_info_from_isa (file_mips_isa)->name,
10367 mips_cpu_info_from_isa (mips_opts.isa)->name);
10370 mips_set_architecture (mips_cpu_info_from_isa (file_mips_isa));
10373 if (mips_arch_info == 0)
10374 mips_set_architecture (mips_parse_cpu ("default CPU",
10375 MIPS_CPU_STRING_DEFAULT));
10377 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (mips_opts.isa))
10378 as_bad ("-march=%s is not compatible with the selected ABI",
10379 mips_arch_info->name);
10381 /* Optimize for mips_arch, unless -mtune selects a different processor. */
10382 if (mips_tune_info == 0)
10383 mips_set_tune (mips_arch_info);
10385 if (file_mips_gp32 >= 0)
10387 /* The user specified the size of the integer registers. Make sure
10388 it agrees with the ABI and ISA. */
10389 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
10390 as_bad (_("-mgp64 used with a 32-bit processor"));
10391 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
10392 as_bad (_("-mgp32 used with a 64-bit ABI"));
10393 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
10394 as_bad (_("-mgp64 used with a 32-bit ABI"));
10398 /* Infer the integer register size from the ABI and processor.
10399 Restrict ourselves to 32-bit registers if that's all the
10400 processor has, or if the ABI cannot handle 64-bit registers. */
10401 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
10402 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
10405 /* ??? GAS treats single-float processors as though they had 64-bit
10406 float registers (although it complains when double-precision
10407 instructions are used). As things stand, saying they have 32-bit
10408 registers would lead to spurious "register must be even" messages.
10409 So here we assume float registers are always the same size as
10410 integer ones, unless the user says otherwise. */
10411 if (file_mips_fp32 < 0)
10412 file_mips_fp32 = file_mips_gp32;
10414 /* End of GCC-shared inference code. */
10416 /* ??? When do we want this flag to be set? Who uses it? */
10417 if (file_mips_gp32 == 1
10418 && mips_abi == NO_ABI
10419 && ISA_HAS_64BIT_REGS (mips_opts.isa))
10420 mips_32bitmode = 1;
10422 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
10423 as_bad (_("trap exception not supported at ISA 1"));
10425 /* If the selected architecture includes support for ASEs, enable
10426 generation of code for them. */
10427 if (mips_opts.mips16 == -1)
10428 mips_opts.mips16 = (CPU_HAS_MIPS16 (mips_arch)) ? 1 : 0;
10429 if (mips_opts.ase_mips3d == -1)
10430 mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (mips_arch)) ? 1 : 0;
10431 if (mips_opts.ase_mdmx == -1)
10432 mips_opts.ase_mdmx = (CPU_HAS_MDMX (mips_arch)) ? 1 : 0;
10434 file_mips_isa = mips_opts.isa;
10435 file_ase_mips16 = mips_opts.mips16;
10436 file_ase_mips3d = mips_opts.ase_mips3d;
10437 file_ase_mdmx = mips_opts.ase_mdmx;
10438 mips_opts.gp32 = file_mips_gp32;
10439 mips_opts.fp32 = file_mips_fp32;
10441 if (mips_flag_mdebug < 0)
10443 #ifdef OBJ_MAYBE_ECOFF
10444 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
10445 mips_flag_mdebug = 1;
10447 #endif /* OBJ_MAYBE_ECOFF */
10448 mips_flag_mdebug = 0;
10453 mips_init_after_args ()
10455 /* initialize opcodes */
10456 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
10457 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
10461 md_pcrel_from (fixP)
10464 if (OUTPUT_FLAVOR != bfd_target_aout_flavour
10465 && fixP->fx_addsy != (symbolS *) NULL
10466 && ! S_IS_DEFINED (fixP->fx_addsy))
10468 /* This makes a branch to an undefined symbol be a branch to the
10469 current location. */
10470 if (mips_pic == EMBEDDED_PIC)
10476 /* Return the address of the delay slot. */
10477 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10480 /* This is called before the symbol table is processed. In order to
10481 work with gcc when using mips-tfile, we must keep all local labels.
10482 However, in other cases, we want to discard them. If we were
10483 called with -g, but we didn't see any debugging information, it may
10484 mean that gcc is smuggling debugging information through to
10485 mips-tfile, in which case we must generate all local labels. */
10488 mips_frob_file_before_adjust ()
10490 #ifndef NO_ECOFF_DEBUGGING
10491 if (ECOFF_DEBUGGING
10493 && ! ecoff_debugging_seen)
10494 flag_keep_locals = 1;
10498 /* Sort any unmatched HI16_S relocs so that they immediately precede
10499 the corresponding LO reloc. This is called before md_apply_fix3 and
10500 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10501 explicit use of the %hi modifier. */
10506 struct mips_hi_fixup *l;
10508 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
10510 segment_info_type *seginfo;
10513 assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S);
10515 /* Check quickly whether the next fixup happens to be a matching
10517 if (l->fixp->fx_next != NULL
10518 && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16
10519 && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
10520 && l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
10523 /* Look through the fixups for this segment for a matching %lo.
10524 When we find one, move the %hi just in front of it. We do
10525 this in two passes. In the first pass, we try to find a
10526 unique %lo. In the second pass, we permit multiple %hi
10527 relocs for a single %lo (this is a GNU extension). */
10528 seginfo = seg_info (l->seg);
10529 for (pass = 0; pass < 2; pass++)
10534 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
10536 /* Check whether this is a %lo fixup which matches l->fixp. */
10537 if (f->fx_r_type == BFD_RELOC_LO16
10538 && f->fx_addsy == l->fixp->fx_addsy
10539 && f->fx_offset == l->fixp->fx_offset
10542 || prev->fx_r_type != BFD_RELOC_HI16_S
10543 || prev->fx_addsy != f->fx_addsy
10544 || prev->fx_offset != f->fx_offset))
10548 /* Move l->fixp before f. */
10549 for (pf = &seginfo->fix_root;
10551 pf = &(*pf)->fx_next)
10552 assert (*pf != NULL);
10554 *pf = l->fixp->fx_next;
10556 l->fixp->fx_next = f;
10558 seginfo->fix_root = l->fixp;
10560 prev->fx_next = l->fixp;
10571 #if 0 /* GCC code motion plus incomplete dead code elimination
10572 can leave a %hi without a %lo. */
10574 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
10575 _("Unmatched %%hi reloc"));
10581 /* When generating embedded PIC code we need to use a special
10582 relocation to represent the difference of two symbols in the .text
10583 section (switch tables use a difference of this sort). See
10584 include/coff/mips.h for details. This macro checks whether this
10585 fixup requires the special reloc. */
10586 #define SWITCH_TABLE(fixp) \
10587 ((fixp)->fx_r_type == BFD_RELOC_32 \
10588 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
10589 && (fixp)->fx_addsy != NULL \
10590 && (fixp)->fx_subsy != NULL \
10591 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
10592 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
10594 /* When generating embedded PIC code we must keep all PC relative
10595 relocations, in case the linker has to relax a call. We also need
10596 to keep relocations for switch table entries.
10598 We may have combined relocations without symbols in the N32/N64 ABI.
10599 We have to prevent gas from dropping them. */
10602 mips_force_relocation (fixp)
10605 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
10606 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY
10607 || S_FORCE_RELOC (fixp->fx_addsy))
10611 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
10612 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
10613 || fixp->fx_r_type == BFD_RELOC_HI16_S
10614 || fixp->fx_r_type == BFD_RELOC_LO16))
10617 return (mips_pic == EMBEDDED_PIC
10619 || SWITCH_TABLE (fixp)
10620 || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S
10621 || fixp->fx_r_type == BFD_RELOC_PCREL_LO16));
10626 mips_need_elf_addend_fixup (fixP)
10629 if (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16)
10631 if (mips_pic == EMBEDDED_PIC
10632 && S_IS_WEAK (fixP->fx_addsy))
10634 if (mips_pic != EMBEDDED_PIC
10635 && (S_IS_WEAK (fixP->fx_addsy)
10636 || S_IS_EXTERNAL (fixP->fx_addsy))
10637 && !S_IS_COMMON (fixP->fx_addsy))
10639 if (symbol_used_in_reloc_p (fixP->fx_addsy)
10640 && (((bfd_get_section_flags (stdoutput,
10641 S_GET_SEGMENT (fixP->fx_addsy))
10642 & SEC_LINK_ONCE) != 0)
10643 || !strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)),
10645 sizeof (".gnu.linkonce") - 1)))
10651 /* Apply a fixup to the object file. */
10654 md_apply_fix3 (fixP, valP, seg)
10657 segT seg ATTRIBUTE_UNUSED;
10662 static int previous_fx_r_type = 0;
10664 /* FIXME: Maybe just return for all reloc types not listed below?
10665 Eric Christopher says: "This is stupid, please rewrite md_apply_fix3. */
10666 if (fixP->fx_r_type == BFD_RELOC_8)
10669 assert (fixP->fx_size == 4
10670 || fixP->fx_r_type == BFD_RELOC_16
10671 || fixP->fx_r_type == BFD_RELOC_32
10672 || fixP->fx_r_type == BFD_RELOC_MIPS_JMP
10673 || fixP->fx_r_type == BFD_RELOC_HI16_S
10674 || fixP->fx_r_type == BFD_RELOC_LO16
10675 || fixP->fx_r_type == BFD_RELOC_GPREL16
10676 || fixP->fx_r_type == BFD_RELOC_MIPS_LITERAL
10677 || fixP->fx_r_type == BFD_RELOC_GPREL32
10678 || fixP->fx_r_type == BFD_RELOC_64
10679 || fixP->fx_r_type == BFD_RELOC_CTOR
10680 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
10681 || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHEST
10682 || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHER
10683 || fixP->fx_r_type == BFD_RELOC_MIPS_SCN_DISP
10684 || fixP->fx_r_type == BFD_RELOC_MIPS_REL16
10685 || fixP->fx_r_type == BFD_RELOC_MIPS_RELGOT
10686 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
10687 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
10688 || fixP->fx_r_type == BFD_RELOC_MIPS_JALR);
10692 /* If we aren't adjusting this fixup to be against the section
10693 symbol, we need to adjust the value. */
10695 if (fixP->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour)
10697 if (mips_need_elf_addend_fixup (fixP))
10699 reloc_howto_type *howto;
10700 valueT symval = S_GET_VALUE (fixP->fx_addsy);
10704 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
10705 if (value != 0 && howto->partial_inplace && ! fixP->fx_pcrel)
10707 /* In this case, the bfd_install_relocation routine will
10708 incorrectly add the symbol value back in. We just want
10709 the addend to appear in the object file. */
10712 /* Make sure the addend is still non-zero. If it became zero
10713 after the last operation, set it to a spurious value and
10714 subtract the same value from the object file's contents. */
10719 /* The in-place addends for LO16 relocations are signed;
10720 leave the matching HI16 in-place addends as zero. */
10721 if (fixP->fx_r_type != BFD_RELOC_HI16_S)
10723 bfd_vma contents, mask, field;
10725 contents = bfd_get_bits (fixP->fx_frag->fr_literal
10728 target_big_endian);
10730 /* MASK has bits set where the relocation should go.
10731 FIELD is -value, shifted into the appropriate place
10732 for this relocation. */
10733 mask = 1 << (howto->bitsize - 1);
10734 mask = (((mask - 1) << 1) | 1) << howto->bitpos;
10735 field = (-value >> howto->rightshift) << howto->bitpos;
10737 bfd_put_bits ((field & mask) | (contents & ~mask),
10738 fixP->fx_frag->fr_literal + fixP->fx_where,
10740 target_big_endian);
10746 /* This code was generated using trial and error and so is
10747 fragile and not trustworthy. If you change it, you should
10748 rerun the elf-rel, elf-rel2, and empic testcases and ensure
10749 they still pass. */
10750 if (fixP->fx_pcrel || fixP->fx_subsy != NULL)
10752 value += fixP->fx_frag->fr_address + fixP->fx_where;
10754 /* BFD's REL handling, for MIPS, is _very_ weird.
10755 This gives the right results, but it can't possibly
10756 be the way things are supposed to work. */
10757 if ((fixP->fx_r_type != BFD_RELOC_16_PCREL
10758 && fixP->fx_r_type != BFD_RELOC_16_PCREL_S2)
10759 || S_GET_SEGMENT (fixP->fx_addsy) != undefined_section)
10760 value += fixP->fx_frag->fr_address + fixP->fx_where;
10765 fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc. */
10767 /* We are not done if this is a composite relocation to set up gp. */
10768 if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel
10769 && !(fixP->fx_r_type == BFD_RELOC_MIPS_SUB
10770 || (previous_fx_r_type == BFD_RELOC_MIPS_SUB
10771 && (fixP->fx_r_type == BFD_RELOC_HI16_S
10772 || fixP->fx_r_type == BFD_RELOC_LO16))))
10774 previous_fx_r_type = fixP->fx_r_type;
10776 switch (fixP->fx_r_type)
10778 case BFD_RELOC_MIPS_JMP:
10779 case BFD_RELOC_MIPS_SHIFT5:
10780 case BFD_RELOC_MIPS_SHIFT6:
10781 case BFD_RELOC_MIPS_GOT_DISP:
10782 case BFD_RELOC_MIPS_GOT_PAGE:
10783 case BFD_RELOC_MIPS_GOT_OFST:
10784 case BFD_RELOC_MIPS_SUB:
10785 case BFD_RELOC_MIPS_INSERT_A:
10786 case BFD_RELOC_MIPS_INSERT_B:
10787 case BFD_RELOC_MIPS_DELETE:
10788 case BFD_RELOC_MIPS_HIGHEST:
10789 case BFD_RELOC_MIPS_HIGHER:
10790 case BFD_RELOC_MIPS_SCN_DISP:
10791 case BFD_RELOC_MIPS_REL16:
10792 case BFD_RELOC_MIPS_RELGOT:
10793 case BFD_RELOC_MIPS_JALR:
10794 case BFD_RELOC_HI16:
10795 case BFD_RELOC_HI16_S:
10796 case BFD_RELOC_GPREL16:
10797 case BFD_RELOC_MIPS_LITERAL:
10798 case BFD_RELOC_MIPS_CALL16:
10799 case BFD_RELOC_MIPS_GOT16:
10800 case BFD_RELOC_GPREL32:
10801 case BFD_RELOC_MIPS_GOT_HI16:
10802 case BFD_RELOC_MIPS_GOT_LO16:
10803 case BFD_RELOC_MIPS_CALL_HI16:
10804 case BFD_RELOC_MIPS_CALL_LO16:
10805 case BFD_RELOC_MIPS16_GPREL:
10806 if (fixP->fx_pcrel)
10807 as_bad_where (fixP->fx_file, fixP->fx_line,
10808 _("Invalid PC relative reloc"));
10809 /* Nothing needed to do. The value comes from the reloc entry */
10812 case BFD_RELOC_MIPS16_JMP:
10813 /* We currently always generate a reloc against a symbol, which
10814 means that we don't want an addend even if the symbol is
10816 fixP->fx_addnumber = 0;
10819 case BFD_RELOC_PCREL_HI16_S:
10820 /* The addend for this is tricky if it is internal, so we just
10821 do everything here rather than in bfd_install_relocation. */
10822 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
10827 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
10829 /* For an external symbol adjust by the address to make it
10830 pcrel_offset. We use the address of the RELLO reloc
10831 which follows this one. */
10832 value += (fixP->fx_next->fx_frag->fr_address
10833 + fixP->fx_next->fx_where);
10835 value = ((value + 0x8000) >> 16) & 0xffff;
10836 buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where;
10837 if (target_big_endian)
10839 md_number_to_chars ((char *) buf, value, 2);
10842 case BFD_RELOC_PCREL_LO16:
10843 /* The addend for this is tricky if it is internal, so we just
10844 do everything here rather than in bfd_install_relocation. */
10845 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
10850 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
10851 value += fixP->fx_frag->fr_address + fixP->fx_where;
10852 buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where;
10853 if (target_big_endian)
10855 md_number_to_chars ((char *) buf, value, 2);
10859 /* This is handled like BFD_RELOC_32, but we output a sign
10860 extended value if we are only 32 bits. */
10862 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
10864 if (8 <= sizeof (valueT))
10865 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
10872 w1 = w2 = fixP->fx_where;
10873 if (target_big_endian)
10877 md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4);
10878 if ((value & 0x80000000) != 0)
10882 md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4);
10887 case BFD_RELOC_RVA:
10889 /* If we are deleting this reloc entry, we must fill in the
10890 value now. This can happen if we have a .word which is not
10891 resolved when it appears but is later defined. We also need
10892 to fill in the value if this is an embedded PIC switch table
10895 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
10896 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
10901 /* If we are deleting this reloc entry, we must fill in the
10903 assert (fixP->fx_size == 2);
10905 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
10909 case BFD_RELOC_LO16:
10910 /* When handling an embedded PIC switch statement, we can wind
10911 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
10914 if (value + 0x8000 > 0xffff)
10915 as_bad_where (fixP->fx_file, fixP->fx_line,
10916 _("relocation overflow"));
10917 buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where;
10918 if (target_big_endian)
10920 md_number_to_chars ((char *) buf, value, 2);
10924 case BFD_RELOC_16_PCREL_S2:
10925 if ((value & 0x3) != 0)
10926 as_bad_where (fixP->fx_file, fixP->fx_line,
10927 _("Branch to odd address (%lx)"), (long) value);
10929 /* Fall through. */
10931 case BFD_RELOC_16_PCREL:
10933 * We need to save the bits in the instruction since fixup_segment()
10934 * might be deleting the relocation entry (i.e., a branch within
10935 * the current segment).
10937 if (!fixP->fx_done && value != 0)
10939 /* If 'value' is zero, the remaining reloc code won't actually
10940 do the store, so it must be done here. This is probably
10941 a bug somewhere. */
10943 && (fixP->fx_r_type != BFD_RELOC_16_PCREL_S2
10944 || fixP->fx_addsy == NULL /* ??? */
10945 || ! S_IS_DEFINED (fixP->fx_addsy)))
10946 value -= fixP->fx_frag->fr_address + fixP->fx_where;
10948 value = (offsetT) value >> 2;
10950 /* update old instruction data */
10951 buf = (bfd_byte *) (fixP->fx_where + fixP->fx_frag->fr_literal);
10952 if (target_big_endian)
10953 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
10955 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
10957 if (value + 0x8000 <= 0xffff)
10958 insn |= value & 0xffff;
10961 /* The branch offset is too large. If this is an
10962 unconditional branch, and we are not generating PIC code,
10963 we can convert it to an absolute jump instruction. */
10964 if (mips_pic == NO_PIC
10966 && fixP->fx_frag->fr_address >= text_section->vma
10967 && (fixP->fx_frag->fr_address
10968 < text_section->vma + text_section->_raw_size)
10969 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
10970 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
10971 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
10973 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
10974 insn = 0x0c000000; /* jal */
10976 insn = 0x08000000; /* j */
10977 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
10979 fixP->fx_addsy = section_symbol (text_section);
10980 fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP);
10984 /* FIXME. It would be possible in principle to handle
10985 conditional branches which overflow. They could be
10986 transformed into a branch around a jump. This would
10987 require setting up variant frags for each different
10988 branch type. The native MIPS assembler attempts to
10989 handle these cases, but it appears to do it
10991 as_bad_where (fixP->fx_file, fixP->fx_line,
10992 _("Branch out of range"));
10996 md_number_to_chars ((char *) buf, (valueT) insn, 4);
10999 case BFD_RELOC_VTABLE_INHERIT:
11002 && !S_IS_DEFINED (fixP->fx_addsy)
11003 && !S_IS_WEAK (fixP->fx_addsy))
11004 S_SET_WEAK (fixP->fx_addsy);
11007 case BFD_RELOC_VTABLE_ENTRY:
11021 const struct mips_opcode *p;
11022 int treg, sreg, dreg, shamt;
11027 for (i = 0; i < NUMOPCODES; ++i)
11029 p = &mips_opcodes[i];
11030 if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO))
11032 printf ("%08lx %s\t", oc, p->name);
11033 treg = (oc >> 16) & 0x1f;
11034 sreg = (oc >> 21) & 0x1f;
11035 dreg = (oc >> 11) & 0x1f;
11036 shamt = (oc >> 6) & 0x1f;
11038 for (args = p->args;; ++args)
11049 printf ("%c", *args);
11053 assert (treg == sreg);
11054 printf ("$%d,$%d", treg, sreg);
11059 printf ("$%d", dreg);
11064 printf ("$%d", treg);
11068 printf ("0x%x", treg);
11073 printf ("$%d", sreg);
11077 printf ("0x%08lx", oc & 0x1ffffff);
11084 printf ("%d", imm);
11089 printf ("$%d", shamt);
11100 printf (_("%08lx UNDEFINED\n"), oc);
11111 name = input_line_pointer;
11112 c = get_symbol_end ();
11113 p = (symbolS *) symbol_find_or_make (name);
11114 *input_line_pointer = c;
11118 /* Align the current frag to a given power of two. The MIPS assembler
11119 also automatically adjusts any preceding label. */
11122 mips_align (to, fill, label)
11127 mips_emit_delays (false);
11128 frag_align (to, fill, 0);
11129 record_alignment (now_seg, to);
11132 assert (S_GET_SEGMENT (label) == now_seg);
11133 symbol_set_frag (label, frag_now);
11134 S_SET_VALUE (label, (valueT) frag_now_fix ());
11138 /* Align to a given power of two. .align 0 turns off the automatic
11139 alignment used by the data creating pseudo-ops. */
11143 int x ATTRIBUTE_UNUSED;
11146 register long temp_fill;
11147 long max_alignment = 15;
11151 o Note that the assembler pulls down any immediately preceeding label
11152 to the aligned address.
11153 o It's not documented but auto alignment is reinstated by
11154 a .align pseudo instruction.
11155 o Note also that after auto alignment is turned off the mips assembler
11156 issues an error on attempt to assemble an improperly aligned data item.
11161 temp = get_absolute_expression ();
11162 if (temp > max_alignment)
11163 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
11166 as_warn (_("Alignment negative: 0 assumed."));
11169 if (*input_line_pointer == ',')
11171 ++input_line_pointer;
11172 temp_fill = get_absolute_expression ();
11179 mips_align (temp, (int) temp_fill,
11180 insn_labels != NULL ? insn_labels->label : NULL);
11187 demand_empty_rest_of_line ();
11191 mips_flush_pending_output ()
11193 mips_emit_delays (false);
11194 mips_clear_insn_labels ();
11203 /* When generating embedded PIC code, we only use the .text, .lit8,
11204 .sdata and .sbss sections. We change the .data and .rdata
11205 pseudo-ops to use .sdata. */
11206 if (mips_pic == EMBEDDED_PIC
11207 && (sec == 'd' || sec == 'r'))
11211 /* The ELF backend needs to know that we are changing sections, so
11212 that .previous works correctly. We could do something like check
11213 for an obj_section_change_hook macro, but that might be confusing
11214 as it would not be appropriate to use it in the section changing
11215 functions in read.c, since obj-elf.c intercepts those. FIXME:
11216 This should be cleaner, somehow. */
11217 obj_elf_section_change_hook ();
11220 mips_emit_delays (false);
11230 subseg_set (bss_section, (subsegT) get_absolute_expression ());
11231 demand_empty_rest_of_line ();
11235 if (USE_GLOBAL_POINTER_OPT)
11237 seg = subseg_new (RDATA_SECTION_NAME,
11238 (subsegT) get_absolute_expression ());
11239 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11241 bfd_set_section_flags (stdoutput, seg,
11247 if (strcmp (TARGET_OS, "elf") != 0)
11248 record_alignment (seg, 4);
11250 demand_empty_rest_of_line ();
11254 as_bad (_("No read only data section in this object file format"));
11255 demand_empty_rest_of_line ();
11261 if (USE_GLOBAL_POINTER_OPT)
11263 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
11264 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11266 bfd_set_section_flags (stdoutput, seg,
11267 SEC_ALLOC | SEC_LOAD | SEC_RELOC
11269 if (strcmp (TARGET_OS, "elf") != 0)
11270 record_alignment (seg, 4);
11272 demand_empty_rest_of_line ();
11277 as_bad (_("Global pointers not supported; recompile -G 0"));
11278 demand_empty_rest_of_line ();
11287 s_change_section (ignore)
11288 int ignore ATTRIBUTE_UNUSED;
11291 char *section_name;
11296 int section_entry_size;
11297 int section_alignment;
11299 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
11302 section_name = input_line_pointer;
11303 c = get_symbol_end ();
11304 next_c = *(input_line_pointer + 1);
11306 /* Do we have .section Name<,"flags">? */
11307 if (c != ',' || (c == ',' && next_c == '"'))
11309 /* just after name is now '\0'. */
11310 *input_line_pointer = c;
11311 input_line_pointer = section_name;
11312 obj_elf_section (ignore);
11315 input_line_pointer++;
11317 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11319 section_type = get_absolute_expression ();
11322 if (*input_line_pointer++ == ',')
11323 section_flag = get_absolute_expression ();
11326 if (*input_line_pointer++ == ',')
11327 section_entry_size = get_absolute_expression ();
11329 section_entry_size = 0;
11330 if (*input_line_pointer++ == ',')
11331 section_alignment = get_absolute_expression ();
11333 section_alignment = 0;
11335 obj_elf_change_section (section_name, section_type, section_flag,
11336 section_entry_size, 0, 0, 0);
11337 #endif /* OBJ_ELF */
11341 mips_enable_auto_align ()
11352 label = insn_labels != NULL ? insn_labels->label : NULL;
11353 mips_emit_delays (false);
11354 if (log_size > 0 && auto_align)
11355 mips_align (log_size, 0, label);
11356 mips_clear_insn_labels ();
11357 cons (1 << log_size);
11361 s_float_cons (type)
11366 label = insn_labels != NULL ? insn_labels->label : NULL;
11368 mips_emit_delays (false);
11373 mips_align (3, 0, label);
11375 mips_align (2, 0, label);
11378 mips_clear_insn_labels ();
11383 /* Handle .globl. We need to override it because on Irix 5 you are
11386 where foo is an undefined symbol, to mean that foo should be
11387 considered to be the address of a function. */
11391 int x ATTRIBUTE_UNUSED;
11398 name = input_line_pointer;
11399 c = get_symbol_end ();
11400 symbolP = symbol_find_or_make (name);
11401 *input_line_pointer = c;
11402 SKIP_WHITESPACE ();
11404 /* On Irix 5, every global symbol that is not explicitly labelled as
11405 being a function is apparently labelled as being an object. */
11408 if (! is_end_of_line[(unsigned char) *input_line_pointer])
11413 secname = input_line_pointer;
11414 c = get_symbol_end ();
11415 sec = bfd_get_section_by_name (stdoutput, secname);
11417 as_bad (_("%s: no such section"), secname);
11418 *input_line_pointer = c;
11420 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
11421 flag = BSF_FUNCTION;
11424 symbol_get_bfdsym (symbolP)->flags |= flag;
11426 S_SET_EXTERNAL (symbolP);
11427 demand_empty_rest_of_line ();
11432 int x ATTRIBUTE_UNUSED;
11437 opt = input_line_pointer;
11438 c = get_symbol_end ();
11442 /* FIXME: What does this mean? */
11444 else if (strncmp (opt, "pic", 3) == 0)
11448 i = atoi (opt + 3);
11452 mips_pic = SVR4_PIC;
11454 as_bad (_(".option pic%d not supported"), i);
11456 if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC)
11458 if (g_switch_seen && g_switch_value != 0)
11459 as_warn (_("-G may not be used with SVR4 PIC code"));
11460 g_switch_value = 0;
11461 bfd_set_gp_size (stdoutput, 0);
11465 as_warn (_("Unrecognized option \"%s\""), opt);
11467 *input_line_pointer = c;
11468 demand_empty_rest_of_line ();
11471 /* This structure is used to hold a stack of .set values. */
11473 struct mips_option_stack
11475 struct mips_option_stack *next;
11476 struct mips_set_options options;
11479 static struct mips_option_stack *mips_opts_stack;
11481 /* Handle the .set pseudo-op. */
11485 int x ATTRIBUTE_UNUSED;
11487 char *name = input_line_pointer, ch;
11489 while (!is_end_of_line[(unsigned char) *input_line_pointer])
11490 ++input_line_pointer;
11491 ch = *input_line_pointer;
11492 *input_line_pointer = '\0';
11494 if (strcmp (name, "reorder") == 0)
11496 if (mips_opts.noreorder && prev_nop_frag != NULL)
11498 /* If we still have pending nops, we can discard them. The
11499 usual nop handling will insert any that are still
11501 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11502 * (mips_opts.mips16 ? 2 : 4));
11503 prev_nop_frag = NULL;
11505 mips_opts.noreorder = 0;
11507 else if (strcmp (name, "noreorder") == 0)
11509 mips_emit_delays (true);
11510 mips_opts.noreorder = 1;
11511 mips_any_noreorder = 1;
11513 else if (strcmp (name, "at") == 0)
11515 mips_opts.noat = 0;
11517 else if (strcmp (name, "noat") == 0)
11519 mips_opts.noat = 1;
11521 else if (strcmp (name, "macro") == 0)
11523 mips_opts.warn_about_macros = 0;
11525 else if (strcmp (name, "nomacro") == 0)
11527 if (mips_opts.noreorder == 0)
11528 as_bad (_("`noreorder' must be set before `nomacro'"));
11529 mips_opts.warn_about_macros = 1;
11531 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
11533 mips_opts.nomove = 0;
11535 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
11537 mips_opts.nomove = 1;
11539 else if (strcmp (name, "bopt") == 0)
11541 mips_opts.nobopt = 0;
11543 else if (strcmp (name, "nobopt") == 0)
11545 mips_opts.nobopt = 1;
11547 else if (strcmp (name, "mips16") == 0
11548 || strcmp (name, "MIPS-16") == 0)
11549 mips_opts.mips16 = 1;
11550 else if (strcmp (name, "nomips16") == 0
11551 || strcmp (name, "noMIPS-16") == 0)
11552 mips_opts.mips16 = 0;
11553 else if (strcmp (name, "mips3d") == 0)
11554 mips_opts.ase_mips3d = 1;
11555 else if (strcmp (name, "nomips3d") == 0)
11556 mips_opts.ase_mips3d = 0;
11557 else if (strcmp (name, "mdmx") == 0)
11558 mips_opts.ase_mdmx = 1;
11559 else if (strcmp (name, "nomdmx") == 0)
11560 mips_opts.ase_mdmx = 0;
11561 else if (strncmp (name, "mips", 4) == 0)
11565 /* Permit the user to change the ISA on the fly. Needless to
11566 say, misuse can cause serious problems. */
11567 isa = atoi (name + 4);
11571 mips_opts.gp32 = file_mips_gp32;
11572 mips_opts.fp32 = file_mips_fp32;
11577 mips_opts.gp32 = 1;
11578 mips_opts.fp32 = 1;
11584 mips_opts.gp32 = 0;
11585 mips_opts.fp32 = 0;
11588 as_bad (_("unknown ISA level %s"), name + 4);
11594 case 0: mips_opts.isa = file_mips_isa; break;
11595 case 1: mips_opts.isa = ISA_MIPS1; break;
11596 case 2: mips_opts.isa = ISA_MIPS2; break;
11597 case 3: mips_opts.isa = ISA_MIPS3; break;
11598 case 4: mips_opts.isa = ISA_MIPS4; break;
11599 case 5: mips_opts.isa = ISA_MIPS5; break;
11600 case 32: mips_opts.isa = ISA_MIPS32; break;
11601 case 64: mips_opts.isa = ISA_MIPS64; break;
11602 default: as_bad (_("unknown ISA level %s"), name + 4); break;
11605 else if (strcmp (name, "autoextend") == 0)
11606 mips_opts.noautoextend = 0;
11607 else if (strcmp (name, "noautoextend") == 0)
11608 mips_opts.noautoextend = 1;
11609 else if (strcmp (name, "push") == 0)
11611 struct mips_option_stack *s;
11613 s = (struct mips_option_stack *) xmalloc (sizeof *s);
11614 s->next = mips_opts_stack;
11615 s->options = mips_opts;
11616 mips_opts_stack = s;
11618 else if (strcmp (name, "pop") == 0)
11620 struct mips_option_stack *s;
11622 s = mips_opts_stack;
11624 as_bad (_(".set pop with no .set push"));
11627 /* If we're changing the reorder mode we need to handle
11628 delay slots correctly. */
11629 if (s->options.noreorder && ! mips_opts.noreorder)
11630 mips_emit_delays (true);
11631 else if (! s->options.noreorder && mips_opts.noreorder)
11633 if (prev_nop_frag != NULL)
11635 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11636 * (mips_opts.mips16 ? 2 : 4));
11637 prev_nop_frag = NULL;
11641 mips_opts = s->options;
11642 mips_opts_stack = s->next;
11648 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
11650 *input_line_pointer = ch;
11651 demand_empty_rest_of_line ();
11654 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11655 .option pic2. It means to generate SVR4 PIC calls. */
11658 s_abicalls (ignore)
11659 int ignore ATTRIBUTE_UNUSED;
11661 mips_pic = SVR4_PIC;
11662 if (USE_GLOBAL_POINTER_OPT)
11664 if (g_switch_seen && g_switch_value != 0)
11665 as_warn (_("-G may not be used with SVR4 PIC code"));
11666 g_switch_value = 0;
11668 bfd_set_gp_size (stdoutput, 0);
11669 demand_empty_rest_of_line ();
11672 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11673 PIC code. It sets the $gp register for the function based on the
11674 function address, which is in the register named in the argument.
11675 This uses a relocation against _gp_disp, which is handled specially
11676 by the linker. The result is:
11677 lui $gp,%hi(_gp_disp)
11678 addiu $gp,$gp,%lo(_gp_disp)
11679 addu $gp,$gp,.cpload argument
11680 The .cpload argument is normally $25 == $t9. */
11684 int ignore ATTRIBUTE_UNUSED;
11689 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11690 .cpload is ignored. */
11691 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
11697 /* .cpload should be in a .set noreorder section. */
11698 if (mips_opts.noreorder == 0)
11699 as_warn (_(".cpload not in noreorder section"));
11701 ex.X_op = O_symbol;
11702 ex.X_add_symbol = symbol_find_or_make ("_gp_disp");
11703 ex.X_op_symbol = NULL;
11704 ex.X_add_number = 0;
11706 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11707 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
11709 macro_build_lui (NULL, &icnt, &ex, mips_gp_register);
11710 macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j",
11711 mips_gp_register, mips_gp_register, (int) BFD_RELOC_LO16);
11713 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t",
11714 mips_gp_register, mips_gp_register, tc_get_register (0));
11716 demand_empty_rest_of_line ();
11719 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11720 .cpsetup $reg1, offset|$reg2, label
11722 If offset is given, this results in:
11723 sd $gp, offset($sp)
11724 lui $gp, %hi(%neg(%gp_rel(label)))
11725 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11726 daddu $gp, $gp, $reg1
11728 If $reg2 is given, this results in:
11729 daddu $reg2, $gp, $0
11730 lui $gp, %hi(%neg(%gp_rel(label)))
11731 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11732 daddu $gp, $gp, $reg1
11733 $reg1 is normally $25 == $t9. */
11736 int ignore ATTRIBUTE_UNUSED;
11738 expressionS ex_off;
11739 expressionS ex_sym;
11744 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
11745 We also need NewABI support. */
11746 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11752 reg1 = tc_get_register (0);
11753 SKIP_WHITESPACE ();
11754 if (*input_line_pointer != ',')
11756 as_bad (_("missing argument separator ',' for .cpsetup"));
11760 ++input_line_pointer;
11761 SKIP_WHITESPACE ();
11762 if (*input_line_pointer == '$')
11764 mips_cpreturn_register = tc_get_register (0);
11765 mips_cpreturn_offset = -1;
11769 mips_cpreturn_offset = get_absolute_expression ();
11770 mips_cpreturn_register = -1;
11772 SKIP_WHITESPACE ();
11773 if (*input_line_pointer != ',')
11775 as_bad (_("missing argument separator ',' for .cpsetup"));
11779 ++input_line_pointer;
11780 SKIP_WHITESPACE ();
11781 expression (&ex_sym);
11783 if (mips_cpreturn_register == -1)
11785 ex_off.X_op = O_constant;
11786 ex_off.X_add_symbol = NULL;
11787 ex_off.X_op_symbol = NULL;
11788 ex_off.X_add_number = mips_cpreturn_offset;
11790 macro_build ((char *) NULL, &icnt, &ex_off, "sd", "t,o(b)",
11791 mips_gp_register, (int) BFD_RELOC_LO16, SP);
11794 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu",
11795 "d,v,t", mips_cpreturn_register, mips_gp_register, 0);
11797 /* Ensure there's room for the next two instructions, so that `f'
11798 doesn't end up with an address in the wrong frag. */
11801 macro_build ((char *) NULL, &icnt, &ex_sym, "lui", "t,u", mips_gp_register,
11802 (int) BFD_RELOC_GPREL16);
11803 fix_new (frag_now, f - frag_now->fr_literal,
11804 0, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
11805 fix_new (frag_now, f - frag_now->fr_literal,
11806 0, NULL, 0, 0, BFD_RELOC_HI16_S);
11809 macro_build ((char *) NULL, &icnt, &ex_sym, "addiu", "t,r,j",
11810 mips_gp_register, mips_gp_register, (int) BFD_RELOC_GPREL16);
11811 fix_new (frag_now, f - frag_now->fr_literal,
11812 0, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
11813 fix_new (frag_now, f - frag_now->fr_literal,
11814 0, NULL, 0, 0, BFD_RELOC_LO16);
11816 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
11817 HAVE_64BIT_ADDRESSES ? "daddu" : "addu", "d,v,t",
11818 mips_gp_register, mips_gp_register, reg1);
11820 demand_empty_rest_of_line ();
11825 int ignore ATTRIBUTE_UNUSED;
11827 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11828 .cplocal is ignored. */
11829 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11835 mips_gp_register = tc_get_register (0);
11836 demand_empty_rest_of_line ();
11839 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11840 offset from $sp. The offset is remembered, and after making a PIC
11841 call $gp is restored from that location. */
11844 s_cprestore (ignore)
11845 int ignore ATTRIBUTE_UNUSED;
11850 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11851 .cprestore is ignored. */
11852 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
11858 mips_cprestore_offset = get_absolute_expression ();
11859 mips_cprestore_valid = 1;
11861 ex.X_op = O_constant;
11862 ex.X_add_symbol = NULL;
11863 ex.X_op_symbol = NULL;
11864 ex.X_add_number = mips_cprestore_offset;
11866 macro_build ((char *) NULL, &icnt, &ex, HAVE_32BIT_ADDRESSES ? "sw" : "sd",
11867 "t,o(b)", mips_gp_register, (int) BFD_RELOC_LO16, SP);
11869 demand_empty_rest_of_line ();
11872 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
11873 was given in the preceeding .gpsetup, it results in:
11874 ld $gp, offset($sp)
11876 If a register $reg2 was given there, it results in:
11877 daddiu $gp, $gp, $reg2
11880 s_cpreturn (ignore)
11881 int ignore ATTRIBUTE_UNUSED;
11886 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
11887 We also need NewABI support. */
11888 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11894 if (mips_cpreturn_register == -1)
11896 ex.X_op = O_constant;
11897 ex.X_add_symbol = NULL;
11898 ex.X_op_symbol = NULL;
11899 ex.X_add_number = mips_cpreturn_offset;
11901 macro_build ((char *) NULL, &icnt, &ex, "ld", "t,o(b)",
11902 mips_gp_register, (int) BFD_RELOC_LO16, SP);
11905 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu",
11906 "d,v,t", mips_gp_register, mips_cpreturn_register, 0);
11908 demand_empty_rest_of_line ();
11911 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
11912 code. It sets the offset to use in gp_rel relocations. */
11916 int ignore ATTRIBUTE_UNUSED;
11918 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
11919 We also need NewABI support. */
11920 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11926 mips_gprel_offset = get_absolute_expression ();
11928 demand_empty_rest_of_line ();
11931 /* Handle the .gpword pseudo-op. This is used when generating PIC
11932 code. It generates a 32 bit GP relative reloc. */
11936 int ignore ATTRIBUTE_UNUSED;
11942 /* When not generating PIC code, this is treated as .word. */
11943 if (mips_pic != SVR4_PIC)
11949 label = insn_labels != NULL ? insn_labels->label : NULL;
11950 mips_emit_delays (true);
11952 mips_align (2, 0, label);
11953 mips_clear_insn_labels ();
11957 if (ex.X_op != O_symbol || ex.X_add_number != 0)
11959 as_bad (_("Unsupported use of .gpword"));
11960 ignore_rest_of_line ();
11964 md_number_to_chars (p, (valueT) 0, 4);
11965 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, false,
11966 BFD_RELOC_GPREL32);
11968 demand_empty_rest_of_line ();
11971 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
11972 tables in SVR4 PIC code. */
11976 int ignore ATTRIBUTE_UNUSED;
11981 /* This is ignored when not generating SVR4 PIC code or if this is NewABI
11983 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
11989 /* Add $gp to the register named as an argument. */
11990 reg = tc_get_register (0);
11991 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
11992 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
11993 "d,v,t", reg, reg, mips_gp_register);
11995 demand_empty_rest_of_line ();
11998 /* Handle the .insn pseudo-op. This marks instruction labels in
11999 mips16 mode. This permits the linker to handle them specially,
12000 such as generating jalx instructions when needed. We also make
12001 them odd for the duration of the assembly, in order to generate the
12002 right sort of code. We will make them even in the adjust_symtab
12003 routine, while leaving them marked. This is convenient for the
12004 debugger and the disassembler. The linker knows to make them odd
12009 int ignore ATTRIBUTE_UNUSED;
12011 mips16_mark_labels ();
12013 demand_empty_rest_of_line ();
12016 /* Handle a .stabn directive. We need these in order to mark a label
12017 as being a mips16 text label correctly. Sometimes the compiler
12018 will emit a label, followed by a .stabn, and then switch sections.
12019 If the label and .stabn are in mips16 mode, then the label is
12020 really a mips16 text label. */
12027 mips16_mark_labels ();
12032 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12036 s_mips_weakext (ignore)
12037 int ignore ATTRIBUTE_UNUSED;
12044 name = input_line_pointer;
12045 c = get_symbol_end ();
12046 symbolP = symbol_find_or_make (name);
12047 S_SET_WEAK (symbolP);
12048 *input_line_pointer = c;
12050 SKIP_WHITESPACE ();
12052 if (! is_end_of_line[(unsigned char) *input_line_pointer])
12054 if (S_IS_DEFINED (symbolP))
12056 as_bad ("ignoring attempt to redefine symbol %s",
12057 S_GET_NAME (symbolP));
12058 ignore_rest_of_line ();
12062 if (*input_line_pointer == ',')
12064 ++input_line_pointer;
12065 SKIP_WHITESPACE ();
12069 if (exp.X_op != O_symbol)
12071 as_bad ("bad .weakext directive");
12072 ignore_rest_of_line ();
12075 symbol_set_value_expression (symbolP, &exp);
12078 demand_empty_rest_of_line ();
12081 /* Parse a register string into a number. Called from the ECOFF code
12082 to parse .frame. The argument is non-zero if this is the frame
12083 register, so that we can record it in mips_frame_reg. */
12086 tc_get_register (frame)
12091 SKIP_WHITESPACE ();
12092 if (*input_line_pointer++ != '$')
12094 as_warn (_("expected `$'"));
12097 else if (ISDIGIT (*input_line_pointer))
12099 reg = get_absolute_expression ();
12100 if (reg < 0 || reg >= 32)
12102 as_warn (_("Bad register number"));
12108 if (strncmp (input_line_pointer, "ra", 2) == 0)
12111 input_line_pointer += 2;
12113 else if (strncmp (input_line_pointer, "fp", 2) == 0)
12116 input_line_pointer += 2;
12118 else if (strncmp (input_line_pointer, "sp", 2) == 0)
12121 input_line_pointer += 2;
12123 else if (strncmp (input_line_pointer, "gp", 2) == 0)
12126 input_line_pointer += 2;
12128 else if (strncmp (input_line_pointer, "at", 2) == 0)
12131 input_line_pointer += 2;
12133 else if (strncmp (input_line_pointer, "kt0", 3) == 0)
12136 input_line_pointer += 3;
12138 else if (strncmp (input_line_pointer, "kt1", 3) == 0)
12141 input_line_pointer += 3;
12143 else if (strncmp (input_line_pointer, "zero", 4) == 0)
12146 input_line_pointer += 4;
12150 as_warn (_("Unrecognized register name"));
12152 while (ISALNUM(*input_line_pointer))
12153 input_line_pointer++;
12158 mips_frame_reg = reg != 0 ? reg : SP;
12159 mips_frame_reg_valid = 1;
12160 mips_cprestore_valid = 0;
12166 md_section_align (seg, addr)
12170 int align = bfd_get_section_alignment (stdoutput, seg);
12173 /* We don't need to align ELF sections to the full alignment.
12174 However, Irix 5 may prefer that we align them at least to a 16
12175 byte boundary. We don't bother to align the sections if we are
12176 targeted for an embedded system. */
12177 if (strcmp (TARGET_OS, "elf") == 0)
12183 return ((addr + (1 << align) - 1) & (-1 << align));
12186 /* Utility routine, called from above as well. If called while the
12187 input file is still being read, it's only an approximation. (For
12188 example, a symbol may later become defined which appeared to be
12189 undefined earlier.) */
12192 nopic_need_relax (sym, before_relaxing)
12194 int before_relaxing;
12199 if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0)
12201 const char *symname;
12204 /* Find out whether this symbol can be referenced off the $gp
12205 register. It can be if it is smaller than the -G size or if
12206 it is in the .sdata or .sbss section. Certain symbols can
12207 not be referenced off the $gp, although it appears as though
12209 symname = S_GET_NAME (sym);
12210 if (symname != (const char *) NULL
12211 && (strcmp (symname, "eprol") == 0
12212 || strcmp (symname, "etext") == 0
12213 || strcmp (symname, "_gp") == 0
12214 || strcmp (symname, "edata") == 0
12215 || strcmp (symname, "_fbss") == 0
12216 || strcmp (symname, "_fdata") == 0
12217 || strcmp (symname, "_ftext") == 0
12218 || strcmp (symname, "end") == 0
12219 || strcmp (symname, "_gp_disp") == 0))
12221 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
12223 #ifndef NO_ECOFF_DEBUGGING
12224 || (symbol_get_obj (sym)->ecoff_extern_size != 0
12225 && (symbol_get_obj (sym)->ecoff_extern_size
12226 <= g_switch_value))
12228 /* We must defer this decision until after the whole
12229 file has been read, since there might be a .extern
12230 after the first use of this symbol. */
12231 || (before_relaxing
12232 #ifndef NO_ECOFF_DEBUGGING
12233 && symbol_get_obj (sym)->ecoff_extern_size == 0
12235 && S_GET_VALUE (sym) == 0)
12236 || (S_GET_VALUE (sym) != 0
12237 && S_GET_VALUE (sym) <= g_switch_value)))
12241 const char *segname;
12243 segname = segment_name (S_GET_SEGMENT (sym));
12244 assert (strcmp (segname, ".lit8") != 0
12245 && strcmp (segname, ".lit4") != 0);
12246 change = (strcmp (segname, ".sdata") != 0
12247 && strcmp (segname, ".sbss") != 0
12248 && strncmp (segname, ".sdata.", 7) != 0
12249 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
12254 /* We are not optimizing for the $gp register. */
12258 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12259 extended opcode. SEC is the section the frag is in. */
12262 mips16_extended_frag (fragp, sec, stretch)
12268 register const struct mips16_immed_operand *op;
12270 int mintiny, maxtiny;
12274 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
12276 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
12279 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
12280 op = mips16_immed_operands;
12281 while (op->type != type)
12284 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
12289 if (type == '<' || type == '>' || type == '[' || type == ']')
12292 maxtiny = 1 << op->nbits;
12297 maxtiny = (1 << op->nbits) - 1;
12302 mintiny = - (1 << (op->nbits - 1));
12303 maxtiny = (1 << (op->nbits - 1)) - 1;
12306 sym_frag = symbol_get_frag (fragp->fr_symbol);
12307 val = S_GET_VALUE (fragp->fr_symbol);
12308 symsec = S_GET_SEGMENT (fragp->fr_symbol);
12314 /* We won't have the section when we are called from
12315 mips_relax_frag. However, we will always have been called
12316 from md_estimate_size_before_relax first. If this is a
12317 branch to a different section, we mark it as such. If SEC is
12318 NULL, and the frag is not marked, then it must be a branch to
12319 the same section. */
12322 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
12327 /* Must have been called from md_estimate_size_before_relax. */
12330 fragp->fr_subtype =
12331 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12333 /* FIXME: We should support this, and let the linker
12334 catch branches and loads that are out of range. */
12335 as_bad_where (fragp->fr_file, fragp->fr_line,
12336 _("unsupported PC relative reference to different section"));
12340 if (fragp != sym_frag && sym_frag->fr_address == 0)
12341 /* Assume non-extended on the first relaxation pass.
12342 The address we have calculated will be bogus if this is
12343 a forward branch to another frag, as the forward frag
12344 will have fr_address == 0. */
12348 /* In this case, we know for sure that the symbol fragment is in
12349 the same section. If the relax_marker of the symbol fragment
12350 differs from the relax_marker of this fragment, we have not
12351 yet adjusted the symbol fragment fr_address. We want to add
12352 in STRETCH in order to get a better estimate of the address.
12353 This particularly matters because of the shift bits. */
12355 && sym_frag->relax_marker != fragp->relax_marker)
12359 /* Adjust stretch for any alignment frag. Note that if have
12360 been expanding the earlier code, the symbol may be
12361 defined in what appears to be an earlier frag. FIXME:
12362 This doesn't handle the fr_subtype field, which specifies
12363 a maximum number of bytes to skip when doing an
12365 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
12367 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
12370 stretch = - ((- stretch)
12371 & ~ ((1 << (int) f->fr_offset) - 1));
12373 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
12382 addr = fragp->fr_address + fragp->fr_fix;
12384 /* The base address rules are complicated. The base address of
12385 a branch is the following instruction. The base address of a
12386 PC relative load or add is the instruction itself, but if it
12387 is in a delay slot (in which case it can not be extended) use
12388 the address of the instruction whose delay slot it is in. */
12389 if (type == 'p' || type == 'q')
12393 /* If we are currently assuming that this frag should be
12394 extended, then, the current address is two bytes
12396 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12399 /* Ignore the low bit in the target, since it will be set
12400 for a text label. */
12401 if ((val & 1) != 0)
12404 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
12406 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
12409 val -= addr & ~ ((1 << op->shift) - 1);
12411 /* Branch offsets have an implicit 0 in the lowest bit. */
12412 if (type == 'p' || type == 'q')
12415 /* If any of the shifted bits are set, we must use an extended
12416 opcode. If the address depends on the size of this
12417 instruction, this can lead to a loop, so we arrange to always
12418 use an extended opcode. We only check this when we are in
12419 the main relaxation loop, when SEC is NULL. */
12420 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
12422 fragp->fr_subtype =
12423 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12427 /* If we are about to mark a frag as extended because the value
12428 is precisely maxtiny + 1, then there is a chance of an
12429 infinite loop as in the following code:
12434 In this case when the la is extended, foo is 0x3fc bytes
12435 away, so the la can be shrunk, but then foo is 0x400 away, so
12436 the la must be extended. To avoid this loop, we mark the
12437 frag as extended if it was small, and is about to become
12438 extended with a value of maxtiny + 1. */
12439 if (val == ((maxtiny + 1) << op->shift)
12440 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
12443 fragp->fr_subtype =
12444 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12448 else if (symsec != absolute_section && sec != NULL)
12449 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
12451 if ((val & ((1 << op->shift) - 1)) != 0
12452 || val < (mintiny << op->shift)
12453 || val > (maxtiny << op->shift))
12459 /* Estimate the size of a frag before relaxing. Unless this is the
12460 mips16, we are not really relaxing here, and the final size is
12461 encoded in the subtype information. For the mips16, we have to
12462 decide whether we are using an extended opcode or not. */
12465 md_estimate_size_before_relax (fragp, segtype)
12470 boolean linkonce = false;
12472 if (RELAX_MIPS16_P (fragp->fr_subtype))
12473 /* We don't want to modify the EXTENDED bit here; it might get us
12474 into infinite loops. We change it only in mips_relax_frag(). */
12475 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
12477 if (mips_pic == NO_PIC)
12479 change = nopic_need_relax (fragp->fr_symbol, 0);
12481 else if (mips_pic == SVR4_PIC)
12486 sym = fragp->fr_symbol;
12488 /* Handle the case of a symbol equated to another symbol. */
12489 while (symbol_equated_reloc_p (sym))
12493 /* It's possible to get a loop here in a badly written
12495 n = symbol_get_value_expression (sym)->X_add_symbol;
12501 symsec = S_GET_SEGMENT (sym);
12503 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12504 if (symsec != segtype && ! S_IS_LOCAL (sym))
12506 if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE)
12510 /* The GNU toolchain uses an extension for ELF: a section
12511 beginning with the magic string .gnu.linkonce is a linkonce
12513 if (strncmp (segment_name (symsec), ".gnu.linkonce",
12514 sizeof ".gnu.linkonce" - 1) == 0)
12518 /* This must duplicate the test in adjust_reloc_syms. */
12519 change = (symsec != &bfd_und_section
12520 && symsec != &bfd_abs_section
12521 && ! bfd_is_com_section (symsec)
12524 /* A global or weak symbol is treated as external. */
12525 && (OUTPUT_FLAVOR != bfd_target_elf_flavour
12526 || (! S_IS_WEAK (sym)
12527 && (! S_IS_EXTERNAL (sym)
12528 || mips_pic == EMBEDDED_PIC)))
12537 /* Record the offset to the first reloc in the fr_opcode field.
12538 This lets md_convert_frag and tc_gen_reloc know that the code
12539 must be expanded. */
12540 fragp->fr_opcode = (fragp->fr_literal
12542 - RELAX_OLD (fragp->fr_subtype)
12543 + RELAX_RELOC1 (fragp->fr_subtype));
12544 /* FIXME: This really needs as_warn_where. */
12545 if (RELAX_WARN (fragp->fr_subtype))
12546 as_warn (_("AT used after \".set noat\" or macro used after "
12547 "\".set nomacro\""));
12549 return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype);
12555 /* This is called to see whether a reloc against a defined symbol
12556 should be converted into a reloc against a section. Don't adjust
12557 MIPS16 jump relocations, so we don't have to worry about the format
12558 of the offset in the .o file. Don't adjust relocations against
12559 mips16 symbols, so that the linker can find them if it needs to set
12563 mips_fix_adjustable (fixp)
12566 if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
12569 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12570 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12573 if (fixp->fx_addsy == NULL)
12577 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
12578 && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
12579 && fixp->fx_subsy == NULL)
12586 /* Translate internal representation of relocation info to BFD target
12590 tc_gen_reloc (section, fixp)
12591 asection *section ATTRIBUTE_UNUSED;
12594 static arelent *retval[4];
12596 bfd_reloc_code_real_type code;
12598 reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent));
12601 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
12602 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
12603 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
12605 if (mips_pic == EMBEDDED_PIC
12606 && SWITCH_TABLE (fixp))
12608 /* For a switch table entry we use a special reloc. The addend
12609 is actually the difference between the reloc address and the
12611 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
12612 if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour)
12613 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
12614 fixp->fx_r_type = BFD_RELOC_GPREL32;
12616 else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16)
12618 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
12619 reloc->addend = fixp->fx_addnumber;
12622 /* We use a special addend for an internal RELLO reloc. */
12623 if (symbol_section_p (fixp->fx_addsy))
12624 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
12626 reloc->addend = fixp->fx_addnumber + reloc->address;
12629 else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
12631 assert (fixp->fx_next != NULL
12632 && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16);
12634 /* The reloc is relative to the RELLO; adjust the addend
12636 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
12637 reloc->addend = fixp->fx_next->fx_addnumber;
12640 /* We use a special addend for an internal RELHI reloc. */
12641 if (symbol_section_p (fixp->fx_addsy))
12642 reloc->addend = (fixp->fx_next->fx_frag->fr_address
12643 + fixp->fx_next->fx_where
12644 - S_GET_VALUE (fixp->fx_subsy));
12646 reloc->addend = (fixp->fx_addnumber
12647 + fixp->fx_next->fx_frag->fr_address
12648 + fixp->fx_next->fx_where);
12651 else if (fixp->fx_pcrel == 0 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
12652 reloc->addend = fixp->fx_addnumber;
12655 if (OUTPUT_FLAVOR != bfd_target_aout_flavour)
12656 /* A gruesome hack which is a result of the gruesome gas reloc
12658 reloc->addend = reloc->address;
12660 reloc->addend = -reloc->address;
12663 /* If this is a variant frag, we may need to adjust the existing
12664 reloc and generate a new one. */
12665 if (fixp->fx_frag->fr_opcode != NULL
12666 && ((fixp->fx_r_type == BFD_RELOC_GPREL16
12668 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
12669 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16
12670 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
12671 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16
12672 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
12673 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)
12678 assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype));
12680 /* If this is not the last reloc in this frag, then we have two
12681 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
12682 CALL_HI16/CALL_LO16, both of which are being replaced. Let
12683 the second one handle all of them. */
12684 if (fixp->fx_next != NULL
12685 && fixp->fx_frag == fixp->fx_next->fx_frag)
12687 assert ((fixp->fx_r_type == BFD_RELOC_GPREL16
12688 && fixp->fx_next->fx_r_type == BFD_RELOC_GPREL16)
12689 || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
12690 && (fixp->fx_next->fx_r_type
12691 == BFD_RELOC_MIPS_GOT_LO16))
12692 || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
12693 && (fixp->fx_next->fx_r_type
12694 == BFD_RELOC_MIPS_CALL_LO16)));
12699 fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal;
12700 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
12701 reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent));
12703 reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
12704 *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
12705 reloc2->address = (reloc->address
12706 + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype)
12707 - RELAX_RELOC1 (fixp->fx_frag->fr_subtype)));
12708 reloc2->addend = fixp->fx_addnumber;
12709 reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16);
12710 assert (reloc2->howto != NULL);
12712 if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype))
12716 reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent));
12719 reloc3->address += 4;
12722 if (mips_pic == NO_PIC)
12724 assert (fixp->fx_r_type == BFD_RELOC_GPREL16);
12725 fixp->fx_r_type = BFD_RELOC_HI16_S;
12727 else if (mips_pic == SVR4_PIC)
12729 switch (fixp->fx_r_type)
12733 case BFD_RELOC_MIPS_GOT16:
12735 case BFD_RELOC_MIPS_GOT_LO16:
12736 case BFD_RELOC_MIPS_CALL_LO16:
12737 fixp->fx_r_type = BFD_RELOC_MIPS_GOT16;
12739 case BFD_RELOC_MIPS_CALL16:
12742 /* BFD_RELOC_MIPS_GOT16;*/
12743 fixp->fx_r_type = BFD_RELOC_MIPS_GOT_PAGE;
12744 reloc2->howto = bfd_reloc_type_lookup
12745 (stdoutput, BFD_RELOC_MIPS_GOT_OFST);
12748 fixp->fx_r_type = BFD_RELOC_MIPS_GOT16;
12755 /* newabi uses R_MIPS_GOT_DISP for local symbols */
12756 if (HAVE_NEWABI && BFD_RELOC_MIPS_GOT_LO16)
12758 fixp->fx_r_type = BFD_RELOC_MIPS_GOT_DISP;
12763 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
12764 entry to be used in the relocation's section offset. */
12765 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12767 reloc->address = reloc->addend;
12771 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
12772 fixup_segment converted a non-PC relative reloc into a PC
12773 relative reloc. In such a case, we need to convert the reloc
12775 code = fixp->fx_r_type;
12776 if (fixp->fx_pcrel)
12781 code = BFD_RELOC_8_PCREL;
12784 code = BFD_RELOC_16_PCREL;
12787 code = BFD_RELOC_32_PCREL;
12790 code = BFD_RELOC_64_PCREL;
12792 case BFD_RELOC_8_PCREL:
12793 case BFD_RELOC_16_PCREL:
12794 case BFD_RELOC_32_PCREL:
12795 case BFD_RELOC_64_PCREL:
12796 case BFD_RELOC_16_PCREL_S2:
12797 case BFD_RELOC_PCREL_HI16_S:
12798 case BFD_RELOC_PCREL_LO16:
12801 as_bad_where (fixp->fx_file, fixp->fx_line,
12802 _("Cannot make %s relocation PC relative"),
12803 bfd_get_reloc_code_name (code));
12808 /* md_apply_fix3 has a double-subtraction hack to get
12809 bfd_install_relocation to behave nicely. GPREL relocations are
12810 handled correctly without this hack, so undo it here. We can't
12811 stop md_apply_fix3 from subtracting twice in the first place since
12812 the fake addend is required for variant frags above. */
12813 if (fixp->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour
12814 && (code == BFD_RELOC_GPREL16 || code == BFD_RELOC_MIPS16_GPREL)
12815 && reloc->addend != 0
12816 && mips_need_elf_addend_fixup (fixp))
12817 reloc->addend += S_GET_VALUE (fixp->fx_addsy);
12820 /* To support a PC relative reloc when generating embedded PIC code
12821 for ECOFF, we use a Cygnus extension. We check for that here to
12822 make sure that we don't let such a reloc escape normally. */
12823 if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
12824 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
12825 && code == BFD_RELOC_16_PCREL_S2
12826 && mips_pic != EMBEDDED_PIC)
12827 reloc->howto = NULL;
12829 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
12831 if (reloc->howto == NULL)
12833 as_bad_where (fixp->fx_file, fixp->fx_line,
12834 _("Can not represent %s relocation in this object file format"),
12835 bfd_get_reloc_code_name (code));
12842 /* Relax a machine dependent frag. This returns the amount by which
12843 the current size of the frag should change. */
12846 mips_relax_frag (fragp, stretch)
12850 if (! RELAX_MIPS16_P (fragp->fr_subtype))
12853 if (mips16_extended_frag (fragp, NULL, stretch))
12855 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12857 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
12862 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12864 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
12871 /* Convert a machine dependent frag. */
12874 md_convert_frag (abfd, asec, fragp)
12875 bfd *abfd ATTRIBUTE_UNUSED;
12882 if (RELAX_MIPS16_P (fragp->fr_subtype))
12885 register const struct mips16_immed_operand *op;
12886 boolean small, ext;
12889 unsigned long insn;
12890 boolean use_extend;
12891 unsigned short extend;
12893 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
12894 op = mips16_immed_operands;
12895 while (op->type != type)
12898 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12909 resolve_symbol_value (fragp->fr_symbol);
12910 val = S_GET_VALUE (fragp->fr_symbol);
12915 addr = fragp->fr_address + fragp->fr_fix;
12917 /* The rules for the base address of a PC relative reloc are
12918 complicated; see mips16_extended_frag. */
12919 if (type == 'p' || type == 'q')
12924 /* Ignore the low bit in the target, since it will be
12925 set for a text label. */
12926 if ((val & 1) != 0)
12929 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
12931 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
12934 addr &= ~ (addressT) ((1 << op->shift) - 1);
12937 /* Make sure the section winds up with the alignment we have
12940 record_alignment (asec, op->shift);
12944 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
12945 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
12946 as_warn_where (fragp->fr_file, fragp->fr_line,
12947 _("extended instruction in delay slot"));
12949 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
12951 if (target_big_endian)
12952 insn = bfd_getb16 (buf);
12954 insn = bfd_getl16 (buf);
12956 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
12957 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
12958 small, ext, &insn, &use_extend, &extend);
12962 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
12963 fragp->fr_fix += 2;
12967 md_number_to_chars ((char *) buf, insn, 2);
12968 fragp->fr_fix += 2;
12973 if (fragp->fr_opcode == NULL)
12976 old = RELAX_OLD (fragp->fr_subtype);
12977 new = RELAX_NEW (fragp->fr_subtype);
12978 fixptr = fragp->fr_literal + fragp->fr_fix;
12981 memcpy (fixptr - old, fixptr, new);
12983 fragp->fr_fix += new - old;
12989 /* This function is called after the relocs have been generated.
12990 We've been storing mips16 text labels as odd. Here we convert them
12991 back to even for the convenience of the debugger. */
12994 mips_frob_file_after_relocs ()
12997 unsigned int count, i;
12999 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
13002 syms = bfd_get_outsymbols (stdoutput);
13003 count = bfd_get_symcount (stdoutput);
13004 for (i = 0; i < count; i++, syms++)
13006 if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16
13007 && ((*syms)->value & 1) != 0)
13009 (*syms)->value &= ~1;
13010 /* If the symbol has an odd size, it was probably computed
13011 incorrectly, so adjust that as well. */
13012 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
13013 ++elf_symbol (*syms)->internal_elf_sym.st_size;
13020 /* This function is called whenever a label is defined. It is used
13021 when handling branch delays; if a branch has a label, we assume we
13022 can not move it. */
13025 mips_define_label (sym)
13028 struct insn_label_list *l;
13030 if (free_insn_labels == NULL)
13031 l = (struct insn_label_list *) xmalloc (sizeof *l);
13034 l = free_insn_labels;
13035 free_insn_labels = l->next;
13039 l->next = insn_labels;
13043 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13045 /* Some special processing for a MIPS ELF file. */
13048 mips_elf_final_processing ()
13050 /* Write out the register information. */
13051 if (mips_abi != N64_ABI)
13055 s.ri_gprmask = mips_gprmask;
13056 s.ri_cprmask[0] = mips_cprmask[0];
13057 s.ri_cprmask[1] = mips_cprmask[1];
13058 s.ri_cprmask[2] = mips_cprmask[2];
13059 s.ri_cprmask[3] = mips_cprmask[3];
13060 /* The gp_value field is set by the MIPS ELF backend. */
13062 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
13063 ((Elf32_External_RegInfo *)
13064 mips_regmask_frag));
13068 Elf64_Internal_RegInfo s;
13070 s.ri_gprmask = mips_gprmask;
13072 s.ri_cprmask[0] = mips_cprmask[0];
13073 s.ri_cprmask[1] = mips_cprmask[1];
13074 s.ri_cprmask[2] = mips_cprmask[2];
13075 s.ri_cprmask[3] = mips_cprmask[3];
13076 /* The gp_value field is set by the MIPS ELF backend. */
13078 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
13079 ((Elf64_External_RegInfo *)
13080 mips_regmask_frag));
13083 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13084 sort of BFD interface for this. */
13085 if (mips_any_noreorder)
13086 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
13087 if (mips_pic != NO_PIC)
13088 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
13090 /* Set MIPS ELF flags for ASEs. */
13091 if (file_ase_mips16)
13092 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
13093 #if 0 /* XXX FIXME */
13094 if (file_ase_mips3d)
13095 elf_elfheader (stdoutput)->e_flags |= ???;
13098 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
13100 /* Set the MIPS ELF ABI flags. */
13101 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
13102 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
13103 else if (mips_abi == O64_ABI)
13104 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
13105 else if (mips_abi == EABI_ABI)
13107 if (!file_mips_gp32)
13108 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
13110 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
13112 else if (mips_abi == N32_ABI)
13113 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
13115 /* Nothing to do for N64_ABI. */
13117 if (mips_32bitmode)
13118 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
13121 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13123 typedef struct proc {
13125 unsigned long reg_mask;
13126 unsigned long reg_offset;
13127 unsigned long fpreg_mask;
13128 unsigned long fpreg_offset;
13129 unsigned long frame_offset;
13130 unsigned long frame_reg;
13131 unsigned long pc_reg;
13134 static procS cur_proc;
13135 static procS *cur_proc_ptr;
13136 static int numprocs;
13138 /* Fill in an rs_align_code fragment. */
13141 mips_handle_align (fragp)
13144 if (fragp->fr_type != rs_align_code)
13147 if (mips_opts.mips16)
13149 static const unsigned char be_nop[] = { 0x65, 0x00 };
13150 static const unsigned char le_nop[] = { 0x00, 0x65 };
13155 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
13156 p = fragp->fr_literal + fragp->fr_fix;
13164 memcpy (p, (target_big_endian ? be_nop : le_nop), 2);
13168 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13179 /* check for premature end, nesting errors, etc */
13181 as_warn (_("missing .end at end of assembly"));
13190 if (*input_line_pointer == '-')
13192 ++input_line_pointer;
13195 if (!ISDIGIT (*input_line_pointer))
13196 as_bad (_("expected simple number"));
13197 if (input_line_pointer[0] == '0')
13199 if (input_line_pointer[1] == 'x')
13201 input_line_pointer += 2;
13202 while (ISXDIGIT (*input_line_pointer))
13205 val |= hex_value (*input_line_pointer++);
13207 return negative ? -val : val;
13211 ++input_line_pointer;
13212 while (ISDIGIT (*input_line_pointer))
13215 val |= *input_line_pointer++ - '0';
13217 return negative ? -val : val;
13220 if (!ISDIGIT (*input_line_pointer))
13222 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13223 *input_line_pointer, *input_line_pointer);
13224 as_warn (_("invalid number"));
13227 while (ISDIGIT (*input_line_pointer))
13230 val += *input_line_pointer++ - '0';
13232 return negative ? -val : val;
13235 /* The .file directive; just like the usual .file directive, but there
13236 is an initial number which is the ECOFF file index. In the non-ECOFF
13237 case .file implies DWARF-2. */
13241 int x ATTRIBUTE_UNUSED;
13243 static int first_file_directive = 0;
13245 if (ECOFF_DEBUGGING)
13254 filename = dwarf2_directive_file (0);
13256 /* Versions of GCC up to 3.1 start files with a ".file"
13257 directive even for stabs output. Make sure that this
13258 ".file" is handled. Note that you need a version of GCC
13259 after 3.1 in order to support DWARF-2 on MIPS. */
13260 if (filename != NULL && ! first_file_directive)
13262 (void) new_logical_line (filename, -1);
13263 s_app_file_string (filename);
13265 first_file_directive = 1;
13269 /* The .loc directive, implying DWARF-2. */
13273 int x ATTRIBUTE_UNUSED;
13275 if (!ECOFF_DEBUGGING)
13276 dwarf2_directive_loc (0);
13279 /* The .end directive. */
13283 int x ATTRIBUTE_UNUSED;
13288 /* Following functions need their own .frame and .cprestore directives. */
13289 mips_frame_reg_valid = 0;
13290 mips_cprestore_valid = 0;
13292 if (!is_end_of_line[(unsigned char) *input_line_pointer])
13295 demand_empty_rest_of_line ();
13300 #ifdef BFD_ASSEMBLER
13301 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
13306 if (now_seg != data_section && now_seg != bss_section)
13313 as_warn (_(".end not in text section"));
13317 as_warn (_(".end directive without a preceding .ent directive."));
13318 demand_empty_rest_of_line ();
13324 assert (S_GET_NAME (p));
13325 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym)))
13326 as_warn (_(".end symbol does not match .ent symbol."));
13328 if (debug_type == DEBUG_STABS)
13329 stabs_generate_asm_endfunc (S_GET_NAME (p),
13333 as_warn (_(".end directive missing or unknown symbol"));
13336 /* Generate a .pdr section. */
13337 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
13339 segT saved_seg = now_seg;
13340 subsegT saved_subseg = now_subseg;
13345 dot = frag_now_fix ();
13347 #ifdef md_flush_pending_output
13348 md_flush_pending_output ();
13352 subseg_set (pdr_seg, 0);
13354 /* Write the symbol. */
13355 exp.X_op = O_symbol;
13356 exp.X_add_symbol = p;
13357 exp.X_add_number = 0;
13358 emit_expr (&exp, 4);
13360 fragp = frag_more (7 * 4);
13362 md_number_to_chars (fragp, (valueT) cur_proc_ptr->reg_mask, 4);
13363 md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4);
13364 md_number_to_chars (fragp + 8, (valueT) cur_proc_ptr->fpreg_mask, 4);
13365 md_number_to_chars (fragp + 12, (valueT) cur_proc_ptr->fpreg_offset, 4);
13366 md_number_to_chars (fragp + 16, (valueT) cur_proc_ptr->frame_offset, 4);
13367 md_number_to_chars (fragp + 20, (valueT) cur_proc_ptr->frame_reg, 4);
13368 md_number_to_chars (fragp + 24, (valueT) cur_proc_ptr->pc_reg, 4);
13370 subseg_set (saved_seg, saved_subseg);
13372 #endif /* OBJ_ELF */
13374 cur_proc_ptr = NULL;
13377 /* The .aent and .ent directives. */
13386 symbolP = get_symbol ();
13387 if (*input_line_pointer == ',')
13388 ++input_line_pointer;
13389 SKIP_WHITESPACE ();
13390 if (ISDIGIT (*input_line_pointer)
13391 || *input_line_pointer == '-')
13394 #ifdef BFD_ASSEMBLER
13395 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
13400 if (now_seg != data_section && now_seg != bss_section)
13407 as_warn (_(".ent or .aent not in text section."));
13409 if (!aent && cur_proc_ptr)
13410 as_warn (_("missing .end"));
13414 /* This function needs its own .frame and .cprestore directives. */
13415 mips_frame_reg_valid = 0;
13416 mips_cprestore_valid = 0;
13418 cur_proc_ptr = &cur_proc;
13419 memset (cur_proc_ptr, '\0', sizeof (procS));
13421 cur_proc_ptr->isym = symbolP;
13423 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
13427 if (debug_type == DEBUG_STABS)
13428 stabs_generate_asm_func (S_GET_NAME (symbolP),
13429 S_GET_NAME (symbolP));
13432 demand_empty_rest_of_line ();
13435 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13436 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13437 s_mips_frame is used so that we can set the PDR information correctly.
13438 We can't use the ecoff routines because they make reference to the ecoff
13439 symbol table (in the mdebug section). */
13442 s_mips_frame (ignore)
13443 int ignore ATTRIBUTE_UNUSED;
13446 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
13450 if (cur_proc_ptr == (procS *) NULL)
13452 as_warn (_(".frame outside of .ent"));
13453 demand_empty_rest_of_line ();
13457 cur_proc_ptr->frame_reg = tc_get_register (1);
13459 SKIP_WHITESPACE ();
13460 if (*input_line_pointer++ != ','
13461 || get_absolute_expression_and_terminator (&val) != ',')
13463 as_warn (_("Bad .frame directive"));
13464 --input_line_pointer;
13465 demand_empty_rest_of_line ();
13469 cur_proc_ptr->frame_offset = val;
13470 cur_proc_ptr->pc_reg = tc_get_register (0);
13472 demand_empty_rest_of_line ();
13475 #endif /* OBJ_ELF */
13479 /* The .fmask and .mask directives. If the mdebug section is present
13480 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13481 embedded targets, s_mips_mask is used so that we can set the PDR
13482 information correctly. We can't use the ecoff routines because they
13483 make reference to the ecoff symbol table (in the mdebug section). */
13486 s_mips_mask (reg_type)
13490 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
13494 if (cur_proc_ptr == (procS *) NULL)
13496 as_warn (_(".mask/.fmask outside of .ent"));
13497 demand_empty_rest_of_line ();
13501 if (get_absolute_expression_and_terminator (&mask) != ',')
13503 as_warn (_("Bad .mask/.fmask directive"));
13504 --input_line_pointer;
13505 demand_empty_rest_of_line ();
13509 off = get_absolute_expression ();
13511 if (reg_type == 'F')
13513 cur_proc_ptr->fpreg_mask = mask;
13514 cur_proc_ptr->fpreg_offset = off;
13518 cur_proc_ptr->reg_mask = mask;
13519 cur_proc_ptr->reg_offset = off;
13522 demand_empty_rest_of_line ();
13525 #endif /* OBJ_ELF */
13526 s_ignore (reg_type);
13529 /* The .loc directive. */
13540 assert (now_seg == text_section);
13542 lineno = get_number ();
13543 addroff = frag_now_fix ();
13545 symbolP = symbol_new ("", N_SLINE, addroff, frag_now);
13546 S_SET_TYPE (symbolP, N_SLINE);
13547 S_SET_OTHER (symbolP, 0);
13548 S_SET_DESC (symbolP, lineno);
13549 symbolP->sy_segment = now_seg;
13553 /* A table describing all the processors gas knows about. Names are
13554 matched in the order listed.
13556 To ease comparison, please keep this table in the same order as
13557 gcc's mips_cpu_info_table[]. */
13558 static const struct mips_cpu_info mips_cpu_info_table[] =
13560 /* Entries for generic ISAs */
13561 { "mips1", 1, ISA_MIPS1, CPU_R3000 },
13562 { "mips2", 1, ISA_MIPS2, CPU_R6000 },
13563 { "mips3", 1, ISA_MIPS3, CPU_R4000 },
13564 { "mips4", 1, ISA_MIPS4, CPU_R8000 },
13565 { "mips5", 1, ISA_MIPS5, CPU_MIPS5 },
13566 { "mips32", 1, ISA_MIPS32, CPU_MIPS32 },
13567 { "mips64", 1, ISA_MIPS64, CPU_MIPS64 },
13570 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
13571 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
13572 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
13575 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
13578 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
13579 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
13580 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
13581 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
13582 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
13583 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
13584 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
13585 { "orion", 0, ISA_MIPS3, CPU_R4600 },
13586 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
13589 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
13590 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
13591 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
13592 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
13593 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
13594 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
13595 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
13596 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
13597 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
13598 { "r7000", 0, ISA_MIPS4, CPU_R5000 },
13601 { "4kc", 0, ISA_MIPS32, CPU_MIPS32, },
13602 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
13603 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
13606 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
13607 { "20kc", 0, ISA_MIPS64, CPU_MIPS64 },
13609 /* Broadcom SB-1 CPU core */
13610 { "sb1", 0, ISA_MIPS64, CPU_SB1 },
13617 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
13618 with a final "000" replaced by "k". Ignore case.
13620 Note: this function is shared between GCC and GAS. */
13623 mips_strict_matching_cpu_name_p (canonical, given)
13624 const char *canonical, *given;
13626 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
13627 given++, canonical++;
13629 return ((*given == 0 && *canonical == 0)
13630 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
13634 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
13635 CPU name. We've traditionally allowed a lot of variation here.
13637 Note: this function is shared between GCC and GAS. */
13640 mips_matching_cpu_name_p (canonical, given)
13641 const char *canonical, *given;
13643 /* First see if the name matches exactly, or with a final "000"
13644 turned into "k". */
13645 if (mips_strict_matching_cpu_name_p (canonical, given))
13648 /* If not, try comparing based on numerical designation alone.
13649 See if GIVEN is an unadorned number, or 'r' followed by a number. */
13650 if (TOLOWER (*given) == 'r')
13652 if (!ISDIGIT (*given))
13655 /* Skip over some well-known prefixes in the canonical name,
13656 hoping to find a number there too. */
13657 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
13659 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
13661 else if (TOLOWER (canonical[0]) == 'r')
13664 return mips_strict_matching_cpu_name_p (canonical, given);
13668 /* Parse an option that takes the name of a processor as its argument.
13669 OPTION is the name of the option and CPU_STRING is the argument.
13670 Return the corresponding processor enumeration if the CPU_STRING is
13671 recognized, otherwise report an error and return null.
13673 A similar function exists in GCC. */
13675 static const struct mips_cpu_info *
13676 mips_parse_cpu (option, cpu_string)
13677 const char *option, *cpu_string;
13679 const struct mips_cpu_info *p;
13681 /* 'from-abi' selects the most compatible architecture for the given
13682 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
13683 EABIs, we have to decide whether we're using the 32-bit or 64-bit
13684 version. Look first at the -mgp options, if given, otherwise base
13685 the choice on MIPS_DEFAULT_64BIT.
13687 Treat NO_ABI like the EABIs. One reason to do this is that the
13688 plain 'mips' and 'mips64' configs have 'from-abi' as their default
13689 architecture. This code picks MIPS I for 'mips' and MIPS III for
13690 'mips64', just as we did in the days before 'from-abi'. */
13691 if (strcasecmp (cpu_string, "from-abi") == 0)
13693 if (ABI_NEEDS_32BIT_REGS (mips_abi))
13694 return mips_cpu_info_from_isa (ISA_MIPS1);
13696 if (ABI_NEEDS_64BIT_REGS (mips_abi))
13697 return mips_cpu_info_from_isa (ISA_MIPS3);
13699 if (file_mips_gp32 >= 0)
13700 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
13702 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
13707 /* 'default' has traditionally been a no-op. Probably not very useful. */
13708 if (strcasecmp (cpu_string, "default") == 0)
13711 for (p = mips_cpu_info_table; p->name != 0; p++)
13712 if (mips_matching_cpu_name_p (p->name, cpu_string))
13715 as_bad ("Bad value (%s) for %s", cpu_string, option);
13719 /* Return the canonical processor information for ISA (a member of the
13720 ISA_MIPS* enumeration). */
13722 static const struct mips_cpu_info *
13723 mips_cpu_info_from_isa (isa)
13728 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
13729 if (mips_cpu_info_table[i].is_isa
13730 && isa == mips_cpu_info_table[i].isa)
13731 return (&mips_cpu_info_table[i]);
13737 show (stream, string, col_p, first_p)
13739 const char *string;
13745 fprintf (stream, "%24s", "");
13750 fprintf (stream, ", ");
13754 if (*col_p + strlen (string) > 72)
13756 fprintf (stream, "\n%24s", "");
13760 fprintf (stream, "%s", string);
13761 *col_p += strlen (string);
13767 md_show_usage (stream)
13773 fprintf (stream, _("\
13775 -membedded-pic generate embedded position independent code\n\
13776 -EB generate big endian output\n\
13777 -EL generate little endian output\n\
13778 -g, -g2 do not remove unneeded NOPs or swap branches\n\
13779 -G NUM allow referencing objects up to NUM bytes\n\
13780 implicitly with the gp register [default 8]\n"));
13781 fprintf (stream, _("\
13782 -mips1 generate MIPS ISA I instructions\n\
13783 -mips2 generate MIPS ISA II instructions\n\
13784 -mips3 generate MIPS ISA III instructions\n\
13785 -mips4 generate MIPS ISA IV instructions\n\
13786 -mips5 generate MIPS ISA V instructions\n\
13787 -mips32 generate MIPS32 ISA instructions\n\
13788 -mips64 generate MIPS64 ISA instructions\n\
13789 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
13793 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
13794 show (stream, mips_cpu_info_table[i].name, &column, &first);
13795 show (stream, "from-abi", &column, &first);
13796 fputc ('\n', stream);
13798 fprintf (stream, _("\
13799 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
13800 -no-mCPU don't generate code specific to CPU.\n\
13801 For -mCPU and -no-mCPU, CPU must be one of:\n"));
13805 show (stream, "3900", &column, &first);
13806 show (stream, "4010", &column, &first);
13807 show (stream, "4100", &column, &first);
13808 show (stream, "4650", &column, &first);
13809 fputc ('\n', stream);
13811 fprintf (stream, _("\
13812 -mips16 generate mips16 instructions\n\
13813 -no-mips16 do not generate mips16 instructions\n"));
13814 fprintf (stream, _("\
13815 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
13816 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
13817 -O0 remove unneeded NOPs, do not swap branches\n\
13818 -O remove unneeded NOPs and swap branches\n\
13819 -n warn about NOPs generated from macros\n\
13820 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
13821 --trap, --no-break trap exception on div by 0 and mult overflow\n\
13822 --break, --no-trap break exception on div by 0 and mult overflow\n"));
13824 fprintf (stream, _("\
13825 -KPIC, -call_shared generate SVR4 position independent code\n\
13826 -non_shared do not generate position independent code\n\
13827 -xgot assume a 32 bit GOT\n\
13828 -mabi=ABI create ABI conformant object file for:\n"));
13832 show (stream, "32", &column, &first);
13833 show (stream, "o64", &column, &first);
13834 show (stream, "n32", &column, &first);
13835 show (stream, "64", &column, &first);
13836 show (stream, "eabi", &column, &first);
13838 fputc ('\n', stream);
13840 fprintf (stream, _("\
13841 -32 create o32 ABI object file (default)\n\
13842 -n32 create n32 ABI object file\n\
13843 -64 create 64 ABI object file\n"));