1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2016 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1];
37 typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define streq(a, b) (strcmp (a, b) == 0)
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug = -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr = FALSE;
86 int mips_flag_pdr = TRUE;
91 static char *mips_regmask_frag;
92 static char *mips_flags_frag;
99 #define PIC_CALL_REG 25
107 #define ILLEGAL_REG (32)
109 #define AT mips_opts.at
111 extern int target_big_endian;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME ".rodata"
116 /* Ways in which an instruction can be "appended" to the output. */
118 /* Just add it normally. */
121 /* Add it normally and then add a nop. */
124 /* Turn an instruction with a delay slot into a "compact" version. */
127 /* Insert the instruction before the last one. */
131 /* Information about an instruction, including its format, operands
135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
136 const struct mips_opcode *insn_mo;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. If we have
140 decided to use an extended MIPS16 instruction, this includes the
142 unsigned long insn_opcode;
144 /* The frag that contains the instruction. */
147 /* The offset into FRAG of the first instruction byte. */
150 /* The relocs associated with the instruction, if any. */
153 /* True if this entry cannot be moved from its current position. */
154 unsigned int fixed_p : 1;
156 /* True if this instruction occurred in a .set noreorder block. */
157 unsigned int noreorder_p : 1;
159 /* True for mips16 instructions that jump to an absolute address. */
160 unsigned int mips16_absolute_jump_p : 1;
162 /* True if this instruction is complete. */
163 unsigned int complete_p : 1;
165 /* True if this instruction is cleared from history by unconditional
167 unsigned int cleared_p : 1;
170 /* The ABI to use. */
181 /* MIPS ABI we are using for this output file. */
182 static enum mips_abi_level mips_abi = NO_ABI;
184 /* Whether or not we have code that can call pic code. */
185 int mips_abicalls = FALSE;
187 /* Whether or not we have code which can be put into a shared
189 static bfd_boolean mips_in_shared = TRUE;
191 /* This is the set of options which may be modified by the .set
192 pseudo-op. We use a struct so that .set push and .set pop are more
195 struct mips_set_options
197 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
198 if it has not been initialized. Changed by `.set mipsN', and the
199 -mipsN command line option, and the default CPU. */
201 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
202 <asename>', by command line options, and based on the default
205 /* Whether we are assembling for the mips16 processor. 0 if we are
206 not, 1 if we are, and -1 if the value has not been initialized.
207 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
208 -nomips16 command line options, and the default CPU. */
210 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
211 1 if we are, and -1 if the value has not been initialized. Changed
212 by `.set micromips' and `.set nomicromips', and the -mmicromips
213 and -mno-micromips command line options, and the default CPU. */
215 /* Non-zero if we should not reorder instructions. Changed by `.set
216 reorder' and `.set noreorder'. */
218 /* Non-zero if we should not permit the register designated "assembler
219 temporary" to be used in instructions. The value is the register
220 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
221 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
223 /* Non-zero if we should warn when a macro instruction expands into
224 more than one machine instruction. Changed by `.set nomacro' and
226 int warn_about_macros;
227 /* Non-zero if we should not move instructions. Changed by `.set
228 move', `.set volatile', `.set nomove', and `.set novolatile'. */
230 /* Non-zero if we should not optimize branches by moving the target
231 of the branch into the delay slot. Actually, we don't perform
232 this optimization anyhow. Changed by `.set bopt' and `.set
235 /* Non-zero if we should not autoextend mips16 instructions.
236 Changed by `.set autoextend' and `.set noautoextend'. */
238 /* True if we should only emit 32-bit microMIPS instructions.
239 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
240 and -mno-insn32 command line options. */
242 /* Restrict general purpose registers and floating point registers
243 to 32 bit. This is initially determined when -mgp32 or -mfp32
244 is passed but can changed if the assembler code uses .set mipsN. */
247 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
248 command line option, and the default CPU. */
250 /* True if ".set sym32" is in effect. */
252 /* True if floating-point operations are not allowed. Changed by .set
253 softfloat or .set hardfloat, by command line options -msoft-float or
254 -mhard-float. The default is false. */
255 bfd_boolean soft_float;
257 /* True if only single-precision floating-point operations are allowed.
258 Changed by .set singlefloat or .set doublefloat, command-line options
259 -msingle-float or -mdouble-float. The default is false. */
260 bfd_boolean single_float;
262 /* 1 if single-precision operations on odd-numbered registers are
267 /* Specifies whether module level options have been checked yet. */
268 static bfd_boolean file_mips_opts_checked = FALSE;
270 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
271 value has not been initialized. Changed by `.nan legacy' and
272 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
273 options, and the default CPU. */
274 static int mips_nan2008 = -1;
276 /* This is the struct we use to hold the module level set of options.
277 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
278 fp fields to -1 to indicate that they have not been initialized. */
280 static struct mips_set_options file_mips_opts =
282 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
283 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
284 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
285 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
286 /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1
289 /* This is similar to file_mips_opts, but for the current set of options. */
291 static struct mips_set_options mips_opts =
293 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
294 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
295 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
296 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
297 /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1
300 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
301 static unsigned int file_ase_explicit;
303 /* These variables are filled in with the masks of registers used.
304 The object format code reads them and puts them in the appropriate
306 unsigned long mips_gprmask;
307 unsigned long mips_cprmask[4];
309 /* True if any MIPS16 code was produced. */
310 static int file_ase_mips16;
312 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
313 || mips_opts.isa == ISA_MIPS32R2 \
314 || mips_opts.isa == ISA_MIPS32R3 \
315 || mips_opts.isa == ISA_MIPS32R5 \
316 || mips_opts.isa == ISA_MIPS64 \
317 || mips_opts.isa == ISA_MIPS64R2 \
318 || mips_opts.isa == ISA_MIPS64R3 \
319 || mips_opts.isa == ISA_MIPS64R5)
321 /* True if any microMIPS code was produced. */
322 static int file_ase_micromips;
324 /* True if we want to create R_MIPS_JALR for jalr $25. */
326 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
328 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
329 because there's no place for any addend, the only acceptable
330 expression is a bare symbol. */
331 #define MIPS_JALR_HINT_P(EXPR) \
332 (!HAVE_IN_PLACE_ADDENDS \
333 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
336 /* The argument of the -march= flag. The architecture we are assembling. */
337 static const char *mips_arch_string;
339 /* The argument of the -mtune= flag. The architecture for which we
341 static int mips_tune = CPU_UNKNOWN;
342 static const char *mips_tune_string;
344 /* True when generating 32-bit code for a 64-bit processor. */
345 static int mips_32bitmode = 0;
347 /* True if the given ABI requires 32-bit registers. */
348 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
350 /* Likewise 64-bit registers. */
351 #define ABI_NEEDS_64BIT_REGS(ABI) \
353 || (ABI) == N64_ABI \
356 #define ISA_IS_R6(ISA) \
357 ((ISA) == ISA_MIPS32R6 \
358 || (ISA) == ISA_MIPS64R6)
360 /* Return true if ISA supports 64 bit wide gp registers. */
361 #define ISA_HAS_64BIT_REGS(ISA) \
362 ((ISA) == ISA_MIPS3 \
363 || (ISA) == ISA_MIPS4 \
364 || (ISA) == ISA_MIPS5 \
365 || (ISA) == ISA_MIPS64 \
366 || (ISA) == ISA_MIPS64R2 \
367 || (ISA) == ISA_MIPS64R3 \
368 || (ISA) == ISA_MIPS64R5 \
369 || (ISA) == ISA_MIPS64R6)
371 /* Return true if ISA supports 64 bit wide float registers. */
372 #define ISA_HAS_64BIT_FPRS(ISA) \
373 ((ISA) == ISA_MIPS3 \
374 || (ISA) == ISA_MIPS4 \
375 || (ISA) == ISA_MIPS5 \
376 || (ISA) == ISA_MIPS32R2 \
377 || (ISA) == ISA_MIPS32R3 \
378 || (ISA) == ISA_MIPS32R5 \
379 || (ISA) == ISA_MIPS32R6 \
380 || (ISA) == ISA_MIPS64 \
381 || (ISA) == ISA_MIPS64R2 \
382 || (ISA) == ISA_MIPS64R3 \
383 || (ISA) == ISA_MIPS64R5 \
384 || (ISA) == ISA_MIPS64R6)
386 /* Return true if ISA supports 64-bit right rotate (dror et al.)
388 #define ISA_HAS_DROR(ISA) \
389 ((ISA) == ISA_MIPS64R2 \
390 || (ISA) == ISA_MIPS64R3 \
391 || (ISA) == ISA_MIPS64R5 \
392 || (ISA) == ISA_MIPS64R6 \
393 || (mips_opts.micromips \
394 && ISA_HAS_64BIT_REGS (ISA)) \
397 /* Return true if ISA supports 32-bit right rotate (ror et al.)
399 #define ISA_HAS_ROR(ISA) \
400 ((ISA) == ISA_MIPS32R2 \
401 || (ISA) == ISA_MIPS32R3 \
402 || (ISA) == ISA_MIPS32R5 \
403 || (ISA) == ISA_MIPS32R6 \
404 || (ISA) == ISA_MIPS64R2 \
405 || (ISA) == ISA_MIPS64R3 \
406 || (ISA) == ISA_MIPS64R5 \
407 || (ISA) == ISA_MIPS64R6 \
408 || (mips_opts.ase & ASE_SMARTMIPS) \
409 || mips_opts.micromips \
412 /* Return true if ISA supports single-precision floats in odd registers. */
413 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
414 (((ISA) == ISA_MIPS32 \
415 || (ISA) == ISA_MIPS32R2 \
416 || (ISA) == ISA_MIPS32R3 \
417 || (ISA) == ISA_MIPS32R5 \
418 || (ISA) == ISA_MIPS32R6 \
419 || (ISA) == ISA_MIPS64 \
420 || (ISA) == ISA_MIPS64R2 \
421 || (ISA) == ISA_MIPS64R3 \
422 || (ISA) == ISA_MIPS64R5 \
423 || (ISA) == ISA_MIPS64R6 \
424 || (CPU) == CPU_R5900) \
425 && (CPU) != CPU_LOONGSON_3A)
427 /* Return true if ISA supports move to/from high part of a 64-bit
428 floating-point register. */
429 #define ISA_HAS_MXHC1(ISA) \
430 ((ISA) == ISA_MIPS32R2 \
431 || (ISA) == ISA_MIPS32R3 \
432 || (ISA) == ISA_MIPS32R5 \
433 || (ISA) == ISA_MIPS32R6 \
434 || (ISA) == ISA_MIPS64R2 \
435 || (ISA) == ISA_MIPS64R3 \
436 || (ISA) == ISA_MIPS64R5 \
437 || (ISA) == ISA_MIPS64R6)
439 /* Return true if ISA supports legacy NAN. */
440 #define ISA_HAS_LEGACY_NAN(ISA) \
441 ((ISA) == ISA_MIPS1 \
442 || (ISA) == ISA_MIPS2 \
443 || (ISA) == ISA_MIPS3 \
444 || (ISA) == ISA_MIPS4 \
445 || (ISA) == ISA_MIPS5 \
446 || (ISA) == ISA_MIPS32 \
447 || (ISA) == ISA_MIPS32R2 \
448 || (ISA) == ISA_MIPS32R3 \
449 || (ISA) == ISA_MIPS32R5 \
450 || (ISA) == ISA_MIPS64 \
451 || (ISA) == ISA_MIPS64R2 \
452 || (ISA) == ISA_MIPS64R3 \
453 || (ISA) == ISA_MIPS64R5)
456 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
461 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
465 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
467 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
469 /* True if relocations are stored in-place. */
470 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
472 /* The ABI-derived address size. */
473 #define HAVE_64BIT_ADDRESSES \
474 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
475 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
477 /* The size of symbolic constants (i.e., expressions of the form
478 "SYMBOL" or "SYMBOL + OFFSET"). */
479 #define HAVE_32BIT_SYMBOLS \
480 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
481 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
483 /* Addresses are loaded in different ways, depending on the address size
484 in use. The n32 ABI Documentation also mandates the use of additions
485 with overflow checking, but existing implementations don't follow it. */
486 #define ADDRESS_ADD_INSN \
487 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
489 #define ADDRESS_ADDI_INSN \
490 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
492 #define ADDRESS_LOAD_INSN \
493 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
495 #define ADDRESS_STORE_INSN \
496 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
498 /* Return true if the given CPU supports the MIPS16 ASE. */
499 #define CPU_HAS_MIPS16(cpu) \
500 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
501 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
503 /* Return true if the given CPU supports the microMIPS ASE. */
504 #define CPU_HAS_MICROMIPS(cpu) 0
506 /* True if CPU has a dror instruction. */
507 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
509 /* True if CPU has a ror instruction. */
510 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
512 /* True if CPU is in the Octeon family */
513 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
514 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
516 /* True if CPU has seq/sne and seqi/snei instructions. */
517 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
519 /* True, if CPU has support for ldc1 and sdc1. */
520 #define CPU_HAS_LDC1_SDC1(CPU) \
521 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
523 /* True if mflo and mfhi can be immediately followed by instructions
524 which write to the HI and LO registers.
526 According to MIPS specifications, MIPS ISAs I, II, and III need
527 (at least) two instructions between the reads of HI/LO and
528 instructions which write them, and later ISAs do not. Contradicting
529 the MIPS specifications, some MIPS IV processor user manuals (e.g.
530 the UM for the NEC Vr5000) document needing the instructions between
531 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
532 MIPS64 and later ISAs to have the interlocks, plus any specific
533 earlier-ISA CPUs for which CPU documentation declares that the
534 instructions are really interlocked. */
535 #define hilo_interlocks \
536 (mips_opts.isa == ISA_MIPS32 \
537 || mips_opts.isa == ISA_MIPS32R2 \
538 || mips_opts.isa == ISA_MIPS32R3 \
539 || mips_opts.isa == ISA_MIPS32R5 \
540 || mips_opts.isa == ISA_MIPS32R6 \
541 || mips_opts.isa == ISA_MIPS64 \
542 || mips_opts.isa == ISA_MIPS64R2 \
543 || mips_opts.isa == ISA_MIPS64R3 \
544 || mips_opts.isa == ISA_MIPS64R5 \
545 || mips_opts.isa == ISA_MIPS64R6 \
546 || mips_opts.arch == CPU_R4010 \
547 || mips_opts.arch == CPU_R5900 \
548 || mips_opts.arch == CPU_R10000 \
549 || mips_opts.arch == CPU_R12000 \
550 || mips_opts.arch == CPU_R14000 \
551 || mips_opts.arch == CPU_R16000 \
552 || mips_opts.arch == CPU_RM7000 \
553 || mips_opts.arch == CPU_VR5500 \
554 || mips_opts.micromips \
557 /* Whether the processor uses hardware interlocks to protect reads
558 from the GPRs after they are loaded from memory, and thus does not
559 require nops to be inserted. This applies to instructions marked
560 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
561 level I and microMIPS mode instructions are always interlocked. */
562 #define gpr_interlocks \
563 (mips_opts.isa != ISA_MIPS1 \
564 || mips_opts.arch == CPU_R3900 \
565 || mips_opts.arch == CPU_R5900 \
566 || mips_opts.micromips \
569 /* Whether the processor uses hardware interlocks to avoid delays
570 required by coprocessor instructions, and thus does not require
571 nops to be inserted. This applies to instructions marked
572 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
573 instructions marked INSN_WRITE_COND_CODE and ones marked
574 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
575 levels I, II, and III and microMIPS mode instructions are always
577 /* Itbl support may require additional care here. */
578 #define cop_interlocks \
579 ((mips_opts.isa != ISA_MIPS1 \
580 && mips_opts.isa != ISA_MIPS2 \
581 && mips_opts.isa != ISA_MIPS3) \
582 || mips_opts.arch == CPU_R4300 \
583 || mips_opts.micromips \
586 /* Whether the processor uses hardware interlocks to protect reads
587 from coprocessor registers after they are loaded from memory, and
588 thus does not require nops to be inserted. This applies to
589 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
590 requires at MIPS ISA level I and microMIPS mode instructions are
591 always interlocked. */
592 #define cop_mem_interlocks \
593 (mips_opts.isa != ISA_MIPS1 \
594 || mips_opts.micromips \
597 /* Is this a mfhi or mflo instruction? */
598 #define MF_HILO_INSN(PINFO) \
599 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
601 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
602 has been selected. This implies, in particular, that addresses of text
603 labels have their LSB set. */
604 #define HAVE_CODE_COMPRESSION \
605 ((mips_opts.mips16 | mips_opts.micromips) != 0)
607 /* The minimum and maximum signed values that can be stored in a GPR. */
608 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
609 #define GPR_SMIN (-GPR_SMAX - 1)
611 /* MIPS PIC level. */
613 enum mips_pic_level mips_pic;
615 /* 1 if we should generate 32 bit offsets from the $gp register in
616 SVR4_PIC mode. Currently has no meaning in other modes. */
617 static int mips_big_got = 0;
619 /* 1 if trap instructions should used for overflow rather than break
621 static int mips_trap = 0;
623 /* 1 if double width floating point constants should not be constructed
624 by assembling two single width halves into two single width floating
625 point registers which just happen to alias the double width destination
626 register. On some architectures this aliasing can be disabled by a bit
627 in the status register, and the setting of this bit cannot be determined
628 automatically at assemble time. */
629 static int mips_disable_float_construction;
631 /* Non-zero if any .set noreorder directives were used. */
633 static int mips_any_noreorder;
635 /* Non-zero if nops should be inserted when the register referenced in
636 an mfhi/mflo instruction is read in the next two instructions. */
637 static int mips_7000_hilo_fix;
639 /* The size of objects in the small data section. */
640 static unsigned int g_switch_value = 8;
641 /* Whether the -G option was used. */
642 static int g_switch_seen = 0;
647 /* If we can determine in advance that GP optimization won't be
648 possible, we can skip the relaxation stuff that tries to produce
649 GP-relative references. This makes delay slot optimization work
652 This function can only provide a guess, but it seems to work for
653 gcc output. It needs to guess right for gcc, otherwise gcc
654 will put what it thinks is a GP-relative instruction in a branch
657 I don't know if a fix is needed for the SVR4_PIC mode. I've only
658 fixed it for the non-PIC mode. KR 95/04/07 */
659 static int nopic_need_relax (symbolS *, int);
661 /* handle of the OPCODE hash table */
662 static struct hash_control *op_hash = NULL;
664 /* The opcode hash table we use for the mips16. */
665 static struct hash_control *mips16_op_hash = NULL;
667 /* The opcode hash table we use for the microMIPS ASE. */
668 static struct hash_control *micromips_op_hash = NULL;
670 /* This array holds the chars that always start a comment. If the
671 pre-processor is disabled, these aren't very useful */
672 const char comment_chars[] = "#";
674 /* This array holds the chars that only start a comment at the beginning of
675 a line. If the line seems to have the form '# 123 filename'
676 .line and .file directives will appear in the pre-processed output */
677 /* Note that input_file.c hand checks for '#' at the beginning of the
678 first line of the input file. This is because the compiler outputs
679 #NO_APP at the beginning of its output. */
680 /* Also note that C style comments are always supported. */
681 const char line_comment_chars[] = "#";
683 /* This array holds machine specific line separator characters. */
684 const char line_separator_chars[] = ";";
686 /* Chars that can be used to separate mant from exp in floating point nums */
687 const char EXP_CHARS[] = "eE";
689 /* Chars that mean this number is a floating point constant */
692 const char FLT_CHARS[] = "rRsSfFdDxXpP";
694 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
695 changed in read.c . Ideally it shouldn't have to know about it at all,
696 but nothing is ideal around here.
699 /* Types of printf format used for instruction-related error messages.
700 "I" means int ("%d") and "S" means string ("%s"). */
701 enum mips_insn_error_format {
707 /* Information about an error that was found while assembling the current
709 struct mips_insn_error {
710 /* We sometimes need to match an instruction against more than one
711 opcode table entry. Errors found during this matching are reported
712 against a particular syntactic argument rather than against the
713 instruction as a whole. We grade these messages so that errors
714 against argument N have a greater priority than an error against
715 any argument < N, since the former implies that arguments up to N
716 were acceptable and that the opcode entry was therefore a closer match.
717 If several matches report an error against the same argument,
718 we only use that error if it is the same in all cases.
720 min_argnum is the minimum argument number for which an error message
721 should be accepted. It is 0 if MSG is against the instruction as
725 /* The printf()-style message, including its format and arguments. */
726 enum mips_insn_error_format format;
734 /* The error that should be reported for the current instruction. */
735 static struct mips_insn_error insn_error;
737 static int auto_align = 1;
739 /* When outputting SVR4 PIC code, the assembler needs to know the
740 offset in the stack frame from which to restore the $gp register.
741 This is set by the .cprestore pseudo-op, and saved in this
743 static offsetT mips_cprestore_offset = -1;
745 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
746 more optimizations, it can use a register value instead of a memory-saved
747 offset and even an other register than $gp as global pointer. */
748 static offsetT mips_cpreturn_offset = -1;
749 static int mips_cpreturn_register = -1;
750 static int mips_gp_register = GP;
751 static int mips_gprel_offset = 0;
753 /* Whether mips_cprestore_offset has been set in the current function
754 (or whether it has already been warned about, if not). */
755 static int mips_cprestore_valid = 0;
757 /* This is the register which holds the stack frame, as set by the
758 .frame pseudo-op. This is needed to implement .cprestore. */
759 static int mips_frame_reg = SP;
761 /* Whether mips_frame_reg has been set in the current function
762 (or whether it has already been warned about, if not). */
763 static int mips_frame_reg_valid = 0;
765 /* To output NOP instructions correctly, we need to keep information
766 about the previous two instructions. */
768 /* Whether we are optimizing. The default value of 2 means to remove
769 unneeded NOPs and swap branch instructions when possible. A value
770 of 1 means to not swap branches. A value of 0 means to always
772 static int mips_optimize = 2;
774 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
775 equivalent to seeing no -g option at all. */
776 static int mips_debug = 0;
778 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
779 #define MAX_VR4130_NOPS 4
781 /* The maximum number of NOPs needed to fill delay slots. */
782 #define MAX_DELAY_NOPS 2
784 /* The maximum number of NOPs needed for any purpose. */
787 /* A list of previous instructions, with index 0 being the most recent.
788 We need to look back MAX_NOPS instructions when filling delay slots
789 or working around processor errata. We need to look back one
790 instruction further if we're thinking about using history[0] to
791 fill a branch delay slot. */
792 static struct mips_cl_insn history[1 + MAX_NOPS];
794 /* Arrays of operands for each instruction. */
795 #define MAX_OPERANDS 6
796 struct mips_operand_array {
797 const struct mips_operand *operand[MAX_OPERANDS];
799 static struct mips_operand_array *mips_operands;
800 static struct mips_operand_array *mips16_operands;
801 static struct mips_operand_array *micromips_operands;
803 /* Nop instructions used by emit_nop. */
804 static struct mips_cl_insn nop_insn;
805 static struct mips_cl_insn mips16_nop_insn;
806 static struct mips_cl_insn micromips_nop16_insn;
807 static struct mips_cl_insn micromips_nop32_insn;
809 /* The appropriate nop for the current mode. */
810 #define NOP_INSN (mips_opts.mips16 \
812 : (mips_opts.micromips \
813 ? (mips_opts.insn32 \
814 ? µmips_nop32_insn \
815 : µmips_nop16_insn) \
818 /* The size of NOP_INSN in bytes. */
819 #define NOP_INSN_SIZE ((mips_opts.mips16 \
820 || (mips_opts.micromips && !mips_opts.insn32)) \
823 /* If this is set, it points to a frag holding nop instructions which
824 were inserted before the start of a noreorder section. If those
825 nops turn out to be unnecessary, the size of the frag can be
827 static fragS *prev_nop_frag;
829 /* The number of nop instructions we created in prev_nop_frag. */
830 static int prev_nop_frag_holds;
832 /* The number of nop instructions that we know we need in
834 static int prev_nop_frag_required;
836 /* The number of instructions we've seen since prev_nop_frag. */
837 static int prev_nop_frag_since;
839 /* Relocations against symbols are sometimes done in two parts, with a HI
840 relocation and a LO relocation. Each relocation has only 16 bits of
841 space to store an addend. This means that in order for the linker to
842 handle carries correctly, it must be able to locate both the HI and
843 the LO relocation. This means that the relocations must appear in
844 order in the relocation table.
846 In order to implement this, we keep track of each unmatched HI
847 relocation. We then sort them so that they immediately precede the
848 corresponding LO relocation. */
853 struct mips_hi_fixup *next;
856 /* The section this fixup is in. */
860 /* The list of unmatched HI relocs. */
862 static struct mips_hi_fixup *mips_hi_fixup_list;
864 /* The frag containing the last explicit relocation operator.
865 Null if explicit relocations have not been used. */
867 static fragS *prev_reloc_op_frag;
869 /* Map mips16 register numbers to normal MIPS register numbers. */
871 static const unsigned int mips16_to_32_reg_map[] =
873 16, 17, 2, 3, 4, 5, 6, 7
876 /* Map microMIPS register numbers to normal MIPS register numbers. */
878 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
880 /* The microMIPS registers with type h. */
881 static const unsigned int micromips_to_32_reg_h_map1[] =
883 5, 5, 6, 4, 4, 4, 4, 4
885 static const unsigned int micromips_to_32_reg_h_map2[] =
887 6, 7, 7, 21, 22, 5, 6, 7
890 /* The microMIPS registers with type m. */
891 static const unsigned int micromips_to_32_reg_m_map[] =
893 0, 17, 2, 3, 16, 18, 19, 20
896 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
898 /* Classifies the kind of instructions we're interested in when
899 implementing -mfix-vr4120. */
900 enum fix_vr4120_class
908 NUM_FIX_VR4120_CLASSES
911 /* ...likewise -mfix-loongson2f-jump. */
912 static bfd_boolean mips_fix_loongson2f_jump;
914 /* ...likewise -mfix-loongson2f-nop. */
915 static bfd_boolean mips_fix_loongson2f_nop;
917 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
918 static bfd_boolean mips_fix_loongson2f;
920 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
921 there must be at least one other instruction between an instruction
922 of type X and an instruction of type Y. */
923 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
925 /* True if -mfix-vr4120 is in force. */
926 static int mips_fix_vr4120;
928 /* ...likewise -mfix-vr4130. */
929 static int mips_fix_vr4130;
931 /* ...likewise -mfix-24k. */
932 static int mips_fix_24k;
934 /* ...likewise -mfix-rm7000 */
935 static int mips_fix_rm7000;
937 /* ...likewise -mfix-cn63xxp1 */
938 static bfd_boolean mips_fix_cn63xxp1;
940 /* We don't relax branches by default, since this causes us to expand
941 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
942 fail to compute the offset before expanding the macro to the most
943 efficient expansion. */
945 static int mips_relax_branch;
947 /* The expansion of many macros depends on the type of symbol that
948 they refer to. For example, when generating position-dependent code,
949 a macro that refers to a symbol may have two different expansions,
950 one which uses GP-relative addresses and one which uses absolute
951 addresses. When generating SVR4-style PIC, a macro may have
952 different expansions for local and global symbols.
954 We handle these situations by generating both sequences and putting
955 them in variant frags. In position-dependent code, the first sequence
956 will be the GP-relative one and the second sequence will be the
957 absolute one. In SVR4 PIC, the first sequence will be for global
958 symbols and the second will be for local symbols.
960 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
961 SECOND are the lengths of the two sequences in bytes. These fields
962 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
963 the subtype has the following flags:
966 Set if it has been decided that we should use the second
967 sequence instead of the first.
970 Set in the first variant frag if the macro's second implementation
971 is longer than its first. This refers to the macro as a whole,
972 not an individual relaxation.
975 Set in the first variant frag if the macro appeared in a .set nomacro
976 block and if one alternative requires a warning but the other does not.
979 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
982 RELAX_DELAY_SLOT_16BIT
983 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
986 RELAX_DELAY_SLOT_SIZE_FIRST
987 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
988 the macro is of the wrong size for the branch delay slot.
990 RELAX_DELAY_SLOT_SIZE_SECOND
991 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
992 the macro is of the wrong size for the branch delay slot.
994 The frag's "opcode" points to the first fixup for relaxable code.
996 Relaxable macros are generated using a sequence such as:
998 relax_start (SYMBOL);
999 ... generate first expansion ...
1001 ... generate second expansion ...
1004 The code and fixups for the unwanted alternative are discarded
1005 by md_convert_frag. */
1006 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
1008 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1009 #define RELAX_SECOND(X) ((X) & 0xff)
1010 #define RELAX_USE_SECOND 0x10000
1011 #define RELAX_SECOND_LONGER 0x20000
1012 #define RELAX_NOMACRO 0x40000
1013 #define RELAX_DELAY_SLOT 0x80000
1014 #define RELAX_DELAY_SLOT_16BIT 0x100000
1015 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1016 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
1018 /* Branch without likely bit. If label is out of range, we turn:
1020 beq reg1, reg2, label
1030 with the following opcode replacements:
1037 bltzal <-> bgezal (with jal label instead of j label)
1039 Even though keeping the delay slot instruction in the delay slot of
1040 the branch would be more efficient, it would be very tricky to do
1041 correctly, because we'd have to introduce a variable frag *after*
1042 the delay slot instruction, and expand that instead. Let's do it
1043 the easy way for now, even if the branch-not-taken case now costs
1044 one additional instruction. Out-of-range branches are not supposed
1045 to be common, anyway.
1047 Branch likely. If label is out of range, we turn:
1049 beql reg1, reg2, label
1050 delay slot (annulled if branch not taken)
1059 delay slot (executed only if branch taken)
1062 It would be possible to generate a shorter sequence by losing the
1063 likely bit, generating something like:
1068 delay slot (executed only if branch taken)
1080 bltzall -> bgezal (with jal label instead of j label)
1081 bgezall -> bltzal (ditto)
1084 but it's not clear that it would actually improve performance. */
1085 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1086 ((relax_substateT) \
1089 | ((toofar) ? 0x20 : 0) \
1090 | ((link) ? 0x40 : 0) \
1091 | ((likely) ? 0x80 : 0) \
1092 | ((uncond) ? 0x100 : 0)))
1093 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1094 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1095 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1096 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1097 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1098 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1100 /* For mips16 code, we use an entirely different form of relaxation.
1101 mips16 supports two versions of most instructions which take
1102 immediate values: a small one which takes some small value, and a
1103 larger one which takes a 16 bit value. Since branches also follow
1104 this pattern, relaxing these values is required.
1106 We can assemble both mips16 and normal MIPS code in a single
1107 object. Therefore, we need to support this type of relaxation at
1108 the same time that we support the relaxation described above. We
1109 use the high bit of the subtype field to distinguish these cases.
1111 The information we store for this type of relaxation is the
1112 argument code found in the opcode file for this relocation, whether
1113 the user explicitly requested a small or extended form, and whether
1114 the relocation is in a jump or jal delay slot. That tells us the
1115 size of the value, and how it should be stored. We also store
1116 whether the fragment is considered to be extended or not. We also
1117 store whether this is known to be a branch to a different section,
1118 whether we have tried to relax this frag yet, and whether we have
1119 ever extended a PC relative fragment because of a shift count. */
1120 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1123 | ((small) ? 0x100 : 0) \
1124 | ((ext) ? 0x200 : 0) \
1125 | ((dslot) ? 0x400 : 0) \
1126 | ((jal_dslot) ? 0x800 : 0))
1127 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1128 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1129 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1130 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1131 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1132 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1133 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1134 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1135 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1136 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1137 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1138 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1140 /* For microMIPS code, we use relaxation similar to one we use for
1141 MIPS16 code. Some instructions that take immediate values support
1142 two encodings: a small one which takes some small value, and a
1143 larger one which takes a 16 bit value. As some branches also follow
1144 this pattern, relaxing these values is required.
1146 We can assemble both microMIPS and normal MIPS code in a single
1147 object. Therefore, we need to support this type of relaxation at
1148 the same time that we support the relaxation described above. We
1149 use one of the high bits of the subtype field to distinguish these
1152 The information we store for this type of relaxation is the argument
1153 code found in the opcode file for this relocation, the register
1154 selected as the assembler temporary, whether in the 32-bit
1155 instruction mode, whether the branch is unconditional, whether it is
1156 compact, whether there is no delay-slot instruction available to fill
1157 in, whether it stores the link address implicitly in $ra, whether
1158 relaxation of out-of-range 32-bit branches to a sequence of
1159 instructions is enabled, and whether the displacement of a branch is
1160 too large to fit as an immediate argument of a 16-bit and a 32-bit
1161 branch, respectively. */
1162 #define RELAX_MICROMIPS_ENCODE(type, at, insn32, \
1163 uncond, compact, link, nods, \
1164 relax32, toofar16, toofar32) \
1167 | (((at) & 0x1f) << 8) \
1168 | ((insn32) ? 0x2000 : 0) \
1169 | ((uncond) ? 0x4000 : 0) \
1170 | ((compact) ? 0x8000 : 0) \
1171 | ((link) ? 0x10000 : 0) \
1172 | ((nods) ? 0x20000 : 0) \
1173 | ((relax32) ? 0x40000 : 0) \
1174 | ((toofar16) ? 0x80000 : 0) \
1175 | ((toofar32) ? 0x100000 : 0))
1176 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1177 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1178 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1179 #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0)
1180 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x4000) != 0)
1181 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x8000) != 0)
1182 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x10000) != 0)
1183 #define RELAX_MICROMIPS_NODS(i) (((i) & 0x20000) != 0)
1184 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x40000) != 0)
1186 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x80000) != 0)
1187 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x80000)
1188 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x80000)
1189 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x100000) != 0)
1190 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x100000)
1191 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x100000)
1193 /* Sign-extend 16-bit value X. */
1194 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1196 /* Is the given value a sign-extended 32-bit value? */
1197 #define IS_SEXT_32BIT_NUM(x) \
1198 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1199 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1201 /* Is the given value a sign-extended 16-bit value? */
1202 #define IS_SEXT_16BIT_NUM(x) \
1203 (((x) &~ (offsetT) 0x7fff) == 0 \
1204 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1206 /* Is the given value a sign-extended 12-bit value? */
1207 #define IS_SEXT_12BIT_NUM(x) \
1208 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1210 /* Is the given value a sign-extended 9-bit value? */
1211 #define IS_SEXT_9BIT_NUM(x) \
1212 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1214 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1215 #define IS_ZEXT_32BIT_NUM(x) \
1216 (((x) &~ (offsetT) 0xffffffff) == 0 \
1217 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1219 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1221 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1222 (((STRUCT) >> (SHIFT)) & (MASK))
1224 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1225 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1227 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1228 : EXTRACT_BITS ((INSN).insn_opcode, \
1229 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1230 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1231 EXTRACT_BITS ((INSN).insn_opcode, \
1232 MIPS16OP_MASK_##FIELD, \
1233 MIPS16OP_SH_##FIELD)
1235 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1236 #define MIPS16_EXTEND (0xf000U << 16)
1238 /* Whether or not we are emitting a branch-likely macro. */
1239 static bfd_boolean emit_branch_likely_macro = FALSE;
1241 /* Global variables used when generating relaxable macros. See the
1242 comment above RELAX_ENCODE for more details about how relaxation
1245 /* 0 if we're not emitting a relaxable macro.
1246 1 if we're emitting the first of the two relaxation alternatives.
1247 2 if we're emitting the second alternative. */
1250 /* The first relaxable fixup in the current frag. (In other words,
1251 the first fixup that refers to relaxable code.) */
1254 /* sizes[0] says how many bytes of the first alternative are stored in
1255 the current frag. Likewise sizes[1] for the second alternative. */
1256 unsigned int sizes[2];
1258 /* The symbol on which the choice of sequence depends. */
1262 /* Global variables used to decide whether a macro needs a warning. */
1264 /* True if the macro is in a branch delay slot. */
1265 bfd_boolean delay_slot_p;
1267 /* Set to the length in bytes required if the macro is in a delay slot
1268 that requires a specific length of instruction, otherwise zero. */
1269 unsigned int delay_slot_length;
1271 /* For relaxable macros, sizes[0] is the length of the first alternative
1272 in bytes and sizes[1] is the length of the second alternative.
1273 For non-relaxable macros, both elements give the length of the
1275 unsigned int sizes[2];
1277 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1278 instruction of the first alternative in bytes and first_insn_sizes[1]
1279 is the length of the first instruction of the second alternative.
1280 For non-relaxable macros, both elements give the length of the first
1281 instruction in bytes.
1283 Set to zero if we haven't yet seen the first instruction. */
1284 unsigned int first_insn_sizes[2];
1286 /* For relaxable macros, insns[0] is the number of instructions for the
1287 first alternative and insns[1] is the number of instructions for the
1290 For non-relaxable macros, both elements give the number of
1291 instructions for the macro. */
1292 unsigned int insns[2];
1294 /* The first variant frag for this macro. */
1296 } mips_macro_warning;
1298 /* Prototypes for static functions. */
1300 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1302 static void append_insn
1303 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1304 bfd_boolean expansionp);
1305 static void mips_no_prev_insn (void);
1306 static void macro_build (expressionS *, const char *, const char *, ...);
1307 static void mips16_macro_build
1308 (expressionS *, const char *, const char *, va_list *);
1309 static void load_register (int, expressionS *, int);
1310 static void macro_start (void);
1311 static void macro_end (void);
1312 static void macro (struct mips_cl_insn *ip, char *str);
1313 static void mips16_macro (struct mips_cl_insn * ip);
1314 static void mips_ip (char *str, struct mips_cl_insn * ip);
1315 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1316 static void mips16_immed
1317 (const char *, unsigned int, int, bfd_reloc_code_real_type, offsetT,
1318 unsigned int, unsigned long *);
1319 static size_t my_getSmallExpression
1320 (expressionS *, bfd_reloc_code_real_type *, char *);
1321 static void my_getExpression (expressionS *, char *);
1322 static void s_align (int);
1323 static void s_change_sec (int);
1324 static void s_change_section (int);
1325 static void s_cons (int);
1326 static void s_float_cons (int);
1327 static void s_mips_globl (int);
1328 static void s_option (int);
1329 static void s_mipsset (int);
1330 static void s_abicalls (int);
1331 static void s_cpload (int);
1332 static void s_cpsetup (int);
1333 static void s_cplocal (int);
1334 static void s_cprestore (int);
1335 static void s_cpreturn (int);
1336 static void s_dtprelword (int);
1337 static void s_dtpreldword (int);
1338 static void s_tprelword (int);
1339 static void s_tpreldword (int);
1340 static void s_gpvalue (int);
1341 static void s_gpword (int);
1342 static void s_gpdword (int);
1343 static void s_ehword (int);
1344 static void s_cpadd (int);
1345 static void s_insn (int);
1346 static void s_nan (int);
1347 static void s_module (int);
1348 static void s_mips_ent (int);
1349 static void s_mips_end (int);
1350 static void s_mips_frame (int);
1351 static void s_mips_mask (int reg_type);
1352 static void s_mips_stab (int);
1353 static void s_mips_weakext (int);
1354 static void s_mips_file (int);
1355 static void s_mips_loc (int);
1356 static bfd_boolean pic_need_relax (symbolS *, asection *);
1357 static int relaxed_branch_length (fragS *, asection *, int);
1358 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1359 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1360 static void file_mips_check_options (void);
1362 /* Table and functions used to map between CPU/ISA names, and
1363 ISA levels, and CPU numbers. */
1365 struct mips_cpu_info
1367 const char *name; /* CPU or ISA name. */
1368 int flags; /* MIPS_CPU_* flags. */
1369 int ase; /* Set of ASEs implemented by the CPU. */
1370 int isa; /* ISA level. */
1371 int cpu; /* CPU number (default CPU if ISA). */
1374 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1376 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1377 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1378 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1380 /* Command-line options. */
1381 const char *md_shortopts = "O::g::G:";
1385 OPTION_MARCH = OPTION_MD_BASE,
1417 OPTION_NO_SMARTMIPS,
1427 OPTION_NO_MICROMIPS,
1430 OPTION_COMPAT_ARCH_BASE,
1439 OPTION_M7000_HILO_FIX,
1440 OPTION_MNO_7000_HILO_FIX,
1444 OPTION_NO_FIX_RM7000,
1445 OPTION_FIX_LOONGSON2F_JUMP,
1446 OPTION_NO_FIX_LOONGSON2F_JUMP,
1447 OPTION_FIX_LOONGSON2F_NOP,
1448 OPTION_NO_FIX_LOONGSON2F_NOP,
1450 OPTION_NO_FIX_VR4120,
1452 OPTION_NO_FIX_VR4130,
1453 OPTION_FIX_CN63XXP1,
1454 OPTION_NO_FIX_CN63XXP1,
1461 OPTION_CONSTRUCT_FLOATS,
1462 OPTION_NO_CONSTRUCT_FLOATS,
1466 OPTION_RELAX_BRANCH,
1467 OPTION_NO_RELAX_BRANCH,
1476 OPTION_SINGLE_FLOAT,
1477 OPTION_DOUBLE_FLOAT,
1490 OPTION_MVXWORKS_PIC,
1493 OPTION_NO_ODD_SPREG,
1497 struct option md_longopts[] =
1499 /* Options which specify architecture. */
1500 {"march", required_argument, NULL, OPTION_MARCH},
1501 {"mtune", required_argument, NULL, OPTION_MTUNE},
1502 {"mips0", no_argument, NULL, OPTION_MIPS1},
1503 {"mips1", no_argument, NULL, OPTION_MIPS1},
1504 {"mips2", no_argument, NULL, OPTION_MIPS2},
1505 {"mips3", no_argument, NULL, OPTION_MIPS3},
1506 {"mips4", no_argument, NULL, OPTION_MIPS4},
1507 {"mips5", no_argument, NULL, OPTION_MIPS5},
1508 {"mips32", no_argument, NULL, OPTION_MIPS32},
1509 {"mips64", no_argument, NULL, OPTION_MIPS64},
1510 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
1511 {"mips32r3", no_argument, NULL, OPTION_MIPS32R3},
1512 {"mips32r5", no_argument, NULL, OPTION_MIPS32R5},
1513 {"mips32r6", no_argument, NULL, OPTION_MIPS32R6},
1514 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
1515 {"mips64r3", no_argument, NULL, OPTION_MIPS64R3},
1516 {"mips64r5", no_argument, NULL, OPTION_MIPS64R5},
1517 {"mips64r6", no_argument, NULL, OPTION_MIPS64R6},
1519 /* Options which specify Application Specific Extensions (ASEs). */
1520 {"mips16", no_argument, NULL, OPTION_MIPS16},
1521 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
1522 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
1523 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
1524 {"mdmx", no_argument, NULL, OPTION_MDMX},
1525 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
1526 {"mdsp", no_argument, NULL, OPTION_DSP},
1527 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
1528 {"mmt", no_argument, NULL, OPTION_MT},
1529 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
1530 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
1531 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
1532 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
1533 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
1534 {"mdspr3", no_argument, NULL, OPTION_DSPR3},
1535 {"mno-dspr3", no_argument, NULL, OPTION_NO_DSPR3},
1536 {"meva", no_argument, NULL, OPTION_EVA},
1537 {"mno-eva", no_argument, NULL, OPTION_NO_EVA},
1538 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
1539 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
1540 {"mmcu", no_argument, NULL, OPTION_MCU},
1541 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
1542 {"mvirt", no_argument, NULL, OPTION_VIRT},
1543 {"mno-virt", no_argument, NULL, OPTION_NO_VIRT},
1544 {"mmsa", no_argument, NULL, OPTION_MSA},
1545 {"mno-msa", no_argument, NULL, OPTION_NO_MSA},
1546 {"mxpa", no_argument, NULL, OPTION_XPA},
1547 {"mno-xpa", no_argument, NULL, OPTION_NO_XPA},
1549 /* Old-style architecture options. Don't add more of these. */
1550 {"m4650", no_argument, NULL, OPTION_M4650},
1551 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
1552 {"m4010", no_argument, NULL, OPTION_M4010},
1553 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
1554 {"m4100", no_argument, NULL, OPTION_M4100},
1555 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
1556 {"m3900", no_argument, NULL, OPTION_M3900},
1557 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
1559 /* Options which enable bug fixes. */
1560 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
1561 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1562 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1563 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
1564 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
1565 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
1566 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
1567 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
1568 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
1569 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
1570 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
1571 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
1572 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
1573 {"mfix-rm7000", no_argument, NULL, OPTION_FIX_RM7000},
1574 {"mno-fix-rm7000", no_argument, NULL, OPTION_NO_FIX_RM7000},
1575 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
1576 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
1578 /* Miscellaneous options. */
1579 {"trap", no_argument, NULL, OPTION_TRAP},
1580 {"no-break", no_argument, NULL, OPTION_TRAP},
1581 {"break", no_argument, NULL, OPTION_BREAK},
1582 {"no-trap", no_argument, NULL, OPTION_BREAK},
1583 {"EB", no_argument, NULL, OPTION_EB},
1584 {"EL", no_argument, NULL, OPTION_EL},
1585 {"mfp32", no_argument, NULL, OPTION_FP32},
1586 {"mgp32", no_argument, NULL, OPTION_GP32},
1587 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
1588 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
1589 {"mfp64", no_argument, NULL, OPTION_FP64},
1590 {"mfpxx", no_argument, NULL, OPTION_FPXX},
1591 {"mgp64", no_argument, NULL, OPTION_GP64},
1592 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
1593 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
1594 {"minsn32", no_argument, NULL, OPTION_INSN32},
1595 {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32},
1596 {"mshared", no_argument, NULL, OPTION_MSHARED},
1597 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
1598 {"msym32", no_argument, NULL, OPTION_MSYM32},
1599 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
1600 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
1601 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
1602 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
1603 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
1604 {"modd-spreg", no_argument, NULL, OPTION_ODD_SPREG},
1605 {"mno-odd-spreg", no_argument, NULL, OPTION_NO_ODD_SPREG},
1607 /* Strictly speaking this next option is ELF specific,
1608 but we allow it for other ports as well in order to
1609 make testing easier. */
1610 {"32", no_argument, NULL, OPTION_32},
1612 /* ELF-specific options. */
1613 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
1614 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
1615 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
1616 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
1617 {"xgot", no_argument, NULL, OPTION_XGOT},
1618 {"mabi", required_argument, NULL, OPTION_MABI},
1619 {"n32", no_argument, NULL, OPTION_N32},
1620 {"64", no_argument, NULL, OPTION_64},
1621 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
1622 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
1623 {"mpdr", no_argument, NULL, OPTION_PDR},
1624 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
1625 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
1626 {"mnan", required_argument, NULL, OPTION_NAN},
1628 {NULL, no_argument, NULL, 0}
1630 size_t md_longopts_size = sizeof (md_longopts);
1632 /* Information about either an Application Specific Extension or an
1633 optional architecture feature that, for simplicity, we treat in the
1634 same way as an ASE. */
1637 /* The name of the ASE, used in both the command-line and .set options. */
1640 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1641 and 64-bit architectures, the flags here refer to the subset that
1642 is available on both. */
1645 /* The ASE_* flag used for instructions that are available on 64-bit
1646 architectures but that are not included in FLAGS. */
1647 unsigned int flags64;
1649 /* The command-line options that turn the ASE on and off. */
1653 /* The minimum required architecture revisions for MIPS32, MIPS64,
1654 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1657 int micromips32_rev;
1658 int micromips64_rev;
1660 /* The architecture where the ASE was removed or -1 if the extension has not
1665 /* A table of all supported ASEs. */
1666 static const struct mips_ase mips_ases[] = {
1667 { "dsp", ASE_DSP, ASE_DSP64,
1668 OPTION_DSP, OPTION_NO_DSP,
1672 { "dspr2", ASE_DSP | ASE_DSPR2, 0,
1673 OPTION_DSPR2, OPTION_NO_DSPR2,
1677 { "dspr3", ASE_DSP | ASE_DSPR2 | ASE_DSPR3, 0,
1678 OPTION_DSPR3, OPTION_NO_DSPR3,
1682 { "eva", ASE_EVA, 0,
1683 OPTION_EVA, OPTION_NO_EVA,
1687 { "mcu", ASE_MCU, 0,
1688 OPTION_MCU, OPTION_NO_MCU,
1692 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1693 { "mdmx", ASE_MDMX, 0,
1694 OPTION_MDMX, OPTION_NO_MDMX,
1698 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1699 { "mips3d", ASE_MIPS3D, 0,
1700 OPTION_MIPS3D, OPTION_NO_MIPS3D,
1705 OPTION_MT, OPTION_NO_MT,
1709 { "smartmips", ASE_SMARTMIPS, 0,
1710 OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS,
1714 { "virt", ASE_VIRT, ASE_VIRT64,
1715 OPTION_VIRT, OPTION_NO_VIRT,
1719 { "msa", ASE_MSA, ASE_MSA64,
1720 OPTION_MSA, OPTION_NO_MSA,
1724 { "xpa", ASE_XPA, 0,
1725 OPTION_XPA, OPTION_NO_XPA,
1730 /* The set of ASEs that require -mfp64. */
1731 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
1733 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1734 static const unsigned int mips_ase_groups[] = {
1735 ASE_DSP | ASE_DSPR2 | ASE_DSPR3
1740 The following pseudo-ops from the Kane and Heinrich MIPS book
1741 should be defined here, but are currently unsupported: .alias,
1742 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1744 The following pseudo-ops from the Kane and Heinrich MIPS book are
1745 specific to the type of debugging information being generated, and
1746 should be defined by the object format: .aent, .begin, .bend,
1747 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1750 The following pseudo-ops from the Kane and Heinrich MIPS book are
1751 not MIPS CPU specific, but are also not specific to the object file
1752 format. This file is probably the best place to define them, but
1753 they are not currently supported: .asm0, .endr, .lab, .struct. */
1755 static const pseudo_typeS mips_pseudo_table[] =
1757 /* MIPS specific pseudo-ops. */
1758 {"option", s_option, 0},
1759 {"set", s_mipsset, 0},
1760 {"rdata", s_change_sec, 'r'},
1761 {"sdata", s_change_sec, 's'},
1762 {"livereg", s_ignore, 0},
1763 {"abicalls", s_abicalls, 0},
1764 {"cpload", s_cpload, 0},
1765 {"cpsetup", s_cpsetup, 0},
1766 {"cplocal", s_cplocal, 0},
1767 {"cprestore", s_cprestore, 0},
1768 {"cpreturn", s_cpreturn, 0},
1769 {"dtprelword", s_dtprelword, 0},
1770 {"dtpreldword", s_dtpreldword, 0},
1771 {"tprelword", s_tprelword, 0},
1772 {"tpreldword", s_tpreldword, 0},
1773 {"gpvalue", s_gpvalue, 0},
1774 {"gpword", s_gpword, 0},
1775 {"gpdword", s_gpdword, 0},
1776 {"ehword", s_ehword, 0},
1777 {"cpadd", s_cpadd, 0},
1778 {"insn", s_insn, 0},
1780 {"module", s_module, 0},
1782 /* Relatively generic pseudo-ops that happen to be used on MIPS
1784 {"asciiz", stringer, 8 + 1},
1785 {"bss", s_change_sec, 'b'},
1787 {"half", s_cons, 1},
1788 {"dword", s_cons, 3},
1789 {"weakext", s_mips_weakext, 0},
1790 {"origin", s_org, 0},
1791 {"repeat", s_rept, 0},
1793 /* For MIPS this is non-standard, but we define it for consistency. */
1794 {"sbss", s_change_sec, 'B'},
1796 /* These pseudo-ops are defined in read.c, but must be overridden
1797 here for one reason or another. */
1798 {"align", s_align, 0},
1799 {"byte", s_cons, 0},
1800 {"data", s_change_sec, 'd'},
1801 {"double", s_float_cons, 'd'},
1802 {"float", s_float_cons, 'f'},
1803 {"globl", s_mips_globl, 0},
1804 {"global", s_mips_globl, 0},
1805 {"hword", s_cons, 1},
1807 {"long", s_cons, 2},
1808 {"octa", s_cons, 4},
1809 {"quad", s_cons, 3},
1810 {"section", s_change_section, 0},
1811 {"short", s_cons, 1},
1812 {"single", s_float_cons, 'f'},
1813 {"stabd", s_mips_stab, 'd'},
1814 {"stabn", s_mips_stab, 'n'},
1815 {"stabs", s_mips_stab, 's'},
1816 {"text", s_change_sec, 't'},
1817 {"word", s_cons, 2},
1819 { "extern", ecoff_directive_extern, 0},
1824 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1826 /* These pseudo-ops should be defined by the object file format.
1827 However, a.out doesn't support them, so we have versions here. */
1828 {"aent", s_mips_ent, 1},
1829 {"bgnb", s_ignore, 0},
1830 {"end", s_mips_end, 0},
1831 {"endb", s_ignore, 0},
1832 {"ent", s_mips_ent, 0},
1833 {"file", s_mips_file, 0},
1834 {"fmask", s_mips_mask, 'F'},
1835 {"frame", s_mips_frame, 0},
1836 {"loc", s_mips_loc, 0},
1837 {"mask", s_mips_mask, 'R'},
1838 {"verstamp", s_ignore, 0},
1842 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1843 purpose of the `.dc.a' internal pseudo-op. */
1846 mips_address_bytes (void)
1848 file_mips_check_options ();
1849 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1852 extern void pop_insert (const pseudo_typeS *);
1855 mips_pop_insert (void)
1857 pop_insert (mips_pseudo_table);
1858 if (! ECOFF_DEBUGGING)
1859 pop_insert (mips_nonecoff_pseudo_table);
1862 /* Symbols labelling the current insn. */
1864 struct insn_label_list
1866 struct insn_label_list *next;
1870 static struct insn_label_list *free_insn_labels;
1871 #define label_list tc_segment_info_data.labels
1873 static void mips_clear_insn_labels (void);
1874 static void mips_mark_labels (void);
1875 static void mips_compressed_mark_labels (void);
1878 mips_clear_insn_labels (void)
1880 struct insn_label_list **pl;
1881 segment_info_type *si;
1885 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1888 si = seg_info (now_seg);
1889 *pl = si->label_list;
1890 si->label_list = NULL;
1894 /* Mark instruction labels in MIPS16/microMIPS mode. */
1897 mips_mark_labels (void)
1899 if (HAVE_CODE_COMPRESSION)
1900 mips_compressed_mark_labels ();
1903 static char *expr_end;
1905 /* An expression in a macro instruction. This is set by mips_ip and
1906 mips16_ip and when populated is always an O_constant. */
1908 static expressionS imm_expr;
1910 /* The relocatable field in an instruction and the relocs associated
1911 with it. These variables are used for instructions like LUI and
1912 JAL as well as true offsets. They are also used for address
1913 operands in macros. */
1915 static expressionS offset_expr;
1916 static bfd_reloc_code_real_type offset_reloc[3]
1917 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1919 /* This is set to the resulting size of the instruction to be produced
1920 by mips16_ip if an explicit extension is used or by mips_ip if an
1921 explicit size is supplied. */
1923 static unsigned int forced_insn_length;
1925 /* True if we are assembling an instruction. All dot symbols defined during
1926 this time should be treated as code labels. */
1928 static bfd_boolean mips_assembling_insn;
1930 /* The pdr segment for per procedure frame/regmask info. Not used for
1933 static segT pdr_seg;
1935 /* The default target format to use. */
1937 #if defined (TE_FreeBSD)
1938 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1939 #elif defined (TE_TMIPS)
1940 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1942 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1946 mips_target_format (void)
1948 switch (OUTPUT_FLAVOR)
1950 case bfd_target_elf_flavour:
1952 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1953 return (target_big_endian
1954 ? "elf32-bigmips-vxworks"
1955 : "elf32-littlemips-vxworks");
1957 return (target_big_endian
1958 ? (HAVE_64BIT_OBJECTS
1959 ? ELF_TARGET ("elf64-", "big")
1961 ? ELF_TARGET ("elf32-n", "big")
1962 : ELF_TARGET ("elf32-", "big")))
1963 : (HAVE_64BIT_OBJECTS
1964 ? ELF_TARGET ("elf64-", "little")
1966 ? ELF_TARGET ("elf32-n", "little")
1967 : ELF_TARGET ("elf32-", "little"))));
1974 /* Return the ISA revision that is currently in use, or 0 if we are
1975 generating code for MIPS V or below. */
1980 if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2)
1983 if (mips_opts.isa == ISA_MIPS32R3 || mips_opts.isa == ISA_MIPS64R3)
1986 if (mips_opts.isa == ISA_MIPS32R5 || mips_opts.isa == ISA_MIPS64R5)
1989 if (mips_opts.isa == ISA_MIPS32R6 || mips_opts.isa == ISA_MIPS64R6)
1992 /* microMIPS implies revision 2 or above. */
1993 if (mips_opts.micromips)
1996 if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64)
2002 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
2005 mips_ase_mask (unsigned int flags)
2009 for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++)
2010 if (flags & mips_ase_groups[i])
2011 flags |= mips_ase_groups[i];
2015 /* Check whether the current ISA supports ASE. Issue a warning if
2019 mips_check_isa_supports_ase (const struct mips_ase *ase)
2023 static unsigned int warned_isa;
2024 static unsigned int warned_fp32;
2026 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
2027 min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev;
2029 min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev;
2030 if ((min_rev < 0 || mips_isa_rev () < min_rev)
2031 && (warned_isa & ase->flags) != ase->flags)
2033 warned_isa |= ase->flags;
2034 base = mips_opts.micromips ? "microMIPS" : "MIPS";
2035 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
2037 as_warn (_("the %d-bit %s architecture does not support the"
2038 " `%s' extension"), size, base, ase->name);
2040 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
2041 ase->name, base, size, min_rev);
2043 else if ((ase->rem_rev > 0 && mips_isa_rev () >= ase->rem_rev)
2044 && (warned_isa & ase->flags) != ase->flags)
2046 warned_isa |= ase->flags;
2047 base = mips_opts.micromips ? "microMIPS" : "MIPS";
2048 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
2049 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2050 ase->name, base, size, ase->rem_rev);
2053 if ((ase->flags & FP64_ASES)
2054 && mips_opts.fp != 64
2055 && (warned_fp32 & ase->flags) != ase->flags)
2057 warned_fp32 |= ase->flags;
2058 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase->name);
2062 /* Check all enabled ASEs to see whether they are supported by the
2063 chosen architecture. */
2066 mips_check_isa_supports_ases (void)
2068 unsigned int i, mask;
2070 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2072 mask = mips_ase_mask (mips_ases[i].flags);
2073 if ((mips_opts.ase & mask) == mips_ases[i].flags)
2074 mips_check_isa_supports_ase (&mips_ases[i]);
2078 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2079 that were affected. */
2082 mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts,
2083 bfd_boolean enabled_p)
2087 mask = mips_ase_mask (ase->flags);
2090 opts->ase |= ase->flags;
2094 /* Return the ASE called NAME, or null if none. */
2096 static const struct mips_ase *
2097 mips_lookup_ase (const char *name)
2101 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2102 if (strcmp (name, mips_ases[i].name) == 0)
2103 return &mips_ases[i];
2107 /* Return the length of a microMIPS instruction in bytes. If bits of
2108 the mask beyond the low 16 are 0, then it is a 16-bit instruction,
2109 otherwise it is a 32-bit instruction. */
2111 static inline unsigned int
2112 micromips_insn_length (const struct mips_opcode *mo)
2114 return (mo->mask >> 16) == 0 ? 2 : 4;
2117 /* Return the length of MIPS16 instruction OPCODE. */
2119 static inline unsigned int
2120 mips16_opcode_length (unsigned long opcode)
2122 return (opcode >> 16) == 0 ? 2 : 4;
2125 /* Return the length of instruction INSN. */
2127 static inline unsigned int
2128 insn_length (const struct mips_cl_insn *insn)
2130 if (mips_opts.micromips)
2131 return micromips_insn_length (insn->insn_mo);
2132 else if (mips_opts.mips16)
2133 return mips16_opcode_length (insn->insn_opcode);
2138 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2141 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
2146 insn->insn_opcode = mo->match;
2149 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2150 insn->fixp[i] = NULL;
2151 insn->fixed_p = (mips_opts.noreorder > 0);
2152 insn->noreorder_p = (mips_opts.noreorder > 0);
2153 insn->mips16_absolute_jump_p = 0;
2154 insn->complete_p = 0;
2155 insn->cleared_p = 0;
2158 /* Get a list of all the operands in INSN. */
2160 static const struct mips_operand_array *
2161 insn_operands (const struct mips_cl_insn *insn)
2163 if (insn->insn_mo >= &mips_opcodes[0]
2164 && insn->insn_mo < &mips_opcodes[NUMOPCODES])
2165 return &mips_operands[insn->insn_mo - &mips_opcodes[0]];
2167 if (insn->insn_mo >= &mips16_opcodes[0]
2168 && insn->insn_mo < &mips16_opcodes[bfd_mips16_num_opcodes])
2169 return &mips16_operands[insn->insn_mo - &mips16_opcodes[0]];
2171 if (insn->insn_mo >= µmips_opcodes[0]
2172 && insn->insn_mo < µmips_opcodes[bfd_micromips_num_opcodes])
2173 return µmips_operands[insn->insn_mo - µmips_opcodes[0]];
2178 /* Get a description of operand OPNO of INSN. */
2180 static const struct mips_operand *
2181 insn_opno (const struct mips_cl_insn *insn, unsigned opno)
2183 const struct mips_operand_array *operands;
2185 operands = insn_operands (insn);
2186 if (opno >= MAX_OPERANDS || !operands->operand[opno])
2188 return operands->operand[opno];
2191 /* Install UVAL as the value of OPERAND in INSN. */
2194 insn_insert_operand (struct mips_cl_insn *insn,
2195 const struct mips_operand *operand, unsigned int uval)
2197 insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval);
2200 /* Extract the value of OPERAND from INSN. */
2202 static inline unsigned
2203 insn_extract_operand (const struct mips_cl_insn *insn,
2204 const struct mips_operand *operand)
2206 return mips_extract_operand (operand, insn->insn_opcode);
2209 /* Record the current MIPS16/microMIPS mode in now_seg. */
2212 mips_record_compressed_mode (void)
2214 segment_info_type *si;
2216 si = seg_info (now_seg);
2217 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
2218 si->tc_segment_info_data.mips16 = mips_opts.mips16;
2219 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
2220 si->tc_segment_info_data.micromips = mips_opts.micromips;
2223 /* Read a standard MIPS instruction from BUF. */
2225 static unsigned long
2226 read_insn (char *buf)
2228 if (target_big_endian)
2229 return bfd_getb32 ((bfd_byte *) buf);
2231 return bfd_getl32 ((bfd_byte *) buf);
2234 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2238 write_insn (char *buf, unsigned int insn)
2240 md_number_to_chars (buf, insn, 4);
2244 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2245 has length LENGTH. */
2247 static unsigned long
2248 read_compressed_insn (char *buf, unsigned int length)
2254 for (i = 0; i < length; i += 2)
2257 if (target_big_endian)
2258 insn |= bfd_getb16 ((char *) buf);
2260 insn |= bfd_getl16 ((char *) buf);
2266 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2267 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2270 write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
2274 for (i = 0; i < length; i += 2)
2275 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
2276 return buf + length;
2279 /* Install INSN at the location specified by its "frag" and "where" fields. */
2282 install_insn (const struct mips_cl_insn *insn)
2284 char *f = insn->frag->fr_literal + insn->where;
2285 if (HAVE_CODE_COMPRESSION)
2286 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
2288 write_insn (f, insn->insn_opcode);
2289 mips_record_compressed_mode ();
2292 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2293 and install the opcode in the new location. */
2296 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
2301 insn->where = where;
2302 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2303 if (insn->fixp[i] != NULL)
2305 insn->fixp[i]->fx_frag = frag;
2306 insn->fixp[i]->fx_where = where;
2308 install_insn (insn);
2311 /* Add INSN to the end of the output. */
2314 add_fixed_insn (struct mips_cl_insn *insn)
2316 char *f = frag_more (insn_length (insn));
2317 move_insn (insn, frag_now, f - frag_now->fr_literal);
2320 /* Start a variant frag and move INSN to the start of the variant part,
2321 marking it as fixed. The other arguments are as for frag_var. */
2324 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
2325 relax_substateT subtype, symbolS *symbol, offsetT offset)
2327 frag_grow (max_chars);
2328 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
2330 frag_var (rs_machine_dependent, max_chars, var,
2331 subtype, symbol, offset, NULL);
2334 /* Insert N copies of INSN into the history buffer, starting at
2335 position FIRST. Neither FIRST nor N need to be clipped. */
2338 insert_into_history (unsigned int first, unsigned int n,
2339 const struct mips_cl_insn *insn)
2341 if (mips_relax.sequence != 2)
2345 for (i = ARRAY_SIZE (history); i-- > first;)
2347 history[i] = history[i - n];
2353 /* Clear the error in insn_error. */
2356 clear_insn_error (void)
2358 memset (&insn_error, 0, sizeof (insn_error));
2361 /* Possibly record error message MSG for the current instruction.
2362 If the error is about a particular argument, ARGNUM is the 1-based
2363 number of that argument, otherwise it is 0. FORMAT is the format
2364 of MSG. Return true if MSG was used, false if the current message
2368 set_insn_error_format (int argnum, enum mips_insn_error_format format,
2373 /* Give priority to errors against specific arguments, and to
2374 the first whole-instruction message. */
2380 /* Keep insn_error if it is against a later argument. */
2381 if (argnum < insn_error.min_argnum)
2384 /* If both errors are against the same argument but are different,
2385 give up on reporting a specific error for this argument.
2386 See the comment about mips_insn_error for details. */
2387 if (argnum == insn_error.min_argnum
2389 && strcmp (insn_error.msg, msg) != 0)
2392 insn_error.min_argnum += 1;
2396 insn_error.min_argnum = argnum;
2397 insn_error.format = format;
2398 insn_error.msg = msg;
2402 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2403 as for set_insn_error_format. */
2406 set_insn_error (int argnum, const char *msg)
2408 set_insn_error_format (argnum, ERR_FMT_PLAIN, msg);
2411 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2412 as for set_insn_error_format. */
2415 set_insn_error_i (int argnum, const char *msg, int i)
2417 if (set_insn_error_format (argnum, ERR_FMT_I, msg))
2421 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2422 are as for set_insn_error_format. */
2425 set_insn_error_ss (int argnum, const char *msg, const char *s1, const char *s2)
2427 if (set_insn_error_format (argnum, ERR_FMT_SS, msg))
2429 insn_error.u.ss[0] = s1;
2430 insn_error.u.ss[1] = s2;
2434 /* Report the error in insn_error, which is against assembly code STR. */
2437 report_insn_error (const char *str)
2439 const char *msg = concat (insn_error.msg, " `%s'", NULL);
2441 switch (insn_error.format)
2448 as_bad (msg, insn_error.u.i, str);
2452 as_bad (msg, insn_error.u.ss[0], insn_error.u.ss[1], str);
2456 free ((char *) msg);
2459 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2460 the idea is to make it obvious at a glance that each errata is
2464 init_vr4120_conflicts (void)
2466 #define CONFLICT(FIRST, SECOND) \
2467 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2469 /* Errata 21 - [D]DIV[U] after [D]MACC */
2470 CONFLICT (MACC, DIV);
2471 CONFLICT (DMACC, DIV);
2473 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2474 CONFLICT (DMULT, DMULT);
2475 CONFLICT (DMULT, DMACC);
2476 CONFLICT (DMACC, DMULT);
2477 CONFLICT (DMACC, DMACC);
2479 /* Errata 24 - MT{LO,HI} after [D]MACC */
2480 CONFLICT (MACC, MTHILO);
2481 CONFLICT (DMACC, MTHILO);
2483 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2484 instruction is executed immediately after a MACC or DMACC
2485 instruction, the result of [either instruction] is incorrect." */
2486 CONFLICT (MACC, MULT);
2487 CONFLICT (MACC, DMULT);
2488 CONFLICT (DMACC, MULT);
2489 CONFLICT (DMACC, DMULT);
2491 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2492 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2493 DDIV or DDIVU instruction, the result of the MACC or
2494 DMACC instruction is incorrect.". */
2495 CONFLICT (DMULT, MACC);
2496 CONFLICT (DMULT, DMACC);
2497 CONFLICT (DIV, MACC);
2498 CONFLICT (DIV, DMACC);
2508 #define RNUM_MASK 0x00000ff
2509 #define RTYPE_MASK 0x0ffff00
2510 #define RTYPE_NUM 0x0000100
2511 #define RTYPE_FPU 0x0000200
2512 #define RTYPE_FCC 0x0000400
2513 #define RTYPE_VEC 0x0000800
2514 #define RTYPE_GP 0x0001000
2515 #define RTYPE_CP0 0x0002000
2516 #define RTYPE_PC 0x0004000
2517 #define RTYPE_ACC 0x0008000
2518 #define RTYPE_CCC 0x0010000
2519 #define RTYPE_VI 0x0020000
2520 #define RTYPE_VF 0x0040000
2521 #define RTYPE_R5900_I 0x0080000
2522 #define RTYPE_R5900_Q 0x0100000
2523 #define RTYPE_R5900_R 0x0200000
2524 #define RTYPE_R5900_ACC 0x0400000
2525 #define RTYPE_MSA 0x0800000
2526 #define RWARN 0x8000000
2528 #define GENERIC_REGISTER_NUMBERS \
2529 {"$0", RTYPE_NUM | 0}, \
2530 {"$1", RTYPE_NUM | 1}, \
2531 {"$2", RTYPE_NUM | 2}, \
2532 {"$3", RTYPE_NUM | 3}, \
2533 {"$4", RTYPE_NUM | 4}, \
2534 {"$5", RTYPE_NUM | 5}, \
2535 {"$6", RTYPE_NUM | 6}, \
2536 {"$7", RTYPE_NUM | 7}, \
2537 {"$8", RTYPE_NUM | 8}, \
2538 {"$9", RTYPE_NUM | 9}, \
2539 {"$10", RTYPE_NUM | 10}, \
2540 {"$11", RTYPE_NUM | 11}, \
2541 {"$12", RTYPE_NUM | 12}, \
2542 {"$13", RTYPE_NUM | 13}, \
2543 {"$14", RTYPE_NUM | 14}, \
2544 {"$15", RTYPE_NUM | 15}, \
2545 {"$16", RTYPE_NUM | 16}, \
2546 {"$17", RTYPE_NUM | 17}, \
2547 {"$18", RTYPE_NUM | 18}, \
2548 {"$19", RTYPE_NUM | 19}, \
2549 {"$20", RTYPE_NUM | 20}, \
2550 {"$21", RTYPE_NUM | 21}, \
2551 {"$22", RTYPE_NUM | 22}, \
2552 {"$23", RTYPE_NUM | 23}, \
2553 {"$24", RTYPE_NUM | 24}, \
2554 {"$25", RTYPE_NUM | 25}, \
2555 {"$26", RTYPE_NUM | 26}, \
2556 {"$27", RTYPE_NUM | 27}, \
2557 {"$28", RTYPE_NUM | 28}, \
2558 {"$29", RTYPE_NUM | 29}, \
2559 {"$30", RTYPE_NUM | 30}, \
2560 {"$31", RTYPE_NUM | 31}
2562 #define FPU_REGISTER_NAMES \
2563 {"$f0", RTYPE_FPU | 0}, \
2564 {"$f1", RTYPE_FPU | 1}, \
2565 {"$f2", RTYPE_FPU | 2}, \
2566 {"$f3", RTYPE_FPU | 3}, \
2567 {"$f4", RTYPE_FPU | 4}, \
2568 {"$f5", RTYPE_FPU | 5}, \
2569 {"$f6", RTYPE_FPU | 6}, \
2570 {"$f7", RTYPE_FPU | 7}, \
2571 {"$f8", RTYPE_FPU | 8}, \
2572 {"$f9", RTYPE_FPU | 9}, \
2573 {"$f10", RTYPE_FPU | 10}, \
2574 {"$f11", RTYPE_FPU | 11}, \
2575 {"$f12", RTYPE_FPU | 12}, \
2576 {"$f13", RTYPE_FPU | 13}, \
2577 {"$f14", RTYPE_FPU | 14}, \
2578 {"$f15", RTYPE_FPU | 15}, \
2579 {"$f16", RTYPE_FPU | 16}, \
2580 {"$f17", RTYPE_FPU | 17}, \
2581 {"$f18", RTYPE_FPU | 18}, \
2582 {"$f19", RTYPE_FPU | 19}, \
2583 {"$f20", RTYPE_FPU | 20}, \
2584 {"$f21", RTYPE_FPU | 21}, \
2585 {"$f22", RTYPE_FPU | 22}, \
2586 {"$f23", RTYPE_FPU | 23}, \
2587 {"$f24", RTYPE_FPU | 24}, \
2588 {"$f25", RTYPE_FPU | 25}, \
2589 {"$f26", RTYPE_FPU | 26}, \
2590 {"$f27", RTYPE_FPU | 27}, \
2591 {"$f28", RTYPE_FPU | 28}, \
2592 {"$f29", RTYPE_FPU | 29}, \
2593 {"$f30", RTYPE_FPU | 30}, \
2594 {"$f31", RTYPE_FPU | 31}
2596 #define FPU_CONDITION_CODE_NAMES \
2597 {"$fcc0", RTYPE_FCC | 0}, \
2598 {"$fcc1", RTYPE_FCC | 1}, \
2599 {"$fcc2", RTYPE_FCC | 2}, \
2600 {"$fcc3", RTYPE_FCC | 3}, \
2601 {"$fcc4", RTYPE_FCC | 4}, \
2602 {"$fcc5", RTYPE_FCC | 5}, \
2603 {"$fcc6", RTYPE_FCC | 6}, \
2604 {"$fcc7", RTYPE_FCC | 7}
2606 #define COPROC_CONDITION_CODE_NAMES \
2607 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2608 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2609 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2610 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2611 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2612 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2613 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2614 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2616 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2617 {"$a4", RTYPE_GP | 8}, \
2618 {"$a5", RTYPE_GP | 9}, \
2619 {"$a6", RTYPE_GP | 10}, \
2620 {"$a7", RTYPE_GP | 11}, \
2621 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2622 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2623 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2624 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2625 {"$t0", RTYPE_GP | 12}, \
2626 {"$t1", RTYPE_GP | 13}, \
2627 {"$t2", RTYPE_GP | 14}, \
2628 {"$t3", RTYPE_GP | 15}
2630 #define O32_SYMBOLIC_REGISTER_NAMES \
2631 {"$t0", RTYPE_GP | 8}, \
2632 {"$t1", RTYPE_GP | 9}, \
2633 {"$t2", RTYPE_GP | 10}, \
2634 {"$t3", RTYPE_GP | 11}, \
2635 {"$t4", RTYPE_GP | 12}, \
2636 {"$t5", RTYPE_GP | 13}, \
2637 {"$t6", RTYPE_GP | 14}, \
2638 {"$t7", RTYPE_GP | 15}, \
2639 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2640 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2641 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2642 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2644 /* Remaining symbolic register names */
2645 #define SYMBOLIC_REGISTER_NAMES \
2646 {"$zero", RTYPE_GP | 0}, \
2647 {"$at", RTYPE_GP | 1}, \
2648 {"$AT", RTYPE_GP | 1}, \
2649 {"$v0", RTYPE_GP | 2}, \
2650 {"$v1", RTYPE_GP | 3}, \
2651 {"$a0", RTYPE_GP | 4}, \
2652 {"$a1", RTYPE_GP | 5}, \
2653 {"$a2", RTYPE_GP | 6}, \
2654 {"$a3", RTYPE_GP | 7}, \
2655 {"$s0", RTYPE_GP | 16}, \
2656 {"$s1", RTYPE_GP | 17}, \
2657 {"$s2", RTYPE_GP | 18}, \
2658 {"$s3", RTYPE_GP | 19}, \
2659 {"$s4", RTYPE_GP | 20}, \
2660 {"$s5", RTYPE_GP | 21}, \
2661 {"$s6", RTYPE_GP | 22}, \
2662 {"$s7", RTYPE_GP | 23}, \
2663 {"$t8", RTYPE_GP | 24}, \
2664 {"$t9", RTYPE_GP | 25}, \
2665 {"$k0", RTYPE_GP | 26}, \
2666 {"$kt0", RTYPE_GP | 26}, \
2667 {"$k1", RTYPE_GP | 27}, \
2668 {"$kt1", RTYPE_GP | 27}, \
2669 {"$gp", RTYPE_GP | 28}, \
2670 {"$sp", RTYPE_GP | 29}, \
2671 {"$s8", RTYPE_GP | 30}, \
2672 {"$fp", RTYPE_GP | 30}, \
2673 {"$ra", RTYPE_GP | 31}
2675 #define MIPS16_SPECIAL_REGISTER_NAMES \
2676 {"$pc", RTYPE_PC | 0}
2678 #define MDMX_VECTOR_REGISTER_NAMES \
2679 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2680 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2681 {"$v2", RTYPE_VEC | 2}, \
2682 {"$v3", RTYPE_VEC | 3}, \
2683 {"$v4", RTYPE_VEC | 4}, \
2684 {"$v5", RTYPE_VEC | 5}, \
2685 {"$v6", RTYPE_VEC | 6}, \
2686 {"$v7", RTYPE_VEC | 7}, \
2687 {"$v8", RTYPE_VEC | 8}, \
2688 {"$v9", RTYPE_VEC | 9}, \
2689 {"$v10", RTYPE_VEC | 10}, \
2690 {"$v11", RTYPE_VEC | 11}, \
2691 {"$v12", RTYPE_VEC | 12}, \
2692 {"$v13", RTYPE_VEC | 13}, \
2693 {"$v14", RTYPE_VEC | 14}, \
2694 {"$v15", RTYPE_VEC | 15}, \
2695 {"$v16", RTYPE_VEC | 16}, \
2696 {"$v17", RTYPE_VEC | 17}, \
2697 {"$v18", RTYPE_VEC | 18}, \
2698 {"$v19", RTYPE_VEC | 19}, \
2699 {"$v20", RTYPE_VEC | 20}, \
2700 {"$v21", RTYPE_VEC | 21}, \
2701 {"$v22", RTYPE_VEC | 22}, \
2702 {"$v23", RTYPE_VEC | 23}, \
2703 {"$v24", RTYPE_VEC | 24}, \
2704 {"$v25", RTYPE_VEC | 25}, \
2705 {"$v26", RTYPE_VEC | 26}, \
2706 {"$v27", RTYPE_VEC | 27}, \
2707 {"$v28", RTYPE_VEC | 28}, \
2708 {"$v29", RTYPE_VEC | 29}, \
2709 {"$v30", RTYPE_VEC | 30}, \
2710 {"$v31", RTYPE_VEC | 31}
2712 #define R5900_I_NAMES \
2713 {"$I", RTYPE_R5900_I | 0}
2715 #define R5900_Q_NAMES \
2716 {"$Q", RTYPE_R5900_Q | 0}
2718 #define R5900_R_NAMES \
2719 {"$R", RTYPE_R5900_R | 0}
2721 #define R5900_ACC_NAMES \
2722 {"$ACC", RTYPE_R5900_ACC | 0 }
2724 #define MIPS_DSP_ACCUMULATOR_NAMES \
2725 {"$ac0", RTYPE_ACC | 0}, \
2726 {"$ac1", RTYPE_ACC | 1}, \
2727 {"$ac2", RTYPE_ACC | 2}, \
2728 {"$ac3", RTYPE_ACC | 3}
2730 static const struct regname reg_names[] = {
2731 GENERIC_REGISTER_NUMBERS,
2733 FPU_CONDITION_CODE_NAMES,
2734 COPROC_CONDITION_CODE_NAMES,
2736 /* The $txx registers depends on the abi,
2737 these will be added later into the symbol table from
2738 one of the tables below once mips_abi is set after
2739 parsing of arguments from the command line. */
2740 SYMBOLIC_REGISTER_NAMES,
2742 MIPS16_SPECIAL_REGISTER_NAMES,
2743 MDMX_VECTOR_REGISTER_NAMES,
2748 MIPS_DSP_ACCUMULATOR_NAMES,
2752 static const struct regname reg_names_o32[] = {
2753 O32_SYMBOLIC_REGISTER_NAMES,
2757 static const struct regname reg_names_n32n64[] = {
2758 N32N64_SYMBOLIC_REGISTER_NAMES,
2762 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2763 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2764 of these register symbols, return the associated vector register,
2765 otherwise return SYMVAL itself. */
2768 mips_prefer_vec_regno (unsigned int symval)
2770 if ((symval & -2) == (RTYPE_GP | 2))
2771 return RTYPE_VEC | (symval & 1);
2775 /* Return true if string [S, E) is a valid register name, storing its
2776 symbol value in *SYMVAL_PTR if so. */
2779 mips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr)
2784 /* Terminate name. */
2788 /* Look up the name. */
2789 symbol = symbol_find (s);
2792 if (!symbol || S_GET_SEGMENT (symbol) != reg_section)
2795 *symval_ptr = S_GET_VALUE (symbol);
2799 /* Return true if the string at *SPTR is a valid register name. Allow it
2800 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2803 When returning true, move *SPTR past the register, store the
2804 register's symbol value in *SYMVAL_PTR and the channel mask in
2805 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2806 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2807 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2810 mips_parse_register (char **sptr, unsigned int *symval_ptr,
2811 unsigned int *channels_ptr)
2815 unsigned int channels, symval, bit;
2817 /* Find end of name. */
2819 if (is_name_beginner (*e))
2821 while (is_part_of_name (*e))
2825 if (!mips_parse_register_1 (s, e, &symval))
2830 /* Eat characters from the end of the string that are valid
2831 channel suffixes. The preceding register must be $ACC or
2832 end with a digit, so there is no ambiguity. */
2835 for (q = "wzyx"; *q; q++, bit <<= 1)
2836 if (m > s && m[-1] == *q)
2843 || !mips_parse_register_1 (s, m, &symval)
2844 || (symval & (RTYPE_VI | RTYPE_VF | RTYPE_R5900_ACC)) == 0)
2849 *symval_ptr = symval;
2851 *channels_ptr = channels;
2855 /* Check if SPTR points at a valid register specifier according to TYPES.
2856 If so, then return 1, advance S to consume the specifier and store
2857 the register's number in REGNOP, otherwise return 0. */
2860 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2864 if (mips_parse_register (s, ®no, NULL))
2866 if (types & RTYPE_VEC)
2867 regno = mips_prefer_vec_regno (regno);
2876 as_warn (_("unrecognized register name `%s'"), *s);
2881 return regno <= RNUM_MASK;
2884 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2885 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2888 mips_parse_vu0_channels (char *s, unsigned int *channels)
2893 for (i = 0; i < 4; i++)
2894 if (*s == "xyzw"[i])
2896 *channels |= 1 << (3 - i);
2902 /* Token types for parsed operand lists. */
2903 enum mips_operand_token_type {
2904 /* A plain register, e.g. $f2. */
2907 /* A 4-bit XYZW channel mask. */
2910 /* A constant vector index, e.g. [1]. */
2913 /* A register vector index, e.g. [$2]. */
2916 /* A continuous range of registers, e.g. $s0-$s4. */
2919 /* A (possibly relocated) expression. */
2922 /* A floating-point value. */
2925 /* A single character. This can be '(', ')' or ',', but '(' only appears
2929 /* A doubled character, either "--" or "++". */
2932 /* The end of the operand list. */
2936 /* A parsed operand token. */
2937 struct mips_operand_token
2939 /* The type of token. */
2940 enum mips_operand_token_type type;
2943 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
2946 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
2947 unsigned int channels;
2949 /* The integer value of an OT_INTEGER_INDEX. */
2952 /* The two register symbol values involved in an OT_REG_RANGE. */
2954 unsigned int regno1;
2955 unsigned int regno2;
2958 /* The value of an OT_INTEGER. The value is represented as an
2959 expression and the relocation operators that were applied to
2960 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2961 relocation operators were used. */
2964 bfd_reloc_code_real_type relocs[3];
2967 /* The binary data for an OT_FLOAT constant, and the number of bytes
2970 unsigned char data[8];
2974 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
2979 /* An obstack used to construct lists of mips_operand_tokens. */
2980 static struct obstack mips_operand_tokens;
2982 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
2985 mips_add_token (struct mips_operand_token *token,
2986 enum mips_operand_token_type type)
2989 obstack_grow (&mips_operand_tokens, token, sizeof (*token));
2992 /* Check whether S is '(' followed by a register name. Add OT_CHAR
2993 and OT_REG tokens for them if so, and return a pointer to the first
2994 unconsumed character. Return null otherwise. */
2997 mips_parse_base_start (char *s)
2999 struct mips_operand_token token;
3000 unsigned int regno, channels;
3001 bfd_boolean decrement_p;
3007 SKIP_SPACE_TABS (s);
3009 /* Only match "--" as part of a base expression. In other contexts "--X"
3010 is a double negative. */
3011 decrement_p = (s[0] == '-' && s[1] == '-');
3015 SKIP_SPACE_TABS (s);
3018 /* Allow a channel specifier because that leads to better error messages
3019 than treating something like "$vf0x++" as an expression. */
3020 if (!mips_parse_register (&s, ®no, &channels))
3024 mips_add_token (&token, OT_CHAR);
3029 mips_add_token (&token, OT_DOUBLE_CHAR);
3032 token.u.regno = regno;
3033 mips_add_token (&token, OT_REG);
3037 token.u.channels = channels;
3038 mips_add_token (&token, OT_CHANNELS);
3041 /* For consistency, only match "++" as part of base expressions too. */
3042 SKIP_SPACE_TABS (s);
3043 if (s[0] == '+' && s[1] == '+')
3047 mips_add_token (&token, OT_DOUBLE_CHAR);
3053 /* Parse one or more tokens from S. Return a pointer to the first
3054 unconsumed character on success. Return null if an error was found
3055 and store the error text in insn_error. FLOAT_FORMAT is as for
3056 mips_parse_arguments. */
3059 mips_parse_argument_token (char *s, char float_format)
3061 char *end, *save_in;
3063 unsigned int regno1, regno2, channels;
3064 struct mips_operand_token token;
3066 /* First look for "($reg", since we want to treat that as an
3067 OT_CHAR and OT_REG rather than an expression. */
3068 end = mips_parse_base_start (s);
3072 /* Handle other characters that end up as OT_CHARs. */
3073 if (*s == ')' || *s == ',')
3076 mips_add_token (&token, OT_CHAR);
3081 /* Handle tokens that start with a register. */
3082 if (mips_parse_register (&s, ®no1, &channels))
3086 /* A register and a VU0 channel suffix. */
3087 token.u.regno = regno1;
3088 mips_add_token (&token, OT_REG);
3090 token.u.channels = channels;
3091 mips_add_token (&token, OT_CHANNELS);
3095 SKIP_SPACE_TABS (s);
3098 /* A register range. */
3100 SKIP_SPACE_TABS (s);
3101 if (!mips_parse_register (&s, ®no2, NULL))
3103 set_insn_error (0, _("invalid register range"));
3107 token.u.reg_range.regno1 = regno1;
3108 token.u.reg_range.regno2 = regno2;
3109 mips_add_token (&token, OT_REG_RANGE);
3113 /* Add the register itself. */
3114 token.u.regno = regno1;
3115 mips_add_token (&token, OT_REG);
3117 /* Check for a vector index. */
3121 SKIP_SPACE_TABS (s);
3122 if (mips_parse_register (&s, &token.u.regno, NULL))
3123 mips_add_token (&token, OT_REG_INDEX);
3126 expressionS element;
3128 my_getExpression (&element, s);
3129 if (element.X_op != O_constant)
3131 set_insn_error (0, _("vector element must be constant"));
3135 token.u.index = element.X_add_number;
3136 mips_add_token (&token, OT_INTEGER_INDEX);
3138 SKIP_SPACE_TABS (s);
3141 set_insn_error (0, _("missing `]'"));
3151 /* First try to treat expressions as floats. */
3152 save_in = input_line_pointer;
3153 input_line_pointer = s;
3154 err = md_atof (float_format, (char *) token.u.flt.data,
3155 &token.u.flt.length);
3156 end = input_line_pointer;
3157 input_line_pointer = save_in;
3160 set_insn_error (0, err);
3165 mips_add_token (&token, OT_FLOAT);
3170 /* Treat everything else as an integer expression. */
3171 token.u.integer.relocs[0] = BFD_RELOC_UNUSED;
3172 token.u.integer.relocs[1] = BFD_RELOC_UNUSED;
3173 token.u.integer.relocs[2] = BFD_RELOC_UNUSED;
3174 my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s);
3176 mips_add_token (&token, OT_INTEGER);
3180 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3181 if expressions should be treated as 32-bit floating-point constants,
3182 'd' if they should be treated as 64-bit floating-point constants,
3183 or 0 if they should be treated as integer expressions (the usual case).
3185 Return a list of tokens on success, otherwise return 0. The caller
3186 must obstack_free the list after use. */
3188 static struct mips_operand_token *
3189 mips_parse_arguments (char *s, char float_format)
3191 struct mips_operand_token token;
3193 SKIP_SPACE_TABS (s);
3196 s = mips_parse_argument_token (s, float_format);
3199 obstack_free (&mips_operand_tokens,
3200 obstack_finish (&mips_operand_tokens));
3203 SKIP_SPACE_TABS (s);
3205 mips_add_token (&token, OT_END);
3206 return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens);
3209 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3210 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3213 is_opcode_valid (const struct mips_opcode *mo)
3215 int isa = mips_opts.isa;
3216 int ase = mips_opts.ase;
3220 if (ISA_HAS_64BIT_REGS (isa))
3221 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
3222 if ((ase & mips_ases[i].flags) == mips_ases[i].flags)
3223 ase |= mips_ases[i].flags64;
3225 if (!opcode_is_member (mo, isa, ase, mips_opts.arch))
3228 /* Check whether the instruction or macro requires single-precision or
3229 double-precision floating-point support. Note that this information is
3230 stored differently in the opcode table for insns and macros. */
3231 if (mo->pinfo == INSN_MACRO)
3233 fp_s = mo->pinfo2 & INSN2_M_FP_S;
3234 fp_d = mo->pinfo2 & INSN2_M_FP_D;
3238 fp_s = mo->pinfo & FP_S;
3239 fp_d = mo->pinfo & FP_D;
3242 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
3245 if (fp_s && mips_opts.soft_float)
3251 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3252 selected ISA and architecture. */
3255 is_opcode_valid_16 (const struct mips_opcode *mo)
3257 return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch);
3260 /* Return TRUE if the size of the microMIPS opcode MO matches one
3261 explicitly requested. Always TRUE in the standard MIPS mode. */
3264 is_size_valid (const struct mips_opcode *mo)
3266 if (!mips_opts.micromips)
3269 if (mips_opts.insn32)
3271 if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4)
3273 if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0)
3276 if (!forced_insn_length)
3278 if (mo->pinfo == INSN_MACRO)
3280 return forced_insn_length == micromips_insn_length (mo);
3283 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3284 of the preceding instruction. Always TRUE in the standard MIPS mode.
3286 We don't accept macros in 16-bit delay slots to avoid a case where
3287 a macro expansion fails because it relies on a preceding 32-bit real
3288 instruction to have matched and does not handle the operands correctly.
3289 The only macros that may expand to 16-bit instructions are JAL that
3290 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3291 and BGT (that likewise cannot be placed in a delay slot) that decay to
3292 a NOP. In all these cases the macros precede any corresponding real
3293 instruction definitions in the opcode table, so they will match in the
3294 second pass where the size of the delay slot is ignored and therefore
3295 produce correct code. */
3298 is_delay_slot_valid (const struct mips_opcode *mo)
3300 if (!mips_opts.micromips)
3303 if (mo->pinfo == INSN_MACRO)
3304 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0;
3305 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
3306 && micromips_insn_length (mo) != 4)
3308 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
3309 && micromips_insn_length (mo) != 2)
3315 /* For consistency checking, verify that all bits of OPCODE are specified
3316 either by the match/mask part of the instruction definition, or by the
3317 operand list. Also build up a list of operands in OPERANDS.
3319 INSN_BITS says which bits of the instruction are significant.
3320 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3321 provides the mips_operand description of each operand. DECODE_OPERAND
3322 is null for MIPS16 instructions. */
3325 validate_mips_insn (const struct mips_opcode *opcode,
3326 unsigned long insn_bits,
3327 const struct mips_operand *(*decode_operand) (const char *),
3328 struct mips_operand_array *operands)
3331 unsigned long used_bits, doubled, undefined, opno, mask;
3332 const struct mips_operand *operand;
3334 mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask);
3335 if ((mask & opcode->match) != opcode->match)
3337 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3338 opcode->name, opcode->args);
3343 if (opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX)
3344 used_bits = mips_insert_operand (&mips_vu0_channel_mask, used_bits, -1);
3345 for (s = opcode->args; *s; ++s)
3358 if (!decode_operand)
3359 operand = decode_mips16_operand (*s, FALSE);
3361 operand = decode_operand (s);
3362 if (!operand && opcode->pinfo != INSN_MACRO)
3364 as_bad (_("internal: unknown operand type: %s %s"),
3365 opcode->name, opcode->args);
3368 gas_assert (opno < MAX_OPERANDS);
3369 operands->operand[opno] = operand;
3370 if (operand && operand->type != OP_VU0_MATCH_SUFFIX)
3372 used_bits = mips_insert_operand (operand, used_bits, -1);
3373 if (operand->type == OP_MDMX_IMM_REG)
3374 /* Bit 5 is the format selector (OB vs QH). The opcode table
3375 has separate entries for each format. */
3376 used_bits &= ~(1 << (operand->lsb + 5));
3377 if (operand->type == OP_ENTRY_EXIT_LIST)
3378 used_bits &= ~(mask & 0x700);
3380 /* Skip prefix characters. */
3381 if (decode_operand && (*s == '+' || *s == 'm' || *s == '-'))
3386 doubled = used_bits & mask & insn_bits;
3389 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3390 " %s %s"), doubled, opcode->name, opcode->args);
3394 undefined = ~used_bits & insn_bits;
3395 if (opcode->pinfo != INSN_MACRO && undefined)
3397 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3398 undefined, opcode->name, opcode->args);
3401 used_bits &= ~insn_bits;
3404 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3405 used_bits, opcode->name, opcode->args);
3411 /* The MIPS16 version of validate_mips_insn. */
3414 validate_mips16_insn (const struct mips_opcode *opcode,
3415 struct mips_operand_array *operands)
3417 if (opcode->args[0] == 'a' || opcode->args[0] == 'i')
3419 /* In this case OPCODE defines the first 16 bits in a 32-bit jump
3420 instruction. Use TMP to describe the full instruction. */
3421 struct mips_opcode tmp;
3426 return validate_mips_insn (&tmp, 0xffffffff, 0, operands);
3428 return validate_mips_insn (opcode, 0xffff, 0, operands);
3431 /* The microMIPS version of validate_mips_insn. */
3434 validate_micromips_insn (const struct mips_opcode *opc,
3435 struct mips_operand_array *operands)
3437 unsigned long insn_bits;
3438 unsigned long major;
3439 unsigned int length;
3441 if (opc->pinfo == INSN_MACRO)
3442 return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand,
3445 length = micromips_insn_length (opc);
3446 if (length != 2 && length != 4)
3448 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3449 "%s %s"), length, opc->name, opc->args);
3452 major = opc->match >> (10 + 8 * (length - 2));
3453 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
3454 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
3456 as_bad (_("internal error: bad microMIPS opcode "
3457 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
3461 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3462 insn_bits = 1 << 4 * length;
3463 insn_bits <<= 4 * length;
3465 return validate_mips_insn (opc, insn_bits, decode_micromips_operand,
3469 /* This function is called once, at assembler startup time. It should set up
3470 all the tables, etc. that the MD part of the assembler will need. */
3475 const char *retval = NULL;
3479 if (mips_pic != NO_PIC)
3481 if (g_switch_seen && g_switch_value != 0)
3482 as_bad (_("-G may not be used in position-independent code"));
3485 else if (mips_abicalls)
3487 if (g_switch_seen && g_switch_value != 0)
3488 as_bad (_("-G may not be used with abicalls"));
3492 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch))
3493 as_warn (_("could not set architecture and machine"));
3495 op_hash = hash_new ();
3497 mips_operands = XCNEWVEC (struct mips_operand_array, NUMOPCODES);
3498 for (i = 0; i < NUMOPCODES;)
3500 const char *name = mips_opcodes[i].name;
3502 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
3505 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
3506 mips_opcodes[i].name, retval);
3507 /* Probably a memory allocation problem? Give up now. */
3508 as_fatal (_("broken assembler, no assembly attempted"));
3512 if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff,
3513 decode_mips_operand, &mips_operands[i]))
3515 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3517 create_insn (&nop_insn, mips_opcodes + i);
3518 if (mips_fix_loongson2f_nop)
3519 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
3520 nop_insn.fixed_p = 1;
3524 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
3527 mips16_op_hash = hash_new ();
3528 mips16_operands = XCNEWVEC (struct mips_operand_array,
3529 bfd_mips16_num_opcodes);
3532 while (i < bfd_mips16_num_opcodes)
3534 const char *name = mips16_opcodes[i].name;
3536 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
3538 as_fatal (_("internal: can't hash `%s': %s"),
3539 mips16_opcodes[i].name, retval);
3542 if (!validate_mips16_insn (&mips16_opcodes[i], &mips16_operands[i]))
3544 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3546 create_insn (&mips16_nop_insn, mips16_opcodes + i);
3547 mips16_nop_insn.fixed_p = 1;
3551 while (i < bfd_mips16_num_opcodes
3552 && strcmp (mips16_opcodes[i].name, name) == 0);
3555 micromips_op_hash = hash_new ();
3556 micromips_operands = XCNEWVEC (struct mips_operand_array,
3557 bfd_micromips_num_opcodes);
3560 while (i < bfd_micromips_num_opcodes)
3562 const char *name = micromips_opcodes[i].name;
3564 retval = hash_insert (micromips_op_hash, name,
3565 (void *) µmips_opcodes[i]);
3567 as_fatal (_("internal: can't hash `%s': %s"),
3568 micromips_opcodes[i].name, retval);
3571 struct mips_cl_insn *micromips_nop_insn;
3573 if (!validate_micromips_insn (µmips_opcodes[i],
3574 µmips_operands[i]))
3577 if (micromips_opcodes[i].pinfo != INSN_MACRO)
3579 if (micromips_insn_length (micromips_opcodes + i) == 2)
3580 micromips_nop_insn = µmips_nop16_insn;
3581 else if (micromips_insn_length (micromips_opcodes + i) == 4)
3582 micromips_nop_insn = µmips_nop32_insn;
3586 if (micromips_nop_insn->insn_mo == NULL
3587 && strcmp (name, "nop") == 0)
3589 create_insn (micromips_nop_insn, micromips_opcodes + i);
3590 micromips_nop_insn->fixed_p = 1;
3594 while (++i < bfd_micromips_num_opcodes
3595 && strcmp (micromips_opcodes[i].name, name) == 0);
3599 as_fatal (_("broken assembler, no assembly attempted"));
3601 /* We add all the general register names to the symbol table. This
3602 helps us detect invalid uses of them. */
3603 for (i = 0; reg_names[i].name; i++)
3604 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
3605 reg_names[i].num, /* & RNUM_MASK, */
3606 &zero_address_frag));
3608 for (i = 0; reg_names_n32n64[i].name; i++)
3609 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
3610 reg_names_n32n64[i].num, /* & RNUM_MASK, */
3611 &zero_address_frag));
3613 for (i = 0; reg_names_o32[i].name; i++)
3614 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
3615 reg_names_o32[i].num, /* & RNUM_MASK, */
3616 &zero_address_frag));
3618 for (i = 0; i < 32; i++)
3622 /* R5900 VU0 floating-point register. */
3623 sprintf (regname, "$vf%d", i);
3624 symbol_table_insert (symbol_new (regname, reg_section,
3625 RTYPE_VF | i, &zero_address_frag));
3627 /* R5900 VU0 integer register. */
3628 sprintf (regname, "$vi%d", i);
3629 symbol_table_insert (symbol_new (regname, reg_section,
3630 RTYPE_VI | i, &zero_address_frag));
3633 sprintf (regname, "$w%d", i);
3634 symbol_table_insert (symbol_new (regname, reg_section,
3635 RTYPE_MSA | i, &zero_address_frag));
3638 obstack_init (&mips_operand_tokens);
3640 mips_no_prev_insn ();
3643 mips_cprmask[0] = 0;
3644 mips_cprmask[1] = 0;
3645 mips_cprmask[2] = 0;
3646 mips_cprmask[3] = 0;
3648 /* set the default alignment for the text section (2**2) */
3649 record_alignment (text_section, 2);
3651 bfd_set_gp_size (stdoutput, g_switch_value);
3653 /* On a native system other than VxWorks, sections must be aligned
3654 to 16 byte boundaries. When configured for an embedded ELF
3655 target, we don't bother. */
3656 if (strncmp (TARGET_OS, "elf", 3) != 0
3657 && strncmp (TARGET_OS, "vxworks", 7) != 0)
3659 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
3660 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
3661 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
3664 /* Create a .reginfo section for register masks and a .mdebug
3665 section for debugging information. */
3673 subseg = now_subseg;
3675 /* The ABI says this section should be loaded so that the
3676 running program can access it. However, we don't load it
3677 if we are configured for an embedded target */
3678 flags = SEC_READONLY | SEC_DATA;
3679 if (strncmp (TARGET_OS, "elf", 3) != 0)
3680 flags |= SEC_ALLOC | SEC_LOAD;
3682 if (mips_abi != N64_ABI)
3684 sec = subseg_new (".reginfo", (subsegT) 0);
3686 bfd_set_section_flags (stdoutput, sec, flags);
3687 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
3689 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
3693 /* The 64-bit ABI uses a .MIPS.options section rather than
3694 .reginfo section. */
3695 sec = subseg_new (".MIPS.options", (subsegT) 0);
3696 bfd_set_section_flags (stdoutput, sec, flags);
3697 bfd_set_section_alignment (stdoutput, sec, 3);
3699 /* Set up the option header. */
3701 Elf_Internal_Options opthdr;
3704 opthdr.kind = ODK_REGINFO;
3705 opthdr.size = (sizeof (Elf_External_Options)
3706 + sizeof (Elf64_External_RegInfo));
3709 f = frag_more (sizeof (Elf_External_Options));
3710 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
3711 (Elf_External_Options *) f);
3713 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
3717 sec = subseg_new (".MIPS.abiflags", (subsegT) 0);
3718 bfd_set_section_flags (stdoutput, sec,
3719 SEC_READONLY | SEC_DATA | SEC_ALLOC | SEC_LOAD);
3720 bfd_set_section_alignment (stdoutput, sec, 3);
3721 mips_flags_frag = frag_more (sizeof (Elf_External_ABIFlags_v0));
3723 if (ECOFF_DEBUGGING)
3725 sec = subseg_new (".mdebug", (subsegT) 0);
3726 (void) bfd_set_section_flags (stdoutput, sec,
3727 SEC_HAS_CONTENTS | SEC_READONLY);
3728 (void) bfd_set_section_alignment (stdoutput, sec, 2);
3730 else if (mips_flag_pdr)
3732 pdr_seg = subseg_new (".pdr", (subsegT) 0);
3733 (void) bfd_set_section_flags (stdoutput, pdr_seg,
3734 SEC_READONLY | SEC_RELOC
3736 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
3739 subseg_set (seg, subseg);
3742 if (mips_fix_vr4120)
3743 init_vr4120_conflicts ();
3747 fpabi_incompatible_with (int fpabi, const char *what)
3749 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3750 Tag_GNU_MIPS_ABI_FP, fpabi, what);
3754 fpabi_requires (int fpabi, const char *what)
3756 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3757 Tag_GNU_MIPS_ABI_FP, fpabi, what);
3760 /* Check -mabi and register sizes against the specified FP ABI. */
3762 check_fpabi (int fpabi)
3766 case Val_GNU_MIPS_ABI_FP_DOUBLE:
3767 if (file_mips_opts.soft_float)
3768 fpabi_incompatible_with (fpabi, "softfloat");
3769 else if (file_mips_opts.single_float)
3770 fpabi_incompatible_with (fpabi, "singlefloat");
3771 if (file_mips_opts.gp == 64 && file_mips_opts.fp == 32)
3772 fpabi_incompatible_with (fpabi, "gp=64 fp=32");
3773 else if (file_mips_opts.gp == 32 && file_mips_opts.fp == 64)
3774 fpabi_incompatible_with (fpabi, "gp=32 fp=64");
3777 case Val_GNU_MIPS_ABI_FP_XX:
3778 if (mips_abi != O32_ABI)
3779 fpabi_requires (fpabi, "-mabi=32");
3780 else if (file_mips_opts.soft_float)
3781 fpabi_incompatible_with (fpabi, "softfloat");
3782 else if (file_mips_opts.single_float)
3783 fpabi_incompatible_with (fpabi, "singlefloat");
3784 else if (file_mips_opts.fp != 0)
3785 fpabi_requires (fpabi, "fp=xx");
3788 case Val_GNU_MIPS_ABI_FP_64A:
3789 case Val_GNU_MIPS_ABI_FP_64:
3790 if (mips_abi != O32_ABI)
3791 fpabi_requires (fpabi, "-mabi=32");
3792 else if (file_mips_opts.soft_float)
3793 fpabi_incompatible_with (fpabi, "softfloat");
3794 else if (file_mips_opts.single_float)
3795 fpabi_incompatible_with (fpabi, "singlefloat");
3796 else if (file_mips_opts.fp != 64)
3797 fpabi_requires (fpabi, "fp=64");
3798 else if (fpabi == Val_GNU_MIPS_ABI_FP_64 && !file_mips_opts.oddspreg)
3799 fpabi_incompatible_with (fpabi, "nooddspreg");
3800 else if (fpabi == Val_GNU_MIPS_ABI_FP_64A && file_mips_opts.oddspreg)
3801 fpabi_requires (fpabi, "nooddspreg");
3804 case Val_GNU_MIPS_ABI_FP_SINGLE:
3805 if (file_mips_opts.soft_float)
3806 fpabi_incompatible_with (fpabi, "softfloat");
3807 else if (!file_mips_opts.single_float)
3808 fpabi_requires (fpabi, "singlefloat");
3811 case Val_GNU_MIPS_ABI_FP_SOFT:
3812 if (!file_mips_opts.soft_float)
3813 fpabi_requires (fpabi, "softfloat");
3816 case Val_GNU_MIPS_ABI_FP_OLD_64:
3817 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
3818 Tag_GNU_MIPS_ABI_FP, fpabi);
3821 case Val_GNU_MIPS_ABI_FP_NAN2008:
3822 /* Silently ignore compatibility value. */
3826 as_warn (_(".gnu_attribute %d,%d is not a recognized"
3827 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP, fpabi);
3832 /* Perform consistency checks on the current options. */
3835 mips_check_options (struct mips_set_options *opts, bfd_boolean abi_checks)
3837 /* Check the size of integer registers agrees with the ABI and ISA. */
3838 if (opts->gp == 64 && !ISA_HAS_64BIT_REGS (opts->isa))
3839 as_bad (_("`gp=64' used with a 32-bit processor"));
3841 && opts->gp == 32 && ABI_NEEDS_64BIT_REGS (mips_abi))
3842 as_bad (_("`gp=32' used with a 64-bit ABI"));
3844 && opts->gp == 64 && ABI_NEEDS_32BIT_REGS (mips_abi))
3845 as_bad (_("`gp=64' used with a 32-bit ABI"));
3847 /* Check the size of the float registers agrees with the ABI and ISA. */
3851 if (!CPU_HAS_LDC1_SDC1 (opts->arch))
3852 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
3853 else if (opts->single_float == 1)
3854 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
3857 if (!ISA_HAS_64BIT_FPRS (opts->isa))
3858 as_bad (_("`fp=64' used with a 32-bit fpu"));
3860 && ABI_NEEDS_32BIT_REGS (mips_abi)
3861 && !ISA_HAS_MXHC1 (opts->isa))
3862 as_warn (_("`fp=64' used with a 32-bit ABI"));
3866 && ABI_NEEDS_64BIT_REGS (mips_abi))
3867 as_warn (_("`fp=32' used with a 64-bit ABI"));
3868 if (ISA_IS_R6 (opts->isa) && opts->single_float == 0)
3869 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
3872 as_bad (_("Unknown size of floating point registers"));
3876 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !opts->oddspreg)
3877 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
3879 if (opts->micromips == 1 && opts->mips16 == 1)
3880 as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips");
3881 else if (ISA_IS_R6 (opts->isa)
3882 && (opts->micromips == 1
3883 || opts->mips16 == 1))
3884 as_fatal (_("`%s' cannot be used with `%s'"),
3885 opts->micromips ? "micromips" : "mips16",
3886 mips_cpu_info_from_isa (opts->isa)->name);
3888 if (ISA_IS_R6 (opts->isa) && mips_relax_branch)
3889 as_fatal (_("branch relaxation is not supported in `%s'"),
3890 mips_cpu_info_from_isa (opts->isa)->name);
3893 /* Perform consistency checks on the module level options exactly once.
3894 This is a deferred check that happens:
3895 at the first .set directive
3896 or, at the first pseudo op that generates code (inc .dc.a)
3897 or, at the first instruction
3901 file_mips_check_options (void)
3903 const struct mips_cpu_info *arch_info = 0;
3905 if (file_mips_opts_checked)
3908 /* The following code determines the register size.
3909 Similar code was added to GCC 3.3 (see override_options() in
3910 config/mips/mips.c). The GAS and GCC code should be kept in sync
3911 as much as possible. */
3913 if (file_mips_opts.gp < 0)
3915 /* Infer the integer register size from the ABI and processor.
3916 Restrict ourselves to 32-bit registers if that's all the
3917 processor has, or if the ABI cannot handle 64-bit registers. */
3918 file_mips_opts.gp = (ABI_NEEDS_32BIT_REGS (mips_abi)
3919 || !ISA_HAS_64BIT_REGS (file_mips_opts.isa))
3923 if (file_mips_opts.fp < 0)
3925 /* No user specified float register size.
3926 ??? GAS treats single-float processors as though they had 64-bit
3927 float registers (although it complains when double-precision
3928 instructions are used). As things stand, saying they have 32-bit
3929 registers would lead to spurious "register must be even" messages.
3930 So here we assume float registers are never smaller than the
3932 if (file_mips_opts.gp == 64)
3933 /* 64-bit integer registers implies 64-bit float registers. */
3934 file_mips_opts.fp = 64;
3935 else if ((file_mips_opts.ase & FP64_ASES)
3936 && ISA_HAS_64BIT_FPRS (file_mips_opts.isa))
3937 /* Handle ASEs that require 64-bit float registers, if possible. */
3938 file_mips_opts.fp = 64;
3939 else if (ISA_IS_R6 (mips_opts.isa))
3940 /* R6 implies 64-bit float registers. */
3941 file_mips_opts.fp = 64;
3943 /* 32-bit float registers. */
3944 file_mips_opts.fp = 32;
3947 arch_info = mips_cpu_info_from_arch (file_mips_opts.arch);
3949 /* Disable operations on odd-numbered floating-point registers by default
3950 when using the FPXX ABI. */
3951 if (file_mips_opts.oddspreg < 0)
3953 if (file_mips_opts.fp == 0)
3954 file_mips_opts.oddspreg = 0;
3956 file_mips_opts.oddspreg = 1;
3959 /* End of GCC-shared inference code. */
3961 /* This flag is set when we have a 64-bit capable CPU but use only
3962 32-bit wide registers. Note that EABI does not use it. */
3963 if (ISA_HAS_64BIT_REGS (file_mips_opts.isa)
3964 && ((mips_abi == NO_ABI && file_mips_opts.gp == 32)
3965 || mips_abi == O32_ABI))
3968 if (file_mips_opts.isa == ISA_MIPS1 && mips_trap)
3969 as_bad (_("trap exception not supported at ISA 1"));
3971 /* If the selected architecture includes support for ASEs, enable
3972 generation of code for them. */
3973 if (file_mips_opts.mips16 == -1)
3974 file_mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_opts.arch)) ? 1 : 0;
3975 if (file_mips_opts.micromips == -1)
3976 file_mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_opts.arch))
3979 if (mips_nan2008 == -1)
3980 mips_nan2008 = (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) ? 0 : 1;
3981 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts.isa) && mips_nan2008 == 0)
3982 as_fatal (_("`%s' does not support legacy NaN"),
3983 mips_cpu_info_from_arch (file_mips_opts.arch)->name);
3985 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
3986 being selected implicitly. */
3987 if (file_mips_opts.fp != 64)
3988 file_ase_explicit |= ASE_MIPS3D | ASE_MDMX | ASE_MSA;
3990 /* If the user didn't explicitly select or deselect a particular ASE,
3991 use the default setting for the CPU. */
3992 file_mips_opts.ase |= (arch_info->ase & ~file_ase_explicit);
3994 /* Set up the current options. These may change throughout assembly. */
3995 mips_opts = file_mips_opts;
3997 mips_check_isa_supports_ases ();
3998 mips_check_options (&file_mips_opts, TRUE);
3999 file_mips_opts_checked = TRUE;
4001 if (!bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch))
4002 as_warn (_("could not set architecture and machine"));
4006 md_assemble (char *str)
4008 struct mips_cl_insn insn;
4009 bfd_reloc_code_real_type unused_reloc[3]
4010 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
4012 file_mips_check_options ();
4014 imm_expr.X_op = O_absent;
4015 offset_expr.X_op = O_absent;
4016 offset_reloc[0] = BFD_RELOC_UNUSED;
4017 offset_reloc[1] = BFD_RELOC_UNUSED;
4018 offset_reloc[2] = BFD_RELOC_UNUSED;
4020 mips_mark_labels ();
4021 mips_assembling_insn = TRUE;
4022 clear_insn_error ();
4024 if (mips_opts.mips16)
4025 mips16_ip (str, &insn);
4028 mips_ip (str, &insn);
4029 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4030 str, insn.insn_opcode));
4034 report_insn_error (str);
4035 else if (insn.insn_mo->pinfo == INSN_MACRO)
4038 if (mips_opts.mips16)
4039 mips16_macro (&insn);
4046 if (offset_expr.X_op != O_absent)
4047 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
4049 append_insn (&insn, NULL, unused_reloc, FALSE);
4052 mips_assembling_insn = FALSE;
4055 /* Convenience functions for abstracting away the differences between
4056 MIPS16 and non-MIPS16 relocations. */
4058 static inline bfd_boolean
4059 mips16_reloc_p (bfd_reloc_code_real_type reloc)
4063 case BFD_RELOC_MIPS16_JMP:
4064 case BFD_RELOC_MIPS16_GPREL:
4065 case BFD_RELOC_MIPS16_GOT16:
4066 case BFD_RELOC_MIPS16_CALL16:
4067 case BFD_RELOC_MIPS16_HI16_S:
4068 case BFD_RELOC_MIPS16_HI16:
4069 case BFD_RELOC_MIPS16_LO16:
4070 case BFD_RELOC_MIPS16_16_PCREL_S1:
4078 static inline bfd_boolean
4079 micromips_reloc_p (bfd_reloc_code_real_type reloc)
4083 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
4084 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
4085 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
4086 case BFD_RELOC_MICROMIPS_GPREL16:
4087 case BFD_RELOC_MICROMIPS_JMP:
4088 case BFD_RELOC_MICROMIPS_HI16:
4089 case BFD_RELOC_MICROMIPS_HI16_S:
4090 case BFD_RELOC_MICROMIPS_LO16:
4091 case BFD_RELOC_MICROMIPS_LITERAL:
4092 case BFD_RELOC_MICROMIPS_GOT16:
4093 case BFD_RELOC_MICROMIPS_CALL16:
4094 case BFD_RELOC_MICROMIPS_GOT_HI16:
4095 case BFD_RELOC_MICROMIPS_GOT_LO16:
4096 case BFD_RELOC_MICROMIPS_CALL_HI16:
4097 case BFD_RELOC_MICROMIPS_CALL_LO16:
4098 case BFD_RELOC_MICROMIPS_SUB:
4099 case BFD_RELOC_MICROMIPS_GOT_PAGE:
4100 case BFD_RELOC_MICROMIPS_GOT_OFST:
4101 case BFD_RELOC_MICROMIPS_GOT_DISP:
4102 case BFD_RELOC_MICROMIPS_HIGHEST:
4103 case BFD_RELOC_MICROMIPS_HIGHER:
4104 case BFD_RELOC_MICROMIPS_SCN_DISP:
4105 case BFD_RELOC_MICROMIPS_JALR:
4113 static inline bfd_boolean
4114 jmp_reloc_p (bfd_reloc_code_real_type reloc)
4116 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
4119 static inline bfd_boolean
4120 b_reloc_p (bfd_reloc_code_real_type reloc)
4122 return (reloc == BFD_RELOC_MIPS_26_PCREL_S2
4123 || reloc == BFD_RELOC_MIPS_21_PCREL_S2
4124 || reloc == BFD_RELOC_16_PCREL_S2
4125 || reloc == BFD_RELOC_MIPS16_16_PCREL_S1
4126 || reloc == BFD_RELOC_MICROMIPS_16_PCREL_S1
4127 || reloc == BFD_RELOC_MICROMIPS_10_PCREL_S1
4128 || reloc == BFD_RELOC_MICROMIPS_7_PCREL_S1);
4131 static inline bfd_boolean
4132 got16_reloc_p (bfd_reloc_code_real_type reloc)
4134 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
4135 || reloc == BFD_RELOC_MICROMIPS_GOT16);
4138 static inline bfd_boolean
4139 hi16_reloc_p (bfd_reloc_code_real_type reloc)
4141 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
4142 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
4145 static inline bfd_boolean
4146 lo16_reloc_p (bfd_reloc_code_real_type reloc)
4148 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
4149 || reloc == BFD_RELOC_MICROMIPS_LO16);
4152 static inline bfd_boolean
4153 jalr_reloc_p (bfd_reloc_code_real_type reloc)
4155 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
4158 static inline bfd_boolean
4159 gprel16_reloc_p (bfd_reloc_code_real_type reloc)
4161 return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL
4162 || reloc == BFD_RELOC_MICROMIPS_GPREL16);
4165 /* Return true if RELOC is a PC-relative relocation that does not have
4166 full address range. */
4168 static inline bfd_boolean
4169 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc)
4173 case BFD_RELOC_16_PCREL_S2:
4174 case BFD_RELOC_MIPS16_16_PCREL_S1:
4175 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
4176 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
4177 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
4178 case BFD_RELOC_MIPS_21_PCREL_S2:
4179 case BFD_RELOC_MIPS_26_PCREL_S2:
4180 case BFD_RELOC_MIPS_18_PCREL_S3:
4181 case BFD_RELOC_MIPS_19_PCREL_S2:
4184 case BFD_RELOC_32_PCREL:
4185 case BFD_RELOC_HI16_S_PCREL:
4186 case BFD_RELOC_LO16_PCREL:
4187 return HAVE_64BIT_ADDRESSES;
4194 /* Return true if the given relocation might need a matching %lo().
4195 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4196 need a matching %lo() when applied to local symbols. */
4198 static inline bfd_boolean
4199 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
4201 return (HAVE_IN_PLACE_ADDENDS
4202 && (hi16_reloc_p (reloc)
4203 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4204 all GOT16 relocations evaluate to "G". */
4205 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
4208 /* Return the type of %lo() reloc needed by RELOC, given that
4209 reloc_needs_lo_p. */
4211 static inline bfd_reloc_code_real_type
4212 matching_lo_reloc (bfd_reloc_code_real_type reloc)
4214 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
4215 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
4219 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
4222 static inline bfd_boolean
4223 fixup_has_matching_lo_p (fixS *fixp)
4225 return (fixp->fx_next != NULL
4226 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
4227 && fixp->fx_addsy == fixp->fx_next->fx_addsy
4228 && fixp->fx_offset == fixp->fx_next->fx_offset);
4231 /* Move all labels in LABELS to the current insertion point. TEXT_P
4232 says whether the labels refer to text or data. */
4235 mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
4237 struct insn_label_list *l;
4240 for (l = labels; l != NULL; l = l->next)
4242 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
4243 symbol_set_frag (l->label, frag_now);
4244 val = (valueT) frag_now_fix ();
4245 /* MIPS16/microMIPS text labels are stored as odd. */
4246 if (text_p && HAVE_CODE_COMPRESSION)
4248 S_SET_VALUE (l->label, val);
4252 /* Move all labels in insn_labels to the current insertion point
4253 and treat them as text labels. */
4256 mips_move_text_labels (void)
4258 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
4262 s_is_linkonce (symbolS *sym, segT from_seg)
4264 bfd_boolean linkonce = FALSE;
4265 segT symseg = S_GET_SEGMENT (sym);
4267 if (symseg != from_seg && !S_IS_LOCAL (sym))
4269 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
4271 /* The GNU toolchain uses an extension for ELF: a section
4272 beginning with the magic string .gnu.linkonce is a
4273 linkonce section. */
4274 if (strncmp (segment_name (symseg), ".gnu.linkonce",
4275 sizeof ".gnu.linkonce" - 1) == 0)
4281 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
4282 linker to handle them specially, such as generating jalx instructions
4283 when needed. We also make them odd for the duration of the assembly,
4284 in order to generate the right sort of code. We will make them even
4285 in the adjust_symtab routine, while leaving them marked. This is
4286 convenient for the debugger and the disassembler. The linker knows
4287 to make them odd again. */
4290 mips_compressed_mark_label (symbolS *label)
4292 gas_assert (HAVE_CODE_COMPRESSION);
4294 if (mips_opts.mips16)
4295 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
4297 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
4298 if ((S_GET_VALUE (label) & 1) == 0
4299 /* Don't adjust the address if the label is global or weak, or
4300 in a link-once section, since we'll be emitting symbol reloc
4301 references to it which will be patched up by the linker, and
4302 the final value of the symbol may or may not be MIPS16/microMIPS. */
4303 && !S_IS_WEAK (label)
4304 && !S_IS_EXTERNAL (label)
4305 && !s_is_linkonce (label, now_seg))
4306 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
4309 /* Mark preceding MIPS16 or microMIPS instruction labels. */
4312 mips_compressed_mark_labels (void)
4314 struct insn_label_list *l;
4316 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next)
4317 mips_compressed_mark_label (l->label);
4320 /* End the current frag. Make it a variant frag and record the
4324 relax_close_frag (void)
4326 mips_macro_warning.first_frag = frag_now;
4327 frag_var (rs_machine_dependent, 0, 0,
4328 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
4329 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
4331 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
4332 mips_relax.first_fixup = 0;
4335 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
4336 See the comment above RELAX_ENCODE for more details. */
4339 relax_start (symbolS *symbol)
4341 gas_assert (mips_relax.sequence == 0);
4342 mips_relax.sequence = 1;
4343 mips_relax.symbol = symbol;
4346 /* Start generating the second version of a relaxable sequence.
4347 See the comment above RELAX_ENCODE for more details. */
4352 gas_assert (mips_relax.sequence == 1);
4353 mips_relax.sequence = 2;
4356 /* End the current relaxable sequence. */
4361 gas_assert (mips_relax.sequence == 2);
4362 relax_close_frag ();
4363 mips_relax.sequence = 0;
4366 /* Return true if IP is a delayed branch or jump. */
4368 static inline bfd_boolean
4369 delayed_branch_p (const struct mips_cl_insn *ip)
4371 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
4372 | INSN_COND_BRANCH_DELAY
4373 | INSN_COND_BRANCH_LIKELY)) != 0;
4376 /* Return true if IP is a compact branch or jump. */
4378 static inline bfd_boolean
4379 compact_branch_p (const struct mips_cl_insn *ip)
4381 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
4382 | INSN2_COND_BRANCH)) != 0;
4385 /* Return true if IP is an unconditional branch or jump. */
4387 static inline bfd_boolean
4388 uncond_branch_p (const struct mips_cl_insn *ip)
4390 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
4391 || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0);
4394 /* Return true if IP is a branch-likely instruction. */
4396 static inline bfd_boolean
4397 branch_likely_p (const struct mips_cl_insn *ip)
4399 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
4402 /* Return the type of nop that should be used to fill the delay slot
4403 of delayed branch IP. */
4405 static struct mips_cl_insn *
4406 get_delay_slot_nop (const struct mips_cl_insn *ip)
4408 if (mips_opts.micromips
4409 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
4410 return µmips_nop32_insn;
4414 /* Return a mask that has bit N set if OPCODE reads the register(s)
4418 insn_read_mask (const struct mips_opcode *opcode)
4420 return (opcode->pinfo & INSN_READ_ALL) >> INSN_READ_SHIFT;
4423 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4427 insn_write_mask (const struct mips_opcode *opcode)
4429 return (opcode->pinfo & INSN_WRITE_ALL) >> INSN_WRITE_SHIFT;
4432 /* Return a mask of the registers specified by operand OPERAND of INSN.
4433 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4437 operand_reg_mask (const struct mips_cl_insn *insn,
4438 const struct mips_operand *operand,
4439 unsigned int type_mask)
4441 unsigned int uval, vsel;
4443 switch (operand->type)
4450 case OP_ADDIUSP_INT:
4451 case OP_ENTRY_EXIT_LIST:
4452 case OP_REPEAT_DEST_REG:
4453 case OP_REPEAT_PREV_REG:
4456 case OP_VU0_MATCH_SUFFIX:
4461 case OP_OPTIONAL_REG:
4463 const struct mips_reg_operand *reg_op;
4465 reg_op = (const struct mips_reg_operand *) operand;
4466 if (!(type_mask & (1 << reg_op->reg_type)))
4468 uval = insn_extract_operand (insn, operand);
4469 return 1 << mips_decode_reg_operand (reg_op, uval);
4474 const struct mips_reg_pair_operand *pair_op;
4476 pair_op = (const struct mips_reg_pair_operand *) operand;
4477 if (!(type_mask & (1 << pair_op->reg_type)))
4479 uval = insn_extract_operand (insn, operand);
4480 return (1 << pair_op->reg1_map[uval]) | (1 << pair_op->reg2_map[uval]);
4483 case OP_CLO_CLZ_DEST:
4484 if (!(type_mask & (1 << OP_REG_GP)))
4486 uval = insn_extract_operand (insn, operand);
4487 return (1 << (uval & 31)) | (1 << (uval >> 5));
4490 if (!(type_mask & (1 << OP_REG_GP)))
4492 uval = insn_extract_operand (insn, operand);
4493 gas_assert ((uval & 31) == (uval >> 5));
4494 return 1 << (uval & 31);
4497 case OP_NON_ZERO_REG:
4498 if (!(type_mask & (1 << OP_REG_GP)))
4500 uval = insn_extract_operand (insn, operand);
4501 return 1 << (uval & 31);
4503 case OP_LWM_SWM_LIST:
4506 case OP_SAVE_RESTORE_LIST:
4509 case OP_MDMX_IMM_REG:
4510 if (!(type_mask & (1 << OP_REG_VEC)))
4512 uval = insn_extract_operand (insn, operand);
4514 if ((vsel & 0x18) == 0x18)
4516 return 1 << (uval & 31);
4519 if (!(type_mask & (1 << OP_REG_GP)))
4521 return 1 << insn_extract_operand (insn, operand);
4526 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4527 where bit N of OPNO_MASK is set if operand N should be included.
4528 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4532 insn_reg_mask (const struct mips_cl_insn *insn,
4533 unsigned int type_mask, unsigned int opno_mask)
4535 unsigned int opno, reg_mask;
4539 while (opno_mask != 0)
4542 reg_mask |= operand_reg_mask (insn, insn_opno (insn, opno), type_mask);
4549 /* Return the mask of core registers that IP reads. */
4552 gpr_read_mask (const struct mips_cl_insn *ip)
4554 unsigned long pinfo, pinfo2;
4557 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_read_mask (ip->insn_mo));
4558 pinfo = ip->insn_mo->pinfo;
4559 pinfo2 = ip->insn_mo->pinfo2;
4560 if (pinfo & INSN_UDI)
4562 /* UDI instructions have traditionally been assumed to read RS
4564 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
4565 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
4567 if (pinfo & INSN_READ_GPR_24)
4569 if (pinfo2 & INSN2_READ_GPR_16)
4571 if (pinfo2 & INSN2_READ_SP)
4573 if (pinfo2 & INSN2_READ_GPR_31)
4575 /* Don't include register 0. */
4579 /* Return the mask of core registers that IP writes. */
4582 gpr_write_mask (const struct mips_cl_insn *ip)
4584 unsigned long pinfo, pinfo2;
4587 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_write_mask (ip->insn_mo));
4588 pinfo = ip->insn_mo->pinfo;
4589 pinfo2 = ip->insn_mo->pinfo2;
4590 if (pinfo & INSN_WRITE_GPR_24)
4592 if (pinfo & INSN_WRITE_GPR_31)
4594 if (pinfo & INSN_UDI)
4595 /* UDI instructions have traditionally been assumed to write to RD. */
4596 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
4597 if (pinfo2 & INSN2_WRITE_SP)
4599 /* Don't include register 0. */
4603 /* Return the mask of floating-point registers that IP reads. */
4606 fpr_read_mask (const struct mips_cl_insn *ip)
4608 unsigned long pinfo;
4611 mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC)
4612 | (1 << OP_REG_MSA)),
4613 insn_read_mask (ip->insn_mo));
4614 pinfo = ip->insn_mo->pinfo;
4615 /* Conservatively treat all operands to an FP_D instruction are doubles.
4616 (This is overly pessimistic for things like cvt.d.s.) */
4617 if (FPR_SIZE != 64 && (pinfo & FP_D))
4622 /* Return the mask of floating-point registers that IP writes. */
4625 fpr_write_mask (const struct mips_cl_insn *ip)
4627 unsigned long pinfo;
4630 mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC)
4631 | (1 << OP_REG_MSA)),
4632 insn_write_mask (ip->insn_mo));
4633 pinfo = ip->insn_mo->pinfo;
4634 /* Conservatively treat all operands to an FP_D instruction are doubles.
4635 (This is overly pessimistic for things like cvt.s.d.) */
4636 if (FPR_SIZE != 64 && (pinfo & FP_D))
4641 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4642 Check whether that is allowed. */
4645 mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum)
4647 const char *s = insn->name;
4648 bfd_boolean oddspreg = (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa, mips_opts.arch)
4650 && mips_opts.oddspreg;
4652 if (insn->pinfo == INSN_MACRO)
4653 /* Let a macro pass, we'll catch it later when it is expanded. */
4656 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4657 otherwise it depends on oddspreg. */
4658 if ((insn->pinfo & FP_S)
4659 && (insn->pinfo & (INSN_LOAD_MEMORY | INSN_STORE_MEMORY
4660 | INSN_LOAD_COPROC | INSN_COPROC_MOVE)))
4661 return FPR_SIZE == 32 || oddspreg;
4663 /* Allow odd registers for single-precision ops and double-precision if the
4664 floating-point registers are 64-bit wide. */
4665 switch (insn->pinfo & (FP_S | FP_D))
4671 return FPR_SIZE == 64;
4676 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4677 s = strchr (insn->name, '.');
4678 if (s != NULL && opnum == 2)
4679 s = strchr (s + 1, '.');
4680 if (s != NULL && (s[1] == 'w' || s[1] == 's'))
4683 return FPR_SIZE == 64;
4686 /* Information about an instruction argument that we're trying to match. */
4687 struct mips_arg_info
4689 /* The instruction so far. */
4690 struct mips_cl_insn *insn;
4692 /* The first unconsumed operand token. */
4693 struct mips_operand_token *token;
4695 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4698 /* The 1-based argument number, for error reporting. This does not
4699 count elided optional registers, etc.. */
4702 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4703 unsigned int last_regno;
4705 /* If the first operand was an OP_REG, this is the register that it
4706 specified, otherwise it is ILLEGAL_REG. */
4707 unsigned int dest_regno;
4709 /* The value of the last OP_INT operand. Only used for OP_MSB,
4710 where it gives the lsb position. */
4711 unsigned int last_op_int;
4713 /* If true, match routines should assume that no later instruction
4714 alternative matches and should therefore be as accommodating as
4715 possible. Match routines should not report errors if something
4716 is only invalid for !LAX_MATCH. */
4717 bfd_boolean lax_match;
4719 /* True if a reference to the current AT register was seen. */
4720 bfd_boolean seen_at;
4723 /* Record that the argument is out of range. */
4726 match_out_of_range (struct mips_arg_info *arg)
4728 set_insn_error_i (arg->argnum, _("operand %d out of range"), arg->argnum);
4731 /* Record that the argument isn't constant but needs to be. */
4734 match_not_constant (struct mips_arg_info *arg)
4736 set_insn_error_i (arg->argnum, _("operand %d must be constant"),
4740 /* Try to match an OT_CHAR token for character CH. Consume the token
4741 and return true on success, otherwise return false. */
4744 match_char (struct mips_arg_info *arg, char ch)
4746 if (arg->token->type == OT_CHAR && arg->token->u.ch == ch)
4756 /* Try to get an expression from the next tokens in ARG. Consume the
4757 tokens and return true on success, storing the expression value in
4758 VALUE and relocation types in R. */
4761 match_expression (struct mips_arg_info *arg, expressionS *value,
4762 bfd_reloc_code_real_type *r)
4764 /* If the next token is a '(' that was parsed as being part of a base
4765 expression, assume we have an elided offset. The later match will fail
4766 if this turns out to be wrong. */
4767 if (arg->token->type == OT_CHAR && arg->token->u.ch == '(')
4769 value->X_op = O_constant;
4770 value->X_add_number = 0;
4771 r[0] = r[1] = r[2] = BFD_RELOC_UNUSED;
4775 /* Reject register-based expressions such as "0+$2" and "(($2))".
4776 For plain registers the default error seems more appropriate. */
4777 if (arg->token->type == OT_INTEGER
4778 && arg->token->u.integer.value.X_op == O_register)
4780 set_insn_error (arg->argnum, _("register value used as expression"));
4784 if (arg->token->type == OT_INTEGER)
4786 *value = arg->token->u.integer.value;
4787 memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r));
4793 (arg->argnum, _("operand %d must be an immediate expression"),
4798 /* Try to get a constant expression from the next tokens in ARG. Consume
4799 the tokens and return return true on success, storing the constant value
4800 in *VALUE. Use FALLBACK as the value if the match succeeded with an
4804 match_const_int (struct mips_arg_info *arg, offsetT *value)
4807 bfd_reloc_code_real_type r[3];
4809 if (!match_expression (arg, &ex, r))
4812 if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant)
4813 *value = ex.X_add_number;
4816 match_not_constant (arg);
4822 /* Return the RTYPE_* flags for a register operand of type TYPE that
4823 appears in instruction OPCODE. */
4826 convert_reg_type (const struct mips_opcode *opcode,
4827 enum mips_reg_operand_type type)
4832 return RTYPE_NUM | RTYPE_GP;
4835 /* Allow vector register names for MDMX if the instruction is a 64-bit
4836 FPR load, store or move (including moves to and from GPRs). */
4837 if ((mips_opts.ase & ASE_MDMX)
4838 && (opcode->pinfo & FP_D)
4839 && (opcode->pinfo & (INSN_COPROC_MOVE
4840 | INSN_COPROC_MEMORY_DELAY
4843 | INSN_STORE_MEMORY)))
4844 return RTYPE_FPU | RTYPE_VEC;
4848 if (opcode->pinfo & (FP_D | FP_S))
4849 return RTYPE_CCC | RTYPE_FCC;
4853 if (opcode->membership & INSN_5400)
4855 return RTYPE_FPU | RTYPE_VEC;
4861 if (opcode->name[strlen (opcode->name) - 1] == '0')
4862 return RTYPE_NUM | RTYPE_CP0;
4869 return RTYPE_NUM | RTYPE_VI;
4872 return RTYPE_NUM | RTYPE_VF;
4874 case OP_REG_R5900_I:
4875 return RTYPE_R5900_I;
4877 case OP_REG_R5900_Q:
4878 return RTYPE_R5900_Q;
4880 case OP_REG_R5900_R:
4881 return RTYPE_R5900_R;
4883 case OP_REG_R5900_ACC:
4884 return RTYPE_R5900_ACC;
4889 case OP_REG_MSA_CTRL:
4895 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4898 check_regno (struct mips_arg_info *arg,
4899 enum mips_reg_operand_type type, unsigned int regno)
4901 if (AT && type == OP_REG_GP && regno == AT)
4902 arg->seen_at = TRUE;
4904 if (type == OP_REG_FP
4906 && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum))
4908 /* This was a warning prior to introducing O32 FPXX and FP64 support
4909 so maintain a warning for FP32 but raise an error for the new
4912 as_warn (_("float register should be even, was %d"), regno);
4914 as_bad (_("float register should be even, was %d"), regno);
4917 if (type == OP_REG_CCC)
4922 name = arg->insn->insn_mo->name;
4923 length = strlen (name);
4924 if ((regno & 1) != 0
4925 && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0)
4926 || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0)))
4927 as_warn (_("condition code register should be even for %s, was %d"),
4930 if ((regno & 3) != 0
4931 && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0))
4932 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
4937 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
4938 a register of type TYPE. Return true on success, storing the register
4939 number in *REGNO and warning about any dubious uses. */
4942 match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4943 unsigned int symval, unsigned int *regno)
4945 if (type == OP_REG_VEC)
4946 symval = mips_prefer_vec_regno (symval);
4947 if (!(symval & convert_reg_type (arg->insn->insn_mo, type)))
4950 *regno = symval & RNUM_MASK;
4951 check_regno (arg, type, *regno);
4955 /* Try to interpret the next token in ARG as a register of type TYPE.
4956 Consume the token and return true on success, storing the register
4957 number in *REGNO. Return false on failure. */
4960 match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4961 unsigned int *regno)
4963 if (arg->token->type == OT_REG
4964 && match_regno (arg, type, arg->token->u.regno, regno))
4972 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
4973 Consume the token and return true on success, storing the register numbers
4974 in *REGNO1 and *REGNO2. Return false on failure. */
4977 match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4978 unsigned int *regno1, unsigned int *regno2)
4980 if (match_reg (arg, type, regno1))
4985 if (arg->token->type == OT_REG_RANGE
4986 && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1)
4987 && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2)
4988 && *regno1 <= *regno2)
4996 /* OP_INT matcher. */
4999 match_int_operand (struct mips_arg_info *arg,
5000 const struct mips_operand *operand_base)
5002 const struct mips_int_operand *operand;
5004 int min_val, max_val, factor;
5007 operand = (const struct mips_int_operand *) operand_base;
5008 factor = 1 << operand->shift;
5009 min_val = mips_int_operand_min (operand);
5010 max_val = mips_int_operand_max (operand);
5012 if (operand_base->lsb == 0
5013 && operand_base->size == 16
5014 && operand->shift == 0
5015 && operand->bias == 0
5016 && (operand->max_val == 32767 || operand->max_val == 65535))
5018 /* The operand can be relocated. */
5019 if (!match_expression (arg, &offset_expr, offset_reloc))
5022 if (offset_reloc[0] != BFD_RELOC_UNUSED)
5023 /* Relocation operators were used. Accept the arguent and
5024 leave the relocation value in offset_expr and offset_relocs
5025 for the caller to process. */
5028 if (offset_expr.X_op != O_constant)
5030 /* Accept non-constant operands if no later alternative matches,
5031 leaving it for the caller to process. */
5032 if (!arg->lax_match)
5034 offset_reloc[0] = BFD_RELOC_LO16;
5038 /* Clear the global state; we're going to install the operand
5040 sval = offset_expr.X_add_number;
5041 offset_expr.X_op = O_absent;
5043 /* For compatibility with older assemblers, we accept
5044 0x8000-0xffff as signed 16-bit numbers when only
5045 signed numbers are allowed. */
5048 max_val = ((1 << operand_base->size) - 1) << operand->shift;
5049 if (!arg->lax_match && sval <= max_val)
5055 if (!match_const_int (arg, &sval))
5059 arg->last_op_int = sval;
5061 if (sval < min_val || sval > max_val || sval % factor)
5063 match_out_of_range (arg);
5067 uval = (unsigned int) sval >> operand->shift;
5068 uval -= operand->bias;
5070 /* Handle -mfix-cn63xxp1. */
5072 && mips_fix_cn63xxp1
5073 && !mips_opts.micromips
5074 && strcmp ("pref", arg->insn->insn_mo->name) == 0)
5089 /* The rest must be changed to 28. */
5094 insn_insert_operand (arg->insn, operand_base, uval);
5098 /* OP_MAPPED_INT matcher. */
5101 match_mapped_int_operand (struct mips_arg_info *arg,
5102 const struct mips_operand *operand_base)
5104 const struct mips_mapped_int_operand *operand;
5105 unsigned int uval, num_vals;
5108 operand = (const struct mips_mapped_int_operand *) operand_base;
5109 if (!match_const_int (arg, &sval))
5112 num_vals = 1 << operand_base->size;
5113 for (uval = 0; uval < num_vals; uval++)
5114 if (operand->int_map[uval] == sval)
5116 if (uval == num_vals)
5118 match_out_of_range (arg);
5122 insn_insert_operand (arg->insn, operand_base, uval);
5126 /* OP_MSB matcher. */
5129 match_msb_operand (struct mips_arg_info *arg,
5130 const struct mips_operand *operand_base)
5132 const struct mips_msb_operand *operand;
5133 int min_val, max_val, max_high;
5134 offsetT size, sval, high;
5136 operand = (const struct mips_msb_operand *) operand_base;
5137 min_val = operand->bias;
5138 max_val = min_val + (1 << operand_base->size) - 1;
5139 max_high = operand->opsize;
5141 if (!match_const_int (arg, &size))
5144 high = size + arg->last_op_int;
5145 sval = operand->add_lsb ? high : size;
5147 if (size < 0 || high > max_high || sval < min_val || sval > max_val)
5149 match_out_of_range (arg);
5152 insn_insert_operand (arg->insn, operand_base, sval - min_val);
5156 /* OP_REG matcher. */
5159 match_reg_operand (struct mips_arg_info *arg,
5160 const struct mips_operand *operand_base)
5162 const struct mips_reg_operand *operand;
5163 unsigned int regno, uval, num_vals;
5165 operand = (const struct mips_reg_operand *) operand_base;
5166 if (!match_reg (arg, operand->reg_type, ®no))
5169 if (operand->reg_map)
5171 num_vals = 1 << operand->root.size;
5172 for (uval = 0; uval < num_vals; uval++)
5173 if (operand->reg_map[uval] == regno)
5175 if (num_vals == uval)
5181 arg->last_regno = regno;
5182 if (arg->opnum == 1)
5183 arg->dest_regno = regno;
5184 insn_insert_operand (arg->insn, operand_base, uval);
5188 /* OP_REG_PAIR matcher. */
5191 match_reg_pair_operand (struct mips_arg_info *arg,
5192 const struct mips_operand *operand_base)
5194 const struct mips_reg_pair_operand *operand;
5195 unsigned int regno1, regno2, uval, num_vals;
5197 operand = (const struct mips_reg_pair_operand *) operand_base;
5198 if (!match_reg (arg, operand->reg_type, ®no1)
5199 || !match_char (arg, ',')
5200 || !match_reg (arg, operand->reg_type, ®no2))
5203 num_vals = 1 << operand_base->size;
5204 for (uval = 0; uval < num_vals; uval++)
5205 if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2)
5207 if (uval == num_vals)
5210 insn_insert_operand (arg->insn, operand_base, uval);
5214 /* OP_PCREL matcher. The caller chooses the relocation type. */
5217 match_pcrel_operand (struct mips_arg_info *arg)
5219 bfd_reloc_code_real_type r[3];
5221 return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED;
5224 /* OP_PERF_REG matcher. */
5227 match_perf_reg_operand (struct mips_arg_info *arg,
5228 const struct mips_operand *operand)
5232 if (!match_const_int (arg, &sval))
5237 || (mips_opts.arch == CPU_R5900
5238 && (strcmp (arg->insn->insn_mo->name, "mfps") == 0
5239 || strcmp (arg->insn->insn_mo->name, "mtps") == 0))))
5241 set_insn_error (arg->argnum, _("invalid performance register"));
5245 insn_insert_operand (arg->insn, operand, sval);
5249 /* OP_ADDIUSP matcher. */
5252 match_addiusp_operand (struct mips_arg_info *arg,
5253 const struct mips_operand *operand)
5258 if (!match_const_int (arg, &sval))
5263 match_out_of_range (arg);
5268 if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1))
5270 match_out_of_range (arg);
5274 uval = (unsigned int) sval;
5275 uval = ((uval >> 1) & ~0xff) | (uval & 0xff);
5276 insn_insert_operand (arg->insn, operand, uval);
5280 /* OP_CLO_CLZ_DEST matcher. */
5283 match_clo_clz_dest_operand (struct mips_arg_info *arg,
5284 const struct mips_operand *operand)
5288 if (!match_reg (arg, OP_REG_GP, ®no))
5291 insn_insert_operand (arg->insn, operand, regno | (regno << 5));
5295 /* OP_CHECK_PREV matcher. */
5298 match_check_prev_operand (struct mips_arg_info *arg,
5299 const struct mips_operand *operand_base)
5301 const struct mips_check_prev_operand *operand;
5304 operand = (const struct mips_check_prev_operand *) operand_base;
5306 if (!match_reg (arg, OP_REG_GP, ®no))
5309 if (!operand->zero_ok && regno == 0)
5312 if ((operand->less_than_ok && regno < arg->last_regno)
5313 || (operand->greater_than_ok && regno > arg->last_regno)
5314 || (operand->equal_ok && regno == arg->last_regno))
5316 arg->last_regno = regno;
5317 insn_insert_operand (arg->insn, operand_base, regno);
5324 /* OP_SAME_RS_RT matcher. */
5327 match_same_rs_rt_operand (struct mips_arg_info *arg,
5328 const struct mips_operand *operand)
5332 if (!match_reg (arg, OP_REG_GP, ®no))
5337 set_insn_error (arg->argnum, _("the source register must not be $0"));
5341 arg->last_regno = regno;
5343 insn_insert_operand (arg->insn, operand, regno | (regno << 5));
5347 /* OP_LWM_SWM_LIST matcher. */
5350 match_lwm_swm_list_operand (struct mips_arg_info *arg,
5351 const struct mips_operand *operand)
5353 unsigned int reglist, sregs, ra, regno1, regno2;
5354 struct mips_arg_info reset;
5357 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
5361 if (regno2 == FP && regno1 >= S0 && regno1 <= S7)
5366 reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1);
5369 while (match_char (arg, ',')
5370 && match_reg_range (arg, OP_REG_GP, ®no1, ®no2));
5373 if (operand->size == 2)
5375 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5381 and any permutations of these. */
5382 if ((reglist & 0xfff1ffff) != 0x80010000)
5385 sregs = (reglist >> 17) & 7;
5390 /* The list must include at least one of ra and s0-sN,
5391 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5392 which are $23 and $30 respectively.) E.g.:
5400 and any permutations of these. */
5401 if ((reglist & 0x3f00ffff) != 0)
5404 ra = (reglist >> 27) & 0x10;
5405 sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
5408 if ((sregs & -sregs) != sregs)
5411 insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra);
5415 /* OP_ENTRY_EXIT_LIST matcher. */
5418 match_entry_exit_operand (struct mips_arg_info *arg,
5419 const struct mips_operand *operand)
5422 bfd_boolean is_exit;
5424 /* The format is the same for both ENTRY and EXIT, but the constraints
5426 is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0;
5427 mask = (is_exit ? 7 << 3 : 0);
5430 unsigned int regno1, regno2;
5431 bfd_boolean is_freg;
5433 if (match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
5435 else if (match_reg_range (arg, OP_REG_FP, ®no1, ®no2))
5440 if (is_exit && is_freg && regno1 == 0 && regno2 < 2)
5443 mask |= (5 + regno2) << 3;
5445 else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7)
5446 mask |= (regno2 - 3) << 3;
5447 else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17)
5448 mask |= (regno2 - 15) << 1;
5449 else if (regno1 == RA && regno2 == RA)
5454 while (match_char (arg, ','));
5456 insn_insert_operand (arg->insn, operand, mask);
5460 /* OP_SAVE_RESTORE_LIST matcher. */
5463 match_save_restore_list_operand (struct mips_arg_info *arg)
5465 unsigned int opcode, args, statics, sregs;
5466 unsigned int num_frame_sizes, num_args, num_statics, num_sregs;
5469 opcode = arg->insn->insn_opcode;
5471 num_frame_sizes = 0;
5477 unsigned int regno1, regno2;
5479 if (arg->token->type == OT_INTEGER)
5481 /* Handle the frame size. */
5482 if (!match_const_int (arg, &frame_size))
5484 num_frame_sizes += 1;
5488 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
5491 while (regno1 <= regno2)
5493 if (regno1 >= 4 && regno1 <= 7)
5495 if (num_frame_sizes == 0)
5497 args |= 1 << (regno1 - 4);
5499 /* statics $a0-$a3 */
5500 statics |= 1 << (regno1 - 4);
5502 else if (regno1 >= 16 && regno1 <= 23)
5504 sregs |= 1 << (regno1 - 16);
5505 else if (regno1 == 30)
5508 else if (regno1 == 31)
5509 /* Add $ra to insn. */
5519 while (match_char (arg, ','));
5521 /* Encode args/statics combination. */
5524 else if (args == 0xf)
5525 /* All $a0-$a3 are args. */
5526 opcode |= MIPS16_ALL_ARGS << 16;
5527 else if (statics == 0xf)
5528 /* All $a0-$a3 are statics. */
5529 opcode |= MIPS16_ALL_STATICS << 16;
5532 /* Count arg registers. */
5542 /* Count static registers. */
5544 while (statics & 0x8)
5546 statics = (statics << 1) & 0xf;
5552 /* Encode args/statics. */
5553 opcode |= ((num_args << 2) | num_statics) << 16;
5556 /* Encode $s0/$s1. */
5557 if (sregs & (1 << 0)) /* $s0 */
5559 if (sregs & (1 << 1)) /* $s1 */
5563 /* Encode $s2-$s8. */
5572 opcode |= num_sregs << 24;
5574 /* Encode frame size. */
5575 if (num_frame_sizes == 0)
5577 set_insn_error (arg->argnum, _("missing frame size"));
5580 if (num_frame_sizes > 1)
5582 set_insn_error (arg->argnum, _("frame size specified twice"));
5585 if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8)
5587 set_insn_error (arg->argnum, _("invalid frame size"));
5590 if (frame_size != 128 || (opcode >> 16) != 0)
5593 opcode |= (((frame_size & 0xf0) << 16)
5594 | (frame_size & 0x0f));
5597 /* Finally build the instruction. */
5598 if ((opcode >> 16) != 0 || frame_size == 0)
5599 opcode |= MIPS16_EXTEND;
5600 arg->insn->insn_opcode = opcode;
5604 /* OP_MDMX_IMM_REG matcher. */
5607 match_mdmx_imm_reg_operand (struct mips_arg_info *arg,
5608 const struct mips_operand *operand)
5610 unsigned int regno, uval;
5612 const struct mips_opcode *opcode;
5614 /* The mips_opcode records whether this is an octobyte or quadhalf
5615 instruction. Start out with that bit in place. */
5616 opcode = arg->insn->insn_mo;
5617 uval = mips_extract_operand (operand, opcode->match);
5618 is_qh = (uval != 0);
5620 if (arg->token->type == OT_REG)
5622 if ((opcode->membership & INSN_5400)
5623 && strcmp (opcode->name, "rzu.ob") == 0)
5625 set_insn_error_i (arg->argnum, _("operand %d must be an immediate"),
5630 if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no))
5634 /* Check whether this is a vector register or a broadcast of
5635 a single element. */
5636 if (arg->token->type == OT_INTEGER_INDEX)
5638 if (arg->token->u.index > (is_qh ? 3 : 7))
5640 set_insn_error (arg->argnum, _("invalid element selector"));
5643 uval |= arg->token->u.index << (is_qh ? 2 : 1) << 5;
5648 /* A full vector. */
5649 if ((opcode->membership & INSN_5400)
5650 && (strcmp (opcode->name, "sll.ob") == 0
5651 || strcmp (opcode->name, "srl.ob") == 0))
5653 set_insn_error_i (arg->argnum, _("operand %d must be scalar"),
5659 uval |= MDMX_FMTSEL_VEC_QH << 5;
5661 uval |= MDMX_FMTSEL_VEC_OB << 5;
5669 if (!match_const_int (arg, &sval))
5671 if (sval < 0 || sval > 31)
5673 match_out_of_range (arg);
5676 uval |= (sval & 31);
5678 uval |= MDMX_FMTSEL_IMM_QH << 5;
5680 uval |= MDMX_FMTSEL_IMM_OB << 5;
5682 insn_insert_operand (arg->insn, operand, uval);
5686 /* OP_IMM_INDEX matcher. */
5689 match_imm_index_operand (struct mips_arg_info *arg,
5690 const struct mips_operand *operand)
5692 unsigned int max_val;
5694 if (arg->token->type != OT_INTEGER_INDEX)
5697 max_val = (1 << operand->size) - 1;
5698 if (arg->token->u.index > max_val)
5700 match_out_of_range (arg);
5703 insn_insert_operand (arg->insn, operand, arg->token->u.index);
5708 /* OP_REG_INDEX matcher. */
5711 match_reg_index_operand (struct mips_arg_info *arg,
5712 const struct mips_operand *operand)
5716 if (arg->token->type != OT_REG_INDEX)
5719 if (!match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no))
5722 insn_insert_operand (arg->insn, operand, regno);
5727 /* OP_PC matcher. */
5730 match_pc_operand (struct mips_arg_info *arg)
5732 if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC))
5740 /* OP_NON_ZERO_REG matcher. */
5743 match_non_zero_reg_operand (struct mips_arg_info *arg,
5744 const struct mips_operand *operand)
5748 if (!match_reg (arg, OP_REG_GP, ®no))
5754 arg->last_regno = regno;
5755 insn_insert_operand (arg->insn, operand, regno);
5759 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5760 register that we need to match. */
5763 match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno)
5767 return match_reg (arg, OP_REG_GP, ®no) && regno == other_regno;
5770 /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
5771 the length of the value in bytes (4 for float, 8 for double) and
5772 USING_GPRS says whether the destination is a GPR rather than an FPR.
5774 Return the constant in IMM and OFFSET as follows:
5776 - If the constant should be loaded via memory, set IMM to O_absent and
5777 OFFSET to the memory address.
5779 - Otherwise, if the constant should be loaded into two 32-bit registers,
5780 set IMM to the O_constant to load into the high register and OFFSET
5781 to the corresponding value for the low register.
5783 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5785 These constants only appear as the last operand in an instruction,
5786 and every instruction that accepts them in any variant accepts them
5787 in all variants. This means we don't have to worry about backing out
5788 any changes if the instruction does not match. We just match
5789 unconditionally and report an error if the constant is invalid. */
5792 match_float_constant (struct mips_arg_info *arg, expressionS *imm,
5793 expressionS *offset, int length, bfd_boolean using_gprs)
5798 const char *newname;
5799 unsigned char *data;
5801 /* Where the constant is placed is based on how the MIPS assembler
5804 length == 4 && using_gprs -- immediate value only
5805 length == 8 && using_gprs -- .rdata or immediate value
5806 length == 4 && !using_gprs -- .lit4 or immediate value
5807 length == 8 && !using_gprs -- .lit8 or immediate value
5809 The .lit4 and .lit8 sections are only used if permitted by the
5811 if (arg->token->type != OT_FLOAT)
5813 set_insn_error (arg->argnum, _("floating-point expression required"));
5817 gas_assert (arg->token->u.flt.length == length);
5818 data = arg->token->u.flt.data;
5821 /* Handle 32-bit constants for which an immediate value is best. */
5824 || g_switch_value < 4
5825 || (data[0] == 0 && data[1] == 0)
5826 || (data[2] == 0 && data[3] == 0)))
5828 imm->X_op = O_constant;
5829 if (!target_big_endian)
5830 imm->X_add_number = bfd_getl32 (data);
5832 imm->X_add_number = bfd_getb32 (data);
5833 offset->X_op = O_absent;
5837 /* Handle 64-bit constants for which an immediate value is best. */
5839 && !mips_disable_float_construction
5840 /* Constants can only be constructed in GPRs and copied to FPRs if the
5841 GPRs are at least as wide as the FPRs or MTHC1 is available.
5842 Unlike most tests for 32-bit floating-point registers this check
5843 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
5844 permit 64-bit moves without MXHC1.
5845 Force the constant into memory otherwise. */
5848 || ISA_HAS_MXHC1 (mips_opts.isa)
5850 && ((data[0] == 0 && data[1] == 0)
5851 || (data[2] == 0 && data[3] == 0))
5852 && ((data[4] == 0 && data[5] == 0)
5853 || (data[6] == 0 && data[7] == 0)))
5855 /* The value is simple enough to load with a couple of instructions.
5856 If using 32-bit registers, set IMM to the high order 32 bits and
5857 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
5859 if (GPR_SIZE == 32 || (!using_gprs && FPR_SIZE != 64))
5861 imm->X_op = O_constant;
5862 offset->X_op = O_constant;
5863 if (!target_big_endian)
5865 imm->X_add_number = bfd_getl32 (data + 4);
5866 offset->X_add_number = bfd_getl32 (data);
5870 imm->X_add_number = bfd_getb32 (data);
5871 offset->X_add_number = bfd_getb32 (data + 4);
5873 if (offset->X_add_number == 0)
5874 offset->X_op = O_absent;
5878 imm->X_op = O_constant;
5879 if (!target_big_endian)
5880 imm->X_add_number = bfd_getl64 (data);
5882 imm->X_add_number = bfd_getb64 (data);
5883 offset->X_op = O_absent;
5888 /* Switch to the right section. */
5890 subseg = now_subseg;
5893 gas_assert (!using_gprs && g_switch_value >= 4);
5898 if (using_gprs || g_switch_value < 8)
5899 newname = RDATA_SECTION_NAME;
5904 new_seg = subseg_new (newname, (subsegT) 0);
5905 bfd_set_section_flags (stdoutput, new_seg,
5906 SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA);
5907 frag_align (length == 4 ? 2 : 3, 0, 0);
5908 if (strncmp (TARGET_OS, "elf", 3) != 0)
5909 record_alignment (new_seg, 4);
5911 record_alignment (new_seg, length == 4 ? 2 : 3);
5913 as_bad (_("cannot use `%s' in this section"), arg->insn->insn_mo->name);
5915 /* Set the argument to the current address in the section. */
5916 imm->X_op = O_absent;
5917 offset->X_op = O_symbol;
5918 offset->X_add_symbol = symbol_temp_new_now ();
5919 offset->X_add_number = 0;
5921 /* Put the floating point number into the section. */
5922 p = frag_more (length);
5923 memcpy (p, data, length);
5925 /* Switch back to the original section. */
5926 subseg_set (seg, subseg);
5930 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
5934 match_vu0_suffix_operand (struct mips_arg_info *arg,
5935 const struct mips_operand *operand,
5936 bfd_boolean match_p)
5940 /* The operand can be an XYZW mask or a single 2-bit channel index
5941 (with X being 0). */
5942 gas_assert (operand->size == 2 || operand->size == 4);
5944 /* The suffix can be omitted when it is already part of the opcode. */
5945 if (arg->token->type != OT_CHANNELS)
5948 uval = arg->token->u.channels;
5949 if (operand->size == 2)
5951 /* Check that a single bit is set and convert it into a 2-bit index. */
5952 if ((uval & -uval) != uval)
5954 uval = 4 - ffs (uval);
5957 if (match_p && insn_extract_operand (arg->insn, operand) != uval)
5962 insn_insert_operand (arg->insn, operand, uval);
5966 /* S is the text seen for ARG. Match it against OPERAND. Return the end
5967 of the argument text if the match is successful, otherwise return null. */
5970 match_operand (struct mips_arg_info *arg,
5971 const struct mips_operand *operand)
5973 switch (operand->type)
5976 return match_int_operand (arg, operand);
5979 return match_mapped_int_operand (arg, operand);
5982 return match_msb_operand (arg, operand);
5985 case OP_OPTIONAL_REG:
5986 return match_reg_operand (arg, operand);
5989 return match_reg_pair_operand (arg, operand);
5992 return match_pcrel_operand (arg);
5995 return match_perf_reg_operand (arg, operand);
5997 case OP_ADDIUSP_INT:
5998 return match_addiusp_operand (arg, operand);
6000 case OP_CLO_CLZ_DEST:
6001 return match_clo_clz_dest_operand (arg, operand);
6003 case OP_LWM_SWM_LIST:
6004 return match_lwm_swm_list_operand (arg, operand);
6006 case OP_ENTRY_EXIT_LIST:
6007 return match_entry_exit_operand (arg, operand);
6009 case OP_SAVE_RESTORE_LIST:
6010 return match_save_restore_list_operand (arg);
6012 case OP_MDMX_IMM_REG:
6013 return match_mdmx_imm_reg_operand (arg, operand);
6015 case OP_REPEAT_DEST_REG:
6016 return match_tied_reg_operand (arg, arg->dest_regno);
6018 case OP_REPEAT_PREV_REG:
6019 return match_tied_reg_operand (arg, arg->last_regno);
6022 return match_pc_operand (arg);
6025 return match_vu0_suffix_operand (arg, operand, FALSE);
6027 case OP_VU0_MATCH_SUFFIX:
6028 return match_vu0_suffix_operand (arg, operand, TRUE);
6031 return match_imm_index_operand (arg, operand);
6034 return match_reg_index_operand (arg, operand);
6037 return match_same_rs_rt_operand (arg, operand);
6040 return match_check_prev_operand (arg, operand);
6042 case OP_NON_ZERO_REG:
6043 return match_non_zero_reg_operand (arg, operand);
6048 /* ARG is the state after successfully matching an instruction.
6049 Issue any queued-up warnings. */
6052 check_completed_insn (struct mips_arg_info *arg)
6057 as_warn (_("used $at without \".set noat\""));
6059 as_warn (_("used $%u with \".set at=$%u\""), AT, AT);
6063 /* Return true if modifying general-purpose register REG needs a delay. */
6066 reg_needs_delay (unsigned int reg)
6068 unsigned long prev_pinfo;
6070 prev_pinfo = history[0].insn_mo->pinfo;
6071 if (!mips_opts.noreorder
6072 && (((prev_pinfo & INSN_LOAD_MEMORY) && !gpr_interlocks)
6073 || ((prev_pinfo & INSN_LOAD_COPROC) && !cop_interlocks))
6074 && (gpr_write_mask (&history[0]) & (1 << reg)))
6080 /* Classify an instruction according to the FIX_VR4120_* enumeration.
6081 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6082 by VR4120 errata. */
6085 classify_vr4120_insn (const char *name)
6087 if (strncmp (name, "macc", 4) == 0)
6088 return FIX_VR4120_MACC;
6089 if (strncmp (name, "dmacc", 5) == 0)
6090 return FIX_VR4120_DMACC;
6091 if (strncmp (name, "mult", 4) == 0)
6092 return FIX_VR4120_MULT;
6093 if (strncmp (name, "dmult", 5) == 0)
6094 return FIX_VR4120_DMULT;
6095 if (strstr (name, "div"))
6096 return FIX_VR4120_DIV;
6097 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
6098 return FIX_VR4120_MTHILO;
6099 return NUM_FIX_VR4120_CLASSES;
6102 #define INSN_ERET 0x42000018
6103 #define INSN_DERET 0x4200001f
6104 #define INSN_DMULT 0x1c
6105 #define INSN_DMULTU 0x1d
6107 /* Return the number of instructions that must separate INSN1 and INSN2,
6108 where INSN1 is the earlier instruction. Return the worst-case value
6109 for any INSN2 if INSN2 is null. */
6112 insns_between (const struct mips_cl_insn *insn1,
6113 const struct mips_cl_insn *insn2)
6115 unsigned long pinfo1, pinfo2;
6118 /* If INFO2 is null, pessimistically assume that all flags are set for
6119 the second instruction. */
6120 pinfo1 = insn1->insn_mo->pinfo;
6121 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
6123 /* For most targets, write-after-read dependencies on the HI and LO
6124 registers must be separated by at least two instructions. */
6125 if (!hilo_interlocks)
6127 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
6129 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
6133 /* If we're working around r7000 errata, there must be two instructions
6134 between an mfhi or mflo and any instruction that uses the result. */
6135 if (mips_7000_hilo_fix
6136 && !mips_opts.micromips
6137 && MF_HILO_INSN (pinfo1)
6138 && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))))
6141 /* If we're working around 24K errata, one instruction is required
6142 if an ERET or DERET is followed by a branch instruction. */
6143 if (mips_fix_24k && !mips_opts.micromips)
6145 if (insn1->insn_opcode == INSN_ERET
6146 || insn1->insn_opcode == INSN_DERET)
6149 || insn2->insn_opcode == INSN_ERET
6150 || insn2->insn_opcode == INSN_DERET
6151 || delayed_branch_p (insn2))
6156 /* If we're working around PMC RM7000 errata, there must be three
6157 nops between a dmult and a load instruction. */
6158 if (mips_fix_rm7000 && !mips_opts.micromips)
6160 if ((insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULT
6161 || (insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULTU)
6163 if (pinfo2 & INSN_LOAD_MEMORY)
6168 /* If working around VR4120 errata, check for combinations that need
6169 a single intervening instruction. */
6170 if (mips_fix_vr4120 && !mips_opts.micromips)
6172 unsigned int class1, class2;
6174 class1 = classify_vr4120_insn (insn1->insn_mo->name);
6175 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
6179 class2 = classify_vr4120_insn (insn2->insn_mo->name);
6180 if (vr4120_conflicts[class1] & (1 << class2))
6185 if (!HAVE_CODE_COMPRESSION)
6187 /* Check for GPR or coprocessor load delays. All such delays
6188 are on the RT register. */
6189 /* Itbl support may require additional care here. */
6190 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY))
6191 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC)))
6193 if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))
6197 /* Check for generic coprocessor hazards.
6199 This case is not handled very well. There is no special
6200 knowledge of CP0 handling, and the coprocessors other than
6201 the floating point unit are not distinguished at all. */
6202 /* Itbl support may require additional care here. FIXME!
6203 Need to modify this to include knowledge about
6204 user specified delays! */
6205 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE))
6206 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
6208 /* Handle cases where INSN1 writes to a known general coprocessor
6209 register. There must be a one instruction delay before INSN2
6210 if INSN2 reads that register, otherwise no delay is needed. */
6211 mask = fpr_write_mask (insn1);
6214 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
6219 /* Read-after-write dependencies on the control registers
6220 require a two-instruction gap. */
6221 if ((pinfo1 & INSN_WRITE_COND_CODE)
6222 && (pinfo2 & INSN_READ_COND_CODE))
6225 /* We don't know exactly what INSN1 does. If INSN2 is
6226 also a coprocessor instruction, assume there must be
6227 a one instruction gap. */
6228 if (pinfo2 & INSN_COP)
6233 /* Check for read-after-write dependencies on the coprocessor
6234 control registers in cases where INSN1 does not need a general
6235 coprocessor delay. This means that INSN1 is a floating point
6236 comparison instruction. */
6237 /* Itbl support may require additional care here. */
6238 else if (!cop_interlocks
6239 && (pinfo1 & INSN_WRITE_COND_CODE)
6240 && (pinfo2 & INSN_READ_COND_CODE))
6244 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6245 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6247 if ((insn1->insn_mo->pinfo2 & INSN2_FORBIDDEN_SLOT)
6248 && ((pinfo2 & INSN_NO_DELAY_SLOT)
6249 || (insn2 && delayed_branch_p (insn2))))
6255 /* Return the number of nops that would be needed to work around the
6256 VR4130 mflo/mfhi errata if instruction INSN immediately followed
6257 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6258 that are contained within the first IGNORE instructions of HIST. */
6261 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
6262 const struct mips_cl_insn *insn)
6267 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6268 are not affected by the errata. */
6270 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
6271 || strcmp (insn->insn_mo->name, "mtlo") == 0
6272 || strcmp (insn->insn_mo->name, "mthi") == 0))
6275 /* Search for the first MFLO or MFHI. */
6276 for (i = 0; i < MAX_VR4130_NOPS; i++)
6277 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
6279 /* Extract the destination register. */
6280 mask = gpr_write_mask (&hist[i]);
6282 /* No nops are needed if INSN reads that register. */
6283 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
6286 /* ...or if any of the intervening instructions do. */
6287 for (j = 0; j < i; j++)
6288 if (gpr_read_mask (&hist[j]) & mask)
6292 return MAX_VR4130_NOPS - i;
6297 #define BASE_REG_EQ(INSN1, INSN2) \
6298 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
6299 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6301 /* Return the minimum alignment for this store instruction. */
6304 fix_24k_align_to (const struct mips_opcode *mo)
6306 if (strcmp (mo->name, "sh") == 0)
6309 if (strcmp (mo->name, "swc1") == 0
6310 || strcmp (mo->name, "swc2") == 0
6311 || strcmp (mo->name, "sw") == 0
6312 || strcmp (mo->name, "sc") == 0
6313 || strcmp (mo->name, "s.s") == 0)
6316 if (strcmp (mo->name, "sdc1") == 0
6317 || strcmp (mo->name, "sdc2") == 0
6318 || strcmp (mo->name, "s.d") == 0)
6325 struct fix_24k_store_info
6327 /* Immediate offset, if any, for this store instruction. */
6329 /* Alignment required by this store instruction. */
6331 /* True for register offsets. */
6332 int register_offset;
6335 /* Comparison function used by qsort. */
6338 fix_24k_sort (const void *a, const void *b)
6340 const struct fix_24k_store_info *pos1 = a;
6341 const struct fix_24k_store_info *pos2 = b;
6343 return (pos1->off - pos2->off);
6346 /* INSN is a store instruction. Try to record the store information
6347 in STINFO. Return false if the information isn't known. */
6350 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
6351 const struct mips_cl_insn *insn)
6353 /* The instruction must have a known offset. */
6354 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
6357 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
6358 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
6362 /* Return the number of nops that would be needed to work around the 24k
6363 "lost data on stores during refill" errata if instruction INSN
6364 immediately followed the 2 instructions described by HIST.
6365 Ignore hazards that are contained within the first IGNORE
6366 instructions of HIST.
6368 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6369 for the data cache refills and store data. The following describes
6370 the scenario where the store data could be lost.
6372 * A data cache miss, due to either a load or a store, causing fill
6373 data to be supplied by the memory subsystem
6374 * The first three doublewords of fill data are returned and written
6376 * A sequence of four stores occurs in consecutive cycles around the
6377 final doubleword of the fill:
6381 * Zero, One or more instructions
6384 The four stores A-D must be to different doublewords of the line that
6385 is being filled. The fourth instruction in the sequence above permits
6386 the fill of the final doubleword to be transferred from the FSB into
6387 the cache. In the sequence above, the stores may be either integer
6388 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6389 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6390 different doublewords on the line. If the floating point unit is
6391 running in 1:2 mode, it is not possible to create the sequence above
6392 using only floating point store instructions.
6394 In this case, the cache line being filled is incorrectly marked
6395 invalid, thereby losing the data from any store to the line that
6396 occurs between the original miss and the completion of the five
6397 cycle sequence shown above.
6399 The workarounds are:
6401 * Run the data cache in write-through mode.
6402 * Insert a non-store instruction between
6403 Store A and Store B or Store B and Store C. */
6406 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
6407 const struct mips_cl_insn *insn)
6409 struct fix_24k_store_info pos[3];
6410 int align, i, base_offset;
6415 /* If the previous instruction wasn't a store, there's nothing to
6417 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
6420 /* If the instructions after the previous one are unknown, we have
6421 to assume the worst. */
6425 /* Check whether we are dealing with three consecutive stores. */
6426 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
6427 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
6430 /* If we don't know the relationship between the store addresses,
6431 assume the worst. */
6432 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
6433 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
6436 if (!fix_24k_record_store_info (&pos[0], insn)
6437 || !fix_24k_record_store_info (&pos[1], &hist[0])
6438 || !fix_24k_record_store_info (&pos[2], &hist[1]))
6441 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
6443 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6444 X bytes and such that the base register + X is known to be aligned
6447 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
6451 align = pos[0].align_to;
6452 base_offset = pos[0].off;
6453 for (i = 1; i < 3; i++)
6454 if (align < pos[i].align_to)
6456 align = pos[i].align_to;
6457 base_offset = pos[i].off;
6459 for (i = 0; i < 3; i++)
6460 pos[i].off -= base_offset;
6463 pos[0].off &= ~align + 1;
6464 pos[1].off &= ~align + 1;
6465 pos[2].off &= ~align + 1;
6467 /* If any two stores write to the same chunk, they also write to the
6468 same doubleword. The offsets are still sorted at this point. */
6469 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
6472 /* A range of at least 9 bytes is needed for the stores to be in
6473 non-overlapping doublewords. */
6474 if (pos[2].off - pos[0].off <= 8)
6477 if (pos[2].off - pos[1].off >= 24
6478 || pos[1].off - pos[0].off >= 24
6479 || pos[2].off - pos[0].off >= 32)
6485 /* Return the number of nops that would be needed if instruction INSN
6486 immediately followed the MAX_NOPS instructions given by HIST,
6487 where HIST[0] is the most recent instruction. Ignore hazards
6488 between INSN and the first IGNORE instructions in HIST.
6490 If INSN is null, return the worse-case number of nops for any
6494 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
6495 const struct mips_cl_insn *insn)
6497 int i, nops, tmp_nops;
6500 for (i = ignore; i < MAX_DELAY_NOPS; i++)
6502 tmp_nops = insns_between (hist + i, insn) - i;
6503 if (tmp_nops > nops)
6507 if (mips_fix_vr4130 && !mips_opts.micromips)
6509 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
6510 if (tmp_nops > nops)
6514 if (mips_fix_24k && !mips_opts.micromips)
6516 tmp_nops = nops_for_24k (ignore, hist, insn);
6517 if (tmp_nops > nops)
6524 /* The variable arguments provide NUM_INSNS extra instructions that
6525 might be added to HIST. Return the largest number of nops that
6526 would be needed after the extended sequence, ignoring hazards
6527 in the first IGNORE instructions. */
6530 nops_for_sequence (int num_insns, int ignore,
6531 const struct mips_cl_insn *hist, ...)
6534 struct mips_cl_insn buffer[MAX_NOPS];
6535 struct mips_cl_insn *cursor;
6538 va_start (args, hist);
6539 cursor = buffer + num_insns;
6540 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
6541 while (cursor > buffer)
6542 *--cursor = *va_arg (args, const struct mips_cl_insn *);
6544 nops = nops_for_insn (ignore, buffer, NULL);
6549 /* Like nops_for_insn, but if INSN is a branch, take into account the
6550 worst-case delay for the branch target. */
6553 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
6554 const struct mips_cl_insn *insn)
6558 nops = nops_for_insn (ignore, hist, insn);
6559 if (delayed_branch_p (insn))
6561 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
6562 hist, insn, get_delay_slot_nop (insn));
6563 if (tmp_nops > nops)
6566 else if (compact_branch_p (insn))
6568 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
6569 if (tmp_nops > nops)
6575 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6578 fix_loongson2f_nop (struct mips_cl_insn * ip)
6580 gas_assert (!HAVE_CODE_COMPRESSION);
6581 if (strcmp (ip->insn_mo->name, "nop") == 0)
6582 ip->insn_opcode = LOONGSON2F_NOP_INSN;
6585 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6586 jr target pc &= 'hffff_ffff_cfff_ffff. */
6589 fix_loongson2f_jump (struct mips_cl_insn * ip)
6591 gas_assert (!HAVE_CODE_COMPRESSION);
6592 if (strcmp (ip->insn_mo->name, "j") == 0
6593 || strcmp (ip->insn_mo->name, "jr") == 0
6594 || strcmp (ip->insn_mo->name, "jalr") == 0)
6602 sreg = EXTRACT_OPERAND (0, RS, *ip);
6603 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
6606 ep.X_op = O_constant;
6607 ep.X_add_number = 0xcfff0000;
6608 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
6609 ep.X_add_number = 0xffff;
6610 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
6611 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
6616 fix_loongson2f (struct mips_cl_insn * ip)
6618 if (mips_fix_loongson2f_nop)
6619 fix_loongson2f_nop (ip);
6621 if (mips_fix_loongson2f_jump)
6622 fix_loongson2f_jump (ip);
6625 /* IP is a branch that has a delay slot, and we need to fill it
6626 automatically. Return true if we can do that by swapping IP
6627 with the previous instruction.
6628 ADDRESS_EXPR is an operand of the instruction to be used with
6632 can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
6633 bfd_reloc_code_real_type *reloc_type)
6635 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
6636 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
6637 unsigned int fpr_read, prev_fpr_write;
6639 /* -O2 and above is required for this optimization. */
6640 if (mips_optimize < 2)
6643 /* If we have seen .set volatile or .set nomove, don't optimize. */
6644 if (mips_opts.nomove)
6647 /* We can't swap if the previous instruction's position is fixed. */
6648 if (history[0].fixed_p)
6651 /* If the previous previous insn was in a .set noreorder, we can't
6652 swap. Actually, the MIPS assembler will swap in this situation.
6653 However, gcc configured -with-gnu-as will generate code like
6661 in which we can not swap the bne and INSN. If gcc is not configured
6662 -with-gnu-as, it does not output the .set pseudo-ops. */
6663 if (history[1].noreorder_p)
6666 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6667 This means that the previous instruction was a 4-byte one anyhow. */
6668 if (mips_opts.mips16 && history[0].fixp[0])
6671 /* If the branch is itself the target of a branch, we can not swap.
6672 We cheat on this; all we check for is whether there is a label on
6673 this instruction. If there are any branches to anything other than
6674 a label, users must use .set noreorder. */
6675 if (seg_info (now_seg)->label_list)
6678 /* If the previous instruction is in a variant frag other than this
6679 branch's one, we cannot do the swap. This does not apply to
6680 MIPS16 code, which uses variant frags for different purposes. */
6681 if (!mips_opts.mips16
6683 && history[0].frag->fr_type == rs_machine_dependent)
6686 /* We do not swap with instructions that cannot architecturally
6687 be placed in a branch delay slot, such as SYNC or ERET. We
6688 also refrain from swapping with a trap instruction, since it
6689 complicates trap handlers to have the trap instruction be in
6691 prev_pinfo = history[0].insn_mo->pinfo;
6692 if (prev_pinfo & INSN_NO_DELAY_SLOT)
6695 /* Check for conflicts between the branch and the instructions
6696 before the candidate delay slot. */
6697 if (nops_for_insn (0, history + 1, ip) > 0)
6700 /* Check for conflicts between the swapped sequence and the
6701 target of the branch. */
6702 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
6705 /* If the branch reads a register that the previous
6706 instruction sets, we can not swap. */
6707 gpr_read = gpr_read_mask (ip);
6708 prev_gpr_write = gpr_write_mask (&history[0]);
6709 if (gpr_read & prev_gpr_write)
6712 fpr_read = fpr_read_mask (ip);
6713 prev_fpr_write = fpr_write_mask (&history[0]);
6714 if (fpr_read & prev_fpr_write)
6717 /* If the branch writes a register that the previous
6718 instruction sets, we can not swap. */
6719 gpr_write = gpr_write_mask (ip);
6720 if (gpr_write & prev_gpr_write)
6723 /* If the branch writes a register that the previous
6724 instruction reads, we can not swap. */
6725 prev_gpr_read = gpr_read_mask (&history[0]);
6726 if (gpr_write & prev_gpr_read)
6729 /* If one instruction sets a condition code and the
6730 other one uses a condition code, we can not swap. */
6731 pinfo = ip->insn_mo->pinfo;
6732 if ((pinfo & INSN_READ_COND_CODE)
6733 && (prev_pinfo & INSN_WRITE_COND_CODE))
6735 if ((pinfo & INSN_WRITE_COND_CODE)
6736 && (prev_pinfo & INSN_READ_COND_CODE))
6739 /* If the previous instruction uses the PC, we can not swap. */
6740 prev_pinfo2 = history[0].insn_mo->pinfo2;
6741 if (prev_pinfo2 & INSN2_READ_PC)
6744 /* If the previous instruction has an incorrect size for a fixed
6745 branch delay slot in microMIPS mode, we cannot swap. */
6746 pinfo2 = ip->insn_mo->pinfo2;
6747 if (mips_opts.micromips
6748 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
6749 && insn_length (history) != 2)
6751 if (mips_opts.micromips
6752 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
6753 && insn_length (history) != 4)
6756 /* On R5900 short loops need to be fixed by inserting a nop in
6757 the branch delay slots.
6758 A short loop can be terminated too early. */
6759 if (mips_opts.arch == CPU_R5900
6760 /* Check if instruction has a parameter, ignore "j $31". */
6761 && (address_expr != NULL)
6762 /* Parameter must be 16 bit. */
6763 && (*reloc_type == BFD_RELOC_16_PCREL_S2)
6764 /* Branch to same segment. */
6765 && (S_GET_SEGMENT (address_expr->X_add_symbol) == now_seg)
6766 /* Branch to same code fragment. */
6767 && (symbol_get_frag (address_expr->X_add_symbol) == frag_now)
6768 /* Can only calculate branch offset if value is known. */
6769 && symbol_constant_p (address_expr->X_add_symbol)
6770 /* Check if branch is really conditional. */
6771 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */
6772 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */
6773 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
6776 /* Check if loop is shorter than 6 instructions including
6777 branch and delay slot. */
6778 distance = frag_now_fix () - S_GET_VALUE (address_expr->X_add_symbol);
6785 /* When the loop includes branches or jumps,
6786 it is not a short loop. */
6787 for (i = 0; i < (distance / 4); i++)
6789 if ((history[i].cleared_p)
6790 || delayed_branch_p (&history[i]))
6798 /* Insert nop after branch to fix short loop. */
6807 /* Decide how we should add IP to the instruction stream.
6808 ADDRESS_EXPR is an operand of the instruction to be used with
6811 static enum append_method
6812 get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
6813 bfd_reloc_code_real_type *reloc_type)
6815 /* The relaxed version of a macro sequence must be inherently
6817 if (mips_relax.sequence == 2)
6820 /* We must not dabble with instructions in a ".set noreorder" block. */
6821 if (mips_opts.noreorder)
6824 /* Otherwise, it's our responsibility to fill branch delay slots. */
6825 if (delayed_branch_p (ip))
6827 if (!branch_likely_p (ip)
6828 && can_swap_branch_p (ip, address_expr, reloc_type))
6831 if (mips_opts.mips16
6832 && ISA_SUPPORTS_MIPS16E
6833 && gpr_read_mask (ip) != 0)
6834 return APPEND_ADD_COMPACT;
6836 if (mips_opts.micromips
6837 && ((ip->insn_opcode & 0xffe0) == 0x4580
6838 || (!forced_insn_length
6839 && ((ip->insn_opcode & 0xfc00) == 0xcc00
6840 || (ip->insn_opcode & 0xdc00) == 0x8c00))
6841 || (ip->insn_opcode & 0xdfe00000) == 0x94000000
6842 || (ip->insn_opcode & 0xdc1f0000) == 0x94000000))
6843 return APPEND_ADD_COMPACT;
6845 return APPEND_ADD_WITH_NOP;
6851 /* IP is an instruction whose opcode we have just changed, END points
6852 to the end of the opcode table processed. Point IP->insn_mo to the
6853 new opcode's definition. */
6856 find_altered_opcode (struct mips_cl_insn *ip, const struct mips_opcode *end)
6858 const struct mips_opcode *mo;
6860 for (mo = ip->insn_mo; mo < end; mo++)
6861 if (mo->pinfo != INSN_MACRO
6862 && (ip->insn_opcode & mo->mask) == mo->match)
6870 /* IP is a MIPS16 instruction whose opcode we have just changed.
6871 Point IP->insn_mo to the new opcode's definition. */
6874 find_altered_mips16_opcode (struct mips_cl_insn *ip)
6876 find_altered_opcode (ip, &mips16_opcodes[bfd_mips16_num_opcodes]);
6879 /* IP is a microMIPS instruction whose opcode we have just changed.
6880 Point IP->insn_mo to the new opcode's definition. */
6883 find_altered_micromips_opcode (struct mips_cl_insn *ip)
6885 find_altered_opcode (ip, µmips_opcodes[bfd_micromips_num_opcodes]);
6888 /* For microMIPS macros, we need to generate a local number label
6889 as the target of branches. */
6890 #define MICROMIPS_LABEL_CHAR '\037'
6891 static unsigned long micromips_target_label;
6892 static char micromips_target_name[32];
6895 micromips_label_name (void)
6897 char *p = micromips_target_name;
6898 char symbol_name_temporary[24];
6906 l = micromips_target_label;
6907 #ifdef LOCAL_LABEL_PREFIX
6908 *p++ = LOCAL_LABEL_PREFIX;
6911 *p++ = MICROMIPS_LABEL_CHAR;
6914 symbol_name_temporary[i++] = l % 10 + '0';
6919 *p++ = symbol_name_temporary[--i];
6922 return micromips_target_name;
6926 micromips_label_expr (expressionS *label_expr)
6928 label_expr->X_op = O_symbol;
6929 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
6930 label_expr->X_add_number = 0;
6934 micromips_label_inc (void)
6936 micromips_target_label++;
6937 *micromips_target_name = '\0';
6941 micromips_add_label (void)
6945 s = colon (micromips_label_name ());
6946 micromips_label_inc ();
6947 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
6950 /* If assembling microMIPS code, then return the microMIPS reloc
6951 corresponding to the requested one if any. Otherwise return
6952 the reloc unchanged. */
6954 static bfd_reloc_code_real_type
6955 micromips_map_reloc (bfd_reloc_code_real_type reloc)
6957 static const bfd_reloc_code_real_type relocs[][2] =
6959 /* Keep sorted incrementally by the left-hand key. */
6960 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
6961 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
6962 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
6963 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
6964 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
6965 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
6966 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
6967 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
6968 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
6969 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
6970 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
6971 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
6972 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
6973 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
6974 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
6975 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
6976 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
6977 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
6978 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
6979 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
6980 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
6981 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
6982 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
6983 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
6984 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
6985 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
6986 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
6988 bfd_reloc_code_real_type r;
6991 if (!mips_opts.micromips)
6993 for (i = 0; i < ARRAY_SIZE (relocs); i++)
6999 return relocs[i][1];
7004 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
7005 Return true on success, storing the resolved value in RESULT. */
7008 calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
7013 case BFD_RELOC_MIPS_HIGHEST:
7014 case BFD_RELOC_MICROMIPS_HIGHEST:
7015 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff;
7018 case BFD_RELOC_MIPS_HIGHER:
7019 case BFD_RELOC_MICROMIPS_HIGHER:
7020 *result = ((operand + 0x80008000ull) >> 32) & 0xffff;
7023 case BFD_RELOC_HI16_S:
7024 case BFD_RELOC_HI16_S_PCREL:
7025 case BFD_RELOC_MICROMIPS_HI16_S:
7026 case BFD_RELOC_MIPS16_HI16_S:
7027 *result = ((operand + 0x8000) >> 16) & 0xffff;
7030 case BFD_RELOC_HI16:
7031 case BFD_RELOC_MICROMIPS_HI16:
7032 case BFD_RELOC_MIPS16_HI16:
7033 *result = (operand >> 16) & 0xffff;
7036 case BFD_RELOC_LO16:
7037 case BFD_RELOC_LO16_PCREL:
7038 case BFD_RELOC_MICROMIPS_LO16:
7039 case BFD_RELOC_MIPS16_LO16:
7040 *result = operand & 0xffff;
7043 case BFD_RELOC_UNUSED:
7052 /* Output an instruction. IP is the instruction information.
7053 ADDRESS_EXPR is an operand of the instruction to be used with
7054 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
7055 a macro expansion. */
7058 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
7059 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
7061 unsigned long prev_pinfo2, pinfo;
7062 bfd_boolean relaxed_branch = FALSE;
7063 enum append_method method;
7064 bfd_boolean relax32;
7067 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
7068 fix_loongson2f (ip);
7070 file_ase_mips16 |= mips_opts.mips16;
7071 file_ase_micromips |= mips_opts.micromips;
7073 prev_pinfo2 = history[0].insn_mo->pinfo2;
7074 pinfo = ip->insn_mo->pinfo;
7076 /* Don't raise alarm about `nods' frags as they'll fill in the right
7077 kind of nop in relaxation if required. */
7078 if (mips_opts.micromips
7080 && !(history[0].frag
7081 && history[0].frag->fr_type == rs_machine_dependent
7082 && RELAX_MICROMIPS_P (history[0].frag->fr_subtype)
7083 && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype))
7084 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
7085 && micromips_insn_length (ip->insn_mo) != 2)
7086 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
7087 && micromips_insn_length (ip->insn_mo) != 4)))
7088 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
7089 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
7091 if (address_expr == NULL)
7093 else if (reloc_type[0] <= BFD_RELOC_UNUSED
7094 && reloc_type[1] == BFD_RELOC_UNUSED
7095 && reloc_type[2] == BFD_RELOC_UNUSED
7096 && address_expr->X_op == O_constant)
7098 switch (*reloc_type)
7100 case BFD_RELOC_MIPS_JMP:
7104 /* Shift is 2, unusually, for microMIPS JALX. */
7105 shift = (mips_opts.micromips
7106 && strcmp (ip->insn_mo->name, "jalx") != 0) ? 1 : 2;
7107 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7108 as_bad (_("jump to misaligned address (0x%lx)"),
7109 (unsigned long) address_expr->X_add_number);
7110 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7116 case BFD_RELOC_MIPS16_JMP:
7117 if ((address_expr->X_add_number & 3) != 0)
7118 as_bad (_("jump to misaligned address (0x%lx)"),
7119 (unsigned long) address_expr->X_add_number);
7121 (((address_expr->X_add_number & 0x7c0000) << 3)
7122 | ((address_expr->X_add_number & 0xf800000) >> 7)
7123 | ((address_expr->X_add_number & 0x3fffc) >> 2));
7127 case BFD_RELOC_16_PCREL_S2:
7131 shift = mips_opts.micromips ? 1 : 2;
7132 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7133 as_bad (_("branch to misaligned address (0x%lx)"),
7134 (unsigned long) address_expr->X_add_number);
7135 if (!mips_relax_branch)
7137 if ((address_expr->X_add_number + (1 << (shift + 15)))
7138 & ~((1 << (shift + 16)) - 1))
7139 as_bad (_("branch address range overflow (0x%lx)"),
7140 (unsigned long) address_expr->X_add_number);
7141 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7147 case BFD_RELOC_MIPS_21_PCREL_S2:
7152 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7153 as_bad (_("branch to misaligned address (0x%lx)"),
7154 (unsigned long) address_expr->X_add_number);
7155 if ((address_expr->X_add_number + (1 << (shift + 20)))
7156 & ~((1 << (shift + 21)) - 1))
7157 as_bad (_("branch address range overflow (0x%lx)"),
7158 (unsigned long) address_expr->X_add_number);
7159 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7164 case BFD_RELOC_MIPS_26_PCREL_S2:
7169 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7170 as_bad (_("branch to misaligned address (0x%lx)"),
7171 (unsigned long) address_expr->X_add_number);
7172 if ((address_expr->X_add_number + (1 << (shift + 25)))
7173 & ~((1 << (shift + 26)) - 1))
7174 as_bad (_("branch address range overflow (0x%lx)"),
7175 (unsigned long) address_expr->X_add_number);
7176 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7185 if (calculate_reloc (*reloc_type, address_expr->X_add_number,
7188 ip->insn_opcode |= value & 0xffff;
7196 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
7198 /* There are a lot of optimizations we could do that we don't.
7199 In particular, we do not, in general, reorder instructions.
7200 If you use gcc with optimization, it will reorder
7201 instructions and generally do much more optimization then we
7202 do here; repeating all that work in the assembler would only
7203 benefit hand written assembly code, and does not seem worth
7205 int nops = (mips_optimize == 0
7206 ? nops_for_insn (0, history, NULL)
7207 : nops_for_insn_or_target (0, history, ip));
7211 unsigned long old_frag_offset;
7214 old_frag = frag_now;
7215 old_frag_offset = frag_now_fix ();
7217 for (i = 0; i < nops; i++)
7218 add_fixed_insn (NOP_INSN);
7219 insert_into_history (0, nops, NOP_INSN);
7223 listing_prev_line ();
7224 /* We may be at the start of a variant frag. In case we
7225 are, make sure there is enough space for the frag
7226 after the frags created by listing_prev_line. The
7227 argument to frag_grow here must be at least as large
7228 as the argument to all other calls to frag_grow in
7229 this file. We don't have to worry about being in the
7230 middle of a variant frag, because the variants insert
7231 all needed nop instructions themselves. */
7235 mips_move_text_labels ();
7237 #ifndef NO_ECOFF_DEBUGGING
7238 if (ECOFF_DEBUGGING)
7239 ecoff_fix_loc (old_frag, old_frag_offset);
7243 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
7247 /* Work out how many nops in prev_nop_frag are needed by IP,
7248 ignoring hazards generated by the first prev_nop_frag_since
7250 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
7251 gas_assert (nops <= prev_nop_frag_holds);
7253 /* Enforce NOPS as a minimum. */
7254 if (nops > prev_nop_frag_required)
7255 prev_nop_frag_required = nops;
7257 if (prev_nop_frag_holds == prev_nop_frag_required)
7259 /* Settle for the current number of nops. Update the history
7260 accordingly (for the benefit of any future .set reorder code). */
7261 prev_nop_frag = NULL;
7262 insert_into_history (prev_nop_frag_since,
7263 prev_nop_frag_holds, NOP_INSN);
7267 /* Allow this instruction to replace one of the nops that was
7268 tentatively added to prev_nop_frag. */
7269 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
7270 prev_nop_frag_holds--;
7271 prev_nop_frag_since++;
7275 method = get_append_method (ip, address_expr, reloc_type);
7276 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
7278 dwarf2_emit_insn (0);
7279 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7280 so "move" the instruction address accordingly.
7282 Also, it doesn't seem appropriate for the assembler to reorder .loc
7283 entries. If this instruction is a branch that we are going to swap
7284 with the previous instruction, the two instructions should be
7285 treated as a unit, and the debug information for both instructions
7286 should refer to the start of the branch sequence. Using the
7287 current position is certainly wrong when swapping a 32-bit branch
7288 and a 16-bit delay slot, since the current position would then be
7289 in the middle of a branch. */
7290 dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp);
7292 relax32 = (mips_relax_branch
7293 /* Don't try branch relaxation within .set nomacro, or within
7294 .set noat if we use $at for PIC computations. If it turns
7295 out that the branch was out-of-range, we'll get an error. */
7296 && !mips_opts.warn_about_macros
7297 && (mips_opts.at || mips_pic == NO_PIC)
7298 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7299 as they have no complementing branches. */
7300 && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP)));
7302 if (!HAVE_CODE_COMPRESSION
7305 && *reloc_type == BFD_RELOC_16_PCREL_S2
7306 && delayed_branch_p (ip))
7308 relaxed_branch = TRUE;
7309 add_relaxed_insn (ip, (relaxed_branch_length
7311 uncond_branch_p (ip) ? -1
7312 : branch_likely_p (ip) ? 1
7316 uncond_branch_p (ip),
7317 branch_likely_p (ip),
7318 pinfo & INSN_WRITE_GPR_31,
7320 address_expr->X_add_symbol,
7321 address_expr->X_add_number);
7322 *reloc_type = BFD_RELOC_UNUSED;
7324 else if (mips_opts.micromips
7326 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
7327 || *reloc_type > BFD_RELOC_UNUSED)
7328 && (delayed_branch_p (ip) || compact_branch_p (ip))
7329 /* Don't try branch relaxation when users specify
7330 16-bit/32-bit instructions. */
7331 && !forced_insn_length)
7333 bfd_boolean relax16 = (method != APPEND_ADD_COMPACT
7334 && *reloc_type > BFD_RELOC_UNUSED);
7335 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
7336 int uncond = uncond_branch_p (ip) ? -1 : 0;
7337 int compact = compact_branch_p (ip) || method == APPEND_ADD_COMPACT;
7338 int nods = method == APPEND_ADD_WITH_NOP;
7339 int al = pinfo & INSN_WRITE_GPR_31;
7340 int length32 = nods ? 8 : 4;
7342 gas_assert (address_expr != NULL);
7343 gas_assert (!mips_relax.sequence);
7345 relaxed_branch = TRUE;
7347 method = APPEND_ADD;
7349 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
7350 add_relaxed_insn (ip, length32, relax16 ? 2 : 4,
7351 RELAX_MICROMIPS_ENCODE (type, AT, mips_opts.insn32,
7352 uncond, compact, al, nods,
7354 address_expr->X_add_symbol,
7355 address_expr->X_add_number);
7356 *reloc_type = BFD_RELOC_UNUSED;
7358 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
7363 /* We need to set up a variant frag. */
7364 gas_assert (address_expr != NULL);
7365 /* Pass any `O_symbol' expression unchanged as an `expr_section'
7366 symbol created by `make_expr_symbol' may not get a necessary
7367 external relocation produced. */
7368 if (address_expr->X_op == O_symbol)
7370 symbol = address_expr->X_add_symbol;
7371 offset = address_expr->X_add_number;
7375 symbol = make_expr_symbol (address_expr);
7378 add_relaxed_insn (ip, 4, 0,
7380 (*reloc_type - BFD_RELOC_UNUSED,
7381 forced_insn_length == 2, forced_insn_length == 4,
7382 delayed_branch_p (&history[0]),
7383 history[0].mips16_absolute_jump_p),
7386 else if (mips_opts.mips16 && insn_length (ip) == 2)
7388 if (!delayed_branch_p (ip))
7389 /* Make sure there is enough room to swap this instruction with
7390 a following jump instruction. */
7392 add_fixed_insn (ip);
7396 if (mips_opts.mips16
7397 && mips_opts.noreorder
7398 && delayed_branch_p (&history[0]))
7399 as_warn (_("extended instruction in delay slot"));
7401 if (mips_relax.sequence)
7403 /* If we've reached the end of this frag, turn it into a variant
7404 frag and record the information for the instructions we've
7406 if (frag_room () < 4)
7407 relax_close_frag ();
7408 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
7411 if (mips_relax.sequence != 2)
7413 if (mips_macro_warning.first_insn_sizes[0] == 0)
7414 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
7415 mips_macro_warning.sizes[0] += insn_length (ip);
7416 mips_macro_warning.insns[0]++;
7418 if (mips_relax.sequence != 1)
7420 if (mips_macro_warning.first_insn_sizes[1] == 0)
7421 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
7422 mips_macro_warning.sizes[1] += insn_length (ip);
7423 mips_macro_warning.insns[1]++;
7426 if (mips_opts.mips16)
7429 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
7431 add_fixed_insn (ip);
7434 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
7436 bfd_reloc_code_real_type final_type[3];
7437 reloc_howto_type *howto0;
7438 reloc_howto_type *howto;
7441 /* Perform any necessary conversion to microMIPS relocations
7442 and find out how many relocations there actually are. */
7443 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
7444 final_type[i] = micromips_map_reloc (reloc_type[i]);
7446 /* In a compound relocation, it is the final (outermost)
7447 operator that determines the relocated field. */
7448 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
7453 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
7454 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
7455 bfd_get_reloc_size (howto),
7457 howto0 && howto0->pc_relative,
7460 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
7461 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
7462 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
7464 /* These relocations can have an addend that won't fit in
7465 4 octets for 64bit assembly. */
7467 && ! howto->partial_inplace
7468 && (reloc_type[0] == BFD_RELOC_16
7469 || reloc_type[0] == BFD_RELOC_32
7470 || reloc_type[0] == BFD_RELOC_MIPS_JMP
7471 || reloc_type[0] == BFD_RELOC_GPREL16
7472 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
7473 || reloc_type[0] == BFD_RELOC_GPREL32
7474 || reloc_type[0] == BFD_RELOC_64
7475 || reloc_type[0] == BFD_RELOC_CTOR
7476 || reloc_type[0] == BFD_RELOC_MIPS_SUB
7477 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
7478 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
7479 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
7480 || reloc_type[0] == BFD_RELOC_MIPS_REL16
7481 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
7482 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
7483 || hi16_reloc_p (reloc_type[0])
7484 || lo16_reloc_p (reloc_type[0])))
7485 ip->fixp[0]->fx_no_overflow = 1;
7487 /* These relocations can have an addend that won't fit in 2 octets. */
7488 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
7489 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1)
7490 ip->fixp[0]->fx_no_overflow = 1;
7492 if (mips_relax.sequence)
7494 if (mips_relax.first_fixup == 0)
7495 mips_relax.first_fixup = ip->fixp[0];
7497 else if (reloc_needs_lo_p (*reloc_type))
7499 struct mips_hi_fixup *hi_fixup;
7501 /* Reuse the last entry if it already has a matching %lo. */
7502 hi_fixup = mips_hi_fixup_list;
7504 || !fixup_has_matching_lo_p (hi_fixup->fixp))
7506 hi_fixup = XNEW (struct mips_hi_fixup);
7507 hi_fixup->next = mips_hi_fixup_list;
7508 mips_hi_fixup_list = hi_fixup;
7510 hi_fixup->fixp = ip->fixp[0];
7511 hi_fixup->seg = now_seg;
7514 /* Add fixups for the second and third relocations, if given.
7515 Note that the ABI allows the second relocation to be
7516 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
7517 moment we only use RSS_UNDEF, but we could add support
7518 for the others if it ever becomes necessary. */
7519 for (i = 1; i < 3; i++)
7520 if (reloc_type[i] != BFD_RELOC_UNUSED)
7522 ip->fixp[i] = fix_new (ip->frag, ip->where,
7523 ip->fixp[0]->fx_size, NULL, 0,
7524 FALSE, final_type[i]);
7526 /* Use fx_tcbit to mark compound relocs. */
7527 ip->fixp[0]->fx_tcbit = 1;
7528 ip->fixp[i]->fx_tcbit = 1;
7532 /* Update the register mask information. */
7533 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
7534 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
7539 insert_into_history (0, 1, ip);
7542 case APPEND_ADD_WITH_NOP:
7544 struct mips_cl_insn *nop;
7546 insert_into_history (0, 1, ip);
7547 nop = get_delay_slot_nop (ip);
7548 add_fixed_insn (nop);
7549 insert_into_history (0, 1, nop);
7550 if (mips_relax.sequence)
7551 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
7555 case APPEND_ADD_COMPACT:
7556 /* Convert MIPS16 jr/jalr into a "compact" jump. */
7557 if (mips_opts.mips16)
7559 ip->insn_opcode |= 0x0080;
7560 find_altered_mips16_opcode (ip);
7562 /* Convert microMIPS instructions. */
7563 else if (mips_opts.micromips)
7566 if ((ip->insn_opcode & 0xffe0) == 0x4580)
7567 ip->insn_opcode |= 0x0020;
7569 else if ((ip->insn_opcode & 0xfc00) == 0xcc00)
7570 ip->insn_opcode = 0x40e00000;
7571 /* beqz16->beqzc, bnez16->bnezc */
7572 else if ((ip->insn_opcode & 0xdc00) == 0x8c00)
7574 unsigned long regno;
7576 regno = ip->insn_opcode >> MICROMIPSOP_SH_MD;
7577 regno &= MICROMIPSOP_MASK_MD;
7578 regno = micromips_to_32_reg_d_map[regno];
7579 ip->insn_opcode = (((ip->insn_opcode << 9) & 0x00400000)
7580 | (regno << MICROMIPSOP_SH_RS)
7581 | 0x40a00000) ^ 0x00400000;
7583 /* beqz->beqzc, bnez->bnezc */
7584 else if ((ip->insn_opcode & 0xdfe00000) == 0x94000000)
7585 ip->insn_opcode = ((ip->insn_opcode & 0x001f0000)
7586 | ((ip->insn_opcode >> 7) & 0x00400000)
7587 | 0x40a00000) ^ 0x00400000;
7588 /* beq $0->beqzc, bne $0->bnezc */
7589 else if ((ip->insn_opcode & 0xdc1f0000) == 0x94000000)
7590 ip->insn_opcode = (((ip->insn_opcode >>
7591 (MICROMIPSOP_SH_RT - MICROMIPSOP_SH_RS))
7592 & (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS))
7593 | ((ip->insn_opcode >> 7) & 0x00400000)
7594 | 0x40a00000) ^ 0x00400000;
7597 find_altered_micromips_opcode (ip);
7602 insert_into_history (0, 1, ip);
7607 struct mips_cl_insn delay = history[0];
7609 if (relaxed_branch || delay.frag != ip->frag)
7611 /* Add the delay slot instruction to the end of the
7612 current frag and shrink the fixed part of the
7613 original frag. If the branch occupies the tail of
7614 the latter, move it backwards to cover the gap. */
7615 delay.frag->fr_fix -= branch_disp;
7616 if (delay.frag == ip->frag)
7617 move_insn (ip, ip->frag, ip->where - branch_disp);
7618 add_fixed_insn (&delay);
7622 /* If this is not a relaxed branch and we are in the
7623 same frag, then just swap the instructions. */
7624 move_insn (ip, delay.frag, delay.where);
7625 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
7629 insert_into_history (0, 1, &delay);
7634 /* If we have just completed an unconditional branch, clear the history. */
7635 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
7636 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
7640 mips_no_prev_insn ();
7642 for (i = 0; i < ARRAY_SIZE (history); i++)
7643 history[i].cleared_p = 1;
7646 /* We need to emit a label at the end of branch-likely macros. */
7647 if (emit_branch_likely_macro)
7649 emit_branch_likely_macro = FALSE;
7650 micromips_add_label ();
7653 /* We just output an insn, so the next one doesn't have a label. */
7654 mips_clear_insn_labels ();
7657 /* Forget that there was any previous instruction or label.
7658 When BRANCH is true, the branch history is also flushed. */
7661 mips_no_prev_insn (void)
7663 prev_nop_frag = NULL;
7664 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
7665 mips_clear_insn_labels ();
7668 /* This function must be called before we emit something other than
7669 instructions. It is like mips_no_prev_insn except that it inserts
7670 any NOPS that might be needed by previous instructions. */
7673 mips_emit_delays (void)
7675 if (! mips_opts.noreorder)
7677 int nops = nops_for_insn (0, history, NULL);
7681 add_fixed_insn (NOP_INSN);
7682 mips_move_text_labels ();
7685 mips_no_prev_insn ();
7688 /* Start a (possibly nested) noreorder block. */
7691 start_noreorder (void)
7693 if (mips_opts.noreorder == 0)
7698 /* None of the instructions before the .set noreorder can be moved. */
7699 for (i = 0; i < ARRAY_SIZE (history); i++)
7700 history[i].fixed_p = 1;
7702 /* Insert any nops that might be needed between the .set noreorder
7703 block and the previous instructions. We will later remove any
7704 nops that turn out not to be needed. */
7705 nops = nops_for_insn (0, history, NULL);
7708 if (mips_optimize != 0)
7710 /* Record the frag which holds the nop instructions, so
7711 that we can remove them if we don't need them. */
7712 frag_grow (nops * NOP_INSN_SIZE);
7713 prev_nop_frag = frag_now;
7714 prev_nop_frag_holds = nops;
7715 prev_nop_frag_required = 0;
7716 prev_nop_frag_since = 0;
7719 for (; nops > 0; --nops)
7720 add_fixed_insn (NOP_INSN);
7722 /* Move on to a new frag, so that it is safe to simply
7723 decrease the size of prev_nop_frag. */
7724 frag_wane (frag_now);
7726 mips_move_text_labels ();
7728 mips_mark_labels ();
7729 mips_clear_insn_labels ();
7731 mips_opts.noreorder++;
7732 mips_any_noreorder = 1;
7735 /* End a nested noreorder block. */
7738 end_noreorder (void)
7740 mips_opts.noreorder--;
7741 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
7743 /* Commit to inserting prev_nop_frag_required nops and go back to
7744 handling nop insertion the .set reorder way. */
7745 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
7747 insert_into_history (prev_nop_frag_since,
7748 prev_nop_frag_required, NOP_INSN);
7749 prev_nop_frag = NULL;
7753 /* Sign-extend 32-bit mode constants that have bit 31 set and all
7754 higher bits unset. */
7757 normalize_constant_expr (expressionS *ex)
7759 if (ex->X_op == O_constant
7760 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7761 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7765 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
7766 all higher bits unset. */
7769 normalize_address_expr (expressionS *ex)
7771 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
7772 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
7773 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7774 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7778 /* Try to match TOKENS against OPCODE, storing the result in INSN.
7779 Return true if the match was successful.
7781 OPCODE_EXTRA is a value that should be ORed into the opcode
7782 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
7783 there are more alternatives after OPCODE and SOFT_MATCH is
7784 as for mips_arg_info. */
7787 match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
7788 struct mips_operand_token *tokens, unsigned int opcode_extra,
7789 bfd_boolean lax_match, bfd_boolean complete_p)
7792 struct mips_arg_info arg;
7793 const struct mips_operand *operand;
7796 imm_expr.X_op = O_absent;
7797 offset_expr.X_op = O_absent;
7798 offset_reloc[0] = BFD_RELOC_UNUSED;
7799 offset_reloc[1] = BFD_RELOC_UNUSED;
7800 offset_reloc[2] = BFD_RELOC_UNUSED;
7802 create_insn (insn, opcode);
7803 /* When no opcode suffix is specified, assume ".xyzw". */
7804 if ((opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0 && opcode_extra == 0)
7805 insn->insn_opcode |= 0xf << mips_vu0_channel_mask.lsb;
7807 insn->insn_opcode |= opcode_extra;
7808 memset (&arg, 0, sizeof (arg));
7812 arg.last_regno = ILLEGAL_REG;
7813 arg.dest_regno = ILLEGAL_REG;
7814 arg.lax_match = lax_match;
7815 for (args = opcode->args;; ++args)
7817 if (arg.token->type == OT_END)
7819 /* Handle unary instructions in which only one operand is given.
7820 The source is then the same as the destination. */
7821 if (arg.opnum == 1 && *args == ',')
7823 operand = (mips_opts.micromips
7824 ? decode_micromips_operand (args + 1)
7825 : decode_mips_operand (args + 1));
7826 if (operand && mips_optional_operand_p (operand))
7834 /* Treat elided base registers as $0. */
7835 if (strcmp (args, "(b)") == 0)
7843 /* The register suffix is optional. */
7848 /* Fail the match if there were too few operands. */
7852 /* Successful match. */
7855 clear_insn_error ();
7856 if (arg.dest_regno == arg.last_regno
7857 && strncmp (insn->insn_mo->name, "jalr", 4) == 0)
7861 (0, _("source and destination must be different"));
7862 else if (arg.last_regno == 31)
7864 (0, _("a destination register must be supplied"));
7866 else if (arg.last_regno == 31
7867 && (strncmp (insn->insn_mo->name, "bltzal", 6) == 0
7868 || strncmp (insn->insn_mo->name, "bgezal", 6) == 0))
7869 set_insn_error (0, _("the source register must not be $31"));
7870 check_completed_insn (&arg);
7874 /* Fail the match if the line has too many operands. */
7878 /* Handle characters that need to match exactly. */
7879 if (*args == '(' || *args == ')' || *args == ',')
7881 if (match_char (&arg, *args))
7888 if (arg.token->type == OT_DOUBLE_CHAR
7889 && arg.token->u.ch == *args)
7897 /* Handle special macro operands. Work out the properties of
7906 *offset_reloc = BFD_RELOC_MIPS_19_PCREL_S2;
7910 *offset_reloc = BFD_RELOC_MIPS_18_PCREL_S3;
7919 *offset_reloc = BFD_RELOC_MIPS_JMP;
7923 *offset_reloc = BFD_RELOC_MIPS_26_PCREL_S2;
7927 *offset_reloc = BFD_RELOC_MIPS_21_PCREL_S2;
7933 if (!match_const_int (&arg, &imm_expr.X_add_number))
7935 imm_expr.X_op = O_constant;
7937 normalize_constant_expr (&imm_expr);
7941 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
7943 /* Assume that the offset has been elided and that what
7944 we saw was a base register. The match will fail later
7945 if that assumption turns out to be wrong. */
7946 offset_expr.X_op = O_constant;
7947 offset_expr.X_add_number = 0;
7951 if (!match_expression (&arg, &offset_expr, offset_reloc))
7953 normalize_address_expr (&offset_expr);
7958 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7964 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7970 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7976 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7982 *offset_reloc = BFD_RELOC_16_PCREL_S2;
7986 *offset_reloc = BFD_RELOC_MIPS_JMP;
7990 gas_assert (mips_opts.micromips);
7996 if (!forced_insn_length)
7997 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
7999 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
8001 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
8007 operand = (mips_opts.micromips
8008 ? decode_micromips_operand (args)
8009 : decode_mips_operand (args));
8013 /* Skip prefixes. */
8014 if (*args == '+' || *args == 'm' || *args == '-')
8017 if (mips_optional_operand_p (operand)
8019 && (arg.token[0].type != OT_REG
8020 || arg.token[1].type == OT_END))
8022 /* Assume that the register has been elided and is the
8023 same as the first operand. */
8028 if (!match_operand (&arg, operand))
8033 /* Like match_insn, but for MIPS16. */
8036 match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
8037 struct mips_operand_token *tokens)
8040 const struct mips_operand *operand;
8041 const struct mips_operand *ext_operand;
8042 struct mips_arg_info arg;
8045 create_insn (insn, opcode);
8046 imm_expr.X_op = O_absent;
8047 offset_expr.X_op = O_absent;
8048 offset_reloc[0] = BFD_RELOC_UNUSED;
8049 offset_reloc[1] = BFD_RELOC_UNUSED;
8050 offset_reloc[2] = BFD_RELOC_UNUSED;
8053 memset (&arg, 0, sizeof (arg));
8057 arg.last_regno = ILLEGAL_REG;
8058 arg.dest_regno = ILLEGAL_REG;
8060 for (args = opcode->args;; ++args)
8064 if (arg.token->type == OT_END)
8068 /* Handle unary instructions in which only one operand is given.
8069 The source is then the same as the destination. */
8070 if (arg.opnum == 1 && *args == ',')
8072 operand = decode_mips16_operand (args[1], FALSE);
8073 if (operand && mips_optional_operand_p (operand))
8081 /* Fail the match if there were too few operands. */
8085 /* Successful match. Stuff the immediate value in now, if
8087 clear_insn_error ();
8088 if (opcode->pinfo == INSN_MACRO)
8090 gas_assert (relax_char == 0 || relax_char == 'p');
8091 gas_assert (*offset_reloc == BFD_RELOC_UNUSED);
8094 && offset_expr.X_op == O_constant
8095 && calculate_reloc (*offset_reloc,
8096 offset_expr.X_add_number,
8099 mips16_immed (NULL, 0, relax_char, *offset_reloc, value,
8100 forced_insn_length, &insn->insn_opcode);
8101 offset_expr.X_op = O_absent;
8102 *offset_reloc = BFD_RELOC_UNUSED;
8104 else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED)
8106 if (forced_insn_length == 2)
8107 set_insn_error (0, _("invalid unextended operand value"));
8108 forced_insn_length = 4;
8109 insn->insn_opcode |= MIPS16_EXTEND;
8111 else if (relax_char)
8112 *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char;
8114 check_completed_insn (&arg);
8118 /* Fail the match if the line has too many operands. */
8122 /* Handle characters that need to match exactly. */
8123 if (*args == '(' || *args == ')' || *args == ',')
8125 if (match_char (&arg, *args))
8143 if (!match_const_int (&arg, &imm_expr.X_add_number))
8145 imm_expr.X_op = O_constant;
8147 normalize_constant_expr (&imm_expr);
8152 *offset_reloc = BFD_RELOC_MIPS16_JMP;
8153 insn->insn_opcode <<= 16;
8157 operand = decode_mips16_operand (c, FALSE);
8161 /* '6' is a special case. It is used for BREAK and SDBBP,
8162 whose operands are only meaningful to the software that decodes
8163 them. This means that there is no architectural reason why
8164 they cannot be prefixed by EXTEND, but in practice,
8165 exception handlers will only look at the instruction
8166 itself. We therefore allow '6' to be extended when
8167 disassembling but not when assembling. */
8168 if (operand->type != OP_PCREL && c != '6')
8170 ext_operand = decode_mips16_operand (c, TRUE);
8171 if (operand != ext_operand)
8173 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
8175 offset_expr.X_op = O_constant;
8176 offset_expr.X_add_number = 0;
8181 /* We need the OT_INTEGER check because some MIPS16
8182 immediate variants are listed before the register ones. */
8183 if (arg.token->type != OT_INTEGER
8184 || !match_expression (&arg, &offset_expr, offset_reloc))
8187 /* '8' is used for SLTI(U) and has traditionally not
8188 been allowed to take relocation operators. */
8189 if (offset_reloc[0] != BFD_RELOC_UNUSED
8190 && (ext_operand->size != 16 || c == '8'))
8198 if (mips_optional_operand_p (operand)
8200 && (arg.token[0].type != OT_REG
8201 || arg.token[1].type == OT_END))
8203 /* Assume that the register has been elided and is the
8204 same as the first operand. */
8209 if (!match_operand (&arg, operand))
8214 /* Record that the current instruction is invalid for the current ISA. */
8217 match_invalid_for_isa (void)
8220 (0, _("opcode not supported on this processor: %s (%s)"),
8221 mips_cpu_info_from_arch (mips_opts.arch)->name,
8222 mips_cpu_info_from_isa (mips_opts.isa)->name);
8225 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8226 Return true if a definite match or failure was found, storing any match
8227 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8228 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8229 tried and failed to match under normal conditions and now want to try a
8230 more relaxed match. */
8233 match_insns (struct mips_cl_insn *insn, const struct mips_opcode *first,
8234 const struct mips_opcode *past, struct mips_operand_token *tokens,
8235 int opcode_extra, bfd_boolean lax_match)
8237 const struct mips_opcode *opcode;
8238 const struct mips_opcode *invalid_delay_slot;
8239 bfd_boolean seen_valid_for_isa, seen_valid_for_size;
8241 /* Search for a match, ignoring alternatives that don't satisfy the
8242 current ISA or forced_length. */
8243 invalid_delay_slot = 0;
8244 seen_valid_for_isa = FALSE;
8245 seen_valid_for_size = FALSE;
8249 gas_assert (strcmp (opcode->name, first->name) == 0);
8250 if (is_opcode_valid (opcode))
8252 seen_valid_for_isa = TRUE;
8253 if (is_size_valid (opcode))
8255 bfd_boolean delay_slot_ok;
8257 seen_valid_for_size = TRUE;
8258 delay_slot_ok = is_delay_slot_valid (opcode);
8259 if (match_insn (insn, opcode, tokens, opcode_extra,
8260 lax_match, delay_slot_ok))
8264 if (!invalid_delay_slot)
8265 invalid_delay_slot = opcode;
8274 while (opcode < past && strcmp (opcode->name, first->name) == 0);
8276 /* If the only matches we found had the wrong length for the delay slot,
8277 pick the first such match. We'll issue an appropriate warning later. */
8278 if (invalid_delay_slot)
8280 if (match_insn (insn, invalid_delay_slot, tokens, opcode_extra,
8286 /* Handle the case where we didn't try to match an instruction because
8287 all the alternatives were incompatible with the current ISA. */
8288 if (!seen_valid_for_isa)
8290 match_invalid_for_isa ();
8294 /* Handle the case where we didn't try to match an instruction because
8295 all the alternatives were of the wrong size. */
8296 if (!seen_valid_for_size)
8298 if (mips_opts.insn32)
8299 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
8302 (0, _("unrecognized %d-bit version of microMIPS opcode"),
8303 8 * forced_insn_length);
8310 /* Like match_insns, but for MIPS16. */
8313 match_mips16_insns (struct mips_cl_insn *insn, const struct mips_opcode *first,
8314 struct mips_operand_token *tokens)
8316 const struct mips_opcode *opcode;
8317 bfd_boolean seen_valid_for_isa;
8319 /* Search for a match, ignoring alternatives that don't satisfy the
8320 current ISA. There are no separate entries for extended forms so
8321 we deal with forced_length later. */
8322 seen_valid_for_isa = FALSE;
8326 gas_assert (strcmp (opcode->name, first->name) == 0);
8327 if (is_opcode_valid_16 (opcode))
8329 seen_valid_for_isa = TRUE;
8330 if (match_mips16_insn (insn, opcode, tokens))
8335 while (opcode < &mips16_opcodes[bfd_mips16_num_opcodes]
8336 && strcmp (opcode->name, first->name) == 0);
8338 /* Handle the case where we didn't try to match an instruction because
8339 all the alternatives were incompatible with the current ISA. */
8340 if (!seen_valid_for_isa)
8342 match_invalid_for_isa ();
8349 /* Set up global variables for the start of a new macro. */
8354 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
8355 memset (&mips_macro_warning.first_insn_sizes, 0,
8356 sizeof (mips_macro_warning.first_insn_sizes));
8357 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
8358 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
8359 && delayed_branch_p (&history[0]));
8361 && history[0].frag->fr_type == rs_machine_dependent
8362 && RELAX_MICROMIPS_P (history[0].frag->fr_subtype)
8363 && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype))
8364 mips_macro_warning.delay_slot_length = 0;
8366 switch (history[0].insn_mo->pinfo2
8367 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
8369 case INSN2_BRANCH_DELAY_32BIT:
8370 mips_macro_warning.delay_slot_length = 4;
8372 case INSN2_BRANCH_DELAY_16BIT:
8373 mips_macro_warning.delay_slot_length = 2;
8376 mips_macro_warning.delay_slot_length = 0;
8379 mips_macro_warning.first_frag = NULL;
8382 /* Given that a macro is longer than one instruction or of the wrong size,
8383 return the appropriate warning for it. Return null if no warning is
8384 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8385 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8386 and RELAX_NOMACRO. */
8389 macro_warning (relax_substateT subtype)
8391 if (subtype & RELAX_DELAY_SLOT)
8392 return _("macro instruction expanded into multiple instructions"
8393 " in a branch delay slot");
8394 else if (subtype & RELAX_NOMACRO)
8395 return _("macro instruction expanded into multiple instructions");
8396 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
8397 | RELAX_DELAY_SLOT_SIZE_SECOND))
8398 return ((subtype & RELAX_DELAY_SLOT_16BIT)
8399 ? _("macro instruction expanded into a wrong size instruction"
8400 " in a 16-bit branch delay slot")
8401 : _("macro instruction expanded into a wrong size instruction"
8402 " in a 32-bit branch delay slot"));
8407 /* Finish up a macro. Emit warnings as appropriate. */
8412 /* Relaxation warning flags. */
8413 relax_substateT subtype = 0;
8415 /* Check delay slot size requirements. */
8416 if (mips_macro_warning.delay_slot_length == 2)
8417 subtype |= RELAX_DELAY_SLOT_16BIT;
8418 if (mips_macro_warning.delay_slot_length != 0)
8420 if (mips_macro_warning.delay_slot_length
8421 != mips_macro_warning.first_insn_sizes[0])
8422 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
8423 if (mips_macro_warning.delay_slot_length
8424 != mips_macro_warning.first_insn_sizes[1])
8425 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
8428 /* Check instruction count requirements. */
8429 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
8431 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
8432 subtype |= RELAX_SECOND_LONGER;
8433 if (mips_opts.warn_about_macros)
8434 subtype |= RELAX_NOMACRO;
8435 if (mips_macro_warning.delay_slot_p)
8436 subtype |= RELAX_DELAY_SLOT;
8439 /* If both alternatives fail to fill a delay slot correctly,
8440 emit the warning now. */
8441 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
8442 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
8447 s = subtype & (RELAX_DELAY_SLOT_16BIT
8448 | RELAX_DELAY_SLOT_SIZE_FIRST
8449 | RELAX_DELAY_SLOT_SIZE_SECOND);
8450 msg = macro_warning (s);
8452 as_warn ("%s", msg);
8456 /* If both implementations are longer than 1 instruction, then emit the
8458 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
8463 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
8464 msg = macro_warning (s);
8466 as_warn ("%s", msg);
8470 /* If any flags still set, then one implementation might need a warning
8471 and the other either will need one of a different kind or none at all.
8472 Pass any remaining flags over to relaxation. */
8473 if (mips_macro_warning.first_frag != NULL)
8474 mips_macro_warning.first_frag->fr_subtype |= subtype;
8477 /* Instruction operand formats used in macros that vary between
8478 standard MIPS and microMIPS code. */
8480 static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } };
8481 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
8482 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
8483 static const char * const lui_fmt[2] = { "t,u", "s,u" };
8484 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
8485 static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } };
8486 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
8487 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
8489 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
8490 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8491 : cop12_fmt[mips_opts.micromips])
8492 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
8493 #define LUI_FMT (lui_fmt[mips_opts.micromips])
8494 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
8495 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
8496 : mem12_fmt[mips_opts.micromips])
8497 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
8498 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
8499 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
8501 /* Read a macro's relocation codes from *ARGS and store them in *R.
8502 The first argument in *ARGS will be either the code for a single
8503 relocation or -1 followed by the three codes that make up a
8504 composite relocation. */
8507 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
8511 next = va_arg (*args, int);
8513 r[0] = (bfd_reloc_code_real_type) next;
8516 for (i = 0; i < 3; i++)
8517 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
8518 /* This function is only used for 16-bit relocation fields.
8519 To make the macro code simpler, treat an unrelocated value
8520 in the same way as BFD_RELOC_LO16. */
8521 if (r[0] == BFD_RELOC_UNUSED)
8522 r[0] = BFD_RELOC_LO16;
8526 /* Build an instruction created by a macro expansion. This is passed
8527 a pointer to the count of instructions created so far, an
8528 expression, the name of the instruction to build, an operand format
8529 string, and corresponding arguments. */
8532 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
8534 const struct mips_opcode *mo = NULL;
8535 bfd_reloc_code_real_type r[3];
8536 const struct mips_opcode *amo;
8537 const struct mips_operand *operand;
8538 struct hash_control *hash;
8539 struct mips_cl_insn insn;
8543 va_start (args, fmt);
8545 if (mips_opts.mips16)
8547 mips16_macro_build (ep, name, fmt, &args);
8552 r[0] = BFD_RELOC_UNUSED;
8553 r[1] = BFD_RELOC_UNUSED;
8554 r[2] = BFD_RELOC_UNUSED;
8555 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
8556 amo = (struct mips_opcode *) hash_find (hash, name);
8558 gas_assert (strcmp (name, amo->name) == 0);
8562 /* Search until we get a match for NAME. It is assumed here that
8563 macros will never generate MDMX, MIPS-3D, or MT instructions.
8564 We try to match an instruction that fulfils the branch delay
8565 slot instruction length requirement (if any) of the previous
8566 instruction. While doing this we record the first instruction
8567 seen that matches all the other conditions and use it anyway
8568 if the requirement cannot be met; we will issue an appropriate
8569 warning later on. */
8570 if (strcmp (fmt, amo->args) == 0
8571 && amo->pinfo != INSN_MACRO
8572 && is_opcode_valid (amo)
8573 && is_size_valid (amo))
8575 if (is_delay_slot_valid (amo))
8585 gas_assert (amo->name);
8587 while (strcmp (name, amo->name) == 0);
8590 create_insn (&insn, mo);
8603 macro_read_relocs (&args, r);
8604 gas_assert (*r == BFD_RELOC_GPREL16
8605 || *r == BFD_RELOC_MIPS_HIGHER
8606 || *r == BFD_RELOC_HI16_S
8607 || *r == BFD_RELOC_LO16
8608 || *r == BFD_RELOC_MIPS_GOT_OFST);
8612 macro_read_relocs (&args, r);
8616 macro_read_relocs (&args, r);
8617 gas_assert (ep != NULL
8618 && (ep->X_op == O_constant
8619 || (ep->X_op == O_symbol
8620 && (*r == BFD_RELOC_MIPS_HIGHEST
8621 || *r == BFD_RELOC_HI16_S
8622 || *r == BFD_RELOC_HI16
8623 || *r == BFD_RELOC_GPREL16
8624 || *r == BFD_RELOC_MIPS_GOT_HI16
8625 || *r == BFD_RELOC_MIPS_CALL_HI16))));
8629 gas_assert (ep != NULL);
8632 * This allows macro() to pass an immediate expression for
8633 * creating short branches without creating a symbol.
8635 * We don't allow branch relaxation for these branches, as
8636 * they should only appear in ".set nomacro" anyway.
8638 if (ep->X_op == O_constant)
8640 /* For microMIPS we always use relocations for branches.
8641 So we should not resolve immediate values. */
8642 gas_assert (!mips_opts.micromips);
8644 if ((ep->X_add_number & 3) != 0)
8645 as_bad (_("branch to misaligned address (0x%lx)"),
8646 (unsigned long) ep->X_add_number);
8647 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
8648 as_bad (_("branch address range overflow (0x%lx)"),
8649 (unsigned long) ep->X_add_number);
8650 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
8654 *r = BFD_RELOC_16_PCREL_S2;
8658 gas_assert (ep != NULL);
8659 *r = BFD_RELOC_MIPS_JMP;
8663 operand = (mips_opts.micromips
8664 ? decode_micromips_operand (fmt)
8665 : decode_mips_operand (fmt));
8669 uval = va_arg (args, int);
8670 if (operand->type == OP_CLO_CLZ_DEST)
8671 uval |= (uval << 5);
8672 insn_insert_operand (&insn, operand, uval);
8674 if (*fmt == '+' || *fmt == 'm' || *fmt == '-')
8680 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
8682 append_insn (&insn, ep, r, TRUE);
8686 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
8689 struct mips_opcode *mo;
8690 struct mips_cl_insn insn;
8691 const struct mips_operand *operand;
8692 bfd_reloc_code_real_type r[3]
8693 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
8695 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
8697 gas_assert (strcmp (name, mo->name) == 0);
8699 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
8702 gas_assert (mo->name);
8703 gas_assert (strcmp (name, mo->name) == 0);
8706 create_insn (&insn, mo);
8743 gas_assert (ep != NULL);
8745 if (ep->X_op != O_constant)
8746 *r = (int) BFD_RELOC_UNUSED + c;
8747 else if (calculate_reloc (*r, ep->X_add_number, &value))
8749 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode);
8751 *r = BFD_RELOC_UNUSED;
8757 operand = decode_mips16_operand (c, FALSE);
8761 insn_insert_operand (&insn, operand, va_arg (*args, int));
8766 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
8768 append_insn (&insn, ep, r, TRUE);
8772 * Generate a "jalr" instruction with a relocation hint to the called
8773 * function. This occurs in NewABI PIC code.
8776 macro_build_jalr (expressionS *ep, int cprestore)
8778 static const bfd_reloc_code_real_type jalr_relocs[2]
8779 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
8780 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
8784 if (MIPS_JALR_HINT_P (ep))
8789 if (mips_opts.micromips)
8791 jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32
8792 ? "jalr" : "jalrs");
8793 if (MIPS_JALR_HINT_P (ep)
8795 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
8796 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
8798 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
8801 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
8802 if (MIPS_JALR_HINT_P (ep))
8803 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
8807 * Generate a "lui" instruction.
8810 macro_build_lui (expressionS *ep, int regnum)
8812 gas_assert (! mips_opts.mips16);
8814 if (ep->X_op != O_constant)
8816 gas_assert (ep->X_op == O_symbol);
8817 /* _gp_disp is a special case, used from s_cpload.
8818 __gnu_local_gp is used if mips_no_shared. */
8819 gas_assert (mips_pic == NO_PIC
8821 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
8822 || (! mips_in_shared
8823 && strcmp (S_GET_NAME (ep->X_add_symbol),
8824 "__gnu_local_gp") == 0));
8827 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
8830 /* Generate a sequence of instructions to do a load or store from a constant
8831 offset off of a base register (breg) into/from a target register (treg),
8832 using AT if necessary. */
8834 macro_build_ldst_constoffset (expressionS *ep, const char *op,
8835 int treg, int breg, int dbl)
8837 gas_assert (ep->X_op == O_constant);
8839 /* Sign-extending 32-bit constants makes their handling easier. */
8841 normalize_constant_expr (ep);
8843 /* Right now, this routine can only handle signed 32-bit constants. */
8844 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
8845 as_warn (_("operand overflow"));
8847 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
8849 /* Signed 16-bit offset will fit in the op. Easy! */
8850 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8854 /* 32-bit offset, need multiple instructions and AT, like:
8855 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
8856 addu $tempreg,$tempreg,$breg
8857 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
8858 to handle the complete offset. */
8859 macro_build_lui (ep, AT);
8860 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8861 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8864 as_bad (_("macro used $at after \".set noat\""));
8869 * Generates code to set the $at register to true (one)
8870 * if reg is less than the immediate expression.
8873 set_at (int reg, int unsignedp)
8875 if (imm_expr.X_add_number >= -0x8000
8876 && imm_expr.X_add_number < 0x8000)
8877 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
8878 AT, reg, BFD_RELOC_LO16);
8881 load_register (AT, &imm_expr, GPR_SIZE == 64);
8882 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
8886 /* Count the leading zeroes by performing a binary chop. This is a
8887 bulky bit of source, but performance is a LOT better for the
8888 majority of values than a simple loop to count the bits:
8889 for (lcnt = 0; (lcnt < 32); lcnt++)
8890 if ((v) & (1 << (31 - lcnt)))
8892 However it is not code size friendly, and the gain will drop a bit
8893 on certain cached systems.
8895 #define COUNT_TOP_ZEROES(v) \
8896 (((v) & ~0xffff) == 0 \
8897 ? ((v) & ~0xff) == 0 \
8898 ? ((v) & ~0xf) == 0 \
8899 ? ((v) & ~0x3) == 0 \
8900 ? ((v) & ~0x1) == 0 \
8905 : ((v) & ~0x7) == 0 \
8908 : ((v) & ~0x3f) == 0 \
8909 ? ((v) & ~0x1f) == 0 \
8912 : ((v) & ~0x7f) == 0 \
8915 : ((v) & ~0xfff) == 0 \
8916 ? ((v) & ~0x3ff) == 0 \
8917 ? ((v) & ~0x1ff) == 0 \
8920 : ((v) & ~0x7ff) == 0 \
8923 : ((v) & ~0x3fff) == 0 \
8924 ? ((v) & ~0x1fff) == 0 \
8927 : ((v) & ~0x7fff) == 0 \
8930 : ((v) & ~0xffffff) == 0 \
8931 ? ((v) & ~0xfffff) == 0 \
8932 ? ((v) & ~0x3ffff) == 0 \
8933 ? ((v) & ~0x1ffff) == 0 \
8936 : ((v) & ~0x7ffff) == 0 \
8939 : ((v) & ~0x3fffff) == 0 \
8940 ? ((v) & ~0x1fffff) == 0 \
8943 : ((v) & ~0x7fffff) == 0 \
8946 : ((v) & ~0xfffffff) == 0 \
8947 ? ((v) & ~0x3ffffff) == 0 \
8948 ? ((v) & ~0x1ffffff) == 0 \
8951 : ((v) & ~0x7ffffff) == 0 \
8954 : ((v) & ~0x3fffffff) == 0 \
8955 ? ((v) & ~0x1fffffff) == 0 \
8958 : ((v) & ~0x7fffffff) == 0 \
8963 * This routine generates the least number of instructions necessary to load
8964 * an absolute expression value into a register.
8967 load_register (int reg, expressionS *ep, int dbl)
8970 expressionS hi32, lo32;
8972 if (ep->X_op != O_big)
8974 gas_assert (ep->X_op == O_constant);
8976 /* Sign-extending 32-bit constants makes their handling easier. */
8978 normalize_constant_expr (ep);
8980 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
8982 /* We can handle 16 bit signed values with an addiu to
8983 $zero. No need to ever use daddiu here, since $zero and
8984 the result are always correct in 32 bit mode. */
8985 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
8988 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
8990 /* We can handle 16 bit unsigned values with an ori to
8992 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
8995 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
8997 /* 32 bit values require an lui. */
8998 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
8999 if ((ep->X_add_number & 0xffff) != 0)
9000 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
9005 /* The value is larger than 32 bits. */
9007 if (!dbl || GPR_SIZE == 32)
9011 sprintf_vma (value, ep->X_add_number);
9012 as_bad (_("number (0x%s) larger than 32 bits"), value);
9013 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
9017 if (ep->X_op != O_big)
9020 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
9021 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
9022 hi32.X_add_number &= 0xffffffff;
9024 lo32.X_add_number &= 0xffffffff;
9028 gas_assert (ep->X_add_number > 2);
9029 if (ep->X_add_number == 3)
9030 generic_bignum[3] = 0;
9031 else if (ep->X_add_number > 4)
9032 as_bad (_("number larger than 64 bits"));
9033 lo32.X_op = O_constant;
9034 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
9035 hi32.X_op = O_constant;
9036 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
9039 if (hi32.X_add_number == 0)
9044 unsigned long hi, lo;
9046 if (hi32.X_add_number == (offsetT) 0xffffffff)
9048 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
9050 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
9053 if (lo32.X_add_number & 0x80000000)
9055 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
9056 if (lo32.X_add_number & 0xffff)
9057 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
9062 /* Check for 16bit shifted constant. We know that hi32 is
9063 non-zero, so start the mask on the first bit of the hi32
9068 unsigned long himask, lomask;
9072 himask = 0xffff >> (32 - shift);
9073 lomask = (0xffff << shift) & 0xffffffff;
9077 himask = 0xffff << (shift - 32);
9080 if ((hi32.X_add_number & ~(offsetT) himask) == 0
9081 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
9085 tmp.X_op = O_constant;
9087 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
9088 | (lo32.X_add_number >> shift));
9090 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
9091 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
9092 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
9093 reg, reg, (shift >= 32) ? shift - 32 : shift);
9098 while (shift <= (64 - 16));
9100 /* Find the bit number of the lowest one bit, and store the
9101 shifted value in hi/lo. */
9102 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
9103 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
9107 while ((lo & 1) == 0)
9112 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
9118 while ((hi & 1) == 0)
9127 /* Optimize if the shifted value is a (power of 2) - 1. */
9128 if ((hi == 0 && ((lo + 1) & lo) == 0)
9129 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
9131 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
9136 /* This instruction will set the register to be all
9138 tmp.X_op = O_constant;
9139 tmp.X_add_number = (offsetT) -1;
9140 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
9144 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
9145 reg, reg, (bit >= 32) ? bit - 32 : bit);
9147 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
9148 reg, reg, (shift >= 32) ? shift - 32 : shift);
9153 /* Sign extend hi32 before calling load_register, because we can
9154 generally get better code when we load a sign extended value. */
9155 if ((hi32.X_add_number & 0x80000000) != 0)
9156 hi32.X_add_number |= ~(offsetT) 0xffffffff;
9157 load_register (reg, &hi32, 0);
9160 if ((lo32.X_add_number & 0xffff0000) == 0)
9164 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
9172 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
9174 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
9175 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
9181 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
9185 mid16.X_add_number >>= 16;
9186 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
9187 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
9190 if ((lo32.X_add_number & 0xffff) != 0)
9191 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
9195 load_delay_nop (void)
9197 if (!gpr_interlocks)
9198 macro_build (NULL, "nop", "");
9201 /* Load an address into a register. */
9204 load_address (int reg, expressionS *ep, int *used_at)
9206 if (ep->X_op != O_constant
9207 && ep->X_op != O_symbol)
9209 as_bad (_("expression too complex"));
9210 ep->X_op = O_constant;
9213 if (ep->X_op == O_constant)
9215 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
9219 if (mips_pic == NO_PIC)
9221 /* If this is a reference to a GP relative symbol, we want
9222 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
9224 lui $reg,<sym> (BFD_RELOC_HI16_S)
9225 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9226 If we have an addend, we always use the latter form.
9228 With 64bit address space and a usable $at we want
9229 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9230 lui $at,<sym> (BFD_RELOC_HI16_S)
9231 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9232 daddiu $at,<sym> (BFD_RELOC_LO16)
9236 If $at is already in use, we use a path which is suboptimal
9237 on superscalar processors.
9238 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9239 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9241 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9243 daddiu $reg,<sym> (BFD_RELOC_LO16)
9245 For GP relative symbols in 64bit address space we can use
9246 the same sequence as in 32bit address space. */
9247 if (HAVE_64BIT_SYMBOLS)
9249 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
9250 && !nopic_need_relax (ep->X_add_symbol, 1))
9252 relax_start (ep->X_add_symbol);
9253 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
9254 mips_gp_register, BFD_RELOC_GPREL16);
9258 if (*used_at == 0 && mips_opts.at)
9260 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
9261 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
9262 macro_build (ep, "daddiu", "t,r,j", reg, reg,
9263 BFD_RELOC_MIPS_HIGHER);
9264 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
9265 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
9266 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
9271 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
9272 macro_build (ep, "daddiu", "t,r,j", reg, reg,
9273 BFD_RELOC_MIPS_HIGHER);
9274 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
9275 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
9276 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
9277 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
9280 if (mips_relax.sequence)
9285 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
9286 && !nopic_need_relax (ep->X_add_symbol, 1))
9288 relax_start (ep->X_add_symbol);
9289 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
9290 mips_gp_register, BFD_RELOC_GPREL16);
9293 macro_build_lui (ep, reg);
9294 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
9295 reg, reg, BFD_RELOC_LO16);
9296 if (mips_relax.sequence)
9300 else if (!mips_big_got)
9304 /* If this is a reference to an external symbol, we want
9305 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9307 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9309 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9310 If there is a constant, it must be added in after.
9312 If we have NewABI, we want
9313 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9314 unless we're referencing a global symbol with a non-zero
9315 offset, in which case cst must be added separately. */
9318 if (ep->X_add_number)
9320 ex.X_add_number = ep->X_add_number;
9321 ep->X_add_number = 0;
9322 relax_start (ep->X_add_symbol);
9323 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9324 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9325 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9326 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9327 ex.X_op = O_constant;
9328 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
9329 reg, reg, BFD_RELOC_LO16);
9330 ep->X_add_number = ex.X_add_number;
9333 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9334 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9335 if (mips_relax.sequence)
9340 ex.X_add_number = ep->X_add_number;
9341 ep->X_add_number = 0;
9342 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9343 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9345 relax_start (ep->X_add_symbol);
9347 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9351 if (ex.X_add_number != 0)
9353 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9354 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9355 ex.X_op = O_constant;
9356 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
9357 reg, reg, BFD_RELOC_LO16);
9361 else if (mips_big_got)
9365 /* This is the large GOT case. If this is a reference to an
9366 external symbol, we want
9367 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9369 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
9371 Otherwise, for a reference to a local symbol in old ABI, we want
9372 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9374 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9375 If there is a constant, it must be added in after.
9377 In the NewABI, for local symbols, with or without offsets, we want:
9378 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9379 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9383 ex.X_add_number = ep->X_add_number;
9384 ep->X_add_number = 0;
9385 relax_start (ep->X_add_symbol);
9386 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
9387 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9388 reg, reg, mips_gp_register);
9389 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
9390 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
9391 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9392 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9393 else if (ex.X_add_number)
9395 ex.X_op = O_constant;
9396 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9400 ep->X_add_number = ex.X_add_number;
9402 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9403 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
9404 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9405 BFD_RELOC_MIPS_GOT_OFST);
9410 ex.X_add_number = ep->X_add_number;
9411 ep->X_add_number = 0;
9412 relax_start (ep->X_add_symbol);
9413 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
9414 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9415 reg, reg, mips_gp_register);
9416 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
9417 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
9419 if (reg_needs_delay (mips_gp_register))
9421 /* We need a nop before loading from $gp. This special
9422 check is required because the lui which starts the main
9423 instruction stream does not refer to $gp, and so will not
9424 insert the nop which may be required. */
9425 macro_build (NULL, "nop", "");
9427 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9428 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9430 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9434 if (ex.X_add_number != 0)
9436 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9437 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9438 ex.X_op = O_constant;
9439 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9447 if (!mips_opts.at && *used_at == 1)
9448 as_bad (_("macro used $at after \".set noat\""));
9451 /* Move the contents of register SOURCE into register DEST. */
9454 move_register (int dest, int source)
9456 /* Prefer to use a 16-bit microMIPS instruction unless the previous
9457 instruction specifically requires a 32-bit one. */
9458 if (mips_opts.micromips
9459 && !mips_opts.insn32
9460 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
9461 macro_build (NULL, "move", "mp,mj", dest, source);
9463 macro_build (NULL, "or", "d,v,t", dest, source, 0);
9466 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
9467 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
9468 The two alternatives are:
9470 Global symbol Local sybmol
9471 ------------- ------------
9472 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
9474 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
9476 load_got_offset emits the first instruction and add_got_offset
9477 emits the second for a 16-bit offset or add_got_offset_hilo emits
9478 a sequence to add a 32-bit offset using a scratch register. */
9481 load_got_offset (int dest, expressionS *local)
9486 global.X_add_number = 0;
9488 relax_start (local->X_add_symbol);
9489 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
9490 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9492 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
9493 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9498 add_got_offset (int dest, expressionS *local)
9502 global.X_op = O_constant;
9503 global.X_op_symbol = NULL;
9504 global.X_add_symbol = NULL;
9505 global.X_add_number = local->X_add_number;
9507 relax_start (local->X_add_symbol);
9508 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
9509 dest, dest, BFD_RELOC_LO16);
9511 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
9516 add_got_offset_hilo (int dest, expressionS *local, int tmp)
9519 int hold_mips_optimize;
9521 global.X_op = O_constant;
9522 global.X_op_symbol = NULL;
9523 global.X_add_symbol = NULL;
9524 global.X_add_number = local->X_add_number;
9526 relax_start (local->X_add_symbol);
9527 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
9529 /* Set mips_optimize around the lui instruction to avoid
9530 inserting an unnecessary nop after the lw. */
9531 hold_mips_optimize = mips_optimize;
9533 macro_build_lui (&global, tmp);
9534 mips_optimize = hold_mips_optimize;
9535 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
9538 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
9541 /* Emit a sequence of instructions to emulate a branch likely operation.
9542 BR is an ordinary branch corresponding to one to be emulated. BRNEG
9543 is its complementing branch with the original condition negated.
9544 CALL is set if the original branch specified the link operation.
9545 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
9547 Code like this is produced in the noreorder mode:
9552 delay slot (executed only if branch taken)
9560 delay slot (executed only if branch taken)
9563 In the reorder mode the delay slot would be filled with a nop anyway,
9564 so code produced is simply:
9569 This function is used when producing code for the microMIPS ASE that
9570 does not implement branch likely instructions in hardware. */
9573 macro_build_branch_likely (const char *br, const char *brneg,
9574 int call, expressionS *ep, const char *fmt,
9575 unsigned int sreg, unsigned int treg)
9577 int noreorder = mips_opts.noreorder;
9580 gas_assert (mips_opts.micromips);
9584 micromips_label_expr (&expr1);
9585 macro_build (&expr1, brneg, fmt, sreg, treg);
9586 macro_build (NULL, "nop", "");
9587 macro_build (ep, call ? "bal" : "b", "p");
9589 /* Set to true so that append_insn adds a label. */
9590 emit_branch_likely_macro = TRUE;
9594 macro_build (ep, br, fmt, sreg, treg);
9595 macro_build (NULL, "nop", "");
9600 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
9601 the condition code tested. EP specifies the branch target. */
9604 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
9631 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
9634 /* Emit a two-argument branch macro specified by TYPE, using SREG as
9635 the register tested. EP specifies the branch target. */
9638 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
9640 const char *brneg = NULL;
9650 br = mips_opts.micromips ? "bgez" : "bgezl";
9654 gas_assert (mips_opts.micromips);
9655 br = mips_opts.insn32 ? "bgezal" : "bgezals";
9663 br = mips_opts.micromips ? "bgtz" : "bgtzl";
9670 br = mips_opts.micromips ? "blez" : "blezl";
9677 br = mips_opts.micromips ? "bltz" : "bltzl";
9681 gas_assert (mips_opts.micromips);
9682 br = mips_opts.insn32 ? "bltzal" : "bltzals";
9689 if (mips_opts.micromips && brneg)
9690 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
9692 macro_build (ep, br, "s,p", sreg);
9695 /* Emit a three-argument branch macro specified by TYPE, using SREG and
9696 TREG as the registers tested. EP specifies the branch target. */
9699 macro_build_branch_rsrt (int type, expressionS *ep,
9700 unsigned int sreg, unsigned int treg)
9702 const char *brneg = NULL;
9714 br = mips_opts.micromips ? "beq" : "beql";
9723 br = mips_opts.micromips ? "bne" : "bnel";
9729 if (mips_opts.micromips && brneg)
9730 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
9732 macro_build (ep, br, "s,t,p", sreg, treg);
9735 /* Return the high part that should be loaded in order to make the low
9736 part of VALUE accessible using an offset of OFFBITS bits. */
9739 offset_high_part (offsetT value, unsigned int offbits)
9746 bias = 1 << (offbits - 1);
9747 low_mask = bias * 2 - 1;
9748 return (value + bias) & ~low_mask;
9751 /* Return true if the value stored in offset_expr and offset_reloc
9752 fits into a signed offset of OFFBITS bits. RANGE is the maximum
9753 amount that the caller wants to add without inducing overflow
9754 and ALIGN is the known alignment of the value in bytes. */
9757 small_offset_p (unsigned int range, unsigned int align, unsigned int offbits)
9761 /* Accept any relocation operator if overflow isn't a concern. */
9762 if (range < align && *offset_reloc != BFD_RELOC_UNUSED)
9765 /* These relocations are guaranteed not to overflow in correct links. */
9766 if (*offset_reloc == BFD_RELOC_MIPS_LITERAL
9767 || gprel16_reloc_p (*offset_reloc))
9770 if (offset_expr.X_op == O_constant
9771 && offset_high_part (offset_expr.X_add_number, offbits) == 0
9772 && offset_high_part (offset_expr.X_add_number + range, offbits) == 0)
9779 * This routine implements the seemingly endless macro or synthesized
9780 * instructions and addressing modes in the mips assembly language. Many
9781 * of these macros are simple and are similar to each other. These could
9782 * probably be handled by some kind of table or grammar approach instead of
9783 * this verbose method. Others are not simple macros but are more like
9784 * optimizing code generation.
9785 * One interesting optimization is when several store macros appear
9786 * consecutively that would load AT with the upper half of the same address.
9787 * The ensuing load upper instructions are omitted. This implies some kind
9788 * of global optimization. We currently only optimize within a single macro.
9789 * For many of the load and store macros if the address is specified as a
9790 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
9791 * first load register 'at' with zero and use it as the base register. The
9792 * mips assembler simply uses register $zero. Just one tiny optimization
9796 macro (struct mips_cl_insn *ip, char *str)
9798 const struct mips_operand_array *operands;
9799 unsigned int breg, i;
9800 unsigned int tempreg;
9803 expressionS label_expr;
9818 bfd_boolean large_offset;
9820 int hold_mips_optimize;
9822 unsigned int op[MAX_OPERANDS];
9824 gas_assert (! mips_opts.mips16);
9826 operands = insn_operands (ip);
9827 for (i = 0; i < MAX_OPERANDS; i++)
9828 if (operands->operand[i])
9829 op[i] = insn_extract_operand (ip, operands->operand[i]);
9833 mask = ip->insn_mo->mask;
9835 label_expr.X_op = O_constant;
9836 label_expr.X_op_symbol = NULL;
9837 label_expr.X_add_symbol = NULL;
9838 label_expr.X_add_number = 0;
9840 expr1.X_op = O_constant;
9841 expr1.X_op_symbol = NULL;
9842 expr1.X_add_symbol = NULL;
9843 expr1.X_add_number = 1;
9860 if (mips_opts.micromips)
9861 micromips_label_expr (&label_expr);
9863 label_expr.X_add_number = 8;
9864 macro_build (&label_expr, "bgez", "s,p", op[1]);
9866 macro_build (NULL, "nop", "");
9868 move_register (op[0], op[1]);
9869 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", op[0], 0, op[1]);
9870 if (mips_opts.micromips)
9871 micromips_add_label ();
9888 if (!mips_opts.micromips)
9890 if (imm_expr.X_add_number >= -0x200
9891 && imm_expr.X_add_number < 0x200)
9893 macro_build (NULL, s, "t,r,.", op[0], op[1],
9894 (int) imm_expr.X_add_number);
9903 if (imm_expr.X_add_number >= -0x8000
9904 && imm_expr.X_add_number < 0x8000)
9906 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
9911 load_register (AT, &imm_expr, dbl);
9912 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
9931 if (imm_expr.X_add_number >= 0
9932 && imm_expr.X_add_number < 0x10000)
9934 if (mask != M_NOR_I)
9935 macro_build (&imm_expr, s, "t,r,i", op[0], op[1], BFD_RELOC_LO16);
9938 macro_build (&imm_expr, "ori", "t,r,i",
9939 op[0], op[1], BFD_RELOC_LO16);
9940 macro_build (NULL, "nor", "d,v,t", op[0], op[0], 0);
9946 load_register (AT, &imm_expr, GPR_SIZE == 64);
9947 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
9951 switch (imm_expr.X_add_number)
9954 macro_build (NULL, "nop", "");
9957 macro_build (NULL, "packrl.ph", "d,s,t", op[0], op[0], op[1]);
9961 macro_build (NULL, "balign", "t,s,2", op[0], op[1],
9962 (int) imm_expr.X_add_number);
9965 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
9966 (unsigned long) imm_expr.X_add_number);
9975 gas_assert (mips_opts.micromips);
9976 macro_build_branch_ccl (mask, &offset_expr,
9977 EXTRACT_OPERAND (1, BCC, *ip));
9984 if (imm_expr.X_add_number == 0)
9990 load_register (op[1], &imm_expr, GPR_SIZE == 64);
9995 macro_build_branch_rsrt (mask, &offset_expr, op[0], op[1]);
10000 /* Fall through. */
10003 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[0]);
10004 else if (op[0] == 0)
10005 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[1]);
10009 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
10010 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10011 &offset_expr, AT, ZERO);
10021 macro_build_branch_rs (mask, &offset_expr, op[0]);
10026 /* Fall through. */
10028 /* Check for > max integer. */
10029 if (imm_expr.X_add_number >= GPR_SMAX)
10032 /* Result is always false. */
10034 macro_build (NULL, "nop", "");
10036 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
10039 ++imm_expr.X_add_number;
10043 if (mask == M_BGEL_I)
10045 if (imm_expr.X_add_number == 0)
10047 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
10048 &offset_expr, op[0]);
10051 if (imm_expr.X_add_number == 1)
10053 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
10054 &offset_expr, op[0]);
10057 if (imm_expr.X_add_number <= GPR_SMIN)
10060 /* result is always true */
10061 as_warn (_("branch %s is always true"), ip->insn_mo->name);
10062 macro_build (&offset_expr, "b", "p");
10067 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10068 &offset_expr, AT, ZERO);
10073 /* Fall through. */
10077 else if (op[0] == 0)
10078 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10079 &offset_expr, ZERO, op[1]);
10083 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
10084 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10085 &offset_expr, AT, ZERO);
10091 /* Fall through. */
10095 && imm_expr.X_add_number == -1))
10097 ++imm_expr.X_add_number;
10101 if (mask == M_BGEUL_I)
10103 if (imm_expr.X_add_number == 0)
10105 else if (imm_expr.X_add_number == 1)
10106 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10107 &offset_expr, op[0], ZERO);
10112 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10113 &offset_expr, AT, ZERO);
10119 /* Fall through. */
10122 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[0]);
10123 else if (op[0] == 0)
10124 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[1]);
10128 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
10129 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10130 &offset_expr, AT, ZERO);
10136 /* Fall through. */
10139 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10140 &offset_expr, op[0], ZERO);
10141 else if (op[0] == 0)
10146 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
10147 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10148 &offset_expr, AT, ZERO);
10154 /* Fall through. */
10157 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
10158 else if (op[0] == 0)
10159 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[1]);
10163 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
10164 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10165 &offset_expr, AT, ZERO);
10171 /* Fall through. */
10173 if (imm_expr.X_add_number >= GPR_SMAX)
10175 ++imm_expr.X_add_number;
10179 if (mask == M_BLTL_I)
10181 if (imm_expr.X_add_number == 0)
10182 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
10183 else if (imm_expr.X_add_number == 1)
10184 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
10189 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10190 &offset_expr, AT, ZERO);
10196 /* Fall through. */
10199 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10200 &offset_expr, op[0], ZERO);
10201 else if (op[0] == 0)
10206 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
10207 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10208 &offset_expr, AT, ZERO);
10214 /* Fall through. */
10218 && imm_expr.X_add_number == -1))
10220 ++imm_expr.X_add_number;
10224 if (mask == M_BLTUL_I)
10226 if (imm_expr.X_add_number == 0)
10228 else if (imm_expr.X_add_number == 1)
10229 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10230 &offset_expr, op[0], ZERO);
10235 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10236 &offset_expr, AT, ZERO);
10242 /* Fall through. */
10245 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
10246 else if (op[0] == 0)
10247 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[1]);
10251 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
10252 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10253 &offset_expr, AT, ZERO);
10259 /* Fall through. */
10263 else if (op[0] == 0)
10264 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10265 &offset_expr, ZERO, op[1]);
10269 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
10270 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10271 &offset_expr, AT, ZERO);
10277 /* Fall through. */
10283 /* Fall through. */
10289 as_warn (_("divide by zero"));
10291 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
10293 macro_build (NULL, "break", BRK_FMT, 7);
10297 start_noreorder ();
10300 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
10301 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
10305 if (mips_opts.micromips)
10306 micromips_label_expr (&label_expr);
10308 label_expr.X_add_number = 8;
10309 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
10310 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
10311 macro_build (NULL, "break", BRK_FMT, 7);
10312 if (mips_opts.micromips)
10313 micromips_add_label ();
10315 expr1.X_add_number = -1;
10317 load_register (AT, &expr1, dbl);
10318 if (mips_opts.micromips)
10319 micromips_label_expr (&label_expr);
10321 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
10322 macro_build (&label_expr, "bne", "s,t,p", op[2], AT);
10325 expr1.X_add_number = 1;
10326 load_register (AT, &expr1, dbl);
10327 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
10331 expr1.X_add_number = 0x80000000;
10332 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
10336 macro_build (NULL, "teq", TRAP_FMT, op[1], AT, 6);
10337 /* We want to close the noreorder block as soon as possible, so
10338 that later insns are available for delay slot filling. */
10343 if (mips_opts.micromips)
10344 micromips_label_expr (&label_expr);
10346 label_expr.X_add_number = 8;
10347 macro_build (&label_expr, "bne", "s,t,p", op[1], AT);
10348 macro_build (NULL, "nop", "");
10350 /* We want to close the noreorder block as soon as possible, so
10351 that later insns are available for delay slot filling. */
10354 macro_build (NULL, "break", BRK_FMT, 6);
10356 if (mips_opts.micromips)
10357 micromips_add_label ();
10358 macro_build (NULL, s, MFHL_FMT, op[0]);
10397 if (imm_expr.X_add_number == 0)
10399 as_warn (_("divide by zero"));
10401 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
10403 macro_build (NULL, "break", BRK_FMT, 7);
10406 if (imm_expr.X_add_number == 1)
10408 if (strcmp (s2, "mflo") == 0)
10409 move_register (op[0], op[1]);
10411 move_register (op[0], ZERO);
10414 if (imm_expr.X_add_number == -1 && s[strlen (s) - 1] != 'u')
10416 if (strcmp (s2, "mflo") == 0)
10417 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", op[0], op[1]);
10419 move_register (op[0], ZERO);
10424 load_register (AT, &imm_expr, dbl);
10425 macro_build (NULL, s, "z,s,t", op[1], AT);
10426 macro_build (NULL, s2, MFHL_FMT, op[0]);
10445 start_noreorder ();
10448 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
10449 macro_build (NULL, s, "z,s,t", op[1], op[2]);
10450 /* We want to close the noreorder block as soon as possible, so
10451 that later insns are available for delay slot filling. */
10456 if (mips_opts.micromips)
10457 micromips_label_expr (&label_expr);
10459 label_expr.X_add_number = 8;
10460 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
10461 macro_build (NULL, s, "z,s,t", op[1], op[2]);
10463 /* We want to close the noreorder block as soon as possible, so
10464 that later insns are available for delay slot filling. */
10466 macro_build (NULL, "break", BRK_FMT, 7);
10467 if (mips_opts.micromips)
10468 micromips_add_label ();
10470 macro_build (NULL, s2, MFHL_FMT, op[0]);
10475 /* Fall through. */
10481 /* Fall through. */
10484 /* Load the address of a symbol into a register. If breg is not
10485 zero, we then add a base register to it. */
10488 if (dbl && GPR_SIZE == 32)
10489 as_warn (_("dla used to load 32-bit register; recommend using la "
10492 if (!dbl && HAVE_64BIT_OBJECTS)
10493 as_warn (_("la used to load 64-bit address; recommend using dla "
10496 if (small_offset_p (0, align, 16))
10498 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", op[0], breg,
10499 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
10503 if (mips_opts.at && (op[0] == breg))
10511 if (offset_expr.X_op != O_symbol
10512 && offset_expr.X_op != O_constant)
10514 as_bad (_("expression too complex"));
10515 offset_expr.X_op = O_constant;
10518 if (offset_expr.X_op == O_constant)
10519 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
10520 else if (mips_pic == NO_PIC)
10522 /* If this is a reference to a GP relative symbol, we want
10523 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
10525 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10526 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10527 If we have a constant, we need two instructions anyhow,
10528 so we may as well always use the latter form.
10530 With 64bit address space and a usable $at we want
10531 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10532 lui $at,<sym> (BFD_RELOC_HI16_S)
10533 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10534 daddiu $at,<sym> (BFD_RELOC_LO16)
10536 daddu $tempreg,$tempreg,$at
10538 If $at is already in use, we use a path which is suboptimal
10539 on superscalar processors.
10540 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10541 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10543 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10545 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
10547 For GP relative symbols in 64bit address space we can use
10548 the same sequence as in 32bit address space. */
10549 if (HAVE_64BIT_SYMBOLS)
10551 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10552 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10554 relax_start (offset_expr.X_add_symbol);
10555 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10556 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
10560 if (used_at == 0 && mips_opts.at)
10562 macro_build (&offset_expr, "lui", LUI_FMT,
10563 tempreg, BFD_RELOC_MIPS_HIGHEST);
10564 macro_build (&offset_expr, "lui", LUI_FMT,
10565 AT, BFD_RELOC_HI16_S);
10566 macro_build (&offset_expr, "daddiu", "t,r,j",
10567 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
10568 macro_build (&offset_expr, "daddiu", "t,r,j",
10569 AT, AT, BFD_RELOC_LO16);
10570 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
10571 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
10576 macro_build (&offset_expr, "lui", LUI_FMT,
10577 tempreg, BFD_RELOC_MIPS_HIGHEST);
10578 macro_build (&offset_expr, "daddiu", "t,r,j",
10579 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
10580 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
10581 macro_build (&offset_expr, "daddiu", "t,r,j",
10582 tempreg, tempreg, BFD_RELOC_HI16_S);
10583 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
10584 macro_build (&offset_expr, "daddiu", "t,r,j",
10585 tempreg, tempreg, BFD_RELOC_LO16);
10588 if (mips_relax.sequence)
10593 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10594 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10596 relax_start (offset_expr.X_add_symbol);
10597 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10598 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
10601 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
10602 as_bad (_("offset too large"));
10603 macro_build_lui (&offset_expr, tempreg);
10604 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10605 tempreg, tempreg, BFD_RELOC_LO16);
10606 if (mips_relax.sequence)
10610 else if (!mips_big_got && !HAVE_NEWABI)
10612 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
10614 /* If this is a reference to an external symbol, and there
10615 is no constant, we want
10616 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10617 or for lca or if tempreg is PIC_CALL_REG
10618 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10619 For a local symbol, we want
10620 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10622 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10624 If we have a small constant, and this is a reference to
10625 an external symbol, we want
10626 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10628 addiu $tempreg,$tempreg,<constant>
10629 For a local symbol, we want the same instruction
10630 sequence, but we output a BFD_RELOC_LO16 reloc on the
10633 If we have a large constant, and this is a reference to
10634 an external symbol, we want
10635 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10636 lui $at,<hiconstant>
10637 addiu $at,$at,<loconstant>
10638 addu $tempreg,$tempreg,$at
10639 For a local symbol, we want the same instruction
10640 sequence, but we output a BFD_RELOC_LO16 reloc on the
10644 if (offset_expr.X_add_number == 0)
10646 if (mips_pic == SVR4_PIC
10648 && (call || tempreg == PIC_CALL_REG))
10649 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
10651 relax_start (offset_expr.X_add_symbol);
10652 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10653 lw_reloc_type, mips_gp_register);
10656 /* We're going to put in an addu instruction using
10657 tempreg, so we may as well insert the nop right
10662 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10663 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
10665 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10666 tempreg, tempreg, BFD_RELOC_LO16);
10668 /* FIXME: If breg == 0, and the next instruction uses
10669 $tempreg, then if this variant case is used an extra
10670 nop will be generated. */
10672 else if (offset_expr.X_add_number >= -0x8000
10673 && offset_expr.X_add_number < 0x8000)
10675 load_got_offset (tempreg, &offset_expr);
10677 add_got_offset (tempreg, &offset_expr);
10681 expr1.X_add_number = offset_expr.X_add_number;
10682 offset_expr.X_add_number =
10683 SEXT_16BIT (offset_expr.X_add_number);
10684 load_got_offset (tempreg, &offset_expr);
10685 offset_expr.X_add_number = expr1.X_add_number;
10686 /* If we are going to add in a base register, and the
10687 target register and the base register are the same,
10688 then we are using AT as a temporary register. Since
10689 we want to load the constant into AT, we add our
10690 current AT (from the global offset table) and the
10691 register into the register now, and pretend we were
10692 not using a base register. */
10696 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10701 add_got_offset_hilo (tempreg, &offset_expr, AT);
10705 else if (!mips_big_got && HAVE_NEWABI)
10707 int add_breg_early = 0;
10709 /* If this is a reference to an external, and there is no
10710 constant, or local symbol (*), with or without a
10712 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10713 or for lca or if tempreg is PIC_CALL_REG
10714 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10716 If we have a small constant, and this is a reference to
10717 an external symbol, we want
10718 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10719 addiu $tempreg,$tempreg,<constant>
10721 If we have a large constant, and this is a reference to
10722 an external symbol, we want
10723 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10724 lui $at,<hiconstant>
10725 addiu $at,$at,<loconstant>
10726 addu $tempreg,$tempreg,$at
10728 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
10729 local symbols, even though it introduces an additional
10732 if (offset_expr.X_add_number)
10734 expr1.X_add_number = offset_expr.X_add_number;
10735 offset_expr.X_add_number = 0;
10737 relax_start (offset_expr.X_add_symbol);
10738 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10739 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10741 if (expr1.X_add_number >= -0x8000
10742 && expr1.X_add_number < 0x8000)
10744 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
10745 tempreg, tempreg, BFD_RELOC_LO16);
10747 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
10751 /* If we are going to add in a base register, and the
10752 target register and the base register are the same,
10753 then we are using AT as a temporary register. Since
10754 we want to load the constant into AT, we add our
10755 current AT (from the global offset table) and the
10756 register into the register now, and pretend we were
10757 not using a base register. */
10762 gas_assert (tempreg == AT);
10763 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10766 add_breg_early = 1;
10769 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
10770 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10776 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10779 offset_expr.X_add_number = expr1.X_add_number;
10781 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10782 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10783 if (add_breg_early)
10785 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10786 op[0], tempreg, breg);
10792 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
10794 relax_start (offset_expr.X_add_symbol);
10795 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10796 BFD_RELOC_MIPS_CALL16, mips_gp_register);
10798 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10799 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10804 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10805 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10808 else if (mips_big_got && !HAVE_NEWABI)
10811 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
10812 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
10813 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
10815 /* This is the large GOT case. If this is a reference to an
10816 external symbol, and there is no constant, we want
10817 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10818 addu $tempreg,$tempreg,$gp
10819 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10820 or for lca or if tempreg is PIC_CALL_REG
10821 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10822 addu $tempreg,$tempreg,$gp
10823 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10824 For a local symbol, we want
10825 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10827 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10829 If we have a small constant, and this is a reference to
10830 an external symbol, we want
10831 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10832 addu $tempreg,$tempreg,$gp
10833 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10835 addiu $tempreg,$tempreg,<constant>
10836 For a local symbol, we want
10837 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10839 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
10841 If we have a large constant, and this is a reference to
10842 an external symbol, we want
10843 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10844 addu $tempreg,$tempreg,$gp
10845 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10846 lui $at,<hiconstant>
10847 addiu $at,$at,<loconstant>
10848 addu $tempreg,$tempreg,$at
10849 For a local symbol, we want
10850 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10851 lui $at,<hiconstant>
10852 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
10853 addu $tempreg,$tempreg,$at
10856 expr1.X_add_number = offset_expr.X_add_number;
10857 offset_expr.X_add_number = 0;
10858 relax_start (offset_expr.X_add_symbol);
10859 gpdelay = reg_needs_delay (mips_gp_register);
10860 if (expr1.X_add_number == 0 && breg == 0
10861 && (call || tempreg == PIC_CALL_REG))
10863 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
10864 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
10866 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
10867 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10868 tempreg, tempreg, mips_gp_register);
10869 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10870 tempreg, lw_reloc_type, tempreg);
10871 if (expr1.X_add_number == 0)
10875 /* We're going to put in an addu instruction using
10876 tempreg, so we may as well insert the nop right
10881 else if (expr1.X_add_number >= -0x8000
10882 && expr1.X_add_number < 0x8000)
10885 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
10886 tempreg, tempreg, BFD_RELOC_LO16);
10892 /* If we are going to add in a base register, and the
10893 target register and the base register are the same,
10894 then we are using AT as a temporary register. Since
10895 we want to load the constant into AT, we add our
10896 current AT (from the global offset table) and the
10897 register into the register now, and pretend we were
10898 not using a base register. */
10903 gas_assert (tempreg == AT);
10905 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10910 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
10911 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
10915 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number);
10920 /* This is needed because this instruction uses $gp, but
10921 the first instruction on the main stream does not. */
10922 macro_build (NULL, "nop", "");
10925 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10926 local_reloc_type, mips_gp_register);
10927 if (expr1.X_add_number >= -0x8000
10928 && expr1.X_add_number < 0x8000)
10931 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10932 tempreg, tempreg, BFD_RELOC_LO16);
10933 /* FIXME: If add_number is 0, and there was no base
10934 register, the external symbol case ended with a load,
10935 so if the symbol turns out to not be external, and
10936 the next instruction uses tempreg, an unnecessary nop
10937 will be inserted. */
10943 /* We must add in the base register now, as in the
10944 external symbol case. */
10945 gas_assert (tempreg == AT);
10947 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10950 /* We set breg to 0 because we have arranged to add
10951 it in in both cases. */
10955 macro_build_lui (&expr1, AT);
10956 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10957 AT, AT, BFD_RELOC_LO16);
10958 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10959 tempreg, tempreg, AT);
10964 else if (mips_big_got && HAVE_NEWABI)
10966 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
10967 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
10968 int add_breg_early = 0;
10970 /* This is the large GOT case. If this is a reference to an
10971 external symbol, and there is no constant, we want
10972 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10973 add $tempreg,$tempreg,$gp
10974 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10975 or for lca or if tempreg is PIC_CALL_REG
10976 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10977 add $tempreg,$tempreg,$gp
10978 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10980 If we have a small constant, and this is a reference to
10981 an external symbol, we want
10982 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10983 add $tempreg,$tempreg,$gp
10984 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10985 addi $tempreg,$tempreg,<constant>
10987 If we have a large constant, and this is a reference to
10988 an external symbol, we want
10989 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10990 addu $tempreg,$tempreg,$gp
10991 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10992 lui $at,<hiconstant>
10993 addi $at,$at,<loconstant>
10994 add $tempreg,$tempreg,$at
10996 If we have NewABI, and we know it's a local symbol, we want
10997 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10998 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
10999 otherwise we have to resort to GOT_HI16/GOT_LO16. */
11001 relax_start (offset_expr.X_add_symbol);
11003 expr1.X_add_number = offset_expr.X_add_number;
11004 offset_expr.X_add_number = 0;
11006 if (expr1.X_add_number == 0 && breg == 0
11007 && (call || tempreg == PIC_CALL_REG))
11009 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
11010 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
11012 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
11013 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11014 tempreg, tempreg, mips_gp_register);
11015 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11016 tempreg, lw_reloc_type, tempreg);
11018 if (expr1.X_add_number == 0)
11020 else if (expr1.X_add_number >= -0x8000
11021 && expr1.X_add_number < 0x8000)
11023 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
11024 tempreg, tempreg, BFD_RELOC_LO16);
11026 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
11030 /* If we are going to add in a base register, and the
11031 target register and the base register are the same,
11032 then we are using AT as a temporary register. Since
11033 we want to load the constant into AT, we add our
11034 current AT (from the global offset table) and the
11035 register into the register now, and pretend we were
11036 not using a base register. */
11041 gas_assert (tempreg == AT);
11042 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11045 add_breg_early = 1;
11048 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
11049 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
11054 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11057 offset_expr.X_add_number = expr1.X_add_number;
11058 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11059 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
11060 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
11061 tempreg, BFD_RELOC_MIPS_GOT_OFST);
11062 if (add_breg_early)
11064 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11065 op[0], tempreg, breg);
11075 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", op[0], tempreg, breg);
11079 gas_assert (!mips_opts.micromips);
11080 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x01);
11084 gas_assert (!mips_opts.micromips);
11085 macro_build (NULL, "c2", "C", 0x02);
11089 gas_assert (!mips_opts.micromips);
11090 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x02);
11094 gas_assert (!mips_opts.micromips);
11095 macro_build (NULL, "c2", "C", 3);
11099 gas_assert (!mips_opts.micromips);
11100 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x03);
11104 /* The j instruction may not be used in PIC code, since it
11105 requires an absolute address. We convert it to a b
11107 if (mips_pic == NO_PIC)
11108 macro_build (&offset_expr, "j", "a");
11110 macro_build (&offset_expr, "b", "p");
11113 /* The jal instructions must be handled as macros because when
11114 generating PIC code they expand to multi-instruction
11115 sequences. Normally they are simple instructions. */
11119 /* Fall through. */
11121 gas_assert (mips_opts.micromips);
11122 if (mips_opts.insn32)
11124 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str);
11132 /* Fall through. */
11135 if (mips_pic == NO_PIC)
11137 s = jals ? "jalrs" : "jalr";
11138 if (mips_opts.micromips
11139 && !mips_opts.insn32
11141 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
11142 macro_build (NULL, s, "mj", op[1]);
11144 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
11148 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
11149 && mips_cprestore_offset >= 0);
11151 if (op[1] != PIC_CALL_REG)
11152 as_warn (_("MIPS PIC call to register other than $25"));
11154 s = ((mips_opts.micromips
11155 && !mips_opts.insn32
11156 && (!mips_opts.noreorder || cprestore))
11157 ? "jalrs" : "jalr");
11158 if (mips_opts.micromips
11159 && !mips_opts.insn32
11161 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
11162 macro_build (NULL, s, "mj", op[1]);
11164 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
11165 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
11167 if (mips_cprestore_offset < 0)
11168 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11171 if (!mips_frame_reg_valid)
11173 as_warn (_("no .frame pseudo-op used in PIC code"));
11174 /* Quiet this warning. */
11175 mips_frame_reg_valid = 1;
11177 if (!mips_cprestore_valid)
11179 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11180 /* Quiet this warning. */
11181 mips_cprestore_valid = 1;
11183 if (mips_opts.noreorder)
11184 macro_build (NULL, "nop", "");
11185 expr1.X_add_number = mips_cprestore_offset;
11186 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
11189 HAVE_64BIT_ADDRESSES);
11197 gas_assert (mips_opts.micromips);
11198 if (mips_opts.insn32)
11200 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str);
11204 /* Fall through. */
11206 if (mips_pic == NO_PIC)
11207 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
11208 else if (mips_pic == SVR4_PIC)
11210 /* If this is a reference to an external symbol, and we are
11211 using a small GOT, we want
11212 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11216 lw $gp,cprestore($sp)
11217 The cprestore value is set using the .cprestore
11218 pseudo-op. If we are using a big GOT, we want
11219 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11221 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11225 lw $gp,cprestore($sp)
11226 If the symbol is not external, we want
11227 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11229 addiu $25,$25,<sym> (BFD_RELOC_LO16)
11232 lw $gp,cprestore($sp)
11234 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11235 sequences above, minus nops, unless the symbol is local,
11236 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11242 relax_start (offset_expr.X_add_symbol);
11243 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11244 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
11247 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11248 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
11254 relax_start (offset_expr.X_add_symbol);
11255 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
11256 BFD_RELOC_MIPS_CALL_HI16);
11257 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
11258 PIC_CALL_REG, mips_gp_register);
11259 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11260 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
11263 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11264 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
11266 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11267 PIC_CALL_REG, PIC_CALL_REG,
11268 BFD_RELOC_MIPS_GOT_OFST);
11272 macro_build_jalr (&offset_expr, 0);
11276 relax_start (offset_expr.X_add_symbol);
11279 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11280 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
11289 gpdelay = reg_needs_delay (mips_gp_register);
11290 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
11291 BFD_RELOC_MIPS_CALL_HI16);
11292 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
11293 PIC_CALL_REG, mips_gp_register);
11294 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11295 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
11300 macro_build (NULL, "nop", "");
11302 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11303 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
11306 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11307 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
11309 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
11311 if (mips_cprestore_offset < 0)
11312 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11315 if (!mips_frame_reg_valid)
11317 as_warn (_("no .frame pseudo-op used in PIC code"));
11318 /* Quiet this warning. */
11319 mips_frame_reg_valid = 1;
11321 if (!mips_cprestore_valid)
11323 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11324 /* Quiet this warning. */
11325 mips_cprestore_valid = 1;
11327 if (mips_opts.noreorder)
11328 macro_build (NULL, "nop", "");
11329 expr1.X_add_number = mips_cprestore_offset;
11330 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
11333 HAVE_64BIT_ADDRESSES);
11337 else if (mips_pic == VXWORKS_PIC)
11338 as_bad (_("non-PIC jump used in PIC library"));
11445 gas_assert (!mips_opts.micromips);
11448 /* Itbl support may require additional care here. */
11454 /* Itbl support may require additional care here. */
11460 offbits = (mips_opts.micromips ? 12
11461 : ISA_IS_R6 (mips_opts.isa) ? 11
11463 /* Itbl support may require additional care here. */
11467 gas_assert (!mips_opts.micromips);
11470 /* Itbl support may require additional care here. */
11476 offbits = (mips_opts.micromips ? 12 : 16);
11481 offbits = (mips_opts.micromips ? 12 : 16);
11486 /* Itbl support may require additional care here. */
11492 offbits = (mips_opts.micromips ? 12
11493 : ISA_IS_R6 (mips_opts.isa) ? 11
11495 /* Itbl support may require additional care here. */
11501 /* Itbl support may require additional care here. */
11507 /* Itbl support may require additional care here. */
11513 offbits = (mips_opts.micromips ? 12 : 16);
11518 offbits = (mips_opts.micromips ? 12 : 16);
11523 offbits = (mips_opts.micromips ? 12
11524 : ISA_IS_R6 (mips_opts.isa) ? 9
11530 offbits = (mips_opts.micromips ? 12
11531 : ISA_IS_R6 (mips_opts.isa) ? 9
11537 offbits = (mips_opts.micromips ? 12 : 16);
11540 gas_assert (mips_opts.micromips);
11547 gas_assert (mips_opts.micromips);
11554 gas_assert (mips_opts.micromips);
11560 gas_assert (mips_opts.micromips);
11567 /* We don't want to use $0 as tempreg. */
11568 if (op[2] == op[0] + lp || op[0] + lp == ZERO)
11571 tempreg = op[0] + lp;
11587 gas_assert (!mips_opts.micromips);
11590 /* Itbl support may require additional care here. */
11596 /* Itbl support may require additional care here. */
11602 offbits = (mips_opts.micromips ? 12
11603 : ISA_IS_R6 (mips_opts.isa) ? 11
11605 /* Itbl support may require additional care here. */
11609 gas_assert (!mips_opts.micromips);
11612 /* Itbl support may require additional care here. */
11618 offbits = (mips_opts.micromips ? 12 : 16);
11623 offbits = (mips_opts.micromips ? 12 : 16);
11628 offbits = (mips_opts.micromips ? 12
11629 : ISA_IS_R6 (mips_opts.isa) ? 9
11635 offbits = (mips_opts.micromips ? 12
11636 : ISA_IS_R6 (mips_opts.isa) ? 9
11641 fmt = (mips_opts.micromips ? "k,~(b)"
11642 : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)"
11644 offbits = (mips_opts.micromips ? 12
11645 : ISA_IS_R6 (mips_opts.isa) ? 9
11655 fmt = (mips_opts.micromips ? "k,~(b)"
11656 : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)"
11658 offbits = (mips_opts.micromips ? 12
11659 : ISA_IS_R6 (mips_opts.isa) ? 9
11671 /* Itbl support may require additional care here. */
11676 offbits = (mips_opts.micromips ? 12
11677 : ISA_IS_R6 (mips_opts.isa) ? 11
11679 /* Itbl support may require additional care here. */
11685 /* Itbl support may require additional care here. */
11689 gas_assert (!mips_opts.micromips);
11692 /* Itbl support may require additional care here. */
11698 offbits = (mips_opts.micromips ? 12 : 16);
11703 offbits = (mips_opts.micromips ? 12 : 16);
11706 gas_assert (mips_opts.micromips);
11712 gas_assert (mips_opts.micromips);
11718 gas_assert (mips_opts.micromips);
11724 gas_assert (mips_opts.micromips);
11733 if (small_offset_p (0, align, 16))
11735 /* The first case exists for M_LD_AB and M_SD_AB, which are
11736 macros for o32 but which should act like normal instructions
11739 macro_build (&offset_expr, s, fmt, op[0], -1, offset_reloc[0],
11740 offset_reloc[1], offset_reloc[2], breg);
11741 else if (small_offset_p (0, align, offbits))
11744 macro_build (NULL, s, fmt, op[0], breg);
11746 macro_build (NULL, s, fmt, op[0],
11747 (int) offset_expr.X_add_number, breg);
11753 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11754 tempreg, breg, -1, offset_reloc[0],
11755 offset_reloc[1], offset_reloc[2]);
11757 macro_build (NULL, s, fmt, op[0], tempreg);
11759 macro_build (NULL, s, fmt, op[0], 0, tempreg);
11767 if (offset_expr.X_op != O_constant
11768 && offset_expr.X_op != O_symbol)
11770 as_bad (_("expression too complex"));
11771 offset_expr.X_op = O_constant;
11774 if (HAVE_32BIT_ADDRESSES
11775 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
11779 sprintf_vma (value, offset_expr.X_add_number);
11780 as_bad (_("number (0x%s) larger than 32 bits"), value);
11783 /* A constant expression in PIC code can be handled just as it
11784 is in non PIC code. */
11785 if (offset_expr.X_op == O_constant)
11787 expr1.X_add_number = offset_high_part (offset_expr.X_add_number,
11788 offbits == 0 ? 16 : offbits);
11789 offset_expr.X_add_number -= expr1.X_add_number;
11791 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
11793 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11794 tempreg, tempreg, breg);
11797 if (offset_expr.X_add_number != 0)
11798 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
11799 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
11800 macro_build (NULL, s, fmt, op[0], tempreg);
11802 else if (offbits == 16)
11803 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
11805 macro_build (NULL, s, fmt, op[0],
11806 (int) offset_expr.X_add_number, tempreg);
11808 else if (offbits != 16)
11810 /* The offset field is too narrow to be used for a low-part
11811 relocation, so load the whole address into the auxiliary
11813 load_address (tempreg, &offset_expr, &used_at);
11815 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11816 tempreg, tempreg, breg);
11818 macro_build (NULL, s, fmt, op[0], tempreg);
11820 macro_build (NULL, s, fmt, op[0], 0, tempreg);
11822 else if (mips_pic == NO_PIC)
11824 /* If this is a reference to a GP relative symbol, and there
11825 is no base register, we want
11826 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11827 Otherwise, if there is no base register, we want
11828 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11829 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11830 If we have a constant, we need two instructions anyhow,
11831 so we always use the latter form.
11833 If we have a base register, and this is a reference to a
11834 GP relative symbol, we want
11835 addu $tempreg,$breg,$gp
11836 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
11838 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11839 addu $tempreg,$tempreg,$breg
11840 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11841 With a constant we always use the latter case.
11843 With 64bit address space and no base register and $at usable,
11845 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11846 lui $at,<sym> (BFD_RELOC_HI16_S)
11847 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11850 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11851 If we have a base register, we want
11852 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11853 lui $at,<sym> (BFD_RELOC_HI16_S)
11854 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11858 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11860 Without $at we can't generate the optimal path for superscalar
11861 processors here since this would require two temporary registers.
11862 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11863 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11865 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11867 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11868 If we have a base register, we want
11869 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11870 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11872 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11874 daddu $tempreg,$tempreg,$breg
11875 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11877 For GP relative symbols in 64bit address space we can use
11878 the same sequence as in 32bit address space. */
11879 if (HAVE_64BIT_SYMBOLS)
11881 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
11882 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11884 relax_start (offset_expr.X_add_symbol);
11887 macro_build (&offset_expr, s, fmt, op[0],
11888 BFD_RELOC_GPREL16, mips_gp_register);
11892 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11893 tempreg, breg, mips_gp_register);
11894 macro_build (&offset_expr, s, fmt, op[0],
11895 BFD_RELOC_GPREL16, tempreg);
11900 if (used_at == 0 && mips_opts.at)
11902 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11903 BFD_RELOC_MIPS_HIGHEST);
11904 macro_build (&offset_expr, "lui", LUI_FMT, AT,
11906 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11907 tempreg, BFD_RELOC_MIPS_HIGHER);
11909 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
11910 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
11911 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
11912 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16,
11918 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11919 BFD_RELOC_MIPS_HIGHEST);
11920 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11921 tempreg, BFD_RELOC_MIPS_HIGHER);
11922 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
11923 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11924 tempreg, BFD_RELOC_HI16_S);
11925 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
11927 macro_build (NULL, "daddu", "d,v,t",
11928 tempreg, tempreg, breg);
11929 macro_build (&offset_expr, s, fmt, op[0],
11930 BFD_RELOC_LO16, tempreg);
11933 if (mips_relax.sequence)
11940 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
11941 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11943 relax_start (offset_expr.X_add_symbol);
11944 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_GPREL16,
11948 macro_build_lui (&offset_expr, tempreg);
11949 macro_build (&offset_expr, s, fmt, op[0],
11950 BFD_RELOC_LO16, tempreg);
11951 if (mips_relax.sequence)
11956 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
11957 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11959 relax_start (offset_expr.X_add_symbol);
11960 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11961 tempreg, breg, mips_gp_register);
11962 macro_build (&offset_expr, s, fmt, op[0],
11963 BFD_RELOC_GPREL16, tempreg);
11966 macro_build_lui (&offset_expr, tempreg);
11967 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11968 tempreg, tempreg, breg);
11969 macro_build (&offset_expr, s, fmt, op[0],
11970 BFD_RELOC_LO16, tempreg);
11971 if (mips_relax.sequence)
11975 else if (!mips_big_got)
11977 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
11979 /* If this is a reference to an external symbol, we want
11980 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11982 <op> op[0],0($tempreg)
11984 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11986 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11987 <op> op[0],0($tempreg)
11989 For NewABI, we want
11990 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11991 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
11993 If there is a base register, we add it to $tempreg before
11994 the <op>. If there is a constant, we stick it in the
11995 <op> instruction. We don't handle constants larger than
11996 16 bits, because we have no way to load the upper 16 bits
11997 (actually, we could handle them for the subset of cases
11998 in which we are not using $at). */
11999 gas_assert (offset_expr.X_op == O_symbol);
12002 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12003 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
12005 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12006 tempreg, tempreg, breg);
12007 macro_build (&offset_expr, s, fmt, op[0],
12008 BFD_RELOC_MIPS_GOT_OFST, tempreg);
12011 expr1.X_add_number = offset_expr.X_add_number;
12012 offset_expr.X_add_number = 0;
12013 if (expr1.X_add_number < -0x8000
12014 || expr1.X_add_number >= 0x8000)
12015 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12016 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12017 lw_reloc_type, mips_gp_register);
12019 relax_start (offset_expr.X_add_symbol);
12021 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
12022 tempreg, BFD_RELOC_LO16);
12025 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12026 tempreg, tempreg, breg);
12027 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
12029 else if (mips_big_got && !HAVE_NEWABI)
12033 /* If this is a reference to an external symbol, we want
12034 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12035 addu $tempreg,$tempreg,$gp
12036 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12037 <op> op[0],0($tempreg)
12039 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12041 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12042 <op> op[0],0($tempreg)
12043 If there is a base register, we add it to $tempreg before
12044 the <op>. If there is a constant, we stick it in the
12045 <op> instruction. We don't handle constants larger than
12046 16 bits, because we have no way to load the upper 16 bits
12047 (actually, we could handle them for the subset of cases
12048 in which we are not using $at). */
12049 gas_assert (offset_expr.X_op == O_symbol);
12050 expr1.X_add_number = offset_expr.X_add_number;
12051 offset_expr.X_add_number = 0;
12052 if (expr1.X_add_number < -0x8000
12053 || expr1.X_add_number >= 0x8000)
12054 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12055 gpdelay = reg_needs_delay (mips_gp_register);
12056 relax_start (offset_expr.X_add_symbol);
12057 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
12058 BFD_RELOC_MIPS_GOT_HI16);
12059 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
12061 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12062 BFD_RELOC_MIPS_GOT_LO16, tempreg);
12065 macro_build (NULL, "nop", "");
12066 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12067 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12069 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
12070 tempreg, BFD_RELOC_LO16);
12074 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12075 tempreg, tempreg, breg);
12076 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
12078 else if (mips_big_got && HAVE_NEWABI)
12080 /* If this is a reference to an external symbol, we want
12081 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12082 add $tempreg,$tempreg,$gp
12083 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12084 <op> op[0],<ofst>($tempreg)
12085 Otherwise, for local symbols, we want:
12086 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12087 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
12088 gas_assert (offset_expr.X_op == O_symbol);
12089 expr1.X_add_number = offset_expr.X_add_number;
12090 offset_expr.X_add_number = 0;
12091 if (expr1.X_add_number < -0x8000
12092 || expr1.X_add_number >= 0x8000)
12093 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12094 relax_start (offset_expr.X_add_symbol);
12095 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
12096 BFD_RELOC_MIPS_GOT_HI16);
12097 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
12099 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12100 BFD_RELOC_MIPS_GOT_LO16, tempreg);
12102 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12103 tempreg, tempreg, breg);
12104 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
12107 offset_expr.X_add_number = expr1.X_add_number;
12108 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12109 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
12111 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12112 tempreg, tempreg, breg);
12113 macro_build (&offset_expr, s, fmt, op[0],
12114 BFD_RELOC_MIPS_GOT_OFST, tempreg);
12123 gas_assert (mips_opts.micromips);
12124 gas_assert (mips_opts.insn32);
12125 start_noreorder ();
12126 macro_build (NULL, "jr", "s", RA);
12127 expr1.X_add_number = op[0] << 2;
12128 macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16);
12133 gas_assert (mips_opts.micromips);
12134 gas_assert (mips_opts.insn32);
12135 macro_build (NULL, "jr", "s", op[0]);
12136 if (mips_opts.noreorder)
12137 macro_build (NULL, "nop", "");
12142 load_register (op[0], &imm_expr, 0);
12146 load_register (op[0], &imm_expr, 1);
12150 if (imm_expr.X_op == O_constant)
12153 load_register (AT, &imm_expr, 0);
12154 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
12159 gas_assert (imm_expr.X_op == O_absent
12160 && offset_expr.X_op == O_symbol
12161 && strcmp (segment_name (S_GET_SEGMENT
12162 (offset_expr.X_add_symbol)),
12164 && offset_expr.X_add_number == 0);
12165 macro_build (&offset_expr, "lwc1", "T,o(b)", op[0],
12166 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
12171 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12172 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12173 order 32 bits of the value and the low order 32 bits are either
12174 zero or in OFFSET_EXPR. */
12175 if (imm_expr.X_op == O_constant)
12177 if (GPR_SIZE == 64)
12178 load_register (op[0], &imm_expr, 1);
12183 if (target_big_endian)
12195 load_register (hreg, &imm_expr, 0);
12198 if (offset_expr.X_op == O_absent)
12199 move_register (lreg, 0);
12202 gas_assert (offset_expr.X_op == O_constant);
12203 load_register (lreg, &offset_expr, 0);
12209 gas_assert (imm_expr.X_op == O_absent);
12211 /* We know that sym is in the .rdata section. First we get the
12212 upper 16 bits of the address. */
12213 if (mips_pic == NO_PIC)
12215 macro_build_lui (&offset_expr, AT);
12220 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12221 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12225 /* Now we load the register(s). */
12226 if (GPR_SIZE == 64)
12229 macro_build (&offset_expr, "ld", "t,o(b)", op[0],
12230 BFD_RELOC_LO16, AT);
12235 macro_build (&offset_expr, "lw", "t,o(b)", op[0],
12236 BFD_RELOC_LO16, AT);
12239 /* FIXME: How in the world do we deal with the possible
12241 offset_expr.X_add_number += 4;
12242 macro_build (&offset_expr, "lw", "t,o(b)",
12243 op[0] + 1, BFD_RELOC_LO16, AT);
12249 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12250 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12251 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12252 the value and the low order 32 bits are either zero or in
12254 if (imm_expr.X_op == O_constant)
12257 load_register (AT, &imm_expr, FPR_SIZE == 64);
12258 if (FPR_SIZE == 64 && GPR_SIZE == 64)
12259 macro_build (NULL, "dmtc1", "t,S", AT, op[0]);
12262 if (ISA_HAS_MXHC1 (mips_opts.isa))
12263 macro_build (NULL, "mthc1", "t,G", AT, op[0]);
12264 else if (FPR_SIZE != 32)
12265 as_bad (_("Unable to generate `%s' compliant code "
12267 (FPR_SIZE == 64) ? "fp64" : "fpxx");
12269 macro_build (NULL, "mtc1", "t,G", AT, op[0] + 1);
12270 if (offset_expr.X_op == O_absent)
12271 macro_build (NULL, "mtc1", "t,G", 0, op[0]);
12274 gas_assert (offset_expr.X_op == O_constant);
12275 load_register (AT, &offset_expr, 0);
12276 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
12282 gas_assert (imm_expr.X_op == O_absent
12283 && offset_expr.X_op == O_symbol
12284 && offset_expr.X_add_number == 0);
12285 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
12286 if (strcmp (s, ".lit8") == 0)
12288 op[2] = mips_gp_register;
12289 offset_reloc[0] = BFD_RELOC_MIPS_LITERAL;
12290 offset_reloc[1] = BFD_RELOC_UNUSED;
12291 offset_reloc[2] = BFD_RELOC_UNUSED;
12295 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
12297 if (mips_pic != NO_PIC)
12298 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12299 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12302 /* FIXME: This won't work for a 64 bit address. */
12303 macro_build_lui (&offset_expr, AT);
12307 offset_reloc[0] = BFD_RELOC_LO16;
12308 offset_reloc[1] = BFD_RELOC_UNUSED;
12309 offset_reloc[2] = BFD_RELOC_UNUSED;
12316 * The MIPS assembler seems to check for X_add_number not
12317 * being double aligned and generating:
12318 * lui at,%hi(foo+1)
12320 * addiu at,at,%lo(foo+1)
12323 * But, the resulting address is the same after relocation so why
12324 * generate the extra instruction?
12326 /* Itbl support may require additional care here. */
12329 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
12338 gas_assert (!mips_opts.micromips);
12339 /* Itbl support may require additional care here. */
12342 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
12362 if (GPR_SIZE == 64)
12372 if (GPR_SIZE == 64)
12380 /* Even on a big endian machine $fn comes before $fn+1. We have
12381 to adjust when loading from memory. We set coproc if we must
12382 load $fn+1 first. */
12383 /* Itbl support may require additional care here. */
12384 if (!target_big_endian)
12388 if (small_offset_p (0, align, 16))
12391 if (!small_offset_p (4, align, 16))
12393 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg,
12394 -1, offset_reloc[0], offset_reloc[1],
12396 expr1.X_add_number = 0;
12400 offset_reloc[0] = BFD_RELOC_LO16;
12401 offset_reloc[1] = BFD_RELOC_UNUSED;
12402 offset_reloc[2] = BFD_RELOC_UNUSED;
12404 if (strcmp (s, "lw") == 0 && op[0] == breg)
12406 ep->X_add_number += 4;
12407 macro_build (ep, s, fmt, op[0] + 1, -1, offset_reloc[0],
12408 offset_reloc[1], offset_reloc[2], breg);
12409 ep->X_add_number -= 4;
12410 macro_build (ep, s, fmt, op[0], -1, offset_reloc[0],
12411 offset_reloc[1], offset_reloc[2], breg);
12415 macro_build (ep, s, fmt, coproc ? op[0] + 1 : op[0], -1,
12416 offset_reloc[0], offset_reloc[1], offset_reloc[2],
12418 ep->X_add_number += 4;
12419 macro_build (ep, s, fmt, coproc ? op[0] : op[0] + 1, -1,
12420 offset_reloc[0], offset_reloc[1], offset_reloc[2],
12426 if (offset_expr.X_op != O_symbol
12427 && offset_expr.X_op != O_constant)
12429 as_bad (_("expression too complex"));
12430 offset_expr.X_op = O_constant;
12433 if (HAVE_32BIT_ADDRESSES
12434 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
12438 sprintf_vma (value, offset_expr.X_add_number);
12439 as_bad (_("number (0x%s) larger than 32 bits"), value);
12442 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
12444 /* If this is a reference to a GP relative symbol, we want
12445 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12446 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
12447 If we have a base register, we use this
12449 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
12450 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
12451 If this is not a GP relative symbol, we want
12452 lui $at,<sym> (BFD_RELOC_HI16_S)
12453 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12454 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12455 If there is a base register, we add it to $at after the
12456 lui instruction. If there is a constant, we always use
12458 if (offset_expr.X_op == O_symbol
12459 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
12460 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
12462 relax_start (offset_expr.X_add_symbol);
12465 tempreg = mips_gp_register;
12469 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12470 AT, breg, mips_gp_register);
12475 /* Itbl support may require additional care here. */
12476 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12477 BFD_RELOC_GPREL16, tempreg);
12478 offset_expr.X_add_number += 4;
12480 /* Set mips_optimize to 2 to avoid inserting an
12482 hold_mips_optimize = mips_optimize;
12484 /* Itbl support may require additional care here. */
12485 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12486 BFD_RELOC_GPREL16, tempreg);
12487 mips_optimize = hold_mips_optimize;
12491 offset_expr.X_add_number -= 4;
12494 if (offset_high_part (offset_expr.X_add_number, 16)
12495 != offset_high_part (offset_expr.X_add_number + 4, 16))
12497 load_address (AT, &offset_expr, &used_at);
12498 offset_expr.X_op = O_constant;
12499 offset_expr.X_add_number = 0;
12502 macro_build_lui (&offset_expr, AT);
12504 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12505 /* Itbl support may require additional care here. */
12506 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12507 BFD_RELOC_LO16, AT);
12508 /* FIXME: How do we handle overflow here? */
12509 offset_expr.X_add_number += 4;
12510 /* Itbl support may require additional care here. */
12511 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12512 BFD_RELOC_LO16, AT);
12513 if (mips_relax.sequence)
12516 else if (!mips_big_got)
12518 /* If this is a reference to an external symbol, we want
12519 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12522 <op> op[0]+1,4($at)
12524 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12526 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12527 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12528 If there is a base register we add it to $at before the
12529 lwc1 instructions. If there is a constant we include it
12530 in the lwc1 instructions. */
12532 expr1.X_add_number = offset_expr.X_add_number;
12533 if (expr1.X_add_number < -0x8000
12534 || expr1.X_add_number >= 0x8000 - 4)
12535 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12536 load_got_offset (AT, &offset_expr);
12539 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12541 /* Set mips_optimize to 2 to avoid inserting an undesired
12543 hold_mips_optimize = mips_optimize;
12546 /* Itbl support may require additional care here. */
12547 relax_start (offset_expr.X_add_symbol);
12548 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
12549 BFD_RELOC_LO16, AT);
12550 expr1.X_add_number += 4;
12551 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
12552 BFD_RELOC_LO16, AT);
12554 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12555 BFD_RELOC_LO16, AT);
12556 offset_expr.X_add_number += 4;
12557 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12558 BFD_RELOC_LO16, AT);
12561 mips_optimize = hold_mips_optimize;
12563 else if (mips_big_got)
12567 /* If this is a reference to an external symbol, we want
12568 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12570 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
12573 <op> op[0]+1,4($at)
12575 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12577 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12578 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12579 If there is a base register we add it to $at before the
12580 lwc1 instructions. If there is a constant we include it
12581 in the lwc1 instructions. */
12583 expr1.X_add_number = offset_expr.X_add_number;
12584 offset_expr.X_add_number = 0;
12585 if (expr1.X_add_number < -0x8000
12586 || expr1.X_add_number >= 0x8000 - 4)
12587 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12588 gpdelay = reg_needs_delay (mips_gp_register);
12589 relax_start (offset_expr.X_add_symbol);
12590 macro_build (&offset_expr, "lui", LUI_FMT,
12591 AT, BFD_RELOC_MIPS_GOT_HI16);
12592 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12593 AT, AT, mips_gp_register);
12594 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
12595 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
12598 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12599 /* Itbl support may require additional care here. */
12600 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
12601 BFD_RELOC_LO16, AT);
12602 expr1.X_add_number += 4;
12604 /* Set mips_optimize to 2 to avoid inserting an undesired
12606 hold_mips_optimize = mips_optimize;
12608 /* Itbl support may require additional care here. */
12609 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
12610 BFD_RELOC_LO16, AT);
12611 mips_optimize = hold_mips_optimize;
12612 expr1.X_add_number -= 4;
12615 offset_expr.X_add_number = expr1.X_add_number;
12617 macro_build (NULL, "nop", "");
12618 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12619 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12622 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12623 /* Itbl support may require additional care here. */
12624 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12625 BFD_RELOC_LO16, AT);
12626 offset_expr.X_add_number += 4;
12628 /* Set mips_optimize to 2 to avoid inserting an undesired
12630 hold_mips_optimize = mips_optimize;
12632 /* Itbl support may require additional care here. */
12633 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12634 BFD_RELOC_LO16, AT);
12635 mips_optimize = hold_mips_optimize;
12649 gas_assert (!mips_opts.micromips);
12654 /* New code added to support COPZ instructions.
12655 This code builds table entries out of the macros in mip_opcodes.
12656 R4000 uses interlocks to handle coproc delays.
12657 Other chips (like the R3000) require nops to be inserted for delays.
12659 FIXME: Currently, we require that the user handle delays.
12660 In order to fill delay slots for non-interlocked chips,
12661 we must have a way to specify delays based on the coprocessor.
12662 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
12663 What are the side-effects of the cop instruction?
12664 What cache support might we have and what are its effects?
12665 Both coprocessor & memory require delays. how long???
12666 What registers are read/set/modified?
12668 If an itbl is provided to interpret cop instructions,
12669 this knowledge can be encoded in the itbl spec. */
12683 gas_assert (!mips_opts.micromips);
12684 /* For now we just do C (same as Cz). The parameter will be
12685 stored in insn_opcode by mips_ip. */
12686 macro_build (NULL, s, "C", (int) ip->insn_opcode);
12690 move_register (op[0], op[1]);
12694 gas_assert (mips_opts.micromips);
12695 gas_assert (mips_opts.insn32);
12696 move_register (micromips_to_32_reg_h_map1[op[0]],
12697 micromips_to_32_reg_m_map[op[1]]);
12698 move_register (micromips_to_32_reg_h_map2[op[0]],
12699 micromips_to_32_reg_n_map[op[2]]);
12704 /* Fall through. */
12706 if (mips_opts.arch == CPU_R5900)
12707 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", op[0], op[1],
12711 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", op[1], op[2]);
12712 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12718 /* Fall through. */
12720 /* The MIPS assembler some times generates shifts and adds. I'm
12721 not trying to be that fancy. GCC should do this for us
12724 load_register (AT, &imm_expr, dbl);
12725 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", op[1], AT);
12726 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12731 /* Fall through. */
12738 /* Fall through. */
12741 start_noreorder ();
12744 load_register (AT, &imm_expr, dbl);
12745 macro_build (NULL, dbl ? "dmult" : "mult", "s,t",
12746 op[1], imm ? AT : op[2]);
12747 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12748 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, op[0], op[0], 31);
12749 macro_build (NULL, "mfhi", MFHL_FMT, AT);
12751 macro_build (NULL, "tne", TRAP_FMT, op[0], AT, 6);
12754 if (mips_opts.micromips)
12755 micromips_label_expr (&label_expr);
12757 label_expr.X_add_number = 8;
12758 macro_build (&label_expr, "beq", "s,t,p", op[0], AT);
12759 macro_build (NULL, "nop", "");
12760 macro_build (NULL, "break", BRK_FMT, 6);
12761 if (mips_opts.micromips)
12762 micromips_add_label ();
12765 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12770 /* Fall through. */
12777 /* Fall through. */
12780 start_noreorder ();
12783 load_register (AT, &imm_expr, dbl);
12784 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
12785 op[1], imm ? AT : op[2]);
12786 macro_build (NULL, "mfhi", MFHL_FMT, AT);
12787 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12789 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
12792 if (mips_opts.micromips)
12793 micromips_label_expr (&label_expr);
12795 label_expr.X_add_number = 8;
12796 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
12797 macro_build (NULL, "nop", "");
12798 macro_build (NULL, "break", BRK_FMT, 6);
12799 if (mips_opts.micromips)
12800 micromips_add_label ();
12806 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12808 if (op[0] == op[1])
12815 macro_build (NULL, "dnegu", "d,w", tempreg, op[2]);
12816 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], tempreg);
12820 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
12821 macro_build (NULL, "dsrlv", "d,t,s", AT, op[1], AT);
12822 macro_build (NULL, "dsllv", "d,t,s", op[0], op[1], op[2]);
12823 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12827 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12829 if (op[0] == op[1])
12836 macro_build (NULL, "negu", "d,w", tempreg, op[2]);
12837 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], tempreg);
12841 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
12842 macro_build (NULL, "srlv", "d,t,s", AT, op[1], AT);
12843 macro_build (NULL, "sllv", "d,t,s", op[0], op[1], op[2]);
12844 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12853 rot = imm_expr.X_add_number & 0x3f;
12854 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12856 rot = (64 - rot) & 0x3f;
12858 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
12860 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
12865 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
12868 l = (rot < 0x20) ? "dsll" : "dsll32";
12869 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
12872 macro_build (NULL, l, SHFT_FMT, AT, op[1], rot);
12873 macro_build (NULL, rr, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12874 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12882 rot = imm_expr.X_add_number & 0x1f;
12883 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12885 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1],
12886 (32 - rot) & 0x1f);
12891 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
12895 macro_build (NULL, "sll", SHFT_FMT, AT, op[1], rot);
12896 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12897 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12902 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12904 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], op[2]);
12908 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
12909 macro_build (NULL, "dsllv", "d,t,s", AT, op[1], AT);
12910 macro_build (NULL, "dsrlv", "d,t,s", op[0], op[1], op[2]);
12911 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12915 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12917 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], op[2]);
12921 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
12922 macro_build (NULL, "sllv", "d,t,s", AT, op[1], AT);
12923 macro_build (NULL, "srlv", "d,t,s", op[0], op[1], op[2]);
12924 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12933 rot = imm_expr.X_add_number & 0x3f;
12934 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12937 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
12939 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
12944 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
12947 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
12948 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
12951 macro_build (NULL, rr, SHFT_FMT, AT, op[1], rot);
12952 macro_build (NULL, l, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12953 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12961 rot = imm_expr.X_add_number & 0x1f;
12962 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12964 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], rot);
12969 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
12973 macro_build (NULL, "srl", SHFT_FMT, AT, op[1], rot);
12974 macro_build (NULL, "sll", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12975 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12981 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[2], BFD_RELOC_LO16);
12982 else if (op[2] == 0)
12983 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
12986 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
12987 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
12992 if (imm_expr.X_add_number == 0)
12994 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
12999 as_warn (_("instruction %s: result is always false"),
13000 ip->insn_mo->name);
13001 move_register (op[0], 0);
13004 if (CPU_HAS_SEQ (mips_opts.arch)
13005 && -512 <= imm_expr.X_add_number
13006 && imm_expr.X_add_number < 512)
13008 macro_build (NULL, "seqi", "t,r,+Q", op[0], op[1],
13009 (int) imm_expr.X_add_number);
13012 if (imm_expr.X_add_number >= 0
13013 && imm_expr.X_add_number < 0x10000)
13014 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], BFD_RELOC_LO16);
13015 else if (imm_expr.X_add_number > -0x8000
13016 && imm_expr.X_add_number < 0)
13018 imm_expr.X_add_number = -imm_expr.X_add_number;
13019 macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu",
13020 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13022 else if (CPU_HAS_SEQ (mips_opts.arch))
13025 load_register (AT, &imm_expr, GPR_SIZE == 64);
13026 macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT);
13031 load_register (AT, &imm_expr, GPR_SIZE == 64);
13032 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
13035 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
13038 case M_SGE: /* X >= Y <==> not (X < Y) */
13044 macro_build (NULL, s, "d,v,t", op[0], op[1], op[2]);
13045 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
13048 case M_SGE_I: /* X >= I <==> not (X < I) */
13050 if (imm_expr.X_add_number >= -0x8000
13051 && imm_expr.X_add_number < 0x8000)
13052 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
13053 op[0], op[1], BFD_RELOC_LO16);
13056 load_register (AT, &imm_expr, GPR_SIZE == 64);
13057 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
13061 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
13064 case M_SGT: /* X > Y <==> Y < X */
13070 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
13073 case M_SGT_I: /* X > I <==> I < X */
13080 load_register (AT, &imm_expr, GPR_SIZE == 64);
13081 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
13084 case M_SLE: /* X <= Y <==> Y >= X <==> not (Y < X) */
13090 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
13091 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
13094 case M_SLE_I: /* X <= I <==> I >= X <==> not (I < X) */
13101 load_register (AT, &imm_expr, GPR_SIZE == 64);
13102 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
13103 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
13107 if (imm_expr.X_add_number >= -0x8000
13108 && imm_expr.X_add_number < 0x8000)
13110 macro_build (&imm_expr, "slti", "t,r,j", op[0], op[1],
13115 load_register (AT, &imm_expr, GPR_SIZE == 64);
13116 macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT);
13120 if (imm_expr.X_add_number >= -0x8000
13121 && imm_expr.X_add_number < 0x8000)
13123 macro_build (&imm_expr, "sltiu", "t,r,j", op[0], op[1],
13128 load_register (AT, &imm_expr, GPR_SIZE == 64);
13129 macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT);
13134 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[2]);
13135 else if (op[2] == 0)
13136 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
13139 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
13140 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
13145 if (imm_expr.X_add_number == 0)
13147 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
13152 as_warn (_("instruction %s: result is always true"),
13153 ip->insn_mo->name);
13154 macro_build (&expr1, GPR_SIZE == 32 ? "addiu" : "daddiu", "t,r,j",
13155 op[0], 0, BFD_RELOC_LO16);
13158 if (CPU_HAS_SEQ (mips_opts.arch)
13159 && -512 <= imm_expr.X_add_number
13160 && imm_expr.X_add_number < 512)
13162 macro_build (NULL, "snei", "t,r,+Q", op[0], op[1],
13163 (int) imm_expr.X_add_number);
13166 if (imm_expr.X_add_number >= 0
13167 && imm_expr.X_add_number < 0x10000)
13169 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1],
13172 else if (imm_expr.X_add_number > -0x8000
13173 && imm_expr.X_add_number < 0)
13175 imm_expr.X_add_number = -imm_expr.X_add_number;
13176 macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu",
13177 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13179 else if (CPU_HAS_SEQ (mips_opts.arch))
13182 load_register (AT, &imm_expr, GPR_SIZE == 64);
13183 macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT);
13188 load_register (AT, &imm_expr, GPR_SIZE == 64);
13189 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
13192 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
13207 if (!mips_opts.micromips)
13209 if (imm_expr.X_add_number > -0x200
13210 && imm_expr.X_add_number <= 0x200)
13212 macro_build (NULL, s, "t,r,.", op[0], op[1],
13213 (int) -imm_expr.X_add_number);
13222 if (imm_expr.X_add_number > -0x8000
13223 && imm_expr.X_add_number <= 0x8000)
13225 imm_expr.X_add_number = -imm_expr.X_add_number;
13226 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13231 load_register (AT, &imm_expr, dbl);
13232 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
13254 load_register (AT, &imm_expr, GPR_SIZE == 64);
13255 macro_build (NULL, s, "s,t", op[0], AT);
13260 gas_assert (!mips_opts.micromips);
13261 gas_assert (mips_opts.isa == ISA_MIPS1);
13265 * Is the double cfc1 instruction a bug in the mips assembler;
13266 * or is there a reason for it?
13268 start_noreorder ();
13269 macro_build (NULL, "cfc1", "t,G", op[2], RA);
13270 macro_build (NULL, "cfc1", "t,G", op[2], RA);
13271 macro_build (NULL, "nop", "");
13272 expr1.X_add_number = 3;
13273 macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16);
13274 expr1.X_add_number = 2;
13275 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
13276 macro_build (NULL, "ctc1", "t,G", AT, RA);
13277 macro_build (NULL, "nop", "");
13278 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
13280 macro_build (NULL, "ctc1", "t,G", op[2], RA);
13281 macro_build (NULL, "nop", "");
13298 offbits = (mips_opts.micromips ? 12 : 16);
13304 offbits = (mips_opts.micromips ? 12 : 16);
13316 offbits = (mips_opts.micromips ? 12 : 16);
13323 offbits = (mips_opts.micromips ? 12 : 16);
13329 large_offset = !small_offset_p (off, align, offbits);
13331 expr1.X_add_number = 0;
13336 if (small_offset_p (0, align, 16))
13337 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1,
13338 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
13341 load_address (tempreg, ep, &used_at);
13343 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
13344 tempreg, tempreg, breg);
13346 offset_reloc[0] = BFD_RELOC_LO16;
13347 offset_reloc[1] = BFD_RELOC_UNUSED;
13348 offset_reloc[2] = BFD_RELOC_UNUSED;
13353 else if (!ust && op[0] == breg)
13364 if (!target_big_endian)
13365 ep->X_add_number += off;
13367 macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg);
13369 macro_build (ep, s, "t,o(b)", tempreg, -1,
13370 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13372 if (!target_big_endian)
13373 ep->X_add_number -= off;
13375 ep->X_add_number += off;
13377 macro_build (NULL, s2, "t,~(b)",
13378 tempreg, (int) ep->X_add_number, breg);
13380 macro_build (ep, s2, "t,o(b)", tempreg, -1,
13381 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13383 /* If necessary, move the result in tempreg to the final destination. */
13384 if (!ust && op[0] != tempreg)
13386 /* Protect second load's delay slot. */
13388 move_register (op[0], tempreg);
13394 if (target_big_endian == ust)
13395 ep->X_add_number += off;
13396 tempreg = ust || large_offset ? op[0] : AT;
13397 macro_build (ep, s, "t,o(b)", tempreg, -1,
13398 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13400 /* For halfword transfers we need a temporary register to shuffle
13401 bytes. Unfortunately for M_USH_A we have none available before
13402 the next store as AT holds the base address. We deal with this
13403 case by clobbering TREG and then restoring it as with ULH. */
13404 tempreg = ust == large_offset ? op[0] : AT;
13406 macro_build (NULL, "srl", SHFT_FMT, tempreg, op[0], 8);
13408 if (target_big_endian == ust)
13409 ep->X_add_number -= off;
13411 ep->X_add_number += off;
13412 macro_build (ep, s2, "t,o(b)", tempreg, -1,
13413 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13415 /* For M_USH_A re-retrieve the LSB. */
13416 if (ust && large_offset)
13418 if (target_big_endian)
13419 ep->X_add_number += off;
13421 ep->X_add_number -= off;
13422 macro_build (&expr1, "lbu", "t,o(b)", AT, -1,
13423 offset_reloc[0], offset_reloc[1], offset_reloc[2], AT);
13425 /* For ULH and M_USH_A OR the LSB in. */
13426 if (!ust || large_offset)
13428 tempreg = !large_offset ? AT : op[0];
13429 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
13430 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13435 /* FIXME: Check if this is one of the itbl macros, since they
13436 are added dynamically. */
13437 as_bad (_("macro %s not implemented yet"), ip->insn_mo->name);
13440 if (!mips_opts.at && used_at)
13441 as_bad (_("macro used $at after \".set noat\""));
13444 /* Implement macros in mips16 mode. */
13447 mips16_macro (struct mips_cl_insn *ip)
13449 const struct mips_operand_array *operands;
13454 const char *s, *s2, *s3;
13455 unsigned int op[MAX_OPERANDS];
13458 mask = ip->insn_mo->mask;
13460 operands = insn_operands (ip);
13461 for (i = 0; i < MAX_OPERANDS; i++)
13462 if (operands->operand[i])
13463 op[i] = insn_extract_operand (ip, operands->operand[i]);
13467 expr1.X_op = O_constant;
13468 expr1.X_op_symbol = NULL;
13469 expr1.X_add_symbol = NULL;
13470 expr1.X_add_number = 1;
13481 /* Fall through. */
13487 /* Fall through. */
13491 start_noreorder ();
13492 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", op[1], op[2]);
13493 expr1.X_add_number = 2;
13494 macro_build (&expr1, "bnez", "x,p", op[2]);
13495 macro_build (NULL, "break", "6", 7);
13497 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
13498 since that causes an overflow. We should do that as well,
13499 but I don't see how to do the comparisons without a temporary
13502 macro_build (NULL, s, "x", op[0]);
13521 start_noreorder ();
13522 macro_build (NULL, s, "0,x,y", op[1], op[2]);
13523 expr1.X_add_number = 2;
13524 macro_build (&expr1, "bnez", "x,p", op[2]);
13525 macro_build (NULL, "break", "6", 7);
13527 macro_build (NULL, s2, "x", op[0]);
13532 /* Fall through. */
13534 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", op[1], op[2]);
13535 macro_build (NULL, "mflo", "x", op[0]);
13543 imm_expr.X_add_number = -imm_expr.X_add_number;
13544 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", op[0], op[1]);
13548 imm_expr.X_add_number = -imm_expr.X_add_number;
13549 macro_build (&imm_expr, "addiu", "x,k", op[0]);
13553 imm_expr.X_add_number = -imm_expr.X_add_number;
13554 macro_build (&imm_expr, "daddiu", "y,j", op[0]);
13576 goto do_reverse_branch;
13580 goto do_reverse_branch;
13592 goto do_reverse_branch;
13603 macro_build (NULL, s, "x,y", op[0], op[1]);
13604 macro_build (&offset_expr, s2, "p");
13631 goto do_addone_branch_i;
13636 goto do_addone_branch_i;
13651 goto do_addone_branch_i;
13657 do_addone_branch_i:
13658 ++imm_expr.X_add_number;
13661 macro_build (&imm_expr, s, s3, op[0]);
13662 macro_build (&offset_expr, s2, "p");
13666 expr1.X_add_number = 0;
13667 macro_build (&expr1, "slti", "x,8", op[1]);
13668 if (op[0] != op[1])
13669 macro_build (NULL, "move", "y,X", op[0], mips16_to_32_reg_map[op[1]]);
13670 expr1.X_add_number = 2;
13671 macro_build (&expr1, "bteqz", "p");
13672 macro_build (NULL, "neg", "x,w", op[0], op[0]);
13677 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
13678 opcode bits in *OPCODE_EXTRA. */
13680 static struct mips_opcode *
13681 mips_lookup_insn (struct hash_control *hash, const char *start,
13682 ssize_t length, unsigned int *opcode_extra)
13684 char *name, *dot, *p;
13685 unsigned int mask, suffix;
13687 struct mips_opcode *insn;
13689 /* Make a copy of the instruction so that we can fiddle with it. */
13690 name = xstrndup (start, length);
13692 /* Look up the instruction as-is. */
13693 insn = (struct mips_opcode *) hash_find (hash, name);
13697 dot = strchr (name, '.');
13700 /* Try to interpret the text after the dot as a VU0 channel suffix. */
13701 p = mips_parse_vu0_channels (dot + 1, &mask);
13702 if (*p == 0 && mask != 0)
13705 insn = (struct mips_opcode *) hash_find (hash, name);
13707 if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0)
13709 *opcode_extra |= mask << mips_vu0_channel_mask.lsb;
13715 if (mips_opts.micromips)
13717 /* See if there's an instruction size override suffix,
13718 either `16' or `32', at the end of the mnemonic proper,
13719 that defines the operation, i.e. before the first `.'
13720 character if any. Strip it and retry. */
13721 opend = dot != NULL ? dot - name : length;
13722 if (opend >= 3 && name[opend - 2] == '1' && name[opend - 1] == '6')
13724 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
13730 memcpy (name + opend - 2, name + opend, length - opend + 1);
13731 insn = (struct mips_opcode *) hash_find (hash, name);
13734 forced_insn_length = suffix;
13746 /* Assemble an instruction into its binary format. If the instruction
13747 is a macro, set imm_expr and offset_expr to the values associated
13748 with "I" and "A" operands respectively. Otherwise store the value
13749 of the relocatable field (if any) in offset_expr. In both cases
13750 set offset_reloc to the relocation operators applied to offset_expr. */
13753 mips_ip (char *str, struct mips_cl_insn *insn)
13755 const struct mips_opcode *first, *past;
13756 struct hash_control *hash;
13759 struct mips_operand_token *tokens;
13760 unsigned int opcode_extra;
13762 if (mips_opts.micromips)
13764 hash = micromips_op_hash;
13765 past = µmips_opcodes[bfd_micromips_num_opcodes];
13770 past = &mips_opcodes[NUMOPCODES];
13772 forced_insn_length = 0;
13775 /* We first try to match an instruction up to a space or to the end. */
13776 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
13779 first = mips_lookup_insn (hash, str, end, &opcode_extra);
13782 set_insn_error (0, _("unrecognized opcode"));
13786 if (strcmp (first->name, "li.s") == 0)
13788 else if (strcmp (first->name, "li.d") == 0)
13792 tokens = mips_parse_arguments (str + end, format);
13796 if (!match_insns (insn, first, past, tokens, opcode_extra, FALSE)
13797 && !match_insns (insn, first, past, tokens, opcode_extra, TRUE))
13798 set_insn_error (0, _("invalid operands"));
13800 obstack_free (&mips_operand_tokens, tokens);
13803 /* As for mips_ip, but used when assembling MIPS16 code.
13804 Also set forced_insn_length to the resulting instruction size in
13805 bytes if the user explicitly requested a small or extended instruction. */
13808 mips16_ip (char *str, struct mips_cl_insn *insn)
13811 struct mips_opcode *first;
13812 struct mips_operand_token *tokens;
13814 forced_insn_length = 0;
13816 for (s = str; ISLOWER (*s); ++s)
13830 if (s[1] == 't' && s[2] == ' ')
13832 forced_insn_length = 2;
13836 else if (s[1] == 'e' && s[2] == ' ')
13838 forced_insn_length = 4;
13842 /* Fall through. */
13844 set_insn_error (0, _("unrecognized opcode"));
13848 if (mips_opts.noautoextend && !forced_insn_length)
13849 forced_insn_length = 2;
13852 first = (struct mips_opcode *) hash_find (mips16_op_hash, str);
13857 set_insn_error (0, _("unrecognized opcode"));
13861 tokens = mips_parse_arguments (s, 0);
13865 if (!match_mips16_insns (insn, first, tokens))
13866 set_insn_error (0, _("invalid operands"));
13868 obstack_free (&mips_operand_tokens, tokens);
13871 /* Marshal immediate value VAL for an extended MIPS16 instruction.
13872 NBITS is the number of significant bits in VAL. */
13874 static unsigned long
13875 mips16_immed_extend (offsetT val, unsigned int nbits)
13880 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
13883 else if (nbits == 15)
13885 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
13890 extval = ((val & 0x1f) << 6) | (val & 0x20);
13893 return (extval << 16) | val;
13896 /* Like decode_mips16_operand, but require the operand to be defined and
13897 require it to be an integer. */
13899 static const struct mips_int_operand *
13900 mips16_immed_operand (int type, bfd_boolean extended_p)
13902 const struct mips_operand *operand;
13904 operand = decode_mips16_operand (type, extended_p);
13905 if (!operand || (operand->type != OP_INT && operand->type != OP_PCREL))
13907 return (const struct mips_int_operand *) operand;
13910 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
13913 mips16_immed_in_range_p (const struct mips_int_operand *operand,
13914 bfd_reloc_code_real_type reloc, offsetT sval)
13916 int min_val, max_val;
13918 min_val = mips_int_operand_min (operand);
13919 max_val = mips_int_operand_max (operand);
13920 if (reloc != BFD_RELOC_UNUSED)
13923 sval = SEXT_16BIT (sval);
13928 return (sval >= min_val
13930 && (sval & ((1 << operand->shift) - 1)) == 0);
13933 /* Install immediate value VAL into MIPS16 instruction *INSN,
13934 extending it if necessary. The instruction in *INSN may
13935 already be extended.
13937 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
13938 if none. In the former case, VAL is a 16-bit number with no
13939 defined signedness.
13941 TYPE is the type of the immediate field. USER_INSN_LENGTH
13942 is the length that the user requested, or 0 if none. */
13945 mips16_immed (const char *file, unsigned int line, int type,
13946 bfd_reloc_code_real_type reloc, offsetT val,
13947 unsigned int user_insn_length, unsigned long *insn)
13949 const struct mips_int_operand *operand;
13950 unsigned int uval, length;
13952 operand = mips16_immed_operand (type, FALSE);
13953 if (!mips16_immed_in_range_p (operand, reloc, val))
13955 /* We need an extended instruction. */
13956 if (user_insn_length == 2)
13957 as_bad_where (file, line, _("invalid unextended operand value"));
13959 *insn |= MIPS16_EXTEND;
13961 else if (user_insn_length == 4)
13963 /* The operand doesn't force an unextended instruction to be extended.
13964 Warn if the user wanted an extended instruction anyway. */
13965 *insn |= MIPS16_EXTEND;
13966 as_warn_where (file, line,
13967 _("extended operand requested but not required"));
13970 length = mips16_opcode_length (*insn);
13973 operand = mips16_immed_operand (type, TRUE);
13974 if (!mips16_immed_in_range_p (operand, reloc, val))
13975 as_bad_where (file, line,
13976 _("operand value out of range for instruction"));
13978 uval = ((unsigned int) val >> operand->shift) - operand->bias;
13980 *insn = mips_insert_operand (&operand->root, *insn, uval);
13982 *insn |= mips16_immed_extend (uval, operand->root.size);
13985 struct percent_op_match
13988 bfd_reloc_code_real_type reloc;
13991 static const struct percent_op_match mips_percent_op[] =
13993 {"%lo", BFD_RELOC_LO16},
13994 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
13995 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
13996 {"%call16", BFD_RELOC_MIPS_CALL16},
13997 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
13998 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
13999 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
14000 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
14001 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
14002 {"%got", BFD_RELOC_MIPS_GOT16},
14003 {"%gp_rel", BFD_RELOC_GPREL16},
14004 {"%half", BFD_RELOC_16},
14005 {"%highest", BFD_RELOC_MIPS_HIGHEST},
14006 {"%higher", BFD_RELOC_MIPS_HIGHER},
14007 {"%neg", BFD_RELOC_MIPS_SUB},
14008 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
14009 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
14010 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
14011 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
14012 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
14013 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
14014 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
14015 {"%hi", BFD_RELOC_HI16_S},
14016 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL},
14017 {"%pcrel_lo", BFD_RELOC_LO16_PCREL}
14020 static const struct percent_op_match mips16_percent_op[] =
14022 {"%lo", BFD_RELOC_MIPS16_LO16},
14023 {"%gprel", BFD_RELOC_MIPS16_GPREL},
14024 {"%got", BFD_RELOC_MIPS16_GOT16},
14025 {"%call16", BFD_RELOC_MIPS16_CALL16},
14026 {"%hi", BFD_RELOC_MIPS16_HI16_S},
14027 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
14028 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
14029 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
14030 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
14031 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
14032 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
14033 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
14037 /* Return true if *STR points to a relocation operator. When returning true,
14038 move *STR over the operator and store its relocation code in *RELOC.
14039 Leave both *STR and *RELOC alone when returning false. */
14042 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
14044 const struct percent_op_match *percent_op;
14047 if (mips_opts.mips16)
14049 percent_op = mips16_percent_op;
14050 limit = ARRAY_SIZE (mips16_percent_op);
14054 percent_op = mips_percent_op;
14055 limit = ARRAY_SIZE (mips_percent_op);
14058 for (i = 0; i < limit; i++)
14059 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
14061 int len = strlen (percent_op[i].str);
14063 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
14066 *str += strlen (percent_op[i].str);
14067 *reloc = percent_op[i].reloc;
14069 /* Check whether the output BFD supports this relocation.
14070 If not, issue an error and fall back on something safe. */
14071 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
14073 as_bad (_("relocation %s isn't supported by the current ABI"),
14074 percent_op[i].str);
14075 *reloc = BFD_RELOC_UNUSED;
14083 /* Parse string STR as a 16-bit relocatable operand. Store the
14084 expression in *EP and the relocations in the array starting
14085 at RELOC. Return the number of relocation operators used.
14087 On exit, EXPR_END points to the first character after the expression. */
14090 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
14093 bfd_reloc_code_real_type reversed_reloc[3];
14094 size_t reloc_index, i;
14095 int crux_depth, str_depth;
14098 /* Search for the start of the main expression, recoding relocations
14099 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14100 of the main expression and with CRUX_DEPTH containing the number
14101 of open brackets at that point. */
14108 crux_depth = str_depth;
14110 /* Skip over whitespace and brackets, keeping count of the number
14112 while (*str == ' ' || *str == '\t' || *str == '(')
14117 && reloc_index < (HAVE_NEWABI ? 3 : 1)
14118 && parse_relocation (&str, &reversed_reloc[reloc_index]));
14120 my_getExpression (ep, crux);
14123 /* Match every open bracket. */
14124 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
14128 if (crux_depth > 0)
14129 as_bad (_("unclosed '('"));
14133 if (reloc_index != 0)
14135 prev_reloc_op_frag = frag_now;
14136 for (i = 0; i < reloc_index; i++)
14137 reloc[i] = reversed_reloc[reloc_index - 1 - i];
14140 return reloc_index;
14144 my_getExpression (expressionS *ep, char *str)
14148 save_in = input_line_pointer;
14149 input_line_pointer = str;
14151 expr_end = input_line_pointer;
14152 input_line_pointer = save_in;
14156 md_atof (int type, char *litP, int *sizeP)
14158 return ieee_md_atof (type, litP, sizeP, target_big_endian);
14162 md_number_to_chars (char *buf, valueT val, int n)
14164 if (target_big_endian)
14165 number_to_chars_bigendian (buf, val, n);
14167 number_to_chars_littleendian (buf, val, n);
14170 static int support_64bit_objects(void)
14172 const char **list, **l;
14175 list = bfd_target_list ();
14176 for (l = list; *l != NULL; l++)
14177 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
14178 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
14180 yes = (*l != NULL);
14185 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14186 NEW_VALUE. Warn if another value was already specified. Note:
14187 we have to defer parsing the -march and -mtune arguments in order
14188 to handle 'from-abi' correctly, since the ABI might be specified
14189 in a later argument. */
14192 mips_set_option_string (const char **string_ptr, const char *new_value)
14194 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
14195 as_warn (_("a different %s was already specified, is now %s"),
14196 string_ptr == &mips_arch_string ? "-march" : "-mtune",
14199 *string_ptr = new_value;
14203 md_parse_option (int c, const char *arg)
14207 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
14208 if (c == mips_ases[i].option_on || c == mips_ases[i].option_off)
14210 file_ase_explicit |= mips_set_ase (&mips_ases[i], &file_mips_opts,
14211 c == mips_ases[i].option_on);
14217 case OPTION_CONSTRUCT_FLOATS:
14218 mips_disable_float_construction = 0;
14221 case OPTION_NO_CONSTRUCT_FLOATS:
14222 mips_disable_float_construction = 1;
14234 target_big_endian = 1;
14238 target_big_endian = 0;
14244 else if (arg[0] == '0')
14246 else if (arg[0] == '1')
14256 mips_debug = atoi (arg);
14260 file_mips_opts.isa = ISA_MIPS1;
14264 file_mips_opts.isa = ISA_MIPS2;
14268 file_mips_opts.isa = ISA_MIPS3;
14272 file_mips_opts.isa = ISA_MIPS4;
14276 file_mips_opts.isa = ISA_MIPS5;
14279 case OPTION_MIPS32:
14280 file_mips_opts.isa = ISA_MIPS32;
14283 case OPTION_MIPS32R2:
14284 file_mips_opts.isa = ISA_MIPS32R2;
14287 case OPTION_MIPS32R3:
14288 file_mips_opts.isa = ISA_MIPS32R3;
14291 case OPTION_MIPS32R5:
14292 file_mips_opts.isa = ISA_MIPS32R5;
14295 case OPTION_MIPS32R6:
14296 file_mips_opts.isa = ISA_MIPS32R6;
14299 case OPTION_MIPS64R2:
14300 file_mips_opts.isa = ISA_MIPS64R2;
14303 case OPTION_MIPS64R3:
14304 file_mips_opts.isa = ISA_MIPS64R3;
14307 case OPTION_MIPS64R5:
14308 file_mips_opts.isa = ISA_MIPS64R5;
14311 case OPTION_MIPS64R6:
14312 file_mips_opts.isa = ISA_MIPS64R6;
14315 case OPTION_MIPS64:
14316 file_mips_opts.isa = ISA_MIPS64;
14320 mips_set_option_string (&mips_tune_string, arg);
14324 mips_set_option_string (&mips_arch_string, arg);
14328 mips_set_option_string (&mips_arch_string, "4650");
14329 mips_set_option_string (&mips_tune_string, "4650");
14332 case OPTION_NO_M4650:
14336 mips_set_option_string (&mips_arch_string, "4010");
14337 mips_set_option_string (&mips_tune_string, "4010");
14340 case OPTION_NO_M4010:
14344 mips_set_option_string (&mips_arch_string, "4100");
14345 mips_set_option_string (&mips_tune_string, "4100");
14348 case OPTION_NO_M4100:
14352 mips_set_option_string (&mips_arch_string, "3900");
14353 mips_set_option_string (&mips_tune_string, "3900");
14356 case OPTION_NO_M3900:
14359 case OPTION_MICROMIPS:
14360 if (file_mips_opts.mips16 == 1)
14362 as_bad (_("-mmicromips cannot be used with -mips16"));
14365 file_mips_opts.micromips = 1;
14366 mips_no_prev_insn ();
14369 case OPTION_NO_MICROMIPS:
14370 file_mips_opts.micromips = 0;
14371 mips_no_prev_insn ();
14374 case OPTION_MIPS16:
14375 if (file_mips_opts.micromips == 1)
14377 as_bad (_("-mips16 cannot be used with -micromips"));
14380 file_mips_opts.mips16 = 1;
14381 mips_no_prev_insn ();
14384 case OPTION_NO_MIPS16:
14385 file_mips_opts.mips16 = 0;
14386 mips_no_prev_insn ();
14389 case OPTION_FIX_24K:
14393 case OPTION_NO_FIX_24K:
14397 case OPTION_FIX_RM7000:
14398 mips_fix_rm7000 = 1;
14401 case OPTION_NO_FIX_RM7000:
14402 mips_fix_rm7000 = 0;
14405 case OPTION_FIX_LOONGSON2F_JUMP:
14406 mips_fix_loongson2f_jump = TRUE;
14409 case OPTION_NO_FIX_LOONGSON2F_JUMP:
14410 mips_fix_loongson2f_jump = FALSE;
14413 case OPTION_FIX_LOONGSON2F_NOP:
14414 mips_fix_loongson2f_nop = TRUE;
14417 case OPTION_NO_FIX_LOONGSON2F_NOP:
14418 mips_fix_loongson2f_nop = FALSE;
14421 case OPTION_FIX_VR4120:
14422 mips_fix_vr4120 = 1;
14425 case OPTION_NO_FIX_VR4120:
14426 mips_fix_vr4120 = 0;
14429 case OPTION_FIX_VR4130:
14430 mips_fix_vr4130 = 1;
14433 case OPTION_NO_FIX_VR4130:
14434 mips_fix_vr4130 = 0;
14437 case OPTION_FIX_CN63XXP1:
14438 mips_fix_cn63xxp1 = TRUE;
14441 case OPTION_NO_FIX_CN63XXP1:
14442 mips_fix_cn63xxp1 = FALSE;
14445 case OPTION_RELAX_BRANCH:
14446 mips_relax_branch = 1;
14449 case OPTION_NO_RELAX_BRANCH:
14450 mips_relax_branch = 0;
14453 case OPTION_INSN32:
14454 file_mips_opts.insn32 = TRUE;
14457 case OPTION_NO_INSN32:
14458 file_mips_opts.insn32 = FALSE;
14461 case OPTION_MSHARED:
14462 mips_in_shared = TRUE;
14465 case OPTION_MNO_SHARED:
14466 mips_in_shared = FALSE;
14469 case OPTION_MSYM32:
14470 file_mips_opts.sym32 = TRUE;
14473 case OPTION_MNO_SYM32:
14474 file_mips_opts.sym32 = FALSE;
14477 /* When generating ELF code, we permit -KPIC and -call_shared to
14478 select SVR4_PIC, and -non_shared to select no PIC. This is
14479 intended to be compatible with Irix 5. */
14480 case OPTION_CALL_SHARED:
14481 mips_pic = SVR4_PIC;
14482 mips_abicalls = TRUE;
14485 case OPTION_CALL_NONPIC:
14487 mips_abicalls = TRUE;
14490 case OPTION_NON_SHARED:
14492 mips_abicalls = FALSE;
14495 /* The -xgot option tells the assembler to use 32 bit offsets
14496 when accessing the got in SVR4_PIC mode. It is for Irix
14503 g_switch_value = atoi (arg);
14507 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14510 mips_abi = O32_ABI;
14514 mips_abi = N32_ABI;
14518 mips_abi = N64_ABI;
14519 if (!support_64bit_objects())
14520 as_fatal (_("no compiled in support for 64 bit object file format"));
14524 file_mips_opts.gp = 32;
14528 file_mips_opts.gp = 64;
14532 file_mips_opts.fp = 32;
14536 file_mips_opts.fp = 0;
14540 file_mips_opts.fp = 64;
14543 case OPTION_ODD_SPREG:
14544 file_mips_opts.oddspreg = 1;
14547 case OPTION_NO_ODD_SPREG:
14548 file_mips_opts.oddspreg = 0;
14551 case OPTION_SINGLE_FLOAT:
14552 file_mips_opts.single_float = 1;
14555 case OPTION_DOUBLE_FLOAT:
14556 file_mips_opts.single_float = 0;
14559 case OPTION_SOFT_FLOAT:
14560 file_mips_opts.soft_float = 1;
14563 case OPTION_HARD_FLOAT:
14564 file_mips_opts.soft_float = 0;
14568 if (strcmp (arg, "32") == 0)
14569 mips_abi = O32_ABI;
14570 else if (strcmp (arg, "o64") == 0)
14571 mips_abi = O64_ABI;
14572 else if (strcmp (arg, "n32") == 0)
14573 mips_abi = N32_ABI;
14574 else if (strcmp (arg, "64") == 0)
14576 mips_abi = N64_ABI;
14577 if (! support_64bit_objects())
14578 as_fatal (_("no compiled in support for 64 bit object file "
14581 else if (strcmp (arg, "eabi") == 0)
14582 mips_abi = EABI_ABI;
14585 as_fatal (_("invalid abi -mabi=%s"), arg);
14590 case OPTION_M7000_HILO_FIX:
14591 mips_7000_hilo_fix = TRUE;
14594 case OPTION_MNO_7000_HILO_FIX:
14595 mips_7000_hilo_fix = FALSE;
14598 case OPTION_MDEBUG:
14599 mips_flag_mdebug = TRUE;
14602 case OPTION_NO_MDEBUG:
14603 mips_flag_mdebug = FALSE;
14607 mips_flag_pdr = TRUE;
14610 case OPTION_NO_PDR:
14611 mips_flag_pdr = FALSE;
14614 case OPTION_MVXWORKS_PIC:
14615 mips_pic = VXWORKS_PIC;
14619 if (strcmp (arg, "2008") == 0)
14621 else if (strcmp (arg, "legacy") == 0)
14625 as_fatal (_("invalid NaN setting -mnan=%s"), arg);
14634 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
14639 /* Set up globals to tune for the ISA or processor described by INFO. */
14642 mips_set_tune (const struct mips_cpu_info *info)
14645 mips_tune = info->cpu;
14650 mips_after_parse_args (void)
14652 const struct mips_cpu_info *arch_info = 0;
14653 const struct mips_cpu_info *tune_info = 0;
14655 /* GP relative stuff not working for PE */
14656 if (strncmp (TARGET_OS, "pe", 2) == 0)
14658 if (g_switch_seen && g_switch_value != 0)
14659 as_bad (_("-G not supported in this configuration"));
14660 g_switch_value = 0;
14663 if (mips_abi == NO_ABI)
14664 mips_abi = MIPS_DEFAULT_ABI;
14666 /* The following code determines the architecture.
14667 Similar code was added to GCC 3.3 (see override_options() in
14668 config/mips/mips.c). The GAS and GCC code should be kept in sync
14669 as much as possible. */
14671 if (mips_arch_string != 0)
14672 arch_info = mips_parse_cpu ("-march", mips_arch_string);
14674 if (file_mips_opts.isa != ISA_UNKNOWN)
14676 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
14677 ISA level specified by -mipsN, while arch_info->isa contains
14678 the -march selection (if any). */
14679 if (arch_info != 0)
14681 /* -march takes precedence over -mipsN, since it is more descriptive.
14682 There's no harm in specifying both as long as the ISA levels
14684 if (file_mips_opts.isa != arch_info->isa)
14685 as_bad (_("-%s conflicts with the other architecture options,"
14686 " which imply -%s"),
14687 mips_cpu_info_from_isa (file_mips_opts.isa)->name,
14688 mips_cpu_info_from_isa (arch_info->isa)->name);
14691 arch_info = mips_cpu_info_from_isa (file_mips_opts.isa);
14694 if (arch_info == 0)
14696 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
14697 gas_assert (arch_info);
14700 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
14701 as_bad (_("-march=%s is not compatible with the selected ABI"),
14704 file_mips_opts.arch = arch_info->cpu;
14705 file_mips_opts.isa = arch_info->isa;
14707 /* Set up initial mips_opts state. */
14708 mips_opts = file_mips_opts;
14710 /* The register size inference code is now placed in
14711 file_mips_check_options. */
14713 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
14715 if (mips_tune_string != 0)
14716 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
14718 if (tune_info == 0)
14719 mips_set_tune (arch_info);
14721 mips_set_tune (tune_info);
14723 if (mips_flag_mdebug < 0)
14724 mips_flag_mdebug = 0;
14728 mips_init_after_args (void)
14730 /* initialize opcodes */
14731 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
14732 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
14736 md_pcrel_from (fixS *fixP)
14738 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
14739 switch (fixP->fx_r_type)
14741 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
14742 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
14743 /* Return the address of the delay slot. */
14746 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
14747 case BFD_RELOC_MICROMIPS_JMP:
14748 case BFD_RELOC_MIPS16_16_PCREL_S1:
14749 case BFD_RELOC_16_PCREL_S2:
14750 case BFD_RELOC_MIPS_21_PCREL_S2:
14751 case BFD_RELOC_MIPS_26_PCREL_S2:
14752 case BFD_RELOC_MIPS_JMP:
14753 /* Return the address of the delay slot. */
14756 case BFD_RELOC_MIPS_18_PCREL_S3:
14757 /* Return the aligned address of the doubleword containing
14758 the instruction. */
14766 /* This is called before the symbol table is processed. In order to
14767 work with gcc when using mips-tfile, we must keep all local labels.
14768 However, in other cases, we want to discard them. If we were
14769 called with -g, but we didn't see any debugging information, it may
14770 mean that gcc is smuggling debugging information through to
14771 mips-tfile, in which case we must generate all local labels. */
14774 mips_frob_file_before_adjust (void)
14776 #ifndef NO_ECOFF_DEBUGGING
14777 if (ECOFF_DEBUGGING
14779 && ! ecoff_debugging_seen)
14780 flag_keep_locals = 1;
14784 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
14785 the corresponding LO16 reloc. This is called before md_apply_fix and
14786 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
14787 relocation operators.
14789 For our purposes, a %lo() expression matches a %got() or %hi()
14792 (a) it refers to the same symbol; and
14793 (b) the offset applied in the %lo() expression is no lower than
14794 the offset applied in the %got() or %hi().
14796 (b) allows us to cope with code like:
14799 lh $4,%lo(foo+2)($4)
14801 ...which is legal on RELA targets, and has a well-defined behaviour
14802 if the user knows that adding 2 to "foo" will not induce a carry to
14805 When several %lo()s match a particular %got() or %hi(), we use the
14806 following rules to distinguish them:
14808 (1) %lo()s with smaller offsets are a better match than %lo()s with
14811 (2) %lo()s with no matching %got() or %hi() are better than those
14812 that already have a matching %got() or %hi().
14814 (3) later %lo()s are better than earlier %lo()s.
14816 These rules are applied in order.
14818 (1) means, among other things, that %lo()s with identical offsets are
14819 chosen if they exist.
14821 (2) means that we won't associate several high-part relocations with
14822 the same low-part relocation unless there's no alternative. Having
14823 several high parts for the same low part is a GNU extension; this rule
14824 allows careful users to avoid it.
14826 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
14827 with the last high-part relocation being at the front of the list.
14828 It therefore makes sense to choose the last matching low-part
14829 relocation, all other things being equal. It's also easier
14830 to code that way. */
14833 mips_frob_file (void)
14835 struct mips_hi_fixup *l;
14836 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
14838 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
14840 segment_info_type *seginfo;
14841 bfd_boolean matched_lo_p;
14842 fixS **hi_pos, **lo_pos, **pos;
14844 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
14846 /* If a GOT16 relocation turns out to be against a global symbol,
14847 there isn't supposed to be a matching LO. Ignore %gots against
14848 constants; we'll report an error for those later. */
14849 if (got16_reloc_p (l->fixp->fx_r_type)
14850 && !(l->fixp->fx_addsy
14851 && pic_need_relax (l->fixp->fx_addsy, l->seg)))
14854 /* Check quickly whether the next fixup happens to be a matching %lo. */
14855 if (fixup_has_matching_lo_p (l->fixp))
14858 seginfo = seg_info (l->seg);
14860 /* Set HI_POS to the position of this relocation in the chain.
14861 Set LO_POS to the position of the chosen low-part relocation.
14862 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
14863 relocation that matches an immediately-preceding high-part
14867 matched_lo_p = FALSE;
14868 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
14870 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
14872 if (*pos == l->fixp)
14875 if ((*pos)->fx_r_type == looking_for_rtype
14876 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
14877 && (*pos)->fx_offset >= l->fixp->fx_offset
14879 || (*pos)->fx_offset < (*lo_pos)->fx_offset
14881 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
14884 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
14885 && fixup_has_matching_lo_p (*pos));
14888 /* If we found a match, remove the high-part relocation from its
14889 current position and insert it before the low-part relocation.
14890 Make the offsets match so that fixup_has_matching_lo_p()
14893 We don't warn about unmatched high-part relocations since some
14894 versions of gcc have been known to emit dead "lui ...%hi(...)"
14896 if (lo_pos != NULL)
14898 l->fixp->fx_offset = (*lo_pos)->fx_offset;
14899 if (l->fixp->fx_next != *lo_pos)
14901 *hi_pos = l->fixp->fx_next;
14902 l->fixp->fx_next = *lo_pos;
14910 mips_force_relocation (fixS *fixp)
14912 if (generic_force_reloc (fixp))
14915 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
14916 so that the linker relaxation can update targets. */
14917 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
14918 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
14919 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
14922 /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2
14923 and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and
14924 microMIPS symbols so that we can do cross-mode branch diagnostics
14925 and BAL to JALX conversion by the linker. */
14926 if ((fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
14927 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
14928 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2)
14930 && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp->fx_addsy)))
14933 /* We want all PC-relative relocations to be kept for R6 relaxation. */
14934 if (ISA_IS_R6 (file_mips_opts.isa)
14935 && (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
14936 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
14937 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2
14938 || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3
14939 || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2
14940 || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL
14941 || fixp->fx_r_type == BFD_RELOC_LO16_PCREL))
14947 /* Implement TC_FORCE_RELOCATION_ABS. */
14950 mips_force_relocation_abs (fixS *fixp)
14952 if (generic_force_reloc (fixp))
14955 /* These relocations do not have enough bits in the in-place addend
14956 to hold an arbitrary absolute section's offset. */
14957 if (HAVE_IN_PLACE_ADDENDS && limited_pcrel_reloc_p (fixp->fx_r_type))
14963 /* Read the instruction associated with RELOC from BUF. */
14965 static unsigned int
14966 read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc)
14968 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
14969 return read_compressed_insn (buf, 4);
14971 return read_insn (buf);
14974 /* Write instruction INSN to BUF, given that it has been relocated
14978 write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc,
14979 unsigned long insn)
14981 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
14982 write_compressed_insn (buf, insn, 4);
14984 write_insn (buf, insn);
14987 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
14988 to a symbol in another ISA mode, which cannot be converted to JALX. */
14991 fix_bad_cross_mode_jump_p (fixS *fixP)
14993 unsigned long opcode;
14997 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
15000 other = S_GET_OTHER (fixP->fx_addsy);
15001 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15002 opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26;
15003 switch (fixP->fx_r_type)
15005 case BFD_RELOC_MIPS_JMP:
15006 return opcode != 0x1d && opcode != 0x03 && ELF_ST_IS_COMPRESSED (other);
15007 case BFD_RELOC_MICROMIPS_JMP:
15008 return opcode != 0x3c && opcode != 0x3d && !ELF_ST_IS_MICROMIPS (other);
15014 /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX
15015 jump to a symbol in the same ISA mode. */
15018 fix_bad_same_mode_jalx_p (fixS *fixP)
15020 unsigned long opcode;
15024 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
15027 other = S_GET_OTHER (fixP->fx_addsy);
15028 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15029 opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26;
15030 switch (fixP->fx_r_type)
15032 case BFD_RELOC_MIPS_JMP:
15033 return opcode == 0x1d && !ELF_ST_IS_COMPRESSED (other);
15034 case BFD_RELOC_MIPS16_JMP:
15035 return opcode == 0x07 && ELF_ST_IS_COMPRESSED (other);
15036 case BFD_RELOC_MICROMIPS_JMP:
15037 return opcode == 0x3c && ELF_ST_IS_COMPRESSED (other);
15043 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15044 to a symbol whose value plus addend is not aligned according to the
15045 ultimate (after linker relaxation) jump instruction's immediate field
15046 requirement, either to (1 << SHIFT), or, for jumps from microMIPS to
15047 regular MIPS code, to (1 << 2). */
15050 fix_bad_misaligned_jump_p (fixS *fixP, int shift)
15052 bfd_boolean micro_to_mips_p;
15056 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
15059 other = S_GET_OTHER (fixP->fx_addsy);
15060 val = S_GET_VALUE (fixP->fx_addsy) | ELF_ST_IS_COMPRESSED (other);
15061 val += fixP->fx_offset;
15062 micro_to_mips_p = (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP
15063 && !ELF_ST_IS_MICROMIPS (other));
15064 return ((val & ((1 << (micro_to_mips_p ? 2 : shift)) - 1))
15065 != ELF_ST_IS_COMPRESSED (other));
15068 /* Return TRUE if the instruction pointed to by FIXP is an invalid branch
15069 to a symbol whose annotation indicates another ISA mode. For absolute
15070 symbols check the ISA bit instead.
15072 We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS
15073 symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular
15074 MIPS symbols and associated with BAL instructions as these instructions
15075 may be be converted to JALX by the linker. */
15078 fix_bad_cross_mode_branch_p (fixS *fixP)
15080 bfd_boolean absolute_p;
15081 unsigned long opcode;
15087 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
15090 symsec = S_GET_SEGMENT (fixP->fx_addsy);
15091 absolute_p = bfd_is_abs_section (symsec);
15093 val = S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset;
15094 other = S_GET_OTHER (fixP->fx_addsy);
15096 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15097 opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 16;
15098 switch (fixP->fx_r_type)
15100 case BFD_RELOC_16_PCREL_S2:
15101 return ((absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other))
15102 && opcode != 0x0411);
15103 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15104 return ((absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other))
15105 && opcode != 0x4060);
15106 case BFD_RELOC_MIPS_21_PCREL_S2:
15107 case BFD_RELOC_MIPS_26_PCREL_S2:
15108 return absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other);
15109 case BFD_RELOC_MIPS16_16_PCREL_S1:
15110 return absolute_p ? !(val & 1) : !ELF_ST_IS_MIPS16 (other);
15111 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15112 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15113 return absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other);
15119 /* Return TRUE if the symbol plus addend associated with a regular MIPS
15120 branch instruction pointed to by FIXP is not aligned according to the
15121 branch instruction's immediate field requirement. We need the addend
15122 to preserve the ISA bit and also the sum must not have bit 2 set. We
15123 must explicitly OR in the ISA bit from symbol annotation as the bit
15124 won't be set in the symbol's value then. */
15127 fix_bad_misaligned_branch_p (fixS *fixP)
15129 bfd_boolean absolute_p;
15136 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
15139 symsec = S_GET_SEGMENT (fixP->fx_addsy);
15140 absolute_p = bfd_is_abs_section (symsec);
15142 val = S_GET_VALUE (fixP->fx_addsy);
15143 other = S_GET_OTHER (fixP->fx_addsy);
15144 off = fixP->fx_offset;
15146 isa_bit = absolute_p ? (val + off) & 1 : ELF_ST_IS_COMPRESSED (other);
15147 val |= ELF_ST_IS_COMPRESSED (other);
15149 return (val & 0x3) != isa_bit;
15152 /* Make the necessary checks on a regular MIPS branch pointed to by FIXP
15153 and its calculated value VAL. */
15156 fix_validate_branch (fixS *fixP, valueT val)
15158 if (fixP->fx_done && (val & 0x3) != 0)
15159 as_bad_where (fixP->fx_file, fixP->fx_line,
15160 _("branch to misaligned address (0x%lx)"),
15161 (long) (val + md_pcrel_from (fixP)));
15162 else if (fix_bad_cross_mode_branch_p (fixP))
15163 as_bad_where (fixP->fx_file, fixP->fx_line,
15164 _("branch to a symbol in another ISA mode"));
15165 else if (fix_bad_misaligned_branch_p (fixP))
15166 as_bad_where (fixP->fx_file, fixP->fx_line,
15167 _("branch to misaligned address (0x%lx)"),
15168 (long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset));
15169 else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x3) != 0)
15170 as_bad_where (fixP->fx_file, fixP->fx_line,
15171 _("cannot encode misaligned addend "
15172 "in the relocatable field (0x%lx)"),
15173 (long) fixP->fx_offset);
15176 /* Apply a fixup to the object file. */
15179 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
15182 unsigned long insn;
15183 reloc_howto_type *howto;
15185 if (fixP->fx_pcrel)
15186 switch (fixP->fx_r_type)
15188 case BFD_RELOC_16_PCREL_S2:
15189 case BFD_RELOC_MIPS16_16_PCREL_S1:
15190 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15191 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15192 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15193 case BFD_RELOC_32_PCREL:
15194 case BFD_RELOC_MIPS_21_PCREL_S2:
15195 case BFD_RELOC_MIPS_26_PCREL_S2:
15196 case BFD_RELOC_MIPS_18_PCREL_S3:
15197 case BFD_RELOC_MIPS_19_PCREL_S2:
15198 case BFD_RELOC_HI16_S_PCREL:
15199 case BFD_RELOC_LO16_PCREL:
15203 fixP->fx_r_type = BFD_RELOC_32_PCREL;
15207 as_bad_where (fixP->fx_file, fixP->fx_line,
15208 _("PC-relative reference to a different section"));
15212 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
15213 that have no MIPS ELF equivalent. */
15214 if (fixP->fx_r_type != BFD_RELOC_8)
15216 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
15221 gas_assert (fixP->fx_size == 2
15222 || fixP->fx_size == 4
15223 || fixP->fx_r_type == BFD_RELOC_8
15224 || fixP->fx_r_type == BFD_RELOC_16
15225 || fixP->fx_r_type == BFD_RELOC_64
15226 || fixP->fx_r_type == BFD_RELOC_CTOR
15227 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
15228 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
15229 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
15230 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
15231 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64
15232 || fixP->fx_r_type == BFD_RELOC_NONE);
15234 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15236 /* Don't treat parts of a composite relocation as done. There are two
15239 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15240 should nevertheless be emitted if the first part is.
15242 (2) In normal usage, composite relocations are never assembly-time
15243 constants. The easiest way of dealing with the pathological
15244 exceptions is to generate a relocation against STN_UNDEF and
15245 leave everything up to the linker. */
15246 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
15249 switch (fixP->fx_r_type)
15251 case BFD_RELOC_MIPS_TLS_GD:
15252 case BFD_RELOC_MIPS_TLS_LDM:
15253 case BFD_RELOC_MIPS_TLS_DTPREL32:
15254 case BFD_RELOC_MIPS_TLS_DTPREL64:
15255 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
15256 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
15257 case BFD_RELOC_MIPS_TLS_GOTTPREL:
15258 case BFD_RELOC_MIPS_TLS_TPREL32:
15259 case BFD_RELOC_MIPS_TLS_TPREL64:
15260 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
15261 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
15262 case BFD_RELOC_MICROMIPS_TLS_GD:
15263 case BFD_RELOC_MICROMIPS_TLS_LDM:
15264 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
15265 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
15266 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
15267 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
15268 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
15269 case BFD_RELOC_MIPS16_TLS_GD:
15270 case BFD_RELOC_MIPS16_TLS_LDM:
15271 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
15272 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
15273 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
15274 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
15275 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
15276 if (fixP->fx_addsy)
15277 S_SET_THREAD_LOCAL (fixP->fx_addsy);
15279 as_bad_where (fixP->fx_file, fixP->fx_line,
15280 _("TLS relocation against a constant"));
15283 case BFD_RELOC_MIPS_JMP:
15284 case BFD_RELOC_MIPS16_JMP:
15285 case BFD_RELOC_MICROMIPS_JMP:
15289 gas_assert (!fixP->fx_done);
15291 /* Shift is 2, unusually, for microMIPS JALX. */
15292 if (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP
15293 && (read_compressed_insn (buf, 4) >> 26) != 0x3c)
15298 if (fix_bad_cross_mode_jump_p (fixP))
15299 as_bad_where (fixP->fx_file, fixP->fx_line,
15300 _("jump to a symbol in another ISA mode"));
15301 else if (fix_bad_same_mode_jalx_p (fixP))
15302 as_bad_where (fixP->fx_file, fixP->fx_line,
15303 _("JALX to a symbol in the same ISA mode"));
15304 else if (fix_bad_misaligned_jump_p (fixP, shift))
15305 as_bad_where (fixP->fx_file, fixP->fx_line,
15306 _("jump to misaligned address (0x%lx)"),
15307 (long) (S_GET_VALUE (fixP->fx_addsy)
15308 + fixP->fx_offset));
15309 else if (HAVE_IN_PLACE_ADDENDS
15310 && (fixP->fx_offset & ((1 << shift) - 1)) != 0)
15311 as_bad_where (fixP->fx_file, fixP->fx_line,
15312 _("cannot encode misaligned addend "
15313 "in the relocatable field (0x%lx)"),
15314 (long) fixP->fx_offset);
15316 /* Fall through. */
15318 case BFD_RELOC_MIPS_SHIFT5:
15319 case BFD_RELOC_MIPS_SHIFT6:
15320 case BFD_RELOC_MIPS_GOT_DISP:
15321 case BFD_RELOC_MIPS_GOT_PAGE:
15322 case BFD_RELOC_MIPS_GOT_OFST:
15323 case BFD_RELOC_MIPS_SUB:
15324 case BFD_RELOC_MIPS_INSERT_A:
15325 case BFD_RELOC_MIPS_INSERT_B:
15326 case BFD_RELOC_MIPS_DELETE:
15327 case BFD_RELOC_MIPS_HIGHEST:
15328 case BFD_RELOC_MIPS_HIGHER:
15329 case BFD_RELOC_MIPS_SCN_DISP:
15330 case BFD_RELOC_MIPS_REL16:
15331 case BFD_RELOC_MIPS_RELGOT:
15332 case BFD_RELOC_MIPS_JALR:
15333 case BFD_RELOC_HI16:
15334 case BFD_RELOC_HI16_S:
15335 case BFD_RELOC_LO16:
15336 case BFD_RELOC_GPREL16:
15337 case BFD_RELOC_MIPS_LITERAL:
15338 case BFD_RELOC_MIPS_CALL16:
15339 case BFD_RELOC_MIPS_GOT16:
15340 case BFD_RELOC_GPREL32:
15341 case BFD_RELOC_MIPS_GOT_HI16:
15342 case BFD_RELOC_MIPS_GOT_LO16:
15343 case BFD_RELOC_MIPS_CALL_HI16:
15344 case BFD_RELOC_MIPS_CALL_LO16:
15345 case BFD_RELOC_HI16_S_PCREL:
15346 case BFD_RELOC_LO16_PCREL:
15347 case BFD_RELOC_MIPS16_GPREL:
15348 case BFD_RELOC_MIPS16_GOT16:
15349 case BFD_RELOC_MIPS16_CALL16:
15350 case BFD_RELOC_MIPS16_HI16:
15351 case BFD_RELOC_MIPS16_HI16_S:
15352 case BFD_RELOC_MIPS16_LO16:
15353 case BFD_RELOC_MICROMIPS_GOT_DISP:
15354 case BFD_RELOC_MICROMIPS_GOT_PAGE:
15355 case BFD_RELOC_MICROMIPS_GOT_OFST:
15356 case BFD_RELOC_MICROMIPS_SUB:
15357 case BFD_RELOC_MICROMIPS_HIGHEST:
15358 case BFD_RELOC_MICROMIPS_HIGHER:
15359 case BFD_RELOC_MICROMIPS_SCN_DISP:
15360 case BFD_RELOC_MICROMIPS_JALR:
15361 case BFD_RELOC_MICROMIPS_HI16:
15362 case BFD_RELOC_MICROMIPS_HI16_S:
15363 case BFD_RELOC_MICROMIPS_LO16:
15364 case BFD_RELOC_MICROMIPS_GPREL16:
15365 case BFD_RELOC_MICROMIPS_LITERAL:
15366 case BFD_RELOC_MICROMIPS_CALL16:
15367 case BFD_RELOC_MICROMIPS_GOT16:
15368 case BFD_RELOC_MICROMIPS_GOT_HI16:
15369 case BFD_RELOC_MICROMIPS_GOT_LO16:
15370 case BFD_RELOC_MICROMIPS_CALL_HI16:
15371 case BFD_RELOC_MICROMIPS_CALL_LO16:
15372 case BFD_RELOC_MIPS_EH:
15377 if (calculate_reloc (fixP->fx_r_type, *valP, &value))
15379 insn = read_reloc_insn (buf, fixP->fx_r_type);
15380 if (mips16_reloc_p (fixP->fx_r_type))
15381 insn |= mips16_immed_extend (value, 16);
15383 insn |= (value & 0xffff);
15384 write_reloc_insn (buf, fixP->fx_r_type, insn);
15387 as_bad_where (fixP->fx_file, fixP->fx_line,
15388 _("unsupported constant in relocation"));
15393 /* This is handled like BFD_RELOC_32, but we output a sign
15394 extended value if we are only 32 bits. */
15397 if (8 <= sizeof (valueT))
15398 md_number_to_chars (buf, *valP, 8);
15403 if ((*valP & 0x80000000) != 0)
15407 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4);
15408 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4);
15413 case BFD_RELOC_RVA:
15415 case BFD_RELOC_32_PCREL:
15418 /* If we are deleting this reloc entry, we must fill in the
15419 value now. This can happen if we have a .word which is not
15420 resolved when it appears but is later defined. */
15422 md_number_to_chars (buf, *valP, fixP->fx_size);
15425 case BFD_RELOC_MIPS_21_PCREL_S2:
15426 fix_validate_branch (fixP, *valP);
15427 if (!fixP->fx_done)
15430 if (*valP + 0x400000 <= 0x7fffff)
15432 insn = read_insn (buf);
15433 insn |= (*valP >> 2) & 0x1fffff;
15434 write_insn (buf, insn);
15437 as_bad_where (fixP->fx_file, fixP->fx_line,
15438 _("branch out of range"));
15441 case BFD_RELOC_MIPS_26_PCREL_S2:
15442 fix_validate_branch (fixP, *valP);
15443 if (!fixP->fx_done)
15446 if (*valP + 0x8000000 <= 0xfffffff)
15448 insn = read_insn (buf);
15449 insn |= (*valP >> 2) & 0x3ffffff;
15450 write_insn (buf, insn);
15453 as_bad_where (fixP->fx_file, fixP->fx_line,
15454 _("branch out of range"));
15457 case BFD_RELOC_MIPS_18_PCREL_S3:
15458 if (fixP->fx_addsy && (S_GET_VALUE (fixP->fx_addsy) & 0x7) != 0)
15459 as_bad_where (fixP->fx_file, fixP->fx_line,
15460 _("PC-relative access using misaligned symbol (%lx)"),
15461 (long) S_GET_VALUE (fixP->fx_addsy));
15462 if ((fixP->fx_offset & 0x7) != 0)
15463 as_bad_where (fixP->fx_file, fixP->fx_line,
15464 _("PC-relative access using misaligned offset (%lx)"),
15465 (long) fixP->fx_offset);
15466 if (!fixP->fx_done)
15469 if (*valP + 0x100000 <= 0x1fffff)
15471 insn = read_insn (buf);
15472 insn |= (*valP >> 3) & 0x3ffff;
15473 write_insn (buf, insn);
15476 as_bad_where (fixP->fx_file, fixP->fx_line,
15477 _("PC-relative access out of range"));
15480 case BFD_RELOC_MIPS_19_PCREL_S2:
15481 if ((*valP & 0x3) != 0)
15482 as_bad_where (fixP->fx_file, fixP->fx_line,
15483 _("PC-relative access to misaligned address (%lx)"),
15485 if (!fixP->fx_done)
15488 if (*valP + 0x100000 <= 0x1fffff)
15490 insn = read_insn (buf);
15491 insn |= (*valP >> 2) & 0x7ffff;
15492 write_insn (buf, insn);
15495 as_bad_where (fixP->fx_file, fixP->fx_line,
15496 _("PC-relative access out of range"));
15499 case BFD_RELOC_16_PCREL_S2:
15500 fix_validate_branch (fixP, *valP);
15502 /* We need to save the bits in the instruction since fixup_segment()
15503 might be deleting the relocation entry (i.e., a branch within
15504 the current segment). */
15505 if (! fixP->fx_done)
15508 /* Update old instruction data. */
15509 insn = read_insn (buf);
15511 if (*valP + 0x20000 <= 0x3ffff)
15513 insn |= (*valP >> 2) & 0xffff;
15514 write_insn (buf, insn);
15516 else if (mips_pic == NO_PIC
15518 && fixP->fx_frag->fr_address >= text_section->vma
15519 && (fixP->fx_frag->fr_address
15520 < text_section->vma + bfd_get_section_size (text_section))
15521 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
15522 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
15523 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
15525 /* The branch offset is too large. If this is an
15526 unconditional branch, and we are not generating PIC code,
15527 we can convert it to an absolute jump instruction. */
15528 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
15529 insn = 0x0c000000; /* jal */
15531 insn = 0x08000000; /* j */
15532 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
15534 fixP->fx_addsy = section_symbol (text_section);
15535 *valP += md_pcrel_from (fixP);
15536 write_insn (buf, insn);
15540 /* If we got here, we have branch-relaxation disabled,
15541 and there's nothing we can do to fix this instruction
15542 without turning it into a longer sequence. */
15543 as_bad_where (fixP->fx_file, fixP->fx_line,
15544 _("branch out of range"));
15548 case BFD_RELOC_MIPS16_16_PCREL_S1:
15549 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15550 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15551 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15552 gas_assert (!fixP->fx_done);
15553 if (fix_bad_cross_mode_branch_p (fixP))
15554 as_bad_where (fixP->fx_file, fixP->fx_line,
15555 _("branch to a symbol in another ISA mode"));
15556 else if (fixP->fx_addsy
15557 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
15558 && !bfd_is_abs_section (S_GET_SEGMENT (fixP->fx_addsy))
15559 && (fixP->fx_offset & 0x1) != 0)
15560 as_bad_where (fixP->fx_file, fixP->fx_line,
15561 _("branch to misaligned address (0x%lx)"),
15562 (long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset));
15563 else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x1) != 0)
15564 as_bad_where (fixP->fx_file, fixP->fx_line,
15565 _("cannot encode misaligned addend "
15566 "in the relocatable field (0x%lx)"),
15567 (long) fixP->fx_offset);
15570 case BFD_RELOC_VTABLE_INHERIT:
15573 && !S_IS_DEFINED (fixP->fx_addsy)
15574 && !S_IS_WEAK (fixP->fx_addsy))
15575 S_SET_WEAK (fixP->fx_addsy);
15578 case BFD_RELOC_NONE:
15579 case BFD_RELOC_VTABLE_ENTRY:
15587 /* Remember value for tc_gen_reloc. */
15588 fixP->fx_addnumber = *valP;
15598 c = get_symbol_name (&name);
15599 p = (symbolS *) symbol_find_or_make (name);
15600 (void) restore_line_pointer (c);
15604 /* Align the current frag to a given power of two. If a particular
15605 fill byte should be used, FILL points to an integer that contains
15606 that byte, otherwise FILL is null.
15608 This function used to have the comment:
15610 The MIPS assembler also automatically adjusts any preceding label.
15612 The implementation therefore applied the adjustment to a maximum of
15613 one label. However, other label adjustments are applied to batches
15614 of labels, and adjusting just one caused problems when new labels
15615 were added for the sake of debugging or unwind information.
15616 We therefore adjust all preceding labels (given as LABELS) instead. */
15619 mips_align (int to, int *fill, struct insn_label_list *labels)
15621 mips_emit_delays ();
15622 mips_record_compressed_mode ();
15623 if (fill == NULL && subseg_text_p (now_seg))
15624 frag_align_code (to, 0);
15626 frag_align (to, fill ? *fill : 0, 0);
15627 record_alignment (now_seg, to);
15628 mips_move_labels (labels, FALSE);
15631 /* Align to a given power of two. .align 0 turns off the automatic
15632 alignment used by the data creating pseudo-ops. */
15635 s_align (int x ATTRIBUTE_UNUSED)
15637 int temp, fill_value, *fill_ptr;
15638 long max_alignment = 28;
15640 /* o Note that the assembler pulls down any immediately preceding label
15641 to the aligned address.
15642 o It's not documented but auto alignment is reinstated by
15643 a .align pseudo instruction.
15644 o Note also that after auto alignment is turned off the mips assembler
15645 issues an error on attempt to assemble an improperly aligned data item.
15648 temp = get_absolute_expression ();
15649 if (temp > max_alignment)
15650 as_bad (_("alignment too large, %d assumed"), temp = max_alignment);
15653 as_warn (_("alignment negative, 0 assumed"));
15656 if (*input_line_pointer == ',')
15658 ++input_line_pointer;
15659 fill_value = get_absolute_expression ();
15660 fill_ptr = &fill_value;
15666 segment_info_type *si = seg_info (now_seg);
15667 struct insn_label_list *l = si->label_list;
15668 /* Auto alignment should be switched on by next section change. */
15670 mips_align (temp, fill_ptr, l);
15677 demand_empty_rest_of_line ();
15681 s_change_sec (int sec)
15685 /* The ELF backend needs to know that we are changing sections, so
15686 that .previous works correctly. We could do something like check
15687 for an obj_section_change_hook macro, but that might be confusing
15688 as it would not be appropriate to use it in the section changing
15689 functions in read.c, since obj-elf.c intercepts those. FIXME:
15690 This should be cleaner, somehow. */
15691 obj_elf_section_change_hook ();
15693 mips_emit_delays ();
15704 subseg_set (bss_section, (subsegT) get_absolute_expression ());
15705 demand_empty_rest_of_line ();
15709 seg = subseg_new (RDATA_SECTION_NAME,
15710 (subsegT) get_absolute_expression ());
15711 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
15712 | SEC_READONLY | SEC_RELOC
15714 if (strncmp (TARGET_OS, "elf", 3) != 0)
15715 record_alignment (seg, 4);
15716 demand_empty_rest_of_line ();
15720 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
15721 bfd_set_section_flags (stdoutput, seg,
15722 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
15723 if (strncmp (TARGET_OS, "elf", 3) != 0)
15724 record_alignment (seg, 4);
15725 demand_empty_rest_of_line ();
15729 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
15730 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
15731 if (strncmp (TARGET_OS, "elf", 3) != 0)
15732 record_alignment (seg, 4);
15733 demand_empty_rest_of_line ();
15741 s_change_section (int ignore ATTRIBUTE_UNUSED)
15744 char *section_name;
15749 int section_entry_size;
15750 int section_alignment;
15752 saved_ilp = input_line_pointer;
15753 endc = get_symbol_name (§ion_name);
15754 c = (endc == '"' ? input_line_pointer[1] : endc);
15756 next_c = input_line_pointer [(endc == '"' ? 2 : 1)];
15758 /* Do we have .section Name<,"flags">? */
15759 if (c != ',' || (c == ',' && next_c == '"'))
15761 /* Just after name is now '\0'. */
15762 (void) restore_line_pointer (endc);
15763 input_line_pointer = saved_ilp;
15764 obj_elf_section (ignore);
15768 section_name = xstrdup (section_name);
15769 c = restore_line_pointer (endc);
15771 input_line_pointer++;
15773 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
15775 section_type = get_absolute_expression ();
15779 if (*input_line_pointer++ == ',')
15780 section_flag = get_absolute_expression ();
15784 if (*input_line_pointer++ == ',')
15785 section_entry_size = get_absolute_expression ();
15787 section_entry_size = 0;
15789 if (*input_line_pointer++ == ',')
15790 section_alignment = get_absolute_expression ();
15792 section_alignment = 0;
15794 /* FIXME: really ignore? */
15795 (void) section_alignment;
15797 /* When using the generic form of .section (as implemented by obj-elf.c),
15798 there's no way to set the section type to SHT_MIPS_DWARF. Users have
15799 traditionally had to fall back on the more common @progbits instead.
15801 There's nothing really harmful in this, since bfd will correct
15802 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
15803 means that, for backwards compatibility, the special_section entries
15804 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
15806 Even so, we shouldn't force users of the MIPS .section syntax to
15807 incorrectly label the sections as SHT_PROGBITS. The best compromise
15808 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
15809 generic type-checking code. */
15810 if (section_type == SHT_MIPS_DWARF)
15811 section_type = SHT_PROGBITS;
15813 obj_elf_change_section (section_name, section_type, section_flag,
15814 section_entry_size, 0, 0, 0);
15816 if (now_seg->name != section_name)
15817 free (section_name);
15821 mips_enable_auto_align (void)
15827 s_cons (int log_size)
15829 segment_info_type *si = seg_info (now_seg);
15830 struct insn_label_list *l = si->label_list;
15832 mips_emit_delays ();
15833 if (log_size > 0 && auto_align)
15834 mips_align (log_size, 0, l);
15835 cons (1 << log_size);
15836 mips_clear_insn_labels ();
15840 s_float_cons (int type)
15842 segment_info_type *si = seg_info (now_seg);
15843 struct insn_label_list *l = si->label_list;
15845 mips_emit_delays ();
15850 mips_align (3, 0, l);
15852 mips_align (2, 0, l);
15856 mips_clear_insn_labels ();
15859 /* Handle .globl. We need to override it because on Irix 5 you are
15862 where foo is an undefined symbol, to mean that foo should be
15863 considered to be the address of a function. */
15866 s_mips_globl (int x ATTRIBUTE_UNUSED)
15875 c = get_symbol_name (&name);
15876 symbolP = symbol_find_or_make (name);
15877 S_SET_EXTERNAL (symbolP);
15879 *input_line_pointer = c;
15880 SKIP_WHITESPACE_AFTER_NAME ();
15882 /* On Irix 5, every global symbol that is not explicitly labelled as
15883 being a function is apparently labelled as being an object. */
15886 if (!is_end_of_line[(unsigned char) *input_line_pointer]
15887 && (*input_line_pointer != ','))
15892 c = get_symbol_name (&secname);
15893 sec = bfd_get_section_by_name (stdoutput, secname);
15895 as_bad (_("%s: no such section"), secname);
15896 (void) restore_line_pointer (c);
15898 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
15899 flag = BSF_FUNCTION;
15902 symbol_get_bfdsym (symbolP)->flags |= flag;
15904 c = *input_line_pointer;
15907 input_line_pointer++;
15908 SKIP_WHITESPACE ();
15909 if (is_end_of_line[(unsigned char) *input_line_pointer])
15915 demand_empty_rest_of_line ();
15919 s_option (int x ATTRIBUTE_UNUSED)
15924 c = get_symbol_name (&opt);
15928 /* FIXME: What does this mean? */
15930 else if (strncmp (opt, "pic", 3) == 0 && ISDIGIT (opt[3]) && opt[4] == '\0')
15934 i = atoi (opt + 3);
15935 if (i != 0 && i != 2)
15936 as_bad (_(".option pic%d not supported"), i);
15937 else if (mips_pic == VXWORKS_PIC)
15938 as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i);
15943 mips_pic = SVR4_PIC;
15944 mips_abicalls = TRUE;
15947 if (mips_pic == SVR4_PIC)
15949 if (g_switch_seen && g_switch_value != 0)
15950 as_warn (_("-G may not be used with SVR4 PIC code"));
15951 g_switch_value = 0;
15952 bfd_set_gp_size (stdoutput, 0);
15956 as_warn (_("unrecognized option \"%s\""), opt);
15958 (void) restore_line_pointer (c);
15959 demand_empty_rest_of_line ();
15962 /* This structure is used to hold a stack of .set values. */
15964 struct mips_option_stack
15966 struct mips_option_stack *next;
15967 struct mips_set_options options;
15970 static struct mips_option_stack *mips_opts_stack;
15972 /* Return status for .set/.module option handling. */
15974 enum code_option_type
15976 /* Unrecognized option. */
15977 OPTION_TYPE_BAD = -1,
15979 /* Ordinary option. */
15980 OPTION_TYPE_NORMAL,
15982 /* ISA changing option. */
15986 /* Handle common .set/.module options. Return status indicating option
15989 static enum code_option_type
15990 parse_code_option (char * name)
15992 bfd_boolean isa_set = FALSE;
15993 const struct mips_ase *ase;
15995 if (strncmp (name, "at=", 3) == 0)
15997 char *s = name + 3;
15999 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
16000 as_bad (_("unrecognized register name `%s'"), s);
16002 else if (strcmp (name, "at") == 0)
16003 mips_opts.at = ATREG;
16004 else if (strcmp (name, "noat") == 0)
16005 mips_opts.at = ZERO;
16006 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
16007 mips_opts.nomove = 0;
16008 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
16009 mips_opts.nomove = 1;
16010 else if (strcmp (name, "bopt") == 0)
16011 mips_opts.nobopt = 0;
16012 else if (strcmp (name, "nobopt") == 0)
16013 mips_opts.nobopt = 1;
16014 else if (strcmp (name, "gp=32") == 0)
16016 else if (strcmp (name, "gp=64") == 0)
16018 else if (strcmp (name, "fp=32") == 0)
16020 else if (strcmp (name, "fp=xx") == 0)
16022 else if (strcmp (name, "fp=64") == 0)
16024 else if (strcmp (name, "softfloat") == 0)
16025 mips_opts.soft_float = 1;
16026 else if (strcmp (name, "hardfloat") == 0)
16027 mips_opts.soft_float = 0;
16028 else if (strcmp (name, "singlefloat") == 0)
16029 mips_opts.single_float = 1;
16030 else if (strcmp (name, "doublefloat") == 0)
16031 mips_opts.single_float = 0;
16032 else if (strcmp (name, "nooddspreg") == 0)
16033 mips_opts.oddspreg = 0;
16034 else if (strcmp (name, "oddspreg") == 0)
16035 mips_opts.oddspreg = 1;
16036 else if (strcmp (name, "mips16") == 0
16037 || strcmp (name, "MIPS-16") == 0)
16038 mips_opts.mips16 = 1;
16039 else if (strcmp (name, "nomips16") == 0
16040 || strcmp (name, "noMIPS-16") == 0)
16041 mips_opts.mips16 = 0;
16042 else if (strcmp (name, "micromips") == 0)
16043 mips_opts.micromips = 1;
16044 else if (strcmp (name, "nomicromips") == 0)
16045 mips_opts.micromips = 0;
16046 else if (name[0] == 'n'
16048 && (ase = mips_lookup_ase (name + 2)))
16049 mips_set_ase (ase, &mips_opts, FALSE);
16050 else if ((ase = mips_lookup_ase (name)))
16051 mips_set_ase (ase, &mips_opts, TRUE);
16052 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
16054 /* Permit the user to change the ISA and architecture on the fly.
16055 Needless to say, misuse can cause serious problems. */
16056 if (strncmp (name, "arch=", 5) == 0)
16058 const struct mips_cpu_info *p;
16060 p = mips_parse_cpu ("internal use", name + 5);
16062 as_bad (_("unknown architecture %s"), name + 5);
16065 mips_opts.arch = p->cpu;
16066 mips_opts.isa = p->isa;
16070 else if (strncmp (name, "mips", 4) == 0)
16072 const struct mips_cpu_info *p;
16074 p = mips_parse_cpu ("internal use", name);
16076 as_bad (_("unknown ISA level %s"), name + 4);
16079 mips_opts.arch = p->cpu;
16080 mips_opts.isa = p->isa;
16085 as_bad (_("unknown ISA or architecture %s"), name);
16087 else if (strcmp (name, "autoextend") == 0)
16088 mips_opts.noautoextend = 0;
16089 else if (strcmp (name, "noautoextend") == 0)
16090 mips_opts.noautoextend = 1;
16091 else if (strcmp (name, "insn32") == 0)
16092 mips_opts.insn32 = TRUE;
16093 else if (strcmp (name, "noinsn32") == 0)
16094 mips_opts.insn32 = FALSE;
16095 else if (strcmp (name, "sym32") == 0)
16096 mips_opts.sym32 = TRUE;
16097 else if (strcmp (name, "nosym32") == 0)
16098 mips_opts.sym32 = FALSE;
16100 return OPTION_TYPE_BAD;
16102 return isa_set ? OPTION_TYPE_ISA : OPTION_TYPE_NORMAL;
16105 /* Handle the .set pseudo-op. */
16108 s_mipsset (int x ATTRIBUTE_UNUSED)
16110 enum code_option_type type = OPTION_TYPE_NORMAL;
16111 char *name = input_line_pointer, ch;
16113 file_mips_check_options ();
16115 while (!is_end_of_line[(unsigned char) *input_line_pointer])
16116 ++input_line_pointer;
16117 ch = *input_line_pointer;
16118 *input_line_pointer = '\0';
16120 if (strchr (name, ','))
16122 /* Generic ".set" directive; use the generic handler. */
16123 *input_line_pointer = ch;
16124 input_line_pointer = name;
16129 if (strcmp (name, "reorder") == 0)
16131 if (mips_opts.noreorder)
16134 else if (strcmp (name, "noreorder") == 0)
16136 if (!mips_opts.noreorder)
16137 start_noreorder ();
16139 else if (strcmp (name, "macro") == 0)
16140 mips_opts.warn_about_macros = 0;
16141 else if (strcmp (name, "nomacro") == 0)
16143 if (mips_opts.noreorder == 0)
16144 as_bad (_("`noreorder' must be set before `nomacro'"));
16145 mips_opts.warn_about_macros = 1;
16147 else if (strcmp (name, "gp=default") == 0)
16148 mips_opts.gp = file_mips_opts.gp;
16149 else if (strcmp (name, "fp=default") == 0)
16150 mips_opts.fp = file_mips_opts.fp;
16151 else if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
16153 mips_opts.isa = file_mips_opts.isa;
16154 mips_opts.arch = file_mips_opts.arch;
16155 mips_opts.gp = file_mips_opts.gp;
16156 mips_opts.fp = file_mips_opts.fp;
16158 else if (strcmp (name, "push") == 0)
16160 struct mips_option_stack *s;
16162 s = XNEW (struct mips_option_stack);
16163 s->next = mips_opts_stack;
16164 s->options = mips_opts;
16165 mips_opts_stack = s;
16167 else if (strcmp (name, "pop") == 0)
16169 struct mips_option_stack *s;
16171 s = mips_opts_stack;
16173 as_bad (_(".set pop with no .set push"));
16176 /* If we're changing the reorder mode we need to handle
16177 delay slots correctly. */
16178 if (s->options.noreorder && ! mips_opts.noreorder)
16179 start_noreorder ();
16180 else if (! s->options.noreorder && mips_opts.noreorder)
16183 mips_opts = s->options;
16184 mips_opts_stack = s->next;
16190 type = parse_code_option (name);
16191 if (type == OPTION_TYPE_BAD)
16192 as_warn (_("tried to set unrecognized symbol: %s\n"), name);
16195 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
16196 registers based on what is supported by the arch/cpu. */
16197 if (type == OPTION_TYPE_ISA)
16199 switch (mips_opts.isa)
16204 /* MIPS I cannot support FPXX. */
16206 /* fall-through. */
16213 if (mips_opts.fp != 0)
16229 if (mips_opts.fp != 0)
16231 if (mips_opts.arch == CPU_R5900)
16238 as_bad (_("unknown ISA level %s"), name + 4);
16243 mips_check_options (&mips_opts, FALSE);
16245 mips_check_isa_supports_ases ();
16246 *input_line_pointer = ch;
16247 demand_empty_rest_of_line ();
16250 /* Handle the .module pseudo-op. */
16253 s_module (int ignore ATTRIBUTE_UNUSED)
16255 char *name = input_line_pointer, ch;
16257 while (!is_end_of_line[(unsigned char) *input_line_pointer])
16258 ++input_line_pointer;
16259 ch = *input_line_pointer;
16260 *input_line_pointer = '\0';
16262 if (!file_mips_opts_checked)
16264 if (parse_code_option (name) == OPTION_TYPE_BAD)
16265 as_bad (_(".module used with unrecognized symbol: %s\n"), name);
16267 /* Update module level settings from mips_opts. */
16268 file_mips_opts = mips_opts;
16271 as_bad (_(".module is not permitted after generating code"));
16273 *input_line_pointer = ch;
16274 demand_empty_rest_of_line ();
16277 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16278 .option pic2. It means to generate SVR4 PIC calls. */
16281 s_abicalls (int ignore ATTRIBUTE_UNUSED)
16283 mips_pic = SVR4_PIC;
16284 mips_abicalls = TRUE;
16286 if (g_switch_seen && g_switch_value != 0)
16287 as_warn (_("-G may not be used with SVR4 PIC code"));
16288 g_switch_value = 0;
16290 bfd_set_gp_size (stdoutput, 0);
16291 demand_empty_rest_of_line ();
16294 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16295 PIC code. It sets the $gp register for the function based on the
16296 function address, which is in the register named in the argument.
16297 This uses a relocation against _gp_disp, which is handled specially
16298 by the linker. The result is:
16299 lui $gp,%hi(_gp_disp)
16300 addiu $gp,$gp,%lo(_gp_disp)
16301 addu $gp,$gp,.cpload argument
16302 The .cpload argument is normally $25 == $t9.
16304 The -mno-shared option changes this to:
16305 lui $gp,%hi(__gnu_local_gp)
16306 addiu $gp,$gp,%lo(__gnu_local_gp)
16307 and the argument is ignored. This saves an instruction, but the
16308 resulting code is not position independent; it uses an absolute
16309 address for __gnu_local_gp. Thus code assembled with -mno-shared
16310 can go into an ordinary executable, but not into a shared library. */
16313 s_cpload (int ignore ATTRIBUTE_UNUSED)
16319 file_mips_check_options ();
16321 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16322 .cpload is ignored. */
16323 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16329 if (mips_opts.mips16)
16331 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16332 ignore_rest_of_line ();
16336 /* .cpload should be in a .set noreorder section. */
16337 if (mips_opts.noreorder == 0)
16338 as_warn (_(".cpload not in noreorder section"));
16340 reg = tc_get_register (0);
16342 /* If we need to produce a 64-bit address, we are better off using
16343 the default instruction sequence. */
16344 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
16346 ex.X_op = O_symbol;
16347 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
16349 ex.X_op_symbol = NULL;
16350 ex.X_add_number = 0;
16352 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16353 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16355 mips_mark_labels ();
16356 mips_assembling_insn = TRUE;
16359 macro_build_lui (&ex, mips_gp_register);
16360 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16361 mips_gp_register, BFD_RELOC_LO16);
16363 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
16364 mips_gp_register, reg);
16367 mips_assembling_insn = FALSE;
16368 demand_empty_rest_of_line ();
16371 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16372 .cpsetup $reg1, offset|$reg2, label
16374 If offset is given, this results in:
16375 sd $gp, offset($sp)
16376 lui $gp, %hi(%neg(%gp_rel(label)))
16377 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16378 daddu $gp, $gp, $reg1
16380 If $reg2 is given, this results in:
16382 lui $gp, %hi(%neg(%gp_rel(label)))
16383 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16384 daddu $gp, $gp, $reg1
16385 $reg1 is normally $25 == $t9.
16387 The -mno-shared option replaces the last three instructions with
16389 addiu $gp,$gp,%lo(_gp) */
16392 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
16394 expressionS ex_off;
16395 expressionS ex_sym;
16398 file_mips_check_options ();
16400 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16401 We also need NewABI support. */
16402 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16408 if (mips_opts.mips16)
16410 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16411 ignore_rest_of_line ();
16415 reg1 = tc_get_register (0);
16416 SKIP_WHITESPACE ();
16417 if (*input_line_pointer != ',')
16419 as_bad (_("missing argument separator ',' for .cpsetup"));
16423 ++input_line_pointer;
16424 SKIP_WHITESPACE ();
16425 if (*input_line_pointer == '$')
16427 mips_cpreturn_register = tc_get_register (0);
16428 mips_cpreturn_offset = -1;
16432 mips_cpreturn_offset = get_absolute_expression ();
16433 mips_cpreturn_register = -1;
16435 SKIP_WHITESPACE ();
16436 if (*input_line_pointer != ',')
16438 as_bad (_("missing argument separator ',' for .cpsetup"));
16442 ++input_line_pointer;
16443 SKIP_WHITESPACE ();
16444 expression (&ex_sym);
16446 mips_mark_labels ();
16447 mips_assembling_insn = TRUE;
16450 if (mips_cpreturn_register == -1)
16452 ex_off.X_op = O_constant;
16453 ex_off.X_add_symbol = NULL;
16454 ex_off.X_op_symbol = NULL;
16455 ex_off.X_add_number = mips_cpreturn_offset;
16457 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
16458 BFD_RELOC_LO16, SP);
16461 move_register (mips_cpreturn_register, mips_gp_register);
16463 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
16465 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
16466 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
16469 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
16470 mips_gp_register, -1, BFD_RELOC_GPREL16,
16471 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
16473 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
16474 mips_gp_register, reg1);
16480 ex.X_op = O_symbol;
16481 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
16482 ex.X_op_symbol = NULL;
16483 ex.X_add_number = 0;
16485 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16486 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16488 macro_build_lui (&ex, mips_gp_register);
16489 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16490 mips_gp_register, BFD_RELOC_LO16);
16495 mips_assembling_insn = FALSE;
16496 demand_empty_rest_of_line ();
16500 s_cplocal (int ignore ATTRIBUTE_UNUSED)
16502 file_mips_check_options ();
16504 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16505 .cplocal is ignored. */
16506 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16512 if (mips_opts.mips16)
16514 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16515 ignore_rest_of_line ();
16519 mips_gp_register = tc_get_register (0);
16520 demand_empty_rest_of_line ();
16523 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16524 offset from $sp. The offset is remembered, and after making a PIC
16525 call $gp is restored from that location. */
16528 s_cprestore (int ignore ATTRIBUTE_UNUSED)
16532 file_mips_check_options ();
16534 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16535 .cprestore is ignored. */
16536 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16542 if (mips_opts.mips16)
16544 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16545 ignore_rest_of_line ();
16549 mips_cprestore_offset = get_absolute_expression ();
16550 mips_cprestore_valid = 1;
16552 ex.X_op = O_constant;
16553 ex.X_add_symbol = NULL;
16554 ex.X_op_symbol = NULL;
16555 ex.X_add_number = mips_cprestore_offset;
16557 mips_mark_labels ();
16558 mips_assembling_insn = TRUE;
16561 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
16562 SP, HAVE_64BIT_ADDRESSES);
16565 mips_assembling_insn = FALSE;
16566 demand_empty_rest_of_line ();
16569 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16570 was given in the preceding .cpsetup, it results in:
16571 ld $gp, offset($sp)
16573 If a register $reg2 was given there, it results in:
16574 or $gp, $reg2, $0 */
16577 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
16581 file_mips_check_options ();
16583 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16584 We also need NewABI support. */
16585 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16591 if (mips_opts.mips16)
16593 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16594 ignore_rest_of_line ();
16598 mips_mark_labels ();
16599 mips_assembling_insn = TRUE;
16602 if (mips_cpreturn_register == -1)
16604 ex.X_op = O_constant;
16605 ex.X_add_symbol = NULL;
16606 ex.X_op_symbol = NULL;
16607 ex.X_add_number = mips_cpreturn_offset;
16609 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
16612 move_register (mips_gp_register, mips_cpreturn_register);
16616 mips_assembling_insn = FALSE;
16617 demand_empty_rest_of_line ();
16620 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16621 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16622 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16623 debug information or MIPS16 TLS. */
16626 s_tls_rel_directive (const size_t bytes, const char *dirstr,
16627 bfd_reloc_code_real_type rtype)
16634 if (ex.X_op != O_symbol)
16636 as_bad (_("unsupported use of %s"), dirstr);
16637 ignore_rest_of_line ();
16640 p = frag_more (bytes);
16641 md_number_to_chars (p, 0, bytes);
16642 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
16643 demand_empty_rest_of_line ();
16644 mips_clear_insn_labels ();
16647 /* Handle .dtprelword. */
16650 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
16652 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
16655 /* Handle .dtpreldword. */
16658 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
16660 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
16663 /* Handle .tprelword. */
16666 s_tprelword (int ignore ATTRIBUTE_UNUSED)
16668 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
16671 /* Handle .tpreldword. */
16674 s_tpreldword (int ignore ATTRIBUTE_UNUSED)
16676 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
16679 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16680 code. It sets the offset to use in gp_rel relocations. */
16683 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
16685 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16686 We also need NewABI support. */
16687 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16693 mips_gprel_offset = get_absolute_expression ();
16695 demand_empty_rest_of_line ();
16698 /* Handle the .gpword pseudo-op. This is used when generating PIC
16699 code. It generates a 32 bit GP relative reloc. */
16702 s_gpword (int ignore ATTRIBUTE_UNUSED)
16704 segment_info_type *si;
16705 struct insn_label_list *l;
16709 /* When not generating PIC code, this is treated as .word. */
16710 if (mips_pic != SVR4_PIC)
16716 si = seg_info (now_seg);
16717 l = si->label_list;
16718 mips_emit_delays ();
16720 mips_align (2, 0, l);
16723 mips_clear_insn_labels ();
16725 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16727 as_bad (_("unsupported use of .gpword"));
16728 ignore_rest_of_line ();
16732 md_number_to_chars (p, 0, 4);
16733 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16734 BFD_RELOC_GPREL32);
16736 demand_empty_rest_of_line ();
16740 s_gpdword (int ignore ATTRIBUTE_UNUSED)
16742 segment_info_type *si;
16743 struct insn_label_list *l;
16747 /* When not generating PIC code, this is treated as .dword. */
16748 if (mips_pic != SVR4_PIC)
16754 si = seg_info (now_seg);
16755 l = si->label_list;
16756 mips_emit_delays ();
16758 mips_align (3, 0, l);
16761 mips_clear_insn_labels ();
16763 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16765 as_bad (_("unsupported use of .gpdword"));
16766 ignore_rest_of_line ();
16770 md_number_to_chars (p, 0, 8);
16771 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16772 BFD_RELOC_GPREL32)->fx_tcbit = 1;
16774 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
16775 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
16776 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
16778 demand_empty_rest_of_line ();
16781 /* Handle the .ehword pseudo-op. This is used when generating unwinding
16782 tables. It generates a R_MIPS_EH reloc. */
16785 s_ehword (int ignore ATTRIBUTE_UNUSED)
16790 mips_emit_delays ();
16793 mips_clear_insn_labels ();
16795 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16797 as_bad (_("unsupported use of .ehword"));
16798 ignore_rest_of_line ();
16802 md_number_to_chars (p, 0, 4);
16803 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16804 BFD_RELOC_32_PCREL);
16806 demand_empty_rest_of_line ();
16809 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
16810 tables in SVR4 PIC code. */
16813 s_cpadd (int ignore ATTRIBUTE_UNUSED)
16817 file_mips_check_options ();
16819 /* This is ignored when not generating SVR4 PIC code. */
16820 if (mips_pic != SVR4_PIC)
16826 mips_mark_labels ();
16827 mips_assembling_insn = TRUE;
16829 /* Add $gp to the register named as an argument. */
16831 reg = tc_get_register (0);
16832 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
16835 mips_assembling_insn = FALSE;
16836 demand_empty_rest_of_line ();
16839 /* Handle the .insn pseudo-op. This marks instruction labels in
16840 mips16/micromips mode. This permits the linker to handle them specially,
16841 such as generating jalx instructions when needed. We also make
16842 them odd for the duration of the assembly, in order to generate the
16843 right sort of code. We will make them even in the adjust_symtab
16844 routine, while leaving them marked. This is convenient for the
16845 debugger and the disassembler. The linker knows to make them odd
16849 s_insn (int ignore ATTRIBUTE_UNUSED)
16851 file_mips_check_options ();
16852 file_ase_mips16 |= mips_opts.mips16;
16853 file_ase_micromips |= mips_opts.micromips;
16855 mips_mark_labels ();
16857 demand_empty_rest_of_line ();
16860 /* Handle the .nan pseudo-op. */
16863 s_nan (int ignore ATTRIBUTE_UNUSED)
16865 static const char str_legacy[] = "legacy";
16866 static const char str_2008[] = "2008";
16869 for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++);
16871 if (i == sizeof (str_2008) - 1
16872 && memcmp (input_line_pointer, str_2008, i) == 0)
16874 else if (i == sizeof (str_legacy) - 1
16875 && memcmp (input_line_pointer, str_legacy, i) == 0)
16877 if (ISA_HAS_LEGACY_NAN (file_mips_opts.isa))
16880 as_bad (_("`%s' does not support legacy NaN"),
16881 mips_cpu_info_from_isa (file_mips_opts.isa)->name);
16884 as_bad (_("bad .nan directive"));
16886 input_line_pointer += i;
16887 demand_empty_rest_of_line ();
16890 /* Handle a .stab[snd] directive. Ideally these directives would be
16891 implemented in a transparent way, so that removing them would not
16892 have any effect on the generated instructions. However, s_stab
16893 internally changes the section, so in practice we need to decide
16894 now whether the preceding label marks compressed code. We do not
16895 support changing the compression mode of a label after a .stab*
16896 directive, such as in:
16902 so the current mode wins. */
16905 s_mips_stab (int type)
16907 mips_mark_labels ();
16911 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
16914 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
16921 c = get_symbol_name (&name);
16922 symbolP = symbol_find_or_make (name);
16923 S_SET_WEAK (symbolP);
16924 *input_line_pointer = c;
16926 SKIP_WHITESPACE_AFTER_NAME ();
16928 if (! is_end_of_line[(unsigned char) *input_line_pointer])
16930 if (S_IS_DEFINED (symbolP))
16932 as_bad (_("ignoring attempt to redefine symbol %s"),
16933 S_GET_NAME (symbolP));
16934 ignore_rest_of_line ();
16938 if (*input_line_pointer == ',')
16940 ++input_line_pointer;
16941 SKIP_WHITESPACE ();
16945 if (exp.X_op != O_symbol)
16947 as_bad (_("bad .weakext directive"));
16948 ignore_rest_of_line ();
16951 symbol_set_value_expression (symbolP, &exp);
16954 demand_empty_rest_of_line ();
16957 /* Parse a register string into a number. Called from the ECOFF code
16958 to parse .frame. The argument is non-zero if this is the frame
16959 register, so that we can record it in mips_frame_reg. */
16962 tc_get_register (int frame)
16966 SKIP_WHITESPACE ();
16967 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
16971 mips_frame_reg = reg != 0 ? reg : SP;
16972 mips_frame_reg_valid = 1;
16973 mips_cprestore_valid = 0;
16979 md_section_align (asection *seg, valueT addr)
16981 int align = bfd_get_section_alignment (stdoutput, seg);
16983 /* We don't need to align ELF sections to the full alignment.
16984 However, Irix 5 may prefer that we align them at least to a 16
16985 byte boundary. We don't bother to align the sections if we
16986 are targeted for an embedded system. */
16987 if (strncmp (TARGET_OS, "elf", 3) == 0)
16992 return ((addr + (1 << align) - 1) & -(1 << align));
16995 /* Utility routine, called from above as well. If called while the
16996 input file is still being read, it's only an approximation. (For
16997 example, a symbol may later become defined which appeared to be
16998 undefined earlier.) */
17001 nopic_need_relax (symbolS *sym, int before_relaxing)
17006 if (g_switch_value > 0)
17008 const char *symname;
17011 /* Find out whether this symbol can be referenced off the $gp
17012 register. It can be if it is smaller than the -G size or if
17013 it is in the .sdata or .sbss section. Certain symbols can
17014 not be referenced off the $gp, although it appears as though
17016 symname = S_GET_NAME (sym);
17017 if (symname != (const char *) NULL
17018 && (strcmp (symname, "eprol") == 0
17019 || strcmp (symname, "etext") == 0
17020 || strcmp (symname, "_gp") == 0
17021 || strcmp (symname, "edata") == 0
17022 || strcmp (symname, "_fbss") == 0
17023 || strcmp (symname, "_fdata") == 0
17024 || strcmp (symname, "_ftext") == 0
17025 || strcmp (symname, "end") == 0
17026 || strcmp (symname, "_gp_disp") == 0))
17028 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
17030 #ifndef NO_ECOFF_DEBUGGING
17031 || (symbol_get_obj (sym)->ecoff_extern_size != 0
17032 && (symbol_get_obj (sym)->ecoff_extern_size
17033 <= g_switch_value))
17035 /* We must defer this decision until after the whole
17036 file has been read, since there might be a .extern
17037 after the first use of this symbol. */
17038 || (before_relaxing
17039 #ifndef NO_ECOFF_DEBUGGING
17040 && symbol_get_obj (sym)->ecoff_extern_size == 0
17042 && S_GET_VALUE (sym) == 0)
17043 || (S_GET_VALUE (sym) != 0
17044 && S_GET_VALUE (sym) <= g_switch_value)))
17048 const char *segname;
17050 segname = segment_name (S_GET_SEGMENT (sym));
17051 gas_assert (strcmp (segname, ".lit8") != 0
17052 && strcmp (segname, ".lit4") != 0);
17053 change = (strcmp (segname, ".sdata") != 0
17054 && strcmp (segname, ".sbss") != 0
17055 && strncmp (segname, ".sdata.", 7) != 0
17056 && strncmp (segname, ".sbss.", 6) != 0
17057 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
17058 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
17063 /* We are not optimizing for the $gp register. */
17068 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17071 pic_need_relax (symbolS *sym, asection *segtype)
17075 /* Handle the case of a symbol equated to another symbol. */
17076 while (symbol_equated_reloc_p (sym))
17080 /* It's possible to get a loop here in a badly written program. */
17081 n = symbol_get_value_expression (sym)->X_add_symbol;
17087 if (symbol_section_p (sym))
17090 symsec = S_GET_SEGMENT (sym);
17092 /* This must duplicate the test in adjust_reloc_syms. */
17093 return (!bfd_is_und_section (symsec)
17094 && !bfd_is_abs_section (symsec)
17095 && !bfd_is_com_section (symsec)
17096 && !s_is_linkonce (sym, segtype)
17097 /* A global or weak symbol is treated as external. */
17098 && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym)));
17102 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17103 extended opcode. SEC is the section the frag is in. */
17106 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
17109 const struct mips_int_operand *operand;
17114 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
17116 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17119 symsec = S_GET_SEGMENT (fragp->fr_symbol);
17120 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
17121 operand = mips16_immed_operand (type, FALSE);
17122 if (S_FORCE_RELOC (fragp->fr_symbol, TRUE)
17123 || (operand->root.type == OP_PCREL
17125 : !bfd_is_abs_section (symsec)))
17128 sym_frag = symbol_get_frag (fragp->fr_symbol);
17129 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17131 if (operand->root.type == OP_PCREL)
17133 const struct mips_pcrel_operand *pcrel_op;
17137 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
17140 pcrel_op = (const struct mips_pcrel_operand *) operand;
17142 /* If the relax_marker of the symbol fragment differs from the
17143 relax_marker of this fragment, we have not yet adjusted the
17144 symbol fragment fr_address. We want to add in STRETCH in
17145 order to get a better estimate of the address. This
17146 particularly matters because of the shift bits. */
17148 && sym_frag->relax_marker != fragp->relax_marker)
17152 /* Adjust stretch for any alignment frag. Note that if have
17153 been expanding the earlier code, the symbol may be
17154 defined in what appears to be an earlier frag. FIXME:
17155 This doesn't handle the fr_subtype field, which specifies
17156 a maximum number of bytes to skip when doing an
17158 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
17160 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
17163 stretch = - ((- stretch)
17164 & ~ ((1 << (int) f->fr_offset) - 1));
17166 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
17175 addr = fragp->fr_address + fragp->fr_fix;
17177 /* The base address rules are complicated. The base address of
17178 a branch is the following instruction. The base address of a
17179 PC relative load or add is the instruction itself, but if it
17180 is in a delay slot (in which case it can not be extended) use
17181 the address of the instruction whose delay slot it is in. */
17182 if (pcrel_op->include_isa_bit)
17186 /* If we are currently assuming that this frag should be
17187 extended, then, the current address is two bytes
17189 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17192 /* Ignore the low bit in the target, since it will be set
17193 for a text label. */
17196 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17198 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17201 val -= addr & -(1 << pcrel_op->align_log2);
17203 /* If any of the shifted bits are set, we must use an extended
17204 opcode. If the address depends on the size of this
17205 instruction, this can lead to a loop, so we arrange to always
17206 use an extended opcode. */
17207 if ((val & ((1 << operand->shift) - 1)) != 0)
17209 fragp->fr_subtype =
17210 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17214 /* If we are about to mark a frag as extended because the value
17215 is precisely the next value above maxtiny, then there is a
17216 chance of an infinite loop as in the following code:
17221 In this case when the la is extended, foo is 0x3fc bytes
17222 away, so the la can be shrunk, but then foo is 0x400 away, so
17223 the la must be extended. To avoid this loop, we mark the
17224 frag as extended if it was small, and is about to become
17225 extended with the next value above maxtiny. */
17226 maxtiny = mips_int_operand_max (operand);
17227 if (val == maxtiny + (1 << operand->shift)
17228 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17230 fragp->fr_subtype =
17231 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17236 return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val);
17239 /* Compute the length of a branch sequence, and adjust the
17240 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17241 worst-case length is computed, with UPDATE being used to indicate
17242 whether an unconditional (-1), branch-likely (+1) or regular (0)
17243 branch is to be computed. */
17245 relaxed_branch_length (fragS *fragp, asection *sec, int update)
17247 bfd_boolean toofar;
17251 && S_IS_DEFINED (fragp->fr_symbol)
17252 && !S_IS_WEAK (fragp->fr_symbol)
17253 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17258 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17260 addr = fragp->fr_address + fragp->fr_fix + 4;
17264 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
17267 /* If the symbol is not defined or it's in a different segment,
17268 we emit the long sequence. */
17271 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17273 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
17274 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
17275 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
17276 RELAX_BRANCH_LINK (fragp->fr_subtype),
17282 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
17285 if (mips_pic != NO_PIC)
17287 /* Additional space for PIC loading of target address. */
17289 if (mips_opts.isa == ISA_MIPS1)
17290 /* Additional space for $at-stabilizing nop. */
17294 /* If branch is conditional. */
17295 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
17302 /* Get a FRAG's branch instruction delay slot size, either from the
17303 short-delay-slot bit of a branch-and-link instruction if AL is TRUE,
17304 or SHORT_INSN_SIZE otherwise. */
17307 frag_branch_delay_slot_size (fragS *fragp, bfd_boolean al, int short_insn_size)
17309 char *buf = fragp->fr_literal + fragp->fr_fix;
17312 return (read_compressed_insn (buf, 4) & 0x02000000) ? 2 : 4;
17314 return short_insn_size;
17317 /* Compute the length of a branch sequence, and adjust the
17318 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17319 worst-case length is computed, with UPDATE being used to indicate
17320 whether an unconditional (-1), or regular (0) branch is to be
17324 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
17326 bfd_boolean insn32 = TRUE;
17327 bfd_boolean nods = TRUE;
17328 bfd_boolean al = TRUE;
17329 int short_insn_size;
17330 bfd_boolean toofar;
17335 insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype);
17336 nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype);
17337 al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
17339 short_insn_size = insn32 ? 4 : 2;
17342 && S_IS_DEFINED (fragp->fr_symbol)
17343 && !S_IS_WEAK (fragp->fr_symbol)
17344 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17349 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17350 /* Ignore the low bit in the target, since it will be set
17351 for a text label. */
17352 if ((val & 1) != 0)
17355 addr = fragp->fr_address + fragp->fr_fix + 4;
17359 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
17362 /* If the symbol is not defined or it's in a different segment,
17363 we emit the long sequence. */
17366 if (fragp && update
17367 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17368 fragp->fr_subtype = (toofar
17369 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
17370 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
17375 bfd_boolean compact_known = fragp != NULL;
17376 bfd_boolean compact = FALSE;
17377 bfd_boolean uncond;
17381 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17382 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
17385 uncond = update < 0;
17387 /* If label is out of range, we turn branch <br>:
17389 <br> label # 4 bytes
17396 # compact && (!PIC || insn32)
17399 if ((mips_pic == NO_PIC || insn32) && (!compact_known || compact))
17400 length += short_insn_size;
17402 /* If assembling PIC code, we further turn:
17408 lw/ld at, %got(label)(gp) # 4 bytes
17409 d/addiu at, %lo(label) # 4 bytes
17410 jr/c at # 2/4 bytes
17412 if (mips_pic != NO_PIC)
17413 length += 4 + short_insn_size;
17415 /* Add an extra nop if the jump has no compact form and we need
17416 to fill the delay slot. */
17417 if ((mips_pic == NO_PIC || al) && nods)
17419 ? frag_branch_delay_slot_size (fragp, al, short_insn_size)
17420 : short_insn_size);
17422 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17424 <brneg> 0f # 4 bytes
17425 nop # 2/4 bytes if !compact
17428 length += (compact_known && compact) ? 4 : 4 + short_insn_size;
17432 /* Add an extra nop to fill the delay slot. */
17433 gas_assert (fragp);
17434 length += frag_branch_delay_slot_size (fragp, al, short_insn_size);
17440 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17441 bit accordingly. */
17444 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
17446 bfd_boolean toofar;
17449 && S_IS_DEFINED (fragp->fr_symbol)
17450 && !S_IS_WEAK (fragp->fr_symbol)
17451 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17457 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17458 /* Ignore the low bit in the target, since it will be set
17459 for a text label. */
17460 if ((val & 1) != 0)
17463 /* Assume this is a 2-byte branch. */
17464 addr = fragp->fr_address + fragp->fr_fix + 2;
17466 /* We try to avoid the infinite loop by not adding 2 more bytes for
17471 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17473 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
17474 else if (type == 'E')
17475 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
17480 /* If the symbol is not defined or it's in a different segment,
17481 we emit a normal 32-bit branch. */
17484 if (fragp && update
17485 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17487 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
17488 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
17496 /* Estimate the size of a frag before relaxing. Unless this is the
17497 mips16, we are not really relaxing here, and the final size is
17498 encoded in the subtype information. For the mips16, we have to
17499 decide whether we are using an extended opcode or not. */
17502 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
17506 if (RELAX_BRANCH_P (fragp->fr_subtype))
17509 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
17511 return fragp->fr_var;
17514 if (RELAX_MIPS16_P (fragp->fr_subtype))
17515 /* We don't want to modify the EXTENDED bit here; it might get us
17516 into infinite loops. We change it only in mips_relax_frag(). */
17517 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
17519 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17523 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17524 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
17525 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17526 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
17527 fragp->fr_var = length;
17532 if (mips_pic == NO_PIC)
17533 change = nopic_need_relax (fragp->fr_symbol, 0);
17534 else if (mips_pic == SVR4_PIC)
17535 change = pic_need_relax (fragp->fr_symbol, segtype);
17536 else if (mips_pic == VXWORKS_PIC)
17537 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17544 fragp->fr_subtype |= RELAX_USE_SECOND;
17545 return -RELAX_FIRST (fragp->fr_subtype);
17548 return -RELAX_SECOND (fragp->fr_subtype);
17551 /* This is called to see whether a reloc against a defined symbol
17552 should be converted into a reloc against a section. */
17555 mips_fix_adjustable (fixS *fixp)
17557 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
17558 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17561 if (fixp->fx_addsy == NULL)
17564 /* Allow relocs used for EH tables. */
17565 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
17568 /* If symbol SYM is in a mergeable section, relocations of the form
17569 SYM + 0 can usually be made section-relative. The mergeable data
17570 is then identified by the section offset rather than by the symbol.
17572 However, if we're generating REL LO16 relocations, the offset is split
17573 between the LO16 and parterning high part relocation. The linker will
17574 need to recalculate the complete offset in order to correctly identify
17577 The linker has traditionally not looked for the parterning high part
17578 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17579 placed anywhere. Rather than break backwards compatibility by changing
17580 this, it seems better not to force the issue, and instead keep the
17581 original symbol. This will work with either linker behavior. */
17582 if ((lo16_reloc_p (fixp->fx_r_type)
17583 || reloc_needs_lo_p (fixp->fx_r_type))
17584 && HAVE_IN_PLACE_ADDENDS
17585 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
17588 /* There is no place to store an in-place offset for JALR relocations. */
17589 if (jalr_reloc_p (fixp->fx_r_type) && HAVE_IN_PLACE_ADDENDS)
17592 /* Likewise an in-range offset of limited PC-relative relocations may
17593 overflow the in-place relocatable field if recalculated against the
17594 start address of the symbol's containing section.
17596 Also, PC relative relocations for MIPS R6 need to be symbol rather than
17597 section relative to allow linker relaxations to be performed later on. */
17598 if (limited_pcrel_reloc_p (fixp->fx_r_type)
17599 && (HAVE_IN_PLACE_ADDENDS || ISA_IS_R6 (file_mips_opts.isa)))
17602 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17603 to a floating-point stub. The same is true for non-R_MIPS16_26
17604 relocations against MIPS16 functions; in this case, the stub becomes
17605 the function's canonical address.
17607 Floating-point stubs are stored in unique .mips16.call.* or
17608 .mips16.fn.* sections. If a stub T for function F is in section S,
17609 the first relocation in section S must be against F; this is how the
17610 linker determines the target function. All relocations that might
17611 resolve to T must also be against F. We therefore have the following
17612 restrictions, which are given in an intentionally-redundant way:
17614 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17617 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17618 if that stub might be used.
17620 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17623 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17624 that stub might be used.
17626 There is a further restriction:
17628 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17629 R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2,
17630 R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1,
17631 R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1)
17632 against MIPS16 or microMIPS symbols because we need to keep the
17633 MIPS16 or microMIPS symbol for the purpose of mode mismatch
17634 detection and JAL or BAL to JALX instruction conversion in the
17637 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17638 against a MIPS16 symbol. We deal with (5) by additionally leaving
17639 alone any jump and branch relocations against a microMIPS symbol.
17641 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17642 relocation against some symbol R, no relocation against R may be
17643 reduced. (Note that this deals with (2) as well as (1) because
17644 relocations against global symbols will never be reduced on ELF
17645 targets.) This approach is a little simpler than trying to detect
17646 stub sections, and gives the "all or nothing" per-symbol consistency
17647 that we have for MIPS16 symbols. */
17648 if (fixp->fx_subsy == NULL
17649 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
17650 || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
17651 && (jmp_reloc_p (fixp->fx_r_type)
17652 || b_reloc_p (fixp->fx_r_type)))
17653 || *symbol_get_tc (fixp->fx_addsy)))
17659 /* Translate internal representation of relocation info to BFD target
17663 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
17665 static arelent *retval[4];
17667 bfd_reloc_code_real_type code;
17669 memset (retval, 0, sizeof(retval));
17670 reloc = retval[0] = XCNEW (arelent);
17671 reloc->sym_ptr_ptr = XNEW (asymbol *);
17672 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
17673 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
17675 if (fixp->fx_pcrel)
17677 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
17678 || fixp->fx_r_type == BFD_RELOC_MIPS16_16_PCREL_S1
17679 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
17680 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
17681 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
17682 || fixp->fx_r_type == BFD_RELOC_32_PCREL
17683 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
17684 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2
17685 || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3
17686 || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2
17687 || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL
17688 || fixp->fx_r_type == BFD_RELOC_LO16_PCREL);
17690 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17691 Relocations want only the symbol offset. */
17692 switch (fixp->fx_r_type)
17694 case BFD_RELOC_MIPS_18_PCREL_S3:
17695 reloc->addend = fixp->fx_addnumber + (reloc->address & ~7);
17698 reloc->addend = fixp->fx_addnumber + reloc->address;
17702 else if (HAVE_IN_PLACE_ADDENDS
17703 && fixp->fx_r_type == BFD_RELOC_MICROMIPS_JMP
17704 && (read_compressed_insn (fixp->fx_frag->fr_literal
17705 + fixp->fx_where, 4) >> 26) == 0x3c)
17707 /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place
17708 addend accordingly. */
17709 reloc->addend = fixp->fx_addnumber >> 1;
17712 reloc->addend = fixp->fx_addnumber;
17714 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17715 entry to be used in the relocation's section offset. */
17716 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17718 reloc->address = reloc->addend;
17722 code = fixp->fx_r_type;
17724 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
17725 if (reloc->howto == NULL)
17727 as_bad_where (fixp->fx_file, fixp->fx_line,
17728 _("cannot represent %s relocation in this object file"
17730 bfd_get_reloc_code_name (code));
17737 /* Relax a machine dependent frag. This returns the amount by which
17738 the current size of the frag should change. */
17741 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
17743 if (RELAX_BRANCH_P (fragp->fr_subtype))
17745 offsetT old_var = fragp->fr_var;
17747 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
17749 return fragp->fr_var - old_var;
17752 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17754 offsetT old_var = fragp->fr_var;
17755 offsetT new_var = 4;
17757 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17758 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
17759 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17760 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
17761 fragp->fr_var = new_var;
17763 return new_var - old_var;
17766 if (! RELAX_MIPS16_P (fragp->fr_subtype))
17769 if (mips16_extended_frag (fragp, sec, stretch))
17771 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17773 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
17778 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17780 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
17787 /* Convert a machine dependent frag. */
17790 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
17792 if (RELAX_BRANCH_P (fragp->fr_subtype))
17795 unsigned long insn;
17799 buf = fragp->fr_literal + fragp->fr_fix;
17800 insn = read_insn (buf);
17802 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17804 /* We generate a fixup instead of applying it right now
17805 because, if there are linker relaxations, we're going to
17806 need the relocations. */
17807 exp.X_op = O_symbol;
17808 exp.X_add_symbol = fragp->fr_symbol;
17809 exp.X_add_number = fragp->fr_offset;
17811 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
17812 BFD_RELOC_16_PCREL_S2);
17813 fixp->fx_file = fragp->fr_file;
17814 fixp->fx_line = fragp->fr_line;
17816 buf = write_insn (buf, insn);
17822 as_warn_where (fragp->fr_file, fragp->fr_line,
17823 _("relaxed out-of-range branch into a jump"));
17825 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
17828 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17830 /* Reverse the branch. */
17831 switch ((insn >> 28) & 0xf)
17834 if ((insn & 0xff000000) == 0x47000000
17835 || (insn & 0xff600000) == 0x45600000)
17837 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
17838 reversed by tweaking bit 23. */
17839 insn ^= 0x00800000;
17843 /* bc[0-3][tf]l? instructions can have the condition
17844 reversed by tweaking a single TF bit, and their
17845 opcodes all have 0x4???????. */
17846 gas_assert ((insn & 0xf3e00000) == 0x41000000);
17847 insn ^= 0x00010000;
17852 /* bltz 0x04000000 bgez 0x04010000
17853 bltzal 0x04100000 bgezal 0x04110000 */
17854 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
17855 insn ^= 0x00010000;
17859 /* beq 0x10000000 bne 0x14000000
17860 blez 0x18000000 bgtz 0x1c000000 */
17861 insn ^= 0x04000000;
17869 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
17871 /* Clear the and-link bit. */
17872 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
17874 /* bltzal 0x04100000 bgezal 0x04110000
17875 bltzall 0x04120000 bgezall 0x04130000 */
17876 insn &= ~0x00100000;
17879 /* Branch over the branch (if the branch was likely) or the
17880 full jump (not likely case). Compute the offset from the
17881 current instruction to branch to. */
17882 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17886 /* How many bytes in instructions we've already emitted? */
17887 i = buf - fragp->fr_literal - fragp->fr_fix;
17888 /* How many bytes in instructions from here to the end? */
17889 i = fragp->fr_var - i;
17891 /* Convert to instruction count. */
17893 /* Branch counts from the next instruction. */
17896 /* Branch over the jump. */
17897 buf = write_insn (buf, insn);
17900 buf = write_insn (buf, 0);
17902 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17904 /* beql $0, $0, 2f */
17906 /* Compute the PC offset from the current instruction to
17907 the end of the variable frag. */
17908 /* How many bytes in instructions we've already emitted? */
17909 i = buf - fragp->fr_literal - fragp->fr_fix;
17910 /* How many bytes in instructions from here to the end? */
17911 i = fragp->fr_var - i;
17912 /* Convert to instruction count. */
17914 /* Don't decrement i, because we want to branch over the
17918 buf = write_insn (buf, insn);
17919 buf = write_insn (buf, 0);
17923 if (mips_pic == NO_PIC)
17926 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
17927 ? 0x0c000000 : 0x08000000);
17928 exp.X_op = O_symbol;
17929 exp.X_add_symbol = fragp->fr_symbol;
17930 exp.X_add_number = fragp->fr_offset;
17932 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
17933 FALSE, BFD_RELOC_MIPS_JMP);
17934 fixp->fx_file = fragp->fr_file;
17935 fixp->fx_line = fragp->fr_line;
17937 buf = write_insn (buf, insn);
17941 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
17943 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
17944 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
17945 insn |= at << OP_SH_RT;
17946 exp.X_op = O_symbol;
17947 exp.X_add_symbol = fragp->fr_symbol;
17948 exp.X_add_number = fragp->fr_offset;
17950 if (fragp->fr_offset)
17952 exp.X_add_symbol = make_expr_symbol (&exp);
17953 exp.X_add_number = 0;
17956 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
17957 FALSE, BFD_RELOC_MIPS_GOT16);
17958 fixp->fx_file = fragp->fr_file;
17959 fixp->fx_line = fragp->fr_line;
17961 buf = write_insn (buf, insn);
17963 if (mips_opts.isa == ISA_MIPS1)
17965 buf = write_insn (buf, 0);
17967 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
17968 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
17969 insn |= at << OP_SH_RS | at << OP_SH_RT;
17971 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
17972 FALSE, BFD_RELOC_LO16);
17973 fixp->fx_file = fragp->fr_file;
17974 fixp->fx_line = fragp->fr_line;
17976 buf = write_insn (buf, insn);
17979 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
17983 insn |= at << OP_SH_RS;
17985 buf = write_insn (buf, insn);
17989 fragp->fr_fix += fragp->fr_var;
17990 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
17994 /* Relax microMIPS branches. */
17995 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17997 char *buf = fragp->fr_literal + fragp->fr_fix;
17998 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17999 bfd_boolean insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype);
18000 bfd_boolean nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype);
18001 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
18002 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
18003 bfd_boolean short_ds;
18004 unsigned long insn;
18008 exp.X_op = O_symbol;
18009 exp.X_add_symbol = fragp->fr_symbol;
18010 exp.X_add_number = fragp->fr_offset;
18012 fragp->fr_fix += fragp->fr_var;
18014 /* Handle 16-bit branches that fit or are forced to fit. */
18015 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
18017 /* We generate a fixup instead of applying it right now,
18018 because if there is linker relaxation, we're going to
18019 need the relocations. */
18021 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
18022 BFD_RELOC_MICROMIPS_10_PCREL_S1);
18023 else if (type == 'E')
18024 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
18025 BFD_RELOC_MICROMIPS_7_PCREL_S1);
18029 fixp->fx_file = fragp->fr_file;
18030 fixp->fx_line = fragp->fr_line;
18032 /* These relocations can have an addend that won't fit in
18034 fixp->fx_no_overflow = 1;
18039 /* Handle 32-bit branches that fit or are forced to fit. */
18040 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18041 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18043 /* We generate a fixup instead of applying it right now,
18044 because if there is linker relaxation, we're going to
18045 need the relocations. */
18046 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
18047 BFD_RELOC_MICROMIPS_16_PCREL_S1);
18048 fixp->fx_file = fragp->fr_file;
18049 fixp->fx_line = fragp->fr_line;
18053 insn = read_compressed_insn (buf, 4);
18058 /* Check the short-delay-slot bit. */
18059 if (!al || (insn & 0x02000000) != 0)
18060 buf = write_compressed_insn (buf, 0x0c00, 2);
18062 buf = write_compressed_insn (buf, 0x00000000, 4);
18065 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18070 /* Relax 16-bit branches to 32-bit branches. */
18073 insn = read_compressed_insn (buf, 2);
18075 if ((insn & 0xfc00) == 0xcc00) /* b16 */
18076 insn = 0x94000000; /* beq */
18077 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18079 unsigned long regno;
18081 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
18082 regno = micromips_to_32_reg_d_map [regno];
18083 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
18084 insn |= regno << MICROMIPSOP_SH_RS;
18089 /* Nothing else to do, just write it out. */
18090 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18091 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18093 buf = write_compressed_insn (buf, insn, 4);
18095 buf = write_compressed_insn (buf, 0x0c00, 2);
18096 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18101 insn = read_compressed_insn (buf, 4);
18103 /* Relax 32-bit branches to a sequence of instructions. */
18104 as_warn_where (fragp->fr_file, fragp->fr_line,
18105 _("relaxed out-of-range branch into a jump"));
18107 /* Set the short-delay-slot bit. */
18108 short_ds = !al || (insn & 0x02000000) != 0;
18110 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
18114 /* Reverse the branch. */
18115 if ((insn & 0xfc000000) == 0x94000000 /* beq */
18116 || (insn & 0xfc000000) == 0xb4000000) /* bne */
18117 insn ^= 0x20000000;
18118 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
18119 || (insn & 0xffe00000) == 0x40400000 /* bgez */
18120 || (insn & 0xffe00000) == 0x40800000 /* blez */
18121 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
18122 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
18123 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
18124 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
18125 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
18126 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
18127 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
18128 insn ^= 0x00400000;
18129 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
18130 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
18131 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
18132 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
18133 insn ^= 0x00200000;
18134 else if ((insn & 0xff000000) == 0x83000000 /* BZ.df
18136 || (insn & 0xff600000) == 0x81600000) /* BZ.V
18138 insn ^= 0x00800000;
18144 /* Clear the and-link and short-delay-slot bits. */
18145 gas_assert ((insn & 0xfda00000) == 0x40200000);
18147 /* bltzal 0x40200000 bgezal 0x40600000 */
18148 /* bltzals 0x42200000 bgezals 0x42600000 */
18149 insn &= ~0x02200000;
18152 /* Make a label at the end for use with the branch. */
18153 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
18154 micromips_label_inc ();
18155 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
18158 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE,
18159 BFD_RELOC_MICROMIPS_16_PCREL_S1);
18160 fixp->fx_file = fragp->fr_file;
18161 fixp->fx_line = fragp->fr_line;
18163 /* Branch over the jump. */
18164 buf = write_compressed_insn (buf, insn, 4);
18170 buf = write_compressed_insn (buf, 0x00000000, 4);
18172 buf = write_compressed_insn (buf, 0x0c00, 2);
18176 if (mips_pic == NO_PIC)
18178 unsigned long jal = (short_ds || nods
18179 ? 0x74000000 : 0xf4000000); /* jal/s */
18181 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18182 insn = al ? jal : 0xd4000000;
18184 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18185 BFD_RELOC_MICROMIPS_JMP);
18186 fixp->fx_file = fragp->fr_file;
18187 fixp->fx_line = fragp->fr_line;
18189 buf = write_compressed_insn (buf, insn, 4);
18191 if (compact || nods)
18195 buf = write_compressed_insn (buf, 0x00000000, 4);
18197 buf = write_compressed_insn (buf, 0x0c00, 2);
18202 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
18204 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18205 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
18206 insn |= at << MICROMIPSOP_SH_RT;
18208 if (exp.X_add_number)
18210 exp.X_add_symbol = make_expr_symbol (&exp);
18211 exp.X_add_number = 0;
18214 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18215 BFD_RELOC_MICROMIPS_GOT16);
18216 fixp->fx_file = fragp->fr_file;
18217 fixp->fx_line = fragp->fr_line;
18219 buf = write_compressed_insn (buf, insn, 4);
18221 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18222 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
18223 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
18225 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18226 BFD_RELOC_MICROMIPS_LO16);
18227 fixp->fx_file = fragp->fr_file;
18228 fixp->fx_line = fragp->fr_line;
18230 buf = write_compressed_insn (buf, insn, 4);
18235 insn = 0x00000f3c | (al ? RA : ZERO) << MICROMIPSOP_SH_RT;
18236 insn |= at << MICROMIPSOP_SH_RS;
18238 buf = write_compressed_insn (buf, insn, 4);
18240 if (compact || nods)
18242 buf = write_compressed_insn (buf, 0x00000000, 4);
18246 /* jr/jrc/jalr/jalrs $at */
18247 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
18248 unsigned long jr = compact || nods ? 0x45a0 : 0x4580; /* jr/c */
18250 insn = al ? jalr : jr;
18251 insn |= at << MICROMIPSOP_SH_MJ;
18253 buf = write_compressed_insn (buf, insn, 2);
18258 buf = write_compressed_insn (buf, 0x0c00, 2);
18260 buf = write_compressed_insn (buf, 0x00000000, 4);
18265 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18269 if (RELAX_MIPS16_P (fragp->fr_subtype))
18272 const struct mips_int_operand *operand;
18275 unsigned int user_length, length;
18276 bfd_boolean need_reloc;
18277 unsigned long insn;
18281 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
18282 operand = mips16_immed_operand (type, FALSE);
18284 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
18285 val = resolve_symbol_value (fragp->fr_symbol) + fragp->fr_offset;
18287 symsec = S_GET_SEGMENT (fragp->fr_symbol);
18288 need_reloc = (S_FORCE_RELOC (fragp->fr_symbol, TRUE)
18289 || (operand->root.type == OP_PCREL
18291 : !bfd_is_abs_section (symsec)));
18293 if (operand->root.type == OP_PCREL)
18295 const struct mips_pcrel_operand *pcrel_op;
18298 pcrel_op = (const struct mips_pcrel_operand *) operand;
18299 addr = fragp->fr_address + fragp->fr_fix;
18301 /* The rules for the base address of a PC relative reloc are
18302 complicated; see mips16_extended_frag. */
18303 if (pcrel_op->include_isa_bit)
18307 if (!ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp->fr_symbol)))
18308 as_bad_where (fragp->fr_file, fragp->fr_line,
18309 _("branch to a symbol in another ISA mode"));
18310 else if ((fragp->fr_offset & 0x1) != 0)
18311 as_bad_where (fragp->fr_file, fragp->fr_line,
18312 _("branch to misaligned address (0x%lx)"),
18318 /* Ignore the low bit in the target, since it will be
18319 set for a text label. */
18322 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
18324 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
18327 addr &= -(1 << pcrel_op->align_log2);
18330 /* Make sure the section winds up with the alignment we have
18332 if (operand->shift > 0)
18333 record_alignment (asec, operand->shift);
18337 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
18338 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
18339 as_warn_where (fragp->fr_file, fragp->fr_line,
18340 _("extended instruction in delay slot"));
18342 buf = fragp->fr_literal + fragp->fr_fix;
18344 insn = read_compressed_insn (buf, 2);
18346 insn |= MIPS16_EXTEND;
18348 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
18350 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
18357 bfd_reloc_code_real_type reloc = BFD_RELOC_NONE;
18365 reloc = BFD_RELOC_MIPS16_16_PCREL_S1;
18368 as_bad_where (fragp->fr_file, fragp->fr_line,
18369 _("unsupported relocation"));
18372 if (reloc != BFD_RELOC_NONE)
18376 exp.X_op = O_symbol;
18377 exp.X_add_symbol = fragp->fr_symbol;
18378 exp.X_add_number = fragp->fr_offset;
18380 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp,
18383 fixp->fx_file = fragp->fr_file;
18384 fixp->fx_line = fragp->fr_line;
18386 /* These relocations can have an addend that won't fit
18388 fixp->fx_no_overflow = 1;
18392 mips16_immed (fragp->fr_file, fragp->fr_line, type,
18393 BFD_RELOC_UNUSED, val, user_length, &insn);
18395 length = (ext ? 4 : 2);
18396 gas_assert (mips16_opcode_length (insn) == length);
18397 write_compressed_insn (buf, insn, length);
18398 fragp->fr_fix += length;
18402 relax_substateT subtype = fragp->fr_subtype;
18403 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
18404 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
18408 first = RELAX_FIRST (subtype);
18409 second = RELAX_SECOND (subtype);
18410 fixp = (fixS *) fragp->fr_opcode;
18412 /* If the delay slot chosen does not match the size of the instruction,
18413 then emit a warning. */
18414 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
18415 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
18420 s = subtype & (RELAX_DELAY_SLOT_16BIT
18421 | RELAX_DELAY_SLOT_SIZE_FIRST
18422 | RELAX_DELAY_SLOT_SIZE_SECOND);
18423 msg = macro_warning (s);
18425 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18429 /* Possibly emit a warning if we've chosen the longer option. */
18430 if (use_second == second_longer)
18436 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
18437 msg = macro_warning (s);
18439 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18443 /* Go through all the fixups for the first sequence. Disable them
18444 (by marking them as done) if we're going to use the second
18445 sequence instead. */
18447 && fixp->fx_frag == fragp
18448 && fixp->fx_where < fragp->fr_fix - second)
18450 if (subtype & RELAX_USE_SECOND)
18452 fixp = fixp->fx_next;
18455 /* Go through the fixups for the second sequence. Disable them if
18456 we're going to use the first sequence, otherwise adjust their
18457 addresses to account for the relaxation. */
18458 while (fixp && fixp->fx_frag == fragp)
18460 if (subtype & RELAX_USE_SECOND)
18461 fixp->fx_where -= first;
18464 fixp = fixp->fx_next;
18467 /* Now modify the frag contents. */
18468 if (subtype & RELAX_USE_SECOND)
18472 start = fragp->fr_literal + fragp->fr_fix - first - second;
18473 memmove (start, start + first, second);
18474 fragp->fr_fix -= first;
18477 fragp->fr_fix -= second;
18481 /* This function is called after the relocs have been generated.
18482 We've been storing mips16 text labels as odd. Here we convert them
18483 back to even for the convenience of the debugger. */
18486 mips_frob_file_after_relocs (void)
18489 unsigned int count, i;
18491 syms = bfd_get_outsymbols (stdoutput);
18492 count = bfd_get_symcount (stdoutput);
18493 for (i = 0; i < count; i++, syms++)
18494 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
18495 && ((*syms)->value & 1) != 0)
18497 (*syms)->value &= ~1;
18498 /* If the symbol has an odd size, it was probably computed
18499 incorrectly, so adjust that as well. */
18500 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
18501 ++elf_symbol (*syms)->internal_elf_sym.st_size;
18505 /* This function is called whenever a label is defined, including fake
18506 labels instantiated off the dot special symbol. It is used when
18507 handling branch delays; if a branch has a label, we assume we cannot
18508 move it. This also bumps the value of the symbol by 1 in compressed
18512 mips_record_label (symbolS *sym)
18514 segment_info_type *si = seg_info (now_seg);
18515 struct insn_label_list *l;
18517 if (free_insn_labels == NULL)
18518 l = XNEW (struct insn_label_list);
18521 l = free_insn_labels;
18522 free_insn_labels = l->next;
18526 l->next = si->label_list;
18527 si->label_list = l;
18530 /* This function is called as tc_frob_label() whenever a label is defined
18531 and adds a DWARF-2 record we only want for true labels. */
18534 mips_define_label (symbolS *sym)
18536 mips_record_label (sym);
18537 dwarf2_emit_label (sym);
18540 /* This function is called by tc_new_dot_label whenever a new dot symbol
18544 mips_add_dot_label (symbolS *sym)
18546 mips_record_label (sym);
18547 if (mips_assembling_insn && HAVE_CODE_COMPRESSION)
18548 mips_compressed_mark_label (sym);
18551 /* Converting ASE flags from internal to .MIPS.abiflags values. */
18552 static unsigned int
18553 mips_convert_ase_flags (int ase)
18555 unsigned int ext_ases = 0;
18558 ext_ases |= AFL_ASE_DSP;
18559 if (ase & ASE_DSPR2)
18560 ext_ases |= AFL_ASE_DSPR2;
18561 if (ase & ASE_DSPR3)
18562 ext_ases |= AFL_ASE_DSPR3;
18564 ext_ases |= AFL_ASE_EVA;
18566 ext_ases |= AFL_ASE_MCU;
18567 if (ase & ASE_MDMX)
18568 ext_ases |= AFL_ASE_MDMX;
18569 if (ase & ASE_MIPS3D)
18570 ext_ases |= AFL_ASE_MIPS3D;
18572 ext_ases |= AFL_ASE_MT;
18573 if (ase & ASE_SMARTMIPS)
18574 ext_ases |= AFL_ASE_SMARTMIPS;
18575 if (ase & ASE_VIRT)
18576 ext_ases |= AFL_ASE_VIRT;
18578 ext_ases |= AFL_ASE_MSA;
18580 ext_ases |= AFL_ASE_XPA;
18584 /* Some special processing for a MIPS ELF file. */
18587 mips_elf_final_processing (void)
18590 Elf_Internal_ABIFlags_v0 flags;
18594 switch (file_mips_opts.isa)
18597 flags.isa_level = 1;
18600 flags.isa_level = 2;
18603 flags.isa_level = 3;
18606 flags.isa_level = 4;
18609 flags.isa_level = 5;
18612 flags.isa_level = 32;
18616 flags.isa_level = 32;
18620 flags.isa_level = 32;
18624 flags.isa_level = 32;
18628 flags.isa_level = 32;
18632 flags.isa_level = 64;
18636 flags.isa_level = 64;
18640 flags.isa_level = 64;
18644 flags.isa_level = 64;
18648 flags.isa_level = 64;
18653 flags.gpr_size = file_mips_opts.gp == 32 ? AFL_REG_32 : AFL_REG_64;
18654 flags.cpr1_size = file_mips_opts.soft_float ? AFL_REG_NONE
18655 : (file_mips_opts.ase & ASE_MSA) ? AFL_REG_128
18656 : (file_mips_opts.fp == 64) ? AFL_REG_64
18658 flags.cpr2_size = AFL_REG_NONE;
18659 flags.fp_abi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
18660 Tag_GNU_MIPS_ABI_FP);
18661 flags.isa_ext = bfd_mips_isa_ext (stdoutput);
18662 flags.ases = mips_convert_ase_flags (file_mips_opts.ase);
18663 if (file_ase_mips16)
18664 flags.ases |= AFL_ASE_MIPS16;
18665 if (file_ase_micromips)
18666 flags.ases |= AFL_ASE_MICROMIPS;
18668 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts.isa, file_mips_opts.arch)
18669 || file_mips_opts.fp == 64)
18670 && file_mips_opts.oddspreg)
18671 flags.flags1 |= AFL_FLAGS1_ODDSPREG;
18674 bfd_mips_elf_swap_abiflags_v0_out (stdoutput, &flags,
18675 ((Elf_External_ABIFlags_v0 *)
18678 /* Write out the register information. */
18679 if (mips_abi != N64_ABI)
18683 s.ri_gprmask = mips_gprmask;
18684 s.ri_cprmask[0] = mips_cprmask[0];
18685 s.ri_cprmask[1] = mips_cprmask[1];
18686 s.ri_cprmask[2] = mips_cprmask[2];
18687 s.ri_cprmask[3] = mips_cprmask[3];
18688 /* The gp_value field is set by the MIPS ELF backend. */
18690 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
18691 ((Elf32_External_RegInfo *)
18692 mips_regmask_frag));
18696 Elf64_Internal_RegInfo s;
18698 s.ri_gprmask = mips_gprmask;
18700 s.ri_cprmask[0] = mips_cprmask[0];
18701 s.ri_cprmask[1] = mips_cprmask[1];
18702 s.ri_cprmask[2] = mips_cprmask[2];
18703 s.ri_cprmask[3] = mips_cprmask[3];
18704 /* The gp_value field is set by the MIPS ELF backend. */
18706 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
18707 ((Elf64_External_RegInfo *)
18708 mips_regmask_frag));
18711 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18712 sort of BFD interface for this. */
18713 if (mips_any_noreorder)
18714 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
18715 if (mips_pic != NO_PIC)
18717 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
18718 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18721 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18723 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
18724 defined at present; this might need to change in future. */
18725 if (file_ase_mips16)
18726 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
18727 if (file_ase_micromips)
18728 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
18729 if (file_mips_opts.ase & ASE_MDMX)
18730 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
18732 /* Set the MIPS ELF ABI flags. */
18733 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
18734 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
18735 else if (mips_abi == O64_ABI)
18736 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
18737 else if (mips_abi == EABI_ABI)
18739 if (file_mips_opts.gp == 64)
18740 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
18742 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
18744 else if (mips_abi == N32_ABI)
18745 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
18747 /* Nothing to do for N64_ABI. */
18749 if (mips_32bitmode)
18750 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
18752 if (mips_nan2008 == 1)
18753 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008;
18755 /* 32 bit code with 64 bit FP registers. */
18756 fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
18757 Tag_GNU_MIPS_ABI_FP);
18758 if (fpabi == Val_GNU_MIPS_ABI_FP_OLD_64)
18759 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_FP64;
18762 typedef struct proc {
18764 symbolS *func_end_sym;
18765 unsigned long reg_mask;
18766 unsigned long reg_offset;
18767 unsigned long fpreg_mask;
18768 unsigned long fpreg_offset;
18769 unsigned long frame_offset;
18770 unsigned long frame_reg;
18771 unsigned long pc_reg;
18774 static procS cur_proc;
18775 static procS *cur_proc_ptr;
18776 static int numprocs;
18778 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18779 as "2", and a normal nop as "0". */
18781 #define NOP_OPCODE_MIPS 0
18782 #define NOP_OPCODE_MIPS16 1
18783 #define NOP_OPCODE_MICROMIPS 2
18786 mips_nop_opcode (void)
18788 if (seg_info (now_seg)->tc_segment_info_data.micromips)
18789 return NOP_OPCODE_MICROMIPS;
18790 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
18791 return NOP_OPCODE_MIPS16;
18793 return NOP_OPCODE_MIPS;
18796 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18797 32-bit microMIPS NOPs here (if applicable). */
18800 mips_handle_align (fragS *fragp)
18804 int bytes, size, excess;
18807 if (fragp->fr_type != rs_align_code)
18810 p = fragp->fr_literal + fragp->fr_fix;
18812 switch (nop_opcode)
18814 case NOP_OPCODE_MICROMIPS:
18815 opcode = micromips_nop32_insn.insn_opcode;
18818 case NOP_OPCODE_MIPS16:
18819 opcode = mips16_nop_insn.insn_opcode;
18822 case NOP_OPCODE_MIPS:
18824 opcode = nop_insn.insn_opcode;
18829 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
18830 excess = bytes % size;
18832 /* Handle the leading part if we're not inserting a whole number of
18833 instructions, and make it the end of the fixed part of the frag.
18834 Try to fit in a short microMIPS NOP if applicable and possible,
18835 and use zeroes otherwise. */
18836 gas_assert (excess < 4);
18837 fragp->fr_fix += excess;
18842 /* Fall through. */
18844 if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32)
18846 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2);
18850 /* Fall through. */
18853 /* Fall through. */
18858 md_number_to_chars (p, opcode, size);
18859 fragp->fr_var = size;
18868 if (*input_line_pointer == '-')
18870 ++input_line_pointer;
18873 if (!ISDIGIT (*input_line_pointer))
18874 as_bad (_("expected simple number"));
18875 if (input_line_pointer[0] == '0')
18877 if (input_line_pointer[1] == 'x')
18879 input_line_pointer += 2;
18880 while (ISXDIGIT (*input_line_pointer))
18883 val |= hex_value (*input_line_pointer++);
18885 return negative ? -val : val;
18889 ++input_line_pointer;
18890 while (ISDIGIT (*input_line_pointer))
18893 val |= *input_line_pointer++ - '0';
18895 return negative ? -val : val;
18898 if (!ISDIGIT (*input_line_pointer))
18900 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18901 *input_line_pointer, *input_line_pointer);
18902 as_warn (_("invalid number"));
18905 while (ISDIGIT (*input_line_pointer))
18908 val += *input_line_pointer++ - '0';
18910 return negative ? -val : val;
18913 /* The .file directive; just like the usual .file directive, but there
18914 is an initial number which is the ECOFF file index. In the non-ECOFF
18915 case .file implies DWARF-2. */
18918 s_mips_file (int x ATTRIBUTE_UNUSED)
18920 static int first_file_directive = 0;
18922 if (ECOFF_DEBUGGING)
18931 filename = dwarf2_directive_file (0);
18933 /* Versions of GCC up to 3.1 start files with a ".file"
18934 directive even for stabs output. Make sure that this
18935 ".file" is handled. Note that you need a version of GCC
18936 after 3.1 in order to support DWARF-2 on MIPS. */
18937 if (filename != NULL && ! first_file_directive)
18939 (void) new_logical_line (filename, -1);
18940 s_app_file_string (filename, 0);
18942 first_file_directive = 1;
18946 /* The .loc directive, implying DWARF-2. */
18949 s_mips_loc (int x ATTRIBUTE_UNUSED)
18951 if (!ECOFF_DEBUGGING)
18952 dwarf2_directive_loc (0);
18955 /* The .end directive. */
18958 s_mips_end (int x ATTRIBUTE_UNUSED)
18962 /* Following functions need their own .frame and .cprestore directives. */
18963 mips_frame_reg_valid = 0;
18964 mips_cprestore_valid = 0;
18966 if (!is_end_of_line[(unsigned char) *input_line_pointer])
18969 demand_empty_rest_of_line ();
18974 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
18975 as_warn (_(".end not in text section"));
18979 as_warn (_(".end directive without a preceding .ent directive"));
18980 demand_empty_rest_of_line ();
18986 gas_assert (S_GET_NAME (p));
18987 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
18988 as_warn (_(".end symbol does not match .ent symbol"));
18990 if (debug_type == DEBUG_STABS)
18991 stabs_generate_asm_endfunc (S_GET_NAME (p),
18995 as_warn (_(".end directive missing or unknown symbol"));
18997 /* Create an expression to calculate the size of the function. */
18998 if (p && cur_proc_ptr)
19000 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
19001 expressionS *exp = XNEW (expressionS);
19004 exp->X_op = O_subtract;
19005 exp->X_add_symbol = symbol_temp_new_now ();
19006 exp->X_op_symbol = p;
19007 exp->X_add_number = 0;
19009 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
19012 /* Generate a .pdr section. */
19013 if (!ECOFF_DEBUGGING && mips_flag_pdr)
19015 segT saved_seg = now_seg;
19016 subsegT saved_subseg = now_subseg;
19020 #ifdef md_flush_pending_output
19021 md_flush_pending_output ();
19024 gas_assert (pdr_seg);
19025 subseg_set (pdr_seg, 0);
19027 /* Write the symbol. */
19028 exp.X_op = O_symbol;
19029 exp.X_add_symbol = p;
19030 exp.X_add_number = 0;
19031 emit_expr (&exp, 4);
19033 fragp = frag_more (7 * 4);
19035 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
19036 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
19037 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
19038 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
19039 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
19040 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
19041 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
19043 subseg_set (saved_seg, saved_subseg);
19046 cur_proc_ptr = NULL;
19049 /* The .aent and .ent directives. */
19052 s_mips_ent (int aent)
19056 symbolP = get_symbol ();
19057 if (*input_line_pointer == ',')
19058 ++input_line_pointer;
19059 SKIP_WHITESPACE ();
19060 if (ISDIGIT (*input_line_pointer)
19061 || *input_line_pointer == '-')
19064 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
19065 as_warn (_(".ent or .aent not in text section"));
19067 if (!aent && cur_proc_ptr)
19068 as_warn (_("missing .end"));
19072 /* This function needs its own .frame and .cprestore directives. */
19073 mips_frame_reg_valid = 0;
19074 mips_cprestore_valid = 0;
19076 cur_proc_ptr = &cur_proc;
19077 memset (cur_proc_ptr, '\0', sizeof (procS));
19079 cur_proc_ptr->func_sym = symbolP;
19083 if (debug_type == DEBUG_STABS)
19084 stabs_generate_asm_func (S_GET_NAME (symbolP),
19085 S_GET_NAME (symbolP));
19088 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
19090 demand_empty_rest_of_line ();
19093 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19094 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19095 s_mips_frame is used so that we can set the PDR information correctly.
19096 We can't use the ecoff routines because they make reference to the ecoff
19097 symbol table (in the mdebug section). */
19100 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
19102 if (ECOFF_DEBUGGING)
19108 if (cur_proc_ptr == (procS *) NULL)
19110 as_warn (_(".frame outside of .ent"));
19111 demand_empty_rest_of_line ();
19115 cur_proc_ptr->frame_reg = tc_get_register (1);
19117 SKIP_WHITESPACE ();
19118 if (*input_line_pointer++ != ','
19119 || get_absolute_expression_and_terminator (&val) != ',')
19121 as_warn (_("bad .frame directive"));
19122 --input_line_pointer;
19123 demand_empty_rest_of_line ();
19127 cur_proc_ptr->frame_offset = val;
19128 cur_proc_ptr->pc_reg = tc_get_register (0);
19130 demand_empty_rest_of_line ();
19134 /* The .fmask and .mask directives. If the mdebug section is present
19135 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19136 embedded targets, s_mips_mask is used so that we can set the PDR
19137 information correctly. We can't use the ecoff routines because they
19138 make reference to the ecoff symbol table (in the mdebug section). */
19141 s_mips_mask (int reg_type)
19143 if (ECOFF_DEBUGGING)
19144 s_ignore (reg_type);
19149 if (cur_proc_ptr == (procS *) NULL)
19151 as_warn (_(".mask/.fmask outside of .ent"));
19152 demand_empty_rest_of_line ();
19156 if (get_absolute_expression_and_terminator (&mask) != ',')
19158 as_warn (_("bad .mask/.fmask directive"));
19159 --input_line_pointer;
19160 demand_empty_rest_of_line ();
19164 off = get_absolute_expression ();
19166 if (reg_type == 'F')
19168 cur_proc_ptr->fpreg_mask = mask;
19169 cur_proc_ptr->fpreg_offset = off;
19173 cur_proc_ptr->reg_mask = mask;
19174 cur_proc_ptr->reg_offset = off;
19177 demand_empty_rest_of_line ();
19181 /* A table describing all the processors gas knows about. Names are
19182 matched in the order listed.
19184 To ease comparison, please keep this table in the same order as
19185 gcc's mips_cpu_info_table[]. */
19186 static const struct mips_cpu_info mips_cpu_info_table[] =
19188 /* Entries for generic ISAs */
19189 { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 },
19190 { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 },
19191 { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 },
19192 { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 },
19193 { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 },
19194 { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 },
19195 { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19196 { "mips32r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R3, CPU_MIPS32R3 },
19197 { "mips32r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R5, CPU_MIPS32R5 },
19198 { "mips32r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R6, CPU_MIPS32R6 },
19199 { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 },
19200 { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 },
19201 { "mips64r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R3, CPU_MIPS64R3 },
19202 { "mips64r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R5, CPU_MIPS64R5 },
19203 { "mips64r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R6, CPU_MIPS64R6 },
19206 { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 },
19207 { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 },
19208 { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 },
19211 { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 },
19214 { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 },
19215 { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 },
19216 { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 },
19217 { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 },
19218 { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 },
19219 { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 },
19220 { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 },
19221 { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 },
19222 { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 },
19223 { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 },
19224 { "orion", 0, 0, ISA_MIPS3, CPU_R4600 },
19225 { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 },
19226 { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 },
19227 /* ST Microelectronics Loongson 2E and 2F cores */
19228 { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E },
19229 { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F },
19232 { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 },
19233 { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 },
19234 { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 },
19235 { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 },
19236 { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 },
19237 { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 },
19238 { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 },
19239 { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 },
19240 { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 },
19241 { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 },
19242 { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 },
19243 { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 },
19244 { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 },
19245 { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 },
19246 { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 },
19249 { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19250 { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19251 { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19252 { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
19254 /* MIPS 32 Release 2 */
19255 { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19256 { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19257 { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19258 { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
19259 { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19260 { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19261 { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19262 { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19263 { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
19264 ISA_MIPS32R2, CPU_MIPS32R2 },
19265 { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
19266 ISA_MIPS32R2, CPU_MIPS32R2 },
19267 { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19268 { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19269 { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19270 { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19271 /* Deprecated forms of the above. */
19272 { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19273 { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19274 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19275 { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19276 { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19277 { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19278 { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19279 /* Deprecated forms of the above. */
19280 { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19281 { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19282 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19283 { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19284 { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19285 { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19286 { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19287 /* Deprecated forms of the above. */
19288 { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19289 { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19290 /* 34Kn is a 34kc without DSP. */
19291 { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19292 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19293 { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19294 { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19295 { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19296 { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19297 { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19298 /* Deprecated forms of the above. */
19299 { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19300 { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19301 /* 1004K cores are multiprocessor versions of the 34K. */
19302 { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19303 { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19304 { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19305 { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19306 /* interaptiv is the new name for 1004kf */
19307 { "interaptiv", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19309 { "m5100", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 },
19310 { "m5101", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 },
19311 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
19312 { "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R5, CPU_MIPS32R5 },
19315 { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 },
19316 { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 },
19317 { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19318 { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19320 /* Broadcom SB-1 CPU core */
19321 { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
19322 /* Broadcom SB-1A CPU core */
19323 { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
19325 { "loongson3a", 0, 0, ISA_MIPS64R2, CPU_LOONGSON_3A },
19327 /* MIPS 64 Release 2 */
19329 /* Cavium Networks Octeon CPU core */
19330 { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
19331 { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP },
19332 { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 },
19333 { "octeon3", 0, ASE_VIRT | ASE_VIRT64, ISA_MIPS64R5, CPU_OCTEON3 },
19336 { "xlr", 0, 0, ISA_MIPS64, CPU_XLR },
19339 XLP is mostly like XLR, with the prominent exception that it is
19340 MIPS64R2 rather than MIPS64. */
19341 { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
19343 /* MIPS 64 Release 6 */
19344 { "i6400", 0, ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6},
19345 { "p6600", 0, ASE_VIRT | ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6},
19348 { NULL, 0, 0, 0, 0 }
19352 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19353 with a final "000" replaced by "k". Ignore case.
19355 Note: this function is shared between GCC and GAS. */
19358 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
19360 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
19361 given++, canonical++;
19363 return ((*given == 0 && *canonical == 0)
19364 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
19368 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19369 CPU name. We've traditionally allowed a lot of variation here.
19371 Note: this function is shared between GCC and GAS. */
19374 mips_matching_cpu_name_p (const char *canonical, const char *given)
19376 /* First see if the name matches exactly, or with a final "000"
19377 turned into "k". */
19378 if (mips_strict_matching_cpu_name_p (canonical, given))
19381 /* If not, try comparing based on numerical designation alone.
19382 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19383 if (TOLOWER (*given) == 'r')
19385 if (!ISDIGIT (*given))
19388 /* Skip over some well-known prefixes in the canonical name,
19389 hoping to find a number there too. */
19390 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
19392 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
19394 else if (TOLOWER (canonical[0]) == 'r')
19397 return mips_strict_matching_cpu_name_p (canonical, given);
19401 /* Parse an option that takes the name of a processor as its argument.
19402 OPTION is the name of the option and CPU_STRING is the argument.
19403 Return the corresponding processor enumeration if the CPU_STRING is
19404 recognized, otherwise report an error and return null.
19406 A similar function exists in GCC. */
19408 static const struct mips_cpu_info *
19409 mips_parse_cpu (const char *option, const char *cpu_string)
19411 const struct mips_cpu_info *p;
19413 /* 'from-abi' selects the most compatible architecture for the given
19414 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19415 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19416 version. Look first at the -mgp options, if given, otherwise base
19417 the choice on MIPS_DEFAULT_64BIT.
19419 Treat NO_ABI like the EABIs. One reason to do this is that the
19420 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19421 architecture. This code picks MIPS I for 'mips' and MIPS III for
19422 'mips64', just as we did in the days before 'from-abi'. */
19423 if (strcasecmp (cpu_string, "from-abi") == 0)
19425 if (ABI_NEEDS_32BIT_REGS (mips_abi))
19426 return mips_cpu_info_from_isa (ISA_MIPS1);
19428 if (ABI_NEEDS_64BIT_REGS (mips_abi))
19429 return mips_cpu_info_from_isa (ISA_MIPS3);
19431 if (file_mips_opts.gp >= 0)
19432 return mips_cpu_info_from_isa (file_mips_opts.gp == 32
19433 ? ISA_MIPS1 : ISA_MIPS3);
19435 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19440 /* 'default' has traditionally been a no-op. Probably not very useful. */
19441 if (strcasecmp (cpu_string, "default") == 0)
19444 for (p = mips_cpu_info_table; p->name != 0; p++)
19445 if (mips_matching_cpu_name_p (p->name, cpu_string))
19448 as_bad (_("bad value (%s) for %s"), cpu_string, option);
19452 /* Return the canonical processor information for ISA (a member of the
19453 ISA_MIPS* enumeration). */
19455 static const struct mips_cpu_info *
19456 mips_cpu_info_from_isa (int isa)
19460 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19461 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
19462 && isa == mips_cpu_info_table[i].isa)
19463 return (&mips_cpu_info_table[i]);
19468 static const struct mips_cpu_info *
19469 mips_cpu_info_from_arch (int arch)
19473 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19474 if (arch == mips_cpu_info_table[i].cpu)
19475 return (&mips_cpu_info_table[i]);
19481 show (FILE *stream, const char *string, int *col_p, int *first_p)
19485 fprintf (stream, "%24s", "");
19490 fprintf (stream, ", ");
19494 if (*col_p + strlen (string) > 72)
19496 fprintf (stream, "\n%24s", "");
19500 fprintf (stream, "%s", string);
19501 *col_p += strlen (string);
19507 md_show_usage (FILE *stream)
19512 fprintf (stream, _("\
19514 -EB generate big endian output\n\
19515 -EL generate little endian output\n\
19516 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19517 -G NUM allow referencing objects up to NUM bytes\n\
19518 implicitly with the gp register [default 8]\n"));
19519 fprintf (stream, _("\
19520 -mips1 generate MIPS ISA I instructions\n\
19521 -mips2 generate MIPS ISA II instructions\n\
19522 -mips3 generate MIPS ISA III instructions\n\
19523 -mips4 generate MIPS ISA IV instructions\n\
19524 -mips5 generate MIPS ISA V instructions\n\
19525 -mips32 generate MIPS32 ISA instructions\n\
19526 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19527 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
19528 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
19529 -mips32r6 generate MIPS32 release 6 ISA instructions\n\
19530 -mips64 generate MIPS64 ISA instructions\n\
19531 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19532 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
19533 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
19534 -mips64r6 generate MIPS64 release 6 ISA instructions\n\
19535 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19539 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19540 show (stream, mips_cpu_info_table[i].name, &column, &first);
19541 show (stream, "from-abi", &column, &first);
19542 fputc ('\n', stream);
19544 fprintf (stream, _("\
19545 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19546 -no-mCPU don't generate code specific to CPU.\n\
19547 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19551 show (stream, "3900", &column, &first);
19552 show (stream, "4010", &column, &first);
19553 show (stream, "4100", &column, &first);
19554 show (stream, "4650", &column, &first);
19555 fputc ('\n', stream);
19557 fprintf (stream, _("\
19558 -mips16 generate mips16 instructions\n\
19559 -no-mips16 do not generate mips16 instructions\n"));
19560 fprintf (stream, _("\
19561 -mmicromips generate microMIPS instructions\n\
19562 -mno-micromips do not generate microMIPS instructions\n"));
19563 fprintf (stream, _("\
19564 -msmartmips generate smartmips instructions\n\
19565 -mno-smartmips do not generate smartmips instructions\n"));
19566 fprintf (stream, _("\
19567 -mdsp generate DSP instructions\n\
19568 -mno-dsp do not generate DSP instructions\n"));
19569 fprintf (stream, _("\
19570 -mdspr2 generate DSP R2 instructions\n\
19571 -mno-dspr2 do not generate DSP R2 instructions\n"));
19572 fprintf (stream, _("\
19573 -mdspr3 generate DSP R3 instructions\n\
19574 -mno-dspr3 do not generate DSP R3 instructions\n"));
19575 fprintf (stream, _("\
19576 -mmt generate MT instructions\n\
19577 -mno-mt do not generate MT instructions\n"));
19578 fprintf (stream, _("\
19579 -mmcu generate MCU instructions\n\
19580 -mno-mcu do not generate MCU instructions\n"));
19581 fprintf (stream, _("\
19582 -mmsa generate MSA instructions\n\
19583 -mno-msa do not generate MSA instructions\n"));
19584 fprintf (stream, _("\
19585 -mxpa generate eXtended Physical Address (XPA) instructions\n\
19586 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
19587 fprintf (stream, _("\
19588 -mvirt generate Virtualization instructions\n\
19589 -mno-virt do not generate Virtualization instructions\n"));
19590 fprintf (stream, _("\
19591 -minsn32 only generate 32-bit microMIPS instructions\n\
19592 -mno-insn32 generate all microMIPS instructions\n"));
19593 fprintf (stream, _("\
19594 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19595 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19596 -mfix-vr4120 work around certain VR4120 errata\n\
19597 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19598 -mfix-24k insert a nop after ERET and DERET instructions\n\
19599 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19600 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19601 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19602 -msym32 assume all symbols have 32-bit values\n\
19603 -O0 remove unneeded NOPs, do not swap branches\n\
19604 -O remove unneeded NOPs and swap branches\n\
19605 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19606 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19607 fprintf (stream, _("\
19608 -mhard-float allow floating-point instructions\n\
19609 -msoft-float do not allow floating-point instructions\n\
19610 -msingle-float only allow 32-bit floating-point operations\n\
19611 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19612 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
19613 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
19614 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
19618 show (stream, "legacy", &column, &first);
19619 show (stream, "2008", &column, &first);
19621 fputc ('\n', stream);
19623 fprintf (stream, _("\
19624 -KPIC, -call_shared generate SVR4 position independent code\n\
19625 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19626 -mvxworks-pic generate VxWorks position independent code\n\
19627 -non_shared do not generate code that can operate with DSOs\n\
19628 -xgot assume a 32 bit GOT\n\
19629 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19630 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19631 position dependent (non shared) code\n\
19632 -mabi=ABI create ABI conformant object file for:\n"));
19636 show (stream, "32", &column, &first);
19637 show (stream, "o64", &column, &first);
19638 show (stream, "n32", &column, &first);
19639 show (stream, "64", &column, &first);
19640 show (stream, "eabi", &column, &first);
19642 fputc ('\n', stream);
19644 fprintf (stream, _("\
19645 -32 create o32 ABI object file (default)\n\
19646 -n32 create n32 ABI object file\n\
19647 -64 create 64 ABI object file\n"));
19652 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
19654 if (HAVE_64BIT_SYMBOLS)
19655 return dwarf2_format_64bit_irix;
19657 return dwarf2_format_32bit;
19662 mips_dwarf2_addr_size (void)
19664 if (HAVE_64BIT_OBJECTS)
19670 /* Standard calling conventions leave the CFA at SP on entry. */
19672 mips_cfi_frame_initial_instructions (void)
19674 cfi_add_CFA_def_cfa_register (SP);
19678 tc_mips_regname_to_dw2regnum (char *regname)
19680 unsigned int regnum = -1;
19683 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))
19689 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
19690 Given a symbolic attribute NAME, return the proper integer value.
19691 Returns -1 if the attribute is not known. */
19694 mips_convert_symbolic_attribute (const char *name)
19696 static const struct
19701 attribute_table[] =
19703 #define T(tag) {#tag, tag}
19704 T (Tag_GNU_MIPS_ABI_FP),
19705 T (Tag_GNU_MIPS_ABI_MSA),
19713 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
19714 if (streq (name, attribute_table[i].name))
19715 return attribute_table[i].tag;
19723 int fpabi = Val_GNU_MIPS_ABI_FP_ANY;
19725 mips_emit_delays ();
19727 as_warn (_("missing .end at end of assembly"));
19729 /* Just in case no code was emitted, do the consistency check. */
19730 file_mips_check_options ();
19732 /* Set a floating-point ABI if the user did not. */
19733 if (obj_elf_seen_attribute (OBJ_ATTR_GNU, Tag_GNU_MIPS_ABI_FP))
19735 /* Perform consistency checks on the floating-point ABI. */
19736 fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
19737 Tag_GNU_MIPS_ABI_FP);
19738 if (fpabi != Val_GNU_MIPS_ABI_FP_ANY)
19739 check_fpabi (fpabi);
19743 /* Soft-float gets precedence over single-float, the two options should
19744 not be used together so this should not matter. */
19745 if (file_mips_opts.soft_float == 1)
19746 fpabi = Val_GNU_MIPS_ABI_FP_SOFT;
19747 /* Single-float gets precedence over all double_float cases. */
19748 else if (file_mips_opts.single_float == 1)
19749 fpabi = Val_GNU_MIPS_ABI_FP_SINGLE;
19752 switch (file_mips_opts.fp)
19755 if (file_mips_opts.gp == 32)
19756 fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE;
19759 fpabi = Val_GNU_MIPS_ABI_FP_XX;
19762 if (file_mips_opts.gp == 32 && !file_mips_opts.oddspreg)
19763 fpabi = Val_GNU_MIPS_ABI_FP_64A;
19764 else if (file_mips_opts.gp == 32)
19765 fpabi = Val_GNU_MIPS_ABI_FP_64;
19767 fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE;
19772 bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
19773 Tag_GNU_MIPS_ABI_FP, fpabi);
19777 /* Returns the relocation type required for a particular CFI encoding. */
19779 bfd_reloc_code_real_type
19780 mips_cfi_reloc_for_encoding (int encoding)
19782 if (encoding == (DW_EH_PE_sdata4 | DW_EH_PE_pcrel))
19783 return BFD_RELOC_32_PCREL;
19784 else return BFD_RELOC_NONE;