1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
38 #include "opcode/mips.h"
40 #include "dwarf2dbg.h"
43 #define DBG(x) printf x
49 /* Clean up namespace so we can include obj-elf.h too. */
50 static int mips_output_flavor PARAMS ((void));
51 static int mips_output_flavor () { return OUTPUT_FLAVOR; }
52 #undef OBJ_PROCESS_STAB
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
80 int mips_flag_mdebug = -1;
84 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
85 static char *mips_regmask_frag;
91 #define PIC_CALL_REG 25
99 #define ILLEGAL_REG (32)
101 /* Allow override of standard little-endian ECOFF format. */
103 #ifndef ECOFF_LITTLE_FORMAT
104 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
107 extern int target_big_endian;
109 /* The name of the readonly data section. */
110 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
112 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
114 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
120 /* The ABI to use. */
131 /* MIPS ABI we are using for this output file. */
132 static enum mips_abi_level mips_abi = NO_ABI;
134 /* Whether or not we have code that can call pic code. */
135 int mips_abicalls = FALSE;
137 /* This is the set of options which may be modified by the .set
138 pseudo-op. We use a struct so that .set push and .set pop are more
141 struct mips_set_options
143 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
144 if it has not been initialized. Changed by `.set mipsN', and the
145 -mipsN command line option, and the default CPU. */
147 /* Enabled Application Specific Extensions (ASEs). These are set to -1
148 if they have not been initialized. Changed by `.set <asename>', by
149 command line options, and based on the default architecture. */
152 /* Whether we are assembling for the mips16 processor. 0 if we are
153 not, 1 if we are, and -1 if the value has not been initialized.
154 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
155 -nomips16 command line options, and the default CPU. */
157 /* Non-zero if we should not reorder instructions. Changed by `.set
158 reorder' and `.set noreorder'. */
160 /* Non-zero if we should not permit the $at ($1) register to be used
161 in instructions. Changed by `.set at' and `.set noat'. */
163 /* Non-zero if we should warn when a macro instruction expands into
164 more than one machine instruction. Changed by `.set nomacro' and
166 int warn_about_macros;
167 /* Non-zero if we should not move instructions. Changed by `.set
168 move', `.set volatile', `.set nomove', and `.set novolatile'. */
170 /* Non-zero if we should not optimize branches by moving the target
171 of the branch into the delay slot. Actually, we don't perform
172 this optimization anyhow. Changed by `.set bopt' and `.set
175 /* Non-zero if we should not autoextend mips16 instructions.
176 Changed by `.set autoextend' and `.set noautoextend'. */
178 /* Restrict general purpose registers and floating point registers
179 to 32 bit. This is initially determined when -mgp32 or -mfp32
180 is passed but can changed if the assembler code uses .set mipsN. */
183 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
184 command line option, and the default CPU. */
188 /* True if -mgp32 was passed. */
189 static int file_mips_gp32 = -1;
191 /* True if -mfp32 was passed. */
192 static int file_mips_fp32 = -1;
194 /* This is the struct we use to hold the current set of options. Note
195 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
196 -1 to indicate that they have not been initialized. */
198 static struct mips_set_options mips_opts =
200 ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
203 /* These variables are filled in with the masks of registers used.
204 The object format code reads them and puts them in the appropriate
206 unsigned long mips_gprmask;
207 unsigned long mips_cprmask[4];
209 /* MIPS ISA we are using for this output file. */
210 static int file_mips_isa = ISA_UNKNOWN;
212 /* True if -mips16 was passed or implied by arguments passed on the
213 command line (e.g., by -march). */
214 static int file_ase_mips16;
216 /* True if -mips3d was passed or implied by arguments passed on the
217 command line (e.g., by -march). */
218 static int file_ase_mips3d;
220 /* True if -mdmx was passed or implied by arguments passed on the
221 command line (e.g., by -march). */
222 static int file_ase_mdmx;
224 /* The argument of the -march= flag. The architecture we are assembling. */
225 static int file_mips_arch = CPU_UNKNOWN;
226 static const char *mips_arch_string;
228 /* The argument of the -mtune= flag. The architecture for which we
230 static int mips_tune = CPU_UNKNOWN;
231 static const char *mips_tune_string;
233 /* True when generating 32-bit code for a 64-bit processor. */
234 static int mips_32bitmode = 0;
236 /* Some ISA's have delay slots for instructions which read or write
237 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
238 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
239 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
240 delay slot in this ISA. The uses of this macro assume that any
241 ISA that has delay slots for one of these, has them for all. They
242 also assume that ISAs which don't have delays for these insns, don't
243 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
244 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
246 || (ISA) == ISA_MIPS2 \
247 || (ISA) == ISA_MIPS3 \
250 /* True if the given ABI requires 32-bit registers. */
251 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
253 /* Likewise 64-bit registers. */
254 #define ABI_NEEDS_64BIT_REGS(ABI) \
256 || (ABI) == N64_ABI \
259 /* Return true if ISA supports 64 bit gp register instructions. */
260 #define ISA_HAS_64BIT_REGS(ISA) ( \
262 || (ISA) == ISA_MIPS4 \
263 || (ISA) == ISA_MIPS5 \
264 || (ISA) == ISA_MIPS64 \
267 /* Return true if ISA supports 64-bit right rotate (dror et al.)
269 #define ISA_HAS_DROR(ISA) ( \
273 /* Return true if ISA supports 32-bit right rotate (ror et al.)
275 #define ISA_HAS_ROR(ISA) ( \
276 (ISA) == ISA_MIPS32R2 \
279 #define HAVE_32BIT_GPRS \
280 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
282 #define HAVE_32BIT_FPRS \
283 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
285 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
286 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
288 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
290 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
292 /* We can only have 64bit addresses if the object file format
294 #define HAVE_32BIT_ADDRESSES \
296 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
297 || ! HAVE_64BIT_OBJECTS) \
298 && mips_pic != EMBEDDED_PIC))
300 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
301 #define HAVE_64BIT_ADDRESS_CONSTANTS (HAVE_64BIT_ADDRESSES \
304 /* Addresses are loaded in different ways, depending on the address size
305 in use. The n32 ABI Documentation also mandates the use of additions
306 with overflow checking, but existing implementations don't follow it. */
307 #define ADDRESS_ADD_INSN \
308 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
310 #define ADDRESS_ADDI_INSN \
311 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
313 #define ADDRESS_LOAD_INSN \
314 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
316 #define ADDRESS_STORE_INSN \
317 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
319 /* Return true if the given CPU supports the MIPS16 ASE. */
320 #define CPU_HAS_MIPS16(cpu) \
321 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
322 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
324 /* Return true if the given CPU supports the MIPS3D ASE. */
325 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
328 /* Return true if the given CPU supports the MDMX ASE. */
329 #define CPU_HAS_MDMX(cpu) (FALSE \
332 /* True if CPU has a dror instruction. */
333 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
335 /* True if CPU has a ror instruction. */
336 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
338 /* Whether the processor uses hardware interlocks to protect
339 reads from the HI and LO registers, and thus does not
340 require nops to be inserted. */
342 #define hilo_interlocks (mips_opts.arch == CPU_R4010 \
343 || mips_opts.arch == CPU_VR5500 \
344 || mips_opts.arch == CPU_SB1 \
347 /* Whether the processor uses hardware interlocks to protect reads
348 from the GPRs, and thus does not require nops to be inserted. */
349 #define gpr_interlocks \
350 (mips_opts.isa != ISA_MIPS1 \
351 || mips_opts.arch == CPU_VR5400 \
352 || mips_opts.arch == CPU_VR5500 \
353 || mips_opts.arch == CPU_R3900)
355 /* As with other "interlocks" this is used by hardware that has FP
356 (co-processor) interlocks. */
357 /* Itbl support may require additional care here. */
358 #define cop_interlocks (mips_opts.arch == CPU_R4300 \
359 || mips_opts.arch == CPU_VR5400 \
360 || mips_opts.arch == CPU_VR5500 \
361 || mips_opts.arch == CPU_SB1 \
364 /* Is this a mfhi or mflo instruction? */
365 #define MF_HILO_INSN(PINFO) \
366 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
368 /* MIPS PIC level. */
370 enum mips_pic_level mips_pic;
372 /* Warn about all NOPS that the assembler generates. */
373 static int warn_nops = 0;
375 /* 1 if we should generate 32 bit offsets from the $gp register in
376 SVR4_PIC mode. Currently has no meaning in other modes. */
377 static int mips_big_got = 0;
379 /* 1 if trap instructions should used for overflow rather than break
381 static int mips_trap = 0;
383 /* 1 if double width floating point constants should not be constructed
384 by assembling two single width halves into two single width floating
385 point registers which just happen to alias the double width destination
386 register. On some architectures this aliasing can be disabled by a bit
387 in the status register, and the setting of this bit cannot be determined
388 automatically at assemble time. */
389 static int mips_disable_float_construction;
391 /* Non-zero if any .set noreorder directives were used. */
393 static int mips_any_noreorder;
395 /* Non-zero if nops should be inserted when the register referenced in
396 an mfhi/mflo instruction is read in the next two instructions. */
397 static int mips_7000_hilo_fix;
399 /* The size of the small data section. */
400 static unsigned int g_switch_value = 8;
401 /* Whether the -G option was used. */
402 static int g_switch_seen = 0;
407 /* If we can determine in advance that GP optimization won't be
408 possible, we can skip the relaxation stuff that tries to produce
409 GP-relative references. This makes delay slot optimization work
412 This function can only provide a guess, but it seems to work for
413 gcc output. It needs to guess right for gcc, otherwise gcc
414 will put what it thinks is a GP-relative instruction in a branch
417 I don't know if a fix is needed for the SVR4_PIC mode. I've only
418 fixed it for the non-PIC mode. KR 95/04/07 */
419 static int nopic_need_relax PARAMS ((symbolS *, int));
421 /* handle of the OPCODE hash table */
422 static struct hash_control *op_hash = NULL;
424 /* The opcode hash table we use for the mips16. */
425 static struct hash_control *mips16_op_hash = NULL;
427 /* This array holds the chars that always start a comment. If the
428 pre-processor is disabled, these aren't very useful */
429 const char comment_chars[] = "#";
431 /* This array holds the chars that only start a comment at the beginning of
432 a line. If the line seems to have the form '# 123 filename'
433 .line and .file directives will appear in the pre-processed output */
434 /* Note that input_file.c hand checks for '#' at the beginning of the
435 first line of the input file. This is because the compiler outputs
436 #NO_APP at the beginning of its output. */
437 /* Also note that C style comments are always supported. */
438 const char line_comment_chars[] = "#";
440 /* This array holds machine specific line separator characters. */
441 const char line_separator_chars[] = ";";
443 /* Chars that can be used to separate mant from exp in floating point nums */
444 const char EXP_CHARS[] = "eE";
446 /* Chars that mean this number is a floating point constant */
449 const char FLT_CHARS[] = "rRsSfFdDxXpP";
451 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
452 changed in read.c . Ideally it shouldn't have to know about it at all,
453 but nothing is ideal around here.
456 static char *insn_error;
458 static int auto_align = 1;
460 /* When outputting SVR4 PIC code, the assembler needs to know the
461 offset in the stack frame from which to restore the $gp register.
462 This is set by the .cprestore pseudo-op, and saved in this
464 static offsetT mips_cprestore_offset = -1;
466 /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some
467 more optimizations, it can use a register value instead of a memory-saved
468 offset and even an other register than $gp as global pointer. */
469 static offsetT mips_cpreturn_offset = -1;
470 static int mips_cpreturn_register = -1;
471 static int mips_gp_register = GP;
472 static int mips_gprel_offset = 0;
474 /* Whether mips_cprestore_offset has been set in the current function
475 (or whether it has already been warned about, if not). */
476 static int mips_cprestore_valid = 0;
478 /* This is the register which holds the stack frame, as set by the
479 .frame pseudo-op. This is needed to implement .cprestore. */
480 static int mips_frame_reg = SP;
482 /* Whether mips_frame_reg has been set in the current function
483 (or whether it has already been warned about, if not). */
484 static int mips_frame_reg_valid = 0;
486 /* To output NOP instructions correctly, we need to keep information
487 about the previous two instructions. */
489 /* Whether we are optimizing. The default value of 2 means to remove
490 unneeded NOPs and swap branch instructions when possible. A value
491 of 1 means to not swap branches. A value of 0 means to always
493 static int mips_optimize = 2;
495 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
496 equivalent to seeing no -g option at all. */
497 static int mips_debug = 0;
499 /* The previous instruction. */
500 static struct mips_cl_insn prev_insn;
502 /* The instruction before prev_insn. */
503 static struct mips_cl_insn prev_prev_insn;
505 /* If we don't want information for prev_insn or prev_prev_insn, we
506 point the insn_mo field at this dummy integer. */
507 static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 };
509 /* Non-zero if prev_insn is valid. */
510 static int prev_insn_valid;
512 /* The frag for the previous instruction. */
513 static struct frag *prev_insn_frag;
515 /* The offset into prev_insn_frag for the previous instruction. */
516 static long prev_insn_where;
518 /* The reloc type for the previous instruction, if any. */
519 static bfd_reloc_code_real_type prev_insn_reloc_type[3];
521 /* The reloc for the previous instruction, if any. */
522 static fixS *prev_insn_fixp[3];
524 /* Non-zero if the previous instruction was in a delay slot. */
525 static int prev_insn_is_delay_slot;
527 /* Non-zero if the previous instruction was in a .set noreorder. */
528 static int prev_insn_unreordered;
530 /* Non-zero if the previous instruction uses an extend opcode (if
532 static int prev_insn_extended;
534 /* Non-zero if the previous previous instruction was in a .set
536 static int prev_prev_insn_unreordered;
538 /* If this is set, it points to a frag holding nop instructions which
539 were inserted before the start of a noreorder section. If those
540 nops turn out to be unnecessary, the size of the frag can be
542 static fragS *prev_nop_frag;
544 /* The number of nop instructions we created in prev_nop_frag. */
545 static int prev_nop_frag_holds;
547 /* The number of nop instructions that we know we need in
549 static int prev_nop_frag_required;
551 /* The number of instructions we've seen since prev_nop_frag. */
552 static int prev_nop_frag_since;
554 /* For ECOFF and ELF, relocations against symbols are done in two
555 parts, with a HI relocation and a LO relocation. Each relocation
556 has only 16 bits of space to store an addend. This means that in
557 order for the linker to handle carries correctly, it must be able
558 to locate both the HI and the LO relocation. This means that the
559 relocations must appear in order in the relocation table.
561 In order to implement this, we keep track of each unmatched HI
562 relocation. We then sort them so that they immediately precede the
563 corresponding LO relocation. */
568 struct mips_hi_fixup *next;
571 /* The section this fixup is in. */
575 /* The list of unmatched HI relocs. */
577 static struct mips_hi_fixup *mips_hi_fixup_list;
579 /* The frag containing the last explicit relocation operator.
580 Null if explicit relocations have not been used. */
582 static fragS *prev_reloc_op_frag;
584 /* Map normal MIPS register numbers to mips16 register numbers. */
586 #define X ILLEGAL_REG
587 static const int mips32_to_16_reg_map[] =
589 X, X, 2, 3, 4, 5, 6, 7,
590 X, X, X, X, X, X, X, X,
591 0, 1, X, X, X, X, X, X,
592 X, X, X, X, X, X, X, X
596 /* Map mips16 register numbers to normal MIPS register numbers. */
598 static const unsigned int mips16_to_32_reg_map[] =
600 16, 17, 2, 3, 4, 5, 6, 7
603 static int mips_fix_4122_bugs;
605 /* We don't relax branches by default, since this causes us to expand
606 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
607 fail to compute the offset before expanding the macro to the most
608 efficient expansion. */
610 static int mips_relax_branch;
612 /* Since the MIPS does not have multiple forms of PC relative
613 instructions, we do not have to do relaxing as is done on other
614 platforms. However, we do have to handle GP relative addressing
615 correctly, which turns out to be a similar problem.
617 Every macro that refers to a symbol can occur in (at least) two
618 forms, one with GP relative addressing and one without. For
619 example, loading a global variable into a register generally uses
620 a macro instruction like this:
622 If i can be addressed off the GP register (this is true if it is in
623 the .sbss or .sdata section, or if it is known to be smaller than
624 the -G argument) this will generate the following instruction:
626 This instruction will use a GPREL reloc. If i can not be addressed
627 off the GP register, the following instruction sequence will be used:
630 In this case the first instruction will have a HI16 reloc, and the
631 second reloc will have a LO16 reloc. Both relocs will be against
634 The issue here is that we may not know whether i is GP addressable
635 until after we see the instruction that uses it. Therefore, we
636 want to be able to choose the final instruction sequence only at
637 the end of the assembly. This is similar to the way other
638 platforms choose the size of a PC relative instruction only at the
641 When generating position independent code we do not use GP
642 addressing in quite the same way, but the issue still arises as
643 external symbols and local symbols must be handled differently.
645 We handle these issues by actually generating both possible
646 instruction sequences. The longer one is put in a frag_var with
647 type rs_machine_dependent. We encode what to do with the frag in
648 the subtype field. We encode (1) the number of existing bytes to
649 replace, (2) the number of new bytes to use, (3) the offset from
650 the start of the existing bytes to the first reloc we must generate
651 (that is, the offset is applied from the start of the existing
652 bytes after they are replaced by the new bytes, if any), (4) the
653 offset from the start of the existing bytes to the second reloc,
654 (5) whether a third reloc is needed (the third reloc is always four
655 bytes after the second reloc), and (6) whether to warn if this
656 variant is used (this is sometimes needed if .set nomacro or .set
657 noat is in effect). All these numbers are reasonably small.
659 Generating two instruction sequences must be handled carefully to
660 ensure that delay slots are handled correctly. Fortunately, there
661 are a limited number of cases. When the second instruction
662 sequence is generated, append_insn is directed to maintain the
663 existing delay slot information, so it continues to apply to any
664 code after the second instruction sequence. This means that the
665 second instruction sequence must not impose any requirements not
666 required by the first instruction sequence.
668 These variant frags are then handled in functions called by the
669 machine independent code. md_estimate_size_before_relax returns
670 the final size of the frag. md_convert_frag sets up the final form
671 of the frag. tc_gen_reloc adjust the first reloc and adds a second
673 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
677 | (((reloc1) + 64) << 9) \
678 | (((reloc2) + 64) << 2) \
679 | ((reloc3) ? (1 << 1) : 0) \
681 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
682 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
683 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
684 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
685 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
686 #define RELAX_WARN(i) ((i) & 1)
688 /* Branch without likely bit. If label is out of range, we turn:
690 beq reg1, reg2, label
700 with the following opcode replacements:
707 bltzal <-> bgezal (with jal label instead of j label)
709 Even though keeping the delay slot instruction in the delay slot of
710 the branch would be more efficient, it would be very tricky to do
711 correctly, because we'd have to introduce a variable frag *after*
712 the delay slot instruction, and expand that instead. Let's do it
713 the easy way for now, even if the branch-not-taken case now costs
714 one additional instruction. Out-of-range branches are not supposed
715 to be common, anyway.
717 Branch likely. If label is out of range, we turn:
719 beql reg1, reg2, label
720 delay slot (annulled if branch not taken)
729 delay slot (executed only if branch taken)
732 It would be possible to generate a shorter sequence by losing the
733 likely bit, generating something like:
738 delay slot (executed only if branch taken)
750 bltzall -> bgezal (with jal label instead of j label)
751 bgezall -> bltzal (ditto)
754 but it's not clear that it would actually improve performance. */
755 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
758 | ((toofar) ? 1 : 0) \
760 | ((likely) ? 4 : 0) \
761 | ((uncond) ? 8 : 0)))
762 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
763 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
764 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
765 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
766 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
768 /* For mips16 code, we use an entirely different form of relaxation.
769 mips16 supports two versions of most instructions which take
770 immediate values: a small one which takes some small value, and a
771 larger one which takes a 16 bit value. Since branches also follow
772 this pattern, relaxing these values is required.
774 We can assemble both mips16 and normal MIPS code in a single
775 object. Therefore, we need to support this type of relaxation at
776 the same time that we support the relaxation described above. We
777 use the high bit of the subtype field to distinguish these cases.
779 The information we store for this type of relaxation is the
780 argument code found in the opcode file for this relocation, whether
781 the user explicitly requested a small or extended form, and whether
782 the relocation is in a jump or jal delay slot. That tells us the
783 size of the value, and how it should be stored. We also store
784 whether the fragment is considered to be extended or not. We also
785 store whether this is known to be a branch to a different section,
786 whether we have tried to relax this frag yet, and whether we have
787 ever extended a PC relative fragment because of a shift count. */
788 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
791 | ((small) ? 0x100 : 0) \
792 | ((ext) ? 0x200 : 0) \
793 | ((dslot) ? 0x400 : 0) \
794 | ((jal_dslot) ? 0x800 : 0))
795 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
796 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
797 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
798 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
799 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
800 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
801 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
802 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
803 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
804 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
805 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
806 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
808 /* Is the given value a sign-extended 32-bit value? */
809 #define IS_SEXT_32BIT_NUM(x) \
810 (((x) &~ (offsetT) 0x7fffffff) == 0 \
811 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
813 /* Is the given value a sign-extended 16-bit value? */
814 #define IS_SEXT_16BIT_NUM(x) \
815 (((x) &~ (offsetT) 0x7fff) == 0 \
816 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
819 /* Prototypes for static functions. */
822 #define internalError() \
823 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
825 #define internalError() as_fatal (_("MIPS internal Error"));
828 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
830 static inline bfd_boolean reloc_needs_lo_p
831 PARAMS ((bfd_reloc_code_real_type));
832 static inline bfd_boolean fixup_has_matching_lo_p
834 static int insn_uses_reg
835 PARAMS ((struct mips_cl_insn *ip, unsigned int reg,
836 enum mips_regclass class));
837 static int reg_needs_delay
838 PARAMS ((unsigned int));
839 static void mips16_mark_labels
841 static void append_insn
842 PARAMS ((char *place, struct mips_cl_insn * ip, expressionS * p,
843 bfd_reloc_code_real_type *r));
844 static void mips_no_prev_insn
846 static void mips_emit_delays
847 PARAMS ((bfd_boolean));
849 static void macro_build
850 PARAMS ((char *place, int *counter, expressionS * ep, const char *name,
851 const char *fmt, ...));
853 static void macro_build ();
855 static void mips16_macro_build
856 PARAMS ((char *, int *, expressionS *, const char *, const char *, va_list));
857 static void macro_build_jalr
858 PARAMS ((int, expressionS *));
859 static void macro_build_lui
860 PARAMS ((char *place, int *counter, expressionS * ep, int regnum));
861 static void macro_build_ldst_constoffset
862 PARAMS ((char *place, int *counter, expressionS * ep, const char *op,
863 int valreg, int breg));
865 PARAMS ((int *counter, int reg, int unsignedp));
866 static void check_absolute_expr
867 PARAMS ((struct mips_cl_insn * ip, expressionS *));
868 static void load_register
869 PARAMS ((int *, int, expressionS *, int));
870 static void load_address
871 PARAMS ((int *, int, expressionS *, int *));
872 static void move_register
873 PARAMS ((int *, int, int));
875 PARAMS ((struct mips_cl_insn * ip));
876 static void mips16_macro
877 PARAMS ((struct mips_cl_insn * ip));
878 #ifdef LOSING_COMPILER
880 PARAMS ((struct mips_cl_insn * ip));
883 PARAMS ((char *str, struct mips_cl_insn * ip));
884 static void mips16_ip
885 PARAMS ((char *str, struct mips_cl_insn * ip));
886 static void mips16_immed
887 PARAMS ((char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean,
888 bfd_boolean, unsigned long *, bfd_boolean *, unsigned short *));
889 static bfd_boolean parse_relocation
890 PARAMS ((char **, bfd_reloc_code_real_type *));
891 static size_t my_getSmallExpression
892 PARAMS ((expressionS *, bfd_reloc_code_real_type *, char *));
893 static void my_getExpression
894 PARAMS ((expressionS *, char *));
896 static int support_64bit_objects
899 static void mips_set_option_string
900 PARAMS ((const char **, const char *));
901 static symbolS *get_symbol
903 static void mips_align
904 PARAMS ((int to, int fill, symbolS *label));
907 static void s_change_sec
909 static void s_change_section
913 static void s_float_cons
915 static void s_mips_globl
919 static void s_mipsset
921 static void s_abicalls
925 static void s_cpsetup
927 static void s_cplocal
929 static void s_cprestore
931 static void s_cpreturn
933 static void s_gpvalue
937 static void s_gpdword
943 static void md_obj_begin
945 static void md_obj_end
947 static long get_number
949 static void s_mips_ent
951 static void s_mips_end
953 static void s_mips_frame
955 static void s_mips_mask
957 static void s_mips_stab
959 static void s_mips_weakext
961 static void s_mips_file
963 static void s_mips_loc
965 static bfd_boolean pic_need_relax
966 PARAMS ((symbolS *, asection *));
967 static int mips16_extended_frag
968 PARAMS ((fragS *, asection *, long));
969 static int relaxed_branch_length (fragS *, asection *, int);
970 static int validate_mips_insn
971 PARAMS ((const struct mips_opcode *));
973 PARAMS ((FILE *, const char *, int *, int *));
975 static int mips_need_elf_addend_fixup
979 /* Table and functions used to map between CPU/ISA names, and
980 ISA levels, and CPU numbers. */
984 const char *name; /* CPU or ISA name. */
985 int is_isa; /* Is this an ISA? (If 0, a CPU.) */
986 int isa; /* ISA level. */
987 int cpu; /* CPU number (default CPU if ISA). */
990 static void mips_set_architecture
991 PARAMS ((const struct mips_cpu_info *));
992 static void mips_set_tune
993 PARAMS ((const struct mips_cpu_info *));
994 static bfd_boolean mips_strict_matching_cpu_name_p
995 PARAMS ((const char *, const char *));
996 static bfd_boolean mips_matching_cpu_name_p
997 PARAMS ((const char *, const char *));
998 static const struct mips_cpu_info *mips_parse_cpu
999 PARAMS ((const char *, const char *));
1000 static const struct mips_cpu_info *mips_cpu_info_from_isa
1002 static const struct mips_cpu_info *mips_cpu_info_from_arch
1007 The following pseudo-ops from the Kane and Heinrich MIPS book
1008 should be defined here, but are currently unsupported: .alias,
1009 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1011 The following pseudo-ops from the Kane and Heinrich MIPS book are
1012 specific to the type of debugging information being generated, and
1013 should be defined by the object format: .aent, .begin, .bend,
1014 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1017 The following pseudo-ops from the Kane and Heinrich MIPS book are
1018 not MIPS CPU specific, but are also not specific to the object file
1019 format. This file is probably the best place to define them, but
1020 they are not currently supported: .asm0, .endr, .lab, .repeat,
1023 static const pseudo_typeS mips_pseudo_table[] =
1025 /* MIPS specific pseudo-ops. */
1026 {"option", s_option, 0},
1027 {"set", s_mipsset, 0},
1028 {"rdata", s_change_sec, 'r'},
1029 {"sdata", s_change_sec, 's'},
1030 {"livereg", s_ignore, 0},
1031 {"abicalls", s_abicalls, 0},
1032 {"cpload", s_cpload, 0},
1033 {"cpsetup", s_cpsetup, 0},
1034 {"cplocal", s_cplocal, 0},
1035 {"cprestore", s_cprestore, 0},
1036 {"cpreturn", s_cpreturn, 0},
1037 {"gpvalue", s_gpvalue, 0},
1038 {"gpword", s_gpword, 0},
1039 {"gpdword", s_gpdword, 0},
1040 {"cpadd", s_cpadd, 0},
1041 {"insn", s_insn, 0},
1043 /* Relatively generic pseudo-ops that happen to be used on MIPS
1045 {"asciiz", stringer, 1},
1046 {"bss", s_change_sec, 'b'},
1048 {"half", s_cons, 1},
1049 {"dword", s_cons, 3},
1050 {"weakext", s_mips_weakext, 0},
1052 /* These pseudo-ops are defined in read.c, but must be overridden
1053 here for one reason or another. */
1054 {"align", s_align, 0},
1055 {"byte", s_cons, 0},
1056 {"data", s_change_sec, 'd'},
1057 {"double", s_float_cons, 'd'},
1058 {"float", s_float_cons, 'f'},
1059 {"globl", s_mips_globl, 0},
1060 {"global", s_mips_globl, 0},
1061 {"hword", s_cons, 1},
1063 {"long", s_cons, 2},
1064 {"octa", s_cons, 4},
1065 {"quad", s_cons, 3},
1066 {"section", s_change_section, 0},
1067 {"short", s_cons, 1},
1068 {"single", s_float_cons, 'f'},
1069 {"stabn", s_mips_stab, 'n'},
1070 {"text", s_change_sec, 't'},
1071 {"word", s_cons, 2},
1073 { "extern", ecoff_directive_extern, 0},
1078 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1080 /* These pseudo-ops should be defined by the object file format.
1081 However, a.out doesn't support them, so we have versions here. */
1082 {"aent", s_mips_ent, 1},
1083 {"bgnb", s_ignore, 0},
1084 {"end", s_mips_end, 0},
1085 {"endb", s_ignore, 0},
1086 {"ent", s_mips_ent, 0},
1087 {"file", s_mips_file, 0},
1088 {"fmask", s_mips_mask, 'F'},
1089 {"frame", s_mips_frame, 0},
1090 {"loc", s_mips_loc, 0},
1091 {"mask", s_mips_mask, 'R'},
1092 {"verstamp", s_ignore, 0},
1096 extern void pop_insert PARAMS ((const pseudo_typeS *));
1101 pop_insert (mips_pseudo_table);
1102 if (! ECOFF_DEBUGGING)
1103 pop_insert (mips_nonecoff_pseudo_table);
1106 /* Symbols labelling the current insn. */
1108 struct insn_label_list
1110 struct insn_label_list *next;
1114 static struct insn_label_list *insn_labels;
1115 static struct insn_label_list *free_insn_labels;
1117 static void mips_clear_insn_labels PARAMS ((void));
1120 mips_clear_insn_labels ()
1122 register struct insn_label_list **pl;
1124 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1130 static char *expr_end;
1132 /* Expressions which appear in instructions. These are set by
1135 static expressionS imm_expr;
1136 static expressionS offset_expr;
1138 /* Relocs associated with imm_expr and offset_expr. */
1140 static bfd_reloc_code_real_type imm_reloc[3]
1141 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1142 static bfd_reloc_code_real_type offset_reloc[3]
1143 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1145 /* These are set by mips16_ip if an explicit extension is used. */
1147 static bfd_boolean mips16_small, mips16_ext;
1150 /* The pdr segment for per procedure frame/regmask info. Not used for
1153 static segT pdr_seg;
1156 /* The default target format to use. */
1159 mips_target_format ()
1161 switch (OUTPUT_FLAVOR)
1163 case bfd_target_aout_flavour:
1164 return target_big_endian ? "a.out-mips-big" : "a.out-mips-little";
1165 case bfd_target_ecoff_flavour:
1166 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1167 case bfd_target_coff_flavour:
1169 case bfd_target_elf_flavour:
1171 /* This is traditional mips. */
1172 return (target_big_endian
1173 ? (HAVE_64BIT_OBJECTS
1174 ? "elf64-tradbigmips"
1176 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1177 : (HAVE_64BIT_OBJECTS
1178 ? "elf64-tradlittlemips"
1180 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1182 return (target_big_endian
1183 ? (HAVE_64BIT_OBJECTS
1186 ? "elf32-nbigmips" : "elf32-bigmips"))
1187 : (HAVE_64BIT_OBJECTS
1188 ? "elf64-littlemips"
1190 ? "elf32-nlittlemips" : "elf32-littlemips")));
1198 /* This function is called once, at assembler startup time. It should
1199 set up all the tables, etc. that the MD part of the assembler will need. */
1204 register const char *retval = NULL;
1208 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
1209 as_warn (_("Could not set architecture and machine"));
1211 op_hash = hash_new ();
1213 for (i = 0; i < NUMOPCODES;)
1215 const char *name = mips_opcodes[i].name;
1217 retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]);
1220 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1221 mips_opcodes[i].name, retval);
1222 /* Probably a memory allocation problem? Give up now. */
1223 as_fatal (_("Broken assembler. No assembly attempted."));
1227 if (mips_opcodes[i].pinfo != INSN_MACRO)
1229 if (!validate_mips_insn (&mips_opcodes[i]))
1234 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1237 mips16_op_hash = hash_new ();
1240 while (i < bfd_mips16_num_opcodes)
1242 const char *name = mips16_opcodes[i].name;
1244 retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]);
1246 as_fatal (_("internal: can't hash `%s': %s"),
1247 mips16_opcodes[i].name, retval);
1250 if (mips16_opcodes[i].pinfo != INSN_MACRO
1251 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1252 != mips16_opcodes[i].match))
1254 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1255 mips16_opcodes[i].name, mips16_opcodes[i].args);
1260 while (i < bfd_mips16_num_opcodes
1261 && strcmp (mips16_opcodes[i].name, name) == 0);
1265 as_fatal (_("Broken assembler. No assembly attempted."));
1267 /* We add all the general register names to the symbol table. This
1268 helps us detect invalid uses of them. */
1269 for (i = 0; i < 32; i++)
1273 sprintf (buf, "$%d", i);
1274 symbol_table_insert (symbol_new (buf, reg_section, i,
1275 &zero_address_frag));
1277 symbol_table_insert (symbol_new ("$ra", reg_section, RA,
1278 &zero_address_frag));
1279 symbol_table_insert (symbol_new ("$fp", reg_section, FP,
1280 &zero_address_frag));
1281 symbol_table_insert (symbol_new ("$sp", reg_section, SP,
1282 &zero_address_frag));
1283 symbol_table_insert (symbol_new ("$gp", reg_section, GP,
1284 &zero_address_frag));
1285 symbol_table_insert (symbol_new ("$at", reg_section, AT,
1286 &zero_address_frag));
1287 symbol_table_insert (symbol_new ("$kt0", reg_section, KT0,
1288 &zero_address_frag));
1289 symbol_table_insert (symbol_new ("$kt1", reg_section, KT1,
1290 &zero_address_frag));
1291 symbol_table_insert (symbol_new ("$zero", reg_section, ZERO,
1292 &zero_address_frag));
1293 symbol_table_insert (symbol_new ("$pc", reg_section, -1,
1294 &zero_address_frag));
1296 /* If we don't add these register names to the symbol table, they
1297 may end up being added as regular symbols by operand(), and then
1298 make it to the object file as undefined in case they're not
1299 regarded as local symbols. They're local in o32, since `$' is a
1300 local symbol prefix, but not in n32 or n64. */
1301 for (i = 0; i < 8; i++)
1305 sprintf (buf, "$fcc%i", i);
1306 symbol_table_insert (symbol_new (buf, reg_section, -1,
1307 &zero_address_frag));
1310 mips_no_prev_insn (FALSE);
1313 mips_cprmask[0] = 0;
1314 mips_cprmask[1] = 0;
1315 mips_cprmask[2] = 0;
1316 mips_cprmask[3] = 0;
1318 /* set the default alignment for the text section (2**2) */
1319 record_alignment (text_section, 2);
1321 if (USE_GLOBAL_POINTER_OPT)
1322 bfd_set_gp_size (stdoutput, g_switch_value);
1324 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1326 /* On a native system, sections must be aligned to 16 byte
1327 boundaries. When configured for an embedded ELF target, we
1329 if (strcmp (TARGET_OS, "elf") != 0)
1331 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
1332 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
1333 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
1336 /* Create a .reginfo section for register masks and a .mdebug
1337 section for debugging information. */
1345 subseg = now_subseg;
1347 /* The ABI says this section should be loaded so that the
1348 running program can access it. However, we don't load it
1349 if we are configured for an embedded target */
1350 flags = SEC_READONLY | SEC_DATA;
1351 if (strcmp (TARGET_OS, "elf") != 0)
1352 flags |= SEC_ALLOC | SEC_LOAD;
1354 if (mips_abi != N64_ABI)
1356 sec = subseg_new (".reginfo", (subsegT) 0);
1358 bfd_set_section_flags (stdoutput, sec, flags);
1359 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
1362 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
1367 /* The 64-bit ABI uses a .MIPS.options section rather than
1368 .reginfo section. */
1369 sec = subseg_new (".MIPS.options", (subsegT) 0);
1370 bfd_set_section_flags (stdoutput, sec, flags);
1371 bfd_set_section_alignment (stdoutput, sec, 3);
1374 /* Set up the option header. */
1376 Elf_Internal_Options opthdr;
1379 opthdr.kind = ODK_REGINFO;
1380 opthdr.size = (sizeof (Elf_External_Options)
1381 + sizeof (Elf64_External_RegInfo));
1384 f = frag_more (sizeof (Elf_External_Options));
1385 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
1386 (Elf_External_Options *) f);
1388 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
1393 if (ECOFF_DEBUGGING)
1395 sec = subseg_new (".mdebug", (subsegT) 0);
1396 (void) bfd_set_section_flags (stdoutput, sec,
1397 SEC_HAS_CONTENTS | SEC_READONLY);
1398 (void) bfd_set_section_alignment (stdoutput, sec, 2);
1401 else if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1403 pdr_seg = subseg_new (".pdr", (subsegT) 0);
1404 (void) bfd_set_section_flags (stdoutput, pdr_seg,
1405 SEC_READONLY | SEC_RELOC
1407 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
1411 subseg_set (seg, subseg);
1415 if (! ECOFF_DEBUGGING)
1422 if (! ECOFF_DEBUGGING)
1430 struct mips_cl_insn insn;
1431 bfd_reloc_code_real_type unused_reloc[3]
1432 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1434 imm_expr.X_op = O_absent;
1435 offset_expr.X_op = O_absent;
1436 imm_reloc[0] = BFD_RELOC_UNUSED;
1437 imm_reloc[1] = BFD_RELOC_UNUSED;
1438 imm_reloc[2] = BFD_RELOC_UNUSED;
1439 offset_reloc[0] = BFD_RELOC_UNUSED;
1440 offset_reloc[1] = BFD_RELOC_UNUSED;
1441 offset_reloc[2] = BFD_RELOC_UNUSED;
1443 if (mips_opts.mips16)
1444 mips16_ip (str, &insn);
1447 mips_ip (str, &insn);
1448 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1449 str, insn.insn_opcode));
1454 as_bad ("%s `%s'", insn_error, str);
1458 if (insn.insn_mo->pinfo == INSN_MACRO)
1460 if (mips_opts.mips16)
1461 mips16_macro (&insn);
1467 if (imm_expr.X_op != O_absent)
1468 append_insn (NULL, &insn, &imm_expr, imm_reloc);
1469 else if (offset_expr.X_op != O_absent)
1470 append_insn (NULL, &insn, &offset_expr, offset_reloc);
1472 append_insn (NULL, &insn, NULL, unused_reloc);
1476 /* Return true if the given relocation might need a matching %lo().
1477 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1478 applied to local symbols. */
1480 static inline bfd_boolean
1481 reloc_needs_lo_p (reloc)
1482 bfd_reloc_code_real_type reloc;
1484 return (reloc == BFD_RELOC_HI16_S
1485 || reloc == BFD_RELOC_MIPS_GOT16);
1488 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1491 static inline bfd_boolean
1492 fixup_has_matching_lo_p (fixp)
1495 return (fixp->fx_next != NULL
1496 && fixp->fx_next->fx_r_type == BFD_RELOC_LO16
1497 && fixp->fx_addsy == fixp->fx_next->fx_addsy
1498 && fixp->fx_offset == fixp->fx_next->fx_offset);
1501 /* See whether instruction IP reads register REG. CLASS is the type
1505 insn_uses_reg (ip, reg, class)
1506 struct mips_cl_insn *ip;
1508 enum mips_regclass class;
1510 if (class == MIPS16_REG)
1512 assert (mips_opts.mips16);
1513 reg = mips16_to_32_reg_map[reg];
1514 class = MIPS_GR_REG;
1517 /* Don't report on general register ZERO, since it never changes. */
1518 if (class == MIPS_GR_REG && reg == ZERO)
1521 if (class == MIPS_FP_REG)
1523 assert (! mips_opts.mips16);
1524 /* If we are called with either $f0 or $f1, we must check $f0.
1525 This is not optimal, because it will introduce an unnecessary
1526 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1527 need to distinguish reading both $f0 and $f1 or just one of
1528 them. Note that we don't have to check the other way,
1529 because there is no instruction that sets both $f0 and $f1
1530 and requires a delay. */
1531 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
1532 && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1)
1533 == (reg &~ (unsigned) 1)))
1535 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
1536 && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1)
1537 == (reg &~ (unsigned) 1)))
1540 else if (! mips_opts.mips16)
1542 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
1543 && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg)
1545 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
1546 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg)
1551 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
1552 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX)
1553 & MIPS16OP_MASK_RX)]
1556 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
1557 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY)
1558 & MIPS16OP_MASK_RY)]
1561 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
1562 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
1563 & MIPS16OP_MASK_MOVE32Z)]
1566 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
1568 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
1570 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
1572 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
1573 && ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
1574 & MIPS16OP_MASK_REGR32) == reg)
1581 /* This function returns true if modifying a register requires a
1585 reg_needs_delay (reg)
1588 unsigned long prev_pinfo;
1590 prev_pinfo = prev_insn.insn_mo->pinfo;
1591 if (! mips_opts.noreorder
1592 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1593 && ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1594 || (! gpr_interlocks
1595 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
1597 /* A load from a coprocessor or from memory. All load
1598 delays delay the use of general register rt for one
1599 instruction on the r3000. The r6000 and r4000 use
1601 /* Itbl support may require additional care here. */
1602 know (prev_pinfo & INSN_WRITE_GPR_T);
1603 if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT))
1610 /* Mark instruction labels in mips16 mode. This permits the linker to
1611 handle them specially, such as generating jalx instructions when
1612 needed. We also make them odd for the duration of the assembly, in
1613 order to generate the right sort of code. We will make them even
1614 in the adjust_symtab routine, while leaving them marked. This is
1615 convenient for the debugger and the disassembler. The linker knows
1616 to make them odd again. */
1619 mips16_mark_labels ()
1621 if (mips_opts.mips16)
1623 struct insn_label_list *l;
1626 for (l = insn_labels; l != NULL; l = l->next)
1629 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1630 S_SET_OTHER (l->label, STO_MIPS16);
1632 val = S_GET_VALUE (l->label);
1634 S_SET_VALUE (l->label, val + 1);
1639 /* Output an instruction. PLACE is where to put the instruction; if
1640 it is NULL, this uses frag_more to get room. IP is the instruction
1641 information. ADDRESS_EXPR is an operand of the instruction to be
1642 used with RELOC_TYPE. */
1645 append_insn (place, ip, address_expr, reloc_type)
1647 struct mips_cl_insn *ip;
1648 expressionS *address_expr;
1649 bfd_reloc_code_real_type *reloc_type;
1651 register unsigned long prev_pinfo, pinfo;
1655 bfd_boolean force_new_frag = FALSE;
1657 /* Mark instruction labels in mips16 mode. */
1658 mips16_mark_labels ();
1660 prev_pinfo = prev_insn.insn_mo->pinfo;
1661 pinfo = ip->insn_mo->pinfo;
1663 if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL))
1667 /* If the previous insn required any delay slots, see if we need
1668 to insert a NOP or two. There are eight kinds of possible
1669 hazards, of which an instruction can have at most one type.
1670 (1) a load from memory delay
1671 (2) a load from a coprocessor delay
1672 (3) an unconditional branch delay
1673 (4) a conditional branch delay
1674 (5) a move to coprocessor register delay
1675 (6) a load coprocessor register from memory delay
1676 (7) a coprocessor condition code delay
1677 (8) a HI/LO special register delay
1679 There are a lot of optimizations we could do that we don't.
1680 In particular, we do not, in general, reorder instructions.
1681 If you use gcc with optimization, it will reorder
1682 instructions and generally do much more optimization then we
1683 do here; repeating all that work in the assembler would only
1684 benefit hand written assembly code, and does not seem worth
1687 /* This is how a NOP is emitted. */
1688 #define emit_nop() \
1690 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1691 : md_number_to_chars (frag_more (4), 0, 4))
1693 /* The previous insn might require a delay slot, depending upon
1694 the contents of the current insn. */
1695 if (! mips_opts.mips16
1696 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1697 && (((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1698 && ! cop_interlocks)
1699 || (! gpr_interlocks
1700 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
1702 /* A load from a coprocessor or from memory. All load
1703 delays delay the use of general register rt for one
1704 instruction on the r3000. The r6000 and r4000 use
1706 /* Itbl support may require additional care here. */
1707 know (prev_pinfo & INSN_WRITE_GPR_T);
1708 if (mips_optimize == 0
1709 || insn_uses_reg (ip,
1710 ((prev_insn.insn_opcode >> OP_SH_RT)
1715 else if (! mips_opts.mips16
1716 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1717 && (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
1718 && ! cop_interlocks)
1719 || (mips_opts.isa == ISA_MIPS1
1720 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))))
1722 /* A generic coprocessor delay. The previous instruction
1723 modified a coprocessor general or control register. If
1724 it modified a control register, we need to avoid any
1725 coprocessor instruction (this is probably not always
1726 required, but it sometimes is). If it modified a general
1727 register, we avoid using that register.
1729 On the r6000 and r4000 loading a coprocessor register
1730 from memory is interlocked, and does not require a delay.
1732 This case is not handled very well. There is no special
1733 knowledge of CP0 handling, and the coprocessors other
1734 than the floating point unit are not distinguished at
1736 /* Itbl support may require additional care here. FIXME!
1737 Need to modify this to include knowledge about
1738 user specified delays! */
1739 if (prev_pinfo & INSN_WRITE_FPR_T)
1741 if (mips_optimize == 0
1742 || insn_uses_reg (ip,
1743 ((prev_insn.insn_opcode >> OP_SH_FT)
1748 else if (prev_pinfo & INSN_WRITE_FPR_S)
1750 if (mips_optimize == 0
1751 || insn_uses_reg (ip,
1752 ((prev_insn.insn_opcode >> OP_SH_FS)
1759 /* We don't know exactly what the previous instruction
1760 does. If the current instruction uses a coprocessor
1761 register, we must insert a NOP. If previous
1762 instruction may set the condition codes, and the
1763 current instruction uses them, we must insert two
1765 /* Itbl support may require additional care here. */
1766 if (mips_optimize == 0
1767 || ((prev_pinfo & INSN_WRITE_COND_CODE)
1768 && (pinfo & INSN_READ_COND_CODE)))
1770 else if (pinfo & INSN_COP)
1774 else if (! mips_opts.mips16
1775 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1776 && (prev_pinfo & INSN_WRITE_COND_CODE)
1777 && ! cop_interlocks)
1779 /* The previous instruction sets the coprocessor condition
1780 codes, but does not require a general coprocessor delay
1781 (this means it is a floating point comparison
1782 instruction). If this instruction uses the condition
1783 codes, we need to insert a single NOP. */
1784 /* Itbl support may require additional care here. */
1785 if (mips_optimize == 0
1786 || (pinfo & INSN_READ_COND_CODE))
1790 /* If we're fixing up mfhi/mflo for the r7000 and the
1791 previous insn was an mfhi/mflo and the current insn
1792 reads the register that the mfhi/mflo wrote to, then
1795 else if (mips_7000_hilo_fix
1796 && MF_HILO_INSN (prev_pinfo)
1797 && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD)
1804 /* If we're fixing up mfhi/mflo for the r7000 and the
1805 2nd previous insn was an mfhi/mflo and the current insn
1806 reads the register that the mfhi/mflo wrote to, then
1809 else if (mips_7000_hilo_fix
1810 && MF_HILO_INSN (prev_prev_insn.insn_opcode)
1811 && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD)
1819 else if (prev_pinfo & INSN_READ_LO)
1821 /* The previous instruction reads the LO register; if the
1822 current instruction writes to the LO register, we must
1823 insert two NOPS. Some newer processors have interlocks.
1824 Also the tx39's multiply instructions can be exectuted
1825 immediatly after a read from HI/LO (without the delay),
1826 though the tx39's divide insns still do require the
1828 if (! (hilo_interlocks
1829 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
1830 && (mips_optimize == 0
1831 || (pinfo & INSN_WRITE_LO)))
1833 /* Most mips16 branch insns don't have a delay slot.
1834 If a read from LO is immediately followed by a branch
1835 to a write to LO we have a read followed by a write
1836 less than 2 insns away. We assume the target of
1837 a branch might be a write to LO, and insert a nop
1838 between a read and an immediately following branch. */
1839 else if (mips_opts.mips16
1840 && (mips_optimize == 0
1841 || (pinfo & MIPS16_INSN_BRANCH)))
1844 else if (prev_insn.insn_mo->pinfo & INSN_READ_HI)
1846 /* The previous instruction reads the HI register; if the
1847 current instruction writes to the HI register, we must
1848 insert a NOP. Some newer processors have interlocks.
1849 Also the note tx39's multiply above. */
1850 if (! (hilo_interlocks
1851 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
1852 && (mips_optimize == 0
1853 || (pinfo & INSN_WRITE_HI)))
1855 /* Most mips16 branch insns don't have a delay slot.
1856 If a read from HI is immediately followed by a branch
1857 to a write to HI we have a read followed by a write
1858 less than 2 insns away. We assume the target of
1859 a branch might be a write to HI, and insert a nop
1860 between a read and an immediately following branch. */
1861 else if (mips_opts.mips16
1862 && (mips_optimize == 0
1863 || (pinfo & MIPS16_INSN_BRANCH)))
1867 /* If the previous instruction was in a noreorder section, then
1868 we don't want to insert the nop after all. */
1869 /* Itbl support may require additional care here. */
1870 if (prev_insn_unreordered)
1873 /* There are two cases which require two intervening
1874 instructions: 1) setting the condition codes using a move to
1875 coprocessor instruction which requires a general coprocessor
1876 delay and then reading the condition codes 2) reading the HI
1877 or LO register and then writing to it (except on processors
1878 which have interlocks). If we are not already emitting a NOP
1879 instruction, we must check for these cases compared to the
1880 instruction previous to the previous instruction. */
1881 if ((! mips_opts.mips16
1882 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1883 && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
1884 && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
1885 && (pinfo & INSN_READ_COND_CODE)
1886 && ! cop_interlocks)
1887 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
1888 && (pinfo & INSN_WRITE_LO)
1889 && ! (hilo_interlocks
1890 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))))
1891 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
1892 && (pinfo & INSN_WRITE_HI)
1893 && ! (hilo_interlocks
1894 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))))
1899 if (prev_prev_insn_unreordered)
1902 if (prev_prev_nop && nops == 0)
1905 if (mips_fix_4122_bugs && prev_insn.insn_mo->name)
1907 /* We're out of bits in pinfo, so we must resort to string
1908 ops here. Shortcuts are selected based on opcodes being
1909 limited to the VR4122 instruction set. */
1911 const char *pn = prev_insn.insn_mo->name;
1912 const char *tn = ip->insn_mo->name;
1913 if (strncmp(pn, "macc", 4) == 0
1914 || strncmp(pn, "dmacc", 5) == 0)
1916 /* Errata 21 - [D]DIV[U] after [D]MACC */
1917 if (strstr (tn, "div"))
1922 /* Errata 23 - Continuous DMULT[U]/DMACC instructions */
1923 if (pn[0] == 'd' /* dmacc */
1924 && (strncmp(tn, "dmult", 5) == 0
1925 || strncmp(tn, "dmacc", 5) == 0))
1930 /* Errata 24 - MT{LO,HI} after [D]MACC */
1931 if (strcmp (tn, "mtlo") == 0
1932 || strcmp (tn, "mthi") == 0)
1938 else if (strncmp(pn, "dmult", 5) == 0
1939 && (strncmp(tn, "dmult", 5) == 0
1940 || strncmp(tn, "dmacc", 5) == 0))
1942 /* Here is the rest of errata 23. */
1945 if (nops < min_nops)
1949 /* If we are being given a nop instruction, don't bother with
1950 one of the nops we would otherwise output. This will only
1951 happen when a nop instruction is used with mips_optimize set
1954 && ! mips_opts.noreorder
1955 && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0))
1958 /* Now emit the right number of NOP instructions. */
1959 if (nops > 0 && ! mips_opts.noreorder)
1962 unsigned long old_frag_offset;
1964 struct insn_label_list *l;
1966 old_frag = frag_now;
1967 old_frag_offset = frag_now_fix ();
1969 for (i = 0; i < nops; i++)
1974 listing_prev_line ();
1975 /* We may be at the start of a variant frag. In case we
1976 are, make sure there is enough space for the frag
1977 after the frags created by listing_prev_line. The
1978 argument to frag_grow here must be at least as large
1979 as the argument to all other calls to frag_grow in
1980 this file. We don't have to worry about being in the
1981 middle of a variant frag, because the variants insert
1982 all needed nop instructions themselves. */
1986 for (l = insn_labels; l != NULL; l = l->next)
1990 assert (S_GET_SEGMENT (l->label) == now_seg);
1991 symbol_set_frag (l->label, frag_now);
1992 val = (valueT) frag_now_fix ();
1993 /* mips16 text labels are stored as odd. */
1994 if (mips_opts.mips16)
1996 S_SET_VALUE (l->label, val);
1999 #ifndef NO_ECOFF_DEBUGGING
2000 if (ECOFF_DEBUGGING)
2001 ecoff_fix_loc (old_frag, old_frag_offset);
2004 else if (prev_nop_frag != NULL)
2006 /* We have a frag holding nops we may be able to remove. If
2007 we don't need any nops, we can decrease the size of
2008 prev_nop_frag by the size of one instruction. If we do
2009 need some nops, we count them in prev_nops_required. */
2010 if (prev_nop_frag_since == 0)
2014 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
2015 --prev_nop_frag_holds;
2018 prev_nop_frag_required += nops;
2022 if (prev_prev_nop == 0)
2024 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
2025 --prev_nop_frag_holds;
2028 ++prev_nop_frag_required;
2031 if (prev_nop_frag_holds <= prev_nop_frag_required)
2032 prev_nop_frag = NULL;
2034 ++prev_nop_frag_since;
2036 /* Sanity check: by the time we reach the second instruction
2037 after prev_nop_frag, we should have used up all the nops
2038 one way or another. */
2039 assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL);
2045 && *reloc_type == BFD_RELOC_16_PCREL_S2
2046 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
2047 || pinfo & INSN_COND_BRANCH_LIKELY)
2048 && mips_relax_branch
2049 /* Don't try branch relaxation within .set nomacro, or within
2050 .set noat if we use $at for PIC computations. If it turns
2051 out that the branch was out-of-range, we'll get an error. */
2052 && !mips_opts.warn_about_macros
2053 && !(mips_opts.noat && mips_pic != NO_PIC)
2054 && !mips_opts.mips16)
2056 f = frag_var (rs_machine_dependent,
2057 relaxed_branch_length
2059 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
2060 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4,
2062 (pinfo & INSN_UNCOND_BRANCH_DELAY,
2063 pinfo & INSN_COND_BRANCH_LIKELY,
2064 pinfo & INSN_WRITE_GPR_31,
2066 address_expr->X_add_symbol,
2067 address_expr->X_add_number,
2069 *reloc_type = BFD_RELOC_UNUSED;
2071 else if (*reloc_type > BFD_RELOC_UNUSED)
2073 /* We need to set up a variant frag. */
2074 assert (mips_opts.mips16 && address_expr != NULL);
2075 f = frag_var (rs_machine_dependent, 4, 0,
2076 RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED,
2077 mips16_small, mips16_ext,
2079 & INSN_UNCOND_BRANCH_DELAY),
2080 (*prev_insn_reloc_type
2081 == BFD_RELOC_MIPS16_JMP)),
2082 make_expr_symbol (address_expr), 0, NULL);
2084 else if (place != NULL)
2086 else if (mips_opts.mips16
2088 && *reloc_type != BFD_RELOC_MIPS16_JMP)
2090 /* Make sure there is enough room to swap this instruction with
2091 a following jump instruction. */
2097 if (mips_opts.mips16
2098 && mips_opts.noreorder
2099 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2100 as_warn (_("extended instruction in delay slot"));
2105 fixp[0] = fixp[1] = fixp[2] = NULL;
2106 if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED)
2108 if (address_expr->X_op == O_constant)
2112 switch (*reloc_type)
2115 ip->insn_opcode |= address_expr->X_add_number;
2118 case BFD_RELOC_MIPS_HIGHEST:
2119 tmp = (address_expr->X_add_number
2120 + ((valueT) 0x8000 << 32) + 0x80008000) >> 16;
2122 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2125 case BFD_RELOC_MIPS_HIGHER:
2126 tmp = (address_expr->X_add_number + 0x80008000) >> 16;
2127 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2130 case BFD_RELOC_HI16_S:
2131 ip->insn_opcode |= ((address_expr->X_add_number + 0x8000)
2135 case BFD_RELOC_HI16:
2136 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
2139 case BFD_RELOC_LO16:
2140 case BFD_RELOC_MIPS_GOT_DISP:
2141 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
2144 case BFD_RELOC_MIPS_JMP:
2145 if ((address_expr->X_add_number & 3) != 0)
2146 as_bad (_("jump to misaligned address (0x%lx)"),
2147 (unsigned long) address_expr->X_add_number);
2148 if (address_expr->X_add_number & ~0xfffffff)
2149 as_bad (_("jump address range overflow (0x%lx)"),
2150 (unsigned long) address_expr->X_add_number);
2151 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
2154 case BFD_RELOC_MIPS16_JMP:
2155 if ((address_expr->X_add_number & 3) != 0)
2156 as_bad (_("jump to misaligned address (0x%lx)"),
2157 (unsigned long) address_expr->X_add_number);
2158 if (address_expr->X_add_number & ~0xfffffff)
2159 as_bad (_("jump address range overflow (0x%lx)"),
2160 (unsigned long) address_expr->X_add_number);
2162 (((address_expr->X_add_number & 0x7c0000) << 3)
2163 | ((address_expr->X_add_number & 0xf800000) >> 7)
2164 | ((address_expr->X_add_number & 0x3fffc) >> 2));
2167 case BFD_RELOC_16_PCREL_S2:
2177 /* Don't generate a reloc if we are writing into a variant frag. */
2180 reloc_howto_type *howto;
2183 /* In a compound relocation, it is the final (outermost)
2184 operator that determines the relocated field. */
2185 for (i = 1; i < 3; i++)
2186 if (reloc_type[i] == BFD_RELOC_UNUSED)
2189 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
2190 fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal,
2191 bfd_get_reloc_size(howto),
2193 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
2196 /* These relocations can have an addend that won't fit in
2197 4 octets for 64bit assembly. */
2199 && ! howto->partial_inplace
2200 && (reloc_type[0] == BFD_RELOC_16
2201 || reloc_type[0] == BFD_RELOC_32
2202 || reloc_type[0] == BFD_RELOC_MIPS_JMP
2203 || reloc_type[0] == BFD_RELOC_HI16_S
2204 || reloc_type[0] == BFD_RELOC_LO16
2205 || reloc_type[0] == BFD_RELOC_GPREL16
2206 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
2207 || reloc_type[0] == BFD_RELOC_GPREL32
2208 || reloc_type[0] == BFD_RELOC_64
2209 || reloc_type[0] == BFD_RELOC_CTOR
2210 || reloc_type[0] == BFD_RELOC_MIPS_SUB
2211 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
2212 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
2213 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
2214 || reloc_type[0] == BFD_RELOC_MIPS_REL16
2215 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT))
2216 fixp[0]->fx_no_overflow = 1;
2218 if (reloc_needs_lo_p (*reloc_type))
2220 struct mips_hi_fixup *hi_fixup;
2222 /* Reuse the last entry if it already has a matching %lo. */
2223 hi_fixup = mips_hi_fixup_list;
2225 || !fixup_has_matching_lo_p (hi_fixup->fixp))
2227 hi_fixup = ((struct mips_hi_fixup *)
2228 xmalloc (sizeof (struct mips_hi_fixup)));
2229 hi_fixup->next = mips_hi_fixup_list;
2230 mips_hi_fixup_list = hi_fixup;
2232 hi_fixup->fixp = fixp[0];
2233 hi_fixup->seg = now_seg;
2236 /* Add fixups for the second and third relocations, if given.
2237 Note that the ABI allows the second relocation to be
2238 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2239 moment we only use RSS_UNDEF, but we could add support
2240 for the others if it ever becomes necessary. */
2241 for (i = 1; i < 3; i++)
2242 if (reloc_type[i] != BFD_RELOC_UNUSED)
2244 address_expr->X_op = O_absent;
2245 address_expr->X_add_symbol = 0;
2246 address_expr->X_add_number = 0;
2248 fixp[i] = fix_new_exp (frag_now, fixp[0]->fx_where,
2249 fixp[0]->fx_size, address_expr,
2250 FALSE, reloc_type[i]);
2256 if (! mips_opts.mips16)
2258 md_number_to_chars (f, ip->insn_opcode, 4);
2260 dwarf2_emit_insn (4);
2263 else if (*reloc_type == BFD_RELOC_MIPS16_JMP)
2265 md_number_to_chars (f, ip->insn_opcode >> 16, 2);
2266 md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2);
2268 dwarf2_emit_insn (4);
2275 md_number_to_chars (f, 0xf000 | ip->extend, 2);
2278 md_number_to_chars (f, ip->insn_opcode, 2);
2280 dwarf2_emit_insn (ip->use_extend ? 4 : 2);
2284 /* Update the register mask information. */
2285 if (! mips_opts.mips16)
2287 if (pinfo & INSN_WRITE_GPR_D)
2288 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD);
2289 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
2290 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT);
2291 if (pinfo & INSN_READ_GPR_S)
2292 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS);
2293 if (pinfo & INSN_WRITE_GPR_31)
2294 mips_gprmask |= 1 << RA;
2295 if (pinfo & INSN_WRITE_FPR_D)
2296 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD);
2297 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
2298 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS);
2299 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
2300 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT);
2301 if ((pinfo & INSN_READ_FPR_R) != 0)
2302 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR);
2303 if (pinfo & INSN_COP)
2305 /* We don't keep enough information to sort these cases out.
2306 The itbl support does keep this information however, although
2307 we currently don't support itbl fprmats as part of the cop
2308 instruction. May want to add this support in the future. */
2310 /* Never set the bit for $0, which is always zero. */
2311 mips_gprmask &= ~1 << 0;
2315 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
2316 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX)
2317 & MIPS16OP_MASK_RX);
2318 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
2319 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY)
2320 & MIPS16OP_MASK_RY);
2321 if (pinfo & MIPS16_INSN_WRITE_Z)
2322 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ)
2323 & MIPS16OP_MASK_RZ);
2324 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
2325 mips_gprmask |= 1 << TREG;
2326 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
2327 mips_gprmask |= 1 << SP;
2328 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
2329 mips_gprmask |= 1 << RA;
2330 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2331 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2332 if (pinfo & MIPS16_INSN_READ_Z)
2333 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
2334 & MIPS16OP_MASK_MOVE32Z);
2335 if (pinfo & MIPS16_INSN_READ_GPR_X)
2336 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
2337 & MIPS16OP_MASK_REGR32);
2340 if (place == NULL && ! mips_opts.noreorder)
2342 /* Filling the branch delay slot is more complex. We try to
2343 switch the branch with the previous instruction, which we can
2344 do if the previous instruction does not set up a condition
2345 that the branch tests and if the branch is not itself the
2346 target of any branch. */
2347 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
2348 || (pinfo & INSN_COND_BRANCH_DELAY))
2350 if (mips_optimize < 2
2351 /* If we have seen .set volatile or .set nomove, don't
2353 || mips_opts.nomove != 0
2354 /* If we had to emit any NOP instructions, then we
2355 already know we can not swap. */
2357 /* If we don't even know the previous insn, we can not
2359 || ! prev_insn_valid
2360 /* If the previous insn is already in a branch delay
2361 slot, then we can not swap. */
2362 || prev_insn_is_delay_slot
2363 /* If the previous previous insn was in a .set
2364 noreorder, we can't swap. Actually, the MIPS
2365 assembler will swap in this situation. However, gcc
2366 configured -with-gnu-as will generate code like
2372 in which we can not swap the bne and INSN. If gcc is
2373 not configured -with-gnu-as, it does not output the
2374 .set pseudo-ops. We don't have to check
2375 prev_insn_unreordered, because prev_insn_valid will
2376 be 0 in that case. We don't want to use
2377 prev_prev_insn_valid, because we do want to be able
2378 to swap at the start of a function. */
2379 || prev_prev_insn_unreordered
2380 /* If the branch is itself the target of a branch, we
2381 can not swap. We cheat on this; all we check for is
2382 whether there is a label on this instruction. If
2383 there are any branches to anything other than a
2384 label, users must use .set noreorder. */
2385 || insn_labels != NULL
2386 /* If the previous instruction is in a variant frag, we
2387 can not do the swap. This does not apply to the
2388 mips16, which uses variant frags for different
2390 || (! mips_opts.mips16
2391 && prev_insn_frag->fr_type == rs_machine_dependent)
2392 /* If the branch reads the condition codes, we don't
2393 even try to swap, because in the sequence
2398 we can not swap, and I don't feel like handling that
2400 || (! mips_opts.mips16
2401 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2402 && (pinfo & INSN_READ_COND_CODE))
2403 /* We can not swap with an instruction that requires a
2404 delay slot, becase the target of the branch might
2405 interfere with that instruction. */
2406 || (! mips_opts.mips16
2407 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2409 /* Itbl support may require additional care here. */
2410 & (INSN_LOAD_COPROC_DELAY
2411 | INSN_COPROC_MOVE_DELAY
2412 | INSN_WRITE_COND_CODE)))
2413 || (! (hilo_interlocks
2414 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
2418 || (! mips_opts.mips16
2420 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))
2421 || (! mips_opts.mips16
2422 && mips_opts.isa == ISA_MIPS1
2423 /* Itbl support may require additional care here. */
2424 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))
2425 /* We can not swap with a branch instruction. */
2427 & (INSN_UNCOND_BRANCH_DELAY
2428 | INSN_COND_BRANCH_DELAY
2429 | INSN_COND_BRANCH_LIKELY))
2430 /* We do not swap with a trap instruction, since it
2431 complicates trap handlers to have the trap
2432 instruction be in a delay slot. */
2433 || (prev_pinfo & INSN_TRAP)
2434 /* If the branch reads a register that the previous
2435 instruction sets, we can not swap. */
2436 || (! mips_opts.mips16
2437 && (prev_pinfo & INSN_WRITE_GPR_T)
2438 && insn_uses_reg (ip,
2439 ((prev_insn.insn_opcode >> OP_SH_RT)
2442 || (! mips_opts.mips16
2443 && (prev_pinfo & INSN_WRITE_GPR_D)
2444 && insn_uses_reg (ip,
2445 ((prev_insn.insn_opcode >> OP_SH_RD)
2448 || (mips_opts.mips16
2449 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
2450 && insn_uses_reg (ip,
2451 ((prev_insn.insn_opcode
2453 & MIPS16OP_MASK_RX),
2455 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
2456 && insn_uses_reg (ip,
2457 ((prev_insn.insn_opcode
2459 & MIPS16OP_MASK_RY),
2461 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
2462 && insn_uses_reg (ip,
2463 ((prev_insn.insn_opcode
2465 & MIPS16OP_MASK_RZ),
2467 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
2468 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
2469 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
2470 && insn_uses_reg (ip, RA, MIPS_GR_REG))
2471 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2472 && insn_uses_reg (ip,
2473 MIPS16OP_EXTRACT_REG32R (prev_insn.
2476 /* If the branch writes a register that the previous
2477 instruction sets, we can not swap (we know that
2478 branches write only to RD or to $31). */
2479 || (! mips_opts.mips16
2480 && (prev_pinfo & INSN_WRITE_GPR_T)
2481 && (((pinfo & INSN_WRITE_GPR_D)
2482 && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)
2483 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2484 || ((pinfo & INSN_WRITE_GPR_31)
2485 && (((prev_insn.insn_opcode >> OP_SH_RT)
2488 || (! mips_opts.mips16
2489 && (prev_pinfo & INSN_WRITE_GPR_D)
2490 && (((pinfo & INSN_WRITE_GPR_D)
2491 && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD)
2492 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2493 || ((pinfo & INSN_WRITE_GPR_31)
2494 && (((prev_insn.insn_opcode >> OP_SH_RD)
2497 || (mips_opts.mips16
2498 && (pinfo & MIPS16_INSN_WRITE_31)
2499 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
2500 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2501 && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode)
2503 /* If the branch writes a register that the previous
2504 instruction reads, we can not swap (we know that
2505 branches only write to RD or to $31). */
2506 || (! mips_opts.mips16
2507 && (pinfo & INSN_WRITE_GPR_D)
2508 && insn_uses_reg (&prev_insn,
2509 ((ip->insn_opcode >> OP_SH_RD)
2512 || (! mips_opts.mips16
2513 && (pinfo & INSN_WRITE_GPR_31)
2514 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2515 || (mips_opts.mips16
2516 && (pinfo & MIPS16_INSN_WRITE_31)
2517 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2518 /* If we are generating embedded PIC code, the branch
2519 might be expanded into a sequence which uses $at, so
2520 we can't swap with an instruction which reads it. */
2521 || (mips_pic == EMBEDDED_PIC
2522 && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG))
2523 /* If the previous previous instruction has a load
2524 delay, and sets a register that the branch reads, we
2526 || (! mips_opts.mips16
2527 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2528 /* Itbl support may require additional care here. */
2529 && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
2530 || (! gpr_interlocks
2531 && (prev_prev_insn.insn_mo->pinfo
2532 & INSN_LOAD_MEMORY_DELAY)))
2533 && insn_uses_reg (ip,
2534 ((prev_prev_insn.insn_opcode >> OP_SH_RT)
2537 /* If one instruction sets a condition code and the
2538 other one uses a condition code, we can not swap. */
2539 || ((pinfo & INSN_READ_COND_CODE)
2540 && (prev_pinfo & INSN_WRITE_COND_CODE))
2541 || ((pinfo & INSN_WRITE_COND_CODE)
2542 && (prev_pinfo & INSN_READ_COND_CODE))
2543 /* If the previous instruction uses the PC, we can not
2545 || (mips_opts.mips16
2546 && (prev_pinfo & MIPS16_INSN_READ_PC))
2547 /* If the previous instruction was extended, we can not
2549 || (mips_opts.mips16 && prev_insn_extended)
2550 /* If the previous instruction had a fixup in mips16
2551 mode, we can not swap. This normally means that the
2552 previous instruction was a 4 byte branch anyhow. */
2553 || (mips_opts.mips16 && prev_insn_fixp[0])
2554 /* If the previous instruction is a sync, sync.l, or
2555 sync.p, we can not swap. */
2556 || (prev_pinfo & INSN_SYNC))
2558 /* We could do even better for unconditional branches to
2559 portions of this object file; we could pick up the
2560 instruction at the destination, put it in the delay
2561 slot, and bump the destination address. */
2563 /* Update the previous insn information. */
2564 prev_prev_insn = *ip;
2565 prev_insn.insn_mo = &dummy_opcode;
2569 /* It looks like we can actually do the swap. */
2570 if (! mips_opts.mips16)
2575 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2576 memcpy (temp, prev_f, 4);
2577 memcpy (prev_f, f, 4);
2578 memcpy (f, temp, 4);
2579 if (prev_insn_fixp[0])
2581 prev_insn_fixp[0]->fx_frag = frag_now;
2582 prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal;
2584 if (prev_insn_fixp[1])
2586 prev_insn_fixp[1]->fx_frag = frag_now;
2587 prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal;
2589 if (prev_insn_fixp[2])
2591 prev_insn_fixp[2]->fx_frag = frag_now;
2592 prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal;
2594 if (prev_insn_fixp[0] && HAVE_NEWABI
2595 && prev_insn_frag != frag_now
2596 && (prev_insn_fixp[0]->fx_r_type
2597 == BFD_RELOC_MIPS_GOT_DISP
2598 || (prev_insn_fixp[0]->fx_r_type
2599 == BFD_RELOC_MIPS_CALL16)))
2601 /* To avoid confusion in tc_gen_reloc, we must
2602 ensure that this does not become a variant
2604 force_new_frag = TRUE;
2608 fixp[0]->fx_frag = prev_insn_frag;
2609 fixp[0]->fx_where = prev_insn_where;
2613 fixp[1]->fx_frag = prev_insn_frag;
2614 fixp[1]->fx_where = prev_insn_where;
2618 fixp[2]->fx_frag = prev_insn_frag;
2619 fixp[2]->fx_where = prev_insn_where;
2627 assert (prev_insn_fixp[0] == NULL);
2628 assert (prev_insn_fixp[1] == NULL);
2629 assert (prev_insn_fixp[2] == NULL);
2630 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2631 memcpy (temp, prev_f, 2);
2632 memcpy (prev_f, f, 2);
2633 if (*reloc_type != BFD_RELOC_MIPS16_JMP)
2635 assert (*reloc_type == BFD_RELOC_UNUSED);
2636 memcpy (f, temp, 2);
2640 memcpy (f, f + 2, 2);
2641 memcpy (f + 2, temp, 2);
2645 fixp[0]->fx_frag = prev_insn_frag;
2646 fixp[0]->fx_where = prev_insn_where;
2650 fixp[1]->fx_frag = prev_insn_frag;
2651 fixp[1]->fx_where = prev_insn_where;
2655 fixp[2]->fx_frag = prev_insn_frag;
2656 fixp[2]->fx_where = prev_insn_where;
2660 /* Update the previous insn information; leave prev_insn
2662 prev_prev_insn = *ip;
2664 prev_insn_is_delay_slot = 1;
2666 /* If that was an unconditional branch, forget the previous
2667 insn information. */
2668 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
2670 prev_prev_insn.insn_mo = &dummy_opcode;
2671 prev_insn.insn_mo = &dummy_opcode;
2674 prev_insn_fixp[0] = NULL;
2675 prev_insn_fixp[1] = NULL;
2676 prev_insn_fixp[2] = NULL;
2677 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2678 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2679 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2680 prev_insn_extended = 0;
2682 else if (pinfo & INSN_COND_BRANCH_LIKELY)
2684 /* We don't yet optimize a branch likely. What we should do
2685 is look at the target, copy the instruction found there
2686 into the delay slot, and increment the branch to jump to
2687 the next instruction. */
2689 /* Update the previous insn information. */
2690 prev_prev_insn = *ip;
2691 prev_insn.insn_mo = &dummy_opcode;
2692 prev_insn_fixp[0] = NULL;
2693 prev_insn_fixp[1] = NULL;
2694 prev_insn_fixp[2] = NULL;
2695 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2696 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2697 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2698 prev_insn_extended = 0;
2702 /* Update the previous insn information. */
2704 prev_prev_insn.insn_mo = &dummy_opcode;
2706 prev_prev_insn = prev_insn;
2709 /* Any time we see a branch, we always fill the delay slot
2710 immediately; since this insn is not a branch, we know it
2711 is not in a delay slot. */
2712 prev_insn_is_delay_slot = 0;
2714 prev_insn_fixp[0] = fixp[0];
2715 prev_insn_fixp[1] = fixp[1];
2716 prev_insn_fixp[2] = fixp[2];
2717 prev_insn_reloc_type[0] = reloc_type[0];
2718 prev_insn_reloc_type[1] = reloc_type[1];
2719 prev_insn_reloc_type[2] = reloc_type[2];
2720 if (mips_opts.mips16)
2721 prev_insn_extended = (ip->use_extend
2722 || *reloc_type > BFD_RELOC_UNUSED);
2725 prev_prev_insn_unreordered = prev_insn_unreordered;
2726 prev_insn_unreordered = 0;
2727 prev_insn_frag = frag_now;
2728 prev_insn_where = f - frag_now->fr_literal;
2729 prev_insn_valid = 1;
2731 else if (place == NULL)
2733 /* We need to record a bit of information even when we are not
2734 reordering, in order to determine the base address for mips16
2735 PC relative relocs. */
2736 prev_prev_insn = prev_insn;
2738 prev_insn_reloc_type[0] = reloc_type[0];
2739 prev_insn_reloc_type[1] = reloc_type[1];
2740 prev_insn_reloc_type[2] = reloc_type[2];
2741 prev_prev_insn_unreordered = prev_insn_unreordered;
2742 prev_insn_unreordered = 1;
2745 /* We just output an insn, so the next one doesn't have a label. */
2746 mips_clear_insn_labels ();
2748 /* We must ensure that the frag to which an instruction that was
2749 moved from a non-variant frag doesn't become a variant frag,
2750 otherwise tc_gen_reloc may get confused. */
2753 frag_wane (frag_now);
2758 /* This function forgets that there was any previous instruction or
2759 label. If PRESERVE is non-zero, it remembers enough information to
2760 know whether nops are needed before a noreorder section. */
2763 mips_no_prev_insn (preserve)
2768 prev_insn.insn_mo = &dummy_opcode;
2769 prev_prev_insn.insn_mo = &dummy_opcode;
2770 prev_nop_frag = NULL;
2771 prev_nop_frag_holds = 0;
2772 prev_nop_frag_required = 0;
2773 prev_nop_frag_since = 0;
2775 prev_insn_valid = 0;
2776 prev_insn_is_delay_slot = 0;
2777 prev_insn_unreordered = 0;
2778 prev_insn_extended = 0;
2779 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2780 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2781 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2782 prev_prev_insn_unreordered = 0;
2783 mips_clear_insn_labels ();
2786 /* This function must be called whenever we turn on noreorder or emit
2787 something other than instructions. It inserts any NOPS which might
2788 be needed by the previous instruction, and clears the information
2789 kept for the previous instructions. The INSNS parameter is true if
2790 instructions are to follow. */
2793 mips_emit_delays (insns)
2796 if (! mips_opts.noreorder)
2801 if ((! mips_opts.mips16
2802 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2803 && (! cop_interlocks
2804 && (prev_insn.insn_mo->pinfo
2805 & (INSN_LOAD_COPROC_DELAY
2806 | INSN_COPROC_MOVE_DELAY
2807 | INSN_WRITE_COND_CODE))))
2808 || (! hilo_interlocks
2809 && (prev_insn.insn_mo->pinfo
2812 || (! mips_opts.mips16
2814 && (prev_insn.insn_mo->pinfo
2815 & INSN_LOAD_MEMORY_DELAY))
2816 || (! mips_opts.mips16
2817 && mips_opts.isa == ISA_MIPS1
2818 && (prev_insn.insn_mo->pinfo
2819 & INSN_COPROC_MEMORY_DELAY)))
2821 /* Itbl support may require additional care here. */
2823 if ((! mips_opts.mips16
2824 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2825 && (! cop_interlocks
2826 && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
2827 || (! hilo_interlocks
2828 && ((prev_insn.insn_mo->pinfo & INSN_READ_HI)
2829 || (prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2832 if (prev_insn_unreordered)
2835 else if ((! mips_opts.mips16
2836 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2837 && (! cop_interlocks
2838 && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
2839 || (! hilo_interlocks
2840 && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
2841 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2843 /* Itbl support may require additional care here. */
2844 if (! prev_prev_insn_unreordered)
2848 if (mips_fix_4122_bugs && prev_insn.insn_mo->name)
2851 const char *pn = prev_insn.insn_mo->name;
2852 if (strncmp(pn, "macc", 4) == 0
2853 || strncmp(pn, "dmacc", 5) == 0
2854 || strncmp(pn, "dmult", 5) == 0)
2858 if (nops < min_nops)
2864 struct insn_label_list *l;
2868 /* Record the frag which holds the nop instructions, so
2869 that we can remove them if we don't need them. */
2870 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
2871 prev_nop_frag = frag_now;
2872 prev_nop_frag_holds = nops;
2873 prev_nop_frag_required = 0;
2874 prev_nop_frag_since = 0;
2877 for (; nops > 0; --nops)
2882 /* Move on to a new frag, so that it is safe to simply
2883 decrease the size of prev_nop_frag. */
2884 frag_wane (frag_now);
2888 for (l = insn_labels; l != NULL; l = l->next)
2892 assert (S_GET_SEGMENT (l->label) == now_seg);
2893 symbol_set_frag (l->label, frag_now);
2894 val = (valueT) frag_now_fix ();
2895 /* mips16 text labels are stored as odd. */
2896 if (mips_opts.mips16)
2898 S_SET_VALUE (l->label, val);
2903 /* Mark instruction labels in mips16 mode. */
2905 mips16_mark_labels ();
2907 mips_no_prev_insn (insns);
2910 /* Build an instruction created by a macro expansion. This is passed
2911 a pointer to the count of instructions created so far, an
2912 expression, the name of the instruction to build, an operand format
2913 string, and corresponding arguments. */
2917 macro_build (char *place,
2925 macro_build (place, counter, ep, name, fmt, va_alist)
2934 struct mips_cl_insn insn;
2935 bfd_reloc_code_real_type r[3];
2939 va_start (args, fmt);
2945 * If the macro is about to expand into a second instruction,
2946 * print a warning if needed. We need to pass ip as a parameter
2947 * to generate a better warning message here...
2949 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
2950 as_warn (_("Macro instruction expanded into multiple instructions"));
2953 * If the macro is about to expand into a second instruction,
2954 * and it is in a delay slot, print a warning.
2958 && mips_opts.noreorder
2959 && (prev_prev_insn.insn_mo->pinfo
2960 & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY
2961 | INSN_COND_BRANCH_LIKELY)) != 0)
2962 as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot"));
2965 ++*counter; /* bump instruction counter */
2967 if (mips_opts.mips16)
2969 mips16_macro_build (place, counter, ep, name, fmt, args);
2974 r[0] = BFD_RELOC_UNUSED;
2975 r[1] = BFD_RELOC_UNUSED;
2976 r[2] = BFD_RELOC_UNUSED;
2977 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
2978 assert (insn.insn_mo);
2979 assert (strcmp (name, insn.insn_mo->name) == 0);
2981 /* Search until we get a match for NAME. */
2984 /* It is assumed here that macros will never generate
2985 MDMX or MIPS-3D instructions. */
2986 if (strcmp (fmt, insn.insn_mo->args) == 0
2987 && insn.insn_mo->pinfo != INSN_MACRO
2988 && OPCODE_IS_MEMBER (insn.insn_mo,
2990 | (file_ase_mips16 ? INSN_MIPS16 : 0)),
2992 && (mips_opts.arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
2996 assert (insn.insn_mo->name);
2997 assert (strcmp (name, insn.insn_mo->name) == 0);
3000 insn.insn_opcode = insn.insn_mo->match;
3016 insn.insn_opcode |= va_arg (args, int) << OP_SH_RT;
3020 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE;
3025 insn.insn_opcode |= va_arg (args, int) << OP_SH_FT;
3031 insn.insn_opcode |= va_arg (args, int) << OP_SH_RD;
3036 int tmp = va_arg (args, int);
3038 insn.insn_opcode |= tmp << OP_SH_RT;
3039 insn.insn_opcode |= tmp << OP_SH_RD;
3045 insn.insn_opcode |= va_arg (args, int) << OP_SH_FS;
3052 insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT;
3056 insn.insn_opcode |= va_arg (args, int) << OP_SH_FD;
3060 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20;
3064 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19;
3068 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2;
3075 insn.insn_opcode |= va_arg (args, int) << OP_SH_RS;
3081 *r = (bfd_reloc_code_real_type) va_arg (args, int);
3082 assert (*r == BFD_RELOC_GPREL16
3083 || *r == BFD_RELOC_MIPS_LITERAL
3084 || *r == BFD_RELOC_MIPS_HIGHER
3085 || *r == BFD_RELOC_HI16_S
3086 || *r == BFD_RELOC_LO16
3087 || *r == BFD_RELOC_MIPS_GOT16
3088 || *r == BFD_RELOC_MIPS_CALL16
3089 || *r == BFD_RELOC_MIPS_GOT_DISP
3090 || *r == BFD_RELOC_MIPS_GOT_PAGE
3091 || *r == BFD_RELOC_MIPS_GOT_OFST
3092 || *r == BFD_RELOC_MIPS_GOT_LO16
3093 || *r == BFD_RELOC_MIPS_CALL_LO16
3094 || (ep->X_op == O_subtract
3095 && *r == BFD_RELOC_PCREL_LO16));
3099 *r = (bfd_reloc_code_real_type) va_arg (args, int);
3101 && (ep->X_op == O_constant
3102 || (ep->X_op == O_symbol
3103 && (*r == BFD_RELOC_MIPS_HIGHEST
3104 || *r == BFD_RELOC_HI16_S
3105 || *r == BFD_RELOC_HI16
3106 || *r == BFD_RELOC_GPREL16
3107 || *r == BFD_RELOC_MIPS_GOT_HI16
3108 || *r == BFD_RELOC_MIPS_CALL_HI16))
3109 || (ep->X_op == O_subtract
3110 && *r == BFD_RELOC_PCREL_HI16_S)));
3114 assert (ep != NULL);
3116 * This allows macro() to pass an immediate expression for
3117 * creating short branches without creating a symbol.
3118 * Note that the expression still might come from the assembly
3119 * input, in which case the value is not checked for range nor
3120 * is a relocation entry generated (yuck).
3122 if (ep->X_op == O_constant)
3124 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
3128 *r = BFD_RELOC_16_PCREL_S2;
3132 assert (ep != NULL);
3133 *r = BFD_RELOC_MIPS_JMP;
3137 insn.insn_opcode |= va_arg (args, unsigned long);
3146 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3148 append_insn (place, &insn, ep, r);
3152 mips16_macro_build (place, counter, ep, name, fmt, args)
3154 int *counter ATTRIBUTE_UNUSED;
3160 struct mips_cl_insn insn;
3161 bfd_reloc_code_real_type r[3]
3162 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3164 insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
3165 assert (insn.insn_mo);
3166 assert (strcmp (name, insn.insn_mo->name) == 0);
3168 while (strcmp (fmt, insn.insn_mo->args) != 0
3169 || insn.insn_mo->pinfo == INSN_MACRO)
3172 assert (insn.insn_mo->name);
3173 assert (strcmp (name, insn.insn_mo->name) == 0);
3176 insn.insn_opcode = insn.insn_mo->match;
3177 insn.use_extend = FALSE;
3196 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY;
3201 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX;
3205 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ;
3209 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z;
3219 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32;
3226 regno = va_arg (args, int);
3227 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
3228 insn.insn_opcode |= regno << MIPS16OP_SH_REG32R;
3249 assert (ep != NULL);
3251 if (ep->X_op != O_constant)
3252 *r = (int) BFD_RELOC_UNUSED + c;
3255 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
3256 FALSE, &insn.insn_opcode, &insn.use_extend,
3259 *r = BFD_RELOC_UNUSED;
3265 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6;
3272 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3274 append_insn (place, &insn, ep, r);
3278 * Generate a "jalr" instruction with a relocation hint to the called
3279 * function. This occurs in NewABI PIC code.
3282 macro_build_jalr (icnt, ep)
3293 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", "d,s",
3296 fix_new_exp (frag_now, f - frag_now->fr_literal,
3297 4, ep, FALSE, BFD_RELOC_MIPS_JALR);
3301 * Generate a "lui" instruction.
3304 macro_build_lui (place, counter, ep, regnum)
3310 expressionS high_expr;
3311 struct mips_cl_insn insn;
3312 bfd_reloc_code_real_type r[3]
3313 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3314 const char *name = "lui";
3315 const char *fmt = "t,u";
3317 assert (! mips_opts.mips16);
3323 high_expr.X_op = O_constant;
3324 high_expr.X_add_number = ep->X_add_number;
3327 if (high_expr.X_op == O_constant)
3329 /* we can compute the instruction now without a relocation entry */
3330 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
3332 *r = BFD_RELOC_UNUSED;
3336 assert (ep->X_op == O_symbol);
3337 /* _gp_disp is a special case, used from s_cpload. */
3338 assert (mips_pic == NO_PIC
3340 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0));
3341 *r = BFD_RELOC_HI16_S;
3345 * If the macro is about to expand into a second instruction,
3346 * print a warning if needed. We need to pass ip as a parameter
3347 * to generate a better warning message here...
3349 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
3350 as_warn (_("Macro instruction expanded into multiple instructions"));
3353 ++*counter; /* bump instruction counter */
3355 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
3356 assert (insn.insn_mo);
3357 assert (strcmp (name, insn.insn_mo->name) == 0);
3358 assert (strcmp (fmt, insn.insn_mo->args) == 0);
3360 insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT);
3361 if (*r == BFD_RELOC_UNUSED)
3363 insn.insn_opcode |= high_expr.X_add_number;
3364 append_insn (place, &insn, NULL, r);
3367 append_insn (place, &insn, &high_expr, r);
3370 /* Generate a sequence of instructions to do a load or store from a constant
3371 offset off of a base register (breg) into/from a target register (treg),
3372 using AT if necessary. */
3374 macro_build_ldst_constoffset (place, counter, ep, op, treg, breg)
3381 assert (ep->X_op == O_constant);
3383 /* Right now, this routine can only handle signed 32-bit contants. */
3384 if (! IS_SEXT_32BIT_NUM(ep->X_add_number))
3385 as_warn (_("operand overflow"));
3387 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
3389 /* Signed 16-bit offset will fit in the op. Easy! */
3390 macro_build (place, counter, ep, op, "t,o(b)", treg,
3391 (int) BFD_RELOC_LO16, breg);
3395 /* 32-bit offset, need multiple instructions and AT, like:
3396 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3397 addu $tempreg,$tempreg,$breg
3398 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3399 to handle the complete offset. */
3400 macro_build_lui (place, counter, ep, AT);
3403 macro_build (place, counter, (expressionS *) NULL, ADDRESS_ADD_INSN,
3404 "d,v,t", AT, AT, breg);
3407 macro_build (place, counter, ep, op, "t,o(b)", treg,
3408 (int) BFD_RELOC_LO16, AT);
3411 as_warn (_("Macro used $at after \".set noat\""));
3416 * Generates code to set the $at register to true (one)
3417 * if reg is less than the immediate expression.
3420 set_at (counter, reg, unsignedp)
3425 if (imm_expr.X_op == O_constant
3426 && imm_expr.X_add_number >= -0x8000
3427 && imm_expr.X_add_number < 0x8000)
3428 macro_build ((char *) NULL, counter, &imm_expr,
3429 unsignedp ? "sltiu" : "slti",
3430 "t,r,j", AT, reg, (int) BFD_RELOC_LO16);
3433 load_register (counter, AT, &imm_expr, HAVE_64BIT_GPRS);
3434 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3435 unsignedp ? "sltu" : "slt",
3436 "d,v,t", AT, reg, AT);
3440 /* Warn if an expression is not a constant. */
3443 check_absolute_expr (ip, ex)
3444 struct mips_cl_insn *ip;
3447 if (ex->X_op == O_big)
3448 as_bad (_("unsupported large constant"));
3449 else if (ex->X_op != O_constant)
3450 as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name);
3453 /* Count the leading zeroes by performing a binary chop. This is a
3454 bulky bit of source, but performance is a LOT better for the
3455 majority of values than a simple loop to count the bits:
3456 for (lcnt = 0; (lcnt < 32); lcnt++)
3457 if ((v) & (1 << (31 - lcnt)))
3459 However it is not code size friendly, and the gain will drop a bit
3460 on certain cached systems.
3462 #define COUNT_TOP_ZEROES(v) \
3463 (((v) & ~0xffff) == 0 \
3464 ? ((v) & ~0xff) == 0 \
3465 ? ((v) & ~0xf) == 0 \
3466 ? ((v) & ~0x3) == 0 \
3467 ? ((v) & ~0x1) == 0 \
3472 : ((v) & ~0x7) == 0 \
3475 : ((v) & ~0x3f) == 0 \
3476 ? ((v) & ~0x1f) == 0 \
3479 : ((v) & ~0x7f) == 0 \
3482 : ((v) & ~0xfff) == 0 \
3483 ? ((v) & ~0x3ff) == 0 \
3484 ? ((v) & ~0x1ff) == 0 \
3487 : ((v) & ~0x7ff) == 0 \
3490 : ((v) & ~0x3fff) == 0 \
3491 ? ((v) & ~0x1fff) == 0 \
3494 : ((v) & ~0x7fff) == 0 \
3497 : ((v) & ~0xffffff) == 0 \
3498 ? ((v) & ~0xfffff) == 0 \
3499 ? ((v) & ~0x3ffff) == 0 \
3500 ? ((v) & ~0x1ffff) == 0 \
3503 : ((v) & ~0x7ffff) == 0 \
3506 : ((v) & ~0x3fffff) == 0 \
3507 ? ((v) & ~0x1fffff) == 0 \
3510 : ((v) & ~0x7fffff) == 0 \
3513 : ((v) & ~0xfffffff) == 0 \
3514 ? ((v) & ~0x3ffffff) == 0 \
3515 ? ((v) & ~0x1ffffff) == 0 \
3518 : ((v) & ~0x7ffffff) == 0 \
3521 : ((v) & ~0x3fffffff) == 0 \
3522 ? ((v) & ~0x1fffffff) == 0 \
3525 : ((v) & ~0x7fffffff) == 0 \
3530 * This routine generates the least number of instructions neccessary to load
3531 * an absolute expression value into a register.
3534 load_register (counter, reg, ep, dbl)
3541 expressionS hi32, lo32;
3543 if (ep->X_op != O_big)
3545 assert (ep->X_op == O_constant);
3546 if (ep->X_add_number < 0x8000
3547 && (ep->X_add_number >= 0
3548 || (ep->X_add_number >= -0x8000
3551 || sizeof (ep->X_add_number) > 4))))
3553 /* We can handle 16 bit signed values with an addiu to
3554 $zero. No need to ever use daddiu here, since $zero and
3555 the result are always correct in 32 bit mode. */
3556 macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3557 (int) BFD_RELOC_LO16);
3560 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
3562 /* We can handle 16 bit unsigned values with an ori to
3564 macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0,
3565 (int) BFD_RELOC_LO16);
3568 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)
3571 || sizeof (ep->X_add_number) > 4
3572 || (ep->X_add_number & 0x80000000) == 0))
3573 || ((HAVE_32BIT_GPRS || ! dbl)
3574 && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0)
3577 && ((ep->X_add_number &~ (offsetT) 0xffffffff)
3578 == ~ (offsetT) 0xffffffff)))
3580 /* 32 bit values require an lui. */
3581 macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg,
3582 (int) BFD_RELOC_HI16);
3583 if ((ep->X_add_number & 0xffff) != 0)
3584 macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg,
3585 (int) BFD_RELOC_LO16);
3590 /* The value is larger than 32 bits. */
3592 if (HAVE_32BIT_GPRS)
3594 as_bad (_("Number (0x%lx) larger than 32 bits"),
3595 (unsigned long) ep->X_add_number);
3596 macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3597 (int) BFD_RELOC_LO16);
3601 if (ep->X_op != O_big)
3604 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3605 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3606 hi32.X_add_number &= 0xffffffff;
3608 lo32.X_add_number &= 0xffffffff;
3612 assert (ep->X_add_number > 2);
3613 if (ep->X_add_number == 3)
3614 generic_bignum[3] = 0;
3615 else if (ep->X_add_number > 4)
3616 as_bad (_("Number larger than 64 bits"));
3617 lo32.X_op = O_constant;
3618 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
3619 hi32.X_op = O_constant;
3620 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
3623 if (hi32.X_add_number == 0)
3628 unsigned long hi, lo;
3630 if (hi32.X_add_number == (offsetT) 0xffffffff)
3632 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
3634 macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j",
3635 reg, 0, (int) BFD_RELOC_LO16);
3638 if (lo32.X_add_number & 0x80000000)
3640 macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg,
3641 (int) BFD_RELOC_HI16);
3642 if (lo32.X_add_number & 0xffff)
3643 macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i",
3644 reg, reg, (int) BFD_RELOC_LO16);
3649 /* Check for 16bit shifted constant. We know that hi32 is
3650 non-zero, so start the mask on the first bit of the hi32
3655 unsigned long himask, lomask;
3659 himask = 0xffff >> (32 - shift);
3660 lomask = (0xffff << shift) & 0xffffffff;
3664 himask = 0xffff << (shift - 32);
3667 if ((hi32.X_add_number & ~(offsetT) himask) == 0
3668 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
3672 tmp.X_op = O_constant;
3674 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
3675 | (lo32.X_add_number >> shift));
3677 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
3678 macro_build ((char *) NULL, counter, &tmp,
3679 "ori", "t,r,i", reg, 0,
3680 (int) BFD_RELOC_LO16);
3681 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3682 (shift >= 32) ? "dsll32" : "dsll",
3684 (shift >= 32) ? shift - 32 : shift);
3689 while (shift <= (64 - 16));
3691 /* Find the bit number of the lowest one bit, and store the
3692 shifted value in hi/lo. */
3693 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
3694 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
3698 while ((lo & 1) == 0)
3703 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
3709 while ((hi & 1) == 0)
3718 /* Optimize if the shifted value is a (power of 2) - 1. */
3719 if ((hi == 0 && ((lo + 1) & lo) == 0)
3720 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
3722 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
3727 /* This instruction will set the register to be all
3729 tmp.X_op = O_constant;
3730 tmp.X_add_number = (offsetT) -1;
3731 macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j",
3732 reg, 0, (int) BFD_RELOC_LO16);
3736 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3737 (bit >= 32) ? "dsll32" : "dsll",
3739 (bit >= 32) ? bit - 32 : bit);
3741 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3742 (shift >= 32) ? "dsrl32" : "dsrl",
3744 (shift >= 32) ? shift - 32 : shift);
3749 /* Sign extend hi32 before calling load_register, because we can
3750 generally get better code when we load a sign extended value. */
3751 if ((hi32.X_add_number & 0x80000000) != 0)
3752 hi32.X_add_number |= ~(offsetT) 0xffffffff;
3753 load_register (counter, reg, &hi32, 0);
3756 if ((lo32.X_add_number & 0xffff0000) == 0)
3760 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3761 "dsll32", "d,w,<", reg, freg, 0);
3769 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
3771 macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg,
3772 (int) BFD_RELOC_HI16);
3773 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3774 "dsrl32", "d,w,<", reg, reg, 0);
3780 macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll",
3781 "d,w,<", reg, freg, 16);
3785 mid16.X_add_number >>= 16;
3786 macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg,
3787 freg, (int) BFD_RELOC_LO16);
3788 macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll",
3789 "d,w,<", reg, reg, 16);
3792 if ((lo32.X_add_number & 0xffff) != 0)
3793 macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg,
3794 (int) BFD_RELOC_LO16);
3797 /* Load an address into a register. */
3800 load_address (counter, reg, ep, used_at)
3808 if (ep->X_op != O_constant
3809 && ep->X_op != O_symbol)
3811 as_bad (_("expression too complex"));
3812 ep->X_op = O_constant;
3815 if (ep->X_op == O_constant)
3817 load_register (counter, reg, ep, HAVE_64BIT_ADDRESSES);
3821 if (mips_pic == NO_PIC)
3823 /* If this is a reference to a GP relative symbol, we want
3824 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3826 lui $reg,<sym> (BFD_RELOC_HI16_S)
3827 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3828 If we have an addend, we always use the latter form.
3830 With 64bit address space and a usable $at we want
3831 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3832 lui $at,<sym> (BFD_RELOC_HI16_S)
3833 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3834 daddiu $at,<sym> (BFD_RELOC_LO16)
3838 If $at is already in use, we use a path which is suboptimal
3839 on superscalar processors.
3840 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3841 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3843 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3845 daddiu $reg,<sym> (BFD_RELOC_LO16)
3847 if (HAVE_64BIT_ADDRESSES)
3849 /* We don't do GP optimization for now because RELAX_ENCODE can't
3850 hold the data for such large chunks. */
3852 if (*used_at == 0 && ! mips_opts.noat)
3854 macro_build (p, counter, ep, "lui", "t,u",
3855 reg, (int) BFD_RELOC_MIPS_HIGHEST);
3856 macro_build (p, counter, ep, "lui", "t,u",
3857 AT, (int) BFD_RELOC_HI16_S);
3858 macro_build (p, counter, ep, "daddiu", "t,r,j",
3859 reg, reg, (int) BFD_RELOC_MIPS_HIGHER);
3860 macro_build (p, counter, ep, "daddiu", "t,r,j",
3861 AT, AT, (int) BFD_RELOC_LO16);
3862 macro_build (p, counter, (expressionS *) NULL, "dsll32",
3863 "d,w,<", reg, reg, 0);
3864 macro_build (p, counter, (expressionS *) NULL, "daddu",
3865 "d,v,t", reg, reg, AT);
3870 macro_build (p, counter, ep, "lui", "t,u",
3871 reg, (int) BFD_RELOC_MIPS_HIGHEST);
3872 macro_build (p, counter, ep, "daddiu", "t,r,j",
3873 reg, reg, (int) BFD_RELOC_MIPS_HIGHER);
3874 macro_build (p, counter, (expressionS *) NULL, "dsll",
3875 "d,w,<", reg, reg, 16);
3876 macro_build (p, counter, ep, "daddiu", "t,r,j",
3877 reg, reg, (int) BFD_RELOC_HI16_S);
3878 macro_build (p, counter, (expressionS *) NULL, "dsll",
3879 "d,w,<", reg, reg, 16);
3880 macro_build (p, counter, ep, "daddiu", "t,r,j",
3881 reg, reg, (int) BFD_RELOC_LO16);
3886 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
3887 && ! nopic_need_relax (ep->X_add_symbol, 1))
3890 macro_build ((char *) NULL, counter, ep, ADDRESS_ADDI_INSN,
3891 "t,r,j", reg, mips_gp_register,
3892 (int) BFD_RELOC_GPREL16);
3893 p = frag_var (rs_machine_dependent, 8, 0,
3894 RELAX_ENCODE (4, 8, 0, 4, 0,
3895 mips_opts.warn_about_macros),
3896 ep->X_add_symbol, 0, NULL);
3898 macro_build_lui (p, counter, ep, reg);
3901 macro_build (p, counter, ep, ADDRESS_ADDI_INSN,
3902 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3905 else if (mips_pic == SVR4_PIC && ! mips_big_got)
3909 /* If this is a reference to an external symbol, we want
3910 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3912 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3914 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3915 If there is a constant, it must be added in after.
3917 If we have NewABI, we want
3918 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3919 unless we're referencing a global symbol with a non-zero
3920 offset, in which case cst must be added separately. */
3925 if (ep->X_add_number)
3927 frag_now->tc_frag_data.tc_fr_offset =
3928 ex.X_add_number = ep->X_add_number;
3929 ep->X_add_number = 0;
3930 macro_build ((char *) NULL, counter, ep, ADDRESS_LOAD_INSN,
3931 "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_DISP,
3933 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3934 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3935 ex.X_op = O_constant;
3936 macro_build ((char *) NULL, counter, &ex, ADDRESS_ADDI_INSN,
3937 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3938 p = frag_var (rs_machine_dependent, 8, 0,
3939 RELAX_ENCODE (8, 4, 0, 0, 0,
3940 mips_opts.warn_about_macros),
3941 ep->X_add_symbol, 0, (char *) NULL);
3942 ep->X_add_number = ex.X_add_number;
3945 macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3946 (int) BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
3950 /* To avoid confusion in tc_gen_reloc, we must ensure
3951 that this does not become a variant frag. */
3952 frag_wane (frag_now);
3958 ex.X_add_number = ep->X_add_number;
3959 ep->X_add_number = 0;
3961 macro_build ((char *) NULL, counter, ep, ADDRESS_LOAD_INSN,
3962 "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16,
3964 macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", "");
3965 p = frag_var (rs_machine_dependent, 4, 0,
3966 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros),
3967 ep->X_add_symbol, (offsetT) 0, (char *) NULL);
3968 macro_build (p, counter, ep, ADDRESS_ADDI_INSN,
3969 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3971 if (ex.X_add_number != 0)
3973 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3974 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3975 ex.X_op = O_constant;
3976 macro_build ((char *) NULL, counter, &ex, ADDRESS_ADDI_INSN,
3977 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3981 else if (mips_pic == SVR4_PIC)
3986 /* This is the large GOT case. If this is a reference to an
3987 external symbol, we want
3988 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3990 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3992 Otherwise, for a reference to a local symbol in old ABI, we want
3993 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3995 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3996 If there is a constant, it must be added in after.
3998 In the NewABI, for local symbols, with or without offsets, we want:
3999 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4000 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4006 frag_now->tc_frag_data.tc_fr_offset =
4007 ex.X_add_number = ep->X_add_number;
4008 ep->X_add_number = 0;
4009 macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg,
4010 (int) BFD_RELOC_MIPS_GOT_HI16);
4011 macro_build ((char *) NULL, counter, (expressionS *) NULL,
4012 ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
4013 macro_build ((char *) NULL, counter, ep, ADDRESS_LOAD_INSN,
4014 "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg);
4015 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4016 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4017 else if (ex.X_add_number)
4019 ex.X_op = O_constant;
4020 macro_build ((char *) NULL, counter, &ex, ADDRESS_ADDI_INSN,
4021 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
4024 ep->X_add_number = ex.X_add_number;
4025 p = frag_var (rs_machine_dependent, 8, 0,
4026 RELAX_ENCODE (ex.X_add_number ? 16 : 12, 8, 0, 4, 0,
4027 mips_opts.warn_about_macros),
4028 ep->X_add_symbol, 0, (char *) NULL);
4029 macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4030 (int) BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
4031 macro_build (p + 4, counter, ep, ADDRESS_ADDI_INSN, "t,r,j",
4032 reg, reg, (int) BFD_RELOC_MIPS_GOT_OFST);
4036 ex.X_add_number = ep->X_add_number;
4037 ep->X_add_number = 0;
4038 if (reg_needs_delay (mips_gp_register))
4043 macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg,
4044 (int) BFD_RELOC_MIPS_GOT_HI16);
4045 macro_build ((char *) NULL, counter, (expressionS *) NULL,
4046 ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
4047 macro_build ((char *) NULL, counter, ep, ADDRESS_LOAD_INSN,
4048 "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg);
4049 p = frag_var (rs_machine_dependent, 12 + off, 0,
4050 RELAX_ENCODE (12, 12 + off, off, 8 + off, 0,
4051 mips_opts.warn_about_macros),
4052 ep->X_add_symbol, 0, NULL);
4055 /* We need a nop before loading from $gp. This special
4056 check is required because the lui which starts the main
4057 instruction stream does not refer to $gp, and so will not
4058 insert the nop which may be required. */
4059 macro_build (p, counter, (expressionS *) NULL, "nop", "");
4062 macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4063 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
4065 macro_build (p, counter, (expressionS *) NULL, "nop", "");
4067 macro_build (p, counter, ep, ADDRESS_ADDI_INSN,
4068 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
4070 if (ex.X_add_number != 0)
4072 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4073 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4074 ex.X_op = O_constant;
4075 macro_build ((char *) NULL, counter, &ex, ADDRESS_ADDI_INSN,
4076 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
4080 else if (mips_pic == EMBEDDED_PIC)
4083 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4085 macro_build ((char *) NULL, counter, ep, ADDRESS_ADDI_INSN,
4086 "t,r,j", reg, mips_gp_register, (int) BFD_RELOC_GPREL16);
4092 /* Move the contents of register SOURCE into register DEST. */
4095 move_register (counter, dest, source)
4100 macro_build ((char *) NULL, counter, (expressionS *) NULL,
4101 HAVE_32BIT_GPRS ? "addu" : "daddu",
4102 "d,v,t", dest, source, 0);
4107 * This routine implements the seemingly endless macro or synthesized
4108 * instructions and addressing modes in the mips assembly language. Many
4109 * of these macros are simple and are similar to each other. These could
4110 * probably be handled by some kind of table or grammer aproach instead of
4111 * this verbose method. Others are not simple macros but are more like
4112 * optimizing code generation.
4113 * One interesting optimization is when several store macros appear
4114 * consecutivly that would load AT with the upper half of the same address.
4115 * The ensuing load upper instructions are ommited. This implies some kind
4116 * of global optimization. We currently only optimize within a single macro.
4117 * For many of the load and store macros if the address is specified as a
4118 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4119 * first load register 'at' with zero and use it as the base register. The
4120 * mips assembler simply uses register $zero. Just one tiny optimization
4125 struct mips_cl_insn *ip;
4127 register int treg, sreg, dreg, breg;
4143 bfd_reloc_code_real_type r;
4144 int hold_mips_optimize;
4146 assert (! mips_opts.mips16);
4148 treg = (ip->insn_opcode >> 16) & 0x1f;
4149 dreg = (ip->insn_opcode >> 11) & 0x1f;
4150 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
4151 mask = ip->insn_mo->mask;
4153 expr1.X_op = O_constant;
4154 expr1.X_op_symbol = NULL;
4155 expr1.X_add_symbol = NULL;
4156 expr1.X_add_number = 1;
4158 /* Umatched fixups should not be put in the same frag as a relaxable
4159 macro. For example, suppose we have:
4163 addiu $4,$4,%lo(l1) # 3
4165 If instructions 1 and 2 were put in the same frag, md_frob_file would
4166 move the fixup for #1 after the fixups for the "unrelaxed" version of
4167 #2. This would confuse tc_gen_reloc, which expects the relocations
4168 for #2 to be the last for that frag.
4170 Also, if tc_gen_reloc sees certain relocations in a variant frag,
4171 it assumes that they belong to a relaxable macro. We mustn't put
4172 other uses of such relocations into a variant frag.
4174 To avoid both problems, finish the current frag it contains a
4175 %reloc() operator. The macro then goes into a new frag. */
4176 if (prev_reloc_op_frag == frag_now)
4178 frag_wane (frag_now);
4192 mips_emit_delays (TRUE);
4193 ++mips_opts.noreorder;
4194 mips_any_noreorder = 1;
4196 expr1.X_add_number = 8;
4197 macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg);
4199 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
4202 move_register (&icnt, dreg, sreg);
4203 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4204 dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
4206 --mips_opts.noreorder;
4227 if (imm_expr.X_op == O_constant
4228 && imm_expr.X_add_number >= -0x8000
4229 && imm_expr.X_add_number < 0x8000)
4231 macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg,
4232 (int) BFD_RELOC_LO16);
4235 load_register (&icnt, AT, &imm_expr, dbl);
4236 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t",
4256 if (imm_expr.X_op == O_constant
4257 && imm_expr.X_add_number >= 0
4258 && imm_expr.X_add_number < 0x10000)
4260 if (mask != M_NOR_I)
4261 macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg,
4262 sreg, (int) BFD_RELOC_LO16);
4265 macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i",
4266 treg, sreg, (int) BFD_RELOC_LO16);
4267 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nor",
4268 "d,v,t", treg, treg, 0);
4273 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
4274 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t",
4292 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4294 macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg,
4298 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
4299 macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT);
4307 macro_build ((char *) NULL, &icnt, &offset_expr,
4308 likely ? "bgezl" : "bgez", "s,p", sreg);
4313 macro_build ((char *) NULL, &icnt, &offset_expr,
4314 likely ? "blezl" : "blez", "s,p", treg);
4317 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4319 macro_build ((char *) NULL, &icnt, &offset_expr,
4320 likely ? "beql" : "beq", "s,t,p", AT, 0);
4326 /* check for > max integer */
4327 maxnum = 0x7fffffff;
4328 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4335 if (imm_expr.X_op == O_constant
4336 && imm_expr.X_add_number >= maxnum
4337 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4340 /* result is always false */
4344 as_warn (_("Branch %s is always false (nop)"),
4346 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop",
4352 as_warn (_("Branch likely %s is always false"),
4354 macro_build ((char *) NULL, &icnt, &offset_expr, "bnel",
4359 if (imm_expr.X_op != O_constant)
4360 as_bad (_("Unsupported large constant"));
4361 ++imm_expr.X_add_number;
4365 if (mask == M_BGEL_I)
4367 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4369 macro_build ((char *) NULL, &icnt, &offset_expr,
4370 likely ? "bgezl" : "bgez", "s,p", sreg);
4373 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4375 macro_build ((char *) NULL, &icnt, &offset_expr,
4376 likely ? "bgtzl" : "bgtz", "s,p", sreg);
4379 maxnum = 0x7fffffff;
4380 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4387 maxnum = - maxnum - 1;
4388 if (imm_expr.X_op == O_constant
4389 && imm_expr.X_add_number <= maxnum
4390 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4393 /* result is always true */
4394 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
4395 macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p");
4398 set_at (&icnt, sreg, 0);
4399 macro_build ((char *) NULL, &icnt, &offset_expr,
4400 likely ? "beql" : "beq", "s,t,p", AT, 0);
4410 macro_build ((char *) NULL, &icnt, &offset_expr,
4411 likely ? "beql" : "beq", "s,t,p", 0, treg);
4414 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4415 "d,v,t", AT, sreg, treg);
4416 macro_build ((char *) NULL, &icnt, &offset_expr,
4417 likely ? "beql" : "beq", "s,t,p", AT, 0);
4425 && imm_expr.X_op == O_constant
4426 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4428 if (imm_expr.X_op != O_constant)
4429 as_bad (_("Unsupported large constant"));
4430 ++imm_expr.X_add_number;
4434 if (mask == M_BGEUL_I)
4436 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4438 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4440 macro_build ((char *) NULL, &icnt, &offset_expr,
4441 likely ? "bnel" : "bne", "s,t,p", sreg, 0);
4444 set_at (&icnt, sreg, 1);
4445 macro_build ((char *) NULL, &icnt, &offset_expr,
4446 likely ? "beql" : "beq", "s,t,p", AT, 0);
4454 macro_build ((char *) NULL, &icnt, &offset_expr,
4455 likely ? "bgtzl" : "bgtz", "s,p", sreg);
4460 macro_build ((char *) NULL, &icnt, &offset_expr,
4461 likely ? "bltzl" : "bltz", "s,p", treg);
4464 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4466 macro_build ((char *) NULL, &icnt, &offset_expr,
4467 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4475 macro_build ((char *) NULL, &icnt, &offset_expr,
4476 likely ? "bnel" : "bne", "s,t,p", sreg, 0);
4481 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4482 "d,v,t", AT, treg, sreg);
4483 macro_build ((char *) NULL, &icnt, &offset_expr,
4484 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4492 macro_build ((char *) NULL, &icnt, &offset_expr,
4493 likely ? "blezl" : "blez", "s,p", sreg);
4498 macro_build ((char *) NULL, &icnt, &offset_expr,
4499 likely ? "bgezl" : "bgez", "s,p", treg);
4502 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4504 macro_build ((char *) NULL, &icnt, &offset_expr,
4505 likely ? "beql" : "beq", "s,t,p", AT, 0);
4511 maxnum = 0x7fffffff;
4512 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4519 if (imm_expr.X_op == O_constant
4520 && imm_expr.X_add_number >= maxnum
4521 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4523 if (imm_expr.X_op != O_constant)
4524 as_bad (_("Unsupported large constant"));
4525 ++imm_expr.X_add_number;
4529 if (mask == M_BLTL_I)
4531 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4533 macro_build ((char *) NULL, &icnt, &offset_expr,
4534 likely ? "bltzl" : "bltz", "s,p", sreg);
4537 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4539 macro_build ((char *) NULL, &icnt, &offset_expr,
4540 likely ? "blezl" : "blez", "s,p", sreg);
4543 set_at (&icnt, sreg, 0);
4544 macro_build ((char *) NULL, &icnt, &offset_expr,
4545 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4553 macro_build ((char *) NULL, &icnt, &offset_expr,
4554 likely ? "beql" : "beq", "s,t,p", sreg, 0);
4559 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4560 "d,v,t", AT, treg, sreg);
4561 macro_build ((char *) NULL, &icnt, &offset_expr,
4562 likely ? "beql" : "beq", "s,t,p", AT, 0);
4570 && imm_expr.X_op == O_constant
4571 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4573 if (imm_expr.X_op != O_constant)
4574 as_bad (_("Unsupported large constant"));
4575 ++imm_expr.X_add_number;
4579 if (mask == M_BLTUL_I)
4581 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4583 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4585 macro_build ((char *) NULL, &icnt, &offset_expr,
4586 likely ? "beql" : "beq",
4590 set_at (&icnt, sreg, 1);
4591 macro_build ((char *) NULL, &icnt, &offset_expr,
4592 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4600 macro_build ((char *) NULL, &icnt, &offset_expr,
4601 likely ? "bltzl" : "bltz", "s,p", sreg);
4606 macro_build ((char *) NULL, &icnt, &offset_expr,
4607 likely ? "bgtzl" : "bgtz", "s,p", treg);
4610 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4612 macro_build ((char *) NULL, &icnt, &offset_expr,
4613 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4623 macro_build ((char *) NULL, &icnt, &offset_expr,
4624 likely ? "bnel" : "bne", "s,t,p", 0, treg);
4627 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4630 macro_build ((char *) NULL, &icnt, &offset_expr,
4631 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4646 as_warn (_("Divide by zero."));
4648 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4651 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4656 mips_emit_delays (TRUE);
4657 ++mips_opts.noreorder;
4658 mips_any_noreorder = 1;
4661 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4662 "s,t,q", treg, 0, 7);
4663 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4664 dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4668 expr1.X_add_number = 8;
4669 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4670 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4671 dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4672 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4675 expr1.X_add_number = -1;
4676 macro_build ((char *) NULL, &icnt, &expr1,
4677 dbl ? "daddiu" : "addiu",
4678 "t,r,j", AT, 0, (int) BFD_RELOC_LO16);
4679 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
4680 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT);
4683 expr1.X_add_number = 1;
4684 macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0,
4685 (int) BFD_RELOC_LO16);
4686 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsll32",
4687 "d,w,<", AT, AT, 31);
4691 expr1.X_add_number = 0x80000000;
4692 macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT,
4693 (int) BFD_RELOC_HI16);
4697 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4698 "s,t,q", sreg, AT, 6);
4699 /* We want to close the noreorder block as soon as possible, so
4700 that later insns are available for delay slot filling. */
4701 --mips_opts.noreorder;
4705 expr1.X_add_number = 8;
4706 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT);
4707 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
4710 /* We want to close the noreorder block as soon as possible, so
4711 that later insns are available for delay slot filling. */
4712 --mips_opts.noreorder;
4714 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4717 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d", dreg);
4756 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4758 as_warn (_("Divide by zero."));
4760 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4763 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4767 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4769 if (strcmp (s2, "mflo") == 0)
4770 move_register (&icnt, dreg, sreg);
4772 move_register (&icnt, dreg, 0);
4775 if (imm_expr.X_op == O_constant
4776 && imm_expr.X_add_number == -1
4777 && s[strlen (s) - 1] != 'u')
4779 if (strcmp (s2, "mflo") == 0)
4781 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4782 dbl ? "dneg" : "neg", "d,w", dreg, sreg);
4785 move_register (&icnt, dreg, 0);
4789 load_register (&icnt, AT, &imm_expr, dbl);
4790 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4792 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg);
4811 mips_emit_delays (TRUE);
4812 ++mips_opts.noreorder;
4813 mips_any_noreorder = 1;
4816 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4817 "s,t,q", treg, 0, 7);
4818 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4820 /* We want to close the noreorder block as soon as possible, so
4821 that later insns are available for delay slot filling. */
4822 --mips_opts.noreorder;
4826 expr1.X_add_number = 8;
4827 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4828 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4831 /* We want to close the noreorder block as soon as possible, so
4832 that later insns are available for delay slot filling. */
4833 --mips_opts.noreorder;
4834 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4837 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg);
4843 /* Load the address of a symbol into a register. If breg is not
4844 zero, we then add a base register to it. */
4846 if (dbl && HAVE_32BIT_GPRS)
4847 as_warn (_("dla used to load 32-bit register"));
4849 if (! dbl && HAVE_64BIT_OBJECTS)
4850 as_warn (_("la used to load 64-bit address"));
4852 if (offset_expr.X_op == O_constant
4853 && offset_expr.X_add_number >= -0x8000
4854 && offset_expr.X_add_number < 0x8000)
4856 macro_build ((char *) NULL, &icnt, &offset_expr,
4857 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4858 "t,r,j", treg, sreg, (int) BFD_RELOC_LO16);
4873 /* When generating embedded PIC code, we permit expressions of
4876 la $treg,foo-bar($breg)
4877 where bar is an address in the current section. These are used
4878 when getting the addresses of functions. We don't permit
4879 X_add_number to be non-zero, because if the symbol is
4880 external the relaxing code needs to know that any addend is
4881 purely the offset to X_op_symbol. */
4882 if (mips_pic == EMBEDDED_PIC
4883 && offset_expr.X_op == O_subtract
4884 && (symbol_constant_p (offset_expr.X_op_symbol)
4885 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
4886 : (symbol_equated_p (offset_expr.X_op_symbol)
4888 (symbol_get_value_expression (offset_expr.X_op_symbol)
4891 && (offset_expr.X_add_number == 0
4892 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
4898 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4899 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
4903 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4904 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
4905 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4906 (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu",
4907 "d,v,t", tempreg, tempreg, breg);
4909 macro_build ((char *) NULL, &icnt, &offset_expr,
4910 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4911 "t,r,j", treg, tempreg, (int) BFD_RELOC_PCREL_LO16);
4917 if (offset_expr.X_op != O_symbol
4918 && offset_expr.X_op != O_constant)
4920 as_bad (_("expression too complex"));
4921 offset_expr.X_op = O_constant;
4924 if (offset_expr.X_op == O_constant)
4925 load_register (&icnt, tempreg, &offset_expr,
4926 ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
4927 ? (dbl || HAVE_64BIT_ADDRESSES)
4928 : HAVE_64BIT_ADDRESSES));
4929 else if (mips_pic == NO_PIC)
4931 /* If this is a reference to a GP relative symbol, we want
4932 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4934 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4935 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4936 If we have a constant, we need two instructions anyhow,
4937 so we may as well always use the latter form.
4939 With 64bit address space and a usable $at we want
4940 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4941 lui $at,<sym> (BFD_RELOC_HI16_S)
4942 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4943 daddiu $at,<sym> (BFD_RELOC_LO16)
4945 daddu $tempreg,$tempreg,$at
4947 If $at is already in use, we use a path which is suboptimal
4948 on superscalar processors.
4949 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4950 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4952 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4954 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4957 if (HAVE_64BIT_ADDRESSES)
4959 /* We don't do GP optimization for now because RELAX_ENCODE can't
4960 hold the data for such large chunks. */
4962 if (used_at == 0 && ! mips_opts.noat)
4964 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4965 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
4966 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4967 AT, (int) BFD_RELOC_HI16_S);
4968 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4969 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
4970 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4971 AT, AT, (int) BFD_RELOC_LO16);
4972 macro_build (p, &icnt, (expressionS *) NULL, "dsll32",
4973 "d,w,<", tempreg, tempreg, 0);
4974 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
4975 "d,v,t", tempreg, tempreg, AT);
4980 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4981 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
4982 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4983 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
4984 macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<",
4985 tempreg, tempreg, 16);
4986 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4987 tempreg, tempreg, (int) BFD_RELOC_HI16_S);
4988 macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<",
4989 tempreg, tempreg, 16);
4990 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4991 tempreg, tempreg, (int) BFD_RELOC_LO16);
4996 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
4997 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
5000 macro_build ((char *) NULL, &icnt, &offset_expr,
5001 ADDRESS_ADDI_INSN, "t,r,j", tempreg,
5002 mips_gp_register, (int) BFD_RELOC_GPREL16);
5003 p = frag_var (rs_machine_dependent, 8, 0,
5004 RELAX_ENCODE (4, 8, 0, 4, 0,
5005 mips_opts.warn_about_macros),
5006 offset_expr.X_add_symbol, 0, NULL);
5008 macro_build_lui (p, &icnt, &offset_expr, tempreg);
5011 macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
5012 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5015 else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI)
5017 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5019 /* If this is a reference to an external symbol, and there
5020 is no constant, we want
5021 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5022 or if tempreg is PIC_CALL_REG
5023 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5024 For a local symbol, we want
5025 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5027 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5029 If we have a small constant, and this is a reference to
5030 an external symbol, we want
5031 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5033 addiu $tempreg,$tempreg,<constant>
5034 For a local symbol, we want the same instruction
5035 sequence, but we output a BFD_RELOC_LO16 reloc on the
5038 If we have a large constant, and this is a reference to
5039 an external symbol, we want
5040 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5041 lui $at,<hiconstant>
5042 addiu $at,$at,<loconstant>
5043 addu $tempreg,$tempreg,$at
5044 For a local symbol, we want the same instruction
5045 sequence, but we output a BFD_RELOC_LO16 reloc on the
5049 expr1.X_add_number = offset_expr.X_add_number;
5050 offset_expr.X_add_number = 0;
5052 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
5053 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
5054 macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5055 "t,o(b)", tempreg, lw_reloc_type, mips_gp_register);
5056 if (expr1.X_add_number == 0)
5065 /* We're going to put in an addu instruction using
5066 tempreg, so we may as well insert the nop right
5068 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5072 p = frag_var (rs_machine_dependent, 8 - off, 0,
5073 RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0,
5075 ? mips_opts.warn_about_macros
5077 offset_expr.X_add_symbol, 0, NULL);
5080 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5083 macro_build (p, &icnt, &expr1, ADDRESS_ADDI_INSN,
5084 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5085 /* FIXME: If breg == 0, and the next instruction uses
5086 $tempreg, then if this variant case is used an extra
5087 nop will be generated. */
5089 else if (expr1.X_add_number >= -0x8000
5090 && expr1.X_add_number < 0x8000)
5092 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5094 macro_build ((char *) NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
5095 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5096 frag_var (rs_machine_dependent, 0, 0,
5097 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
5098 offset_expr.X_add_symbol, 0, NULL);
5104 /* If we are going to add in a base register, and the
5105 target register and the base register are the same,
5106 then we are using AT as a temporary register. Since
5107 we want to load the constant into AT, we add our
5108 current AT (from the global offset table) and the
5109 register into the register now, and pretend we were
5110 not using a base register. */
5115 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5117 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5118 ADDRESS_ADD_INSN, "d,v,t", treg, AT, breg);
5124 /* Set mips_optimize around the lui instruction to avoid
5125 inserting an unnecessary nop after the lw. */
5126 hold_mips_optimize = mips_optimize;
5128 macro_build_lui (NULL, &icnt, &expr1, AT);
5129 mips_optimize = hold_mips_optimize;
5131 macro_build ((char *) NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
5132 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
5133 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5134 ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, AT);
5135 frag_var (rs_machine_dependent, 0, 0,
5136 RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0),
5137 offset_expr.X_add_symbol, 0, NULL);
5141 else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI)
5144 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_DISP;
5147 /* If this is a reference to an external, and there is no
5148 constant, or local symbol (*), with or without a
5150 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5151 or if tempreg is PIC_CALL_REG
5152 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5154 If we have a small constant, and this is a reference to
5155 an external symbol, we want
5156 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5157 addiu $tempreg,$tempreg,<constant>
5159 If we have a large constant, and this is a reference to
5160 an external symbol, we want
5161 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5162 lui $at,<hiconstant>
5163 addiu $at,$at,<loconstant>
5164 addu $tempreg,$tempreg,$at
5166 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5167 local symbols, even though it introduces an additional
5171 if (offset_expr.X_add_number == 0 && tempreg == PIC_CALL_REG)
5172 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
5173 if (offset_expr.X_add_number)
5175 frag_now->tc_frag_data.tc_fr_offset =
5176 expr1.X_add_number = offset_expr.X_add_number;
5177 offset_expr.X_add_number = 0;
5179 macro_build ((char *) NULL, &icnt, &offset_expr,
5180 ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5181 lw_reloc_type, mips_gp_register);
5183 if (expr1.X_add_number >= -0x8000
5184 && expr1.X_add_number < 0x8000)
5186 macro_build ((char *) NULL, &icnt, &expr1,
5187 ADDRESS_ADDI_INSN, "t,r,j", tempreg, tempreg,
5188 (int) BFD_RELOC_LO16);
5189 p = frag_var (rs_machine_dependent, 4, 0,
5190 RELAX_ENCODE (8, 4, 0, 0, 0, 0),
5191 offset_expr.X_add_symbol, 0, NULL);
5193 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number))
5197 /* If we are going to add in a base register, and the
5198 target register and the base register are the same,
5199 then we are using AT as a temporary register. Since
5200 we want to load the constant into AT, we add our
5201 current AT (from the global offset table) and the
5202 register into the register now, and pretend we were
5203 not using a base register. */
5208 assert (tempreg == AT);
5209 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5210 ADDRESS_ADD_INSN, "d,v,t", treg, AT, breg);
5215 macro_build_lui ((char *) NULL, &icnt, &expr1, AT);
5216 macro_build ((char *) NULL, &icnt, &expr1,
5217 ADDRESS_ADDI_INSN, "t,r,j", AT, AT,
5218 (int) BFD_RELOC_LO16);
5219 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5220 ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
5222 p = frag_var (rs_machine_dependent, 4 + adj, 0,
5223 RELAX_ENCODE (16 + adj, 4 + adj,
5225 offset_expr.X_add_symbol, 0, NULL);
5230 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5232 offset_expr.X_add_number = expr1.X_add_number;
5234 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5235 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_DISP,
5239 macro_build (p + 4, &icnt, (expressionS *) NULL,
5240 ADDRESS_ADD_INSN, "d,v,t",
5241 treg, tempreg, breg);
5248 macro_build ((char *) NULL, &icnt, &offset_expr,
5249 ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5250 lw_reloc_type, mips_gp_register);
5251 if (lw_reloc_type != BFD_RELOC_MIPS_GOT_DISP)
5252 p = frag_var (rs_machine_dependent, 0, 0,
5253 RELAX_ENCODE (0, 0, -4, 0, 0, 0),
5254 offset_expr.X_add_symbol, 0, NULL);
5259 /* To avoid confusion in tc_gen_reloc, we must ensure
5260 that this does not become a variant frag. */
5261 frag_wane (frag_now);
5265 else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
5269 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5270 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5271 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5273 /* This is the large GOT case. If this is a reference to an
5274 external symbol, and there is no constant, we want
5275 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5276 addu $tempreg,$tempreg,$gp
5277 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5278 or if tempreg is PIC_CALL_REG
5279 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5280 addu $tempreg,$tempreg,$gp
5281 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5282 For a local symbol, we want
5283 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5285 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5287 If we have a small constant, and this is a reference to
5288 an external symbol, we want
5289 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5290 addu $tempreg,$tempreg,$gp
5291 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5293 addiu $tempreg,$tempreg,<constant>
5294 For a local symbol, we want
5295 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5297 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5299 If we have a large constant, and this is a reference to
5300 an external symbol, we want
5301 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5302 addu $tempreg,$tempreg,$gp
5303 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5304 lui $at,<hiconstant>
5305 addiu $at,$at,<loconstant>
5306 addu $tempreg,$tempreg,$at
5307 For a local symbol, we want
5308 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5309 lui $at,<hiconstant>
5310 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5311 addu $tempreg,$tempreg,$at
5314 expr1.X_add_number = offset_expr.X_add_number;
5315 offset_expr.X_add_number = 0;
5317 if (reg_needs_delay (mips_gp_register))
5321 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
5323 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5324 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5326 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
5327 tempreg, lui_reloc_type);
5328 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5329 ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
5331 macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5332 "t,o(b)", tempreg, lw_reloc_type, tempreg);
5333 if (expr1.X_add_number == 0)
5341 /* We're going to put in an addu instruction using
5342 tempreg, so we may as well insert the nop right
5344 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5349 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5350 RELAX_ENCODE (12 + off, 12 + gpdel, gpdel,
5353 ? mips_opts.warn_about_macros
5355 offset_expr.X_add_symbol, 0, NULL);
5357 else if (expr1.X_add_number >= -0x8000
5358 && expr1.X_add_number < 0x8000)
5360 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5362 macro_build ((char *) NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
5363 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5365 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5366 RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0,
5368 ? mips_opts.warn_about_macros
5370 offset_expr.X_add_symbol, 0, NULL);
5376 /* If we are going to add in a base register, and the
5377 target register and the base register are the same,
5378 then we are using AT as a temporary register. Since
5379 we want to load the constant into AT, we add our
5380 current AT (from the global offset table) and the
5381 register into the register now, and pretend we were
5382 not using a base register. */
5390 assert (tempreg == AT);
5391 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5393 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5394 ADDRESS_ADD_INSN, "d,v,t", treg, AT, breg);
5399 /* Set mips_optimize around the lui instruction to avoid
5400 inserting an unnecessary nop after the lw. */
5401 hold_mips_optimize = mips_optimize;
5403 macro_build_lui (NULL, &icnt, &expr1, AT);
5404 mips_optimize = hold_mips_optimize;
5406 macro_build ((char *) NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
5407 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
5408 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5409 ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
5411 p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0,
5412 RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel,
5415 ? mips_opts.warn_about_macros
5417 offset_expr.X_add_symbol, 0, NULL);
5424 /* This is needed because this instruction uses $gp, but
5425 the first instruction on the main stream does not. */
5426 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5430 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5431 tempreg, local_reloc_type, mips_gp_register);
5433 if (expr1.X_add_number >= -0x8000
5434 && expr1.X_add_number < 0x8000)
5436 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5438 macro_build (p, &icnt, &expr1, ADDRESS_ADDI_INSN,
5439 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5440 /* FIXME: If add_number is 0, and there was no base
5441 register, the external symbol case ended with a load,
5442 so if the symbol turns out to not be external, and
5443 the next instruction uses tempreg, an unnecessary nop
5444 will be inserted. */
5450 /* We must add in the base register now, as in the
5451 external symbol case. */
5452 assert (tempreg == AT);
5453 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5455 macro_build (p, &icnt, (expressionS *) NULL,
5456 ADDRESS_ADD_INSN, "d,v,t", treg, AT, breg);
5459 /* We set breg to 0 because we have arranged to add
5460 it in in both cases. */
5464 macro_build_lui (p, &icnt, &expr1, AT);
5466 macro_build (p, &icnt, &expr1, ADDRESS_ADDI_INSN,
5467 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
5469 macro_build (p, &icnt, (expressionS *) NULL, ADDRESS_ADD_INSN,
5470 "d,v,t", tempreg, tempreg, AT);
5474 else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
5477 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5478 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5481 /* This is the large GOT case. If this is a reference to an
5482 external symbol, and there is no constant, we want
5483 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5484 add $tempreg,$tempreg,$gp
5485 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5486 or if tempreg is PIC_CALL_REG
5487 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5488 add $tempreg,$tempreg,$gp
5489 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5491 If we have a small constant, and this is a reference to
5492 an external symbol, we want
5493 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5494 add $tempreg,$tempreg,$gp
5495 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5496 addi $tempreg,$tempreg,<constant>
5498 If we have a large constant, and this is a reference to
5499 an external symbol, we want
5500 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5501 addu $tempreg,$tempreg,$gp
5502 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5503 lui $at,<hiconstant>
5504 addi $at,$at,<loconstant>
5505 add $tempreg,$tempreg,$at
5507 If we have NewABI, and we know it's a local symbol, we want
5508 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5509 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5510 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5514 frag_now->tc_frag_data.tc_fr_offset =
5515 expr1.X_add_number = offset_expr.X_add_number;
5516 offset_expr.X_add_number = 0;
5518 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
5520 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5521 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5523 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
5524 tempreg, lui_reloc_type);
5525 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5526 ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
5528 macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5529 "t,o(b)", tempreg, lw_reloc_type, tempreg);
5531 if (expr1.X_add_number == 0)
5533 p = frag_var (rs_machine_dependent, 8, 0,
5534 RELAX_ENCODE (12, 8, 0, 4, 0,
5535 mips_opts.warn_about_macros),
5536 offset_expr.X_add_symbol, 0, NULL);
5538 else if (expr1.X_add_number >= -0x8000
5539 && expr1.X_add_number < 0x8000)
5541 macro_build ((char *) NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
5542 "t,r,j", tempreg, tempreg,
5543 (int) BFD_RELOC_LO16);
5544 p = frag_var (rs_machine_dependent, 8, 0,
5545 RELAX_ENCODE (16, 8, 0, 4, 0,
5546 mips_opts.warn_about_macros),
5547 offset_expr.X_add_symbol, 0, NULL);
5549 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number))
5553 /* If we are going to add in a base register, and the
5554 target register and the base register are the same,
5555 then we are using AT as a temporary register. Since
5556 we want to load the constant into AT, we add our
5557 current AT (from the global offset table) and the
5558 register into the register now, and pretend we were
5559 not using a base register. */
5564 assert (tempreg == AT);
5565 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5566 ADDRESS_ADD_INSN, "d,v,t", treg, AT, breg);
5571 /* Set mips_optimize around the lui instruction to avoid
5572 inserting an unnecessary nop after the lw. */
5573 macro_build_lui ((char *) NULL, &icnt, &expr1, AT);
5574 macro_build ((char *) NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
5575 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
5576 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5577 ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
5579 p = frag_var (rs_machine_dependent, 8 + adj, 0,
5580 RELAX_ENCODE (24 + adj, 8 + adj,
5583 ? mips_opts.warn_about_macros
5585 offset_expr.X_add_symbol, 0, NULL);
5590 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5592 offset_expr.X_add_number = expr1.X_add_number;
5593 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5594 tempreg, (int) BFD_RELOC_MIPS_GOT_PAGE,
5596 macro_build (p + 4, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5597 tempreg, tempreg, (int) BFD_RELOC_MIPS_GOT_OFST);
5600 macro_build (p + 8, &icnt, (expressionS *) NULL,
5601 ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
5606 else if (mips_pic == EMBEDDED_PIC)
5609 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5611 macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
5612 "t,r,j", tempreg, mips_gp_register,
5613 (int) BFD_RELOC_GPREL16);
5622 if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
5623 s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu";
5625 s = ADDRESS_ADD_INSN;
5627 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s,
5628 "d,v,t", treg, tempreg, breg);
5637 /* The j instruction may not be used in PIC code, since it
5638 requires an absolute address. We convert it to a b
5640 if (mips_pic == NO_PIC)
5641 macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a");
5643 macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p");
5646 /* The jal instructions must be handled as macros because when
5647 generating PIC code they expand to multi-instruction
5648 sequences. Normally they are simple instructions. */
5653 if (mips_pic == NO_PIC
5654 || mips_pic == EMBEDDED_PIC)
5655 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr",
5657 else if (mips_pic == SVR4_PIC)
5659 if (sreg != PIC_CALL_REG)
5660 as_warn (_("MIPS PIC call to register other than $25"));
5662 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr",
5666 if (mips_cprestore_offset < 0)
5667 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5670 if (! mips_frame_reg_valid)
5672 as_warn (_("No .frame pseudo-op used in PIC code"));
5673 /* Quiet this warning. */
5674 mips_frame_reg_valid = 1;
5676 if (! mips_cprestore_valid)
5678 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5679 /* Quiet this warning. */
5680 mips_cprestore_valid = 1;
5682 expr1.X_add_number = mips_cprestore_offset;
5683 macro_build_ldst_constoffset ((char *) NULL, &icnt, &expr1,
5696 if (mips_pic == NO_PIC)
5697 macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a");
5698 else if (mips_pic == SVR4_PIC)
5702 /* If this is a reference to an external symbol, and we are
5703 using a small GOT, we want
5704 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5708 lw $gp,cprestore($sp)
5709 The cprestore value is set using the .cprestore
5710 pseudo-op. If we are using a big GOT, we want
5711 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5713 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5717 lw $gp,cprestore($sp)
5718 If the symbol is not external, we want
5719 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5721 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5724 lw $gp,cprestore($sp)
5726 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5727 sequences above, minus nops, unless the symbol is local,
5728 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5735 macro_build ((char *) NULL, &icnt, &offset_expr,
5736 ADDRESS_LOAD_INSN, "t,o(b)", PIC_CALL_REG,
5737 (int) BFD_RELOC_MIPS_CALL16,
5739 frag_var (rs_machine_dependent, 0, 0,
5740 RELAX_ENCODE (0, 0, -4, 0, 0, 0),
5741 offset_expr.X_add_symbol, 0, NULL);
5746 macro_build ((char *) NULL, &icnt, &offset_expr, "lui",
5747 "t,u", PIC_CALL_REG,
5748 (int) BFD_RELOC_MIPS_CALL_HI16);
5749 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5750 ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
5751 PIC_CALL_REG, mips_gp_register);
5752 macro_build ((char *) NULL, &icnt, &offset_expr,
5753 ADDRESS_LOAD_INSN, "t,o(b)", PIC_CALL_REG,
5754 (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
5755 p = frag_var (rs_machine_dependent, 8, 0,
5756 RELAX_ENCODE (12, 8, 0, 4, 0, 0),
5757 offset_expr.X_add_symbol, 0, NULL);
5758 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5759 "t,o(b)", PIC_CALL_REG,
5760 (int) BFD_RELOC_MIPS_GOT_PAGE,
5762 macro_build (p + 4, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
5763 "t,r,j", PIC_CALL_REG, PIC_CALL_REG,
5764 (int) BFD_RELOC_MIPS_GOT_OFST);
5767 macro_build_jalr (icnt, &offset_expr);
5774 macro_build ((char *) NULL, &icnt, &offset_expr,
5775 ADDRESS_LOAD_INSN, "t,o(b)", PIC_CALL_REG,
5776 (int) BFD_RELOC_MIPS_CALL16, mips_gp_register);
5777 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5779 p = frag_var (rs_machine_dependent, 4, 0,
5780 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5781 offset_expr.X_add_symbol, 0, NULL);
5787 if (reg_needs_delay (mips_gp_register))
5791 macro_build ((char *) NULL, &icnt, &offset_expr, "lui",
5792 "t,u", PIC_CALL_REG,
5793 (int) BFD_RELOC_MIPS_CALL_HI16);
5794 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5795 ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
5796 PIC_CALL_REG, mips_gp_register);
5797 macro_build ((char *) NULL, &icnt, &offset_expr,
5798 ADDRESS_LOAD_INSN, "t,o(b)", PIC_CALL_REG,
5799 (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
5800 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5802 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5803 RELAX_ENCODE (16, 12 + gpdel, gpdel,
5805 offset_expr.X_add_symbol, 0, NULL);
5808 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5811 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5812 "t,o(b)", PIC_CALL_REG,
5813 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
5815 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5818 macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
5819 "t,r,j", PIC_CALL_REG, PIC_CALL_REG,
5820 (int) BFD_RELOC_LO16);
5821 macro_build_jalr (icnt, &offset_expr);
5823 if (mips_cprestore_offset < 0)
5824 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5827 if (! mips_frame_reg_valid)
5829 as_warn (_("No .frame pseudo-op used in PIC code"));
5830 /* Quiet this warning. */
5831 mips_frame_reg_valid = 1;
5833 if (! mips_cprestore_valid)
5835 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5836 /* Quiet this warning. */
5837 mips_cprestore_valid = 1;
5839 if (mips_opts.noreorder)
5840 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5842 expr1.X_add_number = mips_cprestore_offset;
5843 macro_build_ldst_constoffset ((char *) NULL, &icnt, &expr1,
5850 else if (mips_pic == EMBEDDED_PIC)
5852 macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p");
5853 /* The linker may expand the call to a longer sequence which
5854 uses $at, so we must break rather than return. */
5879 /* Itbl support may require additional care here. */
5884 /* Itbl support may require additional care here. */
5889 /* Itbl support may require additional care here. */
5894 /* Itbl support may require additional care here. */
5906 if (mips_opts.arch == CPU_R4650)
5908 as_bad (_("opcode not supported on this processor"));
5912 /* Itbl support may require additional care here. */
5917 /* Itbl support may require additional care here. */
5922 /* Itbl support may require additional care here. */
5942 if (breg == treg || coproc || lr)
5964 /* Itbl support may require additional care here. */
5969 /* Itbl support may require additional care here. */
5974 /* Itbl support may require additional care here. */
5979 /* Itbl support may require additional care here. */
5995 if (mips_opts.arch == CPU_R4650)
5997 as_bad (_("opcode not supported on this processor"));
6002 /* Itbl support may require additional care here. */
6006 /* Itbl support may require additional care here. */
6011 /* Itbl support may require additional care here. */
6023 /* Itbl support may require additional care here. */
6024 if (mask == M_LWC1_AB
6025 || mask == M_SWC1_AB
6026 || mask == M_LDC1_AB
6027 || mask == M_SDC1_AB
6036 /* For embedded PIC, we allow loads where the offset is calculated
6037 by subtracting a symbol in the current segment from an unknown
6038 symbol, relative to a base register, e.g.:
6039 <op> $treg, <sym>-<localsym>($breg)
6040 This is used by the compiler for switch statements. */
6041 if (mips_pic == EMBEDDED_PIC
6042 && offset_expr.X_op == O_subtract
6043 && (symbol_constant_p (offset_expr.X_op_symbol)
6044 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
6045 : (symbol_equated_p (offset_expr.X_op_symbol)
6047 (symbol_get_value_expression (offset_expr.X_op_symbol)
6051 && (offset_expr.X_add_number == 0
6052 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
6054 /* For this case, we output the instructions:
6055 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
6056 addiu $tempreg,$tempreg,$breg
6057 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
6058 If the relocation would fit entirely in 16 bits, it would be
6060 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
6061 instead, but that seems quite difficult. */
6062 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
6063 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
6064 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6065 ((bfd_arch_bits_per_address (stdoutput) == 32
6066 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
6067 ? "addu" : "daddu"),
6068 "d,v,t", tempreg, tempreg, breg);
6069 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, treg,
6070 (int) BFD_RELOC_PCREL_LO16, tempreg);
6076 if (offset_expr.X_op != O_constant
6077 && offset_expr.X_op != O_symbol)
6079 as_bad (_("expression too complex"));
6080 offset_expr.X_op = O_constant;
6083 /* A constant expression in PIC code can be handled just as it
6084 is in non PIC code. */
6085 if (mips_pic == NO_PIC
6086 || offset_expr.X_op == O_constant)
6090 /* If this is a reference to a GP relative symbol, and there
6091 is no base register, we want
6092 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6093 Otherwise, if there is no base register, we want
6094 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6095 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6096 If we have a constant, we need two instructions anyhow,
6097 so we always use the latter form.
6099 If we have a base register, and this is a reference to a
6100 GP relative symbol, we want
6101 addu $tempreg,$breg,$gp
6102 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6104 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6105 addu $tempreg,$tempreg,$breg
6106 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6107 With a constant we always use the latter case.
6109 With 64bit address space and no base register and $at usable,
6111 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6112 lui $at,<sym> (BFD_RELOC_HI16_S)
6113 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6116 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6117 If we have a base register, we want
6118 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6119 lui $at,<sym> (BFD_RELOC_HI16_S)
6120 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6124 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6126 Without $at we can't generate the optimal path for superscalar
6127 processors here since this would require two temporary registers.
6128 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6129 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6131 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6133 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6134 If we have a base register, we want
6135 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6136 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6138 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6140 daddu $tempreg,$tempreg,$breg
6141 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6143 If we have 64-bit addresses, as an optimization, for
6144 addresses which are 32-bit constants (e.g. kseg0/kseg1
6145 addresses) we fall back to the 32-bit address generation
6146 mechanism since it is more efficient. Note that due to
6147 the signed offset used by memory operations, the 32-bit
6148 range is shifted down by 32768 here. This code should
6149 probably attempt to generate 64-bit constants more
6150 efficiently in general.
6152 As an extension for architectures with 64-bit registers,
6153 we don't truncate 64-bit addresses given as literal
6154 constants down to 32 bits, to support existing practice
6155 in the mips64 Linux (the kernel), that compiles source
6156 files with -mabi=64, assembling them as o32 or n32 (with
6157 -Wa,-32 or -Wa,-n32). This is not beautiful, but since
6158 the whole kernel is loaded into a memory region that is
6159 addressible with sign-extended 32-bit addresses, it is
6160 wasteful to compute the upper 32 bits of every
6161 non-literal address, that takes more space and time.
6162 Some day this should probably be implemented as an
6163 assembler option, such that the kernel doesn't have to
6164 use such ugly hacks, even though it will still have to
6165 end up converting the binary to ELF32 for a number of
6166 platforms whose boot loaders don't support ELF64
6168 if ((offset_expr.X_op != O_constant && HAVE_64BIT_ADDRESSES)
6169 || (offset_expr.X_op == O_constant
6170 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)
6171 && HAVE_64BIT_ADDRESS_CONSTANTS))
6175 /* We don't do GP optimization for now because RELAX_ENCODE can't
6176 hold the data for such large chunks. */
6178 if (used_at == 0 && ! mips_opts.noat)
6180 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
6181 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
6182 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
6183 AT, (int) BFD_RELOC_HI16_S);
6184 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
6185 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
6187 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
6188 "d,v,t", AT, AT, breg);
6189 macro_build (p, &icnt, (expressionS *) NULL, "dsll32",
6190 "d,w,<", tempreg, tempreg, 0);
6191 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
6192 "d,v,t", tempreg, tempreg, AT);
6193 macro_build (p, &icnt, &offset_expr, s,
6194 fmt, treg, (int) BFD_RELOC_LO16, tempreg);
6199 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
6200 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
6201 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
6202 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
6203 macro_build (p, &icnt, (expressionS *) NULL, "dsll",
6204 "d,w,<", tempreg, tempreg, 16);
6205 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
6206 tempreg, tempreg, (int) BFD_RELOC_HI16_S);
6207 macro_build (p, &icnt, (expressionS *) NULL, "dsll",
6208 "d,w,<", tempreg, tempreg, 16);
6210 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
6211 "d,v,t", tempreg, tempreg, breg);
6212 macro_build (p, &icnt, &offset_expr, s,
6213 fmt, treg, (int) BFD_RELOC_LO16, tempreg);
6218 else if (offset_expr.X_op == O_constant
6219 && !HAVE_64BIT_ADDRESS_CONSTANTS
6220 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
6221 as_bad (_("load/store address overflow (max 32 bits)"));
6225 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6226 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6231 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6232 treg, (int) BFD_RELOC_GPREL16,
6234 p = frag_var (rs_machine_dependent, 8, 0,
6235 RELAX_ENCODE (4, 8, 0, 4, 0,
6236 (mips_opts.warn_about_macros
6238 && mips_opts.noat))),
6239 offset_expr.X_add_symbol, 0, NULL);
6242 macro_build_lui (p, &icnt, &offset_expr, tempreg);
6245 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
6246 (int) BFD_RELOC_LO16, tempreg);
6250 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6251 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6256 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6257 ADDRESS_ADD_INSN, "d,v,t", tempreg, breg,
6259 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6260 treg, (int) BFD_RELOC_GPREL16, tempreg);
6261 p = frag_var (rs_machine_dependent, 12, 0,
6262 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
6263 offset_expr.X_add_symbol, 0, NULL);
6265 macro_build_lui (p, &icnt, &offset_expr, tempreg);
6268 macro_build (p, &icnt, (expressionS *) NULL, ADDRESS_ADD_INSN,
6269 "d,v,t", tempreg, tempreg, breg);
6272 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
6273 (int) BFD_RELOC_LO16, tempreg);
6276 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6279 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6281 /* If this is a reference to an external symbol, we want
6282 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6284 <op> $treg,0($tempreg)
6286 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6288 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6289 <op> $treg,0($tempreg)
6292 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6293 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6295 If there is a base register, we add it to $tempreg before
6296 the <op>. If there is a constant, we stick it in the
6297 <op> instruction. We don't handle constants larger than
6298 16 bits, because we have no way to load the upper 16 bits
6299 (actually, we could handle them for the subset of cases
6300 in which we are not using $at). */
6301 assert (offset_expr.X_op == O_symbol);
6304 macro_build ((char *) NULL, &icnt, &offset_expr,
6305 ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6306 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6308 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6309 ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
6311 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, treg,
6312 (int) BFD_RELOC_MIPS_GOT_OFST, tempreg);
6319 expr1.X_add_number = offset_expr.X_add_number;
6320 offset_expr.X_add_number = 0;
6321 if (expr1.X_add_number < -0x8000
6322 || expr1.X_add_number >= 0x8000)
6323 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6325 macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
6326 "t,o(b)", tempreg, (int) lw_reloc_type,
6328 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
6329 p = frag_var (rs_machine_dependent, 4, 0,
6330 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
6331 offset_expr.X_add_symbol, 0, NULL);
6332 macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
6333 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
6335 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6336 ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, breg);
6337 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
6338 (int) BFD_RELOC_LO16, tempreg);
6340 else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
6345 /* If this is a reference to an external symbol, we want
6346 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6347 addu $tempreg,$tempreg,$gp
6348 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6349 <op> $treg,0($tempreg)
6351 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6353 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6354 <op> $treg,0($tempreg)
6355 If there is a base register, we add it to $tempreg before
6356 the <op>. If there is a constant, we stick it in the
6357 <op> instruction. We don't handle constants larger than
6358 16 bits, because we have no way to load the upper 16 bits
6359 (actually, we could handle them for the subset of cases
6360 in which we are not using $at). */
6361 assert (offset_expr.X_op == O_symbol);
6362 expr1.X_add_number = offset_expr.X_add_number;
6363 offset_expr.X_add_number = 0;
6364 if (expr1.X_add_number < -0x8000
6365 || expr1.X_add_number >= 0x8000)
6366 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6367 if (reg_needs_delay (mips_gp_register))
6372 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
6373 tempreg, (int) BFD_RELOC_MIPS_GOT_HI16);
6374 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6375 ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
6377 macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
6378 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16,
6380 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
6381 RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0),
6382 offset_expr.X_add_symbol, 0, NULL);
6385 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
6388 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
6389 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16,
6392 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
6394 macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
6395 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
6397 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6398 ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, breg);
6399 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
6400 (int) BFD_RELOC_LO16, tempreg);
6402 else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
6405 int bregsz = breg != 0 ? 4 : 0;
6407 /* If this is a reference to an external symbol, we want
6408 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6409 add $tempreg,$tempreg,$gp
6410 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6411 <op> $treg,<ofst>($tempreg)
6412 Otherwise, for local symbols, we want:
6413 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6414 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6415 assert (offset_expr.X_op == O_symbol);
6416 frag_now->tc_frag_data.tc_fr_offset =
6417 expr1.X_add_number = offset_expr.X_add_number;
6418 offset_expr.X_add_number = 0;
6419 if (expr1.X_add_number < -0x8000
6420 || expr1.X_add_number >= 0x8000)
6421 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6423 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
6424 tempreg, (int) BFD_RELOC_MIPS_GOT_HI16);
6425 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6426 ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
6428 macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
6429 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16,
6432 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6433 ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, breg);
6434 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
6435 (int) BFD_RELOC_LO16, tempreg);
6437 offset_expr.X_add_number = expr1.X_add_number;
6438 p = frag_var (rs_machine_dependent, 12 + bregsz, 0,
6439 RELAX_ENCODE (16 + bregsz, 8 + bregsz,
6440 0, 4 + bregsz, 0, 0),
6441 offset_expr.X_add_symbol, 0, NULL);
6442 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6443 tempreg, (int) BFD_RELOC_MIPS_GOT_PAGE,
6446 macro_build (p + 4, &icnt, (expressionS *) NULL,
6447 ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, breg);
6448 macro_build (p + 4 + bregsz, &icnt, &offset_expr, s, fmt, treg,
6449 (int) BFD_RELOC_MIPS_GOT_OFST, tempreg);
6451 else if (mips_pic == EMBEDDED_PIC)
6453 /* If there is no base register, we want
6454 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6455 If there is a base register, we want
6456 addu $tempreg,$breg,$gp
6457 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6459 assert (offset_expr.X_op == O_symbol);
6462 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6463 treg, (int) BFD_RELOC_GPREL16, mips_gp_register);
6468 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6469 ADDRESS_ADD_INSN, "d,v,t", tempreg, breg,
6471 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6472 treg, (int) BFD_RELOC_GPREL16, tempreg);
6485 load_register (&icnt, treg, &imm_expr, 0);
6489 load_register (&icnt, treg, &imm_expr, 1);
6493 if (imm_expr.X_op == O_constant)
6495 load_register (&icnt, AT, &imm_expr, 0);
6496 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6497 "mtc1", "t,G", AT, treg);
6502 assert (offset_expr.X_op == O_symbol
6503 && strcmp (segment_name (S_GET_SEGMENT
6504 (offset_expr.X_add_symbol)),
6506 && offset_expr.X_add_number == 0);
6507 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
6508 treg, (int) BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6513 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6514 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6515 order 32 bits of the value and the low order 32 bits are either
6516 zero or in OFFSET_EXPR. */
6517 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6519 if (HAVE_64BIT_GPRS)
6520 load_register (&icnt, treg, &imm_expr, 1);
6525 if (target_big_endian)
6537 load_register (&icnt, hreg, &imm_expr, 0);
6540 if (offset_expr.X_op == O_absent)
6541 move_register (&icnt, lreg, 0);
6544 assert (offset_expr.X_op == O_constant);
6545 load_register (&icnt, lreg, &offset_expr, 0);
6552 /* We know that sym is in the .rdata section. First we get the
6553 upper 16 bits of the address. */
6554 if (mips_pic == NO_PIC)
6556 macro_build_lui (NULL, &icnt, &offset_expr, AT);
6558 else if (mips_pic == SVR4_PIC)
6560 macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
6561 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
6564 else if (mips_pic == EMBEDDED_PIC)
6566 /* For embedded PIC we pick up the entire address off $gp in
6567 a single instruction. */
6568 macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
6569 "t,r,j", AT, mips_gp_register,
6570 (int) BFD_RELOC_GPREL16);
6571 offset_expr.X_op = O_constant;
6572 offset_expr.X_add_number = 0;
6577 /* Now we load the register(s). */
6578 if (HAVE_64BIT_GPRS)
6579 macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)",
6580 treg, (int) BFD_RELOC_LO16, AT);
6583 macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)",
6584 treg, (int) BFD_RELOC_LO16, AT);
6587 /* FIXME: How in the world do we deal with the possible
6589 offset_expr.X_add_number += 4;
6590 macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)",
6591 treg + 1, (int) BFD_RELOC_LO16, AT);
6595 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6596 does not become a variant frag. */
6597 frag_wane (frag_now);
6603 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6604 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6605 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6606 the value and the low order 32 bits are either zero or in
6608 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6610 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS);
6611 if (HAVE_64BIT_FPRS)
6613 assert (HAVE_64BIT_GPRS);
6614 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6615 "dmtc1", "t,S", AT, treg);
6619 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6620 "mtc1", "t,G", AT, treg + 1);
6621 if (offset_expr.X_op == O_absent)
6622 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6623 "mtc1", "t,G", 0, treg);
6626 assert (offset_expr.X_op == O_constant);
6627 load_register (&icnt, AT, &offset_expr, 0);
6628 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6629 "mtc1", "t,G", AT, treg);
6635 assert (offset_expr.X_op == O_symbol
6636 && offset_expr.X_add_number == 0);
6637 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
6638 if (strcmp (s, ".lit8") == 0)
6640 if (mips_opts.isa != ISA_MIPS1)
6642 macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
6643 "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL,
6647 breg = mips_gp_register;
6648 r = BFD_RELOC_MIPS_LITERAL;
6653 assert (strcmp (s, RDATA_SECTION_NAME) == 0);
6654 if (mips_pic == SVR4_PIC)
6655 macro_build ((char *) NULL, &icnt, &offset_expr,
6656 ADDRESS_LOAD_INSN, "t,o(b)", AT,
6657 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
6660 /* FIXME: This won't work for a 64 bit address. */
6661 macro_build_lui (NULL, &icnt, &offset_expr, AT);
6664 if (mips_opts.isa != ISA_MIPS1)
6666 macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
6667 "T,o(b)", treg, (int) BFD_RELOC_LO16, AT);
6669 /* To avoid confusion in tc_gen_reloc, we must ensure
6670 that this does not become a variant frag. */
6671 frag_wane (frag_now);
6682 if (mips_opts.arch == CPU_R4650)
6684 as_bad (_("opcode not supported on this processor"));
6687 /* Even on a big endian machine $fn comes before $fn+1. We have
6688 to adjust when loading from memory. */
6691 assert (mips_opts.isa == ISA_MIPS1);
6692 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
6693 target_big_endian ? treg + 1 : treg,
6695 /* FIXME: A possible overflow which I don't know how to deal
6697 offset_expr.X_add_number += 4;
6698 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
6699 target_big_endian ? treg : treg + 1,
6702 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6703 does not become a variant frag. */
6704 frag_wane (frag_now);
6713 * The MIPS assembler seems to check for X_add_number not
6714 * being double aligned and generating:
6717 * addiu at,at,%lo(foo+1)
6720 * But, the resulting address is the same after relocation so why
6721 * generate the extra instruction?
6723 if (mips_opts.arch == CPU_R4650)
6725 as_bad (_("opcode not supported on this processor"));
6728 /* Itbl support may require additional care here. */
6730 if (mips_opts.isa != ISA_MIPS1)
6741 if (mips_opts.arch == CPU_R4650)
6743 as_bad (_("opcode not supported on this processor"));
6747 if (mips_opts.isa != ISA_MIPS1)
6755 /* Itbl support may require additional care here. */
6760 if (HAVE_64BIT_GPRS)
6771 if (HAVE_64BIT_GPRS)
6781 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6782 loads for the case of doing a pair of loads to simulate an 'ld'.
6783 This is not currently done by the compiler, and assembly coders
6784 writing embedded-pic code can cope. */
6786 if (offset_expr.X_op != O_symbol
6787 && offset_expr.X_op != O_constant)
6789 as_bad (_("expression too complex"));
6790 offset_expr.X_op = O_constant;
6793 /* Even on a big endian machine $fn comes before $fn+1. We have
6794 to adjust when loading from memory. We set coproc if we must
6795 load $fn+1 first. */
6796 /* Itbl support may require additional care here. */
6797 if (! target_big_endian)
6800 if (mips_pic == NO_PIC
6801 || offset_expr.X_op == O_constant)
6805 /* If this is a reference to a GP relative symbol, we want
6806 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6807 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6808 If we have a base register, we use this
6810 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6811 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6812 If this is not a GP relative symbol, we want
6813 lui $at,<sym> (BFD_RELOC_HI16_S)
6814 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6815 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6816 If there is a base register, we add it to $at after the
6817 lui instruction. If there is a constant, we always use
6819 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6820 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6832 tempreg = mips_gp_register;
6839 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6840 ADDRESS_ADD_INSN, "d,v,t", AT, breg,
6847 /* Itbl support may require additional care here. */
6848 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6849 coproc ? treg + 1 : treg,
6850 (int) BFD_RELOC_GPREL16, tempreg);
6851 offset_expr.X_add_number += 4;
6853 /* Set mips_optimize to 2 to avoid inserting an
6855 hold_mips_optimize = mips_optimize;
6857 /* Itbl support may require additional care here. */
6858 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6859 coproc ? treg : treg + 1,
6860 (int) BFD_RELOC_GPREL16, tempreg);
6861 mips_optimize = hold_mips_optimize;
6863 p = frag_var (rs_machine_dependent, 12 + off, 0,
6864 RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1,
6865 used_at && mips_opts.noat),
6866 offset_expr.X_add_symbol, 0, NULL);
6868 /* We just generated two relocs. When tc_gen_reloc
6869 handles this case, it will skip the first reloc and
6870 handle the second. The second reloc already has an
6871 extra addend of 4, which we added above. We must
6872 subtract it out, and then subtract another 4 to make
6873 the first reloc come out right. The second reloc
6874 will come out right because we are going to add 4 to
6875 offset_expr when we build its instruction below.
6877 If we have a symbol, then we don't want to include
6878 the offset, because it will wind up being included
6879 when we generate the reloc. */
6881 if (offset_expr.X_op == O_constant)
6882 offset_expr.X_add_number -= 8;
6885 offset_expr.X_add_number = -4;
6886 offset_expr.X_op = O_constant;
6889 macro_build_lui (p, &icnt, &offset_expr, AT);
6894 macro_build (p, &icnt, (expressionS *) NULL, ADDRESS_ADD_INSN,
6895 "d,v,t", AT, breg, AT);
6899 /* Itbl support may require additional care here. */
6900 macro_build (p, &icnt, &offset_expr, s, fmt,
6901 coproc ? treg + 1 : treg,
6902 (int) BFD_RELOC_LO16, AT);
6905 /* FIXME: How do we handle overflow here? */
6906 offset_expr.X_add_number += 4;
6907 /* Itbl support may require additional care here. */
6908 macro_build (p, &icnt, &offset_expr, s, fmt,
6909 coproc ? treg : treg + 1,
6910 (int) BFD_RELOC_LO16, AT);
6912 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6916 /* If this is a reference to an external symbol, we want
6917 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6922 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6924 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6925 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6926 If there is a base register we add it to $at before the
6927 lwc1 instructions. If there is a constant we include it
6928 in the lwc1 instructions. */
6930 expr1.X_add_number = offset_expr.X_add_number;
6931 offset_expr.X_add_number = 0;
6932 if (expr1.X_add_number < -0x8000
6933 || expr1.X_add_number >= 0x8000 - 4)
6934 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6939 frag_grow (24 + off);
6940 macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
6941 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
6943 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
6945 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6946 ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6947 /* Itbl support may require additional care here. */
6948 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6949 coproc ? treg + 1 : treg,
6950 (int) BFD_RELOC_LO16, AT);
6951 expr1.X_add_number += 4;
6953 /* Set mips_optimize to 2 to avoid inserting an undesired
6955 hold_mips_optimize = mips_optimize;
6957 /* Itbl support may require additional care here. */
6958 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6959 coproc ? treg : treg + 1,
6960 (int) BFD_RELOC_LO16, AT);
6961 mips_optimize = hold_mips_optimize;
6963 (void) frag_var (rs_machine_dependent, 0, 0,
6964 RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0),
6965 offset_expr.X_add_symbol, 0, NULL);
6967 else if (mips_pic == SVR4_PIC)
6972 /* If this is a reference to an external symbol, we want
6973 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6975 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6980 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6982 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6983 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6984 If there is a base register we add it to $at before the
6985 lwc1 instructions. If there is a constant we include it
6986 in the lwc1 instructions. */
6988 expr1.X_add_number = offset_expr.X_add_number;
6989 offset_expr.X_add_number = 0;
6990 if (expr1.X_add_number < -0x8000
6991 || expr1.X_add_number >= 0x8000 - 4)
6992 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6993 if (reg_needs_delay (mips_gp_register))
7002 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
7003 AT, (int) BFD_RELOC_MIPS_GOT_HI16);
7004 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7005 ADDRESS_ADD_INSN, "d,v,t", AT, AT, mips_gp_register);
7006 macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
7007 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT);
7008 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7010 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7011 ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7012 /* Itbl support may require additional care here. */
7013 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
7014 coproc ? treg + 1 : treg,
7015 (int) BFD_RELOC_LO16, AT);
7016 expr1.X_add_number += 4;
7018 /* Set mips_optimize to 2 to avoid inserting an undesired
7020 hold_mips_optimize = mips_optimize;
7022 /* Itbl support may require additional care here. */
7023 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
7024 coproc ? treg : treg + 1,
7025 (int) BFD_RELOC_LO16, AT);
7026 mips_optimize = hold_mips_optimize;
7027 expr1.X_add_number -= 4;
7029 p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0,
7030 RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel,
7031 8 + gpdel + off, 1, 0),
7032 offset_expr.X_add_symbol, 0, NULL);
7035 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
7038 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
7039 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
7042 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
7046 macro_build (p, &icnt, (expressionS *) NULL, ADDRESS_ADD_INSN,
7047 "d,v,t", AT, breg, AT);
7050 /* Itbl support may require additional care here. */
7051 macro_build (p, &icnt, &expr1, s, fmt,
7052 coproc ? treg + 1 : treg,
7053 (int) BFD_RELOC_LO16, AT);
7055 expr1.X_add_number += 4;
7057 /* Set mips_optimize to 2 to avoid inserting an undesired
7059 hold_mips_optimize = mips_optimize;
7061 /* Itbl support may require additional care here. */
7062 macro_build (p, &icnt, &expr1, s, fmt,
7063 coproc ? treg : treg + 1,
7064 (int) BFD_RELOC_LO16, AT);
7065 mips_optimize = hold_mips_optimize;
7067 else if (mips_pic == EMBEDDED_PIC)
7069 /* If there is no base register, we use
7070 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
7071 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
7072 If we have a base register, we use
7074 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
7075 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
7079 tempreg = mips_gp_register;
7084 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7085 ADDRESS_ADD_INSN, "d,v,t", AT, breg,
7091 /* Itbl support may require additional care here. */
7092 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
7093 coproc ? treg + 1 : treg,
7094 (int) BFD_RELOC_GPREL16, tempreg);
7095 offset_expr.X_add_number += 4;
7096 /* Itbl support may require additional care here. */
7097 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
7098 coproc ? treg : treg + 1,
7099 (int) BFD_RELOC_GPREL16, tempreg);
7115 assert (HAVE_32BIT_ADDRESSES);
7116 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7117 (int) BFD_RELOC_LO16, breg);
7118 offset_expr.X_add_number += 4;
7119 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1,
7120 (int) BFD_RELOC_LO16, breg);
7123 /* New code added to support COPZ instructions.
7124 This code builds table entries out of the macros in mip_opcodes.
7125 R4000 uses interlocks to handle coproc delays.
7126 Other chips (like the R3000) require nops to be inserted for delays.
7128 FIXME: Currently, we require that the user handle delays.
7129 In order to fill delay slots for non-interlocked chips,
7130 we must have a way to specify delays based on the coprocessor.
7131 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7132 What are the side-effects of the cop instruction?
7133 What cache support might we have and what are its effects?
7134 Both coprocessor & memory require delays. how long???
7135 What registers are read/set/modified?
7137 If an itbl is provided to interpret cop instructions,
7138 this knowledge can be encoded in the itbl spec. */
7152 /* For now we just do C (same as Cz). The parameter will be
7153 stored in insn_opcode by mips_ip. */
7154 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "C",
7159 move_register (&icnt, dreg, sreg);
7162 #ifdef LOSING_COMPILER
7164 /* Try and see if this is a new itbl instruction.
7165 This code builds table entries out of the macros in mip_opcodes.
7166 FIXME: For now we just assemble the expression and pass it's
7167 value along as a 32-bit immediate.
7168 We may want to have the assembler assemble this value,
7169 so that we gain the assembler's knowledge of delay slots,
7171 Would it be more efficient to use mask (id) here? */
7172 if (itbl_have_entries
7173 && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
7175 s = ip->insn_mo->name;
7177 coproc = ITBL_DECODE_PNUM (immed_expr);;
7178 macro_build ((char *) NULL, &icnt, &immed_expr, s, "C");
7185 as_warn (_("Macro used $at after \".set noat\""));
7190 struct mips_cl_insn *ip;
7192 register int treg, sreg, dreg, breg;
7208 bfd_reloc_code_real_type r;
7211 treg = (ip->insn_opcode >> 16) & 0x1f;
7212 dreg = (ip->insn_opcode >> 11) & 0x1f;
7213 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
7214 mask = ip->insn_mo->mask;
7216 expr1.X_op = O_constant;
7217 expr1.X_op_symbol = NULL;
7218 expr1.X_add_symbol = NULL;
7219 expr1.X_add_number = 1;
7223 #endif /* LOSING_COMPILER */
7228 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7229 dbl ? "dmultu" : "multu", "s,t", sreg, treg);
7230 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
7237 /* The MIPS assembler some times generates shifts and adds. I'm
7238 not trying to be that fancy. GCC should do this for us
7240 load_register (&icnt, AT, &imm_expr, dbl);
7241 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7242 dbl ? "dmult" : "mult", "s,t", sreg, AT);
7243 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
7257 mips_emit_delays (TRUE);
7258 ++mips_opts.noreorder;
7259 mips_any_noreorder = 1;
7261 load_register (&icnt, AT, &imm_expr, dbl);
7262 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7263 dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
7264 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
7266 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7267 dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
7268 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d",
7271 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne",
7272 "s,t,q", dreg, AT, 6);
7275 expr1.X_add_number = 8;
7276 macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg,
7278 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
7280 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
7283 --mips_opts.noreorder;
7284 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", dreg);
7297 mips_emit_delays (TRUE);
7298 ++mips_opts.noreorder;
7299 mips_any_noreorder = 1;
7301 load_register (&icnt, AT, &imm_expr, dbl);
7302 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7303 dbl ? "dmultu" : "multu",
7304 "s,t", sreg, imm ? AT : treg);
7305 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d",
7307 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
7310 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne",
7314 expr1.X_add_number = 8;
7315 macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0);
7316 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
7318 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
7321 --mips_opts.noreorder;
7325 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7337 macro_build ((char *) NULL, &icnt, NULL, "dnegu",
7338 "d,w", tempreg, treg);
7339 macro_build ((char *) NULL, &icnt, NULL, "drorv",
7340 "d,t,s", dreg, sreg, tempreg);
7345 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
7346 "d,v,t", AT, 0, treg);
7347 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
7348 "d,t,s", AT, sreg, AT);
7349 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
7350 "d,t,s", dreg, sreg, treg);
7351 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
7352 "d,v,t", dreg, dreg, AT);
7356 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7368 macro_build ((char *) NULL, &icnt, NULL, "negu",
7369 "d,w", tempreg, treg);
7370 macro_build ((char *) NULL, &icnt, NULL, "rorv",
7371 "d,t,s", dreg, sreg, tempreg);
7376 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
7377 "d,v,t", AT, 0, treg);
7378 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv",
7379 "d,t,s", AT, sreg, AT);
7380 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv",
7381 "d,t,s", dreg, sreg, treg);
7382 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
7383 "d,v,t", dreg, dreg, AT);
7391 if (imm_expr.X_op != O_constant)
7392 as_bad (_("Improper rotate count"));
7393 rot = imm_expr.X_add_number & 0x3f;
7394 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7396 rot = (64 - rot) & 0x3f;
7398 macro_build ((char *) NULL, &icnt, NULL, "dror32",
7399 "d,w,<", dreg, sreg, rot - 32);
7401 macro_build ((char *) NULL, &icnt, NULL, "dror",
7402 "d,w,<", dreg, sreg, rot);
7407 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrl",
7408 "d,w,<", dreg, sreg, 0);
7411 l = (rot < 0x20) ? "dsll" : "dsll32";
7412 r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
7414 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
7415 "d,w,<", AT, sreg, rot);
7416 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
7417 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7418 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
7419 "d,v,t", dreg, dreg, AT);
7427 if (imm_expr.X_op != O_constant)
7428 as_bad (_("Improper rotate count"));
7429 rot = imm_expr.X_add_number & 0x1f;
7430 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7432 macro_build ((char *) NULL, &icnt, NULL, "ror",
7433 "d,w,<", dreg, sreg, (32 - rot) & 0x1f);
7438 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
7439 "d,w,<", dreg, sreg, 0);
7442 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
7443 "d,w,<", AT, sreg, rot);
7444 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
7445 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7446 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
7447 "d,v,t", dreg, dreg, AT);
7452 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7454 macro_build ((char *) NULL, &icnt, NULL, "drorv",
7455 "d,t,s", dreg, sreg, treg);
7458 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
7459 "d,v,t", AT, 0, treg);
7460 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
7461 "d,t,s", AT, sreg, AT);
7462 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
7463 "d,t,s", dreg, sreg, treg);
7464 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
7465 "d,v,t", dreg, dreg, AT);
7469 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7471 macro_build ((char *) NULL, &icnt, NULL, "rorv",
7472 "d,t,s", dreg, sreg, treg);
7475 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
7476 "d,v,t", AT, 0, treg);
7477 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv",
7478 "d,t,s", AT, sreg, AT);
7479 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv",
7480 "d,t,s", dreg, sreg, treg);
7481 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
7482 "d,v,t", dreg, dreg, AT);
7490 if (imm_expr.X_op != O_constant)
7491 as_bad (_("Improper rotate count"));
7492 rot = imm_expr.X_add_number & 0x3f;
7493 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7496 macro_build ((char *) NULL, &icnt, NULL, "dror32",
7497 "d,w,<", dreg, sreg, rot - 32);
7499 macro_build ((char *) NULL, &icnt, NULL, "dror",
7500 "d,w,<", dreg, sreg, rot);
7505 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrl",
7506 "d,w,<", dreg, sreg, 0);
7509 r = (rot < 0x20) ? "dsrl" : "dsrl32";
7510 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7512 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
7513 "d,w,<", AT, sreg, rot);
7514 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
7515 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7516 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
7517 "d,v,t", dreg, dreg, AT);
7525 if (imm_expr.X_op != O_constant)
7526 as_bad (_("Improper rotate count"));
7527 rot = imm_expr.X_add_number & 0x1f;
7528 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7530 macro_build ((char *) NULL, &icnt, NULL, "ror",
7531 "d,w,<", dreg, sreg, rot);
7536 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
7537 "d,w,<", dreg, sreg, 0);
7540 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
7541 "d,w,<", AT, sreg, rot);
7542 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
7543 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7544 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
7545 "d,v,t", dreg, dreg, AT);
7550 if (mips_opts.arch == CPU_R4650)
7552 as_bad (_("opcode not supported on this processor"));
7555 assert (mips_opts.isa == ISA_MIPS1);
7556 /* Even on a big endian machine $fn comes before $fn+1. We have
7557 to adjust when storing to memory. */
7558 macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
7559 target_big_endian ? treg + 1 : treg,
7560 (int) BFD_RELOC_LO16, breg);
7561 offset_expr.X_add_number += 4;
7562 macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
7563 target_big_endian ? treg : treg + 1,
7564 (int) BFD_RELOC_LO16, breg);
7569 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
7570 treg, (int) BFD_RELOC_LO16);
7572 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
7573 sreg, (int) BFD_RELOC_LO16);
7576 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
7577 "d,v,t", dreg, sreg, treg);
7578 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
7579 dreg, (int) BFD_RELOC_LO16);
7584 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7586 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
7587 sreg, (int) BFD_RELOC_LO16);
7592 as_warn (_("Instruction %s: result is always false"),
7594 move_register (&icnt, dreg, 0);
7597 if (imm_expr.X_op == O_constant
7598 && imm_expr.X_add_number >= 0
7599 && imm_expr.X_add_number < 0x10000)
7601 macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg,
7602 sreg, (int) BFD_RELOC_LO16);
7605 else if (imm_expr.X_op == O_constant
7606 && imm_expr.X_add_number > -0x8000
7607 && imm_expr.X_add_number < 0)
7609 imm_expr.X_add_number = -imm_expr.X_add_number;
7610 macro_build ((char *) NULL, &icnt, &imm_expr,
7611 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7612 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
7617 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7618 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
7619 "d,v,t", dreg, sreg, AT);
7622 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg,
7623 (int) BFD_RELOC_LO16);
7628 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
7634 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
7636 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7637 (int) BFD_RELOC_LO16);
7640 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
7642 if (imm_expr.X_op == O_constant
7643 && imm_expr.X_add_number >= -0x8000
7644 && imm_expr.X_add_number < 0x8000)
7646 macro_build ((char *) NULL, &icnt, &imm_expr,
7647 mask == M_SGE_I ? "slti" : "sltiu",
7648 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
7653 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7654 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7655 mask == M_SGE_I ? "slt" : "sltu", "d,v,t", dreg, sreg,
7659 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7660 (int) BFD_RELOC_LO16);
7665 case M_SGT: /* sreg > treg <==> treg < sreg */
7671 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
7675 case M_SGT_I: /* sreg > I <==> I < sreg */
7681 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7682 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
7686 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7692 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
7694 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7695 (int) BFD_RELOC_LO16);
7698 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7704 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7705 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
7707 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7708 (int) BFD_RELOC_LO16);
7712 if (imm_expr.X_op == O_constant
7713 && imm_expr.X_add_number >= -0x8000
7714 && imm_expr.X_add_number < 0x8000)
7716 macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j",
7717 dreg, sreg, (int) BFD_RELOC_LO16);
7720 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7721 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
7726 if (imm_expr.X_op == O_constant
7727 && imm_expr.X_add_number >= -0x8000
7728 && imm_expr.X_add_number < 0x8000)
7730 macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j",
7731 dreg, sreg, (int) BFD_RELOC_LO16);
7734 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7735 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
7736 "d,v,t", dreg, sreg, AT);
7741 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
7742 "d,v,t", dreg, 0, treg);
7744 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
7745 "d,v,t", dreg, 0, sreg);
7748 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
7749 "d,v,t", dreg, sreg, treg);
7750 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
7751 "d,v,t", dreg, 0, dreg);
7756 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7758 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
7759 "d,v,t", dreg, 0, sreg);
7764 as_warn (_("Instruction %s: result is always true"),
7766 macro_build ((char *) NULL, &icnt, &expr1,
7767 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7768 "t,r,j", dreg, 0, (int) BFD_RELOC_LO16);
7771 if (imm_expr.X_op == O_constant
7772 && imm_expr.X_add_number >= 0
7773 && imm_expr.X_add_number < 0x10000)
7775 macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i",
7776 dreg, sreg, (int) BFD_RELOC_LO16);
7779 else if (imm_expr.X_op == O_constant
7780 && imm_expr.X_add_number > -0x8000
7781 && imm_expr.X_add_number < 0)
7783 imm_expr.X_add_number = -imm_expr.X_add_number;
7784 macro_build ((char *) NULL, &icnt, &imm_expr,
7785 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7786 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
7791 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7792 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
7793 "d,v,t", dreg, sreg, AT);
7796 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
7797 "d,v,t", dreg, 0, dreg);
7805 if (imm_expr.X_op == O_constant
7806 && imm_expr.X_add_number > -0x8000
7807 && imm_expr.X_add_number <= 0x8000)
7809 imm_expr.X_add_number = -imm_expr.X_add_number;
7810 macro_build ((char *) NULL, &icnt, &imm_expr,
7811 dbl ? "daddi" : "addi",
7812 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
7815 load_register (&icnt, AT, &imm_expr, dbl);
7816 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7817 dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
7823 if (imm_expr.X_op == O_constant
7824 && imm_expr.X_add_number > -0x8000
7825 && imm_expr.X_add_number <= 0x8000)
7827 imm_expr.X_add_number = -imm_expr.X_add_number;
7828 macro_build ((char *) NULL, &icnt, &imm_expr,
7829 dbl ? "daddiu" : "addiu",
7830 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
7833 load_register (&icnt, AT, &imm_expr, dbl);
7834 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7835 dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
7856 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7857 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "s,t", sreg,
7863 assert (mips_opts.isa == ISA_MIPS1);
7864 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
7865 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
7868 * Is the double cfc1 instruction a bug in the mips assembler;
7869 * or is there a reason for it?
7871 mips_emit_delays (TRUE);
7872 ++mips_opts.noreorder;
7873 mips_any_noreorder = 1;
7874 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G",
7876 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G",
7878 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7879 expr1.X_add_number = 3;
7880 macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg,
7881 (int) BFD_RELOC_LO16);
7882 expr1.X_add_number = 2;
7883 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT,
7884 (int) BFD_RELOC_LO16);
7885 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G",
7887 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7888 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7889 mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg);
7890 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G",
7892 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7893 --mips_opts.noreorder;
7902 if (offset_expr.X_add_number >= 0x7fff)
7903 as_bad (_("operand overflow"));
7904 if (! target_big_endian)
7905 ++offset_expr.X_add_number;
7906 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", AT,
7907 (int) BFD_RELOC_LO16, breg);
7908 if (! target_big_endian)
7909 --offset_expr.X_add_number;
7911 ++offset_expr.X_add_number;
7912 macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", treg,
7913 (int) BFD_RELOC_LO16, breg);
7914 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7916 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7930 if (offset_expr.X_add_number >= 0x8000 - off)
7931 as_bad (_("operand overflow"));
7936 if (! target_big_endian)
7937 offset_expr.X_add_number += off;
7938 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", tempreg,
7939 (int) BFD_RELOC_LO16, breg);
7940 if (! target_big_endian)
7941 offset_expr.X_add_number -= off;
7943 offset_expr.X_add_number += off;
7944 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", tempreg,
7945 (int) BFD_RELOC_LO16, breg);
7947 /* If necessary, move the result in tempreg the final destination. */
7948 if (treg == tempreg)
7950 /* Protect second load's delay slot. */
7951 if (!gpr_interlocks)
7952 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7953 move_register (&icnt, treg, tempreg);
7967 load_address (&icnt, AT, &offset_expr, &used_at);
7969 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7970 ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7971 if (! target_big_endian)
7972 expr1.X_add_number = off;
7974 expr1.X_add_number = 0;
7975 macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg,
7976 (int) BFD_RELOC_LO16, AT);
7977 if (! target_big_endian)
7978 expr1.X_add_number = 0;
7980 expr1.X_add_number = off;
7981 macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7982 (int) BFD_RELOC_LO16, AT);
7988 load_address (&icnt, AT, &offset_expr, &used_at);
7990 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7991 ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7992 if (target_big_endian)
7993 expr1.X_add_number = 0;
7994 macro_build ((char *) NULL, &icnt, &expr1,
7995 mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg,
7996 (int) BFD_RELOC_LO16, AT);
7997 if (target_big_endian)
7998 expr1.X_add_number = 1;
8000 expr1.X_add_number = 0;
8001 macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
8002 (int) BFD_RELOC_LO16, AT);
8003 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
8005 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
8010 if (offset_expr.X_add_number >= 0x7fff)
8011 as_bad (_("operand overflow"));
8012 if (target_big_endian)
8013 ++offset_expr.X_add_number;
8014 macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg,
8015 (int) BFD_RELOC_LO16, breg);
8016 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
8018 if (target_big_endian)
8019 --offset_expr.X_add_number;
8021 ++offset_expr.X_add_number;
8022 macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT,
8023 (int) BFD_RELOC_LO16, breg);
8036 if (offset_expr.X_add_number >= 0x8000 - off)
8037 as_bad (_("operand overflow"));
8038 if (! target_big_endian)
8039 offset_expr.X_add_number += off;
8040 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
8041 (int) BFD_RELOC_LO16, breg);
8042 if (! target_big_endian)
8043 offset_expr.X_add_number -= off;
8045 offset_expr.X_add_number += off;
8046 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
8047 (int) BFD_RELOC_LO16, breg);
8061 load_address (&icnt, AT, &offset_expr, &used_at);
8063 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
8064 ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8065 if (! target_big_endian)
8066 expr1.X_add_number = off;
8068 expr1.X_add_number = 0;
8069 macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg,
8070 (int) BFD_RELOC_LO16, AT);
8071 if (! target_big_endian)
8072 expr1.X_add_number = 0;
8074 expr1.X_add_number = off;
8075 macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg,
8076 (int) BFD_RELOC_LO16, AT);
8081 load_address (&icnt, AT, &offset_expr, &used_at);
8083 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
8084 ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8085 if (! target_big_endian)
8086 expr1.X_add_number = 0;
8087 macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
8088 (int) BFD_RELOC_LO16, AT);
8089 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
8091 if (! target_big_endian)
8092 expr1.X_add_number = 1;
8094 expr1.X_add_number = 0;
8095 macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
8096 (int) BFD_RELOC_LO16, AT);
8097 if (! target_big_endian)
8098 expr1.X_add_number = 0;
8100 expr1.X_add_number = 1;
8101 macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
8102 (int) BFD_RELOC_LO16, AT);
8103 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
8105 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
8110 /* FIXME: Check if this is one of the itbl macros, since they
8111 are added dynamically. */
8112 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
8116 as_warn (_("Macro used $at after \".set noat\""));
8119 /* Implement macros in mips16 mode. */
8123 struct mips_cl_insn *ip;
8126 int xreg, yreg, zreg, tmp;
8130 const char *s, *s2, *s3;
8132 mask = ip->insn_mo->mask;
8134 xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
8135 yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY;
8136 zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
8140 expr1.X_op = O_constant;
8141 expr1.X_op_symbol = NULL;
8142 expr1.X_add_symbol = NULL;
8143 expr1.X_add_number = 1;
8162 mips_emit_delays (TRUE);
8163 ++mips_opts.noreorder;
8164 mips_any_noreorder = 1;
8165 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
8166 dbl ? "ddiv" : "div",
8167 "0,x,y", xreg, yreg);
8168 expr1.X_add_number = 2;
8169 macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg);
8170 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", "6",
8173 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
8174 since that causes an overflow. We should do that as well,
8175 but I don't see how to do the comparisons without a temporary
8177 --mips_opts.noreorder;
8178 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x", zreg);
8197 mips_emit_delays (TRUE);
8198 ++mips_opts.noreorder;
8199 mips_any_noreorder = 1;
8200 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "0,x,y",
8202 expr1.X_add_number = 2;
8203 macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg);
8204 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
8206 --mips_opts.noreorder;
8207 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "x", zreg);
8213 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
8214 dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
8215 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "x",
8224 if (imm_expr.X_op != O_constant)
8225 as_bad (_("Unsupported large constant"));
8226 imm_expr.X_add_number = -imm_expr.X_add_number;
8227 macro_build ((char *) NULL, &icnt, &imm_expr,
8228 dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
8232 if (imm_expr.X_op != O_constant)
8233 as_bad (_("Unsupported large constant"));
8234 imm_expr.X_add_number = -imm_expr.X_add_number;
8235 macro_build ((char *) NULL, &icnt, &imm_expr, "addiu",
8240 if (imm_expr.X_op != O_constant)
8241 as_bad (_("Unsupported large constant"));
8242 imm_expr.X_add_number = -imm_expr.X_add_number;
8243 macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu",
8266 goto do_reverse_branch;
8270 goto do_reverse_branch;
8282 goto do_reverse_branch;
8293 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y",
8295 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p");
8322 goto do_addone_branch_i;
8327 goto do_addone_branch_i;
8342 goto do_addone_branch_i;
8349 if (imm_expr.X_op != O_constant)
8350 as_bad (_("Unsupported large constant"));
8351 ++imm_expr.X_add_number;
8354 macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg);
8355 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p");
8359 expr1.X_add_number = 0;
8360 macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg);
8362 move_register (&icnt, xreg, yreg);
8363 expr1.X_add_number = 2;
8364 macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p");
8365 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
8366 "neg", "x,w", xreg, xreg);
8370 /* For consistency checking, verify that all bits are specified either
8371 by the match/mask part of the instruction definition, or by the
8374 validate_mips_insn (opc)
8375 const struct mips_opcode *opc;
8377 const char *p = opc->args;
8379 unsigned long used_bits = opc->mask;
8381 if ((used_bits & opc->match) != opc->match)
8383 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8384 opc->name, opc->args);
8387 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8397 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8398 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8399 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8400 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
8401 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8403 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8404 c, opc->name, opc->args);
8408 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8409 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8411 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
8412 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
8413 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8414 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8416 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8417 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8419 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
8420 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8422 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
8423 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
8424 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
8425 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
8426 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8427 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
8428 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8429 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8430 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8431 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8432 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8433 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8434 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8435 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
8436 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8437 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
8438 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8440 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
8441 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8442 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8443 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
8445 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8446 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8447 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
8448 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8449 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8450 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8451 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8452 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8453 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8456 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
8457 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
8458 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8459 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
8460 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
8464 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8465 c, opc->name, opc->args);
8469 if (used_bits != 0xffffffff)
8471 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8472 ~used_bits & 0xffffffff, opc->name, opc->args);
8478 /* This routine assembles an instruction into its binary format. As a
8479 side effect, it sets one of the global variables imm_reloc or
8480 offset_reloc to the type of relocation to do if one of the operands
8481 is an address expression. */
8486 struct mips_cl_insn *ip;
8491 struct mips_opcode *insn;
8494 unsigned int lastregno = 0;
8495 unsigned int lastpos = 0;
8496 unsigned int limlo, limhi;
8502 /* If the instruction contains a '.', we first try to match an instruction
8503 including the '.'. Then we try again without the '.'. */
8505 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
8508 /* If we stopped on whitespace, then replace the whitespace with null for
8509 the call to hash_find. Save the character we replaced just in case we
8510 have to re-parse the instruction. */
8517 insn = (struct mips_opcode *) hash_find (op_hash, str);
8519 /* If we didn't find the instruction in the opcode table, try again, but
8520 this time with just the instruction up to, but not including the
8524 /* Restore the character we overwrite above (if any). */
8528 /* Scan up to the first '.' or whitespace. */
8530 *s != '\0' && *s != '.' && !ISSPACE (*s);
8534 /* If we did not find a '.', then we can quit now. */
8537 insn_error = "unrecognized opcode";
8541 /* Lookup the instruction in the hash table. */
8543 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
8545 insn_error = "unrecognized opcode";
8555 assert (strcmp (insn->name, str) == 0);
8557 if (OPCODE_IS_MEMBER (insn,
8559 | (file_ase_mips16 ? INSN_MIPS16 : 0)
8560 | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
8561 | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
8567 if (insn->pinfo != INSN_MACRO)
8569 if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)
8575 if (insn + 1 < &mips_opcodes[NUMOPCODES]
8576 && strcmp (insn->name, insn[1].name) == 0)
8585 static char buf[100];
8587 _("opcode not supported on this processor: %s (%s)"),
8588 mips_cpu_info_from_arch (mips_opts.arch)->name,
8589 mips_cpu_info_from_isa (mips_opts.isa)->name);
8599 ip->insn_opcode = insn->match;
8601 for (args = insn->args;; ++args)
8605 s += strspn (s, " \t");
8609 case '\0': /* end of args */
8622 ip->insn_opcode |= lastregno << OP_SH_RS;
8626 ip->insn_opcode |= lastregno << OP_SH_RT;
8630 ip->insn_opcode |= lastregno << OP_SH_FT;
8634 ip->insn_opcode |= lastregno << OP_SH_FS;
8640 /* Handle optional base register.
8641 Either the base register is omitted or
8642 we must have a left paren. */
8643 /* This is dependent on the next operand specifier
8644 is a base register specification. */
8645 assert (args[1] == 'b' || args[1] == '5'
8646 || args[1] == '-' || args[1] == '4');
8650 case ')': /* these must match exactly */
8657 case '+': /* Opcode extension character. */
8660 case 'A': /* ins/ext position, becomes LSB. */
8663 my_getExpression (&imm_expr, s);
8664 check_absolute_expr (ip, &imm_expr);
8665 if ((unsigned long) imm_expr.X_add_number < limlo
8666 || (unsigned long) imm_expr.X_add_number > limhi)
8668 as_bad (_("Improper position (%lu)"),
8669 (unsigned long) imm_expr.X_add_number);
8670 imm_expr.X_add_number = limlo;
8672 lastpos = imm_expr.X_add_number;
8673 ip->insn_opcode |= (imm_expr.X_add_number
8674 & OP_MASK_SHAMT) << OP_SH_SHAMT;
8675 imm_expr.X_op = O_absent;
8679 case 'B': /* ins size, becomes MSB. */
8682 my_getExpression (&imm_expr, s);
8683 check_absolute_expr (ip, &imm_expr);
8684 /* Check for negative input so that small negative numbers
8685 will not succeed incorrectly. The checks against
8686 (pos+size) transitively check "size" itself,
8687 assuming that "pos" is reasonable. */
8688 if ((long) imm_expr.X_add_number < 0
8689 || ((unsigned long) imm_expr.X_add_number
8691 || ((unsigned long) imm_expr.X_add_number
8694 as_bad (_("Improper insert size (%lu, position %lu)"),
8695 (unsigned long) imm_expr.X_add_number,
8696 (unsigned long) lastpos);
8697 imm_expr.X_add_number = limlo - lastpos;
8699 ip->insn_opcode |= ((lastpos + imm_expr.X_add_number - 1)
8700 & OP_MASK_INSMSB) << OP_SH_INSMSB;
8701 imm_expr.X_op = O_absent;
8705 case 'C': /* ext size, becomes MSBD. */
8708 my_getExpression (&imm_expr, s);
8709 check_absolute_expr (ip, &imm_expr);
8710 /* Check for negative input so that small negative numbers
8711 will not succeed incorrectly. The checks against
8712 (pos+size) transitively check "size" itself,
8713 assuming that "pos" is reasonable. */
8714 if ((long) imm_expr.X_add_number < 0
8715 || ((unsigned long) imm_expr.X_add_number
8717 || ((unsigned long) imm_expr.X_add_number
8720 as_bad (_("Improper extract size (%lu, position %lu)"),
8721 (unsigned long) imm_expr.X_add_number,
8722 (unsigned long) lastpos);
8723 imm_expr.X_add_number = limlo - lastpos;
8725 ip->insn_opcode |= ((imm_expr.X_add_number - 1)
8726 & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD;
8727 imm_expr.X_op = O_absent;
8732 /* +D is for disassembly only; never match. */
8736 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8737 *args, insn->name, insn->args);
8738 /* Further processing is fruitless. */
8743 case '<': /* must be at least one digit */
8745 * According to the manual, if the shift amount is greater
8746 * than 31 or less than 0, then the shift amount should be
8747 * mod 32. In reality the mips assembler issues an error.
8748 * We issue a warning and mask out all but the low 5 bits.
8750 my_getExpression (&imm_expr, s);
8751 check_absolute_expr (ip, &imm_expr);
8752 if ((unsigned long) imm_expr.X_add_number > 31)
8754 as_warn (_("Improper shift amount (%lu)"),
8755 (unsigned long) imm_expr.X_add_number);
8756 imm_expr.X_add_number &= OP_MASK_SHAMT;
8758 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT;
8759 imm_expr.X_op = O_absent;
8763 case '>': /* shift amount minus 32 */
8764 my_getExpression (&imm_expr, s);
8765 check_absolute_expr (ip, &imm_expr);
8766 if ((unsigned long) imm_expr.X_add_number < 32
8767 || (unsigned long) imm_expr.X_add_number > 63)
8769 ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT;
8770 imm_expr.X_op = O_absent;
8774 case 'k': /* cache code */
8775 case 'h': /* prefx code */
8776 my_getExpression (&imm_expr, s);
8777 check_absolute_expr (ip, &imm_expr);
8778 if ((unsigned long) imm_expr.X_add_number > 31)
8780 as_warn (_("Invalid value for `%s' (%lu)"),
8782 (unsigned long) imm_expr.X_add_number);
8783 imm_expr.X_add_number &= 0x1f;
8786 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE;
8788 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX;
8789 imm_expr.X_op = O_absent;
8793 case 'c': /* break code */
8794 my_getExpression (&imm_expr, s);
8795 check_absolute_expr (ip, &imm_expr);
8796 if ((unsigned long) imm_expr.X_add_number > 1023)
8798 as_warn (_("Illegal break code (%lu)"),
8799 (unsigned long) imm_expr.X_add_number);
8800 imm_expr.X_add_number &= OP_MASK_CODE;
8802 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE;
8803 imm_expr.X_op = O_absent;
8807 case 'q': /* lower break code */
8808 my_getExpression (&imm_expr, s);
8809 check_absolute_expr (ip, &imm_expr);
8810 if ((unsigned long) imm_expr.X_add_number > 1023)
8812 as_warn (_("Illegal lower break code (%lu)"),
8813 (unsigned long) imm_expr.X_add_number);
8814 imm_expr.X_add_number &= OP_MASK_CODE2;
8816 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2;
8817 imm_expr.X_op = O_absent;
8821 case 'B': /* 20-bit syscall/break code. */
8822 my_getExpression (&imm_expr, s);
8823 check_absolute_expr (ip, &imm_expr);
8824 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
8825 as_warn (_("Illegal 20-bit code (%lu)"),
8826 (unsigned long) imm_expr.X_add_number);
8827 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20;
8828 imm_expr.X_op = O_absent;
8832 case 'C': /* Coprocessor code */
8833 my_getExpression (&imm_expr, s);
8834 check_absolute_expr (ip, &imm_expr);
8835 if ((unsigned long) imm_expr.X_add_number >= (1 << 25))
8837 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8838 (unsigned long) imm_expr.X_add_number);
8839 imm_expr.X_add_number &= ((1 << 25) - 1);
8841 ip->insn_opcode |= imm_expr.X_add_number;
8842 imm_expr.X_op = O_absent;
8846 case 'J': /* 19-bit wait code. */
8847 my_getExpression (&imm_expr, s);
8848 check_absolute_expr (ip, &imm_expr);
8849 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
8850 as_warn (_("Illegal 19-bit code (%lu)"),
8851 (unsigned long) imm_expr.X_add_number);
8852 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19;
8853 imm_expr.X_op = O_absent;
8857 case 'P': /* Performance register */
8858 my_getExpression (&imm_expr, s);
8859 check_absolute_expr (ip, &imm_expr);
8860 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
8862 as_warn (_("Invalid performance register (%lu)"),
8863 (unsigned long) imm_expr.X_add_number);
8864 imm_expr.X_add_number &= OP_MASK_PERFREG;
8866 ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG);
8867 imm_expr.X_op = O_absent;
8871 case 'b': /* base register */
8872 case 'd': /* destination register */
8873 case 's': /* source register */
8874 case 't': /* target register */
8875 case 'r': /* both target and source */
8876 case 'v': /* both dest and source */
8877 case 'w': /* both dest and target */
8878 case 'E': /* coprocessor target register */
8879 case 'G': /* coprocessor destination register */
8880 case 'K': /* 'rdhwr' destination register */
8881 case 'x': /* ignore register name */
8882 case 'z': /* must be zero register */
8883 case 'U': /* destination register (clo/clz). */
8898 while (ISDIGIT (*s));
8900 as_bad (_("Invalid register number (%d)"), regno);
8902 else if (*args == 'E' || *args == 'G' || *args == 'K')
8906 if (s[1] == 'r' && s[2] == 'a')
8911 else if (s[1] == 'f' && s[2] == 'p')
8916 else if (s[1] == 's' && s[2] == 'p')
8921 else if (s[1] == 'g' && s[2] == 'p')
8926 else if (s[1] == 'a' && s[2] == 't')
8931 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
8936 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
8941 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
8946 else if (itbl_have_entries)
8951 p = s + 1; /* advance past '$' */
8952 n = itbl_get_field (&p); /* n is name */
8954 /* See if this is a register defined in an
8956 if (itbl_get_reg_val (n, &r))
8958 /* Get_field advances to the start of
8959 the next field, so we need to back
8960 rack to the end of the last field. */
8964 s = strchr (s, '\0');
8978 as_warn (_("Used $at without \".set noat\""));
8984 if (c == 'r' || c == 'v' || c == 'w')
8991 /* 'z' only matches $0. */
8992 if (c == 'z' && regno != 0)
8995 /* Now that we have assembled one operand, we use the args string
8996 * to figure out where it goes in the instruction. */
9003 ip->insn_opcode |= regno << OP_SH_RS;
9008 ip->insn_opcode |= regno << OP_SH_RD;
9011 ip->insn_opcode |= regno << OP_SH_RD;
9012 ip->insn_opcode |= regno << OP_SH_RT;
9017 ip->insn_opcode |= regno << OP_SH_RT;
9020 /* This case exists because on the r3000 trunc
9021 expands into a macro which requires a gp
9022 register. On the r6000 or r4000 it is
9023 assembled into a single instruction which
9024 ignores the register. Thus the insn version
9025 is MIPS_ISA2 and uses 'x', and the macro
9026 version is MIPS_ISA1 and uses 't'. */
9029 /* This case is for the div instruction, which
9030 acts differently if the destination argument
9031 is $0. This only matches $0, and is checked
9032 outside the switch. */
9035 /* Itbl operand; not yet implemented. FIXME ?? */
9037 /* What about all other operands like 'i', which
9038 can be specified in the opcode table? */
9048 ip->insn_opcode |= lastregno << OP_SH_RS;
9051 ip->insn_opcode |= lastregno << OP_SH_RT;
9056 case 'O': /* MDMX alignment immediate constant. */
9057 my_getExpression (&imm_expr, s);
9058 check_absolute_expr (ip, &imm_expr);
9059 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
9061 as_warn ("Improper align amount (%ld), using low bits",
9062 (long) imm_expr.X_add_number);
9063 imm_expr.X_add_number &= OP_MASK_ALN;
9065 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN;
9066 imm_expr.X_op = O_absent;
9070 case 'Q': /* MDMX vector, element sel, or const. */
9073 /* MDMX Immediate. */
9074 my_getExpression (&imm_expr, s);
9075 check_absolute_expr (ip, &imm_expr);
9076 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
9078 as_warn (_("Invalid MDMX Immediate (%ld)"),
9079 (long) imm_expr.X_add_number);
9080 imm_expr.X_add_number &= OP_MASK_FT;
9082 imm_expr.X_add_number &= OP_MASK_FT;
9083 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
9084 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
9086 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
9087 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT;
9088 imm_expr.X_op = O_absent;
9092 /* Not MDMX Immediate. Fall through. */
9093 case 'X': /* MDMX destination register. */
9094 case 'Y': /* MDMX source register. */
9095 case 'Z': /* MDMX target register. */
9097 case 'D': /* floating point destination register */
9098 case 'S': /* floating point source register */
9099 case 'T': /* floating point target register */
9100 case 'R': /* floating point source register */
9104 /* Accept $fN for FP and MDMX register numbers, and in
9105 addition accept $vN for MDMX register numbers. */
9106 if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2]))
9107 || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v'
9118 while (ISDIGIT (*s));
9121 as_bad (_("Invalid float register number (%d)"), regno);
9123 if ((regno & 1) != 0
9125 && ! (strcmp (str, "mtc1") == 0
9126 || strcmp (str, "mfc1") == 0
9127 || strcmp (str, "lwc1") == 0
9128 || strcmp (str, "swc1") == 0
9129 || strcmp (str, "l.s") == 0
9130 || strcmp (str, "s.s") == 0))
9131 as_warn (_("Float register should be even, was %d"),
9139 if (c == 'V' || c == 'W')
9150 ip->insn_opcode |= regno << OP_SH_FD;
9155 ip->insn_opcode |= regno << OP_SH_FS;
9158 /* This is like 'Z', but also needs to fix the MDMX
9159 vector/scalar select bits. Note that the
9160 scalar immediate case is handled above. */
9163 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
9164 int max_el = (is_qh ? 3 : 7);
9166 my_getExpression(&imm_expr, s);
9167 check_absolute_expr (ip, &imm_expr);
9169 if (imm_expr.X_add_number > max_el)
9170 as_bad(_("Bad element selector %ld"),
9171 (long) imm_expr.X_add_number);
9172 imm_expr.X_add_number &= max_el;
9173 ip->insn_opcode |= (imm_expr.X_add_number
9177 as_warn(_("Expecting ']' found '%s'"), s);
9183 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
9184 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
9187 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
9194 ip->insn_opcode |= regno << OP_SH_FT;
9197 ip->insn_opcode |= regno << OP_SH_FR;
9207 ip->insn_opcode |= lastregno << OP_SH_FS;
9210 ip->insn_opcode |= lastregno << OP_SH_FT;
9216 my_getExpression (&imm_expr, s);
9217 if (imm_expr.X_op != O_big
9218 && imm_expr.X_op != O_constant)
9219 insn_error = _("absolute expression required");
9224 my_getExpression (&offset_expr, s);
9225 *imm_reloc = BFD_RELOC_32;
9238 unsigned char temp[8];
9240 unsigned int length;
9245 /* These only appear as the last operand in an
9246 instruction, and every instruction that accepts
9247 them in any variant accepts them in all variants.
9248 This means we don't have to worry about backing out
9249 any changes if the instruction does not match.
9251 The difference between them is the size of the
9252 floating point constant and where it goes. For 'F'
9253 and 'L' the constant is 64 bits; for 'f' and 'l' it
9254 is 32 bits. Where the constant is placed is based
9255 on how the MIPS assembler does things:
9258 f -- immediate value
9261 The .lit4 and .lit8 sections are only used if
9262 permitted by the -G argument.
9264 When generating embedded PIC code, we use the
9265 .lit8 section but not the .lit4 section (we can do
9266 .lit4 inline easily; we need to put .lit8
9267 somewhere in the data segment, and using .lit8
9268 permits the linker to eventually combine identical
9271 The code below needs to know whether the target register
9272 is 32 or 64 bits wide. It relies on the fact 'f' and
9273 'F' are used with GPR-based instructions and 'l' and
9274 'L' are used with FPR-based instructions. */
9276 f64 = *args == 'F' || *args == 'L';
9277 using_gprs = *args == 'F' || *args == 'f';
9279 save_in = input_line_pointer;
9280 input_line_pointer = s;
9281 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
9283 s = input_line_pointer;
9284 input_line_pointer = save_in;
9285 if (err != NULL && *err != '\0')
9287 as_bad (_("Bad floating point constant: %s"), err);
9288 memset (temp, '\0', sizeof temp);
9289 length = f64 ? 8 : 4;
9292 assert (length == (unsigned) (f64 ? 8 : 4));
9296 && (! USE_GLOBAL_POINTER_OPT
9297 || mips_pic == EMBEDDED_PIC
9298 || g_switch_value < 4
9299 || (temp[0] == 0 && temp[1] == 0)
9300 || (temp[2] == 0 && temp[3] == 0))))
9302 imm_expr.X_op = O_constant;
9303 if (! target_big_endian)
9304 imm_expr.X_add_number = bfd_getl32 (temp);
9306 imm_expr.X_add_number = bfd_getb32 (temp);
9309 && ! mips_disable_float_construction
9310 /* Constants can only be constructed in GPRs and
9311 copied to FPRs if the GPRs are at least as wide
9312 as the FPRs. Force the constant into memory if
9313 we are using 64-bit FPRs but the GPRs are only
9316 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
9317 && ((temp[0] == 0 && temp[1] == 0)
9318 || (temp[2] == 0 && temp[3] == 0))
9319 && ((temp[4] == 0 && temp[5] == 0)
9320 || (temp[6] == 0 && temp[7] == 0)))
9322 /* The value is simple enough to load with a couple of
9323 instructions. If using 32-bit registers, set
9324 imm_expr to the high order 32 bits and offset_expr to
9325 the low order 32 bits. Otherwise, set imm_expr to
9326 the entire 64 bit constant. */
9327 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
9329 imm_expr.X_op = O_constant;
9330 offset_expr.X_op = O_constant;
9331 if (! target_big_endian)
9333 imm_expr.X_add_number = bfd_getl32 (temp + 4);
9334 offset_expr.X_add_number = bfd_getl32 (temp);
9338 imm_expr.X_add_number = bfd_getb32 (temp);
9339 offset_expr.X_add_number = bfd_getb32 (temp + 4);
9341 if (offset_expr.X_add_number == 0)
9342 offset_expr.X_op = O_absent;
9344 else if (sizeof (imm_expr.X_add_number) > 4)
9346 imm_expr.X_op = O_constant;
9347 if (! target_big_endian)
9348 imm_expr.X_add_number = bfd_getl64 (temp);
9350 imm_expr.X_add_number = bfd_getb64 (temp);
9354 imm_expr.X_op = O_big;
9355 imm_expr.X_add_number = 4;
9356 if (! target_big_endian)
9358 generic_bignum[0] = bfd_getl16 (temp);
9359 generic_bignum[1] = bfd_getl16 (temp + 2);
9360 generic_bignum[2] = bfd_getl16 (temp + 4);
9361 generic_bignum[3] = bfd_getl16 (temp + 6);
9365 generic_bignum[0] = bfd_getb16 (temp + 6);
9366 generic_bignum[1] = bfd_getb16 (temp + 4);
9367 generic_bignum[2] = bfd_getb16 (temp + 2);
9368 generic_bignum[3] = bfd_getb16 (temp);
9374 const char *newname;
9377 /* Switch to the right section. */
9379 subseg = now_subseg;
9382 default: /* unused default case avoids warnings. */
9384 newname = RDATA_SECTION_NAME;
9385 if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8)
9386 || mips_pic == EMBEDDED_PIC)
9390 if (mips_pic == EMBEDDED_PIC)
9393 newname = RDATA_SECTION_NAME;
9396 assert (!USE_GLOBAL_POINTER_OPT
9397 || g_switch_value >= 4);
9401 new_seg = subseg_new (newname, (subsegT) 0);
9402 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
9403 bfd_set_section_flags (stdoutput, new_seg,
9408 frag_align (*args == 'l' ? 2 : 3, 0, 0);
9409 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
9410 && strcmp (TARGET_OS, "elf") != 0)
9411 record_alignment (new_seg, 4);
9413 record_alignment (new_seg, *args == 'l' ? 2 : 3);
9415 as_bad (_("Can't use floating point insn in this section"));
9417 /* Set the argument to the current address in the
9419 offset_expr.X_op = O_symbol;
9420 offset_expr.X_add_symbol =
9421 symbol_new ("L0\001", now_seg,
9422 (valueT) frag_now_fix (), frag_now);
9423 offset_expr.X_add_number = 0;
9425 /* Put the floating point number into the section. */
9426 p = frag_more ((int) length);
9427 memcpy (p, temp, length);
9429 /* Switch back to the original section. */
9430 subseg_set (seg, subseg);
9435 case 'i': /* 16 bit unsigned immediate */
9436 case 'j': /* 16 bit signed immediate */
9437 *imm_reloc = BFD_RELOC_LO16;
9438 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
9441 offsetT minval, maxval;
9443 more = (insn + 1 < &mips_opcodes[NUMOPCODES]
9444 && strcmp (insn->name, insn[1].name) == 0);
9446 /* If the expression was written as an unsigned number,
9447 only treat it as signed if there are no more
9451 && sizeof (imm_expr.X_add_number) <= 4
9452 && imm_expr.X_op == O_constant
9453 && imm_expr.X_add_number < 0
9454 && imm_expr.X_unsigned
9458 /* For compatibility with older assemblers, we accept
9459 0x8000-0xffff as signed 16-bit numbers when only
9460 signed numbers are allowed. */
9462 minval = 0, maxval = 0xffff;
9464 minval = -0x8000, maxval = 0x7fff;
9466 minval = -0x8000, maxval = 0xffff;
9468 if (imm_expr.X_op != O_constant
9469 || imm_expr.X_add_number < minval
9470 || imm_expr.X_add_number > maxval)
9474 if (imm_expr.X_op == O_constant
9475 || imm_expr.X_op == O_big)
9476 as_bad (_("expression out of range"));
9482 case 'o': /* 16 bit offset */
9483 /* Check whether there is only a single bracketed expression
9484 left. If so, it must be the base register and the
9485 constant must be zero. */
9486 if (*s == '(' && strchr (s + 1, '(') == 0)
9488 offset_expr.X_op = O_constant;
9489 offset_expr.X_add_number = 0;
9493 /* If this value won't fit into a 16 bit offset, then go
9494 find a macro that will generate the 32 bit offset
9496 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
9497 && (offset_expr.X_op != O_constant
9498 || offset_expr.X_add_number >= 0x8000
9499 || offset_expr.X_add_number < -0x8000))
9505 case 'p': /* pc relative offset */
9506 *offset_reloc = BFD_RELOC_16_PCREL_S2;
9507 my_getExpression (&offset_expr, s);
9511 case 'u': /* upper 16 bits */
9512 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
9513 && imm_expr.X_op == O_constant
9514 && (imm_expr.X_add_number < 0
9515 || imm_expr.X_add_number >= 0x10000))
9516 as_bad (_("lui expression not in range 0..65535"));
9520 case 'a': /* 26 bit address */
9521 my_getExpression (&offset_expr, s);
9523 *offset_reloc = BFD_RELOC_MIPS_JMP;
9526 case 'N': /* 3 bit branch condition code */
9527 case 'M': /* 3 bit compare condition code */
9528 if (strncmp (s, "$fcc", 4) != 0)
9538 while (ISDIGIT (*s));
9540 as_bad (_("invalid condition code register $fcc%d"), regno);
9542 ip->insn_opcode |= regno << OP_SH_BCC;
9544 ip->insn_opcode |= regno << OP_SH_CCC;
9548 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
9559 while (ISDIGIT (*s));
9562 c = 8; /* Invalid sel value. */
9565 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9566 ip->insn_opcode |= c;
9570 /* Must be at least one digit. */
9571 my_getExpression (&imm_expr, s);
9572 check_absolute_expr (ip, &imm_expr);
9574 if ((unsigned long) imm_expr.X_add_number
9575 > (unsigned long) OP_MASK_VECBYTE)
9577 as_bad (_("bad byte vector index (%ld)"),
9578 (long) imm_expr.X_add_number);
9579 imm_expr.X_add_number = 0;
9582 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE;
9583 imm_expr.X_op = O_absent;
9588 my_getExpression (&imm_expr, s);
9589 check_absolute_expr (ip, &imm_expr);
9591 if ((unsigned long) imm_expr.X_add_number
9592 > (unsigned long) OP_MASK_VECALIGN)
9594 as_bad (_("bad byte vector index (%ld)"),
9595 (long) imm_expr.X_add_number);
9596 imm_expr.X_add_number = 0;
9599 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN;
9600 imm_expr.X_op = O_absent;
9605 as_bad (_("bad char = '%c'\n"), *args);
9610 /* Args don't match. */
9611 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
9612 !strcmp (insn->name, insn[1].name))
9616 insn_error = _("illegal operands");
9621 insn_error = _("illegal operands");
9626 /* This routine assembles an instruction into its binary format when
9627 assembling for the mips16. As a side effect, it sets one of the
9628 global variables imm_reloc or offset_reloc to the type of
9629 relocation to do if one of the operands is an address expression.
9630 It also sets mips16_small and mips16_ext if the user explicitly
9631 requested a small or extended instruction. */
9636 struct mips_cl_insn *ip;
9640 struct mips_opcode *insn;
9643 unsigned int lastregno = 0;
9648 mips16_small = FALSE;
9651 for (s = str; ISLOWER (*s); ++s)
9663 if (s[1] == 't' && s[2] == ' ')
9666 mips16_small = TRUE;
9670 else if (s[1] == 'e' && s[2] == ' ')
9679 insn_error = _("unknown opcode");
9683 if (mips_opts.noautoextend && ! mips16_ext)
9684 mips16_small = TRUE;
9686 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
9688 insn_error = _("unrecognized opcode");
9695 assert (strcmp (insn->name, str) == 0);
9698 ip->insn_opcode = insn->match;
9699 ip->use_extend = FALSE;
9700 imm_expr.X_op = O_absent;
9701 imm_reloc[0] = BFD_RELOC_UNUSED;
9702 imm_reloc[1] = BFD_RELOC_UNUSED;
9703 imm_reloc[2] = BFD_RELOC_UNUSED;
9704 offset_expr.X_op = O_absent;
9705 offset_reloc[0] = BFD_RELOC_UNUSED;
9706 offset_reloc[1] = BFD_RELOC_UNUSED;
9707 offset_reloc[2] = BFD_RELOC_UNUSED;
9708 for (args = insn->args; 1; ++args)
9715 /* In this switch statement we call break if we did not find
9716 a match, continue if we did find a match, or return if we
9725 /* Stuff the immediate value in now, if we can. */
9726 if (imm_expr.X_op == O_constant
9727 && *imm_reloc > BFD_RELOC_UNUSED
9728 && insn->pinfo != INSN_MACRO)
9730 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
9731 imm_expr.X_add_number, TRUE, mips16_small,
9732 mips16_ext, &ip->insn_opcode,
9733 &ip->use_extend, &ip->extend);
9734 imm_expr.X_op = O_absent;
9735 *imm_reloc = BFD_RELOC_UNUSED;
9749 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9752 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9768 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9770 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9797 while (ISDIGIT (*s));
9800 as_bad (_("invalid register number (%d)"), regno);
9806 if (s[1] == 'r' && s[2] == 'a')
9811 else if (s[1] == 'f' && s[2] == 'p')
9816 else if (s[1] == 's' && s[2] == 'p')
9821 else if (s[1] == 'g' && s[2] == 'p')
9826 else if (s[1] == 'a' && s[2] == 't')
9831 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
9836 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
9841 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
9854 if (c == 'v' || c == 'w')
9856 regno = mips16_to_32_reg_map[lastregno];
9870 regno = mips32_to_16_reg_map[regno];
9875 regno = ILLEGAL_REG;
9880 regno = ILLEGAL_REG;
9885 regno = ILLEGAL_REG;
9890 if (regno == AT && ! mips_opts.noat)
9891 as_warn (_("used $at without \".set noat\""));
9898 if (regno == ILLEGAL_REG)
9905 ip->insn_opcode |= regno << MIPS16OP_SH_RX;
9909 ip->insn_opcode |= regno << MIPS16OP_SH_RY;
9912 ip->insn_opcode |= regno << MIPS16OP_SH_RZ;
9915 ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z;
9921 ip->insn_opcode |= regno << MIPS16OP_SH_REGR32;
9924 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
9925 ip->insn_opcode |= regno << MIPS16OP_SH_REG32R;
9935 if (strncmp (s, "$pc", 3) == 0)
9959 && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0)
9961 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9962 and generate the appropriate reloc. If the text
9963 inside %gprel is not a symbol name with an
9964 optional offset, then we generate a normal reloc
9965 and will probably fail later. */
9966 my_getExpression (&imm_expr, s + sizeof "%gprel" - 1);
9967 if (imm_expr.X_op == O_symbol)
9970 *imm_reloc = BFD_RELOC_MIPS16_GPREL;
9972 ip->use_extend = TRUE;
9979 /* Just pick up a normal expression. */
9980 my_getExpression (&imm_expr, s);
9983 if (imm_expr.X_op == O_register)
9985 /* What we thought was an expression turned out to
9988 if (s[0] == '(' && args[1] == '(')
9990 /* It looks like the expression was omitted
9991 before a register indirection, which means
9992 that the expression is implicitly zero. We
9993 still set up imm_expr, so that we handle
9994 explicit extensions correctly. */
9995 imm_expr.X_op = O_constant;
9996 imm_expr.X_add_number = 0;
9997 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10004 /* We need to relax this instruction. */
10005 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10014 /* We use offset_reloc rather than imm_reloc for the PC
10015 relative operands. This lets macros with both
10016 immediate and address operands work correctly. */
10017 my_getExpression (&offset_expr, s);
10019 if (offset_expr.X_op == O_register)
10022 /* We need to relax this instruction. */
10023 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
10027 case '6': /* break code */
10028 my_getExpression (&imm_expr, s);
10029 check_absolute_expr (ip, &imm_expr);
10030 if ((unsigned long) imm_expr.X_add_number > 63)
10032 as_warn (_("Invalid value for `%s' (%lu)"),
10034 (unsigned long) imm_expr.X_add_number);
10035 imm_expr.X_add_number &= 0x3f;
10037 ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6;
10038 imm_expr.X_op = O_absent;
10042 case 'a': /* 26 bit address */
10043 my_getExpression (&offset_expr, s);
10045 *offset_reloc = BFD_RELOC_MIPS16_JMP;
10046 ip->insn_opcode <<= 16;
10049 case 'l': /* register list for entry macro */
10050 case 'L': /* register list for exit macro */
10060 int freg, reg1, reg2;
10062 while (*s == ' ' || *s == ',')
10066 as_bad (_("can't parse register list"));
10078 while (ISDIGIT (*s))
10100 as_bad (_("invalid register list"));
10105 while (ISDIGIT (*s))
10112 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
10114 mask &= ~ (7 << 3);
10117 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
10119 mask &= ~ (7 << 3);
10122 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
10123 mask |= (reg2 - 3) << 3;
10124 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
10125 mask |= (reg2 - 15) << 1;
10126 else if (reg1 == RA && reg2 == RA)
10130 as_bad (_("invalid register list"));
10134 /* The mask is filled in in the opcode table for the
10135 benefit of the disassembler. We remove it before
10136 applying the actual mask. */
10137 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
10138 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
10142 case 'e': /* extend code */
10143 my_getExpression (&imm_expr, s);
10144 check_absolute_expr (ip, &imm_expr);
10145 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
10147 as_warn (_("Invalid value for `%s' (%lu)"),
10149 (unsigned long) imm_expr.X_add_number);
10150 imm_expr.X_add_number &= 0x7ff;
10152 ip->insn_opcode |= imm_expr.X_add_number;
10153 imm_expr.X_op = O_absent;
10163 /* Args don't match. */
10164 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
10165 strcmp (insn->name, insn[1].name) == 0)
10172 insn_error = _("illegal operands");
10178 /* This structure holds information we know about a mips16 immediate
10181 struct mips16_immed_operand
10183 /* The type code used in the argument string in the opcode table. */
10185 /* The number of bits in the short form of the opcode. */
10187 /* The number of bits in the extended form of the opcode. */
10189 /* The amount by which the short form is shifted when it is used;
10190 for example, the sw instruction has a shift count of 2. */
10192 /* The amount by which the short form is shifted when it is stored
10193 into the instruction code. */
10195 /* Non-zero if the short form is unsigned. */
10197 /* Non-zero if the extended form is unsigned. */
10199 /* Non-zero if the value is PC relative. */
10203 /* The mips16 immediate operand types. */
10205 static const struct mips16_immed_operand mips16_immed_operands[] =
10207 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
10208 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
10209 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
10210 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
10211 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
10212 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
10213 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
10214 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
10215 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
10216 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
10217 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
10218 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
10219 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
10220 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
10221 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
10222 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
10223 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
10224 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
10225 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
10226 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
10227 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
10230 #define MIPS16_NUM_IMMED \
10231 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
10233 /* Handle a mips16 instruction with an immediate value. This or's the
10234 small immediate value into *INSN. It sets *USE_EXTEND to indicate
10235 whether an extended value is needed; if one is needed, it sets
10236 *EXTEND to the value. The argument type is TYPE. The value is VAL.
10237 If SMALL is true, an unextended opcode was explicitly requested.
10238 If EXT is true, an extended opcode was explicitly requested. If
10239 WARN is true, warn if EXT does not match reality. */
10242 mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend,
10251 unsigned long *insn;
10252 bfd_boolean *use_extend;
10253 unsigned short *extend;
10255 register const struct mips16_immed_operand *op;
10256 int mintiny, maxtiny;
10257 bfd_boolean needext;
10259 op = mips16_immed_operands;
10260 while (op->type != type)
10263 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
10268 if (type == '<' || type == '>' || type == '[' || type == ']')
10271 maxtiny = 1 << op->nbits;
10276 maxtiny = (1 << op->nbits) - 1;
10281 mintiny = - (1 << (op->nbits - 1));
10282 maxtiny = (1 << (op->nbits - 1)) - 1;
10285 /* Branch offsets have an implicit 0 in the lowest bit. */
10286 if (type == 'p' || type == 'q')
10289 if ((val & ((1 << op->shift) - 1)) != 0
10290 || val < (mintiny << op->shift)
10291 || val > (maxtiny << op->shift))
10296 if (warn && ext && ! needext)
10297 as_warn_where (file, line,
10298 _("extended operand requested but not required"));
10299 if (small && needext)
10300 as_bad_where (file, line, _("invalid unextended operand value"));
10302 if (small || (! ext && ! needext))
10306 *use_extend = FALSE;
10307 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
10308 insnval <<= op->op_shift;
10313 long minext, maxext;
10319 maxext = (1 << op->extbits) - 1;
10323 minext = - (1 << (op->extbits - 1));
10324 maxext = (1 << (op->extbits - 1)) - 1;
10326 if (val < minext || val > maxext)
10327 as_bad_where (file, line,
10328 _("operand value out of range for instruction"));
10330 *use_extend = TRUE;
10331 if (op->extbits == 16)
10333 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
10336 else if (op->extbits == 15)
10338 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
10343 extval = ((val & 0x1f) << 6) | (val & 0x20);
10347 *extend = (unsigned short) extval;
10352 static const struct percent_op_match
10355 bfd_reloc_code_real_type reloc;
10358 {"%lo", BFD_RELOC_LO16},
10360 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
10361 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
10362 {"%call16", BFD_RELOC_MIPS_CALL16},
10363 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
10364 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
10365 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
10366 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
10367 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
10368 {"%got", BFD_RELOC_MIPS_GOT16},
10369 {"%gp_rel", BFD_RELOC_GPREL16},
10370 {"%half", BFD_RELOC_16},
10371 {"%highest", BFD_RELOC_MIPS_HIGHEST},
10372 {"%higher", BFD_RELOC_MIPS_HIGHER},
10373 {"%neg", BFD_RELOC_MIPS_SUB},
10375 {"%hi", BFD_RELOC_HI16_S}
10379 /* Return true if *STR points to a relocation operator. When returning true,
10380 move *STR over the operator and store its relocation code in *RELOC.
10381 Leave both *STR and *RELOC alone when returning false. */
10384 parse_relocation (str, reloc)
10386 bfd_reloc_code_real_type *reloc;
10390 for (i = 0; i < ARRAY_SIZE (percent_op); i++)
10391 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
10393 *str += strlen (percent_op[i].str);
10394 *reloc = percent_op[i].reloc;
10396 /* Check whether the output BFD supports this relocation.
10397 If not, issue an error and fall back on something safe. */
10398 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
10400 as_bad ("relocation %s isn't supported by the current ABI",
10401 percent_op[i].str);
10402 *reloc = BFD_RELOC_LO16;
10410 /* Parse string STR as a 16-bit relocatable operand. Store the
10411 expression in *EP and the relocations in the array starting
10412 at RELOC. Return the number of relocation operators used.
10414 On exit, EXPR_END points to the first character after the expression.
10415 If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16. */
10418 my_getSmallExpression (ep, reloc, str)
10420 bfd_reloc_code_real_type *reloc;
10423 bfd_reloc_code_real_type reversed_reloc[3];
10424 size_t reloc_index, i;
10425 int crux_depth, str_depth;
10428 /* Search for the start of the main expression, recoding relocations
10429 in REVERSED_RELOC. End the loop with CRUX pointing to the start
10430 of the main expression and with CRUX_DEPTH containing the number
10431 of open brackets at that point. */
10438 crux_depth = str_depth;
10440 /* Skip over whitespace and brackets, keeping count of the number
10442 while (*str == ' ' || *str == '\t' || *str == '(')
10447 && reloc_index < (HAVE_NEWABI ? 3 : 1)
10448 && parse_relocation (&str, &reversed_reloc[reloc_index]));
10450 my_getExpression (ep, crux);
10453 /* Match every open bracket. */
10454 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
10458 if (crux_depth > 0)
10459 as_bad ("unclosed '('");
10463 if (reloc_index == 0)
10464 reloc[0] = BFD_RELOC_LO16;
10467 prev_reloc_op_frag = frag_now;
10468 for (i = 0; i < reloc_index; i++)
10469 reloc[i] = reversed_reloc[reloc_index - 1 - i];
10472 return reloc_index;
10476 my_getExpression (ep, str)
10483 save_in = input_line_pointer;
10484 input_line_pointer = str;
10486 expr_end = input_line_pointer;
10487 input_line_pointer = save_in;
10489 /* If we are in mips16 mode, and this is an expression based on `.',
10490 then we bump the value of the symbol by 1 since that is how other
10491 text symbols are handled. We don't bother to handle complex
10492 expressions, just `.' plus or minus a constant. */
10493 if (mips_opts.mips16
10494 && ep->X_op == O_symbol
10495 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
10496 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg
10497 && symbol_get_frag (ep->X_add_symbol) == frag_now
10498 && symbol_constant_p (ep->X_add_symbol)
10499 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
10500 S_SET_VALUE (ep->X_add_symbol, val + 1);
10503 /* Turn a string in input_line_pointer into a floating point constant
10504 of type TYPE, and store the appropriate bytes in *LITP. The number
10505 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10506 returned, or NULL on OK. */
10509 md_atof (type, litP, sizeP)
10515 LITTLENUM_TYPE words[4];
10531 return _("bad call to md_atof");
10534 t = atof_ieee (input_line_pointer, type, words);
10536 input_line_pointer = t;
10540 if (! target_big_endian)
10542 for (i = prec - 1; i >= 0; i--)
10544 md_number_to_chars (litP, (valueT) words[i], 2);
10550 for (i = 0; i < prec; i++)
10552 md_number_to_chars (litP, (valueT) words[i], 2);
10561 md_number_to_chars (buf, val, n)
10566 if (target_big_endian)
10567 number_to_chars_bigendian (buf, val, n);
10569 number_to_chars_littleendian (buf, val, n);
10573 static int support_64bit_objects(void)
10575 const char **list, **l;
10578 list = bfd_target_list ();
10579 for (l = list; *l != NULL; l++)
10581 /* This is traditional mips */
10582 if (strcmp (*l, "elf64-tradbigmips") == 0
10583 || strcmp (*l, "elf64-tradlittlemips") == 0)
10585 if (strcmp (*l, "elf64-bigmips") == 0
10586 || strcmp (*l, "elf64-littlemips") == 0)
10589 yes = (*l != NULL);
10593 #endif /* OBJ_ELF */
10595 const char *md_shortopts = "nO::g::G:";
10597 struct option md_longopts[] =
10599 /* Options which specify architecture. */
10600 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10601 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10602 {"march", required_argument, NULL, OPTION_MARCH},
10603 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10604 {"mtune", required_argument, NULL, OPTION_MTUNE},
10605 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10606 {"mips0", no_argument, NULL, OPTION_MIPS1},
10607 {"mips1", no_argument, NULL, OPTION_MIPS1},
10608 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10609 {"mips2", no_argument, NULL, OPTION_MIPS2},
10610 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10611 {"mips3", no_argument, NULL, OPTION_MIPS3},
10612 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10613 {"mips4", no_argument, NULL, OPTION_MIPS4},
10614 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10615 {"mips5", no_argument, NULL, OPTION_MIPS5},
10616 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10617 {"mips32", no_argument, NULL, OPTION_MIPS32},
10618 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10619 {"mips64", no_argument, NULL, OPTION_MIPS64},
10620 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10621 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
10623 /* Options which specify Application Specific Extensions (ASEs). */
10624 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 10)
10625 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10626 {"mips16", no_argument, NULL, OPTION_MIPS16},
10627 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10628 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
10629 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10630 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
10631 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10632 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
10633 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10634 {"mdmx", no_argument, NULL, OPTION_MDMX},
10635 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10636 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
10638 /* Old-style architecture options. Don't add more of these. */
10639 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
10640 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10641 {"m4650", no_argument, NULL, OPTION_M4650},
10642 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10643 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
10644 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10645 {"m4010", no_argument, NULL, OPTION_M4010},
10646 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10647 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
10648 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10649 {"m4100", no_argument, NULL, OPTION_M4100},
10650 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10651 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
10652 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10653 {"m3900", no_argument, NULL, OPTION_M3900},
10654 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10655 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
10657 /* Options which enable bug fixes. */
10658 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10659 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10660 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
10661 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10662 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10663 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10664 #define OPTION_FIX_VR4122 (OPTION_FIX_BASE + 2)
10665 #define OPTION_NO_FIX_VR4122 (OPTION_FIX_BASE + 3)
10666 {"mfix-vr4122-bugs", no_argument, NULL, OPTION_FIX_VR4122},
10667 {"no-mfix-vr4122-bugs", no_argument, NULL, OPTION_NO_FIX_VR4122},
10669 /* Miscellaneous options. */
10670 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
10671 #define OPTION_MEMBEDDED_PIC (OPTION_MISC_BASE + 0)
10672 {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC},
10673 #define OPTION_TRAP (OPTION_MISC_BASE + 1)
10674 {"trap", no_argument, NULL, OPTION_TRAP},
10675 {"no-break", no_argument, NULL, OPTION_TRAP},
10676 #define OPTION_BREAK (OPTION_MISC_BASE + 2)
10677 {"break", no_argument, NULL, OPTION_BREAK},
10678 {"no-trap", no_argument, NULL, OPTION_BREAK},
10679 #define OPTION_EB (OPTION_MISC_BASE + 3)
10680 {"EB", no_argument, NULL, OPTION_EB},
10681 #define OPTION_EL (OPTION_MISC_BASE + 4)
10682 {"EL", no_argument, NULL, OPTION_EL},
10683 #define OPTION_FP32 (OPTION_MISC_BASE + 5)
10684 {"mfp32", no_argument, NULL, OPTION_FP32},
10685 #define OPTION_GP32 (OPTION_MISC_BASE + 6)
10686 {"mgp32", no_argument, NULL, OPTION_GP32},
10687 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10688 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
10689 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 8)
10690 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
10691 #define OPTION_FP64 (OPTION_MISC_BASE + 9)
10692 {"mfp64", no_argument, NULL, OPTION_FP64},
10693 #define OPTION_GP64 (OPTION_MISC_BASE + 10)
10694 {"mgp64", no_argument, NULL, OPTION_GP64},
10695 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10696 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 12)
10697 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
10698 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
10700 /* ELF-specific options. */
10702 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 13)
10703 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10704 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
10705 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
10706 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10707 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
10708 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10709 {"xgot", no_argument, NULL, OPTION_XGOT},
10710 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10711 {"mabi", required_argument, NULL, OPTION_MABI},
10712 #define OPTION_32 (OPTION_ELF_BASE + 4)
10713 {"32", no_argument, NULL, OPTION_32},
10714 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10715 {"n32", no_argument, NULL, OPTION_N32},
10716 #define OPTION_64 (OPTION_ELF_BASE + 6)
10717 {"64", no_argument, NULL, OPTION_64},
10718 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10719 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
10720 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10721 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
10722 #endif /* OBJ_ELF */
10724 {NULL, no_argument, NULL, 0}
10726 size_t md_longopts_size = sizeof (md_longopts);
10728 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10729 NEW_VALUE. Warn if another value was already specified. Note:
10730 we have to defer parsing the -march and -mtune arguments in order
10731 to handle 'from-abi' correctly, since the ABI might be specified
10732 in a later argument. */
10735 mips_set_option_string (string_ptr, new_value)
10736 const char **string_ptr, *new_value;
10738 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
10739 as_warn (_("A different %s was already specified, is now %s"),
10740 string_ptr == &mips_arch_string ? "-march" : "-mtune",
10743 *string_ptr = new_value;
10747 md_parse_option (c, arg)
10753 case OPTION_CONSTRUCT_FLOATS:
10754 mips_disable_float_construction = 0;
10757 case OPTION_NO_CONSTRUCT_FLOATS:
10758 mips_disable_float_construction = 1;
10770 target_big_endian = 1;
10774 target_big_endian = 0;
10782 if (arg && arg[1] == '0')
10792 mips_debug = atoi (arg);
10793 /* When the MIPS assembler sees -g or -g2, it does not do
10794 optimizations which limit full symbolic debugging. We take
10795 that to be equivalent to -O0. */
10796 if (mips_debug == 2)
10801 file_mips_isa = ISA_MIPS1;
10805 file_mips_isa = ISA_MIPS2;
10809 file_mips_isa = ISA_MIPS3;
10813 file_mips_isa = ISA_MIPS4;
10817 file_mips_isa = ISA_MIPS5;
10820 case OPTION_MIPS32:
10821 file_mips_isa = ISA_MIPS32;
10824 case OPTION_MIPS32R2:
10825 file_mips_isa = ISA_MIPS32R2;
10828 case OPTION_MIPS64:
10829 file_mips_isa = ISA_MIPS64;
10833 mips_set_option_string (&mips_tune_string, arg);
10837 mips_set_option_string (&mips_arch_string, arg);
10841 mips_set_option_string (&mips_arch_string, "4650");
10842 mips_set_option_string (&mips_tune_string, "4650");
10845 case OPTION_NO_M4650:
10849 mips_set_option_string (&mips_arch_string, "4010");
10850 mips_set_option_string (&mips_tune_string, "4010");
10853 case OPTION_NO_M4010:
10857 mips_set_option_string (&mips_arch_string, "4100");
10858 mips_set_option_string (&mips_tune_string, "4100");
10861 case OPTION_NO_M4100:
10865 mips_set_option_string (&mips_arch_string, "3900");
10866 mips_set_option_string (&mips_tune_string, "3900");
10869 case OPTION_NO_M3900:
10873 mips_opts.ase_mdmx = 1;
10876 case OPTION_NO_MDMX:
10877 mips_opts.ase_mdmx = 0;
10880 case OPTION_MIPS16:
10881 mips_opts.mips16 = 1;
10882 mips_no_prev_insn (FALSE);
10885 case OPTION_NO_MIPS16:
10886 mips_opts.mips16 = 0;
10887 mips_no_prev_insn (FALSE);
10890 case OPTION_MIPS3D:
10891 mips_opts.ase_mips3d = 1;
10894 case OPTION_NO_MIPS3D:
10895 mips_opts.ase_mips3d = 0;
10898 case OPTION_MEMBEDDED_PIC:
10899 mips_pic = EMBEDDED_PIC;
10900 if (USE_GLOBAL_POINTER_OPT && g_switch_seen)
10902 as_bad (_("-G may not be used with embedded PIC code"));
10905 g_switch_value = 0x7fffffff;
10908 case OPTION_FIX_VR4122:
10909 mips_fix_4122_bugs = 1;
10912 case OPTION_NO_FIX_VR4122:
10913 mips_fix_4122_bugs = 0;
10916 case OPTION_RELAX_BRANCH:
10917 mips_relax_branch = 1;
10920 case OPTION_NO_RELAX_BRANCH:
10921 mips_relax_branch = 0;
10925 /* When generating ELF code, we permit -KPIC and -call_shared to
10926 select SVR4_PIC, and -non_shared to select no PIC. This is
10927 intended to be compatible with Irix 5. */
10928 case OPTION_CALL_SHARED:
10929 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10931 as_bad (_("-call_shared is supported only for ELF format"));
10934 mips_pic = SVR4_PIC;
10935 mips_abicalls = TRUE;
10936 if (g_switch_seen && g_switch_value != 0)
10938 as_bad (_("-G may not be used with SVR4 PIC code"));
10941 g_switch_value = 0;
10944 case OPTION_NON_SHARED:
10945 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10947 as_bad (_("-non_shared is supported only for ELF format"));
10951 mips_abicalls = FALSE;
10954 /* The -xgot option tells the assembler to use 32 offsets when
10955 accessing the got in SVR4_PIC mode. It is for Irix
10960 #endif /* OBJ_ELF */
10963 if (! USE_GLOBAL_POINTER_OPT)
10965 as_bad (_("-G is not supported for this configuration"));
10968 else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC)
10970 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
10974 g_switch_value = atoi (arg);
10979 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10982 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10984 as_bad (_("-32 is supported for ELF format only"));
10987 mips_abi = O32_ABI;
10991 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10993 as_bad (_("-n32 is supported for ELF format only"));
10996 mips_abi = N32_ABI;
11000 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
11002 as_bad (_("-64 is supported for ELF format only"));
11005 mips_abi = N64_ABI;
11006 if (! support_64bit_objects())
11007 as_fatal (_("No compiled in support for 64 bit object file format"));
11009 #endif /* OBJ_ELF */
11012 file_mips_gp32 = 1;
11016 file_mips_gp32 = 0;
11020 file_mips_fp32 = 1;
11024 file_mips_fp32 = 0;
11029 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
11031 as_bad (_("-mabi is supported for ELF format only"));
11034 if (strcmp (arg, "32") == 0)
11035 mips_abi = O32_ABI;
11036 else if (strcmp (arg, "o64") == 0)
11037 mips_abi = O64_ABI;
11038 else if (strcmp (arg, "n32") == 0)
11039 mips_abi = N32_ABI;
11040 else if (strcmp (arg, "64") == 0)
11042 mips_abi = N64_ABI;
11043 if (! support_64bit_objects())
11044 as_fatal (_("No compiled in support for 64 bit object file "
11047 else if (strcmp (arg, "eabi") == 0)
11048 mips_abi = EABI_ABI;
11051 as_fatal (_("invalid abi -mabi=%s"), arg);
11055 #endif /* OBJ_ELF */
11057 case OPTION_M7000_HILO_FIX:
11058 mips_7000_hilo_fix = TRUE;
11061 case OPTION_MNO_7000_HILO_FIX:
11062 mips_7000_hilo_fix = FALSE;
11066 case OPTION_MDEBUG:
11067 mips_flag_mdebug = TRUE;
11070 case OPTION_NO_MDEBUG:
11071 mips_flag_mdebug = FALSE;
11073 #endif /* OBJ_ELF */
11082 /* Set up globals to generate code for the ISA or processor
11083 described by INFO. */
11086 mips_set_architecture (info)
11087 const struct mips_cpu_info *info;
11091 file_mips_arch = info->cpu;
11092 mips_opts.arch = info->cpu;
11093 mips_opts.isa = info->isa;
11098 /* Likewise for tuning. */
11101 mips_set_tune (info)
11102 const struct mips_cpu_info *info;
11105 mips_tune = info->cpu;
11110 mips_after_parse_args ()
11112 const struct mips_cpu_info *arch_info = 0;
11113 const struct mips_cpu_info *tune_info = 0;
11115 /* GP relative stuff not working for PE */
11116 if (strncmp (TARGET_OS, "pe", 2) == 0
11117 && g_switch_value != 0)
11120 as_bad (_("-G not supported in this configuration."));
11121 g_switch_value = 0;
11124 if (mips_abi == NO_ABI)
11125 mips_abi = MIPS_DEFAULT_ABI;
11127 /* The following code determines the architecture and register size.
11128 Similar code was added to GCC 3.3 (see override_options() in
11129 config/mips/mips.c). The GAS and GCC code should be kept in sync
11130 as much as possible. */
11132 if (mips_arch_string != 0)
11133 arch_info = mips_parse_cpu ("-march", mips_arch_string);
11135 if (file_mips_isa != ISA_UNKNOWN)
11137 /* Handle -mipsN. At this point, file_mips_isa contains the
11138 ISA level specified by -mipsN, while arch_info->isa contains
11139 the -march selection (if any). */
11140 if (arch_info != 0)
11142 /* -march takes precedence over -mipsN, since it is more descriptive.
11143 There's no harm in specifying both as long as the ISA levels
11145 if (file_mips_isa != arch_info->isa)
11146 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
11147 mips_cpu_info_from_isa (file_mips_isa)->name,
11148 mips_cpu_info_from_isa (arch_info->isa)->name);
11151 arch_info = mips_cpu_info_from_isa (file_mips_isa);
11154 if (arch_info == 0)
11155 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
11157 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
11158 as_bad ("-march=%s is not compatible with the selected ABI",
11161 mips_set_architecture (arch_info);
11163 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
11164 if (mips_tune_string != 0)
11165 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
11167 if (tune_info == 0)
11168 mips_set_tune (arch_info);
11170 mips_set_tune (tune_info);
11172 if (file_mips_gp32 >= 0)
11174 /* The user specified the size of the integer registers. Make sure
11175 it agrees with the ABI and ISA. */
11176 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
11177 as_bad (_("-mgp64 used with a 32-bit processor"));
11178 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
11179 as_bad (_("-mgp32 used with a 64-bit ABI"));
11180 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
11181 as_bad (_("-mgp64 used with a 32-bit ABI"));
11185 /* Infer the integer register size from the ABI and processor.
11186 Restrict ourselves to 32-bit registers if that's all the
11187 processor has, or if the ABI cannot handle 64-bit registers. */
11188 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
11189 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
11192 /* ??? GAS treats single-float processors as though they had 64-bit
11193 float registers (although it complains when double-precision
11194 instructions are used). As things stand, saying they have 32-bit
11195 registers would lead to spurious "register must be even" messages.
11196 So here we assume float registers are always the same size as
11197 integer ones, unless the user says otherwise. */
11198 if (file_mips_fp32 < 0)
11199 file_mips_fp32 = file_mips_gp32;
11201 /* End of GCC-shared inference code. */
11203 /* ??? When do we want this flag to be set? Who uses it? */
11204 if (file_mips_gp32 == 1
11205 && mips_abi == NO_ABI
11206 && ISA_HAS_64BIT_REGS (mips_opts.isa))
11207 mips_32bitmode = 1;
11209 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
11210 as_bad (_("trap exception not supported at ISA 1"));
11212 /* If the selected architecture includes support for ASEs, enable
11213 generation of code for them. */
11214 if (mips_opts.mips16 == -1)
11215 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
11216 if (mips_opts.ase_mips3d == -1)
11217 mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0;
11218 if (mips_opts.ase_mdmx == -1)
11219 mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0;
11221 file_mips_isa = mips_opts.isa;
11222 file_ase_mips16 = mips_opts.mips16;
11223 file_ase_mips3d = mips_opts.ase_mips3d;
11224 file_ase_mdmx = mips_opts.ase_mdmx;
11225 mips_opts.gp32 = file_mips_gp32;
11226 mips_opts.fp32 = file_mips_fp32;
11228 if (mips_flag_mdebug < 0)
11230 #ifdef OBJ_MAYBE_ECOFF
11231 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
11232 mips_flag_mdebug = 1;
11234 #endif /* OBJ_MAYBE_ECOFF */
11235 mips_flag_mdebug = 0;
11240 mips_init_after_args ()
11242 /* initialize opcodes */
11243 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
11244 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
11248 md_pcrel_from (fixP)
11251 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
11252 switch (fixP->fx_r_type)
11254 case BFD_RELOC_16_PCREL_S2:
11255 case BFD_RELOC_MIPS_JMP:
11256 /* Return the address of the delay slot. */
11263 /* This is called before the symbol table is processed. In order to
11264 work with gcc when using mips-tfile, we must keep all local labels.
11265 However, in other cases, we want to discard them. If we were
11266 called with -g, but we didn't see any debugging information, it may
11267 mean that gcc is smuggling debugging information through to
11268 mips-tfile, in which case we must generate all local labels. */
11271 mips_frob_file_before_adjust ()
11273 #ifndef NO_ECOFF_DEBUGGING
11274 if (ECOFF_DEBUGGING
11276 && ! ecoff_debugging_seen)
11277 flag_keep_locals = 1;
11281 /* Sort any unmatched HI16_S relocs so that they immediately precede
11282 the corresponding LO reloc. This is called before md_apply_fix3 and
11283 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
11284 explicit use of the %hi modifier. */
11289 struct mips_hi_fixup *l;
11291 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
11293 segment_info_type *seginfo;
11296 assert (reloc_needs_lo_p (l->fixp->fx_r_type));
11298 /* If a GOT16 relocation turns out to be against a global symbol,
11299 there isn't supposed to be a matching LO. */
11300 if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
11301 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
11304 /* Check quickly whether the next fixup happens to be a matching %lo. */
11305 if (fixup_has_matching_lo_p (l->fixp))
11308 /* Look through the fixups for this segment for a matching %lo.
11309 When we find one, move the %hi just in front of it. We do
11310 this in two passes. In the first pass, we try to find a
11311 unique %lo. In the second pass, we permit multiple %hi
11312 relocs for a single %lo (this is a GNU extension). */
11313 seginfo = seg_info (l->seg);
11314 for (pass = 0; pass < 2; pass++)
11319 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
11321 /* Check whether this is a %lo fixup which matches l->fixp. */
11322 if (f->fx_r_type == BFD_RELOC_LO16
11323 && f->fx_addsy == l->fixp->fx_addsy
11324 && f->fx_offset == l->fixp->fx_offset
11327 || !reloc_needs_lo_p (prev->fx_r_type)
11328 || !fixup_has_matching_lo_p (prev)))
11332 /* Move l->fixp before f. */
11333 for (pf = &seginfo->fix_root;
11335 pf = &(*pf)->fx_next)
11336 assert (*pf != NULL);
11338 *pf = l->fixp->fx_next;
11340 l->fixp->fx_next = f;
11342 seginfo->fix_root = l->fixp;
11344 prev->fx_next = l->fixp;
11355 #if 0 /* GCC code motion plus incomplete dead code elimination
11356 can leave a %hi without a %lo. */
11358 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
11359 _("Unmatched %%hi reloc"));
11365 /* When generating embedded PIC code we need to use a special
11366 relocation to represent the difference of two symbols in the .text
11367 section (switch tables use a difference of this sort). See
11368 include/coff/mips.h for details. This macro checks whether this
11369 fixup requires the special reloc. */
11370 #define SWITCH_TABLE(fixp) \
11371 ((fixp)->fx_r_type == BFD_RELOC_32 \
11372 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
11373 && (fixp)->fx_addsy != NULL \
11374 && (fixp)->fx_subsy != NULL \
11375 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
11376 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
11378 /* When generating embedded PIC code we must keep all PC relative
11379 relocations, in case the linker has to relax a call. We also need
11380 to keep relocations for switch table entries.
11382 We may have combined relocations without symbols in the N32/N64 ABI.
11383 We have to prevent gas from dropping them. */
11386 mips_force_relocation (fixp)
11389 if (generic_force_reloc (fixp))
11393 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
11394 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
11395 || fixp->fx_r_type == BFD_RELOC_HI16_S
11396 || fixp->fx_r_type == BFD_RELOC_LO16))
11399 return (mips_pic == EMBEDDED_PIC
11401 || SWITCH_TABLE (fixp)
11402 || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S
11403 || fixp->fx_r_type == BFD_RELOC_PCREL_LO16));
11406 /* This hook is called before a fix is simplified. We don't really
11407 decide whether to skip a fix here. Rather, we turn global symbols
11408 used as branch targets into local symbols, such that they undergo
11409 simplification. We can only do this if the symbol is defined and
11410 it is in the same section as the branch. If this doesn't hold, we
11411 emit a better error message than just saying the relocation is not
11412 valid for the selected object format.
11414 FIXP is the fix-up we're going to try to simplify, SEG is the
11415 segment in which the fix up occurs. The return value should be
11416 non-zero to indicate the fix-up is valid for further
11417 simplifications. */
11420 mips_validate_fix (fixP, seg)
11424 /* There's a lot of discussion on whether it should be possible to
11425 use R_MIPS_PC16 to represent branch relocations. The outcome
11426 seems to be that it can, but gas/bfd are very broken in creating
11427 RELA relocations for this, so for now we only accept branches to
11428 symbols in the same section. Anything else is of dubious value,
11429 since there's no guarantee that at link time the symbol would be
11430 in range. Even for branches to local symbols this is arguably
11431 wrong, since it we assume the symbol is not going to be
11432 overridden, which should be possible per ELF library semantics,
11433 but then, there isn't a dynamic relocation that could be used to
11434 this effect, and the target would likely be out of range as well.
11436 Unfortunately, it seems that there is too much code out there
11437 that relies on branches to symbols that are global to be resolved
11438 as if they were local, like the IRIX tools do, so we do it as
11439 well, but with a warning so that people are reminded to fix their
11440 code. If we ever get back to using R_MIPS_PC16 for branch
11441 targets, this entire block should go away (and probably the
11442 whole function). */
11444 if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
11445 && (((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
11446 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
11447 && mips_pic != EMBEDDED_PIC)
11448 || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL)
11451 if (! S_IS_DEFINED (fixP->fx_addsy))
11453 as_bad_where (fixP->fx_file, fixP->fx_line,
11454 _("Cannot branch to undefined symbol."));
11455 /* Avoid any further errors about this fixup. */
11458 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
11460 as_bad_where (fixP->fx_file, fixP->fx_line,
11461 _("Cannot branch to symbol in another section."));
11464 else if (S_IS_EXTERNAL (fixP->fx_addsy))
11466 symbolS *sym = fixP->fx_addsy;
11468 as_warn_where (fixP->fx_file, fixP->fx_line,
11469 _("Pretending global symbol used as branch target is local."));
11471 fixP->fx_addsy = symbol_create (S_GET_NAME (sym),
11472 S_GET_SEGMENT (sym),
11474 symbol_get_frag (sym));
11475 copy_symbol_attributes (fixP->fx_addsy, sym);
11476 S_CLEAR_EXTERNAL (fixP->fx_addsy);
11477 assert (symbol_resolved_p (sym));
11478 symbol_mark_resolved (fixP->fx_addsy);
11487 mips_need_elf_addend_fixup (fixP)
11490 if (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16)
11492 if (mips_pic == EMBEDDED_PIC
11493 && S_IS_WEAK (fixP->fx_addsy))
11495 if (mips_pic != EMBEDDED_PIC
11496 && (S_IS_WEAK (fixP->fx_addsy)
11497 || S_IS_EXTERNAL (fixP->fx_addsy))
11498 && !S_IS_COMMON (fixP->fx_addsy))
11500 if (((bfd_get_section_flags (stdoutput,
11501 S_GET_SEGMENT (fixP->fx_addsy))
11502 & (SEC_LINK_ONCE | SEC_MERGE)) != 0)
11503 || !strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)),
11505 sizeof (".gnu.linkonce") - 1))
11511 /* Apply a fixup to the object file. */
11514 md_apply_fix3 (fixP, valP, seg)
11517 segT seg ATTRIBUTE_UNUSED;
11521 static int previous_fx_r_type = 0;
11522 reloc_howto_type *howto;
11524 /* We ignore generic BFD relocations we don't know about. */
11525 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
11529 assert (fixP->fx_size == 4
11530 || fixP->fx_r_type == BFD_RELOC_16
11531 || fixP->fx_r_type == BFD_RELOC_64
11532 || fixP->fx_r_type == BFD_RELOC_CTOR
11533 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
11534 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
11535 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY);
11537 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
11539 /* If we aren't adjusting this fixup to be against the section
11540 symbol, we need to adjust the value. */
11542 if (fixP->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour)
11544 if (mips_need_elf_addend_fixup (fixP)
11545 && howto->partial_inplace
11546 && fixP->fx_r_type != BFD_RELOC_GPREL16
11547 && fixP->fx_r_type != BFD_RELOC_GPREL32
11548 && fixP->fx_r_type != BFD_RELOC_MIPS16_GPREL)
11550 /* In this case, the bfd_install_relocation routine will
11551 incorrectly add the symbol value back in. We just want
11552 the addend to appear in the object file.
11554 The condition above used to include
11555 "&& (! fixP->fx_pcrel || howto->pcrel_offset)".
11557 However, howto can't be trusted here, because we
11558 might change the reloc type in tc_gen_reloc. We can
11559 check howto->partial_inplace because that conversion
11560 happens to preserve howto->partial_inplace; but it
11561 does not preserve howto->pcrel_offset. I've just
11562 eliminated the check, because all MIPS PC-relative
11563 relocations are marked howto->pcrel_offset.
11565 howto->pcrel_offset was originally added for
11566 R_MIPS_PC16, which is generated for code like
11575 *valP -= S_GET_VALUE (fixP->fx_addsy);
11578 /* This code was generated using trial and error and so is
11579 fragile and not trustworthy. If you change it, you should
11580 rerun the elf-rel, elf-rel2, and empic testcases and ensure
11581 they still pass. */
11582 if (fixP->fx_pcrel)
11584 *valP += fixP->fx_frag->fr_address + fixP->fx_where;
11586 /* BFD's REL handling, for MIPS, is _very_ weird.
11587 This gives the right results, but it can't possibly
11588 be the way things are supposed to work. */
11589 *valP += fixP->fx_frag->fr_address + fixP->fx_where;
11594 /* We are not done if this is a composite relocation to set up gp. */
11595 if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel
11596 && !(fixP->fx_r_type == BFD_RELOC_MIPS_SUB
11597 || (fixP->fx_r_type == BFD_RELOC_64
11598 && (previous_fx_r_type == BFD_RELOC_GPREL32
11599 || previous_fx_r_type == BFD_RELOC_GPREL16))
11600 || (previous_fx_r_type == BFD_RELOC_MIPS_SUB
11601 && (fixP->fx_r_type == BFD_RELOC_HI16_S
11602 || fixP->fx_r_type == BFD_RELOC_LO16))))
11604 previous_fx_r_type = fixP->fx_r_type;
11606 switch (fixP->fx_r_type)
11608 case BFD_RELOC_MIPS_JMP:
11609 case BFD_RELOC_MIPS_SHIFT5:
11610 case BFD_RELOC_MIPS_SHIFT6:
11611 case BFD_RELOC_MIPS_GOT_DISP:
11612 case BFD_RELOC_MIPS_GOT_PAGE:
11613 case BFD_RELOC_MIPS_GOT_OFST:
11614 case BFD_RELOC_MIPS_SUB:
11615 case BFD_RELOC_MIPS_INSERT_A:
11616 case BFD_RELOC_MIPS_INSERT_B:
11617 case BFD_RELOC_MIPS_DELETE:
11618 case BFD_RELOC_MIPS_HIGHEST:
11619 case BFD_RELOC_MIPS_HIGHER:
11620 case BFD_RELOC_MIPS_SCN_DISP:
11621 case BFD_RELOC_MIPS_REL16:
11622 case BFD_RELOC_MIPS_RELGOT:
11623 case BFD_RELOC_MIPS_JALR:
11624 case BFD_RELOC_HI16:
11625 case BFD_RELOC_HI16_S:
11626 case BFD_RELOC_GPREL16:
11627 case BFD_RELOC_MIPS_LITERAL:
11628 case BFD_RELOC_MIPS_CALL16:
11629 case BFD_RELOC_MIPS_GOT16:
11630 case BFD_RELOC_GPREL32:
11631 case BFD_RELOC_MIPS_GOT_HI16:
11632 case BFD_RELOC_MIPS_GOT_LO16:
11633 case BFD_RELOC_MIPS_CALL_HI16:
11634 case BFD_RELOC_MIPS_CALL_LO16:
11635 case BFD_RELOC_MIPS16_GPREL:
11636 if (fixP->fx_pcrel)
11637 as_bad_where (fixP->fx_file, fixP->fx_line,
11638 _("Invalid PC relative reloc"));
11639 /* Nothing needed to do. The value comes from the reloc entry */
11642 case BFD_RELOC_MIPS16_JMP:
11643 /* We currently always generate a reloc against a symbol, which
11644 means that we don't want an addend even if the symbol is
11649 case BFD_RELOC_PCREL_HI16_S:
11650 /* The addend for this is tricky if it is internal, so we just
11651 do everything here rather than in bfd_install_relocation. */
11652 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done)
11655 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
11657 /* For an external symbol adjust by the address to make it
11658 pcrel_offset. We use the address of the RELLO reloc
11659 which follows this one. */
11660 *valP += (fixP->fx_next->fx_frag->fr_address
11661 + fixP->fx_next->fx_where);
11663 *valP = ((*valP + 0x8000) >> 16) & 0xffff;
11664 if (target_big_endian)
11666 md_number_to_chars ((char *) buf, *valP, 2);
11669 case BFD_RELOC_PCREL_LO16:
11670 /* The addend for this is tricky if it is internal, so we just
11671 do everything here rather than in bfd_install_relocation. */
11672 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done)
11675 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
11676 *valP += fixP->fx_frag->fr_address + fixP->fx_where;
11677 if (target_big_endian)
11679 md_number_to_chars ((char *) buf, *valP, 2);
11683 /* This is handled like BFD_RELOC_32, but we output a sign
11684 extended value if we are only 32 bits. */
11686 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
11688 if (8 <= sizeof (valueT))
11689 md_number_to_chars (buf, *valP, 8);
11694 if ((*valP & 0x80000000) != 0)
11698 md_number_to_chars ((char *)(buf + target_big_endian ? 4 : 0),
11700 md_number_to_chars ((char *)(buf + target_big_endian ? 0 : 4),
11706 case BFD_RELOC_RVA:
11708 /* If we are deleting this reloc entry, we must fill in the
11709 value now. This can happen if we have a .word which is not
11710 resolved when it appears but is later defined. We also need
11711 to fill in the value if this is an embedded PIC switch table
11714 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
11715 md_number_to_chars (buf, *valP, 4);
11719 /* If we are deleting this reloc entry, we must fill in the
11721 assert (fixP->fx_size == 2);
11723 md_number_to_chars (buf, *valP, 2);
11726 case BFD_RELOC_LO16:
11727 /* When handling an embedded PIC switch statement, we can wind
11728 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11731 if (*valP + 0x8000 > 0xffff)
11732 as_bad_where (fixP->fx_file, fixP->fx_line,
11733 _("relocation overflow"));
11734 if (target_big_endian)
11736 md_number_to_chars ((char *) buf, *valP, 2);
11740 case BFD_RELOC_16_PCREL_S2:
11741 if ((*valP & 0x3) != 0)
11742 as_bad_where (fixP->fx_file, fixP->fx_line,
11743 _("Branch to odd address (%lx)"), (long) *valP);
11746 * We need to save the bits in the instruction since fixup_segment()
11747 * might be deleting the relocation entry (i.e., a branch within
11748 * the current segment).
11750 if (! fixP->fx_done)
11753 /* update old instruction data */
11754 if (target_big_endian)
11755 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
11757 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
11759 if (*valP + 0x20000 <= 0x3ffff)
11761 insn |= (*valP >> 2) & 0xffff;
11762 md_number_to_chars ((char *) buf, (valueT) insn, 4);
11764 else if (mips_pic == NO_PIC
11766 && fixP->fx_frag->fr_address >= text_section->vma
11767 && (fixP->fx_frag->fr_address
11768 < text_section->vma + text_section->_raw_size)
11769 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
11770 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
11771 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
11773 /* The branch offset is too large. If this is an
11774 unconditional branch, and we are not generating PIC code,
11775 we can convert it to an absolute jump instruction. */
11776 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
11777 insn = 0x0c000000; /* jal */
11779 insn = 0x08000000; /* j */
11780 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
11782 fixP->fx_addsy = section_symbol (text_section);
11783 *valP += md_pcrel_from (fixP);
11784 md_number_to_chars ((char *) buf, (valueT) insn, 4);
11788 /* If we got here, we have branch-relaxation disabled,
11789 and there's nothing we can do to fix this instruction
11790 without turning it into a longer sequence. */
11791 as_bad_where (fixP->fx_file, fixP->fx_line,
11792 _("Branch out of range"));
11796 case BFD_RELOC_VTABLE_INHERIT:
11799 && !S_IS_DEFINED (fixP->fx_addsy)
11800 && !S_IS_WEAK (fixP->fx_addsy))
11801 S_SET_WEAK (fixP->fx_addsy);
11804 case BFD_RELOC_VTABLE_ENTRY:
11812 /* Remember value for tc_gen_reloc. */
11813 fixP->fx_addnumber = *valP;
11821 const struct mips_opcode *p;
11822 int treg, sreg, dreg, shamt;
11827 for (i = 0; i < NUMOPCODES; ++i)
11829 p = &mips_opcodes[i];
11830 if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO))
11832 printf ("%08lx %s\t", oc, p->name);
11833 treg = (oc >> 16) & 0x1f;
11834 sreg = (oc >> 21) & 0x1f;
11835 dreg = (oc >> 11) & 0x1f;
11836 shamt = (oc >> 6) & 0x1f;
11838 for (args = p->args;; ++args)
11849 printf ("%c", *args);
11853 assert (treg == sreg);
11854 printf ("$%d,$%d", treg, sreg);
11859 printf ("$%d", dreg);
11864 printf ("$%d", treg);
11868 printf ("0x%x", treg);
11873 printf ("$%d", sreg);
11877 printf ("0x%08lx", oc & 0x1ffffff);
11884 printf ("%d", imm);
11889 printf ("$%d", shamt);
11900 printf (_("%08lx UNDEFINED\n"), oc);
11911 name = input_line_pointer;
11912 c = get_symbol_end ();
11913 p = (symbolS *) symbol_find_or_make (name);
11914 *input_line_pointer = c;
11918 /* Align the current frag to a given power of two. The MIPS assembler
11919 also automatically adjusts any preceding label. */
11922 mips_align (to, fill, label)
11927 mips_emit_delays (FALSE);
11928 frag_align (to, fill, 0);
11929 record_alignment (now_seg, to);
11932 assert (S_GET_SEGMENT (label) == now_seg);
11933 symbol_set_frag (label, frag_now);
11934 S_SET_VALUE (label, (valueT) frag_now_fix ());
11938 /* Align to a given power of two. .align 0 turns off the automatic
11939 alignment used by the data creating pseudo-ops. */
11943 int x ATTRIBUTE_UNUSED;
11946 register long temp_fill;
11947 long max_alignment = 15;
11951 o Note that the assembler pulls down any immediately preceeding label
11952 to the aligned address.
11953 o It's not documented but auto alignment is reinstated by
11954 a .align pseudo instruction.
11955 o Note also that after auto alignment is turned off the mips assembler
11956 issues an error on attempt to assemble an improperly aligned data item.
11961 temp = get_absolute_expression ();
11962 if (temp > max_alignment)
11963 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
11966 as_warn (_("Alignment negative: 0 assumed."));
11969 if (*input_line_pointer == ',')
11971 ++input_line_pointer;
11972 temp_fill = get_absolute_expression ();
11979 mips_align (temp, (int) temp_fill,
11980 insn_labels != NULL ? insn_labels->label : NULL);
11987 demand_empty_rest_of_line ();
11991 mips_flush_pending_output ()
11993 mips_emit_delays (FALSE);
11994 mips_clear_insn_labels ();
12003 /* When generating embedded PIC code, we only use the .text, .lit8,
12004 .sdata and .sbss sections. We change the .data and .rdata
12005 pseudo-ops to use .sdata. */
12006 if (mips_pic == EMBEDDED_PIC
12007 && (sec == 'd' || sec == 'r'))
12011 /* The ELF backend needs to know that we are changing sections, so
12012 that .previous works correctly. We could do something like check
12013 for an obj_section_change_hook macro, but that might be confusing
12014 as it would not be appropriate to use it in the section changing
12015 functions in read.c, since obj-elf.c intercepts those. FIXME:
12016 This should be cleaner, somehow. */
12017 obj_elf_section_change_hook ();
12020 mips_emit_delays (FALSE);
12030 subseg_set (bss_section, (subsegT) get_absolute_expression ());
12031 demand_empty_rest_of_line ();
12035 if (USE_GLOBAL_POINTER_OPT)
12037 seg = subseg_new (RDATA_SECTION_NAME,
12038 (subsegT) get_absolute_expression ());
12039 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
12041 bfd_set_section_flags (stdoutput, seg,
12047 if (strcmp (TARGET_OS, "elf") != 0)
12048 record_alignment (seg, 4);
12050 demand_empty_rest_of_line ();
12054 as_bad (_("No read only data section in this object file format"));
12055 demand_empty_rest_of_line ();
12061 if (USE_GLOBAL_POINTER_OPT)
12063 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
12064 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
12066 bfd_set_section_flags (stdoutput, seg,
12067 SEC_ALLOC | SEC_LOAD | SEC_RELOC
12069 if (strcmp (TARGET_OS, "elf") != 0)
12070 record_alignment (seg, 4);
12072 demand_empty_rest_of_line ();
12077 as_bad (_("Global pointers not supported; recompile -G 0"));
12078 demand_empty_rest_of_line ();
12087 s_change_section (ignore)
12088 int ignore ATTRIBUTE_UNUSED;
12091 char *section_name;
12096 int section_entry_size;
12097 int section_alignment;
12099 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
12102 section_name = input_line_pointer;
12103 c = get_symbol_end ();
12105 next_c = *(input_line_pointer + 1);
12107 /* Do we have .section Name<,"flags">? */
12108 if (c != ',' || (c == ',' && next_c == '"'))
12110 /* just after name is now '\0'. */
12111 *input_line_pointer = c;
12112 input_line_pointer = section_name;
12113 obj_elf_section (ignore);
12116 input_line_pointer++;
12118 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
12120 section_type = get_absolute_expression ();
12123 if (*input_line_pointer++ == ',')
12124 section_flag = get_absolute_expression ();
12127 if (*input_line_pointer++ == ',')
12128 section_entry_size = get_absolute_expression ();
12130 section_entry_size = 0;
12131 if (*input_line_pointer++ == ',')
12132 section_alignment = get_absolute_expression ();
12134 section_alignment = 0;
12136 section_name = xstrdup (section_name);
12138 obj_elf_change_section (section_name, section_type, section_flag,
12139 section_entry_size, 0, 0, 0);
12141 if (now_seg->name != section_name)
12142 free (section_name);
12143 #endif /* OBJ_ELF */
12147 mips_enable_auto_align ()
12158 label = insn_labels != NULL ? insn_labels->label : NULL;
12159 mips_emit_delays (FALSE);
12160 if (log_size > 0 && auto_align)
12161 mips_align (log_size, 0, label);
12162 mips_clear_insn_labels ();
12163 cons (1 << log_size);
12167 s_float_cons (type)
12172 label = insn_labels != NULL ? insn_labels->label : NULL;
12174 mips_emit_delays (FALSE);
12179 mips_align (3, 0, label);
12181 mips_align (2, 0, label);
12184 mips_clear_insn_labels ();
12189 /* Handle .globl. We need to override it because on Irix 5 you are
12192 where foo is an undefined symbol, to mean that foo should be
12193 considered to be the address of a function. */
12197 int x ATTRIBUTE_UNUSED;
12204 name = input_line_pointer;
12205 c = get_symbol_end ();
12206 symbolP = symbol_find_or_make (name);
12207 *input_line_pointer = c;
12208 SKIP_WHITESPACE ();
12210 /* On Irix 5, every global symbol that is not explicitly labelled as
12211 being a function is apparently labelled as being an object. */
12214 if (! is_end_of_line[(unsigned char) *input_line_pointer])
12219 secname = input_line_pointer;
12220 c = get_symbol_end ();
12221 sec = bfd_get_section_by_name (stdoutput, secname);
12223 as_bad (_("%s: no such section"), secname);
12224 *input_line_pointer = c;
12226 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
12227 flag = BSF_FUNCTION;
12230 symbol_get_bfdsym (symbolP)->flags |= flag;
12232 S_SET_EXTERNAL (symbolP);
12233 demand_empty_rest_of_line ();
12238 int x ATTRIBUTE_UNUSED;
12243 opt = input_line_pointer;
12244 c = get_symbol_end ();
12248 /* FIXME: What does this mean? */
12250 else if (strncmp (opt, "pic", 3) == 0)
12254 i = atoi (opt + 3);
12259 mips_pic = SVR4_PIC;
12260 mips_abicalls = TRUE;
12263 as_bad (_(".option pic%d not supported"), i);
12265 if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC)
12267 if (g_switch_seen && g_switch_value != 0)
12268 as_warn (_("-G may not be used with SVR4 PIC code"));
12269 g_switch_value = 0;
12270 bfd_set_gp_size (stdoutput, 0);
12274 as_warn (_("Unrecognized option \"%s\""), opt);
12276 *input_line_pointer = c;
12277 demand_empty_rest_of_line ();
12280 /* This structure is used to hold a stack of .set values. */
12282 struct mips_option_stack
12284 struct mips_option_stack *next;
12285 struct mips_set_options options;
12288 static struct mips_option_stack *mips_opts_stack;
12290 /* Handle the .set pseudo-op. */
12294 int x ATTRIBUTE_UNUSED;
12296 char *name = input_line_pointer, ch;
12298 while (!is_end_of_line[(unsigned char) *input_line_pointer])
12299 ++input_line_pointer;
12300 ch = *input_line_pointer;
12301 *input_line_pointer = '\0';
12303 if (strcmp (name, "reorder") == 0)
12305 if (mips_opts.noreorder && prev_nop_frag != NULL)
12307 /* If we still have pending nops, we can discard them. The
12308 usual nop handling will insert any that are still
12310 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
12311 * (mips_opts.mips16 ? 2 : 4));
12312 prev_nop_frag = NULL;
12314 mips_opts.noreorder = 0;
12316 else if (strcmp (name, "noreorder") == 0)
12318 mips_emit_delays (TRUE);
12319 mips_opts.noreorder = 1;
12320 mips_any_noreorder = 1;
12322 else if (strcmp (name, "at") == 0)
12324 mips_opts.noat = 0;
12326 else if (strcmp (name, "noat") == 0)
12328 mips_opts.noat = 1;
12330 else if (strcmp (name, "macro") == 0)
12332 mips_opts.warn_about_macros = 0;
12334 else if (strcmp (name, "nomacro") == 0)
12336 if (mips_opts.noreorder == 0)
12337 as_bad (_("`noreorder' must be set before `nomacro'"));
12338 mips_opts.warn_about_macros = 1;
12340 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
12342 mips_opts.nomove = 0;
12344 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
12346 mips_opts.nomove = 1;
12348 else if (strcmp (name, "bopt") == 0)
12350 mips_opts.nobopt = 0;
12352 else if (strcmp (name, "nobopt") == 0)
12354 mips_opts.nobopt = 1;
12356 else if (strcmp (name, "mips16") == 0
12357 || strcmp (name, "MIPS-16") == 0)
12358 mips_opts.mips16 = 1;
12359 else if (strcmp (name, "nomips16") == 0
12360 || strcmp (name, "noMIPS-16") == 0)
12361 mips_opts.mips16 = 0;
12362 else if (strcmp (name, "mips3d") == 0)
12363 mips_opts.ase_mips3d = 1;
12364 else if (strcmp (name, "nomips3d") == 0)
12365 mips_opts.ase_mips3d = 0;
12366 else if (strcmp (name, "mdmx") == 0)
12367 mips_opts.ase_mdmx = 1;
12368 else if (strcmp (name, "nomdmx") == 0)
12369 mips_opts.ase_mdmx = 0;
12370 else if (strncmp (name, "mips", 4) == 0)
12374 /* Permit the user to change the ISA on the fly. Needless to
12375 say, misuse can cause serious problems. */
12376 if (strcmp (name, "mips0") == 0)
12379 mips_opts.isa = file_mips_isa;
12381 else if (strcmp (name, "mips1") == 0)
12382 mips_opts.isa = ISA_MIPS1;
12383 else if (strcmp (name, "mips2") == 0)
12384 mips_opts.isa = ISA_MIPS2;
12385 else if (strcmp (name, "mips3") == 0)
12386 mips_opts.isa = ISA_MIPS3;
12387 else if (strcmp (name, "mips4") == 0)
12388 mips_opts.isa = ISA_MIPS4;
12389 else if (strcmp (name, "mips5") == 0)
12390 mips_opts.isa = ISA_MIPS5;
12391 else if (strcmp (name, "mips32") == 0)
12392 mips_opts.isa = ISA_MIPS32;
12393 else if (strcmp (name, "mips32r2") == 0)
12394 mips_opts.isa = ISA_MIPS32R2;
12395 else if (strcmp (name, "mips64") == 0)
12396 mips_opts.isa = ISA_MIPS64;
12398 as_bad (_("unknown ISA level %s"), name + 4);
12400 switch (mips_opts.isa)
12408 mips_opts.gp32 = 1;
12409 mips_opts.fp32 = 1;
12415 mips_opts.gp32 = 0;
12416 mips_opts.fp32 = 0;
12419 as_bad (_("unknown ISA level %s"), name + 4);
12424 mips_opts.gp32 = file_mips_gp32;
12425 mips_opts.fp32 = file_mips_fp32;
12428 else if (strcmp (name, "autoextend") == 0)
12429 mips_opts.noautoextend = 0;
12430 else if (strcmp (name, "noautoextend") == 0)
12431 mips_opts.noautoextend = 1;
12432 else if (strcmp (name, "push") == 0)
12434 struct mips_option_stack *s;
12436 s = (struct mips_option_stack *) xmalloc (sizeof *s);
12437 s->next = mips_opts_stack;
12438 s->options = mips_opts;
12439 mips_opts_stack = s;
12441 else if (strcmp (name, "pop") == 0)
12443 struct mips_option_stack *s;
12445 s = mips_opts_stack;
12447 as_bad (_(".set pop with no .set push"));
12450 /* If we're changing the reorder mode we need to handle
12451 delay slots correctly. */
12452 if (s->options.noreorder && ! mips_opts.noreorder)
12453 mips_emit_delays (TRUE);
12454 else if (! s->options.noreorder && mips_opts.noreorder)
12456 if (prev_nop_frag != NULL)
12458 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
12459 * (mips_opts.mips16 ? 2 : 4));
12460 prev_nop_frag = NULL;
12464 mips_opts = s->options;
12465 mips_opts_stack = s->next;
12469 else if (strncmp (name, "arch=", 5) == 0)
12471 /* Permit the user to change the architecture on the fly. Needless
12472 to say, misuse can cause serious problems. */
12473 if (strcmp (name + 5, "default") == 0)
12475 mips_opts.arch = file_mips_arch;
12476 mips_opts.isa = file_mips_isa;
12477 mips_opts.gp32 = file_mips_gp32;
12478 mips_opts.fp32 = file_mips_fp32;
12482 const struct mips_cpu_info *p;
12484 p = mips_parse_cpu("internal use", name + 5);
12486 as_bad (_("unknown architecture %s"), name + 5);
12489 mips_opts.arch = p->cpu;
12490 mips_opts.isa = p->isa;
12493 switch (mips_opts.arch)
12500 mips_opts.gp32 = 1;
12501 mips_opts.fp32 = 1;
12504 mips_opts.gp32 = 0;
12505 mips_opts.fp32 = 0;
12512 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
12514 *input_line_pointer = ch;
12515 demand_empty_rest_of_line ();
12518 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
12519 .option pic2. It means to generate SVR4 PIC calls. */
12522 s_abicalls (ignore)
12523 int ignore ATTRIBUTE_UNUSED;
12525 mips_pic = SVR4_PIC;
12526 mips_abicalls = TRUE;
12527 if (USE_GLOBAL_POINTER_OPT)
12529 if (g_switch_seen && g_switch_value != 0)
12530 as_warn (_("-G may not be used with SVR4 PIC code"));
12531 g_switch_value = 0;
12533 bfd_set_gp_size (stdoutput, 0);
12534 demand_empty_rest_of_line ();
12537 /* Handle the .cpload pseudo-op. This is used when generating SVR4
12538 PIC code. It sets the $gp register for the function based on the
12539 function address, which is in the register named in the argument.
12540 This uses a relocation against _gp_disp, which is handled specially
12541 by the linker. The result is:
12542 lui $gp,%hi(_gp_disp)
12543 addiu $gp,$gp,%lo(_gp_disp)
12544 addu $gp,$gp,.cpload argument
12545 The .cpload argument is normally $25 == $t9. */
12549 int ignore ATTRIBUTE_UNUSED;
12554 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12555 .cpload is ignored. */
12556 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12562 /* .cpload should be in a .set noreorder section. */
12563 if (mips_opts.noreorder == 0)
12564 as_warn (_(".cpload not in noreorder section"));
12566 ex.X_op = O_symbol;
12567 ex.X_add_symbol = symbol_find_or_make ("_gp_disp");
12568 ex.X_op_symbol = NULL;
12569 ex.X_add_number = 0;
12571 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12572 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
12574 macro_build_lui (NULL, &icnt, &ex, mips_gp_register);
12575 macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j",
12576 mips_gp_register, mips_gp_register, (int) BFD_RELOC_LO16);
12578 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t",
12579 mips_gp_register, mips_gp_register, tc_get_register (0));
12581 demand_empty_rest_of_line ();
12584 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12585 .cpsetup $reg1, offset|$reg2, label
12587 If offset is given, this results in:
12588 sd $gp, offset($sp)
12589 lui $gp, %hi(%neg(%gp_rel(label)))
12590 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12591 daddu $gp, $gp, $reg1
12593 If $reg2 is given, this results in:
12594 daddu $reg2, $gp, $0
12595 lui $gp, %hi(%neg(%gp_rel(label)))
12596 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12597 daddu $gp, $gp, $reg1
12598 $reg1 is normally $25 == $t9. */
12601 int ignore ATTRIBUTE_UNUSED;
12603 expressionS ex_off;
12604 expressionS ex_sym;
12609 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12610 We also need NewABI support. */
12611 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12617 reg1 = tc_get_register (0);
12618 SKIP_WHITESPACE ();
12619 if (*input_line_pointer != ',')
12621 as_bad (_("missing argument separator ',' for .cpsetup"));
12625 ++input_line_pointer;
12626 SKIP_WHITESPACE ();
12627 if (*input_line_pointer == '$')
12629 mips_cpreturn_register = tc_get_register (0);
12630 mips_cpreturn_offset = -1;
12634 mips_cpreturn_offset = get_absolute_expression ();
12635 mips_cpreturn_register = -1;
12637 SKIP_WHITESPACE ();
12638 if (*input_line_pointer != ',')
12640 as_bad (_("missing argument separator ',' for .cpsetup"));
12644 ++input_line_pointer;
12645 SKIP_WHITESPACE ();
12646 expression (&ex_sym);
12648 if (mips_cpreturn_register == -1)
12650 ex_off.X_op = O_constant;
12651 ex_off.X_add_symbol = NULL;
12652 ex_off.X_op_symbol = NULL;
12653 ex_off.X_add_number = mips_cpreturn_offset;
12655 macro_build ((char *) NULL, &icnt, &ex_off, "sd", "t,o(b)",
12656 mips_gp_register, (int) BFD_RELOC_LO16, SP);
12659 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu",
12660 "d,v,t", mips_cpreturn_register, mips_gp_register, 0);
12662 /* Ensure there's room for the next two instructions, so that `f'
12663 doesn't end up with an address in the wrong frag. */
12666 macro_build ((char *) NULL, &icnt, &ex_sym, "lui", "t,u", mips_gp_register,
12667 (int) BFD_RELOC_GPREL16);
12668 fix_new (frag_now, f - frag_now->fr_literal,
12669 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
12670 fix_new (frag_now, f - frag_now->fr_literal,
12671 4, NULL, 0, 0, BFD_RELOC_HI16_S);
12674 macro_build ((char *) NULL, &icnt, &ex_sym, "addiu", "t,r,j",
12675 mips_gp_register, mips_gp_register, (int) BFD_RELOC_GPREL16);
12676 fix_new (frag_now, f - frag_now->fr_literal,
12677 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
12678 fix_new (frag_now, f - frag_now->fr_literal,
12679 4, NULL, 0, 0, BFD_RELOC_LO16);
12681 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, ADDRESS_ADD_INSN,
12682 "d,v,t", mips_gp_register, mips_gp_register, reg1);
12684 demand_empty_rest_of_line ();
12689 int ignore ATTRIBUTE_UNUSED;
12691 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12692 .cplocal is ignored. */
12693 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12699 mips_gp_register = tc_get_register (0);
12700 demand_empty_rest_of_line ();
12703 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12704 offset from $sp. The offset is remembered, and after making a PIC
12705 call $gp is restored from that location. */
12708 s_cprestore (ignore)
12709 int ignore ATTRIBUTE_UNUSED;
12714 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12715 .cprestore is ignored. */
12716 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12722 mips_cprestore_offset = get_absolute_expression ();
12723 mips_cprestore_valid = 1;
12725 ex.X_op = O_constant;
12726 ex.X_add_symbol = NULL;
12727 ex.X_op_symbol = NULL;
12728 ex.X_add_number = mips_cprestore_offset;
12730 macro_build_ldst_constoffset ((char *) NULL, &icnt, &ex, ADDRESS_STORE_INSN,
12731 mips_gp_register, SP);
12733 demand_empty_rest_of_line ();
12736 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12737 was given in the preceeding .gpsetup, it results in:
12738 ld $gp, offset($sp)
12740 If a register $reg2 was given there, it results in:
12741 daddiu $gp, $gp, $reg2
12744 s_cpreturn (ignore)
12745 int ignore ATTRIBUTE_UNUSED;
12750 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12751 We also need NewABI support. */
12752 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12758 if (mips_cpreturn_register == -1)
12760 ex.X_op = O_constant;
12761 ex.X_add_symbol = NULL;
12762 ex.X_op_symbol = NULL;
12763 ex.X_add_number = mips_cpreturn_offset;
12765 macro_build ((char *) NULL, &icnt, &ex, "ld", "t,o(b)",
12766 mips_gp_register, (int) BFD_RELOC_LO16, SP);
12769 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu",
12770 "d,v,t", mips_gp_register, mips_cpreturn_register, 0);
12772 demand_empty_rest_of_line ();
12775 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12776 code. It sets the offset to use in gp_rel relocations. */
12780 int ignore ATTRIBUTE_UNUSED;
12782 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12783 We also need NewABI support. */
12784 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12790 mips_gprel_offset = get_absolute_expression ();
12792 demand_empty_rest_of_line ();
12795 /* Handle the .gpword pseudo-op. This is used when generating PIC
12796 code. It generates a 32 bit GP relative reloc. */
12800 int ignore ATTRIBUTE_UNUSED;
12806 /* When not generating PIC code, this is treated as .word. */
12807 if (mips_pic != SVR4_PIC)
12813 label = insn_labels != NULL ? insn_labels->label : NULL;
12814 mips_emit_delays (TRUE);
12816 mips_align (2, 0, label);
12817 mips_clear_insn_labels ();
12821 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12823 as_bad (_("Unsupported use of .gpword"));
12824 ignore_rest_of_line ();
12828 md_number_to_chars (p, (valueT) 0, 4);
12829 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
12830 BFD_RELOC_GPREL32);
12832 demand_empty_rest_of_line ();
12837 int ignore ATTRIBUTE_UNUSED;
12843 /* When not generating PIC code, this is treated as .dword. */
12844 if (mips_pic != SVR4_PIC)
12850 label = insn_labels != NULL ? insn_labels->label : NULL;
12851 mips_emit_delays (TRUE);
12853 mips_align (3, 0, label);
12854 mips_clear_insn_labels ();
12858 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12860 as_bad (_("Unsupported use of .gpdword"));
12861 ignore_rest_of_line ();
12865 md_number_to_chars (p, (valueT) 0, 8);
12866 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
12867 BFD_RELOC_GPREL32);
12869 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12870 ex.X_op = O_absent;
12871 ex.X_add_symbol = 0;
12872 ex.X_add_number = 0;
12873 fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &ex, FALSE,
12876 demand_empty_rest_of_line ();
12879 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12880 tables in SVR4 PIC code. */
12884 int ignore ATTRIBUTE_UNUSED;
12889 /* This is ignored when not generating SVR4 PIC code. */
12890 if (mips_pic != SVR4_PIC)
12896 /* Add $gp to the register named as an argument. */
12897 reg = tc_get_register (0);
12898 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, ADDRESS_ADD_INSN,
12899 "d,v,t", reg, reg, mips_gp_register);
12901 demand_empty_rest_of_line ();
12904 /* Handle the .insn pseudo-op. This marks instruction labels in
12905 mips16 mode. This permits the linker to handle them specially,
12906 such as generating jalx instructions when needed. We also make
12907 them odd for the duration of the assembly, in order to generate the
12908 right sort of code. We will make them even in the adjust_symtab
12909 routine, while leaving them marked. This is convenient for the
12910 debugger and the disassembler. The linker knows to make them odd
12915 int ignore ATTRIBUTE_UNUSED;
12917 mips16_mark_labels ();
12919 demand_empty_rest_of_line ();
12922 /* Handle a .stabn directive. We need these in order to mark a label
12923 as being a mips16 text label correctly. Sometimes the compiler
12924 will emit a label, followed by a .stabn, and then switch sections.
12925 If the label and .stabn are in mips16 mode, then the label is
12926 really a mips16 text label. */
12933 mips16_mark_labels ();
12938 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12942 s_mips_weakext (ignore)
12943 int ignore ATTRIBUTE_UNUSED;
12950 name = input_line_pointer;
12951 c = get_symbol_end ();
12952 symbolP = symbol_find_or_make (name);
12953 S_SET_WEAK (symbolP);
12954 *input_line_pointer = c;
12956 SKIP_WHITESPACE ();
12958 if (! is_end_of_line[(unsigned char) *input_line_pointer])
12960 if (S_IS_DEFINED (symbolP))
12962 as_bad ("ignoring attempt to redefine symbol %s",
12963 S_GET_NAME (symbolP));
12964 ignore_rest_of_line ();
12968 if (*input_line_pointer == ',')
12970 ++input_line_pointer;
12971 SKIP_WHITESPACE ();
12975 if (exp.X_op != O_symbol)
12977 as_bad ("bad .weakext directive");
12978 ignore_rest_of_line ();
12981 symbol_set_value_expression (symbolP, &exp);
12984 demand_empty_rest_of_line ();
12987 /* Parse a register string into a number. Called from the ECOFF code
12988 to parse .frame. The argument is non-zero if this is the frame
12989 register, so that we can record it in mips_frame_reg. */
12992 tc_get_register (frame)
12997 SKIP_WHITESPACE ();
12998 if (*input_line_pointer++ != '$')
13000 as_warn (_("expected `$'"));
13003 else if (ISDIGIT (*input_line_pointer))
13005 reg = get_absolute_expression ();
13006 if (reg < 0 || reg >= 32)
13008 as_warn (_("Bad register number"));
13014 if (strncmp (input_line_pointer, "ra", 2) == 0)
13017 input_line_pointer += 2;
13019 else if (strncmp (input_line_pointer, "fp", 2) == 0)
13022 input_line_pointer += 2;
13024 else if (strncmp (input_line_pointer, "sp", 2) == 0)
13027 input_line_pointer += 2;
13029 else if (strncmp (input_line_pointer, "gp", 2) == 0)
13032 input_line_pointer += 2;
13034 else if (strncmp (input_line_pointer, "at", 2) == 0)
13037 input_line_pointer += 2;
13039 else if (strncmp (input_line_pointer, "kt0", 3) == 0)
13042 input_line_pointer += 3;
13044 else if (strncmp (input_line_pointer, "kt1", 3) == 0)
13047 input_line_pointer += 3;
13049 else if (strncmp (input_line_pointer, "zero", 4) == 0)
13052 input_line_pointer += 4;
13056 as_warn (_("Unrecognized register name"));
13058 while (ISALNUM(*input_line_pointer))
13059 input_line_pointer++;
13064 mips_frame_reg = reg != 0 ? reg : SP;
13065 mips_frame_reg_valid = 1;
13066 mips_cprestore_valid = 0;
13072 md_section_align (seg, addr)
13076 int align = bfd_get_section_alignment (stdoutput, seg);
13079 /* We don't need to align ELF sections to the full alignment.
13080 However, Irix 5 may prefer that we align them at least to a 16
13081 byte boundary. We don't bother to align the sections if we are
13082 targeted for an embedded system. */
13083 if (strcmp (TARGET_OS, "elf") == 0)
13089 return ((addr + (1 << align) - 1) & (-1 << align));
13092 /* Utility routine, called from above as well. If called while the
13093 input file is still being read, it's only an approximation. (For
13094 example, a symbol may later become defined which appeared to be
13095 undefined earlier.) */
13098 nopic_need_relax (sym, before_relaxing)
13100 int before_relaxing;
13105 if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0)
13107 const char *symname;
13110 /* Find out whether this symbol can be referenced off the $gp
13111 register. It can be if it is smaller than the -G size or if
13112 it is in the .sdata or .sbss section. Certain symbols can
13113 not be referenced off the $gp, although it appears as though
13115 symname = S_GET_NAME (sym);
13116 if (symname != (const char *) NULL
13117 && (strcmp (symname, "eprol") == 0
13118 || strcmp (symname, "etext") == 0
13119 || strcmp (symname, "_gp") == 0
13120 || strcmp (symname, "edata") == 0
13121 || strcmp (symname, "_fbss") == 0
13122 || strcmp (symname, "_fdata") == 0
13123 || strcmp (symname, "_ftext") == 0
13124 || strcmp (symname, "end") == 0
13125 || strcmp (symname, "_gp_disp") == 0))
13127 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
13129 #ifndef NO_ECOFF_DEBUGGING
13130 || (symbol_get_obj (sym)->ecoff_extern_size != 0
13131 && (symbol_get_obj (sym)->ecoff_extern_size
13132 <= g_switch_value))
13134 /* We must defer this decision until after the whole
13135 file has been read, since there might be a .extern
13136 after the first use of this symbol. */
13137 || (before_relaxing
13138 #ifndef NO_ECOFF_DEBUGGING
13139 && symbol_get_obj (sym)->ecoff_extern_size == 0
13141 && S_GET_VALUE (sym) == 0)
13142 || (S_GET_VALUE (sym) != 0
13143 && S_GET_VALUE (sym) <= g_switch_value)))
13147 const char *segname;
13149 segname = segment_name (S_GET_SEGMENT (sym));
13150 assert (strcmp (segname, ".lit8") != 0
13151 && strcmp (segname, ".lit4") != 0);
13152 change = (strcmp (segname, ".sdata") != 0
13153 && strcmp (segname, ".sbss") != 0
13154 && strncmp (segname, ".sdata.", 7) != 0
13155 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
13160 /* We are not optimizing for the $gp register. */
13165 /* Return true if the given symbol should be considered local for SVR4 PIC. */
13168 pic_need_relax (sym, segtype)
13173 bfd_boolean linkonce;
13175 /* Handle the case of a symbol equated to another symbol. */
13176 while (symbol_equated_reloc_p (sym))
13180 /* It's possible to get a loop here in a badly written
13182 n = symbol_get_value_expression (sym)->X_add_symbol;
13188 symsec = S_GET_SEGMENT (sym);
13190 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
13192 if (symsec != segtype && ! S_IS_LOCAL (sym))
13194 if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE)
13198 /* The GNU toolchain uses an extension for ELF: a section
13199 beginning with the magic string .gnu.linkonce is a linkonce
13201 if (strncmp (segment_name (symsec), ".gnu.linkonce",
13202 sizeof ".gnu.linkonce" - 1) == 0)
13206 /* This must duplicate the test in adjust_reloc_syms. */
13207 return (symsec != &bfd_und_section
13208 && symsec != &bfd_abs_section
13209 && ! bfd_is_com_section (symsec)
13212 /* A global or weak symbol is treated as external. */
13213 && (OUTPUT_FLAVOR != bfd_target_elf_flavour
13214 || (! S_IS_WEAK (sym)
13215 && (! S_IS_EXTERNAL (sym)
13216 || mips_pic == EMBEDDED_PIC)))
13222 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
13223 extended opcode. SEC is the section the frag is in. */
13226 mips16_extended_frag (fragp, sec, stretch)
13232 register const struct mips16_immed_operand *op;
13234 int mintiny, maxtiny;
13238 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
13240 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
13243 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
13244 op = mips16_immed_operands;
13245 while (op->type != type)
13248 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
13253 if (type == '<' || type == '>' || type == '[' || type == ']')
13256 maxtiny = 1 << op->nbits;
13261 maxtiny = (1 << op->nbits) - 1;
13266 mintiny = - (1 << (op->nbits - 1));
13267 maxtiny = (1 << (op->nbits - 1)) - 1;
13270 sym_frag = symbol_get_frag (fragp->fr_symbol);
13271 val = S_GET_VALUE (fragp->fr_symbol);
13272 symsec = S_GET_SEGMENT (fragp->fr_symbol);
13278 /* We won't have the section when we are called from
13279 mips_relax_frag. However, we will always have been called
13280 from md_estimate_size_before_relax first. If this is a
13281 branch to a different section, we mark it as such. If SEC is
13282 NULL, and the frag is not marked, then it must be a branch to
13283 the same section. */
13286 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
13291 /* Must have been called from md_estimate_size_before_relax. */
13294 fragp->fr_subtype =
13295 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
13297 /* FIXME: We should support this, and let the linker
13298 catch branches and loads that are out of range. */
13299 as_bad_where (fragp->fr_file, fragp->fr_line,
13300 _("unsupported PC relative reference to different section"));
13304 if (fragp != sym_frag && sym_frag->fr_address == 0)
13305 /* Assume non-extended on the first relaxation pass.
13306 The address we have calculated will be bogus if this is
13307 a forward branch to another frag, as the forward frag
13308 will have fr_address == 0. */
13312 /* In this case, we know for sure that the symbol fragment is in
13313 the same section. If the relax_marker of the symbol fragment
13314 differs from the relax_marker of this fragment, we have not
13315 yet adjusted the symbol fragment fr_address. We want to add
13316 in STRETCH in order to get a better estimate of the address.
13317 This particularly matters because of the shift bits. */
13319 && sym_frag->relax_marker != fragp->relax_marker)
13323 /* Adjust stretch for any alignment frag. Note that if have
13324 been expanding the earlier code, the symbol may be
13325 defined in what appears to be an earlier frag. FIXME:
13326 This doesn't handle the fr_subtype field, which specifies
13327 a maximum number of bytes to skip when doing an
13329 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
13331 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
13334 stretch = - ((- stretch)
13335 & ~ ((1 << (int) f->fr_offset) - 1));
13337 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
13346 addr = fragp->fr_address + fragp->fr_fix;
13348 /* The base address rules are complicated. The base address of
13349 a branch is the following instruction. The base address of a
13350 PC relative load or add is the instruction itself, but if it
13351 is in a delay slot (in which case it can not be extended) use
13352 the address of the instruction whose delay slot it is in. */
13353 if (type == 'p' || type == 'q')
13357 /* If we are currently assuming that this frag should be
13358 extended, then, the current address is two bytes
13360 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13363 /* Ignore the low bit in the target, since it will be set
13364 for a text label. */
13365 if ((val & 1) != 0)
13368 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
13370 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
13373 val -= addr & ~ ((1 << op->shift) - 1);
13375 /* Branch offsets have an implicit 0 in the lowest bit. */
13376 if (type == 'p' || type == 'q')
13379 /* If any of the shifted bits are set, we must use an extended
13380 opcode. If the address depends on the size of this
13381 instruction, this can lead to a loop, so we arrange to always
13382 use an extended opcode. We only check this when we are in
13383 the main relaxation loop, when SEC is NULL. */
13384 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
13386 fragp->fr_subtype =
13387 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
13391 /* If we are about to mark a frag as extended because the value
13392 is precisely maxtiny + 1, then there is a chance of an
13393 infinite loop as in the following code:
13398 In this case when the la is extended, foo is 0x3fc bytes
13399 away, so the la can be shrunk, but then foo is 0x400 away, so
13400 the la must be extended. To avoid this loop, we mark the
13401 frag as extended if it was small, and is about to become
13402 extended with a value of maxtiny + 1. */
13403 if (val == ((maxtiny + 1) << op->shift)
13404 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
13407 fragp->fr_subtype =
13408 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
13412 else if (symsec != absolute_section && sec != NULL)
13413 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
13415 if ((val & ((1 << op->shift) - 1)) != 0
13416 || val < (mintiny << op->shift)
13417 || val > (maxtiny << op->shift))
13423 /* Compute the length of a branch sequence, and adjust the
13424 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
13425 worst-case length is computed, with UPDATE being used to indicate
13426 whether an unconditional (-1), branch-likely (+1) or regular (0)
13427 branch is to be computed. */
13429 relaxed_branch_length (fragp, sec, update)
13434 bfd_boolean toofar;
13438 && S_IS_DEFINED (fragp->fr_symbol)
13439 && sec == S_GET_SEGMENT (fragp->fr_symbol))
13444 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
13446 addr = fragp->fr_address + fragp->fr_fix + 4;
13450 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
13453 /* If the symbol is not defined or it's in a different segment,
13454 assume the user knows what's going on and emit a short
13460 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
13462 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype),
13463 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
13464 RELAX_BRANCH_LINK (fragp->fr_subtype),
13470 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
13473 if (mips_pic != NO_PIC)
13475 /* Additional space for PIC loading of target address. */
13477 if (mips_opts.isa == ISA_MIPS1)
13478 /* Additional space for $at-stabilizing nop. */
13482 /* If branch is conditional. */
13483 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
13490 /* Estimate the size of a frag before relaxing. Unless this is the
13491 mips16, we are not really relaxing here, and the final size is
13492 encoded in the subtype information. For the mips16, we have to
13493 decide whether we are using an extended opcode or not. */
13496 md_estimate_size_before_relax (fragp, segtype)
13502 if (RELAX_BRANCH_P (fragp->fr_subtype))
13505 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
13507 return fragp->fr_var;
13510 if (RELAX_MIPS16_P (fragp->fr_subtype))
13511 /* We don't want to modify the EXTENDED bit here; it might get us
13512 into infinite loops. We change it only in mips_relax_frag(). */
13513 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
13515 if (mips_pic == NO_PIC)
13516 change = nopic_need_relax (fragp->fr_symbol, 0);
13517 else if (mips_pic == SVR4_PIC)
13518 change = pic_need_relax (fragp->fr_symbol, segtype);
13524 /* Record the offset to the first reloc in the fr_opcode field.
13525 This lets md_convert_frag and tc_gen_reloc know that the code
13526 must be expanded. */
13527 fragp->fr_opcode = (fragp->fr_literal
13529 - RELAX_OLD (fragp->fr_subtype)
13530 + RELAX_RELOC1 (fragp->fr_subtype));
13531 /* FIXME: This really needs as_warn_where. */
13532 if (RELAX_WARN (fragp->fr_subtype))
13533 as_warn (_("AT used after \".set noat\" or macro used after "
13534 "\".set nomacro\""));
13536 return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype);
13542 /* This is called to see whether a reloc against a defined symbol
13543 should be converted into a reloc against a section. Don't adjust
13544 MIPS16 jump relocations, so we don't have to worry about the format
13545 of the offset in the .o file. Don't adjust relocations against
13546 mips16 symbols, so that the linker can find them if it needs to set
13550 mips_fix_adjustable (fixp)
13553 if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
13556 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
13557 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
13560 if (fixp->fx_addsy == NULL)
13564 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
13565 && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
13566 && fixp->fx_subsy == NULL)
13573 /* Translate internal representation of relocation info to BFD target
13577 tc_gen_reloc (section, fixp)
13578 asection *section ATTRIBUTE_UNUSED;
13581 static arelent *retval[4];
13583 bfd_reloc_code_real_type code;
13585 memset (retval, 0, sizeof(retval));
13586 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
13587 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
13588 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
13589 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
13591 if (mips_pic == EMBEDDED_PIC
13592 && SWITCH_TABLE (fixp))
13594 /* For a switch table entry we use a special reloc. The addend
13595 is actually the difference between the reloc address and the
13597 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
13598 if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour)
13599 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
13600 fixp->fx_r_type = BFD_RELOC_GPREL32;
13602 else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16)
13604 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
13605 reloc->addend = fixp->fx_addnumber;
13608 /* We use a special addend for an internal RELLO reloc. */
13609 if (symbol_section_p (fixp->fx_addsy))
13610 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
13612 reloc->addend = fixp->fx_addnumber + reloc->address;
13615 else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
13617 assert (fixp->fx_next != NULL
13618 && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16);
13620 /* The reloc is relative to the RELLO; adjust the addend
13622 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
13623 reloc->addend = fixp->fx_next->fx_addnumber;
13626 /* We use a special addend for an internal RELHI reloc. */
13627 if (symbol_section_p (fixp->fx_addsy))
13628 reloc->addend = (fixp->fx_next->fx_frag->fr_address
13629 + fixp->fx_next->fx_where
13630 - S_GET_VALUE (fixp->fx_subsy));
13632 reloc->addend = (fixp->fx_addnumber
13633 + fixp->fx_next->fx_frag->fr_address
13634 + fixp->fx_next->fx_where);
13637 else if (fixp->fx_pcrel == 0 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
13638 reloc->addend = fixp->fx_addnumber;
13641 if (OUTPUT_FLAVOR != bfd_target_aout_flavour)
13642 /* A gruesome hack which is a result of the gruesome gas reloc
13644 reloc->addend = reloc->address;
13646 reloc->addend = -reloc->address;
13649 /* If this is a variant frag, we may need to adjust the existing
13650 reloc and generate a new one. */
13651 if (fixp->fx_frag->fr_opcode != NULL
13652 && ((fixp->fx_r_type == BFD_RELOC_GPREL16
13654 || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_DISP
13656 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
13657 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16
13658 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
13659 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16
13660 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
13661 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)
13666 assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype));
13668 /* If this is not the last reloc in this frag, then we have two
13669 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
13670 CALL_HI16/CALL_LO16, both of which are being replaced. Let
13671 the second one handle all of them. */
13672 if (fixp->fx_next != NULL
13673 && fixp->fx_frag == fixp->fx_next->fx_frag)
13675 assert ((fixp->fx_r_type == BFD_RELOC_GPREL16
13676 && fixp->fx_next->fx_r_type == BFD_RELOC_GPREL16)
13677 || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
13678 && (fixp->fx_next->fx_r_type
13679 == BFD_RELOC_MIPS_GOT_LO16))
13680 || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
13681 && (fixp->fx_next->fx_r_type
13682 == BFD_RELOC_MIPS_CALL_LO16)));
13687 fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal;
13688 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
13689 reloc->addend += fixp->fx_frag->tc_frag_data.tc_fr_offset;
13690 reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent));
13691 reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
13692 *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
13693 reloc2->address = (reloc->address
13694 + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype)
13695 - RELAX_RELOC1 (fixp->fx_frag->fr_subtype)));
13696 reloc2->addend = fixp->fx_addnumber - S_GET_VALUE (fixp->fx_addsy)
13697 + fixp->fx_frag->tc_frag_data.tc_fr_offset;
13698 reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16);
13699 assert (reloc2->howto != NULL);
13701 if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype))
13705 reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent));
13707 reloc3->address += 4;
13710 if (mips_pic == NO_PIC)
13712 assert (fixp->fx_r_type == BFD_RELOC_GPREL16);
13713 fixp->fx_r_type = BFD_RELOC_HI16_S;
13715 else if (mips_pic == SVR4_PIC)
13717 switch (fixp->fx_r_type)
13721 case BFD_RELOC_MIPS_GOT16:
13723 case BFD_RELOC_MIPS_GOT_LO16:
13724 case BFD_RELOC_MIPS_CALL_LO16:
13727 fixp->fx_r_type = BFD_RELOC_MIPS_GOT_PAGE;
13728 reloc2->howto = bfd_reloc_type_lookup
13729 (stdoutput, BFD_RELOC_MIPS_GOT_OFST);
13732 fixp->fx_r_type = BFD_RELOC_MIPS_GOT16;
13734 case BFD_RELOC_MIPS_CALL16:
13735 case BFD_RELOC_MIPS_GOT_OFST:
13736 case BFD_RELOC_MIPS_GOT_DISP:
13739 /* It may seem nonsensical to relax GOT_DISP to
13740 GOT_DISP, but we're actually turning a GOT_DISP
13741 without offset into a GOT_DISP with an offset,
13742 getting rid of the separate addition, which we can
13743 do when the symbol is found to be local. */
13744 fixp->fx_r_type = BFD_RELOC_MIPS_GOT_DISP;
13748 fixp->fx_r_type = BFD_RELOC_MIPS_GOT16;
13756 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
13757 entry to be used in the relocation's section offset. */
13758 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
13760 reloc->address = reloc->addend;
13764 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
13765 fixup_segment converted a non-PC relative reloc into a PC
13766 relative reloc. In such a case, we need to convert the reloc
13768 code = fixp->fx_r_type;
13769 if (fixp->fx_pcrel)
13774 code = BFD_RELOC_8_PCREL;
13777 code = BFD_RELOC_16_PCREL;
13780 code = BFD_RELOC_32_PCREL;
13783 code = BFD_RELOC_64_PCREL;
13785 case BFD_RELOC_8_PCREL:
13786 case BFD_RELOC_16_PCREL:
13787 case BFD_RELOC_32_PCREL:
13788 case BFD_RELOC_64_PCREL:
13789 case BFD_RELOC_16_PCREL_S2:
13790 case BFD_RELOC_PCREL_HI16_S:
13791 case BFD_RELOC_PCREL_LO16:
13794 as_bad_where (fixp->fx_file, fixp->fx_line,
13795 _("Cannot make %s relocation PC relative"),
13796 bfd_get_reloc_code_name (code));
13800 /* To support a PC relative reloc when generating embedded PIC code
13801 for ECOFF, we use a Cygnus extension. We check for that here to
13802 make sure that we don't let such a reloc escape normally. */
13803 if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
13804 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
13805 && code == BFD_RELOC_16_PCREL_S2
13806 && mips_pic != EMBEDDED_PIC)
13807 reloc->howto = NULL;
13809 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
13811 if (reloc->howto == NULL)
13813 as_bad_where (fixp->fx_file, fixp->fx_line,
13814 _("Can not represent %s relocation in this object file format"),
13815 bfd_get_reloc_code_name (code));
13822 /* Relax a machine dependent frag. This returns the amount by which
13823 the current size of the frag should change. */
13826 mips_relax_frag (sec, fragp, stretch)
13831 if (RELAX_BRANCH_P (fragp->fr_subtype))
13833 offsetT old_var = fragp->fr_var;
13835 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
13837 return fragp->fr_var - old_var;
13840 if (! RELAX_MIPS16_P (fragp->fr_subtype))
13843 if (mips16_extended_frag (fragp, NULL, stretch))
13845 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13847 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
13852 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13854 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
13861 /* Convert a machine dependent frag. */
13864 md_convert_frag (abfd, asec, fragp)
13865 bfd *abfd ATTRIBUTE_UNUSED;
13872 if (RELAX_BRANCH_P (fragp->fr_subtype))
13875 unsigned long insn;
13879 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
13881 if (target_big_endian)
13882 insn = bfd_getb32 (buf);
13884 insn = bfd_getl32 (buf);
13886 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
13888 /* We generate a fixup instead of applying it right now
13889 because, if there are linker relaxations, we're going to
13890 need the relocations. */
13891 exp.X_op = O_symbol;
13892 exp.X_add_symbol = fragp->fr_symbol;
13893 exp.X_add_number = fragp->fr_offset;
13895 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13897 BFD_RELOC_16_PCREL_S2);
13898 fixp->fx_file = fragp->fr_file;
13899 fixp->fx_line = fragp->fr_line;
13901 md_number_to_chars ((char *)buf, insn, 4);
13908 as_warn_where (fragp->fr_file, fragp->fr_line,
13909 _("relaxed out-of-range branch into a jump"));
13911 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
13914 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13916 /* Reverse the branch. */
13917 switch ((insn >> 28) & 0xf)
13920 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
13921 have the condition reversed by tweaking a single
13922 bit, and their opcodes all have 0x4???????. */
13923 assert ((insn & 0xf1000000) == 0x41000000);
13924 insn ^= 0x00010000;
13928 /* bltz 0x04000000 bgez 0x04010000
13929 bltzal 0x04100000 bgezal 0x04110000 */
13930 assert ((insn & 0xfc0e0000) == 0x04000000);
13931 insn ^= 0x00010000;
13935 /* beq 0x10000000 bne 0x14000000
13936 blez 0x18000000 bgtz 0x1c000000 */
13937 insn ^= 0x04000000;
13945 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13947 /* Clear the and-link bit. */
13948 assert ((insn & 0xfc1c0000) == 0x04100000);
13950 /* bltzal 0x04100000 bgezal 0x04110000
13951 bltzall 0x04120000 bgezall 0x04130000 */
13952 insn &= ~0x00100000;
13955 /* Branch over the branch (if the branch was likely) or the
13956 full jump (not likely case). Compute the offset from the
13957 current instruction to branch to. */
13958 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13962 /* How many bytes in instructions we've already emitted? */
13963 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
13964 /* How many bytes in instructions from here to the end? */
13965 i = fragp->fr_var - i;
13967 /* Convert to instruction count. */
13969 /* Branch counts from the next instruction. */
13972 /* Branch over the jump. */
13973 md_number_to_chars ((char *)buf, insn, 4);
13977 md_number_to_chars ((char*)buf, 0, 4);
13980 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13982 /* beql $0, $0, 2f */
13984 /* Compute the PC offset from the current instruction to
13985 the end of the variable frag. */
13986 /* How many bytes in instructions we've already emitted? */
13987 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
13988 /* How many bytes in instructions from here to the end? */
13989 i = fragp->fr_var - i;
13990 /* Convert to instruction count. */
13992 /* Don't decrement i, because we want to branch over the
13996 md_number_to_chars ((char *)buf, insn, 4);
13999 md_number_to_chars ((char *)buf, 0, 4);
14004 if (mips_pic == NO_PIC)
14007 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
14008 ? 0x0c000000 : 0x08000000);
14009 exp.X_op = O_symbol;
14010 exp.X_add_symbol = fragp->fr_symbol;
14011 exp.X_add_number = fragp->fr_offset;
14013 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14014 4, &exp, 0, BFD_RELOC_MIPS_JMP);
14015 fixp->fx_file = fragp->fr_file;
14016 fixp->fx_line = fragp->fr_line;
14018 md_number_to_chars ((char*)buf, insn, 4);
14023 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
14024 insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000;
14025 exp.X_op = O_symbol;
14026 exp.X_add_symbol = fragp->fr_symbol;
14027 exp.X_add_number = fragp->fr_offset;
14029 if (fragp->fr_offset)
14031 exp.X_add_symbol = make_expr_symbol (&exp);
14032 exp.X_add_number = 0;
14035 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14036 4, &exp, 0, BFD_RELOC_MIPS_GOT16);
14037 fixp->fx_file = fragp->fr_file;
14038 fixp->fx_line = fragp->fr_line;
14040 md_number_to_chars ((char*)buf, insn, 4);
14043 if (mips_opts.isa == ISA_MIPS1)
14046 md_number_to_chars ((char*)buf, 0, 4);
14050 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
14051 insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000;
14053 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14054 4, &exp, 0, BFD_RELOC_LO16);
14055 fixp->fx_file = fragp->fr_file;
14056 fixp->fx_line = fragp->fr_line;
14058 md_number_to_chars ((char*)buf, insn, 4);
14062 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
14067 md_number_to_chars ((char*)buf, insn, 4);
14072 assert (buf == (bfd_byte *)fragp->fr_literal
14073 + fragp->fr_fix + fragp->fr_var);
14075 fragp->fr_fix += fragp->fr_var;
14080 if (RELAX_MIPS16_P (fragp->fr_subtype))
14083 register const struct mips16_immed_operand *op;
14084 bfd_boolean small, ext;
14087 unsigned long insn;
14088 bfd_boolean use_extend;
14089 unsigned short extend;
14091 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
14092 op = mips16_immed_operands;
14093 while (op->type != type)
14096 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14107 resolve_symbol_value (fragp->fr_symbol);
14108 val = S_GET_VALUE (fragp->fr_symbol);
14113 addr = fragp->fr_address + fragp->fr_fix;
14115 /* The rules for the base address of a PC relative reloc are
14116 complicated; see mips16_extended_frag. */
14117 if (type == 'p' || type == 'q')
14122 /* Ignore the low bit in the target, since it will be
14123 set for a text label. */
14124 if ((val & 1) != 0)
14127 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
14129 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
14132 addr &= ~ (addressT) ((1 << op->shift) - 1);
14135 /* Make sure the section winds up with the alignment we have
14138 record_alignment (asec, op->shift);
14142 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
14143 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
14144 as_warn_where (fragp->fr_file, fragp->fr_line,
14145 _("extended instruction in delay slot"));
14147 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
14149 if (target_big_endian)
14150 insn = bfd_getb16 (buf);
14152 insn = bfd_getl16 (buf);
14154 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
14155 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
14156 small, ext, &insn, &use_extend, &extend);
14160 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
14161 fragp->fr_fix += 2;
14165 md_number_to_chars ((char *) buf, insn, 2);
14166 fragp->fr_fix += 2;
14171 if (fragp->fr_opcode == NULL)
14174 old = RELAX_OLD (fragp->fr_subtype);
14175 new = RELAX_NEW (fragp->fr_subtype);
14176 fixptr = fragp->fr_literal + fragp->fr_fix;
14179 memmove (fixptr - old, fixptr, new);
14181 fragp->fr_fix += new - old;
14187 /* This function is called after the relocs have been generated.
14188 We've been storing mips16 text labels as odd. Here we convert them
14189 back to even for the convenience of the debugger. */
14192 mips_frob_file_after_relocs ()
14195 unsigned int count, i;
14197 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
14200 syms = bfd_get_outsymbols (stdoutput);
14201 count = bfd_get_symcount (stdoutput);
14202 for (i = 0; i < count; i++, syms++)
14204 if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16
14205 && ((*syms)->value & 1) != 0)
14207 (*syms)->value &= ~1;
14208 /* If the symbol has an odd size, it was probably computed
14209 incorrectly, so adjust that as well. */
14210 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
14211 ++elf_symbol (*syms)->internal_elf_sym.st_size;
14218 /* This function is called whenever a label is defined. It is used
14219 when handling branch delays; if a branch has a label, we assume we
14220 can not move it. */
14223 mips_define_label (sym)
14226 struct insn_label_list *l;
14228 if (free_insn_labels == NULL)
14229 l = (struct insn_label_list *) xmalloc (sizeof *l);
14232 l = free_insn_labels;
14233 free_insn_labels = l->next;
14237 l->next = insn_labels;
14241 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14243 /* Some special processing for a MIPS ELF file. */
14246 mips_elf_final_processing ()
14248 /* Write out the register information. */
14249 if (mips_abi != N64_ABI)
14253 s.ri_gprmask = mips_gprmask;
14254 s.ri_cprmask[0] = mips_cprmask[0];
14255 s.ri_cprmask[1] = mips_cprmask[1];
14256 s.ri_cprmask[2] = mips_cprmask[2];
14257 s.ri_cprmask[3] = mips_cprmask[3];
14258 /* The gp_value field is set by the MIPS ELF backend. */
14260 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
14261 ((Elf32_External_RegInfo *)
14262 mips_regmask_frag));
14266 Elf64_Internal_RegInfo s;
14268 s.ri_gprmask = mips_gprmask;
14270 s.ri_cprmask[0] = mips_cprmask[0];
14271 s.ri_cprmask[1] = mips_cprmask[1];
14272 s.ri_cprmask[2] = mips_cprmask[2];
14273 s.ri_cprmask[3] = mips_cprmask[3];
14274 /* The gp_value field is set by the MIPS ELF backend. */
14276 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
14277 ((Elf64_External_RegInfo *)
14278 mips_regmask_frag));
14281 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
14282 sort of BFD interface for this. */
14283 if (mips_any_noreorder)
14284 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
14285 if (mips_pic != NO_PIC)
14287 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
14288 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
14291 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
14293 /* Set MIPS ELF flags for ASEs. */
14294 if (file_ase_mips16)
14295 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
14296 #if 0 /* XXX FIXME */
14297 if (file_ase_mips3d)
14298 elf_elfheader (stdoutput)->e_flags |= ???;
14301 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
14303 /* Set the MIPS ELF ABI flags. */
14304 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
14305 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
14306 else if (mips_abi == O64_ABI)
14307 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
14308 else if (mips_abi == EABI_ABI)
14310 if (!file_mips_gp32)
14311 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
14313 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
14315 else if (mips_abi == N32_ABI)
14316 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
14318 /* Nothing to do for N64_ABI. */
14320 if (mips_32bitmode)
14321 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
14324 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
14326 typedef struct proc {
14328 unsigned long reg_mask;
14329 unsigned long reg_offset;
14330 unsigned long fpreg_mask;
14331 unsigned long fpreg_offset;
14332 unsigned long frame_offset;
14333 unsigned long frame_reg;
14334 unsigned long pc_reg;
14337 static procS cur_proc;
14338 static procS *cur_proc_ptr;
14339 static int numprocs;
14341 /* Fill in an rs_align_code fragment. */
14344 mips_handle_align (fragp)
14347 if (fragp->fr_type != rs_align_code)
14350 if (mips_opts.mips16)
14352 static const unsigned char be_nop[] = { 0x65, 0x00 };
14353 static const unsigned char le_nop[] = { 0x00, 0x65 };
14358 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
14359 p = fragp->fr_literal + fragp->fr_fix;
14367 memcpy (p, (target_big_endian ? be_nop : le_nop), 2);
14371 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
14382 /* check for premature end, nesting errors, etc */
14384 as_warn (_("missing .end at end of assembly"));
14393 if (*input_line_pointer == '-')
14395 ++input_line_pointer;
14398 if (!ISDIGIT (*input_line_pointer))
14399 as_bad (_("expected simple number"));
14400 if (input_line_pointer[0] == '0')
14402 if (input_line_pointer[1] == 'x')
14404 input_line_pointer += 2;
14405 while (ISXDIGIT (*input_line_pointer))
14408 val |= hex_value (*input_line_pointer++);
14410 return negative ? -val : val;
14414 ++input_line_pointer;
14415 while (ISDIGIT (*input_line_pointer))
14418 val |= *input_line_pointer++ - '0';
14420 return negative ? -val : val;
14423 if (!ISDIGIT (*input_line_pointer))
14425 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
14426 *input_line_pointer, *input_line_pointer);
14427 as_warn (_("invalid number"));
14430 while (ISDIGIT (*input_line_pointer))
14433 val += *input_line_pointer++ - '0';
14435 return negative ? -val : val;
14438 /* The .file directive; just like the usual .file directive, but there
14439 is an initial number which is the ECOFF file index. In the non-ECOFF
14440 case .file implies DWARF-2. */
14444 int x ATTRIBUTE_UNUSED;
14446 static int first_file_directive = 0;
14448 if (ECOFF_DEBUGGING)
14457 filename = dwarf2_directive_file (0);
14459 /* Versions of GCC up to 3.1 start files with a ".file"
14460 directive even for stabs output. Make sure that this
14461 ".file" is handled. Note that you need a version of GCC
14462 after 3.1 in order to support DWARF-2 on MIPS. */
14463 if (filename != NULL && ! first_file_directive)
14465 (void) new_logical_line (filename, -1);
14466 s_app_file_string (filename);
14468 first_file_directive = 1;
14472 /* The .loc directive, implying DWARF-2. */
14476 int x ATTRIBUTE_UNUSED;
14478 if (!ECOFF_DEBUGGING)
14479 dwarf2_directive_loc (0);
14482 /* The .end directive. */
14486 int x ATTRIBUTE_UNUSED;
14490 /* Following functions need their own .frame and .cprestore directives. */
14491 mips_frame_reg_valid = 0;
14492 mips_cprestore_valid = 0;
14494 if (!is_end_of_line[(unsigned char) *input_line_pointer])
14497 demand_empty_rest_of_line ();
14502 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
14503 as_warn (_(".end not in text section"));
14507 as_warn (_(".end directive without a preceding .ent directive."));
14508 demand_empty_rest_of_line ();
14514 assert (S_GET_NAME (p));
14515 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym)))
14516 as_warn (_(".end symbol does not match .ent symbol."));
14518 if (debug_type == DEBUG_STABS)
14519 stabs_generate_asm_endfunc (S_GET_NAME (p),
14523 as_warn (_(".end directive missing or unknown symbol"));
14526 /* Generate a .pdr section. */
14527 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
14529 segT saved_seg = now_seg;
14530 subsegT saved_subseg = now_subseg;
14535 dot = frag_now_fix ();
14537 #ifdef md_flush_pending_output
14538 md_flush_pending_output ();
14542 subseg_set (pdr_seg, 0);
14544 /* Write the symbol. */
14545 exp.X_op = O_symbol;
14546 exp.X_add_symbol = p;
14547 exp.X_add_number = 0;
14548 emit_expr (&exp, 4);
14550 fragp = frag_more (7 * 4);
14552 md_number_to_chars (fragp, (valueT) cur_proc_ptr->reg_mask, 4);
14553 md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4);
14554 md_number_to_chars (fragp + 8, (valueT) cur_proc_ptr->fpreg_mask, 4);
14555 md_number_to_chars (fragp + 12, (valueT) cur_proc_ptr->fpreg_offset, 4);
14556 md_number_to_chars (fragp + 16, (valueT) cur_proc_ptr->frame_offset, 4);
14557 md_number_to_chars (fragp + 20, (valueT) cur_proc_ptr->frame_reg, 4);
14558 md_number_to_chars (fragp + 24, (valueT) cur_proc_ptr->pc_reg, 4);
14560 subseg_set (saved_seg, saved_subseg);
14562 #endif /* OBJ_ELF */
14564 cur_proc_ptr = NULL;
14567 /* The .aent and .ent directives. */
14575 symbolP = get_symbol ();
14576 if (*input_line_pointer == ',')
14577 ++input_line_pointer;
14578 SKIP_WHITESPACE ();
14579 if (ISDIGIT (*input_line_pointer)
14580 || *input_line_pointer == '-')
14583 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
14584 as_warn (_(".ent or .aent not in text section."));
14586 if (!aent && cur_proc_ptr)
14587 as_warn (_("missing .end"));
14591 /* This function needs its own .frame and .cprestore directives. */
14592 mips_frame_reg_valid = 0;
14593 mips_cprestore_valid = 0;
14595 cur_proc_ptr = &cur_proc;
14596 memset (cur_proc_ptr, '\0', sizeof (procS));
14598 cur_proc_ptr->isym = symbolP;
14600 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
14604 if (debug_type == DEBUG_STABS)
14605 stabs_generate_asm_func (S_GET_NAME (symbolP),
14606 S_GET_NAME (symbolP));
14609 demand_empty_rest_of_line ();
14612 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
14613 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
14614 s_mips_frame is used so that we can set the PDR information correctly.
14615 We can't use the ecoff routines because they make reference to the ecoff
14616 symbol table (in the mdebug section). */
14619 s_mips_frame (ignore)
14620 int ignore ATTRIBUTE_UNUSED;
14623 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
14627 if (cur_proc_ptr == (procS *) NULL)
14629 as_warn (_(".frame outside of .ent"));
14630 demand_empty_rest_of_line ();
14634 cur_proc_ptr->frame_reg = tc_get_register (1);
14636 SKIP_WHITESPACE ();
14637 if (*input_line_pointer++ != ','
14638 || get_absolute_expression_and_terminator (&val) != ',')
14640 as_warn (_("Bad .frame directive"));
14641 --input_line_pointer;
14642 demand_empty_rest_of_line ();
14646 cur_proc_ptr->frame_offset = val;
14647 cur_proc_ptr->pc_reg = tc_get_register (0);
14649 demand_empty_rest_of_line ();
14652 #endif /* OBJ_ELF */
14656 /* The .fmask and .mask directives. If the mdebug section is present
14657 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
14658 embedded targets, s_mips_mask is used so that we can set the PDR
14659 information correctly. We can't use the ecoff routines because they
14660 make reference to the ecoff symbol table (in the mdebug section). */
14663 s_mips_mask (reg_type)
14667 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
14671 if (cur_proc_ptr == (procS *) NULL)
14673 as_warn (_(".mask/.fmask outside of .ent"));
14674 demand_empty_rest_of_line ();
14678 if (get_absolute_expression_and_terminator (&mask) != ',')
14680 as_warn (_("Bad .mask/.fmask directive"));
14681 --input_line_pointer;
14682 demand_empty_rest_of_line ();
14686 off = get_absolute_expression ();
14688 if (reg_type == 'F')
14690 cur_proc_ptr->fpreg_mask = mask;
14691 cur_proc_ptr->fpreg_offset = off;
14695 cur_proc_ptr->reg_mask = mask;
14696 cur_proc_ptr->reg_offset = off;
14699 demand_empty_rest_of_line ();
14702 #endif /* OBJ_ELF */
14703 s_ignore (reg_type);
14706 /* The .loc directive. */
14717 assert (now_seg == text_section);
14719 lineno = get_number ();
14720 addroff = frag_now_fix ();
14722 symbolP = symbol_new ("", N_SLINE, addroff, frag_now);
14723 S_SET_TYPE (symbolP, N_SLINE);
14724 S_SET_OTHER (symbolP, 0);
14725 S_SET_DESC (symbolP, lineno);
14726 symbolP->sy_segment = now_seg;
14730 /* A table describing all the processors gas knows about. Names are
14731 matched in the order listed.
14733 To ease comparison, please keep this table in the same order as
14734 gcc's mips_cpu_info_table[]. */
14735 static const struct mips_cpu_info mips_cpu_info_table[] =
14737 /* Entries for generic ISAs */
14738 { "mips1", 1, ISA_MIPS1, CPU_R3000 },
14739 { "mips2", 1, ISA_MIPS2, CPU_R6000 },
14740 { "mips3", 1, ISA_MIPS3, CPU_R4000 },
14741 { "mips4", 1, ISA_MIPS4, CPU_R8000 },
14742 { "mips5", 1, ISA_MIPS5, CPU_MIPS5 },
14743 { "mips32", 1, ISA_MIPS32, CPU_MIPS32 },
14744 { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 },
14745 { "mips64", 1, ISA_MIPS64, CPU_MIPS64 },
14748 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
14749 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
14750 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
14753 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
14756 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
14757 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
14758 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
14759 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
14760 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
14761 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
14762 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
14763 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
14764 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
14765 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
14766 { "orion", 0, ISA_MIPS3, CPU_R4600 },
14767 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
14770 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
14771 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
14772 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
14773 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
14774 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
14775 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
14776 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
14777 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
14778 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
14779 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
14780 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
14781 { "r7000", 0, ISA_MIPS4, CPU_R5000 },
14784 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
14785 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
14786 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
14789 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
14790 { "20kc", 0, ISA_MIPS64, CPU_MIPS64 },
14792 /* Broadcom SB-1 CPU core */
14793 { "sb1", 0, ISA_MIPS64, CPU_SB1 },
14800 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14801 with a final "000" replaced by "k". Ignore case.
14803 Note: this function is shared between GCC and GAS. */
14806 mips_strict_matching_cpu_name_p (canonical, given)
14807 const char *canonical, *given;
14809 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
14810 given++, canonical++;
14812 return ((*given == 0 && *canonical == 0)
14813 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
14817 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14818 CPU name. We've traditionally allowed a lot of variation here.
14820 Note: this function is shared between GCC and GAS. */
14823 mips_matching_cpu_name_p (canonical, given)
14824 const char *canonical, *given;
14826 /* First see if the name matches exactly, or with a final "000"
14827 turned into "k". */
14828 if (mips_strict_matching_cpu_name_p (canonical, given))
14831 /* If not, try comparing based on numerical designation alone.
14832 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14833 if (TOLOWER (*given) == 'r')
14835 if (!ISDIGIT (*given))
14838 /* Skip over some well-known prefixes in the canonical name,
14839 hoping to find a number there too. */
14840 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
14842 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
14844 else if (TOLOWER (canonical[0]) == 'r')
14847 return mips_strict_matching_cpu_name_p (canonical, given);
14851 /* Parse an option that takes the name of a processor as its argument.
14852 OPTION is the name of the option and CPU_STRING is the argument.
14853 Return the corresponding processor enumeration if the CPU_STRING is
14854 recognized, otherwise report an error and return null.
14856 A similar function exists in GCC. */
14858 static const struct mips_cpu_info *
14859 mips_parse_cpu (option, cpu_string)
14860 const char *option, *cpu_string;
14862 const struct mips_cpu_info *p;
14864 /* 'from-abi' selects the most compatible architecture for the given
14865 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14866 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14867 version. Look first at the -mgp options, if given, otherwise base
14868 the choice on MIPS_DEFAULT_64BIT.
14870 Treat NO_ABI like the EABIs. One reason to do this is that the
14871 plain 'mips' and 'mips64' configs have 'from-abi' as their default
14872 architecture. This code picks MIPS I for 'mips' and MIPS III for
14873 'mips64', just as we did in the days before 'from-abi'. */
14874 if (strcasecmp (cpu_string, "from-abi") == 0)
14876 if (ABI_NEEDS_32BIT_REGS (mips_abi))
14877 return mips_cpu_info_from_isa (ISA_MIPS1);
14879 if (ABI_NEEDS_64BIT_REGS (mips_abi))
14880 return mips_cpu_info_from_isa (ISA_MIPS3);
14882 if (file_mips_gp32 >= 0)
14883 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
14885 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
14890 /* 'default' has traditionally been a no-op. Probably not very useful. */
14891 if (strcasecmp (cpu_string, "default") == 0)
14894 for (p = mips_cpu_info_table; p->name != 0; p++)
14895 if (mips_matching_cpu_name_p (p->name, cpu_string))
14898 as_bad ("Bad value (%s) for %s", cpu_string, option);
14902 /* Return the canonical processor information for ISA (a member of the
14903 ISA_MIPS* enumeration). */
14905 static const struct mips_cpu_info *
14906 mips_cpu_info_from_isa (isa)
14911 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14912 if (mips_cpu_info_table[i].is_isa
14913 && isa == mips_cpu_info_table[i].isa)
14914 return (&mips_cpu_info_table[i]);
14919 static const struct mips_cpu_info *
14920 mips_cpu_info_from_arch (arch)
14925 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14926 if (arch == mips_cpu_info_table[i].cpu)
14927 return (&mips_cpu_info_table[i]);
14933 show (stream, string, col_p, first_p)
14935 const char *string;
14941 fprintf (stream, "%24s", "");
14946 fprintf (stream, ", ");
14950 if (*col_p + strlen (string) > 72)
14952 fprintf (stream, "\n%24s", "");
14956 fprintf (stream, "%s", string);
14957 *col_p += strlen (string);
14963 md_show_usage (stream)
14969 fprintf (stream, _("\
14971 -membedded-pic generate embedded position independent code\n\
14972 -EB generate big endian output\n\
14973 -EL generate little endian output\n\
14974 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14975 -G NUM allow referencing objects up to NUM bytes\n\
14976 implicitly with the gp register [default 8]\n"));
14977 fprintf (stream, _("\
14978 -mips1 generate MIPS ISA I instructions\n\
14979 -mips2 generate MIPS ISA II instructions\n\
14980 -mips3 generate MIPS ISA III instructions\n\
14981 -mips4 generate MIPS ISA IV instructions\n\
14982 -mips5 generate MIPS ISA V instructions\n\
14983 -mips32 generate MIPS32 ISA instructions\n\
14984 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14985 -mips64 generate MIPS64 ISA instructions\n\
14986 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14990 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14991 show (stream, mips_cpu_info_table[i].name, &column, &first);
14992 show (stream, "from-abi", &column, &first);
14993 fputc ('\n', stream);
14995 fprintf (stream, _("\
14996 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14997 -no-mCPU don't generate code specific to CPU.\n\
14998 For -mCPU and -no-mCPU, CPU must be one of:\n"));
15002 show (stream, "3900", &column, &first);
15003 show (stream, "4010", &column, &first);
15004 show (stream, "4100", &column, &first);
15005 show (stream, "4650", &column, &first);
15006 fputc ('\n', stream);
15008 fprintf (stream, _("\
15009 -mips16 generate mips16 instructions\n\
15010 -no-mips16 do not generate mips16 instructions\n"));
15011 fprintf (stream, _("\
15012 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
15013 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
15014 -O0 remove unneeded NOPs, do not swap branches\n\
15015 -O remove unneeded NOPs and swap branches\n\
15016 -n warn about NOPs generated from macros\n\
15017 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
15018 --trap, --no-break trap exception on div by 0 and mult overflow\n\
15019 --break, --no-trap break exception on div by 0 and mult overflow\n"));
15021 fprintf (stream, _("\
15022 -KPIC, -call_shared generate SVR4 position independent code\n\
15023 -non_shared do not generate position independent code\n\
15024 -xgot assume a 32 bit GOT\n\
15025 -mabi=ABI create ABI conformant object file for:\n"));
15029 show (stream, "32", &column, &first);
15030 show (stream, "o64", &column, &first);
15031 show (stream, "n32", &column, &first);
15032 show (stream, "64", &column, &first);
15033 show (stream, "eabi", &column, &first);
15035 fputc ('\n', stream);
15037 fprintf (stream, _("\
15038 -32 create o32 ABI object file (default)\n\
15039 -n32 create n32 ABI object file\n\
15040 -64 create 64 ABI object file\n"));
15045 mips_dwarf2_format ()
15047 if (mips_abi == N64_ABI)
15050 return dwarf2_format_64bit_irix;
15052 return dwarf2_format_64bit;
15056 return dwarf2_format_32bit;