1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2018 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1];
37 typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define streq(a, b) (strcmp (a, b) == 0)
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug = -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr = FALSE;
86 int mips_flag_pdr = TRUE;
91 static char *mips_regmask_frag;
92 static char *mips_flags_frag;
99 #define PIC_CALL_REG 25
107 #define ILLEGAL_REG (32)
109 #define AT mips_opts.at
111 extern int target_big_endian;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME ".rodata"
116 /* Ways in which an instruction can be "appended" to the output. */
118 /* Just add it normally. */
121 /* Add it normally and then add a nop. */
124 /* Turn an instruction with a delay slot into a "compact" version. */
127 /* Insert the instruction before the last one. */
131 /* Information about an instruction, including its format, operands
135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
136 const struct mips_opcode *insn_mo;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. If we have
140 decided to use an extended MIPS16 instruction, this includes the
142 unsigned long insn_opcode;
144 /* The frag that contains the instruction. */
147 /* The offset into FRAG of the first instruction byte. */
150 /* The relocs associated with the instruction, if any. */
153 /* True if this entry cannot be moved from its current position. */
154 unsigned int fixed_p : 1;
156 /* True if this instruction occurred in a .set noreorder block. */
157 unsigned int noreorder_p : 1;
159 /* True for mips16 instructions that jump to an absolute address. */
160 unsigned int mips16_absolute_jump_p : 1;
162 /* True if this instruction is complete. */
163 unsigned int complete_p : 1;
165 /* True if this instruction is cleared from history by unconditional
167 unsigned int cleared_p : 1;
170 /* The ABI to use. */
181 /* MIPS ABI we are using for this output file. */
182 static enum mips_abi_level mips_abi = NO_ABI;
184 /* Whether or not we have code that can call pic code. */
185 int mips_abicalls = FALSE;
187 /* Whether or not we have code which can be put into a shared
189 static bfd_boolean mips_in_shared = TRUE;
191 /* This is the set of options which may be modified by the .set
192 pseudo-op. We use a struct so that .set push and .set pop are more
195 struct mips_set_options
197 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
198 if it has not been initialized. Changed by `.set mipsN', and the
199 -mipsN command line option, and the default CPU. */
201 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
202 <asename>', by command line options, and based on the default
205 /* Whether we are assembling for the mips16 processor. 0 if we are
206 not, 1 if we are, and -1 if the value has not been initialized.
207 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
208 -nomips16 command line options, and the default CPU. */
210 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
211 1 if we are, and -1 if the value has not been initialized. Changed
212 by `.set micromips' and `.set nomicromips', and the -mmicromips
213 and -mno-micromips command line options, and the default CPU. */
215 /* Non-zero if we should not reorder instructions. Changed by `.set
216 reorder' and `.set noreorder'. */
218 /* Non-zero if we should not permit the register designated "assembler
219 temporary" to be used in instructions. The value is the register
220 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
221 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
223 /* Non-zero if we should warn when a macro instruction expands into
224 more than one machine instruction. Changed by `.set nomacro' and
226 int warn_about_macros;
227 /* Non-zero if we should not move instructions. Changed by `.set
228 move', `.set volatile', `.set nomove', and `.set novolatile'. */
230 /* Non-zero if we should not optimize branches by moving the target
231 of the branch into the delay slot. Actually, we don't perform
232 this optimization anyhow. Changed by `.set bopt' and `.set
235 /* Non-zero if we should not autoextend mips16 instructions.
236 Changed by `.set autoextend' and `.set noautoextend'. */
238 /* True if we should only emit 32-bit microMIPS instructions.
239 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
240 and -mno-insn32 command line options. */
242 /* Restrict general purpose registers and floating point registers
243 to 32 bit. This is initially determined when -mgp32 or -mfp32
244 is passed but can changed if the assembler code uses .set mipsN. */
247 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
248 command line option, and the default CPU. */
250 /* True if ".set sym32" is in effect. */
252 /* True if floating-point operations are not allowed. Changed by .set
253 softfloat or .set hardfloat, by command line options -msoft-float or
254 -mhard-float. The default is false. */
255 bfd_boolean soft_float;
257 /* True if only single-precision floating-point operations are allowed.
258 Changed by .set singlefloat or .set doublefloat, command-line options
259 -msingle-float or -mdouble-float. The default is false. */
260 bfd_boolean single_float;
262 /* 1 if single-precision operations on odd-numbered registers are
267 /* Specifies whether module level options have been checked yet. */
268 static bfd_boolean file_mips_opts_checked = FALSE;
270 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
271 value has not been initialized. Changed by `.nan legacy' and
272 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
273 options, and the default CPU. */
274 static int mips_nan2008 = -1;
276 /* This is the struct we use to hold the module level set of options.
277 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
278 fp fields to -1 to indicate that they have not been initialized. */
280 static struct mips_set_options file_mips_opts =
282 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
283 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
284 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
285 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
286 /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1
289 /* This is similar to file_mips_opts, but for the current set of options. */
291 static struct mips_set_options mips_opts =
293 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
294 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
295 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
296 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
297 /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1
300 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
301 static unsigned int file_ase_explicit;
303 /* These variables are filled in with the masks of registers used.
304 The object format code reads them and puts them in the appropriate
306 unsigned long mips_gprmask;
307 unsigned long mips_cprmask[4];
309 /* True if any MIPS16 code was produced. */
310 static int file_ase_mips16;
312 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
313 || mips_opts.isa == ISA_MIPS32R2 \
314 || mips_opts.isa == ISA_MIPS32R3 \
315 || mips_opts.isa == ISA_MIPS32R5 \
316 || mips_opts.isa == ISA_MIPS64 \
317 || mips_opts.isa == ISA_MIPS64R2 \
318 || mips_opts.isa == ISA_MIPS64R3 \
319 || mips_opts.isa == ISA_MIPS64R5)
321 /* True if any microMIPS code was produced. */
322 static int file_ase_micromips;
324 /* True if we want to create R_MIPS_JALR for jalr $25. */
326 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
328 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
329 because there's no place for any addend, the only acceptable
330 expression is a bare symbol. */
331 #define MIPS_JALR_HINT_P(EXPR) \
332 (!HAVE_IN_PLACE_ADDENDS \
333 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
336 /* The argument of the -march= flag. The architecture we are assembling. */
337 static const char *mips_arch_string;
339 /* The argument of the -mtune= flag. The architecture for which we
341 static int mips_tune = CPU_UNKNOWN;
342 static const char *mips_tune_string;
344 /* True when generating 32-bit code for a 64-bit processor. */
345 static int mips_32bitmode = 0;
347 /* True if the given ABI requires 32-bit registers. */
348 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
350 /* Likewise 64-bit registers. */
351 #define ABI_NEEDS_64BIT_REGS(ABI) \
353 || (ABI) == N64_ABI \
356 #define ISA_IS_R6(ISA) \
357 ((ISA) == ISA_MIPS32R6 \
358 || (ISA) == ISA_MIPS64R6)
360 /* Return true if ISA supports 64 bit wide gp registers. */
361 #define ISA_HAS_64BIT_REGS(ISA) \
362 ((ISA) == ISA_MIPS3 \
363 || (ISA) == ISA_MIPS4 \
364 || (ISA) == ISA_MIPS5 \
365 || (ISA) == ISA_MIPS64 \
366 || (ISA) == ISA_MIPS64R2 \
367 || (ISA) == ISA_MIPS64R3 \
368 || (ISA) == ISA_MIPS64R5 \
369 || (ISA) == ISA_MIPS64R6)
371 /* Return true if ISA supports 64 bit wide float registers. */
372 #define ISA_HAS_64BIT_FPRS(ISA) \
373 ((ISA) == ISA_MIPS3 \
374 || (ISA) == ISA_MIPS4 \
375 || (ISA) == ISA_MIPS5 \
376 || (ISA) == ISA_MIPS32R2 \
377 || (ISA) == ISA_MIPS32R3 \
378 || (ISA) == ISA_MIPS32R5 \
379 || (ISA) == ISA_MIPS32R6 \
380 || (ISA) == ISA_MIPS64 \
381 || (ISA) == ISA_MIPS64R2 \
382 || (ISA) == ISA_MIPS64R3 \
383 || (ISA) == ISA_MIPS64R5 \
384 || (ISA) == ISA_MIPS64R6)
386 /* Return true if ISA supports 64-bit right rotate (dror et al.)
388 #define ISA_HAS_DROR(ISA) \
389 ((ISA) == ISA_MIPS64R2 \
390 || (ISA) == ISA_MIPS64R3 \
391 || (ISA) == ISA_MIPS64R5 \
392 || (ISA) == ISA_MIPS64R6 \
393 || (mips_opts.micromips \
394 && ISA_HAS_64BIT_REGS (ISA)) \
397 /* Return true if ISA supports 32-bit right rotate (ror et al.)
399 #define ISA_HAS_ROR(ISA) \
400 ((ISA) == ISA_MIPS32R2 \
401 || (ISA) == ISA_MIPS32R3 \
402 || (ISA) == ISA_MIPS32R5 \
403 || (ISA) == ISA_MIPS32R6 \
404 || (ISA) == ISA_MIPS64R2 \
405 || (ISA) == ISA_MIPS64R3 \
406 || (ISA) == ISA_MIPS64R5 \
407 || (ISA) == ISA_MIPS64R6 \
408 || (mips_opts.ase & ASE_SMARTMIPS) \
409 || mips_opts.micromips \
412 /* Return true if ISA supports single-precision floats in odd registers. */
413 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
414 (((ISA) == ISA_MIPS32 \
415 || (ISA) == ISA_MIPS32R2 \
416 || (ISA) == ISA_MIPS32R3 \
417 || (ISA) == ISA_MIPS32R5 \
418 || (ISA) == ISA_MIPS32R6 \
419 || (ISA) == ISA_MIPS64 \
420 || (ISA) == ISA_MIPS64R2 \
421 || (ISA) == ISA_MIPS64R3 \
422 || (ISA) == ISA_MIPS64R5 \
423 || (ISA) == ISA_MIPS64R6 \
424 || (CPU) == CPU_R5900) \
425 && (CPU) != CPU_LOONGSON_3A)
427 /* Return true if ISA supports move to/from high part of a 64-bit
428 floating-point register. */
429 #define ISA_HAS_MXHC1(ISA) \
430 ((ISA) == ISA_MIPS32R2 \
431 || (ISA) == ISA_MIPS32R3 \
432 || (ISA) == ISA_MIPS32R5 \
433 || (ISA) == ISA_MIPS32R6 \
434 || (ISA) == ISA_MIPS64R2 \
435 || (ISA) == ISA_MIPS64R3 \
436 || (ISA) == ISA_MIPS64R5 \
437 || (ISA) == ISA_MIPS64R6)
439 /* Return true if ISA supports legacy NAN. */
440 #define ISA_HAS_LEGACY_NAN(ISA) \
441 ((ISA) == ISA_MIPS1 \
442 || (ISA) == ISA_MIPS2 \
443 || (ISA) == ISA_MIPS3 \
444 || (ISA) == ISA_MIPS4 \
445 || (ISA) == ISA_MIPS5 \
446 || (ISA) == ISA_MIPS32 \
447 || (ISA) == ISA_MIPS32R2 \
448 || (ISA) == ISA_MIPS32R3 \
449 || (ISA) == ISA_MIPS32R5 \
450 || (ISA) == ISA_MIPS64 \
451 || (ISA) == ISA_MIPS64R2 \
452 || (ISA) == ISA_MIPS64R3 \
453 || (ISA) == ISA_MIPS64R5)
456 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
461 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
465 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
467 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
469 /* True if relocations are stored in-place. */
470 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
472 /* The ABI-derived address size. */
473 #define HAVE_64BIT_ADDRESSES \
474 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
475 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
477 /* The size of symbolic constants (i.e., expressions of the form
478 "SYMBOL" or "SYMBOL + OFFSET"). */
479 #define HAVE_32BIT_SYMBOLS \
480 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
481 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
483 /* Addresses are loaded in different ways, depending on the address size
484 in use. The n32 ABI Documentation also mandates the use of additions
485 with overflow checking, but existing implementations don't follow it. */
486 #define ADDRESS_ADD_INSN \
487 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
489 #define ADDRESS_ADDI_INSN \
490 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
492 #define ADDRESS_LOAD_INSN \
493 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
495 #define ADDRESS_STORE_INSN \
496 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
498 /* Return true if the given CPU supports the MIPS16 ASE. */
499 #define CPU_HAS_MIPS16(cpu) \
500 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
501 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
503 /* Return true if the given CPU supports the microMIPS ASE. */
504 #define CPU_HAS_MICROMIPS(cpu) 0
506 /* True if CPU has a dror instruction. */
507 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
509 /* True if CPU has a ror instruction. */
510 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
512 /* True if CPU is in the Octeon family */
513 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
514 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
516 /* True if CPU has seq/sne and seqi/snei instructions. */
517 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
519 /* True, if CPU has support for ldc1 and sdc1. */
520 #define CPU_HAS_LDC1_SDC1(CPU) \
521 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
523 /* True if mflo and mfhi can be immediately followed by instructions
524 which write to the HI and LO registers.
526 According to MIPS specifications, MIPS ISAs I, II, and III need
527 (at least) two instructions between the reads of HI/LO and
528 instructions which write them, and later ISAs do not. Contradicting
529 the MIPS specifications, some MIPS IV processor user manuals (e.g.
530 the UM for the NEC Vr5000) document needing the instructions between
531 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
532 MIPS64 and later ISAs to have the interlocks, plus any specific
533 earlier-ISA CPUs for which CPU documentation declares that the
534 instructions are really interlocked. */
535 #define hilo_interlocks \
536 (mips_opts.isa == ISA_MIPS32 \
537 || mips_opts.isa == ISA_MIPS32R2 \
538 || mips_opts.isa == ISA_MIPS32R3 \
539 || mips_opts.isa == ISA_MIPS32R5 \
540 || mips_opts.isa == ISA_MIPS32R6 \
541 || mips_opts.isa == ISA_MIPS64 \
542 || mips_opts.isa == ISA_MIPS64R2 \
543 || mips_opts.isa == ISA_MIPS64R3 \
544 || mips_opts.isa == ISA_MIPS64R5 \
545 || mips_opts.isa == ISA_MIPS64R6 \
546 || mips_opts.arch == CPU_R4010 \
547 || mips_opts.arch == CPU_R5900 \
548 || mips_opts.arch == CPU_R10000 \
549 || mips_opts.arch == CPU_R12000 \
550 || mips_opts.arch == CPU_R14000 \
551 || mips_opts.arch == CPU_R16000 \
552 || mips_opts.arch == CPU_RM7000 \
553 || mips_opts.arch == CPU_VR5500 \
554 || mips_opts.micromips \
557 /* Whether the processor uses hardware interlocks to protect reads
558 from the GPRs after they are loaded from memory, and thus does not
559 require nops to be inserted. This applies to instructions marked
560 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
561 level I and microMIPS mode instructions are always interlocked. */
562 #define gpr_interlocks \
563 (mips_opts.isa != ISA_MIPS1 \
564 || mips_opts.arch == CPU_R3900 \
565 || mips_opts.arch == CPU_R5900 \
566 || mips_opts.micromips \
569 /* Whether the processor uses hardware interlocks to avoid delays
570 required by coprocessor instructions, and thus does not require
571 nops to be inserted. This applies to instructions marked
572 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
573 instructions marked INSN_WRITE_COND_CODE and ones marked
574 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
575 levels I, II, and III and microMIPS mode instructions are always
577 /* Itbl support may require additional care here. */
578 #define cop_interlocks \
579 ((mips_opts.isa != ISA_MIPS1 \
580 && mips_opts.isa != ISA_MIPS2 \
581 && mips_opts.isa != ISA_MIPS3) \
582 || mips_opts.arch == CPU_R4300 \
583 || mips_opts.micromips \
586 /* Whether the processor uses hardware interlocks to protect reads
587 from coprocessor registers after they are loaded from memory, and
588 thus does not require nops to be inserted. This applies to
589 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
590 requires at MIPS ISA level I and microMIPS mode instructions are
591 always interlocked. */
592 #define cop_mem_interlocks \
593 (mips_opts.isa != ISA_MIPS1 \
594 || mips_opts.micromips \
597 /* Is this a mfhi or mflo instruction? */
598 #define MF_HILO_INSN(PINFO) \
599 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
601 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
602 has been selected. This implies, in particular, that addresses of text
603 labels have their LSB set. */
604 #define HAVE_CODE_COMPRESSION \
605 ((mips_opts.mips16 | mips_opts.micromips) != 0)
607 /* The minimum and maximum signed values that can be stored in a GPR. */
608 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
609 #define GPR_SMIN (-GPR_SMAX - 1)
611 /* MIPS PIC level. */
613 enum mips_pic_level mips_pic;
615 /* 1 if we should generate 32 bit offsets from the $gp register in
616 SVR4_PIC mode. Currently has no meaning in other modes. */
617 static int mips_big_got = 0;
619 /* 1 if trap instructions should used for overflow rather than break
621 static int mips_trap = 0;
623 /* 1 if double width floating point constants should not be constructed
624 by assembling two single width halves into two single width floating
625 point registers which just happen to alias the double width destination
626 register. On some architectures this aliasing can be disabled by a bit
627 in the status register, and the setting of this bit cannot be determined
628 automatically at assemble time. */
629 static int mips_disable_float_construction;
631 /* Non-zero if any .set noreorder directives were used. */
633 static int mips_any_noreorder;
635 /* Non-zero if nops should be inserted when the register referenced in
636 an mfhi/mflo instruction is read in the next two instructions. */
637 static int mips_7000_hilo_fix;
639 /* The size of objects in the small data section. */
640 static unsigned int g_switch_value = 8;
641 /* Whether the -G option was used. */
642 static int g_switch_seen = 0;
647 /* If we can determine in advance that GP optimization won't be
648 possible, we can skip the relaxation stuff that tries to produce
649 GP-relative references. This makes delay slot optimization work
652 This function can only provide a guess, but it seems to work for
653 gcc output. It needs to guess right for gcc, otherwise gcc
654 will put what it thinks is a GP-relative instruction in a branch
657 I don't know if a fix is needed for the SVR4_PIC mode. I've only
658 fixed it for the non-PIC mode. KR 95/04/07 */
659 static int nopic_need_relax (symbolS *, int);
661 /* handle of the OPCODE hash table */
662 static struct hash_control *op_hash = NULL;
664 /* The opcode hash table we use for the mips16. */
665 static struct hash_control *mips16_op_hash = NULL;
667 /* The opcode hash table we use for the microMIPS ASE. */
668 static struct hash_control *micromips_op_hash = NULL;
670 /* This array holds the chars that always start a comment. If the
671 pre-processor is disabled, these aren't very useful */
672 const char comment_chars[] = "#";
674 /* This array holds the chars that only start a comment at the beginning of
675 a line. If the line seems to have the form '# 123 filename'
676 .line and .file directives will appear in the pre-processed output */
677 /* Note that input_file.c hand checks for '#' at the beginning of the
678 first line of the input file. This is because the compiler outputs
679 #NO_APP at the beginning of its output. */
680 /* Also note that C style comments are always supported. */
681 const char line_comment_chars[] = "#";
683 /* This array holds machine specific line separator characters. */
684 const char line_separator_chars[] = ";";
686 /* Chars that can be used to separate mant from exp in floating point nums */
687 const char EXP_CHARS[] = "eE";
689 /* Chars that mean this number is a floating point constant */
692 const char FLT_CHARS[] = "rRsSfFdDxXpP";
694 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
695 changed in read.c . Ideally it shouldn't have to know about it at all,
696 but nothing is ideal around here.
699 /* Types of printf format used for instruction-related error messages.
700 "I" means int ("%d") and "S" means string ("%s"). */
701 enum mips_insn_error_format {
707 /* Information about an error that was found while assembling the current
709 struct mips_insn_error {
710 /* We sometimes need to match an instruction against more than one
711 opcode table entry. Errors found during this matching are reported
712 against a particular syntactic argument rather than against the
713 instruction as a whole. We grade these messages so that errors
714 against argument N have a greater priority than an error against
715 any argument < N, since the former implies that arguments up to N
716 were acceptable and that the opcode entry was therefore a closer match.
717 If several matches report an error against the same argument,
718 we only use that error if it is the same in all cases.
720 min_argnum is the minimum argument number for which an error message
721 should be accepted. It is 0 if MSG is against the instruction as
725 /* The printf()-style message, including its format and arguments. */
726 enum mips_insn_error_format format;
734 /* The error that should be reported for the current instruction. */
735 static struct mips_insn_error insn_error;
737 static int auto_align = 1;
739 /* When outputting SVR4 PIC code, the assembler needs to know the
740 offset in the stack frame from which to restore the $gp register.
741 This is set by the .cprestore pseudo-op, and saved in this
743 static offsetT mips_cprestore_offset = -1;
745 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
746 more optimizations, it can use a register value instead of a memory-saved
747 offset and even an other register than $gp as global pointer. */
748 static offsetT mips_cpreturn_offset = -1;
749 static int mips_cpreturn_register = -1;
750 static int mips_gp_register = GP;
751 static int mips_gprel_offset = 0;
753 /* Whether mips_cprestore_offset has been set in the current function
754 (or whether it has already been warned about, if not). */
755 static int mips_cprestore_valid = 0;
757 /* This is the register which holds the stack frame, as set by the
758 .frame pseudo-op. This is needed to implement .cprestore. */
759 static int mips_frame_reg = SP;
761 /* Whether mips_frame_reg has been set in the current function
762 (or whether it has already been warned about, if not). */
763 static int mips_frame_reg_valid = 0;
765 /* To output NOP instructions correctly, we need to keep information
766 about the previous two instructions. */
768 /* Whether we are optimizing. The default value of 2 means to remove
769 unneeded NOPs and swap branch instructions when possible. A value
770 of 1 means to not swap branches. A value of 0 means to always
772 static int mips_optimize = 2;
774 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
775 equivalent to seeing no -g option at all. */
776 static int mips_debug = 0;
778 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
779 #define MAX_VR4130_NOPS 4
781 /* The maximum number of NOPs needed to fill delay slots. */
782 #define MAX_DELAY_NOPS 2
784 /* The maximum number of NOPs needed for any purpose. */
787 /* A list of previous instructions, with index 0 being the most recent.
788 We need to look back MAX_NOPS instructions when filling delay slots
789 or working around processor errata. We need to look back one
790 instruction further if we're thinking about using history[0] to
791 fill a branch delay slot. */
792 static struct mips_cl_insn history[1 + MAX_NOPS];
794 /* Arrays of operands for each instruction. */
795 #define MAX_OPERANDS 6
796 struct mips_operand_array {
797 const struct mips_operand *operand[MAX_OPERANDS];
799 static struct mips_operand_array *mips_operands;
800 static struct mips_operand_array *mips16_operands;
801 static struct mips_operand_array *micromips_operands;
803 /* Nop instructions used by emit_nop. */
804 static struct mips_cl_insn nop_insn;
805 static struct mips_cl_insn mips16_nop_insn;
806 static struct mips_cl_insn micromips_nop16_insn;
807 static struct mips_cl_insn micromips_nop32_insn;
809 /* The appropriate nop for the current mode. */
810 #define NOP_INSN (mips_opts.mips16 \
812 : (mips_opts.micromips \
813 ? (mips_opts.insn32 \
814 ? µmips_nop32_insn \
815 : µmips_nop16_insn) \
818 /* The size of NOP_INSN in bytes. */
819 #define NOP_INSN_SIZE ((mips_opts.mips16 \
820 || (mips_opts.micromips && !mips_opts.insn32)) \
823 /* If this is set, it points to a frag holding nop instructions which
824 were inserted before the start of a noreorder section. If those
825 nops turn out to be unnecessary, the size of the frag can be
827 static fragS *prev_nop_frag;
829 /* The number of nop instructions we created in prev_nop_frag. */
830 static int prev_nop_frag_holds;
832 /* The number of nop instructions that we know we need in
834 static int prev_nop_frag_required;
836 /* The number of instructions we've seen since prev_nop_frag. */
837 static int prev_nop_frag_since;
839 /* Relocations against symbols are sometimes done in two parts, with a HI
840 relocation and a LO relocation. Each relocation has only 16 bits of
841 space to store an addend. This means that in order for the linker to
842 handle carries correctly, it must be able to locate both the HI and
843 the LO relocation. This means that the relocations must appear in
844 order in the relocation table.
846 In order to implement this, we keep track of each unmatched HI
847 relocation. We then sort them so that they immediately precede the
848 corresponding LO relocation. */
853 struct mips_hi_fixup *next;
856 /* The section this fixup is in. */
860 /* The list of unmatched HI relocs. */
862 static struct mips_hi_fixup *mips_hi_fixup_list;
864 /* The frag containing the last explicit relocation operator.
865 Null if explicit relocations have not been used. */
867 static fragS *prev_reloc_op_frag;
869 /* Map mips16 register numbers to normal MIPS register numbers. */
871 static const unsigned int mips16_to_32_reg_map[] =
873 16, 17, 2, 3, 4, 5, 6, 7
876 /* Map microMIPS register numbers to normal MIPS register numbers. */
878 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
880 /* The microMIPS registers with type h. */
881 static const unsigned int micromips_to_32_reg_h_map1[] =
883 5, 5, 6, 4, 4, 4, 4, 4
885 static const unsigned int micromips_to_32_reg_h_map2[] =
887 6, 7, 7, 21, 22, 5, 6, 7
890 /* The microMIPS registers with type m. */
891 static const unsigned int micromips_to_32_reg_m_map[] =
893 0, 17, 2, 3, 16, 18, 19, 20
896 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
898 /* Classifies the kind of instructions we're interested in when
899 implementing -mfix-vr4120. */
900 enum fix_vr4120_class
908 NUM_FIX_VR4120_CLASSES
911 /* ...likewise -mfix-loongson2f-jump. */
912 static bfd_boolean mips_fix_loongson2f_jump;
914 /* ...likewise -mfix-loongson2f-nop. */
915 static bfd_boolean mips_fix_loongson2f_nop;
917 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
918 static bfd_boolean mips_fix_loongson2f;
920 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
921 there must be at least one other instruction between an instruction
922 of type X and an instruction of type Y. */
923 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
925 /* True if -mfix-vr4120 is in force. */
926 static int mips_fix_vr4120;
928 /* ...likewise -mfix-vr4130. */
929 static int mips_fix_vr4130;
931 /* ...likewise -mfix-24k. */
932 static int mips_fix_24k;
934 /* ...likewise -mfix-rm7000 */
935 static int mips_fix_rm7000;
937 /* ...likewise -mfix-cn63xxp1 */
938 static bfd_boolean mips_fix_cn63xxp1;
940 /* We don't relax branches by default, since this causes us to expand
941 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
942 fail to compute the offset before expanding the macro to the most
943 efficient expansion. */
945 static int mips_relax_branch;
947 /* TRUE if checks are suppressed for invalid branches between ISA modes.
948 Needed for broken assembly produced by some GCC versions and some
949 sloppy code out there, where branches to data labels are present. */
950 static bfd_boolean mips_ignore_branch_isa;
952 /* The expansion of many macros depends on the type of symbol that
953 they refer to. For example, when generating position-dependent code,
954 a macro that refers to a symbol may have two different expansions,
955 one which uses GP-relative addresses and one which uses absolute
956 addresses. When generating SVR4-style PIC, a macro may have
957 different expansions for local and global symbols.
959 We handle these situations by generating both sequences and putting
960 them in variant frags. In position-dependent code, the first sequence
961 will be the GP-relative one and the second sequence will be the
962 absolute one. In SVR4 PIC, the first sequence will be for global
963 symbols and the second will be for local symbols.
965 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
966 SECOND are the lengths of the two sequences in bytes. These fields
967 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
968 the subtype has the following flags:
971 Set if generating PIC code.
974 Set if it has been decided that we should use the second
975 sequence instead of the first.
978 Set in the first variant frag if the macro's second implementation
979 is longer than its first. This refers to the macro as a whole,
980 not an individual relaxation.
983 Set in the first variant frag if the macro appeared in a .set nomacro
984 block and if one alternative requires a warning but the other does not.
987 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
990 RELAX_DELAY_SLOT_16BIT
991 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
994 RELAX_DELAY_SLOT_SIZE_FIRST
995 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
996 the macro is of the wrong size for the branch delay slot.
998 RELAX_DELAY_SLOT_SIZE_SECOND
999 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
1000 the macro is of the wrong size for the branch delay slot.
1002 The frag's "opcode" points to the first fixup for relaxable code.
1004 Relaxable macros are generated using a sequence such as:
1006 relax_start (SYMBOL);
1007 ... generate first expansion ...
1009 ... generate second expansion ...
1012 The code and fixups for the unwanted alternative are discarded
1013 by md_convert_frag. */
1014 #define RELAX_ENCODE(FIRST, SECOND, PIC) \
1015 (((FIRST) << 8) | (SECOND) | ((PIC) ? 0x10000 : 0))
1017 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1018 #define RELAX_SECOND(X) ((X) & 0xff)
1019 #define RELAX_PIC(X) (((X) & 0x10000) != 0)
1020 #define RELAX_USE_SECOND 0x20000
1021 #define RELAX_SECOND_LONGER 0x40000
1022 #define RELAX_NOMACRO 0x80000
1023 #define RELAX_DELAY_SLOT 0x100000
1024 #define RELAX_DELAY_SLOT_16BIT 0x200000
1025 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x400000
1026 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x800000
1028 /* Branch without likely bit. If label is out of range, we turn:
1030 beq reg1, reg2, label
1040 with the following opcode replacements:
1047 bltzal <-> bgezal (with jal label instead of j label)
1049 Even though keeping the delay slot instruction in the delay slot of
1050 the branch would be more efficient, it would be very tricky to do
1051 correctly, because we'd have to introduce a variable frag *after*
1052 the delay slot instruction, and expand that instead. Let's do it
1053 the easy way for now, even if the branch-not-taken case now costs
1054 one additional instruction. Out-of-range branches are not supposed
1055 to be common, anyway.
1057 Branch likely. If label is out of range, we turn:
1059 beql reg1, reg2, label
1060 delay slot (annulled if branch not taken)
1069 delay slot (executed only if branch taken)
1072 It would be possible to generate a shorter sequence by losing the
1073 likely bit, generating something like:
1078 delay slot (executed only if branch taken)
1090 bltzall -> bgezal (with jal label instead of j label)
1091 bgezall -> bltzal (ditto)
1094 but it's not clear that it would actually improve performance. */
1095 #define RELAX_BRANCH_ENCODE(at, pic, \
1096 uncond, likely, link, toofar) \
1097 ((relax_substateT) \
1100 | ((pic) ? 0x20 : 0) \
1101 | ((toofar) ? 0x40 : 0) \
1102 | ((link) ? 0x80 : 0) \
1103 | ((likely) ? 0x100 : 0) \
1104 | ((uncond) ? 0x200 : 0)))
1105 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1106 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x200) != 0)
1107 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x100) != 0)
1108 #define RELAX_BRANCH_LINK(i) (((i) & 0x80) != 0)
1109 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x40) != 0)
1110 #define RELAX_BRANCH_PIC(i) (((i) & 0x20) != 0)
1111 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1113 /* For mips16 code, we use an entirely different form of relaxation.
1114 mips16 supports two versions of most instructions which take
1115 immediate values: a small one which takes some small value, and a
1116 larger one which takes a 16 bit value. Since branches also follow
1117 this pattern, relaxing these values is required.
1119 We can assemble both mips16 and normal MIPS code in a single
1120 object. Therefore, we need to support this type of relaxation at
1121 the same time that we support the relaxation described above. We
1122 use the high bit of the subtype field to distinguish these cases.
1124 The information we store for this type of relaxation is the
1125 argument code found in the opcode file for this relocation, whether
1126 the user explicitly requested a small or extended form, and whether
1127 the relocation is in a jump or jal delay slot. That tells us the
1128 size of the value, and how it should be stored. We also store
1129 whether the fragment is considered to be extended or not. We also
1130 store whether this is known to be a branch to a different section,
1131 whether we have tried to relax this frag yet, and whether we have
1132 ever extended a PC relative fragment because of a shift count. */
1133 #define RELAX_MIPS16_ENCODE(type, e2, pic, sym32, nomacro, \
1138 | ((e2) ? 0x100 : 0) \
1139 | ((pic) ? 0x200 : 0) \
1140 | ((sym32) ? 0x400 : 0) \
1141 | ((nomacro) ? 0x800 : 0) \
1142 | ((small) ? 0x1000 : 0) \
1143 | ((ext) ? 0x2000 : 0) \
1144 | ((dslot) ? 0x4000 : 0) \
1145 | ((jal_dslot) ? 0x8000 : 0))
1147 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1148 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1149 #define RELAX_MIPS16_E2(i) (((i) & 0x100) != 0)
1150 #define RELAX_MIPS16_PIC(i) (((i) & 0x200) != 0)
1151 #define RELAX_MIPS16_SYM32(i) (((i) & 0x400) != 0)
1152 #define RELAX_MIPS16_NOMACRO(i) (((i) & 0x800) != 0)
1153 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x1000) != 0)
1154 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x2000) != 0)
1155 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x4000) != 0)
1156 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x8000) != 0)
1158 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x10000) != 0)
1159 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x10000)
1160 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) & ~0x10000)
1161 #define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x20000) != 0)
1162 #define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x20000)
1163 #define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x20000)
1164 #define RELAX_MIPS16_MACRO(i) (((i) & 0x40000) != 0)
1165 #define RELAX_MIPS16_MARK_MACRO(i) ((i) | 0x40000)
1166 #define RELAX_MIPS16_CLEAR_MACRO(i) ((i) & ~0x40000)
1168 /* For microMIPS code, we use relaxation similar to one we use for
1169 MIPS16 code. Some instructions that take immediate values support
1170 two encodings: a small one which takes some small value, and a
1171 larger one which takes a 16 bit value. As some branches also follow
1172 this pattern, relaxing these values is required.
1174 We can assemble both microMIPS and normal MIPS code in a single
1175 object. Therefore, we need to support this type of relaxation at
1176 the same time that we support the relaxation described above. We
1177 use one of the high bits of the subtype field to distinguish these
1180 The information we store for this type of relaxation is the argument
1181 code found in the opcode file for this relocation, the register
1182 selected as the assembler temporary, whether in the 32-bit
1183 instruction mode, whether the branch is unconditional, whether it is
1184 compact, whether there is no delay-slot instruction available to fill
1185 in, whether it stores the link address implicitly in $ra, whether
1186 relaxation of out-of-range 32-bit branches to a sequence of
1187 instructions is enabled, and whether the displacement of a branch is
1188 too large to fit as an immediate argument of a 16-bit and a 32-bit
1189 branch, respectively. */
1190 #define RELAX_MICROMIPS_ENCODE(type, at, insn32, pic, \
1191 uncond, compact, link, nods, \
1192 relax32, toofar16, toofar32) \
1195 | (((at) & 0x1f) << 8) \
1196 | ((insn32) ? 0x2000 : 0) \
1197 | ((pic) ? 0x4000 : 0) \
1198 | ((uncond) ? 0x8000 : 0) \
1199 | ((compact) ? 0x10000 : 0) \
1200 | ((link) ? 0x20000 : 0) \
1201 | ((nods) ? 0x40000 : 0) \
1202 | ((relax32) ? 0x80000 : 0) \
1203 | ((toofar16) ? 0x100000 : 0) \
1204 | ((toofar32) ? 0x200000 : 0))
1205 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1206 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1207 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1208 #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0)
1209 #define RELAX_MICROMIPS_PIC(i) (((i) & 0x4000) != 0)
1210 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x8000) != 0)
1211 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x10000) != 0)
1212 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x20000) != 0)
1213 #define RELAX_MICROMIPS_NODS(i) (((i) & 0x40000) != 0)
1214 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x80000) != 0)
1216 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x100000) != 0)
1217 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x100000)
1218 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x100000)
1219 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x200000) != 0)
1220 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x200000)
1221 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x200000)
1223 /* Sign-extend 16-bit value X. */
1224 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1226 /* Is the given value a sign-extended 32-bit value? */
1227 #define IS_SEXT_32BIT_NUM(x) \
1228 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1229 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1231 /* Is the given value a sign-extended 16-bit value? */
1232 #define IS_SEXT_16BIT_NUM(x) \
1233 (((x) &~ (offsetT) 0x7fff) == 0 \
1234 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1236 /* Is the given value a sign-extended 12-bit value? */
1237 #define IS_SEXT_12BIT_NUM(x) \
1238 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1240 /* Is the given value a sign-extended 9-bit value? */
1241 #define IS_SEXT_9BIT_NUM(x) \
1242 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1244 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1245 #define IS_ZEXT_32BIT_NUM(x) \
1246 (((x) &~ (offsetT) 0xffffffff) == 0 \
1247 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1249 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1251 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1252 (((STRUCT) >> (SHIFT)) & (MASK))
1254 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1255 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1257 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1258 : EXTRACT_BITS ((INSN).insn_opcode, \
1259 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1260 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1261 EXTRACT_BITS ((INSN).insn_opcode, \
1262 MIPS16OP_MASK_##FIELD, \
1263 MIPS16OP_SH_##FIELD)
1265 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1266 #define MIPS16_EXTEND (0xf000U << 16)
1268 /* Whether or not we are emitting a branch-likely macro. */
1269 static bfd_boolean emit_branch_likely_macro = FALSE;
1271 /* Global variables used when generating relaxable macros. See the
1272 comment above RELAX_ENCODE for more details about how relaxation
1275 /* 0 if we're not emitting a relaxable macro.
1276 1 if we're emitting the first of the two relaxation alternatives.
1277 2 if we're emitting the second alternative. */
1280 /* The first relaxable fixup in the current frag. (In other words,
1281 the first fixup that refers to relaxable code.) */
1284 /* sizes[0] says how many bytes of the first alternative are stored in
1285 the current frag. Likewise sizes[1] for the second alternative. */
1286 unsigned int sizes[2];
1288 /* The symbol on which the choice of sequence depends. */
1292 /* Global variables used to decide whether a macro needs a warning. */
1294 /* True if the macro is in a branch delay slot. */
1295 bfd_boolean delay_slot_p;
1297 /* Set to the length in bytes required if the macro is in a delay slot
1298 that requires a specific length of instruction, otherwise zero. */
1299 unsigned int delay_slot_length;
1301 /* For relaxable macros, sizes[0] is the length of the first alternative
1302 in bytes and sizes[1] is the length of the second alternative.
1303 For non-relaxable macros, both elements give the length of the
1305 unsigned int sizes[2];
1307 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1308 instruction of the first alternative in bytes and first_insn_sizes[1]
1309 is the length of the first instruction of the second alternative.
1310 For non-relaxable macros, both elements give the length of the first
1311 instruction in bytes.
1313 Set to zero if we haven't yet seen the first instruction. */
1314 unsigned int first_insn_sizes[2];
1316 /* For relaxable macros, insns[0] is the number of instructions for the
1317 first alternative and insns[1] is the number of instructions for the
1320 For non-relaxable macros, both elements give the number of
1321 instructions for the macro. */
1322 unsigned int insns[2];
1324 /* The first variant frag for this macro. */
1326 } mips_macro_warning;
1328 /* Prototypes for static functions. */
1330 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1332 static void append_insn
1333 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1334 bfd_boolean expansionp);
1335 static void mips_no_prev_insn (void);
1336 static void macro_build (expressionS *, const char *, const char *, ...);
1337 static void mips16_macro_build
1338 (expressionS *, const char *, const char *, va_list *);
1339 static void load_register (int, expressionS *, int);
1340 static void macro_start (void);
1341 static void macro_end (void);
1342 static void macro (struct mips_cl_insn *ip, char *str);
1343 static void mips16_macro (struct mips_cl_insn * ip);
1344 static void mips_ip (char *str, struct mips_cl_insn * ip);
1345 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1346 static unsigned long mips16_immed_extend (offsetT, unsigned int);
1347 static void mips16_immed
1348 (const char *, unsigned int, int, bfd_reloc_code_real_type, offsetT,
1349 unsigned int, unsigned long *);
1350 static size_t my_getSmallExpression
1351 (expressionS *, bfd_reloc_code_real_type *, char *);
1352 static void my_getExpression (expressionS *, char *);
1353 static void s_align (int);
1354 static void s_change_sec (int);
1355 static void s_change_section (int);
1356 static void s_cons (int);
1357 static void s_float_cons (int);
1358 static void s_mips_globl (int);
1359 static void s_option (int);
1360 static void s_mipsset (int);
1361 static void s_abicalls (int);
1362 static void s_cpload (int);
1363 static void s_cpsetup (int);
1364 static void s_cplocal (int);
1365 static void s_cprestore (int);
1366 static void s_cpreturn (int);
1367 static void s_dtprelword (int);
1368 static void s_dtpreldword (int);
1369 static void s_tprelword (int);
1370 static void s_tpreldword (int);
1371 static void s_gpvalue (int);
1372 static void s_gpword (int);
1373 static void s_gpdword (int);
1374 static void s_ehword (int);
1375 static void s_cpadd (int);
1376 static void s_insn (int);
1377 static void s_nan (int);
1378 static void s_module (int);
1379 static void s_mips_ent (int);
1380 static void s_mips_end (int);
1381 static void s_mips_frame (int);
1382 static void s_mips_mask (int reg_type);
1383 static void s_mips_stab (int);
1384 static void s_mips_weakext (int);
1385 static void s_mips_file (int);
1386 static void s_mips_loc (int);
1387 static bfd_boolean pic_need_relax (symbolS *);
1388 static int relaxed_branch_length (fragS *, asection *, int);
1389 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1390 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1391 static void file_mips_check_options (void);
1393 /* Table and functions used to map between CPU/ISA names, and
1394 ISA levels, and CPU numbers. */
1396 struct mips_cpu_info
1398 const char *name; /* CPU or ISA name. */
1399 int flags; /* MIPS_CPU_* flags. */
1400 int ase; /* Set of ASEs implemented by the CPU. */
1401 int isa; /* ISA level. */
1402 int cpu; /* CPU number (default CPU if ISA). */
1405 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1407 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1408 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1409 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1411 /* Command-line options. */
1412 const char *md_shortopts = "O::g::G:";
1416 OPTION_MARCH = OPTION_MD_BASE,
1448 OPTION_NO_SMARTMIPS,
1458 OPTION_NO_MICROMIPS,
1471 OPTION_M7000_HILO_FIX,
1472 OPTION_MNO_7000_HILO_FIX,
1476 OPTION_NO_FIX_RM7000,
1477 OPTION_FIX_LOONGSON2F_JUMP,
1478 OPTION_NO_FIX_LOONGSON2F_JUMP,
1479 OPTION_FIX_LOONGSON2F_NOP,
1480 OPTION_NO_FIX_LOONGSON2F_NOP,
1482 OPTION_NO_FIX_VR4120,
1484 OPTION_NO_FIX_VR4130,
1485 OPTION_FIX_CN63XXP1,
1486 OPTION_NO_FIX_CN63XXP1,
1493 OPTION_CONSTRUCT_FLOATS,
1494 OPTION_NO_CONSTRUCT_FLOATS,
1498 OPTION_RELAX_BRANCH,
1499 OPTION_NO_RELAX_BRANCH,
1500 OPTION_IGNORE_BRANCH_ISA,
1501 OPTION_NO_IGNORE_BRANCH_ISA,
1510 OPTION_SINGLE_FLOAT,
1511 OPTION_DOUBLE_FLOAT,
1524 OPTION_MVXWORKS_PIC,
1527 OPTION_NO_ODD_SPREG,
1531 struct option md_longopts[] =
1533 /* Options which specify architecture. */
1534 {"march", required_argument, NULL, OPTION_MARCH},
1535 {"mtune", required_argument, NULL, OPTION_MTUNE},
1536 {"mips0", no_argument, NULL, OPTION_MIPS1},
1537 {"mips1", no_argument, NULL, OPTION_MIPS1},
1538 {"mips2", no_argument, NULL, OPTION_MIPS2},
1539 {"mips3", no_argument, NULL, OPTION_MIPS3},
1540 {"mips4", no_argument, NULL, OPTION_MIPS4},
1541 {"mips5", no_argument, NULL, OPTION_MIPS5},
1542 {"mips32", no_argument, NULL, OPTION_MIPS32},
1543 {"mips64", no_argument, NULL, OPTION_MIPS64},
1544 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
1545 {"mips32r3", no_argument, NULL, OPTION_MIPS32R3},
1546 {"mips32r5", no_argument, NULL, OPTION_MIPS32R5},
1547 {"mips32r6", no_argument, NULL, OPTION_MIPS32R6},
1548 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
1549 {"mips64r3", no_argument, NULL, OPTION_MIPS64R3},
1550 {"mips64r5", no_argument, NULL, OPTION_MIPS64R5},
1551 {"mips64r6", no_argument, NULL, OPTION_MIPS64R6},
1553 /* Options which specify Application Specific Extensions (ASEs). */
1554 {"mips16", no_argument, NULL, OPTION_MIPS16},
1555 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
1556 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
1557 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
1558 {"mdmx", no_argument, NULL, OPTION_MDMX},
1559 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
1560 {"mdsp", no_argument, NULL, OPTION_DSP},
1561 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
1562 {"mmt", no_argument, NULL, OPTION_MT},
1563 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
1564 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
1565 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
1566 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
1567 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
1568 {"mdspr3", no_argument, NULL, OPTION_DSPR3},
1569 {"mno-dspr3", no_argument, NULL, OPTION_NO_DSPR3},
1570 {"meva", no_argument, NULL, OPTION_EVA},
1571 {"mno-eva", no_argument, NULL, OPTION_NO_EVA},
1572 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
1573 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
1574 {"mmcu", no_argument, NULL, OPTION_MCU},
1575 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
1576 {"mvirt", no_argument, NULL, OPTION_VIRT},
1577 {"mno-virt", no_argument, NULL, OPTION_NO_VIRT},
1578 {"mmsa", no_argument, NULL, OPTION_MSA},
1579 {"mno-msa", no_argument, NULL, OPTION_NO_MSA},
1580 {"mxpa", no_argument, NULL, OPTION_XPA},
1581 {"mno-xpa", no_argument, NULL, OPTION_NO_XPA},
1582 {"mmips16e2", no_argument, NULL, OPTION_MIPS16E2},
1583 {"mno-mips16e2", no_argument, NULL, OPTION_NO_MIPS16E2},
1585 /* Old-style architecture options. Don't add more of these. */
1586 {"m4650", no_argument, NULL, OPTION_M4650},
1587 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
1588 {"m4010", no_argument, NULL, OPTION_M4010},
1589 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
1590 {"m4100", no_argument, NULL, OPTION_M4100},
1591 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
1592 {"m3900", no_argument, NULL, OPTION_M3900},
1593 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
1595 /* Options which enable bug fixes. */
1596 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
1597 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1598 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1599 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
1600 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
1601 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
1602 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
1603 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
1604 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
1605 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
1606 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
1607 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
1608 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
1609 {"mfix-rm7000", no_argument, NULL, OPTION_FIX_RM7000},
1610 {"mno-fix-rm7000", no_argument, NULL, OPTION_NO_FIX_RM7000},
1611 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
1612 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
1614 /* Miscellaneous options. */
1615 {"trap", no_argument, NULL, OPTION_TRAP},
1616 {"no-break", no_argument, NULL, OPTION_TRAP},
1617 {"break", no_argument, NULL, OPTION_BREAK},
1618 {"no-trap", no_argument, NULL, OPTION_BREAK},
1619 {"EB", no_argument, NULL, OPTION_EB},
1620 {"EL", no_argument, NULL, OPTION_EL},
1621 {"mfp32", no_argument, NULL, OPTION_FP32},
1622 {"mgp32", no_argument, NULL, OPTION_GP32},
1623 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
1624 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
1625 {"mfp64", no_argument, NULL, OPTION_FP64},
1626 {"mfpxx", no_argument, NULL, OPTION_FPXX},
1627 {"mgp64", no_argument, NULL, OPTION_GP64},
1628 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
1629 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
1630 {"mignore-branch-isa", no_argument, NULL, OPTION_IGNORE_BRANCH_ISA},
1631 {"mno-ignore-branch-isa", no_argument, NULL, OPTION_NO_IGNORE_BRANCH_ISA},
1632 {"minsn32", no_argument, NULL, OPTION_INSN32},
1633 {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32},
1634 {"mshared", no_argument, NULL, OPTION_MSHARED},
1635 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
1636 {"msym32", no_argument, NULL, OPTION_MSYM32},
1637 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
1638 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
1639 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
1640 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
1641 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
1642 {"modd-spreg", no_argument, NULL, OPTION_ODD_SPREG},
1643 {"mno-odd-spreg", no_argument, NULL, OPTION_NO_ODD_SPREG},
1645 /* Strictly speaking this next option is ELF specific,
1646 but we allow it for other ports as well in order to
1647 make testing easier. */
1648 {"32", no_argument, NULL, OPTION_32},
1650 /* ELF-specific options. */
1651 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
1652 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
1653 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
1654 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
1655 {"xgot", no_argument, NULL, OPTION_XGOT},
1656 {"mabi", required_argument, NULL, OPTION_MABI},
1657 {"n32", no_argument, NULL, OPTION_N32},
1658 {"64", no_argument, NULL, OPTION_64},
1659 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
1660 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
1661 {"mpdr", no_argument, NULL, OPTION_PDR},
1662 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
1663 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
1664 {"mnan", required_argument, NULL, OPTION_NAN},
1666 {NULL, no_argument, NULL, 0}
1668 size_t md_longopts_size = sizeof (md_longopts);
1670 /* Information about either an Application Specific Extension or an
1671 optional architecture feature that, for simplicity, we treat in the
1672 same way as an ASE. */
1675 /* The name of the ASE, used in both the command-line and .set options. */
1678 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1679 and 64-bit architectures, the flags here refer to the subset that
1680 is available on both. */
1683 /* The ASE_* flag used for instructions that are available on 64-bit
1684 architectures but that are not included in FLAGS. */
1685 unsigned int flags64;
1687 /* The command-line options that turn the ASE on and off. */
1691 /* The minimum required architecture revisions for MIPS32, MIPS64,
1692 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1695 int micromips32_rev;
1696 int micromips64_rev;
1698 /* The architecture where the ASE was removed or -1 if the extension has not
1703 /* A table of all supported ASEs. */
1704 static const struct mips_ase mips_ases[] = {
1705 { "dsp", ASE_DSP, ASE_DSP64,
1706 OPTION_DSP, OPTION_NO_DSP,
1710 { "dspr2", ASE_DSP | ASE_DSPR2, 0,
1711 OPTION_DSPR2, OPTION_NO_DSPR2,
1715 { "dspr3", ASE_DSP | ASE_DSPR2 | ASE_DSPR3, 0,
1716 OPTION_DSPR3, OPTION_NO_DSPR3,
1720 { "eva", ASE_EVA, 0,
1721 OPTION_EVA, OPTION_NO_EVA,
1725 { "mcu", ASE_MCU, 0,
1726 OPTION_MCU, OPTION_NO_MCU,
1730 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1731 { "mdmx", ASE_MDMX, 0,
1732 OPTION_MDMX, OPTION_NO_MDMX,
1736 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1737 { "mips3d", ASE_MIPS3D, 0,
1738 OPTION_MIPS3D, OPTION_NO_MIPS3D,
1743 OPTION_MT, OPTION_NO_MT,
1747 { "smartmips", ASE_SMARTMIPS, 0,
1748 OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS,
1752 { "virt", ASE_VIRT, ASE_VIRT64,
1753 OPTION_VIRT, OPTION_NO_VIRT,
1757 { "msa", ASE_MSA, ASE_MSA64,
1758 OPTION_MSA, OPTION_NO_MSA,
1762 { "xpa", ASE_XPA, 0,
1763 OPTION_XPA, OPTION_NO_XPA,
1767 { "mips16e2", ASE_MIPS16E2, 0,
1768 OPTION_MIPS16E2, OPTION_NO_MIPS16E2,
1773 /* The set of ASEs that require -mfp64. */
1774 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
1776 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1777 static const unsigned int mips_ase_groups[] = {
1778 ASE_DSP | ASE_DSPR2 | ASE_DSPR3
1783 The following pseudo-ops from the Kane and Heinrich MIPS book
1784 should be defined here, but are currently unsupported: .alias,
1785 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1787 The following pseudo-ops from the Kane and Heinrich MIPS book are
1788 specific to the type of debugging information being generated, and
1789 should be defined by the object format: .aent, .begin, .bend,
1790 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1793 The following pseudo-ops from the Kane and Heinrich MIPS book are
1794 not MIPS CPU specific, but are also not specific to the object file
1795 format. This file is probably the best place to define them, but
1796 they are not currently supported: .asm0, .endr, .lab, .struct. */
1798 static const pseudo_typeS mips_pseudo_table[] =
1800 /* MIPS specific pseudo-ops. */
1801 {"option", s_option, 0},
1802 {"set", s_mipsset, 0},
1803 {"rdata", s_change_sec, 'r'},
1804 {"sdata", s_change_sec, 's'},
1805 {"livereg", s_ignore, 0},
1806 {"abicalls", s_abicalls, 0},
1807 {"cpload", s_cpload, 0},
1808 {"cpsetup", s_cpsetup, 0},
1809 {"cplocal", s_cplocal, 0},
1810 {"cprestore", s_cprestore, 0},
1811 {"cpreturn", s_cpreturn, 0},
1812 {"dtprelword", s_dtprelword, 0},
1813 {"dtpreldword", s_dtpreldword, 0},
1814 {"tprelword", s_tprelword, 0},
1815 {"tpreldword", s_tpreldword, 0},
1816 {"gpvalue", s_gpvalue, 0},
1817 {"gpword", s_gpword, 0},
1818 {"gpdword", s_gpdword, 0},
1819 {"ehword", s_ehword, 0},
1820 {"cpadd", s_cpadd, 0},
1821 {"insn", s_insn, 0},
1823 {"module", s_module, 0},
1825 /* Relatively generic pseudo-ops that happen to be used on MIPS
1827 {"asciiz", stringer, 8 + 1},
1828 {"bss", s_change_sec, 'b'},
1830 {"half", s_cons, 1},
1831 {"dword", s_cons, 3},
1832 {"weakext", s_mips_weakext, 0},
1833 {"origin", s_org, 0},
1834 {"repeat", s_rept, 0},
1836 /* For MIPS this is non-standard, but we define it for consistency. */
1837 {"sbss", s_change_sec, 'B'},
1839 /* These pseudo-ops are defined in read.c, but must be overridden
1840 here for one reason or another. */
1841 {"align", s_align, 0},
1842 {"byte", s_cons, 0},
1843 {"data", s_change_sec, 'd'},
1844 {"double", s_float_cons, 'd'},
1845 {"float", s_float_cons, 'f'},
1846 {"globl", s_mips_globl, 0},
1847 {"global", s_mips_globl, 0},
1848 {"hword", s_cons, 1},
1850 {"long", s_cons, 2},
1851 {"octa", s_cons, 4},
1852 {"quad", s_cons, 3},
1853 {"section", s_change_section, 0},
1854 {"short", s_cons, 1},
1855 {"single", s_float_cons, 'f'},
1856 {"stabd", s_mips_stab, 'd'},
1857 {"stabn", s_mips_stab, 'n'},
1858 {"stabs", s_mips_stab, 's'},
1859 {"text", s_change_sec, 't'},
1860 {"word", s_cons, 2},
1862 { "extern", ecoff_directive_extern, 0},
1867 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1869 /* These pseudo-ops should be defined by the object file format.
1870 However, a.out doesn't support them, so we have versions here. */
1871 {"aent", s_mips_ent, 1},
1872 {"bgnb", s_ignore, 0},
1873 {"end", s_mips_end, 0},
1874 {"endb", s_ignore, 0},
1875 {"ent", s_mips_ent, 0},
1876 {"file", s_mips_file, 0},
1877 {"fmask", s_mips_mask, 'F'},
1878 {"frame", s_mips_frame, 0},
1879 {"loc", s_mips_loc, 0},
1880 {"mask", s_mips_mask, 'R'},
1881 {"verstamp", s_ignore, 0},
1885 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1886 purpose of the `.dc.a' internal pseudo-op. */
1889 mips_address_bytes (void)
1891 file_mips_check_options ();
1892 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1895 extern void pop_insert (const pseudo_typeS *);
1898 mips_pop_insert (void)
1900 pop_insert (mips_pseudo_table);
1901 if (! ECOFF_DEBUGGING)
1902 pop_insert (mips_nonecoff_pseudo_table);
1905 /* Symbols labelling the current insn. */
1907 struct insn_label_list
1909 struct insn_label_list *next;
1913 static struct insn_label_list *free_insn_labels;
1914 #define label_list tc_segment_info_data.labels
1916 static void mips_clear_insn_labels (void);
1917 static void mips_mark_labels (void);
1918 static void mips_compressed_mark_labels (void);
1921 mips_clear_insn_labels (void)
1923 struct insn_label_list **pl;
1924 segment_info_type *si;
1928 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1931 si = seg_info (now_seg);
1932 *pl = si->label_list;
1933 si->label_list = NULL;
1937 /* Mark instruction labels in MIPS16/microMIPS mode. */
1940 mips_mark_labels (void)
1942 if (HAVE_CODE_COMPRESSION)
1943 mips_compressed_mark_labels ();
1946 static char *expr_end;
1948 /* An expression in a macro instruction. This is set by mips_ip and
1949 mips16_ip and when populated is always an O_constant. */
1951 static expressionS imm_expr;
1953 /* The relocatable field in an instruction and the relocs associated
1954 with it. These variables are used for instructions like LUI and
1955 JAL as well as true offsets. They are also used for address
1956 operands in macros. */
1958 static expressionS offset_expr;
1959 static bfd_reloc_code_real_type offset_reloc[3]
1960 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1962 /* This is set to the resulting size of the instruction to be produced
1963 by mips16_ip if an explicit extension is used or by mips_ip if an
1964 explicit size is supplied. */
1966 static unsigned int forced_insn_length;
1968 /* True if we are assembling an instruction. All dot symbols defined during
1969 this time should be treated as code labels. */
1971 static bfd_boolean mips_assembling_insn;
1973 /* The pdr segment for per procedure frame/regmask info. Not used for
1976 static segT pdr_seg;
1978 /* The default target format to use. */
1980 #if defined (TE_FreeBSD)
1981 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1982 #elif defined (TE_TMIPS)
1983 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1985 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1989 mips_target_format (void)
1991 switch (OUTPUT_FLAVOR)
1993 case bfd_target_elf_flavour:
1995 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1996 return (target_big_endian
1997 ? "elf32-bigmips-vxworks"
1998 : "elf32-littlemips-vxworks");
2000 return (target_big_endian
2001 ? (HAVE_64BIT_OBJECTS
2002 ? ELF_TARGET ("elf64-", "big")
2004 ? ELF_TARGET ("elf32-n", "big")
2005 : ELF_TARGET ("elf32-", "big")))
2006 : (HAVE_64BIT_OBJECTS
2007 ? ELF_TARGET ("elf64-", "little")
2009 ? ELF_TARGET ("elf32-n", "little")
2010 : ELF_TARGET ("elf32-", "little"))));
2017 /* Return the ISA revision that is currently in use, or 0 if we are
2018 generating code for MIPS V or below. */
2023 if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2)
2026 if (mips_opts.isa == ISA_MIPS32R3 || mips_opts.isa == ISA_MIPS64R3)
2029 if (mips_opts.isa == ISA_MIPS32R5 || mips_opts.isa == ISA_MIPS64R5)
2032 if (mips_opts.isa == ISA_MIPS32R6 || mips_opts.isa == ISA_MIPS64R6)
2035 /* microMIPS implies revision 2 or above. */
2036 if (mips_opts.micromips)
2039 if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64)
2045 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
2048 mips_ase_mask (unsigned int flags)
2052 for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++)
2053 if (flags & mips_ase_groups[i])
2054 flags |= mips_ase_groups[i];
2058 /* Check whether the current ISA supports ASE. Issue a warning if
2062 mips_check_isa_supports_ase (const struct mips_ase *ase)
2066 static unsigned int warned_isa;
2067 static unsigned int warned_fp32;
2069 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
2070 min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev;
2072 min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev;
2073 if ((min_rev < 0 || mips_isa_rev () < min_rev)
2074 && (warned_isa & ase->flags) != ase->flags)
2076 warned_isa |= ase->flags;
2077 base = mips_opts.micromips ? "microMIPS" : "MIPS";
2078 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
2080 as_warn (_("the %d-bit %s architecture does not support the"
2081 " `%s' extension"), size, base, ase->name);
2083 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
2084 ase->name, base, size, min_rev);
2086 else if ((ase->rem_rev > 0 && mips_isa_rev () >= ase->rem_rev)
2087 && (warned_isa & ase->flags) != ase->flags)
2089 warned_isa |= ase->flags;
2090 base = mips_opts.micromips ? "microMIPS" : "MIPS";
2091 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
2092 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2093 ase->name, base, size, ase->rem_rev);
2096 if ((ase->flags & FP64_ASES)
2097 && mips_opts.fp != 64
2098 && (warned_fp32 & ase->flags) != ase->flags)
2100 warned_fp32 |= ase->flags;
2101 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase->name);
2105 /* Check all enabled ASEs to see whether they are supported by the
2106 chosen architecture. */
2109 mips_check_isa_supports_ases (void)
2111 unsigned int i, mask;
2113 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2115 mask = mips_ase_mask (mips_ases[i].flags);
2116 if ((mips_opts.ase & mask) == mips_ases[i].flags)
2117 mips_check_isa_supports_ase (&mips_ases[i]);
2121 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2122 that were affected. */
2125 mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts,
2126 bfd_boolean enabled_p)
2130 mask = mips_ase_mask (ase->flags);
2133 /* Clear combination ASE flags, which need to be recalculated based on
2134 updated regular ASE settings. */
2135 opts->ase &= ~(ASE_MIPS16E2_MT | ASE_XPA_VIRT);
2138 opts->ase |= ase->flags;
2140 /* The Virtualization ASE has eXtended Physical Addressing (XPA)
2141 instructions which are only valid when both ASEs are enabled.
2142 This sets the ASE_XPA_VIRT flag when both ASEs are present. */
2143 if ((opts->ase & (ASE_XPA | ASE_VIRT)) == (ASE_XPA | ASE_VIRT))
2145 opts->ase |= ASE_XPA_VIRT;
2146 mask |= ASE_XPA_VIRT;
2148 if ((opts->ase & (ASE_MIPS16E2 | ASE_MT)) == (ASE_MIPS16E2 | ASE_MT))
2150 opts->ase |= ASE_MIPS16E2_MT;
2151 mask |= ASE_MIPS16E2_MT;
2157 /* Return the ASE called NAME, or null if none. */
2159 static const struct mips_ase *
2160 mips_lookup_ase (const char *name)
2164 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2165 if (strcmp (name, mips_ases[i].name) == 0)
2166 return &mips_ases[i];
2170 /* Return the length of a microMIPS instruction in bytes. If bits of
2171 the mask beyond the low 16 are 0, then it is a 16-bit instruction,
2172 otherwise it is a 32-bit instruction. */
2174 static inline unsigned int
2175 micromips_insn_length (const struct mips_opcode *mo)
2177 return mips_opcode_32bit_p (mo) ? 4 : 2;
2180 /* Return the length of MIPS16 instruction OPCODE. */
2182 static inline unsigned int
2183 mips16_opcode_length (unsigned long opcode)
2185 return (opcode >> 16) == 0 ? 2 : 4;
2188 /* Return the length of instruction INSN. */
2190 static inline unsigned int
2191 insn_length (const struct mips_cl_insn *insn)
2193 if (mips_opts.micromips)
2194 return micromips_insn_length (insn->insn_mo);
2195 else if (mips_opts.mips16)
2196 return mips16_opcode_length (insn->insn_opcode);
2201 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2204 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
2209 insn->insn_opcode = mo->match;
2212 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2213 insn->fixp[i] = NULL;
2214 insn->fixed_p = (mips_opts.noreorder > 0);
2215 insn->noreorder_p = (mips_opts.noreorder > 0);
2216 insn->mips16_absolute_jump_p = 0;
2217 insn->complete_p = 0;
2218 insn->cleared_p = 0;
2221 /* Get a list of all the operands in INSN. */
2223 static const struct mips_operand_array *
2224 insn_operands (const struct mips_cl_insn *insn)
2226 if (insn->insn_mo >= &mips_opcodes[0]
2227 && insn->insn_mo < &mips_opcodes[NUMOPCODES])
2228 return &mips_operands[insn->insn_mo - &mips_opcodes[0]];
2230 if (insn->insn_mo >= &mips16_opcodes[0]
2231 && insn->insn_mo < &mips16_opcodes[bfd_mips16_num_opcodes])
2232 return &mips16_operands[insn->insn_mo - &mips16_opcodes[0]];
2234 if (insn->insn_mo >= µmips_opcodes[0]
2235 && insn->insn_mo < µmips_opcodes[bfd_micromips_num_opcodes])
2236 return µmips_operands[insn->insn_mo - µmips_opcodes[0]];
2241 /* Get a description of operand OPNO of INSN. */
2243 static const struct mips_operand *
2244 insn_opno (const struct mips_cl_insn *insn, unsigned opno)
2246 const struct mips_operand_array *operands;
2248 operands = insn_operands (insn);
2249 if (opno >= MAX_OPERANDS || !operands->operand[opno])
2251 return operands->operand[opno];
2254 /* Install UVAL as the value of OPERAND in INSN. */
2257 insn_insert_operand (struct mips_cl_insn *insn,
2258 const struct mips_operand *operand, unsigned int uval)
2260 if (mips_opts.mips16
2261 && operand->type == OP_INT && operand->lsb == 0
2262 && mips_opcode_32bit_p (insn->insn_mo))
2263 insn->insn_opcode |= mips16_immed_extend (uval, operand->size);
2265 insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval);
2268 /* Extract the value of OPERAND from INSN. */
2270 static inline unsigned
2271 insn_extract_operand (const struct mips_cl_insn *insn,
2272 const struct mips_operand *operand)
2274 return mips_extract_operand (operand, insn->insn_opcode);
2277 /* Record the current MIPS16/microMIPS mode in now_seg. */
2280 mips_record_compressed_mode (void)
2282 segment_info_type *si;
2284 si = seg_info (now_seg);
2285 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
2286 si->tc_segment_info_data.mips16 = mips_opts.mips16;
2287 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
2288 si->tc_segment_info_data.micromips = mips_opts.micromips;
2291 /* Read a standard MIPS instruction from BUF. */
2293 static unsigned long
2294 read_insn (char *buf)
2296 if (target_big_endian)
2297 return bfd_getb32 ((bfd_byte *) buf);
2299 return bfd_getl32 ((bfd_byte *) buf);
2302 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2306 write_insn (char *buf, unsigned int insn)
2308 md_number_to_chars (buf, insn, 4);
2312 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2313 has length LENGTH. */
2315 static unsigned long
2316 read_compressed_insn (char *buf, unsigned int length)
2322 for (i = 0; i < length; i += 2)
2325 if (target_big_endian)
2326 insn |= bfd_getb16 ((char *) buf);
2328 insn |= bfd_getl16 ((char *) buf);
2334 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2335 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2338 write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
2342 for (i = 0; i < length; i += 2)
2343 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
2344 return buf + length;
2347 /* Install INSN at the location specified by its "frag" and "where" fields. */
2350 install_insn (const struct mips_cl_insn *insn)
2352 char *f = insn->frag->fr_literal + insn->where;
2353 if (HAVE_CODE_COMPRESSION)
2354 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
2356 write_insn (f, insn->insn_opcode);
2357 mips_record_compressed_mode ();
2360 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2361 and install the opcode in the new location. */
2364 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
2369 insn->where = where;
2370 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2371 if (insn->fixp[i] != NULL)
2373 insn->fixp[i]->fx_frag = frag;
2374 insn->fixp[i]->fx_where = where;
2376 install_insn (insn);
2379 /* Add INSN to the end of the output. */
2382 add_fixed_insn (struct mips_cl_insn *insn)
2384 char *f = frag_more (insn_length (insn));
2385 move_insn (insn, frag_now, f - frag_now->fr_literal);
2388 /* Start a variant frag and move INSN to the start of the variant part,
2389 marking it as fixed. The other arguments are as for frag_var. */
2392 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
2393 relax_substateT subtype, symbolS *symbol, offsetT offset)
2395 frag_grow (max_chars);
2396 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
2398 frag_var (rs_machine_dependent, max_chars, var,
2399 subtype, symbol, offset, NULL);
2402 /* Insert N copies of INSN into the history buffer, starting at
2403 position FIRST. Neither FIRST nor N need to be clipped. */
2406 insert_into_history (unsigned int first, unsigned int n,
2407 const struct mips_cl_insn *insn)
2409 if (mips_relax.sequence != 2)
2413 for (i = ARRAY_SIZE (history); i-- > first;)
2415 history[i] = history[i - n];
2421 /* Clear the error in insn_error. */
2424 clear_insn_error (void)
2426 memset (&insn_error, 0, sizeof (insn_error));
2429 /* Possibly record error message MSG for the current instruction.
2430 If the error is about a particular argument, ARGNUM is the 1-based
2431 number of that argument, otherwise it is 0. FORMAT is the format
2432 of MSG. Return true if MSG was used, false if the current message
2436 set_insn_error_format (int argnum, enum mips_insn_error_format format,
2441 /* Give priority to errors against specific arguments, and to
2442 the first whole-instruction message. */
2448 /* Keep insn_error if it is against a later argument. */
2449 if (argnum < insn_error.min_argnum)
2452 /* If both errors are against the same argument but are different,
2453 give up on reporting a specific error for this argument.
2454 See the comment about mips_insn_error for details. */
2455 if (argnum == insn_error.min_argnum
2457 && strcmp (insn_error.msg, msg) != 0)
2460 insn_error.min_argnum += 1;
2464 insn_error.min_argnum = argnum;
2465 insn_error.format = format;
2466 insn_error.msg = msg;
2470 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2471 as for set_insn_error_format. */
2474 set_insn_error (int argnum, const char *msg)
2476 set_insn_error_format (argnum, ERR_FMT_PLAIN, msg);
2479 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2480 as for set_insn_error_format. */
2483 set_insn_error_i (int argnum, const char *msg, int i)
2485 if (set_insn_error_format (argnum, ERR_FMT_I, msg))
2489 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2490 are as for set_insn_error_format. */
2493 set_insn_error_ss (int argnum, const char *msg, const char *s1, const char *s2)
2495 if (set_insn_error_format (argnum, ERR_FMT_SS, msg))
2497 insn_error.u.ss[0] = s1;
2498 insn_error.u.ss[1] = s2;
2502 /* Report the error in insn_error, which is against assembly code STR. */
2505 report_insn_error (const char *str)
2507 const char *msg = concat (insn_error.msg, " `%s'", NULL);
2509 switch (insn_error.format)
2516 as_bad (msg, insn_error.u.i, str);
2520 as_bad (msg, insn_error.u.ss[0], insn_error.u.ss[1], str);
2524 free ((char *) msg);
2527 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2528 the idea is to make it obvious at a glance that each errata is
2532 init_vr4120_conflicts (void)
2534 #define CONFLICT(FIRST, SECOND) \
2535 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2537 /* Errata 21 - [D]DIV[U] after [D]MACC */
2538 CONFLICT (MACC, DIV);
2539 CONFLICT (DMACC, DIV);
2541 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2542 CONFLICT (DMULT, DMULT);
2543 CONFLICT (DMULT, DMACC);
2544 CONFLICT (DMACC, DMULT);
2545 CONFLICT (DMACC, DMACC);
2547 /* Errata 24 - MT{LO,HI} after [D]MACC */
2548 CONFLICT (MACC, MTHILO);
2549 CONFLICT (DMACC, MTHILO);
2551 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2552 instruction is executed immediately after a MACC or DMACC
2553 instruction, the result of [either instruction] is incorrect." */
2554 CONFLICT (MACC, MULT);
2555 CONFLICT (MACC, DMULT);
2556 CONFLICT (DMACC, MULT);
2557 CONFLICT (DMACC, DMULT);
2559 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2560 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2561 DDIV or DDIVU instruction, the result of the MACC or
2562 DMACC instruction is incorrect.". */
2563 CONFLICT (DMULT, MACC);
2564 CONFLICT (DMULT, DMACC);
2565 CONFLICT (DIV, MACC);
2566 CONFLICT (DIV, DMACC);
2576 #define RNUM_MASK 0x00000ff
2577 #define RTYPE_MASK 0x0ffff00
2578 #define RTYPE_NUM 0x0000100
2579 #define RTYPE_FPU 0x0000200
2580 #define RTYPE_FCC 0x0000400
2581 #define RTYPE_VEC 0x0000800
2582 #define RTYPE_GP 0x0001000
2583 #define RTYPE_CP0 0x0002000
2584 #define RTYPE_PC 0x0004000
2585 #define RTYPE_ACC 0x0008000
2586 #define RTYPE_CCC 0x0010000
2587 #define RTYPE_VI 0x0020000
2588 #define RTYPE_VF 0x0040000
2589 #define RTYPE_R5900_I 0x0080000
2590 #define RTYPE_R5900_Q 0x0100000
2591 #define RTYPE_R5900_R 0x0200000
2592 #define RTYPE_R5900_ACC 0x0400000
2593 #define RTYPE_MSA 0x0800000
2594 #define RWARN 0x8000000
2596 #define GENERIC_REGISTER_NUMBERS \
2597 {"$0", RTYPE_NUM | 0}, \
2598 {"$1", RTYPE_NUM | 1}, \
2599 {"$2", RTYPE_NUM | 2}, \
2600 {"$3", RTYPE_NUM | 3}, \
2601 {"$4", RTYPE_NUM | 4}, \
2602 {"$5", RTYPE_NUM | 5}, \
2603 {"$6", RTYPE_NUM | 6}, \
2604 {"$7", RTYPE_NUM | 7}, \
2605 {"$8", RTYPE_NUM | 8}, \
2606 {"$9", RTYPE_NUM | 9}, \
2607 {"$10", RTYPE_NUM | 10}, \
2608 {"$11", RTYPE_NUM | 11}, \
2609 {"$12", RTYPE_NUM | 12}, \
2610 {"$13", RTYPE_NUM | 13}, \
2611 {"$14", RTYPE_NUM | 14}, \
2612 {"$15", RTYPE_NUM | 15}, \
2613 {"$16", RTYPE_NUM | 16}, \
2614 {"$17", RTYPE_NUM | 17}, \
2615 {"$18", RTYPE_NUM | 18}, \
2616 {"$19", RTYPE_NUM | 19}, \
2617 {"$20", RTYPE_NUM | 20}, \
2618 {"$21", RTYPE_NUM | 21}, \
2619 {"$22", RTYPE_NUM | 22}, \
2620 {"$23", RTYPE_NUM | 23}, \
2621 {"$24", RTYPE_NUM | 24}, \
2622 {"$25", RTYPE_NUM | 25}, \
2623 {"$26", RTYPE_NUM | 26}, \
2624 {"$27", RTYPE_NUM | 27}, \
2625 {"$28", RTYPE_NUM | 28}, \
2626 {"$29", RTYPE_NUM | 29}, \
2627 {"$30", RTYPE_NUM | 30}, \
2628 {"$31", RTYPE_NUM | 31}
2630 #define FPU_REGISTER_NAMES \
2631 {"$f0", RTYPE_FPU | 0}, \
2632 {"$f1", RTYPE_FPU | 1}, \
2633 {"$f2", RTYPE_FPU | 2}, \
2634 {"$f3", RTYPE_FPU | 3}, \
2635 {"$f4", RTYPE_FPU | 4}, \
2636 {"$f5", RTYPE_FPU | 5}, \
2637 {"$f6", RTYPE_FPU | 6}, \
2638 {"$f7", RTYPE_FPU | 7}, \
2639 {"$f8", RTYPE_FPU | 8}, \
2640 {"$f9", RTYPE_FPU | 9}, \
2641 {"$f10", RTYPE_FPU | 10}, \
2642 {"$f11", RTYPE_FPU | 11}, \
2643 {"$f12", RTYPE_FPU | 12}, \
2644 {"$f13", RTYPE_FPU | 13}, \
2645 {"$f14", RTYPE_FPU | 14}, \
2646 {"$f15", RTYPE_FPU | 15}, \
2647 {"$f16", RTYPE_FPU | 16}, \
2648 {"$f17", RTYPE_FPU | 17}, \
2649 {"$f18", RTYPE_FPU | 18}, \
2650 {"$f19", RTYPE_FPU | 19}, \
2651 {"$f20", RTYPE_FPU | 20}, \
2652 {"$f21", RTYPE_FPU | 21}, \
2653 {"$f22", RTYPE_FPU | 22}, \
2654 {"$f23", RTYPE_FPU | 23}, \
2655 {"$f24", RTYPE_FPU | 24}, \
2656 {"$f25", RTYPE_FPU | 25}, \
2657 {"$f26", RTYPE_FPU | 26}, \
2658 {"$f27", RTYPE_FPU | 27}, \
2659 {"$f28", RTYPE_FPU | 28}, \
2660 {"$f29", RTYPE_FPU | 29}, \
2661 {"$f30", RTYPE_FPU | 30}, \
2662 {"$f31", RTYPE_FPU | 31}
2664 #define FPU_CONDITION_CODE_NAMES \
2665 {"$fcc0", RTYPE_FCC | 0}, \
2666 {"$fcc1", RTYPE_FCC | 1}, \
2667 {"$fcc2", RTYPE_FCC | 2}, \
2668 {"$fcc3", RTYPE_FCC | 3}, \
2669 {"$fcc4", RTYPE_FCC | 4}, \
2670 {"$fcc5", RTYPE_FCC | 5}, \
2671 {"$fcc6", RTYPE_FCC | 6}, \
2672 {"$fcc7", RTYPE_FCC | 7}
2674 #define COPROC_CONDITION_CODE_NAMES \
2675 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2676 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2677 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2678 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2679 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2680 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2681 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2682 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2684 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2685 {"$a4", RTYPE_GP | 8}, \
2686 {"$a5", RTYPE_GP | 9}, \
2687 {"$a6", RTYPE_GP | 10}, \
2688 {"$a7", RTYPE_GP | 11}, \
2689 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2690 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2691 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2692 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2693 {"$t0", RTYPE_GP | 12}, \
2694 {"$t1", RTYPE_GP | 13}, \
2695 {"$t2", RTYPE_GP | 14}, \
2696 {"$t3", RTYPE_GP | 15}
2698 #define O32_SYMBOLIC_REGISTER_NAMES \
2699 {"$t0", RTYPE_GP | 8}, \
2700 {"$t1", RTYPE_GP | 9}, \
2701 {"$t2", RTYPE_GP | 10}, \
2702 {"$t3", RTYPE_GP | 11}, \
2703 {"$t4", RTYPE_GP | 12}, \
2704 {"$t5", RTYPE_GP | 13}, \
2705 {"$t6", RTYPE_GP | 14}, \
2706 {"$t7", RTYPE_GP | 15}, \
2707 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2708 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2709 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2710 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2712 /* Remaining symbolic register names */
2713 #define SYMBOLIC_REGISTER_NAMES \
2714 {"$zero", RTYPE_GP | 0}, \
2715 {"$at", RTYPE_GP | 1}, \
2716 {"$AT", RTYPE_GP | 1}, \
2717 {"$v0", RTYPE_GP | 2}, \
2718 {"$v1", RTYPE_GP | 3}, \
2719 {"$a0", RTYPE_GP | 4}, \
2720 {"$a1", RTYPE_GP | 5}, \
2721 {"$a2", RTYPE_GP | 6}, \
2722 {"$a3", RTYPE_GP | 7}, \
2723 {"$s0", RTYPE_GP | 16}, \
2724 {"$s1", RTYPE_GP | 17}, \
2725 {"$s2", RTYPE_GP | 18}, \
2726 {"$s3", RTYPE_GP | 19}, \
2727 {"$s4", RTYPE_GP | 20}, \
2728 {"$s5", RTYPE_GP | 21}, \
2729 {"$s6", RTYPE_GP | 22}, \
2730 {"$s7", RTYPE_GP | 23}, \
2731 {"$t8", RTYPE_GP | 24}, \
2732 {"$t9", RTYPE_GP | 25}, \
2733 {"$k0", RTYPE_GP | 26}, \
2734 {"$kt0", RTYPE_GP | 26}, \
2735 {"$k1", RTYPE_GP | 27}, \
2736 {"$kt1", RTYPE_GP | 27}, \
2737 {"$gp", RTYPE_GP | 28}, \
2738 {"$sp", RTYPE_GP | 29}, \
2739 {"$s8", RTYPE_GP | 30}, \
2740 {"$fp", RTYPE_GP | 30}, \
2741 {"$ra", RTYPE_GP | 31}
2743 #define MIPS16_SPECIAL_REGISTER_NAMES \
2744 {"$pc", RTYPE_PC | 0}
2746 #define MDMX_VECTOR_REGISTER_NAMES \
2747 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2748 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2749 {"$v2", RTYPE_VEC | 2}, \
2750 {"$v3", RTYPE_VEC | 3}, \
2751 {"$v4", RTYPE_VEC | 4}, \
2752 {"$v5", RTYPE_VEC | 5}, \
2753 {"$v6", RTYPE_VEC | 6}, \
2754 {"$v7", RTYPE_VEC | 7}, \
2755 {"$v8", RTYPE_VEC | 8}, \
2756 {"$v9", RTYPE_VEC | 9}, \
2757 {"$v10", RTYPE_VEC | 10}, \
2758 {"$v11", RTYPE_VEC | 11}, \
2759 {"$v12", RTYPE_VEC | 12}, \
2760 {"$v13", RTYPE_VEC | 13}, \
2761 {"$v14", RTYPE_VEC | 14}, \
2762 {"$v15", RTYPE_VEC | 15}, \
2763 {"$v16", RTYPE_VEC | 16}, \
2764 {"$v17", RTYPE_VEC | 17}, \
2765 {"$v18", RTYPE_VEC | 18}, \
2766 {"$v19", RTYPE_VEC | 19}, \
2767 {"$v20", RTYPE_VEC | 20}, \
2768 {"$v21", RTYPE_VEC | 21}, \
2769 {"$v22", RTYPE_VEC | 22}, \
2770 {"$v23", RTYPE_VEC | 23}, \
2771 {"$v24", RTYPE_VEC | 24}, \
2772 {"$v25", RTYPE_VEC | 25}, \
2773 {"$v26", RTYPE_VEC | 26}, \
2774 {"$v27", RTYPE_VEC | 27}, \
2775 {"$v28", RTYPE_VEC | 28}, \
2776 {"$v29", RTYPE_VEC | 29}, \
2777 {"$v30", RTYPE_VEC | 30}, \
2778 {"$v31", RTYPE_VEC | 31}
2780 #define R5900_I_NAMES \
2781 {"$I", RTYPE_R5900_I | 0}
2783 #define R5900_Q_NAMES \
2784 {"$Q", RTYPE_R5900_Q | 0}
2786 #define R5900_R_NAMES \
2787 {"$R", RTYPE_R5900_R | 0}
2789 #define R5900_ACC_NAMES \
2790 {"$ACC", RTYPE_R5900_ACC | 0 }
2792 #define MIPS_DSP_ACCUMULATOR_NAMES \
2793 {"$ac0", RTYPE_ACC | 0}, \
2794 {"$ac1", RTYPE_ACC | 1}, \
2795 {"$ac2", RTYPE_ACC | 2}, \
2796 {"$ac3", RTYPE_ACC | 3}
2798 static const struct regname reg_names[] = {
2799 GENERIC_REGISTER_NUMBERS,
2801 FPU_CONDITION_CODE_NAMES,
2802 COPROC_CONDITION_CODE_NAMES,
2804 /* The $txx registers depends on the abi,
2805 these will be added later into the symbol table from
2806 one of the tables below once mips_abi is set after
2807 parsing of arguments from the command line. */
2808 SYMBOLIC_REGISTER_NAMES,
2810 MIPS16_SPECIAL_REGISTER_NAMES,
2811 MDMX_VECTOR_REGISTER_NAMES,
2816 MIPS_DSP_ACCUMULATOR_NAMES,
2820 static const struct regname reg_names_o32[] = {
2821 O32_SYMBOLIC_REGISTER_NAMES,
2825 static const struct regname reg_names_n32n64[] = {
2826 N32N64_SYMBOLIC_REGISTER_NAMES,
2830 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2831 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2832 of these register symbols, return the associated vector register,
2833 otherwise return SYMVAL itself. */
2836 mips_prefer_vec_regno (unsigned int symval)
2838 if ((symval & -2) == (RTYPE_GP | 2))
2839 return RTYPE_VEC | (symval & 1);
2843 /* Return true if string [S, E) is a valid register name, storing its
2844 symbol value in *SYMVAL_PTR if so. */
2847 mips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr)
2852 /* Terminate name. */
2856 /* Look up the name. */
2857 symbol = symbol_find (s);
2860 if (!symbol || S_GET_SEGMENT (symbol) != reg_section)
2863 *symval_ptr = S_GET_VALUE (symbol);
2867 /* Return true if the string at *SPTR is a valid register name. Allow it
2868 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2871 When returning true, move *SPTR past the register, store the
2872 register's symbol value in *SYMVAL_PTR and the channel mask in
2873 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2874 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2875 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2878 mips_parse_register (char **sptr, unsigned int *symval_ptr,
2879 unsigned int *channels_ptr)
2883 unsigned int channels, symval, bit;
2885 /* Find end of name. */
2887 if (is_name_beginner (*e))
2889 while (is_part_of_name (*e))
2893 if (!mips_parse_register_1 (s, e, &symval))
2898 /* Eat characters from the end of the string that are valid
2899 channel suffixes. The preceding register must be $ACC or
2900 end with a digit, so there is no ambiguity. */
2903 for (q = "wzyx"; *q; q++, bit <<= 1)
2904 if (m > s && m[-1] == *q)
2911 || !mips_parse_register_1 (s, m, &symval)
2912 || (symval & (RTYPE_VI | RTYPE_VF | RTYPE_R5900_ACC)) == 0)
2917 *symval_ptr = symval;
2919 *channels_ptr = channels;
2923 /* Check if SPTR points at a valid register specifier according to TYPES.
2924 If so, then return 1, advance S to consume the specifier and store
2925 the register's number in REGNOP, otherwise return 0. */
2928 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2932 if (mips_parse_register (s, ®no, NULL))
2934 if (types & RTYPE_VEC)
2935 regno = mips_prefer_vec_regno (regno);
2944 as_warn (_("unrecognized register name `%s'"), *s);
2949 return regno <= RNUM_MASK;
2952 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2953 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2956 mips_parse_vu0_channels (char *s, unsigned int *channels)
2961 for (i = 0; i < 4; i++)
2962 if (*s == "xyzw"[i])
2964 *channels |= 1 << (3 - i);
2970 /* Token types for parsed operand lists. */
2971 enum mips_operand_token_type {
2972 /* A plain register, e.g. $f2. */
2975 /* A 4-bit XYZW channel mask. */
2978 /* A constant vector index, e.g. [1]. */
2981 /* A register vector index, e.g. [$2]. */
2984 /* A continuous range of registers, e.g. $s0-$s4. */
2987 /* A (possibly relocated) expression. */
2990 /* A floating-point value. */
2993 /* A single character. This can be '(', ')' or ',', but '(' only appears
2997 /* A doubled character, either "--" or "++". */
3000 /* The end of the operand list. */
3004 /* A parsed operand token. */
3005 struct mips_operand_token
3007 /* The type of token. */
3008 enum mips_operand_token_type type;
3011 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
3014 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
3015 unsigned int channels;
3017 /* The integer value of an OT_INTEGER_INDEX. */
3020 /* The two register symbol values involved in an OT_REG_RANGE. */
3022 unsigned int regno1;
3023 unsigned int regno2;
3026 /* The value of an OT_INTEGER. The value is represented as an
3027 expression and the relocation operators that were applied to
3028 that expression. The reloc entries are BFD_RELOC_UNUSED if no
3029 relocation operators were used. */
3032 bfd_reloc_code_real_type relocs[3];
3035 /* The binary data for an OT_FLOAT constant, and the number of bytes
3038 unsigned char data[8];
3042 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
3047 /* An obstack used to construct lists of mips_operand_tokens. */
3048 static struct obstack mips_operand_tokens;
3050 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
3053 mips_add_token (struct mips_operand_token *token,
3054 enum mips_operand_token_type type)
3057 obstack_grow (&mips_operand_tokens, token, sizeof (*token));
3060 /* Check whether S is '(' followed by a register name. Add OT_CHAR
3061 and OT_REG tokens for them if so, and return a pointer to the first
3062 unconsumed character. Return null otherwise. */
3065 mips_parse_base_start (char *s)
3067 struct mips_operand_token token;
3068 unsigned int regno, channels;
3069 bfd_boolean decrement_p;
3075 SKIP_SPACE_TABS (s);
3077 /* Only match "--" as part of a base expression. In other contexts "--X"
3078 is a double negative. */
3079 decrement_p = (s[0] == '-' && s[1] == '-');
3083 SKIP_SPACE_TABS (s);
3086 /* Allow a channel specifier because that leads to better error messages
3087 than treating something like "$vf0x++" as an expression. */
3088 if (!mips_parse_register (&s, ®no, &channels))
3092 mips_add_token (&token, OT_CHAR);
3097 mips_add_token (&token, OT_DOUBLE_CHAR);
3100 token.u.regno = regno;
3101 mips_add_token (&token, OT_REG);
3105 token.u.channels = channels;
3106 mips_add_token (&token, OT_CHANNELS);
3109 /* For consistency, only match "++" as part of base expressions too. */
3110 SKIP_SPACE_TABS (s);
3111 if (s[0] == '+' && s[1] == '+')
3115 mips_add_token (&token, OT_DOUBLE_CHAR);
3121 /* Parse one or more tokens from S. Return a pointer to the first
3122 unconsumed character on success. Return null if an error was found
3123 and store the error text in insn_error. FLOAT_FORMAT is as for
3124 mips_parse_arguments. */
3127 mips_parse_argument_token (char *s, char float_format)
3129 char *end, *save_in;
3131 unsigned int regno1, regno2, channels;
3132 struct mips_operand_token token;
3134 /* First look for "($reg", since we want to treat that as an
3135 OT_CHAR and OT_REG rather than an expression. */
3136 end = mips_parse_base_start (s);
3140 /* Handle other characters that end up as OT_CHARs. */
3141 if (*s == ')' || *s == ',')
3144 mips_add_token (&token, OT_CHAR);
3149 /* Handle tokens that start with a register. */
3150 if (mips_parse_register (&s, ®no1, &channels))
3154 /* A register and a VU0 channel suffix. */
3155 token.u.regno = regno1;
3156 mips_add_token (&token, OT_REG);
3158 token.u.channels = channels;
3159 mips_add_token (&token, OT_CHANNELS);
3163 SKIP_SPACE_TABS (s);
3166 /* A register range. */
3168 SKIP_SPACE_TABS (s);
3169 if (!mips_parse_register (&s, ®no2, NULL))
3171 set_insn_error (0, _("invalid register range"));
3175 token.u.reg_range.regno1 = regno1;
3176 token.u.reg_range.regno2 = regno2;
3177 mips_add_token (&token, OT_REG_RANGE);
3181 /* Add the register itself. */
3182 token.u.regno = regno1;
3183 mips_add_token (&token, OT_REG);
3185 /* Check for a vector index. */
3189 SKIP_SPACE_TABS (s);
3190 if (mips_parse_register (&s, &token.u.regno, NULL))
3191 mips_add_token (&token, OT_REG_INDEX);
3194 expressionS element;
3196 my_getExpression (&element, s);
3197 if (element.X_op != O_constant)
3199 set_insn_error (0, _("vector element must be constant"));
3203 token.u.index = element.X_add_number;
3204 mips_add_token (&token, OT_INTEGER_INDEX);
3206 SKIP_SPACE_TABS (s);
3209 set_insn_error (0, _("missing `]'"));
3219 /* First try to treat expressions as floats. */
3220 save_in = input_line_pointer;
3221 input_line_pointer = s;
3222 err = md_atof (float_format, (char *) token.u.flt.data,
3223 &token.u.flt.length);
3224 end = input_line_pointer;
3225 input_line_pointer = save_in;
3228 set_insn_error (0, err);
3233 mips_add_token (&token, OT_FLOAT);
3238 /* Treat everything else as an integer expression. */
3239 token.u.integer.relocs[0] = BFD_RELOC_UNUSED;
3240 token.u.integer.relocs[1] = BFD_RELOC_UNUSED;
3241 token.u.integer.relocs[2] = BFD_RELOC_UNUSED;
3242 my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s);
3244 mips_add_token (&token, OT_INTEGER);
3248 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3249 if expressions should be treated as 32-bit floating-point constants,
3250 'd' if they should be treated as 64-bit floating-point constants,
3251 or 0 if they should be treated as integer expressions (the usual case).
3253 Return a list of tokens on success, otherwise return 0. The caller
3254 must obstack_free the list after use. */
3256 static struct mips_operand_token *
3257 mips_parse_arguments (char *s, char float_format)
3259 struct mips_operand_token token;
3261 SKIP_SPACE_TABS (s);
3264 s = mips_parse_argument_token (s, float_format);
3267 obstack_free (&mips_operand_tokens,
3268 obstack_finish (&mips_operand_tokens));
3271 SKIP_SPACE_TABS (s);
3273 mips_add_token (&token, OT_END);
3274 return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens);
3277 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3278 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3281 is_opcode_valid (const struct mips_opcode *mo)
3283 int isa = mips_opts.isa;
3284 int ase = mips_opts.ase;
3288 if (ISA_HAS_64BIT_REGS (isa))
3289 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
3290 if ((ase & mips_ases[i].flags) == mips_ases[i].flags)
3291 ase |= mips_ases[i].flags64;
3293 if (!opcode_is_member (mo, isa, ase, mips_opts.arch))
3296 /* Check whether the instruction or macro requires single-precision or
3297 double-precision floating-point support. Note that this information is
3298 stored differently in the opcode table for insns and macros. */
3299 if (mo->pinfo == INSN_MACRO)
3301 fp_s = mo->pinfo2 & INSN2_M_FP_S;
3302 fp_d = mo->pinfo2 & INSN2_M_FP_D;
3306 fp_s = mo->pinfo & FP_S;
3307 fp_d = mo->pinfo & FP_D;
3310 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
3313 if (fp_s && mips_opts.soft_float)
3319 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3320 selected ISA and architecture. */
3323 is_opcode_valid_16 (const struct mips_opcode *mo)
3325 int isa = mips_opts.isa;
3326 int ase = mips_opts.ase;
3329 if (ISA_HAS_64BIT_REGS (isa))
3330 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
3331 if ((ase & mips_ases[i].flags) == mips_ases[i].flags)
3332 ase |= mips_ases[i].flags64;
3334 return opcode_is_member (mo, isa, ase, mips_opts.arch);
3337 /* Return TRUE if the size of the microMIPS opcode MO matches one
3338 explicitly requested. Always TRUE in the standard MIPS mode.
3339 Use is_size_valid_16 for MIPS16 opcodes. */
3342 is_size_valid (const struct mips_opcode *mo)
3344 if (!mips_opts.micromips)
3347 if (mips_opts.insn32)
3349 if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4)
3351 if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0)
3354 if (!forced_insn_length)
3356 if (mo->pinfo == INSN_MACRO)
3358 return forced_insn_length == micromips_insn_length (mo);
3361 /* Return TRUE if the size of the MIPS16 opcode MO matches one
3362 explicitly requested. */
3365 is_size_valid_16 (const struct mips_opcode *mo)
3367 if (!forced_insn_length)
3369 if (mo->pinfo == INSN_MACRO)
3371 if (forced_insn_length == 2 && mips_opcode_32bit_p (mo))
3373 if (forced_insn_length == 4 && (mo->pinfo2 & INSN2_SHORT_ONLY))
3378 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3379 of the preceding instruction. Always TRUE in the standard MIPS mode.
3381 We don't accept macros in 16-bit delay slots to avoid a case where
3382 a macro expansion fails because it relies on a preceding 32-bit real
3383 instruction to have matched and does not handle the operands correctly.
3384 The only macros that may expand to 16-bit instructions are JAL that
3385 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3386 and BGT (that likewise cannot be placed in a delay slot) that decay to
3387 a NOP. In all these cases the macros precede any corresponding real
3388 instruction definitions in the opcode table, so they will match in the
3389 second pass where the size of the delay slot is ignored and therefore
3390 produce correct code. */
3393 is_delay_slot_valid (const struct mips_opcode *mo)
3395 if (!mips_opts.micromips)
3398 if (mo->pinfo == INSN_MACRO)
3399 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0;
3400 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
3401 && micromips_insn_length (mo) != 4)
3403 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
3404 && micromips_insn_length (mo) != 2)
3410 /* For consistency checking, verify that all bits of OPCODE are specified
3411 either by the match/mask part of the instruction definition, or by the
3412 operand list. Also build up a list of operands in OPERANDS.
3414 INSN_BITS says which bits of the instruction are significant.
3415 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3416 provides the mips_operand description of each operand. DECODE_OPERAND
3417 is null for MIPS16 instructions. */
3420 validate_mips_insn (const struct mips_opcode *opcode,
3421 unsigned long insn_bits,
3422 const struct mips_operand *(*decode_operand) (const char *),
3423 struct mips_operand_array *operands)
3426 unsigned long used_bits, doubled, undefined, opno, mask;
3427 const struct mips_operand *operand;
3429 mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask);
3430 if ((mask & opcode->match) != opcode->match)
3432 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3433 opcode->name, opcode->args);
3438 if (opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX)
3439 used_bits = mips_insert_operand (&mips_vu0_channel_mask, used_bits, -1);
3440 for (s = opcode->args; *s; ++s)
3453 if (!decode_operand)
3454 operand = decode_mips16_operand (*s, mips_opcode_32bit_p (opcode));
3456 operand = decode_operand (s);
3457 if (!operand && opcode->pinfo != INSN_MACRO)
3459 as_bad (_("internal: unknown operand type: %s %s"),
3460 opcode->name, opcode->args);
3463 gas_assert (opno < MAX_OPERANDS);
3464 operands->operand[opno] = operand;
3465 if (!decode_operand && operand
3466 && operand->type == OP_INT && operand->lsb == 0
3467 && mips_opcode_32bit_p (opcode))
3468 used_bits |= mips16_immed_extend (-1, operand->size);
3469 else if (operand && operand->type != OP_VU0_MATCH_SUFFIX)
3471 used_bits = mips_insert_operand (operand, used_bits, -1);
3472 if (operand->type == OP_MDMX_IMM_REG)
3473 /* Bit 5 is the format selector (OB vs QH). The opcode table
3474 has separate entries for each format. */
3475 used_bits &= ~(1 << (operand->lsb + 5));
3476 if (operand->type == OP_ENTRY_EXIT_LIST)
3477 used_bits &= ~(mask & 0x700);
3478 /* interAptiv MR2 SAVE/RESTORE instructions have a discontiguous
3479 operand field that cannot be fully described with LSB/SIZE. */
3480 if (operand->type == OP_SAVE_RESTORE_LIST && operand->lsb == 6)
3481 used_bits &= ~0x6000;
3483 /* Skip prefix characters. */
3484 if (decode_operand && (*s == '+' || *s == 'm' || *s == '-'))
3489 doubled = used_bits & mask & insn_bits;
3492 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3493 " %s %s"), doubled, opcode->name, opcode->args);
3497 undefined = ~used_bits & insn_bits;
3498 if (opcode->pinfo != INSN_MACRO && undefined)
3500 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3501 undefined, opcode->name, opcode->args);
3504 used_bits &= ~insn_bits;
3507 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3508 used_bits, opcode->name, opcode->args);
3514 /* The MIPS16 version of validate_mips_insn. */
3517 validate_mips16_insn (const struct mips_opcode *opcode,
3518 struct mips_operand_array *operands)
3520 unsigned long insn_bits = mips_opcode_32bit_p (opcode) ? 0xffffffff : 0xffff;
3522 return validate_mips_insn (opcode, insn_bits, 0, operands);
3525 /* The microMIPS version of validate_mips_insn. */
3528 validate_micromips_insn (const struct mips_opcode *opc,
3529 struct mips_operand_array *operands)
3531 unsigned long insn_bits;
3532 unsigned long major;
3533 unsigned int length;
3535 if (opc->pinfo == INSN_MACRO)
3536 return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand,
3539 length = micromips_insn_length (opc);
3540 if (length != 2 && length != 4)
3542 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3543 "%s %s"), length, opc->name, opc->args);
3546 major = opc->match >> (10 + 8 * (length - 2));
3547 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
3548 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
3550 as_bad (_("internal error: bad microMIPS opcode "
3551 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
3555 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3556 insn_bits = 1 << 4 * length;
3557 insn_bits <<= 4 * length;
3559 return validate_mips_insn (opc, insn_bits, decode_micromips_operand,
3563 /* This function is called once, at assembler startup time. It should set up
3564 all the tables, etc. that the MD part of the assembler will need. */
3569 const char *retval = NULL;
3573 if (mips_pic != NO_PIC)
3575 if (g_switch_seen && g_switch_value != 0)
3576 as_bad (_("-G may not be used in position-independent code"));
3579 else if (mips_abicalls)
3581 if (g_switch_seen && g_switch_value != 0)
3582 as_bad (_("-G may not be used with abicalls"));
3586 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch))
3587 as_warn (_("could not set architecture and machine"));
3589 op_hash = hash_new ();
3591 mips_operands = XCNEWVEC (struct mips_operand_array, NUMOPCODES);
3592 for (i = 0; i < NUMOPCODES;)
3594 const char *name = mips_opcodes[i].name;
3596 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
3599 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
3600 mips_opcodes[i].name, retval);
3601 /* Probably a memory allocation problem? Give up now. */
3602 as_fatal (_("broken assembler, no assembly attempted"));
3606 if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff,
3607 decode_mips_operand, &mips_operands[i]))
3609 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3611 create_insn (&nop_insn, mips_opcodes + i);
3612 if (mips_fix_loongson2f_nop)
3613 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
3614 nop_insn.fixed_p = 1;
3618 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
3621 mips16_op_hash = hash_new ();
3622 mips16_operands = XCNEWVEC (struct mips_operand_array,
3623 bfd_mips16_num_opcodes);
3626 while (i < bfd_mips16_num_opcodes)
3628 const char *name = mips16_opcodes[i].name;
3630 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
3632 as_fatal (_("internal: can't hash `%s': %s"),
3633 mips16_opcodes[i].name, retval);
3636 if (!validate_mips16_insn (&mips16_opcodes[i], &mips16_operands[i]))
3638 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3640 create_insn (&mips16_nop_insn, mips16_opcodes + i);
3641 mips16_nop_insn.fixed_p = 1;
3645 while (i < bfd_mips16_num_opcodes
3646 && strcmp (mips16_opcodes[i].name, name) == 0);
3649 micromips_op_hash = hash_new ();
3650 micromips_operands = XCNEWVEC (struct mips_operand_array,
3651 bfd_micromips_num_opcodes);
3654 while (i < bfd_micromips_num_opcodes)
3656 const char *name = micromips_opcodes[i].name;
3658 retval = hash_insert (micromips_op_hash, name,
3659 (void *) µmips_opcodes[i]);
3661 as_fatal (_("internal: can't hash `%s': %s"),
3662 micromips_opcodes[i].name, retval);
3665 struct mips_cl_insn *micromips_nop_insn;
3667 if (!validate_micromips_insn (µmips_opcodes[i],
3668 µmips_operands[i]))
3671 if (micromips_opcodes[i].pinfo != INSN_MACRO)
3673 if (micromips_insn_length (micromips_opcodes + i) == 2)
3674 micromips_nop_insn = µmips_nop16_insn;
3675 else if (micromips_insn_length (micromips_opcodes + i) == 4)
3676 micromips_nop_insn = µmips_nop32_insn;
3680 if (micromips_nop_insn->insn_mo == NULL
3681 && strcmp (name, "nop") == 0)
3683 create_insn (micromips_nop_insn, micromips_opcodes + i);
3684 micromips_nop_insn->fixed_p = 1;
3688 while (++i < bfd_micromips_num_opcodes
3689 && strcmp (micromips_opcodes[i].name, name) == 0);
3693 as_fatal (_("broken assembler, no assembly attempted"));
3695 /* We add all the general register names to the symbol table. This
3696 helps us detect invalid uses of them. */
3697 for (i = 0; reg_names[i].name; i++)
3698 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
3699 reg_names[i].num, /* & RNUM_MASK, */
3700 &zero_address_frag));
3702 for (i = 0; reg_names_n32n64[i].name; i++)
3703 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
3704 reg_names_n32n64[i].num, /* & RNUM_MASK, */
3705 &zero_address_frag));
3707 for (i = 0; reg_names_o32[i].name; i++)
3708 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
3709 reg_names_o32[i].num, /* & RNUM_MASK, */
3710 &zero_address_frag));
3712 for (i = 0; i < 32; i++)
3716 /* R5900 VU0 floating-point register. */
3717 sprintf (regname, "$vf%d", i);
3718 symbol_table_insert (symbol_new (regname, reg_section,
3719 RTYPE_VF | i, &zero_address_frag));
3721 /* R5900 VU0 integer register. */
3722 sprintf (regname, "$vi%d", i);
3723 symbol_table_insert (symbol_new (regname, reg_section,
3724 RTYPE_VI | i, &zero_address_frag));
3727 sprintf (regname, "$w%d", i);
3728 symbol_table_insert (symbol_new (regname, reg_section,
3729 RTYPE_MSA | i, &zero_address_frag));
3732 obstack_init (&mips_operand_tokens);
3734 mips_no_prev_insn ();
3737 mips_cprmask[0] = 0;
3738 mips_cprmask[1] = 0;
3739 mips_cprmask[2] = 0;
3740 mips_cprmask[3] = 0;
3742 /* set the default alignment for the text section (2**2) */
3743 record_alignment (text_section, 2);
3745 bfd_set_gp_size (stdoutput, g_switch_value);
3747 /* On a native system other than VxWorks, sections must be aligned
3748 to 16 byte boundaries. When configured for an embedded ELF
3749 target, we don't bother. */
3750 if (strncmp (TARGET_OS, "elf", 3) != 0
3751 && strncmp (TARGET_OS, "vxworks", 7) != 0)
3753 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
3754 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
3755 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
3758 /* Create a .reginfo section for register masks and a .mdebug
3759 section for debugging information. */
3767 subseg = now_subseg;
3769 /* The ABI says this section should be loaded so that the
3770 running program can access it. However, we don't load it
3771 if we are configured for an embedded target */
3772 flags = SEC_READONLY | SEC_DATA;
3773 if (strncmp (TARGET_OS, "elf", 3) != 0)
3774 flags |= SEC_ALLOC | SEC_LOAD;
3776 if (mips_abi != N64_ABI)
3778 sec = subseg_new (".reginfo", (subsegT) 0);
3780 bfd_set_section_flags (stdoutput, sec, flags);
3781 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
3783 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
3787 /* The 64-bit ABI uses a .MIPS.options section rather than
3788 .reginfo section. */
3789 sec = subseg_new (".MIPS.options", (subsegT) 0);
3790 bfd_set_section_flags (stdoutput, sec, flags);
3791 bfd_set_section_alignment (stdoutput, sec, 3);
3793 /* Set up the option header. */
3795 Elf_Internal_Options opthdr;
3798 opthdr.kind = ODK_REGINFO;
3799 opthdr.size = (sizeof (Elf_External_Options)
3800 + sizeof (Elf64_External_RegInfo));
3803 f = frag_more (sizeof (Elf_External_Options));
3804 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
3805 (Elf_External_Options *) f);
3807 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
3811 sec = subseg_new (".MIPS.abiflags", (subsegT) 0);
3812 bfd_set_section_flags (stdoutput, sec,
3813 SEC_READONLY | SEC_DATA | SEC_ALLOC | SEC_LOAD);
3814 bfd_set_section_alignment (stdoutput, sec, 3);
3815 mips_flags_frag = frag_more (sizeof (Elf_External_ABIFlags_v0));
3817 if (ECOFF_DEBUGGING)
3819 sec = subseg_new (".mdebug", (subsegT) 0);
3820 (void) bfd_set_section_flags (stdoutput, sec,
3821 SEC_HAS_CONTENTS | SEC_READONLY);
3822 (void) bfd_set_section_alignment (stdoutput, sec, 2);
3824 else if (mips_flag_pdr)
3826 pdr_seg = subseg_new (".pdr", (subsegT) 0);
3827 (void) bfd_set_section_flags (stdoutput, pdr_seg,
3828 SEC_READONLY | SEC_RELOC
3830 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
3833 subseg_set (seg, subseg);
3836 if (mips_fix_vr4120)
3837 init_vr4120_conflicts ();
3841 fpabi_incompatible_with (int fpabi, const char *what)
3843 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3844 Tag_GNU_MIPS_ABI_FP, fpabi, what);
3848 fpabi_requires (int fpabi, const char *what)
3850 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3851 Tag_GNU_MIPS_ABI_FP, fpabi, what);
3854 /* Check -mabi and register sizes against the specified FP ABI. */
3856 check_fpabi (int fpabi)
3860 case Val_GNU_MIPS_ABI_FP_DOUBLE:
3861 if (file_mips_opts.soft_float)
3862 fpabi_incompatible_with (fpabi, "softfloat");
3863 else if (file_mips_opts.single_float)
3864 fpabi_incompatible_with (fpabi, "singlefloat");
3865 if (file_mips_opts.gp == 64 && file_mips_opts.fp == 32)
3866 fpabi_incompatible_with (fpabi, "gp=64 fp=32");
3867 else if (file_mips_opts.gp == 32 && file_mips_opts.fp == 64)
3868 fpabi_incompatible_with (fpabi, "gp=32 fp=64");
3871 case Val_GNU_MIPS_ABI_FP_XX:
3872 if (mips_abi != O32_ABI)
3873 fpabi_requires (fpabi, "-mabi=32");
3874 else if (file_mips_opts.soft_float)
3875 fpabi_incompatible_with (fpabi, "softfloat");
3876 else if (file_mips_opts.single_float)
3877 fpabi_incompatible_with (fpabi, "singlefloat");
3878 else if (file_mips_opts.fp != 0)
3879 fpabi_requires (fpabi, "fp=xx");
3882 case Val_GNU_MIPS_ABI_FP_64A:
3883 case Val_GNU_MIPS_ABI_FP_64:
3884 if (mips_abi != O32_ABI)
3885 fpabi_requires (fpabi, "-mabi=32");
3886 else if (file_mips_opts.soft_float)
3887 fpabi_incompatible_with (fpabi, "softfloat");
3888 else if (file_mips_opts.single_float)
3889 fpabi_incompatible_with (fpabi, "singlefloat");
3890 else if (file_mips_opts.fp != 64)
3891 fpabi_requires (fpabi, "fp=64");
3892 else if (fpabi == Val_GNU_MIPS_ABI_FP_64 && !file_mips_opts.oddspreg)
3893 fpabi_incompatible_with (fpabi, "nooddspreg");
3894 else if (fpabi == Val_GNU_MIPS_ABI_FP_64A && file_mips_opts.oddspreg)
3895 fpabi_requires (fpabi, "nooddspreg");
3898 case Val_GNU_MIPS_ABI_FP_SINGLE:
3899 if (file_mips_opts.soft_float)
3900 fpabi_incompatible_with (fpabi, "softfloat");
3901 else if (!file_mips_opts.single_float)
3902 fpabi_requires (fpabi, "singlefloat");
3905 case Val_GNU_MIPS_ABI_FP_SOFT:
3906 if (!file_mips_opts.soft_float)
3907 fpabi_requires (fpabi, "softfloat");
3910 case Val_GNU_MIPS_ABI_FP_OLD_64:
3911 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
3912 Tag_GNU_MIPS_ABI_FP, fpabi);
3915 case Val_GNU_MIPS_ABI_FP_NAN2008:
3916 /* Silently ignore compatibility value. */
3920 as_warn (_(".gnu_attribute %d,%d is not a recognized"
3921 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP, fpabi);
3926 /* Perform consistency checks on the current options. */
3929 mips_check_options (struct mips_set_options *opts, bfd_boolean abi_checks)
3931 /* Check the size of integer registers agrees with the ABI and ISA. */
3932 if (opts->gp == 64 && !ISA_HAS_64BIT_REGS (opts->isa))
3933 as_bad (_("`gp=64' used with a 32-bit processor"));
3935 && opts->gp == 32 && ABI_NEEDS_64BIT_REGS (mips_abi))
3936 as_bad (_("`gp=32' used with a 64-bit ABI"));
3938 && opts->gp == 64 && ABI_NEEDS_32BIT_REGS (mips_abi))
3939 as_bad (_("`gp=64' used with a 32-bit ABI"));
3941 /* Check the size of the float registers agrees with the ABI and ISA. */
3945 if (!CPU_HAS_LDC1_SDC1 (opts->arch))
3946 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
3947 else if (opts->single_float == 1)
3948 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
3951 if (!ISA_HAS_64BIT_FPRS (opts->isa))
3952 as_bad (_("`fp=64' used with a 32-bit fpu"));
3954 && ABI_NEEDS_32BIT_REGS (mips_abi)
3955 && !ISA_HAS_MXHC1 (opts->isa))
3956 as_warn (_("`fp=64' used with a 32-bit ABI"));
3960 && ABI_NEEDS_64BIT_REGS (mips_abi))
3961 as_warn (_("`fp=32' used with a 64-bit ABI"));
3962 if (ISA_IS_R6 (opts->isa) && opts->single_float == 0)
3963 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
3966 as_bad (_("Unknown size of floating point registers"));
3970 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !opts->oddspreg)
3971 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
3973 if (opts->micromips == 1 && opts->mips16 == 1)
3974 as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips");
3975 else if (ISA_IS_R6 (opts->isa)
3976 && (opts->micromips == 1
3977 || opts->mips16 == 1))
3978 as_fatal (_("`%s' cannot be used with `%s'"),
3979 opts->micromips ? "micromips" : "mips16",
3980 mips_cpu_info_from_isa (opts->isa)->name);
3982 if (ISA_IS_R6 (opts->isa) && mips_relax_branch)
3983 as_fatal (_("branch relaxation is not supported in `%s'"),
3984 mips_cpu_info_from_isa (opts->isa)->name);
3987 /* Perform consistency checks on the module level options exactly once.
3988 This is a deferred check that happens:
3989 at the first .set directive
3990 or, at the first pseudo op that generates code (inc .dc.a)
3991 or, at the first instruction
3995 file_mips_check_options (void)
3997 const struct mips_cpu_info *arch_info = 0;
3999 if (file_mips_opts_checked)
4002 /* The following code determines the register size.
4003 Similar code was added to GCC 3.3 (see override_options() in
4004 config/mips/mips.c). The GAS and GCC code should be kept in sync
4005 as much as possible. */
4007 if (file_mips_opts.gp < 0)
4009 /* Infer the integer register size from the ABI and processor.
4010 Restrict ourselves to 32-bit registers if that's all the
4011 processor has, or if the ABI cannot handle 64-bit registers. */
4012 file_mips_opts.gp = (ABI_NEEDS_32BIT_REGS (mips_abi)
4013 || !ISA_HAS_64BIT_REGS (file_mips_opts.isa))
4017 if (file_mips_opts.fp < 0)
4019 /* No user specified float register size.
4020 ??? GAS treats single-float processors as though they had 64-bit
4021 float registers (although it complains when double-precision
4022 instructions are used). As things stand, saying they have 32-bit
4023 registers would lead to spurious "register must be even" messages.
4024 So here we assume float registers are never smaller than the
4026 if (file_mips_opts.gp == 64)
4027 /* 64-bit integer registers implies 64-bit float registers. */
4028 file_mips_opts.fp = 64;
4029 else if ((file_mips_opts.ase & FP64_ASES)
4030 && ISA_HAS_64BIT_FPRS (file_mips_opts.isa))
4031 /* Handle ASEs that require 64-bit float registers, if possible. */
4032 file_mips_opts.fp = 64;
4033 else if (ISA_IS_R6 (mips_opts.isa))
4034 /* R6 implies 64-bit float registers. */
4035 file_mips_opts.fp = 64;
4037 /* 32-bit float registers. */
4038 file_mips_opts.fp = 32;
4041 arch_info = mips_cpu_info_from_arch (file_mips_opts.arch);
4043 /* Disable operations on odd-numbered floating-point registers by default
4044 when using the FPXX ABI. */
4045 if (file_mips_opts.oddspreg < 0)
4047 if (file_mips_opts.fp == 0)
4048 file_mips_opts.oddspreg = 0;
4050 file_mips_opts.oddspreg = 1;
4053 /* End of GCC-shared inference code. */
4055 /* This flag is set when we have a 64-bit capable CPU but use only
4056 32-bit wide registers. Note that EABI does not use it. */
4057 if (ISA_HAS_64BIT_REGS (file_mips_opts.isa)
4058 && ((mips_abi == NO_ABI && file_mips_opts.gp == 32)
4059 || mips_abi == O32_ABI))
4062 if (file_mips_opts.isa == ISA_MIPS1 && mips_trap)
4063 as_bad (_("trap exception not supported at ISA 1"));
4065 /* If the selected architecture includes support for ASEs, enable
4066 generation of code for them. */
4067 if (file_mips_opts.mips16 == -1)
4068 file_mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_opts.arch)) ? 1 : 0;
4069 if (file_mips_opts.micromips == -1)
4070 file_mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_opts.arch))
4073 if (mips_nan2008 == -1)
4074 mips_nan2008 = (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) ? 0 : 1;
4075 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts.isa) && mips_nan2008 == 0)
4076 as_fatal (_("`%s' does not support legacy NaN"),
4077 mips_cpu_info_from_arch (file_mips_opts.arch)->name);
4079 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
4080 being selected implicitly. */
4081 if (file_mips_opts.fp != 64)
4082 file_ase_explicit |= ASE_MIPS3D | ASE_MDMX | ASE_MSA;
4084 /* If the user didn't explicitly select or deselect a particular ASE,
4085 use the default setting for the CPU. */
4086 file_mips_opts.ase |= (arch_info->ase & ~file_ase_explicit);
4088 /* Set up the current options. These may change throughout assembly. */
4089 mips_opts = file_mips_opts;
4091 mips_check_isa_supports_ases ();
4092 mips_check_options (&file_mips_opts, TRUE);
4093 file_mips_opts_checked = TRUE;
4095 if (!bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch))
4096 as_warn (_("could not set architecture and machine"));
4100 md_assemble (char *str)
4102 struct mips_cl_insn insn;
4103 bfd_reloc_code_real_type unused_reloc[3]
4104 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
4106 file_mips_check_options ();
4108 imm_expr.X_op = O_absent;
4109 offset_expr.X_op = O_absent;
4110 offset_reloc[0] = BFD_RELOC_UNUSED;
4111 offset_reloc[1] = BFD_RELOC_UNUSED;
4112 offset_reloc[2] = BFD_RELOC_UNUSED;
4114 mips_mark_labels ();
4115 mips_assembling_insn = TRUE;
4116 clear_insn_error ();
4118 if (mips_opts.mips16)
4119 mips16_ip (str, &insn);
4122 mips_ip (str, &insn);
4123 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4124 str, insn.insn_opcode));
4128 report_insn_error (str);
4129 else if (insn.insn_mo->pinfo == INSN_MACRO)
4132 if (mips_opts.mips16)
4133 mips16_macro (&insn);
4140 if (offset_expr.X_op != O_absent)
4141 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
4143 append_insn (&insn, NULL, unused_reloc, FALSE);
4146 mips_assembling_insn = FALSE;
4149 /* Convenience functions for abstracting away the differences between
4150 MIPS16 and non-MIPS16 relocations. */
4152 static inline bfd_boolean
4153 mips16_reloc_p (bfd_reloc_code_real_type reloc)
4157 case BFD_RELOC_MIPS16_JMP:
4158 case BFD_RELOC_MIPS16_GPREL:
4159 case BFD_RELOC_MIPS16_GOT16:
4160 case BFD_RELOC_MIPS16_CALL16:
4161 case BFD_RELOC_MIPS16_HI16_S:
4162 case BFD_RELOC_MIPS16_HI16:
4163 case BFD_RELOC_MIPS16_LO16:
4164 case BFD_RELOC_MIPS16_16_PCREL_S1:
4172 static inline bfd_boolean
4173 micromips_reloc_p (bfd_reloc_code_real_type reloc)
4177 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
4178 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
4179 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
4180 case BFD_RELOC_MICROMIPS_GPREL16:
4181 case BFD_RELOC_MICROMIPS_JMP:
4182 case BFD_RELOC_MICROMIPS_HI16:
4183 case BFD_RELOC_MICROMIPS_HI16_S:
4184 case BFD_RELOC_MICROMIPS_LO16:
4185 case BFD_RELOC_MICROMIPS_LITERAL:
4186 case BFD_RELOC_MICROMIPS_GOT16:
4187 case BFD_RELOC_MICROMIPS_CALL16:
4188 case BFD_RELOC_MICROMIPS_GOT_HI16:
4189 case BFD_RELOC_MICROMIPS_GOT_LO16:
4190 case BFD_RELOC_MICROMIPS_CALL_HI16:
4191 case BFD_RELOC_MICROMIPS_CALL_LO16:
4192 case BFD_RELOC_MICROMIPS_SUB:
4193 case BFD_RELOC_MICROMIPS_GOT_PAGE:
4194 case BFD_RELOC_MICROMIPS_GOT_OFST:
4195 case BFD_RELOC_MICROMIPS_GOT_DISP:
4196 case BFD_RELOC_MICROMIPS_HIGHEST:
4197 case BFD_RELOC_MICROMIPS_HIGHER:
4198 case BFD_RELOC_MICROMIPS_SCN_DISP:
4199 case BFD_RELOC_MICROMIPS_JALR:
4207 static inline bfd_boolean
4208 jmp_reloc_p (bfd_reloc_code_real_type reloc)
4210 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
4213 static inline bfd_boolean
4214 b_reloc_p (bfd_reloc_code_real_type reloc)
4216 return (reloc == BFD_RELOC_MIPS_26_PCREL_S2
4217 || reloc == BFD_RELOC_MIPS_21_PCREL_S2
4218 || reloc == BFD_RELOC_16_PCREL_S2
4219 || reloc == BFD_RELOC_MIPS16_16_PCREL_S1
4220 || reloc == BFD_RELOC_MICROMIPS_16_PCREL_S1
4221 || reloc == BFD_RELOC_MICROMIPS_10_PCREL_S1
4222 || reloc == BFD_RELOC_MICROMIPS_7_PCREL_S1);
4225 static inline bfd_boolean
4226 got16_reloc_p (bfd_reloc_code_real_type reloc)
4228 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
4229 || reloc == BFD_RELOC_MICROMIPS_GOT16);
4232 static inline bfd_boolean
4233 hi16_reloc_p (bfd_reloc_code_real_type reloc)
4235 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
4236 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
4239 static inline bfd_boolean
4240 lo16_reloc_p (bfd_reloc_code_real_type reloc)
4242 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
4243 || reloc == BFD_RELOC_MICROMIPS_LO16);
4246 static inline bfd_boolean
4247 jalr_reloc_p (bfd_reloc_code_real_type reloc)
4249 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
4252 static inline bfd_boolean
4253 gprel16_reloc_p (bfd_reloc_code_real_type reloc)
4255 return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL
4256 || reloc == BFD_RELOC_MICROMIPS_GPREL16);
4259 /* Return true if RELOC is a PC-relative relocation that does not have
4260 full address range. */
4262 static inline bfd_boolean
4263 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc)
4267 case BFD_RELOC_16_PCREL_S2:
4268 case BFD_RELOC_MIPS16_16_PCREL_S1:
4269 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
4270 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
4271 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
4272 case BFD_RELOC_MIPS_21_PCREL_S2:
4273 case BFD_RELOC_MIPS_26_PCREL_S2:
4274 case BFD_RELOC_MIPS_18_PCREL_S3:
4275 case BFD_RELOC_MIPS_19_PCREL_S2:
4278 case BFD_RELOC_32_PCREL:
4279 case BFD_RELOC_HI16_S_PCREL:
4280 case BFD_RELOC_LO16_PCREL:
4281 return HAVE_64BIT_ADDRESSES;
4288 /* Return true if the given relocation might need a matching %lo().
4289 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4290 need a matching %lo() when applied to local symbols. */
4292 static inline bfd_boolean
4293 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
4295 return (HAVE_IN_PLACE_ADDENDS
4296 && (hi16_reloc_p (reloc)
4297 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4298 all GOT16 relocations evaluate to "G". */
4299 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
4302 /* Return the type of %lo() reloc needed by RELOC, given that
4303 reloc_needs_lo_p. */
4305 static inline bfd_reloc_code_real_type
4306 matching_lo_reloc (bfd_reloc_code_real_type reloc)
4308 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
4309 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
4313 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
4316 static inline bfd_boolean
4317 fixup_has_matching_lo_p (fixS *fixp)
4319 return (fixp->fx_next != NULL
4320 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
4321 && fixp->fx_addsy == fixp->fx_next->fx_addsy
4322 && fixp->fx_offset == fixp->fx_next->fx_offset);
4325 /* Move all labels in LABELS to the current insertion point. TEXT_P
4326 says whether the labels refer to text or data. */
4329 mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
4331 struct insn_label_list *l;
4334 for (l = labels; l != NULL; l = l->next)
4336 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
4337 symbol_set_frag (l->label, frag_now);
4338 val = (valueT) frag_now_fix ();
4339 /* MIPS16/microMIPS text labels are stored as odd. */
4340 if (text_p && HAVE_CODE_COMPRESSION)
4342 S_SET_VALUE (l->label, val);
4346 /* Move all labels in insn_labels to the current insertion point
4347 and treat them as text labels. */
4350 mips_move_text_labels (void)
4352 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
4355 /* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */
4358 s_is_linkonce (symbolS *sym, segT from_seg)
4360 bfd_boolean linkonce = FALSE;
4361 segT symseg = S_GET_SEGMENT (sym);
4363 if (symseg != from_seg && !S_IS_LOCAL (sym))
4365 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
4367 /* The GNU toolchain uses an extension for ELF: a section
4368 beginning with the magic string .gnu.linkonce is a
4369 linkonce section. */
4370 if (strncmp (segment_name (symseg), ".gnu.linkonce",
4371 sizeof ".gnu.linkonce" - 1) == 0)
4377 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
4378 linker to handle them specially, such as generating jalx instructions
4379 when needed. We also make them odd for the duration of the assembly,
4380 in order to generate the right sort of code. We will make them even
4381 in the adjust_symtab routine, while leaving them marked. This is
4382 convenient for the debugger and the disassembler. The linker knows
4383 to make them odd again. */
4386 mips_compressed_mark_label (symbolS *label)
4388 gas_assert (HAVE_CODE_COMPRESSION);
4390 if (mips_opts.mips16)
4391 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
4393 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
4394 if ((S_GET_VALUE (label) & 1) == 0
4395 /* Don't adjust the address if the label is global or weak, or
4396 in a link-once section, since we'll be emitting symbol reloc
4397 references to it which will be patched up by the linker, and
4398 the final value of the symbol may or may not be MIPS16/microMIPS. */
4399 && !S_IS_WEAK (label)
4400 && !S_IS_EXTERNAL (label)
4401 && !s_is_linkonce (label, now_seg))
4402 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
4405 /* Mark preceding MIPS16 or microMIPS instruction labels. */
4408 mips_compressed_mark_labels (void)
4410 struct insn_label_list *l;
4412 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next)
4413 mips_compressed_mark_label (l->label);
4416 /* End the current frag. Make it a variant frag and record the
4420 relax_close_frag (void)
4422 mips_macro_warning.first_frag = frag_now;
4423 frag_var (rs_machine_dependent, 0, 0,
4424 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1],
4425 mips_pic != NO_PIC),
4426 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
4428 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
4429 mips_relax.first_fixup = 0;
4432 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
4433 See the comment above RELAX_ENCODE for more details. */
4436 relax_start (symbolS *symbol)
4438 gas_assert (mips_relax.sequence == 0);
4439 mips_relax.sequence = 1;
4440 mips_relax.symbol = symbol;
4443 /* Start generating the second version of a relaxable sequence.
4444 See the comment above RELAX_ENCODE for more details. */
4449 gas_assert (mips_relax.sequence == 1);
4450 mips_relax.sequence = 2;
4453 /* End the current relaxable sequence. */
4458 gas_assert (mips_relax.sequence == 2);
4459 relax_close_frag ();
4460 mips_relax.sequence = 0;
4463 /* Return true if IP is a delayed branch or jump. */
4465 static inline bfd_boolean
4466 delayed_branch_p (const struct mips_cl_insn *ip)
4468 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
4469 | INSN_COND_BRANCH_DELAY
4470 | INSN_COND_BRANCH_LIKELY)) != 0;
4473 /* Return true if IP is a compact branch or jump. */
4475 static inline bfd_boolean
4476 compact_branch_p (const struct mips_cl_insn *ip)
4478 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
4479 | INSN2_COND_BRANCH)) != 0;
4482 /* Return true if IP is an unconditional branch or jump. */
4484 static inline bfd_boolean
4485 uncond_branch_p (const struct mips_cl_insn *ip)
4487 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
4488 || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0);
4491 /* Return true if IP is a branch-likely instruction. */
4493 static inline bfd_boolean
4494 branch_likely_p (const struct mips_cl_insn *ip)
4496 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
4499 /* Return the type of nop that should be used to fill the delay slot
4500 of delayed branch IP. */
4502 static struct mips_cl_insn *
4503 get_delay_slot_nop (const struct mips_cl_insn *ip)
4505 if (mips_opts.micromips
4506 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
4507 return µmips_nop32_insn;
4511 /* Return a mask that has bit N set if OPCODE reads the register(s)
4515 insn_read_mask (const struct mips_opcode *opcode)
4517 return (opcode->pinfo & INSN_READ_ALL) >> INSN_READ_SHIFT;
4520 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4524 insn_write_mask (const struct mips_opcode *opcode)
4526 return (opcode->pinfo & INSN_WRITE_ALL) >> INSN_WRITE_SHIFT;
4529 /* Return a mask of the registers specified by operand OPERAND of INSN.
4530 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4534 operand_reg_mask (const struct mips_cl_insn *insn,
4535 const struct mips_operand *operand,
4536 unsigned int type_mask)
4538 unsigned int uval, vsel;
4540 switch (operand->type)
4547 case OP_ADDIUSP_INT:
4548 case OP_ENTRY_EXIT_LIST:
4549 case OP_REPEAT_DEST_REG:
4550 case OP_REPEAT_PREV_REG:
4553 case OP_VU0_MATCH_SUFFIX:
4561 case OP_OPTIONAL_REG:
4563 const struct mips_reg_operand *reg_op;
4565 reg_op = (const struct mips_reg_operand *) operand;
4566 if (!(type_mask & (1 << reg_op->reg_type)))
4568 uval = insn_extract_operand (insn, operand);
4569 return 1 << mips_decode_reg_operand (reg_op, uval);
4574 const struct mips_reg_pair_operand *pair_op;
4576 pair_op = (const struct mips_reg_pair_operand *) operand;
4577 if (!(type_mask & (1 << pair_op->reg_type)))
4579 uval = insn_extract_operand (insn, operand);
4580 return (1 << pair_op->reg1_map[uval]) | (1 << pair_op->reg2_map[uval]);
4583 case OP_CLO_CLZ_DEST:
4584 if (!(type_mask & (1 << OP_REG_GP)))
4586 uval = insn_extract_operand (insn, operand);
4587 return (1 << (uval & 31)) | (1 << (uval >> 5));
4590 if (!(type_mask & (1 << OP_REG_GP)))
4592 uval = insn_extract_operand (insn, operand);
4593 gas_assert ((uval & 31) == (uval >> 5));
4594 return 1 << (uval & 31);
4597 case OP_NON_ZERO_REG:
4598 if (!(type_mask & (1 << OP_REG_GP)))
4600 uval = insn_extract_operand (insn, operand);
4601 return 1 << (uval & 31);
4603 case OP_LWM_SWM_LIST:
4606 case OP_SAVE_RESTORE_LIST:
4609 case OP_MDMX_IMM_REG:
4610 if (!(type_mask & (1 << OP_REG_VEC)))
4612 uval = insn_extract_operand (insn, operand);
4614 if ((vsel & 0x18) == 0x18)
4616 return 1 << (uval & 31);
4619 if (!(type_mask & (1 << OP_REG_GP)))
4621 return 1 << insn_extract_operand (insn, operand);
4626 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4627 where bit N of OPNO_MASK is set if operand N should be included.
4628 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4632 insn_reg_mask (const struct mips_cl_insn *insn,
4633 unsigned int type_mask, unsigned int opno_mask)
4635 unsigned int opno, reg_mask;
4639 while (opno_mask != 0)
4642 reg_mask |= operand_reg_mask (insn, insn_opno (insn, opno), type_mask);
4649 /* Return the mask of core registers that IP reads. */
4652 gpr_read_mask (const struct mips_cl_insn *ip)
4654 unsigned long pinfo, pinfo2;
4657 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_read_mask (ip->insn_mo));
4658 pinfo = ip->insn_mo->pinfo;
4659 pinfo2 = ip->insn_mo->pinfo2;
4660 if (pinfo & INSN_UDI)
4662 /* UDI instructions have traditionally been assumed to read RS
4664 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
4665 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
4667 if (pinfo & INSN_READ_GPR_24)
4669 if (pinfo2 & INSN2_READ_GPR_16)
4671 if (pinfo2 & INSN2_READ_SP)
4673 if (pinfo2 & INSN2_READ_GPR_31)
4675 /* Don't include register 0. */
4679 /* Return the mask of core registers that IP writes. */
4682 gpr_write_mask (const struct mips_cl_insn *ip)
4684 unsigned long pinfo, pinfo2;
4687 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_write_mask (ip->insn_mo));
4688 pinfo = ip->insn_mo->pinfo;
4689 pinfo2 = ip->insn_mo->pinfo2;
4690 if (pinfo & INSN_WRITE_GPR_24)
4692 if (pinfo & INSN_WRITE_GPR_31)
4694 if (pinfo & INSN_UDI)
4695 /* UDI instructions have traditionally been assumed to write to RD. */
4696 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
4697 if (pinfo2 & INSN2_WRITE_SP)
4699 /* Don't include register 0. */
4703 /* Return the mask of floating-point registers that IP reads. */
4706 fpr_read_mask (const struct mips_cl_insn *ip)
4708 unsigned long pinfo;
4711 mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC)
4712 | (1 << OP_REG_MSA)),
4713 insn_read_mask (ip->insn_mo));
4714 pinfo = ip->insn_mo->pinfo;
4715 /* Conservatively treat all operands to an FP_D instruction are doubles.
4716 (This is overly pessimistic for things like cvt.d.s.) */
4717 if (FPR_SIZE != 64 && (pinfo & FP_D))
4722 /* Return the mask of floating-point registers that IP writes. */
4725 fpr_write_mask (const struct mips_cl_insn *ip)
4727 unsigned long pinfo;
4730 mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC)
4731 | (1 << OP_REG_MSA)),
4732 insn_write_mask (ip->insn_mo));
4733 pinfo = ip->insn_mo->pinfo;
4734 /* Conservatively treat all operands to an FP_D instruction are doubles.
4735 (This is overly pessimistic for things like cvt.s.d.) */
4736 if (FPR_SIZE != 64 && (pinfo & FP_D))
4741 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4742 Check whether that is allowed. */
4745 mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum)
4747 const char *s = insn->name;
4748 bfd_boolean oddspreg = (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa, mips_opts.arch)
4750 && mips_opts.oddspreg;
4752 if (insn->pinfo == INSN_MACRO)
4753 /* Let a macro pass, we'll catch it later when it is expanded. */
4756 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4757 otherwise it depends on oddspreg. */
4758 if ((insn->pinfo & FP_S)
4759 && (insn->pinfo & (INSN_LOAD_MEMORY | INSN_STORE_MEMORY
4760 | INSN_LOAD_COPROC | INSN_COPROC_MOVE)))
4761 return FPR_SIZE == 32 || oddspreg;
4763 /* Allow odd registers for single-precision ops and double-precision if the
4764 floating-point registers are 64-bit wide. */
4765 switch (insn->pinfo & (FP_S | FP_D))
4771 return FPR_SIZE == 64;
4776 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4777 s = strchr (insn->name, '.');
4778 if (s != NULL && opnum == 2)
4779 s = strchr (s + 1, '.');
4780 if (s != NULL && (s[1] == 'w' || s[1] == 's'))
4783 return FPR_SIZE == 64;
4786 /* Information about an instruction argument that we're trying to match. */
4787 struct mips_arg_info
4789 /* The instruction so far. */
4790 struct mips_cl_insn *insn;
4792 /* The first unconsumed operand token. */
4793 struct mips_operand_token *token;
4795 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4798 /* The 1-based argument number, for error reporting. This does not
4799 count elided optional registers, etc.. */
4802 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4803 unsigned int last_regno;
4805 /* If the first operand was an OP_REG, this is the register that it
4806 specified, otherwise it is ILLEGAL_REG. */
4807 unsigned int dest_regno;
4809 /* The value of the last OP_INT operand. Only used for OP_MSB,
4810 where it gives the lsb position. */
4811 unsigned int last_op_int;
4813 /* If true, match routines should assume that no later instruction
4814 alternative matches and should therefore be as accommodating as
4815 possible. Match routines should not report errors if something
4816 is only invalid for !LAX_MATCH. */
4817 bfd_boolean lax_match;
4819 /* True if a reference to the current AT register was seen. */
4820 bfd_boolean seen_at;
4823 /* Record that the argument is out of range. */
4826 match_out_of_range (struct mips_arg_info *arg)
4828 set_insn_error_i (arg->argnum, _("operand %d out of range"), arg->argnum);
4831 /* Record that the argument isn't constant but needs to be. */
4834 match_not_constant (struct mips_arg_info *arg)
4836 set_insn_error_i (arg->argnum, _("operand %d must be constant"),
4840 /* Try to match an OT_CHAR token for character CH. Consume the token
4841 and return true on success, otherwise return false. */
4844 match_char (struct mips_arg_info *arg, char ch)
4846 if (arg->token->type == OT_CHAR && arg->token->u.ch == ch)
4856 /* Try to get an expression from the next tokens in ARG. Consume the
4857 tokens and return true on success, storing the expression value in
4858 VALUE and relocation types in R. */
4861 match_expression (struct mips_arg_info *arg, expressionS *value,
4862 bfd_reloc_code_real_type *r)
4864 /* If the next token is a '(' that was parsed as being part of a base
4865 expression, assume we have an elided offset. The later match will fail
4866 if this turns out to be wrong. */
4867 if (arg->token->type == OT_CHAR && arg->token->u.ch == '(')
4869 value->X_op = O_constant;
4870 value->X_add_number = 0;
4871 r[0] = r[1] = r[2] = BFD_RELOC_UNUSED;
4875 /* Reject register-based expressions such as "0+$2" and "(($2))".
4876 For plain registers the default error seems more appropriate. */
4877 if (arg->token->type == OT_INTEGER
4878 && arg->token->u.integer.value.X_op == O_register)
4880 set_insn_error (arg->argnum, _("register value used as expression"));
4884 if (arg->token->type == OT_INTEGER)
4886 *value = arg->token->u.integer.value;
4887 memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r));
4893 (arg->argnum, _("operand %d must be an immediate expression"),
4898 /* Try to get a constant expression from the next tokens in ARG. Consume
4899 the tokens and return true on success, storing the constant value
4903 match_const_int (struct mips_arg_info *arg, offsetT *value)
4906 bfd_reloc_code_real_type r[3];
4908 if (!match_expression (arg, &ex, r))
4911 if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant)
4912 *value = ex.X_add_number;
4915 if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_big)
4916 match_out_of_range (arg);
4918 match_not_constant (arg);
4924 /* Return the RTYPE_* flags for a register operand of type TYPE that
4925 appears in instruction OPCODE. */
4928 convert_reg_type (const struct mips_opcode *opcode,
4929 enum mips_reg_operand_type type)
4934 return RTYPE_NUM | RTYPE_GP;
4937 /* Allow vector register names for MDMX if the instruction is a 64-bit
4938 FPR load, store or move (including moves to and from GPRs). */
4939 if ((mips_opts.ase & ASE_MDMX)
4940 && (opcode->pinfo & FP_D)
4941 && (opcode->pinfo & (INSN_COPROC_MOVE
4942 | INSN_COPROC_MEMORY_DELAY
4945 | INSN_STORE_MEMORY)))
4946 return RTYPE_FPU | RTYPE_VEC;
4950 if (opcode->pinfo & (FP_D | FP_S))
4951 return RTYPE_CCC | RTYPE_FCC;
4955 if (opcode->membership & INSN_5400)
4957 return RTYPE_FPU | RTYPE_VEC;
4963 if (opcode->name[strlen (opcode->name) - 1] == '0')
4964 return RTYPE_NUM | RTYPE_CP0;
4971 return RTYPE_NUM | RTYPE_VI;
4974 return RTYPE_NUM | RTYPE_VF;
4976 case OP_REG_R5900_I:
4977 return RTYPE_R5900_I;
4979 case OP_REG_R5900_Q:
4980 return RTYPE_R5900_Q;
4982 case OP_REG_R5900_R:
4983 return RTYPE_R5900_R;
4985 case OP_REG_R5900_ACC:
4986 return RTYPE_R5900_ACC;
4991 case OP_REG_MSA_CTRL:
4997 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
5000 check_regno (struct mips_arg_info *arg,
5001 enum mips_reg_operand_type type, unsigned int regno)
5003 if (AT && type == OP_REG_GP && regno == AT)
5004 arg->seen_at = TRUE;
5006 if (type == OP_REG_FP
5008 && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum))
5010 /* This was a warning prior to introducing O32 FPXX and FP64 support
5011 so maintain a warning for FP32 but raise an error for the new
5014 as_warn (_("float register should be even, was %d"), regno);
5016 as_bad (_("float register should be even, was %d"), regno);
5019 if (type == OP_REG_CCC)
5024 name = arg->insn->insn_mo->name;
5025 length = strlen (name);
5026 if ((regno & 1) != 0
5027 && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0)
5028 || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0)))
5029 as_warn (_("condition code register should be even for %s, was %d"),
5032 if ((regno & 3) != 0
5033 && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0))
5034 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
5039 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
5040 a register of type TYPE. Return true on success, storing the register
5041 number in *REGNO and warning about any dubious uses. */
5044 match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type,
5045 unsigned int symval, unsigned int *regno)
5047 if (type == OP_REG_VEC)
5048 symval = mips_prefer_vec_regno (symval);
5049 if (!(symval & convert_reg_type (arg->insn->insn_mo, type)))
5052 *regno = symval & RNUM_MASK;
5053 check_regno (arg, type, *regno);
5057 /* Try to interpret the next token in ARG as a register of type TYPE.
5058 Consume the token and return true on success, storing the register
5059 number in *REGNO. Return false on failure. */
5062 match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type,
5063 unsigned int *regno)
5065 if (arg->token->type == OT_REG
5066 && match_regno (arg, type, arg->token->u.regno, regno))
5074 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
5075 Consume the token and return true on success, storing the register numbers
5076 in *REGNO1 and *REGNO2. Return false on failure. */
5079 match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type,
5080 unsigned int *regno1, unsigned int *regno2)
5082 if (match_reg (arg, type, regno1))
5087 if (arg->token->type == OT_REG_RANGE
5088 && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1)
5089 && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2)
5090 && *regno1 <= *regno2)
5098 /* OP_INT matcher. */
5101 match_int_operand (struct mips_arg_info *arg,
5102 const struct mips_operand *operand_base)
5104 const struct mips_int_operand *operand;
5106 int min_val, max_val, factor;
5109 operand = (const struct mips_int_operand *) operand_base;
5110 factor = 1 << operand->shift;
5111 min_val = mips_int_operand_min (operand);
5112 max_val = mips_int_operand_max (operand);
5114 if (operand_base->lsb == 0
5115 && operand_base->size == 16
5116 && operand->shift == 0
5117 && operand->bias == 0
5118 && (operand->max_val == 32767 || operand->max_val == 65535))
5120 /* The operand can be relocated. */
5121 if (!match_expression (arg, &offset_expr, offset_reloc))
5124 if (offset_expr.X_op == O_big)
5126 match_out_of_range (arg);
5130 if (offset_reloc[0] != BFD_RELOC_UNUSED)
5131 /* Relocation operators were used. Accept the argument and
5132 leave the relocation value in offset_expr and offset_relocs
5133 for the caller to process. */
5136 if (offset_expr.X_op != O_constant)
5138 /* Accept non-constant operands if no later alternative matches,
5139 leaving it for the caller to process. */
5140 if (!arg->lax_match)
5142 match_not_constant (arg);
5145 offset_reloc[0] = BFD_RELOC_LO16;
5149 /* Clear the global state; we're going to install the operand
5151 sval = offset_expr.X_add_number;
5152 offset_expr.X_op = O_absent;
5154 /* For compatibility with older assemblers, we accept
5155 0x8000-0xffff as signed 16-bit numbers when only
5156 signed numbers are allowed. */
5159 max_val = ((1 << operand_base->size) - 1) << operand->shift;
5160 if (!arg->lax_match && sval <= max_val)
5162 match_out_of_range (arg);
5169 if (!match_const_int (arg, &sval))
5173 arg->last_op_int = sval;
5175 if (sval < min_val || sval > max_val || sval % factor)
5177 match_out_of_range (arg);
5181 uval = (unsigned int) sval >> operand->shift;
5182 uval -= operand->bias;
5184 /* Handle -mfix-cn63xxp1. */
5186 && mips_fix_cn63xxp1
5187 && !mips_opts.micromips
5188 && strcmp ("pref", arg->insn->insn_mo->name) == 0)
5203 /* The rest must be changed to 28. */
5208 insn_insert_operand (arg->insn, operand_base, uval);
5212 /* OP_MAPPED_INT matcher. */
5215 match_mapped_int_operand (struct mips_arg_info *arg,
5216 const struct mips_operand *operand_base)
5218 const struct mips_mapped_int_operand *operand;
5219 unsigned int uval, num_vals;
5222 operand = (const struct mips_mapped_int_operand *) operand_base;
5223 if (!match_const_int (arg, &sval))
5226 num_vals = 1 << operand_base->size;
5227 for (uval = 0; uval < num_vals; uval++)
5228 if (operand->int_map[uval] == sval)
5230 if (uval == num_vals)
5232 match_out_of_range (arg);
5236 insn_insert_operand (arg->insn, operand_base, uval);
5240 /* OP_MSB matcher. */
5243 match_msb_operand (struct mips_arg_info *arg,
5244 const struct mips_operand *operand_base)
5246 const struct mips_msb_operand *operand;
5247 int min_val, max_val, max_high;
5248 offsetT size, sval, high;
5250 operand = (const struct mips_msb_operand *) operand_base;
5251 min_val = operand->bias;
5252 max_val = min_val + (1 << operand_base->size) - 1;
5253 max_high = operand->opsize;
5255 if (!match_const_int (arg, &size))
5258 high = size + arg->last_op_int;
5259 sval = operand->add_lsb ? high : size;
5261 if (size < 0 || high > max_high || sval < min_val || sval > max_val)
5263 match_out_of_range (arg);
5266 insn_insert_operand (arg->insn, operand_base, sval - min_val);
5270 /* OP_REG matcher. */
5273 match_reg_operand (struct mips_arg_info *arg,
5274 const struct mips_operand *operand_base)
5276 const struct mips_reg_operand *operand;
5277 unsigned int regno, uval, num_vals;
5279 operand = (const struct mips_reg_operand *) operand_base;
5280 if (!match_reg (arg, operand->reg_type, ®no))
5283 if (operand->reg_map)
5285 num_vals = 1 << operand->root.size;
5286 for (uval = 0; uval < num_vals; uval++)
5287 if (operand->reg_map[uval] == regno)
5289 if (num_vals == uval)
5295 arg->last_regno = regno;
5296 if (arg->opnum == 1)
5297 arg->dest_regno = regno;
5298 insn_insert_operand (arg->insn, operand_base, uval);
5302 /* OP_REG_PAIR matcher. */
5305 match_reg_pair_operand (struct mips_arg_info *arg,
5306 const struct mips_operand *operand_base)
5308 const struct mips_reg_pair_operand *operand;
5309 unsigned int regno1, regno2, uval, num_vals;
5311 operand = (const struct mips_reg_pair_operand *) operand_base;
5312 if (!match_reg (arg, operand->reg_type, ®no1)
5313 || !match_char (arg, ',')
5314 || !match_reg (arg, operand->reg_type, ®no2))
5317 num_vals = 1 << operand_base->size;
5318 for (uval = 0; uval < num_vals; uval++)
5319 if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2)
5321 if (uval == num_vals)
5324 insn_insert_operand (arg->insn, operand_base, uval);
5328 /* OP_PCREL matcher. The caller chooses the relocation type. */
5331 match_pcrel_operand (struct mips_arg_info *arg)
5333 bfd_reloc_code_real_type r[3];
5335 return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED;
5338 /* OP_PERF_REG matcher. */
5341 match_perf_reg_operand (struct mips_arg_info *arg,
5342 const struct mips_operand *operand)
5346 if (!match_const_int (arg, &sval))
5351 || (mips_opts.arch == CPU_R5900
5352 && (strcmp (arg->insn->insn_mo->name, "mfps") == 0
5353 || strcmp (arg->insn->insn_mo->name, "mtps") == 0))))
5355 set_insn_error (arg->argnum, _("invalid performance register"));
5359 insn_insert_operand (arg->insn, operand, sval);
5363 /* OP_ADDIUSP matcher. */
5366 match_addiusp_operand (struct mips_arg_info *arg,
5367 const struct mips_operand *operand)
5372 if (!match_const_int (arg, &sval))
5377 match_out_of_range (arg);
5382 if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1))
5384 match_out_of_range (arg);
5388 uval = (unsigned int) sval;
5389 uval = ((uval >> 1) & ~0xff) | (uval & 0xff);
5390 insn_insert_operand (arg->insn, operand, uval);
5394 /* OP_CLO_CLZ_DEST matcher. */
5397 match_clo_clz_dest_operand (struct mips_arg_info *arg,
5398 const struct mips_operand *operand)
5402 if (!match_reg (arg, OP_REG_GP, ®no))
5405 insn_insert_operand (arg->insn, operand, regno | (regno << 5));
5409 /* OP_CHECK_PREV matcher. */
5412 match_check_prev_operand (struct mips_arg_info *arg,
5413 const struct mips_operand *operand_base)
5415 const struct mips_check_prev_operand *operand;
5418 operand = (const struct mips_check_prev_operand *) operand_base;
5420 if (!match_reg (arg, OP_REG_GP, ®no))
5423 if (!operand->zero_ok && regno == 0)
5426 if ((operand->less_than_ok && regno < arg->last_regno)
5427 || (operand->greater_than_ok && regno > arg->last_regno)
5428 || (operand->equal_ok && regno == arg->last_regno))
5430 arg->last_regno = regno;
5431 insn_insert_operand (arg->insn, operand_base, regno);
5438 /* OP_SAME_RS_RT matcher. */
5441 match_same_rs_rt_operand (struct mips_arg_info *arg,
5442 const struct mips_operand *operand)
5446 if (!match_reg (arg, OP_REG_GP, ®no))
5451 set_insn_error (arg->argnum, _("the source register must not be $0"));
5455 arg->last_regno = regno;
5457 insn_insert_operand (arg->insn, operand, regno | (regno << 5));
5461 /* OP_LWM_SWM_LIST matcher. */
5464 match_lwm_swm_list_operand (struct mips_arg_info *arg,
5465 const struct mips_operand *operand)
5467 unsigned int reglist, sregs, ra, regno1, regno2;
5468 struct mips_arg_info reset;
5471 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
5475 if (regno2 == FP && regno1 >= S0 && regno1 <= S7)
5480 reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1);
5483 while (match_char (arg, ',')
5484 && match_reg_range (arg, OP_REG_GP, ®no1, ®no2));
5487 if (operand->size == 2)
5489 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5495 and any permutations of these. */
5496 if ((reglist & 0xfff1ffff) != 0x80010000)
5499 sregs = (reglist >> 17) & 7;
5504 /* The list must include at least one of ra and s0-sN,
5505 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5506 which are $23 and $30 respectively.) E.g.:
5514 and any permutations of these. */
5515 if ((reglist & 0x3f00ffff) != 0)
5518 ra = (reglist >> 27) & 0x10;
5519 sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
5522 if ((sregs & -sregs) != sregs)
5525 insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra);
5529 /* OP_ENTRY_EXIT_LIST matcher. */
5532 match_entry_exit_operand (struct mips_arg_info *arg,
5533 const struct mips_operand *operand)
5536 bfd_boolean is_exit;
5538 /* The format is the same for both ENTRY and EXIT, but the constraints
5540 is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0;
5541 mask = (is_exit ? 7 << 3 : 0);
5544 unsigned int regno1, regno2;
5545 bfd_boolean is_freg;
5547 if (match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
5549 else if (match_reg_range (arg, OP_REG_FP, ®no1, ®no2))
5554 if (is_exit && is_freg && regno1 == 0 && regno2 < 2)
5557 mask |= (5 + regno2) << 3;
5559 else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7)
5560 mask |= (regno2 - 3) << 3;
5561 else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17)
5562 mask |= (regno2 - 15) << 1;
5563 else if (regno1 == RA && regno2 == RA)
5568 while (match_char (arg, ','));
5570 insn_insert_operand (arg->insn, operand, mask);
5574 /* Encode regular MIPS SAVE/RESTORE instruction operands according to
5575 the argument register mask AMASK, the number of static registers
5576 saved NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5577 respectively, and the frame size FRAME_SIZE. */
5580 mips_encode_save_restore (unsigned int amask, unsigned int nsreg,
5581 unsigned int ra, unsigned int s0, unsigned int s1,
5582 unsigned int frame_size)
5584 return ((nsreg << 23) | ((frame_size & 0xf0) << 15) | (amask << 15)
5585 | (ra << 12) | (s0 << 11) | (s1 << 10) | ((frame_size & 0xf) << 6));
5588 /* Encode MIPS16 SAVE/RESTORE instruction operands according to the
5589 argument register mask AMASK, the number of static registers saved
5590 NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5591 respectively, and the frame size FRAME_SIZE. */
5594 mips16_encode_save_restore (unsigned int amask, unsigned int nsreg,
5595 unsigned int ra, unsigned int s0, unsigned int s1,
5596 unsigned int frame_size)
5600 args = (ra << 6) | (s0 << 5) | (s1 << 4) | (frame_size & 0xf);
5601 if (nsreg || amask || frame_size == 0 || frame_size > 16)
5602 args |= (MIPS16_EXTEND | (nsreg << 24) | (amask << 16)
5603 | ((frame_size & 0xf0) << 16));
5607 /* OP_SAVE_RESTORE_LIST matcher. */
5610 match_save_restore_list_operand (struct mips_arg_info *arg)
5612 unsigned int opcode, args, statics, sregs;
5613 unsigned int num_frame_sizes, num_args, num_statics, num_sregs;
5614 unsigned int arg_mask, ra, s0, s1;
5617 opcode = arg->insn->insn_opcode;
5619 num_frame_sizes = 0;
5628 unsigned int regno1, regno2;
5630 if (arg->token->type == OT_INTEGER)
5632 /* Handle the frame size. */
5633 if (!match_const_int (arg, &frame_size))
5635 num_frame_sizes += 1;
5639 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
5642 while (regno1 <= regno2)
5644 if (regno1 >= 4 && regno1 <= 7)
5646 if (num_frame_sizes == 0)
5648 args |= 1 << (regno1 - 4);
5650 /* statics $a0-$a3 */
5651 statics |= 1 << (regno1 - 4);
5653 else if (regno1 >= 16 && regno1 <= 23)
5655 sregs |= 1 << (regno1 - 16);
5656 else if (regno1 == 30)
5659 else if (regno1 == 31)
5660 /* Add $ra to insn. */
5670 while (match_char (arg, ','));
5672 /* Encode args/statics combination. */
5675 else if (args == 0xf)
5676 /* All $a0-$a3 are args. */
5677 arg_mask = MIPS_SVRS_ALL_ARGS;
5678 else if (statics == 0xf)
5679 /* All $a0-$a3 are statics. */
5680 arg_mask = MIPS_SVRS_ALL_STATICS;
5683 /* Count arg registers. */
5693 /* Count static registers. */
5695 while (statics & 0x8)
5697 statics = (statics << 1) & 0xf;
5703 /* Encode args/statics. */
5704 arg_mask = (num_args << 2) | num_statics;
5707 /* Encode $s0/$s1. */
5708 if (sregs & (1 << 0)) /* $s0 */
5710 if (sregs & (1 << 1)) /* $s1 */
5714 /* Encode $s2-$s8. */
5724 /* Encode frame size. */
5725 if (num_frame_sizes == 0)
5727 set_insn_error (arg->argnum, _("missing frame size"));
5730 if (num_frame_sizes > 1)
5732 set_insn_error (arg->argnum, _("frame size specified twice"));
5735 if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8)
5737 set_insn_error (arg->argnum, _("invalid frame size"));
5742 /* Finally build the instruction. */
5743 if (mips_opts.mips16)
5744 opcode |= mips16_encode_save_restore (arg_mask, num_sregs, ra, s0, s1,
5746 else if (!mips_opts.micromips)
5747 opcode |= mips_encode_save_restore (arg_mask, num_sregs, ra, s0, s1,
5752 arg->insn->insn_opcode = opcode;
5756 /* OP_MDMX_IMM_REG matcher. */
5759 match_mdmx_imm_reg_operand (struct mips_arg_info *arg,
5760 const struct mips_operand *operand)
5762 unsigned int regno, uval;
5764 const struct mips_opcode *opcode;
5766 /* The mips_opcode records whether this is an octobyte or quadhalf
5767 instruction. Start out with that bit in place. */
5768 opcode = arg->insn->insn_mo;
5769 uval = mips_extract_operand (operand, opcode->match);
5770 is_qh = (uval != 0);
5772 if (arg->token->type == OT_REG)
5774 if ((opcode->membership & INSN_5400)
5775 && strcmp (opcode->name, "rzu.ob") == 0)
5777 set_insn_error_i (arg->argnum, _("operand %d must be an immediate"),
5782 if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no))
5786 /* Check whether this is a vector register or a broadcast of
5787 a single element. */
5788 if (arg->token->type == OT_INTEGER_INDEX)
5790 if (arg->token->u.index > (is_qh ? 3 : 7))
5792 set_insn_error (arg->argnum, _("invalid element selector"));
5795 uval |= arg->token->u.index << (is_qh ? 2 : 1) << 5;
5800 /* A full vector. */
5801 if ((opcode->membership & INSN_5400)
5802 && (strcmp (opcode->name, "sll.ob") == 0
5803 || strcmp (opcode->name, "srl.ob") == 0))
5805 set_insn_error_i (arg->argnum, _("operand %d must be scalar"),
5811 uval |= MDMX_FMTSEL_VEC_QH << 5;
5813 uval |= MDMX_FMTSEL_VEC_OB << 5;
5821 if (!match_const_int (arg, &sval))
5823 if (sval < 0 || sval > 31)
5825 match_out_of_range (arg);
5828 uval |= (sval & 31);
5830 uval |= MDMX_FMTSEL_IMM_QH << 5;
5832 uval |= MDMX_FMTSEL_IMM_OB << 5;
5834 insn_insert_operand (arg->insn, operand, uval);
5838 /* OP_IMM_INDEX matcher. */
5841 match_imm_index_operand (struct mips_arg_info *arg,
5842 const struct mips_operand *operand)
5844 unsigned int max_val;
5846 if (arg->token->type != OT_INTEGER_INDEX)
5849 max_val = (1 << operand->size) - 1;
5850 if (arg->token->u.index > max_val)
5852 match_out_of_range (arg);
5855 insn_insert_operand (arg->insn, operand, arg->token->u.index);
5860 /* OP_REG_INDEX matcher. */
5863 match_reg_index_operand (struct mips_arg_info *arg,
5864 const struct mips_operand *operand)
5868 if (arg->token->type != OT_REG_INDEX)
5871 if (!match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no))
5874 insn_insert_operand (arg->insn, operand, regno);
5879 /* OP_PC matcher. */
5882 match_pc_operand (struct mips_arg_info *arg)
5884 if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC))
5892 /* OP_REG28 matcher. */
5895 match_reg28_operand (struct mips_arg_info *arg)
5899 if (arg->token->type == OT_REG
5900 && match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no)
5909 /* OP_NON_ZERO_REG matcher. */
5912 match_non_zero_reg_operand (struct mips_arg_info *arg,
5913 const struct mips_operand *operand)
5917 if (!match_reg (arg, OP_REG_GP, ®no))
5923 arg->last_regno = regno;
5924 insn_insert_operand (arg->insn, operand, regno);
5928 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5929 register that we need to match. */
5932 match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno)
5936 return match_reg (arg, OP_REG_GP, ®no) && regno == other_regno;
5939 /* Try to match a floating-point constant from ARG for LI.S or LI.D.
5940 LENGTH is the length of the value in bytes (4 for float, 8 for double)
5941 and USING_GPRS says whether the destination is a GPR rather than an FPR.
5943 Return the constant in IMM and OFFSET as follows:
5945 - If the constant should be loaded via memory, set IMM to O_absent and
5946 OFFSET to the memory address.
5948 - Otherwise, if the constant should be loaded into two 32-bit registers,
5949 set IMM to the O_constant to load into the high register and OFFSET
5950 to the corresponding value for the low register.
5952 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5954 These constants only appear as the last operand in an instruction,
5955 and every instruction that accepts them in any variant accepts them
5956 in all variants. This means we don't have to worry about backing out
5957 any changes if the instruction does not match. We just match
5958 unconditionally and report an error if the constant is invalid. */
5961 match_float_constant (struct mips_arg_info *arg, expressionS *imm,
5962 expressionS *offset, int length, bfd_boolean using_gprs)
5967 const char *newname;
5968 unsigned char *data;
5970 /* Where the constant is placed is based on how the MIPS assembler
5973 length == 4 && using_gprs -- immediate value only
5974 length == 8 && using_gprs -- .rdata or immediate value
5975 length == 4 && !using_gprs -- .lit4 or immediate value
5976 length == 8 && !using_gprs -- .lit8 or immediate value
5978 The .lit4 and .lit8 sections are only used if permitted by the
5980 if (arg->token->type != OT_FLOAT)
5982 set_insn_error (arg->argnum, _("floating-point expression required"));
5986 gas_assert (arg->token->u.flt.length == length);
5987 data = arg->token->u.flt.data;
5990 /* Handle 32-bit constants for which an immediate value is best. */
5993 || g_switch_value < 4
5994 || (data[0] == 0 && data[1] == 0)
5995 || (data[2] == 0 && data[3] == 0)))
5997 imm->X_op = O_constant;
5998 if (!target_big_endian)
5999 imm->X_add_number = bfd_getl32 (data);
6001 imm->X_add_number = bfd_getb32 (data);
6002 offset->X_op = O_absent;
6006 /* Handle 64-bit constants for which an immediate value is best. */
6008 && !mips_disable_float_construction
6009 /* Constants can only be constructed in GPRs and copied to FPRs if the
6010 GPRs are at least as wide as the FPRs or MTHC1 is available.
6011 Unlike most tests for 32-bit floating-point registers this check
6012 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
6013 permit 64-bit moves without MXHC1.
6014 Force the constant into memory otherwise. */
6017 || ISA_HAS_MXHC1 (mips_opts.isa)
6019 && ((data[0] == 0 && data[1] == 0)
6020 || (data[2] == 0 && data[3] == 0))
6021 && ((data[4] == 0 && data[5] == 0)
6022 || (data[6] == 0 && data[7] == 0)))
6024 /* The value is simple enough to load with a couple of instructions.
6025 If using 32-bit registers, set IMM to the high order 32 bits and
6026 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
6028 if (GPR_SIZE == 32 || (!using_gprs && FPR_SIZE != 64))
6030 imm->X_op = O_constant;
6031 offset->X_op = O_constant;
6032 if (!target_big_endian)
6034 imm->X_add_number = bfd_getl32 (data + 4);
6035 offset->X_add_number = bfd_getl32 (data);
6039 imm->X_add_number = bfd_getb32 (data);
6040 offset->X_add_number = bfd_getb32 (data + 4);
6042 if (offset->X_add_number == 0)
6043 offset->X_op = O_absent;
6047 imm->X_op = O_constant;
6048 if (!target_big_endian)
6049 imm->X_add_number = bfd_getl64 (data);
6051 imm->X_add_number = bfd_getb64 (data);
6052 offset->X_op = O_absent;
6057 /* Switch to the right section. */
6059 subseg = now_subseg;
6062 gas_assert (!using_gprs && g_switch_value >= 4);
6067 if (using_gprs || g_switch_value < 8)
6068 newname = RDATA_SECTION_NAME;
6073 new_seg = subseg_new (newname, (subsegT) 0);
6074 bfd_set_section_flags (stdoutput, new_seg,
6075 SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA);
6076 frag_align (length == 4 ? 2 : 3, 0, 0);
6077 if (strncmp (TARGET_OS, "elf", 3) != 0)
6078 record_alignment (new_seg, 4);
6080 record_alignment (new_seg, length == 4 ? 2 : 3);
6082 as_bad (_("cannot use `%s' in this section"), arg->insn->insn_mo->name);
6084 /* Set the argument to the current address in the section. */
6085 imm->X_op = O_absent;
6086 offset->X_op = O_symbol;
6087 offset->X_add_symbol = symbol_temp_new_now ();
6088 offset->X_add_number = 0;
6090 /* Put the floating point number into the section. */
6091 p = frag_more (length);
6092 memcpy (p, data, length);
6094 /* Switch back to the original section. */
6095 subseg_set (seg, subseg);
6099 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
6103 match_vu0_suffix_operand (struct mips_arg_info *arg,
6104 const struct mips_operand *operand,
6105 bfd_boolean match_p)
6109 /* The operand can be an XYZW mask or a single 2-bit channel index
6110 (with X being 0). */
6111 gas_assert (operand->size == 2 || operand->size == 4);
6113 /* The suffix can be omitted when it is already part of the opcode. */
6114 if (arg->token->type != OT_CHANNELS)
6117 uval = arg->token->u.channels;
6118 if (operand->size == 2)
6120 /* Check that a single bit is set and convert it into a 2-bit index. */
6121 if ((uval & -uval) != uval)
6123 uval = 4 - ffs (uval);
6126 if (match_p && insn_extract_operand (arg->insn, operand) != uval)
6131 insn_insert_operand (arg->insn, operand, uval);
6135 /* Try to match a token from ARG against OPERAND. Consume the token
6136 and return true on success, otherwise return false. */
6139 match_operand (struct mips_arg_info *arg,
6140 const struct mips_operand *operand)
6142 switch (operand->type)
6145 return match_int_operand (arg, operand);
6148 return match_mapped_int_operand (arg, operand);
6151 return match_msb_operand (arg, operand);
6154 case OP_OPTIONAL_REG:
6155 return match_reg_operand (arg, operand);
6158 return match_reg_pair_operand (arg, operand);
6161 return match_pcrel_operand (arg);
6164 return match_perf_reg_operand (arg, operand);
6166 case OP_ADDIUSP_INT:
6167 return match_addiusp_operand (arg, operand);
6169 case OP_CLO_CLZ_DEST:
6170 return match_clo_clz_dest_operand (arg, operand);
6172 case OP_LWM_SWM_LIST:
6173 return match_lwm_swm_list_operand (arg, operand);
6175 case OP_ENTRY_EXIT_LIST:
6176 return match_entry_exit_operand (arg, operand);
6178 case OP_SAVE_RESTORE_LIST:
6179 return match_save_restore_list_operand (arg);
6181 case OP_MDMX_IMM_REG:
6182 return match_mdmx_imm_reg_operand (arg, operand);
6184 case OP_REPEAT_DEST_REG:
6185 return match_tied_reg_operand (arg, arg->dest_regno);
6187 case OP_REPEAT_PREV_REG:
6188 return match_tied_reg_operand (arg, arg->last_regno);
6191 return match_pc_operand (arg);
6194 return match_reg28_operand (arg);
6197 return match_vu0_suffix_operand (arg, operand, FALSE);
6199 case OP_VU0_MATCH_SUFFIX:
6200 return match_vu0_suffix_operand (arg, operand, TRUE);
6203 return match_imm_index_operand (arg, operand);
6206 return match_reg_index_operand (arg, operand);
6209 return match_same_rs_rt_operand (arg, operand);
6212 return match_check_prev_operand (arg, operand);
6214 case OP_NON_ZERO_REG:
6215 return match_non_zero_reg_operand (arg, operand);
6220 /* ARG is the state after successfully matching an instruction.
6221 Issue any queued-up warnings. */
6224 check_completed_insn (struct mips_arg_info *arg)
6229 as_warn (_("used $at without \".set noat\""));
6231 as_warn (_("used $%u with \".set at=$%u\""), AT, AT);
6235 /* Return true if modifying general-purpose register REG needs a delay. */
6238 reg_needs_delay (unsigned int reg)
6240 unsigned long prev_pinfo;
6242 prev_pinfo = history[0].insn_mo->pinfo;
6243 if (!mips_opts.noreorder
6244 && (((prev_pinfo & INSN_LOAD_MEMORY) && !gpr_interlocks)
6245 || ((prev_pinfo & INSN_LOAD_COPROC) && !cop_interlocks))
6246 && (gpr_write_mask (&history[0]) & (1 << reg)))
6252 /* Classify an instruction according to the FIX_VR4120_* enumeration.
6253 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6254 by VR4120 errata. */
6257 classify_vr4120_insn (const char *name)
6259 if (strncmp (name, "macc", 4) == 0)
6260 return FIX_VR4120_MACC;
6261 if (strncmp (name, "dmacc", 5) == 0)
6262 return FIX_VR4120_DMACC;
6263 if (strncmp (name, "mult", 4) == 0)
6264 return FIX_VR4120_MULT;
6265 if (strncmp (name, "dmult", 5) == 0)
6266 return FIX_VR4120_DMULT;
6267 if (strstr (name, "div"))
6268 return FIX_VR4120_DIV;
6269 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
6270 return FIX_VR4120_MTHILO;
6271 return NUM_FIX_VR4120_CLASSES;
6274 #define INSN_ERET 0x42000018
6275 #define INSN_DERET 0x4200001f
6276 #define INSN_DMULT 0x1c
6277 #define INSN_DMULTU 0x1d
6279 /* Return the number of instructions that must separate INSN1 and INSN2,
6280 where INSN1 is the earlier instruction. Return the worst-case value
6281 for any INSN2 if INSN2 is null. */
6284 insns_between (const struct mips_cl_insn *insn1,
6285 const struct mips_cl_insn *insn2)
6287 unsigned long pinfo1, pinfo2;
6290 /* If INFO2 is null, pessimistically assume that all flags are set for
6291 the second instruction. */
6292 pinfo1 = insn1->insn_mo->pinfo;
6293 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
6295 /* For most targets, write-after-read dependencies on the HI and LO
6296 registers must be separated by at least two instructions. */
6297 if (!hilo_interlocks)
6299 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
6301 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
6305 /* If we're working around r7000 errata, there must be two instructions
6306 between an mfhi or mflo and any instruction that uses the result. */
6307 if (mips_7000_hilo_fix
6308 && !mips_opts.micromips
6309 && MF_HILO_INSN (pinfo1)
6310 && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))))
6313 /* If we're working around 24K errata, one instruction is required
6314 if an ERET or DERET is followed by a branch instruction. */
6315 if (mips_fix_24k && !mips_opts.micromips)
6317 if (insn1->insn_opcode == INSN_ERET
6318 || insn1->insn_opcode == INSN_DERET)
6321 || insn2->insn_opcode == INSN_ERET
6322 || insn2->insn_opcode == INSN_DERET
6323 || delayed_branch_p (insn2))
6328 /* If we're working around PMC RM7000 errata, there must be three
6329 nops between a dmult and a load instruction. */
6330 if (mips_fix_rm7000 && !mips_opts.micromips)
6332 if ((insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULT
6333 || (insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULTU)
6335 if (pinfo2 & INSN_LOAD_MEMORY)
6340 /* If working around VR4120 errata, check for combinations that need
6341 a single intervening instruction. */
6342 if (mips_fix_vr4120 && !mips_opts.micromips)
6344 unsigned int class1, class2;
6346 class1 = classify_vr4120_insn (insn1->insn_mo->name);
6347 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
6351 class2 = classify_vr4120_insn (insn2->insn_mo->name);
6352 if (vr4120_conflicts[class1] & (1 << class2))
6357 if (!HAVE_CODE_COMPRESSION)
6359 /* Check for GPR or coprocessor load delays. All such delays
6360 are on the RT register. */
6361 /* Itbl support may require additional care here. */
6362 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY))
6363 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC)))
6365 if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))
6369 /* Check for generic coprocessor hazards.
6371 This case is not handled very well. There is no special
6372 knowledge of CP0 handling, and the coprocessors other than
6373 the floating point unit are not distinguished at all. */
6374 /* Itbl support may require additional care here. FIXME!
6375 Need to modify this to include knowledge about
6376 user specified delays! */
6377 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE))
6378 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
6380 /* Handle cases where INSN1 writes to a known general coprocessor
6381 register. There must be a one instruction delay before INSN2
6382 if INSN2 reads that register, otherwise no delay is needed. */
6383 mask = fpr_write_mask (insn1);
6386 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
6391 /* Read-after-write dependencies on the control registers
6392 require a two-instruction gap. */
6393 if ((pinfo1 & INSN_WRITE_COND_CODE)
6394 && (pinfo2 & INSN_READ_COND_CODE))
6397 /* We don't know exactly what INSN1 does. If INSN2 is
6398 also a coprocessor instruction, assume there must be
6399 a one instruction gap. */
6400 if (pinfo2 & INSN_COP)
6405 /* Check for read-after-write dependencies on the coprocessor
6406 control registers in cases where INSN1 does not need a general
6407 coprocessor delay. This means that INSN1 is a floating point
6408 comparison instruction. */
6409 /* Itbl support may require additional care here. */
6410 else if (!cop_interlocks
6411 && (pinfo1 & INSN_WRITE_COND_CODE)
6412 && (pinfo2 & INSN_READ_COND_CODE))
6416 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6417 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6419 if ((insn1->insn_mo->pinfo2 & INSN2_FORBIDDEN_SLOT)
6420 && ((pinfo2 & INSN_NO_DELAY_SLOT)
6421 || (insn2 && delayed_branch_p (insn2))))
6427 /* Return the number of nops that would be needed to work around the
6428 VR4130 mflo/mfhi errata if instruction INSN immediately followed
6429 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6430 that are contained within the first IGNORE instructions of HIST. */
6433 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
6434 const struct mips_cl_insn *insn)
6439 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6440 are not affected by the errata. */
6442 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
6443 || strcmp (insn->insn_mo->name, "mtlo") == 0
6444 || strcmp (insn->insn_mo->name, "mthi") == 0))
6447 /* Search for the first MFLO or MFHI. */
6448 for (i = 0; i < MAX_VR4130_NOPS; i++)
6449 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
6451 /* Extract the destination register. */
6452 mask = gpr_write_mask (&hist[i]);
6454 /* No nops are needed if INSN reads that register. */
6455 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
6458 /* ...or if any of the intervening instructions do. */
6459 for (j = 0; j < i; j++)
6460 if (gpr_read_mask (&hist[j]) & mask)
6464 return MAX_VR4130_NOPS - i;
6469 #define BASE_REG_EQ(INSN1, INSN2) \
6470 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
6471 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6473 /* Return the minimum alignment for this store instruction. */
6476 fix_24k_align_to (const struct mips_opcode *mo)
6478 if (strcmp (mo->name, "sh") == 0)
6481 if (strcmp (mo->name, "swc1") == 0
6482 || strcmp (mo->name, "swc2") == 0
6483 || strcmp (mo->name, "sw") == 0
6484 || strcmp (mo->name, "sc") == 0
6485 || strcmp (mo->name, "s.s") == 0)
6488 if (strcmp (mo->name, "sdc1") == 0
6489 || strcmp (mo->name, "sdc2") == 0
6490 || strcmp (mo->name, "s.d") == 0)
6497 struct fix_24k_store_info
6499 /* Immediate offset, if any, for this store instruction. */
6501 /* Alignment required by this store instruction. */
6503 /* True for register offsets. */
6504 int register_offset;
6507 /* Comparison function used by qsort. */
6510 fix_24k_sort (const void *a, const void *b)
6512 const struct fix_24k_store_info *pos1 = a;
6513 const struct fix_24k_store_info *pos2 = b;
6515 return (pos1->off - pos2->off);
6518 /* INSN is a store instruction. Try to record the store information
6519 in STINFO. Return false if the information isn't known. */
6522 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
6523 const struct mips_cl_insn *insn)
6525 /* The instruction must have a known offset. */
6526 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
6529 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
6530 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
6534 /* Return the number of nops that would be needed to work around the 24k
6535 "lost data on stores during refill" errata if instruction INSN
6536 immediately followed the 2 instructions described by HIST.
6537 Ignore hazards that are contained within the first IGNORE
6538 instructions of HIST.
6540 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6541 for the data cache refills and store data. The following describes
6542 the scenario where the store data could be lost.
6544 * A data cache miss, due to either a load or a store, causing fill
6545 data to be supplied by the memory subsystem
6546 * The first three doublewords of fill data are returned and written
6548 * A sequence of four stores occurs in consecutive cycles around the
6549 final doubleword of the fill:
6553 * Zero, One or more instructions
6556 The four stores A-D must be to different doublewords of the line that
6557 is being filled. The fourth instruction in the sequence above permits
6558 the fill of the final doubleword to be transferred from the FSB into
6559 the cache. In the sequence above, the stores may be either integer
6560 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6561 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6562 different doublewords on the line. If the floating point unit is
6563 running in 1:2 mode, it is not possible to create the sequence above
6564 using only floating point store instructions.
6566 In this case, the cache line being filled is incorrectly marked
6567 invalid, thereby losing the data from any store to the line that
6568 occurs between the original miss and the completion of the five
6569 cycle sequence shown above.
6571 The workarounds are:
6573 * Run the data cache in write-through mode.
6574 * Insert a non-store instruction between
6575 Store A and Store B or Store B and Store C. */
6578 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
6579 const struct mips_cl_insn *insn)
6581 struct fix_24k_store_info pos[3];
6582 int align, i, base_offset;
6587 /* If the previous instruction wasn't a store, there's nothing to
6589 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
6592 /* If the instructions after the previous one are unknown, we have
6593 to assume the worst. */
6597 /* Check whether we are dealing with three consecutive stores. */
6598 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
6599 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
6602 /* If we don't know the relationship between the store addresses,
6603 assume the worst. */
6604 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
6605 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
6608 if (!fix_24k_record_store_info (&pos[0], insn)
6609 || !fix_24k_record_store_info (&pos[1], &hist[0])
6610 || !fix_24k_record_store_info (&pos[2], &hist[1]))
6613 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
6615 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6616 X bytes and such that the base register + X is known to be aligned
6619 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
6623 align = pos[0].align_to;
6624 base_offset = pos[0].off;
6625 for (i = 1; i < 3; i++)
6626 if (align < pos[i].align_to)
6628 align = pos[i].align_to;
6629 base_offset = pos[i].off;
6631 for (i = 0; i < 3; i++)
6632 pos[i].off -= base_offset;
6635 pos[0].off &= ~align + 1;
6636 pos[1].off &= ~align + 1;
6637 pos[2].off &= ~align + 1;
6639 /* If any two stores write to the same chunk, they also write to the
6640 same doubleword. The offsets are still sorted at this point. */
6641 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
6644 /* A range of at least 9 bytes is needed for the stores to be in
6645 non-overlapping doublewords. */
6646 if (pos[2].off - pos[0].off <= 8)
6649 if (pos[2].off - pos[1].off >= 24
6650 || pos[1].off - pos[0].off >= 24
6651 || pos[2].off - pos[0].off >= 32)
6657 /* Return the number of nops that would be needed if instruction INSN
6658 immediately followed the MAX_NOPS instructions given by HIST,
6659 where HIST[0] is the most recent instruction. Ignore hazards
6660 between INSN and the first IGNORE instructions in HIST.
6662 If INSN is null, return the worse-case number of nops for any
6666 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
6667 const struct mips_cl_insn *insn)
6669 int i, nops, tmp_nops;
6672 for (i = ignore; i < MAX_DELAY_NOPS; i++)
6674 tmp_nops = insns_between (hist + i, insn) - i;
6675 if (tmp_nops > nops)
6679 if (mips_fix_vr4130 && !mips_opts.micromips)
6681 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
6682 if (tmp_nops > nops)
6686 if (mips_fix_24k && !mips_opts.micromips)
6688 tmp_nops = nops_for_24k (ignore, hist, insn);
6689 if (tmp_nops > nops)
6696 /* The variable arguments provide NUM_INSNS extra instructions that
6697 might be added to HIST. Return the largest number of nops that
6698 would be needed after the extended sequence, ignoring hazards
6699 in the first IGNORE instructions. */
6702 nops_for_sequence (int num_insns, int ignore,
6703 const struct mips_cl_insn *hist, ...)
6706 struct mips_cl_insn buffer[MAX_NOPS];
6707 struct mips_cl_insn *cursor;
6710 va_start (args, hist);
6711 cursor = buffer + num_insns;
6712 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
6713 while (cursor > buffer)
6714 *--cursor = *va_arg (args, const struct mips_cl_insn *);
6716 nops = nops_for_insn (ignore, buffer, NULL);
6721 /* Like nops_for_insn, but if INSN is a branch, take into account the
6722 worst-case delay for the branch target. */
6725 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
6726 const struct mips_cl_insn *insn)
6730 nops = nops_for_insn (ignore, hist, insn);
6731 if (delayed_branch_p (insn))
6733 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
6734 hist, insn, get_delay_slot_nop (insn));
6735 if (tmp_nops > nops)
6738 else if (compact_branch_p (insn))
6740 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
6741 if (tmp_nops > nops)
6747 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6750 fix_loongson2f_nop (struct mips_cl_insn * ip)
6752 gas_assert (!HAVE_CODE_COMPRESSION);
6753 if (strcmp (ip->insn_mo->name, "nop") == 0)
6754 ip->insn_opcode = LOONGSON2F_NOP_INSN;
6757 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6758 jr target pc &= 'hffff_ffff_cfff_ffff. */
6761 fix_loongson2f_jump (struct mips_cl_insn * ip)
6763 gas_assert (!HAVE_CODE_COMPRESSION);
6764 if (strcmp (ip->insn_mo->name, "j") == 0
6765 || strcmp (ip->insn_mo->name, "jr") == 0
6766 || strcmp (ip->insn_mo->name, "jalr") == 0)
6774 sreg = EXTRACT_OPERAND (0, RS, *ip);
6775 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
6778 ep.X_op = O_constant;
6779 ep.X_add_number = 0xcfff0000;
6780 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
6781 ep.X_add_number = 0xffff;
6782 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
6783 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
6788 fix_loongson2f (struct mips_cl_insn * ip)
6790 if (mips_fix_loongson2f_nop)
6791 fix_loongson2f_nop (ip);
6793 if (mips_fix_loongson2f_jump)
6794 fix_loongson2f_jump (ip);
6797 /* IP is a branch that has a delay slot, and we need to fill it
6798 automatically. Return true if we can do that by swapping IP
6799 with the previous instruction.
6800 ADDRESS_EXPR is an operand of the instruction to be used with
6804 can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
6805 bfd_reloc_code_real_type *reloc_type)
6807 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
6808 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
6809 unsigned int fpr_read, prev_fpr_write;
6811 /* -O2 and above is required for this optimization. */
6812 if (mips_optimize < 2)
6815 /* If we have seen .set volatile or .set nomove, don't optimize. */
6816 if (mips_opts.nomove)
6819 /* We can't swap if the previous instruction's position is fixed. */
6820 if (history[0].fixed_p)
6823 /* If the previous previous insn was in a .set noreorder, we can't
6824 swap. Actually, the MIPS assembler will swap in this situation.
6825 However, gcc configured -with-gnu-as will generate code like
6833 in which we can not swap the bne and INSN. If gcc is not configured
6834 -with-gnu-as, it does not output the .set pseudo-ops. */
6835 if (history[1].noreorder_p)
6838 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6839 This means that the previous instruction was a 4-byte one anyhow. */
6840 if (mips_opts.mips16 && history[0].fixp[0])
6843 /* If the branch is itself the target of a branch, we can not swap.
6844 We cheat on this; all we check for is whether there is a label on
6845 this instruction. If there are any branches to anything other than
6846 a label, users must use .set noreorder. */
6847 if (seg_info (now_seg)->label_list)
6850 /* If the previous instruction is in a variant frag other than this
6851 branch's one, we cannot do the swap. This does not apply to
6852 MIPS16 code, which uses variant frags for different purposes. */
6853 if (!mips_opts.mips16
6855 && history[0].frag->fr_type == rs_machine_dependent)
6858 /* We do not swap with instructions that cannot architecturally
6859 be placed in a branch delay slot, such as SYNC or ERET. We
6860 also refrain from swapping with a trap instruction, since it
6861 complicates trap handlers to have the trap instruction be in
6863 prev_pinfo = history[0].insn_mo->pinfo;
6864 if (prev_pinfo & INSN_NO_DELAY_SLOT)
6867 /* Check for conflicts between the branch and the instructions
6868 before the candidate delay slot. */
6869 if (nops_for_insn (0, history + 1, ip) > 0)
6872 /* Check for conflicts between the swapped sequence and the
6873 target of the branch. */
6874 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
6877 /* If the branch reads a register that the previous
6878 instruction sets, we can not swap. */
6879 gpr_read = gpr_read_mask (ip);
6880 prev_gpr_write = gpr_write_mask (&history[0]);
6881 if (gpr_read & prev_gpr_write)
6884 fpr_read = fpr_read_mask (ip);
6885 prev_fpr_write = fpr_write_mask (&history[0]);
6886 if (fpr_read & prev_fpr_write)
6889 /* If the branch writes a register that the previous
6890 instruction sets, we can not swap. */
6891 gpr_write = gpr_write_mask (ip);
6892 if (gpr_write & prev_gpr_write)
6895 /* If the branch writes a register that the previous
6896 instruction reads, we can not swap. */
6897 prev_gpr_read = gpr_read_mask (&history[0]);
6898 if (gpr_write & prev_gpr_read)
6901 /* If one instruction sets a condition code and the
6902 other one uses a condition code, we can not swap. */
6903 pinfo = ip->insn_mo->pinfo;
6904 if ((pinfo & INSN_READ_COND_CODE)
6905 && (prev_pinfo & INSN_WRITE_COND_CODE))
6907 if ((pinfo & INSN_WRITE_COND_CODE)
6908 && (prev_pinfo & INSN_READ_COND_CODE))
6911 /* If the previous instruction uses the PC, we can not swap. */
6912 prev_pinfo2 = history[0].insn_mo->pinfo2;
6913 if (prev_pinfo2 & INSN2_READ_PC)
6916 /* If the previous instruction has an incorrect size for a fixed
6917 branch delay slot in microMIPS mode, we cannot swap. */
6918 pinfo2 = ip->insn_mo->pinfo2;
6919 if (mips_opts.micromips
6920 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
6921 && insn_length (history) != 2)
6923 if (mips_opts.micromips
6924 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
6925 && insn_length (history) != 4)
6928 /* On R5900 short loops need to be fixed by inserting a nop in
6929 the branch delay slots.
6930 A short loop can be terminated too early. */
6931 if (mips_opts.arch == CPU_R5900
6932 /* Check if instruction has a parameter, ignore "j $31". */
6933 && (address_expr != NULL)
6934 /* Parameter must be 16 bit. */
6935 && (*reloc_type == BFD_RELOC_16_PCREL_S2)
6936 /* Branch to same segment. */
6937 && (S_GET_SEGMENT (address_expr->X_add_symbol) == now_seg)
6938 /* Branch to same code fragment. */
6939 && (symbol_get_frag (address_expr->X_add_symbol) == frag_now)
6940 /* Can only calculate branch offset if value is known. */
6941 && symbol_constant_p (address_expr->X_add_symbol)
6942 /* Check if branch is really conditional. */
6943 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */
6944 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */
6945 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
6948 /* Check if loop is shorter than 6 instructions including
6949 branch and delay slot. */
6950 distance = frag_now_fix () - S_GET_VALUE (address_expr->X_add_symbol);
6957 /* When the loop includes branches or jumps,
6958 it is not a short loop. */
6959 for (i = 0; i < (distance / 4); i++)
6961 if ((history[i].cleared_p)
6962 || delayed_branch_p (&history[i]))
6970 /* Insert nop after branch to fix short loop. */
6979 /* Decide how we should add IP to the instruction stream.
6980 ADDRESS_EXPR is an operand of the instruction to be used with
6983 static enum append_method
6984 get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
6985 bfd_reloc_code_real_type *reloc_type)
6987 /* The relaxed version of a macro sequence must be inherently
6989 if (mips_relax.sequence == 2)
6992 /* We must not dabble with instructions in a ".set noreorder" block. */
6993 if (mips_opts.noreorder)
6996 /* Otherwise, it's our responsibility to fill branch delay slots. */
6997 if (delayed_branch_p (ip))
6999 if (!branch_likely_p (ip)
7000 && can_swap_branch_p (ip, address_expr, reloc_type))
7003 if (mips_opts.mips16
7004 && ISA_SUPPORTS_MIPS16E
7005 && gpr_read_mask (ip) != 0)
7006 return APPEND_ADD_COMPACT;
7008 if (mips_opts.micromips
7009 && ((ip->insn_opcode & 0xffe0) == 0x4580
7010 || (!forced_insn_length
7011 && ((ip->insn_opcode & 0xfc00) == 0xcc00
7012 || (ip->insn_opcode & 0xdc00) == 0x8c00))
7013 || (ip->insn_opcode & 0xdfe00000) == 0x94000000
7014 || (ip->insn_opcode & 0xdc1f0000) == 0x94000000))
7015 return APPEND_ADD_COMPACT;
7017 return APPEND_ADD_WITH_NOP;
7023 /* IP is an instruction whose opcode we have just changed, END points
7024 to the end of the opcode table processed. Point IP->insn_mo to the
7025 new opcode's definition. */
7028 find_altered_opcode (struct mips_cl_insn *ip, const struct mips_opcode *end)
7030 const struct mips_opcode *mo;
7032 for (mo = ip->insn_mo; mo < end; mo++)
7033 if (mo->pinfo != INSN_MACRO
7034 && (ip->insn_opcode & mo->mask) == mo->match)
7042 /* IP is a MIPS16 instruction whose opcode we have just changed.
7043 Point IP->insn_mo to the new opcode's definition. */
7046 find_altered_mips16_opcode (struct mips_cl_insn *ip)
7048 find_altered_opcode (ip, &mips16_opcodes[bfd_mips16_num_opcodes]);
7051 /* IP is a microMIPS instruction whose opcode we have just changed.
7052 Point IP->insn_mo to the new opcode's definition. */
7055 find_altered_micromips_opcode (struct mips_cl_insn *ip)
7057 find_altered_opcode (ip, µmips_opcodes[bfd_micromips_num_opcodes]);
7060 /* For microMIPS macros, we need to generate a local number label
7061 as the target of branches. */
7062 #define MICROMIPS_LABEL_CHAR '\037'
7063 static unsigned long micromips_target_label;
7064 static char micromips_target_name[32];
7067 micromips_label_name (void)
7069 char *p = micromips_target_name;
7070 char symbol_name_temporary[24];
7078 l = micromips_target_label;
7079 #ifdef LOCAL_LABEL_PREFIX
7080 *p++ = LOCAL_LABEL_PREFIX;
7083 *p++ = MICROMIPS_LABEL_CHAR;
7086 symbol_name_temporary[i++] = l % 10 + '0';
7091 *p++ = symbol_name_temporary[--i];
7094 return micromips_target_name;
7098 micromips_label_expr (expressionS *label_expr)
7100 label_expr->X_op = O_symbol;
7101 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
7102 label_expr->X_add_number = 0;
7106 micromips_label_inc (void)
7108 micromips_target_label++;
7109 *micromips_target_name = '\0';
7113 micromips_add_label (void)
7117 s = colon (micromips_label_name ());
7118 micromips_label_inc ();
7119 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
7122 /* If assembling microMIPS code, then return the microMIPS reloc
7123 corresponding to the requested one if any. Otherwise return
7124 the reloc unchanged. */
7126 static bfd_reloc_code_real_type
7127 micromips_map_reloc (bfd_reloc_code_real_type reloc)
7129 static const bfd_reloc_code_real_type relocs[][2] =
7131 /* Keep sorted incrementally by the left-hand key. */
7132 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
7133 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
7134 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
7135 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
7136 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
7137 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
7138 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
7139 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
7140 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
7141 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
7142 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
7143 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
7144 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
7145 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
7146 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
7147 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
7148 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
7149 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
7150 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
7151 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
7152 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
7153 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
7154 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
7155 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
7156 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
7157 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
7158 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
7160 bfd_reloc_code_real_type r;
7163 if (!mips_opts.micromips)
7165 for (i = 0; i < ARRAY_SIZE (relocs); i++)
7171 return relocs[i][1];
7176 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
7177 Return true on success, storing the resolved value in RESULT. */
7180 calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
7185 case BFD_RELOC_MIPS_HIGHEST:
7186 case BFD_RELOC_MICROMIPS_HIGHEST:
7187 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff;
7190 case BFD_RELOC_MIPS_HIGHER:
7191 case BFD_RELOC_MICROMIPS_HIGHER:
7192 *result = ((operand + 0x80008000ull) >> 32) & 0xffff;
7195 case BFD_RELOC_HI16_S:
7196 case BFD_RELOC_HI16_S_PCREL:
7197 case BFD_RELOC_MICROMIPS_HI16_S:
7198 case BFD_RELOC_MIPS16_HI16_S:
7199 *result = ((operand + 0x8000) >> 16) & 0xffff;
7202 case BFD_RELOC_HI16:
7203 case BFD_RELOC_MICROMIPS_HI16:
7204 case BFD_RELOC_MIPS16_HI16:
7205 *result = (operand >> 16) & 0xffff;
7208 case BFD_RELOC_LO16:
7209 case BFD_RELOC_LO16_PCREL:
7210 case BFD_RELOC_MICROMIPS_LO16:
7211 case BFD_RELOC_MIPS16_LO16:
7212 *result = operand & 0xffff;
7215 case BFD_RELOC_UNUSED:
7224 /* Output an instruction. IP is the instruction information.
7225 ADDRESS_EXPR is an operand of the instruction to be used with
7226 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
7227 a macro expansion. */
7230 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
7231 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
7233 unsigned long prev_pinfo2, pinfo;
7234 bfd_boolean relaxed_branch = FALSE;
7235 enum append_method method;
7236 bfd_boolean relax32;
7239 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
7240 fix_loongson2f (ip);
7242 file_ase_mips16 |= mips_opts.mips16;
7243 file_ase_micromips |= mips_opts.micromips;
7245 prev_pinfo2 = history[0].insn_mo->pinfo2;
7246 pinfo = ip->insn_mo->pinfo;
7248 /* Don't raise alarm about `nods' frags as they'll fill in the right
7249 kind of nop in relaxation if required. */
7250 if (mips_opts.micromips
7252 && !(history[0].frag
7253 && history[0].frag->fr_type == rs_machine_dependent
7254 && RELAX_MICROMIPS_P (history[0].frag->fr_subtype)
7255 && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype))
7256 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
7257 && micromips_insn_length (ip->insn_mo) != 2)
7258 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
7259 && micromips_insn_length (ip->insn_mo) != 4)))
7260 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
7261 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
7263 if (address_expr == NULL)
7265 else if (reloc_type[0] <= BFD_RELOC_UNUSED
7266 && reloc_type[1] == BFD_RELOC_UNUSED
7267 && reloc_type[2] == BFD_RELOC_UNUSED
7268 && address_expr->X_op == O_constant)
7270 switch (*reloc_type)
7272 case BFD_RELOC_MIPS_JMP:
7276 /* Shift is 2, unusually, for microMIPS JALX. */
7277 shift = (mips_opts.micromips
7278 && strcmp (ip->insn_mo->name, "jalx") != 0) ? 1 : 2;
7279 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7280 as_bad (_("jump to misaligned address (0x%lx)"),
7281 (unsigned long) address_expr->X_add_number);
7282 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7288 case BFD_RELOC_MIPS16_JMP:
7289 if ((address_expr->X_add_number & 3) != 0)
7290 as_bad (_("jump to misaligned address (0x%lx)"),
7291 (unsigned long) address_expr->X_add_number);
7293 (((address_expr->X_add_number & 0x7c0000) << 3)
7294 | ((address_expr->X_add_number & 0xf800000) >> 7)
7295 | ((address_expr->X_add_number & 0x3fffc) >> 2));
7299 case BFD_RELOC_16_PCREL_S2:
7303 shift = mips_opts.micromips ? 1 : 2;
7304 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7305 as_bad (_("branch to misaligned address (0x%lx)"),
7306 (unsigned long) address_expr->X_add_number);
7307 if (!mips_relax_branch)
7309 if ((address_expr->X_add_number + (1 << (shift + 15)))
7310 & ~((1 << (shift + 16)) - 1))
7311 as_bad (_("branch address range overflow (0x%lx)"),
7312 (unsigned long) address_expr->X_add_number);
7313 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7319 case BFD_RELOC_MIPS_21_PCREL_S2:
7324 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7325 as_bad (_("branch to misaligned address (0x%lx)"),
7326 (unsigned long) address_expr->X_add_number);
7327 if ((address_expr->X_add_number + (1 << (shift + 20)))
7328 & ~((1 << (shift + 21)) - 1))
7329 as_bad (_("branch address range overflow (0x%lx)"),
7330 (unsigned long) address_expr->X_add_number);
7331 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7336 case BFD_RELOC_MIPS_26_PCREL_S2:
7341 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7342 as_bad (_("branch to misaligned address (0x%lx)"),
7343 (unsigned long) address_expr->X_add_number);
7344 if ((address_expr->X_add_number + (1 << (shift + 25)))
7345 & ~((1 << (shift + 26)) - 1))
7346 as_bad (_("branch address range overflow (0x%lx)"),
7347 (unsigned long) address_expr->X_add_number);
7348 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7357 if (calculate_reloc (*reloc_type, address_expr->X_add_number,
7360 ip->insn_opcode |= value & 0xffff;
7368 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
7370 /* There are a lot of optimizations we could do that we don't.
7371 In particular, we do not, in general, reorder instructions.
7372 If you use gcc with optimization, it will reorder
7373 instructions and generally do much more optimization then we
7374 do here; repeating all that work in the assembler would only
7375 benefit hand written assembly code, and does not seem worth
7377 int nops = (mips_optimize == 0
7378 ? nops_for_insn (0, history, NULL)
7379 : nops_for_insn_or_target (0, history, ip));
7383 unsigned long old_frag_offset;
7386 old_frag = frag_now;
7387 old_frag_offset = frag_now_fix ();
7389 for (i = 0; i < nops; i++)
7390 add_fixed_insn (NOP_INSN);
7391 insert_into_history (0, nops, NOP_INSN);
7395 listing_prev_line ();
7396 /* We may be at the start of a variant frag. In case we
7397 are, make sure there is enough space for the frag
7398 after the frags created by listing_prev_line. The
7399 argument to frag_grow here must be at least as large
7400 as the argument to all other calls to frag_grow in
7401 this file. We don't have to worry about being in the
7402 middle of a variant frag, because the variants insert
7403 all needed nop instructions themselves. */
7407 mips_move_text_labels ();
7409 #ifndef NO_ECOFF_DEBUGGING
7410 if (ECOFF_DEBUGGING)
7411 ecoff_fix_loc (old_frag, old_frag_offset);
7415 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
7419 /* Work out how many nops in prev_nop_frag are needed by IP,
7420 ignoring hazards generated by the first prev_nop_frag_since
7422 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
7423 gas_assert (nops <= prev_nop_frag_holds);
7425 /* Enforce NOPS as a minimum. */
7426 if (nops > prev_nop_frag_required)
7427 prev_nop_frag_required = nops;
7429 if (prev_nop_frag_holds == prev_nop_frag_required)
7431 /* Settle for the current number of nops. Update the history
7432 accordingly (for the benefit of any future .set reorder code). */
7433 prev_nop_frag = NULL;
7434 insert_into_history (prev_nop_frag_since,
7435 prev_nop_frag_holds, NOP_INSN);
7439 /* Allow this instruction to replace one of the nops that was
7440 tentatively added to prev_nop_frag. */
7441 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
7442 prev_nop_frag_holds--;
7443 prev_nop_frag_since++;
7447 method = get_append_method (ip, address_expr, reloc_type);
7448 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
7450 dwarf2_emit_insn (0);
7451 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7452 so "move" the instruction address accordingly.
7454 Also, it doesn't seem appropriate for the assembler to reorder .loc
7455 entries. If this instruction is a branch that we are going to swap
7456 with the previous instruction, the two instructions should be
7457 treated as a unit, and the debug information for both instructions
7458 should refer to the start of the branch sequence. Using the
7459 current position is certainly wrong when swapping a 32-bit branch
7460 and a 16-bit delay slot, since the current position would then be
7461 in the middle of a branch. */
7462 dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp);
7464 relax32 = (mips_relax_branch
7465 /* Don't try branch relaxation within .set nomacro, or within
7466 .set noat if we use $at for PIC computations. If it turns
7467 out that the branch was out-of-range, we'll get an error. */
7468 && !mips_opts.warn_about_macros
7469 && (mips_opts.at || mips_pic == NO_PIC)
7470 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7471 as they have no complementing branches. */
7472 && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP)));
7474 if (!HAVE_CODE_COMPRESSION
7477 && *reloc_type == BFD_RELOC_16_PCREL_S2
7478 && delayed_branch_p (ip))
7480 relaxed_branch = TRUE;
7481 add_relaxed_insn (ip, (relaxed_branch_length
7483 uncond_branch_p (ip) ? -1
7484 : branch_likely_p (ip) ? 1
7487 (AT, mips_pic != NO_PIC,
7488 uncond_branch_p (ip),
7489 branch_likely_p (ip),
7490 pinfo & INSN_WRITE_GPR_31,
7492 address_expr->X_add_symbol,
7493 address_expr->X_add_number);
7494 *reloc_type = BFD_RELOC_UNUSED;
7496 else if (mips_opts.micromips
7498 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
7499 || *reloc_type > BFD_RELOC_UNUSED)
7500 && (delayed_branch_p (ip) || compact_branch_p (ip))
7501 /* Don't try branch relaxation when users specify
7502 16-bit/32-bit instructions. */
7503 && !forced_insn_length)
7505 bfd_boolean relax16 = (method != APPEND_ADD_COMPACT
7506 && *reloc_type > BFD_RELOC_UNUSED);
7507 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
7508 int uncond = uncond_branch_p (ip) ? -1 : 0;
7509 int compact = compact_branch_p (ip) || method == APPEND_ADD_COMPACT;
7510 int nods = method == APPEND_ADD_WITH_NOP;
7511 int al = pinfo & INSN_WRITE_GPR_31;
7512 int length32 = nods ? 8 : 4;
7514 gas_assert (address_expr != NULL);
7515 gas_assert (!mips_relax.sequence);
7517 relaxed_branch = TRUE;
7519 method = APPEND_ADD;
7521 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
7522 add_relaxed_insn (ip, length32, relax16 ? 2 : 4,
7523 RELAX_MICROMIPS_ENCODE (type, AT, mips_opts.insn32,
7525 uncond, compact, al, nods,
7527 address_expr->X_add_symbol,
7528 address_expr->X_add_number);
7529 *reloc_type = BFD_RELOC_UNUSED;
7531 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
7533 bfd_boolean require_unextended;
7534 bfd_boolean require_extended;
7538 if (forced_insn_length != 0)
7540 require_unextended = forced_insn_length == 2;
7541 require_extended = forced_insn_length == 4;
7545 require_unextended = (mips_opts.noautoextend
7546 && !mips_opcode_32bit_p (ip->insn_mo));
7547 require_extended = 0;
7550 /* We need to set up a variant frag. */
7551 gas_assert (address_expr != NULL);
7552 /* Pass any `O_symbol' expression unchanged as an `expr_section'
7553 symbol created by `make_expr_symbol' may not get a necessary
7554 external relocation produced. */
7555 if (address_expr->X_op == O_symbol)
7557 symbol = address_expr->X_add_symbol;
7558 offset = address_expr->X_add_number;
7562 symbol = make_expr_symbol (address_expr);
7563 symbol_append (symbol, symbol_lastP, &symbol_rootP, &symbol_lastP);
7566 add_relaxed_insn (ip, 12, 0,
7568 (*reloc_type - BFD_RELOC_UNUSED,
7569 mips_opts.ase & ASE_MIPS16E2,
7572 mips_opts.warn_about_macros,
7573 require_unextended, require_extended,
7574 delayed_branch_p (&history[0]),
7575 history[0].mips16_absolute_jump_p),
7578 else if (mips_opts.mips16 && insn_length (ip) == 2)
7580 if (!delayed_branch_p (ip))
7581 /* Make sure there is enough room to swap this instruction with
7582 a following jump instruction. */
7584 add_fixed_insn (ip);
7588 if (mips_opts.mips16
7589 && mips_opts.noreorder
7590 && delayed_branch_p (&history[0]))
7591 as_warn (_("extended instruction in delay slot"));
7593 if (mips_relax.sequence)
7595 /* If we've reached the end of this frag, turn it into a variant
7596 frag and record the information for the instructions we've
7598 if (frag_room () < 4)
7599 relax_close_frag ();
7600 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
7603 if (mips_relax.sequence != 2)
7605 if (mips_macro_warning.first_insn_sizes[0] == 0)
7606 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
7607 mips_macro_warning.sizes[0] += insn_length (ip);
7608 mips_macro_warning.insns[0]++;
7610 if (mips_relax.sequence != 1)
7612 if (mips_macro_warning.first_insn_sizes[1] == 0)
7613 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
7614 mips_macro_warning.sizes[1] += insn_length (ip);
7615 mips_macro_warning.insns[1]++;
7618 if (mips_opts.mips16)
7621 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
7623 add_fixed_insn (ip);
7626 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
7628 bfd_reloc_code_real_type final_type[3];
7629 reloc_howto_type *howto0;
7630 reloc_howto_type *howto;
7633 /* Perform any necessary conversion to microMIPS relocations
7634 and find out how many relocations there actually are. */
7635 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
7636 final_type[i] = micromips_map_reloc (reloc_type[i]);
7638 /* In a compound relocation, it is the final (outermost)
7639 operator that determines the relocated field. */
7640 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
7645 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
7646 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
7647 bfd_get_reloc_size (howto),
7649 howto0 && howto0->pc_relative,
7651 /* Record non-PIC mode in `fx_tcbit2' for `md_apply_fix'. */
7652 ip->fixp[0]->fx_tcbit2 = mips_pic == NO_PIC;
7654 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
7655 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
7656 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
7658 /* These relocations can have an addend that won't fit in
7659 4 octets for 64bit assembly. */
7661 && ! howto->partial_inplace
7662 && (reloc_type[0] == BFD_RELOC_16
7663 || reloc_type[0] == BFD_RELOC_32
7664 || reloc_type[0] == BFD_RELOC_MIPS_JMP
7665 || reloc_type[0] == BFD_RELOC_GPREL16
7666 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
7667 || reloc_type[0] == BFD_RELOC_GPREL32
7668 || reloc_type[0] == BFD_RELOC_64
7669 || reloc_type[0] == BFD_RELOC_CTOR
7670 || reloc_type[0] == BFD_RELOC_MIPS_SUB
7671 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
7672 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
7673 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
7674 || reloc_type[0] == BFD_RELOC_MIPS_REL16
7675 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
7676 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
7677 || hi16_reloc_p (reloc_type[0])
7678 || lo16_reloc_p (reloc_type[0])))
7679 ip->fixp[0]->fx_no_overflow = 1;
7681 /* These relocations can have an addend that won't fit in 2 octets. */
7682 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
7683 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1)
7684 ip->fixp[0]->fx_no_overflow = 1;
7686 if (mips_relax.sequence)
7688 if (mips_relax.first_fixup == 0)
7689 mips_relax.first_fixup = ip->fixp[0];
7691 else if (reloc_needs_lo_p (*reloc_type))
7693 struct mips_hi_fixup *hi_fixup;
7695 /* Reuse the last entry if it already has a matching %lo. */
7696 hi_fixup = mips_hi_fixup_list;
7698 || !fixup_has_matching_lo_p (hi_fixup->fixp))
7700 hi_fixup = XNEW (struct mips_hi_fixup);
7701 hi_fixup->next = mips_hi_fixup_list;
7702 mips_hi_fixup_list = hi_fixup;
7704 hi_fixup->fixp = ip->fixp[0];
7705 hi_fixup->seg = now_seg;
7708 /* Add fixups for the second and third relocations, if given.
7709 Note that the ABI allows the second relocation to be
7710 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
7711 moment we only use RSS_UNDEF, but we could add support
7712 for the others if it ever becomes necessary. */
7713 for (i = 1; i < 3; i++)
7714 if (reloc_type[i] != BFD_RELOC_UNUSED)
7716 ip->fixp[i] = fix_new (ip->frag, ip->where,
7717 ip->fixp[0]->fx_size, NULL, 0,
7718 FALSE, final_type[i]);
7720 /* Use fx_tcbit to mark compound relocs. */
7721 ip->fixp[0]->fx_tcbit = 1;
7722 ip->fixp[i]->fx_tcbit = 1;
7726 /* Update the register mask information. */
7727 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
7728 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
7733 insert_into_history (0, 1, ip);
7736 case APPEND_ADD_WITH_NOP:
7738 struct mips_cl_insn *nop;
7740 insert_into_history (0, 1, ip);
7741 nop = get_delay_slot_nop (ip);
7742 add_fixed_insn (nop);
7743 insert_into_history (0, 1, nop);
7744 if (mips_relax.sequence)
7745 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
7749 case APPEND_ADD_COMPACT:
7750 /* Convert MIPS16 jr/jalr into a "compact" jump. */
7751 if (mips_opts.mips16)
7753 ip->insn_opcode |= 0x0080;
7754 find_altered_mips16_opcode (ip);
7756 /* Convert microMIPS instructions. */
7757 else if (mips_opts.micromips)
7760 if ((ip->insn_opcode & 0xffe0) == 0x4580)
7761 ip->insn_opcode |= 0x0020;
7763 else if ((ip->insn_opcode & 0xfc00) == 0xcc00)
7764 ip->insn_opcode = 0x40e00000;
7765 /* beqz16->beqzc, bnez16->bnezc */
7766 else if ((ip->insn_opcode & 0xdc00) == 0x8c00)
7768 unsigned long regno;
7770 regno = ip->insn_opcode >> MICROMIPSOP_SH_MD;
7771 regno &= MICROMIPSOP_MASK_MD;
7772 regno = micromips_to_32_reg_d_map[regno];
7773 ip->insn_opcode = (((ip->insn_opcode << 9) & 0x00400000)
7774 | (regno << MICROMIPSOP_SH_RS)
7775 | 0x40a00000) ^ 0x00400000;
7777 /* beqz->beqzc, bnez->bnezc */
7778 else if ((ip->insn_opcode & 0xdfe00000) == 0x94000000)
7779 ip->insn_opcode = ((ip->insn_opcode & 0x001f0000)
7780 | ((ip->insn_opcode >> 7) & 0x00400000)
7781 | 0x40a00000) ^ 0x00400000;
7782 /* beq $0->beqzc, bne $0->bnezc */
7783 else if ((ip->insn_opcode & 0xdc1f0000) == 0x94000000)
7784 ip->insn_opcode = (((ip->insn_opcode >>
7785 (MICROMIPSOP_SH_RT - MICROMIPSOP_SH_RS))
7786 & (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS))
7787 | ((ip->insn_opcode >> 7) & 0x00400000)
7788 | 0x40a00000) ^ 0x00400000;
7791 find_altered_micromips_opcode (ip);
7796 insert_into_history (0, 1, ip);
7801 struct mips_cl_insn delay = history[0];
7803 if (relaxed_branch || delay.frag != ip->frag)
7805 /* Add the delay slot instruction to the end of the
7806 current frag and shrink the fixed part of the
7807 original frag. If the branch occupies the tail of
7808 the latter, move it backwards to cover the gap. */
7809 delay.frag->fr_fix -= branch_disp;
7810 if (delay.frag == ip->frag)
7811 move_insn (ip, ip->frag, ip->where - branch_disp);
7812 add_fixed_insn (&delay);
7816 /* If this is not a relaxed branch and we are in the
7817 same frag, then just swap the instructions. */
7818 move_insn (ip, delay.frag, delay.where);
7819 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
7823 insert_into_history (0, 1, &delay);
7828 /* If we have just completed an unconditional branch, clear the history. */
7829 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
7830 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
7834 mips_no_prev_insn ();
7836 for (i = 0; i < ARRAY_SIZE (history); i++)
7837 history[i].cleared_p = 1;
7840 /* We need to emit a label at the end of branch-likely macros. */
7841 if (emit_branch_likely_macro)
7843 emit_branch_likely_macro = FALSE;
7844 micromips_add_label ();
7847 /* We just output an insn, so the next one doesn't have a label. */
7848 mips_clear_insn_labels ();
7851 /* Forget that there was any previous instruction or label.
7852 When BRANCH is true, the branch history is also flushed. */
7855 mips_no_prev_insn (void)
7857 prev_nop_frag = NULL;
7858 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
7859 mips_clear_insn_labels ();
7862 /* This function must be called before we emit something other than
7863 instructions. It is like mips_no_prev_insn except that it inserts
7864 any NOPS that might be needed by previous instructions. */
7867 mips_emit_delays (void)
7869 if (! mips_opts.noreorder)
7871 int nops = nops_for_insn (0, history, NULL);
7875 add_fixed_insn (NOP_INSN);
7876 mips_move_text_labels ();
7879 mips_no_prev_insn ();
7882 /* Start a (possibly nested) noreorder block. */
7885 start_noreorder (void)
7887 if (mips_opts.noreorder == 0)
7892 /* None of the instructions before the .set noreorder can be moved. */
7893 for (i = 0; i < ARRAY_SIZE (history); i++)
7894 history[i].fixed_p = 1;
7896 /* Insert any nops that might be needed between the .set noreorder
7897 block and the previous instructions. We will later remove any
7898 nops that turn out not to be needed. */
7899 nops = nops_for_insn (0, history, NULL);
7902 if (mips_optimize != 0)
7904 /* Record the frag which holds the nop instructions, so
7905 that we can remove them if we don't need them. */
7906 frag_grow (nops * NOP_INSN_SIZE);
7907 prev_nop_frag = frag_now;
7908 prev_nop_frag_holds = nops;
7909 prev_nop_frag_required = 0;
7910 prev_nop_frag_since = 0;
7913 for (; nops > 0; --nops)
7914 add_fixed_insn (NOP_INSN);
7916 /* Move on to a new frag, so that it is safe to simply
7917 decrease the size of prev_nop_frag. */
7918 frag_wane (frag_now);
7920 mips_move_text_labels ();
7922 mips_mark_labels ();
7923 mips_clear_insn_labels ();
7925 mips_opts.noreorder++;
7926 mips_any_noreorder = 1;
7929 /* End a nested noreorder block. */
7932 end_noreorder (void)
7934 mips_opts.noreorder--;
7935 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
7937 /* Commit to inserting prev_nop_frag_required nops and go back to
7938 handling nop insertion the .set reorder way. */
7939 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
7941 insert_into_history (prev_nop_frag_since,
7942 prev_nop_frag_required, NOP_INSN);
7943 prev_nop_frag = NULL;
7947 /* Sign-extend 32-bit mode constants that have bit 31 set and all
7948 higher bits unset. */
7951 normalize_constant_expr (expressionS *ex)
7953 if (ex->X_op == O_constant
7954 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7955 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7959 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
7960 all higher bits unset. */
7963 normalize_address_expr (expressionS *ex)
7965 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
7966 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
7967 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7968 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7972 /* Try to match TOKENS against OPCODE, storing the result in INSN.
7973 Return true if the match was successful.
7975 OPCODE_EXTRA is a value that should be ORed into the opcode
7976 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
7977 there are more alternatives after OPCODE and SOFT_MATCH is
7978 as for mips_arg_info. */
7981 match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
7982 struct mips_operand_token *tokens, unsigned int opcode_extra,
7983 bfd_boolean lax_match, bfd_boolean complete_p)
7986 struct mips_arg_info arg;
7987 const struct mips_operand *operand;
7990 imm_expr.X_op = O_absent;
7991 offset_expr.X_op = O_absent;
7992 offset_reloc[0] = BFD_RELOC_UNUSED;
7993 offset_reloc[1] = BFD_RELOC_UNUSED;
7994 offset_reloc[2] = BFD_RELOC_UNUSED;
7996 create_insn (insn, opcode);
7997 /* When no opcode suffix is specified, assume ".xyzw". */
7998 if ((opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0 && opcode_extra == 0)
7999 insn->insn_opcode |= 0xf << mips_vu0_channel_mask.lsb;
8001 insn->insn_opcode |= opcode_extra;
8002 memset (&arg, 0, sizeof (arg));
8006 arg.last_regno = ILLEGAL_REG;
8007 arg.dest_regno = ILLEGAL_REG;
8008 arg.lax_match = lax_match;
8009 for (args = opcode->args;; ++args)
8011 if (arg.token->type == OT_END)
8013 /* Handle unary instructions in which only one operand is given.
8014 The source is then the same as the destination. */
8015 if (arg.opnum == 1 && *args == ',')
8017 operand = (mips_opts.micromips
8018 ? decode_micromips_operand (args + 1)
8019 : decode_mips_operand (args + 1));
8020 if (operand && mips_optional_operand_p (operand))
8028 /* Treat elided base registers as $0. */
8029 if (strcmp (args, "(b)") == 0)
8037 /* The register suffix is optional. */
8042 /* Fail the match if there were too few operands. */
8046 /* Successful match. */
8049 clear_insn_error ();
8050 if (arg.dest_regno == arg.last_regno
8051 && strncmp (insn->insn_mo->name, "jalr", 4) == 0)
8055 (0, _("source and destination must be different"));
8056 else if (arg.last_regno == 31)
8058 (0, _("a destination register must be supplied"));
8060 else if (arg.last_regno == 31
8061 && (strncmp (insn->insn_mo->name, "bltzal", 6) == 0
8062 || strncmp (insn->insn_mo->name, "bgezal", 6) == 0))
8063 set_insn_error (0, _("the source register must not be $31"));
8064 check_completed_insn (&arg);
8068 /* Fail the match if the line has too many operands. */
8072 /* Handle characters that need to match exactly. */
8073 if (*args == '(' || *args == ')' || *args == ',')
8075 if (match_char (&arg, *args))
8082 if (arg.token->type == OT_DOUBLE_CHAR
8083 && arg.token->u.ch == *args)
8091 /* Handle special macro operands. Work out the properties of
8100 *offset_reloc = BFD_RELOC_MIPS_19_PCREL_S2;
8104 *offset_reloc = BFD_RELOC_MIPS_18_PCREL_S3;
8113 *offset_reloc = BFD_RELOC_MIPS_JMP;
8117 *offset_reloc = BFD_RELOC_MIPS_26_PCREL_S2;
8121 *offset_reloc = BFD_RELOC_MIPS_21_PCREL_S2;
8127 if (!match_const_int (&arg, &imm_expr.X_add_number))
8129 imm_expr.X_op = O_constant;
8131 normalize_constant_expr (&imm_expr);
8135 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
8137 /* Assume that the offset has been elided and that what
8138 we saw was a base register. The match will fail later
8139 if that assumption turns out to be wrong. */
8140 offset_expr.X_op = O_constant;
8141 offset_expr.X_add_number = 0;
8145 if (!match_expression (&arg, &offset_expr, offset_reloc))
8147 normalize_address_expr (&offset_expr);
8152 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
8158 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
8164 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
8170 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
8176 *offset_reloc = BFD_RELOC_16_PCREL_S2;
8180 *offset_reloc = BFD_RELOC_MIPS_JMP;
8184 gas_assert (mips_opts.micromips);
8190 if (!forced_insn_length)
8191 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
8193 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
8195 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
8201 operand = (mips_opts.micromips
8202 ? decode_micromips_operand (args)
8203 : decode_mips_operand (args));
8207 /* Skip prefixes. */
8208 if (*args == '+' || *args == 'm' || *args == '-')
8211 if (mips_optional_operand_p (operand)
8213 && (arg.token[0].type != OT_REG
8214 || arg.token[1].type == OT_END))
8216 /* Assume that the register has been elided and is the
8217 same as the first operand. */
8222 if (!match_operand (&arg, operand))
8227 /* Like match_insn, but for MIPS16. */
8230 match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
8231 struct mips_operand_token *tokens)
8234 const struct mips_operand *operand;
8235 const struct mips_operand *ext_operand;
8236 bfd_boolean pcrel = FALSE;
8237 int required_insn_length;
8238 struct mips_arg_info arg;
8241 if (forced_insn_length)
8242 required_insn_length = forced_insn_length;
8243 else if (mips_opts.noautoextend && !mips_opcode_32bit_p (opcode))
8244 required_insn_length = 2;
8246 required_insn_length = 0;
8248 create_insn (insn, opcode);
8249 imm_expr.X_op = O_absent;
8250 offset_expr.X_op = O_absent;
8251 offset_reloc[0] = BFD_RELOC_UNUSED;
8252 offset_reloc[1] = BFD_RELOC_UNUSED;
8253 offset_reloc[2] = BFD_RELOC_UNUSED;
8256 memset (&arg, 0, sizeof (arg));
8260 arg.last_regno = ILLEGAL_REG;
8261 arg.dest_regno = ILLEGAL_REG;
8263 for (args = opcode->args;; ++args)
8267 if (arg.token->type == OT_END)
8271 /* Handle unary instructions in which only one operand is given.
8272 The source is then the same as the destination. */
8273 if (arg.opnum == 1 && *args == ',')
8275 operand = decode_mips16_operand (args[1], FALSE);
8276 if (operand && mips_optional_operand_p (operand))
8284 /* Fail the match if there were too few operands. */
8288 /* Successful match. Stuff the immediate value in now, if
8290 clear_insn_error ();
8291 if (opcode->pinfo == INSN_MACRO)
8293 gas_assert (relax_char == 0 || relax_char == 'p');
8294 gas_assert (*offset_reloc == BFD_RELOC_UNUSED);
8297 && offset_expr.X_op == O_constant
8299 && calculate_reloc (*offset_reloc,
8300 offset_expr.X_add_number,
8303 mips16_immed (NULL, 0, relax_char, *offset_reloc, value,
8304 required_insn_length, &insn->insn_opcode);
8305 offset_expr.X_op = O_absent;
8306 *offset_reloc = BFD_RELOC_UNUSED;
8308 else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED)
8310 if (required_insn_length == 2)
8311 set_insn_error (0, _("invalid unextended operand value"));
8312 else if (!mips_opcode_32bit_p (opcode))
8314 forced_insn_length = 4;
8315 insn->insn_opcode |= MIPS16_EXTEND;
8318 else if (relax_char)
8319 *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char;
8321 check_completed_insn (&arg);
8325 /* Fail the match if the line has too many operands. */
8329 /* Handle characters that need to match exactly. */
8330 if (*args == '(' || *args == ')' || *args == ',')
8332 if (match_char (&arg, *args))
8352 if (!match_const_int (&arg, &imm_expr.X_add_number))
8354 imm_expr.X_op = O_constant;
8356 normalize_constant_expr (&imm_expr);
8361 *offset_reloc = BFD_RELOC_MIPS16_JMP;
8365 operand = decode_mips16_operand (c, mips_opcode_32bit_p (opcode));
8369 if (operand->type == OP_PCREL)
8373 ext_operand = decode_mips16_operand (c, TRUE);
8374 if (operand != ext_operand)
8376 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
8378 offset_expr.X_op = O_constant;
8379 offset_expr.X_add_number = 0;
8384 if (!match_expression (&arg, &offset_expr, offset_reloc))
8387 /* '8' is used for SLTI(U) and has traditionally not
8388 been allowed to take relocation operators. */
8389 if (offset_reloc[0] != BFD_RELOC_UNUSED
8390 && (ext_operand->size != 16 || c == '8'))
8392 match_not_constant (&arg);
8396 if (offset_expr.X_op == O_big)
8398 match_out_of_range (&arg);
8407 if (mips_optional_operand_p (operand)
8409 && (arg.token[0].type != OT_REG
8410 || arg.token[1].type == OT_END))
8412 /* Assume that the register has been elided and is the
8413 same as the first operand. */
8418 if (!match_operand (&arg, operand))
8423 /* Record that the current instruction is invalid for the current ISA. */
8426 match_invalid_for_isa (void)
8429 (0, _("opcode not supported on this processor: %s (%s)"),
8430 mips_cpu_info_from_arch (mips_opts.arch)->name,
8431 mips_cpu_info_from_isa (mips_opts.isa)->name);
8434 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8435 Return true if a definite match or failure was found, storing any match
8436 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8437 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8438 tried and failed to match under normal conditions and now want to try a
8439 more relaxed match. */
8442 match_insns (struct mips_cl_insn *insn, const struct mips_opcode *first,
8443 const struct mips_opcode *past, struct mips_operand_token *tokens,
8444 int opcode_extra, bfd_boolean lax_match)
8446 const struct mips_opcode *opcode;
8447 const struct mips_opcode *invalid_delay_slot;
8448 bfd_boolean seen_valid_for_isa, seen_valid_for_size;
8450 /* Search for a match, ignoring alternatives that don't satisfy the
8451 current ISA or forced_length. */
8452 invalid_delay_slot = 0;
8453 seen_valid_for_isa = FALSE;
8454 seen_valid_for_size = FALSE;
8458 gas_assert (strcmp (opcode->name, first->name) == 0);
8459 if (is_opcode_valid (opcode))
8461 seen_valid_for_isa = TRUE;
8462 if (is_size_valid (opcode))
8464 bfd_boolean delay_slot_ok;
8466 seen_valid_for_size = TRUE;
8467 delay_slot_ok = is_delay_slot_valid (opcode);
8468 if (match_insn (insn, opcode, tokens, opcode_extra,
8469 lax_match, delay_slot_ok))
8473 if (!invalid_delay_slot)
8474 invalid_delay_slot = opcode;
8483 while (opcode < past && strcmp (opcode->name, first->name) == 0);
8485 /* If the only matches we found had the wrong length for the delay slot,
8486 pick the first such match. We'll issue an appropriate warning later. */
8487 if (invalid_delay_slot)
8489 if (match_insn (insn, invalid_delay_slot, tokens, opcode_extra,
8495 /* Handle the case where we didn't try to match an instruction because
8496 all the alternatives were incompatible with the current ISA. */
8497 if (!seen_valid_for_isa)
8499 match_invalid_for_isa ();
8503 /* Handle the case where we didn't try to match an instruction because
8504 all the alternatives were of the wrong size. */
8505 if (!seen_valid_for_size)
8507 if (mips_opts.insn32)
8508 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
8511 (0, _("unrecognized %d-bit version of microMIPS opcode"),
8512 8 * forced_insn_length);
8519 /* Like match_insns, but for MIPS16. */
8522 match_mips16_insns (struct mips_cl_insn *insn, const struct mips_opcode *first,
8523 struct mips_operand_token *tokens)
8525 const struct mips_opcode *opcode;
8526 bfd_boolean seen_valid_for_isa;
8527 bfd_boolean seen_valid_for_size;
8529 /* Search for a match, ignoring alternatives that don't satisfy the
8530 current ISA. There are no separate entries for extended forms so
8531 we deal with forced_length later. */
8532 seen_valid_for_isa = FALSE;
8533 seen_valid_for_size = FALSE;
8537 gas_assert (strcmp (opcode->name, first->name) == 0);
8538 if (is_opcode_valid_16 (opcode))
8540 seen_valid_for_isa = TRUE;
8541 if (is_size_valid_16 (opcode))
8543 seen_valid_for_size = TRUE;
8544 if (match_mips16_insn (insn, opcode, tokens))
8550 while (opcode < &mips16_opcodes[bfd_mips16_num_opcodes]
8551 && strcmp (opcode->name, first->name) == 0);
8553 /* Handle the case where we didn't try to match an instruction because
8554 all the alternatives were incompatible with the current ISA. */
8555 if (!seen_valid_for_isa)
8557 match_invalid_for_isa ();
8561 /* Handle the case where we didn't try to match an instruction because
8562 all the alternatives were of the wrong size. */
8563 if (!seen_valid_for_size)
8565 if (forced_insn_length == 2)
8567 (0, _("unrecognized unextended version of MIPS16 opcode"));
8570 (0, _("unrecognized extended version of MIPS16 opcode"));
8577 /* Set up global variables for the start of a new macro. */
8582 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
8583 memset (&mips_macro_warning.first_insn_sizes, 0,
8584 sizeof (mips_macro_warning.first_insn_sizes));
8585 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
8586 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
8587 && delayed_branch_p (&history[0]));
8589 && history[0].frag->fr_type == rs_machine_dependent
8590 && RELAX_MICROMIPS_P (history[0].frag->fr_subtype)
8591 && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype))
8592 mips_macro_warning.delay_slot_length = 0;
8594 switch (history[0].insn_mo->pinfo2
8595 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
8597 case INSN2_BRANCH_DELAY_32BIT:
8598 mips_macro_warning.delay_slot_length = 4;
8600 case INSN2_BRANCH_DELAY_16BIT:
8601 mips_macro_warning.delay_slot_length = 2;
8604 mips_macro_warning.delay_slot_length = 0;
8607 mips_macro_warning.first_frag = NULL;
8610 /* Given that a macro is longer than one instruction or of the wrong size,
8611 return the appropriate warning for it. Return null if no warning is
8612 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8613 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8614 and RELAX_NOMACRO. */
8617 macro_warning (relax_substateT subtype)
8619 if (subtype & RELAX_DELAY_SLOT)
8620 return _("macro instruction expanded into multiple instructions"
8621 " in a branch delay slot");
8622 else if (subtype & RELAX_NOMACRO)
8623 return _("macro instruction expanded into multiple instructions");
8624 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
8625 | RELAX_DELAY_SLOT_SIZE_SECOND))
8626 return ((subtype & RELAX_DELAY_SLOT_16BIT)
8627 ? _("macro instruction expanded into a wrong size instruction"
8628 " in a 16-bit branch delay slot")
8629 : _("macro instruction expanded into a wrong size instruction"
8630 " in a 32-bit branch delay slot"));
8635 /* Finish up a macro. Emit warnings as appropriate. */
8640 /* Relaxation warning flags. */
8641 relax_substateT subtype = 0;
8643 /* Check delay slot size requirements. */
8644 if (mips_macro_warning.delay_slot_length == 2)
8645 subtype |= RELAX_DELAY_SLOT_16BIT;
8646 if (mips_macro_warning.delay_slot_length != 0)
8648 if (mips_macro_warning.delay_slot_length
8649 != mips_macro_warning.first_insn_sizes[0])
8650 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
8651 if (mips_macro_warning.delay_slot_length
8652 != mips_macro_warning.first_insn_sizes[1])
8653 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
8656 /* Check instruction count requirements. */
8657 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
8659 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
8660 subtype |= RELAX_SECOND_LONGER;
8661 if (mips_opts.warn_about_macros)
8662 subtype |= RELAX_NOMACRO;
8663 if (mips_macro_warning.delay_slot_p)
8664 subtype |= RELAX_DELAY_SLOT;
8667 /* If both alternatives fail to fill a delay slot correctly,
8668 emit the warning now. */
8669 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
8670 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
8675 s = subtype & (RELAX_DELAY_SLOT_16BIT
8676 | RELAX_DELAY_SLOT_SIZE_FIRST
8677 | RELAX_DELAY_SLOT_SIZE_SECOND);
8678 msg = macro_warning (s);
8680 as_warn ("%s", msg);
8684 /* If both implementations are longer than 1 instruction, then emit the
8686 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
8691 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
8692 msg = macro_warning (s);
8694 as_warn ("%s", msg);
8698 /* If any flags still set, then one implementation might need a warning
8699 and the other either will need one of a different kind or none at all.
8700 Pass any remaining flags over to relaxation. */
8701 if (mips_macro_warning.first_frag != NULL)
8702 mips_macro_warning.first_frag->fr_subtype |= subtype;
8705 /* Instruction operand formats used in macros that vary between
8706 standard MIPS and microMIPS code. */
8708 static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } };
8709 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
8710 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
8711 static const char * const lui_fmt[2] = { "t,u", "s,u" };
8712 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
8713 static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } };
8714 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
8715 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
8717 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
8718 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8719 : cop12_fmt[mips_opts.micromips])
8720 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
8721 #define LUI_FMT (lui_fmt[mips_opts.micromips])
8722 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
8723 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
8724 : mem12_fmt[mips_opts.micromips])
8725 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
8726 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
8727 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
8729 /* Read a macro's relocation codes from *ARGS and store them in *R.
8730 The first argument in *ARGS will be either the code for a single
8731 relocation or -1 followed by the three codes that make up a
8732 composite relocation. */
8735 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
8739 next = va_arg (*args, int);
8741 r[0] = (bfd_reloc_code_real_type) next;
8744 for (i = 0; i < 3; i++)
8745 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
8746 /* This function is only used for 16-bit relocation fields.
8747 To make the macro code simpler, treat an unrelocated value
8748 in the same way as BFD_RELOC_LO16. */
8749 if (r[0] == BFD_RELOC_UNUSED)
8750 r[0] = BFD_RELOC_LO16;
8754 /* Build an instruction created by a macro expansion. This is passed
8755 a pointer to the count of instructions created so far, an
8756 expression, the name of the instruction to build, an operand format
8757 string, and corresponding arguments. */
8760 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
8762 const struct mips_opcode *mo = NULL;
8763 bfd_reloc_code_real_type r[3];
8764 const struct mips_opcode *amo;
8765 const struct mips_operand *operand;
8766 struct hash_control *hash;
8767 struct mips_cl_insn insn;
8771 va_start (args, fmt);
8773 if (mips_opts.mips16)
8775 mips16_macro_build (ep, name, fmt, &args);
8780 r[0] = BFD_RELOC_UNUSED;
8781 r[1] = BFD_RELOC_UNUSED;
8782 r[2] = BFD_RELOC_UNUSED;
8783 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
8784 amo = (struct mips_opcode *) hash_find (hash, name);
8786 gas_assert (strcmp (name, amo->name) == 0);
8790 /* Search until we get a match for NAME. It is assumed here that
8791 macros will never generate MDMX, MIPS-3D, or MT instructions.
8792 We try to match an instruction that fulfills the branch delay
8793 slot instruction length requirement (if any) of the previous
8794 instruction. While doing this we record the first instruction
8795 seen that matches all the other conditions and use it anyway
8796 if the requirement cannot be met; we will issue an appropriate
8797 warning later on. */
8798 if (strcmp (fmt, amo->args) == 0
8799 && amo->pinfo != INSN_MACRO
8800 && is_opcode_valid (amo)
8801 && is_size_valid (amo))
8803 if (is_delay_slot_valid (amo))
8813 gas_assert (amo->name);
8815 while (strcmp (name, amo->name) == 0);
8818 create_insn (&insn, mo);
8831 macro_read_relocs (&args, r);
8832 gas_assert (*r == BFD_RELOC_GPREL16
8833 || *r == BFD_RELOC_MIPS_HIGHER
8834 || *r == BFD_RELOC_HI16_S
8835 || *r == BFD_RELOC_LO16
8836 || *r == BFD_RELOC_MIPS_GOT_OFST);
8840 macro_read_relocs (&args, r);
8844 macro_read_relocs (&args, r);
8845 gas_assert (ep != NULL
8846 && (ep->X_op == O_constant
8847 || (ep->X_op == O_symbol
8848 && (*r == BFD_RELOC_MIPS_HIGHEST
8849 || *r == BFD_RELOC_HI16_S
8850 || *r == BFD_RELOC_HI16
8851 || *r == BFD_RELOC_GPREL16
8852 || *r == BFD_RELOC_MIPS_GOT_HI16
8853 || *r == BFD_RELOC_MIPS_CALL_HI16))));
8857 gas_assert (ep != NULL);
8860 * This allows macro() to pass an immediate expression for
8861 * creating short branches without creating a symbol.
8863 * We don't allow branch relaxation for these branches, as
8864 * they should only appear in ".set nomacro" anyway.
8866 if (ep->X_op == O_constant)
8868 /* For microMIPS we always use relocations for branches.
8869 So we should not resolve immediate values. */
8870 gas_assert (!mips_opts.micromips);
8872 if ((ep->X_add_number & 3) != 0)
8873 as_bad (_("branch to misaligned address (0x%lx)"),
8874 (unsigned long) ep->X_add_number);
8875 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
8876 as_bad (_("branch address range overflow (0x%lx)"),
8877 (unsigned long) ep->X_add_number);
8878 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
8882 *r = BFD_RELOC_16_PCREL_S2;
8886 gas_assert (ep != NULL);
8887 *r = BFD_RELOC_MIPS_JMP;
8891 operand = (mips_opts.micromips
8892 ? decode_micromips_operand (fmt)
8893 : decode_mips_operand (fmt));
8897 uval = va_arg (args, int);
8898 if (operand->type == OP_CLO_CLZ_DEST)
8899 uval |= (uval << 5);
8900 insn_insert_operand (&insn, operand, uval);
8902 if (*fmt == '+' || *fmt == 'm' || *fmt == '-')
8908 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
8910 append_insn (&insn, ep, r, TRUE);
8914 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
8917 struct mips_opcode *mo;
8918 struct mips_cl_insn insn;
8919 const struct mips_operand *operand;
8920 bfd_reloc_code_real_type r[3]
8921 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
8923 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
8925 gas_assert (strcmp (name, mo->name) == 0);
8927 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
8930 gas_assert (mo->name);
8931 gas_assert (strcmp (name, mo->name) == 0);
8934 create_insn (&insn, mo);
8971 gas_assert (ep != NULL);
8973 if (ep->X_op != O_constant)
8974 *r = (int) BFD_RELOC_UNUSED + c;
8975 else if (calculate_reloc (*r, ep->X_add_number, &value))
8977 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode);
8979 *r = BFD_RELOC_UNUSED;
8985 operand = decode_mips16_operand (c, FALSE);
8989 insn_insert_operand (&insn, operand, va_arg (*args, int));
8994 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
8996 append_insn (&insn, ep, r, TRUE);
9000 * Generate a "jalr" instruction with a relocation hint to the called
9001 * function. This occurs in NewABI PIC code.
9004 macro_build_jalr (expressionS *ep, int cprestore)
9006 static const bfd_reloc_code_real_type jalr_relocs[2]
9007 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
9008 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
9012 if (MIPS_JALR_HINT_P (ep))
9017 if (mips_opts.micromips)
9019 jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32
9020 ? "jalr" : "jalrs");
9021 if (MIPS_JALR_HINT_P (ep)
9023 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
9024 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
9026 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
9029 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
9030 if (MIPS_JALR_HINT_P (ep))
9031 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
9035 * Generate a "lui" instruction.
9038 macro_build_lui (expressionS *ep, int regnum)
9040 gas_assert (! mips_opts.mips16);
9042 if (ep->X_op != O_constant)
9044 gas_assert (ep->X_op == O_symbol);
9045 /* _gp_disp is a special case, used from s_cpload.
9046 __gnu_local_gp is used if mips_no_shared. */
9047 gas_assert (mips_pic == NO_PIC
9049 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
9050 || (! mips_in_shared
9051 && strcmp (S_GET_NAME (ep->X_add_symbol),
9052 "__gnu_local_gp") == 0));
9055 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
9058 /* Generate a sequence of instructions to do a load or store from a constant
9059 offset off of a base register (breg) into/from a target register (treg),
9060 using AT if necessary. */
9062 macro_build_ldst_constoffset (expressionS *ep, const char *op,
9063 int treg, int breg, int dbl)
9065 gas_assert (ep->X_op == O_constant);
9067 /* Sign-extending 32-bit constants makes their handling easier. */
9069 normalize_constant_expr (ep);
9071 /* Right now, this routine can only handle signed 32-bit constants. */
9072 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
9073 as_warn (_("operand overflow"));
9075 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
9077 /* Signed 16-bit offset will fit in the op. Easy! */
9078 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
9082 /* 32-bit offset, need multiple instructions and AT, like:
9083 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
9084 addu $tempreg,$tempreg,$breg
9085 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
9086 to handle the complete offset. */
9087 macro_build_lui (ep, AT);
9088 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
9089 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
9092 as_bad (_("macro used $at after \".set noat\""));
9097 * Generates code to set the $at register to true (one)
9098 * if reg is less than the immediate expression.
9101 set_at (int reg, int unsignedp)
9103 if (imm_expr.X_add_number >= -0x8000
9104 && imm_expr.X_add_number < 0x8000)
9105 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
9106 AT, reg, BFD_RELOC_LO16);
9109 load_register (AT, &imm_expr, GPR_SIZE == 64);
9110 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
9114 /* Count the leading zeroes by performing a binary chop. This is a
9115 bulky bit of source, but performance is a LOT better for the
9116 majority of values than a simple loop to count the bits:
9117 for (lcnt = 0; (lcnt < 32); lcnt++)
9118 if ((v) & (1 << (31 - lcnt)))
9120 However it is not code size friendly, and the gain will drop a bit
9121 on certain cached systems.
9123 #define COUNT_TOP_ZEROES(v) \
9124 (((v) & ~0xffff) == 0 \
9125 ? ((v) & ~0xff) == 0 \
9126 ? ((v) & ~0xf) == 0 \
9127 ? ((v) & ~0x3) == 0 \
9128 ? ((v) & ~0x1) == 0 \
9133 : ((v) & ~0x7) == 0 \
9136 : ((v) & ~0x3f) == 0 \
9137 ? ((v) & ~0x1f) == 0 \
9140 : ((v) & ~0x7f) == 0 \
9143 : ((v) & ~0xfff) == 0 \
9144 ? ((v) & ~0x3ff) == 0 \
9145 ? ((v) & ~0x1ff) == 0 \
9148 : ((v) & ~0x7ff) == 0 \
9151 : ((v) & ~0x3fff) == 0 \
9152 ? ((v) & ~0x1fff) == 0 \
9155 : ((v) & ~0x7fff) == 0 \
9158 : ((v) & ~0xffffff) == 0 \
9159 ? ((v) & ~0xfffff) == 0 \
9160 ? ((v) & ~0x3ffff) == 0 \
9161 ? ((v) & ~0x1ffff) == 0 \
9164 : ((v) & ~0x7ffff) == 0 \
9167 : ((v) & ~0x3fffff) == 0 \
9168 ? ((v) & ~0x1fffff) == 0 \
9171 : ((v) & ~0x7fffff) == 0 \
9174 : ((v) & ~0xfffffff) == 0 \
9175 ? ((v) & ~0x3ffffff) == 0 \
9176 ? ((v) & ~0x1ffffff) == 0 \
9179 : ((v) & ~0x7ffffff) == 0 \
9182 : ((v) & ~0x3fffffff) == 0 \
9183 ? ((v) & ~0x1fffffff) == 0 \
9186 : ((v) & ~0x7fffffff) == 0 \
9191 * This routine generates the least number of instructions necessary to load
9192 * an absolute expression value into a register.
9195 load_register (int reg, expressionS *ep, int dbl)
9198 expressionS hi32, lo32;
9200 if (ep->X_op != O_big)
9202 gas_assert (ep->X_op == O_constant);
9204 /* Sign-extending 32-bit constants makes their handling easier. */
9206 normalize_constant_expr (ep);
9208 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
9210 /* We can handle 16 bit signed values with an addiu to
9211 $zero. No need to ever use daddiu here, since $zero and
9212 the result are always correct in 32 bit mode. */
9213 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
9216 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
9218 /* We can handle 16 bit unsigned values with an ori to
9220 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
9223 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
9225 /* 32 bit values require an lui. */
9226 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
9227 if ((ep->X_add_number & 0xffff) != 0)
9228 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
9233 /* The value is larger than 32 bits. */
9235 if (!dbl || GPR_SIZE == 32)
9239 sprintf_vma (value, ep->X_add_number);
9240 as_bad (_("number (0x%s) larger than 32 bits"), value);
9241 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
9245 if (ep->X_op != O_big)
9248 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
9249 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
9250 hi32.X_add_number &= 0xffffffff;
9252 lo32.X_add_number &= 0xffffffff;
9256 gas_assert (ep->X_add_number > 2);
9257 if (ep->X_add_number == 3)
9258 generic_bignum[3] = 0;
9259 else if (ep->X_add_number > 4)
9260 as_bad (_("number larger than 64 bits"));
9261 lo32.X_op = O_constant;
9262 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
9263 hi32.X_op = O_constant;
9264 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
9267 if (hi32.X_add_number == 0)
9272 unsigned long hi, lo;
9274 if (hi32.X_add_number == (offsetT) 0xffffffff)
9276 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
9278 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
9281 if (lo32.X_add_number & 0x80000000)
9283 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
9284 if (lo32.X_add_number & 0xffff)
9285 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
9290 /* Check for 16bit shifted constant. We know that hi32 is
9291 non-zero, so start the mask on the first bit of the hi32
9296 unsigned long himask, lomask;
9300 himask = 0xffff >> (32 - shift);
9301 lomask = (0xffff << shift) & 0xffffffff;
9305 himask = 0xffff << (shift - 32);
9308 if ((hi32.X_add_number & ~(offsetT) himask) == 0
9309 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
9313 tmp.X_op = O_constant;
9315 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
9316 | (lo32.X_add_number >> shift));
9318 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
9319 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
9320 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
9321 reg, reg, (shift >= 32) ? shift - 32 : shift);
9326 while (shift <= (64 - 16));
9328 /* Find the bit number of the lowest one bit, and store the
9329 shifted value in hi/lo. */
9330 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
9331 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
9335 while ((lo & 1) == 0)
9340 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
9346 while ((hi & 1) == 0)
9355 /* Optimize if the shifted value is a (power of 2) - 1. */
9356 if ((hi == 0 && ((lo + 1) & lo) == 0)
9357 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
9359 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
9364 /* This instruction will set the register to be all
9366 tmp.X_op = O_constant;
9367 tmp.X_add_number = (offsetT) -1;
9368 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
9372 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
9373 reg, reg, (bit >= 32) ? bit - 32 : bit);
9375 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
9376 reg, reg, (shift >= 32) ? shift - 32 : shift);
9381 /* Sign extend hi32 before calling load_register, because we can
9382 generally get better code when we load a sign extended value. */
9383 if ((hi32.X_add_number & 0x80000000) != 0)
9384 hi32.X_add_number |= ~(offsetT) 0xffffffff;
9385 load_register (reg, &hi32, 0);
9388 if ((lo32.X_add_number & 0xffff0000) == 0)
9392 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
9400 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
9402 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
9403 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
9409 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
9413 mid16.X_add_number >>= 16;
9414 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
9415 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
9418 if ((lo32.X_add_number & 0xffff) != 0)
9419 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
9423 load_delay_nop (void)
9425 if (!gpr_interlocks)
9426 macro_build (NULL, "nop", "");
9429 /* Load an address into a register. */
9432 load_address (int reg, expressionS *ep, int *used_at)
9434 if (ep->X_op != O_constant
9435 && ep->X_op != O_symbol)
9437 as_bad (_("expression too complex"));
9438 ep->X_op = O_constant;
9441 if (ep->X_op == O_constant)
9443 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
9447 if (mips_pic == NO_PIC)
9449 /* If this is a reference to a GP relative symbol, we want
9450 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
9452 lui $reg,<sym> (BFD_RELOC_HI16_S)
9453 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9454 If we have an addend, we always use the latter form.
9456 With 64bit address space and a usable $at we want
9457 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9458 lui $at,<sym> (BFD_RELOC_HI16_S)
9459 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9460 daddiu $at,<sym> (BFD_RELOC_LO16)
9464 If $at is already in use, we use a path which is suboptimal
9465 on superscalar processors.
9466 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9467 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9469 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9471 daddiu $reg,<sym> (BFD_RELOC_LO16)
9473 For GP relative symbols in 64bit address space we can use
9474 the same sequence as in 32bit address space. */
9475 if (HAVE_64BIT_SYMBOLS)
9477 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
9478 && !nopic_need_relax (ep->X_add_symbol, 1))
9480 relax_start (ep->X_add_symbol);
9481 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
9482 mips_gp_register, BFD_RELOC_GPREL16);
9486 if (*used_at == 0 && mips_opts.at)
9488 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
9489 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
9490 macro_build (ep, "daddiu", "t,r,j", reg, reg,
9491 BFD_RELOC_MIPS_HIGHER);
9492 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
9493 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
9494 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
9499 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
9500 macro_build (ep, "daddiu", "t,r,j", reg, reg,
9501 BFD_RELOC_MIPS_HIGHER);
9502 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
9503 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
9504 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
9505 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
9508 if (mips_relax.sequence)
9513 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
9514 && !nopic_need_relax (ep->X_add_symbol, 1))
9516 relax_start (ep->X_add_symbol);
9517 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
9518 mips_gp_register, BFD_RELOC_GPREL16);
9521 macro_build_lui (ep, reg);
9522 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
9523 reg, reg, BFD_RELOC_LO16);
9524 if (mips_relax.sequence)
9528 else if (!mips_big_got)
9532 /* If this is a reference to an external symbol, we want
9533 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9535 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9537 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9538 If there is a constant, it must be added in after.
9540 If we have NewABI, we want
9541 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9542 unless we're referencing a global symbol with a non-zero
9543 offset, in which case cst must be added separately. */
9546 if (ep->X_add_number)
9548 ex.X_add_number = ep->X_add_number;
9549 ep->X_add_number = 0;
9550 relax_start (ep->X_add_symbol);
9551 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9552 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9553 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9554 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9555 ex.X_op = O_constant;
9556 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
9557 reg, reg, BFD_RELOC_LO16);
9558 ep->X_add_number = ex.X_add_number;
9561 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9562 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9563 if (mips_relax.sequence)
9568 ex.X_add_number = ep->X_add_number;
9569 ep->X_add_number = 0;
9570 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9571 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9573 relax_start (ep->X_add_symbol);
9575 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9579 if (ex.X_add_number != 0)
9581 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9582 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9583 ex.X_op = O_constant;
9584 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
9585 reg, reg, BFD_RELOC_LO16);
9589 else if (mips_big_got)
9593 /* This is the large GOT case. If this is a reference to an
9594 external symbol, we want
9595 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9597 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
9599 Otherwise, for a reference to a local symbol in old ABI, we want
9600 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9602 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9603 If there is a constant, it must be added in after.
9605 In the NewABI, for local symbols, with or without offsets, we want:
9606 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9607 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9611 ex.X_add_number = ep->X_add_number;
9612 ep->X_add_number = 0;
9613 relax_start (ep->X_add_symbol);
9614 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
9615 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9616 reg, reg, mips_gp_register);
9617 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
9618 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
9619 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9620 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9621 else if (ex.X_add_number)
9623 ex.X_op = O_constant;
9624 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9628 ep->X_add_number = ex.X_add_number;
9630 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9631 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
9632 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9633 BFD_RELOC_MIPS_GOT_OFST);
9638 ex.X_add_number = ep->X_add_number;
9639 ep->X_add_number = 0;
9640 relax_start (ep->X_add_symbol);
9641 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
9642 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9643 reg, reg, mips_gp_register);
9644 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
9645 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
9647 if (reg_needs_delay (mips_gp_register))
9649 /* We need a nop before loading from $gp. This special
9650 check is required because the lui which starts the main
9651 instruction stream does not refer to $gp, and so will not
9652 insert the nop which may be required. */
9653 macro_build (NULL, "nop", "");
9655 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9656 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9658 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9662 if (ex.X_add_number != 0)
9664 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9665 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9666 ex.X_op = O_constant;
9667 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9675 if (!mips_opts.at && *used_at == 1)
9676 as_bad (_("macro used $at after \".set noat\""));
9679 /* Move the contents of register SOURCE into register DEST. */
9682 move_register (int dest, int source)
9684 /* Prefer to use a 16-bit microMIPS instruction unless the previous
9685 instruction specifically requires a 32-bit one. */
9686 if (mips_opts.micromips
9687 && !mips_opts.insn32
9688 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
9689 macro_build (NULL, "move", "mp,mj", dest, source);
9691 macro_build (NULL, "or", "d,v,t", dest, source, 0);
9694 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
9695 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
9696 The two alternatives are:
9698 Global symbol Local symbol
9699 ------------- ------------
9700 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
9702 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
9704 load_got_offset emits the first instruction and add_got_offset
9705 emits the second for a 16-bit offset or add_got_offset_hilo emits
9706 a sequence to add a 32-bit offset using a scratch register. */
9709 load_got_offset (int dest, expressionS *local)
9714 global.X_add_number = 0;
9716 relax_start (local->X_add_symbol);
9717 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
9718 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9720 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
9721 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9726 add_got_offset (int dest, expressionS *local)
9730 global.X_op = O_constant;
9731 global.X_op_symbol = NULL;
9732 global.X_add_symbol = NULL;
9733 global.X_add_number = local->X_add_number;
9735 relax_start (local->X_add_symbol);
9736 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
9737 dest, dest, BFD_RELOC_LO16);
9739 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
9744 add_got_offset_hilo (int dest, expressionS *local, int tmp)
9747 int hold_mips_optimize;
9749 global.X_op = O_constant;
9750 global.X_op_symbol = NULL;
9751 global.X_add_symbol = NULL;
9752 global.X_add_number = local->X_add_number;
9754 relax_start (local->X_add_symbol);
9755 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
9757 /* Set mips_optimize around the lui instruction to avoid
9758 inserting an unnecessary nop after the lw. */
9759 hold_mips_optimize = mips_optimize;
9761 macro_build_lui (&global, tmp);
9762 mips_optimize = hold_mips_optimize;
9763 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
9766 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
9769 /* Emit a sequence of instructions to emulate a branch likely operation.
9770 BR is an ordinary branch corresponding to one to be emulated. BRNEG
9771 is its complementing branch with the original condition negated.
9772 CALL is set if the original branch specified the link operation.
9773 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
9775 Code like this is produced in the noreorder mode:
9780 delay slot (executed only if branch taken)
9788 delay slot (executed only if branch taken)
9791 In the reorder mode the delay slot would be filled with a nop anyway,
9792 so code produced is simply:
9797 This function is used when producing code for the microMIPS ASE that
9798 does not implement branch likely instructions in hardware. */
9801 macro_build_branch_likely (const char *br, const char *brneg,
9802 int call, expressionS *ep, const char *fmt,
9803 unsigned int sreg, unsigned int treg)
9805 int noreorder = mips_opts.noreorder;
9808 gas_assert (mips_opts.micromips);
9812 micromips_label_expr (&expr1);
9813 macro_build (&expr1, brneg, fmt, sreg, treg);
9814 macro_build (NULL, "nop", "");
9815 macro_build (ep, call ? "bal" : "b", "p");
9817 /* Set to true so that append_insn adds a label. */
9818 emit_branch_likely_macro = TRUE;
9822 macro_build (ep, br, fmt, sreg, treg);
9823 macro_build (NULL, "nop", "");
9828 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
9829 the condition code tested. EP specifies the branch target. */
9832 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
9859 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
9862 /* Emit a two-argument branch macro specified by TYPE, using SREG as
9863 the register tested. EP specifies the branch target. */
9866 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
9868 const char *brneg = NULL;
9878 br = mips_opts.micromips ? "bgez" : "bgezl";
9882 gas_assert (mips_opts.micromips);
9883 br = mips_opts.insn32 ? "bgezal" : "bgezals";
9891 br = mips_opts.micromips ? "bgtz" : "bgtzl";
9898 br = mips_opts.micromips ? "blez" : "blezl";
9905 br = mips_opts.micromips ? "bltz" : "bltzl";
9909 gas_assert (mips_opts.micromips);
9910 br = mips_opts.insn32 ? "bltzal" : "bltzals";
9917 if (mips_opts.micromips && brneg)
9918 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
9920 macro_build (ep, br, "s,p", sreg);
9923 /* Emit a three-argument branch macro specified by TYPE, using SREG and
9924 TREG as the registers tested. EP specifies the branch target. */
9927 macro_build_branch_rsrt (int type, expressionS *ep,
9928 unsigned int sreg, unsigned int treg)
9930 const char *brneg = NULL;
9942 br = mips_opts.micromips ? "beq" : "beql";
9951 br = mips_opts.micromips ? "bne" : "bnel";
9957 if (mips_opts.micromips && brneg)
9958 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
9960 macro_build (ep, br, "s,t,p", sreg, treg);
9963 /* Return the high part that should be loaded in order to make the low
9964 part of VALUE accessible using an offset of OFFBITS bits. */
9967 offset_high_part (offsetT value, unsigned int offbits)
9974 bias = 1 << (offbits - 1);
9975 low_mask = bias * 2 - 1;
9976 return (value + bias) & ~low_mask;
9979 /* Return true if the value stored in offset_expr and offset_reloc
9980 fits into a signed offset of OFFBITS bits. RANGE is the maximum
9981 amount that the caller wants to add without inducing overflow
9982 and ALIGN is the known alignment of the value in bytes. */
9985 small_offset_p (unsigned int range, unsigned int align, unsigned int offbits)
9989 /* Accept any relocation operator if overflow isn't a concern. */
9990 if (range < align && *offset_reloc != BFD_RELOC_UNUSED)
9993 /* These relocations are guaranteed not to overflow in correct links. */
9994 if (*offset_reloc == BFD_RELOC_MIPS_LITERAL
9995 || gprel16_reloc_p (*offset_reloc))
9998 if (offset_expr.X_op == O_constant
9999 && offset_high_part (offset_expr.X_add_number, offbits) == 0
10000 && offset_high_part (offset_expr.X_add_number + range, offbits) == 0)
10007 * This routine implements the seemingly endless macro or synthesized
10008 * instructions and addressing modes in the mips assembly language. Many
10009 * of these macros are simple and are similar to each other. These could
10010 * probably be handled by some kind of table or grammar approach instead of
10011 * this verbose method. Others are not simple macros but are more like
10012 * optimizing code generation.
10013 * One interesting optimization is when several store macros appear
10014 * consecutively that would load AT with the upper half of the same address.
10015 * The ensuing load upper instructions are omitted. This implies some kind
10016 * of global optimization. We currently only optimize within a single macro.
10017 * For many of the load and store macros if the address is specified as a
10018 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
10019 * first load register 'at' with zero and use it as the base register. The
10020 * mips assembler simply uses register $zero. Just one tiny optimization
10024 macro (struct mips_cl_insn *ip, char *str)
10026 const struct mips_operand_array *operands;
10027 unsigned int breg, i;
10028 unsigned int tempreg;
10031 expressionS label_expr;
10046 bfd_boolean large_offset;
10048 int hold_mips_optimize;
10049 unsigned int align;
10050 unsigned int op[MAX_OPERANDS];
10052 gas_assert (! mips_opts.mips16);
10054 operands = insn_operands (ip);
10055 for (i = 0; i < MAX_OPERANDS; i++)
10056 if (operands->operand[i])
10057 op[i] = insn_extract_operand (ip, operands->operand[i]);
10061 mask = ip->insn_mo->mask;
10063 label_expr.X_op = O_constant;
10064 label_expr.X_op_symbol = NULL;
10065 label_expr.X_add_symbol = NULL;
10066 label_expr.X_add_number = 0;
10068 expr1.X_op = O_constant;
10069 expr1.X_op_symbol = NULL;
10070 expr1.X_add_symbol = NULL;
10071 expr1.X_add_number = 1;
10078 /* Fall through. */
10086 start_noreorder ();
10088 if (mips_opts.micromips)
10089 micromips_label_expr (&label_expr);
10091 label_expr.X_add_number = 8;
10092 macro_build (&label_expr, "bgez", "s,p", op[1]);
10093 if (op[0] == op[1])
10094 macro_build (NULL, "nop", "");
10096 move_register (op[0], op[1]);
10097 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", op[0], 0, op[1]);
10098 if (mips_opts.micromips)
10099 micromips_add_label ();
10116 if (!mips_opts.micromips)
10118 if (imm_expr.X_add_number >= -0x200
10119 && imm_expr.X_add_number < 0x200)
10121 macro_build (NULL, s, "t,r,.", op[0], op[1],
10122 (int) imm_expr.X_add_number);
10131 if (imm_expr.X_add_number >= -0x8000
10132 && imm_expr.X_add_number < 0x8000)
10134 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
10139 load_register (AT, &imm_expr, dbl);
10140 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
10159 if (imm_expr.X_add_number >= 0
10160 && imm_expr.X_add_number < 0x10000)
10162 if (mask != M_NOR_I)
10163 macro_build (&imm_expr, s, "t,r,i", op[0], op[1], BFD_RELOC_LO16);
10166 macro_build (&imm_expr, "ori", "t,r,i",
10167 op[0], op[1], BFD_RELOC_LO16);
10168 macro_build (NULL, "nor", "d,v,t", op[0], op[0], 0);
10174 load_register (AT, &imm_expr, GPR_SIZE == 64);
10175 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
10179 switch (imm_expr.X_add_number)
10182 macro_build (NULL, "nop", "");
10185 macro_build (NULL, "packrl.ph", "d,s,t", op[0], op[0], op[1]);
10189 macro_build (NULL, "balign", "t,s,2", op[0], op[1],
10190 (int) imm_expr.X_add_number);
10193 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
10194 (unsigned long) imm_expr.X_add_number);
10203 gas_assert (mips_opts.micromips);
10204 macro_build_branch_ccl (mask, &offset_expr,
10205 EXTRACT_OPERAND (1, BCC, *ip));
10212 if (imm_expr.X_add_number == 0)
10218 load_register (op[1], &imm_expr, GPR_SIZE == 64);
10220 /* Fall through. */
10223 macro_build_branch_rsrt (mask, &offset_expr, op[0], op[1]);
10228 /* Fall through. */
10231 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[0]);
10232 else if (op[0] == 0)
10233 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[1]);
10237 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
10238 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10239 &offset_expr, AT, ZERO);
10249 macro_build_branch_rs (mask, &offset_expr, op[0]);
10254 /* Fall through. */
10256 /* Check for > max integer. */
10257 if (imm_expr.X_add_number >= GPR_SMAX)
10260 /* Result is always false. */
10262 macro_build (NULL, "nop", "");
10264 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
10267 ++imm_expr.X_add_number;
10271 if (mask == M_BGEL_I)
10273 if (imm_expr.X_add_number == 0)
10275 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
10276 &offset_expr, op[0]);
10279 if (imm_expr.X_add_number == 1)
10281 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
10282 &offset_expr, op[0]);
10285 if (imm_expr.X_add_number <= GPR_SMIN)
10288 /* result is always true */
10289 as_warn (_("branch %s is always true"), ip->insn_mo->name);
10290 macro_build (&offset_expr, "b", "p");
10295 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10296 &offset_expr, AT, ZERO);
10301 /* Fall through. */
10305 else if (op[0] == 0)
10306 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10307 &offset_expr, ZERO, op[1]);
10311 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
10312 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10313 &offset_expr, AT, ZERO);
10319 /* Fall through. */
10323 && imm_expr.X_add_number == -1))
10325 ++imm_expr.X_add_number;
10329 if (mask == M_BGEUL_I)
10331 if (imm_expr.X_add_number == 0)
10333 else if (imm_expr.X_add_number == 1)
10334 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10335 &offset_expr, op[0], ZERO);
10340 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10341 &offset_expr, AT, ZERO);
10347 /* Fall through. */
10350 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[0]);
10351 else if (op[0] == 0)
10352 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[1]);
10356 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
10357 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10358 &offset_expr, AT, ZERO);
10364 /* Fall through. */
10367 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10368 &offset_expr, op[0], ZERO);
10369 else if (op[0] == 0)
10374 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
10375 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10376 &offset_expr, AT, ZERO);
10382 /* Fall through. */
10385 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
10386 else if (op[0] == 0)
10387 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[1]);
10391 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
10392 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10393 &offset_expr, AT, ZERO);
10399 /* Fall through. */
10401 if (imm_expr.X_add_number >= GPR_SMAX)
10403 ++imm_expr.X_add_number;
10407 if (mask == M_BLTL_I)
10409 if (imm_expr.X_add_number == 0)
10410 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
10411 else if (imm_expr.X_add_number == 1)
10412 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
10417 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10418 &offset_expr, AT, ZERO);
10424 /* Fall through. */
10427 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10428 &offset_expr, op[0], ZERO);
10429 else if (op[0] == 0)
10434 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
10435 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10436 &offset_expr, AT, ZERO);
10442 /* Fall through. */
10446 && imm_expr.X_add_number == -1))
10448 ++imm_expr.X_add_number;
10452 if (mask == M_BLTUL_I)
10454 if (imm_expr.X_add_number == 0)
10456 else if (imm_expr.X_add_number == 1)
10457 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10458 &offset_expr, op[0], ZERO);
10463 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10464 &offset_expr, AT, ZERO);
10470 /* Fall through. */
10473 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
10474 else if (op[0] == 0)
10475 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[1]);
10479 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
10480 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10481 &offset_expr, AT, ZERO);
10487 /* Fall through. */
10491 else if (op[0] == 0)
10492 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10493 &offset_expr, ZERO, op[1]);
10497 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
10498 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10499 &offset_expr, AT, ZERO);
10505 /* Fall through. */
10511 /* Fall through. */
10517 as_warn (_("divide by zero"));
10519 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
10521 macro_build (NULL, "break", BRK_FMT, 7);
10525 start_noreorder ();
10528 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
10529 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
10533 if (mips_opts.micromips)
10534 micromips_label_expr (&label_expr);
10536 label_expr.X_add_number = 8;
10537 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
10538 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
10539 macro_build (NULL, "break", BRK_FMT, 7);
10540 if (mips_opts.micromips)
10541 micromips_add_label ();
10543 expr1.X_add_number = -1;
10545 load_register (AT, &expr1, dbl);
10546 if (mips_opts.micromips)
10547 micromips_label_expr (&label_expr);
10549 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
10550 macro_build (&label_expr, "bne", "s,t,p", op[2], AT);
10553 expr1.X_add_number = 1;
10554 load_register (AT, &expr1, dbl);
10555 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
10559 expr1.X_add_number = 0x80000000;
10560 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
10564 macro_build (NULL, "teq", TRAP_FMT, op[1], AT, 6);
10565 /* We want to close the noreorder block as soon as possible, so
10566 that later insns are available for delay slot filling. */
10571 if (mips_opts.micromips)
10572 micromips_label_expr (&label_expr);
10574 label_expr.X_add_number = 8;
10575 macro_build (&label_expr, "bne", "s,t,p", op[1], AT);
10576 macro_build (NULL, "nop", "");
10578 /* We want to close the noreorder block as soon as possible, so
10579 that later insns are available for delay slot filling. */
10582 macro_build (NULL, "break", BRK_FMT, 6);
10584 if (mips_opts.micromips)
10585 micromips_add_label ();
10586 macro_build (NULL, s, MFHL_FMT, op[0]);
10625 if (imm_expr.X_add_number == 0)
10627 as_warn (_("divide by zero"));
10629 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
10631 macro_build (NULL, "break", BRK_FMT, 7);
10634 if (imm_expr.X_add_number == 1)
10636 if (strcmp (s2, "mflo") == 0)
10637 move_register (op[0], op[1]);
10639 move_register (op[0], ZERO);
10642 if (imm_expr.X_add_number == -1 && s[strlen (s) - 1] != 'u')
10644 if (strcmp (s2, "mflo") == 0)
10645 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", op[0], op[1]);
10647 move_register (op[0], ZERO);
10652 load_register (AT, &imm_expr, dbl);
10653 macro_build (NULL, s, "z,s,t", op[1], AT);
10654 macro_build (NULL, s2, MFHL_FMT, op[0]);
10673 start_noreorder ();
10676 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
10677 macro_build (NULL, s, "z,s,t", op[1], op[2]);
10678 /* We want to close the noreorder block as soon as possible, so
10679 that later insns are available for delay slot filling. */
10684 if (mips_opts.micromips)
10685 micromips_label_expr (&label_expr);
10687 label_expr.X_add_number = 8;
10688 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
10689 macro_build (NULL, s, "z,s,t", op[1], op[2]);
10691 /* We want to close the noreorder block as soon as possible, so
10692 that later insns are available for delay slot filling. */
10694 macro_build (NULL, "break", BRK_FMT, 7);
10695 if (mips_opts.micromips)
10696 micromips_add_label ();
10698 macro_build (NULL, s2, MFHL_FMT, op[0]);
10703 /* Fall through. */
10709 /* Fall through. */
10712 /* Load the address of a symbol into a register. If breg is not
10713 zero, we then add a base register to it. */
10716 if (dbl && GPR_SIZE == 32)
10717 as_warn (_("dla used to load 32-bit register; recommend using la "
10720 if (!dbl && HAVE_64BIT_OBJECTS)
10721 as_warn (_("la used to load 64-bit address; recommend using dla "
10724 if (small_offset_p (0, align, 16))
10726 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", op[0], breg,
10727 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
10731 if (mips_opts.at && (op[0] == breg))
10739 if (offset_expr.X_op != O_symbol
10740 && offset_expr.X_op != O_constant)
10742 as_bad (_("expression too complex"));
10743 offset_expr.X_op = O_constant;
10746 if (offset_expr.X_op == O_constant)
10747 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
10748 else if (mips_pic == NO_PIC)
10750 /* If this is a reference to a GP relative symbol, we want
10751 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
10753 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10754 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10755 If we have a constant, we need two instructions anyhow,
10756 so we may as well always use the latter form.
10758 With 64bit address space and a usable $at we want
10759 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10760 lui $at,<sym> (BFD_RELOC_HI16_S)
10761 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10762 daddiu $at,<sym> (BFD_RELOC_LO16)
10764 daddu $tempreg,$tempreg,$at
10766 If $at is already in use, we use a path which is suboptimal
10767 on superscalar processors.
10768 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10769 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10771 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10773 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
10775 For GP relative symbols in 64bit address space we can use
10776 the same sequence as in 32bit address space. */
10777 if (HAVE_64BIT_SYMBOLS)
10779 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10780 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10782 relax_start (offset_expr.X_add_symbol);
10783 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10784 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
10788 if (used_at == 0 && mips_opts.at)
10790 macro_build (&offset_expr, "lui", LUI_FMT,
10791 tempreg, BFD_RELOC_MIPS_HIGHEST);
10792 macro_build (&offset_expr, "lui", LUI_FMT,
10793 AT, BFD_RELOC_HI16_S);
10794 macro_build (&offset_expr, "daddiu", "t,r,j",
10795 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
10796 macro_build (&offset_expr, "daddiu", "t,r,j",
10797 AT, AT, BFD_RELOC_LO16);
10798 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
10799 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
10804 macro_build (&offset_expr, "lui", LUI_FMT,
10805 tempreg, BFD_RELOC_MIPS_HIGHEST);
10806 macro_build (&offset_expr, "daddiu", "t,r,j",
10807 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
10808 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
10809 macro_build (&offset_expr, "daddiu", "t,r,j",
10810 tempreg, tempreg, BFD_RELOC_HI16_S);
10811 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
10812 macro_build (&offset_expr, "daddiu", "t,r,j",
10813 tempreg, tempreg, BFD_RELOC_LO16);
10816 if (mips_relax.sequence)
10821 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10822 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10824 relax_start (offset_expr.X_add_symbol);
10825 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10826 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
10829 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
10830 as_bad (_("offset too large"));
10831 macro_build_lui (&offset_expr, tempreg);
10832 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10833 tempreg, tempreg, BFD_RELOC_LO16);
10834 if (mips_relax.sequence)
10838 else if (!mips_big_got && !HAVE_NEWABI)
10840 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
10842 /* If this is a reference to an external symbol, and there
10843 is no constant, we want
10844 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10845 or for lca or if tempreg is PIC_CALL_REG
10846 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10847 For a local symbol, we want
10848 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10850 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10852 If we have a small constant, and this is a reference to
10853 an external symbol, we want
10854 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10856 addiu $tempreg,$tempreg,<constant>
10857 For a local symbol, we want the same instruction
10858 sequence, but we output a BFD_RELOC_LO16 reloc on the
10861 If we have a large constant, and this is a reference to
10862 an external symbol, we want
10863 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10864 lui $at,<hiconstant>
10865 addiu $at,$at,<loconstant>
10866 addu $tempreg,$tempreg,$at
10867 For a local symbol, we want the same instruction
10868 sequence, but we output a BFD_RELOC_LO16 reloc on the
10872 if (offset_expr.X_add_number == 0)
10874 if (mips_pic == SVR4_PIC
10876 && (call || tempreg == PIC_CALL_REG))
10877 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
10879 relax_start (offset_expr.X_add_symbol);
10880 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10881 lw_reloc_type, mips_gp_register);
10884 /* We're going to put in an addu instruction using
10885 tempreg, so we may as well insert the nop right
10890 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10891 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
10893 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10894 tempreg, tempreg, BFD_RELOC_LO16);
10896 /* FIXME: If breg == 0, and the next instruction uses
10897 $tempreg, then if this variant case is used an extra
10898 nop will be generated. */
10900 else if (offset_expr.X_add_number >= -0x8000
10901 && offset_expr.X_add_number < 0x8000)
10903 load_got_offset (tempreg, &offset_expr);
10905 add_got_offset (tempreg, &offset_expr);
10909 expr1.X_add_number = offset_expr.X_add_number;
10910 offset_expr.X_add_number =
10911 SEXT_16BIT (offset_expr.X_add_number);
10912 load_got_offset (tempreg, &offset_expr);
10913 offset_expr.X_add_number = expr1.X_add_number;
10914 /* If we are going to add in a base register, and the
10915 target register and the base register are the same,
10916 then we are using AT as a temporary register. Since
10917 we want to load the constant into AT, we add our
10918 current AT (from the global offset table) and the
10919 register into the register now, and pretend we were
10920 not using a base register. */
10924 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10929 add_got_offset_hilo (tempreg, &offset_expr, AT);
10933 else if (!mips_big_got && HAVE_NEWABI)
10935 int add_breg_early = 0;
10937 /* If this is a reference to an external, and there is no
10938 constant, or local symbol (*), with or without a
10940 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10941 or for lca or if tempreg is PIC_CALL_REG
10942 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10944 If we have a small constant, and this is a reference to
10945 an external symbol, we want
10946 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10947 addiu $tempreg,$tempreg,<constant>
10949 If we have a large constant, and this is a reference to
10950 an external symbol, we want
10951 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10952 lui $at,<hiconstant>
10953 addiu $at,$at,<loconstant>
10954 addu $tempreg,$tempreg,$at
10956 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
10957 local symbols, even though it introduces an additional
10960 if (offset_expr.X_add_number)
10962 expr1.X_add_number = offset_expr.X_add_number;
10963 offset_expr.X_add_number = 0;
10965 relax_start (offset_expr.X_add_symbol);
10966 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10967 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10969 if (expr1.X_add_number >= -0x8000
10970 && expr1.X_add_number < 0x8000)
10972 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
10973 tempreg, tempreg, BFD_RELOC_LO16);
10975 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
10979 /* If we are going to add in a base register, and the
10980 target register and the base register are the same,
10981 then we are using AT as a temporary register. Since
10982 we want to load the constant into AT, we add our
10983 current AT (from the global offset table) and the
10984 register into the register now, and pretend we were
10985 not using a base register. */
10990 gas_assert (tempreg == AT);
10991 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10994 add_breg_early = 1;
10997 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
10998 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11004 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11007 offset_expr.X_add_number = expr1.X_add_number;
11009 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11010 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
11011 if (add_breg_early)
11013 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11014 op[0], tempreg, breg);
11020 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
11022 relax_start (offset_expr.X_add_symbol);
11023 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11024 BFD_RELOC_MIPS_CALL16, mips_gp_register);
11026 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11027 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
11032 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11033 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
11036 else if (mips_big_got && !HAVE_NEWABI)
11039 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
11040 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
11041 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
11043 /* This is the large GOT case. If this is a reference to an
11044 external symbol, and there is no constant, we want
11045 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11046 addu $tempreg,$tempreg,$gp
11047 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11048 or for lca or if tempreg is PIC_CALL_REG
11049 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11050 addu $tempreg,$tempreg,$gp
11051 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11052 For a local symbol, we want
11053 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11055 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11057 If we have a small constant, and this is a reference to
11058 an external symbol, we want
11059 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11060 addu $tempreg,$tempreg,$gp
11061 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11063 addiu $tempreg,$tempreg,<constant>
11064 For a local symbol, we want
11065 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11067 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
11069 If we have a large constant, and this is a reference to
11070 an external symbol, we want
11071 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11072 addu $tempreg,$tempreg,$gp
11073 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11074 lui $at,<hiconstant>
11075 addiu $at,$at,<loconstant>
11076 addu $tempreg,$tempreg,$at
11077 For a local symbol, we want
11078 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11079 lui $at,<hiconstant>
11080 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
11081 addu $tempreg,$tempreg,$at
11084 expr1.X_add_number = offset_expr.X_add_number;
11085 offset_expr.X_add_number = 0;
11086 relax_start (offset_expr.X_add_symbol);
11087 gpdelay = reg_needs_delay (mips_gp_register);
11088 if (expr1.X_add_number == 0 && breg == 0
11089 && (call || tempreg == PIC_CALL_REG))
11091 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
11092 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
11094 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
11095 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11096 tempreg, tempreg, mips_gp_register);
11097 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11098 tempreg, lw_reloc_type, tempreg);
11099 if (expr1.X_add_number == 0)
11103 /* We're going to put in an addu instruction using
11104 tempreg, so we may as well insert the nop right
11109 else if (expr1.X_add_number >= -0x8000
11110 && expr1.X_add_number < 0x8000)
11113 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
11114 tempreg, tempreg, BFD_RELOC_LO16);
11120 /* If we are going to add in a base register, and the
11121 target register and the base register are the same,
11122 then we are using AT as a temporary register. Since
11123 we want to load the constant into AT, we add our
11124 current AT (from the global offset table) and the
11125 register into the register now, and pretend we were
11126 not using a base register. */
11131 gas_assert (tempreg == AT);
11133 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11138 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
11139 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
11143 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number);
11148 /* This is needed because this instruction uses $gp, but
11149 the first instruction on the main stream does not. */
11150 macro_build (NULL, "nop", "");
11153 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11154 local_reloc_type, mips_gp_register);
11155 if (expr1.X_add_number >= -0x8000
11156 && expr1.X_add_number < 0x8000)
11159 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11160 tempreg, tempreg, BFD_RELOC_LO16);
11161 /* FIXME: If add_number is 0, and there was no base
11162 register, the external symbol case ended with a load,
11163 so if the symbol turns out to not be external, and
11164 the next instruction uses tempreg, an unnecessary nop
11165 will be inserted. */
11171 /* We must add in the base register now, as in the
11172 external symbol case. */
11173 gas_assert (tempreg == AT);
11175 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11178 /* We set breg to 0 because we have arranged to add
11179 it in in both cases. */
11183 macro_build_lui (&expr1, AT);
11184 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11185 AT, AT, BFD_RELOC_LO16);
11186 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11187 tempreg, tempreg, AT);
11192 else if (mips_big_got && HAVE_NEWABI)
11194 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
11195 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
11196 int add_breg_early = 0;
11198 /* This is the large GOT case. If this is a reference to an
11199 external symbol, and there is no constant, we want
11200 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11201 add $tempreg,$tempreg,$gp
11202 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11203 or for lca or if tempreg is PIC_CALL_REG
11204 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11205 add $tempreg,$tempreg,$gp
11206 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11208 If we have a small constant, and this is a reference to
11209 an external symbol, we want
11210 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11211 add $tempreg,$tempreg,$gp
11212 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11213 addi $tempreg,$tempreg,<constant>
11215 If we have a large constant, and this is a reference to
11216 an external symbol, we want
11217 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11218 addu $tempreg,$tempreg,$gp
11219 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11220 lui $at,<hiconstant>
11221 addi $at,$at,<loconstant>
11222 add $tempreg,$tempreg,$at
11224 If we have NewABI, and we know it's a local symbol, we want
11225 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11226 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
11227 otherwise we have to resort to GOT_HI16/GOT_LO16. */
11229 relax_start (offset_expr.X_add_symbol);
11231 expr1.X_add_number = offset_expr.X_add_number;
11232 offset_expr.X_add_number = 0;
11234 if (expr1.X_add_number == 0 && breg == 0
11235 && (call || tempreg == PIC_CALL_REG))
11237 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
11238 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
11240 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
11241 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11242 tempreg, tempreg, mips_gp_register);
11243 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11244 tempreg, lw_reloc_type, tempreg);
11246 if (expr1.X_add_number == 0)
11248 else if (expr1.X_add_number >= -0x8000
11249 && expr1.X_add_number < 0x8000)
11251 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
11252 tempreg, tempreg, BFD_RELOC_LO16);
11254 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
11258 /* If we are going to add in a base register, and the
11259 target register and the base register are the same,
11260 then we are using AT as a temporary register. Since
11261 we want to load the constant into AT, we add our
11262 current AT (from the global offset table) and the
11263 register into the register now, and pretend we were
11264 not using a base register. */
11269 gas_assert (tempreg == AT);
11270 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11273 add_breg_early = 1;
11276 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
11277 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
11282 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11285 offset_expr.X_add_number = expr1.X_add_number;
11286 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11287 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
11288 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
11289 tempreg, BFD_RELOC_MIPS_GOT_OFST);
11290 if (add_breg_early)
11292 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11293 op[0], tempreg, breg);
11303 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", op[0], tempreg, breg);
11307 gas_assert (!mips_opts.micromips);
11308 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x01);
11312 gas_assert (!mips_opts.micromips);
11313 macro_build (NULL, "c2", "C", 0x02);
11317 gas_assert (!mips_opts.micromips);
11318 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x02);
11322 gas_assert (!mips_opts.micromips);
11323 macro_build (NULL, "c2", "C", 3);
11327 gas_assert (!mips_opts.micromips);
11328 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x03);
11332 /* The j instruction may not be used in PIC code, since it
11333 requires an absolute address. We convert it to a b
11335 if (mips_pic == NO_PIC)
11336 macro_build (&offset_expr, "j", "a");
11338 macro_build (&offset_expr, "b", "p");
11341 /* The jal instructions must be handled as macros because when
11342 generating PIC code they expand to multi-instruction
11343 sequences. Normally they are simple instructions. */
11347 /* Fall through. */
11349 gas_assert (mips_opts.micromips);
11350 if (mips_opts.insn32)
11352 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str);
11360 /* Fall through. */
11363 if (mips_pic == NO_PIC)
11365 s = jals ? "jalrs" : "jalr";
11366 if (mips_opts.micromips
11367 && !mips_opts.insn32
11369 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
11370 macro_build (NULL, s, "mj", op[1]);
11372 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
11376 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
11377 && mips_cprestore_offset >= 0);
11379 if (op[1] != PIC_CALL_REG)
11380 as_warn (_("MIPS PIC call to register other than $25"));
11382 s = ((mips_opts.micromips
11383 && !mips_opts.insn32
11384 && (!mips_opts.noreorder || cprestore))
11385 ? "jalrs" : "jalr");
11386 if (mips_opts.micromips
11387 && !mips_opts.insn32
11389 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
11390 macro_build (NULL, s, "mj", op[1]);
11392 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
11393 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
11395 if (mips_cprestore_offset < 0)
11396 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11399 if (!mips_frame_reg_valid)
11401 as_warn (_("no .frame pseudo-op used in PIC code"));
11402 /* Quiet this warning. */
11403 mips_frame_reg_valid = 1;
11405 if (!mips_cprestore_valid)
11407 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11408 /* Quiet this warning. */
11409 mips_cprestore_valid = 1;
11411 if (mips_opts.noreorder)
11412 macro_build (NULL, "nop", "");
11413 expr1.X_add_number = mips_cprestore_offset;
11414 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
11417 HAVE_64BIT_ADDRESSES);
11425 gas_assert (mips_opts.micromips);
11426 if (mips_opts.insn32)
11428 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str);
11432 /* Fall through. */
11434 if (mips_pic == NO_PIC)
11435 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
11436 else if (mips_pic == SVR4_PIC)
11438 /* If this is a reference to an external symbol, and we are
11439 using a small GOT, we want
11440 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11444 lw $gp,cprestore($sp)
11445 The cprestore value is set using the .cprestore
11446 pseudo-op. If we are using a big GOT, we want
11447 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11449 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11453 lw $gp,cprestore($sp)
11454 If the symbol is not external, we want
11455 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11457 addiu $25,$25,<sym> (BFD_RELOC_LO16)
11460 lw $gp,cprestore($sp)
11462 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11463 sequences above, minus nops, unless the symbol is local,
11464 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11470 relax_start (offset_expr.X_add_symbol);
11471 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11472 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
11475 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11476 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
11482 relax_start (offset_expr.X_add_symbol);
11483 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
11484 BFD_RELOC_MIPS_CALL_HI16);
11485 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
11486 PIC_CALL_REG, mips_gp_register);
11487 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11488 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
11491 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11492 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
11494 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11495 PIC_CALL_REG, PIC_CALL_REG,
11496 BFD_RELOC_MIPS_GOT_OFST);
11500 macro_build_jalr (&offset_expr, 0);
11504 relax_start (offset_expr.X_add_symbol);
11507 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11508 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
11517 gpdelay = reg_needs_delay (mips_gp_register);
11518 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
11519 BFD_RELOC_MIPS_CALL_HI16);
11520 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
11521 PIC_CALL_REG, mips_gp_register);
11522 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11523 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
11528 macro_build (NULL, "nop", "");
11530 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11531 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
11534 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11535 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
11537 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
11539 if (mips_cprestore_offset < 0)
11540 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11543 if (!mips_frame_reg_valid)
11545 as_warn (_("no .frame pseudo-op used in PIC code"));
11546 /* Quiet this warning. */
11547 mips_frame_reg_valid = 1;
11549 if (!mips_cprestore_valid)
11551 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11552 /* Quiet this warning. */
11553 mips_cprestore_valid = 1;
11555 if (mips_opts.noreorder)
11556 macro_build (NULL, "nop", "");
11557 expr1.X_add_number = mips_cprestore_offset;
11558 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
11561 HAVE_64BIT_ADDRESSES);
11565 else if (mips_pic == VXWORKS_PIC)
11566 as_bad (_("non-PIC jump used in PIC library"));
11673 gas_assert (!mips_opts.micromips);
11676 /* Itbl support may require additional care here. */
11682 /* Itbl support may require additional care here. */
11688 offbits = (mips_opts.micromips ? 12
11689 : ISA_IS_R6 (mips_opts.isa) ? 11
11691 /* Itbl support may require additional care here. */
11695 gas_assert (!mips_opts.micromips);
11698 /* Itbl support may require additional care here. */
11704 offbits = (mips_opts.micromips ? 12 : 16);
11709 offbits = (mips_opts.micromips ? 12 : 16);
11714 /* Itbl support may require additional care here. */
11720 offbits = (mips_opts.micromips ? 12
11721 : ISA_IS_R6 (mips_opts.isa) ? 11
11723 /* Itbl support may require additional care here. */
11729 /* Itbl support may require additional care here. */
11735 /* Itbl support may require additional care here. */
11741 offbits = (mips_opts.micromips ? 12 : 16);
11746 offbits = (mips_opts.micromips ? 12 : 16);
11751 offbits = (mips_opts.micromips ? 12
11752 : ISA_IS_R6 (mips_opts.isa) ? 9
11758 offbits = (mips_opts.micromips ? 12
11759 : ISA_IS_R6 (mips_opts.isa) ? 9
11765 offbits = (mips_opts.micromips ? 12 : 16);
11768 gas_assert (mips_opts.micromips);
11775 gas_assert (mips_opts.micromips);
11782 gas_assert (mips_opts.micromips);
11788 gas_assert (mips_opts.micromips);
11795 /* We don't want to use $0 as tempreg. */
11796 if (op[2] == op[0] + lp || op[0] + lp == ZERO)
11799 tempreg = op[0] + lp;
11815 gas_assert (!mips_opts.micromips);
11818 /* Itbl support may require additional care here. */
11824 /* Itbl support may require additional care here. */
11830 offbits = (mips_opts.micromips ? 12
11831 : ISA_IS_R6 (mips_opts.isa) ? 11
11833 /* Itbl support may require additional care here. */
11837 gas_assert (!mips_opts.micromips);
11840 /* Itbl support may require additional care here. */
11846 offbits = (mips_opts.micromips ? 12 : 16);
11851 offbits = (mips_opts.micromips ? 12 : 16);
11856 offbits = (mips_opts.micromips ? 12
11857 : ISA_IS_R6 (mips_opts.isa) ? 9
11863 offbits = (mips_opts.micromips ? 12
11864 : ISA_IS_R6 (mips_opts.isa) ? 9
11869 fmt = (mips_opts.micromips ? "k,~(b)"
11870 : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)"
11872 offbits = (mips_opts.micromips ? 12
11873 : ISA_IS_R6 (mips_opts.isa) ? 9
11883 fmt = (mips_opts.micromips ? "k,~(b)"
11884 : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)"
11886 offbits = (mips_opts.micromips ? 12
11887 : ISA_IS_R6 (mips_opts.isa) ? 9
11899 /* Itbl support may require additional care here. */
11904 offbits = (mips_opts.micromips ? 12
11905 : ISA_IS_R6 (mips_opts.isa) ? 11
11907 /* Itbl support may require additional care here. */
11913 /* Itbl support may require additional care here. */
11917 gas_assert (!mips_opts.micromips);
11920 /* Itbl support may require additional care here. */
11926 offbits = (mips_opts.micromips ? 12 : 16);
11931 offbits = (mips_opts.micromips ? 12 : 16);
11934 gas_assert (mips_opts.micromips);
11940 gas_assert (mips_opts.micromips);
11946 gas_assert (mips_opts.micromips);
11952 gas_assert (mips_opts.micromips);
11961 if (small_offset_p (0, align, 16))
11963 /* The first case exists for M_LD_AB and M_SD_AB, which are
11964 macros for o32 but which should act like normal instructions
11967 macro_build (&offset_expr, s, fmt, op[0], -1, offset_reloc[0],
11968 offset_reloc[1], offset_reloc[2], breg);
11969 else if (small_offset_p (0, align, offbits))
11972 macro_build (NULL, s, fmt, op[0], breg);
11974 macro_build (NULL, s, fmt, op[0],
11975 (int) offset_expr.X_add_number, breg);
11981 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11982 tempreg, breg, -1, offset_reloc[0],
11983 offset_reloc[1], offset_reloc[2]);
11985 macro_build (NULL, s, fmt, op[0], tempreg);
11987 macro_build (NULL, s, fmt, op[0], 0, tempreg);
11995 if (offset_expr.X_op != O_constant
11996 && offset_expr.X_op != O_symbol)
11998 as_bad (_("expression too complex"));
11999 offset_expr.X_op = O_constant;
12002 if (HAVE_32BIT_ADDRESSES
12003 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
12007 sprintf_vma (value, offset_expr.X_add_number);
12008 as_bad (_("number (0x%s) larger than 32 bits"), value);
12011 /* A constant expression in PIC code can be handled just as it
12012 is in non PIC code. */
12013 if (offset_expr.X_op == O_constant)
12015 expr1.X_add_number = offset_high_part (offset_expr.X_add_number,
12016 offbits == 0 ? 16 : offbits);
12017 offset_expr.X_add_number -= expr1.X_add_number;
12019 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
12021 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12022 tempreg, tempreg, breg);
12025 if (offset_expr.X_add_number != 0)
12026 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
12027 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
12028 macro_build (NULL, s, fmt, op[0], tempreg);
12030 else if (offbits == 16)
12031 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
12033 macro_build (NULL, s, fmt, op[0],
12034 (int) offset_expr.X_add_number, tempreg);
12036 else if (offbits != 16)
12038 /* The offset field is too narrow to be used for a low-part
12039 relocation, so load the whole address into the auxiliary
12041 load_address (tempreg, &offset_expr, &used_at);
12043 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12044 tempreg, tempreg, breg);
12046 macro_build (NULL, s, fmt, op[0], tempreg);
12048 macro_build (NULL, s, fmt, op[0], 0, tempreg);
12050 else if (mips_pic == NO_PIC)
12052 /* If this is a reference to a GP relative symbol, and there
12053 is no base register, we want
12054 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12055 Otherwise, if there is no base register, we want
12056 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12057 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12058 If we have a constant, we need two instructions anyhow,
12059 so we always use the latter form.
12061 If we have a base register, and this is a reference to a
12062 GP relative symbol, we want
12063 addu $tempreg,$breg,$gp
12064 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
12066 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12067 addu $tempreg,$tempreg,$breg
12068 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12069 With a constant we always use the latter case.
12071 With 64bit address space and no base register and $at usable,
12073 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12074 lui $at,<sym> (BFD_RELOC_HI16_S)
12075 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12078 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12079 If we have a base register, we want
12080 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12081 lui $at,<sym> (BFD_RELOC_HI16_S)
12082 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12086 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12088 Without $at we can't generate the optimal path for superscalar
12089 processors here since this would require two temporary registers.
12090 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12091 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12093 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12095 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12096 If we have a base register, we want
12097 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12098 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12100 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12102 daddu $tempreg,$tempreg,$breg
12103 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12105 For GP relative symbols in 64bit address space we can use
12106 the same sequence as in 32bit address space. */
12107 if (HAVE_64BIT_SYMBOLS)
12109 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
12110 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
12112 relax_start (offset_expr.X_add_symbol);
12115 macro_build (&offset_expr, s, fmt, op[0],
12116 BFD_RELOC_GPREL16, mips_gp_register);
12120 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12121 tempreg, breg, mips_gp_register);
12122 macro_build (&offset_expr, s, fmt, op[0],
12123 BFD_RELOC_GPREL16, tempreg);
12128 if (used_at == 0 && mips_opts.at)
12130 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
12131 BFD_RELOC_MIPS_HIGHEST);
12132 macro_build (&offset_expr, "lui", LUI_FMT, AT,
12134 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
12135 tempreg, BFD_RELOC_MIPS_HIGHER);
12137 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
12138 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
12139 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
12140 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16,
12146 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
12147 BFD_RELOC_MIPS_HIGHEST);
12148 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
12149 tempreg, BFD_RELOC_MIPS_HIGHER);
12150 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
12151 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
12152 tempreg, BFD_RELOC_HI16_S);
12153 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
12155 macro_build (NULL, "daddu", "d,v,t",
12156 tempreg, tempreg, breg);
12157 macro_build (&offset_expr, s, fmt, op[0],
12158 BFD_RELOC_LO16, tempreg);
12161 if (mips_relax.sequence)
12168 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
12169 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
12171 relax_start (offset_expr.X_add_symbol);
12172 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_GPREL16,
12176 macro_build_lui (&offset_expr, tempreg);
12177 macro_build (&offset_expr, s, fmt, op[0],
12178 BFD_RELOC_LO16, tempreg);
12179 if (mips_relax.sequence)
12184 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
12185 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
12187 relax_start (offset_expr.X_add_symbol);
12188 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12189 tempreg, breg, mips_gp_register);
12190 macro_build (&offset_expr, s, fmt, op[0],
12191 BFD_RELOC_GPREL16, tempreg);
12194 macro_build_lui (&offset_expr, tempreg);
12195 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12196 tempreg, tempreg, breg);
12197 macro_build (&offset_expr, s, fmt, op[0],
12198 BFD_RELOC_LO16, tempreg);
12199 if (mips_relax.sequence)
12203 else if (!mips_big_got)
12205 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
12207 /* If this is a reference to an external symbol, we want
12208 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12210 <op> op[0],0($tempreg)
12212 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12214 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12215 <op> op[0],0($tempreg)
12217 For NewABI, we want
12218 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12219 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
12221 If there is a base register, we add it to $tempreg before
12222 the <op>. If there is a constant, we stick it in the
12223 <op> instruction. We don't handle constants larger than
12224 16 bits, because we have no way to load the upper 16 bits
12225 (actually, we could handle them for the subset of cases
12226 in which we are not using $at). */
12227 gas_assert (offset_expr.X_op == O_symbol);
12230 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12231 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
12233 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12234 tempreg, tempreg, breg);
12235 macro_build (&offset_expr, s, fmt, op[0],
12236 BFD_RELOC_MIPS_GOT_OFST, tempreg);
12239 expr1.X_add_number = offset_expr.X_add_number;
12240 offset_expr.X_add_number = 0;
12241 if (expr1.X_add_number < -0x8000
12242 || expr1.X_add_number >= 0x8000)
12243 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12244 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12245 lw_reloc_type, mips_gp_register);
12247 relax_start (offset_expr.X_add_symbol);
12249 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
12250 tempreg, BFD_RELOC_LO16);
12253 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12254 tempreg, tempreg, breg);
12255 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
12257 else if (mips_big_got && !HAVE_NEWABI)
12261 /* If this is a reference to an external symbol, we want
12262 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12263 addu $tempreg,$tempreg,$gp
12264 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12265 <op> op[0],0($tempreg)
12267 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12269 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12270 <op> op[0],0($tempreg)
12271 If there is a base register, we add it to $tempreg before
12272 the <op>. If there is a constant, we stick it in the
12273 <op> instruction. We don't handle constants larger than
12274 16 bits, because we have no way to load the upper 16 bits
12275 (actually, we could handle them for the subset of cases
12276 in which we are not using $at). */
12277 gas_assert (offset_expr.X_op == O_symbol);
12278 expr1.X_add_number = offset_expr.X_add_number;
12279 offset_expr.X_add_number = 0;
12280 if (expr1.X_add_number < -0x8000
12281 || expr1.X_add_number >= 0x8000)
12282 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12283 gpdelay = reg_needs_delay (mips_gp_register);
12284 relax_start (offset_expr.X_add_symbol);
12285 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
12286 BFD_RELOC_MIPS_GOT_HI16);
12287 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
12289 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12290 BFD_RELOC_MIPS_GOT_LO16, tempreg);
12293 macro_build (NULL, "nop", "");
12294 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12295 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12297 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
12298 tempreg, BFD_RELOC_LO16);
12302 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12303 tempreg, tempreg, breg);
12304 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
12306 else if (mips_big_got && HAVE_NEWABI)
12308 /* If this is a reference to an external symbol, we want
12309 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12310 add $tempreg,$tempreg,$gp
12311 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12312 <op> op[0],<ofst>($tempreg)
12313 Otherwise, for local symbols, we want:
12314 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12315 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
12316 gas_assert (offset_expr.X_op == O_symbol);
12317 expr1.X_add_number = offset_expr.X_add_number;
12318 offset_expr.X_add_number = 0;
12319 if (expr1.X_add_number < -0x8000
12320 || expr1.X_add_number >= 0x8000)
12321 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12322 relax_start (offset_expr.X_add_symbol);
12323 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
12324 BFD_RELOC_MIPS_GOT_HI16);
12325 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
12327 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12328 BFD_RELOC_MIPS_GOT_LO16, tempreg);
12330 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12331 tempreg, tempreg, breg);
12332 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
12335 offset_expr.X_add_number = expr1.X_add_number;
12336 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12337 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
12339 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12340 tempreg, tempreg, breg);
12341 macro_build (&offset_expr, s, fmt, op[0],
12342 BFD_RELOC_MIPS_GOT_OFST, tempreg);
12351 gas_assert (mips_opts.micromips);
12352 gas_assert (mips_opts.insn32);
12353 start_noreorder ();
12354 macro_build (NULL, "jr", "s", RA);
12355 expr1.X_add_number = op[0] << 2;
12356 macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16);
12361 gas_assert (mips_opts.micromips);
12362 gas_assert (mips_opts.insn32);
12363 macro_build (NULL, "jr", "s", op[0]);
12364 if (mips_opts.noreorder)
12365 macro_build (NULL, "nop", "");
12370 load_register (op[0], &imm_expr, 0);
12374 load_register (op[0], &imm_expr, 1);
12378 if (imm_expr.X_op == O_constant)
12381 load_register (AT, &imm_expr, 0);
12382 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
12387 gas_assert (imm_expr.X_op == O_absent
12388 && offset_expr.X_op == O_symbol
12389 && strcmp (segment_name (S_GET_SEGMENT
12390 (offset_expr.X_add_symbol)),
12392 && offset_expr.X_add_number == 0);
12393 macro_build (&offset_expr, "lwc1", "T,o(b)", op[0],
12394 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
12399 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12400 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12401 order 32 bits of the value and the low order 32 bits are either
12402 zero or in OFFSET_EXPR. */
12403 if (imm_expr.X_op == O_constant)
12405 if (GPR_SIZE == 64)
12406 load_register (op[0], &imm_expr, 1);
12411 if (target_big_endian)
12423 load_register (hreg, &imm_expr, 0);
12426 if (offset_expr.X_op == O_absent)
12427 move_register (lreg, 0);
12430 gas_assert (offset_expr.X_op == O_constant);
12431 load_register (lreg, &offset_expr, 0);
12437 gas_assert (imm_expr.X_op == O_absent);
12439 /* We know that sym is in the .rdata section. First we get the
12440 upper 16 bits of the address. */
12441 if (mips_pic == NO_PIC)
12443 macro_build_lui (&offset_expr, AT);
12448 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12449 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12453 /* Now we load the register(s). */
12454 if (GPR_SIZE == 64)
12457 macro_build (&offset_expr, "ld", "t,o(b)", op[0],
12458 BFD_RELOC_LO16, AT);
12463 macro_build (&offset_expr, "lw", "t,o(b)", op[0],
12464 BFD_RELOC_LO16, AT);
12467 /* FIXME: How in the world do we deal with the possible
12469 offset_expr.X_add_number += 4;
12470 macro_build (&offset_expr, "lw", "t,o(b)",
12471 op[0] + 1, BFD_RELOC_LO16, AT);
12477 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12478 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12479 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12480 the value and the low order 32 bits are either zero or in
12482 if (imm_expr.X_op == O_constant)
12485 load_register (AT, &imm_expr, FPR_SIZE == 64);
12486 if (FPR_SIZE == 64 && GPR_SIZE == 64)
12487 macro_build (NULL, "dmtc1", "t,S", AT, op[0]);
12490 if (ISA_HAS_MXHC1 (mips_opts.isa))
12491 macro_build (NULL, "mthc1", "t,G", AT, op[0]);
12492 else if (FPR_SIZE != 32)
12493 as_bad (_("Unable to generate `%s' compliant code "
12495 (FPR_SIZE == 64) ? "fp64" : "fpxx");
12497 macro_build (NULL, "mtc1", "t,G", AT, op[0] + 1);
12498 if (offset_expr.X_op == O_absent)
12499 macro_build (NULL, "mtc1", "t,G", 0, op[0]);
12502 gas_assert (offset_expr.X_op == O_constant);
12503 load_register (AT, &offset_expr, 0);
12504 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
12510 gas_assert (imm_expr.X_op == O_absent
12511 && offset_expr.X_op == O_symbol
12512 && offset_expr.X_add_number == 0);
12513 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
12514 if (strcmp (s, ".lit8") == 0)
12516 op[2] = mips_gp_register;
12517 offset_reloc[0] = BFD_RELOC_MIPS_LITERAL;
12518 offset_reloc[1] = BFD_RELOC_UNUSED;
12519 offset_reloc[2] = BFD_RELOC_UNUSED;
12523 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
12525 if (mips_pic != NO_PIC)
12526 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12527 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12530 /* FIXME: This won't work for a 64 bit address. */
12531 macro_build_lui (&offset_expr, AT);
12535 offset_reloc[0] = BFD_RELOC_LO16;
12536 offset_reloc[1] = BFD_RELOC_UNUSED;
12537 offset_reloc[2] = BFD_RELOC_UNUSED;
12544 * The MIPS assembler seems to check for X_add_number not
12545 * being double aligned and generating:
12546 * lui at,%hi(foo+1)
12548 * addiu at,at,%lo(foo+1)
12551 * But, the resulting address is the same after relocation so why
12552 * generate the extra instruction?
12554 /* Itbl support may require additional care here. */
12557 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
12566 gas_assert (!mips_opts.micromips);
12567 /* Itbl support may require additional care here. */
12570 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
12590 if (GPR_SIZE == 64)
12600 if (GPR_SIZE == 64)
12608 /* Even on a big endian machine $fn comes before $fn+1. We have
12609 to adjust when loading from memory. We set coproc if we must
12610 load $fn+1 first. */
12611 /* Itbl support may require additional care here. */
12612 if (!target_big_endian)
12616 if (small_offset_p (0, align, 16))
12619 if (!small_offset_p (4, align, 16))
12621 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg,
12622 -1, offset_reloc[0], offset_reloc[1],
12624 expr1.X_add_number = 0;
12628 offset_reloc[0] = BFD_RELOC_LO16;
12629 offset_reloc[1] = BFD_RELOC_UNUSED;
12630 offset_reloc[2] = BFD_RELOC_UNUSED;
12632 if (strcmp (s, "lw") == 0 && op[0] == breg)
12634 ep->X_add_number += 4;
12635 macro_build (ep, s, fmt, op[0] + 1, -1, offset_reloc[0],
12636 offset_reloc[1], offset_reloc[2], breg);
12637 ep->X_add_number -= 4;
12638 macro_build (ep, s, fmt, op[0], -1, offset_reloc[0],
12639 offset_reloc[1], offset_reloc[2], breg);
12643 macro_build (ep, s, fmt, coproc ? op[0] + 1 : op[0], -1,
12644 offset_reloc[0], offset_reloc[1], offset_reloc[2],
12646 ep->X_add_number += 4;
12647 macro_build (ep, s, fmt, coproc ? op[0] : op[0] + 1, -1,
12648 offset_reloc[0], offset_reloc[1], offset_reloc[2],
12654 if (offset_expr.X_op != O_symbol
12655 && offset_expr.X_op != O_constant)
12657 as_bad (_("expression too complex"));
12658 offset_expr.X_op = O_constant;
12661 if (HAVE_32BIT_ADDRESSES
12662 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
12666 sprintf_vma (value, offset_expr.X_add_number);
12667 as_bad (_("number (0x%s) larger than 32 bits"), value);
12670 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
12672 /* If this is a reference to a GP relative symbol, we want
12673 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12674 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
12675 If we have a base register, we use this
12677 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
12678 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
12679 If this is not a GP relative symbol, we want
12680 lui $at,<sym> (BFD_RELOC_HI16_S)
12681 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12682 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12683 If there is a base register, we add it to $at after the
12684 lui instruction. If there is a constant, we always use
12686 if (offset_expr.X_op == O_symbol
12687 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
12688 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
12690 relax_start (offset_expr.X_add_symbol);
12693 tempreg = mips_gp_register;
12697 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12698 AT, breg, mips_gp_register);
12703 /* Itbl support may require additional care here. */
12704 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12705 BFD_RELOC_GPREL16, tempreg);
12706 offset_expr.X_add_number += 4;
12708 /* Set mips_optimize to 2 to avoid inserting an
12710 hold_mips_optimize = mips_optimize;
12712 /* Itbl support may require additional care here. */
12713 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12714 BFD_RELOC_GPREL16, tempreg);
12715 mips_optimize = hold_mips_optimize;
12719 offset_expr.X_add_number -= 4;
12722 if (offset_high_part (offset_expr.X_add_number, 16)
12723 != offset_high_part (offset_expr.X_add_number + 4, 16))
12725 load_address (AT, &offset_expr, &used_at);
12726 offset_expr.X_op = O_constant;
12727 offset_expr.X_add_number = 0;
12730 macro_build_lui (&offset_expr, AT);
12732 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12733 /* Itbl support may require additional care here. */
12734 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12735 BFD_RELOC_LO16, AT);
12736 /* FIXME: How do we handle overflow here? */
12737 offset_expr.X_add_number += 4;
12738 /* Itbl support may require additional care here. */
12739 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12740 BFD_RELOC_LO16, AT);
12741 if (mips_relax.sequence)
12744 else if (!mips_big_got)
12746 /* If this is a reference to an external symbol, we want
12747 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12750 <op> op[0]+1,4($at)
12752 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12754 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12755 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12756 If there is a base register we add it to $at before the
12757 lwc1 instructions. If there is a constant we include it
12758 in the lwc1 instructions. */
12760 expr1.X_add_number = offset_expr.X_add_number;
12761 if (expr1.X_add_number < -0x8000
12762 || expr1.X_add_number >= 0x8000 - 4)
12763 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12764 load_got_offset (AT, &offset_expr);
12767 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12769 /* Set mips_optimize to 2 to avoid inserting an undesired
12771 hold_mips_optimize = mips_optimize;
12774 /* Itbl support may require additional care here. */
12775 relax_start (offset_expr.X_add_symbol);
12776 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
12777 BFD_RELOC_LO16, AT);
12778 expr1.X_add_number += 4;
12779 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
12780 BFD_RELOC_LO16, AT);
12782 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12783 BFD_RELOC_LO16, AT);
12784 offset_expr.X_add_number += 4;
12785 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12786 BFD_RELOC_LO16, AT);
12789 mips_optimize = hold_mips_optimize;
12791 else if (mips_big_got)
12795 /* If this is a reference to an external symbol, we want
12796 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12798 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
12801 <op> op[0]+1,4($at)
12803 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12805 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12806 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12807 If there is a base register we add it to $at before the
12808 lwc1 instructions. If there is a constant we include it
12809 in the lwc1 instructions. */
12811 expr1.X_add_number = offset_expr.X_add_number;
12812 offset_expr.X_add_number = 0;
12813 if (expr1.X_add_number < -0x8000
12814 || expr1.X_add_number >= 0x8000 - 4)
12815 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12816 gpdelay = reg_needs_delay (mips_gp_register);
12817 relax_start (offset_expr.X_add_symbol);
12818 macro_build (&offset_expr, "lui", LUI_FMT,
12819 AT, BFD_RELOC_MIPS_GOT_HI16);
12820 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12821 AT, AT, mips_gp_register);
12822 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
12823 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
12826 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12827 /* Itbl support may require additional care here. */
12828 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
12829 BFD_RELOC_LO16, AT);
12830 expr1.X_add_number += 4;
12832 /* Set mips_optimize to 2 to avoid inserting an undesired
12834 hold_mips_optimize = mips_optimize;
12836 /* Itbl support may require additional care here. */
12837 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
12838 BFD_RELOC_LO16, AT);
12839 mips_optimize = hold_mips_optimize;
12840 expr1.X_add_number -= 4;
12843 offset_expr.X_add_number = expr1.X_add_number;
12845 macro_build (NULL, "nop", "");
12846 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12847 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12850 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12851 /* Itbl support may require additional care here. */
12852 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12853 BFD_RELOC_LO16, AT);
12854 offset_expr.X_add_number += 4;
12856 /* Set mips_optimize to 2 to avoid inserting an undesired
12858 hold_mips_optimize = mips_optimize;
12860 /* Itbl support may require additional care here. */
12861 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12862 BFD_RELOC_LO16, AT);
12863 mips_optimize = hold_mips_optimize;
12877 gas_assert (!mips_opts.micromips);
12882 /* New code added to support COPZ instructions.
12883 This code builds table entries out of the macros in mip_opcodes.
12884 R4000 uses interlocks to handle coproc delays.
12885 Other chips (like the R3000) require nops to be inserted for delays.
12887 FIXME: Currently, we require that the user handle delays.
12888 In order to fill delay slots for non-interlocked chips,
12889 we must have a way to specify delays based on the coprocessor.
12890 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
12891 What are the side-effects of the cop instruction?
12892 What cache support might we have and what are its effects?
12893 Both coprocessor & memory require delays. how long???
12894 What registers are read/set/modified?
12896 If an itbl is provided to interpret cop instructions,
12897 this knowledge can be encoded in the itbl spec. */
12911 gas_assert (!mips_opts.micromips);
12912 /* For now we just do C (same as Cz). The parameter will be
12913 stored in insn_opcode by mips_ip. */
12914 macro_build (NULL, s, "C", (int) ip->insn_opcode);
12918 move_register (op[0], op[1]);
12922 gas_assert (mips_opts.micromips);
12923 gas_assert (mips_opts.insn32);
12924 move_register (micromips_to_32_reg_h_map1[op[0]],
12925 micromips_to_32_reg_m_map[op[1]]);
12926 move_register (micromips_to_32_reg_h_map2[op[0]],
12927 micromips_to_32_reg_n_map[op[2]]);
12932 /* Fall through. */
12934 if (mips_opts.arch == CPU_R5900)
12935 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", op[0], op[1],
12939 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", op[1], op[2]);
12940 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12946 /* Fall through. */
12948 /* The MIPS assembler some times generates shifts and adds. I'm
12949 not trying to be that fancy. GCC should do this for us
12952 load_register (AT, &imm_expr, dbl);
12953 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", op[1], AT);
12954 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12959 /* Fall through. */
12966 /* Fall through. */
12969 start_noreorder ();
12972 load_register (AT, &imm_expr, dbl);
12973 macro_build (NULL, dbl ? "dmult" : "mult", "s,t",
12974 op[1], imm ? AT : op[2]);
12975 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12976 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, op[0], op[0], 31);
12977 macro_build (NULL, "mfhi", MFHL_FMT, AT);
12979 macro_build (NULL, "tne", TRAP_FMT, op[0], AT, 6);
12982 if (mips_opts.micromips)
12983 micromips_label_expr (&label_expr);
12985 label_expr.X_add_number = 8;
12986 macro_build (&label_expr, "beq", "s,t,p", op[0], AT);
12987 macro_build (NULL, "nop", "");
12988 macro_build (NULL, "break", BRK_FMT, 6);
12989 if (mips_opts.micromips)
12990 micromips_add_label ();
12993 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12998 /* Fall through. */
13005 /* Fall through. */
13008 start_noreorder ();
13011 load_register (AT, &imm_expr, dbl);
13012 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
13013 op[1], imm ? AT : op[2]);
13014 macro_build (NULL, "mfhi", MFHL_FMT, AT);
13015 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
13017 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
13020 if (mips_opts.micromips)
13021 micromips_label_expr (&label_expr);
13023 label_expr.X_add_number = 8;
13024 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
13025 macro_build (NULL, "nop", "");
13026 macro_build (NULL, "break", BRK_FMT, 6);
13027 if (mips_opts.micromips)
13028 micromips_add_label ();
13034 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
13036 if (op[0] == op[1])
13043 macro_build (NULL, "dnegu", "d,w", tempreg, op[2]);
13044 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], tempreg);
13048 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
13049 macro_build (NULL, "dsrlv", "d,t,s", AT, op[1], AT);
13050 macro_build (NULL, "dsllv", "d,t,s", op[0], op[1], op[2]);
13051 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13055 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
13057 if (op[0] == op[1])
13064 macro_build (NULL, "negu", "d,w", tempreg, op[2]);
13065 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], tempreg);
13069 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
13070 macro_build (NULL, "srlv", "d,t,s", AT, op[1], AT);
13071 macro_build (NULL, "sllv", "d,t,s", op[0], op[1], op[2]);
13072 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13081 rot = imm_expr.X_add_number & 0x3f;
13082 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
13084 rot = (64 - rot) & 0x3f;
13086 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
13088 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
13093 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
13096 l = (rot < 0x20) ? "dsll" : "dsll32";
13097 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
13100 macro_build (NULL, l, SHFT_FMT, AT, op[1], rot);
13101 macro_build (NULL, rr, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
13102 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13110 rot = imm_expr.X_add_number & 0x1f;
13111 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
13113 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1],
13114 (32 - rot) & 0x1f);
13119 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
13123 macro_build (NULL, "sll", SHFT_FMT, AT, op[1], rot);
13124 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
13125 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13130 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
13132 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], op[2]);
13136 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
13137 macro_build (NULL, "dsllv", "d,t,s", AT, op[1], AT);
13138 macro_build (NULL, "dsrlv", "d,t,s", op[0], op[1], op[2]);
13139 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13143 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
13145 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], op[2]);
13149 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
13150 macro_build (NULL, "sllv", "d,t,s", AT, op[1], AT);
13151 macro_build (NULL, "srlv", "d,t,s", op[0], op[1], op[2]);
13152 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13161 rot = imm_expr.X_add_number & 0x3f;
13162 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
13165 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
13167 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
13172 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
13175 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
13176 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
13179 macro_build (NULL, rr, SHFT_FMT, AT, op[1], rot);
13180 macro_build (NULL, l, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
13181 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13189 rot = imm_expr.X_add_number & 0x1f;
13190 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
13192 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], rot);
13197 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
13201 macro_build (NULL, "srl", SHFT_FMT, AT, op[1], rot);
13202 macro_build (NULL, "sll", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
13203 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13209 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[2], BFD_RELOC_LO16);
13210 else if (op[2] == 0)
13211 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13214 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
13215 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
13220 if (imm_expr.X_add_number == 0)
13222 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13227 as_warn (_("instruction %s: result is always false"),
13228 ip->insn_mo->name);
13229 move_register (op[0], 0);
13232 if (CPU_HAS_SEQ (mips_opts.arch)
13233 && -512 <= imm_expr.X_add_number
13234 && imm_expr.X_add_number < 512)
13236 macro_build (NULL, "seqi", "t,r,+Q", op[0], op[1],
13237 (int) imm_expr.X_add_number);
13240 if (imm_expr.X_add_number >= 0
13241 && imm_expr.X_add_number < 0x10000)
13242 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], BFD_RELOC_LO16);
13243 else if (imm_expr.X_add_number > -0x8000
13244 && imm_expr.X_add_number < 0)
13246 imm_expr.X_add_number = -imm_expr.X_add_number;
13247 macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu",
13248 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13250 else if (CPU_HAS_SEQ (mips_opts.arch))
13253 load_register (AT, &imm_expr, GPR_SIZE == 64);
13254 macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT);
13259 load_register (AT, &imm_expr, GPR_SIZE == 64);
13260 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
13263 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
13266 case M_SGE: /* X >= Y <==> not (X < Y) */
13272 macro_build (NULL, s, "d,v,t", op[0], op[1], op[2]);
13273 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
13276 case M_SGE_I: /* X >= I <==> not (X < I) */
13278 if (imm_expr.X_add_number >= -0x8000
13279 && imm_expr.X_add_number < 0x8000)
13280 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
13281 op[0], op[1], BFD_RELOC_LO16);
13284 load_register (AT, &imm_expr, GPR_SIZE == 64);
13285 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
13289 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
13292 case M_SGT: /* X > Y <==> Y < X */
13298 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
13301 case M_SGT_I: /* X > I <==> I < X */
13308 load_register (AT, &imm_expr, GPR_SIZE == 64);
13309 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
13312 case M_SLE: /* X <= Y <==> Y >= X <==> not (Y < X) */
13318 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
13319 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
13322 case M_SLE_I: /* X <= I <==> I >= X <==> not (I < X) */
13329 load_register (AT, &imm_expr, GPR_SIZE == 64);
13330 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
13331 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
13335 if (imm_expr.X_add_number >= -0x8000
13336 && imm_expr.X_add_number < 0x8000)
13338 macro_build (&imm_expr, "slti", "t,r,j", op[0], op[1],
13343 load_register (AT, &imm_expr, GPR_SIZE == 64);
13344 macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT);
13348 if (imm_expr.X_add_number >= -0x8000
13349 && imm_expr.X_add_number < 0x8000)
13351 macro_build (&imm_expr, "sltiu", "t,r,j", op[0], op[1],
13356 load_register (AT, &imm_expr, GPR_SIZE == 64);
13357 macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT);
13362 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[2]);
13363 else if (op[2] == 0)
13364 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
13367 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
13368 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
13373 if (imm_expr.X_add_number == 0)
13375 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
13380 as_warn (_("instruction %s: result is always true"),
13381 ip->insn_mo->name);
13382 macro_build (&expr1, GPR_SIZE == 32 ? "addiu" : "daddiu", "t,r,j",
13383 op[0], 0, BFD_RELOC_LO16);
13386 if (CPU_HAS_SEQ (mips_opts.arch)
13387 && -512 <= imm_expr.X_add_number
13388 && imm_expr.X_add_number < 512)
13390 macro_build (NULL, "snei", "t,r,+Q", op[0], op[1],
13391 (int) imm_expr.X_add_number);
13394 if (imm_expr.X_add_number >= 0
13395 && imm_expr.X_add_number < 0x10000)
13397 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1],
13400 else if (imm_expr.X_add_number > -0x8000
13401 && imm_expr.X_add_number < 0)
13403 imm_expr.X_add_number = -imm_expr.X_add_number;
13404 macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu",
13405 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13407 else if (CPU_HAS_SEQ (mips_opts.arch))
13410 load_register (AT, &imm_expr, GPR_SIZE == 64);
13411 macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT);
13416 load_register (AT, &imm_expr, GPR_SIZE == 64);
13417 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
13420 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
13435 if (!mips_opts.micromips)
13437 if (imm_expr.X_add_number > -0x200
13438 && imm_expr.X_add_number <= 0x200)
13440 macro_build (NULL, s, "t,r,.", op[0], op[1],
13441 (int) -imm_expr.X_add_number);
13450 if (imm_expr.X_add_number > -0x8000
13451 && imm_expr.X_add_number <= 0x8000)
13453 imm_expr.X_add_number = -imm_expr.X_add_number;
13454 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13459 load_register (AT, &imm_expr, dbl);
13460 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
13482 load_register (AT, &imm_expr, GPR_SIZE == 64);
13483 macro_build (NULL, s, "s,t", op[0], AT);
13488 gas_assert (!mips_opts.micromips);
13489 gas_assert (mips_opts.isa == ISA_MIPS1);
13493 * Is the double cfc1 instruction a bug in the mips assembler;
13494 * or is there a reason for it?
13496 start_noreorder ();
13497 macro_build (NULL, "cfc1", "t,G", op[2], RA);
13498 macro_build (NULL, "cfc1", "t,G", op[2], RA);
13499 macro_build (NULL, "nop", "");
13500 expr1.X_add_number = 3;
13501 macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16);
13502 expr1.X_add_number = 2;
13503 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
13504 macro_build (NULL, "ctc1", "t,G", AT, RA);
13505 macro_build (NULL, "nop", "");
13506 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
13508 macro_build (NULL, "ctc1", "t,G", op[2], RA);
13509 macro_build (NULL, "nop", "");
13526 offbits = (mips_opts.micromips ? 12 : 16);
13532 offbits = (mips_opts.micromips ? 12 : 16);
13544 offbits = (mips_opts.micromips ? 12 : 16);
13551 offbits = (mips_opts.micromips ? 12 : 16);
13557 large_offset = !small_offset_p (off, align, offbits);
13559 expr1.X_add_number = 0;
13564 if (small_offset_p (0, align, 16))
13565 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1,
13566 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
13569 load_address (tempreg, ep, &used_at);
13571 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
13572 tempreg, tempreg, breg);
13574 offset_reloc[0] = BFD_RELOC_LO16;
13575 offset_reloc[1] = BFD_RELOC_UNUSED;
13576 offset_reloc[2] = BFD_RELOC_UNUSED;
13581 else if (!ust && op[0] == breg)
13592 if (!target_big_endian)
13593 ep->X_add_number += off;
13595 macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg);
13597 macro_build (ep, s, "t,o(b)", tempreg, -1,
13598 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13600 if (!target_big_endian)
13601 ep->X_add_number -= off;
13603 ep->X_add_number += off;
13605 macro_build (NULL, s2, "t,~(b)",
13606 tempreg, (int) ep->X_add_number, breg);
13608 macro_build (ep, s2, "t,o(b)", tempreg, -1,
13609 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13611 /* If necessary, move the result in tempreg to the final destination. */
13612 if (!ust && op[0] != tempreg)
13614 /* Protect second load's delay slot. */
13616 move_register (op[0], tempreg);
13622 if (target_big_endian == ust)
13623 ep->X_add_number += off;
13624 tempreg = ust || large_offset ? op[0] : AT;
13625 macro_build (ep, s, "t,o(b)", tempreg, -1,
13626 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13628 /* For halfword transfers we need a temporary register to shuffle
13629 bytes. Unfortunately for M_USH_A we have none available before
13630 the next store as AT holds the base address. We deal with this
13631 case by clobbering TREG and then restoring it as with ULH. */
13632 tempreg = ust == large_offset ? op[0] : AT;
13634 macro_build (NULL, "srl", SHFT_FMT, tempreg, op[0], 8);
13636 if (target_big_endian == ust)
13637 ep->X_add_number -= off;
13639 ep->X_add_number += off;
13640 macro_build (ep, s2, "t,o(b)", tempreg, -1,
13641 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13643 /* For M_USH_A re-retrieve the LSB. */
13644 if (ust && large_offset)
13646 if (target_big_endian)
13647 ep->X_add_number += off;
13649 ep->X_add_number -= off;
13650 macro_build (&expr1, "lbu", "t,o(b)", AT, -1,
13651 offset_reloc[0], offset_reloc[1], offset_reloc[2], AT);
13653 /* For ULH and M_USH_A OR the LSB in. */
13654 if (!ust || large_offset)
13656 tempreg = !large_offset ? AT : op[0];
13657 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
13658 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13663 /* FIXME: Check if this is one of the itbl macros, since they
13664 are added dynamically. */
13665 as_bad (_("macro %s not implemented yet"), ip->insn_mo->name);
13668 if (!mips_opts.at && used_at)
13669 as_bad (_("macro used $at after \".set noat\""));
13672 /* Implement macros in mips16 mode. */
13675 mips16_macro (struct mips_cl_insn *ip)
13677 const struct mips_operand_array *operands;
13682 const char *s, *s2, *s3;
13683 unsigned int op[MAX_OPERANDS];
13686 mask = ip->insn_mo->mask;
13688 operands = insn_operands (ip);
13689 for (i = 0; i < MAX_OPERANDS; i++)
13690 if (operands->operand[i])
13691 op[i] = insn_extract_operand (ip, operands->operand[i]);
13695 expr1.X_op = O_constant;
13696 expr1.X_op_symbol = NULL;
13697 expr1.X_add_symbol = NULL;
13698 expr1.X_add_number = 1;
13709 /* Fall through. */
13715 /* Fall through. */
13719 start_noreorder ();
13720 macro_build (NULL, dbl ? "ddiv" : "div", ".,x,y", op[1], op[2]);
13721 expr1.X_add_number = 2;
13722 macro_build (&expr1, "bnez", "x,p", op[2]);
13723 macro_build (NULL, "break", "6", 7);
13725 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
13726 since that causes an overflow. We should do that as well,
13727 but I don't see how to do the comparisons without a temporary
13730 macro_build (NULL, s, "x", op[0]);
13749 start_noreorder ();
13750 macro_build (NULL, s, ".,x,y", op[1], op[2]);
13751 expr1.X_add_number = 2;
13752 macro_build (&expr1, "bnez", "x,p", op[2]);
13753 macro_build (NULL, "break", "6", 7);
13755 macro_build (NULL, s2, "x", op[0]);
13760 /* Fall through. */
13762 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", op[1], op[2]);
13763 macro_build (NULL, "mflo", "x", op[0]);
13771 imm_expr.X_add_number = -imm_expr.X_add_number;
13772 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,F", op[0], op[1]);
13776 imm_expr.X_add_number = -imm_expr.X_add_number;
13777 macro_build (&imm_expr, "addiu", "x,k", op[0]);
13781 imm_expr.X_add_number = -imm_expr.X_add_number;
13782 macro_build (&imm_expr, "daddiu", "y,j", op[0]);
13804 goto do_reverse_branch;
13808 goto do_reverse_branch;
13820 goto do_reverse_branch;
13831 macro_build (NULL, s, "x,y", op[0], op[1]);
13832 macro_build (&offset_expr, s2, "p");
13859 goto do_addone_branch_i;
13864 goto do_addone_branch_i;
13879 goto do_addone_branch_i;
13885 do_addone_branch_i:
13886 ++imm_expr.X_add_number;
13889 macro_build (&imm_expr, s, s3, op[0]);
13890 macro_build (&offset_expr, s2, "p");
13894 expr1.X_add_number = 0;
13895 macro_build (&expr1, "slti", "x,8", op[1]);
13896 if (op[0] != op[1])
13897 macro_build (NULL, "move", "y,X", op[0], mips16_to_32_reg_map[op[1]]);
13898 expr1.X_add_number = 2;
13899 macro_build (&expr1, "bteqz", "p");
13900 macro_build (NULL, "neg", "x,w", op[0], op[0]);
13905 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
13906 opcode bits in *OPCODE_EXTRA. */
13908 static struct mips_opcode *
13909 mips_lookup_insn (struct hash_control *hash, const char *start,
13910 ssize_t length, unsigned int *opcode_extra)
13912 char *name, *dot, *p;
13913 unsigned int mask, suffix;
13915 struct mips_opcode *insn;
13917 /* Make a copy of the instruction so that we can fiddle with it. */
13918 name = xstrndup (start, length);
13920 /* Look up the instruction as-is. */
13921 insn = (struct mips_opcode *) hash_find (hash, name);
13925 dot = strchr (name, '.');
13928 /* Try to interpret the text after the dot as a VU0 channel suffix. */
13929 p = mips_parse_vu0_channels (dot + 1, &mask);
13930 if (*p == 0 && mask != 0)
13933 insn = (struct mips_opcode *) hash_find (hash, name);
13935 if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0)
13937 *opcode_extra |= mask << mips_vu0_channel_mask.lsb;
13943 if (mips_opts.micromips)
13945 /* See if there's an instruction size override suffix,
13946 either `16' or `32', at the end of the mnemonic proper,
13947 that defines the operation, i.e. before the first `.'
13948 character if any. Strip it and retry. */
13949 opend = dot != NULL ? dot - name : length;
13950 if (opend >= 3 && name[opend - 2] == '1' && name[opend - 1] == '6')
13952 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
13958 memcpy (name + opend - 2, name + opend, length - opend + 1);
13959 insn = (struct mips_opcode *) hash_find (hash, name);
13962 forced_insn_length = suffix;
13974 /* Assemble an instruction into its binary format. If the instruction
13975 is a macro, set imm_expr and offset_expr to the values associated
13976 with "I" and "A" operands respectively. Otherwise store the value
13977 of the relocatable field (if any) in offset_expr. In both cases
13978 set offset_reloc to the relocation operators applied to offset_expr. */
13981 mips_ip (char *str, struct mips_cl_insn *insn)
13983 const struct mips_opcode *first, *past;
13984 struct hash_control *hash;
13987 struct mips_operand_token *tokens;
13988 unsigned int opcode_extra;
13990 if (mips_opts.micromips)
13992 hash = micromips_op_hash;
13993 past = µmips_opcodes[bfd_micromips_num_opcodes];
13998 past = &mips_opcodes[NUMOPCODES];
14000 forced_insn_length = 0;
14003 /* We first try to match an instruction up to a space or to the end. */
14004 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
14007 first = mips_lookup_insn (hash, str, end, &opcode_extra);
14010 set_insn_error (0, _("unrecognized opcode"));
14014 if (strcmp (first->name, "li.s") == 0)
14016 else if (strcmp (first->name, "li.d") == 0)
14020 tokens = mips_parse_arguments (str + end, format);
14024 if (!match_insns (insn, first, past, tokens, opcode_extra, FALSE)
14025 && !match_insns (insn, first, past, tokens, opcode_extra, TRUE))
14026 set_insn_error (0, _("invalid operands"));
14028 obstack_free (&mips_operand_tokens, tokens);
14031 /* As for mips_ip, but used when assembling MIPS16 code.
14032 Also set forced_insn_length to the resulting instruction size in
14033 bytes if the user explicitly requested a small or extended instruction. */
14036 mips16_ip (char *str, struct mips_cl_insn *insn)
14039 struct mips_opcode *first;
14040 struct mips_operand_token *tokens;
14043 for (s = str; *s != '\0' && *s != '.' && *s != ' '; ++s)
14065 else if (*s == 'e')
14072 else if (*s++ == ' ')
14074 set_insn_error (0, _("unrecognized opcode"));
14077 forced_insn_length = l;
14080 first = (struct mips_opcode *) hash_find (mips16_op_hash, str);
14085 set_insn_error (0, _("unrecognized opcode"));
14089 tokens = mips_parse_arguments (s, 0);
14093 if (!match_mips16_insns (insn, first, tokens))
14094 set_insn_error (0, _("invalid operands"));
14096 obstack_free (&mips_operand_tokens, tokens);
14099 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14100 NBITS is the number of significant bits in VAL. */
14102 static unsigned long
14103 mips16_immed_extend (offsetT val, unsigned int nbits)
14108 val &= (1U << nbits) - 1;
14109 if (nbits == 16 || nbits == 9)
14111 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
14114 else if (nbits == 15)
14116 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
14119 else if (nbits == 6)
14121 extval = ((val & 0x1f) << 6) | (val & 0x20);
14124 return (extval << 16) | val;
14127 /* Like decode_mips16_operand, but require the operand to be defined and
14128 require it to be an integer. */
14130 static const struct mips_int_operand *
14131 mips16_immed_operand (int type, bfd_boolean extended_p)
14133 const struct mips_operand *operand;
14135 operand = decode_mips16_operand (type, extended_p);
14136 if (!operand || (operand->type != OP_INT && operand->type != OP_PCREL))
14138 return (const struct mips_int_operand *) operand;
14141 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
14144 mips16_immed_in_range_p (const struct mips_int_operand *operand,
14145 bfd_reloc_code_real_type reloc, offsetT sval)
14147 int min_val, max_val;
14149 min_val = mips_int_operand_min (operand);
14150 max_val = mips_int_operand_max (operand);
14151 if (reloc != BFD_RELOC_UNUSED)
14154 sval = SEXT_16BIT (sval);
14159 return (sval >= min_val
14161 && (sval & ((1 << operand->shift) - 1)) == 0);
14164 /* Install immediate value VAL into MIPS16 instruction *INSN,
14165 extending it if necessary. The instruction in *INSN may
14166 already be extended.
14168 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14169 if none. In the former case, VAL is a 16-bit number with no
14170 defined signedness.
14172 TYPE is the type of the immediate field. USER_INSN_LENGTH
14173 is the length that the user requested, or 0 if none. */
14176 mips16_immed (const char *file, unsigned int line, int type,
14177 bfd_reloc_code_real_type reloc, offsetT val,
14178 unsigned int user_insn_length, unsigned long *insn)
14180 const struct mips_int_operand *operand;
14181 unsigned int uval, length;
14183 operand = mips16_immed_operand (type, FALSE);
14184 if (!mips16_immed_in_range_p (operand, reloc, val))
14186 /* We need an extended instruction. */
14187 if (user_insn_length == 2)
14188 as_bad_where (file, line, _("invalid unextended operand value"));
14190 *insn |= MIPS16_EXTEND;
14192 else if (user_insn_length == 4)
14194 /* The operand doesn't force an unextended instruction to be extended.
14195 Warn if the user wanted an extended instruction anyway. */
14196 *insn |= MIPS16_EXTEND;
14197 as_warn_where (file, line,
14198 _("extended operand requested but not required"));
14201 length = mips16_opcode_length (*insn);
14204 operand = mips16_immed_operand (type, TRUE);
14205 if (!mips16_immed_in_range_p (operand, reloc, val))
14206 as_bad_where (file, line,
14207 _("operand value out of range for instruction"));
14209 uval = ((unsigned int) val >> operand->shift) - operand->bias;
14210 if (length == 2 || operand->root.lsb != 0)
14211 *insn = mips_insert_operand (&operand->root, *insn, uval);
14213 *insn |= mips16_immed_extend (uval, operand->root.size);
14216 struct percent_op_match
14219 bfd_reloc_code_real_type reloc;
14222 static const struct percent_op_match mips_percent_op[] =
14224 {"%lo", BFD_RELOC_LO16},
14225 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
14226 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
14227 {"%call16", BFD_RELOC_MIPS_CALL16},
14228 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
14229 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
14230 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
14231 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
14232 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
14233 {"%got", BFD_RELOC_MIPS_GOT16},
14234 {"%gp_rel", BFD_RELOC_GPREL16},
14235 {"%gprel", BFD_RELOC_GPREL16},
14236 {"%half", BFD_RELOC_16},
14237 {"%highest", BFD_RELOC_MIPS_HIGHEST},
14238 {"%higher", BFD_RELOC_MIPS_HIGHER},
14239 {"%neg", BFD_RELOC_MIPS_SUB},
14240 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
14241 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
14242 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
14243 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
14244 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
14245 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
14246 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
14247 {"%hi", BFD_RELOC_HI16_S},
14248 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL},
14249 {"%pcrel_lo", BFD_RELOC_LO16_PCREL}
14252 static const struct percent_op_match mips16_percent_op[] =
14254 {"%lo", BFD_RELOC_MIPS16_LO16},
14255 {"%gp_rel", BFD_RELOC_MIPS16_GPREL},
14256 {"%gprel", BFD_RELOC_MIPS16_GPREL},
14257 {"%got", BFD_RELOC_MIPS16_GOT16},
14258 {"%call16", BFD_RELOC_MIPS16_CALL16},
14259 {"%hi", BFD_RELOC_MIPS16_HI16_S},
14260 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
14261 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
14262 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
14263 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
14264 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
14265 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
14266 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
14270 /* Return true if *STR points to a relocation operator. When returning true,
14271 move *STR over the operator and store its relocation code in *RELOC.
14272 Leave both *STR and *RELOC alone when returning false. */
14275 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
14277 const struct percent_op_match *percent_op;
14280 if (mips_opts.mips16)
14282 percent_op = mips16_percent_op;
14283 limit = ARRAY_SIZE (mips16_percent_op);
14287 percent_op = mips_percent_op;
14288 limit = ARRAY_SIZE (mips_percent_op);
14291 for (i = 0; i < limit; i++)
14292 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
14294 int len = strlen (percent_op[i].str);
14296 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
14299 *str += strlen (percent_op[i].str);
14300 *reloc = percent_op[i].reloc;
14302 /* Check whether the output BFD supports this relocation.
14303 If not, issue an error and fall back on something safe. */
14304 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
14306 as_bad (_("relocation %s isn't supported by the current ABI"),
14307 percent_op[i].str);
14308 *reloc = BFD_RELOC_UNUSED;
14316 /* Parse string STR as a 16-bit relocatable operand. Store the
14317 expression in *EP and the relocations in the array starting
14318 at RELOC. Return the number of relocation operators used.
14320 On exit, EXPR_END points to the first character after the expression. */
14323 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
14326 bfd_reloc_code_real_type reversed_reloc[3];
14327 size_t reloc_index, i;
14328 int crux_depth, str_depth;
14331 /* Search for the start of the main expression, recoding relocations
14332 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14333 of the main expression and with CRUX_DEPTH containing the number
14334 of open brackets at that point. */
14341 crux_depth = str_depth;
14343 /* Skip over whitespace and brackets, keeping count of the number
14345 while (*str == ' ' || *str == '\t' || *str == '(')
14350 && reloc_index < (HAVE_NEWABI ? 3 : 1)
14351 && parse_relocation (&str, &reversed_reloc[reloc_index]));
14353 my_getExpression (ep, crux);
14356 /* Match every open bracket. */
14357 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
14361 if (crux_depth > 0)
14362 as_bad (_("unclosed '('"));
14366 if (reloc_index != 0)
14368 prev_reloc_op_frag = frag_now;
14369 for (i = 0; i < reloc_index; i++)
14370 reloc[i] = reversed_reloc[reloc_index - 1 - i];
14373 return reloc_index;
14377 my_getExpression (expressionS *ep, char *str)
14381 save_in = input_line_pointer;
14382 input_line_pointer = str;
14384 expr_end = input_line_pointer;
14385 input_line_pointer = save_in;
14389 md_atof (int type, char *litP, int *sizeP)
14391 return ieee_md_atof (type, litP, sizeP, target_big_endian);
14395 md_number_to_chars (char *buf, valueT val, int n)
14397 if (target_big_endian)
14398 number_to_chars_bigendian (buf, val, n);
14400 number_to_chars_littleendian (buf, val, n);
14403 static int support_64bit_objects(void)
14405 const char **list, **l;
14408 list = bfd_target_list ();
14409 for (l = list; *l != NULL; l++)
14410 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
14411 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
14413 yes = (*l != NULL);
14418 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14419 NEW_VALUE. Warn if another value was already specified. Note:
14420 we have to defer parsing the -march and -mtune arguments in order
14421 to handle 'from-abi' correctly, since the ABI might be specified
14422 in a later argument. */
14425 mips_set_option_string (const char **string_ptr, const char *new_value)
14427 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
14428 as_warn (_("a different %s was already specified, is now %s"),
14429 string_ptr == &mips_arch_string ? "-march" : "-mtune",
14432 *string_ptr = new_value;
14436 md_parse_option (int c, const char *arg)
14440 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
14441 if (c == mips_ases[i].option_on || c == mips_ases[i].option_off)
14443 file_ase_explicit |= mips_set_ase (&mips_ases[i], &file_mips_opts,
14444 c == mips_ases[i].option_on);
14450 case OPTION_CONSTRUCT_FLOATS:
14451 mips_disable_float_construction = 0;
14454 case OPTION_NO_CONSTRUCT_FLOATS:
14455 mips_disable_float_construction = 1;
14467 target_big_endian = 1;
14471 target_big_endian = 0;
14477 else if (arg[0] == '0')
14479 else if (arg[0] == '1')
14489 mips_debug = atoi (arg);
14493 file_mips_opts.isa = ISA_MIPS1;
14497 file_mips_opts.isa = ISA_MIPS2;
14501 file_mips_opts.isa = ISA_MIPS3;
14505 file_mips_opts.isa = ISA_MIPS4;
14509 file_mips_opts.isa = ISA_MIPS5;
14512 case OPTION_MIPS32:
14513 file_mips_opts.isa = ISA_MIPS32;
14516 case OPTION_MIPS32R2:
14517 file_mips_opts.isa = ISA_MIPS32R2;
14520 case OPTION_MIPS32R3:
14521 file_mips_opts.isa = ISA_MIPS32R3;
14524 case OPTION_MIPS32R5:
14525 file_mips_opts.isa = ISA_MIPS32R5;
14528 case OPTION_MIPS32R6:
14529 file_mips_opts.isa = ISA_MIPS32R6;
14532 case OPTION_MIPS64R2:
14533 file_mips_opts.isa = ISA_MIPS64R2;
14536 case OPTION_MIPS64R3:
14537 file_mips_opts.isa = ISA_MIPS64R3;
14540 case OPTION_MIPS64R5:
14541 file_mips_opts.isa = ISA_MIPS64R5;
14544 case OPTION_MIPS64R6:
14545 file_mips_opts.isa = ISA_MIPS64R6;
14548 case OPTION_MIPS64:
14549 file_mips_opts.isa = ISA_MIPS64;
14553 mips_set_option_string (&mips_tune_string, arg);
14557 mips_set_option_string (&mips_arch_string, arg);
14561 mips_set_option_string (&mips_arch_string, "4650");
14562 mips_set_option_string (&mips_tune_string, "4650");
14565 case OPTION_NO_M4650:
14569 mips_set_option_string (&mips_arch_string, "4010");
14570 mips_set_option_string (&mips_tune_string, "4010");
14573 case OPTION_NO_M4010:
14577 mips_set_option_string (&mips_arch_string, "4100");
14578 mips_set_option_string (&mips_tune_string, "4100");
14581 case OPTION_NO_M4100:
14585 mips_set_option_string (&mips_arch_string, "3900");
14586 mips_set_option_string (&mips_tune_string, "3900");
14589 case OPTION_NO_M3900:
14592 case OPTION_MICROMIPS:
14593 if (file_mips_opts.mips16 == 1)
14595 as_bad (_("-mmicromips cannot be used with -mips16"));
14598 file_mips_opts.micromips = 1;
14599 mips_no_prev_insn ();
14602 case OPTION_NO_MICROMIPS:
14603 file_mips_opts.micromips = 0;
14604 mips_no_prev_insn ();
14607 case OPTION_MIPS16:
14608 if (file_mips_opts.micromips == 1)
14610 as_bad (_("-mips16 cannot be used with -micromips"));
14613 file_mips_opts.mips16 = 1;
14614 mips_no_prev_insn ();
14617 case OPTION_NO_MIPS16:
14618 file_mips_opts.mips16 = 0;
14619 mips_no_prev_insn ();
14622 case OPTION_FIX_24K:
14626 case OPTION_NO_FIX_24K:
14630 case OPTION_FIX_RM7000:
14631 mips_fix_rm7000 = 1;
14634 case OPTION_NO_FIX_RM7000:
14635 mips_fix_rm7000 = 0;
14638 case OPTION_FIX_LOONGSON2F_JUMP:
14639 mips_fix_loongson2f_jump = TRUE;
14642 case OPTION_NO_FIX_LOONGSON2F_JUMP:
14643 mips_fix_loongson2f_jump = FALSE;
14646 case OPTION_FIX_LOONGSON2F_NOP:
14647 mips_fix_loongson2f_nop = TRUE;
14650 case OPTION_NO_FIX_LOONGSON2F_NOP:
14651 mips_fix_loongson2f_nop = FALSE;
14654 case OPTION_FIX_VR4120:
14655 mips_fix_vr4120 = 1;
14658 case OPTION_NO_FIX_VR4120:
14659 mips_fix_vr4120 = 0;
14662 case OPTION_FIX_VR4130:
14663 mips_fix_vr4130 = 1;
14666 case OPTION_NO_FIX_VR4130:
14667 mips_fix_vr4130 = 0;
14670 case OPTION_FIX_CN63XXP1:
14671 mips_fix_cn63xxp1 = TRUE;
14674 case OPTION_NO_FIX_CN63XXP1:
14675 mips_fix_cn63xxp1 = FALSE;
14678 case OPTION_RELAX_BRANCH:
14679 mips_relax_branch = 1;
14682 case OPTION_NO_RELAX_BRANCH:
14683 mips_relax_branch = 0;
14686 case OPTION_IGNORE_BRANCH_ISA:
14687 mips_ignore_branch_isa = TRUE;
14690 case OPTION_NO_IGNORE_BRANCH_ISA:
14691 mips_ignore_branch_isa = FALSE;
14694 case OPTION_INSN32:
14695 file_mips_opts.insn32 = TRUE;
14698 case OPTION_NO_INSN32:
14699 file_mips_opts.insn32 = FALSE;
14702 case OPTION_MSHARED:
14703 mips_in_shared = TRUE;
14706 case OPTION_MNO_SHARED:
14707 mips_in_shared = FALSE;
14710 case OPTION_MSYM32:
14711 file_mips_opts.sym32 = TRUE;
14714 case OPTION_MNO_SYM32:
14715 file_mips_opts.sym32 = FALSE;
14718 /* When generating ELF code, we permit -KPIC and -call_shared to
14719 select SVR4_PIC, and -non_shared to select no PIC. This is
14720 intended to be compatible with Irix 5. */
14721 case OPTION_CALL_SHARED:
14722 mips_pic = SVR4_PIC;
14723 mips_abicalls = TRUE;
14726 case OPTION_CALL_NONPIC:
14728 mips_abicalls = TRUE;
14731 case OPTION_NON_SHARED:
14733 mips_abicalls = FALSE;
14736 /* The -xgot option tells the assembler to use 32 bit offsets
14737 when accessing the got in SVR4_PIC mode. It is for Irix
14744 g_switch_value = atoi (arg);
14748 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14751 mips_abi = O32_ABI;
14755 mips_abi = N32_ABI;
14759 mips_abi = N64_ABI;
14760 if (!support_64bit_objects())
14761 as_fatal (_("no compiled in support for 64 bit object file format"));
14765 file_mips_opts.gp = 32;
14769 file_mips_opts.gp = 64;
14773 file_mips_opts.fp = 32;
14777 file_mips_opts.fp = 0;
14781 file_mips_opts.fp = 64;
14784 case OPTION_ODD_SPREG:
14785 file_mips_opts.oddspreg = 1;
14788 case OPTION_NO_ODD_SPREG:
14789 file_mips_opts.oddspreg = 0;
14792 case OPTION_SINGLE_FLOAT:
14793 file_mips_opts.single_float = 1;
14796 case OPTION_DOUBLE_FLOAT:
14797 file_mips_opts.single_float = 0;
14800 case OPTION_SOFT_FLOAT:
14801 file_mips_opts.soft_float = 1;
14804 case OPTION_HARD_FLOAT:
14805 file_mips_opts.soft_float = 0;
14809 if (strcmp (arg, "32") == 0)
14810 mips_abi = O32_ABI;
14811 else if (strcmp (arg, "o64") == 0)
14812 mips_abi = O64_ABI;
14813 else if (strcmp (arg, "n32") == 0)
14814 mips_abi = N32_ABI;
14815 else if (strcmp (arg, "64") == 0)
14817 mips_abi = N64_ABI;
14818 if (! support_64bit_objects())
14819 as_fatal (_("no compiled in support for 64 bit object file "
14822 else if (strcmp (arg, "eabi") == 0)
14823 mips_abi = EABI_ABI;
14826 as_fatal (_("invalid abi -mabi=%s"), arg);
14831 case OPTION_M7000_HILO_FIX:
14832 mips_7000_hilo_fix = TRUE;
14835 case OPTION_MNO_7000_HILO_FIX:
14836 mips_7000_hilo_fix = FALSE;
14839 case OPTION_MDEBUG:
14840 mips_flag_mdebug = TRUE;
14843 case OPTION_NO_MDEBUG:
14844 mips_flag_mdebug = FALSE;
14848 mips_flag_pdr = TRUE;
14851 case OPTION_NO_PDR:
14852 mips_flag_pdr = FALSE;
14855 case OPTION_MVXWORKS_PIC:
14856 mips_pic = VXWORKS_PIC;
14860 if (strcmp (arg, "2008") == 0)
14862 else if (strcmp (arg, "legacy") == 0)
14866 as_fatal (_("invalid NaN setting -mnan=%s"), arg);
14875 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
14880 /* Set up globals to tune for the ISA or processor described by INFO. */
14883 mips_set_tune (const struct mips_cpu_info *info)
14886 mips_tune = info->cpu;
14891 mips_after_parse_args (void)
14893 const struct mips_cpu_info *arch_info = 0;
14894 const struct mips_cpu_info *tune_info = 0;
14896 /* GP relative stuff not working for PE */
14897 if (strncmp (TARGET_OS, "pe", 2) == 0)
14899 if (g_switch_seen && g_switch_value != 0)
14900 as_bad (_("-G not supported in this configuration"));
14901 g_switch_value = 0;
14904 if (mips_abi == NO_ABI)
14905 mips_abi = MIPS_DEFAULT_ABI;
14907 /* The following code determines the architecture.
14908 Similar code was added to GCC 3.3 (see override_options() in
14909 config/mips/mips.c). The GAS and GCC code should be kept in sync
14910 as much as possible. */
14912 if (mips_arch_string != 0)
14913 arch_info = mips_parse_cpu ("-march", mips_arch_string);
14915 if (file_mips_opts.isa != ISA_UNKNOWN)
14917 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
14918 ISA level specified by -mipsN, while arch_info->isa contains
14919 the -march selection (if any). */
14920 if (arch_info != 0)
14922 /* -march takes precedence over -mipsN, since it is more descriptive.
14923 There's no harm in specifying both as long as the ISA levels
14925 if (file_mips_opts.isa != arch_info->isa)
14926 as_bad (_("-%s conflicts with the other architecture options,"
14927 " which imply -%s"),
14928 mips_cpu_info_from_isa (file_mips_opts.isa)->name,
14929 mips_cpu_info_from_isa (arch_info->isa)->name);
14932 arch_info = mips_cpu_info_from_isa (file_mips_opts.isa);
14935 if (arch_info == 0)
14937 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
14938 gas_assert (arch_info);
14941 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
14942 as_bad (_("-march=%s is not compatible with the selected ABI"),
14945 file_mips_opts.arch = arch_info->cpu;
14946 file_mips_opts.isa = arch_info->isa;
14948 /* Set up initial mips_opts state. */
14949 mips_opts = file_mips_opts;
14951 /* The register size inference code is now placed in
14952 file_mips_check_options. */
14954 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
14956 if (mips_tune_string != 0)
14957 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
14959 if (tune_info == 0)
14960 mips_set_tune (arch_info);
14962 mips_set_tune (tune_info);
14964 if (mips_flag_mdebug < 0)
14965 mips_flag_mdebug = 0;
14969 mips_init_after_args (void)
14971 /* initialize opcodes */
14972 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
14973 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
14977 md_pcrel_from (fixS *fixP)
14979 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
14980 switch (fixP->fx_r_type)
14982 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
14983 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
14984 /* Return the address of the delay slot. */
14987 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
14988 case BFD_RELOC_MICROMIPS_JMP:
14989 case BFD_RELOC_MIPS16_16_PCREL_S1:
14990 case BFD_RELOC_16_PCREL_S2:
14991 case BFD_RELOC_MIPS_21_PCREL_S2:
14992 case BFD_RELOC_MIPS_26_PCREL_S2:
14993 case BFD_RELOC_MIPS_JMP:
14994 /* Return the address of the delay slot. */
14997 case BFD_RELOC_MIPS_18_PCREL_S3:
14998 /* Return the aligned address of the doubleword containing
14999 the instruction. */
15007 /* This is called before the symbol table is processed. In order to
15008 work with gcc when using mips-tfile, we must keep all local labels.
15009 However, in other cases, we want to discard them. If we were
15010 called with -g, but we didn't see any debugging information, it may
15011 mean that gcc is smuggling debugging information through to
15012 mips-tfile, in which case we must generate all local labels. */
15015 mips_frob_file_before_adjust (void)
15017 #ifndef NO_ECOFF_DEBUGGING
15018 if (ECOFF_DEBUGGING
15020 && ! ecoff_debugging_seen)
15021 flag_keep_locals = 1;
15025 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15026 the corresponding LO16 reloc. This is called before md_apply_fix and
15027 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15028 relocation operators.
15030 For our purposes, a %lo() expression matches a %got() or %hi()
15033 (a) it refers to the same symbol; and
15034 (b) the offset applied in the %lo() expression is no lower than
15035 the offset applied in the %got() or %hi().
15037 (b) allows us to cope with code like:
15040 lh $4,%lo(foo+2)($4)
15042 ...which is legal on RELA targets, and has a well-defined behaviour
15043 if the user knows that adding 2 to "foo" will not induce a carry to
15046 When several %lo()s match a particular %got() or %hi(), we use the
15047 following rules to distinguish them:
15049 (1) %lo()s with smaller offsets are a better match than %lo()s with
15052 (2) %lo()s with no matching %got() or %hi() are better than those
15053 that already have a matching %got() or %hi().
15055 (3) later %lo()s are better than earlier %lo()s.
15057 These rules are applied in order.
15059 (1) means, among other things, that %lo()s with identical offsets are
15060 chosen if they exist.
15062 (2) means that we won't associate several high-part relocations with
15063 the same low-part relocation unless there's no alternative. Having
15064 several high parts for the same low part is a GNU extension; this rule
15065 allows careful users to avoid it.
15067 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15068 with the last high-part relocation being at the front of the list.
15069 It therefore makes sense to choose the last matching low-part
15070 relocation, all other things being equal. It's also easier
15071 to code that way. */
15074 mips_frob_file (void)
15076 struct mips_hi_fixup *l;
15077 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
15079 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
15081 segment_info_type *seginfo;
15082 bfd_boolean matched_lo_p;
15083 fixS **hi_pos, **lo_pos, **pos;
15085 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
15087 /* If a GOT16 relocation turns out to be against a global symbol,
15088 there isn't supposed to be a matching LO. Ignore %gots against
15089 constants; we'll report an error for those later. */
15090 if (got16_reloc_p (l->fixp->fx_r_type)
15091 && !(l->fixp->fx_addsy
15092 && pic_need_relax (l->fixp->fx_addsy)))
15095 /* Check quickly whether the next fixup happens to be a matching %lo. */
15096 if (fixup_has_matching_lo_p (l->fixp))
15099 seginfo = seg_info (l->seg);
15101 /* Set HI_POS to the position of this relocation in the chain.
15102 Set LO_POS to the position of the chosen low-part relocation.
15103 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15104 relocation that matches an immediately-preceding high-part
15108 matched_lo_p = FALSE;
15109 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
15111 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
15113 if (*pos == l->fixp)
15116 if ((*pos)->fx_r_type == looking_for_rtype
15117 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
15118 && (*pos)->fx_offset >= l->fixp->fx_offset
15120 || (*pos)->fx_offset < (*lo_pos)->fx_offset
15122 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
15125 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
15126 && fixup_has_matching_lo_p (*pos));
15129 /* If we found a match, remove the high-part relocation from its
15130 current position and insert it before the low-part relocation.
15131 Make the offsets match so that fixup_has_matching_lo_p()
15134 We don't warn about unmatched high-part relocations since some
15135 versions of gcc have been known to emit dead "lui ...%hi(...)"
15137 if (lo_pos != NULL)
15139 l->fixp->fx_offset = (*lo_pos)->fx_offset;
15140 if (l->fixp->fx_next != *lo_pos)
15142 *hi_pos = l->fixp->fx_next;
15143 l->fixp->fx_next = *lo_pos;
15151 mips_force_relocation (fixS *fixp)
15153 if (generic_force_reloc (fixp))
15156 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15157 so that the linker relaxation can update targets. */
15158 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15159 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15160 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
15163 /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2
15164 and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and
15165 microMIPS symbols so that we can do cross-mode branch diagnostics
15166 and BAL to JALX conversion by the linker. */
15167 if ((fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
15168 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
15169 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2)
15171 && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp->fx_addsy)))
15174 /* We want all PC-relative relocations to be kept for R6 relaxation. */
15175 if (ISA_IS_R6 (file_mips_opts.isa)
15176 && (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
15177 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
15178 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2
15179 || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3
15180 || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2
15181 || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL
15182 || fixp->fx_r_type == BFD_RELOC_LO16_PCREL))
15188 /* Implement TC_FORCE_RELOCATION_ABS. */
15191 mips_force_relocation_abs (fixS *fixp)
15193 if (generic_force_reloc (fixp))
15196 /* These relocations do not have enough bits in the in-place addend
15197 to hold an arbitrary absolute section's offset. */
15198 if (HAVE_IN_PLACE_ADDENDS && limited_pcrel_reloc_p (fixp->fx_r_type))
15204 /* Read the instruction associated with RELOC from BUF. */
15206 static unsigned int
15207 read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc)
15209 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
15210 return read_compressed_insn (buf, 4);
15212 return read_insn (buf);
15215 /* Write instruction INSN to BUF, given that it has been relocated
15219 write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc,
15220 unsigned long insn)
15222 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
15223 write_compressed_insn (buf, insn, 4);
15225 write_insn (buf, insn);
15228 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15229 to a symbol in another ISA mode, which cannot be converted to JALX. */
15232 fix_bad_cross_mode_jump_p (fixS *fixP)
15234 unsigned long opcode;
15238 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
15241 other = S_GET_OTHER (fixP->fx_addsy);
15242 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15243 opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26;
15244 switch (fixP->fx_r_type)
15246 case BFD_RELOC_MIPS_JMP:
15247 return opcode != 0x1d && opcode != 0x03 && ELF_ST_IS_COMPRESSED (other);
15248 case BFD_RELOC_MICROMIPS_JMP:
15249 return opcode != 0x3c && opcode != 0x3d && !ELF_ST_IS_MICROMIPS (other);
15255 /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX
15256 jump to a symbol in the same ISA mode. */
15259 fix_bad_same_mode_jalx_p (fixS *fixP)
15261 unsigned long opcode;
15265 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
15268 other = S_GET_OTHER (fixP->fx_addsy);
15269 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15270 opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26;
15271 switch (fixP->fx_r_type)
15273 case BFD_RELOC_MIPS_JMP:
15274 return opcode == 0x1d && !ELF_ST_IS_COMPRESSED (other);
15275 case BFD_RELOC_MIPS16_JMP:
15276 return opcode == 0x07 && ELF_ST_IS_COMPRESSED (other);
15277 case BFD_RELOC_MICROMIPS_JMP:
15278 return opcode == 0x3c && ELF_ST_IS_COMPRESSED (other);
15284 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15285 to a symbol whose value plus addend is not aligned according to the
15286 ultimate (after linker relaxation) jump instruction's immediate field
15287 requirement, either to (1 << SHIFT), or, for jumps from microMIPS to
15288 regular MIPS code, to (1 << 2). */
15291 fix_bad_misaligned_jump_p (fixS *fixP, int shift)
15293 bfd_boolean micro_to_mips_p;
15297 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
15300 other = S_GET_OTHER (fixP->fx_addsy);
15301 val = S_GET_VALUE (fixP->fx_addsy) | ELF_ST_IS_COMPRESSED (other);
15302 val += fixP->fx_offset;
15303 micro_to_mips_p = (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP
15304 && !ELF_ST_IS_MICROMIPS (other));
15305 return ((val & ((1 << (micro_to_mips_p ? 2 : shift)) - 1))
15306 != ELF_ST_IS_COMPRESSED (other));
15309 /* Return TRUE if the instruction pointed to by FIXP is an invalid branch
15310 to a symbol whose annotation indicates another ISA mode. For absolute
15311 symbols check the ISA bit instead.
15313 We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS
15314 symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular
15315 MIPS symbols and associated with BAL instructions as these instructions
15316 may be converted to JALX by the linker. */
15319 fix_bad_cross_mode_branch_p (fixS *fixP)
15321 bfd_boolean absolute_p;
15322 unsigned long opcode;
15328 if (mips_ignore_branch_isa)
15331 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
15334 symsec = S_GET_SEGMENT (fixP->fx_addsy);
15335 absolute_p = bfd_is_abs_section (symsec);
15337 val = S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset;
15338 other = S_GET_OTHER (fixP->fx_addsy);
15340 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15341 opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 16;
15342 switch (fixP->fx_r_type)
15344 case BFD_RELOC_16_PCREL_S2:
15345 return ((absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other))
15346 && opcode != 0x0411);
15347 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15348 return ((absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other))
15349 && opcode != 0x4060);
15350 case BFD_RELOC_MIPS_21_PCREL_S2:
15351 case BFD_RELOC_MIPS_26_PCREL_S2:
15352 return absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other);
15353 case BFD_RELOC_MIPS16_16_PCREL_S1:
15354 return absolute_p ? !(val & 1) : !ELF_ST_IS_MIPS16 (other);
15355 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15356 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15357 return absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other);
15363 /* Return TRUE if the symbol plus addend associated with a regular MIPS
15364 branch instruction pointed to by FIXP is not aligned according to the
15365 branch instruction's immediate field requirement. We need the addend
15366 to preserve the ISA bit and also the sum must not have bit 2 set. We
15367 must explicitly OR in the ISA bit from symbol annotation as the bit
15368 won't be set in the symbol's value then. */
15371 fix_bad_misaligned_branch_p (fixS *fixP)
15373 bfd_boolean absolute_p;
15380 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
15383 symsec = S_GET_SEGMENT (fixP->fx_addsy);
15384 absolute_p = bfd_is_abs_section (symsec);
15386 val = S_GET_VALUE (fixP->fx_addsy);
15387 other = S_GET_OTHER (fixP->fx_addsy);
15388 off = fixP->fx_offset;
15390 isa_bit = absolute_p ? (val + off) & 1 : ELF_ST_IS_COMPRESSED (other);
15391 val |= ELF_ST_IS_COMPRESSED (other);
15393 return (val & 0x3) != isa_bit;
15396 /* Make the necessary checks on a regular MIPS branch pointed to by FIXP
15397 and its calculated value VAL. */
15400 fix_validate_branch (fixS *fixP, valueT val)
15402 if (fixP->fx_done && (val & 0x3) != 0)
15403 as_bad_where (fixP->fx_file, fixP->fx_line,
15404 _("branch to misaligned address (0x%lx)"),
15405 (long) (val + md_pcrel_from (fixP)));
15406 else if (fix_bad_cross_mode_branch_p (fixP))
15407 as_bad_where (fixP->fx_file, fixP->fx_line,
15408 _("branch to a symbol in another ISA mode"));
15409 else if (fix_bad_misaligned_branch_p (fixP))
15410 as_bad_where (fixP->fx_file, fixP->fx_line,
15411 _("branch to misaligned address (0x%lx)"),
15412 (long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset));
15413 else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x3) != 0)
15414 as_bad_where (fixP->fx_file, fixP->fx_line,
15415 _("cannot encode misaligned addend "
15416 "in the relocatable field (0x%lx)"),
15417 (long) fixP->fx_offset);
15420 /* Apply a fixup to the object file. */
15423 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
15426 unsigned long insn;
15427 reloc_howto_type *howto;
15429 if (fixP->fx_pcrel)
15430 switch (fixP->fx_r_type)
15432 case BFD_RELOC_16_PCREL_S2:
15433 case BFD_RELOC_MIPS16_16_PCREL_S1:
15434 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15435 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15436 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15437 case BFD_RELOC_32_PCREL:
15438 case BFD_RELOC_MIPS_21_PCREL_S2:
15439 case BFD_RELOC_MIPS_26_PCREL_S2:
15440 case BFD_RELOC_MIPS_18_PCREL_S3:
15441 case BFD_RELOC_MIPS_19_PCREL_S2:
15442 case BFD_RELOC_HI16_S_PCREL:
15443 case BFD_RELOC_LO16_PCREL:
15447 fixP->fx_r_type = BFD_RELOC_32_PCREL;
15451 as_bad_where (fixP->fx_file, fixP->fx_line,
15452 _("PC-relative reference to a different section"));
15456 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
15457 that have no MIPS ELF equivalent. */
15458 if (fixP->fx_r_type != BFD_RELOC_8)
15460 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
15465 gas_assert (fixP->fx_size == 2
15466 || fixP->fx_size == 4
15467 || fixP->fx_r_type == BFD_RELOC_8
15468 || fixP->fx_r_type == BFD_RELOC_16
15469 || fixP->fx_r_type == BFD_RELOC_64
15470 || fixP->fx_r_type == BFD_RELOC_CTOR
15471 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
15472 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
15473 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
15474 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
15475 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64
15476 || fixP->fx_r_type == BFD_RELOC_NONE);
15478 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15480 /* Don't treat parts of a composite relocation as done. There are two
15483 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15484 should nevertheless be emitted if the first part is.
15486 (2) In normal usage, composite relocations are never assembly-time
15487 constants. The easiest way of dealing with the pathological
15488 exceptions is to generate a relocation against STN_UNDEF and
15489 leave everything up to the linker. */
15490 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
15493 switch (fixP->fx_r_type)
15495 case BFD_RELOC_MIPS_TLS_GD:
15496 case BFD_RELOC_MIPS_TLS_LDM:
15497 case BFD_RELOC_MIPS_TLS_DTPREL32:
15498 case BFD_RELOC_MIPS_TLS_DTPREL64:
15499 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
15500 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
15501 case BFD_RELOC_MIPS_TLS_GOTTPREL:
15502 case BFD_RELOC_MIPS_TLS_TPREL32:
15503 case BFD_RELOC_MIPS_TLS_TPREL64:
15504 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
15505 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
15506 case BFD_RELOC_MICROMIPS_TLS_GD:
15507 case BFD_RELOC_MICROMIPS_TLS_LDM:
15508 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
15509 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
15510 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
15511 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
15512 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
15513 case BFD_RELOC_MIPS16_TLS_GD:
15514 case BFD_RELOC_MIPS16_TLS_LDM:
15515 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
15516 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
15517 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
15518 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
15519 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
15520 if (fixP->fx_addsy)
15521 S_SET_THREAD_LOCAL (fixP->fx_addsy);
15523 as_bad_where (fixP->fx_file, fixP->fx_line,
15524 _("TLS relocation against a constant"));
15527 case BFD_RELOC_MIPS_JMP:
15528 case BFD_RELOC_MIPS16_JMP:
15529 case BFD_RELOC_MICROMIPS_JMP:
15533 gas_assert (!fixP->fx_done);
15535 /* Shift is 2, unusually, for microMIPS JALX. */
15536 if (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP
15537 && (read_compressed_insn (buf, 4) >> 26) != 0x3c)
15542 if (fix_bad_cross_mode_jump_p (fixP))
15543 as_bad_where (fixP->fx_file, fixP->fx_line,
15544 _("jump to a symbol in another ISA mode"));
15545 else if (fix_bad_same_mode_jalx_p (fixP))
15546 as_bad_where (fixP->fx_file, fixP->fx_line,
15547 _("JALX to a symbol in the same ISA mode"));
15548 else if (fix_bad_misaligned_jump_p (fixP, shift))
15549 as_bad_where (fixP->fx_file, fixP->fx_line,
15550 _("jump to misaligned address (0x%lx)"),
15551 (long) (S_GET_VALUE (fixP->fx_addsy)
15552 + fixP->fx_offset));
15553 else if (HAVE_IN_PLACE_ADDENDS
15554 && (fixP->fx_offset & ((1 << shift) - 1)) != 0)
15555 as_bad_where (fixP->fx_file, fixP->fx_line,
15556 _("cannot encode misaligned addend "
15557 "in the relocatable field (0x%lx)"),
15558 (long) fixP->fx_offset);
15560 /* Fall through. */
15562 case BFD_RELOC_MIPS_SHIFT5:
15563 case BFD_RELOC_MIPS_SHIFT6:
15564 case BFD_RELOC_MIPS_GOT_DISP:
15565 case BFD_RELOC_MIPS_GOT_PAGE:
15566 case BFD_RELOC_MIPS_GOT_OFST:
15567 case BFD_RELOC_MIPS_SUB:
15568 case BFD_RELOC_MIPS_INSERT_A:
15569 case BFD_RELOC_MIPS_INSERT_B:
15570 case BFD_RELOC_MIPS_DELETE:
15571 case BFD_RELOC_MIPS_HIGHEST:
15572 case BFD_RELOC_MIPS_HIGHER:
15573 case BFD_RELOC_MIPS_SCN_DISP:
15574 case BFD_RELOC_MIPS_REL16:
15575 case BFD_RELOC_MIPS_RELGOT:
15576 case BFD_RELOC_MIPS_JALR:
15577 case BFD_RELOC_HI16:
15578 case BFD_RELOC_HI16_S:
15579 case BFD_RELOC_LO16:
15580 case BFD_RELOC_GPREL16:
15581 case BFD_RELOC_MIPS_LITERAL:
15582 case BFD_RELOC_MIPS_CALL16:
15583 case BFD_RELOC_MIPS_GOT16:
15584 case BFD_RELOC_GPREL32:
15585 case BFD_RELOC_MIPS_GOT_HI16:
15586 case BFD_RELOC_MIPS_GOT_LO16:
15587 case BFD_RELOC_MIPS_CALL_HI16:
15588 case BFD_RELOC_MIPS_CALL_LO16:
15589 case BFD_RELOC_HI16_S_PCREL:
15590 case BFD_RELOC_LO16_PCREL:
15591 case BFD_RELOC_MIPS16_GPREL:
15592 case BFD_RELOC_MIPS16_GOT16:
15593 case BFD_RELOC_MIPS16_CALL16:
15594 case BFD_RELOC_MIPS16_HI16:
15595 case BFD_RELOC_MIPS16_HI16_S:
15596 case BFD_RELOC_MIPS16_LO16:
15597 case BFD_RELOC_MICROMIPS_GOT_DISP:
15598 case BFD_RELOC_MICROMIPS_GOT_PAGE:
15599 case BFD_RELOC_MICROMIPS_GOT_OFST:
15600 case BFD_RELOC_MICROMIPS_SUB:
15601 case BFD_RELOC_MICROMIPS_HIGHEST:
15602 case BFD_RELOC_MICROMIPS_HIGHER:
15603 case BFD_RELOC_MICROMIPS_SCN_DISP:
15604 case BFD_RELOC_MICROMIPS_JALR:
15605 case BFD_RELOC_MICROMIPS_HI16:
15606 case BFD_RELOC_MICROMIPS_HI16_S:
15607 case BFD_RELOC_MICROMIPS_LO16:
15608 case BFD_RELOC_MICROMIPS_GPREL16:
15609 case BFD_RELOC_MICROMIPS_LITERAL:
15610 case BFD_RELOC_MICROMIPS_CALL16:
15611 case BFD_RELOC_MICROMIPS_GOT16:
15612 case BFD_RELOC_MICROMIPS_GOT_HI16:
15613 case BFD_RELOC_MICROMIPS_GOT_LO16:
15614 case BFD_RELOC_MICROMIPS_CALL_HI16:
15615 case BFD_RELOC_MICROMIPS_CALL_LO16:
15616 case BFD_RELOC_MIPS_EH:
15621 if (calculate_reloc (fixP->fx_r_type, *valP, &value))
15623 insn = read_reloc_insn (buf, fixP->fx_r_type);
15624 if (mips16_reloc_p (fixP->fx_r_type))
15625 insn |= mips16_immed_extend (value, 16);
15627 insn |= (value & 0xffff);
15628 write_reloc_insn (buf, fixP->fx_r_type, insn);
15631 as_bad_where (fixP->fx_file, fixP->fx_line,
15632 _("unsupported constant in relocation"));
15637 /* This is handled like BFD_RELOC_32, but we output a sign
15638 extended value if we are only 32 bits. */
15641 if (8 <= sizeof (valueT))
15642 md_number_to_chars (buf, *valP, 8);
15647 if ((*valP & 0x80000000) != 0)
15651 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4);
15652 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4);
15657 case BFD_RELOC_RVA:
15659 case BFD_RELOC_32_PCREL:
15662 /* If we are deleting this reloc entry, we must fill in the
15663 value now. This can happen if we have a .word which is not
15664 resolved when it appears but is later defined. */
15666 md_number_to_chars (buf, *valP, fixP->fx_size);
15669 case BFD_RELOC_MIPS_21_PCREL_S2:
15670 fix_validate_branch (fixP, *valP);
15671 if (!fixP->fx_done)
15674 if (*valP + 0x400000 <= 0x7fffff)
15676 insn = read_insn (buf);
15677 insn |= (*valP >> 2) & 0x1fffff;
15678 write_insn (buf, insn);
15681 as_bad_where (fixP->fx_file, fixP->fx_line,
15682 _("branch out of range"));
15685 case BFD_RELOC_MIPS_26_PCREL_S2:
15686 fix_validate_branch (fixP, *valP);
15687 if (!fixP->fx_done)
15690 if (*valP + 0x8000000 <= 0xfffffff)
15692 insn = read_insn (buf);
15693 insn |= (*valP >> 2) & 0x3ffffff;
15694 write_insn (buf, insn);
15697 as_bad_where (fixP->fx_file, fixP->fx_line,
15698 _("branch out of range"));
15701 case BFD_RELOC_MIPS_18_PCREL_S3:
15702 if (fixP->fx_addsy && (S_GET_VALUE (fixP->fx_addsy) & 0x7) != 0)
15703 as_bad_where (fixP->fx_file, fixP->fx_line,
15704 _("PC-relative access using misaligned symbol (%lx)"),
15705 (long) S_GET_VALUE (fixP->fx_addsy));
15706 if ((fixP->fx_offset & 0x7) != 0)
15707 as_bad_where (fixP->fx_file, fixP->fx_line,
15708 _("PC-relative access using misaligned offset (%lx)"),
15709 (long) fixP->fx_offset);
15710 if (!fixP->fx_done)
15713 if (*valP + 0x100000 <= 0x1fffff)
15715 insn = read_insn (buf);
15716 insn |= (*valP >> 3) & 0x3ffff;
15717 write_insn (buf, insn);
15720 as_bad_where (fixP->fx_file, fixP->fx_line,
15721 _("PC-relative access out of range"));
15724 case BFD_RELOC_MIPS_19_PCREL_S2:
15725 if ((*valP & 0x3) != 0)
15726 as_bad_where (fixP->fx_file, fixP->fx_line,
15727 _("PC-relative access to misaligned address (%lx)"),
15729 if (!fixP->fx_done)
15732 if (*valP + 0x100000 <= 0x1fffff)
15734 insn = read_insn (buf);
15735 insn |= (*valP >> 2) & 0x7ffff;
15736 write_insn (buf, insn);
15739 as_bad_where (fixP->fx_file, fixP->fx_line,
15740 _("PC-relative access out of range"));
15743 case BFD_RELOC_16_PCREL_S2:
15744 fix_validate_branch (fixP, *valP);
15746 /* We need to save the bits in the instruction since fixup_segment()
15747 might be deleting the relocation entry (i.e., a branch within
15748 the current segment). */
15749 if (! fixP->fx_done)
15752 /* Update old instruction data. */
15753 insn = read_insn (buf);
15755 if (*valP + 0x20000 <= 0x3ffff)
15757 insn |= (*valP >> 2) & 0xffff;
15758 write_insn (buf, insn);
15760 else if (fixP->fx_tcbit2
15762 && fixP->fx_frag->fr_address >= text_section->vma
15763 && (fixP->fx_frag->fr_address
15764 < text_section->vma + bfd_get_section_size (text_section))
15765 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
15766 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
15767 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
15769 /* The branch offset is too large. If this is an
15770 unconditional branch, and we are not generating PIC code,
15771 we can convert it to an absolute jump instruction. */
15772 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
15773 insn = 0x0c000000; /* jal */
15775 insn = 0x08000000; /* j */
15776 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
15778 fixP->fx_addsy = section_symbol (text_section);
15779 *valP += md_pcrel_from (fixP);
15780 write_insn (buf, insn);
15784 /* If we got here, we have branch-relaxation disabled,
15785 and there's nothing we can do to fix this instruction
15786 without turning it into a longer sequence. */
15787 as_bad_where (fixP->fx_file, fixP->fx_line,
15788 _("branch out of range"));
15792 case BFD_RELOC_MIPS16_16_PCREL_S1:
15793 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15794 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15795 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15796 gas_assert (!fixP->fx_done);
15797 if (fix_bad_cross_mode_branch_p (fixP))
15798 as_bad_where (fixP->fx_file, fixP->fx_line,
15799 _("branch to a symbol in another ISA mode"));
15800 else if (fixP->fx_addsy
15801 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
15802 && !bfd_is_abs_section (S_GET_SEGMENT (fixP->fx_addsy))
15803 && (fixP->fx_offset & 0x1) != 0)
15804 as_bad_where (fixP->fx_file, fixP->fx_line,
15805 _("branch to misaligned address (0x%lx)"),
15806 (long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset));
15807 else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x1) != 0)
15808 as_bad_where (fixP->fx_file, fixP->fx_line,
15809 _("cannot encode misaligned addend "
15810 "in the relocatable field (0x%lx)"),
15811 (long) fixP->fx_offset);
15814 case BFD_RELOC_VTABLE_INHERIT:
15817 && !S_IS_DEFINED (fixP->fx_addsy)
15818 && !S_IS_WEAK (fixP->fx_addsy))
15819 S_SET_WEAK (fixP->fx_addsy);
15822 case BFD_RELOC_NONE:
15823 case BFD_RELOC_VTABLE_ENTRY:
15831 /* Remember value for tc_gen_reloc. */
15832 fixP->fx_addnumber = *valP;
15842 c = get_symbol_name (&name);
15843 p = (symbolS *) symbol_find_or_make (name);
15844 (void) restore_line_pointer (c);
15848 /* Align the current frag to a given power of two. If a particular
15849 fill byte should be used, FILL points to an integer that contains
15850 that byte, otherwise FILL is null.
15852 This function used to have the comment:
15854 The MIPS assembler also automatically adjusts any preceding label.
15856 The implementation therefore applied the adjustment to a maximum of
15857 one label. However, other label adjustments are applied to batches
15858 of labels, and adjusting just one caused problems when new labels
15859 were added for the sake of debugging or unwind information.
15860 We therefore adjust all preceding labels (given as LABELS) instead. */
15863 mips_align (int to, int *fill, struct insn_label_list *labels)
15865 mips_emit_delays ();
15866 mips_record_compressed_mode ();
15867 if (fill == NULL && subseg_text_p (now_seg))
15868 frag_align_code (to, 0);
15870 frag_align (to, fill ? *fill : 0, 0);
15871 record_alignment (now_seg, to);
15872 mips_move_labels (labels, FALSE);
15875 /* Align to a given power of two. .align 0 turns off the automatic
15876 alignment used by the data creating pseudo-ops. */
15879 s_align (int x ATTRIBUTE_UNUSED)
15881 int temp, fill_value, *fill_ptr;
15882 long max_alignment = 28;
15884 /* o Note that the assembler pulls down any immediately preceding label
15885 to the aligned address.
15886 o It's not documented but auto alignment is reinstated by
15887 a .align pseudo instruction.
15888 o Note also that after auto alignment is turned off the mips assembler
15889 issues an error on attempt to assemble an improperly aligned data item.
15892 temp = get_absolute_expression ();
15893 if (temp > max_alignment)
15894 as_bad (_("alignment too large, %d assumed"), temp = max_alignment);
15897 as_warn (_("alignment negative, 0 assumed"));
15900 if (*input_line_pointer == ',')
15902 ++input_line_pointer;
15903 fill_value = get_absolute_expression ();
15904 fill_ptr = &fill_value;
15910 segment_info_type *si = seg_info (now_seg);
15911 struct insn_label_list *l = si->label_list;
15912 /* Auto alignment should be switched on by next section change. */
15914 mips_align (temp, fill_ptr, l);
15921 demand_empty_rest_of_line ();
15925 s_change_sec (int sec)
15929 /* The ELF backend needs to know that we are changing sections, so
15930 that .previous works correctly. We could do something like check
15931 for an obj_section_change_hook macro, but that might be confusing
15932 as it would not be appropriate to use it in the section changing
15933 functions in read.c, since obj-elf.c intercepts those. FIXME:
15934 This should be cleaner, somehow. */
15935 obj_elf_section_change_hook ();
15937 mips_emit_delays ();
15948 subseg_set (bss_section, (subsegT) get_absolute_expression ());
15949 demand_empty_rest_of_line ();
15953 seg = subseg_new (RDATA_SECTION_NAME,
15954 (subsegT) get_absolute_expression ());
15955 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
15956 | SEC_READONLY | SEC_RELOC
15958 if (strncmp (TARGET_OS, "elf", 3) != 0)
15959 record_alignment (seg, 4);
15960 demand_empty_rest_of_line ();
15964 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
15965 bfd_set_section_flags (stdoutput, seg,
15966 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
15967 if (strncmp (TARGET_OS, "elf", 3) != 0)
15968 record_alignment (seg, 4);
15969 demand_empty_rest_of_line ();
15973 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
15974 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
15975 if (strncmp (TARGET_OS, "elf", 3) != 0)
15976 record_alignment (seg, 4);
15977 demand_empty_rest_of_line ();
15985 s_change_section (int ignore ATTRIBUTE_UNUSED)
15988 char *section_name;
15993 int section_entry_size;
15994 int section_alignment;
15996 saved_ilp = input_line_pointer;
15997 endc = get_symbol_name (§ion_name);
15998 c = (endc == '"' ? input_line_pointer[1] : endc);
16000 next_c = input_line_pointer [(endc == '"' ? 2 : 1)];
16002 /* Do we have .section Name<,"flags">? */
16003 if (c != ',' || (c == ',' && next_c == '"'))
16005 /* Just after name is now '\0'. */
16006 (void) restore_line_pointer (endc);
16007 input_line_pointer = saved_ilp;
16008 obj_elf_section (ignore);
16012 section_name = xstrdup (section_name);
16013 c = restore_line_pointer (endc);
16015 input_line_pointer++;
16017 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16019 section_type = get_absolute_expression ();
16023 if (*input_line_pointer++ == ',')
16024 section_flag = get_absolute_expression ();
16028 if (*input_line_pointer++ == ',')
16029 section_entry_size = get_absolute_expression ();
16031 section_entry_size = 0;
16033 if (*input_line_pointer++ == ',')
16034 section_alignment = get_absolute_expression ();
16036 section_alignment = 0;
16038 /* FIXME: really ignore? */
16039 (void) section_alignment;
16041 /* When using the generic form of .section (as implemented by obj-elf.c),
16042 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16043 traditionally had to fall back on the more common @progbits instead.
16045 There's nothing really harmful in this, since bfd will correct
16046 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16047 means that, for backwards compatibility, the special_section entries
16048 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16050 Even so, we shouldn't force users of the MIPS .section syntax to
16051 incorrectly label the sections as SHT_PROGBITS. The best compromise
16052 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16053 generic type-checking code. */
16054 if (section_type == SHT_MIPS_DWARF)
16055 section_type = SHT_PROGBITS;
16057 obj_elf_change_section (section_name, section_type, 0, section_flag,
16058 section_entry_size, 0, 0, 0);
16060 if (now_seg->name != section_name)
16061 free (section_name);
16065 mips_enable_auto_align (void)
16071 s_cons (int log_size)
16073 segment_info_type *si = seg_info (now_seg);
16074 struct insn_label_list *l = si->label_list;
16076 mips_emit_delays ();
16077 if (log_size > 0 && auto_align)
16078 mips_align (log_size, 0, l);
16079 cons (1 << log_size);
16080 mips_clear_insn_labels ();
16084 s_float_cons (int type)
16086 segment_info_type *si = seg_info (now_seg);
16087 struct insn_label_list *l = si->label_list;
16089 mips_emit_delays ();
16094 mips_align (3, 0, l);
16096 mips_align (2, 0, l);
16100 mips_clear_insn_labels ();
16103 /* Handle .globl. We need to override it because on Irix 5 you are
16106 where foo is an undefined symbol, to mean that foo should be
16107 considered to be the address of a function. */
16110 s_mips_globl (int x ATTRIBUTE_UNUSED)
16119 c = get_symbol_name (&name);
16120 symbolP = symbol_find_or_make (name);
16121 S_SET_EXTERNAL (symbolP);
16123 *input_line_pointer = c;
16124 SKIP_WHITESPACE_AFTER_NAME ();
16126 /* On Irix 5, every global symbol that is not explicitly labelled as
16127 being a function is apparently labelled as being an object. */
16130 if (!is_end_of_line[(unsigned char) *input_line_pointer]
16131 && (*input_line_pointer != ','))
16136 c = get_symbol_name (&secname);
16137 sec = bfd_get_section_by_name (stdoutput, secname);
16139 as_bad (_("%s: no such section"), secname);
16140 (void) restore_line_pointer (c);
16142 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
16143 flag = BSF_FUNCTION;
16146 symbol_get_bfdsym (symbolP)->flags |= flag;
16148 c = *input_line_pointer;
16151 input_line_pointer++;
16152 SKIP_WHITESPACE ();
16153 if (is_end_of_line[(unsigned char) *input_line_pointer])
16159 demand_empty_rest_of_line ();
16163 s_option (int x ATTRIBUTE_UNUSED)
16168 c = get_symbol_name (&opt);
16172 /* FIXME: What does this mean? */
16174 else if (strncmp (opt, "pic", 3) == 0 && ISDIGIT (opt[3]) && opt[4] == '\0')
16178 i = atoi (opt + 3);
16179 if (i != 0 && i != 2)
16180 as_bad (_(".option pic%d not supported"), i);
16181 else if (mips_pic == VXWORKS_PIC)
16182 as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i);
16187 mips_pic = SVR4_PIC;
16188 mips_abicalls = TRUE;
16191 if (mips_pic == SVR4_PIC)
16193 if (g_switch_seen && g_switch_value != 0)
16194 as_warn (_("-G may not be used with SVR4 PIC code"));
16195 g_switch_value = 0;
16196 bfd_set_gp_size (stdoutput, 0);
16200 as_warn (_("unrecognized option \"%s\""), opt);
16202 (void) restore_line_pointer (c);
16203 demand_empty_rest_of_line ();
16206 /* This structure is used to hold a stack of .set values. */
16208 struct mips_option_stack
16210 struct mips_option_stack *next;
16211 struct mips_set_options options;
16214 static struct mips_option_stack *mips_opts_stack;
16216 /* Return status for .set/.module option handling. */
16218 enum code_option_type
16220 /* Unrecognized option. */
16221 OPTION_TYPE_BAD = -1,
16223 /* Ordinary option. */
16224 OPTION_TYPE_NORMAL,
16226 /* ISA changing option. */
16230 /* Handle common .set/.module options. Return status indicating option
16233 static enum code_option_type
16234 parse_code_option (char * name)
16236 bfd_boolean isa_set = FALSE;
16237 const struct mips_ase *ase;
16239 if (strncmp (name, "at=", 3) == 0)
16241 char *s = name + 3;
16243 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
16244 as_bad (_("unrecognized register name `%s'"), s);
16246 else if (strcmp (name, "at") == 0)
16247 mips_opts.at = ATREG;
16248 else if (strcmp (name, "noat") == 0)
16249 mips_opts.at = ZERO;
16250 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
16251 mips_opts.nomove = 0;
16252 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
16253 mips_opts.nomove = 1;
16254 else if (strcmp (name, "bopt") == 0)
16255 mips_opts.nobopt = 0;
16256 else if (strcmp (name, "nobopt") == 0)
16257 mips_opts.nobopt = 1;
16258 else if (strcmp (name, "gp=32") == 0)
16260 else if (strcmp (name, "gp=64") == 0)
16262 else if (strcmp (name, "fp=32") == 0)
16264 else if (strcmp (name, "fp=xx") == 0)
16266 else if (strcmp (name, "fp=64") == 0)
16268 else if (strcmp (name, "softfloat") == 0)
16269 mips_opts.soft_float = 1;
16270 else if (strcmp (name, "hardfloat") == 0)
16271 mips_opts.soft_float = 0;
16272 else if (strcmp (name, "singlefloat") == 0)
16273 mips_opts.single_float = 1;
16274 else if (strcmp (name, "doublefloat") == 0)
16275 mips_opts.single_float = 0;
16276 else if (strcmp (name, "nooddspreg") == 0)
16277 mips_opts.oddspreg = 0;
16278 else if (strcmp (name, "oddspreg") == 0)
16279 mips_opts.oddspreg = 1;
16280 else if (strcmp (name, "mips16") == 0
16281 || strcmp (name, "MIPS-16") == 0)
16282 mips_opts.mips16 = 1;
16283 else if (strcmp (name, "nomips16") == 0
16284 || strcmp (name, "noMIPS-16") == 0)
16285 mips_opts.mips16 = 0;
16286 else if (strcmp (name, "micromips") == 0)
16287 mips_opts.micromips = 1;
16288 else if (strcmp (name, "nomicromips") == 0)
16289 mips_opts.micromips = 0;
16290 else if (name[0] == 'n'
16292 && (ase = mips_lookup_ase (name + 2)))
16293 mips_set_ase (ase, &mips_opts, FALSE);
16294 else if ((ase = mips_lookup_ase (name)))
16295 mips_set_ase (ase, &mips_opts, TRUE);
16296 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
16298 /* Permit the user to change the ISA and architecture on the fly.
16299 Needless to say, misuse can cause serious problems. */
16300 if (strncmp (name, "arch=", 5) == 0)
16302 const struct mips_cpu_info *p;
16304 p = mips_parse_cpu ("internal use", name + 5);
16306 as_bad (_("unknown architecture %s"), name + 5);
16309 mips_opts.arch = p->cpu;
16310 mips_opts.isa = p->isa;
16314 else if (strncmp (name, "mips", 4) == 0)
16316 const struct mips_cpu_info *p;
16318 p = mips_parse_cpu ("internal use", name);
16320 as_bad (_("unknown ISA level %s"), name + 4);
16323 mips_opts.arch = p->cpu;
16324 mips_opts.isa = p->isa;
16329 as_bad (_("unknown ISA or architecture %s"), name);
16331 else if (strcmp (name, "autoextend") == 0)
16332 mips_opts.noautoextend = 0;
16333 else if (strcmp (name, "noautoextend") == 0)
16334 mips_opts.noautoextend = 1;
16335 else if (strcmp (name, "insn32") == 0)
16336 mips_opts.insn32 = TRUE;
16337 else if (strcmp (name, "noinsn32") == 0)
16338 mips_opts.insn32 = FALSE;
16339 else if (strcmp (name, "sym32") == 0)
16340 mips_opts.sym32 = TRUE;
16341 else if (strcmp (name, "nosym32") == 0)
16342 mips_opts.sym32 = FALSE;
16344 return OPTION_TYPE_BAD;
16346 return isa_set ? OPTION_TYPE_ISA : OPTION_TYPE_NORMAL;
16349 /* Handle the .set pseudo-op. */
16352 s_mipsset (int x ATTRIBUTE_UNUSED)
16354 enum code_option_type type = OPTION_TYPE_NORMAL;
16355 char *name = input_line_pointer, ch;
16357 file_mips_check_options ();
16359 while (!is_end_of_line[(unsigned char) *input_line_pointer])
16360 ++input_line_pointer;
16361 ch = *input_line_pointer;
16362 *input_line_pointer = '\0';
16364 if (strchr (name, ','))
16366 /* Generic ".set" directive; use the generic handler. */
16367 *input_line_pointer = ch;
16368 input_line_pointer = name;
16373 if (strcmp (name, "reorder") == 0)
16375 if (mips_opts.noreorder)
16378 else if (strcmp (name, "noreorder") == 0)
16380 if (!mips_opts.noreorder)
16381 start_noreorder ();
16383 else if (strcmp (name, "macro") == 0)
16384 mips_opts.warn_about_macros = 0;
16385 else if (strcmp (name, "nomacro") == 0)
16387 if (mips_opts.noreorder == 0)
16388 as_bad (_("`noreorder' must be set before `nomacro'"));
16389 mips_opts.warn_about_macros = 1;
16391 else if (strcmp (name, "gp=default") == 0)
16392 mips_opts.gp = file_mips_opts.gp;
16393 else if (strcmp (name, "fp=default") == 0)
16394 mips_opts.fp = file_mips_opts.fp;
16395 else if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
16397 mips_opts.isa = file_mips_opts.isa;
16398 mips_opts.arch = file_mips_opts.arch;
16399 mips_opts.gp = file_mips_opts.gp;
16400 mips_opts.fp = file_mips_opts.fp;
16402 else if (strcmp (name, "push") == 0)
16404 struct mips_option_stack *s;
16406 s = XNEW (struct mips_option_stack);
16407 s->next = mips_opts_stack;
16408 s->options = mips_opts;
16409 mips_opts_stack = s;
16411 else if (strcmp (name, "pop") == 0)
16413 struct mips_option_stack *s;
16415 s = mips_opts_stack;
16417 as_bad (_(".set pop with no .set push"));
16420 /* If we're changing the reorder mode we need to handle
16421 delay slots correctly. */
16422 if (s->options.noreorder && ! mips_opts.noreorder)
16423 start_noreorder ();
16424 else if (! s->options.noreorder && mips_opts.noreorder)
16427 mips_opts = s->options;
16428 mips_opts_stack = s->next;
16434 type = parse_code_option (name);
16435 if (type == OPTION_TYPE_BAD)
16436 as_warn (_("tried to set unrecognized symbol: %s\n"), name);
16439 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
16440 registers based on what is supported by the arch/cpu. */
16441 if (type == OPTION_TYPE_ISA)
16443 switch (mips_opts.isa)
16448 /* MIPS I cannot support FPXX. */
16450 /* fall-through. */
16457 if (mips_opts.fp != 0)
16473 if (mips_opts.fp != 0)
16475 if (mips_opts.arch == CPU_R5900)
16482 as_bad (_("unknown ISA level %s"), name + 4);
16487 mips_check_options (&mips_opts, FALSE);
16489 mips_check_isa_supports_ases ();
16490 *input_line_pointer = ch;
16491 demand_empty_rest_of_line ();
16494 /* Handle the .module pseudo-op. */
16497 s_module (int ignore ATTRIBUTE_UNUSED)
16499 char *name = input_line_pointer, ch;
16501 while (!is_end_of_line[(unsigned char) *input_line_pointer])
16502 ++input_line_pointer;
16503 ch = *input_line_pointer;
16504 *input_line_pointer = '\0';
16506 if (!file_mips_opts_checked)
16508 if (parse_code_option (name) == OPTION_TYPE_BAD)
16509 as_bad (_(".module used with unrecognized symbol: %s\n"), name);
16511 /* Update module level settings from mips_opts. */
16512 file_mips_opts = mips_opts;
16515 as_bad (_(".module is not permitted after generating code"));
16517 *input_line_pointer = ch;
16518 demand_empty_rest_of_line ();
16521 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16522 .option pic2. It means to generate SVR4 PIC calls. */
16525 s_abicalls (int ignore ATTRIBUTE_UNUSED)
16527 mips_pic = SVR4_PIC;
16528 mips_abicalls = TRUE;
16530 if (g_switch_seen && g_switch_value != 0)
16531 as_warn (_("-G may not be used with SVR4 PIC code"));
16532 g_switch_value = 0;
16534 bfd_set_gp_size (stdoutput, 0);
16535 demand_empty_rest_of_line ();
16538 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16539 PIC code. It sets the $gp register for the function based on the
16540 function address, which is in the register named in the argument.
16541 This uses a relocation against _gp_disp, which is handled specially
16542 by the linker. The result is:
16543 lui $gp,%hi(_gp_disp)
16544 addiu $gp,$gp,%lo(_gp_disp)
16545 addu $gp,$gp,.cpload argument
16546 The .cpload argument is normally $25 == $t9.
16548 The -mno-shared option changes this to:
16549 lui $gp,%hi(__gnu_local_gp)
16550 addiu $gp,$gp,%lo(__gnu_local_gp)
16551 and the argument is ignored. This saves an instruction, but the
16552 resulting code is not position independent; it uses an absolute
16553 address for __gnu_local_gp. Thus code assembled with -mno-shared
16554 can go into an ordinary executable, but not into a shared library. */
16557 s_cpload (int ignore ATTRIBUTE_UNUSED)
16563 file_mips_check_options ();
16565 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16566 .cpload is ignored. */
16567 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16573 if (mips_opts.mips16)
16575 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16576 ignore_rest_of_line ();
16580 /* .cpload should be in a .set noreorder section. */
16581 if (mips_opts.noreorder == 0)
16582 as_warn (_(".cpload not in noreorder section"));
16584 reg = tc_get_register (0);
16586 /* If we need to produce a 64-bit address, we are better off using
16587 the default instruction sequence. */
16588 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
16590 ex.X_op = O_symbol;
16591 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
16593 ex.X_op_symbol = NULL;
16594 ex.X_add_number = 0;
16596 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16597 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16599 mips_mark_labels ();
16600 mips_assembling_insn = TRUE;
16603 macro_build_lui (&ex, mips_gp_register);
16604 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16605 mips_gp_register, BFD_RELOC_LO16);
16607 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
16608 mips_gp_register, reg);
16611 mips_assembling_insn = FALSE;
16612 demand_empty_rest_of_line ();
16615 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16616 .cpsetup $reg1, offset|$reg2, label
16618 If offset is given, this results in:
16619 sd $gp, offset($sp)
16620 lui $gp, %hi(%neg(%gp_rel(label)))
16621 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16622 daddu $gp, $gp, $reg1
16624 If $reg2 is given, this results in:
16626 lui $gp, %hi(%neg(%gp_rel(label)))
16627 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16628 daddu $gp, $gp, $reg1
16629 $reg1 is normally $25 == $t9.
16631 The -mno-shared option replaces the last three instructions with
16633 addiu $gp,$gp,%lo(_gp) */
16636 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
16638 expressionS ex_off;
16639 expressionS ex_sym;
16642 file_mips_check_options ();
16644 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16645 We also need NewABI support. */
16646 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16652 if (mips_opts.mips16)
16654 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16655 ignore_rest_of_line ();
16659 reg1 = tc_get_register (0);
16660 SKIP_WHITESPACE ();
16661 if (*input_line_pointer != ',')
16663 as_bad (_("missing argument separator ',' for .cpsetup"));
16667 ++input_line_pointer;
16668 SKIP_WHITESPACE ();
16669 if (*input_line_pointer == '$')
16671 mips_cpreturn_register = tc_get_register (0);
16672 mips_cpreturn_offset = -1;
16676 mips_cpreturn_offset = get_absolute_expression ();
16677 mips_cpreturn_register = -1;
16679 SKIP_WHITESPACE ();
16680 if (*input_line_pointer != ',')
16682 as_bad (_("missing argument separator ',' for .cpsetup"));
16686 ++input_line_pointer;
16687 SKIP_WHITESPACE ();
16688 expression (&ex_sym);
16690 mips_mark_labels ();
16691 mips_assembling_insn = TRUE;
16694 if (mips_cpreturn_register == -1)
16696 ex_off.X_op = O_constant;
16697 ex_off.X_add_symbol = NULL;
16698 ex_off.X_op_symbol = NULL;
16699 ex_off.X_add_number = mips_cpreturn_offset;
16701 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
16702 BFD_RELOC_LO16, SP);
16705 move_register (mips_cpreturn_register, mips_gp_register);
16707 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
16709 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
16710 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
16713 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
16714 mips_gp_register, -1, BFD_RELOC_GPREL16,
16715 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
16717 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
16718 mips_gp_register, reg1);
16724 ex.X_op = O_symbol;
16725 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
16726 ex.X_op_symbol = NULL;
16727 ex.X_add_number = 0;
16729 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16730 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16732 macro_build_lui (&ex, mips_gp_register);
16733 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16734 mips_gp_register, BFD_RELOC_LO16);
16739 mips_assembling_insn = FALSE;
16740 demand_empty_rest_of_line ();
16744 s_cplocal (int ignore ATTRIBUTE_UNUSED)
16746 file_mips_check_options ();
16748 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16749 .cplocal is ignored. */
16750 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16756 if (mips_opts.mips16)
16758 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16759 ignore_rest_of_line ();
16763 mips_gp_register = tc_get_register (0);
16764 demand_empty_rest_of_line ();
16767 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16768 offset from $sp. The offset is remembered, and after making a PIC
16769 call $gp is restored from that location. */
16772 s_cprestore (int ignore ATTRIBUTE_UNUSED)
16776 file_mips_check_options ();
16778 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16779 .cprestore is ignored. */
16780 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16786 if (mips_opts.mips16)
16788 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16789 ignore_rest_of_line ();
16793 mips_cprestore_offset = get_absolute_expression ();
16794 mips_cprestore_valid = 1;
16796 ex.X_op = O_constant;
16797 ex.X_add_symbol = NULL;
16798 ex.X_op_symbol = NULL;
16799 ex.X_add_number = mips_cprestore_offset;
16801 mips_mark_labels ();
16802 mips_assembling_insn = TRUE;
16805 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
16806 SP, HAVE_64BIT_ADDRESSES);
16809 mips_assembling_insn = FALSE;
16810 demand_empty_rest_of_line ();
16813 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16814 was given in the preceding .cpsetup, it results in:
16815 ld $gp, offset($sp)
16817 If a register $reg2 was given there, it results in:
16818 or $gp, $reg2, $0 */
16821 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
16825 file_mips_check_options ();
16827 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16828 We also need NewABI support. */
16829 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16835 if (mips_opts.mips16)
16837 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16838 ignore_rest_of_line ();
16842 mips_mark_labels ();
16843 mips_assembling_insn = TRUE;
16846 if (mips_cpreturn_register == -1)
16848 ex.X_op = O_constant;
16849 ex.X_add_symbol = NULL;
16850 ex.X_op_symbol = NULL;
16851 ex.X_add_number = mips_cpreturn_offset;
16853 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
16856 move_register (mips_gp_register, mips_cpreturn_register);
16860 mips_assembling_insn = FALSE;
16861 demand_empty_rest_of_line ();
16864 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16865 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16866 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16867 debug information or MIPS16 TLS. */
16870 s_tls_rel_directive (const size_t bytes, const char *dirstr,
16871 bfd_reloc_code_real_type rtype)
16878 if (ex.X_op != O_symbol)
16880 as_bad (_("unsupported use of %s"), dirstr);
16881 ignore_rest_of_line ();
16884 p = frag_more (bytes);
16885 md_number_to_chars (p, 0, bytes);
16886 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
16887 demand_empty_rest_of_line ();
16888 mips_clear_insn_labels ();
16891 /* Handle .dtprelword. */
16894 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
16896 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
16899 /* Handle .dtpreldword. */
16902 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
16904 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
16907 /* Handle .tprelword. */
16910 s_tprelword (int ignore ATTRIBUTE_UNUSED)
16912 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
16915 /* Handle .tpreldword. */
16918 s_tpreldword (int ignore ATTRIBUTE_UNUSED)
16920 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
16923 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16924 code. It sets the offset to use in gp_rel relocations. */
16927 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
16929 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16930 We also need NewABI support. */
16931 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16937 mips_gprel_offset = get_absolute_expression ();
16939 demand_empty_rest_of_line ();
16942 /* Handle the .gpword pseudo-op. This is used when generating PIC
16943 code. It generates a 32 bit GP relative reloc. */
16946 s_gpword (int ignore ATTRIBUTE_UNUSED)
16948 segment_info_type *si;
16949 struct insn_label_list *l;
16953 /* When not generating PIC code, this is treated as .word. */
16954 if (mips_pic != SVR4_PIC)
16960 si = seg_info (now_seg);
16961 l = si->label_list;
16962 mips_emit_delays ();
16964 mips_align (2, 0, l);
16967 mips_clear_insn_labels ();
16969 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16971 as_bad (_("unsupported use of .gpword"));
16972 ignore_rest_of_line ();
16976 md_number_to_chars (p, 0, 4);
16977 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16978 BFD_RELOC_GPREL32);
16980 demand_empty_rest_of_line ();
16984 s_gpdword (int ignore ATTRIBUTE_UNUSED)
16986 segment_info_type *si;
16987 struct insn_label_list *l;
16991 /* When not generating PIC code, this is treated as .dword. */
16992 if (mips_pic != SVR4_PIC)
16998 si = seg_info (now_seg);
16999 l = si->label_list;
17000 mips_emit_delays ();
17002 mips_align (3, 0, l);
17005 mips_clear_insn_labels ();
17007 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17009 as_bad (_("unsupported use of .gpdword"));
17010 ignore_rest_of_line ();
17014 md_number_to_chars (p, 0, 8);
17015 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17016 BFD_RELOC_GPREL32)->fx_tcbit = 1;
17018 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17019 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
17020 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
17022 demand_empty_rest_of_line ();
17025 /* Handle the .ehword pseudo-op. This is used when generating unwinding
17026 tables. It generates a R_MIPS_EH reloc. */
17029 s_ehword (int ignore ATTRIBUTE_UNUSED)
17034 mips_emit_delays ();
17037 mips_clear_insn_labels ();
17039 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17041 as_bad (_("unsupported use of .ehword"));
17042 ignore_rest_of_line ();
17046 md_number_to_chars (p, 0, 4);
17047 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17048 BFD_RELOC_32_PCREL);
17050 demand_empty_rest_of_line ();
17053 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17054 tables in SVR4 PIC code. */
17057 s_cpadd (int ignore ATTRIBUTE_UNUSED)
17061 file_mips_check_options ();
17063 /* This is ignored when not generating SVR4 PIC code. */
17064 if (mips_pic != SVR4_PIC)
17070 mips_mark_labels ();
17071 mips_assembling_insn = TRUE;
17073 /* Add $gp to the register named as an argument. */
17075 reg = tc_get_register (0);
17076 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
17079 mips_assembling_insn = FALSE;
17080 demand_empty_rest_of_line ();
17083 /* Handle the .insn pseudo-op. This marks instruction labels in
17084 mips16/micromips mode. This permits the linker to handle them specially,
17085 such as generating jalx instructions when needed. We also make
17086 them odd for the duration of the assembly, in order to generate the
17087 right sort of code. We will make them even in the adjust_symtab
17088 routine, while leaving them marked. This is convenient for the
17089 debugger and the disassembler. The linker knows to make them odd
17093 s_insn (int ignore ATTRIBUTE_UNUSED)
17095 file_mips_check_options ();
17096 file_ase_mips16 |= mips_opts.mips16;
17097 file_ase_micromips |= mips_opts.micromips;
17099 mips_mark_labels ();
17101 demand_empty_rest_of_line ();
17104 /* Handle the .nan pseudo-op. */
17107 s_nan (int ignore ATTRIBUTE_UNUSED)
17109 static const char str_legacy[] = "legacy";
17110 static const char str_2008[] = "2008";
17113 for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++);
17115 if (i == sizeof (str_2008) - 1
17116 && memcmp (input_line_pointer, str_2008, i) == 0)
17118 else if (i == sizeof (str_legacy) - 1
17119 && memcmp (input_line_pointer, str_legacy, i) == 0)
17121 if (ISA_HAS_LEGACY_NAN (file_mips_opts.isa))
17124 as_bad (_("`%s' does not support legacy NaN"),
17125 mips_cpu_info_from_isa (file_mips_opts.isa)->name);
17128 as_bad (_("bad .nan directive"));
17130 input_line_pointer += i;
17131 demand_empty_rest_of_line ();
17134 /* Handle a .stab[snd] directive. Ideally these directives would be
17135 implemented in a transparent way, so that removing them would not
17136 have any effect on the generated instructions. However, s_stab
17137 internally changes the section, so in practice we need to decide
17138 now whether the preceding label marks compressed code. We do not
17139 support changing the compression mode of a label after a .stab*
17140 directive, such as in:
17146 so the current mode wins. */
17149 s_mips_stab (int type)
17151 file_mips_check_options ();
17152 mips_mark_labels ();
17156 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17159 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
17166 c = get_symbol_name (&name);
17167 symbolP = symbol_find_or_make (name);
17168 S_SET_WEAK (symbolP);
17169 *input_line_pointer = c;
17171 SKIP_WHITESPACE_AFTER_NAME ();
17173 if (! is_end_of_line[(unsigned char) *input_line_pointer])
17175 if (S_IS_DEFINED (symbolP))
17177 as_bad (_("ignoring attempt to redefine symbol %s"),
17178 S_GET_NAME (symbolP));
17179 ignore_rest_of_line ();
17183 if (*input_line_pointer == ',')
17185 ++input_line_pointer;
17186 SKIP_WHITESPACE ();
17190 if (exp.X_op != O_symbol)
17192 as_bad (_("bad .weakext directive"));
17193 ignore_rest_of_line ();
17196 symbol_set_value_expression (symbolP, &exp);
17199 demand_empty_rest_of_line ();
17202 /* Parse a register string into a number. Called from the ECOFF code
17203 to parse .frame. The argument is non-zero if this is the frame
17204 register, so that we can record it in mips_frame_reg. */
17207 tc_get_register (int frame)
17211 SKIP_WHITESPACE ();
17212 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
17216 mips_frame_reg = reg != 0 ? reg : SP;
17217 mips_frame_reg_valid = 1;
17218 mips_cprestore_valid = 0;
17224 md_section_align (asection *seg, valueT addr)
17226 int align = bfd_get_section_alignment (stdoutput, seg);
17228 /* We don't need to align ELF sections to the full alignment.
17229 However, Irix 5 may prefer that we align them at least to a 16
17230 byte boundary. We don't bother to align the sections if we
17231 are targeted for an embedded system. */
17232 if (strncmp (TARGET_OS, "elf", 3) == 0)
17237 return ((addr + (1 << align) - 1) & -(1 << align));
17240 /* Utility routine, called from above as well. If called while the
17241 input file is still being read, it's only an approximation. (For
17242 example, a symbol may later become defined which appeared to be
17243 undefined earlier.) */
17246 nopic_need_relax (symbolS *sym, int before_relaxing)
17251 if (g_switch_value > 0)
17253 const char *symname;
17256 /* Find out whether this symbol can be referenced off the $gp
17257 register. It can be if it is smaller than the -G size or if
17258 it is in the .sdata or .sbss section. Certain symbols can
17259 not be referenced off the $gp, although it appears as though
17261 symname = S_GET_NAME (sym);
17262 if (symname != (const char *) NULL
17263 && (strcmp (symname, "eprol") == 0
17264 || strcmp (symname, "etext") == 0
17265 || strcmp (symname, "_gp") == 0
17266 || strcmp (symname, "edata") == 0
17267 || strcmp (symname, "_fbss") == 0
17268 || strcmp (symname, "_fdata") == 0
17269 || strcmp (symname, "_ftext") == 0
17270 || strcmp (symname, "end") == 0
17271 || strcmp (symname, "_gp_disp") == 0))
17273 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
17275 #ifndef NO_ECOFF_DEBUGGING
17276 || (symbol_get_obj (sym)->ecoff_extern_size != 0
17277 && (symbol_get_obj (sym)->ecoff_extern_size
17278 <= g_switch_value))
17280 /* We must defer this decision until after the whole
17281 file has been read, since there might be a .extern
17282 after the first use of this symbol. */
17283 || (before_relaxing
17284 #ifndef NO_ECOFF_DEBUGGING
17285 && symbol_get_obj (sym)->ecoff_extern_size == 0
17287 && S_GET_VALUE (sym) == 0)
17288 || (S_GET_VALUE (sym) != 0
17289 && S_GET_VALUE (sym) <= g_switch_value)))
17293 const char *segname;
17295 segname = segment_name (S_GET_SEGMENT (sym));
17296 gas_assert (strcmp (segname, ".lit8") != 0
17297 && strcmp (segname, ".lit4") != 0);
17298 change = (strcmp (segname, ".sdata") != 0
17299 && strcmp (segname, ".sbss") != 0
17300 && strncmp (segname, ".sdata.", 7) != 0
17301 && strncmp (segname, ".sbss.", 6) != 0
17302 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
17303 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
17308 /* We are not optimizing for the $gp register. */
17313 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17316 pic_need_relax (symbolS *sym)
17320 /* Handle the case of a symbol equated to another symbol. */
17321 while (symbol_equated_reloc_p (sym))
17325 /* It's possible to get a loop here in a badly written program. */
17326 n = symbol_get_value_expression (sym)->X_add_symbol;
17332 if (symbol_section_p (sym))
17335 symsec = S_GET_SEGMENT (sym);
17337 /* This must duplicate the test in adjust_reloc_syms. */
17338 return (!bfd_is_und_section (symsec)
17339 && !bfd_is_abs_section (symsec)
17340 && !bfd_is_com_section (symsec)
17341 /* A global or weak symbol is treated as external. */
17342 && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym)));
17345 /* Given a MIPS16 variant frag FRAGP and PC-relative operand PCREL_OP
17346 convert a section-relative value VAL to the equivalent PC-relative
17350 mips16_pcrel_val (fragS *fragp, const struct mips_pcrel_operand *pcrel_op,
17351 offsetT val, long stretch)
17356 gas_assert (pcrel_op->root.root.type == OP_PCREL);
17358 sym_frag = symbol_get_frag (fragp->fr_symbol);
17360 /* If the relax_marker of the symbol fragment differs from the
17361 relax_marker of this fragment, we have not yet adjusted the
17362 symbol fragment fr_address. We want to add in STRETCH in
17363 order to get a better estimate of the address. This
17364 particularly matters because of the shift bits. */
17365 if (stretch != 0 && sym_frag->relax_marker != fragp->relax_marker)
17369 /* Adjust stretch for any alignment frag. Note that if have
17370 been expanding the earlier code, the symbol may be
17371 defined in what appears to be an earlier frag. FIXME:
17372 This doesn't handle the fr_subtype field, which specifies
17373 a maximum number of bytes to skip when doing an
17375 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
17377 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
17380 stretch = -(-stretch & ~((1 << (int) f->fr_offset) - 1));
17382 stretch &= ~((1 << (int) f->fr_offset) - 1);
17391 addr = fragp->fr_address + fragp->fr_fix;
17393 /* The base address rules are complicated. The base address of
17394 a branch is the following instruction. The base address of a
17395 PC relative load or add is the instruction itself, but if it
17396 is in a delay slot (in which case it can not be extended) use
17397 the address of the instruction whose delay slot it is in. */
17398 if (pcrel_op->include_isa_bit)
17402 /* If we are currently assuming that this frag should be
17403 extended, then the current address is two bytes higher. */
17404 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17407 /* Ignore the low bit in the target, since it will be set
17408 for a text label. */
17411 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17413 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17416 val -= addr & -(1 << pcrel_op->align_log2);
17421 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17422 extended opcode. SEC is the section the frag is in. */
17425 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
17427 const struct mips_int_operand *operand;
17432 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
17434 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17437 symsec = S_GET_SEGMENT (fragp->fr_symbol);
17438 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
17439 operand = mips16_immed_operand (type, FALSE);
17440 if (S_FORCE_RELOC (fragp->fr_symbol, TRUE)
17441 || (operand->root.type == OP_PCREL
17443 : !bfd_is_abs_section (symsec)))
17446 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17448 if (operand->root.type == OP_PCREL)
17450 const struct mips_pcrel_operand *pcrel_op;
17453 if (RELAX_MIPS16_ALWAYS_EXTENDED (fragp->fr_subtype))
17456 pcrel_op = (const struct mips_pcrel_operand *) operand;
17457 val = mips16_pcrel_val (fragp, pcrel_op, val, stretch);
17459 /* If any of the shifted bits are set, we must use an extended
17460 opcode. If the address depends on the size of this
17461 instruction, this can lead to a loop, so we arrange to always
17462 use an extended opcode. */
17463 if ((val & ((1 << operand->shift) - 1)) != 0)
17465 fragp->fr_subtype =
17466 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp->fr_subtype);
17470 /* If we are about to mark a frag as extended because the value
17471 is precisely the next value above maxtiny, then there is a
17472 chance of an infinite loop as in the following code:
17477 In this case when the la is extended, foo is 0x3fc bytes
17478 away, so the la can be shrunk, but then foo is 0x400 away, so
17479 the la must be extended. To avoid this loop, we mark the
17480 frag as extended if it was small, and is about to become
17481 extended with the next value above maxtiny. */
17482 maxtiny = mips_int_operand_max (operand);
17483 if (val == maxtiny + (1 << operand->shift)
17484 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17486 fragp->fr_subtype =
17487 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp->fr_subtype);
17492 return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val);
17495 /* Given a MIPS16 variant frag FRAGP, return non-zero if it needs
17496 macro expansion. SEC is the section the frag is in. We only
17497 support PC-relative instructions (LA, DLA, LW, LD) here, in
17498 non-PIC code using 32-bit addressing. */
17501 mips16_macro_frag (fragS *fragp, asection *sec, long stretch)
17503 const struct mips_pcrel_operand *pcrel_op;
17504 const struct mips_int_operand *operand;
17509 gas_assert (!RELAX_MIPS16_USER_SMALL (fragp->fr_subtype));
17511 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17513 if (!RELAX_MIPS16_SYM32 (fragp->fr_subtype))
17516 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
17522 symsec = S_GET_SEGMENT (fragp->fr_symbol);
17523 if (bfd_is_abs_section (symsec))
17525 if (RELAX_MIPS16_PIC (fragp->fr_subtype))
17527 if (S_FORCE_RELOC (fragp->fr_symbol, TRUE) || sec != symsec)
17530 operand = mips16_immed_operand (type, TRUE);
17531 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17532 pcrel_op = (const struct mips_pcrel_operand *) operand;
17533 val = mips16_pcrel_val (fragp, pcrel_op, val, stretch);
17535 return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val);
17542 /* Compute the length of a branch sequence, and adjust the
17543 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17544 worst-case length is computed, with UPDATE being used to indicate
17545 whether an unconditional (-1), branch-likely (+1) or regular (0)
17546 branch is to be computed. */
17548 relaxed_branch_length (fragS *fragp, asection *sec, int update)
17550 bfd_boolean toofar;
17554 && S_IS_DEFINED (fragp->fr_symbol)
17555 && !S_IS_WEAK (fragp->fr_symbol)
17556 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17561 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17563 addr = fragp->fr_address + fragp->fr_fix + 4;
17567 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
17570 /* If the symbol is not defined or it's in a different segment,
17571 we emit the long sequence. */
17574 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17576 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
17577 RELAX_BRANCH_PIC (fragp->fr_subtype),
17578 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
17579 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
17580 RELAX_BRANCH_LINK (fragp->fr_subtype),
17586 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
17589 if (!fragp || RELAX_BRANCH_PIC (fragp->fr_subtype))
17591 /* Additional space for PIC loading of target address. */
17593 if (mips_opts.isa == ISA_MIPS1)
17594 /* Additional space for $at-stabilizing nop. */
17598 /* If branch is conditional. */
17599 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
17606 /* Get a FRAG's branch instruction delay slot size, either from the
17607 short-delay-slot bit of a branch-and-link instruction if AL is TRUE,
17608 or SHORT_INSN_SIZE otherwise. */
17611 frag_branch_delay_slot_size (fragS *fragp, bfd_boolean al, int short_insn_size)
17613 char *buf = fragp->fr_literal + fragp->fr_fix;
17616 return (read_compressed_insn (buf, 4) & 0x02000000) ? 2 : 4;
17618 return short_insn_size;
17621 /* Compute the length of a branch sequence, and adjust the
17622 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17623 worst-case length is computed, with UPDATE being used to indicate
17624 whether an unconditional (-1), or regular (0) branch is to be
17628 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
17630 bfd_boolean insn32 = TRUE;
17631 bfd_boolean nods = TRUE;
17632 bfd_boolean pic = TRUE;
17633 bfd_boolean al = TRUE;
17634 int short_insn_size;
17635 bfd_boolean toofar;
17640 insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype);
17641 nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype);
17642 pic = RELAX_MICROMIPS_PIC (fragp->fr_subtype);
17643 al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
17645 short_insn_size = insn32 ? 4 : 2;
17648 && S_IS_DEFINED (fragp->fr_symbol)
17649 && !S_IS_WEAK (fragp->fr_symbol)
17650 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17655 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17656 /* Ignore the low bit in the target, since it will be set
17657 for a text label. */
17658 if ((val & 1) != 0)
17661 addr = fragp->fr_address + fragp->fr_fix + 4;
17665 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
17668 /* If the symbol is not defined or it's in a different segment,
17669 we emit the long sequence. */
17672 if (fragp && update
17673 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17674 fragp->fr_subtype = (toofar
17675 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
17676 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
17681 bfd_boolean compact_known = fragp != NULL;
17682 bfd_boolean compact = FALSE;
17683 bfd_boolean uncond;
17687 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17688 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
17691 uncond = update < 0;
17693 /* If label is out of range, we turn branch <br>:
17695 <br> label # 4 bytes
17702 # compact && (!PIC || insn32)
17705 if ((!pic || insn32) && (!compact_known || compact))
17706 length += short_insn_size;
17708 /* If assembling PIC code, we further turn:
17714 lw/ld at, %got(label)(gp) # 4 bytes
17715 d/addiu at, %lo(label) # 4 bytes
17716 jr/c at # 2/4 bytes
17719 length += 4 + short_insn_size;
17721 /* Add an extra nop if the jump has no compact form and we need
17722 to fill the delay slot. */
17723 if ((!pic || al) && nods)
17725 ? frag_branch_delay_slot_size (fragp, al, short_insn_size)
17726 : short_insn_size);
17728 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17730 <brneg> 0f # 4 bytes
17731 nop # 2/4 bytes if !compact
17734 length += (compact_known && compact) ? 4 : 4 + short_insn_size;
17738 /* Add an extra nop to fill the delay slot. */
17739 gas_assert (fragp);
17740 length += frag_branch_delay_slot_size (fragp, al, short_insn_size);
17746 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17747 bit accordingly. */
17750 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
17752 bfd_boolean toofar;
17755 && S_IS_DEFINED (fragp->fr_symbol)
17756 && !S_IS_WEAK (fragp->fr_symbol)
17757 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17763 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17764 /* Ignore the low bit in the target, since it will be set
17765 for a text label. */
17766 if ((val & 1) != 0)
17769 /* Assume this is a 2-byte branch. */
17770 addr = fragp->fr_address + fragp->fr_fix + 2;
17772 /* We try to avoid the infinite loop by not adding 2 more bytes for
17777 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17779 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
17780 else if (type == 'E')
17781 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
17786 /* If the symbol is not defined or it's in a different segment,
17787 we emit a normal 32-bit branch. */
17790 if (fragp && update
17791 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17793 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
17794 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
17802 /* Estimate the size of a frag before relaxing. Unless this is the
17803 mips16, we are not really relaxing here, and the final size is
17804 encoded in the subtype information. For the mips16, we have to
17805 decide whether we are using an extended opcode or not. */
17808 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
17812 if (RELAX_BRANCH_P (fragp->fr_subtype))
17815 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
17817 return fragp->fr_var;
17820 if (RELAX_MIPS16_P (fragp->fr_subtype))
17822 /* We don't want to modify the EXTENDED bit here; it might get us
17823 into infinite loops. We change it only in mips_relax_frag(). */
17824 if (RELAX_MIPS16_MACRO (fragp->fr_subtype))
17825 return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 8 : 12;
17827 return RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2;
17830 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17834 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17835 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
17836 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17837 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
17838 fragp->fr_var = length;
17843 if (mips_pic == VXWORKS_PIC)
17844 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17846 else if (RELAX_PIC (fragp->fr_subtype))
17847 change = pic_need_relax (fragp->fr_symbol);
17849 change = nopic_need_relax (fragp->fr_symbol, 0);
17853 fragp->fr_subtype |= RELAX_USE_SECOND;
17854 return -RELAX_FIRST (fragp->fr_subtype);
17857 return -RELAX_SECOND (fragp->fr_subtype);
17860 /* This is called to see whether a reloc against a defined symbol
17861 should be converted into a reloc against a section. */
17864 mips_fix_adjustable (fixS *fixp)
17866 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
17867 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17870 if (fixp->fx_addsy == NULL)
17873 /* Allow relocs used for EH tables. */
17874 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
17877 /* If symbol SYM is in a mergeable section, relocations of the form
17878 SYM + 0 can usually be made section-relative. The mergeable data
17879 is then identified by the section offset rather than by the symbol.
17881 However, if we're generating REL LO16 relocations, the offset is split
17882 between the LO16 and partnering high part relocation. The linker will
17883 need to recalculate the complete offset in order to correctly identify
17886 The linker has traditionally not looked for the partnering high part
17887 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17888 placed anywhere. Rather than break backwards compatibility by changing
17889 this, it seems better not to force the issue, and instead keep the
17890 original symbol. This will work with either linker behavior. */
17891 if ((lo16_reloc_p (fixp->fx_r_type)
17892 || reloc_needs_lo_p (fixp->fx_r_type))
17893 && HAVE_IN_PLACE_ADDENDS
17894 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
17897 /* There is no place to store an in-place offset for JALR relocations. */
17898 if (jalr_reloc_p (fixp->fx_r_type) && HAVE_IN_PLACE_ADDENDS)
17901 /* Likewise an in-range offset of limited PC-relative relocations may
17902 overflow the in-place relocatable field if recalculated against the
17903 start address of the symbol's containing section.
17905 Also, PC relative relocations for MIPS R6 need to be symbol rather than
17906 section relative to allow linker relaxations to be performed later on. */
17907 if (limited_pcrel_reloc_p (fixp->fx_r_type)
17908 && (HAVE_IN_PLACE_ADDENDS || ISA_IS_R6 (file_mips_opts.isa)))
17911 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17912 to a floating-point stub. The same is true for non-R_MIPS16_26
17913 relocations against MIPS16 functions; in this case, the stub becomes
17914 the function's canonical address.
17916 Floating-point stubs are stored in unique .mips16.call.* or
17917 .mips16.fn.* sections. If a stub T for function F is in section S,
17918 the first relocation in section S must be against F; this is how the
17919 linker determines the target function. All relocations that might
17920 resolve to T must also be against F. We therefore have the following
17921 restrictions, which are given in an intentionally-redundant way:
17923 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17926 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17927 if that stub might be used.
17929 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17932 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17933 that stub might be used.
17935 There is a further restriction:
17937 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17938 R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2,
17939 R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1,
17940 R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1)
17941 against MIPS16 or microMIPS symbols because we need to keep the
17942 MIPS16 or microMIPS symbol for the purpose of mode mismatch
17943 detection and JAL or BAL to JALX instruction conversion in the
17946 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17947 against a MIPS16 symbol. We deal with (5) by additionally leaving
17948 alone any jump and branch relocations against a microMIPS symbol.
17950 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17951 relocation against some symbol R, no relocation against R may be
17952 reduced. (Note that this deals with (2) as well as (1) because
17953 relocations against global symbols will never be reduced on ELF
17954 targets.) This approach is a little simpler than trying to detect
17955 stub sections, and gives the "all or nothing" per-symbol consistency
17956 that we have for MIPS16 symbols. */
17957 if (fixp->fx_subsy == NULL
17958 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
17959 || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
17960 && (jmp_reloc_p (fixp->fx_r_type)
17961 || b_reloc_p (fixp->fx_r_type)))
17962 || *symbol_get_tc (fixp->fx_addsy)))
17968 /* Translate internal representation of relocation info to BFD target
17972 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
17974 static arelent *retval[4];
17976 bfd_reloc_code_real_type code;
17978 memset (retval, 0, sizeof(retval));
17979 reloc = retval[0] = XCNEW (arelent);
17980 reloc->sym_ptr_ptr = XNEW (asymbol *);
17981 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
17982 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
17984 if (fixp->fx_pcrel)
17986 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
17987 || fixp->fx_r_type == BFD_RELOC_MIPS16_16_PCREL_S1
17988 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
17989 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
17990 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
17991 || fixp->fx_r_type == BFD_RELOC_32_PCREL
17992 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
17993 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2
17994 || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3
17995 || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2
17996 || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL
17997 || fixp->fx_r_type == BFD_RELOC_LO16_PCREL);
17999 /* At this point, fx_addnumber is "symbol offset - pcrel address".
18000 Relocations want only the symbol offset. */
18001 switch (fixp->fx_r_type)
18003 case BFD_RELOC_MIPS_18_PCREL_S3:
18004 reloc->addend = fixp->fx_addnumber + (reloc->address & ~7);
18007 reloc->addend = fixp->fx_addnumber + reloc->address;
18011 else if (HAVE_IN_PLACE_ADDENDS
18012 && fixp->fx_r_type == BFD_RELOC_MICROMIPS_JMP
18013 && (read_compressed_insn (fixp->fx_frag->fr_literal
18014 + fixp->fx_where, 4) >> 26) == 0x3c)
18016 /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place
18017 addend accordingly. */
18018 reloc->addend = fixp->fx_addnumber >> 1;
18021 reloc->addend = fixp->fx_addnumber;
18023 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
18024 entry to be used in the relocation's section offset. */
18025 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
18027 reloc->address = reloc->addend;
18031 code = fixp->fx_r_type;
18033 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
18034 if (reloc->howto == NULL)
18036 as_bad_where (fixp->fx_file, fixp->fx_line,
18037 _("cannot represent %s relocation in this object file"
18039 bfd_get_reloc_code_name (code));
18046 /* Relax a machine dependent frag. This returns the amount by which
18047 the current size of the frag should change. */
18050 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
18052 if (RELAX_BRANCH_P (fragp->fr_subtype))
18054 offsetT old_var = fragp->fr_var;
18056 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
18058 return fragp->fr_var - old_var;
18061 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
18063 offsetT old_var = fragp->fr_var;
18064 offsetT new_var = 4;
18066 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
18067 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
18068 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
18069 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
18070 fragp->fr_var = new_var;
18072 return new_var - old_var;
18075 if (! RELAX_MIPS16_P (fragp->fr_subtype))
18078 if (!mips16_extended_frag (fragp, sec, stretch))
18080 if (RELAX_MIPS16_MACRO (fragp->fr_subtype))
18082 fragp->fr_subtype = RELAX_MIPS16_CLEAR_MACRO (fragp->fr_subtype);
18083 return RELAX_MIPS16_E2 (fragp->fr_subtype) ? -6 : -10;
18085 else if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18087 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
18093 else if (!mips16_macro_frag (fragp, sec, stretch))
18095 if (RELAX_MIPS16_MACRO (fragp->fr_subtype))
18097 fragp->fr_subtype = RELAX_MIPS16_CLEAR_MACRO (fragp->fr_subtype);
18098 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
18099 return RELAX_MIPS16_E2 (fragp->fr_subtype) ? -4 : -8;
18101 else if (!RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18103 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
18111 if (RELAX_MIPS16_MACRO (fragp->fr_subtype))
18113 else if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18115 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
18116 fragp->fr_subtype = RELAX_MIPS16_MARK_MACRO (fragp->fr_subtype);
18117 return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 4 : 8;
18121 fragp->fr_subtype = RELAX_MIPS16_MARK_MACRO (fragp->fr_subtype);
18122 return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 6 : 10;
18129 /* Convert a machine dependent frag. */
18132 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
18134 if (RELAX_BRANCH_P (fragp->fr_subtype))
18137 unsigned long insn;
18140 buf = fragp->fr_literal + fragp->fr_fix;
18141 insn = read_insn (buf);
18143 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
18145 /* We generate a fixup instead of applying it right now
18146 because, if there are linker relaxations, we're going to
18147 need the relocations. */
18148 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18149 fragp->fr_symbol, fragp->fr_offset,
18150 TRUE, BFD_RELOC_16_PCREL_S2);
18151 fixp->fx_file = fragp->fr_file;
18152 fixp->fx_line = fragp->fr_line;
18154 buf = write_insn (buf, insn);
18160 as_warn_where (fragp->fr_file, fragp->fr_line,
18161 _("relaxed out-of-range branch into a jump"));
18163 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
18166 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18168 /* Reverse the branch. */
18169 switch ((insn >> 28) & 0xf)
18172 if ((insn & 0xff000000) == 0x47000000
18173 || (insn & 0xff600000) == 0x45600000)
18175 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
18176 reversed by tweaking bit 23. */
18177 insn ^= 0x00800000;
18181 /* bc[0-3][tf]l? instructions can have the condition
18182 reversed by tweaking a single TF bit, and their
18183 opcodes all have 0x4???????. */
18184 gas_assert ((insn & 0xf3e00000) == 0x41000000);
18185 insn ^= 0x00010000;
18190 /* bltz 0x04000000 bgez 0x04010000
18191 bltzal 0x04100000 bgezal 0x04110000 */
18192 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
18193 insn ^= 0x00010000;
18197 /* beq 0x10000000 bne 0x14000000
18198 blez 0x18000000 bgtz 0x1c000000 */
18199 insn ^= 0x04000000;
18207 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
18209 /* Clear the and-link bit. */
18210 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
18212 /* bltzal 0x04100000 bgezal 0x04110000
18213 bltzall 0x04120000 bgezall 0x04130000 */
18214 insn &= ~0x00100000;
18217 /* Branch over the branch (if the branch was likely) or the
18218 full jump (not likely case). Compute the offset from the
18219 current instruction to branch to. */
18220 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18224 /* How many bytes in instructions we've already emitted? */
18225 i = buf - fragp->fr_literal - fragp->fr_fix;
18226 /* How many bytes in instructions from here to the end? */
18227 i = fragp->fr_var - i;
18229 /* Convert to instruction count. */
18231 /* Branch counts from the next instruction. */
18234 /* Branch over the jump. */
18235 buf = write_insn (buf, insn);
18238 buf = write_insn (buf, 0);
18240 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18242 /* beql $0, $0, 2f */
18244 /* Compute the PC offset from the current instruction to
18245 the end of the variable frag. */
18246 /* How many bytes in instructions we've already emitted? */
18247 i = buf - fragp->fr_literal - fragp->fr_fix;
18248 /* How many bytes in instructions from here to the end? */
18249 i = fragp->fr_var - i;
18250 /* Convert to instruction count. */
18252 /* Don't decrement i, because we want to branch over the
18256 buf = write_insn (buf, insn);
18257 buf = write_insn (buf, 0);
18261 if (!RELAX_BRANCH_PIC (fragp->fr_subtype))
18264 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
18265 ? 0x0c000000 : 0x08000000);
18267 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18268 fragp->fr_symbol, fragp->fr_offset,
18269 FALSE, BFD_RELOC_MIPS_JMP);
18270 fixp->fx_file = fragp->fr_file;
18271 fixp->fx_line = fragp->fr_line;
18273 buf = write_insn (buf, insn);
18277 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
18279 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18280 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
18281 insn |= at << OP_SH_RT;
18283 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18284 fragp->fr_symbol, fragp->fr_offset,
18285 FALSE, BFD_RELOC_MIPS_GOT16);
18286 fixp->fx_file = fragp->fr_file;
18287 fixp->fx_line = fragp->fr_line;
18289 buf = write_insn (buf, insn);
18291 if (mips_opts.isa == ISA_MIPS1)
18293 buf = write_insn (buf, 0);
18295 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18296 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
18297 insn |= at << OP_SH_RS | at << OP_SH_RT;
18299 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18300 fragp->fr_symbol, fragp->fr_offset,
18301 FALSE, BFD_RELOC_LO16);
18302 fixp->fx_file = fragp->fr_file;
18303 fixp->fx_line = fragp->fr_line;
18305 buf = write_insn (buf, insn);
18308 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
18312 insn |= at << OP_SH_RS;
18314 buf = write_insn (buf, insn);
18318 fragp->fr_fix += fragp->fr_var;
18319 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18323 /* Relax microMIPS branches. */
18324 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
18326 char *buf = fragp->fr_literal + fragp->fr_fix;
18327 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
18328 bfd_boolean insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype);
18329 bfd_boolean nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype);
18330 bfd_boolean pic = RELAX_MICROMIPS_PIC (fragp->fr_subtype);
18331 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
18332 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
18333 bfd_boolean short_ds;
18334 unsigned long insn;
18337 fragp->fr_fix += fragp->fr_var;
18339 /* Handle 16-bit branches that fit or are forced to fit. */
18340 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
18342 /* We generate a fixup instead of applying it right now,
18343 because if there is linker relaxation, we're going to
18344 need the relocations. */
18348 fixp = fix_new (fragp, buf - fragp->fr_literal, 2,
18349 fragp->fr_symbol, fragp->fr_offset,
18350 TRUE, BFD_RELOC_MICROMIPS_10_PCREL_S1);
18353 fixp = fix_new (fragp, buf - fragp->fr_literal, 2,
18354 fragp->fr_symbol, fragp->fr_offset,
18355 TRUE, BFD_RELOC_MICROMIPS_7_PCREL_S1);
18361 fixp->fx_file = fragp->fr_file;
18362 fixp->fx_line = fragp->fr_line;
18364 /* These relocations can have an addend that won't fit in
18366 fixp->fx_no_overflow = 1;
18371 /* Handle 32-bit branches that fit or are forced to fit. */
18372 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18373 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18375 /* We generate a fixup instead of applying it right now,
18376 because if there is linker relaxation, we're going to
18377 need the relocations. */
18378 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18379 fragp->fr_symbol, fragp->fr_offset,
18380 TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1);
18381 fixp->fx_file = fragp->fr_file;
18382 fixp->fx_line = fragp->fr_line;
18386 insn = read_compressed_insn (buf, 4);
18391 /* Check the short-delay-slot bit. */
18392 if (!al || (insn & 0x02000000) != 0)
18393 buf = write_compressed_insn (buf, 0x0c00, 2);
18395 buf = write_compressed_insn (buf, 0x00000000, 4);
18398 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18403 /* Relax 16-bit branches to 32-bit branches. */
18406 insn = read_compressed_insn (buf, 2);
18408 if ((insn & 0xfc00) == 0xcc00) /* b16 */
18409 insn = 0x94000000; /* beq */
18410 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18412 unsigned long regno;
18414 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
18415 regno = micromips_to_32_reg_d_map [regno];
18416 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
18417 insn |= regno << MICROMIPSOP_SH_RS;
18422 /* Nothing else to do, just write it out. */
18423 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18424 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18426 buf = write_compressed_insn (buf, insn, 4);
18428 buf = write_compressed_insn (buf, 0x0c00, 2);
18429 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18434 insn = read_compressed_insn (buf, 4);
18436 /* Relax 32-bit branches to a sequence of instructions. */
18437 as_warn_where (fragp->fr_file, fragp->fr_line,
18438 _("relaxed out-of-range branch into a jump"));
18440 /* Set the short-delay-slot bit. */
18441 short_ds = !al || (insn & 0x02000000) != 0;
18443 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
18447 /* Reverse the branch. */
18448 if ((insn & 0xfc000000) == 0x94000000 /* beq */
18449 || (insn & 0xfc000000) == 0xb4000000) /* bne */
18450 insn ^= 0x20000000;
18451 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
18452 || (insn & 0xffe00000) == 0x40400000 /* bgez */
18453 || (insn & 0xffe00000) == 0x40800000 /* blez */
18454 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
18455 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
18456 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
18457 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
18458 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
18459 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
18460 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
18461 insn ^= 0x00400000;
18462 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
18463 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
18464 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
18465 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
18466 insn ^= 0x00200000;
18467 else if ((insn & 0xff000000) == 0x83000000 /* BZ.df
18469 || (insn & 0xff600000) == 0x81600000) /* BZ.V
18471 insn ^= 0x00800000;
18477 /* Clear the and-link and short-delay-slot bits. */
18478 gas_assert ((insn & 0xfda00000) == 0x40200000);
18480 /* bltzal 0x40200000 bgezal 0x40600000 */
18481 /* bltzals 0x42200000 bgezals 0x42600000 */
18482 insn &= ~0x02200000;
18485 /* Make a label at the end for use with the branch. */
18486 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
18487 micromips_label_inc ();
18488 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
18491 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE,
18492 BFD_RELOC_MICROMIPS_16_PCREL_S1);
18493 fixp->fx_file = fragp->fr_file;
18494 fixp->fx_line = fragp->fr_line;
18496 /* Branch over the jump. */
18497 buf = write_compressed_insn (buf, insn, 4);
18503 buf = write_compressed_insn (buf, 0x00000000, 4);
18505 buf = write_compressed_insn (buf, 0x0c00, 2);
18511 unsigned long jal = (short_ds || nods
18512 ? 0x74000000 : 0xf4000000); /* jal/s */
18514 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18515 insn = al ? jal : 0xd4000000;
18517 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18518 fragp->fr_symbol, fragp->fr_offset,
18519 FALSE, BFD_RELOC_MICROMIPS_JMP);
18520 fixp->fx_file = fragp->fr_file;
18521 fixp->fx_line = fragp->fr_line;
18523 buf = write_compressed_insn (buf, insn, 4);
18525 if (compact || nods)
18529 buf = write_compressed_insn (buf, 0x00000000, 4);
18531 buf = write_compressed_insn (buf, 0x0c00, 2);
18536 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
18538 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18539 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
18540 insn |= at << MICROMIPSOP_SH_RT;
18542 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18543 fragp->fr_symbol, fragp->fr_offset,
18544 FALSE, BFD_RELOC_MICROMIPS_GOT16);
18545 fixp->fx_file = fragp->fr_file;
18546 fixp->fx_line = fragp->fr_line;
18548 buf = write_compressed_insn (buf, insn, 4);
18550 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18551 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
18552 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
18554 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18555 fragp->fr_symbol, fragp->fr_offset,
18556 FALSE, BFD_RELOC_MICROMIPS_LO16);
18557 fixp->fx_file = fragp->fr_file;
18558 fixp->fx_line = fragp->fr_line;
18560 buf = write_compressed_insn (buf, insn, 4);
18565 insn = 0x00000f3c | (al ? RA : ZERO) << MICROMIPSOP_SH_RT;
18566 insn |= at << MICROMIPSOP_SH_RS;
18568 buf = write_compressed_insn (buf, insn, 4);
18570 if (compact || nods)
18572 buf = write_compressed_insn (buf, 0x00000000, 4);
18576 /* jr/jrc/jalr/jalrs $at */
18577 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
18578 unsigned long jr = compact || nods ? 0x45a0 : 0x4580; /* jr/c */
18580 insn = al ? jalr : jr;
18581 insn |= at << MICROMIPSOP_SH_MJ;
18583 buf = write_compressed_insn (buf, insn, 2);
18588 buf = write_compressed_insn (buf, 0x0c00, 2);
18590 buf = write_compressed_insn (buf, 0x00000000, 4);
18595 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18599 if (RELAX_MIPS16_P (fragp->fr_subtype))
18602 const struct mips_int_operand *operand;
18605 unsigned int user_length;
18606 bfd_boolean need_reloc;
18607 unsigned long insn;
18612 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
18613 operand = mips16_immed_operand (type, FALSE);
18615 mac = RELAX_MIPS16_MACRO (fragp->fr_subtype);
18616 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
18617 val = resolve_symbol_value (fragp->fr_symbol) + fragp->fr_offset;
18619 symsec = S_GET_SEGMENT (fragp->fr_symbol);
18620 need_reloc = (S_FORCE_RELOC (fragp->fr_symbol, TRUE)
18621 || (operand->root.type == OP_PCREL && !mac
18623 : !bfd_is_abs_section (symsec)));
18625 if (operand->root.type == OP_PCREL && !mac)
18627 const struct mips_pcrel_operand *pcrel_op;
18629 pcrel_op = (const struct mips_pcrel_operand *) operand;
18631 if (pcrel_op->include_isa_bit && !need_reloc)
18633 if (!mips_ignore_branch_isa
18634 && !ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp->fr_symbol)))
18635 as_bad_where (fragp->fr_file, fragp->fr_line,
18636 _("branch to a symbol in another ISA mode"));
18637 else if ((fragp->fr_offset & 0x1) != 0)
18638 as_bad_where (fragp->fr_file, fragp->fr_line,
18639 _("branch to misaligned address (0x%lx)"),
18643 val = mips16_pcrel_val (fragp, pcrel_op, val, 0);
18645 /* Make sure the section winds up with the alignment we have
18647 if (operand->shift > 0)
18648 record_alignment (asec, operand->shift);
18651 if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
18652 || RELAX_MIPS16_DSLOT (fragp->fr_subtype))
18655 as_warn_where (fragp->fr_file, fragp->fr_line,
18656 _("macro instruction expanded into multiple "
18657 "instructions in a branch delay slot"));
18659 as_warn_where (fragp->fr_file, fragp->fr_line,
18660 _("extended instruction in a branch delay slot"));
18662 else if (RELAX_MIPS16_NOMACRO (fragp->fr_subtype) && mac)
18663 as_warn_where (fragp->fr_file, fragp->fr_line,
18664 _("macro instruction expanded into multiple "
18667 buf = fragp->fr_literal + fragp->fr_fix;
18669 insn = read_compressed_insn (buf, 2);
18671 insn |= MIPS16_EXTEND;
18673 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
18675 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
18687 gas_assert (type == 'A' || type == 'B' || type == 'E');
18688 gas_assert (RELAX_MIPS16_SYM32 (fragp->fr_subtype));
18690 e2 = RELAX_MIPS16_E2 (fragp->fr_subtype);
18696 gas_assert (!RELAX_MIPS16_PIC (fragp->fr_subtype));
18698 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18699 fragp->fr_symbol, fragp->fr_offset,
18700 FALSE, BFD_RELOC_MIPS16_HI16_S);
18701 fixp->fx_file = fragp->fr_file;
18702 fixp->fx_line = fragp->fr_line;
18704 fixp = fix_new (fragp, buf - fragp->fr_literal + (e2 ? 4 : 8), 4,
18705 fragp->fr_symbol, fragp->fr_offset,
18706 FALSE, BFD_RELOC_MIPS16_LO16);
18707 fixp->fx_file = fragp->fr_file;
18708 fixp->fx_line = fragp->fr_line;
18713 switch (insn & 0xf800)
18715 case 0x0800: /* ADDIU */
18716 reg = (insn >> 8) & 0x7;
18717 op = 0xf0004800 | (reg << 8);
18719 case 0xb000: /* LW */
18720 reg = (insn >> 8) & 0x7;
18721 op = 0xf0009800 | (reg << 8) | (reg << 5);
18723 case 0xf800: /* I64 */
18724 reg = (insn >> 5) & 0x7;
18725 switch (insn & 0x0700)
18727 case 0x0400: /* LD */
18728 op = 0xf0003800 | (reg << 8) | (reg << 5);
18730 case 0x0600: /* DADDIU */
18731 op = 0xf000fd00 | (reg << 5);
18741 new = (e2 ? 0xf0006820 : 0xf0006800) | (reg << 8); /* LUI/LI */
18742 new |= mips16_immed_extend ((val + 0x8000) >> 16, 16);
18743 buf = write_compressed_insn (buf, new, 4);
18746 new = 0xf4003000 | (reg << 8) | (reg << 5); /* SLL */
18747 buf = write_compressed_insn (buf, new, 4);
18749 op |= mips16_immed_extend (val, 16);
18750 buf = write_compressed_insn (buf, op, 4);
18752 fragp->fr_fix += e2 ? 8 : 12;
18756 unsigned int length = ext ? 4 : 2;
18760 bfd_reloc_code_real_type reloc = BFD_RELOC_NONE;
18767 reloc = BFD_RELOC_MIPS16_16_PCREL_S1;
18772 if (mac || reloc == BFD_RELOC_NONE)
18773 as_bad_where (fragp->fr_file, fragp->fr_line,
18774 _("unsupported relocation"));
18777 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18778 fragp->fr_symbol, fragp->fr_offset,
18780 fixp->fx_file = fragp->fr_file;
18781 fixp->fx_line = fragp->fr_line;
18784 as_bad_where (fragp->fr_file, fragp->fr_line,
18785 _("invalid unextended operand value"));
18788 mips16_immed (fragp->fr_file, fragp->fr_line, type,
18789 BFD_RELOC_UNUSED, val, user_length, &insn);
18791 gas_assert (mips16_opcode_length (insn) == length);
18792 write_compressed_insn (buf, insn, length);
18793 fragp->fr_fix += length;
18798 relax_substateT subtype = fragp->fr_subtype;
18799 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
18800 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
18804 first = RELAX_FIRST (subtype);
18805 second = RELAX_SECOND (subtype);
18806 fixp = (fixS *) fragp->fr_opcode;
18808 /* If the delay slot chosen does not match the size of the instruction,
18809 then emit a warning. */
18810 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
18811 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
18816 s = subtype & (RELAX_DELAY_SLOT_16BIT
18817 | RELAX_DELAY_SLOT_SIZE_FIRST
18818 | RELAX_DELAY_SLOT_SIZE_SECOND);
18819 msg = macro_warning (s);
18821 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18825 /* Possibly emit a warning if we've chosen the longer option. */
18826 if (use_second == second_longer)
18832 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
18833 msg = macro_warning (s);
18835 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18839 /* Go through all the fixups for the first sequence. Disable them
18840 (by marking them as done) if we're going to use the second
18841 sequence instead. */
18843 && fixp->fx_frag == fragp
18844 && fixp->fx_where < fragp->fr_fix - second)
18846 if (subtype & RELAX_USE_SECOND)
18848 fixp = fixp->fx_next;
18851 /* Go through the fixups for the second sequence. Disable them if
18852 we're going to use the first sequence, otherwise adjust their
18853 addresses to account for the relaxation. */
18854 while (fixp && fixp->fx_frag == fragp)
18856 if (subtype & RELAX_USE_SECOND)
18857 fixp->fx_where -= first;
18860 fixp = fixp->fx_next;
18863 /* Now modify the frag contents. */
18864 if (subtype & RELAX_USE_SECOND)
18868 start = fragp->fr_literal + fragp->fr_fix - first - second;
18869 memmove (start, start + first, second);
18870 fragp->fr_fix -= first;
18873 fragp->fr_fix -= second;
18877 /* This function is called after the relocs have been generated.
18878 We've been storing mips16 text labels as odd. Here we convert them
18879 back to even for the convenience of the debugger. */
18882 mips_frob_file_after_relocs (void)
18885 unsigned int count, i;
18887 syms = bfd_get_outsymbols (stdoutput);
18888 count = bfd_get_symcount (stdoutput);
18889 for (i = 0; i < count; i++, syms++)
18890 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
18891 && ((*syms)->value & 1) != 0)
18893 (*syms)->value &= ~1;
18894 /* If the symbol has an odd size, it was probably computed
18895 incorrectly, so adjust that as well. */
18896 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
18897 ++elf_symbol (*syms)->internal_elf_sym.st_size;
18901 /* This function is called whenever a label is defined, including fake
18902 labels instantiated off the dot special symbol. It is used when
18903 handling branch delays; if a branch has a label, we assume we cannot
18904 move it. This also bumps the value of the symbol by 1 in compressed
18908 mips_record_label (symbolS *sym)
18910 segment_info_type *si = seg_info (now_seg);
18911 struct insn_label_list *l;
18913 if (free_insn_labels == NULL)
18914 l = XNEW (struct insn_label_list);
18917 l = free_insn_labels;
18918 free_insn_labels = l->next;
18922 l->next = si->label_list;
18923 si->label_list = l;
18926 /* This function is called as tc_frob_label() whenever a label is defined
18927 and adds a DWARF-2 record we only want for true labels. */
18930 mips_define_label (symbolS *sym)
18932 mips_record_label (sym);
18933 dwarf2_emit_label (sym);
18936 /* This function is called by tc_new_dot_label whenever a new dot symbol
18940 mips_add_dot_label (symbolS *sym)
18942 mips_record_label (sym);
18943 if (mips_assembling_insn && HAVE_CODE_COMPRESSION)
18944 mips_compressed_mark_label (sym);
18947 /* Converting ASE flags from internal to .MIPS.abiflags values. */
18948 static unsigned int
18949 mips_convert_ase_flags (int ase)
18951 unsigned int ext_ases = 0;
18954 ext_ases |= AFL_ASE_DSP;
18955 if (ase & ASE_DSPR2)
18956 ext_ases |= AFL_ASE_DSPR2;
18957 if (ase & ASE_DSPR3)
18958 ext_ases |= AFL_ASE_DSPR3;
18960 ext_ases |= AFL_ASE_EVA;
18962 ext_ases |= AFL_ASE_MCU;
18963 if (ase & ASE_MDMX)
18964 ext_ases |= AFL_ASE_MDMX;
18965 if (ase & ASE_MIPS3D)
18966 ext_ases |= AFL_ASE_MIPS3D;
18968 ext_ases |= AFL_ASE_MT;
18969 if (ase & ASE_SMARTMIPS)
18970 ext_ases |= AFL_ASE_SMARTMIPS;
18971 if (ase & ASE_VIRT)
18972 ext_ases |= AFL_ASE_VIRT;
18974 ext_ases |= AFL_ASE_MSA;
18976 ext_ases |= AFL_ASE_XPA;
18977 if (ase & ASE_MIPS16E2)
18978 ext_ases |= file_ase_mips16 ? AFL_ASE_MIPS16E2 : 0;
18982 /* Some special processing for a MIPS ELF file. */
18985 mips_elf_final_processing (void)
18988 Elf_Internal_ABIFlags_v0 flags;
18992 switch (file_mips_opts.isa)
18995 flags.isa_level = 1;
18998 flags.isa_level = 2;
19001 flags.isa_level = 3;
19004 flags.isa_level = 4;
19007 flags.isa_level = 5;
19010 flags.isa_level = 32;
19014 flags.isa_level = 32;
19018 flags.isa_level = 32;
19022 flags.isa_level = 32;
19026 flags.isa_level = 32;
19030 flags.isa_level = 64;
19034 flags.isa_level = 64;
19038 flags.isa_level = 64;
19042 flags.isa_level = 64;
19046 flags.isa_level = 64;
19051 flags.gpr_size = file_mips_opts.gp == 32 ? AFL_REG_32 : AFL_REG_64;
19052 flags.cpr1_size = file_mips_opts.soft_float ? AFL_REG_NONE
19053 : (file_mips_opts.ase & ASE_MSA) ? AFL_REG_128
19054 : (file_mips_opts.fp == 64) ? AFL_REG_64
19056 flags.cpr2_size = AFL_REG_NONE;
19057 flags.fp_abi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
19058 Tag_GNU_MIPS_ABI_FP);
19059 flags.isa_ext = bfd_mips_isa_ext (stdoutput);
19060 flags.ases = mips_convert_ase_flags (file_mips_opts.ase);
19061 if (file_ase_mips16)
19062 flags.ases |= AFL_ASE_MIPS16;
19063 if (file_ase_micromips)
19064 flags.ases |= AFL_ASE_MICROMIPS;
19066 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts.isa, file_mips_opts.arch)
19067 || file_mips_opts.fp == 64)
19068 && file_mips_opts.oddspreg)
19069 flags.flags1 |= AFL_FLAGS1_ODDSPREG;
19072 bfd_mips_elf_swap_abiflags_v0_out (stdoutput, &flags,
19073 ((Elf_External_ABIFlags_v0 *)
19076 /* Write out the register information. */
19077 if (mips_abi != N64_ABI)
19081 s.ri_gprmask = mips_gprmask;
19082 s.ri_cprmask[0] = mips_cprmask[0];
19083 s.ri_cprmask[1] = mips_cprmask[1];
19084 s.ri_cprmask[2] = mips_cprmask[2];
19085 s.ri_cprmask[3] = mips_cprmask[3];
19086 /* The gp_value field is set by the MIPS ELF backend. */
19088 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
19089 ((Elf32_External_RegInfo *)
19090 mips_regmask_frag));
19094 Elf64_Internal_RegInfo s;
19096 s.ri_gprmask = mips_gprmask;
19098 s.ri_cprmask[0] = mips_cprmask[0];
19099 s.ri_cprmask[1] = mips_cprmask[1];
19100 s.ri_cprmask[2] = mips_cprmask[2];
19101 s.ri_cprmask[3] = mips_cprmask[3];
19102 /* The gp_value field is set by the MIPS ELF backend. */
19104 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
19105 ((Elf64_External_RegInfo *)
19106 mips_regmask_frag));
19109 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
19110 sort of BFD interface for this. */
19111 if (mips_any_noreorder)
19112 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
19113 if (mips_pic != NO_PIC)
19115 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
19116 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
19119 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
19121 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
19122 defined at present; this might need to change in future. */
19123 if (file_ase_mips16)
19124 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
19125 if (file_ase_micromips)
19126 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
19127 if (file_mips_opts.ase & ASE_MDMX)
19128 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
19130 /* Set the MIPS ELF ABI flags. */
19131 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
19132 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
19133 else if (mips_abi == O64_ABI)
19134 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
19135 else if (mips_abi == EABI_ABI)
19137 if (file_mips_opts.gp == 64)
19138 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
19140 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
19143 /* Nothing to do for N32_ABI or N64_ABI. */
19145 if (mips_32bitmode)
19146 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
19148 if (mips_nan2008 == 1)
19149 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008;
19151 /* 32 bit code with 64 bit FP registers. */
19152 fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
19153 Tag_GNU_MIPS_ABI_FP);
19154 if (fpabi == Val_GNU_MIPS_ABI_FP_OLD_64)
19155 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_FP64;
19158 typedef struct proc {
19160 symbolS *func_end_sym;
19161 unsigned long reg_mask;
19162 unsigned long reg_offset;
19163 unsigned long fpreg_mask;
19164 unsigned long fpreg_offset;
19165 unsigned long frame_offset;
19166 unsigned long frame_reg;
19167 unsigned long pc_reg;
19170 static procS cur_proc;
19171 static procS *cur_proc_ptr;
19172 static int numprocs;
19174 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
19175 as "2", and a normal nop as "0". */
19177 #define NOP_OPCODE_MIPS 0
19178 #define NOP_OPCODE_MIPS16 1
19179 #define NOP_OPCODE_MICROMIPS 2
19182 mips_nop_opcode (void)
19184 if (seg_info (now_seg)->tc_segment_info_data.micromips)
19185 return NOP_OPCODE_MICROMIPS;
19186 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
19187 return NOP_OPCODE_MIPS16;
19189 return NOP_OPCODE_MIPS;
19192 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
19193 32-bit microMIPS NOPs here (if applicable). */
19196 mips_handle_align (fragS *fragp)
19200 int bytes, size, excess;
19203 if (fragp->fr_type != rs_align_code)
19206 p = fragp->fr_literal + fragp->fr_fix;
19208 switch (nop_opcode)
19210 case NOP_OPCODE_MICROMIPS:
19211 opcode = micromips_nop32_insn.insn_opcode;
19214 case NOP_OPCODE_MIPS16:
19215 opcode = mips16_nop_insn.insn_opcode;
19218 case NOP_OPCODE_MIPS:
19220 opcode = nop_insn.insn_opcode;
19225 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
19226 excess = bytes % size;
19228 /* Handle the leading part if we're not inserting a whole number of
19229 instructions, and make it the end of the fixed part of the frag.
19230 Try to fit in a short microMIPS NOP if applicable and possible,
19231 and use zeroes otherwise. */
19232 gas_assert (excess < 4);
19233 fragp->fr_fix += excess;
19238 /* Fall through. */
19240 if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32)
19242 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2);
19246 /* Fall through. */
19249 /* Fall through. */
19254 md_number_to_chars (p, opcode, size);
19255 fragp->fr_var = size;
19264 if (*input_line_pointer == '-')
19266 ++input_line_pointer;
19269 if (!ISDIGIT (*input_line_pointer))
19270 as_bad (_("expected simple number"));
19271 if (input_line_pointer[0] == '0')
19273 if (input_line_pointer[1] == 'x')
19275 input_line_pointer += 2;
19276 while (ISXDIGIT (*input_line_pointer))
19279 val |= hex_value (*input_line_pointer++);
19281 return negative ? -val : val;
19285 ++input_line_pointer;
19286 while (ISDIGIT (*input_line_pointer))
19289 val |= *input_line_pointer++ - '0';
19291 return negative ? -val : val;
19294 if (!ISDIGIT (*input_line_pointer))
19296 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
19297 *input_line_pointer, *input_line_pointer);
19298 as_warn (_("invalid number"));
19301 while (ISDIGIT (*input_line_pointer))
19304 val += *input_line_pointer++ - '0';
19306 return negative ? -val : val;
19309 /* The .file directive; just like the usual .file directive, but there
19310 is an initial number which is the ECOFF file index. In the non-ECOFF
19311 case .file implies DWARF-2. */
19314 s_mips_file (int x ATTRIBUTE_UNUSED)
19316 static int first_file_directive = 0;
19318 if (ECOFF_DEBUGGING)
19327 filename = dwarf2_directive_file (0);
19329 /* Versions of GCC up to 3.1 start files with a ".file"
19330 directive even for stabs output. Make sure that this
19331 ".file" is handled. Note that you need a version of GCC
19332 after 3.1 in order to support DWARF-2 on MIPS. */
19333 if (filename != NULL && ! first_file_directive)
19335 (void) new_logical_line (filename, -1);
19336 s_app_file_string (filename, 0);
19338 first_file_directive = 1;
19342 /* The .loc directive, implying DWARF-2. */
19345 s_mips_loc (int x ATTRIBUTE_UNUSED)
19347 if (!ECOFF_DEBUGGING)
19348 dwarf2_directive_loc (0);
19351 /* The .end directive. */
19354 s_mips_end (int x ATTRIBUTE_UNUSED)
19358 /* Following functions need their own .frame and .cprestore directives. */
19359 mips_frame_reg_valid = 0;
19360 mips_cprestore_valid = 0;
19362 if (!is_end_of_line[(unsigned char) *input_line_pointer])
19365 demand_empty_rest_of_line ();
19370 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
19371 as_warn (_(".end not in text section"));
19375 as_warn (_(".end directive without a preceding .ent directive"));
19376 demand_empty_rest_of_line ();
19382 gas_assert (S_GET_NAME (p));
19383 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
19384 as_warn (_(".end symbol does not match .ent symbol"));
19386 if (debug_type == DEBUG_STABS)
19387 stabs_generate_asm_endfunc (S_GET_NAME (p),
19391 as_warn (_(".end directive missing or unknown symbol"));
19393 /* Create an expression to calculate the size of the function. */
19394 if (p && cur_proc_ptr)
19396 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
19397 expressionS *exp = XNEW (expressionS);
19400 exp->X_op = O_subtract;
19401 exp->X_add_symbol = symbol_temp_new_now ();
19402 exp->X_op_symbol = p;
19403 exp->X_add_number = 0;
19405 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
19408 #ifdef md_flush_pending_output
19409 md_flush_pending_output ();
19412 /* Generate a .pdr section. */
19413 if (!ECOFF_DEBUGGING && mips_flag_pdr)
19415 segT saved_seg = now_seg;
19416 subsegT saved_subseg = now_subseg;
19420 gas_assert (pdr_seg);
19421 subseg_set (pdr_seg, 0);
19423 /* Write the symbol. */
19424 exp.X_op = O_symbol;
19425 exp.X_add_symbol = p;
19426 exp.X_add_number = 0;
19427 emit_expr (&exp, 4);
19429 fragp = frag_more (7 * 4);
19431 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
19432 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
19433 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
19434 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
19435 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
19436 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
19437 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
19439 subseg_set (saved_seg, saved_subseg);
19442 cur_proc_ptr = NULL;
19445 /* The .aent and .ent directives. */
19448 s_mips_ent (int aent)
19452 symbolP = get_symbol ();
19453 if (*input_line_pointer == ',')
19454 ++input_line_pointer;
19455 SKIP_WHITESPACE ();
19456 if (ISDIGIT (*input_line_pointer)
19457 || *input_line_pointer == '-')
19460 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
19461 as_warn (_(".ent or .aent not in text section"));
19463 if (!aent && cur_proc_ptr)
19464 as_warn (_("missing .end"));
19468 /* This function needs its own .frame and .cprestore directives. */
19469 mips_frame_reg_valid = 0;
19470 mips_cprestore_valid = 0;
19472 cur_proc_ptr = &cur_proc;
19473 memset (cur_proc_ptr, '\0', sizeof (procS));
19475 cur_proc_ptr->func_sym = symbolP;
19479 if (debug_type == DEBUG_STABS)
19480 stabs_generate_asm_func (S_GET_NAME (symbolP),
19481 S_GET_NAME (symbolP));
19484 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
19486 demand_empty_rest_of_line ();
19489 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19490 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19491 s_mips_frame is used so that we can set the PDR information correctly.
19492 We can't use the ecoff routines because they make reference to the ecoff
19493 symbol table (in the mdebug section). */
19496 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
19498 if (ECOFF_DEBUGGING)
19504 if (cur_proc_ptr == (procS *) NULL)
19506 as_warn (_(".frame outside of .ent"));
19507 demand_empty_rest_of_line ();
19511 cur_proc_ptr->frame_reg = tc_get_register (1);
19513 SKIP_WHITESPACE ();
19514 if (*input_line_pointer++ != ','
19515 || get_absolute_expression_and_terminator (&val) != ',')
19517 as_warn (_("bad .frame directive"));
19518 --input_line_pointer;
19519 demand_empty_rest_of_line ();
19523 cur_proc_ptr->frame_offset = val;
19524 cur_proc_ptr->pc_reg = tc_get_register (0);
19526 demand_empty_rest_of_line ();
19530 /* The .fmask and .mask directives. If the mdebug section is present
19531 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19532 embedded targets, s_mips_mask is used so that we can set the PDR
19533 information correctly. We can't use the ecoff routines because they
19534 make reference to the ecoff symbol table (in the mdebug section). */
19537 s_mips_mask (int reg_type)
19539 if (ECOFF_DEBUGGING)
19540 s_ignore (reg_type);
19545 if (cur_proc_ptr == (procS *) NULL)
19547 as_warn (_(".mask/.fmask outside of .ent"));
19548 demand_empty_rest_of_line ();
19552 if (get_absolute_expression_and_terminator (&mask) != ',')
19554 as_warn (_("bad .mask/.fmask directive"));
19555 --input_line_pointer;
19556 demand_empty_rest_of_line ();
19560 off = get_absolute_expression ();
19562 if (reg_type == 'F')
19564 cur_proc_ptr->fpreg_mask = mask;
19565 cur_proc_ptr->fpreg_offset = off;
19569 cur_proc_ptr->reg_mask = mask;
19570 cur_proc_ptr->reg_offset = off;
19573 demand_empty_rest_of_line ();
19577 /* A table describing all the processors gas knows about. Names are
19578 matched in the order listed.
19580 To ease comparison, please keep this table in the same order as
19581 gcc's mips_cpu_info_table[]. */
19582 static const struct mips_cpu_info mips_cpu_info_table[] =
19584 /* Entries for generic ISAs */
19585 { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 },
19586 { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 },
19587 { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 },
19588 { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 },
19589 { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 },
19590 { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 },
19591 { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19592 { "mips32r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R3, CPU_MIPS32R3 },
19593 { "mips32r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R5, CPU_MIPS32R5 },
19594 { "mips32r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R6, CPU_MIPS32R6 },
19595 { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 },
19596 { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 },
19597 { "mips64r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R3, CPU_MIPS64R3 },
19598 { "mips64r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R5, CPU_MIPS64R5 },
19599 { "mips64r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R6, CPU_MIPS64R6 },
19602 { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 },
19603 { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 },
19604 { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 },
19607 { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 },
19610 { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 },
19611 { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 },
19612 { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 },
19613 { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 },
19614 { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 },
19615 { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 },
19616 { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 },
19617 { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 },
19618 { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 },
19619 { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 },
19620 { "orion", 0, 0, ISA_MIPS3, CPU_R4600 },
19621 { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 },
19622 { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 },
19623 /* ST Microelectronics Loongson 2E and 2F cores */
19624 { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E },
19625 { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F },
19628 { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 },
19629 { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 },
19630 { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 },
19631 { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 },
19632 { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 },
19633 { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 },
19634 { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 },
19635 { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 },
19636 { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 },
19637 { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 },
19638 { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 },
19639 { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 },
19640 { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 },
19641 { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 },
19642 { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 },
19645 { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19646 { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19647 { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19648 { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
19650 /* MIPS 32 Release 2 */
19651 { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19652 { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19653 { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19654 { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
19655 { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19656 { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19657 { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19658 { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19659 { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
19660 ISA_MIPS32R2, CPU_MIPS32R2 },
19661 { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
19662 ISA_MIPS32R2, CPU_MIPS32R2 },
19663 { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19664 { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19665 { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19666 { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19667 /* Deprecated forms of the above. */
19668 { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19669 { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19670 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19671 { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19672 { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19673 { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19674 { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19675 /* Deprecated forms of the above. */
19676 { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19677 { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19678 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19679 { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19680 { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19681 { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19682 { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19683 /* Deprecated forms of the above. */
19684 { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19685 { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19686 /* 34Kn is a 34kc without DSP. */
19687 { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19688 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19689 { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19690 { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19691 { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19692 { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19693 { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19694 /* Deprecated forms of the above. */
19695 { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19696 { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19697 /* 1004K cores are multiprocessor versions of the 34K. */
19698 { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19699 { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19700 { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19701 { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19702 /* interaptiv is the new name for 1004kf */
19703 { "interaptiv", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19704 { "interaptiv-mr2", 0,
19705 ASE_DSP | ASE_EVA | ASE_MT | ASE_MIPS16E2 | ASE_MIPS16E2_MT,
19706 ISA_MIPS32R3, CPU_INTERAPTIV_MR2 },
19708 { "m5100", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 },
19709 { "m5101", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 },
19710 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
19711 { "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R5, CPU_MIPS32R5 },
19714 { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 },
19715 { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 },
19716 { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19717 { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19719 /* Broadcom SB-1 CPU core */
19720 { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
19721 /* Broadcom SB-1A CPU core */
19722 { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
19724 { "loongson3a", 0, 0, ISA_MIPS64R2, CPU_LOONGSON_3A },
19726 /* MIPS 64 Release 2 */
19728 /* Cavium Networks Octeon CPU core */
19729 { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
19730 { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP },
19731 { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 },
19732 { "octeon3", 0, ASE_VIRT | ASE_VIRT64, ISA_MIPS64R5, CPU_OCTEON3 },
19735 { "xlr", 0, 0, ISA_MIPS64, CPU_XLR },
19738 XLP is mostly like XLR, with the prominent exception that it is
19739 MIPS64R2 rather than MIPS64. */
19740 { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
19742 /* MIPS 64 Release 6 */
19743 { "i6400", 0, ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6},
19744 { "p6600", 0, ASE_VIRT | ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6},
19747 { NULL, 0, 0, 0, 0 }
19751 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19752 with a final "000" replaced by "k". Ignore case.
19754 Note: this function is shared between GCC and GAS. */
19757 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
19759 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
19760 given++, canonical++;
19762 return ((*given == 0 && *canonical == 0)
19763 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
19767 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19768 CPU name. We've traditionally allowed a lot of variation here.
19770 Note: this function is shared between GCC and GAS. */
19773 mips_matching_cpu_name_p (const char *canonical, const char *given)
19775 /* First see if the name matches exactly, or with a final "000"
19776 turned into "k". */
19777 if (mips_strict_matching_cpu_name_p (canonical, given))
19780 /* If not, try comparing based on numerical designation alone.
19781 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19782 if (TOLOWER (*given) == 'r')
19784 if (!ISDIGIT (*given))
19787 /* Skip over some well-known prefixes in the canonical name,
19788 hoping to find a number there too. */
19789 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
19791 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
19793 else if (TOLOWER (canonical[0]) == 'r')
19796 return mips_strict_matching_cpu_name_p (canonical, given);
19800 /* Parse an option that takes the name of a processor as its argument.
19801 OPTION is the name of the option and CPU_STRING is the argument.
19802 Return the corresponding processor enumeration if the CPU_STRING is
19803 recognized, otherwise report an error and return null.
19805 A similar function exists in GCC. */
19807 static const struct mips_cpu_info *
19808 mips_parse_cpu (const char *option, const char *cpu_string)
19810 const struct mips_cpu_info *p;
19812 /* 'from-abi' selects the most compatible architecture for the given
19813 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19814 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19815 version. Look first at the -mgp options, if given, otherwise base
19816 the choice on MIPS_DEFAULT_64BIT.
19818 Treat NO_ABI like the EABIs. One reason to do this is that the
19819 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19820 architecture. This code picks MIPS I for 'mips' and MIPS III for
19821 'mips64', just as we did in the days before 'from-abi'. */
19822 if (strcasecmp (cpu_string, "from-abi") == 0)
19824 if (ABI_NEEDS_32BIT_REGS (mips_abi))
19825 return mips_cpu_info_from_isa (ISA_MIPS1);
19827 if (ABI_NEEDS_64BIT_REGS (mips_abi))
19828 return mips_cpu_info_from_isa (ISA_MIPS3);
19830 if (file_mips_opts.gp >= 0)
19831 return mips_cpu_info_from_isa (file_mips_opts.gp == 32
19832 ? ISA_MIPS1 : ISA_MIPS3);
19834 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19839 /* 'default' has traditionally been a no-op. Probably not very useful. */
19840 if (strcasecmp (cpu_string, "default") == 0)
19843 for (p = mips_cpu_info_table; p->name != 0; p++)
19844 if (mips_matching_cpu_name_p (p->name, cpu_string))
19847 as_bad (_("bad value (%s) for %s"), cpu_string, option);
19851 /* Return the canonical processor information for ISA (a member of the
19852 ISA_MIPS* enumeration). */
19854 static const struct mips_cpu_info *
19855 mips_cpu_info_from_isa (int isa)
19859 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19860 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
19861 && isa == mips_cpu_info_table[i].isa)
19862 return (&mips_cpu_info_table[i]);
19867 static const struct mips_cpu_info *
19868 mips_cpu_info_from_arch (int arch)
19872 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19873 if (arch == mips_cpu_info_table[i].cpu)
19874 return (&mips_cpu_info_table[i]);
19880 show (FILE *stream, const char *string, int *col_p, int *first_p)
19884 fprintf (stream, "%24s", "");
19889 fprintf (stream, ", ");
19893 if (*col_p + strlen (string) > 72)
19895 fprintf (stream, "\n%24s", "");
19899 fprintf (stream, "%s", string);
19900 *col_p += strlen (string);
19906 md_show_usage (FILE *stream)
19911 fprintf (stream, _("\
19913 -EB generate big endian output\n\
19914 -EL generate little endian output\n\
19915 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19916 -G NUM allow referencing objects up to NUM bytes\n\
19917 implicitly with the gp register [default 8]\n"));
19918 fprintf (stream, _("\
19919 -mips1 generate MIPS ISA I instructions\n\
19920 -mips2 generate MIPS ISA II instructions\n\
19921 -mips3 generate MIPS ISA III instructions\n\
19922 -mips4 generate MIPS ISA IV instructions\n\
19923 -mips5 generate MIPS ISA V instructions\n\
19924 -mips32 generate MIPS32 ISA instructions\n\
19925 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19926 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
19927 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
19928 -mips32r6 generate MIPS32 release 6 ISA instructions\n\
19929 -mips64 generate MIPS64 ISA instructions\n\
19930 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19931 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
19932 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
19933 -mips64r6 generate MIPS64 release 6 ISA instructions\n\
19934 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19938 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19939 show (stream, mips_cpu_info_table[i].name, &column, &first);
19940 show (stream, "from-abi", &column, &first);
19941 fputc ('\n', stream);
19943 fprintf (stream, _("\
19944 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19945 -no-mCPU don't generate code specific to CPU.\n\
19946 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19950 show (stream, "3900", &column, &first);
19951 show (stream, "4010", &column, &first);
19952 show (stream, "4100", &column, &first);
19953 show (stream, "4650", &column, &first);
19954 fputc ('\n', stream);
19956 fprintf (stream, _("\
19957 -mips16 generate mips16 instructions\n\
19958 -no-mips16 do not generate mips16 instructions\n"));
19959 fprintf (stream, _("\
19960 -mmips16e2 generate MIPS16e2 instructions\n\
19961 -mno-mips16e2 do not generate MIPS16e2 instructions\n"));
19962 fprintf (stream, _("\
19963 -mmicromips generate microMIPS instructions\n\
19964 -mno-micromips do not generate microMIPS instructions\n"));
19965 fprintf (stream, _("\
19966 -msmartmips generate smartmips instructions\n\
19967 -mno-smartmips do not generate smartmips instructions\n"));
19968 fprintf (stream, _("\
19969 -mdsp generate DSP instructions\n\
19970 -mno-dsp do not generate DSP instructions\n"));
19971 fprintf (stream, _("\
19972 -mdspr2 generate DSP R2 instructions\n\
19973 -mno-dspr2 do not generate DSP R2 instructions\n"));
19974 fprintf (stream, _("\
19975 -mdspr3 generate DSP R3 instructions\n\
19976 -mno-dspr3 do not generate DSP R3 instructions\n"));
19977 fprintf (stream, _("\
19978 -mmt generate MT instructions\n\
19979 -mno-mt do not generate MT instructions\n"));
19980 fprintf (stream, _("\
19981 -mmcu generate MCU instructions\n\
19982 -mno-mcu do not generate MCU instructions\n"));
19983 fprintf (stream, _("\
19984 -mmsa generate MSA instructions\n\
19985 -mno-msa do not generate MSA instructions\n"));
19986 fprintf (stream, _("\
19987 -mxpa generate eXtended Physical Address (XPA) instructions\n\
19988 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
19989 fprintf (stream, _("\
19990 -mvirt generate Virtualization instructions\n\
19991 -mno-virt do not generate Virtualization instructions\n"));
19992 fprintf (stream, _("\
19993 -minsn32 only generate 32-bit microMIPS instructions\n\
19994 -mno-insn32 generate all microMIPS instructions\n"));
19995 fprintf (stream, _("\
19996 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19997 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19998 -mfix-vr4120 work around certain VR4120 errata\n\
19999 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
20000 -mfix-24k insert a nop after ERET and DERET instructions\n\
20001 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
20002 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
20003 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
20004 -msym32 assume all symbols have 32-bit values\n\
20005 -O0 remove unneeded NOPs, do not swap branches\n\
20006 -O remove unneeded NOPs and swap branches\n\
20007 --trap, --no-break trap exception on div by 0 and mult overflow\n\
20008 --break, --no-trap break exception on div by 0 and mult overflow\n"));
20009 fprintf (stream, _("\
20010 -mhard-float allow floating-point instructions\n\
20011 -msoft-float do not allow floating-point instructions\n\
20012 -msingle-float only allow 32-bit floating-point operations\n\
20013 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
20014 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
20015 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
20016 -mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\
20017 -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\
20018 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
20022 show (stream, "legacy", &column, &first);
20023 show (stream, "2008", &column, &first);
20025 fputc ('\n', stream);
20027 fprintf (stream, _("\
20028 -KPIC, -call_shared generate SVR4 position independent code\n\
20029 -call_nonpic generate non-PIC code that can operate with DSOs\n\
20030 -mvxworks-pic generate VxWorks position independent code\n\
20031 -non_shared do not generate code that can operate with DSOs\n\
20032 -xgot assume a 32 bit GOT\n\
20033 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
20034 -mshared, -mno-shared disable/enable .cpload optimization for\n\
20035 position dependent (non shared) code\n\
20036 -mabi=ABI create ABI conformant object file for:\n"));
20040 show (stream, "32", &column, &first);
20041 show (stream, "o64", &column, &first);
20042 show (stream, "n32", &column, &first);
20043 show (stream, "64", &column, &first);
20044 show (stream, "eabi", &column, &first);
20046 fputc ('\n', stream);
20048 fprintf (stream, _("\
20049 -32 create o32 ABI object file%s\n"),
20050 MIPS_DEFAULT_ABI == O32_ABI ? _(" (default)") : "");
20051 fprintf (stream, _("\
20052 -n32 create n32 ABI object file%s\n"),
20053 MIPS_DEFAULT_ABI == N32_ABI ? _(" (default)") : "");
20054 fprintf (stream, _("\
20055 -64 create 64 ABI object file%s\n"),
20056 MIPS_DEFAULT_ABI == N64_ABI ? _(" (default)") : "");
20061 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
20063 if (HAVE_64BIT_SYMBOLS)
20064 return dwarf2_format_64bit_irix;
20066 return dwarf2_format_32bit;
20071 mips_dwarf2_addr_size (void)
20073 if (HAVE_64BIT_OBJECTS)
20079 /* Standard calling conventions leave the CFA at SP on entry. */
20081 mips_cfi_frame_initial_instructions (void)
20083 cfi_add_CFA_def_cfa_register (SP);
20087 tc_mips_regname_to_dw2regnum (char *regname)
20089 unsigned int regnum = -1;
20092 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))
20098 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
20099 Given a symbolic attribute NAME, return the proper integer value.
20100 Returns -1 if the attribute is not known. */
20103 mips_convert_symbolic_attribute (const char *name)
20105 static const struct
20110 attribute_table[] =
20112 #define T(tag) {#tag, tag}
20113 T (Tag_GNU_MIPS_ABI_FP),
20114 T (Tag_GNU_MIPS_ABI_MSA),
20122 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
20123 if (streq (name, attribute_table[i].name))
20124 return attribute_table[i].tag;
20132 int fpabi = Val_GNU_MIPS_ABI_FP_ANY;
20134 mips_emit_delays ();
20136 as_warn (_("missing .end at end of assembly"));
20138 /* Just in case no code was emitted, do the consistency check. */
20139 file_mips_check_options ();
20141 /* Set a floating-point ABI if the user did not. */
20142 if (obj_elf_seen_attribute (OBJ_ATTR_GNU, Tag_GNU_MIPS_ABI_FP))
20144 /* Perform consistency checks on the floating-point ABI. */
20145 fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
20146 Tag_GNU_MIPS_ABI_FP);
20147 if (fpabi != Val_GNU_MIPS_ABI_FP_ANY)
20148 check_fpabi (fpabi);
20152 /* Soft-float gets precedence over single-float, the two options should
20153 not be used together so this should not matter. */
20154 if (file_mips_opts.soft_float == 1)
20155 fpabi = Val_GNU_MIPS_ABI_FP_SOFT;
20156 /* Single-float gets precedence over all double_float cases. */
20157 else if (file_mips_opts.single_float == 1)
20158 fpabi = Val_GNU_MIPS_ABI_FP_SINGLE;
20161 switch (file_mips_opts.fp)
20164 if (file_mips_opts.gp == 32)
20165 fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE;
20168 fpabi = Val_GNU_MIPS_ABI_FP_XX;
20171 if (file_mips_opts.gp == 32 && !file_mips_opts.oddspreg)
20172 fpabi = Val_GNU_MIPS_ABI_FP_64A;
20173 else if (file_mips_opts.gp == 32)
20174 fpabi = Val_GNU_MIPS_ABI_FP_64;
20176 fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE;
20181 bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
20182 Tag_GNU_MIPS_ABI_FP, fpabi);
20186 /* Returns the relocation type required for a particular CFI encoding. */
20188 bfd_reloc_code_real_type
20189 mips_cfi_reloc_for_encoding (int encoding)
20191 if (encoding == (DW_EH_PE_sdata4 | DW_EH_PE_pcrel))
20192 return BFD_RELOC_32_PCREL;
20193 else return BFD_RELOC_NONE;